1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright (c) 2014-2019 Broadcom Inc.
5 * DO NOT MODIFY!!! This file is automatically generated.
8 #ifndef _HSI_STRUCT_DEF_DPDK_H_
9 #define _HSI_STRUCT_DEF_DPDK_H_
11 /* This is the HWRM command header. */
12 /* hwrm_cmd_hdr (size:128b/16B) */
14 /* The HWRM command request type. */
17 * The completion ring to send the completion event on. This should
18 * be the NQ ID returned from the `nq_alloc` HWRM command.
22 * The sequence ID is used by the driver for tracking multiple
23 * commands. This ID is treated as opaque data by the firmware and
24 * the value is returned in the `hwrm_resp_hdr` upon completion.
28 * The target ID of the command:
29 * * 0x0-0xFFF8 - The function ID
30 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
31 * * 0xFFFD - Reserved for user-space HWRM interface
36 * A physical address pointer pointing to a host buffer that the
37 * command's response data will be written. This can be either a host
38 * physical address (HPA) or a guest physical address (GPA) and must
39 * point to a physically contiguous block of memory.
42 } __attribute__((packed));
44 /* This is the HWRM response header. */
45 /* hwrm_resp_hdr (size:64b/8B) */
46 struct hwrm_resp_hdr {
47 /* The specific error status for the command. */
49 /* The HWRM command request type. */
51 /* The sequence ID from the original command. */
53 /* The length of the response data in number of bytes. */
55 } __attribute__((packed));
58 * TLV encapsulated message. Use the TLV type field of the
59 * TLV to determine the type of message encapsulated.
61 #define CMD_DISCR_TLV_ENCAP UINT32_C(0x8000)
62 #define CMD_DISCR_LAST CMD_DISCR_TLV_ENCAP
65 /* HWRM request message */
66 #define TLV_TYPE_HWRM_REQUEST UINT32_C(0x1)
67 /* HWRM response message */
68 #define TLV_TYPE_HWRM_RESPONSE UINT32_C(0x2)
69 /* RoCE slow path command */
70 #define TLV_TYPE_ROCE_SP_COMMAND UINT32_C(0x3)
71 /* RoCE slow path command to query CC Gen1 support. */
72 #define TLV_TYPE_QUERY_ROCE_CC_GEN1 UINT32_C(0x4)
73 /* RoCE slow path command to modify CC Gen1 support. */
74 #define TLV_TYPE_MODIFY_ROCE_CC_GEN1 UINT32_C(0x5)
75 /* Engine CKV - The Alias key EC curve and ECC public key information. */
76 #define TLV_TYPE_ENGINE_CKV_ALIAS_ECC_PUBLIC_KEY UINT32_C(0x8001)
77 /* Engine CKV - Initialization vector. */
78 #define TLV_TYPE_ENGINE_CKV_IV UINT32_C(0x8003)
79 /* Engine CKV - Authentication tag. */
80 #define TLV_TYPE_ENGINE_CKV_AUTH_TAG UINT32_C(0x8004)
81 /* Engine CKV - The encrypted data. */
82 #define TLV_TYPE_ENGINE_CKV_CIPHERTEXT UINT32_C(0x8005)
83 /* Engine CKV - Supported algorithms. */
84 #define TLV_TYPE_ENGINE_CKV_ALGORITHMS UINT32_C(0x8006)
85 /* Engine CKV - The Host EC curve name and ECC public key information. */
86 #define TLV_TYPE_ENGINE_CKV_HOST_ECC_PUBLIC_KEY UINT32_C(0x8007)
87 /* Engine CKV - The ECDSA signature. */
88 #define TLV_TYPE_ENGINE_CKV_ECDSA_SIGNATURE UINT32_C(0x8008)
89 /* Engine CKV - The SRT EC curve name and ECC public key information. */
90 #define TLV_TYPE_ENGINE_CKV_SRT_ECC_PUBLIC_KEY UINT32_C(0x8009)
91 #define TLV_TYPE_LAST \
92 TLV_TYPE_ENGINE_CKV_SRT_ECC_PUBLIC_KEY
95 /* tlv (size:64b/8B) */
98 * The command discriminator is used to differentiate between various
99 * types of HWRM messages. This includes legacy HWRM and RoCE slowpath
100 * command messages as well as newer TLV encapsulated HWRM commands.
102 * For TLV encapsulated messages this field must be 0x8000.
108 * Indicates the presence of additional TLV encapsulated data
111 #define TLV_FLAGS_MORE UINT32_C(0x1)
112 /* Last TLV in a sequence of TLVs. */
113 #define TLV_FLAGS_MORE_LAST UINT32_C(0x0)
114 /* More TLVs follow this TLV. */
115 #define TLV_FLAGS_MORE_NOT_LAST UINT32_C(0x1)
117 * When an HWRM receiver detects a TLV type that it does not
118 * support with the TLV required flag set, the receiver must
119 * reject the HWRM message with an error code indicating an
120 * unsupported TLV type.
122 #define TLV_FLAGS_REQUIRED UINT32_C(0x2)
124 #define TLV_FLAGS_REQUIRED_NO (UINT32_C(0x0) << 1)
126 #define TLV_FLAGS_REQUIRED_YES (UINT32_C(0x1) << 1)
127 #define TLV_FLAGS_REQUIRED_LAST TLV_FLAGS_REQUIRED_YES
129 * This field defines the TLV type value which is divided into
130 * two ranges to differentiate between global and local TLV types.
131 * Global TLV types must be unique across all defined TLV types.
132 * Local TLV types are valid only for extensions to a given
133 * HWRM message and may be repeated across different HWRM message
134 * types. There is a direct correlation of each HWRM message type
135 * to a single global TLV type value.
137 * Global TLV range: `0 - (63k-1)`
139 * Local TLV range: `63k - (64k-1)`
143 * Length of the message data encapsulated by this TLV in bytes.
144 * This length does not include the size of the TLV header itself
145 * and it must be an integer multiple of 8B.
148 } __attribute__((packed));
151 /* input (size:128b/16B) */
154 * This value indicates what type of request this is. The format
155 * for the rest of the command is determined by this field.
159 * This value indicates the what completion ring the request will
160 * be optionally completed on. If the value is -1, then no
161 * CR completion will be generated. Any other value must be a
162 * valid CR ring_id value for this function.
165 /* This value indicates the command sequence number. */
168 * Target ID of this command.
170 * 0x0 - 0xFFF8 - Used for function ids
171 * 0xFFF8 - 0xFFFE - Reserved for internal processors
176 * This is the host address where the response will be written
177 * when the request is complete. This area must be 16B aligned
178 * and must be cleared to zero before the request is made.
181 } __attribute__((packed));
184 /* output (size:64b/8B) */
187 * Pass/Fail or error type
189 * Note: receiver to verify the in parameters, and fail the call
190 * with an error when appropriate
193 /* This field returns the type of original request. */
195 /* This field provides original sequence number of the command. */
198 * This field is the length of the response in bytes. The
199 * last byte of the response is a valid flag that will read
200 * as '1' when the command has been completely written to
204 } __attribute__((packed));
206 /* Short Command Structure */
207 /* hwrm_short_input (size:128b/16B) */
208 struct hwrm_short_input {
210 * This field indicates the type of request in the request buffer.
211 * The format for the rest of the command (request) is determined
216 * This field indicates a signature that is used to identify short
217 * form of the command listed here. This field shall be set to
221 /* Signature indicating this is a short form of HWRM command */
222 #define HWRM_SHORT_INPUT_SIGNATURE_SHORT_CMD UINT32_C(0x4321)
223 #define HWRM_SHORT_INPUT_SIGNATURE_LAST \
224 HWRM_SHORT_INPUT_SIGNATURE_SHORT_CMD
225 /* The target ID of the command */
227 /* Default target_id (0x0) to maintain compatibility with old driver */
228 #define HWRM_SHORT_INPUT_TARGET_ID_DEFAULT UINT32_C(0x0)
229 /* Reserved for user-space HWRM interface */
230 #define HWRM_SHORT_INPUT_TARGET_ID_TOOLS UINT32_C(0xfffd)
231 #define HWRM_SHORT_INPUT_TARGET_ID_LAST \
232 HWRM_SHORT_INPUT_TARGET_ID_TOOLS
233 /* This value indicates the length of the request. */
236 * This is the host address where the request was written.
237 * This area must be 16B aligned.
240 } __attribute__((packed));
244 * # NOTE - definitions already in hwrm_req_type, in hwrm_types.yaml
245 * # So only structure definition is provided here.
247 /* cmd_nums (size:64b/8B) */
250 * This version of the specification defines the commands listed in
251 * the table below. The following are general implementation
252 * requirements for these commands:
254 * # All commands listed below that are marked neither
255 * reserved nor experimental shall be implemented by the HWRM.
256 * # A HWRM client compliant to this specification should not use
257 * commands outside of the list below.
258 * # A HWRM client compliant to this specification should not use
259 * command numbers marked reserved below.
260 * # A command marked experimental below may not be implemented
262 * # A command marked experimental may change in the
263 * future version of the HWRM specification.
264 * # A command not listed below may be implemented by the HWRM.
265 * The behavior of commands that are not listed below is outside
266 * the scope of this specification.
269 #define HWRM_VER_GET UINT32_C(0x0)
270 #define HWRM_ERROR_RECOVERY_QCFG UINT32_C(0xc)
271 #define HWRM_FUNC_DRV_IF_CHANGE UINT32_C(0xd)
272 #define HWRM_FUNC_BUF_UNRGTR UINT32_C(0xe)
273 #define HWRM_FUNC_VF_CFG UINT32_C(0xf)
274 /* Reserved for future use. */
275 #define HWRM_RESERVED1 UINT32_C(0x10)
276 #define HWRM_FUNC_RESET UINT32_C(0x11)
277 #define HWRM_FUNC_GETFID UINT32_C(0x12)
278 #define HWRM_FUNC_VF_ALLOC UINT32_C(0x13)
279 #define HWRM_FUNC_VF_FREE UINT32_C(0x14)
280 #define HWRM_FUNC_QCAPS UINT32_C(0x15)
281 #define HWRM_FUNC_QCFG UINT32_C(0x16)
282 #define HWRM_FUNC_CFG UINT32_C(0x17)
283 #define HWRM_FUNC_QSTATS UINT32_C(0x18)
284 #define HWRM_FUNC_CLR_STATS UINT32_C(0x19)
285 #define HWRM_FUNC_DRV_UNRGTR UINT32_C(0x1a)
286 #define HWRM_FUNC_VF_RESC_FREE UINT32_C(0x1b)
287 #define HWRM_FUNC_VF_VNIC_IDS_QUERY UINT32_C(0x1c)
288 #define HWRM_FUNC_DRV_RGTR UINT32_C(0x1d)
289 #define HWRM_FUNC_DRV_QVER UINT32_C(0x1e)
290 #define HWRM_FUNC_BUF_RGTR UINT32_C(0x1f)
291 #define HWRM_PORT_PHY_CFG UINT32_C(0x20)
292 #define HWRM_PORT_MAC_CFG UINT32_C(0x21)
294 #define HWRM_PORT_TS_QUERY UINT32_C(0x22)
295 #define HWRM_PORT_QSTATS UINT32_C(0x23)
296 #define HWRM_PORT_LPBK_QSTATS UINT32_C(0x24)
298 #define HWRM_PORT_CLR_STATS UINT32_C(0x25)
300 #define HWRM_PORT_LPBK_CLR_STATS UINT32_C(0x26)
301 #define HWRM_PORT_PHY_QCFG UINT32_C(0x27)
302 #define HWRM_PORT_MAC_QCFG UINT32_C(0x28)
304 #define HWRM_PORT_MAC_PTP_QCFG UINT32_C(0x29)
305 #define HWRM_PORT_PHY_QCAPS UINT32_C(0x2a)
306 #define HWRM_PORT_PHY_I2C_WRITE UINT32_C(0x2b)
307 #define HWRM_PORT_PHY_I2C_READ UINT32_C(0x2c)
308 #define HWRM_PORT_LED_CFG UINT32_C(0x2d)
309 #define HWRM_PORT_LED_QCFG UINT32_C(0x2e)
310 #define HWRM_PORT_LED_QCAPS UINT32_C(0x2f)
311 #define HWRM_QUEUE_QPORTCFG UINT32_C(0x30)
312 #define HWRM_QUEUE_QCFG UINT32_C(0x31)
313 #define HWRM_QUEUE_CFG UINT32_C(0x32)
314 #define HWRM_FUNC_VLAN_CFG UINT32_C(0x33)
315 #define HWRM_FUNC_VLAN_QCFG UINT32_C(0x34)
316 #define HWRM_QUEUE_PFCENABLE_QCFG UINT32_C(0x35)
317 #define HWRM_QUEUE_PFCENABLE_CFG UINT32_C(0x36)
318 #define HWRM_QUEUE_PRI2COS_QCFG UINT32_C(0x37)
319 #define HWRM_QUEUE_PRI2COS_CFG UINT32_C(0x38)
320 #define HWRM_QUEUE_COS2BW_QCFG UINT32_C(0x39)
321 #define HWRM_QUEUE_COS2BW_CFG UINT32_C(0x3a)
323 #define HWRM_QUEUE_DSCP_QCAPS UINT32_C(0x3b)
325 #define HWRM_QUEUE_DSCP2PRI_QCFG UINT32_C(0x3c)
327 #define HWRM_QUEUE_DSCP2PRI_CFG UINT32_C(0x3d)
328 #define HWRM_VNIC_ALLOC UINT32_C(0x40)
329 #define HWRM_VNIC_FREE UINT32_C(0x41)
330 #define HWRM_VNIC_CFG UINT32_C(0x42)
331 #define HWRM_VNIC_QCFG UINT32_C(0x43)
332 #define HWRM_VNIC_TPA_CFG UINT32_C(0x44)
334 #define HWRM_VNIC_TPA_QCFG UINT32_C(0x45)
335 #define HWRM_VNIC_RSS_CFG UINT32_C(0x46)
336 #define HWRM_VNIC_RSS_QCFG UINT32_C(0x47)
337 #define HWRM_VNIC_PLCMODES_CFG UINT32_C(0x48)
338 #define HWRM_VNIC_PLCMODES_QCFG UINT32_C(0x49)
339 #define HWRM_VNIC_QCAPS UINT32_C(0x4a)
340 #define HWRM_RING_ALLOC UINT32_C(0x50)
341 #define HWRM_RING_FREE UINT32_C(0x51)
342 #define HWRM_RING_CMPL_RING_QAGGINT_PARAMS UINT32_C(0x52)
343 #define HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS UINT32_C(0x53)
344 #define HWRM_RING_AGGINT_QCAPS UINT32_C(0x54)
345 #define HWRM_RING_RESET UINT32_C(0x5e)
346 #define HWRM_RING_GRP_ALLOC UINT32_C(0x60)
347 #define HWRM_RING_GRP_FREE UINT32_C(0x61)
348 /* Reserved for future use. */
349 #define HWRM_RESERVED5 UINT32_C(0x64)
350 /* Reserved for future use. */
351 #define HWRM_RESERVED6 UINT32_C(0x65)
352 #define HWRM_VNIC_RSS_COS_LB_CTX_ALLOC UINT32_C(0x70)
353 #define HWRM_VNIC_RSS_COS_LB_CTX_FREE UINT32_C(0x71)
354 #define HWRM_CFA_L2_FILTER_ALLOC UINT32_C(0x90)
355 #define HWRM_CFA_L2_FILTER_FREE UINT32_C(0x91)
356 #define HWRM_CFA_L2_FILTER_CFG UINT32_C(0x92)
357 #define HWRM_CFA_L2_SET_RX_MASK UINT32_C(0x93)
358 #define HWRM_CFA_VLAN_ANTISPOOF_CFG UINT32_C(0x94)
359 #define HWRM_CFA_TUNNEL_FILTER_ALLOC UINT32_C(0x95)
360 #define HWRM_CFA_TUNNEL_FILTER_FREE UINT32_C(0x96)
362 #define HWRM_CFA_ENCAP_RECORD_ALLOC UINT32_C(0x97)
364 #define HWRM_CFA_ENCAP_RECORD_FREE UINT32_C(0x98)
365 #define HWRM_CFA_NTUPLE_FILTER_ALLOC UINT32_C(0x99)
366 #define HWRM_CFA_NTUPLE_FILTER_FREE UINT32_C(0x9a)
367 #define HWRM_CFA_NTUPLE_FILTER_CFG UINT32_C(0x9b)
369 #define HWRM_CFA_EM_FLOW_ALLOC UINT32_C(0x9c)
371 #define HWRM_CFA_EM_FLOW_FREE UINT32_C(0x9d)
373 #define HWRM_CFA_EM_FLOW_CFG UINT32_C(0x9e)
374 #define HWRM_TUNNEL_DST_PORT_QUERY UINT32_C(0xa0)
375 #define HWRM_TUNNEL_DST_PORT_ALLOC UINT32_C(0xa1)
376 #define HWRM_TUNNEL_DST_PORT_FREE UINT32_C(0xa2)
377 #define HWRM_STAT_CTX_ENG_QUERY UINT32_C(0xaf)
378 #define HWRM_STAT_CTX_ALLOC UINT32_C(0xb0)
379 #define HWRM_STAT_CTX_FREE UINT32_C(0xb1)
380 #define HWRM_STAT_CTX_QUERY UINT32_C(0xb2)
381 #define HWRM_STAT_CTX_CLR_STATS UINT32_C(0xb3)
382 #define HWRM_PORT_QSTATS_EXT UINT32_C(0xb4)
383 #define HWRM_PORT_PHY_MDIO_WRITE UINT32_C(0xb5)
384 #define HWRM_PORT_PHY_MDIO_READ UINT32_C(0xb6)
385 #define HWRM_FW_RESET UINT32_C(0xc0)
386 #define HWRM_FW_QSTATUS UINT32_C(0xc1)
387 #define HWRM_FW_HEALTH_CHECK UINT32_C(0xc2)
388 #define HWRM_FW_SYNC UINT32_C(0xc3)
389 #define HWRM_FW_STATE_BUFFER_QCAPS UINT32_C(0xc4)
390 #define HWRM_FW_STATE_QUIESCE UINT32_C(0xc5)
391 #define HWRM_FW_STATE_BACKUP UINT32_C(0xc6)
392 #define HWRM_FW_STATE_RESTORE UINT32_C(0xc7)
394 #define HWRM_FW_SET_TIME UINT32_C(0xc8)
396 #define HWRM_FW_GET_TIME UINT32_C(0xc9)
398 #define HWRM_FW_SET_STRUCTURED_DATA UINT32_C(0xca)
400 #define HWRM_FW_GET_STRUCTURED_DATA UINT32_C(0xcb)
402 #define HWRM_FW_IPC_MAILBOX UINT32_C(0xcc)
403 #define HWRM_EXEC_FWD_RESP UINT32_C(0xd0)
404 #define HWRM_REJECT_FWD_RESP UINT32_C(0xd1)
405 #define HWRM_FWD_RESP UINT32_C(0xd2)
406 #define HWRM_FWD_ASYNC_EVENT_CMPL UINT32_C(0xd3)
407 #define HWRM_OEM_CMD UINT32_C(0xd4)
408 /* Tells the fw to run PRBS test on a given port and lane. */
409 #define HWRM_PORT_PRBS_TEST UINT32_C(0xd5)
410 #define HWRM_TEMP_MONITOR_QUERY UINT32_C(0xe0)
411 #define HWRM_WOL_FILTER_ALLOC UINT32_C(0xf0)
412 #define HWRM_WOL_FILTER_FREE UINT32_C(0xf1)
413 #define HWRM_WOL_FILTER_QCFG UINT32_C(0xf2)
414 #define HWRM_WOL_REASON_QCFG UINT32_C(0xf3)
416 #define HWRM_CFA_METER_QCAPS UINT32_C(0xf4)
418 #define HWRM_CFA_METER_PROFILE_ALLOC UINT32_C(0xf5)
420 #define HWRM_CFA_METER_PROFILE_FREE UINT32_C(0xf6)
422 #define HWRM_CFA_METER_PROFILE_CFG UINT32_C(0xf7)
424 #define HWRM_CFA_METER_INSTANCE_ALLOC UINT32_C(0xf8)
426 #define HWRM_CFA_METER_INSTANCE_FREE UINT32_C(0xf9)
428 #define HWRM_CFA_METER_INSTANCE_CFG UINT32_C(0xfa)
430 #define HWRM_CFA_VFR_ALLOC UINT32_C(0xfd)
432 #define HWRM_CFA_VFR_FREE UINT32_C(0xfe)
434 #define HWRM_CFA_VF_PAIR_ALLOC UINT32_C(0x100)
436 #define HWRM_CFA_VF_PAIR_FREE UINT32_C(0x101)
438 #define HWRM_CFA_VF_PAIR_INFO UINT32_C(0x102)
440 #define HWRM_CFA_FLOW_ALLOC UINT32_C(0x103)
442 #define HWRM_CFA_FLOW_FREE UINT32_C(0x104)
444 #define HWRM_CFA_FLOW_FLUSH UINT32_C(0x105)
446 #define HWRM_CFA_FLOW_STATS UINT32_C(0x106)
448 #define HWRM_CFA_FLOW_INFO UINT32_C(0x107)
450 #define HWRM_CFA_DECAP_FILTER_ALLOC UINT32_C(0x108)
452 #define HWRM_CFA_DECAP_FILTER_FREE UINT32_C(0x109)
453 #define HWRM_CFA_VLAN_ANTISPOOF_QCFG UINT32_C(0x10a)
454 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_ALLOC UINT32_C(0x10b)
455 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_FREE UINT32_C(0x10c)
457 #define HWRM_CFA_PAIR_ALLOC UINT32_C(0x10d)
459 #define HWRM_CFA_PAIR_FREE UINT32_C(0x10e)
461 #define HWRM_CFA_PAIR_INFO UINT32_C(0x10f)
463 #define HWRM_FW_IPC_MSG UINT32_C(0x110)
464 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_INFO UINT32_C(0x111)
465 #define HWRM_CFA_REDIRECT_QUERY_TUNNEL_TYPE UINT32_C(0x112)
467 #define HWRM_CFA_FLOW_AGING_TIMER_RESET UINT32_C(0x113)
469 #define HWRM_CFA_FLOW_AGING_CFG UINT32_C(0x114)
471 #define HWRM_CFA_FLOW_AGING_QCFG UINT32_C(0x115)
473 #define HWRM_CFA_FLOW_AGING_QCAPS UINT32_C(0x116)
475 #define HWRM_CFA_CTX_MEM_RGTR UINT32_C(0x117)
477 #define HWRM_CFA_CTX_MEM_UNRGTR UINT32_C(0x118)
479 #define HWRM_CFA_CTX_MEM_QCTX UINT32_C(0x119)
481 #define HWRM_CFA_CTX_MEM_QCAPS UINT32_C(0x11a)
483 #define HWRM_CFA_COUNTER_QCAPS UINT32_C(0x11b)
485 #define HWRM_CFA_COUNTER_CFG UINT32_C(0x11c)
487 #define HWRM_CFA_COUNTER_QCFG UINT32_C(0x11d)
489 #define HWRM_CFA_COUNTER_QSTATS UINT32_C(0x11e)
491 #define HWRM_CFA_TCP_FLAG_PROCESS_QCFG UINT32_C(0x11f)
493 #define HWRM_CFA_EEM_QCAPS UINT32_C(0x120)
495 #define HWRM_CFA_EEM_CFG UINT32_C(0x121)
497 #define HWRM_CFA_EEM_QCFG UINT32_C(0x122)
499 #define HWRM_CFA_EEM_OP UINT32_C(0x123)
501 #define HWRM_CFA_ADV_FLOW_MGNT_QCAPS UINT32_C(0x124)
503 #define HWRM_CFA_TFLIB UINT32_C(0x125)
504 /* Engine CKV - Get the current allocation status of keys provisioned in the key vault. */
505 #define HWRM_ENGINE_CKV_STATUS UINT32_C(0x12e)
506 /* Engine CKV - Add a new CKEK used to encrypt keys. */
507 #define HWRM_ENGINE_CKV_CKEK_ADD UINT32_C(0x12f)
508 /* Engine CKV - Delete a previously added CKEK. */
509 #define HWRM_ENGINE_CKV_CKEK_DELETE UINT32_C(0x130)
510 /* Engine CKV - Add a new key to the key vault. */
511 #define HWRM_ENGINE_CKV_KEY_ADD UINT32_C(0x131)
512 /* Engine CKV - Delete a key from the key vault. */
513 #define HWRM_ENGINE_CKV_KEY_DELETE UINT32_C(0x132)
514 /* Engine CKV - Delete all keys from the key vault. */
515 #define HWRM_ENGINE_CKV_FLUSH UINT32_C(0x133)
516 /* Engine CKV - Get random data. */
517 #define HWRM_ENGINE_CKV_RNG_GET UINT32_C(0x134)
518 /* Engine CKV - Generate and encrypt a new AES key. */
519 #define HWRM_ENGINE_CKV_KEY_GEN UINT32_C(0x135)
520 /* Engine CKV - Configure a label index with a label value. */
521 #define HWRM_ENGINE_CKV_KEY_LABEL_CFG UINT32_C(0x136)
522 /* Engine CKV - Query a label */
523 #define HWRM_ENGINE_CKV_KEY_LABEL_QCFG UINT32_C(0x137)
524 /* Engine - Query the available queue groups configuration. */
525 #define HWRM_ENGINE_QG_CONFIG_QUERY UINT32_C(0x13c)
526 /* Engine - Query the queue groups assigned to a function. */
527 #define HWRM_ENGINE_QG_QUERY UINT32_C(0x13d)
528 /* Engine - Query the available queue group meter profile configuration. */
529 #define HWRM_ENGINE_QG_METER_PROFILE_CONFIG_QUERY UINT32_C(0x13e)
530 /* Engine - Query the configuration of a queue group meter profile. */
531 #define HWRM_ENGINE_QG_METER_PROFILE_QUERY UINT32_C(0x13f)
532 /* Engine - Allocate a queue group meter profile. */
533 #define HWRM_ENGINE_QG_METER_PROFILE_ALLOC UINT32_C(0x140)
534 /* Engine - Free a queue group meter profile. */
535 #define HWRM_ENGINE_QG_METER_PROFILE_FREE UINT32_C(0x141)
536 /* Engine - Query the meters assigned to a queue group. */
537 #define HWRM_ENGINE_QG_METER_QUERY UINT32_C(0x142)
538 /* Engine - Bind a queue group meter profile to a queue group. */
539 #define HWRM_ENGINE_QG_METER_BIND UINT32_C(0x143)
540 /* Engine - Unbind a queue group meter profile from a queue group. */
541 #define HWRM_ENGINE_QG_METER_UNBIND UINT32_C(0x144)
542 /* Engine - Bind a queue group to a function. */
543 #define HWRM_ENGINE_QG_FUNC_BIND UINT32_C(0x145)
544 /* Engine - Query the scheduling group configuration. */
545 #define HWRM_ENGINE_SG_CONFIG_QUERY UINT32_C(0x146)
546 /* Engine - Query the queue groups assigned to a scheduling group. */
547 #define HWRM_ENGINE_SG_QUERY UINT32_C(0x147)
548 /* Engine - Query the configuration of a scheduling group's meter profiles. */
549 #define HWRM_ENGINE_SG_METER_QUERY UINT32_C(0x148)
550 /* Engine - Configure a scheduling group's meter profiles. */
551 #define HWRM_ENGINE_SG_METER_CONFIG UINT32_C(0x149)
552 /* Engine - Bind a queue group to a scheduling group. */
553 #define HWRM_ENGINE_SG_QG_BIND UINT32_C(0x14a)
554 /* Engine - Unbind a queue group from its scheduling group. */
555 #define HWRM_ENGINE_QG_SG_UNBIND UINT32_C(0x14b)
556 /* Engine - Query the Engine configuration. */
557 #define HWRM_ENGINE_CONFIG_QUERY UINT32_C(0x154)
558 /* Engine - Configure the statistics accumulator for an Engine. */
559 #define HWRM_ENGINE_STATS_CONFIG UINT32_C(0x155)
560 /* Engine - Clear the statistics accumulator for an Engine. */
561 #define HWRM_ENGINE_STATS_CLEAR UINT32_C(0x156)
562 /* Engine - Query the statistics accumulator for an Engine. */
563 #define HWRM_ENGINE_STATS_QUERY UINT32_C(0x157)
564 /* Engine - Allocate an Engine RQ. */
565 #define HWRM_ENGINE_RQ_ALLOC UINT32_C(0x15e)
566 /* Engine - Free an Engine RQ. */
567 #define HWRM_ENGINE_RQ_FREE UINT32_C(0x15f)
568 /* Engine - Allocate an Engine CQ. */
569 #define HWRM_ENGINE_CQ_ALLOC UINT32_C(0x160)
570 /* Engine - Free an Engine CQ. */
571 #define HWRM_ENGINE_CQ_FREE UINT32_C(0x161)
572 /* Engine - Allocate an NQ. */
573 #define HWRM_ENGINE_NQ_ALLOC UINT32_C(0x162)
574 /* Engine - Free an NQ. */
575 #define HWRM_ENGINE_NQ_FREE UINT32_C(0x163)
576 /* Engine - Set the on-die RQE credit update location. */
577 #define HWRM_ENGINE_ON_DIE_RQE_CREDITS UINT32_C(0x164)
578 /* Engine - Query the engine function configuration. */
579 #define HWRM_ENGINE_FUNC_QCFG UINT32_C(0x165)
581 #define HWRM_FUNC_RESOURCE_QCAPS UINT32_C(0x190)
583 #define HWRM_FUNC_VF_RESOURCE_CFG UINT32_C(0x191)
585 #define HWRM_FUNC_BACKING_STORE_QCAPS UINT32_C(0x192)
587 #define HWRM_FUNC_BACKING_STORE_CFG UINT32_C(0x193)
589 #define HWRM_FUNC_BACKING_STORE_QCFG UINT32_C(0x194)
590 /* Configures the BW of any VF */
591 #define HWRM_FUNC_VF_BW_CFG UINT32_C(0x195)
592 /* Queries the BW of any VF */
593 #define HWRM_FUNC_VF_BW_QCFG UINT32_C(0x196)
594 /* Queries pf ids belong to specified host(s) */
595 #define HWRM_FUNC_HOST_PF_IDS_QUERY UINT32_C(0x197)
597 #define HWRM_SELFTEST_QLIST UINT32_C(0x200)
599 #define HWRM_SELFTEST_EXEC UINT32_C(0x201)
601 #define HWRM_SELFTEST_IRQ UINT32_C(0x202)
603 #define HWRM_SELFTEST_RETRIEVE_SERDES_DATA UINT32_C(0x203)
605 #define HWRM_PCIE_QSTATS UINT32_C(0x204)
607 #define HWRM_MFG_FRU_WRITE_CONTROL UINT32_C(0x205)
608 /* Returns the current value of a free running counter from the device. */
609 #define HWRM_MFG_TIMERS_QUERY UINT32_C(0x206)
611 #define HWRM_MFG_OTP_CFG UINT32_C(0x207)
613 #define HWRM_MFG_OTP_QCFG UINT32_C(0x208)
615 * Tells the fw to run the DMA read from the host and DMA write
618 #define HWRM_MFG_HDMA_TEST UINT32_C(0x209)
620 #define HWRM_DBG_READ_DIRECT UINT32_C(0xff10)
622 #define HWRM_DBG_READ_INDIRECT UINT32_C(0xff11)
624 #define HWRM_DBG_WRITE_DIRECT UINT32_C(0xff12)
626 #define HWRM_DBG_WRITE_INDIRECT UINT32_C(0xff13)
627 #define HWRM_DBG_DUMP UINT32_C(0xff14)
629 #define HWRM_DBG_ERASE_NVM UINT32_C(0xff15)
631 #define HWRM_DBG_CFG UINT32_C(0xff16)
633 #define HWRM_DBG_COREDUMP_LIST UINT32_C(0xff17)
635 #define HWRM_DBG_COREDUMP_INITIATE UINT32_C(0xff18)
637 #define HWRM_DBG_COREDUMP_RETRIEVE UINT32_C(0xff19)
639 #define HWRM_DBG_FW_CLI UINT32_C(0xff1a)
641 #define HWRM_DBG_I2C_CMD UINT32_C(0xff1b)
643 #define HWRM_DBG_RING_INFO_GET UINT32_C(0xff1c)
645 #define HWRM_DBG_CRASHDUMP_HEADER UINT32_C(0xff1d)
647 #define HWRM_DBG_CRASHDUMP_ERASE UINT32_C(0xff1e)
649 #define HWRM_NVM_FACTORY_DEFAULTS UINT32_C(0xffee)
650 #define HWRM_NVM_VALIDATE_OPTION UINT32_C(0xffef)
651 #define HWRM_NVM_FLUSH UINT32_C(0xfff0)
652 #define HWRM_NVM_GET_VARIABLE UINT32_C(0xfff1)
653 #define HWRM_NVM_SET_VARIABLE UINT32_C(0xfff2)
654 #define HWRM_NVM_INSTALL_UPDATE UINT32_C(0xfff3)
655 #define HWRM_NVM_MODIFY UINT32_C(0xfff4)
656 #define HWRM_NVM_VERIFY_UPDATE UINT32_C(0xfff5)
657 #define HWRM_NVM_GET_DEV_INFO UINT32_C(0xfff6)
658 #define HWRM_NVM_ERASE_DIR_ENTRY UINT32_C(0xfff7)
659 #define HWRM_NVM_MOD_DIR_ENTRY UINT32_C(0xfff8)
660 #define HWRM_NVM_FIND_DIR_ENTRY UINT32_C(0xfff9)
661 #define HWRM_NVM_GET_DIR_ENTRIES UINT32_C(0xfffa)
662 #define HWRM_NVM_GET_DIR_INFO UINT32_C(0xfffb)
663 #define HWRM_NVM_RAW_DUMP UINT32_C(0xfffc)
664 #define HWRM_NVM_READ UINT32_C(0xfffd)
665 #define HWRM_NVM_WRITE UINT32_C(0xfffe)
666 #define HWRM_NVM_RAW_WRITE_BLK UINT32_C(0xffff)
667 #define HWRM_LAST HWRM_NVM_RAW_WRITE_BLK
668 uint16_t unused_0[3];
669 } __attribute__((packed));
672 /* ret_codes (size:64b/8B) */
675 /* Request was successfully executed by the HWRM. */
676 #define HWRM_ERR_CODE_SUCCESS UINT32_C(0x0)
677 /* The HWRM failed to execute the request. */
678 #define HWRM_ERR_CODE_FAIL UINT32_C(0x1)
680 * The request contains invalid argument(s) or input
683 #define HWRM_ERR_CODE_INVALID_PARAMS UINT32_C(0x2)
685 * The requester is not allowed to access the requested
686 * resource. This error code shall be provided in a
687 * response to a request to query or modify an existing
688 * resource that is not accessible by the requester.
690 #define HWRM_ERR_CODE_RESOURCE_ACCESS_DENIED UINT32_C(0x3)
692 * The HWRM is unable to allocate the requested resource.
693 * This code only applies to requests for HWRM resource
696 #define HWRM_ERR_CODE_RESOURCE_ALLOC_ERROR UINT32_C(0x4)
698 * Invalid combination of flags is specified in the
701 #define HWRM_ERR_CODE_INVALID_FLAGS UINT32_C(0x5)
703 * Invalid combination of enables fields is specified in
706 #define HWRM_ERR_CODE_INVALID_ENABLES UINT32_C(0x6)
708 * Request contains a required TLV that is not supported by
709 * the installed version of firmware.
711 #define HWRM_ERR_CODE_UNSUPPORTED_TLV UINT32_C(0x7)
713 * No firmware buffer available to accept the request. Driver
714 * should retry the request.
716 #define HWRM_ERR_CODE_NO_BUFFER UINT32_C(0x8)
718 * This error code is only reported by firmware when some
719 * sub-option of a supported HWRM command is unsupported.
721 #define HWRM_ERR_CODE_UNSUPPORTED_OPTION_ERR UINT32_C(0x9)
723 * This error code is only reported by firmware when the specific
724 * request is not able to process when the HOT reset in progress.
726 #define HWRM_ERR_CODE_HOT_RESET_PROGRESS UINT32_C(0xa)
728 * This error code is only reported by firmware when the registered
729 * driver instances are not capable of hot reset.
731 #define HWRM_ERR_CODE_HOT_RESET_FAIL UINT32_C(0xb)
733 * This error code is only reported by the firmware when during
734 * flow allocation when a requeest for a flow counter fails because
735 * the number of flow counters are exhausted.
737 #define HWRM_ERR_CODE_NO_FLOW_COUNTER_DURING_ALLOC UINT32_C(0xc)
739 * This error code is only reported by firmware when the registered
740 * driver instances requested to offloaded a flow but was unable to because
741 * the requested key's hash collides with the installed keys.
743 #define HWRM_ERR_CODE_KEY_HASH_COLLISION UINT32_C(0xd)
745 * This error code is only reported by firmware when the registered
746 * driver instances requested to offloaded a flow but was unable to because
747 * the same key has already been installed.
749 #define HWRM_ERR_CODE_KEY_ALREADY_EXISTS UINT32_C(0xe)
751 * Generic HWRM execution error that represents an
754 #define HWRM_ERR_CODE_HWRM_ERROR UINT32_C(0xf)
756 * This value indicates that the HWRM response is in TLV format and
757 * should be interpreted as one or more TLVs starting with the
758 * hwrm_resp_hdr TLV. This value is not an indicatation of any error
759 * by itself, just an indicatation that the response should be parsed
760 * as TLV and the actual error code will be in the hwrm_resp_hdr TLV.
762 #define HWRM_ERR_CODE_TLV_ENCAPSULATED_RESPONSE UINT32_C(0x8000)
764 #define HWRM_ERR_CODE_UNKNOWN_ERR UINT32_C(0xfffe)
765 /* Unsupported or invalid command */
766 #define HWRM_ERR_CODE_CMD_NOT_SUPPORTED UINT32_C(0xffff)
767 #define HWRM_ERR_CODE_LAST \
768 HWRM_ERR_CODE_CMD_NOT_SUPPORTED
769 uint16_t unused_0[3];
770 } __attribute__((packed));
773 /* hwrm_err_output (size:128b/16B) */
774 struct hwrm_err_output {
776 * Pass/Fail or error type
778 * Note: receiver to verify the in parameters, and fail the call
779 * with an error when appropriate
782 /* This field returns the type of original request. */
784 /* This field provides original sequence number of the command. */
787 * This field is the length of the response in bytes. The
788 * last byte of the response is a valid flag that will read
789 * as '1' when the command has been completely written to
793 /* debug info for this error response. */
795 /* debug info for this error response. */
798 * In the case of an error response, command specific error
799 * code is returned in this field.
803 * This field is used in Output records to indicate that the output
804 * is completely written to RAM. This field should be read as '1'
805 * to indicate that the output has been completely written.
806 * When writing a command completion or response to an internal processor,
807 * the order of writes has to be such that this field is written last.
810 } __attribute__((packed));
812 * Following is the signature for HWRM message field that indicates not
813 * applicable (All F's). Need to cast it the size of the field if needed.
815 #define HWRM_NA_SIGNATURE ((uint32_t)(-1))
816 /* hwrm_func_buf_rgtr */
817 #define HWRM_MAX_REQ_LEN 128
818 /* hwrm_cfa_flow_info */
819 #define HWRM_MAX_RESP_LEN 704
820 /* 7 bit indirection table index. */
821 #define HW_HASH_INDEX_SIZE 0x80
822 #define HW_HASH_KEY_SIZE 40
823 /* valid key for HWRM response */
824 #define HWRM_RESP_VALID_KEY 1
825 /* Reserved for BONO processor */
826 #define HWRM_TARGET_ID_BONO 0xFFF8
827 /* Reserved for KONG processor */
828 #define HWRM_TARGET_ID_KONG 0xFFF9
829 /* Reserved for APE processor */
830 #define HWRM_TARGET_ID_APE 0xFFFA
832 * This value will be used by tools for User-space HWRM Interface.
833 * When tool execute any HWRM command with this target_id, firmware
834 * will copy the response and/or data payload via register space instead
837 #define HWRM_TARGET_ID_TOOLS 0xFFFD
838 #define HWRM_VERSION_MAJOR 1
839 #define HWRM_VERSION_MINOR 10
840 #define HWRM_VERSION_UPDATE 0
841 /* non-zero means beta version */
842 #define HWRM_VERSION_RSVD 91
843 #define HWRM_VERSION_STR "1.10.0.91"
850 /* hwrm_ver_get_input (size:192b/24B) */
851 struct hwrm_ver_get_input {
852 /* The HWRM command request type. */
855 * The completion ring to send the completion event on. This should
856 * be the NQ ID returned from the `nq_alloc` HWRM command.
860 * The sequence ID is used by the driver for tracking multiple
861 * commands. This ID is treated as opaque data by the firmware and
862 * the value is returned in the `hwrm_resp_hdr` upon completion.
866 * The target ID of the command:
867 * * 0x0-0xFFF8 - The function ID
868 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
869 * * 0xFFFD - Reserved for user-space HWRM interface
874 * A physical address pointer pointing to a host buffer that the
875 * command's response data will be written. This can be either a host
876 * physical address (HPA) or a guest physical address (GPA) and must
877 * point to a physically contiguous block of memory.
881 * This field represents the major version of HWRM interface
882 * specification supported by the driver HWRM implementation.
883 * The interface major version is intended to change only when
884 * non backward compatible changes are made to the HWRM
885 * interface specification.
887 uint8_t hwrm_intf_maj;
889 * This field represents the minor version of HWRM interface
890 * specification supported by the driver HWRM implementation.
891 * A change in interface minor version is used to reflect
892 * significant backward compatible modification to HWRM
893 * interface specification.
894 * This can be due to addition or removal of functionality.
895 * HWRM interface specifications with the same major version
896 * but different minor versions are compatible.
898 uint8_t hwrm_intf_min;
900 * This field represents the update version of HWRM interface
901 * specification supported by the driver HWRM implementation.
902 * The interface update version is used to reflect minor
903 * changes or bug fixes to a released HWRM interface
906 uint8_t hwrm_intf_upd;
908 } __attribute__((packed));
910 /* hwrm_ver_get_output (size:1408b/176B) */
911 struct hwrm_ver_get_output {
912 /* The specific error status for the command. */
914 /* The HWRM command request type. */
916 /* The sequence ID from the original command. */
918 /* The length of the response data in number of bytes. */
921 * This field represents the major version of HWRM interface
922 * specification supported by the HWRM implementation.
923 * The interface major version is intended to change only when
924 * non backward compatible changes are made to the HWRM
925 * interface specification.
926 * A HWRM implementation that is compliant with this
927 * specification shall provide value of 1 in this field.
929 uint8_t hwrm_intf_maj_8b;
931 * This field represents the minor version of HWRM interface
932 * specification supported by the HWRM implementation.
933 * A change in interface minor version is used to reflect
934 * significant backward compatible modification to HWRM
935 * interface specification.
936 * This can be due to addition or removal of functionality.
937 * HWRM interface specifications with the same major version
938 * but different minor versions are compatible.
939 * A HWRM implementation that is compliant with this
940 * specification shall provide value of 2 in this field.
942 uint8_t hwrm_intf_min_8b;
944 * This field represents the update version of HWRM interface
945 * specification supported by the HWRM implementation.
946 * The interface update version is used to reflect minor
947 * changes or bug fixes to a released HWRM interface
949 * A HWRM implementation that is compliant with this
950 * specification shall provide value of 2 in this field.
952 uint8_t hwrm_intf_upd_8b;
953 uint8_t hwrm_intf_rsvd_8b;
955 * This field represents the major version of HWRM firmware.
956 * A change in firmware major version represents a major
959 uint8_t hwrm_fw_maj_8b;
961 * This field represents the minor version of HWRM firmware.
962 * A change in firmware minor version represents significant
963 * firmware functionality changes.
965 uint8_t hwrm_fw_min_8b;
967 * This field represents the build version of HWRM firmware.
968 * A change in firmware build version represents bug fixes
969 * to a released firmware.
971 uint8_t hwrm_fw_bld_8b;
973 * This field is a reserved field. This field can be used to
974 * represent firmware branches or customer specific releases
975 * tied to a specific (major,minor,update) version of the
978 uint8_t hwrm_fw_rsvd_8b;
980 * This field represents the major version of mgmt firmware.
981 * A change in major version represents a major release.
983 uint8_t mgmt_fw_maj_8b;
985 * This field represents the minor version of mgmt firmware.
986 * A change in minor version represents significant
987 * functionality changes.
989 uint8_t mgmt_fw_min_8b;
991 * This field represents the build version of mgmt firmware.
992 * A change in update version represents bug fixes.
994 uint8_t mgmt_fw_bld_8b;
996 * This field is a reserved field. This field can be used to
997 * represent firmware branches or customer specific releases
998 * tied to a specific (major,minor,update) version
1000 uint8_t mgmt_fw_rsvd_8b;
1002 * This field represents the major version of network
1004 * A change in major version represents a major release.
1006 uint8_t netctrl_fw_maj_8b;
1008 * This field represents the minor version of network
1010 * A change in minor version represents significant
1011 * functionality changes.
1013 uint8_t netctrl_fw_min_8b;
1015 * This field represents the build version of network
1017 * A change in update version represents bug fixes.
1019 uint8_t netctrl_fw_bld_8b;
1021 * This field is a reserved field. This field can be used to
1022 * represent firmware branches or customer specific releases
1023 * tied to a specific (major,minor,update) version
1025 uint8_t netctrl_fw_rsvd_8b;
1027 * This field is used to indicate device's capabilities and
1030 uint32_t dev_caps_cfg;
1032 * If set to 1, then secure firmware update behavior
1034 * If set to 0, then secure firmware update behavior is
1037 #define HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_SECURE_FW_UPD_SUPPORTED \
1040 * If set to 1, then firmware based DCBX agent is supported.
1041 * If set to 0, then firmware based DCBX agent capability
1042 * is not supported on this device.
1044 #define HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_FW_DCBX_AGENT_SUPPORTED \
1047 * If set to 1, then HWRM short command format is supported.
1048 * If set to 0, then HWRM short command format is not supported.
1050 #define HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_SHORT_CMD_SUPPORTED \
1053 * If set to 1, then HWRM short command format is required.
1054 * If set to 0, then HWRM short command format is not required.
1056 #define HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_SHORT_CMD_REQUIRED \
1059 * If set to 1, then the KONG host mailbox channel is supported.
1060 * If set to 0, then the KONG host mailbox channel is not supported.
1061 * By default, this flag should be 0 for older version of core firmware.
1063 #define HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_KONG_MB_CHNL_SUPPORTED \
1066 * If set to 1, then the 64bit flow handle is supported in addition to the
1067 * legacy 16bit flow handle. If set to 0, then the 64bit flow handle is not
1068 * supported. By default, this flag should be 0 for older version of core firmware.
1070 #define HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_FLOW_HANDLE_64BIT_SUPPORTED \
1073 * If set to 1, then filter type can be provided in filter_alloc or filter_cfg
1074 * filter types like L2 for l2 traffic and ROCE for roce & l2 traffic.
1075 * If set to 0, then filter types not supported.
1076 * By default, this flag should be 0 for older version of core firmware.
1078 #define HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_L2_FILTER_TYPES_ROCE_OR_L2_SUPPORTED \
1081 * If set to 1, firmware is capable to support virtio vSwitch offload model.
1082 * If set to 0, firmware can't supported virtio vSwitch offload model.
1083 * By default, this flag should be 0 for older version of core firmware.
1085 #define HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_VIRTIO_VSWITCH_OFFLOAD_SUPPORTED \
1088 * If set to 1, firmware is capable to support trusted VF.
1089 * If set to 0, firmware is not capable to support trusted VF.
1090 * By default, this flag should be 0 for older version of core firmware.
1092 #define HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_TRUSTED_VF_SUPPORTED \
1095 * If set to 1, firmware is capable to support flow aging.
1096 * If set to 0, firmware is not capable to support flow aging.
1097 * By default, this flag should be 0 for older version of core firmware.
1099 #define HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_FLOW_AGING_SUPPORTED \
1102 * If set to 1, firmware is capable to support advanced flow counters like,
1103 * Meter drop counters and EEM counters.
1104 * If set to 0, firmware is not capable to support advanced flow counters.
1105 * By default, this flag should be 0 for older version of core firmware.
1107 #define HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_ADV_FLOW_COUNTERS_SUPPORTED \
1110 * If set to 1, the firmware is able to support the use of the CFA
1111 * Extended Exact Match(EEM) feature.
1112 * If set to 0, firmware is not capable to support the use of the
1114 * By default, this flag should be 0 for older version of core firmware.
1116 #define HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_CFA_EEM_SUPPORTED \
1119 * If set to 1, the firmware is able to support advance CFA flow management
1120 * features reported in the HWRM_CFA_FLOW_MGNT_QCAPS.
1121 * If set to 0, then the firmware doesn’t support the advance CFA flow management
1123 * By default, this flag should be 0 for older version of core firmware.
1125 #define HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_CFA_ADV_FLOW_MGNT_SUPPORTED \
1128 * If set to 1, the firmware is able to support TFLIB features.
1129 * If set to 0, then the firmware doesn’t support TFLIB features.
1130 * By default, this flag should be 0 for older version of core firmware.
1132 #define HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_CFA_TFLIB_SUPPORTED \
1135 * This field represents the major version of RoCE firmware.
1136 * A change in major version represents a major release.
1138 uint8_t roce_fw_maj_8b;
1140 * This field represents the minor version of RoCE firmware.
1141 * A change in minor version represents significant
1142 * functionality changes.
1144 uint8_t roce_fw_min_8b;
1146 * This field represents the build version of RoCE firmware.
1147 * A change in update version represents bug fixes.
1149 uint8_t roce_fw_bld_8b;
1151 * This field is a reserved field. This field can be used to
1152 * represent firmware branches or customer specific releases
1153 * tied to a specific (major,minor,update) version
1155 uint8_t roce_fw_rsvd_8b;
1157 * This field represents the name of HWRM FW (ASCII chars
1158 * with NULL at the end).
1160 char hwrm_fw_name[16];
1162 * This field represents the name of mgmt FW (ASCII chars
1163 * with NULL at the end).
1165 char mgmt_fw_name[16];
1167 * This field represents the name of network control
1168 * firmware (ASCII chars with NULL at the end).
1170 char netctrl_fw_name[16];
1171 /* This field represents the active board package name. */
1172 char active_pkg_name[16];
1174 * This field represents the name of RoCE FW (ASCII chars
1175 * with NULL at the end).
1177 char roce_fw_name[16];
1178 /* This field returns the chip number. */
1180 /* This field returns the revision of chip. */
1182 /* This field returns the chip metal number. */
1184 /* This field returns the bond id of the chip. */
1185 uint8_t chip_bond_id;
1186 /* This value indicates the type of platform used for chip implementation. */
1187 uint8_t chip_platform_type;
1189 #define HWRM_VER_GET_OUTPUT_CHIP_PLATFORM_TYPE_ASIC UINT32_C(0x0)
1190 /* FPGA platform of the chip. */
1191 #define HWRM_VER_GET_OUTPUT_CHIP_PLATFORM_TYPE_FPGA UINT32_C(0x1)
1192 /* Palladium platform of the chip. */
1193 #define HWRM_VER_GET_OUTPUT_CHIP_PLATFORM_TYPE_PALLADIUM UINT32_C(0x2)
1194 #define HWRM_VER_GET_OUTPUT_CHIP_PLATFORM_TYPE_LAST \
1195 HWRM_VER_GET_OUTPUT_CHIP_PLATFORM_TYPE_PALLADIUM
1197 * This field returns the maximum value of request window that
1198 * is supported by the HWRM. The request window is mapped
1199 * into device address space using MMIO.
1201 uint16_t max_req_win_len;
1203 * This field returns the maximum value of response buffer in
1206 uint16_t max_resp_len;
1208 * This field returns the default request timeout value in
1211 uint16_t def_req_timeout;
1213 * This field will indicate if any subsystems is not fully
1218 * If set to 1, it will indicate to host drivers that firmware is
1219 * not ready to start full blown HWRM commands. Host drivers should
1220 * re-try HWRM_VER_GET with some timeout period. The timeout period
1221 * can be selected up to 5 seconds.
1222 * For Example, PCIe hot-plug:
1223 * Hot plug timing is system dependent. It generally takes up to
1224 * 600 miliseconds for firmware to clear DEV_NOT_RDY flag.
1225 * If set to 0, device is ready to accept all HWRM commands.
1227 #define HWRM_VER_GET_OUTPUT_FLAGS_DEV_NOT_RDY UINT32_C(0x1)
1229 * If set to 1, external version present.
1230 * If set to 0, external version not present.
1232 #define HWRM_VER_GET_OUTPUT_FLAGS_EXT_VER_AVAIL UINT32_C(0x2)
1233 uint8_t unused_0[2];
1235 * For backward compatibility this field must be set to 1.
1236 * Older drivers might look for this field to be 1 before
1237 * processing the message.
1241 * This field represents the major version of HWRM interface
1242 * specification supported by the HWRM implementation.
1243 * The interface major version is intended to change only when
1244 * non backward compatible changes are made to the HWRM
1245 * interface specification. A HWRM implementation that is
1246 * compliant with this specification shall provide value of 1
1249 uint16_t hwrm_intf_major;
1251 * This field represents the minor version of HWRM interface
1252 * specification supported by the HWRM implementation.
1253 * A change in interface minor version is used to reflect
1254 * significant backward compatible modification to HWRM
1255 * interface specification. This can be due to addition or
1256 * removal of functionality. HWRM interface specifications
1257 * with the same major version but different minor versions are
1258 * compatible. A HWRM implementation that is compliant with
1259 * this specification shall provide value of 2 in this field.
1261 uint16_t hwrm_intf_minor;
1263 * This field represents the update version of HWRM interface
1264 * specification supported by the HWRM implementation. The
1265 * interface update version is used to reflect minor changes or
1266 * bug fixes to a released HWRM interface specification.
1267 * A HWRM implementation that is compliant with this
1268 * specification shall provide value of 2 in this field.
1270 uint16_t hwrm_intf_build;
1272 * This field represents the patch version of HWRM interface
1273 * specification supported by the HWRM implementation.
1275 uint16_t hwrm_intf_patch;
1277 * This field represents the major version of HWRM firmware.
1278 * A change in firmware major version represents a major
1281 uint16_t hwrm_fw_major;
1283 * This field represents the minor version of HWRM firmware.
1284 * A change in firmware minor version represents significant
1285 * firmware functionality changes.
1287 uint16_t hwrm_fw_minor;
1289 * This field represents the build version of HWRM firmware.
1290 * A change in firmware build version represents bug fixes to
1291 * a released firmware.
1293 uint16_t hwrm_fw_build;
1295 * This field is a reserved field.
1296 * This field can be used to represent firmware branches or customer
1297 * specific releases tied to a specific (major,minor,update) version
1298 * of the HWRM firmware.
1300 uint16_t hwrm_fw_patch;
1302 * This field represents the major version of mgmt firmware.
1303 * A change in major version represents a major release.
1305 uint16_t mgmt_fw_major;
1307 * This field represents the minor version of HWRM firmware.
1308 * A change in firmware minor version represents significant
1309 * firmware functionality changes.
1311 uint16_t mgmt_fw_minor;
1313 * This field represents the build version of mgmt firmware.
1314 * A change in update version represents bug fixes.
1316 uint16_t mgmt_fw_build;
1318 * This field is a reserved field. This field can be used to
1319 * represent firmware branches or customer specific releases
1320 * tied to a specific (major,minor,update) version.
1322 uint16_t mgmt_fw_patch;
1324 * This field represents the major version of network control
1325 * firmware. A change in major version represents
1328 uint16_t netctrl_fw_major;
1330 * This field represents the minor version of network control
1331 * firmware. A change in minor version represents significant
1332 * functionality changes.
1334 uint16_t netctrl_fw_minor;
1336 * This field represents the build version of network control
1337 * firmware. A change in update version represents bug fixes.
1339 uint16_t netctrl_fw_build;
1341 * This field is a reserved field. This field can be used to
1342 * represent firmware branches or customer specific releases
1343 * tied to a specific (major,minor,update) version
1345 uint16_t netctrl_fw_patch;
1347 * This field represents the major version of RoCE firmware.
1348 * A change in major version represents a major release.
1350 uint16_t roce_fw_major;
1352 * This field represents the minor version of RoCE firmware.
1353 * A change in minor version represents significant
1354 * functionality changes.
1356 uint16_t roce_fw_minor;
1358 * This field represents the build version of RoCE firmware.
1359 * A change in update version represents bug fixes.
1361 uint16_t roce_fw_build;
1363 * This field is a reserved field. This field can be used to
1364 * represent firmware branches or customer specific releases
1365 * tied to a specific (major,minor,update) version
1367 uint16_t roce_fw_patch;
1369 * This field returns the maximum extended request length acceptable
1370 * by the device which allows requests greater than mailbox size when
1371 * used with the short cmd request format.
1373 uint16_t max_ext_req_len;
1374 uint8_t unused_1[5];
1376 * This field is used in Output records to indicate that the output
1377 * is completely written to RAM. This field should be read as '1'
1378 * to indicate that the output has been completely written.
1379 * When writing a command completion or response to an internal processor,
1380 * the order of writes has to be such that this field is written last.
1383 } __attribute__((packed));
1385 /* bd_base (size:64b/8B) */
1388 /* This value identifies the type of buffer descriptor. */
1389 #define BD_BASE_TYPE_MASK UINT32_C(0x3f)
1390 #define BD_BASE_TYPE_SFT 0
1392 * Indicates that this BD is 16B long and is used for
1393 * normal L2 packet transmission.
1395 #define BD_BASE_TYPE_TX_BD_SHORT UINT32_C(0x0)
1397 * Indicates that this BD is 1BB long and is an empty
1398 * TX BD. Not valid for use by the driver.
1400 #define BD_BASE_TYPE_TX_BD_EMPTY UINT32_C(0x1)
1402 * Indicates that this BD is 16B long and is an RX Producer
1403 * (ie. empty) buffer descriptor.
1405 #define BD_BASE_TYPE_RX_PROD_PKT UINT32_C(0x4)
1407 * Indicates that this BD is 16B long and is an RX
1408 * Producer Buffer BD.
1410 #define BD_BASE_TYPE_RX_PROD_BFR UINT32_C(0x5)
1412 * Indicates that this BD is 16B long and is an
1413 * RX Producer Assembly Buffer Descriptor.
1415 #define BD_BASE_TYPE_RX_PROD_AGG UINT32_C(0x6)
1417 * Indicates that this BD is 32B long and is used for
1418 * normal L2 packet transmission.
1420 #define BD_BASE_TYPE_TX_BD_LONG UINT32_C(0x10)
1422 * Indicates that this BD is 32B long and is used for
1423 * L2 packet transmission for small packets that require
1426 #define BD_BASE_TYPE_TX_BD_LONG_INLINE UINT32_C(0x11)
1427 #define BD_BASE_TYPE_LAST BD_BASE_TYPE_TX_BD_LONG_INLINE
1428 uint8_t unused_1[7];
1429 } __attribute__((packed));
1431 /* tx_bd_short (size:128b/16B) */
1432 struct tx_bd_short {
1434 * All bits in this field must be valid on the first BD of a packet.
1435 * Only the packet_end bit must be valid for the remaining BDs
1438 uint16_t flags_type;
1439 /* This value identifies the type of buffer descriptor. */
1440 #define TX_BD_SHORT_TYPE_MASK UINT32_C(0x3f)
1441 #define TX_BD_SHORT_TYPE_SFT 0
1443 * Indicates that this BD is 16B long and is used for
1444 * normal L2 packet transmission.
1446 #define TX_BD_SHORT_TYPE_TX_BD_SHORT UINT32_C(0x0)
1447 #define TX_BD_SHORT_TYPE_LAST TX_BD_SHORT_TYPE_TX_BD_SHORT
1449 * All bits in this field must be valid on the first BD of a packet.
1450 * Only the packet_end bit must be valid for the remaining BDs
1453 #define TX_BD_SHORT_FLAGS_MASK UINT32_C(0xffc0)
1454 #define TX_BD_SHORT_FLAGS_SFT 6
1456 * If set to 1, the packet ends with the data in the buffer
1457 * pointed to by this descriptor. This flag must be
1458 * valid on every BD.
1460 #define TX_BD_SHORT_FLAGS_PACKET_END UINT32_C(0x40)
1462 * If set to 1, the device will not generate a completion for
1463 * this transmit packet unless there is an error in it's
1466 * is set to 0, then the packet will be completed normally.
1468 * This bit must be valid only on the first BD of a packet.
1470 #define TX_BD_SHORT_FLAGS_NO_CMPL UINT32_C(0x80)
1472 * This value indicates how many 16B BD locations are consumed
1473 * in the ring by this packet.
1474 * A value of 1 indicates that this BD is the only BD (and that
1475 * the it is a short BD). A value
1476 * of 3 indicates either 3 short BDs or 1 long BD and one short
1477 * BD in the packet. A value of 0 indicates
1478 * that there are 32 BD locations in the packet (the maximum).
1480 * This field is valid only on the first BD of a packet.
1482 #define TX_BD_SHORT_FLAGS_BD_CNT_MASK UINT32_C(0x1f00)
1483 #define TX_BD_SHORT_FLAGS_BD_CNT_SFT 8
1485 * This value is a hint for the length of the entire packet.
1486 * It is used by the chip to optimize internal processing.
1488 * The packet will be dropped if the hint is too short.
1490 * This field is valid only on the first BD of a packet.
1492 #define TX_BD_SHORT_FLAGS_LHINT_MASK UINT32_C(0x6000)
1493 #define TX_BD_SHORT_FLAGS_LHINT_SFT 13
1494 /* indicates packet length < 512B */
1495 #define TX_BD_SHORT_FLAGS_LHINT_LT512 (UINT32_C(0x0) << 13)
1496 /* indicates 512 <= packet length < 1KB */
1497 #define TX_BD_SHORT_FLAGS_LHINT_LT1K (UINT32_C(0x1) << 13)
1498 /* indicates 1KB <= packet length < 2KB */
1499 #define TX_BD_SHORT_FLAGS_LHINT_LT2K (UINT32_C(0x2) << 13)
1500 /* indicates packet length >= 2KB */
1501 #define TX_BD_SHORT_FLAGS_LHINT_GTE2K (UINT32_C(0x3) << 13)
1502 #define TX_BD_SHORT_FLAGS_LHINT_LAST \
1503 TX_BD_SHORT_FLAGS_LHINT_GTE2K
1505 * If set to 1, the device immediately updates the Send Consumer
1506 * Index after the buffer associated with this descriptor has
1507 * been transferred via DMA to NIC memory from host memory. An
1508 * interrupt may or may not be generated according to the state
1509 * of the interrupt avoidance mechanisms. If this bit
1510 * is set to 0, then the Consumer Index is only updated as soon
1511 * as one of the host interrupt coalescing conditions has been met.
1513 * This bit must be valid on the first BD of a packet.
1515 #define TX_BD_SHORT_FLAGS_COAL_NOW UINT32_C(0x8000)
1517 * This is the length of the host physical buffer this BD describes
1520 * This field must be valid on all BDs of a packet.
1524 * The opaque data field is pass through to the completion and can be
1525 * used for any data that the driver wants to associate with the
1528 * This field must be valid on the first BD of a packet.
1532 * This is the host physical address for the portion of the packet
1533 * described by this TX BD.
1535 * This value must be valid on all BDs of a packet.
1538 } __attribute__((packed));
1540 /* tx_bd_long (size:128b/16B) */
1542 /* This value identifies the type of buffer descriptor. */
1543 uint16_t flags_type;
1545 * This value indicates the type of buffer descriptor.
1548 #define TX_BD_LONG_TYPE_MASK UINT32_C(0x3f)
1549 #define TX_BD_LONG_TYPE_SFT 0
1551 * Indicates that this BD is 32B long and is used for
1552 * normal L2 packet transmission.
1554 #define TX_BD_LONG_TYPE_TX_BD_LONG UINT32_C(0x10)
1555 #define TX_BD_LONG_TYPE_LAST TX_BD_LONG_TYPE_TX_BD_LONG
1557 * All bits in this field must be valid on the first BD of a packet.
1558 * Only the packet_end bit must be valid for the remaining BDs
1561 #define TX_BD_LONG_FLAGS_MASK UINT32_C(0xffc0)
1562 #define TX_BD_LONG_FLAGS_SFT 6
1564 * If set to 1, the packet ends with the data in the buffer
1565 * pointed to by this descriptor. This flag must be
1566 * valid on every BD.
1568 #define TX_BD_LONG_FLAGS_PACKET_END UINT32_C(0x40)
1570 * If set to 1, the device will not generate a completion for
1571 * this transmit packet unless there is an error in it's
1574 * is set to 0, then the packet will be completed normally.
1576 * This bit must be valid only on the first BD of a packet.
1578 #define TX_BD_LONG_FLAGS_NO_CMPL UINT32_C(0x80)
1580 * This value indicates how many 16B BD locations are consumed
1581 * in the ring by this packet.
1582 * A value of 1 indicates that this BD is the only BD (and that
1583 * the it is a short BD). A value
1584 * of 3 indicates either 3 short BDs or 1 long BD and one short
1585 * BD in the packet. A value of 0 indicates
1586 * that there are 32 BD locations in the packet (the maximum).
1588 * This field is valid only on the first BD of a packet.
1590 #define TX_BD_LONG_FLAGS_BD_CNT_MASK UINT32_C(0x1f00)
1591 #define TX_BD_LONG_FLAGS_BD_CNT_SFT 8
1593 * This value is a hint for the length of the entire packet.
1594 * It is used by the chip to optimize internal processing.
1596 * The packet will be dropped if the hint is too short.
1598 * This field is valid only on the first BD of a packet.
1600 #define TX_BD_LONG_FLAGS_LHINT_MASK UINT32_C(0x6000)
1601 #define TX_BD_LONG_FLAGS_LHINT_SFT 13
1602 /* indicates packet length < 512B */
1603 #define TX_BD_LONG_FLAGS_LHINT_LT512 (UINT32_C(0x0) << 13)
1604 /* indicates 512 <= packet length < 1KB */
1605 #define TX_BD_LONG_FLAGS_LHINT_LT1K (UINT32_C(0x1) << 13)
1606 /* indicates 1KB <= packet length < 2KB */
1607 #define TX_BD_LONG_FLAGS_LHINT_LT2K (UINT32_C(0x2) << 13)
1608 /* indicates packet length >= 2KB */
1609 #define TX_BD_LONG_FLAGS_LHINT_GTE2K (UINT32_C(0x3) << 13)
1610 #define TX_BD_LONG_FLAGS_LHINT_LAST TX_BD_LONG_FLAGS_LHINT_GTE2K
1612 * If set to 1, the device immediately updates the Send Consumer
1613 * Index after the buffer associated with this descriptor has
1614 * been transferred via DMA to NIC memory from host memory. An
1615 * interrupt may or may not be generated according to the state
1616 * of the interrupt avoidance mechanisms. If this bit
1617 * is set to 0, then the Consumer Index is only updated as soon
1618 * as one of the host interrupt coalescing conditions has been met.
1620 * This bit must be valid on the first BD of a packet.
1622 #define TX_BD_LONG_FLAGS_COAL_NOW UINT32_C(0x8000)
1624 * This is the length of the host physical buffer this BD describes
1627 * This field must be valid on all BDs of a packet.
1631 * The opaque data field is pass through to the completion and can be
1632 * used for any data that the driver wants to associate with the
1635 * This field must be valid on the first BD of a packet.
1639 * This is the host physical address for the portion of the packet
1640 * described by this TX BD.
1642 * This value must be valid on all BDs of a packet.
1645 } __attribute__((packed));
1647 /* Last 16 bytes of tx_bd_long. */
1648 /* tx_bd_long_hi (size:128b/16B) */
1649 struct tx_bd_long_hi {
1651 * All bits in this field must be valid on the first BD of a packet.
1652 * Their value on other BDs of the packet will be ignored.
1656 * If set to 1, the controller replaces the TCP/UPD checksum
1657 * fields of normal TCP/UPD checksum, or the inner TCP/UDP
1658 * checksum field of the encapsulated TCP/UDP packets with the
1659 * hardware calculated TCP/UDP checksum for the packet associated
1660 * with this descriptor. The flag is ignored if the LSO flag is set.
1662 * This bit must be valid on the first BD of a packet.
1664 #define TX_BD_LONG_LFLAGS_TCP_UDP_CHKSUM UINT32_C(0x1)
1666 * If set to 1, the controller replaces the IP checksum of the
1667 * normal packets, or the inner IP checksum of the encapsulated
1668 * packets with the hardware calculated IP checksum for the
1669 * packet associated with this descriptor.
1671 * This bit must be valid on the first BD of a packet.
1673 #define TX_BD_LONG_LFLAGS_IP_CHKSUM UINT32_C(0x2)
1675 * If set to 1, the controller will not append an Ethernet CRC
1676 * to the end of the frame.
1678 * This bit must be valid on the first BD of a packet.
1680 * Packet must be 64B or longer when this flag is set. It is not
1681 * useful to use this bit with any form of TX offload such as
1682 * CSO or LSO. The intent is that the packet from the host already
1683 * has a valid Ethernet CRC on the packet.
1685 #define TX_BD_LONG_LFLAGS_NOCRC UINT32_C(0x4)
1687 * If set to 1, the device will record the time at which the packet
1688 * was actually transmitted at the TX MAC.
1690 * This bit must be valid on the first BD of a packet.
1692 #define TX_BD_LONG_LFLAGS_STAMP UINT32_C(0x8)
1694 * If set to 1, The controller replaces the tunnel IP checksum
1695 * field with hardware calculated IP checksum for the IP header
1696 * of the packet associated with this descriptor.
1698 * For outer UDP checksum, global outer UDP checksum TE_NIC register
1699 * needs to be enabled. If the global outer UDP checksum TE_NIC register
1700 * bit is set, outer UDP checksum will be calculated for the following
1702 * 1. Packets with tcp_udp_chksum flag set to offload checksum for inner
1703 * packet AND the inner packet is TCP/UDP. If the inner packet is ICMP for
1704 * example (non-TCP/UDP), even if the tcp_udp_chksum is set, the outer UDP
1705 * checksum will not be calculated.
1706 * 2. Packets with lso flag set which implies inner TCP checksum calculation
1707 * as part of LSO operation.
1709 #define TX_BD_LONG_LFLAGS_T_IP_CHKSUM UINT32_C(0x10)
1711 * If set to 1, the device will treat this packet with LSO(Large
1712 * Send Offload) processing for both normal or encapsulated
1713 * packets, which is a form of TCP segmentation. When this bit
1714 * is 1, the hdr_size and mss fields must be valid. The driver
1715 * doesn't need to set t_ip_chksum, ip_chksum, and tcp_udp_chksum
1716 * flags since the controller will replace the appropriate
1717 * checksum fields for segmented packets.
1719 * When this bit is 1, the hdr_size and mss fields must be valid.
1721 #define TX_BD_LONG_LFLAGS_LSO UINT32_C(0x20)
1723 * If set to zero when LSO is '1', then the IPID will be treated
1724 * as a 16b number and will be wrapped if it exceeds a value of
1727 * If set to one when LSO is '1', then the IPID will be treated
1728 * as a 15b number and will be wrapped if it exceeds a value 0f
1731 #define TX_BD_LONG_LFLAGS_IPID_FMT UINT32_C(0x40)
1733 * If set to zero when LSO is '1', then the IPID of the tunnel
1734 * IP header will not be modified during LSO operations.
1736 * If set to one when LSO is '1', then the IPID of the tunnel
1737 * IP header will be incremented for each subsequent segment of an
1740 * The flag is ignored if the LSO packet is a normal (non-tunneled)
1743 #define TX_BD_LONG_LFLAGS_T_IPID UINT32_C(0x80)
1745 * If set to '1', then the RoCE ICRC will be appended to the
1746 * packet. Packet must be a valid RoCE format packet.
1748 #define TX_BD_LONG_LFLAGS_ROCE_CRC UINT32_C(0x100)
1750 * If set to '1', then the FCoE CRC will be appended to the
1751 * packet. Packet must be a valid FCoE format packet.
1753 #define TX_BD_LONG_LFLAGS_FCOE_CRC UINT32_C(0x200)
1756 * When LSO is '1', this field must contain the offset of the
1757 * TCP payload from the beginning of the packet in as
1758 * 16b words. In case of encapsulated/tunneling packet, this field
1759 * contains the offset of the inner TCP payload from beginning of the
1760 * packet as 16-bit words.
1762 * This value must be valid on the first BD of a packet.
1764 #define TX_BD_LONG_HDR_SIZE_MASK UINT32_C(0x1ff)
1765 #define TX_BD_LONG_HDR_SIZE_SFT 0
1768 * This is the MSS value that will be used to do the LSO processing.
1769 * The value is the length in bytes of the TCP payload for each
1770 * segment generated by the LSO operation.
1772 * This value must be valid on the first BD of a packet.
1774 #define TX_BD_LONG_MSS_MASK UINT32_C(0x7fff)
1775 #define TX_BD_LONG_MSS_SFT 0
1778 * This value selects a CFA action to perform on the packet.
1779 * Set this value to zero if no CFA action is desired.
1781 * This value must be valid on the first BD of a packet.
1783 uint16_t cfa_action;
1785 * This value is action meta-data that defines CFA edit operations
1786 * that are done in addition to any action editing.
1789 /* When key=1, This is the VLAN tag VID value. */
1790 #define TX_BD_LONG_CFA_META_VLAN_VID_MASK UINT32_C(0xfff)
1791 #define TX_BD_LONG_CFA_META_VLAN_VID_SFT 0
1792 /* When key=1, This is the VLAN tag DE value. */
1793 #define TX_BD_LONG_CFA_META_VLAN_DE UINT32_C(0x1000)
1794 /* When key=1, This is the VLAN tag PRI value. */
1795 #define TX_BD_LONG_CFA_META_VLAN_PRI_MASK UINT32_C(0xe000)
1796 #define TX_BD_LONG_CFA_META_VLAN_PRI_SFT 13
1797 /* When key=1, This is the VLAN tag TPID select value. */
1798 #define TX_BD_LONG_CFA_META_VLAN_TPID_MASK UINT32_C(0x70000)
1799 #define TX_BD_LONG_CFA_META_VLAN_TPID_SFT 16
1801 #define TX_BD_LONG_CFA_META_VLAN_TPID_TPID88A8 (UINT32_C(0x0) << 16)
1803 #define TX_BD_LONG_CFA_META_VLAN_TPID_TPID8100 (UINT32_C(0x1) << 16)
1805 #define TX_BD_LONG_CFA_META_VLAN_TPID_TPID9100 (UINT32_C(0x2) << 16)
1807 #define TX_BD_LONG_CFA_META_VLAN_TPID_TPID9200 (UINT32_C(0x3) << 16)
1809 #define TX_BD_LONG_CFA_META_VLAN_TPID_TPID9300 (UINT32_C(0x4) << 16)
1810 /* Value programmed in CFA VLANTPID register. */
1811 #define TX_BD_LONG_CFA_META_VLAN_TPID_TPIDCFG (UINT32_C(0x5) << 16)
1812 #define TX_BD_LONG_CFA_META_VLAN_TPID_LAST \
1813 TX_BD_LONG_CFA_META_VLAN_TPID_TPIDCFG
1814 /* When key=1, This is the VLAN tag TPID select value. */
1815 #define TX_BD_LONG_CFA_META_VLAN_RESERVED_MASK UINT32_C(0xff80000)
1816 #define TX_BD_LONG_CFA_META_VLAN_RESERVED_SFT 19
1818 * This field identifies the type of edit to be performed
1821 * This value must be valid on the first BD of a packet.
1823 #define TX_BD_LONG_CFA_META_KEY_MASK UINT32_C(0xf0000000)
1824 #define TX_BD_LONG_CFA_META_KEY_SFT 28
1826 #define TX_BD_LONG_CFA_META_KEY_NONE (UINT32_C(0x0) << 28)
1828 * - meta[17:16] - TPID select value (0 = 0x8100).
1829 * - meta[15:12] - PRI/DE value.
1830 * - meta[11:0] - VID value.
1832 #define TX_BD_LONG_CFA_META_KEY_VLAN_TAG (UINT32_C(0x1) << 28)
1833 #define TX_BD_LONG_CFA_META_KEY_LAST \
1834 TX_BD_LONG_CFA_META_KEY_VLAN_TAG
1835 } __attribute__((packed));
1838 * This structure is used to inform the NIC of packet data that needs to be
1839 * transmitted with additional processing that requires extra data such as
1840 * VLAN insertion plus attached inline data. This BD type may be used to
1841 * improve latency for small packets needing the additional extended features
1842 * supported by long BDs.
1844 /* tx_bd_long_inline (size:256b/32B) */
1845 struct tx_bd_long_inline {
1846 uint16_t flags_type;
1847 /* This value identifies the type of buffer descriptor. */
1848 #define TX_BD_LONG_INLINE_TYPE_MASK UINT32_C(0x3f)
1849 #define TX_BD_LONG_INLINE_TYPE_SFT 0
1851 * This type of BD is 32B long and is used for inline L2 packet
1854 #define TX_BD_LONG_INLINE_TYPE_TX_BD_LONG_INLINE UINT32_C(0x11)
1855 #define TX_BD_LONG_INLINE_TYPE_LAST \
1856 TX_BD_LONG_INLINE_TYPE_TX_BD_LONG_INLINE
1858 * All bits in this field may be set on the first BD of a packet.
1859 * Only the packet_end bit may be set in non-first BDs.
1861 #define TX_BD_LONG_INLINE_FLAGS_MASK UINT32_C(0xffc0)
1862 #define TX_BD_LONG_INLINE_FLAGS_SFT 6
1864 * If set to 1, the packet ends with the data in the buffer
1865 * pointed to by this descriptor. This flag must be
1866 * valid on every BD.
1868 #define TX_BD_LONG_INLINE_FLAGS_PACKET_END UINT32_C(0x40)
1870 * If set to 1, the device will not generate a completion for
1871 * this transmit packet unless there is an error in its processing.
1872 * If this bit is set to 0, then the packet will be completed
1875 * This bit may be set only on the first BD of a packet.
1877 #define TX_BD_LONG_INLINE_FLAGS_NO_CMPL UINT32_C(0x80)
1879 * This value indicates how many 16B BD locations are consumed
1880 * in the ring by this packet, including the BD and inline
1883 #define TX_BD_LONG_INLINE_FLAGS_BD_CNT_MASK UINT32_C(0x1f00)
1884 #define TX_BD_LONG_INLINE_FLAGS_BD_CNT_SFT 8
1885 /* This field is deprecated. */
1886 #define TX_BD_LONG_INLINE_FLAGS_LHINT_MASK UINT32_C(0x6000)
1887 #define TX_BD_LONG_INLINE_FLAGS_LHINT_SFT 13
1889 * If set to 1, the device immediately updates the Send Consumer
1890 * Index after the buffer associated with this descriptor has
1891 * been transferred via DMA to NIC memory from host memory. An
1892 * interrupt may or may not be generated according to the state
1893 * of the interrupt avoidance mechanisms. If this bit
1894 * is set to 0, then the Consumer Index is only updated as soon
1895 * as one of the host interrupt coalescing conditions has been met.
1897 * This bit must be valid on the first BD of a packet.
1899 #define TX_BD_LONG_INLINE_FLAGS_COAL_NOW UINT32_C(0x8000)
1901 * This is the length of the inline data, not including BD length, in
1903 * The maximum value is 480.
1905 * This field must be valid on all BDs of a packet.
1909 * The opaque data field is passed through to the completion and can be
1910 * used for any data that the driver wants to associate with the transmit
1913 * This field must be valid on the first BD of a packet.
1918 * All bits in this field must be valid on the first BD of a packet.
1919 * Their value on other BDs of the packet is ignored.
1923 * If set to 1, the controller replaces the TCP/UPD checksum
1924 * fields of normal TCP/UPD checksum, or the inner TCP/UDP
1925 * checksum field of the encapsulated TCP/UDP packets with the
1926 * hardware calculated TCP/UDP checksum for the packet associated
1927 * with this descriptor. The flag is ignored if the LSO flag is set.
1929 #define TX_BD_LONG_INLINE_LFLAGS_TCP_UDP_CHKSUM UINT32_C(0x1)
1931 * If set to 1, the controller replaces the IP checksum of the
1932 * normal packets, or the inner IP checksum of the encapsulated
1933 * packets with the hardware calculated IP checksum for the
1934 * packet associated with this descriptor.
1936 #define TX_BD_LONG_INLINE_LFLAGS_IP_CHKSUM UINT32_C(0x2)
1938 * If set to 1, the controller will not append an Ethernet CRC
1939 * to the end of the frame.
1941 * Packet must be 64B or longer when this flag is set. It is not
1942 * useful to use this bit with any form of TX offload such as
1943 * CSO or LSO. The intent is that the packet from the host already
1944 * has a valid Ethernet CRC on the packet.
1946 #define TX_BD_LONG_INLINE_LFLAGS_NOCRC UINT32_C(0x4)
1948 * If set to 1, the device will record the time at which the packet
1949 * was actually transmitted at the TX MAC.
1951 #define TX_BD_LONG_INLINE_LFLAGS_STAMP UINT32_C(0x8)
1953 * If set to 1, the controller replaces the tunnel IP checksum
1954 * field with hardware calculated IP checksum for the IP header
1955 * of the packet associated with this descriptor. The hardware
1956 * updates an outer UDP checksum if it is non-zero.
1958 #define TX_BD_LONG_INLINE_LFLAGS_T_IP_CHKSUM UINT32_C(0x10)
1960 * This bit must be 0 for BDs of this type. LSO is not supported with
1963 #define TX_BD_LONG_INLINE_LFLAGS_LSO UINT32_C(0x20)
1964 /* Since LSO is not supported with inline BDs, this bit is not used. */
1965 #define TX_BD_LONG_INLINE_LFLAGS_IPID_FMT UINT32_C(0x40)
1966 /* Since LSO is not supported with inline BDs, this bit is not used. */
1967 #define TX_BD_LONG_INLINE_LFLAGS_T_IPID UINT32_C(0x80)
1969 * If set to '1', then the RoCE ICRC will be appended to the
1970 * packet. Packet must be a valid RoCE format packet.
1972 #define TX_BD_LONG_INLINE_LFLAGS_ROCE_CRC UINT32_C(0x100)
1974 * If set to '1', then the FCoE CRC will be appended to the
1975 * packet. Packet must be a valid FCoE format packet.
1977 #define TX_BD_LONG_INLINE_LFLAGS_FCOE_CRC UINT32_C(0x200)
1982 * This value selects a CFA action to perform on the packet.
1983 * Set this value to zero if no CFA action is desired.
1985 * This value must be valid on the first BD of a packet.
1987 uint16_t cfa_action;
1989 * This value is action meta-data that defines CFA edit operations
1990 * that are done in addition to any action editing.
1993 /* When key = 1, this is the VLAN tag VID value. */
1994 #define TX_BD_LONG_INLINE_CFA_META_VLAN_VID_MASK UINT32_C(0xfff)
1995 #define TX_BD_LONG_INLINE_CFA_META_VLAN_VID_SFT 0
1996 /* When key = 1, this is the VLAN tag DE value. */
1997 #define TX_BD_LONG_INLINE_CFA_META_VLAN_DE UINT32_C(0x1000)
1998 /* When key = 1, this is the VLAN tag PRI value. */
1999 #define TX_BD_LONG_INLINE_CFA_META_VLAN_PRI_MASK UINT32_C(0xe000)
2000 #define TX_BD_LONG_INLINE_CFA_META_VLAN_PRI_SFT 13
2001 /* When key = 1, this is the VLAN tag TPID select value. */
2002 #define TX_BD_LONG_INLINE_CFA_META_VLAN_TPID_MASK UINT32_C(0x70000)
2003 #define TX_BD_LONG_INLINE_CFA_META_VLAN_TPID_SFT 16
2005 #define TX_BD_LONG_INLINE_CFA_META_VLAN_TPID_TPID88A8 \
2006 (UINT32_C(0x0) << 16)
2008 #define TX_BD_LONG_INLINE_CFA_META_VLAN_TPID_TPID8100 \
2009 (UINT32_C(0x1) << 16)
2011 #define TX_BD_LONG_INLINE_CFA_META_VLAN_TPID_TPID9100 \
2012 (UINT32_C(0x2) << 16)
2014 #define TX_BD_LONG_INLINE_CFA_META_VLAN_TPID_TPID9200 \
2015 (UINT32_C(0x3) << 16)
2017 #define TX_BD_LONG_INLINE_CFA_META_VLAN_TPID_TPID9300 \
2018 (UINT32_C(0x4) << 16)
2019 /* Value programmed in CFA VLANTPID register. */
2020 #define TX_BD_LONG_INLINE_CFA_META_VLAN_TPID_TPIDCFG \
2021 (UINT32_C(0x5) << 16)
2022 #define TX_BD_LONG_INLINE_CFA_META_VLAN_TPID_LAST \
2023 TX_BD_LONG_INLINE_CFA_META_VLAN_TPID_TPIDCFG
2024 #define TX_BD_LONG_INLINE_CFA_META_VLAN_RESERVED_MASK \
2026 #define TX_BD_LONG_INLINE_CFA_META_VLAN_RESERVED_SFT 19
2028 * This field identifies the type of edit to be performed
2031 * This value must be valid on the first BD of a packet.
2033 #define TX_BD_LONG_INLINE_CFA_META_KEY_MASK \
2034 UINT32_C(0xf0000000)
2035 #define TX_BD_LONG_INLINE_CFA_META_KEY_SFT 28
2037 #define TX_BD_LONG_INLINE_CFA_META_KEY_NONE \
2038 (UINT32_C(0x0) << 28)
2040 * - meta[17:16] - TPID select value (0 = 0x8100).
2041 * - meta[15:12] - PRI/DE value.
2042 * - meta[11:0] - VID value.
2044 #define TX_BD_LONG_INLINE_CFA_META_KEY_VLAN_TAG \
2045 (UINT32_C(0x1) << 28)
2046 #define TX_BD_LONG_INLINE_CFA_META_KEY_LAST \
2047 TX_BD_LONG_INLINE_CFA_META_KEY_VLAN_TAG
2048 } __attribute__((packed));
2050 /* tx_bd_empty (size:128b/16B) */
2051 struct tx_bd_empty {
2052 /* This value identifies the type of buffer descriptor. */
2054 #define TX_BD_EMPTY_TYPE_MASK UINT32_C(0x3f)
2055 #define TX_BD_EMPTY_TYPE_SFT 0
2057 * Indicates that this BD is 1BB long and is an empty
2058 * TX BD. Not valid for use by the driver.
2060 #define TX_BD_EMPTY_TYPE_TX_BD_EMPTY UINT32_C(0x1)
2061 #define TX_BD_EMPTY_TYPE_LAST TX_BD_EMPTY_TYPE_TX_BD_EMPTY
2062 uint8_t unused_1[3];
2064 uint8_t unused_3[3];
2065 uint8_t unused_4[8];
2066 } __attribute__((packed));
2068 /* rx_prod_pkt_bd (size:128b/16B) */
2069 struct rx_prod_pkt_bd {
2070 /* This value identifies the type of buffer descriptor. */
2071 uint16_t flags_type;
2072 /* This value identifies the type of buffer descriptor. */
2073 #define RX_PROD_PKT_BD_TYPE_MASK UINT32_C(0x3f)
2074 #define RX_PROD_PKT_BD_TYPE_SFT 0
2076 * Indicates that this BD is 16B long and is an RX Producer
2077 * (ie. empty) buffer descriptor.
2079 #define RX_PROD_PKT_BD_TYPE_RX_PROD_PKT UINT32_C(0x4)
2080 #define RX_PROD_PKT_BD_TYPE_LAST \
2081 RX_PROD_PKT_BD_TYPE_RX_PROD_PKT
2082 #define RX_PROD_PKT_BD_FLAGS_MASK UINT32_C(0xffc0)
2083 #define RX_PROD_PKT_BD_FLAGS_SFT 6
2085 * If set to 1, the packet will be placed at the address plus
2086 * 2B. The 2 Bytes of padding will be written as zero.
2088 #define RX_PROD_PKT_BD_FLAGS_SOP_PAD UINT32_C(0x40)
2090 * If set to 1, the packet write will be padded out to the
2091 * nearest cache-line with zero value padding.
2093 #define RX_PROD_PKT_BD_FLAGS_EOP_PAD UINT32_C(0x80)
2095 * This value is the number of additional buffers in the ring that
2096 * describe the buffer space to be consumed for the this packet.
2097 * If the value is zero, then the packet must fit within the
2098 * space described by this BD. If this value is 1 or more, it
2099 * indicates how many additional "buffer" BDs are in the ring
2100 * immediately following this BD to be used for the same
2103 * Even if the packet to be placed does not need all the
2104 * additional buffers, they will be consumed anyway.
2106 #define RX_PROD_PKT_BD_FLAGS_BUFFERS_MASK UINT32_C(0x300)
2107 #define RX_PROD_PKT_BD_FLAGS_BUFFERS_SFT 8
2109 * This is the length in Bytes of the host physical buffer where
2110 * data for the packet may be placed in host memory.
2114 * The opaque data field is pass through to the completion and can be
2115 * used for any data that the driver wants to associate with this
2116 * receive buffer set.
2120 * This is the host physical address where data for the packet may
2121 * by placed in host memory.
2124 } __attribute__((packed));
2126 /* rx_prod_bfr_bd (size:128b/16B) */
2127 struct rx_prod_bfr_bd {
2128 /* This value identifies the type of buffer descriptor. */
2129 uint16_t flags_type;
2130 /* This value identifies the type of buffer descriptor. */
2131 #define RX_PROD_BFR_BD_TYPE_MASK UINT32_C(0x3f)
2132 #define RX_PROD_BFR_BD_TYPE_SFT 0
2134 * Indicates that this BD is 16B long and is an RX
2135 * Producer Buffer BD.
2137 #define RX_PROD_BFR_BD_TYPE_RX_PROD_BFR UINT32_C(0x5)
2138 #define RX_PROD_BFR_BD_TYPE_LAST RX_PROD_BFR_BD_TYPE_RX_PROD_BFR
2139 #define RX_PROD_BFR_BD_FLAGS_MASK UINT32_C(0xffc0)
2140 #define RX_PROD_BFR_BD_FLAGS_SFT 6
2142 * This is the length in Bytes of the host physical buffer where
2143 * data for the packet may be placed in host memory.
2146 /* This field is not used. */
2149 * This is the host physical address where data for the packet may
2150 * by placed in host memory.
2153 } __attribute__((packed));
2155 /* rx_prod_agg_bd (size:128b/16B) */
2156 struct rx_prod_agg_bd {
2157 /* This value identifies the type of buffer descriptor. */
2158 uint16_t flags_type;
2159 /* This value identifies the type of buffer descriptor. */
2160 #define RX_PROD_AGG_BD_TYPE_MASK UINT32_C(0x3f)
2161 #define RX_PROD_AGG_BD_TYPE_SFT 0
2163 * Indicates that this BD is 16B long and is an
2164 * RX Producer Assembly Buffer Descriptor.
2166 #define RX_PROD_AGG_BD_TYPE_RX_PROD_AGG UINT32_C(0x6)
2167 #define RX_PROD_AGG_BD_TYPE_LAST \
2168 RX_PROD_AGG_BD_TYPE_RX_PROD_AGG
2169 #define RX_PROD_AGG_BD_FLAGS_MASK UINT32_C(0xffc0)
2170 #define RX_PROD_AGG_BD_FLAGS_SFT 6
2172 * If set to 1, the packet write will be padded out to the
2173 * nearest cache-line with zero value padding.
2175 #define RX_PROD_AGG_BD_FLAGS_EOP_PAD UINT32_C(0x40)
2177 * This is the length in Bytes of the host physical buffer where
2178 * data for the packet may be placed in host memory.
2182 * The opaque data field is pass through to the completion and can be
2183 * used for any data that the driver wants to associate with this
2184 * receive assembly buffer.
2188 * This is the host physical address where data for the packet may
2189 * by placed in host memory.
2192 } __attribute__((packed));
2194 /* cmpl_base (size:128b/16B) */
2198 * This field indicates the exact type of the completion.
2199 * By convention, the LSB identifies the length of the
2200 * record in 16B units. Even values indicate 16B
2201 * records. Odd values indicate 32B
2204 #define CMPL_BASE_TYPE_MASK UINT32_C(0x3f)
2205 #define CMPL_BASE_TYPE_SFT 0
2208 * Completion of TX packet. Length = 16B
2210 #define CMPL_BASE_TYPE_TX_L2 UINT32_C(0x0)
2213 * Completion of and L2 RX packet. Length = 32B
2215 #define CMPL_BASE_TYPE_RX_L2 UINT32_C(0x11)
2217 * RX Aggregation Buffer completion :
2218 * Completion of an L2 aggregation buffer in support of
2219 * TPA, HDS, or Jumbo packet completion. Length = 16B
2221 #define CMPL_BASE_TYPE_RX_AGG UINT32_C(0x12)
2223 * RX L2 TPA Start Completion:
2224 * Completion at the beginning of a TPA operation.
2227 #define CMPL_BASE_TYPE_RX_TPA_START UINT32_C(0x13)
2229 * RX L2 TPA End Completion:
2230 * Completion at the end of a TPA operation.
2233 #define CMPL_BASE_TYPE_RX_TPA_END UINT32_C(0x15)
2235 * Statistics Ejection Completion:
2236 * Completion of statistics data ejection buffer.
2239 #define CMPL_BASE_TYPE_STAT_EJECT UINT32_C(0x1a)
2241 * HWRM Command Completion:
2242 * Completion of an HWRM command.
2244 #define CMPL_BASE_TYPE_HWRM_DONE UINT32_C(0x20)
2245 /* Forwarded HWRM Request */
2246 #define CMPL_BASE_TYPE_HWRM_FWD_REQ UINT32_C(0x22)
2247 /* Forwarded HWRM Response */
2248 #define CMPL_BASE_TYPE_HWRM_FWD_RESP UINT32_C(0x24)
2249 /* HWRM Asynchronous Event Information */
2250 #define CMPL_BASE_TYPE_HWRM_ASYNC_EVENT UINT32_C(0x2e)
2251 /* CQ Notification */
2252 #define CMPL_BASE_TYPE_CQ_NOTIFICATION UINT32_C(0x30)
2253 /* SRQ Threshold Event */
2254 #define CMPL_BASE_TYPE_SRQ_EVENT UINT32_C(0x32)
2255 /* DBQ Threshold Event */
2256 #define CMPL_BASE_TYPE_DBQ_EVENT UINT32_C(0x34)
2257 /* QP Async Notification */
2258 #define CMPL_BASE_TYPE_QP_EVENT UINT32_C(0x38)
2259 /* Function Async Notification */
2260 #define CMPL_BASE_TYPE_FUNC_EVENT UINT32_C(0x3a)
2261 #define CMPL_BASE_TYPE_LAST CMPL_BASE_TYPE_FUNC_EVENT
2267 * This value is written by the NIC such that it will be different
2268 * for each pass through the completion queue. The even passes
2269 * will write 1. The odd passes will write 0.
2272 #define CMPL_BASE_V UINT32_C(0x1)
2273 #define CMPL_BASE_INFO3_MASK UINT32_C(0xfffffffe)
2274 #define CMPL_BASE_INFO3_SFT 1
2277 } __attribute__((packed));
2279 /* tx_cmpl (size:128b/16B) */
2281 uint16_t flags_type;
2283 * This field indicates the exact type of the completion.
2284 * By convention, the LSB identifies the length of the
2285 * record in 16B units. Even values indicate 16B
2286 * records. Odd values indicate 32B
2289 #define TX_CMPL_TYPE_MASK UINT32_C(0x3f)
2290 #define TX_CMPL_TYPE_SFT 0
2293 * Completion of TX packet. Length = 16B
2295 #define TX_CMPL_TYPE_TX_L2 UINT32_C(0x0)
2296 #define TX_CMPL_TYPE_LAST TX_CMPL_TYPE_TX_L2
2297 #define TX_CMPL_FLAGS_MASK UINT32_C(0xffc0)
2298 #define TX_CMPL_FLAGS_SFT 6
2300 * When this bit is '1', it indicates a packet that has an
2301 * error of some type. Type of error is indicated in
2304 #define TX_CMPL_FLAGS_ERROR UINT32_C(0x40)
2306 * When this bit is '1', it indicates that the packet completed
2307 * was transmitted using the push acceleration data provided
2308 * by the driver. When this bit is '0', it indicates that the
2309 * packet had not push acceleration data written or was executed
2310 * as a normal packet even though push data was provided.
2312 #define TX_CMPL_FLAGS_PUSH UINT32_C(0x80)
2313 /* unused1 is 16 b */
2316 * This is a copy of the opaque field from the first TX BD of this
2317 * transmitted packet.
2322 * This value is written by the NIC such that it will be different
2323 * for each pass through the completion queue. The even passes
2324 * will write 1. The odd passes will write 0.
2326 #define TX_CMPL_V UINT32_C(0x1)
2327 #define TX_CMPL_ERRORS_MASK UINT32_C(0xfffe)
2328 #define TX_CMPL_ERRORS_SFT 1
2330 * This error indicates that there was some sort of problem
2331 * with the BDs for the packet.
2333 #define TX_CMPL_ERRORS_BUFFER_ERROR_MASK UINT32_C(0xe)
2334 #define TX_CMPL_ERRORS_BUFFER_ERROR_SFT 1
2336 #define TX_CMPL_ERRORS_BUFFER_ERROR_NO_ERROR (UINT32_C(0x0) << 1)
2339 * BDs were not formatted correctly.
2341 #define TX_CMPL_ERRORS_BUFFER_ERROR_BAD_FMT (UINT32_C(0x2) << 1)
2342 #define TX_CMPL_ERRORS_BUFFER_ERROR_LAST \
2343 TX_CMPL_ERRORS_BUFFER_ERROR_BAD_FMT
2345 * When this bit is '1', it indicates that the length of
2346 * the packet was zero. No packet was transmitted.
2348 #define TX_CMPL_ERRORS_ZERO_LENGTH_PKT UINT32_C(0x10)
2350 * When this bit is '1', it indicates that the packet
2351 * was longer than the programmed limit in TDI. No
2352 * packet was transmitted.
2354 #define TX_CMPL_ERRORS_EXCESSIVE_BD_LENGTH UINT32_C(0x20)
2356 * When this bit is '1', it indicates that one or more of the
2357 * BDs associated with this packet generated a PCI error.
2358 * This probably means the address was not valid.
2360 #define TX_CMPL_ERRORS_DMA_ERROR UINT32_C(0x40)
2362 * When this bit is '1', it indicates that the packet was longer
2363 * than indicated by the hint. No packet was transmitted.
2365 #define TX_CMPL_ERRORS_HINT_TOO_SHORT UINT32_C(0x80)
2367 * When this bit is '1', it indicates that the packet was
2368 * dropped due to Poison TLP error on one or more of the
2369 * TLPs in the PXP completion.
2371 #define TX_CMPL_ERRORS_POISON_TLP_ERROR UINT32_C(0x100)
2372 /* unused2 is 16 b */
2374 /* unused3 is 32 b */
2376 } __attribute__((packed));
2378 /* rx_pkt_cmpl (size:128b/16B) */
2379 struct rx_pkt_cmpl {
2380 uint16_t flags_type;
2382 * This field indicates the exact type of the completion.
2383 * By convention, the LSB identifies the length of the
2384 * record in 16B units. Even values indicate 16B
2385 * records. Odd values indicate 32B
2388 #define RX_PKT_CMPL_TYPE_MASK UINT32_C(0x3f)
2389 #define RX_PKT_CMPL_TYPE_SFT 0
2392 * Completion of and L2 RX packet. Length = 32B
2394 #define RX_PKT_CMPL_TYPE_RX_L2 UINT32_C(0x11)
2395 #define RX_PKT_CMPL_TYPE_LAST RX_PKT_CMPL_TYPE_RX_L2
2396 #define RX_PKT_CMPL_FLAGS_MASK UINT32_C(0xffc0)
2397 #define RX_PKT_CMPL_FLAGS_SFT 6
2399 * When this bit is '1', it indicates a packet that has an
2400 * error of some type. Type of error is indicated in
2403 #define RX_PKT_CMPL_FLAGS_ERROR UINT32_C(0x40)
2404 /* This field indicates how the packet was placed in the buffer. */
2405 #define RX_PKT_CMPL_FLAGS_PLACEMENT_MASK UINT32_C(0x380)
2406 #define RX_PKT_CMPL_FLAGS_PLACEMENT_SFT 7
2409 * Packet was placed using normal algorithm.
2411 #define RX_PKT_CMPL_FLAGS_PLACEMENT_NORMAL (UINT32_C(0x0) << 7)
2414 * Packet was placed using jumbo algorithm.
2416 #define RX_PKT_CMPL_FLAGS_PLACEMENT_JUMBO (UINT32_C(0x1) << 7)
2418 * Header/Data Separation:
2419 * Packet was placed using Header/Data separation algorithm.
2420 * The separation location is indicated by the itype field.
2422 #define RX_PKT_CMPL_FLAGS_PLACEMENT_HDS (UINT32_C(0x2) << 7)
2423 #define RX_PKT_CMPL_FLAGS_PLACEMENT_LAST \
2424 RX_PKT_CMPL_FLAGS_PLACEMENT_HDS
2425 /* This bit is '1' if the RSS field in this completion is valid. */
2426 #define RX_PKT_CMPL_FLAGS_RSS_VALID UINT32_C(0x400)
2428 #define RX_PKT_CMPL_FLAGS_UNUSED UINT32_C(0x800)
2430 * This value indicates what the inner packet determined for the
2433 #define RX_PKT_CMPL_FLAGS_ITYPE_MASK UINT32_C(0xf000)
2434 #define RX_PKT_CMPL_FLAGS_ITYPE_SFT 12
2437 * Indicates that the packet type was not known.
2439 #define RX_PKT_CMPL_FLAGS_ITYPE_NOT_KNOWN \
2440 (UINT32_C(0x0) << 12)
2443 * Indicates that the packet was an IP packet, but further
2444 * classification was not possible.
2446 #define RX_PKT_CMPL_FLAGS_ITYPE_IP \
2447 (UINT32_C(0x1) << 12)
2450 * Indicates that the packet was IP and TCP.
2451 * This indicates that the payload_offset field is valid.
2453 #define RX_PKT_CMPL_FLAGS_ITYPE_TCP \
2454 (UINT32_C(0x2) << 12)
2457 * Indicates that the packet was IP and UDP.
2458 * This indicates that the payload_offset field is valid.
2460 #define RX_PKT_CMPL_FLAGS_ITYPE_UDP \
2461 (UINT32_C(0x3) << 12)
2464 * Indicates that the packet was recognized as a FCoE.
2465 * This also indicates that the payload_offset field is valid.
2467 #define RX_PKT_CMPL_FLAGS_ITYPE_FCOE \
2468 (UINT32_C(0x4) << 12)
2471 * Indicates that the packet was recognized as a RoCE.
2472 * This also indicates that the payload_offset field is valid.
2474 #define RX_PKT_CMPL_FLAGS_ITYPE_ROCE \
2475 (UINT32_C(0x5) << 12)
2478 * Indicates that the packet was recognized as ICMP.
2479 * This indicates that the payload_offset field is valid.
2481 #define RX_PKT_CMPL_FLAGS_ITYPE_ICMP \
2482 (UINT32_C(0x7) << 12)
2484 * PtP packet wo/timestamp:
2485 * Indicates that the packet was recognized as a PtP
2488 #define RX_PKT_CMPL_FLAGS_ITYPE_PTP_WO_TIMESTAMP \
2489 (UINT32_C(0x8) << 12)
2491 * PtP packet w/timestamp:
2492 * Indicates that the packet was recognized as a PtP
2493 * packet and that a timestamp was taken for the packet.
2495 #define RX_PKT_CMPL_FLAGS_ITYPE_PTP_W_TIMESTAMP \
2496 (UINT32_C(0x9) << 12)
2497 #define RX_PKT_CMPL_FLAGS_ITYPE_LAST \
2498 RX_PKT_CMPL_FLAGS_ITYPE_PTP_W_TIMESTAMP
2500 * This is the length of the data for the packet stored in the
2501 * buffer(s) identified by the opaque value. This includes
2502 * the packet BD and any associated buffer BDs. This does not include
2503 * the the length of any data places in aggregation BDs.
2507 * This is a copy of the opaque field from the RX BD this completion
2511 uint8_t agg_bufs_v1;
2513 * This value is written by the NIC such that it will be different
2514 * for each pass through the completion queue. The even passes
2515 * will write 1. The odd passes will write 0.
2517 #define RX_PKT_CMPL_V1 UINT32_C(0x1)
2519 * This value is the number of aggregation buffers that follow this
2520 * entry in the completion ring that are a part of this packet.
2521 * If the value is zero, then the packet is completely contained
2522 * in the buffer space provided for the packet in the RX ring.
2524 #define RX_PKT_CMPL_AGG_BUFS_MASK UINT32_C(0x3e)
2525 #define RX_PKT_CMPL_AGG_BUFS_SFT 1
2526 /* unused1 is 2 b */
2527 #define RX_PKT_CMPL_UNUSED1_MASK UINT32_C(0xc0)
2528 #define RX_PKT_CMPL_UNUSED1_SFT 6
2530 * This is the RSS hash type for the packet. The value is packed
2531 * {tuple_extrac_op[1:0],rss_profile_id[4:0],tuple_extrac_op[2]}.
2533 * The value of tuple_extrac_op provides the information about
2534 * what fields the hash was computed on.
2535 * * 0: The RSS hash was computed over source IP address,
2536 * destination IP address, source port, and destination port of inner
2537 * IP and TCP or UDP headers. Note: For non-tunneled packets,
2538 * the packet headers are considered inner packet headers for the RSS
2539 * hash computation purpose.
2540 * * 1: The RSS hash was computed over source IP address and destination
2541 * IP address of inner IP header. Note: For non-tunneled packets,
2542 * the packet headers are considered inner packet headers for the RSS
2543 * hash computation purpose.
2544 * * 2: The RSS hash was computed over source IP address,
2545 * destination IP address, source port, and destination port of
2546 * IP and TCP or UDP headers of outer tunnel headers.
2547 * Note: For non-tunneled packets, this value is not applicable.
2548 * * 3: The RSS hash was computed over source IP address and
2549 * destination IP address of IP header of outer tunnel headers.
2550 * Note: For non-tunneled packets, this value is not applicable.
2552 * Note that 4-tuples values listed above are applicable
2553 * for layer 4 protocols supported and enabled for RSS in the hardware,
2554 * HWRM firmware, and drivers. For example, if RSS hash is supported and
2555 * enabled for TCP traffic only, then the values of tuple_extract_op
2556 * corresponding to 4-tuples are only valid for TCP traffic.
2558 uint8_t rss_hash_type;
2560 * This value indicates the offset in bytes from the beginning of the packet
2561 * where the inner payload starts. This value is valid for TCP, UDP,
2562 * FCoE, and RoCE packets.
2564 * A value of zero indicates that header is 256B into the packet.
2566 uint8_t payload_offset;
2567 /* unused2 is 8 b */
2570 * This value is the RSS hash value calculated for the packet
2571 * based on the mode bits and key value in the VNIC.
2574 } __attribute__((packed));
2576 /* Last 16 bytes of rx_pkt_cmpl. */
2577 /* rx_pkt_cmpl_hi (size:128b/16B) */
2578 struct rx_pkt_cmpl_hi {
2581 * This indicates that the ip checksum was calculated for the
2582 * inner packet and that the ip_cs_error field indicates if there
2585 #define RX_PKT_CMPL_FLAGS2_IP_CS_CALC UINT32_C(0x1)
2587 * This indicates that the TCP, UDP or ICMP checksum was
2588 * calculated for the inner packet and that the l4_cs_error field
2589 * indicates if there was an error.
2591 #define RX_PKT_CMPL_FLAGS2_L4_CS_CALC UINT32_C(0x2)
2593 * This indicates that the ip checksum was calculated for the
2594 * tunnel header and that the t_ip_cs_error field indicates if there
2597 #define RX_PKT_CMPL_FLAGS2_T_IP_CS_CALC UINT32_C(0x4)
2599 * This indicates that the UDP checksum was
2600 * calculated for the tunnel packet and that the t_l4_cs_error field
2601 * indicates if there was an error.
2603 #define RX_PKT_CMPL_FLAGS2_T_L4_CS_CALC UINT32_C(0x8)
2604 /* This value indicates what format the metadata field is. */
2605 #define RX_PKT_CMPL_FLAGS2_META_FORMAT_MASK UINT32_C(0xf0)
2606 #define RX_PKT_CMPL_FLAGS2_META_FORMAT_SFT 4
2607 /* No metadata informtaion. Value is zero. */
2608 #define RX_PKT_CMPL_FLAGS2_META_FORMAT_NONE \
2609 (UINT32_C(0x0) << 4)
2611 * The metadata field contains the VLAN tag and TPID value.
2612 * - metadata[11:0] contains the vlan VID value.
2613 * - metadata[12] contains the vlan DE value.
2614 * - metadata[15:13] contains the vlan PRI value.
2615 * - metadata[31:16] contains the vlan TPID value.
2617 #define RX_PKT_CMPL_FLAGS2_META_FORMAT_VLAN \
2618 (UINT32_C(0x1) << 4)
2620 * If ext_meta_format is equal to 1, the metadata field
2621 * contains the lower 16b of the tunnel ID value, justified
2623 * - VXLAN = VNI[23:0] -> VXLAN Network ID
2624 * - Geneve (NGE) = VNI[23:0] a-> Virtual Network Identifier.
2625 * - NVGRE = TNI[23:0] -> Tenant Network ID
2626 * - GRE = KEY[31:0 -> key fieled with bit mask. zero if K = 0
2627 * - IPV4 = 0 (not populated)
2628 * - IPV6 = Flow Label[19:0]
2629 * - PPPoE = sessionID[15:0]
2630 * - MPLs = Outer label[19:0]
2631 * - UPAR = Selected[31:0] with bit mask
2633 #define RX_PKT_CMPL_FLAGS2_META_FORMAT_TUNNEL_ID \
2634 (UINT32_C(0x2) << 4)
2636 * if ext_meta_format is equal to 1, metadata field contains
2637 * 16b metadata from the prepended header (chdr_data).
2639 #define RX_PKT_CMPL_FLAGS2_META_FORMAT_CHDR_DATA \
2640 (UINT32_C(0x3) << 4)
2642 * If ext_meta_format is equal to 1, the metadata field contains
2643 * the outer_l3_offset, inner_l2_offset, inner_l3_offset and
2645 * - metadata[8:0] contains the outer_l3_offset.
2646 * - metadata[17:9] contains the inner_l2_offset.
2647 * - metadata[26:18] contains the inner_l3_offset.
2648 * - metadata[31:27] contains the inner_l4_size.
2650 #define RX_PKT_CMPL_FLAGS2_META_FORMAT_HDR_OFFSET \
2651 (UINT32_C(0x4) << 4)
2652 #define RX_PKT_CMPL_FLAGS2_META_FORMAT_LAST \
2653 RX_PKT_CMPL_FLAGS2_META_FORMAT_HDR_OFFSET
2655 * This field indicates the IP type for the inner-most IP header.
2656 * A value of '0' indicates IPv4. A value of '1' indicates IPv6.
2657 * This value is only valid if itype indicates a packet
2658 * with an IP header.
2660 #define RX_PKT_CMPL_FLAGS2_IP_TYPE UINT32_C(0x100)
2662 * This indicates that the complete 1's complement checksum was
2663 * calculated for the packet.
2665 #define RX_PKT_CMPL_FLAGS2_COMPLETE_CHECKSUM_CALC UINT32_C(0x200)
2667 * The combination of this value and meta_format indicated what
2668 * format the metadata field is.
2670 #define RX_PKT_CMPL_FLAGS2_EXT_META_FORMAT_MASK UINT32_C(0xc00)
2671 #define RX_PKT_CMPL_FLAGS2_EXT_META_FORMAT_SFT 10
2673 * This value is the complete 1's complement checksum calculated from
2674 * the start of the outer L3 header to the end of the packet (not
2675 * including the ethernet crc). It is valid when the
2676 * 'complete_checksum_calc' flag is set.
2678 #define RX_PKT_CMPL_FLAGS2_COMPLETE_CHECKSUM_MASK \
2679 UINT32_C(0xffff0000)
2680 #define RX_PKT_CMPL_FLAGS2_COMPLETE_CHECKSUM_SFT 16
2682 * This is data from the CFA block as indicated by the meta_format
2686 /* When meta_format=1, this value is the VLAN VID. */
2687 #define RX_PKT_CMPL_METADATA_VID_MASK UINT32_C(0xfff)
2688 #define RX_PKT_CMPL_METADATA_VID_SFT 0
2689 /* When meta_format=1, this value is the VLAN DE. */
2690 #define RX_PKT_CMPL_METADATA_DE UINT32_C(0x1000)
2691 /* When meta_format=1, this value is the VLAN PRI. */
2692 #define RX_PKT_CMPL_METADATA_PRI_MASK UINT32_C(0xe000)
2693 #define RX_PKT_CMPL_METADATA_PRI_SFT 13
2694 /* When meta_format=1, this value is the VLAN TPID. */
2695 #define RX_PKT_CMPL_METADATA_TPID_MASK UINT32_C(0xffff0000)
2696 #define RX_PKT_CMPL_METADATA_TPID_SFT 16
2699 * This value is written by the NIC such that it will be different
2700 * for each pass through the completion queue. The even passes
2701 * will write 1. The odd passes will write 0.
2703 #define RX_PKT_CMPL_V2 \
2705 #define RX_PKT_CMPL_ERRORS_MASK \
2707 #define RX_PKT_CMPL_ERRORS_SFT 1
2709 * This error indicates that there was some sort of problem with
2710 * the BDs for the packet that was found after part of the
2711 * packet was already placed. The packet should be treated as
2714 #define RX_PKT_CMPL_ERRORS_BUFFER_ERROR_MASK \
2716 #define RX_PKT_CMPL_ERRORS_BUFFER_ERROR_SFT 1
2717 /* No buffer error */
2718 #define RX_PKT_CMPL_ERRORS_BUFFER_ERROR_NO_BUFFER \
2719 (UINT32_C(0x0) << 1)
2722 * Packet did not fit into packet buffer provided.
2723 * For regular placement, this means the packet did not fit
2724 * in the buffer provided. For HDS and jumbo placement, this
2725 * means that the packet could not be placed into 7 physical
2728 #define RX_PKT_CMPL_ERRORS_BUFFER_ERROR_DID_NOT_FIT \
2729 (UINT32_C(0x1) << 1)
2732 * All BDs needed for the packet were not on-chip when
2733 * the packet arrived.
2735 #define RX_PKT_CMPL_ERRORS_BUFFER_ERROR_NOT_ON_CHIP \
2736 (UINT32_C(0x2) << 1)
2739 * BDs were not formatted correctly.
2741 #define RX_PKT_CMPL_ERRORS_BUFFER_ERROR_BAD_FORMAT \
2742 (UINT32_C(0x3) << 1)
2745 * There was a bad_format error on the previous operation
2747 #define RX_PKT_CMPL_ERRORS_BUFFER_ERROR_FLUSH \
2748 (UINT32_C(0x5) << 1)
2749 #define RX_PKT_CMPL_ERRORS_BUFFER_ERROR_LAST \
2750 RX_PKT_CMPL_ERRORS_BUFFER_ERROR_FLUSH
2752 * This indicates that there was an error in the IP header
2755 #define RX_PKT_CMPL_ERRORS_IP_CS_ERROR \
2758 * This indicates that there was an error in the TCP, UDP
2761 #define RX_PKT_CMPL_ERRORS_L4_CS_ERROR \
2764 * This indicates that there was an error in the tunnel
2765 * IP header checksum.
2767 #define RX_PKT_CMPL_ERRORS_T_IP_CS_ERROR \
2770 * This indicates that there was an error in the tunnel
2773 #define RX_PKT_CMPL_ERRORS_T_L4_CS_ERROR \
2776 * This indicates that there was a CRC error on either an FCoE
2777 * or RoCE packet. The itype indicates the packet type.
2779 #define RX_PKT_CMPL_ERRORS_CRC_ERROR \
2782 * This indicates that there was an error in the tunnel
2783 * portion of the packet when this
2784 * field is non-zero.
2786 #define RX_PKT_CMPL_ERRORS_T_PKT_ERROR_MASK \
2788 #define RX_PKT_CMPL_ERRORS_T_PKT_ERROR_SFT 9
2790 * No additional error occurred on the tunnel portion
2791 * or the packet of the packet does not have a tunnel.
2793 #define RX_PKT_CMPL_ERRORS_T_PKT_ERROR_NO_ERROR \
2794 (UINT32_C(0x0) << 9)
2796 * Indicates that IP header version does not match
2797 * expectation from L2 Ethertype for IPv4 and IPv6
2798 * in the tunnel header.
2800 #define RX_PKT_CMPL_ERRORS_T_PKT_ERROR_T_L3_BAD_VERSION \
2801 (UINT32_C(0x1) << 9)
2803 * Indicates that header length is out of range in the
2804 * tunnel header. Valid for
2807 #define RX_PKT_CMPL_ERRORS_T_PKT_ERROR_T_L3_BAD_HDR_LEN \
2808 (UINT32_C(0x2) << 9)
2810 * Indicates that the physical packet is shorter than that
2811 * claimed by the PPPoE header length for a tunnel PPPoE
2814 #define RX_PKT_CMPL_ERRORS_T_PKT_ERROR_TUNNEL_TOTAL_ERROR \
2815 (UINT32_C(0x3) << 9)
2817 * Indicates that physical packet is shorter than that claimed
2818 * by the tunnel l3 header length. Valid for IPv4, or IPv6
2819 * tunnel packet packets.
2821 #define RX_PKT_CMPL_ERRORS_T_PKT_ERROR_T_IP_TOTAL_ERROR \
2822 (UINT32_C(0x4) << 9)
2824 * Indicates that the physical packet is shorter than that
2825 * claimed by the tunnel UDP header length for a tunnel
2826 * UDP packet that is not fragmented.
2828 #define RX_PKT_CMPL_ERRORS_T_PKT_ERROR_T_UDP_TOTAL_ERROR \
2829 (UINT32_C(0x5) << 9)
2831 * indicates that the IPv4 TTL or IPv6 hop limit check
2832 * have failed (e.g. TTL = 0) in the tunnel header. Valid
2833 * for IPv4, and IPv6.
2835 #define RX_PKT_CMPL_ERRORS_T_PKT_ERROR_T_L3_BAD_TTL \
2836 (UINT32_C(0x6) << 9)
2837 #define RX_PKT_CMPL_ERRORS_T_PKT_ERROR_LAST \
2838 RX_PKT_CMPL_ERRORS_T_PKT_ERROR_T_L3_BAD_TTL
2840 * This indicates that there was an error in the inner
2841 * portion of the packet when this
2842 * field is non-zero.
2844 #define RX_PKT_CMPL_ERRORS_PKT_ERROR_MASK \
2846 #define RX_PKT_CMPL_ERRORS_PKT_ERROR_SFT 12
2848 * No additional error occurred on the tunnel portion
2849 * or the packet of the packet does not have a tunnel.
2851 #define RX_PKT_CMPL_ERRORS_PKT_ERROR_NO_ERROR \
2852 (UINT32_C(0x0) << 12)
2854 * Indicates that IP header version does not match
2855 * expectation from L2 Ethertype for IPv4 and IPv6 or that
2856 * option other than VFT was parsed on
2859 #define RX_PKT_CMPL_ERRORS_PKT_ERROR_L3_BAD_VERSION \
2860 (UINT32_C(0x1) << 12)
2862 * indicates that header length is out of range. Valid for
2865 #define RX_PKT_CMPL_ERRORS_PKT_ERROR_L3_BAD_HDR_LEN \
2866 (UINT32_C(0x2) << 12)
2868 * indicates that the IPv4 TTL or IPv6 hop limit check
2869 * have failed (e.g. TTL = 0). Valid for IPv4, and IPv6
2871 #define RX_PKT_CMPL_ERRORS_PKT_ERROR_L3_BAD_TTL \
2872 (UINT32_C(0x3) << 12)
2874 * Indicates that physical packet is shorter than that
2875 * claimed by the l3 header length. Valid for IPv4,
2876 * IPv6 packet or RoCE packets.
2878 #define RX_PKT_CMPL_ERRORS_PKT_ERROR_IP_TOTAL_ERROR \
2879 (UINT32_C(0x4) << 12)
2881 * Indicates that the physical packet is shorter than that
2882 * claimed by the UDP header length for a UDP packet that is
2885 #define RX_PKT_CMPL_ERRORS_PKT_ERROR_UDP_TOTAL_ERROR \
2886 (UINT32_C(0x5) << 12)
2888 * Indicates that TCP header length > IP payload. Valid for
2891 #define RX_PKT_CMPL_ERRORS_PKT_ERROR_L4_BAD_HDR_LEN \
2892 (UINT32_C(0x6) << 12)
2893 /* Indicates that TCP header length < 5. Valid for TCP. */
2894 #define RX_PKT_CMPL_ERRORS_PKT_ERROR_L4_BAD_HDR_LEN_TOO_SMALL \
2895 (UINT32_C(0x7) << 12)
2897 * Indicates that TCP option headers result in a TCP header
2898 * size that does not match data offset in TCP header. Valid
2901 #define RX_PKT_CMPL_ERRORS_PKT_ERROR_L4_BAD_OPT_LEN \
2902 (UINT32_C(0x8) << 12)
2903 #define RX_PKT_CMPL_ERRORS_PKT_ERROR_LAST \
2904 RX_PKT_CMPL_ERRORS_PKT_ERROR_L4_BAD_OPT_LEN
2906 * This field identifies the CFA action rule that was used for this
2912 * This value holds the reordering sequence number for the packet.
2913 * If the reordering sequence is not valid, then this value is zero.
2914 * The reordering domain for the packet is in the bottom 8 to 10b of
2915 * the rss_hash value. The bottom 20b of this value contain the
2916 * ordering domain value for the packet.
2918 #define RX_PKT_CMPL_REORDER_MASK UINT32_C(0xffffff)
2919 #define RX_PKT_CMPL_REORDER_SFT 0
2920 } __attribute__((packed));
2923 * This TPA completion structure is used on devices where the
2924 * `hwrm_vnic_qcaps.max_aggs_supported` value is 0.
2926 /* rx_tpa_start_cmpl (size:128b/16B) */
2927 struct rx_tpa_start_cmpl {
2928 uint16_t flags_type;
2930 * This field indicates the exact type of the completion.
2931 * By convention, the LSB identifies the length of the
2932 * record in 16B units. Even values indicate 16B
2933 * records. Odd values indicate 32B
2936 #define RX_TPA_START_CMPL_TYPE_MASK UINT32_C(0x3f)
2937 #define RX_TPA_START_CMPL_TYPE_SFT 0
2939 * RX L2 TPA Start Completion:
2940 * Completion at the beginning of a TPA operation.
2943 #define RX_TPA_START_CMPL_TYPE_RX_TPA_START UINT32_C(0x13)
2944 #define RX_TPA_START_CMPL_TYPE_LAST \
2945 RX_TPA_START_CMPL_TYPE_RX_TPA_START
2946 #define RX_TPA_START_CMPL_FLAGS_MASK UINT32_C(0xffc0)
2947 #define RX_TPA_START_CMPL_FLAGS_SFT 6
2948 /* This bit will always be '0' for TPA start completions. */
2949 #define RX_TPA_START_CMPL_FLAGS_ERROR UINT32_C(0x40)
2950 /* This field indicates how the packet was placed in the buffer. */
2951 #define RX_TPA_START_CMPL_FLAGS_PLACEMENT_MASK UINT32_C(0x380)
2952 #define RX_TPA_START_CMPL_FLAGS_PLACEMENT_SFT 7
2955 * TPA Packet was placed using jumbo algorithm. This means
2956 * that the first buffer will be filled with data before
2957 * moving to aggregation buffers. Each aggregation buffer
2958 * will be filled before moving to the next aggregation
2961 #define RX_TPA_START_CMPL_FLAGS_PLACEMENT_JUMBO \
2962 (UINT32_C(0x1) << 7)
2964 * Header/Data Separation:
2965 * Packet was placed using Header/Data separation algorithm.
2966 * The separation location is indicated by the itype field.
2968 #define RX_TPA_START_CMPL_FLAGS_PLACEMENT_HDS \
2969 (UINT32_C(0x2) << 7)
2972 * Packet will be placed using GRO/Jumbo where the first
2973 * packet is filled with data. Subsequent packets will be
2974 * placed such that any one packet does not span two
2975 * aggregation buffers unless it starts at the beginning of
2976 * an aggregation buffer.
2978 #define RX_TPA_START_CMPL_FLAGS_PLACEMENT_GRO_JUMBO \
2979 (UINT32_C(0x5) << 7)
2981 * GRO/Header-Data Separation:
2982 * Packet will be placed using GRO/HDS where the header
2983 * is in the first packet.
2984 * Payload of each packet will be
2985 * placed such that any one packet does not span two
2986 * aggregation buffers unless it starts at the beginning of
2987 * an aggregation buffer.
2989 #define RX_TPA_START_CMPL_FLAGS_PLACEMENT_GRO_HDS \
2990 (UINT32_C(0x6) << 7)
2991 #define RX_TPA_START_CMPL_FLAGS_PLACEMENT_LAST \
2992 RX_TPA_START_CMPL_FLAGS_PLACEMENT_GRO_HDS
2993 /* This bit is '1' if the RSS field in this completion is valid. */
2994 #define RX_TPA_START_CMPL_FLAGS_RSS_VALID UINT32_C(0x400)
2996 #define RX_TPA_START_CMPL_FLAGS_UNUSED UINT32_C(0x800)
2998 * This value indicates what the inner packet determined for the
3001 #define RX_TPA_START_CMPL_FLAGS_ITYPE_MASK UINT32_C(0xf000)
3002 #define RX_TPA_START_CMPL_FLAGS_ITYPE_SFT 12
3005 * Indicates that the packet was IP and TCP.
3007 #define RX_TPA_START_CMPL_FLAGS_ITYPE_TCP \
3008 (UINT32_C(0x2) << 12)
3009 #define RX_TPA_START_CMPL_FLAGS_ITYPE_LAST \
3010 RX_TPA_START_CMPL_FLAGS_ITYPE_TCP
3012 * This value indicates the amount of packet data written to the
3013 * buffer the opaque field in this completion corresponds to.
3017 * This is a copy of the opaque field from the RX BD this completion
3022 * This value is written by the NIC such that it will be different
3023 * for each pass through the completion queue. The even passes
3024 * will write 1. The odd passes will write 0.
3028 * This value is written by the NIC such that it will be different
3029 * for each pass through the completion queue. The even passes
3030 * will write 1. The odd passes will write 0.
3032 #define RX_TPA_START_CMPL_V1 UINT32_C(0x1)
3033 #define RX_TPA_START_CMPL_LAST RX_TPA_START_CMPL_V1
3035 * This is the RSS hash type for the packet. The value is packed
3036 * {tuple_extrac_op[1:0],rss_profile_id[4:0],tuple_extrac_op[2]}.
3038 * The value of tuple_extrac_op provides the information about
3039 * what fields the hash was computed on.
3040 * * 0: The RSS hash was computed over source IP address,
3041 * destination IP address, source port, and destination port of inner
3042 * IP and TCP or UDP headers. Note: For non-tunneled packets,
3043 * the packet headers are considered inner packet headers for the RSS
3044 * hash computation purpose.
3045 * * 1: The RSS hash was computed over source IP address and destination
3046 * IP address of inner IP header. Note: For non-tunneled packets,
3047 * the packet headers are considered inner packet headers for the RSS
3048 * hash computation purpose.
3049 * * 2: The RSS hash was computed over source IP address,
3050 * destination IP address, source port, and destination port of
3051 * IP and TCP or UDP headers of outer tunnel headers.
3052 * Note: For non-tunneled packets, this value is not applicable.
3053 * * 3: The RSS hash was computed over source IP address and
3054 * destination IP address of IP header of outer tunnel headers.
3055 * Note: For non-tunneled packets, this value is not applicable.
3057 * Note that 4-tuples values listed above are applicable
3058 * for layer 4 protocols supported and enabled for RSS in the hardware,
3059 * HWRM firmware, and drivers. For example, if RSS hash is supported and
3060 * enabled for TCP traffic only, then the values of tuple_extract_op
3061 * corresponding to 4-tuples are only valid for TCP traffic.
3063 uint8_t rss_hash_type;
3065 * This is the aggregation ID that the completion is associated
3066 * with. Use this number to correlate the TPA start completion
3067 * with the TPA end completion.
3070 /* unused2 is 9 b */
3071 #define RX_TPA_START_CMPL_UNUSED2_MASK UINT32_C(0x1ff)
3072 #define RX_TPA_START_CMPL_UNUSED2_SFT 0
3074 * This is the aggregation ID that the completion is associated
3075 * with. Use this number to correlate the TPA start completion
3076 * with the TPA end completion.
3078 #define RX_TPA_START_CMPL_AGG_ID_MASK UINT32_C(0xfe00)
3079 #define RX_TPA_START_CMPL_AGG_ID_SFT 9
3081 * This value is the RSS hash value calculated for the packet
3082 * based on the mode bits and key value in the VNIC.
3085 } __attribute__((packed));
3088 * Last 16 bytes of rx_tpa_start_cmpl.
3090 * This TPA completion structure is used on devices where the
3091 * `hwrm_vnic_qcaps.max_aggs_supported` value is 0.
3093 /* rx_tpa_start_cmpl_hi (size:128b/16B) */
3094 struct rx_tpa_start_cmpl_hi {
3097 * This indicates that the ip checksum was calculated for the
3098 * inner packet and that the sum passed for all segments
3099 * included in the aggregation.
3101 #define RX_TPA_START_CMPL_FLAGS2_IP_CS_CALC UINT32_C(0x1)
3103 * This indicates that the TCP, UDP or ICMP checksum was
3104 * calculated for the inner packet and that the sum passed
3105 * for all segments included in the aggregation.
3107 #define RX_TPA_START_CMPL_FLAGS2_L4_CS_CALC UINT32_C(0x2)
3109 * This indicates that the ip checksum was calculated for the
3110 * tunnel header and that the sum passed for all segments
3111 * included in the aggregation.
3113 #define RX_TPA_START_CMPL_FLAGS2_T_IP_CS_CALC UINT32_C(0x4)
3115 * This indicates that the UDP checksum was
3116 * calculated for the tunnel packet and that the sum passed for
3117 * all segments included in the aggregation.
3119 #define RX_TPA_START_CMPL_FLAGS2_T_L4_CS_CALC UINT32_C(0x8)
3120 /* This value indicates what format the metadata field is. */
3121 #define RX_TPA_START_CMPL_FLAGS2_META_FORMAT_MASK UINT32_C(0xf0)
3122 #define RX_TPA_START_CMPL_FLAGS2_META_FORMAT_SFT 4
3123 /* No metadata information. Value is zero. */
3124 #define RX_TPA_START_CMPL_FLAGS2_META_FORMAT_NONE \
3125 (UINT32_C(0x0) << 4)
3127 * The metadata field contains the VLAN tag and TPID value.
3128 * - metadata[11:0] contains the vlan VID value.
3129 * - metadata[12] contains the vlan DE value.
3130 * - metadata[15:13] contains the vlan PRI value.
3131 * - metadata[31:16] contains the vlan TPID value.
3133 #define RX_TPA_START_CMPL_FLAGS2_META_FORMAT_VLAN \
3134 (UINT32_C(0x1) << 4)
3135 #define RX_TPA_START_CMPL_FLAGS2_META_FORMAT_LAST \
3136 RX_TPA_START_CMPL_FLAGS2_META_FORMAT_VLAN
3138 * This field indicates the IP type for the inner-most IP header.
3139 * A value of '0' indicates IPv4. A value of '1' indicates IPv6.
3141 #define RX_TPA_START_CMPL_FLAGS2_IP_TYPE UINT32_C(0x100)
3143 * This is data from the CFA block as indicated by the meta_format
3147 /* When meta_format=1, this value is the VLAN VID. */
3148 #define RX_TPA_START_CMPL_METADATA_VID_MASK UINT32_C(0xfff)
3149 #define RX_TPA_START_CMPL_METADATA_VID_SFT 0
3150 /* When meta_format=1, this value is the VLAN DE. */
3151 #define RX_TPA_START_CMPL_METADATA_DE UINT32_C(0x1000)
3152 /* When meta_format=1, this value is the VLAN PRI. */
3153 #define RX_TPA_START_CMPL_METADATA_PRI_MASK UINT32_C(0xe000)
3154 #define RX_TPA_START_CMPL_METADATA_PRI_SFT 13
3155 /* When meta_format=1, this value is the VLAN TPID. */
3156 #define RX_TPA_START_CMPL_METADATA_TPID_MASK UINT32_C(0xffff0000)
3157 #define RX_TPA_START_CMPL_METADATA_TPID_SFT 16
3160 * This value is written by the NIC such that it will be different
3161 * for each pass through the completion queue. The even passes
3162 * will write 1. The odd passes will write 0.
3164 #define RX_TPA_START_CMPL_V2 UINT32_C(0x1)
3166 * This field identifies the CFA action rule that was used for this
3171 * This is the size in bytes of the inner most L4 header.
3172 * This can be subtracted from the payload_offset to determine
3173 * the start of the inner most L4 header.
3175 uint32_t inner_l4_size_inner_l3_offset_inner_l2_offset_outer_l3_offset;
3177 * This is the offset from the beginning of the packet in bytes for
3178 * the outer L3 header. If there is no outer L3 header, then this
3181 #define RX_TPA_START_CMPL_OUTER_L3_OFFSET_MASK UINT32_C(0x1ff)
3182 #define RX_TPA_START_CMPL_OUTER_L3_OFFSET_SFT 0
3184 * This is the offset from the beginning of the packet in bytes for
3185 * the inner most L2 header.
3187 #define RX_TPA_START_CMPL_INNER_L2_OFFSET_MASK UINT32_C(0x3fe00)
3188 #define RX_TPA_START_CMPL_INNER_L2_OFFSET_SFT 9
3190 * This is the offset from the beginning of the packet in bytes for
3191 * the inner most L3 header.
3193 #define RX_TPA_START_CMPL_INNER_L3_OFFSET_MASK UINT32_C(0x7fc0000)
3194 #define RX_TPA_START_CMPL_INNER_L3_OFFSET_SFT 18
3196 * This is the size in bytes of the inner most L4 header.
3197 * This can be subtracted from the payload_offset to determine
3198 * the start of the inner most L4 header.
3200 #define RX_TPA_START_CMPL_INNER_L4_SIZE_MASK UINT32_C(0xf8000000)
3201 #define RX_TPA_START_CMPL_INNER_L4_SIZE_SFT 27
3202 } __attribute__((packed));
3205 * This TPA completion structure is used on devices where the
3206 * `hwrm_vnic_qcaps.max_aggs_supported` value is 0.
3208 /* rx_tpa_end_cmpl (size:128b/16B) */
3209 struct rx_tpa_end_cmpl {
3210 uint16_t flags_type;
3212 * This field indicates the exact type of the completion.
3213 * By convention, the LSB identifies the length of the
3214 * record in 16B units. Even values indicate 16B
3215 * records. Odd values indicate 32B
3218 #define RX_TPA_END_CMPL_TYPE_MASK UINT32_C(0x3f)
3219 #define RX_TPA_END_CMPL_TYPE_SFT 0
3221 * RX L2 TPA End Completion:
3222 * Completion at the end of a TPA operation.
3225 #define RX_TPA_END_CMPL_TYPE_RX_TPA_END UINT32_C(0x15)
3226 #define RX_TPA_END_CMPL_TYPE_LAST \
3227 RX_TPA_END_CMPL_TYPE_RX_TPA_END
3228 #define RX_TPA_END_CMPL_FLAGS_MASK UINT32_C(0xffc0)
3229 #define RX_TPA_END_CMPL_FLAGS_SFT 6
3231 * When this bit is '1', it indicates a packet that has an
3232 * error of some type. Type of error is indicated in
3235 #define RX_TPA_END_CMPL_FLAGS_ERROR UINT32_C(0x40)
3236 /* This field indicates how the packet was placed in the buffer. */
3237 #define RX_TPA_END_CMPL_FLAGS_PLACEMENT_MASK UINT32_C(0x380)
3238 #define RX_TPA_END_CMPL_FLAGS_PLACEMENT_SFT 7
3241 * TPA Packet was placed using jumbo algorithm. This means
3242 * that the first buffer will be filled with data before
3243 * moving to aggregation buffers. Each aggregation buffer
3244 * will be filled before moving to the next aggregation
3247 #define RX_TPA_END_CMPL_FLAGS_PLACEMENT_JUMBO \
3248 (UINT32_C(0x1) << 7)
3250 * Header/Data Separation:
3251 * Packet was placed using Header/Data separation algorithm.
3252 * The separation location is indicated by the itype field.
3254 #define RX_TPA_END_CMPL_FLAGS_PLACEMENT_HDS \
3255 (UINT32_C(0x2) << 7)
3258 * Packet will be placed using GRO/Jumbo where the first
3259 * packet is filled with data. Subsequent packets will be
3260 * placed such that any one packet does not span two
3261 * aggregation buffers unless it starts at the beginning of
3262 * an aggregation buffer.
3264 #define RX_TPA_END_CMPL_FLAGS_PLACEMENT_GRO_JUMBO \
3265 (UINT32_C(0x5) << 7)
3267 * GRO/Header-Data Separation:
3268 * Packet will be placed using GRO/HDS where the header
3269 * is in the first packet.
3270 * Payload of each packet will be
3271 * placed such that any one packet does not span two
3272 * aggregation buffers unless it starts at the beginning of
3273 * an aggregation buffer.
3275 #define RX_TPA_END_CMPL_FLAGS_PLACEMENT_GRO_HDS \
3276 (UINT32_C(0x6) << 7)
3277 #define RX_TPA_END_CMPL_FLAGS_PLACEMENT_LAST \
3278 RX_TPA_END_CMPL_FLAGS_PLACEMENT_GRO_HDS
3280 #define RX_TPA_END_CMPL_FLAGS_UNUSED_MASK UINT32_C(0xc00)
3281 #define RX_TPA_END_CMPL_FLAGS_UNUSED_SFT 10
3283 * This value indicates what the inner packet determined for the
3286 * Indicates that the packet was IP and TCP. This indicates
3287 * that the ip_cs field is valid and that the tcp_udp_cs
3288 * field is valid and contains the TCP checksum.
3289 * This also indicates that the payload_offset field is valid.
3291 #define RX_TPA_END_CMPL_FLAGS_ITYPE_MASK UINT32_C(0xf000)
3292 #define RX_TPA_END_CMPL_FLAGS_ITYPE_SFT 12
3294 * This value is zero for TPA End completions.
3295 * There is no data in the buffer that corresponds to the opaque
3296 * value in this completion.
3300 * This is a copy of the opaque field from the RX BD this completion
3305 * This value is written by the NIC such that it will be different
3306 * for each pass through the completion queue. The even passes
3307 * will write 1. The odd passes will write 0.
3309 uint8_t agg_bufs_v1;
3311 * This value is written by the NIC such that it will be different
3312 * for each pass through the completion queue. The even passes
3313 * will write 1. The odd passes will write 0.
3315 #define RX_TPA_END_CMPL_V1 UINT32_C(0x1)
3317 * This value is the number of aggregation buffers that follow this
3318 * entry in the completion ring that are a part of this aggregation
3320 * If the value is zero, then the packet is completely contained
3321 * in the buffer space provided in the aggregation start completion.
3323 #define RX_TPA_END_CMPL_AGG_BUFS_MASK UINT32_C(0x7e)
3324 #define RX_TPA_END_CMPL_AGG_BUFS_SFT 1
3325 /* This value is the number of segments in the TPA operation. */
3328 * This value indicates the offset in bytes from the beginning of the packet
3329 * where the inner payload starts. This value is valid for TCP, UDP,
3330 * FCoE, and RoCE packets.
3332 * A value of zero indicates an offset of 256 bytes.
3334 uint8_t payload_offset;
3336 /* unused2 is 1 b */
3337 #define RX_TPA_END_CMPL_UNUSED2 UINT32_C(0x1)
3339 * This is the aggregation ID that the completion is associated
3340 * with. Use this number to correlate the TPA start completion
3341 * with the TPA end completion.
3343 #define RX_TPA_END_CMPL_AGG_ID_MASK UINT32_C(0xfe)
3344 #define RX_TPA_END_CMPL_AGG_ID_SFT 1
3346 * For non-GRO packets, this value is the
3347 * timestamp delta between earliest and latest timestamp values for
3348 * TPA packet. If packets were not time stamped, then delta will be
3351 * For GRO packets, this field is zero except for the following
3354 * Timestamp present indication. When '0', no Timestamp
3355 * option is in the packet. When '1', then a Timestamp
3356 * option is present in the packet.
3359 } __attribute__((packed));
3362 * Last 16 bytes of rx_tpa_end_cmpl.
3364 * This TPA completion structure is used on devices where the
3365 * `hwrm_vnic_qcaps.max_aggs_supported` value is 0.
3367 /* rx_tpa_end_cmpl_hi (size:128b/16B) */
3368 struct rx_tpa_end_cmpl_hi {
3369 uint32_t tpa_dup_acks;
3371 * This value is the number of duplicate ACKs that have been
3372 * received as part of the TPA operation.
3374 #define RX_TPA_END_CMPL_TPA_DUP_ACKS_MASK UINT32_C(0xf)
3375 #define RX_TPA_END_CMPL_TPA_DUP_ACKS_SFT 0
3377 * This value is the valid when TPA completion is active. It
3378 * indicates the length of the longest segment of the TPA operation
3379 * for LRO mode and the length of the first segment in GRO mode.
3381 * This value may be used by GRO software to re-construct the original
3382 * packet stream from the TPA packet. This is the length of all
3383 * but the last segment for GRO. In LRO mode this value may be used
3384 * to indicate MSS size to the stack.
3386 uint16_t tpa_seg_len;
3387 /* unused4 is 16 b */
3391 * This value is written by the NIC such that it will be different
3392 * for each pass through the completion queue. The even passes
3393 * will write 1. The odd passes will write 0.
3395 #define RX_TPA_END_CMPL_V2 UINT32_C(0x1)
3396 #define RX_TPA_END_CMPL_ERRORS_MASK UINT32_C(0xfffe)
3397 #define RX_TPA_END_CMPL_ERRORS_SFT 1
3399 * This error indicates that there was some sort of problem with
3400 * the BDs for the packet that was found after part of the
3401 * packet was already placed. The packet should be treated as
3404 #define RX_TPA_END_CMPL_ERRORS_BUFFER_ERROR_MASK UINT32_C(0xe)
3405 #define RX_TPA_END_CMPL_ERRORS_BUFFER_ERROR_SFT 1
3407 * This error occurs when there is a fatal HW problem in
3408 * the chip only. It indicates that there were not
3409 * BDs on chip but that there was adequate reservation.
3410 * provided by the TPA block.
3412 #define RX_TPA_END_CMPL_ERRORS_BUFFER_ERROR_NOT_ON_CHIP \
3413 (UINT32_C(0x2) << 1)
3415 * This error occurs when TPA block was not configured to
3416 * reserve adequate BDs for TPA operations on this RX
3417 * ring. All data for the TPA operation was not placed.
3419 * This error can also be generated when the number of
3420 * segments is not programmed correctly in TPA and the
3421 * 33 total aggregation buffers allowed for the TPA
3422 * operation has been exceeded.
3424 #define RX_TPA_END_CMPL_ERRORS_BUFFER_ERROR_RSV_ERROR \
3425 (UINT32_C(0x4) << 1)
3426 #define RX_TPA_END_CMPL_ERRORS_BUFFER_ERROR_LAST \
3427 RX_TPA_END_CMPL_ERRORS_BUFFER_ERROR_RSV_ERROR
3428 /* unused5 is 16 b */
3431 * This is the opaque value that was completed for the TPA start
3432 * completion that corresponds to this TPA end completion.
3434 uint32_t start_opaque;
3435 } __attribute__((packed));
3438 * This TPA completion structure is used on devices where the
3439 * `hwrm_vnic_qcaps.max_aggs_supported` value is greater than 0.
3441 /* rx_tpa_v2_start_cmpl (size:128b/16B) */
3442 struct rx_tpa_v2_start_cmpl {
3443 uint16_t flags_type;
3445 * This field indicates the exact type of the completion.
3446 * By convention, the LSB identifies the length of the
3447 * record in 16B units. Even values indicate 16B
3448 * records. Odd values indicate 32B
3451 #define RX_TPA_V2_START_CMPL_TYPE_MASK \
3453 #define RX_TPA_V2_START_CMPL_TYPE_SFT 0
3455 * RX L2 TPA Start Completion:
3456 * Completion at the beginning of a TPA operation.
3459 #define RX_TPA_V2_START_CMPL_TYPE_RX_TPA_START \
3461 #define RX_TPA_V2_START_CMPL_TYPE_LAST \
3462 RX_TPA_V2_START_CMPL_TYPE_RX_TPA_START
3463 #define RX_TPA_V2_START_CMPL_FLAGS_MASK \
3465 #define RX_TPA_V2_START_CMPL_FLAGS_SFT 6
3466 /* This bit will always be '0' for TPA start completions. */
3467 #define RX_TPA_V2_START_CMPL_FLAGS_ERROR \
3469 /* This field indicates how the packet was placed in the buffer. */
3470 #define RX_TPA_V2_START_CMPL_FLAGS_PLACEMENT_MASK \
3472 #define RX_TPA_V2_START_CMPL_FLAGS_PLACEMENT_SFT 7
3475 * TPA Packet was placed using jumbo algorithm. This means
3476 * that the first buffer will be filled with data before
3477 * moving to aggregation buffers. Each aggregation buffer
3478 * will be filled before moving to the next aggregation
3481 #define RX_TPA_V2_START_CMPL_FLAGS_PLACEMENT_JUMBO \
3482 (UINT32_C(0x1) << 7)
3484 * Header/Data Separation:
3485 * Packet was placed using Header/Data separation algorithm.
3486 * The separation location is indicated by the itype field.
3488 #define RX_TPA_V2_START_CMPL_FLAGS_PLACEMENT_HDS \
3489 (UINT32_C(0x2) << 7)
3492 * Packet will be placed using GRO/Jumbo where the first
3493 * packet is filled with data. Subsequent packets will be
3494 * placed such that any one packet does not span two
3495 * aggregation buffers unless it starts at the beginning of
3496 * an aggregation buffer.
3498 #define RX_TPA_V2_START_CMPL_FLAGS_PLACEMENT_GRO_JUMBO \
3499 (UINT32_C(0x5) << 7)
3501 * GRO/Header-Data Separation:
3502 * Packet will be placed using GRO/HDS where the header
3503 * is in the first packet.
3504 * Payload of each packet will be
3505 * placed such that any one packet does not span two
3506 * aggregation buffers unless it starts at the beginning of
3507 * an aggregation buffer.
3509 #define RX_TPA_V2_START_CMPL_FLAGS_PLACEMENT_GRO_HDS \
3510 (UINT32_C(0x6) << 7)
3511 #define RX_TPA_V2_START_CMPL_FLAGS_PLACEMENT_LAST \
3512 RX_TPA_V2_START_CMPL_FLAGS_PLACEMENT_GRO_HDS
3513 /* This bit is '1' if the RSS field in this completion is valid. */
3514 #define RX_TPA_V2_START_CMPL_FLAGS_RSS_VALID \
3517 * For devices that support timestamps, when this bit is cleared the
3518 * `inner_l4_size_inner_l3_offset_inner_l2_offset_outer_l3_offset`
3519 * field contains the 32b timestamp for
3520 * the packet from the MAC. When this bit is set, the
3521 * `inner_l4_size_inner_l3_offset_inner_l2_offset_outer_l3_offset`
3522 * field contains the outer_l3_offset, inner_l2_offset,
3523 * inner_l3_offset, and inner_l4_size.
3525 #define RX_TPA_V2_START_CMPL_FLAGS_TIMESTAMP_FLD_FORMAT \
3528 * This value indicates what the inner packet determined for the
3531 #define RX_TPA_V2_START_CMPL_FLAGS_ITYPE_MASK \
3533 #define RX_TPA_V2_START_CMPL_FLAGS_ITYPE_SFT 12
3536 * Indicates that the packet was IP and TCP.
3538 #define RX_TPA_V2_START_CMPL_FLAGS_ITYPE_TCP \
3539 (UINT32_C(0x2) << 12)
3540 #define RX_TPA_V2_START_CMPL_FLAGS_ITYPE_LAST \
3541 RX_TPA_V2_START_CMPL_FLAGS_ITYPE_TCP
3543 * This value indicates the amount of packet data written to the
3544 * buffer the opaque field in this completion corresponds to.
3548 * This is a copy of the opaque field from the RX BD this completion
3553 * This value is written by the NIC such that it will be different
3554 * for each pass through the completion queue. The even passes
3555 * will write 1. The odd passes will write 0.
3559 * This value is written by the NIC such that it will be different
3560 * for each pass through the completion queue. The even passes
3561 * will write 1. The odd passes will write 0.
3563 #define RX_TPA_V2_START_CMPL_V1 UINT32_C(0x1)
3564 #define RX_TPA_V2_START_CMPL_LAST RX_TPA_V2_START_CMPL_V1
3566 * This is the RSS hash type for the packet. The value is packed
3567 * {tuple_extrac_op[1:0],rss_profile_id[4:0],tuple_extrac_op[2]}.
3569 * The value of tuple_extrac_op provides the information about
3570 * what fields the hash was computed on.
3571 * * 0: The RSS hash was computed over source IP address,
3572 * destination IP address, source port, and destination port of inner
3573 * IP and TCP or UDP headers. Note: For non-tunneled packets,
3574 * the packet headers are considered inner packet headers for the RSS
3575 * hash computation purpose.
3576 * * 1: The RSS hash was computed over source IP address and destination
3577 * IP address of inner IP header. Note: For non-tunneled packets,
3578 * the packet headers are considered inner packet headers for the RSS
3579 * hash computation purpose.
3580 * * 2: The RSS hash was computed over source IP address,
3581 * destination IP address, source port, and destination port of
3582 * IP and TCP or UDP headers of outer tunnel headers.
3583 * Note: For non-tunneled packets, this value is not applicable.
3584 * * 3: The RSS hash was computed over source IP address and
3585 * destination IP address of IP header of outer tunnel headers.
3586 * Note: For non-tunneled packets, this value is not applicable.
3588 * Note that 4-tuples values listed above are applicable
3589 * for layer 4 protocols supported and enabled for RSS in the hardware,
3590 * HWRM firmware, and drivers. For example, if RSS hash is supported and
3591 * enabled for TCP traffic only, then the values of tuple_extract_op
3592 * corresponding to 4-tuples are only valid for TCP traffic.
3594 uint8_t rss_hash_type;
3596 * This is the aggregation ID that the completion is associated
3597 * with. Use this number to correlate the TPA start completion
3598 * with the TPA end completion.
3602 * This value is the RSS hash value calculated for the packet
3603 * based on the mode bits and key value in the VNIC.
3606 } __attribute__((packed));
3609 * Last 16 bytes of rx_tpa_v2_start_cmpl.
3611 * This TPA completion structure is used on devices where the
3612 * `hwrm_vnic_qcaps.max_aggs_supported` value is greater than 0.
3614 /* rx_tpa_v2_start_cmpl_hi (size:128b/16B) */
3615 struct rx_tpa_v2_start_cmpl_hi {
3618 * This indicates that the ip checksum was calculated for the
3619 * inner packet and that the sum passed for all segments
3620 * included in the aggregation.
3622 #define RX_TPA_V2_START_CMPL_FLAGS2_IP_CS_CALC \
3625 * This indicates that the TCP, UDP or ICMP checksum was
3626 * calculated for the inner packet and that the sum passed
3627 * for all segments included in the aggregation.
3629 #define RX_TPA_V2_START_CMPL_FLAGS2_L4_CS_CALC \
3632 * This indicates that the ip checksum was calculated for the
3633 * tunnel header and that the sum passed for all segments
3634 * included in the aggregation.
3636 #define RX_TPA_V2_START_CMPL_FLAGS2_T_IP_CS_CALC \
3639 * This indicates that the UDP checksum was
3640 * calculated for the tunnel packet and that the sum passed for
3641 * all segments included in the aggregation.
3643 #define RX_TPA_V2_START_CMPL_FLAGS2_T_L4_CS_CALC \
3645 /* This value indicates what format the metadata field is. */
3646 #define RX_TPA_V2_START_CMPL_FLAGS2_META_FORMAT_MASK \
3648 #define RX_TPA_V2_START_CMPL_FLAGS2_META_FORMAT_SFT 4
3649 /* No metadata informtaion. Value is zero. */
3650 #define RX_TPA_V2_START_CMPL_FLAGS2_META_FORMAT_NONE \
3651 (UINT32_C(0x0) << 4)
3653 * The metadata field contains the VLAN tag and TPID value.
3654 * - metadata[11:0] contains the vlan VID value.
3655 * - metadata[12] contains the vlan DE value.
3656 * - metadata[15:13] contains the vlan PRI value.
3657 * - metadata[31:16] contains the vlan TPID value.
3659 #define RX_TPA_V2_START_CMPL_FLAGS2_META_FORMAT_VLAN \
3660 (UINT32_C(0x1) << 4)
3662 * If ext_meta_format is equal to 1, the metadata field
3663 * contains the lower 16b of the tunnel ID value, justified
3665 * - VXLAN = VNI[23:0] -> VXLAN Network ID
3666 * - Geneve (NGE) = VNI[23:0] a-> Virtual Network Identifier.
3667 * - NVGRE = TNI[23:0] -> Tenant Network ID
3668 * - GRE = KEY[31:0 -> key fieled with bit mask. zero if K = 0
3669 * - IPV4 = 0 (not populated)
3670 * - IPV6 = Flow Label[19:0]
3671 * - PPPoE = sessionID[15:0]
3672 * - MPLs = Outer label[19:0]
3673 * - UPAR = Selected[31:0] with bit mask
3675 #define RX_TPA_V2_START_CMPL_FLAGS2_META_FORMAT_TUNNEL_ID \
3676 (UINT32_C(0x2) << 4)
3678 * if ext_meta_format is equal to 1, metadata field contains
3679 * 16b metadata from the prepended header (chdr_data).
3681 #define RX_TPA_V2_START_CMPL_FLAGS2_META_FORMAT_CHDR_DATA \
3682 (UINT32_C(0x3) << 4)
3684 * If ext_meta_format is equal to 1, the metadata field contains
3685 * the outer_l3_offset, inner_l2_offset, inner_l3_offset and
3687 * - metadata[8:0] contains the outer_l3_offset.
3688 * - metadata[17:9] contains the inner_l2_offset.
3689 * - metadata[26:18] contains the inner_l3_offset.
3690 * - metadata[31:27] contains the inner_l4_size.
3692 #define RX_TPA_V2_START_CMPL_FLAGS2_META_FORMAT_HDR_OFFSET \
3693 (UINT32_C(0x4) << 4)
3694 #define RX_TPA_V2_START_CMPL_FLAGS2_META_FORMAT_LAST \
3695 RX_TPA_V2_START_CMPL_FLAGS2_META_FORMAT_HDR_OFFSET
3697 * This field indicates the IP type for the inner-most IP header.
3698 * A value of '0' indicates IPv4. A value of '1' indicates IPv6.
3700 #define RX_TPA_V2_START_CMPL_FLAGS2_IP_TYPE \
3703 * This indicates that the complete 1's complement checksum was
3704 * calculated for the packet.
3706 #define RX_TPA_V2_START_CMPL_FLAGS2_COMPLETE_CHECKSUM_CALC \
3709 * The combination of this value and meta_format indicated what
3710 * format the metadata field is.
3712 #define RX_TPA_V2_START_CMPL_FLAGS2_EXT_META_FORMAT_MASK \
3714 #define RX_TPA_V2_START_CMPL_FLAGS2_EXT_META_FORMAT_SFT 10
3716 * This value is the complete 1's complement checksum calculated from
3717 * the start of the outer L3 header to the end of the packet (not
3718 * including the ethernet crc). It is valid when the
3719 * 'complete_checksum_calc' flag is set. For TPA Start completions,
3720 * the complete checksum is calculated for the first packet in the
3723 #define RX_TPA_V2_START_CMPL_FLAGS2_COMPLETE_CHECKSUM_MASK \
3724 UINT32_C(0xffff0000)
3725 #define RX_TPA_V2_START_CMPL_FLAGS2_COMPLETE_CHECKSUM_SFT 16
3727 * This is data from the CFA block as indicated by the meta_format
3731 /* When {ext_meta_format,meta_format}=1, this value is the VLAN VID. */
3732 #define RX_TPA_V2_START_CMPL_METADATA_VID_MASK UINT32_C(0xfff)
3733 #define RX_TPA_V2_START_CMPL_METADATA_VID_SFT 0
3734 /* When {ext_meta_format,meta_format}=1, this value is the VLAN DE. */
3735 #define RX_TPA_V2_START_CMPL_METADATA_DE UINT32_C(0x1000)
3736 /* When {ext_meta_format,meta_format}=1, this value is the VLAN PRI. */
3737 #define RX_TPA_V2_START_CMPL_METADATA_PRI_MASK UINT32_C(0xe000)
3738 #define RX_TPA_V2_START_CMPL_METADATA_PRI_SFT 13
3739 /* When {ext_meta_format,meta_format}=1, this value is the VLAN TPID. */
3740 #define RX_TPA_V2_START_CMPL_METADATA_TPID_MASK UINT32_C(0xffff0000)
3741 #define RX_TPA_V2_START_CMPL_METADATA_TPID_SFT 16
3744 * This value is written by the NIC such that it will be different
3745 * for each pass through the completion queue. The even passes
3746 * will write 1. The odd passes will write 0.
3748 #define RX_TPA_V2_START_CMPL_V2 \
3750 #define RX_TPA_V2_START_CMPL_ERRORS_MASK \
3752 #define RX_TPA_V2_START_CMPL_ERRORS_SFT 1
3754 * This error indicates that there was some sort of problem with
3755 * the BDs for the packet that was found after part of the
3756 * packet was already placed. The packet should be treated as
3759 #define RX_TPA_V2_START_CMPL_ERRORS_BUFFER_ERROR_MASK \
3761 #define RX_TPA_V2_START_CMPL_ERRORS_BUFFER_ERROR_SFT 1
3762 /* No buffer error */
3763 #define RX_TPA_V2_START_CMPL_ERRORS_BUFFER_ERROR_NO_BUFFER \
3764 (UINT32_C(0x0) << 1)
3767 * BDs were not formatted correctly.
3769 #define RX_TPA_V2_START_CMPL_ERRORS_BUFFER_ERROR_BAD_FORMAT \
3770 (UINT32_C(0x3) << 1)
3773 * There was a bad_format error on the previous operation
3775 #define RX_TPA_V2_START_CMPL_ERRORS_BUFFER_ERROR_FLUSH \
3776 (UINT32_C(0x5) << 1)
3777 #define RX_TPA_V2_START_CMPL_ERRORS_BUFFER_ERROR_LAST \
3778 RX_TPA_V2_START_CMPL_ERRORS_BUFFER_ERROR_FLUSH
3780 * This field identifies the CFA action rule that was used for this
3785 * For devices that support timestamps this field is overridden
3786 * with the timestamp value. When `flags.timestamp_fld_format` is
3787 * cleared, this field contains the 32b timestamp for the packet from the
3790 * When `flags.timestamp_fld_format` is set, this field contains the
3791 * outer_l3_offset, inner_l2_offset, inner_l3_offset, and inner_l4_size
3794 uint32_t inner_l4_size_inner_l3_offset_inner_l2_offset_outer_l3_offset;
3796 * This is the offset from the beginning of the packet in bytes for
3797 * the outer L3 header. If there is no outer L3 header, then this
3800 #define RX_TPA_V2_START_CMPL_OUTER_L3_OFFSET_MASK UINT32_C(0x1ff)
3801 #define RX_TPA_V2_START_CMPL_OUTER_L3_OFFSET_SFT 0
3803 * This is the offset from the beginning of the packet in bytes for
3804 * the inner most L2 header.
3806 #define RX_TPA_V2_START_CMPL_INNER_L2_OFFSET_MASK UINT32_C(0x3fe00)
3807 #define RX_TPA_V2_START_CMPL_INNER_L2_OFFSET_SFT 9
3809 * This is the offset from the beginning of the packet in bytes for
3810 * the inner most L3 header.
3812 #define RX_TPA_V2_START_CMPL_INNER_L3_OFFSET_MASK UINT32_C(0x7fc0000)
3813 #define RX_TPA_V2_START_CMPL_INNER_L3_OFFSET_SFT 18
3815 * This is the size in bytes of the inner most L4 header.
3816 * This can be subtracted from the payload_offset to determine
3817 * the start of the inner most L4 header.
3819 #define RX_TPA_V2_START_CMPL_INNER_L4_SIZE_MASK UINT32_C(0xf8000000)
3820 #define RX_TPA_V2_START_CMPL_INNER_L4_SIZE_SFT 27
3821 } __attribute__((packed));
3824 * This TPA completion structure is used on devices where the
3825 * `hwrm_vnic_qcaps.max_aggs_supported` value is greater than 0.
3827 /* rx_tpa_v2_end_cmpl (size:128b/16B) */
3828 struct rx_tpa_v2_end_cmpl {
3829 uint16_t flags_type;
3831 * This field indicates the exact type of the completion.
3832 * By convention, the LSB identifies the length of the
3833 * record in 16B units. Even values indicate 16B
3834 * records. Odd values indicate 32B
3837 #define RX_TPA_V2_END_CMPL_TYPE_MASK UINT32_C(0x3f)
3838 #define RX_TPA_V2_END_CMPL_TYPE_SFT 0
3840 * RX L2 TPA End Completion:
3841 * Completion at the end of a TPA operation.
3844 #define RX_TPA_V2_END_CMPL_TYPE_RX_TPA_END UINT32_C(0x15)
3845 #define RX_TPA_V2_END_CMPL_TYPE_LAST \
3846 RX_TPA_V2_END_CMPL_TYPE_RX_TPA_END
3847 #define RX_TPA_V2_END_CMPL_FLAGS_MASK UINT32_C(0xffc0)
3848 #define RX_TPA_V2_END_CMPL_FLAGS_SFT 6
3850 * When this bit is '1', it indicates a packet that has an
3851 * error of some type. Type of error is indicated in
3854 #define RX_TPA_V2_END_CMPL_FLAGS_ERROR UINT32_C(0x40)
3855 /* This field indicates how the packet was placed in the buffer. */
3856 #define RX_TPA_V2_END_CMPL_FLAGS_PLACEMENT_MASK UINT32_C(0x380)
3857 #define RX_TPA_V2_END_CMPL_FLAGS_PLACEMENT_SFT 7
3860 * TPA Packet was placed using jumbo algorithm. This means
3861 * that the first buffer will be filled with data before
3862 * moving to aggregation buffers. Each aggregation buffer
3863 * will be filled before moving to the next aggregation
3866 #define RX_TPA_V2_END_CMPL_FLAGS_PLACEMENT_JUMBO \
3867 (UINT32_C(0x1) << 7)
3869 * Header/Data Separation:
3870 * Packet was placed using Header/Data separation algorithm.
3871 * The separation location is indicated by the itype field.
3873 #define RX_TPA_V2_END_CMPL_FLAGS_PLACEMENT_HDS \
3874 (UINT32_C(0x2) << 7)
3877 * Packet will be placed using GRO/Jumbo where the first
3878 * packet is filled with data. Subsequent packets will be
3879 * placed such that any one packet does not span two
3880 * aggregation buffers unless it starts at the beginning of
3881 * an aggregation buffer.
3883 #define RX_TPA_V2_END_CMPL_FLAGS_PLACEMENT_GRO_JUMBO \
3884 (UINT32_C(0x5) << 7)
3886 * GRO/Header-Data Separation:
3887 * Packet will be placed using GRO/HDS where the header
3888 * is in the first packet.
3889 * Payload of each packet will be
3890 * placed such that any one packet does not span two
3891 * aggregation buffers unless it starts at the beginning of
3892 * an aggregation buffer.
3894 #define RX_TPA_V2_END_CMPL_FLAGS_PLACEMENT_GRO_HDS \
3895 (UINT32_C(0x6) << 7)
3896 #define RX_TPA_V2_END_CMPL_FLAGS_PLACEMENT_LAST \
3897 RX_TPA_V2_END_CMPL_FLAGS_PLACEMENT_GRO_HDS
3899 #define RX_TPA_V2_END_CMPL_FLAGS_UNUSED_MASK UINT32_C(0xc00)
3900 #define RX_TPA_V2_END_CMPL_FLAGS_UNUSED_SFT 10
3902 * This value indicates what the inner packet determined for the
3905 * Indicates that the packet was IP and TCP. This indicates
3906 * that the ip_cs field is valid and that the tcp_udp_cs
3907 * field is valid and contains the TCP checksum.
3908 * This also indicates that the payload_offset field is valid.
3910 #define RX_TPA_V2_END_CMPL_FLAGS_ITYPE_MASK UINT32_C(0xf000)
3911 #define RX_TPA_V2_END_CMPL_FLAGS_ITYPE_SFT 12
3913 * This value is zero for TPA End completions.
3914 * There is no data in the buffer that corresponds to the opaque
3915 * value in this completion.
3919 * This is a copy of the opaque field from the RX BD this completion
3925 * This value is written by the NIC such that it will be different
3926 * for each pass through the completion queue. The even passes
3927 * will write 1. The odd passes will write 0.
3929 #define RX_TPA_V2_END_CMPL_V1 UINT32_C(0x1)
3930 /* This value is the number of segments in the TPA operation. */
3933 * This is the aggregation ID that the completion is associated
3934 * with. Use this number to correlate the TPA start completion
3935 * with the TPA end completion.
3939 * For non-GRO packets, this value is the
3940 * timestamp delta between earliest and latest timestamp values for
3941 * TPA packet. If packets were not time stamped, then delta will be
3944 * For GRO packets, this field is zero except for the following
3947 * Timestamp present indication. When '0', no Timestamp
3948 * option is in the packet. When '1', then a Timestamp
3949 * option is present in the packet.
3952 } __attribute__((packed));
3955 * Last 16 bytes of rx_tpa_v2_end_cmpl.
3957 * This TPA completion structure is used on devices where the
3958 * `hwrm_vnic_qcaps.max_aggs_supported` value is greater than 0.
3960 /* rx_tpa_v2_end_cmpl_hi (size:128b/16B) */
3961 struct rx_tpa_v2_end_cmpl_hi {
3963 * This value is the number of duplicate ACKs that have been
3964 * received as part of the TPA operation.
3966 uint16_t tpa_dup_acks;
3968 * This value is the number of duplicate ACKs that have been
3969 * received as part of the TPA operation.
3971 #define RX_TPA_V2_END_CMPL_TPA_DUP_ACKS_MASK UINT32_C(0xf)
3972 #define RX_TPA_V2_END_CMPL_TPA_DUP_ACKS_SFT 0
3974 * This value indicated the offset in bytes from the beginning of
3975 * the packet where the inner payload starts. This value is valid
3976 * for TCP, UDP, FCoE and RoCE packets
3978 uint8_t payload_offset;
3980 * The value is the total number of aggregation buffers that were
3981 * used in the TPA operation. All TPA aggregation buffer completions
3982 * precede the TPA End completion. If the value is zero, then the
3983 * aggregation is completely contained in the buffer space provided
3984 * in the aggregation start completion.
3985 * Note that the field is simply provided as a cross check.
3987 uint8_t tpa_agg_bufs;
3989 * This value is the valid when TPA completion is active. It
3990 * indicates the length of the longest segment of the TPA operation
3991 * for LRO mode and the length of the first segment in GRO mode.
3993 * This value may be used by GRO software to re-construct the original
3994 * packet stream from the TPA packet. This is the length of all
3995 * but the last segment for GRO. In LRO mode this value may be used
3996 * to indicate MSS size to the stack.
3998 uint16_t tpa_seg_len;
4002 * This value is written by the NIC such that it will be different
4003 * for each pass through the completion queue. The even passes
4004 * will write 1. The odd passes will write 0.
4006 #define RX_TPA_V2_END_CMPL_V2 UINT32_C(0x1)
4007 #define RX_TPA_V2_END_CMPL_ERRORS_MASK \
4009 #define RX_TPA_V2_END_CMPL_ERRORS_SFT 1
4011 * This error indicates that there was some sort of problem with
4012 * the BDs for the packet that was found after part of the
4013 * packet was already placed. The packet should be treated as
4016 #define RX_TPA_V2_END_CMPL_ERRORS_BUFFER_ERROR_MASK \
4018 #define RX_TPA_V2_END_CMPL_ERRORS_BUFFER_ERROR_SFT 1
4019 /* No buffer error */
4020 #define RX_TPA_V2_END_CMPL_ERRORS_BUFFER_ERROR_NO_BUFFER \
4021 (UINT32_C(0x0) << 1)
4023 * This error occurs when there is a fatal HW problem in
4024 * the chip only. It indicates that there were not
4025 * BDs on chip but that there was adequate reservation.
4026 * provided by the TPA block.
4028 #define RX_TPA_V2_END_CMPL_ERRORS_BUFFER_ERROR_NOT_ON_CHIP \
4029 (UINT32_C(0x2) << 1)
4032 * BDs were not formatted correctly.
4034 #define RX_TPA_V2_END_CMPL_ERRORS_BUFFER_ERROR_BAD_FORMAT \
4035 (UINT32_C(0x3) << 1)
4037 * This error occurs when TPA block was not configured to
4038 * reserve adequate BDs for TPA operations on this RX
4039 * ring. All data for the TPA operation was not placed.
4041 * This error can also be generated when the number of
4042 * segments is not programmed correctly in TPA and the
4043 * 33 total aggregation buffers allowed for the TPA
4044 * operation has been exceeded.
4046 #define RX_TPA_V2_END_CMPL_ERRORS_BUFFER_ERROR_RSV_ERROR \
4047 (UINT32_C(0x4) << 1)
4050 * There was a bad_format error on the previous operation
4052 #define RX_TPA_V2_END_CMPL_ERRORS_BUFFER_ERROR_FLUSH \
4053 (UINT32_C(0x5) << 1)
4054 #define RX_TPA_V2_END_CMPL_ERRORS_BUFFER_ERROR_LAST \
4055 RX_TPA_V2_END_CMPL_ERRORS_BUFFER_ERROR_FLUSH
4058 * This is the opaque value that was completed for the TPA start
4059 * completion that corresponds to this TPA end completion.
4061 uint32_t start_opaque;
4062 } __attribute__((packed));
4065 * This TPA completion structure is used on devices where the
4066 * `hwrm_vnic_qcaps.max_aggs_supported` value is greater than 0.
4068 /* rx_tpa_v2_abuf_cmpl (size:128b/16B) */
4069 struct rx_tpa_v2_abuf_cmpl {
4072 * This field indicates the exact type of the completion.
4073 * By convention, the LSB identifies the length of the
4074 * record in 16B units. Even values indicate 16B
4075 * records. Odd values indicate 32B
4078 #define RX_TPA_V2_ABUF_CMPL_TYPE_MASK UINT32_C(0x3f)
4079 #define RX_TPA_V2_ABUF_CMPL_TYPE_SFT 0
4081 * RX TPA Aggregation Buffer completion :
4082 * Completion of an L2 aggregation buffer in support of
4083 * TPA packet completion. Length = 16B
4085 #define RX_TPA_V2_ABUF_CMPL_TYPE_RX_TPA_AGG UINT32_C(0x16)
4086 #define RX_TPA_V2_ABUF_CMPL_TYPE_LAST \
4087 RX_TPA_V2_ABUF_CMPL_TYPE_RX_TPA_AGG
4089 * This is the length of the data for the packet stored in this
4090 * aggregation buffer identified by the opaque value. This does not
4091 * include the length of any
4092 * data placed in other aggregation BDs or in the packet or buffer
4093 * BDs. This length does not include any space added due to
4094 * hdr_offset register during HDS placement mode.
4098 * This is a copy of the opaque field from the RX BD this aggregation
4099 * buffer corresponds to.
4104 * This value is written by the NIC such that it will be different
4105 * for each pass through the completion queue. The even passes
4106 * will write 1. The odd passes will write 0.
4108 #define RX_TPA_V2_ABUF_CMPL_V UINT32_C(0x1)
4110 * This is the aggregation ID that the completion is associated with. Use
4111 * this number to correlate the TPA agg completion with the TPA start
4112 * completion and the TPA end completion.
4116 } __attribute__((packed));
4118 /* rx_abuf_cmpl (size:128b/16B) */
4119 struct rx_abuf_cmpl {
4122 * This field indicates the exact type of the completion.
4123 * By convention, the LSB identifies the length of the
4124 * record in 16B units. Even values indicate 16B
4125 * records. Odd values indicate 32B
4128 #define RX_ABUF_CMPL_TYPE_MASK UINT32_C(0x3f)
4129 #define RX_ABUF_CMPL_TYPE_SFT 0
4131 * RX Aggregation Buffer completion :
4132 * Completion of an L2 aggregation buffer in support of
4133 * TPA, HDS, or Jumbo packet completion. Length = 16B
4135 #define RX_ABUF_CMPL_TYPE_RX_AGG UINT32_C(0x12)
4136 #define RX_ABUF_CMPL_TYPE_LAST RX_ABUF_CMPL_TYPE_RX_AGG
4138 * This is the length of the data for the packet stored in this
4139 * aggregation buffer identified by the opaque value. This does not
4140 * include the length of any
4141 * data placed in other aggregation BDs or in the packet or buffer
4142 * BDs. This length does not include any space added due to
4143 * hdr_offset register during HDS placement mode.
4147 * This is a copy of the opaque field from the RX BD this aggregation
4148 * buffer corresponds to.
4153 * This value is written by the NIC such that it will be different
4154 * for each pass through the completion queue. The even passes
4155 * will write 1. The odd passes will write 0.
4157 #define RX_ABUF_CMPL_V UINT32_C(0x1)
4158 /* unused3 is 32 b */
4160 } __attribute__((packed));
4162 /* eject_cmpl (size:128b/16B) */
4166 * This field indicates the exact type of the completion.
4167 * By convention, the LSB identifies the length of the
4168 * record in 16B units. Even values indicate 16B
4169 * records. Odd values indicate 32B
4172 #define EJECT_CMPL_TYPE_MASK UINT32_C(0x3f)
4173 #define EJECT_CMPL_TYPE_SFT 0
4175 * Statistics Ejection Completion:
4176 * Completion of statistics data ejection buffer.
4179 #define EJECT_CMPL_TYPE_STAT_EJECT UINT32_C(0x1a)
4180 #define EJECT_CMPL_TYPE_LAST EJECT_CMPL_TYPE_STAT_EJECT
4181 #define EJECT_CMPL_FLAGS_MASK UINT32_C(0xffc0)
4182 #define EJECT_CMPL_FLAGS_SFT 6
4184 * When this bit is '1', it indicates a packet that has an
4185 * error of some type. Type of error is indicated in
4188 #define EJECT_CMPL_FLAGS_ERROR UINT32_C(0x40)
4190 * This is the length of the statistics data stored in this
4195 * This is a copy of the opaque field from the RX BD this ejection
4196 * buffer corresponds to.
4201 * This value is written by the NIC such that it will be different
4202 * for each pass through the completion queue. The even passes
4203 * will write 1. The odd passes will write 0.
4205 #define EJECT_CMPL_V UINT32_C(0x1)
4206 #define EJECT_CMPL_ERRORS_MASK UINT32_C(0xfffe)
4207 #define EJECT_CMPL_ERRORS_SFT 1
4209 * This error indicates that there was some sort of problem with
4210 * the BDs for statistics ejection. The statistics ejection should
4211 * be treated as invalid
4213 #define EJECT_CMPL_ERRORS_BUFFER_ERROR_MASK UINT32_C(0xe)
4214 #define EJECT_CMPL_ERRORS_BUFFER_ERROR_SFT 1
4215 /* No buffer error */
4216 #define EJECT_CMPL_ERRORS_BUFFER_ERROR_NO_BUFFER \
4217 (UINT32_C(0x0) << 1)
4220 * Statistics did not fit into aggregation buffer provided.
4222 #define EJECT_CMPL_ERRORS_BUFFER_ERROR_DID_NOT_FIT \
4223 (UINT32_C(0x1) << 1)
4226 * BDs were not formatted correctly.
4228 #define EJECT_CMPL_ERRORS_BUFFER_ERROR_BAD_FORMAT \
4229 (UINT32_C(0x3) << 1)
4232 * There was a bad_format error on the previous operation
4234 #define EJECT_CMPL_ERRORS_BUFFER_ERROR_FLUSH \
4235 (UINT32_C(0x5) << 1)
4236 #define EJECT_CMPL_ERRORS_BUFFER_ERROR_LAST \
4237 EJECT_CMPL_ERRORS_BUFFER_ERROR_FLUSH
4238 /* reserved16 is 16 b */
4239 uint16_t reserved16;
4240 /* unused3 is 32 b */
4242 } __attribute__((packed));
4244 /* hwrm_cmpl (size:128b/16B) */
4248 * This field indicates the exact type of the completion.
4249 * By convention, the LSB identifies the length of the
4250 * record in 16B units. Even values indicate 16B
4251 * records. Odd values indicate 32B
4254 #define HWRM_CMPL_TYPE_MASK UINT32_C(0x3f)
4255 #define HWRM_CMPL_TYPE_SFT 0
4257 * HWRM Command Completion:
4258 * Completion of an HWRM command.
4260 #define HWRM_CMPL_TYPE_HWRM_DONE UINT32_C(0x20)
4261 #define HWRM_CMPL_TYPE_LAST HWRM_CMPL_TYPE_HWRM_DONE
4262 /* This is the sequence_id of the HWRM command that has completed. */
4263 uint16_t sequence_id;
4264 /* unused2 is 32 b */
4268 * This value is written by the NIC such that it will be different
4269 * for each pass through the completion queue. The even passes
4270 * will write 1. The odd passes will write 0.
4272 #define HWRM_CMPL_V UINT32_C(0x1)
4273 /* unused4 is 32 b */
4275 } __attribute__((packed));
4277 /* hwrm_fwd_req_cmpl (size:128b/16B) */
4278 struct hwrm_fwd_req_cmpl {
4280 * This field indicates the exact type of the completion.
4281 * By convention, the LSB identifies the length of the
4282 * record in 16B units. Even values indicate 16B
4283 * records. Odd values indicate 32B
4286 uint16_t req_len_type;
4288 * This field indicates the exact type of the completion.
4289 * By convention, the LSB identifies the length of the
4290 * record in 16B units. Even values indicate 16B
4291 * records. Odd values indicate 32B
4294 #define HWRM_FWD_REQ_CMPL_TYPE_MASK UINT32_C(0x3f)
4295 #define HWRM_FWD_REQ_CMPL_TYPE_SFT 0
4296 /* Forwarded HWRM Request */
4297 #define HWRM_FWD_REQ_CMPL_TYPE_HWRM_FWD_REQ UINT32_C(0x22)
4298 #define HWRM_FWD_REQ_CMPL_TYPE_LAST \
4299 HWRM_FWD_REQ_CMPL_TYPE_HWRM_FWD_REQ
4300 /* Length of forwarded request in bytes. */
4301 #define HWRM_FWD_REQ_CMPL_REQ_LEN_MASK UINT32_C(0xffc0)
4302 #define HWRM_FWD_REQ_CMPL_REQ_LEN_SFT 6
4304 * Source ID of this request.
4305 * Typically used in forwarding requests and responses.
4306 * 0x0 - 0xFFF8 - Used for function ids
4307 * 0xFFF8 - 0xFFFE - Reserved for internal processors
4311 /* unused1 is 32 b */
4313 /* Address of forwarded request. */
4314 uint32_t req_buf_addr_v[2];
4316 * This value is written by the NIC such that it will be different
4317 * for each pass through the completion queue. The even passes
4318 * will write 1. The odd passes will write 0.
4320 #define HWRM_FWD_REQ_CMPL_V UINT32_C(0x1)
4321 /* Address of forwarded request. */
4322 #define HWRM_FWD_REQ_CMPL_REQ_BUF_ADDR_MASK UINT32_C(0xfffffffe)
4323 #define HWRM_FWD_REQ_CMPL_REQ_BUF_ADDR_SFT 1
4324 } __attribute__((packed));
4326 /* hwrm_fwd_resp_cmpl (size:128b/16B) */
4327 struct hwrm_fwd_resp_cmpl {
4330 * This field indicates the exact type of the completion.
4331 * By convention, the LSB identifies the length of the
4332 * record in 16B units. Even values indicate 16B
4333 * records. Odd values indicate 32B
4336 #define HWRM_FWD_RESP_CMPL_TYPE_MASK UINT32_C(0x3f)
4337 #define HWRM_FWD_RESP_CMPL_TYPE_SFT 0
4338 /* Forwarded HWRM Response */
4339 #define HWRM_FWD_RESP_CMPL_TYPE_HWRM_FWD_RESP UINT32_C(0x24)
4340 #define HWRM_FWD_RESP_CMPL_TYPE_LAST \
4341 HWRM_FWD_RESP_CMPL_TYPE_HWRM_FWD_RESP
4343 * Source ID of this response.
4344 * Typically used in forwarding requests and responses.
4345 * 0x0 - 0xFFF8 - Used for function ids
4346 * 0xFFF8 - 0xFFFE - Reserved for internal processors
4350 /* Length of forwarded response in bytes. */
4352 /* unused2 is 16 b */
4354 /* Address of forwarded request. */
4355 uint32_t resp_buf_addr_v[2];
4357 * This value is written by the NIC such that it will be different
4358 * for each pass through the completion queue. The even passes
4359 * will write 1. The odd passes will write 0.
4361 #define HWRM_FWD_RESP_CMPL_V UINT32_C(0x1)
4362 /* Address of forwarded request. */
4363 #define HWRM_FWD_RESP_CMPL_RESP_BUF_ADDR_MASK UINT32_C(0xfffffffe)
4364 #define HWRM_FWD_RESP_CMPL_RESP_BUF_ADDR_SFT 1
4365 } __attribute__((packed));
4367 /* hwrm_async_event_cmpl (size:128b/16B) */
4368 struct hwrm_async_event_cmpl {
4371 * This field indicates the exact type of the completion.
4372 * By convention, the LSB identifies the length of the
4373 * record in 16B units. Even values indicate 16B
4374 * records. Odd values indicate 32B
4377 #define HWRM_ASYNC_EVENT_CMPL_TYPE_MASK UINT32_C(0x3f)
4378 #define HWRM_ASYNC_EVENT_CMPL_TYPE_SFT 0
4379 /* HWRM Asynchronous Event Information */
4380 #define HWRM_ASYNC_EVENT_CMPL_TYPE_HWRM_ASYNC_EVENT UINT32_C(0x2e)
4381 #define HWRM_ASYNC_EVENT_CMPL_TYPE_LAST \
4382 HWRM_ASYNC_EVENT_CMPL_TYPE_HWRM_ASYNC_EVENT
4383 /* Identifiers of events. */
4385 /* Link status changed */
4386 #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_LINK_STATUS_CHANGE \
4388 /* Link MTU changed */
4389 #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_LINK_MTU_CHANGE \
4391 /* Link speed changed */
4392 #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_LINK_SPEED_CHANGE \
4394 /* DCB Configuration changed */
4395 #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_DCB_CONFIG_CHANGE \
4397 /* Port connection not allowed */
4398 #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_PORT_CONN_NOT_ALLOWED \
4400 /* Link speed configuration was not allowed */
4401 #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_LINK_SPEED_CFG_NOT_ALLOWED \
4403 /* Link speed configuration change */
4404 #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_LINK_SPEED_CFG_CHANGE \
4406 /* Port PHY configuration change */
4407 #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_PORT_PHY_CFG_CHANGE \
4409 /* Reset notification to clients */
4410 #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_RESET_NOTIFY \
4412 /* Master function selection event */
4413 #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_ERROR_RECOVERY \
4415 /* Function driver unloaded */
4416 #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_FUNC_DRVR_UNLOAD \
4418 /* Function driver loaded */
4419 #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_FUNC_DRVR_LOAD \
4421 /* Function FLR related processing has completed */
4422 #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_FUNC_FLR_PROC_CMPLT \
4424 /* PF driver unloaded */
4425 #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_PF_DRVR_UNLOAD \
4427 /* PF driver loaded */
4428 #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_PF_DRVR_LOAD \
4430 /* VF Function Level Reset (FLR) */
4431 #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_VF_FLR \
4433 /* VF MAC Address Change */
4434 #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_VF_MAC_ADDR_CHANGE \
4436 /* PF-VF communication channel status change. */
4437 #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_PF_VF_COMM_STATUS_CHANGE \
4439 /* VF Configuration Change */
4440 #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_VF_CFG_CHANGE \
4442 /* LLFC/PFC Configuration Change */
4443 #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_LLFC_PFC_CHANGE \
4445 /* Default VNIC Configuration Change */
4446 #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_DEFAULT_VNIC_CHANGE \
4449 #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_HW_FLOW_AGED \
4452 * A debug notification being posted to the driver. These
4453 * notifications are purely for diagnostic purpose and should not be
4454 * used for functional purpose. The driver is not supposed to act
4455 * on these messages except to log/record it.
4457 #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_DEBUG_NOTIFICATION \
4460 * An EEM flow cached memory flush for all flows request event being
4461 * posted to the PF driver.
4463 #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_EEM_CACHE_FLUSH_REQ \
4466 * An EEM flow cache memory flush completion event being posted to the
4467 * firmware by the PF driver. This is indication that host EEM flush
4468 * has completed by the PF.
4470 #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_EEM_CACHE_FLUSH_DONE \
4473 * A tcp flag action change event being posted to the PF or trusted VF
4474 * driver by the firmware. The PF or trusted VF driver should query
4475 * the firmware for the new TCP flag action update after receiving
4478 #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_TCP_FLAG_ACTION_CHANGE \
4481 * An EEM flow active event being posted to the PF or trusted VF driver
4482 * by the firmware. The PF or trusted VF driver should update the
4483 * flow's aging timer after receiving this async event.
4485 #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_EEM_FLOW_ACTIVE \
4488 * A eem cfg change event being posted to the trusted VF driver by the
4489 * firmware if the parent PF EEM configuration changed.
4491 #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_EEM_CFG_CHANGE \
4493 /* TFLIB unique default VNIC Configuration Change */
4494 #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_TFLIB_DEFAULT_VNIC_CHANGE \
4496 /* TFLIB unique link status changed */
4497 #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_TFLIB_LINK_STATUS_CHANGE \
4500 * A trace log message. This contains firmware trace logs string
4501 * embedded in the asynchronous message. This is an experimental
4502 * event, not meant for production use at this time.
4504 #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_FW_TRACE_MSG \
4507 #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_HWRM_ERROR \
4509 #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_LAST \
4510 HWRM_ASYNC_EVENT_CMPL_EVENT_ID_HWRM_ERROR
4511 /* Event specific data */
4512 uint32_t event_data2;
4515 * This value is written by the NIC such that it will be different
4516 * for each pass through the completion queue. The even passes
4517 * will write 1. The odd passes will write 0.
4519 #define HWRM_ASYNC_EVENT_CMPL_V UINT32_C(0x1)
4521 #define HWRM_ASYNC_EVENT_CMPL_OPAQUE_MASK UINT32_C(0xfe)
4522 #define HWRM_ASYNC_EVENT_CMPL_OPAQUE_SFT 1
4523 /* 8-lsb timestamp from POR (100-msec resolution) */
4524 uint8_t timestamp_lo;
4525 /* 16-lsb timestamp from POR (100-msec resolution) */
4526 uint16_t timestamp_hi;
4527 /* Event specific data */
4528 uint32_t event_data1;
4529 } __attribute__((packed));
4531 /* hwrm_async_event_cmpl_link_status_change (size:128b/16B) */
4532 struct hwrm_async_event_cmpl_link_status_change {
4535 * This field indicates the exact type of the completion.
4536 * By convention, the LSB identifies the length of the
4537 * record in 16B units. Even values indicate 16B
4538 * records. Odd values indicate 32B
4541 #define HWRM_ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_TYPE_MASK \
4543 #define HWRM_ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_TYPE_SFT 0
4544 /* HWRM Asynchronous Event Information */
4545 #define HWRM_ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_TYPE_HWRM_ASYNC_EVENT \
4547 #define HWRM_ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_TYPE_LAST \
4548 HWRM_ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_TYPE_HWRM_ASYNC_EVENT
4549 /* Identifiers of events. */
4551 /* Link status changed */
4552 #define HWRM_ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_ID_LINK_STATUS_CHANGE \
4554 #define HWRM_ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_ID_LAST \
4555 HWRM_ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_ID_LINK_STATUS_CHANGE
4556 /* Event specific data */
4557 uint32_t event_data2;
4560 * This value is written by the NIC such that it will be different
4561 * for each pass through the completion queue. The even passes
4562 * will write 1. The odd passes will write 0.
4564 #define HWRM_ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_V \
4567 #define HWRM_ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_OPAQUE_MASK \
4569 #define HWRM_ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_OPAQUE_SFT 1
4570 /* 8-lsb timestamp from POR (100-msec resolution) */
4571 uint8_t timestamp_lo;
4572 /* 16-lsb timestamp from POR (100-msec resolution) */
4573 uint16_t timestamp_hi;
4574 /* Event specific data */
4575 uint32_t event_data1;
4576 /* Indicates link status change */
4577 #define HWRM_ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_DATA1_LINK_CHANGE \
4580 * If this bit set to 0, then it indicates that the link
4581 * was up and it went down.
4583 #define HWRM_ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_DATA1_LINK_CHANGE_DOWN \
4586 * If this bit is set to 1, then it indicates that the link
4587 * was down and it went up.
4589 #define HWRM_ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_DATA1_LINK_CHANGE_UP \
4591 #define HWRM_ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_DATA1_LINK_CHANGE_LAST \
4592 HWRM_ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_DATA1_LINK_CHANGE_UP
4593 /* Indicates the physical port this link status change occur */
4594 #define HWRM_ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_DATA1_PORT_MASK \
4596 #define HWRM_ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_DATA1_PORT_SFT \
4599 #define HWRM_ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_DATA1_PORT_ID_MASK \
4601 #define HWRM_ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_DATA1_PORT_ID_SFT \
4603 /* Indicates the physical function this event occurred on. */
4604 #define HWRM_ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_DATA1_PF_ID_MASK \
4606 #define HWRM_ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_DATA1_PF_ID_SFT \
4608 } __attribute__((packed));
4610 /* hwrm_async_event_cmpl_link_mtu_change (size:128b/16B) */
4611 struct hwrm_async_event_cmpl_link_mtu_change {
4614 * This field indicates the exact type of the completion.
4615 * By convention, the LSB identifies the length of the
4616 * record in 16B units. Even values indicate 16B
4617 * records. Odd values indicate 32B
4620 #define HWRM_ASYNC_EVENT_CMPL_LINK_MTU_CHANGE_TYPE_MASK \
4622 #define HWRM_ASYNC_EVENT_CMPL_LINK_MTU_CHANGE_TYPE_SFT 0
4623 /* HWRM Asynchronous Event Information */
4624 #define HWRM_ASYNC_EVENT_CMPL_LINK_MTU_CHANGE_TYPE_HWRM_ASYNC_EVENT \
4626 #define HWRM_ASYNC_EVENT_CMPL_LINK_MTU_CHANGE_TYPE_LAST \
4627 HWRM_ASYNC_EVENT_CMPL_LINK_MTU_CHANGE_TYPE_HWRM_ASYNC_EVENT
4628 /* Identifiers of events. */
4630 /* Link MTU changed */
4631 #define HWRM_ASYNC_EVENT_CMPL_LINK_MTU_CHANGE_EVENT_ID_LINK_MTU_CHANGE \
4633 #define HWRM_ASYNC_EVENT_CMPL_LINK_MTU_CHANGE_EVENT_ID_LAST \
4634 HWRM_ASYNC_EVENT_CMPL_LINK_MTU_CHANGE_EVENT_ID_LINK_MTU_CHANGE
4635 /* Event specific data */
4636 uint32_t event_data2;
4639 * This value is written by the NIC such that it will be different
4640 * for each pass through the completion queue. The even passes
4641 * will write 1. The odd passes will write 0.
4643 #define HWRM_ASYNC_EVENT_CMPL_LINK_MTU_CHANGE_V UINT32_C(0x1)
4645 #define HWRM_ASYNC_EVENT_CMPL_LINK_MTU_CHANGE_OPAQUE_MASK \
4647 #define HWRM_ASYNC_EVENT_CMPL_LINK_MTU_CHANGE_OPAQUE_SFT 1
4648 /* 8-lsb timestamp from POR (100-msec resolution) */
4649 uint8_t timestamp_lo;
4650 /* 16-lsb timestamp from POR (100-msec resolution) */
4651 uint16_t timestamp_hi;
4652 /* Event specific data */
4653 uint32_t event_data1;
4654 /* The new MTU of the link in bytes. */
4655 #define HWRM_ASYNC_EVENT_CMPL_LINK_MTU_CHANGE_EVENT_DATA1_NEW_MTU_MASK \
4657 #define HWRM_ASYNC_EVENT_CMPL_LINK_MTU_CHANGE_EVENT_DATA1_NEW_MTU_SFT 0
4658 } __attribute__((packed));
4660 /* hwrm_async_event_cmpl_link_speed_change (size:128b/16B) */
4661 struct hwrm_async_event_cmpl_link_speed_change {
4664 * This field indicates the exact type of the completion.
4665 * By convention, the LSB identifies the length of the
4666 * record in 16B units. Even values indicate 16B
4667 * records. Odd values indicate 32B
4670 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_TYPE_MASK \
4672 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_TYPE_SFT 0
4673 /* HWRM Asynchronous Event Information */
4674 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_TYPE_HWRM_ASYNC_EVENT \
4676 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_TYPE_LAST \
4677 HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_TYPE_HWRM_ASYNC_EVENT
4678 /* Identifiers of events. */
4680 /* Link speed changed */
4681 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_EVENT_ID_LINK_SPEED_CHANGE \
4683 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_EVENT_ID_LAST \
4684 HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_EVENT_ID_LINK_SPEED_CHANGE
4685 /* Event specific data */
4686 uint32_t event_data2;
4689 * This value is written by the NIC such that it will be different
4690 * for each pass through the completion queue. The even passes
4691 * will write 1. The odd passes will write 0.
4693 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_V \
4696 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_OPAQUE_MASK \
4698 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_OPAQUE_SFT 1
4699 /* 8-lsb timestamp from POR (100-msec resolution) */
4700 uint8_t timestamp_lo;
4701 /* 16-lsb timestamp from POR (100-msec resolution) */
4702 uint16_t timestamp_hi;
4703 /* Event specific data */
4704 uint32_t event_data1;
4706 * When this bit is '1', the link was forced to the
4707 * force_link_speed value.
4709 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_EVENT_DATA1_FORCE \
4711 /* The new link speed in 100 Mbps units. */
4712 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_EVENT_DATA1_NEW_LINK_SPEED_100MBPS_MASK \
4714 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_EVENT_DATA1_NEW_LINK_SPEED_100MBPS_SFT \
4716 /* 100Mb link speed */
4717 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_EVENT_DATA1_NEW_LINK_SPEED_100MBPS_100MB \
4718 (UINT32_C(0x1) << 1)
4719 /* 1Gb link speed */
4720 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_EVENT_DATA1_NEW_LINK_SPEED_100MBPS_1GB \
4721 (UINT32_C(0xa) << 1)
4722 /* 2Gb link speed */
4723 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_EVENT_DATA1_NEW_LINK_SPEED_100MBPS_2GB \
4724 (UINT32_C(0x14) << 1)
4725 /* 25Gb link speed */
4726 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_EVENT_DATA1_NEW_LINK_SPEED_100MBPS_2_5GB \
4727 (UINT32_C(0x19) << 1)
4728 /* 10Gb link speed */
4729 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_EVENT_DATA1_NEW_LINK_SPEED_100MBPS_10GB \
4730 (UINT32_C(0x64) << 1)
4731 /* 20Mb link speed */
4732 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_EVENT_DATA1_NEW_LINK_SPEED_100MBPS_20GB \
4733 (UINT32_C(0xc8) << 1)
4734 /* 25Gb link speed */
4735 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_EVENT_DATA1_NEW_LINK_SPEED_100MBPS_25GB \
4736 (UINT32_C(0xfa) << 1)
4737 /* 40Gb link speed */
4738 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_EVENT_DATA1_NEW_LINK_SPEED_100MBPS_40GB \
4739 (UINT32_C(0x190) << 1)
4740 /* 50Gb link speed */
4741 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_EVENT_DATA1_NEW_LINK_SPEED_100MBPS_50GB \
4742 (UINT32_C(0x1f4) << 1)
4743 /* 100Gb link speed */
4744 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_EVENT_DATA1_NEW_LINK_SPEED_100MBPS_100GB \
4745 (UINT32_C(0x3e8) << 1)
4746 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_EVENT_DATA1_NEW_LINK_SPEED_100MBPS_LAST \
4747 HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_EVENT_DATA1_NEW_LINK_SPEED_100MBPS_100GB
4749 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_EVENT_DATA1_PORT_ID_MASK \
4750 UINT32_C(0xffff0000)
4751 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_EVENT_DATA1_PORT_ID_SFT \
4753 } __attribute__((packed));
4755 /* hwrm_async_event_cmpl_dcb_config_change (size:128b/16B) */
4756 struct hwrm_async_event_cmpl_dcb_config_change {
4759 * This field indicates the exact type of the completion.
4760 * By convention, the LSB identifies the length of the
4761 * record in 16B units. Even values indicate 16B
4762 * records. Odd values indicate 32B
4765 #define HWRM_ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_TYPE_MASK \
4767 #define HWRM_ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_TYPE_SFT 0
4768 /* HWRM Asynchronous Event Information */
4769 #define HWRM_ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_TYPE_HWRM_ASYNC_EVENT \
4771 #define HWRM_ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_TYPE_LAST \
4772 HWRM_ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_TYPE_HWRM_ASYNC_EVENT
4773 /* Identifiers of events. */
4775 /* DCB Configuration changed */
4776 #define HWRM_ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_EVENT_ID_DCB_CONFIG_CHANGE \
4778 #define HWRM_ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_EVENT_ID_LAST \
4779 HWRM_ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_EVENT_ID_DCB_CONFIG_CHANGE
4780 /* Event specific data */
4781 uint32_t event_data2;
4782 /* ETS configuration change */
4783 #define HWRM_ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_EVENT_DATA2_ETS \
4785 /* PFC configuration change */
4786 #define HWRM_ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_EVENT_DATA2_PFC \
4788 /* APP configuration change */
4789 #define HWRM_ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_EVENT_DATA2_APP \
4793 * This value is written by the NIC such that it will be different
4794 * for each pass through the completion queue. The even passes
4795 * will write 1. The odd passes will write 0.
4797 #define HWRM_ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_V \
4800 #define HWRM_ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_OPAQUE_MASK \
4802 #define HWRM_ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_OPAQUE_SFT 1
4803 /* 8-lsb timestamp from POR (100-msec resolution) */
4804 uint8_t timestamp_lo;
4805 /* 16-lsb timestamp from POR (100-msec resolution) */
4806 uint16_t timestamp_hi;
4807 /* Event specific data */
4808 uint32_t event_data1;
4810 #define HWRM_ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_EVENT_DATA1_PORT_ID_MASK \
4812 #define HWRM_ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_EVENT_DATA1_PORT_ID_SFT \
4814 /* Priority recommended for RoCE traffic */
4815 #define HWRM_ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_EVENT_DATA1_RECOMMEND_ROCE_PRIORITY_MASK \
4817 #define HWRM_ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_EVENT_DATA1_RECOMMEND_ROCE_PRIORITY_SFT \
4820 #define HWRM_ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_EVENT_DATA1_RECOMMEND_ROCE_PRIORITY_NONE \
4821 (UINT32_C(0xff) << 16)
4822 #define HWRM_ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_EVENT_DATA1_RECOMMEND_ROCE_PRIORITY_LAST \
4823 HWRM_ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_EVENT_DATA1_RECOMMEND_ROCE_PRIORITY_NONE
4824 /* Priority recommended for L2 traffic */
4825 #define HWRM_ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_EVENT_DATA1_RECOMMEND_L2_PRIORITY_MASK \
4826 UINT32_C(0xff000000)
4827 #define HWRM_ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_EVENT_DATA1_RECOMMEND_L2_PRIORITY_SFT \
4830 #define HWRM_ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_EVENT_DATA1_RECOMMEND_L2_PRIORITY_NONE \
4831 (UINT32_C(0xff) << 24)
4832 #define HWRM_ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_EVENT_DATA1_RECOMMEND_L2_PRIORITY_LAST \
4833 HWRM_ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_EVENT_DATA1_RECOMMEND_L2_PRIORITY_NONE
4834 } __attribute__((packed));
4836 /* hwrm_async_event_cmpl_port_conn_not_allowed (size:128b/16B) */
4837 struct hwrm_async_event_cmpl_port_conn_not_allowed {
4840 * This field indicates the exact type of the completion.
4841 * By convention, the LSB identifies the length of the
4842 * record in 16B units. Even values indicate 16B
4843 * records. Odd values indicate 32B
4846 #define HWRM_ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_TYPE_MASK \
4848 #define HWRM_ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_TYPE_SFT \
4850 /* HWRM Asynchronous Event Information */
4851 #define HWRM_ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_TYPE_HWRM_ASYNC_EVENT \
4853 #define HWRM_ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_TYPE_LAST \
4854 HWRM_ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_TYPE_HWRM_ASYNC_EVENT
4855 /* Identifiers of events. */
4857 /* Port connection not allowed */
4858 #define HWRM_ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_ID_PORT_CONN_NOT_ALLOWED \
4860 #define HWRM_ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_ID_LAST \
4861 HWRM_ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_ID_PORT_CONN_NOT_ALLOWED
4862 /* Event specific data */
4863 uint32_t event_data2;
4866 * This value is written by the NIC such that it will be different
4867 * for each pass through the completion queue. The even passes
4868 * will write 1. The odd passes will write 0.
4870 #define HWRM_ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_V \
4873 #define HWRM_ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_OPAQUE_MASK \
4875 #define HWRM_ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_OPAQUE_SFT 1
4876 /* 8-lsb timestamp from POR (100-msec resolution) */
4877 uint8_t timestamp_lo;
4878 /* 16-lsb timestamp from POR (100-msec resolution) */
4879 uint16_t timestamp_hi;
4880 /* Event specific data */
4881 uint32_t event_data1;
4883 #define HWRM_ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_PORT_ID_MASK \
4885 #define HWRM_ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_PORT_ID_SFT \
4888 * This value indicates the current port level enforcement policy
4889 * for the optics module when there is an optical module mismatch
4890 * and port is not connected.
4892 #define HWRM_ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_ENFORCEMENT_POLICY_MASK \
4894 #define HWRM_ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_ENFORCEMENT_POLICY_SFT \
4896 /* No enforcement */
4897 #define HWRM_ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_ENFORCEMENT_POLICY_NONE \
4898 (UINT32_C(0x0) << 16)
4899 /* Disable Transmit side Laser. */
4900 #define HWRM_ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_ENFORCEMENT_POLICY_DISABLETX \
4901 (UINT32_C(0x1) << 16)
4902 /* Raise a warning message. */
4903 #define HWRM_ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_ENFORCEMENT_POLICY_WARNINGMSG \
4904 (UINT32_C(0x2) << 16)
4905 /* Power down the module. */
4906 #define HWRM_ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_ENFORCEMENT_POLICY_PWRDOWN \
4907 (UINT32_C(0x3) << 16)
4908 #define HWRM_ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_ENFORCEMENT_POLICY_LAST \
4909 HWRM_ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_ENFORCEMENT_POLICY_PWRDOWN
4910 } __attribute__((packed));
4912 /* hwrm_async_event_cmpl_link_speed_cfg_not_allowed (size:128b/16B) */
4913 struct hwrm_async_event_cmpl_link_speed_cfg_not_allowed {
4916 * This field indicates the exact type of the completion.
4917 * By convention, the LSB identifies the length of the
4918 * record in 16B units. Even values indicate 16B
4919 * records. Odd values indicate 32B
4922 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_NOT_ALLOWED_TYPE_MASK \
4924 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_NOT_ALLOWED_TYPE_SFT \
4926 /* HWRM Asynchronous Event Information */
4927 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_NOT_ALLOWED_TYPE_HWRM_ASYNC_EVENT \
4929 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_NOT_ALLOWED_TYPE_LAST \
4930 HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_NOT_ALLOWED_TYPE_HWRM_ASYNC_EVENT
4931 /* Identifiers of events. */
4933 /* Link speed configuration was not allowed */
4934 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_NOT_ALLOWED_EVENT_ID_LINK_SPEED_CFG_NOT_ALLOWED \
4936 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_NOT_ALLOWED_EVENT_ID_LAST \
4937 HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_NOT_ALLOWED_EVENT_ID_LINK_SPEED_CFG_NOT_ALLOWED
4938 /* Event specific data */
4939 uint32_t event_data2;
4942 * This value is written by the NIC such that it will be different
4943 * for each pass through the completion queue. The even passes
4944 * will write 1. The odd passes will write 0.
4946 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_NOT_ALLOWED_V \
4949 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_NOT_ALLOWED_OPAQUE_MASK \
4951 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_NOT_ALLOWED_OPAQUE_SFT 1
4952 /* 8-lsb timestamp from POR (100-msec resolution) */
4953 uint8_t timestamp_lo;
4954 /* 16-lsb timestamp from POR (100-msec resolution) */
4955 uint16_t timestamp_hi;
4956 /* Event specific data */
4957 uint32_t event_data1;
4959 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_NOT_ALLOWED_EVENT_DATA1_PORT_ID_MASK \
4961 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_NOT_ALLOWED_EVENT_DATA1_PORT_ID_SFT \
4963 } __attribute__((packed));
4965 /* hwrm_async_event_cmpl_link_speed_cfg_change (size:128b/16B) */
4966 struct hwrm_async_event_cmpl_link_speed_cfg_change {
4969 * This field indicates the exact type of the completion.
4970 * By convention, the LSB identifies the length of the
4971 * record in 16B units. Even values indicate 16B
4972 * records. Odd values indicate 32B
4975 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_TYPE_MASK \
4977 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_TYPE_SFT \
4979 /* HWRM Asynchronous Event Information */
4980 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_TYPE_HWRM_ASYNC_EVENT \
4982 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_TYPE_LAST \
4983 HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_TYPE_HWRM_ASYNC_EVENT
4984 /* Identifiers of events. */
4986 /* Link speed configuration change */
4987 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_EVENT_ID_LINK_SPEED_CFG_CHANGE \
4989 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_EVENT_ID_LAST \
4990 HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_EVENT_ID_LINK_SPEED_CFG_CHANGE
4991 /* Event specific data */
4992 uint32_t event_data2;
4995 * This value is written by the NIC such that it will be different
4996 * for each pass through the completion queue. The even passes
4997 * will write 1. The odd passes will write 0.
4999 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_V \
5002 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_OPAQUE_MASK \
5004 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_OPAQUE_SFT 1
5005 /* 8-lsb timestamp from POR (100-msec resolution) */
5006 uint8_t timestamp_lo;
5007 /* 16-lsb timestamp from POR (100-msec resolution) */
5008 uint16_t timestamp_hi;
5009 /* Event specific data */
5010 uint32_t event_data1;
5012 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_EVENT_DATA1_PORT_ID_MASK \
5014 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_EVENT_DATA1_PORT_ID_SFT \
5017 * If set to 1, it indicates that the supported link speeds
5018 * configuration on the port has changed.
5019 * If set to 0, then there is no change in supported link speeds
5022 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_EVENT_DATA1_SUPPORTED_LINK_SPEEDS_CHANGE \
5025 * If set to 1, it indicates that the link speed configuration
5026 * on the port has become illegal or invalid.
5027 * If set to 0, then the link speed configuration on the port is
5030 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_EVENT_DATA1_ILLEGAL_LINK_SPEED_CFG \
5032 } __attribute__((packed));
5034 /* hwrm_async_event_cmpl_port_phy_cfg_change (size:128b/16B) */
5035 struct hwrm_async_event_cmpl_port_phy_cfg_change {
5038 * This field indicates the exact type of the completion.
5039 * By convention, the LSB identifies the length of the
5040 * record in 16B units. Even values indicate 16B
5041 * records. Odd values indicate 32B
5044 #define HWRM_ASYNC_EVENT_CMPL_PORT_PHY_CFG_CHANGE_TYPE_MASK \
5046 #define HWRM_ASYNC_EVENT_CMPL_PORT_PHY_CFG_CHANGE_TYPE_SFT \
5048 /* HWRM Asynchronous Event Information */
5049 #define HWRM_ASYNC_EVENT_CMPL_PORT_PHY_CFG_CHANGE_TYPE_HWRM_ASYNC_EVENT \
5051 #define HWRM_ASYNC_EVENT_CMPL_PORT_PHY_CFG_CHANGE_TYPE_LAST \
5052 HWRM_ASYNC_EVENT_CMPL_PORT_PHY_CFG_CHANGE_TYPE_HWRM_ASYNC_EVENT
5053 /* Identifiers of events. */
5055 /* Port PHY configuration change */
5056 #define HWRM_ASYNC_EVENT_CMPL_PORT_PHY_CFG_CHANGE_EVENT_ID_PORT_PHY_CFG_CHANGE \
5058 #define HWRM_ASYNC_EVENT_CMPL_PORT_PHY_CFG_CHANGE_EVENT_ID_LAST \
5059 HWRM_ASYNC_EVENT_CMPL_PORT_PHY_CFG_CHANGE_EVENT_ID_PORT_PHY_CFG_CHANGE
5060 /* Event specific data */
5061 uint32_t event_data2;
5064 * This value is written by the NIC such that it will be different
5065 * for each pass through the completion queue. The even passes
5066 * will write 1. The odd passes will write 0.
5068 #define HWRM_ASYNC_EVENT_CMPL_PORT_PHY_CFG_CHANGE_V \
5071 #define HWRM_ASYNC_EVENT_CMPL_PORT_PHY_CFG_CHANGE_OPAQUE_MASK \
5073 #define HWRM_ASYNC_EVENT_CMPL_PORT_PHY_CFG_CHANGE_OPAQUE_SFT 1
5074 /* 8-lsb timestamp from POR (100-msec resolution) */
5075 uint8_t timestamp_lo;
5076 /* 16-lsb timestamp from POR (100-msec resolution) */
5077 uint16_t timestamp_hi;
5078 /* Event specific data */
5079 uint32_t event_data1;
5081 #define HWRM_ASYNC_EVENT_CMPL_PORT_PHY_CFG_CHANGE_EVENT_DATA1_PORT_ID_MASK \
5083 #define HWRM_ASYNC_EVENT_CMPL_PORT_PHY_CFG_CHANGE_EVENT_DATA1_PORT_ID_SFT \
5086 * If set to 1, it indicates that the FEC
5087 * configuration on the port has changed.
5088 * If set to 0, then there is no change in FEC configuration.
5090 #define HWRM_ASYNC_EVENT_CMPL_PORT_PHY_CFG_CHANGE_EVENT_DATA1_FEC_CFG_CHANGE \
5093 * If set to 1, it indicates that the EEE configuration
5094 * on the port has changed.
5095 * If set to 0, then there is no change in EEE configuration
5098 #define HWRM_ASYNC_EVENT_CMPL_PORT_PHY_CFG_CHANGE_EVENT_DATA1_EEE_CFG_CHANGE \
5101 * If set to 1, it indicates that the pause configuration
5102 * on the PHY has changed.
5103 * If set to 0, then there is no change in the pause
5104 * configuration on the PHY.
5106 #define HWRM_ASYNC_EVENT_CMPL_PORT_PHY_CFG_CHANGE_EVENT_DATA1_PAUSE_CFG_CHANGE \
5108 } __attribute__((packed));
5110 /* hwrm_async_event_cmpl_reset_notify (size:128b/16B) */
5111 struct hwrm_async_event_cmpl_reset_notify {
5114 * This field indicates the exact type of the completion.
5115 * By convention, the LSB identifies the length of the
5116 * record in 16B units. Even values indicate 16B
5117 * records. Odd values indicate 32B
5120 #define HWRM_ASYNC_EVENT_CMPL_RESET_NOTIFY_TYPE_MASK \
5122 #define HWRM_ASYNC_EVENT_CMPL_RESET_NOTIFY_TYPE_SFT 0
5123 /* HWRM Asynchronous Event Information */
5124 #define HWRM_ASYNC_EVENT_CMPL_RESET_NOTIFY_TYPE_HWRM_ASYNC_EVENT \
5126 #define HWRM_ASYNC_EVENT_CMPL_RESET_NOTIFY_TYPE_LAST \
5127 HWRM_ASYNC_EVENT_CMPL_RESET_NOTIFY_TYPE_HWRM_ASYNC_EVENT
5128 /* Identifiers of events. */
5130 /* Notify clients of imminent reset. */
5131 #define HWRM_ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_ID_RESET_NOTIFY \
5133 #define HWRM_ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_ID_LAST \
5134 HWRM_ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_ID_RESET_NOTIFY
5135 /* Event specific data */
5136 uint32_t event_data2;
5139 * This value is written by the NIC such that it will be different
5140 * for each pass through the completion queue. The even passes
5141 * will write 1. The odd passes will write 0.
5143 #define HWRM_ASYNC_EVENT_CMPL_RESET_NOTIFY_V UINT32_C(0x1)
5145 #define HWRM_ASYNC_EVENT_CMPL_RESET_NOTIFY_OPAQUE_MASK UINT32_C(0xfe)
5146 #define HWRM_ASYNC_EVENT_CMPL_RESET_NOTIFY_OPAQUE_SFT 1
5148 * 8-lsb timestamp (100-msec resolution)
5149 * The Minimum time required for the Firmware readiness after sending this
5150 * notification to the driver instances.
5152 uint8_t timestamp_lo;
5154 * 16-lsb timestamp (100-msec resolution)
5155 * The Maximum Firmware Reset bail out value in the order of 100
5156 * milli seconds. The driver instances will use this value to re-initiate the
5157 * registration process again if the core firmware didn’t set the ready
5160 uint16_t timestamp_hi;
5161 /* Event specific data */
5162 uint32_t event_data1;
5163 /* Indicates driver action requested */
5164 #define HWRM_ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_DRIVER_ACTION_MASK \
5166 #define HWRM_ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_DRIVER_ACTION_SFT \
5169 * If set to 1, it indicates that the l2 client should
5170 * stop sending in band traffic to Nitro.
5171 * if set to 0, there is no change in L2 client behavior.
5173 #define HWRM_ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_DRIVER_ACTION_DRIVER_STOP_TX_QUEUE \
5176 * If set to 1, it indicates that the L2 client should
5177 * bring down the interface.
5178 * If set to 0, then there is no change in L2 client behavior.
5180 #define HWRM_ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_DRIVER_ACTION_DRIVER_IFDOWN \
5182 #define HWRM_ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_DRIVER_ACTION_LAST \
5183 HWRM_ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_DRIVER_ACTION_DRIVER_IFDOWN
5184 /* Indicates reason for reset. */
5185 #define HWRM_ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_REASON_CODE_MASK \
5187 #define HWRM_ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_REASON_CODE_SFT \
5189 /* A management client has requested reset. */
5190 #define HWRM_ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_REASON_CODE_MANAGEMENT_RESET_REQUEST \
5191 (UINT32_C(0x1) << 8)
5192 /* A fatal firmware exception has occurred. */
5193 #define HWRM_ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_REASON_CODE_FW_EXCEPTION_FATAL \
5194 (UINT32_C(0x2) << 8)
5195 /* A non-fatal firmware exception has occurred. */
5196 #define HWRM_ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_REASON_CODE_FW_EXCEPTION_NON_FATAL \
5197 (UINT32_C(0x3) << 8)
5198 #define HWRM_ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_REASON_CODE_LAST \
5199 HWRM_ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_REASON_CODE_FW_EXCEPTION_NON_FATAL
5201 * Minimum time before driver should attempt access - units 100ms ticks.
5204 #define HWRM_ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_DELAY_IN_100MS_TICKS_MASK \
5205 UINT32_C(0xffff0000)
5206 #define HWRM_ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_DELAY_IN_100MS_TICKS_SFT \
5208 } __attribute__((packed));
5210 /* hwrm_async_event_cmpl_error_recovery (size:128b/16B) */
5211 struct hwrm_async_event_cmpl_error_recovery {
5214 * This field indicates the exact type of the completion.
5215 * By convention, the LSB identifies the length of the
5216 * record in 16B units. Even values indicate 16B
5217 * records. Odd values indicate 32B
5220 #define HWRM_ASYNC_EVENT_CMPL_ERROR_RECOVERY_TYPE_MASK \
5222 #define HWRM_ASYNC_EVENT_CMPL_ERROR_RECOVERY_TYPE_SFT 0
5223 /* HWRM Asynchronous Event Information */
5224 #define HWRM_ASYNC_EVENT_CMPL_ERROR_RECOVERY_TYPE_HWRM_ASYNC_EVENT \
5226 #define HWRM_ASYNC_EVENT_CMPL_ERROR_RECOVERY_TYPE_LAST \
5227 HWRM_ASYNC_EVENT_CMPL_ERROR_RECOVERY_TYPE_HWRM_ASYNC_EVENT
5228 /* Identifiers of events. */
5231 * This async notification message can be used for selecting or
5232 * deselecting master function for error recovery,
5233 * and to communicate to all the functions whether error recovery
5234 * was enabled/disabled.
5236 #define HWRM_ASYNC_EVENT_CMPL_ERROR_RECOVERY_EVENT_ID_ERROR_RECOVERY \
5238 #define HWRM_ASYNC_EVENT_CMPL_ERROR_RECOVERY_EVENT_ID_LAST \
5239 HWRM_ASYNC_EVENT_CMPL_ERROR_RECOVERY_EVENT_ID_ERROR_RECOVERY
5240 /* Event specific data */
5241 uint32_t event_data2;
5244 * This value is written by the NIC such that it will be different
5245 * for each pass through the completion queue. The even passes
5246 * will write 1. The odd passes will write 0.
5248 #define HWRM_ASYNC_EVENT_CMPL_ERROR_RECOVERY_V UINT32_C(0x1)
5250 #define HWRM_ASYNC_EVENT_CMPL_ERROR_RECOVERY_OPAQUE_MASK UINT32_C(0xfe)
5251 #define HWRM_ASYNC_EVENT_CMPL_ERROR_RECOVERY_OPAQUE_SFT 1
5252 /* 8-lsb timestamp (100-msec resolution) */
5253 uint8_t timestamp_lo;
5254 /* 16-lsb timestamp (100-msec resolution) */
5255 uint16_t timestamp_hi;
5256 /* Event specific data */
5257 uint32_t event_data1;
5258 /* Indicates driver action requested */
5259 #define HWRM_ASYNC_EVENT_CMPL_ERROR_RECOVERY_EVENT_DATA1_FLAGS_MASK \
5261 #define HWRM_ASYNC_EVENT_CMPL_ERROR_RECOVERY_EVENT_DATA1_FLAGS_SFT \
5264 * If set to 1, this function is selected as Master function.
5265 * This function has responsibility to do 'chip reset' when it
5266 * detects a fatal error. If set to 0, master function functionality
5267 * is disabled on this function.
5269 #define HWRM_ASYNC_EVENT_CMPL_ERROR_RECOVERY_EVENT_DATA1_FLAGS_MASTER_FUNC \
5272 * If set to 1, error recovery is enabled.
5273 * If set to 0, error recovery is disabled.
5275 #define HWRM_ASYNC_EVENT_CMPL_ERROR_RECOVERY_EVENT_DATA1_FLAGS_RECOVERY_ENABLED \
5277 } __attribute__((packed));
5279 /* hwrm_async_event_cmpl_func_drvr_unload (size:128b/16B) */
5280 struct hwrm_async_event_cmpl_func_drvr_unload {
5283 * This field indicates the exact type of the completion.
5284 * By convention, the LSB identifies the length of the
5285 * record in 16B units. Even values indicate 16B
5286 * records. Odd values indicate 32B
5289 #define HWRM_ASYNC_EVENT_CMPL_FUNC_DRVR_UNLOAD_TYPE_MASK \
5291 #define HWRM_ASYNC_EVENT_CMPL_FUNC_DRVR_UNLOAD_TYPE_SFT 0
5292 /* HWRM Asynchronous Event Information */
5293 #define HWRM_ASYNC_EVENT_CMPL_FUNC_DRVR_UNLOAD_TYPE_HWRM_ASYNC_EVENT \
5295 #define HWRM_ASYNC_EVENT_CMPL_FUNC_DRVR_UNLOAD_TYPE_LAST \
5296 HWRM_ASYNC_EVENT_CMPL_FUNC_DRVR_UNLOAD_TYPE_HWRM_ASYNC_EVENT
5297 /* Identifiers of events. */
5299 /* Function driver unloaded */
5300 #define HWRM_ASYNC_EVENT_CMPL_FUNC_DRVR_UNLOAD_EVENT_ID_FUNC_DRVR_UNLOAD \
5302 #define HWRM_ASYNC_EVENT_CMPL_FUNC_DRVR_UNLOAD_EVENT_ID_LAST \
5303 HWRM_ASYNC_EVENT_CMPL_FUNC_DRVR_UNLOAD_EVENT_ID_FUNC_DRVR_UNLOAD
5304 /* Event specific data */
5305 uint32_t event_data2;
5308 * This value is written by the NIC such that it will be different
5309 * for each pass through the completion queue. The even passes
5310 * will write 1. The odd passes will write 0.
5312 #define HWRM_ASYNC_EVENT_CMPL_FUNC_DRVR_UNLOAD_V UINT32_C(0x1)
5314 #define HWRM_ASYNC_EVENT_CMPL_FUNC_DRVR_UNLOAD_OPAQUE_MASK \
5316 #define HWRM_ASYNC_EVENT_CMPL_FUNC_DRVR_UNLOAD_OPAQUE_SFT 1
5317 /* 8-lsb timestamp from POR (100-msec resolution) */
5318 uint8_t timestamp_lo;
5319 /* 16-lsb timestamp from POR (100-msec resolution) */
5320 uint16_t timestamp_hi;
5321 /* Event specific data */
5322 uint32_t event_data1;
5324 #define HWRM_ASYNC_EVENT_CMPL_FUNC_DRVR_UNLOAD_EVENT_DATA1_FUNC_ID_MASK \
5326 #define HWRM_ASYNC_EVENT_CMPL_FUNC_DRVR_UNLOAD_EVENT_DATA1_FUNC_ID_SFT \
5328 } __attribute__((packed));
5330 /* hwrm_async_event_cmpl_func_drvr_load (size:128b/16B) */
5331 struct hwrm_async_event_cmpl_func_drvr_load {
5334 * This field indicates the exact type of the completion.
5335 * By convention, the LSB identifies the length of the
5336 * record in 16B units. Even values indicate 16B
5337 * records. Odd values indicate 32B
5340 #define HWRM_ASYNC_EVENT_CMPL_FUNC_DRVR_LOAD_TYPE_MASK \
5342 #define HWRM_ASYNC_EVENT_CMPL_FUNC_DRVR_LOAD_TYPE_SFT 0
5343 /* HWRM Asynchronous Event Information */
5344 #define HWRM_ASYNC_EVENT_CMPL_FUNC_DRVR_LOAD_TYPE_HWRM_ASYNC_EVENT \
5346 #define HWRM_ASYNC_EVENT_CMPL_FUNC_DRVR_LOAD_TYPE_LAST \
5347 HWRM_ASYNC_EVENT_CMPL_FUNC_DRVR_LOAD_TYPE_HWRM_ASYNC_EVENT
5348 /* Identifiers of events. */
5350 /* Function driver loaded */
5351 #define HWRM_ASYNC_EVENT_CMPL_FUNC_DRVR_LOAD_EVENT_ID_FUNC_DRVR_LOAD \
5353 #define HWRM_ASYNC_EVENT_CMPL_FUNC_DRVR_LOAD_EVENT_ID_LAST \
5354 HWRM_ASYNC_EVENT_CMPL_FUNC_DRVR_LOAD_EVENT_ID_FUNC_DRVR_LOAD
5355 /* Event specific data */
5356 uint32_t event_data2;
5359 * This value is written by the NIC such that it will be different
5360 * for each pass through the completion queue. The even passes
5361 * will write 1. The odd passes will write 0.
5363 #define HWRM_ASYNC_EVENT_CMPL_FUNC_DRVR_LOAD_V UINT32_C(0x1)
5365 #define HWRM_ASYNC_EVENT_CMPL_FUNC_DRVR_LOAD_OPAQUE_MASK UINT32_C(0xfe)
5366 #define HWRM_ASYNC_EVENT_CMPL_FUNC_DRVR_LOAD_OPAQUE_SFT 1
5367 /* 8-lsb timestamp from POR (100-msec resolution) */
5368 uint8_t timestamp_lo;
5369 /* 16-lsb timestamp from POR (100-msec resolution) */
5370 uint16_t timestamp_hi;
5371 /* Event specific data */
5372 uint32_t event_data1;
5374 #define HWRM_ASYNC_EVENT_CMPL_FUNC_DRVR_LOAD_EVENT_DATA1_FUNC_ID_MASK \
5376 #define HWRM_ASYNC_EVENT_CMPL_FUNC_DRVR_LOAD_EVENT_DATA1_FUNC_ID_SFT 0
5377 } __attribute__((packed));
5379 /* hwrm_async_event_cmpl_func_flr_proc_cmplt (size:128b/16B) */
5380 struct hwrm_async_event_cmpl_func_flr_proc_cmplt {
5383 * This field indicates the exact type of the completion.
5384 * By convention, the LSB identifies the length of the
5385 * record in 16B units. Even values indicate 16B
5386 * records. Odd values indicate 32B
5389 #define HWRM_ASYNC_EVENT_CMPL_FUNC_FLR_PROC_CMPLT_TYPE_MASK \
5391 #define HWRM_ASYNC_EVENT_CMPL_FUNC_FLR_PROC_CMPLT_TYPE_SFT \
5393 /* HWRM Asynchronous Event Information */
5394 #define HWRM_ASYNC_EVENT_CMPL_FUNC_FLR_PROC_CMPLT_TYPE_HWRM_ASYNC_EVENT \
5396 #define HWRM_ASYNC_EVENT_CMPL_FUNC_FLR_PROC_CMPLT_TYPE_LAST \
5397 HWRM_ASYNC_EVENT_CMPL_FUNC_FLR_PROC_CMPLT_TYPE_HWRM_ASYNC_EVENT
5398 /* Identifiers of events. */
5400 /* Function FLR related processing has completed */
5401 #define HWRM_ASYNC_EVENT_CMPL_FUNC_FLR_PROC_CMPLT_EVENT_ID_FUNC_FLR_PROC_CMPLT \
5403 #define HWRM_ASYNC_EVENT_CMPL_FUNC_FLR_PROC_CMPLT_EVENT_ID_LAST \
5404 HWRM_ASYNC_EVENT_CMPL_FUNC_FLR_PROC_CMPLT_EVENT_ID_FUNC_FLR_PROC_CMPLT
5405 /* Event specific data */
5406 uint32_t event_data2;
5409 * This value is written by the NIC such that it will be different
5410 * for each pass through the completion queue. The even passes
5411 * will write 1. The odd passes will write 0.
5413 #define HWRM_ASYNC_EVENT_CMPL_FUNC_FLR_PROC_CMPLT_V \
5416 #define HWRM_ASYNC_EVENT_CMPL_FUNC_FLR_PROC_CMPLT_OPAQUE_MASK \
5418 #define HWRM_ASYNC_EVENT_CMPL_FUNC_FLR_PROC_CMPLT_OPAQUE_SFT 1
5419 /* 8-lsb timestamp from POR (100-msec resolution) */
5420 uint8_t timestamp_lo;
5421 /* 16-lsb timestamp from POR (100-msec resolution) */
5422 uint16_t timestamp_hi;
5423 /* Event specific data */
5424 uint32_t event_data1;
5426 #define HWRM_ASYNC_EVENT_CMPL_FUNC_FLR_PROC_CMPLT_EVENT_DATA1_FUNC_ID_MASK \
5428 #define HWRM_ASYNC_EVENT_CMPL_FUNC_FLR_PROC_CMPLT_EVENT_DATA1_FUNC_ID_SFT \
5430 } __attribute__((packed));
5432 /* hwrm_async_event_cmpl_pf_drvr_unload (size:128b/16B) */
5433 struct hwrm_async_event_cmpl_pf_drvr_unload {
5436 * This field indicates the exact type of the completion.
5437 * By convention, the LSB identifies the length of the
5438 * record in 16B units. Even values indicate 16B
5439 * records. Odd values indicate 32B
5442 #define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_UNLOAD_TYPE_MASK \
5444 #define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_UNLOAD_TYPE_SFT 0
5445 /* HWRM Asynchronous Event Information */
5446 #define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_UNLOAD_TYPE_HWRM_ASYNC_EVENT \
5448 #define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_UNLOAD_TYPE_LAST \
5449 HWRM_ASYNC_EVENT_CMPL_PF_DRVR_UNLOAD_TYPE_HWRM_ASYNC_EVENT
5450 /* Identifiers of events. */
5452 /* PF driver unloaded */
5453 #define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_UNLOAD_EVENT_ID_PF_DRVR_UNLOAD \
5455 #define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_UNLOAD_EVENT_ID_LAST \
5456 HWRM_ASYNC_EVENT_CMPL_PF_DRVR_UNLOAD_EVENT_ID_PF_DRVR_UNLOAD
5457 /* Event specific data */
5458 uint32_t event_data2;
5461 * This value is written by the NIC such that it will be different
5462 * for each pass through the completion queue. The even passes
5463 * will write 1. The odd passes will write 0.
5465 #define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_UNLOAD_V UINT32_C(0x1)
5467 #define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_UNLOAD_OPAQUE_MASK UINT32_C(0xfe)
5468 #define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_UNLOAD_OPAQUE_SFT 1
5469 /* 8-lsb timestamp from POR (100-msec resolution) */
5470 uint8_t timestamp_lo;
5471 /* 16-lsb timestamp from POR (100-msec resolution) */
5472 uint16_t timestamp_hi;
5473 /* Event specific data */
5474 uint32_t event_data1;
5476 #define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_UNLOAD_EVENT_DATA1_FUNC_ID_MASK \
5478 #define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_UNLOAD_EVENT_DATA1_FUNC_ID_SFT 0
5479 /* Indicates the physical port this pf belongs to */
5480 #define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_UNLOAD_EVENT_DATA1_PORT_MASK \
5482 #define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_UNLOAD_EVENT_DATA1_PORT_SFT 16
5483 } __attribute__((packed));
5485 /* hwrm_async_event_cmpl_pf_drvr_load (size:128b/16B) */
5486 struct hwrm_async_event_cmpl_pf_drvr_load {
5489 * This field indicates the exact type of the completion.
5490 * By convention, the LSB identifies the length of the
5491 * record in 16B units. Even values indicate 16B
5492 * records. Odd values indicate 32B
5495 #define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_LOAD_TYPE_MASK \
5497 #define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_LOAD_TYPE_SFT 0
5498 /* HWRM Asynchronous Event Information */
5499 #define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_LOAD_TYPE_HWRM_ASYNC_EVENT \
5501 #define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_LOAD_TYPE_LAST \
5502 HWRM_ASYNC_EVENT_CMPL_PF_DRVR_LOAD_TYPE_HWRM_ASYNC_EVENT
5503 /* Identifiers of events. */
5505 /* PF driver loaded */
5506 #define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_LOAD_EVENT_ID_PF_DRVR_LOAD \
5508 #define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_LOAD_EVENT_ID_LAST \
5509 HWRM_ASYNC_EVENT_CMPL_PF_DRVR_LOAD_EVENT_ID_PF_DRVR_LOAD
5510 /* Event specific data */
5511 uint32_t event_data2;
5514 * This value is written by the NIC such that it will be different
5515 * for each pass through the completion queue. The even passes
5516 * will write 1. The odd passes will write 0.
5518 #define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_LOAD_V UINT32_C(0x1)
5520 #define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_LOAD_OPAQUE_MASK UINT32_C(0xfe)
5521 #define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_LOAD_OPAQUE_SFT 1
5522 /* 8-lsb timestamp from POR (100-msec resolution) */
5523 uint8_t timestamp_lo;
5524 /* 16-lsb timestamp from POR (100-msec resolution) */
5525 uint16_t timestamp_hi;
5526 /* Event specific data */
5527 uint32_t event_data1;
5529 #define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_LOAD_EVENT_DATA1_FUNC_ID_MASK \
5531 #define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_LOAD_EVENT_DATA1_FUNC_ID_SFT 0
5532 /* Indicates the physical port this pf belongs to */
5533 #define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_LOAD_EVENT_DATA1_PORT_MASK \
5535 #define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_LOAD_EVENT_DATA1_PORT_SFT 16
5536 } __attribute__((packed));
5538 /* hwrm_async_event_cmpl_vf_flr (size:128b/16B) */
5539 struct hwrm_async_event_cmpl_vf_flr {
5542 * This field indicates the exact type of the completion.
5543 * By convention, the LSB identifies the length of the
5544 * record in 16B units. Even values indicate 16B
5545 * records. Odd values indicate 32B
5548 #define HWRM_ASYNC_EVENT_CMPL_VF_FLR_TYPE_MASK \
5550 #define HWRM_ASYNC_EVENT_CMPL_VF_FLR_TYPE_SFT 0
5551 /* HWRM Asynchronous Event Information */
5552 #define HWRM_ASYNC_EVENT_CMPL_VF_FLR_TYPE_HWRM_ASYNC_EVENT \
5554 #define HWRM_ASYNC_EVENT_CMPL_VF_FLR_TYPE_LAST \
5555 HWRM_ASYNC_EVENT_CMPL_VF_FLR_TYPE_HWRM_ASYNC_EVENT
5556 /* Identifiers of events. */
5558 /* VF Function Level Reset (FLR) */
5559 #define HWRM_ASYNC_EVENT_CMPL_VF_FLR_EVENT_ID_VF_FLR UINT32_C(0x30)
5560 #define HWRM_ASYNC_EVENT_CMPL_VF_FLR_EVENT_ID_LAST \
5561 HWRM_ASYNC_EVENT_CMPL_VF_FLR_EVENT_ID_VF_FLR
5562 /* Event specific data */
5563 uint32_t event_data2;
5566 * This value is written by the NIC such that it will be different
5567 * for each pass through the completion queue. The even passes
5568 * will write 1. The odd passes will write 0.
5570 #define HWRM_ASYNC_EVENT_CMPL_VF_FLR_V UINT32_C(0x1)
5572 #define HWRM_ASYNC_EVENT_CMPL_VF_FLR_OPAQUE_MASK UINT32_C(0xfe)
5573 #define HWRM_ASYNC_EVENT_CMPL_VF_FLR_OPAQUE_SFT 1
5574 /* 8-lsb timestamp from POR (100-msec resolution) */
5575 uint8_t timestamp_lo;
5576 /* 16-lsb timestamp from POR (100-msec resolution) */
5577 uint16_t timestamp_hi;
5578 /* Event specific data */
5579 uint32_t event_data1;
5581 #define HWRM_ASYNC_EVENT_CMPL_VF_FLR_EVENT_DATA1_VF_ID_MASK \
5583 #define HWRM_ASYNC_EVENT_CMPL_VF_FLR_EVENT_DATA1_VF_ID_SFT 0
5584 /* Indicates the physical function this event occurred on. */
5585 #define HWRM_ASYNC_EVENT_CMPL_VF_FLR_EVENT_DATA1_PF_ID_MASK \
5587 #define HWRM_ASYNC_EVENT_CMPL_VF_FLR_EVENT_DATA1_PF_ID_SFT 16
5588 } __attribute__((packed));
5590 /* hwrm_async_event_cmpl_vf_mac_addr_change (size:128b/16B) */
5591 struct hwrm_async_event_cmpl_vf_mac_addr_change {
5594 * This field indicates the exact type of the completion.
5595 * By convention, the LSB identifies the length of the
5596 * record in 16B units. Even values indicate 16B
5597 * records. Odd values indicate 32B
5600 #define HWRM_ASYNC_EVENT_CMPL_VF_MAC_ADDR_CHANGE_TYPE_MASK \
5602 #define HWRM_ASYNC_EVENT_CMPL_VF_MAC_ADDR_CHANGE_TYPE_SFT 0
5603 /* HWRM Asynchronous Event Information */
5604 #define HWRM_ASYNC_EVENT_CMPL_VF_MAC_ADDR_CHANGE_TYPE_HWRM_ASYNC_EVENT \
5606 #define HWRM_ASYNC_EVENT_CMPL_VF_MAC_ADDR_CHANGE_TYPE_LAST \
5607 HWRM_ASYNC_EVENT_CMPL_VF_MAC_ADDR_CHANGE_TYPE_HWRM_ASYNC_EVENT
5608 /* Identifiers of events. */
5610 /* VF MAC Address Change */
5611 #define HWRM_ASYNC_EVENT_CMPL_VF_MAC_ADDR_CHANGE_EVENT_ID_VF_MAC_ADDR_CHANGE \
5613 #define HWRM_ASYNC_EVENT_CMPL_VF_MAC_ADDR_CHANGE_EVENT_ID_LAST \
5614 HWRM_ASYNC_EVENT_CMPL_VF_MAC_ADDR_CHANGE_EVENT_ID_VF_MAC_ADDR_CHANGE
5615 /* Event specific data */
5616 uint32_t event_data2;
5619 * This value is written by the NIC such that it will be different
5620 * for each pass through the completion queue. The even passes
5621 * will write 1. The odd passes will write 0.
5623 #define HWRM_ASYNC_EVENT_CMPL_VF_MAC_ADDR_CHANGE_V \
5626 #define HWRM_ASYNC_EVENT_CMPL_VF_MAC_ADDR_CHANGE_OPAQUE_MASK \
5628 #define HWRM_ASYNC_EVENT_CMPL_VF_MAC_ADDR_CHANGE_OPAQUE_SFT 1
5629 /* 8-lsb timestamp from POR (100-msec resolution) */
5630 uint8_t timestamp_lo;
5631 /* 16-lsb timestamp from POR (100-msec resolution) */
5632 uint16_t timestamp_hi;
5633 /* Event specific data */
5634 uint32_t event_data1;
5636 #define HWRM_ASYNC_EVENT_CMPL_VF_MAC_ADDR_CHANGE_EVENT_DATA1_VF_ID_MASK \
5638 #define HWRM_ASYNC_EVENT_CMPL_VF_MAC_ADDR_CHANGE_EVENT_DATA1_VF_ID_SFT \
5640 } __attribute__((packed));
5642 /* hwrm_async_event_cmpl_pf_vf_comm_status_change (size:128b/16B) */
5643 struct hwrm_async_event_cmpl_pf_vf_comm_status_change {
5646 * This field indicates the exact type of the completion.
5647 * By convention, the LSB identifies the length of the
5648 * record in 16B units. Even values indicate 16B
5649 * records. Odd values indicate 32B
5652 #define HWRM_ASYNC_EVENT_CMPL_PF_VF_COMM_STATUS_CHANGE_TYPE_MASK \
5654 #define HWRM_ASYNC_EVENT_CMPL_PF_VF_COMM_STATUS_CHANGE_TYPE_SFT \
5656 /* HWRM Asynchronous Event Information */
5657 #define HWRM_ASYNC_EVENT_CMPL_PF_VF_COMM_STATUS_CHANGE_TYPE_HWRM_ASYNC_EVENT \
5659 #define HWRM_ASYNC_EVENT_CMPL_PF_VF_COMM_STATUS_CHANGE_TYPE_LAST \
5660 HWRM_ASYNC_EVENT_CMPL_PF_VF_COMM_STATUS_CHANGE_TYPE_HWRM_ASYNC_EVENT
5661 /* Identifiers of events. */
5663 /* PF-VF communication channel status change. */
5664 #define HWRM_ASYNC_EVENT_CMPL_PF_VF_COMM_STATUS_CHANGE_EVENT_ID_PF_VF_COMM_STATUS_CHANGE \
5666 #define HWRM_ASYNC_EVENT_CMPL_PF_VF_COMM_STATUS_CHANGE_EVENT_ID_LAST \
5667 HWRM_ASYNC_EVENT_CMPL_PF_VF_COMM_STATUS_CHANGE_EVENT_ID_PF_VF_COMM_STATUS_CHANGE
5668 /* Event specific data */
5669 uint32_t event_data2;
5672 * This value is written by the NIC such that it will be different
5673 * for each pass through the completion queue. The even passes
5674 * will write 1. The odd passes will write 0.
5676 #define HWRM_ASYNC_EVENT_CMPL_PF_VF_COMM_STATUS_CHANGE_V \
5679 #define HWRM_ASYNC_EVENT_CMPL_PF_VF_COMM_STATUS_CHANGE_OPAQUE_MASK \
5681 #define HWRM_ASYNC_EVENT_CMPL_PF_VF_COMM_STATUS_CHANGE_OPAQUE_SFT 1
5682 /* 8-lsb timestamp from POR (100-msec resolution) */
5683 uint8_t timestamp_lo;
5684 /* 16-lsb timestamp from POR (100-msec resolution) */
5685 uint16_t timestamp_hi;
5686 /* Event specific data */
5687 uint32_t event_data1;
5689 * If this bit is set to 1, then it indicates that the PF-VF
5690 * communication was lost and it is established.
5691 * If this bit set to 0, then it indicates that the PF-VF
5692 * communication was established and it is lost.
5694 #define HWRM_ASYNC_EVENT_CMPL_PF_VF_COMM_STATUS_CHANGE_EVENT_DATA1_COMM_ESTABLISHED \
5696 } __attribute__((packed));
5698 /* hwrm_async_event_cmpl_vf_cfg_change (size:128b/16B) */
5699 struct hwrm_async_event_cmpl_vf_cfg_change {
5702 * This field indicates the exact type of the completion.
5703 * By convention, the LSB identifies the length of the
5704 * record in 16B units. Even values indicate 16B
5705 * records. Odd values indicate 32B
5708 #define HWRM_ASYNC_EVENT_CMPL_VF_CFG_CHANGE_TYPE_MASK \
5710 #define HWRM_ASYNC_EVENT_CMPL_VF_CFG_CHANGE_TYPE_SFT 0
5711 /* HWRM Asynchronous Event Information */
5712 #define HWRM_ASYNC_EVENT_CMPL_VF_CFG_CHANGE_TYPE_HWRM_ASYNC_EVENT \
5714 #define HWRM_ASYNC_EVENT_CMPL_VF_CFG_CHANGE_TYPE_LAST \
5715 HWRM_ASYNC_EVENT_CMPL_VF_CFG_CHANGE_TYPE_HWRM_ASYNC_EVENT
5716 /* Identifiers of events. */
5718 /* VF Configuration Change */
5719 #define HWRM_ASYNC_EVENT_CMPL_VF_CFG_CHANGE_EVENT_ID_VF_CFG_CHANGE \
5721 #define HWRM_ASYNC_EVENT_CMPL_VF_CFG_CHANGE_EVENT_ID_LAST \
5722 HWRM_ASYNC_EVENT_CMPL_VF_CFG_CHANGE_EVENT_ID_VF_CFG_CHANGE
5723 /* Event specific data */
5724 uint32_t event_data2;
5727 * This value is written by the NIC such that it will be different
5728 * for each pass through the completion queue. The even passes
5729 * will write 1. The odd passes will write 0.
5731 #define HWRM_ASYNC_EVENT_CMPL_VF_CFG_CHANGE_V UINT32_C(0x1)
5733 #define HWRM_ASYNC_EVENT_CMPL_VF_CFG_CHANGE_OPAQUE_MASK UINT32_C(0xfe)
5734 #define HWRM_ASYNC_EVENT_CMPL_VF_CFG_CHANGE_OPAQUE_SFT 1
5735 /* 8-lsb timestamp from POR (100-msec resolution) */
5736 uint8_t timestamp_lo;
5737 /* 16-lsb timestamp from POR (100-msec resolution) */
5738 uint16_t timestamp_hi;
5740 * Each flag provided in this field indicates a specific VF
5741 * configuration change. At least one of these flags shall be set to 1
5742 * when an asynchronous event completion of this type is provided
5745 uint32_t event_data1;
5747 * If this bit is set to 1, then the value of MTU
5748 * was changed on this VF.
5749 * If set to 0, then this bit should be ignored.
5751 #define HWRM_ASYNC_EVENT_CMPL_VF_CFG_CHANGE_EVENT_DATA1_MTU_CHANGE \
5754 * If this bit is set to 1, then the value of MRU
5755 * was changed on this VF.
5756 * If set to 0, then this bit should be ignored.
5758 #define HWRM_ASYNC_EVENT_CMPL_VF_CFG_CHANGE_EVENT_DATA1_MRU_CHANGE \
5761 * If this bit is set to 1, then the value of default MAC
5762 * address was changed on this VF.
5763 * If set to 0, then this bit should be ignored.
5765 #define HWRM_ASYNC_EVENT_CMPL_VF_CFG_CHANGE_EVENT_DATA1_DFLT_MAC_ADDR_CHANGE \
5768 * If this bit is set to 1, then the value of default VLAN
5769 * was changed on this VF.
5770 * If set to 0, then this bit should be ignored.
5772 #define HWRM_ASYNC_EVENT_CMPL_VF_CFG_CHANGE_EVENT_DATA1_DFLT_VLAN_CHANGE \
5775 * If this bit is set to 1, then the value of trusted VF enable
5776 * was changed on this VF.
5777 * If set to 0, then this bit should be ignored.
5779 #define HWRM_ASYNC_EVENT_CMPL_VF_CFG_CHANGE_EVENT_DATA1_TRUSTED_VF_CFG_CHANGE \
5781 } __attribute__((packed));
5783 /* hwrm_async_event_cmpl_llfc_pfc_change (size:128b/16B) */
5784 struct hwrm_async_event_cmpl_llfc_pfc_change {
5787 * This field indicates the exact type of the completion.
5788 * By convention, the LSB identifies the length of the
5789 * record in 16B units. Even values indicate 16B
5790 * records. Odd values indicate 32B
5793 #define HWRM_ASYNC_EVENT_CMPL_LLFC_PFC_CHANGE_TYPE_MASK \
5795 #define HWRM_ASYNC_EVENT_CMPL_LLFC_PFC_CHANGE_TYPE_SFT 0
5796 /* HWRM Asynchronous Event Information */
5797 #define HWRM_ASYNC_EVENT_CMPL_LLFC_PFC_CHANGE_TYPE_HWRM_ASYNC_EVENT \
5799 #define HWRM_ASYNC_EVENT_CMPL_LLFC_PFC_CHANGE_TYPE_LAST \
5800 HWRM_ASYNC_EVENT_CMPL_LLFC_PFC_CHANGE_TYPE_HWRM_ASYNC_EVENT
5801 /* unused1 is 10 b */
5802 #define HWRM_ASYNC_EVENT_CMPL_LLFC_PFC_CHANGE_UNUSED1_MASK \
5804 #define HWRM_ASYNC_EVENT_CMPL_LLFC_PFC_CHANGE_UNUSED1_SFT 6
5805 /* Identifiers of events. */
5807 /* LLFC/PFC Configuration Change */
5808 #define HWRM_ASYNC_EVENT_CMPL_LLFC_PFC_CHANGE_EVENT_ID_LLFC_PFC_CHANGE \
5810 #define HWRM_ASYNC_EVENT_CMPL_LLFC_PFC_CHANGE_EVENT_ID_LAST \
5811 HWRM_ASYNC_EVENT_CMPL_LLFC_PFC_CHANGE_EVENT_ID_LLFC_PFC_CHANGE
5812 /* Event specific data */
5813 uint32_t event_data2;
5816 * This value is written by the NIC such that it will be different
5817 * for each pass through the completion queue. The even passes
5818 * will write 1. The odd passes will write 0.
5820 #define HWRM_ASYNC_EVENT_CMPL_LLFC_PFC_CHANGE_V UINT32_C(0x1)
5822 #define HWRM_ASYNC_EVENT_CMPL_LLFC_PFC_CHANGE_OPAQUE_MASK \
5824 #define HWRM_ASYNC_EVENT_CMPL_LLFC_PFC_CHANGE_OPAQUE_SFT 1
5825 /* 8-lsb timestamp from POR (100-msec resolution) */
5826 uint8_t timestamp_lo;
5827 /* 16-lsb timestamp from POR (100-msec resolution) */
5828 uint16_t timestamp_hi;
5829 /* Event specific data */
5830 uint32_t event_data1;
5831 /* Indicates llfc pfc status change */
5832 #define HWRM_ASYNC_EVENT_CMPL_LLFC_PFC_CHANGE_EVENT_DATA1_LLFC_PFC_MASK \
5834 #define HWRM_ASYNC_EVENT_CMPL_LLFC_PFC_CHANGE_EVENT_DATA1_LLFC_PFC_SFT \
5837 * If this field set to 1, then it indicates that llfc is
5840 #define HWRM_ASYNC_EVENT_CMPL_LLFC_PFC_CHANGE_EVENT_DATA1_LLFC_PFC_LLFC \
5843 * If this field is set to 2, then it indicates that pfc
5846 #define HWRM_ASYNC_EVENT_CMPL_LLFC_PFC_CHANGE_EVENT_DATA1_LLFC_PFC_PFC \
5848 #define HWRM_ASYNC_EVENT_CMPL_LLFC_PFC_CHANGE_EVENT_DATA1_LLFC_PFC_LAST \
5849 HWRM_ASYNC_EVENT_CMPL_LLFC_PFC_CHANGE_EVENT_DATA1_LLFC_PFC_PFC
5850 /* Indicates the physical port this llfc pfc change occur */
5851 #define HWRM_ASYNC_EVENT_CMPL_LLFC_PFC_CHANGE_EVENT_DATA1_PORT_MASK \
5853 #define HWRM_ASYNC_EVENT_CMPL_LLFC_PFC_CHANGE_EVENT_DATA1_PORT_SFT \
5856 #define HWRM_ASYNC_EVENT_CMPL_LLFC_PFC_CHANGE_EVENT_DATA1_PORT_ID_MASK \
5858 #define HWRM_ASYNC_EVENT_CMPL_LLFC_PFC_CHANGE_EVENT_DATA1_PORT_ID_SFT \
5860 } __attribute__((packed));
5862 /* hwrm_async_event_cmpl_default_vnic_change (size:128b/16B) */
5863 struct hwrm_async_event_cmpl_default_vnic_change {
5866 * This field indicates the exact type of the completion.
5867 * By convention, the LSB identifies the length of the
5868 * record in 16B units. Even values indicate 16B
5869 * records. Odd values indicate 32B
5872 #define HWRM_ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_TYPE_MASK \
5874 #define HWRM_ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_TYPE_SFT \
5876 /* HWRM Asynchronous Event Information */
5877 #define HWRM_ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_TYPE_HWRM_ASYNC_EVENT \
5879 #define HWRM_ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_TYPE_LAST \
5880 HWRM_ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_TYPE_HWRM_ASYNC_EVENT
5881 /* unused1 is 10 b */
5882 #define HWRM_ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_UNUSED1_MASK \
5884 #define HWRM_ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_UNUSED1_SFT \
5886 /* Identifiers of events. */
5888 /* Notification of a default vnic allocaiton or free */
5889 #define HWRM_ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_EVENT_ID_ALLOC_FREE_NOTIFICATION \
5891 #define HWRM_ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_EVENT_ID_LAST \
5892 HWRM_ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_EVENT_ID_ALLOC_FREE_NOTIFICATION
5893 /* Event specific data */
5894 uint32_t event_data2;
5897 * This value is written by the NIC such that it will be different
5898 * for each pass through the completion queue. The even passes
5899 * will write 1. The odd passes will write 0.
5901 #define HWRM_ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_V \
5904 #define HWRM_ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_OPAQUE_MASK \
5906 #define HWRM_ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_OPAQUE_SFT 1
5907 /* 8-lsb timestamp from POR (100-msec resolution) */
5908 uint8_t timestamp_lo;
5909 /* 16-lsb timestamp from POR (100-msec resolution) */
5910 uint16_t timestamp_hi;
5911 /* Event specific data */
5912 uint32_t event_data1;
5913 /* Indicates default vnic configuration change */
5914 #define HWRM_ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_EVENT_DATA1_DEF_VNIC_STATE_MASK \
5916 #define HWRM_ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_EVENT_DATA1_DEF_VNIC_STATE_SFT \
5919 * If this field is set to 1, then it indicates that
5920 * a default VNIC has been allocate.
5922 #define HWRM_ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_EVENT_DATA1_DEF_VNIC_STATE_DEF_VNIC_ALLOC \
5925 * If this field is set to 2, then it indicates that
5926 * a default VNIC has been freed.
5928 #define HWRM_ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_EVENT_DATA1_DEF_VNIC_STATE_DEF_VNIC_FREE \
5930 #define HWRM_ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_EVENT_DATA1_DEF_VNIC_STATE_LAST \
5931 HWRM_ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_EVENT_DATA1_DEF_VNIC_STATE_DEF_VNIC_FREE
5932 /* Indicates the physical function this event occurred on. */
5933 #define HWRM_ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_EVENT_DATA1_PF_ID_MASK \
5935 #define HWRM_ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_EVENT_DATA1_PF_ID_SFT \
5937 /* Indicates the virtual function this event occurred on */
5938 #define HWRM_ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_EVENT_DATA1_VF_ID_MASK \
5940 #define HWRM_ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_EVENT_DATA1_VF_ID_SFT \
5942 } __attribute__((packed));
5944 /* hwrm_async_event_cmpl_hw_flow_aged (size:128b/16B) */
5945 struct hwrm_async_event_cmpl_hw_flow_aged {
5948 * This field indicates the exact type of the completion.
5949 * By convention, the LSB identifies the length of the
5950 * record in 16B units. Even values indicate 16B
5951 * records. Odd values indicate 32B
5954 #define HWRM_ASYNC_EVENT_CMPL_HW_FLOW_AGED_TYPE_MASK \
5956 #define HWRM_ASYNC_EVENT_CMPL_HW_FLOW_AGED_TYPE_SFT 0
5957 /* HWRM Asynchronous Event Information */
5958 #define HWRM_ASYNC_EVENT_CMPL_HW_FLOW_AGED_TYPE_HWRM_ASYNC_EVENT \
5960 #define HWRM_ASYNC_EVENT_CMPL_HW_FLOW_AGED_TYPE_LAST \
5961 HWRM_ASYNC_EVENT_CMPL_HW_FLOW_AGED_TYPE_HWRM_ASYNC_EVENT
5962 /* Identifiers of events. */
5964 /* Notification of a hw flow aged */
5965 #define HWRM_ASYNC_EVENT_CMPL_HW_FLOW_AGED_EVENT_ID_HW_FLOW_AGED \
5967 #define HWRM_ASYNC_EVENT_CMPL_HW_FLOW_AGED_EVENT_ID_LAST \
5968 HWRM_ASYNC_EVENT_CMPL_HW_FLOW_AGED_EVENT_ID_HW_FLOW_AGED
5969 /* Event specific data */
5970 uint32_t event_data2;
5973 * This value is written by the NIC such that it will be different
5974 * for each pass through the completion queue. The even passes
5975 * will write 1. The odd passes will write 0.
5977 #define HWRM_ASYNC_EVENT_CMPL_HW_FLOW_AGED_V UINT32_C(0x1)
5979 #define HWRM_ASYNC_EVENT_CMPL_HW_FLOW_AGED_OPAQUE_MASK UINT32_C(0xfe)
5980 #define HWRM_ASYNC_EVENT_CMPL_HW_FLOW_AGED_OPAQUE_SFT 1
5981 /* 8-lsb timestamp from POR (100-msec resolution) */
5982 uint8_t timestamp_lo;
5983 /* 16-lsb timestamp from POR (100-msec resolution) */
5984 uint16_t timestamp_hi;
5985 /* Event specific data */
5986 uint32_t event_data1;
5987 /* Indicates flow ID this event occurred on. */
5988 #define HWRM_ASYNC_EVENT_CMPL_HW_FLOW_AGED_EVENT_DATA1_FLOW_ID_MASK \
5989 UINT32_C(0x7fffffff)
5990 #define HWRM_ASYNC_EVENT_CMPL_HW_FLOW_AGED_EVENT_DATA1_FLOW_ID_SFT \
5992 /* Indicates flow direction this event occurred on. */
5993 #define HWRM_ASYNC_EVENT_CMPL_HW_FLOW_AGED_EVENT_DATA1_FLOW_DIRECTION \
5994 UINT32_C(0x80000000)
5996 * If this bit set to 0, then it indicates that the aged
5997 * event was rx flow.
5999 #define HWRM_ASYNC_EVENT_CMPL_HW_FLOW_AGED_EVENT_DATA1_FLOW_DIRECTION_RX \
6000 (UINT32_C(0x0) << 31)
6002 * If this bit is set to 1, then it indicates that the aged
6003 * event was tx flow.
6005 #define HWRM_ASYNC_EVENT_CMPL_HW_FLOW_AGED_EVENT_DATA1_FLOW_DIRECTION_TX \
6006 (UINT32_C(0x1) << 31)
6007 #define HWRM_ASYNC_EVENT_CMPL_HW_FLOW_AGED_EVENT_DATA1_FLOW_DIRECTION_LAST \
6008 HWRM_ASYNC_EVENT_CMPL_HW_FLOW_AGED_EVENT_DATA1_FLOW_DIRECTION_TX
6009 } __attribute__((packed));
6011 /* hwrm_async_event_cmpl_eem_cache_flush_req (size:128b/16B) */
6012 struct hwrm_async_event_cmpl_eem_cache_flush_req {
6015 * This field indicates the exact type of the completion.
6016 * By convention, the LSB identifies the length of the
6017 * record in 16B units. Even values indicate 16B
6018 * records. Odd values indicate 32B
6021 #define HWRM_ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_REQ_TYPE_MASK \
6023 #define HWRM_ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_REQ_TYPE_SFT \
6025 /* HWRM Asynchronous Event Information */
6026 #define HWRM_ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_REQ_TYPE_HWRM_ASYNC_EVENT \
6028 #define HWRM_ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_REQ_TYPE_LAST \
6029 HWRM_ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_REQ_TYPE_HWRM_ASYNC_EVENT
6030 /* Identifiers of events. */
6032 /* Notification of a eem_cache_flush request */
6033 #define HWRM_ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_REQ_EVENT_ID_EEM_CACHE_FLUSH_REQ \
6035 #define HWRM_ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_REQ_EVENT_ID_LAST \
6036 HWRM_ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_REQ_EVENT_ID_EEM_CACHE_FLUSH_REQ
6037 /* Event specific data */
6038 uint32_t event_data2;
6041 * This value is written by the NIC such that it will be different
6042 * for each pass through the completion queue. The even passes
6043 * will write 1. The odd passes will write 0.
6045 #define HWRM_ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_REQ_V \
6048 #define HWRM_ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_REQ_OPAQUE_MASK \
6050 #define HWRM_ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_REQ_OPAQUE_SFT 1
6051 /* 8-lsb timestamp from POR (100-msec resolution) */
6052 uint8_t timestamp_lo;
6053 /* 16-lsb timestamp from POR (100-msec resolution) */
6054 uint16_t timestamp_hi;
6055 /* Event specific data */
6056 uint32_t event_data1;
6057 } __attribute__((packed));
6059 /* hwrm_async_event_cmpl_eem_cache_flush_done (size:128b/16B) */
6060 struct hwrm_async_event_cmpl_eem_cache_flush_done {
6063 * This field indicates the exact type of the completion.
6064 * By convention, the LSB identifies the length of the
6065 * record in 16B units. Even values indicate 16B
6066 * records. Odd values indicate 32B
6069 #define HWRM_ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_DONE_TYPE_MASK \
6071 #define HWRM_ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_DONE_TYPE_SFT \
6073 /* HWRM Asynchronous Event Information */
6074 #define HWRM_ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_DONE_TYPE_HWRM_ASYNC_EVENT \
6076 #define HWRM_ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_DONE_TYPE_LAST \
6077 HWRM_ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_DONE_TYPE_HWRM_ASYNC_EVENT
6078 /* Identifiers of events. */
6081 * Notification of a host eem_cache_flush has completed. This event
6082 * is generated by the host driver.
6084 #define HWRM_ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_DONE_EVENT_ID_EEM_CACHE_FLUSH_DONE \
6086 #define HWRM_ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_DONE_EVENT_ID_LAST \
6087 HWRM_ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_DONE_EVENT_ID_EEM_CACHE_FLUSH_DONE
6088 /* Event specific data */
6089 uint32_t event_data2;
6092 * This value is written by the NIC such that it will be different
6093 * for each pass through the completion queue. The even passes
6094 * will write 1. The odd passes will write 0.
6096 #define HWRM_ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_DONE_V \
6099 #define HWRM_ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_DONE_OPAQUE_MASK \
6101 #define HWRM_ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_DONE_OPAQUE_SFT 1
6102 /* 8-lsb timestamp from POR (100-msec resolution) */
6103 uint8_t timestamp_lo;
6104 /* 16-lsb timestamp from POR (100-msec resolution) */
6105 uint16_t timestamp_hi;
6106 /* Event specific data */
6107 uint32_t event_data1;
6108 /* Indicates function ID that this event occurred on. */
6109 #define HWRM_ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_DONE_EVENT_DATA1_FID_MASK \
6111 #define HWRM_ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_DONE_EVENT_DATA1_FID_SFT \
6113 } __attribute__((packed));
6115 /* hwrm_async_event_cmpl_tcp_flag_action_change (size:128b/16B) */
6116 struct hwrm_async_event_cmpl_tcp_flag_action_change {
6119 * This field indicates the exact type of the completion.
6120 * By convention, the LSB identifies the length of the
6121 * record in 16B units. Even values indicate 16B
6122 * records. Odd values indicate 32B
6125 #define HWRM_ASYNC_EVENT_CMPL_TCP_FLAG_ACTION_CHANGE_TYPE_MASK \
6127 #define HWRM_ASYNC_EVENT_CMPL_TCP_FLAG_ACTION_CHANGE_TYPE_SFT \
6129 /* HWRM Asynchronous Event Information */
6130 #define HWRM_ASYNC_EVENT_CMPL_TCP_FLAG_ACTION_CHANGE_TYPE_HWRM_ASYNC_EVENT \
6132 #define HWRM_ASYNC_EVENT_CMPL_TCP_FLAG_ACTION_CHANGE_TYPE_LAST \
6133 HWRM_ASYNC_EVENT_CMPL_TCP_FLAG_ACTION_CHANGE_TYPE_HWRM_ASYNC_EVENT
6134 /* Identifiers of events. */
6136 /* Notification of tcp flag action change */
6137 #define HWRM_ASYNC_EVENT_CMPL_TCP_FLAG_ACTION_CHANGE_EVENT_ID_TCP_FLAG_ACTION_CHANGE \
6139 #define HWRM_ASYNC_EVENT_CMPL_TCP_FLAG_ACTION_CHANGE_EVENT_ID_LAST \
6140 HWRM_ASYNC_EVENT_CMPL_TCP_FLAG_ACTION_CHANGE_EVENT_ID_TCP_FLAG_ACTION_CHANGE
6141 /* Event specific data */
6142 uint32_t event_data2;
6145 * This value is written by the NIC such that it will be different
6146 * for each pass through the completion queue. The even passes
6147 * will write 1. The odd passes will write 0.
6149 #define HWRM_ASYNC_EVENT_CMPL_TCP_FLAG_ACTION_CHANGE_V \
6152 #define HWRM_ASYNC_EVENT_CMPL_TCP_FLAG_ACTION_CHANGE_OPAQUE_MASK \
6154 #define HWRM_ASYNC_EVENT_CMPL_TCP_FLAG_ACTION_CHANGE_OPAQUE_SFT 1
6155 /* 8-lsb timestamp from POR (100-msec resolution) */
6156 uint8_t timestamp_lo;
6157 /* 16-lsb timestamp from POR (100-msec resolution) */
6158 uint16_t timestamp_hi;
6159 /* Event specific data */
6160 uint32_t event_data1;
6161 } __attribute__((packed));
6163 /* hwrm_async_event_cmpl_eem_flow_active (size:128b/16B) */
6164 struct hwrm_async_event_cmpl_eem_flow_active {
6167 * This field indicates the exact type of the completion.
6168 * By convention, the LSB identifies the length of the
6169 * record in 16B units. Even values indicate 16B
6170 * records. Odd values indicate 32B
6173 #define HWRM_ASYNC_EVENT_CMPL_EEM_FLOW_ACTIVE_TYPE_MASK \
6175 #define HWRM_ASYNC_EVENT_CMPL_EEM_FLOW_ACTIVE_TYPE_SFT 0
6176 /* HWRM Asynchronous Event Information */
6177 #define HWRM_ASYNC_EVENT_CMPL_EEM_FLOW_ACTIVE_TYPE_HWRM_ASYNC_EVENT \
6179 #define HWRM_ASYNC_EVENT_CMPL_EEM_FLOW_ACTIVE_TYPE_LAST \
6180 HWRM_ASYNC_EVENT_CMPL_EEM_FLOW_ACTIVE_TYPE_HWRM_ASYNC_EVENT
6181 /* Identifiers of events. */
6183 /* Notification of an active eem flow */
6184 #define HWRM_ASYNC_EVENT_CMPL_EEM_FLOW_ACTIVE_EVENT_ID_EEM_FLOW_ACTIVE \
6186 #define HWRM_ASYNC_EVENT_CMPL_EEM_FLOW_ACTIVE_EVENT_ID_LAST \
6187 HWRM_ASYNC_EVENT_CMPL_EEM_FLOW_ACTIVE_EVENT_ID_EEM_FLOW_ACTIVE
6188 /* Event specific data */
6189 uint32_t event_data2;
6190 /* Indicates the 2nd global id this event occurred on. */
6191 #define HWRM_ASYNC_EVENT_CMPL_EEM_FLOW_ACTIVE_EVENT_DATA2_GLOBAL_ID_2_MASK \
6192 UINT32_C(0x3fffffff)
6193 #define HWRM_ASYNC_EVENT_CMPL_EEM_FLOW_ACTIVE_EVENT_DATA2_GLOBAL_ID_2_SFT \
6196 * Indicates flow direction of the flow identified by
6199 #define HWRM_ASYNC_EVENT_CMPL_EEM_FLOW_ACTIVE_EVENT_DATA2_FLOW_DIRECTION \
6200 UINT32_C(0x40000000)
6201 /* If this bit is set to 0, then it indicates that this rx flow. */
6202 #define HWRM_ASYNC_EVENT_CMPL_EEM_FLOW_ACTIVE_EVENT_DATA2_FLOW_DIRECTION_RX \
6203 (UINT32_C(0x0) << 30)
6204 /* If this bit is set to 1, then it indicates that this tx flow. */
6205 #define HWRM_ASYNC_EVENT_CMPL_EEM_FLOW_ACTIVE_EVENT_DATA2_FLOW_DIRECTION_TX \
6206 (UINT32_C(0x1) << 30)
6207 #define HWRM_ASYNC_EVENT_CMPL_EEM_FLOW_ACTIVE_EVENT_DATA2_FLOW_DIRECTION_LAST \
6208 HWRM_ASYNC_EVENT_CMPL_EEM_FLOW_ACTIVE_EVENT_DATA2_FLOW_DIRECTION_TX
6211 * This value is written by the NIC such that it will be different
6212 * for each pass through the completion queue. The even passes
6213 * will write 1. The odd passes will write 0.
6215 #define HWRM_ASYNC_EVENT_CMPL_EEM_FLOW_ACTIVE_V UINT32_C(0x1)
6217 #define HWRM_ASYNC_EVENT_CMPL_EEM_FLOW_ACTIVE_OPAQUE_MASK \
6219 #define HWRM_ASYNC_EVENT_CMPL_EEM_FLOW_ACTIVE_OPAQUE_SFT 1
6220 /* 8-lsb timestamp from POR (100-msec resolution) */
6221 uint8_t timestamp_lo;
6222 /* 16-lsb timestamp from POR (100-msec resolution) */
6223 uint16_t timestamp_hi;
6224 /* Event specific data */
6225 uint32_t event_data1;
6226 /* Indicates the 1st global id this event occurred on. */
6227 #define HWRM_ASYNC_EVENT_CMPL_EEM_FLOW_ACTIVE_EVENT_DATA1_GLOBAL_ID_1_MASK \
6228 UINT32_C(0x3fffffff)
6229 #define HWRM_ASYNC_EVENT_CMPL_EEM_FLOW_ACTIVE_EVENT_DATA1_GLOBAL_ID_1_SFT \
6232 * Indicates flow direction of the flow identified by the
6235 #define HWRM_ASYNC_EVENT_CMPL_EEM_FLOW_ACTIVE_EVENT_DATA1_FLOW_DIRECTION \
6236 UINT32_C(0x40000000)
6237 /* If this bit is set to 0, then it indicates that this is rx flow. */
6238 #define HWRM_ASYNC_EVENT_CMPL_EEM_FLOW_ACTIVE_EVENT_DATA1_FLOW_DIRECTION_RX \
6239 (UINT32_C(0x0) << 30)
6240 /* If this bit is set to 1, then it indicates that this is tx flow. */
6241 #define HWRM_ASYNC_EVENT_CMPL_EEM_FLOW_ACTIVE_EVENT_DATA1_FLOW_DIRECTION_TX \
6242 (UINT32_C(0x1) << 30)
6243 #define HWRM_ASYNC_EVENT_CMPL_EEM_FLOW_ACTIVE_EVENT_DATA1_FLOW_DIRECTION_LAST \
6244 HWRM_ASYNC_EVENT_CMPL_EEM_FLOW_ACTIVE_EVENT_DATA1_FLOW_DIRECTION_TX
6246 * Indicates EEM flow aging mode this event occurred on. If
6247 * this bit is set to 0, the event_data1 is the EEM global
6248 * ID. If this bit is set to 1, the event_data1 is the number
6249 * of global ID in the context memory.
6251 #define HWRM_ASYNC_EVENT_CMPL_EEM_FLOW_ACTIVE_EVENT_DATA1_MODE \
6252 UINT32_C(0x80000000)
6253 /* EEM flow aging mode 0. */
6254 #define HWRM_ASYNC_EVENT_CMPL_EEM_FLOW_ACTIVE_EVENT_DATA1_MODE_0 \
6255 (UINT32_C(0x0) << 31)
6256 /* EEM flow aging mode 1. */
6257 #define HWRM_ASYNC_EVENT_CMPL_EEM_FLOW_ACTIVE_EVENT_DATA1_MODE_1 \
6258 (UINT32_C(0x1) << 31)
6259 #define HWRM_ASYNC_EVENT_CMPL_EEM_FLOW_ACTIVE_EVENT_DATA1_MODE_LAST \
6260 HWRM_ASYNC_EVENT_CMPL_EEM_FLOW_ACTIVE_EVENT_DATA1_MODE_1
6261 } __attribute__((packed));
6263 /* hwrm_async_event_cmpl_eem_cfg_change (size:128b/16B) */
6264 struct hwrm_async_event_cmpl_eem_cfg_change {
6267 * This field indicates the exact type of the completion.
6268 * By convention, the LSB identifies the length of the
6269 * record in 16B units. Even values indicate 16B
6270 * records. Odd values indicate 32B
6273 #define HWRM_ASYNC_EVENT_CMPL_EEM_CFG_CHANGE_TYPE_MASK \
6275 #define HWRM_ASYNC_EVENT_CMPL_EEM_CFG_CHANGE_TYPE_SFT 0
6276 /* HWRM Asynchronous Event Information */
6277 #define HWRM_ASYNC_EVENT_CMPL_EEM_CFG_CHANGE_TYPE_HWRM_ASYNC_EVENT \
6279 #define HWRM_ASYNC_EVENT_CMPL_EEM_CFG_CHANGE_TYPE_LAST \
6280 HWRM_ASYNC_EVENT_CMPL_EEM_CFG_CHANGE_TYPE_HWRM_ASYNC_EVENT
6281 /* Identifiers of events. */
6283 /* Notification of EEM configuration change */
6284 #define HWRM_ASYNC_EVENT_CMPL_EEM_CFG_CHANGE_EVENT_ID_EEM_CFG_CHANGE \
6286 #define HWRM_ASYNC_EVENT_CMPL_EEM_CFG_CHANGE_EVENT_ID_LAST \
6287 HWRM_ASYNC_EVENT_CMPL_EEM_CFG_CHANGE_EVENT_ID_EEM_CFG_CHANGE
6288 /* Event specific data */
6289 uint32_t event_data2;
6292 * This value is written by the NIC such that it will be different
6293 * for each pass through the completion queue. The even passes
6294 * will write 1. The odd passes will write 0.
6296 #define HWRM_ASYNC_EVENT_CMPL_EEM_CFG_CHANGE_V UINT32_C(0x1)
6298 #define HWRM_ASYNC_EVENT_CMPL_EEM_CFG_CHANGE_OPAQUE_MASK UINT32_C(0xfe)
6299 #define HWRM_ASYNC_EVENT_CMPL_EEM_CFG_CHANGE_OPAQUE_SFT 1
6300 /* 8-lsb timestamp from POR (100-msec resolution) */
6301 uint8_t timestamp_lo;
6302 /* 16-lsb timestamp from POR (100-msec resolution) */
6303 uint16_t timestamp_hi;
6304 /* Event specific data */
6305 uint32_t event_data1;
6307 * Value of 1 to indicate EEM TX configuration is enabled. Value of
6308 * 0 to indicate the EEM TX configuration is disabled.
6310 #define HWRM_ASYNC_EVENT_CMPL_EEM_CFG_CHANGE_EVENT_DATA1_EEM_TX_ENABLE \
6313 * Value of 1 to indicate EEM RX configuration is enabled. Value of 0
6314 * to indicate the EEM RX configuration is disabled.
6316 #define HWRM_ASYNC_EVENT_CMPL_EEM_CFG_CHANGE_EVENT_DATA1_EEM_RX_ENABLE \
6318 } __attribute__((packed));
6320 /* hwrm_async_event_cmpl_fw_trace_msg (size:128b/16B) */
6321 struct hwrm_async_event_cmpl_fw_trace_msg {
6324 * This field indicates the exact type of the completion.
6325 * By convention, the LSB identifies the length of the
6326 * record in 16B units. Even values indicate 16B
6327 * records. Odd values indicate 32B
6330 #define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_TYPE_MASK \
6332 #define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_TYPE_SFT 0
6333 /* HWRM Asynchronous Event Information */
6334 #define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_TYPE_HWRM_ASYNC_EVENT \
6336 #define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_TYPE_LAST \
6337 HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_TYPE_HWRM_ASYNC_EVENT
6338 /* Identifiers of events. */
6340 /* Firmware trace log message */
6341 #define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_EVENT_ID_FW_TRACE_MSG \
6343 #define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_EVENT_ID_LAST \
6344 HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_EVENT_ID_FW_TRACE_MSG
6345 /* Trace byte 0 to 3 */
6346 uint32_t event_data2;
6348 #define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_EVENT_DATA2_BYTE0_MASK \
6350 #define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_EVENT_DATA2_BYTE0_SFT 0
6352 #define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_EVENT_DATA2_BYTE1_MASK \
6354 #define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_EVENT_DATA2_BYTE1_SFT 8
6356 #define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_EVENT_DATA2_BYTE2_MASK \
6358 #define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_EVENT_DATA2_BYTE2_SFT 16
6360 #define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_EVENT_DATA2_BYTE3_MASK \
6361 UINT32_C(0xff000000)
6362 #define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_EVENT_DATA2_BYTE3_SFT 24
6365 * This value is written by the NIC such that it will be different
6366 * for each pass through the completion queue. The even passes
6367 * will write 1. The odd passes will write 0.
6369 #define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_V UINT32_C(0x1)
6371 #define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_OPAQUE_MASK UINT32_C(0xfe)
6372 #define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_OPAQUE_SFT 1
6374 uint8_t timestamp_lo;
6375 /* Indicates if the string is partial or complete. */
6376 #define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_TIMESTAMP_LO_STRING \
6378 /* Complete string */
6379 #define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_TIMESTAMP_LO_STRING_COMPLETE \
6381 /* Partial string */
6382 #define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_TIMESTAMP_LO_STRING_PARTIAL \
6384 #define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_TIMESTAMP_LO_STRING_LAST \
6385 HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_TIMESTAMP_LO_STRING_PARTIAL
6386 /* Indicates the firmware that sent the trace message. */
6387 #define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_TIMESTAMP_LO_FIRMWARE \
6389 /* Primary firmware */
6390 #define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_TIMESTAMP_LO_FIRMWARE_PRIMARY \
6391 (UINT32_C(0x0) << 1)
6392 /* Secondary firmware */
6393 #define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_TIMESTAMP_LO_FIRMWARE_SECONDARY \
6394 (UINT32_C(0x1) << 1)
6395 #define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_TIMESTAMP_LO_FIRMWARE_LAST \
6396 HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_TIMESTAMP_LO_FIRMWARE_SECONDARY
6397 /* Trace byte 4 to 5 */
6398 uint16_t timestamp_hi;
6400 #define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_TIMESTAMP_HI_BYTE4_MASK \
6402 #define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_TIMESTAMP_HI_BYTE4_SFT 0
6404 #define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_TIMESTAMP_HI_BYTE5_MASK \
6406 #define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_TIMESTAMP_HI_BYTE5_SFT 8
6407 /* Trace byte 6 to 9 */
6408 uint32_t event_data1;
6410 #define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_EVENT_DATA1_BYTE6_MASK \
6412 #define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_EVENT_DATA1_BYTE6_SFT 0
6414 #define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_EVENT_DATA1_BYTE7_MASK \
6416 #define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_EVENT_DATA1_BYTE7_SFT 8
6418 #define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_EVENT_DATA1_BYTE8_MASK \
6420 #define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_EVENT_DATA1_BYTE8_SFT 16
6422 #define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_EVENT_DATA1_BYTE9_MASK \
6423 UINT32_C(0xff000000)
6424 #define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_EVENT_DATA1_BYTE9_SFT 24
6425 } __attribute__((packed));
6427 /* hwrm_async_event_cmpl_hwrm_error (size:128b/16B) */
6428 struct hwrm_async_event_cmpl_hwrm_error {
6431 * This field indicates the exact type of the completion.
6432 * By convention, the LSB identifies the length of the
6433 * record in 16B units. Even values indicate 16B
6434 * records. Odd values indicate 32B
6437 #define HWRM_ASYNC_EVENT_CMPL_HWRM_ERROR_TYPE_MASK \
6439 #define HWRM_ASYNC_EVENT_CMPL_HWRM_ERROR_TYPE_SFT 0
6440 /* HWRM Asynchronous Event Information */
6441 #define HWRM_ASYNC_EVENT_CMPL_HWRM_ERROR_TYPE_HWRM_ASYNC_EVENT \
6443 #define HWRM_ASYNC_EVENT_CMPL_HWRM_ERROR_TYPE_LAST \
6444 HWRM_ASYNC_EVENT_CMPL_HWRM_ERROR_TYPE_HWRM_ASYNC_EVENT
6445 /* Identifiers of events. */
6448 #define HWRM_ASYNC_EVENT_CMPL_HWRM_ERROR_EVENT_ID_HWRM_ERROR \
6450 #define HWRM_ASYNC_EVENT_CMPL_HWRM_ERROR_EVENT_ID_LAST \
6451 HWRM_ASYNC_EVENT_CMPL_HWRM_ERROR_EVENT_ID_HWRM_ERROR
6452 /* Event specific data */
6453 uint32_t event_data2;
6454 /* Severity of HWRM Error */
6455 #define HWRM_ASYNC_EVENT_CMPL_HWRM_ERROR_EVENT_DATA2_SEVERITY_MASK \
6457 #define HWRM_ASYNC_EVENT_CMPL_HWRM_ERROR_EVENT_DATA2_SEVERITY_SFT 0
6459 #define HWRM_ASYNC_EVENT_CMPL_HWRM_ERROR_EVENT_DATA2_SEVERITY_WARNING \
6461 /* Non-fatal Error */
6462 #define HWRM_ASYNC_EVENT_CMPL_HWRM_ERROR_EVENT_DATA2_SEVERITY_NONFATAL \
6465 #define HWRM_ASYNC_EVENT_CMPL_HWRM_ERROR_EVENT_DATA2_SEVERITY_FATAL \
6467 #define HWRM_ASYNC_EVENT_CMPL_HWRM_ERROR_EVENT_DATA2_SEVERITY_LAST \
6468 HWRM_ASYNC_EVENT_CMPL_HWRM_ERROR_EVENT_DATA2_SEVERITY_FATAL
6471 * This value is written by the NIC such that it will be different
6472 * for each pass through the completion queue. The even passes
6473 * will write 1. The odd passes will write 0.
6475 #define HWRM_ASYNC_EVENT_CMPL_HWRM_ERROR_V UINT32_C(0x1)
6477 #define HWRM_ASYNC_EVENT_CMPL_HWRM_ERROR_OPAQUE_MASK UINT32_C(0xfe)
6478 #define HWRM_ASYNC_EVENT_CMPL_HWRM_ERROR_OPAQUE_SFT 1
6479 /* 8-lsb timestamp from POR (100-msec resolution) */
6480 uint8_t timestamp_lo;
6481 /* 16-lsb timestamp from POR (100-msec resolution) */
6482 uint16_t timestamp_hi;
6483 /* Event specific data */
6484 uint32_t event_data1;
6485 /* Time stamp for error event */
6486 #define HWRM_ASYNC_EVENT_CMPL_HWRM_ERROR_EVENT_DATA1_TIMESTAMP \
6488 } __attribute__((packed));
6490 /*******************
6492 *******************/
6495 /* hwrm_func_reset_input (size:192b/24B) */
6496 struct hwrm_func_reset_input {
6497 /* The HWRM command request type. */
6500 * The completion ring to send the completion event on. This should
6501 * be the NQ ID returned from the `nq_alloc` HWRM command.
6505 * The sequence ID is used by the driver for tracking multiple
6506 * commands. This ID is treated as opaque data by the firmware and
6507 * the value is returned in the `hwrm_resp_hdr` upon completion.
6511 * The target ID of the command:
6512 * * 0x0-0xFFF8 - The function ID
6513 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
6514 * * 0xFFFD - Reserved for user-space HWRM interface
6519 * A physical address pointer pointing to a host buffer that the
6520 * command's response data will be written. This can be either a host
6521 * physical address (HPA) or a guest physical address (GPA) and must
6522 * point to a physically contiguous block of memory.
6527 * This bit must be '1' for the vf_id_valid field to be
6530 #define HWRM_FUNC_RESET_INPUT_ENABLES_VF_ID_VALID UINT32_C(0x1)
6532 * The ID of the VF that this PF is trying to reset.
6533 * Only the parent PF shall be allowed to reset a child VF.
6535 * A parent PF driver shall use this field only when a specific child VF
6536 * is requested to be reset.
6539 /* This value indicates the level of a function reset. */
6540 uint8_t func_reset_level;
6542 * Reset the caller function and its children VFs (if any). If no
6543 * children functions exist, then reset the caller function only.
6545 #define HWRM_FUNC_RESET_INPUT_FUNC_RESET_LEVEL_RESETALL \
6547 /* Reset the caller function only */
6548 #define HWRM_FUNC_RESET_INPUT_FUNC_RESET_LEVEL_RESETME \
6551 * Reset all children VFs of the caller function driver if the
6552 * caller is a PF driver.
6553 * It is an error to specify this level by a VF driver.
6554 * It is an error to specify this level by a PF driver with
6557 #define HWRM_FUNC_RESET_INPUT_FUNC_RESET_LEVEL_RESETCHILDREN \
6560 * Reset a specific VF of the caller function driver if the caller
6561 * is the parent PF driver.
6562 * It is an error to specify this level by a VF driver.
6563 * It is an error to specify this level by a PF driver that is not
6564 * the parent of the VF that is being requested to reset.
6566 #define HWRM_FUNC_RESET_INPUT_FUNC_RESET_LEVEL_RESETVF \
6568 #define HWRM_FUNC_RESET_INPUT_FUNC_RESET_LEVEL_LAST \
6569 HWRM_FUNC_RESET_INPUT_FUNC_RESET_LEVEL_RESETVF
6571 } __attribute__((packed));
6573 /* hwrm_func_reset_output (size:128b/16B) */
6574 struct hwrm_func_reset_output {
6575 /* The specific error status for the command. */
6576 uint16_t error_code;
6577 /* The HWRM command request type. */
6579 /* The sequence ID from the original command. */
6581 /* The length of the response data in number of bytes. */
6583 uint8_t unused_0[7];
6585 * This field is used in Output records to indicate that the output
6586 * is completely written to RAM. This field should be read as '1'
6587 * to indicate that the output has been completely written.
6588 * When writing a command completion or response to an internal processor,
6589 * the order of writes has to be such that this field is written last.
6592 } __attribute__((packed));
6594 /********************
6595 * hwrm_func_getfid *
6596 ********************/
6599 /* hwrm_func_getfid_input (size:192b/24B) */
6600 struct hwrm_func_getfid_input {
6601 /* The HWRM command request type. */
6604 * The completion ring to send the completion event on. This should
6605 * be the NQ ID returned from the `nq_alloc` HWRM command.
6609 * The sequence ID is used by the driver for tracking multiple
6610 * commands. This ID is treated as opaque data by the firmware and
6611 * the value is returned in the `hwrm_resp_hdr` upon completion.
6615 * The target ID of the command:
6616 * * 0x0-0xFFF8 - The function ID
6617 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
6618 * * 0xFFFD - Reserved for user-space HWRM interface
6623 * A physical address pointer pointing to a host buffer that the
6624 * command's response data will be written. This can be either a host
6625 * physical address (HPA) or a guest physical address (GPA) and must
6626 * point to a physically contiguous block of memory.
6631 * This bit must be '1' for the pci_id field to be
6634 #define HWRM_FUNC_GETFID_INPUT_ENABLES_PCI_ID UINT32_C(0x1)
6636 * This value is the PCI ID of the queried function.
6637 * If ARI is enabled, then it is
6638 * Bus Number (8b):Function Number(8b). Otherwise, it is
6639 * Bus Number (8b):Device Number (5b):Function Number(3b).
6642 uint8_t unused_0[2];
6643 } __attribute__((packed));
6645 /* hwrm_func_getfid_output (size:128b/16B) */
6646 struct hwrm_func_getfid_output {
6647 /* The specific error status for the command. */
6648 uint16_t error_code;
6649 /* The HWRM command request type. */
6651 /* The sequence ID from the original command. */
6653 /* The length of the response data in number of bytes. */
6656 * FID value. This value is used to identify operations on the PCI
6657 * bus as belonging to a particular PCI function.
6660 uint8_t unused_0[5];
6662 * This field is used in Output records to indicate that the output
6663 * is completely written to RAM. This field should be read as '1'
6664 * to indicate that the output has been completely written.
6665 * When writing a command completion or response to an internal processor,
6666 * the order of writes has to be such that this field is written last.
6669 } __attribute__((packed));
6671 /**********************
6672 * hwrm_func_vf_alloc *
6673 **********************/
6676 /* hwrm_func_vf_alloc_input (size:192b/24B) */
6677 struct hwrm_func_vf_alloc_input {
6678 /* The HWRM command request type. */
6681 * The completion ring to send the completion event on. This should
6682 * be the NQ ID returned from the `nq_alloc` HWRM command.
6686 * The sequence ID is used by the driver for tracking multiple
6687 * commands. This ID is treated as opaque data by the firmware and
6688 * the value is returned in the `hwrm_resp_hdr` upon completion.
6692 * The target ID of the command:
6693 * * 0x0-0xFFF8 - The function ID
6694 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
6695 * * 0xFFFD - Reserved for user-space HWRM interface
6700 * A physical address pointer pointing to a host buffer that the
6701 * command's response data will be written. This can be either a host
6702 * physical address (HPA) or a guest physical address (GPA) and must
6703 * point to a physically contiguous block of memory.
6708 * This bit must be '1' for the first_vf_id field to be
6711 #define HWRM_FUNC_VF_ALLOC_INPUT_ENABLES_FIRST_VF_ID UINT32_C(0x1)
6713 * This value is used to identify a Virtual Function (VF).
6714 * The scope of VF ID is local within a PF.
6716 uint16_t first_vf_id;
6717 /* The number of virtual functions requested. */
6719 } __attribute__((packed));
6721 /* hwrm_func_vf_alloc_output (size:128b/16B) */
6722 struct hwrm_func_vf_alloc_output {
6723 /* The specific error status for the command. */
6724 uint16_t error_code;
6725 /* The HWRM command request type. */
6727 /* The sequence ID from the original command. */
6729 /* The length of the response data in number of bytes. */
6731 /* The ID of the first VF allocated. */
6732 uint16_t first_vf_id;
6733 uint8_t unused_0[5];
6735 * This field is used in Output records to indicate that the output
6736 * is completely written to RAM. This field should be read as '1'
6737 * to indicate that the output has been completely written.
6738 * When writing a command completion or response to an internal processor,
6739 * the order of writes has to be such that this field is written last.
6742 } __attribute__((packed));
6744 /*********************
6745 * hwrm_func_vf_free *
6746 *********************/
6749 /* hwrm_func_vf_free_input (size:192b/24B) */
6750 struct hwrm_func_vf_free_input {
6751 /* The HWRM command request type. */
6754 * The completion ring to send the completion event on. This should
6755 * be the NQ ID returned from the `nq_alloc` HWRM command.
6759 * The sequence ID is used by the driver for tracking multiple
6760 * commands. This ID is treated as opaque data by the firmware and
6761 * the value is returned in the `hwrm_resp_hdr` upon completion.
6765 * The target ID of the command:
6766 * * 0x0-0xFFF8 - The function ID
6767 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
6768 * * 0xFFFD - Reserved for user-space HWRM interface
6773 * A physical address pointer pointing to a host buffer that the
6774 * command's response data will be written. This can be either a host
6775 * physical address (HPA) or a guest physical address (GPA) and must
6776 * point to a physically contiguous block of memory.
6781 * This bit must be '1' for the first_vf_id field to be
6784 #define HWRM_FUNC_VF_FREE_INPUT_ENABLES_FIRST_VF_ID UINT32_C(0x1)
6786 * This value is used to identify a Virtual Function (VF).
6787 * The scope of VF ID is local within a PF.
6789 uint16_t first_vf_id;
6791 * The number of virtual functions requested.
6792 * 0xFFFF - Cleanup all children of this PF.
6795 } __attribute__((packed));
6797 /* hwrm_func_vf_free_output (size:128b/16B) */
6798 struct hwrm_func_vf_free_output {
6799 /* The specific error status for the command. */
6800 uint16_t error_code;
6801 /* The HWRM command request type. */
6803 /* The sequence ID from the original command. */
6805 /* The length of the response data in number of bytes. */
6807 uint8_t unused_0[7];
6809 * This field is used in Output records to indicate that the output
6810 * is completely written to RAM. This field should be read as '1'
6811 * to indicate that the output has been completely written.
6812 * When writing a command completion or response to an internal processor,
6813 * the order of writes has to be such that this field is written last.
6816 } __attribute__((packed));
6818 /********************
6819 * hwrm_func_vf_cfg *
6820 ********************/
6823 /* hwrm_func_vf_cfg_input (size:448b/56B) */
6824 struct hwrm_func_vf_cfg_input {
6825 /* The HWRM command request type. */
6828 * The completion ring to send the completion event on. This should
6829 * be the NQ ID returned from the `nq_alloc` HWRM command.
6833 * The sequence ID is used by the driver for tracking multiple
6834 * commands. This ID is treated as opaque data by the firmware and
6835 * the value is returned in the `hwrm_resp_hdr` upon completion.
6839 * The target ID of the command:
6840 * * 0x0-0xFFF8 - The function ID
6841 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
6842 * * 0xFFFD - Reserved for user-space HWRM interface
6847 * A physical address pointer pointing to a host buffer that the
6848 * command's response data will be written. This can be either a host
6849 * physical address (HPA) or a guest physical address (GPA) and must
6850 * point to a physically contiguous block of memory.
6855 * This bit must be '1' for the mtu field to be
6858 #define HWRM_FUNC_VF_CFG_INPUT_ENABLES_MTU \
6861 * This bit must be '1' for the guest_vlan field to be
6864 #define HWRM_FUNC_VF_CFG_INPUT_ENABLES_GUEST_VLAN \
6867 * This bit must be '1' for the async_event_cr field to be
6870 #define HWRM_FUNC_VF_CFG_INPUT_ENABLES_ASYNC_EVENT_CR \
6873 * This bit must be '1' for the dflt_mac_addr field to be
6876 #define HWRM_FUNC_VF_CFG_INPUT_ENABLES_DFLT_MAC_ADDR \
6879 * This bit must be '1' for the num_rsscos_ctxs field to be
6882 #define HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_RSSCOS_CTXS \
6885 * This bit must be '1' for the num_cmpl_rings field to be
6888 #define HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_CMPL_RINGS \
6891 * This bit must be '1' for the num_tx_rings field to be
6894 #define HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_TX_RINGS \
6897 * This bit must be '1' for the num_rx_rings field to be
6900 #define HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_RX_RINGS \
6903 * This bit must be '1' for the num_l2_ctxs field to be
6906 #define HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_L2_CTXS \
6909 * This bit must be '1' for the num_vnics field to be
6912 #define HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_VNICS \
6915 * This bit must be '1' for the num_stat_ctxs field to be
6918 #define HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_STAT_CTXS \
6921 * This bit must be '1' for the num_hw_ring_grps field to be
6924 #define HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_HW_RING_GRPS \
6927 * The maximum transmission unit requested on the function.
6928 * The HWRM should make sure that the mtu of
6929 * the function does not exceed the mtu of the physical
6930 * port that this function is associated with.
6932 * In addition to requesting mtu per function, it is
6933 * possible to configure mtu per transmit ring.
6934 * By default, the mtu of each transmit ring associated
6935 * with a function is equal to the mtu of the function.
6936 * The HWRM should make sure that the mtu of each transmit
6937 * ring that is assigned to a function has a valid mtu.
6941 * The guest VLAN for the function being configured.
6942 * This field's format is same as 802.1Q Tag's
6943 * Tag Control Information (TCI) format that includes both
6944 * Priority Code Point (PCP) and VLAN Identifier (VID).
6946 uint16_t guest_vlan;
6948 * ID of the target completion ring for receiving asynchronous
6949 * event completions. If this field is not valid, then the
6950 * HWRM shall use the default completion ring of the function
6951 * that is being configured as the target completion ring for
6952 * providing any asynchronous event completions for that
6954 * If this field is valid, then the HWRM shall use the
6955 * completion ring identified by this ID as the target
6956 * completion ring for providing any asynchronous event
6957 * completions for the function that is being configured.
6959 uint16_t async_event_cr;
6961 * This value is the current MAC address requested by the VF
6962 * driver to be configured on this VF. A value of
6963 * 00-00-00-00-00-00 indicates no MAC address configuration
6964 * is requested by the VF driver.
6965 * The parent PF driver may reject or overwrite this
6968 uint8_t dflt_mac_addr[6];
6971 * This bit requests that the firmware test to see if all the assets
6972 * requested in this command (i.e. number of TX rings) are available.
6973 * The firmware will return an error if the requested assets are
6974 * not available. The firwmare will NOT reserve the assets if they
6977 #define HWRM_FUNC_VF_CFG_INPUT_FLAGS_TX_ASSETS_TEST \
6980 * This bit requests that the firmware test to see if all the assets
6981 * requested in this command (i.e. number of RX rings) are available.
6982 * The firmware will return an error if the requested assets are
6983 * not available. The firwmare will NOT reserve the assets if they
6986 #define HWRM_FUNC_VF_CFG_INPUT_FLAGS_RX_ASSETS_TEST \
6989 * This bit requests that the firmware test to see if all the assets
6990 * requested in this command (i.e. number of CMPL rings) are available.
6991 * The firmware will return an error if the requested assets are
6992 * not available. The firwmare will NOT reserve the assets if they
6995 #define HWRM_FUNC_VF_CFG_INPUT_FLAGS_CMPL_ASSETS_TEST \
6998 * This bit requests that the firmware test to see if all the assets
6999 * requested in this command (i.e. number of RSS ctx) are available.
7000 * The firmware will return an error if the requested assets are
7001 * not available. The firwmare will NOT reserve the assets if they
7004 #define HWRM_FUNC_VF_CFG_INPUT_FLAGS_RSSCOS_CTX_ASSETS_TEST \
7007 * This bit requests that the firmware test to see if all the assets
7008 * requested in this command (i.e. number of ring groups) are available.
7009 * The firmware will return an error if the requested assets are
7010 * not available. The firwmare will NOT reserve the assets if they
7013 #define HWRM_FUNC_VF_CFG_INPUT_FLAGS_RING_GRP_ASSETS_TEST \
7016 * This bit requests that the firmware test to see if all the assets
7017 * requested in this command (i.e. number of stat ctx) are available.
7018 * The firmware will return an error if the requested assets are
7019 * not available. The firwmare will NOT reserve the assets if they
7022 #define HWRM_FUNC_VF_CFG_INPUT_FLAGS_STAT_CTX_ASSETS_TEST \
7025 * This bit requests that the firmware test to see if all the assets
7026 * requested in this command (i.e. number of VNICs) are available.
7027 * The firmware will return an error if the requested assets are
7028 * not available. The firwmare will NOT reserve the assets if they
7031 #define HWRM_FUNC_VF_CFG_INPUT_FLAGS_VNIC_ASSETS_TEST \
7034 * This bit requests that the firmware test to see if all the assets
7035 * requested in this command (i.e. number of L2 ctx) are available.
7036 * The firmware will return an error if the requested assets are
7037 * not available. The firwmare will NOT reserve the assets if they
7040 #define HWRM_FUNC_VF_CFG_INPUT_FLAGS_L2_CTX_ASSETS_TEST \
7042 /* The number of RSS/COS contexts requested for the VF. */
7043 uint16_t num_rsscos_ctxs;
7044 /* The number of completion rings requested for the VF. */
7045 uint16_t num_cmpl_rings;
7046 /* The number of transmit rings requested for the VF. */
7047 uint16_t num_tx_rings;
7048 /* The number of receive rings requested for the VF. */
7049 uint16_t num_rx_rings;
7050 /* The number of L2 contexts requested for the VF. */
7051 uint16_t num_l2_ctxs;
7052 /* The number of vnics requested for the VF. */
7054 /* The number of statistic contexts requested for the VF. */
7055 uint16_t num_stat_ctxs;
7056 /* The number of HW ring groups requested for the VF. */
7057 uint16_t num_hw_ring_grps;
7058 uint8_t unused_0[4];
7059 } __attribute__((packed));
7061 /* hwrm_func_vf_cfg_output (size:128b/16B) */
7062 struct hwrm_func_vf_cfg_output {
7063 /* The specific error status for the command. */
7064 uint16_t error_code;
7065 /* The HWRM command request type. */
7067 /* The sequence ID from the original command. */
7069 /* The length of the response data in number of bytes. */
7071 uint8_t unused_0[7];
7073 * This field is used in Output records to indicate that the output
7074 * is completely written to RAM. This field should be read as '1'
7075 * to indicate that the output has been completely written.
7076 * When writing a command completion or response to an internal processor,
7077 * the order of writes has to be such that this field is written last.
7080 } __attribute__((packed));
7082 /*******************
7084 *******************/
7087 /* hwrm_func_qcaps_input (size:192b/24B) */
7088 struct hwrm_func_qcaps_input {
7089 /* The HWRM command request type. */
7092 * The completion ring to send the completion event on. This should
7093 * be the NQ ID returned from the `nq_alloc` HWRM command.
7097 * The sequence ID is used by the driver for tracking multiple
7098 * commands. This ID is treated as opaque data by the firmware and
7099 * the value is returned in the `hwrm_resp_hdr` upon completion.
7103 * The target ID of the command:
7104 * * 0x0-0xFFF8 - The function ID
7105 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
7106 * * 0xFFFD - Reserved for user-space HWRM interface
7111 * A physical address pointer pointing to a host buffer that the
7112 * command's response data will be written. This can be either a host
7113 * physical address (HPA) or a guest physical address (GPA) and must
7114 * point to a physically contiguous block of memory.
7118 * Function ID of the function that is being queried.
7119 * 0xFF... (All Fs) if the query is for the requesting
7123 uint8_t unused_0[6];
7124 } __attribute__((packed));
7126 /* hwrm_func_qcaps_output (size:640b/80B) */
7127 struct hwrm_func_qcaps_output {
7128 /* The specific error status for the command. */
7129 uint16_t error_code;
7130 /* The HWRM command request type. */
7132 /* The sequence ID from the original command. */
7134 /* The length of the response data in number of bytes. */
7137 * FID value. This value is used to identify operations on the PCI
7138 * bus as belonging to a particular PCI function.
7142 * Port ID of port that this function is associated with.
7143 * Valid only for the PF.
7144 * 0xFF... (All Fs) if this function is not associated with
7146 * 0xFF... (All Fs) if this function is called from a VF.
7150 /* If 1, then Push mode is supported on this function. */
7151 #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_PUSH_MODE_SUPPORTED \
7154 * If 1, then the global MSI-X auto-masking is enabled for the
7157 #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_GLOBAL_MSIX_AUTOMASKING \
7160 * If 1, then the Precision Time Protocol (PTP) processing
7161 * is supported on this function.
7162 * The HWRM should enable PTP on only a single Physical
7163 * Function (PF) per port.
7165 #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_PTP_SUPPORTED \
7168 * If 1, then RDMA over Converged Ethernet (RoCE) v1
7169 * is supported on this function.
7171 #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_ROCE_V1_SUPPORTED \
7174 * If 1, then RDMA over Converged Ethernet (RoCE) v2
7175 * is supported on this function.
7177 #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_ROCE_V2_SUPPORTED \
7180 * If 1, then control and configuration of WoL magic packet
7181 * are supported on this function.
7183 #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_WOL_MAGICPKT_SUPPORTED \
7186 * If 1, then control and configuration of bitmap pattern
7187 * packet are supported on this function.
7189 #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_WOL_BMP_SUPPORTED \
7192 * If set to 1, then the control and configuration of rate limit
7193 * of an allocated TX ring on the queried function is supported.
7195 #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_TX_RING_RL_SUPPORTED \
7198 * If 1, then control and configuration of minimum and
7199 * maximum bandwidths are supported on the queried function.
7201 #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_TX_BW_CFG_SUPPORTED \
7204 * If the query is for a VF, then this flag shall be ignored.
7205 * If this query is for a PF and this flag is set to 1,
7206 * then the PF has the capability to set the rate limits
7207 * on the TX rings of its children VFs.
7208 * If this query is for a PF and this flag is set to 0, then
7209 * the PF does not have the capability to set the rate limits
7210 * on the TX rings of its children VFs.
7212 #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_VF_TX_RING_RL_SUPPORTED \
7215 * If the query is for a VF, then this flag shall be ignored.
7216 * If this query is for a PF and this flag is set to 1,
7217 * then the PF has the capability to set the minimum and/or
7218 * maximum bandwidths for its children VFs.
7219 * If this query is for a PF and this flag is set to 0, then
7220 * the PF does not have the capability to set the minimum or
7221 * maximum bandwidths for its children VFs.
7223 #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_VF_BW_CFG_SUPPORTED \
7226 * Standard TX Ring mode is used for the allocation of TX ring
7227 * and underlying scheduling resources that allow bandwidth
7228 * reservation and limit settings on the queried function.
7229 * If set to 1, then standard TX ring mode is supported
7230 * on the queried function.
7231 * If set to 0, then standard TX ring mode is not available
7232 * on the queried function.
7234 #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_STD_TX_RING_MODE_SUPPORTED \
7237 * If the query is for a VF, then this flag shall be ignored,
7238 * If this query is for a PF and this flag is set to 1,
7239 * then the PF has the capability to detect GENEVE tunnel
7242 #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_GENEVE_TUN_FLAGS_SUPPORTED \
7245 * If the query is for a VF, then this flag shall be ignored,
7246 * If this query is for a PF and this flag is set to 1,
7247 * then the PF has the capability to detect NVGRE tunnel
7250 #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_NVGRE_TUN_FLAGS_SUPPORTED \
7253 * If the query is for a VF, then this flag shall be ignored,
7254 * If this query is for a PF and this flag is set to 1,
7255 * then the PF has the capability to detect GRE tunnel
7258 #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_GRE_TUN_FLAGS_SUPPORTED \
7261 * If the query is for a VF, then this flag shall be ignored,
7262 * If this query is for a PF and this flag is set to 1,
7263 * then the PF has the capability to detect MPLS tunnel
7266 #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_MPLS_TUN_FLAGS_SUPPORTED \
7269 * If the query is for a VF, then this flag shall be ignored,
7270 * If this query is for a PF and this flag is set to 1,
7271 * then the PF has the capability to support pcie stats.
7273 #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_PCIE_STATS_SUPPORTED \
7276 * If the query is for a VF, then this flag shall be ignored,
7277 * If this query is for a PF and this flag is set to 1,
7278 * then the PF has the capability to adopt the VF's belonging
7281 #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_ADOPTED_PF_SUPPORTED \
7284 * If the query is for a VF, then this flag shall be ignored,
7285 * If this query is for a PF and this flag is set to 1,
7286 * then the PF has the administrative privilege to configure another PF
7288 #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_ADMIN_PF_SUPPORTED \
7291 * If the query is for a VF, then this flag shall be ignored.
7292 * If this query is for a PF and this flag is set to 1, then
7293 * the PF will know that the firmware has the capability to track
7294 * the virtual link status.
7296 #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_LINK_ADMIN_STATUS_SUPPORTED \
7299 * If 1, then this function supports the push mode that uses
7300 * write combine buffers and the long inline tx buffer descriptor.
7302 #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_WCB_PUSH_MODE \
7305 * If 1, then FW has capability to allocate TX rings dynamically
7306 * in ring alloc even if PF reserved pool is zero.
7307 * This bit will be used only for PFs.
7309 #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_DYNAMIC_TX_RING_ALLOC \
7312 * When this bit is '1', it indicates that core firmware is
7313 * capable of Hot Reset.
7315 #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_HOT_RESET_CAPABLE \
7318 * This flag will be set to 1 by the FW if FW supports adapter error
7321 #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_ERROR_RECOVERY_CAPABLE \
7324 * If the query is for a VF, then this flag shall be ignored.
7325 * If this query is for a PF and this flag is set to 1, then
7326 * the PF has the capability to support extended stats.
7328 #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_EXT_STATS_SUPPORTED \
7331 * This value is current MAC address configured for this
7332 * function. A value of 00-00-00-00-00-00 indicates no
7333 * MAC address is currently configured.
7335 uint8_t mac_address[6];
7337 * The maximum number of RSS/COS contexts that can be
7338 * allocated to the function.
7340 uint16_t max_rsscos_ctx;
7342 * The maximum number of completion rings that can be
7343 * allocated to the function.
7345 uint16_t max_cmpl_rings;
7347 * The maximum number of transmit rings that can be
7348 * allocated to the function.
7350 uint16_t max_tx_rings;
7352 * The maximum number of receive rings that can be
7353 * allocated to the function.
7355 uint16_t max_rx_rings;
7357 * The maximum number of L2 contexts that can be
7358 * allocated to the function.
7360 uint16_t max_l2_ctxs;
7362 * The maximum number of VNICs that can be
7363 * allocated to the function.
7367 * The identifier for the first VF enabled on a PF. This
7368 * is valid only on the PF with SR-IOV enabled.
7369 * 0xFF... (All Fs) if this command is called on a PF with
7370 * SR-IOV disabled or on a VF.
7372 uint16_t first_vf_id;
7374 * The maximum number of VFs that can be
7375 * allocated to the function. This is valid only on the
7376 * PF with SR-IOV enabled. 0xFF... (All Fs) if this
7377 * command is called on a PF with SR-IOV disabled or
7382 * The maximum number of statistic contexts that can be
7383 * allocated to the function.
7385 uint16_t max_stat_ctx;
7387 * The maximum number of Encapsulation records that can be
7388 * offloaded by this function.
7390 uint32_t max_encap_records;
7392 * The maximum number of decapsulation records that can
7393 * be offloaded by this function.
7395 uint32_t max_decap_records;
7397 * The maximum number of Exact Match (EM) flows that can be
7398 * offloaded by this function on the TX side.
7400 uint32_t max_tx_em_flows;
7402 * The maximum number of Wildcard Match (WM) flows that can
7403 * be offloaded by this function on the TX side.
7405 uint32_t max_tx_wm_flows;
7407 * The maximum number of Exact Match (EM) flows that can be
7408 * offloaded by this function on the RX side.
7410 uint32_t max_rx_em_flows;
7412 * The maximum number of Wildcard Match (WM) flows that can
7413 * be offloaded by this function on the RX side.
7415 uint32_t max_rx_wm_flows;
7417 * The maximum number of multicast filters that can
7418 * be supported by this function on the RX side.
7420 uint32_t max_mcast_filters;
7422 * The maximum value of flow_id that can be supported
7423 * in completion records.
7425 uint32_t max_flow_id;
7427 * The maximum number of HW ring groups that can be
7428 * supported on this function.
7430 uint32_t max_hw_ring_grps;
7432 * The maximum number of strict priority transmit rings
7433 * that can be allocated to the function.
7434 * This number indicates the maximum number of TX rings
7435 * that can be assigned strict priorities out of the
7436 * maximum number of TX rings that can be allocated
7437 * (max_tx_rings) to the function.
7439 uint16_t max_sp_tx_rings;
7442 * This field is used in Output records to indicate that the output
7443 * is completely written to RAM. This field should be read as '1'
7444 * to indicate that the output has been completely written.
7445 * When writing a command completion or response to an internal processor,
7446 * the order of writes has to be such that this field is written last.
7449 } __attribute__((packed));
7456 /* hwrm_func_qcfg_input (size:192b/24B) */
7457 struct hwrm_func_qcfg_input {
7458 /* The HWRM command request type. */
7461 * The completion ring to send the completion event on. This should
7462 * be the NQ ID returned from the `nq_alloc` HWRM command.
7466 * The sequence ID is used by the driver for tracking multiple
7467 * commands. This ID is treated as opaque data by the firmware and
7468 * the value is returned in the `hwrm_resp_hdr` upon completion.
7472 * The target ID of the command:
7473 * * 0x0-0xFFF8 - The function ID
7474 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
7475 * * 0xFFFD - Reserved for user-space HWRM interface
7480 * A physical address pointer pointing to a host buffer that the
7481 * command's response data will be written. This can be either a host
7482 * physical address (HPA) or a guest physical address (GPA) and must
7483 * point to a physically contiguous block of memory.
7487 * Function ID of the function that is being queried.
7488 * 0xFF... (All Fs) if the query is for the requesting
7492 uint8_t unused_0[6];
7493 } __attribute__((packed));
7495 /* hwrm_func_qcfg_output (size:704b/88B) */
7496 struct hwrm_func_qcfg_output {
7497 /* The specific error status for the command. */
7498 uint16_t error_code;
7499 /* The HWRM command request type. */
7501 /* The sequence ID from the original command. */
7503 /* The length of the response data in number of bytes. */
7506 * FID value. This value is used to identify operations on the PCI
7507 * bus as belonging to a particular PCI function.
7511 * Port ID of port that this function is associated with.
7512 * 0xFF... (All Fs) if this function is not associated with
7517 * This value is the current VLAN setting for this
7518 * function. The value of 0 for this field indicates
7519 * no priority tagging or VLAN is used.
7520 * This field's format is same as 802.1Q Tag's
7521 * Tag Control Information (TCI) format that includes both
7522 * Priority Code Point (PCP) and VLAN Identifier (VID).
7527 * If 1, then magic packet based Out-Of-Box WoL is enabled on
7528 * the port associated with this function.
7530 #define HWRM_FUNC_QCFG_OUTPUT_FLAGS_OOB_WOL_MAGICPKT_ENABLED \
7533 * If 1, then bitmap pattern based Out-Of-Box WoL packet is enabled
7534 * on the port associated with this function.
7536 #define HWRM_FUNC_QCFG_OUTPUT_FLAGS_OOB_WOL_BMP_ENABLED \
7539 * If set to 1, then FW based DCBX agent is enabled and running on
7540 * the port associated with this function.
7541 * If set to 0, then DCBX agent is not running in the firmware.
7543 #define HWRM_FUNC_QCFG_OUTPUT_FLAGS_FW_DCBX_AGENT_ENABLED \
7546 * Standard TX Ring mode is used for the allocation of TX ring
7547 * and underlying scheduling resources that allow bandwidth
7548 * reservation and limit settings on the queried function.
7549 * If set to 1, then standard TX ring mode is enabled
7550 * on the queried function.
7551 * If set to 0, then the standard TX ring mode is disabled
7552 * on the queried function. In this extended TX ring resource
7553 * mode, the minimum and maximum bandwidth settings are not
7554 * supported to allow the allocation of TX rings to span multiple
7557 #define HWRM_FUNC_QCFG_OUTPUT_FLAGS_STD_TX_RING_MODE_ENABLED \
7560 * If set to 1 then FW based LLDP agent is enabled and running on
7561 * the port associated with this function.
7562 * If set to 0 then the LLDP agent is not running in the firmware.
7564 #define HWRM_FUNC_QCFG_OUTPUT_FLAGS_FW_LLDP_AGENT_ENABLED \
7567 * If set to 1, then multi-host mode is active for this function.
7568 * If set to 0, then multi-host mode is inactive for this function
7569 * or not applicable for this device.
7571 #define HWRM_FUNC_QCFG_OUTPUT_FLAGS_MULTI_HOST \
7574 * If the function that is being queried is a PF, then the HWRM shall
7575 * set this field to 0 and the HWRM client shall ignore this field.
7576 * If the function that is being queried is a VF, then the HWRM shall
7577 * set this field to 1 if the queried VF is trusted, otherwise the HWRM
7578 * shall set this field to 0.
7580 #define HWRM_FUNC_QCFG_OUTPUT_FLAGS_TRUSTED_VF \
7583 * If set to 1, then secure mode is enabled for this function or device.
7584 * If set to 0, then secure mode is disabled (or normal mode) for this
7585 * function or device.
7587 #define HWRM_FUNC_QCFG_OUTPUT_FLAGS_SECURE_MODE_ENABLED \
7590 * If set to 1, then this PF is enabled with a preboot driver that
7591 * requires access to the legacy L2 ring model and legacy 32b
7592 * doorbells. If set to 0, then this PF is not allowed to use
7593 * the legacy L2 rings. This feature is not allowed on VFs and
7594 * is only relevant for devices that require a context backing
7597 #define HWRM_FUNC_QCFG_OUTPUT_FLAGS_PREBOOT_LEGACY_L2_RINGS \
7600 * This value is current MAC address configured for this
7601 * function. A value of 00-00-00-00-00-00 indicates no
7602 * MAC address is currently configured.
7604 uint8_t mac_address[6];
7606 * This value is current PCI ID of this
7607 * function. If ARI is enabled, then it is
7608 * Bus Number (8b):Function Number(8b). Otherwise, it is
7609 * Bus Number (8b):Device Number (4b):Function Number(4b).
7610 * If multi-host mode is active, the 4 lsb will indicate
7611 * the PF index for this function.
7615 * The number of RSS/COS contexts currently
7616 * allocated to the function.
7618 uint16_t alloc_rsscos_ctx;
7620 * The number of completion rings currently allocated to
7621 * the function. This does not include the rings allocated
7622 * to any children functions if any.
7624 uint16_t alloc_cmpl_rings;
7626 * The number of transmit rings currently allocated to
7627 * the function. This does not include the rings allocated
7628 * to any children functions if any.
7630 uint16_t alloc_tx_rings;
7632 * The number of receive rings currently allocated to
7633 * the function. This does not include the rings allocated
7634 * to any children functions if any.
7636 uint16_t alloc_rx_rings;
7637 /* The allocated number of L2 contexts to the function. */
7638 uint16_t alloc_l2_ctx;
7639 /* The allocated number of vnics to the function. */
7640 uint16_t alloc_vnics;
7642 * The maximum transmission unit of the function.
7643 * If the reported mtu value is non-zero then it will used for the
7644 * rings allocated on this function. otherwise the default
7645 * value is used if ring MTU is not specified.
7649 * The maximum receive unit of the function.
7650 * For vnics allocated on this function, this default
7651 * value is used if vnic MRU is not specified.
7654 /* The statistics context assigned to a function. */
7655 uint16_t stat_ctx_id;
7657 * The HWRM shall return Unknown value for this field
7658 * when this command is used to query VF's configuration.
7660 uint8_t port_partition_type;
7661 /* Single physical function */
7662 #define HWRM_FUNC_QCFG_OUTPUT_PORT_PARTITION_TYPE_SPF UINT32_C(0x0)
7663 /* Multiple physical functions */
7664 #define HWRM_FUNC_QCFG_OUTPUT_PORT_PARTITION_TYPE_MPFS UINT32_C(0x1)
7665 /* Network Partitioning 1.0 */
7666 #define HWRM_FUNC_QCFG_OUTPUT_PORT_PARTITION_TYPE_NPAR1_0 UINT32_C(0x2)
7667 /* Network Partitioning 1.5 */
7668 #define HWRM_FUNC_QCFG_OUTPUT_PORT_PARTITION_TYPE_NPAR1_5 UINT32_C(0x3)
7669 /* Network Partitioning 2.0 */
7670 #define HWRM_FUNC_QCFG_OUTPUT_PORT_PARTITION_TYPE_NPAR2_0 UINT32_C(0x4)
7672 #define HWRM_FUNC_QCFG_OUTPUT_PORT_PARTITION_TYPE_UNKNOWN \
7674 #define HWRM_FUNC_QCFG_OUTPUT_PORT_PARTITION_TYPE_LAST \
7675 HWRM_FUNC_QCFG_OUTPUT_PORT_PARTITION_TYPE_UNKNOWN
7677 * This field will indicate number of physical functions on this port_partition.
7678 * HWRM shall return unavail (i.e. value of 0) for this field
7679 * when this command is used to query VF's configuration or
7680 * from older firmware that doesn't support this field.
7682 uint8_t port_pf_cnt;
7683 /* number of PFs is not available */
7684 #define HWRM_FUNC_QCFG_OUTPUT_PORT_PF_CNT_UNAVAIL UINT32_C(0x0)
7685 #define HWRM_FUNC_QCFG_OUTPUT_PORT_PF_CNT_LAST \
7686 HWRM_FUNC_QCFG_OUTPUT_PORT_PF_CNT_UNAVAIL
7688 * The default VNIC ID assigned to a function that is
7691 uint16_t dflt_vnic_id;
7692 uint16_t max_mtu_configured;
7694 * Minimum BW allocated for this function.
7695 * The HWRM will translate this value into byte counter and
7696 * time interval used for the scheduler inside the device.
7697 * A value of 0 indicates the minimum bandwidth is not
7701 /* The bandwidth value. */
7702 #define HWRM_FUNC_QCFG_OUTPUT_MIN_BW_BW_VALUE_MASK \
7704 #define HWRM_FUNC_QCFG_OUTPUT_MIN_BW_BW_VALUE_SFT 0
7705 /* The granularity of the value (bits or bytes). */
7706 #define HWRM_FUNC_QCFG_OUTPUT_MIN_BW_SCALE \
7707 UINT32_C(0x10000000)
7708 /* Value is in bits. */
7709 #define HWRM_FUNC_QCFG_OUTPUT_MIN_BW_SCALE_BITS \
7710 (UINT32_C(0x0) << 28)
7711 /* Value is in bytes. */
7712 #define HWRM_FUNC_QCFG_OUTPUT_MIN_BW_SCALE_BYTES \
7713 (UINT32_C(0x1) << 28)
7714 #define HWRM_FUNC_QCFG_OUTPUT_MIN_BW_SCALE_LAST \
7715 HWRM_FUNC_QCFG_OUTPUT_MIN_BW_SCALE_BYTES
7716 /* bw_value_unit is 3 b */
7717 #define HWRM_FUNC_QCFG_OUTPUT_MIN_BW_BW_VALUE_UNIT_MASK \
7718 UINT32_C(0xe0000000)
7719 #define HWRM_FUNC_QCFG_OUTPUT_MIN_BW_BW_VALUE_UNIT_SFT 29
7720 /* Value is in Mb or MB (base 10). */
7721 #define HWRM_FUNC_QCFG_OUTPUT_MIN_BW_BW_VALUE_UNIT_MEGA \
7722 (UINT32_C(0x0) << 29)
7723 /* Value is in Kb or KB (base 10). */
7724 #define HWRM_FUNC_QCFG_OUTPUT_MIN_BW_BW_VALUE_UNIT_KILO \
7725 (UINT32_C(0x2) << 29)
7726 /* Value is in bits or bytes. */
7727 #define HWRM_FUNC_QCFG_OUTPUT_MIN_BW_BW_VALUE_UNIT_BASE \
7728 (UINT32_C(0x4) << 29)
7729 /* Value is in Gb or GB (base 10). */
7730 #define HWRM_FUNC_QCFG_OUTPUT_MIN_BW_BW_VALUE_UNIT_GIGA \
7731 (UINT32_C(0x6) << 29)
7732 /* Value is in 1/100th of a percentage of total bandwidth. */
7733 #define HWRM_FUNC_QCFG_OUTPUT_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 \
7734 (UINT32_C(0x1) << 29)
7736 #define HWRM_FUNC_QCFG_OUTPUT_MIN_BW_BW_VALUE_UNIT_INVALID \
7737 (UINT32_C(0x7) << 29)
7738 #define HWRM_FUNC_QCFG_OUTPUT_MIN_BW_BW_VALUE_UNIT_LAST \
7739 HWRM_FUNC_QCFG_OUTPUT_MIN_BW_BW_VALUE_UNIT_INVALID
7741 * Maximum BW allocated for this function.
7742 * The HWRM will translate this value into byte counter and
7743 * time interval used for the scheduler inside the device.
7744 * A value of 0 indicates that the maximum bandwidth is not
7748 /* The bandwidth value. */
7749 #define HWRM_FUNC_QCFG_OUTPUT_MAX_BW_BW_VALUE_MASK \
7751 #define HWRM_FUNC_QCFG_OUTPUT_MAX_BW_BW_VALUE_SFT 0
7752 /* The granularity of the value (bits or bytes). */
7753 #define HWRM_FUNC_QCFG_OUTPUT_MAX_BW_SCALE \
7754 UINT32_C(0x10000000)
7755 /* Value is in bits. */
7756 #define HWRM_FUNC_QCFG_OUTPUT_MAX_BW_SCALE_BITS \
7757 (UINT32_C(0x0) << 28)
7758 /* Value is in bytes. */
7759 #define HWRM_FUNC_QCFG_OUTPUT_MAX_BW_SCALE_BYTES \
7760 (UINT32_C(0x1) << 28)
7761 #define HWRM_FUNC_QCFG_OUTPUT_MAX_BW_SCALE_LAST \
7762 HWRM_FUNC_QCFG_OUTPUT_MAX_BW_SCALE_BYTES
7763 /* bw_value_unit is 3 b */
7764 #define HWRM_FUNC_QCFG_OUTPUT_MAX_BW_BW_VALUE_UNIT_MASK \
7765 UINT32_C(0xe0000000)
7766 #define HWRM_FUNC_QCFG_OUTPUT_MAX_BW_BW_VALUE_UNIT_SFT 29
7767 /* Value is in Mb or MB (base 10). */
7768 #define HWRM_FUNC_QCFG_OUTPUT_MAX_BW_BW_VALUE_UNIT_MEGA \
7769 (UINT32_C(0x0) << 29)
7770 /* Value is in Kb or KB (base 10). */
7771 #define HWRM_FUNC_QCFG_OUTPUT_MAX_BW_BW_VALUE_UNIT_KILO \
7772 (UINT32_C(0x2) << 29)
7773 /* Value is in bits or bytes. */
7774 #define HWRM_FUNC_QCFG_OUTPUT_MAX_BW_BW_VALUE_UNIT_BASE \
7775 (UINT32_C(0x4) << 29)
7776 /* Value is in Gb or GB (base 10). */
7777 #define HWRM_FUNC_QCFG_OUTPUT_MAX_BW_BW_VALUE_UNIT_GIGA \
7778 (UINT32_C(0x6) << 29)
7779 /* Value is in 1/100th of a percentage of total bandwidth. */
7780 #define HWRM_FUNC_QCFG_OUTPUT_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 \
7781 (UINT32_C(0x1) << 29)
7783 #define HWRM_FUNC_QCFG_OUTPUT_MAX_BW_BW_VALUE_UNIT_INVALID \
7784 (UINT32_C(0x7) << 29)
7785 #define HWRM_FUNC_QCFG_OUTPUT_MAX_BW_BW_VALUE_UNIT_LAST \
7786 HWRM_FUNC_QCFG_OUTPUT_MAX_BW_BW_VALUE_UNIT_INVALID
7788 * This value indicates the Edge virtual bridge mode for the
7789 * domain that this function belongs to.
7792 /* No Edge Virtual Bridging (EVB) */
7793 #define HWRM_FUNC_QCFG_OUTPUT_EVB_MODE_NO_EVB UINT32_C(0x0)
7794 /* Virtual Ethernet Bridge (VEB) */
7795 #define HWRM_FUNC_QCFG_OUTPUT_EVB_MODE_VEB UINT32_C(0x1)
7796 /* Virtual Ethernet Port Aggregator (VEPA) */
7797 #define HWRM_FUNC_QCFG_OUTPUT_EVB_MODE_VEPA UINT32_C(0x2)
7798 #define HWRM_FUNC_QCFG_OUTPUT_EVB_MODE_LAST \
7799 HWRM_FUNC_QCFG_OUTPUT_EVB_MODE_VEPA
7802 * This value indicates the PCIE device cache line size.
7803 * The cache line size allows the DMA writes to terminate and
7804 * start at the cache boundary.
7806 #define HWRM_FUNC_QCFG_OUTPUT_OPTIONS_CACHE_LINESIZE_MASK \
7808 #define HWRM_FUNC_QCFG_OUTPUT_OPTIONS_CACHE_LINESIZE_SFT 0
7809 /* Cache Line Size 64 bytes */
7810 #define HWRM_FUNC_QCFG_OUTPUT_OPTIONS_CACHE_LINESIZE_SIZE_64 \
7812 /* Cache Line Size 128 bytes */
7813 #define HWRM_FUNC_QCFG_OUTPUT_OPTIONS_CACHE_LINESIZE_SIZE_128 \
7815 #define HWRM_FUNC_QCFG_OUTPUT_OPTIONS_CACHE_LINESIZE_LAST \
7816 HWRM_FUNC_QCFG_OUTPUT_OPTIONS_CACHE_LINESIZE_SIZE_128
7817 /* This value is the virtual link admin state setting. */
7818 #define HWRM_FUNC_QCFG_OUTPUT_OPTIONS_LINK_ADMIN_STATE_MASK \
7820 #define HWRM_FUNC_QCFG_OUTPUT_OPTIONS_LINK_ADMIN_STATE_SFT 2
7821 /* Admin link state is in forced down mode. */
7822 #define HWRM_FUNC_QCFG_OUTPUT_OPTIONS_LINK_ADMIN_STATE_FORCED_DOWN \
7823 (UINT32_C(0x0) << 2)
7824 /* Admin link state is in forced up mode. */
7825 #define HWRM_FUNC_QCFG_OUTPUT_OPTIONS_LINK_ADMIN_STATE_FORCED_UP \
7826 (UINT32_C(0x1) << 2)
7827 /* Admin link state is in auto mode - follows the physical link state. */
7828 #define HWRM_FUNC_QCFG_OUTPUT_OPTIONS_LINK_ADMIN_STATE_AUTO \
7829 (UINT32_C(0x2) << 2)
7830 #define HWRM_FUNC_QCFG_OUTPUT_OPTIONS_LINK_ADMIN_STATE_LAST \
7831 HWRM_FUNC_QCFG_OUTPUT_OPTIONS_LINK_ADMIN_STATE_AUTO
7832 /* Reserved for future. */
7833 #define HWRM_FUNC_QCFG_OUTPUT_OPTIONS_RSVD_MASK \
7835 #define HWRM_FUNC_QCFG_OUTPUT_OPTIONS_RSVD_SFT 4
7837 * The number of VFs that are allocated to the function.
7838 * This is valid only on the PF with SR-IOV enabled.
7839 * 0xFF... (All Fs) if this command is called on a PF with
7840 * SR-IOV disabled or on a VF.
7844 * The number of allocated multicast filters for this
7845 * function on the RX side.
7847 uint32_t alloc_mcast_filters;
7849 * The number of allocated HW ring groups for this
7852 uint32_t alloc_hw_ring_grps;
7854 * The number of strict priority transmit rings out of
7855 * currently allocated TX rings to the function
7858 uint16_t alloc_sp_tx_rings;
7860 * The number of statistics contexts
7861 * currently reserved for the function.
7863 uint16_t alloc_stat_ctx;
7865 * This field specifies how many NQs are reserved for the PF.
7866 * Remaining NQs that belong to the PF are available for VFs.
7867 * Once a PF has created VFs, it cannot change how many NQs are
7868 * reserved for itself (since the NQs must be contiguous in HW).
7870 uint16_t alloc_msix;
7872 * The number of registered VF’s associated with the PF. This field
7873 * should be ignored when the request received on the VF interface.
7874 * This field will be updated on the PF interface to initiate
7875 * the unregister request on PF in the HOT Reset Process.
7877 uint16_t registered_vfs;
7879 * The size of the doorbell BAR in KBytes reserved for L2 including
7880 * any area that is shared between L2 and RoCE. The L2 driver
7881 * should only map the L2 portion of the doorbell BAR. Any rounding
7882 * of the BAR size to the native CPU page size should be performed
7883 * by the driver. If the value is zero, no special partitioning
7884 * of the doorbell BAR between L2 and RoCE is required.
7886 uint16_t l2_doorbell_bar_size_kb;
7889 * For backward compatibility this field must be set to 1.
7890 * Older drivers might look for this field to be 1 before
7891 * processing the message.
7895 * This GRC address location is used by the Host driver interfaces to poll
7896 * the adapter ready state to re-initiate the registration process again
7897 * after receiving the RESET Notify event.
7899 uint32_t reset_addr_poll;
7900 uint8_t unused_2[3];
7902 * This field is used in Output records to indicate that the output
7903 * is completely written to RAM. This field should be read as '1'
7904 * to indicate that the output has been completely written.
7905 * When writing a command completion or response to an internal processor,
7906 * the order of writes has to be such that this field is written last.
7909 } __attribute__((packed));
7916 /* hwrm_func_cfg_input (size:704b/88B) */
7917 struct hwrm_func_cfg_input {
7918 /* The HWRM command request type. */
7921 * The completion ring to send the completion event on. This should
7922 * be the NQ ID returned from the `nq_alloc` HWRM command.
7926 * The sequence ID is used by the driver for tracking multiple
7927 * commands. This ID is treated as opaque data by the firmware and
7928 * the value is returned in the `hwrm_resp_hdr` upon completion.
7932 * The target ID of the command:
7933 * * 0x0-0xFFF8 - The function ID
7934 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
7935 * * 0xFFFD - Reserved for user-space HWRM interface
7940 * A physical address pointer pointing to a host buffer that the
7941 * command's response data will be written. This can be either a host
7942 * physical address (HPA) or a guest physical address (GPA) and must
7943 * point to a physically contiguous block of memory.
7947 * Function ID of the function that is being
7949 * If set to 0xFF... (All Fs), then the the configuration is
7950 * for the requesting function.
7954 * This field specifies how many NQs will be reserved for the PF.
7955 * Remaining NQs that belong to the PF become available for VFs.
7956 * Once a PF has created VFs, it cannot change how many NQs are
7957 * reserved for itself (since the NQs must be contiguous in HW).
7962 * When this bit is '1', the function is disabled with
7963 * source MAC address check.
7964 * This is an anti-spoofing check. If this flag is set,
7965 * then the function shall be configured to disallow
7966 * transmission of frames with the source MAC address that
7967 * is configured for this function.
7969 #define HWRM_FUNC_CFG_INPUT_FLAGS_SRC_MAC_ADDR_CHECK_DISABLE \
7972 * When this bit is '1', the function is enabled with
7973 * source MAC address check.
7974 * This is an anti-spoofing check. If this flag is set,
7975 * then the function shall be configured to allow
7976 * transmission of frames with the source MAC address that
7977 * is configured for this function.
7979 #define HWRM_FUNC_CFG_INPUT_FLAGS_SRC_MAC_ADDR_CHECK_ENABLE \
7982 #define HWRM_FUNC_CFG_INPUT_FLAGS_RSVD_MASK \
7984 #define HWRM_FUNC_CFG_INPUT_FLAGS_RSVD_SFT 2
7986 * Standard TX Ring mode is used for the allocation of TX ring
7987 * and underlying scheduling resources that allow bandwidth
7988 * reservation and limit settings on the queried function.
7989 * If set to 1, then standard TX ring mode is requested to be
7990 * enabled on the function being configured.
7992 #define HWRM_FUNC_CFG_INPUT_FLAGS_STD_TX_RING_MODE_ENABLE \
7995 * Standard TX Ring mode is used for the allocation of TX ring
7996 * and underlying scheduling resources that allow bandwidth
7997 * reservation and limit settings on the queried function.
7998 * If set to 1, then the standard TX ring mode is requested to
7999 * be disabled on the function being configured. In this extended
8000 * TX ring resource mode, the minimum and maximum bandwidth settings
8001 * are not supported to allow the allocation of TX rings to
8002 * span multiple scheduler nodes.
8004 #define HWRM_FUNC_CFG_INPUT_FLAGS_STD_TX_RING_MODE_DISABLE \
8007 * If this bit is set, virtual mac address configured
8008 * in this command will be persistent over warm boot.
8010 #define HWRM_FUNC_CFG_INPUT_FLAGS_VIRT_MAC_PERSIST \
8013 * This bit only applies to the VF. If this bit is set, the statistic
8014 * context counters will not be cleared when the statistic context is freed
8015 * or a function reset is called on VF. This bit will be cleared when the PF
8016 * is unloaded or a function reset is called on the PF.
8018 #define HWRM_FUNC_CFG_INPUT_FLAGS_NO_AUTOCLEAR_STATISTIC \
8021 * This bit requests that the firmware test to see if all the assets
8022 * requested in this command (i.e. number of TX rings) are available.
8023 * The firmware will return an error if the requested assets are
8024 * not available. The firwmare will NOT reserve the assets if they
8027 #define HWRM_FUNC_CFG_INPUT_FLAGS_TX_ASSETS_TEST \
8030 * This bit requests that the firmware test to see if all the assets
8031 * requested in this command (i.e. number of RX rings) are available.
8032 * The firmware will return an error if the requested assets are
8033 * not available. The firwmare will NOT reserve the assets if they
8036 #define HWRM_FUNC_CFG_INPUT_FLAGS_RX_ASSETS_TEST \
8039 * This bit requests that the firmware test to see if all the assets
8040 * requested in this command (i.e. number of CMPL rings) are available.
8041 * The firmware will return an error if the requested assets are
8042 * not available. The firwmare will NOT reserve the assets if they
8045 #define HWRM_FUNC_CFG_INPUT_FLAGS_CMPL_ASSETS_TEST \
8048 * This bit requests that the firmware test to see if all the assets
8049 * requested in this command (i.e. number of RSS ctx) are available.
8050 * The firmware will return an error if the requested assets are
8051 * not available. The firwmare will NOT reserve the assets if they
8054 #define HWRM_FUNC_CFG_INPUT_FLAGS_RSSCOS_CTX_ASSETS_TEST \
8057 * This bit requests that the firmware test to see if all the assets
8058 * requested in this command (i.e. number of ring groups) are available.
8059 * The firmware will return an error if the requested assets are
8060 * not available. The firwmare will NOT reserve the assets if they
8063 #define HWRM_FUNC_CFG_INPUT_FLAGS_RING_GRP_ASSETS_TEST \
8066 * This bit requests that the firmware test to see if all the assets
8067 * requested in this command (i.e. number of stat ctx) are available.
8068 * The firmware will return an error if the requested assets are
8069 * not available. The firwmare will NOT reserve the assets if they
8072 #define HWRM_FUNC_CFG_INPUT_FLAGS_STAT_CTX_ASSETS_TEST \
8075 * This bit requests that the firmware test to see if all the assets
8076 * requested in this command (i.e. number of VNICs) are available.
8077 * The firmware will return an error if the requested assets are
8078 * not available. The firwmare will NOT reserve the assets if they
8081 #define HWRM_FUNC_CFG_INPUT_FLAGS_VNIC_ASSETS_TEST \
8084 * This bit requests that the firmware test to see if all the assets
8085 * requested in this command (i.e. number of L2 ctx) are available.
8086 * The firmware will return an error if the requested assets are
8087 * not available. The firwmare will NOT reserve the assets if they
8090 #define HWRM_FUNC_CFG_INPUT_FLAGS_L2_CTX_ASSETS_TEST \
8093 * This configuration change can be initiated by a PF driver. This
8094 * configuration request shall be targeted to a VF. From local host
8095 * resident HWRM clients, only the parent PF driver shall be allowed
8096 * to initiate this change on one of its children VFs. If this bit is
8097 * set to 1, then the VF that is being configured is requested to be
8100 #define HWRM_FUNC_CFG_INPUT_FLAGS_TRUSTED_VF_ENABLE \
8103 * When this bit it set, even if PF reserved pool size is zero,
8104 * FW will allow driver to create TX rings in ring alloc,
8105 * by reserving TX ring, S3 node dynamically.
8107 #define HWRM_FUNC_CFG_INPUT_FLAGS_DYNAMIC_TX_RING_ALLOC \
8110 * This bit requests that the firmware test to see if all the assets
8111 * requested in this command (i.e. number of NQ rings) are available.
8112 * The firmware will return an error if the requested assets are
8113 * not available. The firwmare will NOT reserve the assets if they
8116 #define HWRM_FUNC_CFG_INPUT_FLAGS_NQ_ASSETS_TEST \
8119 * This configuration change can be initiated by a PF driver. This
8120 * configuration request shall be targeted to a VF. From local host
8121 * resident HWRM clients, only the parent PF driver shall be allowed
8122 * to initiate this change on one of its children VFs. If this bit is
8123 * set to 1, then the VF that is being configured is requested to be
8126 #define HWRM_FUNC_CFG_INPUT_FLAGS_TRUSTED_VF_DISABLE \
8129 * This bit is used by preboot drivers on a PF that require access
8130 * to the legacy L2 ring model and legacy 32b doorbells. This
8131 * feature is not allowed on VFs and is only relevant for devices
8132 * that require a context backing store.
8134 #define HWRM_FUNC_CFG_INPUT_FLAGS_PREBOOT_LEGACY_L2_RINGS \
8138 * This bit must be '1' for the mtu field to be
8141 #define HWRM_FUNC_CFG_INPUT_ENABLES_MTU \
8144 * This bit must be '1' for the mru field to be
8147 #define HWRM_FUNC_CFG_INPUT_ENABLES_MRU \
8150 * This bit must be '1' for the num_rsscos_ctxs field to be
8153 #define HWRM_FUNC_CFG_INPUT_ENABLES_NUM_RSSCOS_CTXS \
8156 * This bit must be '1' for the num_cmpl_rings field to be
8159 #define HWRM_FUNC_CFG_INPUT_ENABLES_NUM_CMPL_RINGS \
8162 * This bit must be '1' for the num_tx_rings field to be
8165 #define HWRM_FUNC_CFG_INPUT_ENABLES_NUM_TX_RINGS \
8168 * This bit must be '1' for the num_rx_rings field to be
8171 #define HWRM_FUNC_CFG_INPUT_ENABLES_NUM_RX_RINGS \
8174 * This bit must be '1' for the num_l2_ctxs field to be
8177 #define HWRM_FUNC_CFG_INPUT_ENABLES_NUM_L2_CTXS \
8180 * This bit must be '1' for the num_vnics field to be
8183 #define HWRM_FUNC_CFG_INPUT_ENABLES_NUM_VNICS \
8186 * This bit must be '1' for the num_stat_ctxs field to be
8189 #define HWRM_FUNC_CFG_INPUT_ENABLES_NUM_STAT_CTXS \
8192 * This bit must be '1' for the dflt_mac_addr field to be
8195 #define HWRM_FUNC_CFG_INPUT_ENABLES_DFLT_MAC_ADDR \
8198 * This bit must be '1' for the dflt_vlan field to be
8201 #define HWRM_FUNC_CFG_INPUT_ENABLES_DFLT_VLAN \
8204 * This bit must be '1' for the dflt_ip_addr field to be
8207 #define HWRM_FUNC_CFG_INPUT_ENABLES_DFLT_IP_ADDR \
8210 * This bit must be '1' for the min_bw field to be
8213 #define HWRM_FUNC_CFG_INPUT_ENABLES_MIN_BW \
8216 * This bit must be '1' for the max_bw field to be
8219 #define HWRM_FUNC_CFG_INPUT_ENABLES_MAX_BW \
8222 * This bit must be '1' for the async_event_cr field to be
8225 #define HWRM_FUNC_CFG_INPUT_ENABLES_ASYNC_EVENT_CR \
8228 * This bit must be '1' for the vlan_antispoof_mode field to be
8231 #define HWRM_FUNC_CFG_INPUT_ENABLES_VLAN_ANTISPOOF_MODE \
8234 * This bit must be '1' for the allowed_vlan_pris field to be
8237 #define HWRM_FUNC_CFG_INPUT_ENABLES_ALLOWED_VLAN_PRIS \
8240 * This bit must be '1' for the evb_mode field to be
8243 #define HWRM_FUNC_CFG_INPUT_ENABLES_EVB_MODE \
8246 * This bit must be '1' for the num_mcast_filters field to be
8249 #define HWRM_FUNC_CFG_INPUT_ENABLES_NUM_MCAST_FILTERS \
8252 * This bit must be '1' for the num_hw_ring_grps field to be
8255 #define HWRM_FUNC_CFG_INPUT_ENABLES_NUM_HW_RING_GRPS \
8258 * This bit must be '1' for the cache_linesize field to be
8261 #define HWRM_FUNC_CFG_INPUT_ENABLES_CACHE_LINESIZE \
8264 * This bit must be '1' for the num_msix field to be
8267 #define HWRM_FUNC_CFG_INPUT_ENABLES_NUM_MSIX \
8270 * This bit must be '1' for the link admin state field to be
8273 #define HWRM_FUNC_CFG_INPUT_ENABLES_ADMIN_LINK_STATE \
8276 * The maximum transmission unit of the function.
8277 * The HWRM should make sure that the mtu of
8278 * the function does not exceed the mtu of the physical
8279 * port that this function is associated with.
8281 * In addition to configuring mtu per function, it is
8282 * possible to configure mtu per transmit ring.
8283 * By default, the mtu of each transmit ring associated
8284 * with a function is equal to the mtu of the function.
8285 * The HWRM should make sure that the mtu of each transmit
8286 * ring that is assigned to a function has a valid mtu.
8290 * The maximum receive unit of the function.
8291 * The HWRM should make sure that the mru of
8292 * the function does not exceed the mru of the physical
8293 * port that this function is associated with.
8295 * In addition to configuring mru per function, it is
8296 * possible to configure mru per vnic.
8297 * By default, the mru of each vnic associated
8298 * with a function is equal to the mru of the function.
8299 * The HWRM should make sure that the mru of each vnic
8300 * that is assigned to a function has a valid mru.
8304 * The number of RSS/COS contexts requested for the
8307 uint16_t num_rsscos_ctxs;
8309 * The number of completion rings requested for the
8310 * function. This does not include the rings allocated
8311 * to any children functions if any.
8313 uint16_t num_cmpl_rings;
8315 * The number of transmit rings requested for the function.
8316 * This does not include the rings allocated to any
8317 * children functions if any.
8319 uint16_t num_tx_rings;
8321 * The number of receive rings requested for the function.
8322 * This does not include the rings allocated
8323 * to any children functions if any.
8325 uint16_t num_rx_rings;
8326 /* The requested number of L2 contexts for the function. */
8327 uint16_t num_l2_ctxs;
8328 /* The requested number of vnics for the function. */
8330 /* The requested number of statistic contexts for the function. */
8331 uint16_t num_stat_ctxs;
8333 * The number of HW ring groups that should
8334 * be reserved for this function.
8336 uint16_t num_hw_ring_grps;
8337 /* The default MAC address for the function being configured. */
8338 uint8_t dflt_mac_addr[6];
8340 * The default VLAN for the function being configured.
8341 * This field's format is same as 802.1Q Tag's
8342 * Tag Control Information (TCI) format that includes both
8343 * Priority Code Point (PCP) and VLAN Identifier (VID).
8347 * The default IP address for the function being configured.
8348 * This address is only used in enabling source property check.
8350 uint32_t dflt_ip_addr[4];
8352 * Minimum BW allocated for this function.
8353 * The HWRM will translate this value into byte counter and
8354 * time interval used for the scheduler inside the device.
8357 /* The bandwidth value. */
8358 #define HWRM_FUNC_CFG_INPUT_MIN_BW_BW_VALUE_MASK \
8360 #define HWRM_FUNC_CFG_INPUT_MIN_BW_BW_VALUE_SFT 0
8361 /* The granularity of the value (bits or bytes). */
8362 #define HWRM_FUNC_CFG_INPUT_MIN_BW_SCALE \
8363 UINT32_C(0x10000000)
8364 /* Value is in bits. */
8365 #define HWRM_FUNC_CFG_INPUT_MIN_BW_SCALE_BITS \
8366 (UINT32_C(0x0) << 28)
8367 /* Value is in bytes. */
8368 #define HWRM_FUNC_CFG_INPUT_MIN_BW_SCALE_BYTES \
8369 (UINT32_C(0x1) << 28)
8370 #define HWRM_FUNC_CFG_INPUT_MIN_BW_SCALE_LAST \
8371 HWRM_FUNC_CFG_INPUT_MIN_BW_SCALE_BYTES
8372 /* bw_value_unit is 3 b */
8373 #define HWRM_FUNC_CFG_INPUT_MIN_BW_BW_VALUE_UNIT_MASK \
8374 UINT32_C(0xe0000000)
8375 #define HWRM_FUNC_CFG_INPUT_MIN_BW_BW_VALUE_UNIT_SFT 29
8376 /* Value is in Mb or MB (base 10). */
8377 #define HWRM_FUNC_CFG_INPUT_MIN_BW_BW_VALUE_UNIT_MEGA \
8378 (UINT32_C(0x0) << 29)
8379 /* Value is in Kb or KB (base 10). */
8380 #define HWRM_FUNC_CFG_INPUT_MIN_BW_BW_VALUE_UNIT_KILO \
8381 (UINT32_C(0x2) << 29)
8382 /* Value is in bits or bytes. */
8383 #define HWRM_FUNC_CFG_INPUT_MIN_BW_BW_VALUE_UNIT_BASE \
8384 (UINT32_C(0x4) << 29)
8385 /* Value is in Gb or GB (base 10). */
8386 #define HWRM_FUNC_CFG_INPUT_MIN_BW_BW_VALUE_UNIT_GIGA \
8387 (UINT32_C(0x6) << 29)
8388 /* Value is in 1/100th of a percentage of total bandwidth. */
8389 #define HWRM_FUNC_CFG_INPUT_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 \
8390 (UINT32_C(0x1) << 29)
8392 #define HWRM_FUNC_CFG_INPUT_MIN_BW_BW_VALUE_UNIT_INVALID \
8393 (UINT32_C(0x7) << 29)
8394 #define HWRM_FUNC_CFG_INPUT_MIN_BW_BW_VALUE_UNIT_LAST \
8395 HWRM_FUNC_CFG_INPUT_MIN_BW_BW_VALUE_UNIT_INVALID
8397 * Maximum BW allocated for this function.
8398 * The HWRM will translate this value into byte counter and
8399 * time interval used for the scheduler inside the device.
8402 /* The bandwidth value. */
8403 #define HWRM_FUNC_CFG_INPUT_MAX_BW_BW_VALUE_MASK \
8405 #define HWRM_FUNC_CFG_INPUT_MAX_BW_BW_VALUE_SFT 0
8406 /* The granularity of the value (bits or bytes). */
8407 #define HWRM_FUNC_CFG_INPUT_MAX_BW_SCALE \
8408 UINT32_C(0x10000000)
8409 /* Value is in bits. */
8410 #define HWRM_FUNC_CFG_INPUT_MAX_BW_SCALE_BITS \
8411 (UINT32_C(0x0) << 28)
8412 /* Value is in bytes. */
8413 #define HWRM_FUNC_CFG_INPUT_MAX_BW_SCALE_BYTES \
8414 (UINT32_C(0x1) << 28)
8415 #define HWRM_FUNC_CFG_INPUT_MAX_BW_SCALE_LAST \
8416 HWRM_FUNC_CFG_INPUT_MAX_BW_SCALE_BYTES
8417 /* bw_value_unit is 3 b */
8418 #define HWRM_FUNC_CFG_INPUT_MAX_BW_BW_VALUE_UNIT_MASK \
8419 UINT32_C(0xe0000000)
8420 #define HWRM_FUNC_CFG_INPUT_MAX_BW_BW_VALUE_UNIT_SFT 29
8421 /* Value is in Mb or MB (base 10). */
8422 #define HWRM_FUNC_CFG_INPUT_MAX_BW_BW_VALUE_UNIT_MEGA \
8423 (UINT32_C(0x0) << 29)
8424 /* Value is in Kb or KB (base 10). */
8425 #define HWRM_FUNC_CFG_INPUT_MAX_BW_BW_VALUE_UNIT_KILO \
8426 (UINT32_C(0x2) << 29)
8427 /* Value is in bits or bytes. */
8428 #define HWRM_FUNC_CFG_INPUT_MAX_BW_BW_VALUE_UNIT_BASE \
8429 (UINT32_C(0x4) << 29)
8430 /* Value is in Gb or GB (base 10). */
8431 #define HWRM_FUNC_CFG_INPUT_MAX_BW_BW_VALUE_UNIT_GIGA \
8432 (UINT32_C(0x6) << 29)
8433 /* Value is in 1/100th of a percentage of total bandwidth. */
8434 #define HWRM_FUNC_CFG_INPUT_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 \
8435 (UINT32_C(0x1) << 29)
8437 #define HWRM_FUNC_CFG_INPUT_MAX_BW_BW_VALUE_UNIT_INVALID \
8438 (UINT32_C(0x7) << 29)
8439 #define HWRM_FUNC_CFG_INPUT_MAX_BW_BW_VALUE_UNIT_LAST \
8440 HWRM_FUNC_CFG_INPUT_MAX_BW_BW_VALUE_UNIT_INVALID
8442 * ID of the target completion ring for receiving asynchronous
8443 * event completions. If this field is not valid, then the
8444 * HWRM shall use the default completion ring of the function
8445 * that is being configured as the target completion ring for
8446 * providing any asynchronous event completions for that
8448 * If this field is valid, then the HWRM shall use the
8449 * completion ring identified by this ID as the target
8450 * completion ring for providing any asynchronous event
8451 * completions for the function that is being configured.
8453 uint16_t async_event_cr;
8454 /* VLAN Anti-spoofing mode. */
8455 uint8_t vlan_antispoof_mode;
8456 /* No VLAN anti-spoofing checks are enabled */
8457 #define HWRM_FUNC_CFG_INPUT_VLAN_ANTISPOOF_MODE_NOCHECK \
8459 /* Validate VLAN against the configured VLAN(s) */
8460 #define HWRM_FUNC_CFG_INPUT_VLAN_ANTISPOOF_MODE_VALIDATE_VLAN \
8462 /* Insert VLAN if it does not exist, otherwise discard */
8463 #define HWRM_FUNC_CFG_INPUT_VLAN_ANTISPOOF_MODE_INSERT_IF_VLANDNE \
8465 /* Insert VLAN if it does not exist, override VLAN if it exists */
8466 #define HWRM_FUNC_CFG_INPUT_VLAN_ANTISPOOF_MODE_INSERT_OR_OVERRIDE_VLAN \
8468 #define HWRM_FUNC_CFG_INPUT_VLAN_ANTISPOOF_MODE_LAST \
8469 HWRM_FUNC_CFG_INPUT_VLAN_ANTISPOOF_MODE_INSERT_OR_OVERRIDE_VLAN
8471 * This bit field defines VLAN PRIs that are allowed on
8473 * If nth bit is set, then VLAN PRI n is allowed on this
8476 uint8_t allowed_vlan_pris;
8478 * The HWRM shall allow a PF driver to change EVB mode for the
8479 * partition it belongs to.
8480 * The HWRM shall not allow a VF driver to change the EVB mode.
8481 * The HWRM shall take into account the switching of EVB mode
8482 * from one to another and reconfigure hardware resources as
8484 * The switching from VEB to VEPA mode requires
8485 * the disabling of the loopback traffic. Additionally,
8486 * source knock outs are handled differently in VEB and VEPA
8490 /* No Edge Virtual Bridging (EVB) */
8491 #define HWRM_FUNC_CFG_INPUT_EVB_MODE_NO_EVB UINT32_C(0x0)
8492 /* Virtual Ethernet Bridge (VEB) */
8493 #define HWRM_FUNC_CFG_INPUT_EVB_MODE_VEB UINT32_C(0x1)
8494 /* Virtual Ethernet Port Aggregator (VEPA) */
8495 #define HWRM_FUNC_CFG_INPUT_EVB_MODE_VEPA UINT32_C(0x2)
8496 #define HWRM_FUNC_CFG_INPUT_EVB_MODE_LAST \
8497 HWRM_FUNC_CFG_INPUT_EVB_MODE_VEPA
8500 * This value indicates the PCIE device cache line size.
8501 * The cache line size allows the DMA writes to terminate and
8502 * start at the cache boundary.
8504 #define HWRM_FUNC_CFG_INPUT_OPTIONS_CACHE_LINESIZE_MASK \
8506 #define HWRM_FUNC_CFG_INPUT_OPTIONS_CACHE_LINESIZE_SFT 0
8507 /* Cache Line Size 64 bytes */
8508 #define HWRM_FUNC_CFG_INPUT_OPTIONS_CACHE_LINESIZE_SIZE_64 \
8510 /* Cache Line Size 128 bytes */
8511 #define HWRM_FUNC_CFG_INPUT_OPTIONS_CACHE_LINESIZE_SIZE_128 \
8513 #define HWRM_FUNC_CFG_INPUT_OPTIONS_CACHE_LINESIZE_LAST \
8514 HWRM_FUNC_CFG_INPUT_OPTIONS_CACHE_LINESIZE_SIZE_128
8515 /* This value is the virtual link admin state setting. */
8516 #define HWRM_FUNC_CFG_INPUT_OPTIONS_LINK_ADMIN_STATE_MASK \
8518 #define HWRM_FUNC_CFG_INPUT_OPTIONS_LINK_ADMIN_STATE_SFT 2
8519 /* Admin state is forced down. */
8520 #define HWRM_FUNC_CFG_INPUT_OPTIONS_LINK_ADMIN_STATE_FORCED_DOWN \
8521 (UINT32_C(0x0) << 2)
8522 /* Admin state is forced up. */
8523 #define HWRM_FUNC_CFG_INPUT_OPTIONS_LINK_ADMIN_STATE_FORCED_UP \
8524 (UINT32_C(0x1) << 2)
8525 /* Admin state is in auto mode - is to follow the physical link state. */
8526 #define HWRM_FUNC_CFG_INPUT_OPTIONS_LINK_ADMIN_STATE_AUTO \
8527 (UINT32_C(0x2) << 2)
8528 #define HWRM_FUNC_CFG_INPUT_OPTIONS_LINK_ADMIN_STATE_LAST \
8529 HWRM_FUNC_CFG_INPUT_OPTIONS_LINK_ADMIN_STATE_AUTO
8530 /* Reserved for future. */
8531 #define HWRM_FUNC_CFG_INPUT_OPTIONS_RSVD_MASK \
8533 #define HWRM_FUNC_CFG_INPUT_OPTIONS_RSVD_SFT 4
8535 * The number of multicast filters that should
8536 * be reserved for this function on the RX side.
8538 uint16_t num_mcast_filters;
8539 } __attribute__((packed));
8541 /* hwrm_func_cfg_output (size:128b/16B) */
8542 struct hwrm_func_cfg_output {
8543 /* The specific error status for the command. */
8544 uint16_t error_code;
8545 /* The HWRM command request type. */
8547 /* The sequence ID from the original command. */
8549 /* The length of the response data in number of bytes. */
8551 uint8_t unused_0[7];
8553 * This field is used in Output records to indicate that the output
8554 * is completely written to RAM. This field should be read as '1'
8555 * to indicate that the output has been completely written.
8556 * When writing a command completion or response to an internal processor,
8557 * the order of writes has to be such that this field is written last.
8560 } __attribute__((packed));
8562 /********************
8563 * hwrm_func_qstats *
8564 ********************/
8567 /* hwrm_func_qstats_input (size:192b/24B) */
8568 struct hwrm_func_qstats_input {
8569 /* The HWRM command request type. */
8572 * The completion ring to send the completion event on. This should
8573 * be the NQ ID returned from the `nq_alloc` HWRM command.
8577 * The sequence ID is used by the driver for tracking multiple
8578 * commands. This ID is treated as opaque data by the firmware and
8579 * the value is returned in the `hwrm_resp_hdr` upon completion.
8583 * The target ID of the command:
8584 * * 0x0-0xFFF8 - The function ID
8585 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
8586 * * 0xFFFD - Reserved for user-space HWRM interface
8591 * A physical address pointer pointing to a host buffer that the
8592 * command's response data will be written. This can be either a host
8593 * physical address (HPA) or a guest physical address (GPA) and must
8594 * point to a physically contiguous block of memory.
8598 * Function ID of the function that is being queried.
8599 * 0xFF... (All Fs) if the query is for the requesting
8603 uint8_t unused_0[6];
8604 } __attribute__((packed));
8606 /* hwrm_func_qstats_output (size:1408b/176B) */
8607 struct hwrm_func_qstats_output {
8608 /* The specific error status for the command. */
8609 uint16_t error_code;
8610 /* The HWRM command request type. */
8612 /* The sequence ID from the original command. */
8614 /* The length of the response data in number of bytes. */
8616 /* Number of transmitted unicast packets on the function. */
8617 uint64_t tx_ucast_pkts;
8618 /* Number of transmitted multicast packets on the function. */
8619 uint64_t tx_mcast_pkts;
8620 /* Number of transmitted broadcast packets on the function. */
8621 uint64_t tx_bcast_pkts;
8623 * Number of transmitted packets that were discarded due to
8624 * internal NIC resource problems. For transmit, this
8625 * can only happen if TMP is configured to allow dropping
8626 * in HOL blocking conditions, which is not a normal
8629 uint64_t tx_discard_pkts;
8631 * Number of dropped packets on transmit path on the function.
8632 * These are packets that have been marked for drop by
8633 * the TE CFA block or are packets that exceeded the
8634 * transmit MTU limit for the function.
8636 uint64_t tx_drop_pkts;
8637 /* Number of transmitted bytes for unicast traffic on the function. */
8638 uint64_t tx_ucast_bytes;
8639 /* Number of transmitted bytes for multicast traffic on the function. */
8640 uint64_t tx_mcast_bytes;
8641 /* Number of transmitted bytes for broadcast traffic on the function. */
8642 uint64_t tx_bcast_bytes;
8643 /* Number of received unicast packets on the function. */
8644 uint64_t rx_ucast_pkts;
8645 /* Number of received multicast packets on the function. */
8646 uint64_t rx_mcast_pkts;
8647 /* Number of received broadcast packets on the function. */
8648 uint64_t rx_bcast_pkts;
8650 * Number of received packets that were discarded on the function
8651 * due to resource limitations. This can happen for 3 reasons.
8652 * # The BD used for the packet has a bad format.
8653 * # There were no BDs available in the ring for the packet.
8654 * # There were no BDs available on-chip for the packet.
8656 uint64_t rx_discard_pkts;
8658 * Number of dropped packets on received path on the function.
8659 * These are packets that have been marked for drop by the
8662 uint64_t rx_drop_pkts;
8663 /* Number of received bytes for unicast traffic on the function. */
8664 uint64_t rx_ucast_bytes;
8665 /* Number of received bytes for multicast traffic on the function. */
8666 uint64_t rx_mcast_bytes;
8667 /* Number of received bytes for broadcast traffic on the function. */
8668 uint64_t rx_bcast_bytes;
8669 /* Number of aggregated unicast packets on the function. */
8670 uint64_t rx_agg_pkts;
8671 /* Number of aggregated unicast bytes on the function. */
8672 uint64_t rx_agg_bytes;
8673 /* Number of aggregation events on the function. */
8674 uint64_t rx_agg_events;
8675 /* Number of aborted aggregations on the function. */
8676 uint64_t rx_agg_aborts;
8677 uint8_t unused_0[7];
8679 * This field is used in Output records to indicate that the output
8680 * is completely written to RAM. This field should be read as '1'
8681 * to indicate that the output has been completely written.
8682 * When writing a command completion or response to an internal processor,
8683 * the order of writes has to be such that this field is written last.
8686 } __attribute__((packed));
8688 /***********************
8689 * hwrm_func_clr_stats *
8690 ***********************/
8693 /* hwrm_func_clr_stats_input (size:192b/24B) */
8694 struct hwrm_func_clr_stats_input {
8695 /* The HWRM command request type. */
8698 * The completion ring to send the completion event on. This should
8699 * be the NQ ID returned from the `nq_alloc` HWRM command.
8703 * The sequence ID is used by the driver for tracking multiple
8704 * commands. This ID is treated as opaque data by the firmware and
8705 * the value is returned in the `hwrm_resp_hdr` upon completion.
8709 * The target ID of the command:
8710 * * 0x0-0xFFF8 - The function ID
8711 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
8712 * * 0xFFFD - Reserved for user-space HWRM interface
8717 * A physical address pointer pointing to a host buffer that the
8718 * command's response data will be written. This can be either a host
8719 * physical address (HPA) or a guest physical address (GPA) and must
8720 * point to a physically contiguous block of memory.
8724 * Function ID of the function.
8725 * 0xFF... (All Fs) if the query is for the requesting
8729 uint8_t unused_0[6];
8730 } __attribute__((packed));
8732 /* hwrm_func_clr_stats_output (size:128b/16B) */
8733 struct hwrm_func_clr_stats_output {
8734 /* The specific error status for the command. */
8735 uint16_t error_code;
8736 /* The HWRM command request type. */
8738 /* The sequence ID from the original command. */
8740 /* The length of the response data in number of bytes. */
8742 uint8_t unused_0[7];
8744 * This field is used in Output records to indicate that the output
8745 * is completely written to RAM. This field should be read as '1'
8746 * to indicate that the output has been completely written.
8747 * When writing a command completion or response to an internal processor,
8748 * the order of writes has to be such that this field is written last.
8751 } __attribute__((packed));
8753 /**************************
8754 * hwrm_func_vf_resc_free *
8755 **************************/
8758 /* hwrm_func_vf_resc_free_input (size:192b/24B) */
8759 struct hwrm_func_vf_resc_free_input {
8760 /* The HWRM command request type. */
8763 * The completion ring to send the completion event on. This should
8764 * be the NQ ID returned from the `nq_alloc` HWRM command.
8768 * The sequence ID is used by the driver for tracking multiple
8769 * commands. This ID is treated as opaque data by the firmware and
8770 * the value is returned in the `hwrm_resp_hdr` upon completion.
8774 * The target ID of the command:
8775 * * 0x0-0xFFF8 - The function ID
8776 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
8777 * * 0xFFFD - Reserved for user-space HWRM interface
8782 * A physical address pointer pointing to a host buffer that the
8783 * command's response data will be written. This can be either a host
8784 * physical address (HPA) or a guest physical address (GPA) and must
8785 * point to a physically contiguous block of memory.
8789 * This value is used to identify a Virtual Function (VF).
8790 * The scope of VF ID is local within a PF.
8793 uint8_t unused_0[6];
8794 } __attribute__((packed));
8796 /* hwrm_func_vf_resc_free_output (size:128b/16B) */
8797 struct hwrm_func_vf_resc_free_output {
8798 /* The specific error status for the command. */
8799 uint16_t error_code;
8800 /* The HWRM command request type. */
8802 /* The sequence ID from the original command. */
8804 /* The length of the response data in number of bytes. */
8806 uint8_t unused_0[7];
8808 * This field is used in Output records to indicate that the output
8809 * is completely written to RAM. This field should be read as '1'
8810 * to indicate that the output has been completely written.
8811 * When writing a command completion or response to an internal processor,
8812 * the order of writes has to be such that this field is written last.
8815 } __attribute__((packed));
8817 /**********************
8818 * hwrm_func_drv_rgtr *
8819 **********************/
8822 /* hwrm_func_drv_rgtr_input (size:896b/112B) */
8823 struct hwrm_func_drv_rgtr_input {
8824 /* The HWRM command request type. */
8827 * The completion ring to send the completion event on. This should
8828 * be the NQ ID returned from the `nq_alloc` HWRM command.
8832 * The sequence ID is used by the driver for tracking multiple
8833 * commands. This ID is treated as opaque data by the firmware and
8834 * the value is returned in the `hwrm_resp_hdr` upon completion.
8838 * The target ID of the command:
8839 * * 0x0-0xFFF8 - The function ID
8840 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
8841 * * 0xFFFD - Reserved for user-space HWRM interface
8846 * A physical address pointer pointing to a host buffer that the
8847 * command's response data will be written. This can be either a host
8848 * physical address (HPA) or a guest physical address (GPA) and must
8849 * point to a physically contiguous block of memory.
8854 * When this bit is '1', the function driver is requesting
8855 * all requests from its children VF drivers to be
8856 * forwarded to itself.
8857 * This flag can only be set by the PF driver.
8858 * If a VF driver sets this flag, it should be ignored
8861 #define HWRM_FUNC_DRV_RGTR_INPUT_FLAGS_FWD_ALL_MODE \
8864 * When this bit is '1', the function is requesting none of
8865 * the requests from its children VF drivers to be
8866 * forwarded to itself.
8867 * This flag can only be set by the PF driver.
8868 * If a VF driver sets this flag, it should be ignored
8871 #define HWRM_FUNC_DRV_RGTR_INPUT_FLAGS_FWD_NONE_MODE \
8874 * When this bit is '1', then ver_maj_8b, ver_min_8b, ver_upd_8b
8875 * fields shall be ignored and ver_maj, ver_min, ver_upd
8876 * and ver_patch shall be used for the driver version information.
8877 * When this bit is '0', then ver_maj_8b, ver_min_8b, ver_upd_8b
8878 * fields shall be used for the driver version information and
8879 * ver_maj, ver_min, ver_upd and ver_patch shall be ignored.
8881 #define HWRM_FUNC_DRV_RGTR_INPUT_FLAGS_16BIT_VER_MODE \
8884 * When this bit is '1', the function is indicating support of
8885 * 64bit flow handle. The firmware that only supports 64bit flow
8886 * handle should check this bit before allowing processing of
8887 * HWRM_CFA_FLOW_XXX commands from the requesting function as firmware
8888 * with 64bit flow handle support can only be compatible with drivers
8889 * that support 64bit flow handle. The legacy drivers that don't support
8890 * 64bit flow handle won't be able to use HWRM_CFA_FLOW_XXX commands when
8891 * running with new firmware that only supports 64bit flow handle. The new
8892 * firmware support 64bit flow handle returns HWRM_ERR_CODE_CMD_NOT_SUPPORTED
8893 * status to the legacy driver when encounters these commands.
8895 #define HWRM_FUNC_DRV_RGTR_INPUT_FLAGS_FLOW_HANDLE_64BIT_MODE \
8898 * When this bit is '1', the function is indicating support of
8899 * Hot Reset. The driver interface will destroy the resources,
8900 * unregister the function and register again up on receiving
8901 * the RESET_NOTIFY Async notification from the core firmware.
8902 * The core firmware will this use flag and trigger the Hot Reset
8903 * process only if all the registered driver instances are capable
8906 #define HWRM_FUNC_DRV_RGTR_INPUT_FLAGS_HOT_RESET_SUPPORT \
8909 * When this bit is 1, the function is indicating the support of the
8910 * error recovery capability. Error recovery support will be used by
8911 * firmware only if all the driver instances support error recovery
8912 * process. By setting this bit, driver is indicating support for
8913 * corresponding async event completion message. These will be
8914 * delivered to the driver even if they did not register for it.
8915 * If supported, after receiving reset notify async event with fatal
8916 * flag set in event data1, then all the drivers have to tear down
8917 * their resources without sending any HWRM commands to FW.
8919 #define HWRM_FUNC_DRV_RGTR_INPUT_FLAGS_ERROR_RECOVERY_SUPPORT \
8923 * This bit must be '1' for the os_type field to be
8926 #define HWRM_FUNC_DRV_RGTR_INPUT_ENABLES_OS_TYPE \
8929 * This bit must be '1' for the ver field to be
8932 #define HWRM_FUNC_DRV_RGTR_INPUT_ENABLES_VER \
8935 * This bit must be '1' for the timestamp field to be
8938 #define HWRM_FUNC_DRV_RGTR_INPUT_ENABLES_TIMESTAMP \
8941 * This bit must be '1' for the vf_req_fwd field to be
8944 #define HWRM_FUNC_DRV_RGTR_INPUT_ENABLES_VF_REQ_FWD \
8947 * This bit must be '1' for the async_event_fwd field to be
8950 #define HWRM_FUNC_DRV_RGTR_INPUT_ENABLES_ASYNC_EVENT_FWD \
8952 /* This value indicates the type of OS. The values are based on CIM_OperatingSystem.mof file as published by the DMTF. */
8955 #define HWRM_FUNC_DRV_RGTR_INPUT_OS_TYPE_UNKNOWN UINT32_C(0x0)
8956 /* Other OS not listed below. */
8957 #define HWRM_FUNC_DRV_RGTR_INPUT_OS_TYPE_OTHER UINT32_C(0x1)
8959 #define HWRM_FUNC_DRV_RGTR_INPUT_OS_TYPE_MSDOS UINT32_C(0xe)
8961 #define HWRM_FUNC_DRV_RGTR_INPUT_OS_TYPE_WINDOWS UINT32_C(0x12)
8963 #define HWRM_FUNC_DRV_RGTR_INPUT_OS_TYPE_SOLARIS UINT32_C(0x1d)
8965 #define HWRM_FUNC_DRV_RGTR_INPUT_OS_TYPE_LINUX UINT32_C(0x24)
8967 #define HWRM_FUNC_DRV_RGTR_INPUT_OS_TYPE_FREEBSD UINT32_C(0x2a)
8968 /* VMware ESXi OS. */
8969 #define HWRM_FUNC_DRV_RGTR_INPUT_OS_TYPE_ESXI UINT32_C(0x68)
8970 /* Microsoft Windows 8 64-bit OS. */
8971 #define HWRM_FUNC_DRV_RGTR_INPUT_OS_TYPE_WIN864 UINT32_C(0x73)
8972 /* Microsoft Windows Server 2012 R2 OS. */
8973 #define HWRM_FUNC_DRV_RGTR_INPUT_OS_TYPE_WIN2012R2 UINT32_C(0x74)
8975 #define HWRM_FUNC_DRV_RGTR_INPUT_OS_TYPE_UEFI UINT32_C(0x8000)
8976 #define HWRM_FUNC_DRV_RGTR_INPUT_OS_TYPE_LAST \
8977 HWRM_FUNC_DRV_RGTR_INPUT_OS_TYPE_UEFI
8978 /* This is the 8bit major version of the driver. */
8980 /* This is the 8bit minor version of the driver. */
8982 /* This is the 8bit update version of the driver. */
8984 uint8_t unused_0[3];
8986 * This is a 32-bit timestamp provided by the driver for
8988 * The timestamp is in multiples of 1ms.
8991 uint8_t unused_1[4];
8993 * This is a 256-bit bit mask provided by the PF driver for
8994 * letting the HWRM know what commands issued by the VF driver
8995 * to the HWRM should be forwarded to the PF driver.
8996 * Nth bit refers to the Nth req_type.
8998 * Setting Nth bit to 1 indicates that requests from the
8999 * VF driver with req_type equal to N shall be forwarded to
9000 * the parent PF driver.
9002 * This field is not valid for the VF driver.
9004 uint32_t vf_req_fwd[8];
9006 * This is a 256-bit bit mask provided by the function driver
9007 * (PF or VF driver) to indicate the list of asynchronous event
9008 * completions to be forwarded.
9010 * Nth bit refers to the Nth event_id.
9012 * Setting Nth bit to 1 by the function driver shall result in
9013 * the HWRM forwarding asynchronous event completion with
9014 * event_id equal to N.
9016 * If all bits are set to 0 (value of 0), then the HWRM shall
9017 * not forward any asynchronous event completion to this
9020 uint32_t async_event_fwd[8];
9021 /* This is the 16bit major version of the driver. */
9023 /* This is the 16bit minor version of the driver. */
9025 /* This is the 16bit update version of the driver. */
9027 /* This is the 16bit patch version of the driver. */
9029 } __attribute__((packed));
9031 /* hwrm_func_drv_rgtr_output (size:128b/16B) */
9032 struct hwrm_func_drv_rgtr_output {
9033 /* The specific error status for the command. */
9034 uint16_t error_code;
9035 /* The HWRM command request type. */
9037 /* The sequence ID from the original command. */
9039 /* The length of the response data in number of bytes. */
9043 * When this bit is '1', it indicates that the
9044 * HWRM_FUNC_DRV_IF_CHANGE call is supported.
9046 #define HWRM_FUNC_DRV_RGTR_OUTPUT_FLAGS_IF_CHANGE_SUPPORTED \
9048 uint8_t unused_0[3];
9050 * This field is used in Output records to indicate that the output
9051 * is completely written to RAM. This field should be read as '1'
9052 * to indicate that the output has been completely written.
9053 * When writing a command completion or response to an internal processor,
9054 * the order of writes has to be such that this field is written last.
9057 } __attribute__((packed));
9059 /************************
9060 * hwrm_func_drv_unrgtr *
9061 ************************/
9064 /* hwrm_func_drv_unrgtr_input (size:192b/24B) */
9065 struct hwrm_func_drv_unrgtr_input {
9066 /* The HWRM command request type. */
9069 * The completion ring to send the completion event on. This should
9070 * be the NQ ID returned from the `nq_alloc` HWRM command.
9074 * The sequence ID is used by the driver for tracking multiple
9075 * commands. This ID is treated as opaque data by the firmware and
9076 * the value is returned in the `hwrm_resp_hdr` upon completion.
9080 * The target ID of the command:
9081 * * 0x0-0xFFF8 - The function ID
9082 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
9083 * * 0xFFFD - Reserved for user-space HWRM interface
9088 * A physical address pointer pointing to a host buffer that the
9089 * command's response data will be written. This can be either a host
9090 * physical address (HPA) or a guest physical address (GPA) and must
9091 * point to a physically contiguous block of memory.
9096 * When this bit is '1', the function driver is notifying
9097 * the HWRM to prepare for the shutdown.
9099 #define HWRM_FUNC_DRV_UNRGTR_INPUT_FLAGS_PREPARE_FOR_SHUTDOWN \
9101 uint8_t unused_0[4];
9102 } __attribute__((packed));
9104 /* hwrm_func_drv_unrgtr_output (size:128b/16B) */
9105 struct hwrm_func_drv_unrgtr_output {
9106 /* The specific error status for the command. */
9107 uint16_t error_code;
9108 /* The HWRM command request type. */
9110 /* The sequence ID from the original command. */
9112 /* The length of the response data in number of bytes. */
9114 uint8_t unused_0[7];
9116 * This field is used in Output records to indicate that the output
9117 * is completely written to RAM. This field should be read as '1'
9118 * to indicate that the output has been completely written.
9119 * When writing a command completion or response to an internal processor,
9120 * the order of writes has to be such that this field is written last.
9123 } __attribute__((packed));
9125 /**********************
9126 * hwrm_func_buf_rgtr *
9127 **********************/
9130 /* hwrm_func_buf_rgtr_input (size:1024b/128B) */
9131 struct hwrm_func_buf_rgtr_input {
9132 /* The HWRM command request type. */
9135 * The completion ring to send the completion event on. This should
9136 * be the NQ ID returned from the `nq_alloc` HWRM command.
9140 * The sequence ID is used by the driver for tracking multiple
9141 * commands. This ID is treated as opaque data by the firmware and
9142 * the value is returned in the `hwrm_resp_hdr` upon completion.
9146 * The target ID of the command:
9147 * * 0x0-0xFFF8 - The function ID
9148 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
9149 * * 0xFFFD - Reserved for user-space HWRM interface
9154 * A physical address pointer pointing to a host buffer that the
9155 * command's response data will be written. This can be either a host
9156 * physical address (HPA) or a guest physical address (GPA) and must
9157 * point to a physically contiguous block of memory.
9162 * This bit must be '1' for the vf_id field to be
9165 #define HWRM_FUNC_BUF_RGTR_INPUT_ENABLES_VF_ID UINT32_C(0x1)
9167 * This bit must be '1' for the err_buf_addr field to be
9170 #define HWRM_FUNC_BUF_RGTR_INPUT_ENABLES_ERR_BUF_ADDR UINT32_C(0x2)
9172 * This value is used to identify a Virtual Function (VF).
9173 * The scope of VF ID is local within a PF.
9177 * This field represents the number of pages used for request
9180 uint16_t req_buf_num_pages;
9182 * This field represents the page size used for request
9185 uint16_t req_buf_page_size;
9187 #define HWRM_FUNC_BUF_RGTR_INPUT_REQ_BUF_PAGE_SIZE_16B UINT32_C(0x4)
9189 #define HWRM_FUNC_BUF_RGTR_INPUT_REQ_BUF_PAGE_SIZE_4K UINT32_C(0xc)
9191 #define HWRM_FUNC_BUF_RGTR_INPUT_REQ_BUF_PAGE_SIZE_8K UINT32_C(0xd)
9193 #define HWRM_FUNC_BUF_RGTR_INPUT_REQ_BUF_PAGE_SIZE_64K UINT32_C(0x10)
9195 #define HWRM_FUNC_BUF_RGTR_INPUT_REQ_BUF_PAGE_SIZE_2M UINT32_C(0x15)
9197 #define HWRM_FUNC_BUF_RGTR_INPUT_REQ_BUF_PAGE_SIZE_4M UINT32_C(0x16)
9199 #define HWRM_FUNC_BUF_RGTR_INPUT_REQ_BUF_PAGE_SIZE_1G UINT32_C(0x1e)
9200 #define HWRM_FUNC_BUF_RGTR_INPUT_REQ_BUF_PAGE_SIZE_LAST \
9201 HWRM_FUNC_BUF_RGTR_INPUT_REQ_BUF_PAGE_SIZE_1G
9202 /* The length of the request buffer per VF in bytes. */
9203 uint16_t req_buf_len;
9204 /* The length of the response buffer in bytes. */
9205 uint16_t resp_buf_len;
9206 uint8_t unused_0[2];
9207 /* This field represents the page address of page #0. */
9208 uint64_t req_buf_page_addr0;
9209 /* This field represents the page address of page #1. */
9210 uint64_t req_buf_page_addr1;
9211 /* This field represents the page address of page #2. */
9212 uint64_t req_buf_page_addr2;
9213 /* This field represents the page address of page #3. */
9214 uint64_t req_buf_page_addr3;
9215 /* This field represents the page address of page #4. */
9216 uint64_t req_buf_page_addr4;
9217 /* This field represents the page address of page #5. */
9218 uint64_t req_buf_page_addr5;
9219 /* This field represents the page address of page #6. */
9220 uint64_t req_buf_page_addr6;
9221 /* This field represents the page address of page #7. */
9222 uint64_t req_buf_page_addr7;
9223 /* This field represents the page address of page #8. */
9224 uint64_t req_buf_page_addr8;
9225 /* This field represents the page address of page #9. */
9226 uint64_t req_buf_page_addr9;
9228 * This field is used to receive the error reporting from
9229 * the chipset. Only applicable for PFs.
9231 uint64_t error_buf_addr;
9233 * This field is used to receive the response forwarded by the
9236 uint64_t resp_buf_addr;
9237 } __attribute__((packed));
9239 /* hwrm_func_buf_rgtr_output (size:128b/16B) */
9240 struct hwrm_func_buf_rgtr_output {
9241 /* The specific error status for the command. */
9242 uint16_t error_code;
9243 /* The HWRM command request type. */
9245 /* The sequence ID from the original command. */
9247 /* The length of the response data in number of bytes. */
9249 uint8_t unused_0[7];
9251 * This field is used in Output records to indicate that the output
9252 * is completely written to RAM. This field should be read as '1'
9253 * to indicate that the output has been completely written.
9254 * When writing a command completion or response to an internal processor,
9255 * the order of writes has to be such that this field is written last.
9258 } __attribute__((packed));
9260 /************************
9261 * hwrm_func_buf_unrgtr *
9262 ************************/
9265 /* hwrm_func_buf_unrgtr_input (size:192b/24B) */
9266 struct hwrm_func_buf_unrgtr_input {
9267 /* The HWRM command request type. */
9270 * The completion ring to send the completion event on. This should
9271 * be the NQ ID returned from the `nq_alloc` HWRM command.
9275 * The sequence ID is used by the driver for tracking multiple
9276 * commands. This ID is treated as opaque data by the firmware and
9277 * the value is returned in the `hwrm_resp_hdr` upon completion.
9281 * The target ID of the command:
9282 * * 0x0-0xFFF8 - The function ID
9283 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
9284 * * 0xFFFD - Reserved for user-space HWRM interface
9289 * A physical address pointer pointing to a host buffer that the
9290 * command's response data will be written. This can be either a host
9291 * physical address (HPA) or a guest physical address (GPA) and must
9292 * point to a physically contiguous block of memory.
9297 * This bit must be '1' for the vf_id field to be
9300 #define HWRM_FUNC_BUF_UNRGTR_INPUT_ENABLES_VF_ID UINT32_C(0x1)
9302 * This value is used to identify a Virtual Function (VF).
9303 * The scope of VF ID is local within a PF.
9306 uint8_t unused_0[2];
9307 } __attribute__((packed));
9309 /* hwrm_func_buf_unrgtr_output (size:128b/16B) */
9310 struct hwrm_func_buf_unrgtr_output {
9311 /* The specific error status for the command. */
9312 uint16_t error_code;
9313 /* The HWRM command request type. */
9315 /* The sequence ID from the original command. */
9317 /* The length of the response data in number of bytes. */
9319 uint8_t unused_0[7];
9321 * This field is used in Output records to indicate that the output
9322 * is completely written to RAM. This field should be read as '1'
9323 * to indicate that the output has been completely written.
9324 * When writing a command completion or response to an internal processor,
9325 * the order of writes has to be such that this field is written last.
9328 } __attribute__((packed));
9330 /**********************
9331 * hwrm_func_drv_qver *
9332 **********************/
9335 /* hwrm_func_drv_qver_input (size:192b/24B) */
9336 struct hwrm_func_drv_qver_input {
9337 /* The HWRM command request type. */
9340 * The completion ring to send the completion event on. This should
9341 * be the NQ ID returned from the `nq_alloc` HWRM command.
9345 * The sequence ID is used by the driver for tracking multiple
9346 * commands. This ID is treated as opaque data by the firmware and
9347 * the value is returned in the `hwrm_resp_hdr` upon completion.
9351 * The target ID of the command:
9352 * * 0x0-0xFFF8 - The function ID
9353 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
9354 * * 0xFFFD - Reserved for user-space HWRM interface
9359 * A physical address pointer pointing to a host buffer that the
9360 * command's response data will be written. This can be either a host
9361 * physical address (HPA) or a guest physical address (GPA) and must
9362 * point to a physically contiguous block of memory.
9365 /* Reserved for future use. */
9368 * Function ID of the function that is being queried.
9369 * 0xFF... (All Fs) if the query is for the requesting
9373 uint8_t unused_0[2];
9374 } __attribute__((packed));
9376 /* hwrm_func_drv_qver_output (size:256b/32B) */
9377 struct hwrm_func_drv_qver_output {
9378 /* The specific error status for the command. */
9379 uint16_t error_code;
9380 /* The HWRM command request type. */
9382 /* The sequence ID from the original command. */
9384 /* The length of the response data in number of bytes. */
9386 /* This value indicates the type of OS. The values are based on CIM_OperatingSystem.mof file as published by the DMTF. */
9389 #define HWRM_FUNC_DRV_QVER_OUTPUT_OS_TYPE_UNKNOWN UINT32_C(0x0)
9390 /* Other OS not listed below. */
9391 #define HWRM_FUNC_DRV_QVER_OUTPUT_OS_TYPE_OTHER UINT32_C(0x1)
9393 #define HWRM_FUNC_DRV_QVER_OUTPUT_OS_TYPE_MSDOS UINT32_C(0xe)
9395 #define HWRM_FUNC_DRV_QVER_OUTPUT_OS_TYPE_WINDOWS UINT32_C(0x12)
9397 #define HWRM_FUNC_DRV_QVER_OUTPUT_OS_TYPE_SOLARIS UINT32_C(0x1d)
9399 #define HWRM_FUNC_DRV_QVER_OUTPUT_OS_TYPE_LINUX UINT32_C(0x24)
9401 #define HWRM_FUNC_DRV_QVER_OUTPUT_OS_TYPE_FREEBSD UINT32_C(0x2a)
9402 /* VMware ESXi OS. */
9403 #define HWRM_FUNC_DRV_QVER_OUTPUT_OS_TYPE_ESXI UINT32_C(0x68)
9404 /* Microsoft Windows 8 64-bit OS. */
9405 #define HWRM_FUNC_DRV_QVER_OUTPUT_OS_TYPE_WIN864 UINT32_C(0x73)
9406 /* Microsoft Windows Server 2012 R2 OS. */
9407 #define HWRM_FUNC_DRV_QVER_OUTPUT_OS_TYPE_WIN2012R2 UINT32_C(0x74)
9409 #define HWRM_FUNC_DRV_QVER_OUTPUT_OS_TYPE_UEFI UINT32_C(0x8000)
9410 #define HWRM_FUNC_DRV_QVER_OUTPUT_OS_TYPE_LAST \
9411 HWRM_FUNC_DRV_QVER_OUTPUT_OS_TYPE_UEFI
9412 /* This is the 8bit major version of the driver. */
9414 /* This is the 8bit minor version of the driver. */
9416 /* This is the 8bit update version of the driver. */
9418 uint8_t unused_0[3];
9419 /* This is the 16bit major version of the driver. */
9421 /* This is the 16bit minor version of the driver. */
9423 /* This is the 16bit update version of the driver. */
9425 /* This is the 16bit patch version of the driver. */
9427 uint8_t unused_1[7];
9429 * This field is used in Output records to indicate that the output
9430 * is completely written to RAM. This field should be read as '1'
9431 * to indicate that the output has been completely written.
9432 * When writing a command completion or response to an internal processor,
9433 * the order of writes has to be such that this field is written last.
9436 } __attribute__((packed));
9438 /****************************
9439 * hwrm_func_resource_qcaps *
9440 ****************************/
9443 /* hwrm_func_resource_qcaps_input (size:192b/24B) */
9444 struct hwrm_func_resource_qcaps_input {
9445 /* The HWRM command request type. */
9448 * The completion ring to send the completion event on. This should
9449 * be the NQ ID returned from the `nq_alloc` HWRM command.
9453 * The sequence ID is used by the driver for tracking multiple
9454 * commands. This ID is treated as opaque data by the firmware and
9455 * the value is returned in the `hwrm_resp_hdr` upon completion.
9459 * The target ID of the command:
9460 * * 0x0-0xFFF8 - The function ID
9461 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
9462 * * 0xFFFD - Reserved for user-space HWRM interface
9467 * A physical address pointer pointing to a host buffer that the
9468 * command's response data will be written. This can be either a host
9469 * physical address (HPA) or a guest physical address (GPA) and must
9470 * point to a physically contiguous block of memory.
9474 * Function ID of the function that is being queried.
9475 * 0xFF... (All Fs) if the query is for the requesting
9479 uint8_t unused_0[6];
9480 } __attribute__((packed));
9482 /* hwrm_func_resource_qcaps_output (size:448b/56B) */
9483 struct hwrm_func_resource_qcaps_output {
9484 /* The specific error status for the command. */
9485 uint16_t error_code;
9486 /* The HWRM command request type. */
9488 /* The sequence ID from the original command. */
9490 /* The length of the response data in number of bytes. */
9492 /* Maximum guaranteed number of VFs supported by PF. Not applicable for VFs. */
9494 /* Maximum guaranteed number of MSI-X vectors supported by function */
9496 /* Hint of strategy to be used by PF driver to reserve resources for its VF */
9497 uint16_t vf_reservation_strategy;
9498 /* The PF driver should evenly divide its remaining resources among all VFs. */
9499 #define HWRM_FUNC_RESOURCE_QCAPS_OUTPUT_VF_RESERVATION_STRATEGY_MAXIMAL \
9501 /* The PF driver should only reserve minimal resources for each VF. */
9502 #define HWRM_FUNC_RESOURCE_QCAPS_OUTPUT_VF_RESERVATION_STRATEGY_MINIMAL \
9505 * The PF driver should not reserve any resources for each VF until the
9506 * the VF interface is brought up.
9508 #define HWRM_FUNC_RESOURCE_QCAPS_OUTPUT_VF_RESERVATION_STRATEGY_MINIMAL_STATIC \
9510 #define HWRM_FUNC_RESOURCE_QCAPS_OUTPUT_VF_RESERVATION_STRATEGY_LAST \
9511 HWRM_FUNC_RESOURCE_QCAPS_OUTPUT_VF_RESERVATION_STRATEGY_MINIMAL_STATIC
9512 /* Minimum guaranteed number of RSS/COS contexts */
9513 uint16_t min_rsscos_ctx;
9514 /* Maximum non-guaranteed number of RSS/COS contexts */
9515 uint16_t max_rsscos_ctx;
9516 /* Minimum guaranteed number of completion rings */
9517 uint16_t min_cmpl_rings;
9518 /* Maximum non-guaranteed number of completion rings */
9519 uint16_t max_cmpl_rings;
9520 /* Minimum guaranteed number of transmit rings */
9521 uint16_t min_tx_rings;
9522 /* Maximum non-guaranteed number of transmit rings */
9523 uint16_t max_tx_rings;
9524 /* Minimum guaranteed number of receive rings */
9525 uint16_t min_rx_rings;
9526 /* Maximum non-guaranteed number of receive rings */
9527 uint16_t max_rx_rings;
9528 /* Minimum guaranteed number of L2 contexts */
9529 uint16_t min_l2_ctxs;
9530 /* Maximum non-guaranteed number of L2 contexts */
9531 uint16_t max_l2_ctxs;
9532 /* Minimum guaranteed number of VNICs */
9534 /* Maximum non-guaranteed number of VNICs */
9536 /* Minimum guaranteed number of statistic contexts */
9537 uint16_t min_stat_ctx;
9538 /* Maximum non-guaranteed number of statistic contexts */
9539 uint16_t max_stat_ctx;
9540 /* Minimum guaranteed number of ring groups */
9541 uint16_t min_hw_ring_grps;
9542 /* Maximum non-guaranteed number of ring groups */
9543 uint16_t max_hw_ring_grps;
9545 * Maximum number of inputs into the transmit scheduler for this function.
9546 * The number of TX rings assigned to the function cannot exceed this value.
9548 uint16_t max_tx_scheduler_inputs;
9551 * When this bit is '1', it indicates that VF_RESOURCE_CFG supports
9552 * feature to reserve all minimum resources when minimum >= 1, otherwise
9555 #define HWRM_FUNC_RESOURCE_QCAPS_OUTPUT_FLAGS_MIN_GUARANTEED \
9557 uint8_t unused_0[5];
9559 * This field is used in Output records to indicate that the output
9560 * is completely written to RAM. This field should be read as '1'
9561 * to indicate that the output has been completely written.
9562 * When writing a command completion or response to an internal processor,
9563 * the order of writes has to be such that this field is written last.
9566 } __attribute__((packed));
9568 /*********************************
9569 * hwrm_func_backing_store_qcaps *
9570 *********************************/
9573 /* hwrm_func_backing_store_qcaps_input (size:128b/16B) */
9574 struct hwrm_func_backing_store_qcaps_input {
9575 /* The HWRM command request type. */
9578 * The completion ring to send the completion event on. This should
9579 * be the NQ ID returned from the `nq_alloc` HWRM command.
9583 * The sequence ID is used by the driver for tracking multiple
9584 * commands. This ID is treated as opaque data by the firmware and
9585 * the value is returned in the `hwrm_resp_hdr` upon completion.
9589 * The target ID of the command:
9590 * * 0x0-0xFFF8 - The function ID
9591 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
9592 * * 0xFFFD - Reserved for user-space HWRM interface
9597 * A physical address pointer pointing to a host buffer that the
9598 * command's response data will be written. This can be either a host
9599 * physical address (HPA) or a guest physical address (GPA) and must
9600 * point to a physically contiguous block of memory.
9603 } __attribute__((packed));
9605 /* hwrm_func_backing_store_qcaps_output (size:576b/72B) */
9606 struct hwrm_func_backing_store_qcaps_output {
9607 /* The specific error status for the command. */
9608 uint16_t error_code;
9609 /* The HWRM command request type. */
9611 /* The sequence ID from the original command. */
9613 /* The length of the response data in number of bytes. */
9615 /* Maximum number of QP context entries supported for this function. */
9616 uint32_t qp_max_entries;
9618 * Minimum number of QP context entries that are needed to be reserved
9619 * for QP1 for the PF and its VFs. PF drivers must allocate at least
9620 * this many QP context entries, even if RoCE will not be used.
9622 uint16_t qp_min_qp1_entries;
9623 /* Maximum number of QP context entries that can be used for L2. */
9624 uint16_t qp_max_l2_entries;
9625 /* Number of bytes that must be allocated for each context entry. */
9626 uint16_t qp_entry_size;
9627 /* Maximum number of SRQ context entries that can be used for L2. */
9628 uint16_t srq_max_l2_entries;
9629 /* Maximum number of SRQ context entries supported for this function. */
9630 uint32_t srq_max_entries;
9631 /* Number of bytes that must be allocated for each context entry. */
9632 uint16_t srq_entry_size;
9633 /* Maximum number of CQ context entries that can be used for L2. */
9634 uint16_t cq_max_l2_entries;
9635 /* Maximum number of CQ context entries supported for this function. */
9636 uint32_t cq_max_entries;
9637 /* Number of bytes that must be allocated for each context entry. */
9638 uint16_t cq_entry_size;
9639 /* Maximum number of VNIC context entries supported for this function. */
9640 uint16_t vnic_max_vnic_entries;
9641 /* Maximum number of Ring table context entries supported for this function. */
9642 uint16_t vnic_max_ring_table_entries;
9643 /* Number of bytes that must be allocated for each context entry. */
9644 uint16_t vnic_entry_size;
9645 /* Maximum number of statistic context entries supported for this function. */
9646 uint32_t stat_max_entries;
9647 /* Number of bytes that must be allocated for each context entry. */
9648 uint16_t stat_entry_size;
9649 /* Number of bytes that must be allocated for each context entry. */
9650 uint16_t tqm_entry_size;
9651 /* Minimum number of TQM context entries required per ring. */
9652 uint32_t tqm_min_entries_per_ring;
9654 * Maximum number of TQM context entries supported per ring. This is
9655 * actually a recommended TQM queue size based on worst case usage of
9658 * TQM fastpath rings should be sized large enough to accommodate the
9659 * maximum number of QPs (either L2 or RoCE, or both if shared)
9660 * that can be enqueued to the TQM ring.
9662 * TQM slowpath rings should be sized as follows:
9664 * num_entries = num_vnics + num_l2_tx_rings + num_roce_qps + tqm_min_size
9667 * num_vnics is the number of VNICs allocated in the VNIC backing store
9668 * num_l2_tx_rings is the number of L2 rings in the QP backing store
9669 * num_roce_qps is the number of RoCE QPs in the QP backing store
9670 * tqm_min_size is tqm_min_entries_per_ring reported by
9671 * HWRM_FUNC_BACKING_STORE_QCAPS
9673 * Note that TQM ring sizes cannot be extended while the system is
9674 * operational. If a PF driver needs to extend a TQM ring, it needs
9675 * to reset the function (e.g. HWRM_FUNC_RESET) and then reallocate
9676 * the backing store.
9678 uint32_t tqm_max_entries_per_ring;
9680 * Maximum number of MR plus AV context entries supported for this
9683 uint32_t mrav_max_entries;
9684 /* Number of bytes that must be allocated for each context entry. */
9685 uint16_t mrav_entry_size;
9686 /* Number of bytes that must be allocated for each context entry. */
9687 uint16_t tim_entry_size;
9688 /* Maximum number of Timer context entries supported for this function. */
9689 uint32_t tim_max_entries;
9691 * When this field is zero, the 32b `mrav_num_entries` field in the
9692 * `backing_store_cfg` and `backing_store_qcfg` commands represents
9693 * the total number of MR plus AV entries allowed in the MR/AV backing
9696 * When this field is non-zero, the 32b `mrav_num_entries` field in
9697 * the `backing_store_cfg` and `backing_store_qcfg` commands is
9698 * logically divided into two 16b fields. Bits `[31:16]` represents
9699 * the `mr_num_entries` and bits `[15:0]` represents `av_num_entries`.
9700 * Both of these values are represented in a unit granularity
9701 * specified by this field. For example, if this field is 16 and
9702 * `mrav_num_entries` is `0x02000100`, then the number of MR entries
9703 * is 8192 and the number of AV entries is 4096.
9705 uint16_t mrav_num_entries_units;
9707 * The number of entries specified for any TQM ring must be a
9708 * multiple of this value to prevent any resource allocation
9711 uint8_t tqm_entries_multiple;
9713 * This field is used in Output records to indicate that the output
9714 * is completely written to RAM. This field should be read as '1'
9715 * to indicate that the output has been completely written.
9716 * When writing a command completion or response to an internal processor,
9717 * the order of writes has to be such that this field is written last.
9720 } __attribute__((packed));
9722 /*******************************
9723 * hwrm_func_backing_store_cfg *
9724 *******************************/
9727 /* hwrm_func_backing_store_cfg_input (size:2048b/256B) */
9728 struct hwrm_func_backing_store_cfg_input {
9729 /* The HWRM command request type. */
9732 * The completion ring to send the completion event on. This should
9733 * be the NQ ID returned from the `nq_alloc` HWRM command.
9737 * The sequence ID is used by the driver for tracking multiple
9738 * commands. This ID is treated as opaque data by the firmware and
9739 * the value is returned in the `hwrm_resp_hdr` upon completion.
9743 * The target ID of the command:
9744 * * 0x0-0xFFF8 - The function ID
9745 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
9746 * * 0xFFFD - Reserved for user-space HWRM interface
9751 * A physical address pointer pointing to a host buffer that the
9752 * command's response data will be written. This can be either a host
9753 * physical address (HPA) or a guest physical address (GPA) and must
9754 * point to a physically contiguous block of memory.
9759 * When set, the firmware only uses on-chip resources and does not
9760 * expect any backing store to be provided by the host driver. This
9761 * mode provides minimal L2 functionality (e.g. limited L2 resources,
9764 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_FLAGS_PREBOOT_MODE \
9767 * When set, the 32b `mrav_num_entries` field is logically divided
9768 * into two 16b fields, `mr_num_entries` and `av_num_entries`.
9770 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_FLAGS_MRAV_RESERVATION_SPLIT \
9774 * This bit must be '1' for the qp fields to be
9777 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_QP \
9780 * This bit must be '1' for the srq fields to be
9783 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_SRQ \
9786 * This bit must be '1' for the cq fields to be
9789 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_CQ \
9792 * This bit must be '1' for the vnic fields to be
9795 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_VNIC \
9798 * This bit must be '1' for the stat fields to be
9801 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_STAT \
9804 * This bit must be '1' for the tqm_sp fields to be
9807 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_TQM_SP \
9810 * This bit must be '1' for the tqm_ring0 fields to be
9813 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_TQM_RING0 \
9816 * This bit must be '1' for the tqm_ring1 fields to be
9819 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_TQM_RING1 \
9822 * This bit must be '1' for the tqm_ring2 fields to be
9825 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_TQM_RING2 \
9828 * This bit must be '1' for the tqm_ring3 fields to be
9831 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_TQM_RING3 \
9834 * This bit must be '1' for the tqm_ring4 fields to be
9837 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_TQM_RING4 \
9840 * This bit must be '1' for the tqm_ring5 fields to be
9843 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_TQM_RING5 \
9846 * This bit must be '1' for the tqm_ring6 fields to be
9849 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_TQM_RING6 \
9852 * This bit must be '1' for the tqm_ring7 fields to be
9855 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_TQM_RING7 \
9858 * This bit must be '1' for the mrav fields to be
9861 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_MRAV \
9864 * This bit must be '1' for the tim fields to be
9867 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_TIM \
9869 /* QPC page size and level. */
9870 uint8_t qpc_pg_size_qpc_lvl;
9871 /* QPC PBL indirect levels. */
9872 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_QPC_LVL_MASK \
9874 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_QPC_LVL_SFT 0
9875 /* PBL pointer is physical start address. */
9876 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_QPC_LVL_LVL_0 \
9878 /* PBL pointer points to PTE table. */
9879 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_QPC_LVL_LVL_1 \
9881 /* PBL pointer points to PDE table with each entry pointing to PTE tables. */
9882 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_QPC_LVL_LVL_2 \
9884 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_QPC_LVL_LAST \
9885 HWRM_FUNC_BACKING_STORE_CFG_INPUT_QPC_LVL_LVL_2
9886 /* QPC page size. */
9887 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_QPC_PG_SIZE_MASK \
9889 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_QPC_PG_SIZE_SFT 4
9891 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_QPC_PG_SIZE_PG_4K \
9892 (UINT32_C(0x0) << 4)
9894 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_QPC_PG_SIZE_PG_8K \
9895 (UINT32_C(0x1) << 4)
9897 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_QPC_PG_SIZE_PG_64K \
9898 (UINT32_C(0x2) << 4)
9900 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_QPC_PG_SIZE_PG_2M \
9901 (UINT32_C(0x3) << 4)
9903 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_QPC_PG_SIZE_PG_8M \
9904 (UINT32_C(0x4) << 4)
9906 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_QPC_PG_SIZE_PG_1G \
9907 (UINT32_C(0x5) << 4)
9908 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_QPC_PG_SIZE_LAST \
9909 HWRM_FUNC_BACKING_STORE_CFG_INPUT_QPC_PG_SIZE_PG_1G
9910 /* SRQ page size and level. */
9911 uint8_t srq_pg_size_srq_lvl;
9912 /* SRQ PBL indirect levels. */
9913 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_SRQ_LVL_MASK \
9915 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_SRQ_LVL_SFT 0
9916 /* PBL pointer is physical start address. */
9917 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_SRQ_LVL_LVL_0 \
9919 /* PBL pointer points to PTE table. */
9920 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_SRQ_LVL_LVL_1 \
9922 /* PBL pointer points to PDE table with each entry pointing to PTE tables. */
9923 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_SRQ_LVL_LVL_2 \
9925 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_SRQ_LVL_LAST \
9926 HWRM_FUNC_BACKING_STORE_CFG_INPUT_SRQ_LVL_LVL_2
9927 /* SRQ page size. */
9928 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_SRQ_PG_SIZE_MASK \
9930 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_SRQ_PG_SIZE_SFT 4
9932 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_SRQ_PG_SIZE_PG_4K \
9933 (UINT32_C(0x0) << 4)
9935 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_SRQ_PG_SIZE_PG_8K \
9936 (UINT32_C(0x1) << 4)
9938 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_SRQ_PG_SIZE_PG_64K \
9939 (UINT32_C(0x2) << 4)
9941 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_SRQ_PG_SIZE_PG_2M \
9942 (UINT32_C(0x3) << 4)
9944 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_SRQ_PG_SIZE_PG_8M \
9945 (UINT32_C(0x4) << 4)
9947 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_SRQ_PG_SIZE_PG_1G \
9948 (UINT32_C(0x5) << 4)
9949 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_SRQ_PG_SIZE_LAST \
9950 HWRM_FUNC_BACKING_STORE_CFG_INPUT_SRQ_PG_SIZE_PG_1G
9951 /* CQ page size and level. */
9952 uint8_t cq_pg_size_cq_lvl;
9953 /* CQ PBL indirect levels. */
9954 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_CQ_LVL_MASK \
9956 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_CQ_LVL_SFT 0
9957 /* PBL pointer is physical start address. */
9958 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_CQ_LVL_LVL_0 \
9960 /* PBL pointer points to PTE table. */
9961 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_CQ_LVL_LVL_1 \
9963 /* PBL pointer points to PDE table with each entry pointing to PTE tables. */
9964 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_CQ_LVL_LVL_2 \
9966 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_CQ_LVL_LAST \
9967 HWRM_FUNC_BACKING_STORE_CFG_INPUT_CQ_LVL_LVL_2
9969 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_CQ_PG_SIZE_MASK \
9971 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_CQ_PG_SIZE_SFT 4
9973 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_CQ_PG_SIZE_PG_4K \
9974 (UINT32_C(0x0) << 4)
9976 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_CQ_PG_SIZE_PG_8K \
9977 (UINT32_C(0x1) << 4)
9979 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_CQ_PG_SIZE_PG_64K \
9980 (UINT32_C(0x2) << 4)
9982 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_CQ_PG_SIZE_PG_2M \
9983 (UINT32_C(0x3) << 4)
9985 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_CQ_PG_SIZE_PG_8M \
9986 (UINT32_C(0x4) << 4)
9988 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_CQ_PG_SIZE_PG_1G \
9989 (UINT32_C(0x5) << 4)
9990 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_CQ_PG_SIZE_LAST \
9991 HWRM_FUNC_BACKING_STORE_CFG_INPUT_CQ_PG_SIZE_PG_1G
9992 /* VNIC page size and level. */
9993 uint8_t vnic_pg_size_vnic_lvl;
9994 /* VNIC PBL indirect levels. */
9995 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_VNIC_LVL_MASK \
9997 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_VNIC_LVL_SFT 0
9998 /* PBL pointer is physical start address. */
9999 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_VNIC_LVL_LVL_0 \
10001 /* PBL pointer points to PTE table. */
10002 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_VNIC_LVL_LVL_1 \
10004 /* PBL pointer points to PDE table with each entry pointing to PTE tables. */
10005 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_VNIC_LVL_LVL_2 \
10007 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_VNIC_LVL_LAST \
10008 HWRM_FUNC_BACKING_STORE_CFG_INPUT_VNIC_LVL_LVL_2
10009 /* VNIC page size. */
10010 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_VNIC_PG_SIZE_MASK \
10012 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_VNIC_PG_SIZE_SFT 4
10014 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_VNIC_PG_SIZE_PG_4K \
10015 (UINT32_C(0x0) << 4)
10017 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_VNIC_PG_SIZE_PG_8K \
10018 (UINT32_C(0x1) << 4)
10020 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_VNIC_PG_SIZE_PG_64K \
10021 (UINT32_C(0x2) << 4)
10023 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_VNIC_PG_SIZE_PG_2M \
10024 (UINT32_C(0x3) << 4)
10026 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_VNIC_PG_SIZE_PG_8M \
10027 (UINT32_C(0x4) << 4)
10029 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_VNIC_PG_SIZE_PG_1G \
10030 (UINT32_C(0x5) << 4)
10031 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_VNIC_PG_SIZE_LAST \
10032 HWRM_FUNC_BACKING_STORE_CFG_INPUT_VNIC_PG_SIZE_PG_1G
10033 /* Stat page size and level. */
10034 uint8_t stat_pg_size_stat_lvl;
10035 /* Stat PBL indirect levels. */
10036 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_STAT_LVL_MASK \
10038 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_STAT_LVL_SFT 0
10039 /* PBL pointer is physical start address. */
10040 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_STAT_LVL_LVL_0 \
10042 /* PBL pointer points to PTE table. */
10043 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_STAT_LVL_LVL_1 \
10045 /* PBL pointer points to PDE table with each entry pointing to PTE tables. */
10046 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_STAT_LVL_LVL_2 \
10048 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_STAT_LVL_LAST \
10049 HWRM_FUNC_BACKING_STORE_CFG_INPUT_STAT_LVL_LVL_2
10050 /* Stat page size. */
10051 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_STAT_PG_SIZE_MASK \
10053 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_STAT_PG_SIZE_SFT 4
10055 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_STAT_PG_SIZE_PG_4K \
10056 (UINT32_C(0x0) << 4)
10058 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_STAT_PG_SIZE_PG_8K \
10059 (UINT32_C(0x1) << 4)
10061 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_STAT_PG_SIZE_PG_64K \
10062 (UINT32_C(0x2) << 4)
10064 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_STAT_PG_SIZE_PG_2M \
10065 (UINT32_C(0x3) << 4)
10067 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_STAT_PG_SIZE_PG_8M \
10068 (UINT32_C(0x4) << 4)
10070 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_STAT_PG_SIZE_PG_1G \
10071 (UINT32_C(0x5) << 4)
10072 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_STAT_PG_SIZE_LAST \
10073 HWRM_FUNC_BACKING_STORE_CFG_INPUT_STAT_PG_SIZE_PG_1G
10074 /* TQM slow path page size and level. */
10075 uint8_t tqm_sp_pg_size_tqm_sp_lvl;
10076 /* TQM slow path PBL indirect levels. */
10077 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_SP_LVL_MASK \
10079 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_SP_LVL_SFT 0
10080 /* PBL pointer is physical start address. */
10081 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_SP_LVL_LVL_0 \
10083 /* PBL pointer points to PTE table. */
10084 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_SP_LVL_LVL_1 \
10086 /* PBL pointer points to PDE table with each entry pointing to PTE tables. */
10087 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_SP_LVL_LVL_2 \
10089 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_SP_LVL_LAST \
10090 HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_SP_LVL_LVL_2
10091 /* TQM slow path page size. */
10092 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_SP_PG_SIZE_MASK \
10094 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_SP_PG_SIZE_SFT 4
10096 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_SP_PG_SIZE_PG_4K \
10097 (UINT32_C(0x0) << 4)
10099 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_SP_PG_SIZE_PG_8K \
10100 (UINT32_C(0x1) << 4)
10102 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_SP_PG_SIZE_PG_64K \
10103 (UINT32_C(0x2) << 4)
10105 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_SP_PG_SIZE_PG_2M \
10106 (UINT32_C(0x3) << 4)
10108 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_SP_PG_SIZE_PG_8M \
10109 (UINT32_C(0x4) << 4)
10111 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_SP_PG_SIZE_PG_1G \
10112 (UINT32_C(0x5) << 4)
10113 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_SP_PG_SIZE_LAST \
10114 HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_SP_PG_SIZE_PG_1G
10115 /* TQM ring 0 page size and level. */
10116 uint8_t tqm_ring0_pg_size_tqm_ring0_lvl;
10117 /* TQM ring 0 PBL indirect levels. */
10118 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING0_LVL_MASK \
10120 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING0_LVL_SFT 0
10121 /* PBL pointer is physical start address. */
10122 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING0_LVL_LVL_0 \
10124 /* PBL pointer points to PTE table. */
10125 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING0_LVL_LVL_1 \
10127 /* PBL pointer points to PDE table with each entry pointing to PTE tables. */
10128 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING0_LVL_LVL_2 \
10130 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING0_LVL_LAST \
10131 HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING0_LVL_LVL_2
10132 /* TQM ring 0 page size. */
10133 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING0_PG_SIZE_MASK \
10135 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING0_PG_SIZE_SFT 4
10137 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING0_PG_SIZE_PG_4K \
10138 (UINT32_C(0x0) << 4)
10140 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING0_PG_SIZE_PG_8K \
10141 (UINT32_C(0x1) << 4)
10143 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING0_PG_SIZE_PG_64K \
10144 (UINT32_C(0x2) << 4)
10146 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING0_PG_SIZE_PG_2M \
10147 (UINT32_C(0x3) << 4)
10149 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING0_PG_SIZE_PG_8M \
10150 (UINT32_C(0x4) << 4)
10152 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING0_PG_SIZE_PG_1G \
10153 (UINT32_C(0x5) << 4)
10154 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING0_PG_SIZE_LAST \
10155 HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING0_PG_SIZE_PG_1G
10156 /* TQM ring 1 page size and level. */
10157 uint8_t tqm_ring1_pg_size_tqm_ring1_lvl;
10158 /* TQM ring 1 PBL indirect levels. */
10159 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING1_LVL_MASK \
10161 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING1_LVL_SFT 0
10162 /* PBL pointer is physical start address. */
10163 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING1_LVL_LVL_0 \
10165 /* PBL pointer points to PTE table. */
10166 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING1_LVL_LVL_1 \
10168 /* PBL pointer points to PDE table with each entry pointing to PTE tables. */
10169 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING1_LVL_LVL_2 \
10171 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING1_LVL_LAST \
10172 HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING1_LVL_LVL_2
10173 /* TQM ring 1 page size. */
10174 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING1_PG_SIZE_MASK \
10176 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING1_PG_SIZE_SFT 4
10178 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING1_PG_SIZE_PG_4K \
10179 (UINT32_C(0x0) << 4)
10181 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING1_PG_SIZE_PG_8K \
10182 (UINT32_C(0x1) << 4)
10184 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING1_PG_SIZE_PG_64K \
10185 (UINT32_C(0x2) << 4)
10187 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING1_PG_SIZE_PG_2M \
10188 (UINT32_C(0x3) << 4)
10190 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING1_PG_SIZE_PG_8M \
10191 (UINT32_C(0x4) << 4)
10193 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING1_PG_SIZE_PG_1G \
10194 (UINT32_C(0x5) << 4)
10195 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING1_PG_SIZE_LAST \
10196 HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING1_PG_SIZE_PG_1G
10197 /* TQM ring 2 page size and level. */
10198 uint8_t tqm_ring2_pg_size_tqm_ring2_lvl;
10199 /* TQM ring 2 PBL indirect levels. */
10200 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING2_LVL_MASK \
10202 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING2_LVL_SFT 0
10203 /* PBL pointer is physical start address. */
10204 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING2_LVL_LVL_0 \
10206 /* PBL pointer points to PTE table. */
10207 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING2_LVL_LVL_1 \
10209 /* PBL pointer points to PDE table with each entry pointing to PTE tables. */
10210 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING2_LVL_LVL_2 \
10212 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING2_LVL_LAST \
10213 HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING2_LVL_LVL_2
10214 /* TQM ring 2 page size. */
10215 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING2_PG_SIZE_MASK \
10217 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING2_PG_SIZE_SFT 4
10219 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING2_PG_SIZE_PG_4K \
10220 (UINT32_C(0x0) << 4)
10222 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING2_PG_SIZE_PG_8K \
10223 (UINT32_C(0x1) << 4)
10225 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING2_PG_SIZE_PG_64K \
10226 (UINT32_C(0x2) << 4)
10228 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING2_PG_SIZE_PG_2M \
10229 (UINT32_C(0x3) << 4)
10231 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING2_PG_SIZE_PG_8M \
10232 (UINT32_C(0x4) << 4)
10234 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING2_PG_SIZE_PG_1G \
10235 (UINT32_C(0x5) << 4)
10236 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING2_PG_SIZE_LAST \
10237 HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING2_PG_SIZE_PG_1G
10238 /* TQM ring 3 page size and level. */
10239 uint8_t tqm_ring3_pg_size_tqm_ring3_lvl;
10240 /* TQM ring 3 PBL indirect levels. */
10241 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING3_LVL_MASK \
10243 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING3_LVL_SFT 0
10244 /* PBL pointer is physical start address. */
10245 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING3_LVL_LVL_0 \
10247 /* PBL pointer points to PTE table. */
10248 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING3_LVL_LVL_1 \
10250 /* PBL pointer points to PDE table with each entry pointing to PTE tables. */
10251 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING3_LVL_LVL_2 \
10253 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING3_LVL_LAST \
10254 HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING3_LVL_LVL_2
10255 /* TQM ring 3 page size. */
10256 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING3_PG_SIZE_MASK \
10258 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING3_PG_SIZE_SFT 4
10260 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING3_PG_SIZE_PG_4K \
10261 (UINT32_C(0x0) << 4)
10263 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING3_PG_SIZE_PG_8K \
10264 (UINT32_C(0x1) << 4)
10266 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING3_PG_SIZE_PG_64K \
10267 (UINT32_C(0x2) << 4)
10269 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING3_PG_SIZE_PG_2M \
10270 (UINT32_C(0x3) << 4)
10272 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING3_PG_SIZE_PG_8M \
10273 (UINT32_C(0x4) << 4)
10275 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING3_PG_SIZE_PG_1G \
10276 (UINT32_C(0x5) << 4)
10277 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING3_PG_SIZE_LAST \
10278 HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING3_PG_SIZE_PG_1G
10279 /* TQM ring 4 page size and level. */
10280 uint8_t tqm_ring4_pg_size_tqm_ring4_lvl;
10281 /* TQM ring 4 PBL indirect levels. */
10282 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING4_LVL_MASK \
10284 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING4_LVL_SFT 0
10285 /* PBL pointer is physical start address. */
10286 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING4_LVL_LVL_0 \
10288 /* PBL pointer points to PTE table. */
10289 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING4_LVL_LVL_1 \
10291 /* PBL pointer points to PDE table with each entry pointing to PTE tables. */
10292 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING4_LVL_LVL_2 \
10294 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING4_LVL_LAST \
10295 HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING4_LVL_LVL_2
10296 /* TQM ring 4 page size. */
10297 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING4_PG_SIZE_MASK \
10299 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING4_PG_SIZE_SFT 4
10301 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING4_PG_SIZE_PG_4K \
10302 (UINT32_C(0x0) << 4)
10304 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING4_PG_SIZE_PG_8K \
10305 (UINT32_C(0x1) << 4)
10307 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING4_PG_SIZE_PG_64K \
10308 (UINT32_C(0x2) << 4)
10310 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING4_PG_SIZE_PG_2M \
10311 (UINT32_C(0x3) << 4)
10313 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING4_PG_SIZE_PG_8M \
10314 (UINT32_C(0x4) << 4)
10316 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING4_PG_SIZE_PG_1G \
10317 (UINT32_C(0x5) << 4)
10318 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING4_PG_SIZE_LAST \
10319 HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING4_PG_SIZE_PG_1G
10320 /* TQM ring 5 page size and level. */
10321 uint8_t tqm_ring5_pg_size_tqm_ring5_lvl;
10322 /* TQM ring 5 PBL indirect levels. */
10323 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING5_LVL_MASK \
10325 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING5_LVL_SFT 0
10326 /* PBL pointer is physical start address. */
10327 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING5_LVL_LVL_0 \
10329 /* PBL pointer points to PTE table. */
10330 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING5_LVL_LVL_1 \
10332 /* PBL pointer points to PDE table with each entry pointing to PTE tables. */
10333 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING5_LVL_LVL_2 \
10335 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING5_LVL_LAST \
10336 HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING5_LVL_LVL_2
10337 /* TQM ring 5 page size. */
10338 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING5_PG_SIZE_MASK \
10340 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING5_PG_SIZE_SFT 4
10342 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING5_PG_SIZE_PG_4K \
10343 (UINT32_C(0x0) << 4)
10345 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING5_PG_SIZE_PG_8K \
10346 (UINT32_C(0x1) << 4)
10348 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING5_PG_SIZE_PG_64K \
10349 (UINT32_C(0x2) << 4)
10351 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING5_PG_SIZE_PG_2M \
10352 (UINT32_C(0x3) << 4)
10354 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING5_PG_SIZE_PG_8M \
10355 (UINT32_C(0x4) << 4)
10357 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING5_PG_SIZE_PG_1G \
10358 (UINT32_C(0x5) << 4)
10359 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING5_PG_SIZE_LAST \
10360 HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING5_PG_SIZE_PG_1G
10361 /* TQM ring 6 page size and level. */
10362 uint8_t tqm_ring6_pg_size_tqm_ring6_lvl;
10363 /* TQM ring 6 PBL indirect levels. */
10364 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING6_LVL_MASK \
10366 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING6_LVL_SFT 0
10367 /* PBL pointer is physical start address. */
10368 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING6_LVL_LVL_0 \
10370 /* PBL pointer points to PTE table. */
10371 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING6_LVL_LVL_1 \
10373 /* PBL pointer points to PDE table with each entry pointing to PTE tables. */
10374 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING6_LVL_LVL_2 \
10376 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING6_LVL_LAST \
10377 HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING6_LVL_LVL_2
10378 /* TQM ring 6 page size. */
10379 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING6_PG_SIZE_MASK \
10381 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING6_PG_SIZE_SFT 4
10383 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING6_PG_SIZE_PG_4K \
10384 (UINT32_C(0x0) << 4)
10386 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING6_PG_SIZE_PG_8K \
10387 (UINT32_C(0x1) << 4)
10389 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING6_PG_SIZE_PG_64K \
10390 (UINT32_C(0x2) << 4)
10392 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING6_PG_SIZE_PG_2M \
10393 (UINT32_C(0x3) << 4)
10395 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING6_PG_SIZE_PG_8M \
10396 (UINT32_C(0x4) << 4)
10398 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING6_PG_SIZE_PG_1G \
10399 (UINT32_C(0x5) << 4)
10400 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING6_PG_SIZE_LAST \
10401 HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING6_PG_SIZE_PG_1G
10402 /* TQM ring 7 page size and level. */
10403 uint8_t tqm_ring7_pg_size_tqm_ring7_lvl;
10404 /* TQM ring 7 PBL indirect levels. */
10405 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING7_LVL_MASK \
10407 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING7_LVL_SFT 0
10408 /* PBL pointer is physical start address. */
10409 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING7_LVL_LVL_0 \
10411 /* PBL pointer points to PTE table. */
10412 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING7_LVL_LVL_1 \
10414 /* PBL pointer points to PDE table with each entry pointing to PTE tables. */
10415 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING7_LVL_LVL_2 \
10417 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING7_LVL_LAST \
10418 HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING7_LVL_LVL_2
10419 /* TQM ring 7 page size. */
10420 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING7_PG_SIZE_MASK \
10422 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING7_PG_SIZE_SFT 4
10424 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING7_PG_SIZE_PG_4K \
10425 (UINT32_C(0x0) << 4)
10427 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING7_PG_SIZE_PG_8K \
10428 (UINT32_C(0x1) << 4)
10430 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING7_PG_SIZE_PG_64K \
10431 (UINT32_C(0x2) << 4)
10433 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING7_PG_SIZE_PG_2M \
10434 (UINT32_C(0x3) << 4)
10436 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING7_PG_SIZE_PG_8M \
10437 (UINT32_C(0x4) << 4)
10439 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING7_PG_SIZE_PG_1G \
10440 (UINT32_C(0x5) << 4)
10441 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING7_PG_SIZE_LAST \
10442 HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING7_PG_SIZE_PG_1G
10443 /* MR/AV page size and level. */
10444 uint8_t mrav_pg_size_mrav_lvl;
10445 /* MR/AV PBL indirect levels. */
10446 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_MRAV_LVL_MASK \
10448 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_MRAV_LVL_SFT 0
10449 /* PBL pointer is physical start address. */
10450 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_MRAV_LVL_LVL_0 \
10452 /* PBL pointer points to PTE table. */
10453 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_MRAV_LVL_LVL_1 \
10455 /* PBL pointer points to PDE table with each entry pointing to PTE tables. */
10456 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_MRAV_LVL_LVL_2 \
10458 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_MRAV_LVL_LAST \
10459 HWRM_FUNC_BACKING_STORE_CFG_INPUT_MRAV_LVL_LVL_2
10460 /* MR/AV page size. */
10461 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_MRAV_PG_SIZE_MASK \
10463 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_MRAV_PG_SIZE_SFT 4
10465 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_MRAV_PG_SIZE_PG_4K \
10466 (UINT32_C(0x0) << 4)
10468 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_MRAV_PG_SIZE_PG_8K \
10469 (UINT32_C(0x1) << 4)
10471 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_MRAV_PG_SIZE_PG_64K \
10472 (UINT32_C(0x2) << 4)
10474 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_MRAV_PG_SIZE_PG_2M \
10475 (UINT32_C(0x3) << 4)
10477 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_MRAV_PG_SIZE_PG_8M \
10478 (UINT32_C(0x4) << 4)
10480 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_MRAV_PG_SIZE_PG_1G \
10481 (UINT32_C(0x5) << 4)
10482 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_MRAV_PG_SIZE_LAST \
10483 HWRM_FUNC_BACKING_STORE_CFG_INPUT_MRAV_PG_SIZE_PG_1G
10484 /* Timer page size and level. */
10485 uint8_t tim_pg_size_tim_lvl;
10486 /* Timer PBL indirect levels. */
10487 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TIM_LVL_MASK \
10489 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TIM_LVL_SFT 0
10490 /* PBL pointer is physical start address. */
10491 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TIM_LVL_LVL_0 \
10493 /* PBL pointer points to PTE table. */
10494 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TIM_LVL_LVL_1 \
10496 /* PBL pointer points to PDE table with each entry pointing to PTE tables. */
10497 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TIM_LVL_LVL_2 \
10499 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TIM_LVL_LAST \
10500 HWRM_FUNC_BACKING_STORE_CFG_INPUT_TIM_LVL_LVL_2
10501 /* Timer page size. */
10502 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TIM_PG_SIZE_MASK \
10504 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TIM_PG_SIZE_SFT 4
10506 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TIM_PG_SIZE_PG_4K \
10507 (UINT32_C(0x0) << 4)
10509 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TIM_PG_SIZE_PG_8K \
10510 (UINT32_C(0x1) << 4)
10512 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TIM_PG_SIZE_PG_64K \
10513 (UINT32_C(0x2) << 4)
10515 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TIM_PG_SIZE_PG_2M \
10516 (UINT32_C(0x3) << 4)
10518 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TIM_PG_SIZE_PG_8M \
10519 (UINT32_C(0x4) << 4)
10521 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TIM_PG_SIZE_PG_1G \
10522 (UINT32_C(0x5) << 4)
10523 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TIM_PG_SIZE_LAST \
10524 HWRM_FUNC_BACKING_STORE_CFG_INPUT_TIM_PG_SIZE_PG_1G
10525 /* QP page directory. */
10526 uint64_t qpc_page_dir;
10527 /* SRQ page directory. */
10528 uint64_t srq_page_dir;
10529 /* CQ page directory. */
10530 uint64_t cq_page_dir;
10531 /* VNIC page directory. */
10532 uint64_t vnic_page_dir;
10533 /* Stat page directory. */
10534 uint64_t stat_page_dir;
10535 /* TQM slowpath page directory. */
10536 uint64_t tqm_sp_page_dir;
10537 /* TQM ring 0 page directory. */
10538 uint64_t tqm_ring0_page_dir;
10539 /* TQM ring 1 page directory. */
10540 uint64_t tqm_ring1_page_dir;
10541 /* TQM ring 2 page directory. */
10542 uint64_t tqm_ring2_page_dir;
10543 /* TQM ring 3 page directory. */
10544 uint64_t tqm_ring3_page_dir;
10545 /* TQM ring 4 page directory. */
10546 uint64_t tqm_ring4_page_dir;
10547 /* TQM ring 5 page directory. */
10548 uint64_t tqm_ring5_page_dir;
10549 /* TQM ring 6 page directory. */
10550 uint64_t tqm_ring6_page_dir;
10551 /* TQM ring 7 page directory. */
10552 uint64_t tqm_ring7_page_dir;
10553 /* MR/AV page directory. */
10554 uint64_t mrav_page_dir;
10555 /* Timer page directory. */
10556 uint64_t tim_page_dir;
10557 /* Number of QPs. */
10558 uint32_t qp_num_entries;
10559 /* Number of SRQs. */
10560 uint32_t srq_num_entries;
10561 /* Number of CQs. */
10562 uint32_t cq_num_entries;
10563 /* Number of Stats. */
10564 uint32_t stat_num_entries;
10566 * Number of TQM slowpath entries.
10568 * TQM slowpath rings should be sized as follows:
10570 * num_entries = num_vnics + num_l2_tx_rings + num_roce_qps + tqm_min_size
10573 * num_vnics is the number of VNICs allocated in the VNIC backing store
10574 * num_l2_tx_rings is the number of L2 rings in the QP backing store
10575 * num_roce_qps is the number of RoCE QPs in the QP backing store
10576 * tqm_min_size is tqm_min_entries_per_ring reported by
10577 * HWRM_FUNC_BACKING_STORE_QCAPS
10579 * Note that TQM ring sizes cannot be extended while the system is
10580 * operational. If a PF driver needs to extend a TQM ring, it needs
10581 * to reset the function (e.g. HWRM_FUNC_RESET) and then reallocate
10582 * the backing store.
10584 uint32_t tqm_sp_num_entries;
10586 * Number of TQM ring 0 entries.
10588 * TQM fastpath rings should be sized large enough to accommodate the
10589 * maximum number of QPs (either L2 or RoCE, or both if shared)
10590 * that can be enqueued to the TQM ring.
10592 * Note that TQM ring sizes cannot be extended while the system is
10593 * operational. If a PF driver needs to extend a TQM ring, it needs
10594 * to reset the function (e.g. HWRM_FUNC_RESET) and then reallocate
10595 * the backing store.
10597 uint32_t tqm_ring0_num_entries;
10599 * Number of TQM ring 1 entries.
10601 * TQM fastpath rings should be sized large enough to accommodate the
10602 * maximum number of QPs (either L2 or RoCE, or both if shared)
10603 * that can be enqueued to the TQM ring.
10605 * Note that TQM ring sizes cannot be extended while the system is
10606 * operational. If a PF driver needs to extend a TQM ring, it needs
10607 * to reset the function (e.g. HWRM_FUNC_RESET) and then reallocate
10608 * the backing store.
10610 uint32_t tqm_ring1_num_entries;
10612 * Number of TQM ring 2 entries.
10614 * TQM fastpath rings should be sized large enough to accommodate the
10615 * maximum number of QPs (either L2 or RoCE, or both if shared)
10616 * that can be enqueued to the TQM ring.
10618 * Note that TQM ring sizes cannot be extended while the system is
10619 * operational. If a PF driver needs to extend a TQM ring, it needs
10620 * to reset the function (e.g. HWRM_FUNC_RESET) and then reallocate
10621 * the backing store.
10623 uint32_t tqm_ring2_num_entries;
10625 * Number of TQM ring 3 entries.
10627 * TQM fastpath rings should be sized large enough to accommodate the
10628 * maximum number of QPs (either L2 or RoCE, or both if shared)
10629 * that can be enqueued to the TQM ring.
10631 * Note that TQM ring sizes cannot be extended while the system is
10632 * operational. If a PF driver needs to extend a TQM ring, it needs
10633 * to reset the function (e.g. HWRM_FUNC_RESET) and then reallocate
10634 * the backing store.
10636 uint32_t tqm_ring3_num_entries;
10638 * Number of TQM ring 4 entries.
10640 * TQM fastpath rings should be sized large enough to accommodate the
10641 * maximum number of QPs (either L2 or RoCE, or both if shared)
10642 * that can be enqueued to the TQM ring.
10644 * Note that TQM ring sizes cannot be extended while the system is
10645 * operational. If a PF driver needs to extend a TQM ring, it needs
10646 * to reset the function (e.g. HWRM_FUNC_RESET) and then reallocate
10647 * the backing store.
10649 uint32_t tqm_ring4_num_entries;
10651 * Number of TQM ring 5 entries.
10653 * TQM fastpath rings should be sized large enough to accommodate the
10654 * maximum number of QPs (either L2 or RoCE, or both if shared)
10655 * that can be enqueued to the TQM ring.
10657 * Note that TQM ring sizes cannot be extended while the system is
10658 * operational. If a PF driver needs to extend a TQM ring, it needs
10659 * to reset the function (e.g. HWRM_FUNC_RESET) and then reallocate
10660 * the backing store.
10662 uint32_t tqm_ring5_num_entries;
10664 * Number of TQM ring 6 entries.
10666 * TQM fastpath rings should be sized large enough to accommodate the
10667 * maximum number of QPs (either L2 or RoCE, or both if shared)
10668 * that can be enqueued to the TQM ring.
10670 * Note that TQM ring sizes cannot be extended while the system is
10671 * operational. If a PF driver needs to extend a TQM ring, it needs
10672 * to reset the function (e.g. HWRM_FUNC_RESET) and then reallocate
10673 * the backing store.
10675 uint32_t tqm_ring6_num_entries;
10677 * Number of TQM ring 7 entries.
10679 * TQM fastpath rings should be sized large enough to accommodate the
10680 * maximum number of QPs (either L2 or RoCE, or both if shared)
10681 * that can be enqueued to the TQM ring.
10683 * Note that TQM ring sizes cannot be extended while the system is
10684 * operational. If a PF driver needs to extend a TQM ring, it needs
10685 * to reset the function (e.g. HWRM_FUNC_RESET) and then reallocate
10686 * the backing store.
10688 uint32_t tqm_ring7_num_entries;
10690 * If the MR/AV split reservation flag is not set, then this field
10691 * represents the total number of MR plus AV entries. For versions
10692 * of firmware that support the split reservation, when it is not
10693 * specified half of the entries will be reserved for MRs and the
10694 * other half for AVs.
10696 * If the MR/AV split reservation flag is set, then this
10697 * field is logically divided into two 16b fields. Bits `[31:16]`
10698 * represents the `mr_num_entries` and bits `[15:0]` represents
10699 * `av_num_entries`. The granularity of these values is defined by
10700 * the `mrav_num_entries_unit` field returned by the
10701 * `backing_store_qcaps` command.
10703 uint32_t mrav_num_entries;
10704 /* Number of Timer entries. */
10705 uint32_t tim_num_entries;
10706 /* Number of entries to reserve for QP1 */
10707 uint16_t qp_num_qp1_entries;
10708 /* Number of entries to reserve for L2 */
10709 uint16_t qp_num_l2_entries;
10710 /* Number of bytes that have been allocated for each context entry. */
10711 uint16_t qp_entry_size;
10712 /* Number of entries to reserve for L2 */
10713 uint16_t srq_num_l2_entries;
10714 /* Number of bytes that have been allocated for each context entry. */
10715 uint16_t srq_entry_size;
10716 /* Number of entries to reserve for L2 */
10717 uint16_t cq_num_l2_entries;
10718 /* Number of bytes that have been allocated for each context entry. */
10719 uint16_t cq_entry_size;
10720 /* Number of entries to reserve for VNIC entries */
10721 uint16_t vnic_num_vnic_entries;
10722 /* Number of entries to reserve for Ring table entries */
10723 uint16_t vnic_num_ring_table_entries;
10724 /* Number of bytes that have been allocated for each context entry. */
10725 uint16_t vnic_entry_size;
10726 /* Number of bytes that have been allocated for each context entry. */
10727 uint16_t stat_entry_size;
10728 /* Number of bytes that have been allocated for each context entry. */
10729 uint16_t tqm_entry_size;
10730 /* Number of bytes that have been allocated for each context entry. */
10731 uint16_t mrav_entry_size;
10732 /* Number of bytes that have been allocated for each context entry. */
10733 uint16_t tim_entry_size;
10734 } __attribute__((packed));
10736 /* hwrm_func_backing_store_cfg_output (size:128b/16B) */
10737 struct hwrm_func_backing_store_cfg_output {
10738 /* The specific error status for the command. */
10739 uint16_t error_code;
10740 /* The HWRM command request type. */
10742 /* The sequence ID from the original command. */
10744 /* The length of the response data in number of bytes. */
10746 uint8_t unused_0[7];
10748 * This field is used in Output records to indicate that the output
10749 * is completely written to RAM. This field should be read as '1'
10750 * to indicate that the output has been completely written.
10751 * When writing a command completion or response to an internal processor,
10752 * the order of writes has to be such that this field is written last.
10755 } __attribute__((packed));
10757 /********************************
10758 * hwrm_func_backing_store_qcfg *
10759 ********************************/
10762 /* hwrm_func_backing_store_qcfg_input (size:128b/16B) */
10763 struct hwrm_func_backing_store_qcfg_input {
10764 /* The HWRM command request type. */
10767 * The completion ring to send the completion event on. This should
10768 * be the NQ ID returned from the `nq_alloc` HWRM command.
10770 uint16_t cmpl_ring;
10772 * The sequence ID is used by the driver for tracking multiple
10773 * commands. This ID is treated as opaque data by the firmware and
10774 * the value is returned in the `hwrm_resp_hdr` upon completion.
10778 * The target ID of the command:
10779 * * 0x0-0xFFF8 - The function ID
10780 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
10781 * * 0xFFFD - Reserved for user-space HWRM interface
10784 uint16_t target_id;
10786 * A physical address pointer pointing to a host buffer that the
10787 * command's response data will be written. This can be either a host
10788 * physical address (HPA) or a guest physical address (GPA) and must
10789 * point to a physically contiguous block of memory.
10791 uint64_t resp_addr;
10792 } __attribute__((packed));
10794 /* hwrm_func_backing_store_qcfg_output (size:1920b/240B) */
10795 struct hwrm_func_backing_store_qcfg_output {
10796 /* The specific error status for the command. */
10797 uint16_t error_code;
10798 /* The HWRM command request type. */
10800 /* The sequence ID from the original command. */
10802 /* The length of the response data in number of bytes. */
10806 * When set, the firmware only uses on-chip resources and does not
10807 * expect any backing store to be provided by the host driver. This
10808 * mode provides minimal L2 functionality (e.g. limited L2 resources,
10811 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_FLAGS_PREBOOT_MODE \
10814 * When set, the 32b `mrav_num_entries` field is logically divided
10815 * into two 16b fields, `mr_num_entries` and `av_num_entries`.
10817 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_FLAGS_MRAV_RESERVATION_SPLIT \
10819 uint8_t unused_0[4];
10821 * This bit must be '1' for the qp fields to be
10824 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_UNUSED_0_QP \
10827 * This bit must be '1' for the srq fields to be
10830 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_UNUSED_0_SRQ \
10833 * This bit must be '1' for the cq fields to be
10836 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_UNUSED_0_CQ \
10839 * This bit must be '1' for the vnic fields to be
10842 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_UNUSED_0_VNIC \
10845 * This bit must be '1' for the stat fields to be
10848 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_UNUSED_0_STAT \
10851 * This bit must be '1' for the tqm_sp fields to be
10854 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_UNUSED_0_TQM_SP \
10857 * This bit must be '1' for the tqm_ring0 fields to be
10860 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_UNUSED_0_TQM_RING0 \
10863 * This bit must be '1' for the tqm_ring1 fields to be
10866 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_UNUSED_0_TQM_RING1 \
10869 * This bit must be '1' for the tqm_ring2 fields to be
10872 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_UNUSED_0_TQM_RING2 \
10875 * This bit must be '1' for the tqm_ring3 fields to be
10878 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_UNUSED_0_TQM_RING3 \
10881 * This bit must be '1' for the tqm_ring4 fields to be
10884 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_UNUSED_0_TQM_RING4 \
10887 * This bit must be '1' for the tqm_ring5 fields to be
10890 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_UNUSED_0_TQM_RING5 \
10893 * This bit must be '1' for the tqm_ring6 fields to be
10896 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_UNUSED_0_TQM_RING6 \
10899 * This bit must be '1' for the tqm_ring7 fields to be
10902 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_UNUSED_0_TQM_RING7 \
10905 * This bit must be '1' for the mrav fields to be
10908 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_UNUSED_0_MRAV \
10911 * This bit must be '1' for the tim fields to be
10914 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_UNUSED_0_TIM \
10916 /* QPC page size and level. */
10917 uint8_t qpc_pg_size_qpc_lvl;
10918 /* QPC PBL indirect levels. */
10919 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_QPC_LVL_MASK \
10921 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_QPC_LVL_SFT 0
10922 /* PBL pointer is physical start address. */
10923 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_QPC_LVL_LVL_0 \
10925 /* PBL pointer points to PTE table. */
10926 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_QPC_LVL_LVL_1 \
10928 /* PBL pointer points to PDE table with each entry pointing to PTE tables. */
10929 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_QPC_LVL_LVL_2 \
10931 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_QPC_LVL_LAST \
10932 HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_QPC_LVL_LVL_2
10933 /* QPC page size. */
10934 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_QPC_PG_SIZE_MASK \
10936 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_QPC_PG_SIZE_SFT 4
10938 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_QPC_PG_SIZE_PG_4K \
10939 (UINT32_C(0x0) << 4)
10941 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_QPC_PG_SIZE_PG_8K \
10942 (UINT32_C(0x1) << 4)
10944 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_QPC_PG_SIZE_PG_64K \
10945 (UINT32_C(0x2) << 4)
10947 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_QPC_PG_SIZE_PG_2M \
10948 (UINT32_C(0x3) << 4)
10950 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_QPC_PG_SIZE_PG_8M \
10951 (UINT32_C(0x4) << 4)
10953 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_QPC_PG_SIZE_PG_1G \
10954 (UINT32_C(0x5) << 4)
10955 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_QPC_PG_SIZE_LAST \
10956 HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_QPC_PG_SIZE_PG_1G
10957 /* SRQ page size and level. */
10958 uint8_t srq_pg_size_srq_lvl;
10959 /* SRQ PBL indirect levels. */
10960 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_SRQ_LVL_MASK \
10962 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_SRQ_LVL_SFT 0
10963 /* PBL pointer is physical start address. */
10964 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_SRQ_LVL_LVL_0 \
10966 /* PBL pointer points to PTE table. */
10967 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_SRQ_LVL_LVL_1 \
10969 /* PBL pointer points to PDE table with each entry pointing to PTE tables. */
10970 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_SRQ_LVL_LVL_2 \
10972 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_SRQ_LVL_LAST \
10973 HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_SRQ_LVL_LVL_2
10974 /* SRQ page size. */
10975 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_SRQ_PG_SIZE_MASK \
10977 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_SRQ_PG_SIZE_SFT 4
10979 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_SRQ_PG_SIZE_PG_4K \
10980 (UINT32_C(0x0) << 4)
10982 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_SRQ_PG_SIZE_PG_8K \
10983 (UINT32_C(0x1) << 4)
10985 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_SRQ_PG_SIZE_PG_64K \
10986 (UINT32_C(0x2) << 4)
10988 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_SRQ_PG_SIZE_PG_2M \
10989 (UINT32_C(0x3) << 4)
10991 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_SRQ_PG_SIZE_PG_8M \
10992 (UINT32_C(0x4) << 4)
10994 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_SRQ_PG_SIZE_PG_1G \
10995 (UINT32_C(0x5) << 4)
10996 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_SRQ_PG_SIZE_LAST \
10997 HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_SRQ_PG_SIZE_PG_1G
10998 /* CQ page size and level. */
10999 uint8_t cq_pg_size_cq_lvl;
11000 /* CQ PBL indirect levels. */
11001 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_CQ_LVL_MASK \
11003 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_CQ_LVL_SFT 0
11004 /* PBL pointer is physical start address. */
11005 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_CQ_LVL_LVL_0 \
11007 /* PBL pointer points to PTE table. */
11008 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_CQ_LVL_LVL_1 \
11010 /* PBL pointer points to PDE table with each entry pointing to PTE tables. */
11011 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_CQ_LVL_LVL_2 \
11013 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_CQ_LVL_LAST \
11014 HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_CQ_LVL_LVL_2
11015 /* CQ page size. */
11016 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_CQ_PG_SIZE_MASK \
11018 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_CQ_PG_SIZE_SFT 4
11020 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_CQ_PG_SIZE_PG_4K \
11021 (UINT32_C(0x0) << 4)
11023 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_CQ_PG_SIZE_PG_8K \
11024 (UINT32_C(0x1) << 4)
11026 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_CQ_PG_SIZE_PG_64K \
11027 (UINT32_C(0x2) << 4)
11029 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_CQ_PG_SIZE_PG_2M \
11030 (UINT32_C(0x3) << 4)
11032 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_CQ_PG_SIZE_PG_8M \
11033 (UINT32_C(0x4) << 4)
11035 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_CQ_PG_SIZE_PG_1G \
11036 (UINT32_C(0x5) << 4)
11037 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_CQ_PG_SIZE_LAST \
11038 HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_CQ_PG_SIZE_PG_1G
11039 /* VNIC page size and level. */
11040 uint8_t vnic_pg_size_vnic_lvl;
11041 /* VNIC PBL indirect levels. */
11042 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_VNIC_LVL_MASK \
11044 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_VNIC_LVL_SFT 0
11045 /* PBL pointer is physical start address. */
11046 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_VNIC_LVL_LVL_0 \
11048 /* PBL pointer points to PTE table. */
11049 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_VNIC_LVL_LVL_1 \
11051 /* PBL pointer points to PDE table with each entry pointing to PTE tables. */
11052 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_VNIC_LVL_LVL_2 \
11054 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_VNIC_LVL_LAST \
11055 HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_VNIC_LVL_LVL_2
11056 /* VNIC page size. */
11057 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_VNIC_PG_SIZE_MASK \
11059 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_VNIC_PG_SIZE_SFT 4
11061 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_VNIC_PG_SIZE_PG_4K \
11062 (UINT32_C(0x0) << 4)
11064 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_VNIC_PG_SIZE_PG_8K \
11065 (UINT32_C(0x1) << 4)
11067 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_VNIC_PG_SIZE_PG_64K \
11068 (UINT32_C(0x2) << 4)
11070 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_VNIC_PG_SIZE_PG_2M \
11071 (UINT32_C(0x3) << 4)
11073 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_VNIC_PG_SIZE_PG_8M \
11074 (UINT32_C(0x4) << 4)
11076 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_VNIC_PG_SIZE_PG_1G \
11077 (UINT32_C(0x5) << 4)
11078 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_VNIC_PG_SIZE_LAST \
11079 HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_VNIC_PG_SIZE_PG_1G
11080 /* Stat page size and level. */
11081 uint8_t stat_pg_size_stat_lvl;
11082 /* Stat PBL indirect levels. */
11083 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_STAT_LVL_MASK \
11085 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_STAT_LVL_SFT 0
11086 /* PBL pointer is physical start address. */
11087 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_STAT_LVL_LVL_0 \
11089 /* PBL pointer points to PTE table. */
11090 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_STAT_LVL_LVL_1 \
11092 /* PBL pointer points to PDE table with each entry pointing to PTE tables. */
11093 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_STAT_LVL_LVL_2 \
11095 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_STAT_LVL_LAST \
11096 HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_STAT_LVL_LVL_2
11097 /* Stat page size. */
11098 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_STAT_PG_SIZE_MASK \
11100 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_STAT_PG_SIZE_SFT 4
11102 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_STAT_PG_SIZE_PG_4K \
11103 (UINT32_C(0x0) << 4)
11105 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_STAT_PG_SIZE_PG_8K \
11106 (UINT32_C(0x1) << 4)
11108 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_STAT_PG_SIZE_PG_64K \
11109 (UINT32_C(0x2) << 4)
11111 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_STAT_PG_SIZE_PG_2M \
11112 (UINT32_C(0x3) << 4)
11114 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_STAT_PG_SIZE_PG_8M \
11115 (UINT32_C(0x4) << 4)
11117 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_STAT_PG_SIZE_PG_1G \
11118 (UINT32_C(0x5) << 4)
11119 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_STAT_PG_SIZE_LAST \
11120 HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_STAT_PG_SIZE_PG_1G
11121 /* TQM slow path page size and level. */
11122 uint8_t tqm_sp_pg_size_tqm_sp_lvl;
11123 /* TQM slow path PBL indirect levels. */
11124 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_SP_LVL_MASK \
11126 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_SP_LVL_SFT 0
11127 /* PBL pointer is physical start address. */
11128 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_SP_LVL_LVL_0 \
11130 /* PBL pointer points to PTE table. */
11131 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_SP_LVL_LVL_1 \
11133 /* PBL pointer points to PDE table with each entry pointing to PTE tables. */
11134 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_SP_LVL_LVL_2 \
11136 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_SP_LVL_LAST \
11137 HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_SP_LVL_LVL_2
11138 /* TQM slow path page size. */
11139 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_SP_PG_SIZE_MASK \
11141 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_SP_PG_SIZE_SFT 4
11143 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_SP_PG_SIZE_PG_4K \
11144 (UINT32_C(0x0) << 4)
11146 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_SP_PG_SIZE_PG_8K \
11147 (UINT32_C(0x1) << 4)
11149 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_SP_PG_SIZE_PG_64K \
11150 (UINT32_C(0x2) << 4)
11152 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_SP_PG_SIZE_PG_2M \
11153 (UINT32_C(0x3) << 4)
11155 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_SP_PG_SIZE_PG_8M \
11156 (UINT32_C(0x4) << 4)
11158 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_SP_PG_SIZE_PG_1G \
11159 (UINT32_C(0x5) << 4)
11160 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_SP_PG_SIZE_LAST \
11161 HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_SP_PG_SIZE_PG_1G
11162 /* TQM ring 0 page size and level. */
11163 uint8_t tqm_ring0_pg_size_tqm_ring0_lvl;
11164 /* TQM ring 0 PBL indirect levels. */
11165 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING0_LVL_MASK \
11167 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING0_LVL_SFT 0
11168 /* PBL pointer is physical start address. */
11169 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING0_LVL_LVL_0 \
11171 /* PBL pointer points to PTE table. */
11172 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING0_LVL_LVL_1 \
11174 /* PBL pointer points to PDE table with each entry pointing to PTE tables. */
11175 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING0_LVL_LVL_2 \
11177 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING0_LVL_LAST \
11178 HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING0_LVL_LVL_2
11179 /* TQM ring 0 page size. */
11180 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING0_PG_SIZE_MASK \
11182 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING0_PG_SIZE_SFT 4
11184 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING0_PG_SIZE_PG_4K \
11185 (UINT32_C(0x0) << 4)
11187 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING0_PG_SIZE_PG_8K \
11188 (UINT32_C(0x1) << 4)
11190 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING0_PG_SIZE_PG_64K \
11191 (UINT32_C(0x2) << 4)
11193 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING0_PG_SIZE_PG_2M \
11194 (UINT32_C(0x3) << 4)
11196 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING0_PG_SIZE_PG_8M \
11197 (UINT32_C(0x4) << 4)
11199 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING0_PG_SIZE_PG_1G \
11200 (UINT32_C(0x5) << 4)
11201 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING0_PG_SIZE_LAST \
11202 HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING0_PG_SIZE_PG_1G
11203 /* TQM ring 1 page size and level. */
11204 uint8_t tqm_ring1_pg_size_tqm_ring1_lvl;
11205 /* TQM ring 1 PBL indirect levels. */
11206 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING1_LVL_MASK \
11208 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING1_LVL_SFT 0
11209 /* PBL pointer is physical start address. */
11210 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING1_LVL_LVL_0 \
11212 /* PBL pointer points to PTE table. */
11213 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING1_LVL_LVL_1 \
11215 /* PBL pointer points to PDE table with each entry pointing to PTE tables. */
11216 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING1_LVL_LVL_2 \
11218 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING1_LVL_LAST \
11219 HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING1_LVL_LVL_2
11220 /* TQM ring 1 page size. */
11221 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING1_PG_SIZE_MASK \
11223 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING1_PG_SIZE_SFT 4
11225 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING1_PG_SIZE_PG_4K \
11226 (UINT32_C(0x0) << 4)
11228 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING1_PG_SIZE_PG_8K \
11229 (UINT32_C(0x1) << 4)
11231 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING1_PG_SIZE_PG_64K \
11232 (UINT32_C(0x2) << 4)
11234 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING1_PG_SIZE_PG_2M \
11235 (UINT32_C(0x3) << 4)
11237 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING1_PG_SIZE_PG_8M \
11238 (UINT32_C(0x4) << 4)
11240 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING1_PG_SIZE_PG_1G \
11241 (UINT32_C(0x5) << 4)
11242 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING1_PG_SIZE_LAST \
11243 HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING1_PG_SIZE_PG_1G
11244 /* TQM ring 2 page size and level. */
11245 uint8_t tqm_ring2_pg_size_tqm_ring2_lvl;
11246 /* TQM ring 2 PBL indirect levels. */
11247 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING2_LVL_MASK \
11249 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING2_LVL_SFT 0
11250 /* PBL pointer is physical start address. */
11251 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING2_LVL_LVL_0 \
11253 /* PBL pointer points to PTE table. */
11254 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING2_LVL_LVL_1 \
11256 /* PBL pointer points to PDE table with each entry pointing to PTE tables. */
11257 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING2_LVL_LVL_2 \
11259 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING2_LVL_LAST \
11260 HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING2_LVL_LVL_2
11261 /* TQM ring 2 page size. */
11262 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING2_PG_SIZE_MASK \
11264 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING2_PG_SIZE_SFT 4
11266 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING2_PG_SIZE_PG_4K \
11267 (UINT32_C(0x0) << 4)
11269 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING2_PG_SIZE_PG_8K \
11270 (UINT32_C(0x1) << 4)
11272 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING2_PG_SIZE_PG_64K \
11273 (UINT32_C(0x2) << 4)
11275 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING2_PG_SIZE_PG_2M \
11276 (UINT32_C(0x3) << 4)
11278 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING2_PG_SIZE_PG_8M \
11279 (UINT32_C(0x4) << 4)
11281 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING2_PG_SIZE_PG_1G \
11282 (UINT32_C(0x5) << 4)
11283 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING2_PG_SIZE_LAST \
11284 HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING2_PG_SIZE_PG_1G
11285 /* TQM ring 3 page size and level. */
11286 uint8_t tqm_ring3_pg_size_tqm_ring3_lvl;
11287 /* TQM ring 3 PBL indirect levels. */
11288 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING3_LVL_MASK \
11290 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING3_LVL_SFT 0
11291 /* PBL pointer is physical start address. */
11292 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING3_LVL_LVL_0 \
11294 /* PBL pointer points to PTE table. */
11295 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING3_LVL_LVL_1 \
11297 /* PBL pointer points to PDE table with each entry pointing to PTE tables. */
11298 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING3_LVL_LVL_2 \
11300 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING3_LVL_LAST \
11301 HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING3_LVL_LVL_2
11302 /* TQM ring 3 page size. */
11303 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING3_PG_SIZE_MASK \
11305 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING3_PG_SIZE_SFT 4
11307 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING3_PG_SIZE_PG_4K \
11308 (UINT32_C(0x0) << 4)
11310 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING3_PG_SIZE_PG_8K \
11311 (UINT32_C(0x1) << 4)
11313 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING3_PG_SIZE_PG_64K \
11314 (UINT32_C(0x2) << 4)
11316 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING3_PG_SIZE_PG_2M \
11317 (UINT32_C(0x3) << 4)
11319 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING3_PG_SIZE_PG_8M \
11320 (UINT32_C(0x4) << 4)
11322 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING3_PG_SIZE_PG_1G \
11323 (UINT32_C(0x5) << 4)
11324 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING3_PG_SIZE_LAST \
11325 HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING3_PG_SIZE_PG_1G
11326 /* TQM ring 4 page size and level. */
11327 uint8_t tqm_ring4_pg_size_tqm_ring4_lvl;
11328 /* TQM ring 4 PBL indirect levels. */
11329 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING4_LVL_MASK \
11331 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING4_LVL_SFT 0
11332 /* PBL pointer is physical start address. */
11333 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING4_LVL_LVL_0 \
11335 /* PBL pointer points to PTE table. */
11336 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING4_LVL_LVL_1 \
11338 /* PBL pointer points to PDE table with each entry pointing to PTE tables. */
11339 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING4_LVL_LVL_2 \
11341 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING4_LVL_LAST \
11342 HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING4_LVL_LVL_2
11343 /* TQM ring 4 page size. */
11344 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING4_PG_SIZE_MASK \
11346 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING4_PG_SIZE_SFT 4
11348 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING4_PG_SIZE_PG_4K \
11349 (UINT32_C(0x0) << 4)
11351 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING4_PG_SIZE_PG_8K \
11352 (UINT32_C(0x1) << 4)
11354 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING4_PG_SIZE_PG_64K \
11355 (UINT32_C(0x2) << 4)
11357 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING4_PG_SIZE_PG_2M \
11358 (UINT32_C(0x3) << 4)
11360 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING4_PG_SIZE_PG_8M \
11361 (UINT32_C(0x4) << 4)
11363 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING4_PG_SIZE_PG_1G \
11364 (UINT32_C(0x5) << 4)
11365 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING4_PG_SIZE_LAST \
11366 HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING4_PG_SIZE_PG_1G
11367 /* TQM ring 5 page size and level. */
11368 uint8_t tqm_ring5_pg_size_tqm_ring5_lvl;
11369 /* TQM ring 5 PBL indirect levels. */
11370 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING5_LVL_MASK \
11372 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING5_LVL_SFT 0
11373 /* PBL pointer is physical start address. */
11374 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING5_LVL_LVL_0 \
11376 /* PBL pointer points to PTE table. */
11377 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING5_LVL_LVL_1 \
11379 /* PBL pointer points to PDE table with each entry pointing to PTE tables. */
11380 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING5_LVL_LVL_2 \
11382 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING5_LVL_LAST \
11383 HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING5_LVL_LVL_2
11384 /* TQM ring 5 page size. */
11385 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING5_PG_SIZE_MASK \
11387 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING5_PG_SIZE_SFT 4
11389 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING5_PG_SIZE_PG_4K \
11390 (UINT32_C(0x0) << 4)
11392 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING5_PG_SIZE_PG_8K \
11393 (UINT32_C(0x1) << 4)
11395 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING5_PG_SIZE_PG_64K \
11396 (UINT32_C(0x2) << 4)
11398 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING5_PG_SIZE_PG_2M \
11399 (UINT32_C(0x3) << 4)
11401 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING5_PG_SIZE_PG_8M \
11402 (UINT32_C(0x4) << 4)
11404 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING5_PG_SIZE_PG_1G \
11405 (UINT32_C(0x5) << 4)
11406 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING5_PG_SIZE_LAST \
11407 HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING5_PG_SIZE_PG_1G
11408 /* TQM ring 6 page size and level. */
11409 uint8_t tqm_ring6_pg_size_tqm_ring6_lvl;
11410 /* TQM ring 6 PBL indirect levels. */
11411 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING6_LVL_MASK \
11413 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING6_LVL_SFT 0
11414 /* PBL pointer is physical start address. */
11415 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING6_LVL_LVL_0 \
11417 /* PBL pointer points to PTE table. */
11418 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING6_LVL_LVL_1 \
11420 /* PBL pointer points to PDE table with each entry pointing to PTE tables. */
11421 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING6_LVL_LVL_2 \
11423 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING6_LVL_LAST \
11424 HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING6_LVL_LVL_2
11425 /* TQM ring 6 page size. */
11426 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING6_PG_SIZE_MASK \
11428 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING6_PG_SIZE_SFT 4
11430 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING6_PG_SIZE_PG_4K \
11431 (UINT32_C(0x0) << 4)
11433 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING6_PG_SIZE_PG_8K \
11434 (UINT32_C(0x1) << 4)
11436 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING6_PG_SIZE_PG_64K \
11437 (UINT32_C(0x2) << 4)
11439 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING6_PG_SIZE_PG_2M \
11440 (UINT32_C(0x3) << 4)
11442 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING6_PG_SIZE_PG_8M \
11443 (UINT32_C(0x4) << 4)
11445 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING6_PG_SIZE_PG_1G \
11446 (UINT32_C(0x5) << 4)
11447 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING6_PG_SIZE_LAST \
11448 HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING6_PG_SIZE_PG_1G
11449 /* TQM ring 7 page size and level. */
11450 uint8_t tqm_ring7_pg_size_tqm_ring7_lvl;
11451 /* TQM ring 7 PBL indirect levels. */
11452 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING7_LVL_MASK \
11454 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING7_LVL_SFT 0
11455 /* PBL pointer is physical start address. */
11456 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING7_LVL_LVL_0 \
11458 /* PBL pointer points to PTE table. */
11459 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING7_LVL_LVL_1 \
11461 /* PBL pointer points to PDE table with each entry pointing to PTE tables. */
11462 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING7_LVL_LVL_2 \
11464 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING7_LVL_LAST \
11465 HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING7_LVL_LVL_2
11466 /* TQM ring 7 page size. */
11467 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING7_PG_SIZE_MASK \
11469 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING7_PG_SIZE_SFT 4
11471 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING7_PG_SIZE_PG_4K \
11472 (UINT32_C(0x0) << 4)
11474 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING7_PG_SIZE_PG_8K \
11475 (UINT32_C(0x1) << 4)
11477 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING7_PG_SIZE_PG_64K \
11478 (UINT32_C(0x2) << 4)
11480 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING7_PG_SIZE_PG_2M \
11481 (UINT32_C(0x3) << 4)
11483 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING7_PG_SIZE_PG_8M \
11484 (UINT32_C(0x4) << 4)
11486 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING7_PG_SIZE_PG_1G \
11487 (UINT32_C(0x5) << 4)
11488 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING7_PG_SIZE_LAST \
11489 HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING7_PG_SIZE_PG_1G
11490 /* MR/AV page size and level. */
11491 uint8_t mrav_pg_size_mrav_lvl;
11492 /* MR/AV PBL indirect levels. */
11493 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_MRAV_LVL_MASK \
11495 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_MRAV_LVL_SFT 0
11496 /* PBL pointer is physical start address. */
11497 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_MRAV_LVL_LVL_0 \
11499 /* PBL pointer points to PTE table. */
11500 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_MRAV_LVL_LVL_1 \
11502 /* PBL pointer points to PDE table with each entry pointing to PTE tables. */
11503 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_MRAV_LVL_LVL_2 \
11505 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_MRAV_LVL_LAST \
11506 HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_MRAV_LVL_LVL_2
11507 /* MR/AV page size. */
11508 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_MRAV_PG_SIZE_MASK \
11510 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_MRAV_PG_SIZE_SFT 4
11512 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_MRAV_PG_SIZE_PG_4K \
11513 (UINT32_C(0x0) << 4)
11515 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_MRAV_PG_SIZE_PG_8K \
11516 (UINT32_C(0x1) << 4)
11518 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_MRAV_PG_SIZE_PG_64K \
11519 (UINT32_C(0x2) << 4)
11521 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_MRAV_PG_SIZE_PG_2M \
11522 (UINT32_C(0x3) << 4)
11524 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_MRAV_PG_SIZE_PG_8M \
11525 (UINT32_C(0x4) << 4)
11527 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_MRAV_PG_SIZE_PG_1G \
11528 (UINT32_C(0x5) << 4)
11529 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_MRAV_PG_SIZE_LAST \
11530 HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_MRAV_PG_SIZE_PG_1G
11531 /* Timer page size and level. */
11532 uint8_t tim_pg_size_tim_lvl;
11533 /* Timer PBL indirect levels. */
11534 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TIM_LVL_MASK \
11536 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TIM_LVL_SFT 0
11537 /* PBL pointer is physical start address. */
11538 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TIM_LVL_LVL_0 \
11540 /* PBL pointer points to PTE table. */
11541 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TIM_LVL_LVL_1 \
11543 /* PBL pointer points to PDE table with each entry pointing to PTE tables. */
11544 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TIM_LVL_LVL_2 \
11546 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TIM_LVL_LAST \
11547 HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TIM_LVL_LVL_2
11548 /* Timer page size. */
11549 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TIM_PG_SIZE_MASK \
11551 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TIM_PG_SIZE_SFT 4
11553 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TIM_PG_SIZE_PG_4K \
11554 (UINT32_C(0x0) << 4)
11556 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TIM_PG_SIZE_PG_8K \
11557 (UINT32_C(0x1) << 4)
11559 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TIM_PG_SIZE_PG_64K \
11560 (UINT32_C(0x2) << 4)
11562 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TIM_PG_SIZE_PG_2M \
11563 (UINT32_C(0x3) << 4)
11565 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TIM_PG_SIZE_PG_8M \
11566 (UINT32_C(0x4) << 4)
11568 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TIM_PG_SIZE_PG_1G \
11569 (UINT32_C(0x5) << 4)
11570 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TIM_PG_SIZE_LAST \
11571 HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TIM_PG_SIZE_PG_1G
11572 /* QP page directory. */
11573 uint64_t qpc_page_dir;
11574 /* SRQ page directory. */
11575 uint64_t srq_page_dir;
11576 /* CQ page directory. */
11577 uint64_t cq_page_dir;
11578 /* VNIC page directory. */
11579 uint64_t vnic_page_dir;
11580 /* Stat page directory. */
11581 uint64_t stat_page_dir;
11582 /* TQM slowpath page directory. */
11583 uint64_t tqm_sp_page_dir;
11584 /* TQM ring 0 page directory. */
11585 uint64_t tqm_ring0_page_dir;
11586 /* TQM ring 1 page directory. */
11587 uint64_t tqm_ring1_page_dir;
11588 /* TQM ring 2 page directory. */
11589 uint64_t tqm_ring2_page_dir;
11590 /* TQM ring 3 page directory. */
11591 uint64_t tqm_ring3_page_dir;
11592 /* TQM ring 4 page directory. */
11593 uint64_t tqm_ring4_page_dir;
11594 /* TQM ring 5 page directory. */
11595 uint64_t tqm_ring5_page_dir;
11596 /* TQM ring 6 page directory. */
11597 uint64_t tqm_ring6_page_dir;
11598 /* TQM ring 7 page directory. */
11599 uint64_t tqm_ring7_page_dir;
11600 /* MR/AV page directory. */
11601 uint64_t mrav_page_dir;
11602 /* Timer page directory. */
11603 uint64_t tim_page_dir;
11604 /* Number of entries to reserve for QP1 */
11605 uint16_t qp_num_qp1_entries;
11606 /* Number of entries to reserve for L2 */
11607 uint16_t qp_num_l2_entries;
11608 /* Number of QPs. */
11609 uint32_t qp_num_entries;
11610 /* Number of SRQs. */
11611 uint32_t srq_num_entries;
11612 /* Number of entries to reserve for L2 */
11613 uint16_t srq_num_l2_entries;
11614 /* Number of entries to reserve for L2 */
11615 uint16_t cq_num_l2_entries;
11616 /* Number of CQs. */
11617 uint32_t cq_num_entries;
11618 /* Number of entries to reserve for VNIC entries */
11619 uint16_t vnic_num_vnic_entries;
11620 /* Number of entries to reserve for Ring table entries */
11621 uint16_t vnic_num_ring_table_entries;
11622 /* Number of Stats. */
11623 uint32_t stat_num_entries;
11624 /* Number of TQM slowpath entries. */
11625 uint32_t tqm_sp_num_entries;
11626 /* Number of TQM ring 0 entries. */
11627 uint32_t tqm_ring0_num_entries;
11628 /* Number of TQM ring 1 entries. */
11629 uint32_t tqm_ring1_num_entries;
11630 /* Number of TQM ring 2 entries. */
11631 uint32_t tqm_ring2_num_entries;
11632 /* Number of TQM ring 3 entries. */
11633 uint32_t tqm_ring3_num_entries;
11634 /* Number of TQM ring 4 entries. */
11635 uint32_t tqm_ring4_num_entries;
11636 /* Number of TQM ring 5 entries. */
11637 uint32_t tqm_ring5_num_entries;
11638 /* Number of TQM ring 6 entries. */
11639 uint32_t tqm_ring6_num_entries;
11640 /* Number of TQM ring 7 entries. */
11641 uint32_t tqm_ring7_num_entries;
11643 * If the MR/AV split reservation flag is not set, then this field
11644 * represents the total number of MR plus AV entries. For versions
11645 * of firmware that support the split reservation, when it is not
11646 * specified half of the entries will be reserved for MRs and the
11647 * other half for AVs.
11649 * If the MR/AV split reservation flag is set, then this
11650 * field is logically divided into two 16b fields. Bits `[31:16]`
11651 * represents the `mr_num_entries` and bits `[15:0]` represents
11652 * `av_num_entries`. The granularity of these values is defined by
11653 * the `mrav_num_entries_unit` field returned by the
11654 * `backing_store_qcaps` command.
11656 uint32_t mrav_num_entries;
11657 /* Number of Timer entries. */
11658 uint32_t tim_num_entries;
11659 uint8_t unused_1[7];
11661 * This field is used in Output records to indicate that the output
11662 * is completely written to RAM. This field should be read as 1
11663 * to indicate that the output has been completely written.
11664 * When writing a command completion or response to an internal
11665 * processor, the order of writes has to be such that this field
11669 } __attribute__((packed));
11671 /****************************
11672 * hwrm_error_recovery_qcfg *
11673 ****************************/
11676 /* hwrm_error_recovery_qcfg_input (size:192b/24B) */
11677 struct hwrm_error_recovery_qcfg_input {
11678 /* The HWRM command request type. */
11681 * The completion ring to send the completion event on. This should
11682 * be the NQ ID returned from the `nq_alloc` HWRM command.
11684 uint16_t cmpl_ring;
11686 * The sequence ID is used by the driver for tracking multiple
11687 * commands. This ID is treated as opaque data by the firmware and
11688 * the value is returned in the `hwrm_resp_hdr` upon completion.
11692 * The target ID of the command:
11693 * * 0x0-0xFFF8 - The function ID
11694 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
11695 * * 0xFFFD - Reserved for user-space HWRM interface
11698 uint16_t target_id;
11700 * A physical address pointer pointing to a host buffer that the
11701 * command's response data will be written. This can be either a host
11702 * physical address (HPA) or a guest physical address (GPA) and must
11703 * point to a physically contiguous block of memory.
11705 uint64_t resp_addr;
11706 uint8_t unused_0[8];
11707 } __attribute__((packed));
11709 /* hwrm_error_recovery_qcfg_output (size:1664b/208B) */
11710 struct hwrm_error_recovery_qcfg_output {
11711 /* The specific error status for the command. */
11712 uint16_t error_code;
11713 /* The HWRM command request type. */
11715 /* The sequence ID from the original command. */
11717 /* The length of the response data in number of bytes. */
11721 * When this flag is set to 1, error recovery will be initiated
11722 * through master function driver.
11724 #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FLAGS_HOST UINT32_C(0x1)
11726 * When this flag is set to 1, error recovery will be performed
11727 * through Co processor.
11729 #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FLAGS_CO_CPU UINT32_C(0x2)
11731 * Driver Polling frequency. This value is in units of 100msec.
11732 * Typical value would be 10 to indicate 1sec.
11733 * Drivers can poll FW health status, Heartbeat, reset_counter with
11736 uint32_t driver_polling_freq;
11738 * This value is in units of 100msec.
11739 * Typical value would be 30 to indicate 3sec.
11740 * Master function wait period from detecting a fatal error to
11741 * initiating reset. In this time period Master PF expects every
11742 * active driver will detect fatal error.
11744 uint32_t master_func_wait_period;
11746 * This value is in units of 100msec.
11747 * Typical value would be 50 to indicate 5sec.
11748 * Normal function wait period from fatal error detection to
11749 * polling FW health status. In this time period, drivers should not
11750 * do any PCIe MMIO transaction and should not send any HWRM commands.
11752 uint32_t normal_func_wait_period;
11754 * This value is in units of 100msec.
11755 * Typical value would be 20 to indicate 2sec.
11756 * This field indicates that, master function wait period after chip
11757 * reset. After this time, master function should reinitialize with
11760 uint32_t master_func_wait_period_after_reset;
11762 * This value is in units of 100msec.
11763 * Typical value would be 60 to indicate 6sec.
11764 * This field is applicable to both master and normal functions.
11765 * Even after chip reset, if FW status not changed to ready,
11766 * then all the functions can poll for this much time and bailout.
11768 uint32_t max_bailout_time_after_reset;
11770 * FW health status register.
11771 * Lower 2 bits indicates address space location and upper 30 bits
11772 * indicates upper 30bits of the register address.
11773 * A value of 0xFFFF-FFFF indicates this register does not exist.
11775 uint32_t fw_health_status_reg;
11776 /* Lower 2 bits indicates address space location. */
11777 #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FW_HEALTH_STATUS_REG_ADDR_SPACE_MASK \
11779 #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FW_HEALTH_STATUS_REG_ADDR_SPACE_SFT \
11782 * If value is 0, this register is located in PCIe config space.
11783 * Drivers have to map appropriate window to access this
11786 #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FW_HEALTH_STATUS_REG_ADDR_SPACE_PCIE_CFG \
11789 * If value is 1, this register is located in GRC address space.
11790 * Drivers have to map appropriate window to access this
11793 #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FW_HEALTH_STATUS_REG_ADDR_SPACE_GRC \
11796 * If value is 2, this register is located in first BAR address
11797 * space. Drivers have to map appropriate window to access this
11800 #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FW_HEALTH_STATUS_REG_ADDR_SPACE_BAR0 \
11803 * If value is 3, this register is located in second BAR address
11804 * space. Drivers have to map appropriate window to access this
11805 * Drivers have to map appropriate window to access this
11808 #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FW_HEALTH_STATUS_REG_ADDR_SPACE_BAR1 \
11810 #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FW_HEALTH_STATUS_REG_ADDR_SPACE_LAST \
11811 HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FW_HEALTH_STATUS_REG_ADDR_SPACE_BAR1
11812 /* Upper 30bits of the register address. */
11813 #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FW_HEALTH_STATUS_REG_ADDR_MASK \
11814 UINT32_C(0xfffffffc)
11815 #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FW_HEALTH_STATUS_REG_ADDR_SFT \
11818 * FW HeartBeat register.
11819 * Lower 2 bits indicates address space location and upper 30 bits
11820 * indicates actual address.
11821 * A value of 0xFFFF-FFFF indicates this register does not exist.
11823 uint32_t fw_heartbeat_reg;
11824 /* Lower 2 bits indicates address space location. */
11825 #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FW_HEARTBEAT_REG_ADDR_SPACE_MASK \
11827 #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FW_HEARTBEAT_REG_ADDR_SPACE_SFT \
11830 * If value is 0, this register is located in PCIe config space.
11831 * Drivers have to map appropriate window to access this
11834 #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FW_HEARTBEAT_REG_ADDR_SPACE_PCIE_CFG \
11837 * If value is 1, this register is located in GRC address space.
11838 * Drivers have to map appropriate window to access this
11841 #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FW_HEARTBEAT_REG_ADDR_SPACE_GRC \
11844 * If value is 2, this register is located in first BAR address
11845 * space. Drivers have to map appropriate window to access this
11848 #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FW_HEARTBEAT_REG_ADDR_SPACE_BAR0 \
11851 * If value is 3, this register is located in second BAR address
11852 * space. Drivers have to map appropriate window to access this
11855 #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FW_HEARTBEAT_REG_ADDR_SPACE_BAR1 \
11857 #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FW_HEARTBEAT_REG_ADDR_SPACE_LAST \
11858 HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FW_HEARTBEAT_REG_ADDR_SPACE_BAR1
11859 /* Upper 30bits of the register address. */
11860 #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FW_HEARTBEAT_REG_ADDR_MASK \
11861 UINT32_C(0xfffffffc)
11862 #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FW_HEARTBEAT_REG_ADDR_SFT \
11865 * FW reset counter.
11866 * Lower 2 bits indicates address space location and upper 30 bits
11867 * indicates actual address.
11868 * A value of 0xFFFF-FFFF indicates this register does not exist.
11870 uint32_t fw_reset_cnt_reg;
11871 /* Lower 2 bits indicates address space location. */
11872 #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FW_RESET_CNT_REG_ADDR_SPACE_MASK \
11874 #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FW_RESET_CNT_REG_ADDR_SPACE_SFT \
11877 * If value is 0, this register is located in PCIe config space.
11878 * Drivers have to map appropriate window to access this
11881 #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FW_RESET_CNT_REG_ADDR_SPACE_PCIE_CFG \
11884 * If value is 1, this register is located in GRC address space.
11885 * Drivers have to map appropriate window to access this
11888 #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FW_RESET_CNT_REG_ADDR_SPACE_GRC \
11891 * If value is 2, this register is located in first BAR address
11892 * space. Drivers have to map appropriate window to access this
11895 #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FW_RESET_CNT_REG_ADDR_SPACE_BAR0 \
11898 * If value is 3, this register is located in second BAR address
11899 * space. Drivers have to map appropriate window to access this
11902 #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FW_RESET_CNT_REG_ADDR_SPACE_BAR1 \
11904 #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FW_RESET_CNT_REG_ADDR_SPACE_LAST \
11905 HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FW_RESET_CNT_REG_ADDR_SPACE_BAR1
11906 /* Upper 30bits of the register address. */
11907 #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FW_RESET_CNT_REG_ADDR_MASK \
11908 UINT32_C(0xfffffffc)
11909 #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FW_RESET_CNT_REG_ADDR_SFT \
11912 * Reset Inprogress Register address for PFs.
11913 * Lower 2 bits indicates address space location and upper 30 bits
11914 * indicates actual address.
11915 * A value of 0xFFFF-FFFF indicates this register does not exist.
11917 uint32_t reset_inprogress_reg;
11918 /* Lower 2 bits indicates address space location. */
11919 #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_RESET_INPROGRESS_REG_ADDR_SPACE_MASK \
11921 #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_RESET_INPROGRESS_REG_ADDR_SPACE_SFT \
11924 * If value is 0, this register is located in PCIe config space.
11925 * Drivers have to map appropriate window to access this
11928 #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_RESET_INPROGRESS_REG_ADDR_SPACE_PCIE_CFG \
11931 * If value is 1, this register is located in GRC address space.
11932 * Drivers have to map appropriate window to access this
11935 #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_RESET_INPROGRESS_REG_ADDR_SPACE_GRC \
11938 * If value is 2, this register is located in first BAR address
11939 * space. Drivers have to map appropriate window to access this
11942 #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_RESET_INPROGRESS_REG_ADDR_SPACE_BAR0 \
11945 * If value is 3, this register is located in second BAR address
11946 * space. Drivers have to map appropriate window to access this
11949 #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_RESET_INPROGRESS_REG_ADDR_SPACE_BAR1 \
11951 #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_RESET_INPROGRESS_REG_ADDR_SPACE_LAST \
11952 HWRM_ERROR_RECOVERY_QCFG_OUTPUT_RESET_INPROGRESS_REG_ADDR_SPACE_BAR1
11953 /* Upper 30bits of the register address. */
11954 #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_RESET_INPROGRESS_REG_ADDR_MASK \
11955 UINT32_C(0xfffffffc)
11956 #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_RESET_INPROGRESS_REG_ADDR_SFT \
11958 /* This field indicates the mask value for reset_inprogress_reg. */
11959 uint32_t reset_inprogress_reg_mask;
11960 uint8_t unused_0[3];
11962 * Array of registers and value count to reset the Chip
11963 * Each array count has reset_reg, reset_reg_val, delay_after_reset
11964 * in TLV format. Depending upon Chip type, number of reset registers
11965 * will vary. Drivers have to write reset_reg_val in the reset_reg
11966 * location in the same sequence in order to recover from a fatal
11969 uint8_t reg_array_cnt;
11972 * Lower 2 bits indicates address space location and upper 30 bits
11973 * indicates actual address.
11974 * A value of 0xFFFF-FFFF indicates this register does not exist.
11976 uint32_t reset_reg[16];
11977 /* Lower 2 bits indicates address space location. */
11978 #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_RESET_REG_ADDR_SPACE_MASK \
11980 #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_RESET_REG_ADDR_SPACE_SFT 0
11982 * If value is 0, this register is located in PCIe config space.
11983 * Drivers have to map appropriate window to access this
11986 #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_RESET_REG_ADDR_SPACE_PCIE_CFG \
11989 * If value is 1, this register is located in GRC address space.
11990 * Drivers have to map appropriate window to access this
11993 #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_RESET_REG_ADDR_SPACE_GRC \
11996 * If value is 2, this register is located in first BAR address
11997 * space. Drivers have to map appropriate window to access this
12000 #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_RESET_REG_ADDR_SPACE_BAR0 \
12003 * If value is 3, this register is located in second BAR address
12004 * space. Drivers have to map appropriate window to access this
12007 #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_RESET_REG_ADDR_SPACE_BAR1 \
12009 #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_RESET_REG_ADDR_SPACE_LAST \
12010 HWRM_ERROR_RECOVERY_QCFG_OUTPUT_RESET_REG_ADDR_SPACE_BAR1
12011 /* Upper 30bits of the register address. */
12012 #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_RESET_REG_ADDR_MASK \
12013 UINT32_C(0xfffffffc)
12014 #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_RESET_REG_ADDR_SFT 2
12015 /* Value to be written in reset_reg to reset the controller. */
12016 uint32_t reset_reg_val[16];
12018 * This value is in units of 1msec.
12019 * Typical value would be 10 to indicate 10msec.
12020 * Some of the operations like Core reset require delay before
12021 * accessing PCIE MMIO register space.
12022 * If this value is non-zero, drivers have to wait for
12023 * this much time after writing reset_reg_val in reset_reg.
12025 uint8_t delay_after_reset[16];
12026 uint8_t unused_1[7];
12028 * This field is used in Output records to indicate that the output
12029 * is completely written to RAM. This field should be read as '1'
12030 * to indicate that the output has been completely written.
12031 * When writing a command completion or response to an internal
12032 * processor, the order of writes has to be such that this field
12036 } __attribute__((packed));
12038 /***********************
12039 * hwrm_func_vlan_qcfg *
12040 ***********************/
12043 /* hwrm_func_vlan_qcfg_input (size:192b/24B) */
12044 struct hwrm_func_vlan_qcfg_input {
12045 /* The HWRM command request type. */
12048 * The completion ring to send the completion event on. This should
12049 * be the NQ ID returned from the `nq_alloc` HWRM command.
12051 uint16_t cmpl_ring;
12053 * The sequence ID is used by the driver for tracking multiple
12054 * commands. This ID is treated as opaque data by the firmware and
12055 * the value is returned in the `hwrm_resp_hdr` upon completion.
12059 * The target ID of the command:
12060 * * 0x0-0xFFF8 - The function ID
12061 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
12062 * * 0xFFFD - Reserved for user-space HWRM interface
12065 uint16_t target_id;
12067 * A physical address pointer pointing to a host buffer that the
12068 * command's response data will be written. This can be either a host
12069 * physical address (HPA) or a guest physical address (GPA) and must
12070 * point to a physically contiguous block of memory.
12072 uint64_t resp_addr;
12074 * Function ID of the function that is being
12076 * If set to 0xFF... (All Fs), then the configuration is
12077 * for the requesting function.
12080 uint8_t unused_0[6];
12081 } __attribute__((packed));
12083 /* hwrm_func_vlan_qcfg_output (size:320b/40B) */
12084 struct hwrm_func_vlan_qcfg_output {
12085 /* The specific error status for the command. */
12086 uint16_t error_code;
12087 /* The HWRM command request type. */
12089 /* The sequence ID from the original command. */
12091 /* The length of the response data in number of bytes. */
12094 /* S-TAG VLAN identifier configured for the function. */
12096 /* S-TAG PCP value configured for the function. */
12100 * S-TAG TPID value configured for the function. This field is specified in
12101 * network byte order.
12103 uint16_t stag_tpid;
12104 /* C-TAG VLAN identifier configured for the function. */
12106 /* C-TAG PCP value configured for the function. */
12110 * C-TAG TPID value configured for the function. This field is specified in
12111 * network byte order.
12113 uint16_t ctag_tpid;
12118 uint8_t unused_3[3];
12120 * This field is used in Output records to indicate that the output
12121 * is completely written to RAM. This field should be read as '1'
12122 * to indicate that the output has been completely written.
12123 * When writing a command completion or response to an internal processor,
12124 * the order of writes has to be such that this field is written last.
12127 } __attribute__((packed));
12129 /**********************
12130 * hwrm_func_vlan_cfg *
12131 **********************/
12134 /* hwrm_func_vlan_cfg_input (size:384b/48B) */
12135 struct hwrm_func_vlan_cfg_input {
12136 /* The HWRM command request type. */
12139 * The completion ring to send the completion event on. This should
12140 * be the NQ ID returned from the `nq_alloc` HWRM command.
12142 uint16_t cmpl_ring;
12144 * The sequence ID is used by the driver for tracking multiple
12145 * commands. This ID is treated as opaque data by the firmware and
12146 * the value is returned in the `hwrm_resp_hdr` upon completion.
12150 * The target ID of the command:
12151 * * 0x0-0xFFF8 - The function ID
12152 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
12153 * * 0xFFFD - Reserved for user-space HWRM interface
12156 uint16_t target_id;
12158 * A physical address pointer pointing to a host buffer that the
12159 * command's response data will be written. This can be either a host
12160 * physical address (HPA) or a guest physical address (GPA) and must
12161 * point to a physically contiguous block of memory.
12163 uint64_t resp_addr;
12165 * Function ID of the function that is being
12167 * If set to 0xFF... (All Fs), then the configuration is
12168 * for the requesting function.
12171 uint8_t unused_0[2];
12174 * This bit must be '1' for the stag_vid field to be
12177 #define HWRM_FUNC_VLAN_CFG_INPUT_ENABLES_STAG_VID UINT32_C(0x1)
12179 * This bit must be '1' for the ctag_vid field to be
12182 #define HWRM_FUNC_VLAN_CFG_INPUT_ENABLES_CTAG_VID UINT32_C(0x2)
12184 * This bit must be '1' for the stag_pcp field to be
12187 #define HWRM_FUNC_VLAN_CFG_INPUT_ENABLES_STAG_PCP UINT32_C(0x4)
12189 * This bit must be '1' for the ctag_pcp field to be
12192 #define HWRM_FUNC_VLAN_CFG_INPUT_ENABLES_CTAG_PCP UINT32_C(0x8)
12194 * This bit must be '1' for the stag_tpid field to be
12197 #define HWRM_FUNC_VLAN_CFG_INPUT_ENABLES_STAG_TPID UINT32_C(0x10)
12199 * This bit must be '1' for the ctag_tpid field to be
12202 #define HWRM_FUNC_VLAN_CFG_INPUT_ENABLES_CTAG_TPID UINT32_C(0x20)
12203 /* S-TAG VLAN identifier configured for the function. */
12205 /* S-TAG PCP value configured for the function. */
12209 * S-TAG TPID value configured for the function. This field is specified in
12210 * network byte order.
12212 uint16_t stag_tpid;
12213 /* C-TAG VLAN identifier configured for the function. */
12215 /* C-TAG PCP value configured for the function. */
12219 * C-TAG TPID value configured for the function. This field is specified in
12220 * network byte order.
12222 uint16_t ctag_tpid;
12227 uint8_t unused_3[4];
12228 } __attribute__((packed));
12230 /* hwrm_func_vlan_cfg_output (size:128b/16B) */
12231 struct hwrm_func_vlan_cfg_output {
12232 /* The specific error status for the command. */
12233 uint16_t error_code;
12234 /* The HWRM command request type. */
12236 /* The sequence ID from the original command. */
12238 /* The length of the response data in number of bytes. */
12240 uint8_t unused_0[7];
12242 * This field is used in Output records to indicate that the output
12243 * is completely written to RAM. This field should be read as '1'
12244 * to indicate that the output has been completely written.
12245 * When writing a command completion or response to an internal processor,
12246 * the order of writes has to be such that this field is written last.
12249 } __attribute__((packed));
12251 /*******************************
12252 * hwrm_func_vf_vnic_ids_query *
12253 *******************************/
12256 /* hwrm_func_vf_vnic_ids_query_input (size:256b/32B) */
12257 struct hwrm_func_vf_vnic_ids_query_input {
12258 /* The HWRM command request type. */
12261 * The completion ring to send the completion event on. This should
12262 * be the NQ ID returned from the `nq_alloc` HWRM command.
12264 uint16_t cmpl_ring;
12266 * The sequence ID is used by the driver for tracking multiple
12267 * commands. This ID is treated as opaque data by the firmware and
12268 * the value is returned in the `hwrm_resp_hdr` upon completion.
12272 * The target ID of the command:
12273 * * 0x0-0xFFF8 - The function ID
12274 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
12275 * * 0xFFFD - Reserved for user-space HWRM interface
12278 uint16_t target_id;
12280 * A physical address pointer pointing to a host buffer that the
12281 * command's response data will be written. This can be either a host
12282 * physical address (HPA) or a guest physical address (GPA) and must
12283 * point to a physically contiguous block of memory.
12285 uint64_t resp_addr;
12287 * This value is used to identify a Virtual Function (VF).
12288 * The scope of VF ID is local within a PF.
12291 uint8_t unused_0[2];
12292 /* Max number of vnic ids in vnic id table */
12293 uint32_t max_vnic_id_cnt;
12294 /* This is the address for VF VNIC ID table */
12295 uint64_t vnic_id_tbl_addr;
12296 } __attribute__((packed));
12298 /* hwrm_func_vf_vnic_ids_query_output (size:128b/16B) */
12299 struct hwrm_func_vf_vnic_ids_query_output {
12300 /* The specific error status for the command. */
12301 uint16_t error_code;
12302 /* The HWRM command request type. */
12304 /* The sequence ID from the original command. */
12306 /* The length of the response data in number of bytes. */
12309 * Actual number of vnic ids
12311 * Each VNIC ID is written as a 32-bit number.
12313 uint32_t vnic_id_cnt;
12314 uint8_t unused_0[3];
12316 * This field is used in Output records to indicate that the output
12317 * is completely written to RAM. This field should be read as '1'
12318 * to indicate that the output has been completely written.
12319 * When writing a command completion or response to an internal processor,
12320 * the order of writes has to be such that this field is written last.
12323 } __attribute__((packed));
12325 /***********************
12326 * hwrm_func_vf_bw_cfg *
12327 ***********************/
12330 /* hwrm_func_vf_bw_cfg_input (size:960b/120B) */
12331 struct hwrm_func_vf_bw_cfg_input {
12332 /* The HWRM command request type. */
12335 * The completion ring to send the completion event on. This should
12336 * be the NQ ID returned from the `nq_alloc` HWRM command.
12338 uint16_t cmpl_ring;
12340 * The sequence ID is used by the driver for tracking multiple
12341 * commands. This ID is treated as opaque data by the firmware and
12342 * the value is returned in the `hwrm_resp_hdr` upon completion.
12346 * The target ID of the command:
12347 * * 0x0-0xFFF8 - The function ID
12348 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
12349 * * 0xFFFD - Reserved for user-space HWRM interface
12352 uint16_t target_id;
12354 * A physical address pointer pointing to a host buffer that the
12355 * command's response data will be written. This can be either a host
12356 * physical address (HPA) or a guest physical address (GPA) and must
12357 * point to a physically contiguous block of memory.
12359 uint64_t resp_addr;
12361 * The number of VF functions that are being configured.
12362 * The cmd space allows up to 50 VFs' BW to be configured with one cmd.
12365 uint16_t unused[3];
12366 /* These 16-bit fields contain the VF fid and the rate scale percentage. */
12368 /* The physical VF id the adjustment will be made to. */
12369 #define HWRM_FUNC_VF_BW_CFG_INPUT_VFN_VFID_MASK UINT32_C(0xfff)
12370 #define HWRM_FUNC_VF_BW_CFG_INPUT_VFN_VFID_SFT 0
12372 * This field configures the rate scale percentage of the VF as specified
12373 * by the physical VF id.
12375 #define HWRM_FUNC_VF_BW_CFG_INPUT_VFN_RATE_MASK UINT32_C(0xf000)
12376 #define HWRM_FUNC_VF_BW_CFG_INPUT_VFN_RATE_SFT 12
12377 /* 0% of the max tx rate */
12378 #define HWRM_FUNC_VF_BW_CFG_INPUT_VFN_RATE_PCT_0 \
12379 (UINT32_C(0x0) << 12)
12380 /* 6.66% of the max tx rate */
12381 #define HWRM_FUNC_VF_BW_CFG_INPUT_VFN_RATE_PCT_6_66 \
12382 (UINT32_C(0x1) << 12)
12383 /* 13.33% of the max tx rate */
12384 #define HWRM_FUNC_VF_BW_CFG_INPUT_VFN_RATE_PCT_13_33 \
12385 (UINT32_C(0x2) << 12)
12386 /* 20% of the max tx rate */
12387 #define HWRM_FUNC_VF_BW_CFG_INPUT_VFN_RATE_PCT_20 \
12388 (UINT32_C(0x3) << 12)
12389 /* 26.66% of the max tx rate */
12390 #define HWRM_FUNC_VF_BW_CFG_INPUT_VFN_RATE_PCT_26_66 \
12391 (UINT32_C(0x4) << 12)
12392 /* 33% of the max tx rate */
12393 #define HWRM_FUNC_VF_BW_CFG_INPUT_VFN_RATE_PCT_33_33 \
12394 (UINT32_C(0x5) << 12)
12395 /* 40% of the max tx rate */
12396 #define HWRM_FUNC_VF_BW_CFG_INPUT_VFN_RATE_PCT_40 \
12397 (UINT32_C(0x6) << 12)
12398 /* 46.66% of the max tx rate */
12399 #define HWRM_FUNC_VF_BW_CFG_INPUT_VFN_RATE_PCT_46_66 \
12400 (UINT32_C(0x7) << 12)
12401 /* 53.33% of the max tx rate */
12402 #define HWRM_FUNC_VF_BW_CFG_INPUT_VFN_RATE_PCT_53_33 \
12403 (UINT32_C(0x8) << 12)
12404 /* 60% of the max tx rate */
12405 #define HWRM_FUNC_VF_BW_CFG_INPUT_VFN_RATE_PCT_60 \
12406 (UINT32_C(0x9) << 12)
12407 /* 66.66% of the max tx rate */
12408 #define HWRM_FUNC_VF_BW_CFG_INPUT_VFN_RATE_PCT_66_66 \
12409 (UINT32_C(0xa) << 12)
12410 /* 53.33% of the max tx rate */
12411 #define HWRM_FUNC_VF_BW_CFG_INPUT_VFN_RATE_PCT_73_33 \
12412 (UINT32_C(0xb) << 12)
12413 /* 80% of the max tx rate */
12414 #define HWRM_FUNC_VF_BW_CFG_INPUT_VFN_RATE_PCT_80 \
12415 (UINT32_C(0xc) << 12)
12416 /* 86.66% of the max tx rate */
12417 #define HWRM_FUNC_VF_BW_CFG_INPUT_VFN_RATE_PCT_86_66 \
12418 (UINT32_C(0xd) << 12)
12419 /* 93.33% of the max tx rate */
12420 #define HWRM_FUNC_VF_BW_CFG_INPUT_VFN_RATE_PCT_93_33 \
12421 (UINT32_C(0xe) << 12)
12422 /* 100% of the max tx rate */
12423 #define HWRM_FUNC_VF_BW_CFG_INPUT_VFN_RATE_PCT_100 \
12424 (UINT32_C(0xf) << 12)
12425 #define HWRM_FUNC_VF_BW_CFG_INPUT_VFN_RATE_LAST \
12426 HWRM_FUNC_VF_BW_CFG_INPUT_VFN_RATE_PCT_100
12427 } __attribute__((packed));
12429 /* hwrm_func_vf_bw_cfg_output (size:128b/16B) */
12430 struct hwrm_func_vf_bw_cfg_output {
12431 /* The specific error status for the command. */
12432 uint16_t error_code;
12433 /* The HWRM command request type. */
12435 /* The sequence ID from the original command. */
12437 /* The length of the response data in number of bytes. */
12439 uint8_t unused_0[7];
12441 * This field is used in Output records to indicate that the output
12442 * is completely written to RAM. This field should be read as '1'
12443 * to indicate that the output has been completely written.
12444 * When writing a command completion or response to an internal processor,
12445 * the order of writes has to be such that this field is written last.
12448 } __attribute__((packed));
12450 /************************
12451 * hwrm_func_vf_bw_qcfg *
12452 ************************/
12455 /* hwrm_func_vf_bw_qcfg_input (size:960b/120B) */
12456 struct hwrm_func_vf_bw_qcfg_input {
12457 /* The HWRM command request type. */
12460 * The completion ring to send the completion event on. This should
12461 * be the NQ ID returned from the `nq_alloc` HWRM command.
12463 uint16_t cmpl_ring;
12465 * The sequence ID is used by the driver for tracking multiple
12466 * commands. This ID is treated as opaque data by the firmware and
12467 * the value is returned in the `hwrm_resp_hdr` upon completion.
12471 * The target ID of the command:
12472 * * 0x0-0xFFF8 - The function ID
12473 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
12474 * * 0xFFFD - Reserved for user-space HWRM interface
12477 uint16_t target_id;
12479 * A physical address pointer pointing to a host buffer that the
12480 * command's response data will be written. This can be either a host
12481 * physical address (HPA) or a guest physical address (GPA) and must
12482 * point to a physically contiguous block of memory.
12484 uint64_t resp_addr;
12486 * The number of VF functions that are being queried.
12487 * The inline response space allows the host to query up to 50 VFs'
12488 * rate scale percentage
12491 uint16_t unused[3];
12492 /* These 16-bit fields contain the VF fid */
12494 /* The physical VF id of interest */
12495 #define HWRM_FUNC_VF_BW_QCFG_INPUT_VFN_VFID_MASK UINT32_C(0xfff)
12496 #define HWRM_FUNC_VF_BW_QCFG_INPUT_VFN_VFID_SFT 0
12497 } __attribute__((packed));
12499 /* hwrm_func_vf_bw_qcfg_output (size:960b/120B) */
12500 struct hwrm_func_vf_bw_qcfg_output {
12501 /* The specific error status for the command. */
12502 uint16_t error_code;
12503 /* The HWRM command request type. */
12505 /* The sequence ID from the original command. */
12507 /* The length of the response data in number of bytes. */
12510 * The number of VF functions that are being queried.
12511 * The inline response space allows the host to query up to 50 VFs' rate
12515 uint16_t unused[3];
12516 /* These 16-bit fields contain the VF fid and the rate scale percentage. */
12518 /* The physical VF id the adjustment will be made to. */
12519 #define HWRM_FUNC_VF_BW_QCFG_OUTPUT_VFN_VFID_MASK UINT32_C(0xfff)
12520 #define HWRM_FUNC_VF_BW_QCFG_OUTPUT_VFN_VFID_SFT 0
12522 * This field configures the rate scale percentage of the VF as specified
12523 * by the physical VF id.
12525 #define HWRM_FUNC_VF_BW_QCFG_OUTPUT_VFN_RATE_MASK UINT32_C(0xf000)
12526 #define HWRM_FUNC_VF_BW_QCFG_OUTPUT_VFN_RATE_SFT 12
12527 /* 0% of the max tx rate */
12528 #define HWRM_FUNC_VF_BW_QCFG_OUTPUT_VFN_RATE_PCT_0 \
12529 (UINT32_C(0x0) << 12)
12530 /* 6.66% of the max tx rate */
12531 #define HWRM_FUNC_VF_BW_QCFG_OUTPUT_VFN_RATE_PCT_6_66 \
12532 (UINT32_C(0x1) << 12)
12533 /* 13.33% of the max tx rate */
12534 #define HWRM_FUNC_VF_BW_QCFG_OUTPUT_VFN_RATE_PCT_13_33 \
12535 (UINT32_C(0x2) << 12)
12536 /* 20% of the max tx rate */
12537 #define HWRM_FUNC_VF_BW_QCFG_OUTPUT_VFN_RATE_PCT_20 \
12538 (UINT32_C(0x3) << 12)
12539 /* 26.66% of the max tx rate */
12540 #define HWRM_FUNC_VF_BW_QCFG_OUTPUT_VFN_RATE_PCT_26_66 \
12541 (UINT32_C(0x4) << 12)
12542 /* 33% of the max tx rate */
12543 #define HWRM_FUNC_VF_BW_QCFG_OUTPUT_VFN_RATE_PCT_33_33 \
12544 (UINT32_C(0x5) << 12)
12545 /* 40% of the max tx rate */
12546 #define HWRM_FUNC_VF_BW_QCFG_OUTPUT_VFN_RATE_PCT_40 \
12547 (UINT32_C(0x6) << 12)
12548 /* 46.66% of the max tx rate */
12549 #define HWRM_FUNC_VF_BW_QCFG_OUTPUT_VFN_RATE_PCT_46_66 \
12550 (UINT32_C(0x7) << 12)
12551 /* 53.33% of the max tx rate */
12552 #define HWRM_FUNC_VF_BW_QCFG_OUTPUT_VFN_RATE_PCT_53_33 \
12553 (UINT32_C(0x8) << 12)
12554 /* 60% of the max tx rate */
12555 #define HWRM_FUNC_VF_BW_QCFG_OUTPUT_VFN_RATE_PCT_60 \
12556 (UINT32_C(0x9) << 12)
12557 /* 66.66% of the max tx rate */
12558 #define HWRM_FUNC_VF_BW_QCFG_OUTPUT_VFN_RATE_PCT_66_66 \
12559 (UINT32_C(0xa) << 12)
12560 /* 53.33% of the max tx rate */
12561 #define HWRM_FUNC_VF_BW_QCFG_OUTPUT_VFN_RATE_PCT_73_33 \
12562 (UINT32_C(0xb) << 12)
12563 /* 80% of the max tx rate */
12564 #define HWRM_FUNC_VF_BW_QCFG_OUTPUT_VFN_RATE_PCT_80 \
12565 (UINT32_C(0xc) << 12)
12566 /* 86.66% of the max tx rate */
12567 #define HWRM_FUNC_VF_BW_QCFG_OUTPUT_VFN_RATE_PCT_86_66 \
12568 (UINT32_C(0xd) << 12)
12569 /* 93.33% of the max tx rate */
12570 #define HWRM_FUNC_VF_BW_QCFG_OUTPUT_VFN_RATE_PCT_93_33 \
12571 (UINT32_C(0xe) << 12)
12572 /* 100% of the max tx rate */
12573 #define HWRM_FUNC_VF_BW_QCFG_OUTPUT_VFN_RATE_PCT_100 \
12574 (UINT32_C(0xf) << 12)
12575 #define HWRM_FUNC_VF_BW_QCFG_OUTPUT_VFN_RATE_LAST \
12576 HWRM_FUNC_VF_BW_QCFG_OUTPUT_VFN_RATE_PCT_100
12577 uint8_t unused_0[7];
12579 * This field is used in Output records to indicate that the output
12580 * is completely written to RAM. This field should be read as '1'
12581 * to indicate that the output has been completely written.
12582 * When writing a command completion or response to an internal processor,
12583 * the order of writes has to be such that this field is written last.
12586 } __attribute__((packed));
12588 /***************************
12589 * hwrm_func_drv_if_change *
12590 ***************************/
12593 /* hwrm_func_drv_if_change_input (size:192b/24B) */
12594 struct hwrm_func_drv_if_change_input {
12595 /* The HWRM command request type. */
12598 * The completion ring to send the completion event on. This should
12599 * be the NQ ID returned from the `nq_alloc` HWRM command.
12601 uint16_t cmpl_ring;
12603 * The sequence ID is used by the driver for tracking multiple
12604 * commands. This ID is treated as opaque data by the firmware and
12605 * the value is returned in the `hwrm_resp_hdr` upon completion.
12609 * The target ID of the command:
12610 * * 0x0-0xFFF8 - The function ID
12611 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
12612 * * 0xFFFD - Reserved for user-space HWRM interface
12615 uint16_t target_id;
12617 * A physical address pointer pointing to a host buffer that the
12618 * command's response data will be written. This can be either a host
12619 * physical address (HPA) or a guest physical address (GPA) and must
12620 * point to a physically contiguous block of memory.
12622 uint64_t resp_addr;
12625 * When this bit is '1', the function driver is indicating
12626 * that the IF state is changing to UP state. The call should
12627 * be made at the beginning of the driver's open call before
12628 * resources are allocated. After making the call, the driver
12629 * should check the response to see if any resources may have
12630 * changed (see the response below). If the driver fails
12631 * the open call, the driver should make this call again with
12632 * this bit cleared to indicate that the IF state is not UP.
12633 * During the driver's close call when the IF state is changing
12634 * to DOWN, the driver should make this call with the bit cleared
12635 * after all resources have been freed.
12637 #define HWRM_FUNC_DRV_IF_CHANGE_INPUT_FLAGS_UP UINT32_C(0x1)
12639 } __attribute__((packed));
12641 /* hwrm_func_drv_if_change_output (size:128b/16B) */
12642 struct hwrm_func_drv_if_change_output {
12643 /* The specific error status for the command. */
12644 uint16_t error_code;
12645 /* The HWRM command request type. */
12647 /* The sequence ID from the original command. */
12649 /* The length of the response data in number of bytes. */
12653 * When this bit is '1', it indicates that the resources reserved
12654 * for this function may have changed. The driver should check
12655 * resource capabilities and reserve resources again before
12656 * allocating resources.
12658 #define HWRM_FUNC_DRV_IF_CHANGE_OUTPUT_FLAGS_RESC_CHANGE \
12661 * When this bit is '1', it indicates that the firmware got changed / reset.
12662 * The driver should do complete re-initialization when that bit is set.
12664 #define HWRM_FUNC_DRV_IF_CHANGE_OUTPUT_FLAGS_HOT_FW_RESET_DONE \
12666 uint8_t unused_0[3];
12668 * This field is used in Output records to indicate that the output
12669 * is completely written to RAM. This field should be read as '1'
12670 * to indicate that the output has been completely written.
12671 * When writing a command completion or response to an internal processor,
12672 * the order of writes has to be such that this field is written last.
12675 } __attribute__((packed));
12677 /*******************************
12678 * hwrm_func_host_pf_ids_query *
12679 *******************************/
12682 /* hwrm_func_host_pf_ids_query_input (size:192b/24B) */
12683 struct hwrm_func_host_pf_ids_query_input {
12684 /* The HWRM command request type. */
12687 * The completion ring to send the completion event on. This should
12688 * be the NQ ID returned from the `nq_alloc` HWRM command.
12690 uint16_t cmpl_ring;
12692 * The sequence ID is used by the driver for tracking multiple
12693 * commands. This ID is treated as opaque data by the firmware and
12694 * the value is returned in the `hwrm_resp_hdr` upon completion.
12698 * The target ID of the command:
12699 * * 0x0-0xFFF8 - The function ID
12700 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
12701 * * 0xFFFD - Reserved for user-space HWRM interface
12704 uint16_t target_id;
12706 * A physical address pointer pointing to a host buffer that the
12707 * command's response data will be written. This can be either a host
12708 * physical address (HPA) or a guest physical address (GPA) and must
12709 * point to a physically contiguous block of memory.
12711 uint64_t resp_addr;
12714 * # If this bit is set to '1', the query will contain PF(s)
12715 * belongs to SOC host.
12717 #define HWRM_FUNC_HOST_PF_IDS_QUERY_INPUT_HOST_SOC UINT32_C(0x1)
12719 * # If this bit is set to '1', the query will contain PF(s)
12720 * belongs to EP0 host.
12722 #define HWRM_FUNC_HOST_PF_IDS_QUERY_INPUT_HOST_EP_0 UINT32_C(0x2)
12724 * # If this bit is set to '1', the query will contain PF(s)
12725 * belongs to EP1 host.
12727 #define HWRM_FUNC_HOST_PF_IDS_QUERY_INPUT_HOST_EP_1 UINT32_C(0x4)
12729 * # If this bit is set to '1', the query will contain PF(s)
12730 * belongs to EP2 host.
12732 #define HWRM_FUNC_HOST_PF_IDS_QUERY_INPUT_HOST_EP_2 UINT32_C(0x8)
12734 * # If this bit is set to '1', the query will contain PF(s)
12735 * belongs to EP3 host.
12737 #define HWRM_FUNC_HOST_PF_IDS_QUERY_INPUT_HOST_EP_3 UINT32_C(0x10)
12739 * This provides a filter of what PF(s) will be returned in the
12744 * all available PF(s) belong to the host(s) (defined in the
12745 * host field). This includes the hidden PFs.
12747 #define HWRM_FUNC_HOST_PF_IDS_QUERY_INPUT_FILTER_ALL UINT32_C(0x0)
12749 * all available PF(s) belong to the host(s) (defined in the
12750 * host field) that is available for L2 traffic.
12752 #define HWRM_FUNC_HOST_PF_IDS_QUERY_INPUT_FILTER_L2 UINT32_C(0x1)
12754 * all available PF(s) belong to the host(s) (defined in the
12755 * host field) that is available for ROCE traffic.
12757 #define HWRM_FUNC_HOST_PF_IDS_QUERY_INPUT_FILTER_ROCE UINT32_C(0x2)
12758 #define HWRM_FUNC_HOST_PF_IDS_QUERY_INPUT_FILTER_LAST \
12759 HWRM_FUNC_HOST_PF_IDS_QUERY_INPUT_FILTER_ROCE
12760 uint8_t unused_1[6];
12761 } __attribute__((packed));
12763 /* hwrm_func_host_pf_ids_query_output (size:128b/16B) */
12764 struct hwrm_func_host_pf_ids_query_output {
12765 /* The specific error status for the command. */
12766 uint16_t error_code;
12767 /* The HWRM command request type. */
12769 /* The sequence ID from the original command. */
12771 /* The length of the response data in number of bytes. */
12773 /* This provides the first PF ID of the device. */
12774 uint16_t first_pf_id;
12775 uint16_t pf_ordinal_mask;
12777 * When this bit is '1', it indicates first PF belongs to one of
12778 * the hosts defined in the input request.
12780 #define HWRM_FUNC_HOST_PF_IDS_QUERY_OUTPUT_PF_ORDINAL_MASK_FUNC_0 \
12783 * When this bit is '1', it indicates 2nd PF belongs to one of the
12784 * hosts defined in the input request.
12786 #define HWRM_FUNC_HOST_PF_IDS_QUERY_OUTPUT_PF_ORDINAL_MASK_FUNC_1 \
12789 * When this bit is '1', it indicates 3rd PF belongs to one of the
12790 * hosts defined in the input request.
12792 #define HWRM_FUNC_HOST_PF_IDS_QUERY_OUTPUT_PF_ORDINAL_MASK_FUNC_2 \
12795 * When this bit is '1', it indicates 4th PF belongs to one of the
12796 * hosts defined in the input request.
12798 #define HWRM_FUNC_HOST_PF_IDS_QUERY_OUTPUT_PF_ORDINAL_MASK_FUNC_3 \
12801 * When this bit is '1', it indicates 5th PF belongs to one of the
12802 * hosts defined in the input request.
12804 #define HWRM_FUNC_HOST_PF_IDS_QUERY_OUTPUT_PF_ORDINAL_MASK_FUNC_4 \
12807 * When this bit is '1', it indicates 6th PF belongs to one of the
12808 * hosts defined in the input request.
12810 #define HWRM_FUNC_HOST_PF_IDS_QUERY_OUTPUT_PF_ORDINAL_MASK_FUNC_5 \
12813 * When this bit is '1', it indicates 7th PF belongs to one of the
12814 * hosts defined in the input request.
12816 #define HWRM_FUNC_HOST_PF_IDS_QUERY_OUTPUT_PF_ORDINAL_MASK_FUNC_6 \
12819 * When this bit is '1', it indicates 8th PF belongs to one of the
12820 * hosts defined in the input request.
12822 #define HWRM_FUNC_HOST_PF_IDS_QUERY_OUTPUT_PF_ORDINAL_MASK_FUNC_7 \
12825 * When this bit is '1', it indicates 9th PF belongs to one of the
12826 * hosts defined in the input request.
12828 #define HWRM_FUNC_HOST_PF_IDS_QUERY_OUTPUT_PF_ORDINAL_MASK_FUNC_8 \
12831 * When this bit is '1', it indicates 10th PF belongs to one of the
12832 * hosts defined in the input request.
12834 #define HWRM_FUNC_HOST_PF_IDS_QUERY_OUTPUT_PF_ORDINAL_MASK_FUNC_9 \
12837 * When this bit is '1', it indicates 11th PF belongs to one of the
12838 * hosts defined in the input request.
12840 #define HWRM_FUNC_HOST_PF_IDS_QUERY_OUTPUT_PF_ORDINAL_MASK_FUNC_10 \
12843 * When this bit is '1', it indicates 12th PF belongs to one of the
12844 * hosts defined in the input request.
12846 #define HWRM_FUNC_HOST_PF_IDS_QUERY_OUTPUT_PF_ORDINAL_MASK_FUNC_11 \
12849 * When this bit is '1', it indicates 13th PF belongs to one of the
12850 * hosts defined in the input request.
12852 #define HWRM_FUNC_HOST_PF_IDS_QUERY_OUTPUT_PF_ORDINAL_MASK_FUNC_12 \
12855 * When this bit is '1', it indicates 14th PF belongs to one of the
12856 * hosts defined in the input request.
12858 #define HWRM_FUNC_HOST_PF_IDS_QUERY_OUTPUT_PF_ORDINAL_MASK_FUNC_13 \
12861 * When this bit is '1', it indicates 15th PF belongs to one of the
12862 * hosts defined in the input request.
12864 #define HWRM_FUNC_HOST_PF_IDS_QUERY_OUTPUT_PF_ORDINAL_MASK_FUNC_14 \
12867 * When this bit is '1', it indicates 16th PF belongs to one of the
12868 * hosts defined in the input request.
12870 #define HWRM_FUNC_HOST_PF_IDS_QUERY_OUTPUT_PF_ORDINAL_MASK_FUNC_15 \
12872 uint8_t unused_1[3];
12874 * This field is used in Output records to indicate that the output
12875 * is completely written to RAM. This field should be read as '1'
12876 * to indicate that the output has been completely written.
12877 * When writing a command completion or response to an internal processor,
12878 * the order of writes has to be such that this field is written last.
12881 } __attribute__((packed));
12883 /*********************
12884 * hwrm_port_phy_cfg *
12885 *********************/
12888 /* hwrm_port_phy_cfg_input (size:448b/56B) */
12889 struct hwrm_port_phy_cfg_input {
12890 /* The HWRM command request type. */
12893 * The completion ring to send the completion event on. This should
12894 * be the NQ ID returned from the `nq_alloc` HWRM command.
12896 uint16_t cmpl_ring;
12898 * The sequence ID is used by the driver for tracking multiple
12899 * commands. This ID is treated as opaque data by the firmware and
12900 * the value is returned in the `hwrm_resp_hdr` upon completion.
12904 * The target ID of the command:
12905 * * 0x0-0xFFF8 - The function ID
12906 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
12907 * * 0xFFFD - Reserved for user-space HWRM interface
12910 uint16_t target_id;
12912 * A physical address pointer pointing to a host buffer that the
12913 * command's response data will be written. This can be either a host
12914 * physical address (HPA) or a guest physical address (GPA) and must
12915 * point to a physically contiguous block of memory.
12917 uint64_t resp_addr;
12920 * When this bit is set to '1', the PHY for the port shall
12923 * # If this bit is set to 1, then the HWRM shall reset the
12924 * PHY after applying PHY configuration changes specified
12926 * # In order to guarantee that PHY configuration changes
12927 * specified in this command take effect, the HWRM
12928 * client should set this flag to 1.
12929 * # If this bit is not set to 1, then the HWRM may reset
12930 * the PHY depending on the current PHY configuration and
12931 * settings specified in this command.
12933 #define HWRM_PORT_PHY_CFG_INPUT_FLAGS_RESET_PHY \
12935 /* deprecated bit. Do not use!!! */
12936 #define HWRM_PORT_PHY_CFG_INPUT_FLAGS_DEPRECATED \
12939 * When this bit is set to '1', the link shall be forced to
12940 * the force_link_speed value.
12942 * When this bit is set to '1', the HWRM client should
12943 * not enable any of the auto negotiation related
12944 * fields represented by auto_XXX fields in this command.
12945 * When this bit is set to '1' and the HWRM client has
12946 * enabled a auto_XXX field in this command, then the
12947 * HWRM shall ignore the enabled auto_XXX field.
12949 * When this bit is set to zero, the link
12950 * shall be allowed to autoneg.
12952 #define HWRM_PORT_PHY_CFG_INPUT_FLAGS_FORCE \
12955 * When this bit is set to '1', the auto-negotiation process
12956 * shall be restarted on the link.
12958 #define HWRM_PORT_PHY_CFG_INPUT_FLAGS_RESTART_AUTONEG \
12961 * When this bit is set to '1', Energy Efficient Ethernet
12962 * (EEE) is requested to be enabled on this link.
12963 * If EEE is not supported on this port, then this flag
12964 * shall be ignored by the HWRM.
12966 #define HWRM_PORT_PHY_CFG_INPUT_FLAGS_EEE_ENABLE \
12969 * When this bit is set to '1', Energy Efficient Ethernet
12970 * (EEE) is requested to be disabled on this link.
12971 * If EEE is not supported on this port, then this flag
12972 * shall be ignored by the HWRM.
12974 #define HWRM_PORT_PHY_CFG_INPUT_FLAGS_EEE_DISABLE \
12977 * When this bit is set to '1' and EEE is enabled on this
12978 * link, then TX LPI is requested to be enabled on the link.
12979 * If EEE is not supported on this port, then this flag
12980 * shall be ignored by the HWRM.
12981 * If EEE is disabled on this port, then this flag shall be
12982 * ignored by the HWRM.
12984 #define HWRM_PORT_PHY_CFG_INPUT_FLAGS_EEE_TX_LPI_ENABLE \
12987 * When this bit is set to '1' and EEE is enabled on this
12988 * link, then TX LPI is requested to be disabled on the link.
12989 * If EEE is not supported on this port, then this flag
12990 * shall be ignored by the HWRM.
12991 * If EEE is disabled on this port, then this flag shall be
12992 * ignored by the HWRM.
12994 #define HWRM_PORT_PHY_CFG_INPUT_FLAGS_EEE_TX_LPI_DISABLE \
12997 * When set to 1, then the HWRM shall enable FEC autonegotitation
12998 * on this port if supported.
12999 * When set to 0, then this flag shall be ignored.
13000 * If FEC autonegotiation is not supported, then the HWRM shall ignore this
13003 #define HWRM_PORT_PHY_CFG_INPUT_FLAGS_FEC_AUTONEG_ENABLE \
13006 * When set to 1, then the HWRM shall disable FEC autonegotiation
13007 * on this port if supported.
13008 * When set to 0, then this flag shall be ignored.
13009 * If FEC autonegotiation is not supported, then the HWRM shall ignore this
13012 #define HWRM_PORT_PHY_CFG_INPUT_FLAGS_FEC_AUTONEG_DISABLE \
13015 * When set to 1, then the HWRM shall enable FEC CLAUSE 74 (Fire Code)
13016 * on this port if supported.
13017 * When set to 0, then this flag shall be ignored.
13018 * If FEC CLAUSE 74 is not supported, then the HWRM shall ignore this
13021 #define HWRM_PORT_PHY_CFG_INPUT_FLAGS_FEC_CLAUSE74_ENABLE \
13024 * When set to 1, then the HWRM shall disable FEC CLAUSE 74 (Fire Code)
13025 * on this port if supported.
13026 * When set to 0, then this flag shall be ignored.
13027 * If FEC CLAUSE 74 is not supported, then the HWRM shall ignore this
13030 #define HWRM_PORT_PHY_CFG_INPUT_FLAGS_FEC_CLAUSE74_DISABLE \
13033 * When set to 1, then the HWRM shall enable FEC CLAUSE 91 (Reed Solomon)
13034 * on this port if supported.
13035 * When set to 0, then this flag shall be ignored.
13036 * If FEC CLAUSE 91 is not supported, then the HWRM shall ignore this
13039 #define HWRM_PORT_PHY_CFG_INPUT_FLAGS_FEC_CLAUSE91_ENABLE \
13042 * When set to 1, then the HWRM shall disable FEC CLAUSE 91 (Reed Solomon)
13043 * on this port if supported.
13044 * When set to 0, then this flag shall be ignored.
13045 * If FEC CLAUSE 91 is not supported, then the HWRM shall ignore this
13048 #define HWRM_PORT_PHY_CFG_INPUT_FLAGS_FEC_CLAUSE91_DISABLE \
13051 * When this bit is set to '1', the link shall be forced to
13054 * # When this bit is set to '1", all other
13055 * command input settings related to the link speed shall
13057 * Once the link state is forced down, it can be
13058 * explicitly cleared from that state by setting this flag
13060 * # If this flag is set to '0', then the link shall be
13061 * cleared from forced down state if the link is in forced
13063 * There may be conditions (e.g. out-of-band or sideband
13064 * configuration changes for the link) outside the scope
13065 * of the HWRM implementation that may clear forced down
13068 #define HWRM_PORT_PHY_CFG_INPUT_FLAGS_FORCE_LINK_DWN \
13072 * This bit must be '1' for the auto_mode field to be
13075 #define HWRM_PORT_PHY_CFG_INPUT_ENABLES_AUTO_MODE \
13078 * This bit must be '1' for the auto_duplex field to be
13081 #define HWRM_PORT_PHY_CFG_INPUT_ENABLES_AUTO_DUPLEX \
13084 * This bit must be '1' for the auto_pause field to be
13087 #define HWRM_PORT_PHY_CFG_INPUT_ENABLES_AUTO_PAUSE \
13090 * This bit must be '1' for the auto_link_speed field to be
13093 #define HWRM_PORT_PHY_CFG_INPUT_ENABLES_AUTO_LINK_SPEED \
13096 * This bit must be '1' for the auto_link_speed_mask field to be
13099 #define HWRM_PORT_PHY_CFG_INPUT_ENABLES_AUTO_LINK_SPEED_MASK \
13102 * This bit must be '1' for the wirespeed field to be
13105 #define HWRM_PORT_PHY_CFG_INPUT_ENABLES_WIRESPEED \
13108 * This bit must be '1' for the lpbk field to be
13111 #define HWRM_PORT_PHY_CFG_INPUT_ENABLES_LPBK \
13114 * This bit must be '1' for the preemphasis field to be
13117 #define HWRM_PORT_PHY_CFG_INPUT_ENABLES_PREEMPHASIS \
13120 * This bit must be '1' for the force_pause field to be
13123 #define HWRM_PORT_PHY_CFG_INPUT_ENABLES_FORCE_PAUSE \
13126 * This bit must be '1' for the eee_link_speed_mask field to be
13129 #define HWRM_PORT_PHY_CFG_INPUT_ENABLES_EEE_LINK_SPEED_MASK \
13132 * This bit must be '1' for the tx_lpi_timer field to be
13135 #define HWRM_PORT_PHY_CFG_INPUT_ENABLES_TX_LPI_TIMER \
13137 /* Port ID of port that is to be configured. */
13140 * This is the speed that will be used if the force
13141 * bit is '1'. If unsupported speed is selected, an error
13142 * will be generated.
13144 uint16_t force_link_speed;
13145 /* 100Mb link speed */
13146 #define HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_100MB UINT32_C(0x1)
13147 /* 1Gb link speed */
13148 #define HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_1GB UINT32_C(0xa)
13149 /* 2Gb link speed */
13150 #define HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_2GB UINT32_C(0x14)
13151 /* 25Gb link speed */
13152 #define HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_2_5GB UINT32_C(0x19)
13153 /* 10Gb link speed */
13154 #define HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_10GB UINT32_C(0x64)
13155 /* 20Mb link speed */
13156 #define HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_20GB UINT32_C(0xc8)
13157 /* 25Gb link speed */
13158 #define HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_25GB UINT32_C(0xfa)
13159 /* 40Gb link speed */
13160 #define HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_40GB UINT32_C(0x190)
13161 /* 50Gb link speed */
13162 #define HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_50GB UINT32_C(0x1f4)
13163 /* 100Gb link speed */
13164 #define HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_100GB UINT32_C(0x3e8)
13165 /* 200Gb link speed */
13166 #define HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_200GB UINT32_C(0x7d0)
13167 /* 10Mb link speed */
13168 #define HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_10MB UINT32_C(0xffff)
13169 #define HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_LAST \
13170 HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_10MB
13172 * This value is used to identify what autoneg mode is
13173 * used when the link speed is not being forced.
13176 /* Disable autoneg or autoneg disabled. No speeds are selected. */
13177 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_MODE_NONE UINT32_C(0x0)
13178 /* Select all possible speeds for autoneg mode. */
13179 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_MODE_ALL_SPEEDS UINT32_C(0x1)
13181 * Select only the auto_link_speed speed for autoneg mode. This mode has
13182 * been DEPRECATED. An HWRM client should not use this mode.
13184 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_MODE_ONE_SPEED UINT32_C(0x2)
13186 * Select the auto_link_speed or any speed below that speed for autoneg.
13187 * This mode has been DEPRECATED. An HWRM client should not use this mode.
13189 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_MODE_ONE_OR_BELOW UINT32_C(0x3)
13191 * Select the speeds based on the corresponding link speed mask value
13192 * that is provided.
13194 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_MODE_SPEED_MASK UINT32_C(0x4)
13195 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_MODE_LAST \
13196 HWRM_PORT_PHY_CFG_INPUT_AUTO_MODE_SPEED_MASK
13198 * This is the duplex setting that will be used if the autoneg_mode
13199 * is "one_speed" or "one_or_below".
13201 uint8_t auto_duplex;
13202 /* Half Duplex will be requested. */
13203 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_HALF UINT32_C(0x0)
13204 /* Full duplex will be requested. */
13205 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_FULL UINT32_C(0x1)
13206 /* Both Half and Full dupex will be requested. */
13207 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_BOTH UINT32_C(0x2)
13208 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_LAST \
13209 HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_BOTH
13211 * This value is used to configure the pause that will be
13212 * used for autonegotiation.
13213 * Add text on the usage of auto_pause and force_pause.
13215 uint8_t auto_pause;
13217 * When this bit is '1', Generation of tx pause messages
13218 * has been requested. Disabled otherwise.
13220 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_TX \
13223 * When this bit is '1', Reception of rx pause messages
13224 * has been requested. Disabled otherwise.
13226 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_RX \
13229 * When set to 1, the advertisement of pause is enabled.
13231 * # When the auto_mode is not set to none and this flag is
13232 * set to 1, then the auto_pause bits on this port are being
13233 * advertised and autoneg pause results are being interpreted.
13234 * # When the auto_mode is not set to none and this
13235 * flag is set to 0, the pause is forced as indicated in
13236 * force_pause, and also advertised as auto_pause bits, but
13237 * the autoneg results are not interpreted since the pause
13238 * configuration is being forced.
13239 * # When the auto_mode is set to none and this flag is set to
13240 * 1, auto_pause bits should be ignored and should be set to 0.
13242 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_AUTONEG_PAUSE \
13246 * This is the speed that will be used if the autoneg_mode
13247 * is "one_speed" or "one_or_below". If an unsupported speed
13248 * is selected, an error will be generated.
13250 uint16_t auto_link_speed;
13251 /* 100Mb link speed */
13252 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_100MB UINT32_C(0x1)
13253 /* 1Gb link speed */
13254 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_1GB UINT32_C(0xa)
13255 /* 2Gb link speed */
13256 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_2GB UINT32_C(0x14)
13257 /* 25Gb link speed */
13258 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_2_5GB UINT32_C(0x19)
13259 /* 10Gb link speed */
13260 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_10GB UINT32_C(0x64)
13261 /* 20Mb link speed */
13262 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_20GB UINT32_C(0xc8)
13263 /* 25Gb link speed */
13264 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_25GB UINT32_C(0xfa)
13265 /* 40Gb link speed */
13266 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_40GB UINT32_C(0x190)
13267 /* 50Gb link speed */
13268 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_50GB UINT32_C(0x1f4)
13269 /* 100Gb link speed */
13270 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_100GB UINT32_C(0x3e8)
13271 /* 200Gb link speed */
13272 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_200GB UINT32_C(0x7d0)
13273 /* 10Mb link speed */
13274 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_10MB UINT32_C(0xffff)
13275 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_LAST \
13276 HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_10MB
13278 * This is a mask of link speeds that will be used if
13279 * autoneg_mode is "mask". If unsupported speed is enabled
13280 * an error will be generated.
13282 uint16_t auto_link_speed_mask;
13283 /* 100Mb link speed (Half-duplex) */
13284 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_100MBHD \
13286 /* 100Mb link speed (Full-duplex) */
13287 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_100MB \
13289 /* 1Gb link speed (Half-duplex) */
13290 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_1GBHD \
13292 /* 1Gb link speed (Full-duplex) */
13293 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_1GB \
13295 /* 2Gb link speed */
13296 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_2GB \
13298 /* 25Gb link speed */
13299 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_2_5GB \
13301 /* 10Gb link speed */
13302 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_10GB \
13304 /* 20Gb link speed */
13305 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_20GB \
13307 /* 25Gb link speed */
13308 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_25GB \
13310 /* 40Gb link speed */
13311 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_40GB \
13313 /* 50Gb link speed */
13314 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_50GB \
13316 /* 100Gb link speed */
13317 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_100GB \
13319 /* 10Mb link speed (Half-duplex) */
13320 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_10MBHD \
13322 /* 10Mb link speed (Full-duplex) */
13323 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_10MB \
13325 /* 200Gb link speed */
13326 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_200GB \
13328 /* This value controls the wirespeed feature. */
13330 /* Wirespeed feature is disabled. */
13331 #define HWRM_PORT_PHY_CFG_INPUT_WIRESPEED_OFF UINT32_C(0x0)
13332 /* Wirespeed feature is enabled. */
13333 #define HWRM_PORT_PHY_CFG_INPUT_WIRESPEED_ON UINT32_C(0x1)
13334 #define HWRM_PORT_PHY_CFG_INPUT_WIRESPEED_LAST \
13335 HWRM_PORT_PHY_CFG_INPUT_WIRESPEED_ON
13336 /* This value controls the loopback setting for the PHY. */
13338 /* No loopback is selected. Normal operation. */
13339 #define HWRM_PORT_PHY_CFG_INPUT_LPBK_NONE UINT32_C(0x0)
13341 * The HW will be configured with local loopback such that
13342 * host data is sent back to the host without modification.
13344 #define HWRM_PORT_PHY_CFG_INPUT_LPBK_LOCAL UINT32_C(0x1)
13346 * The HW will be configured with remote loopback such that
13347 * port logic will send packets back out the transmitter that
13350 #define HWRM_PORT_PHY_CFG_INPUT_LPBK_REMOTE UINT32_C(0x2)
13352 * The HW will be configured with external loopback such that
13353 * host data is sent on the trasmitter and based on the external
13354 * loopback connection the data will be received without modification.
13356 #define HWRM_PORT_PHY_CFG_INPUT_LPBK_EXTERNAL UINT32_C(0x3)
13357 #define HWRM_PORT_PHY_CFG_INPUT_LPBK_LAST \
13358 HWRM_PORT_PHY_CFG_INPUT_LPBK_EXTERNAL
13360 * This value is used to configure the pause that will be
13361 * used for force mode.
13363 uint8_t force_pause;
13365 * When this bit is '1', Generation of tx pause messages
13366 * is supported. Disabled otherwise.
13368 #define HWRM_PORT_PHY_CFG_INPUT_FORCE_PAUSE_TX UINT32_C(0x1)
13370 * When this bit is '1', Reception of rx pause messages
13371 * is supported. Disabled otherwise.
13373 #define HWRM_PORT_PHY_CFG_INPUT_FORCE_PAUSE_RX UINT32_C(0x2)
13376 * This value controls the pre-emphasis to be used for the
13377 * link. Driver should not set this value (use
13378 * enable.preemphasis = 0) unless driver is sure of setting.
13379 * Normally HWRM FW will determine proper pre-emphasis.
13381 uint32_t preemphasis;
13383 * Setting for link speed mask that is used to
13384 * advertise speeds during autonegotiation when EEE is enabled.
13385 * This field is valid only when EEE is enabled.
13386 * The speeds specified in this field shall be a subset of
13387 * speeds specified in auto_link_speed_mask.
13388 * If EEE is enabled,then at least one speed shall be provided
13391 uint16_t eee_link_speed_mask;
13393 #define HWRM_PORT_PHY_CFG_INPUT_EEE_LINK_SPEED_MASK_RSVD1 \
13395 /* 100Mb link speed (Full-duplex) */
13396 #define HWRM_PORT_PHY_CFG_INPUT_EEE_LINK_SPEED_MASK_100MB \
13399 #define HWRM_PORT_PHY_CFG_INPUT_EEE_LINK_SPEED_MASK_RSVD2 \
13401 /* 1Gb link speed (Full-duplex) */
13402 #define HWRM_PORT_PHY_CFG_INPUT_EEE_LINK_SPEED_MASK_1GB \
13405 #define HWRM_PORT_PHY_CFG_INPUT_EEE_LINK_SPEED_MASK_RSVD3 \
13408 #define HWRM_PORT_PHY_CFG_INPUT_EEE_LINK_SPEED_MASK_RSVD4 \
13410 /* 10Gb link speed */
13411 #define HWRM_PORT_PHY_CFG_INPUT_EEE_LINK_SPEED_MASK_10GB \
13413 uint8_t unused_2[2];
13415 * Reuested setting of TX LPI timer in microseconds.
13416 * This field is valid only when EEE is enabled and TX LPI is
13419 uint32_t tx_lpi_timer;
13420 #define HWRM_PORT_PHY_CFG_INPUT_TX_LPI_TIMER_MASK UINT32_C(0xffffff)
13421 #define HWRM_PORT_PHY_CFG_INPUT_TX_LPI_TIMER_SFT 0
13423 } __attribute__((packed));
13425 /* hwrm_port_phy_cfg_output (size:128b/16B) */
13426 struct hwrm_port_phy_cfg_output {
13427 /* The specific error status for the command. */
13428 uint16_t error_code;
13429 /* The HWRM command request type. */
13431 /* The sequence ID from the original command. */
13433 /* The length of the response data in number of bytes. */
13435 uint8_t unused_0[7];
13437 * This field is used in Output records to indicate that the output
13438 * is completely written to RAM. This field should be read as '1'
13439 * to indicate that the output has been completely written.
13440 * When writing a command completion or response to an internal processor,
13441 * the order of writes has to be such that this field is written last.
13444 } __attribute__((packed));
13446 /* hwrm_port_phy_cfg_cmd_err (size:64b/8B) */
13447 struct hwrm_port_phy_cfg_cmd_err {
13449 * command specific error codes that goes to
13450 * the cmd_err field in Common HWRM Error Response.
13453 /* Unknown error */
13454 #define HWRM_PORT_PHY_CFG_CMD_ERR_CODE_UNKNOWN UINT32_C(0x0)
13455 /* Unable to complete operation due to invalid speed */
13456 #define HWRM_PORT_PHY_CFG_CMD_ERR_CODE_ILLEGAL_SPEED UINT32_C(0x1)
13458 * retry the command since the phy is not ready.
13459 * retry count is returned in opaque_0.
13460 * This is only valid for the first command and
13461 * this value will not change for successive calls.
13462 * but if a 0 is returned at any time then this should
13463 * be treated as an un recoverable failure,
13465 * retry interval in milli seconds is returned in opaque_1.
13466 * This specifies the time that user should wait before
13467 * issuing the next port_phy_cfg command.
13469 #define HWRM_PORT_PHY_CFG_CMD_ERR_CODE_RETRY UINT32_C(0x2)
13470 #define HWRM_PORT_PHY_CFG_CMD_ERR_CODE_LAST \
13471 HWRM_PORT_PHY_CFG_CMD_ERR_CODE_RETRY
13472 uint8_t unused_0[7];
13473 } __attribute__((packed));
13475 /**********************
13476 * hwrm_port_phy_qcfg *
13477 **********************/
13480 /* hwrm_port_phy_qcfg_input (size:192b/24B) */
13481 struct hwrm_port_phy_qcfg_input {
13482 /* The HWRM command request type. */
13485 * The completion ring to send the completion event on. This should
13486 * be the NQ ID returned from the `nq_alloc` HWRM command.
13488 uint16_t cmpl_ring;
13490 * The sequence ID is used by the driver for tracking multiple
13491 * commands. This ID is treated as opaque data by the firmware and
13492 * the value is returned in the `hwrm_resp_hdr` upon completion.
13496 * The target ID of the command:
13497 * * 0x0-0xFFF8 - The function ID
13498 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
13499 * * 0xFFFD - Reserved for user-space HWRM interface
13502 uint16_t target_id;
13504 * A physical address pointer pointing to a host buffer that the
13505 * command's response data will be written. This can be either a host
13506 * physical address (HPA) or a guest physical address (GPA) and must
13507 * point to a physically contiguous block of memory.
13509 uint64_t resp_addr;
13510 /* Port ID of port that is to be queried. */
13512 uint8_t unused_0[6];
13513 } __attribute__((packed));
13515 /* hwrm_port_phy_qcfg_output (size:768b/96B) */
13516 struct hwrm_port_phy_qcfg_output {
13517 /* The specific error status for the command. */
13518 uint16_t error_code;
13519 /* The HWRM command request type. */
13521 /* The sequence ID from the original command. */
13523 /* The length of the response data in number of bytes. */
13525 /* This value indicates the current link status. */
13527 /* There is no link or cable detected. */
13528 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_NO_LINK UINT32_C(0x0)
13529 /* There is no link, but a cable has been detected. */
13530 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SIGNAL UINT32_C(0x1)
13531 /* There is a link. */
13532 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_LINK UINT32_C(0x2)
13533 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_LAST \
13534 HWRM_PORT_PHY_QCFG_OUTPUT_LINK_LINK
13536 /* This value indicates the current link speed of the connection. */
13537 uint16_t link_speed;
13538 /* 100Mb link speed */
13539 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_100MB UINT32_C(0x1)
13540 /* 1Gb link speed */
13541 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_1GB UINT32_C(0xa)
13542 /* 2Gb link speed */
13543 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_2GB UINT32_C(0x14)
13544 /* 25Gb link speed */
13545 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_2_5GB UINT32_C(0x19)
13546 /* 10Gb link speed */
13547 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_10GB UINT32_C(0x64)
13548 /* 20Mb link speed */
13549 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_20GB UINT32_C(0xc8)
13550 /* 25Gb link speed */
13551 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_25GB UINT32_C(0xfa)
13552 /* 40Gb link speed */
13553 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_40GB UINT32_C(0x190)
13554 /* 50Gb link speed */
13555 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_50GB UINT32_C(0x1f4)
13556 /* 100Gb link speed */
13557 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_100GB UINT32_C(0x3e8)
13558 /* 200Gb link speed */
13559 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_200GB UINT32_C(0x7d0)
13560 /* 10Mb link speed */
13561 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_10MB UINT32_C(0xffff)
13562 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_LAST \
13563 HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_10MB
13565 * This value is indicates the duplex of the current
13568 uint8_t duplex_cfg;
13569 /* Half Duplex connection. */
13570 #define HWRM_PORT_PHY_QCFG_OUTPUT_DUPLEX_CFG_HALF UINT32_C(0x0)
13571 /* Full duplex connection. */
13572 #define HWRM_PORT_PHY_QCFG_OUTPUT_DUPLEX_CFG_FULL UINT32_C(0x1)
13573 #define HWRM_PORT_PHY_QCFG_OUTPUT_DUPLEX_CFG_LAST \
13574 HWRM_PORT_PHY_QCFG_OUTPUT_DUPLEX_CFG_FULL
13576 * This value is used to indicate the current
13577 * pause configuration. When autoneg is enabled, this value
13578 * represents the autoneg results of pause configuration.
13582 * When this bit is '1', Generation of tx pause messages
13583 * is supported. Disabled otherwise.
13585 #define HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_TX UINT32_C(0x1)
13587 * When this bit is '1', Reception of rx pause messages
13588 * is supported. Disabled otherwise.
13590 #define HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_RX UINT32_C(0x2)
13592 * The supported speeds for the port. This is a bit mask.
13593 * For each speed that is supported, the corrresponding
13594 * bit will be set to '1'.
13596 uint16_t support_speeds;
13597 /* 100Mb link speed (Half-duplex) */
13598 #define HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_100MBHD \
13600 /* 100Mb link speed (Full-duplex) */
13601 #define HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_100MB \
13603 /* 1Gb link speed (Half-duplex) */
13604 #define HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_1GBHD \
13606 /* 1Gb link speed (Full-duplex) */
13607 #define HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_1GB \
13609 /* 2Gb link speed */
13610 #define HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_2GB \
13612 /* 25Gb link speed */
13613 #define HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_2_5GB \
13615 /* 10Gb link speed */
13616 #define HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_10GB \
13618 /* 20Gb link speed */
13619 #define HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_20GB \
13621 /* 25Gb link speed */
13622 #define HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_25GB \
13624 /* 40Gb link speed */
13625 #define HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_40GB \
13627 /* 50Gb link speed */
13628 #define HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_50GB \
13630 /* 100Gb link speed */
13631 #define HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_100GB \
13633 /* 10Mb link speed (Half-duplex) */
13634 #define HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_10MBHD \
13636 /* 10Mb link speed (Full-duplex) */
13637 #define HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_10MB \
13639 /* 200Gb link speed */
13640 #define HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_200GB \
13643 * Current setting of forced link speed.
13644 * When the link speed is not being forced, this
13645 * value shall be set to 0.
13647 uint16_t force_link_speed;
13648 /* 100Mb link speed */
13649 #define HWRM_PORT_PHY_QCFG_OUTPUT_FORCE_LINK_SPEED_100MB UINT32_C(0x1)
13650 /* 1Gb link speed */
13651 #define HWRM_PORT_PHY_QCFG_OUTPUT_FORCE_LINK_SPEED_1GB UINT32_C(0xa)
13652 /* 2Gb link speed */
13653 #define HWRM_PORT_PHY_QCFG_OUTPUT_FORCE_LINK_SPEED_2GB UINT32_C(0x14)
13654 /* 25Gb link speed */
13655 #define HWRM_PORT_PHY_QCFG_OUTPUT_FORCE_LINK_SPEED_2_5GB UINT32_C(0x19)
13656 /* 10Gb link speed */
13657 #define HWRM_PORT_PHY_QCFG_OUTPUT_FORCE_LINK_SPEED_10GB UINT32_C(0x64)
13658 /* 20Mb link speed */
13659 #define HWRM_PORT_PHY_QCFG_OUTPUT_FORCE_LINK_SPEED_20GB UINT32_C(0xc8)
13660 /* 25Gb link speed */
13661 #define HWRM_PORT_PHY_QCFG_OUTPUT_FORCE_LINK_SPEED_25GB UINT32_C(0xfa)
13662 /* 40Gb link speed */
13663 #define HWRM_PORT_PHY_QCFG_OUTPUT_FORCE_LINK_SPEED_40GB \
13665 /* 50Gb link speed */
13666 #define HWRM_PORT_PHY_QCFG_OUTPUT_FORCE_LINK_SPEED_50GB \
13668 /* 100Gb link speed */
13669 #define HWRM_PORT_PHY_QCFG_OUTPUT_FORCE_LINK_SPEED_100GB \
13671 /* 200Gb link speed */
13672 #define HWRM_PORT_PHY_QCFG_OUTPUT_FORCE_LINK_SPEED_200GB \
13674 /* 10Mb link speed */
13675 #define HWRM_PORT_PHY_QCFG_OUTPUT_FORCE_LINK_SPEED_10MB \
13677 #define HWRM_PORT_PHY_QCFG_OUTPUT_FORCE_LINK_SPEED_LAST \
13678 HWRM_PORT_PHY_QCFG_OUTPUT_FORCE_LINK_SPEED_10MB
13679 /* Current setting of auto negotiation mode. */
13681 /* Disable autoneg or autoneg disabled. No speeds are selected. */
13682 #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_MODE_NONE UINT32_C(0x0)
13683 /* Select all possible speeds for autoneg mode. */
13684 #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_MODE_ALL_SPEEDS UINT32_C(0x1)
13686 * Select only the auto_link_speed speed for autoneg mode. This mode has
13687 * been DEPRECATED. An HWRM client should not use this mode.
13689 #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_MODE_ONE_SPEED UINT32_C(0x2)
13691 * Select the auto_link_speed or any speed below that speed for autoneg.
13692 * This mode has been DEPRECATED. An HWRM client should not use this mode.
13694 #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_MODE_ONE_OR_BELOW UINT32_C(0x3)
13696 * Select the speeds based on the corresponding link speed mask value
13697 * that is provided.
13699 #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_MODE_SPEED_MASK UINT32_C(0x4)
13700 #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_MODE_LAST \
13701 HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_MODE_SPEED_MASK
13703 * Current setting of pause autonegotiation.
13704 * Move autoneg_pause flag here.
13706 uint8_t auto_pause;
13708 * When this bit is '1', Generation of tx pause messages
13709 * has been requested. Disabled otherwise.
13711 #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_PAUSE_TX \
13714 * When this bit is '1', Reception of rx pause messages
13715 * has been requested. Disabled otherwise.
13717 #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_PAUSE_RX \
13720 * When set to 1, the advertisement of pause is enabled.
13722 * # When the auto_mode is not set to none and this flag is
13723 * set to 1, then the auto_pause bits on this port are being
13724 * advertised and autoneg pause results are being interpreted.
13725 * # When the auto_mode is not set to none and this
13726 * flag is set to 0, the pause is forced as indicated in
13727 * force_pause, and also advertised as auto_pause bits, but
13728 * the autoneg results are not interpreted since the pause
13729 * configuration is being forced.
13730 * # When the auto_mode is set to none and this flag is set to
13731 * 1, auto_pause bits should be ignored and should be set to 0.
13733 #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_PAUSE_AUTONEG_PAUSE \
13736 * Current setting for auto_link_speed. This field is only
13737 * valid when auto_mode is set to "one_speed" or "one_or_below".
13739 uint16_t auto_link_speed;
13740 /* 100Mb link speed */
13741 #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_100MB UINT32_C(0x1)
13742 /* 1Gb link speed */
13743 #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_1GB UINT32_C(0xa)
13744 /* 2Gb link speed */
13745 #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_2GB UINT32_C(0x14)
13746 /* 25Gb link speed */
13747 #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_2_5GB UINT32_C(0x19)
13748 /* 10Gb link speed */
13749 #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_10GB UINT32_C(0x64)
13750 /* 20Mb link speed */
13751 #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_20GB UINT32_C(0xc8)
13752 /* 25Gb link speed */
13753 #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_25GB UINT32_C(0xfa)
13754 /* 40Gb link speed */
13755 #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_40GB UINT32_C(0x190)
13756 /* 50Gb link speed */
13757 #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_50GB UINT32_C(0x1f4)
13758 /* 100Gb link speed */
13759 #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_100GB UINT32_C(0x3e8)
13760 /* 200Gb link speed */
13761 #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_200GB UINT32_C(0x7d0)
13762 /* 10Mb link speed */
13763 #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_10MB \
13765 #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_LAST \
13766 HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_10MB
13768 * Current setting for auto_link_speed_mask that is used to
13769 * advertise speeds during autonegotiation.
13770 * This field is only valid when auto_mode is set to "mask".
13771 * The speeds specified in this field shall be a subset of
13772 * supported speeds on this port.
13774 uint16_t auto_link_speed_mask;
13775 /* 100Mb link speed (Half-duplex) */
13776 #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_MASK_100MBHD \
13778 /* 100Mb link speed (Full-duplex) */
13779 #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_MASK_100MB \
13781 /* 1Gb link speed (Half-duplex) */
13782 #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_MASK_1GBHD \
13784 /* 1Gb link speed (Full-duplex) */
13785 #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_MASK_1GB \
13787 /* 2Gb link speed */
13788 #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_MASK_2GB \
13790 /* 25Gb link speed */
13791 #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_MASK_2_5GB \
13793 /* 10Gb link speed */
13794 #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_MASK_10GB \
13796 /* 20Gb link speed */
13797 #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_MASK_20GB \
13799 /* 25Gb link speed */
13800 #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_MASK_25GB \
13802 /* 40Gb link speed */
13803 #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_MASK_40GB \
13805 /* 50Gb link speed */
13806 #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_MASK_50GB \
13808 /* 100Gb link speed */
13809 #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_MASK_100GB \
13811 /* 10Mb link speed (Half-duplex) */
13812 #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_MASK_10MBHD \
13814 /* 10Mb link speed (Full-duplex) */
13815 #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_MASK_10MB \
13817 /* 200Gb link speed */
13818 #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_MASK_200GB \
13820 /* Current setting for wirespeed. */
13822 /* Wirespeed feature is disabled. */
13823 #define HWRM_PORT_PHY_QCFG_OUTPUT_WIRESPEED_OFF UINT32_C(0x0)
13824 /* Wirespeed feature is enabled. */
13825 #define HWRM_PORT_PHY_QCFG_OUTPUT_WIRESPEED_ON UINT32_C(0x1)
13826 #define HWRM_PORT_PHY_QCFG_OUTPUT_WIRESPEED_LAST \
13827 HWRM_PORT_PHY_QCFG_OUTPUT_WIRESPEED_ON
13828 /* Current setting for loopback. */
13830 /* No loopback is selected. Normal operation. */
13831 #define HWRM_PORT_PHY_QCFG_OUTPUT_LPBK_NONE UINT32_C(0x0)
13833 * The HW will be configured with local loopback such that
13834 * host data is sent back to the host without modification.
13836 #define HWRM_PORT_PHY_QCFG_OUTPUT_LPBK_LOCAL UINT32_C(0x1)
13838 * The HW will be configured with remote loopback such that
13839 * port logic will send packets back out the transmitter that
13842 #define HWRM_PORT_PHY_QCFG_OUTPUT_LPBK_REMOTE UINT32_C(0x2)
13844 * The HW will be configured with external loopback such that
13845 * host data is sent on the trasmitter and based on the external
13846 * loopback connection the data will be received without modification.
13848 #define HWRM_PORT_PHY_QCFG_OUTPUT_LPBK_EXTERNAL UINT32_C(0x3)
13849 #define HWRM_PORT_PHY_QCFG_OUTPUT_LPBK_LAST \
13850 HWRM_PORT_PHY_QCFG_OUTPUT_LPBK_EXTERNAL
13852 * Current setting of forced pause.
13853 * When the pause configuration is not being forced, then
13854 * this value shall be set to 0.
13856 uint8_t force_pause;
13858 * When this bit is '1', Generation of tx pause messages
13859 * is supported. Disabled otherwise.
13861 #define HWRM_PORT_PHY_QCFG_OUTPUT_FORCE_PAUSE_TX UINT32_C(0x1)
13863 * When this bit is '1', Reception of rx pause messages
13864 * is supported. Disabled otherwise.
13866 #define HWRM_PORT_PHY_QCFG_OUTPUT_FORCE_PAUSE_RX UINT32_C(0x2)
13868 * This value indicates the current status of the optics module on
13871 uint8_t module_status;
13872 /* Module is inserted and accepted */
13873 #define HWRM_PORT_PHY_QCFG_OUTPUT_MODULE_STATUS_NONE \
13875 /* Module is rejected and transmit side Laser is disabled. */
13876 #define HWRM_PORT_PHY_QCFG_OUTPUT_MODULE_STATUS_DISABLETX \
13878 /* Module mismatch warning. */
13879 #define HWRM_PORT_PHY_QCFG_OUTPUT_MODULE_STATUS_WARNINGMSG \
13881 /* Module is rejected and powered down. */
13882 #define HWRM_PORT_PHY_QCFG_OUTPUT_MODULE_STATUS_PWRDOWN \
13884 /* Module is not inserted. */
13885 #define HWRM_PORT_PHY_QCFG_OUTPUT_MODULE_STATUS_NOTINSERTED \
13887 /* Module status is not applicable. */
13888 #define HWRM_PORT_PHY_QCFG_OUTPUT_MODULE_STATUS_NOTAPPLICABLE \
13890 #define HWRM_PORT_PHY_QCFG_OUTPUT_MODULE_STATUS_LAST \
13891 HWRM_PORT_PHY_QCFG_OUTPUT_MODULE_STATUS_NOTAPPLICABLE
13892 /* Current setting for preemphasis. */
13893 uint32_t preemphasis;
13894 /* This field represents the major version of the PHY. */
13896 /* This field represents the minor version of the PHY. */
13898 /* This field represents the build version of the PHY. */
13900 /* This value represents a PHY type. */
13903 #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_UNKNOWN \
13906 #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_BASECR \
13908 /* BASE-KR4 (Deprecated) */
13909 #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_BASEKR4 \
13912 #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_BASELR \
13915 #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_BASESR \
13917 /* BASE-KR2 (Deprecated) */
13918 #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_BASEKR2 \
13921 #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_BASEKX \
13924 #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_BASEKR \
13927 #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_BASET \
13929 /* EEE capable BASE-T */
13930 #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_BASETE \
13932 /* SGMII connected external PHY */
13933 #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_SGMIIEXTPHY \
13935 /* 25G_BASECR_CA_L */
13936 #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_25G_BASECR_CA_L \
13938 /* 25G_BASECR_CA_S */
13939 #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_25G_BASECR_CA_S \
13941 /* 25G_BASECR_CA_N */
13942 #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_25G_BASECR_CA_N \
13945 #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_25G_BASESR \
13948 #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_100G_BASECR4 \
13951 #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_100G_BASESR4 \
13954 #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_100G_BASELR4 \
13957 #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_100G_BASEER4 \
13959 /* 100G_BASESR10 */
13960 #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_100G_BASESR10 \
13963 #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_40G_BASECR4 \
13966 #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_40G_BASESR4 \
13969 #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_40G_BASELR4 \
13972 #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_40G_BASEER4 \
13974 /* 40G_ACTIVE_CABLE */
13975 #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_40G_ACTIVE_CABLE \
13978 #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_1G_BASET \
13981 #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_1G_BASESX \
13984 #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_1G_BASECX \
13987 #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_200G_BASECR4 \
13990 #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_200G_BASESR4 \
13993 #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_200G_BASELR4 \
13996 #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_200G_BASEER4 \
13998 #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_LAST \
13999 HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_200G_BASEER4
14000 /* This value represents a media type. */
14001 uint8_t media_type;
14003 #define HWRM_PORT_PHY_QCFG_OUTPUT_MEDIA_TYPE_UNKNOWN UINT32_C(0x0)
14005 #define HWRM_PORT_PHY_QCFG_OUTPUT_MEDIA_TYPE_TP UINT32_C(0x1)
14006 /* Direct Attached Copper */
14007 #define HWRM_PORT_PHY_QCFG_OUTPUT_MEDIA_TYPE_DAC UINT32_C(0x2)
14009 #define HWRM_PORT_PHY_QCFG_OUTPUT_MEDIA_TYPE_FIBRE UINT32_C(0x3)
14010 #define HWRM_PORT_PHY_QCFG_OUTPUT_MEDIA_TYPE_LAST \
14011 HWRM_PORT_PHY_QCFG_OUTPUT_MEDIA_TYPE_FIBRE
14012 /* This value represents a transceiver type. */
14013 uint8_t xcvr_pkg_type;
14014 /* PHY and MAC are in the same package */
14015 #define HWRM_PORT_PHY_QCFG_OUTPUT_XCVR_PKG_TYPE_XCVR_INTERNAL \
14017 /* PHY and MAC are in different packages */
14018 #define HWRM_PORT_PHY_QCFG_OUTPUT_XCVR_PKG_TYPE_XCVR_EXTERNAL \
14020 #define HWRM_PORT_PHY_QCFG_OUTPUT_XCVR_PKG_TYPE_LAST \
14021 HWRM_PORT_PHY_QCFG_OUTPUT_XCVR_PKG_TYPE_XCVR_EXTERNAL
14022 uint8_t eee_config_phy_addr;
14023 /* This field represents PHY address. */
14024 #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_ADDR_MASK \
14026 #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_ADDR_SFT 0
14028 * This field represents flags related to EEE configuration.
14029 * These EEE configuration flags are valid only when the
14030 * auto_mode is not set to none (in other words autonegotiation
14033 #define HWRM_PORT_PHY_QCFG_OUTPUT_EEE_CONFIG_MASK \
14035 #define HWRM_PORT_PHY_QCFG_OUTPUT_EEE_CONFIG_SFT 5
14037 * When set to 1, Energy Efficient Ethernet (EEE) mode is enabled.
14038 * Speeds for autoneg with EEE mode enabled
14039 * are based on eee_link_speed_mask.
14041 #define HWRM_PORT_PHY_QCFG_OUTPUT_EEE_CONFIG_EEE_ENABLED \
14044 * This flag is valid only when eee_enabled is set to 1.
14046 * # If eee_enabled is set to 0, then EEE mode is disabled
14047 * and this flag shall be ignored.
14048 * # If eee_enabled is set to 1 and this flag is set to 1,
14049 * then Energy Efficient Ethernet (EEE) mode is enabled
14051 * # If eee_enabled is set to 1 and this flag is set to 0,
14052 * then Energy Efficient Ethernet (EEE) mode is enabled
14053 * but is currently not in use.
14055 #define HWRM_PORT_PHY_QCFG_OUTPUT_EEE_CONFIG_EEE_ACTIVE \
14058 * This flag is valid only when eee_enabled is set to 1.
14060 * # If eee_enabled is set to 0, then EEE mode is disabled
14061 * and this flag shall be ignored.
14062 * # If eee_enabled is set to 1 and this flag is set to 1,
14063 * then Energy Efficient Ethernet (EEE) mode is enabled
14064 * and TX LPI is enabled.
14065 * # If eee_enabled is set to 1 and this flag is set to 0,
14066 * then Energy Efficient Ethernet (EEE) mode is enabled
14067 * but TX LPI is disabled.
14069 #define HWRM_PORT_PHY_QCFG_OUTPUT_EEE_CONFIG_EEE_TX_LPI \
14072 * When set to 1, the parallel detection is used to determine
14073 * the speed of the link partner.
14075 * Parallel detection is used when a autonegotiation capable
14076 * device is connected to a link parter that is not capable
14077 * of autonegotiation.
14079 uint8_t parallel_detect;
14081 * When set to 1, the parallel detection is used to determine
14082 * the speed of the link partner.
14084 * Parallel detection is used when a autonegotiation capable
14085 * device is connected to a link parter that is not capable
14086 * of autonegotiation.
14088 #define HWRM_PORT_PHY_QCFG_OUTPUT_PARALLEL_DETECT UINT32_C(0x1)
14090 * The advertised speeds for the port by the link partner.
14091 * Each advertised speed will be set to '1'.
14093 uint16_t link_partner_adv_speeds;
14094 /* 100Mb link speed (Half-duplex) */
14095 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_SPEEDS_100MBHD \
14097 /* 100Mb link speed (Full-duplex) */
14098 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_SPEEDS_100MB \
14100 /* 1Gb link speed (Half-duplex) */
14101 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_SPEEDS_1GBHD \
14103 /* 1Gb link speed (Full-duplex) */
14104 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_SPEEDS_1GB \
14106 /* 2Gb link speed */
14107 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_SPEEDS_2GB \
14109 /* 25Gb link speed */
14110 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_SPEEDS_2_5GB \
14112 /* 10Gb link speed */
14113 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_SPEEDS_10GB \
14115 /* 20Gb link speed */
14116 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_SPEEDS_20GB \
14118 /* 25Gb link speed */
14119 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_SPEEDS_25GB \
14121 /* 40Gb link speed */
14122 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_SPEEDS_40GB \
14124 /* 50Gb link speed */
14125 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_SPEEDS_50GB \
14127 /* 100Gb link speed */
14128 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_SPEEDS_100GB \
14130 /* 10Mb link speed (Half-duplex) */
14131 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_SPEEDS_10MBHD \
14133 /* 10Mb link speed (Full-duplex) */
14134 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_SPEEDS_10MB \
14137 * The advertised autoneg for the port by the link partner.
14138 * This field is deprecated and should be set to 0.
14140 uint8_t link_partner_adv_auto_mode;
14141 /* Disable autoneg or autoneg disabled. No speeds are selected. */
14142 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_AUTO_MODE_NONE \
14144 /* Select all possible speeds for autoneg mode. */
14145 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_AUTO_MODE_ALL_SPEEDS \
14148 * Select only the auto_link_speed speed for autoneg mode. This mode has
14149 * been DEPRECATED. An HWRM client should not use this mode.
14151 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_AUTO_MODE_ONE_SPEED \
14154 * Select the auto_link_speed or any speed below that speed for autoneg.
14155 * This mode has been DEPRECATED. An HWRM client should not use this mode.
14157 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_AUTO_MODE_ONE_OR_BELOW \
14160 * Select the speeds based on the corresponding link speed mask value
14161 * that is provided.
14163 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_AUTO_MODE_SPEED_MASK \
14165 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_AUTO_MODE_LAST \
14166 HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_AUTO_MODE_SPEED_MASK
14167 /* The advertised pause settings on the port by the link partner. */
14168 uint8_t link_partner_adv_pause;
14170 * When this bit is '1', Generation of tx pause messages
14171 * is supported. Disabled otherwise.
14173 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_PAUSE_TX \
14176 * When this bit is '1', Reception of rx pause messages
14177 * is supported. Disabled otherwise.
14179 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_PAUSE_RX \
14182 * Current setting for link speed mask that is used to
14183 * advertise speeds during autonegotiation when EEE is enabled.
14184 * This field is valid only when eee_enabled flags is set to 1.
14185 * The speeds specified in this field shall be a subset of
14186 * speeds specified in auto_link_speed_mask.
14188 uint16_t adv_eee_link_speed_mask;
14190 #define HWRM_PORT_PHY_QCFG_OUTPUT_ADV_EEE_LINK_SPEED_MASK_RSVD1 \
14192 /* 100Mb link speed (Full-duplex) */
14193 #define HWRM_PORT_PHY_QCFG_OUTPUT_ADV_EEE_LINK_SPEED_MASK_100MB \
14196 #define HWRM_PORT_PHY_QCFG_OUTPUT_ADV_EEE_LINK_SPEED_MASK_RSVD2 \
14198 /* 1Gb link speed (Full-duplex) */
14199 #define HWRM_PORT_PHY_QCFG_OUTPUT_ADV_EEE_LINK_SPEED_MASK_1GB \
14202 #define HWRM_PORT_PHY_QCFG_OUTPUT_ADV_EEE_LINK_SPEED_MASK_RSVD3 \
14205 #define HWRM_PORT_PHY_QCFG_OUTPUT_ADV_EEE_LINK_SPEED_MASK_RSVD4 \
14207 /* 10Gb link speed */
14208 #define HWRM_PORT_PHY_QCFG_OUTPUT_ADV_EEE_LINK_SPEED_MASK_10GB \
14211 * Current setting for link speed mask that is advertised by
14212 * the link partner when EEE is enabled.
14213 * This field is valid only when eee_enabled flags is set to 1.
14215 uint16_t link_partner_adv_eee_link_speed_mask;
14217 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_EEE_LINK_SPEED_MASK_RSVD1 \
14219 /* 100Mb link speed (Full-duplex) */
14220 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_EEE_LINK_SPEED_MASK_100MB \
14223 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_EEE_LINK_SPEED_MASK_RSVD2 \
14225 /* 1Gb link speed (Full-duplex) */
14226 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_EEE_LINK_SPEED_MASK_1GB \
14229 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_EEE_LINK_SPEED_MASK_RSVD3 \
14232 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_EEE_LINK_SPEED_MASK_RSVD4 \
14234 /* 10Gb link speed */
14235 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_EEE_LINK_SPEED_MASK_10GB \
14237 uint32_t xcvr_identifier_type_tx_lpi_timer;
14239 * Current setting of TX LPI timer in microseconds.
14240 * This field is valid only when_eee_enabled flag is set to 1
14241 * and tx_lpi_enabled is set to 1.
14243 #define HWRM_PORT_PHY_QCFG_OUTPUT_TX_LPI_TIMER_MASK \
14245 #define HWRM_PORT_PHY_QCFG_OUTPUT_TX_LPI_TIMER_SFT 0
14246 /* This value represents transceiver identifier type. */
14247 #define HWRM_PORT_PHY_QCFG_OUTPUT_XCVR_IDENTIFIER_TYPE_MASK \
14248 UINT32_C(0xff000000)
14249 #define HWRM_PORT_PHY_QCFG_OUTPUT_XCVR_IDENTIFIER_TYPE_SFT 24
14251 #define HWRM_PORT_PHY_QCFG_OUTPUT_XCVR_IDENTIFIER_TYPE_UNKNOWN \
14252 (UINT32_C(0x0) << 24)
14253 /* SFP/SFP+/SFP28 */
14254 #define HWRM_PORT_PHY_QCFG_OUTPUT_XCVR_IDENTIFIER_TYPE_SFP \
14255 (UINT32_C(0x3) << 24)
14257 #define HWRM_PORT_PHY_QCFG_OUTPUT_XCVR_IDENTIFIER_TYPE_QSFP \
14258 (UINT32_C(0xc) << 24)
14260 #define HWRM_PORT_PHY_QCFG_OUTPUT_XCVR_IDENTIFIER_TYPE_QSFPPLUS \
14261 (UINT32_C(0xd) << 24)
14263 #define HWRM_PORT_PHY_QCFG_OUTPUT_XCVR_IDENTIFIER_TYPE_QSFP28 \
14264 (UINT32_C(0x11) << 24)
14265 #define HWRM_PORT_PHY_QCFG_OUTPUT_XCVR_IDENTIFIER_TYPE_LAST \
14266 HWRM_PORT_PHY_QCFG_OUTPUT_XCVR_IDENTIFIER_TYPE_QSFP28
14268 * This value represents the current configuration of
14269 * Forward Error Correction (FEC) on the port.
14273 * When set to 1, then FEC is not supported on this port. If this flag
14274 * is set to 1, then all other FEC configuration flags shall be ignored.
14275 * When set to 0, then FEC is supported as indicated by other
14276 * configuration flags.
14277 * If no cable is attached and the HWRM does not yet know the FEC
14278 * capability, then the HWRM shall set this flag to 1 when reporting
14281 #define HWRM_PORT_PHY_QCFG_OUTPUT_FEC_CFG_FEC_NONE_SUPPORTED \
14284 * When set to 1, then FEC autonegotiation is supported on this port.
14285 * When set to 0, then FEC autonegotiation is not supported on this port.
14287 #define HWRM_PORT_PHY_QCFG_OUTPUT_FEC_CFG_FEC_AUTONEG_SUPPORTED \
14290 * When set to 1, then FEC autonegotiation is enabled on this port.
14291 * When set to 0, then FEC autonegotiation is disabled if supported.
14292 * This flag should be ignored if FEC autonegotiation is not supported on this port.
14294 #define HWRM_PORT_PHY_QCFG_OUTPUT_FEC_CFG_FEC_AUTONEG_ENABLED \
14297 * When set to 1, then FEC CLAUSE 74 (Fire Code) is supported on this port.
14298 * When set to 0, then FEC CLAUSE 74 (Fire Code) is not supported on this port.
14300 #define HWRM_PORT_PHY_QCFG_OUTPUT_FEC_CFG_FEC_CLAUSE74_SUPPORTED \
14303 * When set to 1, then FEC CLAUSE 74 (Fire Code) is enabled on this port.
14304 * When set to 0, then FEC CLAUSE 74 (Fire Code) is disabled if supported.
14305 * This flag should be ignored if FEC CLAUSE 74 is not supported on this port.
14307 #define HWRM_PORT_PHY_QCFG_OUTPUT_FEC_CFG_FEC_CLAUSE74_ENABLED \
14310 * When set to 1, then FEC CLAUSE 91 (Reed Solomon) is supported on this port.
14311 * When set to 0, then FEC CLAUSE 91 (Reed Solomon) is not supported on this port.
14313 #define HWRM_PORT_PHY_QCFG_OUTPUT_FEC_CFG_FEC_CLAUSE91_SUPPORTED \
14316 * When set to 1, then FEC CLAUSE 91 (Reed Solomon) is enabled on this port.
14317 * When set to 0, then FEC CLAUSE 91 (Reed Solomon) is disabled if supported.
14318 * This flag should be ignored if FEC CLAUSE 91 is not supported on this port.
14320 #define HWRM_PORT_PHY_QCFG_OUTPUT_FEC_CFG_FEC_CLAUSE91_ENABLED \
14323 * This value is indicates the duplex of the current
14324 * connection state.
14326 uint8_t duplex_state;
14327 /* Half Duplex connection. */
14328 #define HWRM_PORT_PHY_QCFG_OUTPUT_DUPLEX_STATE_HALF UINT32_C(0x0)
14329 /* Full duplex connection. */
14330 #define HWRM_PORT_PHY_QCFG_OUTPUT_DUPLEX_STATE_FULL UINT32_C(0x1)
14331 #define HWRM_PORT_PHY_QCFG_OUTPUT_DUPLEX_STATE_LAST \
14332 HWRM_PORT_PHY_QCFG_OUTPUT_DUPLEX_STATE_FULL
14333 /* Option flags fields. */
14334 uint8_t option_flags;
14335 /* When this bit is '1', Media auto detect is enabled. */
14336 #define HWRM_PORT_PHY_QCFG_OUTPUT_OPTION_FLAGS_MEDIA_AUTO_DETECT \
14339 * Up to 16 bytes of null padded ASCII string representing
14341 * If the string is set to null, then the vendor name is not
14344 char phy_vendor_name[16];
14346 * Up to 16 bytes of null padded ASCII string that
14347 * identifies vendor specific part number of the PHY.
14348 * If the string is set to null, then the vendor specific
14349 * part number is not available.
14351 char phy_vendor_partnumber[16];
14352 uint8_t unused_2[7];
14354 * This field is used in Output records to indicate that the output
14355 * is completely written to RAM. This field should be read as '1'
14356 * to indicate that the output has been completely written.
14357 * When writing a command completion or response to an internal processor,
14358 * the order of writes has to be such that this field is written last.
14361 } __attribute__((packed));
14363 /*********************
14364 * hwrm_port_mac_cfg *
14365 *********************/
14368 /* hwrm_port_mac_cfg_input (size:384b/48B) */
14369 struct hwrm_port_mac_cfg_input {
14370 /* The HWRM command request type. */
14373 * The completion ring to send the completion event on. This should
14374 * be the NQ ID returned from the `nq_alloc` HWRM command.
14376 uint16_t cmpl_ring;
14378 * The sequence ID is used by the driver for tracking multiple
14379 * commands. This ID is treated as opaque data by the firmware and
14380 * the value is returned in the `hwrm_resp_hdr` upon completion.
14384 * The target ID of the command:
14385 * * 0x0-0xFFF8 - The function ID
14386 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
14387 * * 0xFFFD - Reserved for user-space HWRM interface
14390 uint16_t target_id;
14392 * A physical address pointer pointing to a host buffer that the
14393 * command's response data will be written. This can be either a host
14394 * physical address (HPA) or a guest physical address (GPA) and must
14395 * point to a physically contiguous block of memory.
14397 uint64_t resp_addr;
14399 * In this field, there are a number of CoS mappings related flags
14400 * that are used to configure CoS mappings and their corresponding
14401 * priorities in the hardware.
14402 * For the priorities of CoS mappings, the HWRM uses the following
14403 * priority order (high to low) by default:
14406 * # tunnel_vlan_pri
14409 * A subset of CoS mappings can be enabled.
14410 * If a priority is not specified for an enabled CoS mapping, the
14411 * priority will be assigned in the above order for the enabled CoS
14412 * mappings. For example, if vlan_pri and ip_dscp CoS mappings are
14413 * enabled and their priorities are not specified, the following
14414 * priority order (high to low) will be used by the HWRM:
14419 * vlan_pri CoS mapping together with default CoS with lower priority
14420 * are enabled by default by the HWRM.
14424 * When this bit is '1', this command will configure
14425 * the MAC to match the current link state of the PHY.
14426 * If the link is not established on the PHY, then this
14427 * bit has no effect.
14429 #define HWRM_PORT_MAC_CFG_INPUT_FLAGS_MATCH_LINK \
14432 * When this bit is set to '1', the inner VLAN PRI to CoS mapping
14433 * is requested to be enabled.
14435 #define HWRM_PORT_MAC_CFG_INPUT_FLAGS_VLAN_PRI2COS_ENABLE \
14438 * When this bit is set to '1', tunnel VLAN PRI field to
14439 * CoS mapping is requested to be enabled.
14441 #define HWRM_PORT_MAC_CFG_INPUT_FLAGS_TUNNEL_PRI2COS_ENABLE \
14444 * When this bit is set to '1', the IP DSCP to CoS mapping is
14445 * requested to be enabled.
14447 #define HWRM_PORT_MAC_CFG_INPUT_FLAGS_IP_DSCP2COS_ENABLE \
14450 * When this bit is '1', the HWRM is requested to
14451 * enable timestamp capture capability on the receive side
14454 #define HWRM_PORT_MAC_CFG_INPUT_FLAGS_PTP_RX_TS_CAPTURE_ENABLE \
14457 * When this bit is '1', the HWRM is requested to
14458 * disable timestamp capture capability on the receive side
14461 #define HWRM_PORT_MAC_CFG_INPUT_FLAGS_PTP_RX_TS_CAPTURE_DISABLE \
14464 * When this bit is '1', the HWRM is requested to
14465 * enable timestamp capture capability on the transmit side
14468 #define HWRM_PORT_MAC_CFG_INPUT_FLAGS_PTP_TX_TS_CAPTURE_ENABLE \
14471 * When this bit is '1', the HWRM is requested to
14472 * disable timestamp capture capability on the transmit side
14475 #define HWRM_PORT_MAC_CFG_INPUT_FLAGS_PTP_TX_TS_CAPTURE_DISABLE \
14478 * When this bit is '1', the Out-Of-Box WoL is requested to
14479 * be enabled on this port.
14481 #define HWRM_PORT_MAC_CFG_INPUT_FLAGS_OOB_WOL_ENABLE \
14484 * When this bit is '1', the the Out-Of-Box WoL is requested to
14485 * be disabled on this port.
14487 #define HWRM_PORT_MAC_CFG_INPUT_FLAGS_OOB_WOL_DISABLE \
14490 * When this bit is set to '1', the inner VLAN PRI to CoS mapping
14491 * is requested to be disabled.
14493 #define HWRM_PORT_MAC_CFG_INPUT_FLAGS_VLAN_PRI2COS_DISABLE \
14496 * When this bit is set to '1', tunnel VLAN PRI field to
14497 * CoS mapping is requested to be disabled.
14499 #define HWRM_PORT_MAC_CFG_INPUT_FLAGS_TUNNEL_PRI2COS_DISABLE \
14502 * When this bit is set to '1', the IP DSCP to CoS mapping is
14503 * requested to be disabled.
14505 #define HWRM_PORT_MAC_CFG_INPUT_FLAGS_IP_DSCP2COS_DISABLE \
14508 * When this bit is set to '1', and the ptp_tx_ts_capture_enable
14509 * bit is set, then the device uses one step Tx timestamping.
14510 * This bit is temporary and used for experimental purposes.
14512 #define HWRM_PORT_MAC_CFG_INPUT_FLAGS_PTP_ONE_STEP_TX_TS \
14516 * This bit must be '1' for the ipg field to be
14519 #define HWRM_PORT_MAC_CFG_INPUT_ENABLES_IPG \
14522 * This bit must be '1' for the lpbk field to be
14525 #define HWRM_PORT_MAC_CFG_INPUT_ENABLES_LPBK \
14528 * This bit must be '1' for the vlan_pri2cos_map_pri field to be
14531 #define HWRM_PORT_MAC_CFG_INPUT_ENABLES_VLAN_PRI2COS_MAP_PRI \
14534 * This bit must be '1' for the tunnel_pri2cos_map_pri field to be
14537 #define HWRM_PORT_MAC_CFG_INPUT_ENABLES_TUNNEL_PRI2COS_MAP_PRI \
14540 * This bit must be '1' for the dscp2cos_map_pri field to be
14543 #define HWRM_PORT_MAC_CFG_INPUT_ENABLES_DSCP2COS_MAP_PRI \
14546 * This bit must be '1' for the rx_ts_capture_ptp_msg_type field to be
14549 #define HWRM_PORT_MAC_CFG_INPUT_ENABLES_RX_TS_CAPTURE_PTP_MSG_TYPE \
14552 * This bit must be '1' for the tx_ts_capture_ptp_msg_type field to be
14555 #define HWRM_PORT_MAC_CFG_INPUT_ENABLES_TX_TS_CAPTURE_PTP_MSG_TYPE \
14558 * This bit must be '1' for the cos_field_cfg field to be
14561 #define HWRM_PORT_MAC_CFG_INPUT_ENABLES_COS_FIELD_CFG \
14564 * This bit must be '1' for the ptp_freq_adj_ppb field to be
14567 #define HWRM_PORT_MAC_CFG_INPUT_ENABLES_PTP_FREQ_ADJ_PPB \
14569 /* Port ID of port that is to be configured. */
14572 * This value is used to configure the minimum IPG that will
14573 * be sent between packets by this port.
14576 /* This value controls the loopback setting for the MAC. */
14578 /* No loopback is selected. Normal operation. */
14579 #define HWRM_PORT_MAC_CFG_INPUT_LPBK_NONE UINT32_C(0x0)
14581 * The HW will be configured with local loopback such that
14582 * host data is sent back to the host without modification.
14584 #define HWRM_PORT_MAC_CFG_INPUT_LPBK_LOCAL UINT32_C(0x1)
14586 * The HW will be configured with remote loopback such that
14587 * port logic will send packets back out the transmitter that
14590 #define HWRM_PORT_MAC_CFG_INPUT_LPBK_REMOTE UINT32_C(0x2)
14591 #define HWRM_PORT_MAC_CFG_INPUT_LPBK_LAST \
14592 HWRM_PORT_MAC_CFG_INPUT_LPBK_REMOTE
14594 * This value controls the priority setting of VLAN PRI to CoS
14595 * mapping based on VLAN Tags of inner packet headers of
14596 * tunneled packets or packet headers of non-tunneled packets.
14598 * # Each XXX_pri variable shall have a unique priority value
14599 * when it is being specified.
14600 * # When comparing priorities of mappings, higher value
14601 * indicates higher priority.
14602 * For example, a value of 0-3 is returned where 0 is being
14603 * the lowest priority and 3 is being the highest priority.
14605 uint8_t vlan_pri2cos_map_pri;
14606 /* Reserved field. */
14609 * This value controls the priority setting of VLAN PRI to CoS
14610 * mapping based on VLAN Tags of tunneled header.
14611 * This mapping only applies when tunneled headers
14614 * # Each XXX_pri variable shall have a unique priority value
14615 * when it is being specified.
14616 * # When comparing priorities of mappings, higher value
14617 * indicates higher priority.
14618 * For example, a value of 0-3 is returned where 0 is being
14619 * the lowest priority and 3 is being the highest priority.
14621 uint8_t tunnel_pri2cos_map_pri;
14623 * This value controls the priority setting of IP DSCP to CoS
14624 * mapping based on inner IP header of tunneled packets or
14625 * IP header of non-tunneled packets.
14627 * # Each XXX_pri variable shall have a unique priority value
14628 * when it is being specified.
14629 * # When comparing priorities of mappings, higher value
14630 * indicates higher priority.
14631 * For example, a value of 0-3 is returned where 0 is being
14632 * the lowest priority and 3 is being the highest priority.
14634 uint8_t dscp2pri_map_pri;
14636 * This is a 16-bit bit mask that is used to request a
14637 * specific configuration of time stamp capture of PTP messages
14638 * on the receive side of this port.
14639 * This field shall be ignored if the ptp_rx_ts_capture_enable
14640 * flag is not set in this command.
14641 * Otherwise, if bit 'i' is set, then the HWRM is being
14642 * requested to configure the receive side of the port to
14643 * capture the time stamp of every received PTP message
14644 * with messageType field value set to i.
14646 uint16_t rx_ts_capture_ptp_msg_type;
14648 * This is a 16-bit bit mask that is used to request a
14649 * specific configuration of time stamp capture of PTP messages
14650 * on the transmit side of this port.
14651 * This field shall be ignored if the ptp_tx_ts_capture_enable
14652 * flag is not set in this command.
14653 * Otherwise, if bit 'i' is set, then the HWRM is being
14654 * requested to configure the transmit sied of the port to
14655 * capture the time stamp of every transmitted PTP message
14656 * with messageType field value set to i.
14658 uint16_t tx_ts_capture_ptp_msg_type;
14659 /* Configuration of CoS fields. */
14660 uint8_t cos_field_cfg;
14662 #define HWRM_PORT_MAC_CFG_INPUT_COS_FIELD_CFG_RSVD1 \
14665 * This field is used to specify selection of VLAN PRI value
14666 * based on whether one or two VLAN Tags are present in
14667 * the inner packet headers of tunneled packets or
14668 * non-tunneled packets.
14669 * This field is valid only if inner VLAN PRI to CoS mapping
14671 * If VLAN PRI to CoS mapping is not enabled, then this
14672 * field shall be ignored.
14674 #define HWRM_PORT_MAC_CFG_INPUT_COS_FIELD_CFG_VLAN_PRI_SEL_MASK \
14676 #define HWRM_PORT_MAC_CFG_INPUT_COS_FIELD_CFG_VLAN_PRI_SEL_SFT \
14679 * Select inner VLAN PRI when 1 or 2 VLAN Tags are
14680 * present in the inner packet headers
14682 #define HWRM_PORT_MAC_CFG_INPUT_COS_FIELD_CFG_VLAN_PRI_SEL_INNERMOST \
14683 (UINT32_C(0x0) << 1)
14685 * Select outer VLAN Tag PRI when 2 VLAN Tags are
14686 * present in the inner packet headers.
14687 * No VLAN PRI shall be selected for this configuration
14688 * if only one VLAN Tag is present in the inner
14691 #define HWRM_PORT_MAC_CFG_INPUT_COS_FIELD_CFG_VLAN_PRI_SEL_OUTER \
14692 (UINT32_C(0x1) << 1)
14694 * Select outermost VLAN PRI when 1 or 2 VLAN Tags
14695 * are present in the inner packet headers
14697 #define HWRM_PORT_MAC_CFG_INPUT_COS_FIELD_CFG_VLAN_PRI_SEL_OUTERMOST \
14698 (UINT32_C(0x2) << 1)
14700 #define HWRM_PORT_MAC_CFG_INPUT_COS_FIELD_CFG_VLAN_PRI_SEL_UNSPECIFIED \
14701 (UINT32_C(0x3) << 1)
14702 #define HWRM_PORT_MAC_CFG_INPUT_COS_FIELD_CFG_VLAN_PRI_SEL_LAST \
14703 HWRM_PORT_MAC_CFG_INPUT_COS_FIELD_CFG_VLAN_PRI_SEL_UNSPECIFIED
14705 * This field is used to specify selection of tunnel VLAN
14706 * PRI value based on whether one or two VLAN Tags are
14707 * present in tunnel headers.
14708 * This field is valid only if tunnel VLAN PRI to CoS mapping
14710 * If tunnel VLAN PRI to CoS mapping is not enabled, then this
14711 * field shall be ignored.
14713 #define HWRM_PORT_MAC_CFG_INPUT_COS_FIELD_CFG_T_VLAN_PRI_SEL_MASK \
14715 #define HWRM_PORT_MAC_CFG_INPUT_COS_FIELD_CFG_T_VLAN_PRI_SEL_SFT \
14718 * Select inner VLAN PRI when 1 or 2 VLAN Tags are
14719 * present in the tunnel packet headers
14721 #define HWRM_PORT_MAC_CFG_INPUT_COS_FIELD_CFG_T_VLAN_PRI_SEL_INNERMOST \
14722 (UINT32_C(0x0) << 3)
14724 * Select outer VLAN Tag PRI when 2 VLAN Tags are
14725 * present in the tunnel packet headers.
14726 * No tunnel VLAN PRI shall be selected for this
14727 * configuration if only one VLAN Tag is present in
14728 * the tunnel packet headers.
14730 #define HWRM_PORT_MAC_CFG_INPUT_COS_FIELD_CFG_T_VLAN_PRI_SEL_OUTER \
14731 (UINT32_C(0x1) << 3)
14733 * Select outermost VLAN PRI when 1 or 2 VLAN Tags
14734 * are present in the tunnel packet headers
14736 #define HWRM_PORT_MAC_CFG_INPUT_COS_FIELD_CFG_T_VLAN_PRI_SEL_OUTERMOST \
14737 (UINT32_C(0x2) << 3)
14739 #define HWRM_PORT_MAC_CFG_INPUT_COS_FIELD_CFG_T_VLAN_PRI_SEL_UNSPECIFIED \
14740 (UINT32_C(0x3) << 3)
14741 #define HWRM_PORT_MAC_CFG_INPUT_COS_FIELD_CFG_T_VLAN_PRI_SEL_LAST \
14742 HWRM_PORT_MAC_CFG_INPUT_COS_FIELD_CFG_T_VLAN_PRI_SEL_UNSPECIFIED
14744 * This field shall be used to provide default CoS value
14745 * that has been configured on this port.
14746 * This field is valid only if default CoS mapping
14748 * If default CoS mapping is not enabled, then this
14749 * field shall be ignored.
14751 #define HWRM_PORT_MAC_CFG_INPUT_COS_FIELD_CFG_DEFAULT_COS_MASK \
14753 #define HWRM_PORT_MAC_CFG_INPUT_COS_FIELD_CFG_DEFAULT_COS_SFT \
14755 uint8_t unused_0[3];
14757 * This signed field specifies by how much to adjust the frequency
14758 * of sync timer updates (measured in parts per billion).
14760 int32_t ptp_freq_adj_ppb;
14761 uint8_t unused_1[4];
14762 } __attribute__((packed));
14764 /* hwrm_port_mac_cfg_output (size:128b/16B) */
14765 struct hwrm_port_mac_cfg_output {
14766 /* The specific error status for the command. */
14767 uint16_t error_code;
14768 /* The HWRM command request type. */
14770 /* The sequence ID from the original command. */
14772 /* The length of the response data in number of bytes. */
14775 * This is the configured maximum length of Ethernet packet
14776 * payload that is allowed to be received on the port.
14777 * This value does not include the number of bytes used by
14778 * Ethernet header and trailer (CRC).
14782 * This is the configured maximum length of Ethernet packet
14783 * payload that is allowed to be transmitted on the port.
14784 * This value does not include the number of bytes used by
14785 * Ethernet header and trailer (CRC).
14788 /* Current configuration of the IPG value. */
14790 /* Current value of the loopback value. */
14792 /* No loopback is selected. Normal operation. */
14793 #define HWRM_PORT_MAC_CFG_OUTPUT_LPBK_NONE UINT32_C(0x0)
14795 * The HW will be configured with local loopback such that
14796 * host data is sent back to the host without modification.
14798 #define HWRM_PORT_MAC_CFG_OUTPUT_LPBK_LOCAL UINT32_C(0x1)
14800 * The HW will be configured with remote loopback such that
14801 * port logic will send packets back out the transmitter that
14804 #define HWRM_PORT_MAC_CFG_OUTPUT_LPBK_REMOTE UINT32_C(0x2)
14805 #define HWRM_PORT_MAC_CFG_OUTPUT_LPBK_LAST \
14806 HWRM_PORT_MAC_CFG_OUTPUT_LPBK_REMOTE
14809 * This field is used in Output records to indicate that the output
14810 * is completely written to RAM. This field should be read as '1'
14811 * to indicate that the output has been completely written.
14812 * When writing a command completion or response to an internal processor,
14813 * the order of writes has to be such that this field is written last.
14816 } __attribute__((packed));
14818 /**********************
14819 * hwrm_port_mac_qcfg *
14820 **********************/
14823 /* hwrm_port_mac_qcfg_input (size:192b/24B) */
14824 struct hwrm_port_mac_qcfg_input {
14825 /* The HWRM command request type. */
14828 * The completion ring to send the completion event on. This should
14829 * be the NQ ID returned from the `nq_alloc` HWRM command.
14831 uint16_t cmpl_ring;
14833 * The sequence ID is used by the driver for tracking multiple
14834 * commands. This ID is treated as opaque data by the firmware and
14835 * the value is returned in the `hwrm_resp_hdr` upon completion.
14839 * The target ID of the command:
14840 * * 0x0-0xFFF8 - The function ID
14841 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
14842 * * 0xFFFD - Reserved for user-space HWRM interface
14845 uint16_t target_id;
14847 * A physical address pointer pointing to a host buffer that the
14848 * command's response data will be written. This can be either a host
14849 * physical address (HPA) or a guest physical address (GPA) and must
14850 * point to a physically contiguous block of memory.
14852 uint64_t resp_addr;
14853 /* Port ID of port that is to be configured. */
14855 uint8_t unused_0[6];
14856 } __attribute__((packed));
14858 /* hwrm_port_mac_qcfg_output (size:192b/24B) */
14859 struct hwrm_port_mac_qcfg_output {
14860 /* The specific error status for the command. */
14861 uint16_t error_code;
14862 /* The HWRM command request type. */
14864 /* The sequence ID from the original command. */
14866 /* The length of the response data in number of bytes. */
14869 * This is the configured maximum length of Ethernet packet
14870 * payload that is allowed to be received on the port.
14871 * This value does not include the number of bytes used by the
14872 * Ethernet header and trailer (CRC).
14876 * This is the configured maximum length of Ethernet packet
14877 * payload that is allowed to be transmitted on the port.
14878 * This value does not include the number of bytes used by the
14879 * Ethernet header and trailer (CRC).
14883 * The minimum IPG that will
14884 * be sent between packets by this port.
14887 /* The loopback setting for the MAC. */
14889 /* No loopback is selected. Normal operation. */
14890 #define HWRM_PORT_MAC_QCFG_OUTPUT_LPBK_NONE UINT32_C(0x0)
14892 * The HW will be configured with local loopback such that
14893 * host data is sent back to the host without modification.
14895 #define HWRM_PORT_MAC_QCFG_OUTPUT_LPBK_LOCAL UINT32_C(0x1)
14897 * The HW will be configured with remote loopback such that
14898 * port logic will send packets back out the transmitter that
14901 #define HWRM_PORT_MAC_QCFG_OUTPUT_LPBK_REMOTE UINT32_C(0x2)
14902 #define HWRM_PORT_MAC_QCFG_OUTPUT_LPBK_LAST \
14903 HWRM_PORT_MAC_QCFG_OUTPUT_LPBK_REMOTE
14905 * Priority setting for VLAN PRI to CoS mapping.
14906 * # Each XXX_pri variable shall have a unique priority value
14907 * when it is being used.
14908 * # When comparing priorities of mappings, higher value
14909 * indicates higher priority.
14910 * For example, a value of 0-3 is returned where 0 is being
14911 * the lowest priority and 3 is being the highest priority.
14912 * # If the correspoding CoS mapping is not enabled, then this
14913 * field should be ignored.
14914 * # This value indicates the normalized priority value retained
14917 uint8_t vlan_pri2cos_map_pri;
14919 * In this field, a number of CoS mappings related flags
14920 * are used to indicate configured CoS mappings.
14924 * When this bit is set to '1', the inner VLAN PRI to CoS mapping
14927 #define HWRM_PORT_MAC_QCFG_OUTPUT_FLAGS_VLAN_PRI2COS_ENABLE \
14930 * When this bit is set to '1', tunnel VLAN PRI field to
14931 * CoS mapping is enabled.
14933 #define HWRM_PORT_MAC_QCFG_OUTPUT_FLAGS_TUNNEL_PRI2COS_ENABLE \
14936 * When this bit is set to '1', the IP DSCP to CoS mapping is
14939 #define HWRM_PORT_MAC_QCFG_OUTPUT_FLAGS_IP_DSCP2COS_ENABLE \
14942 * When this bit is '1', the Out-Of-Box WoL is enabled on this
14945 #define HWRM_PORT_MAC_QCFG_OUTPUT_FLAGS_OOB_WOL_ENABLE \
14947 /* When this bit is '1', PTP is enabled for RX on this port. */
14948 #define HWRM_PORT_MAC_QCFG_OUTPUT_FLAGS_PTP_RX_TS_CAPTURE_ENABLE \
14950 /* When this bit is '1', PTP is enabled for TX on this port. */
14951 #define HWRM_PORT_MAC_QCFG_OUTPUT_FLAGS_PTP_TX_TS_CAPTURE_ENABLE \
14954 * Priority setting for tunnel VLAN PRI to CoS mapping.
14955 * # Each XXX_pri variable shall have a unique priority value
14956 * when it is being used.
14957 * # When comparing priorities of mappings, higher value
14958 * indicates higher priority.
14959 * For example, a value of 0-3 is returned where 0 is being
14960 * the lowest priority and 3 is being the highest priority.
14961 * # If the correspoding CoS mapping is not enabled, then this
14962 * field should be ignored.
14963 * # This value indicates the normalized priority value retained
14966 uint8_t tunnel_pri2cos_map_pri;
14968 * Priority setting for DSCP to PRI mapping.
14969 * # Each XXX_pri variable shall have a unique priority value
14970 * when it is being used.
14971 * # When comparing priorities of mappings, higher value
14972 * indicates higher priority.
14973 * For example, a value of 0-3 is returned where 0 is being
14974 * the lowest priority and 3 is being the highest priority.
14975 * # If the correspoding CoS mapping is not enabled, then this
14976 * field should be ignored.
14977 * # This value indicates the normalized priority value retained
14980 uint8_t dscp2pri_map_pri;
14982 * This is a 16-bit bit mask that represents the
14983 * current configuration of time stamp capture of PTP messages
14984 * on the receive side of this port.
14985 * If bit 'i' is set, then the receive side of the port
14986 * is configured to capture the time stamp of every
14987 * received PTP message with messageType field value set
14989 * If all bits are set to 0 (i.e. field value set 0),
14990 * then the receive side of the port is not configured
14991 * to capture timestamp for PTP messages.
14992 * If all bits are set to 1, then the receive side of the
14993 * port is configured to capture timestamp for all PTP
14996 uint16_t rx_ts_capture_ptp_msg_type;
14998 * This is a 16-bit bit mask that represents the
14999 * current configuration of time stamp capture of PTP messages
15000 * on the transmit side of this port.
15001 * If bit 'i' is set, then the transmit side of the port
15002 * is configured to capture the time stamp of every
15003 * received PTP message with messageType field value set
15005 * If all bits are set to 0 (i.e. field value set 0),
15006 * then the transmit side of the port is not configured
15007 * to capture timestamp for PTP messages.
15008 * If all bits are set to 1, then the transmit side of the
15009 * port is configured to capture timestamp for all PTP
15012 uint16_t tx_ts_capture_ptp_msg_type;
15013 /* Configuration of CoS fields. */
15014 uint8_t cos_field_cfg;
15016 #define HWRM_PORT_MAC_QCFG_OUTPUT_COS_FIELD_CFG_RSVD \
15019 * This field is used for selecting VLAN PRI value
15020 * based on whether one or two VLAN Tags are present in
15021 * the inner packet headers of tunneled packets or
15022 * non-tunneled packets.
15024 #define HWRM_PORT_MAC_QCFG_OUTPUT_COS_FIELD_CFG_VLAN_PRI_SEL_MASK \
15026 #define HWRM_PORT_MAC_QCFG_OUTPUT_COS_FIELD_CFG_VLAN_PRI_SEL_SFT \
15029 * Select inner VLAN PRI when 1 or 2 VLAN Tags are
15030 * present in the inner packet headers
15032 #define HWRM_PORT_MAC_QCFG_OUTPUT_COS_FIELD_CFG_VLAN_PRI_SEL_INNERMOST \
15033 (UINT32_C(0x0) << 1)
15035 * Select outer VLAN Tag PRI when 2 VLAN Tags are
15036 * present in the inner packet headers.
15037 * No VLAN PRI is selected for this configuration
15038 * if only one VLAN Tag is present in the inner
15041 #define HWRM_PORT_MAC_QCFG_OUTPUT_COS_FIELD_CFG_VLAN_PRI_SEL_OUTER \
15042 (UINT32_C(0x1) << 1)
15044 * Select outermost VLAN PRI when 1 or 2 VLAN Tags
15045 * are present in the inner packet headers
15047 #define HWRM_PORT_MAC_QCFG_OUTPUT_COS_FIELD_CFG_VLAN_PRI_SEL_OUTERMOST \
15048 (UINT32_C(0x2) << 1)
15050 #define HWRM_PORT_MAC_QCFG_OUTPUT_COS_FIELD_CFG_VLAN_PRI_SEL_UNSPECIFIED \
15051 (UINT32_C(0x3) << 1)
15052 #define HWRM_PORT_MAC_QCFG_OUTPUT_COS_FIELD_CFG_VLAN_PRI_SEL_LAST \
15053 HWRM_PORT_MAC_QCFG_OUTPUT_COS_FIELD_CFG_VLAN_PRI_SEL_UNSPECIFIED
15055 * This field is used for selecting tunnel VLAN PRI value
15056 * based on whether one or two VLAN Tags are present in
15057 * the tunnel headers of tunneled packets. This selection
15058 * does not apply to non-tunneled packets.
15060 #define HWRM_PORT_MAC_QCFG_OUTPUT_COS_FIELD_CFG_T_VLAN_PRI_SEL_MASK \
15062 #define HWRM_PORT_MAC_QCFG_OUTPUT_COS_FIELD_CFG_T_VLAN_PRI_SEL_SFT \
15065 * Select inner VLAN PRI when 1 or 2 VLAN Tags are
15066 * present in the tunnel packet headers
15068 #define HWRM_PORT_MAC_QCFG_OUTPUT_COS_FIELD_CFG_T_VLAN_PRI_SEL_INNERMOST \
15069 (UINT32_C(0x0) << 3)
15071 * Select outer VLAN Tag PRI when 2 VLAN Tags are
15072 * present in the tunnel packet headers.
15073 * No VLAN PRI is selected for this configuration
15074 * if only one VLAN Tag is present in the tunnel
15077 #define HWRM_PORT_MAC_QCFG_OUTPUT_COS_FIELD_CFG_T_VLAN_PRI_SEL_OUTER \
15078 (UINT32_C(0x1) << 3)
15080 * Select outermost VLAN PRI when 1 or 2 VLAN Tags
15081 * are present in the tunnel packet headers
15083 #define HWRM_PORT_MAC_QCFG_OUTPUT_COS_FIELD_CFG_T_VLAN_PRI_SEL_OUTERMOST \
15084 (UINT32_C(0x2) << 3)
15086 #define HWRM_PORT_MAC_QCFG_OUTPUT_COS_FIELD_CFG_T_VLAN_PRI_SEL_UNSPECIFIED \
15087 (UINT32_C(0x3) << 3)
15088 #define HWRM_PORT_MAC_QCFG_OUTPUT_COS_FIELD_CFG_T_VLAN_PRI_SEL_LAST \
15089 HWRM_PORT_MAC_QCFG_OUTPUT_COS_FIELD_CFG_T_VLAN_PRI_SEL_UNSPECIFIED
15091 * This field is used to provide default CoS value that
15092 * has been configured on this port.
15094 #define HWRM_PORT_MAC_QCFG_OUTPUT_COS_FIELD_CFG_DEFAULT_COS_MASK \
15096 #define HWRM_PORT_MAC_QCFG_OUTPUT_COS_FIELD_CFG_DEFAULT_COS_SFT \
15099 * This field is used in Output records to indicate that the output
15100 * is completely written to RAM. This field should be read as '1'
15101 * to indicate that the output has been completely written.
15102 * When writing a command completion or response to an internal processor,
15103 * the order of writes has to be such that this field is written last.
15106 } __attribute__((packed));
15108 /**************************
15109 * hwrm_port_mac_ptp_qcfg *
15110 **************************/
15113 /* hwrm_port_mac_ptp_qcfg_input (size:192b/24B) */
15114 struct hwrm_port_mac_ptp_qcfg_input {
15115 /* The HWRM command request type. */
15118 * The completion ring to send the completion event on. This should
15119 * be the NQ ID returned from the `nq_alloc` HWRM command.
15121 uint16_t cmpl_ring;
15123 * The sequence ID is used by the driver for tracking multiple
15124 * commands. This ID is treated as opaque data by the firmware and
15125 * the value is returned in the `hwrm_resp_hdr` upon completion.
15129 * The target ID of the command:
15130 * * 0x0-0xFFF8 - The function ID
15131 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
15132 * * 0xFFFD - Reserved for user-space HWRM interface
15135 uint16_t target_id;
15137 * A physical address pointer pointing to a host buffer that the
15138 * command's response data will be written. This can be either a host
15139 * physical address (HPA) or a guest physical address (GPA) and must
15140 * point to a physically contiguous block of memory.
15142 uint64_t resp_addr;
15143 /* Port ID of port that is being queried. */
15145 uint8_t unused_0[6];
15146 } __attribute__((packed));
15148 /* hwrm_port_mac_ptp_qcfg_output (size:640b/80B) */
15149 struct hwrm_port_mac_ptp_qcfg_output {
15150 /* The specific error status for the command. */
15151 uint16_t error_code;
15152 /* The HWRM command request type. */
15154 /* The sequence ID from the original command. */
15156 /* The length of the response data in number of bytes. */
15159 * In this field, a number of PTP related flags
15160 * are used to indicate configured PTP capabilities.
15164 * When this bit is set to '1', the PTP related registers are
15165 * directly accessible by the host.
15167 #define HWRM_PORT_MAC_PTP_QCFG_OUTPUT_FLAGS_DIRECT_ACCESS \
15170 * When this bit is set to '1', the PTP information is accessible
15171 * via HWRM commands.
15173 #define HWRM_PORT_MAC_PTP_QCFG_OUTPUT_FLAGS_HWRM_ACCESS \
15176 * When this bit is set to '1', the device supports one-step
15179 #define HWRM_PORT_MAC_PTP_QCFG_OUTPUT_FLAGS_ONE_STEP_TX_TS \
15181 uint8_t unused_0[3];
15182 /* Offset of the PTP register for the lower 32 bits of timestamp for RX. */
15183 uint32_t rx_ts_reg_off_lower;
15184 /* Offset of the PTP register for the upper 32 bits of timestamp for RX. */
15185 uint32_t rx_ts_reg_off_upper;
15186 /* Offset of the PTP register for the sequence ID for RX. */
15187 uint32_t rx_ts_reg_off_seq_id;
15188 /* Offset of the first PTP source ID for RX. */
15189 uint32_t rx_ts_reg_off_src_id_0;
15190 /* Offset of the second PTP source ID for RX. */
15191 uint32_t rx_ts_reg_off_src_id_1;
15192 /* Offset of the third PTP source ID for RX. */
15193 uint32_t rx_ts_reg_off_src_id_2;
15194 /* Offset of the domain ID for RX. */
15195 uint32_t rx_ts_reg_off_domain_id;
15196 /* Offset of the PTP FIFO register for RX. */
15197 uint32_t rx_ts_reg_off_fifo;
15198 /* Offset of the PTP advance FIFO register for RX. */
15199 uint32_t rx_ts_reg_off_fifo_adv;
15200 /* PTP timestamp granularity for RX. */
15201 uint32_t rx_ts_reg_off_granularity;
15202 /* Offset of the PTP register for the lower 32 bits of timestamp for TX. */
15203 uint32_t tx_ts_reg_off_lower;
15204 /* Offset of the PTP register for the upper 32 bits of timestamp for TX. */
15205 uint32_t tx_ts_reg_off_upper;
15206 /* Offset of the PTP register for the sequence ID for TX. */
15207 uint32_t tx_ts_reg_off_seq_id;
15208 /* Offset of the PTP FIFO register for TX. */
15209 uint32_t tx_ts_reg_off_fifo;
15210 /* PTP timestamp granularity for TX. */
15211 uint32_t tx_ts_reg_off_granularity;
15212 uint8_t unused_1[7];
15214 * This field is used in Output records to indicate that the output
15215 * is completely written to RAM. This field should be read as '1'
15216 * to indicate that the output has been completely written.
15217 * When writing a command completion or response to an internal processor,
15218 * the order of writes has to be such that this field is written last.
15221 } __attribute__((packed));
15223 /* Port Tx Statistics Formats */
15224 /* tx_port_stats (size:3264b/408B) */
15225 struct tx_port_stats {
15226 /* Total Number of 64 Bytes frames transmitted */
15227 uint64_t tx_64b_frames;
15228 /* Total Number of 65-127 Bytes frames transmitted */
15229 uint64_t tx_65b_127b_frames;
15230 /* Total Number of 128-255 Bytes frames transmitted */
15231 uint64_t tx_128b_255b_frames;
15232 /* Total Number of 256-511 Bytes frames transmitted */
15233 uint64_t tx_256b_511b_frames;
15234 /* Total Number of 512-1023 Bytes frames transmitted */
15235 uint64_t tx_512b_1023b_frames;
15236 /* Total Number of 1024-1518 Bytes frames transmitted */
15237 uint64_t tx_1024b_1518b_frames;
15239 * Total Number of each good VLAN (exludes FCS errors)
15240 * frame transmitted which is 1519 to 1522 bytes in length
15241 * inclusive (excluding framing bits but including FCS bytes).
15243 uint64_t tx_good_vlan_frames;
15244 /* Total Number of 1519-2047 Bytes frames transmitted */
15245 uint64_t tx_1519b_2047b_frames;
15246 /* Total Number of 2048-4095 Bytes frames transmitted */
15247 uint64_t tx_2048b_4095b_frames;
15248 /* Total Number of 4096-9216 Bytes frames transmitted */
15249 uint64_t tx_4096b_9216b_frames;
15250 /* Total Number of 9217-16383 Bytes frames transmitted */
15251 uint64_t tx_9217b_16383b_frames;
15252 /* Total Number of good frames transmitted */
15253 uint64_t tx_good_frames;
15254 /* Total Number of frames transmitted */
15255 uint64_t tx_total_frames;
15256 /* Total number of unicast frames transmitted */
15257 uint64_t tx_ucast_frames;
15258 /* Total number of multicast frames transmitted */
15259 uint64_t tx_mcast_frames;
15260 /* Total number of broadcast frames transmitted */
15261 uint64_t tx_bcast_frames;
15262 /* Total number of PAUSE control frames transmitted */
15263 uint64_t tx_pause_frames;
15265 * Total number of PFC/per-priority PAUSE
15266 * control frames transmitted
15268 uint64_t tx_pfc_frames;
15269 /* Total number of jabber frames transmitted */
15270 uint64_t tx_jabber_frames;
15271 /* Total number of frames transmitted with FCS error */
15272 uint64_t tx_fcs_err_frames;
15273 /* Total number of control frames transmitted */
15274 uint64_t tx_control_frames;
15275 /* Total number of over-sized frames transmitted */
15276 uint64_t tx_oversz_frames;
15277 /* Total number of frames with single deferral */
15278 uint64_t tx_single_dfrl_frames;
15279 /* Total number of frames with multiple deferrals */
15280 uint64_t tx_multi_dfrl_frames;
15281 /* Total number of frames with single collision */
15282 uint64_t tx_single_coll_frames;
15283 /* Total number of frames with multiple collisions */
15284 uint64_t tx_multi_coll_frames;
15285 /* Total number of frames with late collisions */
15286 uint64_t tx_late_coll_frames;
15287 /* Total number of frames with excessive collisions */
15288 uint64_t tx_excessive_coll_frames;
15289 /* Total number of fragmented frames transmitted */
15290 uint64_t tx_frag_frames;
15291 /* Total number of transmit errors */
15293 /* Total number of single VLAN tagged frames transmitted */
15294 uint64_t tx_tagged_frames;
15295 /* Total number of double VLAN tagged frames transmitted */
15296 uint64_t tx_dbl_tagged_frames;
15297 /* Total number of runt frames transmitted */
15298 uint64_t tx_runt_frames;
15299 /* Total number of TX FIFO under runs */
15300 uint64_t tx_fifo_underruns;
15302 * Total number of PFC frames with PFC enabled bit for
15303 * Pri 0 transmitted
15305 uint64_t tx_pfc_ena_frames_pri0;
15307 * Total number of PFC frames with PFC enabled bit for
15308 * Pri 1 transmitted
15310 uint64_t tx_pfc_ena_frames_pri1;
15312 * Total number of PFC frames with PFC enabled bit for
15313 * Pri 2 transmitted
15315 uint64_t tx_pfc_ena_frames_pri2;
15317 * Total number of PFC frames with PFC enabled bit for
15318 * Pri 3 transmitted
15320 uint64_t tx_pfc_ena_frames_pri3;
15322 * Total number of PFC frames with PFC enabled bit for
15323 * Pri 4 transmitted
15325 uint64_t tx_pfc_ena_frames_pri4;
15327 * Total number of PFC frames with PFC enabled bit for
15328 * Pri 5 transmitted
15330 uint64_t tx_pfc_ena_frames_pri5;
15332 * Total number of PFC frames with PFC enabled bit for
15333 * Pri 6 transmitted
15335 uint64_t tx_pfc_ena_frames_pri6;
15337 * Total number of PFC frames with PFC enabled bit for
15338 * Pri 7 transmitted
15340 uint64_t tx_pfc_ena_frames_pri7;
15341 /* Total number of EEE LPI Events on TX */
15342 uint64_t tx_eee_lpi_events;
15343 /* EEE LPI Duration Counter on TX */
15344 uint64_t tx_eee_lpi_duration;
15346 * Total number of Link Level Flow Control (LLFC) messages
15349 uint64_t tx_llfc_logical_msgs;
15350 /* Total number of HCFC messages transmitted */
15351 uint64_t tx_hcfc_msgs;
15352 /* Total number of TX collisions */
15353 uint64_t tx_total_collisions;
15354 /* Total number of transmitted bytes */
15356 /* Total number of end-to-end HOL frames */
15357 uint64_t tx_xthol_frames;
15358 /* Total Tx Drops per Port reported by STATS block */
15359 uint64_t tx_stat_discard;
15360 /* Total Tx Error Drops per Port reported by STATS block */
15361 uint64_t tx_stat_error;
15362 } __attribute__((packed));
15364 /* Port Rx Statistics Formats */
15365 /* rx_port_stats (size:4224b/528B) */
15366 struct rx_port_stats {
15367 /* Total Number of 64 Bytes frames received */
15368 uint64_t rx_64b_frames;
15369 /* Total Number of 65-127 Bytes frames received */
15370 uint64_t rx_65b_127b_frames;
15371 /* Total Number of 128-255 Bytes frames received */
15372 uint64_t rx_128b_255b_frames;
15373 /* Total Number of 256-511 Bytes frames received */
15374 uint64_t rx_256b_511b_frames;
15375 /* Total Number of 512-1023 Bytes frames received */
15376 uint64_t rx_512b_1023b_frames;
15377 /* Total Number of 1024-1518 Bytes frames received */
15378 uint64_t rx_1024b_1518b_frames;
15380 * Total Number of each good VLAN (exludes FCS errors)
15381 * frame received which is 1519 to 1522 bytes in length
15382 * inclusive (excluding framing bits but including FCS bytes).
15384 uint64_t rx_good_vlan_frames;
15385 /* Total Number of 1519-2047 Bytes frames received */
15386 uint64_t rx_1519b_2047b_frames;
15387 /* Total Number of 2048-4095 Bytes frames received */
15388 uint64_t rx_2048b_4095b_frames;
15389 /* Total Number of 4096-9216 Bytes frames received */
15390 uint64_t rx_4096b_9216b_frames;
15391 /* Total Number of 9217-16383 Bytes frames received */
15392 uint64_t rx_9217b_16383b_frames;
15393 /* Total number of frames received */
15394 uint64_t rx_total_frames;
15395 /* Total number of unicast frames received */
15396 uint64_t rx_ucast_frames;
15397 /* Total number of multicast frames received */
15398 uint64_t rx_mcast_frames;
15399 /* Total number of broadcast frames received */
15400 uint64_t rx_bcast_frames;
15401 /* Total number of received frames with FCS error */
15402 uint64_t rx_fcs_err_frames;
15403 /* Total number of control frames received */
15404 uint64_t rx_ctrl_frames;
15405 /* Total number of PAUSE frames received */
15406 uint64_t rx_pause_frames;
15407 /* Total number of PFC frames received */
15408 uint64_t rx_pfc_frames;
15410 * Total number of frames received with an unsupported
15413 uint64_t rx_unsupported_opcode_frames;
15415 * Total number of frames received with an unsupported
15416 * DA for pause and PFC
15418 uint64_t rx_unsupported_da_pausepfc_frames;
15419 /* Total number of frames received with an unsupported SA */
15420 uint64_t rx_wrong_sa_frames;
15421 /* Total number of received packets with alignment error */
15422 uint64_t rx_align_err_frames;
15423 /* Total number of received frames with out-of-range length */
15424 uint64_t rx_oor_len_frames;
15425 /* Total number of received frames with error termination */
15426 uint64_t rx_code_err_frames;
15428 * Total number of received frames with a false carrier is
15429 * detected during idle, as defined by RX_ER samples active
15430 * and RXD is 0xE. The event is reported along with the
15431 * statistics generated on the next received frame. Only
15432 * one false carrier condition can be detected and logged
15435 * Carrier event, valid for 10M/100M speed modes only.
15437 uint64_t rx_false_carrier_frames;
15438 /* Total number of over-sized frames received */
15439 uint64_t rx_ovrsz_frames;
15440 /* Total number of jabber packets received */
15441 uint64_t rx_jbr_frames;
15442 /* Total number of received frames with MTU error */
15443 uint64_t rx_mtu_err_frames;
15444 /* Total number of received frames with CRC match */
15445 uint64_t rx_match_crc_frames;
15446 /* Total number of frames received promiscuously */
15447 uint64_t rx_promiscuous_frames;
15449 * Total number of received frames with one or two VLAN
15452 uint64_t rx_tagged_frames;
15453 /* Total number of received frames with two VLAN tags */
15454 uint64_t rx_double_tagged_frames;
15455 /* Total number of truncated frames received */
15456 uint64_t rx_trunc_frames;
15457 /* Total number of good frames (without errors) received */
15458 uint64_t rx_good_frames;
15460 * Total number of received PFC frames with transition from
15461 * XON to XOFF on Pri 0
15463 uint64_t rx_pfc_xon2xoff_frames_pri0;
15465 * Total number of received PFC frames with transition from
15466 * XON to XOFF on Pri 1
15468 uint64_t rx_pfc_xon2xoff_frames_pri1;
15470 * Total number of received PFC frames with transition from
15471 * XON to XOFF on Pri 2
15473 uint64_t rx_pfc_xon2xoff_frames_pri2;
15475 * Total number of received PFC frames with transition from
15476 * XON to XOFF on Pri 3
15478 uint64_t rx_pfc_xon2xoff_frames_pri3;
15480 * Total number of received PFC frames with transition from
15481 * XON to XOFF on Pri 4
15483 uint64_t rx_pfc_xon2xoff_frames_pri4;
15485 * Total number of received PFC frames with transition from
15486 * XON to XOFF on Pri 5
15488 uint64_t rx_pfc_xon2xoff_frames_pri5;
15490 * Total number of received PFC frames with transition from
15491 * XON to XOFF on Pri 6
15493 uint64_t rx_pfc_xon2xoff_frames_pri6;
15495 * Total number of received PFC frames with transition from
15496 * XON to XOFF on Pri 7
15498 uint64_t rx_pfc_xon2xoff_frames_pri7;
15500 * Total number of received PFC frames with PFC enabled
15503 uint64_t rx_pfc_ena_frames_pri0;
15505 * Total number of received PFC frames with PFC enabled
15508 uint64_t rx_pfc_ena_frames_pri1;
15510 * Total number of received PFC frames with PFC enabled
15513 uint64_t rx_pfc_ena_frames_pri2;
15515 * Total number of received PFC frames with PFC enabled
15518 uint64_t rx_pfc_ena_frames_pri3;
15520 * Total number of received PFC frames with PFC enabled
15523 uint64_t rx_pfc_ena_frames_pri4;
15525 * Total number of received PFC frames with PFC enabled
15528 uint64_t rx_pfc_ena_frames_pri5;
15530 * Total number of received PFC frames with PFC enabled
15533 uint64_t rx_pfc_ena_frames_pri6;
15535 * Total number of received PFC frames with PFC enabled
15538 uint64_t rx_pfc_ena_frames_pri7;
15539 /* Total Number of frames received with SCH CRC error */
15540 uint64_t rx_sch_crc_err_frames;
15541 /* Total Number of under-sized frames received */
15542 uint64_t rx_undrsz_frames;
15543 /* Total Number of fragmented frames received */
15544 uint64_t rx_frag_frames;
15545 /* Total number of RX EEE LPI Events */
15546 uint64_t rx_eee_lpi_events;
15547 /* EEE LPI Duration Counter on RX */
15548 uint64_t rx_eee_lpi_duration;
15550 * Total number of physical type Link Level Flow Control
15551 * (LLFC) messages received
15553 uint64_t rx_llfc_physical_msgs;
15555 * Total number of logical type Link Level Flow Control
15556 * (LLFC) messages received
15558 uint64_t rx_llfc_logical_msgs;
15560 * Total number of logical type Link Level Flow Control
15561 * (LLFC) messages received with CRC error
15563 uint64_t rx_llfc_msgs_with_crc_err;
15564 /* Total number of HCFC messages received */
15565 uint64_t rx_hcfc_msgs;
15566 /* Total number of HCFC messages received with CRC error */
15567 uint64_t rx_hcfc_msgs_with_crc_err;
15568 /* Total number of received bytes */
15570 /* Total number of bytes received in runt frames */
15571 uint64_t rx_runt_bytes;
15572 /* Total number of runt frames received */
15573 uint64_t rx_runt_frames;
15574 /* Total Rx Discards per Port reported by STATS block */
15575 uint64_t rx_stat_discard;
15576 uint64_t rx_stat_err;
15577 } __attribute__((packed));
15579 /********************
15580 * hwrm_port_qstats *
15581 ********************/
15584 /* hwrm_port_qstats_input (size:320b/40B) */
15585 struct hwrm_port_qstats_input {
15586 /* The HWRM command request type. */
15589 * The completion ring to send the completion event on. This should
15590 * be the NQ ID returned from the `nq_alloc` HWRM command.
15592 uint16_t cmpl_ring;
15594 * The sequence ID is used by the driver for tracking multiple
15595 * commands. This ID is treated as opaque data by the firmware and
15596 * the value is returned in the `hwrm_resp_hdr` upon completion.
15600 * The target ID of the command:
15601 * * 0x0-0xFFF8 - The function ID
15602 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
15603 * * 0xFFFD - Reserved for user-space HWRM interface
15606 uint16_t target_id;
15608 * A physical address pointer pointing to a host buffer that the
15609 * command's response data will be written. This can be either a host
15610 * physical address (HPA) or a guest physical address (GPA) and must
15611 * point to a physically contiguous block of memory.
15613 uint64_t resp_addr;
15614 /* Port ID of port that is being queried. */
15616 uint8_t unused_0[6];
15618 * This is the host address where
15619 * Tx port statistics will be stored
15621 uint64_t tx_stat_host_addr;
15623 * This is the host address where
15624 * Rx port statistics will be stored
15626 uint64_t rx_stat_host_addr;
15627 } __attribute__((packed));
15629 /* hwrm_port_qstats_output (size:128b/16B) */
15630 struct hwrm_port_qstats_output {
15631 /* The specific error status for the command. */
15632 uint16_t error_code;
15633 /* The HWRM command request type. */
15635 /* The sequence ID from the original command. */
15637 /* The length of the response data in number of bytes. */
15639 /* The size of TX port statistics block in bytes. */
15640 uint16_t tx_stat_size;
15641 /* The size of RX port statistics block in bytes. */
15642 uint16_t rx_stat_size;
15643 uint8_t unused_0[3];
15645 * This field is used in Output records to indicate that the output
15646 * is completely written to RAM. This field should be read as '1'
15647 * to indicate that the output has been completely written.
15648 * When writing a command completion or response to an internal processor,
15649 * the order of writes has to be such that this field is written last.
15652 } __attribute__((packed));
15654 /* Port Tx Statistics extended Formats */
15655 /* tx_port_stats_ext (size:2048b/256B) */
15656 struct tx_port_stats_ext {
15657 /* Total number of tx bytes count on cos queue 0 */
15658 uint64_t tx_bytes_cos0;
15659 /* Total number of tx bytes count on cos queue 1 */
15660 uint64_t tx_bytes_cos1;
15661 /* Total number of tx bytes count on cos queue 2 */
15662 uint64_t tx_bytes_cos2;
15663 /* Total number of tx bytes count on cos queue 3 */
15664 uint64_t tx_bytes_cos3;
15665 /* Total number of tx bytes count on cos queue 4 */
15666 uint64_t tx_bytes_cos4;
15667 /* Total number of tx bytes count on cos queue 5 */
15668 uint64_t tx_bytes_cos5;
15669 /* Total number of tx bytes count on cos queue 6 */
15670 uint64_t tx_bytes_cos6;
15671 /* Total number of tx bytes count on cos queue 7 */
15672 uint64_t tx_bytes_cos7;
15673 /* Total number of tx packets count on cos queue 0 */
15674 uint64_t tx_packets_cos0;
15675 /* Total number of tx packets count on cos queue 1 */
15676 uint64_t tx_packets_cos1;
15677 /* Total number of tx packets count on cos queue 2 */
15678 uint64_t tx_packets_cos2;
15679 /* Total number of tx packets count on cos queue 3 */
15680 uint64_t tx_packets_cos3;
15681 /* Total number of tx packets count on cos queue 4 */
15682 uint64_t tx_packets_cos4;
15683 /* Total number of tx packets count on cos queue 5 */
15684 uint64_t tx_packets_cos5;
15685 /* Total number of tx packets count on cos queue 6 */
15686 uint64_t tx_packets_cos6;
15687 /* Total number of tx packets count on cos queue 7 */
15688 uint64_t tx_packets_cos7;
15689 /* time duration between transmitting a XON -> XOFF and a subsequent XOFF -> XON for priority 0 */
15690 uint64_t pfc_pri0_tx_duration_us;
15691 /* Number of times, a XON -> XOFF and XOFF -> XON transitions occur for priority 0 */
15692 uint64_t pfc_pri0_tx_transitions;
15693 /* time duration between transmitting a XON -> XOFF and a subsequent XOFF -> XON for priority 1 */
15694 uint64_t pfc_pri1_tx_duration_us;
15695 /* Number of times, a XON -> XOFF and XOFF -> XON transitions occur for priority 1 */
15696 uint64_t pfc_pri1_tx_transitions;
15697 /* time duration between transmitting a XON -> XOFF and a subsequent XOFF -> XON for priority 2 */
15698 uint64_t pfc_pri2_tx_duration_us;
15699 /* Number of times, a XON -> XOFF and XOFF -> XON transitions occur for priority 2 */
15700 uint64_t pfc_pri2_tx_transitions;
15701 /* time duration between transmitting a XON -> XOFF and a subsequent XOFF -> XON for priority 3 */
15702 uint64_t pfc_pri3_tx_duration_us;
15703 /* Number of times, a XON -> XOFF and XOFF -> XON transitions occur for priority 3 */
15704 uint64_t pfc_pri3_tx_transitions;
15705 /* time duration between transmitting a XON -> XOFF and a subsequent XOFF -> XON for priority 4 */
15706 uint64_t pfc_pri4_tx_duration_us;
15707 /* Number of times, a XON -> XOFF and XOFF -> XON transitions occur for priority 4 */
15708 uint64_t pfc_pri4_tx_transitions;
15709 /* time duration between transmitting a XON -> XOFF and a subsequent XOFF -> XON for priority 5 */
15710 uint64_t pfc_pri5_tx_duration_us;
15711 /* Number of times, a XON -> XOFF and XOFF -> XON transitions occur for priority 5 */
15712 uint64_t pfc_pri5_tx_transitions;
15713 /* time duration between transmitting a XON -> XOFF and a subsequent XOFF -> XON for priority 6 */
15714 uint64_t pfc_pri6_tx_duration_us;
15715 /* Number of times, a XON -> XOFF and XOFF -> XON transitions occur for priority 6 */
15716 uint64_t pfc_pri6_tx_transitions;
15717 /* time duration between transmitting a XON -> XOFF and a subsequent XOFF -> XON for priority 7 */
15718 uint64_t pfc_pri7_tx_duration_us;
15719 /* Number of times, a XON -> XOFF and XOFF -> XON transitions occur for priority 7 */
15720 uint64_t pfc_pri7_tx_transitions;
15721 } __attribute__((packed));
15723 /* Port Rx Statistics extended Formats */
15724 /* rx_port_stats_ext (size:3648b/456B) */
15725 struct rx_port_stats_ext {
15726 /* Number of times link state changed to down */
15727 uint64_t link_down_events;
15728 /* Number of times the idle rings with pause bit are found */
15729 uint64_t continuous_pause_events;
15730 /* Number of times the active rings pause bit resumed back */
15731 uint64_t resume_pause_events;
15732 /* Number of times, the ROCE cos queue PFC is disabled to avoid pause flood/burst */
15733 uint64_t continuous_roce_pause_events;
15734 /* Number of times, the ROCE cos queue PFC is enabled back */
15735 uint64_t resume_roce_pause_events;
15736 /* Total number of rx bytes count on cos queue 0 */
15737 uint64_t rx_bytes_cos0;
15738 /* Total number of rx bytes count on cos queue 1 */
15739 uint64_t rx_bytes_cos1;
15740 /* Total number of rx bytes count on cos queue 2 */
15741 uint64_t rx_bytes_cos2;
15742 /* Total number of rx bytes count on cos queue 3 */
15743 uint64_t rx_bytes_cos3;
15744 /* Total number of rx bytes count on cos queue 4 */
15745 uint64_t rx_bytes_cos4;
15746 /* Total number of rx bytes count on cos queue 5 */
15747 uint64_t rx_bytes_cos5;
15748 /* Total number of rx bytes count on cos queue 6 */
15749 uint64_t rx_bytes_cos6;
15750 /* Total number of rx bytes count on cos queue 7 */
15751 uint64_t rx_bytes_cos7;
15752 /* Total number of rx packets count on cos queue 0 */
15753 uint64_t rx_packets_cos0;
15754 /* Total number of rx packets count on cos queue 1 */
15755 uint64_t rx_packets_cos1;
15756 /* Total number of rx packets count on cos queue 2 */
15757 uint64_t rx_packets_cos2;
15758 /* Total number of rx packets count on cos queue 3 */
15759 uint64_t rx_packets_cos3;
15760 /* Total number of rx packets count on cos queue 4 */
15761 uint64_t rx_packets_cos4;
15762 /* Total number of rx packets count on cos queue 5 */
15763 uint64_t rx_packets_cos5;
15764 /* Total number of rx packets count on cos queue 6 */
15765 uint64_t rx_packets_cos6;
15766 /* Total number of rx packets count on cos queue 7 */
15767 uint64_t rx_packets_cos7;
15768 /* time duration receiving a XON -> XOFF and a subsequent XOFF -> XON for priority 0 */
15769 uint64_t pfc_pri0_rx_duration_us;
15770 /* Number of times, a XON -> XOFF and XOFF -> XON transitions occur for priority 0 */
15771 uint64_t pfc_pri0_rx_transitions;
15772 /* time duration receiving a XON -> XOFF and a subsequent XOFF -> XON for priority 1 */
15773 uint64_t pfc_pri1_rx_duration_us;
15774 /* Number of times, a XON -> XOFF and XOFF -> XON transitions occur for priority 1 */
15775 uint64_t pfc_pri1_rx_transitions;
15776 /* time duration receiving a XON -> XOFF and a subsequent XOFF -> XON for priority 2 */
15777 uint64_t pfc_pri2_rx_duration_us;
15778 /* Number of times, a XON -> XOFF and XOFF -> XON transitions occur for priority 2 */
15779 uint64_t pfc_pri2_rx_transitions;
15780 /* time duration receiving a XON -> XOFF and a subsequent XOFF -> XON for priority 3 */
15781 uint64_t pfc_pri3_rx_duration_us;
15782 /* Number of times, a XON -> XOFF and XOFF -> XON transitions occur for priority 3 */
15783 uint64_t pfc_pri3_rx_transitions;
15784 /* time duration receiving a XON -> XOFF and a subsequent XOFF -> XON for priority 4 */
15785 uint64_t pfc_pri4_rx_duration_us;
15786 /* Number of times, a XON -> XOFF and XOFF -> XON transitions occur for priority 4 */
15787 uint64_t pfc_pri4_rx_transitions;
15788 /* time duration receiving a XON -> XOFF and a subsequent XOFF -> XON for priority 5 */
15789 uint64_t pfc_pri5_rx_duration_us;
15790 /* Number of times, a XON -> XOFF and XOFF -> XON transitions occur for priority 5 */
15791 uint64_t pfc_pri5_rx_transitions;
15792 /* time duration receiving a XON -> XOFF and a subsequent XOFF -> XON for priority 6 */
15793 uint64_t pfc_pri6_rx_duration_us;
15794 /* Number of times, a XON -> XOFF and XOFF -> XON transitions occur for priority 6 */
15795 uint64_t pfc_pri6_rx_transitions;
15796 /* time duration receiving a XON -> XOFF and a subsequent XOFF -> XON for priority 7 */
15797 uint64_t pfc_pri7_rx_duration_us;
15798 /* Number of times, a XON -> XOFF and XOFF -> XON transitions occur for priority 7 */
15799 uint64_t pfc_pri7_rx_transitions;
15800 /* Total number of received bits */
15802 /* The number of events where the port receive buffer was over 85% full */
15803 uint64_t rx_buffer_passed_threshold;
15805 * The number of symbol errors that wasn't corrected by FEC correction
15808 uint64_t rx_pcs_symbol_err;
15809 /* The number of corrected bits on the port according to active FEC */
15810 uint64_t rx_corrected_bits;
15811 /* Total number of rx discard bytes count on cos queue 0 */
15812 uint64_t rx_discard_bytes_cos0;
15813 /* Total number of rx discard bytes count on cos queue 1 */
15814 uint64_t rx_discard_bytes_cos1;
15815 /* Total number of rx discard bytes count on cos queue 2 */
15816 uint64_t rx_discard_bytes_cos2;
15817 /* Total number of rx discard bytes count on cos queue 3 */
15818 uint64_t rx_discard_bytes_cos3;
15819 /* Total number of rx discard bytes count on cos queue 4 */
15820 uint64_t rx_discard_bytes_cos4;
15821 /* Total number of rx discard bytes count on cos queue 5 */
15822 uint64_t rx_discard_bytes_cos5;
15823 /* Total number of rx discard bytes count on cos queue 6 */
15824 uint64_t rx_discard_bytes_cos6;
15825 /* Total number of rx discard bytes count on cos queue 7 */
15826 uint64_t rx_discard_bytes_cos7;
15827 /* Total number of rx discard packets count on cos queue 0 */
15828 uint64_t rx_discard_packets_cos0;
15829 /* Total number of rx discard packets count on cos queue 1 */
15830 uint64_t rx_discard_packets_cos1;
15831 /* Total number of rx discard packets count on cos queue 2 */
15832 uint64_t rx_discard_packets_cos2;
15833 /* Total number of rx discard packets count on cos queue 3 */
15834 uint64_t rx_discard_packets_cos3;
15835 /* Total number of rx discard packets count on cos queue 4 */
15836 uint64_t rx_discard_packets_cos4;
15837 /* Total number of rx discard packets count on cos queue 5 */
15838 uint64_t rx_discard_packets_cos5;
15839 /* Total number of rx discard packets count on cos queue 6 */
15840 uint64_t rx_discard_packets_cos6;
15841 /* Total number of rx discard packets count on cos queue 7 */
15842 uint64_t rx_discard_packets_cos7;
15843 } __attribute__((packed));
15845 /************************
15846 * hwrm_port_qstats_ext *
15847 ************************/
15850 /* hwrm_port_qstats_ext_input (size:320b/40B) */
15851 struct hwrm_port_qstats_ext_input {
15852 /* The HWRM command request type. */
15855 * The completion ring to send the completion event on. This should
15856 * be the NQ ID returned from the `nq_alloc` HWRM command.
15858 uint16_t cmpl_ring;
15860 * The sequence ID is used by the driver for tracking multiple
15861 * commands. This ID is treated as opaque data by the firmware and
15862 * the value is returned in the `hwrm_resp_hdr` upon completion.
15866 * The target ID of the command:
15867 * * 0x0-0xFFF8 - The function ID
15868 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
15869 * * 0xFFFD - Reserved for user-space HWRM interface
15872 uint16_t target_id;
15874 * A physical address pointer pointing to a host buffer that the
15875 * command's response data will be written. This can be either a host
15876 * physical address (HPA) or a guest physical address (GPA) and must
15877 * point to a physically contiguous block of memory.
15879 uint64_t resp_addr;
15880 /* Port ID of port that is being queried. */
15883 * The size of TX port extended
15884 * statistics block in bytes.
15886 uint16_t tx_stat_size;
15888 * The size of RX port extended
15889 * statistics block in bytes
15891 uint16_t rx_stat_size;
15892 uint8_t unused_0[2];
15894 * This is the host address where
15895 * Tx port statistics will be stored
15897 uint64_t tx_stat_host_addr;
15899 * This is the host address where
15900 * Rx port statistics will be stored
15902 uint64_t rx_stat_host_addr;
15903 } __attribute__((packed));
15905 /* hwrm_port_qstats_ext_output (size:128b/16B) */
15906 struct hwrm_port_qstats_ext_output {
15907 /* The specific error status for the command. */
15908 uint16_t error_code;
15909 /* The HWRM command request type. */
15911 /* The sequence ID from the original command. */
15913 /* The length of the response data in number of bytes. */
15915 /* The size of TX port statistics block in bytes. */
15916 uint16_t tx_stat_size;
15917 /* The size of RX port statistics block in bytes. */
15918 uint16_t rx_stat_size;
15919 /* Total number of active cos queues available. */
15920 uint16_t total_active_cos_queues;
15923 * If set to 1, then this field indicates that clear
15924 * roce specific counters is supported.
15926 #define HWRM_PORT_QSTATS_EXT_OUTPUT_FLAGS_CLEAR_ROCE_COUNTERS_SUPPORTED \
15929 * This field is used in Output records to indicate that the output
15930 * is completely written to RAM. This field should be read as '1'
15931 * to indicate that the output has been completely written.
15932 * When writing a command completion or response to an internal processor,
15933 * the order of writes has to be such that this field is written last.
15936 } __attribute__((packed));
15938 /*************************
15939 * hwrm_port_lpbk_qstats *
15940 *************************/
15943 /* hwrm_port_lpbk_qstats_input (size:128b/16B) */
15944 struct hwrm_port_lpbk_qstats_input {
15945 /* The HWRM command request type. */
15948 * The completion ring to send the completion event on. This should
15949 * be the NQ ID returned from the `nq_alloc` HWRM command.
15951 uint16_t cmpl_ring;
15953 * The sequence ID is used by the driver for tracking multiple
15954 * commands. This ID is treated as opaque data by the firmware and
15955 * the value is returned in the `hwrm_resp_hdr` upon completion.
15959 * The target ID of the command:
15960 * * 0x0-0xFFF8 - The function ID
15961 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
15962 * * 0xFFFD - Reserved for user-space HWRM interface
15965 uint16_t target_id;
15967 * A physical address pointer pointing to a host buffer that the
15968 * command's response data will be written. This can be either a host
15969 * physical address (HPA) or a guest physical address (GPA) and must
15970 * point to a physically contiguous block of memory.
15972 uint64_t resp_addr;
15973 } __attribute__((packed));
15975 /* hwrm_port_lpbk_qstats_output (size:768b/96B) */
15976 struct hwrm_port_lpbk_qstats_output {
15977 /* The specific error status for the command. */
15978 uint16_t error_code;
15979 /* The HWRM command request type. */
15981 /* The sequence ID from the original command. */
15983 /* The length of the response data in number of bytes. */
15985 /* Number of transmitted unicast frames */
15986 uint64_t lpbk_ucast_frames;
15987 /* Number of transmitted multicast frames */
15988 uint64_t lpbk_mcast_frames;
15989 /* Number of transmitted broadcast frames */
15990 uint64_t lpbk_bcast_frames;
15991 /* Number of transmitted bytes for unicast traffic */
15992 uint64_t lpbk_ucast_bytes;
15993 /* Number of transmitted bytes for multicast traffic */
15994 uint64_t lpbk_mcast_bytes;
15995 /* Number of transmitted bytes for broadcast traffic */
15996 uint64_t lpbk_bcast_bytes;
15997 /* Total Tx Drops for loopback traffic reported by STATS block */
15998 uint64_t tx_stat_discard;
15999 /* Total Tx Error Drops for loopback traffic reported by STATS block */
16000 uint64_t tx_stat_error;
16001 /* Total Rx Drops for loopback traffic reported by STATS block */
16002 uint64_t rx_stat_discard;
16003 /* Total Rx Error Drops for loopback traffic reported by STATS block */
16004 uint64_t rx_stat_error;
16005 uint8_t unused_0[7];
16007 * This field is used in Output records to indicate that the output
16008 * is completely written to RAM. This field should be read as '1'
16009 * to indicate that the output has been completely written.
16010 * When writing a command completion or response to an internal processor,
16011 * the order of writes has to be such that this field is written last.
16014 } __attribute__((packed));
16016 /***********************
16017 * hwrm_port_clr_stats *
16018 ***********************/
16021 /* hwrm_port_clr_stats_input (size:192b/24B) */
16022 struct hwrm_port_clr_stats_input {
16023 /* The HWRM command request type. */
16026 * The completion ring to send the completion event on. This should
16027 * be the NQ ID returned from the `nq_alloc` HWRM command.
16029 uint16_t cmpl_ring;
16031 * The sequence ID is used by the driver for tracking multiple
16032 * commands. This ID is treated as opaque data by the firmware and
16033 * the value is returned in the `hwrm_resp_hdr` upon completion.
16037 * The target ID of the command:
16038 * * 0x0-0xFFF8 - The function ID
16039 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
16040 * * 0xFFFD - Reserved for user-space HWRM interface
16043 uint16_t target_id;
16045 * A physical address pointer pointing to a host buffer that the
16046 * command's response data will be written. This can be either a host
16047 * physical address (HPA) or a guest physical address (GPA) and must
16048 * point to a physically contiguous block of memory.
16050 uint64_t resp_addr;
16051 /* Port ID of port that is being queried. */
16055 * If set to 1, then this field indicates clear the following RoCE
16056 * specific counters.
16057 * RoCE associated TX/RX cos counters
16058 * CNP associated TX/RX cos counters
16059 * RoCE/CNP specific TX/RX flow counters
16060 * Firmware will determine the RoCE/CNP cos queue based on qos profile.
16061 * This flag is honored only when RoCE is enabled on that port.
16063 #define HWRM_PORT_CLR_STATS_INPUT_FLAGS_ROCE_COUNTERS UINT32_C(0x1)
16064 uint8_t unused_0[5];
16065 } __attribute__((packed));
16067 /* hwrm_port_clr_stats_output (size:128b/16B) */
16068 struct hwrm_port_clr_stats_output {
16069 /* The specific error status for the command. */
16070 uint16_t error_code;
16071 /* The HWRM command request type. */
16073 /* The sequence ID from the original command. */
16075 /* The length of the response data in number of bytes. */
16077 uint8_t unused_0[7];
16079 * This field is used in Output records to indicate that the output
16080 * is completely written to RAM. This field should be read as '1'
16081 * to indicate that the output has been completely written.
16082 * When writing a command completion or response to an internal processor,
16083 * the order of writes has to be such that this field is written last.
16086 } __attribute__((packed));
16088 /***********************
16089 * hwrm_port_phy_qcaps *
16090 ***********************/
16093 /* hwrm_port_phy_qcaps_input (size:192b/24B) */
16094 struct hwrm_port_phy_qcaps_input {
16095 /* The HWRM command request type. */
16098 * The completion ring to send the completion event on. This should
16099 * be the NQ ID returned from the `nq_alloc` HWRM command.
16101 uint16_t cmpl_ring;
16103 * The sequence ID is used by the driver for tracking multiple
16104 * commands. This ID is treated as opaque data by the firmware and
16105 * the value is returned in the `hwrm_resp_hdr` upon completion.
16109 * The target ID of the command:
16110 * * 0x0-0xFFF8 - The function ID
16111 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
16112 * * 0xFFFD - Reserved for user-space HWRM interface
16115 uint16_t target_id;
16117 * A physical address pointer pointing to a host buffer that the
16118 * command's response data will be written. This can be either a host
16119 * physical address (HPA) or a guest physical address (GPA) and must
16120 * point to a physically contiguous block of memory.
16122 uint64_t resp_addr;
16123 /* Port ID of port that is being queried. */
16125 uint8_t unused_0[6];
16126 } __attribute__((packed));
16128 /* hwrm_port_phy_qcaps_output (size:192b/24B) */
16129 struct hwrm_port_phy_qcaps_output {
16130 /* The specific error status for the command. */
16131 uint16_t error_code;
16132 /* The HWRM command request type. */
16134 /* The sequence ID from the original command. */
16136 /* The length of the response data in number of bytes. */
16138 /* PHY capability flags */
16141 * If set to 1, then this field indicates that the
16142 * link is capable of supporting EEE.
16144 #define HWRM_PORT_PHY_QCAPS_OUTPUT_FLAGS_EEE_SUPPORTED \
16147 * If set to 1, then this field indicates that the
16148 * PHY is capable of supporting external loopback.
16150 #define HWRM_PORT_PHY_QCAPS_OUTPUT_FLAGS_EXTERNAL_LPBK_SUPPORTED \
16153 * Reserved field. The HWRM shall set this field to 0.
16154 * An HWRM client shall ignore this field.
16156 #define HWRM_PORT_PHY_QCAPS_OUTPUT_FLAGS_RSVD1_MASK \
16158 #define HWRM_PORT_PHY_QCAPS_OUTPUT_FLAGS_RSVD1_SFT 2
16159 /* Number of front panel ports for this device. */
16161 /* Not supported or unknown */
16162 #define HWRM_PORT_PHY_QCAPS_OUTPUT_PORT_CNT_UNKNOWN UINT32_C(0x0)
16163 /* single port device */
16164 #define HWRM_PORT_PHY_QCAPS_OUTPUT_PORT_CNT_1 UINT32_C(0x1)
16165 /* 2-port device */
16166 #define HWRM_PORT_PHY_QCAPS_OUTPUT_PORT_CNT_2 UINT32_C(0x2)
16167 /* 3-port device */
16168 #define HWRM_PORT_PHY_QCAPS_OUTPUT_PORT_CNT_3 UINT32_C(0x3)
16169 /* 4-port device */
16170 #define HWRM_PORT_PHY_QCAPS_OUTPUT_PORT_CNT_4 UINT32_C(0x4)
16171 #define HWRM_PORT_PHY_QCAPS_OUTPUT_PORT_CNT_LAST \
16172 HWRM_PORT_PHY_QCAPS_OUTPUT_PORT_CNT_4
16174 * This is a bit mask to indicate what speeds are supported
16175 * as forced speeds on this link.
16176 * For each speed that can be forced on this link, the
16177 * corresponding mask bit shall be set to '1'.
16179 uint16_t supported_speeds_force_mode;
16180 /* 100Mb link speed (Half-duplex) */
16181 #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_FORCE_MODE_100MBHD \
16183 /* 100Mb link speed (Full-duplex) */
16184 #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_FORCE_MODE_100MB \
16186 /* 1Gb link speed (Half-duplex) */
16187 #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_FORCE_MODE_1GBHD \
16189 /* 1Gb link speed (Full-duplex) */
16190 #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_FORCE_MODE_1GB \
16192 /* 2Gb link speed */
16193 #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_FORCE_MODE_2GB \
16195 /* 25Gb link speed */
16196 #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_FORCE_MODE_2_5GB \
16198 /* 10Gb link speed */
16199 #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_FORCE_MODE_10GB \
16201 /* 20Gb link speed */
16202 #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_FORCE_MODE_20GB \
16204 /* 25Gb link speed */
16205 #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_FORCE_MODE_25GB \
16207 /* 40Gb link speed */
16208 #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_FORCE_MODE_40GB \
16210 /* 50Gb link speed */
16211 #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_FORCE_MODE_50GB \
16213 /* 100Gb link speed */
16214 #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_FORCE_MODE_100GB \
16216 /* 10Mb link speed (Half-duplex) */
16217 #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_FORCE_MODE_10MBHD \
16219 /* 10Mb link speed (Full-duplex) */
16220 #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_FORCE_MODE_10MB \
16222 /* 200Gb link speed */
16223 #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_FORCE_MODE_200GB \
16226 * This is a bit mask to indicate what speeds are supported
16227 * for autonegotiation on this link.
16228 * For each speed that can be autonegotiated on this link, the
16229 * corresponding mask bit shall be set to '1'.
16231 uint16_t supported_speeds_auto_mode;
16232 /* 100Mb link speed (Half-duplex) */
16233 #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_AUTO_MODE_100MBHD \
16235 /* 100Mb link speed (Full-duplex) */
16236 #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_AUTO_MODE_100MB \
16238 /* 1Gb link speed (Half-duplex) */
16239 #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_AUTO_MODE_1GBHD \
16241 /* 1Gb link speed (Full-duplex) */
16242 #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_AUTO_MODE_1GB \
16244 /* 2Gb link speed */
16245 #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_AUTO_MODE_2GB \
16247 /* 25Gb link speed */
16248 #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_AUTO_MODE_2_5GB \
16250 /* 10Gb link speed */
16251 #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_AUTO_MODE_10GB \
16253 /* 20Gb link speed */
16254 #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_AUTO_MODE_20GB \
16256 /* 25Gb link speed */
16257 #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_AUTO_MODE_25GB \
16259 /* 40Gb link speed */
16260 #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_AUTO_MODE_40GB \
16262 /* 50Gb link speed */
16263 #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_AUTO_MODE_50GB \
16265 /* 100Gb link speed */
16266 #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_AUTO_MODE_100GB \
16268 /* 10Mb link speed (Half-duplex) */
16269 #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_AUTO_MODE_10MBHD \
16271 /* 10Mb link speed (Full-duplex) */
16272 #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_AUTO_MODE_10MB \
16274 /* 200Gb link speed */
16275 #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_AUTO_MODE_200GB \
16278 * This is a bit mask to indicate what speeds are supported
16279 * for EEE on this link.
16280 * For each speed that can be autonegotiated when EEE is enabled
16281 * on this link, the corresponding mask bit shall be set to '1'.
16282 * This field is only valid when the eee_suppotred is set to '1'.
16284 uint16_t supported_speeds_eee_mode;
16286 #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_EEE_MODE_RSVD1 \
16288 /* 100Mb link speed (Full-duplex) */
16289 #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_EEE_MODE_100MB \
16292 #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_EEE_MODE_RSVD2 \
16294 /* 1Gb link speed (Full-duplex) */
16295 #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_EEE_MODE_1GB \
16298 #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_EEE_MODE_RSVD3 \
16301 #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_EEE_MODE_RSVD4 \
16303 /* 10Gb link speed */
16304 #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_EEE_MODE_10GB \
16306 uint32_t tx_lpi_timer_low;
16308 * The lowest value of TX LPI timer that can be set on this link
16309 * when EEE is enabled. This value is in microseconds.
16310 * This field is valid only when_eee_supported is set to '1'.
16312 #define HWRM_PORT_PHY_QCAPS_OUTPUT_TX_LPI_TIMER_LOW_MASK \
16314 #define HWRM_PORT_PHY_QCAPS_OUTPUT_TX_LPI_TIMER_LOW_SFT 0
16316 * Reserved field. The HWRM shall set this field to 0.
16317 * An HWRM client shall ignore this field.
16319 #define HWRM_PORT_PHY_QCAPS_OUTPUT_RSVD2_MASK \
16320 UINT32_C(0xff000000)
16321 #define HWRM_PORT_PHY_QCAPS_OUTPUT_RSVD2_SFT 24
16322 uint32_t valid_tx_lpi_timer_high;
16324 * The highest value of TX LPI timer that can be set on this link
16325 * when EEE is enabled. This value is in microseconds.
16326 * This field is valid only when_eee_supported is set to '1'.
16328 #define HWRM_PORT_PHY_QCAPS_OUTPUT_TX_LPI_TIMER_HIGH_MASK \
16330 #define HWRM_PORT_PHY_QCAPS_OUTPUT_TX_LPI_TIMER_HIGH_SFT 0
16332 * This field is used in Output records to indicate that the output
16333 * is completely written to RAM. This field should be read as '1'
16334 * to indicate that the output has been completely written.
16335 * When writing a command completion or response to an internal processor,
16336 * the order of writes has to be such that this field is written last.
16338 #define HWRM_PORT_PHY_QCAPS_OUTPUT_VALID_MASK \
16339 UINT32_C(0xff000000)
16340 #define HWRM_PORT_PHY_QCAPS_OUTPUT_VALID_SFT 24
16341 } __attribute__((packed));
16343 /****************************
16344 * hwrm_port_phy_mdio_write *
16345 ****************************/
16348 /* hwrm_port_phy_mdio_write_input (size:320b/40B) */
16349 struct hwrm_port_phy_mdio_write_input {
16350 /* The HWRM command request type. */
16353 * The completion ring to send the completion event on. This should
16354 * be the NQ ID returned from the `nq_alloc` HWRM command.
16356 uint16_t cmpl_ring;
16358 * The sequence ID is used by the driver for tracking multiple
16359 * commands. This ID is treated as opaque data by the firmware and
16360 * the value is returned in the `hwrm_resp_hdr` upon completion.
16364 * The target ID of the command:
16365 * * 0x0-0xFFF8 - The function ID
16366 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
16367 * * 0xFFFD - Reserved for user-space HWRM interface
16370 uint16_t target_id;
16372 * A physical address pointer pointing to a host buffer that the
16373 * command's response data will be written. This can be either a host
16374 * physical address (HPA) or a guest physical address (GPA) and must
16375 * point to a physically contiguous block of memory.
16377 uint64_t resp_addr;
16378 /* Reserved for future use. */
16379 uint32_t unused_0[2];
16380 /* Port ID of port. */
16382 /* If phy_address is 0xFF, port_id will be used to derive phy_addr. */
16384 /* 8-bit device address. */
16386 /* 16-bit register address. */
16388 /* 16-bit register data. */
16391 * When this bit is set to 1 a Clause 45 mdio access is done.
16392 * when this bit is set to 0 a Clause 22 mdio access is done.
16396 uint8_t unused_1[7];
16397 } __attribute__((packed));
16399 /* hwrm_port_phy_mdio_write_output (size:128b/16B) */
16400 struct hwrm_port_phy_mdio_write_output {
16401 /* The specific error status for the command. */
16402 uint16_t error_code;
16403 /* The HWRM command request type. */
16405 /* The sequence ID from the original command. */
16407 /* The length of the response data in number of bytes. */
16409 uint8_t unused_0[7];
16411 * This field is used in Output records to indicate that the output
16412 * is completely written to RAM. This field should be read as '1'
16413 * to indicate that the output has been completely written.
16414 * When writing a command completion or response to an internal processor,
16415 * the order of writes has to be such that this field is written last.
16418 } __attribute__((packed));
16420 /***************************
16421 * hwrm_port_phy_mdio_read *
16422 ***************************/
16425 /* hwrm_port_phy_mdio_read_input (size:256b/32B) */
16426 struct hwrm_port_phy_mdio_read_input {
16427 /* The HWRM command request type. */
16430 * The completion ring to send the completion event on. This should
16431 * be the NQ ID returned from the `nq_alloc` HWRM command.
16433 uint16_t cmpl_ring;
16435 * The sequence ID is used by the driver for tracking multiple
16436 * commands. This ID is treated as opaque data by the firmware and
16437 * the value is returned in the `hwrm_resp_hdr` upon completion.
16441 * The target ID of the command:
16442 * * 0x0-0xFFF8 - The function ID
16443 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
16444 * * 0xFFFD - Reserved for user-space HWRM interface
16447 uint16_t target_id;
16449 * A physical address pointer pointing to a host buffer that the
16450 * command's response data will be written. This can be either a host
16451 * physical address (HPA) or a guest physical address (GPA) and must
16452 * point to a physically contiguous block of memory.
16454 uint64_t resp_addr;
16455 /* Reserved for future use. */
16456 uint32_t unused_0[2];
16457 /* Port ID of port. */
16459 /* If phy_address is 0xFF, port_id will be used to derive phy_addr. */
16461 /* 8-bit device address. */
16463 /* 16-bit register address. */
16466 * When this bit is set to 1 a Clause 45 mdio access is done.
16467 * when this bit is set to 0 a Clause 22 mdio access is done.
16472 } __attribute__((packed));
16474 /* hwrm_port_phy_mdio_read_output (size:128b/16B) */
16475 struct hwrm_port_phy_mdio_read_output {
16476 /* The specific error status for the command. */
16477 uint16_t error_code;
16478 /* The HWRM command request type. */
16480 /* The sequence ID from the original command. */
16482 /* The length of the response data in number of bytes. */
16484 /* 16-bit register data. */
16486 uint8_t unused_0[5];
16488 * This field is used in Output records to indicate that the output
16489 * is completely written to RAM. This field should be read as '1'
16490 * to indicate that the output has been completely written.
16491 * When writing a command completion or response to an internal processor,
16492 * the order of writes has to be such that this field is written last.
16495 } __attribute__((packed));
16497 /*********************
16498 * hwrm_port_led_cfg *
16499 *********************/
16502 /* hwrm_port_led_cfg_input (size:512b/64B) */
16503 struct hwrm_port_led_cfg_input {
16504 /* The HWRM command request type. */
16507 * The completion ring to send the completion event on. This should
16508 * be the NQ ID returned from the `nq_alloc` HWRM command.
16510 uint16_t cmpl_ring;
16512 * The sequence ID is used by the driver for tracking multiple
16513 * commands. This ID is treated as opaque data by the firmware and
16514 * the value is returned in the `hwrm_resp_hdr` upon completion.
16518 * The target ID of the command:
16519 * * 0x0-0xFFF8 - The function ID
16520 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
16521 * * 0xFFFD - Reserved for user-space HWRM interface
16524 uint16_t target_id;
16526 * A physical address pointer pointing to a host buffer that the
16527 * command's response data will be written. This can be either a host
16528 * physical address (HPA) or a guest physical address (GPA) and must
16529 * point to a physically contiguous block of memory.
16531 uint64_t resp_addr;
16534 * This bit must be '1' for the led0_id field to be
16537 #define HWRM_PORT_LED_CFG_INPUT_ENABLES_LED0_ID \
16540 * This bit must be '1' for the led0_state field to be
16543 #define HWRM_PORT_LED_CFG_INPUT_ENABLES_LED0_STATE \
16546 * This bit must be '1' for the led0_color field to be
16549 #define HWRM_PORT_LED_CFG_INPUT_ENABLES_LED0_COLOR \
16552 * This bit must be '1' for the led0_blink_on field to be
16555 #define HWRM_PORT_LED_CFG_INPUT_ENABLES_LED0_BLINK_ON \
16558 * This bit must be '1' for the led0_blink_off field to be
16561 #define HWRM_PORT_LED_CFG_INPUT_ENABLES_LED0_BLINK_OFF \
16564 * This bit must be '1' for the led0_group_id field to be
16567 #define HWRM_PORT_LED_CFG_INPUT_ENABLES_LED0_GROUP_ID \
16570 * This bit must be '1' for the led1_id field to be
16573 #define HWRM_PORT_LED_CFG_INPUT_ENABLES_LED1_ID \
16576 * This bit must be '1' for the led1_state field to be
16579 #define HWRM_PORT_LED_CFG_INPUT_ENABLES_LED1_STATE \
16582 * This bit must be '1' for the led1_color field to be
16585 #define HWRM_PORT_LED_CFG_INPUT_ENABLES_LED1_COLOR \
16588 * This bit must be '1' for the led1_blink_on field to be
16591 #define HWRM_PORT_LED_CFG_INPUT_ENABLES_LED1_BLINK_ON \
16594 * This bit must be '1' for the led1_blink_off field to be
16597 #define HWRM_PORT_LED_CFG_INPUT_ENABLES_LED1_BLINK_OFF \
16600 * This bit must be '1' for the led1_group_id field to be
16603 #define HWRM_PORT_LED_CFG_INPUT_ENABLES_LED1_GROUP_ID \
16606 * This bit must be '1' for the led2_id field to be
16609 #define HWRM_PORT_LED_CFG_INPUT_ENABLES_LED2_ID \
16612 * This bit must be '1' for the led2_state field to be
16615 #define HWRM_PORT_LED_CFG_INPUT_ENABLES_LED2_STATE \
16618 * This bit must be '1' for the led2_color field to be
16621 #define HWRM_PORT_LED_CFG_INPUT_ENABLES_LED2_COLOR \
16624 * This bit must be '1' for the led2_blink_on field to be
16627 #define HWRM_PORT_LED_CFG_INPUT_ENABLES_LED2_BLINK_ON \
16630 * This bit must be '1' for the led2_blink_off field to be
16633 #define HWRM_PORT_LED_CFG_INPUT_ENABLES_LED2_BLINK_OFF \
16636 * This bit must be '1' for the led2_group_id field to be
16639 #define HWRM_PORT_LED_CFG_INPUT_ENABLES_LED2_GROUP_ID \
16642 * This bit must be '1' for the led3_id field to be
16645 #define HWRM_PORT_LED_CFG_INPUT_ENABLES_LED3_ID \
16648 * This bit must be '1' for the led3_state field to be
16651 #define HWRM_PORT_LED_CFG_INPUT_ENABLES_LED3_STATE \
16654 * This bit must be '1' for the led3_color field to be
16657 #define HWRM_PORT_LED_CFG_INPUT_ENABLES_LED3_COLOR \
16660 * This bit must be '1' for the led3_blink_on field to be
16663 #define HWRM_PORT_LED_CFG_INPUT_ENABLES_LED3_BLINK_ON \
16666 * This bit must be '1' for the led3_blink_off field to be
16669 #define HWRM_PORT_LED_CFG_INPUT_ENABLES_LED3_BLINK_OFF \
16672 * This bit must be '1' for the led3_group_id field to be
16675 #define HWRM_PORT_LED_CFG_INPUT_ENABLES_LED3_GROUP_ID \
16677 /* Port ID of port whose LEDs are configured. */
16680 * The number of LEDs that are being configured.
16681 * Up to 4 LEDs can be configured with this command.
16684 /* Reserved field. */
16686 /* An identifier for the LED #0. */
16688 /* The requested state of the LED #0. */
16689 uint8_t led0_state;
16690 /* Default state of the LED */
16691 #define HWRM_PORT_LED_CFG_INPUT_LED0_STATE_DEFAULT UINT32_C(0x0)
16693 #define HWRM_PORT_LED_CFG_INPUT_LED0_STATE_OFF UINT32_C(0x1)
16695 #define HWRM_PORT_LED_CFG_INPUT_LED0_STATE_ON UINT32_C(0x2)
16697 #define HWRM_PORT_LED_CFG_INPUT_LED0_STATE_BLINK UINT32_C(0x3)
16698 /* Blink Alternately */
16699 #define HWRM_PORT_LED_CFG_INPUT_LED0_STATE_BLINKALT UINT32_C(0x4)
16700 #define HWRM_PORT_LED_CFG_INPUT_LED0_STATE_LAST \
16701 HWRM_PORT_LED_CFG_INPUT_LED0_STATE_BLINKALT
16702 /* The requested color of LED #0. */
16703 uint8_t led0_color;
16705 #define HWRM_PORT_LED_CFG_INPUT_LED0_COLOR_DEFAULT UINT32_C(0x0)
16707 #define HWRM_PORT_LED_CFG_INPUT_LED0_COLOR_AMBER UINT32_C(0x1)
16709 #define HWRM_PORT_LED_CFG_INPUT_LED0_COLOR_GREEN UINT32_C(0x2)
16710 /* Green or Amber */
16711 #define HWRM_PORT_LED_CFG_INPUT_LED0_COLOR_GREENAMBER UINT32_C(0x3)
16712 #define HWRM_PORT_LED_CFG_INPUT_LED0_COLOR_LAST \
16713 HWRM_PORT_LED_CFG_INPUT_LED0_COLOR_GREENAMBER
16716 * If the LED #0 state is "blink" or "blinkalt", then
16717 * this field represents the requested time in milliseconds
16718 * to keep LED on between cycles.
16720 uint16_t led0_blink_on;
16722 * If the LED #0 state is "blink" or "blinkalt", then
16723 * this field represents the requested time in milliseconds
16724 * to keep LED off between cycles.
16726 uint16_t led0_blink_off;
16728 * An identifier for the group of LEDs that LED #0 belongs
16730 * If set to 0, then the LED #0 shall not be grouped and
16731 * shall be treated as an individual resource.
16732 * For all other non-zero values of this field, LED #0 shall
16733 * be grouped together with the LEDs with the same group ID
16736 uint8_t led0_group_id;
16737 /* Reserved field. */
16739 /* An identifier for the LED #1. */
16741 /* The requested state of the LED #1. */
16742 uint8_t led1_state;
16743 /* Default state of the LED */
16744 #define HWRM_PORT_LED_CFG_INPUT_LED1_STATE_DEFAULT UINT32_C(0x0)
16746 #define HWRM_PORT_LED_CFG_INPUT_LED1_STATE_OFF UINT32_C(0x1)
16748 #define HWRM_PORT_LED_CFG_INPUT_LED1_STATE_ON UINT32_C(0x2)
16750 #define HWRM_PORT_LED_CFG_INPUT_LED1_STATE_BLINK UINT32_C(0x3)
16751 /* Blink Alternately */
16752 #define HWRM_PORT_LED_CFG_INPUT_LED1_STATE_BLINKALT UINT32_C(0x4)
16753 #define HWRM_PORT_LED_CFG_INPUT_LED1_STATE_LAST \
16754 HWRM_PORT_LED_CFG_INPUT_LED1_STATE_BLINKALT
16755 /* The requested color of LED #1. */
16756 uint8_t led1_color;
16758 #define HWRM_PORT_LED_CFG_INPUT_LED1_COLOR_DEFAULT UINT32_C(0x0)
16760 #define HWRM_PORT_LED_CFG_INPUT_LED1_COLOR_AMBER UINT32_C(0x1)
16762 #define HWRM_PORT_LED_CFG_INPUT_LED1_COLOR_GREEN UINT32_C(0x2)
16763 /* Green or Amber */
16764 #define HWRM_PORT_LED_CFG_INPUT_LED1_COLOR_GREENAMBER UINT32_C(0x3)
16765 #define HWRM_PORT_LED_CFG_INPUT_LED1_COLOR_LAST \
16766 HWRM_PORT_LED_CFG_INPUT_LED1_COLOR_GREENAMBER
16769 * If the LED #1 state is "blink" or "blinkalt", then
16770 * this field represents the requested time in milliseconds
16771 * to keep LED on between cycles.
16773 uint16_t led1_blink_on;
16775 * If the LED #1 state is "blink" or "blinkalt", then
16776 * this field represents the requested time in milliseconds
16777 * to keep LED off between cycles.
16779 uint16_t led1_blink_off;
16781 * An identifier for the group of LEDs that LED #1 belongs
16783 * If set to 0, then the LED #1 shall not be grouped and
16784 * shall be treated as an individual resource.
16785 * For all other non-zero values of this field, LED #1 shall
16786 * be grouped together with the LEDs with the same group ID
16789 uint8_t led1_group_id;
16790 /* Reserved field. */
16792 /* An identifier for the LED #2. */
16794 /* The requested state of the LED #2. */
16795 uint8_t led2_state;
16796 /* Default state of the LED */
16797 #define HWRM_PORT_LED_CFG_INPUT_LED2_STATE_DEFAULT UINT32_C(0x0)
16799 #define HWRM_PORT_LED_CFG_INPUT_LED2_STATE_OFF UINT32_C(0x1)
16801 #define HWRM_PORT_LED_CFG_INPUT_LED2_STATE_ON UINT32_C(0x2)
16803 #define HWRM_PORT_LED_CFG_INPUT_LED2_STATE_BLINK UINT32_C(0x3)
16804 /* Blink Alternately */
16805 #define HWRM_PORT_LED_CFG_INPUT_LED2_STATE_BLINKALT UINT32_C(0x4)
16806 #define HWRM_PORT_LED_CFG_INPUT_LED2_STATE_LAST \
16807 HWRM_PORT_LED_CFG_INPUT_LED2_STATE_BLINKALT
16808 /* The requested color of LED #2. */
16809 uint8_t led2_color;
16811 #define HWRM_PORT_LED_CFG_INPUT_LED2_COLOR_DEFAULT UINT32_C(0x0)
16813 #define HWRM_PORT_LED_CFG_INPUT_LED2_COLOR_AMBER UINT32_C(0x1)
16815 #define HWRM_PORT_LED_CFG_INPUT_LED2_COLOR_GREEN UINT32_C(0x2)
16816 /* Green or Amber */
16817 #define HWRM_PORT_LED_CFG_INPUT_LED2_COLOR_GREENAMBER UINT32_C(0x3)
16818 #define HWRM_PORT_LED_CFG_INPUT_LED2_COLOR_LAST \
16819 HWRM_PORT_LED_CFG_INPUT_LED2_COLOR_GREENAMBER
16822 * If the LED #2 state is "blink" or "blinkalt", then
16823 * this field represents the requested time in milliseconds
16824 * to keep LED on between cycles.
16826 uint16_t led2_blink_on;
16828 * If the LED #2 state is "blink" or "blinkalt", then
16829 * this field represents the requested time in milliseconds
16830 * to keep LED off between cycles.
16832 uint16_t led2_blink_off;
16834 * An identifier for the group of LEDs that LED #2 belongs
16836 * If set to 0, then the LED #2 shall not be grouped and
16837 * shall be treated as an individual resource.
16838 * For all other non-zero values of this field, LED #2 shall
16839 * be grouped together with the LEDs with the same group ID
16842 uint8_t led2_group_id;
16843 /* Reserved field. */
16845 /* An identifier for the LED #3. */
16847 /* The requested state of the LED #3. */
16848 uint8_t led3_state;
16849 /* Default state of the LED */
16850 #define HWRM_PORT_LED_CFG_INPUT_LED3_STATE_DEFAULT UINT32_C(0x0)
16852 #define HWRM_PORT_LED_CFG_INPUT_LED3_STATE_OFF UINT32_C(0x1)
16854 #define HWRM_PORT_LED_CFG_INPUT_LED3_STATE_ON UINT32_C(0x2)
16856 #define HWRM_PORT_LED_CFG_INPUT_LED3_STATE_BLINK UINT32_C(0x3)
16857 /* Blink Alternately */
16858 #define HWRM_PORT_LED_CFG_INPUT_LED3_STATE_BLINKALT UINT32_C(0x4)
16859 #define HWRM_PORT_LED_CFG_INPUT_LED3_STATE_LAST \
16860 HWRM_PORT_LED_CFG_INPUT_LED3_STATE_BLINKALT
16861 /* The requested color of LED #3. */
16862 uint8_t led3_color;
16864 #define HWRM_PORT_LED_CFG_INPUT_LED3_COLOR_DEFAULT UINT32_C(0x0)
16866 #define HWRM_PORT_LED_CFG_INPUT_LED3_COLOR_AMBER UINT32_C(0x1)
16868 #define HWRM_PORT_LED_CFG_INPUT_LED3_COLOR_GREEN UINT32_C(0x2)
16869 /* Green or Amber */
16870 #define HWRM_PORT_LED_CFG_INPUT_LED3_COLOR_GREENAMBER UINT32_C(0x3)
16871 #define HWRM_PORT_LED_CFG_INPUT_LED3_COLOR_LAST \
16872 HWRM_PORT_LED_CFG_INPUT_LED3_COLOR_GREENAMBER
16875 * If the LED #3 state is "blink" or "blinkalt", then
16876 * this field represents the requested time in milliseconds
16877 * to keep LED on between cycles.
16879 uint16_t led3_blink_on;
16881 * If the LED #3 state is "blink" or "blinkalt", then
16882 * this field represents the requested time in milliseconds
16883 * to keep LED off between cycles.
16885 uint16_t led3_blink_off;
16887 * An identifier for the group of LEDs that LED #3 belongs
16889 * If set to 0, then the LED #3 shall not be grouped and
16890 * shall be treated as an individual resource.
16891 * For all other non-zero values of this field, LED #3 shall
16892 * be grouped together with the LEDs with the same group ID
16895 uint8_t led3_group_id;
16896 /* Reserved field. */
16898 } __attribute__((packed));
16900 /* hwrm_port_led_cfg_output (size:128b/16B) */
16901 struct hwrm_port_led_cfg_output {
16902 /* The specific error status for the command. */
16903 uint16_t error_code;
16904 /* The HWRM command request type. */
16906 /* The sequence ID from the original command. */
16908 /* The length of the response data in number of bytes. */
16910 uint8_t unused_0[7];
16912 * This field is used in Output records to indicate that the output
16913 * is completely written to RAM. This field should be read as '1'
16914 * to indicate that the output has been completely written.
16915 * When writing a command completion or response to an internal processor,
16916 * the order of writes has to be such that this field is written last.
16919 } __attribute__((packed));
16921 /**********************
16922 * hwrm_port_led_qcfg *
16923 **********************/
16926 /* hwrm_port_led_qcfg_input (size:192b/24B) */
16927 struct hwrm_port_led_qcfg_input {
16928 /* The HWRM command request type. */
16931 * The completion ring to send the completion event on. This should
16932 * be the NQ ID returned from the `nq_alloc` HWRM command.
16934 uint16_t cmpl_ring;
16936 * The sequence ID is used by the driver for tracking multiple
16937 * commands. This ID is treated as opaque data by the firmware and
16938 * the value is returned in the `hwrm_resp_hdr` upon completion.
16942 * The target ID of the command:
16943 * * 0x0-0xFFF8 - The function ID
16944 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
16945 * * 0xFFFD - Reserved for user-space HWRM interface
16948 uint16_t target_id;
16950 * A physical address pointer pointing to a host buffer that the
16951 * command's response data will be written. This can be either a host
16952 * physical address (HPA) or a guest physical address (GPA) and must
16953 * point to a physically contiguous block of memory.
16955 uint64_t resp_addr;
16956 /* Port ID of port whose LED configuration is being queried. */
16958 uint8_t unused_0[6];
16959 } __attribute__((packed));
16961 /* hwrm_port_led_qcfg_output (size:448b/56B) */
16962 struct hwrm_port_led_qcfg_output {
16963 /* The specific error status for the command. */
16964 uint16_t error_code;
16965 /* The HWRM command request type. */
16967 /* The sequence ID from the original command. */
16969 /* The length of the response data in number of bytes. */
16972 * The number of LEDs that are configured on this port.
16973 * Up to 4 LEDs can be returned in the response.
16976 /* An identifier for the LED #0. */
16978 /* The type of LED #0. */
16981 #define HWRM_PORT_LED_QCFG_OUTPUT_LED0_TYPE_SPEED UINT32_C(0x0)
16983 #define HWRM_PORT_LED_QCFG_OUTPUT_LED0_TYPE_ACTIVITY UINT32_C(0x1)
16985 #define HWRM_PORT_LED_QCFG_OUTPUT_LED0_TYPE_INVALID UINT32_C(0xff)
16986 #define HWRM_PORT_LED_QCFG_OUTPUT_LED0_TYPE_LAST \
16987 HWRM_PORT_LED_QCFG_OUTPUT_LED0_TYPE_INVALID
16988 /* The current state of the LED #0. */
16989 uint8_t led0_state;
16990 /* Default state of the LED */
16991 #define HWRM_PORT_LED_QCFG_OUTPUT_LED0_STATE_DEFAULT UINT32_C(0x0)
16993 #define HWRM_PORT_LED_QCFG_OUTPUT_LED0_STATE_OFF UINT32_C(0x1)
16995 #define HWRM_PORT_LED_QCFG_OUTPUT_LED0_STATE_ON UINT32_C(0x2)
16997 #define HWRM_PORT_LED_QCFG_OUTPUT_LED0_STATE_BLINK UINT32_C(0x3)
16998 /* Blink Alternately */
16999 #define HWRM_PORT_LED_QCFG_OUTPUT_LED0_STATE_BLINKALT UINT32_C(0x4)
17000 #define HWRM_PORT_LED_QCFG_OUTPUT_LED0_STATE_LAST \
17001 HWRM_PORT_LED_QCFG_OUTPUT_LED0_STATE_BLINKALT
17002 /* The color of LED #0. */
17003 uint8_t led0_color;
17005 #define HWRM_PORT_LED_QCFG_OUTPUT_LED0_COLOR_DEFAULT UINT32_C(0x0)
17007 #define HWRM_PORT_LED_QCFG_OUTPUT_LED0_COLOR_AMBER UINT32_C(0x1)
17009 #define HWRM_PORT_LED_QCFG_OUTPUT_LED0_COLOR_GREEN UINT32_C(0x2)
17010 /* Green or Amber */
17011 #define HWRM_PORT_LED_QCFG_OUTPUT_LED0_COLOR_GREENAMBER UINT32_C(0x3)
17012 #define HWRM_PORT_LED_QCFG_OUTPUT_LED0_COLOR_LAST \
17013 HWRM_PORT_LED_QCFG_OUTPUT_LED0_COLOR_GREENAMBER
17016 * If the LED #0 state is "blink" or "blinkalt", then
17017 * this field represents the requested time in milliseconds
17018 * to keep LED on between cycles.
17020 uint16_t led0_blink_on;
17022 * If the LED #0 state is "blink" or "blinkalt", then
17023 * this field represents the requested time in milliseconds
17024 * to keep LED off between cycles.
17026 uint16_t led0_blink_off;
17028 * An identifier for the group of LEDs that LED #0 belongs
17030 * If set to 0, then the LED #0 is not grouped.
17031 * For all other non-zero values of this field, LED #0 is
17032 * grouped together with the LEDs with the same group ID
17035 uint8_t led0_group_id;
17036 /* An identifier for the LED #1. */
17038 /* The type of LED #1. */
17041 #define HWRM_PORT_LED_QCFG_OUTPUT_LED1_TYPE_SPEED UINT32_C(0x0)
17043 #define HWRM_PORT_LED_QCFG_OUTPUT_LED1_TYPE_ACTIVITY UINT32_C(0x1)
17045 #define HWRM_PORT_LED_QCFG_OUTPUT_LED1_TYPE_INVALID UINT32_C(0xff)
17046 #define HWRM_PORT_LED_QCFG_OUTPUT_LED1_TYPE_LAST \
17047 HWRM_PORT_LED_QCFG_OUTPUT_LED1_TYPE_INVALID
17048 /* The current state of the LED #1. */
17049 uint8_t led1_state;
17050 /* Default state of the LED */
17051 #define HWRM_PORT_LED_QCFG_OUTPUT_LED1_STATE_DEFAULT UINT32_C(0x0)
17053 #define HWRM_PORT_LED_QCFG_OUTPUT_LED1_STATE_OFF UINT32_C(0x1)
17055 #define HWRM_PORT_LED_QCFG_OUTPUT_LED1_STATE_ON UINT32_C(0x2)
17057 #define HWRM_PORT_LED_QCFG_OUTPUT_LED1_STATE_BLINK UINT32_C(0x3)
17058 /* Blink Alternately */
17059 #define HWRM_PORT_LED_QCFG_OUTPUT_LED1_STATE_BLINKALT UINT32_C(0x4)
17060 #define HWRM_PORT_LED_QCFG_OUTPUT_LED1_STATE_LAST \
17061 HWRM_PORT_LED_QCFG_OUTPUT_LED1_STATE_BLINKALT
17062 /* The color of LED #1. */
17063 uint8_t led1_color;
17065 #define HWRM_PORT_LED_QCFG_OUTPUT_LED1_COLOR_DEFAULT UINT32_C(0x0)
17067 #define HWRM_PORT_LED_QCFG_OUTPUT_LED1_COLOR_AMBER UINT32_C(0x1)
17069 #define HWRM_PORT_LED_QCFG_OUTPUT_LED1_COLOR_GREEN UINT32_C(0x2)
17070 /* Green or Amber */
17071 #define HWRM_PORT_LED_QCFG_OUTPUT_LED1_COLOR_GREENAMBER UINT32_C(0x3)
17072 #define HWRM_PORT_LED_QCFG_OUTPUT_LED1_COLOR_LAST \
17073 HWRM_PORT_LED_QCFG_OUTPUT_LED1_COLOR_GREENAMBER
17076 * If the LED #1 state is "blink" or "blinkalt", then
17077 * this field represents the requested time in milliseconds
17078 * to keep LED on between cycles.
17080 uint16_t led1_blink_on;
17082 * If the LED #1 state is "blink" or "blinkalt", then
17083 * this field represents the requested time in milliseconds
17084 * to keep LED off between cycles.
17086 uint16_t led1_blink_off;
17088 * An identifier for the group of LEDs that LED #1 belongs
17090 * If set to 0, then the LED #1 is not grouped.
17091 * For all other non-zero values of this field, LED #1 is
17092 * grouped together with the LEDs with the same group ID
17095 uint8_t led1_group_id;
17096 /* An identifier for the LED #2. */
17098 /* The type of LED #2. */
17101 #define HWRM_PORT_LED_QCFG_OUTPUT_LED2_TYPE_SPEED UINT32_C(0x0)
17103 #define HWRM_PORT_LED_QCFG_OUTPUT_LED2_TYPE_ACTIVITY UINT32_C(0x1)
17105 #define HWRM_PORT_LED_QCFG_OUTPUT_LED2_TYPE_INVALID UINT32_C(0xff)
17106 #define HWRM_PORT_LED_QCFG_OUTPUT_LED2_TYPE_LAST \
17107 HWRM_PORT_LED_QCFG_OUTPUT_LED2_TYPE_INVALID
17108 /* The current state of the LED #2. */
17109 uint8_t led2_state;
17110 /* Default state of the LED */
17111 #define HWRM_PORT_LED_QCFG_OUTPUT_LED2_STATE_DEFAULT UINT32_C(0x0)
17113 #define HWRM_PORT_LED_QCFG_OUTPUT_LED2_STATE_OFF UINT32_C(0x1)
17115 #define HWRM_PORT_LED_QCFG_OUTPUT_LED2_STATE_ON UINT32_C(0x2)
17117 #define HWRM_PORT_LED_QCFG_OUTPUT_LED2_STATE_BLINK UINT32_C(0x3)
17118 /* Blink Alternately */
17119 #define HWRM_PORT_LED_QCFG_OUTPUT_LED2_STATE_BLINKALT UINT32_C(0x4)
17120 #define HWRM_PORT_LED_QCFG_OUTPUT_LED2_STATE_LAST \
17121 HWRM_PORT_LED_QCFG_OUTPUT_LED2_STATE_BLINKALT
17122 /* The color of LED #2. */
17123 uint8_t led2_color;
17125 #define HWRM_PORT_LED_QCFG_OUTPUT_LED2_COLOR_DEFAULT UINT32_C(0x0)
17127 #define HWRM_PORT_LED_QCFG_OUTPUT_LED2_COLOR_AMBER UINT32_C(0x1)
17129 #define HWRM_PORT_LED_QCFG_OUTPUT_LED2_COLOR_GREEN UINT32_C(0x2)
17130 /* Green or Amber */
17131 #define HWRM_PORT_LED_QCFG_OUTPUT_LED2_COLOR_GREENAMBER UINT32_C(0x3)
17132 #define HWRM_PORT_LED_QCFG_OUTPUT_LED2_COLOR_LAST \
17133 HWRM_PORT_LED_QCFG_OUTPUT_LED2_COLOR_GREENAMBER
17136 * If the LED #2 state is "blink" or "blinkalt", then
17137 * this field represents the requested time in milliseconds
17138 * to keep LED on between cycles.
17140 uint16_t led2_blink_on;
17142 * If the LED #2 state is "blink" or "blinkalt", then
17143 * this field represents the requested time in milliseconds
17144 * to keep LED off between cycles.
17146 uint16_t led2_blink_off;
17148 * An identifier for the group of LEDs that LED #2 belongs
17150 * If set to 0, then the LED #2 is not grouped.
17151 * For all other non-zero values of this field, LED #2 is
17152 * grouped together with the LEDs with the same group ID
17155 uint8_t led2_group_id;
17156 /* An identifier for the LED #3. */
17158 /* The type of LED #3. */
17161 #define HWRM_PORT_LED_QCFG_OUTPUT_LED3_TYPE_SPEED UINT32_C(0x0)
17163 #define HWRM_PORT_LED_QCFG_OUTPUT_LED3_TYPE_ACTIVITY UINT32_C(0x1)
17165 #define HWRM_PORT_LED_QCFG_OUTPUT_LED3_TYPE_INVALID UINT32_C(0xff)
17166 #define HWRM_PORT_LED_QCFG_OUTPUT_LED3_TYPE_LAST \
17167 HWRM_PORT_LED_QCFG_OUTPUT_LED3_TYPE_INVALID
17168 /* The current state of the LED #3. */
17169 uint8_t led3_state;
17170 /* Default state of the LED */
17171 #define HWRM_PORT_LED_QCFG_OUTPUT_LED3_STATE_DEFAULT UINT32_C(0x0)
17173 #define HWRM_PORT_LED_QCFG_OUTPUT_LED3_STATE_OFF UINT32_C(0x1)
17175 #define HWRM_PORT_LED_QCFG_OUTPUT_LED3_STATE_ON UINT32_C(0x2)
17177 #define HWRM_PORT_LED_QCFG_OUTPUT_LED3_STATE_BLINK UINT32_C(0x3)
17178 /* Blink Alternately */
17179 #define HWRM_PORT_LED_QCFG_OUTPUT_LED3_STATE_BLINKALT UINT32_C(0x4)
17180 #define HWRM_PORT_LED_QCFG_OUTPUT_LED3_STATE_LAST \
17181 HWRM_PORT_LED_QCFG_OUTPUT_LED3_STATE_BLINKALT
17182 /* The color of LED #3. */
17183 uint8_t led3_color;
17185 #define HWRM_PORT_LED_QCFG_OUTPUT_LED3_COLOR_DEFAULT UINT32_C(0x0)
17187 #define HWRM_PORT_LED_QCFG_OUTPUT_LED3_COLOR_AMBER UINT32_C(0x1)
17189 #define HWRM_PORT_LED_QCFG_OUTPUT_LED3_COLOR_GREEN UINT32_C(0x2)
17190 /* Green or Amber */
17191 #define HWRM_PORT_LED_QCFG_OUTPUT_LED3_COLOR_GREENAMBER UINT32_C(0x3)
17192 #define HWRM_PORT_LED_QCFG_OUTPUT_LED3_COLOR_LAST \
17193 HWRM_PORT_LED_QCFG_OUTPUT_LED3_COLOR_GREENAMBER
17196 * If the LED #3 state is "blink" or "blinkalt", then
17197 * this field represents the requested time in milliseconds
17198 * to keep LED on between cycles.
17200 uint16_t led3_blink_on;
17202 * If the LED #3 state is "blink" or "blinkalt", then
17203 * this field represents the requested time in milliseconds
17204 * to keep LED off between cycles.
17206 uint16_t led3_blink_off;
17208 * An identifier for the group of LEDs that LED #3 belongs
17210 * If set to 0, then the LED #3 is not grouped.
17211 * For all other non-zero values of this field, LED #3 is
17212 * grouped together with the LEDs with the same group ID
17215 uint8_t led3_group_id;
17216 uint8_t unused_4[6];
17218 * This field is used in Output records to indicate that the output
17219 * is completely written to RAM. This field should be read as '1'
17220 * to indicate that the output has been completely written.
17221 * When writing a command completion or response to an internal processor,
17222 * the order of writes has to be such that this field is written last.
17225 } __attribute__((packed));
17227 /***********************
17228 * hwrm_port_led_qcaps *
17229 ***********************/
17232 /* hwrm_port_led_qcaps_input (size:192b/24B) */
17233 struct hwrm_port_led_qcaps_input {
17234 /* The HWRM command request type. */
17237 * The completion ring to send the completion event on. This should
17238 * be the NQ ID returned from the `nq_alloc` HWRM command.
17240 uint16_t cmpl_ring;
17242 * The sequence ID is used by the driver for tracking multiple
17243 * commands. This ID is treated as opaque data by the firmware and
17244 * the value is returned in the `hwrm_resp_hdr` upon completion.
17248 * The target ID of the command:
17249 * * 0x0-0xFFF8 - The function ID
17250 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
17251 * * 0xFFFD - Reserved for user-space HWRM interface
17254 uint16_t target_id;
17256 * A physical address pointer pointing to a host buffer that the
17257 * command's response data will be written. This can be either a host
17258 * physical address (HPA) or a guest physical address (GPA) and must
17259 * point to a physically contiguous block of memory.
17261 uint64_t resp_addr;
17262 /* Port ID of port whose LED configuration is being queried. */
17264 uint8_t unused_0[6];
17265 } __attribute__((packed));
17267 /* hwrm_port_led_qcaps_output (size:384b/48B) */
17268 struct hwrm_port_led_qcaps_output {
17269 /* The specific error status for the command. */
17270 uint16_t error_code;
17271 /* The HWRM command request type. */
17273 /* The sequence ID from the original command. */
17275 /* The length of the response data in number of bytes. */
17278 * The number of LEDs that are configured on this port.
17279 * Up to 4 LEDs can be returned in the response.
17282 /* Reserved for future use. */
17284 /* An identifier for the LED #0. */
17286 /* The type of LED #0. */
17289 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED0_TYPE_SPEED UINT32_C(0x0)
17291 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED0_TYPE_ACTIVITY UINT32_C(0x1)
17293 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED0_TYPE_INVALID UINT32_C(0xff)
17294 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED0_TYPE_LAST \
17295 HWRM_PORT_LED_QCAPS_OUTPUT_LED0_TYPE_INVALID
17297 * An identifier for the group of LEDs that LED #0 belongs
17299 * If set to 0, then the LED #0 cannot be grouped.
17300 * For all other non-zero values of this field, LED #0 is
17301 * grouped together with the LEDs with the same group ID
17304 uint8_t led0_group_id;
17306 /* The states supported by LED #0. */
17307 uint16_t led0_state_caps;
17309 * If set to 1, this LED is enabled.
17310 * If set to 0, this LED is disabled.
17312 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED0_STATE_CAPS_ENABLED \
17315 * If set to 1, off state is supported on this LED.
17316 * If set to 0, off state is not supported on this LED.
17318 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED0_STATE_CAPS_OFF_SUPPORTED \
17321 * If set to 1, on state is supported on this LED.
17322 * If set to 0, on state is not supported on this LED.
17324 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED0_STATE_CAPS_ON_SUPPORTED \
17327 * If set to 1, blink state is supported on this LED.
17328 * If set to 0, blink state is not supported on this LED.
17330 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED0_STATE_CAPS_BLINK_SUPPORTED \
17333 * If set to 1, blink_alt state is supported on this LED.
17334 * If set to 0, blink_alt state is not supported on this LED.
17336 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED0_STATE_CAPS_BLINK_ALT_SUPPORTED \
17338 /* The colors supported by LED #0. */
17339 uint16_t led0_color_caps;
17341 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED0_COLOR_CAPS_RSVD \
17344 * If set to 1, Amber color is supported on this LED.
17345 * If set to 0, Amber color is not supported on this LED.
17347 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED0_COLOR_CAPS_AMBER_SUPPORTED \
17350 * If set to 1, Green color is supported on this LED.
17351 * If set to 0, Green color is not supported on this LED.
17353 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED0_COLOR_CAPS_GREEN_SUPPORTED \
17355 /* An identifier for the LED #1. */
17357 /* The type of LED #1. */
17360 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED1_TYPE_SPEED UINT32_C(0x0)
17362 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED1_TYPE_ACTIVITY UINT32_C(0x1)
17364 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED1_TYPE_INVALID UINT32_C(0xff)
17365 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED1_TYPE_LAST \
17366 HWRM_PORT_LED_QCAPS_OUTPUT_LED1_TYPE_INVALID
17368 * An identifier for the group of LEDs that LED #1 belongs
17370 * If set to 0, then the LED #0 cannot be grouped.
17371 * For all other non-zero values of this field, LED #0 is
17372 * grouped together with the LEDs with the same group ID
17375 uint8_t led1_group_id;
17377 /* The states supported by LED #1. */
17378 uint16_t led1_state_caps;
17380 * If set to 1, this LED is enabled.
17381 * If set to 0, this LED is disabled.
17383 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED1_STATE_CAPS_ENABLED \
17386 * If set to 1, off state is supported on this LED.
17387 * If set to 0, off state is not supported on this LED.
17389 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED1_STATE_CAPS_OFF_SUPPORTED \
17392 * If set to 1, on state is supported on this LED.
17393 * If set to 0, on state is not supported on this LED.
17395 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED1_STATE_CAPS_ON_SUPPORTED \
17398 * If set to 1, blink state is supported on this LED.
17399 * If set to 0, blink state is not supported on this LED.
17401 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED1_STATE_CAPS_BLINK_SUPPORTED \
17404 * If set to 1, blink_alt state is supported on this LED.
17405 * If set to 0, blink_alt state is not supported on this LED.
17407 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED1_STATE_CAPS_BLINK_ALT_SUPPORTED \
17409 /* The colors supported by LED #1. */
17410 uint16_t led1_color_caps;
17412 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED1_COLOR_CAPS_RSVD \
17415 * If set to 1, Amber color is supported on this LED.
17416 * If set to 0, Amber color is not supported on this LED.
17418 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED1_COLOR_CAPS_AMBER_SUPPORTED \
17421 * If set to 1, Green color is supported on this LED.
17422 * If set to 0, Green color is not supported on this LED.
17424 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED1_COLOR_CAPS_GREEN_SUPPORTED \
17426 /* An identifier for the LED #2. */
17428 /* The type of LED #2. */
17431 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED2_TYPE_SPEED UINT32_C(0x0)
17433 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED2_TYPE_ACTIVITY UINT32_C(0x1)
17435 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED2_TYPE_INVALID UINT32_C(0xff)
17436 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED2_TYPE_LAST \
17437 HWRM_PORT_LED_QCAPS_OUTPUT_LED2_TYPE_INVALID
17439 * An identifier for the group of LEDs that LED #0 belongs
17441 * If set to 0, then the LED #0 cannot be grouped.
17442 * For all other non-zero values of this field, LED #0 is
17443 * grouped together with the LEDs with the same group ID
17446 uint8_t led2_group_id;
17448 /* The states supported by LED #2. */
17449 uint16_t led2_state_caps;
17451 * If set to 1, this LED is enabled.
17452 * If set to 0, this LED is disabled.
17454 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED2_STATE_CAPS_ENABLED \
17457 * If set to 1, off state is supported on this LED.
17458 * If set to 0, off state is not supported on this LED.
17460 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED2_STATE_CAPS_OFF_SUPPORTED \
17463 * If set to 1, on state is supported on this LED.
17464 * If set to 0, on state is not supported on this LED.
17466 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED2_STATE_CAPS_ON_SUPPORTED \
17469 * If set to 1, blink state is supported on this LED.
17470 * If set to 0, blink state is not supported on this LED.
17472 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED2_STATE_CAPS_BLINK_SUPPORTED \
17475 * If set to 1, blink_alt state is supported on this LED.
17476 * If set to 0, blink_alt state is not supported on this LED.
17478 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED2_STATE_CAPS_BLINK_ALT_SUPPORTED \
17480 /* The colors supported by LED #2. */
17481 uint16_t led2_color_caps;
17483 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED2_COLOR_CAPS_RSVD \
17486 * If set to 1, Amber color is supported on this LED.
17487 * If set to 0, Amber color is not supported on this LED.
17489 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED2_COLOR_CAPS_AMBER_SUPPORTED \
17492 * If set to 1, Green color is supported on this LED.
17493 * If set to 0, Green color is not supported on this LED.
17495 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED2_COLOR_CAPS_GREEN_SUPPORTED \
17497 /* An identifier for the LED #3. */
17499 /* The type of LED #3. */
17502 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED3_TYPE_SPEED UINT32_C(0x0)
17504 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED3_TYPE_ACTIVITY UINT32_C(0x1)
17506 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED3_TYPE_INVALID UINT32_C(0xff)
17507 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED3_TYPE_LAST \
17508 HWRM_PORT_LED_QCAPS_OUTPUT_LED3_TYPE_INVALID
17510 * An identifier for the group of LEDs that LED #3 belongs
17512 * If set to 0, then the LED #0 cannot be grouped.
17513 * For all other non-zero values of this field, LED #0 is
17514 * grouped together with the LEDs with the same group ID
17517 uint8_t led3_group_id;
17519 /* The states supported by LED #3. */
17520 uint16_t led3_state_caps;
17522 * If set to 1, this LED is enabled.
17523 * If set to 0, this LED is disabled.
17525 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED3_STATE_CAPS_ENABLED \
17528 * If set to 1, off state is supported on this LED.
17529 * If set to 0, off state is not supported on this LED.
17531 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED3_STATE_CAPS_OFF_SUPPORTED \
17534 * If set to 1, on state is supported on this LED.
17535 * If set to 0, on state is not supported on this LED.
17537 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED3_STATE_CAPS_ON_SUPPORTED \
17540 * If set to 1, blink state is supported on this LED.
17541 * If set to 0, blink state is not supported on this LED.
17543 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED3_STATE_CAPS_BLINK_SUPPORTED \
17546 * If set to 1, blink_alt state is supported on this LED.
17547 * If set to 0, blink_alt state is not supported on this LED.
17549 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED3_STATE_CAPS_BLINK_ALT_SUPPORTED \
17551 /* The colors supported by LED #3. */
17552 uint16_t led3_color_caps;
17554 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED3_COLOR_CAPS_RSVD \
17557 * If set to 1, Amber color is supported on this LED.
17558 * If set to 0, Amber color is not supported on this LED.
17560 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED3_COLOR_CAPS_AMBER_SUPPORTED \
17563 * If set to 1, Green color is supported on this LED.
17564 * If set to 0, Green color is not supported on this LED.
17566 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED3_COLOR_CAPS_GREEN_SUPPORTED \
17568 uint8_t unused_4[3];
17570 * This field is used in Output records to indicate that the output
17571 * is completely written to RAM. This field should be read as '1'
17572 * to indicate that the output has been completely written.
17573 * When writing a command completion or response to an internal processor,
17574 * the order of writes has to be such that this field is written last.
17577 } __attribute__((packed));
17579 /***********************
17580 * hwrm_port_prbs_test *
17581 ***********************/
17584 /* hwrm_port_prbs_test_input (size:384b/48B) */
17585 struct hwrm_port_prbs_test_input {
17586 /* The HWRM command request type. */
17589 * The completion ring to send the completion event on. This should
17590 * be the NQ ID returned from the `nq_alloc` HWRM command.
17592 uint16_t cmpl_ring;
17594 * The sequence ID is used by the driver for tracking multiple
17595 * commands. This ID is treated as opaque data by the firmware and
17596 * the value is returned in the `hwrm_resp_hdr` upon completion.
17600 * The target ID of the command:
17601 * * 0x0-0xFFF8 - The function ID
17602 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
17603 * * 0xFFFD - Reserved for user-space HWRM interface
17606 uint16_t target_id;
17608 * A physical address pointer pointing to a host buffer that the
17609 * command's response data will be written. This can be either a host
17610 * physical address (HPA) or a guest physical address (GPA) and must
17611 * point to a physically contiguous block of memory.
17613 uint64_t resp_addr;
17614 /* Host address data is to DMA'd to. */
17615 uint64_t resp_data_addr;
17617 * Size of the buffer pointed to by resp_data_addr. The firmware may
17618 * use this entire buffer or less than the entire buffer, but never more.
17623 /* Port ID of port where PRBS test to be run. */
17625 /* Polynomial selection for PRBS test. */
17628 #define HWRM_PORT_PRBS_TEST_INPUT_POLY_PRBS7 UINT32_C(0x0)
17630 #define HWRM_PORT_PRBS_TEST_INPUT_POLY_PRBS9 UINT32_C(0x1)
17632 #define HWRM_PORT_PRBS_TEST_INPUT_POLY_PRBS11 UINT32_C(0x2)
17634 #define HWRM_PORT_PRBS_TEST_INPUT_POLY_PRBS15 UINT32_C(0x3)
17636 #define HWRM_PORT_PRBS_TEST_INPUT_POLY_PRBS23 UINT32_C(0x4)
17638 #define HWRM_PORT_PRBS_TEST_INPUT_POLY_PRBS31 UINT32_C(0x5)
17640 #define HWRM_PORT_PRBS_TEST_INPUT_POLY_PRBS58 UINT32_C(0x6)
17642 #define HWRM_PORT_PRBS_TEST_INPUT_POLY_INVALID UINT32_C(0xff)
17643 #define HWRM_PORT_PRBS_TEST_INPUT_POLY_LAST \
17644 HWRM_PORT_PRBS_TEST_INPUT_POLY_INVALID
17646 * Configuration bits for PRBS test.
17647 * Use enable bit to start/stop test.
17648 * Use tx/rx lane map bits to run test on specific lanes,
17649 * if set to 0 test will be run on all lanes.
17651 uint16_t prbs_config;
17653 * Set 0 to stop test currently in progress
17654 * Set 1 to start test with configuration provided.
17656 #define HWRM_PORT_PRBS_TEST_INPUT_PRBS_CONFIG_START_STOP \
17659 * If set to 1, tx_lane_map bitmap should have lane bits set.
17660 * If set to 0, test will be run on all lanes for this port.
17662 #define HWRM_PORT_PRBS_TEST_INPUT_PRBS_CONFIG_TX_LANE_MAP_VALID \
17665 * If set to 1, rx_lane_map bitmap should have lane bits set.
17666 * If set to 0, test will be run on all lanes for this port.
17668 #define HWRM_PORT_PRBS_TEST_INPUT_PRBS_CONFIG_RX_LANE_MAP_VALID \
17670 /* Duration in seconds to run the PRBS test. */
17673 * If tx_lane_map_valid is set to 1, this field is a bitmap
17674 * of tx lanes to run PRBS test. bit0 = lane0,
17675 * bit1 = lane1 ..bit31 = lane31
17677 uint32_t tx_lane_map;
17679 * If rx_lane_map_valid is set to 1, this field is a bitmap
17680 * of rx lanes to run PRBS test. bit0 = lane0,
17681 * bit1 = lane1 ..bit31 = lane31
17683 uint32_t rx_lane_map;
17684 } __attribute__((packed));
17686 /* hwrm_port_prbs_test_output (size:128b/16B) */
17687 struct hwrm_port_prbs_test_output {
17688 /* The specific error status for the command. */
17689 uint16_t error_code;
17690 /* The HWRM command request type. */
17692 /* The sequence ID from the original command. */
17694 /* The length of the response data in number of bytes. */
17696 /* Total length of stored data. */
17697 uint16_t total_data_len;
17699 uint8_t unused_1[3];
17701 * This field is used in Output records to indicate that the output
17702 * is completely written to RAM. This field should be read as '1'
17703 * to indicate that the output has been completely written.
17704 * When writing a command completion or response to an internal processor,
17705 * the order of writes has to be such that this field is written last.
17708 } __attribute__((packed));
17710 /***********************
17711 * hwrm_queue_qportcfg *
17712 ***********************/
17715 /* hwrm_queue_qportcfg_input (size:192b/24B) */
17716 struct hwrm_queue_qportcfg_input {
17717 /* The HWRM command request type. */
17720 * The completion ring to send the completion event on. This should
17721 * be the NQ ID returned from the `nq_alloc` HWRM command.
17723 uint16_t cmpl_ring;
17725 * The sequence ID is used by the driver for tracking multiple
17726 * commands. This ID is treated as opaque data by the firmware and
17727 * the value is returned in the `hwrm_resp_hdr` upon completion.
17731 * The target ID of the command:
17732 * * 0x0-0xFFF8 - The function ID
17733 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
17734 * * 0xFFFD - Reserved for user-space HWRM interface
17737 uint16_t target_id;
17739 * A physical address pointer pointing to a host buffer that the
17740 * command's response data will be written. This can be either a host
17741 * physical address (HPA) or a guest physical address (GPA) and must
17742 * point to a physically contiguous block of memory.
17744 uint64_t resp_addr;
17747 * Enumeration denoting the RX, TX type of the resource.
17748 * This enumeration is used for resources that are similar for both
17749 * TX and RX paths of the chip.
17751 #define HWRM_QUEUE_QPORTCFG_INPUT_FLAGS_PATH UINT32_C(0x1)
17753 #define HWRM_QUEUE_QPORTCFG_INPUT_FLAGS_PATH_TX UINT32_C(0x0)
17755 #define HWRM_QUEUE_QPORTCFG_INPUT_FLAGS_PATH_RX UINT32_C(0x1)
17756 #define HWRM_QUEUE_QPORTCFG_INPUT_FLAGS_PATH_LAST \
17757 HWRM_QUEUE_QPORTCFG_INPUT_FLAGS_PATH_RX
17759 * Port ID of port for which the queue configuration is being
17760 * queried. This field is only required when sent by IPC.
17764 * Drivers will set this capability when it can use
17765 * queue_idx_service_profile to map the queues to application.
17767 uint8_t drv_qmap_cap;
17769 #define HWRM_QUEUE_QPORTCFG_INPUT_DRV_QMAP_CAP_DISABLED UINT32_C(0x0)
17771 #define HWRM_QUEUE_QPORTCFG_INPUT_DRV_QMAP_CAP_ENABLED UINT32_C(0x1)
17772 #define HWRM_QUEUE_QPORTCFG_INPUT_DRV_QMAP_CAP_LAST \
17773 HWRM_QUEUE_QPORTCFG_INPUT_DRV_QMAP_CAP_ENABLED
17775 } __attribute__((packed));
17777 /* hwrm_queue_qportcfg_output (size:256b/32B) */
17778 struct hwrm_queue_qportcfg_output {
17779 /* The specific error status for the command. */
17780 uint16_t error_code;
17781 /* The HWRM command request type. */
17783 /* The sequence ID from the original command. */
17785 /* The length of the response data in number of bytes. */
17788 * The maximum number of queues that can be configured on this
17790 * Valid values range from 1 through 8.
17792 uint8_t max_configurable_queues;
17794 * The maximum number of lossless queues that can be configured
17796 * Valid values range from 0 through 8.
17798 uint8_t max_configurable_lossless_queues;
17800 * Bitmask indicating which queues can be configured by the
17801 * hwrm_queue_cfg command.
17803 * Each bit represents a specific queue where bit 0 represents
17804 * queue 0 and bit 7 represents queue 7.
17805 * # A value of 0 indicates that the queue is not configurable
17806 * by the hwrm_queue_cfg command.
17807 * # A value of 1 indicates that the queue is configurable.
17808 * # A hwrm_queue_cfg command shall return error when trying to
17809 * configure a queue not configurable.
17811 uint8_t queue_cfg_allowed;
17812 /* Information about queue configuration. */
17813 uint8_t queue_cfg_info;
17815 * If this flag is set to '1', then the queues are
17816 * configured asymmetrically on TX and RX sides.
17817 * If this flag is set to '0', then the queues are
17818 * configured symmetrically on TX and RX sides. For
17819 * symmetric configuration, the queue configuration
17820 * including queue ids and service profiles on the
17821 * TX side is the same as the corresponding queue
17822 * configuration on the RX side.
17824 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_CFG_INFO_ASYM_CFG \
17827 * Bitmask indicating which queues can be configured by the
17828 * hwrm_queue_pfcenable_cfg command.
17830 * Each bit represents a specific priority where bit 0 represents
17831 * priority 0 and bit 7 represents priority 7.
17832 * # A value of 0 indicates that the priority is not configurable by
17833 * the hwrm_queue_pfcenable_cfg command.
17834 * # A value of 1 indicates that the priority is configurable.
17835 * # A hwrm_queue_pfcenable_cfg command shall return error when
17836 * trying to configure a priority that is not configurable.
17838 uint8_t queue_pfcenable_cfg_allowed;
17840 * Bitmask indicating which queues can be configured by the
17841 * hwrm_queue_pri2cos_cfg command.
17843 * Each bit represents a specific queue where bit 0 represents
17844 * queue 0 and bit 7 represents queue 7.
17845 * # A value of 0 indicates that the queue is not configurable
17846 * by the hwrm_queue_pri2cos_cfg command.
17847 * # A value of 1 indicates that the queue is configurable.
17848 * # A hwrm_queue_pri2cos_cfg command shall return error when
17849 * trying to configure a queue that is not configurable.
17851 uint8_t queue_pri2cos_cfg_allowed;
17853 * Bitmask indicating which queues can be configured by the
17854 * hwrm_queue_pri2cos_cfg command.
17856 * Each bit represents a specific queue where bit 0 represents
17857 * queue 0 and bit 7 represents queue 7.
17858 * # A value of 0 indicates that the queue is not configurable
17859 * by the hwrm_queue_pri2cos_cfg command.
17860 * # A value of 1 indicates that the queue is configurable.
17861 * # A hwrm_queue_pri2cos_cfg command shall return error when
17862 * trying to configure a queue not configurable.
17864 uint8_t queue_cos2bw_cfg_allowed;
17866 * ID of CoS Queue 0.
17869 * # This ID can be used on any subsequent call to an hwrm command
17870 * that takes a queue id.
17871 * # IDs must always be queried by this command before any use
17872 * by the driver or software.
17873 * # Any driver or software should not make any assumptions about
17875 * # A value of 0xff indicates that the queue is not available.
17876 * # Available queues may not be in sequential order.
17879 /* This value is applicable to CoS queues only. */
17880 uint8_t queue_id0_service_profile;
17881 /* Lossy (best-effort) */
17882 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID0_SERVICE_PROFILE_LOSSY \
17884 /* Lossless (legacy) */
17885 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID0_SERVICE_PROFILE_LOSSLESS \
17887 /* Lossless RoCE */
17888 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID0_SERVICE_PROFILE_LOSSLESS_ROCE \
17890 /* Lossy RoCE CNP */
17891 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID0_SERVICE_PROFILE_LOSSY_ROCE_CNP \
17894 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID0_SERVICE_PROFILE_LOSSLESS_NIC \
17896 /* Set to 0xFF... (All Fs) if there is no service profile specified */
17897 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID0_SERVICE_PROFILE_UNKNOWN \
17899 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID0_SERVICE_PROFILE_LAST \
17900 HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID0_SERVICE_PROFILE_UNKNOWN
17902 * ID of CoS Queue 1.
17905 * # This ID can be used on any subsequent call to an hwrm command
17906 * that takes a queue id.
17907 * # IDs must always be queried by this command before any use
17908 * by the driver or software.
17909 * # Any driver or software should not make any assumptions about
17911 * # A value of 0xff indicates that the queue is not available.
17912 * # Available queues may not be in sequential order.
17915 /* This value is applicable to CoS queues only. */
17916 uint8_t queue_id1_service_profile;
17917 /* Lossy (best-effort) */
17918 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID1_SERVICE_PROFILE_LOSSY \
17920 /* Lossless (legacy) */
17921 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID1_SERVICE_PROFILE_LOSSLESS \
17923 /* Lossless RoCE */
17924 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID1_SERVICE_PROFILE_LOSSLESS_ROCE \
17926 /* Lossy RoCE CNP */
17927 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID1_SERVICE_PROFILE_LOSSY_ROCE_CNP \
17930 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID1_SERVICE_PROFILE_LOSSLESS_NIC \
17932 /* Set to 0xFF... (All Fs) if there is no service profile specified */
17933 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID1_SERVICE_PROFILE_UNKNOWN \
17935 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID1_SERVICE_PROFILE_LAST \
17936 HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID1_SERVICE_PROFILE_UNKNOWN
17938 * ID of CoS Queue 2.
17941 * # This ID can be used on any subsequent call to an hwrm command
17942 * that takes a queue id.
17943 * # IDs must always be queried by this command before any use
17944 * by the driver or software.
17945 * # Any driver or software should not make any assumptions about
17947 * # A value of 0xff indicates that the queue is not available.
17948 * # Available queues may not be in sequential order.
17951 /* This value is applicable to CoS queues only. */
17952 uint8_t queue_id2_service_profile;
17953 /* Lossy (best-effort) */
17954 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID2_SERVICE_PROFILE_LOSSY \
17956 /* Lossless (legacy) */
17957 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID2_SERVICE_PROFILE_LOSSLESS \
17959 /* Lossless RoCE */
17960 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID2_SERVICE_PROFILE_LOSSLESS_ROCE \
17962 /* Lossy RoCE CNP */
17963 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID2_SERVICE_PROFILE_LOSSY_ROCE_CNP \
17966 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID2_SERVICE_PROFILE_LOSSLESS_NIC \
17968 /* Set to 0xFF... (All Fs) if there is no service profile specified */
17969 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID2_SERVICE_PROFILE_UNKNOWN \
17971 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID2_SERVICE_PROFILE_LAST \
17972 HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID2_SERVICE_PROFILE_UNKNOWN
17974 * ID of CoS Queue 3.
17977 * # This ID can be used on any subsequent call to an hwrm command
17978 * that takes a queue id.
17979 * # IDs must always be queried by this command before any use
17980 * by the driver or software.
17981 * # Any driver or software should not make any assumptions about
17983 * # A value of 0xff indicates that the queue is not available.
17984 * # Available queues may not be in sequential order.
17987 /* This value is applicable to CoS queues only. */
17988 uint8_t queue_id3_service_profile;
17989 /* Lossy (best-effort) */
17990 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID3_SERVICE_PROFILE_LOSSY \
17992 /* Lossless (legacy) */
17993 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID3_SERVICE_PROFILE_LOSSLESS \
17995 /* Lossless RoCE */
17996 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID3_SERVICE_PROFILE_LOSSLESS_ROCE \
17998 /* Lossy RoCE CNP */
17999 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID3_SERVICE_PROFILE_LOSSY_ROCE_CNP \
18002 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID3_SERVICE_PROFILE_LOSSLESS_NIC \
18004 /* Set to 0xFF... (All Fs) if there is no service profile specified */
18005 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID3_SERVICE_PROFILE_UNKNOWN \
18007 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID3_SERVICE_PROFILE_LAST \
18008 HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID3_SERVICE_PROFILE_UNKNOWN
18010 * ID of CoS Queue 4.
18013 * # This ID can be used on any subsequent call to an hwrm command
18014 * that takes a queue id.
18015 * # IDs must always be queried by this command before any use
18016 * by the driver or software.
18017 * # Any driver or software should not make any assumptions about
18019 * # A value of 0xff indicates that the queue is not available.
18020 * # Available queues may not be in sequential order.
18023 /* This value is applicable to CoS queues only. */
18024 uint8_t queue_id4_service_profile;
18025 /* Lossy (best-effort) */
18026 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID4_SERVICE_PROFILE_LOSSY \
18028 /* Lossless (legacy) */
18029 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID4_SERVICE_PROFILE_LOSSLESS \
18031 /* Lossless RoCE */
18032 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID4_SERVICE_PROFILE_LOSSLESS_ROCE \
18034 /* Lossy RoCE CNP */
18035 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID4_SERVICE_PROFILE_LOSSY_ROCE_CNP \
18038 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID4_SERVICE_PROFILE_LOSSLESS_NIC \
18040 /* Set to 0xFF... (All Fs) if there is no service profile specified */
18041 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID4_SERVICE_PROFILE_UNKNOWN \
18043 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID4_SERVICE_PROFILE_LAST \
18044 HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID4_SERVICE_PROFILE_UNKNOWN
18046 * ID of CoS Queue 5.
18049 * # This ID can be used on any subsequent call to an hwrm command
18050 * that takes a queue id.
18051 * # IDs must always be queried by this command before any use
18052 * by the driver or software.
18053 * # Any driver or software should not make any assumptions about
18055 * # A value of 0xff indicates that the queue is not available.
18056 * # Available queues may not be in sequential order.
18059 /* This value is applicable to CoS queues only. */
18060 uint8_t queue_id5_service_profile;
18061 /* Lossy (best-effort) */
18062 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID5_SERVICE_PROFILE_LOSSY \
18064 /* Lossless (legacy) */
18065 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID5_SERVICE_PROFILE_LOSSLESS \
18067 /* Lossless RoCE */
18068 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID5_SERVICE_PROFILE_LOSSLESS_ROCE \
18070 /* Lossy RoCE CNP */
18071 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID5_SERVICE_PROFILE_LOSSY_ROCE_CNP \
18074 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID5_SERVICE_PROFILE_LOSSLESS_NIC \
18076 /* Set to 0xFF... (All Fs) if there is no service profile specified */
18077 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID5_SERVICE_PROFILE_UNKNOWN \
18079 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID5_SERVICE_PROFILE_LAST \
18080 HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID5_SERVICE_PROFILE_UNKNOWN
18082 * ID of CoS Queue 6.
18085 * # This ID can be used on any subsequent call to an hwrm command
18086 * that takes a queue id.
18087 * # IDs must always be queried by this command before any use
18088 * by the driver or software.
18089 * # Any driver or software should not make any assumptions about
18091 * # A value of 0xff indicates that the queue is not available.
18092 * # Available queues may not be in sequential order.
18095 /* This value is applicable to CoS queues only. */
18096 uint8_t queue_id6_service_profile;
18097 /* Lossy (best-effort) */
18098 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID6_SERVICE_PROFILE_LOSSY \
18100 /* Lossless (legacy) */
18101 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID6_SERVICE_PROFILE_LOSSLESS \
18103 /* Lossless RoCE */
18104 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID6_SERVICE_PROFILE_LOSSLESS_ROCE \
18106 /* Lossy RoCE CNP */
18107 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID6_SERVICE_PROFILE_LOSSY_ROCE_CNP \
18110 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID6_SERVICE_PROFILE_LOSSLESS_NIC \
18112 /* Set to 0xFF... (All Fs) if there is no service profile specified */
18113 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID6_SERVICE_PROFILE_UNKNOWN \
18115 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID6_SERVICE_PROFILE_LAST \
18116 HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID6_SERVICE_PROFILE_UNKNOWN
18118 * ID of CoS Queue 7.
18121 * # This ID can be used on any subsequent call to an hwrm command
18122 * that takes a queue id.
18123 * # IDs must always be queried by this command before any use
18124 * by the driver or software.
18125 * # Any driver or software should not make any assumptions about
18127 * # A value of 0xff indicates that the queue is not available.
18128 * # Available queues may not be in sequential order.
18131 /* This value is applicable to CoS queues only. */
18132 uint8_t queue_id7_service_profile;
18133 /* Lossy (best-effort) */
18134 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID7_SERVICE_PROFILE_LOSSY \
18136 /* Lossless (legacy) */
18137 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID7_SERVICE_PROFILE_LOSSLESS \
18139 /* Lossless RoCE */
18140 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID7_SERVICE_PROFILE_LOSSLESS_ROCE \
18142 /* Lossy RoCE CNP */
18143 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID7_SERVICE_PROFILE_LOSSY_ROCE_CNP \
18146 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID7_SERVICE_PROFILE_LOSSLESS_NIC \
18148 /* Set to 0xFF... (All Fs) if there is no service profile specified */
18149 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID7_SERVICE_PROFILE_UNKNOWN \
18151 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID7_SERVICE_PROFILE_LAST \
18152 HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID7_SERVICE_PROFILE_UNKNOWN
18154 * This field is used in Output records to indicate that the output
18155 * is completely written to RAM. This field should be read as '1'
18156 * to indicate that the output has been completely written.
18157 * When writing a command completion or response to an internal processor,
18158 * the order of writes has to be such that this field is written last.
18161 } __attribute__((packed));
18163 /*******************
18164 * hwrm_queue_qcfg *
18165 *******************/
18168 /* hwrm_queue_qcfg_input (size:192b/24B) */
18169 struct hwrm_queue_qcfg_input {
18170 /* The HWRM command request type. */
18173 * The completion ring to send the completion event on. This should
18174 * be the NQ ID returned from the `nq_alloc` HWRM command.
18176 uint16_t cmpl_ring;
18178 * The sequence ID is used by the driver for tracking multiple
18179 * commands. This ID is treated as opaque data by the firmware and
18180 * the value is returned in the `hwrm_resp_hdr` upon completion.
18184 * The target ID of the command:
18185 * * 0x0-0xFFF8 - The function ID
18186 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
18187 * * 0xFFFD - Reserved for user-space HWRM interface
18190 uint16_t target_id;
18192 * A physical address pointer pointing to a host buffer that the
18193 * command's response data will be written. This can be either a host
18194 * physical address (HPA) or a guest physical address (GPA) and must
18195 * point to a physically contiguous block of memory.
18197 uint64_t resp_addr;
18200 * Enumeration denoting the RX, TX type of the resource.
18201 * This enumeration is used for resources that are similar for both
18202 * TX and RX paths of the chip.
18204 #define HWRM_QUEUE_QCFG_INPUT_FLAGS_PATH UINT32_C(0x1)
18206 #define HWRM_QUEUE_QCFG_INPUT_FLAGS_PATH_TX UINT32_C(0x0)
18208 #define HWRM_QUEUE_QCFG_INPUT_FLAGS_PATH_RX UINT32_C(0x1)
18209 #define HWRM_QUEUE_QCFG_INPUT_FLAGS_PATH_LAST \
18210 HWRM_QUEUE_QCFG_INPUT_FLAGS_PATH_RX
18211 /* Queue ID of the queue. */
18213 } __attribute__((packed));
18215 /* hwrm_queue_qcfg_output (size:128b/16B) */
18216 struct hwrm_queue_qcfg_output {
18217 /* The specific error status for the command. */
18218 uint16_t error_code;
18219 /* The HWRM command request type. */
18221 /* The sequence ID from the original command. */
18223 /* The length of the response data in number of bytes. */
18226 * This value is a the estimate packet length used in the
18229 uint32_t queue_len;
18230 /* This value is applicable to CoS queues only. */
18231 uint8_t service_profile;
18232 /* Lossy (best-effort) */
18233 #define HWRM_QUEUE_QCFG_OUTPUT_SERVICE_PROFILE_LOSSY UINT32_C(0x0)
18235 #define HWRM_QUEUE_QCFG_OUTPUT_SERVICE_PROFILE_LOSSLESS UINT32_C(0x1)
18236 /* Set to 0xFF... (All Fs) if there is no service profile specified */
18237 #define HWRM_QUEUE_QCFG_OUTPUT_SERVICE_PROFILE_UNKNOWN UINT32_C(0xff)
18238 #define HWRM_QUEUE_QCFG_OUTPUT_SERVICE_PROFILE_LAST \
18239 HWRM_QUEUE_QCFG_OUTPUT_SERVICE_PROFILE_UNKNOWN
18240 /* Information about queue configuration. */
18241 uint8_t queue_cfg_info;
18243 * If this flag is set to '1', then the queue is
18244 * configured asymmetrically on TX and RX sides.
18245 * If this flag is set to '0', then this queue is
18246 * configured symmetrically on TX and RX sides.
18248 #define HWRM_QUEUE_QCFG_OUTPUT_QUEUE_CFG_INFO_ASYM_CFG \
18252 * This field is used in Output records to indicate that the output
18253 * is completely written to RAM. This field should be read as '1'
18254 * to indicate that the output has been completely written.
18255 * When writing a command completion or response to an internal processor,
18256 * the order of writes has to be such that this field is written last.
18259 } __attribute__((packed));
18261 /******************
18263 ******************/
18266 /* hwrm_queue_cfg_input (size:320b/40B) */
18267 struct hwrm_queue_cfg_input {
18268 /* The HWRM command request type. */
18271 * The completion ring to send the completion event on. This should
18272 * be the NQ ID returned from the `nq_alloc` HWRM command.
18274 uint16_t cmpl_ring;
18276 * The sequence ID is used by the driver for tracking multiple
18277 * commands. This ID is treated as opaque data by the firmware and
18278 * the value is returned in the `hwrm_resp_hdr` upon completion.
18282 * The target ID of the command:
18283 * * 0x0-0xFFF8 - The function ID
18284 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
18285 * * 0xFFFD - Reserved for user-space HWRM interface
18288 uint16_t target_id;
18290 * A physical address pointer pointing to a host buffer that the
18291 * command's response data will be written. This can be either a host
18292 * physical address (HPA) or a guest physical address (GPA) and must
18293 * point to a physically contiguous block of memory.
18295 uint64_t resp_addr;
18298 * Enumeration denoting the RX, TX, or both directions applicable to the resource.
18299 * This enumeration is used for resources that are similar for both
18300 * TX and RX paths of the chip.
18302 #define HWRM_QUEUE_CFG_INPUT_FLAGS_PATH_MASK UINT32_C(0x3)
18303 #define HWRM_QUEUE_CFG_INPUT_FLAGS_PATH_SFT 0
18305 #define HWRM_QUEUE_CFG_INPUT_FLAGS_PATH_TX UINT32_C(0x0)
18307 #define HWRM_QUEUE_CFG_INPUT_FLAGS_PATH_RX UINT32_C(0x1)
18308 /* Bi-directional (Symmetrically applicable to TX and RX paths) */
18309 #define HWRM_QUEUE_CFG_INPUT_FLAGS_PATH_BIDIR UINT32_C(0x2)
18310 #define HWRM_QUEUE_CFG_INPUT_FLAGS_PATH_LAST \
18311 HWRM_QUEUE_CFG_INPUT_FLAGS_PATH_BIDIR
18314 * This bit must be '1' for the dflt_len field to be
18317 #define HWRM_QUEUE_CFG_INPUT_ENABLES_DFLT_LEN UINT32_C(0x1)
18319 * This bit must be '1' for the service_profile field to be
18322 #define HWRM_QUEUE_CFG_INPUT_ENABLES_SERVICE_PROFILE UINT32_C(0x2)
18323 /* Queue ID of queue that is to be configured by this function. */
18326 * This value is a the estimate packet length used in the
18328 * Set to 0xFF... (All Fs) to not adjust this value.
18331 /* This value is applicable to CoS queues only. */
18332 uint8_t service_profile;
18333 /* Lossy (best-effort) */
18334 #define HWRM_QUEUE_CFG_INPUT_SERVICE_PROFILE_LOSSY UINT32_C(0x0)
18336 #define HWRM_QUEUE_CFG_INPUT_SERVICE_PROFILE_LOSSLESS UINT32_C(0x1)
18337 /* Set to 0xFF... (All Fs) if there is no service profile specified */
18338 #define HWRM_QUEUE_CFG_INPUT_SERVICE_PROFILE_UNKNOWN UINT32_C(0xff)
18339 #define HWRM_QUEUE_CFG_INPUT_SERVICE_PROFILE_LAST \
18340 HWRM_QUEUE_CFG_INPUT_SERVICE_PROFILE_UNKNOWN
18341 uint8_t unused_0[7];
18342 } __attribute__((packed));
18344 /* hwrm_queue_cfg_output (size:128b/16B) */
18345 struct hwrm_queue_cfg_output {
18346 /* The specific error status for the command. */
18347 uint16_t error_code;
18348 /* The HWRM command request type. */
18350 /* The sequence ID from the original command. */
18352 /* The length of the response data in number of bytes. */
18354 uint8_t unused_0[7];
18356 * This field is used in Output records to indicate that the output
18357 * is completely written to RAM. This field should be read as '1'
18358 * to indicate that the output has been completely written.
18359 * When writing a command completion or response to an internal processor,
18360 * the order of writes has to be such that this field is written last.
18363 } __attribute__((packed));
18365 /*****************************
18366 * hwrm_queue_pfcenable_qcfg *
18367 *****************************/
18370 /* hwrm_queue_pfcenable_qcfg_input (size:192b/24B) */
18371 struct hwrm_queue_pfcenable_qcfg_input {
18372 /* The HWRM command request type. */
18375 * The completion ring to send the completion event on. This should
18376 * be the NQ ID returned from the `nq_alloc` HWRM command.
18378 uint16_t cmpl_ring;
18380 * The sequence ID is used by the driver for tracking multiple
18381 * commands. This ID is treated as opaque data by the firmware and
18382 * the value is returned in the `hwrm_resp_hdr` upon completion.
18386 * The target ID of the command:
18387 * * 0x0-0xFFF8 - The function ID
18388 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
18389 * * 0xFFFD - Reserved for user-space HWRM interface
18392 uint16_t target_id;
18394 * A physical address pointer pointing to a host buffer that the
18395 * command's response data will be written. This can be either a host
18396 * physical address (HPA) or a guest physical address (GPA) and must
18397 * point to a physically contiguous block of memory.
18399 uint64_t resp_addr;
18401 * Port ID of port for which the table is being configured.
18402 * The HWRM needs to check whether this function is allowed
18403 * to configure pri2cos mapping on this port.
18406 uint8_t unused_0[6];
18407 } __attribute__((packed));
18409 /* hwrm_queue_pfcenable_qcfg_output (size:128b/16B) */
18410 struct hwrm_queue_pfcenable_qcfg_output {
18411 /* The specific error status for the command. */
18412 uint16_t error_code;
18413 /* The HWRM command request type. */
18415 /* The sequence ID from the original command. */
18417 /* The length of the response data in number of bytes. */
18420 /* If set to 1, then PFC is enabled on PRI 0. */
18421 #define HWRM_QUEUE_PFCENABLE_QCFG_OUTPUT_FLAGS_PRI0_PFC_ENABLED \
18423 /* If set to 1, then PFC is enabled on PRI 1. */
18424 #define HWRM_QUEUE_PFCENABLE_QCFG_OUTPUT_FLAGS_PRI1_PFC_ENABLED \
18426 /* If set to 1, then PFC is enabled on PRI 2. */
18427 #define HWRM_QUEUE_PFCENABLE_QCFG_OUTPUT_FLAGS_PRI2_PFC_ENABLED \
18429 /* If set to 1, then PFC is enabled on PRI 3. */
18430 #define HWRM_QUEUE_PFCENABLE_QCFG_OUTPUT_FLAGS_PRI3_PFC_ENABLED \
18432 /* If set to 1, then PFC is enabled on PRI 4. */
18433 #define HWRM_QUEUE_PFCENABLE_QCFG_OUTPUT_FLAGS_PRI4_PFC_ENABLED \
18435 /* If set to 1, then PFC is enabled on PRI 5. */
18436 #define HWRM_QUEUE_PFCENABLE_QCFG_OUTPUT_FLAGS_PRI5_PFC_ENABLED \
18438 /* If set to 1, then PFC is enabled on PRI 6. */
18439 #define HWRM_QUEUE_PFCENABLE_QCFG_OUTPUT_FLAGS_PRI6_PFC_ENABLED \
18441 /* If set to 1, then PFC is enabled on PRI 7. */
18442 #define HWRM_QUEUE_PFCENABLE_QCFG_OUTPUT_FLAGS_PRI7_PFC_ENABLED \
18444 uint8_t unused_0[3];
18446 * This field is used in Output records to indicate that the output
18447 * is completely written to RAM. This field should be read as '1'
18448 * to indicate that the output has been completely written.
18449 * When writing a command completion or response to an internal processor,
18450 * the order of writes has to be such that this field is written last.
18453 } __attribute__((packed));
18455 /****************************
18456 * hwrm_queue_pfcenable_cfg *
18457 ****************************/
18460 /* hwrm_queue_pfcenable_cfg_input (size:192b/24B) */
18461 struct hwrm_queue_pfcenable_cfg_input {
18462 /* The HWRM command request type. */
18465 * The completion ring to send the completion event on. This should
18466 * be the NQ ID returned from the `nq_alloc` HWRM command.
18468 uint16_t cmpl_ring;
18470 * The sequence ID is used by the driver for tracking multiple
18471 * commands. This ID is treated as opaque data by the firmware and
18472 * the value is returned in the `hwrm_resp_hdr` upon completion.
18476 * The target ID of the command:
18477 * * 0x0-0xFFF8 - The function ID
18478 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
18479 * * 0xFFFD - Reserved for user-space HWRM interface
18482 uint16_t target_id;
18484 * A physical address pointer pointing to a host buffer that the
18485 * command's response data will be written. This can be either a host
18486 * physical address (HPA) or a guest physical address (GPA) and must
18487 * point to a physically contiguous block of memory.
18489 uint64_t resp_addr;
18491 /* If set to 1, then PFC is requested to be enabled on PRI 0. */
18492 #define HWRM_QUEUE_PFCENABLE_CFG_INPUT_FLAGS_PRI0_PFC_ENABLED \
18494 /* If set to 1, then PFC is requested to be enabled on PRI 1. */
18495 #define HWRM_QUEUE_PFCENABLE_CFG_INPUT_FLAGS_PRI1_PFC_ENABLED \
18497 /* If set to 1, then PFC is requested to be enabled on PRI 2. */
18498 #define HWRM_QUEUE_PFCENABLE_CFG_INPUT_FLAGS_PRI2_PFC_ENABLED \
18500 /* If set to 1, then PFC is requested to be enabled on PRI 3. */
18501 #define HWRM_QUEUE_PFCENABLE_CFG_INPUT_FLAGS_PRI3_PFC_ENABLED \
18503 /* If set to 1, then PFC is requested to be enabled on PRI 4. */
18504 #define HWRM_QUEUE_PFCENABLE_CFG_INPUT_FLAGS_PRI4_PFC_ENABLED \
18506 /* If set to 1, then PFC is requested to be enabled on PRI 5. */
18507 #define HWRM_QUEUE_PFCENABLE_CFG_INPUT_FLAGS_PRI5_PFC_ENABLED \
18509 /* If set to 1, then PFC is requested to be enabled on PRI 6. */
18510 #define HWRM_QUEUE_PFCENABLE_CFG_INPUT_FLAGS_PRI6_PFC_ENABLED \
18512 /* If set to 1, then PFC is requested to be enabled on PRI 7. */
18513 #define HWRM_QUEUE_PFCENABLE_CFG_INPUT_FLAGS_PRI7_PFC_ENABLED \
18516 * Port ID of port for which the table is being configured.
18517 * The HWRM needs to check whether this function is allowed
18518 * to configure pri2cos mapping on this port.
18521 uint8_t unused_0[2];
18522 } __attribute__((packed));
18524 /* hwrm_queue_pfcenable_cfg_output (size:128b/16B) */
18525 struct hwrm_queue_pfcenable_cfg_output {
18526 /* The specific error status for the command. */
18527 uint16_t error_code;
18528 /* The HWRM command request type. */
18530 /* The sequence ID from the original command. */
18532 /* The length of the response data in number of bytes. */
18534 uint8_t unused_0[7];
18536 * This field is used in Output records to indicate that the output
18537 * is completely written to RAM. This field should be read as '1'
18538 * to indicate that the output has been completely written.
18539 * When writing a command completion or response to an internal processor,
18540 * the order of writes has to be such that this field is written last.
18543 } __attribute__((packed));
18545 /***************************
18546 * hwrm_queue_pri2cos_qcfg *
18547 ***************************/
18550 /* hwrm_queue_pri2cos_qcfg_input (size:192b/24B) */
18551 struct hwrm_queue_pri2cos_qcfg_input {
18552 /* The HWRM command request type. */
18555 * The completion ring to send the completion event on. This should
18556 * be the NQ ID returned from the `nq_alloc` HWRM command.
18558 uint16_t cmpl_ring;
18560 * The sequence ID is used by the driver for tracking multiple
18561 * commands. This ID is treated as opaque data by the firmware and
18562 * the value is returned in the `hwrm_resp_hdr` upon completion.
18566 * The target ID of the command:
18567 * * 0x0-0xFFF8 - The function ID
18568 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
18569 * * 0xFFFD - Reserved for user-space HWRM interface
18572 uint16_t target_id;
18574 * A physical address pointer pointing to a host buffer that the
18575 * command's response data will be written. This can be either a host
18576 * physical address (HPA) or a guest physical address (GPA) and must
18577 * point to a physically contiguous block of memory.
18579 uint64_t resp_addr;
18582 * Enumeration denoting the RX, TX type of the resource.
18583 * This enumeration is used for resources that are similar for both
18584 * TX and RX paths of the chip.
18586 #define HWRM_QUEUE_PRI2COS_QCFG_INPUT_FLAGS_PATH UINT32_C(0x1)
18588 #define HWRM_QUEUE_PRI2COS_QCFG_INPUT_FLAGS_PATH_TX UINT32_C(0x0)
18590 #define HWRM_QUEUE_PRI2COS_QCFG_INPUT_FLAGS_PATH_RX UINT32_C(0x1)
18591 #define HWRM_QUEUE_PRI2COS_QCFG_INPUT_FLAGS_PATH_LAST \
18592 HWRM_QUEUE_PRI2COS_QCFG_INPUT_FLAGS_PATH_RX
18594 * When this bit is set to '0', the query is
18595 * for VLAN PRI field in tunnel headers.
18596 * When this bit is set to '1', the query is
18597 * for VLAN PRI field in inner packet headers.
18599 #define HWRM_QUEUE_PRI2COS_QCFG_INPUT_FLAGS_IVLAN UINT32_C(0x2)
18601 * Port ID of port for which the table is being configured.
18602 * The HWRM needs to check whether this function is allowed
18603 * to configure pri2cos mapping on this port.
18606 uint8_t unused_0[3];
18607 } __attribute__((packed));
18609 /* hwrm_queue_pri2cos_qcfg_output (size:192b/24B) */
18610 struct hwrm_queue_pri2cos_qcfg_output {
18611 /* The specific error status for the command. */
18612 uint16_t error_code;
18613 /* The HWRM command request type. */
18615 /* The sequence ID from the original command. */
18617 /* The length of the response data in number of bytes. */
18620 * CoS Queue assigned to priority 0. This value can only
18621 * be changed before traffic has started.
18622 * A value of 0xff indicates that no CoS queue is assigned to the
18623 * specified priority.
18625 uint8_t pri0_cos_queue_id;
18627 * CoS Queue assigned to priority 1. This value can only
18628 * be changed before traffic has started.
18629 * A value of 0xff indicates that no CoS queue is assigned to the
18630 * specified priority.
18632 uint8_t pri1_cos_queue_id;
18634 * CoS Queue assigned to priority 2 This value can only
18635 * be changed before traffic has started.
18636 * A value of 0xff indicates that no CoS queue is assigned to the
18637 * specified priority.
18639 uint8_t pri2_cos_queue_id;
18641 * CoS Queue assigned to priority 3. This value can only
18642 * be changed before traffic has started.
18643 * A value of 0xff indicates that no CoS queue is assigned to the
18644 * specified priority.
18646 uint8_t pri3_cos_queue_id;
18648 * CoS Queue assigned to priority 4. This value can only
18649 * be changed before traffic has started.
18650 * A value of 0xff indicates that no CoS queue is assigned to the
18651 * specified priority.
18653 uint8_t pri4_cos_queue_id;
18655 * CoS Queue assigned to priority 5. This value can only
18656 * be changed before traffic has started.
18657 * A value of 0xff indicates that no CoS queue is assigned to the
18658 * specified priority.
18660 uint8_t pri5_cos_queue_id;
18662 * CoS Queue assigned to priority 6. This value can only
18663 * be changed before traffic has started.
18664 * A value of 0xff indicates that no CoS queue is assigned to the
18665 * specified priority.
18667 uint8_t pri6_cos_queue_id;
18669 * CoS Queue assigned to priority 7. This value can only
18670 * be changed before traffic has started.
18671 * A value of 0xff indicates that no CoS queue is assigned to the
18672 * specified priority.
18674 uint8_t pri7_cos_queue_id;
18675 /* Information about queue configuration. */
18676 uint8_t queue_cfg_info;
18678 * If this flag is set to '1', then the PRI to CoS
18679 * configuration is asymmetric on TX and RX sides.
18680 * If this flag is set to '0', then PRI to CoS configuration
18681 * is symmetric on TX and RX sides.
18683 #define HWRM_QUEUE_PRI2COS_QCFG_OUTPUT_QUEUE_CFG_INFO_ASYM_CFG \
18685 uint8_t unused_0[6];
18687 * This field is used in Output records to indicate that the output
18688 * is completely written to RAM. This field should be read as '1'
18689 * to indicate that the output has been completely written.
18690 * When writing a command completion or response to an internal processor,
18691 * the order of writes has to be such that this field is written last.
18694 } __attribute__((packed));
18696 /**************************
18697 * hwrm_queue_pri2cos_cfg *
18698 **************************/
18701 /* hwrm_queue_pri2cos_cfg_input (size:320b/40B) */
18702 struct hwrm_queue_pri2cos_cfg_input {
18703 /* The HWRM command request type. */
18706 * The completion ring to send the completion event on. This should
18707 * be the NQ ID returned from the `nq_alloc` HWRM command.
18709 uint16_t cmpl_ring;
18711 * The sequence ID is used by the driver for tracking multiple
18712 * commands. This ID is treated as opaque data by the firmware and
18713 * the value is returned in the `hwrm_resp_hdr` upon completion.
18717 * The target ID of the command:
18718 * * 0x0-0xFFF8 - The function ID
18719 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
18720 * * 0xFFFD - Reserved for user-space HWRM interface
18723 uint16_t target_id;
18725 * A physical address pointer pointing to a host buffer that the
18726 * command's response data will be written. This can be either a host
18727 * physical address (HPA) or a guest physical address (GPA) and must
18728 * point to a physically contiguous block of memory.
18730 uint64_t resp_addr;
18733 * Enumeration denoting the RX, TX, or both directions applicable to the resource.
18734 * This enumeration is used for resources that are similar for both
18735 * TX and RX paths of the chip.
18737 #define HWRM_QUEUE_PRI2COS_CFG_INPUT_FLAGS_PATH_MASK UINT32_C(0x3)
18738 #define HWRM_QUEUE_PRI2COS_CFG_INPUT_FLAGS_PATH_SFT 0
18740 #define HWRM_QUEUE_PRI2COS_CFG_INPUT_FLAGS_PATH_TX UINT32_C(0x0)
18742 #define HWRM_QUEUE_PRI2COS_CFG_INPUT_FLAGS_PATH_RX UINT32_C(0x1)
18743 /* Bi-directional (Symmetrically applicable to TX and RX paths) */
18744 #define HWRM_QUEUE_PRI2COS_CFG_INPUT_FLAGS_PATH_BIDIR UINT32_C(0x2)
18745 #define HWRM_QUEUE_PRI2COS_CFG_INPUT_FLAGS_PATH_LAST \
18746 HWRM_QUEUE_PRI2COS_CFG_INPUT_FLAGS_PATH_BIDIR
18748 * When this bit is set to '0', the mapping is requested
18749 * for VLAN PRI field in tunnel headers.
18750 * When this bit is set to '1', the mapping is requested
18751 * for VLAN PRI field in inner packet headers.
18753 #define HWRM_QUEUE_PRI2COS_CFG_INPUT_FLAGS_IVLAN UINT32_C(0x4)
18756 * This bit must be '1' for the pri0_cos_queue_id field to be
18759 #define HWRM_QUEUE_PRI2COS_CFG_INPUT_ENABLES_PRI0_COS_QUEUE_ID \
18762 * This bit must be '1' for the pri1_cos_queue_id field to be
18765 #define HWRM_QUEUE_PRI2COS_CFG_INPUT_ENABLES_PRI1_COS_QUEUE_ID \
18768 * This bit must be '1' for the pri2_cos_queue_id field to be
18771 #define HWRM_QUEUE_PRI2COS_CFG_INPUT_ENABLES_PRI2_COS_QUEUE_ID \
18774 * This bit must be '1' for the pri3_cos_queue_id field to be
18777 #define HWRM_QUEUE_PRI2COS_CFG_INPUT_ENABLES_PRI3_COS_QUEUE_ID \
18780 * This bit must be '1' for the pri4_cos_queue_id field to be
18783 #define HWRM_QUEUE_PRI2COS_CFG_INPUT_ENABLES_PRI4_COS_QUEUE_ID \
18786 * This bit must be '1' for the pri5_cos_queue_id field to be
18789 #define HWRM_QUEUE_PRI2COS_CFG_INPUT_ENABLES_PRI5_COS_QUEUE_ID \
18792 * This bit must be '1' for the pri6_cos_queue_id field to be
18795 #define HWRM_QUEUE_PRI2COS_CFG_INPUT_ENABLES_PRI6_COS_QUEUE_ID \
18798 * This bit must be '1' for the pri7_cos_queue_id field to be
18801 #define HWRM_QUEUE_PRI2COS_CFG_INPUT_ENABLES_PRI7_COS_QUEUE_ID \
18804 * Port ID of port for which the table is being configured.
18805 * The HWRM needs to check whether this function is allowed
18806 * to configure pri2cos mapping on this port.
18810 * CoS Queue assigned to priority 0. This value can only
18811 * be changed before traffic has started.
18813 uint8_t pri0_cos_queue_id;
18815 * CoS Queue assigned to priority 1. This value can only
18816 * be changed before traffic has started.
18818 uint8_t pri1_cos_queue_id;
18820 * CoS Queue assigned to priority 2 This value can only
18821 * be changed before traffic has started.
18823 uint8_t pri2_cos_queue_id;
18825 * CoS Queue assigned to priority 3. This value can only
18826 * be changed before traffic has started.
18828 uint8_t pri3_cos_queue_id;
18830 * CoS Queue assigned to priority 4. This value can only
18831 * be changed before traffic has started.
18833 uint8_t pri4_cos_queue_id;
18835 * CoS Queue assigned to priority 5. This value can only
18836 * be changed before traffic has started.
18838 uint8_t pri5_cos_queue_id;
18840 * CoS Queue assigned to priority 6. This value can only
18841 * be changed before traffic has started.
18843 uint8_t pri6_cos_queue_id;
18845 * CoS Queue assigned to priority 7. This value can only
18846 * be changed before traffic has started.
18848 uint8_t pri7_cos_queue_id;
18849 uint8_t unused_0[7];
18850 } __attribute__((packed));
18852 /* hwrm_queue_pri2cos_cfg_output (size:128b/16B) */
18853 struct hwrm_queue_pri2cos_cfg_output {
18854 /* The specific error status for the command. */
18855 uint16_t error_code;
18856 /* The HWRM command request type. */
18858 /* The sequence ID from the original command. */
18860 /* The length of the response data in number of bytes. */
18862 uint8_t unused_0[7];
18864 * This field is used in Output records to indicate that the output
18865 * is completely written to RAM. This field should be read as '1'
18866 * to indicate that the output has been completely written.
18867 * When writing a command completion or response to an internal processor,
18868 * the order of writes has to be such that this field is written last.
18871 } __attribute__((packed));
18873 /**************************
18874 * hwrm_queue_cos2bw_qcfg *
18875 **************************/
18878 /* hwrm_queue_cos2bw_qcfg_input (size:192b/24B) */
18879 struct hwrm_queue_cos2bw_qcfg_input {
18880 /* The HWRM command request type. */
18883 * The completion ring to send the completion event on. This should
18884 * be the NQ ID returned from the `nq_alloc` HWRM command.
18886 uint16_t cmpl_ring;
18888 * The sequence ID is used by the driver for tracking multiple
18889 * commands. This ID is treated as opaque data by the firmware and
18890 * the value is returned in the `hwrm_resp_hdr` upon completion.
18894 * The target ID of the command:
18895 * * 0x0-0xFFF8 - The function ID
18896 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
18897 * * 0xFFFD - Reserved for user-space HWRM interface
18900 uint16_t target_id;
18902 * A physical address pointer pointing to a host buffer that the
18903 * command's response data will be written. This can be either a host
18904 * physical address (HPA) or a guest physical address (GPA) and must
18905 * point to a physically contiguous block of memory.
18907 uint64_t resp_addr;
18909 * Port ID of port for which the table is being configured.
18910 * The HWRM needs to check whether this function is allowed
18911 * to configure TC BW assignment on this port.
18914 uint8_t unused_0[6];
18915 } __attribute__((packed));
18917 /* hwrm_queue_cos2bw_qcfg_output (size:896b/112B) */
18918 struct hwrm_queue_cos2bw_qcfg_output {
18919 /* The specific error status for the command. */
18920 uint16_t error_code;
18921 /* The HWRM command request type. */
18923 /* The sequence ID from the original command. */
18925 /* The length of the response data in number of bytes. */
18927 /* ID of CoS Queue 0. */
18932 * Minimum BW allocated to CoS Queue.
18933 * The HWRM will translate this value into byte counter and
18934 * time interval used for this COS inside the device.
18936 uint32_t queue_id0_min_bw;
18937 /* The bandwidth value. */
18938 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MIN_BW_BW_VALUE_MASK \
18939 UINT32_C(0xfffffff)
18940 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MIN_BW_BW_VALUE_SFT \
18942 /* The granularity of the value (bits or bytes). */
18943 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MIN_BW_SCALE \
18944 UINT32_C(0x10000000)
18945 /* Value is in bits. */
18946 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MIN_BW_SCALE_BITS \
18947 (UINT32_C(0x0) << 28)
18948 /* Value is in bytes. */
18949 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MIN_BW_SCALE_BYTES \
18950 (UINT32_C(0x1) << 28)
18951 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MIN_BW_SCALE_LAST \
18952 HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MIN_BW_SCALE_BYTES
18953 /* bw_value_unit is 3 b */
18954 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_MASK \
18955 UINT32_C(0xe0000000)
18956 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_SFT \
18958 /* Value is in Mb or MB (base 10). */
18959 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_MEGA \
18960 (UINT32_C(0x0) << 29)
18961 /* Value is in Kb or KB (base 10). */
18962 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_KILO \
18963 (UINT32_C(0x2) << 29)
18964 /* Value is in bits or bytes. */
18965 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_BASE \
18966 (UINT32_C(0x4) << 29)
18967 /* Value is in Gb or GB (base 10). */
18968 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_GIGA \
18969 (UINT32_C(0x6) << 29)
18970 /* Value is in 1/100th of a percentage of total bandwidth. */
18971 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 \
18972 (UINT32_C(0x1) << 29)
18974 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_INVALID \
18975 (UINT32_C(0x7) << 29)
18976 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_LAST \
18977 HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_INVALID
18979 * Maximum BW allocated to CoS Queue.
18980 * The HWRM will translate this value into byte counter and
18981 * time interval used for this COS inside the device.
18983 uint32_t queue_id0_max_bw;
18984 /* The bandwidth value. */
18985 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MAX_BW_BW_VALUE_MASK \
18986 UINT32_C(0xfffffff)
18987 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MAX_BW_BW_VALUE_SFT \
18989 /* The granularity of the value (bits or bytes). */
18990 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MAX_BW_SCALE \
18991 UINT32_C(0x10000000)
18992 /* Value is in bits. */
18993 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MAX_BW_SCALE_BITS \
18994 (UINT32_C(0x0) << 28)
18995 /* Value is in bytes. */
18996 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MAX_BW_SCALE_BYTES \
18997 (UINT32_C(0x1) << 28)
18998 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MAX_BW_SCALE_LAST \
18999 HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MAX_BW_SCALE_BYTES
19000 /* bw_value_unit is 3 b */
19001 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_MASK \
19002 UINT32_C(0xe0000000)
19003 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_SFT \
19005 /* Value is in Mb or MB (base 10). */
19006 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_MEGA \
19007 (UINT32_C(0x0) << 29)
19008 /* Value is in Kb or KB (base 10). */
19009 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_KILO \
19010 (UINT32_C(0x2) << 29)
19011 /* Value is in bits or bytes. */
19012 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_BASE \
19013 (UINT32_C(0x4) << 29)
19014 /* Value is in Gb or GB (base 10). */
19015 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_GIGA \
19016 (UINT32_C(0x6) << 29)
19017 /* Value is in 1/100th of a percentage of total bandwidth. */
19018 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 \
19019 (UINT32_C(0x1) << 29)
19021 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_INVALID \
19022 (UINT32_C(0x7) << 29)
19023 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_LAST \
19024 HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_INVALID
19025 /* Transmission Selection Algorithm (TSA) for CoS Queue. */
19026 uint8_t queue_id0_tsa_assign;
19027 /* Strict Priority */
19028 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_TSA_ASSIGN_SP \
19030 /* Enhanced Transmission Selection */
19031 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_TSA_ASSIGN_ETS \
19034 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_TSA_ASSIGN_RESERVED_FIRST \
19037 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_TSA_ASSIGN_RESERVED_LAST \
19040 * Priority level for strict priority. Valid only when the
19041 * tsa_assign is 0 - Strict Priority (SP)
19042 * 0..7 - Valid values.
19043 * 8..255 - Reserved.
19045 uint8_t queue_id0_pri_lvl;
19047 * Weight used to allocate remaining BW for this COS after
19048 * servicing guaranteed bandwidths for all COS.
19050 uint8_t queue_id0_bw_weight;
19051 /* ID of CoS Queue 1. */
19054 * Minimum BW allocated to CoS Queue.
19055 * The HWRM will translate this value into byte counter and
19056 * time interval used for this COS inside the device.
19058 uint32_t queue_id1_min_bw;
19059 /* The bandwidth value. */
19060 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MIN_BW_BW_VALUE_MASK \
19061 UINT32_C(0xfffffff)
19062 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MIN_BW_BW_VALUE_SFT \
19064 /* The granularity of the value (bits or bytes). */
19065 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MIN_BW_SCALE \
19066 UINT32_C(0x10000000)
19067 /* Value is in bits. */
19068 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MIN_BW_SCALE_BITS \
19069 (UINT32_C(0x0) << 28)
19070 /* Value is in bytes. */
19071 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MIN_BW_SCALE_BYTES \
19072 (UINT32_C(0x1) << 28)
19073 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MIN_BW_SCALE_LAST \
19074 HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MIN_BW_SCALE_BYTES
19075 /* bw_value_unit is 3 b */
19076 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_MASK \
19077 UINT32_C(0xe0000000)
19078 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_SFT \
19080 /* Value is in Mb or MB (base 10). */
19081 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_MEGA \
19082 (UINT32_C(0x0) << 29)
19083 /* Value is in Kb or KB (base 10). */
19084 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_KILO \
19085 (UINT32_C(0x2) << 29)
19086 /* Value is in bits or bytes. */
19087 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_BASE \
19088 (UINT32_C(0x4) << 29)
19089 /* Value is in Gb or GB (base 10). */
19090 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_GIGA \
19091 (UINT32_C(0x6) << 29)
19092 /* Value is in 1/100th of a percentage of total bandwidth. */
19093 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 \
19094 (UINT32_C(0x1) << 29)
19096 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_INVALID \
19097 (UINT32_C(0x7) << 29)
19098 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_LAST \
19099 HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_INVALID
19101 * Maximum BW allocated to CoS queue.
19102 * The HWRM will translate this value into byte counter and
19103 * time interval used for this COS inside the device.
19105 uint32_t queue_id1_max_bw;
19106 /* The bandwidth value. */
19107 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MAX_BW_BW_VALUE_MASK \
19108 UINT32_C(0xfffffff)
19109 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MAX_BW_BW_VALUE_SFT \
19111 /* The granularity of the value (bits or bytes). */
19112 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MAX_BW_SCALE \
19113 UINT32_C(0x10000000)
19114 /* Value is in bits. */
19115 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MAX_BW_SCALE_BITS \
19116 (UINT32_C(0x0) << 28)
19117 /* Value is in bytes. */
19118 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MAX_BW_SCALE_BYTES \
19119 (UINT32_C(0x1) << 28)
19120 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MAX_BW_SCALE_LAST \
19121 HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MAX_BW_SCALE_BYTES
19122 /* bw_value_unit is 3 b */
19123 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_MASK \
19124 UINT32_C(0xe0000000)
19125 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_SFT \
19127 /* Value is in Mb or MB (base 10). */
19128 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_MEGA \
19129 (UINT32_C(0x0) << 29)
19130 /* Value is in Kb or KB (base 10). */
19131 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_KILO \
19132 (UINT32_C(0x2) << 29)
19133 /* Value is in bits or bytes. */
19134 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_BASE \
19135 (UINT32_C(0x4) << 29)
19136 /* Value is in Gb or GB (base 10). */
19137 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_GIGA \
19138 (UINT32_C(0x6) << 29)
19139 /* Value is in 1/100th of a percentage of total bandwidth. */
19140 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 \
19141 (UINT32_C(0x1) << 29)
19143 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_INVALID \
19144 (UINT32_C(0x7) << 29)
19145 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_LAST \
19146 HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_INVALID
19147 /* Transmission Selection Algorithm (TSA) for CoS Queue. */
19148 uint8_t queue_id1_tsa_assign;
19149 /* Strict Priority */
19150 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_TSA_ASSIGN_SP \
19152 /* Enhanced Transmission Selection */
19153 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_TSA_ASSIGN_ETS \
19156 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_TSA_ASSIGN_RESERVED_FIRST \
19159 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_TSA_ASSIGN_RESERVED_LAST \
19162 * Priority level for strict priority. Valid only when the
19163 * tsa_assign is 0 - Strict Priority (SP)
19164 * 0..7 - Valid values.
19165 * 8..255 - Reserved.
19167 uint8_t queue_id1_pri_lvl;
19169 * Weight used to allocate remaining BW for this COS after
19170 * servicing guaranteed bandwidths for all COS.
19172 uint8_t queue_id1_bw_weight;
19173 /* ID of CoS Queue 2. */
19176 * Minimum BW allocated to CoS Queue.
19177 * The HWRM will translate this value into byte counter and
19178 * time interval used for this COS inside the device.
19180 uint32_t queue_id2_min_bw;
19181 /* The bandwidth value. */
19182 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MIN_BW_BW_VALUE_MASK \
19183 UINT32_C(0xfffffff)
19184 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MIN_BW_BW_VALUE_SFT \
19186 /* The granularity of the value (bits or bytes). */
19187 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MIN_BW_SCALE \
19188 UINT32_C(0x10000000)
19189 /* Value is in bits. */
19190 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MIN_BW_SCALE_BITS \
19191 (UINT32_C(0x0) << 28)
19192 /* Value is in bytes. */
19193 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MIN_BW_SCALE_BYTES \
19194 (UINT32_C(0x1) << 28)
19195 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MIN_BW_SCALE_LAST \
19196 HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MIN_BW_SCALE_BYTES
19197 /* bw_value_unit is 3 b */
19198 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_MASK \
19199 UINT32_C(0xe0000000)
19200 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_SFT \
19202 /* Value is in Mb or MB (base 10). */
19203 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_MEGA \
19204 (UINT32_C(0x0) << 29)
19205 /* Value is in Kb or KB (base 10). */
19206 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_KILO \
19207 (UINT32_C(0x2) << 29)
19208 /* Value is in bits or bytes. */
19209 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_BASE \
19210 (UINT32_C(0x4) << 29)
19211 /* Value is in Gb or GB (base 10). */
19212 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_GIGA \
19213 (UINT32_C(0x6) << 29)
19214 /* Value is in 1/100th of a percentage of total bandwidth. */
19215 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 \
19216 (UINT32_C(0x1) << 29)
19218 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_INVALID \
19219 (UINT32_C(0x7) << 29)
19220 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_LAST \
19221 HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_INVALID
19223 * Maximum BW allocated to CoS queue.
19224 * The HWRM will translate this value into byte counter and
19225 * time interval used for this COS inside the device.
19227 uint32_t queue_id2_max_bw;
19228 /* The bandwidth value. */
19229 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MAX_BW_BW_VALUE_MASK \
19230 UINT32_C(0xfffffff)
19231 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MAX_BW_BW_VALUE_SFT \
19233 /* The granularity of the value (bits or bytes). */
19234 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MAX_BW_SCALE \
19235 UINT32_C(0x10000000)
19236 /* Value is in bits. */
19237 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MAX_BW_SCALE_BITS \
19238 (UINT32_C(0x0) << 28)
19239 /* Value is in bytes. */
19240 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MAX_BW_SCALE_BYTES \
19241 (UINT32_C(0x1) << 28)
19242 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MAX_BW_SCALE_LAST \
19243 HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MAX_BW_SCALE_BYTES
19244 /* bw_value_unit is 3 b */
19245 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_MASK \
19246 UINT32_C(0xe0000000)
19247 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_SFT \
19249 /* Value is in Mb or MB (base 10). */
19250 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_MEGA \
19251 (UINT32_C(0x0) << 29)
19252 /* Value is in Kb or KB (base 10). */
19253 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_KILO \
19254 (UINT32_C(0x2) << 29)
19255 /* Value is in bits or bytes. */
19256 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_BASE \
19257 (UINT32_C(0x4) << 29)
19258 /* Value is in Gb or GB (base 10). */
19259 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_GIGA \
19260 (UINT32_C(0x6) << 29)
19261 /* Value is in 1/100th of a percentage of total bandwidth. */
19262 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 \
19263 (UINT32_C(0x1) << 29)
19265 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_INVALID \
19266 (UINT32_C(0x7) << 29)
19267 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_LAST \
19268 HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_INVALID
19269 /* Transmission Selection Algorithm (TSA) for CoS Queue. */
19270 uint8_t queue_id2_tsa_assign;
19271 /* Strict Priority */
19272 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_TSA_ASSIGN_SP \
19274 /* Enhanced Transmission Selection */
19275 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_TSA_ASSIGN_ETS \
19278 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_TSA_ASSIGN_RESERVED_FIRST \
19281 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_TSA_ASSIGN_RESERVED_LAST \
19284 * Priority level for strict priority. Valid only when the
19285 * tsa_assign is 0 - Strict Priority (SP)
19286 * 0..7 - Valid values.
19287 * 8..255 - Reserved.
19289 uint8_t queue_id2_pri_lvl;
19291 * Weight used to allocate remaining BW for this COS after
19292 * servicing guaranteed bandwidths for all COS.
19294 uint8_t queue_id2_bw_weight;
19295 /* ID of CoS Queue 3. */
19298 * Minimum BW allocated to CoS Queue.
19299 * The HWRM will translate this value into byte counter and
19300 * time interval used for this COS inside the device.
19302 uint32_t queue_id3_min_bw;
19303 /* The bandwidth value. */
19304 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MIN_BW_BW_VALUE_MASK \
19305 UINT32_C(0xfffffff)
19306 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MIN_BW_BW_VALUE_SFT \
19308 /* The granularity of the value (bits or bytes). */
19309 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MIN_BW_SCALE \
19310 UINT32_C(0x10000000)
19311 /* Value is in bits. */
19312 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MIN_BW_SCALE_BITS \
19313 (UINT32_C(0x0) << 28)
19314 /* Value is in bytes. */
19315 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MIN_BW_SCALE_BYTES \
19316 (UINT32_C(0x1) << 28)
19317 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MIN_BW_SCALE_LAST \
19318 HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MIN_BW_SCALE_BYTES
19319 /* bw_value_unit is 3 b */
19320 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_MASK \
19321 UINT32_C(0xe0000000)
19322 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_SFT \
19324 /* Value is in Mb or MB (base 10). */
19325 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_MEGA \
19326 (UINT32_C(0x0) << 29)
19327 /* Value is in Kb or KB (base 10). */
19328 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_KILO \
19329 (UINT32_C(0x2) << 29)
19330 /* Value is in bits or bytes. */
19331 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_BASE \
19332 (UINT32_C(0x4) << 29)
19333 /* Value is in Gb or GB (base 10). */
19334 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_GIGA \
19335 (UINT32_C(0x6) << 29)
19336 /* Value is in 1/100th of a percentage of total bandwidth. */
19337 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 \
19338 (UINT32_C(0x1) << 29)
19340 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_INVALID \
19341 (UINT32_C(0x7) << 29)
19342 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_LAST \
19343 HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_INVALID
19345 * Maximum BW allocated to CoS queue.
19346 * The HWRM will translate this value into byte counter and
19347 * time interval used for this COS inside the device.
19349 uint32_t queue_id3_max_bw;
19350 /* The bandwidth value. */
19351 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MAX_BW_BW_VALUE_MASK \
19352 UINT32_C(0xfffffff)
19353 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MAX_BW_BW_VALUE_SFT \
19355 /* The granularity of the value (bits or bytes). */
19356 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MAX_BW_SCALE \
19357 UINT32_C(0x10000000)
19358 /* Value is in bits. */
19359 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MAX_BW_SCALE_BITS \
19360 (UINT32_C(0x0) << 28)
19361 /* Value is in bytes. */
19362 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MAX_BW_SCALE_BYTES \
19363 (UINT32_C(0x1) << 28)
19364 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MAX_BW_SCALE_LAST \
19365 HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MAX_BW_SCALE_BYTES
19366 /* bw_value_unit is 3 b */
19367 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_MASK \
19368 UINT32_C(0xe0000000)
19369 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_SFT \
19371 /* Value is in Mb or MB (base 10). */
19372 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_MEGA \
19373 (UINT32_C(0x0) << 29)
19374 /* Value is in Kb or KB (base 10). */
19375 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_KILO \
19376 (UINT32_C(0x2) << 29)
19377 /* Value is in bits or bytes. */
19378 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_BASE \
19379 (UINT32_C(0x4) << 29)
19380 /* Value is in Gb or GB (base 10). */
19381 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_GIGA \
19382 (UINT32_C(0x6) << 29)
19383 /* Value is in 1/100th of a percentage of total bandwidth. */
19384 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 \
19385 (UINT32_C(0x1) << 29)
19387 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_INVALID \
19388 (UINT32_C(0x7) << 29)
19389 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_LAST \
19390 HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_INVALID
19391 /* Transmission Selection Algorithm (TSA) for CoS Queue. */
19392 uint8_t queue_id3_tsa_assign;
19393 /* Strict Priority */
19394 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_TSA_ASSIGN_SP \
19396 /* Enhanced Transmission Selection */
19397 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_TSA_ASSIGN_ETS \
19400 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_TSA_ASSIGN_RESERVED_FIRST \
19403 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_TSA_ASSIGN_RESERVED_LAST \
19406 * Priority level for strict priority. Valid only when the
19407 * tsa_assign is 0 - Strict Priority (SP)
19408 * 0..7 - Valid values.
19409 * 8..255 - Reserved.
19411 uint8_t queue_id3_pri_lvl;
19413 * Weight used to allocate remaining BW for this COS after
19414 * servicing guaranteed bandwidths for all COS.
19416 uint8_t queue_id3_bw_weight;
19417 /* ID of CoS Queue 4. */
19420 * Minimum BW allocated to CoS Queue.
19421 * The HWRM will translate this value into byte counter and
19422 * time interval used for this COS inside the device.
19424 uint32_t queue_id4_min_bw;
19425 /* The bandwidth value. */
19426 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MIN_BW_BW_VALUE_MASK \
19427 UINT32_C(0xfffffff)
19428 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MIN_BW_BW_VALUE_SFT \
19430 /* The granularity of the value (bits or bytes). */
19431 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MIN_BW_SCALE \
19432 UINT32_C(0x10000000)
19433 /* Value is in bits. */
19434 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MIN_BW_SCALE_BITS \
19435 (UINT32_C(0x0) << 28)
19436 /* Value is in bytes. */
19437 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MIN_BW_SCALE_BYTES \
19438 (UINT32_C(0x1) << 28)
19439 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MIN_BW_SCALE_LAST \
19440 HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MIN_BW_SCALE_BYTES
19441 /* bw_value_unit is 3 b */
19442 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_MASK \
19443 UINT32_C(0xe0000000)
19444 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_SFT \
19446 /* Value is in Mb or MB (base 10). */
19447 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_MEGA \
19448 (UINT32_C(0x0) << 29)
19449 /* Value is in Kb or KB (base 10). */
19450 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_KILO \
19451 (UINT32_C(0x2) << 29)
19452 /* Value is in bits or bytes. */
19453 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_BASE \
19454 (UINT32_C(0x4) << 29)
19455 /* Value is in Gb or GB (base 10). */
19456 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_GIGA \
19457 (UINT32_C(0x6) << 29)
19458 /* Value is in 1/100th of a percentage of total bandwidth. */
19459 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 \
19460 (UINT32_C(0x1) << 29)
19462 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_INVALID \
19463 (UINT32_C(0x7) << 29)
19464 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_LAST \
19465 HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_INVALID
19467 * Maximum BW allocated to CoS queue.
19468 * The HWRM will translate this value into byte counter and
19469 * time interval used for this COS inside the device.
19471 uint32_t queue_id4_max_bw;
19472 /* The bandwidth value. */
19473 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MAX_BW_BW_VALUE_MASK \
19474 UINT32_C(0xfffffff)
19475 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MAX_BW_BW_VALUE_SFT \
19477 /* The granularity of the value (bits or bytes). */
19478 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MAX_BW_SCALE \
19479 UINT32_C(0x10000000)
19480 /* Value is in bits. */
19481 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MAX_BW_SCALE_BITS \
19482 (UINT32_C(0x0) << 28)
19483 /* Value is in bytes. */
19484 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MAX_BW_SCALE_BYTES \
19485 (UINT32_C(0x1) << 28)
19486 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MAX_BW_SCALE_LAST \
19487 HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MAX_BW_SCALE_BYTES
19488 /* bw_value_unit is 3 b */
19489 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_MASK \
19490 UINT32_C(0xe0000000)
19491 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_SFT \
19493 /* Value is in Mb or MB (base 10). */
19494 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_MEGA \
19495 (UINT32_C(0x0) << 29)
19496 /* Value is in Kb or KB (base 10). */
19497 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_KILO \
19498 (UINT32_C(0x2) << 29)
19499 /* Value is in bits or bytes. */
19500 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_BASE \
19501 (UINT32_C(0x4) << 29)
19502 /* Value is in Gb or GB (base 10). */
19503 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_GIGA \
19504 (UINT32_C(0x6) << 29)
19505 /* Value is in 1/100th of a percentage of total bandwidth. */
19506 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 \
19507 (UINT32_C(0x1) << 29)
19509 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_INVALID \
19510 (UINT32_C(0x7) << 29)
19511 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_LAST \
19512 HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_INVALID
19513 /* Transmission Selection Algorithm (TSA) for CoS Queue. */
19514 uint8_t queue_id4_tsa_assign;
19515 /* Strict Priority */
19516 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_TSA_ASSIGN_SP \
19518 /* Enhanced Transmission Selection */
19519 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_TSA_ASSIGN_ETS \
19522 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_TSA_ASSIGN_RESERVED_FIRST \
19525 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_TSA_ASSIGN_RESERVED_LAST \
19528 * Priority level for strict priority. Valid only when the
19529 * tsa_assign is 0 - Strict Priority (SP)
19530 * 0..7 - Valid values.
19531 * 8..255 - Reserved.
19533 uint8_t queue_id4_pri_lvl;
19535 * Weight used to allocate remaining BW for this COS after
19536 * servicing guaranteed bandwidths for all COS.
19538 uint8_t queue_id4_bw_weight;
19539 /* ID of CoS Queue 5. */
19542 * Minimum BW allocated to CoS Queue.
19543 * The HWRM will translate this value into byte counter and
19544 * time interval used for this COS inside the device.
19546 uint32_t queue_id5_min_bw;
19547 /* The bandwidth value. */
19548 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MIN_BW_BW_VALUE_MASK \
19549 UINT32_C(0xfffffff)
19550 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MIN_BW_BW_VALUE_SFT \
19552 /* The granularity of the value (bits or bytes). */
19553 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MIN_BW_SCALE \
19554 UINT32_C(0x10000000)
19555 /* Value is in bits. */
19556 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MIN_BW_SCALE_BITS \
19557 (UINT32_C(0x0) << 28)
19558 /* Value is in bytes. */
19559 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MIN_BW_SCALE_BYTES \
19560 (UINT32_C(0x1) << 28)
19561 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MIN_BW_SCALE_LAST \
19562 HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MIN_BW_SCALE_BYTES
19563 /* bw_value_unit is 3 b */
19564 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_MASK \
19565 UINT32_C(0xe0000000)
19566 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_SFT \
19568 /* Value is in Mb or MB (base 10). */
19569 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_MEGA \
19570 (UINT32_C(0x0) << 29)
19571 /* Value is in Kb or KB (base 10). */
19572 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_KILO \
19573 (UINT32_C(0x2) << 29)
19574 /* Value is in bits or bytes. */
19575 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_BASE \
19576 (UINT32_C(0x4) << 29)
19577 /* Value is in Gb or GB (base 10). */
19578 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_GIGA \
19579 (UINT32_C(0x6) << 29)
19580 /* Value is in 1/100th of a percentage of total bandwidth. */
19581 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 \
19582 (UINT32_C(0x1) << 29)
19584 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_INVALID \
19585 (UINT32_C(0x7) << 29)
19586 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_LAST \
19587 HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_INVALID
19589 * Maximum BW allocated to CoS queue.
19590 * The HWRM will translate this value into byte counter and
19591 * time interval used for this COS inside the device.
19593 uint32_t queue_id5_max_bw;
19594 /* The bandwidth value. */
19595 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MAX_BW_BW_VALUE_MASK \
19596 UINT32_C(0xfffffff)
19597 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MAX_BW_BW_VALUE_SFT \
19599 /* The granularity of the value (bits or bytes). */
19600 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MAX_BW_SCALE \
19601 UINT32_C(0x10000000)
19602 /* Value is in bits. */
19603 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MAX_BW_SCALE_BITS \
19604 (UINT32_C(0x0) << 28)
19605 /* Value is in bytes. */
19606 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MAX_BW_SCALE_BYTES \
19607 (UINT32_C(0x1) << 28)
19608 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MAX_BW_SCALE_LAST \
19609 HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MAX_BW_SCALE_BYTES
19610 /* bw_value_unit is 3 b */
19611 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_MASK \
19612 UINT32_C(0xe0000000)
19613 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_SFT \
19615 /* Value is in Mb or MB (base 10). */
19616 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_MEGA \
19617 (UINT32_C(0x0) << 29)
19618 /* Value is in Kb or KB (base 10). */
19619 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_KILO \
19620 (UINT32_C(0x2) << 29)
19621 /* Value is in bits or bytes. */
19622 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_BASE \
19623 (UINT32_C(0x4) << 29)
19624 /* Value is in Gb or GB (base 10). */
19625 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_GIGA \
19626 (UINT32_C(0x6) << 29)
19627 /* Value is in 1/100th of a percentage of total bandwidth. */
19628 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 \
19629 (UINT32_C(0x1) << 29)
19631 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_INVALID \
19632 (UINT32_C(0x7) << 29)
19633 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_LAST \
19634 HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_INVALID
19635 /* Transmission Selection Algorithm (TSA) for CoS Queue. */
19636 uint8_t queue_id5_tsa_assign;
19637 /* Strict Priority */
19638 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_TSA_ASSIGN_SP \
19640 /* Enhanced Transmission Selection */
19641 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_TSA_ASSIGN_ETS \
19644 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_TSA_ASSIGN_RESERVED_FIRST \
19647 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_TSA_ASSIGN_RESERVED_LAST \
19650 * Priority level for strict priority. Valid only when the
19651 * tsa_assign is 0 - Strict Priority (SP)
19652 * 0..7 - Valid values.
19653 * 8..255 - Reserved.
19655 uint8_t queue_id5_pri_lvl;
19657 * Weight used to allocate remaining BW for this COS after
19658 * servicing guaranteed bandwidths for all COS.
19660 uint8_t queue_id5_bw_weight;
19661 /* ID of CoS Queue 6. */
19664 * Minimum BW allocated to CoS Queue.
19665 * The HWRM will translate this value into byte counter and
19666 * time interval used for this COS inside the device.
19668 uint32_t queue_id6_min_bw;
19669 /* The bandwidth value. */
19670 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MIN_BW_BW_VALUE_MASK \
19671 UINT32_C(0xfffffff)
19672 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MIN_BW_BW_VALUE_SFT \
19674 /* The granularity of the value (bits or bytes). */
19675 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MIN_BW_SCALE \
19676 UINT32_C(0x10000000)
19677 /* Value is in bits. */
19678 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MIN_BW_SCALE_BITS \
19679 (UINT32_C(0x0) << 28)
19680 /* Value is in bytes. */
19681 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MIN_BW_SCALE_BYTES \
19682 (UINT32_C(0x1) << 28)
19683 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MIN_BW_SCALE_LAST \
19684 HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MIN_BW_SCALE_BYTES
19685 /* bw_value_unit is 3 b */
19686 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_MASK \
19687 UINT32_C(0xe0000000)
19688 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_SFT \
19690 /* Value is in Mb or MB (base 10). */
19691 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_MEGA \
19692 (UINT32_C(0x0) << 29)
19693 /* Value is in Kb or KB (base 10). */
19694 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_KILO \
19695 (UINT32_C(0x2) << 29)
19696 /* Value is in bits or bytes. */
19697 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_BASE \
19698 (UINT32_C(0x4) << 29)
19699 /* Value is in Gb or GB (base 10). */
19700 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_GIGA \
19701 (UINT32_C(0x6) << 29)
19702 /* Value is in 1/100th of a percentage of total bandwidth. */
19703 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 \
19704 (UINT32_C(0x1) << 29)
19706 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_INVALID \
19707 (UINT32_C(0x7) << 29)
19708 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_LAST \
19709 HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_INVALID
19711 * Maximum BW allocated to CoS queue.
19712 * The HWRM will translate this value into byte counter and
19713 * time interval used for this COS inside the device.
19715 uint32_t queue_id6_max_bw;
19716 /* The bandwidth value. */
19717 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MAX_BW_BW_VALUE_MASK \
19718 UINT32_C(0xfffffff)
19719 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MAX_BW_BW_VALUE_SFT \
19721 /* The granularity of the value (bits or bytes). */
19722 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MAX_BW_SCALE \
19723 UINT32_C(0x10000000)
19724 /* Value is in bits. */
19725 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MAX_BW_SCALE_BITS \
19726 (UINT32_C(0x0) << 28)
19727 /* Value is in bytes. */
19728 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MAX_BW_SCALE_BYTES \
19729 (UINT32_C(0x1) << 28)
19730 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MAX_BW_SCALE_LAST \
19731 HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MAX_BW_SCALE_BYTES
19732 /* bw_value_unit is 3 b */
19733 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_MASK \
19734 UINT32_C(0xe0000000)
19735 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_SFT \
19737 /* Value is in Mb or MB (base 10). */
19738 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_MEGA \
19739 (UINT32_C(0x0) << 29)
19740 /* Value is in Kb or KB (base 10). */
19741 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_KILO \
19742 (UINT32_C(0x2) << 29)
19743 /* Value is in bits or bytes. */
19744 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_BASE \
19745 (UINT32_C(0x4) << 29)
19746 /* Value is in Gb or GB (base 10). */
19747 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_GIGA \
19748 (UINT32_C(0x6) << 29)
19749 /* Value is in 1/100th of a percentage of total bandwidth. */
19750 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 \
19751 (UINT32_C(0x1) << 29)
19753 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_INVALID \
19754 (UINT32_C(0x7) << 29)
19755 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_LAST \
19756 HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_INVALID
19757 /* Transmission Selection Algorithm (TSA) for CoS Queue. */
19758 uint8_t queue_id6_tsa_assign;
19759 /* Strict Priority */
19760 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_TSA_ASSIGN_SP \
19762 /* Enhanced Transmission Selection */
19763 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_TSA_ASSIGN_ETS \
19766 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_TSA_ASSIGN_RESERVED_FIRST \
19769 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_TSA_ASSIGN_RESERVED_LAST \
19772 * Priority level for strict priority. Valid only when the
19773 * tsa_assign is 0 - Strict Priority (SP)
19774 * 0..7 - Valid values.
19775 * 8..255 - Reserved.
19777 uint8_t queue_id6_pri_lvl;
19779 * Weight used to allocate remaining BW for this COS after
19780 * servicing guaranteed bandwidths for all COS.
19782 uint8_t queue_id6_bw_weight;
19783 /* ID of CoS Queue 7. */
19786 * Minimum BW allocated to CoS Queue.
19787 * The HWRM will translate this value into byte counter and
19788 * time interval used for this COS inside the device.
19790 uint32_t queue_id7_min_bw;
19791 /* The bandwidth value. */
19792 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MIN_BW_BW_VALUE_MASK \
19793 UINT32_C(0xfffffff)
19794 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MIN_BW_BW_VALUE_SFT \
19796 /* The granularity of the value (bits or bytes). */
19797 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MIN_BW_SCALE \
19798 UINT32_C(0x10000000)
19799 /* Value is in bits. */
19800 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MIN_BW_SCALE_BITS \
19801 (UINT32_C(0x0) << 28)
19802 /* Value is in bytes. */
19803 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MIN_BW_SCALE_BYTES \
19804 (UINT32_C(0x1) << 28)
19805 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MIN_BW_SCALE_LAST \
19806 HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MIN_BW_SCALE_BYTES
19807 /* bw_value_unit is 3 b */
19808 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_MASK \
19809 UINT32_C(0xe0000000)
19810 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_SFT \
19812 /* Value is in Mb or MB (base 10). */
19813 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_MEGA \
19814 (UINT32_C(0x0) << 29)
19815 /* Value is in Kb or KB (base 10). */
19816 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_KILO \
19817 (UINT32_C(0x2) << 29)
19818 /* Value is in bits or bytes. */
19819 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_BASE \
19820 (UINT32_C(0x4) << 29)
19821 /* Value is in Gb or GB (base 10). */
19822 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_GIGA \
19823 (UINT32_C(0x6) << 29)
19824 /* Value is in 1/100th of a percentage of total bandwidth. */
19825 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 \
19826 (UINT32_C(0x1) << 29)
19828 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_INVALID \
19829 (UINT32_C(0x7) << 29)
19830 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_LAST \
19831 HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_INVALID
19833 * Maximum BW allocated to CoS queue.
19834 * The HWRM will translate this value into byte counter and
19835 * time interval used for this COS inside the device.
19837 uint32_t queue_id7_max_bw;
19838 /* The bandwidth value. */
19839 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MAX_BW_BW_VALUE_MASK \
19840 UINT32_C(0xfffffff)
19841 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MAX_BW_BW_VALUE_SFT \
19843 /* The granularity of the value (bits or bytes). */
19844 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MAX_BW_SCALE \
19845 UINT32_C(0x10000000)
19846 /* Value is in bits. */
19847 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MAX_BW_SCALE_BITS \
19848 (UINT32_C(0x0) << 28)
19849 /* Value is in bytes. */
19850 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MAX_BW_SCALE_BYTES \
19851 (UINT32_C(0x1) << 28)
19852 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MAX_BW_SCALE_LAST \
19853 HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MAX_BW_SCALE_BYTES
19854 /* bw_value_unit is 3 b */
19855 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_MASK \
19856 UINT32_C(0xe0000000)
19857 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_SFT \
19859 /* Value is in Mb or MB (base 10). */
19860 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_MEGA \
19861 (UINT32_C(0x0) << 29)
19862 /* Value is in Kb or KB (base 10). */
19863 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_KILO \
19864 (UINT32_C(0x2) << 29)
19865 /* Value is in bits or bytes. */
19866 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_BASE \
19867 (UINT32_C(0x4) << 29)
19868 /* Value is in Gb or GB (base 10). */
19869 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_GIGA \
19870 (UINT32_C(0x6) << 29)
19871 /* Value is in 1/100th of a percentage of total bandwidth. */
19872 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 \
19873 (UINT32_C(0x1) << 29)
19875 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_INVALID \
19876 (UINT32_C(0x7) << 29)
19877 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_LAST \
19878 HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_INVALID
19879 /* Transmission Selection Algorithm (TSA) for CoS Queue. */
19880 uint8_t queue_id7_tsa_assign;
19881 /* Strict Priority */
19882 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_TSA_ASSIGN_SP \
19884 /* Enhanced Transmission Selection */
19885 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_TSA_ASSIGN_ETS \
19888 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_TSA_ASSIGN_RESERVED_FIRST \
19891 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_TSA_ASSIGN_RESERVED_LAST \
19894 * Priority level for strict priority. Valid only when the
19895 * tsa_assign is 0 - Strict Priority (SP)
19896 * 0..7 - Valid values.
19897 * 8..255 - Reserved.
19899 uint8_t queue_id7_pri_lvl;
19901 * Weight used to allocate remaining BW for this COS after
19902 * servicing guaranteed bandwidths for all COS.
19904 uint8_t queue_id7_bw_weight;
19905 uint8_t unused_2[4];
19907 * This field is used in Output records to indicate that the output
19908 * is completely written to RAM. This field should be read as '1'
19909 * to indicate that the output has been completely written.
19910 * When writing a command completion or response to an internal processor,
19911 * the order of writes has to be such that this field is written last.
19914 } __attribute__((packed));
19916 /*************************
19917 * hwrm_queue_cos2bw_cfg *
19918 *************************/
19921 /* hwrm_queue_cos2bw_cfg_input (size:1024b/128B) */
19922 struct hwrm_queue_cos2bw_cfg_input {
19923 /* The HWRM command request type. */
19926 * The completion ring to send the completion event on. This should
19927 * be the NQ ID returned from the `nq_alloc` HWRM command.
19929 uint16_t cmpl_ring;
19931 * The sequence ID is used by the driver for tracking multiple
19932 * commands. This ID is treated as opaque data by the firmware and
19933 * the value is returned in the `hwrm_resp_hdr` upon completion.
19937 * The target ID of the command:
19938 * * 0x0-0xFFF8 - The function ID
19939 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
19940 * * 0xFFFD - Reserved for user-space HWRM interface
19943 uint16_t target_id;
19945 * A physical address pointer pointing to a host buffer that the
19946 * command's response data will be written. This can be either a host
19947 * physical address (HPA) or a guest physical address (GPA) and must
19948 * point to a physically contiguous block of memory.
19950 uint64_t resp_addr;
19954 * If this bit is set to 1, then all queue_id0 related
19955 * parameters in this command are valid.
19957 #define HWRM_QUEUE_COS2BW_CFG_INPUT_ENABLES_COS_QUEUE_ID0_VALID \
19960 * If this bit is set to 1, then all queue_id1 related
19961 * parameters in this command are valid.
19963 #define HWRM_QUEUE_COS2BW_CFG_INPUT_ENABLES_COS_QUEUE_ID1_VALID \
19966 * If this bit is set to 1, then all queue_id2 related
19967 * parameters in this command are valid.
19969 #define HWRM_QUEUE_COS2BW_CFG_INPUT_ENABLES_COS_QUEUE_ID2_VALID \
19972 * If this bit is set to 1, then all queue_id3 related
19973 * parameters in this command are valid.
19975 #define HWRM_QUEUE_COS2BW_CFG_INPUT_ENABLES_COS_QUEUE_ID3_VALID \
19978 * If this bit is set to 1, then all queue_id4 related
19979 * parameters in this command are valid.
19981 #define HWRM_QUEUE_COS2BW_CFG_INPUT_ENABLES_COS_QUEUE_ID4_VALID \
19984 * If this bit is set to 1, then all queue_id5 related
19985 * parameters in this command are valid.
19987 #define HWRM_QUEUE_COS2BW_CFG_INPUT_ENABLES_COS_QUEUE_ID5_VALID \
19990 * If this bit is set to 1, then all queue_id6 related
19991 * parameters in this command are valid.
19993 #define HWRM_QUEUE_COS2BW_CFG_INPUT_ENABLES_COS_QUEUE_ID6_VALID \
19996 * If this bit is set to 1, then all queue_id7 related
19997 * parameters in this command are valid.
19999 #define HWRM_QUEUE_COS2BW_CFG_INPUT_ENABLES_COS_QUEUE_ID7_VALID \
20002 * Port ID of port for which the table is being configured.
20003 * The HWRM needs to check whether this function is allowed
20004 * to configure TC BW assignment on this port.
20007 /* ID of CoS Queue 0. */
20011 * Minimum BW allocated to CoS Queue.
20012 * The HWRM will translate this value into byte counter and
20013 * time interval used for this COS inside the device.
20015 uint32_t queue_id0_min_bw;
20016 /* The bandwidth value. */
20017 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MIN_BW_BW_VALUE_MASK \
20018 UINT32_C(0xfffffff)
20019 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MIN_BW_BW_VALUE_SFT \
20021 /* The granularity of the value (bits or bytes). */
20022 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MIN_BW_SCALE \
20023 UINT32_C(0x10000000)
20024 /* Value is in bits. */
20025 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MIN_BW_SCALE_BITS \
20026 (UINT32_C(0x0) << 28)
20027 /* Value is in bytes. */
20028 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MIN_BW_SCALE_BYTES \
20029 (UINT32_C(0x1) << 28)
20030 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MIN_BW_SCALE_LAST \
20031 HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MIN_BW_SCALE_BYTES
20032 /* bw_value_unit is 3 b */
20033 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_MASK \
20034 UINT32_C(0xe0000000)
20035 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_SFT \
20037 /* Value is in Mb or MB (base 10). */
20038 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_MEGA \
20039 (UINT32_C(0x0) << 29)
20040 /* Value is in Kb or KB (base 10). */
20041 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_KILO \
20042 (UINT32_C(0x2) << 29)
20043 /* Value is in bits or bytes. */
20044 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_BASE \
20045 (UINT32_C(0x4) << 29)
20046 /* Value is in Gb or GB (base 10). */
20047 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_GIGA \
20048 (UINT32_C(0x6) << 29)
20049 /* Value is in 1/100th of a percentage of total bandwidth. */
20050 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 \
20051 (UINT32_C(0x1) << 29)
20053 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_INVALID \
20054 (UINT32_C(0x7) << 29)
20055 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_LAST \
20056 HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_INVALID
20058 * Maximum BW allocated to CoS Queue.
20059 * The HWRM will translate this value into byte counter and
20060 * time interval used for this COS inside the device.
20062 uint32_t queue_id0_max_bw;
20063 /* The bandwidth value. */
20064 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MAX_BW_BW_VALUE_MASK \
20065 UINT32_C(0xfffffff)
20066 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MAX_BW_BW_VALUE_SFT \
20068 /* The granularity of the value (bits or bytes). */
20069 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MAX_BW_SCALE \
20070 UINT32_C(0x10000000)
20071 /* Value is in bits. */
20072 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MAX_BW_SCALE_BITS \
20073 (UINT32_C(0x0) << 28)
20074 /* Value is in bytes. */
20075 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MAX_BW_SCALE_BYTES \
20076 (UINT32_C(0x1) << 28)
20077 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MAX_BW_SCALE_LAST \
20078 HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MAX_BW_SCALE_BYTES
20079 /* bw_value_unit is 3 b */
20080 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_MASK \
20081 UINT32_C(0xe0000000)
20082 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_SFT \
20084 /* Value is in Mb or MB (base 10). */
20085 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_MEGA \
20086 (UINT32_C(0x0) << 29)
20087 /* Value is in Kb or KB (base 10). */
20088 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_KILO \
20089 (UINT32_C(0x2) << 29)
20090 /* Value is in bits or bytes. */
20091 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_BASE \
20092 (UINT32_C(0x4) << 29)
20093 /* Value is in Gb or GB (base 10). */
20094 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_GIGA \
20095 (UINT32_C(0x6) << 29)
20096 /* Value is in 1/100th of a percentage of total bandwidth. */
20097 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 \
20098 (UINT32_C(0x1) << 29)
20100 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_INVALID \
20101 (UINT32_C(0x7) << 29)
20102 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_LAST \
20103 HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_INVALID
20104 /* Transmission Selection Algorithm (TSA) for CoS Queue. */
20105 uint8_t queue_id0_tsa_assign;
20106 /* Strict Priority */
20107 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_TSA_ASSIGN_SP \
20109 /* Enhanced Transmission Selection */
20110 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_TSA_ASSIGN_ETS \
20113 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_TSA_ASSIGN_RESERVED_FIRST \
20116 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_TSA_ASSIGN_RESERVED_LAST \
20119 * Priority level for strict priority. Valid only when the
20120 * tsa_assign is 0 - Strict Priority (SP)
20121 * 0..7 - Valid values.
20122 * 8..255 - Reserved.
20124 uint8_t queue_id0_pri_lvl;
20126 * Weight used to allocate remaining BW for this COS after
20127 * servicing guaranteed bandwidths for all COS.
20129 uint8_t queue_id0_bw_weight;
20130 /* ID of CoS Queue 1. */
20133 * Minimum BW allocated to CoS Queue.
20134 * The HWRM will translate this value into byte counter and
20135 * time interval used for this COS inside the device.
20137 uint32_t queue_id1_min_bw;
20138 /* The bandwidth value. */
20139 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MIN_BW_BW_VALUE_MASK \
20140 UINT32_C(0xfffffff)
20141 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MIN_BW_BW_VALUE_SFT \
20143 /* The granularity of the value (bits or bytes). */
20144 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MIN_BW_SCALE \
20145 UINT32_C(0x10000000)
20146 /* Value is in bits. */
20147 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MIN_BW_SCALE_BITS \
20148 (UINT32_C(0x0) << 28)
20149 /* Value is in bytes. */
20150 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MIN_BW_SCALE_BYTES \
20151 (UINT32_C(0x1) << 28)
20152 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MIN_BW_SCALE_LAST \
20153 HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MIN_BW_SCALE_BYTES
20154 /* bw_value_unit is 3 b */
20155 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_MASK \
20156 UINT32_C(0xe0000000)
20157 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_SFT \
20159 /* Value is in Mb or MB (base 10). */
20160 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_MEGA \
20161 (UINT32_C(0x0) << 29)
20162 /* Value is in Kb or KB (base 10). */
20163 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_KILO \
20164 (UINT32_C(0x2) << 29)
20165 /* Value is in bits or bytes. */
20166 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_BASE \
20167 (UINT32_C(0x4) << 29)
20168 /* Value is in Gb or GB (base 10). */
20169 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_GIGA \
20170 (UINT32_C(0x6) << 29)
20171 /* Value is in 1/100th of a percentage of total bandwidth. */
20172 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 \
20173 (UINT32_C(0x1) << 29)
20175 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_INVALID \
20176 (UINT32_C(0x7) << 29)
20177 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_LAST \
20178 HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_INVALID
20180 * Maximum BW allocated to CoS queue.
20181 * The HWRM will translate this value into byte counter and
20182 * time interval used for this COS inside the device.
20184 uint32_t queue_id1_max_bw;
20185 /* The bandwidth value. */
20186 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MAX_BW_BW_VALUE_MASK \
20187 UINT32_C(0xfffffff)
20188 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MAX_BW_BW_VALUE_SFT \
20190 /* The granularity of the value (bits or bytes). */
20191 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MAX_BW_SCALE \
20192 UINT32_C(0x10000000)
20193 /* Value is in bits. */
20194 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MAX_BW_SCALE_BITS \
20195 (UINT32_C(0x0) << 28)
20196 /* Value is in bytes. */
20197 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MAX_BW_SCALE_BYTES \
20198 (UINT32_C(0x1) << 28)
20199 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MAX_BW_SCALE_LAST \
20200 HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MAX_BW_SCALE_BYTES
20201 /* bw_value_unit is 3 b */
20202 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_MASK \
20203 UINT32_C(0xe0000000)
20204 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_SFT \
20206 /* Value is in Mb or MB (base 10). */
20207 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_MEGA \
20208 (UINT32_C(0x0) << 29)
20209 /* Value is in Kb or KB (base 10). */
20210 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_KILO \
20211 (UINT32_C(0x2) << 29)
20212 /* Value is in bits or bytes. */
20213 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_BASE \
20214 (UINT32_C(0x4) << 29)
20215 /* Value is in Gb or GB (base 10). */
20216 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_GIGA \
20217 (UINT32_C(0x6) << 29)
20218 /* Value is in 1/100th of a percentage of total bandwidth. */
20219 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 \
20220 (UINT32_C(0x1) << 29)
20222 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_INVALID \
20223 (UINT32_C(0x7) << 29)
20224 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_LAST \
20225 HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_INVALID
20226 /* Transmission Selection Algorithm (TSA) for CoS Queue. */
20227 uint8_t queue_id1_tsa_assign;
20228 /* Strict Priority */
20229 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_TSA_ASSIGN_SP \
20231 /* Enhanced Transmission Selection */
20232 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_TSA_ASSIGN_ETS \
20235 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_TSA_ASSIGN_RESERVED_FIRST \
20238 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_TSA_ASSIGN_RESERVED_LAST \
20241 * Priority level for strict priority. Valid only when the
20242 * tsa_assign is 0 - Strict Priority (SP)
20243 * 0..7 - Valid values.
20244 * 8..255 - Reserved.
20246 uint8_t queue_id1_pri_lvl;
20248 * Weight used to allocate remaining BW for this COS after
20249 * servicing guaranteed bandwidths for all COS.
20251 uint8_t queue_id1_bw_weight;
20252 /* ID of CoS Queue 2. */
20255 * Minimum BW allocated to CoS Queue.
20256 * The HWRM will translate this value into byte counter and
20257 * time interval used for this COS inside the device.
20259 uint32_t queue_id2_min_bw;
20260 /* The bandwidth value. */
20261 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MIN_BW_BW_VALUE_MASK \
20262 UINT32_C(0xfffffff)
20263 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MIN_BW_BW_VALUE_SFT \
20265 /* The granularity of the value (bits or bytes). */
20266 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MIN_BW_SCALE \
20267 UINT32_C(0x10000000)
20268 /* Value is in bits. */
20269 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MIN_BW_SCALE_BITS \
20270 (UINT32_C(0x0) << 28)
20271 /* Value is in bytes. */
20272 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MIN_BW_SCALE_BYTES \
20273 (UINT32_C(0x1) << 28)
20274 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MIN_BW_SCALE_LAST \
20275 HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MIN_BW_SCALE_BYTES
20276 /* bw_value_unit is 3 b */
20277 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_MASK \
20278 UINT32_C(0xe0000000)
20279 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_SFT \
20281 /* Value is in Mb or MB (base 10). */
20282 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_MEGA \
20283 (UINT32_C(0x0) << 29)
20284 /* Value is in Kb or KB (base 10). */
20285 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_KILO \
20286 (UINT32_C(0x2) << 29)
20287 /* Value is in bits or bytes. */
20288 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_BASE \
20289 (UINT32_C(0x4) << 29)
20290 /* Value is in Gb or GB (base 10). */
20291 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_GIGA \
20292 (UINT32_C(0x6) << 29)
20293 /* Value is in 1/100th of a percentage of total bandwidth. */
20294 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 \
20295 (UINT32_C(0x1) << 29)
20297 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_INVALID \
20298 (UINT32_C(0x7) << 29)
20299 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_LAST \
20300 HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_INVALID
20302 * Maximum BW allocated to CoS queue.
20303 * The HWRM will translate this value into byte counter and
20304 * time interval used for this COS inside the device.
20306 uint32_t queue_id2_max_bw;
20307 /* The bandwidth value. */
20308 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MAX_BW_BW_VALUE_MASK \
20309 UINT32_C(0xfffffff)
20310 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MAX_BW_BW_VALUE_SFT \
20312 /* The granularity of the value (bits or bytes). */
20313 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MAX_BW_SCALE \
20314 UINT32_C(0x10000000)
20315 /* Value is in bits. */
20316 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MAX_BW_SCALE_BITS \
20317 (UINT32_C(0x0) << 28)
20318 /* Value is in bytes. */
20319 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MAX_BW_SCALE_BYTES \
20320 (UINT32_C(0x1) << 28)
20321 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MAX_BW_SCALE_LAST \
20322 HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MAX_BW_SCALE_BYTES
20323 /* bw_value_unit is 3 b */
20324 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_MASK \
20325 UINT32_C(0xe0000000)
20326 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_SFT \
20328 /* Value is in Mb or MB (base 10). */
20329 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_MEGA \
20330 (UINT32_C(0x0) << 29)
20331 /* Value is in Kb or KB (base 10). */
20332 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_KILO \
20333 (UINT32_C(0x2) << 29)
20334 /* Value is in bits or bytes. */
20335 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_BASE \
20336 (UINT32_C(0x4) << 29)
20337 /* Value is in Gb or GB (base 10). */
20338 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_GIGA \
20339 (UINT32_C(0x6) << 29)
20340 /* Value is in 1/100th of a percentage of total bandwidth. */
20341 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 \
20342 (UINT32_C(0x1) << 29)
20344 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_INVALID \
20345 (UINT32_C(0x7) << 29)
20346 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_LAST \
20347 HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_INVALID
20348 /* Transmission Selection Algorithm (TSA) for CoS Queue. */
20349 uint8_t queue_id2_tsa_assign;
20350 /* Strict Priority */
20351 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_TSA_ASSIGN_SP \
20353 /* Enhanced Transmission Selection */
20354 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_TSA_ASSIGN_ETS \
20357 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_TSA_ASSIGN_RESERVED_FIRST \
20360 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_TSA_ASSIGN_RESERVED_LAST \
20363 * Priority level for strict priority. Valid only when the
20364 * tsa_assign is 0 - Strict Priority (SP)
20365 * 0..7 - Valid values.
20366 * 8..255 - Reserved.
20368 uint8_t queue_id2_pri_lvl;
20370 * Weight used to allocate remaining BW for this COS after
20371 * servicing guaranteed bandwidths for all COS.
20373 uint8_t queue_id2_bw_weight;
20374 /* ID of CoS Queue 3. */
20377 * Minimum BW allocated to CoS Queue.
20378 * The HWRM will translate this value into byte counter and
20379 * time interval used for this COS inside the device.
20381 uint32_t queue_id3_min_bw;
20382 /* The bandwidth value. */
20383 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MIN_BW_BW_VALUE_MASK \
20384 UINT32_C(0xfffffff)
20385 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MIN_BW_BW_VALUE_SFT \
20387 /* The granularity of the value (bits or bytes). */
20388 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MIN_BW_SCALE \
20389 UINT32_C(0x10000000)
20390 /* Value is in bits. */
20391 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MIN_BW_SCALE_BITS \
20392 (UINT32_C(0x0) << 28)
20393 /* Value is in bytes. */
20394 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MIN_BW_SCALE_BYTES \
20395 (UINT32_C(0x1) << 28)
20396 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MIN_BW_SCALE_LAST \
20397 HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MIN_BW_SCALE_BYTES
20398 /* bw_value_unit is 3 b */
20399 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_MASK \
20400 UINT32_C(0xe0000000)
20401 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_SFT \
20403 /* Value is in Mb or MB (base 10). */
20404 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_MEGA \
20405 (UINT32_C(0x0) << 29)
20406 /* Value is in Kb or KB (base 10). */
20407 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_KILO \
20408 (UINT32_C(0x2) << 29)
20409 /* Value is in bits or bytes. */
20410 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_BASE \
20411 (UINT32_C(0x4) << 29)
20412 /* Value is in Gb or GB (base 10). */
20413 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_GIGA \
20414 (UINT32_C(0x6) << 29)
20415 /* Value is in 1/100th of a percentage of total bandwidth. */
20416 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 \
20417 (UINT32_C(0x1) << 29)
20419 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_INVALID \
20420 (UINT32_C(0x7) << 29)
20421 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_LAST \
20422 HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_INVALID
20424 * Maximum BW allocated to CoS queue.
20425 * The HWRM will translate this value into byte counter and
20426 * time interval used for this COS inside the device.
20428 uint32_t queue_id3_max_bw;
20429 /* The bandwidth value. */
20430 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MAX_BW_BW_VALUE_MASK \
20431 UINT32_C(0xfffffff)
20432 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MAX_BW_BW_VALUE_SFT \
20434 /* The granularity of the value (bits or bytes). */
20435 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MAX_BW_SCALE \
20436 UINT32_C(0x10000000)
20437 /* Value is in bits. */
20438 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MAX_BW_SCALE_BITS \
20439 (UINT32_C(0x0) << 28)
20440 /* Value is in bytes. */
20441 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MAX_BW_SCALE_BYTES \
20442 (UINT32_C(0x1) << 28)
20443 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MAX_BW_SCALE_LAST \
20444 HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MAX_BW_SCALE_BYTES
20445 /* bw_value_unit is 3 b */
20446 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_MASK \
20447 UINT32_C(0xe0000000)
20448 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_SFT \
20450 /* Value is in Mb or MB (base 10). */
20451 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_MEGA \
20452 (UINT32_C(0x0) << 29)
20453 /* Value is in Kb or KB (base 10). */
20454 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_KILO \
20455 (UINT32_C(0x2) << 29)
20456 /* Value is in bits or bytes. */
20457 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_BASE \
20458 (UINT32_C(0x4) << 29)
20459 /* Value is in Gb or GB (base 10). */
20460 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_GIGA \
20461 (UINT32_C(0x6) << 29)
20462 /* Value is in 1/100th of a percentage of total bandwidth. */
20463 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 \
20464 (UINT32_C(0x1) << 29)
20466 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_INVALID \
20467 (UINT32_C(0x7) << 29)
20468 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_LAST \
20469 HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_INVALID
20470 /* Transmission Selection Algorithm (TSA) for CoS Queue. */
20471 uint8_t queue_id3_tsa_assign;
20472 /* Strict Priority */
20473 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_TSA_ASSIGN_SP \
20475 /* Enhanced Transmission Selection */
20476 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_TSA_ASSIGN_ETS \
20479 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_TSA_ASSIGN_RESERVED_FIRST \
20482 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_TSA_ASSIGN_RESERVED_LAST \
20485 * Priority level for strict priority. Valid only when the
20486 * tsa_assign is 0 - Strict Priority (SP)
20487 * 0..7 - Valid values.
20488 * 8..255 - Reserved.
20490 uint8_t queue_id3_pri_lvl;
20492 * Weight used to allocate remaining BW for this COS after
20493 * servicing guaranteed bandwidths for all COS.
20495 uint8_t queue_id3_bw_weight;
20496 /* ID of CoS Queue 4. */
20499 * Minimum BW allocated to CoS Queue.
20500 * The HWRM will translate this value into byte counter and
20501 * time interval used for this COS inside the device.
20503 uint32_t queue_id4_min_bw;
20504 /* The bandwidth value. */
20505 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MIN_BW_BW_VALUE_MASK \
20506 UINT32_C(0xfffffff)
20507 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MIN_BW_BW_VALUE_SFT \
20509 /* The granularity of the value (bits or bytes). */
20510 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MIN_BW_SCALE \
20511 UINT32_C(0x10000000)
20512 /* Value is in bits. */
20513 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MIN_BW_SCALE_BITS \
20514 (UINT32_C(0x0) << 28)
20515 /* Value is in bytes. */
20516 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MIN_BW_SCALE_BYTES \
20517 (UINT32_C(0x1) << 28)
20518 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MIN_BW_SCALE_LAST \
20519 HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MIN_BW_SCALE_BYTES
20520 /* bw_value_unit is 3 b */
20521 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_MASK \
20522 UINT32_C(0xe0000000)
20523 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_SFT \
20525 /* Value is in Mb or MB (base 10). */
20526 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_MEGA \
20527 (UINT32_C(0x0) << 29)
20528 /* Value is in Kb or KB (base 10). */
20529 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_KILO \
20530 (UINT32_C(0x2) << 29)
20531 /* Value is in bits or bytes. */
20532 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_BASE \
20533 (UINT32_C(0x4) << 29)
20534 /* Value is in Gb or GB (base 10). */
20535 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_GIGA \
20536 (UINT32_C(0x6) << 29)
20537 /* Value is in 1/100th of a percentage of total bandwidth. */
20538 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 \
20539 (UINT32_C(0x1) << 29)
20541 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_INVALID \
20542 (UINT32_C(0x7) << 29)
20543 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_LAST \
20544 HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_INVALID
20546 * Maximum BW allocated to CoS queue.
20547 * The HWRM will translate this value into byte counter and
20548 * time interval used for this COS inside the device.
20550 uint32_t queue_id4_max_bw;
20551 /* The bandwidth value. */
20552 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MAX_BW_BW_VALUE_MASK \
20553 UINT32_C(0xfffffff)
20554 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MAX_BW_BW_VALUE_SFT \
20556 /* The granularity of the value (bits or bytes). */
20557 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MAX_BW_SCALE \
20558 UINT32_C(0x10000000)
20559 /* Value is in bits. */
20560 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MAX_BW_SCALE_BITS \
20561 (UINT32_C(0x0) << 28)
20562 /* Value is in bytes. */
20563 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MAX_BW_SCALE_BYTES \
20564 (UINT32_C(0x1) << 28)
20565 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MAX_BW_SCALE_LAST \
20566 HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MAX_BW_SCALE_BYTES
20567 /* bw_value_unit is 3 b */
20568 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_MASK \
20569 UINT32_C(0xe0000000)
20570 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_SFT \
20572 /* Value is in Mb or MB (base 10). */
20573 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_MEGA \
20574 (UINT32_C(0x0) << 29)
20575 /* Value is in Kb or KB (base 10). */
20576 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_KILO \
20577 (UINT32_C(0x2) << 29)
20578 /* Value is in bits or bytes. */
20579 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_BASE \
20580 (UINT32_C(0x4) << 29)
20581 /* Value is in Gb or GB (base 10). */
20582 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_GIGA \
20583 (UINT32_C(0x6) << 29)
20584 /* Value is in 1/100th of a percentage of total bandwidth. */
20585 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 \
20586 (UINT32_C(0x1) << 29)
20588 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_INVALID \
20589 (UINT32_C(0x7) << 29)
20590 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_LAST \
20591 HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_INVALID
20592 /* Transmission Selection Algorithm (TSA) for CoS Queue. */
20593 uint8_t queue_id4_tsa_assign;
20594 /* Strict Priority */
20595 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_TSA_ASSIGN_SP \
20597 /* Enhanced Transmission Selection */
20598 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_TSA_ASSIGN_ETS \
20601 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_TSA_ASSIGN_RESERVED_FIRST \
20604 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_TSA_ASSIGN_RESERVED_LAST \
20607 * Priority level for strict priority. Valid only when the
20608 * tsa_assign is 0 - Strict Priority (SP)
20609 * 0..7 - Valid values.
20610 * 8..255 - Reserved.
20612 uint8_t queue_id4_pri_lvl;
20614 * Weight used to allocate remaining BW for this COS after
20615 * servicing guaranteed bandwidths for all COS.
20617 uint8_t queue_id4_bw_weight;
20618 /* ID of CoS Queue 5. */
20621 * Minimum BW allocated to CoS Queue.
20622 * The HWRM will translate this value into byte counter and
20623 * time interval used for this COS inside the device.
20625 uint32_t queue_id5_min_bw;
20626 /* The bandwidth value. */
20627 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MIN_BW_BW_VALUE_MASK \
20628 UINT32_C(0xfffffff)
20629 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MIN_BW_BW_VALUE_SFT \
20631 /* The granularity of the value (bits or bytes). */
20632 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MIN_BW_SCALE \
20633 UINT32_C(0x10000000)
20634 /* Value is in bits. */
20635 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MIN_BW_SCALE_BITS \
20636 (UINT32_C(0x0) << 28)
20637 /* Value is in bytes. */
20638 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MIN_BW_SCALE_BYTES \
20639 (UINT32_C(0x1) << 28)
20640 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MIN_BW_SCALE_LAST \
20641 HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MIN_BW_SCALE_BYTES
20642 /* bw_value_unit is 3 b */
20643 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_MASK \
20644 UINT32_C(0xe0000000)
20645 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_SFT \
20647 /* Value is in Mb or MB (base 10). */
20648 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_MEGA \
20649 (UINT32_C(0x0) << 29)
20650 /* Value is in Kb or KB (base 10). */
20651 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_KILO \
20652 (UINT32_C(0x2) << 29)
20653 /* Value is in bits or bytes. */
20654 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_BASE \
20655 (UINT32_C(0x4) << 29)
20656 /* Value is in Gb or GB (base 10). */
20657 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_GIGA \
20658 (UINT32_C(0x6) << 29)
20659 /* Value is in 1/100th of a percentage of total bandwidth. */
20660 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 \
20661 (UINT32_C(0x1) << 29)
20663 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_INVALID \
20664 (UINT32_C(0x7) << 29)
20665 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_LAST \
20666 HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_INVALID
20668 * Maximum BW allocated to CoS queue.
20669 * The HWRM will translate this value into byte counter and
20670 * time interval used for this COS inside the device.
20672 uint32_t queue_id5_max_bw;
20673 /* The bandwidth value. */
20674 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MAX_BW_BW_VALUE_MASK \
20675 UINT32_C(0xfffffff)
20676 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MAX_BW_BW_VALUE_SFT \
20678 /* The granularity of the value (bits or bytes). */
20679 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MAX_BW_SCALE \
20680 UINT32_C(0x10000000)
20681 /* Value is in bits. */
20682 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MAX_BW_SCALE_BITS \
20683 (UINT32_C(0x0) << 28)
20684 /* Value is in bytes. */
20685 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MAX_BW_SCALE_BYTES \
20686 (UINT32_C(0x1) << 28)
20687 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MAX_BW_SCALE_LAST \
20688 HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MAX_BW_SCALE_BYTES
20689 /* bw_value_unit is 3 b */
20690 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_MASK \
20691 UINT32_C(0xe0000000)
20692 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_SFT \
20694 /* Value is in Mb or MB (base 10). */
20695 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_MEGA \
20696 (UINT32_C(0x0) << 29)
20697 /* Value is in Kb or KB (base 10). */
20698 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_KILO \
20699 (UINT32_C(0x2) << 29)
20700 /* Value is in bits or bytes. */
20701 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_BASE \
20702 (UINT32_C(0x4) << 29)
20703 /* Value is in Gb or GB (base 10). */
20704 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_GIGA \
20705 (UINT32_C(0x6) << 29)
20706 /* Value is in 1/100th of a percentage of total bandwidth. */
20707 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 \
20708 (UINT32_C(0x1) << 29)
20710 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_INVALID \
20711 (UINT32_C(0x7) << 29)
20712 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_LAST \
20713 HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_INVALID
20714 /* Transmission Selection Algorithm (TSA) for CoS Queue. */
20715 uint8_t queue_id5_tsa_assign;
20716 /* Strict Priority */
20717 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_TSA_ASSIGN_SP \
20719 /* Enhanced Transmission Selection */
20720 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_TSA_ASSIGN_ETS \
20723 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_TSA_ASSIGN_RESERVED_FIRST \
20726 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_TSA_ASSIGN_RESERVED_LAST \
20729 * Priority level for strict priority. Valid only when the
20730 * tsa_assign is 0 - Strict Priority (SP)
20731 * 0..7 - Valid values.
20732 * 8..255 - Reserved.
20734 uint8_t queue_id5_pri_lvl;
20736 * Weight used to allocate remaining BW for this COS after
20737 * servicing guaranteed bandwidths for all COS.
20739 uint8_t queue_id5_bw_weight;
20740 /* ID of CoS Queue 6. */
20743 * Minimum BW allocated to CoS Queue.
20744 * The HWRM will translate this value into byte counter and
20745 * time interval used for this COS inside the device.
20747 uint32_t queue_id6_min_bw;
20748 /* The bandwidth value. */
20749 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MIN_BW_BW_VALUE_MASK \
20750 UINT32_C(0xfffffff)
20751 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MIN_BW_BW_VALUE_SFT \
20753 /* The granularity of the value (bits or bytes). */
20754 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MIN_BW_SCALE \
20755 UINT32_C(0x10000000)
20756 /* Value is in bits. */
20757 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MIN_BW_SCALE_BITS \
20758 (UINT32_C(0x0) << 28)
20759 /* Value is in bytes. */
20760 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MIN_BW_SCALE_BYTES \
20761 (UINT32_C(0x1) << 28)
20762 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MIN_BW_SCALE_LAST \
20763 HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MIN_BW_SCALE_BYTES
20764 /* bw_value_unit is 3 b */
20765 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_MASK \
20766 UINT32_C(0xe0000000)
20767 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_SFT \
20769 /* Value is in Mb or MB (base 10). */
20770 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_MEGA \
20771 (UINT32_C(0x0) << 29)
20772 /* Value is in Kb or KB (base 10). */
20773 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_KILO \
20774 (UINT32_C(0x2) << 29)
20775 /* Value is in bits or bytes. */
20776 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_BASE \
20777 (UINT32_C(0x4) << 29)
20778 /* Value is in Gb or GB (base 10). */
20779 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_GIGA \
20780 (UINT32_C(0x6) << 29)
20781 /* Value is in 1/100th of a percentage of total bandwidth. */
20782 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 \
20783 (UINT32_C(0x1) << 29)
20785 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_INVALID \
20786 (UINT32_C(0x7) << 29)
20787 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_LAST \
20788 HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_INVALID
20790 * Maximum BW allocated to CoS queue.
20791 * The HWRM will translate this value into byte counter and
20792 * time interval used for this COS inside the device.
20794 uint32_t queue_id6_max_bw;
20795 /* The bandwidth value. */
20796 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MAX_BW_BW_VALUE_MASK \
20797 UINT32_C(0xfffffff)
20798 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MAX_BW_BW_VALUE_SFT \
20800 /* The granularity of the value (bits or bytes). */
20801 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MAX_BW_SCALE \
20802 UINT32_C(0x10000000)
20803 /* Value is in bits. */
20804 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MAX_BW_SCALE_BITS \
20805 (UINT32_C(0x0) << 28)
20806 /* Value is in bytes. */
20807 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MAX_BW_SCALE_BYTES \
20808 (UINT32_C(0x1) << 28)
20809 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MAX_BW_SCALE_LAST \
20810 HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MAX_BW_SCALE_BYTES
20811 /* bw_value_unit is 3 b */
20812 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_MASK \
20813 UINT32_C(0xe0000000)
20814 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_SFT \
20816 /* Value is in Mb or MB (base 10). */
20817 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_MEGA \
20818 (UINT32_C(0x0) << 29)
20819 /* Value is in Kb or KB (base 10). */
20820 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_KILO \
20821 (UINT32_C(0x2) << 29)
20822 /* Value is in bits or bytes. */
20823 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_BASE \
20824 (UINT32_C(0x4) << 29)
20825 /* Value is in Gb or GB (base 10). */
20826 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_GIGA \
20827 (UINT32_C(0x6) << 29)
20828 /* Value is in 1/100th of a percentage of total bandwidth. */
20829 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 \
20830 (UINT32_C(0x1) << 29)
20832 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_INVALID \
20833 (UINT32_C(0x7) << 29)
20834 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_LAST \
20835 HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_INVALID
20836 /* Transmission Selection Algorithm (TSA) for CoS Queue. */
20837 uint8_t queue_id6_tsa_assign;
20838 /* Strict Priority */
20839 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_TSA_ASSIGN_SP \
20841 /* Enhanced Transmission Selection */
20842 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_TSA_ASSIGN_ETS \
20845 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_TSA_ASSIGN_RESERVED_FIRST \
20848 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_TSA_ASSIGN_RESERVED_LAST \
20851 * Priority level for strict priority. Valid only when the
20852 * tsa_assign is 0 - Strict Priority (SP)
20853 * 0..7 - Valid values.
20854 * 8..255 - Reserved.
20856 uint8_t queue_id6_pri_lvl;
20858 * Weight used to allocate remaining BW for this COS after
20859 * servicing guaranteed bandwidths for all COS.
20861 uint8_t queue_id6_bw_weight;
20862 /* ID of CoS Queue 7. */
20865 * Minimum BW allocated to CoS Queue.
20866 * The HWRM will translate this value into byte counter and
20867 * time interval used for this COS inside the device.
20869 uint32_t queue_id7_min_bw;
20870 /* The bandwidth value. */
20871 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MIN_BW_BW_VALUE_MASK \
20872 UINT32_C(0xfffffff)
20873 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MIN_BW_BW_VALUE_SFT \
20875 /* The granularity of the value (bits or bytes). */
20876 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MIN_BW_SCALE \
20877 UINT32_C(0x10000000)
20878 /* Value is in bits. */
20879 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MIN_BW_SCALE_BITS \
20880 (UINT32_C(0x0) << 28)
20881 /* Value is in bytes. */
20882 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MIN_BW_SCALE_BYTES \
20883 (UINT32_C(0x1) << 28)
20884 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MIN_BW_SCALE_LAST \
20885 HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MIN_BW_SCALE_BYTES
20886 /* bw_value_unit is 3 b */
20887 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_MASK \
20888 UINT32_C(0xe0000000)
20889 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_SFT \
20891 /* Value is in Mb or MB (base 10). */
20892 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_MEGA \
20893 (UINT32_C(0x0) << 29)
20894 /* Value is in Kb or KB (base 10). */
20895 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_KILO \
20896 (UINT32_C(0x2) << 29)
20897 /* Value is in bits or bytes. */
20898 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_BASE \
20899 (UINT32_C(0x4) << 29)
20900 /* Value is in Gb or GB (base 10). */
20901 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_GIGA \
20902 (UINT32_C(0x6) << 29)
20903 /* Value is in 1/100th of a percentage of total bandwidth. */
20904 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 \
20905 (UINT32_C(0x1) << 29)
20907 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_INVALID \
20908 (UINT32_C(0x7) << 29)
20909 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_LAST \
20910 HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_INVALID
20912 * Maximum BW allocated to CoS queue.
20913 * The HWRM will translate this value into byte counter and
20914 * time interval used for this COS inside the device.
20916 uint32_t queue_id7_max_bw;
20917 /* The bandwidth value. */
20918 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MAX_BW_BW_VALUE_MASK \
20919 UINT32_C(0xfffffff)
20920 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MAX_BW_BW_VALUE_SFT \
20922 /* The granularity of the value (bits or bytes). */
20923 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MAX_BW_SCALE \
20924 UINT32_C(0x10000000)
20925 /* Value is in bits. */
20926 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MAX_BW_SCALE_BITS \
20927 (UINT32_C(0x0) << 28)
20928 /* Value is in bytes. */
20929 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MAX_BW_SCALE_BYTES \
20930 (UINT32_C(0x1) << 28)
20931 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MAX_BW_SCALE_LAST \
20932 HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MAX_BW_SCALE_BYTES
20933 /* bw_value_unit is 3 b */
20934 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_MASK \
20935 UINT32_C(0xe0000000)
20936 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_SFT \
20938 /* Value is in Mb or MB (base 10). */
20939 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_MEGA \
20940 (UINT32_C(0x0) << 29)
20941 /* Value is in Kb or KB (base 10). */
20942 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_KILO \
20943 (UINT32_C(0x2) << 29)
20944 /* Value is in bits or bytes. */
20945 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_BASE \
20946 (UINT32_C(0x4) << 29)
20947 /* Value is in Gb or GB (base 10). */
20948 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_GIGA \
20949 (UINT32_C(0x6) << 29)
20950 /* Value is in 1/100th of a percentage of total bandwidth. */
20951 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 \
20952 (UINT32_C(0x1) << 29)
20954 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_INVALID \
20955 (UINT32_C(0x7) << 29)
20956 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_LAST \
20957 HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_INVALID
20958 /* Transmission Selection Algorithm (TSA) for CoS Queue. */
20959 uint8_t queue_id7_tsa_assign;
20960 /* Strict Priority */
20961 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_TSA_ASSIGN_SP \
20963 /* Enhanced Transmission Selection */
20964 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_TSA_ASSIGN_ETS \
20967 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_TSA_ASSIGN_RESERVED_FIRST \
20970 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_TSA_ASSIGN_RESERVED_LAST \
20973 * Priority level for strict priority. Valid only when the
20974 * tsa_assign is 0 - Strict Priority (SP)
20975 * 0..7 - Valid values.
20976 * 8..255 - Reserved.
20978 uint8_t queue_id7_pri_lvl;
20980 * Weight used to allocate remaining BW for this COS after
20981 * servicing guaranteed bandwidths for all COS.
20983 uint8_t queue_id7_bw_weight;
20984 uint8_t unused_1[5];
20985 } __attribute__((packed));
20987 /* hwrm_queue_cos2bw_cfg_output (size:128b/16B) */
20988 struct hwrm_queue_cos2bw_cfg_output {
20989 /* The specific error status for the command. */
20990 uint16_t error_code;
20991 /* The HWRM command request type. */
20993 /* The sequence ID from the original command. */
20995 /* The length of the response data in number of bytes. */
20997 uint8_t unused_0[7];
20999 * This field is used in Output records to indicate that the output
21000 * is completely written to RAM. This field should be read as '1'
21001 * to indicate that the output has been completely written.
21002 * When writing a command completion or response to an internal processor,
21003 * the order of writes has to be such that this field is written last.
21006 } __attribute__((packed));
21008 /*******************
21009 * hwrm_vnic_alloc *
21010 *******************/
21013 /* hwrm_vnic_alloc_input (size:192b/24B) */
21014 struct hwrm_vnic_alloc_input {
21015 /* The HWRM command request type. */
21018 * The completion ring to send the completion event on. This should
21019 * be the NQ ID returned from the `nq_alloc` HWRM command.
21021 uint16_t cmpl_ring;
21023 * The sequence ID is used by the driver for tracking multiple
21024 * commands. This ID is treated as opaque data by the firmware and
21025 * the value is returned in the `hwrm_resp_hdr` upon completion.
21029 * The target ID of the command:
21030 * * 0x0-0xFFF8 - The function ID
21031 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
21032 * * 0xFFFD - Reserved for user-space HWRM interface
21035 uint16_t target_id;
21037 * A physical address pointer pointing to a host buffer that the
21038 * command's response data will be written. This can be either a host
21039 * physical address (HPA) or a guest physical address (GPA) and must
21040 * point to a physically contiguous block of memory.
21042 uint64_t resp_addr;
21045 * When this bit is '1', this VNIC is requested to
21046 * be the default VNIC for this function.
21048 #define HWRM_VNIC_ALLOC_INPUT_FLAGS_DEFAULT UINT32_C(0x1)
21049 uint8_t unused_0[4];
21050 } __attribute__((packed));
21052 /* hwrm_vnic_alloc_output (size:128b/16B) */
21053 struct hwrm_vnic_alloc_output {
21054 /* The specific error status for the command. */
21055 uint16_t error_code;
21056 /* The HWRM command request type. */
21058 /* The sequence ID from the original command. */
21060 /* The length of the response data in number of bytes. */
21062 /* Logical vnic ID */
21064 uint8_t unused_0[3];
21066 * This field is used in Output records to indicate that the output
21067 * is completely written to RAM. This field should be read as '1'
21068 * to indicate that the output has been completely written.
21069 * When writing a command completion or response to an internal processor,
21070 * the order of writes has to be such that this field is written last.
21073 } __attribute__((packed));
21075 /******************
21077 ******************/
21080 /* hwrm_vnic_free_input (size:192b/24B) */
21081 struct hwrm_vnic_free_input {
21082 /* The HWRM command request type. */
21085 * The completion ring to send the completion event on. This should
21086 * be the NQ ID returned from the `nq_alloc` HWRM command.
21088 uint16_t cmpl_ring;
21090 * The sequence ID is used by the driver for tracking multiple
21091 * commands. This ID is treated as opaque data by the firmware and
21092 * the value is returned in the `hwrm_resp_hdr` upon completion.
21096 * The target ID of the command:
21097 * * 0x0-0xFFF8 - The function ID
21098 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
21099 * * 0xFFFD - Reserved for user-space HWRM interface
21102 uint16_t target_id;
21104 * A physical address pointer pointing to a host buffer that the
21105 * command's response data will be written. This can be either a host
21106 * physical address (HPA) or a guest physical address (GPA) and must
21107 * point to a physically contiguous block of memory.
21109 uint64_t resp_addr;
21110 /* Logical vnic ID */
21112 uint8_t unused_0[4];
21113 } __attribute__((packed));
21115 /* hwrm_vnic_free_output (size:128b/16B) */
21116 struct hwrm_vnic_free_output {
21117 /* The specific error status for the command. */
21118 uint16_t error_code;
21119 /* The HWRM command request type. */
21121 /* The sequence ID from the original command. */
21123 /* The length of the response data in number of bytes. */
21125 uint8_t unused_0[7];
21127 * This field is used in Output records to indicate that the output
21128 * is completely written to RAM. This field should be read as '1'
21129 * to indicate that the output has been completely written.
21130 * When writing a command completion or response to an internal processor,
21131 * the order of writes has to be such that this field is written last.
21134 } __attribute__((packed));
21141 /* hwrm_vnic_cfg_input (size:320b/40B) */
21142 struct hwrm_vnic_cfg_input {
21143 /* The HWRM command request type. */
21146 * The completion ring to send the completion event on. This should
21147 * be the NQ ID returned from the `nq_alloc` HWRM command.
21149 uint16_t cmpl_ring;
21151 * The sequence ID is used by the driver for tracking multiple
21152 * commands. This ID is treated as opaque data by the firmware and
21153 * the value is returned in the `hwrm_resp_hdr` upon completion.
21157 * The target ID of the command:
21158 * * 0x0-0xFFF8 - The function ID
21159 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
21160 * * 0xFFFD - Reserved for user-space HWRM interface
21163 uint16_t target_id;
21165 * A physical address pointer pointing to a host buffer that the
21166 * command's response data will be written. This can be either a host
21167 * physical address (HPA) or a guest physical address (GPA) and must
21168 * point to a physically contiguous block of memory.
21170 uint64_t resp_addr;
21173 * When this bit is '1', the VNIC is requested to
21174 * be the default VNIC for the function.
21176 #define HWRM_VNIC_CFG_INPUT_FLAGS_DEFAULT \
21179 * When this bit is '1', the VNIC is being configured to
21180 * strip VLAN in the RX path.
21181 * If set to '0', then VLAN stripping is disabled on
21184 #define HWRM_VNIC_CFG_INPUT_FLAGS_VLAN_STRIP_MODE \
21187 * When this bit is '1', the VNIC is being configured to
21188 * buffer receive packets in the hardware until the host
21189 * posts new receive buffers.
21190 * If set to '0', then bd_stall is being configured to be
21191 * disabled on this VNIC.
21193 #define HWRM_VNIC_CFG_INPUT_FLAGS_BD_STALL_MODE \
21196 * When this bit is '1', the VNIC is being configured to
21197 * receive both RoCE and non-RoCE traffic.
21198 * If set to '0', then this VNIC is not configured to be
21199 * operating in dual VNIC mode.
21201 #define HWRM_VNIC_CFG_INPUT_FLAGS_ROCE_DUAL_VNIC_MODE \
21204 * When this flag is set to '1', the VNIC is requested to
21205 * be configured to receive only RoCE traffic.
21206 * If this flag is set to '0', then this flag shall be
21207 * ignored by the HWRM.
21208 * If roce_dual_vnic_mode flag is set to '1'
21209 * or roce_mirroring_capable_vnic_mode flag to 1,
21210 * then the HWRM client shall not set this flag to '1'.
21212 #define HWRM_VNIC_CFG_INPUT_FLAGS_ROCE_ONLY_VNIC_MODE \
21215 * When a VNIC uses one destination ring group for certain
21216 * application (e.g. Receive Flow Steering) where
21217 * exact match is used to direct packets to a VNIC with one
21218 * destination ring group only, there is no need to configure
21219 * RSS indirection table for that VNIC as only one destination
21220 * ring group is used.
21222 * This flag is used to enable a mode where
21223 * RSS is enabled in the VNIC using a RSS context
21224 * for computing RSS hash but the RSS indirection table is
21225 * not configured using hwrm_vnic_rss_cfg.
21227 * If this mode is enabled, then the driver should not program
21228 * RSS indirection table for the RSS context that is used for
21229 * computing RSS hash only.
21231 #define HWRM_VNIC_CFG_INPUT_FLAGS_RSS_DFLT_CR_MODE \
21234 * When this bit is '1', the VNIC is being configured to
21235 * receive both RoCE and non-RoCE traffic, but forward only the
21236 * RoCE traffic further. Also, RoCE traffic can be mirrored to
21239 #define HWRM_VNIC_CFG_INPUT_FLAGS_ROCE_MIRRORING_CAPABLE_VNIC_MODE \
21243 * This bit must be '1' for the dflt_ring_grp field to be
21246 #define HWRM_VNIC_CFG_INPUT_ENABLES_DFLT_RING_GRP \
21249 * This bit must be '1' for the rss_rule field to be
21252 #define HWRM_VNIC_CFG_INPUT_ENABLES_RSS_RULE \
21255 * This bit must be '1' for the cos_rule field to be
21258 #define HWRM_VNIC_CFG_INPUT_ENABLES_COS_RULE \
21261 * This bit must be '1' for the lb_rule field to be
21264 #define HWRM_VNIC_CFG_INPUT_ENABLES_LB_RULE \
21267 * This bit must be '1' for the mru field to be
21270 #define HWRM_VNIC_CFG_INPUT_ENABLES_MRU \
21273 * This bit must be '1' for the default_rx_ring_id field to be
21276 #define HWRM_VNIC_CFG_INPUT_ENABLES_DEFAULT_RX_RING_ID \
21279 * This bit must be '1' for the default_cmpl_ring_id field to be
21282 #define HWRM_VNIC_CFG_INPUT_ENABLES_DEFAULT_CMPL_RING_ID \
21284 /* Logical vnic ID */
21287 * Default Completion ring for the VNIC. This ring will
21288 * be chosen if packet does not match any RSS rules and if
21289 * there is no COS rule.
21291 uint16_t dflt_ring_grp;
21293 * RSS ID for RSS rule/table structure. 0xFF... (All Fs) if
21294 * there is no RSS rule.
21298 * RSS ID for COS rule/table structure. 0xFF... (All Fs) if
21299 * there is no COS rule.
21303 * RSS ID for load balancing rule/table structure.
21304 * 0xFF... (All Fs) if there is no LB rule.
21308 * The maximum receive unit of the vnic.
21309 * Each vnic is associated with a function.
21310 * The vnic mru value overwrites the mru setting of the
21311 * associated function.
21312 * The HWRM shall make sure that vnic mru does not exceed
21313 * the mru of the port the function is associated with.
21317 * Default Rx ring for the VNIC. This ring will
21318 * be chosen if packet does not match any RSS rules.
21319 * The aggregation ring associated with the Rx ring is
21320 * implied based on the Rx ring specified when the
21321 * aggregation ring was allocated.
21323 uint16_t default_rx_ring_id;
21325 * Default completion ring for the VNIC. This ring will
21326 * be chosen if packet does not match any RSS rules.
21328 uint16_t default_cmpl_ring_id;
21329 } __attribute__((packed));
21331 /* hwrm_vnic_cfg_output (size:128b/16B) */
21332 struct hwrm_vnic_cfg_output {
21333 /* The specific error status for the command. */
21334 uint16_t error_code;
21335 /* The HWRM command request type. */
21337 /* The sequence ID from the original command. */
21339 /* The length of the response data in number of bytes. */
21341 uint8_t unused_0[7];
21343 * This field is used in Output records to indicate that the output
21344 * is completely written to RAM. This field should be read as '1'
21345 * to indicate that the output has been completely written.
21346 * When writing a command completion or response to an internal processor,
21347 * the order of writes has to be such that this field is written last.
21350 } __attribute__((packed));
21352 /******************
21354 ******************/
21357 /* hwrm_vnic_qcfg_input (size:256b/32B) */
21358 struct hwrm_vnic_qcfg_input {
21359 /* The HWRM command request type. */
21362 * The completion ring to send the completion event on. This should
21363 * be the NQ ID returned from the `nq_alloc` HWRM command.
21365 uint16_t cmpl_ring;
21367 * The sequence ID is used by the driver for tracking multiple
21368 * commands. This ID is treated as opaque data by the firmware and
21369 * the value is returned in the `hwrm_resp_hdr` upon completion.
21373 * The target ID of the command:
21374 * * 0x0-0xFFF8 - The function ID
21375 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
21376 * * 0xFFFD - Reserved for user-space HWRM interface
21379 uint16_t target_id;
21381 * A physical address pointer pointing to a host buffer that the
21382 * command's response data will be written. This can be either a host
21383 * physical address (HPA) or a guest physical address (GPA) and must
21384 * point to a physically contiguous block of memory.
21386 uint64_t resp_addr;
21389 * This bit must be '1' for the vf_id_valid field to be
21392 #define HWRM_VNIC_QCFG_INPUT_ENABLES_VF_ID_VALID UINT32_C(0x1)
21393 /* Logical vnic ID */
21395 /* ID of Virtual Function whose VNIC resource is being queried. */
21397 uint8_t unused_0[6];
21398 } __attribute__((packed));
21400 /* hwrm_vnic_qcfg_output (size:256b/32B) */
21401 struct hwrm_vnic_qcfg_output {
21402 /* The specific error status for the command. */
21403 uint16_t error_code;
21404 /* The HWRM command request type. */
21406 /* The sequence ID from the original command. */
21408 /* The length of the response data in number of bytes. */
21410 /* Default Completion ring for the VNIC. */
21411 uint16_t dflt_ring_grp;
21413 * RSS ID for RSS rule/table structure. 0xFF... (All Fs) if
21414 * there is no RSS rule.
21418 * RSS ID for COS rule/table structure. 0xFF... (All Fs) if
21419 * there is no COS rule.
21423 * RSS ID for load balancing rule/table structure.
21424 * 0xFF... (All Fs) if there is no LB rule.
21427 /* The maximum receive unit of the vnic. */
21429 uint8_t unused_0[2];
21432 * When this bit is '1', the VNIC is the default VNIC for
21435 #define HWRM_VNIC_QCFG_OUTPUT_FLAGS_DEFAULT \
21438 * When this bit is '1', the VNIC is configured to
21439 * strip VLAN in the RX path.
21440 * If set to '0', then VLAN stripping is disabled on
21443 #define HWRM_VNIC_QCFG_OUTPUT_FLAGS_VLAN_STRIP_MODE \
21446 * When this bit is '1', the VNIC is configured to
21447 * buffer receive packets in the hardware until the host
21448 * posts new receive buffers.
21449 * If set to '0', then bd_stall is disabled on
21452 #define HWRM_VNIC_QCFG_OUTPUT_FLAGS_BD_STALL_MODE \
21455 * When this bit is '1', the VNIC is configured to
21456 * receive both RoCE and non-RoCE traffic.
21457 * If set to '0', then this VNIC is not configured to
21458 * operate in dual VNIC mode.
21460 #define HWRM_VNIC_QCFG_OUTPUT_FLAGS_ROCE_DUAL_VNIC_MODE \
21463 * When this flag is set to '1', the VNIC is configured to
21464 * receive only RoCE traffic.
21465 * When this flag is set to '0', the VNIC is not configured
21466 * to receive only RoCE traffic.
21467 * If roce_dual_vnic_mode flag and this flag both are set
21468 * to '1', then it is an invalid configuration of the
21469 * VNIC. The HWRM should not allow that type of
21470 * mis-configuration by HWRM clients.
21472 #define HWRM_VNIC_QCFG_OUTPUT_FLAGS_ROCE_ONLY_VNIC_MODE \
21475 * When a VNIC uses one destination ring group for certain
21476 * application (e.g. Receive Flow Steering) where
21477 * exact match is used to direct packets to a VNIC with one
21478 * destination ring group only, there is no need to configure
21479 * RSS indirection table for that VNIC as only one destination
21480 * ring group is used.
21482 * When this bit is set to '1', then the VNIC is enabled in a
21483 * mode where RSS is enabled in the VNIC using a RSS context
21484 * for computing RSS hash but the RSS indirection table is
21487 #define HWRM_VNIC_QCFG_OUTPUT_FLAGS_RSS_DFLT_CR_MODE \
21490 * When this bit is '1', the VNIC is configured to
21491 * receive both RoCE and non-RoCE traffic, but forward only
21492 * RoCE traffic further. Also RoCE traffic can be mirrored to
21495 #define HWRM_VNIC_QCFG_OUTPUT_FLAGS_ROCE_MIRRORING_CAPABLE_VNIC_MODE \
21497 uint8_t unused_1[7];
21499 * This field is used in Output records to indicate that the output
21500 * is completely written to RAM. This field should be read as '1'
21501 * to indicate that the output has been completely written.
21502 * When writing a command completion or response to an internal processor,
21503 * the order of writes has to be such that this field is written last.
21506 } __attribute__((packed));
21508 /*******************
21509 * hwrm_vnic_qcaps *
21510 *******************/
21513 /* hwrm_vnic_qcaps_input (size:192b/24B) */
21514 struct hwrm_vnic_qcaps_input {
21515 /* The HWRM command request type. */
21518 * The completion ring to send the completion event on. This should
21519 * be the NQ ID returned from the `nq_alloc` HWRM command.
21521 uint16_t cmpl_ring;
21523 * The sequence ID is used by the driver for tracking multiple
21524 * commands. This ID is treated as opaque data by the firmware and
21525 * the value is returned in the `hwrm_resp_hdr` upon completion.
21529 * The target ID of the command:
21530 * * 0x0-0xFFF8 - The function ID
21531 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
21532 * * 0xFFFD - Reserved for user-space HWRM interface
21535 uint16_t target_id;
21537 * A physical address pointer pointing to a host buffer that the
21538 * command's response data will be written. This can be either a host
21539 * physical address (HPA) or a guest physical address (GPA) and must
21540 * point to a physically contiguous block of memory.
21542 uint64_t resp_addr;
21544 uint8_t unused_0[4];
21545 } __attribute__((packed));
21547 /* hwrm_vnic_qcaps_output (size:192b/24B) */
21548 struct hwrm_vnic_qcaps_output {
21549 /* The specific error status for the command. */
21550 uint16_t error_code;
21551 /* The HWRM command request type. */
21553 /* The sequence ID from the original command. */
21555 /* The length of the response data in number of bytes. */
21557 /* The maximum receive unit that is settable on a vnic. */
21559 uint8_t unused_0[2];
21562 #define HWRM_VNIC_QCAPS_OUTPUT_FLAGS_UNUSED \
21565 * When this bit is '1', the capability of stripping VLAN in
21566 * the RX path is supported on VNIC(s).
21567 * If set to '0', then VLAN stripping capability is
21568 * not supported on VNIC(s).
21570 #define HWRM_VNIC_QCAPS_OUTPUT_FLAGS_VLAN_STRIP_CAP \
21573 * When this bit is '1', the capability to buffer receive
21574 * packets in the hardware until the host posts new receive buffers
21575 * is supported on VNIC(s).
21576 * If set to '0', then bd_stall capability is not supported
21579 #define HWRM_VNIC_QCAPS_OUTPUT_FLAGS_BD_STALL_CAP \
21582 * When this bit is '1', the capability to
21583 * receive both RoCE and non-RoCE traffic on VNIC(s) is
21585 * If set to '0', then the capability to receive
21586 * both RoCE and non-RoCE traffic on VNIC(s) is
21589 #define HWRM_VNIC_QCAPS_OUTPUT_FLAGS_ROCE_DUAL_VNIC_CAP \
21592 * When this bit is set to '1', the capability to configure
21593 * a VNIC to receive only RoCE traffic is supported.
21594 * When this flag is set to '0', the VNIC capability to
21595 * configure to receive only RoCE traffic is not supported.
21597 #define HWRM_VNIC_QCAPS_OUTPUT_FLAGS_ROCE_ONLY_VNIC_CAP \
21600 * When this bit is set to '1', then the capability to enable
21601 * a VNIC in a mode where RSS context without configuring
21602 * RSS indirection table is supported (for RSS hash computation).
21603 * When this bit is set to '0', then a VNIC can not be configured
21604 * with a mode to enable RSS context without configuring RSS
21605 * indirection table.
21607 #define HWRM_VNIC_QCAPS_OUTPUT_FLAGS_RSS_DFLT_CR_CAP \
21610 * When this bit is '1', the capability to
21611 * mirror the the RoCE traffic is supported.
21612 * If set to '0', then the capability to mirror the
21613 * RoCE traffic is not supported.
21615 #define HWRM_VNIC_QCAPS_OUTPUT_FLAGS_ROCE_MIRRORING_CAPABLE_VNIC_CAP \
21618 * When this bit is '1', the outermost RSS hashing capability
21619 * is supported. If set to '0', then the outermost RSS hashing
21620 * capability is not supported.
21622 #define HWRM_VNIC_QCAPS_OUTPUT_FLAGS_OUTERMOST_RSS_CAP \
21625 * This field advertises the maximum concurrent TPA aggregations
21626 * supported by the VNIC on new devices that support TPA v2.
21627 * '0' means that TPA v2 is not supported.
21629 uint16_t max_aggs_supported;
21630 uint8_t unused_1[5];
21632 * This field is used in Output records to indicate that the output
21633 * is completely written to RAM. This field should be read as '1'
21634 * to indicate that the output has been completely written.
21635 * When writing a command completion or response to an internal processor,
21636 * the order of writes has to be such that this field is written last.
21639 } __attribute__((packed));
21641 /*********************
21642 * hwrm_vnic_tpa_cfg *
21643 *********************/
21646 /* hwrm_vnic_tpa_cfg_input (size:320b/40B) */
21647 struct hwrm_vnic_tpa_cfg_input {
21648 /* The HWRM command request type. */
21651 * The completion ring to send the completion event on. This should
21652 * be the NQ ID returned from the `nq_alloc` HWRM command.
21654 uint16_t cmpl_ring;
21656 * The sequence ID is used by the driver for tracking multiple
21657 * commands. This ID is treated as opaque data by the firmware and
21658 * the value is returned in the `hwrm_resp_hdr` upon completion.
21662 * The target ID of the command:
21663 * * 0x0-0xFFF8 - The function ID
21664 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
21665 * * 0xFFFD - Reserved for user-space HWRM interface
21668 uint16_t target_id;
21670 * A physical address pointer pointing to a host buffer that the
21671 * command's response data will be written. This can be either a host
21672 * physical address (HPA) or a guest physical address (GPA) and must
21673 * point to a physically contiguous block of memory.
21675 uint64_t resp_addr;
21678 * When this bit is '1', the VNIC shall be configured to
21679 * perform transparent packet aggregation (TPA) of
21680 * non-tunneled TCP packets.
21682 #define HWRM_VNIC_TPA_CFG_INPUT_FLAGS_TPA \
21685 * When this bit is '1', the VNIC shall be configured to
21686 * perform transparent packet aggregation (TPA) of
21687 * tunneled TCP packets.
21689 #define HWRM_VNIC_TPA_CFG_INPUT_FLAGS_ENCAP_TPA \
21692 * When this bit is '1', the VNIC shall be configured to
21693 * perform transparent packet aggregation (TPA) according
21694 * to Windows Receive Segment Coalescing (RSC) rules.
21696 #define HWRM_VNIC_TPA_CFG_INPUT_FLAGS_RSC_WND_UPDATE \
21699 * When this bit is '1', the VNIC shall be configured to
21700 * perform transparent packet aggregation (TPA) according
21701 * to Linux Generic Receive Offload (GRO) rules.
21703 #define HWRM_VNIC_TPA_CFG_INPUT_FLAGS_GRO \
21706 * When this bit is '1', the VNIC shall be configured to
21707 * perform transparent packet aggregation (TPA) for TCP
21708 * packets with IP ECN set to non-zero.
21710 #define HWRM_VNIC_TPA_CFG_INPUT_FLAGS_AGG_WITH_ECN \
21713 * When this bit is '1', the VNIC shall be configured to
21714 * perform transparent packet aggregation (TPA) for
21715 * GRE tunneled TCP packets only if all packets have the
21716 * same GRE sequence.
21718 #define HWRM_VNIC_TPA_CFG_INPUT_FLAGS_AGG_WITH_SAME_GRE_SEQ \
21721 * When this bit is '1' and the GRO mode is enabled,
21722 * the VNIC shall be configured to
21723 * perform transparent packet aggregation (TPA) for
21724 * TCP/IPv4 packets with consecutively increasing IPIDs.
21725 * In other words, the last packet that is being
21726 * aggregated to an already existing aggregation context
21727 * shall have IPID 1 more than the IPID of the last packet
21728 * that was aggregated in that aggregation context.
21730 #define HWRM_VNIC_TPA_CFG_INPUT_FLAGS_GRO_IPID_CHECK \
21733 * When this bit is '1' and the GRO mode is enabled,
21734 * the VNIC shall be configured to
21735 * perform transparent packet aggregation (TPA) for
21736 * TCP packets with the same TTL (IPv4) or Hop limit (IPv6)
21739 #define HWRM_VNIC_TPA_CFG_INPUT_FLAGS_GRO_TTL_CHECK \
21742 * When this bit is '1' and the GRO mode is enabled,
21743 * the VNIC shall DMA payload data using GRO rules.
21744 * When this bit is '0', the VNIC shall DMA payload data
21745 * using the more efficient LRO rules of filling all
21746 * aggregation buffers.
21748 #define HWRM_VNIC_TPA_CFG_INPUT_FLAGS_AGG_PACK_AS_GRO \
21752 * This bit must be '1' for the max_agg_segs field to be
21755 #define HWRM_VNIC_TPA_CFG_INPUT_ENABLES_MAX_AGG_SEGS UINT32_C(0x1)
21757 * This bit must be '1' for the max_aggs field to be
21760 #define HWRM_VNIC_TPA_CFG_INPUT_ENABLES_MAX_AGGS UINT32_C(0x2)
21762 * This bit must be '1' for the max_agg_timer field to be
21765 #define HWRM_VNIC_TPA_CFG_INPUT_ENABLES_MAX_AGG_TIMER UINT32_C(0x4)
21766 /* deprecated bit. Do not use!!! */
21767 #define HWRM_VNIC_TPA_CFG_INPUT_ENABLES_MIN_AGG_LEN UINT32_C(0x8)
21768 /* Logical vnic ID */
21771 * This is the maximum number of TCP segments that can
21772 * be aggregated (unit is Log2). Max value is 31. On new
21773 * devices supporting TPA v2, the unit is multiples of 4 and
21774 * valid values are > 0 and <= 63.
21776 uint16_t max_agg_segs;
21778 #define HWRM_VNIC_TPA_CFG_INPUT_MAX_AGG_SEGS_1 UINT32_C(0x0)
21780 #define HWRM_VNIC_TPA_CFG_INPUT_MAX_AGG_SEGS_2 UINT32_C(0x1)
21782 #define HWRM_VNIC_TPA_CFG_INPUT_MAX_AGG_SEGS_4 UINT32_C(0x2)
21784 #define HWRM_VNIC_TPA_CFG_INPUT_MAX_AGG_SEGS_8 UINT32_C(0x3)
21785 /* Any segment size larger than this is not valid */
21786 #define HWRM_VNIC_TPA_CFG_INPUT_MAX_AGG_SEGS_MAX UINT32_C(0x1f)
21787 #define HWRM_VNIC_TPA_CFG_INPUT_MAX_AGG_SEGS_LAST \
21788 HWRM_VNIC_TPA_CFG_INPUT_MAX_AGG_SEGS_MAX
21790 * This is the maximum number of aggregations this VNIC is
21791 * allowed (unit is Log2). Max value is 7. On new devices
21792 * supporting TPA v2, this is in unit of 1 and must be > 0
21793 * and <= max_aggs_supported in the hwrm_vnic_qcaps response
21794 * to enable TPA v2.
21797 /* 1 aggregation */
21798 #define HWRM_VNIC_TPA_CFG_INPUT_MAX_AGGS_1 UINT32_C(0x0)
21799 /* 2 aggregations */
21800 #define HWRM_VNIC_TPA_CFG_INPUT_MAX_AGGS_2 UINT32_C(0x1)
21801 /* 4 aggregations */
21802 #define HWRM_VNIC_TPA_CFG_INPUT_MAX_AGGS_4 UINT32_C(0x2)
21803 /* 8 aggregations */
21804 #define HWRM_VNIC_TPA_CFG_INPUT_MAX_AGGS_8 UINT32_C(0x3)
21805 /* 16 aggregations */
21806 #define HWRM_VNIC_TPA_CFG_INPUT_MAX_AGGS_16 UINT32_C(0x4)
21807 /* Any aggregation size larger than this is not valid */
21808 #define HWRM_VNIC_TPA_CFG_INPUT_MAX_AGGS_MAX UINT32_C(0x7)
21809 #define HWRM_VNIC_TPA_CFG_INPUT_MAX_AGGS_LAST \
21810 HWRM_VNIC_TPA_CFG_INPUT_MAX_AGGS_MAX
21811 uint8_t unused_0[2];
21813 * This is the maximum amount of time allowed for
21814 * an aggregation context to complete after it was initiated.
21816 uint32_t max_agg_timer;
21818 * This is the minimum amount of payload length required to
21819 * start an aggregation context. This field is deprecated and
21820 * should be set to 0. The minimum length is set by firmware
21821 * and can be queried using hwrm_vnic_tpa_qcfg.
21823 uint32_t min_agg_len;
21824 } __attribute__((packed));
21826 /* hwrm_vnic_tpa_cfg_output (size:128b/16B) */
21827 struct hwrm_vnic_tpa_cfg_output {
21828 /* The specific error status for the command. */
21829 uint16_t error_code;
21830 /* The HWRM command request type. */
21832 /* The sequence ID from the original command. */
21834 /* The length of the response data in number of bytes. */
21836 uint8_t unused_0[7];
21838 * This field is used in Output records to indicate that the output
21839 * is completely written to RAM. This field should be read as '1'
21840 * to indicate that the output has been completely written.
21841 * When writing a command completion or response to an internal processor,
21842 * the order of writes has to be such that this field is written last.
21845 } __attribute__((packed));
21847 /*********************
21848 * hwrm_vnic_rss_cfg *
21849 *********************/
21852 /* hwrm_vnic_rss_cfg_input (size:384b/48B) */
21853 struct hwrm_vnic_rss_cfg_input {
21854 /* The HWRM command request type. */
21857 * The completion ring to send the completion event on. This should
21858 * be the NQ ID returned from the `nq_alloc` HWRM command.
21860 uint16_t cmpl_ring;
21862 * The sequence ID is used by the driver for tracking multiple
21863 * commands. This ID is treated as opaque data by the firmware and
21864 * the value is returned in the `hwrm_resp_hdr` upon completion.
21868 * The target ID of the command:
21869 * * 0x0-0xFFF8 - The function ID
21870 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
21871 * * 0xFFFD - Reserved for user-space HWRM interface
21874 uint16_t target_id;
21876 * A physical address pointer pointing to a host buffer that the
21877 * command's response data will be written. This can be either a host
21878 * physical address (HPA) or a guest physical address (GPA) and must
21879 * point to a physically contiguous block of memory.
21881 uint64_t resp_addr;
21882 uint32_t hash_type;
21884 * When this bit is '1', the RSS hash shall be computed
21885 * over source and destination IPv4 addresses of IPv4
21888 #define HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV4 UINT32_C(0x1)
21890 * When this bit is '1', the RSS hash shall be computed
21891 * over source/destination IPv4 addresses and
21892 * source/destination ports of TCP/IPv4 packets.
21894 #define HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV4 UINT32_C(0x2)
21896 * When this bit is '1', the RSS hash shall be computed
21897 * over source/destination IPv4 addresses and
21898 * source/destination ports of UDP/IPv4 packets.
21900 #define HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV4 UINT32_C(0x4)
21902 * When this bit is '1', the RSS hash shall be computed
21903 * over source and destination IPv4 addresses of IPv6
21906 #define HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV6 UINT32_C(0x8)
21908 * When this bit is '1', the RSS hash shall be computed
21909 * over source/destination IPv6 addresses and
21910 * source/destination ports of TCP/IPv6 packets.
21912 #define HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV6 UINT32_C(0x10)
21914 * When this bit is '1', the RSS hash shall be computed
21915 * over source/destination IPv6 addresses and
21916 * source/destination ports of UDP/IPv6 packets.
21918 #define HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV6 UINT32_C(0x20)
21919 /* VNIC ID of VNIC associated with RSS table being configured. */
21922 * Specifies which VNIC ring table pair to configure.
21923 * Valid values range from 0 to 7.
21925 uint8_t ring_table_pair_index;
21926 /* Flags to specify different RSS hash modes. */
21927 uint8_t hash_mode_flags;
21929 * When this bit is '1', it indicates using current RSS
21930 * hash mode setting configured in the device.
21932 #define HWRM_VNIC_RSS_CFG_INPUT_HASH_MODE_FLAGS_DEFAULT \
21935 * When this bit is '1', it indicates requesting support of
21936 * RSS hashing over innermost 4 tuples {l3.src, l3.dest,
21937 * l4.src, l4.dest} for tunnel packets. For none-tunnel
21938 * packets, the RSS hash is computed over the normal
21939 * src/dest l3 and src/dest l4 headers.
21941 #define HWRM_VNIC_RSS_CFG_INPUT_HASH_MODE_FLAGS_INNERMOST_4 \
21944 * When this bit is '1', it indicates requesting support of
21945 * RSS hashing over innermost 2 tuples {l3.src, l3.dest} for
21946 * tunnel packets. For none-tunnel packets, the RSS hash is
21947 * computed over the normal src/dest l3 headers.
21949 #define HWRM_VNIC_RSS_CFG_INPUT_HASH_MODE_FLAGS_INNERMOST_2 \
21952 * When this bit is '1', it indicates requesting support of
21953 * RSS hashing over outermost 4 tuples {t_l3.src, t_l3.dest,
21954 * t_l4.src, t_l4.dest} for tunnel packets. For none-tunnel
21955 * packets, the RSS hash is computed over the normal
21956 * src/dest l3 and src/dest l4 headers.
21958 #define HWRM_VNIC_RSS_CFG_INPUT_HASH_MODE_FLAGS_OUTERMOST_4 \
21961 * When this bit is '1', it indicates requesting support of
21962 * RSS hashing over outermost 2 tuples {t_l3.src, t_l3.dest} for
21963 * tunnel packets. For none-tunnel packets, the RSS hash is
21964 * computed over the normal src/dest l3 headers.
21966 #define HWRM_VNIC_RSS_CFG_INPUT_HASH_MODE_FLAGS_OUTERMOST_2 \
21968 /* This is the address for rss ring group table */
21969 uint64_t ring_grp_tbl_addr;
21970 /* This is the address for rss hash key table */
21971 uint64_t hash_key_tbl_addr;
21972 /* Index to the rss indirection table. */
21973 uint16_t rss_ctx_idx;
21974 uint8_t unused_1[6];
21975 } __attribute__((packed));
21977 /* hwrm_vnic_rss_cfg_output (size:128b/16B) */
21978 struct hwrm_vnic_rss_cfg_output {
21979 /* The specific error status for the command. */
21980 uint16_t error_code;
21981 /* The HWRM command request type. */
21983 /* The sequence ID from the original command. */
21985 /* The length of the response data in number of bytes. */
21987 uint8_t unused_0[7];
21989 * This field is used in Output records to indicate that the output
21990 * is completely written to RAM. This field should be read as '1'
21991 * to indicate that the output has been completely written.
21992 * When writing a command completion or response to an internal processor,
21993 * the order of writes has to be such that this field is written last.
21996 } __attribute__((packed));
21998 /**********************
21999 * hwrm_vnic_rss_qcfg *
22000 **********************/
22003 /* hwrm_vnic_rss_qcfg_input (size:192b/24B) */
22004 struct hwrm_vnic_rss_qcfg_input {
22005 /* The HWRM command request type. */
22008 * The completion ring to send the completion event on. This should
22009 * be the NQ ID returned from the `nq_alloc` HWRM command.
22011 uint16_t cmpl_ring;
22013 * The sequence ID is used by the driver for tracking multiple
22014 * commands. This ID is treated as opaque data by the firmware and
22015 * the value is returned in the `hwrm_resp_hdr` upon completion.
22019 * The target ID of the command:
22020 * * 0x0-0xFFF8 - The function ID
22021 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
22022 * * 0xFFFD - Reserved for user-space HWRM interface
22025 uint16_t target_id;
22027 * A physical address pointer pointing to a host buffer that the
22028 * command's response data will be written. This can be either a host
22029 * physical address (HPA) or a guest physical address (GPA) and must
22030 * point to a physically contiguous block of memory.
22032 uint64_t resp_addr;
22033 /* Index to the rss indirection table. */
22034 uint16_t rss_ctx_idx;
22035 uint8_t unused_0[6];
22036 } __attribute__((packed));
22038 /* hwrm_vnic_rss_qcfg_output (size:512b/64B) */
22039 struct hwrm_vnic_rss_qcfg_output {
22040 /* The specific error status for the command. */
22041 uint16_t error_code;
22042 /* The HWRM command request type. */
22044 /* The sequence ID from the original command. */
22046 /* The length of the response data in number of bytes. */
22048 uint32_t hash_type;
22050 * When this bit is '1', the RSS hash shall be computed
22051 * over source and destination IPv4 addresses of IPv4
22054 #define HWRM_VNIC_RSS_QCFG_OUTPUT_HASH_TYPE_IPV4 UINT32_C(0x1)
22056 * When this bit is '1', the RSS hash shall be computed
22057 * over source/destination IPv4 addresses and
22058 * source/destination ports of TCP/IPv4 packets.
22060 #define HWRM_VNIC_RSS_QCFG_OUTPUT_HASH_TYPE_TCP_IPV4 UINT32_C(0x2)
22062 * When this bit is '1', the RSS hash shall be computed
22063 * over source/destination IPv4 addresses and
22064 * source/destination ports of UDP/IPv4 packets.
22066 #define HWRM_VNIC_RSS_QCFG_OUTPUT_HASH_TYPE_UDP_IPV4 UINT32_C(0x4)
22068 * When this bit is '1', the RSS hash shall be computed
22069 * over source and destination IPv4 addresses of IPv6
22072 #define HWRM_VNIC_RSS_QCFG_OUTPUT_HASH_TYPE_IPV6 UINT32_C(0x8)
22074 * When this bit is '1', the RSS hash shall be computed
22075 * over source/destination IPv6 addresses and
22076 * source/destination ports of TCP/IPv6 packets.
22078 #define HWRM_VNIC_RSS_QCFG_OUTPUT_HASH_TYPE_TCP_IPV6 UINT32_C(0x10)
22080 * When this bit is '1', the RSS hash shall be computed
22081 * over source/destination IPv6 addresses and
22082 * source/destination ports of UDP/IPv6 packets.
22084 #define HWRM_VNIC_RSS_QCFG_OUTPUT_HASH_TYPE_UDP_IPV6 UINT32_C(0x20)
22085 uint8_t unused_0[4];
22086 /* This is the value of rss hash key */
22087 uint32_t hash_key[10];
22088 /* Flags to specify different RSS hash modes. */
22089 uint8_t hash_mode_flags;
22091 * When this bit is '1', it indicates using current RSS
22092 * hash mode setting configured in the device.
22094 #define HWRM_VNIC_RSS_QCFG_OUTPUT_HASH_MODE_FLAGS_DEFAULT \
22097 * When this bit is '1', it indicates requesting support of
22098 * RSS hashing over innermost 4 tuples {l3.src, l3.dest,
22099 * l4.src, l4.dest} for tunnel packets. For none-tunnel
22100 * packets, the RSS hash is computed over the normal
22101 * src/dest l3 and src/dest l4 headers.
22103 #define HWRM_VNIC_RSS_QCFG_OUTPUT_HASH_MODE_FLAGS_INNERMOST_4 \
22106 * When this bit is '1', it indicates requesting support of
22107 * RSS hashing over innermost 2 tuples {l3.src, l3.dest} for
22108 * tunnel packets. For none-tunnel packets, the RSS hash is
22109 * computed over the normal src/dest l3 headers.
22111 #define HWRM_VNIC_RSS_QCFG_OUTPUT_HASH_MODE_FLAGS_INNERMOST_2 \
22114 * When this bit is '1', it indicates requesting support of
22115 * RSS hashing over outermost 4 tuples {t_l3.src, t_l3.dest,
22116 * t_l4.src, t_l4.dest} for tunnel packets. For none-tunnel
22117 * packets, the RSS hash is computed over the normal
22118 * src/dest l3 and src/dest l4 headers.
22120 #define HWRM_VNIC_RSS_QCFG_OUTPUT_HASH_MODE_FLAGS_OUTERMOST_4 \
22123 * When this bit is '1', it indicates requesting support of
22124 * RSS hashing over outermost 2 tuples {t_l3.src, t_l3.dest} for
22125 * tunnel packets. For none-tunnel packets, the RSS hash is
22126 * computed over the normal src/dest l3 headers.
22128 #define HWRM_VNIC_RSS_QCFG_OUTPUT_HASH_MODE_FLAGS_OUTERMOST_2 \
22130 uint8_t unused_1[6];
22132 * This field is used in Output records to indicate that the output
22133 * is completely written to RAM. This field should be read as '1'
22134 * to indicate that the output has been completely written.
22135 * When writing a command completion or response to an internal processor,
22136 * the order of writes has to be such that this field is written last.
22139 } __attribute__((packed));
22141 /**************************
22142 * hwrm_vnic_plcmodes_cfg *
22143 **************************/
22146 /* hwrm_vnic_plcmodes_cfg_input (size:320b/40B) */
22147 struct hwrm_vnic_plcmodes_cfg_input {
22148 /* The HWRM command request type. */
22151 * The completion ring to send the completion event on. This should
22152 * be the NQ ID returned from the `nq_alloc` HWRM command.
22154 uint16_t cmpl_ring;
22156 * The sequence ID is used by the driver for tracking multiple
22157 * commands. This ID is treated as opaque data by the firmware and
22158 * the value is returned in the `hwrm_resp_hdr` upon completion.
22162 * The target ID of the command:
22163 * * 0x0-0xFFF8 - The function ID
22164 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
22165 * * 0xFFFD - Reserved for user-space HWRM interface
22168 uint16_t target_id;
22170 * A physical address pointer pointing to a host buffer that the
22171 * command's response data will be written. This can be either a host
22172 * physical address (HPA) or a guest physical address (GPA) and must
22173 * point to a physically contiguous block of memory.
22175 uint64_t resp_addr;
22178 * When this bit is '1', the VNIC shall be configured to
22179 * use regular placement algorithm.
22180 * By default, the regular placement algorithm shall be
22181 * enabled on the VNIC.
22183 #define HWRM_VNIC_PLCMODES_CFG_INPUT_FLAGS_REGULAR_PLACEMENT \
22186 * When this bit is '1', the VNIC shall be configured
22187 * use the jumbo placement algorithm.
22189 #define HWRM_VNIC_PLCMODES_CFG_INPUT_FLAGS_JUMBO_PLACEMENT \
22192 * When this bit is '1', the VNIC shall be configured
22193 * to enable Header-Data split for IPv4 packets according
22194 * to the following rules:
22195 * # If the packet is identified as TCP/IPv4, then the
22196 * packet is split at the beginning of the TCP payload.
22197 * # If the packet is identified as UDP/IPv4, then the
22198 * packet is split at the beginning of UDP payload.
22199 * # If the packet is identified as non-TCP and non-UDP
22200 * IPv4 packet, then the packet is split at the beginning
22201 * of the upper layer protocol header carried in the IPv4
22204 #define HWRM_VNIC_PLCMODES_CFG_INPUT_FLAGS_HDS_IPV4 \
22207 * When this bit is '1', the VNIC shall be configured
22208 * to enable Header-Data split for IPv6 packets according
22209 * to the following rules:
22210 * # If the packet is identified as TCP/IPv6, then the
22211 * packet is split at the beginning of the TCP payload.
22212 * # If the packet is identified as UDP/IPv6, then the
22213 * packet is split at the beginning of UDP payload.
22214 * # If the packet is identified as non-TCP and non-UDP
22215 * IPv6 packet, then the packet is split at the beginning
22216 * of the upper layer protocol header carried in the IPv6
22219 #define HWRM_VNIC_PLCMODES_CFG_INPUT_FLAGS_HDS_IPV6 \
22222 * When this bit is '1', the VNIC shall be configured
22223 * to enable Header-Data split for FCoE packets at the
22224 * beginning of FC payload.
22226 #define HWRM_VNIC_PLCMODES_CFG_INPUT_FLAGS_HDS_FCOE \
22229 * When this bit is '1', the VNIC shall be configured
22230 * to enable Header-Data split for RoCE packets at the
22231 * beginning of RoCE payload (after BTH/GRH headers).
22233 #define HWRM_VNIC_PLCMODES_CFG_INPUT_FLAGS_HDS_ROCE \
22237 * This bit must be '1' for the jumbo_thresh_valid field to be
22240 #define HWRM_VNIC_PLCMODES_CFG_INPUT_ENABLES_JUMBO_THRESH_VALID \
22243 * This bit must be '1' for the hds_offset_valid field to be
22246 #define HWRM_VNIC_PLCMODES_CFG_INPUT_ENABLES_HDS_OFFSET_VALID \
22249 * This bit must be '1' for the hds_threshold_valid field to be
22252 #define HWRM_VNIC_PLCMODES_CFG_INPUT_ENABLES_HDS_THRESHOLD_VALID \
22254 /* Logical vnic ID */
22257 * When jumbo placement algorithm is enabled, this value
22258 * is used to determine the threshold for jumbo placement.
22259 * Packets with length larger than this value will be
22260 * placed according to the jumbo placement algorithm.
22262 uint16_t jumbo_thresh;
22264 * This value is used to determine the offset into
22265 * packet buffer where the split data (payload) will be
22266 * placed according to one of of HDS placement algorithm.
22268 * The lengths of packet buffers provided for split data
22269 * shall be larger than this value.
22271 uint16_t hds_offset;
22273 * When one of the HDS placement algorithm is enabled, this
22274 * value is used to determine the threshold for HDS
22276 * Packets with length larger than this value will be
22277 * placed according to the HDS placement algorithm.
22278 * This value shall be in multiple of 4 bytes.
22280 uint16_t hds_threshold;
22281 uint8_t unused_0[6];
22282 } __attribute__((packed));
22284 /* hwrm_vnic_plcmodes_cfg_output (size:128b/16B) */
22285 struct hwrm_vnic_plcmodes_cfg_output {
22286 /* The specific error status for the command. */
22287 uint16_t error_code;
22288 /* The HWRM command request type. */
22290 /* The sequence ID from the original command. */
22292 /* The length of the response data in number of bytes. */
22294 uint8_t unused_0[7];
22296 * This field is used in Output records to indicate that the output
22297 * is completely written to RAM. This field should be read as '1'
22298 * to indicate that the output has been completely written.
22299 * When writing a command completion or response to an internal processor,
22300 * the order of writes has to be such that this field is written last.
22303 } __attribute__((packed));
22305 /***************************
22306 * hwrm_vnic_plcmodes_qcfg *
22307 ***************************/
22310 /* hwrm_vnic_plcmodes_qcfg_input (size:192b/24B) */
22311 struct hwrm_vnic_plcmodes_qcfg_input {
22312 /* The HWRM command request type. */
22315 * The completion ring to send the completion event on. This should
22316 * be the NQ ID returned from the `nq_alloc` HWRM command.
22318 uint16_t cmpl_ring;
22320 * The sequence ID is used by the driver for tracking multiple
22321 * commands. This ID is treated as opaque data by the firmware and
22322 * the value is returned in the `hwrm_resp_hdr` upon completion.
22326 * The target ID of the command:
22327 * * 0x0-0xFFF8 - The function ID
22328 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
22329 * * 0xFFFD - Reserved for user-space HWRM interface
22332 uint16_t target_id;
22334 * A physical address pointer pointing to a host buffer that the
22335 * command's response data will be written. This can be either a host
22336 * physical address (HPA) or a guest physical address (GPA) and must
22337 * point to a physically contiguous block of memory.
22339 uint64_t resp_addr;
22340 /* Logical vnic ID */
22342 uint8_t unused_0[4];
22343 } __attribute__((packed));
22345 /* hwrm_vnic_plcmodes_qcfg_output (size:192b/24B) */
22346 struct hwrm_vnic_plcmodes_qcfg_output {
22347 /* The specific error status for the command. */
22348 uint16_t error_code;
22349 /* The HWRM command request type. */
22351 /* The sequence ID from the original command. */
22353 /* The length of the response data in number of bytes. */
22357 * When this bit is '1', the VNIC is configured to
22358 * use regular placement algorithm.
22360 #define HWRM_VNIC_PLCMODES_QCFG_OUTPUT_FLAGS_REGULAR_PLACEMENT \
22363 * When this bit is '1', the VNIC is configured to
22364 * use the jumbo placement algorithm.
22366 #define HWRM_VNIC_PLCMODES_QCFG_OUTPUT_FLAGS_JUMBO_PLACEMENT \
22369 * When this bit is '1', the VNIC is configured
22370 * to enable Header-Data split for IPv4 packets.
22372 #define HWRM_VNIC_PLCMODES_QCFG_OUTPUT_FLAGS_HDS_IPV4 \
22375 * When this bit is '1', the VNIC is configured
22376 * to enable Header-Data split for IPv6 packets.
22378 #define HWRM_VNIC_PLCMODES_QCFG_OUTPUT_FLAGS_HDS_IPV6 \
22381 * When this bit is '1', the VNIC is configured
22382 * to enable Header-Data split for FCoE packets.
22384 #define HWRM_VNIC_PLCMODES_QCFG_OUTPUT_FLAGS_HDS_FCOE \
22387 * When this bit is '1', the VNIC is configured
22388 * to enable Header-Data split for RoCE packets.
22390 #define HWRM_VNIC_PLCMODES_QCFG_OUTPUT_FLAGS_HDS_ROCE \
22393 * When this bit is '1', the VNIC is configured
22394 * to be the default VNIC of the requesting function.
22396 #define HWRM_VNIC_PLCMODES_QCFG_OUTPUT_FLAGS_DFLT_VNIC \
22399 * When jumbo placement algorithm is enabled, this value
22400 * is used to determine the threshold for jumbo placement.
22401 * Packets with length larger than this value will be
22402 * placed according to the jumbo placement algorithm.
22404 uint16_t jumbo_thresh;
22406 * This value is used to determine the offset into
22407 * packet buffer where the split data (payload) will be
22408 * placed according to one of of HDS placement algorithm.
22410 * The lengths of packet buffers provided for split data
22411 * shall be larger than this value.
22413 uint16_t hds_offset;
22415 * When one of the HDS placement algorithm is enabled, this
22416 * value is used to determine the threshold for HDS
22418 * Packets with length larger than this value will be
22419 * placed according to the HDS placement algorithm.
22420 * This value shall be in multiple of 4 bytes.
22422 uint16_t hds_threshold;
22423 uint8_t unused_0[5];
22425 * This field is used in Output records to indicate that the output
22426 * is completely written to RAM. This field should be read as '1'
22427 * to indicate that the output has been completely written.
22428 * When writing a command completion or response to an internal processor,
22429 * the order of writes has to be such that this field is written last.
22432 } __attribute__((packed));
22434 /**********************************
22435 * hwrm_vnic_rss_cos_lb_ctx_alloc *
22436 **********************************/
22439 /* hwrm_vnic_rss_cos_lb_ctx_alloc_input (size:128b/16B) */
22440 struct hwrm_vnic_rss_cos_lb_ctx_alloc_input {
22441 /* The HWRM command request type. */
22444 * The completion ring to send the completion event on. This should
22445 * be the NQ ID returned from the `nq_alloc` HWRM command.
22447 uint16_t cmpl_ring;
22449 * The sequence ID is used by the driver for tracking multiple
22450 * commands. This ID is treated as opaque data by the firmware and
22451 * the value is returned in the `hwrm_resp_hdr` upon completion.
22455 * The target ID of the command:
22456 * * 0x0-0xFFF8 - The function ID
22457 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
22458 * * 0xFFFD - Reserved for user-space HWRM interface
22461 uint16_t target_id;
22463 * A physical address pointer pointing to a host buffer that the
22464 * command's response data will be written. This can be either a host
22465 * physical address (HPA) or a guest physical address (GPA) and must
22466 * point to a physically contiguous block of memory.
22468 uint64_t resp_addr;
22469 } __attribute__((packed));
22471 /* hwrm_vnic_rss_cos_lb_ctx_alloc_output (size:128b/16B) */
22472 struct hwrm_vnic_rss_cos_lb_ctx_alloc_output {
22473 /* The specific error status for the command. */
22474 uint16_t error_code;
22475 /* The HWRM command request type. */
22477 /* The sequence ID from the original command. */
22479 /* The length of the response data in number of bytes. */
22481 /* rss_cos_lb_ctx_id is 16 b */
22482 uint16_t rss_cos_lb_ctx_id;
22483 uint8_t unused_0[5];
22485 * This field is used in Output records to indicate that the output
22486 * is completely written to RAM. This field should be read as '1'
22487 * to indicate that the output has been completely written.
22488 * When writing a command completion or response to an internal processor,
22489 * the order of writes has to be such that this field is written last.
22492 } __attribute__((packed));
22494 /*********************************
22495 * hwrm_vnic_rss_cos_lb_ctx_free *
22496 *********************************/
22499 /* hwrm_vnic_rss_cos_lb_ctx_free_input (size:192b/24B) */
22500 struct hwrm_vnic_rss_cos_lb_ctx_free_input {
22501 /* The HWRM command request type. */
22504 * The completion ring to send the completion event on. This should
22505 * be the NQ ID returned from the `nq_alloc` HWRM command.
22507 uint16_t cmpl_ring;
22509 * The sequence ID is used by the driver for tracking multiple
22510 * commands. This ID is treated as opaque data by the firmware and
22511 * the value is returned in the `hwrm_resp_hdr` upon completion.
22515 * The target ID of the command:
22516 * * 0x0-0xFFF8 - The function ID
22517 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
22518 * * 0xFFFD - Reserved for user-space HWRM interface
22521 uint16_t target_id;
22523 * A physical address pointer pointing to a host buffer that the
22524 * command's response data will be written. This can be either a host
22525 * physical address (HPA) or a guest physical address (GPA) and must
22526 * point to a physically contiguous block of memory.
22528 uint64_t resp_addr;
22529 /* rss_cos_lb_ctx_id is 16 b */
22530 uint16_t rss_cos_lb_ctx_id;
22531 uint8_t unused_0[6];
22532 } __attribute__((packed));
22534 /* hwrm_vnic_rss_cos_lb_ctx_free_output (size:128b/16B) */
22535 struct hwrm_vnic_rss_cos_lb_ctx_free_output {
22536 /* The specific error status for the command. */
22537 uint16_t error_code;
22538 /* The HWRM command request type. */
22540 /* The sequence ID from the original command. */
22542 /* The length of the response data in number of bytes. */
22544 uint8_t unused_0[7];
22546 * This field is used in Output records to indicate that the output
22547 * is completely written to RAM. This field should be read as '1'
22548 * to indicate that the output has been completely written.
22549 * When writing a command completion or response to an internal processor,
22550 * the order of writes has to be such that this field is written last.
22553 } __attribute__((packed));
22555 /*******************
22556 * hwrm_ring_alloc *
22557 *******************/
22560 /* hwrm_ring_alloc_input (size:704b/88B) */
22561 struct hwrm_ring_alloc_input {
22562 /* The HWRM command request type. */
22565 * The completion ring to send the completion event on. This should
22566 * be the NQ ID returned from the `nq_alloc` HWRM command.
22568 uint16_t cmpl_ring;
22570 * The sequence ID is used by the driver for tracking multiple
22571 * commands. This ID is treated as opaque data by the firmware and
22572 * the value is returned in the `hwrm_resp_hdr` upon completion.
22576 * The target ID of the command:
22577 * * 0x0-0xFFF8 - The function ID
22578 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
22579 * * 0xFFFD - Reserved for user-space HWRM interface
22582 uint16_t target_id;
22584 * A physical address pointer pointing to a host buffer that the
22585 * command's response data will be written. This can be either a host
22586 * physical address (HPA) or a guest physical address (GPA) and must
22587 * point to a physically contiguous block of memory.
22589 uint64_t resp_addr;
22592 * This bit must be '1' for the ring_arb_cfg field to be
22595 #define HWRM_RING_ALLOC_INPUT_ENABLES_RING_ARB_CFG \
22598 * This bit must be '1' for the stat_ctx_id_valid field to be
22601 #define HWRM_RING_ALLOC_INPUT_ENABLES_STAT_CTX_ID_VALID \
22604 * This bit must be '1' for the max_bw_valid field to be
22607 #define HWRM_RING_ALLOC_INPUT_ENABLES_MAX_BW_VALID \
22610 * This bit must be '1' for the rx_ring_id field to be
22613 #define HWRM_RING_ALLOC_INPUT_ENABLES_RX_RING_ID_VALID \
22616 * This bit must be '1' for the nq_ring_id field to be
22619 #define HWRM_RING_ALLOC_INPUT_ENABLES_NQ_RING_ID_VALID \
22622 * This bit must be '1' for the rx_buf_size field to be
22625 #define HWRM_RING_ALLOC_INPUT_ENABLES_RX_BUF_SIZE_VALID \
22629 /* L2 Completion Ring (CR) */
22630 #define HWRM_RING_ALLOC_INPUT_RING_TYPE_L2_CMPL UINT32_C(0x0)
22632 #define HWRM_RING_ALLOC_INPUT_RING_TYPE_TX UINT32_C(0x1)
22634 #define HWRM_RING_ALLOC_INPUT_RING_TYPE_RX UINT32_C(0x2)
22635 /* RoCE Notification Completion Ring (ROCE_CR) */
22636 #define HWRM_RING_ALLOC_INPUT_RING_TYPE_ROCE_CMPL UINT32_C(0x3)
22637 /* RX Aggregation Ring */
22638 #define HWRM_RING_ALLOC_INPUT_RING_TYPE_RX_AGG UINT32_C(0x4)
22639 /* Notification Queue */
22640 #define HWRM_RING_ALLOC_INPUT_RING_TYPE_NQ UINT32_C(0x5)
22641 #define HWRM_RING_ALLOC_INPUT_RING_TYPE_LAST \
22642 HWRM_RING_ALLOC_INPUT_RING_TYPE_NQ
22644 /* Ring allocation flags. */
22647 * For Rx rings, the incoming packet data can be placed at either
22648 * a 0B or 2B offset from the start of the Rx packet buffer. When
22649 * '1', the received packet will be padded with 2B of zeros at the
22650 * front of the packet. Note that this flag is only used for
22651 * Rx rings and is ignored for all other rings included Rx
22652 * Aggregation rings.
22654 #define HWRM_RING_ALLOC_INPUT_FLAGS_RX_SOP_PAD UINT32_C(0x1)
22656 * This value is a pointer to the page table for the
22659 uint64_t page_tbl_addr;
22660 /* First Byte Offset of the first entry in the first page. */
22663 * Actual page size in 2^page_size. The supported range is increments
22664 * in powers of 2 from 16 bytes to 1GB.
22666 * Page size is 16 B.
22668 * Page size is 4 KB.
22670 * Page size is 8 KB.
22672 * Page size is 64 KB.
22674 * Page size is 2 MB.
22676 * Page size is 4 MB.
22678 * Page size is 1 GB.
22682 * This value indicates the depth of page table.
22683 * For this version of the specification, value other than 0 or
22684 * 1 shall be considered as an invalid value.
22685 * When the page_tbl_depth = 0, then it is treated as a
22686 * special case with the following.
22687 * 1. FBO and page size fields are not valid.
22688 * 2. page_tbl_addr is the physical address of the first
22689 * element of the ring.
22691 uint8_t page_tbl_depth;
22692 uint8_t unused_1[2];
22694 * Number of 16B units in the ring. Minimum size for
22695 * a ring is 16 16B entries.
22699 * Logical ring number for the ring to be allocated.
22700 * This value determines the position in the doorbell
22701 * area where the update to the ring will be made.
22703 * For completion rings, this value is also the MSI-X
22704 * vector number for the function the completion ring is
22707 uint16_t logical_id;
22709 * This field is used only when ring_type is a TX ring.
22710 * This value indicates what completion ring the TX ring
22711 * is associated with.
22713 uint16_t cmpl_ring_id;
22715 * This field is used only when ring_type is a TX ring.
22716 * This value indicates what CoS queue the TX ring
22717 * is associated with.
22721 * When allocating a Rx ring or Rx aggregation ring, this field
22722 * specifies the size of the buffer descriptors posted to the ring.
22724 uint16_t rx_buf_size;
22726 * When allocating an Rx aggregation ring, this field
22727 * specifies the associated Rx ring ID.
22729 uint16_t rx_ring_id;
22731 * When allocating a completion ring, this field
22732 * specifies the associated NQ ring ID.
22734 uint16_t nq_ring_id;
22736 * This field is used only when ring_type is a TX ring.
22737 * This field is used to configure arbitration related
22738 * parameters for a TX ring.
22740 uint16_t ring_arb_cfg;
22741 /* Arbitration policy used for the ring. */
22742 #define HWRM_RING_ALLOC_INPUT_RING_ARB_CFG_ARB_POLICY_MASK \
22744 #define HWRM_RING_ALLOC_INPUT_RING_ARB_CFG_ARB_POLICY_SFT 0
22746 * Use strict priority for the TX ring.
22747 * Priority value is specified in arb_policy_param
22749 #define HWRM_RING_ALLOC_INPUT_RING_ARB_CFG_ARB_POLICY_SP \
22752 * Use weighted fair queue arbitration for the TX ring.
22753 * Weight is specified in arb_policy_param
22755 #define HWRM_RING_ALLOC_INPUT_RING_ARB_CFG_ARB_POLICY_WFQ \
22757 #define HWRM_RING_ALLOC_INPUT_RING_ARB_CFG_ARB_POLICY_LAST \
22758 HWRM_RING_ALLOC_INPUT_RING_ARB_CFG_ARB_POLICY_WFQ
22759 /* Reserved field. */
22760 #define HWRM_RING_ALLOC_INPUT_RING_ARB_CFG_RSVD_MASK \
22762 #define HWRM_RING_ALLOC_INPUT_RING_ARB_CFG_RSVD_SFT 4
22764 * Arbitration policy specific parameter.
22765 * # For strict priority arbitration policy, this field
22766 * represents a priority value. If set to 0, then the priority
22767 * is not specified and the HWRM is allowed to select
22768 * any priority for this TX ring.
22769 * # For weighted fair queue arbitration policy, this field
22770 * represents a weight value. If set to 0, then the weight
22771 * is not specified and the HWRM is allowed to select
22772 * any weight for this TX ring.
22774 #define HWRM_RING_ALLOC_INPUT_RING_ARB_CFG_ARB_POLICY_PARAM_MASK \
22776 #define HWRM_RING_ALLOC_INPUT_RING_ARB_CFG_ARB_POLICY_PARAM_SFT 8
22779 * This field is reserved for the future use.
22780 * It shall be set to 0.
22782 uint32_t reserved3;
22784 * This field is used only when ring_type is a TX ring.
22785 * This input indicates what statistics context this ring
22786 * should be associated with.
22788 uint32_t stat_ctx_id;
22790 * This field is reserved for the future use.
22791 * It shall be set to 0.
22793 uint32_t reserved4;
22795 * This field is used only when ring_type is a TX ring
22796 * to specify maximum BW allocated to the TX ring.
22797 * The HWRM will translate this value into byte counter and
22798 * time interval used for this ring inside the device.
22801 /* The bandwidth value. */
22802 #define HWRM_RING_ALLOC_INPUT_MAX_BW_BW_VALUE_MASK \
22803 UINT32_C(0xfffffff)
22804 #define HWRM_RING_ALLOC_INPUT_MAX_BW_BW_VALUE_SFT 0
22805 /* The granularity of the value (bits or bytes). */
22806 #define HWRM_RING_ALLOC_INPUT_MAX_BW_SCALE \
22807 UINT32_C(0x10000000)
22808 /* Value is in bits. */
22809 #define HWRM_RING_ALLOC_INPUT_MAX_BW_SCALE_BITS \
22810 (UINT32_C(0x0) << 28)
22811 /* Value is in bytes. */
22812 #define HWRM_RING_ALLOC_INPUT_MAX_BW_SCALE_BYTES \
22813 (UINT32_C(0x1) << 28)
22814 #define HWRM_RING_ALLOC_INPUT_MAX_BW_SCALE_LAST \
22815 HWRM_RING_ALLOC_INPUT_MAX_BW_SCALE_BYTES
22816 /* bw_value_unit is 3 b */
22817 #define HWRM_RING_ALLOC_INPUT_MAX_BW_BW_VALUE_UNIT_MASK \
22818 UINT32_C(0xe0000000)
22819 #define HWRM_RING_ALLOC_INPUT_MAX_BW_BW_VALUE_UNIT_SFT 29
22820 /* Value is in Mb or MB (base 10). */
22821 #define HWRM_RING_ALLOC_INPUT_MAX_BW_BW_VALUE_UNIT_MEGA \
22822 (UINT32_C(0x0) << 29)
22823 /* Value is in Kb or KB (base 10). */
22824 #define HWRM_RING_ALLOC_INPUT_MAX_BW_BW_VALUE_UNIT_KILO \
22825 (UINT32_C(0x2) << 29)
22826 /* Value is in bits or bytes. */
22827 #define HWRM_RING_ALLOC_INPUT_MAX_BW_BW_VALUE_UNIT_BASE \
22828 (UINT32_C(0x4) << 29)
22829 /* Value is in Gb or GB (base 10). */
22830 #define HWRM_RING_ALLOC_INPUT_MAX_BW_BW_VALUE_UNIT_GIGA \
22831 (UINT32_C(0x6) << 29)
22832 /* Value is in 1/100th of a percentage of total bandwidth. */
22833 #define HWRM_RING_ALLOC_INPUT_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 \
22834 (UINT32_C(0x1) << 29)
22836 #define HWRM_RING_ALLOC_INPUT_MAX_BW_BW_VALUE_UNIT_INVALID \
22837 (UINT32_C(0x7) << 29)
22838 #define HWRM_RING_ALLOC_INPUT_MAX_BW_BW_VALUE_UNIT_LAST \
22839 HWRM_RING_ALLOC_INPUT_MAX_BW_BW_VALUE_UNIT_INVALID
22841 * This field is used only when ring_type is a Completion ring.
22842 * This value indicates what interrupt mode should be used
22843 * on this completion ring.
22844 * Note: In the legacy interrupt mode, no more than 16
22845 * completion rings are allowed.
22849 #define HWRM_RING_ALLOC_INPUT_INT_MODE_LEGACY UINT32_C(0x0)
22851 #define HWRM_RING_ALLOC_INPUT_INT_MODE_RSVD UINT32_C(0x1)
22853 #define HWRM_RING_ALLOC_INPUT_INT_MODE_MSIX UINT32_C(0x2)
22854 /* No Interrupt - Polled mode */
22855 #define HWRM_RING_ALLOC_INPUT_INT_MODE_POLL UINT32_C(0x3)
22856 #define HWRM_RING_ALLOC_INPUT_INT_MODE_LAST \
22857 HWRM_RING_ALLOC_INPUT_INT_MODE_POLL
22858 uint8_t unused_4[3];
22860 * The cq_handle is specified when allocating a completion ring. For
22861 * devices that support NQs, this cq_handle will be included in the
22862 * NQE to specify which CQ should be read to retrieve the completion
22865 uint64_t cq_handle;
22866 } __attribute__((packed));
22868 /* hwrm_ring_alloc_output (size:128b/16B) */
22869 struct hwrm_ring_alloc_output {
22870 /* The specific error status for the command. */
22871 uint16_t error_code;
22872 /* The HWRM command request type. */
22874 /* The sequence ID from the original command. */
22876 /* The length of the response data in number of bytes. */
22879 * Physical number of ring allocated.
22880 * This value shall be unique for a ring type.
22883 /* Logical number of ring allocated. */
22884 uint16_t logical_ring_id;
22885 uint8_t unused_0[3];
22887 * This field is used in Output records to indicate that the output
22888 * is completely written to RAM. This field should be read as '1'
22889 * to indicate that the output has been completely written.
22890 * When writing a command completion or response to an internal processor,
22891 * the order of writes has to be such that this field is written last.
22894 } __attribute__((packed));
22896 /******************
22898 ******************/
22901 /* hwrm_ring_free_input (size:192b/24B) */
22902 struct hwrm_ring_free_input {
22903 /* The HWRM command request type. */
22906 * The completion ring to send the completion event on. This should
22907 * be the NQ ID returned from the `nq_alloc` HWRM command.
22909 uint16_t cmpl_ring;
22911 * The sequence ID is used by the driver for tracking multiple
22912 * commands. This ID is treated as opaque data by the firmware and
22913 * the value is returned in the `hwrm_resp_hdr` upon completion.
22917 * The target ID of the command:
22918 * * 0x0-0xFFF8 - The function ID
22919 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
22920 * * 0xFFFD - Reserved for user-space HWRM interface
22923 uint16_t target_id;
22925 * A physical address pointer pointing to a host buffer that the
22926 * command's response data will be written. This can be either a host
22927 * physical address (HPA) or a guest physical address (GPA) and must
22928 * point to a physically contiguous block of memory.
22930 uint64_t resp_addr;
22933 /* L2 Completion Ring (CR) */
22934 #define HWRM_RING_FREE_INPUT_RING_TYPE_L2_CMPL UINT32_C(0x0)
22936 #define HWRM_RING_FREE_INPUT_RING_TYPE_TX UINT32_C(0x1)
22938 #define HWRM_RING_FREE_INPUT_RING_TYPE_RX UINT32_C(0x2)
22939 /* RoCE Notification Completion Ring (ROCE_CR) */
22940 #define HWRM_RING_FREE_INPUT_RING_TYPE_ROCE_CMPL UINT32_C(0x3)
22941 /* RX Aggregation Ring */
22942 #define HWRM_RING_FREE_INPUT_RING_TYPE_RX_AGG UINT32_C(0x4)
22943 /* Notification Queue */
22944 #define HWRM_RING_FREE_INPUT_RING_TYPE_NQ UINT32_C(0x5)
22945 #define HWRM_RING_FREE_INPUT_RING_TYPE_LAST \
22946 HWRM_RING_FREE_INPUT_RING_TYPE_NQ
22948 /* Physical number of ring allocated. */
22950 uint8_t unused_1[4];
22951 } __attribute__((packed));
22953 /* hwrm_ring_free_output (size:128b/16B) */
22954 struct hwrm_ring_free_output {
22955 /* The specific error status for the command. */
22956 uint16_t error_code;
22957 /* The HWRM command request type. */
22959 /* The sequence ID from the original command. */
22961 /* The length of the response data in number of bytes. */
22963 uint8_t unused_0[7];
22965 * This field is used in Output records to indicate that the output
22966 * is completely written to RAM. This field should be read as '1'
22967 * to indicate that the output has been completely written.
22968 * When writing a command completion or response to an internal processor,
22969 * the order of writes has to be such that this field is written last.
22972 } __attribute__((packed));
22974 /*******************
22975 * hwrm_ring_reset *
22976 *******************/
22979 /* hwrm_ring_reset_input (size:192b/24B) */
22980 struct hwrm_ring_reset_input {
22981 /* The HWRM command request type. */
22984 * The completion ring to send the completion event on. This should
22985 * be the NQ ID returned from the `nq_alloc` HWRM command.
22987 uint16_t cmpl_ring;
22989 * The sequence ID is used by the driver for tracking multiple
22990 * commands. This ID is treated as opaque data by the firmware and
22991 * the value is returned in the `hwrm_resp_hdr` upon completion.
22995 * The target ID of the command:
22996 * * 0x0-0xFFF8 - The function ID
22997 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
22998 * * 0xFFFD - Reserved for user-space HWRM interface
23001 uint16_t target_id;
23003 * A physical address pointer pointing to a host buffer that the
23004 * command's response data will be written. This can be either a host
23005 * physical address (HPA) or a guest physical address (GPA) and must
23006 * point to a physically contiguous block of memory.
23008 uint64_t resp_addr;
23011 /* L2 Completion Ring (CR) */
23012 #define HWRM_RING_RESET_INPUT_RING_TYPE_L2_CMPL UINT32_C(0x0)
23014 #define HWRM_RING_RESET_INPUT_RING_TYPE_TX UINT32_C(0x1)
23016 #define HWRM_RING_RESET_INPUT_RING_TYPE_RX UINT32_C(0x2)
23017 /* RoCE Notification Completion Ring (ROCE_CR) */
23018 #define HWRM_RING_RESET_INPUT_RING_TYPE_ROCE_CMPL UINT32_C(0x3)
23019 #define HWRM_RING_RESET_INPUT_RING_TYPE_LAST \
23020 HWRM_RING_RESET_INPUT_RING_TYPE_ROCE_CMPL
23022 /* Physical number of the ring. */
23024 uint8_t unused_1[4];
23025 } __attribute__((packed));
23027 /* hwrm_ring_reset_output (size:128b/16B) */
23028 struct hwrm_ring_reset_output {
23029 /* The specific error status for the command. */
23030 uint16_t error_code;
23031 /* The HWRM command request type. */
23033 /* The sequence ID from the original command. */
23035 /* The length of the response data in number of bytes. */
23037 uint8_t unused_0[4];
23038 /* Position of consumer index after ring reset completes. */
23039 uint8_t consumer_idx[3];
23041 * This field is used in Output records to indicate that the output
23042 * is completely written to RAM. This field should be read as '1'
23043 * to indicate that the output has been completely written.
23044 * When writing a command completion or response to an internal processor,
23045 * the order of writes has to be such that this field is written last.
23048 } __attribute__((packed));
23050 /**************************
23051 * hwrm_ring_aggint_qcaps *
23052 **************************/
23055 /* hwrm_ring_aggint_qcaps_input (size:128b/16B) */
23056 struct hwrm_ring_aggint_qcaps_input {
23057 /* The HWRM command request type. */
23060 * The completion ring to send the completion event on. This should
23061 * be the NQ ID returned from the `nq_alloc` HWRM command.
23063 uint16_t cmpl_ring;
23065 * The sequence ID is used by the driver for tracking multiple
23066 * commands. This ID is treated as opaque data by the firmware and
23067 * the value is returned in the `hwrm_resp_hdr` upon completion.
23071 * The target ID of the command:
23072 * * 0x0-0xFFF8 - The function ID
23073 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
23074 * * 0xFFFD - Reserved for user-space HWRM interface
23077 uint16_t target_id;
23079 * A physical address pointer pointing to a host buffer that the
23080 * command's response data will be written. This can be either a host
23081 * physical address (HPA) or a guest physical address (GPA) and must
23082 * point to a physically contiguous block of memory.
23084 uint64_t resp_addr;
23085 } __attribute__((packed));
23087 /* hwrm_ring_aggint_qcaps_output (size:384b/48B) */
23088 struct hwrm_ring_aggint_qcaps_output {
23089 /* The specific error status for the command. */
23090 uint16_t error_code;
23091 /* The HWRM command request type. */
23093 /* The sequence ID from the original command. */
23095 /* The length of the response data in number of bytes. */
23097 uint32_t cmpl_params;
23099 * When this bit is set to '1', int_lat_tmr_min can be configured
23100 * on completion rings.
23102 #define HWRM_RING_AGGINT_QCAPS_OUTPUT_CMPL_PARAMS_INT_LAT_TMR_MIN \
23105 * When this bit is set to '1', int_lat_tmr_max can be configured
23106 * on completion rings.
23108 #define HWRM_RING_AGGINT_QCAPS_OUTPUT_CMPL_PARAMS_INT_LAT_TMR_MAX \
23111 * When this bit is set to '1', timer_reset can be enabled
23112 * on completion rings.
23114 #define HWRM_RING_AGGINT_QCAPS_OUTPUT_CMPL_PARAMS_TIMER_RESET \
23117 * When this bit is set to '1', ring_idle can be enabled
23118 * on completion rings.
23120 #define HWRM_RING_AGGINT_QCAPS_OUTPUT_CMPL_PARAMS_RING_IDLE \
23123 * When this bit is set to '1', num_cmpl_dma_aggr can be configured
23124 * on completion rings.
23126 #define HWRM_RING_AGGINT_QCAPS_OUTPUT_CMPL_PARAMS_NUM_CMPL_DMA_AGGR \
23129 * When this bit is set to '1', num_cmpl_dma_aggr_during_int can be configured
23130 * on completion rings.
23132 #define HWRM_RING_AGGINT_QCAPS_OUTPUT_CMPL_PARAMS_NUM_CMPL_DMA_AGGR_DURING_INT \
23135 * When this bit is set to '1', cmpl_aggr_dma_tmr can be configured
23136 * on completion rings.
23138 #define HWRM_RING_AGGINT_QCAPS_OUTPUT_CMPL_PARAMS_CMPL_AGGR_DMA_TMR \
23141 * When this bit is set to '1', cmpl_aggr_dma_tmr_during_int can be configured
23142 * on completion rings.
23144 #define HWRM_RING_AGGINT_QCAPS_OUTPUT_CMPL_PARAMS_CMPL_AGGR_DMA_TMR_DURING_INT \
23147 * When this bit is set to '1', num_cmpl_aggr_int can be configured
23148 * on completion rings.
23150 #define HWRM_RING_AGGINT_QCAPS_OUTPUT_CMPL_PARAMS_NUM_CMPL_AGGR_INT \
23152 uint32_t nq_params;
23154 * When this bit is set to '1', int_lat_tmr_min can be configured
23155 * on notification queues.
23157 #define HWRM_RING_AGGINT_QCAPS_OUTPUT_NQ_PARAMS_INT_LAT_TMR_MIN \
23159 /* Minimum value for num_cmpl_dma_aggr */
23160 uint16_t num_cmpl_dma_aggr_min;
23161 /* Maximum value for num_cmpl_dma_aggr */
23162 uint16_t num_cmpl_dma_aggr_max;
23163 /* Minimum value for num_cmpl_dma_aggr_during_int */
23164 uint16_t num_cmpl_dma_aggr_during_int_min;
23165 /* Maximum value for num_cmpl_dma_aggr_during_int */
23166 uint16_t num_cmpl_dma_aggr_during_int_max;
23167 /* Minimum value for cmpl_aggr_dma_tmr */
23168 uint16_t cmpl_aggr_dma_tmr_min;
23169 /* Maximum value for cmpl_aggr_dma_tmr */
23170 uint16_t cmpl_aggr_dma_tmr_max;
23171 /* Minimum value for cmpl_aggr_dma_tmr_during_int */
23172 uint16_t cmpl_aggr_dma_tmr_during_int_min;
23173 /* Maximum value for cmpl_aggr_dma_tmr_during_int */
23174 uint16_t cmpl_aggr_dma_tmr_during_int_max;
23175 /* Minimum value for int_lat_tmr_min */
23176 uint16_t int_lat_tmr_min_min;
23177 /* Maximum value for int_lat_tmr_min */
23178 uint16_t int_lat_tmr_min_max;
23179 /* Minimum value for int_lat_tmr_max */
23180 uint16_t int_lat_tmr_max_min;
23181 /* Maximum value for int_lat_tmr_max */
23182 uint16_t int_lat_tmr_max_max;
23183 /* Minimum value for num_cmpl_aggr_int */
23184 uint16_t num_cmpl_aggr_int_min;
23185 /* Maximum value for num_cmpl_aggr_int */
23186 uint16_t num_cmpl_aggr_int_max;
23187 /* The units for timer parameters, in nanoseconds. */
23188 uint16_t timer_units;
23189 uint8_t unused_0[1];
23191 * This field is used in Output records to indicate that the output
23192 * is completely written to RAM. This field should be read as '1'
23193 * to indicate that the output has been completely written.
23194 * When writing a command completion or response to an internal processor,
23195 * the order of writes has to be such that this field is written last.
23198 } __attribute__((packed));
23200 /**************************************
23201 * hwrm_ring_cmpl_ring_qaggint_params *
23202 **************************************/
23205 /* hwrm_ring_cmpl_ring_qaggint_params_input (size:192b/24B) */
23206 struct hwrm_ring_cmpl_ring_qaggint_params_input {
23207 /* The HWRM command request type. */
23210 * The completion ring to send the completion event on. This should
23211 * be the NQ ID returned from the `nq_alloc` HWRM command.
23213 uint16_t cmpl_ring;
23215 * The sequence ID is used by the driver for tracking multiple
23216 * commands. This ID is treated as opaque data by the firmware and
23217 * the value is returned in the `hwrm_resp_hdr` upon completion.
23221 * The target ID of the command:
23222 * * 0x0-0xFFF8 - The function ID
23223 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
23224 * * 0xFFFD - Reserved for user-space HWRM interface
23227 uint16_t target_id;
23229 * A physical address pointer pointing to a host buffer that the
23230 * command's response data will be written. This can be either a host
23231 * physical address (HPA) or a guest physical address (GPA) and must
23232 * point to a physically contiguous block of memory.
23234 uint64_t resp_addr;
23235 /* Physical number of completion ring. */
23237 uint8_t unused_0[6];
23238 } __attribute__((packed));
23240 /* hwrm_ring_cmpl_ring_qaggint_params_output (size:256b/32B) */
23241 struct hwrm_ring_cmpl_ring_qaggint_params_output {
23242 /* The specific error status for the command. */
23243 uint16_t error_code;
23244 /* The HWRM command request type. */
23246 /* The sequence ID from the original command. */
23248 /* The length of the response data in number of bytes. */
23252 * When this bit is set to '1', interrupt max
23253 * timer is reset whenever a completion is received.
23255 #define HWRM_RING_CMPL_RING_QAGGINT_PARAMS_OUTPUT_FLAGS_TIMER_RESET \
23258 * When this bit is set to '1', ring idle mode
23259 * aggregation will be enabled.
23261 #define HWRM_RING_CMPL_RING_QAGGINT_PARAMS_OUTPUT_FLAGS_RING_IDLE \
23264 * Number of completions to aggregate before DMA
23265 * during the normal mode.
23267 uint16_t num_cmpl_dma_aggr;
23269 * Number of completions to aggregate before DMA
23270 * during the interrupt mode.
23272 uint16_t num_cmpl_dma_aggr_during_int;
23274 * Timer in unit of 80-nsec used to aggregate completions before
23275 * DMA during the normal mode (not in interrupt mode).
23277 uint16_t cmpl_aggr_dma_tmr;
23279 * Timer in unit of 80-nsec used to aggregate completions before
23280 * DMA during the interrupt mode.
23282 uint16_t cmpl_aggr_dma_tmr_during_int;
23283 /* Minimum time (in unit of 80-nsec) between two interrupts. */
23284 uint16_t int_lat_tmr_min;
23286 * Maximum wait time (in unit of 80-nsec) spent aggregating
23287 * completions before signaling the interrupt after the
23288 * interrupt is enabled.
23290 uint16_t int_lat_tmr_max;
23292 * Minimum number of completions aggregated before signaling
23295 uint16_t num_cmpl_aggr_int;
23296 uint8_t unused_0[7];
23298 * This field is used in Output records to indicate that the output
23299 * is completely written to RAM. This field should be read as '1'
23300 * to indicate that the output has been completely written.
23301 * When writing a command completion or response to an internal processor,
23302 * the order of writes has to be such that this field is written last.
23305 } __attribute__((packed));
23307 /*****************************************
23308 * hwrm_ring_cmpl_ring_cfg_aggint_params *
23309 *****************************************/
23312 /* hwrm_ring_cmpl_ring_cfg_aggint_params_input (size:320b/40B) */
23313 struct hwrm_ring_cmpl_ring_cfg_aggint_params_input {
23314 /* The HWRM command request type. */
23317 * The completion ring to send the completion event on. This should
23318 * be the NQ ID returned from the `nq_alloc` HWRM command.
23320 uint16_t cmpl_ring;
23322 * The sequence ID is used by the driver for tracking multiple
23323 * commands. This ID is treated as opaque data by the firmware and
23324 * the value is returned in the `hwrm_resp_hdr` upon completion.
23328 * The target ID of the command:
23329 * * 0x0-0xFFF8 - The function ID
23330 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
23331 * * 0xFFFD - Reserved for user-space HWRM interface
23334 uint16_t target_id;
23336 * A physical address pointer pointing to a host buffer that the
23337 * command's response data will be written. This can be either a host
23338 * physical address (HPA) or a guest physical address (GPA) and must
23339 * point to a physically contiguous block of memory.
23341 uint64_t resp_addr;
23342 /* Physical number of completion ring. */
23346 * When this bit is set to '1', interrupt latency max
23347 * timer is reset whenever a completion is received.
23349 #define HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_FLAGS_TIMER_RESET \
23352 * When this bit is set to '1', ring idle mode
23353 * aggregation will be enabled.
23355 #define HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_FLAGS_RING_IDLE \
23358 * Set this flag to 1 when configuring parameters on a
23359 * notification queue. Set this flag to 0 when configuring
23360 * parameters on a completion queue.
23362 #define HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_FLAGS_IS_NQ \
23365 * Number of completions to aggregate before DMA
23366 * during the normal mode.
23368 uint16_t num_cmpl_dma_aggr;
23370 * Number of completions to aggregate before DMA
23371 * during the interrupt mode.
23373 uint16_t num_cmpl_dma_aggr_during_int;
23375 * Timer in unit of 80-nsec used to aggregate completions before
23376 * DMA during the normal mode (not in interrupt mode).
23378 uint16_t cmpl_aggr_dma_tmr;
23380 * Timer in unit of 80-nsec used to aggregate completions before
23381 * DMA during the interrupt mode.
23383 uint16_t cmpl_aggr_dma_tmr_during_int;
23384 /* Minimum time (in unit of 80-nsec) between two interrupts. */
23385 uint16_t int_lat_tmr_min;
23387 * Maximum wait time (in unit of 80-nsec) spent aggregating
23388 * cmpls before signaling the interrupt after the
23389 * interrupt is enabled.
23391 uint16_t int_lat_tmr_max;
23393 * Minimum number of completions aggregated before signaling
23396 uint16_t num_cmpl_aggr_int;
23398 * Bitfield that indicates which parameters are to be applied. Only
23399 * required when configuring devices with notification queues, and
23400 * used in that case to set certain parameters on completion queues
23401 * and others on notification queues.
23405 * This bit must be '1' for the num_cmpl_dma_aggr field to be
23408 #define HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_ENABLES_NUM_CMPL_DMA_AGGR \
23411 * This bit must be '1' for the num_cmpl_dma_aggr_during_int field to be
23414 #define HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_ENABLES_NUM_CMPL_DMA_AGGR_DURING_INT \
23417 * This bit must be '1' for the cmpl_aggr_dma_tmr field to be
23420 #define HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_ENABLES_CMPL_AGGR_DMA_TMR \
23423 * This bit must be '1' for the int_lat_tmr_min field to be
23426 #define HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_ENABLES_INT_LAT_TMR_MIN \
23429 * This bit must be '1' for the int_lat_tmr_max field to be
23432 #define HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_ENABLES_INT_LAT_TMR_MAX \
23435 * This bit must be '1' for the num_cmpl_aggr_int field to be
23438 #define HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_ENABLES_NUM_CMPL_AGGR_INT \
23440 uint8_t unused_0[4];
23441 } __attribute__((packed));
23443 /* hwrm_ring_cmpl_ring_cfg_aggint_params_output (size:128b/16B) */
23444 struct hwrm_ring_cmpl_ring_cfg_aggint_params_output {
23445 /* The specific error status for the command. */
23446 uint16_t error_code;
23447 /* The HWRM command request type. */
23449 /* The sequence ID from the original command. */
23451 /* The length of the response data in number of bytes. */
23453 uint8_t unused_0[7];
23455 * This field is used in Output records to indicate that the output
23456 * is completely written to RAM. This field should be read as '1'
23457 * to indicate that the output has been completely written.
23458 * When writing a command completion or response to an internal processor,
23459 * the order of writes has to be such that this field is written last.
23462 } __attribute__((packed));
23464 /***********************
23465 * hwrm_ring_grp_alloc *
23466 ***********************/
23469 /* hwrm_ring_grp_alloc_input (size:192b/24B) */
23470 struct hwrm_ring_grp_alloc_input {
23471 /* The HWRM command request type. */
23474 * The completion ring to send the completion event on. This should
23475 * be the NQ ID returned from the `nq_alloc` HWRM command.
23477 uint16_t cmpl_ring;
23479 * The sequence ID is used by the driver for tracking multiple
23480 * commands. This ID is treated as opaque data by the firmware and
23481 * the value is returned in the `hwrm_resp_hdr` upon completion.
23485 * The target ID of the command:
23486 * * 0x0-0xFFF8 - The function ID
23487 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
23488 * * 0xFFFD - Reserved for user-space HWRM interface
23491 uint16_t target_id;
23493 * A physical address pointer pointing to a host buffer that the
23494 * command's response data will be written. This can be either a host
23495 * physical address (HPA) or a guest physical address (GPA) and must
23496 * point to a physically contiguous block of memory.
23498 uint64_t resp_addr;
23500 * This value identifies the CR associated with the ring
23505 * This value identifies the main RR associated with the ring
23510 * This value identifies the aggregation RR associated with
23511 * the ring group. If this value is 0xFF... (All Fs), then no
23512 * Aggregation ring will be set.
23516 * This value identifies the statistics context associated
23517 * with the ring group.
23520 } __attribute__((packed));
23522 /* hwrm_ring_grp_alloc_output (size:128b/16B) */
23523 struct hwrm_ring_grp_alloc_output {
23524 /* The specific error status for the command. */
23525 uint16_t error_code;
23526 /* The HWRM command request type. */
23528 /* The sequence ID from the original command. */
23530 /* The length of the response data in number of bytes. */
23533 * This is the ring group ID value. Use this value to program
23534 * the default ring group for the VNIC or as table entries
23535 * in an RSS/COS context.
23537 uint32_t ring_group_id;
23538 uint8_t unused_0[3];
23540 * This field is used in Output records to indicate that the output
23541 * is completely written to RAM. This field should be read as '1'
23542 * to indicate that the output has been completely written.
23543 * When writing a command completion or response to an internal processor,
23544 * the order of writes has to be such that this field is written last.
23547 } __attribute__((packed));
23549 /**********************
23550 * hwrm_ring_grp_free *
23551 **********************/
23554 /* hwrm_ring_grp_free_input (size:192b/24B) */
23555 struct hwrm_ring_grp_free_input {
23556 /* The HWRM command request type. */
23559 * The completion ring to send the completion event on. This should
23560 * be the NQ ID returned from the `nq_alloc` HWRM command.
23562 uint16_t cmpl_ring;
23564 * The sequence ID is used by the driver for tracking multiple
23565 * commands. This ID is treated as opaque data by the firmware and
23566 * the value is returned in the `hwrm_resp_hdr` upon completion.
23570 * The target ID of the command:
23571 * * 0x0-0xFFF8 - The function ID
23572 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
23573 * * 0xFFFD - Reserved for user-space HWRM interface
23576 uint16_t target_id;
23578 * A physical address pointer pointing to a host buffer that the
23579 * command's response data will be written. This can be either a host
23580 * physical address (HPA) or a guest physical address (GPA) and must
23581 * point to a physically contiguous block of memory.
23583 uint64_t resp_addr;
23584 /* This is the ring group ID value. */
23585 uint32_t ring_group_id;
23586 uint8_t unused_0[4];
23587 } __attribute__((packed));
23589 /* hwrm_ring_grp_free_output (size:128b/16B) */
23590 struct hwrm_ring_grp_free_output {
23591 /* The specific error status for the command. */
23592 uint16_t error_code;
23593 /* The HWRM command request type. */
23595 /* The sequence ID from the original command. */
23597 /* The length of the response data in number of bytes. */
23599 uint8_t unused_0[7];
23601 * This field is used in Output records to indicate that the output
23602 * is completely written to RAM. This field should be read as '1'
23603 * to indicate that the output has been completely written.
23604 * When writing a command completion or response to an internal processor,
23605 * the order of writes has to be such that this field is written last.
23608 } __attribute__((packed));
23610 * special reserved flow ID to identify per function default
23611 * flows for vSwitch offload
23613 #define DEFAULT_FLOW_ID 0xFFFFFFFFUL
23615 * special reserved flow ID to identify per function RoCEv1
23618 #define ROCEV1_FLOW_ID 0xFFFFFFFEUL
23620 * special reserved flow ID to identify per function RoCEv2
23623 #define ROCEV2_FLOW_ID 0xFFFFFFFDUL
23625 * special reserved flow ID to identify per function RoCEv2
23628 #define ROCEV2_CNP_FLOW_ID 0xFFFFFFFCUL
23630 /****************************
23631 * hwrm_cfa_l2_filter_alloc *
23632 ****************************/
23635 /* hwrm_cfa_l2_filter_alloc_input (size:768b/96B) */
23636 struct hwrm_cfa_l2_filter_alloc_input {
23637 /* The HWRM command request type. */
23640 * The completion ring to send the completion event on. This should
23641 * be the NQ ID returned from the `nq_alloc` HWRM command.
23643 uint16_t cmpl_ring;
23645 * The sequence ID is used by the driver for tracking multiple
23646 * commands. This ID is treated as opaque data by the firmware and
23647 * the value is returned in the `hwrm_resp_hdr` upon completion.
23651 * The target ID of the command:
23652 * * 0x0-0xFFF8 - The function ID
23653 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
23654 * * 0xFFFD - Reserved for user-space HWRM interface
23657 uint16_t target_id;
23659 * A physical address pointer pointing to a host buffer that the
23660 * command's response data will be written. This can be either a host
23661 * physical address (HPA) or a guest physical address (GPA) and must
23662 * point to a physically contiguous block of memory.
23664 uint64_t resp_addr;
23667 * Enumeration denoting the RX, TX type of the resource.
23668 * This enumeration is used for resources that are similar for both
23669 * TX and RX paths of the chip.
23671 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_PATH \
23674 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_PATH_TX \
23677 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_PATH_RX \
23679 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_PATH_LAST \
23680 HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_PATH_RX
23681 /* Setting of this flag indicates the applicability to the loopback path. */
23682 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_LOOPBACK \
23685 * Setting of this flag indicates drop action. If this flag is not set,
23686 * then it should be considered accept action.
23688 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_DROP \
23691 * If this flag is set, all t_l2_* fields are invalid
23692 * and they should not be specified.
23693 * If this flag is set, then l2_* fields refer to
23694 * fields of outermost L2 header.
23696 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_OUTERMOST \
23699 * Enumeration denoting NO_ROCE_L2 to support old drivers.
23700 * New driver L2 for only L2 traffic, ROCE for roce and l2 traffic
23702 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_TRAFFIC_MASK \
23704 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_TRAFFIC_SFT 4
23705 /* To support old drivers */
23706 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_TRAFFIC_NO_ROCE_L2 \
23707 (UINT32_C(0x0) << 4)
23708 /* Only L2 traffic */
23709 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_TRAFFIC_L2 \
23710 (UINT32_C(0x1) << 4)
23711 /* Roce & L2 traffic */
23712 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_TRAFFIC_ROCE \
23713 (UINT32_C(0x2) << 4)
23714 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_TRAFFIC_LAST \
23715 HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_TRAFFIC_ROCE
23717 * Setting of this flag indicates that no XDP filter is created with
23719 * 0 - legacy behavior, XDP filter is created with L2 filter
23720 * 1 - XDP filter won't be created with L2 filter
23722 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_XDP_DISABLE \
23725 * Setting this flag to 1 indicate the L2 fields in this command
23726 * pertain to source fields. Setting this flag to 0 indicate the
23727 * L2 fields in this command pertain to the destination fields
23728 * and this is the default/legacy behavior.
23730 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_SOURCE_VALID \
23734 * This bit must be '1' for the l2_addr field to be
23737 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_ADDR \
23740 * This bit must be '1' for the l2_addr_mask field to be
23743 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_ADDR_MASK \
23746 * This bit must be '1' for the l2_ovlan field to be
23749 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_OVLAN \
23752 * This bit must be '1' for the l2_ovlan_mask field to be
23755 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_OVLAN_MASK \
23758 * This bit must be '1' for the l2_ivlan field to be
23761 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN \
23764 * This bit must be '1' for the l2_ivlan_mask field to be
23767 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN_MASK \
23770 * This bit must be '1' for the t_l2_addr field to be
23773 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_T_L2_ADDR \
23776 * This bit must be '1' for the t_l2_addr_mask field to be
23779 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_T_L2_ADDR_MASK \
23782 * This bit must be '1' for the t_l2_ovlan field to be
23785 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_T_L2_OVLAN \
23788 * This bit must be '1' for the t_l2_ovlan_mask field to be
23791 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_T_L2_OVLAN_MASK \
23794 * This bit must be '1' for the t_l2_ivlan field to be
23797 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_T_L2_IVLAN \
23800 * This bit must be '1' for the t_l2_ivlan_mask field to be
23803 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_T_L2_IVLAN_MASK \
23806 * This bit must be '1' for the src_type field to be
23809 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_SRC_TYPE \
23812 * This bit must be '1' for the src_id field to be
23815 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_SRC_ID \
23818 * This bit must be '1' for the tunnel_type field to be
23821 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_TUNNEL_TYPE \
23824 * This bit must be '1' for the dst_id field to be
23827 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_DST_ID \
23830 * This bit must be '1' for the mirror_vnic_id field to be
23833 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_MIRROR_VNIC_ID \
23836 * This bit must be '1' for the num_vlans field to be
23839 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_NUM_VLANS \
23842 * This bit must be '1' for the t_num_vlans field to be
23845 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_T_NUM_VLANS \
23848 * This value sets the match value for the L2 MAC address.
23849 * Destination MAC address for RX path.
23850 * Source MAC address for TX path.
23852 uint8_t l2_addr[6];
23853 /* This value sets the match value for the number of VLANs. */
23856 * This value sets the match value for the number of VLANs
23857 * in the tunnel headers.
23859 uint8_t t_num_vlans;
23861 * This value sets the mask value for the L2 address.
23862 * A value of 0 will mask the corresponding bit from
23865 uint8_t l2_addr_mask[6];
23866 /* This value sets VLAN ID value for outer VLAN. */
23869 * This value sets the mask value for the ovlan id.
23870 * A value of 0 will mask the corresponding bit from
23873 uint16_t l2_ovlan_mask;
23874 /* This value sets VLAN ID value for inner VLAN. */
23877 * This value sets the mask value for the ivlan id.
23878 * A value of 0 will mask the corresponding bit from
23881 uint16_t l2_ivlan_mask;
23882 uint8_t unused_1[2];
23884 * This value sets the match value for the tunnel
23886 * Destination MAC address for RX path.
23887 * Source MAC address for TX path.
23889 uint8_t t_l2_addr[6];
23890 uint8_t unused_2[2];
23892 * This value sets the mask value for the tunnel L2
23894 * A value of 0 will mask the corresponding bit from
23897 uint8_t t_l2_addr_mask[6];
23898 /* This value sets VLAN ID value for tunnel outer VLAN. */
23899 uint16_t t_l2_ovlan;
23901 * This value sets the mask value for the tunnel ovlan id.
23902 * A value of 0 will mask the corresponding bit from
23905 uint16_t t_l2_ovlan_mask;
23906 /* This value sets VLAN ID value for tunnel inner VLAN. */
23907 uint16_t t_l2_ivlan;
23909 * This value sets the mask value for the tunnel ivlan id.
23910 * A value of 0 will mask the corresponding bit from
23913 uint16_t t_l2_ivlan_mask;
23914 /* This value identifies the type of source of the packet. */
23917 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_SRC_TYPE_NPORT UINT32_C(0x0)
23918 /* Physical function */
23919 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_SRC_TYPE_PF UINT32_C(0x1)
23920 /* Virtual function */
23921 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_SRC_TYPE_VF UINT32_C(0x2)
23922 /* Virtual NIC of a function */
23923 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_SRC_TYPE_VNIC UINT32_C(0x3)
23924 /* Embedded processor for CFA management */
23925 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_SRC_TYPE_KONG UINT32_C(0x4)
23926 /* Embedded processor for OOB management */
23927 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_SRC_TYPE_APE UINT32_C(0x5)
23928 /* Embedded processor for RoCE */
23929 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_SRC_TYPE_BONO UINT32_C(0x6)
23930 /* Embedded processor for network proxy functions */
23931 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_SRC_TYPE_TANG UINT32_C(0x7)
23932 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_SRC_TYPE_LAST \
23933 HWRM_CFA_L2_FILTER_ALLOC_INPUT_SRC_TYPE_TANG
23936 * This value is the id of the source.
23937 * For a network port, it represents port_id.
23938 * For a physical function, it represents fid.
23939 * For a virtual function, it represents vf_id.
23940 * For a vnic, it represents vnic_id.
23941 * For embedded processors, this id is not valid.
23944 * 1. The function ID is implied if it src_id is
23945 * not provided for a src_type that is either
23949 uint8_t tunnel_type;
23951 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_TUNNEL_TYPE_NONTUNNEL \
23953 /* Virtual eXtensible Local Area Network (VXLAN) */
23954 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_TUNNEL_TYPE_VXLAN \
23956 /* Network Virtualization Generic Routing Encapsulation (NVGRE) */
23957 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_TUNNEL_TYPE_NVGRE \
23959 /* Generic Routing Encapsulation (GRE) inside Ethernet payload */
23960 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_TUNNEL_TYPE_L2GRE \
23963 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_TUNNEL_TYPE_IPIP \
23965 /* Generic Network Virtualization Encapsulation (Geneve) */
23966 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_TUNNEL_TYPE_GENEVE \
23968 /* Multi-Protocol Lable Switching (MPLS) */
23969 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_TUNNEL_TYPE_MPLS \
23971 /* Stateless Transport Tunnel (STT) */
23972 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_TUNNEL_TYPE_STT \
23974 /* Generic Routing Encapsulation (GRE) inside IP datagram payload */
23975 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_TUNNEL_TYPE_IPGRE \
23977 /* IPV4 over virtual eXtensible Local Area Network (IPV4oVXLAN) */
23978 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_TUNNEL_TYPE_VXLAN_V4 \
23980 /* Enhance Generic Routing Encapsulation (GRE version 1) inside IP datagram payload */
23981 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_TUNNEL_TYPE_IPGRE_V1 \
23983 /* Use fixed layer 2 ether type of 0xFFFF */
23984 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_TUNNEL_TYPE_L2_ETYPE \
23986 /* IPV6 over virtual eXtensible Local Area Network with GPE header (IPV6oVXLANGPE) */
23987 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_TUNNEL_TYPE_VXLAN_GPE_V6 \
23989 /* Any tunneled traffic */
23990 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_TUNNEL_TYPE_ANYTUNNEL \
23992 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_TUNNEL_TYPE_LAST \
23993 HWRM_CFA_L2_FILTER_ALLOC_INPUT_TUNNEL_TYPE_ANYTUNNEL
23996 * If set, this value shall represent the
23997 * Logical VNIC ID of the destination VNIC for the RX
23998 * path and network port id of the destination port for
24003 * Logical VNIC ID of the VNIC where traffic is
24006 uint16_t mirror_vnic_id;
24008 * This hint is provided to help in placing
24009 * the filter in the filter table.
24012 /* No preference */
24013 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_PRI_HINT_NO_PREFER \
24015 /* Above the given filter */
24016 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_PRI_HINT_ABOVE_FILTER \
24018 /* Below the given filter */
24019 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_PRI_HINT_BELOW_FILTER \
24021 /* As high as possible */
24022 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_PRI_HINT_MAX \
24024 /* As low as possible */
24025 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_PRI_HINT_MIN \
24027 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_PRI_HINT_LAST \
24028 HWRM_CFA_L2_FILTER_ALLOC_INPUT_PRI_HINT_MIN
24032 * This is the ID of the filter that goes along with
24035 * This field is valid only for the following values.
24036 * 1 - Above the given filter
24037 * 2 - Below the given filter
24039 uint64_t l2_filter_id_hint;
24040 } __attribute__((packed));
24042 /* hwrm_cfa_l2_filter_alloc_output (size:192b/24B) */
24043 struct hwrm_cfa_l2_filter_alloc_output {
24044 /* The specific error status for the command. */
24045 uint16_t error_code;
24046 /* The HWRM command request type. */
24048 /* The sequence ID from the original command. */
24050 /* The length of the response data in number of bytes. */
24053 * This value identifies a set of CFA data structures used for an L2
24056 uint64_t l2_filter_id;
24058 * The flow id value in bit 0-29 is the actual ID of the flow
24059 * associated with this filter and it shall be used to match
24060 * and associate the flow identifier returned in completion
24061 * records. A value of 0xFFFFFFFF in the 32-bit flow_id field
24062 * shall indicate no valid flow id.
24065 /* Indicate the flow id value. */
24066 #define HWRM_CFA_L2_FILTER_ALLOC_OUTPUT_FLOW_ID_VALUE_MASK \
24067 UINT32_C(0x3fffffff)
24068 #define HWRM_CFA_L2_FILTER_ALLOC_OUTPUT_FLOW_ID_VALUE_SFT 0
24069 /* Indicate type of the flow. */
24070 #define HWRM_CFA_L2_FILTER_ALLOC_OUTPUT_FLOW_ID_TYPE \
24071 UINT32_C(0x40000000)
24073 * If this bit set to 0, then it indicates that the flow is
24076 #define HWRM_CFA_L2_FILTER_ALLOC_OUTPUT_FLOW_ID_TYPE_INT \
24077 (UINT32_C(0x0) << 30)
24079 * If this bit is set to 1, then it indicates that the flow is
24082 #define HWRM_CFA_L2_FILTER_ALLOC_OUTPUT_FLOW_ID_TYPE_EXT \
24083 (UINT32_C(0x1) << 30)
24084 #define HWRM_CFA_L2_FILTER_ALLOC_OUTPUT_FLOW_ID_TYPE_LAST \
24085 HWRM_CFA_L2_FILTER_ALLOC_OUTPUT_FLOW_ID_TYPE_EXT
24086 /* Indicate the flow direction. */
24087 #define HWRM_CFA_L2_FILTER_ALLOC_OUTPUT_FLOW_ID_DIR \
24088 UINT32_C(0x80000000)
24089 /* If this bit set to 0, then it indicates rx flow. */
24090 #define HWRM_CFA_L2_FILTER_ALLOC_OUTPUT_FLOW_ID_DIR_RX \
24091 (UINT32_C(0x0) << 31)
24092 /* If this bit is set to 1, then it indicates that tx flow. */
24093 #define HWRM_CFA_L2_FILTER_ALLOC_OUTPUT_FLOW_ID_DIR_TX \
24094 (UINT32_C(0x1) << 31)
24095 #define HWRM_CFA_L2_FILTER_ALLOC_OUTPUT_FLOW_ID_DIR_LAST \
24096 HWRM_CFA_L2_FILTER_ALLOC_OUTPUT_FLOW_ID_DIR_TX
24097 uint8_t unused_0[3];
24099 * This field is used in Output records to indicate that the output
24100 * is completely written to RAM. This field should be read as '1'
24101 * to indicate that the output has been completely written.
24102 * When writing a command completion or response to an internal processor,
24103 * the order of writes has to be such that this field is written last.
24106 } __attribute__((packed));
24108 /***************************
24109 * hwrm_cfa_l2_filter_free *
24110 ***************************/
24113 /* hwrm_cfa_l2_filter_free_input (size:192b/24B) */
24114 struct hwrm_cfa_l2_filter_free_input {
24115 /* The HWRM command request type. */
24118 * The completion ring to send the completion event on. This should
24119 * be the NQ ID returned from the `nq_alloc` HWRM command.
24121 uint16_t cmpl_ring;
24123 * The sequence ID is used by the driver for tracking multiple
24124 * commands. This ID is treated as opaque data by the firmware and
24125 * the value is returned in the `hwrm_resp_hdr` upon completion.
24129 * The target ID of the command:
24130 * * 0x0-0xFFF8 - The function ID
24131 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
24132 * * 0xFFFD - Reserved for user-space HWRM interface
24135 uint16_t target_id;
24137 * A physical address pointer pointing to a host buffer that the
24138 * command's response data will be written. This can be either a host
24139 * physical address (HPA) or a guest physical address (GPA) and must
24140 * point to a physically contiguous block of memory.
24142 uint64_t resp_addr;
24144 * This value identifies a set of CFA data structures used for an L2
24147 uint64_t l2_filter_id;
24148 } __attribute__((packed));
24150 /* hwrm_cfa_l2_filter_free_output (size:128b/16B) */
24151 struct hwrm_cfa_l2_filter_free_output {
24152 /* The specific error status for the command. */
24153 uint16_t error_code;
24154 /* The HWRM command request type. */
24156 /* The sequence ID from the original command. */
24158 /* The length of the response data in number of bytes. */
24160 uint8_t unused_0[7];
24162 * This field is used in Output records to indicate that the output
24163 * is completely written to RAM. This field should be read as '1'
24164 * to indicate that the output has been completely written.
24165 * When writing a command completion or response to an internal processor,
24166 * the order of writes has to be such that this field is written last.
24169 } __attribute__((packed));
24171 /**************************
24172 * hwrm_cfa_l2_filter_cfg *
24173 **************************/
24176 /* hwrm_cfa_l2_filter_cfg_input (size:320b/40B) */
24177 struct hwrm_cfa_l2_filter_cfg_input {
24178 /* The HWRM command request type. */
24181 * The completion ring to send the completion event on. This should
24182 * be the NQ ID returned from the `nq_alloc` HWRM command.
24184 uint16_t cmpl_ring;
24186 * The sequence ID is used by the driver for tracking multiple
24187 * commands. This ID is treated as opaque data by the firmware and
24188 * the value is returned in the `hwrm_resp_hdr` upon completion.
24192 * The target ID of the command:
24193 * * 0x0-0xFFF8 - The function ID
24194 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
24195 * * 0xFFFD - Reserved for user-space HWRM interface
24198 uint16_t target_id;
24200 * A physical address pointer pointing to a host buffer that the
24201 * command's response data will be written. This can be either a host
24202 * physical address (HPA) or a guest physical address (GPA) and must
24203 * point to a physically contiguous block of memory.
24205 uint64_t resp_addr;
24208 * Enumeration denoting the RX, TX type of the resource.
24209 * This enumeration is used for resources that are similar for both
24210 * TX and RX paths of the chip.
24212 #define HWRM_CFA_L2_FILTER_CFG_INPUT_FLAGS_PATH \
24215 #define HWRM_CFA_L2_FILTER_CFG_INPUT_FLAGS_PATH_TX \
24218 #define HWRM_CFA_L2_FILTER_CFG_INPUT_FLAGS_PATH_RX \
24220 #define HWRM_CFA_L2_FILTER_CFG_INPUT_FLAGS_PATH_LAST \
24221 HWRM_CFA_L2_FILTER_CFG_INPUT_FLAGS_PATH_RX
24223 * Setting of this flag indicates drop action. If this flag is not set,
24224 * then it should be considered accept action.
24226 #define HWRM_CFA_L2_FILTER_CFG_INPUT_FLAGS_DROP \
24229 * Enumeration denoting NO_ROCE_L2 to support old drivers.
24230 * New driver L2 for only L2 traffic, ROCE for roce and l2 traffic
24232 #define HWRM_CFA_L2_FILTER_CFG_INPUT_FLAGS_TRAFFIC_MASK \
24234 #define HWRM_CFA_L2_FILTER_CFG_INPUT_FLAGS_TRAFFIC_SFT 2
24235 /* To support old drivers */
24236 #define HWRM_CFA_L2_FILTER_CFG_INPUT_FLAGS_TRAFFIC_NO_ROCE_L2 \
24237 (UINT32_C(0x0) << 2)
24238 /* Only L2 traffic */
24239 #define HWRM_CFA_L2_FILTER_CFG_INPUT_FLAGS_TRAFFIC_L2 \
24240 (UINT32_C(0x1) << 2)
24241 /* Roce & L2 traffic */
24242 #define HWRM_CFA_L2_FILTER_CFG_INPUT_FLAGS_TRAFFIC_ROCE \
24243 (UINT32_C(0x2) << 2)
24244 #define HWRM_CFA_L2_FILTER_CFG_INPUT_FLAGS_TRAFFIC_LAST \
24245 HWRM_CFA_L2_FILTER_CFG_INPUT_FLAGS_TRAFFIC_ROCE
24248 * This bit must be '1' for the dst_id field to be
24251 #define HWRM_CFA_L2_FILTER_CFG_INPUT_ENABLES_DST_ID \
24254 * This bit must be '1' for the new_mirror_vnic_id field to be
24257 #define HWRM_CFA_L2_FILTER_CFG_INPUT_ENABLES_NEW_MIRROR_VNIC_ID \
24260 * This value identifies a set of CFA data structures used for an L2
24263 uint64_t l2_filter_id;
24265 * If set, this value shall represent the
24266 * Logical VNIC ID of the destination VNIC for the RX
24267 * path and network port id of the destination port for
24272 * New Logical VNIC ID of the VNIC where traffic is
24275 uint32_t new_mirror_vnic_id;
24276 } __attribute__((packed));
24278 /* hwrm_cfa_l2_filter_cfg_output (size:128b/16B) */
24279 struct hwrm_cfa_l2_filter_cfg_output {
24280 /* The specific error status for the command. */
24281 uint16_t error_code;
24282 /* The HWRM command request type. */
24284 /* The sequence ID from the original command. */
24286 /* The length of the response data in number of bytes. */
24288 uint8_t unused_0[7];
24290 * This field is used in Output records to indicate that the output
24291 * is completely written to RAM. This field should be read as '1'
24292 * to indicate that the output has been completely written.
24293 * When writing a command completion or response to an internal processor,
24294 * the order of writes has to be such that this field is written last.
24297 } __attribute__((packed));
24299 /***************************
24300 * hwrm_cfa_l2_set_rx_mask *
24301 ***************************/
24304 /* hwrm_cfa_l2_set_rx_mask_input (size:448b/56B) */
24305 struct hwrm_cfa_l2_set_rx_mask_input {
24306 /* The HWRM command request type. */
24309 * The completion ring to send the completion event on. This should
24310 * be the NQ ID returned from the `nq_alloc` HWRM command.
24312 uint16_t cmpl_ring;
24314 * The sequence ID is used by the driver for tracking multiple
24315 * commands. This ID is treated as opaque data by the firmware and
24316 * the value is returned in the `hwrm_resp_hdr` upon completion.
24320 * The target ID of the command:
24321 * * 0x0-0xFFF8 - The function ID
24322 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
24323 * * 0xFFFD - Reserved for user-space HWRM interface
24326 uint16_t target_id;
24328 * A physical address pointer pointing to a host buffer that the
24329 * command's response data will be written. This can be either a host
24330 * physical address (HPA) or a guest physical address (GPA) and must
24331 * point to a physically contiguous block of memory.
24333 uint64_t resp_addr;
24338 * When this bit is '1', the function is requested to accept
24339 * multi-cast packets specified by the multicast addr table.
24341 #define HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_MCAST \
24344 * When this bit is '1', the function is requested to accept
24345 * all multi-cast packets.
24347 #define HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_ALL_MCAST \
24350 * When this bit is '1', the function is requested to accept
24351 * broadcast packets.
24353 #define HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_BCAST \
24356 * When this bit is '1', the function is requested to be
24357 * put in the promiscuous mode.
24359 * The HWRM should accept any function to set up
24360 * promiscuous mode.
24362 * The HWRM shall follow the semantics below for the
24363 * promiscuous mode support.
24364 * # When partitioning is not enabled on a port
24365 * (i.e. single PF on the port), then the PF shall
24366 * be allowed to be in the promiscuous mode. When the
24367 * PF is in the promiscuous mode, then it shall
24368 * receive all host bound traffic on that port.
24369 * # When partitioning is enabled on a port
24370 * (i.e. multiple PFs per port) and a PF on that
24371 * port is in the promiscuous mode, then the PF
24372 * receives all traffic within that partition as
24373 * identified by a unique identifier for the
24374 * PF (e.g. S-Tag). If a unique outer VLAN
24375 * for the PF is specified, then the setting of
24376 * promiscuous mode on that PF shall result in the
24377 * PF receiving all host bound traffic with matching
24379 * # A VF shall can be set in the promiscuous mode.
24380 * In the promiscuous mode, the VF does not receive any
24381 * traffic unless a unique outer VLAN for the
24382 * VF is specified. If a unique outer VLAN
24383 * for the VF is specified, then the setting of
24384 * promiscuous mode on that VF shall result in the
24385 * VF receiving all host bound traffic with the
24386 * matching outer VLAN.
24387 * # The HWRM shall allow the setting of promiscuous
24388 * mode on a function independently from the
24389 * promiscuous mode settings on other functions.
24391 #define HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_PROMISCUOUS \
24394 * If this flag is set, the corresponding RX
24395 * filters shall be set up to cover multicast/broadcast
24396 * filters for the outermost Layer 2 destination MAC
24399 #define HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_OUTERMOST \
24402 * If this flag is set, the corresponding RX
24403 * filters shall be set up to cover multicast/broadcast
24404 * filters for the VLAN-tagged packets that match the
24405 * TPID and VID fields of VLAN tags in the VLAN tag
24406 * table specified in this command.
24408 #define HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_VLANONLY \
24411 * If this flag is set, the corresponding RX
24412 * filters shall be set up to cover multicast/broadcast
24413 * filters for non-VLAN tagged packets and VLAN-tagged
24414 * packets that match the TPID and VID fields of VLAN
24415 * tags in the VLAN tag table specified in this command.
24417 #define HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_VLAN_NONVLAN \
24420 * If this flag is set, the corresponding RX
24421 * filters shall be set up to cover multicast/broadcast
24422 * filters for non-VLAN tagged packets and VLAN-tagged
24423 * packets matching any VLAN tag.
24425 * If this flag is set, then the HWRM shall ignore
24426 * VLAN tags specified in vlan_tag_tbl.
24428 * If none of vlanonly, vlan_nonvlan, and anyvlan_nonvlan
24429 * flags is set, then the HWRM shall ignore
24430 * VLAN tags specified in vlan_tag_tbl.
24432 * The HWRM client shall set at most one flag out of
24433 * vlanonly, vlan_nonvlan, and anyvlan_nonvlan.
24435 #define HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_ANYVLAN_NONVLAN \
24437 /* This is the address for mcast address tbl. */
24438 uint64_t mc_tbl_addr;
24440 * This value indicates how many entries in mc_tbl are valid.
24441 * Each entry is 6 bytes.
24443 uint32_t num_mc_entries;
24444 uint8_t unused_0[4];
24446 * This is the address for VLAN tag table.
24447 * Each VLAN entry in the table is 4 bytes of a VLAN tag
24448 * including TPID, PCP, DEI, and VID fields in network byte
24451 uint64_t vlan_tag_tbl_addr;
24453 * This value indicates how many entries in vlan_tag_tbl are
24454 * valid. Each entry is 4 bytes.
24456 uint32_t num_vlan_tags;
24457 uint8_t unused_1[4];
24458 } __attribute__((packed));
24460 /* hwrm_cfa_l2_set_rx_mask_output (size:128b/16B) */
24461 struct hwrm_cfa_l2_set_rx_mask_output {
24462 /* The specific error status for the command. */
24463 uint16_t error_code;
24464 /* The HWRM command request type. */
24466 /* The sequence ID from the original command. */
24468 /* The length of the response data in number of bytes. */
24470 uint8_t unused_0[7];
24472 * This field is used in Output records to indicate that the output
24473 * is completely written to RAM. This field should be read as '1'
24474 * to indicate that the output has been completely written.
24475 * When writing a command completion or response to an internal processor,
24476 * the order of writes has to be such that this field is written last.
24479 } __attribute__((packed));
24481 /* hwrm_cfa_l2_set_rx_mask_cmd_err (size:64b/8B) */
24482 struct hwrm_cfa_l2_set_rx_mask_cmd_err {
24484 * command specific error codes that goes to
24485 * the cmd_err field in Common HWRM Error Response.
24488 /* Unknown error */
24489 #define HWRM_CFA_L2_SET_RX_MASK_CMD_ERR_CODE_UNKNOWN \
24491 /* Unable to complete operation due to conflict with Ntuple Filter */
24492 #define HWRM_CFA_L2_SET_RX_MASK_CMD_ERR_CODE_NTUPLE_FILTER_CONFLICT_ERR \
24494 #define HWRM_CFA_L2_SET_RX_MASK_CMD_ERR_CODE_LAST \
24495 HWRM_CFA_L2_SET_RX_MASK_CMD_ERR_CODE_NTUPLE_FILTER_CONFLICT_ERR
24496 uint8_t unused_0[7];
24497 } __attribute__((packed));
24499 /*******************************
24500 * hwrm_cfa_vlan_antispoof_cfg *
24501 *******************************/
24504 /* hwrm_cfa_vlan_antispoof_cfg_input (size:256b/32B) */
24505 struct hwrm_cfa_vlan_antispoof_cfg_input {
24506 /* The HWRM command request type. */
24509 * The completion ring to send the completion event on. This should
24510 * be the NQ ID returned from the `nq_alloc` HWRM command.
24512 uint16_t cmpl_ring;
24514 * The sequence ID is used by the driver for tracking multiple
24515 * commands. This ID is treated as opaque data by the firmware and
24516 * the value is returned in the `hwrm_resp_hdr` upon completion.
24520 * The target ID of the command:
24521 * * 0x0-0xFFF8 - The function ID
24522 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
24523 * * 0xFFFD - Reserved for user-space HWRM interface
24526 uint16_t target_id;
24528 * A physical address pointer pointing to a host buffer that the
24529 * command's response data will be written. This can be either a host
24530 * physical address (HPA) or a guest physical address (GPA) and must
24531 * point to a physically contiguous block of memory.
24533 uint64_t resp_addr;
24535 * Function ID of the function that is being configured.
24536 * Only valid for a VF FID configured by the PF.
24539 uint8_t unused_0[2];
24540 /* Number of VLAN entries in the vlan_tag_mask_tbl. */
24541 uint32_t num_vlan_entries;
24543 * The vlan_tag_mask_tbl_addr is the DMA address of the VLAN
24544 * antispoof table. Each table entry contains the 16-bit TPID
24545 * (0x8100 or 0x88a8 only), 16-bit VLAN ID, and a 16-bit mask,
24546 * all in network order to match hwrm_cfa_l2_set_rx_mask.
24547 * For an individual VLAN entry, the mask value should be 0xfff
24548 * for the 12-bit VLAN ID.
24550 uint64_t vlan_tag_mask_tbl_addr;
24551 } __attribute__((packed));
24553 /* hwrm_cfa_vlan_antispoof_cfg_output (size:128b/16B) */
24554 struct hwrm_cfa_vlan_antispoof_cfg_output {
24555 /* The specific error status for the command. */
24556 uint16_t error_code;
24557 /* The HWRM command request type. */
24559 /* The sequence ID from the original command. */
24561 /* The length of the response data in number of bytes. */
24563 uint8_t unused_0[7];
24565 * This field is used in Output records to indicate that the output
24566 * is completely written to RAM. This field should be read as '1'
24567 * to indicate that the output has been completely written.
24568 * When writing a command completion or response to an internal processor,
24569 * the order of writes has to be such that this field is written last.
24572 } __attribute__((packed));
24574 /********************************
24575 * hwrm_cfa_vlan_antispoof_qcfg *
24576 ********************************/
24579 /* hwrm_cfa_vlan_antispoof_qcfg_input (size:256b/32B) */
24580 struct hwrm_cfa_vlan_antispoof_qcfg_input {
24581 /* The HWRM command request type. */
24584 * The completion ring to send the completion event on. This should
24585 * be the NQ ID returned from the `nq_alloc` HWRM command.
24587 uint16_t cmpl_ring;
24589 * The sequence ID is used by the driver for tracking multiple
24590 * commands. This ID is treated as opaque data by the firmware and
24591 * the value is returned in the `hwrm_resp_hdr` upon completion.
24595 * The target ID of the command:
24596 * * 0x0-0xFFF8 - The function ID
24597 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
24598 * * 0xFFFD - Reserved for user-space HWRM interface
24601 uint16_t target_id;
24603 * A physical address pointer pointing to a host buffer that the
24604 * command's response data will be written. This can be either a host
24605 * physical address (HPA) or a guest physical address (GPA) and must
24606 * point to a physically contiguous block of memory.
24608 uint64_t resp_addr;
24610 * Function ID of the function that is being queried.
24611 * Only valid for a VF FID queried by the PF.
24614 uint8_t unused_0[2];
24616 * Maximum number of VLAN entries the firmware is allowed to DMA
24617 * to vlan_tag_mask_tbl.
24619 uint32_t max_vlan_entries;
24621 * The vlan_tag_mask_tbl_addr is the DMA address of the VLAN
24622 * antispoof table to which firmware will DMA to. Each table
24623 * entry will contain the 16-bit TPID (0x8100 or 0x88a8 only),
24624 * 16-bit VLAN ID, and a 16-bit mask, all in network order to
24625 * match hwrm_cfa_l2_set_rx_mask. For an individual VLAN entry,
24626 * the mask value should be 0xfff for the 12-bit VLAN ID.
24628 uint64_t vlan_tag_mask_tbl_addr;
24629 } __attribute__((packed));
24631 /* hwrm_cfa_vlan_antispoof_qcfg_output (size:128b/16B) */
24632 struct hwrm_cfa_vlan_antispoof_qcfg_output {
24633 /* The specific error status for the command. */
24634 uint16_t error_code;
24635 /* The HWRM command request type. */
24637 /* The sequence ID from the original command. */
24639 /* The length of the response data in number of bytes. */
24641 /* Number of valid entries DMAd by firmware to vlan_tag_mask_tbl. */
24642 uint32_t num_vlan_entries;
24643 uint8_t unused_0[3];
24645 * This field is used in Output records to indicate that the output
24646 * is completely written to RAM. This field should be read as '1'
24647 * to indicate that the output has been completely written.
24648 * When writing a command completion or response to an internal processor,
24649 * the order of writes has to be such that this field is written last.
24652 } __attribute__((packed));
24654 /********************************
24655 * hwrm_cfa_tunnel_filter_alloc *
24656 ********************************/
24659 /* hwrm_cfa_tunnel_filter_alloc_input (size:704b/88B) */
24660 struct hwrm_cfa_tunnel_filter_alloc_input {
24661 /* The HWRM command request type. */
24664 * The completion ring to send the completion event on. This should
24665 * be the NQ ID returned from the `nq_alloc` HWRM command.
24667 uint16_t cmpl_ring;
24669 * The sequence ID is used by the driver for tracking multiple
24670 * commands. This ID is treated as opaque data by the firmware and
24671 * the value is returned in the `hwrm_resp_hdr` upon completion.
24675 * The target ID of the command:
24676 * * 0x0-0xFFF8 - The function ID
24677 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
24678 * * 0xFFFD - Reserved for user-space HWRM interface
24681 uint16_t target_id;
24683 * A physical address pointer pointing to a host buffer that the
24684 * command's response data will be written. This can be either a host
24685 * physical address (HPA) or a guest physical address (GPA) and must
24686 * point to a physically contiguous block of memory.
24688 uint64_t resp_addr;
24690 /* Setting of this flag indicates the applicability to the loopback path. */
24691 #define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_FLAGS_LOOPBACK \
24695 * This bit must be '1' for the l2_filter_id field to be
24698 #define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_ENABLES_L2_FILTER_ID \
24701 * This bit must be '1' for the l2_addr field to be
24704 #define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_ENABLES_L2_ADDR \
24707 * This bit must be '1' for the l2_ivlan field to be
24710 #define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN \
24713 * This bit must be '1' for the l3_addr field to be
24716 #define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_ENABLES_L3_ADDR \
24719 * This bit must be '1' for the l3_addr_type field to be
24722 #define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_ENABLES_L3_ADDR_TYPE \
24725 * This bit must be '1' for the t_l3_addr_type field to be
24728 #define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_ENABLES_T_L3_ADDR_TYPE \
24731 * This bit must be '1' for the t_l3_addr field to be
24734 #define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_ENABLES_T_L3_ADDR \
24737 * This bit must be '1' for the tunnel_type field to be
24740 #define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_ENABLES_TUNNEL_TYPE \
24743 * This bit must be '1' for the vni field to be
24746 #define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_ENABLES_VNI \
24749 * This bit must be '1' for the dst_vnic_id field to be
24752 #define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_ENABLES_DST_VNIC_ID \
24755 * This bit must be '1' for the mirror_vnic_id field to be
24758 #define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_ENABLES_MIRROR_VNIC_ID \
24761 * This value identifies a set of CFA data structures used for an L2
24764 uint64_t l2_filter_id;
24766 * This value sets the match value for the inner L2
24768 * Destination MAC address for RX path.
24769 * Source MAC address for TX path.
24771 uint8_t l2_addr[6];
24773 * This value sets VLAN ID value for inner VLAN.
24774 * Only 12-bits of VLAN ID are used in setting the filter.
24778 * The value of inner destination IP address to be used in filtering.
24779 * For IPv4, first four bytes represent the IP address.
24781 uint32_t l3_addr[4];
24783 * The value of tunnel destination IP address to be used in filtering.
24784 * For IPv4, first four bytes represent the IP address.
24786 uint32_t t_l3_addr[4];
24788 * This value indicates the type of inner IP address.
24791 * All others are invalid.
24793 uint8_t l3_addr_type;
24795 * This value indicates the type of tunnel IP address.
24798 * All others are invalid.
24800 uint8_t t_l3_addr_type;
24802 uint8_t tunnel_type;
24804 #define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_TUNNEL_TYPE_NONTUNNEL \
24806 /* Virtual eXtensible Local Area Network (VXLAN) */
24807 #define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_TUNNEL_TYPE_VXLAN \
24809 /* Network Virtualization Generic Routing Encapsulation (NVGRE) */
24810 #define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_TUNNEL_TYPE_NVGRE \
24812 /* Generic Routing Encapsulation (GRE) inside Ethernet payload */
24813 #define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_TUNNEL_TYPE_L2GRE \
24816 #define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_TUNNEL_TYPE_IPIP \
24818 /* Generic Network Virtualization Encapsulation (Geneve) */
24819 #define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_TUNNEL_TYPE_GENEVE \
24821 /* Multi-Protocol Lable Switching (MPLS) */
24822 #define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_TUNNEL_TYPE_MPLS \
24824 /* Stateless Transport Tunnel (STT) */
24825 #define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_TUNNEL_TYPE_STT \
24827 /* Generic Routing Encapsulation (GRE) inside IP datagram payload */
24828 #define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_TUNNEL_TYPE_IPGRE \
24830 /* IPV4 over virtual eXtensible Local Area Network (IPV4oVXLAN) */
24831 #define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_TUNNEL_TYPE_VXLAN_V4 \
24833 /* Enhance Generic Routing Encapsulation (GRE version 1) inside IP datagram payload */
24834 #define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_TUNNEL_TYPE_IPGRE_V1 \
24836 /* Use fixed layer 2 ether type of 0xFFFF */
24837 #define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_TUNNEL_TYPE_L2_ETYPE \
24839 /* IPV6 over virtual eXtensible Local Area Network with GPE header (IPV6oVXLANGPE) */
24840 #define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_TUNNEL_TYPE_VXLAN_GPE_V6 \
24842 /* Any tunneled traffic */
24843 #define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_TUNNEL_TYPE_ANYTUNNEL \
24845 #define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_TUNNEL_TYPE_LAST \
24846 HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_TUNNEL_TYPE_ANYTUNNEL
24848 * tunnel_flags allows the user to indicate the tunnel tag detection
24849 * for the tunnel type specified in tunnel_type.
24851 uint8_t tunnel_flags;
24853 * If the tunnel_type is geneve, then this bit indicates if we
24854 * need to match the geneve OAM packet.
24855 * If the tunnel_type is nvgre or gre, then this bit indicates if
24856 * we need to detect checksum present bit in geneve header.
24857 * If the tunnel_type is mpls, then this bit indicates if we need
24858 * to match mpls packet with explicit IPV4/IPV6 null header.
24860 #define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_TUNNEL_FLAGS_TUN_FLAGS_OAM_CHECKSUM_EXPLHDR \
24863 * If the tunnel_type is geneve, then this bit indicates if we
24864 * need to detect the critical option bit set in the oam packet.
24865 * If the tunnel_type is nvgre or gre, then this bit indicates
24866 * if we need to match nvgre packets with key present bit set in
24868 * If the tunnel_type is mpls, then this bit indicates if we
24869 * need to match mpls packet with S bit from inner/second label.
24871 #define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_TUNNEL_FLAGS_TUN_FLAGS_CRITICAL_OPT_S1 \
24874 * If the tunnel_type is geneve, then this bit indicates if we
24875 * need to match geneve packet with extended header bit set in
24877 * If the tunnel_type is nvgre or gre, then this bit indicates
24878 * if we need to match nvgre packets with sequence number
24879 * present bit set in gre header.
24880 * If the tunnel_type is mpls, then this bit indicates if we
24881 * need to match mpls packet with S bit from out/first label.
24883 #define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_TUNNEL_FLAGS_TUN_FLAGS_EXTHDR_SEQNUM_S0 \
24886 * Virtual Network Identifier (VNI). Only valid with
24887 * tunnel_types VXLAN, NVGRE, and Geneve.
24888 * Only lower 24-bits of VNI field are used
24889 * in setting up the filter.
24892 /* Logical VNIC ID of the destination VNIC. */
24893 uint32_t dst_vnic_id;
24895 * Logical VNIC ID of the VNIC where traffic is
24898 uint32_t mirror_vnic_id;
24899 } __attribute__((packed));
24901 /* hwrm_cfa_tunnel_filter_alloc_output (size:192b/24B) */
24902 struct hwrm_cfa_tunnel_filter_alloc_output {
24903 /* The specific error status for the command. */
24904 uint16_t error_code;
24905 /* The HWRM command request type. */
24907 /* The sequence ID from the original command. */
24909 /* The length of the response data in number of bytes. */
24911 /* This value is an opaque id into CFA data structures. */
24912 uint64_t tunnel_filter_id;
24914 * The flow id value in bit 0-29 is the actual ID of the flow
24915 * associated with this filter and it shall be used to match
24916 * and associate the flow identifier returned in completion
24917 * records. A value of 0xFFFFFFFF in the 32-bit flow_id field
24918 * shall indicate no valid flow id.
24921 /* Indicate the flow id value. */
24922 #define HWRM_CFA_TUNNEL_FILTER_ALLOC_OUTPUT_FLOW_ID_VALUE_MASK \
24923 UINT32_C(0x3fffffff)
24924 #define HWRM_CFA_TUNNEL_FILTER_ALLOC_OUTPUT_FLOW_ID_VALUE_SFT 0
24925 /* Indicate type of the flow. */
24926 #define HWRM_CFA_TUNNEL_FILTER_ALLOC_OUTPUT_FLOW_ID_TYPE \
24927 UINT32_C(0x40000000)
24929 * If this bit set to 0, then it indicates that the flow is
24932 #define HWRM_CFA_TUNNEL_FILTER_ALLOC_OUTPUT_FLOW_ID_TYPE_INT \
24933 (UINT32_C(0x0) << 30)
24935 * If this bit is set to 1, then it indicates that the flow is
24938 #define HWRM_CFA_TUNNEL_FILTER_ALLOC_OUTPUT_FLOW_ID_TYPE_EXT \
24939 (UINT32_C(0x1) << 30)
24940 #define HWRM_CFA_TUNNEL_FILTER_ALLOC_OUTPUT_FLOW_ID_TYPE_LAST \
24941 HWRM_CFA_TUNNEL_FILTER_ALLOC_OUTPUT_FLOW_ID_TYPE_EXT
24942 /* Indicate the flow direction. */
24943 #define HWRM_CFA_TUNNEL_FILTER_ALLOC_OUTPUT_FLOW_ID_DIR \
24944 UINT32_C(0x80000000)
24945 /* If this bit set to 0, then it indicates rx flow. */
24946 #define HWRM_CFA_TUNNEL_FILTER_ALLOC_OUTPUT_FLOW_ID_DIR_RX \
24947 (UINT32_C(0x0) << 31)
24948 /* If this bit is set to 1, then it indicates that tx flow. */
24949 #define HWRM_CFA_TUNNEL_FILTER_ALLOC_OUTPUT_FLOW_ID_DIR_TX \
24950 (UINT32_C(0x1) << 31)
24951 #define HWRM_CFA_TUNNEL_FILTER_ALLOC_OUTPUT_FLOW_ID_DIR_LAST \
24952 HWRM_CFA_TUNNEL_FILTER_ALLOC_OUTPUT_FLOW_ID_DIR_TX
24953 uint8_t unused_0[3];
24955 * This field is used in Output records to indicate that the output
24956 * is completely written to RAM. This field should be read as '1'
24957 * to indicate that the output has been completely written.
24958 * When writing a command completion or response to an internal processor,
24959 * the order of writes has to be such that this field is written last.
24962 } __attribute__((packed));
24964 /*******************************
24965 * hwrm_cfa_tunnel_filter_free *
24966 *******************************/
24969 /* hwrm_cfa_tunnel_filter_free_input (size:192b/24B) */
24970 struct hwrm_cfa_tunnel_filter_free_input {
24971 /* The HWRM command request type. */
24974 * The completion ring to send the completion event on. This should
24975 * be the NQ ID returned from the `nq_alloc` HWRM command.
24977 uint16_t cmpl_ring;
24979 * The sequence ID is used by the driver for tracking multiple
24980 * commands. This ID is treated as opaque data by the firmware and
24981 * the value is returned in the `hwrm_resp_hdr` upon completion.
24985 * The target ID of the command:
24986 * * 0x0-0xFFF8 - The function ID
24987 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
24988 * * 0xFFFD - Reserved for user-space HWRM interface
24991 uint16_t target_id;
24993 * A physical address pointer pointing to a host buffer that the
24994 * command's response data will be written. This can be either a host
24995 * physical address (HPA) or a guest physical address (GPA) and must
24996 * point to a physically contiguous block of memory.
24998 uint64_t resp_addr;
24999 /* This value is an opaque id into CFA data structures. */
25000 uint64_t tunnel_filter_id;
25001 } __attribute__((packed));
25003 /* hwrm_cfa_tunnel_filter_free_output (size:128b/16B) */
25004 struct hwrm_cfa_tunnel_filter_free_output {
25005 /* The specific error status for the command. */
25006 uint16_t error_code;
25007 /* The HWRM command request type. */
25009 /* The sequence ID from the original command. */
25011 /* The length of the response data in number of bytes. */
25013 uint8_t unused_0[7];
25015 * This field is used in Output records to indicate that the output
25016 * is completely written to RAM. This field should be read as '1'
25017 * to indicate that the output has been completely written.
25018 * When writing a command completion or response to an internal processor,
25019 * the order of writes has to be such that this field is written last.
25022 } __attribute__((packed));
25024 /***************************************
25025 * hwrm_cfa_redirect_tunnel_type_alloc *
25026 ***************************************/
25029 /* hwrm_cfa_redirect_tunnel_type_alloc_input (size:192b/24B) */
25030 struct hwrm_cfa_redirect_tunnel_type_alloc_input {
25031 /* The HWRM command request type. */
25034 * The completion ring to send the completion event on. This should
25035 * be the NQ ID returned from the `nq_alloc` HWRM command.
25037 uint16_t cmpl_ring;
25039 * The sequence ID is used by the driver for tracking multiple
25040 * commands. This ID is treated as opaque data by the firmware and
25041 * the value is returned in the `hwrm_resp_hdr` upon completion.
25045 * The target ID of the command:
25046 * * 0x0-0xFFF8 - The function ID
25047 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
25048 * * 0xFFFD - Reserved for user-space HWRM interface
25051 uint16_t target_id;
25053 * A physical address pointer pointing to a host buffer that the
25054 * command's response data will be written. This can be either a host
25055 * physical address (HPA) or a guest physical address (GPA) and must
25056 * point to a physically contiguous block of memory.
25058 uint64_t resp_addr;
25059 /* The destination function id, to whom the traffic is redirected. */
25062 uint8_t tunnel_type;
25064 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_ALLOC_INPUT_TUNNEL_TYPE_NONTUNNEL \
25066 /* Virtual eXtensible Local Area Network (VXLAN) */
25067 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_ALLOC_INPUT_TUNNEL_TYPE_VXLAN \
25069 /* Network Virtualization Generic Routing Encapsulation (NVGRE) */
25070 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_ALLOC_INPUT_TUNNEL_TYPE_NVGRE \
25072 /* Generic Routing Encapsulation (GRE) inside Ethernet payload */
25073 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_ALLOC_INPUT_TUNNEL_TYPE_L2GRE \
25076 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_ALLOC_INPUT_TUNNEL_TYPE_IPIP \
25078 /* Generic Network Virtualization Encapsulation (Geneve) */
25079 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_ALLOC_INPUT_TUNNEL_TYPE_GENEVE \
25081 /* Multi-Protocol Lable Switching (MPLS) */
25082 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_ALLOC_INPUT_TUNNEL_TYPE_MPLS \
25084 /* Stateless Transport Tunnel (STT) */
25085 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_ALLOC_INPUT_TUNNEL_TYPE_STT \
25087 /* Generic Routing Encapsulation (GRE) inside IP datagram payload */
25088 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_ALLOC_INPUT_TUNNEL_TYPE_IPGRE \
25090 /* IPV4 over virtual eXtensible Local Area Network (IPV4oVXLAN) */
25091 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_ALLOC_INPUT_TUNNEL_TYPE_VXLAN_V4 \
25093 /* Enhance Generic Routing Encapsulation (GRE version 1) inside IP datagram payload */
25094 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_ALLOC_INPUT_TUNNEL_TYPE_IPGRE_V1 \
25096 /* Use fixed layer 2 ether type of 0xFFFF */
25097 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_ALLOC_INPUT_TUNNEL_TYPE_L2_ETYPE \
25099 /* IPV6 over virtual eXtensible Local Area Network with GPE header (IPV6oVXLANGPE) */
25100 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_ALLOC_INPUT_TUNNEL_TYPE_VXLAN_GPE_V6 \
25102 /* Any tunneled traffic */
25103 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_ALLOC_INPUT_TUNNEL_TYPE_ANYTUNNEL \
25105 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_ALLOC_INPUT_TUNNEL_TYPE_LAST \
25106 HWRM_CFA_REDIRECT_TUNNEL_TYPE_ALLOC_INPUT_TUNNEL_TYPE_ANYTUNNEL
25107 /* Tunnel alloc flags. */
25109 /* Setting of this flag indicates modify existing redirect tunnel to new destination function ID. */
25110 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_ALLOC_INPUT_FLAGS_MODIFY_DST \
25112 uint8_t unused_0[4];
25113 } __attribute__((packed));
25115 /* hwrm_cfa_redirect_tunnel_type_alloc_output (size:128b/16B) */
25116 struct hwrm_cfa_redirect_tunnel_type_alloc_output {
25117 /* The specific error status for the command. */
25118 uint16_t error_code;
25119 /* The HWRM command request type. */
25121 /* The sequence ID from the original command. */
25123 /* The length of the response data in number of bytes. */
25125 uint8_t unused_0[7];
25127 * This field is used in Output records to indicate that the output
25128 * is completely written to RAM. This field should be read as '1'
25129 * to indicate that the output has been completely written.
25130 * When writing a command completion or response to an internal processor,
25131 * the order of writes has to be such that this field is written last.
25134 } __attribute__((packed));
25136 /**************************************
25137 * hwrm_cfa_redirect_tunnel_type_free *
25138 **************************************/
25141 /* hwrm_cfa_redirect_tunnel_type_free_input (size:192b/24B) */
25142 struct hwrm_cfa_redirect_tunnel_type_free_input {
25143 /* The HWRM command request type. */
25146 * The completion ring to send the completion event on. This should
25147 * be the NQ ID returned from the `nq_alloc` HWRM command.
25149 uint16_t cmpl_ring;
25151 * The sequence ID is used by the driver for tracking multiple
25152 * commands. This ID is treated as opaque data by the firmware and
25153 * the value is returned in the `hwrm_resp_hdr` upon completion.
25157 * The target ID of the command:
25158 * * 0x0-0xFFF8 - The function ID
25159 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
25160 * * 0xFFFD - Reserved for user-space HWRM interface
25163 uint16_t target_id;
25165 * A physical address pointer pointing to a host buffer that the
25166 * command's response data will be written. This can be either a host
25167 * physical address (HPA) or a guest physical address (GPA) and must
25168 * point to a physically contiguous block of memory.
25170 uint64_t resp_addr;
25171 /* The destination function id, to whom the traffic is redirected. */
25174 uint8_t tunnel_type;
25176 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_FREE_INPUT_TUNNEL_TYPE_NONTUNNEL \
25178 /* Virtual eXtensible Local Area Network (VXLAN) */
25179 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_FREE_INPUT_TUNNEL_TYPE_VXLAN \
25181 /* Network Virtualization Generic Routing Encapsulation (NVGRE) */
25182 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_FREE_INPUT_TUNNEL_TYPE_NVGRE \
25184 /* Generic Routing Encapsulation (GRE) inside Ethernet payload */
25185 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_FREE_INPUT_TUNNEL_TYPE_L2GRE \
25188 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_FREE_INPUT_TUNNEL_TYPE_IPIP \
25190 /* Generic Network Virtualization Encapsulation (Geneve) */
25191 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_FREE_INPUT_TUNNEL_TYPE_GENEVE \
25193 /* Multi-Protocol Lable Switching (MPLS) */
25194 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_FREE_INPUT_TUNNEL_TYPE_MPLS \
25196 /* Stateless Transport Tunnel (STT) */
25197 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_FREE_INPUT_TUNNEL_TYPE_STT \
25199 /* Generic Routing Encapsulation (GRE) inside IP datagram payload */
25200 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_FREE_INPUT_TUNNEL_TYPE_IPGRE \
25202 /* IPV4 over virtual eXtensible Local Area Network (IPV4oVXLAN) */
25203 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_FREE_INPUT_TUNNEL_TYPE_VXLAN_V4 \
25205 /* Enhance Generic Routing Encapsulation (GRE version 1) inside IP datagram payload */
25206 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_FREE_INPUT_TUNNEL_TYPE_IPGRE_V1 \
25208 /* Use fixed layer 2 ether type of 0xFFFF */
25209 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_FREE_INPUT_TUNNEL_TYPE_L2_ETYPE \
25211 /* IPV6 over virtual eXtensible Local Area Network with GPE header (IPV6oVXLANGPE) */
25212 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_FREE_INPUT_TUNNEL_TYPE_VXLAN_GPE_V6 \
25214 /* Any tunneled traffic */
25215 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_FREE_INPUT_TUNNEL_TYPE_ANYTUNNEL \
25217 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_FREE_INPUT_TUNNEL_TYPE_LAST \
25218 HWRM_CFA_REDIRECT_TUNNEL_TYPE_FREE_INPUT_TUNNEL_TYPE_ANYTUNNEL
25219 uint8_t unused_0[5];
25220 } __attribute__((packed));
25222 /* hwrm_cfa_redirect_tunnel_type_free_output (size:128b/16B) */
25223 struct hwrm_cfa_redirect_tunnel_type_free_output {
25224 /* The specific error status for the command. */
25225 uint16_t error_code;
25226 /* The HWRM command request type. */
25228 /* The sequence ID from the original command. */
25230 /* The length of the response data in number of bytes. */
25232 uint8_t unused_0[7];
25234 * This field is used in Output records to indicate that the output
25235 * is completely written to RAM. This field should be read as '1'
25236 * to indicate that the output has been completely written.
25237 * When writing a command completion or response to an internal processor,
25238 * the order of writes has to be such that this field is written last.
25241 } __attribute__((packed));
25243 /**************************************
25244 * hwrm_cfa_redirect_tunnel_type_info *
25245 **************************************/
25248 /* hwrm_cfa_redirect_tunnel_type_info_input (size:192b/24B) */
25249 struct hwrm_cfa_redirect_tunnel_type_info_input {
25250 /* The HWRM command request type. */
25253 * The completion ring to send the completion event on. This should
25254 * be the NQ ID returned from the `nq_alloc` HWRM command.
25256 uint16_t cmpl_ring;
25258 * The sequence ID is used by the driver for tracking multiple
25259 * commands. This ID is treated as opaque data by the firmware and
25260 * the value is returned in the `hwrm_resp_hdr` upon completion.
25264 * The target ID of the command:
25265 * * 0x0-0xFFF8 - The function ID
25266 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
25267 * * 0xFFFD - Reserved for user-space HWRM interface
25270 uint16_t target_id;
25272 * A physical address pointer pointing to a host buffer that the
25273 * command's response data will be written. This can be either a host
25274 * physical address (HPA) or a guest physical address (GPA) and must
25275 * point to a physically contiguous block of memory.
25277 uint64_t resp_addr;
25278 /* The source function id. */
25281 uint8_t tunnel_type;
25283 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_INFO_INPUT_TUNNEL_TYPE_NONTUNNEL \
25285 /* Virtual eXtensible Local Area Network (VXLAN) */
25286 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_INFO_INPUT_TUNNEL_TYPE_VXLAN \
25288 /* Network Virtualization Generic Routing Encapsulation (NVGRE) */
25289 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_INFO_INPUT_TUNNEL_TYPE_NVGRE \
25291 /* Generic Routing Encapsulation (GRE) inside Ethernet payload */
25292 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_INFO_INPUT_TUNNEL_TYPE_L2GRE \
25295 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_INFO_INPUT_TUNNEL_TYPE_IPIP \
25297 /* Generic Network Virtualization Encapsulation (Geneve) */
25298 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_INFO_INPUT_TUNNEL_TYPE_GENEVE \
25300 /* Multi-Protocol Lable Switching (MPLS) */
25301 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_INFO_INPUT_TUNNEL_TYPE_MPLS \
25303 /* Stateless Transport Tunnel (STT) */
25304 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_INFO_INPUT_TUNNEL_TYPE_STT \
25306 /* Generic Routing Encapsulation (GRE) inside IP datagram payload */
25307 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_INFO_INPUT_TUNNEL_TYPE_IPGRE \
25309 /* IPV4 over virtual eXtensible Local Area Network (IPV4oVXLAN) */
25310 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_INFO_INPUT_TUNNEL_TYPE_VXLAN_V4 \
25312 /* Enhance Generic Routing Encapsulation (GRE version 1) inside IP datagram payload */
25313 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_INFO_INPUT_TUNNEL_TYPE_IPGRE_V1 \
25315 /* Use fixed layer 2 ether type of 0xFFFF */
25316 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_INFO_INPUT_TUNNEL_TYPE_L2_ETYPE \
25318 /* IPV6 over virtual eXtensible Local Area Network with GPE header (IPV6oVXLANGPE) */
25319 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_INFO_INPUT_TUNNEL_TYPE_VXLAN_GPE_V6 \
25321 /* Any tunneled traffic */
25322 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_INFO_INPUT_TUNNEL_TYPE_ANYTUNNEL \
25324 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_INFO_INPUT_TUNNEL_TYPE_LAST \
25325 HWRM_CFA_REDIRECT_TUNNEL_TYPE_INFO_INPUT_TUNNEL_TYPE_ANYTUNNEL
25326 uint8_t unused_0[5];
25327 } __attribute__((packed));
25329 /* hwrm_cfa_redirect_tunnel_type_info_output (size:128b/16B) */
25330 struct hwrm_cfa_redirect_tunnel_type_info_output {
25331 /* The specific error status for the command. */
25332 uint16_t error_code;
25333 /* The HWRM command request type. */
25335 /* The sequence ID from the original command. */
25337 /* The length of the response data in number of bytes. */
25339 /* The destination function id, to whom the traffic is redirected. */
25341 uint8_t unused_0[5];
25343 * This field is used in Output records to indicate that the output
25344 * is completely written to RAM. This field should be read as '1'
25345 * to indicate that the output has been completely written.
25346 * When writing a command completion or response to an internal processor,
25347 * the order of writes has to be such that this field is written last.
25350 } __attribute__((packed));
25352 /* hwrm_vxlan_ipv4_hdr (size:128b/16B) */
25353 struct hwrm_vxlan_ipv4_hdr {
25354 /* IPv4 version and header length. */
25356 /* IPv4 header length */
25357 #define HWRM_VXLAN_IPV4_HDR_VER_HLEN_HEADER_LENGTH_MASK UINT32_C(0xf)
25358 #define HWRM_VXLAN_IPV4_HDR_VER_HLEN_HEADER_LENGTH_SFT 0
25360 #define HWRM_VXLAN_IPV4_HDR_VER_HLEN_VERSION_MASK UINT32_C(0xf0)
25361 #define HWRM_VXLAN_IPV4_HDR_VER_HLEN_VERSION_SFT 4
25362 /* IPv4 type of service. */
25364 /* IPv4 identification. */
25366 /* IPv4 flags and offset. */
25367 uint16_t flags_frag_offset;
25370 /* IPv4 protocol. */
25372 /* IPv4 source address. */
25373 uint32_t src_ip_addr;
25374 /* IPv4 destination address. */
25375 uint32_t dest_ip_addr;
25376 } __attribute__((packed));
25378 /* hwrm_vxlan_ipv6_hdr (size:320b/40B) */
25379 struct hwrm_vxlan_ipv6_hdr {
25380 /* IPv6 version, traffic class and flow label. */
25381 uint32_t ver_tc_flow_label;
25382 /* IPv6 version shift */
25383 #define HWRM_VXLAN_IPV6_HDR_VER_TC_FLOW_LABEL_VER_SFT \
25385 /* IPv6 version mask */
25386 #define HWRM_VXLAN_IPV6_HDR_VER_TC_FLOW_LABEL_VER_MASK \
25387 UINT32_C(0xf0000000)
25388 /* IPv6 TC shift */
25389 #define HWRM_VXLAN_IPV6_HDR_VER_TC_FLOW_LABEL_TC_SFT \
25392 #define HWRM_VXLAN_IPV6_HDR_VER_TC_FLOW_LABEL_TC_MASK \
25393 UINT32_C(0xff00000)
25394 /* IPv6 flow label shift */
25395 #define HWRM_VXLAN_IPV6_HDR_VER_TC_FLOW_LABEL_FLOW_LABEL_SFT \
25397 /* IPv6 flow label mask */
25398 #define HWRM_VXLAN_IPV6_HDR_VER_TC_FLOW_LABEL_FLOW_LABEL_MASK \
25400 #define HWRM_VXLAN_IPV6_HDR_VER_TC_FLOW_LABEL_LAST \
25401 HWRM_VXLAN_IPV6_HDR_VER_TC_FLOW_LABEL_FLOW_LABEL_MASK
25402 /* IPv6 payload length. */
25403 uint16_t payload_len;
25404 /* IPv6 next header. */
25408 /* IPv6 source address. */
25409 uint32_t src_ip_addr[4];
25410 /* IPv6 destination address. */
25411 uint32_t dest_ip_addr[4];
25412 } __attribute__((packed));
25414 /* hwrm_cfa_encap_data_vxlan (size:640b/80B) */
25415 struct hwrm_cfa_encap_data_vxlan {
25416 /* Source MAC address. */
25417 uint8_t src_mac_addr[6];
25420 /* Destination MAC address. */
25421 uint8_t dst_mac_addr[6];
25422 /* Number of VLAN tags. */
25423 uint8_t num_vlan_tags;
25426 /* Outer VLAN TPID. */
25427 uint16_t ovlan_tpid;
25428 /* Outer VLAN TCI. */
25429 uint16_t ovlan_tci;
25430 /* Inner VLAN TPID. */
25431 uint16_t ivlan_tpid;
25432 /* Inner VLAN TCI. */
25433 uint16_t ivlan_tci;
25434 /* L3 header fields. */
25436 /* IP version mask. */
25437 #define HWRM_CFA_ENCAP_DATA_VXLAN_L3_VER_MASK UINT32_C(0xf)
25438 /* IP version 4. */
25439 #define HWRM_CFA_ENCAP_DATA_VXLAN_L3_VER_IPV4 UINT32_C(0x4)
25440 /* IP version 6. */
25441 #define HWRM_CFA_ENCAP_DATA_VXLAN_L3_VER_IPV6 UINT32_C(0x6)
25442 #define HWRM_CFA_ENCAP_DATA_VXLAN_L3_LAST \
25443 HWRM_CFA_ENCAP_DATA_VXLAN_L3_VER_IPV6
25444 /* UDP source port. */
25446 /* UDP destination port. */
25448 /* VXLAN Network Identifier. */
25450 /* 3 bytes VXLAN header reserve fields from 1st dword of the VXLAN header. */
25451 uint8_t hdr_rsvd0[3];
25452 /* 1 byte VXLAN header reserve field from 2nd dword of the VXLAN header. */
25454 /* VXLAN header flags field. */
25457 } __attribute__((packed));
25459 /*******************************
25460 * hwrm_cfa_encap_record_alloc *
25461 *******************************/
25464 /* hwrm_cfa_encap_record_alloc_input (size:832b/104B) */
25465 struct hwrm_cfa_encap_record_alloc_input {
25466 /* The HWRM command request type. */
25469 * The completion ring to send the completion event on. This should
25470 * be the NQ ID returned from the `nq_alloc` HWRM command.
25472 uint16_t cmpl_ring;
25474 * The sequence ID is used by the driver for tracking multiple
25475 * commands. This ID is treated as opaque data by the firmware and
25476 * the value is returned in the `hwrm_resp_hdr` upon completion.
25480 * The target ID of the command:
25481 * * 0x0-0xFFF8 - The function ID
25482 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
25483 * * 0xFFFD - Reserved for user-space HWRM interface
25486 uint16_t target_id;
25488 * A physical address pointer pointing to a host buffer that the
25489 * command's response data will be written. This can be either a host
25490 * physical address (HPA) or a guest physical address (GPA) and must
25491 * point to a physically contiguous block of memory.
25493 uint64_t resp_addr;
25495 /* Setting of this flag indicates the applicability to the loopback path. */
25496 #define HWRM_CFA_ENCAP_RECORD_ALLOC_INPUT_FLAGS_LOOPBACK \
25499 * Setting of this flag indicates this encap record is external encap record.
25500 * Resetting of this flag indicates this flag is internal encap record and
25501 * this is the default setting.
25503 #define HWRM_CFA_ENCAP_RECORD_ALLOC_INPUT_FLAGS_EXTERNAL \
25505 /* Encapsulation Type. */
25506 uint8_t encap_type;
25507 /* Virtual eXtensible Local Area Network (VXLAN) */
25508 #define HWRM_CFA_ENCAP_RECORD_ALLOC_INPUT_ENCAP_TYPE_VXLAN \
25510 /* Network Virtualization Generic Routing Encapsulation (NVGRE) */
25511 #define HWRM_CFA_ENCAP_RECORD_ALLOC_INPUT_ENCAP_TYPE_NVGRE \
25513 /* Generic Routing Encapsulation (GRE) after inside Ethernet payload */
25514 #define HWRM_CFA_ENCAP_RECORD_ALLOC_INPUT_ENCAP_TYPE_L2GRE \
25517 #define HWRM_CFA_ENCAP_RECORD_ALLOC_INPUT_ENCAP_TYPE_IPIP \
25519 /* Generic Network Virtualization Encapsulation (Geneve) */
25520 #define HWRM_CFA_ENCAP_RECORD_ALLOC_INPUT_ENCAP_TYPE_GENEVE \
25522 /* Multi-Protocol Lable Switching (MPLS) */
25523 #define HWRM_CFA_ENCAP_RECORD_ALLOC_INPUT_ENCAP_TYPE_MPLS \
25526 #define HWRM_CFA_ENCAP_RECORD_ALLOC_INPUT_ENCAP_TYPE_VLAN \
25528 /* Generic Routing Encapsulation (GRE) inside IP datagram payload */
25529 #define HWRM_CFA_ENCAP_RECORD_ALLOC_INPUT_ENCAP_TYPE_IPGRE \
25531 /* IPV4 over virtual eXtensible Local Area Network (IPV4oVXLAN) */
25532 #define HWRM_CFA_ENCAP_RECORD_ALLOC_INPUT_ENCAP_TYPE_VXLAN_V4 \
25534 /* Enhance Generic Routing Encapsulation (GRE version 1) inside IP datagram payload */
25535 #define HWRM_CFA_ENCAP_RECORD_ALLOC_INPUT_ENCAP_TYPE_IPGRE_V1 \
25537 /* Use fixed layer 2 ether type of 0xFFFF */
25538 #define HWRM_CFA_ENCAP_RECORD_ALLOC_INPUT_ENCAP_TYPE_L2_ETYPE \
25540 /* IPV6 over virtual eXtensible Local Area Network with GPE header (IPV6oVXLANGPE) */
25541 #define HWRM_CFA_ENCAP_RECORD_ALLOC_INPUT_ENCAP_TYPE_VXLAN_GPE_V6 \
25543 #define HWRM_CFA_ENCAP_RECORD_ALLOC_INPUT_ENCAP_TYPE_LAST \
25544 HWRM_CFA_ENCAP_RECORD_ALLOC_INPUT_ENCAP_TYPE_VXLAN_GPE_V6
25545 uint8_t unused_0[3];
25546 /* This value is encap data used for the given encap type. */
25547 uint32_t encap_data[20];
25548 } __attribute__((packed));
25550 /* hwrm_cfa_encap_record_alloc_output (size:128b/16B) */
25551 struct hwrm_cfa_encap_record_alloc_output {
25552 /* The specific error status for the command. */
25553 uint16_t error_code;
25554 /* The HWRM command request type. */
25556 /* The sequence ID from the original command. */
25558 /* The length of the response data in number of bytes. */
25560 /* This value is an opaque id into CFA data structures. */
25561 uint32_t encap_record_id;
25562 uint8_t unused_0[3];
25564 * This field is used in Output records to indicate that the output
25565 * is completely written to RAM. This field should be read as '1'
25566 * to indicate that the output has been completely written.
25567 * When writing a command completion or response to an internal processor,
25568 * the order of writes has to be such that this field is written last.
25571 } __attribute__((packed));
25573 /******************************
25574 * hwrm_cfa_encap_record_free *
25575 ******************************/
25578 /* hwrm_cfa_encap_record_free_input (size:192b/24B) */
25579 struct hwrm_cfa_encap_record_free_input {
25580 /* The HWRM command request type. */
25583 * The completion ring to send the completion event on. This should
25584 * be the NQ ID returned from the `nq_alloc` HWRM command.
25586 uint16_t cmpl_ring;
25588 * The sequence ID is used by the driver for tracking multiple
25589 * commands. This ID is treated as opaque data by the firmware and
25590 * the value is returned in the `hwrm_resp_hdr` upon completion.
25594 * The target ID of the command:
25595 * * 0x0-0xFFF8 - The function ID
25596 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
25597 * * 0xFFFD - Reserved for user-space HWRM interface
25600 uint16_t target_id;
25602 * A physical address pointer pointing to a host buffer that the
25603 * command's response data will be written. This can be either a host
25604 * physical address (HPA) or a guest physical address (GPA) and must
25605 * point to a physically contiguous block of memory.
25607 uint64_t resp_addr;
25608 /* This value is an opaque id into CFA data structures. */
25609 uint32_t encap_record_id;
25610 uint8_t unused_0[4];
25611 } __attribute__((packed));
25613 /* hwrm_cfa_encap_record_free_output (size:128b/16B) */
25614 struct hwrm_cfa_encap_record_free_output {
25615 /* The specific error status for the command. */
25616 uint16_t error_code;
25617 /* The HWRM command request type. */
25619 /* The sequence ID from the original command. */
25621 /* The length of the response data in number of bytes. */
25623 uint8_t unused_0[7];
25625 * This field is used in Output records to indicate that the output
25626 * is completely written to RAM. This field should be read as '1'
25627 * to indicate that the output has been completely written.
25628 * When writing a command completion or response to an internal processor,
25629 * the order of writes has to be such that this field is written last.
25632 } __attribute__((packed));
25634 /********************************
25635 * hwrm_cfa_ntuple_filter_alloc *
25636 ********************************/
25639 /* hwrm_cfa_ntuple_filter_alloc_input (size:1088b/136B) */
25640 struct hwrm_cfa_ntuple_filter_alloc_input {
25641 /* The HWRM command request type. */
25644 * The completion ring to send the completion event on. This should
25645 * be the NQ ID returned from the `nq_alloc` HWRM command.
25647 uint16_t cmpl_ring;
25649 * The sequence ID is used by the driver for tracking multiple
25650 * commands. This ID is treated as opaque data by the firmware and
25651 * the value is returned in the `hwrm_resp_hdr` upon completion.
25655 * The target ID of the command:
25656 * * 0x0-0xFFF8 - The function ID
25657 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
25658 * * 0xFFFD - Reserved for user-space HWRM interface
25661 uint16_t target_id;
25663 * A physical address pointer pointing to a host buffer that the
25664 * command's response data will be written. This can be either a host
25665 * physical address (HPA) or a guest physical address (GPA) and must
25666 * point to a physically contiguous block of memory.
25668 uint64_t resp_addr;
25670 /* Setting of this flag indicates the applicability to the loopback path. */
25671 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_FLAGS_LOOPBACK \
25674 * Setting of this flag indicates drop action. If this flag is not set,
25675 * then it should be considered accept action.
25677 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_FLAGS_DROP \
25680 * Setting of this flag indicates that a meter is expected to be attached
25681 * to this flow. This hint can be used when choosing the action record
25682 * format required for the flow.
25684 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_FLAGS_METER \
25687 * Setting of this flag indicates that the dest_id field contains function ID.
25688 * If this is not set it indicates dest_id is VNIC or VPORT.
25690 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_FLAGS_DEST_FID \
25694 * This bit must be '1' for the l2_filter_id field to be
25697 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_L2_FILTER_ID \
25700 * This bit must be '1' for the ethertype field to be
25703 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_ETHERTYPE \
25706 * This bit must be '1' for the tunnel_type field to be
25709 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_TUNNEL_TYPE \
25712 * This bit must be '1' for the src_macaddr field to be
25715 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_SRC_MACADDR \
25718 * This bit must be '1' for the ipaddr_type field to be
25721 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_IPADDR_TYPE \
25724 * This bit must be '1' for the src_ipaddr field to be
25727 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_SRC_IPADDR \
25730 * This bit must be '1' for the src_ipaddr_mask field to be
25733 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_SRC_IPADDR_MASK \
25736 * This bit must be '1' for the dst_ipaddr field to be
25739 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_IPADDR \
25742 * This bit must be '1' for the dst_ipaddr_mask field to be
25745 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_IPADDR_MASK \
25748 * This bit must be '1' for the ip_protocol field to be
25751 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_IP_PROTOCOL \
25754 * This bit must be '1' for the src_port field to be
25757 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_SRC_PORT \
25760 * This bit must be '1' for the src_port_mask field to be
25763 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_SRC_PORT_MASK \
25766 * This bit must be '1' for the dst_port field to be
25769 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_PORT \
25772 * This bit must be '1' for the dst_port_mask field to be
25775 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_PORT_MASK \
25778 * This bit must be '1' for the pri_hint field to be
25781 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_PRI_HINT \
25784 * This bit must be '1' for the ntuple_filter_id field to be
25787 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_NTUPLE_FILTER_ID \
25790 * This bit must be '1' for the dst_id field to be
25793 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_ID \
25796 * This bit must be '1' for the mirror_vnic_id field to be
25799 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_MIRROR_VNIC_ID \
25802 * This bit must be '1' for the dst_macaddr field to be
25805 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_MACADDR \
25808 * This bit must be '1' for the rfs_ring_tbl_idx field to be
25811 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_RFS_RING_TBL_IDX \
25814 * This value identifies a set of CFA data structures used for an L2
25817 uint64_t l2_filter_id;
25819 * This value indicates the source MAC address in
25820 * the Ethernet header.
25822 uint8_t src_macaddr[6];
25823 /* This value indicates the ethertype in the Ethernet header. */
25824 uint16_t ethertype;
25826 * This value indicates the type of IP address.
25829 * All others are invalid.
25831 uint8_t ip_addr_type;
25833 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_IP_ADDR_TYPE_UNKNOWN \
25836 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_IP_ADDR_TYPE_IPV4 \
25839 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_IP_ADDR_TYPE_IPV6 \
25841 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_IP_ADDR_TYPE_LAST \
25842 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_IP_ADDR_TYPE_IPV6
25844 * The value of protocol filed in IP header.
25845 * Applies to UDP and TCP traffic.
25849 uint8_t ip_protocol;
25851 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_IP_PROTOCOL_UNKNOWN \
25854 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_IP_PROTOCOL_TCP \
25857 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_IP_PROTOCOL_UDP \
25859 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_IP_PROTOCOL_LAST \
25860 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_IP_PROTOCOL_UDP
25862 * If set, this value shall represent the
25863 * Logical VNIC ID of the destination VNIC for the RX
25864 * path and network port id of the destination port for
25869 * Logical VNIC ID of the VNIC where traffic is
25872 uint16_t mirror_vnic_id;
25874 * This value indicates the tunnel type for this filter.
25875 * If this field is not specified, then the filter shall
25876 * apply to both non-tunneled and tunneled packets.
25877 * If this field conflicts with the tunnel_type specified
25878 * in the l2_filter_id, then the HWRM shall return an
25879 * error for this command.
25881 uint8_t tunnel_type;
25883 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_TUNNEL_TYPE_NONTUNNEL \
25885 /* Virtual eXtensible Local Area Network (VXLAN) */
25886 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_TUNNEL_TYPE_VXLAN \
25888 /* Network Virtualization Generic Routing Encapsulation (NVGRE) */
25889 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_TUNNEL_TYPE_NVGRE \
25891 /* Generic Routing Encapsulation (GRE) inside Ethernet payload */
25892 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_TUNNEL_TYPE_L2GRE \
25895 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_TUNNEL_TYPE_IPIP \
25897 /* Generic Network Virtualization Encapsulation (Geneve) */
25898 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_TUNNEL_TYPE_GENEVE \
25900 /* Multi-Protocol Lable Switching (MPLS) */
25901 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_TUNNEL_TYPE_MPLS \
25903 /* Stateless Transport Tunnel (STT) */
25904 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_TUNNEL_TYPE_STT \
25906 /* Generic Routing Encapsulation (GRE) inside IP datagram payload */
25907 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_TUNNEL_TYPE_IPGRE \
25909 /* IPV4 over virtual eXtensible Local Area Network (IPV4oVXLAN) */
25910 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_TUNNEL_TYPE_VXLAN_V4 \
25912 /* Enhance Generic Routing Encapsulation (GRE version 1) inside IP datagram payload */
25913 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_TUNNEL_TYPE_IPGRE_V1 \
25915 /* Use fixed layer 2 ether type of 0xFFFF */
25916 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_TUNNEL_TYPE_L2_ETYPE \
25918 /* IPV6 over virtual eXtensible Local Area Network with GPE header (IPV6oVXLANGPE) */
25919 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_TUNNEL_TYPE_VXLAN_GPE_V6 \
25921 /* Any tunneled traffic */
25922 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_TUNNEL_TYPE_ANYTUNNEL \
25924 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_TUNNEL_TYPE_LAST \
25925 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_TUNNEL_TYPE_ANYTUNNEL
25927 * This hint is provided to help in placing
25928 * the filter in the filter table.
25931 /* No preference */
25932 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_PRI_HINT_NO_PREFER \
25934 /* Above the given filter */
25935 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_PRI_HINT_ABOVE \
25937 /* Below the given filter */
25938 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_PRI_HINT_BELOW \
25940 /* As high as possible */
25941 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_PRI_HINT_HIGHEST \
25943 /* As low as possible */
25944 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_PRI_HINT_LOWEST \
25946 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_PRI_HINT_LAST \
25947 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_PRI_HINT_LOWEST
25949 * The value of source IP address to be used in filtering.
25950 * For IPv4, first four bytes represent the IP address.
25952 uint32_t src_ipaddr[4];
25954 * The value of source IP address mask to be used in
25956 * For IPv4, first four bytes represent the IP address mask.
25958 uint32_t src_ipaddr_mask[4];
25960 * The value of destination IP address to be used in filtering.
25961 * For IPv4, first four bytes represent the IP address.
25963 uint32_t dst_ipaddr[4];
25965 * The value of destination IP address mask to be used in
25967 * For IPv4, first four bytes represent the IP address mask.
25969 uint32_t dst_ipaddr_mask[4];
25971 * The value of source port to be used in filtering.
25972 * Applies to UDP and TCP traffic.
25976 * The value of source port mask to be used in filtering.
25977 * Applies to UDP and TCP traffic.
25979 uint16_t src_port_mask;
25981 * The value of destination port to be used in filtering.
25982 * Applies to UDP and TCP traffic.
25986 * The value of destination port mask to be used in
25988 * Applies to UDP and TCP traffic.
25990 uint16_t dst_port_mask;
25992 * This is the ID of the filter that goes along with
25995 uint64_t ntuple_filter_id_hint;
25997 * The value of rfs_ring_tbl_idx to be used for RFS for this filter.
25998 * This index is used in lieu of the RSS hash when selecting the
25999 * index into the RSS table to determine the rx ring.
26001 uint16_t rfs_ring_tbl_idx;
26002 uint8_t unused_0[6];
26003 } __attribute__((packed));
26005 /* hwrm_cfa_ntuple_filter_alloc_output (size:192b/24B) */
26006 struct hwrm_cfa_ntuple_filter_alloc_output {
26007 /* The specific error status for the command. */
26008 uint16_t error_code;
26009 /* The HWRM command request type. */
26011 /* The sequence ID from the original command. */
26013 /* The length of the response data in number of bytes. */
26015 /* This value is an opaque id into CFA data structures. */
26016 uint64_t ntuple_filter_id;
26018 * The flow id value in bit 0-29 is the actual ID of the flow
26019 * associated with this filter and it shall be used to match
26020 * and associate the flow identifier returned in completion
26021 * records. A value of 0xFFFFFFFF in the 32-bit flow_id field
26022 * shall indicate no valid flow id.
26025 /* Indicate the flow id value. */
26026 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_OUTPUT_FLOW_ID_VALUE_MASK \
26027 UINT32_C(0x3fffffff)
26028 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_OUTPUT_FLOW_ID_VALUE_SFT 0
26029 /* Indicate type of the flow. */
26030 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_OUTPUT_FLOW_ID_TYPE \
26031 UINT32_C(0x40000000)
26033 * If this bit set to 0, then it indicates that the flow is
26036 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_OUTPUT_FLOW_ID_TYPE_INT \
26037 (UINT32_C(0x0) << 30)
26039 * If this bit is set to 1, then it indicates that the flow is
26042 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_OUTPUT_FLOW_ID_TYPE_EXT \
26043 (UINT32_C(0x1) << 30)
26044 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_OUTPUT_FLOW_ID_TYPE_LAST \
26045 HWRM_CFA_NTUPLE_FILTER_ALLOC_OUTPUT_FLOW_ID_TYPE_EXT
26046 /* Indicate the flow direction. */
26047 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_OUTPUT_FLOW_ID_DIR \
26048 UINT32_C(0x80000000)
26049 /* If this bit set to 0, then it indicates rx flow. */
26050 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_OUTPUT_FLOW_ID_DIR_RX \
26051 (UINT32_C(0x0) << 31)
26052 /* If this bit is set to 1, then it indicates that tx flow. */
26053 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_OUTPUT_FLOW_ID_DIR_TX \
26054 (UINT32_C(0x1) << 31)
26055 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_OUTPUT_FLOW_ID_DIR_LAST \
26056 HWRM_CFA_NTUPLE_FILTER_ALLOC_OUTPUT_FLOW_ID_DIR_TX
26057 uint8_t unused_0[3];
26059 * This field is used in Output records to indicate that the output
26060 * is completely written to RAM. This field should be read as '1'
26061 * to indicate that the output has been completely written.
26062 * When writing a command completion or response to an internal processor,
26063 * the order of writes has to be such that this field is written last.
26066 } __attribute__((packed));
26068 /* hwrm_cfa_ntuple_filter_alloc_cmd_err (size:64b/8B) */
26069 struct hwrm_cfa_ntuple_filter_alloc_cmd_err {
26071 * command specific error codes that goes to
26072 * the cmd_err field in Common HWRM Error Response.
26075 /* Unknown error */
26076 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_CMD_ERR_CODE_UNKNOWN \
26078 /* Unable to complete operation due to conflict with Rx Mask VLAN */
26079 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_CMD_ERR_CODE_RX_MASK_VLAN_CONFLICT_ERR \
26081 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_CMD_ERR_CODE_LAST \
26082 HWRM_CFA_NTUPLE_FILTER_ALLOC_CMD_ERR_CODE_RX_MASK_VLAN_CONFLICT_ERR
26083 uint8_t unused_0[7];
26084 } __attribute__((packed));
26086 /*******************************
26087 * hwrm_cfa_ntuple_filter_free *
26088 *******************************/
26091 /* hwrm_cfa_ntuple_filter_free_input (size:192b/24B) */
26092 struct hwrm_cfa_ntuple_filter_free_input {
26093 /* The HWRM command request type. */
26096 * The completion ring to send the completion event on. This should
26097 * be the NQ ID returned from the `nq_alloc` HWRM command.
26099 uint16_t cmpl_ring;
26101 * The sequence ID is used by the driver for tracking multiple
26102 * commands. This ID is treated as opaque data by the firmware and
26103 * the value is returned in the `hwrm_resp_hdr` upon completion.
26107 * The target ID of the command:
26108 * * 0x0-0xFFF8 - The function ID
26109 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
26110 * * 0xFFFD - Reserved for user-space HWRM interface
26113 uint16_t target_id;
26115 * A physical address pointer pointing to a host buffer that the
26116 * command's response data will be written. This can be either a host
26117 * physical address (HPA) or a guest physical address (GPA) and must
26118 * point to a physically contiguous block of memory.
26120 uint64_t resp_addr;
26121 /* This value is an opaque id into CFA data structures. */
26122 uint64_t ntuple_filter_id;
26123 } __attribute__((packed));
26125 /* hwrm_cfa_ntuple_filter_free_output (size:128b/16B) */
26126 struct hwrm_cfa_ntuple_filter_free_output {
26127 /* The specific error status for the command. */
26128 uint16_t error_code;
26129 /* The HWRM command request type. */
26131 /* The sequence ID from the original command. */
26133 /* The length of the response data in number of bytes. */
26135 uint8_t unused_0[7];
26137 * This field is used in Output records to indicate that the output
26138 * is completely written to RAM. This field should be read as '1'
26139 * to indicate that the output has been completely written.
26140 * When writing a command completion or response to an internal processor,
26141 * the order of writes has to be such that this field is written last.
26144 } __attribute__((packed));
26146 /******************************
26147 * hwrm_cfa_ntuple_filter_cfg *
26148 ******************************/
26151 /* hwrm_cfa_ntuple_filter_cfg_input (size:384b/48B) */
26152 struct hwrm_cfa_ntuple_filter_cfg_input {
26153 /* The HWRM command request type. */
26156 * The completion ring to send the completion event on. This should
26157 * be the NQ ID returned from the `nq_alloc` HWRM command.
26159 uint16_t cmpl_ring;
26161 * The sequence ID is used by the driver for tracking multiple
26162 * commands. This ID is treated as opaque data by the firmware and
26163 * the value is returned in the `hwrm_resp_hdr` upon completion.
26167 * The target ID of the command:
26168 * * 0x0-0xFFF8 - The function ID
26169 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
26170 * * 0xFFFD - Reserved for user-space HWRM interface
26173 uint16_t target_id;
26175 * A physical address pointer pointing to a host buffer that the
26176 * command's response data will be written. This can be either a host
26177 * physical address (HPA) or a guest physical address (GPA) and must
26178 * point to a physically contiguous block of memory.
26180 uint64_t resp_addr;
26183 * This bit must be '1' for the new_dst_id field to be
26186 #define HWRM_CFA_NTUPLE_FILTER_CFG_INPUT_ENABLES_NEW_DST_ID \
26189 * This bit must be '1' for the new_mirror_vnic_id field to be
26192 #define HWRM_CFA_NTUPLE_FILTER_CFG_INPUT_ENABLES_NEW_MIRROR_VNIC_ID \
26195 * This bit must be '1' for the new_meter_instance_id field to be
26198 #define HWRM_CFA_NTUPLE_FILTER_CFG_INPUT_ENABLES_NEW_METER_INSTANCE_ID \
26202 * Setting this bit to 1 indicates that dest_id field contains FID.
26203 * Setting this to 0 indicates that dest_id field contains VNIC or VPORT.
26205 #define HWRM_CFA_NTUPLE_FILTER_CFG_INPUT_FLAGS_DEST_FID \
26207 /* This value is an opaque id into CFA data structures. */
26208 uint64_t ntuple_filter_id;
26210 * If set, this value shall represent the new
26211 * Logical VNIC ID of the destination VNIC for the RX
26212 * path and new network port id of the destination port for
26215 uint32_t new_dst_id;
26217 * New Logical VNIC ID of the VNIC where traffic is
26220 uint32_t new_mirror_vnic_id;
26222 * New meter to attach to the flow. Specifying the
26223 * invalid instance ID is used to remove any existing
26224 * meter from the flow.
26226 uint16_t new_meter_instance_id;
26228 * A value of 0xfff is considered invalid and implies the
26229 * instance is not configured.
26231 #define HWRM_CFA_NTUPLE_FILTER_CFG_INPUT_NEW_METER_INSTANCE_ID_INVALID \
26233 #define HWRM_CFA_NTUPLE_FILTER_CFG_INPUT_NEW_METER_INSTANCE_ID_LAST \
26234 HWRM_CFA_NTUPLE_FILTER_CFG_INPUT_NEW_METER_INSTANCE_ID_INVALID
26235 uint8_t unused_1[6];
26236 } __attribute__((packed));
26238 /* hwrm_cfa_ntuple_filter_cfg_output (size:128b/16B) */
26239 struct hwrm_cfa_ntuple_filter_cfg_output {
26240 /* The specific error status for the command. */
26241 uint16_t error_code;
26242 /* The HWRM command request type. */
26244 /* The sequence ID from the original command. */
26246 /* The length of the response data in number of bytes. */
26248 uint8_t unused_0[7];
26250 * This field is used in Output records to indicate that the output
26251 * is completely written to RAM. This field should be read as '1'
26252 * to indicate that the output has been completely written.
26253 * When writing a command completion or response to an internal processor,
26254 * the order of writes has to be such that this field is written last.
26257 } __attribute__((packed));
26259 /**************************
26260 * hwrm_cfa_em_flow_alloc *
26261 **************************/
26264 /* hwrm_cfa_em_flow_alloc_input (size:896b/112B) */
26265 struct hwrm_cfa_em_flow_alloc_input {
26266 /* The HWRM command request type. */
26269 * The completion ring to send the completion event on. This should
26270 * be the NQ ID returned from the `nq_alloc` HWRM command.
26272 uint16_t cmpl_ring;
26274 * The sequence ID is used by the driver for tracking multiple
26275 * commands. This ID is treated as opaque data by the firmware and
26276 * the value is returned in the `hwrm_resp_hdr` upon completion.
26280 * The target ID of the command:
26281 * * 0x0-0xFFF8 - The function ID
26282 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
26283 * * 0xFFFD - Reserved for user-space HWRM interface
26286 uint16_t target_id;
26288 * A physical address pointer pointing to a host buffer that the
26289 * command's response data will be written. This can be either a host
26290 * physical address (HPA) or a guest physical address (GPA) and must
26291 * point to a physically contiguous block of memory.
26293 uint64_t resp_addr;
26296 * Enumeration denoting the RX, TX type of the resource.
26297 * This enumeration is used for resources that are similar for both
26298 * TX and RX paths of the chip.
26300 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_FLAGS_PATH UINT32_C(0x1)
26302 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_FLAGS_PATH_TX UINT32_C(0x0)
26304 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_FLAGS_PATH_RX UINT32_C(0x1)
26305 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_FLAGS_PATH_LAST \
26306 HWRM_CFA_EM_FLOW_ALLOC_INPUT_FLAGS_PATH_RX
26308 * Setting of this flag indicates enabling of a byte counter for a given
26311 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_FLAGS_BYTE_CTR UINT32_C(0x2)
26313 * Setting of this flag indicates enabling of a packet counter for a given
26316 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_FLAGS_PKT_CTR UINT32_C(0x4)
26317 /* Setting of this flag indicates de-capsulation action for the given flow. */
26318 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_FLAGS_DECAP UINT32_C(0x8)
26319 /* Setting of this flag indicates encapsulation action for the given flow. */
26320 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_FLAGS_ENCAP UINT32_C(0x10)
26322 * Setting of this flag indicates drop action. If this flag is not set,
26323 * then it should be considered accept action.
26325 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_FLAGS_DROP UINT32_C(0x20)
26327 * Setting of this flag indicates that a meter is expected to be attached
26328 * to this flow. This hint can be used when choosing the action record
26329 * format required for the flow.
26331 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_FLAGS_METER UINT32_C(0x40)
26334 * This bit must be '1' for the l2_filter_id field to be
26337 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_L2_FILTER_ID \
26340 * This bit must be '1' for the tunnel_type field to be
26343 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_TUNNEL_TYPE \
26346 * This bit must be '1' for the tunnel_id field to be
26349 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_TUNNEL_ID \
26352 * This bit must be '1' for the src_macaddr field to be
26355 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_SRC_MACADDR \
26358 * This bit must be '1' for the dst_macaddr field to be
26361 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_DST_MACADDR \
26364 * This bit must be '1' for the ovlan_vid field to be
26367 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_OVLAN_VID \
26370 * This bit must be '1' for the ivlan_vid field to be
26373 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_IVLAN_VID \
26376 * This bit must be '1' for the ethertype field to be
26379 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_ETHERTYPE \
26382 * This bit must be '1' for the src_ipaddr field to be
26385 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_SRC_IPADDR \
26388 * This bit must be '1' for the dst_ipaddr field to be
26391 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_DST_IPADDR \
26394 * This bit must be '1' for the ipaddr_type field to be
26397 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_IPADDR_TYPE \
26400 * This bit must be '1' for the ip_protocol field to be
26403 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_IP_PROTOCOL \
26406 * This bit must be '1' for the src_port field to be
26409 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_SRC_PORT \
26412 * This bit must be '1' for the dst_port field to be
26415 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_DST_PORT \
26418 * This bit must be '1' for the dst_id field to be
26421 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_DST_ID \
26424 * This bit must be '1' for the mirror_vnic_id field to be
26427 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_MIRROR_VNIC_ID \
26430 * This bit must be '1' for the encap_record_id field to be
26433 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_ENCAP_RECORD_ID \
26436 * This bit must be '1' for the meter_instance_id field to be
26439 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_METER_INSTANCE_ID \
26442 * This value identifies a set of CFA data structures used for an L2
26445 uint64_t l2_filter_id;
26447 uint8_t tunnel_type;
26449 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_TUNNEL_TYPE_NONTUNNEL \
26451 /* Virtual eXtensible Local Area Network (VXLAN) */
26452 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_TUNNEL_TYPE_VXLAN \
26454 /* Network Virtualization Generic Routing Encapsulation (NVGRE) */
26455 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_TUNNEL_TYPE_NVGRE \
26457 /* Generic Routing Encapsulation (GRE) inside Ethernet payload */
26458 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_TUNNEL_TYPE_L2GRE \
26461 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_TUNNEL_TYPE_IPIP \
26463 /* Generic Network Virtualization Encapsulation (Geneve) */
26464 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_TUNNEL_TYPE_GENEVE \
26466 /* Multi-Protocol Lable Switching (MPLS) */
26467 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_TUNNEL_TYPE_MPLS \
26469 /* Stateless Transport Tunnel (STT) */
26470 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_TUNNEL_TYPE_STT \
26472 /* Generic Routing Encapsulation (GRE) inside IP datagram payload */
26473 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_TUNNEL_TYPE_IPGRE \
26475 /* IPV4 over virtual eXtensible Local Area Network (IPV4oVXLAN) */
26476 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_TUNNEL_TYPE_VXLAN_V4 \
26478 /* Enhance Generic Routing Encapsulation (GRE version 1) inside IP datagram payload */
26479 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_TUNNEL_TYPE_IPGRE_V1 \
26481 /* Use fixed layer 2 ether type of 0xFFFF */
26482 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_TUNNEL_TYPE_L2_ETYPE \
26484 /* IPV6 over virtual eXtensible Local Area Network with GPE header (IPV6oVXLANGPE) */
26485 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_TUNNEL_TYPE_VXLAN_GPE_V6 \
26487 /* Any tunneled traffic */
26488 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_TUNNEL_TYPE_ANYTUNNEL \
26490 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_TUNNEL_TYPE_LAST \
26491 HWRM_CFA_EM_FLOW_ALLOC_INPUT_TUNNEL_TYPE_ANYTUNNEL
26492 uint8_t unused_0[3];
26494 * Tunnel identifier.
26495 * Virtual Network Identifier (VNI). Only valid with
26496 * tunnel_types VXLAN, NVGRE, and Geneve.
26497 * Only lower 24-bits of VNI field are used
26498 * in setting up the filter.
26500 uint32_t tunnel_id;
26502 * This value indicates the source MAC address in
26503 * the Ethernet header.
26505 uint8_t src_macaddr[6];
26506 /* The meter instance to attach to the flow. */
26507 uint16_t meter_instance_id;
26509 * A value of 0xfff is considered invalid and implies the
26510 * instance is not configured.
26512 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_METER_INSTANCE_ID_INVALID \
26514 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_METER_INSTANCE_ID_LAST \
26515 HWRM_CFA_EM_FLOW_ALLOC_INPUT_METER_INSTANCE_ID_INVALID
26517 * This value indicates the destination MAC address in
26518 * the Ethernet header.
26520 uint8_t dst_macaddr[6];
26522 * This value indicates the VLAN ID of the outer VLAN tag
26523 * in the Ethernet header.
26525 uint16_t ovlan_vid;
26527 * This value indicates the VLAN ID of the inner VLAN tag
26528 * in the Ethernet header.
26530 uint16_t ivlan_vid;
26531 /* This value indicates the ethertype in the Ethernet header. */
26532 uint16_t ethertype;
26534 * This value indicates the type of IP address.
26537 * All others are invalid.
26539 uint8_t ip_addr_type;
26541 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_IP_ADDR_TYPE_UNKNOWN UINT32_C(0x0)
26543 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_IP_ADDR_TYPE_IPV4 UINT32_C(0x4)
26545 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_IP_ADDR_TYPE_IPV6 UINT32_C(0x6)
26546 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_IP_ADDR_TYPE_LAST \
26547 HWRM_CFA_EM_FLOW_ALLOC_INPUT_IP_ADDR_TYPE_IPV6
26549 * The value of protocol filed in IP header.
26550 * Applies to UDP and TCP traffic.
26554 uint8_t ip_protocol;
26556 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_IP_PROTOCOL_UNKNOWN UINT32_C(0x0)
26558 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_IP_PROTOCOL_TCP UINT32_C(0x6)
26560 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_IP_PROTOCOL_UDP UINT32_C(0x11)
26561 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_IP_PROTOCOL_LAST \
26562 HWRM_CFA_EM_FLOW_ALLOC_INPUT_IP_PROTOCOL_UDP
26563 uint8_t unused_1[2];
26565 * The value of source IP address to be used in filtering.
26566 * For IPv4, first four bytes represent the IP address.
26568 uint32_t src_ipaddr[4];
26570 * big_endian = True
26571 * The value of destination IP address to be used in filtering.
26572 * For IPv4, first four bytes represent the IP address.
26574 uint32_t dst_ipaddr[4];
26576 * The value of source port to be used in filtering.
26577 * Applies to UDP and TCP traffic.
26581 * The value of destination port to be used in filtering.
26582 * Applies to UDP and TCP traffic.
26586 * If set, this value shall represent the
26587 * Logical VNIC ID of the destination VNIC for the RX
26588 * path and network port id of the destination port for
26593 * Logical VNIC ID of the VNIC where traffic is
26596 uint16_t mirror_vnic_id;
26597 /* Logical ID of the encapsulation record. */
26598 uint32_t encap_record_id;
26599 uint8_t unused_2[4];
26600 } __attribute__((packed));
26602 /* hwrm_cfa_em_flow_alloc_output (size:192b/24B) */
26603 struct hwrm_cfa_em_flow_alloc_output {
26604 /* The specific error status for the command. */
26605 uint16_t error_code;
26606 /* The HWRM command request type. */
26608 /* The sequence ID from the original command. */
26610 /* The length of the response data in number of bytes. */
26612 /* This value is an opaque id into CFA data structures. */
26613 uint64_t em_filter_id;
26615 * The flow id value in bit 0-29 is the actual ID of the flow
26616 * associated with this filter and it shall be used to match
26617 * and associate the flow identifier returned in completion
26618 * records. A value of 0xFFFFFFFF in the 32-bit flow_id field
26619 * shall indicate no valid flow id.
26622 /* Indicate the flow id value. */
26623 #define HWRM_CFA_EM_FLOW_ALLOC_OUTPUT_FLOW_ID_VALUE_MASK \
26624 UINT32_C(0x3fffffff)
26625 #define HWRM_CFA_EM_FLOW_ALLOC_OUTPUT_FLOW_ID_VALUE_SFT 0
26626 /* Indicate type of the flow. */
26627 #define HWRM_CFA_EM_FLOW_ALLOC_OUTPUT_FLOW_ID_TYPE \
26628 UINT32_C(0x40000000)
26630 * If this bit set to 0, then it indicates that the flow is
26633 #define HWRM_CFA_EM_FLOW_ALLOC_OUTPUT_FLOW_ID_TYPE_INT \
26634 (UINT32_C(0x0) << 30)
26636 * If this bit is set to 1, then it indicates that the flow is
26639 #define HWRM_CFA_EM_FLOW_ALLOC_OUTPUT_FLOW_ID_TYPE_EXT \
26640 (UINT32_C(0x1) << 30)
26641 #define HWRM_CFA_EM_FLOW_ALLOC_OUTPUT_FLOW_ID_TYPE_LAST \
26642 HWRM_CFA_EM_FLOW_ALLOC_OUTPUT_FLOW_ID_TYPE_EXT
26643 /* Indicate the flow direction. */
26644 #define HWRM_CFA_EM_FLOW_ALLOC_OUTPUT_FLOW_ID_DIR \
26645 UINT32_C(0x80000000)
26646 /* If this bit set to 0, then it indicates rx flow. */
26647 #define HWRM_CFA_EM_FLOW_ALLOC_OUTPUT_FLOW_ID_DIR_RX \
26648 (UINT32_C(0x0) << 31)
26649 /* If this bit is set to 1, then it indicates that tx flow. */
26650 #define HWRM_CFA_EM_FLOW_ALLOC_OUTPUT_FLOW_ID_DIR_TX \
26651 (UINT32_C(0x1) << 31)
26652 #define HWRM_CFA_EM_FLOW_ALLOC_OUTPUT_FLOW_ID_DIR_LAST \
26653 HWRM_CFA_EM_FLOW_ALLOC_OUTPUT_FLOW_ID_DIR_TX
26654 uint8_t unused_0[3];
26656 * This field is used in Output records to indicate that the output
26657 * is completely written to RAM. This field should be read as '1'
26658 * to indicate that the output has been completely written.
26659 * When writing a command completion or response to an internal processor,
26660 * the order of writes has to be such that this field is written last.
26663 } __attribute__((packed));
26665 /*************************
26666 * hwrm_cfa_em_flow_free *
26667 *************************/
26670 /* hwrm_cfa_em_flow_free_input (size:192b/24B) */
26671 struct hwrm_cfa_em_flow_free_input {
26672 /* The HWRM command request type. */
26675 * The completion ring to send the completion event on. This should
26676 * be the NQ ID returned from the `nq_alloc` HWRM command.
26678 uint16_t cmpl_ring;
26680 * The sequence ID is used by the driver for tracking multiple
26681 * commands. This ID is treated as opaque data by the firmware and
26682 * the value is returned in the `hwrm_resp_hdr` upon completion.
26686 * The target ID of the command:
26687 * * 0x0-0xFFF8 - The function ID
26688 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
26689 * * 0xFFFD - Reserved for user-space HWRM interface
26692 uint16_t target_id;
26694 * A physical address pointer pointing to a host buffer that the
26695 * command's response data will be written. This can be either a host
26696 * physical address (HPA) or a guest physical address (GPA) and must
26697 * point to a physically contiguous block of memory.
26699 uint64_t resp_addr;
26700 /* This value is an opaque id into CFA data structures. */
26701 uint64_t em_filter_id;
26702 } __attribute__((packed));
26704 /* hwrm_cfa_em_flow_free_output (size:128b/16B) */
26705 struct hwrm_cfa_em_flow_free_output {
26706 /* The specific error status for the command. */
26707 uint16_t error_code;
26708 /* The HWRM command request type. */
26710 /* The sequence ID from the original command. */
26712 /* The length of the response data in number of bytes. */
26714 uint8_t unused_0[7];
26716 * This field is used in Output records to indicate that the output
26717 * is completely written to RAM. This field should be read as '1'
26718 * to indicate that the output has been completely written.
26719 * When writing a command completion or response to an internal processor,
26720 * the order of writes has to be such that this field is written last.
26723 } __attribute__((packed));
26725 /************************
26726 * hwrm_cfa_meter_qcaps *
26727 ************************/
26730 /* hwrm_cfa_meter_qcaps_input (size:128b/16B) */
26731 struct hwrm_cfa_meter_qcaps_input {
26732 /* The HWRM command request type. */
26735 * The completion ring to send the completion event on. This should
26736 * be the NQ ID returned from the `nq_alloc` HWRM command.
26738 uint16_t cmpl_ring;
26740 * The sequence ID is used by the driver for tracking multiple
26741 * commands. This ID is treated as opaque data by the firmware and
26742 * the value is returned in the `hwrm_resp_hdr` upon completion.
26746 * The target ID of the command:
26747 * * 0x0-0xFFF8 - The function ID
26748 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
26749 * * 0xFFFD - Reserved for user-space HWRM interface
26752 uint16_t target_id;
26754 * A physical address pointer pointing to a host buffer that the
26755 * command's response data will be written. This can be either a host
26756 * physical address (HPA) or a guest physical address (GPA) and must
26757 * point to a physically contiguous block of memory.
26759 uint64_t resp_addr;
26760 } __attribute__((packed));
26762 /* hwrm_cfa_meter_qcaps_output (size:320b/40B) */
26763 struct hwrm_cfa_meter_qcaps_output {
26764 /* The specific error status for the command. */
26765 uint16_t error_code;
26766 /* The HWRM command request type. */
26768 /* The sequence ID from the original command. */
26770 /* The length of the response data in number of bytes. */
26774 * Enumeration denoting the clock at which the Meter is running with.
26775 * This enumeration is used for resources that are similar for both
26776 * TX and RX paths of the chip.
26778 #define HWRM_CFA_METER_QCAPS_OUTPUT_FLAGS_CLOCK_MASK UINT32_C(0xf)
26779 #define HWRM_CFA_METER_QCAPS_OUTPUT_FLAGS_CLOCK_SFT 0
26781 #define HWRM_CFA_METER_QCAPS_OUTPUT_FLAGS_CLOCK_375MHZ UINT32_C(0x0)
26783 #define HWRM_CFA_METER_QCAPS_OUTPUT_FLAGS_CLOCK_625MHZ UINT32_C(0x1)
26784 #define HWRM_CFA_METER_QCAPS_OUTPUT_FLAGS_CLOCK_LAST \
26785 HWRM_CFA_METER_QCAPS_OUTPUT_FLAGS_CLOCK_625MHZ
26786 uint8_t unused_0[4];
26788 * The minimum guaranteed number of tx meter profiles supported
26789 * for this function.
26791 uint16_t min_tx_profile;
26793 * The maximum non-guaranteed number of tx meter profiles supported
26794 * for this function.
26796 uint16_t max_tx_profile;
26798 * The minimum guaranteed number of rx meter profiles supported
26799 * for this function.
26801 uint16_t min_rx_profile;
26803 * The maximum non-guaranteed number of rx meter profiles supported
26804 * for this function.
26806 uint16_t max_rx_profile;
26808 * The minimum guaranteed number of tx meter instances supported
26809 * for this function.
26811 uint16_t min_tx_instance;
26813 * The maximum non-guaranteed number of tx meter instances supported
26814 * for this function.
26816 uint16_t max_tx_instance;
26818 * The minimum guaranteed number of rx meter instances supported
26819 * for this function.
26821 uint16_t min_rx_instance;
26823 * The maximum non-guaranteed number of rx meter instances supported
26824 * for this function.
26826 uint16_t max_rx_instance;
26827 uint8_t unused_1[7];
26829 * This field is used in Output records to indicate that the output
26830 * is completely written to RAM. This field should be read as '1'
26831 * to indicate that the output has been completely written.
26832 * When writing a command completion or response to an internal processor,
26833 * the order of writes has to be such that this field is written last.
26836 } __attribute__((packed));
26838 /********************************
26839 * hwrm_cfa_meter_profile_alloc *
26840 ********************************/
26843 /* hwrm_cfa_meter_profile_alloc_input (size:320b/40B) */
26844 struct hwrm_cfa_meter_profile_alloc_input {
26845 /* The HWRM command request type. */
26848 * The completion ring to send the completion event on. This should
26849 * be the NQ ID returned from the `nq_alloc` HWRM command.
26851 uint16_t cmpl_ring;
26853 * The sequence ID is used by the driver for tracking multiple
26854 * commands. This ID is treated as opaque data by the firmware and
26855 * the value is returned in the `hwrm_resp_hdr` upon completion.
26859 * The target ID of the command:
26860 * * 0x0-0xFFF8 - The function ID
26861 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
26862 * * 0xFFFD - Reserved for user-space HWRM interface
26865 uint16_t target_id;
26867 * A physical address pointer pointing to a host buffer that the
26868 * command's response data will be written. This can be either a host
26869 * physical address (HPA) or a guest physical address (GPA) and must
26870 * point to a physically contiguous block of memory.
26872 uint64_t resp_addr;
26875 * Enumeration denoting the RX, TX type of the resource.
26876 * This enumeration is used for resources that are similar for both
26877 * TX and RX paths of the chip.
26879 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_FLAGS_PATH UINT32_C(0x1)
26881 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_FLAGS_PATH_TX \
26884 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_FLAGS_PATH_RX \
26886 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_FLAGS_PATH_LAST \
26887 HWRM_CFA_METER_PROFILE_ALLOC_INPUT_FLAGS_PATH_RX
26888 /* The meter algorithm type. */
26889 uint8_t meter_type;
26890 /* RFC 2697 (srTCM) */
26891 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_METER_TYPE_RFC2697 \
26893 /* RFC 2698 (trTCM) */
26894 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_METER_TYPE_RFC2698 \
26896 /* RFC 4115 (trTCM) */
26897 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_METER_TYPE_RFC4115 \
26899 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_METER_TYPE_LAST \
26900 HWRM_CFA_METER_PROFILE_ALLOC_INPUT_METER_TYPE_RFC4115
26902 * This field is reserved for the future use.
26903 * It shall be set to 0.
26905 uint16_t reserved1;
26907 * This field is reserved for the future use.
26908 * It shall be set to 0.
26910 uint32_t reserved2;
26911 /* A meter rate specified in bytes-per-second. */
26912 uint32_t commit_rate;
26913 /* The bandwidth value. */
26914 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_RATE_BW_VALUE_MASK \
26915 UINT32_C(0xfffffff)
26916 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_RATE_BW_VALUE_SFT \
26918 /* The granularity of the value (bits or bytes). */
26919 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_RATE_SCALE \
26920 UINT32_C(0x10000000)
26921 /* Value is in bits. */
26922 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_RATE_SCALE_BITS \
26923 (UINT32_C(0x0) << 28)
26924 /* Value is in bytes. */
26925 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_RATE_SCALE_BYTES \
26926 (UINT32_C(0x1) << 28)
26927 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_RATE_SCALE_LAST \
26928 HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_RATE_SCALE_BYTES
26929 /* bw_value_unit is 3 b */
26930 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_RATE_BW_VALUE_UNIT_MASK \
26931 UINT32_C(0xe0000000)
26932 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_RATE_BW_VALUE_UNIT_SFT \
26934 /* Value is in Mb or MB (base 10). */
26935 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_RATE_BW_VALUE_UNIT_MEGA \
26936 (UINT32_C(0x0) << 29)
26937 /* Value is in Kb or KB (base 10). */
26938 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_RATE_BW_VALUE_UNIT_KILO \
26939 (UINT32_C(0x2) << 29)
26940 /* Value is in bits or bytes. */
26941 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_RATE_BW_VALUE_UNIT_BASE \
26942 (UINT32_C(0x4) << 29)
26943 /* Value is in Gb or GB (base 10). */
26944 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_RATE_BW_VALUE_UNIT_GIGA \
26945 (UINT32_C(0x6) << 29)
26946 /* Value is in 1/100th of a percentage of total bandwidth. */
26947 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_RATE_BW_VALUE_UNIT_PERCENT1_100 \
26948 (UINT32_C(0x1) << 29)
26950 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_RATE_BW_VALUE_UNIT_RAW \
26951 (UINT32_C(0x7) << 29)
26952 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_RATE_BW_VALUE_UNIT_LAST \
26953 HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_RATE_BW_VALUE_UNIT_RAW
26954 /* A meter burst size specified in bytes. */
26955 uint32_t commit_burst;
26956 /* The bandwidth value. */
26957 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_BURST_BW_VALUE_MASK \
26958 UINT32_C(0xfffffff)
26959 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_BURST_BW_VALUE_SFT \
26961 /* The granularity of the value (bits or bytes). */
26962 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_BURST_SCALE \
26963 UINT32_C(0x10000000)
26964 /* Value is in bits. */
26965 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_BURST_SCALE_BITS \
26966 (UINT32_C(0x0) << 28)
26967 /* Value is in bytes. */
26968 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_BURST_SCALE_BYTES \
26969 (UINT32_C(0x1) << 28)
26970 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_BURST_SCALE_LAST \
26971 HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_BURST_SCALE_BYTES
26972 /* bw_value_unit is 3 b */
26973 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_BURST_BW_VALUE_UNIT_MASK \
26974 UINT32_C(0xe0000000)
26975 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_BURST_BW_VALUE_UNIT_SFT \
26977 /* Value is in Mb or MB (base 10). */
26978 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_BURST_BW_VALUE_UNIT_MEGA \
26979 (UINT32_C(0x0) << 29)
26980 /* Value is in Kb or KB (base 10). */
26981 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_BURST_BW_VALUE_UNIT_KILO \
26982 (UINT32_C(0x2) << 29)
26983 /* Value is in bits or bytes. */
26984 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_BURST_BW_VALUE_UNIT_BASE \
26985 (UINT32_C(0x4) << 29)
26986 /* Value is in Gb or GB (base 10). */
26987 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_BURST_BW_VALUE_UNIT_GIGA \
26988 (UINT32_C(0x6) << 29)
26989 /* Value is in 1/100th of a percentage of total bandwidth. */
26990 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_BURST_BW_VALUE_UNIT_PERCENT1_100 \
26991 (UINT32_C(0x1) << 29)
26992 /* Invalid value */
26993 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_BURST_BW_VALUE_UNIT_INVALID \
26994 (UINT32_C(0x7) << 29)
26995 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_BURST_BW_VALUE_UNIT_LAST \
26996 HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_BURST_BW_VALUE_UNIT_INVALID
26997 /* A meter rate specified in bytes-per-second. */
26998 uint32_t excess_peak_rate;
26999 /* The bandwidth value. */
27000 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_RATE_BW_VALUE_MASK \
27001 UINT32_C(0xfffffff)
27002 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_RATE_BW_VALUE_SFT \
27004 /* The granularity of the value (bits or bytes). */
27005 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_RATE_SCALE \
27006 UINT32_C(0x10000000)
27007 /* Value is in bits. */
27008 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_RATE_SCALE_BITS \
27009 (UINT32_C(0x0) << 28)
27010 /* Value is in bytes. */
27011 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_RATE_SCALE_BYTES \
27012 (UINT32_C(0x1) << 28)
27013 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_RATE_SCALE_LAST \
27014 HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_RATE_SCALE_BYTES
27015 /* bw_value_unit is 3 b */
27016 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_RATE_BW_VALUE_UNIT_MASK \
27017 UINT32_C(0xe0000000)
27018 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_RATE_BW_VALUE_UNIT_SFT \
27020 /* Value is in Mb or MB (base 10). */
27021 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_RATE_BW_VALUE_UNIT_MEGA \
27022 (UINT32_C(0x0) << 29)
27023 /* Value is in Kb or KB (base 10). */
27024 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_RATE_BW_VALUE_UNIT_KILO \
27025 (UINT32_C(0x2) << 29)
27026 /* Value is in bits or bytes. */
27027 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_RATE_BW_VALUE_UNIT_BASE \
27028 (UINT32_C(0x4) << 29)
27029 /* Value is in Gb or GB (base 10). */
27030 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_RATE_BW_VALUE_UNIT_GIGA \
27031 (UINT32_C(0x6) << 29)
27032 /* Value is in 1/100th of a percentage of total bandwidth. */
27033 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_RATE_BW_VALUE_UNIT_PERCENT1_100 \
27034 (UINT32_C(0x1) << 29)
27036 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_RATE_BW_VALUE_UNIT_RAW \
27037 (UINT32_C(0x7) << 29)
27038 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_RATE_BW_VALUE_UNIT_LAST \
27039 HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_RATE_BW_VALUE_UNIT_RAW
27040 /* A meter burst size specified in bytes. */
27041 uint32_t excess_peak_burst;
27042 /* The bandwidth value. */
27043 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_BURST_BW_VALUE_MASK \
27044 UINT32_C(0xfffffff)
27045 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_BURST_BW_VALUE_SFT \
27047 /* The granularity of the value (bits or bytes). */
27048 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_BURST_SCALE \
27049 UINT32_C(0x10000000)
27050 /* Value is in bits. */
27051 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_BURST_SCALE_BITS \
27052 (UINT32_C(0x0) << 28)
27053 /* Value is in bytes. */
27054 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_BURST_SCALE_BYTES \
27055 (UINT32_C(0x1) << 28)
27056 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_BURST_SCALE_LAST \
27057 HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_BURST_SCALE_BYTES
27058 /* bw_value_unit is 3 b */
27059 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_BURST_BW_VALUE_UNIT_MASK \
27060 UINT32_C(0xe0000000)
27061 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_BURST_BW_VALUE_UNIT_SFT \
27063 /* Value is in Mb or MB (base 10). */
27064 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_BURST_BW_VALUE_UNIT_MEGA \
27065 (UINT32_C(0x0) << 29)
27066 /* Value is in Kb or KB (base 10). */
27067 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_BURST_BW_VALUE_UNIT_KILO \
27068 (UINT32_C(0x2) << 29)
27069 /* Value is in bits or bytes. */
27070 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_BURST_BW_VALUE_UNIT_BASE \
27071 (UINT32_C(0x4) << 29)
27072 /* Value is in Gb or GB (base 10). */
27073 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_BURST_BW_VALUE_UNIT_GIGA \
27074 (UINT32_C(0x6) << 29)
27075 /* Value is in 1/100th of a percentage of total bandwidth. */
27076 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_BURST_BW_VALUE_UNIT_PERCENT1_100 \
27077 (UINT32_C(0x1) << 29)
27079 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_BURST_BW_VALUE_UNIT_INVALID \
27080 (UINT32_C(0x7) << 29)
27081 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_BURST_BW_VALUE_UNIT_LAST \
27082 HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_BURST_BW_VALUE_UNIT_INVALID
27083 } __attribute__((packed));
27085 /* hwrm_cfa_meter_profile_alloc_output (size:128b/16B) */
27086 struct hwrm_cfa_meter_profile_alloc_output {
27087 /* The specific error status for the command. */
27088 uint16_t error_code;
27089 /* The HWRM command request type. */
27091 /* The sequence ID from the original command. */
27093 /* The length of the response data in number of bytes. */
27095 /* This value identifies a meter profile in CFA. */
27096 uint16_t meter_profile_id;
27098 * A value of 0xfff is considered invalid and implies the
27099 * profile is not configured.
27101 #define HWRM_CFA_METER_PROFILE_ALLOC_OUTPUT_METER_PROFILE_ID_INVALID \
27103 #define HWRM_CFA_METER_PROFILE_ALLOC_OUTPUT_METER_PROFILE_ID_LAST \
27104 HWRM_CFA_METER_PROFILE_ALLOC_OUTPUT_METER_PROFILE_ID_INVALID
27105 uint8_t unused_0[5];
27107 * This field is used in Output records to indicate that the output
27108 * is completely written to RAM. This field should be read as '1'
27109 * to indicate that the output has been completely written.
27110 * When writing a command completion or response to an internal processor,
27111 * the order of writes has to be such that this field is written last.
27114 } __attribute__((packed));
27116 /*******************************
27117 * hwrm_cfa_meter_profile_free *
27118 *******************************/
27121 /* hwrm_cfa_meter_profile_free_input (size:192b/24B) */
27122 struct hwrm_cfa_meter_profile_free_input {
27123 /* The HWRM command request type. */
27126 * The completion ring to send the completion event on. This should
27127 * be the NQ ID returned from the `nq_alloc` HWRM command.
27129 uint16_t cmpl_ring;
27131 * The sequence ID is used by the driver for tracking multiple
27132 * commands. This ID is treated as opaque data by the firmware and
27133 * the value is returned in the `hwrm_resp_hdr` upon completion.
27137 * The target ID of the command:
27138 * * 0x0-0xFFF8 - The function ID
27139 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
27140 * * 0xFFFD - Reserved for user-space HWRM interface
27143 uint16_t target_id;
27145 * A physical address pointer pointing to a host buffer that the
27146 * command's response data will be written. This can be either a host
27147 * physical address (HPA) or a guest physical address (GPA) and must
27148 * point to a physically contiguous block of memory.
27150 uint64_t resp_addr;
27153 * Enumeration denoting the RX, TX type of the resource.
27154 * This enumeration is used for resources that are similar for both
27155 * TX and RX paths of the chip.
27157 #define HWRM_CFA_METER_PROFILE_FREE_INPUT_FLAGS_PATH UINT32_C(0x1)
27159 #define HWRM_CFA_METER_PROFILE_FREE_INPUT_FLAGS_PATH_TX \
27162 #define HWRM_CFA_METER_PROFILE_FREE_INPUT_FLAGS_PATH_RX \
27164 #define HWRM_CFA_METER_PROFILE_FREE_INPUT_FLAGS_PATH_LAST \
27165 HWRM_CFA_METER_PROFILE_FREE_INPUT_FLAGS_PATH_RX
27167 /* This value identifies a meter profile in CFA. */
27168 uint16_t meter_profile_id;
27170 * A value of 0xfff is considered invalid and implies the
27171 * profile is not configured.
27173 #define HWRM_CFA_METER_PROFILE_FREE_INPUT_METER_PROFILE_ID_INVALID \
27175 #define HWRM_CFA_METER_PROFILE_FREE_INPUT_METER_PROFILE_ID_LAST \
27176 HWRM_CFA_METER_PROFILE_FREE_INPUT_METER_PROFILE_ID_INVALID
27177 uint8_t unused_1[4];
27178 } __attribute__((packed));
27180 /* hwrm_cfa_meter_profile_free_output (size:128b/16B) */
27181 struct hwrm_cfa_meter_profile_free_output {
27182 /* The specific error status for the command. */
27183 uint16_t error_code;
27184 /* The HWRM command request type. */
27186 /* The sequence ID from the original command. */
27188 /* The length of the response data in number of bytes. */
27190 uint8_t unused_0[7];
27192 * This field is used in Output records to indicate that the output
27193 * is completely written to RAM. This field should be read as '1'
27194 * to indicate that the output has been completely written.
27195 * When writing a command completion or response to an internal processor,
27196 * the order of writes has to be such that this field is written last.
27199 } __attribute__((packed));
27201 /******************************
27202 * hwrm_cfa_meter_profile_cfg *
27203 ******************************/
27206 /* hwrm_cfa_meter_profile_cfg_input (size:320b/40B) */
27207 struct hwrm_cfa_meter_profile_cfg_input {
27208 /* The HWRM command request type. */
27211 * The completion ring to send the completion event on. This should
27212 * be the NQ ID returned from the `nq_alloc` HWRM command.
27214 uint16_t cmpl_ring;
27216 * The sequence ID is used by the driver for tracking multiple
27217 * commands. This ID is treated as opaque data by the firmware and
27218 * the value is returned in the `hwrm_resp_hdr` upon completion.
27222 * The target ID of the command:
27223 * * 0x0-0xFFF8 - The function ID
27224 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
27225 * * 0xFFFD - Reserved for user-space HWRM interface
27228 uint16_t target_id;
27230 * A physical address pointer pointing to a host buffer that the
27231 * command's response data will be written. This can be either a host
27232 * physical address (HPA) or a guest physical address (GPA) and must
27233 * point to a physically contiguous block of memory.
27235 uint64_t resp_addr;
27238 * Enumeration denoting the RX, TX type of the resource.
27239 * This enumeration is used for resources that are similar for both
27240 * TX and RX paths of the chip.
27242 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_FLAGS_PATH UINT32_C(0x1)
27244 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_FLAGS_PATH_TX UINT32_C(0x0)
27246 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_FLAGS_PATH_RX UINT32_C(0x1)
27247 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_FLAGS_PATH_LAST \
27248 HWRM_CFA_METER_PROFILE_CFG_INPUT_FLAGS_PATH_RX
27249 /* The meter algorithm type. */
27250 uint8_t meter_type;
27251 /* RFC 2697 (srTCM) */
27252 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_METER_TYPE_RFC2697 \
27254 /* RFC 2698 (trTCM) */
27255 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_METER_TYPE_RFC2698 \
27257 /* RFC 4115 (trTCM) */
27258 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_METER_TYPE_RFC4115 \
27260 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_METER_TYPE_LAST \
27261 HWRM_CFA_METER_PROFILE_CFG_INPUT_METER_TYPE_RFC4115
27262 /* This value identifies a meter profile in CFA. */
27263 uint16_t meter_profile_id;
27265 * A value of 0xfff is considered invalid and implies the
27266 * profile is not configured.
27268 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_METER_PROFILE_ID_INVALID \
27270 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_METER_PROFILE_ID_LAST \
27271 HWRM_CFA_METER_PROFILE_CFG_INPUT_METER_PROFILE_ID_INVALID
27273 * This field is reserved for the future use.
27274 * It shall be set to 0.
27277 /* A meter rate specified in bytes-per-second. */
27278 uint32_t commit_rate;
27279 /* The bandwidth value. */
27280 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_RATE_BW_VALUE_MASK \
27281 UINT32_C(0xfffffff)
27282 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_RATE_BW_VALUE_SFT \
27284 /* The granularity of the value (bits or bytes). */
27285 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_RATE_SCALE \
27286 UINT32_C(0x10000000)
27287 /* Value is in bits. */
27288 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_RATE_SCALE_BITS \
27289 (UINT32_C(0x0) << 28)
27290 /* Value is in bytes. */
27291 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_RATE_SCALE_BYTES \
27292 (UINT32_C(0x1) << 28)
27293 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_RATE_SCALE_LAST \
27294 HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_RATE_SCALE_BYTES
27295 /* bw_value_unit is 3 b */
27296 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_RATE_BW_VALUE_UNIT_MASK \
27297 UINT32_C(0xe0000000)
27298 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_RATE_BW_VALUE_UNIT_SFT \
27300 /* Value is in Mb or MB (base 10). */
27301 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_RATE_BW_VALUE_UNIT_MEGA \
27302 (UINT32_C(0x0) << 29)
27303 /* Value is in Kb or KB (base 10). */
27304 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_RATE_BW_VALUE_UNIT_KILO \
27305 (UINT32_C(0x2) << 29)
27306 /* Value is in bits or bytes. */
27307 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_RATE_BW_VALUE_UNIT_BASE \
27308 (UINT32_C(0x4) << 29)
27309 /* Value is in Gb or GB (base 10). */
27310 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_RATE_BW_VALUE_UNIT_GIGA \
27311 (UINT32_C(0x6) << 29)
27312 /* Value is in 1/100th of a percentage of total bandwidth. */
27313 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_RATE_BW_VALUE_UNIT_PERCENT1_100 \
27314 (UINT32_C(0x1) << 29)
27316 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_RATE_BW_VALUE_UNIT_RAW \
27317 (UINT32_C(0x7) << 29)
27318 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_RATE_BW_VALUE_UNIT_LAST \
27319 HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_RATE_BW_VALUE_UNIT_RAW
27320 /* A meter burst size specified in bytes. */
27321 uint32_t commit_burst;
27322 /* The bandwidth value. */
27323 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_BURST_BW_VALUE_MASK \
27324 UINT32_C(0xfffffff)
27325 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_BURST_BW_VALUE_SFT \
27327 /* The granularity of the value (bits or bytes). */
27328 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_BURST_SCALE \
27329 UINT32_C(0x10000000)
27330 /* Value is in bits. */
27331 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_BURST_SCALE_BITS \
27332 (UINT32_C(0x0) << 28)
27333 /* Value is in bytes. */
27334 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_BURST_SCALE_BYTES \
27335 (UINT32_C(0x1) << 28)
27336 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_BURST_SCALE_LAST \
27337 HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_BURST_SCALE_BYTES
27338 /* bw_value_unit is 3 b */
27339 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_BURST_BW_VALUE_UNIT_MASK \
27340 UINT32_C(0xe0000000)
27341 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_BURST_BW_VALUE_UNIT_SFT \
27343 /* Value is in Mb or MB (base 10). */
27344 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_BURST_BW_VALUE_UNIT_MEGA \
27345 (UINT32_C(0x0) << 29)
27346 /* Value is in Kb or KB (base 10). */
27347 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_BURST_BW_VALUE_UNIT_KILO \
27348 (UINT32_C(0x2) << 29)
27349 /* Value is in bits or bytes. */
27350 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_BURST_BW_VALUE_UNIT_BASE \
27351 (UINT32_C(0x4) << 29)
27352 /* Value is in Gb or GB (base 10). */
27353 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_BURST_BW_VALUE_UNIT_GIGA \
27354 (UINT32_C(0x6) << 29)
27355 /* Value is in 1/100th of a percentage of total bandwidth. */
27356 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_BURST_BW_VALUE_UNIT_PERCENT1_100 \
27357 (UINT32_C(0x1) << 29)
27358 /* Invalid value */
27359 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_BURST_BW_VALUE_UNIT_INVALID \
27360 (UINT32_C(0x7) << 29)
27361 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_BURST_BW_VALUE_UNIT_LAST \
27362 HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_BURST_BW_VALUE_UNIT_INVALID
27363 /* A meter rate specified in bytes-per-second. */
27364 uint32_t excess_peak_rate;
27365 /* The bandwidth value. */
27366 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_RATE_BW_VALUE_MASK \
27367 UINT32_C(0xfffffff)
27368 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_RATE_BW_VALUE_SFT \
27370 /* The granularity of the value (bits or bytes). */
27371 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_RATE_SCALE \
27372 UINT32_C(0x10000000)
27373 /* Value is in bits. */
27374 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_RATE_SCALE_BITS \
27375 (UINT32_C(0x0) << 28)
27376 /* Value is in bytes. */
27377 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_RATE_SCALE_BYTES \
27378 (UINT32_C(0x1) << 28)
27379 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_RATE_SCALE_LAST \
27380 HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_RATE_SCALE_BYTES
27381 /* bw_value_unit is 3 b */
27382 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_RATE_BW_VALUE_UNIT_MASK \
27383 UINT32_C(0xe0000000)
27384 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_RATE_BW_VALUE_UNIT_SFT \
27386 /* Value is in Mb or MB (base 10). */
27387 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_RATE_BW_VALUE_UNIT_MEGA \
27388 (UINT32_C(0x0) << 29)
27389 /* Value is in Kb or KB (base 10). */
27390 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_RATE_BW_VALUE_UNIT_KILO \
27391 (UINT32_C(0x2) << 29)
27392 /* Value is in bits or bytes. */
27393 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_RATE_BW_VALUE_UNIT_BASE \
27394 (UINT32_C(0x4) << 29)
27395 /* Value is in Gb or GB (base 10). */
27396 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_RATE_BW_VALUE_UNIT_GIGA \
27397 (UINT32_C(0x6) << 29)
27398 /* Value is in 1/100th of a percentage of total bandwidth. */
27399 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_RATE_BW_VALUE_UNIT_PERCENT1_100 \
27400 (UINT32_C(0x1) << 29)
27402 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_RATE_BW_VALUE_UNIT_RAW \
27403 (UINT32_C(0x7) << 29)
27404 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_RATE_BW_VALUE_UNIT_LAST \
27405 HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_RATE_BW_VALUE_UNIT_RAW
27406 /* A meter burst size specified in bytes. */
27407 uint32_t excess_peak_burst;
27408 /* The bandwidth value. */
27409 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_BURST_BW_VALUE_MASK \
27410 UINT32_C(0xfffffff)
27411 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_BURST_BW_VALUE_SFT \
27413 /* The granularity of the value (bits or bytes). */
27414 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_BURST_SCALE \
27415 UINT32_C(0x10000000)
27416 /* Value is in bits. */
27417 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_BURST_SCALE_BITS \
27418 (UINT32_C(0x0) << 28)
27419 /* Value is in bytes. */
27420 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_BURST_SCALE_BYTES \
27421 (UINT32_C(0x1) << 28)
27422 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_BURST_SCALE_LAST \
27423 HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_BURST_SCALE_BYTES
27424 /* bw_value_unit is 3 b */
27425 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_BURST_BW_VALUE_UNIT_MASK \
27426 UINT32_C(0xe0000000)
27427 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_BURST_BW_VALUE_UNIT_SFT \
27429 /* Value is in Mb or MB (base 10). */
27430 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_BURST_BW_VALUE_UNIT_MEGA \
27431 (UINT32_C(0x0) << 29)
27432 /* Value is in Kb or KB (base 10). */
27433 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_BURST_BW_VALUE_UNIT_KILO \
27434 (UINT32_C(0x2) << 29)
27435 /* Value is in bits or bytes. */
27436 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_BURST_BW_VALUE_UNIT_BASE \
27437 (UINT32_C(0x4) << 29)
27438 /* Value is in Gb or GB (base 10). */
27439 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_BURST_BW_VALUE_UNIT_GIGA \
27440 (UINT32_C(0x6) << 29)
27441 /* Value is in 1/100th of a percentage of total bandwidth. */
27442 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_BURST_BW_VALUE_UNIT_PERCENT1_100 \
27443 (UINT32_C(0x1) << 29)
27445 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_BURST_BW_VALUE_UNIT_INVALID \
27446 (UINT32_C(0x7) << 29)
27447 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_BURST_BW_VALUE_UNIT_LAST \
27448 HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_BURST_BW_VALUE_UNIT_INVALID
27449 } __attribute__((packed));
27451 /* hwrm_cfa_meter_profile_cfg_output (size:128b/16B) */
27452 struct hwrm_cfa_meter_profile_cfg_output {
27453 /* The specific error status for the command. */
27454 uint16_t error_code;
27455 /* The HWRM command request type. */
27457 /* The sequence ID from the original command. */
27459 /* The length of the response data in number of bytes. */
27461 uint8_t unused_0[7];
27463 * This field is used in Output records to indicate that the output
27464 * is completely written to RAM. This field should be read as '1'
27465 * to indicate that the output has been completely written.
27466 * When writing a command completion or response to an internal processor,
27467 * the order of writes has to be such that this field is written last.
27470 } __attribute__((packed));
27472 /*********************************
27473 * hwrm_cfa_meter_instance_alloc *
27474 *********************************/
27477 /* hwrm_cfa_meter_instance_alloc_input (size:192b/24B) */
27478 struct hwrm_cfa_meter_instance_alloc_input {
27479 /* The HWRM command request type. */
27482 * The completion ring to send the completion event on. This should
27483 * be the NQ ID returned from the `nq_alloc` HWRM command.
27485 uint16_t cmpl_ring;
27487 * The sequence ID is used by the driver for tracking multiple
27488 * commands. This ID is treated as opaque data by the firmware and
27489 * the value is returned in the `hwrm_resp_hdr` upon completion.
27493 * The target ID of the command:
27494 * * 0x0-0xFFF8 - The function ID
27495 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
27496 * * 0xFFFD - Reserved for user-space HWRM interface
27499 uint16_t target_id;
27501 * A physical address pointer pointing to a host buffer that the
27502 * command's response data will be written. This can be either a host
27503 * physical address (HPA) or a guest physical address (GPA) and must
27504 * point to a physically contiguous block of memory.
27506 uint64_t resp_addr;
27509 * Enumeration denoting the RX, TX type of the resource.
27510 * This enumeration is used for resources that are similar for both
27511 * TX and RX paths of the chip.
27513 #define HWRM_CFA_METER_INSTANCE_ALLOC_INPUT_FLAGS_PATH \
27516 #define HWRM_CFA_METER_INSTANCE_ALLOC_INPUT_FLAGS_PATH_TX \
27519 #define HWRM_CFA_METER_INSTANCE_ALLOC_INPUT_FLAGS_PATH_RX \
27521 #define HWRM_CFA_METER_INSTANCE_ALLOC_INPUT_FLAGS_PATH_LAST \
27522 HWRM_CFA_METER_INSTANCE_ALLOC_INPUT_FLAGS_PATH_RX
27524 /* This value identifies a meter profile in CFA. */
27525 uint16_t meter_profile_id;
27527 * A value of 0xffff is considered invalid and implies the
27528 * profile is not configured.
27530 #define HWRM_CFA_METER_INSTANCE_ALLOC_INPUT_METER_PROFILE_ID_INVALID \
27532 #define HWRM_CFA_METER_INSTANCE_ALLOC_INPUT_METER_PROFILE_ID_LAST \
27533 HWRM_CFA_METER_INSTANCE_ALLOC_INPUT_METER_PROFILE_ID_INVALID
27534 uint8_t unused_1[4];
27535 } __attribute__((packed));
27537 /* hwrm_cfa_meter_instance_alloc_output (size:128b/16B) */
27538 struct hwrm_cfa_meter_instance_alloc_output {
27539 /* The specific error status for the command. */
27540 uint16_t error_code;
27541 /* The HWRM command request type. */
27543 /* The sequence ID from the original command. */
27545 /* The length of the response data in number of bytes. */
27547 /* This value identifies a meter instance in CFA. */
27548 uint16_t meter_instance_id;
27550 * A value of 0xffff is considered invalid and implies the
27551 * instance is not configured.
27553 #define HWRM_CFA_METER_INSTANCE_ALLOC_OUTPUT_METER_INSTANCE_ID_INVALID \
27555 #define HWRM_CFA_METER_INSTANCE_ALLOC_OUTPUT_METER_INSTANCE_ID_LAST \
27556 HWRM_CFA_METER_INSTANCE_ALLOC_OUTPUT_METER_INSTANCE_ID_INVALID
27557 uint8_t unused_0[5];
27559 * This field is used in Output records to indicate that the output
27560 * is completely written to RAM. This field should be read as '1'
27561 * to indicate that the output has been completely written.
27562 * When writing a command completion or response to an internal processor,
27563 * the order of writes has to be such that this field is written last.
27566 } __attribute__((packed));
27568 /*******************************
27569 * hwrm_cfa_meter_instance_cfg *
27570 *******************************/
27573 /* hwrm_cfa_meter_instance_cfg_input (size:192b/24B) */
27574 struct hwrm_cfa_meter_instance_cfg_input {
27575 /* The HWRM command request type. */
27578 * The completion ring to send the completion event on. This should
27579 * be the NQ ID returned from the `nq_alloc` HWRM command.
27581 uint16_t cmpl_ring;
27583 * The sequence ID is used by the driver for tracking multiple
27584 * commands. This ID is treated as opaque data by the firmware and
27585 * the value is returned in the `hwrm_resp_hdr` upon completion.
27589 * The target ID of the command:
27590 * * 0x0-0xFFF8 - The function ID
27591 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
27592 * * 0xFFFD - Reserved for user-space HWRM interface
27595 uint16_t target_id;
27597 * A physical address pointer pointing to a host buffer that the
27598 * command's response data will be written. This can be either a host
27599 * physical address (HPA) or a guest physical address (GPA) and must
27600 * point to a physically contiguous block of memory.
27602 uint64_t resp_addr;
27605 * Enumeration denoting the RX, TX type of the resource.
27606 * This enumeration is used for resources that are similar for both
27607 * TX and RX paths of the chip.
27609 #define HWRM_CFA_METER_INSTANCE_CFG_INPUT_FLAGS_PATH UINT32_C(0x1)
27611 #define HWRM_CFA_METER_INSTANCE_CFG_INPUT_FLAGS_PATH_TX \
27614 #define HWRM_CFA_METER_INSTANCE_CFG_INPUT_FLAGS_PATH_RX \
27616 #define HWRM_CFA_METER_INSTANCE_CFG_INPUT_FLAGS_PATH_LAST \
27617 HWRM_CFA_METER_INSTANCE_CFG_INPUT_FLAGS_PATH_RX
27620 * This value identifies a new meter profile to be associated with
27621 * the meter instance specified in this command.
27623 uint16_t meter_profile_id;
27625 * A value of 0xffff is considered invalid and implies the
27626 * profile is not configured.
27628 #define HWRM_CFA_METER_INSTANCE_CFG_INPUT_METER_PROFILE_ID_INVALID \
27630 #define HWRM_CFA_METER_INSTANCE_CFG_INPUT_METER_PROFILE_ID_LAST \
27631 HWRM_CFA_METER_INSTANCE_CFG_INPUT_METER_PROFILE_ID_INVALID
27633 * This value identifies the ID of a meter instance that needs to be updated with
27634 * a new meter profile specified in this command.
27636 uint16_t meter_instance_id;
27637 uint8_t unused_1[2];
27638 } __attribute__((packed));
27640 /* hwrm_cfa_meter_instance_cfg_output (size:128b/16B) */
27641 struct hwrm_cfa_meter_instance_cfg_output {
27642 /* The specific error status for the command. */
27643 uint16_t error_code;
27644 /* The HWRM command request type. */
27646 /* The sequence ID from the original command. */
27648 /* The length of the response data in number of bytes. */
27650 uint8_t unused_0[7];
27652 * This field is used in Output records to indicate that the output
27653 * is completely written to RAM. This field should be read as '1'
27654 * to indicate that the output has been completely written.
27655 * When writing a command completion or response to an internal processor,
27656 * the order of writes has to be such that this field is written last.
27659 } __attribute__((packed));
27661 /********************************
27662 * hwrm_cfa_meter_instance_free *
27663 ********************************/
27666 /* hwrm_cfa_meter_instance_free_input (size:192b/24B) */
27667 struct hwrm_cfa_meter_instance_free_input {
27668 /* The HWRM command request type. */
27671 * The completion ring to send the completion event on. This should
27672 * be the NQ ID returned from the `nq_alloc` HWRM command.
27674 uint16_t cmpl_ring;
27676 * The sequence ID is used by the driver for tracking multiple
27677 * commands. This ID is treated as opaque data by the firmware and
27678 * the value is returned in the `hwrm_resp_hdr` upon completion.
27682 * The target ID of the command:
27683 * * 0x0-0xFFF8 - The function ID
27684 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
27685 * * 0xFFFD - Reserved for user-space HWRM interface
27688 uint16_t target_id;
27690 * A physical address pointer pointing to a host buffer that the
27691 * command's response data will be written. This can be either a host
27692 * physical address (HPA) or a guest physical address (GPA) and must
27693 * point to a physically contiguous block of memory.
27695 uint64_t resp_addr;
27698 * Enumeration denoting the RX, TX type of the resource.
27699 * This enumeration is used for resources that are similar for both
27700 * TX and RX paths of the chip.
27702 #define HWRM_CFA_METER_INSTANCE_FREE_INPUT_FLAGS_PATH UINT32_C(0x1)
27704 #define HWRM_CFA_METER_INSTANCE_FREE_INPUT_FLAGS_PATH_TX \
27707 #define HWRM_CFA_METER_INSTANCE_FREE_INPUT_FLAGS_PATH_RX \
27709 #define HWRM_CFA_METER_INSTANCE_FREE_INPUT_FLAGS_PATH_LAST \
27710 HWRM_CFA_METER_INSTANCE_FREE_INPUT_FLAGS_PATH_RX
27712 /* This value identifies a meter instance in CFA. */
27713 uint16_t meter_instance_id;
27715 * A value of 0xfff is considered invalid and implies the
27716 * instance is not configured.
27718 #define HWRM_CFA_METER_INSTANCE_FREE_INPUT_METER_INSTANCE_ID_INVALID \
27720 #define HWRM_CFA_METER_INSTANCE_FREE_INPUT_METER_INSTANCE_ID_LAST \
27721 HWRM_CFA_METER_INSTANCE_FREE_INPUT_METER_INSTANCE_ID_INVALID
27722 uint8_t unused_1[4];
27723 } __attribute__((packed));
27725 /* hwrm_cfa_meter_instance_free_output (size:128b/16B) */
27726 struct hwrm_cfa_meter_instance_free_output {
27727 /* The specific error status for the command. */
27728 uint16_t error_code;
27729 /* The HWRM command request type. */
27731 /* The sequence ID from the original command. */
27733 /* The length of the response data in number of bytes. */
27735 uint8_t unused_0[7];
27737 * This field is used in Output records to indicate that the output
27738 * is completely written to RAM. This field should be read as '1'
27739 * to indicate that the output has been completely written.
27740 * When writing a command completion or response to an internal processor,
27741 * the order of writes has to be such that this field is written last.
27744 } __attribute__((packed));
27746 /*******************************
27747 * hwrm_cfa_decap_filter_alloc *
27748 *******************************/
27751 /* hwrm_cfa_decap_filter_alloc_input (size:832b/104B) */
27752 struct hwrm_cfa_decap_filter_alloc_input {
27753 /* The HWRM command request type. */
27756 * The completion ring to send the completion event on. This should
27757 * be the NQ ID returned from the `nq_alloc` HWRM command.
27759 uint16_t cmpl_ring;
27761 * The sequence ID is used by the driver for tracking multiple
27762 * commands. This ID is treated as opaque data by the firmware and
27763 * the value is returned in the `hwrm_resp_hdr` upon completion.
27767 * The target ID of the command:
27768 * * 0x0-0xFFF8 - The function ID
27769 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
27770 * * 0xFFFD - Reserved for user-space HWRM interface
27773 uint16_t target_id;
27775 * A physical address pointer pointing to a host buffer that the
27776 * command's response data will be written. This can be either a host
27777 * physical address (HPA) or a guest physical address (GPA) and must
27778 * point to a physically contiguous block of memory.
27780 uint64_t resp_addr;
27782 /* ovs_tunnel is 1 b */
27783 #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_FLAGS_OVS_TUNNEL \
27787 * This bit must be '1' for the tunnel_type field to be
27790 #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_ENABLES_TUNNEL_TYPE \
27793 * This bit must be '1' for the tunnel_id field to be
27796 #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_ENABLES_TUNNEL_ID \
27799 * This bit must be '1' for the src_macaddr field to be
27802 #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_ENABLES_SRC_MACADDR \
27805 * This bit must be '1' for the dst_macaddr field to be
27808 #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_ENABLES_DST_MACADDR \
27811 * This bit must be '1' for the ovlan_vid field to be
27814 #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_ENABLES_OVLAN_VID \
27817 * This bit must be '1' for the ivlan_vid field to be
27820 #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_ENABLES_IVLAN_VID \
27823 * This bit must be '1' for the t_ovlan_vid field to be
27826 #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_ENABLES_T_OVLAN_VID \
27829 * This bit must be '1' for the t_ivlan_vid field to be
27832 #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_ENABLES_T_IVLAN_VID \
27835 * This bit must be '1' for the ethertype field to be
27838 #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_ENABLES_ETHERTYPE \
27841 * This bit must be '1' for the src_ipaddr field to be
27844 #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_ENABLES_SRC_IPADDR \
27847 * This bit must be '1' for the dst_ipaddr field to be
27850 #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_ENABLES_DST_IPADDR \
27853 * This bit must be '1' for the ipaddr_type field to be
27856 #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_ENABLES_IPADDR_TYPE \
27859 * This bit must be '1' for the ip_protocol field to be
27862 #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_ENABLES_IP_PROTOCOL \
27865 * This bit must be '1' for the src_port field to be
27868 #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_ENABLES_SRC_PORT \
27871 * This bit must be '1' for the dst_port field to be
27874 #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_ENABLES_DST_PORT \
27877 * This bit must be '1' for the dst_id field to be
27880 #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_ENABLES_DST_ID \
27883 * This bit must be '1' for the mirror_vnic_id field to be
27886 #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_ENABLES_MIRROR_VNIC_ID \
27889 * Tunnel identifier.
27890 * Virtual Network Identifier (VNI). Only valid with
27891 * tunnel_types VXLAN, NVGRE, and Geneve.
27892 * Only lower 24-bits of VNI field are used
27893 * in setting up the filter.
27895 uint32_t tunnel_id;
27897 uint8_t tunnel_type;
27899 #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_TUNNEL_TYPE_NONTUNNEL \
27901 /* Virtual eXtensible Local Area Network (VXLAN) */
27902 #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_TUNNEL_TYPE_VXLAN \
27904 /* Network Virtualization Generic Routing Encapsulation (NVGRE) */
27905 #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_TUNNEL_TYPE_NVGRE \
27907 /* Generic Routing Encapsulation (GRE) inside Ethernet payload */
27908 #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_TUNNEL_TYPE_L2GRE \
27911 #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_TUNNEL_TYPE_IPIP \
27913 /* Generic Network Virtualization Encapsulation (Geneve) */
27914 #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_TUNNEL_TYPE_GENEVE \
27916 /* Multi-Protocol Lable Switching (MPLS) */
27917 #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_TUNNEL_TYPE_MPLS \
27919 /* Stateless Transport Tunnel (STT) */
27920 #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_TUNNEL_TYPE_STT \
27922 /* Generic Routing Encapsulation (GRE) inside IP datagram payload */
27923 #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_TUNNEL_TYPE_IPGRE \
27925 /* IPV4 over virtual eXtensible Local Area Network (IPV4oVXLAN) */
27926 #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_TUNNEL_TYPE_VXLAN_V4 \
27928 /* Enhance Generic Routing Encapsulation (GRE version 1) inside IP datagram payload */
27929 #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_TUNNEL_TYPE_IPGRE_V1 \
27931 /* Use fixed layer 2 ether type of 0xFFFF */
27932 #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_TUNNEL_TYPE_L2_ETYPE \
27934 /* IPV6 over virtual eXtensible Local Area Network with GPE header (IPV6oVXLANGPE) */
27935 #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_TUNNEL_TYPE_VXLAN_GPE_V6 \
27937 /* Any tunneled traffic */
27938 #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_TUNNEL_TYPE_ANYTUNNEL \
27940 #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_TUNNEL_TYPE_LAST \
27941 HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_TUNNEL_TYPE_ANYTUNNEL
27945 * This value indicates the source MAC address in
27946 * the Ethernet header.
27948 uint8_t src_macaddr[6];
27949 uint8_t unused_2[2];
27951 * This value indicates the destination MAC address in
27952 * the Ethernet header.
27954 uint8_t dst_macaddr[6];
27956 * This value indicates the VLAN ID of the outer VLAN tag
27957 * in the Ethernet header.
27959 uint16_t ovlan_vid;
27961 * This value indicates the VLAN ID of the inner VLAN tag
27962 * in the Ethernet header.
27964 uint16_t ivlan_vid;
27966 * This value indicates the VLAN ID of the outer VLAN tag
27967 * in the tunnel Ethernet header.
27969 uint16_t t_ovlan_vid;
27971 * This value indicates the VLAN ID of the inner VLAN tag
27972 * in the tunnel Ethernet header.
27974 uint16_t t_ivlan_vid;
27975 /* This value indicates the ethertype in the Ethernet header. */
27976 uint16_t ethertype;
27978 * This value indicates the type of IP address.
27981 * All others are invalid.
27983 uint8_t ip_addr_type;
27985 #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_IP_ADDR_TYPE_UNKNOWN \
27988 #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_IP_ADDR_TYPE_IPV4 \
27991 #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_IP_ADDR_TYPE_IPV6 \
27993 #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_IP_ADDR_TYPE_LAST \
27994 HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_IP_ADDR_TYPE_IPV6
27996 * The value of protocol filed in IP header.
27997 * Applies to UDP and TCP traffic.
28001 uint8_t ip_protocol;
28003 #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_IP_PROTOCOL_UNKNOWN \
28006 #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_IP_PROTOCOL_TCP \
28009 #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_IP_PROTOCOL_UDP \
28011 #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_IP_PROTOCOL_LAST \
28012 HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_IP_PROTOCOL_UDP
28016 * The value of source IP address to be used in filtering.
28017 * For IPv4, first four bytes represent the IP address.
28019 uint32_t src_ipaddr[4];
28021 * The value of destination IP address to be used in filtering.
28022 * For IPv4, first four bytes represent the IP address.
28024 uint32_t dst_ipaddr[4];
28026 * The value of source port to be used in filtering.
28027 * Applies to UDP and TCP traffic.
28031 * The value of destination port to be used in filtering.
28032 * Applies to UDP and TCP traffic.
28036 * If set, this value shall represent the
28037 * Logical VNIC ID of the destination VNIC for the RX
28042 * If set, this value shall represent the L2 context that matches the L2
28043 * information of the decap filter.
28045 uint16_t l2_ctxt_ref_id;
28046 } __attribute__((packed));
28048 /* hwrm_cfa_decap_filter_alloc_output (size:128b/16B) */
28049 struct hwrm_cfa_decap_filter_alloc_output {
28050 /* The specific error status for the command. */
28051 uint16_t error_code;
28052 /* The HWRM command request type. */
28054 /* The sequence ID from the original command. */
28056 /* The length of the response data in number of bytes. */
28058 /* This value is an opaque id into CFA data structures. */
28059 uint32_t decap_filter_id;
28060 uint8_t unused_0[3];
28062 * This field is used in Output records to indicate that the output
28063 * is completely written to RAM. This field should be read as '1'
28064 * to indicate that the output has been completely written.
28065 * When writing a command completion or response to an internal processor,
28066 * the order of writes has to be such that this field is written last.
28069 } __attribute__((packed));
28071 /******************************
28072 * hwrm_cfa_decap_filter_free *
28073 ******************************/
28076 /* hwrm_cfa_decap_filter_free_input (size:192b/24B) */
28077 struct hwrm_cfa_decap_filter_free_input {
28078 /* The HWRM command request type. */
28081 * The completion ring to send the completion event on. This should
28082 * be the NQ ID returned from the `nq_alloc` HWRM command.
28084 uint16_t cmpl_ring;
28086 * The sequence ID is used by the driver for tracking multiple
28087 * commands. This ID is treated as opaque data by the firmware and
28088 * the value is returned in the `hwrm_resp_hdr` upon completion.
28092 * The target ID of the command:
28093 * * 0x0-0xFFF8 - The function ID
28094 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
28095 * * 0xFFFD - Reserved for user-space HWRM interface
28098 uint16_t target_id;
28100 * A physical address pointer pointing to a host buffer that the
28101 * command's response data will be written. This can be either a host
28102 * physical address (HPA) or a guest physical address (GPA) and must
28103 * point to a physically contiguous block of memory.
28105 uint64_t resp_addr;
28106 /* This value is an opaque id into CFA data structures. */
28107 uint32_t decap_filter_id;
28108 uint8_t unused_0[4];
28109 } __attribute__((packed));
28111 /* hwrm_cfa_decap_filter_free_output (size:128b/16B) */
28112 struct hwrm_cfa_decap_filter_free_output {
28113 /* The specific error status for the command. */
28114 uint16_t error_code;
28115 /* The HWRM command request type. */
28117 /* The sequence ID from the original command. */
28119 /* The length of the response data in number of bytes. */
28121 uint8_t unused_0[7];
28123 * This field is used in Output records to indicate that the output
28124 * is completely written to RAM. This field should be read as '1'
28125 * to indicate that the output has been completely written.
28126 * When writing a command completion or response to an internal processor,
28127 * the order of writes has to be such that this field is written last.
28130 } __attribute__((packed));
28132 /***********************
28133 * hwrm_cfa_flow_alloc *
28134 ***********************/
28137 /* hwrm_cfa_flow_alloc_input (size:1024b/128B) */
28138 struct hwrm_cfa_flow_alloc_input {
28139 /* The HWRM command request type. */
28142 * The completion ring to send the completion event on. This should
28143 * be the NQ ID returned from the `nq_alloc` HWRM command.
28145 uint16_t cmpl_ring;
28147 * The sequence ID is used by the driver for tracking multiple
28148 * commands. This ID is treated as opaque data by the firmware and
28149 * the value is returned in the `hwrm_resp_hdr` upon completion.
28153 * The target ID of the command:
28154 * * 0x0-0xFFF8 - The function ID
28155 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
28156 * * 0xFFFD - Reserved for user-space HWRM interface
28159 uint16_t target_id;
28161 * A physical address pointer pointing to a host buffer that the
28162 * command's response data will be written. This can be either a host
28163 * physical address (HPA) or a guest physical address (GPA) and must
28164 * point to a physically contiguous block of memory.
28166 uint64_t resp_addr;
28168 /* tunnel is 1 b */
28169 #define HWRM_CFA_FLOW_ALLOC_INPUT_FLAGS_TUNNEL \
28171 /* num_vlan is 2 b */
28172 #define HWRM_CFA_FLOW_ALLOC_INPUT_FLAGS_NUM_VLAN_MASK \
28174 #define HWRM_CFA_FLOW_ALLOC_INPUT_FLAGS_NUM_VLAN_SFT 1
28176 #define HWRM_CFA_FLOW_ALLOC_INPUT_FLAGS_NUM_VLAN_NONE \
28177 (UINT32_C(0x0) << 1)
28179 #define HWRM_CFA_FLOW_ALLOC_INPUT_FLAGS_NUM_VLAN_ONE \
28180 (UINT32_C(0x1) << 1)
28182 #define HWRM_CFA_FLOW_ALLOC_INPUT_FLAGS_NUM_VLAN_TWO \
28183 (UINT32_C(0x2) << 1)
28184 #define HWRM_CFA_FLOW_ALLOC_INPUT_FLAGS_NUM_VLAN_LAST \
28185 HWRM_CFA_FLOW_ALLOC_INPUT_FLAGS_NUM_VLAN_TWO
28186 /* Enumeration denoting the Flow Type. */
28187 #define HWRM_CFA_FLOW_ALLOC_INPUT_FLAGS_FLOWTYPE_MASK \
28189 #define HWRM_CFA_FLOW_ALLOC_INPUT_FLAGS_FLOWTYPE_SFT 3
28191 #define HWRM_CFA_FLOW_ALLOC_INPUT_FLAGS_FLOWTYPE_L2 \
28192 (UINT32_C(0x0) << 3)
28194 #define HWRM_CFA_FLOW_ALLOC_INPUT_FLAGS_FLOWTYPE_IPV4 \
28195 (UINT32_C(0x1) << 3)
28197 #define HWRM_CFA_FLOW_ALLOC_INPUT_FLAGS_FLOWTYPE_IPV6 \
28198 (UINT32_C(0x2) << 3)
28199 #define HWRM_CFA_FLOW_ALLOC_INPUT_FLAGS_FLOWTYPE_LAST \
28200 HWRM_CFA_FLOW_ALLOC_INPUT_FLAGS_FLOWTYPE_IPV6
28202 * when set to 1, indicates TX flow offload for function specified in src_fid and
28203 * the dst_fid should be set to invalid value. To indicate a VM to VM flow, both
28204 * of the path_tx and path_rx flags need to be set. For virtio vSwitch offload
28205 * case, the src_fid and dst_fid is set to the same fid value. For the SRIOV
28206 * vSwitch offload case, the src_fid and dst_fid must be set to the same VF FID
28207 * belong to the children VFs of the same PF to indicate VM to VM flow.
28209 #define HWRM_CFA_FLOW_ALLOC_INPUT_FLAGS_PATH_TX \
28212 * when set to 1, indicates RX flow offload for function specified in dst_fid and
28213 * the src_fid should be set to invalid value.
28215 #define HWRM_CFA_FLOW_ALLOC_INPUT_FLAGS_PATH_RX \
28218 * Set to 1 to indicate matching of VXLAN VNI from the custom vxlan header is
28219 * required and the VXLAN VNI value is stored in the first 24 bits of the dmac field.
28220 * This flag is only valid when the flow direction is RX.
28222 #define HWRM_CFA_FLOW_ALLOC_INPUT_FLAGS_MATCH_VXLAN_IP_VNI \
28224 /* Set to 1 to indicate vhost_id is specified in the outer_vlan_tci field. */
28225 #define HWRM_CFA_FLOW_ALLOC_INPUT_FLAGS_VHOST_ID_USE_VLAN \
28232 /* Tunnel handle valid when tunnel flag is set. */
28233 uint32_t tunnel_handle;
28234 uint16_t action_flags;
28236 * Setting of this flag indicates drop action. If this flag is not set,
28237 * then it should be considered accept action.
28239 #define HWRM_CFA_FLOW_ALLOC_INPUT_ACTION_FLAGS_FWD \
28241 /* recycle is 1 b */
28242 #define HWRM_CFA_FLOW_ALLOC_INPUT_ACTION_FLAGS_RECYCLE \
28245 * Setting of this flag indicates drop action. If this flag is not set,
28246 * then it should be considered accept action.
28248 #define HWRM_CFA_FLOW_ALLOC_INPUT_ACTION_FLAGS_DROP \
28251 #define HWRM_CFA_FLOW_ALLOC_INPUT_ACTION_FLAGS_METER \
28253 /* tunnel is 1 b */
28254 #define HWRM_CFA_FLOW_ALLOC_INPUT_ACTION_FLAGS_TUNNEL \
28256 /* nat_src is 1 b */
28257 #define HWRM_CFA_FLOW_ALLOC_INPUT_ACTION_FLAGS_NAT_SRC \
28259 /* nat_dest is 1 b */
28260 #define HWRM_CFA_FLOW_ALLOC_INPUT_ACTION_FLAGS_NAT_DEST \
28262 /* nat_ipv4_address is 1 b */
28263 #define HWRM_CFA_FLOW_ALLOC_INPUT_ACTION_FLAGS_NAT_IPV4_ADDRESS \
28265 /* l2_header_rewrite is 1 b */
28266 #define HWRM_CFA_FLOW_ALLOC_INPUT_ACTION_FLAGS_L2_HEADER_REWRITE \
28268 /* ttl_decrement is 1 b */
28269 #define HWRM_CFA_FLOW_ALLOC_INPUT_ACTION_FLAGS_TTL_DECREMENT \
28272 * If set to 1 and flow direction is TX, it indicates decap of L2 header
28273 * and encap of tunnel header. If set to 1 and flow direction is RX, it
28274 * indicates decap of tunnel header and encap L2 header. The type of tunnel
28275 * is specified in the tunnel_type field.
28277 #define HWRM_CFA_FLOW_ALLOC_INPUT_ACTION_FLAGS_TUNNEL_IP \
28279 /* If set to 1, flow aging is enabled for this flow. */
28280 #define HWRM_CFA_FLOW_ALLOC_INPUT_ACTION_FLAGS_FLOW_AGING_ENABLED \
28283 * If set to 1 an attempt will be made to try to offload this flow to the
28284 * most optimal flow table resource. If set to 0, the flow will be
28285 * placed to the default flow table resource.
28287 #define HWRM_CFA_FLOW_ALLOC_INPUT_ACTION_FLAGS_PRI_HINT \
28290 * If set to 1 there will be no attempt to allocate an on-chip try to
28291 * offload this flow. If set to 0, which will keep compatibility with the
28292 * older drivers, will cause the FW to attempt to allocate an on-chip flow
28293 * counter for the newly created flow. This will keep the existing behavior
28294 * with EM flows which always had an associated flow counter.
28296 #define HWRM_CFA_FLOW_ALLOC_INPUT_ACTION_FLAGS_NO_FLOW_COUNTER_ALLOC \
28299 * Tx Flow: pf or vf fid.
28303 /* VLAN tpid, valid when push_vlan flag is set. */
28304 uint16_t l2_rewrite_vlan_tpid;
28305 /* VLAN tci, valid when push_vlan flag is set. */
28306 uint16_t l2_rewrite_vlan_tci;
28307 /* Meter id, valid when meter flag is set. */
28308 uint16_t act_meter_id;
28309 /* Flow with the same l2 context tcam key. */
28310 uint16_t ref_flow_handle;
28311 /* This value sets the match value for the ethertype. */
28312 uint16_t ethertype;
28313 /* valid when num tags is 1 or 2. */
28314 uint16_t outer_vlan_tci;
28315 /* This value sets the match value for the Destination MAC address. */
28317 /* valid when num tags is 2. */
28318 uint16_t inner_vlan_tci;
28319 /* This value sets the match value for the Source MAC address. */
28321 /* The bit length of destination IP address mask. */
28322 uint8_t ip_dst_mask_len;
28323 /* The bit length of source IP address mask. */
28324 uint8_t ip_src_mask_len;
28325 /* The value of destination IPv4/IPv6 address. */
28326 uint32_t ip_dst[4];
28327 /* The source IPv4/IPv6 address. */
28328 uint32_t ip_src[4];
28330 * The value of source port.
28331 * Applies to UDP and TCP traffic.
28333 uint16_t l4_src_port;
28335 * The value of source port mask.
28336 * Applies to UDP and TCP traffic.
28338 uint16_t l4_src_port_mask;
28340 * The value of destination port.
28341 * Applies to UDP and TCP traffic.
28343 uint16_t l4_dst_port;
28345 * The value of destination port mask.
28346 * Applies to UDP and TCP traffic.
28348 uint16_t l4_dst_port_mask;
28350 * NAT IPv4/6 address based on address type flag.
28351 * 0 values are ignored.
28353 uint32_t nat_ip_address[4];
28354 /* L2 header re-write Destination MAC address. */
28355 uint16_t l2_rewrite_dmac[3];
28357 * The NAT source/destination port based on direction flag.
28358 * Applies to UDP and TCP traffic.
28359 * 0 values are ignored.
28362 /* L2 header re-write Source MAC address. */
28363 uint16_t l2_rewrite_smac[3];
28364 /* The value of ip protocol. */
28367 uint8_t tunnel_type;
28369 #define HWRM_CFA_FLOW_ALLOC_INPUT_TUNNEL_TYPE_NONTUNNEL \
28371 /* Virtual eXtensible Local Area Network (VXLAN) */
28372 #define HWRM_CFA_FLOW_ALLOC_INPUT_TUNNEL_TYPE_VXLAN \
28374 /* Network Virtualization Generic Routing Encapsulation (NVGRE) */
28375 #define HWRM_CFA_FLOW_ALLOC_INPUT_TUNNEL_TYPE_NVGRE \
28377 /* Generic Routing Encapsulation (GRE) inside Ethernet payload */
28378 #define HWRM_CFA_FLOW_ALLOC_INPUT_TUNNEL_TYPE_L2GRE \
28381 #define HWRM_CFA_FLOW_ALLOC_INPUT_TUNNEL_TYPE_IPIP \
28383 /* Generic Network Virtualization Encapsulation (Geneve) */
28384 #define HWRM_CFA_FLOW_ALLOC_INPUT_TUNNEL_TYPE_GENEVE \
28386 /* Multi-Protocol Lable Switching (MPLS) */
28387 #define HWRM_CFA_FLOW_ALLOC_INPUT_TUNNEL_TYPE_MPLS \
28389 /* Stateless Transport Tunnel (STT) */
28390 #define HWRM_CFA_FLOW_ALLOC_INPUT_TUNNEL_TYPE_STT \
28392 /* Generic Routing Encapsulation (GRE) inside IP datagram payload */
28393 #define HWRM_CFA_FLOW_ALLOC_INPUT_TUNNEL_TYPE_IPGRE \
28395 /* IPV4 over virtual eXtensible Local Area Network (IPV4oVXLAN) */
28396 #define HWRM_CFA_FLOW_ALLOC_INPUT_TUNNEL_TYPE_VXLAN_V4 \
28398 /* Enhance Generic Routing Encapsulation (GRE version 1) inside IP datagram payload */
28399 #define HWRM_CFA_FLOW_ALLOC_INPUT_TUNNEL_TYPE_IPGRE_V1 \
28401 /* Use fixed layer 2 ether type of 0xFFFF */
28402 #define HWRM_CFA_FLOW_ALLOC_INPUT_TUNNEL_TYPE_L2_ETYPE \
28404 /* IPV6 over virtual eXtensible Local Area Network with GPE header (IPV6oVXLANGPE) */
28405 #define HWRM_CFA_FLOW_ALLOC_INPUT_TUNNEL_TYPE_VXLAN_GPE_V6 \
28407 /* Any tunneled traffic */
28408 #define HWRM_CFA_FLOW_ALLOC_INPUT_TUNNEL_TYPE_ANYTUNNEL \
28410 #define HWRM_CFA_FLOW_ALLOC_INPUT_TUNNEL_TYPE_LAST \
28411 HWRM_CFA_FLOW_ALLOC_INPUT_TUNNEL_TYPE_ANYTUNNEL
28412 } __attribute__((packed));
28414 /* hwrm_cfa_flow_alloc_output (size:256b/32B) */
28415 struct hwrm_cfa_flow_alloc_output {
28416 /* The specific error status for the command. */
28417 uint16_t error_code;
28418 /* The HWRM command request type. */
28420 /* The sequence ID from the original command. */
28422 /* The length of the response data in number of bytes. */
28424 /* Flow record index. */
28425 uint16_t flow_handle;
28426 uint8_t unused_0[2];
28428 * The flow id value in bit 0-29 is the actual ID of the flow
28429 * associated with this filter and it shall be used to match
28430 * and associate the flow identifier returned in completion
28431 * records. A value of 0xFFFFFFFF in the 32-bit flow_id field
28432 * shall indicate no valid flow id.
28435 /* Indicate the flow id value. */
28436 #define HWRM_CFA_FLOW_ALLOC_OUTPUT_FLOW_ID_VALUE_MASK \
28437 UINT32_C(0x3fffffff)
28438 #define HWRM_CFA_FLOW_ALLOC_OUTPUT_FLOW_ID_VALUE_SFT 0
28439 /* Indicate type of the flow. */
28440 #define HWRM_CFA_FLOW_ALLOC_OUTPUT_FLOW_ID_TYPE \
28441 UINT32_C(0x40000000)
28443 * If this bit set to 0, then it indicates that the flow is
28446 #define HWRM_CFA_FLOW_ALLOC_OUTPUT_FLOW_ID_TYPE_INT \
28447 (UINT32_C(0x0) << 30)
28449 * If this bit is set to 1, then it indicates that the flow is
28452 #define HWRM_CFA_FLOW_ALLOC_OUTPUT_FLOW_ID_TYPE_EXT \
28453 (UINT32_C(0x1) << 30)
28454 #define HWRM_CFA_FLOW_ALLOC_OUTPUT_FLOW_ID_TYPE_LAST \
28455 HWRM_CFA_FLOW_ALLOC_OUTPUT_FLOW_ID_TYPE_EXT
28456 /* Indicate the flow direction. */
28457 #define HWRM_CFA_FLOW_ALLOC_OUTPUT_FLOW_ID_DIR \
28458 UINT32_C(0x80000000)
28459 /* If this bit set to 0, then it indicates rx flow. */
28460 #define HWRM_CFA_FLOW_ALLOC_OUTPUT_FLOW_ID_DIR_RX \
28461 (UINT32_C(0x0) << 31)
28462 /* If this bit is set to 1, then it indicates that tx flow. */
28463 #define HWRM_CFA_FLOW_ALLOC_OUTPUT_FLOW_ID_DIR_TX \
28464 (UINT32_C(0x1) << 31)
28465 #define HWRM_CFA_FLOW_ALLOC_OUTPUT_FLOW_ID_DIR_LAST \
28466 HWRM_CFA_FLOW_ALLOC_OUTPUT_FLOW_ID_DIR_TX
28467 /* This value identifies a set of CFA data structures used for a flow. */
28468 uint64_t ext_flow_handle;
28469 uint32_t flow_counter_id;
28470 uint8_t unused_1[3];
28472 * This field is used in Output records to indicate that the output
28473 * is completely written to RAM. This field should be read as '1'
28474 * to indicate that the output has been completely written.
28475 * When writing a command completion or response to an internal processor,
28476 * the order of writes has to be such that this field is written last.
28479 } __attribute__((packed));
28481 /* hwrm_cfa_flow_alloc_cmd_err (size:64b/8B) */
28482 struct hwrm_cfa_flow_alloc_cmd_err {
28484 * command specific error codes that goes to
28485 * the cmd_err field in Common HWRM Error Response.
28488 /* Unknown error */
28489 #define HWRM_CFA_FLOW_ALLOC_CMD_ERR_CODE_UNKNOWN UINT32_C(0x0)
28490 /* No more L2 Context TCAM */
28491 #define HWRM_CFA_FLOW_ALLOC_CMD_ERR_CODE_L2_CONTEXT_TCAM UINT32_C(0x1)
28492 /* No more action records */
28493 #define HWRM_CFA_FLOW_ALLOC_CMD_ERR_CODE_ACTION_RECORD UINT32_C(0x2)
28494 /* No more flow counters */
28495 #define HWRM_CFA_FLOW_ALLOC_CMD_ERR_CODE_FLOW_COUNTER UINT32_C(0x3)
28496 /* No more wild-card TCAM */
28497 #define HWRM_CFA_FLOW_ALLOC_CMD_ERR_CODE_WILD_CARD_TCAM UINT32_C(0x4)
28498 /* Hash collsion in exact match tables */
28499 #define HWRM_CFA_FLOW_ALLOC_CMD_ERR_CODE_HASH_COLLISION UINT32_C(0x5)
28500 /* Key is already installed */
28501 #define HWRM_CFA_FLOW_ALLOC_CMD_ERR_CODE_KEY_EXISTS UINT32_C(0x6)
28502 /* Flow Context DB is out of resource */
28503 #define HWRM_CFA_FLOW_ALLOC_CMD_ERR_CODE_FLOW_CTXT_DB UINT32_C(0x7)
28504 #define HWRM_CFA_FLOW_ALLOC_CMD_ERR_CODE_LAST \
28505 HWRM_CFA_FLOW_ALLOC_CMD_ERR_CODE_FLOW_CTXT_DB
28506 uint8_t unused_0[7];
28507 } __attribute__((packed));
28509 /**********************
28510 * hwrm_cfa_flow_free *
28511 **********************/
28514 /* hwrm_cfa_flow_free_input (size:256b/32B) */
28515 struct hwrm_cfa_flow_free_input {
28516 /* The HWRM command request type. */
28519 * The completion ring to send the completion event on. This should
28520 * be the NQ ID returned from the `nq_alloc` HWRM command.
28522 uint16_t cmpl_ring;
28524 * The sequence ID is used by the driver for tracking multiple
28525 * commands. This ID is treated as opaque data by the firmware and
28526 * the value is returned in the `hwrm_resp_hdr` upon completion.
28530 * The target ID of the command:
28531 * * 0x0-0xFFF8 - The function ID
28532 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
28533 * * 0xFFFD - Reserved for user-space HWRM interface
28536 uint16_t target_id;
28538 * A physical address pointer pointing to a host buffer that the
28539 * command's response data will be written. This can be either a host
28540 * physical address (HPA) or a guest physical address (GPA) and must
28541 * point to a physically contiguous block of memory.
28543 uint64_t resp_addr;
28544 /* Flow record index. */
28545 uint16_t flow_handle;
28547 /* Flow counter id to be freed. */
28548 uint32_t flow_counter_id;
28549 /* This value identifies a set of CFA data structures used for a flow. */
28550 uint64_t ext_flow_handle;
28551 } __attribute__((packed));
28553 /* hwrm_cfa_flow_free_output (size:256b/32B) */
28554 struct hwrm_cfa_flow_free_output {
28555 /* The specific error status for the command. */
28556 uint16_t error_code;
28557 /* The HWRM command request type. */
28559 /* The sequence ID from the original command. */
28561 /* The length of the response data in number of bytes. */
28563 /* packet is 64 b */
28567 uint8_t unused_0[7];
28569 * This field is used in Output records to indicate that the output
28570 * is completely written to RAM. This field should be read as '1'
28571 * to indicate that the output has been completely written.
28572 * When writing a command completion or response to an internal processor,
28573 * the order of writes has to be such that this field is written last.
28576 } __attribute__((packed));
28578 /* hwrm_cfa_flow_action_data (size:960b/120B) */
28579 struct hwrm_cfa_flow_action_data {
28580 uint16_t action_flags;
28581 /* Setting of this flag indicates accept action. */
28582 #define HWRM_CFA_FLOW_ACTION_DATA_ACTION_FLAGS_FWD \
28584 /* Setting of this flag indicates recycle action. */
28585 #define HWRM_CFA_FLOW_ACTION_DATA_ACTION_FLAGS_RECYCLE \
28587 /* Setting of this flag indicates drop action. */
28588 #define HWRM_CFA_FLOW_ACTION_DATA_ACTION_FLAGS_DROP \
28590 /* Setting of this flag indicates meter action. */
28591 #define HWRM_CFA_FLOW_ACTION_DATA_ACTION_FLAGS_METER \
28593 /* Setting of this flag indicates tunnel action. */
28594 #define HWRM_CFA_FLOW_ACTION_DATA_ACTION_FLAGS_TUNNEL \
28597 * If set to 1 and flow direction is TX, it indicates decap of L2 header
28598 * and encap of tunnel header. If set to 1 and flow direction is RX, it
28599 * indicates decap of tunnel header and encap L2 header.
28601 #define HWRM_CFA_FLOW_ACTION_DATA_ACTION_FLAGS_TUNNEL_IP \
28603 /* Setting of this flag indicates ttl decrement action. */
28604 #define HWRM_CFA_FLOW_ACTION_DATA_ACTION_FLAGS_TTL_DECREMENT \
28606 /* If set to 1, flow aging is enabled for this flow. */
28607 #define HWRM_CFA_FLOW_ACTION_DATA_ACTION_FLAGS_FLOW_AGING_ENABLED \
28609 /* Setting of this flag indicates encap action.. */
28610 #define HWRM_CFA_FLOW_ACTION_DATA_ACTION_FLAGS_ENCAP \
28612 /* Setting of this flag indicates decap action.. */
28613 #define HWRM_CFA_FLOW_ACTION_DATA_ACTION_FLAGS_DECAP \
28616 uint16_t act_meter_id;
28619 /* vport number. */
28621 /* The NAT source/destination. */
28623 uint16_t unused_0[3];
28624 /* NAT IPv4/IPv6 address. */
28625 uint32_t nat_ip_address[4];
28626 /* Encapsulation Type. */
28627 uint8_t encap_type;
28628 /* Virtual eXtensible Local Area Network (VXLAN) */
28629 #define HWRM_CFA_FLOW_ACTION_DATA_ENCAP_TYPE_VXLAN UINT32_C(0x1)
28630 /* Network Virtualization Generic Routing Encapsulation (NVGRE) */
28631 #define HWRM_CFA_FLOW_ACTION_DATA_ENCAP_TYPE_NVGRE UINT32_C(0x2)
28632 /* Generic Routing Encapsulation (GRE) after inside Ethernet payload */
28633 #define HWRM_CFA_FLOW_ACTION_DATA_ENCAP_TYPE_L2GRE UINT32_C(0x3)
28635 #define HWRM_CFA_FLOW_ACTION_DATA_ENCAP_TYPE_IPIP UINT32_C(0x4)
28636 /* Generic Network Virtualization Encapsulation (Geneve) */
28637 #define HWRM_CFA_FLOW_ACTION_DATA_ENCAP_TYPE_GENEVE UINT32_C(0x5)
28638 /* Multi-Protocol Lable Switching (MPLS) */
28639 #define HWRM_CFA_FLOW_ACTION_DATA_ENCAP_TYPE_MPLS UINT32_C(0x6)
28641 #define HWRM_CFA_FLOW_ACTION_DATA_ENCAP_TYPE_VLAN UINT32_C(0x7)
28642 /* Generic Routing Encapsulation (GRE) inside IP datagram payload */
28643 #define HWRM_CFA_FLOW_ACTION_DATA_ENCAP_TYPE_IPGRE UINT32_C(0x8)
28644 /* IPV4 over virtual eXtensible Local Area Network (IPV4oVXLAN) */
28645 #define HWRM_CFA_FLOW_ACTION_DATA_ENCAP_TYPE_VXLAN_V4 UINT32_C(0x9)
28646 /* Enhance Generic Routing Encapsulation (GRE version 1) inside IP datagram payload */
28647 #define HWRM_CFA_FLOW_ACTION_DATA_ENCAP_TYPE_IPGRE_V1 UINT32_C(0xa)
28648 /* Use fixed layer 2 ether type of 0xFFFF */
28649 #define HWRM_CFA_FLOW_ACTION_DATA_ENCAP_TYPE_L2_ETYPE UINT32_C(0xb)
28650 /* IPV6 over virtual eXtensible Local Area Network with GPE header (IPV6oVXLANGPE) */
28651 #define HWRM_CFA_FLOW_ACTION_DATA_ENCAP_TYPE_VXLAN_GPE_V6 UINT32_C(0xc)
28652 #define HWRM_CFA_FLOW_ACTION_DATA_ENCAP_TYPE_LAST \
28653 HWRM_CFA_FLOW_ACTION_DATA_ENCAP_TYPE_VXLAN_GPE_V6
28655 /* This value is encap data for the associated encap type. */
28656 uint32_t encap_data[20];
28657 } __attribute__((packed));
28659 /* hwrm_cfa_flow_tunnel_hdr_data (size:64b/8B) */
28660 struct hwrm_cfa_flow_tunnel_hdr_data {
28662 uint8_t tunnel_type;
28664 #define HWRM_CFA_FLOW_TUNNEL_HDR_DATA_TUNNEL_TYPE_NONTUNNEL \
28666 /* Virtual eXtensible Local Area Network (VXLAN) */
28667 #define HWRM_CFA_FLOW_TUNNEL_HDR_DATA_TUNNEL_TYPE_VXLAN \
28669 /* Network Virtualization Generic Routing Encapsulation (NVGRE) */
28670 #define HWRM_CFA_FLOW_TUNNEL_HDR_DATA_TUNNEL_TYPE_NVGRE \
28672 /* Generic Routing Encapsulation (GRE) inside Ethernet payload */
28673 #define HWRM_CFA_FLOW_TUNNEL_HDR_DATA_TUNNEL_TYPE_L2GRE \
28676 #define HWRM_CFA_FLOW_TUNNEL_HDR_DATA_TUNNEL_TYPE_IPIP \
28678 /* Generic Network Virtualization Encapsulation (Geneve) */
28679 #define HWRM_CFA_FLOW_TUNNEL_HDR_DATA_TUNNEL_TYPE_GENEVE \
28681 /* Multi-Protocol Lable Switching (MPLS) */
28682 #define HWRM_CFA_FLOW_TUNNEL_HDR_DATA_TUNNEL_TYPE_MPLS \
28684 /* Stateless Transport Tunnel (STT) */
28685 #define HWRM_CFA_FLOW_TUNNEL_HDR_DATA_TUNNEL_TYPE_STT \
28687 /* Generic Routing Encapsulation (GRE) inside IP datagram payload */
28688 #define HWRM_CFA_FLOW_TUNNEL_HDR_DATA_TUNNEL_TYPE_IPGRE \
28690 /* IPV4 over virtual eXtensible Local Area Network (IPV4oVXLAN) */
28691 #define HWRM_CFA_FLOW_TUNNEL_HDR_DATA_TUNNEL_TYPE_VXLAN_V4 \
28693 /* Enhance Generic Routing Encapsulation (GRE version 1) inside IP datagram payload */
28694 #define HWRM_CFA_FLOW_TUNNEL_HDR_DATA_TUNNEL_TYPE_IPGRE_V1 \
28696 /* Use fixed layer 2 ether type of 0xFFFF */
28697 #define HWRM_CFA_FLOW_TUNNEL_HDR_DATA_TUNNEL_TYPE_L2_ETYPE \
28699 /* IPV6 over virtual eXtensible Local Area Network with GPE header (IPV6oVXLANGPE) */
28700 #define HWRM_CFA_FLOW_TUNNEL_HDR_DATA_TUNNEL_TYPE_VXLAN_GPE_V6 \
28702 /* Any tunneled traffic */
28703 #define HWRM_CFA_FLOW_TUNNEL_HDR_DATA_TUNNEL_TYPE_ANYTUNNEL \
28705 #define HWRM_CFA_FLOW_TUNNEL_HDR_DATA_TUNNEL_TYPE_LAST \
28706 HWRM_CFA_FLOW_TUNNEL_HDR_DATA_TUNNEL_TYPE_ANYTUNNEL
28709 * Tunnel identifier.
28710 * Virtual Network Identifier (VNI).
28712 uint32_t tunnel_id;
28713 } __attribute__((packed));
28715 /* hwrm_cfa_flow_l4_key_data (size:64b/8B) */
28716 struct hwrm_cfa_flow_l4_key_data {
28717 /* The value of source port. */
28718 uint16_t l4_src_port;
28719 /* The value of destination port. */
28720 uint16_t l4_dst_port;
28722 } __attribute__((packed));
28724 /* hwrm_cfa_flow_l3_key_data (size:512b/64B) */
28725 struct hwrm_cfa_flow_l3_key_data {
28726 /* The value of ip protocol. */
28727 uint8_t ip_protocol;
28728 uint8_t unused_0[7];
28729 /* The value of destination IPv4/IPv6 address. */
28730 uint32_t ip_dst[4];
28731 /* The source IPv4/IPv6 address. */
28732 uint32_t ip_src[4];
28733 /* NAT IPv4/IPv6 address. */
28734 uint32_t nat_ip_address[4];
28735 uint32_t unused[2];
28736 } __attribute__((packed));
28738 /* hwrm_cfa_flow_l2_key_data (size:448b/56B) */
28739 struct hwrm_cfa_flow_l2_key_data {
28740 /* Destination MAC address. */
28743 /* Source MAC address. */
28746 /* L2 header re-write Destination MAC address. */
28747 uint16_t l2_rewrite_dmac[3];
28749 /* L2 header re-write Source MAC address. */
28750 uint16_t l2_rewrite_smac[3];
28752 uint16_t ethertype;
28753 /* Number of VLAN tags. */
28754 uint16_t num_vlan_tags;
28756 uint16_t l2_rewrite_vlan_tpid;
28758 uint16_t l2_rewrite_vlan_tci;
28759 uint8_t unused_3[2];
28760 /* Outer VLAN TPID. */
28761 uint16_t ovlan_tpid;
28762 /* Outer VLAN TCI. */
28763 uint16_t ovlan_tci;
28764 /* Inner VLAN TPID. */
28765 uint16_t ivlan_tpid;
28766 /* Inner VLAN TCI. */
28767 uint16_t ivlan_tci;
28769 } __attribute__((packed));
28771 /* hwrm_cfa_flow_key_data (size:4160b/520B) */
28772 struct hwrm_cfa_flow_key_data {
28773 /* Flow associated tunnel L2 header key info. */
28774 uint32_t t_l2_key_data[14];
28775 /* Flow associated tunnel L2 header mask info. */
28776 uint32_t t_l2_key_mask[14];
28777 /* Flow associated tunnel L3 header key info. */
28778 uint32_t t_l3_key_data[16];
28779 /* Flow associated tunnel L3 header mask info. */
28780 uint32_t t_l3_key_mask[16];
28781 /* Flow associated tunnel L4 header key info. */
28782 uint32_t t_l4_key_data[2];
28783 /* Flow associated tunnel L4 header mask info. */
28784 uint32_t t_l4_key_mask[2];
28785 /* Flow associated tunnel header info. */
28786 uint32_t tunnel_hdr[2];
28787 /* Flow associated L2 header key info. */
28788 uint32_t l2_key_data[14];
28789 /* Flow associated L2 header mask info. */
28790 uint32_t l2_key_mask[14];
28791 /* Flow associated L3 header key info. */
28792 uint32_t l3_key_data[16];
28793 /* Flow associated L3 header mask info. */
28794 uint32_t l3_key_mask[16];
28795 /* Flow associated L4 header key info. */
28796 uint32_t l4_key_data[2];
28797 /* Flow associated L4 header mask info. */
28798 uint32_t l4_key_mask[2];
28799 } __attribute__((packed));
28801 /**********************
28802 * hwrm_cfa_flow_info *
28803 **********************/
28806 /* hwrm_cfa_flow_info_input (size:256b/32B) */
28807 struct hwrm_cfa_flow_info_input {
28808 /* The HWRM command request type. */
28811 * The completion ring to send the completion event on. This should
28812 * be the NQ ID returned from the `nq_alloc` HWRM command.
28814 uint16_t cmpl_ring;
28816 * The sequence ID is used by the driver for tracking multiple
28817 * commands. This ID is treated as opaque data by the firmware and
28818 * the value is returned in the `hwrm_resp_hdr` upon completion.
28822 * The target ID of the command:
28823 * * 0x0-0xFFF8 - The function ID
28824 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
28825 * * 0xFFFD - Reserved for user-space HWRM interface
28828 uint16_t target_id;
28830 * A physical address pointer pointing to a host buffer that the
28831 * command's response data will be written. This can be either a host
28832 * physical address (HPA) or a guest physical address (GPA) and must
28833 * point to a physically contiguous block of memory.
28835 uint64_t resp_addr;
28836 /* Flow record index. */
28837 uint16_t flow_handle;
28838 /* Max flow handle */
28839 #define HWRM_CFA_FLOW_INFO_INPUT_FLOW_HANDLE_MAX_MASK \
28841 #define HWRM_CFA_FLOW_INFO_INPUT_FLOW_HANDLE_MAX_SFT 0
28842 /* CNP flow handle */
28843 #define HWRM_CFA_FLOW_INFO_INPUT_FLOW_HANDLE_CNP_CNT \
28845 /* RoCEv1 flow handle */
28846 #define HWRM_CFA_FLOW_INFO_INPUT_FLOW_HANDLE_ROCEV1_CNT \
28848 /* RoCEv2 flow handle */
28849 #define HWRM_CFA_FLOW_INFO_INPUT_FLOW_HANDLE_ROCEV2_CNT \
28851 /* Direction rx = 1 */
28852 #define HWRM_CFA_FLOW_INFO_INPUT_FLOW_HANDLE_DIR_RX \
28854 uint8_t unused_0[6];
28855 /* This value identifies a set of CFA data structures used for a flow. */
28856 uint64_t ext_flow_handle;
28857 } __attribute__((packed));
28859 /* hwrm_cfa_flow_info_output (size:5632b/704B) */
28860 struct hwrm_cfa_flow_info_output {
28861 /* The specific error status for the command. */
28862 uint16_t error_code;
28863 /* The HWRM command request type. */
28865 /* The sequence ID from the original command. */
28867 /* The length of the response data in number of bytes. */
28870 /* When set to 1, indicates the configuration is the TX flow. */
28871 #define HWRM_CFA_FLOW_INFO_OUTPUT_FLAGS_PATH_TX UINT32_C(0x1)
28872 /* When set to 1, indicates the configuration is the RX flow. */
28873 #define HWRM_CFA_FLOW_INFO_OUTPUT_FLAGS_PATH_RX UINT32_C(0x2)
28874 /* profile is 8 b */
28876 /* src_fid is 16 b */
28878 /* dst_fid is 16 b */
28880 /* l2_ctxt_id is 16 b */
28881 uint16_t l2_ctxt_id;
28882 /* em_info is 64 b */
28884 /* tcam_info is 64 b */
28885 uint64_t tcam_info;
28886 /* vfp_tcam_info is 64 b */
28887 uint64_t vfp_tcam_info;
28888 /* ar_id is 16 b */
28890 /* flow_handle is 16 b */
28891 uint16_t flow_handle;
28892 /* tunnel_handle is 32 b */
28893 uint32_t tunnel_handle;
28894 /* The flow aging timer for the flow, the unit is 100 milliseconds */
28895 uint16_t flow_timer;
28896 uint8_t unused_0[6];
28897 /* Flow associated L2, L3 and L4 headers info. */
28898 uint32_t flow_key_data[130];
28899 /* Flow associated action record info. */
28900 uint32_t flow_action_info[30];
28901 uint8_t unused_1[7];
28903 * This field is used in Output records to indicate that the output
28904 * is completely written to RAM. This field should be read as '1'
28905 * to indicate that the output has been completely written.
28906 * When writing a command completion or response to an internal processor,
28907 * the order of writes has to be such that this field is written last.
28910 } __attribute__((packed));
28912 /***********************
28913 * hwrm_cfa_flow_flush *
28914 ***********************/
28917 /* hwrm_cfa_flow_flush_input (size:256b/32B) */
28918 struct hwrm_cfa_flow_flush_input {
28919 /* The HWRM command request type. */
28922 * The completion ring to send the completion event on. This should
28923 * be the NQ ID returned from the `nq_alloc` HWRM command.
28925 uint16_t cmpl_ring;
28927 * The sequence ID is used by the driver for tracking multiple
28928 * commands. This ID is treated as opaque data by the firmware and
28929 * the value is returned in the `hwrm_resp_hdr` upon completion.
28933 * The target ID of the command:
28934 * * 0x0-0xFFF8 - The function ID
28935 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
28936 * * 0xFFFD - Reserved for user-space HWRM interface
28939 uint16_t target_id;
28941 * A physical address pointer pointing to a host buffer that the
28942 * command's response data will be written. This can be either a host
28943 * physical address (HPA) or a guest physical address (GPA) and must
28944 * point to a physically contiguous block of memory.
28946 uint64_t resp_addr;
28947 /* flags is 32 b */
28950 * Set to 1 to indicate the page size, page layers, and flow_handle_table_dma_addr
28951 * fields are valid. The flow flush operation should only flush the flows from the
28952 * flow table specified. This flag is set to 0 by older driver. For older firmware,
28953 * setting this flag has no effect.
28955 #define HWRM_CFA_FLOW_FLUSH_INPUT_FLAGS_FLOW_TABLE_VALID \
28958 * Set to 1 to indicate flow flush operation to cleanup all the flows, meters, CFA
28959 * context memory tables..etc. This flag is set to 0 by older driver. For older firmware,
28960 * setting this flag has no effect.
28962 #define HWRM_CFA_FLOW_FLUSH_INPUT_FLAGS_FLOW_RESET_ALL \
28965 * Set to 1 to indicate flow flush operation to cleanup all the flows by the caller.
28966 * This flag is set to 0 by older driver. For older firmware, setting this flag has no effect.
28968 #define HWRM_CFA_FLOW_FLUSH_INPUT_FLAGS_FLOW_RESET_PORT \
28970 /* Set to 1 to indicate the flow counter IDs are included in the flow table. */
28971 #define HWRM_CFA_FLOW_FLUSH_INPUT_FLAGS_FLOW_HANDLE_INCL_FC \
28972 UINT32_C(0x8000000)
28974 * This specifies the size of flow handle entries provided by the driver
28975 * in the flow table specified below. Only two flow handle size enums are defined.
28977 #define HWRM_CFA_FLOW_FLUSH_INPUT_FLAGS_FLOW_HANDLE_ENTRY_SIZE_MASK \
28978 UINT32_C(0xc0000000)
28979 #define HWRM_CFA_FLOW_FLUSH_INPUT_FLAGS_FLOW_HANDLE_ENTRY_SIZE_SFT \
28981 /* The flow handle is 16bit */
28982 #define HWRM_CFA_FLOW_FLUSH_INPUT_FLAGS_FLOW_HANDLE_ENTRY_SIZE_FLOW_HND_16BIT \
28983 (UINT32_C(0x0) << 30)
28984 /* The flow handle is 64bit */
28985 #define HWRM_CFA_FLOW_FLUSH_INPUT_FLAGS_FLOW_HANDLE_ENTRY_SIZE_FLOW_HND_64BIT \
28986 (UINT32_C(0x1) << 30)
28987 #define HWRM_CFA_FLOW_FLUSH_INPUT_FLAGS_FLOW_HANDLE_ENTRY_SIZE_LAST \
28988 HWRM_CFA_FLOW_FLUSH_INPUT_FLAGS_FLOW_HANDLE_ENTRY_SIZE_FLOW_HND_64BIT
28989 /* Specify page size of the flow table memory. */
28991 /* The page size is 4K */
28992 #define HWRM_CFA_FLOW_FLUSH_INPUT_PAGE_SIZE_4K UINT32_C(0x0)
28993 /* The page size is 8K */
28994 #define HWRM_CFA_FLOW_FLUSH_INPUT_PAGE_SIZE_8K UINT32_C(0x1)
28995 /* The page size is 64K */
28996 #define HWRM_CFA_FLOW_FLUSH_INPUT_PAGE_SIZE_64K UINT32_C(0x4)
28997 /* The page size is 256K */
28998 #define HWRM_CFA_FLOW_FLUSH_INPUT_PAGE_SIZE_256K UINT32_C(0x6)
28999 /* The page size is 1M */
29000 #define HWRM_CFA_FLOW_FLUSH_INPUT_PAGE_SIZE_1M UINT32_C(0x8)
29001 /* The page size is 2M */
29002 #define HWRM_CFA_FLOW_FLUSH_INPUT_PAGE_SIZE_2M UINT32_C(0x9)
29003 /* The page size is 4M */
29004 #define HWRM_CFA_FLOW_FLUSH_INPUT_PAGE_SIZE_4M UINT32_C(0xa)
29005 /* The page size is 1G */
29006 #define HWRM_CFA_FLOW_FLUSH_INPUT_PAGE_SIZE_1G UINT32_C(0x12)
29007 #define HWRM_CFA_FLOW_FLUSH_INPUT_PAGE_SIZE_LAST \
29008 HWRM_CFA_FLOW_FLUSH_INPUT_PAGE_SIZE_1G
29009 /* FLow table memory indirect levels. */
29010 uint8_t page_level;
29011 /* PBL pointer is physical start address. */
29012 #define HWRM_CFA_FLOW_FLUSH_INPUT_PAGE_LEVEL_LVL_0 UINT32_C(0x0)
29013 /* PBL pointer points to PTE table. */
29014 #define HWRM_CFA_FLOW_FLUSH_INPUT_PAGE_LEVEL_LVL_1 UINT32_C(0x1)
29015 /* PBL pointer points to PDE table with each entry pointing to PTE tables. */
29016 #define HWRM_CFA_FLOW_FLUSH_INPUT_PAGE_LEVEL_LVL_2 UINT32_C(0x2)
29017 #define HWRM_CFA_FLOW_FLUSH_INPUT_PAGE_LEVEL_LAST \
29018 HWRM_CFA_FLOW_FLUSH_INPUT_PAGE_LEVEL_LVL_2
29019 /* number of flows in the flow table */
29020 uint16_t num_flows;
29021 /* Pointer to the PBL, or PDL depending on number of levels */
29023 } __attribute__((packed));
29025 /* hwrm_cfa_flow_flush_output (size:128b/16B) */
29026 struct hwrm_cfa_flow_flush_output {
29027 /* The specific error status for the command. */
29028 uint16_t error_code;
29029 /* The HWRM command request type. */
29031 /* The sequence ID from the original command. */
29033 /* The length of the response data in number of bytes. */
29035 uint8_t unused_0[7];
29037 * This field is used in Output records to indicate that the output
29038 * is completely written to RAM. This field should be read as '1'
29039 * to indicate that the output has been completely written.
29040 * When writing a command completion or response to an internal processor,
29041 * the order of writes has to be such that this field is written last.
29044 } __attribute__((packed));
29046 /***********************
29047 * hwrm_cfa_flow_stats *
29048 ***********************/
29051 /* hwrm_cfa_flow_stats_input (size:640b/80B) */
29052 struct hwrm_cfa_flow_stats_input {
29053 /* The HWRM command request type. */
29056 * The completion ring to send the completion event on. This should
29057 * be the NQ ID returned from the `nq_alloc` HWRM command.
29059 uint16_t cmpl_ring;
29061 * The sequence ID is used by the driver for tracking multiple
29062 * commands. This ID is treated as opaque data by the firmware and
29063 * the value is returned in the `hwrm_resp_hdr` upon completion.
29067 * The target ID of the command:
29068 * * 0x0-0xFFF8 - The function ID
29069 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
29070 * * 0xFFFD - Reserved for user-space HWRM interface
29073 uint16_t target_id;
29075 * A physical address pointer pointing to a host buffer that the
29076 * command's response data will be written. This can be either a host
29077 * physical address (HPA) or a guest physical address (GPA) and must
29078 * point to a physically contiguous block of memory.
29080 uint64_t resp_addr;
29082 uint16_t num_flows;
29084 uint16_t flow_handle_0;
29086 uint16_t flow_handle_1;
29088 uint16_t flow_handle_2;
29090 uint16_t flow_handle_3;
29092 uint16_t flow_handle_4;
29094 uint16_t flow_handle_5;
29096 uint16_t flow_handle_6;
29098 uint16_t flow_handle_7;
29100 uint16_t flow_handle_8;
29102 uint16_t flow_handle_9;
29103 uint8_t unused_0[2];
29104 /* Flow ID of a flow. */
29105 uint32_t flow_id_0;
29106 /* Flow ID of a flow. */
29107 uint32_t flow_id_1;
29108 /* Flow ID of a flow. */
29109 uint32_t flow_id_2;
29110 /* Flow ID of a flow. */
29111 uint32_t flow_id_3;
29112 /* Flow ID of a flow. */
29113 uint32_t flow_id_4;
29114 /* Flow ID of a flow. */
29115 uint32_t flow_id_5;
29116 /* Flow ID of a flow. */
29117 uint32_t flow_id_6;
29118 /* Flow ID of a flow. */
29119 uint32_t flow_id_7;
29120 /* Flow ID of a flow. */
29121 uint32_t flow_id_8;
29122 /* Flow ID of a flow. */
29123 uint32_t flow_id_9;
29124 } __attribute__((packed));
29126 /* hwrm_cfa_flow_stats_output (size:1408b/176B) */
29127 struct hwrm_cfa_flow_stats_output {
29128 /* The specific error status for the command. */
29129 uint16_t error_code;
29130 /* The HWRM command request type. */
29132 /* The sequence ID from the original command. */
29134 /* The length of the response data in number of bytes. */
29136 /* packet_0 is 64 b */
29138 /* packet_1 is 64 b */
29140 /* packet_2 is 64 b */
29142 /* packet_3 is 64 b */
29144 /* packet_4 is 64 b */
29146 /* packet_5 is 64 b */
29148 /* packet_6 is 64 b */
29150 /* packet_7 is 64 b */
29152 /* packet_8 is 64 b */
29154 /* packet_9 is 64 b */
29156 /* byte_0 is 64 b */
29158 /* byte_1 is 64 b */
29160 /* byte_2 is 64 b */
29162 /* byte_3 is 64 b */
29164 /* byte_4 is 64 b */
29166 /* byte_5 is 64 b */
29168 /* byte_6 is 64 b */
29170 /* byte_7 is 64 b */
29172 /* byte_8 is 64 b */
29174 /* byte_9 is 64 b */
29176 uint8_t unused_0[7];
29178 * This field is used in Output records to indicate that the output
29179 * is completely written to RAM. This field should be read as '1'
29180 * to indicate that the output has been completely written.
29181 * When writing a command completion or response to an internal processor,
29182 * the order of writes has to be such that this field is written last.
29185 } __attribute__((packed));
29187 /***********************************
29188 * hwrm_cfa_flow_aging_timer_reset *
29189 ***********************************/
29192 /* hwrm_cfa_flow_aging_timer_reset_input (size:256b/32B) */
29193 struct hwrm_cfa_flow_aging_timer_reset_input {
29194 /* The HWRM command request type. */
29197 * The completion ring to send the completion event on. This should
29198 * be the NQ ID returned from the `nq_alloc` HWRM command.
29200 uint16_t cmpl_ring;
29202 * The sequence ID is used by the driver for tracking multiple
29203 * commands. This ID is treated as opaque data by the firmware and
29204 * the value is returned in the `hwrm_resp_hdr` upon completion.
29208 * The target ID of the command:
29209 * * 0x0-0xFFF8 - The function ID
29210 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
29211 * * 0xFFFD - Reserved for user-space HWRM interface
29214 uint16_t target_id;
29216 * A physical address pointer pointing to a host buffer that the
29217 * command's response data will be written. This can be either a host
29218 * physical address (HPA) or a guest physical address (GPA) and must
29219 * point to a physically contiguous block of memory.
29221 uint64_t resp_addr;
29222 /* Flow record index. */
29223 uint16_t flow_handle;
29224 uint8_t unused_0[2];
29226 * New flow timer value for the flow specified in the ext_flow_handle.
29227 * The flow timer unit is 100ms.
29229 uint32_t flow_timer;
29230 /* This value identifies a set of CFA data structures used for a flow. */
29231 uint64_t ext_flow_handle;
29232 } __attribute__((packed));
29234 /* hwrm_cfa_flow_aging_timer_reset_output (size:128b/16B) */
29235 struct hwrm_cfa_flow_aging_timer_reset_output {
29236 /* The specific error status for the command. */
29237 uint16_t error_code;
29238 /* The HWRM command request type. */
29240 /* The sequence ID from the original command. */
29242 /* The length of the response data in number of bytes. */
29244 uint8_t unused_0[7];
29246 * This field is used in Output records to indicate that the output
29247 * is completely written to RAM. This field should be read as '1'
29248 * to indicate that the output has been completely written.
29249 * When writing a command completion or response to an internal processor,
29250 * the order of writes has to be such that this field is written last.
29253 } __attribute__((packed));
29255 /***************************
29256 * hwrm_cfa_flow_aging_cfg *
29257 ***************************/
29260 /* hwrm_cfa_flow_aging_cfg_input (size:384b/48B) */
29261 struct hwrm_cfa_flow_aging_cfg_input {
29262 /* The HWRM command request type. */
29265 * The completion ring to send the completion event on. This should
29266 * be the NQ ID returned from the `nq_alloc` HWRM command.
29268 uint16_t cmpl_ring;
29270 * The sequence ID is used by the driver for tracking multiple
29271 * commands. This ID is treated as opaque data by the firmware and
29272 * the value is returned in the `hwrm_resp_hdr` upon completion.
29276 * The target ID of the command:
29277 * * 0x0-0xFFF8 - The function ID
29278 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
29279 * * 0xFFFD - Reserved for user-space HWRM interface
29282 uint16_t target_id;
29284 * A physical address pointer pointing to a host buffer that the
29285 * command's response data will be written. This can be either a host
29286 * physical address (HPA) or a guest physical address (GPA) and must
29287 * point to a physically contiguous block of memory.
29289 uint64_t resp_addr;
29290 /* The bit field to enable per flow aging configuration. */
29292 /* This bit must be '1' for the tcp flow timer field to be configured */
29293 #define HWRM_CFA_FLOW_AGING_CFG_INPUT_ENABLES_TCP_FLOW_TIMER \
29295 /* This bit must be '1' for the tcp finish timer field to be configured */
29296 #define HWRM_CFA_FLOW_AGING_CFG_INPUT_ENABLES_TCP_FIN_TIMER \
29298 /* This bit must be '1' for the udp flow timer field to be configured */
29299 #define HWRM_CFA_FLOW_AGING_CFG_INPUT_ENABLES_UDP_FLOW_TIMER \
29301 /* This bit must be '1' for the eem dma interval field to be configured */
29302 #define HWRM_CFA_FLOW_AGING_CFG_INPUT_ENABLES_EEM_DMA_INTERVAL \
29304 /* This bit must be '1' for the eem notice interval field to be configured */
29305 #define HWRM_CFA_FLOW_AGING_CFG_INPUT_ENABLES_EEM_NOTICE_INTERVAL \
29307 /* This bit must be '1' for the eem context memory maximum entries field to be configured */
29308 #define HWRM_CFA_FLOW_AGING_CFG_INPUT_ENABLES_EEM_CTX_MAX_ENTRIES \
29310 /* This bit must be '1' for the eem context memory ID field to be configured */
29311 #define HWRM_CFA_FLOW_AGING_CFG_INPUT_ENABLES_EEM_CTX_ID \
29313 /* This bit must be '1' for the eem context memory type field to be configured */
29314 #define HWRM_CFA_FLOW_AGING_CFG_INPUT_ENABLES_EEM_CTX_MEM_TYPE \
29317 /* Enumeration denoting the RX, TX type of the resource. */
29318 #define HWRM_CFA_FLOW_AGING_CFG_INPUT_FLAGS_PATH UINT32_C(0x1)
29320 #define HWRM_CFA_FLOW_AGING_CFG_INPUT_FLAGS_PATH_TX UINT32_C(0x0)
29322 #define HWRM_CFA_FLOW_AGING_CFG_INPUT_FLAGS_PATH_RX UINT32_C(0x1)
29323 #define HWRM_CFA_FLOW_AGING_CFG_INPUT_FLAGS_PATH_LAST \
29324 HWRM_CFA_FLOW_AGING_CFG_INPUT_FLAGS_PATH_RX
29325 /* Enumeration denoting the enable, disable eem flow aging configuration. */
29326 #define HWRM_CFA_FLOW_AGING_CFG_INPUT_FLAGS_EEM UINT32_C(0x2)
29328 #define HWRM_CFA_FLOW_AGING_CFG_INPUT_FLAGS_EEM_DISABLE \
29329 (UINT32_C(0x0) << 1)
29331 #define HWRM_CFA_FLOW_AGING_CFG_INPUT_FLAGS_EEM_ENABLE \
29332 (UINT32_C(0x1) << 1)
29333 #define HWRM_CFA_FLOW_AGING_CFG_INPUT_FLAGS_EEM_LAST \
29334 HWRM_CFA_FLOW_AGING_CFG_INPUT_FLAGS_EEM_ENABLE
29336 /* The flow aging timer for all TCP flows, the unit is 100 milliseconds. */
29337 uint32_t tcp_flow_timer;
29338 /* The TCP finished timer for all TCP flows, the unit is 100 milliseconds. */
29339 uint32_t tcp_fin_timer;
29340 /* The flow aging timer for all UDP flows, the unit is 100 milliseconds. */
29341 uint32_t udp_flow_timer;
29342 /* The interval to dma eem ejection data to host memory, the unit is milliseconds. */
29343 uint16_t eem_dma_interval;
29344 /* The interval to notify driver to read the eem ejection data, the unit is milliseconds. */
29345 uint16_t eem_notice_interval;
29346 /* The maximum entries number in the eem context memory. */
29347 uint32_t eem_ctx_max_entries;
29348 /* The context memory ID for eem flow aging. */
29349 uint16_t eem_ctx_id;
29350 uint16_t eem_ctx_mem_type;
29351 /* The content of context memory is eem ejection data, the size of each entry is 4 bytes. */
29352 #define HWRM_CFA_FLOW_AGING_CFG_INPUT_EEM_CTX_MEM_TYPE_EJECTION_DATA \
29354 #define HWRM_CFA_FLOW_AGING_CFG_INPUT_EEM_CTX_MEM_TYPE_LAST \
29355 HWRM_CFA_FLOW_AGING_CFG_INPUT_EEM_CTX_MEM_TYPE_EJECTION_DATA
29356 uint8_t unused_1[4];
29357 } __attribute__((packed));
29359 /* hwrm_cfa_flow_aging_cfg_output (size:128b/16B) */
29360 struct hwrm_cfa_flow_aging_cfg_output {
29361 /* The specific error status for the command. */
29362 uint16_t error_code;
29363 /* The HWRM command request type. */
29365 /* The sequence ID from the original command. */
29367 /* The length of the response data in number of bytes. */
29369 uint8_t unused_0[7];
29371 * This field is used in Output records to indicate that the output
29372 * is completely written to RAM. This field should be read as '1'
29373 * to indicate that the output has been completely written.
29374 * When writing a command completion or response to an internal processor,
29375 * the order of writes has to be such that this field is written last.
29378 } __attribute__((packed));
29380 /****************************
29381 * hwrm_cfa_flow_aging_qcfg *
29382 ****************************/
29385 /* hwrm_cfa_flow_aging_qcfg_input (size:192b/24B) */
29386 struct hwrm_cfa_flow_aging_qcfg_input {
29387 /* The HWRM command request type. */
29390 * The completion ring to send the completion event on. This should
29391 * be the NQ ID returned from the `nq_alloc` HWRM command.
29393 uint16_t cmpl_ring;
29395 * The sequence ID is used by the driver for tracking multiple
29396 * commands. This ID is treated as opaque data by the firmware and
29397 * the value is returned in the `hwrm_resp_hdr` upon completion.
29401 * The target ID of the command:
29402 * * 0x0-0xFFF8 - The function ID
29403 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
29404 * * 0xFFFD - Reserved for user-space HWRM interface
29407 uint16_t target_id;
29409 * A physical address pointer pointing to a host buffer that the
29410 * command's response data will be written. This can be either a host
29411 * physical address (HPA) or a guest physical address (GPA) and must
29412 * point to a physically contiguous block of memory.
29414 uint64_t resp_addr;
29415 /* The direction for the flow aging configuration, 1 is rx path, 2 is tx path. */
29417 /* Enumeration denoting the RX, TX type of the resource. */
29418 #define HWRM_CFA_FLOW_AGING_QCFG_INPUT_FLAGS_PATH UINT32_C(0x1)
29420 #define HWRM_CFA_FLOW_AGING_QCFG_INPUT_FLAGS_PATH_TX UINT32_C(0x0)
29422 #define HWRM_CFA_FLOW_AGING_QCFG_INPUT_FLAGS_PATH_RX UINT32_C(0x1)
29423 #define HWRM_CFA_FLOW_AGING_QCFG_INPUT_FLAGS_PATH_LAST \
29424 HWRM_CFA_FLOW_AGING_QCFG_INPUT_FLAGS_PATH_RX
29425 uint8_t unused_0[7];
29426 } __attribute__((packed));
29428 /* hwrm_cfa_flow_aging_qcfg_output (size:320b/40B) */
29429 struct hwrm_cfa_flow_aging_qcfg_output {
29430 /* The specific error status for the command. */
29431 uint16_t error_code;
29432 /* The HWRM command request type. */
29434 /* The sequence ID from the original command. */
29436 /* The length of the response data in number of bytes. */
29438 /* The current flow aging timer for all TCP flows, the unit is 100 millisecond. */
29439 uint32_t tcp_flow_timer;
29440 /* The current TCP finished timer for all TCP flows, the unit is 100 millisecond. */
29441 uint32_t tcp_fin_timer;
29442 /* The current flow aging timer for all UDP flows, the unit is 100 millisecond. */
29443 uint32_t udp_flow_timer;
29444 /* The interval to dma eem ejection data to host memory, the unit is milliseconds. */
29445 uint16_t eem_dma_interval;
29446 /* The interval to notify driver to read the eem ejection data, the unit is milliseconds. */
29447 uint16_t eem_notice_interval;
29448 /* The maximum entries number in the eem context memory. */
29449 uint32_t eem_ctx_max_entries;
29450 /* The context memory ID for eem flow aging. */
29451 uint16_t eem_ctx_id;
29452 /* The context memory type for eem flow aging. */
29453 uint16_t eem_ctx_mem_type;
29454 uint8_t unused_0[7];
29456 * This field is used in Output records to indicate that the output
29457 * is completely written to RAM. This field should be read as '1'
29458 * to indicate that the output has been completely written.
29459 * When writing a command completion or response to an internal processor,
29460 * the order of writes has to be such that this field is written last.
29463 } __attribute__((packed));
29465 /*****************************
29466 * hwrm_cfa_flow_aging_qcaps *
29467 *****************************/
29470 /* hwrm_cfa_flow_aging_qcaps_input (size:192b/24B) */
29471 struct hwrm_cfa_flow_aging_qcaps_input {
29472 /* The HWRM command request type. */
29475 * The completion ring to send the completion event on. This should
29476 * be the NQ ID returned from the `nq_alloc` HWRM command.
29478 uint16_t cmpl_ring;
29480 * The sequence ID is used by the driver for tracking multiple
29481 * commands. This ID is treated as opaque data by the firmware and
29482 * the value is returned in the `hwrm_resp_hdr` upon completion.
29486 * The target ID of the command:
29487 * * 0x0-0xFFF8 - The function ID
29488 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
29489 * * 0xFFFD - Reserved for user-space HWRM interface
29492 uint16_t target_id;
29494 * A physical address pointer pointing to a host buffer that the
29495 * command's response data will be written. This can be either a host
29496 * physical address (HPA) or a guest physical address (GPA) and must
29497 * point to a physically contiguous block of memory.
29499 uint64_t resp_addr;
29500 /* The direction for the flow aging configuration, 1 is rx path, 2 is tx path. */
29502 /* Enumeration denoting the RX, TX type of the resource. */
29503 #define HWRM_CFA_FLOW_AGING_QCAPS_INPUT_FLAGS_PATH UINT32_C(0x1)
29505 #define HWRM_CFA_FLOW_AGING_QCAPS_INPUT_FLAGS_PATH_TX UINT32_C(0x0)
29507 #define HWRM_CFA_FLOW_AGING_QCAPS_INPUT_FLAGS_PATH_RX UINT32_C(0x1)
29508 #define HWRM_CFA_FLOW_AGING_QCAPS_INPUT_FLAGS_PATH_LAST \
29509 HWRM_CFA_FLOW_AGING_QCAPS_INPUT_FLAGS_PATH_RX
29510 uint8_t unused_0[7];
29511 } __attribute__((packed));
29513 /* hwrm_cfa_flow_aging_qcaps_output (size:256b/32B) */
29514 struct hwrm_cfa_flow_aging_qcaps_output {
29515 /* The specific error status for the command. */
29516 uint16_t error_code;
29517 /* The HWRM command request type. */
29519 /* The sequence ID from the original command. */
29521 /* The length of the response data in number of bytes. */
29523 /* The maximum flow aging timer for all TCP flows, the unit is 100 millisecond. */
29524 uint32_t max_tcp_flow_timer;
29525 /* The maximum TCP finished timer for all TCP flows, the unit is 100 millisecond. */
29526 uint32_t max_tcp_fin_timer;
29527 /* The maximum flow aging timer for all UDP flows, the unit is 100 millisecond. */
29528 uint32_t max_udp_flow_timer;
29529 /* The maximum aging flows that HW can support. */
29530 uint32_t max_aging_flows;
29531 uint8_t unused_0[7];
29533 * This field is used in Output records to indicate that the output
29534 * is completely written to RAM. This field should be read as '1'
29535 * to indicate that the output has been completely written.
29536 * When writing a command completion or response to an internal processor,
29537 * the order of writes has to be such that this field is written last.
29540 } __attribute__((packed));
29542 /**********************************
29543 * hwrm_cfa_tcp_flag_process_qcfg *
29544 **********************************/
29547 /* hwrm_cfa_tcp_flag_process_qcfg_input (size:128b/16B) */
29548 struct hwrm_cfa_tcp_flag_process_qcfg_input {
29549 /* The HWRM command request type. */
29552 * The completion ring to send the completion event on. This should
29553 * be the NQ ID returned from the `nq_alloc` HWRM command.
29555 uint16_t cmpl_ring;
29557 * The sequence ID is used by the driver for tracking multiple
29558 * commands. This ID is treated as opaque data by the firmware and
29559 * the value is returned in the `hwrm_resp_hdr` upon completion.
29563 * The target ID of the command:
29564 * * 0x0-0xFFF8 - The function ID
29565 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
29566 * * 0xFFFD - Reserved for user-space HWRM interface
29569 uint16_t target_id;
29571 * A physical address pointer pointing to a host buffer that the
29572 * command's response data will be written. This can be either a host
29573 * physical address (HPA) or a guest physical address (GPA) and must
29574 * point to a physically contiguous block of memory.
29576 uint64_t resp_addr;
29577 } __attribute__((packed));
29579 /* hwrm_cfa_tcp_flag_process_qcfg_output (size:192b/24B) */
29580 struct hwrm_cfa_tcp_flag_process_qcfg_output {
29581 /* The specific error status for the command. */
29582 uint16_t error_code;
29583 /* The HWRM command request type. */
29585 /* The sequence ID from the original command. */
29587 /* The length of the response data in number of bytes. */
29589 /* The port 0 RX mirror action record ID. */
29590 uint16_t rx_ar_id_port0;
29591 /* The port 1 RX mirror action record ID. */
29592 uint16_t rx_ar_id_port1;
29593 /* The port 0 RX action record ID for TX TCP flag packets from loopback path. */
29594 uint16_t tx_ar_id_port0;
29595 /* The port 1 RX action record ID for TX TCP flag packets from loopback path. */
29596 uint16_t tx_ar_id_port1;
29597 uint8_t unused_0[7];
29599 * This field is used in Output records to indicate that the output
29600 * is completely written to RAM. This field should be read as '1'
29601 * to indicate that the output has been completely written.
29602 * When writing a command completion or response to an internal processor,
29603 * the order of writes has to be such that this field is written last.
29606 } __attribute__((packed));
29608 /**********************
29609 * hwrm_cfa_pair_info *
29610 **********************/
29613 /* hwrm_cfa_pair_info_input (size:448b/56B) */
29614 struct hwrm_cfa_pair_info_input {
29615 /* The HWRM command request type. */
29618 * The completion ring to send the completion event on. This should
29619 * be the NQ ID returned from the `nq_alloc` HWRM command.
29621 uint16_t cmpl_ring;
29623 * The sequence ID is used by the driver for tracking multiple
29624 * commands. This ID is treated as opaque data by the firmware and
29625 * the value is returned in the `hwrm_resp_hdr` upon completion.
29629 * The target ID of the command:
29630 * * 0x0-0xFFF8 - The function ID
29631 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
29632 * * 0xFFFD - Reserved for user-space HWRM interface
29635 uint16_t target_id;
29637 * A physical address pointer pointing to a host buffer that the
29638 * command's response data will be written. This can be either a host
29639 * physical address (HPA) or a guest physical address (GPA) and must
29640 * point to a physically contiguous block of memory.
29642 uint64_t resp_addr;
29644 /* If this flag is set, lookup by name else lookup by index. */
29645 #define HWRM_CFA_PAIR_INFO_INPUT_FLAGS_LOOKUP_TYPE UINT32_C(0x1)
29646 /* If this flag is set, lookup by PF id and VF id. */
29647 #define HWRM_CFA_PAIR_INFO_INPUT_FLAGS_LOOKUP_REPRE UINT32_C(0x2)
29648 /* Pair table index. */
29649 uint16_t pair_index;
29650 /* Pair pf index. */
29652 /* Pair vf index. */
29654 /* Pair name (32 byte string). */
29655 char pair_name[32];
29656 } __attribute__((packed));
29658 /* hwrm_cfa_pair_info_output (size:576b/72B) */
29659 struct hwrm_cfa_pair_info_output {
29660 /* The specific error status for the command. */
29661 uint16_t error_code;
29662 /* The HWRM command request type. */
29664 /* The sequence ID from the original command. */
29666 /* The length of the response data in number of bytes. */
29668 /* Pair table index. */
29669 uint16_t next_pair_index;
29670 /* Pair member a's fid. */
29672 /* Logical host number. */
29673 uint8_t host_a_index;
29674 /* Logical PF number. */
29675 uint8_t pf_a_index;
29676 /* Pair member a's Linux logical VF number. */
29677 uint16_t vf_a_index;
29679 uint16_t rx_cfa_code_a;
29680 /* Tx CFA action. */
29681 uint16_t tx_cfa_action_a;
29682 /* Pair member b's fid. */
29684 /* Logical host number. */
29685 uint8_t host_b_index;
29686 /* Logical PF number. */
29687 uint8_t pf_b_index;
29688 /* Pair member a's Linux logical VF number. */
29689 uint16_t vf_b_index;
29691 uint16_t rx_cfa_code_b;
29692 /* Tx CFA action. */
29693 uint16_t tx_cfa_action_b;
29694 /* Pair mode (0-vf2fn, 1-rep2fn, 2-rep2rep, 3-proxy, 4-pfpair). */
29696 /* Pair between VF on local host with PF or VF on specified host. */
29697 #define HWRM_CFA_PAIR_INFO_OUTPUT_PAIR_MODE_VF2FN UINT32_C(0x0)
29698 /* Pair between REP on local host with PF or VF on specified host. */
29699 #define HWRM_CFA_PAIR_INFO_OUTPUT_PAIR_MODE_REP2FN UINT32_C(0x1)
29700 /* Pair between REP on local host with REP on specified host. */
29701 #define HWRM_CFA_PAIR_INFO_OUTPUT_PAIR_MODE_REP2REP UINT32_C(0x2)
29702 /* Pair for the proxy interface. */
29703 #define HWRM_CFA_PAIR_INFO_OUTPUT_PAIR_MODE_PROXY UINT32_C(0x3)
29704 /* Pair for the PF interface. */
29705 #define HWRM_CFA_PAIR_INFO_OUTPUT_PAIR_MODE_PFPAIR UINT32_C(0x4)
29706 #define HWRM_CFA_PAIR_INFO_OUTPUT_PAIR_MODE_LAST \
29707 HWRM_CFA_PAIR_INFO_OUTPUT_PAIR_MODE_PFPAIR
29709 uint8_t pair_state;
29710 /* Pair has been allocated */
29711 #define HWRM_CFA_PAIR_INFO_OUTPUT_PAIR_STATE_ALLOCATED UINT32_C(0x1)
29712 /* Both pair members are active */
29713 #define HWRM_CFA_PAIR_INFO_OUTPUT_PAIR_STATE_ACTIVE UINT32_C(0x2)
29714 #define HWRM_CFA_PAIR_INFO_OUTPUT_PAIR_STATE_LAST \
29715 HWRM_CFA_PAIR_INFO_OUTPUT_PAIR_STATE_ACTIVE
29716 /* Pair name (32 byte string). */
29717 char pair_name[32];
29718 uint8_t unused_0[7];
29720 * This field is used in Output records to indicate that the output
29721 * is completely written to RAM. This field should be read as '1'
29722 * to indicate that the output has been completely written.
29723 * When writing a command completion or response to an internal processor,
29724 * the order of writes has to be such that this field is written last.
29727 } __attribute__((packed));
29729 /***************************************
29730 * hwrm_cfa_redirect_query_tunnel_type *
29731 ***************************************/
29734 /* hwrm_cfa_redirect_query_tunnel_type_input (size:192b/24B) */
29735 struct hwrm_cfa_redirect_query_tunnel_type_input {
29736 /* The HWRM command request type. */
29739 * The completion ring to send the completion event on. This should
29740 * be the NQ ID returned from the `nq_alloc` HWRM command.
29742 uint16_t cmpl_ring;
29744 * The sequence ID is used by the driver for tracking multiple
29745 * commands. This ID is treated as opaque data by the firmware and
29746 * the value is returned in the `hwrm_resp_hdr` upon completion.
29750 * The target ID of the command:
29751 * * 0x0-0xFFF8 - The function ID
29752 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
29753 * * 0xFFFD - Reserved for user-space HWRM interface
29756 uint16_t target_id;
29758 * A physical address pointer pointing to a host buffer that the
29759 * command's response data will be written. This can be either a host
29760 * physical address (HPA) or a guest physical address (GPA) and must
29761 * point to a physically contiguous block of memory.
29763 uint64_t resp_addr;
29764 /* The source function id. */
29766 uint8_t unused_0[6];
29767 } __attribute__((packed));
29769 /* hwrm_cfa_redirect_query_tunnel_type_output (size:128b/16B) */
29770 struct hwrm_cfa_redirect_query_tunnel_type_output {
29771 /* The specific error status for the command. */
29772 uint16_t error_code;
29773 /* The HWRM command request type. */
29775 /* The sequence ID from the original command. */
29777 /* The length of the response data in number of bytes. */
29780 uint32_t tunnel_mask;
29782 #define HWRM_CFA_REDIRECT_QUERY_TUNNEL_TYPE_OUTPUT_TUNNEL_MASK_NONTUNNEL \
29784 /* Virtual eXtensible Local Area Network (VXLAN) */
29785 #define HWRM_CFA_REDIRECT_QUERY_TUNNEL_TYPE_OUTPUT_TUNNEL_MASK_VXLAN \
29787 /* Network Virtualization Generic Routing Encapsulation (NVGRE) */
29788 #define HWRM_CFA_REDIRECT_QUERY_TUNNEL_TYPE_OUTPUT_TUNNEL_MASK_NVGRE \
29790 /* Generic Routing Encapsulation (GRE) inside Ethernet payload */
29791 #define HWRM_CFA_REDIRECT_QUERY_TUNNEL_TYPE_OUTPUT_TUNNEL_MASK_L2GRE \
29794 #define HWRM_CFA_REDIRECT_QUERY_TUNNEL_TYPE_OUTPUT_TUNNEL_MASK_IPIP \
29796 /* Generic Network Virtualization Encapsulation (Geneve) */
29797 #define HWRM_CFA_REDIRECT_QUERY_TUNNEL_TYPE_OUTPUT_TUNNEL_MASK_GENEVE \
29799 /* Multi-Protocol Lable Switching (MPLS) */
29800 #define HWRM_CFA_REDIRECT_QUERY_TUNNEL_TYPE_OUTPUT_TUNNEL_MASK_MPLS \
29802 /* Stateless Transport Tunnel (STT) */
29803 #define HWRM_CFA_REDIRECT_QUERY_TUNNEL_TYPE_OUTPUT_TUNNEL_MASK_STT \
29805 /* Generic Routing Encapsulation (GRE) inside IP datagram payload */
29806 #define HWRM_CFA_REDIRECT_QUERY_TUNNEL_TYPE_OUTPUT_TUNNEL_MASK_IPGRE \
29808 /* IPV4 over virtual eXtensible Local Area Network (IPV4oVXLAN) */
29809 #define HWRM_CFA_REDIRECT_QUERY_TUNNEL_TYPE_OUTPUT_TUNNEL_MASK_VXLAN_V4 \
29811 /* Enhance Generic Routing Encapsulation (GRE version 1) inside IP datagram payload */
29812 #define HWRM_CFA_REDIRECT_QUERY_TUNNEL_TYPE_OUTPUT_TUNNEL_MASK_IPGRE_V1 \
29814 /* Any tunneled traffic */
29815 #define HWRM_CFA_REDIRECT_QUERY_TUNNEL_TYPE_OUTPUT_TUNNEL_MASK_ANYTUNNEL \
29817 /* Use fixed layer 2 ether type of 0xFFFF */
29818 #define HWRM_CFA_REDIRECT_QUERY_TUNNEL_TYPE_OUTPUT_TUNNEL_MASK_L2_ETYPE \
29820 /* IPV6 over virtual eXtensible Local Area Network with GPE header (IPV6oVXLANGPE) */
29821 #define HWRM_CFA_REDIRECT_QUERY_TUNNEL_TYPE_OUTPUT_TUNNEL_MASK_VXLAN_GPE_V6 \
29823 uint8_t unused_0[3];
29825 * This field is used in Output records to indicate that the output
29826 * is completely written to RAM. This field should be read as '1'
29827 * to indicate that the output has been completely written.
29828 * When writing a command completion or response to an internal processor,
29829 * the order of writes has to be such that this field is written last.
29832 } __attribute__((packed));
29834 /*************************
29835 * hwrm_cfa_ctx_mem_rgtr *
29836 *************************/
29839 /* hwrm_cfa_ctx_mem_rgtr_input (size:256b/32B) */
29840 struct hwrm_cfa_ctx_mem_rgtr_input {
29841 /* The HWRM command request type. */
29844 * The completion ring to send the completion event on. This should
29845 * be the NQ ID returned from the `nq_alloc` HWRM command.
29847 uint16_t cmpl_ring;
29849 * The sequence ID is used by the driver for tracking multiple
29850 * commands. This ID is treated as opaque data by the firmware and
29851 * the value is returned in the `hwrm_resp_hdr` upon completion.
29855 * The target ID of the command:
29856 * * 0x0-0xFFF8 - The function ID
29857 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
29858 * * 0xFFFD - Reserved for user-space HWRM interface
29861 uint16_t target_id;
29863 * A physical address pointer pointing to a host buffer that the
29864 * command's response data will be written. This can be either a host
29865 * physical address (HPA) or a guest physical address (GPA) and must
29866 * point to a physically contiguous block of memory.
29868 uint64_t resp_addr;
29870 /* Counter PBL indirect levels. */
29871 uint8_t page_level;
29872 /* PBL pointer is physical start address. */
29873 #define HWRM_CFA_CTX_MEM_RGTR_INPUT_PAGE_LEVEL_LVL_0 UINT32_C(0x0)
29874 /* PBL pointer points to PTE table. */
29875 #define HWRM_CFA_CTX_MEM_RGTR_INPUT_PAGE_LEVEL_LVL_1 UINT32_C(0x1)
29876 /* PBL pointer points to PDE table with each entry pointing to PTE tables. */
29877 #define HWRM_CFA_CTX_MEM_RGTR_INPUT_PAGE_LEVEL_LVL_2 UINT32_C(0x2)
29878 #define HWRM_CFA_CTX_MEM_RGTR_INPUT_PAGE_LEVEL_LAST \
29879 HWRM_CFA_CTX_MEM_RGTR_INPUT_PAGE_LEVEL_LVL_2
29882 /* 4KB page size. */
29883 #define HWRM_CFA_CTX_MEM_RGTR_INPUT_PAGE_SIZE_4K UINT32_C(0x0)
29884 /* 8KB page size. */
29885 #define HWRM_CFA_CTX_MEM_RGTR_INPUT_PAGE_SIZE_8K UINT32_C(0x1)
29886 /* 64KB page size. */
29887 #define HWRM_CFA_CTX_MEM_RGTR_INPUT_PAGE_SIZE_64K UINT32_C(0x4)
29888 /* 256KB page size. */
29889 #define HWRM_CFA_CTX_MEM_RGTR_INPUT_PAGE_SIZE_256K UINT32_C(0x6)
29890 /* 1MB page size. */
29891 #define HWRM_CFA_CTX_MEM_RGTR_INPUT_PAGE_SIZE_1M UINT32_C(0x8)
29892 /* 2MB page size. */
29893 #define HWRM_CFA_CTX_MEM_RGTR_INPUT_PAGE_SIZE_2M UINT32_C(0x9)
29894 /* 4MB page size. */
29895 #define HWRM_CFA_CTX_MEM_RGTR_INPUT_PAGE_SIZE_4M UINT32_C(0xa)
29896 /* 1GB page size. */
29897 #define HWRM_CFA_CTX_MEM_RGTR_INPUT_PAGE_SIZE_1G UINT32_C(0x12)
29898 #define HWRM_CFA_CTX_MEM_RGTR_INPUT_PAGE_SIZE_LAST \
29899 HWRM_CFA_CTX_MEM_RGTR_INPUT_PAGE_SIZE_1G
29901 /* Pointer to the PBL, or PDL depending on number of levels */
29903 } __attribute__((packed));
29905 /* hwrm_cfa_ctx_mem_rgtr_output (size:128b/16B) */
29906 struct hwrm_cfa_ctx_mem_rgtr_output {
29907 /* The specific error status for the command. */
29908 uint16_t error_code;
29909 /* The HWRM command request type. */
29911 /* The sequence ID from the original command. */
29913 /* The length of the response data in number of bytes. */
29916 * Id/Handle to the recently register context memory. This handle is passed
29917 * to the CFA feature.
29920 uint8_t unused_0[5];
29922 * This field is used in Output records to indicate that the output
29923 * is completely written to RAM. This field should be read as '1'
29924 * to indicate that the output has been completely written.
29925 * When writing a command completion or response to an internal processor,
29926 * the order of writes has to be such that this field is written last.
29929 } __attribute__((packed));
29931 /***************************
29932 * hwrm_cfa_ctx_mem_unrgtr *
29933 ***************************/
29936 /* hwrm_cfa_ctx_mem_unrgtr_input (size:192b/24B) */
29937 struct hwrm_cfa_ctx_mem_unrgtr_input {
29938 /* The HWRM command request type. */
29941 * The completion ring to send the completion event on. This should
29942 * be the NQ ID returned from the `nq_alloc` HWRM command.
29944 uint16_t cmpl_ring;
29946 * The sequence ID is used by the driver for tracking multiple
29947 * commands. This ID is treated as opaque data by the firmware and
29948 * the value is returned in the `hwrm_resp_hdr` upon completion.
29952 * The target ID of the command:
29953 * * 0x0-0xFFF8 - The function ID
29954 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
29955 * * 0xFFFD - Reserved for user-space HWRM interface
29958 uint16_t target_id;
29960 * A physical address pointer pointing to a host buffer that the
29961 * command's response data will be written. This can be either a host
29962 * physical address (HPA) or a guest physical address (GPA) and must
29963 * point to a physically contiguous block of memory.
29965 uint64_t resp_addr;
29967 * Id/Handle to the recently register context memory. This handle is passed
29968 * to the CFA feature.
29971 uint8_t unused_0[6];
29972 } __attribute__((packed));
29974 /* hwrm_cfa_ctx_mem_unrgtr_output (size:128b/16B) */
29975 struct hwrm_cfa_ctx_mem_unrgtr_output {
29976 /* The specific error status for the command. */
29977 uint16_t error_code;
29978 /* The HWRM command request type. */
29980 /* The sequence ID from the original command. */
29982 /* The length of the response data in number of bytes. */
29984 uint8_t unused_0[7];
29986 * This field is used in Output records to indicate that the output
29987 * is completely written to RAM. This field should be read as '1'
29988 * to indicate that the output has been completely written.
29989 * When writing a command completion or response to an internal processor,
29990 * the order of writes has to be such that this field is written last.
29993 } __attribute__((packed));
29995 /*************************
29996 * hwrm_cfa_ctx_mem_qctx *
29997 *************************/
30000 /* hwrm_cfa_ctx_mem_qctx_input (size:192b/24B) */
30001 struct hwrm_cfa_ctx_mem_qctx_input {
30002 /* The HWRM command request type. */
30005 * The completion ring to send the completion event on. This should
30006 * be the NQ ID returned from the `nq_alloc` HWRM command.
30008 uint16_t cmpl_ring;
30010 * The sequence ID is used by the driver for tracking multiple
30011 * commands. This ID is treated as opaque data by the firmware and
30012 * the value is returned in the `hwrm_resp_hdr` upon completion.
30016 * The target ID of the command:
30017 * * 0x0-0xFFF8 - The function ID
30018 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
30019 * * 0xFFFD - Reserved for user-space HWRM interface
30022 uint16_t target_id;
30024 * A physical address pointer pointing to a host buffer that the
30025 * command's response data will be written. This can be either a host
30026 * physical address (HPA) or a guest physical address (GPA) and must
30027 * point to a physically contiguous block of memory.
30029 uint64_t resp_addr;
30031 * Id/Handle to the recently register context memory. This handle is passed
30032 * to the CFA feature.
30035 uint8_t unused_0[6];
30036 } __attribute__((packed));
30038 /* hwrm_cfa_ctx_mem_qctx_output (size:256b/32B) */
30039 struct hwrm_cfa_ctx_mem_qctx_output {
30040 /* The specific error status for the command. */
30041 uint16_t error_code;
30042 /* The HWRM command request type. */
30044 /* The sequence ID from the original command. */
30046 /* The length of the response data in number of bytes. */
30049 /* Counter PBL indirect levels. */
30050 uint8_t page_level;
30051 /* PBL pointer is physical start address. */
30052 #define HWRM_CFA_CTX_MEM_QCTX_OUTPUT_PAGE_LEVEL_LVL_0 UINT32_C(0x0)
30053 /* PBL pointer points to PTE table. */
30054 #define HWRM_CFA_CTX_MEM_QCTX_OUTPUT_PAGE_LEVEL_LVL_1 UINT32_C(0x1)
30055 /* PBL pointer points to PDE table with each entry pointing to PTE tables. */
30056 #define HWRM_CFA_CTX_MEM_QCTX_OUTPUT_PAGE_LEVEL_LVL_2 UINT32_C(0x2)
30057 #define HWRM_CFA_CTX_MEM_QCTX_OUTPUT_PAGE_LEVEL_LAST \
30058 HWRM_CFA_CTX_MEM_QCTX_OUTPUT_PAGE_LEVEL_LVL_2
30061 /* 4KB page size. */
30062 #define HWRM_CFA_CTX_MEM_QCTX_OUTPUT_PAGE_SIZE_4K UINT32_C(0x0)
30063 /* 8KB page size. */
30064 #define HWRM_CFA_CTX_MEM_QCTX_OUTPUT_PAGE_SIZE_8K UINT32_C(0x1)
30065 /* 64KB page size. */
30066 #define HWRM_CFA_CTX_MEM_QCTX_OUTPUT_PAGE_SIZE_64K UINT32_C(0x4)
30067 /* 256KB page size. */
30068 #define HWRM_CFA_CTX_MEM_QCTX_OUTPUT_PAGE_SIZE_256K UINT32_C(0x6)
30069 /* 1MB page size. */
30070 #define HWRM_CFA_CTX_MEM_QCTX_OUTPUT_PAGE_SIZE_1M UINT32_C(0x8)
30071 /* 2MB page size. */
30072 #define HWRM_CFA_CTX_MEM_QCTX_OUTPUT_PAGE_SIZE_2M UINT32_C(0x9)
30073 /* 4MB page size. */
30074 #define HWRM_CFA_CTX_MEM_QCTX_OUTPUT_PAGE_SIZE_4M UINT32_C(0xa)
30075 /* 1GB page size. */
30076 #define HWRM_CFA_CTX_MEM_QCTX_OUTPUT_PAGE_SIZE_1G UINT32_C(0x12)
30077 #define HWRM_CFA_CTX_MEM_QCTX_OUTPUT_PAGE_SIZE_LAST \
30078 HWRM_CFA_CTX_MEM_QCTX_OUTPUT_PAGE_SIZE_1G
30079 uint8_t unused_0[4];
30080 /* Pointer to the PBL, or PDL depending on number of levels */
30082 uint8_t unused_1[7];
30084 * This field is used in Output records to indicate that the output
30085 * is completely written to RAM. This field should be read as '1'
30086 * to indicate that the output has been completely written.
30087 * When writing a command completion or response to an internal processor,
30088 * the order of writes has to be such that this field is written last.
30091 } __attribute__((packed));
30093 /**************************
30094 * hwrm_cfa_ctx_mem_qcaps *
30095 **************************/
30098 /* hwrm_cfa_ctx_mem_qcaps_input (size:128b/16B) */
30099 struct hwrm_cfa_ctx_mem_qcaps_input {
30100 /* The HWRM command request type. */
30103 * The completion ring to send the completion event on. This should
30104 * be the NQ ID returned from the `nq_alloc` HWRM command.
30106 uint16_t cmpl_ring;
30108 * The sequence ID is used by the driver for tracking multiple
30109 * commands. This ID is treated as opaque data by the firmware and
30110 * the value is returned in the `hwrm_resp_hdr` upon completion.
30114 * The target ID of the command:
30115 * * 0x0-0xFFF8 - The function ID
30116 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
30117 * * 0xFFFD - Reserved for user-space HWRM interface
30120 uint16_t target_id;
30122 * A physical address pointer pointing to a host buffer that the
30123 * command's response data will be written. This can be either a host
30124 * physical address (HPA) or a guest physical address (GPA) and must
30125 * point to a physically contiguous block of memory.
30127 uint64_t resp_addr;
30128 } __attribute__((packed));
30130 /* hwrm_cfa_ctx_mem_qcaps_output (size:128b/16B) */
30131 struct hwrm_cfa_ctx_mem_qcaps_output {
30132 /* The specific error status for the command. */
30133 uint16_t error_code;
30134 /* The HWRM command request type. */
30136 /* The sequence ID from the original command. */
30138 /* The length of the response data in number of bytes. */
30140 /* Indicates the maximum number of context memory which can be registered. */
30141 uint16_t max_entries;
30142 uint8_t unused_0[5];
30144 * This field is used in Output records to indicate that the output
30145 * is completely written to RAM. This field should be read as '1'
30146 * to indicate that the output has been completely written.
30147 * When writing a command completion or response to an internal processor,
30148 * the order of writes has to be such that this field is written last.
30151 } __attribute__((packed));
30153 /**********************
30154 * hwrm_cfa_eem_qcaps *
30155 **********************/
30158 /* hwrm_cfa_eem_qcaps_input (size:192b/24B) */
30159 struct hwrm_cfa_eem_qcaps_input {
30160 /* The HWRM command request type. */
30163 * The completion ring to send the completion event on. This should
30164 * be the NQ ID returned from the `nq_alloc` HWRM command.
30166 uint16_t cmpl_ring;
30168 * The sequence ID is used by the driver for tracking multiple
30169 * commands. This ID is treated as opaque data by the firmware and
30170 * the value is returned in the `hwrm_resp_hdr` upon completion.
30174 * The target ID of the command:
30175 * * 0x0-0xFFF8 - The function ID
30176 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
30177 * * 0xFFFD - Reserved for user-space HWRM interface
30180 uint16_t target_id;
30182 * A physical address pointer pointing to a host buffer that the
30183 * command's response data will be written. This can be either a host
30184 * physical address (HPA) or a guest physical address (GPA) and must
30185 * point to a physically contiguous block of memory.
30187 uint64_t resp_addr;
30190 * When set to 1, indicates the configuration will apply to TX flows
30191 * which are to be offloaded.
30192 * Note if this bit is set then the path_rx bit can't be set.
30194 #define HWRM_CFA_EEM_QCAPS_INPUT_FLAGS_PATH_TX \
30197 * When set to 1, indicates the configuration will apply to RX flows
30198 * which are to be offloaded.
30199 * Note if this bit is set then the path_tx bit can't be set.
30201 #define HWRM_CFA_EEM_QCAPS_INPUT_FLAGS_PATH_RX \
30203 /* When set to 1, all offloaded flows will be sent to EEM. */
30204 #define HWRM_CFA_EEM_QCAPS_INPUT_FLAGS_PREFERRED_OFFLOAD \
30207 } __attribute__((packed));
30209 /* hwrm_cfa_eem_qcaps_output (size:320b/40B) */
30210 struct hwrm_cfa_eem_qcaps_output {
30211 /* The specific error status for the command. */
30212 uint16_t error_code;
30213 /* The HWRM command request type. */
30215 /* The sequence ID from the original command. */
30217 /* The length of the response data in number of bytes. */
30221 * When set to 1, indicates the configuration will apply to TX flows
30222 * which are to be offloaded.
30223 * Note if this bit is set then the path_rx bit can't be set.
30225 #define HWRM_CFA_EEM_QCAPS_OUTPUT_FLAGS_PATH_TX \
30228 * When set to 1, indicates the configuration will apply to RX flows
30229 * which are to be offloaded.
30230 * Note if this bit is set then the path_tx bit can't be set.
30232 #define HWRM_CFA_EEM_QCAPS_OUTPUT_FLAGS_PATH_RX \
30235 * When set to 1, indicates the the FW supports the Centralized
30236 * Memory Model. The concept designates one entity for the
30237 * memory allocation while all others ‘subscribe’ to it.
30239 #define HWRM_CFA_EEM_QCAPS_OUTPUT_FLAGS_CENTRALIZED_MEMORY_MODEL_SUPPORTED \
30242 * When set to 1, indicates the the FW supports the Detached
30243 * Centralized Memory Model. The memory is allocated and managed
30244 * as a separate entity. All PFs and VFs will be granted direct
30245 * or semi-direct access to the allocated memory while none of
30246 * which can interfere with the management of the memory.
30248 #define HWRM_CFA_EEM_QCAPS_OUTPUT_FLAGS_DETACHED_CENTRALIZED_MEMORY_MODEL_SUPPORTED \
30251 uint32_t supported;
30253 * If set to 1, then EEM KEY0 table is supported using crc32 hash.
30254 * If set to 0, EEM KEY0 table is not supported.
30256 #define HWRM_CFA_EEM_QCAPS_OUTPUT_SUPPORTED_KEY0_TABLE \
30259 * If set to 1, then EEM KEY1 table is supported using lookup3 hash.
30260 * If set to 0, EEM KEY1 table is not supported.
30262 #define HWRM_CFA_EEM_QCAPS_OUTPUT_SUPPORTED_KEY1_TABLE \
30265 * If set to 1, then EEM External Record table is supported.
30266 * If set to 0, EEM External Record table is not supported.
30267 * (This table includes action record, EFC pointers, encap pointers)
30269 #define HWRM_CFA_EEM_QCAPS_OUTPUT_SUPPORTED_EXTERNAL_RECORD_TABLE \
30272 * If set to 1, then EEM External Flow Counters table is supported.
30273 * If set to 0, EEM External Flow Counters table is not supported.
30275 #define HWRM_CFA_EEM_QCAPS_OUTPUT_SUPPORTED_EXTERNAL_FLOW_COUNTERS_TABLE \
30278 * If set to 1, then FID table used for implicit flow flush is supported.
30279 * If set to 0, then FID table used for implicit flow flush is not supported.
30281 #define HWRM_CFA_EEM_QCAPS_OUTPUT_SUPPORTED_FID_TABLE \
30284 * The maximum number of entries supported by EEM. When configuring the host memory
30285 * the number of numbers of entries that can supported are -
30286 * 32k, 64k 128k, 256k, 512k, 1M, 2M, 4M, 8M, 32M, 64M, 128M entries.
30287 * Any value that are not these values, the FW will round down to the closest support
30288 * number of entries.
30290 uint32_t max_entries_supported;
30291 /* The entry size in bytes of each entry in the EEM KEY0/KEY1 tables. */
30292 uint16_t key_entry_size;
30293 /* The entry size in bytes of each entry in the EEM RECORD tables. */
30294 uint16_t record_entry_size;
30295 /* The entry size in bytes of each entry in the EEM EFC tables. */
30296 uint16_t efc_entry_size;
30297 /* The FID size in bytes of each entry in the EEM FID tables. */
30298 uint16_t fid_entry_size;
30299 uint8_t unused_1[7];
30301 * This field is used in Output records to indicate that the output
30302 * is completely written to RAM. This field should be read as '1'
30303 * to indicate that the output has been completely written.
30304 * When writing a command completion or response to an internal processor,
30305 * the order of writes has to be such that this field is written last.
30308 } __attribute__((packed));
30310 /********************
30311 * hwrm_cfa_eem_cfg *
30312 ********************/
30315 /* hwrm_cfa_eem_cfg_input (size:384b/48B) */
30316 struct hwrm_cfa_eem_cfg_input {
30317 /* The HWRM command request type. */
30320 * The completion ring to send the completion event on. This should
30321 * be the NQ ID returned from the `nq_alloc` HWRM command.
30323 uint16_t cmpl_ring;
30325 * The sequence ID is used by the driver for tracking multiple
30326 * commands. This ID is treated as opaque data by the firmware and
30327 * the value is returned in the `hwrm_resp_hdr` upon completion.
30331 * The target ID of the command:
30332 * * 0x0-0xFFF8 - The function ID
30333 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
30334 * * 0xFFFD - Reserved for user-space HWRM interface
30337 uint16_t target_id;
30339 * A physical address pointer pointing to a host buffer that the
30340 * command's response data will be written. This can be either a host
30341 * physical address (HPA) or a guest physical address (GPA) and must
30342 * point to a physically contiguous block of memory.
30344 uint64_t resp_addr;
30347 * When set to 1, indicates the configuration will apply to TX flows
30348 * which are to be offloaded.
30349 * Note if this bit is set then the path_rx bit can't be set.
30351 #define HWRM_CFA_EEM_CFG_INPUT_FLAGS_PATH_TX \
30354 * When set to 1, indicates the configuration will apply to RX flows
30355 * which are to be offloaded.
30356 * Note if this bit is set then the path_tx bit can't be set.
30358 #define HWRM_CFA_EEM_CFG_INPUT_FLAGS_PATH_RX \
30360 /* When set to 1, all offloaded flows will be sent to EEM. */
30361 #define HWRM_CFA_EEM_CFG_INPUT_FLAGS_PREFERRED_OFFLOAD \
30363 /* When set to 1, secondary, 0 means primary. */
30364 #define HWRM_CFA_EEM_CFG_INPUT_FLAGS_SECONDARY_PF \
30367 * Group_id which used by Firmware to identify memory pools belonging
30368 * to certain group.
30373 * Configured EEM with the given number of entries. All the EEM tables KEY0, KEY1,
30374 * RECORD, EFC all have the same number of entries and all tables will be configured
30375 * using this value. Current minimum value is 32k. Current maximum value is 128M.
30377 uint32_t num_entries;
30379 /* Configured EEM with the given context if for KEY0 table. */
30380 uint16_t key0_ctx_id;
30381 /* Configured EEM with the given context if for KEY1 table. */
30382 uint16_t key1_ctx_id;
30383 /* Configured EEM with the given context if for RECORD table. */
30384 uint16_t record_ctx_id;
30385 /* Configured EEM with the given context if for EFC table. */
30386 uint16_t efc_ctx_id;
30387 /* Configured EEM with the given context if for EFC table. */
30388 uint16_t fid_ctx_id;
30391 } __attribute__((packed));
30393 /* hwrm_cfa_eem_cfg_output (size:128b/16B) */
30394 struct hwrm_cfa_eem_cfg_output {
30395 /* The specific error status for the command. */
30396 uint16_t error_code;
30397 /* The HWRM command request type. */
30399 /* The sequence ID from the original command. */
30401 /* The length of the response data in number of bytes. */
30403 uint8_t unused_0[7];
30405 * This field is used in Output records to indicate that the output
30406 * is completely written to RAM. This field should be read as '1'
30407 * to indicate that the output has been completely written.
30408 * When writing a command completion or response to an internal processor,
30409 * the order of writes has to be such that this field is written last.
30412 } __attribute__((packed));
30414 /*********************
30415 * hwrm_cfa_eem_qcfg *
30416 *********************/
30419 /* hwrm_cfa_eem_qcfg_input (size:192b/24B) */
30420 struct hwrm_cfa_eem_qcfg_input {
30421 /* The HWRM command request type. */
30424 * The completion ring to send the completion event on. This should
30425 * be the NQ ID returned from the `nq_alloc` HWRM command.
30427 uint16_t cmpl_ring;
30429 * The sequence ID is used by the driver for tracking multiple
30430 * commands. This ID is treated as opaque data by the firmware and
30431 * the value is returned in the `hwrm_resp_hdr` upon completion.
30435 * The target ID of the command:
30436 * * 0x0-0xFFF8 - The function ID
30437 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
30438 * * 0xFFFD - Reserved for user-space HWRM interface
30441 uint16_t target_id;
30443 * A physical address pointer pointing to a host buffer that the
30444 * command's response data will be written. This can be either a host
30445 * physical address (HPA) or a guest physical address (GPA) and must
30446 * point to a physically contiguous block of memory.
30448 uint64_t resp_addr;
30450 /* When set to 1, indicates the configuration is the TX flow. */
30451 #define HWRM_CFA_EEM_QCFG_INPUT_FLAGS_PATH_TX UINT32_C(0x1)
30452 /* When set to 1, indicates the configuration is the RX flow. */
30453 #define HWRM_CFA_EEM_QCFG_INPUT_FLAGS_PATH_RX UINT32_C(0x2)
30455 } __attribute__((packed));
30457 /* hwrm_cfa_eem_qcfg_output (size:256b/32B) */
30458 struct hwrm_cfa_eem_qcfg_output {
30459 /* The specific error status for the command. */
30460 uint16_t error_code;
30461 /* The HWRM command request type. */
30463 /* The sequence ID from the original command. */
30465 /* The length of the response data in number of bytes. */
30468 /* When set to 1, indicates the configuration is the TX flow. */
30469 #define HWRM_CFA_EEM_QCFG_OUTPUT_FLAGS_PATH_TX \
30471 /* When set to 1, indicates the configuration is the RX flow. */
30472 #define HWRM_CFA_EEM_QCFG_OUTPUT_FLAGS_PATH_RX \
30474 /* When set to 1, all offloaded flows will be sent to EEM. */
30475 #define HWRM_CFA_EEM_QCFG_OUTPUT_FLAGS_PREFERRED_OFFLOAD \
30477 /* The number of entries the FW has configured for EEM. */
30478 uint32_t num_entries;
30479 /* Configured EEM with the given context if for KEY0 table. */
30480 uint16_t key0_ctx_id;
30481 /* Configured EEM with the given context if for KEY1 table. */
30482 uint16_t key1_ctx_id;
30483 /* Configured EEM with the given context if for RECORD table. */
30484 uint16_t record_ctx_id;
30485 /* Configured EEM with the given context if for EFC table. */
30486 uint16_t efc_ctx_id;
30487 /* Configured EEM with the given context if for EFC table. */
30488 uint16_t fid_ctx_id;
30489 uint8_t unused_2[5];
30491 * This field is used in Output records to indicate that the output
30492 * is completely written to RAM. This field should be read as '1'
30493 * to indicate that the output has been completely written.
30494 * When writing a command completion or response to an internal processor,
30495 * the order of writes has to be such that this field is written last.
30498 } __attribute__((packed));
30500 /*******************
30501 * hwrm_cfa_eem_op *
30502 *******************/
30505 /* hwrm_cfa_eem_op_input (size:192b/24B) */
30506 struct hwrm_cfa_eem_op_input {
30507 /* The HWRM command request type. */
30510 * The completion ring to send the completion event on. This should
30511 * be the NQ ID returned from the `nq_alloc` HWRM command.
30513 uint16_t cmpl_ring;
30515 * The sequence ID is used by the driver for tracking multiple
30516 * commands. This ID is treated as opaque data by the firmware and
30517 * the value is returned in the `hwrm_resp_hdr` upon completion.
30521 * The target ID of the command:
30522 * * 0x0-0xFFF8 - The function ID
30523 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
30524 * * 0xFFFD - Reserved for user-space HWRM interface
30527 uint16_t target_id;
30529 * A physical address pointer pointing to a host buffer that the
30530 * command's response data will be written. This can be either a host
30531 * physical address (HPA) or a guest physical address (GPA) and must
30532 * point to a physically contiguous block of memory.
30534 uint64_t resp_addr;
30537 * When set to 1, indicates the host memory which is passed will be
30538 * used for the TX flow offload function specified in fid.
30539 * Note if this bit is set then the path_rx bit can't be set.
30541 #define HWRM_CFA_EEM_OP_INPUT_FLAGS_PATH_TX UINT32_C(0x1)
30543 * When set to 1, indicates the host memory which is passed will be
30544 * used for the RX flow offload function specified in fid.
30545 * Note if this bit is set then the path_tx bit can't be set.
30547 #define HWRM_CFA_EEM_OP_INPUT_FLAGS_PATH_RX UINT32_C(0x2)
30549 /* The number of EEM key table entries to be configured. */
30551 /* This value is reserved and should not be used. */
30552 #define HWRM_CFA_EEM_OP_INPUT_OP_RESERVED UINT32_C(0x0)
30554 * To properly stop EEM and ensure there are no DMA's, the caller
30555 * must disable EEM for the given PF, using this call. This will
30556 * safely disable EEM and ensure that all DMA'ed to the
30557 * keys/records/efc have been completed.
30559 #define HWRM_CFA_EEM_OP_INPUT_OP_EEM_DISABLE UINT32_C(0x1)
30561 * Once the EEM host memory has been configured, EEM options have
30562 * been configured. Then the caller should enable EEM for the given
30563 * PF. Note once this call has been made, then the EEM mechanism
30564 * will be active and DMA's will occur as packets are processed.
30566 #define HWRM_CFA_EEM_OP_INPUT_OP_EEM_ENABLE UINT32_C(0x2)
30568 * Clear EEM settings for the given PF so that the register values
30569 * are reset back to there initial state.
30571 #define HWRM_CFA_EEM_OP_INPUT_OP_EEM_CLEANUP UINT32_C(0x3)
30572 #define HWRM_CFA_EEM_OP_INPUT_OP_LAST \
30573 HWRM_CFA_EEM_OP_INPUT_OP_EEM_CLEANUP
30574 } __attribute__((packed));
30576 /* hwrm_cfa_eem_op_output (size:128b/16B) */
30577 struct hwrm_cfa_eem_op_output {
30578 /* The specific error status for the command. */
30579 uint16_t error_code;
30580 /* The HWRM command request type. */
30582 /* The sequence ID from the original command. */
30584 /* The length of the response data in number of bytes. */
30586 uint8_t unused_0[7];
30588 * This field is used in Output records to indicate that the output
30589 * is completely written to RAM. This field should be read as '1'
30590 * to indicate that the output has been completely written.
30591 * When writing a command completion or response to an internal processor,
30592 * the order of writes has to be such that this field is written last.
30595 } __attribute__((packed));
30597 /********************************
30598 * hwrm_cfa_adv_flow_mgnt_qcaps *
30599 ********************************/
30602 /* hwrm_cfa_adv_flow_mgnt_qcaps_input (size:256b/32B) */
30603 struct hwrm_cfa_adv_flow_mgnt_qcaps_input {
30604 /* The HWRM command request type. */
30607 * The completion ring to send the completion event on. This should
30608 * be the NQ ID returned from the `nq_alloc` HWRM command.
30610 uint16_t cmpl_ring;
30612 * The sequence ID is used by the driver for tracking multiple
30613 * commands. This ID is treated as opaque data by the firmware and
30614 * the value is returned in the `hwrm_resp_hdr` upon completion.
30618 * The target ID of the command:
30619 * * 0x0-0xFFF8 - The function ID
30620 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
30621 * * 0xFFFD - Reserved for user-space HWRM interface
30624 uint16_t target_id;
30626 * A physical address pointer pointing to a host buffer that the
30627 * command's response data will be written. This can be either a host
30628 * physical address (HPA) or a guest physical address (GPA) and must
30629 * point to a physically contiguous block of memory.
30631 uint64_t resp_addr;
30632 uint32_t unused_0[4];
30633 } __attribute__((packed));
30635 /* hwrm_cfa_adv_flow_mgnt_qcaps_output (size:128b/16B) */
30636 struct hwrm_cfa_adv_flow_mgnt_qcaps_output {
30637 /* The specific error status for the command. */
30638 uint16_t error_code;
30639 /* The HWRM command request type. */
30641 /* The sequence ID from the original command. */
30643 /* The length of the response data in number of bytes. */
30647 * Value of 1 to indicate firmware support 16-bit flow handle.
30648 * Value of 0 to indicate firmware not support 16-bit flow handle.
30650 #define HWRM_CFA_ADV_FLOW_MGNT_QCAPS_OUTPUT_FLAGS_FLOW_HND_16BIT_SUPPORTED \
30653 * Value of 1 to indicate firmware support 64-bit flow handle.
30654 * Value of 0 to indicate firmware not support 64-bit flow handle.
30656 #define HWRM_CFA_ADV_FLOW_MGNT_QCAPS_OUTPUT_FLAGS_FLOW_HND_64BIT_SUPPORTED \
30659 * Value of 1 to indicate firmware support flow batch delete operation through
30660 * HWRM_CFA_FLOW_FLUSH command.
30661 * Value of 0 to indicate that the firmware does not support flow batch delete
30664 #define HWRM_CFA_ADV_FLOW_MGNT_QCAPS_OUTPUT_FLAGS_FLOW_BATCH_DELETE_SUPPORTED \
30667 * Value of 1 to indicate that the firmware support flow reset all operation through
30668 * HWRM_CFA_FLOW_FLUSH command.
30669 * Value of 0 indicates firmware does not support flow reset all operation.
30671 #define HWRM_CFA_ADV_FLOW_MGNT_QCAPS_OUTPUT_FLAGS_FLOW_RESET_ALL_SUPPORTED \
30674 * Value of 1 to indicate that firmware supports use of FID as dest_id in
30675 * HWRM_CFA_NTUPLE_ALLOC/CFG commands.
30676 * Value of 0 indicates firmware does not support use of FID as dest_id.
30678 #define HWRM_CFA_ADV_FLOW_MGNT_QCAPS_OUTPUT_FLAGS_NTUPLE_FLOW_DEST_FUNC_SUPPORTED \
30681 * Value of 1 to indicate that firmware supports TX EEM flows.
30682 * Value of 0 indicates firmware does not support TX EEM flows.
30684 #define HWRM_CFA_ADV_FLOW_MGNT_QCAPS_OUTPUT_FLAGS_TX_EEM_FLOW_SUPPORTED \
30687 * Value of 1 to indicate that firmware supports RX EEM flows.
30688 * Value of 0 indicates firmware does not support RX EEM flows.
30690 #define HWRM_CFA_ADV_FLOW_MGNT_QCAPS_OUTPUT_FLAGS_RX_EEM_FLOW_SUPPORTED \
30693 * Value of 1 to indicate that firmware supports the dynamic allocation of an
30694 * on-chip flow counter which can be used for EEM flows.
30695 * Value of 0 indicates firmware does not support the dynamic allocation of an
30696 * on-chip flow counter.
30698 #define HWRM_CFA_ADV_FLOW_MGNT_QCAPS_OUTPUT_FLAGS_FLOW_COUNTER_ALLOC_SUPPORTED \
30701 * Value of 1 to indicate that firmware supports setting of
30702 * rfs_ring_tbl_idx in HWRM_CFA_NTUPLE_ALLOC command.
30703 * Value of 0 indicates firmware does not support rfs_ring_tbl_idx.
30705 #define HWRM_CFA_ADV_FLOW_MGNT_QCAPS_OUTPUT_FLAGS_RFS_RING_TBL_IDX_SUPPORTED \
30708 * Value of 1 to indicate that firmware supports untagged matching
30709 * criteria on HWRM_CFA_L2_FILTER_ALLOC command. Value of 0
30710 * indicates firmware does not support untagged matching.
30712 #define HWRM_CFA_ADV_FLOW_MGNT_QCAPS_OUTPUT_FLAGS_UNTAGGED_VLAN_SUPPORTED \
30715 * Value of 1 to indicate that firmware supports XDP filter. Value
30716 * of 0 indicates firmware does not support XDP filter.
30718 #define HWRM_CFA_ADV_FLOW_MGNT_QCAPS_OUTPUT_FLAGS_XDP_SUPPORTED \
30721 * Value of 1 to indicate that the firmware support L2 header source
30722 * fields matching criteria on HWRM_CFA_L2_FILTER_ALLOC command.
30723 * Value of 0 indicates firmware does not support L2 header source
30726 #define HWRM_CFA_ADV_FLOW_MGNT_QCAPS_OUTPUT_FLAGS_L2_HEADER_SOURCE_FIELDS_SUPPORTED \
30728 uint8_t unused_0[3];
30730 * This field is used in Output records to indicate that the output
30731 * is completely written to RAM. This field should be read as '1'
30732 * to indicate that the output has been completely written.
30733 * When writing a command completion or response to an internal processor,
30734 * the order of writes has to be such that this field is written last.
30737 } __attribute__((packed));
30739 /******************
30741 ******************/
30744 /* hwrm_cfa_tflib_input (size:1024b/128B) */
30745 struct hwrm_cfa_tflib_input {
30746 /* The HWRM command request type. */
30749 * The completion ring to send the completion event on. This should
30750 * be the NQ ID returned from the `nq_alloc` HWRM command.
30752 uint16_t cmpl_ring;
30754 * The sequence ID is used by the driver for tracking multiple
30755 * commands. This ID is treated as opaque data by the firmware and
30756 * the value is returned in the `hwrm_resp_hdr` upon completion.
30760 * The target ID of the command:
30761 * * 0x0-0xFFF8 - The function ID
30762 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
30763 * * 0xFFFD - Reserved for user-space HWRM interface
30766 uint16_t target_id;
30768 * A physical address pointer pointing to a host buffer that the
30769 * command's response data will be written. This can be either a host
30770 * physical address (HPA) or a guest physical address (GPA) and must
30771 * point to a physically contiguous block of memory.
30773 uint64_t resp_addr;
30774 /* TFLIB message type. */
30776 /* TFLIB message subtype. */
30777 uint16_t tf_subtype;
30779 uint8_t unused0[4];
30780 /* TFLIB request data. */
30781 uint32_t tf_req[26];
30782 } __attribute__((packed));
30784 /* hwrm_cfa_tflib_output (size:5632b/704B) */
30785 struct hwrm_cfa_tflib_output {
30786 /* The specific error status for the command. */
30787 uint16_t error_code;
30788 /* The HWRM command request type. */
30790 /* The sequence ID from the original command. */
30792 /* The length of the response data in number of bytes. */
30794 /* TFLIB message type. */
30796 /* TFLIB message subtype. */
30797 uint16_t tf_subtype;
30798 /* TFLIB response code */
30799 uint32_t tf_resp_code;
30800 /* TFLIB response data. */
30801 uint32_t tf_resp[170];
30803 uint8_t unused1[7];
30805 * This field is used in Output records to indicate that the output
30806 * is completely written to RAM. This field should be read as '1'
30807 * to indicate that the output has been completely written.
30808 * When writing a command completion or response to an internal processor,
30809 * the order of writes has to be such that this field is written last.
30812 } __attribute__((packed));
30814 /******************************
30815 * hwrm_tunnel_dst_port_query *
30816 ******************************/
30819 /* hwrm_tunnel_dst_port_query_input (size:192b/24B) */
30820 struct hwrm_tunnel_dst_port_query_input {
30821 /* The HWRM command request type. */
30824 * The completion ring to send the completion event on. This should
30825 * be the NQ ID returned from the `nq_alloc` HWRM command.
30827 uint16_t cmpl_ring;
30829 * The sequence ID is used by the driver for tracking multiple
30830 * commands. This ID is treated as opaque data by the firmware and
30831 * the value is returned in the `hwrm_resp_hdr` upon completion.
30835 * The target ID of the command:
30836 * * 0x0-0xFFF8 - The function ID
30837 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
30838 * * 0xFFFD - Reserved for user-space HWRM interface
30841 uint16_t target_id;
30843 * A physical address pointer pointing to a host buffer that the
30844 * command's response data will be written. This can be either a host
30845 * physical address (HPA) or a guest physical address (GPA) and must
30846 * point to a physically contiguous block of memory.
30848 uint64_t resp_addr;
30850 uint8_t tunnel_type;
30851 /* Virtual eXtensible Local Area Network (VXLAN) */
30852 #define HWRM_TUNNEL_DST_PORT_QUERY_INPUT_TUNNEL_TYPE_VXLAN \
30854 /* Generic Network Virtualization Encapsulation (Geneve) */
30855 #define HWRM_TUNNEL_DST_PORT_QUERY_INPUT_TUNNEL_TYPE_GENEVE \
30857 /* IPV4 over virtual eXtensible Local Area Network (IPV4oVXLAN) */
30858 #define HWRM_TUNNEL_DST_PORT_QUERY_INPUT_TUNNEL_TYPE_VXLAN_V4 \
30860 /* Enhance Generic Routing Encapsulation (GRE version 1) inside IP datagram payload */
30861 #define HWRM_TUNNEL_DST_PORT_QUERY_INPUT_TUNNEL_TYPE_IPGRE_V1 \
30863 /* Use fixed layer 2 ether type of 0xFFFF */
30864 #define HWRM_TUNNEL_DST_PORT_QUERY_INPUT_TUNNEL_TYPE_L2_ETYPE \
30866 /* IPV6 over virtual eXtensible Local Area Network with GPE header (IPV6oVXLANGPE) */
30867 #define HWRM_TUNNEL_DST_PORT_QUERY_INPUT_TUNNEL_TYPE_VXLAN_GPE_V6 \
30869 #define HWRM_TUNNEL_DST_PORT_QUERY_INPUT_TUNNEL_TYPE_LAST \
30870 HWRM_TUNNEL_DST_PORT_QUERY_INPUT_TUNNEL_TYPE_VXLAN_GPE_V6
30871 uint8_t unused_0[7];
30872 } __attribute__((packed));
30874 /* hwrm_tunnel_dst_port_query_output (size:128b/16B) */
30875 struct hwrm_tunnel_dst_port_query_output {
30876 /* The specific error status for the command. */
30877 uint16_t error_code;
30878 /* The HWRM command request type. */
30880 /* The sequence ID from the original command. */
30882 /* The length of the response data in number of bytes. */
30885 * This field represents the identifier of L4 destination port
30886 * used for the given tunnel type. This field is valid for
30887 * specific tunnel types that use layer 4 (e.g. UDP)
30888 * transports for tunneling.
30890 uint16_t tunnel_dst_port_id;
30892 * This field represents the value of L4 destination port
30893 * identified by tunnel_dst_port_id. This field is valid for
30894 * specific tunnel types that use layer 4 (e.g. UDP)
30895 * transports for tunneling.
30896 * This field is in network byte order.
30898 * A value of 0 means that the destination port is not
30901 uint16_t tunnel_dst_port_val;
30902 uint8_t unused_0[3];
30904 * This field is used in Output records to indicate that the output
30905 * is completely written to RAM. This field should be read as '1'
30906 * to indicate that the output has been completely written.
30907 * When writing a command completion or response to an internal processor,
30908 * the order of writes has to be such that this field is written last.
30911 } __attribute__((packed));
30913 /******************************
30914 * hwrm_tunnel_dst_port_alloc *
30915 ******************************/
30918 /* hwrm_tunnel_dst_port_alloc_input (size:192b/24B) */
30919 struct hwrm_tunnel_dst_port_alloc_input {
30920 /* The HWRM command request type. */
30923 * The completion ring to send the completion event on. This should
30924 * be the NQ ID returned from the `nq_alloc` HWRM command.
30926 uint16_t cmpl_ring;
30928 * The sequence ID is used by the driver for tracking multiple
30929 * commands. This ID is treated as opaque data by the firmware and
30930 * the value is returned in the `hwrm_resp_hdr` upon completion.
30934 * The target ID of the command:
30935 * * 0x0-0xFFF8 - The function ID
30936 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
30937 * * 0xFFFD - Reserved for user-space HWRM interface
30940 uint16_t target_id;
30942 * A physical address pointer pointing to a host buffer that the
30943 * command's response data will be written. This can be either a host
30944 * physical address (HPA) or a guest physical address (GPA) and must
30945 * point to a physically contiguous block of memory.
30947 uint64_t resp_addr;
30949 uint8_t tunnel_type;
30950 /* Virtual eXtensible Local Area Network (VXLAN) */
30951 #define HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_VXLAN \
30953 /* Generic Network Virtualization Encapsulation (Geneve) */
30954 #define HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_GENEVE \
30956 /* IPV4 over virtual eXtensible Local Area Network (IPV4oVXLAN) */
30957 #define HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_VXLAN_V4 \
30959 /* Enhance Generic Routing Encapsulation (GRE version 1) inside IP datagram payload */
30960 #define HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_IPGRE_V1 \
30962 /* Use fixed layer 2 ether type of 0xFFFF */
30963 #define HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_L2_ETYPE \
30965 /* IPV6 over virtual eXtensible Local Area Network with GPE header (IPV6oVXLANGPE) */
30966 #define HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_VXLAN_GPE_V6 \
30968 #define HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_LAST \
30969 HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_VXLAN_GPE_V6
30972 * This field represents the value of L4 destination port used
30973 * for the given tunnel type. This field is valid for
30974 * specific tunnel types that use layer 4 (e.g. UDP)
30975 * transports for tunneling.
30977 * This field is in network byte order.
30979 * A value of 0 shall fail the command.
30981 uint16_t tunnel_dst_port_val;
30982 uint8_t unused_1[4];
30983 } __attribute__((packed));
30985 /* hwrm_tunnel_dst_port_alloc_output (size:128b/16B) */
30986 struct hwrm_tunnel_dst_port_alloc_output {
30987 /* The specific error status for the command. */
30988 uint16_t error_code;
30989 /* The HWRM command request type. */
30991 /* The sequence ID from the original command. */
30993 /* The length of the response data in number of bytes. */
30996 * Identifier of a tunnel L4 destination port value. Only applies to tunnel
30997 * types that has l4 destination port parameters.
30999 uint16_t tunnel_dst_port_id;
31000 uint8_t unused_0[5];
31002 * This field is used in Output records to indicate that the output
31003 * is completely written to RAM. This field should be read as '1'
31004 * to indicate that the output has been completely written.
31005 * When writing a command completion or response to an internal processor,
31006 * the order of writes has to be such that this field is written last.
31009 } __attribute__((packed));
31011 /*****************************
31012 * hwrm_tunnel_dst_port_free *
31013 *****************************/
31016 /* hwrm_tunnel_dst_port_free_input (size:192b/24B) */
31017 struct hwrm_tunnel_dst_port_free_input {
31018 /* The HWRM command request type. */
31021 * The completion ring to send the completion event on. This should
31022 * be the NQ ID returned from the `nq_alloc` HWRM command.
31024 uint16_t cmpl_ring;
31026 * The sequence ID is used by the driver for tracking multiple
31027 * commands. This ID is treated as opaque data by the firmware and
31028 * the value is returned in the `hwrm_resp_hdr` upon completion.
31032 * The target ID of the command:
31033 * * 0x0-0xFFF8 - The function ID
31034 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
31035 * * 0xFFFD - Reserved for user-space HWRM interface
31038 uint16_t target_id;
31040 * A physical address pointer pointing to a host buffer that the
31041 * command's response data will be written. This can be either a host
31042 * physical address (HPA) or a guest physical address (GPA) and must
31043 * point to a physically contiguous block of memory.
31045 uint64_t resp_addr;
31047 uint8_t tunnel_type;
31048 /* Virtual eXtensible Local Area Network (VXLAN) */
31049 #define HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_VXLAN \
31051 /* Generic Network Virtualization Encapsulation (Geneve) */
31052 #define HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_GENEVE \
31054 /* IPV4 over virtual eXtensible Local Area Network (IPV4oVXLAN) */
31055 #define HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_VXLAN_V4 \
31057 /* Enhance Generic Routing Encapsulation (GRE version 1) inside IP datagram payload */
31058 #define HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_IPGRE_V1 \
31060 /* Use fixed layer 2 ether type of 0xFFFF */
31061 #define HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_L2_ETYPE \
31063 /* IPV6 over virtual eXtensible Local Area Network with GPE header (IPV6oVXLANGPE) */
31064 #define HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_VXLAN_GPE_V6 \
31066 #define HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_LAST \
31067 HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_VXLAN_GPE_V6
31070 * Identifier of a tunnel L4 destination port value. Only applies to tunnel
31071 * types that has l4 destination port parameters.
31073 uint16_t tunnel_dst_port_id;
31074 uint8_t unused_1[4];
31075 } __attribute__((packed));
31077 /* hwrm_tunnel_dst_port_free_output (size:128b/16B) */
31078 struct hwrm_tunnel_dst_port_free_output {
31079 /* The specific error status for the command. */
31080 uint16_t error_code;
31081 /* The HWRM command request type. */
31083 /* The sequence ID from the original command. */
31085 /* The length of the response data in number of bytes. */
31087 uint8_t unused_1[7];
31089 * This field is used in Output records to indicate that the output
31090 * is completely written to RAM. This field should be read as '1'
31091 * to indicate that the output has been completely written.
31092 * When writing a command completion or response to an internal processor,
31093 * the order of writes has to be such that this field is written last.
31096 } __attribute__((packed));
31098 /* Periodic statistics context DMA to host. */
31099 /* ctx_hw_stats (size:1280b/160B) */
31100 struct ctx_hw_stats {
31101 /* Number of received unicast packets */
31102 uint64_t rx_ucast_pkts;
31103 /* Number of received multicast packets */
31104 uint64_t rx_mcast_pkts;
31105 /* Number of received broadcast packets */
31106 uint64_t rx_bcast_pkts;
31107 /* Number of discarded packets on received path */
31108 uint64_t rx_discard_pkts;
31109 /* Number of dropped packets on received path */
31110 uint64_t rx_drop_pkts;
31111 /* Number of received bytes for unicast traffic */
31112 uint64_t rx_ucast_bytes;
31113 /* Number of received bytes for multicast traffic */
31114 uint64_t rx_mcast_bytes;
31115 /* Number of received bytes for broadcast traffic */
31116 uint64_t rx_bcast_bytes;
31117 /* Number of transmitted unicast packets */
31118 uint64_t tx_ucast_pkts;
31119 /* Number of transmitted multicast packets */
31120 uint64_t tx_mcast_pkts;
31121 /* Number of transmitted broadcast packets */
31122 uint64_t tx_bcast_pkts;
31123 /* Number of discarded packets on transmit path */
31124 uint64_t tx_discard_pkts;
31125 /* Number of dropped packets on transmit path */
31126 uint64_t tx_drop_pkts;
31127 /* Number of transmitted bytes for unicast traffic */
31128 uint64_t tx_ucast_bytes;
31129 /* Number of transmitted bytes for multicast traffic */
31130 uint64_t tx_mcast_bytes;
31131 /* Number of transmitted bytes for broadcast traffic */
31132 uint64_t tx_bcast_bytes;
31133 /* Number of TPA packets */
31135 /* Number of TPA bytes */
31136 uint64_t tpa_bytes;
31137 /* Number of TPA events */
31138 uint64_t tpa_events;
31139 /* Number of TPA aborts */
31140 uint64_t tpa_aborts;
31141 } __attribute__((packed));
31143 /* Periodic statistics context DMA to host. */
31144 /* ctx_hw_stats_ext (size:1344b/168B) */
31145 struct ctx_hw_stats_ext {
31146 /* Number of received unicast packets */
31147 uint64_t rx_ucast_pkts;
31148 /* Number of received multicast packets */
31149 uint64_t rx_mcast_pkts;
31150 /* Number of received broadcast packets */
31151 uint64_t rx_bcast_pkts;
31152 /* Number of discarded packets on received path */
31153 uint64_t rx_discard_pkts;
31154 /* Number of dropped packets on received path */
31155 uint64_t rx_drop_pkts;
31156 /* Number of received bytes for unicast traffic */
31157 uint64_t rx_ucast_bytes;
31158 /* Number of received bytes for multicast traffic */
31159 uint64_t rx_mcast_bytes;
31160 /* Number of received bytes for broadcast traffic */
31161 uint64_t rx_bcast_bytes;
31162 /* Number of transmitted unicast packets */
31163 uint64_t tx_ucast_pkts;
31164 /* Number of transmitted multicast packets */
31165 uint64_t tx_mcast_pkts;
31166 /* Number of transmitted broadcast packets */
31167 uint64_t tx_bcast_pkts;
31168 /* Number of discarded packets on transmit path */
31169 uint64_t tx_discard_pkts;
31170 /* Number of dropped packets on transmit path */
31171 uint64_t tx_drop_pkts;
31172 /* Number of transmitted bytes for unicast traffic */
31173 uint64_t tx_ucast_bytes;
31174 /* Number of transmitted bytes for multicast traffic */
31175 uint64_t tx_mcast_bytes;
31176 /* Number of transmitted bytes for broadcast traffic */
31177 uint64_t tx_bcast_bytes;
31178 /* Number of TPA eligible packets */
31179 uint64_t rx_tpa_eligible_pkt;
31180 /* Number of TPA eligible bytes */
31181 uint64_t rx_tpa_eligible_bytes;
31182 /* Number of TPA packets */
31183 uint64_t rx_tpa_pkt;
31184 /* Number of TPA bytes */
31185 uint64_t rx_tpa_bytes;
31186 /* Number of TPA errors */
31187 uint64_t rx_tpa_errors;
31188 } __attribute__((packed));
31190 /* Periodic Engine statistics context DMA to host. */
31191 /* ctx_eng_stats (size:512b/64B) */
31192 struct ctx_eng_stats {
31194 * Count of data bytes into the Engine.
31195 * This includes any user supplied prefix,
31196 * but does not include any predefined
31199 uint64_t eng_bytes_in;
31200 /* Count of data bytes out of the Engine. */
31201 uint64_t eng_bytes_out;
31203 * Count, in 4-byte (dword) units, of bytes
31204 * that are input as auxiliary data.
31205 * This includes the aux_cmd data.
31207 uint64_t aux_bytes_in;
31209 * Count, in 4-byte (dword) units, of bytes
31210 * that are output as auxiliary data.
31211 * This count is the buffer space for aux_data
31212 * output provided in the RQE, not the actual
31215 uint64_t aux_bytes_out;
31216 /* Count of number of commands executed. */
31219 * Count of number of error commands.
31220 * These are the commands with a
31221 * non-zero status value.
31223 uint64_t error_commands;
31225 * Compression/Encryption Engine usage,
31226 * the unit is count of clock cycles
31228 uint64_t cce_engine_usage;
31230 * De-Compression/De-cryption Engine usage,
31231 * the unit is count of clock cycles
31233 uint64_t cdd_engine_usage;
31234 } __attribute__((packed));
31236 /***********************
31237 * hwrm_stat_ctx_alloc *
31238 ***********************/
31241 /* hwrm_stat_ctx_alloc_input (size:256b/32B) */
31242 struct hwrm_stat_ctx_alloc_input {
31243 /* The HWRM command request type. */
31246 * The completion ring to send the completion event on. This should
31247 * be the NQ ID returned from the `nq_alloc` HWRM command.
31249 uint16_t cmpl_ring;
31251 * The sequence ID is used by the driver for tracking multiple
31252 * commands. This ID is treated as opaque data by the firmware and
31253 * the value is returned in the `hwrm_resp_hdr` upon completion.
31257 * The target ID of the command:
31258 * * 0x0-0xFFF8 - The function ID
31259 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
31260 * * 0xFFFD - Reserved for user-space HWRM interface
31263 uint16_t target_id;
31265 * A physical address pointer pointing to a host buffer that the
31266 * command's response data will be written. This can be either a host
31267 * physical address (HPA) or a guest physical address (GPA) and must
31268 * point to a physically contiguous block of memory.
31270 uint64_t resp_addr;
31272 * This is the address for statistic block.
31273 * > For new versions of the chip, this address should be 128B
31276 uint64_t stats_dma_addr;
31278 * The statistic block update period in ms.
31279 * e.g. 250ms, 500ms, 750ms, 1000ms.
31280 * If update_period_ms is 0, then the stats update
31281 * shall be never done and the DMA address shall not be used.
31282 * In this case, the stat block can only be read by
31283 * hwrm_stat_ctx_query command.
31284 * On Ethernet/L2 based devices:
31285 * if tpa v2 supported (hwrm_vnic_qcaps[max_aggs_supported]>0),
31286 * ctx_hw_stats_ext is used for DMA,
31288 * ctx_hw_stats is used for DMA.
31290 uint32_t update_period_ms;
31292 * This field is used to specify statistics context specific
31293 * configuration flags.
31295 uint8_t stat_ctx_flags;
31297 * When this bit is set to '1', the statistics context shall be
31298 * allocated for RoCE traffic only. In this case, traffic other
31299 * than offloaded RoCE traffic shall not be included in this
31300 * statistic context.
31301 * When this bit is set to '0', the statistics context shall be
31302 * used for network traffic or engine traffic.
31304 #define HWRM_STAT_CTX_ALLOC_INPUT_STAT_CTX_FLAGS_ROCE UINT32_C(0x1)
31307 * This is the size of the structure (ctx_hw_stats or
31308 * ctx_hw_stats_ext) that the driver has allocated to be used
31309 * for the periodic DMA updates.
31311 uint16_t stats_dma_length;
31312 } __attribute__((packed));
31314 /* hwrm_stat_ctx_alloc_output (size:128b/16B) */
31315 struct hwrm_stat_ctx_alloc_output {
31316 /* The specific error status for the command. */
31317 uint16_t error_code;
31318 /* The HWRM command request type. */
31320 /* The sequence ID from the original command. */
31322 /* The length of the response data in number of bytes. */
31324 /* This is the statistics context ID value. */
31325 uint32_t stat_ctx_id;
31326 uint8_t unused_0[3];
31328 * This field is used in Output records to indicate that the output
31329 * is completely written to RAM. This field should be read as '1'
31330 * to indicate that the output has been completely written.
31331 * When writing a command completion or response to an internal processor,
31332 * the order of writes has to be such that this field is written last.
31335 } __attribute__((packed));
31337 /**********************
31338 * hwrm_stat_ctx_free *
31339 **********************/
31342 /* hwrm_stat_ctx_free_input (size:192b/24B) */
31343 struct hwrm_stat_ctx_free_input {
31344 /* The HWRM command request type. */
31347 * The completion ring to send the completion event on. This should
31348 * be the NQ ID returned from the `nq_alloc` HWRM command.
31350 uint16_t cmpl_ring;
31352 * The sequence ID is used by the driver for tracking multiple
31353 * commands. This ID is treated as opaque data by the firmware and
31354 * the value is returned in the `hwrm_resp_hdr` upon completion.
31358 * The target ID of the command:
31359 * * 0x0-0xFFF8 - The function ID
31360 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
31361 * * 0xFFFD - Reserved for user-space HWRM interface
31364 uint16_t target_id;
31366 * A physical address pointer pointing to a host buffer that the
31367 * command's response data will be written. This can be either a host
31368 * physical address (HPA) or a guest physical address (GPA) and must
31369 * point to a physically contiguous block of memory.
31371 uint64_t resp_addr;
31372 /* ID of the statistics context that is being queried. */
31373 uint32_t stat_ctx_id;
31374 uint8_t unused_0[4];
31375 } __attribute__((packed));
31377 /* hwrm_stat_ctx_free_output (size:128b/16B) */
31378 struct hwrm_stat_ctx_free_output {
31379 /* The specific error status for the command. */
31380 uint16_t error_code;
31381 /* The HWRM command request type. */
31383 /* The sequence ID from the original command. */
31385 /* The length of the response data in number of bytes. */
31387 /* This is the statistics context ID value. */
31388 uint32_t stat_ctx_id;
31389 uint8_t unused_0[3];
31391 * This field is used in Output records to indicate that the output
31392 * is completely written to RAM. This field should be read as '1'
31393 * to indicate that the output has been completely written.
31394 * When writing a command completion or response to an internal processor,
31395 * the order of writes has to be such that this field is written last.
31398 } __attribute__((packed));
31400 /***********************
31401 * hwrm_stat_ctx_query *
31402 ***********************/
31405 /* hwrm_stat_ctx_query_input (size:192b/24B) */
31406 struct hwrm_stat_ctx_query_input {
31407 /* The HWRM command request type. */
31410 * The completion ring to send the completion event on. This should
31411 * be the NQ ID returned from the `nq_alloc` HWRM command.
31413 uint16_t cmpl_ring;
31415 * The sequence ID is used by the driver for tracking multiple
31416 * commands. This ID is treated as opaque data by the firmware and
31417 * the value is returned in the `hwrm_resp_hdr` upon completion.
31421 * The target ID of the command:
31422 * * 0x0-0xFFF8 - The function ID
31423 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
31424 * * 0xFFFD - Reserved for user-space HWRM interface
31427 uint16_t target_id;
31429 * A physical address pointer pointing to a host buffer that the
31430 * command's response data will be written. This can be either a host
31431 * physical address (HPA) or a guest physical address (GPA) and must
31432 * point to a physically contiguous block of memory.
31434 uint64_t resp_addr;
31435 /* ID of the statistics context that is being queried. */
31436 uint32_t stat_ctx_id;
31437 uint8_t unused_0[4];
31438 } __attribute__((packed));
31440 /* hwrm_stat_ctx_query_output (size:1408b/176B) */
31441 struct hwrm_stat_ctx_query_output {
31442 /* The specific error status for the command. */
31443 uint16_t error_code;
31444 /* The HWRM command request type. */
31446 /* The sequence ID from the original command. */
31448 /* The length of the response data in number of bytes. */
31450 /* Number of transmitted unicast packets */
31451 uint64_t tx_ucast_pkts;
31452 /* Number of transmitted multicast packets */
31453 uint64_t tx_mcast_pkts;
31454 /* Number of transmitted broadcast packets */
31455 uint64_t tx_bcast_pkts;
31456 /* Number of transmitted packets with error */
31457 uint64_t tx_err_pkts;
31458 /* Number of dropped packets on transmit path */
31459 uint64_t tx_drop_pkts;
31460 /* Number of transmitted bytes for unicast traffic */
31461 uint64_t tx_ucast_bytes;
31462 /* Number of transmitted bytes for multicast traffic */
31463 uint64_t tx_mcast_bytes;
31464 /* Number of transmitted bytes for broadcast traffic */
31465 uint64_t tx_bcast_bytes;
31466 /* Number of received unicast packets */
31467 uint64_t rx_ucast_pkts;
31468 /* Number of received multicast packets */
31469 uint64_t rx_mcast_pkts;
31470 /* Number of received broadcast packets */
31471 uint64_t rx_bcast_pkts;
31472 /* Number of received packets with error */
31473 uint64_t rx_err_pkts;
31474 /* Number of dropped packets on received path */
31475 uint64_t rx_drop_pkts;
31476 /* Number of received bytes for unicast traffic */
31477 uint64_t rx_ucast_bytes;
31478 /* Number of received bytes for multicast traffic */
31479 uint64_t rx_mcast_bytes;
31480 /* Number of received bytes for broadcast traffic */
31481 uint64_t rx_bcast_bytes;
31482 /* Number of aggregated unicast packets */
31483 uint64_t rx_agg_pkts;
31484 /* Number of aggregated unicast bytes */
31485 uint64_t rx_agg_bytes;
31486 /* Number of aggregation events */
31487 uint64_t rx_agg_events;
31488 /* Number of aborted aggregations */
31489 uint64_t rx_agg_aborts;
31490 uint8_t unused_0[7];
31492 * This field is used in Output records to indicate that the output
31493 * is completely written to RAM. This field should be read as '1'
31494 * to indicate that the output has been completely written.
31495 * When writing a command completion or response to an internal processor,
31496 * the order of writes has to be such that this field is written last.
31499 } __attribute__((packed));
31501 /***************************
31502 * hwrm_stat_ctx_eng_query *
31503 ***************************/
31506 /* hwrm_stat_ctx_eng_query_input (size:192b/24B) */
31507 struct hwrm_stat_ctx_eng_query_input {
31508 /* The HWRM command request type. */
31511 * The completion ring to send the completion event on. This should
31512 * be the NQ ID returned from the `nq_alloc` HWRM command.
31514 uint16_t cmpl_ring;
31516 * The sequence ID is used by the driver for tracking multiple
31517 * commands. This ID is treated as opaque data by the firmware and
31518 * the value is returned in the `hwrm_resp_hdr` upon completion.
31522 * The target ID of the command:
31523 * * 0x0-0xFFF8 - The function ID
31524 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
31525 * * 0xFFFD - Reserved for user-space HWRM interface
31528 uint16_t target_id;
31530 * A physical address pointer pointing to a host buffer that the
31531 * command's response data will be written. This can be either a host
31532 * physical address (HPA) or a guest physical address (GPA) and must
31533 * point to a physically contiguous block of memory.
31535 uint64_t resp_addr;
31536 /* ID of the statistics context that is being queried. */
31537 uint32_t stat_ctx_id;
31538 uint8_t unused_0[4];
31539 } __attribute__((packed));
31541 /* hwrm_stat_ctx_eng_query_output (size:640b/80B) */
31542 struct hwrm_stat_ctx_eng_query_output {
31543 /* The specific error status for the command. */
31544 uint16_t error_code;
31545 /* The HWRM command request type. */
31547 /* The sequence ID from the original command. */
31549 /* The length of the response data in number of bytes. */
31552 * Count of data bytes into the Engine.
31553 * This includes any user supplied prefix,
31554 * but does not include any predefined
31557 uint64_t eng_bytes_in;
31558 /* Count of data bytes out of the Engine. */
31559 uint64_t eng_bytes_out;
31561 * Count, in 4-byte (dword) units, of bytes
31562 * that are input as auxiliary data.
31563 * This includes the aux_cmd data.
31565 uint64_t aux_bytes_in;
31567 * Count, in 4-byte (dword) units, of bytes
31568 * that are output as auxiliary data.
31569 * This count is the buffer space for aux_data
31570 * output provided in the RQE, not the actual
31573 uint64_t aux_bytes_out;
31574 /* Count of number of commands executed. */
31577 * Count of number of error commands.
31578 * These are the commands with a
31579 * non-zero status value.
31581 uint64_t error_commands;
31583 * Compression/Encryption Engine usage,
31584 * the unit is count of clock cycles
31586 uint64_t cce_engine_usage;
31588 * De-Compression/De-cryption Engine usage,
31589 * the unit is count of clock cycles
31591 uint64_t cdd_engine_usage;
31592 uint8_t unused_0[7];
31594 * This field is used in Output records to indicate that the output
31595 * is completely written to RAM. This field should be read as '1'
31596 * to indicate that the output has been completely written.
31597 * When writing a command completion or response to an internal processor,
31598 * the order of writes has to be such that this field is written last.
31601 } __attribute__((packed));
31603 /***************************
31604 * hwrm_stat_ctx_clr_stats *
31605 ***************************/
31608 /* hwrm_stat_ctx_clr_stats_input (size:192b/24B) */
31609 struct hwrm_stat_ctx_clr_stats_input {
31610 /* The HWRM command request type. */
31613 * The completion ring to send the completion event on. This should
31614 * be the NQ ID returned from the `nq_alloc` HWRM command.
31616 uint16_t cmpl_ring;
31618 * The sequence ID is used by the driver for tracking multiple
31619 * commands. This ID is treated as opaque data by the firmware and
31620 * the value is returned in the `hwrm_resp_hdr` upon completion.
31624 * The target ID of the command:
31625 * * 0x0-0xFFF8 - The function ID
31626 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
31627 * * 0xFFFD - Reserved for user-space HWRM interface
31630 uint16_t target_id;
31632 * A physical address pointer pointing to a host buffer that the
31633 * command's response data will be written. This can be either a host
31634 * physical address (HPA) or a guest physical address (GPA) and must
31635 * point to a physically contiguous block of memory.
31637 uint64_t resp_addr;
31638 /* ID of the statistics context that is being queried. */
31639 uint32_t stat_ctx_id;
31640 uint8_t unused_0[4];
31641 } __attribute__((packed));
31643 /* hwrm_stat_ctx_clr_stats_output (size:128b/16B) */
31644 struct hwrm_stat_ctx_clr_stats_output {
31645 /* The specific error status for the command. */
31646 uint16_t error_code;
31647 /* The HWRM command request type. */
31649 /* The sequence ID from the original command. */
31651 /* The length of the response data in number of bytes. */
31653 uint8_t unused_0[7];
31655 * This field is used in Output records to indicate that the output
31656 * is completely written to RAM. This field should be read as '1'
31657 * to indicate that the output has been completely written.
31658 * When writing a command completion or response to an internal processor,
31659 * the order of writes has to be such that this field is written last.
31662 } __attribute__((packed));
31664 /********************
31665 * hwrm_pcie_qstats *
31666 ********************/
31669 /* hwrm_pcie_qstats_input (size:256b/32B) */
31670 struct hwrm_pcie_qstats_input {
31671 /* The HWRM command request type. */
31674 * The completion ring to send the completion event on. This should
31675 * be the NQ ID returned from the `nq_alloc` HWRM command.
31677 uint16_t cmpl_ring;
31679 * The sequence ID is used by the driver for tracking multiple
31680 * commands. This ID is treated as opaque data by the firmware and
31681 * the value is returned in the `hwrm_resp_hdr` upon completion.
31685 * The target ID of the command:
31686 * * 0x0-0xFFF8 - The function ID
31687 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
31688 * * 0xFFFD - Reserved for user-space HWRM interface
31691 uint16_t target_id;
31693 * A physical address pointer pointing to a host buffer that the
31694 * command's response data will be written. This can be either a host
31695 * physical address (HPA) or a guest physical address (GPA) and must
31696 * point to a physically contiguous block of memory.
31698 uint64_t resp_addr;
31700 * The size of PCIe statistics block in bytes.
31701 * Firmware will DMA the PCIe statistics to
31702 * the host with this field size in the response.
31704 uint16_t pcie_stat_size;
31705 uint8_t unused_0[6];
31707 * This is the host address where
31708 * PCIe statistics will be stored
31710 uint64_t pcie_stat_host_addr;
31711 } __attribute__((packed));
31713 /* hwrm_pcie_qstats_output (size:128b/16B) */
31714 struct hwrm_pcie_qstats_output {
31715 /* The specific error status for the command. */
31716 uint16_t error_code;
31717 /* The HWRM command request type. */
31719 /* The sequence ID from the original command. */
31721 /* The length of the response data in number of bytes. */
31723 /* The size of PCIe statistics block in bytes. */
31724 uint16_t pcie_stat_size;
31725 uint8_t unused_0[5];
31727 * This field is used in Output records to indicate that the output
31728 * is completely written to RAM. This field should be read as '1'
31729 * to indicate that the output has been completely written.
31730 * When writing a command completion or response to an internal processor,
31731 * the order of writes has to be such that this field is written last.
31734 } __attribute__((packed));
31736 /* PCIe Statistics Formats */
31737 /* pcie_ctx_hw_stats (size:768b/96B) */
31738 struct pcie_ctx_hw_stats {
31739 /* Number of physical layer receiver errors */
31740 uint64_t pcie_pl_signal_integrity;
31741 /* Number of DLLP CRC errors detected by Data Link Layer */
31742 uint64_t pcie_dl_signal_integrity;
31744 * Number of TLP LCRC and sequence number errors detected
31745 * by Data Link Layer
31747 uint64_t pcie_tl_signal_integrity;
31748 /* Number of times LTSSM entered Recovery state */
31749 uint64_t pcie_link_integrity;
31750 /* Number of TLP bytes that have been trasmitted */
31751 uint64_t pcie_tx_traffic_rate;
31752 /* Number of TLP bytes that have been received */
31753 uint64_t pcie_rx_traffic_rate;
31754 /* Number of DLLP bytes that have been trasmitted */
31755 uint64_t pcie_tx_dllp_statistics;
31756 /* Number of DLLP bytes that have been received */
31757 uint64_t pcie_rx_dllp_statistics;
31759 * Number of times spent in each phase of gen3
31762 uint64_t pcie_equalization_time;
31763 /* Records the last 16 transitions of the LTSSM */
31764 uint32_t pcie_ltssm_histogram[4];
31766 * Record the last 8 reasons on why LTSSM transitioned
31769 uint64_t pcie_recovery_histogram;
31770 } __attribute__((packed));
31772 /**********************
31773 * hwrm_exec_fwd_resp *
31774 **********************/
31777 /* hwrm_exec_fwd_resp_input (size:1024b/128B) */
31778 struct hwrm_exec_fwd_resp_input {
31779 /* The HWRM command request type. */
31782 * The completion ring to send the completion event on. This should
31783 * be the NQ ID returned from the `nq_alloc` HWRM command.
31785 uint16_t cmpl_ring;
31787 * The sequence ID is used by the driver for tracking multiple
31788 * commands. This ID is treated as opaque data by the firmware and
31789 * the value is returned in the `hwrm_resp_hdr` upon completion.
31793 * The target ID of the command:
31794 * * 0x0-0xFFF8 - The function ID
31795 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
31796 * * 0xFFFD - Reserved for user-space HWRM interface
31799 uint16_t target_id;
31801 * A physical address pointer pointing to a host buffer that the
31802 * command's response data will be written. This can be either a host
31803 * physical address (HPA) or a guest physical address (GPA) and must
31804 * point to a physically contiguous block of memory.
31806 uint64_t resp_addr;
31808 * This is an encapsulated request. This request should
31809 * be executed by the HWRM and the response should be
31810 * provided in the response buffer inside the encapsulated
31813 uint32_t encap_request[26];
31815 * This value indicates the target id of the response to
31816 * the encapsulated request.
31817 * 0x0 - 0xFFF8 - Used for function ids
31818 * 0xFFF8 - 0xFFFE - Reserved for internal processors
31821 uint16_t encap_resp_target_id;
31822 uint8_t unused_0[6];
31823 } __attribute__((packed));
31825 /* hwrm_exec_fwd_resp_output (size:128b/16B) */
31826 struct hwrm_exec_fwd_resp_output {
31827 /* The specific error status for the command. */
31828 uint16_t error_code;
31829 /* The HWRM command request type. */
31831 /* The sequence ID from the original command. */
31833 /* The length of the response data in number of bytes. */
31835 uint8_t unused_0[7];
31837 * This field is used in Output records to indicate that the output
31838 * is completely written to RAM. This field should be read as '1'
31839 * to indicate that the output has been completely written.
31840 * When writing a command completion or response to an internal processor,
31841 * the order of writes has to be such that this field is written last.
31844 } __attribute__((packed));
31846 /************************
31847 * hwrm_reject_fwd_resp *
31848 ************************/
31851 /* hwrm_reject_fwd_resp_input (size:1024b/128B) */
31852 struct hwrm_reject_fwd_resp_input {
31853 /* The HWRM command request type. */
31856 * The completion ring to send the completion event on. This should
31857 * be the NQ ID returned from the `nq_alloc` HWRM command.
31859 uint16_t cmpl_ring;
31861 * The sequence ID is used by the driver for tracking multiple
31862 * commands. This ID is treated as opaque data by the firmware and
31863 * the value is returned in the `hwrm_resp_hdr` upon completion.
31867 * The target ID of the command:
31868 * * 0x0-0xFFF8 - The function ID
31869 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
31870 * * 0xFFFD - Reserved for user-space HWRM interface
31873 uint16_t target_id;
31875 * A physical address pointer pointing to a host buffer that the
31876 * command's response data will be written. This can be either a host
31877 * physical address (HPA) or a guest physical address (GPA) and must
31878 * point to a physically contiguous block of memory.
31880 uint64_t resp_addr;
31882 * This is an encapsulated request. This request should
31883 * be rejected by the HWRM and the error response should be
31884 * provided in the response buffer inside the encapsulated
31887 uint32_t encap_request[26];
31889 * This value indicates the target id of the response to
31890 * the encapsulated request.
31891 * 0x0 - 0xFFF8 - Used for function ids
31892 * 0xFFF8 - 0xFFFE - Reserved for internal processors
31895 uint16_t encap_resp_target_id;
31896 uint8_t unused_0[6];
31897 } __attribute__((packed));
31899 /* hwrm_reject_fwd_resp_output (size:128b/16B) */
31900 struct hwrm_reject_fwd_resp_output {
31901 /* The specific error status for the command. */
31902 uint16_t error_code;
31903 /* The HWRM command request type. */
31905 /* The sequence ID from the original command. */
31907 /* The length of the response data in number of bytes. */
31909 uint8_t unused_0[7];
31911 * This field is used in Output records to indicate that the output
31912 * is completely written to RAM. This field should be read as '1'
31913 * to indicate that the output has been completely written.
31914 * When writing a command completion or response to an internal processor,
31915 * the order of writes has to be such that this field is written last.
31918 } __attribute__((packed));
31925 /* hwrm_fwd_resp_input (size:1024b/128B) */
31926 struct hwrm_fwd_resp_input {
31927 /* The HWRM command request type. */
31930 * The completion ring to send the completion event on. This should
31931 * be the NQ ID returned from the `nq_alloc` HWRM command.
31933 uint16_t cmpl_ring;
31935 * The sequence ID is used by the driver for tracking multiple
31936 * commands. This ID is treated as opaque data by the firmware and
31937 * the value is returned in the `hwrm_resp_hdr` upon completion.
31941 * The target ID of the command:
31942 * * 0x0-0xFFF8 - The function ID
31943 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
31944 * * 0xFFFD - Reserved for user-space HWRM interface
31947 uint16_t target_id;
31949 * A physical address pointer pointing to a host buffer that the
31950 * command's response data will be written. This can be either a host
31951 * physical address (HPA) or a guest physical address (GPA) and must
31952 * point to a physically contiguous block of memory.
31954 uint64_t resp_addr;
31956 * This value indicates the target id of the encapsulated
31958 * 0x0 - 0xFFF8 - Used for function ids
31959 * 0xFFF8 - 0xFFFE - Reserved for internal processors
31962 uint16_t encap_resp_target_id;
31964 * This value indicates the completion ring the encapsulated
31965 * response will be optionally completed on. If the value is
31966 * -1, then no CR completion shall be generated for the
31967 * encapsulated response. Any other value must be a
31968 * valid CR ring_id value. If a valid encap_resp_cmpl_ring
31969 * is provided, then a CR completion shall be generated for
31970 * the encapsulated response.
31972 uint16_t encap_resp_cmpl_ring;
31973 /* This field indicates the length of encapsulated response. */
31974 uint16_t encap_resp_len;
31978 * This is the host address where the encapsulated response
31980 * This area must be 16B aligned and must be cleared to zero
31981 * before the original request is made.
31983 uint64_t encap_resp_addr;
31984 /* This is an encapsulated response. */
31985 uint32_t encap_resp[24];
31986 } __attribute__((packed));
31988 /* hwrm_fwd_resp_output (size:128b/16B) */
31989 struct hwrm_fwd_resp_output {
31990 /* The specific error status for the command. */
31991 uint16_t error_code;
31992 /* The HWRM command request type. */
31994 /* The sequence ID from the original command. */
31996 /* The length of the response data in number of bytes. */
31998 uint8_t unused_0[7];
32000 * This field is used in Output records to indicate that the output
32001 * is completely written to RAM. This field should be read as '1'
32002 * to indicate that the output has been completely written.
32003 * When writing a command completion or response to an internal processor,
32004 * the order of writes has to be such that this field is written last.
32007 } __attribute__((packed));
32009 /*****************************
32010 * hwrm_fwd_async_event_cmpl *
32011 *****************************/
32014 /* hwrm_fwd_async_event_cmpl_input (size:320b/40B) */
32015 struct hwrm_fwd_async_event_cmpl_input {
32016 /* The HWRM command request type. */
32019 * The completion ring to send the completion event on. This should
32020 * be the NQ ID returned from the `nq_alloc` HWRM command.
32022 uint16_t cmpl_ring;
32024 * The sequence ID is used by the driver for tracking multiple
32025 * commands. This ID is treated as opaque data by the firmware and
32026 * the value is returned in the `hwrm_resp_hdr` upon completion.
32030 * The target ID of the command:
32031 * * 0x0-0xFFF8 - The function ID
32032 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
32033 * * 0xFFFD - Reserved for user-space HWRM interface
32036 uint16_t target_id;
32038 * A physical address pointer pointing to a host buffer that the
32039 * command's response data will be written. This can be either a host
32040 * physical address (HPA) or a guest physical address (GPA) and must
32041 * point to a physically contiguous block of memory.
32043 uint64_t resp_addr;
32045 * This value indicates the target id of the encapsulated
32046 * asynchronous event.
32047 * 0x0 - 0xFFF8 - Used for function ids
32048 * 0xFFF8 - 0xFFFE - Reserved for internal processors
32049 * 0xFFFF - Broadcast to all children VFs (only applicable when
32050 * a PF is the requester)
32052 uint16_t encap_async_event_target_id;
32053 uint8_t unused_0[6];
32054 /* This is an encapsulated asynchronous event completion. */
32055 uint32_t encap_async_event_cmpl[4];
32056 } __attribute__((packed));
32058 /* hwrm_fwd_async_event_cmpl_output (size:128b/16B) */
32059 struct hwrm_fwd_async_event_cmpl_output {
32060 /* The specific error status for the command. */
32061 uint16_t error_code;
32062 /* The HWRM command request type. */
32064 /* The sequence ID from the original command. */
32066 /* The length of the response data in number of bytes. */
32068 uint8_t unused_0[7];
32070 * This field is used in Output records to indicate that the output
32071 * is completely written to RAM. This field should be read as '1'
32072 * to indicate that the output has been completely written.
32073 * When writing a command completion or response to an internal processor,
32074 * the order of writes has to be such that this field is written last.
32077 } __attribute__((packed));
32079 /**************************
32080 * hwrm_nvm_raw_write_blk *
32081 **************************/
32084 /* hwrm_nvm_raw_write_blk_input (size:256b/32B) */
32085 struct hwrm_nvm_raw_write_blk_input {
32086 /* The HWRM command request type. */
32089 * The completion ring to send the completion event on. This should
32090 * be the NQ ID returned from the `nq_alloc` HWRM command.
32092 uint16_t cmpl_ring;
32094 * The sequence ID is used by the driver for tracking multiple
32095 * commands. This ID is treated as opaque data by the firmware and
32096 * the value is returned in the `hwrm_resp_hdr` upon completion.
32100 * The target ID of the command:
32101 * * 0x0-0xFFF8 - The function ID
32102 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
32103 * * 0xFFFD - Reserved for user-space HWRM interface
32106 uint16_t target_id;
32108 * A physical address pointer pointing to a host buffer that the
32109 * command's response data will be written. This can be either a host
32110 * physical address (HPA) or a guest physical address (GPA) and must
32111 * point to a physically contiguous block of memory.
32113 uint64_t resp_addr;
32115 * 64-bit Host Source Address.
32116 * This is the loation of the source data to be written.
32118 uint64_t host_src_addr;
32120 * 32-bit Destination Address.
32121 * This is the NVRAM byte-offset where the source data will be written to.
32123 uint32_t dest_addr;
32124 /* Length of data to be written, in bytes. */
32126 } __attribute__((packed));
32128 /* hwrm_nvm_raw_write_blk_output (size:128b/16B) */
32129 struct hwrm_nvm_raw_write_blk_output {
32130 /* The specific error status for the command. */
32131 uint16_t error_code;
32132 /* The HWRM command request type. */
32134 /* The sequence ID from the original command. */
32136 /* The length of the response data in number of bytes. */
32138 uint8_t unused_0[7];
32140 * This field is used in Output records to indicate that the output
32141 * is completely written to RAM. This field should be read as '1'
32142 * to indicate that the output has been completely written.
32143 * When writing a command completion or response to an internal processor,
32144 * the order of writes has to be such that this field is written last.
32147 } __attribute__((packed));
32154 /* hwrm_nvm_read_input (size:320b/40B) */
32155 struct hwrm_nvm_read_input {
32156 /* The HWRM command request type. */
32159 * The completion ring to send the completion event on. This should
32160 * be the NQ ID returned from the `nq_alloc` HWRM command.
32162 uint16_t cmpl_ring;
32164 * The sequence ID is used by the driver for tracking multiple
32165 * commands. This ID is treated as opaque data by the firmware and
32166 * the value is returned in the `hwrm_resp_hdr` upon completion.
32170 * The target ID of the command:
32171 * * 0x0-0xFFF8 - The function ID
32172 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
32173 * * 0xFFFD - Reserved for user-space HWRM interface
32176 uint16_t target_id;
32178 * A physical address pointer pointing to a host buffer that the
32179 * command's response data will be written. This can be either a host
32180 * physical address (HPA) or a guest physical address (GPA) and must
32181 * point to a physically contiguous block of memory.
32183 uint64_t resp_addr;
32185 * 64-bit Host Destination Address.
32186 * This is the host address where the data will be written to.
32188 uint64_t host_dest_addr;
32189 /* The 0-based index of the directory entry. */
32191 uint8_t unused_0[2];
32192 /* The NVRAM byte-offset to read from. */
32194 /* The length of the data to be read, in bytes. */
32196 uint8_t unused_1[4];
32197 } __attribute__((packed));
32199 /* hwrm_nvm_read_output (size:128b/16B) */
32200 struct hwrm_nvm_read_output {
32201 /* The specific error status for the command. */
32202 uint16_t error_code;
32203 /* The HWRM command request type. */
32205 /* The sequence ID from the original command. */
32207 /* The length of the response data in number of bytes. */
32209 uint8_t unused_0[7];
32211 * This field is used in Output records to indicate that the output
32212 * is completely written to RAM. This field should be read as '1'
32213 * to indicate that the output has been completely written.
32214 * When writing a command completion or response to an internal processor,
32215 * the order of writes has to be such that this field is written last.
32218 } __attribute__((packed));
32220 /*********************
32221 * hwrm_nvm_raw_dump *
32222 *********************/
32225 /* hwrm_nvm_raw_dump_input (size:256b/32B) */
32226 struct hwrm_nvm_raw_dump_input {
32227 /* The HWRM command request type. */
32230 * The completion ring to send the completion event on. This should
32231 * be the NQ ID returned from the `nq_alloc` HWRM command.
32233 uint16_t cmpl_ring;
32235 * The sequence ID is used by the driver for tracking multiple
32236 * commands. This ID is treated as opaque data by the firmware and
32237 * the value is returned in the `hwrm_resp_hdr` upon completion.
32241 * The target ID of the command:
32242 * * 0x0-0xFFF8 - The function ID
32243 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
32244 * * 0xFFFD - Reserved for user-space HWRM interface
32247 uint16_t target_id;
32249 * A physical address pointer pointing to a host buffer that the
32250 * command's response data will be written. This can be either a host
32251 * physical address (HPA) or a guest physical address (GPA) and must
32252 * point to a physically contiguous block of memory.
32254 uint64_t resp_addr;
32256 * 64-bit Host Destination Address.
32257 * This is the host address where the data will be written to.
32259 uint64_t host_dest_addr;
32260 /* 32-bit NVRAM byte-offset to read from. */
32262 /* Total length of NVRAM contents to be read, in bytes. */
32264 } __attribute__((packed));
32266 /* hwrm_nvm_raw_dump_output (size:128b/16B) */
32267 struct hwrm_nvm_raw_dump_output {
32268 /* The specific error status for the command. */
32269 uint16_t error_code;
32270 /* The HWRM command request type. */
32272 /* The sequence ID from the original command. */
32274 /* The length of the response data in number of bytes. */
32276 uint8_t unused_0[7];
32278 * This field is used in Output records to indicate that the output
32279 * is completely written to RAM. This field should be read as '1'
32280 * to indicate that the output has been completely written.
32281 * When writing a command completion or response to an internal processor,
32282 * the order of writes has to be such that this field is written last.
32285 } __attribute__((packed));
32287 /****************************
32288 * hwrm_nvm_get_dir_entries *
32289 ****************************/
32292 /* hwrm_nvm_get_dir_entries_input (size:192b/24B) */
32293 struct hwrm_nvm_get_dir_entries_input {
32294 /* The HWRM command request type. */
32297 * The completion ring to send the completion event on. This should
32298 * be the NQ ID returned from the `nq_alloc` HWRM command.
32300 uint16_t cmpl_ring;
32302 * The sequence ID is used by the driver for tracking multiple
32303 * commands. This ID is treated as opaque data by the firmware and
32304 * the value is returned in the `hwrm_resp_hdr` upon completion.
32308 * The target ID of the command:
32309 * * 0x0-0xFFF8 - The function ID
32310 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
32311 * * 0xFFFD - Reserved for user-space HWRM interface
32314 uint16_t target_id;
32316 * A physical address pointer pointing to a host buffer that the
32317 * command's response data will be written. This can be either a host
32318 * physical address (HPA) or a guest physical address (GPA) and must
32319 * point to a physically contiguous block of memory.
32321 uint64_t resp_addr;
32323 * 64-bit Host Destination Address.
32324 * This is the host address where the directory will be written.
32326 uint64_t host_dest_addr;
32327 } __attribute__((packed));
32329 /* hwrm_nvm_get_dir_entries_output (size:128b/16B) */
32330 struct hwrm_nvm_get_dir_entries_output {
32331 /* The specific error status for the command. */
32332 uint16_t error_code;
32333 /* The HWRM command request type. */
32335 /* The sequence ID from the original command. */
32337 /* The length of the response data in number of bytes. */
32339 uint8_t unused_0[7];
32341 * This field is used in Output records to indicate that the output
32342 * is completely written to RAM. This field should be read as '1'
32343 * to indicate that the output has been completely written.
32344 * When writing a command completion or response to an internal processor,
32345 * the order of writes has to be such that this field is written last.
32348 } __attribute__((packed));
32350 /*************************
32351 * hwrm_nvm_get_dir_info *
32352 *************************/
32355 /* hwrm_nvm_get_dir_info_input (size:128b/16B) */
32356 struct hwrm_nvm_get_dir_info_input {
32357 /* The HWRM command request type. */
32360 * The completion ring to send the completion event on. This should
32361 * be the NQ ID returned from the `nq_alloc` HWRM command.
32363 uint16_t cmpl_ring;
32365 * The sequence ID is used by the driver for tracking multiple
32366 * commands. This ID is treated as opaque data by the firmware and
32367 * the value is returned in the `hwrm_resp_hdr` upon completion.
32371 * The target ID of the command:
32372 * * 0x0-0xFFF8 - The function ID
32373 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
32374 * * 0xFFFD - Reserved for user-space HWRM interface
32377 uint16_t target_id;
32379 * A physical address pointer pointing to a host buffer that the
32380 * command's response data will be written. This can be either a host
32381 * physical address (HPA) or a guest physical address (GPA) and must
32382 * point to a physically contiguous block of memory.
32384 uint64_t resp_addr;
32385 } __attribute__((packed));
32387 /* hwrm_nvm_get_dir_info_output (size:192b/24B) */
32388 struct hwrm_nvm_get_dir_info_output {
32389 /* The specific error status for the command. */
32390 uint16_t error_code;
32391 /* The HWRM command request type. */
32393 /* The sequence ID from the original command. */
32395 /* The length of the response data in number of bytes. */
32397 /* Number of directory entries in the directory. */
32399 /* Size of each directory entry, in bytes. */
32400 uint32_t entry_length;
32401 uint8_t unused_0[7];
32403 * This field is used in Output records to indicate that the output
32404 * is completely written to RAM. This field should be read as '1'
32405 * to indicate that the output has been completely written.
32406 * When writing a command completion or response to an internal processor,
32407 * the order of writes has to be such that this field is written last.
32410 } __attribute__((packed));
32412 /******************
32414 ******************/
32417 /* hwrm_nvm_write_input (size:384b/48B) */
32418 struct hwrm_nvm_write_input {
32419 /* The HWRM command request type. */
32422 * The completion ring to send the completion event on. This should
32423 * be the NQ ID returned from the `nq_alloc` HWRM command.
32425 uint16_t cmpl_ring;
32427 * The sequence ID is used by the driver for tracking multiple
32428 * commands. This ID is treated as opaque data by the firmware and
32429 * the value is returned in the `hwrm_resp_hdr` upon completion.
32433 * The target ID of the command:
32434 * * 0x0-0xFFF8 - The function ID
32435 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
32436 * * 0xFFFD - Reserved for user-space HWRM interface
32439 uint16_t target_id;
32441 * A physical address pointer pointing to a host buffer that the
32442 * command's response data will be written. This can be either a host
32443 * physical address (HPA) or a guest physical address (GPA) and must
32444 * point to a physically contiguous block of memory.
32446 uint64_t resp_addr;
32448 * 64-bit Host Source Address.
32449 * This is where the source data is.
32451 uint64_t host_src_addr;
32452 /* The Directory Entry Type (valid values are defined in the bnxnvm_directory_type enum defined in the file bnxnvm_defs.h). */
32455 * Directory ordinal.
32456 * The 0-based instance of the combined Directory Entry Type and Extension.
32458 uint16_t dir_ordinal;
32459 /* The Directory Entry Extension flags (see BNX_DIR_EXT_* in the file bnxnvm_defs.h). */
32461 /* Directory Entry Attribute flags (see BNX_DIR_ATTR_* in the file bnxnvm_defs.h). */
32464 * Length of data to write, in bytes. May be less than or equal to the allocated size for the directory entry.
32465 * The data length stored in the directory entry will be updated to reflect this value once the write is complete.
32467 uint32_t dir_data_length;
32472 * When this bit is '1', the original active image
32473 * will not be removed. TBD: what purpose is this?
32475 #define HWRM_NVM_WRITE_INPUT_FLAGS_KEEP_ORIG_ACTIVE_IMG \
32478 * The requested length of the allocated NVM for the item, in bytes. This value may be greater than or equal to the specified data length (dir_data_length).
32479 * If this value is less than the specified data length, it will be ignored.
32480 * The response will contain the actual allocated item length, which may be greater than the requested item length.
32481 * The purpose for allocating more than the required number of bytes for an item's data is to pre-allocate extra storage (padding) to accomodate
32482 * the potential future growth of an item (e.g. upgraded firmware with a size increase, log growth, expanded configuration data).
32484 uint32_t dir_item_length;
32486 } __attribute__((packed));
32488 /* hwrm_nvm_write_output (size:128b/16B) */
32489 struct hwrm_nvm_write_output {
32490 /* The specific error status for the command. */
32491 uint16_t error_code;
32492 /* The HWRM command request type. */
32494 /* The sequence ID from the original command. */
32496 /* The length of the response data in number of bytes. */
32499 * Length of the allocated NVM for the item, in bytes. The value may be greater than or equal to the specified data length or the requested item length.
32500 * The actual item length used when creating a new directory entry will be a multiple of an NVM block size.
32502 uint32_t dir_item_length;
32503 /* The directory index of the created or modified item. */
32507 * This field is used in Output records to indicate that the output
32508 * is completely written to RAM. This field should be read as '1'
32509 * to indicate that the output has been completely written.
32510 * When writing a command completion or response to an internal processor,
32511 * the order of writes has to be such that this field is written last.
32514 } __attribute__((packed));
32516 /* hwrm_nvm_write_cmd_err (size:64b/8B) */
32517 struct hwrm_nvm_write_cmd_err {
32519 * command specific error codes that goes to
32520 * the cmd_err field in Common HWRM Error Response.
32523 /* Unknown error */
32524 #define HWRM_NVM_WRITE_CMD_ERR_CODE_UNKNOWN UINT32_C(0x0)
32525 /* Unable to complete operation due to fragmentation */
32526 #define HWRM_NVM_WRITE_CMD_ERR_CODE_FRAG_ERR UINT32_C(0x1)
32527 /* nvm is completely full. */
32528 #define HWRM_NVM_WRITE_CMD_ERR_CODE_NO_SPACE UINT32_C(0x2)
32529 #define HWRM_NVM_WRITE_CMD_ERR_CODE_LAST \
32530 HWRM_NVM_WRITE_CMD_ERR_CODE_NO_SPACE
32531 uint8_t unused_0[7];
32532 } __attribute__((packed));
32534 /*******************
32535 * hwrm_nvm_modify *
32536 *******************/
32539 /* hwrm_nvm_modify_input (size:320b/40B) */
32540 struct hwrm_nvm_modify_input {
32541 /* The HWRM command request type. */
32544 * The completion ring to send the completion event on. This should
32545 * be the NQ ID returned from the `nq_alloc` HWRM command.
32547 uint16_t cmpl_ring;
32549 * The sequence ID is used by the driver for tracking multiple
32550 * commands. This ID is treated as opaque data by the firmware and
32551 * the value is returned in the `hwrm_resp_hdr` upon completion.
32555 * The target ID of the command:
32556 * * 0x0-0xFFF8 - The function ID
32557 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
32558 * * 0xFFFD - Reserved for user-space HWRM interface
32561 uint16_t target_id;
32563 * A physical address pointer pointing to a host buffer that the
32564 * command's response data will be written. This can be either a host
32565 * physical address (HPA) or a guest physical address (GPA) and must
32566 * point to a physically contiguous block of memory.
32568 uint64_t resp_addr;
32570 * 64-bit Host Source Address.
32571 * This is where the modified data is.
32573 uint64_t host_src_addr;
32574 /* 16-bit directory entry index. */
32576 uint8_t unused_0[2];
32577 /* 32-bit NVRAM byte-offset to modify content from. */
32580 * Length of data to be modified, in bytes. The length shall
32584 uint8_t unused_1[4];
32585 } __attribute__((packed));
32587 /* hwrm_nvm_modify_output (size:128b/16B) */
32588 struct hwrm_nvm_modify_output {
32589 /* The specific error status for the command. */
32590 uint16_t error_code;
32591 /* The HWRM command request type. */
32593 /* The sequence ID from the original command. */
32595 /* The length of the response data in number of bytes. */
32597 uint8_t unused_0[7];
32599 * This field is used in Output records to indicate that the output
32600 * is completely written to RAM. This field should be read as '1'
32601 * to indicate that the output has been completely written.
32602 * When writing a command completion or response to an internal processor,
32603 * the order of writes has to be such that this field is written last.
32606 } __attribute__((packed));
32608 /***************************
32609 * hwrm_nvm_find_dir_entry *
32610 ***************************/
32613 /* hwrm_nvm_find_dir_entry_input (size:256b/32B) */
32614 struct hwrm_nvm_find_dir_entry_input {
32615 /* The HWRM command request type. */
32618 * The completion ring to send the completion event on. This should
32619 * be the NQ ID returned from the `nq_alloc` HWRM command.
32621 uint16_t cmpl_ring;
32623 * The sequence ID is used by the driver for tracking multiple
32624 * commands. This ID is treated as opaque data by the firmware and
32625 * the value is returned in the `hwrm_resp_hdr` upon completion.
32629 * The target ID of the command:
32630 * * 0x0-0xFFF8 - The function ID
32631 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
32632 * * 0xFFFD - Reserved for user-space HWRM interface
32635 uint16_t target_id;
32637 * A physical address pointer pointing to a host buffer that the
32638 * command's response data will be written. This can be either a host
32639 * physical address (HPA) or a guest physical address (GPA) and must
32640 * point to a physically contiguous block of memory.
32642 uint64_t resp_addr;
32645 * This bit must be '1' for the dir_idx_valid field to be
32648 #define HWRM_NVM_FIND_DIR_ENTRY_INPUT_ENABLES_DIR_IDX_VALID \
32650 /* Directory Entry Index */
32652 /* Directory Entry (Image) Type */
32655 * Directory ordinal.
32656 * The instance of this Directory Type
32658 uint16_t dir_ordinal;
32659 /* The Directory Entry Extension flags. */
32661 /* This value indicates the search option using dir_ordinal. */
32662 uint8_t opt_ordinal;
32663 /* This value indicates the search option using dir_ordinal. */
32664 #define HWRM_NVM_FIND_DIR_ENTRY_INPUT_OPT_ORDINAL_MASK UINT32_C(0x3)
32665 #define HWRM_NVM_FIND_DIR_ENTRY_INPUT_OPT_ORDINAL_SFT 0
32666 /* Equal to specified ordinal value. */
32667 #define HWRM_NVM_FIND_DIR_ENTRY_INPUT_OPT_ORDINAL_EQ UINT32_C(0x0)
32668 /* Greater than or equal to specified ordinal value */
32669 #define HWRM_NVM_FIND_DIR_ENTRY_INPUT_OPT_ORDINAL_GE UINT32_C(0x1)
32670 /* Greater than specified ordinal value */
32671 #define HWRM_NVM_FIND_DIR_ENTRY_INPUT_OPT_ORDINAL_GT UINT32_C(0x2)
32672 #define HWRM_NVM_FIND_DIR_ENTRY_INPUT_OPT_ORDINAL_LAST \
32673 HWRM_NVM_FIND_DIR_ENTRY_INPUT_OPT_ORDINAL_GT
32674 uint8_t unused_0[3];
32675 } __attribute__((packed));
32677 /* hwrm_nvm_find_dir_entry_output (size:256b/32B) */
32678 struct hwrm_nvm_find_dir_entry_output {
32679 /* The specific error status for the command. */
32680 uint16_t error_code;
32681 /* The HWRM command request type. */
32683 /* The sequence ID from the original command. */
32685 /* The length of the response data in number of bytes. */
32687 /* Allocated NVRAM for this directory entry, in bytes. */
32688 uint32_t dir_item_length;
32689 /* Size of the stored data for this directory entry, in bytes. */
32690 uint32_t dir_data_length;
32692 * Firmware version.
32693 * Only valid if the directory entry is for embedded firmware stored in APE_BIN Format.
32696 /* Directory ordinal. */
32697 uint16_t dir_ordinal;
32698 /* Directory Entry Index */
32700 uint8_t unused_0[7];
32702 * This field is used in Output records to indicate that the output
32703 * is completely written to RAM. This field should be read as '1'
32704 * to indicate that the output has been completely written.
32705 * When writing a command completion or response to an internal processor,
32706 * the order of writes has to be such that this field is written last.
32709 } __attribute__((packed));
32711 /****************************
32712 * hwrm_nvm_erase_dir_entry *
32713 ****************************/
32716 /* hwrm_nvm_erase_dir_entry_input (size:192b/24B) */
32717 struct hwrm_nvm_erase_dir_entry_input {
32718 /* The HWRM command request type. */
32721 * The completion ring to send the completion event on. This should
32722 * be the NQ ID returned from the `nq_alloc` HWRM command.
32724 uint16_t cmpl_ring;
32726 * The sequence ID is used by the driver for tracking multiple
32727 * commands. This ID is treated as opaque data by the firmware and
32728 * the value is returned in the `hwrm_resp_hdr` upon completion.
32732 * The target ID of the command:
32733 * * 0x0-0xFFF8 - The function ID
32734 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
32735 * * 0xFFFD - Reserved for user-space HWRM interface
32738 uint16_t target_id;
32740 * A physical address pointer pointing to a host buffer that the
32741 * command's response data will be written. This can be either a host
32742 * physical address (HPA) or a guest physical address (GPA) and must
32743 * point to a physically contiguous block of memory.
32745 uint64_t resp_addr;
32746 /* Directory Entry Index */
32748 uint8_t unused_0[6];
32749 } __attribute__((packed));
32751 /* hwrm_nvm_erase_dir_entry_output (size:128b/16B) */
32752 struct hwrm_nvm_erase_dir_entry_output {
32753 /* The specific error status for the command. */
32754 uint16_t error_code;
32755 /* The HWRM command request type. */
32757 /* The sequence ID from the original command. */
32759 /* The length of the response data in number of bytes. */
32761 uint8_t unused_0[7];
32763 * This field is used in Output records to indicate that the output
32764 * is completely written to RAM. This field should be read as '1'
32765 * to indicate that the output has been completely written.
32766 * When writing a command completion or response to an internal processor,
32767 * the order of writes has to be such that this field is written last.
32770 } __attribute__((packed));
32772 /*************************
32773 * hwrm_nvm_get_dev_info *
32774 *************************/
32777 /* hwrm_nvm_get_dev_info_input (size:128b/16B) */
32778 struct hwrm_nvm_get_dev_info_input {
32779 /* The HWRM command request type. */
32782 * The completion ring to send the completion event on. This should
32783 * be the NQ ID returned from the `nq_alloc` HWRM command.
32785 uint16_t cmpl_ring;
32787 * The sequence ID is used by the driver for tracking multiple
32788 * commands. This ID is treated as opaque data by the firmware and
32789 * the value is returned in the `hwrm_resp_hdr` upon completion.
32793 * The target ID of the command:
32794 * * 0x0-0xFFF8 - The function ID
32795 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
32796 * * 0xFFFD - Reserved for user-space HWRM interface
32799 uint16_t target_id;
32801 * A physical address pointer pointing to a host buffer that the
32802 * command's response data will be written. This can be either a host
32803 * physical address (HPA) or a guest physical address (GPA) and must
32804 * point to a physically contiguous block of memory.
32806 uint64_t resp_addr;
32807 } __attribute__((packed));
32809 /* hwrm_nvm_get_dev_info_output (size:256b/32B) */
32810 struct hwrm_nvm_get_dev_info_output {
32811 /* The specific error status for the command. */
32812 uint16_t error_code;
32813 /* The HWRM command request type. */
32815 /* The sequence ID from the original command. */
32817 /* The length of the response data in number of bytes. */
32819 /* Manufacturer ID. */
32820 uint16_t manufacturer_id;
32822 uint16_t device_id;
32823 /* Sector size of the NVRAM device. */
32824 uint32_t sector_size;
32825 /* Total size, in bytes of the NVRAM device. */
32826 uint32_t nvram_size;
32827 uint32_t reserved_size;
32828 /* Available size that can be used, in bytes. Available size is the NVRAM size take away the used size and reserved size. */
32829 uint32_t available_size;
32830 /* This field represents the major version of NVM cfg */
32831 uint8_t nvm_cfg_ver_maj;
32832 /* This field represents the minor version of NVM cfg */
32833 uint8_t nvm_cfg_ver_min;
32834 /* This field represents the update version of NVM cfg */
32835 uint8_t nvm_cfg_ver_upd;
32837 * This field is used in Output records to indicate that the output
32838 * is completely written to RAM. This field should be read as '1'
32839 * to indicate that the output has been completely written.
32840 * When writing a command completion or response to an internal processor,
32841 * the order of writes has to be such that this field is written last.
32844 } __attribute__((packed));
32846 /**************************
32847 * hwrm_nvm_mod_dir_entry *
32848 **************************/
32851 /* hwrm_nvm_mod_dir_entry_input (size:256b/32B) */
32852 struct hwrm_nvm_mod_dir_entry_input {
32853 /* The HWRM command request type. */
32856 * The completion ring to send the completion event on. This should
32857 * be the NQ ID returned from the `nq_alloc` HWRM command.
32859 uint16_t cmpl_ring;
32861 * The sequence ID is used by the driver for tracking multiple
32862 * commands. This ID is treated as opaque data by the firmware and
32863 * the value is returned in the `hwrm_resp_hdr` upon completion.
32867 * The target ID of the command:
32868 * * 0x0-0xFFF8 - The function ID
32869 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
32870 * * 0xFFFD - Reserved for user-space HWRM interface
32873 uint16_t target_id;
32875 * A physical address pointer pointing to a host buffer that the
32876 * command's response data will be written. This can be either a host
32877 * physical address (HPA) or a guest physical address (GPA) and must
32878 * point to a physically contiguous block of memory.
32880 uint64_t resp_addr;
32883 * This bit must be '1' for the checksum field to be
32886 #define HWRM_NVM_MOD_DIR_ENTRY_INPUT_ENABLES_CHECKSUM UINT32_C(0x1)
32887 /* Directory Entry Index */
32890 * Directory ordinal.
32891 * The (0-based) instance of this Directory Type.
32893 uint16_t dir_ordinal;
32894 /* The Directory Entry Extension flags (see BNX_DIR_EXT_* for extension flag definitions). */
32896 /* Directory Entry Attribute flags (see BNX_DIR_ATTR_* for attribute flag definitions). */
32899 * If valid, then this field updates the checksum
32900 * value of the content in the directory entry.
32903 } __attribute__((packed));
32905 /* hwrm_nvm_mod_dir_entry_output (size:128b/16B) */
32906 struct hwrm_nvm_mod_dir_entry_output {
32907 /* The specific error status for the command. */
32908 uint16_t error_code;
32909 /* The HWRM command request type. */
32911 /* The sequence ID from the original command. */
32913 /* The length of the response data in number of bytes. */
32915 uint8_t unused_0[7];
32917 * This field is used in Output records to indicate that the output
32918 * is completely written to RAM. This field should be read as '1'
32919 * to indicate that the output has been completely written.
32920 * When writing a command completion or response to an internal processor,
32921 * the order of writes has to be such that this field is written last.
32924 } __attribute__((packed));
32926 /**************************
32927 * hwrm_nvm_verify_update *
32928 **************************/
32931 /* hwrm_nvm_verify_update_input (size:192b/24B) */
32932 struct hwrm_nvm_verify_update_input {
32933 /* The HWRM command request type. */
32936 * The completion ring to send the completion event on. This should
32937 * be the NQ ID returned from the `nq_alloc` HWRM command.
32939 uint16_t cmpl_ring;
32941 * The sequence ID is used by the driver for tracking multiple
32942 * commands. This ID is treated as opaque data by the firmware and
32943 * the value is returned in the `hwrm_resp_hdr` upon completion.
32947 * The target ID of the command:
32948 * * 0x0-0xFFF8 - The function ID
32949 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
32950 * * 0xFFFD - Reserved for user-space HWRM interface
32953 uint16_t target_id;
32955 * A physical address pointer pointing to a host buffer that the
32956 * command's response data will be written. This can be either a host
32957 * physical address (HPA) or a guest physical address (GPA) and must
32958 * point to a physically contiguous block of memory.
32960 uint64_t resp_addr;
32961 /* Directory Entry Type, to be verified. */
32964 * Directory ordinal.
32965 * The instance of the Directory Type to be verified.
32967 uint16_t dir_ordinal;
32969 * The Directory Entry Extension flags.
32970 * The "UPDATE" extension flag must be set in this value.
32971 * A corresponding directory entry with the same type and ordinal values but *without*
32972 * the "UPDATE" extension flag must also exist. The other flags of the extension must
32973 * be identical between the active and update entries.
32976 uint8_t unused_0[2];
32977 } __attribute__((packed));
32979 /* hwrm_nvm_verify_update_output (size:128b/16B) */
32980 struct hwrm_nvm_verify_update_output {
32981 /* The specific error status for the command. */
32982 uint16_t error_code;
32983 /* The HWRM command request type. */
32985 /* The sequence ID from the original command. */
32987 /* The length of the response data in number of bytes. */
32989 uint8_t unused_0[7];
32991 * This field is used in Output records to indicate that the output
32992 * is completely written to RAM. This field should be read as '1'
32993 * to indicate that the output has been completely written.
32994 * When writing a command completion or response to an internal processor,
32995 * the order of writes has to be such that this field is written last.
32998 } __attribute__((packed));
33000 /***************************
33001 * hwrm_nvm_install_update *
33002 ***************************/
33005 /* hwrm_nvm_install_update_input (size:192b/24B) */
33006 struct hwrm_nvm_install_update_input {
33007 /* The HWRM command request type. */
33010 * The completion ring to send the completion event on. This should
33011 * be the NQ ID returned from the `nq_alloc` HWRM command.
33013 uint16_t cmpl_ring;
33015 * The sequence ID is used by the driver for tracking multiple
33016 * commands. This ID is treated as opaque data by the firmware and
33017 * the value is returned in the `hwrm_resp_hdr` upon completion.
33021 * The target ID of the command:
33022 * * 0x0-0xFFF8 - The function ID
33023 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
33024 * * 0xFFFD - Reserved for user-space HWRM interface
33027 uint16_t target_id;
33029 * A physical address pointer pointing to a host buffer that the
33030 * command's response data will be written. This can be either a host
33031 * physical address (HPA) or a guest physical address (GPA) and must
33032 * point to a physically contiguous block of memory.
33034 uint64_t resp_addr;
33036 * Installation type. If the value 3 through 0xffff is used,
33037 * only packaged items with that type value will be installed and
33038 * conditional installation directives for those packaged items
33039 * will be over-ridden (i.e. 'create' or 'replace' will be treated
33042 uint32_t install_type;
33044 * Perform a normal package installation. Conditional installation
33045 * directives (e.g. 'create' and 'replace') of packaged items
33046 * will be followed.
33048 #define HWRM_NVM_INSTALL_UPDATE_INPUT_INSTALL_TYPE_NORMAL UINT32_C(0x0)
33050 * Install all packaged items regardless of installation directive
33051 * (i.e. treat all packaged items as though they have an installation
33052 * directive of 'install').
33054 #define HWRM_NVM_INSTALL_UPDATE_INPUT_INSTALL_TYPE_ALL \
33055 UINT32_C(0xffffffff)
33056 #define HWRM_NVM_INSTALL_UPDATE_INPUT_INSTALL_TYPE_LAST \
33057 HWRM_NVM_INSTALL_UPDATE_INPUT_INSTALL_TYPE_ALL
33059 /* If set to 1, then securely erase all unused locations in persistent storage. */
33060 #define HWRM_NVM_INSTALL_UPDATE_INPUT_FLAGS_ERASE_UNUSED_SPACE \
33063 * If set to 1, then unspecifed images, images not in the package file, will be safely deleted.
33064 * When combined with erase_unused_space then unspecified images will be securely erased.
33066 #define HWRM_NVM_INSTALL_UPDATE_INPUT_FLAGS_REMOVE_UNUSED_PKG \
33069 * If set to 1, FW will defragment the NVM if defragmentation is required for the update.
33070 * Allow additional time for this command to complete if this bit is set to 1.
33072 #define HWRM_NVM_INSTALL_UPDATE_INPUT_FLAGS_ALLOWED_TO_DEFRAG \
33074 uint8_t unused_0[2];
33075 } __attribute__((packed));
33077 /* hwrm_nvm_install_update_output (size:192b/24B) */
33078 struct hwrm_nvm_install_update_output {
33079 /* The specific error status for the command. */
33080 uint16_t error_code;
33081 /* The HWRM command request type. */
33083 /* The sequence ID from the original command. */
33085 /* The length of the response data in number of bytes. */
33088 * Bit-mask of successfully installed items.
33089 * Bit-0 corresponding to the first packaged item, Bit-1 for the second item, etc.
33090 * A value of 0 indicates that no items were successfully installed.
33092 uint64_t installed_items;
33093 /* result is 8 b */
33095 /* There was no problem with the package installation. */
33096 #define HWRM_NVM_INSTALL_UPDATE_OUTPUT_RESULT_SUCCESS UINT32_C(0x0)
33097 #define HWRM_NVM_INSTALL_UPDATE_OUTPUT_RESULT_LAST \
33098 HWRM_NVM_INSTALL_UPDATE_OUTPUT_RESULT_SUCCESS
33099 /* problem_item is 8 b */
33100 uint8_t problem_item;
33101 /* There was no problem with any packaged items. */
33102 #define HWRM_NVM_INSTALL_UPDATE_OUTPUT_PROBLEM_ITEM_NONE \
33104 /* There was a problem with the NVM package itself. */
33105 #define HWRM_NVM_INSTALL_UPDATE_OUTPUT_PROBLEM_ITEM_PACKAGE \
33107 #define HWRM_NVM_INSTALL_UPDATE_OUTPUT_PROBLEM_ITEM_LAST \
33108 HWRM_NVM_INSTALL_UPDATE_OUTPUT_PROBLEM_ITEM_PACKAGE
33109 /* reset_required is 8 b */
33110 uint8_t reset_required;
33112 * No reset is required for installed/updated firmware or
33113 * microcode to take effect.
33115 #define HWRM_NVM_INSTALL_UPDATE_OUTPUT_RESET_REQUIRED_NONE \
33118 * A PCIe reset (e.g. system reboot) is
33119 * required for newly installed/updated firmware or
33120 * microcode to take effect.
33122 #define HWRM_NVM_INSTALL_UPDATE_OUTPUT_RESET_REQUIRED_PCI \
33125 * A controller power reset (e.g. system power-cycle) is
33126 * required for newly installed/updated firmware or
33127 * microcode to take effect. Some newly installed/updated
33128 * firmware or microcode may still take effect upon the
33131 #define HWRM_NVM_INSTALL_UPDATE_OUTPUT_RESET_REQUIRED_POWER \
33133 #define HWRM_NVM_INSTALL_UPDATE_OUTPUT_RESET_REQUIRED_LAST \
33134 HWRM_NVM_INSTALL_UPDATE_OUTPUT_RESET_REQUIRED_POWER
33135 uint8_t unused_0[4];
33137 * This field is used in Output records to indicate that the output
33138 * is completely written to RAM. This field should be read as '1'
33139 * to indicate that the output has been completely written.
33140 * When writing a command completion or response to an internal processor,
33141 * the order of writes has to be such that this field is written last.
33144 } __attribute__((packed));
33146 /* hwrm_nvm_install_update_cmd_err (size:64b/8B) */
33147 struct hwrm_nvm_install_update_cmd_err {
33149 * command specific error codes that goes to
33150 * the cmd_err field in Common HWRM Error Response.
33153 /* Unknown error */
33154 #define HWRM_NVM_INSTALL_UPDATE_CMD_ERR_CODE_UNKNOWN UINT32_C(0x0)
33155 /* Unable to complete operation due to fragmentation */
33156 #define HWRM_NVM_INSTALL_UPDATE_CMD_ERR_CODE_FRAG_ERR UINT32_C(0x1)
33157 /* nvm is completely full. */
33158 #define HWRM_NVM_INSTALL_UPDATE_CMD_ERR_CODE_NO_SPACE UINT32_C(0x2)
33159 #define HWRM_NVM_INSTALL_UPDATE_CMD_ERR_CODE_LAST \
33160 HWRM_NVM_INSTALL_UPDATE_CMD_ERR_CODE_NO_SPACE
33161 uint8_t unused_0[7];
33162 } __attribute__((packed));
33164 /******************
33166 ******************/
33169 /* hwrm_nvm_flush_input (size:128b/16B) */
33170 struct hwrm_nvm_flush_input {
33171 /* The HWRM command request type. */
33174 * The completion ring to send the completion event on. This should
33175 * be the NQ ID returned from the `nq_alloc` HWRM command.
33177 uint16_t cmpl_ring;
33179 * The sequence ID is used by the driver for tracking multiple
33180 * commands. This ID is treated as opaque data by the firmware and
33181 * the value is returned in the `hwrm_resp_hdr` upon completion.
33185 * The target ID of the command:
33186 * * 0x0-0xFFF8 - The function ID
33187 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
33188 * * 0xFFFD - Reserved for user-space HWRM interface
33191 uint16_t target_id;
33193 * A physical address pointer pointing to a host buffer that the
33194 * command's response data will be written. This can be either a host
33195 * physical address (HPA) or a guest physical address (GPA) and must
33196 * point to a physically contiguous block of memory.
33198 uint64_t resp_addr;
33199 } __attribute__((packed));
33201 /* hwrm_nvm_flush_output (size:128b/16B) */
33202 struct hwrm_nvm_flush_output {
33203 /* The specific error status for the command. */
33204 uint16_t error_code;
33205 /* The HWRM command request type. */
33207 /* The sequence ID from the original command. */
33209 /* The length of the response data in number of bytes. */
33211 uint8_t unused_0[7];
33213 * This field is used in Output records to indicate that the output
33214 * is completely written to RAM. This field should be read as '1'
33215 * to indicate that the output has been completely written.
33216 * When writing a command completion or response to an internal processor,
33217 * the order of writes has to be such that this field is written last.
33220 } __attribute__((packed));
33222 /* hwrm_nvm_flush_cmd_err (size:64b/8B) */
33223 struct hwrm_nvm_flush_cmd_err {
33225 * command specific error codes that goes to
33226 * the cmd_err field in Common HWRM Error Response.
33229 /* Unknown error */
33230 #define HWRM_NVM_FLUSH_CMD_ERR_CODE_UNKNOWN UINT32_C(0x0)
33231 /* flush could not be performed */
33232 #define HWRM_NVM_FLUSH_CMD_ERR_CODE_FAIL UINT32_C(0x1)
33233 #define HWRM_NVM_FLUSH_CMD_ERR_CODE_LAST \
33234 HWRM_NVM_FLUSH_CMD_ERR_CODE_FAIL
33235 uint8_t unused_0[7];
33236 } __attribute__((packed));
33238 /*************************
33239 * hwrm_nvm_get_variable *
33240 *************************/
33243 /* hwrm_nvm_get_variable_input (size:320b/40B) */
33244 struct hwrm_nvm_get_variable_input {
33245 /* The HWRM command request type. */
33248 * The completion ring to send the completion event on. This should
33249 * be the NQ ID returned from the `nq_alloc` HWRM command.
33251 uint16_t cmpl_ring;
33253 * The sequence ID is used by the driver for tracking multiple
33254 * commands. This ID is treated as opaque data by the firmware and
33255 * the value is returned in the `hwrm_resp_hdr` upon completion.
33259 * The target ID of the command:
33260 * * 0x0-0xFFF8 - The function ID
33261 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
33262 * * 0xFFFD - Reserved for user-space HWRM interface
33265 uint16_t target_id;
33267 * A physical address pointer pointing to a host buffer that the
33268 * command's response data will be written. This can be either a host
33269 * physical address (HPA) or a guest physical address (GPA) and must
33270 * point to a physically contiguous block of memory.
33272 uint64_t resp_addr;
33274 * This is the host address where
33275 * nvm variable will be stored
33277 uint64_t dest_data_addr;
33278 /* size of data in bits */
33280 /* nvm cfg option number */
33281 uint16_t option_num;
33283 #define HWRM_NVM_GET_VARIABLE_INPUT_OPTION_NUM_RSVD_0 UINT32_C(0x0)
33285 #define HWRM_NVM_GET_VARIABLE_INPUT_OPTION_NUM_RSVD_FFFF \
33287 #define HWRM_NVM_GET_VARIABLE_INPUT_OPTION_NUM_LAST \
33288 HWRM_NVM_GET_VARIABLE_INPUT_OPTION_NUM_RSVD_FFFF
33290 * Number of dimensions for this nvm configuration variable.
33291 * This value indicates how many of the indexN values to use.
33292 * A value of 0 means that none of the indexN values are valid.
33293 * A value of 1 requires at index0 is valued, a value of 2
33294 * requires that index0 and index1 are valid, and so forth
33296 uint16_t dimensions;
33297 /* index for the 1st dimensions */
33299 /* index for the 2nd dimensions */
33301 /* index for the 3rd dimensions */
33303 /* index for the 4th dimensions */
33307 * When this bit is set to 1, the factory default value will be returned,
33308 * 0 returns the operational value.
33310 #define HWRM_NVM_GET_VARIABLE_INPUT_FLAGS_FACTORY_DFLT \
33313 } __attribute__((packed));
33315 /* hwrm_nvm_get_variable_output (size:128b/16B) */
33316 struct hwrm_nvm_get_variable_output {
33317 /* The specific error status for the command. */
33318 uint16_t error_code;
33319 /* The HWRM command request type. */
33321 /* The sequence ID from the original command. */
33323 /* The length of the response data in number of bytes. */
33325 /* size of data of the actual variable retrieved in bits */
33328 * option_num is the option number for the data retrieved. It is possible in the
33329 * future that the option number returned would be different than requested. This
33330 * condition could occur if an option is deprecated and a new option id is defined
33331 * with similar characteristics, but has a slightly different definition. This
33332 * also makes it convenient for the caller to identify the variable result with
33333 * the option id from the response.
33335 uint16_t option_num;
33337 #define HWRM_NVM_GET_VARIABLE_OUTPUT_OPTION_NUM_RSVD_0 UINT32_C(0x0)
33339 #define HWRM_NVM_GET_VARIABLE_OUTPUT_OPTION_NUM_RSVD_FFFF \
33341 #define HWRM_NVM_GET_VARIABLE_OUTPUT_OPTION_NUM_LAST \
33342 HWRM_NVM_GET_VARIABLE_OUTPUT_OPTION_NUM_RSVD_FFFF
33343 uint8_t unused_0[3];
33345 * This field is used in Output records to indicate that the output
33346 * is completely written to RAM. This field should be read as '1'
33347 * to indicate that the output has been completely written.
33348 * When writing a command completion or response to an internal processor,
33349 * the order of writes has to be such that this field is written last.
33352 } __attribute__((packed));
33354 /* hwrm_nvm_get_variable_cmd_err (size:64b/8B) */
33355 struct hwrm_nvm_get_variable_cmd_err {
33357 * command specific error codes that goes to
33358 * the cmd_err field in Common HWRM Error Response.
33361 /* Unknown error */
33362 #define HWRM_NVM_GET_VARIABLE_CMD_ERR_CODE_UNKNOWN UINT32_C(0x0)
33363 /* variable does not exist */
33364 #define HWRM_NVM_GET_VARIABLE_CMD_ERR_CODE_VAR_NOT_EXIST UINT32_C(0x1)
33365 /* configuration is corrupted and the variable cannot be saved */
33366 #define HWRM_NVM_GET_VARIABLE_CMD_ERR_CODE_CORRUPT_VAR UINT32_C(0x2)
33367 /* length specified is too small */
33368 #define HWRM_NVM_GET_VARIABLE_CMD_ERR_CODE_LEN_TOO_SHORT UINT32_C(0x3)
33369 #define HWRM_NVM_GET_VARIABLE_CMD_ERR_CODE_LAST \
33370 HWRM_NVM_GET_VARIABLE_CMD_ERR_CODE_LEN_TOO_SHORT
33371 uint8_t unused_0[7];
33372 } __attribute__((packed));
33374 /*************************
33375 * hwrm_nvm_set_variable *
33376 *************************/
33379 /* hwrm_nvm_set_variable_input (size:320b/40B) */
33380 struct hwrm_nvm_set_variable_input {
33381 /* The HWRM command request type. */
33384 * The completion ring to send the completion event on. This should
33385 * be the NQ ID returned from the `nq_alloc` HWRM command.
33387 uint16_t cmpl_ring;
33389 * The sequence ID is used by the driver for tracking multiple
33390 * commands. This ID is treated as opaque data by the firmware and
33391 * the value is returned in the `hwrm_resp_hdr` upon completion.
33395 * The target ID of the command:
33396 * * 0x0-0xFFF8 - The function ID
33397 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
33398 * * 0xFFFD - Reserved for user-space HWRM interface
33401 uint16_t target_id;
33403 * A physical address pointer pointing to a host buffer that the
33404 * command's response data will be written. This can be either a host
33405 * physical address (HPA) or a guest physical address (GPA) and must
33406 * point to a physically contiguous block of memory.
33408 uint64_t resp_addr;
33410 * This is the host address where
33411 * nvm variable will be copied from
33413 uint64_t src_data_addr;
33414 /* size of data in bits */
33416 /* nvm cfg option number */
33417 uint16_t option_num;
33419 #define HWRM_NVM_SET_VARIABLE_INPUT_OPTION_NUM_RSVD_0 UINT32_C(0x0)
33421 #define HWRM_NVM_SET_VARIABLE_INPUT_OPTION_NUM_RSVD_FFFF \
33423 #define HWRM_NVM_SET_VARIABLE_INPUT_OPTION_NUM_LAST \
33424 HWRM_NVM_SET_VARIABLE_INPUT_OPTION_NUM_RSVD_FFFF
33426 * Number of dimensions for this nvm configuration variable.
33427 * This value indicates how many of the indexN values to use.
33428 * A value of 0 means that none of the indexN values are valid.
33429 * A value of 1 requires at index0 is valued, a value of 2
33430 * requires that index0 and index1 are valid, and so forth
33432 uint16_t dimensions;
33433 /* index for the 1st dimensions */
33435 /* index for the 2nd dimensions */
33437 /* index for the 3rd dimensions */
33439 /* index for the 4th dimensions */
33442 /* When this bit is 1, flush internal cache after this write operation (see hwrm_nvm_flush command.) */
33443 #define HWRM_NVM_SET_VARIABLE_INPUT_FLAGS_FORCE_FLUSH \
33445 /* encryption method */
33446 #define HWRM_NVM_SET_VARIABLE_INPUT_FLAGS_ENCRYPT_MODE_MASK \
33448 #define HWRM_NVM_SET_VARIABLE_INPUT_FLAGS_ENCRYPT_MODE_SFT 1
33449 /* No encryption. */
33450 #define HWRM_NVM_SET_VARIABLE_INPUT_FLAGS_ENCRYPT_MODE_NONE \
33451 (UINT32_C(0x0) << 1)
33452 /* one-way encryption. */
33453 #define HWRM_NVM_SET_VARIABLE_INPUT_FLAGS_ENCRYPT_MODE_HMAC_SHA1 \
33454 (UINT32_C(0x1) << 1)
33455 /* symmetric AES256 encryption. */
33456 #define HWRM_NVM_SET_VARIABLE_INPUT_FLAGS_ENCRYPT_MODE_AES256 \
33457 (UINT32_C(0x2) << 1)
33458 /* SHA1 digest appended to plaintext contents, for authentication */
33459 #define HWRM_NVM_SET_VARIABLE_INPUT_FLAGS_ENCRYPT_MODE_HMAC_SHA1_AUTH \
33460 (UINT32_C(0x3) << 1)
33461 #define HWRM_NVM_SET_VARIABLE_INPUT_FLAGS_ENCRYPT_MODE_LAST \
33462 HWRM_NVM_SET_VARIABLE_INPUT_FLAGS_ENCRYPT_MODE_HMAC_SHA1_AUTH
33463 #define HWRM_NVM_SET_VARIABLE_INPUT_FLAGS_FLAGS_UNUSED_0_MASK \
33465 #define HWRM_NVM_SET_VARIABLE_INPUT_FLAGS_FLAGS_UNUSED_0_SFT 4
33466 /* When this bit is 1, update the factory default region */
33467 #define HWRM_NVM_SET_VARIABLE_INPUT_FLAGS_FACTORY_DEFAULT \
33470 } __attribute__((packed));
33472 /* hwrm_nvm_set_variable_output (size:128b/16B) */
33473 struct hwrm_nvm_set_variable_output {
33474 /* The specific error status for the command. */
33475 uint16_t error_code;
33476 /* The HWRM command request type. */
33478 /* The sequence ID from the original command. */
33480 /* The length of the response data in number of bytes. */
33482 uint8_t unused_0[7];
33484 * This field is used in Output records to indicate that the output
33485 * is completely written to RAM. This field should be read as '1'
33486 * to indicate that the output has been completely written.
33487 * When writing a command completion or response to an internal processor,
33488 * the order of writes has to be such that this field is written last.
33491 } __attribute__((packed));
33493 /* hwrm_nvm_set_variable_cmd_err (size:64b/8B) */
33494 struct hwrm_nvm_set_variable_cmd_err {
33496 * command specific error codes that goes to
33497 * the cmd_err field in Common HWRM Error Response.
33500 /* Unknown error */
33501 #define HWRM_NVM_SET_VARIABLE_CMD_ERR_CODE_UNKNOWN UINT32_C(0x0)
33502 /* variable does not exist */
33503 #define HWRM_NVM_SET_VARIABLE_CMD_ERR_CODE_VAR_NOT_EXIST UINT32_C(0x1)
33504 /* configuration is corrupted and the variable cannot be saved */
33505 #define HWRM_NVM_SET_VARIABLE_CMD_ERR_CODE_CORRUPT_VAR UINT32_C(0x2)
33506 #define HWRM_NVM_SET_VARIABLE_CMD_ERR_CODE_LAST \
33507 HWRM_NVM_SET_VARIABLE_CMD_ERR_CODE_CORRUPT_VAR
33508 uint8_t unused_0[7];
33509 } __attribute__((packed));
33511 /****************************
33512 * hwrm_nvm_validate_option *
33513 ****************************/
33516 /* hwrm_nvm_validate_option_input (size:320b/40B) */
33517 struct hwrm_nvm_validate_option_input {
33518 /* The HWRM command request type. */
33521 * The completion ring to send the completion event on. This should
33522 * be the NQ ID returned from the `nq_alloc` HWRM command.
33524 uint16_t cmpl_ring;
33526 * The sequence ID is used by the driver for tracking multiple
33527 * commands. This ID is treated as opaque data by the firmware and
33528 * the value is returned in the `hwrm_resp_hdr` upon completion.
33532 * The target ID of the command:
33533 * * 0x0-0xFFF8 - The function ID
33534 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
33535 * * 0xFFFD - Reserved for user-space HWRM interface
33538 uint16_t target_id;
33540 * A physical address pointer pointing to a host buffer that the
33541 * command's response data will be written. This can be either a host
33542 * physical address (HPA) or a guest physical address (GPA) and must
33543 * point to a physically contiguous block of memory.
33545 uint64_t resp_addr;
33547 * This is the host address where
33548 * nvm variable will be copied from
33550 uint64_t src_data_addr;
33551 /* size of data in bits */
33553 /* nvm cfg option number */
33554 uint16_t option_num;
33556 #define HWRM_NVM_VALIDATE_OPTION_INPUT_OPTION_NUM_RSVD_0 \
33559 #define HWRM_NVM_VALIDATE_OPTION_INPUT_OPTION_NUM_RSVD_FFFF \
33561 #define HWRM_NVM_VALIDATE_OPTION_INPUT_OPTION_NUM_LAST \
33562 HWRM_NVM_VALIDATE_OPTION_INPUT_OPTION_NUM_RSVD_FFFF
33564 * Number of dimensions for this nvm configuration variable.
33565 * This value indicates how many of the indexN values to use.
33566 * A value of 0 means that none of the indexN values are valid.
33567 * A value of 1 requires at index0 is valued, a value of 2
33568 * requires that index0 and index1 are valid, and so forth
33570 uint16_t dimensions;
33571 /* index for the 1st dimensions */
33573 /* index for the 2nd dimensions */
33575 /* index for the 3rd dimensions */
33577 /* index for the 4th dimensions */
33579 uint8_t unused_0[2];
33580 } __attribute__((packed));
33582 /* hwrm_nvm_validate_option_output (size:128b/16B) */
33583 struct hwrm_nvm_validate_option_output {
33584 /* The specific error status for the command. */
33585 uint16_t error_code;
33586 /* The HWRM command request type. */
33588 /* The sequence ID from the original command. */
33590 /* The length of the response data in number of bytes. */
33593 /* indicates that the value provided for the option is not matching with the saved data. */
33594 #define HWRM_NVM_VALIDATE_OPTION_OUTPUT_RESULT_NOT_MATCH UINT32_C(0x0)
33595 /* indicates that the value provided for the option is matching the saved data. */
33596 #define HWRM_NVM_VALIDATE_OPTION_OUTPUT_RESULT_MATCH UINT32_C(0x1)
33597 #define HWRM_NVM_VALIDATE_OPTION_OUTPUT_RESULT_LAST \
33598 HWRM_NVM_VALIDATE_OPTION_OUTPUT_RESULT_MATCH
33599 uint8_t unused_0[6];
33601 * This field is used in Output records to indicate that the output
33602 * is completely written to RAM. This field should be read as '1'
33603 * to indicate that the output has been completely written.
33604 * When writing a command completion or response to an internal processor,
33605 * the order of writes has to be such that this field is written last.
33608 } __attribute__((packed));
33610 /* hwrm_nvm_validate_option_cmd_err (size:64b/8B) */
33611 struct hwrm_nvm_validate_option_cmd_err {
33613 * command specific error codes that goes to
33614 * the cmd_err field in Common HWRM Error Response.
33617 /* Unknown error */
33618 #define HWRM_NVM_VALIDATE_OPTION_CMD_ERR_CODE_UNKNOWN UINT32_C(0x0)
33619 #define HWRM_NVM_VALIDATE_OPTION_CMD_ERR_CODE_LAST \
33620 HWRM_NVM_VALIDATE_OPTION_CMD_ERR_CODE_UNKNOWN
33621 uint8_t unused_0[7];
33622 } __attribute__((packed));
33624 #endif /* _HSI_STRUCT_DEF_DPDK_H_ */