1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright (c) 2014-2020 Broadcom Inc.
5 * DO NOT MODIFY!!! This file is automatically generated.
8 #ifndef _HSI_STRUCT_DEF_DPDK_H_
9 #define _HSI_STRUCT_DEF_DPDK_H_
11 /* This is the HWRM command header. */
12 /* hwrm_cmd_hdr (size:128b/16B) */
14 /* The HWRM command request type. */
17 * The completion ring to send the completion event on. This should
18 * be the NQ ID returned from the `nq_alloc` HWRM command.
22 * The sequence ID is used by the driver for tracking multiple
23 * commands. This ID is treated as opaque data by the firmware and
24 * the value is returned in the `hwrm_resp_hdr` upon completion.
28 * The target ID of the command:
29 * * 0x0-0xFFF8 - The function ID
30 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
31 * * 0xFFFD - Reserved for user-space HWRM interface
36 * A physical address pointer pointing to a host buffer that the
37 * command's response data will be written. This can be either a host
38 * physical address (HPA) or a guest physical address (GPA) and must
39 * point to a physically contiguous block of memory.
44 /* This is the HWRM response header. */
45 /* hwrm_resp_hdr (size:64b/8B) */
46 struct hwrm_resp_hdr {
47 /* The specific error status for the command. */
49 /* The HWRM command request type. */
51 /* The sequence ID from the original command. */
53 /* The length of the response data in number of bytes. */
58 * TLV encapsulated message. Use the TLV type field of the
59 * TLV to determine the type of message encapsulated.
61 #define CMD_DISCR_TLV_ENCAP UINT32_C(0x8000)
62 #define CMD_DISCR_LAST CMD_DISCR_TLV_ENCAP
65 /* HWRM request message */
66 #define TLV_TYPE_HWRM_REQUEST UINT32_C(0x1)
67 /* HWRM response message */
68 #define TLV_TYPE_HWRM_RESPONSE UINT32_C(0x2)
69 /* RoCE slow path command */
70 #define TLV_TYPE_ROCE_SP_COMMAND UINT32_C(0x3)
71 /* RoCE slow path command to query CC Gen1 support. */
72 #define TLV_TYPE_QUERY_ROCE_CC_GEN1 UINT32_C(0x4)
73 /* RoCE slow path command to modify CC Gen1 support. */
74 #define TLV_TYPE_MODIFY_ROCE_CC_GEN1 UINT32_C(0x5)
75 /* Engine CKV - The Alias key EC curve and ECC public key information. */
76 #define TLV_TYPE_ENGINE_CKV_ALIAS_ECC_PUBLIC_KEY UINT32_C(0x8001)
77 /* Engine CKV - Initialization vector. */
78 #define TLV_TYPE_ENGINE_CKV_IV UINT32_C(0x8003)
79 /* Engine CKV - Authentication tag. */
80 #define TLV_TYPE_ENGINE_CKV_AUTH_TAG UINT32_C(0x8004)
81 /* Engine CKV - The encrypted data. */
82 #define TLV_TYPE_ENGINE_CKV_CIPHERTEXT UINT32_C(0x8005)
83 /* Engine CKV - Supported host_algorithms. */
84 #define TLV_TYPE_ENGINE_CKV_HOST_ALGORITHMS UINT32_C(0x8006)
85 /* Engine CKV - The Host EC curve name and ECC public key information. */
86 #define TLV_TYPE_ENGINE_CKV_HOST_ECC_PUBLIC_KEY UINT32_C(0x8007)
87 /* Engine CKV - The ECDSA signature. */
88 #define TLV_TYPE_ENGINE_CKV_ECDSA_SIGNATURE UINT32_C(0x8008)
89 /* Engine CKV - The firmware EC curve name and ECC public key information. */
90 #define TLV_TYPE_ENGINE_CKV_FW_ECC_PUBLIC_KEY UINT32_C(0x8009)
91 /* Engine CKV - Supported firmware algorithms. */
92 #define TLV_TYPE_ENGINE_CKV_FW_ALGORITHMS UINT32_C(0x800a)
93 #define TLV_TYPE_LAST \
94 TLV_TYPE_ENGINE_CKV_FW_ALGORITHMS
97 /* tlv (size:64b/8B) */
100 * The command discriminator is used to differentiate between various
101 * types of HWRM messages. This includes legacy HWRM and RoCE slowpath
102 * command messages as well as newer TLV encapsulated HWRM commands.
104 * For TLV encapsulated messages this field must be 0x8000.
110 * Indicates the presence of additional TLV encapsulated data
113 #define TLV_FLAGS_MORE UINT32_C(0x1)
114 /* Last TLV in a sequence of TLVs. */
115 #define TLV_FLAGS_MORE_LAST UINT32_C(0x0)
116 /* More TLVs follow this TLV. */
117 #define TLV_FLAGS_MORE_NOT_LAST UINT32_C(0x1)
119 * When an HWRM receiver detects a TLV type that it does not
120 * support with the TLV required flag set, the receiver must
121 * reject the HWRM message with an error code indicating an
122 * unsupported TLV type.
124 #define TLV_FLAGS_REQUIRED UINT32_C(0x2)
126 #define TLV_FLAGS_REQUIRED_NO (UINT32_C(0x0) << 1)
128 #define TLV_FLAGS_REQUIRED_YES (UINT32_C(0x1) << 1)
129 #define TLV_FLAGS_REQUIRED_LAST TLV_FLAGS_REQUIRED_YES
131 * This field defines the TLV type value which is divided into
132 * two ranges to differentiate between global and local TLV types.
133 * Global TLV types must be unique across all defined TLV types.
134 * Local TLV types are valid only for extensions to a given
135 * HWRM message and may be repeated across different HWRM message
136 * types. There is a direct correlation of each HWRM message type
137 * to a single global TLV type value.
139 * Global TLV range: `0 - (63k-1)`
141 * Local TLV range: `63k - (64k-1)`
145 * Length of the message data encapsulated by this TLV in bytes.
146 * This length does not include the size of the TLV header itself
147 * and it must be an integer multiple of 8B.
153 /* input (size:128b/16B) */
156 * This value indicates what type of request this is. The format
157 * for the rest of the command is determined by this field.
161 * This value indicates the what completion ring the request will
162 * be optionally completed on. If the value is -1, then no
163 * CR completion will be generated. Any other value must be a
164 * valid CR ring_id value for this function.
167 /* This value indicates the command sequence number. */
170 * Target ID of this command.
172 * 0x0 - 0xFFF8 - Used for function ids
173 * 0xFFF8 - 0xFFFE - Reserved for internal processors
178 * This is the host address where the response will be written
179 * when the request is complete. This area must be 16B aligned
180 * and must be cleared to zero before the request is made.
186 /* output (size:64b/8B) */
189 * Pass/Fail or error type
191 * Note: receiver to verify the in parameters, and fail the call
192 * with an error when appropriate
195 /* This field returns the type of original request. */
197 /* This field provides original sequence number of the command. */
200 * This field is the length of the response in bytes. The
201 * last byte of the response is a valid flag that will read
202 * as '1' when the command has been completely written to
208 /* Short Command Structure */
209 /* hwrm_short_input (size:128b/16B) */
210 struct hwrm_short_input {
212 * This field indicates the type of request in the request buffer.
213 * The format for the rest of the command (request) is determined
218 * This field indicates a signature that is used to identify short
219 * form of the command listed here. This field shall be set to
223 /* Signature indicating this is a short form of HWRM command */
224 #define HWRM_SHORT_INPUT_SIGNATURE_SHORT_CMD UINT32_C(0x4321)
225 #define HWRM_SHORT_INPUT_SIGNATURE_LAST \
226 HWRM_SHORT_INPUT_SIGNATURE_SHORT_CMD
227 /* The target ID of the command */
229 /* Default target_id (0x0) to maintain compatibility with old driver */
230 #define HWRM_SHORT_INPUT_TARGET_ID_DEFAULT UINT32_C(0x0)
231 /* Reserved for user-space HWRM interface */
232 #define HWRM_SHORT_INPUT_TARGET_ID_TOOLS UINT32_C(0xfffd)
233 #define HWRM_SHORT_INPUT_TARGET_ID_LAST \
234 HWRM_SHORT_INPUT_TARGET_ID_TOOLS
235 /* This value indicates the length of the request. */
238 * This is the host address where the request was written.
239 * This area must be 16B aligned.
246 * # NOTE - definitions already in hwrm_req_type, in hwrm_types.yaml
247 * # So only structure definition is provided here.
249 /* cmd_nums (size:64b/8B) */
252 * This version of the specification defines the commands listed in
253 * the table below. The following are general implementation
254 * requirements for these commands:
256 * # All commands listed below that are marked neither
257 * reserved nor experimental shall be implemented by the HWRM.
258 * # A HWRM client compliant to this specification should not use
259 * commands outside of the list below.
260 * # A HWRM client compliant to this specification should not use
261 * command numbers marked reserved below.
262 * # A command marked experimental below may not be implemented
264 * # A command marked experimental may change in the
265 * future version of the HWRM specification.
266 * # A command not listed below may be implemented by the HWRM.
267 * The behavior of commands that are not listed below is outside
268 * the scope of this specification.
271 #define HWRM_VER_GET UINT32_C(0x0)
272 #define HWRM_ERROR_RECOVERY_QCFG UINT32_C(0xc)
273 #define HWRM_FUNC_DRV_IF_CHANGE UINT32_C(0xd)
274 #define HWRM_FUNC_BUF_UNRGTR UINT32_C(0xe)
275 #define HWRM_FUNC_VF_CFG UINT32_C(0xf)
276 /* Reserved for future use. */
277 #define HWRM_RESERVED1 UINT32_C(0x10)
278 #define HWRM_FUNC_RESET UINT32_C(0x11)
279 #define HWRM_FUNC_GETFID UINT32_C(0x12)
280 #define HWRM_FUNC_VF_ALLOC UINT32_C(0x13)
281 #define HWRM_FUNC_VF_FREE UINT32_C(0x14)
282 #define HWRM_FUNC_QCAPS UINT32_C(0x15)
283 #define HWRM_FUNC_QCFG UINT32_C(0x16)
284 #define HWRM_FUNC_CFG UINT32_C(0x17)
285 #define HWRM_FUNC_QSTATS UINT32_C(0x18)
286 #define HWRM_FUNC_CLR_STATS UINT32_C(0x19)
287 #define HWRM_FUNC_DRV_UNRGTR UINT32_C(0x1a)
288 #define HWRM_FUNC_VF_RESC_FREE UINT32_C(0x1b)
289 #define HWRM_FUNC_VF_VNIC_IDS_QUERY UINT32_C(0x1c)
290 #define HWRM_FUNC_DRV_RGTR UINT32_C(0x1d)
291 #define HWRM_FUNC_DRV_QVER UINT32_C(0x1e)
292 #define HWRM_FUNC_BUF_RGTR UINT32_C(0x1f)
293 #define HWRM_PORT_PHY_CFG UINT32_C(0x20)
294 #define HWRM_PORT_MAC_CFG UINT32_C(0x21)
296 #define HWRM_PORT_TS_QUERY UINT32_C(0x22)
297 #define HWRM_PORT_QSTATS UINT32_C(0x23)
298 #define HWRM_PORT_LPBK_QSTATS UINT32_C(0x24)
300 #define HWRM_PORT_CLR_STATS UINT32_C(0x25)
302 #define HWRM_PORT_LPBK_CLR_STATS UINT32_C(0x26)
303 #define HWRM_PORT_PHY_QCFG UINT32_C(0x27)
304 #define HWRM_PORT_MAC_QCFG UINT32_C(0x28)
306 #define HWRM_PORT_MAC_PTP_QCFG UINT32_C(0x29)
307 #define HWRM_PORT_PHY_QCAPS UINT32_C(0x2a)
308 #define HWRM_PORT_PHY_I2C_WRITE UINT32_C(0x2b)
309 #define HWRM_PORT_PHY_I2C_READ UINT32_C(0x2c)
310 #define HWRM_PORT_LED_CFG UINT32_C(0x2d)
311 #define HWRM_PORT_LED_QCFG UINT32_C(0x2e)
312 #define HWRM_PORT_LED_QCAPS UINT32_C(0x2f)
313 #define HWRM_QUEUE_QPORTCFG UINT32_C(0x30)
314 #define HWRM_QUEUE_QCFG UINT32_C(0x31)
315 #define HWRM_QUEUE_CFG UINT32_C(0x32)
316 #define HWRM_FUNC_VLAN_CFG UINT32_C(0x33)
317 #define HWRM_FUNC_VLAN_QCFG UINT32_C(0x34)
318 #define HWRM_QUEUE_PFCENABLE_QCFG UINT32_C(0x35)
319 #define HWRM_QUEUE_PFCENABLE_CFG UINT32_C(0x36)
320 #define HWRM_QUEUE_PRI2COS_QCFG UINT32_C(0x37)
321 #define HWRM_QUEUE_PRI2COS_CFG UINT32_C(0x38)
322 #define HWRM_QUEUE_COS2BW_QCFG UINT32_C(0x39)
323 #define HWRM_QUEUE_COS2BW_CFG UINT32_C(0x3a)
324 #define HWRM_QUEUE_DSCP_QCAPS UINT32_C(0x3b)
325 #define HWRM_QUEUE_DSCP2PRI_QCFG UINT32_C(0x3c)
326 #define HWRM_QUEUE_DSCP2PRI_CFG UINT32_C(0x3d)
327 #define HWRM_VNIC_ALLOC UINT32_C(0x40)
328 #define HWRM_VNIC_FREE UINT32_C(0x41)
329 #define HWRM_VNIC_CFG UINT32_C(0x42)
330 #define HWRM_VNIC_QCFG UINT32_C(0x43)
331 #define HWRM_VNIC_TPA_CFG UINT32_C(0x44)
333 #define HWRM_VNIC_TPA_QCFG UINT32_C(0x45)
334 #define HWRM_VNIC_RSS_CFG UINT32_C(0x46)
335 #define HWRM_VNIC_RSS_QCFG UINT32_C(0x47)
336 #define HWRM_VNIC_PLCMODES_CFG UINT32_C(0x48)
337 #define HWRM_VNIC_PLCMODES_QCFG UINT32_C(0x49)
338 #define HWRM_VNIC_QCAPS UINT32_C(0x4a)
339 #define HWRM_RING_ALLOC UINT32_C(0x50)
340 #define HWRM_RING_FREE UINT32_C(0x51)
341 #define HWRM_RING_CMPL_RING_QAGGINT_PARAMS UINT32_C(0x52)
342 #define HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS UINT32_C(0x53)
343 #define HWRM_RING_AGGINT_QCAPS UINT32_C(0x54)
344 #define HWRM_RING_SCHQ_ALLOC UINT32_C(0x55)
345 #define HWRM_RING_SCHQ_CFG UINT32_C(0x56)
346 #define HWRM_RING_SCHQ_FREE UINT32_C(0x57)
347 #define HWRM_RING_RESET UINT32_C(0x5e)
348 #define HWRM_RING_GRP_ALLOC UINT32_C(0x60)
349 #define HWRM_RING_GRP_FREE UINT32_C(0x61)
350 #define HWRM_RING_CFG UINT32_C(0x62)
351 #define HWRM_RING_QCFG UINT32_C(0x63)
352 /* Reserved for future use. */
353 #define HWRM_RESERVED5 UINT32_C(0x64)
354 /* Reserved for future use. */
355 #define HWRM_RESERVED6 UINT32_C(0x65)
356 #define HWRM_VNIC_RSS_COS_LB_CTX_ALLOC UINT32_C(0x70)
357 #define HWRM_VNIC_RSS_COS_LB_CTX_FREE UINT32_C(0x71)
358 #define HWRM_QUEUE_MPLS_QCAPS UINT32_C(0x80)
359 #define HWRM_QUEUE_MPLSTC2PRI_QCFG UINT32_C(0x81)
360 #define HWRM_QUEUE_MPLSTC2PRI_CFG UINT32_C(0x82)
361 #define HWRM_CFA_L2_FILTER_ALLOC UINT32_C(0x90)
362 #define HWRM_CFA_L2_FILTER_FREE UINT32_C(0x91)
363 #define HWRM_CFA_L2_FILTER_CFG UINT32_C(0x92)
364 #define HWRM_CFA_L2_SET_RX_MASK UINT32_C(0x93)
365 #define HWRM_CFA_VLAN_ANTISPOOF_CFG UINT32_C(0x94)
366 #define HWRM_CFA_TUNNEL_FILTER_ALLOC UINT32_C(0x95)
367 #define HWRM_CFA_TUNNEL_FILTER_FREE UINT32_C(0x96)
369 #define HWRM_CFA_ENCAP_RECORD_ALLOC UINT32_C(0x97)
371 #define HWRM_CFA_ENCAP_RECORD_FREE UINT32_C(0x98)
372 #define HWRM_CFA_NTUPLE_FILTER_ALLOC UINT32_C(0x99)
373 #define HWRM_CFA_NTUPLE_FILTER_FREE UINT32_C(0x9a)
374 #define HWRM_CFA_NTUPLE_FILTER_CFG UINT32_C(0x9b)
376 #define HWRM_CFA_EM_FLOW_ALLOC UINT32_C(0x9c)
378 #define HWRM_CFA_EM_FLOW_FREE UINT32_C(0x9d)
380 #define HWRM_CFA_EM_FLOW_CFG UINT32_C(0x9e)
381 #define HWRM_TUNNEL_DST_PORT_QUERY UINT32_C(0xa0)
382 #define HWRM_TUNNEL_DST_PORT_ALLOC UINT32_C(0xa1)
383 #define HWRM_TUNNEL_DST_PORT_FREE UINT32_C(0xa2)
384 #define HWRM_STAT_CTX_ENG_QUERY UINT32_C(0xaf)
385 #define HWRM_STAT_CTX_ALLOC UINT32_C(0xb0)
386 #define HWRM_STAT_CTX_FREE UINT32_C(0xb1)
387 #define HWRM_STAT_CTX_QUERY UINT32_C(0xb2)
388 #define HWRM_STAT_CTX_CLR_STATS UINT32_C(0xb3)
389 #define HWRM_PORT_QSTATS_EXT UINT32_C(0xb4)
390 #define HWRM_PORT_PHY_MDIO_WRITE UINT32_C(0xb5)
391 #define HWRM_PORT_PHY_MDIO_READ UINT32_C(0xb6)
392 #define HWRM_PORT_PHY_MDIO_BUS_ACQUIRE UINT32_C(0xb7)
393 #define HWRM_PORT_PHY_MDIO_BUS_RELEASE UINT32_C(0xb8)
394 #define HWRM_PORT_QSTATS_EXT_PFC_WD UINT32_C(0xb9)
395 #define HWRM_PORT_ECN_QSTATS UINT32_C(0xba)
396 #define HWRM_FW_RESET UINT32_C(0xc0)
397 #define HWRM_FW_QSTATUS UINT32_C(0xc1)
398 #define HWRM_FW_HEALTH_CHECK UINT32_C(0xc2)
399 #define HWRM_FW_SYNC UINT32_C(0xc3)
400 #define HWRM_FW_STATE_QCAPS UINT32_C(0xc4)
401 #define HWRM_FW_STATE_QUIESCE UINT32_C(0xc5)
402 #define HWRM_FW_STATE_BACKUP UINT32_C(0xc6)
403 #define HWRM_FW_STATE_RESTORE UINT32_C(0xc7)
405 #define HWRM_FW_SET_TIME UINT32_C(0xc8)
407 #define HWRM_FW_GET_TIME UINT32_C(0xc9)
409 #define HWRM_FW_SET_STRUCTURED_DATA UINT32_C(0xca)
411 #define HWRM_FW_GET_STRUCTURED_DATA UINT32_C(0xcb)
413 #define HWRM_FW_IPC_MAILBOX UINT32_C(0xcc)
414 #define HWRM_FW_ECN_CFG UINT32_C(0xcd)
415 #define HWRM_FW_ECN_QCFG UINT32_C(0xce)
416 #define HWRM_FW_SECURE_CFG UINT32_C(0xcf)
417 #define HWRM_EXEC_FWD_RESP UINT32_C(0xd0)
418 #define HWRM_REJECT_FWD_RESP UINT32_C(0xd1)
419 #define HWRM_FWD_RESP UINT32_C(0xd2)
420 #define HWRM_FWD_ASYNC_EVENT_CMPL UINT32_C(0xd3)
421 #define HWRM_OEM_CMD UINT32_C(0xd4)
422 /* Tells the fw to run PRBS test on a given port and lane. */
423 #define HWRM_PORT_PRBS_TEST UINT32_C(0xd5)
424 #define HWRM_PORT_SFP_SIDEBAND_CFG UINT32_C(0xd6)
425 #define HWRM_PORT_SFP_SIDEBAND_QCFG UINT32_C(0xd7)
426 #define HWRM_FW_STATE_UNQUIESCE UINT32_C(0xd8)
427 /* Tells the fw to collect dsc dump on a given port and lane. */
428 #define HWRM_PORT_DSC_DUMP UINT32_C(0xd9)
429 #define HWRM_TEMP_MONITOR_QUERY UINT32_C(0xe0)
430 #define HWRM_REG_POWER_QUERY UINT32_C(0xe1)
431 #define HWRM_CORE_FREQUENCY_QUERY UINT32_C(0xe2)
432 #define HWRM_REG_POWER_HISTOGRAM UINT32_C(0xe3)
433 #define HWRM_WOL_FILTER_ALLOC UINT32_C(0xf0)
434 #define HWRM_WOL_FILTER_FREE UINT32_C(0xf1)
435 #define HWRM_WOL_FILTER_QCFG UINT32_C(0xf2)
436 #define HWRM_WOL_REASON_QCFG UINT32_C(0xf3)
438 #define HWRM_CFA_METER_QCAPS UINT32_C(0xf4)
440 #define HWRM_CFA_METER_PROFILE_ALLOC UINT32_C(0xf5)
442 #define HWRM_CFA_METER_PROFILE_FREE UINT32_C(0xf6)
444 #define HWRM_CFA_METER_PROFILE_CFG UINT32_C(0xf7)
446 #define HWRM_CFA_METER_INSTANCE_ALLOC UINT32_C(0xf8)
448 #define HWRM_CFA_METER_INSTANCE_FREE UINT32_C(0xf9)
450 #define HWRM_CFA_METER_INSTANCE_CFG UINT32_C(0xfa)
452 #define HWRM_CFA_VFR_ALLOC UINT32_C(0xfd)
454 #define HWRM_CFA_VFR_FREE UINT32_C(0xfe)
456 #define HWRM_CFA_VF_PAIR_ALLOC UINT32_C(0x100)
458 #define HWRM_CFA_VF_PAIR_FREE UINT32_C(0x101)
460 #define HWRM_CFA_VF_PAIR_INFO UINT32_C(0x102)
462 #define HWRM_CFA_FLOW_ALLOC UINT32_C(0x103)
464 #define HWRM_CFA_FLOW_FREE UINT32_C(0x104)
466 #define HWRM_CFA_FLOW_FLUSH UINT32_C(0x105)
468 #define HWRM_CFA_FLOW_STATS UINT32_C(0x106)
470 #define HWRM_CFA_FLOW_INFO UINT32_C(0x107)
472 #define HWRM_CFA_DECAP_FILTER_ALLOC UINT32_C(0x108)
474 #define HWRM_CFA_DECAP_FILTER_FREE UINT32_C(0x109)
475 #define HWRM_CFA_VLAN_ANTISPOOF_QCFG UINT32_C(0x10a)
476 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_ALLOC UINT32_C(0x10b)
477 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_FREE UINT32_C(0x10c)
479 #define HWRM_CFA_PAIR_ALLOC UINT32_C(0x10d)
481 #define HWRM_CFA_PAIR_FREE UINT32_C(0x10e)
483 #define HWRM_CFA_PAIR_INFO UINT32_C(0x10f)
485 #define HWRM_FW_IPC_MSG UINT32_C(0x110)
486 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_INFO UINT32_C(0x111)
487 #define HWRM_CFA_REDIRECT_QUERY_TUNNEL_TYPE UINT32_C(0x112)
489 #define HWRM_CFA_FLOW_AGING_TIMER_RESET UINT32_C(0x113)
491 #define HWRM_CFA_FLOW_AGING_CFG UINT32_C(0x114)
493 #define HWRM_CFA_FLOW_AGING_QCFG UINT32_C(0x115)
495 #define HWRM_CFA_FLOW_AGING_QCAPS UINT32_C(0x116)
497 #define HWRM_CFA_CTX_MEM_RGTR UINT32_C(0x117)
499 #define HWRM_CFA_CTX_MEM_UNRGTR UINT32_C(0x118)
501 #define HWRM_CFA_CTX_MEM_QCTX UINT32_C(0x119)
503 #define HWRM_CFA_CTX_MEM_QCAPS UINT32_C(0x11a)
505 #define HWRM_CFA_COUNTER_QCAPS UINT32_C(0x11b)
507 #define HWRM_CFA_COUNTER_CFG UINT32_C(0x11c)
509 #define HWRM_CFA_COUNTER_QCFG UINT32_C(0x11d)
511 #define HWRM_CFA_COUNTER_QSTATS UINT32_C(0x11e)
513 #define HWRM_CFA_TCP_FLAG_PROCESS_QCFG UINT32_C(0x11f)
515 #define HWRM_CFA_EEM_QCAPS UINT32_C(0x120)
517 #define HWRM_CFA_EEM_CFG UINT32_C(0x121)
519 #define HWRM_CFA_EEM_QCFG UINT32_C(0x122)
521 #define HWRM_CFA_EEM_OP UINT32_C(0x123)
523 #define HWRM_CFA_ADV_FLOW_MGNT_QCAPS UINT32_C(0x124)
524 /* Experimental - DEPRECATED */
525 #define HWRM_CFA_TFLIB UINT32_C(0x125)
526 /* Engine CKV - Get the current allocation status of keys provisioned in the key vault. */
527 #define HWRM_ENGINE_CKV_STATUS UINT32_C(0x12e)
528 /* Engine CKV - Add a new CKEK used to encrypt keys. */
529 #define HWRM_ENGINE_CKV_CKEK_ADD UINT32_C(0x12f)
530 /* Engine CKV - Delete a previously added CKEK. */
531 #define HWRM_ENGINE_CKV_CKEK_DELETE UINT32_C(0x130)
532 /* Engine CKV - Add a new key to the key vault. */
533 #define HWRM_ENGINE_CKV_KEY_ADD UINT32_C(0x131)
534 /* Engine CKV - Delete a key from the key vault. */
535 #define HWRM_ENGINE_CKV_KEY_DELETE UINT32_C(0x132)
536 /* Engine CKV - Delete all keys from the key vault. */
537 #define HWRM_ENGINE_CKV_FLUSH UINT32_C(0x133)
538 /* Engine CKV - Get random data. */
539 #define HWRM_ENGINE_CKV_RNG_GET UINT32_C(0x134)
540 /* Engine CKV - Generate and encrypt a new AES key. */
541 #define HWRM_ENGINE_CKV_KEY_GEN UINT32_C(0x135)
542 /* Engine CKV - Configure a label index with a label value. */
543 #define HWRM_ENGINE_CKV_KEY_LABEL_CFG UINT32_C(0x136)
544 /* Engine CKV - Query a label */
545 #define HWRM_ENGINE_CKV_KEY_LABEL_QCFG UINT32_C(0x137)
546 /* Engine - Query the available queue groups configuration. */
547 #define HWRM_ENGINE_QG_CONFIG_QUERY UINT32_C(0x13c)
548 /* Engine - Query the queue groups assigned to a function. */
549 #define HWRM_ENGINE_QG_QUERY UINT32_C(0x13d)
550 /* Engine - Query the available queue group meter profile configuration. */
551 #define HWRM_ENGINE_QG_METER_PROFILE_CONFIG_QUERY UINT32_C(0x13e)
552 /* Engine - Query the configuration of a queue group meter profile. */
553 #define HWRM_ENGINE_QG_METER_PROFILE_QUERY UINT32_C(0x13f)
554 /* Engine - Allocate a queue group meter profile. */
555 #define HWRM_ENGINE_QG_METER_PROFILE_ALLOC UINT32_C(0x140)
556 /* Engine - Free a queue group meter profile. */
557 #define HWRM_ENGINE_QG_METER_PROFILE_FREE UINT32_C(0x141)
558 /* Engine - Query the meters assigned to a queue group. */
559 #define HWRM_ENGINE_QG_METER_QUERY UINT32_C(0x142)
560 /* Engine - Bind a queue group meter profile to a queue group. */
561 #define HWRM_ENGINE_QG_METER_BIND UINT32_C(0x143)
562 /* Engine - Unbind a queue group meter profile from a queue group. */
563 #define HWRM_ENGINE_QG_METER_UNBIND UINT32_C(0x144)
564 /* Engine - Bind a queue group to a function. */
565 #define HWRM_ENGINE_QG_FUNC_BIND UINT32_C(0x145)
566 /* Engine - Query the scheduling group configuration. */
567 #define HWRM_ENGINE_SG_CONFIG_QUERY UINT32_C(0x146)
568 /* Engine - Query the queue groups assigned to a scheduling group. */
569 #define HWRM_ENGINE_SG_QUERY UINT32_C(0x147)
570 /* Engine - Query the configuration of a scheduling group's meter profiles. */
571 #define HWRM_ENGINE_SG_METER_QUERY UINT32_C(0x148)
572 /* Engine - Configure a scheduling group's meter profiles. */
573 #define HWRM_ENGINE_SG_METER_CONFIG UINT32_C(0x149)
574 /* Engine - Bind a queue group to a scheduling group. */
575 #define HWRM_ENGINE_SG_QG_BIND UINT32_C(0x14a)
576 /* Engine - Unbind a queue group from its scheduling group. */
577 #define HWRM_ENGINE_QG_SG_UNBIND UINT32_C(0x14b)
578 /* Engine - Query the Engine configuration. */
579 #define HWRM_ENGINE_CONFIG_QUERY UINT32_C(0x154)
580 /* Engine - Configure the statistics accumulator for an Engine. */
581 #define HWRM_ENGINE_STATS_CONFIG UINT32_C(0x155)
582 /* Engine - Clear the statistics accumulator for an Engine. */
583 #define HWRM_ENGINE_STATS_CLEAR UINT32_C(0x156)
584 /* Engine - Query the statistics accumulator for an Engine. */
585 #define HWRM_ENGINE_STATS_QUERY UINT32_C(0x157)
586 /* Engine - Query statistics counters for continuous errors from all CDDIP Engines. */
587 #define HWRM_ENGINE_STATS_QUERY_CONTINUOUS_ERROR UINT32_C(0x158)
588 /* Engine - Allocate an Engine RQ. */
589 #define HWRM_ENGINE_RQ_ALLOC UINT32_C(0x15e)
590 /* Engine - Free an Engine RQ. */
591 #define HWRM_ENGINE_RQ_FREE UINT32_C(0x15f)
592 /* Engine - Allocate an Engine CQ. */
593 #define HWRM_ENGINE_CQ_ALLOC UINT32_C(0x160)
594 /* Engine - Free an Engine CQ. */
595 #define HWRM_ENGINE_CQ_FREE UINT32_C(0x161)
596 /* Engine - Allocate an NQ. */
597 #define HWRM_ENGINE_NQ_ALLOC UINT32_C(0x162)
598 /* Engine - Free an NQ. */
599 #define HWRM_ENGINE_NQ_FREE UINT32_C(0x163)
600 /* Engine - Set the on-die RQE credit update location. */
601 #define HWRM_ENGINE_ON_DIE_RQE_CREDITS UINT32_C(0x164)
602 /* Engine - Query the engine function configuration. */
603 #define HWRM_ENGINE_FUNC_QCFG UINT32_C(0x165)
605 #define HWRM_FUNC_RESOURCE_QCAPS UINT32_C(0x190)
607 #define HWRM_FUNC_VF_RESOURCE_CFG UINT32_C(0x191)
609 #define HWRM_FUNC_BACKING_STORE_QCAPS UINT32_C(0x192)
611 #define HWRM_FUNC_BACKING_STORE_CFG UINT32_C(0x193)
613 #define HWRM_FUNC_BACKING_STORE_QCFG UINT32_C(0x194)
614 /* Configures the BW of any VF */
615 #define HWRM_FUNC_VF_BW_CFG UINT32_C(0x195)
616 /* Queries the BW of any VF */
617 #define HWRM_FUNC_VF_BW_QCFG UINT32_C(0x196)
618 /* Queries pf ids belong to specified host(s) */
619 #define HWRM_FUNC_HOST_PF_IDS_QUERY UINT32_C(0x197)
620 /* Queries extended stats per function */
621 #define HWRM_FUNC_QSTATS_EXT UINT32_C(0x198)
622 /* Queries extended statistics context */
623 #define HWRM_STAT_EXT_CTX_QUERY UINT32_C(0x199)
625 #define HWRM_SELFTEST_QLIST UINT32_C(0x200)
627 #define HWRM_SELFTEST_EXEC UINT32_C(0x201)
629 #define HWRM_SELFTEST_IRQ UINT32_C(0x202)
631 #define HWRM_SELFTEST_RETRIEVE_SERDES_DATA UINT32_C(0x203)
633 #define HWRM_PCIE_QSTATS UINT32_C(0x204)
635 #define HWRM_MFG_FRU_WRITE_CONTROL UINT32_C(0x205)
636 /* Returns the current value of a free running counter from the device. */
637 #define HWRM_MFG_TIMERS_QUERY UINT32_C(0x206)
639 #define HWRM_MFG_OTP_CFG UINT32_C(0x207)
641 #define HWRM_MFG_OTP_QCFG UINT32_C(0x208)
643 * Tells the fw to run the DMA read from the host and DMA write
646 #define HWRM_MFG_HDMA_TEST UINT32_C(0x209)
647 /* Tells the fw to program the fru memory */
648 #define HWRM_MFG_FRU_EEPROM_WRITE UINT32_C(0x20a)
649 /* Tells the fw to read the fru memory */
650 #define HWRM_MFG_FRU_EEPROM_READ UINT32_C(0x20b)
652 #define HWRM_TF UINT32_C(0x2bc)
654 #define HWRM_TF_VERSION_GET UINT32_C(0x2bd)
656 #define HWRM_TF_SESSION_OPEN UINT32_C(0x2c6)
658 #define HWRM_TF_SESSION_ATTACH UINT32_C(0x2c7)
660 #define HWRM_TF_SESSION_REGISTER UINT32_C(0x2c8)
662 #define HWRM_TF_SESSION_UNREGISTER UINT32_C(0x2c9)
664 #define HWRM_TF_SESSION_CLOSE UINT32_C(0x2ca)
666 #define HWRM_TF_SESSION_QCFG UINT32_C(0x2cb)
668 #define HWRM_TF_SESSION_RESC_QCAPS UINT32_C(0x2cc)
670 #define HWRM_TF_SESSION_RESC_ALLOC UINT32_C(0x2cd)
672 #define HWRM_TF_SESSION_RESC_FREE UINT32_C(0x2ce)
674 #define HWRM_TF_SESSION_RESC_FLUSH UINT32_C(0x2cf)
676 #define HWRM_TF_TBL_TYPE_GET UINT32_C(0x2da)
678 #define HWRM_TF_TBL_TYPE_SET UINT32_C(0x2db)
680 #define HWRM_TF_CTXT_MEM_RGTR UINT32_C(0x2e4)
682 #define HWRM_TF_CTXT_MEM_UNRGTR UINT32_C(0x2e5)
684 #define HWRM_TF_EXT_EM_QCAPS UINT32_C(0x2e6)
686 #define HWRM_TF_EXT_EM_OP UINT32_C(0x2e7)
688 #define HWRM_TF_EXT_EM_CFG UINT32_C(0x2e8)
690 #define HWRM_TF_EXT_EM_QCFG UINT32_C(0x2e9)
692 #define HWRM_TF_EM_INSERT UINT32_C(0x2ea)
694 #define HWRM_TF_EM_DELETE UINT32_C(0x2eb)
696 #define HWRM_TF_TCAM_SET UINT32_C(0x2f8)
698 #define HWRM_TF_TCAM_GET UINT32_C(0x2f9)
700 #define HWRM_TF_TCAM_MOVE UINT32_C(0x2fa)
702 #define HWRM_TF_TCAM_FREE UINT32_C(0x2fb)
704 #define HWRM_TF_GLOBAL_CFG_SET UINT32_C(0x2fc)
706 #define HWRM_TF_GLOBAL_CFG_GET UINT32_C(0x2fd)
708 #define HWRM_TF_IF_TBL_SET UINT32_C(0x2fe)
710 #define HWRM_TF_IF_TBL_GET UINT32_C(0x2ff)
712 #define HWRM_SV UINT32_C(0x400)
714 #define HWRM_DBG_READ_DIRECT UINT32_C(0xff10)
716 #define HWRM_DBG_READ_INDIRECT UINT32_C(0xff11)
718 #define HWRM_DBG_WRITE_DIRECT UINT32_C(0xff12)
720 #define HWRM_DBG_WRITE_INDIRECT UINT32_C(0xff13)
721 #define HWRM_DBG_DUMP UINT32_C(0xff14)
723 #define HWRM_DBG_ERASE_NVM UINT32_C(0xff15)
725 #define HWRM_DBG_CFG UINT32_C(0xff16)
727 #define HWRM_DBG_COREDUMP_LIST UINT32_C(0xff17)
729 #define HWRM_DBG_COREDUMP_INITIATE UINT32_C(0xff18)
731 #define HWRM_DBG_COREDUMP_RETRIEVE UINT32_C(0xff19)
733 #define HWRM_DBG_FW_CLI UINT32_C(0xff1a)
735 #define HWRM_DBG_I2C_CMD UINT32_C(0xff1b)
737 #define HWRM_DBG_RING_INFO_GET UINT32_C(0xff1c)
739 #define HWRM_DBG_CRASHDUMP_HEADER UINT32_C(0xff1d)
741 #define HWRM_DBG_CRASHDUMP_ERASE UINT32_C(0xff1e)
742 /* Send driver debug information to firmware */
743 #define HWRM_DBG_DRV_TRACE UINT32_C(0xff1f)
744 /* Query debug capabilities of firmware */
745 #define HWRM_DBG_QCAPS UINT32_C(0xff20)
746 /* Retrieve debug settings of firmware */
747 #define HWRM_DBG_QCFG UINT32_C(0xff21)
748 /* Set destination parameters for crashdump medium */
749 #define HWRM_DBG_CRASHDUMP_MEDIUM_CFG UINT32_C(0xff22)
750 #define HWRM_NVM_REQ_ARBITRATION UINT32_C(0xffed)
752 #define HWRM_NVM_FACTORY_DEFAULTS UINT32_C(0xffee)
753 #define HWRM_NVM_VALIDATE_OPTION UINT32_C(0xffef)
754 #define HWRM_NVM_FLUSH UINT32_C(0xfff0)
755 #define HWRM_NVM_GET_VARIABLE UINT32_C(0xfff1)
756 #define HWRM_NVM_SET_VARIABLE UINT32_C(0xfff2)
757 #define HWRM_NVM_INSTALL_UPDATE UINT32_C(0xfff3)
758 #define HWRM_NVM_MODIFY UINT32_C(0xfff4)
759 #define HWRM_NVM_VERIFY_UPDATE UINT32_C(0xfff5)
760 #define HWRM_NVM_GET_DEV_INFO UINT32_C(0xfff6)
761 #define HWRM_NVM_ERASE_DIR_ENTRY UINT32_C(0xfff7)
762 #define HWRM_NVM_MOD_DIR_ENTRY UINT32_C(0xfff8)
763 #define HWRM_NVM_FIND_DIR_ENTRY UINT32_C(0xfff9)
764 #define HWRM_NVM_GET_DIR_ENTRIES UINT32_C(0xfffa)
765 #define HWRM_NVM_GET_DIR_INFO UINT32_C(0xfffb)
766 #define HWRM_NVM_RAW_DUMP UINT32_C(0xfffc)
767 #define HWRM_NVM_READ UINT32_C(0xfffd)
768 #define HWRM_NVM_WRITE UINT32_C(0xfffe)
769 #define HWRM_NVM_RAW_WRITE_BLK UINT32_C(0xffff)
770 #define HWRM_LAST HWRM_NVM_RAW_WRITE_BLK
771 uint16_t unused_0[3];
775 /* ret_codes (size:64b/8B) */
778 /* Request was successfully executed by the HWRM. */
779 #define HWRM_ERR_CODE_SUCCESS UINT32_C(0x0)
780 /* The HWRM failed to execute the request. */
781 #define HWRM_ERR_CODE_FAIL UINT32_C(0x1)
783 * The request contains invalid argument(s) or input
786 #define HWRM_ERR_CODE_INVALID_PARAMS UINT32_C(0x2)
788 * The requester is not allowed to access the requested
789 * resource. This error code shall be provided in a
790 * response to a request to query or modify an existing
791 * resource that is not accessible by the requester.
793 #define HWRM_ERR_CODE_RESOURCE_ACCESS_DENIED UINT32_C(0x3)
795 * The HWRM is unable to allocate the requested resource.
796 * This code only applies to requests for HWRM resource
799 #define HWRM_ERR_CODE_RESOURCE_ALLOC_ERROR UINT32_C(0x4)
801 * Invalid combination of flags is specified in the
804 #define HWRM_ERR_CODE_INVALID_FLAGS UINT32_C(0x5)
806 * Invalid combination of enables fields is specified in
809 #define HWRM_ERR_CODE_INVALID_ENABLES UINT32_C(0x6)
811 * Request contains a required TLV that is not supported by
812 * the installed version of firmware.
814 #define HWRM_ERR_CODE_UNSUPPORTED_TLV UINT32_C(0x7)
816 * No firmware buffer available to accept the request. Driver
817 * should retry the request.
819 #define HWRM_ERR_CODE_NO_BUFFER UINT32_C(0x8)
821 * This error code is only reported by firmware when some
822 * sub-option of a supported HWRM command is unsupported.
824 #define HWRM_ERR_CODE_UNSUPPORTED_OPTION_ERR UINT32_C(0x9)
826 * This error code is only reported by firmware when the specific
827 * request is not able to process when the HOT reset in progress.
829 #define HWRM_ERR_CODE_HOT_RESET_PROGRESS UINT32_C(0xa)
831 * This error code is only reported by firmware when the registered
832 * driver instances are not capable of hot reset.
834 #define HWRM_ERR_CODE_HOT_RESET_FAIL UINT32_C(0xb)
836 * This error code is only reported by the firmware when during
837 * flow allocation when a request for a flow counter fails because
838 * the number of flow counters are exhausted.
840 #define HWRM_ERR_CODE_NO_FLOW_COUNTER_DURING_ALLOC UINT32_C(0xc)
842 * This error code is only reported by firmware when the registered
843 * driver instances requested to offloaded a flow but was unable to because
844 * the requested key's hash collides with the installed keys.
846 #define HWRM_ERR_CODE_KEY_HASH_COLLISION UINT32_C(0xd)
848 * This error code is only reported by firmware when the registered
849 * driver instances requested to offloaded a flow but was unable to because
850 * the same key has already been installed.
852 #define HWRM_ERR_CODE_KEY_ALREADY_EXISTS UINT32_C(0xe)
854 * Generic HWRM execution error that represents an
857 #define HWRM_ERR_CODE_HWRM_ERROR UINT32_C(0xf)
859 * Firmware is unable to service the request at the present time. Caller
860 * may try again later.
862 #define HWRM_ERR_CODE_BUSY UINT32_C(0x10)
864 * This value indicates that the HWRM response is in TLV format and
865 * should be interpreted as one or more TLVs starting with the
866 * hwrm_resp_hdr TLV. This value is not an indication of any error
867 * by itself, just an indication that the response should be parsed
868 * as TLV and the actual error code will be in the hwrm_resp_hdr TLV.
870 #define HWRM_ERR_CODE_TLV_ENCAPSULATED_RESPONSE UINT32_C(0x8000)
872 #define HWRM_ERR_CODE_UNKNOWN_ERR UINT32_C(0xfffe)
873 /* Unsupported or invalid command */
874 #define HWRM_ERR_CODE_CMD_NOT_SUPPORTED UINT32_C(0xffff)
875 #define HWRM_ERR_CODE_LAST \
876 HWRM_ERR_CODE_CMD_NOT_SUPPORTED
877 uint16_t unused_0[3];
881 /* hwrm_err_output (size:128b/16B) */
882 struct hwrm_err_output {
884 * Pass/Fail or error type
886 * Note: receiver to verify the in parameters, and fail the call
887 * with an error when appropriate
890 /* This field returns the type of original request. */
892 /* This field provides original sequence number of the command. */
895 * This field is the length of the response in bytes. The
896 * last byte of the response is a valid flag that will read
897 * as '1' when the command has been completely written to
901 /* debug info for this error response. */
903 /* debug info for this error response. */
906 * In the case of an error response, command specific error
907 * code is returned in this field.
911 * This field is used in Output records to indicate that the output
912 * is completely written to RAM. This field should be read as '1'
913 * to indicate that the output has been completely written.
914 * When writing a command completion or response to an internal processor,
915 * the order of writes has to be such that this field is written last.
920 * Following is the signature for HWRM message field that indicates not
921 * applicable (All F's). Need to cast it the size of the field if needed.
923 #define HWRM_NA_SIGNATURE ((uint32_t)(-1))
924 /* hwrm_func_buf_rgtr */
925 #define HWRM_MAX_REQ_LEN 128
926 /* hwrm_cfa_flow_info */
927 #define HWRM_MAX_RESP_LEN 704
928 /* 7 bit indirection table index. */
929 #define HW_HASH_INDEX_SIZE 0x80
930 #define HW_HASH_KEY_SIZE 40
931 /* valid key for HWRM response */
932 #define HWRM_RESP_VALID_KEY 1
933 /* Reserved for BONO processor */
934 #define HWRM_TARGET_ID_BONO 0xFFF8
935 /* Reserved for KONG processor */
936 #define HWRM_TARGET_ID_KONG 0xFFF9
937 /* Reserved for APE processor */
938 #define HWRM_TARGET_ID_APE 0xFFFA
940 * This value will be used by tools for User-space HWRM Interface.
941 * When tool execute any HWRM command with this target_id, firmware
942 * will copy the response and/or data payload via register space instead
945 #define HWRM_TARGET_ID_TOOLS 0xFFFD
946 #define HWRM_VERSION_MAJOR 1
947 #define HWRM_VERSION_MINOR 10
948 #define HWRM_VERSION_UPDATE 1
949 /* non-zero means beta version */
950 #define HWRM_VERSION_RSVD 56
951 #define HWRM_VERSION_STR "1.10.1.56"
958 /* hwrm_ver_get_input (size:192b/24B) */
959 struct hwrm_ver_get_input {
960 /* The HWRM command request type. */
963 * The completion ring to send the completion event on. This should
964 * be the NQ ID returned from the `nq_alloc` HWRM command.
968 * The sequence ID is used by the driver for tracking multiple
969 * commands. This ID is treated as opaque data by the firmware and
970 * the value is returned in the `hwrm_resp_hdr` upon completion.
974 * The target ID of the command:
975 * * 0x0-0xFFF8 - The function ID
976 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
977 * * 0xFFFD - Reserved for user-space HWRM interface
982 * A physical address pointer pointing to a host buffer that the
983 * command's response data will be written. This can be either a host
984 * physical address (HPA) or a guest physical address (GPA) and must
985 * point to a physically contiguous block of memory.
989 * This field represents the major version of HWRM interface
990 * specification supported by the driver HWRM implementation.
991 * The interface major version is intended to change only when
992 * non backward compatible changes are made to the HWRM
993 * interface specification.
995 uint8_t hwrm_intf_maj;
997 * This field represents the minor version of HWRM interface
998 * specification supported by the driver HWRM implementation.
999 * A change in interface minor version is used to reflect
1000 * significant backward compatible modification to HWRM
1001 * interface specification.
1002 * This can be due to addition or removal of functionality.
1003 * HWRM interface specifications with the same major version
1004 * but different minor versions are compatible.
1006 uint8_t hwrm_intf_min;
1008 * This field represents the update version of HWRM interface
1009 * specification supported by the driver HWRM implementation.
1010 * The interface update version is used to reflect minor
1011 * changes or bug fixes to a released HWRM interface
1014 uint8_t hwrm_intf_upd;
1015 uint8_t unused_0[5];
1018 /* hwrm_ver_get_output (size:1408b/176B) */
1019 struct hwrm_ver_get_output {
1020 /* The specific error status for the command. */
1021 uint16_t error_code;
1022 /* The HWRM command request type. */
1024 /* The sequence ID from the original command. */
1026 /* The length of the response data in number of bytes. */
1029 * This field represents the major version of HWRM interface
1030 * specification supported by the HWRM implementation.
1031 * The interface major version is intended to change only when
1032 * non backward compatible changes are made to the HWRM
1033 * interface specification.
1034 * A HWRM implementation that is compliant with this
1035 * specification shall provide value of 1 in this field.
1037 uint8_t hwrm_intf_maj_8b;
1039 * This field represents the minor version of HWRM interface
1040 * specification supported by the HWRM implementation.
1041 * A change in interface minor version is used to reflect
1042 * significant backward compatible modification to HWRM
1043 * interface specification.
1044 * This can be due to addition or removal of functionality.
1045 * HWRM interface specifications with the same major version
1046 * but different minor versions are compatible.
1047 * A HWRM implementation that is compliant with this
1048 * specification shall provide value of 2 in this field.
1050 uint8_t hwrm_intf_min_8b;
1052 * This field represents the update version of HWRM interface
1053 * specification supported by the HWRM implementation.
1054 * The interface update version is used to reflect minor
1055 * changes or bug fixes to a released HWRM interface
1057 * A HWRM implementation that is compliant with this
1058 * specification shall provide value of 2 in this field.
1060 uint8_t hwrm_intf_upd_8b;
1061 uint8_t hwrm_intf_rsvd_8b;
1063 * This field represents the major version of HWRM firmware.
1064 * A change in firmware major version represents a major
1067 uint8_t hwrm_fw_maj_8b;
1069 * This field represents the minor version of HWRM firmware.
1070 * A change in firmware minor version represents significant
1071 * firmware functionality changes.
1073 uint8_t hwrm_fw_min_8b;
1075 * This field represents the build version of HWRM firmware.
1076 * A change in firmware build version represents bug fixes
1077 * to a released firmware.
1079 uint8_t hwrm_fw_bld_8b;
1081 * This field is a reserved field. This field can be used to
1082 * represent firmware branches or customer specific releases
1083 * tied to a specific (major,minor,update) version of the
1086 uint8_t hwrm_fw_rsvd_8b;
1088 * This field represents the major version of mgmt firmware.
1089 * A change in major version represents a major release.
1091 uint8_t mgmt_fw_maj_8b;
1093 * This field represents the minor version of mgmt firmware.
1094 * A change in minor version represents significant
1095 * functionality changes.
1097 uint8_t mgmt_fw_min_8b;
1099 * This field represents the build version of mgmt firmware.
1100 * A change in update version represents bug fixes.
1102 uint8_t mgmt_fw_bld_8b;
1104 * This field is a reserved field. This field can be used to
1105 * represent firmware branches or customer specific releases
1106 * tied to a specific (major,minor,update) version
1108 uint8_t mgmt_fw_rsvd_8b;
1110 * This field represents the major version of network
1112 * A change in major version represents a major release.
1114 uint8_t netctrl_fw_maj_8b;
1116 * This field represents the minor version of network
1118 * A change in minor version represents significant
1119 * functionality changes.
1121 uint8_t netctrl_fw_min_8b;
1123 * This field represents the build version of network
1125 * A change in update version represents bug fixes.
1127 uint8_t netctrl_fw_bld_8b;
1129 * This field is a reserved field. This field can be used to
1130 * represent firmware branches or customer specific releases
1131 * tied to a specific (major,minor,update) version
1133 uint8_t netctrl_fw_rsvd_8b;
1135 * This field is used to indicate device's capabilities and
1138 uint32_t dev_caps_cfg;
1140 * If set to 1, then secure firmware update behavior
1142 * If set to 0, then secure firmware update behavior is
1145 #define HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_SECURE_FW_UPD_SUPPORTED \
1148 * If set to 1, then firmware based DCBX agent is supported.
1149 * If set to 0, then firmware based DCBX agent capability
1150 * is not supported on this device.
1152 #define HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_FW_DCBX_AGENT_SUPPORTED \
1155 * If set to 1, then HWRM short command format is supported.
1156 * If set to 0, then HWRM short command format is not supported.
1158 #define HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_SHORT_CMD_SUPPORTED \
1161 * If set to 1, then HWRM short command format is required.
1162 * If set to 0, then HWRM short command format is not required.
1164 #define HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_SHORT_CMD_REQUIRED \
1167 * If set to 1, then the KONG host mailbox channel is supported.
1168 * If set to 0, then the KONG host mailbox channel is not supported.
1169 * By default, this flag should be 0 for older version of core firmware.
1171 #define HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_KONG_MB_CHNL_SUPPORTED \
1174 * If set to 1, then the 64bit flow handle is supported in addition to the
1175 * legacy 16bit flow handle. If set to 0, then the 64bit flow handle is not
1176 * supported. By default, this flag should be 0 for older version of core firmware.
1178 #define HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_FLOW_HANDLE_64BIT_SUPPORTED \
1181 * If set to 1, then filter type can be provided in filter_alloc or filter_cfg
1182 * filter types like L2 for l2 traffic and ROCE for roce & l2 traffic.
1183 * If set to 0, then filter types not supported.
1184 * By default, this flag should be 0 for older version of core firmware.
1186 #define HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_L2_FILTER_TYPES_ROCE_OR_L2_SUPPORTED \
1189 * If set to 1, firmware is capable to support virtio vSwitch offload model.
1190 * If set to 0, firmware can't supported virtio vSwitch offload model.
1191 * By default, this flag should be 0 for older version of core firmware.
1193 #define HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_VIRTIO_VSWITCH_OFFLOAD_SUPPORTED \
1196 * If set to 1, firmware is capable to support trusted VF.
1197 * If set to 0, firmware is not capable to support trusted VF.
1198 * By default, this flag should be 0 for older version of core firmware.
1200 #define HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_TRUSTED_VF_SUPPORTED \
1203 * If set to 1, firmware is capable to support flow aging.
1204 * If set to 0, firmware is not capable to support flow aging.
1205 * By default, this flag should be 0 for older version of core firmware.
1207 #define HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_FLOW_AGING_SUPPORTED \
1210 * If set to 1, firmware is capable to support advanced flow counters like,
1211 * Meter drop counters and EEM counters.
1212 * If set to 0, firmware is not capable to support advanced flow counters.
1213 * By default, this flag should be 0 for older version of core firmware.
1215 #define HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_ADV_FLOW_COUNTERS_SUPPORTED \
1218 * If set to 1, the firmware is able to support the use of the CFA
1219 * Extended Exact Match(EEM) feature.
1220 * If set to 0, firmware is not capable to support the use of the
1222 * By default, this flag should be 0 for older version of core firmware.
1224 #define HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_CFA_EEM_SUPPORTED \
1227 * If set to 1, the firmware is able to support advance CFA flow management
1228 * features reported in the HWRM_CFA_FLOW_MGNT_QCAPS.
1229 * If set to 0, then the firmware doesn’t support the advance CFA flow management
1231 * By default, this flag should be 0 for older version of core firmware.
1233 #define HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_CFA_ADV_FLOW_MGNT_SUPPORTED \
1236 * Deprecated and replaced with cfa_truflow_supported.
1237 * If set to 1, the firmware is able to support TFLIB features.
1238 * If set to 0, then the firmware doesn’t support TFLIB features.
1239 * By default, this flag should be 0 for older version of core firmware.
1241 #define HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_CFA_TFLIB_SUPPORTED \
1244 * If set to 1, the firmware is able to support TruFlow features.
1245 * If set to 0, then the firmware doesn’t support TruFlow features.
1246 * By default, this flag should be 0 for older version of
1249 #define HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_CFA_TRUFLOW_SUPPORTED \
1252 * This field represents the major version of RoCE firmware.
1253 * A change in major version represents a major release.
1255 uint8_t roce_fw_maj_8b;
1257 * This field represents the minor version of RoCE firmware.
1258 * A change in minor version represents significant
1259 * functionality changes.
1261 uint8_t roce_fw_min_8b;
1263 * This field represents the build version of RoCE firmware.
1264 * A change in update version represents bug fixes.
1266 uint8_t roce_fw_bld_8b;
1268 * This field is a reserved field. This field can be used to
1269 * represent firmware branches or customer specific releases
1270 * tied to a specific (major,minor,update) version
1272 uint8_t roce_fw_rsvd_8b;
1274 * This field represents the name of HWRM FW (ASCII chars
1275 * with NULL at the end).
1277 char hwrm_fw_name[16];
1279 * This field represents the name of mgmt FW (ASCII chars
1280 * with NULL at the end).
1282 char mgmt_fw_name[16];
1284 * This field represents the name of network control
1285 * firmware (ASCII chars with NULL at the end).
1287 char netctrl_fw_name[16];
1288 /* This field represents the active board package name. */
1289 char active_pkg_name[16];
1291 * This field represents the name of RoCE FW (ASCII chars
1292 * with NULL at the end).
1294 char roce_fw_name[16];
1295 /* This field returns the chip number. */
1297 /* This field returns the revision of chip. */
1299 /* This field returns the chip metal number. */
1301 /* This field returns the bond id of the chip. */
1302 uint8_t chip_bond_id;
1303 /* This value indicates the type of platform used for chip implementation. */
1304 uint8_t chip_platform_type;
1306 #define HWRM_VER_GET_OUTPUT_CHIP_PLATFORM_TYPE_ASIC UINT32_C(0x0)
1307 /* FPGA platform of the chip. */
1308 #define HWRM_VER_GET_OUTPUT_CHIP_PLATFORM_TYPE_FPGA UINT32_C(0x1)
1309 /* Palladium platform of the chip. */
1310 #define HWRM_VER_GET_OUTPUT_CHIP_PLATFORM_TYPE_PALLADIUM UINT32_C(0x2)
1311 #define HWRM_VER_GET_OUTPUT_CHIP_PLATFORM_TYPE_LAST \
1312 HWRM_VER_GET_OUTPUT_CHIP_PLATFORM_TYPE_PALLADIUM
1314 * This field returns the maximum value of request window that
1315 * is supported by the HWRM. The request window is mapped
1316 * into device address space using MMIO.
1318 uint16_t max_req_win_len;
1320 * This field returns the maximum value of response buffer in
1323 uint16_t max_resp_len;
1325 * This field returns the default request timeout value in
1328 uint16_t def_req_timeout;
1330 * This field will indicate if any subsystems is not fully
1335 * If set to 1, it will indicate to host drivers that firmware is
1336 * not ready to start full blown HWRM commands. Host drivers should
1337 * re-try HWRM_VER_GET with some timeout period. The timeout period
1338 * can be selected up to 5 seconds.
1339 * For Example, PCIe hot-plug:
1340 * Hot plug timing is system dependent. It generally takes up to
1341 * 600 miliseconds for firmware to clear DEV_NOT_RDY flag.
1342 * If set to 0, device is ready to accept all HWRM commands.
1344 #define HWRM_VER_GET_OUTPUT_FLAGS_DEV_NOT_RDY UINT32_C(0x1)
1346 * If set to 1, external version present.
1347 * If set to 0, external version not present.
1349 #define HWRM_VER_GET_OUTPUT_FLAGS_EXT_VER_AVAIL UINT32_C(0x2)
1350 uint8_t unused_0[2];
1352 * For backward compatibility this field must be set to 1.
1353 * Older drivers might look for this field to be 1 before
1354 * processing the message.
1358 * This field represents the major version of HWRM interface
1359 * specification supported by the HWRM implementation.
1360 * The interface major version is intended to change only when
1361 * non backward compatible changes are made to the HWRM
1362 * interface specification. A HWRM implementation that is
1363 * compliant with this specification shall provide value of 1
1366 uint16_t hwrm_intf_major;
1368 * This field represents the minor version of HWRM interface
1369 * specification supported by the HWRM implementation.
1370 * A change in interface minor version is used to reflect
1371 * significant backward compatible modification to HWRM
1372 * interface specification. This can be due to addition or
1373 * removal of functionality. HWRM interface specifications
1374 * with the same major version but different minor versions are
1375 * compatible. A HWRM implementation that is compliant with
1376 * this specification shall provide value of 2 in this field.
1378 uint16_t hwrm_intf_minor;
1380 * This field represents the update version of HWRM interface
1381 * specification supported by the HWRM implementation. The
1382 * interface update version is used to reflect minor changes or
1383 * bug fixes to a released HWRM interface specification.
1384 * A HWRM implementation that is compliant with this
1385 * specification shall provide value of 2 in this field.
1387 uint16_t hwrm_intf_build;
1389 * This field represents the patch version of HWRM interface
1390 * specification supported by the HWRM implementation.
1392 uint16_t hwrm_intf_patch;
1394 * This field represents the major version of HWRM firmware.
1395 * A change in firmware major version represents a major
1398 uint16_t hwrm_fw_major;
1400 * This field represents the minor version of HWRM firmware.
1401 * A change in firmware minor version represents significant
1402 * firmware functionality changes.
1404 uint16_t hwrm_fw_minor;
1406 * This field represents the build version of HWRM firmware.
1407 * A change in firmware build version represents bug fixes to
1408 * a released firmware.
1410 uint16_t hwrm_fw_build;
1412 * This field is a reserved field.
1413 * This field can be used to represent firmware branches or customer
1414 * specific releases tied to a specific (major,minor,update) version
1415 * of the HWRM firmware.
1417 uint16_t hwrm_fw_patch;
1419 * This field represents the major version of mgmt firmware.
1420 * A change in major version represents a major release.
1422 uint16_t mgmt_fw_major;
1424 * This field represents the minor version of HWRM firmware.
1425 * A change in firmware minor version represents significant
1426 * firmware functionality changes.
1428 uint16_t mgmt_fw_minor;
1430 * This field represents the build version of mgmt firmware.
1431 * A change in update version represents bug fixes.
1433 uint16_t mgmt_fw_build;
1435 * This field is a reserved field. This field can be used to
1436 * represent firmware branches or customer specific releases
1437 * tied to a specific (major,minor,update) version.
1439 uint16_t mgmt_fw_patch;
1441 * This field represents the major version of network control
1442 * firmware. A change in major version represents
1445 uint16_t netctrl_fw_major;
1447 * This field represents the minor version of network control
1448 * firmware. A change in minor version represents significant
1449 * functionality changes.
1451 uint16_t netctrl_fw_minor;
1453 * This field represents the build version of network control
1454 * firmware. A change in update version represents bug fixes.
1456 uint16_t netctrl_fw_build;
1458 * This field is a reserved field. This field can be used to
1459 * represent firmware branches or customer specific releases
1460 * tied to a specific (major,minor,update) version
1462 uint16_t netctrl_fw_patch;
1464 * This field represents the major version of RoCE firmware.
1465 * A change in major version represents a major release.
1467 uint16_t roce_fw_major;
1469 * This field represents the minor version of RoCE firmware.
1470 * A change in minor version represents significant
1471 * functionality changes.
1473 uint16_t roce_fw_minor;
1475 * This field represents the build version of RoCE firmware.
1476 * A change in update version represents bug fixes.
1478 uint16_t roce_fw_build;
1480 * This field is a reserved field. This field can be used to
1481 * represent firmware branches or customer specific releases
1482 * tied to a specific (major,minor,update) version
1484 uint16_t roce_fw_patch;
1486 * This field returns the maximum extended request length acceptable
1487 * by the device which allows requests greater than mailbox size when
1488 * used with the short cmd request format.
1490 uint16_t max_ext_req_len;
1491 uint8_t unused_1[5];
1493 * This field is used in Output records to indicate that the output
1494 * is completely written to RAM. This field should be read as '1'
1495 * to indicate that the output has been completely written.
1496 * When writing a command completion or response to an internal processor,
1497 * the order of writes has to be such that this field is written last.
1502 /* bd_base (size:64b/8B) */
1505 /* This value identifies the type of buffer descriptor. */
1506 #define BD_BASE_TYPE_MASK UINT32_C(0x3f)
1507 #define BD_BASE_TYPE_SFT 0
1509 * Indicates that this BD is 16B long and is used for
1510 * normal L2 packet transmission.
1512 #define BD_BASE_TYPE_TX_BD_SHORT UINT32_C(0x0)
1514 * Indicates that this BD is 1BB long and is an empty
1515 * TX BD. Not valid for use by the driver.
1517 #define BD_BASE_TYPE_TX_BD_EMPTY UINT32_C(0x1)
1519 * Indicates that this BD is 16B long and is an RX Producer
1520 * (i.e. empty) buffer descriptor.
1522 #define BD_BASE_TYPE_RX_PROD_PKT UINT32_C(0x4)
1524 * Indicates that this BD is 16B long and is an RX
1525 * Producer Buffer BD.
1527 #define BD_BASE_TYPE_RX_PROD_BFR UINT32_C(0x5)
1529 * Indicates that this BD is 16B long and is an
1530 * RX Producer Assembly Buffer Descriptor.
1532 #define BD_BASE_TYPE_RX_PROD_AGG UINT32_C(0x6)
1534 * Indicates that this BD is 32B long and is used for
1535 * normal L2 packet transmission.
1537 #define BD_BASE_TYPE_TX_BD_LONG UINT32_C(0x10)
1539 * Indicates that this BD is 32B long and is used for
1540 * L2 packet transmission for small packets that require
1543 #define BD_BASE_TYPE_TX_BD_LONG_INLINE UINT32_C(0x11)
1544 #define BD_BASE_TYPE_LAST BD_BASE_TYPE_TX_BD_LONG_INLINE
1545 uint8_t unused_1[7];
1548 /* tx_bd_short (size:128b/16B) */
1549 struct tx_bd_short {
1551 * All bits in this field must be valid on the first BD of a packet.
1552 * Only the packet_end bit must be valid for the remaining BDs
1555 uint16_t flags_type;
1556 /* This value identifies the type of buffer descriptor. */
1557 #define TX_BD_SHORT_TYPE_MASK UINT32_C(0x3f)
1558 #define TX_BD_SHORT_TYPE_SFT 0
1560 * Indicates that this BD is 16B long and is used for
1561 * normal L2 packet transmission.
1563 #define TX_BD_SHORT_TYPE_TX_BD_SHORT UINT32_C(0x0)
1564 #define TX_BD_SHORT_TYPE_LAST TX_BD_SHORT_TYPE_TX_BD_SHORT
1566 * All bits in this field must be valid on the first BD of a packet.
1567 * Only the packet_end bit must be valid for the remaining BDs
1570 #define TX_BD_SHORT_FLAGS_MASK UINT32_C(0xffc0)
1571 #define TX_BD_SHORT_FLAGS_SFT 6
1573 * If set to 1, the packet ends with the data in the buffer
1574 * pointed to by this descriptor. This flag must be
1575 * valid on every BD.
1577 #define TX_BD_SHORT_FLAGS_PACKET_END UINT32_C(0x40)
1579 * If set to 1, the device will not generate a completion for
1580 * this transmit packet unless there is an error in it's
1583 * is set to 0, then the packet will be completed normally.
1585 * This bit must be valid only on the first BD of a packet.
1587 #define TX_BD_SHORT_FLAGS_NO_CMPL UINT32_C(0x80)
1589 * This value indicates how many 16B BD locations are consumed
1590 * in the ring by this packet.
1591 * A value of 1 indicates that this BD is the only BD (and that
1592 * it is a short BD). A value
1593 * of 3 indicates either 3 short BDs or 1 long BD and one short
1594 * BD in the packet. A value of 0 indicates
1595 * that there are 32 BD locations in the packet (the maximum).
1597 * This field is valid only on the first BD of a packet.
1599 #define TX_BD_SHORT_FLAGS_BD_CNT_MASK UINT32_C(0x1f00)
1600 #define TX_BD_SHORT_FLAGS_BD_CNT_SFT 8
1602 * This value is a hint for the length of the entire packet.
1603 * It is used by the chip to optimize internal processing.
1605 * The packet will be dropped if the hint is too short.
1607 * This field is valid only on the first BD of a packet.
1609 #define TX_BD_SHORT_FLAGS_LHINT_MASK UINT32_C(0x6000)
1610 #define TX_BD_SHORT_FLAGS_LHINT_SFT 13
1611 /* indicates packet length < 512B */
1612 #define TX_BD_SHORT_FLAGS_LHINT_LT512 (UINT32_C(0x0) << 13)
1613 /* indicates 512 <= packet length < 1KB */
1614 #define TX_BD_SHORT_FLAGS_LHINT_LT1K (UINT32_C(0x1) << 13)
1615 /* indicates 1KB <= packet length < 2KB */
1616 #define TX_BD_SHORT_FLAGS_LHINT_LT2K (UINT32_C(0x2) << 13)
1617 /* indicates packet length >= 2KB */
1618 #define TX_BD_SHORT_FLAGS_LHINT_GTE2K (UINT32_C(0x3) << 13)
1619 #define TX_BD_SHORT_FLAGS_LHINT_LAST \
1620 TX_BD_SHORT_FLAGS_LHINT_GTE2K
1622 * If set to 1, the device immediately updates the Send Consumer
1623 * Index after the buffer associated with this descriptor has
1624 * been transferred via DMA to NIC memory from host memory. An
1625 * interrupt may or may not be generated according to the state
1626 * of the interrupt avoidance mechanisms. If this bit
1627 * is set to 0, then the Consumer Index is only updated as soon
1628 * as one of the host interrupt coalescing conditions has been met.
1630 * This bit must be valid on the first BD of a packet.
1632 #define TX_BD_SHORT_FLAGS_COAL_NOW UINT32_C(0x8000)
1634 * This is the length of the host physical buffer this BD describes
1637 * This field must be valid on all BDs of a packet.
1641 * The opaque data field is pass through to the completion and can be
1642 * used for any data that the driver wants to associate with the
1645 * This field must be valid on the first BD of a packet.
1649 * This is the host physical address for the portion of the packet
1650 * described by this TX BD.
1652 * This value must be valid on all BDs of a packet.
1657 /* tx_bd_long (size:128b/16B) */
1659 /* This value identifies the type of buffer descriptor. */
1660 uint16_t flags_type;
1662 * This value indicates the type of buffer descriptor.
1665 #define TX_BD_LONG_TYPE_MASK UINT32_C(0x3f)
1666 #define TX_BD_LONG_TYPE_SFT 0
1668 * Indicates that this BD is 32B long and is used for
1669 * normal L2 packet transmission.
1671 #define TX_BD_LONG_TYPE_TX_BD_LONG UINT32_C(0x10)
1672 #define TX_BD_LONG_TYPE_LAST TX_BD_LONG_TYPE_TX_BD_LONG
1674 * All bits in this field must be valid on the first BD of a packet.
1675 * Only the packet_end bit must be valid for the remaining BDs
1678 #define TX_BD_LONG_FLAGS_MASK UINT32_C(0xffc0)
1679 #define TX_BD_LONG_FLAGS_SFT 6
1681 * If set to 1, the packet ends with the data in the buffer
1682 * pointed to by this descriptor. This flag must be
1683 * valid on every BD.
1685 #define TX_BD_LONG_FLAGS_PACKET_END UINT32_C(0x40)
1687 * If set to 1, the device will not generate a completion for
1688 * this transmit packet unless there is an error in it's
1691 * is set to 0, then the packet will be completed normally.
1693 * This bit must be valid only on the first BD of a packet.
1695 #define TX_BD_LONG_FLAGS_NO_CMPL UINT32_C(0x80)
1697 * This value indicates how many 16B BD locations are consumed
1698 * in the ring by this packet.
1699 * A value of 1 indicates that this BD is the only BD (and that
1700 * it is a short BD). A value
1701 * of 3 indicates either 3 short BDs or 1 long BD and one short
1702 * BD in the packet. A value of 0 indicates
1703 * that there are 32 BD locations in the packet (the maximum).
1705 * This field is valid only on the first BD of a packet.
1707 #define TX_BD_LONG_FLAGS_BD_CNT_MASK UINT32_C(0x1f00)
1708 #define TX_BD_LONG_FLAGS_BD_CNT_SFT 8
1710 * This value is a hint for the length of the entire packet.
1711 * It is used by the chip to optimize internal processing.
1713 * The packet will be dropped if the hint is too short.
1715 * This field is valid only on the first BD of a packet.
1717 #define TX_BD_LONG_FLAGS_LHINT_MASK UINT32_C(0x6000)
1718 #define TX_BD_LONG_FLAGS_LHINT_SFT 13
1719 /* indicates packet length < 512B */
1720 #define TX_BD_LONG_FLAGS_LHINT_LT512 (UINT32_C(0x0) << 13)
1721 /* indicates 512 <= packet length < 1KB */
1722 #define TX_BD_LONG_FLAGS_LHINT_LT1K (UINT32_C(0x1) << 13)
1723 /* indicates 1KB <= packet length < 2KB */
1724 #define TX_BD_LONG_FLAGS_LHINT_LT2K (UINT32_C(0x2) << 13)
1725 /* indicates packet length >= 2KB */
1726 #define TX_BD_LONG_FLAGS_LHINT_GTE2K (UINT32_C(0x3) << 13)
1727 #define TX_BD_LONG_FLAGS_LHINT_LAST TX_BD_LONG_FLAGS_LHINT_GTE2K
1729 * If set to 1, the device immediately updates the Send Consumer
1730 * Index after the buffer associated with this descriptor has
1731 * been transferred via DMA to NIC memory from host memory. An
1732 * interrupt may or may not be generated according to the state
1733 * of the interrupt avoidance mechanisms. If this bit
1734 * is set to 0, then the Consumer Index is only updated as soon
1735 * as one of the host interrupt coalescing conditions has been met.
1737 * This bit must be valid on the first BD of a packet.
1739 #define TX_BD_LONG_FLAGS_COAL_NOW UINT32_C(0x8000)
1741 * This is the length of the host physical buffer this BD describes
1744 * This field must be valid on all BDs of a packet.
1748 * The opaque data field is pass through to the completion and can be
1749 * used for any data that the driver wants to associate with the
1752 * This field must be valid on the first BD of a packet.
1756 * This is the host physical address for the portion of the packet
1757 * described by this TX BD.
1759 * This value must be valid on all BDs of a packet.
1764 /* Last 16 bytes of tx_bd_long. */
1765 /* tx_bd_long_hi (size:128b/16B) */
1766 struct tx_bd_long_hi {
1768 * All bits in this field must be valid on the first BD of a packet.
1769 * Their value on other BDs of the packet will be ignored.
1773 * If set to 1, the controller replaces the TCP/UPD checksum
1774 * fields of normal TCP/UPD checksum, or the inner TCP/UDP
1775 * checksum field of the encapsulated TCP/UDP packets with the
1776 * hardware calculated TCP/UDP checksum for the packet associated
1777 * with this descriptor. The flag is ignored if the LSO flag is set.
1779 * This bit must be valid on the first BD of a packet.
1781 #define TX_BD_LONG_LFLAGS_TCP_UDP_CHKSUM UINT32_C(0x1)
1783 * If set to 1, the controller replaces the IP checksum of the
1784 * normal packets, or the inner IP checksum of the encapsulated
1785 * packets with the hardware calculated IP checksum for the
1786 * packet associated with this descriptor.
1788 * This bit must be valid on the first BD of a packet.
1790 #define TX_BD_LONG_LFLAGS_IP_CHKSUM UINT32_C(0x2)
1792 * If set to 1, the controller will not append an Ethernet CRC
1793 * to the end of the frame.
1795 * This bit must be valid on the first BD of a packet.
1797 * Packet must be 64B or longer when this flag is set. It is not
1798 * useful to use this bit with any form of TX offload such as
1799 * CSO or LSO. The intent is that the packet from the host already
1800 * has a valid Ethernet CRC on the packet.
1802 #define TX_BD_LONG_LFLAGS_NOCRC UINT32_C(0x4)
1804 * If set to 1, the device will record the time at which the packet
1805 * was actually transmitted at the TX MAC.
1807 * This bit must be valid on the first BD of a packet.
1809 #define TX_BD_LONG_LFLAGS_STAMP UINT32_C(0x8)
1811 * If set to 1, The controller replaces the tunnel IP checksum
1812 * field with hardware calculated IP checksum for the IP header
1813 * of the packet associated with this descriptor.
1815 * For outer UDP checksum, global outer UDP checksum TE_NIC register
1816 * needs to be enabled. If the global outer UDP checksum TE_NIC register
1817 * bit is set, outer UDP checksum will be calculated for the following
1819 * 1. Packets with tcp_udp_chksum flag set to offload checksum for inner
1820 * packet AND the inner packet is TCP/UDP. If the inner packet is ICMP for
1821 * example (non-TCP/UDP), even if the tcp_udp_chksum is set, the outer UDP
1822 * checksum will not be calculated.
1823 * 2. Packets with lso flag set which implies inner TCP checksum calculation
1824 * as part of LSO operation.
1826 #define TX_BD_LONG_LFLAGS_T_IP_CHKSUM UINT32_C(0x10)
1828 * If set to 1, the device will treat this packet with LSO(Large
1829 * Send Offload) processing for both normal or encapsulated
1830 * packets, which is a form of TCP segmentation. When this bit
1831 * is 1, the hdr_size and mss fields must be valid. The driver
1832 * doesn't need to set t_ip_chksum, ip_chksum, and tcp_udp_chksum
1833 * flags since the controller will replace the appropriate
1834 * checksum fields for segmented packets.
1836 * When this bit is 1, the hdr_size and mss fields must be valid.
1838 #define TX_BD_LONG_LFLAGS_LSO UINT32_C(0x20)
1840 * If set to zero when LSO is '1', then the IPID will be treated
1841 * as a 16b number and will be wrapped if it exceeds a value of
1844 * If set to one when LSO is '1', then the IPID will be treated
1845 * as a 15b number and will be wrapped if it exceeds a value 0f
1848 #define TX_BD_LONG_LFLAGS_IPID_FMT UINT32_C(0x40)
1850 * If set to zero when LSO is '1', then the IPID of the tunnel
1851 * IP header will not be modified during LSO operations.
1853 * If set to one when LSO is '1', then the IPID of the tunnel
1854 * IP header will be incremented for each subsequent segment of an
1857 * The flag is ignored if the LSO packet is a normal (non-tunneled)
1860 #define TX_BD_LONG_LFLAGS_T_IPID UINT32_C(0x80)
1862 * If set to '1', then the RoCE ICRC will be appended to the
1863 * packet. Packet must be a valid RoCE format packet.
1865 #define TX_BD_LONG_LFLAGS_ROCE_CRC UINT32_C(0x100)
1867 * If set to '1', then the FCoE CRC will be appended to the
1868 * packet. Packet must be a valid FCoE format packet.
1870 #define TX_BD_LONG_LFLAGS_FCOE_CRC UINT32_C(0x200)
1873 * When LSO is '1', this field must contain the offset of the
1874 * TCP payload from the beginning of the packet in as
1875 * 16b words. In case of encapsulated/tunneling packet, this field
1876 * contains the offset of the inner TCP payload from beginning of the
1877 * packet as 16-bit words.
1879 * This value must be valid on the first BD of a packet.
1881 #define TX_BD_LONG_HDR_SIZE_MASK UINT32_C(0x1ff)
1882 #define TX_BD_LONG_HDR_SIZE_SFT 0
1885 * This is the MSS value that will be used to do the LSO processing.
1886 * The value is the length in bytes of the TCP payload for each
1887 * segment generated by the LSO operation.
1889 * This value must be valid on the first BD of a packet.
1891 #define TX_BD_LONG_MSS_MASK UINT32_C(0x7fff)
1892 #define TX_BD_LONG_MSS_SFT 0
1895 * This value selects a CFA action to perform on the packet.
1896 * Set this value to zero if no CFA action is desired.
1898 * This value must be valid on the first BD of a packet.
1900 uint16_t cfa_action;
1902 * This value is action meta-data that defines CFA edit operations
1903 * that are done in addition to any action editing.
1906 /* When key=1, This is the VLAN tag VID value. */
1907 #define TX_BD_LONG_CFA_META_VLAN_VID_MASK UINT32_C(0xfff)
1908 #define TX_BD_LONG_CFA_META_VLAN_VID_SFT 0
1909 /* When key=1, This is the VLAN tag DE value. */
1910 #define TX_BD_LONG_CFA_META_VLAN_DE UINT32_C(0x1000)
1911 /* When key=1, This is the VLAN tag PRI value. */
1912 #define TX_BD_LONG_CFA_META_VLAN_PRI_MASK UINT32_C(0xe000)
1913 #define TX_BD_LONG_CFA_META_VLAN_PRI_SFT 13
1914 /* When key=1, This is the VLAN tag TPID select value. */
1915 #define TX_BD_LONG_CFA_META_VLAN_TPID_MASK UINT32_C(0x70000)
1916 #define TX_BD_LONG_CFA_META_VLAN_TPID_SFT 16
1918 #define TX_BD_LONG_CFA_META_VLAN_TPID_TPID88A8 (UINT32_C(0x0) << 16)
1920 #define TX_BD_LONG_CFA_META_VLAN_TPID_TPID8100 (UINT32_C(0x1) << 16)
1922 #define TX_BD_LONG_CFA_META_VLAN_TPID_TPID9100 (UINT32_C(0x2) << 16)
1924 #define TX_BD_LONG_CFA_META_VLAN_TPID_TPID9200 (UINT32_C(0x3) << 16)
1926 #define TX_BD_LONG_CFA_META_VLAN_TPID_TPID9300 (UINT32_C(0x4) << 16)
1927 /* Value programmed in CFA VLANTPID register. */
1928 #define TX_BD_LONG_CFA_META_VLAN_TPID_TPIDCFG (UINT32_C(0x5) << 16)
1929 #define TX_BD_LONG_CFA_META_VLAN_TPID_LAST \
1930 TX_BD_LONG_CFA_META_VLAN_TPID_TPIDCFG
1931 /* When key=1, This is the VLAN tag TPID select value. */
1932 #define TX_BD_LONG_CFA_META_VLAN_RESERVED_MASK UINT32_C(0xff80000)
1933 #define TX_BD_LONG_CFA_META_VLAN_RESERVED_SFT 19
1935 * This field identifies the type of edit to be performed
1938 * This value must be valid on the first BD of a packet.
1940 #define TX_BD_LONG_CFA_META_KEY_MASK UINT32_C(0xf0000000)
1941 #define TX_BD_LONG_CFA_META_KEY_SFT 28
1943 #define TX_BD_LONG_CFA_META_KEY_NONE (UINT32_C(0x0) << 28)
1945 * - meta[17:16] - TPID select value (0 = 0x8100).
1946 * - meta[15:12] - PRI/DE value.
1947 * - meta[11:0] - VID value.
1949 #define TX_BD_LONG_CFA_META_KEY_VLAN_TAG (UINT32_C(0x1) << 28)
1950 #define TX_BD_LONG_CFA_META_KEY_LAST \
1951 TX_BD_LONG_CFA_META_KEY_VLAN_TAG
1955 * This structure is used to inform the NIC of packet data that needs to be
1956 * transmitted with additional processing that requires extra data such as
1957 * VLAN insertion plus attached inline data. This BD type may be used to
1958 * improve latency for small packets needing the additional extended features
1959 * supported by long BDs.
1961 /* tx_bd_long_inline (size:256b/32B) */
1962 struct tx_bd_long_inline {
1963 uint16_t flags_type;
1964 /* This value identifies the type of buffer descriptor. */
1965 #define TX_BD_LONG_INLINE_TYPE_MASK UINT32_C(0x3f)
1966 #define TX_BD_LONG_INLINE_TYPE_SFT 0
1968 * This type of BD is 32B long and is used for inline L2 packet
1971 #define TX_BD_LONG_INLINE_TYPE_TX_BD_LONG_INLINE UINT32_C(0x11)
1972 #define TX_BD_LONG_INLINE_TYPE_LAST \
1973 TX_BD_LONG_INLINE_TYPE_TX_BD_LONG_INLINE
1975 * All bits in this field may be set on the first BD of a packet.
1976 * Only the packet_end bit may be set in non-first BDs.
1978 #define TX_BD_LONG_INLINE_FLAGS_MASK UINT32_C(0xffc0)
1979 #define TX_BD_LONG_INLINE_FLAGS_SFT 6
1981 * If set to 1, the packet ends with the data in the buffer
1982 * pointed to by this descriptor. This flag must be
1983 * valid on every BD.
1985 #define TX_BD_LONG_INLINE_FLAGS_PACKET_END UINT32_C(0x40)
1987 * If set to 1, the device will not generate a completion for
1988 * this transmit packet unless there is an error in its processing.
1989 * If this bit is set to 0, then the packet will be completed
1992 * This bit may be set only on the first BD of a packet.
1994 #define TX_BD_LONG_INLINE_FLAGS_NO_CMPL UINT32_C(0x80)
1996 * This value indicates how many 16B BD locations are consumed
1997 * in the ring by this packet, including the BD and inline
2000 #define TX_BD_LONG_INLINE_FLAGS_BD_CNT_MASK UINT32_C(0x1f00)
2001 #define TX_BD_LONG_INLINE_FLAGS_BD_CNT_SFT 8
2002 /* This field is deprecated. */
2003 #define TX_BD_LONG_INLINE_FLAGS_LHINT_MASK UINT32_C(0x6000)
2004 #define TX_BD_LONG_INLINE_FLAGS_LHINT_SFT 13
2006 * If set to 1, the device immediately updates the Send Consumer
2007 * Index after the buffer associated with this descriptor has
2008 * been transferred via DMA to NIC memory from host memory. An
2009 * interrupt may or may not be generated according to the state
2010 * of the interrupt avoidance mechanisms. If this bit
2011 * is set to 0, then the Consumer Index is only updated as soon
2012 * as one of the host interrupt coalescing conditions has been met.
2014 * This bit must be valid on the first BD of a packet.
2016 #define TX_BD_LONG_INLINE_FLAGS_COAL_NOW UINT32_C(0x8000)
2018 * This is the length of the inline data, not including BD length, in
2020 * The maximum value is 480.
2022 * This field must be valid on all BDs of a packet.
2026 * The opaque data field is passed through to the completion and can be
2027 * used for any data that the driver wants to associate with the transmit
2030 * This field must be valid on the first BD of a packet.
2035 * All bits in this field must be valid on the first BD of a packet.
2036 * Their value on other BDs of the packet is ignored.
2040 * If set to 1, the controller replaces the TCP/UPD checksum
2041 * fields of normal TCP/UPD checksum, or the inner TCP/UDP
2042 * checksum field of the encapsulated TCP/UDP packets with the
2043 * hardware calculated TCP/UDP checksum for the packet associated
2044 * with this descriptor. The flag is ignored if the LSO flag is set.
2046 #define TX_BD_LONG_INLINE_LFLAGS_TCP_UDP_CHKSUM UINT32_C(0x1)
2048 * If set to 1, the controller replaces the IP checksum of the
2049 * normal packets, or the inner IP checksum of the encapsulated
2050 * packets with the hardware calculated IP checksum for the
2051 * packet associated with this descriptor.
2053 #define TX_BD_LONG_INLINE_LFLAGS_IP_CHKSUM UINT32_C(0x2)
2055 * If set to 1, the controller will not append an Ethernet CRC
2056 * to the end of the frame.
2058 * Packet must be 64B or longer when this flag is set. It is not
2059 * useful to use this bit with any form of TX offload such as
2060 * CSO or LSO. The intent is that the packet from the host already
2061 * has a valid Ethernet CRC on the packet.
2063 #define TX_BD_LONG_INLINE_LFLAGS_NOCRC UINT32_C(0x4)
2065 * If set to 1, the device will record the time at which the packet
2066 * was actually transmitted at the TX MAC.
2068 #define TX_BD_LONG_INLINE_LFLAGS_STAMP UINT32_C(0x8)
2070 * If set to 1, the controller replaces the tunnel IP checksum
2071 * field with hardware calculated IP checksum for the IP header
2072 * of the packet associated with this descriptor. The hardware
2073 * updates an outer UDP checksum if it is non-zero.
2075 #define TX_BD_LONG_INLINE_LFLAGS_T_IP_CHKSUM UINT32_C(0x10)
2077 * This bit must be 0 for BDs of this type. LSO is not supported with
2080 #define TX_BD_LONG_INLINE_LFLAGS_LSO UINT32_C(0x20)
2081 /* Since LSO is not supported with inline BDs, this bit is not used. */
2082 #define TX_BD_LONG_INLINE_LFLAGS_IPID_FMT UINT32_C(0x40)
2083 /* Since LSO is not supported with inline BDs, this bit is not used. */
2084 #define TX_BD_LONG_INLINE_LFLAGS_T_IPID UINT32_C(0x80)
2086 * If set to '1', then the RoCE ICRC will be appended to the
2087 * packet. Packet must be a valid RoCE format packet.
2089 #define TX_BD_LONG_INLINE_LFLAGS_ROCE_CRC UINT32_C(0x100)
2091 * If set to '1', then the FCoE CRC will be appended to the
2092 * packet. Packet must be a valid FCoE format packet.
2094 #define TX_BD_LONG_INLINE_LFLAGS_FCOE_CRC UINT32_C(0x200)
2099 * This value selects a CFA action to perform on the packet.
2100 * Set this value to zero if no CFA action is desired.
2102 * This value must be valid on the first BD of a packet.
2104 uint16_t cfa_action;
2106 * This value is action meta-data that defines CFA edit operations
2107 * that are done in addition to any action editing.
2110 /* When key = 1, this is the VLAN tag VID value. */
2111 #define TX_BD_LONG_INLINE_CFA_META_VLAN_VID_MASK UINT32_C(0xfff)
2112 #define TX_BD_LONG_INLINE_CFA_META_VLAN_VID_SFT 0
2113 /* When key = 1, this is the VLAN tag DE value. */
2114 #define TX_BD_LONG_INLINE_CFA_META_VLAN_DE UINT32_C(0x1000)
2115 /* When key = 1, this is the VLAN tag PRI value. */
2116 #define TX_BD_LONG_INLINE_CFA_META_VLAN_PRI_MASK UINT32_C(0xe000)
2117 #define TX_BD_LONG_INLINE_CFA_META_VLAN_PRI_SFT 13
2118 /* When key = 1, this is the VLAN tag TPID select value. */
2119 #define TX_BD_LONG_INLINE_CFA_META_VLAN_TPID_MASK UINT32_C(0x70000)
2120 #define TX_BD_LONG_INLINE_CFA_META_VLAN_TPID_SFT 16
2122 #define TX_BD_LONG_INLINE_CFA_META_VLAN_TPID_TPID88A8 \
2123 (UINT32_C(0x0) << 16)
2125 #define TX_BD_LONG_INLINE_CFA_META_VLAN_TPID_TPID8100 \
2126 (UINT32_C(0x1) << 16)
2128 #define TX_BD_LONG_INLINE_CFA_META_VLAN_TPID_TPID9100 \
2129 (UINT32_C(0x2) << 16)
2131 #define TX_BD_LONG_INLINE_CFA_META_VLAN_TPID_TPID9200 \
2132 (UINT32_C(0x3) << 16)
2134 #define TX_BD_LONG_INLINE_CFA_META_VLAN_TPID_TPID9300 \
2135 (UINT32_C(0x4) << 16)
2136 /* Value programmed in CFA VLANTPID register. */
2137 #define TX_BD_LONG_INLINE_CFA_META_VLAN_TPID_TPIDCFG \
2138 (UINT32_C(0x5) << 16)
2139 #define TX_BD_LONG_INLINE_CFA_META_VLAN_TPID_LAST \
2140 TX_BD_LONG_INLINE_CFA_META_VLAN_TPID_TPIDCFG
2141 #define TX_BD_LONG_INLINE_CFA_META_VLAN_RESERVED_MASK \
2143 #define TX_BD_LONG_INLINE_CFA_META_VLAN_RESERVED_SFT 19
2145 * This field identifies the type of edit to be performed
2148 * This value must be valid on the first BD of a packet.
2150 #define TX_BD_LONG_INLINE_CFA_META_KEY_MASK \
2151 UINT32_C(0xf0000000)
2152 #define TX_BD_LONG_INLINE_CFA_META_KEY_SFT 28
2154 #define TX_BD_LONG_INLINE_CFA_META_KEY_NONE \
2155 (UINT32_C(0x0) << 28)
2157 * - meta[17:16] - TPID select value (0 = 0x8100).
2158 * - meta[15:12] - PRI/DE value.
2159 * - meta[11:0] - VID value.
2161 #define TX_BD_LONG_INLINE_CFA_META_KEY_VLAN_TAG \
2162 (UINT32_C(0x1) << 28)
2163 #define TX_BD_LONG_INLINE_CFA_META_KEY_LAST \
2164 TX_BD_LONG_INLINE_CFA_META_KEY_VLAN_TAG
2167 /* tx_bd_empty (size:128b/16B) */
2168 struct tx_bd_empty {
2169 /* This value identifies the type of buffer descriptor. */
2171 #define TX_BD_EMPTY_TYPE_MASK UINT32_C(0x3f)
2172 #define TX_BD_EMPTY_TYPE_SFT 0
2174 * Indicates that this BD is 1BB long and is an empty
2175 * TX BD. Not valid for use by the driver.
2177 #define TX_BD_EMPTY_TYPE_TX_BD_EMPTY UINT32_C(0x1)
2178 #define TX_BD_EMPTY_TYPE_LAST TX_BD_EMPTY_TYPE_TX_BD_EMPTY
2179 uint8_t unused_1[3];
2181 uint8_t unused_3[3];
2182 uint8_t unused_4[8];
2185 /* rx_prod_pkt_bd (size:128b/16B) */
2186 struct rx_prod_pkt_bd {
2187 /* This value identifies the type of buffer descriptor. */
2188 uint16_t flags_type;
2189 /* This value identifies the type of buffer descriptor. */
2190 #define RX_PROD_PKT_BD_TYPE_MASK UINT32_C(0x3f)
2191 #define RX_PROD_PKT_BD_TYPE_SFT 0
2193 * Indicates that this BD is 16B long and is an RX Producer
2194 * (i.e. empty) buffer descriptor.
2196 #define RX_PROD_PKT_BD_TYPE_RX_PROD_PKT UINT32_C(0x4)
2197 #define RX_PROD_PKT_BD_TYPE_LAST \
2198 RX_PROD_PKT_BD_TYPE_RX_PROD_PKT
2199 #define RX_PROD_PKT_BD_FLAGS_MASK UINT32_C(0xffc0)
2200 #define RX_PROD_PKT_BD_FLAGS_SFT 6
2202 * If set to 1, the packet will be placed at the address plus
2203 * 2B. The 2 Bytes of padding will be written as zero.
2205 #define RX_PROD_PKT_BD_FLAGS_SOP_PAD UINT32_C(0x40)
2207 * If set to 1, the packet write will be padded out to the
2208 * nearest cache-line with zero value padding.
2210 #define RX_PROD_PKT_BD_FLAGS_EOP_PAD UINT32_C(0x80)
2212 * This field has been deprecated. There can be no additional
2213 * BDs for this packet from this ring.
2216 * This value is the number of additional buffers in the ring that
2217 * describe the buffer space to be consumed for this packet.
2218 * If the value is zero, then the packet must fit within the
2219 * space described by this BD. If this value is 1 or more, it
2220 * indicates how many additional "buffer" BDs are in the ring
2221 * immediately following this BD to be used for the same
2222 * network packet. Even if the packet to be placed does not need
2223 * all the additional buffers, they will be consumed anyway.
2225 #define RX_PROD_PKT_BD_FLAGS_BUFFERS_MASK UINT32_C(0x300)
2226 #define RX_PROD_PKT_BD_FLAGS_BUFFERS_SFT 8
2228 * This is the length in Bytes of the host physical buffer where
2229 * data for the packet may be placed in host memory.
2233 * The opaque data field is pass through to the completion and can be
2234 * used for any data that the driver wants to associate with this
2235 * receive buffer set.
2239 * This is the host physical address where data for the packet may
2240 * be placed in host memory.
2245 /* rx_prod_bfr_bd (size:128b/16B) */
2246 struct rx_prod_bfr_bd {
2247 /* This value identifies the type of buffer descriptor. */
2248 uint16_t flags_type;
2249 /* This value identifies the type of buffer descriptor. */
2250 #define RX_PROD_BFR_BD_TYPE_MASK UINT32_C(0x3f)
2251 #define RX_PROD_BFR_BD_TYPE_SFT 0
2253 * Indicates that this BD is 16B long and is an RX
2254 * Producer Buffer BD.
2256 #define RX_PROD_BFR_BD_TYPE_RX_PROD_BFR UINT32_C(0x5)
2257 #define RX_PROD_BFR_BD_TYPE_LAST RX_PROD_BFR_BD_TYPE_RX_PROD_BFR
2258 #define RX_PROD_BFR_BD_FLAGS_MASK UINT32_C(0xffc0)
2259 #define RX_PROD_BFR_BD_FLAGS_SFT 6
2261 * This is the length in Bytes of the host physical buffer where
2262 * data for the packet may be placed in host memory.
2265 /* This field is not used. */
2268 * This is the host physical address where data for the packet may
2269 * be placed in host memory.
2274 /* rx_prod_agg_bd (size:128b/16B) */
2275 struct rx_prod_agg_bd {
2276 /* This value identifies the type of buffer descriptor. */
2277 uint16_t flags_type;
2278 /* This value identifies the type of buffer descriptor. */
2279 #define RX_PROD_AGG_BD_TYPE_MASK UINT32_C(0x3f)
2280 #define RX_PROD_AGG_BD_TYPE_SFT 0
2282 * Indicates that this BD is 16B long and is an
2283 * RX Producer Assembly Buffer Descriptor.
2285 #define RX_PROD_AGG_BD_TYPE_RX_PROD_AGG UINT32_C(0x6)
2286 #define RX_PROD_AGG_BD_TYPE_LAST \
2287 RX_PROD_AGG_BD_TYPE_RX_PROD_AGG
2288 #define RX_PROD_AGG_BD_FLAGS_MASK UINT32_C(0xffc0)
2289 #define RX_PROD_AGG_BD_FLAGS_SFT 6
2291 * If set to 1, the packet write will be padded out to the
2292 * nearest cache-line with zero value padding.
2294 #define RX_PROD_AGG_BD_FLAGS_EOP_PAD UINT32_C(0x40)
2296 * This is the length in Bytes of the host physical buffer where
2297 * data for the packet may be placed in host memory.
2301 * The opaque data field is pass through to the completion and can be
2302 * used for any data that the driver wants to associate with this
2303 * receive assembly buffer.
2307 * This is the host physical address where data for the packet may
2308 * be placed in host memory.
2313 /* cmpl_base (size:128b/16B) */
2317 * This field indicates the exact type of the completion.
2318 * By convention, the LSB identifies the length of the
2319 * record in 16B units. Even values indicate 16B
2320 * records. Odd values indicate 32B
2323 #define CMPL_BASE_TYPE_MASK UINT32_C(0x3f)
2324 #define CMPL_BASE_TYPE_SFT 0
2327 * Completion of TX packet. Length = 16B
2329 #define CMPL_BASE_TYPE_TX_L2 UINT32_C(0x0)
2332 * Completion of NO-OP. Length = 16B
2334 #define CMPL_BASE_TYPE_NO_OP UINT32_C(0x1)
2336 * TX L2 coalesced completion:
2337 * Completion of coalesced TX packet. Length = 16B
2339 #define CMPL_BASE_TYPE_TX_L2_COAL UINT32_C(0x2)
2341 * TX L2 PTP completion:
2342 * Completion of PTP TX packet. Length = 32B
2344 #define CMPL_BASE_TYPE_TX_L2_PTP UINT32_C(0x3)
2346 * RX L2 TPA Start V2 Completion:
2347 * Completion of and L2 RX packet. Length = 32B
2348 * This is the new version of the RX_TPA_START completion used
2349 * in SR2 and later chips.
2351 #define CMPL_BASE_TYPE_RX_TPA_START_V2 UINT32_C(0xd)
2353 * RX L2 V2 completion:
2354 * Completion of and L2 RX packet. Length = 32B
2355 * This is the new version of the RX_L2 completion used in SR2
2358 #define CMPL_BASE_TYPE_RX_L2_V2 UINT32_C(0xf)
2361 * Completion of and L2 RX packet. Length = 32B
2363 #define CMPL_BASE_TYPE_RX_L2 UINT32_C(0x11)
2365 * RX Aggregation Buffer completion :
2366 * Completion of an L2 aggregation buffer in support of
2367 * TPA, HDS, or Jumbo packet completion. Length = 16B
2369 #define CMPL_BASE_TYPE_RX_AGG UINT32_C(0x12)
2371 * RX L2 TPA Start Completion:
2372 * Completion at the beginning of a TPA operation.
2375 #define CMPL_BASE_TYPE_RX_TPA_START UINT32_C(0x13)
2377 * RX L2 TPA End Completion:
2378 * Completion at the end of a TPA operation.
2381 #define CMPL_BASE_TYPE_RX_TPA_END UINT32_C(0x15)
2383 * Statistics Ejection Completion:
2384 * Completion of statistics data ejection buffer.
2387 #define CMPL_BASE_TYPE_STAT_EJECT UINT32_C(0x1a)
2389 * VEE Flush Completion:
2390 * This completion is inserted manually by
2391 * the Primate and processed by the VEE hardware to ensure that
2392 * all completions on a VEE function have been processed by the
2393 * VEE hardware before FLR process is completed.
2395 #define CMPL_BASE_TYPE_VEE_FLUSH UINT32_C(0x1c)
2397 * Mid Path Short Completion :
2398 * Completion of a Mid Path Command. Length = 16B
2400 #define CMPL_BASE_TYPE_MID_PATH_SHORT UINT32_C(0x1e)
2402 * Mid Path Long Completion :
2403 * Completion of a Mid Path Command. Length = 32B
2405 #define CMPL_BASE_TYPE_MID_PATH_LONG UINT32_C(0x1f)
2407 * HWRM Command Completion:
2408 * Completion of an HWRM command.
2410 #define CMPL_BASE_TYPE_HWRM_DONE UINT32_C(0x20)
2411 /* Forwarded HWRM Request */
2412 #define CMPL_BASE_TYPE_HWRM_FWD_REQ UINT32_C(0x22)
2413 /* Forwarded HWRM Response */
2414 #define CMPL_BASE_TYPE_HWRM_FWD_RESP UINT32_C(0x24)
2415 /* HWRM Asynchronous Event Information */
2416 #define CMPL_BASE_TYPE_HWRM_ASYNC_EVENT UINT32_C(0x2e)
2417 /* CQ Notification */
2418 #define CMPL_BASE_TYPE_CQ_NOTIFICATION UINT32_C(0x30)
2419 /* SRQ Threshold Event */
2420 #define CMPL_BASE_TYPE_SRQ_EVENT UINT32_C(0x32)
2421 /* DBQ Threshold Event */
2422 #define CMPL_BASE_TYPE_DBQ_EVENT UINT32_C(0x34)
2423 /* QP Async Notification */
2424 #define CMPL_BASE_TYPE_QP_EVENT UINT32_C(0x38)
2425 /* Function Async Notification */
2426 #define CMPL_BASE_TYPE_FUNC_EVENT UINT32_C(0x3a)
2427 #define CMPL_BASE_TYPE_LAST CMPL_BASE_TYPE_FUNC_EVENT
2433 * This value is written by the NIC such that it will be different
2434 * for each pass through the completion queue. The even passes
2435 * will write 1. The odd passes will write 0.
2438 #define CMPL_BASE_V UINT32_C(0x1)
2439 #define CMPL_BASE_INFO3_MASK UINT32_C(0xfffffffe)
2440 #define CMPL_BASE_INFO3_SFT 1
2445 /* tx_cmpl (size:128b/16B) */
2447 uint16_t flags_type;
2449 * This field indicates the exact type of the completion.
2450 * By convention, the LSB identifies the length of the
2451 * record in 16B units. Even values indicate 16B
2452 * records. Odd values indicate 32B
2455 #define TX_CMPL_TYPE_MASK UINT32_C(0x3f)
2456 #define TX_CMPL_TYPE_SFT 0
2459 * Completion of TX packet. Length = 16B
2461 #define TX_CMPL_TYPE_TX_L2 UINT32_C(0x0)
2462 #define TX_CMPL_TYPE_LAST TX_CMPL_TYPE_TX_L2
2463 #define TX_CMPL_FLAGS_MASK UINT32_C(0xffc0)
2464 #define TX_CMPL_FLAGS_SFT 6
2466 * When this bit is '1', it indicates a packet that has an
2467 * error of some type. Type of error is indicated in
2470 #define TX_CMPL_FLAGS_ERROR UINT32_C(0x40)
2472 * When this bit is '1', it indicates that the packet completed
2473 * was transmitted using the push acceleration data provided
2474 * by the driver. When this bit is '0', it indicates that the
2475 * packet had not push acceleration data written or was executed
2476 * as a normal packet even though push data was provided.
2478 #define TX_CMPL_FLAGS_PUSH UINT32_C(0x80)
2479 /* unused1 is 16 b */
2482 * This is a copy of the opaque field from the first TX BD of this
2483 * transmitted packet. Note that, if the packet was described by a short
2484 * CSO or short CSO inline BD, then the 16-bit opaque field from the
2485 * short CSO BD will appear in the bottom 16 bits of this field.
2490 * This value is written by the NIC such that it will be different
2491 * for each pass through the completion queue. The even passes
2492 * will write 1. The odd passes will write 0.
2494 #define TX_CMPL_V UINT32_C(0x1)
2495 #define TX_CMPL_ERRORS_MASK UINT32_C(0xfffe)
2496 #define TX_CMPL_ERRORS_SFT 1
2498 * This error indicates that there was some sort of problem
2499 * with the BDs for the packet.
2501 #define TX_CMPL_ERRORS_BUFFER_ERROR_MASK UINT32_C(0xe)
2502 #define TX_CMPL_ERRORS_BUFFER_ERROR_SFT 1
2504 #define TX_CMPL_ERRORS_BUFFER_ERROR_NO_ERROR \
2505 (UINT32_C(0x0) << 1)
2508 * BDs were not formatted correctly.
2510 #define TX_CMPL_ERRORS_BUFFER_ERROR_BAD_FMT \
2511 (UINT32_C(0x2) << 1)
2512 #define TX_CMPL_ERRORS_BUFFER_ERROR_LAST \
2513 TX_CMPL_ERRORS_BUFFER_ERROR_BAD_FMT
2515 * When this bit is '1', it indicates that the length of
2516 * the packet was zero. No packet was transmitted.
2518 #define TX_CMPL_ERRORS_ZERO_LENGTH_PKT UINT32_C(0x10)
2520 * When this bit is '1', it indicates that the packet
2521 * was longer than the programmed limit in TDI. No
2522 * packet was transmitted.
2524 #define TX_CMPL_ERRORS_EXCESSIVE_BD_LENGTH UINT32_C(0x20)
2526 * When this bit is '1', it indicates that one or more of the
2527 * BDs associated with this packet generated a PCI error.
2528 * This probably means the address was not valid.
2530 #define TX_CMPL_ERRORS_DMA_ERROR UINT32_C(0x40)
2532 * When this bit is '1', it indicates that the packet was longer
2533 * than indicated by the hint. No packet was transmitted.
2535 #define TX_CMPL_ERRORS_HINT_TOO_SHORT UINT32_C(0x80)
2537 * When this bit is '1', it indicates that the packet was
2538 * dropped due to Poison TLP error on one or more of the
2539 * TLPs in the PXP completion.
2541 #define TX_CMPL_ERRORS_POISON_TLP_ERROR UINT32_C(0x100)
2543 * When this bit is '1', it indicates that the packet was dropped
2544 * due to a transient internal error in TDC. The packet or LSO can
2545 * be retried and may transmit successfully on a subsequent attempt.
2547 #define TX_CMPL_ERRORS_INTERNAL_ERROR UINT32_C(0x200)
2549 * When this bit is '1', it was not possible to collect a a timestamp
2550 * for a PTP completion, in which case the timestamp_hi and
2551 * timestamp_lo fields are invalid. When this bit is '0' for a PTP
2552 * completion, the timestamp_hi and timestamp_lo fields are valid.
2553 * RJRN will copy the value of this bit into the field of the same
2554 * name in all TX completions, regardless of whether such completions
2555 * are PTP completions or other TX completions.
2557 #define TX_CMPL_ERRORS_TIMESTAMP_INVALID_ERROR UINT32_C(0x400)
2558 /* unused2 is 16 b */
2560 /* unused3 is 32 b */
2564 /* tx_cmpl_coal (size:128b/16B) */
2565 struct tx_cmpl_coal {
2566 uint16_t flags_type;
2568 * This field indicates the exact type of the completion.
2569 * By convention, the LSB identifies the length of the
2570 * record in 16B units. Even values indicate 16B
2571 * records. Odd values indicate 32B
2574 #define TX_CMPL_COAL_TYPE_MASK UINT32_C(0x3f)
2575 #define TX_CMPL_COAL_TYPE_SFT 0
2577 * TX L2 coalesced completion:
2578 * Completion of TX packet. Length = 16B
2580 #define TX_CMPL_COAL_TYPE_TX_L2_COAL UINT32_C(0x2)
2581 #define TX_CMPL_COAL_TYPE_LAST TX_CMPL_COAL_TYPE_TX_L2_COAL
2582 #define TX_CMPL_COAL_FLAGS_MASK UINT32_C(0xffc0)
2583 #define TX_CMPL_COAL_FLAGS_SFT 6
2585 * When this bit is '1', it indicates a packet that has an
2586 * error of some type. Type of error is indicated in
2589 #define TX_CMPL_COAL_FLAGS_ERROR UINT32_C(0x40)
2591 * When this bit is '1', it indicates that the packet completed
2592 * was transmitted using the push acceleration data provided
2593 * by the driver. When this bit is '0', it indicates that the
2594 * packet had not push acceleration data written or was executed
2595 * as a normal packet even though push data was provided.
2597 #define TX_CMPL_COAL_FLAGS_PUSH UINT32_C(0x80)
2598 /* unused1 is 16 b */
2601 * This is a copy of the opaque field from the first TX BD of the packet
2602 * which corresponds with the reported sq_cons_idx. Note that, with
2603 * coalesced completions, completions are generated for only some of the
2604 * packets. The driver will see the opaque field for only those packets.
2605 * Note that, if the packet was described by a short CSO or short CSO
2606 * inline BD, then the 16-bit opaque field from the short CSO BD will
2607 * appear in the bottom 16 bits of this field. For TX rings with
2608 * completion coalescing enabled (which would use the coalesced
2609 * completion record), it is suggested that the driver populate the
2610 * opaque field to indicate the specific TX ring with which the
2611 * completion is associated, then utilize the opaque and sq_cons_idx
2612 * fields in the coalesced completion record to determine the specific
2613 * packets that are to be completed on that ring.
2618 * This value is written by the NIC such that it will be different
2619 * for each pass through the completion queue. The even passes
2620 * will write 1. The odd passes will write 0.
2622 #define TX_CMPL_COAL_V UINT32_C(0x1)
2623 #define TX_CMPL_COAL_ERRORS_MASK \
2625 #define TX_CMPL_COAL_ERRORS_SFT 1
2627 * This error indicates that there was some sort of problem
2628 * with the BDs for the packet.
2630 #define TX_CMPL_COAL_ERRORS_BUFFER_ERROR_MASK UINT32_C(0xe)
2631 #define TX_CMPL_COAL_ERRORS_BUFFER_ERROR_SFT 1
2633 #define TX_CMPL_COAL_ERRORS_BUFFER_ERROR_NO_ERROR \
2634 (UINT32_C(0x0) << 1)
2637 * BDs were not formatted correctly.
2639 #define TX_CMPL_COAL_ERRORS_BUFFER_ERROR_BAD_FMT \
2640 (UINT32_C(0x2) << 1)
2641 #define TX_CMPL_COAL_ERRORS_BUFFER_ERROR_LAST \
2642 TX_CMPL_COAL_ERRORS_BUFFER_ERROR_BAD_FMT
2644 * When this bit is '1', it indicates that the length of
2645 * the packet was zero. No packet was transmitted.
2647 #define TX_CMPL_COAL_ERRORS_ZERO_LENGTH_PKT UINT32_C(0x10)
2649 * When this bit is '1', it indicates that the packet
2650 * was longer than the programmed limit in TDI. No
2651 * packet was transmitted.
2653 #define TX_CMPL_COAL_ERRORS_EXCESSIVE_BD_LENGTH UINT32_C(0x20)
2655 * When this bit is '1', it indicates that one or more of the
2656 * BDs associated with this packet generated a PCI error.
2657 * This probably means the address was not valid.
2659 #define TX_CMPL_COAL_ERRORS_DMA_ERROR UINT32_C(0x40)
2661 * When this bit is '1', it indicates that the packet was longer
2662 * than indicated by the hint. No packet was transmitted.
2664 #define TX_CMPL_COAL_ERRORS_HINT_TOO_SHORT UINT32_C(0x80)
2666 * When this bit is '1', it indicates that the packet was
2667 * dropped due to Poison TLP error on one or more of the
2668 * TLPs in the PXP completion.
2670 #define TX_CMPL_COAL_ERRORS_POISON_TLP_ERROR \
2673 * When this bit is '1', it indicates that the packet was dropped
2674 * due to a transient internal error in TDC. The packet or LSO can
2675 * be retried and may transmit successfully on a subsequent attempt.
2677 #define TX_CMPL_COAL_ERRORS_INTERNAL_ERROR \
2680 * When this bit is '1', it was not possible to collect a a timestamp
2681 * for a PTP completion, in which case the timestamp_hi and
2682 * timestamp_lo fields are invalid. When this bit is '0' for a PTP
2683 * completion, the timestamp_hi and timestamp_lo fields are valid.
2684 * RJRN will copy the value of this bit into the field of the same
2685 * name in all TX completions, regardless of whether such
2686 * completions are PTP completions or other TX completions.
2688 #define TX_CMPL_COAL_ERRORS_TIMESTAMP_INVALID_ERROR \
2690 /* unused2 is 16 b */
2692 uint32_t sq_cons_idx;
2694 * This value is SQ index for the start of the packet following the
2695 * last completed packet.
2697 #define TX_CMPL_COAL_SQ_CONS_IDX_MASK UINT32_C(0xffffff)
2698 #define TX_CMPL_COAL_SQ_CONS_IDX_SFT 0
2701 /* tx_cmpl_ptp (size:128b/16B) */
2702 struct tx_cmpl_ptp {
2703 uint16_t flags_type;
2705 * This field indicates the exact type of the completion.
2706 * By convention, the LSB identifies the length of the
2707 * record in 16B units. Even values indicate 16B
2708 * records. Odd values indicate 32B
2711 #define TX_CMPL_PTP_TYPE_MASK UINT32_C(0x3f)
2712 #define TX_CMPL_PTP_TYPE_SFT 0
2714 * TX L2 PTP completion:
2715 * Completion of TX packet. Length = 32B
2717 #define TX_CMPL_PTP_TYPE_TX_L2_PTP UINT32_C(0x2)
2718 #define TX_CMPL_PTP_TYPE_LAST TX_CMPL_PTP_TYPE_TX_L2_PTP
2719 #define TX_CMPL_PTP_FLAGS_MASK UINT32_C(0xffc0)
2720 #define TX_CMPL_PTP_FLAGS_SFT 6
2722 * When this bit is '1', it indicates a packet that has an
2723 * error of some type. Type of error is indicated in
2726 #define TX_CMPL_PTP_FLAGS_ERROR UINT32_C(0x40)
2728 * When this bit is '1', it indicates that the packet completed
2729 * was transmitted using the push acceleration data provided
2730 * by the driver. When this bit is '0', it indicates that the
2731 * packet had not push acceleration data written or was executed
2732 * as a normal packet even though push data was provided.
2734 #define TX_CMPL_PTP_FLAGS_PUSH UINT32_C(0x80)
2735 /* unused1 is 16 b */
2738 * This is a copy of the opaque field from the first TX BD of this
2739 * transmitted packet. Note that, if the packet was described by a short
2740 * CSO or short CSO inline BD, then the 16-bit opaque field from the
2741 * short CSO BD will appear in the bottom 16 bits of this field.
2746 * This value is written by the NIC such that it will be different
2747 * for each pass through the completion queue. The even passes
2748 * will write 1. The odd passes will write 0.
2750 #define TX_CMPL_PTP_V UINT32_C(0x1)
2751 #define TX_CMPL_PTP_ERRORS_MASK UINT32_C(0xfffe)
2752 #define TX_CMPL_PTP_ERRORS_SFT 1
2754 * This error indicates that there was some sort of problem
2755 * with the BDs for the packet.
2757 #define TX_CMPL_PTP_ERRORS_BUFFER_ERROR_MASK UINT32_C(0xe)
2758 #define TX_CMPL_PTP_ERRORS_BUFFER_ERROR_SFT 1
2760 #define TX_CMPL_PTP_ERRORS_BUFFER_ERROR_NO_ERROR \
2761 (UINT32_C(0x0) << 1)
2764 * BDs were not formatted correctly.
2766 #define TX_CMPL_PTP_ERRORS_BUFFER_ERROR_BAD_FMT \
2767 (UINT32_C(0x2) << 1)
2768 #define TX_CMPL_PTP_ERRORS_BUFFER_ERROR_LAST \
2769 TX_CMPL_PTP_ERRORS_BUFFER_ERROR_BAD_FMT
2771 * When this bit is '1', it indicates that the length of
2772 * the packet was zero. No packet was transmitted.
2774 #define TX_CMPL_PTP_ERRORS_ZERO_LENGTH_PKT UINT32_C(0x10)
2776 * When this bit is '1', it indicates that the packet
2777 * was longer than the programmed limit in TDI. No
2778 * packet was transmitted.
2780 #define TX_CMPL_PTP_ERRORS_EXCESSIVE_BD_LENGTH UINT32_C(0x20)
2782 * When this bit is '1', it indicates that one or more of the
2783 * BDs associated with this packet generated a PCI error.
2784 * This probably means the address was not valid.
2786 #define TX_CMPL_PTP_ERRORS_DMA_ERROR UINT32_C(0x40)
2788 * When this bit is '1', it indicates that the packet was longer
2789 * than indicated by the hint. No packet was transmitted.
2791 #define TX_CMPL_PTP_ERRORS_HINT_TOO_SHORT UINT32_C(0x80)
2793 * When this bit is '1', it indicates that the packet was
2794 * dropped due to Poison TLP error on one or more of the
2795 * TLPs in the PXP completion.
2797 #define TX_CMPL_PTP_ERRORS_POISON_TLP_ERROR UINT32_C(0x100)
2799 * When this bit is '1', it indicates that the packet was dropped due
2800 * to a transient internal error in TDC. The packet or LSO can be
2801 * retried and may transmit successfully on a subsequent attempt.
2803 #define TX_CMPL_PTP_ERRORS_INTERNAL_ERROR UINT32_C(0x200)
2805 * When this bit is '1', it was not possible to collect a a timestamp
2806 * for a PTP completion, in which case the timestamp_hi and
2807 * timestamp_lo fields are invalid. When this bit is '0' for a PTP
2808 * completion, the timestamp_hi and timestamp_lo fields are valid.
2809 * RJRN will copy the value of this bit into the field of the same
2810 * name in all TX completions, regardless of whether such
2811 * completions are PTP completions or other TX completions.
2813 #define TX_CMPL_PTP_ERRORS_TIMESTAMP_INVALID_ERROR UINT32_C(0x400)
2814 /* unused2 is 16 b */
2817 * This is timestamp value (lower 32bits) read from PM for the PTP
2818 * timestamp enabled packet.
2820 uint32_t timestamp_lo;
2823 /* tx_cmpl_ptp_hi (size:128b/16B) */
2824 struct tx_cmpl_ptp_hi {
2826 * This is timestamp value (lower 32bits) read from PM for the PTP
2827 * timestamp enabled packet.
2829 uint16_t timestamp_hi[3];
2830 uint16_t reserved16;
2833 * This value is written by the NIC such that it will be different for
2834 * each pass through the completion queue.The even passes will write 1.
2835 * The odd passes will write 0
2837 #define TX_CMPL_PTP_HI_V2 UINT32_C(0x1)
2840 /* rx_pkt_cmpl (size:128b/16B) */
2841 struct rx_pkt_cmpl {
2842 uint16_t flags_type;
2844 * This field indicates the exact type of the completion.
2845 * By convention, the LSB identifies the length of the
2846 * record in 16B units. Even values indicate 16B
2847 * records. Odd values indicate 32B
2850 #define RX_PKT_CMPL_TYPE_MASK UINT32_C(0x3f)
2851 #define RX_PKT_CMPL_TYPE_SFT 0
2854 * Completion of and L2 RX packet. Length = 32B
2856 #define RX_PKT_CMPL_TYPE_RX_L2 UINT32_C(0x11)
2857 #define RX_PKT_CMPL_TYPE_LAST RX_PKT_CMPL_TYPE_RX_L2
2858 #define RX_PKT_CMPL_FLAGS_MASK UINT32_C(0xffc0)
2859 #define RX_PKT_CMPL_FLAGS_SFT 6
2861 * When this bit is '1', it indicates a packet that has an
2862 * error of some type. Type of error is indicated in
2865 #define RX_PKT_CMPL_FLAGS_ERROR UINT32_C(0x40)
2866 /* This field indicates how the packet was placed in the buffer. */
2867 #define RX_PKT_CMPL_FLAGS_PLACEMENT_MASK UINT32_C(0x380)
2868 #define RX_PKT_CMPL_FLAGS_PLACEMENT_SFT 7
2871 * Packet was placed using normal algorithm.
2873 #define RX_PKT_CMPL_FLAGS_PLACEMENT_NORMAL (UINT32_C(0x0) << 7)
2876 * Packet was placed using jumbo algorithm.
2878 #define RX_PKT_CMPL_FLAGS_PLACEMENT_JUMBO (UINT32_C(0x1) << 7)
2880 * Header/Data Separation:
2881 * Packet was placed using Header/Data separation algorithm.
2882 * The separation location is indicated by the itype field.
2884 #define RX_PKT_CMPL_FLAGS_PLACEMENT_HDS (UINT32_C(0x2) << 7)
2885 #define RX_PKT_CMPL_FLAGS_PLACEMENT_LAST \
2886 RX_PKT_CMPL_FLAGS_PLACEMENT_HDS
2887 /* This bit is '1' if the RSS field in this completion is valid. */
2888 #define RX_PKT_CMPL_FLAGS_RSS_VALID UINT32_C(0x400)
2890 #define RX_PKT_CMPL_FLAGS_UNUSED UINT32_C(0x800)
2892 * This value indicates what the inner packet determined for the
2895 #define RX_PKT_CMPL_FLAGS_ITYPE_MASK UINT32_C(0xf000)
2896 #define RX_PKT_CMPL_FLAGS_ITYPE_SFT 12
2899 * Indicates that the packet type was not known.
2901 #define RX_PKT_CMPL_FLAGS_ITYPE_NOT_KNOWN \
2902 (UINT32_C(0x0) << 12)
2905 * Indicates that the packet was an IP packet, but further
2906 * classification was not possible.
2908 #define RX_PKT_CMPL_FLAGS_ITYPE_IP \
2909 (UINT32_C(0x1) << 12)
2912 * Indicates that the packet was IP and TCP.
2913 * This indicates that the payload_offset field is valid.
2915 #define RX_PKT_CMPL_FLAGS_ITYPE_TCP \
2916 (UINT32_C(0x2) << 12)
2919 * Indicates that the packet was IP and UDP.
2920 * This indicates that the payload_offset field is valid.
2922 #define RX_PKT_CMPL_FLAGS_ITYPE_UDP \
2923 (UINT32_C(0x3) << 12)
2926 * Indicates that the packet was recognized as a FCoE.
2927 * This also indicates that the payload_offset field is valid.
2929 #define RX_PKT_CMPL_FLAGS_ITYPE_FCOE \
2930 (UINT32_C(0x4) << 12)
2933 * Indicates that the packet was recognized as a RoCE.
2934 * This also indicates that the payload_offset field is valid.
2936 #define RX_PKT_CMPL_FLAGS_ITYPE_ROCE \
2937 (UINT32_C(0x5) << 12)
2940 * Indicates that the packet was recognized as ICMP.
2941 * This indicates that the payload_offset field is valid.
2943 #define RX_PKT_CMPL_FLAGS_ITYPE_ICMP \
2944 (UINT32_C(0x7) << 12)
2946 * PtP packet wo/timestamp:
2947 * Indicates that the packet was recognized as a PtP
2950 #define RX_PKT_CMPL_FLAGS_ITYPE_PTP_WO_TIMESTAMP \
2951 (UINT32_C(0x8) << 12)
2953 * PtP packet w/timestamp:
2954 * Indicates that the packet was recognized as a PtP
2955 * packet and that a timestamp was taken for the packet.
2957 #define RX_PKT_CMPL_FLAGS_ITYPE_PTP_W_TIMESTAMP \
2958 (UINT32_C(0x9) << 12)
2959 #define RX_PKT_CMPL_FLAGS_ITYPE_LAST \
2960 RX_PKT_CMPL_FLAGS_ITYPE_PTP_W_TIMESTAMP
2962 * This is the length of the data for the packet stored in the
2963 * buffer(s) identified by the opaque value. This includes
2964 * the packet BD and any associated buffer BDs. This does not include
2965 * the length of any data places in aggregation BDs.
2969 * This is a copy of the opaque field from the RX BD this completion
2973 uint8_t agg_bufs_v1;
2975 * This value is written by the NIC such that it will be different
2976 * for each pass through the completion queue. The even passes
2977 * will write 1. The odd passes will write 0.
2979 #define RX_PKT_CMPL_V1 UINT32_C(0x1)
2981 * This value is the number of aggregation buffers that follow this
2982 * entry in the completion ring that are a part of this packet.
2983 * If the value is zero, then the packet is completely contained
2984 * in the buffer space provided for the packet in the RX ring.
2986 #define RX_PKT_CMPL_AGG_BUFS_MASK UINT32_C(0x3e)
2987 #define RX_PKT_CMPL_AGG_BUFS_SFT 1
2988 /* unused1 is 2 b */
2989 #define RX_PKT_CMPL_UNUSED1_MASK UINT32_C(0xc0)
2990 #define RX_PKT_CMPL_UNUSED1_SFT 6
2992 * This is the RSS hash type for the packet. The value is packed
2993 * {tuple_extrac_op[1:0],rss_profile_id[4:0],tuple_extrac_op[2]}.
2995 * The value of tuple_extrac_op provides the information about
2996 * what fields the hash was computed on.
2997 * * 0: The RSS hash was computed over source IP address,
2998 * destination IP address, source port, and destination port of inner
2999 * IP and TCP or UDP headers. Note: For non-tunneled packets,
3000 * the packet headers are considered inner packet headers for the RSS
3001 * hash computation purpose.
3002 * * 1: The RSS hash was computed over source IP address and destination
3003 * IP address of inner IP header. Note: For non-tunneled packets,
3004 * the packet headers are considered inner packet headers for the RSS
3005 * hash computation purpose.
3006 * * 2: The RSS hash was computed over source IP address,
3007 * destination IP address, source port, and destination port of
3008 * IP and TCP or UDP headers of outer tunnel headers.
3009 * Note: For non-tunneled packets, this value is not applicable.
3010 * * 3: The RSS hash was computed over source IP address and
3011 * destination IP address of IP header of outer tunnel headers.
3012 * Note: For non-tunneled packets, this value is not applicable.
3014 * Note that 4-tuples values listed above are applicable
3015 * for layer 4 protocols supported and enabled for RSS in the hardware,
3016 * HWRM firmware, and drivers. For example, if RSS hash is supported and
3017 * enabled for TCP traffic only, then the values of tuple_extract_op
3018 * corresponding to 4-tuples are only valid for TCP traffic.
3020 uint8_t rss_hash_type;
3022 * This value indicates the offset in bytes from the beginning of the packet
3023 * where the inner payload starts. This value is valid for TCP, UDP,
3024 * FCoE, and RoCE packets.
3026 * A value of zero indicates that header is 256B into the packet.
3028 uint8_t payload_offset;
3029 /* unused2 is 8 b */
3032 * This value is the RSS hash value calculated for the packet
3033 * based on the mode bits and key value in the VNIC.
3038 /* Last 16 bytes of rx_pkt_cmpl. */
3039 /* rx_pkt_cmpl_hi (size:128b/16B) */
3040 struct rx_pkt_cmpl_hi {
3043 * This indicates that the ip checksum was calculated for the
3044 * inner packet and that the ip_cs_error field indicates if there
3047 #define RX_PKT_CMPL_FLAGS2_IP_CS_CALC UINT32_C(0x1)
3049 * This indicates that the TCP, UDP or ICMP checksum was
3050 * calculated for the inner packet and that the l4_cs_error field
3051 * indicates if there was an error.
3053 #define RX_PKT_CMPL_FLAGS2_L4_CS_CALC UINT32_C(0x2)
3055 * This indicates that the ip checksum was calculated for the
3056 * tunnel header and that the t_ip_cs_error field indicates if there
3059 #define RX_PKT_CMPL_FLAGS2_T_IP_CS_CALC UINT32_C(0x4)
3061 * This indicates that the UDP checksum was
3062 * calculated for the tunnel packet and that the t_l4_cs_error field
3063 * indicates if there was an error.
3065 #define RX_PKT_CMPL_FLAGS2_T_L4_CS_CALC UINT32_C(0x8)
3066 /* This value indicates what format the metadata field is. */
3067 #define RX_PKT_CMPL_FLAGS2_META_FORMAT_MASK UINT32_C(0xf0)
3068 #define RX_PKT_CMPL_FLAGS2_META_FORMAT_SFT 4
3069 /* No metadata information. Value is zero. */
3070 #define RX_PKT_CMPL_FLAGS2_META_FORMAT_NONE \
3071 (UINT32_C(0x0) << 4)
3073 * The metadata field contains the VLAN tag and TPID value.
3074 * - metadata[11:0] contains the vlan VID value.
3075 * - metadata[12] contains the vlan DE value.
3076 * - metadata[15:13] contains the vlan PRI value.
3077 * - metadata[31:16] contains the vlan TPID value.
3079 #define RX_PKT_CMPL_FLAGS2_META_FORMAT_VLAN \
3080 (UINT32_C(0x1) << 4)
3082 * If ext_meta_format is equal to 1, the metadata field
3083 * contains the lower 16b of the tunnel ID value, justified
3085 * - VXLAN = VNI[23:0] -> VXLAN Network ID
3086 * - Geneve (NGE) = VNI[23:0] a-> Virtual Network Identifier.
3087 * - NVGRE = TNI[23:0] -> Tenant Network ID
3088 * - GRE = KEY[31:0] -> key field with bit mask. zero if K = 0
3089 * - IPV4 = 0 (not populated)
3090 * - IPV6 = Flow Label[19:0]
3091 * - PPPoE = sessionID[15:0]
3092 * - MPLs = Outer label[19:0]
3093 * - UPAR = Selected[31:0] with bit mask
3095 #define RX_PKT_CMPL_FLAGS2_META_FORMAT_TUNNEL_ID \
3096 (UINT32_C(0x2) << 4)
3098 * if ext_meta_format is equal to 1, metadata field contains
3099 * 16b metadata from the prepended header (chdr_data).
3101 #define RX_PKT_CMPL_FLAGS2_META_FORMAT_CHDR_DATA \
3102 (UINT32_C(0x3) << 4)
3104 * If ext_meta_format is equal to 1, the metadata field contains
3105 * the outer_l3_offset, inner_l2_offset, inner_l3_offset and
3107 * - metadata[8:0] contains the outer_l3_offset.
3108 * - metadata[17:9] contains the inner_l2_offset.
3109 * - metadata[26:18] contains the inner_l3_offset.
3110 * - metadata[31:27] contains the inner_l4_size.
3112 #define RX_PKT_CMPL_FLAGS2_META_FORMAT_HDR_OFFSET \
3113 (UINT32_C(0x4) << 4)
3114 #define RX_PKT_CMPL_FLAGS2_META_FORMAT_LAST \
3115 RX_PKT_CMPL_FLAGS2_META_FORMAT_HDR_OFFSET
3117 * This field indicates the IP type for the inner-most IP header.
3118 * A value of '0' indicates IPv4. A value of '1' indicates IPv6.
3119 * This value is only valid if itype indicates a packet
3120 * with an IP header.
3122 #define RX_PKT_CMPL_FLAGS2_IP_TYPE UINT32_C(0x100)
3124 * This indicates that the complete 1's complement checksum was
3125 * calculated for the packet.
3127 #define RX_PKT_CMPL_FLAGS2_COMPLETE_CHECKSUM_CALC UINT32_C(0x200)
3129 * The combination of this value and meta_format indicated what
3130 * format the metadata field is.
3132 #define RX_PKT_CMPL_FLAGS2_EXT_META_FORMAT_MASK UINT32_C(0xc00)
3133 #define RX_PKT_CMPL_FLAGS2_EXT_META_FORMAT_SFT 10
3135 * This value is the complete 1's complement checksum calculated from
3136 * the start of the outer L3 header to the end of the packet (not
3137 * including the ethernet crc). It is valid when the
3138 * 'complete_checksum_calc' flag is set.
3140 #define RX_PKT_CMPL_FLAGS2_COMPLETE_CHECKSUM_MASK \
3141 UINT32_C(0xffff0000)
3142 #define RX_PKT_CMPL_FLAGS2_COMPLETE_CHECKSUM_SFT 16
3144 * This is data from the CFA block as indicated by the meta_format
3148 /* When meta_format=1, this value is the VLAN VID. */
3149 #define RX_PKT_CMPL_METADATA_VID_MASK UINT32_C(0xfff)
3150 #define RX_PKT_CMPL_METADATA_VID_SFT 0
3151 /* When meta_format=1, this value is the VLAN DE. */
3152 #define RX_PKT_CMPL_METADATA_DE UINT32_C(0x1000)
3153 /* When meta_format=1, this value is the VLAN PRI. */
3154 #define RX_PKT_CMPL_METADATA_PRI_MASK UINT32_C(0xe000)
3155 #define RX_PKT_CMPL_METADATA_PRI_SFT 13
3156 /* When meta_format=1, this value is the VLAN TPID. */
3157 #define RX_PKT_CMPL_METADATA_TPID_MASK UINT32_C(0xffff0000)
3158 #define RX_PKT_CMPL_METADATA_TPID_SFT 16
3161 * This value is written by the NIC such that it will be different
3162 * for each pass through the completion queue. The even passes
3163 * will write 1. The odd passes will write 0.
3165 #define RX_PKT_CMPL_V2 \
3167 #define RX_PKT_CMPL_ERRORS_MASK \
3169 #define RX_PKT_CMPL_ERRORS_SFT 1
3171 * This error indicates that there was some sort of problem with
3172 * the BDs for the packet that was found after part of the
3173 * packet was already placed. The packet should be treated as
3176 #define RX_PKT_CMPL_ERRORS_BUFFER_ERROR_MASK \
3178 #define RX_PKT_CMPL_ERRORS_BUFFER_ERROR_SFT 1
3179 /* No buffer error */
3180 #define RX_PKT_CMPL_ERRORS_BUFFER_ERROR_NO_BUFFER \
3181 (UINT32_C(0x0) << 1)
3184 * Packet did not fit into packet buffer provided.
3185 * For regular placement, this means the packet did not fit
3186 * in the buffer provided. For HDS and jumbo placement, this
3187 * means that the packet could not be placed into 7 physical
3190 #define RX_PKT_CMPL_ERRORS_BUFFER_ERROR_DID_NOT_FIT \
3191 (UINT32_C(0x1) << 1)
3194 * All BDs needed for the packet were not on-chip when
3195 * the packet arrived.
3197 #define RX_PKT_CMPL_ERRORS_BUFFER_ERROR_NOT_ON_CHIP \
3198 (UINT32_C(0x2) << 1)
3201 * BDs were not formatted correctly.
3203 #define RX_PKT_CMPL_ERRORS_BUFFER_ERROR_BAD_FORMAT \
3204 (UINT32_C(0x3) << 1)
3207 * There was a bad_format error on the previous operation
3209 #define RX_PKT_CMPL_ERRORS_BUFFER_ERROR_FLUSH \
3210 (UINT32_C(0x5) << 1)
3211 #define RX_PKT_CMPL_ERRORS_BUFFER_ERROR_LAST \
3212 RX_PKT_CMPL_ERRORS_BUFFER_ERROR_FLUSH
3214 * This indicates that there was an error in the IP header
3217 #define RX_PKT_CMPL_ERRORS_IP_CS_ERROR \
3220 * This indicates that there was an error in the TCP, UDP
3223 #define RX_PKT_CMPL_ERRORS_L4_CS_ERROR \
3226 * This indicates that there was an error in the tunnel
3227 * IP header checksum.
3229 #define RX_PKT_CMPL_ERRORS_T_IP_CS_ERROR \
3232 * This indicates that there was an error in the tunnel
3235 #define RX_PKT_CMPL_ERRORS_T_L4_CS_ERROR \
3238 * This indicates that there was a CRC error on either an FCoE
3239 * or RoCE packet. The itype indicates the packet type.
3241 #define RX_PKT_CMPL_ERRORS_CRC_ERROR \
3244 * This indicates that there was an error in the tunnel
3245 * portion of the packet when this
3246 * field is non-zero.
3248 #define RX_PKT_CMPL_ERRORS_T_PKT_ERROR_MASK \
3250 #define RX_PKT_CMPL_ERRORS_T_PKT_ERROR_SFT 9
3252 * No additional error occurred on the tunnel portion
3253 * or the packet of the packet does not have a tunnel.
3255 #define RX_PKT_CMPL_ERRORS_T_PKT_ERROR_NO_ERROR \
3256 (UINT32_C(0x0) << 9)
3258 * Indicates that IP header version does not match
3259 * expectation from L2 Ethertype for IPv4 and IPv6
3260 * in the tunnel header.
3262 #define RX_PKT_CMPL_ERRORS_T_PKT_ERROR_T_L3_BAD_VERSION \
3263 (UINT32_C(0x1) << 9)
3265 * Indicates that header length is out of range in the
3266 * tunnel header. Valid for
3269 #define RX_PKT_CMPL_ERRORS_T_PKT_ERROR_T_L3_BAD_HDR_LEN \
3270 (UINT32_C(0x2) << 9)
3272 * Indicates that the physical packet is shorter than that
3273 * claimed by the PPPoE header length for a tunnel PPPoE
3276 #define RX_PKT_CMPL_ERRORS_T_PKT_ERROR_TUNNEL_TOTAL_ERROR \
3277 (UINT32_C(0x3) << 9)
3279 * Indicates that physical packet is shorter than that claimed
3280 * by the tunnel l3 header length. Valid for IPv4, or IPv6
3281 * tunnel packet packets.
3283 #define RX_PKT_CMPL_ERRORS_T_PKT_ERROR_T_IP_TOTAL_ERROR \
3284 (UINT32_C(0x4) << 9)
3286 * Indicates that the physical packet is shorter than that
3287 * claimed by the tunnel UDP header length for a tunnel
3288 * UDP packet that is not fragmented.
3290 #define RX_PKT_CMPL_ERRORS_T_PKT_ERROR_T_UDP_TOTAL_ERROR \
3291 (UINT32_C(0x5) << 9)
3293 * indicates that the IPv4 TTL or IPv6 hop limit check
3294 * have failed (e.g. TTL = 0) in the tunnel header. Valid
3295 * for IPv4, and IPv6.
3297 #define RX_PKT_CMPL_ERRORS_T_PKT_ERROR_T_L3_BAD_TTL \
3298 (UINT32_C(0x6) << 9)
3299 #define RX_PKT_CMPL_ERRORS_T_PKT_ERROR_LAST \
3300 RX_PKT_CMPL_ERRORS_T_PKT_ERROR_T_L3_BAD_TTL
3302 * This indicates that there was an error in the inner
3303 * portion of the packet when this
3304 * field is non-zero.
3306 #define RX_PKT_CMPL_ERRORS_PKT_ERROR_MASK \
3308 #define RX_PKT_CMPL_ERRORS_PKT_ERROR_SFT 12
3310 * No additional error occurred on the tunnel portion
3311 * or the packet of the packet does not have a tunnel.
3313 #define RX_PKT_CMPL_ERRORS_PKT_ERROR_NO_ERROR \
3314 (UINT32_C(0x0) << 12)
3316 * Indicates that IP header version does not match
3317 * expectation from L2 Ethertype for IPv4 and IPv6 or that
3318 * option other than VFT was parsed on
3321 #define RX_PKT_CMPL_ERRORS_PKT_ERROR_L3_BAD_VERSION \
3322 (UINT32_C(0x1) << 12)
3324 * indicates that header length is out of range. Valid for
3327 #define RX_PKT_CMPL_ERRORS_PKT_ERROR_L3_BAD_HDR_LEN \
3328 (UINT32_C(0x2) << 12)
3330 * indicates that the IPv4 TTL or IPv6 hop limit check
3331 * have failed (e.g. TTL = 0). Valid for IPv4, and IPv6
3333 #define RX_PKT_CMPL_ERRORS_PKT_ERROR_L3_BAD_TTL \
3334 (UINT32_C(0x3) << 12)
3336 * Indicates that physical packet is shorter than that
3337 * claimed by the l3 header length. Valid for IPv4,
3338 * IPv6 packet or RoCE packets.
3340 #define RX_PKT_CMPL_ERRORS_PKT_ERROR_IP_TOTAL_ERROR \
3341 (UINT32_C(0x4) << 12)
3343 * Indicates that the physical packet is shorter than that
3344 * claimed by the UDP header length for a UDP packet that is
3347 #define RX_PKT_CMPL_ERRORS_PKT_ERROR_UDP_TOTAL_ERROR \
3348 (UINT32_C(0x5) << 12)
3350 * Indicates that TCP header length > IP payload. Valid for
3353 #define RX_PKT_CMPL_ERRORS_PKT_ERROR_L4_BAD_HDR_LEN \
3354 (UINT32_C(0x6) << 12)
3355 /* Indicates that TCP header length < 5. Valid for TCP. */
3356 #define RX_PKT_CMPL_ERRORS_PKT_ERROR_L4_BAD_HDR_LEN_TOO_SMALL \
3357 (UINT32_C(0x7) << 12)
3359 * Indicates that TCP option headers result in a TCP header
3360 * size that does not match data offset in TCP header. Valid
3363 #define RX_PKT_CMPL_ERRORS_PKT_ERROR_L4_BAD_OPT_LEN \
3364 (UINT32_C(0x8) << 12)
3365 #define RX_PKT_CMPL_ERRORS_PKT_ERROR_LAST \
3366 RX_PKT_CMPL_ERRORS_PKT_ERROR_L4_BAD_OPT_LEN
3368 * This field identifies the CFA action rule that was used for this
3374 * This value holds the reordering sequence number for the packet.
3375 * If the reordering sequence is not valid, then this value is zero.
3376 * The reordering domain for the packet is in the bottom 8 to 10b of
3377 * the rss_hash value. The bottom 20b of this value contain the
3378 * ordering domain value for the packet.
3380 #define RX_PKT_CMPL_REORDER_MASK UINT32_C(0xffffff)
3381 #define RX_PKT_CMPL_REORDER_SFT 0
3384 /* rx_pkt_v2_cmpl (size:128b/16B) */
3385 struct rx_pkt_v2_cmpl {
3386 uint16_t flags_type;
3388 * This field indicates the exact type of the completion.
3389 * By convention, the LSB identifies the length of the
3390 * record in 16B units. Even values indicate 16B
3391 * records. Odd values indicate 32B
3394 #define RX_PKT_V2_CMPL_TYPE_MASK UINT32_C(0x3f)
3395 #define RX_PKT_V2_CMPL_TYPE_SFT 0
3397 * RX L2 V2 completion:
3398 * Completion of and L2 RX packet. Length = 32B
3399 * This is the new version of the RX_L2 completion used in SR2
3402 #define RX_PKT_V2_CMPL_TYPE_RX_L2_V2 UINT32_C(0xf)
3403 #define RX_PKT_V2_CMPL_TYPE_LAST \
3404 RX_PKT_V2_CMPL_TYPE_RX_L2_V2
3405 #define RX_PKT_V2_CMPL_FLAGS_MASK UINT32_C(0xffc0)
3406 #define RX_PKT_V2_CMPL_FLAGS_SFT 6
3408 * When this bit is '1', it indicates a packet that has an
3409 * error of some type. Type of error is indicated in
3412 #define RX_PKT_V2_CMPL_FLAGS_ERROR UINT32_C(0x40)
3413 /* This field indicates how the packet was placed in the buffer. */
3414 #define RX_PKT_V2_CMPL_FLAGS_PLACEMENT_MASK UINT32_C(0x380)
3415 #define RX_PKT_V2_CMPL_FLAGS_PLACEMENT_SFT 7
3418 * Packet was placed using normal algorithm.
3420 #define RX_PKT_V2_CMPL_FLAGS_PLACEMENT_NORMAL \
3421 (UINT32_C(0x0) << 7)
3424 * Packet was placed using jumbo algorithm.
3426 #define RX_PKT_V2_CMPL_FLAGS_PLACEMENT_JUMBO \
3427 (UINT32_C(0x1) << 7)
3429 * Header/Data Separation:
3430 * Packet was placed using Header/Data separation algorithm.
3431 * The separation location is indicated by the itype field.
3433 #define RX_PKT_V2_CMPL_FLAGS_PLACEMENT_HDS \
3434 (UINT32_C(0x2) << 7)
3437 * Packet was placed using truncation algorithm. The
3438 * placed (truncated) length is indicated in the payload_offset
3439 * field. The original length is indicated in the len field.
3441 #define RX_PKT_V2_CMPL_FLAGS_PLACEMENT_TRUNCATION \
3442 (UINT32_C(0x3) << 7)
3443 #define RX_PKT_V2_CMPL_FLAGS_PLACEMENT_LAST \
3444 RX_PKT_V2_CMPL_FLAGS_PLACEMENT_TRUNCATION
3445 /* This bit is '1' if the RSS field in this completion is valid. */
3446 #define RX_PKT_V2_CMPL_FLAGS_RSS_VALID UINT32_C(0x400)
3448 * This bit is '1' if metadata has been added to the end of the
3449 * packet in host memory. Metadata starts at the first 32B boundary
3450 * after the end of the packet for regular and jumbo placement.
3451 * It starts at the first 32B boundary after the end of the header
3452 * for HDS placement. The length of the metadata is indicated in the
3455 #define RX_PKT_V2_CMPL_FLAGS_PKT_METADATA_PRESENT UINT32_C(0x800)
3457 * This value indicates what the inner packet determined for the
3460 #define RX_PKT_V2_CMPL_FLAGS_ITYPE_MASK UINT32_C(0xf000)
3461 #define RX_PKT_V2_CMPL_FLAGS_ITYPE_SFT 12
3464 * Indicates that the packet type was not known.
3466 #define RX_PKT_V2_CMPL_FLAGS_ITYPE_NOT_KNOWN \
3467 (UINT32_C(0x0) << 12)
3470 * Indicates that the packet was an IP packet, but further
3471 * classification was not possible.
3473 #define RX_PKT_V2_CMPL_FLAGS_ITYPE_IP \
3474 (UINT32_C(0x1) << 12)
3477 * Indicates that the packet was IP and TCP.
3478 * This indicates that the payload_offset field is valid.
3480 #define RX_PKT_V2_CMPL_FLAGS_ITYPE_TCP \
3481 (UINT32_C(0x2) << 12)
3484 * Indicates that the packet was IP and UDP.
3485 * This indicates that the payload_offset field is valid.
3487 #define RX_PKT_V2_CMPL_FLAGS_ITYPE_UDP \
3488 (UINT32_C(0x3) << 12)
3491 * Indicates that the packet was recognized as a FCoE.
3492 * This also indicates that the payload_offset field is valid.
3494 #define RX_PKT_V2_CMPL_FLAGS_ITYPE_FCOE \
3495 (UINT32_C(0x4) << 12)
3498 * Indicates that the packet was recognized as a RoCE.
3499 * This also indicates that the payload_offset field is valid.
3501 #define RX_PKT_V2_CMPL_FLAGS_ITYPE_ROCE \
3502 (UINT32_C(0x5) << 12)
3505 * Indicates that the packet was recognized as ICMP.
3506 * This indicates that the payload_offset field is valid.
3508 #define RX_PKT_V2_CMPL_FLAGS_ITYPE_ICMP \
3509 (UINT32_C(0x7) << 12)
3511 * PtP packet wo/timestamp:
3512 * Indicates that the packet was recognized as a PtP
3515 #define RX_PKT_V2_CMPL_FLAGS_ITYPE_PTP_WO_TIMESTAMP \
3516 (UINT32_C(0x8) << 12)
3518 * PtP packet w/timestamp:
3519 * Indicates that the packet was recognized as a PtP
3520 * packet and that a timestamp was taken for the packet.
3522 #define RX_PKT_V2_CMPL_FLAGS_ITYPE_PTP_W_TIMESTAMP \
3523 (UINT32_C(0x9) << 12)
3524 #define RX_PKT_V2_CMPL_FLAGS_ITYPE_LAST \
3525 RX_PKT_V2_CMPL_FLAGS_ITYPE_PTP_W_TIMESTAMP
3527 * This is the length of the data for the packet stored in the
3528 * buffer(s) identified by the opaque value. This includes
3529 * the packet BD and any associated buffer BDs. This does not include
3530 * the length of any data places in aggregation BDs.
3534 * This is a copy of the opaque field from the RX BD this completion
3538 uint8_t agg_bufs_v1;
3540 * This value is written by the NIC such that it will be different
3541 * for each pass through the completion queue. The even passes
3542 * will write 1. The odd passes will write 0.
3544 #define RX_PKT_V2_CMPL_V1 UINT32_C(0x1)
3546 * This value is the number of aggregation buffers that follow this
3547 * entry in the completion ring that are a part of this packet.
3548 * If the value is zero, then the packet is completely contained
3549 * in the buffer space provided for the packet in the RX ring.
3551 #define RX_PKT_V2_CMPL_AGG_BUFS_MASK UINT32_C(0x3e)
3552 #define RX_PKT_V2_CMPL_AGG_BUFS_SFT 1
3553 /* unused1 is 2 b */
3554 #define RX_PKT_V2_CMPL_UNUSED1_MASK UINT32_C(0xc0)
3555 #define RX_PKT_V2_CMPL_UNUSED1_SFT 6
3557 * This is the RSS hash type for the packet. The value is packed
3558 * {tuple_extrac_op[1:0],rss_profile_id[4:0],tuple_extrac_op[2]}.
3560 * The value of tuple_extrac_op provides the information about
3561 * what fields the hash was computed on.
3562 * * 0: The RSS hash was computed over source IP address,
3563 * destination IP address, source port, and destination port of inner
3564 * IP and TCP or UDP headers. Note: For non-tunneled packets,
3565 * the packet headers are considered inner packet headers for the RSS
3566 * hash computation purpose.
3567 * * 1: The RSS hash was computed over source IP address and destination
3568 * IP address of inner IP header. Note: For non-tunneled packets,
3569 * the packet headers are considered inner packet headers for the RSS
3570 * hash computation purpose.
3571 * * 2: The RSS hash was computed over source IP address,
3572 * destination IP address, source port, and destination port of
3573 * IP and TCP or UDP headers of outer tunnel headers.
3574 * Note: For non-tunneled packets, this value is not applicable.
3575 * * 3: The RSS hash was computed over source IP address and
3576 * destination IP address of IP header of outer tunnel headers.
3577 * Note: For non-tunneled packets, this value is not applicable.
3579 * Note that 4-tuples values listed above are applicable
3580 * for layer 4 protocols supported and enabled for RSS in the hardware,
3581 * HWRM firmware, and drivers. For example, if RSS hash is supported and
3582 * enabled for TCP traffic only, then the values of tuple_extract_op
3583 * corresponding to 4-tuples are only valid for TCP traffic.
3585 uint8_t rss_hash_type;
3586 uint16_t metadata1_payload_offset;
3588 * This is data from the CFA as indicated by the meta_format field.
3589 * If truncation placement is not used, this value indicates the offset
3590 * in bytes from the beginning of the packet where the inner payload
3591 * starts. This value is valid for TCP, UDP, FCoE, and RoCE packets. If
3592 * truncation placement is used, this value represents the placed
3593 * (truncated) length of the packet.
3595 #define RX_PKT_V2_CMPL_PAYLOAD_OFFSET_MASK UINT32_C(0x1ff)
3596 #define RX_PKT_V2_CMPL_PAYLOAD_OFFSET_SFT 0
3597 /* This is data from the CFA as indicated by the meta_format field. */
3598 #define RX_PKT_V2_CMPL_METADATA1_MASK UINT32_C(0xf000)
3599 #define RX_PKT_V2_CMPL_METADATA1_SFT 12
3600 /* When meta_format != 0, this value is the VLAN TPID_SEL. */
3601 #define RX_PKT_V2_CMPL_METADATA1_TPID_SEL_MASK UINT32_C(0x7000)
3602 #define RX_PKT_V2_CMPL_METADATA1_TPID_SEL_SFT 12
3604 #define RX_PKT_V2_CMPL_METADATA1_TPID_SEL_TPID88A8 \
3605 (UINT32_C(0x0) << 12)
3607 #define RX_PKT_V2_CMPL_METADATA1_TPID_SEL_TPID8100 \
3608 (UINT32_C(0x1) << 12)
3610 #define RX_PKT_V2_CMPL_METADATA1_TPID_SEL_TPID9100 \
3611 (UINT32_C(0x2) << 12)
3613 #define RX_PKT_V2_CMPL_METADATA1_TPID_SEL_TPID9200 \
3614 (UINT32_C(0x3) << 12)
3616 #define RX_PKT_V2_CMPL_METADATA1_TPID_SEL_TPID9300 \
3617 (UINT32_C(0x4) << 12)
3618 /* Value programmed in CFA VLANTPID register. */
3619 #define RX_PKT_V2_CMPL_METADATA1_TPID_SEL_TPIDCFG \
3620 (UINT32_C(0x5) << 12)
3621 #define RX_PKT_V2_CMPL_METADATA1_TPID_SEL_LAST \
3622 RX_PKT_V2_CMPL_METADATA1_TPID_SEL_TPIDCFG
3623 /* When meta_format != 0, this value is the VLAN valid. */
3624 #define RX_PKT_V2_CMPL_METADATA1_VALID UINT32_C(0x8000)
3626 * This value is the RSS hash value calculated for the packet
3627 * based on the mode bits and key value in the VNIC. When vee_cmpl_mode
3628 * is set in VNIC context, this is the lower 32b of the host address
3629 * from the first BD used to place the packet.
3634 /* Last 16 bytes of RX Packet V2 Completion Record */
3635 /* rx_pkt_v2_cmpl_hi (size:128b/16B) */
3636 struct rx_pkt_v2_cmpl_hi {
3639 * When this bit is '0', the cs_ok field has the following definition:-
3640 * ip_cs_ok[2:0] = The number of header groups with a valid IP checksum
3641 * in the delivered packet, counted from the outer-most header group to
3642 * the inner-most header group, stopping at the first error. -
3643 * l4_cs_ok[5:3] = The number of header groups with a valid L4 checksum
3644 * in the delivered packet, counted from the outer-most header group to
3645 * the inner-most header group, stopping at the first error. When this
3646 * bit is '1', the cs_ok field has the following definition: -
3647 * hdr_cnt[2:0] = The number of header groups that were parsed by the
3648 * chip and passed in the delivered packet. - ip_cs_all_ok[3] =This bit
3649 * will be '1' if all the parsed header groups with an IP checksum are
3650 * valid. - l4_cs_all_ok[4] = This bit will be '1' if all the parsed
3651 * header groups with an L4 checksum are valid.
3653 #define RX_PKT_V2_CMPL_HI_FLAGS2_CS_ALL_OK_MODE \
3655 /* This value indicates what format the metadata field is. */
3656 #define RX_PKT_V2_CMPL_HI_FLAGS2_META_FORMAT_MASK \
3658 #define RX_PKT_V2_CMPL_HI_FLAGS2_META_FORMAT_SFT 4
3659 /* There is no metadata information. Values are zero. */
3660 #define RX_PKT_V2_CMPL_HI_FLAGS2_META_FORMAT_NONE \
3661 (UINT32_C(0x0) << 4)
3663 * The {metadata1, metadata0} fields contain the vtag
3664 * information: - vtag[19:0] = {valid, tpid_sel[2:0], pri[2:0],
3665 * de, vid[11:0]} The metadata2 field contains the table scope
3666 * and action record pointer. - metadata2[25:0] contains the
3667 * action record pointer. - metadata2[31:26] contains the table
3670 #define RX_PKT_V2_CMPL_HI_FLAGS2_META_FORMAT_ACT_REC_PTR \
3671 (UINT32_C(0x1) << 4)
3673 * The {metadata1, metadata0} fields contain the vtag
3675 * - vtag[19:0] = {valid, tpid_sel[2:0], pri[2:0], de, vid[11:0]}
3676 * The metadata2 field contains the Tunnel ID
3677 * value, justified to LSB. i
3678 * - VXLAN = VNI[23:0] -> VXLAN Network ID
3679 * - Geneve (NGE) = VNI[23:0] a-> Virtual Network Identifier
3680 * - NVGRE = TNI[23:0] -> Tenant Network ID
3681 * - GRE = KEY[31:0] -> key field with bit mask. zero if K=0
3682 * - IPv4 = 0 (not populated)
3683 * - IPv6 = Flow Label[19:0]
3684 * - PPPoE = sessionID[15:0]
3685 * - MPLs = Outer label[19:0]
3686 * - UPAR = Selected[31:0] with bit mask
3688 #define RX_PKT_V2_CMPL_HI_FLAGS2_META_FORMAT_TUNNEL_ID \
3689 (UINT32_C(0x2) << 4)
3691 * The {metadata1, metadata0} fields contain the vtag
3693 * - vtag[19:0] = {valid, tpid_sel[2:0], pri[2:0],de, vid[11:0]}
3694 * The metadata2 field contains the 32b metadata from the prepended
3695 * header (chdr_data).
3697 #define RX_PKT_V2_CMPL_HI_FLAGS2_META_FORMAT_CHDR_DATA \
3698 (UINT32_C(0x3) << 4)
3700 * The {metadata1, metadata0} fields contain the vtag
3702 * - vtag[19:0] = {valid, tpid_sel[2:0], pri[2:0], de, vid[11:0]}
3703 * The metadata2 field contains the outer_l3_offset,
3704 * inner_l2_offset, inner_l3_offset, and inner_l4_size.
3705 * - metadata2[8:0] contains the outer_l3_offset.
3706 * - metadata2[17:9] contains the inner_l2_offset.
3707 * - metadata2[26:18] contains the inner_l3_offset.
3708 * - metadata2[31:27] contains the inner_l4_size.
3710 #define RX_PKT_V2_CMPL_HI_FLAGS2_META_FORMAT_HDR_OFFSET \
3711 (UINT32_C(0x4) << 4)
3712 #define RX_PKT_V2_CMPL_HI_FLAGS2_META_FORMAT_LAST \
3713 RX_PKT_V2_CMPL_HI_FLAGS2_META_FORMAT_HDR_OFFSET
3715 * This field indicates the IP type for the inner-most IP header.
3716 * A value of '0' indicates IPv4. A value of '1' indicates IPv6.
3717 * This value is only valid if itype indicates a packet
3718 * with an IP header.
3720 #define RX_PKT_V2_CMPL_HI_FLAGS2_IP_TYPE \
3723 * This indicates that the complete 1's complement checksum was
3724 * calculated for the packet.
3726 #define RX_PKT_V2_CMPL_HI_FLAGS2_COMPLETE_CHECKSUM_CALC \
3729 * This field indicates the status of IP and L4 CS calculations done
3730 * by the chip. The format of this field is indicated by the
3731 * cs_all_ok_mode bit.
3733 #define RX_PKT_V2_CMPL_HI_FLAGS2_CS_OK_MASK \
3735 #define RX_PKT_V2_CMPL_HI_FLAGS2_CS_OK_SFT 10
3737 * This value is the complete 1's complement checksum calculated from
3738 * the start of the outer L3 header to the end of the packet (not
3739 * including the ethernet crc). It is valid when the
3740 * 'complete_checksum_calc' flag is set.
3742 #define RX_PKT_V2_CMPL_HI_FLAGS2_COMPLETE_CHECKSUM_MASK \
3743 UINT32_C(0xffff0000)
3744 #define RX_PKT_V2_CMPL_HI_FLAGS2_COMPLETE_CHECKSUM_SFT 16
3746 * This is data from the CFA block as indicated by the meta_format
3748 * - meta_format 0 - none - metadata2 = 0 - not valid/not stripped
3749 * - meta_format 1 - act_rec_ptr - metadata2 = {table_scope[5:0],
3750 * act_rec_ptr[25:0]}
3751 * - meta_format 2 - tunnel_id - metadata2 = tunnel_id[31:0]
3752 * - meta_format 3 - chdr_data - metadata2 = updated_chdr_data[31:0]
3753 * - meta_format 4 - hdr_offsets - metadata2 = hdr_offsets[31:0]
3754 * When vee_cmpl_mode is set in VNIC context, this is the upper 32b
3755 * of the host address from the first BD used to place the packet.
3760 * This value is written by the NIC such that it will be different
3761 * for each pass through the completion queue. The even passes
3762 * will write 1. The odd passes will write 0.
3764 #define RX_PKT_V2_CMPL_HI_V2 \
3766 #define RX_PKT_V2_CMPL_HI_ERRORS_MASK \
3768 #define RX_PKT_V2_CMPL_HI_ERRORS_SFT 1
3770 * This error indicates that there was some sort of problem with
3771 * the BDs for the packet that was found after part of the
3772 * packet was already placed. The packet should be treated as
3775 #define RX_PKT_V2_CMPL_HI_ERRORS_BUFFER_ERROR_MASK \
3777 #define RX_PKT_V2_CMPL_HI_ERRORS_BUFFER_ERROR_SFT 1
3778 /* No buffer error */
3779 #define RX_PKT_V2_CMPL_HI_ERRORS_BUFFER_ERROR_NO_BUFFER \
3780 (UINT32_C(0x0) << 1)
3782 * Did Not Fit: Packet did not fit into packet buffer provided.
3783 * For regular placement, this means the packet did not fit in
3784 * the buffer provided. For HDS and jumbo placement, this means
3785 * that the packet could not be placed into 8 physical buffers
3786 * (if fixed-size buffers are used), or that the packet could
3787 * not be placed in the number of physical buffers configured
3788 * for the VNIC (if variable-size buffers are used)
3790 #define RX_PKT_V2_CMPL_HI_ERRORS_BUFFER_ERROR_DID_NOT_FIT \
3791 (UINT32_C(0x1) << 1)
3793 * Not On Chip: All BDs needed for the packet were not on-chip
3794 * when the packet arrived. For regular placement, this error is
3795 * not valid. For HDS and jumbo placement, this means that not
3796 * enough agg BDs were posted to place the packet.
3798 #define RX_PKT_V2_CMPL_HI_ERRORS_BUFFER_ERROR_NOT_ON_CHIP \
3799 (UINT32_C(0x2) << 1)
3802 * BDs were not formatted correctly.
3804 #define RX_PKT_V2_CMPL_HI_ERRORS_BUFFER_ERROR_BAD_FORMAT \
3805 (UINT32_C(0x3) << 1)
3808 * There was a bad_format error on the previous operation
3810 #define RX_PKT_V2_CMPL_HI_ERRORS_BUFFER_ERROR_FLUSH \
3811 (UINT32_C(0x5) << 1)
3812 #define RX_PKT_V2_CMPL_HI_ERRORS_BUFFER_ERROR_LAST \
3813 RX_PKT_V2_CMPL_HI_ERRORS_BUFFER_ERROR_FLUSH
3815 * This indicates that there was an error in the outer tunnel
3816 * portion of the packet when this field is non-zero.
3818 #define RX_PKT_V2_CMPL_HI_ERRORS_OT_PKT_ERROR_MASK \
3820 #define RX_PKT_V2_CMPL_HI_ERRORS_OT_PKT_ERROR_SFT 4
3822 * No additional error occurred on the outer tunnel portion
3823 * of the packet or the packet does not have a outer tunnel.
3825 #define RX_PKT_V2_CMPL_HI_ERRORS_OT_PKT_ERROR_NO_ERROR \
3826 (UINT32_C(0x0) << 4)
3828 * Indicates that IP header version does not match expectation
3829 * from L2 Ethertype for IPv4 and IPv6 in the outer tunnel header.
3831 #define RX_PKT_V2_CMPL_HI_ERRORS_OT_PKT_ERROR_OT_L3_BAD_VERSION \
3832 (UINT32_C(0x1) << 4)
3834 * Indicates that header length is out of range in the outer
3835 * tunnel header. Valid for IPv4.
3837 #define RX_PKT_V2_CMPL_HI_ERRORS_OT_PKT_ERROR_OT_L3_BAD_HDR_LEN \
3838 (UINT32_C(0x2) << 4)
3840 * Indicates that physical packet is shorter than that claimed
3841 * by the outer tunnel l3 header length. Valid for IPv4, or
3842 * IPv6 outer tunnel packets.
3844 #define RX_PKT_V2_CMPL_HI_ERRORS_OT_PKT_ERROR_OT_IP_TOTAL_ERROR \
3845 (UINT32_C(0x3) << 4)
3847 * Indicates that the physical packet is shorter than that
3848 * claimed by the outer tunnel UDP header length for a outer
3849 * tunnel UDP packet that is not fragmented.
3851 #define RX_PKT_V2_CMPL_HI_ERRORS_OT_PKT_ERROR_OT_UDP_TOTAL_ERROR \
3852 (UINT32_C(0x4) << 4)
3854 * Indicates that the IPv4 TTL or IPv6 hop limit check have
3855 * failed (e.g. TTL = 0) in the outer tunnel header. Valid for
3858 #define RX_PKT_V2_CMPL_HI_ERRORS_OT_PKT_ERROR_OT_L3_BAD_TTL \
3859 (UINT32_C(0x5) << 4)
3861 * Indicates that the IP checksum failed its check in the outer
3864 #define RX_PKT_V2_CMPL_HI_ERRORS_OT_PKT_ERROR_OT_IP_CS_ERROR \
3865 (UINT32_C(0x6) << 4)
3867 * Indicates that the L4 checksum failed its check in the outer
3870 #define RX_PKT_V2_CMPL_HI_ERRORS_OT_PKT_ERROR_OT_L4_CS_ERROR \
3871 (UINT32_C(0x7) << 4)
3872 #define RX_PKT_V2_CMPL_HI_ERRORS_OT_PKT_ERROR_LAST \
3873 RX_PKT_V2_CMPL_HI_ERRORS_OT_PKT_ERROR_OT_L4_CS_ERROR
3875 * This indicates that there was a CRC error on either an FCoE
3876 * or RoCE packet. The itype indicates the packet type.
3878 #define RX_PKT_V2_CMPL_HI_ERRORS_CRC_ERROR \
3881 * This indicates that there was an error in the tunnel portion
3882 * of the packet when this field is non-zero.
3884 #define RX_PKT_V2_CMPL_HI_ERRORS_T_PKT_ERROR_MASK \
3886 #define RX_PKT_V2_CMPL_HI_ERRORS_T_PKT_ERROR_SFT 9
3888 * No additional error occurred on the tunnel portion
3889 * of the packet or the packet does not have a tunnel.
3891 #define RX_PKT_V2_CMPL_HI_ERRORS_T_PKT_ERROR_NO_ERROR \
3892 (UINT32_C(0x0) << 9)
3894 * Indicates that IP header version does not match expectation
3895 * from L2 Ethertype for IPv4 and IPv6 in the tunnel header.
3897 #define RX_PKT_V2_CMPL_HI_ERRORS_T_PKT_ERROR_T_L3_BAD_VERSION \
3898 (UINT32_C(0x1) << 9)
3900 * Indicates that header length is out of range in the tunnel
3901 * header. Valid for IPv4.
3903 #define RX_PKT_V2_CMPL_HI_ERRORS_T_PKT_ERROR_T_L3_BAD_HDR_LEN \
3904 (UINT32_C(0x2) << 9)
3906 * Indicates that physical packet is shorter than that claimed
3907 * by the tunnel l3 header length. Valid for IPv4, or IPv6 tunnel
3910 #define RX_PKT_V2_CMPL_HI_ERRORS_T_PKT_ERROR_T_IP_TOTAL_ERROR \
3911 (UINT32_C(0x3) << 9)
3913 * Indicates that the physical packet is shorter than that claimed
3914 * by the tunnel UDP header length for a tunnel UDP packet that is
3917 #define RX_PKT_V2_CMPL_HI_ERRORS_T_PKT_ERROR_T_UDP_TOTAL_ERROR \
3918 (UINT32_C(0x4) << 9)
3920 * Indicates that the IPv4 TTL or IPv6 hop limit check have failed
3921 * (e.g. TTL = 0) in the tunnel header. Valid for IPv4, and IPv6.
3923 #define RX_PKT_V2_CMPL_HI_ERRORS_T_PKT_ERROR_T_L3_BAD_TTL \
3924 (UINT32_C(0x5) << 9)
3926 * Indicates that the IP checksum failed its check in the tunnel
3929 #define RX_PKT_V2_CMPL_HI_ERRORS_T_PKT_ERROR_T_IP_CS_ERROR \
3930 (UINT32_C(0x6) << 9)
3932 * Indicates that the L4 checksum failed its check in the tunnel
3935 #define RX_PKT_V2_CMPL_HI_ERRORS_T_PKT_ERROR_T_L4_CS_ERROR \
3936 (UINT32_C(0x7) << 9)
3937 #define RX_PKT_V2_CMPL_HI_ERRORS_T_PKT_ERROR_LAST \
3938 RX_PKT_V2_CMPL_HI_ERRORS_T_PKT_ERROR_T_L4_CS_ERROR
3940 * This indicates that there was an error in the inner
3941 * portion of the packet when this
3942 * field is non-zero.
3944 #define RX_PKT_V2_CMPL_HI_ERRORS_PKT_ERROR_MASK \
3946 #define RX_PKT_V2_CMPL_HI_ERRORS_PKT_ERROR_SFT 12
3948 * No additional error occurred on the tunnel portion
3949 * or the packet of the packet does not have a tunnel.
3951 #define RX_PKT_V2_CMPL_HI_ERRORS_PKT_ERROR_NO_ERROR \
3952 (UINT32_C(0x0) << 12)
3954 * Indicates that IP header version does not match
3955 * expectation from L2 Ethertype for IPv4 and IPv6 or that
3956 * option other than VFT was parsed on
3959 #define RX_PKT_V2_CMPL_HI_ERRORS_PKT_ERROR_L3_BAD_VERSION \
3960 (UINT32_C(0x1) << 12)
3962 * indicates that header length is out of range. Valid for
3965 #define RX_PKT_V2_CMPL_HI_ERRORS_PKT_ERROR_L3_BAD_HDR_LEN \
3966 (UINT32_C(0x2) << 12)
3968 * indicates that the IPv4 TTL or IPv6 hop limit check
3969 * have failed (e.g. TTL = 0). Valid for IPv4, and IPv6
3971 #define RX_PKT_V2_CMPL_HI_ERRORS_PKT_ERROR_L3_BAD_TTL \
3972 (UINT32_C(0x3) << 12)
3974 * Indicates that physical packet is shorter than that
3975 * claimed by the l3 header length. Valid for IPv4,
3976 * IPv6 packet or RoCE packets.
3978 #define RX_PKT_V2_CMPL_HI_ERRORS_PKT_ERROR_IP_TOTAL_ERROR \
3979 (UINT32_C(0x4) << 12)
3981 * Indicates that the physical packet is shorter than that
3982 * claimed by the UDP header length for a UDP packet that is
3985 #define RX_PKT_V2_CMPL_HI_ERRORS_PKT_ERROR_UDP_TOTAL_ERROR \
3986 (UINT32_C(0x5) << 12)
3988 * Indicates that TCP header length > IP payload. Valid for
3991 #define RX_PKT_V2_CMPL_HI_ERRORS_PKT_ERROR_L4_BAD_HDR_LEN \
3992 (UINT32_C(0x6) << 12)
3993 /* Indicates that TCP header length < 5. Valid for TCP. */
3994 #define RX_PKT_V2_CMPL_HI_ERRORS_PKT_ERROR_L4_BAD_HDR_LEN_TOO_SMALL \
3995 (UINT32_C(0x7) << 12)
3997 * Indicates that TCP option headers result in a TCP header
3998 * size that does not match data offset in TCP header. Valid
4001 #define RX_PKT_V2_CMPL_HI_ERRORS_PKT_ERROR_L4_BAD_OPT_LEN \
4002 (UINT32_C(0x8) << 12)
4004 * Indicates that the IP checksum failed its check in the
4007 #define RX_PKT_V2_CMPL_HI_ERRORS_PKT_ERROR_IP_CS_ERROR \
4008 (UINT32_C(0x9) << 12)
4010 * Indicates that the L4 checksum failed its check in the
4013 #define RX_PKT_V2_CMPL_HI_ERRORS_PKT_ERROR_L4_CS_ERROR \
4014 (UINT32_C(0xa) << 12)
4015 #define RX_PKT_V2_CMPL_HI_ERRORS_PKT_ERROR_LAST \
4016 RX_PKT_V2_CMPL_HI_ERRORS_PKT_ERROR_L4_CS_ERROR
4018 * This is data from the CFA block as indicated by the meta_format
4022 /* When meta_format=1, this value is the VLAN VID. */
4023 #define RX_PKT_V2_CMPL_HI_METADATA0_VID_MASK UINT32_C(0xfff)
4024 #define RX_PKT_V2_CMPL_HI_METADATA0_VID_SFT 0
4025 /* When meta_format=1, this value is the VLAN DE. */
4026 #define RX_PKT_V2_CMPL_HI_METADATA0_DE UINT32_C(0x1000)
4027 /* When meta_format=1, this value is the VLAN PRI. */
4028 #define RX_PKT_V2_CMPL_HI_METADATA0_PRI_MASK UINT32_C(0xe000)
4029 #define RX_PKT_V2_CMPL_HI_METADATA0_PRI_SFT 13
4031 * The timestamp field contains the 32b timestamp for the packet from
4038 * This TPA completion structure is used on devices where the
4039 * `hwrm_vnic_qcaps.max_aggs_supported` value is 0.
4041 /* rx_tpa_start_cmpl (size:128b/16B) */
4042 struct rx_tpa_start_cmpl {
4043 uint16_t flags_type;
4045 * This field indicates the exact type of the completion.
4046 * By convention, the LSB identifies the length of the
4047 * record in 16B units. Even values indicate 16B
4048 * records. Odd values indicate 32B
4051 #define RX_TPA_START_CMPL_TYPE_MASK UINT32_C(0x3f)
4052 #define RX_TPA_START_CMPL_TYPE_SFT 0
4054 * RX L2 TPA Start Completion:
4055 * Completion at the beginning of a TPA operation.
4058 #define RX_TPA_START_CMPL_TYPE_RX_TPA_START UINT32_C(0x13)
4059 #define RX_TPA_START_CMPL_TYPE_LAST \
4060 RX_TPA_START_CMPL_TYPE_RX_TPA_START
4061 #define RX_TPA_START_CMPL_FLAGS_MASK UINT32_C(0xffc0)
4062 #define RX_TPA_START_CMPL_FLAGS_SFT 6
4063 /* This bit will always be '0' for TPA start completions. */
4064 #define RX_TPA_START_CMPL_FLAGS_ERROR UINT32_C(0x40)
4065 /* This field indicates how the packet was placed in the buffer. */
4066 #define RX_TPA_START_CMPL_FLAGS_PLACEMENT_MASK UINT32_C(0x380)
4067 #define RX_TPA_START_CMPL_FLAGS_PLACEMENT_SFT 7
4070 * TPA Packet was placed using jumbo algorithm. This means
4071 * that the first buffer will be filled with data before
4072 * moving to aggregation buffers. Each aggregation buffer
4073 * will be filled before moving to the next aggregation
4076 #define RX_TPA_START_CMPL_FLAGS_PLACEMENT_JUMBO \
4077 (UINT32_C(0x1) << 7)
4079 * Header/Data Separation:
4080 * Packet was placed using Header/Data separation algorithm.
4081 * The separation location is indicated by the itype field.
4083 #define RX_TPA_START_CMPL_FLAGS_PLACEMENT_HDS \
4084 (UINT32_C(0x2) << 7)
4087 * Packet will be placed using GRO/Jumbo where the first
4088 * packet is filled with data. Subsequent packets will be
4089 * placed such that any one packet does not span two
4090 * aggregation buffers unless it starts at the beginning of
4091 * an aggregation buffer.
4093 #define RX_TPA_START_CMPL_FLAGS_PLACEMENT_GRO_JUMBO \
4094 (UINT32_C(0x5) << 7)
4096 * GRO/Header-Data Separation:
4097 * Packet will be placed using GRO/HDS where the header
4098 * is in the first packet.
4099 * Payload of each packet will be
4100 * placed such that any one packet does not span two
4101 * aggregation buffers unless it starts at the beginning of
4102 * an aggregation buffer.
4104 #define RX_TPA_START_CMPL_FLAGS_PLACEMENT_GRO_HDS \
4105 (UINT32_C(0x6) << 7)
4106 #define RX_TPA_START_CMPL_FLAGS_PLACEMENT_LAST \
4107 RX_TPA_START_CMPL_FLAGS_PLACEMENT_GRO_HDS
4108 /* This bit is '1' if the RSS field in this completion is valid. */
4109 #define RX_TPA_START_CMPL_FLAGS_RSS_VALID UINT32_C(0x400)
4111 #define RX_TPA_START_CMPL_FLAGS_UNUSED UINT32_C(0x800)
4113 * This value indicates what the inner packet determined for the
4116 #define RX_TPA_START_CMPL_FLAGS_ITYPE_MASK UINT32_C(0xf000)
4117 #define RX_TPA_START_CMPL_FLAGS_ITYPE_SFT 12
4120 * Indicates that the packet was IP and TCP.
4122 #define RX_TPA_START_CMPL_FLAGS_ITYPE_TCP \
4123 (UINT32_C(0x2) << 12)
4124 #define RX_TPA_START_CMPL_FLAGS_ITYPE_LAST \
4125 RX_TPA_START_CMPL_FLAGS_ITYPE_TCP
4127 * This value indicates the amount of packet data written to the
4128 * buffer the opaque field in this completion corresponds to.
4132 * This is a copy of the opaque field from the RX BD this completion
4137 * This value is written by the NIC such that it will be different
4138 * for each pass through the completion queue. The even passes
4139 * will write 1. The odd passes will write 0.
4143 * This value is written by the NIC such that it will be different
4144 * for each pass through the completion queue. The even passes
4145 * will write 1. The odd passes will write 0.
4147 #define RX_TPA_START_CMPL_V1 UINT32_C(0x1)
4148 #define RX_TPA_START_CMPL_LAST RX_TPA_START_CMPL_V1
4150 * This is the RSS hash type for the packet. The value is packed
4151 * {tuple_extrac_op[1:0],rss_profile_id[4:0],tuple_extrac_op[2]}.
4153 * The value of tuple_extrac_op provides the information about
4154 * what fields the hash was computed on.
4155 * * 0: The RSS hash was computed over source IP address,
4156 * destination IP address, source port, and destination port of inner
4157 * IP and TCP or UDP headers. Note: For non-tunneled packets,
4158 * the packet headers are considered inner packet headers for the RSS
4159 * hash computation purpose.
4160 * * 1: The RSS hash was computed over source IP address and destination
4161 * IP address of inner IP header. Note: For non-tunneled packets,
4162 * the packet headers are considered inner packet headers for the RSS
4163 * hash computation purpose.
4164 * * 2: The RSS hash was computed over source IP address,
4165 * destination IP address, source port, and destination port of
4166 * IP and TCP or UDP headers of outer tunnel headers.
4167 * Note: For non-tunneled packets, this value is not applicable.
4168 * * 3: The RSS hash was computed over source IP address and
4169 * destination IP address of IP header of outer tunnel headers.
4170 * Note: For non-tunneled packets, this value is not applicable.
4172 * Note that 4-tuples values listed above are applicable
4173 * for layer 4 protocols supported and enabled for RSS in the hardware,
4174 * HWRM firmware, and drivers. For example, if RSS hash is supported and
4175 * enabled for TCP traffic only, then the values of tuple_extract_op
4176 * corresponding to 4-tuples are only valid for TCP traffic.
4178 uint8_t rss_hash_type;
4180 * This is the aggregation ID that the completion is associated
4181 * with. Use this number to correlate the TPA start completion
4182 * with the TPA end completion.
4185 /* unused2 is 9 b */
4186 #define RX_TPA_START_CMPL_UNUSED2_MASK UINT32_C(0x1ff)
4187 #define RX_TPA_START_CMPL_UNUSED2_SFT 0
4189 * This is the aggregation ID that the completion is associated
4190 * with. Use this number to correlate the TPA start completion
4191 * with the TPA end completion.
4193 #define RX_TPA_START_CMPL_AGG_ID_MASK UINT32_C(0xfe00)
4194 #define RX_TPA_START_CMPL_AGG_ID_SFT 9
4196 * This value is the RSS hash value calculated for the packet
4197 * based on the mode bits and key value in the VNIC.
4203 * Last 16 bytes of rx_tpa_start_cmpl.
4205 * This TPA completion structure is used on devices where the
4206 * `hwrm_vnic_qcaps.max_aggs_supported` value is 0.
4208 /* rx_tpa_start_cmpl_hi (size:128b/16B) */
4209 struct rx_tpa_start_cmpl_hi {
4212 * This indicates that the ip checksum was calculated for the
4213 * inner packet and that the sum passed for all segments
4214 * included in the aggregation.
4216 #define RX_TPA_START_CMPL_FLAGS2_IP_CS_CALC UINT32_C(0x1)
4218 * This indicates that the TCP, UDP or ICMP checksum was
4219 * calculated for the inner packet and that the sum passed
4220 * for all segments included in the aggregation.
4222 #define RX_TPA_START_CMPL_FLAGS2_L4_CS_CALC UINT32_C(0x2)
4224 * This indicates that the ip checksum was calculated for the
4225 * tunnel header and that the sum passed for all segments
4226 * included in the aggregation.
4228 #define RX_TPA_START_CMPL_FLAGS2_T_IP_CS_CALC UINT32_C(0x4)
4230 * This indicates that the UDP checksum was
4231 * calculated for the tunnel packet and that the sum passed for
4232 * all segments included in the aggregation.
4234 #define RX_TPA_START_CMPL_FLAGS2_T_L4_CS_CALC UINT32_C(0x8)
4235 /* This value indicates what format the metadata field is. */
4236 #define RX_TPA_START_CMPL_FLAGS2_META_FORMAT_MASK UINT32_C(0xf0)
4237 #define RX_TPA_START_CMPL_FLAGS2_META_FORMAT_SFT 4
4238 /* No metadata information. Value is zero. */
4239 #define RX_TPA_START_CMPL_FLAGS2_META_FORMAT_NONE \
4240 (UINT32_C(0x0) << 4)
4242 * The metadata field contains the VLAN tag and TPID value.
4243 * - metadata[11:0] contains the vlan VID value.
4244 * - metadata[12] contains the vlan DE value.
4245 * - metadata[15:13] contains the vlan PRI value.
4246 * - metadata[31:16] contains the vlan TPID value.
4248 #define RX_TPA_START_CMPL_FLAGS2_META_FORMAT_VLAN \
4249 (UINT32_C(0x1) << 4)
4250 #define RX_TPA_START_CMPL_FLAGS2_META_FORMAT_LAST \
4251 RX_TPA_START_CMPL_FLAGS2_META_FORMAT_VLAN
4253 * This field indicates the IP type for the inner-most IP header.
4254 * A value of '0' indicates IPv4. A value of '1' indicates IPv6.
4256 #define RX_TPA_START_CMPL_FLAGS2_IP_TYPE UINT32_C(0x100)
4258 * This is data from the CFA block as indicated by the meta_format
4262 /* When meta_format=1, this value is the VLAN VID. */
4263 #define RX_TPA_START_CMPL_METADATA_VID_MASK UINT32_C(0xfff)
4264 #define RX_TPA_START_CMPL_METADATA_VID_SFT 0
4265 /* When meta_format=1, this value is the VLAN DE. */
4266 #define RX_TPA_START_CMPL_METADATA_DE UINT32_C(0x1000)
4267 /* When meta_format=1, this value is the VLAN PRI. */
4268 #define RX_TPA_START_CMPL_METADATA_PRI_MASK UINT32_C(0xe000)
4269 #define RX_TPA_START_CMPL_METADATA_PRI_SFT 13
4270 /* When meta_format=1, this value is the VLAN TPID. */
4271 #define RX_TPA_START_CMPL_METADATA_TPID_MASK UINT32_C(0xffff0000)
4272 #define RX_TPA_START_CMPL_METADATA_TPID_SFT 16
4275 * This value is written by the NIC such that it will be different
4276 * for each pass through the completion queue. The even passes
4277 * will write 1. The odd passes will write 0.
4279 #define RX_TPA_START_CMPL_V2 UINT32_C(0x1)
4281 * This field identifies the CFA action rule that was used for this
4286 * This is the size in bytes of the inner most L4 header.
4287 * This can be subtracted from the payload_offset to determine
4288 * the start of the inner most L4 header.
4290 uint32_t inner_l4_size_inner_l3_offset_inner_l2_offset_outer_l3_offset;
4292 * This is the offset from the beginning of the packet in bytes for
4293 * the outer L3 header. If there is no outer L3 header, then this
4296 #define RX_TPA_START_CMPL_OUTER_L3_OFFSET_MASK UINT32_C(0x1ff)
4297 #define RX_TPA_START_CMPL_OUTER_L3_OFFSET_SFT 0
4299 * This is the offset from the beginning of the packet in bytes for
4300 * the inner most L2 header.
4302 #define RX_TPA_START_CMPL_INNER_L2_OFFSET_MASK UINT32_C(0x3fe00)
4303 #define RX_TPA_START_CMPL_INNER_L2_OFFSET_SFT 9
4305 * This is the offset from the beginning of the packet in bytes for
4306 * the inner most L3 header.
4308 #define RX_TPA_START_CMPL_INNER_L3_OFFSET_MASK UINT32_C(0x7fc0000)
4309 #define RX_TPA_START_CMPL_INNER_L3_OFFSET_SFT 18
4311 * This is the size in bytes of the inner most L4 header.
4312 * This can be subtracted from the payload_offset to determine
4313 * the start of the inner most L4 header.
4315 #define RX_TPA_START_CMPL_INNER_L4_SIZE_MASK UINT32_C(0xf8000000)
4316 #define RX_TPA_START_CMPL_INNER_L4_SIZE_SFT 27
4320 * This TPA completion structure is used on devices where the
4321 * `hwrm_vnic_qcaps.max_aggs_supported` value is 0.
4322 * RX L2 TPA Start V2 Completion Record (32 bytes split to 2 16-byte
4325 /* rx_tpa_start_v2_cmpl (size:128b/16B) */
4326 struct rx_tpa_start_v2_cmpl {
4327 uint16_t flags_type;
4329 * This field indicates the exact type of the completion.
4330 * By convention, the LSB identifies the length of the
4331 * record in 16B units. Even values indicate 16B
4332 * records. Odd values indicate 32B
4335 #define RX_TPA_START_V2_CMPL_TYPE_MASK \
4337 #define RX_TPA_START_V2_CMPL_TYPE_SFT 0
4339 * RX L2 TPA Start V2 Completion:
4340 * Completion at the beginning of a TPA operation.
4342 * This is the new version of the RX_TPA_START completion used
4343 * in SR2 and later chips.
4345 #define RX_TPA_START_V2_CMPL_TYPE_RX_TPA_START_V2 \
4347 #define RX_TPA_START_V2_CMPL_TYPE_LAST \
4348 RX_TPA_START_V2_CMPL_TYPE_RX_TPA_START_V2
4349 #define RX_TPA_START_V2_CMPL_FLAGS_MASK \
4351 #define RX_TPA_START_V2_CMPL_FLAGS_SFT 6
4353 * When this bit is '1', it indicates a packet that has an error
4354 * of some type. Type of error is indicated in error_flags.
4356 #define RX_TPA_START_V2_CMPL_FLAGS_ERROR \
4358 /* This field indicates how the packet was placed in the buffer. */
4359 #define RX_TPA_START_V2_CMPL_FLAGS_PLACEMENT_MASK \
4361 #define RX_TPA_START_V2_CMPL_FLAGS_PLACEMENT_SFT 7
4364 * TPA Packet was placed using jumbo algorithm. This means
4365 * that the first buffer will be filled with data before
4366 * moving to aggregation buffers. Each aggregation buffer
4367 * will be filled before moving to the next aggregation
4370 #define RX_TPA_START_V2_CMPL_FLAGS_PLACEMENT_JUMBO \
4371 (UINT32_C(0x1) << 7)
4373 * Header/Data Separation:
4374 * Packet was placed using Header/Data separation algorithm.
4375 * The separation location is indicated by the itype field.
4377 #define RX_TPA_START_V2_CMPL_FLAGS_PLACEMENT_HDS \
4378 (UINT32_C(0x2) << 7)
4381 * Packet will be placed using In-Order Completion/Jumbo where
4382 * the first packet of the aggregation is placed using Jumbo
4383 * Placement. Subsequent packets will be placed such that each
4384 * packet starts at the beginning of an aggregation buffer.
4386 #define RX_TPA_START_V2_CMPL_FLAGS_PLACEMENT_IOC_JUMBO \
4387 (UINT32_C(0x4) << 7)
4390 * Packet will be placed using GRO/Jumbo where the first
4391 * packet is filled with data. Subsequent packets will be
4392 * placed such that any one packet does not span two
4393 * aggregation buffers unless it starts at the beginning of
4394 * an aggregation buffer.
4396 #define RX_TPA_START_V2_CMPL_FLAGS_PLACEMENT_GRO_JUMBO \
4397 (UINT32_C(0x5) << 7)
4399 * GRO/Header-Data Separation:
4400 * Packet will be placed using GRO/HDS where the header
4401 * is in the first packet.
4402 * Payload of each packet will be
4403 * placed such that any one packet does not span two
4404 * aggregation buffers unless it starts at the beginning of
4405 * an aggregation buffer.
4407 #define RX_TPA_START_V2_CMPL_FLAGS_PLACEMENT_GRO_HDS \
4408 (UINT32_C(0x6) << 7)
4410 * IOC/Header-Data Separation:
4411 * Packet will be placed using In-Order Completion/HDS where
4412 * the header is in the first packet buffer. Payload of each
4413 * packet will be placed such that each packet starts at the
4414 * beginning of an aggregation buffer.
4416 #define RX_TPA_START_V2_CMPL_FLAGS_PLACEMENT_IOC_HDS \
4417 (UINT32_C(0x7) << 7)
4418 #define RX_TPA_START_V2_CMPL_FLAGS_PLACEMENT_LAST \
4419 RX_TPA_START_V2_CMPL_FLAGS_PLACEMENT_IOC_HDS
4420 /* This bit is '1' if the RSS field in this completion is valid. */
4421 #define RX_TPA_START_V2_CMPL_FLAGS_RSS_VALID \
4424 * This bit is '1' if metadata has been added to the end of the
4425 * packet in host memory. Metadata starts at the first 32B boundary
4426 * after the end of the packet for regular and jumbo placement. It
4427 * starts at the first 32B boundary after the end of the header for
4428 * HDS placement. The length of the metadata is indicated in the
4431 #define RX_TPA_START_V2_CMPL_FLAGS_PKT_METADATA_PRESENT \
4434 * This value indicates what the inner packet determined for the
4437 #define RX_TPA_START_V2_CMPL_FLAGS_ITYPE_MASK \
4439 #define RX_TPA_START_V2_CMPL_FLAGS_ITYPE_SFT 12
4442 * Indicates that the packet was IP and TCP.
4444 #define RX_TPA_START_V2_CMPL_FLAGS_ITYPE_TCP \
4445 (UINT32_C(0x2) << 12)
4446 #define RX_TPA_START_V2_CMPL_FLAGS_ITYPE_LAST \
4447 RX_TPA_START_V2_CMPL_FLAGS_ITYPE_TCP
4449 * This value indicates the amount of packet data written to the
4450 * buffer the opaque field in this completion corresponds to.
4454 * This is a copy of the opaque field from the RX BD this completion
4455 * corresponds to. If the VNIC is configured to not use an Rx BD for
4456 * the TPA Start completion, then this is a copy of the opaque field
4457 * from the first BD used to place the TPA Start packet.
4461 * This value is written by the NIC such that it will be different
4462 * for each pass through the completion queue. The even passes
4463 * will write 1. The odd passes will write 0.
4467 * This value is written by the NIC such that it will be different
4468 * for each pass through the completion queue. The even passes
4469 * will write 1. The odd passes will write 0.
4471 #define RX_TPA_START_V2_CMPL_V1 UINT32_C(0x1)
4472 #define RX_TPA_START_V2_CMPL_LAST RX_TPA_START_V2_CMPL_V1
4474 * This is the RSS hash type for the packet. The value is packed
4475 * {tuple_extrac_op[1:0],rss_profile_id[4:0],tuple_extrac_op[2]}.
4477 * The value of tuple_extrac_op provides the information about
4478 * what fields the hash was computed on.
4479 * * 0: The RSS hash was computed over source IP address,
4480 * destination IP address, source port, and destination port of inner
4481 * IP and TCP or UDP headers. Note: For non-tunneled packets,
4482 * the packet headers are considered inner packet headers for the RSS
4483 * hash computation purpose.
4484 * * 1: The RSS hash was computed over source IP address and destination
4485 * IP address of inner IP header. Note: For non-tunneled packets,
4486 * the packet headers are considered inner packet headers for the RSS
4487 * hash computation purpose.
4488 * * 2: The RSS hash was computed over source IP address,
4489 * destination IP address, source port, and destination port of
4490 * IP and TCP or UDP headers of outer tunnel headers.
4491 * Note: For non-tunneled packets, this value is not applicable.
4492 * * 3: The RSS hash was computed over source IP address and
4493 * destination IP address of IP header of outer tunnel headers.
4494 * Note: For non-tunneled packets, this value is not applicable.
4496 * Note that 4-tuples values listed above are applicable
4497 * for layer 4 protocols supported and enabled for RSS in the hardware,
4498 * HWRM firmware, and drivers. For example, if RSS hash is supported and
4499 * enabled for TCP traffic only, then the values of tuple_extract_op
4500 * corresponding to 4-tuples are only valid for TCP traffic.
4502 uint8_t rss_hash_type;
4504 * This is the aggregation ID that the completion is associated
4505 * with. Use this number to correlate the TPA start completion
4506 * with the TPA end completion.
4510 * This is the aggregation ID that the completion is associated
4511 * with. Use this number to correlate the TPA start completion
4512 * with the TPA end completion.
4514 #define RX_TPA_START_V2_CMPL_AGG_ID_MASK UINT32_C(0xfff)
4515 #define RX_TPA_START_V2_CMPL_AGG_ID_SFT 0
4516 #define RX_TPA_START_V2_CMPL_METADATA1_MASK \
4518 #define RX_TPA_START_V2_CMPL_METADATA1_SFT 12
4519 /* When meta_format != 0, this value is the VLAN TPID_SEL. */
4520 #define RX_TPA_START_V2_CMPL_METADATA1_TPID_SEL_MASK \
4522 #define RX_TPA_START_V2_CMPL_METADATA1_TPID_SEL_SFT 12
4524 #define RX_TPA_START_V2_CMPL_METADATA1_TPID_SEL_TPID88A8 \
4525 (UINT32_C(0x0) << 12)
4527 #define RX_TPA_START_V2_CMPL_METADATA1_TPID_SEL_TPID8100 \
4528 (UINT32_C(0x1) << 12)
4530 #define RX_TPA_START_V2_CMPL_METADATA1_TPID_SEL_TPID9100 \
4531 (UINT32_C(0x2) << 12)
4533 #define RX_TPA_START_V2_CMPL_METADATA1_TPID_SEL_TPID9200 \
4534 (UINT32_C(0x3) << 12)
4536 #define RX_TPA_START_V2_CMPL_METADATA1_TPID_SEL_TPID9300 \
4537 (UINT32_C(0x4) << 12)
4538 /* Value programmed in CFA VLANTPID register. */
4539 #define RX_TPA_START_V2_CMPL_METADATA1_TPID_SEL_TPIDCFG \
4540 (UINT32_C(0x5) << 12)
4541 #define RX_TPA_START_V2_CMPL_METADATA1_TPID_SEL_LAST \
4542 RX_TPA_START_V2_CMPL_METADATA1_TPID_SEL_TPIDCFG
4543 /* When meta_format != 0, this value is the VLAN valid. */
4544 #define RX_TPA_START_V2_CMPL_METADATA1_VALID \
4547 * This value is the RSS hash value calculated for the packet
4548 * based on the mode bits and key value in the VNIC.
4549 * When vee_cmpl_mode is set in VNIC context, this is the lower
4550 * 32b of the host address from the first BD used to place the packet.
4556 * Last 16 bytes of RX L2 TPA Start V2 Completion Record
4558 * This TPA completion structure is used on devices where the
4559 * `hwrm_vnic_qcaps.max_aggs_supported` value is 0.
4561 /* rx_tpa_start_v2_cmpl_hi (size:128b/16B) */
4562 struct rx_tpa_start_v2_cmpl_hi {
4564 /* This indicates that the aggregation was done using GRO rules. */
4565 #define RX_TPA_START_V2_CMPL_FLAGS2_AGG_GRO \
4568 * When this bit is '0', the cs_ok field has the following definition:-
4569 * ip_cs_ok[2:0] = The number of header groups with a valid IP checksum
4570 * in the delivered packet, counted from the outer-most header group to
4571 * the inner-most header group, stopping at the first error. -
4572 * l4_cs_ok[5:3] = The number of header groups with a valid L4 checksum
4573 * in the delivered packet, counted from the outer-most header group to
4574 * the inner-most header group, stopping at the first error. When this
4575 * bit is '1', the cs_ok field has the following definition: -
4576 * hdr_cnt[2:0] = The number of header groups that were parsed by the
4577 * chip and passed in the delivered packet. - ip_cs_all_ok[3] =This bit
4578 * will be '1' if all the parsed header groups with an IP checksum are
4579 * valid. - l4_cs_all_ok[4] = This bit will be '1' if all the parsed
4580 * header groups with an L4 checksum are valid.
4582 #define RX_TPA_START_V2_CMPL_FLAGS2_CS_ALL_OK_MODE \
4584 /* This value indicates what format the metadata field is. */
4585 #define RX_TPA_START_V2_CMPL_FLAGS2_META_FORMAT_MASK \
4587 #define RX_TPA_START_V2_CMPL_FLAGS2_META_FORMAT_SFT 4
4588 /* There is no metadata information. Values are zero. */
4589 #define RX_TPA_START_V2_CMPL_FLAGS2_META_FORMAT_NONE \
4590 (UINT32_C(0x0) << 4)
4592 * The {metadata1, metadata0} fields contain the vtag
4593 * information: - vtag[19:0] = {valid, tpid_sel[2:0], pri[2:0],
4594 * de, vid[11:0]} The metadata2 field contains the table scope
4595 * and action record pointer. - metadata2[25:0] contains the
4596 * action record pointer. - metadata2[31:26] contains the table
4599 #define RX_TPA_START_V2_CMPL_FLAGS2_META_FORMAT_ACT_REC_PTR \
4600 (UINT32_C(0x1) << 4)
4602 * The {metadata1, metadata0} fields contain the vtag
4604 * - vtag[19:0] = {valid, tpid_sel[2:0], pri[2:0], de, vid[11:0]}
4605 * The metadata2 field contains the Tunnel ID
4606 * value, justified to LSB. i
4607 * - VXLAN = VNI[23:0] -> VXLAN Network ID
4608 * - Geneve (NGE) = VNI[23:0] a-> Virtual Network Identifier
4609 * - NVGRE = TNI[23:0] -> Tenant Network ID
4610 * - GRE = KEY[31:0] -> key field with bit mask. zero if K=0
4611 * - IPv4 = 0 (not populated)
4612 * - IPv6 = Flow Label[19:0]
4613 * - PPPoE = sessionID[15:0]
4614 * - MPLs = Outer label[19:0]
4615 * - UPAR = Selected[31:0] with bit mask
4617 #define RX_TPA_START_V2_CMPL_FLAGS2_META_FORMAT_TUNNEL_ID \
4618 (UINT32_C(0x2) << 4)
4620 * The {metadata1, metadata0} fields contain the vtag
4622 * - vtag[19:0] = {valid, tpid_sel[2:0], pri[2:0],de, vid[11:0]}
4623 * The metadata2 field contains the 32b metadata from the prepended
4624 * header (chdr_data).
4626 #define RX_TPA_START_V2_CMPL_FLAGS2_META_FORMAT_CHDR_DATA \
4627 (UINT32_C(0x3) << 4)
4629 * The {metadata1, metadata0} fields contain the vtag
4631 * - vtag[19:0] = {valid, tpid_sel[2:0], pri[2:0], de, vid[11:0]}
4632 * The metadata2 field contains the outer_l3_offset,
4633 * inner_l2_offset, inner_l3_offset, and inner_l4_size.
4634 * - metadata2[8:0] contains the outer_l3_offset.
4635 * - metadata2[17:9] contains the inner_l2_offset.
4636 * - metadata2[26:18] contains the inner_l3_offset.
4637 * - metadata2[31:27] contains the inner_l4_size.
4639 #define RX_TPA_START_V2_CMPL_FLAGS2_META_FORMAT_HDR_OFFSET \
4640 (UINT32_C(0x4) << 4)
4641 #define RX_TPA_START_V2_CMPL_FLAGS2_META_FORMAT_LAST \
4642 RX_TPA_START_V2_CMPL_FLAGS2_META_FORMAT_HDR_OFFSET
4644 * This field indicates the IP type for the inner-most IP header.
4645 * A value of '0' indicates IPv4. A value of '1' indicates IPv6.
4646 * This value is only valid if itype indicates a packet
4647 * with an IP header.
4649 #define RX_TPA_START_V2_CMPL_FLAGS2_IP_TYPE \
4652 * This indicates that the complete 1's complement checksum was
4653 * calculated for the packet in the affregation.
4655 #define RX_TPA_START_V2_CMPL_FLAGS2_COMPLETE_CHECKSUM_CALC \
4658 * This field indicates the status of IP and L4 CS calculations done
4659 * by the chip. The format of this field is indicated by the
4660 * cs_all_ok_mode bit.
4661 * CS status for TPA packets is always valid. This means that "all_ok"
4662 * status will always be set. The ok count status will be set
4663 * appropriately for the packet header, such that all existing CS
4666 #define RX_TPA_START_V2_CMPL_FLAGS2_CS_OK_MASK \
4668 #define RX_TPA_START_V2_CMPL_FLAGS2_CS_OK_SFT 10
4670 * This value is the complete 1's complement checksum calculated from
4671 * the start of the outer L3 header to the end of the packet (not
4672 * including the ethernet crc). It is valid when the
4673 * 'complete_checksum_calc' flag is set. For TPA Start completions,
4674 * the complete checksum is calculated for the first packet in the
4677 #define RX_TPA_START_V2_CMPL_FLAGS2_COMPLETE_CHECKSUM_MASK \
4678 UINT32_C(0xffff0000)
4679 #define RX_TPA_START_V2_CMPL_FLAGS2_COMPLETE_CHECKSUM_SFT 16
4681 * This is data from the CFA block as indicated by the meta_format
4683 * - meta_format 0 - none - metadata2 = 0 - not valid/not stripped
4684 * - meta_format 1 - act_rec_ptr - metadata2 = {table_scope[5:0],
4685 * act_rec_ptr[25:0]}
4686 * - meta_format 2 - tunnel_id - metadata2 = tunnel_id[31:0]
4687 * - meta_format 3 - chdr_data - metadata2 = updated_chdr_data[31:0]
4688 * - meta_format 4 - hdr_offsets - metadata2 = hdr_offsets[31:0]
4689 * When vee_cmpl_mode is set in VNIC context, this is the upper 32b
4690 * of the host address from the first BD used to place the packet.
4695 * This value is written by the NIC such that it will be different
4696 * for each pass through the completion queue. The even passes
4697 * will write 1. The odd passes will write 0.
4699 #define RX_TPA_START_V2_CMPL_V2 \
4701 #define RX_TPA_START_V2_CMPL_ERRORS_MASK \
4703 #define RX_TPA_START_V2_CMPL_ERRORS_SFT 1
4705 * This error indicates that there was some sort of problem with
4706 * the BDs for the packetThe packet should be treated as
4709 #define RX_TPA_START_V2_CMPL_ERRORS_BUFFER_ERROR_MASK \
4711 #define RX_TPA_START_V2_CMPL_ERRORS_BUFFER_ERROR_SFT 1
4712 /* No buffer error */
4713 #define RX_TPA_START_V2_CMPL_ERRORS_BUFFER_ERROR_NO_BUFFER \
4714 (UINT32_C(0x0) << 1)
4717 * Packet did not fit into packet buffer provided. This means
4718 * that the TPA Start packet was too big to be placed into the
4719 * per-packet maximum number of physical buffers configured for
4720 * the VNIC, or that it was too big to be placed into the
4721 * per-aggregation maximum number of physical buffers configured
4722 * for the VNIC. This error only occurs when the VNIC is
4723 * configured for variable size receive buffers.
4725 #define RX_TPA_START_V2_CMPL_ERRORS_BUFFER_ERROR_DID_NOT_FIT \
4726 (UINT32_C(0x1) << 1)
4729 * BDs were not formatted correctly.
4731 #define RX_TPA_START_V2_CMPL_ERRORS_BUFFER_ERROR_BAD_FORMAT \
4732 (UINT32_C(0x3) << 1)
4735 * There was a bad_format error on the previous operation
4737 #define RX_TPA_START_V2_CMPL_ERRORS_BUFFER_ERROR_FLUSH \
4738 (UINT32_C(0x5) << 1)
4739 #define RX_TPA_START_V2_CMPL_ERRORS_BUFFER_ERROR_LAST \
4740 RX_TPA_START_V2_CMPL_ERRORS_BUFFER_ERROR_FLUSH
4742 * This is data from the CFA block as indicated by the meta_format
4746 /* When meta_format != 0, this value is the VLAN VID. */
4747 #define RX_TPA_START_V2_CMPL_METADATA0_VID_MASK UINT32_C(0xfff)
4748 #define RX_TPA_START_V2_CMPL_METADATA0_VID_SFT 0
4749 /* When meta_format != 0, this value is the VLAN DE. */
4750 #define RX_TPA_START_V2_CMPL_METADATA0_DE UINT32_C(0x1000)
4751 /* When meta_format != 0, this value is the VLAN PRI. */
4752 #define RX_TPA_START_V2_CMPL_METADATA0_PRI_MASK UINT32_C(0xe000)
4753 #define RX_TPA_START_V2_CMPL_METADATA0_PRI_SFT 13
4755 * This field contains the outer_l3_offset, inner_l2_offset,
4756 * inner_l3_offset, and inner_l4_size.
4758 * hdr_offsets[8:0] contains the outer_l3_offset.
4759 * hdr_offsets[17:9] contains the inner_l2_offset.
4760 * hdr_offsets[26:18] contains the inner_l3_offset.
4761 * hdr_offsets[31:27] contains the inner_l4_size.
4763 uint32_t hdr_offsets;
4767 * This TPA completion structure is used on devices where the
4768 * `hwrm_vnic_qcaps.max_aggs_supported` value is 0.
4770 /* rx_tpa_end_cmpl (size:128b/16B) */
4771 struct rx_tpa_end_cmpl {
4772 uint16_t flags_type;
4774 * This field indicates the exact type of the completion.
4775 * By convention, the LSB identifies the length of the
4776 * record in 16B units. Even values indicate 16B
4777 * records. Odd values indicate 32B
4780 #define RX_TPA_END_CMPL_TYPE_MASK UINT32_C(0x3f)
4781 #define RX_TPA_END_CMPL_TYPE_SFT 0
4783 * RX L2 TPA End Completion:
4784 * Completion at the end of a TPA operation.
4787 #define RX_TPA_END_CMPL_TYPE_RX_TPA_END UINT32_C(0x15)
4788 #define RX_TPA_END_CMPL_TYPE_LAST \
4789 RX_TPA_END_CMPL_TYPE_RX_TPA_END
4790 #define RX_TPA_END_CMPL_FLAGS_MASK UINT32_C(0xffc0)
4791 #define RX_TPA_END_CMPL_FLAGS_SFT 6
4793 * When this bit is '1', it indicates a packet that has an
4794 * error of some type. Type of error is indicated in
4797 #define RX_TPA_END_CMPL_FLAGS_ERROR UINT32_C(0x40)
4798 /* This field indicates how the packet was placed in the buffer. */
4799 #define RX_TPA_END_CMPL_FLAGS_PLACEMENT_MASK UINT32_C(0x380)
4800 #define RX_TPA_END_CMPL_FLAGS_PLACEMENT_SFT 7
4803 * TPA Packet was placed using jumbo algorithm. This means
4804 * that the first buffer will be filled with data before
4805 * moving to aggregation buffers. Each aggregation buffer
4806 * will be filled before moving to the next aggregation
4809 #define RX_TPA_END_CMPL_FLAGS_PLACEMENT_JUMBO \
4810 (UINT32_C(0x1) << 7)
4812 * Header/Data Separation:
4813 * Packet was placed using Header/Data separation algorithm.
4814 * The separation location is indicated by the itype field.
4816 #define RX_TPA_END_CMPL_FLAGS_PLACEMENT_HDS \
4817 (UINT32_C(0x2) << 7)
4820 * Packet will be placed using In-Order Completion/Jumbo where
4821 * the first packet of the aggregation is placed using Jumbo
4822 * Placement. Subsequent packets will be placed such that each
4823 * packet starts at the beginning of an aggregation buffer.
4825 #define RX_TPA_END_CMPL_FLAGS_PLACEMENT_IOC_JUMBO \
4826 (UINT32_C(0x4) << 7)
4829 * Packet will be placed using GRO/Jumbo where the first
4830 * packet is filled with data. Subsequent packets will be
4831 * placed such that any one packet does not span two
4832 * aggregation buffers unless it starts at the beginning of
4833 * an aggregation buffer.
4835 #define RX_TPA_END_CMPL_FLAGS_PLACEMENT_GRO_JUMBO \
4836 (UINT32_C(0x5) << 7)
4838 * GRO/Header-Data Separation:
4839 * Packet will be placed using GRO/HDS where the header
4840 * is in the first packet.
4841 * Payload of each packet will be
4842 * placed such that any one packet does not span two
4843 * aggregation buffers unless it starts at the beginning of
4844 * an aggregation buffer.
4846 #define RX_TPA_END_CMPL_FLAGS_PLACEMENT_GRO_HDS \
4847 (UINT32_C(0x6) << 7)
4849 * IOC/Header-Data Separation:
4850 * Packet will be placed using In-Order Completion/HDS where
4851 * the header is in the first packet buffer. Payload of each
4852 * packet will be placed such that each packet starts at the
4853 * beginning of an aggregation buffer.
4855 #define RX_TPA_END_CMPL_FLAGS_PLACEMENT_IOC_HDS \
4856 (UINT32_C(0x7) << 7)
4857 #define RX_TPA_END_CMPL_FLAGS_PLACEMENT_LAST \
4858 RX_TPA_END_CMPL_FLAGS_PLACEMENT_IOC_HDS
4860 #define RX_TPA_END_CMPL_FLAGS_UNUSED UINT32_C(0x400)
4862 * This bit is '1' if metadata has been added to the end of the
4863 * packet in host memory. Metadata starts at the first 32B boundary
4864 * after the end of the packet for regular and jumbo placement.
4865 * It starts at the first 32B boundary after the end of the header
4866 * for HDS placement. The length of the metadata is indicated in the
4869 #define RX_TPA_END_CMPL_FLAGS_PKT_METADATA_PRESENT UINT32_C(0x800)
4871 * This value indicates what the inner packet determined for the
4874 * Indicates that the packet was IP and TCP. This indicates
4875 * that the ip_cs field is valid and that the tcp_udp_cs
4876 * field is valid and contains the TCP checksum.
4877 * This also indicates that the payload_offset field is valid.
4879 #define RX_TPA_END_CMPL_FLAGS_ITYPE_MASK \
4881 #define RX_TPA_END_CMPL_FLAGS_ITYPE_SFT 12
4883 * This value is zero for TPA End completions.
4884 * There is no data in the buffer that corresponds to the opaque
4885 * value in this completion.
4889 * This is a copy of the opaque field from the RX BD this completion
4894 * This value is written by the NIC such that it will be different
4895 * for each pass through the completion queue. The even passes
4896 * will write 1. The odd passes will write 0.
4898 uint8_t agg_bufs_v1;
4900 * This value is written by the NIC such that it will be different
4901 * for each pass through the completion queue. The even passes
4902 * will write 1. The odd passes will write 0.
4904 #define RX_TPA_END_CMPL_V1 UINT32_C(0x1)
4906 * This value is the number of aggregation buffers that follow this
4907 * entry in the completion ring that are a part of this aggregation
4909 * If the value is zero, then the packet is completely contained
4910 * in the buffer space provided in the aggregation start completion.
4912 #define RX_TPA_END_CMPL_AGG_BUFS_MASK UINT32_C(0x7e)
4913 #define RX_TPA_END_CMPL_AGG_BUFS_SFT 1
4914 /* This value is the number of segments in the TPA operation. */
4917 * This value indicates the offset in bytes from the beginning of the packet
4918 * where the inner payload starts. This value is valid for TCP, UDP,
4919 * FCoE, and RoCE packets.
4921 * A value of zero indicates an offset of 256 bytes.
4923 uint8_t payload_offset;
4925 /* unused2 is 1 b */
4926 #define RX_TPA_END_CMPL_UNUSED2 UINT32_C(0x1)
4928 * This is the aggregation ID that the completion is associated
4929 * with. Use this number to correlate the TPA start completion
4930 * with the TPA end completion.
4932 #define RX_TPA_END_CMPL_AGG_ID_MASK UINT32_C(0xfe)
4933 #define RX_TPA_END_CMPL_AGG_ID_SFT 1
4935 * For non-GRO packets, this value is the
4936 * timestamp delta between earliest and latest timestamp values for
4937 * TPA packet. If packets were not time stamped, then delta will be
4940 * For GRO packets, this field is zero except for the following
4943 * Timestamp present indication. When '0', no Timestamp
4944 * option is in the packet. When '1', then a Timestamp
4945 * option is present in the packet.
4951 * Last 16 bytes of rx_tpa_end_cmpl.
4953 * This TPA completion structure is used on devices where the
4954 * `hwrm_vnic_qcaps.max_aggs_supported` value is 0.
4956 /* rx_tpa_end_cmpl_hi (size:128b/16B) */
4957 struct rx_tpa_end_cmpl_hi {
4958 uint32_t tpa_dup_acks;
4960 * This value is the number of duplicate ACKs that have been
4961 * received as part of the TPA operation.
4963 #define RX_TPA_END_CMPL_TPA_DUP_ACKS_MASK UINT32_C(0xf)
4964 #define RX_TPA_END_CMPL_TPA_DUP_ACKS_SFT 0
4966 * This value is the valid when TPA completion is active. It
4967 * indicates the length of the longest segment of the TPA operation
4968 * for LRO mode and the length of the first segment in GRO mode.
4970 * This value may be used by GRO software to re-construct the original
4971 * packet stream from the TPA packet. This is the length of all
4972 * but the last segment for GRO. In LRO mode this value may be used
4973 * to indicate MSS size to the stack.
4975 uint16_t tpa_seg_len;
4976 /* unused4 is 16 b */
4980 * This value is written by the NIC such that it will be different
4981 * for each pass through the completion queue. The even passes
4982 * will write 1. The odd passes will write 0.
4984 #define RX_TPA_END_CMPL_V2 UINT32_C(0x1)
4985 #define RX_TPA_END_CMPL_ERRORS_MASK UINT32_C(0xfffe)
4986 #define RX_TPA_END_CMPL_ERRORS_SFT 1
4988 * This error indicates that there was some sort of problem with
4989 * the BDs for the packet that was found after part of the
4990 * packet was already placed. The packet should be treated as
4993 #define RX_TPA_END_CMPL_ERRORS_BUFFER_ERROR_MASK UINT32_C(0xe)
4994 #define RX_TPA_END_CMPL_ERRORS_BUFFER_ERROR_SFT 1
4996 * This error occurs when there is a fatal HW problem in
4997 * the chip only. It indicates that there were not
4998 * BDs on chip but that there was adequate reservation.
4999 * provided by the TPA block.
5001 #define RX_TPA_END_CMPL_ERRORS_BUFFER_ERROR_NOT_ON_CHIP \
5002 (UINT32_C(0x2) << 1)
5004 * This error occurs when TPA block was not configured to
5005 * reserve adequate BDs for TPA operations on this RX
5006 * ring. All data for the TPA operation was not placed.
5008 * This error can also be generated when the number of
5009 * segments is not programmed correctly in TPA and the
5010 * 33 total aggregation buffers allowed for the TPA
5011 * operation has been exceeded.
5013 #define RX_TPA_END_CMPL_ERRORS_BUFFER_ERROR_RSV_ERROR \
5014 (UINT32_C(0x4) << 1)
5015 #define RX_TPA_END_CMPL_ERRORS_BUFFER_ERROR_LAST \
5016 RX_TPA_END_CMPL_ERRORS_BUFFER_ERROR_RSV_ERROR
5017 /* unused5 is 16 b */
5020 * This is the opaque value that was completed for the TPA start
5021 * completion that corresponds to this TPA end completion.
5023 uint32_t start_opaque;
5027 * This TPA completion structure is used on devices where the
5028 * `hwrm_vnic_qcaps.max_aggs_supported` value is greater than 0.
5030 /* rx_tpa_v2_start_cmpl (size:128b/16B) */
5031 struct rx_tpa_v2_start_cmpl {
5032 uint16_t flags_type;
5034 * This field indicates the exact type of the completion.
5035 * By convention, the LSB identifies the length of the
5036 * record in 16B units. Even values indicate 16B
5037 * records. Odd values indicate 32B
5040 #define RX_TPA_V2_START_CMPL_TYPE_MASK \
5042 #define RX_TPA_V2_START_CMPL_TYPE_SFT 0
5044 * RX L2 TPA Start Completion:
5045 * Completion at the beginning of a TPA operation.
5048 #define RX_TPA_V2_START_CMPL_TYPE_RX_TPA_START \
5050 #define RX_TPA_V2_START_CMPL_TYPE_LAST \
5051 RX_TPA_V2_START_CMPL_TYPE_RX_TPA_START
5052 #define RX_TPA_V2_START_CMPL_FLAGS_MASK \
5054 #define RX_TPA_V2_START_CMPL_FLAGS_SFT 6
5055 /* This bit will always be '0' for TPA start completions. */
5056 #define RX_TPA_V2_START_CMPL_FLAGS_ERROR \
5058 /* This field indicates how the packet was placed in the buffer. */
5059 #define RX_TPA_V2_START_CMPL_FLAGS_PLACEMENT_MASK \
5061 #define RX_TPA_V2_START_CMPL_FLAGS_PLACEMENT_SFT 7
5064 * TPA Packet was placed using jumbo algorithm. This means
5065 * that the first buffer will be filled with data before
5066 * moving to aggregation buffers. Each aggregation buffer
5067 * will be filled before moving to the next aggregation
5070 #define RX_TPA_V2_START_CMPL_FLAGS_PLACEMENT_JUMBO \
5071 (UINT32_C(0x1) << 7)
5073 * Header/Data Separation:
5074 * Packet was placed using Header/Data separation algorithm.
5075 * The separation location is indicated by the itype field.
5077 #define RX_TPA_V2_START_CMPL_FLAGS_PLACEMENT_HDS \
5078 (UINT32_C(0x2) << 7)
5081 * Packet will be placed using GRO/Jumbo where the first
5082 * packet is filled with data. Subsequent packets will be
5083 * placed such that any one packet does not span two
5084 * aggregation buffers unless it starts at the beginning of
5085 * an aggregation buffer.
5087 #define RX_TPA_V2_START_CMPL_FLAGS_PLACEMENT_GRO_JUMBO \
5088 (UINT32_C(0x5) << 7)
5090 * GRO/Header-Data Separation:
5091 * Packet will be placed using GRO/HDS where the header
5092 * is in the first packet.
5093 * Payload of each packet will be
5094 * placed such that any one packet does not span two
5095 * aggregation buffers unless it starts at the beginning of
5096 * an aggregation buffer.
5098 #define RX_TPA_V2_START_CMPL_FLAGS_PLACEMENT_GRO_HDS \
5099 (UINT32_C(0x6) << 7)
5100 #define RX_TPA_V2_START_CMPL_FLAGS_PLACEMENT_LAST \
5101 RX_TPA_V2_START_CMPL_FLAGS_PLACEMENT_GRO_HDS
5102 /* This bit is '1' if the RSS field in this completion is valid. */
5103 #define RX_TPA_V2_START_CMPL_FLAGS_RSS_VALID \
5106 * For devices that support timestamps, when this bit is cleared the
5107 * `inner_l4_size_inner_l3_offset_inner_l2_offset_outer_l3_offset`
5108 * field contains the 32b timestamp for
5109 * the packet from the MAC. When this bit is set, the
5110 * `inner_l4_size_inner_l3_offset_inner_l2_offset_outer_l3_offset`
5111 * field contains the outer_l3_offset, inner_l2_offset,
5112 * inner_l3_offset, and inner_l4_size.
5114 #define RX_TPA_V2_START_CMPL_FLAGS_TIMESTAMP_FLD_FORMAT \
5117 * This value indicates what the inner packet determined for the
5120 #define RX_TPA_V2_START_CMPL_FLAGS_ITYPE_MASK \
5122 #define RX_TPA_V2_START_CMPL_FLAGS_ITYPE_SFT 12
5125 * Indicates that the packet was IP and TCP.
5127 #define RX_TPA_V2_START_CMPL_FLAGS_ITYPE_TCP \
5128 (UINT32_C(0x2) << 12)
5129 #define RX_TPA_V2_START_CMPL_FLAGS_ITYPE_LAST \
5130 RX_TPA_V2_START_CMPL_FLAGS_ITYPE_TCP
5132 * This value indicates the amount of packet data written to the
5133 * buffer the opaque field in this completion corresponds to.
5137 * This is a copy of the opaque field from the RX BD this completion
5142 * This value is written by the NIC such that it will be different
5143 * for each pass through the completion queue. The even passes
5144 * will write 1. The odd passes will write 0.
5148 * This value is written by the NIC such that it will be different
5149 * for each pass through the completion queue. The even passes
5150 * will write 1. The odd passes will write 0.
5152 #define RX_TPA_V2_START_CMPL_V1 UINT32_C(0x1)
5153 #define RX_TPA_V2_START_CMPL_LAST RX_TPA_V2_START_CMPL_V1
5155 * This is the RSS hash type for the packet. The value is packed
5156 * {tuple_extrac_op[1:0],rss_profile_id[4:0],tuple_extrac_op[2]}.
5158 * The value of tuple_extrac_op provides the information about
5159 * what fields the hash was computed on.
5160 * * 0: The RSS hash was computed over source IP address,
5161 * destination IP address, source port, and destination port of inner
5162 * IP and TCP or UDP headers. Note: For non-tunneled packets,
5163 * the packet headers are considered inner packet headers for the RSS
5164 * hash computation purpose.
5165 * * 1: The RSS hash was computed over source IP address and destination
5166 * IP address of inner IP header. Note: For non-tunneled packets,
5167 * the packet headers are considered inner packet headers for the RSS
5168 * hash computation purpose.
5169 * * 2: The RSS hash was computed over source IP address,
5170 * destination IP address, source port, and destination port of
5171 * IP and TCP or UDP headers of outer tunnel headers.
5172 * Note: For non-tunneled packets, this value is not applicable.
5173 * * 3: The RSS hash was computed over source IP address and
5174 * destination IP address of IP header of outer tunnel headers.
5175 * Note: For non-tunneled packets, this value is not applicable.
5177 * Note that 4-tuples values listed above are applicable
5178 * for layer 4 protocols supported and enabled for RSS in the hardware,
5179 * HWRM firmware, and drivers. For example, if RSS hash is supported and
5180 * enabled for TCP traffic only, then the values of tuple_extract_op
5181 * corresponding to 4-tuples are only valid for TCP traffic.
5183 uint8_t rss_hash_type;
5185 * This is the aggregation ID that the completion is associated
5186 * with. Use this number to correlate the TPA start completion
5187 * with the TPA end completion.
5191 * This value is the RSS hash value calculated for the packet
5192 * based on the mode bits and key value in the VNIC.
5198 * Last 16 bytes of rx_tpa_v2_start_cmpl.
5200 * This TPA completion structure is used on devices where the
5201 * `hwrm_vnic_qcaps.max_aggs_supported` value is greater than 0.
5203 /* rx_tpa_v2_start_cmpl_hi (size:128b/16B) */
5204 struct rx_tpa_v2_start_cmpl_hi {
5207 * This indicates that the ip checksum was calculated for the
5208 * inner packet and that the sum passed for all segments
5209 * included in the aggregation.
5211 #define RX_TPA_V2_START_CMPL_FLAGS2_IP_CS_CALC \
5214 * This indicates that the TCP, UDP or ICMP checksum was
5215 * calculated for the inner packet and that the sum passed
5216 * for all segments included in the aggregation.
5218 #define RX_TPA_V2_START_CMPL_FLAGS2_L4_CS_CALC \
5221 * This indicates that the ip checksum was calculated for the
5222 * tunnel header and that the sum passed for all segments
5223 * included in the aggregation.
5225 #define RX_TPA_V2_START_CMPL_FLAGS2_T_IP_CS_CALC \
5228 * This indicates that the UDP checksum was
5229 * calculated for the tunnel packet and that the sum passed for
5230 * all segments included in the aggregation.
5232 #define RX_TPA_V2_START_CMPL_FLAGS2_T_L4_CS_CALC \
5234 /* This value indicates what format the metadata field is. */
5235 #define RX_TPA_V2_START_CMPL_FLAGS2_META_FORMAT_MASK \
5237 #define RX_TPA_V2_START_CMPL_FLAGS2_META_FORMAT_SFT 4
5238 /* No metadata informtaion. Value is zero. */
5239 #define RX_TPA_V2_START_CMPL_FLAGS2_META_FORMAT_NONE \
5240 (UINT32_C(0x0) << 4)
5242 * The metadata field contains the VLAN tag and TPID value.
5243 * - metadata[11:0] contains the vlan VID value.
5244 * - metadata[12] contains the vlan DE value.
5245 * - metadata[15:13] contains the vlan PRI value.
5246 * - metadata[31:16] contains the vlan TPID value.
5248 #define RX_TPA_V2_START_CMPL_FLAGS2_META_FORMAT_VLAN \
5249 (UINT32_C(0x1) << 4)
5251 * If ext_meta_format is equal to 1, the metadata field
5252 * contains the lower 16b of the tunnel ID value, justified
5254 * - VXLAN = VNI[23:0] -> VXLAN Network ID
5255 * - Geneve (NGE) = VNI[23:0] a-> Virtual Network Identifier.
5256 * - NVGRE = TNI[23:0] -> Tenant Network ID
5257 * - GRE = KEY[31:0 -> key fieled with bit mask. zero if K = 0
5258 * - IPV4 = 0 (not populated)
5259 * - IPV6 = Flow Label[19:0]
5260 * - PPPoE = sessionID[15:0]
5261 * - MPLs = Outer label[19:0]
5262 * - UPAR = Selected[31:0] with bit mask
5264 #define RX_TPA_V2_START_CMPL_FLAGS2_META_FORMAT_TUNNEL_ID \
5265 (UINT32_C(0x2) << 4)
5267 * if ext_meta_format is equal to 1, metadata field contains
5268 * 16b metadata from the prepended header (chdr_data).
5270 #define RX_TPA_V2_START_CMPL_FLAGS2_META_FORMAT_CHDR_DATA \
5271 (UINT32_C(0x3) << 4)
5273 * If ext_meta_format is equal to 1, the metadata field contains
5274 * the outer_l3_offset, inner_l2_offset, inner_l3_offset and
5276 * - metadata[8:0] contains the outer_l3_offset.
5277 * - metadata[17:9] contains the inner_l2_offset.
5278 * - metadata[26:18] contains the inner_l3_offset.
5279 * - metadata[31:27] contains the inner_l4_size.
5281 #define RX_TPA_V2_START_CMPL_FLAGS2_META_FORMAT_HDR_OFFSET \
5282 (UINT32_C(0x4) << 4)
5283 #define RX_TPA_V2_START_CMPL_FLAGS2_META_FORMAT_LAST \
5284 RX_TPA_V2_START_CMPL_FLAGS2_META_FORMAT_HDR_OFFSET
5286 * This field indicates the IP type for the inner-most IP header.
5287 * A value of '0' indicates IPv4. A value of '1' indicates IPv6.
5289 #define RX_TPA_V2_START_CMPL_FLAGS2_IP_TYPE \
5292 * This indicates that the complete 1's complement checksum was
5293 * calculated for the packet.
5295 #define RX_TPA_V2_START_CMPL_FLAGS2_COMPLETE_CHECKSUM_CALC \
5298 * The combination of this value and meta_format indicated what
5299 * format the metadata field is.
5301 #define RX_TPA_V2_START_CMPL_FLAGS2_EXT_META_FORMAT_MASK \
5303 #define RX_TPA_V2_START_CMPL_FLAGS2_EXT_META_FORMAT_SFT 10
5305 * This value is the complete 1's complement checksum calculated from
5306 * the start of the outer L3 header to the end of the packet (not
5307 * including the ethernet crc). It is valid when the
5308 * 'complete_checksum_calc' flag is set. For TPA Start completions,
5309 * the complete checksum is calculated for the first packet in the
5312 #define RX_TPA_V2_START_CMPL_FLAGS2_COMPLETE_CHECKSUM_MASK \
5313 UINT32_C(0xffff0000)
5314 #define RX_TPA_V2_START_CMPL_FLAGS2_COMPLETE_CHECKSUM_SFT 16
5316 * This is data from the CFA block as indicated by the meta_format
5320 /* When {ext_meta_format,meta_format}=1, this value is the VLAN VID. */
5321 #define RX_TPA_V2_START_CMPL_METADATA_VID_MASK UINT32_C(0xfff)
5322 #define RX_TPA_V2_START_CMPL_METADATA_VID_SFT 0
5323 /* When {ext_meta_format,meta_format}=1, this value is the VLAN DE. */
5324 #define RX_TPA_V2_START_CMPL_METADATA_DE UINT32_C(0x1000)
5325 /* When {ext_meta_format,meta_format}=1, this value is the VLAN PRI. */
5326 #define RX_TPA_V2_START_CMPL_METADATA_PRI_MASK UINT32_C(0xe000)
5327 #define RX_TPA_V2_START_CMPL_METADATA_PRI_SFT 13
5328 /* When {ext_meta_format,meta_format}=1, this value is the VLAN TPID. */
5329 #define RX_TPA_V2_START_CMPL_METADATA_TPID_MASK UINT32_C(0xffff0000)
5330 #define RX_TPA_V2_START_CMPL_METADATA_TPID_SFT 16
5333 * This value is written by the NIC such that it will be different
5334 * for each pass through the completion queue. The even passes
5335 * will write 1. The odd passes will write 0.
5337 #define RX_TPA_V2_START_CMPL_V2 \
5339 #define RX_TPA_V2_START_CMPL_ERRORS_MASK \
5341 #define RX_TPA_V2_START_CMPL_ERRORS_SFT 1
5343 * This error indicates that there was some sort of problem with
5344 * the BDs for the packet that was found after part of the
5345 * packet was already placed. The packet should be treated as
5348 #define RX_TPA_V2_START_CMPL_ERRORS_BUFFER_ERROR_MASK \
5350 #define RX_TPA_V2_START_CMPL_ERRORS_BUFFER_ERROR_SFT 1
5351 /* No buffer error */
5352 #define RX_TPA_V2_START_CMPL_ERRORS_BUFFER_ERROR_NO_BUFFER \
5353 (UINT32_C(0x0) << 1)
5356 * BDs were not formatted correctly.
5358 #define RX_TPA_V2_START_CMPL_ERRORS_BUFFER_ERROR_BAD_FORMAT \
5359 (UINT32_C(0x3) << 1)
5362 * There was a bad_format error on the previous operation
5364 #define RX_TPA_V2_START_CMPL_ERRORS_BUFFER_ERROR_FLUSH \
5365 (UINT32_C(0x5) << 1)
5366 #define RX_TPA_V2_START_CMPL_ERRORS_BUFFER_ERROR_LAST \
5367 RX_TPA_V2_START_CMPL_ERRORS_BUFFER_ERROR_FLUSH
5369 * This field identifies the CFA action rule that was used for this
5374 * For devices that support timestamps this field is overridden
5375 * with the timestamp value. When `flags.timestamp_fld_format` is
5376 * cleared, this field contains the 32b timestamp for the packet from the
5379 * When `flags.timestamp_fld_format` is set, this field contains the
5380 * outer_l3_offset, inner_l2_offset, inner_l3_offset, and inner_l4_size
5383 uint32_t inner_l4_size_inner_l3_offset_inner_l2_offset_outer_l3_offset;
5385 * This is the offset from the beginning of the packet in bytes for
5386 * the outer L3 header. If there is no outer L3 header, then this
5389 #define RX_TPA_V2_START_CMPL_OUTER_L3_OFFSET_MASK UINT32_C(0x1ff)
5390 #define RX_TPA_V2_START_CMPL_OUTER_L3_OFFSET_SFT 0
5392 * This is the offset from the beginning of the packet in bytes for
5393 * the inner most L2 header.
5395 #define RX_TPA_V2_START_CMPL_INNER_L2_OFFSET_MASK UINT32_C(0x3fe00)
5396 #define RX_TPA_V2_START_CMPL_INNER_L2_OFFSET_SFT 9
5398 * This is the offset from the beginning of the packet in bytes for
5399 * the inner most L3 header.
5401 #define RX_TPA_V2_START_CMPL_INNER_L3_OFFSET_MASK UINT32_C(0x7fc0000)
5402 #define RX_TPA_V2_START_CMPL_INNER_L3_OFFSET_SFT 18
5404 * This is the size in bytes of the inner most L4 header.
5405 * This can be subtracted from the payload_offset to determine
5406 * the start of the inner most L4 header.
5408 #define RX_TPA_V2_START_CMPL_INNER_L4_SIZE_MASK UINT32_C(0xf8000000)
5409 #define RX_TPA_V2_START_CMPL_INNER_L4_SIZE_SFT 27
5413 * This TPA completion structure is used on devices where the
5414 * `hwrm_vnic_qcaps.max_aggs_supported` value is greater than 0.
5416 /* rx_tpa_v2_end_cmpl (size:128b/16B) */
5417 struct rx_tpa_v2_end_cmpl {
5418 uint16_t flags_type;
5420 * This field indicates the exact type of the completion.
5421 * By convention, the LSB identifies the length of the
5422 * record in 16B units. Even values indicate 16B
5423 * records. Odd values indicate 32B
5426 #define RX_TPA_V2_END_CMPL_TYPE_MASK UINT32_C(0x3f)
5427 #define RX_TPA_V2_END_CMPL_TYPE_SFT 0
5429 * RX L2 TPA End Completion:
5430 * Completion at the end of a TPA operation.
5433 #define RX_TPA_V2_END_CMPL_TYPE_RX_TPA_END UINT32_C(0x15)
5434 #define RX_TPA_V2_END_CMPL_TYPE_LAST \
5435 RX_TPA_V2_END_CMPL_TYPE_RX_TPA_END
5436 #define RX_TPA_V2_END_CMPL_FLAGS_MASK UINT32_C(0xffc0)
5437 #define RX_TPA_V2_END_CMPL_FLAGS_SFT 6
5439 * When this bit is '1', it indicates a packet that has an
5440 * error of some type. Type of error is indicated in
5443 #define RX_TPA_V2_END_CMPL_FLAGS_ERROR UINT32_C(0x40)
5444 /* This field indicates how the packet was placed in the buffer. */
5445 #define RX_TPA_V2_END_CMPL_FLAGS_PLACEMENT_MASK UINT32_C(0x380)
5446 #define RX_TPA_V2_END_CMPL_FLAGS_PLACEMENT_SFT 7
5449 * TPA Packet was placed using jumbo algorithm. This means
5450 * that the first buffer will be filled with data before
5451 * moving to aggregation buffers. Each aggregation buffer
5452 * will be filled before moving to the next aggregation
5455 #define RX_TPA_V2_END_CMPL_FLAGS_PLACEMENT_JUMBO \
5456 (UINT32_C(0x1) << 7)
5458 * Header/Data Separation:
5459 * Packet was placed using Header/Data separation algorithm.
5460 * The separation location is indicated by the itype field.
5462 #define RX_TPA_V2_END_CMPL_FLAGS_PLACEMENT_HDS \
5463 (UINT32_C(0x2) << 7)
5466 * Packet will be placed using GRO/Jumbo where the first
5467 * packet is filled with data. Subsequent packets will be
5468 * placed such that any one packet does not span two
5469 * aggregation buffers unless it starts at the beginning of
5470 * an aggregation buffer.
5472 #define RX_TPA_V2_END_CMPL_FLAGS_PLACEMENT_GRO_JUMBO \
5473 (UINT32_C(0x5) << 7)
5475 * GRO/Header-Data Separation:
5476 * Packet will be placed using GRO/HDS where the header
5477 * is in the first packet.
5478 * Payload of each packet will be
5479 * placed such that any one packet does not span two
5480 * aggregation buffers unless it starts at the beginning of
5481 * an aggregation buffer.
5483 #define RX_TPA_V2_END_CMPL_FLAGS_PLACEMENT_GRO_HDS \
5484 (UINT32_C(0x6) << 7)
5485 #define RX_TPA_V2_END_CMPL_FLAGS_PLACEMENT_LAST \
5486 RX_TPA_V2_END_CMPL_FLAGS_PLACEMENT_GRO_HDS
5488 #define RX_TPA_V2_END_CMPL_FLAGS_UNUSED_MASK UINT32_C(0xc00)
5489 #define RX_TPA_V2_END_CMPL_FLAGS_UNUSED_SFT 10
5491 * This value indicates what the inner packet determined for the
5494 * Indicates that the packet was IP and TCP. This indicates
5495 * that the ip_cs field is valid and that the tcp_udp_cs
5496 * field is valid and contains the TCP checksum.
5497 * This also indicates that the payload_offset field is valid.
5499 #define RX_TPA_V2_END_CMPL_FLAGS_ITYPE_MASK UINT32_C(0xf000)
5500 #define RX_TPA_V2_END_CMPL_FLAGS_ITYPE_SFT 12
5502 * This value is zero for TPA End completions.
5503 * There is no data in the buffer that corresponds to the opaque
5504 * value in this completion.
5508 * This is a copy of the opaque field from the RX BD this completion
5514 * This value is written by the NIC such that it will be different
5515 * for each pass through the completion queue. The even passes
5516 * will write 1. The odd passes will write 0.
5518 #define RX_TPA_V2_END_CMPL_V1 UINT32_C(0x1)
5519 /* This value is the number of segments in the TPA operation. */
5522 * This is the aggregation ID that the completion is associated
5523 * with. Use this number to correlate the TPA start completion
5524 * with the TPA end completion.
5528 * For non-GRO packets, this value is the
5529 * timestamp delta between earliest and latest timestamp values for
5530 * TPA packet. If packets were not time stamped, then delta will be
5533 * For GRO packets, this field is zero except for the following
5536 * Timestamp present indication. When '0', no Timestamp
5537 * option is in the packet. When '1', then a Timestamp
5538 * option is present in the packet.
5544 * Last 16 bytes of rx_tpa_v2_end_cmpl.
5546 * This TPA completion structure is used on devices where the
5547 * `hwrm_vnic_qcaps.max_aggs_supported` value is greater than 0.
5549 /* rx_tpa_v2_end_cmpl_hi (size:128b/16B) */
5550 struct rx_tpa_v2_end_cmpl_hi {
5552 * This value is the number of duplicate ACKs that have been
5553 * received as part of the TPA operation.
5555 uint16_t tpa_dup_acks;
5557 * This value is the number of duplicate ACKs that have been
5558 * received as part of the TPA operation.
5560 #define RX_TPA_V2_END_CMPL_TPA_DUP_ACKS_MASK UINT32_C(0xf)
5561 #define RX_TPA_V2_END_CMPL_TPA_DUP_ACKS_SFT 0
5563 * This value indicated the offset in bytes from the beginning of
5564 * the packet where the inner payload starts. This value is valid
5565 * for TCP, UDP, FCoE and RoCE packets
5567 uint8_t payload_offset;
5569 * The value is the total number of aggregation buffers that were
5570 * used in the TPA operation. All TPA aggregation buffer completions
5571 * precede the TPA End completion. If the value is zero, then the
5572 * aggregation is completely contained in the buffer space provided
5573 * in the aggregation start completion.
5574 * Note that the field is simply provided as a cross check.
5576 uint8_t tpa_agg_bufs;
5578 * This value is the valid when TPA completion is active. It
5579 * indicates the length of the longest segment of the TPA operation
5580 * for LRO mode and the length of the first segment in GRO mode.
5582 * This value may be used by GRO software to re-construct the original
5583 * packet stream from the TPA packet. This is the length of all
5584 * but the last segment for GRO. In LRO mode this value may be used
5585 * to indicate MSS size to the stack.
5587 uint16_t tpa_seg_len;
5591 * This value is written by the NIC such that it will be different
5592 * for each pass through the completion queue. The even passes
5593 * will write 1. The odd passes will write 0.
5595 #define RX_TPA_V2_END_CMPL_V2 UINT32_C(0x1)
5596 #define RX_TPA_V2_END_CMPL_ERRORS_MASK \
5598 #define RX_TPA_V2_END_CMPL_ERRORS_SFT 1
5600 * This error indicates that there was some sort of problem with
5601 * the BDs for the packet that was found after part of the
5602 * packet was already placed. The packet should be treated as
5605 #define RX_TPA_V2_END_CMPL_ERRORS_BUFFER_ERROR_MASK \
5607 #define RX_TPA_V2_END_CMPL_ERRORS_BUFFER_ERROR_SFT 1
5608 /* No buffer error */
5609 #define RX_TPA_V2_END_CMPL_ERRORS_BUFFER_ERROR_NO_BUFFER \
5610 (UINT32_C(0x0) << 1)
5612 * This error occurs when there is a fatal HW problem in
5613 * the chip only. It indicates that there were not
5614 * BDs on chip but that there was adequate reservation.
5615 * provided by the TPA block.
5617 #define RX_TPA_V2_END_CMPL_ERRORS_BUFFER_ERROR_NOT_ON_CHIP \
5618 (UINT32_C(0x2) << 1)
5621 * BDs were not formatted correctly.
5623 #define RX_TPA_V2_END_CMPL_ERRORS_BUFFER_ERROR_BAD_FORMAT \
5624 (UINT32_C(0x3) << 1)
5626 * This error occurs when TPA block was not configured to
5627 * reserve adequate BDs for TPA operations on this RX
5628 * ring. All data for the TPA operation was not placed.
5630 * This error can also be generated when the number of
5631 * segments is not programmed correctly in TPA and the
5632 * 33 total aggregation buffers allowed for the TPA
5633 * operation has been exceeded.
5635 #define RX_TPA_V2_END_CMPL_ERRORS_BUFFER_ERROR_RSV_ERROR \
5636 (UINT32_C(0x4) << 1)
5639 * There was a bad_format error on the previous operation
5641 #define RX_TPA_V2_END_CMPL_ERRORS_BUFFER_ERROR_FLUSH \
5642 (UINT32_C(0x5) << 1)
5643 #define RX_TPA_V2_END_CMPL_ERRORS_BUFFER_ERROR_LAST \
5644 RX_TPA_V2_END_CMPL_ERRORS_BUFFER_ERROR_FLUSH
5647 * This is the opaque value that was completed for the TPA start
5648 * completion that corresponds to this TPA end completion.
5650 uint32_t start_opaque;
5654 * This TPA completion structure is used on devices where the
5655 * `hwrm_vnic_qcaps.max_aggs_supported` value is greater than 0.
5657 /* rx_tpa_v2_abuf_cmpl (size:128b/16B) */
5658 struct rx_tpa_v2_abuf_cmpl {
5661 * This field indicates the exact type of the completion.
5662 * By convention, the LSB identifies the length of the
5663 * record in 16B units. Even values indicate 16B
5664 * records. Odd values indicate 32B
5667 #define RX_TPA_V2_ABUF_CMPL_TYPE_MASK UINT32_C(0x3f)
5668 #define RX_TPA_V2_ABUF_CMPL_TYPE_SFT 0
5670 * RX TPA Aggregation Buffer completion :
5671 * Completion of an L2 aggregation buffer in support of
5672 * TPA packet completion. Length = 16B
5674 #define RX_TPA_V2_ABUF_CMPL_TYPE_RX_TPA_AGG UINT32_C(0x16)
5675 #define RX_TPA_V2_ABUF_CMPL_TYPE_LAST \
5676 RX_TPA_V2_ABUF_CMPL_TYPE_RX_TPA_AGG
5678 * This is the length of the data for the packet stored in this
5679 * aggregation buffer identified by the opaque value. This does not
5680 * include the length of any
5681 * data placed in other aggregation BDs or in the packet or buffer
5682 * BDs. This length does not include any space added due to
5683 * hdr_offset register during HDS placement mode.
5687 * This is a copy of the opaque field from the RX BD this aggregation
5688 * buffer corresponds to.
5693 * This value is written by the NIC such that it will be different
5694 * for each pass through the completion queue. The even passes
5695 * will write 1. The odd passes will write 0.
5697 #define RX_TPA_V2_ABUF_CMPL_V UINT32_C(0x1)
5699 * This is the aggregation ID that the completion is associated with. Use
5700 * this number to correlate the TPA agg completion with the TPA start
5701 * completion and the TPA end completion.
5707 /* rx_abuf_cmpl (size:128b/16B) */
5708 struct rx_abuf_cmpl {
5711 * This field indicates the exact type of the completion.
5712 * By convention, the LSB identifies the length of the
5713 * record in 16B units. Even values indicate 16B
5714 * records. Odd values indicate 32B
5717 #define RX_ABUF_CMPL_TYPE_MASK UINT32_C(0x3f)
5718 #define RX_ABUF_CMPL_TYPE_SFT 0
5720 * RX Aggregation Buffer completion :
5721 * Completion of an L2 aggregation buffer in support of
5722 * TPA, HDS, or Jumbo packet completion. Length = 16B
5724 #define RX_ABUF_CMPL_TYPE_RX_AGG UINT32_C(0x12)
5725 #define RX_ABUF_CMPL_TYPE_LAST RX_ABUF_CMPL_TYPE_RX_AGG
5727 * This is the length of the data for the packet stored in this
5728 * aggregation buffer identified by the opaque value. This does not
5729 * include the length of any
5730 * data placed in other aggregation BDs or in the packet or buffer
5731 * BDs. This length does not include any space added due to
5732 * hdr_offset register during HDS placement mode.
5736 * This is a copy of the opaque field from the RX BD this aggregation
5737 * buffer corresponds to.
5742 * This value is written by the NIC such that it will be different
5743 * for each pass through the completion queue. The even passes
5744 * will write 1. The odd passes will write 0.
5746 #define RX_ABUF_CMPL_V UINT32_C(0x1)
5747 /* unused3 is 32 b */
5751 /* VEE FLUSH Completion Record (16 bytes) */
5752 /* vee_flush (size:128b/16B) */
5754 uint32_t downstream_path_type;
5756 * This field indicates the exact type of the completion.
5757 * By convention, the LSB identifies the length of the
5758 * record in 16B units. Even values indicate 16B
5759 * records. Odd values indicate 32B
5762 #define VEE_FLUSH_TYPE_MASK UINT32_C(0x3f)
5763 #define VEE_FLUSH_TYPE_SFT 0
5765 * VEE Flush Completion:
5766 * This completion is inserted manually by the Primate and processed
5767 * by the VEE hardware to ensure that all completions on a VEE
5768 * function have been processed by the VEE hardware before FLR
5769 * process is completed.
5771 #define VEE_FLUSH_TYPE_VEE_FLUSH UINT32_C(0x1c)
5772 #define VEE_FLUSH_TYPE_LAST VEE_FLUSH_TYPE_VEE_FLUSH
5773 /* downstream_path is 1 b */
5774 #define VEE_FLUSH_DOWNSTREAM_PATH UINT32_C(0x40)
5775 /* This completion is associated with VEE Transmit */
5776 #define VEE_FLUSH_DOWNSTREAM_PATH_TX (UINT32_C(0x0) << 6)
5777 /* This completion is associated with VEE Receive */
5778 #define VEE_FLUSH_DOWNSTREAM_PATH_RX (UINT32_C(0x1) << 6)
5779 #define VEE_FLUSH_DOWNSTREAM_PATH_LAST VEE_FLUSH_DOWNSTREAM_PATH_RX
5781 * This is an opaque value that is passed through the completion
5782 * to the VEE handler SW and is used to indicate what VEE VQ or
5783 * function has completed FLR processing.
5788 * This value is written by the NIC such that it will be different
5789 * for each pass through the completion queue. The even passes will
5790 * write 1. The odd passes will write 0.
5792 #define VEE_FLUSH_V UINT32_C(0x1)
5793 /* unused3 is 32 b */
5797 /* eject_cmpl (size:128b/16B) */
5801 * This field indicates the exact type of the completion.
5802 * By convention, the LSB identifies the length of the
5803 * record in 16B units. Even values indicate 16B
5804 * records. Odd values indicate 32B
5807 #define EJECT_CMPL_TYPE_MASK UINT32_C(0x3f)
5808 #define EJECT_CMPL_TYPE_SFT 0
5810 * Statistics Ejection Completion:
5811 * Completion of statistics data ejection buffer.
5814 #define EJECT_CMPL_TYPE_STAT_EJECT UINT32_C(0x1a)
5815 #define EJECT_CMPL_TYPE_LAST EJECT_CMPL_TYPE_STAT_EJECT
5816 #define EJECT_CMPL_FLAGS_MASK UINT32_C(0xffc0)
5817 #define EJECT_CMPL_FLAGS_SFT 6
5819 * When this bit is '1', it indicates a packet that has an
5820 * error of some type. Type of error is indicated in
5823 #define EJECT_CMPL_FLAGS_ERROR UINT32_C(0x40)
5825 * This is the length of the statistics data stored in this
5830 * This is a copy of the opaque field from the RX BD this ejection
5831 * buffer corresponds to.
5836 * This value is written by the NIC such that it will be different
5837 * for each pass through the completion queue. The even passes
5838 * will write 1. The odd passes will write 0.
5840 #define EJECT_CMPL_V UINT32_C(0x1)
5841 #define EJECT_CMPL_ERRORS_MASK UINT32_C(0xfffe)
5842 #define EJECT_CMPL_ERRORS_SFT 1
5844 * This error indicates that there was some sort of problem with
5845 * the BDs for statistics ejection. The statistics ejection should
5846 * be treated as invalid
5848 #define EJECT_CMPL_ERRORS_BUFFER_ERROR_MASK UINT32_C(0xe)
5849 #define EJECT_CMPL_ERRORS_BUFFER_ERROR_SFT 1
5850 /* No buffer error */
5851 #define EJECT_CMPL_ERRORS_BUFFER_ERROR_NO_BUFFER \
5852 (UINT32_C(0x0) << 1)
5855 * Statistics did not fit into aggregation buffer provided.
5857 #define EJECT_CMPL_ERRORS_BUFFER_ERROR_DID_NOT_FIT \
5858 (UINT32_C(0x1) << 1)
5861 * BDs were not formatted correctly.
5863 #define EJECT_CMPL_ERRORS_BUFFER_ERROR_BAD_FORMAT \
5864 (UINT32_C(0x3) << 1)
5867 * There was a bad_format error on the previous operation
5869 #define EJECT_CMPL_ERRORS_BUFFER_ERROR_FLUSH \
5870 (UINT32_C(0x5) << 1)
5871 #define EJECT_CMPL_ERRORS_BUFFER_ERROR_LAST \
5872 EJECT_CMPL_ERRORS_BUFFER_ERROR_FLUSH
5873 /* reserved16 is 16 b */
5874 uint16_t reserved16;
5875 /* unused3 is 32 b */
5879 /* hwrm_cmpl (size:128b/16B) */
5883 * This field indicates the exact type of the completion.
5884 * By convention, the LSB identifies the length of the
5885 * record in 16B units. Even values indicate 16B
5886 * records. Odd values indicate 32B
5889 #define HWRM_CMPL_TYPE_MASK UINT32_C(0x3f)
5890 #define HWRM_CMPL_TYPE_SFT 0
5892 * HWRM Command Completion:
5893 * Completion of an HWRM command.
5895 #define HWRM_CMPL_TYPE_HWRM_DONE UINT32_C(0x20)
5896 #define HWRM_CMPL_TYPE_LAST HWRM_CMPL_TYPE_HWRM_DONE
5897 /* This is the sequence_id of the HWRM command that has completed. */
5898 uint16_t sequence_id;
5899 /* unused2 is 32 b */
5903 * This value is written by the NIC such that it will be different
5904 * for each pass through the completion queue. The even passes
5905 * will write 1. The odd passes will write 0.
5907 #define HWRM_CMPL_V UINT32_C(0x1)
5908 /* unused4 is 32 b */
5912 /* hwrm_fwd_req_cmpl (size:128b/16B) */
5913 struct hwrm_fwd_req_cmpl {
5915 * This field indicates the exact type of the completion.
5916 * By convention, the LSB identifies the length of the
5917 * record in 16B units. Even values indicate 16B
5918 * records. Odd values indicate 32B
5921 uint16_t req_len_type;
5923 * This field indicates the exact type of the completion.
5924 * By convention, the LSB identifies the length of the
5925 * record in 16B units. Even values indicate 16B
5926 * records. Odd values indicate 32B
5929 #define HWRM_FWD_REQ_CMPL_TYPE_MASK UINT32_C(0x3f)
5930 #define HWRM_FWD_REQ_CMPL_TYPE_SFT 0
5931 /* Forwarded HWRM Request */
5932 #define HWRM_FWD_REQ_CMPL_TYPE_HWRM_FWD_REQ UINT32_C(0x22)
5933 #define HWRM_FWD_REQ_CMPL_TYPE_LAST \
5934 HWRM_FWD_REQ_CMPL_TYPE_HWRM_FWD_REQ
5935 /* Length of forwarded request in bytes. */
5936 #define HWRM_FWD_REQ_CMPL_REQ_LEN_MASK UINT32_C(0xffc0)
5937 #define HWRM_FWD_REQ_CMPL_REQ_LEN_SFT 6
5939 * Source ID of this request.
5940 * Typically used in forwarding requests and responses.
5941 * 0x0 - 0xFFF8 - Used for function ids
5942 * 0xFFF8 - 0xFFFE - Reserved for internal processors
5946 /* unused1 is 32 b */
5948 /* Address of forwarded request. */
5949 uint32_t req_buf_addr_v[2];
5951 * This value is written by the NIC such that it will be different
5952 * for each pass through the completion queue. The even passes
5953 * will write 1. The odd passes will write 0.
5955 #define HWRM_FWD_REQ_CMPL_V UINT32_C(0x1)
5956 /* Address of forwarded request. */
5957 #define HWRM_FWD_REQ_CMPL_REQ_BUF_ADDR_MASK UINT32_C(0xfffffffe)
5958 #define HWRM_FWD_REQ_CMPL_REQ_BUF_ADDR_SFT 1
5961 /* hwrm_fwd_resp_cmpl (size:128b/16B) */
5962 struct hwrm_fwd_resp_cmpl {
5965 * This field indicates the exact type of the completion.
5966 * By convention, the LSB identifies the length of the
5967 * record in 16B units. Even values indicate 16B
5968 * records. Odd values indicate 32B
5971 #define HWRM_FWD_RESP_CMPL_TYPE_MASK UINT32_C(0x3f)
5972 #define HWRM_FWD_RESP_CMPL_TYPE_SFT 0
5973 /* Forwarded HWRM Response */
5974 #define HWRM_FWD_RESP_CMPL_TYPE_HWRM_FWD_RESP UINT32_C(0x24)
5975 #define HWRM_FWD_RESP_CMPL_TYPE_LAST \
5976 HWRM_FWD_RESP_CMPL_TYPE_HWRM_FWD_RESP
5978 * Source ID of this response.
5979 * Typically used in forwarding requests and responses.
5980 * 0x0 - 0xFFF8 - Used for function ids
5981 * 0xFFF8 - 0xFFFE - Reserved for internal processors
5985 /* Length of forwarded response in bytes. */
5987 /* unused2 is 16 b */
5989 /* Address of forwarded request. */
5990 uint32_t resp_buf_addr_v[2];
5992 * This value is written by the NIC such that it will be different
5993 * for each pass through the completion queue. The even passes
5994 * will write 1. The odd passes will write 0.
5996 #define HWRM_FWD_RESP_CMPL_V UINT32_C(0x1)
5997 /* Address of forwarded request. */
5998 #define HWRM_FWD_RESP_CMPL_RESP_BUF_ADDR_MASK UINT32_C(0xfffffffe)
5999 #define HWRM_FWD_RESP_CMPL_RESP_BUF_ADDR_SFT 1
6002 /* hwrm_async_event_cmpl (size:128b/16B) */
6003 struct hwrm_async_event_cmpl {
6006 * This field indicates the exact type of the completion.
6007 * By convention, the LSB identifies the length of the
6008 * record in 16B units. Even values indicate 16B
6009 * records. Odd values indicate 32B
6012 #define HWRM_ASYNC_EVENT_CMPL_TYPE_MASK UINT32_C(0x3f)
6013 #define HWRM_ASYNC_EVENT_CMPL_TYPE_SFT 0
6014 /* HWRM Asynchronous Event Information */
6015 #define HWRM_ASYNC_EVENT_CMPL_TYPE_HWRM_ASYNC_EVENT UINT32_C(0x2e)
6016 #define HWRM_ASYNC_EVENT_CMPL_TYPE_LAST \
6017 HWRM_ASYNC_EVENT_CMPL_TYPE_HWRM_ASYNC_EVENT
6018 /* Identifiers of events. */
6020 /* Link status changed */
6021 #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_LINK_STATUS_CHANGE \
6023 /* Link MTU changed */
6024 #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_LINK_MTU_CHANGE \
6026 /* Link speed changed */
6027 #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_LINK_SPEED_CHANGE \
6029 /* DCB Configuration changed */
6030 #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_DCB_CONFIG_CHANGE \
6032 /* Port connection not allowed */
6033 #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_PORT_CONN_NOT_ALLOWED \
6035 /* Link speed configuration was not allowed */
6036 #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_LINK_SPEED_CFG_NOT_ALLOWED \
6038 /* Link speed configuration change */
6039 #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_LINK_SPEED_CFG_CHANGE \
6041 /* Port PHY configuration change */
6042 #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_PORT_PHY_CFG_CHANGE \
6044 /* Reset notification to clients */
6045 #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_RESET_NOTIFY \
6047 /* Master function selection event */
6048 #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_ERROR_RECOVERY \
6050 /* Function driver unloaded */
6051 #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_FUNC_DRVR_UNLOAD \
6053 /* Function driver loaded */
6054 #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_FUNC_DRVR_LOAD \
6056 /* Function FLR related processing has completed */
6057 #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_FUNC_FLR_PROC_CMPLT \
6059 /* PF driver unloaded */
6060 #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_PF_DRVR_UNLOAD \
6062 /* PF driver loaded */
6063 #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_PF_DRVR_LOAD \
6065 /* VF Function Level Reset (FLR) */
6066 #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_VF_FLR \
6068 /* VF MAC Address Change */
6069 #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_VF_MAC_ADDR_CHANGE \
6071 /* PF-VF communication channel status change. */
6072 #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_PF_VF_COMM_STATUS_CHANGE \
6074 /* VF Configuration Change */
6075 #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_VF_CFG_CHANGE \
6077 /* LLFC/PFC Configuration Change */
6078 #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_LLFC_PFC_CHANGE \
6080 /* Default VNIC Configuration Change */
6081 #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_DEFAULT_VNIC_CHANGE \
6084 #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_HW_FLOW_AGED \
6087 * A debug notification being posted to the driver. These
6088 * notifications are purely for diagnostic purpose and should not be
6089 * used for functional purpose. The driver is not supposed to act
6090 * on these messages except to log/record it.
6092 #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_DEBUG_NOTIFICATION \
6095 * An EEM flow cached memory flush for all flows request event being
6096 * posted to the PF driver.
6098 #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_EEM_CACHE_FLUSH_REQ \
6101 * An EEM flow cache memory flush completion event being posted to the
6102 * firmware by the PF driver. This is indication that host EEM flush
6103 * has completed by the PF.
6105 #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_EEM_CACHE_FLUSH_DONE \
6108 * A tcp flag action change event being posted to the PF or trusted VF
6109 * driver by the firmware. The PF or trusted VF driver should query
6110 * the firmware for the new TCP flag action update after receiving
6113 #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_TCP_FLAG_ACTION_CHANGE \
6116 * An EEM flow active event being posted to the PF or trusted VF driver
6117 * by the firmware. The PF or trusted VF driver should update the
6118 * flow's aging timer after receiving this async event.
6120 #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_EEM_FLOW_ACTIVE \
6123 * A eem cfg change event being posted to the trusted VF driver by the
6124 * firmware if the parent PF EEM configuration changed.
6126 #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_EEM_CFG_CHANGE \
6130 * TFLIB unique default VNIC Configuration Change
6132 #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_TFLIB_DEFAULT_VNIC_CHANGE \
6136 * TFLIB unique link status changed
6138 #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_TFLIB_LINK_STATUS_CHANGE \
6141 * An event signifying completion for HWRM_FW_STATE_QUIESCE
6142 * (completion, timeout, or error)
6144 #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_QUIESCE_DONE \
6147 * An event signifying a HWRM command is in progress and its
6148 * response will be deferred. This event is used on crypto controllers
6151 #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_DEFERRED_RESPONSE \
6154 * An event signifying that a PFC WatchDog configuration
6155 * has changed on any port / cos.
6157 #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_PFC_WATCHDOG_CFG_CHANGE \
6160 * A trace log message. This contains firmware trace logs string
6161 * embedded in the asynchronous message. This is an experimental
6162 * event, not meant for production use at this time.
6164 #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_FW_TRACE_MSG \
6167 #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_HWRM_ERROR \
6169 #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_LAST \
6170 HWRM_ASYNC_EVENT_CMPL_EVENT_ID_HWRM_ERROR
6171 /* Event specific data */
6172 uint32_t event_data2;
6175 * This value is written by the NIC such that it will be different
6176 * for each pass through the completion queue. The even passes
6177 * will write 1. The odd passes will write 0.
6179 #define HWRM_ASYNC_EVENT_CMPL_V UINT32_C(0x1)
6181 #define HWRM_ASYNC_EVENT_CMPL_OPAQUE_MASK UINT32_C(0xfe)
6182 #define HWRM_ASYNC_EVENT_CMPL_OPAQUE_SFT 1
6183 /* 8-lsb timestamp from POR (100-msec resolution) */
6184 uint8_t timestamp_lo;
6185 /* 16-lsb timestamp from POR (100-msec resolution) */
6186 uint16_t timestamp_hi;
6187 /* Event specific data */
6188 uint32_t event_data1;
6191 /* hwrm_async_event_cmpl_link_status_change (size:128b/16B) */
6192 struct hwrm_async_event_cmpl_link_status_change {
6195 * This field indicates the exact type of the completion.
6196 * By convention, the LSB identifies the length of the
6197 * record in 16B units. Even values indicate 16B
6198 * records. Odd values indicate 32B
6201 #define HWRM_ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_TYPE_MASK \
6203 #define HWRM_ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_TYPE_SFT 0
6204 /* HWRM Asynchronous Event Information */
6205 #define HWRM_ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_TYPE_HWRM_ASYNC_EVENT \
6207 #define HWRM_ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_TYPE_LAST \
6208 HWRM_ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_TYPE_HWRM_ASYNC_EVENT
6209 /* Identifiers of events. */
6211 /* Link status changed */
6212 #define HWRM_ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_ID_LINK_STATUS_CHANGE \
6214 #define HWRM_ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_ID_LAST \
6215 HWRM_ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_ID_LINK_STATUS_CHANGE
6216 /* Event specific data */
6217 uint32_t event_data2;
6220 * This value is written by the NIC such that it will be different
6221 * for each pass through the completion queue. The even passes
6222 * will write 1. The odd passes will write 0.
6224 #define HWRM_ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_V \
6227 #define HWRM_ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_OPAQUE_MASK \
6229 #define HWRM_ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_OPAQUE_SFT 1
6230 /* 8-lsb timestamp from POR (100-msec resolution) */
6231 uint8_t timestamp_lo;
6232 /* 16-lsb timestamp from POR (100-msec resolution) */
6233 uint16_t timestamp_hi;
6234 /* Event specific data */
6235 uint32_t event_data1;
6236 /* Indicates link status change */
6237 #define HWRM_ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_DATA1_LINK_CHANGE \
6240 * If this bit set to 0, then it indicates that the link
6241 * was up and it went down.
6243 #define HWRM_ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_DATA1_LINK_CHANGE_DOWN \
6246 * If this bit is set to 1, then it indicates that the link
6247 * was down and it went up.
6249 #define HWRM_ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_DATA1_LINK_CHANGE_UP \
6251 #define HWRM_ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_DATA1_LINK_CHANGE_LAST \
6252 HWRM_ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_DATA1_LINK_CHANGE_UP
6253 /* Indicates the physical port this link status change occur */
6254 #define HWRM_ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_DATA1_PORT_MASK \
6256 #define HWRM_ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_DATA1_PORT_SFT \
6259 #define HWRM_ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_DATA1_PORT_ID_MASK \
6261 #define HWRM_ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_DATA1_PORT_ID_SFT \
6263 /* Indicates the physical function this event occurred on. */
6264 #define HWRM_ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_DATA1_PF_ID_MASK \
6266 #define HWRM_ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_DATA1_PF_ID_SFT \
6270 /* hwrm_async_event_cmpl_link_mtu_change (size:128b/16B) */
6271 struct hwrm_async_event_cmpl_link_mtu_change {
6274 * This field indicates the exact type of the completion.
6275 * By convention, the LSB identifies the length of the
6276 * record in 16B units. Even values indicate 16B
6277 * records. Odd values indicate 32B
6280 #define HWRM_ASYNC_EVENT_CMPL_LINK_MTU_CHANGE_TYPE_MASK \
6282 #define HWRM_ASYNC_EVENT_CMPL_LINK_MTU_CHANGE_TYPE_SFT 0
6283 /* HWRM Asynchronous Event Information */
6284 #define HWRM_ASYNC_EVENT_CMPL_LINK_MTU_CHANGE_TYPE_HWRM_ASYNC_EVENT \
6286 #define HWRM_ASYNC_EVENT_CMPL_LINK_MTU_CHANGE_TYPE_LAST \
6287 HWRM_ASYNC_EVENT_CMPL_LINK_MTU_CHANGE_TYPE_HWRM_ASYNC_EVENT
6288 /* Identifiers of events. */
6290 /* Link MTU changed */
6291 #define HWRM_ASYNC_EVENT_CMPL_LINK_MTU_CHANGE_EVENT_ID_LINK_MTU_CHANGE \
6293 #define HWRM_ASYNC_EVENT_CMPL_LINK_MTU_CHANGE_EVENT_ID_LAST \
6294 HWRM_ASYNC_EVENT_CMPL_LINK_MTU_CHANGE_EVENT_ID_LINK_MTU_CHANGE
6295 /* Event specific data */
6296 uint32_t event_data2;
6299 * This value is written by the NIC such that it will be different
6300 * for each pass through the completion queue. The even passes
6301 * will write 1. The odd passes will write 0.
6303 #define HWRM_ASYNC_EVENT_CMPL_LINK_MTU_CHANGE_V UINT32_C(0x1)
6305 #define HWRM_ASYNC_EVENT_CMPL_LINK_MTU_CHANGE_OPAQUE_MASK \
6307 #define HWRM_ASYNC_EVENT_CMPL_LINK_MTU_CHANGE_OPAQUE_SFT 1
6308 /* 8-lsb timestamp from POR (100-msec resolution) */
6309 uint8_t timestamp_lo;
6310 /* 16-lsb timestamp from POR (100-msec resolution) */
6311 uint16_t timestamp_hi;
6312 /* Event specific data */
6313 uint32_t event_data1;
6314 /* The new MTU of the link in bytes. */
6315 #define HWRM_ASYNC_EVENT_CMPL_LINK_MTU_CHANGE_EVENT_DATA1_NEW_MTU_MASK \
6317 #define HWRM_ASYNC_EVENT_CMPL_LINK_MTU_CHANGE_EVENT_DATA1_NEW_MTU_SFT 0
6320 /* hwrm_async_event_cmpl_link_speed_change (size:128b/16B) */
6321 struct hwrm_async_event_cmpl_link_speed_change {
6324 * This field indicates the exact type of the completion.
6325 * By convention, the LSB identifies the length of the
6326 * record in 16B units. Even values indicate 16B
6327 * records. Odd values indicate 32B
6330 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_TYPE_MASK \
6332 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_TYPE_SFT 0
6333 /* HWRM Asynchronous Event Information */
6334 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_TYPE_HWRM_ASYNC_EVENT \
6336 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_TYPE_LAST \
6337 HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_TYPE_HWRM_ASYNC_EVENT
6338 /* Identifiers of events. */
6340 /* Link speed changed */
6341 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_EVENT_ID_LINK_SPEED_CHANGE \
6343 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_EVENT_ID_LAST \
6344 HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_EVENT_ID_LINK_SPEED_CHANGE
6345 /* Event specific data */
6346 uint32_t event_data2;
6349 * This value is written by the NIC such that it will be different
6350 * for each pass through the completion queue. The even passes
6351 * will write 1. The odd passes will write 0.
6353 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_V \
6356 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_OPAQUE_MASK \
6358 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_OPAQUE_SFT 1
6359 /* 8-lsb timestamp from POR (100-msec resolution) */
6360 uint8_t timestamp_lo;
6361 /* 16-lsb timestamp from POR (100-msec resolution) */
6362 uint16_t timestamp_hi;
6363 /* Event specific data */
6364 uint32_t event_data1;
6366 * When this bit is '1', the link was forced to the
6367 * force_link_speed value.
6369 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_EVENT_DATA1_FORCE \
6371 /* The new link speed in 100 Mbps units. */
6372 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_EVENT_DATA1_NEW_LINK_SPEED_100MBPS_MASK \
6374 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_EVENT_DATA1_NEW_LINK_SPEED_100MBPS_SFT \
6376 /* 100Mb link speed */
6377 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_EVENT_DATA1_NEW_LINK_SPEED_100MBPS_100MB \
6378 (UINT32_C(0x1) << 1)
6379 /* 1Gb link speed */
6380 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_EVENT_DATA1_NEW_LINK_SPEED_100MBPS_1GB \
6381 (UINT32_C(0xa) << 1)
6382 /* 2Gb link speed */
6383 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_EVENT_DATA1_NEW_LINK_SPEED_100MBPS_2GB \
6384 (UINT32_C(0x14) << 1)
6385 /* 25Gb link speed */
6386 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_EVENT_DATA1_NEW_LINK_SPEED_100MBPS_2_5GB \
6387 (UINT32_C(0x19) << 1)
6388 /* 10Gb link speed */
6389 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_EVENT_DATA1_NEW_LINK_SPEED_100MBPS_10GB \
6390 (UINT32_C(0x64) << 1)
6391 /* 20Mb link speed */
6392 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_EVENT_DATA1_NEW_LINK_SPEED_100MBPS_20GB \
6393 (UINT32_C(0xc8) << 1)
6394 /* 25Gb link speed */
6395 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_EVENT_DATA1_NEW_LINK_SPEED_100MBPS_25GB \
6396 (UINT32_C(0xfa) << 1)
6397 /* 40Gb link speed */
6398 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_EVENT_DATA1_NEW_LINK_SPEED_100MBPS_40GB \
6399 (UINT32_C(0x190) << 1)
6400 /* 50Gb link speed */
6401 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_EVENT_DATA1_NEW_LINK_SPEED_100MBPS_50GB \
6402 (UINT32_C(0x1f4) << 1)
6403 /* 100Gb link speed */
6404 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_EVENT_DATA1_NEW_LINK_SPEED_100MBPS_100GB \
6405 (UINT32_C(0x3e8) << 1)
6406 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_EVENT_DATA1_NEW_LINK_SPEED_100MBPS_LAST \
6407 HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_EVENT_DATA1_NEW_LINK_SPEED_100MBPS_100GB
6409 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_EVENT_DATA1_PORT_ID_MASK \
6410 UINT32_C(0xffff0000)
6411 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_EVENT_DATA1_PORT_ID_SFT \
6415 /* hwrm_async_event_cmpl_dcb_config_change (size:128b/16B) */
6416 struct hwrm_async_event_cmpl_dcb_config_change {
6419 * This field indicates the exact type of the completion.
6420 * By convention, the LSB identifies the length of the
6421 * record in 16B units. Even values indicate 16B
6422 * records. Odd values indicate 32B
6425 #define HWRM_ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_TYPE_MASK \
6427 #define HWRM_ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_TYPE_SFT 0
6428 /* HWRM Asynchronous Event Information */
6429 #define HWRM_ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_TYPE_HWRM_ASYNC_EVENT \
6431 #define HWRM_ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_TYPE_LAST \
6432 HWRM_ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_TYPE_HWRM_ASYNC_EVENT
6433 /* Identifiers of events. */
6435 /* DCB Configuration changed */
6436 #define HWRM_ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_EVENT_ID_DCB_CONFIG_CHANGE \
6438 #define HWRM_ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_EVENT_ID_LAST \
6439 HWRM_ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_EVENT_ID_DCB_CONFIG_CHANGE
6440 /* Event specific data */
6441 uint32_t event_data2;
6442 /* ETS configuration change */
6443 #define HWRM_ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_EVENT_DATA2_ETS \
6445 /* PFC configuration change */
6446 #define HWRM_ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_EVENT_DATA2_PFC \
6448 /* APP configuration change */
6449 #define HWRM_ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_EVENT_DATA2_APP \
6453 * This value is written by the NIC such that it will be different
6454 * for each pass through the completion queue. The even passes
6455 * will write 1. The odd passes will write 0.
6457 #define HWRM_ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_V \
6460 #define HWRM_ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_OPAQUE_MASK \
6462 #define HWRM_ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_OPAQUE_SFT 1
6463 /* 8-lsb timestamp from POR (100-msec resolution) */
6464 uint8_t timestamp_lo;
6465 /* 16-lsb timestamp from POR (100-msec resolution) */
6466 uint16_t timestamp_hi;
6467 /* Event specific data */
6468 uint32_t event_data1;
6470 #define HWRM_ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_EVENT_DATA1_PORT_ID_MASK \
6472 #define HWRM_ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_EVENT_DATA1_PORT_ID_SFT \
6474 /* Priority recommended for RoCE traffic */
6475 #define HWRM_ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_EVENT_DATA1_RECOMMEND_ROCE_PRIORITY_MASK \
6477 #define HWRM_ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_EVENT_DATA1_RECOMMEND_ROCE_PRIORITY_SFT \
6480 #define HWRM_ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_EVENT_DATA1_RECOMMEND_ROCE_PRIORITY_NONE \
6481 (UINT32_C(0xff) << 16)
6482 #define HWRM_ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_EVENT_DATA1_RECOMMEND_ROCE_PRIORITY_LAST \
6483 HWRM_ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_EVENT_DATA1_RECOMMEND_ROCE_PRIORITY_NONE
6484 /* Priority recommended for L2 traffic */
6485 #define HWRM_ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_EVENT_DATA1_RECOMMEND_L2_PRIORITY_MASK \
6486 UINT32_C(0xff000000)
6487 #define HWRM_ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_EVENT_DATA1_RECOMMEND_L2_PRIORITY_SFT \
6490 #define HWRM_ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_EVENT_DATA1_RECOMMEND_L2_PRIORITY_NONE \
6491 (UINT32_C(0xff) << 24)
6492 #define HWRM_ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_EVENT_DATA1_RECOMMEND_L2_PRIORITY_LAST \
6493 HWRM_ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_EVENT_DATA1_RECOMMEND_L2_PRIORITY_NONE
6496 /* hwrm_async_event_cmpl_port_conn_not_allowed (size:128b/16B) */
6497 struct hwrm_async_event_cmpl_port_conn_not_allowed {
6500 * This field indicates the exact type of the completion.
6501 * By convention, the LSB identifies the length of the
6502 * record in 16B units. Even values indicate 16B
6503 * records. Odd values indicate 32B
6506 #define HWRM_ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_TYPE_MASK \
6508 #define HWRM_ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_TYPE_SFT \
6510 /* HWRM Asynchronous Event Information */
6511 #define HWRM_ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_TYPE_HWRM_ASYNC_EVENT \
6513 #define HWRM_ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_TYPE_LAST \
6514 HWRM_ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_TYPE_HWRM_ASYNC_EVENT
6515 /* Identifiers of events. */
6517 /* Port connection not allowed */
6518 #define HWRM_ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_ID_PORT_CONN_NOT_ALLOWED \
6520 #define HWRM_ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_ID_LAST \
6521 HWRM_ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_ID_PORT_CONN_NOT_ALLOWED
6522 /* Event specific data */
6523 uint32_t event_data2;
6526 * This value is written by the NIC such that it will be different
6527 * for each pass through the completion queue. The even passes
6528 * will write 1. The odd passes will write 0.
6530 #define HWRM_ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_V \
6533 #define HWRM_ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_OPAQUE_MASK \
6535 #define HWRM_ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_OPAQUE_SFT 1
6536 /* 8-lsb timestamp from POR (100-msec resolution) */
6537 uint8_t timestamp_lo;
6538 /* 16-lsb timestamp from POR (100-msec resolution) */
6539 uint16_t timestamp_hi;
6540 /* Event specific data */
6541 uint32_t event_data1;
6543 #define HWRM_ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_PORT_ID_MASK \
6545 #define HWRM_ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_PORT_ID_SFT \
6548 * This value indicates the current port level enforcement policy
6549 * for the optics module when there is an optical module mismatch
6550 * and port is not connected.
6552 #define HWRM_ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_ENFORCEMENT_POLICY_MASK \
6554 #define HWRM_ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_ENFORCEMENT_POLICY_SFT \
6556 /* No enforcement */
6557 #define HWRM_ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_ENFORCEMENT_POLICY_NONE \
6558 (UINT32_C(0x0) << 16)
6559 /* Disable Transmit side Laser. */
6560 #define HWRM_ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_ENFORCEMENT_POLICY_DISABLETX \
6561 (UINT32_C(0x1) << 16)
6562 /* Raise a warning message. */
6563 #define HWRM_ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_ENFORCEMENT_POLICY_WARNINGMSG \
6564 (UINT32_C(0x2) << 16)
6565 /* Power down the module. */
6566 #define HWRM_ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_ENFORCEMENT_POLICY_PWRDOWN \
6567 (UINT32_C(0x3) << 16)
6568 #define HWRM_ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_ENFORCEMENT_POLICY_LAST \
6569 HWRM_ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_ENFORCEMENT_POLICY_PWRDOWN
6572 /* hwrm_async_event_cmpl_link_speed_cfg_not_allowed (size:128b/16B) */
6573 struct hwrm_async_event_cmpl_link_speed_cfg_not_allowed {
6576 * This field indicates the exact type of the completion.
6577 * By convention, the LSB identifies the length of the
6578 * record in 16B units. Even values indicate 16B
6579 * records. Odd values indicate 32B
6582 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_NOT_ALLOWED_TYPE_MASK \
6584 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_NOT_ALLOWED_TYPE_SFT \
6586 /* HWRM Asynchronous Event Information */
6587 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_NOT_ALLOWED_TYPE_HWRM_ASYNC_EVENT \
6589 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_NOT_ALLOWED_TYPE_LAST \
6590 HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_NOT_ALLOWED_TYPE_HWRM_ASYNC_EVENT
6591 /* Identifiers of events. */
6593 /* Link speed configuration was not allowed */
6594 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_NOT_ALLOWED_EVENT_ID_LINK_SPEED_CFG_NOT_ALLOWED \
6596 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_NOT_ALLOWED_EVENT_ID_LAST \
6597 HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_NOT_ALLOWED_EVENT_ID_LINK_SPEED_CFG_NOT_ALLOWED
6598 /* Event specific data */
6599 uint32_t event_data2;
6602 * This value is written by the NIC such that it will be different
6603 * for each pass through the completion queue. The even passes
6604 * will write 1. The odd passes will write 0.
6606 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_NOT_ALLOWED_V \
6609 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_NOT_ALLOWED_OPAQUE_MASK \
6611 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_NOT_ALLOWED_OPAQUE_SFT 1
6612 /* 8-lsb timestamp from POR (100-msec resolution) */
6613 uint8_t timestamp_lo;
6614 /* 16-lsb timestamp from POR (100-msec resolution) */
6615 uint16_t timestamp_hi;
6616 /* Event specific data */
6617 uint32_t event_data1;
6619 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_NOT_ALLOWED_EVENT_DATA1_PORT_ID_MASK \
6621 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_NOT_ALLOWED_EVENT_DATA1_PORT_ID_SFT \
6625 /* hwrm_async_event_cmpl_link_speed_cfg_change (size:128b/16B) */
6626 struct hwrm_async_event_cmpl_link_speed_cfg_change {
6629 * This field indicates the exact type of the completion.
6630 * By convention, the LSB identifies the length of the
6631 * record in 16B units. Even values indicate 16B
6632 * records. Odd values indicate 32B
6635 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_TYPE_MASK \
6637 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_TYPE_SFT \
6639 /* HWRM Asynchronous Event Information */
6640 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_TYPE_HWRM_ASYNC_EVENT \
6642 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_TYPE_LAST \
6643 HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_TYPE_HWRM_ASYNC_EVENT
6644 /* Identifiers of events. */
6646 /* Link speed configuration change */
6647 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_EVENT_ID_LINK_SPEED_CFG_CHANGE \
6649 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_EVENT_ID_LAST \
6650 HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_EVENT_ID_LINK_SPEED_CFG_CHANGE
6651 /* Event specific data */
6652 uint32_t event_data2;
6655 * This value is written by the NIC such that it will be different
6656 * for each pass through the completion queue. The even passes
6657 * will write 1. The odd passes will write 0.
6659 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_V \
6662 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_OPAQUE_MASK \
6664 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_OPAQUE_SFT 1
6665 /* 8-lsb timestamp from POR (100-msec resolution) */
6666 uint8_t timestamp_lo;
6667 /* 16-lsb timestamp from POR (100-msec resolution) */
6668 uint16_t timestamp_hi;
6669 /* Event specific data */
6670 uint32_t event_data1;
6672 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_EVENT_DATA1_PORT_ID_MASK \
6674 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_EVENT_DATA1_PORT_ID_SFT \
6677 * If set to 1, it indicates that the supported link speeds
6678 * configuration on the port has changed.
6679 * If set to 0, then there is no change in supported link speeds
6682 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_EVENT_DATA1_SUPPORTED_LINK_SPEEDS_CHANGE \
6685 * If set to 1, it indicates that the link speed configuration
6686 * on the port has become illegal or invalid.
6687 * If set to 0, then the link speed configuration on the port is
6690 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_EVENT_DATA1_ILLEGAL_LINK_SPEED_CFG \
6694 /* hwrm_async_event_cmpl_port_phy_cfg_change (size:128b/16B) */
6695 struct hwrm_async_event_cmpl_port_phy_cfg_change {
6698 * This field indicates the exact type of the completion.
6699 * By convention, the LSB identifies the length of the
6700 * record in 16B units. Even values indicate 16B
6701 * records. Odd values indicate 32B
6704 #define HWRM_ASYNC_EVENT_CMPL_PORT_PHY_CFG_CHANGE_TYPE_MASK \
6706 #define HWRM_ASYNC_EVENT_CMPL_PORT_PHY_CFG_CHANGE_TYPE_SFT \
6708 /* HWRM Asynchronous Event Information */
6709 #define HWRM_ASYNC_EVENT_CMPL_PORT_PHY_CFG_CHANGE_TYPE_HWRM_ASYNC_EVENT \
6711 #define HWRM_ASYNC_EVENT_CMPL_PORT_PHY_CFG_CHANGE_TYPE_LAST \
6712 HWRM_ASYNC_EVENT_CMPL_PORT_PHY_CFG_CHANGE_TYPE_HWRM_ASYNC_EVENT
6713 /* Identifiers of events. */
6715 /* Port PHY configuration change */
6716 #define HWRM_ASYNC_EVENT_CMPL_PORT_PHY_CFG_CHANGE_EVENT_ID_PORT_PHY_CFG_CHANGE \
6718 #define HWRM_ASYNC_EVENT_CMPL_PORT_PHY_CFG_CHANGE_EVENT_ID_LAST \
6719 HWRM_ASYNC_EVENT_CMPL_PORT_PHY_CFG_CHANGE_EVENT_ID_PORT_PHY_CFG_CHANGE
6720 /* Event specific data */
6721 uint32_t event_data2;
6724 * This value is written by the NIC such that it will be different
6725 * for each pass through the completion queue. The even passes
6726 * will write 1. The odd passes will write 0.
6728 #define HWRM_ASYNC_EVENT_CMPL_PORT_PHY_CFG_CHANGE_V \
6731 #define HWRM_ASYNC_EVENT_CMPL_PORT_PHY_CFG_CHANGE_OPAQUE_MASK \
6733 #define HWRM_ASYNC_EVENT_CMPL_PORT_PHY_CFG_CHANGE_OPAQUE_SFT 1
6734 /* 8-lsb timestamp from POR (100-msec resolution) */
6735 uint8_t timestamp_lo;
6736 /* 16-lsb timestamp from POR (100-msec resolution) */
6737 uint16_t timestamp_hi;
6738 /* Event specific data */
6739 uint32_t event_data1;
6741 #define HWRM_ASYNC_EVENT_CMPL_PORT_PHY_CFG_CHANGE_EVENT_DATA1_PORT_ID_MASK \
6743 #define HWRM_ASYNC_EVENT_CMPL_PORT_PHY_CFG_CHANGE_EVENT_DATA1_PORT_ID_SFT \
6746 * If set to 1, it indicates that the FEC
6747 * configuration on the port has changed.
6748 * If set to 0, then there is no change in FEC configuration.
6750 #define HWRM_ASYNC_EVENT_CMPL_PORT_PHY_CFG_CHANGE_EVENT_DATA1_FEC_CFG_CHANGE \
6753 * If set to 1, it indicates that the EEE configuration
6754 * on the port has changed.
6755 * If set to 0, then there is no change in EEE configuration
6758 #define HWRM_ASYNC_EVENT_CMPL_PORT_PHY_CFG_CHANGE_EVENT_DATA1_EEE_CFG_CHANGE \
6761 * If set to 1, it indicates that the pause configuration
6762 * on the PHY has changed.
6763 * If set to 0, then there is no change in the pause
6764 * configuration on the PHY.
6766 #define HWRM_ASYNC_EVENT_CMPL_PORT_PHY_CFG_CHANGE_EVENT_DATA1_PAUSE_CFG_CHANGE \
6770 /* hwrm_async_event_cmpl_reset_notify (size:128b/16B) */
6771 struct hwrm_async_event_cmpl_reset_notify {
6774 * This field indicates the exact type of the completion.
6775 * By convention, the LSB identifies the length of the
6776 * record in 16B units. Even values indicate 16B
6777 * records. Odd values indicate 32B
6780 #define HWRM_ASYNC_EVENT_CMPL_RESET_NOTIFY_TYPE_MASK \
6782 #define HWRM_ASYNC_EVENT_CMPL_RESET_NOTIFY_TYPE_SFT 0
6783 /* HWRM Asynchronous Event Information */
6784 #define HWRM_ASYNC_EVENT_CMPL_RESET_NOTIFY_TYPE_HWRM_ASYNC_EVENT \
6786 #define HWRM_ASYNC_EVENT_CMPL_RESET_NOTIFY_TYPE_LAST \
6787 HWRM_ASYNC_EVENT_CMPL_RESET_NOTIFY_TYPE_HWRM_ASYNC_EVENT
6788 /* Identifiers of events. */
6790 /* Notify clients of imminent reset. */
6791 #define HWRM_ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_ID_RESET_NOTIFY \
6793 #define HWRM_ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_ID_LAST \
6794 HWRM_ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_ID_RESET_NOTIFY
6795 /* Event specific data */
6796 uint32_t event_data2;
6799 * This value is written by the NIC such that it will be different
6800 * for each pass through the completion queue. The even passes
6801 * will write 1. The odd passes will write 0.
6803 #define HWRM_ASYNC_EVENT_CMPL_RESET_NOTIFY_V UINT32_C(0x1)
6805 #define HWRM_ASYNC_EVENT_CMPL_RESET_NOTIFY_OPAQUE_MASK UINT32_C(0xfe)
6806 #define HWRM_ASYNC_EVENT_CMPL_RESET_NOTIFY_OPAQUE_SFT 1
6808 * 8-lsb timestamp (100-msec resolution)
6809 * The Minimum time required for the Firmware readiness after sending this
6810 * notification to the driver instances.
6812 uint8_t timestamp_lo;
6814 * 16-lsb timestamp (100-msec resolution)
6815 * The Maximum Firmware Reset bail out value in the order of 100
6816 * milli seconds. The driver instances will use this value to re-initiate the
6817 * registration process again if the core firmware didn’t set the ready
6820 uint16_t timestamp_hi;
6821 /* Event specific data */
6822 uint32_t event_data1;
6823 /* Indicates driver action requested */
6824 #define HWRM_ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_DRIVER_ACTION_MASK \
6826 #define HWRM_ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_DRIVER_ACTION_SFT \
6829 * If set to 1, it indicates that the l2 client should
6830 * stop sending in band traffic to Nitro.
6831 * if set to 0, there is no change in L2 client behavior.
6833 #define HWRM_ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_DRIVER_ACTION_DRIVER_STOP_TX_QUEUE \
6836 * If set to 1, it indicates that the L2 client should
6837 * bring down the interface.
6838 * If set to 0, then there is no change in L2 client behavior.
6840 #define HWRM_ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_DRIVER_ACTION_DRIVER_IFDOWN \
6842 #define HWRM_ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_DRIVER_ACTION_LAST \
6843 HWRM_ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_DRIVER_ACTION_DRIVER_IFDOWN
6844 /* Indicates reason for reset. */
6845 #define HWRM_ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_REASON_CODE_MASK \
6847 #define HWRM_ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_REASON_CODE_SFT \
6849 /* A management client has requested reset. */
6850 #define HWRM_ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_REASON_CODE_MANAGEMENT_RESET_REQUEST \
6851 (UINT32_C(0x1) << 8)
6852 /* A fatal firmware exception has occurred. */
6853 #define HWRM_ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_REASON_CODE_FW_EXCEPTION_FATAL \
6854 (UINT32_C(0x2) << 8)
6855 /* A non-fatal firmware exception has occurred. */
6856 #define HWRM_ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_REASON_CODE_FW_EXCEPTION_NON_FATAL \
6857 (UINT32_C(0x3) << 8)
6858 #define HWRM_ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_REASON_CODE_LAST \
6859 HWRM_ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_REASON_CODE_FW_EXCEPTION_NON_FATAL
6861 * Minimum time before driver should attempt access - units 100ms ticks.
6864 #define HWRM_ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_DELAY_IN_100MS_TICKS_MASK \
6865 UINT32_C(0xffff0000)
6866 #define HWRM_ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_DELAY_IN_100MS_TICKS_SFT \
6870 /* hwrm_async_event_cmpl_error_recovery (size:128b/16B) */
6871 struct hwrm_async_event_cmpl_error_recovery {
6874 * This field indicates the exact type of the completion.
6875 * By convention, the LSB identifies the length of the
6876 * record in 16B units. Even values indicate 16B
6877 * records. Odd values indicate 32B
6880 #define HWRM_ASYNC_EVENT_CMPL_ERROR_RECOVERY_TYPE_MASK \
6882 #define HWRM_ASYNC_EVENT_CMPL_ERROR_RECOVERY_TYPE_SFT 0
6883 /* HWRM Asynchronous Event Information */
6884 #define HWRM_ASYNC_EVENT_CMPL_ERROR_RECOVERY_TYPE_HWRM_ASYNC_EVENT \
6886 #define HWRM_ASYNC_EVENT_CMPL_ERROR_RECOVERY_TYPE_LAST \
6887 HWRM_ASYNC_EVENT_CMPL_ERROR_RECOVERY_TYPE_HWRM_ASYNC_EVENT
6888 /* Identifiers of events. */
6891 * This async notification message can be used for selecting or
6892 * deselecting master function for error recovery,
6893 * and to communicate to all the functions whether error recovery
6894 * was enabled/disabled.
6896 #define HWRM_ASYNC_EVENT_CMPL_ERROR_RECOVERY_EVENT_ID_ERROR_RECOVERY \
6898 #define HWRM_ASYNC_EVENT_CMPL_ERROR_RECOVERY_EVENT_ID_LAST \
6899 HWRM_ASYNC_EVENT_CMPL_ERROR_RECOVERY_EVENT_ID_ERROR_RECOVERY
6900 /* Event specific data */
6901 uint32_t event_data2;
6904 * This value is written by the NIC such that it will be different
6905 * for each pass through the completion queue. The even passes
6906 * will write 1. The odd passes will write 0.
6908 #define HWRM_ASYNC_EVENT_CMPL_ERROR_RECOVERY_V UINT32_C(0x1)
6910 #define HWRM_ASYNC_EVENT_CMPL_ERROR_RECOVERY_OPAQUE_MASK UINT32_C(0xfe)
6911 #define HWRM_ASYNC_EVENT_CMPL_ERROR_RECOVERY_OPAQUE_SFT 1
6912 /* 8-lsb timestamp (100-msec resolution) */
6913 uint8_t timestamp_lo;
6914 /* 16-lsb timestamp (100-msec resolution) */
6915 uint16_t timestamp_hi;
6916 /* Event specific data */
6917 uint32_t event_data1;
6918 /* Indicates driver action requested */
6919 #define HWRM_ASYNC_EVENT_CMPL_ERROR_RECOVERY_EVENT_DATA1_FLAGS_MASK \
6921 #define HWRM_ASYNC_EVENT_CMPL_ERROR_RECOVERY_EVENT_DATA1_FLAGS_SFT \
6924 * If set to 1, this function is selected as Master function.
6925 * This function has responsibility to do 'chip reset' when it
6926 * detects a fatal error. If set to 0, master function functionality
6927 * is disabled on this function.
6929 #define HWRM_ASYNC_EVENT_CMPL_ERROR_RECOVERY_EVENT_DATA1_FLAGS_MASTER_FUNC \
6932 * If set to 1, error recovery is enabled.
6933 * If set to 0, error recovery is disabled.
6935 #define HWRM_ASYNC_EVENT_CMPL_ERROR_RECOVERY_EVENT_DATA1_FLAGS_RECOVERY_ENABLED \
6939 /* hwrm_async_event_cmpl_func_drvr_unload (size:128b/16B) */
6940 struct hwrm_async_event_cmpl_func_drvr_unload {
6943 * This field indicates the exact type of the completion.
6944 * By convention, the LSB identifies the length of the
6945 * record in 16B units. Even values indicate 16B
6946 * records. Odd values indicate 32B
6949 #define HWRM_ASYNC_EVENT_CMPL_FUNC_DRVR_UNLOAD_TYPE_MASK \
6951 #define HWRM_ASYNC_EVENT_CMPL_FUNC_DRVR_UNLOAD_TYPE_SFT 0
6952 /* HWRM Asynchronous Event Information */
6953 #define HWRM_ASYNC_EVENT_CMPL_FUNC_DRVR_UNLOAD_TYPE_HWRM_ASYNC_EVENT \
6955 #define HWRM_ASYNC_EVENT_CMPL_FUNC_DRVR_UNLOAD_TYPE_LAST \
6956 HWRM_ASYNC_EVENT_CMPL_FUNC_DRVR_UNLOAD_TYPE_HWRM_ASYNC_EVENT
6957 /* Identifiers of events. */
6959 /* Function driver unloaded */
6960 #define HWRM_ASYNC_EVENT_CMPL_FUNC_DRVR_UNLOAD_EVENT_ID_FUNC_DRVR_UNLOAD \
6962 #define HWRM_ASYNC_EVENT_CMPL_FUNC_DRVR_UNLOAD_EVENT_ID_LAST \
6963 HWRM_ASYNC_EVENT_CMPL_FUNC_DRVR_UNLOAD_EVENT_ID_FUNC_DRVR_UNLOAD
6964 /* Event specific data */
6965 uint32_t event_data2;
6968 * This value is written by the NIC such that it will be different
6969 * for each pass through the completion queue. The even passes
6970 * will write 1. The odd passes will write 0.
6972 #define HWRM_ASYNC_EVENT_CMPL_FUNC_DRVR_UNLOAD_V UINT32_C(0x1)
6974 #define HWRM_ASYNC_EVENT_CMPL_FUNC_DRVR_UNLOAD_OPAQUE_MASK \
6976 #define HWRM_ASYNC_EVENT_CMPL_FUNC_DRVR_UNLOAD_OPAQUE_SFT 1
6977 /* 8-lsb timestamp from POR (100-msec resolution) */
6978 uint8_t timestamp_lo;
6979 /* 16-lsb timestamp from POR (100-msec resolution) */
6980 uint16_t timestamp_hi;
6981 /* Event specific data */
6982 uint32_t event_data1;
6984 #define HWRM_ASYNC_EVENT_CMPL_FUNC_DRVR_UNLOAD_EVENT_DATA1_FUNC_ID_MASK \
6986 #define HWRM_ASYNC_EVENT_CMPL_FUNC_DRVR_UNLOAD_EVENT_DATA1_FUNC_ID_SFT \
6990 /* hwrm_async_event_cmpl_func_drvr_load (size:128b/16B) */
6991 struct hwrm_async_event_cmpl_func_drvr_load {
6994 * This field indicates the exact type of the completion.
6995 * By convention, the LSB identifies the length of the
6996 * record in 16B units. Even values indicate 16B
6997 * records. Odd values indicate 32B
7000 #define HWRM_ASYNC_EVENT_CMPL_FUNC_DRVR_LOAD_TYPE_MASK \
7002 #define HWRM_ASYNC_EVENT_CMPL_FUNC_DRVR_LOAD_TYPE_SFT 0
7003 /* HWRM Asynchronous Event Information */
7004 #define HWRM_ASYNC_EVENT_CMPL_FUNC_DRVR_LOAD_TYPE_HWRM_ASYNC_EVENT \
7006 #define HWRM_ASYNC_EVENT_CMPL_FUNC_DRVR_LOAD_TYPE_LAST \
7007 HWRM_ASYNC_EVENT_CMPL_FUNC_DRVR_LOAD_TYPE_HWRM_ASYNC_EVENT
7008 /* Identifiers of events. */
7010 /* Function driver loaded */
7011 #define HWRM_ASYNC_EVENT_CMPL_FUNC_DRVR_LOAD_EVENT_ID_FUNC_DRVR_LOAD \
7013 #define HWRM_ASYNC_EVENT_CMPL_FUNC_DRVR_LOAD_EVENT_ID_LAST \
7014 HWRM_ASYNC_EVENT_CMPL_FUNC_DRVR_LOAD_EVENT_ID_FUNC_DRVR_LOAD
7015 /* Event specific data */
7016 uint32_t event_data2;
7019 * This value is written by the NIC such that it will be different
7020 * for each pass through the completion queue. The even passes
7021 * will write 1. The odd passes will write 0.
7023 #define HWRM_ASYNC_EVENT_CMPL_FUNC_DRVR_LOAD_V UINT32_C(0x1)
7025 #define HWRM_ASYNC_EVENT_CMPL_FUNC_DRVR_LOAD_OPAQUE_MASK UINT32_C(0xfe)
7026 #define HWRM_ASYNC_EVENT_CMPL_FUNC_DRVR_LOAD_OPAQUE_SFT 1
7027 /* 8-lsb timestamp from POR (100-msec resolution) */
7028 uint8_t timestamp_lo;
7029 /* 16-lsb timestamp from POR (100-msec resolution) */
7030 uint16_t timestamp_hi;
7031 /* Event specific data */
7032 uint32_t event_data1;
7034 #define HWRM_ASYNC_EVENT_CMPL_FUNC_DRVR_LOAD_EVENT_DATA1_FUNC_ID_MASK \
7036 #define HWRM_ASYNC_EVENT_CMPL_FUNC_DRVR_LOAD_EVENT_DATA1_FUNC_ID_SFT 0
7039 /* hwrm_async_event_cmpl_func_flr_proc_cmplt (size:128b/16B) */
7040 struct hwrm_async_event_cmpl_func_flr_proc_cmplt {
7043 * This field indicates the exact type of the completion.
7044 * By convention, the LSB identifies the length of the
7045 * record in 16B units. Even values indicate 16B
7046 * records. Odd values indicate 32B
7049 #define HWRM_ASYNC_EVENT_CMPL_FUNC_FLR_PROC_CMPLT_TYPE_MASK \
7051 #define HWRM_ASYNC_EVENT_CMPL_FUNC_FLR_PROC_CMPLT_TYPE_SFT \
7053 /* HWRM Asynchronous Event Information */
7054 #define HWRM_ASYNC_EVENT_CMPL_FUNC_FLR_PROC_CMPLT_TYPE_HWRM_ASYNC_EVENT \
7056 #define HWRM_ASYNC_EVENT_CMPL_FUNC_FLR_PROC_CMPLT_TYPE_LAST \
7057 HWRM_ASYNC_EVENT_CMPL_FUNC_FLR_PROC_CMPLT_TYPE_HWRM_ASYNC_EVENT
7058 /* Identifiers of events. */
7060 /* Function FLR related processing has completed */
7061 #define HWRM_ASYNC_EVENT_CMPL_FUNC_FLR_PROC_CMPLT_EVENT_ID_FUNC_FLR_PROC_CMPLT \
7063 #define HWRM_ASYNC_EVENT_CMPL_FUNC_FLR_PROC_CMPLT_EVENT_ID_LAST \
7064 HWRM_ASYNC_EVENT_CMPL_FUNC_FLR_PROC_CMPLT_EVENT_ID_FUNC_FLR_PROC_CMPLT
7065 /* Event specific data */
7066 uint32_t event_data2;
7069 * This value is written by the NIC such that it will be different
7070 * for each pass through the completion queue. The even passes
7071 * will write 1. The odd passes will write 0.
7073 #define HWRM_ASYNC_EVENT_CMPL_FUNC_FLR_PROC_CMPLT_V \
7076 #define HWRM_ASYNC_EVENT_CMPL_FUNC_FLR_PROC_CMPLT_OPAQUE_MASK \
7078 #define HWRM_ASYNC_EVENT_CMPL_FUNC_FLR_PROC_CMPLT_OPAQUE_SFT 1
7079 /* 8-lsb timestamp from POR (100-msec resolution) */
7080 uint8_t timestamp_lo;
7081 /* 16-lsb timestamp from POR (100-msec resolution) */
7082 uint16_t timestamp_hi;
7083 /* Event specific data */
7084 uint32_t event_data1;
7086 #define HWRM_ASYNC_EVENT_CMPL_FUNC_FLR_PROC_CMPLT_EVENT_DATA1_FUNC_ID_MASK \
7088 #define HWRM_ASYNC_EVENT_CMPL_FUNC_FLR_PROC_CMPLT_EVENT_DATA1_FUNC_ID_SFT \
7092 /* hwrm_async_event_cmpl_pf_drvr_unload (size:128b/16B) */
7093 struct hwrm_async_event_cmpl_pf_drvr_unload {
7096 * This field indicates the exact type of the completion.
7097 * By convention, the LSB identifies the length of the
7098 * record in 16B units. Even values indicate 16B
7099 * records. Odd values indicate 32B
7102 #define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_UNLOAD_TYPE_MASK \
7104 #define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_UNLOAD_TYPE_SFT 0
7105 /* HWRM Asynchronous Event Information */
7106 #define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_UNLOAD_TYPE_HWRM_ASYNC_EVENT \
7108 #define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_UNLOAD_TYPE_LAST \
7109 HWRM_ASYNC_EVENT_CMPL_PF_DRVR_UNLOAD_TYPE_HWRM_ASYNC_EVENT
7110 /* Identifiers of events. */
7112 /* PF driver unloaded */
7113 #define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_UNLOAD_EVENT_ID_PF_DRVR_UNLOAD \
7115 #define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_UNLOAD_EVENT_ID_LAST \
7116 HWRM_ASYNC_EVENT_CMPL_PF_DRVR_UNLOAD_EVENT_ID_PF_DRVR_UNLOAD
7117 /* Event specific data */
7118 uint32_t event_data2;
7121 * This value is written by the NIC such that it will be different
7122 * for each pass through the completion queue. The even passes
7123 * will write 1. The odd passes will write 0.
7125 #define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_UNLOAD_V UINT32_C(0x1)
7127 #define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_UNLOAD_OPAQUE_MASK UINT32_C(0xfe)
7128 #define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_UNLOAD_OPAQUE_SFT 1
7129 /* 8-lsb timestamp from POR (100-msec resolution) */
7130 uint8_t timestamp_lo;
7131 /* 16-lsb timestamp from POR (100-msec resolution) */
7132 uint16_t timestamp_hi;
7133 /* Event specific data */
7134 uint32_t event_data1;
7136 #define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_UNLOAD_EVENT_DATA1_FUNC_ID_MASK \
7138 #define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_UNLOAD_EVENT_DATA1_FUNC_ID_SFT 0
7139 /* Indicates the physical port this pf belongs to */
7140 #define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_UNLOAD_EVENT_DATA1_PORT_MASK \
7142 #define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_UNLOAD_EVENT_DATA1_PORT_SFT 16
7145 /* hwrm_async_event_cmpl_pf_drvr_load (size:128b/16B) */
7146 struct hwrm_async_event_cmpl_pf_drvr_load {
7149 * This field indicates the exact type of the completion.
7150 * By convention, the LSB identifies the length of the
7151 * record in 16B units. Even values indicate 16B
7152 * records. Odd values indicate 32B
7155 #define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_LOAD_TYPE_MASK \
7157 #define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_LOAD_TYPE_SFT 0
7158 /* HWRM Asynchronous Event Information */
7159 #define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_LOAD_TYPE_HWRM_ASYNC_EVENT \
7161 #define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_LOAD_TYPE_LAST \
7162 HWRM_ASYNC_EVENT_CMPL_PF_DRVR_LOAD_TYPE_HWRM_ASYNC_EVENT
7163 /* Identifiers of events. */
7165 /* PF driver loaded */
7166 #define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_LOAD_EVENT_ID_PF_DRVR_LOAD \
7168 #define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_LOAD_EVENT_ID_LAST \
7169 HWRM_ASYNC_EVENT_CMPL_PF_DRVR_LOAD_EVENT_ID_PF_DRVR_LOAD
7170 /* Event specific data */
7171 uint32_t event_data2;
7174 * This value is written by the NIC such that it will be different
7175 * for each pass through the completion queue. The even passes
7176 * will write 1. The odd passes will write 0.
7178 #define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_LOAD_V UINT32_C(0x1)
7180 #define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_LOAD_OPAQUE_MASK UINT32_C(0xfe)
7181 #define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_LOAD_OPAQUE_SFT 1
7182 /* 8-lsb timestamp from POR (100-msec resolution) */
7183 uint8_t timestamp_lo;
7184 /* 16-lsb timestamp from POR (100-msec resolution) */
7185 uint16_t timestamp_hi;
7186 /* Event specific data */
7187 uint32_t event_data1;
7189 #define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_LOAD_EVENT_DATA1_FUNC_ID_MASK \
7191 #define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_LOAD_EVENT_DATA1_FUNC_ID_SFT 0
7192 /* Indicates the physical port this pf belongs to */
7193 #define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_LOAD_EVENT_DATA1_PORT_MASK \
7195 #define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_LOAD_EVENT_DATA1_PORT_SFT 16
7198 /* hwrm_async_event_cmpl_vf_flr (size:128b/16B) */
7199 struct hwrm_async_event_cmpl_vf_flr {
7202 * This field indicates the exact type of the completion.
7203 * By convention, the LSB identifies the length of the
7204 * record in 16B units. Even values indicate 16B
7205 * records. Odd values indicate 32B
7208 #define HWRM_ASYNC_EVENT_CMPL_VF_FLR_TYPE_MASK \
7210 #define HWRM_ASYNC_EVENT_CMPL_VF_FLR_TYPE_SFT 0
7211 /* HWRM Asynchronous Event Information */
7212 #define HWRM_ASYNC_EVENT_CMPL_VF_FLR_TYPE_HWRM_ASYNC_EVENT \
7214 #define HWRM_ASYNC_EVENT_CMPL_VF_FLR_TYPE_LAST \
7215 HWRM_ASYNC_EVENT_CMPL_VF_FLR_TYPE_HWRM_ASYNC_EVENT
7216 /* Identifiers of events. */
7218 /* VF Function Level Reset (FLR) */
7219 #define HWRM_ASYNC_EVENT_CMPL_VF_FLR_EVENT_ID_VF_FLR UINT32_C(0x30)
7220 #define HWRM_ASYNC_EVENT_CMPL_VF_FLR_EVENT_ID_LAST \
7221 HWRM_ASYNC_EVENT_CMPL_VF_FLR_EVENT_ID_VF_FLR
7222 /* Event specific data */
7223 uint32_t event_data2;
7226 * This value is written by the NIC such that it will be different
7227 * for each pass through the completion queue. The even passes
7228 * will write 1. The odd passes will write 0.
7230 #define HWRM_ASYNC_EVENT_CMPL_VF_FLR_V UINT32_C(0x1)
7232 #define HWRM_ASYNC_EVENT_CMPL_VF_FLR_OPAQUE_MASK UINT32_C(0xfe)
7233 #define HWRM_ASYNC_EVENT_CMPL_VF_FLR_OPAQUE_SFT 1
7234 /* 8-lsb timestamp from POR (100-msec resolution) */
7235 uint8_t timestamp_lo;
7236 /* 16-lsb timestamp from POR (100-msec resolution) */
7237 uint16_t timestamp_hi;
7238 /* Event specific data */
7239 uint32_t event_data1;
7241 #define HWRM_ASYNC_EVENT_CMPL_VF_FLR_EVENT_DATA1_VF_ID_MASK \
7243 #define HWRM_ASYNC_EVENT_CMPL_VF_FLR_EVENT_DATA1_VF_ID_SFT 0
7244 /* Indicates the physical function this event occurred on. */
7245 #define HWRM_ASYNC_EVENT_CMPL_VF_FLR_EVENT_DATA1_PF_ID_MASK \
7247 #define HWRM_ASYNC_EVENT_CMPL_VF_FLR_EVENT_DATA1_PF_ID_SFT 16
7250 /* hwrm_async_event_cmpl_vf_mac_addr_change (size:128b/16B) */
7251 struct hwrm_async_event_cmpl_vf_mac_addr_change {
7254 * This field indicates the exact type of the completion.
7255 * By convention, the LSB identifies the length of the
7256 * record in 16B units. Even values indicate 16B
7257 * records. Odd values indicate 32B
7260 #define HWRM_ASYNC_EVENT_CMPL_VF_MAC_ADDR_CHANGE_TYPE_MASK \
7262 #define HWRM_ASYNC_EVENT_CMPL_VF_MAC_ADDR_CHANGE_TYPE_SFT 0
7263 /* HWRM Asynchronous Event Information */
7264 #define HWRM_ASYNC_EVENT_CMPL_VF_MAC_ADDR_CHANGE_TYPE_HWRM_ASYNC_EVENT \
7266 #define HWRM_ASYNC_EVENT_CMPL_VF_MAC_ADDR_CHANGE_TYPE_LAST \
7267 HWRM_ASYNC_EVENT_CMPL_VF_MAC_ADDR_CHANGE_TYPE_HWRM_ASYNC_EVENT
7268 /* Identifiers of events. */
7270 /* VF MAC Address Change */
7271 #define HWRM_ASYNC_EVENT_CMPL_VF_MAC_ADDR_CHANGE_EVENT_ID_VF_MAC_ADDR_CHANGE \
7273 #define HWRM_ASYNC_EVENT_CMPL_VF_MAC_ADDR_CHANGE_EVENT_ID_LAST \
7274 HWRM_ASYNC_EVENT_CMPL_VF_MAC_ADDR_CHANGE_EVENT_ID_VF_MAC_ADDR_CHANGE
7275 /* Event specific data */
7276 uint32_t event_data2;
7279 * This value is written by the NIC such that it will be different
7280 * for each pass through the completion queue. The even passes
7281 * will write 1. The odd passes will write 0.
7283 #define HWRM_ASYNC_EVENT_CMPL_VF_MAC_ADDR_CHANGE_V \
7286 #define HWRM_ASYNC_EVENT_CMPL_VF_MAC_ADDR_CHANGE_OPAQUE_MASK \
7288 #define HWRM_ASYNC_EVENT_CMPL_VF_MAC_ADDR_CHANGE_OPAQUE_SFT 1
7289 /* 8-lsb timestamp from POR (100-msec resolution) */
7290 uint8_t timestamp_lo;
7291 /* 16-lsb timestamp from POR (100-msec resolution) */
7292 uint16_t timestamp_hi;
7293 /* Event specific data */
7294 uint32_t event_data1;
7296 #define HWRM_ASYNC_EVENT_CMPL_VF_MAC_ADDR_CHANGE_EVENT_DATA1_VF_ID_MASK \
7298 #define HWRM_ASYNC_EVENT_CMPL_VF_MAC_ADDR_CHANGE_EVENT_DATA1_VF_ID_SFT \
7302 /* hwrm_async_event_cmpl_pf_vf_comm_status_change (size:128b/16B) */
7303 struct hwrm_async_event_cmpl_pf_vf_comm_status_change {
7306 * This field indicates the exact type of the completion.
7307 * By convention, the LSB identifies the length of the
7308 * record in 16B units. Even values indicate 16B
7309 * records. Odd values indicate 32B
7312 #define HWRM_ASYNC_EVENT_CMPL_PF_VF_COMM_STATUS_CHANGE_TYPE_MASK \
7314 #define HWRM_ASYNC_EVENT_CMPL_PF_VF_COMM_STATUS_CHANGE_TYPE_SFT \
7316 /* HWRM Asynchronous Event Information */
7317 #define HWRM_ASYNC_EVENT_CMPL_PF_VF_COMM_STATUS_CHANGE_TYPE_HWRM_ASYNC_EVENT \
7319 #define HWRM_ASYNC_EVENT_CMPL_PF_VF_COMM_STATUS_CHANGE_TYPE_LAST \
7320 HWRM_ASYNC_EVENT_CMPL_PF_VF_COMM_STATUS_CHANGE_TYPE_HWRM_ASYNC_EVENT
7321 /* Identifiers of events. */
7323 /* PF-VF communication channel status change. */
7324 #define HWRM_ASYNC_EVENT_CMPL_PF_VF_COMM_STATUS_CHANGE_EVENT_ID_PF_VF_COMM_STATUS_CHANGE \
7326 #define HWRM_ASYNC_EVENT_CMPL_PF_VF_COMM_STATUS_CHANGE_EVENT_ID_LAST \
7327 HWRM_ASYNC_EVENT_CMPL_PF_VF_COMM_STATUS_CHANGE_EVENT_ID_PF_VF_COMM_STATUS_CHANGE
7328 /* Event specific data */
7329 uint32_t event_data2;
7332 * This value is written by the NIC such that it will be different
7333 * for each pass through the completion queue. The even passes
7334 * will write 1. The odd passes will write 0.
7336 #define HWRM_ASYNC_EVENT_CMPL_PF_VF_COMM_STATUS_CHANGE_V \
7339 #define HWRM_ASYNC_EVENT_CMPL_PF_VF_COMM_STATUS_CHANGE_OPAQUE_MASK \
7341 #define HWRM_ASYNC_EVENT_CMPL_PF_VF_COMM_STATUS_CHANGE_OPAQUE_SFT 1
7342 /* 8-lsb timestamp from POR (100-msec resolution) */
7343 uint8_t timestamp_lo;
7344 /* 16-lsb timestamp from POR (100-msec resolution) */
7345 uint16_t timestamp_hi;
7346 /* Event specific data */
7347 uint32_t event_data1;
7349 * If this bit is set to 1, then it indicates that the PF-VF
7350 * communication was lost and it is established.
7351 * If this bit set to 0, then it indicates that the PF-VF
7352 * communication was established and it is lost.
7354 #define HWRM_ASYNC_EVENT_CMPL_PF_VF_COMM_STATUS_CHANGE_EVENT_DATA1_COMM_ESTABLISHED \
7358 /* hwrm_async_event_cmpl_vf_cfg_change (size:128b/16B) */
7359 struct hwrm_async_event_cmpl_vf_cfg_change {
7362 * This field indicates the exact type of the completion.
7363 * By convention, the LSB identifies the length of the
7364 * record in 16B units. Even values indicate 16B
7365 * records. Odd values indicate 32B
7368 #define HWRM_ASYNC_EVENT_CMPL_VF_CFG_CHANGE_TYPE_MASK \
7370 #define HWRM_ASYNC_EVENT_CMPL_VF_CFG_CHANGE_TYPE_SFT 0
7371 /* HWRM Asynchronous Event Information */
7372 #define HWRM_ASYNC_EVENT_CMPL_VF_CFG_CHANGE_TYPE_HWRM_ASYNC_EVENT \
7374 #define HWRM_ASYNC_EVENT_CMPL_VF_CFG_CHANGE_TYPE_LAST \
7375 HWRM_ASYNC_EVENT_CMPL_VF_CFG_CHANGE_TYPE_HWRM_ASYNC_EVENT
7376 /* Identifiers of events. */
7378 /* VF Configuration Change */
7379 #define HWRM_ASYNC_EVENT_CMPL_VF_CFG_CHANGE_EVENT_ID_VF_CFG_CHANGE \
7381 #define HWRM_ASYNC_EVENT_CMPL_VF_CFG_CHANGE_EVENT_ID_LAST \
7382 HWRM_ASYNC_EVENT_CMPL_VF_CFG_CHANGE_EVENT_ID_VF_CFG_CHANGE
7383 /* Event specific data */
7384 uint32_t event_data2;
7387 * This value is written by the NIC such that it will be different
7388 * for each pass through the completion queue. The even passes
7389 * will write 1. The odd passes will write 0.
7391 #define HWRM_ASYNC_EVENT_CMPL_VF_CFG_CHANGE_V UINT32_C(0x1)
7393 #define HWRM_ASYNC_EVENT_CMPL_VF_CFG_CHANGE_OPAQUE_MASK UINT32_C(0xfe)
7394 #define HWRM_ASYNC_EVENT_CMPL_VF_CFG_CHANGE_OPAQUE_SFT 1
7395 /* 8-lsb timestamp from POR (100-msec resolution) */
7396 uint8_t timestamp_lo;
7397 /* 16-lsb timestamp from POR (100-msec resolution) */
7398 uint16_t timestamp_hi;
7400 * Each flag provided in this field indicates a specific VF
7401 * configuration change. At least one of these flags shall be set to 1
7402 * when an asynchronous event completion of this type is provided
7405 uint32_t event_data1;
7407 * If this bit is set to 1, then the value of MTU
7408 * was changed on this VF.
7409 * If set to 0, then this bit should be ignored.
7411 #define HWRM_ASYNC_EVENT_CMPL_VF_CFG_CHANGE_EVENT_DATA1_MTU_CHANGE \
7414 * If this bit is set to 1, then the value of MRU
7415 * was changed on this VF.
7416 * If set to 0, then this bit should be ignored.
7418 #define HWRM_ASYNC_EVENT_CMPL_VF_CFG_CHANGE_EVENT_DATA1_MRU_CHANGE \
7421 * If this bit is set to 1, then the value of default MAC
7422 * address was changed on this VF.
7423 * If set to 0, then this bit should be ignored.
7425 #define HWRM_ASYNC_EVENT_CMPL_VF_CFG_CHANGE_EVENT_DATA1_DFLT_MAC_ADDR_CHANGE \
7428 * If this bit is set to 1, then the value of default VLAN
7429 * was changed on this VF.
7430 * If set to 0, then this bit should be ignored.
7432 #define HWRM_ASYNC_EVENT_CMPL_VF_CFG_CHANGE_EVENT_DATA1_DFLT_VLAN_CHANGE \
7435 * If this bit is set to 1, then the value of trusted VF enable
7436 * was changed on this VF.
7437 * If set to 0, then this bit should be ignored.
7439 #define HWRM_ASYNC_EVENT_CMPL_VF_CFG_CHANGE_EVENT_DATA1_TRUSTED_VF_CFG_CHANGE \
7443 /* hwrm_async_event_cmpl_llfc_pfc_change (size:128b/16B) */
7444 struct hwrm_async_event_cmpl_llfc_pfc_change {
7447 * This field indicates the exact type of the completion.
7448 * By convention, the LSB identifies the length of the
7449 * record in 16B units. Even values indicate 16B
7450 * records. Odd values indicate 32B
7453 #define HWRM_ASYNC_EVENT_CMPL_LLFC_PFC_CHANGE_TYPE_MASK \
7455 #define HWRM_ASYNC_EVENT_CMPL_LLFC_PFC_CHANGE_TYPE_SFT 0
7456 /* HWRM Asynchronous Event Information */
7457 #define HWRM_ASYNC_EVENT_CMPL_LLFC_PFC_CHANGE_TYPE_HWRM_ASYNC_EVENT \
7459 #define HWRM_ASYNC_EVENT_CMPL_LLFC_PFC_CHANGE_TYPE_LAST \
7460 HWRM_ASYNC_EVENT_CMPL_LLFC_PFC_CHANGE_TYPE_HWRM_ASYNC_EVENT
7461 /* unused1 is 10 b */
7462 #define HWRM_ASYNC_EVENT_CMPL_LLFC_PFC_CHANGE_UNUSED1_MASK \
7464 #define HWRM_ASYNC_EVENT_CMPL_LLFC_PFC_CHANGE_UNUSED1_SFT 6
7465 /* Identifiers of events. */
7467 /* LLFC/PFC Configuration Change */
7468 #define HWRM_ASYNC_EVENT_CMPL_LLFC_PFC_CHANGE_EVENT_ID_LLFC_PFC_CHANGE \
7470 #define HWRM_ASYNC_EVENT_CMPL_LLFC_PFC_CHANGE_EVENT_ID_LAST \
7471 HWRM_ASYNC_EVENT_CMPL_LLFC_PFC_CHANGE_EVENT_ID_LLFC_PFC_CHANGE
7472 /* Event specific data */
7473 uint32_t event_data2;
7476 * This value is written by the NIC such that it will be different
7477 * for each pass through the completion queue. The even passes
7478 * will write 1. The odd passes will write 0.
7480 #define HWRM_ASYNC_EVENT_CMPL_LLFC_PFC_CHANGE_V UINT32_C(0x1)
7482 #define HWRM_ASYNC_EVENT_CMPL_LLFC_PFC_CHANGE_OPAQUE_MASK \
7484 #define HWRM_ASYNC_EVENT_CMPL_LLFC_PFC_CHANGE_OPAQUE_SFT 1
7485 /* 8-lsb timestamp from POR (100-msec resolution) */
7486 uint8_t timestamp_lo;
7487 /* 16-lsb timestamp from POR (100-msec resolution) */
7488 uint16_t timestamp_hi;
7489 /* Event specific data */
7490 uint32_t event_data1;
7491 /* Indicates llfc pfc status change */
7492 #define HWRM_ASYNC_EVENT_CMPL_LLFC_PFC_CHANGE_EVENT_DATA1_LLFC_PFC_MASK \
7494 #define HWRM_ASYNC_EVENT_CMPL_LLFC_PFC_CHANGE_EVENT_DATA1_LLFC_PFC_SFT \
7497 * If this field set to 1, then it indicates that llfc is
7500 #define HWRM_ASYNC_EVENT_CMPL_LLFC_PFC_CHANGE_EVENT_DATA1_LLFC_PFC_LLFC \
7503 * If this field is set to 2, then it indicates that pfc
7506 #define HWRM_ASYNC_EVENT_CMPL_LLFC_PFC_CHANGE_EVENT_DATA1_LLFC_PFC_PFC \
7508 #define HWRM_ASYNC_EVENT_CMPL_LLFC_PFC_CHANGE_EVENT_DATA1_LLFC_PFC_LAST \
7509 HWRM_ASYNC_EVENT_CMPL_LLFC_PFC_CHANGE_EVENT_DATA1_LLFC_PFC_PFC
7510 /* Indicates the physical port this llfc pfc change occur */
7511 #define HWRM_ASYNC_EVENT_CMPL_LLFC_PFC_CHANGE_EVENT_DATA1_PORT_MASK \
7513 #define HWRM_ASYNC_EVENT_CMPL_LLFC_PFC_CHANGE_EVENT_DATA1_PORT_SFT \
7516 #define HWRM_ASYNC_EVENT_CMPL_LLFC_PFC_CHANGE_EVENT_DATA1_PORT_ID_MASK \
7518 #define HWRM_ASYNC_EVENT_CMPL_LLFC_PFC_CHANGE_EVENT_DATA1_PORT_ID_SFT \
7522 /* hwrm_async_event_cmpl_default_vnic_change (size:128b/16B) */
7523 struct hwrm_async_event_cmpl_default_vnic_change {
7526 * This field indicates the exact type of the completion.
7527 * By convention, the LSB identifies the length of the
7528 * record in 16B units. Even values indicate 16B
7529 * records. Odd values indicate 32B
7532 #define HWRM_ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_TYPE_MASK \
7534 #define HWRM_ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_TYPE_SFT \
7536 /* HWRM Asynchronous Event Information */
7537 #define HWRM_ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_TYPE_HWRM_ASYNC_EVENT \
7539 #define HWRM_ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_TYPE_LAST \
7540 HWRM_ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_TYPE_HWRM_ASYNC_EVENT
7541 /* unused1 is 10 b */
7542 #define HWRM_ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_UNUSED1_MASK \
7544 #define HWRM_ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_UNUSED1_SFT \
7546 /* Identifiers of events. */
7548 /* Notification of a default vnic allocation or free */
7549 #define HWRM_ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_EVENT_ID_ALLOC_FREE_NOTIFICATION \
7551 #define HWRM_ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_EVENT_ID_LAST \
7552 HWRM_ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_EVENT_ID_ALLOC_FREE_NOTIFICATION
7553 /* Event specific data */
7554 uint32_t event_data2;
7557 * This value is written by the NIC such that it will be different
7558 * for each pass through the completion queue. The even passes
7559 * will write 1. The odd passes will write 0.
7561 #define HWRM_ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_V \
7564 #define HWRM_ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_OPAQUE_MASK \
7566 #define HWRM_ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_OPAQUE_SFT 1
7567 /* 8-lsb timestamp from POR (100-msec resolution) */
7568 uint8_t timestamp_lo;
7569 /* 16-lsb timestamp from POR (100-msec resolution) */
7570 uint16_t timestamp_hi;
7571 /* Event specific data */
7572 uint32_t event_data1;
7573 /* Indicates default vnic configuration change */
7574 #define HWRM_ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_EVENT_DATA1_DEF_VNIC_STATE_MASK \
7576 #define HWRM_ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_EVENT_DATA1_DEF_VNIC_STATE_SFT \
7579 * If this field is set to 1, then it indicates that
7580 * a default VNIC has been allocate.
7582 #define HWRM_ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_EVENT_DATA1_DEF_VNIC_STATE_DEF_VNIC_ALLOC \
7585 * If this field is set to 2, then it indicates that
7586 * a default VNIC has been freed.
7588 #define HWRM_ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_EVENT_DATA1_DEF_VNIC_STATE_DEF_VNIC_FREE \
7590 #define HWRM_ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_EVENT_DATA1_DEF_VNIC_STATE_LAST \
7591 HWRM_ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_EVENT_DATA1_DEF_VNIC_STATE_DEF_VNIC_FREE
7592 /* Indicates the physical function this event occurred on. */
7593 #define HWRM_ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_EVENT_DATA1_PF_ID_MASK \
7595 #define HWRM_ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_EVENT_DATA1_PF_ID_SFT \
7597 /* Indicates the virtual function this event occurred on */
7598 #define HWRM_ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_EVENT_DATA1_VF_ID_MASK \
7600 #define HWRM_ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_EVENT_DATA1_VF_ID_SFT \
7604 /* hwrm_async_event_cmpl_hw_flow_aged (size:128b/16B) */
7605 struct hwrm_async_event_cmpl_hw_flow_aged {
7608 * This field indicates the exact type of the completion.
7609 * By convention, the LSB identifies the length of the
7610 * record in 16B units. Even values indicate 16B
7611 * records. Odd values indicate 32B
7614 #define HWRM_ASYNC_EVENT_CMPL_HW_FLOW_AGED_TYPE_MASK \
7616 #define HWRM_ASYNC_EVENT_CMPL_HW_FLOW_AGED_TYPE_SFT 0
7617 /* HWRM Asynchronous Event Information */
7618 #define HWRM_ASYNC_EVENT_CMPL_HW_FLOW_AGED_TYPE_HWRM_ASYNC_EVENT \
7620 #define HWRM_ASYNC_EVENT_CMPL_HW_FLOW_AGED_TYPE_LAST \
7621 HWRM_ASYNC_EVENT_CMPL_HW_FLOW_AGED_TYPE_HWRM_ASYNC_EVENT
7622 /* Identifiers of events. */
7624 /* Notification of a hw flow aged */
7625 #define HWRM_ASYNC_EVENT_CMPL_HW_FLOW_AGED_EVENT_ID_HW_FLOW_AGED \
7627 #define HWRM_ASYNC_EVENT_CMPL_HW_FLOW_AGED_EVENT_ID_LAST \
7628 HWRM_ASYNC_EVENT_CMPL_HW_FLOW_AGED_EVENT_ID_HW_FLOW_AGED
7629 /* Event specific data */
7630 uint32_t event_data2;
7633 * This value is written by the NIC such that it will be different
7634 * for each pass through the completion queue. The even passes
7635 * will write 1. The odd passes will write 0.
7637 #define HWRM_ASYNC_EVENT_CMPL_HW_FLOW_AGED_V UINT32_C(0x1)
7639 #define HWRM_ASYNC_EVENT_CMPL_HW_FLOW_AGED_OPAQUE_MASK UINT32_C(0xfe)
7640 #define HWRM_ASYNC_EVENT_CMPL_HW_FLOW_AGED_OPAQUE_SFT 1
7641 /* 8-lsb timestamp from POR (100-msec resolution) */
7642 uint8_t timestamp_lo;
7643 /* 16-lsb timestamp from POR (100-msec resolution) */
7644 uint16_t timestamp_hi;
7645 /* Event specific data */
7646 uint32_t event_data1;
7647 /* Indicates flow ID this event occurred on. */
7648 #define HWRM_ASYNC_EVENT_CMPL_HW_FLOW_AGED_EVENT_DATA1_FLOW_ID_MASK \
7649 UINT32_C(0x7fffffff)
7650 #define HWRM_ASYNC_EVENT_CMPL_HW_FLOW_AGED_EVENT_DATA1_FLOW_ID_SFT \
7652 /* Indicates flow direction this event occurred on. */
7653 #define HWRM_ASYNC_EVENT_CMPL_HW_FLOW_AGED_EVENT_DATA1_FLOW_DIRECTION \
7654 UINT32_C(0x80000000)
7656 * If this bit set to 0, then it indicates that the aged
7657 * event was rx flow.
7659 #define HWRM_ASYNC_EVENT_CMPL_HW_FLOW_AGED_EVENT_DATA1_FLOW_DIRECTION_RX \
7660 (UINT32_C(0x0) << 31)
7662 * If this bit is set to 1, then it indicates that the aged
7663 * event was tx flow.
7665 #define HWRM_ASYNC_EVENT_CMPL_HW_FLOW_AGED_EVENT_DATA1_FLOW_DIRECTION_TX \
7666 (UINT32_C(0x1) << 31)
7667 #define HWRM_ASYNC_EVENT_CMPL_HW_FLOW_AGED_EVENT_DATA1_FLOW_DIRECTION_LAST \
7668 HWRM_ASYNC_EVENT_CMPL_HW_FLOW_AGED_EVENT_DATA1_FLOW_DIRECTION_TX
7671 /* hwrm_async_event_cmpl_eem_cache_flush_req (size:128b/16B) */
7672 struct hwrm_async_event_cmpl_eem_cache_flush_req {
7675 * This field indicates the exact type of the completion.
7676 * By convention, the LSB identifies the length of the
7677 * record in 16B units. Even values indicate 16B
7678 * records. Odd values indicate 32B
7681 #define HWRM_ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_REQ_TYPE_MASK \
7683 #define HWRM_ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_REQ_TYPE_SFT \
7685 /* HWRM Asynchronous Event Information */
7686 #define HWRM_ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_REQ_TYPE_HWRM_ASYNC_EVENT \
7688 #define HWRM_ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_REQ_TYPE_LAST \
7689 HWRM_ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_REQ_TYPE_HWRM_ASYNC_EVENT
7690 /* Identifiers of events. */
7692 /* Notification of a eem_cache_flush request */
7693 #define HWRM_ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_REQ_EVENT_ID_EEM_CACHE_FLUSH_REQ \
7695 #define HWRM_ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_REQ_EVENT_ID_LAST \
7696 HWRM_ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_REQ_EVENT_ID_EEM_CACHE_FLUSH_REQ
7697 /* Event specific data */
7698 uint32_t event_data2;
7701 * This value is written by the NIC such that it will be different
7702 * for each pass through the completion queue. The even passes
7703 * will write 1. The odd passes will write 0.
7705 #define HWRM_ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_REQ_V \
7708 #define HWRM_ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_REQ_OPAQUE_MASK \
7710 #define HWRM_ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_REQ_OPAQUE_SFT 1
7711 /* 8-lsb timestamp from POR (100-msec resolution) */
7712 uint8_t timestamp_lo;
7713 /* 16-lsb timestamp from POR (100-msec resolution) */
7714 uint16_t timestamp_hi;
7715 /* Event specific data */
7716 uint32_t event_data1;
7719 /* hwrm_async_event_cmpl_eem_cache_flush_done (size:128b/16B) */
7720 struct hwrm_async_event_cmpl_eem_cache_flush_done {
7723 * This field indicates the exact type of the completion.
7724 * By convention, the LSB identifies the length of the
7725 * record in 16B units. Even values indicate 16B
7726 * records. Odd values indicate 32B
7729 #define HWRM_ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_DONE_TYPE_MASK \
7731 #define HWRM_ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_DONE_TYPE_SFT \
7733 /* HWRM Asynchronous Event Information */
7734 #define HWRM_ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_DONE_TYPE_HWRM_ASYNC_EVENT \
7736 #define HWRM_ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_DONE_TYPE_LAST \
7737 HWRM_ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_DONE_TYPE_HWRM_ASYNC_EVENT
7738 /* Identifiers of events. */
7741 * Notification of a host eem_cache_flush has completed. This event
7742 * is generated by the host driver.
7744 #define HWRM_ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_DONE_EVENT_ID_EEM_CACHE_FLUSH_DONE \
7746 #define HWRM_ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_DONE_EVENT_ID_LAST \
7747 HWRM_ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_DONE_EVENT_ID_EEM_CACHE_FLUSH_DONE
7748 /* Event specific data */
7749 uint32_t event_data2;
7752 * This value is written by the NIC such that it will be different
7753 * for each pass through the completion queue. The even passes
7754 * will write 1. The odd passes will write 0.
7756 #define HWRM_ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_DONE_V \
7759 #define HWRM_ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_DONE_OPAQUE_MASK \
7761 #define HWRM_ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_DONE_OPAQUE_SFT 1
7762 /* 8-lsb timestamp from POR (100-msec resolution) */
7763 uint8_t timestamp_lo;
7764 /* 16-lsb timestamp from POR (100-msec resolution) */
7765 uint16_t timestamp_hi;
7766 /* Event specific data */
7767 uint32_t event_data1;
7768 /* Indicates function ID that this event occurred on. */
7769 #define HWRM_ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_DONE_EVENT_DATA1_FID_MASK \
7771 #define HWRM_ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_DONE_EVENT_DATA1_FID_SFT \
7775 /* hwrm_async_event_cmpl_tcp_flag_action_change (size:128b/16B) */
7776 struct hwrm_async_event_cmpl_tcp_flag_action_change {
7779 * This field indicates the exact type of the completion.
7780 * By convention, the LSB identifies the length of the
7781 * record in 16B units. Even values indicate 16B
7782 * records. Odd values indicate 32B
7785 #define HWRM_ASYNC_EVENT_CMPL_TCP_FLAG_ACTION_CHANGE_TYPE_MASK \
7787 #define HWRM_ASYNC_EVENT_CMPL_TCP_FLAG_ACTION_CHANGE_TYPE_SFT \
7789 /* HWRM Asynchronous Event Information */
7790 #define HWRM_ASYNC_EVENT_CMPL_TCP_FLAG_ACTION_CHANGE_TYPE_HWRM_ASYNC_EVENT \
7792 #define HWRM_ASYNC_EVENT_CMPL_TCP_FLAG_ACTION_CHANGE_TYPE_LAST \
7793 HWRM_ASYNC_EVENT_CMPL_TCP_FLAG_ACTION_CHANGE_TYPE_HWRM_ASYNC_EVENT
7794 /* Identifiers of events. */
7796 /* Notification of tcp flag action change */
7797 #define HWRM_ASYNC_EVENT_CMPL_TCP_FLAG_ACTION_CHANGE_EVENT_ID_TCP_FLAG_ACTION_CHANGE \
7799 #define HWRM_ASYNC_EVENT_CMPL_TCP_FLAG_ACTION_CHANGE_EVENT_ID_LAST \
7800 HWRM_ASYNC_EVENT_CMPL_TCP_FLAG_ACTION_CHANGE_EVENT_ID_TCP_FLAG_ACTION_CHANGE
7801 /* Event specific data */
7802 uint32_t event_data2;
7805 * This value is written by the NIC such that it will be different
7806 * for each pass through the completion queue. The even passes
7807 * will write 1. The odd passes will write 0.
7809 #define HWRM_ASYNC_EVENT_CMPL_TCP_FLAG_ACTION_CHANGE_V \
7812 #define HWRM_ASYNC_EVENT_CMPL_TCP_FLAG_ACTION_CHANGE_OPAQUE_MASK \
7814 #define HWRM_ASYNC_EVENT_CMPL_TCP_FLAG_ACTION_CHANGE_OPAQUE_SFT 1
7815 /* 8-lsb timestamp from POR (100-msec resolution) */
7816 uint8_t timestamp_lo;
7817 /* 16-lsb timestamp from POR (100-msec resolution) */
7818 uint16_t timestamp_hi;
7819 /* Event specific data */
7820 uint32_t event_data1;
7823 /* hwrm_async_event_cmpl_eem_flow_active (size:128b/16B) */
7824 struct hwrm_async_event_cmpl_eem_flow_active {
7827 * This field indicates the exact type of the completion.
7828 * By convention, the LSB identifies the length of the
7829 * record in 16B units. Even values indicate 16B
7830 * records. Odd values indicate 32B
7833 #define HWRM_ASYNC_EVENT_CMPL_EEM_FLOW_ACTIVE_TYPE_MASK \
7835 #define HWRM_ASYNC_EVENT_CMPL_EEM_FLOW_ACTIVE_TYPE_SFT 0
7836 /* HWRM Asynchronous Event Information */
7837 #define HWRM_ASYNC_EVENT_CMPL_EEM_FLOW_ACTIVE_TYPE_HWRM_ASYNC_EVENT \
7839 #define HWRM_ASYNC_EVENT_CMPL_EEM_FLOW_ACTIVE_TYPE_LAST \
7840 HWRM_ASYNC_EVENT_CMPL_EEM_FLOW_ACTIVE_TYPE_HWRM_ASYNC_EVENT
7841 /* Identifiers of events. */
7843 /* Notification of an active eem flow */
7844 #define HWRM_ASYNC_EVENT_CMPL_EEM_FLOW_ACTIVE_EVENT_ID_EEM_FLOW_ACTIVE \
7846 #define HWRM_ASYNC_EVENT_CMPL_EEM_FLOW_ACTIVE_EVENT_ID_LAST \
7847 HWRM_ASYNC_EVENT_CMPL_EEM_FLOW_ACTIVE_EVENT_ID_EEM_FLOW_ACTIVE
7848 /* Event specific data */
7849 uint32_t event_data2;
7850 /* Indicates the 2nd global id this event occurred on. */
7851 #define HWRM_ASYNC_EVENT_CMPL_EEM_FLOW_ACTIVE_EVENT_DATA2_GLOBAL_ID_2_MASK \
7852 UINT32_C(0x3fffffff)
7853 #define HWRM_ASYNC_EVENT_CMPL_EEM_FLOW_ACTIVE_EVENT_DATA2_GLOBAL_ID_2_SFT \
7856 * Indicates flow direction of the flow identified by
7859 #define HWRM_ASYNC_EVENT_CMPL_EEM_FLOW_ACTIVE_EVENT_DATA2_FLOW_DIRECTION \
7860 UINT32_C(0x40000000)
7861 /* If this bit is set to 0, then it indicates that this rx flow. */
7862 #define HWRM_ASYNC_EVENT_CMPL_EEM_FLOW_ACTIVE_EVENT_DATA2_FLOW_DIRECTION_RX \
7863 (UINT32_C(0x0) << 30)
7864 /* If this bit is set to 1, then it indicates that this tx flow. */
7865 #define HWRM_ASYNC_EVENT_CMPL_EEM_FLOW_ACTIVE_EVENT_DATA2_FLOW_DIRECTION_TX \
7866 (UINT32_C(0x1) << 30)
7867 #define HWRM_ASYNC_EVENT_CMPL_EEM_FLOW_ACTIVE_EVENT_DATA2_FLOW_DIRECTION_LAST \
7868 HWRM_ASYNC_EVENT_CMPL_EEM_FLOW_ACTIVE_EVENT_DATA2_FLOW_DIRECTION_TX
7871 * This value is written by the NIC such that it will be different
7872 * for each pass through the completion queue. The even passes
7873 * will write 1. The odd passes will write 0.
7875 #define HWRM_ASYNC_EVENT_CMPL_EEM_FLOW_ACTIVE_V UINT32_C(0x1)
7877 #define HWRM_ASYNC_EVENT_CMPL_EEM_FLOW_ACTIVE_OPAQUE_MASK \
7879 #define HWRM_ASYNC_EVENT_CMPL_EEM_FLOW_ACTIVE_OPAQUE_SFT 1
7880 /* 8-lsb timestamp from POR (100-msec resolution) */
7881 uint8_t timestamp_lo;
7882 /* 16-lsb timestamp from POR (100-msec resolution) */
7883 uint16_t timestamp_hi;
7884 /* Event specific data */
7885 uint32_t event_data1;
7886 /* Indicates the 1st global id this event occurred on. */
7887 #define HWRM_ASYNC_EVENT_CMPL_EEM_FLOW_ACTIVE_EVENT_DATA1_GLOBAL_ID_1_MASK \
7888 UINT32_C(0x3fffffff)
7889 #define HWRM_ASYNC_EVENT_CMPL_EEM_FLOW_ACTIVE_EVENT_DATA1_GLOBAL_ID_1_SFT \
7892 * Indicates flow direction of the flow identified by the
7895 #define HWRM_ASYNC_EVENT_CMPL_EEM_FLOW_ACTIVE_EVENT_DATA1_FLOW_DIRECTION \
7896 UINT32_C(0x40000000)
7897 /* If this bit is set to 0, then it indicates that this is rx flow. */
7898 #define HWRM_ASYNC_EVENT_CMPL_EEM_FLOW_ACTIVE_EVENT_DATA1_FLOW_DIRECTION_RX \
7899 (UINT32_C(0x0) << 30)
7900 /* If this bit is set to 1, then it indicates that this is tx flow. */
7901 #define HWRM_ASYNC_EVENT_CMPL_EEM_FLOW_ACTIVE_EVENT_DATA1_FLOW_DIRECTION_TX \
7902 (UINT32_C(0x1) << 30)
7903 #define HWRM_ASYNC_EVENT_CMPL_EEM_FLOW_ACTIVE_EVENT_DATA1_FLOW_DIRECTION_LAST \
7904 HWRM_ASYNC_EVENT_CMPL_EEM_FLOW_ACTIVE_EVENT_DATA1_FLOW_DIRECTION_TX
7906 * Indicates EEM flow aging mode this event occurred on. If
7907 * this bit is set to 0, the event_data1 is the EEM global
7908 * ID. If this bit is set to 1, the event_data1 is the number
7909 * of global ID in the context memory.
7911 #define HWRM_ASYNC_EVENT_CMPL_EEM_FLOW_ACTIVE_EVENT_DATA1_MODE \
7912 UINT32_C(0x80000000)
7913 /* EEM flow aging mode 0. */
7914 #define HWRM_ASYNC_EVENT_CMPL_EEM_FLOW_ACTIVE_EVENT_DATA1_MODE_0 \
7915 (UINT32_C(0x0) << 31)
7916 /* EEM flow aging mode 1. */
7917 #define HWRM_ASYNC_EVENT_CMPL_EEM_FLOW_ACTIVE_EVENT_DATA1_MODE_1 \
7918 (UINT32_C(0x1) << 31)
7919 #define HWRM_ASYNC_EVENT_CMPL_EEM_FLOW_ACTIVE_EVENT_DATA1_MODE_LAST \
7920 HWRM_ASYNC_EVENT_CMPL_EEM_FLOW_ACTIVE_EVENT_DATA1_MODE_1
7923 /* hwrm_async_event_cmpl_eem_cfg_change (size:128b/16B) */
7924 struct hwrm_async_event_cmpl_eem_cfg_change {
7927 * This field indicates the exact type of the completion.
7928 * By convention, the LSB identifies the length of the
7929 * record in 16B units. Even values indicate 16B
7930 * records. Odd values indicate 32B
7933 #define HWRM_ASYNC_EVENT_CMPL_EEM_CFG_CHANGE_TYPE_MASK \
7935 #define HWRM_ASYNC_EVENT_CMPL_EEM_CFG_CHANGE_TYPE_SFT 0
7936 /* HWRM Asynchronous Event Information */
7937 #define HWRM_ASYNC_EVENT_CMPL_EEM_CFG_CHANGE_TYPE_HWRM_ASYNC_EVENT \
7939 #define HWRM_ASYNC_EVENT_CMPL_EEM_CFG_CHANGE_TYPE_LAST \
7940 HWRM_ASYNC_EVENT_CMPL_EEM_CFG_CHANGE_TYPE_HWRM_ASYNC_EVENT
7941 /* Identifiers of events. */
7943 /* Notification of EEM configuration change */
7944 #define HWRM_ASYNC_EVENT_CMPL_EEM_CFG_CHANGE_EVENT_ID_EEM_CFG_CHANGE \
7946 #define HWRM_ASYNC_EVENT_CMPL_EEM_CFG_CHANGE_EVENT_ID_LAST \
7947 HWRM_ASYNC_EVENT_CMPL_EEM_CFG_CHANGE_EVENT_ID_EEM_CFG_CHANGE
7948 /* Event specific data */
7949 uint32_t event_data2;
7952 * This value is written by the NIC such that it will be different
7953 * for each pass through the completion queue. The even passes
7954 * will write 1. The odd passes will write 0.
7956 #define HWRM_ASYNC_EVENT_CMPL_EEM_CFG_CHANGE_V UINT32_C(0x1)
7958 #define HWRM_ASYNC_EVENT_CMPL_EEM_CFG_CHANGE_OPAQUE_MASK UINT32_C(0xfe)
7959 #define HWRM_ASYNC_EVENT_CMPL_EEM_CFG_CHANGE_OPAQUE_SFT 1
7960 /* 8-lsb timestamp from POR (100-msec resolution) */
7961 uint8_t timestamp_lo;
7962 /* 16-lsb timestamp from POR (100-msec resolution) */
7963 uint16_t timestamp_hi;
7964 /* Event specific data */
7965 uint32_t event_data1;
7967 * Value of 1 to indicate EEM TX configuration is enabled. Value of
7968 * 0 to indicate the EEM TX configuration is disabled.
7970 #define HWRM_ASYNC_EVENT_CMPL_EEM_CFG_CHANGE_EVENT_DATA1_EEM_TX_ENABLE \
7973 * Value of 1 to indicate EEM RX configuration is enabled. Value of 0
7974 * to indicate the EEM RX configuration is disabled.
7976 #define HWRM_ASYNC_EVENT_CMPL_EEM_CFG_CHANGE_EVENT_DATA1_EEM_RX_ENABLE \
7980 /* hwrm_async_event_cmpl_quiesce_done (size:128b/16B) */
7981 struct hwrm_async_event_cmpl_quiesce_done {
7984 * This field indicates the exact type of the completion.
7985 * By convention, the LSB identifies the length of the
7986 * record in 16B units. Even values indicate 16B
7987 * records. Odd values indicate 32B
7990 #define HWRM_ASYNC_EVENT_CMPL_QUIESCE_DONE_TYPE_MASK \
7992 #define HWRM_ASYNC_EVENT_CMPL_QUIESCE_DONE_TYPE_SFT 0
7993 /* HWRM Asynchronous Event Information */
7994 #define HWRM_ASYNC_EVENT_CMPL_QUIESCE_DONE_TYPE_HWRM_ASYNC_EVENT \
7996 #define HWRM_ASYNC_EVENT_CMPL_QUIESCE_DONE_TYPE_LAST \
7997 HWRM_ASYNC_EVENT_CMPL_QUIESCE_DONE_TYPE_HWRM_ASYNC_EVENT
7998 /* Identifiers of events. */
8000 /* An event signifying completion of HWRM_FW_STATE_QUIESCE */
8001 #define HWRM_ASYNC_EVENT_CMPL_QUIESCE_DONE_EVENT_ID_QUIESCE_DONE \
8003 #define HWRM_ASYNC_EVENT_CMPL_QUIESCE_DONE_EVENT_ID_LAST \
8004 HWRM_ASYNC_EVENT_CMPL_QUIESCE_DONE_EVENT_ID_QUIESCE_DONE
8005 /* Event specific data */
8006 uint32_t event_data2;
8007 /* Status of HWRM_FW_STATE_QUIESCE completion */
8008 #define HWRM_ASYNC_EVENT_CMPL_QUIESCE_DONE_EVENT_DATA2_QUIESCE_STATUS_MASK \
8010 #define HWRM_ASYNC_EVENT_CMPL_QUIESCE_DONE_EVENT_DATA2_QUIESCE_STATUS_SFT \
8013 * The quiesce operation started by HWRM_FW_STATE_QUIESCE
8014 * completed successfully.
8016 #define HWRM_ASYNC_EVENT_CMPL_QUIESCE_DONE_EVENT_DATA2_QUIESCE_STATUS_SUCCESS \
8019 * The quiesce operation started by HWRM_FW_STATE_QUIESCE timed
8022 #define HWRM_ASYNC_EVENT_CMPL_QUIESCE_DONE_EVENT_DATA2_QUIESCE_STATUS_TIMEOUT \
8025 * The quiesce operation started by HWRM_FW_STATE_QUIESCE
8026 * encountered an error.
8028 #define HWRM_ASYNC_EVENT_CMPL_QUIESCE_DONE_EVENT_DATA2_QUIESCE_STATUS_ERROR \
8030 #define HWRM_ASYNC_EVENT_CMPL_QUIESCE_DONE_EVENT_DATA2_QUIESCE_STATUS_LAST \
8031 HWRM_ASYNC_EVENT_CMPL_QUIESCE_DONE_EVENT_DATA2_QUIESCE_STATUS_ERROR
8033 #define HWRM_ASYNC_EVENT_CMPL_QUIESCE_DONE_EVENT_DATA2_OPAQUE_MASK \
8035 #define HWRM_ASYNC_EVENT_CMPL_QUIESCE_DONE_EVENT_DATA2_OPAQUE_SFT \
8038 * Additional information about internal hardware state related to
8039 * idle/quiesce state. QUIESCE may succeed per quiesce_status
8040 * regardless of idle_state_flags. If QUIESCE fails, the host may
8041 * inspect idle_state_flags to determine whether a retry is warranted.
8043 #define HWRM_ASYNC_EVENT_CMPL_QUIESCE_DONE_EVENT_DATA2_IDLE_STATE_FLAGS_MASK \
8045 #define HWRM_ASYNC_EVENT_CMPL_QUIESCE_DONE_EVENT_DATA2_IDLE_STATE_FLAGS_SFT \
8048 * Failure to quiesce is caused by host not updating the NQ consumer
8051 #define HWRM_ASYNC_EVENT_CMPL_QUIESCE_DONE_EVENT_DATA2_IDLE_STATE_FLAGS_INCOMPLETE_NQ \
8053 /* Flag 1 indicating partial non-idle state. */
8054 #define HWRM_ASYNC_EVENT_CMPL_QUIESCE_DONE_EVENT_DATA2_IDLE_STATE_FLAGS_IDLE_STATUS_1 \
8056 /* Flag 2 indicating partial non-idle state. */
8057 #define HWRM_ASYNC_EVENT_CMPL_QUIESCE_DONE_EVENT_DATA2_IDLE_STATE_FLAGS_IDLE_STATUS_2 \
8059 /* Flag 3 indicating partial non-idle state. */
8060 #define HWRM_ASYNC_EVENT_CMPL_QUIESCE_DONE_EVENT_DATA2_IDLE_STATE_FLAGS_IDLE_STATUS_3 \
8064 * This value is written by the NIC such that it will be different
8065 * for each pass through the completion queue. The even passes
8066 * will write 1. The odd passes will write 0.
8068 #define HWRM_ASYNC_EVENT_CMPL_QUIESCE_DONE_V UINT32_C(0x1)
8070 #define HWRM_ASYNC_EVENT_CMPL_QUIESCE_DONE_OPAQUE_MASK UINT32_C(0xfe)
8071 #define HWRM_ASYNC_EVENT_CMPL_QUIESCE_DONE_OPAQUE_SFT 1
8072 /* 8-lsb timestamp from POR (100-msec resolution) */
8073 uint8_t timestamp_lo;
8074 /* 16-lsb timestamp from POR (100-msec resolution) */
8075 uint16_t timestamp_hi;
8076 /* Event specific data */
8077 uint32_t event_data1;
8078 /* Time stamp for error event */
8079 #define HWRM_ASYNC_EVENT_CMPL_QUIESCE_DONE_EVENT_DATA1_TIMESTAMP \
8083 /* hwrm_async_event_cmpl_deferred_response (size:128b/16B) */
8084 struct hwrm_async_event_cmpl_deferred_response {
8087 * This field indicates the exact type of the completion.
8088 * By convention, the LSB identifies the length of the
8089 * record in 16B units. Even values indicate 16B
8090 * records. Odd values indicate 32B
8093 #define HWRM_ASYNC_EVENT_CMPL_DEFERRED_RESPONSE_TYPE_MASK \
8095 #define HWRM_ASYNC_EVENT_CMPL_DEFERRED_RESPONSE_TYPE_SFT 0
8096 /* HWRM Asynchronous Event Information */
8097 #define HWRM_ASYNC_EVENT_CMPL_DEFERRED_RESPONSE_TYPE_HWRM_ASYNC_EVENT \
8099 #define HWRM_ASYNC_EVENT_CMPL_DEFERRED_RESPONSE_TYPE_LAST \
8100 HWRM_ASYNC_EVENT_CMPL_DEFERRED_RESPONSE_TYPE_HWRM_ASYNC_EVENT
8101 /* Identifiers of events. */
8104 * An event signifying a HWRM command is in progress and its
8105 * response will be deferred
8107 #define HWRM_ASYNC_EVENT_CMPL_DEFERRED_RESPONSE_EVENT_ID_DEFERRED_RESPONSE \
8109 #define HWRM_ASYNC_EVENT_CMPL_DEFERRED_RESPONSE_EVENT_ID_LAST \
8110 HWRM_ASYNC_EVENT_CMPL_DEFERRED_RESPONSE_EVENT_ID_DEFERRED_RESPONSE
8111 /* Event specific data */
8112 uint32_t event_data2;
8114 * The PF's mailbox is clear to issue another command.
8115 * A command with this seq_id is still in progress
8116 * and will return a regular HWRM completion when done.
8117 * 'event_data1' field, if non-zero, contains the estimated
8118 * execution time for the command.
8120 #define HWRM_ASYNC_EVENT_CMPL_DEFERRED_RESPONSE_EVENT_DATA2_SEQ_ID_MASK \
8122 #define HWRM_ASYNC_EVENT_CMPL_DEFERRED_RESPONSE_EVENT_DATA2_SEQ_ID_SFT \
8126 * This value is written by the NIC such that it will be different
8127 * for each pass through the completion queue. The even passes
8128 * will write 1. The odd passes will write 0.
8130 #define HWRM_ASYNC_EVENT_CMPL_DEFERRED_RESPONSE_V \
8133 #define HWRM_ASYNC_EVENT_CMPL_DEFERRED_RESPONSE_OPAQUE_MASK \
8135 #define HWRM_ASYNC_EVENT_CMPL_DEFERRED_RESPONSE_OPAQUE_SFT 1
8136 /* 8-lsb timestamp from POR (100-msec resolution) */
8137 uint8_t timestamp_lo;
8138 /* 16-lsb timestamp from POR (100-msec resolution) */
8139 uint16_t timestamp_hi;
8140 /* Estimated remaining time of command execution in ms (if not zero) */
8141 uint32_t event_data1;
8144 /* hwrm_async_event_cmpl_pfc_watchdog_cfg_change (size:128b/16B) */
8145 struct hwrm_async_event_cmpl_pfc_watchdog_cfg_change {
8148 * This field indicates the exact type of the completion.
8149 * By convention, the LSB identifies the length of the
8150 * record in 16B units. Even values indicate 16B
8151 * records. Odd values indicate 32B
8154 #define HWRM_ASYNC_EVENT_CMPL_PFC_WATCHDOG_CFG_CHANGE_TYPE_MASK \
8156 #define HWRM_ASYNC_EVENT_CMPL_PFC_WATCHDOG_CFG_CHANGE_TYPE_SFT \
8158 /* HWRM Asynchronous Event Information */
8159 #define HWRM_ASYNC_EVENT_CMPL_PFC_WATCHDOG_CFG_CHANGE_TYPE_HWRM_ASYNC_EVENT \
8161 #define HWRM_ASYNC_EVENT_CMPL_PFC_WATCHDOG_CFG_CHANGE_TYPE_LAST \
8162 HWRM_ASYNC_EVENT_CMPL_PFC_WATCHDOG_CFG_CHANGE_TYPE_HWRM_ASYNC_EVENT
8163 /* Identifiers of events. */
8165 /* PFC watchdog configuration change for given port/cos */
8166 #define HWRM_ASYNC_EVENT_CMPL_PFC_WATCHDOG_CFG_CHANGE_EVENT_ID_PFC_WATCHDOG_CFG_CHANGE \
8168 #define HWRM_ASYNC_EVENT_CMPL_PFC_WATCHDOG_CFG_CHANGE_EVENT_ID_LAST \
8169 HWRM_ASYNC_EVENT_CMPL_PFC_WATCHDOG_CFG_CHANGE_EVENT_ID_PFC_WATCHDOG_CFG_CHANGE
8170 /* Event specific data */
8171 uint32_t event_data2;
8174 * This value is written by the NIC such that it will be different
8175 * for each pass through the completion queue. The even passes
8176 * will write 1. The odd passes will write 0.
8178 #define HWRM_ASYNC_EVENT_CMPL_PFC_WATCHDOG_CFG_CHANGE_V \
8181 #define HWRM_ASYNC_EVENT_CMPL_PFC_WATCHDOG_CFG_CHANGE_OPAQUE_MASK \
8183 #define HWRM_ASYNC_EVENT_CMPL_PFC_WATCHDOG_CFG_CHANGE_OPAQUE_SFT 1
8184 /* 8-lsb timestamp from POR (100-msec resolution) */
8185 uint8_t timestamp_lo;
8186 /* 16-lsb timestamp from POR (100-msec resolution) */
8187 uint16_t timestamp_hi;
8188 /* Event specific data */
8189 uint32_t event_data1;
8191 * 1 in bit position X indicates PFC watchdog should
8194 #define HWRM_ASYNC_EVENT_CMPL_PFC_WATCHDOG_CFG_CHANGE_EVENT_DATA1_PFC_WD_COS_MASK \
8196 #define HWRM_ASYNC_EVENT_CMPL_PFC_WATCHDOG_CFG_CHANGE_EVENT_DATA1_PFC_WD_COS_SFT \
8198 /* 1 means PFC WD for COS0 is on, 0 - off. */
8199 #define HWRM_ASYNC_EVENT_CMPL_PFC_WATCHDOG_CFG_CHANGE_EVENT_DATA1_PFC_WD_COS_PFC_WD_COS0 \
8201 /* 1 means PFC WD for COS1 is on, 0 - off. */
8202 #define HWRM_ASYNC_EVENT_CMPL_PFC_WATCHDOG_CFG_CHANGE_EVENT_DATA1_PFC_WD_COS_PFC_WD_COS1 \
8204 /* 1 means PFC WD for COS2 is on, 0 - off. */
8205 #define HWRM_ASYNC_EVENT_CMPL_PFC_WATCHDOG_CFG_CHANGE_EVENT_DATA1_PFC_WD_COS_PFC_WD_COS2 \
8207 /* 1 means PFC WD for COS3 is on, 0 - off. */
8208 #define HWRM_ASYNC_EVENT_CMPL_PFC_WATCHDOG_CFG_CHANGE_EVENT_DATA1_PFC_WD_COS_PFC_WD_COS3 \
8210 /* 1 means PFC WD for COS4 is on, 0 - off. */
8211 #define HWRM_ASYNC_EVENT_CMPL_PFC_WATCHDOG_CFG_CHANGE_EVENT_DATA1_PFC_WD_COS_PFC_WD_COS4 \
8213 /* 1 means PFC WD for COS5 is on, 0 - off. */
8214 #define HWRM_ASYNC_EVENT_CMPL_PFC_WATCHDOG_CFG_CHANGE_EVENT_DATA1_PFC_WD_COS_PFC_WD_COS5 \
8216 /* 1 means PFC WD for COS6 is on, 0 - off. */
8217 #define HWRM_ASYNC_EVENT_CMPL_PFC_WATCHDOG_CFG_CHANGE_EVENT_DATA1_PFC_WD_COS_PFC_WD_COS6 \
8219 /* 1 means PFC WD for COS7 is on, 0 - off. */
8220 #define HWRM_ASYNC_EVENT_CMPL_PFC_WATCHDOG_CFG_CHANGE_EVENT_DATA1_PFC_WD_COS_PFC_WD_COS7 \
8223 #define HWRM_ASYNC_EVENT_CMPL_PFC_WATCHDOG_CFG_CHANGE_EVENT_DATA1_PORT_ID_MASK \
8225 #define HWRM_ASYNC_EVENT_CMPL_PFC_WATCHDOG_CFG_CHANGE_EVENT_DATA1_PORT_ID_SFT \
8229 /* hwrm_async_event_cmpl_fw_trace_msg (size:128b/16B) */
8230 struct hwrm_async_event_cmpl_fw_trace_msg {
8233 * This field indicates the exact type of the completion.
8234 * By convention, the LSB identifies the length of the
8235 * record in 16B units. Even values indicate 16B
8236 * records. Odd values indicate 32B
8239 #define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_TYPE_MASK \
8241 #define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_TYPE_SFT 0
8242 /* HWRM Asynchronous Event Information */
8243 #define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_TYPE_HWRM_ASYNC_EVENT \
8245 #define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_TYPE_LAST \
8246 HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_TYPE_HWRM_ASYNC_EVENT
8247 /* Identifiers of events. */
8249 /* Firmware trace log message */
8250 #define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_EVENT_ID_FW_TRACE_MSG \
8252 #define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_EVENT_ID_LAST \
8253 HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_EVENT_ID_FW_TRACE_MSG
8254 /* Trace byte 0 to 3 */
8255 uint32_t event_data2;
8257 #define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_EVENT_DATA2_BYTE0_MASK \
8259 #define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_EVENT_DATA2_BYTE0_SFT 0
8261 #define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_EVENT_DATA2_BYTE1_MASK \
8263 #define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_EVENT_DATA2_BYTE1_SFT 8
8265 #define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_EVENT_DATA2_BYTE2_MASK \
8267 #define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_EVENT_DATA2_BYTE2_SFT 16
8269 #define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_EVENT_DATA2_BYTE3_MASK \
8270 UINT32_C(0xff000000)
8271 #define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_EVENT_DATA2_BYTE3_SFT 24
8274 * This value is written by the NIC such that it will be different
8275 * for each pass through the completion queue. The even passes
8276 * will write 1. The odd passes will write 0.
8278 #define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_V UINT32_C(0x1)
8280 #define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_OPAQUE_MASK UINT32_C(0xfe)
8281 #define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_OPAQUE_SFT 1
8283 uint8_t timestamp_lo;
8284 /* Indicates if the string is partial or complete. */
8285 #define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_TIMESTAMP_LO_STRING \
8287 /* Complete string */
8288 #define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_TIMESTAMP_LO_STRING_COMPLETE \
8290 /* Partial string */
8291 #define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_TIMESTAMP_LO_STRING_PARTIAL \
8293 #define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_TIMESTAMP_LO_STRING_LAST \
8294 HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_TIMESTAMP_LO_STRING_PARTIAL
8295 /* Indicates the firmware that sent the trace message. */
8296 #define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_TIMESTAMP_LO_FIRMWARE \
8298 /* Primary firmware */
8299 #define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_TIMESTAMP_LO_FIRMWARE_PRIMARY \
8300 (UINT32_C(0x0) << 1)
8301 /* Secondary firmware */
8302 #define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_TIMESTAMP_LO_FIRMWARE_SECONDARY \
8303 (UINT32_C(0x1) << 1)
8304 #define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_TIMESTAMP_LO_FIRMWARE_LAST \
8305 HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_TIMESTAMP_LO_FIRMWARE_SECONDARY
8306 /* Trace byte 4 to 5 */
8307 uint16_t timestamp_hi;
8309 #define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_TIMESTAMP_HI_BYTE4_MASK \
8311 #define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_TIMESTAMP_HI_BYTE4_SFT 0
8313 #define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_TIMESTAMP_HI_BYTE5_MASK \
8315 #define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_TIMESTAMP_HI_BYTE5_SFT 8
8316 /* Trace byte 6 to 9 */
8317 uint32_t event_data1;
8319 #define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_EVENT_DATA1_BYTE6_MASK \
8321 #define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_EVENT_DATA1_BYTE6_SFT 0
8323 #define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_EVENT_DATA1_BYTE7_MASK \
8325 #define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_EVENT_DATA1_BYTE7_SFT 8
8327 #define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_EVENT_DATA1_BYTE8_MASK \
8329 #define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_EVENT_DATA1_BYTE8_SFT 16
8331 #define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_EVENT_DATA1_BYTE9_MASK \
8332 UINT32_C(0xff000000)
8333 #define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_EVENT_DATA1_BYTE9_SFT 24
8336 /* hwrm_async_event_cmpl_hwrm_error (size:128b/16B) */
8337 struct hwrm_async_event_cmpl_hwrm_error {
8340 * This field indicates the exact type of the completion.
8341 * By convention, the LSB identifies the length of the
8342 * record in 16B units. Even values indicate 16B
8343 * records. Odd values indicate 32B
8346 #define HWRM_ASYNC_EVENT_CMPL_HWRM_ERROR_TYPE_MASK \
8348 #define HWRM_ASYNC_EVENT_CMPL_HWRM_ERROR_TYPE_SFT 0
8349 /* HWRM Asynchronous Event Information */
8350 #define HWRM_ASYNC_EVENT_CMPL_HWRM_ERROR_TYPE_HWRM_ASYNC_EVENT \
8352 #define HWRM_ASYNC_EVENT_CMPL_HWRM_ERROR_TYPE_LAST \
8353 HWRM_ASYNC_EVENT_CMPL_HWRM_ERROR_TYPE_HWRM_ASYNC_EVENT
8354 /* Identifiers of events. */
8357 #define HWRM_ASYNC_EVENT_CMPL_HWRM_ERROR_EVENT_ID_HWRM_ERROR \
8359 #define HWRM_ASYNC_EVENT_CMPL_HWRM_ERROR_EVENT_ID_LAST \
8360 HWRM_ASYNC_EVENT_CMPL_HWRM_ERROR_EVENT_ID_HWRM_ERROR
8361 /* Event specific data */
8362 uint32_t event_data2;
8363 /* Severity of HWRM Error */
8364 #define HWRM_ASYNC_EVENT_CMPL_HWRM_ERROR_EVENT_DATA2_SEVERITY_MASK \
8366 #define HWRM_ASYNC_EVENT_CMPL_HWRM_ERROR_EVENT_DATA2_SEVERITY_SFT 0
8368 #define HWRM_ASYNC_EVENT_CMPL_HWRM_ERROR_EVENT_DATA2_SEVERITY_WARNING \
8370 /* Non-fatal Error */
8371 #define HWRM_ASYNC_EVENT_CMPL_HWRM_ERROR_EVENT_DATA2_SEVERITY_NONFATAL \
8374 #define HWRM_ASYNC_EVENT_CMPL_HWRM_ERROR_EVENT_DATA2_SEVERITY_FATAL \
8376 #define HWRM_ASYNC_EVENT_CMPL_HWRM_ERROR_EVENT_DATA2_SEVERITY_LAST \
8377 HWRM_ASYNC_EVENT_CMPL_HWRM_ERROR_EVENT_DATA2_SEVERITY_FATAL
8380 * This value is written by the NIC such that it will be different
8381 * for each pass through the completion queue. The even passes
8382 * will write 1. The odd passes will write 0.
8384 #define HWRM_ASYNC_EVENT_CMPL_HWRM_ERROR_V UINT32_C(0x1)
8386 #define HWRM_ASYNC_EVENT_CMPL_HWRM_ERROR_OPAQUE_MASK UINT32_C(0xfe)
8387 #define HWRM_ASYNC_EVENT_CMPL_HWRM_ERROR_OPAQUE_SFT 1
8388 /* 8-lsb timestamp from POR (100-msec resolution) */
8389 uint8_t timestamp_lo;
8390 /* 16-lsb timestamp from POR (100-msec resolution) */
8391 uint16_t timestamp_hi;
8392 /* Event specific data */
8393 uint32_t event_data1;
8394 /* Time stamp for error event */
8395 #define HWRM_ASYNC_EVENT_CMPL_HWRM_ERROR_EVENT_DATA1_TIMESTAMP \
8399 /*******************
8401 *******************/
8404 /* hwrm_func_reset_input (size:192b/24B) */
8405 struct hwrm_func_reset_input {
8406 /* The HWRM command request type. */
8409 * The completion ring to send the completion event on. This should
8410 * be the NQ ID returned from the `nq_alloc` HWRM command.
8414 * The sequence ID is used by the driver for tracking multiple
8415 * commands. This ID is treated as opaque data by the firmware and
8416 * the value is returned in the `hwrm_resp_hdr` upon completion.
8420 * The target ID of the command:
8421 * * 0x0-0xFFF8 - The function ID
8422 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
8423 * * 0xFFFD - Reserved for user-space HWRM interface
8428 * A physical address pointer pointing to a host buffer that the
8429 * command's response data will be written. This can be either a host
8430 * physical address (HPA) or a guest physical address (GPA) and must
8431 * point to a physically contiguous block of memory.
8436 * This bit must be '1' for the vf_id_valid field to be
8439 #define HWRM_FUNC_RESET_INPUT_ENABLES_VF_ID_VALID UINT32_C(0x1)
8441 * The ID of the VF that this PF is trying to reset.
8442 * Only the parent PF shall be allowed to reset a child VF.
8444 * A parent PF driver shall use this field only when a specific child VF
8445 * is requested to be reset.
8448 /* This value indicates the level of a function reset. */
8449 uint8_t func_reset_level;
8451 * Reset the caller function and its children VFs (if any). If no
8452 * children functions exist, then reset the caller function only.
8454 #define HWRM_FUNC_RESET_INPUT_FUNC_RESET_LEVEL_RESETALL \
8456 /* Reset the caller function only */
8457 #define HWRM_FUNC_RESET_INPUT_FUNC_RESET_LEVEL_RESETME \
8460 * Reset all children VFs of the caller function driver if the
8461 * caller is a PF driver.
8462 * It is an error to specify this level by a VF driver.
8463 * It is an error to specify this level by a PF driver with
8466 #define HWRM_FUNC_RESET_INPUT_FUNC_RESET_LEVEL_RESETCHILDREN \
8469 * Reset a specific VF of the caller function driver if the caller
8470 * is the parent PF driver.
8471 * It is an error to specify this level by a VF driver.
8472 * It is an error to specify this level by a PF driver that is not
8473 * the parent of the VF that is being requested to reset.
8475 #define HWRM_FUNC_RESET_INPUT_FUNC_RESET_LEVEL_RESETVF \
8477 #define HWRM_FUNC_RESET_INPUT_FUNC_RESET_LEVEL_LAST \
8478 HWRM_FUNC_RESET_INPUT_FUNC_RESET_LEVEL_RESETVF
8482 /* hwrm_func_reset_output (size:128b/16B) */
8483 struct hwrm_func_reset_output {
8484 /* The specific error status for the command. */
8485 uint16_t error_code;
8486 /* The HWRM command request type. */
8488 /* The sequence ID from the original command. */
8490 /* The length of the response data in number of bytes. */
8492 uint8_t unused_0[7];
8494 * This field is used in Output records to indicate that the output
8495 * is completely written to RAM. This field should be read as '1'
8496 * to indicate that the output has been completely written.
8497 * When writing a command completion or response to an internal processor,
8498 * the order of writes has to be such that this field is written last.
8503 /********************
8504 * hwrm_func_getfid *
8505 ********************/
8508 /* hwrm_func_getfid_input (size:192b/24B) */
8509 struct hwrm_func_getfid_input {
8510 /* The HWRM command request type. */
8513 * The completion ring to send the completion event on. This should
8514 * be the NQ ID returned from the `nq_alloc` HWRM command.
8518 * The sequence ID is used by the driver for tracking multiple
8519 * commands. This ID is treated as opaque data by the firmware and
8520 * the value is returned in the `hwrm_resp_hdr` upon completion.
8524 * The target ID of the command:
8525 * * 0x0-0xFFF8 - The function ID
8526 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
8527 * * 0xFFFD - Reserved for user-space HWRM interface
8532 * A physical address pointer pointing to a host buffer that the
8533 * command's response data will be written. This can be either a host
8534 * physical address (HPA) or a guest physical address (GPA) and must
8535 * point to a physically contiguous block of memory.
8540 * This bit must be '1' for the pci_id field to be
8543 #define HWRM_FUNC_GETFID_INPUT_ENABLES_PCI_ID UINT32_C(0x1)
8545 * This value is the PCI ID of the queried function.
8546 * If ARI is enabled, then it is
8547 * Bus Number (8b):Function Number(8b). Otherwise, it is
8548 * Bus Number (8b):Device Number (5b):Function Number(3b).
8551 uint8_t unused_0[2];
8554 /* hwrm_func_getfid_output (size:128b/16B) */
8555 struct hwrm_func_getfid_output {
8556 /* The specific error status for the command. */
8557 uint16_t error_code;
8558 /* The HWRM command request type. */
8560 /* The sequence ID from the original command. */
8562 /* The length of the response data in number of bytes. */
8565 * FID value. This value is used to identify operations on the PCI
8566 * bus as belonging to a particular PCI function.
8569 uint8_t unused_0[5];
8571 * This field is used in Output records to indicate that the output
8572 * is completely written to RAM. This field should be read as '1'
8573 * to indicate that the output has been completely written.
8574 * When writing a command completion or response to an internal processor,
8575 * the order of writes has to be such that this field is written last.
8580 /**********************
8581 * hwrm_func_vf_alloc *
8582 **********************/
8585 /* hwrm_func_vf_alloc_input (size:192b/24B) */
8586 struct hwrm_func_vf_alloc_input {
8587 /* The HWRM command request type. */
8590 * The completion ring to send the completion event on. This should
8591 * be the NQ ID returned from the `nq_alloc` HWRM command.
8595 * The sequence ID is used by the driver for tracking multiple
8596 * commands. This ID is treated as opaque data by the firmware and
8597 * the value is returned in the `hwrm_resp_hdr` upon completion.
8601 * The target ID of the command:
8602 * * 0x0-0xFFF8 - The function ID
8603 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
8604 * * 0xFFFD - Reserved for user-space HWRM interface
8609 * A physical address pointer pointing to a host buffer that the
8610 * command's response data will be written. This can be either a host
8611 * physical address (HPA) or a guest physical address (GPA) and must
8612 * point to a physically contiguous block of memory.
8617 * This bit must be '1' for the first_vf_id field to be
8620 #define HWRM_FUNC_VF_ALLOC_INPUT_ENABLES_FIRST_VF_ID UINT32_C(0x1)
8622 * This value is used to identify a Virtual Function (VF).
8623 * The scope of VF ID is local within a PF.
8625 uint16_t first_vf_id;
8626 /* The number of virtual functions requested. */
8630 /* hwrm_func_vf_alloc_output (size:128b/16B) */
8631 struct hwrm_func_vf_alloc_output {
8632 /* The specific error status for the command. */
8633 uint16_t error_code;
8634 /* The HWRM command request type. */
8636 /* The sequence ID from the original command. */
8638 /* The length of the response data in number of bytes. */
8640 /* The ID of the first VF allocated. */
8641 uint16_t first_vf_id;
8642 uint8_t unused_0[5];
8644 * This field is used in Output records to indicate that the output
8645 * is completely written to RAM. This field should be read as '1'
8646 * to indicate that the output has been completely written.
8647 * When writing a command completion or response to an internal processor,
8648 * the order of writes has to be such that this field is written last.
8653 /*********************
8654 * hwrm_func_vf_free *
8655 *********************/
8658 /* hwrm_func_vf_free_input (size:192b/24B) */
8659 struct hwrm_func_vf_free_input {
8660 /* The HWRM command request type. */
8663 * The completion ring to send the completion event on. This should
8664 * be the NQ ID returned from the `nq_alloc` HWRM command.
8668 * The sequence ID is used by the driver for tracking multiple
8669 * commands. This ID is treated as opaque data by the firmware and
8670 * the value is returned in the `hwrm_resp_hdr` upon completion.
8674 * The target ID of the command:
8675 * * 0x0-0xFFF8 - The function ID
8676 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
8677 * * 0xFFFD - Reserved for user-space HWRM interface
8682 * A physical address pointer pointing to a host buffer that the
8683 * command's response data will be written. This can be either a host
8684 * physical address (HPA) or a guest physical address (GPA) and must
8685 * point to a physically contiguous block of memory.
8690 * This bit must be '1' for the first_vf_id field to be
8693 #define HWRM_FUNC_VF_FREE_INPUT_ENABLES_FIRST_VF_ID UINT32_C(0x1)
8695 * This value is used to identify a Virtual Function (VF).
8696 * The scope of VF ID is local within a PF.
8698 uint16_t first_vf_id;
8700 * The number of virtual functions requested.
8701 * 0xFFFF - Cleanup all children of this PF.
8706 /* hwrm_func_vf_free_output (size:128b/16B) */
8707 struct hwrm_func_vf_free_output {
8708 /* The specific error status for the command. */
8709 uint16_t error_code;
8710 /* The HWRM command request type. */
8712 /* The sequence ID from the original command. */
8714 /* The length of the response data in number of bytes. */
8716 uint8_t unused_0[7];
8718 * This field is used in Output records to indicate that the output
8719 * is completely written to RAM. This field should be read as '1'
8720 * to indicate that the output has been completely written.
8721 * When writing a command completion or response to an internal processor,
8722 * the order of writes has to be such that this field is written last.
8727 /********************
8728 * hwrm_func_vf_cfg *
8729 ********************/
8732 /* hwrm_func_vf_cfg_input (size:448b/56B) */
8733 struct hwrm_func_vf_cfg_input {
8734 /* The HWRM command request type. */
8737 * The completion ring to send the completion event on. This should
8738 * be the NQ ID returned from the `nq_alloc` HWRM command.
8742 * The sequence ID is used by the driver for tracking multiple
8743 * commands. This ID is treated as opaque data by the firmware and
8744 * the value is returned in the `hwrm_resp_hdr` upon completion.
8748 * The target ID of the command:
8749 * * 0x0-0xFFF8 - The function ID
8750 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
8751 * * 0xFFFD - Reserved for user-space HWRM interface
8756 * A physical address pointer pointing to a host buffer that the
8757 * command's response data will be written. This can be either a host
8758 * physical address (HPA) or a guest physical address (GPA) and must
8759 * point to a physically contiguous block of memory.
8764 * This bit must be '1' for the mtu field to be
8767 #define HWRM_FUNC_VF_CFG_INPUT_ENABLES_MTU \
8770 * This bit must be '1' for the guest_vlan field to be
8773 #define HWRM_FUNC_VF_CFG_INPUT_ENABLES_GUEST_VLAN \
8776 * This bit must be '1' for the async_event_cr field to be
8779 #define HWRM_FUNC_VF_CFG_INPUT_ENABLES_ASYNC_EVENT_CR \
8782 * This bit must be '1' for the dflt_mac_addr field to be
8785 #define HWRM_FUNC_VF_CFG_INPUT_ENABLES_DFLT_MAC_ADDR \
8788 * This bit must be '1' for the num_rsscos_ctxs field to be
8791 #define HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_RSSCOS_CTXS \
8794 * This bit must be '1' for the num_cmpl_rings field to be
8797 #define HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_CMPL_RINGS \
8800 * This bit must be '1' for the num_tx_rings field to be
8803 #define HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_TX_RINGS \
8806 * This bit must be '1' for the num_rx_rings field to be
8809 #define HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_RX_RINGS \
8812 * This bit must be '1' for the num_l2_ctxs field to be
8815 #define HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_L2_CTXS \
8818 * This bit must be '1' for the num_vnics field to be
8821 #define HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_VNICS \
8824 * This bit must be '1' for the num_stat_ctxs field to be
8827 #define HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_STAT_CTXS \
8830 * This bit must be '1' for the num_hw_ring_grps field to be
8833 #define HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_HW_RING_GRPS \
8836 * The maximum transmission unit requested on the function.
8837 * The HWRM should make sure that the mtu of
8838 * the function does not exceed the mtu of the physical
8839 * port that this function is associated with.
8841 * In addition to requesting mtu per function, it is
8842 * possible to configure mtu per transmit ring.
8843 * By default, the mtu of each transmit ring associated
8844 * with a function is equal to the mtu of the function.
8845 * The HWRM should make sure that the mtu of each transmit
8846 * ring that is assigned to a function has a valid mtu.
8850 * The guest VLAN for the function being configured.
8851 * This field's format is same as 802.1Q Tag's
8852 * Tag Control Information (TCI) format that includes both
8853 * Priority Code Point (PCP) and VLAN Identifier (VID).
8855 uint16_t guest_vlan;
8857 * ID of the target completion ring for receiving asynchronous
8858 * event completions. If this field is not valid, then the
8859 * HWRM shall use the default completion ring of the function
8860 * that is being configured as the target completion ring for
8861 * providing any asynchronous event completions for that
8863 * If this field is valid, then the HWRM shall use the
8864 * completion ring identified by this ID as the target
8865 * completion ring for providing any asynchronous event
8866 * completions for the function that is being configured.
8868 uint16_t async_event_cr;
8870 * This value is the current MAC address requested by the VF
8871 * driver to be configured on this VF. A value of
8872 * 00-00-00-00-00-00 indicates no MAC address configuration
8873 * is requested by the VF driver.
8874 * The parent PF driver may reject or overwrite this
8877 uint8_t dflt_mac_addr[6];
8880 * This bit requests that the firmware test to see if all the assets
8881 * requested in this command (i.e. number of TX rings) are available.
8882 * The firmware will return an error if the requested assets are
8883 * not available. The firwmare will NOT reserve the assets if they
8886 #define HWRM_FUNC_VF_CFG_INPUT_FLAGS_TX_ASSETS_TEST \
8889 * This bit requests that the firmware test to see if all the assets
8890 * requested in this command (i.e. number of RX rings) are available.
8891 * The firmware will return an error if the requested assets are
8892 * not available. The firwmare will NOT reserve the assets if they
8895 #define HWRM_FUNC_VF_CFG_INPUT_FLAGS_RX_ASSETS_TEST \
8898 * This bit requests that the firmware test to see if all the assets
8899 * requested in this command (i.e. number of CMPL rings) are available.
8900 * The firmware will return an error if the requested assets are
8901 * not available. The firwmare will NOT reserve the assets if they
8904 #define HWRM_FUNC_VF_CFG_INPUT_FLAGS_CMPL_ASSETS_TEST \
8907 * This bit requests that the firmware test to see if all the assets
8908 * requested in this command (i.e. number of RSS ctx) are available.
8909 * The firmware will return an error if the requested assets are
8910 * not available. The firwmare will NOT reserve the assets if they
8913 #define HWRM_FUNC_VF_CFG_INPUT_FLAGS_RSSCOS_CTX_ASSETS_TEST \
8916 * This bit requests that the firmware test to see if all the assets
8917 * requested in this command (i.e. number of ring groups) are available.
8918 * The firmware will return an error if the requested assets are
8919 * not available. The firwmare will NOT reserve the assets if they
8922 #define HWRM_FUNC_VF_CFG_INPUT_FLAGS_RING_GRP_ASSETS_TEST \
8925 * This bit requests that the firmware test to see if all the assets
8926 * requested in this command (i.e. number of stat ctx) are available.
8927 * The firmware will return an error if the requested assets are
8928 * not available. The firwmare will NOT reserve the assets if they
8931 #define HWRM_FUNC_VF_CFG_INPUT_FLAGS_STAT_CTX_ASSETS_TEST \
8934 * This bit requests that the firmware test to see if all the assets
8935 * requested in this command (i.e. number of VNICs) are available.
8936 * The firmware will return an error if the requested assets are
8937 * not available. The firwmare will NOT reserve the assets if they
8940 #define HWRM_FUNC_VF_CFG_INPUT_FLAGS_VNIC_ASSETS_TEST \
8943 * This bit requests that the firmware test to see if all the assets
8944 * requested in this command (i.e. number of L2 ctx) are available.
8945 * The firmware will return an error if the requested assets are
8946 * not available. The firwmare will NOT reserve the assets if they
8949 #define HWRM_FUNC_VF_CFG_INPUT_FLAGS_L2_CTX_ASSETS_TEST \
8952 * If this bit is set to 1, the VF driver is requesting FW to enable
8953 * PPP TX PUSH feature on all the TX rings specified in the
8954 * num_tx_rings field. By default, the PPP TX push feature is
8955 * disabled for all the TX rings of the VF. This flag is ignored if
8956 * the num_tx_rings field is not specified or the VF doesn't support
8957 * PPP tx push feature.
8959 #define HWRM_FUNC_VF_CFG_INPUT_FLAGS_PPP_PUSH_MODE_ENABLE \
8962 * If this bit is set to 1, the VF driver is requesting FW to disable
8963 * PPP TX PUSH feature on all the TX rings of the VF. This flag is
8964 * ignored if the VF doesn't support PPP tx push feature.
8966 #define HWRM_FUNC_VF_CFG_INPUT_FLAGS_PPP_PUSH_MODE_DISABLE \
8968 /* The number of RSS/COS contexts requested for the VF. */
8969 uint16_t num_rsscos_ctxs;
8970 /* The number of completion rings requested for the VF. */
8971 uint16_t num_cmpl_rings;
8972 /* The number of transmit rings requested for the VF. */
8973 uint16_t num_tx_rings;
8974 /* The number of receive rings requested for the VF. */
8975 uint16_t num_rx_rings;
8976 /* The number of L2 contexts requested for the VF. */
8977 uint16_t num_l2_ctxs;
8978 /* The number of vnics requested for the VF. */
8980 /* The number of statistic contexts requested for the VF. */
8981 uint16_t num_stat_ctxs;
8982 /* The number of HW ring groups requested for the VF. */
8983 uint16_t num_hw_ring_grps;
8984 uint8_t unused_0[4];
8987 /* hwrm_func_vf_cfg_output (size:128b/16B) */
8988 struct hwrm_func_vf_cfg_output {
8989 /* The specific error status for the command. */
8990 uint16_t error_code;
8991 /* The HWRM command request type. */
8993 /* The sequence ID from the original command. */
8995 /* The length of the response data in number of bytes. */
8997 uint8_t unused_0[7];
8999 * This field is used in Output records to indicate that the output
9000 * is completely written to RAM. This field should be read as '1'
9001 * to indicate that the output has been completely written.
9002 * When writing a command completion or response to an internal processor,
9003 * the order of writes has to be such that this field is written last.
9008 /*******************
9010 *******************/
9013 /* hwrm_func_qcaps_input (size:192b/24B) */
9014 struct hwrm_func_qcaps_input {
9015 /* The HWRM command request type. */
9018 * The completion ring to send the completion event on. This should
9019 * be the NQ ID returned from the `nq_alloc` HWRM command.
9023 * The sequence ID is used by the driver for tracking multiple
9024 * commands. This ID is treated as opaque data by the firmware and
9025 * the value is returned in the `hwrm_resp_hdr` upon completion.
9029 * The target ID of the command:
9030 * * 0x0-0xFFF8 - The function ID
9031 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
9032 * * 0xFFFD - Reserved for user-space HWRM interface
9037 * A physical address pointer pointing to a host buffer that the
9038 * command's response data will be written. This can be either a host
9039 * physical address (HPA) or a guest physical address (GPA) and must
9040 * point to a physically contiguous block of memory.
9044 * Function ID of the function that is being queried.
9045 * 0xFF... (All Fs) if the query is for the requesting
9047 * 0xFFFE (REQUESTING_PARENT_FID) This is a special FID
9048 * to be used by a trusted VF to query its parent PF.
9051 uint8_t unused_0[6];
9054 /* hwrm_func_qcaps_output (size:704b/88B) */
9055 struct hwrm_func_qcaps_output {
9056 /* The specific error status for the command. */
9057 uint16_t error_code;
9058 /* The HWRM command request type. */
9060 /* The sequence ID from the original command. */
9062 /* The length of the response data in number of bytes. */
9065 * FID value. This value is used to identify operations on the PCI
9066 * bus as belonging to a particular PCI function.
9070 * Port ID of port that this function is associated with.
9071 * Valid only for the PF.
9072 * 0xFF... (All Fs) if this function is not associated with
9074 * 0xFF... (All Fs) if this function is called from a VF.
9078 /* If 1, then Push mode is supported on this function. */
9079 #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_PUSH_MODE_SUPPORTED \
9082 * If 1, then the global MSI-X auto-masking is enabled for the
9085 #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_GLOBAL_MSIX_AUTOMASKING \
9088 * If 1, then the Precision Time Protocol (PTP) processing
9089 * is supported on this function.
9090 * The HWRM should enable PTP on only a single Physical
9091 * Function (PF) per port.
9093 #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_PTP_SUPPORTED \
9096 * If 1, then RDMA over Converged Ethernet (RoCE) v1
9097 * is supported on this function.
9099 #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_ROCE_V1_SUPPORTED \
9102 * If 1, then RDMA over Converged Ethernet (RoCE) v2
9103 * is supported on this function.
9105 #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_ROCE_V2_SUPPORTED \
9108 * If 1, then control and configuration of WoL magic packet
9109 * are supported on this function.
9111 #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_WOL_MAGICPKT_SUPPORTED \
9114 * If 1, then control and configuration of bitmap pattern
9115 * packet are supported on this function.
9117 #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_WOL_BMP_SUPPORTED \
9120 * If set to 1, then the control and configuration of rate limit
9121 * of an allocated TX ring on the queried function is supported.
9123 #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_TX_RING_RL_SUPPORTED \
9126 * If 1, then control and configuration of minimum and
9127 * maximum bandwidths are supported on the queried function.
9129 #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_TX_BW_CFG_SUPPORTED \
9132 * If the query is for a VF, then this flag shall be ignored.
9133 * If this query is for a PF and this flag is set to 1,
9134 * then the PF has the capability to set the rate limits
9135 * on the TX rings of its children VFs.
9136 * If this query is for a PF and this flag is set to 0, then
9137 * the PF does not have the capability to set the rate limits
9138 * on the TX rings of its children VFs.
9140 #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_VF_TX_RING_RL_SUPPORTED \
9143 * If the query is for a VF, then this flag shall be ignored.
9144 * If this query is for a PF and this flag is set to 1,
9145 * then the PF has the capability to set the minimum and/or
9146 * maximum bandwidths for its children VFs.
9147 * If this query is for a PF and this flag is set to 0, then
9148 * the PF does not have the capability to set the minimum or
9149 * maximum bandwidths for its children VFs.
9151 #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_VF_BW_CFG_SUPPORTED \
9154 * Standard TX Ring mode is used for the allocation of TX ring
9155 * and underlying scheduling resources that allow bandwidth
9156 * reservation and limit settings on the queried function.
9157 * If set to 1, then standard TX ring mode is supported
9158 * on the queried function.
9159 * If set to 0, then standard TX ring mode is not available
9160 * on the queried function.
9162 #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_STD_TX_RING_MODE_SUPPORTED \
9165 * If the query is for a VF, then this flag shall be ignored,
9166 * If this query is for a PF and this flag is set to 1,
9167 * then the PF has the capability to detect GENEVE tunnel
9170 #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_GENEVE_TUN_FLAGS_SUPPORTED \
9173 * If the query is for a VF, then this flag shall be ignored,
9174 * If this query is for a PF and this flag is set to 1,
9175 * then the PF has the capability to detect NVGRE tunnel
9178 #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_NVGRE_TUN_FLAGS_SUPPORTED \
9181 * If the query is for a VF, then this flag shall be ignored,
9182 * If this query is for a PF and this flag is set to 1,
9183 * then the PF has the capability to detect GRE tunnel
9186 #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_GRE_TUN_FLAGS_SUPPORTED \
9189 * If the query is for a VF, then this flag shall be ignored,
9190 * If this query is for a PF and this flag is set to 1,
9191 * then the PF has the capability to detect MPLS tunnel
9194 #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_MPLS_TUN_FLAGS_SUPPORTED \
9197 * If the query is for a VF, then this flag shall be ignored,
9198 * If this query is for a PF and this flag is set to 1,
9199 * then the PF has the capability to support pcie stats.
9201 #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_PCIE_STATS_SUPPORTED \
9204 * If the query is for a VF, then this flag shall be ignored,
9205 * If this query is for a PF and this flag is set to 1,
9206 * then the PF has the capability to adopt the VF's belonging
9209 #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_ADOPTED_PF_SUPPORTED \
9212 * If the query is for a VF, then this flag shall be ignored,
9213 * If this query is for a PF and this flag is set to 1,
9214 * then the PF has the administrative privilege to configure another PF
9216 #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_ADMIN_PF_SUPPORTED \
9219 * If the query is for a VF, then this flag shall be ignored.
9220 * If this query is for a PF and this flag is set to 1, then
9221 * the PF will know that the firmware has the capability to track
9222 * the virtual link status.
9224 #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_LINK_ADMIN_STATUS_SUPPORTED \
9227 * If 1, then this function supports the push mode that uses
9228 * write combine buffers and the long inline tx buffer descriptor.
9230 #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_WCB_PUSH_MODE \
9233 * If 1, then FW has capability to allocate TX rings dynamically
9234 * in ring alloc even if PF reserved pool is zero.
9235 * This bit will be used only for PFs.
9237 #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_DYNAMIC_TX_RING_ALLOC \
9240 * When this bit is '1', it indicates that core firmware is
9241 * capable of Hot Reset.
9243 #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_HOT_RESET_CAPABLE \
9246 * This flag will be set to 1 by the FW if FW supports adapter error
9249 #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_ERROR_RECOVERY_CAPABLE \
9252 * If the query is for a VF, then this flag shall be ignored.
9253 * If this query is for a PF and this flag is set to 1, then
9254 * the PF has the capability to support extended stats.
9256 #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_EXT_STATS_SUPPORTED \
9259 * If the query is for a VF, then this flag shall be ignored.
9260 * If this query is for a PF and this flag is set to 1, then host
9261 * must initiate reset or reload (or fastboot) the firmware image
9262 * upon detection of device shutdown state.
9264 #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_ERR_RECOVER_RELOAD \
9267 * If the query is for a VF, then this flag (always set to 0) shall
9268 * be ignored. If this query is for a PF and this flag is set to 1,
9269 * host, when registered for the default vnic change async event,
9270 * receives async notification whenever a default vnic state is
9271 * changed for any of child or adopted VFs.
9273 #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_NOTIFY_VF_DEF_VNIC_CHNG_SUPPORTED \
9275 /* If set to 1, then the vlan acceleration for TX is disabled. */
9276 #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_VLAN_ACCELERATION_TX_DISABLED \
9279 * When this bit is '1', it indicates that core firmware supports
9280 * DBG_COREDUMP_XXX commands.
9282 #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_COREDUMP_CMD_SUPPORTED \
9283 UINT32_C(0x10000000)
9285 * When this bit is '1', it indicates that core firmware supports
9286 * DBG_CRASHDUMP_XXX commands.
9288 #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_CRASHDUMP_CMD_SUPPORTED \
9289 UINT32_C(0x20000000)
9291 * If the query is for a VF, then this flag should be ignored.
9292 * If the query is for a PF and this flag is set to 1, then
9293 * the PF has the capability to support retrieval of
9294 * rx_port_stats_ext_pfc_wd statistics (supported by the PFC
9295 * WatchDog feature) via the hwrm_port_qstats_ext_pfc_wd command.
9296 * If this flag is set to 1, only that (supported) command should
9297 * be used for retrieval of PFC related statistics (rather than
9298 * hwrm_port_qstats_ext command, which could previously be used).
9300 #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_PFC_WD_STATS_SUPPORTED \
9301 UINT32_C(0x40000000)
9303 * When this bit is '1', it indicates that core firmware supports
9306 #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_DBG_QCAPS_CMD_SUPPORTED \
9307 UINT32_C(0x80000000)
9309 * This value is current MAC address configured for this
9310 * function. A value of 00-00-00-00-00-00 indicates no
9311 * MAC address is currently configured.
9313 uint8_t mac_address[6];
9315 * The maximum number of RSS/COS contexts that can be
9316 * allocated to the function.
9318 uint16_t max_rsscos_ctx;
9320 * The maximum number of completion rings that can be
9321 * allocated to the function.
9323 uint16_t max_cmpl_rings;
9325 * The maximum number of transmit rings that can be
9326 * allocated to the function.
9328 uint16_t max_tx_rings;
9330 * The maximum number of receive rings that can be
9331 * allocated to the function.
9333 uint16_t max_rx_rings;
9335 * The maximum number of L2 contexts that can be
9336 * allocated to the function.
9338 uint16_t max_l2_ctxs;
9340 * The maximum number of VNICs that can be
9341 * allocated to the function.
9345 * The identifier for the first VF enabled on a PF. This
9346 * is valid only on the PF with SR-IOV enabled.
9347 * 0xFF... (All Fs) if this command is called on a PF with
9348 * SR-IOV disabled or on a VF.
9350 uint16_t first_vf_id;
9352 * The maximum number of VFs that can be
9353 * allocated to the function. This is valid only on the
9354 * PF with SR-IOV enabled. 0xFF... (All Fs) if this
9355 * command is called on a PF with SR-IOV disabled or
9360 * The maximum number of statistic contexts that can be
9361 * allocated to the function.
9363 uint16_t max_stat_ctx;
9365 * The maximum number of Encapsulation records that can be
9366 * offloaded by this function.
9368 uint32_t max_encap_records;
9370 * The maximum number of decapsulation records that can
9371 * be offloaded by this function.
9373 uint32_t max_decap_records;
9375 * The maximum number of Exact Match (EM) flows that can be
9376 * offloaded by this function on the TX side.
9378 uint32_t max_tx_em_flows;
9380 * The maximum number of Wildcard Match (WM) flows that can
9381 * be offloaded by this function on the TX side.
9383 uint32_t max_tx_wm_flows;
9385 * The maximum number of Exact Match (EM) flows that can be
9386 * offloaded by this function on the RX side.
9388 uint32_t max_rx_em_flows;
9390 * The maximum number of Wildcard Match (WM) flows that can
9391 * be offloaded by this function on the RX side.
9393 uint32_t max_rx_wm_flows;
9395 * The maximum number of multicast filters that can
9396 * be supported by this function on the RX side.
9398 uint32_t max_mcast_filters;
9400 * The maximum value of flow_id that can be supported
9401 * in completion records.
9403 uint32_t max_flow_id;
9405 * The maximum number of HW ring groups that can be
9406 * supported on this function.
9408 uint32_t max_hw_ring_grps;
9410 * The maximum number of strict priority transmit rings
9411 * that can be allocated to the function.
9412 * This number indicates the maximum number of TX rings
9413 * that can be assigned strict priorities out of the
9414 * maximum number of TX rings that can be allocated
9415 * (max_tx_rings) to the function.
9417 uint16_t max_sp_tx_rings;
9418 uint8_t unused_0[2];
9421 * If 1, the device can be configured to set the ECN bits in the
9422 * IP header of received packets if the receive queue length
9423 * exceeds a given threshold.
9425 #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_EXT_ECN_MARK_SUPPORTED \
9428 * If 1, the device can report the number of received packets
9429 * that it marked as having experienced congestion.
9431 #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_EXT_ECN_STATS_SUPPORTED \
9434 * If 1, the device can report extended hw statistics (including
9435 * additional tpa statistics).
9437 #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_EXT_EXT_HW_STATS_SUPPORTED \
9440 * If set to 1, then the core firmware has support to enable/
9441 * disable hot reset support for interface dynamically through
9444 #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_EXT_HOT_RESET_IF_SUPPORT \
9446 /* If 1, the proxy mode is supported on this function */
9447 #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_EXT_PROXY_MODE_SUPPORT \
9450 * If 1, the tx rings source interface override feature is supported
9453 #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_EXT_TX_PROXY_SRC_INTF_OVERRIDE_SUPPORT \
9456 * If 1, the device supports scheduler queues. SCHQs can be managed
9457 * using RING_SCHQ_ALLOC/CFG/FREE commands.
9459 #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_EXT_SCHQ_SUPPORTED \
9462 * If set to 1, then this function supports the TX push mode that
9463 * uses ping-pong buffers from the push pages.
9465 #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_EXT_PPP_PUSH_MODE_SUPPORTED \
9467 /* The maximum number of SCHQs supported by this device. */
9469 uint8_t unused_1[2];
9471 * This field is used in Output records to indicate that the output
9472 * is completely written to RAM. This field should be read as '1'
9473 * to indicate that the output has been completely written.
9474 * When writing a command completion or response to an internal processor,
9475 * the order of writes has to be such that this field is written last.
9485 /* hwrm_func_qcfg_input (size:192b/24B) */
9486 struct hwrm_func_qcfg_input {
9487 /* The HWRM command request type. */
9490 * The completion ring to send the completion event on. This should
9491 * be the NQ ID returned from the `nq_alloc` HWRM command.
9495 * The sequence ID is used by the driver for tracking multiple
9496 * commands. This ID is treated as opaque data by the firmware and
9497 * the value is returned in the `hwrm_resp_hdr` upon completion.
9501 * The target ID of the command:
9502 * * 0x0-0xFFF8 - The function ID
9503 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
9504 * * 0xFFFD - Reserved for user-space HWRM interface
9509 * A physical address pointer pointing to a host buffer that the
9510 * command's response data will be written. This can be either a host
9511 * physical address (HPA) or a guest physical address (GPA) and must
9512 * point to a physically contiguous block of memory.
9516 * Function ID of the function that is being queried.
9517 * 0xFF... (All Fs) if the query is for the requesting
9519 * 0xFFFE (REQUESTING_PARENT_FID) This is a special FID
9520 * to be used by a trusted VF to query its parent PF.
9523 uint8_t unused_0[6];
9526 /* hwrm_func_qcfg_output (size:768b/96B) */
9527 struct hwrm_func_qcfg_output {
9528 /* The specific error status for the command. */
9529 uint16_t error_code;
9530 /* The HWRM command request type. */
9532 /* The sequence ID from the original command. */
9534 /* The length of the response data in number of bytes. */
9537 * FID value. This value is used to identify operations on the PCI
9538 * bus as belonging to a particular PCI function.
9542 * Port ID of port that this function is associated with.
9543 * 0xFF... (All Fs) if this function is not associated with
9548 * This value is the current VLAN setting for this
9549 * function. The value of 0 for this field indicates
9550 * no priority tagging or VLAN is used.
9551 * This field's format is same as 802.1Q Tag's
9552 * Tag Control Information (TCI) format that includes both
9553 * Priority Code Point (PCP) and VLAN Identifier (VID).
9558 * If 1, then magic packet based Out-Of-Box WoL is enabled on
9559 * the port associated with this function.
9561 #define HWRM_FUNC_QCFG_OUTPUT_FLAGS_OOB_WOL_MAGICPKT_ENABLED \
9564 * If 1, then bitmap pattern based Out-Of-Box WoL packet is enabled
9565 * on the port associated with this function.
9567 #define HWRM_FUNC_QCFG_OUTPUT_FLAGS_OOB_WOL_BMP_ENABLED \
9570 * If set to 1, then FW based DCBX agent is enabled and running on
9571 * the port associated with this function.
9572 * If set to 0, then DCBX agent is not running in the firmware.
9574 #define HWRM_FUNC_QCFG_OUTPUT_FLAGS_FW_DCBX_AGENT_ENABLED \
9577 * Standard TX Ring mode is used for the allocation of TX ring
9578 * and underlying scheduling resources that allow bandwidth
9579 * reservation and limit settings on the queried function.
9580 * If set to 1, then standard TX ring mode is enabled
9581 * on the queried function.
9582 * If set to 0, then the standard TX ring mode is disabled
9583 * on the queried function. In this extended TX ring resource
9584 * mode, the minimum and maximum bandwidth settings are not
9585 * supported to allow the allocation of TX rings to span multiple
9588 #define HWRM_FUNC_QCFG_OUTPUT_FLAGS_STD_TX_RING_MODE_ENABLED \
9591 * If set to 1 then FW based LLDP agent is enabled and running on
9592 * the port associated with this function.
9593 * If set to 0 then the LLDP agent is not running in the firmware.
9595 #define HWRM_FUNC_QCFG_OUTPUT_FLAGS_FW_LLDP_AGENT_ENABLED \
9598 * If set to 1, then multi-host mode is active for this function.
9599 * If set to 0, then multi-host mode is inactive for this function
9600 * or not applicable for this device.
9602 #define HWRM_FUNC_QCFG_OUTPUT_FLAGS_MULTI_HOST \
9605 * If the function that is being queried is a PF, then the HWRM shall
9606 * set this field to 0 and the HWRM client shall ignore this field.
9607 * If the function that is being queried is a VF, then the HWRM shall
9608 * set this field to 1 if the queried VF is trusted, otherwise the HWRM
9609 * shall set this field to 0.
9611 #define HWRM_FUNC_QCFG_OUTPUT_FLAGS_TRUSTED_VF \
9614 * If set to 1, then secure mode is enabled for this function or device.
9615 * If set to 0, then secure mode is disabled (or normal mode) for this
9616 * function or device.
9618 #define HWRM_FUNC_QCFG_OUTPUT_FLAGS_SECURE_MODE_ENABLED \
9621 * If set to 1, then this PF is enabled with a preboot driver that
9622 * requires access to the legacy L2 ring model and legacy 32b
9623 * doorbells. If set to 0, then this PF is not allowed to use
9624 * the legacy L2 rings. This feature is not allowed on VFs and
9625 * is only relevant for devices that require a context backing
9628 #define HWRM_FUNC_QCFG_OUTPUT_FLAGS_PREBOOT_LEGACY_L2_RINGS \
9631 * If set to 1, then the firmware and all currently registered driver
9632 * instances support hot reset. The hot reset support will be updated
9633 * dynamically based on the driver interface advertisement.
9634 * If set to 0, then the adapter is not currently able to initiate
9637 #define HWRM_FUNC_QCFG_OUTPUT_FLAGS_HOT_RESET_ALLOWED \
9640 * If set to 1, then the PPP tx push mode is enabled for all the
9641 * reserved TX rings of this function. If set to 0, then PPP tx push
9642 * mode is disabled for all the reserved TX rings of this function.
9644 #define HWRM_FUNC_QCFG_OUTPUT_FLAGS_PPP_PUSH_MODE_ENABLED \
9647 * This value is current MAC address configured for this
9648 * function. A value of 00-00-00-00-00-00 indicates no
9649 * MAC address is currently configured.
9651 uint8_t mac_address[6];
9653 * This value is current PCI ID of this
9654 * function. If ARI is enabled, then it is
9655 * Bus Number (8b):Function Number(8b). Otherwise, it is
9656 * Bus Number (8b):Device Number (4b):Function Number(4b).
9657 * If multi-host mode is active, the 4 lsb will indicate
9658 * the PF index for this function.
9662 * The number of RSS/COS contexts currently
9663 * allocated to the function.
9665 uint16_t alloc_rsscos_ctx;
9667 * The number of completion rings currently allocated to
9668 * the function. This does not include the rings allocated
9669 * to any children functions if any.
9671 uint16_t alloc_cmpl_rings;
9673 * The number of transmit rings currently allocated to
9674 * the function. This does not include the rings allocated
9675 * to any children functions if any.
9677 uint16_t alloc_tx_rings;
9679 * The number of receive rings currently allocated to
9680 * the function. This does not include the rings allocated
9681 * to any children functions if any.
9683 uint16_t alloc_rx_rings;
9684 /* The allocated number of L2 contexts to the function. */
9685 uint16_t alloc_l2_ctx;
9686 /* The allocated number of vnics to the function. */
9687 uint16_t alloc_vnics;
9689 * The maximum transmission unit of the function.
9690 * If the reported mtu value is non-zero then it will used for the
9691 * rings allocated on this function. otherwise the default
9692 * value is used if ring MTU is not specified.
9696 * The maximum receive unit of the function.
9697 * For vnics allocated on this function, this default
9698 * value is used if vnic MRU is not specified.
9701 /* The statistics context assigned to a function. */
9702 uint16_t stat_ctx_id;
9704 * The HWRM shall return Unknown value for this field
9705 * when this command is used to query VF's configuration.
9707 uint8_t port_partition_type;
9708 /* Single physical function */
9709 #define HWRM_FUNC_QCFG_OUTPUT_PORT_PARTITION_TYPE_SPF UINT32_C(0x0)
9710 /* Multiple physical functions */
9711 #define HWRM_FUNC_QCFG_OUTPUT_PORT_PARTITION_TYPE_MPFS UINT32_C(0x1)
9712 /* Network Partitioning 1.0 */
9713 #define HWRM_FUNC_QCFG_OUTPUT_PORT_PARTITION_TYPE_NPAR1_0 UINT32_C(0x2)
9714 /* Network Partitioning 1.5 */
9715 #define HWRM_FUNC_QCFG_OUTPUT_PORT_PARTITION_TYPE_NPAR1_5 UINT32_C(0x3)
9716 /* Network Partitioning 2.0 */
9717 #define HWRM_FUNC_QCFG_OUTPUT_PORT_PARTITION_TYPE_NPAR2_0 UINT32_C(0x4)
9719 #define HWRM_FUNC_QCFG_OUTPUT_PORT_PARTITION_TYPE_UNKNOWN \
9721 #define HWRM_FUNC_QCFG_OUTPUT_PORT_PARTITION_TYPE_LAST \
9722 HWRM_FUNC_QCFG_OUTPUT_PORT_PARTITION_TYPE_UNKNOWN
9724 * This field will indicate number of physical functions on this port_partition.
9725 * HWRM shall return unavail (i.e. value of 0) for this field
9726 * when this command is used to query VF's configuration or
9727 * from older firmware that doesn't support this field.
9729 uint8_t port_pf_cnt;
9730 /* number of PFs is not available */
9731 #define HWRM_FUNC_QCFG_OUTPUT_PORT_PF_CNT_UNAVAIL UINT32_C(0x0)
9732 #define HWRM_FUNC_QCFG_OUTPUT_PORT_PF_CNT_LAST \
9733 HWRM_FUNC_QCFG_OUTPUT_PORT_PF_CNT_UNAVAIL
9735 * The default VNIC ID assigned to a function that is
9738 uint16_t dflt_vnic_id;
9739 uint16_t max_mtu_configured;
9741 * Minimum BW allocated for this function.
9742 * The HWRM will translate this value into byte counter and
9743 * time interval used for the scheduler inside the device.
9744 * A value of 0 indicates the minimum bandwidth is not
9748 /* The bandwidth value. */
9749 #define HWRM_FUNC_QCFG_OUTPUT_MIN_BW_BW_VALUE_MASK \
9751 #define HWRM_FUNC_QCFG_OUTPUT_MIN_BW_BW_VALUE_SFT 0
9752 /* The granularity of the value (bits or bytes). */
9753 #define HWRM_FUNC_QCFG_OUTPUT_MIN_BW_SCALE \
9754 UINT32_C(0x10000000)
9755 /* Value is in bits. */
9756 #define HWRM_FUNC_QCFG_OUTPUT_MIN_BW_SCALE_BITS \
9757 (UINT32_C(0x0) << 28)
9758 /* Value is in bytes. */
9759 #define HWRM_FUNC_QCFG_OUTPUT_MIN_BW_SCALE_BYTES \
9760 (UINT32_C(0x1) << 28)
9761 #define HWRM_FUNC_QCFG_OUTPUT_MIN_BW_SCALE_LAST \
9762 HWRM_FUNC_QCFG_OUTPUT_MIN_BW_SCALE_BYTES
9763 /* bw_value_unit is 3 b */
9764 #define HWRM_FUNC_QCFG_OUTPUT_MIN_BW_BW_VALUE_UNIT_MASK \
9765 UINT32_C(0xe0000000)
9766 #define HWRM_FUNC_QCFG_OUTPUT_MIN_BW_BW_VALUE_UNIT_SFT 29
9767 /* Value is in Mb or MB (base 10). */
9768 #define HWRM_FUNC_QCFG_OUTPUT_MIN_BW_BW_VALUE_UNIT_MEGA \
9769 (UINT32_C(0x0) << 29)
9770 /* Value is in Kb or KB (base 10). */
9771 #define HWRM_FUNC_QCFG_OUTPUT_MIN_BW_BW_VALUE_UNIT_KILO \
9772 (UINT32_C(0x2) << 29)
9773 /* Value is in bits or bytes. */
9774 #define HWRM_FUNC_QCFG_OUTPUT_MIN_BW_BW_VALUE_UNIT_BASE \
9775 (UINT32_C(0x4) << 29)
9776 /* Value is in Gb or GB (base 10). */
9777 #define HWRM_FUNC_QCFG_OUTPUT_MIN_BW_BW_VALUE_UNIT_GIGA \
9778 (UINT32_C(0x6) << 29)
9779 /* Value is in 1/100th of a percentage of total bandwidth. */
9780 #define HWRM_FUNC_QCFG_OUTPUT_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 \
9781 (UINT32_C(0x1) << 29)
9783 #define HWRM_FUNC_QCFG_OUTPUT_MIN_BW_BW_VALUE_UNIT_INVALID \
9784 (UINT32_C(0x7) << 29)
9785 #define HWRM_FUNC_QCFG_OUTPUT_MIN_BW_BW_VALUE_UNIT_LAST \
9786 HWRM_FUNC_QCFG_OUTPUT_MIN_BW_BW_VALUE_UNIT_INVALID
9788 * Maximum BW allocated for this function.
9789 * The HWRM will translate this value into byte counter and
9790 * time interval used for the scheduler inside the device.
9791 * A value of 0 indicates that the maximum bandwidth is not
9795 /* The bandwidth value. */
9796 #define HWRM_FUNC_QCFG_OUTPUT_MAX_BW_BW_VALUE_MASK \
9798 #define HWRM_FUNC_QCFG_OUTPUT_MAX_BW_BW_VALUE_SFT 0
9799 /* The granularity of the value (bits or bytes). */
9800 #define HWRM_FUNC_QCFG_OUTPUT_MAX_BW_SCALE \
9801 UINT32_C(0x10000000)
9802 /* Value is in bits. */
9803 #define HWRM_FUNC_QCFG_OUTPUT_MAX_BW_SCALE_BITS \
9804 (UINT32_C(0x0) << 28)
9805 /* Value is in bytes. */
9806 #define HWRM_FUNC_QCFG_OUTPUT_MAX_BW_SCALE_BYTES \
9807 (UINT32_C(0x1) << 28)
9808 #define HWRM_FUNC_QCFG_OUTPUT_MAX_BW_SCALE_LAST \
9809 HWRM_FUNC_QCFG_OUTPUT_MAX_BW_SCALE_BYTES
9810 /* bw_value_unit is 3 b */
9811 #define HWRM_FUNC_QCFG_OUTPUT_MAX_BW_BW_VALUE_UNIT_MASK \
9812 UINT32_C(0xe0000000)
9813 #define HWRM_FUNC_QCFG_OUTPUT_MAX_BW_BW_VALUE_UNIT_SFT 29
9814 /* Value is in Mb or MB (base 10). */
9815 #define HWRM_FUNC_QCFG_OUTPUT_MAX_BW_BW_VALUE_UNIT_MEGA \
9816 (UINT32_C(0x0) << 29)
9817 /* Value is in Kb or KB (base 10). */
9818 #define HWRM_FUNC_QCFG_OUTPUT_MAX_BW_BW_VALUE_UNIT_KILO \
9819 (UINT32_C(0x2) << 29)
9820 /* Value is in bits or bytes. */
9821 #define HWRM_FUNC_QCFG_OUTPUT_MAX_BW_BW_VALUE_UNIT_BASE \
9822 (UINT32_C(0x4) << 29)
9823 /* Value is in Gb or GB (base 10). */
9824 #define HWRM_FUNC_QCFG_OUTPUT_MAX_BW_BW_VALUE_UNIT_GIGA \
9825 (UINT32_C(0x6) << 29)
9826 /* Value is in 1/100th of a percentage of total bandwidth. */
9827 #define HWRM_FUNC_QCFG_OUTPUT_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 \
9828 (UINT32_C(0x1) << 29)
9830 #define HWRM_FUNC_QCFG_OUTPUT_MAX_BW_BW_VALUE_UNIT_INVALID \
9831 (UINT32_C(0x7) << 29)
9832 #define HWRM_FUNC_QCFG_OUTPUT_MAX_BW_BW_VALUE_UNIT_LAST \
9833 HWRM_FUNC_QCFG_OUTPUT_MAX_BW_BW_VALUE_UNIT_INVALID
9835 * This value indicates the Edge virtual bridge mode for the
9836 * domain that this function belongs to.
9839 /* No Edge Virtual Bridging (EVB) */
9840 #define HWRM_FUNC_QCFG_OUTPUT_EVB_MODE_NO_EVB UINT32_C(0x0)
9841 /* Virtual Ethernet Bridge (VEB) */
9842 #define HWRM_FUNC_QCFG_OUTPUT_EVB_MODE_VEB UINT32_C(0x1)
9843 /* Virtual Ethernet Port Aggregator (VEPA) */
9844 #define HWRM_FUNC_QCFG_OUTPUT_EVB_MODE_VEPA UINT32_C(0x2)
9845 #define HWRM_FUNC_QCFG_OUTPUT_EVB_MODE_LAST \
9846 HWRM_FUNC_QCFG_OUTPUT_EVB_MODE_VEPA
9849 * This value indicates the PCIE device cache line size.
9850 * The cache line size allows the DMA writes to terminate and
9851 * start at the cache boundary.
9853 #define HWRM_FUNC_QCFG_OUTPUT_OPTIONS_CACHE_LINESIZE_MASK \
9855 #define HWRM_FUNC_QCFG_OUTPUT_OPTIONS_CACHE_LINESIZE_SFT 0
9856 /* Cache Line Size 64 bytes */
9857 #define HWRM_FUNC_QCFG_OUTPUT_OPTIONS_CACHE_LINESIZE_SIZE_64 \
9859 /* Cache Line Size 128 bytes */
9860 #define HWRM_FUNC_QCFG_OUTPUT_OPTIONS_CACHE_LINESIZE_SIZE_128 \
9862 #define HWRM_FUNC_QCFG_OUTPUT_OPTIONS_CACHE_LINESIZE_LAST \
9863 HWRM_FUNC_QCFG_OUTPUT_OPTIONS_CACHE_LINESIZE_SIZE_128
9864 /* This value is the virtual link admin state setting. */
9865 #define HWRM_FUNC_QCFG_OUTPUT_OPTIONS_LINK_ADMIN_STATE_MASK \
9867 #define HWRM_FUNC_QCFG_OUTPUT_OPTIONS_LINK_ADMIN_STATE_SFT 2
9868 /* Admin link state is in forced down mode. */
9869 #define HWRM_FUNC_QCFG_OUTPUT_OPTIONS_LINK_ADMIN_STATE_FORCED_DOWN \
9870 (UINT32_C(0x0) << 2)
9871 /* Admin link state is in forced up mode. */
9872 #define HWRM_FUNC_QCFG_OUTPUT_OPTIONS_LINK_ADMIN_STATE_FORCED_UP \
9873 (UINT32_C(0x1) << 2)
9874 /* Admin link state is in auto mode - follows the physical link state. */
9875 #define HWRM_FUNC_QCFG_OUTPUT_OPTIONS_LINK_ADMIN_STATE_AUTO \
9876 (UINT32_C(0x2) << 2)
9877 #define HWRM_FUNC_QCFG_OUTPUT_OPTIONS_LINK_ADMIN_STATE_LAST \
9878 HWRM_FUNC_QCFG_OUTPUT_OPTIONS_LINK_ADMIN_STATE_AUTO
9879 /* Reserved for future. */
9880 #define HWRM_FUNC_QCFG_OUTPUT_OPTIONS_RSVD_MASK \
9882 #define HWRM_FUNC_QCFG_OUTPUT_OPTIONS_RSVD_SFT 4
9884 * The number of VFs that are allocated to the function.
9885 * This is valid only on the PF with SR-IOV enabled.
9886 * 0xFF... (All Fs) if this command is called on a PF with
9887 * SR-IOV disabled or on a VF.
9891 * The number of allocated multicast filters for this
9892 * function on the RX side.
9894 uint32_t alloc_mcast_filters;
9896 * The number of allocated HW ring groups for this
9899 uint32_t alloc_hw_ring_grps;
9901 * The number of strict priority transmit rings out of
9902 * currently allocated TX rings to the function
9905 uint16_t alloc_sp_tx_rings;
9907 * The number of statistics contexts
9908 * currently reserved for the function.
9910 uint16_t alloc_stat_ctx;
9912 * This field specifies how many NQs are reserved for the PF.
9913 * Remaining NQs that belong to the PF are available for VFs.
9914 * Once a PF has created VFs, it cannot change how many NQs are
9915 * reserved for itself (since the NQs must be contiguous in HW).
9917 uint16_t alloc_msix;
9919 * The number of registered VF’s associated with the PF. This field
9920 * should be ignored when the request received on the VF interface.
9921 * This field will be updated on the PF interface to initiate
9922 * the unregister request on PF in the HOT Reset Process.
9924 uint16_t registered_vfs;
9926 * The size of the doorbell BAR in KBytes reserved for L2 including
9927 * any area that is shared between L2 and RoCE. The L2 driver
9928 * should only map the L2 portion of the doorbell BAR. Any rounding
9929 * of the BAR size to the native CPU page size should be performed
9930 * by the driver. If the value is zero, no special partitioning
9931 * of the doorbell BAR between L2 and RoCE is required.
9933 uint16_t l2_doorbell_bar_size_kb;
9936 * For backward compatibility this field must be set to 1.
9937 * Older drivers might look for this field to be 1 before
9938 * processing the message.
9942 * This GRC address location is used by the Host driver interfaces to poll
9943 * the adapter ready state to re-initiate the registration process again
9944 * after receiving the RESET Notify event.
9946 uint32_t reset_addr_poll;
9948 * This field specifies legacy L2 doorbell size in KBytes. Drivers should use
9949 * this value to find out the doorbell page offset from the BAR.
9951 uint16_t legacy_l2_db_size_kb;
9954 * This field specifies the source virtual interface of the function being
9955 * queried. Drivers can use this to program svif field in the L2 context
9958 #define HWRM_FUNC_QCFG_OUTPUT_SVIF_INFO_SVIF_MASK UINT32_C(0x7fff)
9959 #define HWRM_FUNC_QCFG_OUTPUT_SVIF_INFO_SVIF_SFT 0
9960 /* This field specifies whether svif is valid or not */
9961 #define HWRM_FUNC_QCFG_OUTPUT_SVIF_INFO_SVIF_VALID UINT32_C(0x8000)
9962 uint8_t unused_2[7];
9964 * This field is used in Output records to indicate that the output
9965 * is completely written to RAM. This field should be read as '1'
9966 * to indicate that the output has been completely written.
9967 * When writing a command completion or response to an internal processor,
9968 * the order of writes has to be such that this field is written last.
9978 /* hwrm_func_cfg_input (size:768b/96B) */
9979 struct hwrm_func_cfg_input {
9980 /* The HWRM command request type. */
9983 * The completion ring to send the completion event on. This should
9984 * be the NQ ID returned from the `nq_alloc` HWRM command.
9988 * The sequence ID is used by the driver for tracking multiple
9989 * commands. This ID is treated as opaque data by the firmware and
9990 * the value is returned in the `hwrm_resp_hdr` upon completion.
9994 * The target ID of the command:
9995 * * 0x0-0xFFF8 - The function ID
9996 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
9997 * * 0xFFFD - Reserved for user-space HWRM interface
10000 uint16_t target_id;
10002 * A physical address pointer pointing to a host buffer that the
10003 * command's response data will be written. This can be either a host
10004 * physical address (HPA) or a guest physical address (GPA) and must
10005 * point to a physically contiguous block of memory.
10007 uint64_t resp_addr;
10009 * Function ID of the function that is being
10011 * If set to 0xFF... (All Fs), then the the configuration is
10012 * for the requesting function.
10016 * This field specifies how many NQs will be reserved for the PF.
10017 * Remaining NQs that belong to the PF become available for VFs.
10018 * Once a PF has created VFs, it cannot change how many NQs are
10019 * reserved for itself (since the NQs must be contiguous in HW).
10024 * When this bit is '1', the function is disabled with
10025 * source MAC address check.
10026 * This is an anti-spoofing check. If this flag is set,
10027 * then the function shall be configured to disallow
10028 * transmission of frames with the source MAC address that
10029 * is configured for this function.
10031 #define HWRM_FUNC_CFG_INPUT_FLAGS_SRC_MAC_ADDR_CHECK_DISABLE \
10034 * When this bit is '1', the function is enabled with
10035 * source MAC address check.
10036 * This is an anti-spoofing check. If this flag is set,
10037 * then the function shall be configured to allow
10038 * transmission of frames with the source MAC address that
10039 * is configured for this function.
10041 #define HWRM_FUNC_CFG_INPUT_FLAGS_SRC_MAC_ADDR_CHECK_ENABLE \
10044 #define HWRM_FUNC_CFG_INPUT_FLAGS_RSVD_MASK \
10046 #define HWRM_FUNC_CFG_INPUT_FLAGS_RSVD_SFT 2
10048 * Standard TX Ring mode is used for the allocation of TX ring
10049 * and underlying scheduling resources that allow bandwidth
10050 * reservation and limit settings on the queried function.
10051 * If set to 1, then standard TX ring mode is requested to be
10052 * enabled on the function being configured.
10054 #define HWRM_FUNC_CFG_INPUT_FLAGS_STD_TX_RING_MODE_ENABLE \
10057 * Standard TX Ring mode is used for the allocation of TX ring
10058 * and underlying scheduling resources that allow bandwidth
10059 * reservation and limit settings on the queried function.
10060 * If set to 1, then the standard TX ring mode is requested to
10061 * be disabled on the function being configured. In this extended
10062 * TX ring resource mode, the minimum and maximum bandwidth settings
10063 * are not supported to allow the allocation of TX rings to
10064 * span multiple scheduler nodes.
10066 #define HWRM_FUNC_CFG_INPUT_FLAGS_STD_TX_RING_MODE_DISABLE \
10069 * If this bit is set, virtual mac address configured
10070 * in this command will be persistent over warm boot.
10072 #define HWRM_FUNC_CFG_INPUT_FLAGS_VIRT_MAC_PERSIST \
10075 * This bit only applies to the VF. If this bit is set, the statistic
10076 * context counters will not be cleared when the statistic context is freed
10077 * or a function reset is called on VF. This bit will be cleared when the PF
10078 * is unloaded or a function reset is called on the PF.
10080 #define HWRM_FUNC_CFG_INPUT_FLAGS_NO_AUTOCLEAR_STATISTIC \
10083 * This bit requests that the firmware test to see if all the assets
10084 * requested in this command (i.e. number of TX rings) are available.
10085 * The firmware will return an error if the requested assets are
10086 * not available. The firwmare will NOT reserve the assets if they
10089 #define HWRM_FUNC_CFG_INPUT_FLAGS_TX_ASSETS_TEST \
10092 * This bit requests that the firmware test to see if all the assets
10093 * requested in this command (i.e. number of RX rings) are available.
10094 * The firmware will return an error if the requested assets are
10095 * not available. The firwmare will NOT reserve the assets if they
10098 #define HWRM_FUNC_CFG_INPUT_FLAGS_RX_ASSETS_TEST \
10101 * This bit requests that the firmware test to see if all the assets
10102 * requested in this command (i.e. number of CMPL rings) are available.
10103 * The firmware will return an error if the requested assets are
10104 * not available. The firwmare will NOT reserve the assets if they
10107 #define HWRM_FUNC_CFG_INPUT_FLAGS_CMPL_ASSETS_TEST \
10110 * This bit requests that the firmware test to see if all the assets
10111 * requested in this command (i.e. number of RSS ctx) are available.
10112 * The firmware will return an error if the requested assets are
10113 * not available. The firwmare will NOT reserve the assets if they
10116 #define HWRM_FUNC_CFG_INPUT_FLAGS_RSSCOS_CTX_ASSETS_TEST \
10119 * This bit requests that the firmware test to see if all the assets
10120 * requested in this command (i.e. number of ring groups) are available.
10121 * The firmware will return an error if the requested assets are
10122 * not available. The firwmare will NOT reserve the assets if they
10125 #define HWRM_FUNC_CFG_INPUT_FLAGS_RING_GRP_ASSETS_TEST \
10128 * This bit requests that the firmware test to see if all the assets
10129 * requested in this command (i.e. number of stat ctx) are available.
10130 * The firmware will return an error if the requested assets are
10131 * not available. The firwmare will NOT reserve the assets if they
10134 #define HWRM_FUNC_CFG_INPUT_FLAGS_STAT_CTX_ASSETS_TEST \
10137 * This bit requests that the firmware test to see if all the assets
10138 * requested in this command (i.e. number of VNICs) are available.
10139 * The firmware will return an error if the requested assets are
10140 * not available. The firwmare will NOT reserve the assets if they
10143 #define HWRM_FUNC_CFG_INPUT_FLAGS_VNIC_ASSETS_TEST \
10146 * This bit requests that the firmware test to see if all the assets
10147 * requested in this command (i.e. number of L2 ctx) are available.
10148 * The firmware will return an error if the requested assets are
10149 * not available. The firwmare will NOT reserve the assets if they
10152 #define HWRM_FUNC_CFG_INPUT_FLAGS_L2_CTX_ASSETS_TEST \
10155 * This configuration change can be initiated by a PF driver. This
10156 * configuration request shall be targeted to a VF. From local host
10157 * resident HWRM clients, only the parent PF driver shall be allowed
10158 * to initiate this change on one of its children VFs. If this bit is
10159 * set to 1, then the VF that is being configured is requested to be
10162 #define HWRM_FUNC_CFG_INPUT_FLAGS_TRUSTED_VF_ENABLE \
10165 * When this bit it set, even if PF reserved pool size is zero,
10166 * FW will allow driver to create TX rings in ring alloc,
10167 * by reserving TX ring, S3 node dynamically.
10169 #define HWRM_FUNC_CFG_INPUT_FLAGS_DYNAMIC_TX_RING_ALLOC \
10172 * This bit requests that the firmware test to see if all the assets
10173 * requested in this command (i.e. number of NQ rings) are available.
10174 * The firmware will return an error if the requested assets are
10175 * not available. The firwmare will NOT reserve the assets if they
10178 #define HWRM_FUNC_CFG_INPUT_FLAGS_NQ_ASSETS_TEST \
10181 * This configuration change can be initiated by a PF driver. This
10182 * configuration request shall be targeted to a VF. From local host
10183 * resident HWRM clients, only the parent PF driver shall be allowed
10184 * to initiate this change on one of its children VFs. If this bit is
10185 * set to 1, then the VF that is being configured is requested to be
10188 #define HWRM_FUNC_CFG_INPUT_FLAGS_TRUSTED_VF_DISABLE \
10189 UINT32_C(0x1000000)
10191 * This bit is used by preboot drivers on a PF that require access
10192 * to the legacy L2 ring model and legacy 32b doorbells. This
10193 * feature is not allowed on VFs and is only relevant for devices
10194 * that require a context backing store.
10196 #define HWRM_FUNC_CFG_INPUT_FLAGS_PREBOOT_LEGACY_L2_RINGS \
10197 UINT32_C(0x2000000)
10199 * If this bit is set to 0, then the interface does not support hot
10200 * reset capability which it advertised with the hot_reset_support
10201 * flag in HWRM_FUNC_DRV_RGTR. If any of the function has set this
10202 * flag to 0, adapter cannot do the hot reset. In this state, if the
10203 * firmware receives a hot reset request, firmware must fail the
10204 * request. If this bit is set to 1, then interface is renabling the
10205 * hot reset capability.
10207 #define HWRM_FUNC_CFG_INPUT_FLAGS_HOT_RESET_IF_EN_DIS \
10208 UINT32_C(0x4000000)
10210 * If this bit is set to 1, the PF driver is requesting FW
10211 * to enable PPP TX PUSH feature on all the TX rings specified in
10212 * the num_tx_rings field. By default, the PPP TX push feature is
10213 * disabled for all the TX rings of the function. This flag is
10214 * ignored if num_tx_rings field is not specified or the function
10215 * doesn't support PPP tx push feature.
10217 #define HWRM_FUNC_CFG_INPUT_FLAGS_PPP_PUSH_MODE_ENABLE \
10218 UINT32_C(0x8000000)
10220 * If this bit is set to 1, the PF driver is requesting FW
10221 * to disable PPP TX PUSH feature on all the TX rings specified in
10222 * the num_tx_rings field. This flag is ignored if num_tx_rings
10223 * field is not specified or the function doesn't support PPP tx
10226 #define HWRM_FUNC_CFG_INPUT_FLAGS_PPP_PUSH_MODE_DISABLE \
10227 UINT32_C(0x10000000)
10230 * This bit must be '1' for the mtu field to be
10233 #define HWRM_FUNC_CFG_INPUT_ENABLES_MTU \
10236 * This bit must be '1' for the mru field to be
10239 #define HWRM_FUNC_CFG_INPUT_ENABLES_MRU \
10242 * This bit must be '1' for the num_rsscos_ctxs field to be
10245 #define HWRM_FUNC_CFG_INPUT_ENABLES_NUM_RSSCOS_CTXS \
10248 * This bit must be '1' for the num_cmpl_rings field to be
10251 #define HWRM_FUNC_CFG_INPUT_ENABLES_NUM_CMPL_RINGS \
10254 * This bit must be '1' for the num_tx_rings field to be
10257 #define HWRM_FUNC_CFG_INPUT_ENABLES_NUM_TX_RINGS \
10260 * This bit must be '1' for the num_rx_rings field to be
10263 #define HWRM_FUNC_CFG_INPUT_ENABLES_NUM_RX_RINGS \
10266 * This bit must be '1' for the num_l2_ctxs field to be
10269 #define HWRM_FUNC_CFG_INPUT_ENABLES_NUM_L2_CTXS \
10272 * This bit must be '1' for the num_vnics field to be
10275 #define HWRM_FUNC_CFG_INPUT_ENABLES_NUM_VNICS \
10278 * This bit must be '1' for the num_stat_ctxs field to be
10281 #define HWRM_FUNC_CFG_INPUT_ENABLES_NUM_STAT_CTXS \
10284 * This bit must be '1' for the dflt_mac_addr field to be
10287 #define HWRM_FUNC_CFG_INPUT_ENABLES_DFLT_MAC_ADDR \
10290 * This bit must be '1' for the dflt_vlan field to be
10293 #define HWRM_FUNC_CFG_INPUT_ENABLES_DFLT_VLAN \
10296 * This bit must be '1' for the dflt_ip_addr field to be
10299 #define HWRM_FUNC_CFG_INPUT_ENABLES_DFLT_IP_ADDR \
10302 * This bit must be '1' for the min_bw field to be
10305 #define HWRM_FUNC_CFG_INPUT_ENABLES_MIN_BW \
10308 * This bit must be '1' for the max_bw field to be
10311 #define HWRM_FUNC_CFG_INPUT_ENABLES_MAX_BW \
10314 * This bit must be '1' for the async_event_cr field to be
10317 #define HWRM_FUNC_CFG_INPUT_ENABLES_ASYNC_EVENT_CR \
10320 * This bit must be '1' for the vlan_antispoof_mode field to be
10323 #define HWRM_FUNC_CFG_INPUT_ENABLES_VLAN_ANTISPOOF_MODE \
10326 * This bit must be '1' for the allowed_vlan_pris field to be
10329 #define HWRM_FUNC_CFG_INPUT_ENABLES_ALLOWED_VLAN_PRIS \
10332 * This bit must be '1' for the evb_mode field to be
10335 #define HWRM_FUNC_CFG_INPUT_ENABLES_EVB_MODE \
10338 * This bit must be '1' for the num_mcast_filters field to be
10341 #define HWRM_FUNC_CFG_INPUT_ENABLES_NUM_MCAST_FILTERS \
10344 * This bit must be '1' for the num_hw_ring_grps field to be
10347 #define HWRM_FUNC_CFG_INPUT_ENABLES_NUM_HW_RING_GRPS \
10350 * This bit must be '1' for the cache_linesize field to be
10353 #define HWRM_FUNC_CFG_INPUT_ENABLES_CACHE_LINESIZE \
10356 * This bit must be '1' for the num_msix field to be
10359 #define HWRM_FUNC_CFG_INPUT_ENABLES_NUM_MSIX \
10362 * This bit must be '1' for the link admin state field to be
10365 #define HWRM_FUNC_CFG_INPUT_ENABLES_ADMIN_LINK_STATE \
10368 * This bit must be '1' for the hot_reset_if_en_dis field to be
10371 #define HWRM_FUNC_CFG_INPUT_ENABLES_HOT_RESET_IF_SUPPORT \
10374 * This bit must be '1' for the schq_id field to be
10377 #define HWRM_FUNC_CFG_INPUT_ENABLES_SCHQ_ID \
10378 UINT32_C(0x1000000)
10380 * The maximum transmission unit of the function.
10381 * The HWRM should make sure that the mtu of
10382 * the function does not exceed the mtu of the physical
10383 * port that this function is associated with.
10385 * In addition to configuring mtu per function, it is
10386 * possible to configure mtu per transmit ring.
10387 * By default, the mtu of each transmit ring associated
10388 * with a function is equal to the mtu of the function.
10389 * The HWRM should make sure that the mtu of each transmit
10390 * ring that is assigned to a function has a valid mtu.
10394 * The maximum receive unit of the function.
10395 * The HWRM should make sure that the mru of
10396 * the function does not exceed the mru of the physical
10397 * port that this function is associated with.
10399 * In addition to configuring mru per function, it is
10400 * possible to configure mru per vnic.
10401 * By default, the mru of each vnic associated
10402 * with a function is equal to the mru of the function.
10403 * The HWRM should make sure that the mru of each vnic
10404 * that is assigned to a function has a valid mru.
10408 * The number of RSS/COS contexts requested for the
10411 uint16_t num_rsscos_ctxs;
10413 * The number of completion rings requested for the
10414 * function. This does not include the rings allocated
10415 * to any children functions if any.
10417 uint16_t num_cmpl_rings;
10419 * The number of transmit rings requested for the function.
10420 * This does not include the rings allocated to any
10421 * children functions if any.
10423 uint16_t num_tx_rings;
10425 * The number of receive rings requested for the function.
10426 * This does not include the rings allocated
10427 * to any children functions if any.
10429 uint16_t num_rx_rings;
10430 /* The requested number of L2 contexts for the function. */
10431 uint16_t num_l2_ctxs;
10432 /* The requested number of vnics for the function. */
10433 uint16_t num_vnics;
10434 /* The requested number of statistic contexts for the function. */
10435 uint16_t num_stat_ctxs;
10437 * The number of HW ring groups that should
10438 * be reserved for this function.
10440 uint16_t num_hw_ring_grps;
10441 /* The default MAC address for the function being configured. */
10442 uint8_t dflt_mac_addr[6];
10444 * The default VLAN for the function being configured.
10445 * This field's format is same as 802.1Q Tag's
10446 * Tag Control Information (TCI) format that includes both
10447 * Priority Code Point (PCP) and VLAN Identifier (VID).
10449 uint16_t dflt_vlan;
10451 * The default IP address for the function being configured.
10452 * This address is only used in enabling source property check.
10454 uint32_t dflt_ip_addr[4];
10456 * Minimum BW allocated for this function.
10457 * The HWRM will translate this value into byte counter and
10458 * time interval used for the scheduler inside the device.
10461 /* The bandwidth value. */
10462 #define HWRM_FUNC_CFG_INPUT_MIN_BW_BW_VALUE_MASK \
10463 UINT32_C(0xfffffff)
10464 #define HWRM_FUNC_CFG_INPUT_MIN_BW_BW_VALUE_SFT 0
10465 /* The granularity of the value (bits or bytes). */
10466 #define HWRM_FUNC_CFG_INPUT_MIN_BW_SCALE \
10467 UINT32_C(0x10000000)
10468 /* Value is in bits. */
10469 #define HWRM_FUNC_CFG_INPUT_MIN_BW_SCALE_BITS \
10470 (UINT32_C(0x0) << 28)
10471 /* Value is in bytes. */
10472 #define HWRM_FUNC_CFG_INPUT_MIN_BW_SCALE_BYTES \
10473 (UINT32_C(0x1) << 28)
10474 #define HWRM_FUNC_CFG_INPUT_MIN_BW_SCALE_LAST \
10475 HWRM_FUNC_CFG_INPUT_MIN_BW_SCALE_BYTES
10476 /* bw_value_unit is 3 b */
10477 #define HWRM_FUNC_CFG_INPUT_MIN_BW_BW_VALUE_UNIT_MASK \
10478 UINT32_C(0xe0000000)
10479 #define HWRM_FUNC_CFG_INPUT_MIN_BW_BW_VALUE_UNIT_SFT 29
10480 /* Value is in Mb or MB (base 10). */
10481 #define HWRM_FUNC_CFG_INPUT_MIN_BW_BW_VALUE_UNIT_MEGA \
10482 (UINT32_C(0x0) << 29)
10483 /* Value is in Kb or KB (base 10). */
10484 #define HWRM_FUNC_CFG_INPUT_MIN_BW_BW_VALUE_UNIT_KILO \
10485 (UINT32_C(0x2) << 29)
10486 /* Value is in bits or bytes. */
10487 #define HWRM_FUNC_CFG_INPUT_MIN_BW_BW_VALUE_UNIT_BASE \
10488 (UINT32_C(0x4) << 29)
10489 /* Value is in Gb or GB (base 10). */
10490 #define HWRM_FUNC_CFG_INPUT_MIN_BW_BW_VALUE_UNIT_GIGA \
10491 (UINT32_C(0x6) << 29)
10492 /* Value is in 1/100th of a percentage of total bandwidth. */
10493 #define HWRM_FUNC_CFG_INPUT_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 \
10494 (UINT32_C(0x1) << 29)
10496 #define HWRM_FUNC_CFG_INPUT_MIN_BW_BW_VALUE_UNIT_INVALID \
10497 (UINT32_C(0x7) << 29)
10498 #define HWRM_FUNC_CFG_INPUT_MIN_BW_BW_VALUE_UNIT_LAST \
10499 HWRM_FUNC_CFG_INPUT_MIN_BW_BW_VALUE_UNIT_INVALID
10501 * Maximum BW allocated for this function.
10502 * The HWRM will translate this value into byte counter and
10503 * time interval used for the scheduler inside the device.
10506 /* The bandwidth value. */
10507 #define HWRM_FUNC_CFG_INPUT_MAX_BW_BW_VALUE_MASK \
10508 UINT32_C(0xfffffff)
10509 #define HWRM_FUNC_CFG_INPUT_MAX_BW_BW_VALUE_SFT 0
10510 /* The granularity of the value (bits or bytes). */
10511 #define HWRM_FUNC_CFG_INPUT_MAX_BW_SCALE \
10512 UINT32_C(0x10000000)
10513 /* Value is in bits. */
10514 #define HWRM_FUNC_CFG_INPUT_MAX_BW_SCALE_BITS \
10515 (UINT32_C(0x0) << 28)
10516 /* Value is in bytes. */
10517 #define HWRM_FUNC_CFG_INPUT_MAX_BW_SCALE_BYTES \
10518 (UINT32_C(0x1) << 28)
10519 #define HWRM_FUNC_CFG_INPUT_MAX_BW_SCALE_LAST \
10520 HWRM_FUNC_CFG_INPUT_MAX_BW_SCALE_BYTES
10521 /* bw_value_unit is 3 b */
10522 #define HWRM_FUNC_CFG_INPUT_MAX_BW_BW_VALUE_UNIT_MASK \
10523 UINT32_C(0xe0000000)
10524 #define HWRM_FUNC_CFG_INPUT_MAX_BW_BW_VALUE_UNIT_SFT 29
10525 /* Value is in Mb or MB (base 10). */
10526 #define HWRM_FUNC_CFG_INPUT_MAX_BW_BW_VALUE_UNIT_MEGA \
10527 (UINT32_C(0x0) << 29)
10528 /* Value is in Kb or KB (base 10). */
10529 #define HWRM_FUNC_CFG_INPUT_MAX_BW_BW_VALUE_UNIT_KILO \
10530 (UINT32_C(0x2) << 29)
10531 /* Value is in bits or bytes. */
10532 #define HWRM_FUNC_CFG_INPUT_MAX_BW_BW_VALUE_UNIT_BASE \
10533 (UINT32_C(0x4) << 29)
10534 /* Value is in Gb or GB (base 10). */
10535 #define HWRM_FUNC_CFG_INPUT_MAX_BW_BW_VALUE_UNIT_GIGA \
10536 (UINT32_C(0x6) << 29)
10537 /* Value is in 1/100th of a percentage of total bandwidth. */
10538 #define HWRM_FUNC_CFG_INPUT_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 \
10539 (UINT32_C(0x1) << 29)
10541 #define HWRM_FUNC_CFG_INPUT_MAX_BW_BW_VALUE_UNIT_INVALID \
10542 (UINT32_C(0x7) << 29)
10543 #define HWRM_FUNC_CFG_INPUT_MAX_BW_BW_VALUE_UNIT_LAST \
10544 HWRM_FUNC_CFG_INPUT_MAX_BW_BW_VALUE_UNIT_INVALID
10546 * ID of the target completion ring for receiving asynchronous
10547 * event completions. If this field is not valid, then the
10548 * HWRM shall use the default completion ring of the function
10549 * that is being configured as the target completion ring for
10550 * providing any asynchronous event completions for that
10552 * If this field is valid, then the HWRM shall use the
10553 * completion ring identified by this ID as the target
10554 * completion ring for providing any asynchronous event
10555 * completions for the function that is being configured.
10557 uint16_t async_event_cr;
10558 /* VLAN Anti-spoofing mode. */
10559 uint8_t vlan_antispoof_mode;
10560 /* No VLAN anti-spoofing checks are enabled */
10561 #define HWRM_FUNC_CFG_INPUT_VLAN_ANTISPOOF_MODE_NOCHECK \
10563 /* Validate VLAN against the configured VLAN(s) */
10564 #define HWRM_FUNC_CFG_INPUT_VLAN_ANTISPOOF_MODE_VALIDATE_VLAN \
10566 /* Insert VLAN if it does not exist, otherwise discard */
10567 #define HWRM_FUNC_CFG_INPUT_VLAN_ANTISPOOF_MODE_INSERT_IF_VLANDNE \
10569 /* Insert VLAN if it does not exist, override VLAN if it exists */
10570 #define HWRM_FUNC_CFG_INPUT_VLAN_ANTISPOOF_MODE_INSERT_OR_OVERRIDE_VLAN \
10572 #define HWRM_FUNC_CFG_INPUT_VLAN_ANTISPOOF_MODE_LAST \
10573 HWRM_FUNC_CFG_INPUT_VLAN_ANTISPOOF_MODE_INSERT_OR_OVERRIDE_VLAN
10575 * This bit field defines VLAN PRIs that are allowed on
10577 * If nth bit is set, then VLAN PRI n is allowed on this
10580 uint8_t allowed_vlan_pris;
10582 * The HWRM shall allow a PF driver to change EVB mode for the
10583 * partition it belongs to.
10584 * The HWRM shall not allow a VF driver to change the EVB mode.
10585 * The HWRM shall take into account the switching of EVB mode
10586 * from one to another and reconfigure hardware resources as
10588 * The switching from VEB to VEPA mode requires
10589 * the disabling of the loopback traffic. Additionally,
10590 * source knock outs are handled differently in VEB and VEPA
10594 /* No Edge Virtual Bridging (EVB) */
10595 #define HWRM_FUNC_CFG_INPUT_EVB_MODE_NO_EVB UINT32_C(0x0)
10596 /* Virtual Ethernet Bridge (VEB) */
10597 #define HWRM_FUNC_CFG_INPUT_EVB_MODE_VEB UINT32_C(0x1)
10598 /* Virtual Ethernet Port Aggregator (VEPA) */
10599 #define HWRM_FUNC_CFG_INPUT_EVB_MODE_VEPA UINT32_C(0x2)
10600 #define HWRM_FUNC_CFG_INPUT_EVB_MODE_LAST \
10601 HWRM_FUNC_CFG_INPUT_EVB_MODE_VEPA
10604 * This value indicates the PCIE device cache line size.
10605 * The cache line size allows the DMA writes to terminate and
10606 * start at the cache boundary.
10608 #define HWRM_FUNC_CFG_INPUT_OPTIONS_CACHE_LINESIZE_MASK \
10610 #define HWRM_FUNC_CFG_INPUT_OPTIONS_CACHE_LINESIZE_SFT 0
10611 /* Cache Line Size 64 bytes */
10612 #define HWRM_FUNC_CFG_INPUT_OPTIONS_CACHE_LINESIZE_SIZE_64 \
10614 /* Cache Line Size 128 bytes */
10615 #define HWRM_FUNC_CFG_INPUT_OPTIONS_CACHE_LINESIZE_SIZE_128 \
10617 #define HWRM_FUNC_CFG_INPUT_OPTIONS_CACHE_LINESIZE_LAST \
10618 HWRM_FUNC_CFG_INPUT_OPTIONS_CACHE_LINESIZE_SIZE_128
10619 /* This value is the virtual link admin state setting. */
10620 #define HWRM_FUNC_CFG_INPUT_OPTIONS_LINK_ADMIN_STATE_MASK \
10622 #define HWRM_FUNC_CFG_INPUT_OPTIONS_LINK_ADMIN_STATE_SFT 2
10623 /* Admin state is forced down. */
10624 #define HWRM_FUNC_CFG_INPUT_OPTIONS_LINK_ADMIN_STATE_FORCED_DOWN \
10625 (UINT32_C(0x0) << 2)
10626 /* Admin state is forced up. */
10627 #define HWRM_FUNC_CFG_INPUT_OPTIONS_LINK_ADMIN_STATE_FORCED_UP \
10628 (UINT32_C(0x1) << 2)
10629 /* Admin state is in auto mode - is to follow the physical link state. */
10630 #define HWRM_FUNC_CFG_INPUT_OPTIONS_LINK_ADMIN_STATE_AUTO \
10631 (UINT32_C(0x2) << 2)
10632 #define HWRM_FUNC_CFG_INPUT_OPTIONS_LINK_ADMIN_STATE_LAST \
10633 HWRM_FUNC_CFG_INPUT_OPTIONS_LINK_ADMIN_STATE_AUTO
10634 /* Reserved for future. */
10635 #define HWRM_FUNC_CFG_INPUT_OPTIONS_RSVD_MASK \
10637 #define HWRM_FUNC_CFG_INPUT_OPTIONS_RSVD_SFT 4
10639 * The number of multicast filters that should
10640 * be reserved for this function on the RX side.
10642 uint16_t num_mcast_filters;
10643 /* Used by a PF driver to associate a SCHQ with a VF. */
10645 uint8_t unused_0[6];
10648 /* hwrm_func_cfg_output (size:128b/16B) */
10649 struct hwrm_func_cfg_output {
10650 /* The specific error status for the command. */
10651 uint16_t error_code;
10652 /* The HWRM command request type. */
10654 /* The sequence ID from the original command. */
10656 /* The length of the response data in number of bytes. */
10658 uint8_t unused_0[7];
10660 * This field is used in Output records to indicate that the output
10661 * is completely written to RAM. This field should be read as '1'
10662 * to indicate that the output has been completely written.
10663 * When writing a command completion or response to an internal processor,
10664 * the order of writes has to be such that this field is written last.
10669 /********************
10670 * hwrm_func_qstats *
10671 ********************/
10674 /* hwrm_func_qstats_input (size:192b/24B) */
10675 struct hwrm_func_qstats_input {
10676 /* The HWRM command request type. */
10679 * The completion ring to send the completion event on. This should
10680 * be the NQ ID returned from the `nq_alloc` HWRM command.
10682 uint16_t cmpl_ring;
10684 * The sequence ID is used by the driver for tracking multiple
10685 * commands. This ID is treated as opaque data by the firmware and
10686 * the value is returned in the `hwrm_resp_hdr` upon completion.
10690 * The target ID of the command:
10691 * * 0x0-0xFFF8 - The function ID
10692 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
10693 * * 0xFFFD - Reserved for user-space HWRM interface
10696 uint16_t target_id;
10698 * A physical address pointer pointing to a host buffer that the
10699 * command's response data will be written. This can be either a host
10700 * physical address (HPA) or a guest physical address (GPA) and must
10701 * point to a physically contiguous block of memory.
10703 uint64_t resp_addr;
10705 * Function ID of the function that is being queried.
10706 * 0xFF... (All Fs) if the query is for the requesting
10708 * A privileged PF can query for other function's statistics.
10711 /* This flags indicates the type of statistics request. */
10713 /* This value is not used to avoid backward compatibility issues. */
10714 #define HWRM_FUNC_QSTATS_INPUT_FLAGS_UNUSED UINT32_C(0x0)
10716 * flags should be set to 1 when request is for only RoCE statistics.
10717 * This will be honored only if the caller_fid is a privileged PF.
10718 * In all other cases FID and caller_fid should be the same.
10720 #define HWRM_FUNC_QSTATS_INPUT_FLAGS_ROCE_ONLY UINT32_C(0x1)
10722 * flags should be set to 2 when request is for the counter mask,
10723 * representing the width of each of the stats counters, rather
10724 * than counters themselves.
10726 #define HWRM_FUNC_QSTATS_INPUT_FLAGS_COUNTER_MASK UINT32_C(0x2)
10727 #define HWRM_FUNC_QSTATS_INPUT_FLAGS_LAST \
10728 HWRM_FUNC_QSTATS_INPUT_FLAGS_COUNTER_MASK
10729 uint8_t unused_0[5];
10732 /* hwrm_func_qstats_output (size:1408b/176B) */
10733 struct hwrm_func_qstats_output {
10734 /* The specific error status for the command. */
10735 uint16_t error_code;
10736 /* The HWRM command request type. */
10738 /* The sequence ID from the original command. */
10740 /* The length of the response data in number of bytes. */
10742 /* Number of transmitted unicast packets on the function. */
10743 uint64_t tx_ucast_pkts;
10744 /* Number of transmitted multicast packets on the function. */
10745 uint64_t tx_mcast_pkts;
10746 /* Number of transmitted broadcast packets on the function. */
10747 uint64_t tx_bcast_pkts;
10749 * Number of transmitted packets that were discarded due to
10750 * internal NIC resource problems. For transmit, this
10751 * can only happen if TMP is configured to allow dropping
10752 * in HOL blocking conditions, which is not a normal
10755 uint64_t tx_discard_pkts;
10757 * Number of dropped packets on transmit path on the function.
10758 * These are packets that have been marked for drop by
10759 * the TE CFA block or are packets that exceeded the
10760 * transmit MTU limit for the function.
10762 uint64_t tx_drop_pkts;
10763 /* Number of transmitted bytes for unicast traffic on the function. */
10764 uint64_t tx_ucast_bytes;
10765 /* Number of transmitted bytes for multicast traffic on the function. */
10766 uint64_t tx_mcast_bytes;
10767 /* Number of transmitted bytes for broadcast traffic on the function. */
10768 uint64_t tx_bcast_bytes;
10769 /* Number of received unicast packets on the function. */
10770 uint64_t rx_ucast_pkts;
10771 /* Number of received multicast packets on the function. */
10772 uint64_t rx_mcast_pkts;
10773 /* Number of received broadcast packets on the function. */
10774 uint64_t rx_bcast_pkts;
10776 * Number of received packets that were discarded on the function
10777 * due to resource limitations. This can happen for 3 reasons.
10778 * # The BD used for the packet has a bad format.
10779 * # There were no BDs available in the ring for the packet.
10780 * # There were no BDs available on-chip for the packet.
10782 uint64_t rx_discard_pkts;
10784 * Number of dropped packets on received path on the function.
10785 * These are packets that have been marked for drop by the
10788 uint64_t rx_drop_pkts;
10789 /* Number of received bytes for unicast traffic on the function. */
10790 uint64_t rx_ucast_bytes;
10791 /* Number of received bytes for multicast traffic on the function. */
10792 uint64_t rx_mcast_bytes;
10793 /* Number of received bytes for broadcast traffic on the function. */
10794 uint64_t rx_bcast_bytes;
10795 /* Number of aggregated unicast packets on the function. */
10796 uint64_t rx_agg_pkts;
10797 /* Number of aggregated unicast bytes on the function. */
10798 uint64_t rx_agg_bytes;
10799 /* Number of aggregation events on the function. */
10800 uint64_t rx_agg_events;
10801 /* Number of aborted aggregations on the function. */
10802 uint64_t rx_agg_aborts;
10803 uint8_t unused_0[7];
10805 * This field is used in Output records to indicate that the output
10806 * is completely written to RAM. This field should be read as '1'
10807 * to indicate that the output has been completely written.
10808 * When writing a command completion or response to an internal processor,
10809 * the order of writes has to be such that this field is written last.
10814 /************************
10815 * hwrm_func_qstats_ext *
10816 ************************/
10819 /* hwrm_func_qstats_ext_input (size:256b/32B) */
10820 struct hwrm_func_qstats_ext_input {
10821 /* The HWRM command request type. */
10824 * The completion ring to send the completion event on. This should
10825 * be the NQ ID returned from the `nq_alloc` HWRM command.
10827 uint16_t cmpl_ring;
10829 * The sequence ID is used by the driver for tracking multiple
10830 * commands. This ID is treated as opaque data by the firmware and
10831 * the value is returned in the `hwrm_resp_hdr` upon completion.
10835 * The target ID of the command:
10836 * * 0x0-0xFFF8 - The function ID
10837 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
10838 * * 0xFFFD - Reserved for user-space HWRM interface
10841 uint16_t target_id;
10843 * A physical address pointer pointing to a host buffer that the
10844 * command's response data will be written. This can be either a host
10845 * physical address (HPA) or a guest physical address (GPA) and must
10846 * point to a physically contiguous block of memory.
10848 uint64_t resp_addr;
10850 * Function ID of the function that is being queried.
10851 * 0xFF... (All Fs) if the query is for the requesting
10853 * A privileged PF can query for other function's statistics.
10856 /* This flags indicates the type of statistics request. */
10858 /* This value is not used to avoid backward compatibility issues. */
10859 #define HWRM_FUNC_QSTATS_EXT_INPUT_FLAGS_UNUSED UINT32_C(0x0)
10861 * flags should be set to 1 when request is for only RoCE statistics.
10862 * This will be honored only if the caller_fid is a privileged PF.
10863 * In all other cases FID and caller_fid should be the same.
10865 #define HWRM_FUNC_QSTATS_EXT_INPUT_FLAGS_ROCE_ONLY UINT32_C(0x1)
10867 * flags should be set to 2 when request is for the counter mask
10868 * representing the width of each of the stats counters, rather
10869 * than counters themselves.
10871 #define HWRM_FUNC_QSTATS_EXT_INPUT_FLAGS_COUNTER_MASK UINT32_C(0x2)
10872 #define HWRM_FUNC_QSTATS_EXT_INPUT_FLAGS_LAST \
10873 HWRM_FUNC_QSTATS_EXT_INPUT_FLAGS_COUNTER_MASK
10874 uint8_t unused_0[1];
10877 * This bit must be '1' for the schq_id and traffic_class fields to
10880 #define HWRM_FUNC_QSTATS_EXT_INPUT_ENABLES_SCHQ_ID UINT32_C(0x1)
10881 /* Specifies the SCHQ for which to gather statistics */
10884 * Specifies the traffic class for which to gather statistics. Valid
10885 * values are 0 through (max_configurable_queues - 1), where
10886 * max_configurable_queues is in the response of HWRM_QUEUE_QPORTCFG
10888 uint16_t traffic_class;
10889 uint8_t unused_1[4];
10892 /* hwrm_func_qstats_ext_output (size:1472b/184B) */
10893 struct hwrm_func_qstats_ext_output {
10894 /* The specific error status for the command. */
10895 uint16_t error_code;
10896 /* The HWRM command request type. */
10898 /* The sequence ID from the original command. */
10900 /* The length of the response data in number of bytes. */
10902 /* Number of received unicast packets */
10903 uint64_t rx_ucast_pkts;
10904 /* Number of received multicast packets */
10905 uint64_t rx_mcast_pkts;
10906 /* Number of received broadcast packets */
10907 uint64_t rx_bcast_pkts;
10908 /* Number of discarded packets on received path */
10909 uint64_t rx_discard_pkts;
10910 /* Number of packets on receive path with error */
10911 uint64_t rx_error_pkts;
10912 /* Number of received bytes for unicast traffic */
10913 uint64_t rx_ucast_bytes;
10914 /* Number of received bytes for multicast traffic */
10915 uint64_t rx_mcast_bytes;
10916 /* Number of received bytes for broadcast traffic */
10917 uint64_t rx_bcast_bytes;
10918 /* Number of transmitted unicast packets */
10919 uint64_t tx_ucast_pkts;
10920 /* Number of transmitted multicast packets */
10921 uint64_t tx_mcast_pkts;
10922 /* Number of transmitted broadcast packets */
10923 uint64_t tx_bcast_pkts;
10924 /* Number of packets on transmit path with error */
10925 uint64_t tx_error_pkts;
10926 /* Number of discarded packets on transmit path */
10927 uint64_t tx_discard_pkts;
10928 /* Number of transmitted bytes for unicast traffic */
10929 uint64_t tx_ucast_bytes;
10930 /* Number of transmitted bytes for multicast traffic */
10931 uint64_t tx_mcast_bytes;
10932 /* Number of transmitted bytes for broadcast traffic */
10933 uint64_t tx_bcast_bytes;
10934 /* Number of TPA eligible packets */
10935 uint64_t rx_tpa_eligible_pkt;
10936 /* Number of TPA eligible bytes */
10937 uint64_t rx_tpa_eligible_bytes;
10938 /* Number of TPA packets */
10939 uint64_t rx_tpa_pkt;
10940 /* Number of TPA bytes */
10941 uint64_t rx_tpa_bytes;
10942 /* Number of TPA errors */
10943 uint64_t rx_tpa_errors;
10944 uint8_t unused_0[7];
10946 * This field is used in Output records to indicate that the output
10947 * is completely written to RAM. This field should be read as '1'
10948 * to indicate that the output has been completely written.
10949 * When writing a command completion or response to an internal processor,
10950 * the order of writes has to be such that this field is written last.
10955 /***********************
10956 * hwrm_func_clr_stats *
10957 ***********************/
10960 /* hwrm_func_clr_stats_input (size:192b/24B) */
10961 struct hwrm_func_clr_stats_input {
10962 /* The HWRM command request type. */
10965 * The completion ring to send the completion event on. This should
10966 * be the NQ ID returned from the `nq_alloc` HWRM command.
10968 uint16_t cmpl_ring;
10970 * The sequence ID is used by the driver for tracking multiple
10971 * commands. This ID is treated as opaque data by the firmware and
10972 * the value is returned in the `hwrm_resp_hdr` upon completion.
10976 * The target ID of the command:
10977 * * 0x0-0xFFF8 - The function ID
10978 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
10979 * * 0xFFFD - Reserved for user-space HWRM interface
10982 uint16_t target_id;
10984 * A physical address pointer pointing to a host buffer that the
10985 * command's response data will be written. This can be either a host
10986 * physical address (HPA) or a guest physical address (GPA) and must
10987 * point to a physically contiguous block of memory.
10989 uint64_t resp_addr;
10991 * Function ID of the function.
10992 * 0xFF... (All Fs) if the query is for the requesting
10996 uint8_t unused_0[6];
10999 /* hwrm_func_clr_stats_output (size:128b/16B) */
11000 struct hwrm_func_clr_stats_output {
11001 /* The specific error status for the command. */
11002 uint16_t error_code;
11003 /* The HWRM command request type. */
11005 /* The sequence ID from the original command. */
11007 /* The length of the response data in number of bytes. */
11009 uint8_t unused_0[7];
11011 * This field is used in Output records to indicate that the output
11012 * is completely written to RAM. This field should be read as '1'
11013 * to indicate that the output has been completely written.
11014 * When writing a command completion or response to an internal processor,
11015 * the order of writes has to be such that this field is written last.
11020 /**************************
11021 * hwrm_func_vf_resc_free *
11022 **************************/
11025 /* hwrm_func_vf_resc_free_input (size:192b/24B) */
11026 struct hwrm_func_vf_resc_free_input {
11027 /* The HWRM command request type. */
11030 * The completion ring to send the completion event on. This should
11031 * be the NQ ID returned from the `nq_alloc` HWRM command.
11033 uint16_t cmpl_ring;
11035 * The sequence ID is used by the driver for tracking multiple
11036 * commands. This ID is treated as opaque data by the firmware and
11037 * the value is returned in the `hwrm_resp_hdr` upon completion.
11041 * The target ID of the command:
11042 * * 0x0-0xFFF8 - The function ID
11043 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
11044 * * 0xFFFD - Reserved for user-space HWRM interface
11047 uint16_t target_id;
11049 * A physical address pointer pointing to a host buffer that the
11050 * command's response data will be written. This can be either a host
11051 * physical address (HPA) or a guest physical address (GPA) and must
11052 * point to a physically contiguous block of memory.
11054 uint64_t resp_addr;
11056 * This value is used to identify a Virtual Function (VF).
11057 * The scope of VF ID is local within a PF.
11060 uint8_t unused_0[6];
11063 /* hwrm_func_vf_resc_free_output (size:128b/16B) */
11064 struct hwrm_func_vf_resc_free_output {
11065 /* The specific error status for the command. */
11066 uint16_t error_code;
11067 /* The HWRM command request type. */
11069 /* The sequence ID from the original command. */
11071 /* The length of the response data in number of bytes. */
11073 uint8_t unused_0[7];
11075 * This field is used in Output records to indicate that the output
11076 * is completely written to RAM. This field should be read as '1'
11077 * to indicate that the output has been completely written.
11078 * When writing a command completion or response to an internal processor,
11079 * the order of writes has to be such that this field is written last.
11084 /**********************
11085 * hwrm_func_drv_rgtr *
11086 **********************/
11089 /* hwrm_func_drv_rgtr_input (size:896b/112B) */
11090 struct hwrm_func_drv_rgtr_input {
11091 /* The HWRM command request type. */
11094 * The completion ring to send the completion event on. This should
11095 * be the NQ ID returned from the `nq_alloc` HWRM command.
11097 uint16_t cmpl_ring;
11099 * The sequence ID is used by the driver for tracking multiple
11100 * commands. This ID is treated as opaque data by the firmware and
11101 * the value is returned in the `hwrm_resp_hdr` upon completion.
11105 * The target ID of the command:
11106 * * 0x0-0xFFF8 - The function ID
11107 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
11108 * * 0xFFFD - Reserved for user-space HWRM interface
11111 uint16_t target_id;
11113 * A physical address pointer pointing to a host buffer that the
11114 * command's response data will be written. This can be either a host
11115 * physical address (HPA) or a guest physical address (GPA) and must
11116 * point to a physically contiguous block of memory.
11118 uint64_t resp_addr;
11121 * When this bit is '1', the function driver is requesting
11122 * all requests from its children VF drivers to be
11123 * forwarded to itself.
11124 * This flag can only be set by the PF driver.
11125 * If a VF driver sets this flag, it should be ignored
11128 #define HWRM_FUNC_DRV_RGTR_INPUT_FLAGS_FWD_ALL_MODE \
11131 * When this bit is '1', the function is requesting none of
11132 * the requests from its children VF drivers to be
11133 * forwarded to itself.
11134 * This flag can only be set by the PF driver.
11135 * If a VF driver sets this flag, it should be ignored
11138 #define HWRM_FUNC_DRV_RGTR_INPUT_FLAGS_FWD_NONE_MODE \
11141 * When this bit is '1', then ver_maj_8b, ver_min_8b, ver_upd_8b
11142 * fields shall be ignored and ver_maj, ver_min, ver_upd
11143 * and ver_patch shall be used for the driver version information.
11144 * When this bit is '0', then ver_maj_8b, ver_min_8b, ver_upd_8b
11145 * fields shall be used for the driver version information and
11146 * ver_maj, ver_min, ver_upd and ver_patch shall be ignored.
11148 #define HWRM_FUNC_DRV_RGTR_INPUT_FLAGS_16BIT_VER_MODE \
11151 * When this bit is '1', the function is indicating support of
11152 * 64bit flow handle. The firmware that only supports 64bit flow
11153 * handle should check this bit before allowing processing of
11154 * HWRM_CFA_FLOW_XXX commands from the requesting function as firmware
11155 * with 64bit flow handle support can only be compatible with drivers
11156 * that support 64bit flow handle. The legacy drivers that don't support
11157 * 64bit flow handle won't be able to use HWRM_CFA_FLOW_XXX commands when
11158 * running with new firmware that only supports 64bit flow handle. The new
11159 * firmware support 64bit flow handle returns HWRM_ERR_CODE_CMD_NOT_SUPPORTED
11160 * status to the legacy driver when encounters these commands.
11162 #define HWRM_FUNC_DRV_RGTR_INPUT_FLAGS_FLOW_HANDLE_64BIT_MODE \
11165 * When this bit is '1', the function is indicating support of
11166 * Hot Reset. The driver interface will destroy the resources,
11167 * unregister the function and register again up on receiving
11168 * the RESET_NOTIFY Async notification from the core firmware.
11169 * The core firmware will this use flag and trigger the Hot Reset
11170 * process only if all the registered driver instances are capable
11173 #define HWRM_FUNC_DRV_RGTR_INPUT_FLAGS_HOT_RESET_SUPPORT \
11176 * When this bit is 1, the function is indicating the support of the
11177 * error recovery capability. Error recovery support will be used by
11178 * firmware only if all the driver instances support error recovery
11179 * process. By setting this bit, driver is indicating support for
11180 * corresponding async event completion message. These will be
11181 * delivered to the driver even if they did not register for it.
11182 * If supported, after receiving reset notify async event with fatal
11183 * flag set in event data1, then all the drivers have to tear down
11184 * their resources without sending any HWRM commands to FW.
11186 #define HWRM_FUNC_DRV_RGTR_INPUT_FLAGS_ERROR_RECOVERY_SUPPORT \
11189 * When this bit is 1, the function is indicating the support of the
11190 * Master capability. The Firmware will use this capability to select the
11191 * Master function. The master function will be used to initiate
11192 * designated functionality like error recovery etc… If none of the
11193 * registered PF’s or trusted VF’s indicate this support, then
11194 * firmware will select the 1st registered PF as Master capable instance.
11196 #define HWRM_FUNC_DRV_RGTR_INPUT_FLAGS_MASTER_SUPPORT \
11200 * This bit must be '1' for the os_type field to be
11203 #define HWRM_FUNC_DRV_RGTR_INPUT_ENABLES_OS_TYPE \
11206 * This bit must be '1' for the ver field to be
11209 #define HWRM_FUNC_DRV_RGTR_INPUT_ENABLES_VER \
11212 * This bit must be '1' for the timestamp field to be
11215 #define HWRM_FUNC_DRV_RGTR_INPUT_ENABLES_TIMESTAMP \
11218 * This bit must be '1' for the vf_req_fwd field to be
11221 #define HWRM_FUNC_DRV_RGTR_INPUT_ENABLES_VF_REQ_FWD \
11224 * This bit must be '1' for the async_event_fwd field to be
11227 #define HWRM_FUNC_DRV_RGTR_INPUT_ENABLES_ASYNC_EVENT_FWD \
11229 /* This value indicates the type of OS. The values are based on CIM_OperatingSystem.mof file as published by the DMTF. */
11232 #define HWRM_FUNC_DRV_RGTR_INPUT_OS_TYPE_UNKNOWN UINT32_C(0x0)
11233 /* Other OS not listed below. */
11234 #define HWRM_FUNC_DRV_RGTR_INPUT_OS_TYPE_OTHER UINT32_C(0x1)
11236 #define HWRM_FUNC_DRV_RGTR_INPUT_OS_TYPE_MSDOS UINT32_C(0xe)
11238 #define HWRM_FUNC_DRV_RGTR_INPUT_OS_TYPE_WINDOWS UINT32_C(0x12)
11240 #define HWRM_FUNC_DRV_RGTR_INPUT_OS_TYPE_SOLARIS UINT32_C(0x1d)
11242 #define HWRM_FUNC_DRV_RGTR_INPUT_OS_TYPE_LINUX UINT32_C(0x24)
11244 #define HWRM_FUNC_DRV_RGTR_INPUT_OS_TYPE_FREEBSD UINT32_C(0x2a)
11245 /* VMware ESXi OS. */
11246 #define HWRM_FUNC_DRV_RGTR_INPUT_OS_TYPE_ESXI UINT32_C(0x68)
11247 /* Microsoft Windows 8 64-bit OS. */
11248 #define HWRM_FUNC_DRV_RGTR_INPUT_OS_TYPE_WIN864 UINT32_C(0x73)
11249 /* Microsoft Windows Server 2012 R2 OS. */
11250 #define HWRM_FUNC_DRV_RGTR_INPUT_OS_TYPE_WIN2012R2 UINT32_C(0x74)
11252 #define HWRM_FUNC_DRV_RGTR_INPUT_OS_TYPE_UEFI UINT32_C(0x8000)
11253 #define HWRM_FUNC_DRV_RGTR_INPUT_OS_TYPE_LAST \
11254 HWRM_FUNC_DRV_RGTR_INPUT_OS_TYPE_UEFI
11255 /* This is the 8bit major version of the driver. */
11256 uint8_t ver_maj_8b;
11257 /* This is the 8bit minor version of the driver. */
11258 uint8_t ver_min_8b;
11259 /* This is the 8bit update version of the driver. */
11260 uint8_t ver_upd_8b;
11261 uint8_t unused_0[3];
11263 * This is a 32-bit timestamp provided by the driver for
11265 * The timestamp is in multiples of 1ms.
11267 uint32_t timestamp;
11268 uint8_t unused_1[4];
11270 * This is a 256-bit bit mask provided by the PF driver for
11271 * letting the HWRM know what commands issued by the VF driver
11272 * to the HWRM should be forwarded to the PF driver.
11273 * Nth bit refers to the Nth req_type.
11275 * Setting Nth bit to 1 indicates that requests from the
11276 * VF driver with req_type equal to N shall be forwarded to
11277 * the parent PF driver.
11279 * This field is not valid for the VF driver.
11281 uint32_t vf_req_fwd[8];
11283 * This is a 256-bit bit mask provided by the function driver
11284 * (PF or VF driver) to indicate the list of asynchronous event
11285 * completions to be forwarded.
11287 * Nth bit refers to the Nth event_id.
11289 * Setting Nth bit to 1 by the function driver shall result in
11290 * the HWRM forwarding asynchronous event completion with
11291 * event_id equal to N.
11293 * If all bits are set to 0 (value of 0), then the HWRM shall
11294 * not forward any asynchronous event completion to this
11297 uint32_t async_event_fwd[8];
11298 /* This is the 16bit major version of the driver. */
11300 /* This is the 16bit minor version of the driver. */
11302 /* This is the 16bit update version of the driver. */
11304 /* This is the 16bit patch version of the driver. */
11305 uint16_t ver_patch;
11308 /* hwrm_func_drv_rgtr_output (size:128b/16B) */
11309 struct hwrm_func_drv_rgtr_output {
11310 /* The specific error status for the command. */
11311 uint16_t error_code;
11312 /* The HWRM command request type. */
11314 /* The sequence ID from the original command. */
11316 /* The length of the response data in number of bytes. */
11320 * When this bit is '1', it indicates that the
11321 * HWRM_FUNC_DRV_IF_CHANGE call is supported.
11323 #define HWRM_FUNC_DRV_RGTR_OUTPUT_FLAGS_IF_CHANGE_SUPPORTED \
11325 uint8_t unused_0[3];
11327 * This field is used in Output records to indicate that the output
11328 * is completely written to RAM. This field should be read as '1'
11329 * to indicate that the output has been completely written.
11330 * When writing a command completion or response to an internal processor,
11331 * the order of writes has to be such that this field is written last.
11336 /************************
11337 * hwrm_func_drv_unrgtr *
11338 ************************/
11341 /* hwrm_func_drv_unrgtr_input (size:192b/24B) */
11342 struct hwrm_func_drv_unrgtr_input {
11343 /* The HWRM command request type. */
11346 * The completion ring to send the completion event on. This should
11347 * be the NQ ID returned from the `nq_alloc` HWRM command.
11349 uint16_t cmpl_ring;
11351 * The sequence ID is used by the driver for tracking multiple
11352 * commands. This ID is treated as opaque data by the firmware and
11353 * the value is returned in the `hwrm_resp_hdr` upon completion.
11357 * The target ID of the command:
11358 * * 0x0-0xFFF8 - The function ID
11359 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
11360 * * 0xFFFD - Reserved for user-space HWRM interface
11363 uint16_t target_id;
11365 * A physical address pointer pointing to a host buffer that the
11366 * command's response data will be written. This can be either a host
11367 * physical address (HPA) or a guest physical address (GPA) and must
11368 * point to a physically contiguous block of memory.
11370 uint64_t resp_addr;
11373 * When this bit is '1', the function driver is notifying
11374 * the HWRM to prepare for the shutdown.
11376 #define HWRM_FUNC_DRV_UNRGTR_INPUT_FLAGS_PREPARE_FOR_SHUTDOWN \
11378 uint8_t unused_0[4];
11381 /* hwrm_func_drv_unrgtr_output (size:128b/16B) */
11382 struct hwrm_func_drv_unrgtr_output {
11383 /* The specific error status for the command. */
11384 uint16_t error_code;
11385 /* The HWRM command request type. */
11387 /* The sequence ID from the original command. */
11389 /* The length of the response data in number of bytes. */
11391 uint8_t unused_0[7];
11393 * This field is used in Output records to indicate that the output
11394 * is completely written to RAM. This field should be read as '1'
11395 * to indicate that the output has been completely written.
11396 * When writing a command completion or response to an internal processor,
11397 * the order of writes has to be such that this field is written last.
11402 /**********************
11403 * hwrm_func_buf_rgtr *
11404 **********************/
11407 /* hwrm_func_buf_rgtr_input (size:1024b/128B) */
11408 struct hwrm_func_buf_rgtr_input {
11409 /* The HWRM command request type. */
11412 * The completion ring to send the completion event on. This should
11413 * be the NQ ID returned from the `nq_alloc` HWRM command.
11415 uint16_t cmpl_ring;
11417 * The sequence ID is used by the driver for tracking multiple
11418 * commands. This ID is treated as opaque data by the firmware and
11419 * the value is returned in the `hwrm_resp_hdr` upon completion.
11423 * The target ID of the command:
11424 * * 0x0-0xFFF8 - The function ID
11425 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
11426 * * 0xFFFD - Reserved for user-space HWRM interface
11429 uint16_t target_id;
11431 * A physical address pointer pointing to a host buffer that the
11432 * command's response data will be written. This can be either a host
11433 * physical address (HPA) or a guest physical address (GPA) and must
11434 * point to a physically contiguous block of memory.
11436 uint64_t resp_addr;
11439 * This bit must be '1' for the vf_id field to be
11442 #define HWRM_FUNC_BUF_RGTR_INPUT_ENABLES_VF_ID UINT32_C(0x1)
11444 * This bit must be '1' for the err_buf_addr field to be
11447 #define HWRM_FUNC_BUF_RGTR_INPUT_ENABLES_ERR_BUF_ADDR UINT32_C(0x2)
11449 * This value is used to identify a Virtual Function (VF).
11450 * The scope of VF ID is local within a PF.
11454 * This field represents the number of pages used for request
11457 uint16_t req_buf_num_pages;
11459 * This field represents the page size used for request
11462 uint16_t req_buf_page_size;
11464 #define HWRM_FUNC_BUF_RGTR_INPUT_REQ_BUF_PAGE_SIZE_16B UINT32_C(0x4)
11466 #define HWRM_FUNC_BUF_RGTR_INPUT_REQ_BUF_PAGE_SIZE_4K UINT32_C(0xc)
11468 #define HWRM_FUNC_BUF_RGTR_INPUT_REQ_BUF_PAGE_SIZE_8K UINT32_C(0xd)
11470 #define HWRM_FUNC_BUF_RGTR_INPUT_REQ_BUF_PAGE_SIZE_64K UINT32_C(0x10)
11472 #define HWRM_FUNC_BUF_RGTR_INPUT_REQ_BUF_PAGE_SIZE_2M UINT32_C(0x15)
11474 #define HWRM_FUNC_BUF_RGTR_INPUT_REQ_BUF_PAGE_SIZE_4M UINT32_C(0x16)
11476 #define HWRM_FUNC_BUF_RGTR_INPUT_REQ_BUF_PAGE_SIZE_1G UINT32_C(0x1e)
11477 #define HWRM_FUNC_BUF_RGTR_INPUT_REQ_BUF_PAGE_SIZE_LAST \
11478 HWRM_FUNC_BUF_RGTR_INPUT_REQ_BUF_PAGE_SIZE_1G
11479 /* The length of the request buffer per VF in bytes. */
11480 uint16_t req_buf_len;
11481 /* The length of the response buffer in bytes. */
11482 uint16_t resp_buf_len;
11483 uint8_t unused_0[2];
11484 /* This field represents the page address of page #0. */
11485 uint64_t req_buf_page_addr0;
11486 /* This field represents the page address of page #1. */
11487 uint64_t req_buf_page_addr1;
11488 /* This field represents the page address of page #2. */
11489 uint64_t req_buf_page_addr2;
11490 /* This field represents the page address of page #3. */
11491 uint64_t req_buf_page_addr3;
11492 /* This field represents the page address of page #4. */
11493 uint64_t req_buf_page_addr4;
11494 /* This field represents the page address of page #5. */
11495 uint64_t req_buf_page_addr5;
11496 /* This field represents the page address of page #6. */
11497 uint64_t req_buf_page_addr6;
11498 /* This field represents the page address of page #7. */
11499 uint64_t req_buf_page_addr7;
11500 /* This field represents the page address of page #8. */
11501 uint64_t req_buf_page_addr8;
11502 /* This field represents the page address of page #9. */
11503 uint64_t req_buf_page_addr9;
11505 * This field is used to receive the error reporting from
11506 * the chipset. Only applicable for PFs.
11508 uint64_t error_buf_addr;
11510 * This field is used to receive the response forwarded by the
11513 uint64_t resp_buf_addr;
11516 /* hwrm_func_buf_rgtr_output (size:128b/16B) */
11517 struct hwrm_func_buf_rgtr_output {
11518 /* The specific error status for the command. */
11519 uint16_t error_code;
11520 /* The HWRM command request type. */
11522 /* The sequence ID from the original command. */
11524 /* The length of the response data in number of bytes. */
11526 uint8_t unused_0[7];
11528 * This field is used in Output records to indicate that the output
11529 * is completely written to RAM. This field should be read as '1'
11530 * to indicate that the output has been completely written.
11531 * When writing a command completion or response to an internal processor,
11532 * the order of writes has to be such that this field is written last.
11537 /************************
11538 * hwrm_func_buf_unrgtr *
11539 ************************/
11542 /* hwrm_func_buf_unrgtr_input (size:192b/24B) */
11543 struct hwrm_func_buf_unrgtr_input {
11544 /* The HWRM command request type. */
11547 * The completion ring to send the completion event on. This should
11548 * be the NQ ID returned from the `nq_alloc` HWRM command.
11550 uint16_t cmpl_ring;
11552 * The sequence ID is used by the driver for tracking multiple
11553 * commands. This ID is treated as opaque data by the firmware and
11554 * the value is returned in the `hwrm_resp_hdr` upon completion.
11558 * The target ID of the command:
11559 * * 0x0-0xFFF8 - The function ID
11560 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
11561 * * 0xFFFD - Reserved for user-space HWRM interface
11564 uint16_t target_id;
11566 * A physical address pointer pointing to a host buffer that the
11567 * command's response data will be written. This can be either a host
11568 * physical address (HPA) or a guest physical address (GPA) and must
11569 * point to a physically contiguous block of memory.
11571 uint64_t resp_addr;
11574 * This bit must be '1' for the vf_id field to be
11577 #define HWRM_FUNC_BUF_UNRGTR_INPUT_ENABLES_VF_ID UINT32_C(0x1)
11579 * This value is used to identify a Virtual Function (VF).
11580 * The scope of VF ID is local within a PF.
11583 uint8_t unused_0[2];
11586 /* hwrm_func_buf_unrgtr_output (size:128b/16B) */
11587 struct hwrm_func_buf_unrgtr_output {
11588 /* The specific error status for the command. */
11589 uint16_t error_code;
11590 /* The HWRM command request type. */
11592 /* The sequence ID from the original command. */
11594 /* The length of the response data in number of bytes. */
11596 uint8_t unused_0[7];
11598 * This field is used in Output records to indicate that the output
11599 * is completely written to RAM. This field should be read as '1'
11600 * to indicate that the output has been completely written.
11601 * When writing a command completion or response to an internal processor,
11602 * the order of writes has to be such that this field is written last.
11607 /**********************
11608 * hwrm_func_drv_qver *
11609 **********************/
11612 /* hwrm_func_drv_qver_input (size:192b/24B) */
11613 struct hwrm_func_drv_qver_input {
11614 /* The HWRM command request type. */
11617 * The completion ring to send the completion event on. This should
11618 * be the NQ ID returned from the `nq_alloc` HWRM command.
11620 uint16_t cmpl_ring;
11622 * The sequence ID is used by the driver for tracking multiple
11623 * commands. This ID is treated as opaque data by the firmware and
11624 * the value is returned in the `hwrm_resp_hdr` upon completion.
11628 * The target ID of the command:
11629 * * 0x0-0xFFF8 - The function ID
11630 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
11631 * * 0xFFFD - Reserved for user-space HWRM interface
11634 uint16_t target_id;
11636 * A physical address pointer pointing to a host buffer that the
11637 * command's response data will be written. This can be either a host
11638 * physical address (HPA) or a guest physical address (GPA) and must
11639 * point to a physically contiguous block of memory.
11641 uint64_t resp_addr;
11642 /* Reserved for future use. */
11645 * Function ID of the function that is being queried.
11646 * 0xFF... (All Fs) if the query is for the requesting
11650 uint8_t unused_0[2];
11653 /* hwrm_func_drv_qver_output (size:256b/32B) */
11654 struct hwrm_func_drv_qver_output {
11655 /* The specific error status for the command. */
11656 uint16_t error_code;
11657 /* The HWRM command request type. */
11659 /* The sequence ID from the original command. */
11661 /* The length of the response data in number of bytes. */
11663 /* This value indicates the type of OS. The values are based on CIM_OperatingSystem.mof file as published by the DMTF. */
11666 #define HWRM_FUNC_DRV_QVER_OUTPUT_OS_TYPE_UNKNOWN UINT32_C(0x0)
11667 /* Other OS not listed below. */
11668 #define HWRM_FUNC_DRV_QVER_OUTPUT_OS_TYPE_OTHER UINT32_C(0x1)
11670 #define HWRM_FUNC_DRV_QVER_OUTPUT_OS_TYPE_MSDOS UINT32_C(0xe)
11672 #define HWRM_FUNC_DRV_QVER_OUTPUT_OS_TYPE_WINDOWS UINT32_C(0x12)
11674 #define HWRM_FUNC_DRV_QVER_OUTPUT_OS_TYPE_SOLARIS UINT32_C(0x1d)
11676 #define HWRM_FUNC_DRV_QVER_OUTPUT_OS_TYPE_LINUX UINT32_C(0x24)
11678 #define HWRM_FUNC_DRV_QVER_OUTPUT_OS_TYPE_FREEBSD UINT32_C(0x2a)
11679 /* VMware ESXi OS. */
11680 #define HWRM_FUNC_DRV_QVER_OUTPUT_OS_TYPE_ESXI UINT32_C(0x68)
11681 /* Microsoft Windows 8 64-bit OS. */
11682 #define HWRM_FUNC_DRV_QVER_OUTPUT_OS_TYPE_WIN864 UINT32_C(0x73)
11683 /* Microsoft Windows Server 2012 R2 OS. */
11684 #define HWRM_FUNC_DRV_QVER_OUTPUT_OS_TYPE_WIN2012R2 UINT32_C(0x74)
11686 #define HWRM_FUNC_DRV_QVER_OUTPUT_OS_TYPE_UEFI UINT32_C(0x8000)
11687 #define HWRM_FUNC_DRV_QVER_OUTPUT_OS_TYPE_LAST \
11688 HWRM_FUNC_DRV_QVER_OUTPUT_OS_TYPE_UEFI
11689 /* This is the 8bit major version of the driver. */
11690 uint8_t ver_maj_8b;
11691 /* This is the 8bit minor version of the driver. */
11692 uint8_t ver_min_8b;
11693 /* This is the 8bit update version of the driver. */
11694 uint8_t ver_upd_8b;
11695 uint8_t unused_0[3];
11696 /* This is the 16bit major version of the driver. */
11698 /* This is the 16bit minor version of the driver. */
11700 /* This is the 16bit update version of the driver. */
11702 /* This is the 16bit patch version of the driver. */
11703 uint16_t ver_patch;
11704 uint8_t unused_1[7];
11706 * This field is used in Output records to indicate that the output
11707 * is completely written to RAM. This field should be read as '1'
11708 * to indicate that the output has been completely written.
11709 * When writing a command completion or response to an internal processor,
11710 * the order of writes has to be such that this field is written last.
11715 /****************************
11716 * hwrm_func_resource_qcaps *
11717 ****************************/
11720 /* hwrm_func_resource_qcaps_input (size:192b/24B) */
11721 struct hwrm_func_resource_qcaps_input {
11722 /* The HWRM command request type. */
11725 * The completion ring to send the completion event on. This should
11726 * be the NQ ID returned from the `nq_alloc` HWRM command.
11728 uint16_t cmpl_ring;
11730 * The sequence ID is used by the driver for tracking multiple
11731 * commands. This ID is treated as opaque data by the firmware and
11732 * the value is returned in the `hwrm_resp_hdr` upon completion.
11736 * The target ID of the command:
11737 * * 0x0-0xFFF8 - The function ID
11738 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
11739 * * 0xFFFD - Reserved for user-space HWRM interface
11742 uint16_t target_id;
11744 * A physical address pointer pointing to a host buffer that the
11745 * command's response data will be written. This can be either a host
11746 * physical address (HPA) or a guest physical address (GPA) and must
11747 * point to a physically contiguous block of memory.
11749 uint64_t resp_addr;
11751 * Function ID of the function that is being queried.
11752 * 0xFF... (All Fs) if the query is for the requesting
11756 uint8_t unused_0[6];
11759 /* hwrm_func_resource_qcaps_output (size:448b/56B) */
11760 struct hwrm_func_resource_qcaps_output {
11761 /* The specific error status for the command. */
11762 uint16_t error_code;
11763 /* The HWRM command request type. */
11765 /* The sequence ID from the original command. */
11767 /* The length of the response data in number of bytes. */
11769 /* Maximum guaranteed number of VFs supported by PF. Not applicable for VFs. */
11771 /* Maximum guaranteed number of MSI-X vectors supported by function */
11773 /* Hint of strategy to be used by PF driver to reserve resources for its VF */
11774 uint16_t vf_reservation_strategy;
11775 /* The PF driver should evenly divide its remaining resources among all VFs. */
11776 #define HWRM_FUNC_RESOURCE_QCAPS_OUTPUT_VF_RESERVATION_STRATEGY_MAXIMAL \
11778 /* The PF driver should only reserve minimal resources for each VF. */
11779 #define HWRM_FUNC_RESOURCE_QCAPS_OUTPUT_VF_RESERVATION_STRATEGY_MINIMAL \
11782 * The PF driver should not reserve any resources for each VF until the
11783 * the VF interface is brought up.
11785 #define HWRM_FUNC_RESOURCE_QCAPS_OUTPUT_VF_RESERVATION_STRATEGY_MINIMAL_STATIC \
11787 #define HWRM_FUNC_RESOURCE_QCAPS_OUTPUT_VF_RESERVATION_STRATEGY_LAST \
11788 HWRM_FUNC_RESOURCE_QCAPS_OUTPUT_VF_RESERVATION_STRATEGY_MINIMAL_STATIC
11789 /* Minimum guaranteed number of RSS/COS contexts */
11790 uint16_t min_rsscos_ctx;
11791 /* Maximum non-guaranteed number of RSS/COS contexts */
11792 uint16_t max_rsscos_ctx;
11793 /* Minimum guaranteed number of completion rings */
11794 uint16_t min_cmpl_rings;
11795 /* Maximum non-guaranteed number of completion rings */
11796 uint16_t max_cmpl_rings;
11797 /* Minimum guaranteed number of transmit rings */
11798 uint16_t min_tx_rings;
11799 /* Maximum non-guaranteed number of transmit rings */
11800 uint16_t max_tx_rings;
11801 /* Minimum guaranteed number of receive rings */
11802 uint16_t min_rx_rings;
11803 /* Maximum non-guaranteed number of receive rings */
11804 uint16_t max_rx_rings;
11805 /* Minimum guaranteed number of L2 contexts */
11806 uint16_t min_l2_ctxs;
11807 /* Maximum non-guaranteed number of L2 contexts */
11808 uint16_t max_l2_ctxs;
11809 /* Minimum guaranteed number of VNICs */
11810 uint16_t min_vnics;
11811 /* Maximum non-guaranteed number of VNICs */
11812 uint16_t max_vnics;
11813 /* Minimum guaranteed number of statistic contexts */
11814 uint16_t min_stat_ctx;
11815 /* Maximum non-guaranteed number of statistic contexts */
11816 uint16_t max_stat_ctx;
11817 /* Minimum guaranteed number of ring groups */
11818 uint16_t min_hw_ring_grps;
11819 /* Maximum non-guaranteed number of ring groups */
11820 uint16_t max_hw_ring_grps;
11822 * Maximum number of inputs into the transmit scheduler for this function.
11823 * The number of TX rings assigned to the function cannot exceed this value.
11825 uint16_t max_tx_scheduler_inputs;
11828 * When this bit is '1', it indicates that VF_RESOURCE_CFG supports
11829 * feature to reserve all minimum resources when minimum >= 1, otherwise
11830 * returns an error.
11832 #define HWRM_FUNC_RESOURCE_QCAPS_OUTPUT_FLAGS_MIN_GUARANTEED \
11834 uint8_t unused_0[5];
11836 * This field is used in Output records to indicate that the output
11837 * is completely written to RAM. This field should be read as '1'
11838 * to indicate that the output has been completely written.
11839 * When writing a command completion or response to an internal processor,
11840 * the order of writes has to be such that this field is written last.
11845 /*********************************
11846 * hwrm_func_backing_store_qcaps *
11847 *********************************/
11850 /* hwrm_func_backing_store_qcaps_input (size:128b/16B) */
11851 struct hwrm_func_backing_store_qcaps_input {
11852 /* The HWRM command request type. */
11855 * The completion ring to send the completion event on. This should
11856 * be the NQ ID returned from the `nq_alloc` HWRM command.
11858 uint16_t cmpl_ring;
11860 * The sequence ID is used by the driver for tracking multiple
11861 * commands. This ID is treated as opaque data by the firmware and
11862 * the value is returned in the `hwrm_resp_hdr` upon completion.
11866 * The target ID of the command:
11867 * * 0x0-0xFFF8 - The function ID
11868 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
11869 * * 0xFFFD - Reserved for user-space HWRM interface
11872 uint16_t target_id;
11874 * A physical address pointer pointing to a host buffer that the
11875 * command's response data will be written. This can be either a host
11876 * physical address (HPA) or a guest physical address (GPA) and must
11877 * point to a physically contiguous block of memory.
11879 uint64_t resp_addr;
11882 /* hwrm_func_backing_store_qcaps_output (size:640b/80B) */
11883 struct hwrm_func_backing_store_qcaps_output {
11884 /* The specific error status for the command. */
11885 uint16_t error_code;
11886 /* The HWRM command request type. */
11888 /* The sequence ID from the original command. */
11890 /* The length of the response data in number of bytes. */
11892 /* Maximum number of QP context entries supported for this function. */
11893 uint32_t qp_max_entries;
11895 * Minimum number of QP context entries that are needed to be reserved
11896 * for QP1 for the PF and its VFs. PF drivers must allocate at least
11897 * this many QP context entries, even if RoCE will not be used.
11899 uint16_t qp_min_qp1_entries;
11900 /* Maximum number of QP context entries that can be used for L2. */
11901 uint16_t qp_max_l2_entries;
11902 /* Number of bytes that must be allocated for each context entry. */
11903 uint16_t qp_entry_size;
11904 /* Maximum number of SRQ context entries that can be used for L2. */
11905 uint16_t srq_max_l2_entries;
11906 /* Maximum number of SRQ context entries supported for this function. */
11907 uint32_t srq_max_entries;
11908 /* Number of bytes that must be allocated for each context entry. */
11909 uint16_t srq_entry_size;
11910 /* Maximum number of CQ context entries that can be used for L2. */
11911 uint16_t cq_max_l2_entries;
11912 /* Maximum number of CQ context entries supported for this function. */
11913 uint32_t cq_max_entries;
11914 /* Number of bytes that must be allocated for each context entry. */
11915 uint16_t cq_entry_size;
11916 /* Maximum number of VNIC context entries supported for this function. */
11917 uint16_t vnic_max_vnic_entries;
11918 /* Maximum number of Ring table context entries supported for this function. */
11919 uint16_t vnic_max_ring_table_entries;
11920 /* Number of bytes that must be allocated for each context entry. */
11921 uint16_t vnic_entry_size;
11922 /* Maximum number of statistic context entries supported for this function. */
11923 uint32_t stat_max_entries;
11924 /* Number of bytes that must be allocated for each context entry. */
11925 uint16_t stat_entry_size;
11926 /* Number of bytes that must be allocated for each context entry. */
11927 uint16_t tqm_entry_size;
11928 /* Minimum number of TQM context entries required per ring. */
11929 uint32_t tqm_min_entries_per_ring;
11931 * Maximum number of TQM context entries supported per ring. This is
11932 * actually a recommended TQM queue size based on worst case usage of
11935 * TQM fastpath rings should be sized large enough to accommodate the
11936 * maximum number of QPs (either L2 or RoCE, or both if shared)
11937 * that can be enqueued to the TQM ring.
11939 * TQM slowpath rings should be sized as follows:
11941 * num_entries = num_vnics + num_l2_tx_rings + 2 * num_roce_qps + tqm_min_size
11944 * num_vnics is the number of VNICs allocated in the VNIC backing store
11945 * num_l2_tx_rings is the number of L2 rings in the QP backing store
11946 * num_roce_qps is the number of RoCE QPs in the QP backing store
11947 * tqm_min_size is tqm_min_entries_per_ring reported by
11948 * HWRM_FUNC_BACKING_STORE_QCAPS
11950 * Note that TQM ring sizes cannot be extended while the system is
11951 * operational. If a PF driver needs to extend a TQM ring, it needs
11952 * to reset the function (e.g. HWRM_FUNC_RESET) and then reallocate
11953 * the backing store.
11955 uint32_t tqm_max_entries_per_ring;
11957 * Maximum number of MR plus AV context entries supported for this
11960 uint32_t mrav_max_entries;
11961 /* Number of bytes that must be allocated for each context entry. */
11962 uint16_t mrav_entry_size;
11963 /* Number of bytes that must be allocated for each context entry. */
11964 uint16_t tim_entry_size;
11965 /* Maximum number of Timer context entries supported for this function. */
11966 uint32_t tim_max_entries;
11968 * When this field is zero, the 32b `mrav_num_entries` field in the
11969 * `backing_store_cfg` and `backing_store_qcfg` commands represents
11970 * the total number of MR plus AV entries allowed in the MR/AV backing
11973 * When this field is non-zero, the 32b `mrav_num_entries` field in
11974 * the `backing_store_cfg` and `backing_store_qcfg` commands is
11975 * logically divided into two 16b fields. Bits `[31:16]` represents
11976 * the `mr_num_entries` and bits `[15:0]` represents `av_num_entries`.
11977 * Both of these values are represented in a unit granularity
11978 * specified by this field. For example, if this field is 16 and
11979 * `mrav_num_entries` is `0x02000100`, then the number of MR entries
11980 * is 8192 and the number of AV entries is 4096.
11982 uint16_t mrav_num_entries_units;
11984 * The number of entries specified for any TQM ring must be a
11985 * multiple of this value to prevent any resource allocation
11988 uint8_t tqm_entries_multiple;
11990 * Initializer to be used by drivers
11991 * to initialize context memory to ensure
11992 * context subsystem flags an error for an attack
11993 * before the first time context load.
11995 uint8_t ctx_kind_initializer;
11996 /* Reserved for future. */
11998 /* Reserved for future. */
12001 * Count of TQM fastpath rings to be used for allocating backing store.
12002 * Backing store configuration must be specified for each TQM ring from
12003 * this count in `backing_store_cfg`.
12005 uint8_t tqm_fp_rings_count;
12007 * This field is used in Output records to indicate that the output
12008 * is completely written to RAM. This field should be read as '1'
12009 * to indicate that the output has been completely written.
12010 * When writing a command completion or response to an internal processor,
12011 * the order of writes has to be such that this field is written last.
12016 /*******************************
12017 * hwrm_func_backing_store_cfg *
12018 *******************************/
12021 /* hwrm_func_backing_store_cfg_input (size:2048b/256B) */
12022 struct hwrm_func_backing_store_cfg_input {
12023 /* The HWRM command request type. */
12026 * The completion ring to send the completion event on. This should
12027 * be the NQ ID returned from the `nq_alloc` HWRM command.
12029 uint16_t cmpl_ring;
12031 * The sequence ID is used by the driver for tracking multiple
12032 * commands. This ID is treated as opaque data by the firmware and
12033 * the value is returned in the `hwrm_resp_hdr` upon completion.
12037 * The target ID of the command:
12038 * * 0x0-0xFFF8 - The function ID
12039 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
12040 * * 0xFFFD - Reserved for user-space HWRM interface
12043 uint16_t target_id;
12045 * A physical address pointer pointing to a host buffer that the
12046 * command's response data will be written. This can be either a host
12047 * physical address (HPA) or a guest physical address (GPA) and must
12048 * point to a physically contiguous block of memory.
12050 uint64_t resp_addr;
12053 * When set, the firmware only uses on-chip resources and does not
12054 * expect any backing store to be provided by the host driver. This
12055 * mode provides minimal L2 functionality (e.g. limited L2 resources,
12058 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_FLAGS_PREBOOT_MODE \
12061 * When set, the 32b `mrav_num_entries` field is logically divided
12062 * into two 16b fields, `mr_num_entries` and `av_num_entries`.
12064 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_FLAGS_MRAV_RESERVATION_SPLIT \
12068 * This bit must be '1' for the qp fields to be
12071 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_QP \
12074 * This bit must be '1' for the srq fields to be
12077 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_SRQ \
12080 * This bit must be '1' for the cq fields to be
12083 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_CQ \
12086 * This bit must be '1' for the vnic fields to be
12089 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_VNIC \
12092 * This bit must be '1' for the stat fields to be
12095 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_STAT \
12098 * This bit must be '1' for the tqm_sp fields to be
12101 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_TQM_SP \
12104 * This bit must be '1' for the tqm_ring0 fields to be
12107 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_TQM_RING0 \
12110 * This bit must be '1' for the tqm_ring1 fields to be
12113 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_TQM_RING1 \
12116 * This bit must be '1' for the tqm_ring2 fields to be
12119 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_TQM_RING2 \
12122 * This bit must be '1' for the tqm_ring3 fields to be
12125 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_TQM_RING3 \
12128 * This bit must be '1' for the tqm_ring4 fields to be
12131 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_TQM_RING4 \
12134 * This bit must be '1' for the tqm_ring5 fields to be
12137 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_TQM_RING5 \
12140 * This bit must be '1' for the tqm_ring6 fields to be
12143 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_TQM_RING6 \
12146 * This bit must be '1' for the tqm_ring7 fields to be
12149 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_TQM_RING7 \
12152 * This bit must be '1' for the mrav fields to be
12155 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_MRAV \
12158 * This bit must be '1' for the tim fields to be
12161 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_TIM \
12163 /* QPC page size and level. */
12164 uint8_t qpc_pg_size_qpc_lvl;
12165 /* QPC PBL indirect levels. */
12166 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_QPC_LVL_MASK \
12168 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_QPC_LVL_SFT 0
12169 /* PBL pointer is physical start address. */
12170 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_QPC_LVL_LVL_0 \
12172 /* PBL pointer points to PTE table. */
12173 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_QPC_LVL_LVL_1 \
12175 /* PBL pointer points to PDE table with each entry pointing to PTE tables. */
12176 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_QPC_LVL_LVL_2 \
12178 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_QPC_LVL_LAST \
12179 HWRM_FUNC_BACKING_STORE_CFG_INPUT_QPC_LVL_LVL_2
12180 /* QPC page size. */
12181 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_QPC_PG_SIZE_MASK \
12183 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_QPC_PG_SIZE_SFT 4
12185 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_QPC_PG_SIZE_PG_4K \
12186 (UINT32_C(0x0) << 4)
12188 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_QPC_PG_SIZE_PG_8K \
12189 (UINT32_C(0x1) << 4)
12191 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_QPC_PG_SIZE_PG_64K \
12192 (UINT32_C(0x2) << 4)
12194 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_QPC_PG_SIZE_PG_2M \
12195 (UINT32_C(0x3) << 4)
12197 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_QPC_PG_SIZE_PG_8M \
12198 (UINT32_C(0x4) << 4)
12200 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_QPC_PG_SIZE_PG_1G \
12201 (UINT32_C(0x5) << 4)
12202 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_QPC_PG_SIZE_LAST \
12203 HWRM_FUNC_BACKING_STORE_CFG_INPUT_QPC_PG_SIZE_PG_1G
12204 /* SRQ page size and level. */
12205 uint8_t srq_pg_size_srq_lvl;
12206 /* SRQ PBL indirect levels. */
12207 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_SRQ_LVL_MASK \
12209 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_SRQ_LVL_SFT 0
12210 /* PBL pointer is physical start address. */
12211 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_SRQ_LVL_LVL_0 \
12213 /* PBL pointer points to PTE table. */
12214 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_SRQ_LVL_LVL_1 \
12216 /* PBL pointer points to PDE table with each entry pointing to PTE tables. */
12217 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_SRQ_LVL_LVL_2 \
12219 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_SRQ_LVL_LAST \
12220 HWRM_FUNC_BACKING_STORE_CFG_INPUT_SRQ_LVL_LVL_2
12221 /* SRQ page size. */
12222 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_SRQ_PG_SIZE_MASK \
12224 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_SRQ_PG_SIZE_SFT 4
12226 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_SRQ_PG_SIZE_PG_4K \
12227 (UINT32_C(0x0) << 4)
12229 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_SRQ_PG_SIZE_PG_8K \
12230 (UINT32_C(0x1) << 4)
12232 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_SRQ_PG_SIZE_PG_64K \
12233 (UINT32_C(0x2) << 4)
12235 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_SRQ_PG_SIZE_PG_2M \
12236 (UINT32_C(0x3) << 4)
12238 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_SRQ_PG_SIZE_PG_8M \
12239 (UINT32_C(0x4) << 4)
12241 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_SRQ_PG_SIZE_PG_1G \
12242 (UINT32_C(0x5) << 4)
12243 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_SRQ_PG_SIZE_LAST \
12244 HWRM_FUNC_BACKING_STORE_CFG_INPUT_SRQ_PG_SIZE_PG_1G
12245 /* CQ page size and level. */
12246 uint8_t cq_pg_size_cq_lvl;
12247 /* CQ PBL indirect levels. */
12248 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_CQ_LVL_MASK \
12250 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_CQ_LVL_SFT 0
12251 /* PBL pointer is physical start address. */
12252 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_CQ_LVL_LVL_0 \
12254 /* PBL pointer points to PTE table. */
12255 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_CQ_LVL_LVL_1 \
12257 /* PBL pointer points to PDE table with each entry pointing to PTE tables. */
12258 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_CQ_LVL_LVL_2 \
12260 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_CQ_LVL_LAST \
12261 HWRM_FUNC_BACKING_STORE_CFG_INPUT_CQ_LVL_LVL_2
12262 /* CQ page size. */
12263 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_CQ_PG_SIZE_MASK \
12265 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_CQ_PG_SIZE_SFT 4
12267 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_CQ_PG_SIZE_PG_4K \
12268 (UINT32_C(0x0) << 4)
12270 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_CQ_PG_SIZE_PG_8K \
12271 (UINT32_C(0x1) << 4)
12273 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_CQ_PG_SIZE_PG_64K \
12274 (UINT32_C(0x2) << 4)
12276 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_CQ_PG_SIZE_PG_2M \
12277 (UINT32_C(0x3) << 4)
12279 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_CQ_PG_SIZE_PG_8M \
12280 (UINT32_C(0x4) << 4)
12282 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_CQ_PG_SIZE_PG_1G \
12283 (UINT32_C(0x5) << 4)
12284 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_CQ_PG_SIZE_LAST \
12285 HWRM_FUNC_BACKING_STORE_CFG_INPUT_CQ_PG_SIZE_PG_1G
12286 /* VNIC page size and level. */
12287 uint8_t vnic_pg_size_vnic_lvl;
12288 /* VNIC PBL indirect levels. */
12289 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_VNIC_LVL_MASK \
12291 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_VNIC_LVL_SFT 0
12292 /* PBL pointer is physical start address. */
12293 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_VNIC_LVL_LVL_0 \
12295 /* PBL pointer points to PTE table. */
12296 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_VNIC_LVL_LVL_1 \
12298 /* PBL pointer points to PDE table with each entry pointing to PTE tables. */
12299 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_VNIC_LVL_LVL_2 \
12301 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_VNIC_LVL_LAST \
12302 HWRM_FUNC_BACKING_STORE_CFG_INPUT_VNIC_LVL_LVL_2
12303 /* VNIC page size. */
12304 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_VNIC_PG_SIZE_MASK \
12306 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_VNIC_PG_SIZE_SFT 4
12308 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_VNIC_PG_SIZE_PG_4K \
12309 (UINT32_C(0x0) << 4)
12311 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_VNIC_PG_SIZE_PG_8K \
12312 (UINT32_C(0x1) << 4)
12314 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_VNIC_PG_SIZE_PG_64K \
12315 (UINT32_C(0x2) << 4)
12317 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_VNIC_PG_SIZE_PG_2M \
12318 (UINT32_C(0x3) << 4)
12320 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_VNIC_PG_SIZE_PG_8M \
12321 (UINT32_C(0x4) << 4)
12323 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_VNIC_PG_SIZE_PG_1G \
12324 (UINT32_C(0x5) << 4)
12325 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_VNIC_PG_SIZE_LAST \
12326 HWRM_FUNC_BACKING_STORE_CFG_INPUT_VNIC_PG_SIZE_PG_1G
12327 /* Stat page size and level. */
12328 uint8_t stat_pg_size_stat_lvl;
12329 /* Stat PBL indirect levels. */
12330 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_STAT_LVL_MASK \
12332 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_STAT_LVL_SFT 0
12333 /* PBL pointer is physical start address. */
12334 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_STAT_LVL_LVL_0 \
12336 /* PBL pointer points to PTE table. */
12337 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_STAT_LVL_LVL_1 \
12339 /* PBL pointer points to PDE table with each entry pointing to PTE tables. */
12340 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_STAT_LVL_LVL_2 \
12342 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_STAT_LVL_LAST \
12343 HWRM_FUNC_BACKING_STORE_CFG_INPUT_STAT_LVL_LVL_2
12344 /* Stat page size. */
12345 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_STAT_PG_SIZE_MASK \
12347 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_STAT_PG_SIZE_SFT 4
12349 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_STAT_PG_SIZE_PG_4K \
12350 (UINT32_C(0x0) << 4)
12352 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_STAT_PG_SIZE_PG_8K \
12353 (UINT32_C(0x1) << 4)
12355 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_STAT_PG_SIZE_PG_64K \
12356 (UINT32_C(0x2) << 4)
12358 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_STAT_PG_SIZE_PG_2M \
12359 (UINT32_C(0x3) << 4)
12361 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_STAT_PG_SIZE_PG_8M \
12362 (UINT32_C(0x4) << 4)
12364 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_STAT_PG_SIZE_PG_1G \
12365 (UINT32_C(0x5) << 4)
12366 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_STAT_PG_SIZE_LAST \
12367 HWRM_FUNC_BACKING_STORE_CFG_INPUT_STAT_PG_SIZE_PG_1G
12368 /* TQM slow path page size and level. */
12369 uint8_t tqm_sp_pg_size_tqm_sp_lvl;
12370 /* TQM slow path PBL indirect levels. */
12371 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_SP_LVL_MASK \
12373 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_SP_LVL_SFT 0
12374 /* PBL pointer is physical start address. */
12375 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_SP_LVL_LVL_0 \
12377 /* PBL pointer points to PTE table. */
12378 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_SP_LVL_LVL_1 \
12380 /* PBL pointer points to PDE table with each entry pointing to PTE tables. */
12381 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_SP_LVL_LVL_2 \
12383 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_SP_LVL_LAST \
12384 HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_SP_LVL_LVL_2
12385 /* TQM slow path page size. */
12386 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_SP_PG_SIZE_MASK \
12388 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_SP_PG_SIZE_SFT 4
12390 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_SP_PG_SIZE_PG_4K \
12391 (UINT32_C(0x0) << 4)
12393 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_SP_PG_SIZE_PG_8K \
12394 (UINT32_C(0x1) << 4)
12396 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_SP_PG_SIZE_PG_64K \
12397 (UINT32_C(0x2) << 4)
12399 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_SP_PG_SIZE_PG_2M \
12400 (UINT32_C(0x3) << 4)
12402 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_SP_PG_SIZE_PG_8M \
12403 (UINT32_C(0x4) << 4)
12405 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_SP_PG_SIZE_PG_1G \
12406 (UINT32_C(0x5) << 4)
12407 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_SP_PG_SIZE_LAST \
12408 HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_SP_PG_SIZE_PG_1G
12409 /* TQM ring 0 page size and level. */
12410 uint8_t tqm_ring0_pg_size_tqm_ring0_lvl;
12411 /* TQM ring 0 PBL indirect levels. */
12412 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING0_LVL_MASK \
12414 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING0_LVL_SFT 0
12415 /* PBL pointer is physical start address. */
12416 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING0_LVL_LVL_0 \
12418 /* PBL pointer points to PTE table. */
12419 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING0_LVL_LVL_1 \
12421 /* PBL pointer points to PDE table with each entry pointing to PTE tables. */
12422 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING0_LVL_LVL_2 \
12424 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING0_LVL_LAST \
12425 HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING0_LVL_LVL_2
12426 /* TQM ring 0 page size. */
12427 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING0_PG_SIZE_MASK \
12429 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING0_PG_SIZE_SFT 4
12431 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING0_PG_SIZE_PG_4K \
12432 (UINT32_C(0x0) << 4)
12434 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING0_PG_SIZE_PG_8K \
12435 (UINT32_C(0x1) << 4)
12437 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING0_PG_SIZE_PG_64K \
12438 (UINT32_C(0x2) << 4)
12440 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING0_PG_SIZE_PG_2M \
12441 (UINT32_C(0x3) << 4)
12443 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING0_PG_SIZE_PG_8M \
12444 (UINT32_C(0x4) << 4)
12446 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING0_PG_SIZE_PG_1G \
12447 (UINT32_C(0x5) << 4)
12448 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING0_PG_SIZE_LAST \
12449 HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING0_PG_SIZE_PG_1G
12450 /* TQM ring 1 page size and level. */
12451 uint8_t tqm_ring1_pg_size_tqm_ring1_lvl;
12452 /* TQM ring 1 PBL indirect levels. */
12453 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING1_LVL_MASK \
12455 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING1_LVL_SFT 0
12456 /* PBL pointer is physical start address. */
12457 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING1_LVL_LVL_0 \
12459 /* PBL pointer points to PTE table. */
12460 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING1_LVL_LVL_1 \
12462 /* PBL pointer points to PDE table with each entry pointing to PTE tables. */
12463 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING1_LVL_LVL_2 \
12465 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING1_LVL_LAST \
12466 HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING1_LVL_LVL_2
12467 /* TQM ring 1 page size. */
12468 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING1_PG_SIZE_MASK \
12470 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING1_PG_SIZE_SFT 4
12472 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING1_PG_SIZE_PG_4K \
12473 (UINT32_C(0x0) << 4)
12475 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING1_PG_SIZE_PG_8K \
12476 (UINT32_C(0x1) << 4)
12478 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING1_PG_SIZE_PG_64K \
12479 (UINT32_C(0x2) << 4)
12481 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING1_PG_SIZE_PG_2M \
12482 (UINT32_C(0x3) << 4)
12484 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING1_PG_SIZE_PG_8M \
12485 (UINT32_C(0x4) << 4)
12487 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING1_PG_SIZE_PG_1G \
12488 (UINT32_C(0x5) << 4)
12489 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING1_PG_SIZE_LAST \
12490 HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING1_PG_SIZE_PG_1G
12491 /* TQM ring 2 page size and level. */
12492 uint8_t tqm_ring2_pg_size_tqm_ring2_lvl;
12493 /* TQM ring 2 PBL indirect levels. */
12494 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING2_LVL_MASK \
12496 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING2_LVL_SFT 0
12497 /* PBL pointer is physical start address. */
12498 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING2_LVL_LVL_0 \
12500 /* PBL pointer points to PTE table. */
12501 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING2_LVL_LVL_1 \
12503 /* PBL pointer points to PDE table with each entry pointing to PTE tables. */
12504 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING2_LVL_LVL_2 \
12506 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING2_LVL_LAST \
12507 HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING2_LVL_LVL_2
12508 /* TQM ring 2 page size. */
12509 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING2_PG_SIZE_MASK \
12511 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING2_PG_SIZE_SFT 4
12513 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING2_PG_SIZE_PG_4K \
12514 (UINT32_C(0x0) << 4)
12516 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING2_PG_SIZE_PG_8K \
12517 (UINT32_C(0x1) << 4)
12519 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING2_PG_SIZE_PG_64K \
12520 (UINT32_C(0x2) << 4)
12522 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING2_PG_SIZE_PG_2M \
12523 (UINT32_C(0x3) << 4)
12525 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING2_PG_SIZE_PG_8M \
12526 (UINT32_C(0x4) << 4)
12528 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING2_PG_SIZE_PG_1G \
12529 (UINT32_C(0x5) << 4)
12530 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING2_PG_SIZE_LAST \
12531 HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING2_PG_SIZE_PG_1G
12532 /* TQM ring 3 page size and level. */
12533 uint8_t tqm_ring3_pg_size_tqm_ring3_lvl;
12534 /* TQM ring 3 PBL indirect levels. */
12535 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING3_LVL_MASK \
12537 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING3_LVL_SFT 0
12538 /* PBL pointer is physical start address. */
12539 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING3_LVL_LVL_0 \
12541 /* PBL pointer points to PTE table. */
12542 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING3_LVL_LVL_1 \
12544 /* PBL pointer points to PDE table with each entry pointing to PTE tables. */
12545 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING3_LVL_LVL_2 \
12547 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING3_LVL_LAST \
12548 HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING3_LVL_LVL_2
12549 /* TQM ring 3 page size. */
12550 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING3_PG_SIZE_MASK \
12552 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING3_PG_SIZE_SFT 4
12554 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING3_PG_SIZE_PG_4K \
12555 (UINT32_C(0x0) << 4)
12557 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING3_PG_SIZE_PG_8K \
12558 (UINT32_C(0x1) << 4)
12560 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING3_PG_SIZE_PG_64K \
12561 (UINT32_C(0x2) << 4)
12563 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING3_PG_SIZE_PG_2M \
12564 (UINT32_C(0x3) << 4)
12566 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING3_PG_SIZE_PG_8M \
12567 (UINT32_C(0x4) << 4)
12569 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING3_PG_SIZE_PG_1G \
12570 (UINT32_C(0x5) << 4)
12571 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING3_PG_SIZE_LAST \
12572 HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING3_PG_SIZE_PG_1G
12573 /* TQM ring 4 page size and level. */
12574 uint8_t tqm_ring4_pg_size_tqm_ring4_lvl;
12575 /* TQM ring 4 PBL indirect levels. */
12576 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING4_LVL_MASK \
12578 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING4_LVL_SFT 0
12579 /* PBL pointer is physical start address. */
12580 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING4_LVL_LVL_0 \
12582 /* PBL pointer points to PTE table. */
12583 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING4_LVL_LVL_1 \
12585 /* PBL pointer points to PDE table with each entry pointing to PTE tables. */
12586 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING4_LVL_LVL_2 \
12588 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING4_LVL_LAST \
12589 HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING4_LVL_LVL_2
12590 /* TQM ring 4 page size. */
12591 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING4_PG_SIZE_MASK \
12593 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING4_PG_SIZE_SFT 4
12595 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING4_PG_SIZE_PG_4K \
12596 (UINT32_C(0x0) << 4)
12598 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING4_PG_SIZE_PG_8K \
12599 (UINT32_C(0x1) << 4)
12601 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING4_PG_SIZE_PG_64K \
12602 (UINT32_C(0x2) << 4)
12604 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING4_PG_SIZE_PG_2M \
12605 (UINT32_C(0x3) << 4)
12607 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING4_PG_SIZE_PG_8M \
12608 (UINT32_C(0x4) << 4)
12610 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING4_PG_SIZE_PG_1G \
12611 (UINT32_C(0x5) << 4)
12612 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING4_PG_SIZE_LAST \
12613 HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING4_PG_SIZE_PG_1G
12614 /* TQM ring 5 page size and level. */
12615 uint8_t tqm_ring5_pg_size_tqm_ring5_lvl;
12616 /* TQM ring 5 PBL indirect levels. */
12617 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING5_LVL_MASK \
12619 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING5_LVL_SFT 0
12620 /* PBL pointer is physical start address. */
12621 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING5_LVL_LVL_0 \
12623 /* PBL pointer points to PTE table. */
12624 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING5_LVL_LVL_1 \
12626 /* PBL pointer points to PDE table with each entry pointing to PTE tables. */
12627 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING5_LVL_LVL_2 \
12629 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING5_LVL_LAST \
12630 HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING5_LVL_LVL_2
12631 /* TQM ring 5 page size. */
12632 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING5_PG_SIZE_MASK \
12634 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING5_PG_SIZE_SFT 4
12636 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING5_PG_SIZE_PG_4K \
12637 (UINT32_C(0x0) << 4)
12639 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING5_PG_SIZE_PG_8K \
12640 (UINT32_C(0x1) << 4)
12642 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING5_PG_SIZE_PG_64K \
12643 (UINT32_C(0x2) << 4)
12645 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING5_PG_SIZE_PG_2M \
12646 (UINT32_C(0x3) << 4)
12648 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING5_PG_SIZE_PG_8M \
12649 (UINT32_C(0x4) << 4)
12651 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING5_PG_SIZE_PG_1G \
12652 (UINT32_C(0x5) << 4)
12653 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING5_PG_SIZE_LAST \
12654 HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING5_PG_SIZE_PG_1G
12655 /* TQM ring 6 page size and level. */
12656 uint8_t tqm_ring6_pg_size_tqm_ring6_lvl;
12657 /* TQM ring 6 PBL indirect levels. */
12658 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING6_LVL_MASK \
12660 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING6_LVL_SFT 0
12661 /* PBL pointer is physical start address. */
12662 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING6_LVL_LVL_0 \
12664 /* PBL pointer points to PTE table. */
12665 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING6_LVL_LVL_1 \
12667 /* PBL pointer points to PDE table with each entry pointing to PTE tables. */
12668 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING6_LVL_LVL_2 \
12670 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING6_LVL_LAST \
12671 HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING6_LVL_LVL_2
12672 /* TQM ring 6 page size. */
12673 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING6_PG_SIZE_MASK \
12675 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING6_PG_SIZE_SFT 4
12677 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING6_PG_SIZE_PG_4K \
12678 (UINT32_C(0x0) << 4)
12680 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING6_PG_SIZE_PG_8K \
12681 (UINT32_C(0x1) << 4)
12683 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING6_PG_SIZE_PG_64K \
12684 (UINT32_C(0x2) << 4)
12686 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING6_PG_SIZE_PG_2M \
12687 (UINT32_C(0x3) << 4)
12689 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING6_PG_SIZE_PG_8M \
12690 (UINT32_C(0x4) << 4)
12692 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING6_PG_SIZE_PG_1G \
12693 (UINT32_C(0x5) << 4)
12694 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING6_PG_SIZE_LAST \
12695 HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING6_PG_SIZE_PG_1G
12696 /* TQM ring 7 page size and level. */
12697 uint8_t tqm_ring7_pg_size_tqm_ring7_lvl;
12698 /* TQM ring 7 PBL indirect levels. */
12699 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING7_LVL_MASK \
12701 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING7_LVL_SFT 0
12702 /* PBL pointer is physical start address. */
12703 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING7_LVL_LVL_0 \
12705 /* PBL pointer points to PTE table. */
12706 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING7_LVL_LVL_1 \
12708 /* PBL pointer points to PDE table with each entry pointing to PTE tables. */
12709 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING7_LVL_LVL_2 \
12711 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING7_LVL_LAST \
12712 HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING7_LVL_LVL_2
12713 /* TQM ring 7 page size. */
12714 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING7_PG_SIZE_MASK \
12716 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING7_PG_SIZE_SFT 4
12718 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING7_PG_SIZE_PG_4K \
12719 (UINT32_C(0x0) << 4)
12721 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING7_PG_SIZE_PG_8K \
12722 (UINT32_C(0x1) << 4)
12724 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING7_PG_SIZE_PG_64K \
12725 (UINT32_C(0x2) << 4)
12727 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING7_PG_SIZE_PG_2M \
12728 (UINT32_C(0x3) << 4)
12730 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING7_PG_SIZE_PG_8M \
12731 (UINT32_C(0x4) << 4)
12733 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING7_PG_SIZE_PG_1G \
12734 (UINT32_C(0x5) << 4)
12735 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING7_PG_SIZE_LAST \
12736 HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING7_PG_SIZE_PG_1G
12737 /* MR/AV page size and level. */
12738 uint8_t mrav_pg_size_mrav_lvl;
12739 /* MR/AV PBL indirect levels. */
12740 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_MRAV_LVL_MASK \
12742 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_MRAV_LVL_SFT 0
12743 /* PBL pointer is physical start address. */
12744 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_MRAV_LVL_LVL_0 \
12746 /* PBL pointer points to PTE table. */
12747 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_MRAV_LVL_LVL_1 \
12749 /* PBL pointer points to PDE table with each entry pointing to PTE tables. */
12750 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_MRAV_LVL_LVL_2 \
12752 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_MRAV_LVL_LAST \
12753 HWRM_FUNC_BACKING_STORE_CFG_INPUT_MRAV_LVL_LVL_2
12754 /* MR/AV page size. */
12755 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_MRAV_PG_SIZE_MASK \
12757 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_MRAV_PG_SIZE_SFT 4
12759 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_MRAV_PG_SIZE_PG_4K \
12760 (UINT32_C(0x0) << 4)
12762 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_MRAV_PG_SIZE_PG_8K \
12763 (UINT32_C(0x1) << 4)
12765 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_MRAV_PG_SIZE_PG_64K \
12766 (UINT32_C(0x2) << 4)
12768 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_MRAV_PG_SIZE_PG_2M \
12769 (UINT32_C(0x3) << 4)
12771 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_MRAV_PG_SIZE_PG_8M \
12772 (UINT32_C(0x4) << 4)
12774 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_MRAV_PG_SIZE_PG_1G \
12775 (UINT32_C(0x5) << 4)
12776 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_MRAV_PG_SIZE_LAST \
12777 HWRM_FUNC_BACKING_STORE_CFG_INPUT_MRAV_PG_SIZE_PG_1G
12778 /* Timer page size and level. */
12779 uint8_t tim_pg_size_tim_lvl;
12780 /* Timer PBL indirect levels. */
12781 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TIM_LVL_MASK \
12783 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TIM_LVL_SFT 0
12784 /* PBL pointer is physical start address. */
12785 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TIM_LVL_LVL_0 \
12787 /* PBL pointer points to PTE table. */
12788 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TIM_LVL_LVL_1 \
12790 /* PBL pointer points to PDE table with each entry pointing to PTE tables. */
12791 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TIM_LVL_LVL_2 \
12793 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TIM_LVL_LAST \
12794 HWRM_FUNC_BACKING_STORE_CFG_INPUT_TIM_LVL_LVL_2
12795 /* Timer page size. */
12796 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TIM_PG_SIZE_MASK \
12798 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TIM_PG_SIZE_SFT 4
12800 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TIM_PG_SIZE_PG_4K \
12801 (UINT32_C(0x0) << 4)
12803 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TIM_PG_SIZE_PG_8K \
12804 (UINT32_C(0x1) << 4)
12806 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TIM_PG_SIZE_PG_64K \
12807 (UINT32_C(0x2) << 4)
12809 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TIM_PG_SIZE_PG_2M \
12810 (UINT32_C(0x3) << 4)
12812 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TIM_PG_SIZE_PG_8M \
12813 (UINT32_C(0x4) << 4)
12815 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TIM_PG_SIZE_PG_1G \
12816 (UINT32_C(0x5) << 4)
12817 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TIM_PG_SIZE_LAST \
12818 HWRM_FUNC_BACKING_STORE_CFG_INPUT_TIM_PG_SIZE_PG_1G
12819 /* QP page directory. */
12820 uint64_t qpc_page_dir;
12821 /* SRQ page directory. */
12822 uint64_t srq_page_dir;
12823 /* CQ page directory. */
12824 uint64_t cq_page_dir;
12825 /* VNIC page directory. */
12826 uint64_t vnic_page_dir;
12827 /* Stat page directory. */
12828 uint64_t stat_page_dir;
12829 /* TQM slowpath page directory. */
12830 uint64_t tqm_sp_page_dir;
12831 /* TQM ring 0 page directory. */
12832 uint64_t tqm_ring0_page_dir;
12833 /* TQM ring 1 page directory. */
12834 uint64_t tqm_ring1_page_dir;
12835 /* TQM ring 2 page directory. */
12836 uint64_t tqm_ring2_page_dir;
12837 /* TQM ring 3 page directory. */
12838 uint64_t tqm_ring3_page_dir;
12839 /* TQM ring 4 page directory. */
12840 uint64_t tqm_ring4_page_dir;
12841 /* TQM ring 5 page directory. */
12842 uint64_t tqm_ring5_page_dir;
12843 /* TQM ring 6 page directory. */
12844 uint64_t tqm_ring6_page_dir;
12845 /* TQM ring 7 page directory. */
12846 uint64_t tqm_ring7_page_dir;
12847 /* MR/AV page directory. */
12848 uint64_t mrav_page_dir;
12849 /* Timer page directory. */
12850 uint64_t tim_page_dir;
12851 /* Number of QPs. */
12852 uint32_t qp_num_entries;
12853 /* Number of SRQs. */
12854 uint32_t srq_num_entries;
12855 /* Number of CQs. */
12856 uint32_t cq_num_entries;
12857 /* Number of Stats. */
12858 uint32_t stat_num_entries;
12860 * Number of TQM slowpath entries.
12862 * TQM slowpath rings should be sized as follows:
12864 * num_entries = num_vnics + num_l2_tx_rings + 2 * num_roce_qps + tqm_min_size
12867 * num_vnics is the number of VNICs allocated in the VNIC backing store
12868 * num_l2_tx_rings is the number of L2 rings in the QP backing store
12869 * num_roce_qps is the number of RoCE QPs in the QP backing store
12870 * tqm_min_size is tqm_min_entries_per_ring reported by
12871 * HWRM_FUNC_BACKING_STORE_QCAPS
12873 * Note that TQM ring sizes cannot be extended while the system is
12874 * operational. If a PF driver needs to extend a TQM ring, it needs
12875 * to reset the function (e.g. HWRM_FUNC_RESET) and then reallocate
12876 * the backing store.
12878 uint32_t tqm_sp_num_entries;
12880 * Number of TQM ring 0 entries.
12882 * TQM fastpath rings should be sized large enough to accommodate the
12883 * maximum number of QPs (either L2 or RoCE, or both if shared)
12884 * that can be enqueued to the TQM ring.
12886 * Note that TQM ring sizes cannot be extended while the system is
12887 * operational. If a PF driver needs to extend a TQM ring, it needs
12888 * to reset the function (e.g. HWRM_FUNC_RESET) and then reallocate
12889 * the backing store.
12891 uint32_t tqm_ring0_num_entries;
12893 * Number of TQM ring 1 entries.
12895 * TQM fastpath rings should be sized large enough to accommodate the
12896 * maximum number of QPs (either L2 or RoCE, or both if shared)
12897 * that can be enqueued to the TQM ring.
12899 * Note that TQM ring sizes cannot be extended while the system is
12900 * operational. If a PF driver needs to extend a TQM ring, it needs
12901 * to reset the function (e.g. HWRM_FUNC_RESET) and then reallocate
12902 * the backing store.
12904 uint32_t tqm_ring1_num_entries;
12906 * Number of TQM ring 2 entries.
12908 * TQM fastpath rings should be sized large enough to accommodate the
12909 * maximum number of QPs (either L2 or RoCE, or both if shared)
12910 * that can be enqueued to the TQM ring.
12912 * Note that TQM ring sizes cannot be extended while the system is
12913 * operational. If a PF driver needs to extend a TQM ring, it needs
12914 * to reset the function (e.g. HWRM_FUNC_RESET) and then reallocate
12915 * the backing store.
12917 uint32_t tqm_ring2_num_entries;
12919 * Number of TQM ring 3 entries.
12921 * TQM fastpath rings should be sized large enough to accommodate the
12922 * maximum number of QPs (either L2 or RoCE, or both if shared)
12923 * that can be enqueued to the TQM ring.
12925 * Note that TQM ring sizes cannot be extended while the system is
12926 * operational. If a PF driver needs to extend a TQM ring, it needs
12927 * to reset the function (e.g. HWRM_FUNC_RESET) and then reallocate
12928 * the backing store.
12930 uint32_t tqm_ring3_num_entries;
12932 * Number of TQM ring 4 entries.
12934 * TQM fastpath rings should be sized large enough to accommodate the
12935 * maximum number of QPs (either L2 or RoCE, or both if shared)
12936 * that can be enqueued to the TQM ring.
12938 * Note that TQM ring sizes cannot be extended while the system is
12939 * operational. If a PF driver needs to extend a TQM ring, it needs
12940 * to reset the function (e.g. HWRM_FUNC_RESET) and then reallocate
12941 * the backing store.
12943 uint32_t tqm_ring4_num_entries;
12945 * Number of TQM ring 5 entries.
12947 * TQM fastpath rings should be sized large enough to accommodate the
12948 * maximum number of QPs (either L2 or RoCE, or both if shared)
12949 * that can be enqueued to the TQM ring.
12951 * Note that TQM ring sizes cannot be extended while the system is
12952 * operational. If a PF driver needs to extend a TQM ring, it needs
12953 * to reset the function (e.g. HWRM_FUNC_RESET) and then reallocate
12954 * the backing store.
12956 uint32_t tqm_ring5_num_entries;
12958 * Number of TQM ring 6 entries.
12960 * TQM fastpath rings should be sized large enough to accommodate the
12961 * maximum number of QPs (either L2 or RoCE, or both if shared)
12962 * that can be enqueued to the TQM ring.
12964 * Note that TQM ring sizes cannot be extended while the system is
12965 * operational. If a PF driver needs to extend a TQM ring, it needs
12966 * to reset the function (e.g. HWRM_FUNC_RESET) and then reallocate
12967 * the backing store.
12969 uint32_t tqm_ring6_num_entries;
12971 * Number of TQM ring 7 entries.
12973 * TQM fastpath rings should be sized large enough to accommodate the
12974 * maximum number of QPs (either L2 or RoCE, or both if shared)
12975 * that can be enqueued to the TQM ring.
12977 * Note that TQM ring sizes cannot be extended while the system is
12978 * operational. If a PF driver needs to extend a TQM ring, it needs
12979 * to reset the function (e.g. HWRM_FUNC_RESET) and then reallocate
12980 * the backing store.
12982 uint32_t tqm_ring7_num_entries;
12984 * If the MR/AV split reservation flag is not set, then this field
12985 * represents the total number of MR plus AV entries. For versions
12986 * of firmware that support the split reservation, when it is not
12987 * specified half of the entries will be reserved for MRs and the
12988 * other half for AVs.
12990 * If the MR/AV split reservation flag is set, then this
12991 * field is logically divided into two 16b fields. Bits `[31:16]`
12992 * represents the `mr_num_entries` and bits `[15:0]` represents
12993 * `av_num_entries`. The granularity of these values is defined by
12994 * the `mrav_num_entries_unit` field returned by the
12995 * `backing_store_qcaps` command.
12997 uint32_t mrav_num_entries;
12998 /* Number of Timer entries. */
12999 uint32_t tim_num_entries;
13000 /* Number of entries to reserve for QP1 */
13001 uint16_t qp_num_qp1_entries;
13002 /* Number of entries to reserve for L2 */
13003 uint16_t qp_num_l2_entries;
13004 /* Number of bytes that have been allocated for each context entry. */
13005 uint16_t qp_entry_size;
13006 /* Number of entries to reserve for L2 */
13007 uint16_t srq_num_l2_entries;
13008 /* Number of bytes that have been allocated for each context entry. */
13009 uint16_t srq_entry_size;
13010 /* Number of entries to reserve for L2 */
13011 uint16_t cq_num_l2_entries;
13012 /* Number of bytes that have been allocated for each context entry. */
13013 uint16_t cq_entry_size;
13014 /* Number of entries to reserve for VNIC entries */
13015 uint16_t vnic_num_vnic_entries;
13016 /* Number of entries to reserve for Ring table entries */
13017 uint16_t vnic_num_ring_table_entries;
13018 /* Number of bytes that have been allocated for each context entry. */
13019 uint16_t vnic_entry_size;
13020 /* Number of bytes that have been allocated for each context entry. */
13021 uint16_t stat_entry_size;
13022 /* Number of bytes that have been allocated for each context entry. */
13023 uint16_t tqm_entry_size;
13024 /* Number of bytes that have been allocated for each context entry. */
13025 uint16_t mrav_entry_size;
13026 /* Number of bytes that have been allocated for each context entry. */
13027 uint16_t tim_entry_size;
13030 /* hwrm_func_backing_store_cfg_output (size:128b/16B) */
13031 struct hwrm_func_backing_store_cfg_output {
13032 /* The specific error status for the command. */
13033 uint16_t error_code;
13034 /* The HWRM command request type. */
13036 /* The sequence ID from the original command. */
13038 /* The length of the response data in number of bytes. */
13040 uint8_t unused_0[7];
13042 * This field is used in Output records to indicate that the output
13043 * is completely written to RAM. This field should be read as '1'
13044 * to indicate that the output has been completely written.
13045 * When writing a command completion or response to an internal processor,
13046 * the order of writes has to be such that this field is written last.
13051 /********************************
13052 * hwrm_func_backing_store_qcfg *
13053 ********************************/
13056 /* hwrm_func_backing_store_qcfg_input (size:128b/16B) */
13057 struct hwrm_func_backing_store_qcfg_input {
13058 /* The HWRM command request type. */
13061 * The completion ring to send the completion event on. This should
13062 * be the NQ ID returned from the `nq_alloc` HWRM command.
13064 uint16_t cmpl_ring;
13066 * The sequence ID is used by the driver for tracking multiple
13067 * commands. This ID is treated as opaque data by the firmware and
13068 * the value is returned in the `hwrm_resp_hdr` upon completion.
13072 * The target ID of the command:
13073 * * 0x0-0xFFF8 - The function ID
13074 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
13075 * * 0xFFFD - Reserved for user-space HWRM interface
13078 uint16_t target_id;
13080 * A physical address pointer pointing to a host buffer that the
13081 * command's response data will be written. This can be either a host
13082 * physical address (HPA) or a guest physical address (GPA) and must
13083 * point to a physically contiguous block of memory.
13085 uint64_t resp_addr;
13088 /* hwrm_func_backing_store_qcfg_output (size:1920b/240B) */
13089 struct hwrm_func_backing_store_qcfg_output {
13090 /* The specific error status for the command. */
13091 uint16_t error_code;
13092 /* The HWRM command request type. */
13094 /* The sequence ID from the original command. */
13096 /* The length of the response data in number of bytes. */
13100 * When set, the firmware only uses on-chip resources and does not
13101 * expect any backing store to be provided by the host driver. This
13102 * mode provides minimal L2 functionality (e.g. limited L2 resources,
13105 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_FLAGS_PREBOOT_MODE \
13108 * When set, the 32b `mrav_num_entries` field is logically divided
13109 * into two 16b fields, `mr_num_entries` and `av_num_entries`.
13111 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_FLAGS_MRAV_RESERVATION_SPLIT \
13113 uint8_t unused_0[4];
13115 * This bit must be '1' for the qp fields to be
13118 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_UNUSED_0_QP \
13121 * This bit must be '1' for the srq fields to be
13124 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_UNUSED_0_SRQ \
13127 * This bit must be '1' for the cq fields to be
13130 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_UNUSED_0_CQ \
13133 * This bit must be '1' for the vnic fields to be
13136 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_UNUSED_0_VNIC \
13139 * This bit must be '1' for the stat fields to be
13142 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_UNUSED_0_STAT \
13145 * This bit must be '1' for the tqm_sp fields to be
13148 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_UNUSED_0_TQM_SP \
13151 * This bit must be '1' for the tqm_ring0 fields to be
13154 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_UNUSED_0_TQM_RING0 \
13157 * This bit must be '1' for the tqm_ring1 fields to be
13160 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_UNUSED_0_TQM_RING1 \
13163 * This bit must be '1' for the tqm_ring2 fields to be
13166 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_UNUSED_0_TQM_RING2 \
13169 * This bit must be '1' for the tqm_ring3 fields to be
13172 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_UNUSED_0_TQM_RING3 \
13175 * This bit must be '1' for the tqm_ring4 fields to be
13178 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_UNUSED_0_TQM_RING4 \
13181 * This bit must be '1' for the tqm_ring5 fields to be
13184 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_UNUSED_0_TQM_RING5 \
13187 * This bit must be '1' for the tqm_ring6 fields to be
13190 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_UNUSED_0_TQM_RING6 \
13193 * This bit must be '1' for the tqm_ring7 fields to be
13196 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_UNUSED_0_TQM_RING7 \
13199 * This bit must be '1' for the mrav fields to be
13202 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_UNUSED_0_MRAV \
13205 * This bit must be '1' for the tim fields to be
13208 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_UNUSED_0_TIM \
13210 /* QPC page size and level. */
13211 uint8_t qpc_pg_size_qpc_lvl;
13212 /* QPC PBL indirect levels. */
13213 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_QPC_LVL_MASK \
13215 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_QPC_LVL_SFT 0
13216 /* PBL pointer is physical start address. */
13217 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_QPC_LVL_LVL_0 \
13219 /* PBL pointer points to PTE table. */
13220 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_QPC_LVL_LVL_1 \
13222 /* PBL pointer points to PDE table with each entry pointing to PTE tables. */
13223 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_QPC_LVL_LVL_2 \
13225 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_QPC_LVL_LAST \
13226 HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_QPC_LVL_LVL_2
13227 /* QPC page size. */
13228 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_QPC_PG_SIZE_MASK \
13230 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_QPC_PG_SIZE_SFT 4
13232 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_QPC_PG_SIZE_PG_4K \
13233 (UINT32_C(0x0) << 4)
13235 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_QPC_PG_SIZE_PG_8K \
13236 (UINT32_C(0x1) << 4)
13238 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_QPC_PG_SIZE_PG_64K \
13239 (UINT32_C(0x2) << 4)
13241 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_QPC_PG_SIZE_PG_2M \
13242 (UINT32_C(0x3) << 4)
13244 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_QPC_PG_SIZE_PG_8M \
13245 (UINT32_C(0x4) << 4)
13247 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_QPC_PG_SIZE_PG_1G \
13248 (UINT32_C(0x5) << 4)
13249 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_QPC_PG_SIZE_LAST \
13250 HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_QPC_PG_SIZE_PG_1G
13251 /* SRQ page size and level. */
13252 uint8_t srq_pg_size_srq_lvl;
13253 /* SRQ PBL indirect levels. */
13254 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_SRQ_LVL_MASK \
13256 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_SRQ_LVL_SFT 0
13257 /* PBL pointer is physical start address. */
13258 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_SRQ_LVL_LVL_0 \
13260 /* PBL pointer points to PTE table. */
13261 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_SRQ_LVL_LVL_1 \
13263 /* PBL pointer points to PDE table with each entry pointing to PTE tables. */
13264 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_SRQ_LVL_LVL_2 \
13266 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_SRQ_LVL_LAST \
13267 HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_SRQ_LVL_LVL_2
13268 /* SRQ page size. */
13269 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_SRQ_PG_SIZE_MASK \
13271 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_SRQ_PG_SIZE_SFT 4
13273 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_SRQ_PG_SIZE_PG_4K \
13274 (UINT32_C(0x0) << 4)
13276 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_SRQ_PG_SIZE_PG_8K \
13277 (UINT32_C(0x1) << 4)
13279 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_SRQ_PG_SIZE_PG_64K \
13280 (UINT32_C(0x2) << 4)
13282 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_SRQ_PG_SIZE_PG_2M \
13283 (UINT32_C(0x3) << 4)
13285 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_SRQ_PG_SIZE_PG_8M \
13286 (UINT32_C(0x4) << 4)
13288 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_SRQ_PG_SIZE_PG_1G \
13289 (UINT32_C(0x5) << 4)
13290 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_SRQ_PG_SIZE_LAST \
13291 HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_SRQ_PG_SIZE_PG_1G
13292 /* CQ page size and level. */
13293 uint8_t cq_pg_size_cq_lvl;
13294 /* CQ PBL indirect levels. */
13295 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_CQ_LVL_MASK \
13297 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_CQ_LVL_SFT 0
13298 /* PBL pointer is physical start address. */
13299 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_CQ_LVL_LVL_0 \
13301 /* PBL pointer points to PTE table. */
13302 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_CQ_LVL_LVL_1 \
13304 /* PBL pointer points to PDE table with each entry pointing to PTE tables. */
13305 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_CQ_LVL_LVL_2 \
13307 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_CQ_LVL_LAST \
13308 HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_CQ_LVL_LVL_2
13309 /* CQ page size. */
13310 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_CQ_PG_SIZE_MASK \
13312 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_CQ_PG_SIZE_SFT 4
13314 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_CQ_PG_SIZE_PG_4K \
13315 (UINT32_C(0x0) << 4)
13317 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_CQ_PG_SIZE_PG_8K \
13318 (UINT32_C(0x1) << 4)
13320 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_CQ_PG_SIZE_PG_64K \
13321 (UINT32_C(0x2) << 4)
13323 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_CQ_PG_SIZE_PG_2M \
13324 (UINT32_C(0x3) << 4)
13326 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_CQ_PG_SIZE_PG_8M \
13327 (UINT32_C(0x4) << 4)
13329 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_CQ_PG_SIZE_PG_1G \
13330 (UINT32_C(0x5) << 4)
13331 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_CQ_PG_SIZE_LAST \
13332 HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_CQ_PG_SIZE_PG_1G
13333 /* VNIC page size and level. */
13334 uint8_t vnic_pg_size_vnic_lvl;
13335 /* VNIC PBL indirect levels. */
13336 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_VNIC_LVL_MASK \
13338 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_VNIC_LVL_SFT 0
13339 /* PBL pointer is physical start address. */
13340 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_VNIC_LVL_LVL_0 \
13342 /* PBL pointer points to PTE table. */
13343 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_VNIC_LVL_LVL_1 \
13345 /* PBL pointer points to PDE table with each entry pointing to PTE tables. */
13346 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_VNIC_LVL_LVL_2 \
13348 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_VNIC_LVL_LAST \
13349 HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_VNIC_LVL_LVL_2
13350 /* VNIC page size. */
13351 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_VNIC_PG_SIZE_MASK \
13353 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_VNIC_PG_SIZE_SFT 4
13355 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_VNIC_PG_SIZE_PG_4K \
13356 (UINT32_C(0x0) << 4)
13358 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_VNIC_PG_SIZE_PG_8K \
13359 (UINT32_C(0x1) << 4)
13361 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_VNIC_PG_SIZE_PG_64K \
13362 (UINT32_C(0x2) << 4)
13364 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_VNIC_PG_SIZE_PG_2M \
13365 (UINT32_C(0x3) << 4)
13367 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_VNIC_PG_SIZE_PG_8M \
13368 (UINT32_C(0x4) << 4)
13370 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_VNIC_PG_SIZE_PG_1G \
13371 (UINT32_C(0x5) << 4)
13372 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_VNIC_PG_SIZE_LAST \
13373 HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_VNIC_PG_SIZE_PG_1G
13374 /* Stat page size and level. */
13375 uint8_t stat_pg_size_stat_lvl;
13376 /* Stat PBL indirect levels. */
13377 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_STAT_LVL_MASK \
13379 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_STAT_LVL_SFT 0
13380 /* PBL pointer is physical start address. */
13381 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_STAT_LVL_LVL_0 \
13383 /* PBL pointer points to PTE table. */
13384 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_STAT_LVL_LVL_1 \
13386 /* PBL pointer points to PDE table with each entry pointing to PTE tables. */
13387 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_STAT_LVL_LVL_2 \
13389 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_STAT_LVL_LAST \
13390 HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_STAT_LVL_LVL_2
13391 /* Stat page size. */
13392 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_STAT_PG_SIZE_MASK \
13394 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_STAT_PG_SIZE_SFT 4
13396 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_STAT_PG_SIZE_PG_4K \
13397 (UINT32_C(0x0) << 4)
13399 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_STAT_PG_SIZE_PG_8K \
13400 (UINT32_C(0x1) << 4)
13402 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_STAT_PG_SIZE_PG_64K \
13403 (UINT32_C(0x2) << 4)
13405 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_STAT_PG_SIZE_PG_2M \
13406 (UINT32_C(0x3) << 4)
13408 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_STAT_PG_SIZE_PG_8M \
13409 (UINT32_C(0x4) << 4)
13411 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_STAT_PG_SIZE_PG_1G \
13412 (UINT32_C(0x5) << 4)
13413 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_STAT_PG_SIZE_LAST \
13414 HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_STAT_PG_SIZE_PG_1G
13415 /* TQM slow path page size and level. */
13416 uint8_t tqm_sp_pg_size_tqm_sp_lvl;
13417 /* TQM slow path PBL indirect levels. */
13418 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_SP_LVL_MASK \
13420 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_SP_LVL_SFT 0
13421 /* PBL pointer is physical start address. */
13422 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_SP_LVL_LVL_0 \
13424 /* PBL pointer points to PTE table. */
13425 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_SP_LVL_LVL_1 \
13427 /* PBL pointer points to PDE table with each entry pointing to PTE tables. */
13428 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_SP_LVL_LVL_2 \
13430 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_SP_LVL_LAST \
13431 HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_SP_LVL_LVL_2
13432 /* TQM slow path page size. */
13433 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_SP_PG_SIZE_MASK \
13435 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_SP_PG_SIZE_SFT 4
13437 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_SP_PG_SIZE_PG_4K \
13438 (UINT32_C(0x0) << 4)
13440 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_SP_PG_SIZE_PG_8K \
13441 (UINT32_C(0x1) << 4)
13443 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_SP_PG_SIZE_PG_64K \
13444 (UINT32_C(0x2) << 4)
13446 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_SP_PG_SIZE_PG_2M \
13447 (UINT32_C(0x3) << 4)
13449 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_SP_PG_SIZE_PG_8M \
13450 (UINT32_C(0x4) << 4)
13452 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_SP_PG_SIZE_PG_1G \
13453 (UINT32_C(0x5) << 4)
13454 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_SP_PG_SIZE_LAST \
13455 HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_SP_PG_SIZE_PG_1G
13456 /* TQM ring 0 page size and level. */
13457 uint8_t tqm_ring0_pg_size_tqm_ring0_lvl;
13458 /* TQM ring 0 PBL indirect levels. */
13459 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING0_LVL_MASK \
13461 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING0_LVL_SFT 0
13462 /* PBL pointer is physical start address. */
13463 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING0_LVL_LVL_0 \
13465 /* PBL pointer points to PTE table. */
13466 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING0_LVL_LVL_1 \
13468 /* PBL pointer points to PDE table with each entry pointing to PTE tables. */
13469 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING0_LVL_LVL_2 \
13471 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING0_LVL_LAST \
13472 HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING0_LVL_LVL_2
13473 /* TQM ring 0 page size. */
13474 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING0_PG_SIZE_MASK \
13476 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING0_PG_SIZE_SFT 4
13478 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING0_PG_SIZE_PG_4K \
13479 (UINT32_C(0x0) << 4)
13481 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING0_PG_SIZE_PG_8K \
13482 (UINT32_C(0x1) << 4)
13484 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING0_PG_SIZE_PG_64K \
13485 (UINT32_C(0x2) << 4)
13487 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING0_PG_SIZE_PG_2M \
13488 (UINT32_C(0x3) << 4)
13490 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING0_PG_SIZE_PG_8M \
13491 (UINT32_C(0x4) << 4)
13493 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING0_PG_SIZE_PG_1G \
13494 (UINT32_C(0x5) << 4)
13495 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING0_PG_SIZE_LAST \
13496 HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING0_PG_SIZE_PG_1G
13497 /* TQM ring 1 page size and level. */
13498 uint8_t tqm_ring1_pg_size_tqm_ring1_lvl;
13499 /* TQM ring 1 PBL indirect levels. */
13500 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING1_LVL_MASK \
13502 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING1_LVL_SFT 0
13503 /* PBL pointer is physical start address. */
13504 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING1_LVL_LVL_0 \
13506 /* PBL pointer points to PTE table. */
13507 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING1_LVL_LVL_1 \
13509 /* PBL pointer points to PDE table with each entry pointing to PTE tables. */
13510 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING1_LVL_LVL_2 \
13512 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING1_LVL_LAST \
13513 HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING1_LVL_LVL_2
13514 /* TQM ring 1 page size. */
13515 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING1_PG_SIZE_MASK \
13517 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING1_PG_SIZE_SFT 4
13519 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING1_PG_SIZE_PG_4K \
13520 (UINT32_C(0x0) << 4)
13522 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING1_PG_SIZE_PG_8K \
13523 (UINT32_C(0x1) << 4)
13525 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING1_PG_SIZE_PG_64K \
13526 (UINT32_C(0x2) << 4)
13528 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING1_PG_SIZE_PG_2M \
13529 (UINT32_C(0x3) << 4)
13531 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING1_PG_SIZE_PG_8M \
13532 (UINT32_C(0x4) << 4)
13534 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING1_PG_SIZE_PG_1G \
13535 (UINT32_C(0x5) << 4)
13536 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING1_PG_SIZE_LAST \
13537 HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING1_PG_SIZE_PG_1G
13538 /* TQM ring 2 page size and level. */
13539 uint8_t tqm_ring2_pg_size_tqm_ring2_lvl;
13540 /* TQM ring 2 PBL indirect levels. */
13541 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING2_LVL_MASK \
13543 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING2_LVL_SFT 0
13544 /* PBL pointer is physical start address. */
13545 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING2_LVL_LVL_0 \
13547 /* PBL pointer points to PTE table. */
13548 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING2_LVL_LVL_1 \
13550 /* PBL pointer points to PDE table with each entry pointing to PTE tables. */
13551 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING2_LVL_LVL_2 \
13553 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING2_LVL_LAST \
13554 HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING2_LVL_LVL_2
13555 /* TQM ring 2 page size. */
13556 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING2_PG_SIZE_MASK \
13558 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING2_PG_SIZE_SFT 4
13560 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING2_PG_SIZE_PG_4K \
13561 (UINT32_C(0x0) << 4)
13563 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING2_PG_SIZE_PG_8K \
13564 (UINT32_C(0x1) << 4)
13566 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING2_PG_SIZE_PG_64K \
13567 (UINT32_C(0x2) << 4)
13569 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING2_PG_SIZE_PG_2M \
13570 (UINT32_C(0x3) << 4)
13572 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING2_PG_SIZE_PG_8M \
13573 (UINT32_C(0x4) << 4)
13575 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING2_PG_SIZE_PG_1G \
13576 (UINT32_C(0x5) << 4)
13577 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING2_PG_SIZE_LAST \
13578 HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING2_PG_SIZE_PG_1G
13579 /* TQM ring 3 page size and level. */
13580 uint8_t tqm_ring3_pg_size_tqm_ring3_lvl;
13581 /* TQM ring 3 PBL indirect levels. */
13582 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING3_LVL_MASK \
13584 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING3_LVL_SFT 0
13585 /* PBL pointer is physical start address. */
13586 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING3_LVL_LVL_0 \
13588 /* PBL pointer points to PTE table. */
13589 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING3_LVL_LVL_1 \
13591 /* PBL pointer points to PDE table with each entry pointing to PTE tables. */
13592 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING3_LVL_LVL_2 \
13594 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING3_LVL_LAST \
13595 HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING3_LVL_LVL_2
13596 /* TQM ring 3 page size. */
13597 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING3_PG_SIZE_MASK \
13599 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING3_PG_SIZE_SFT 4
13601 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING3_PG_SIZE_PG_4K \
13602 (UINT32_C(0x0) << 4)
13604 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING3_PG_SIZE_PG_8K \
13605 (UINT32_C(0x1) << 4)
13607 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING3_PG_SIZE_PG_64K \
13608 (UINT32_C(0x2) << 4)
13610 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING3_PG_SIZE_PG_2M \
13611 (UINT32_C(0x3) << 4)
13613 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING3_PG_SIZE_PG_8M \
13614 (UINT32_C(0x4) << 4)
13616 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING3_PG_SIZE_PG_1G \
13617 (UINT32_C(0x5) << 4)
13618 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING3_PG_SIZE_LAST \
13619 HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING3_PG_SIZE_PG_1G
13620 /* TQM ring 4 page size and level. */
13621 uint8_t tqm_ring4_pg_size_tqm_ring4_lvl;
13622 /* TQM ring 4 PBL indirect levels. */
13623 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING4_LVL_MASK \
13625 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING4_LVL_SFT 0
13626 /* PBL pointer is physical start address. */
13627 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING4_LVL_LVL_0 \
13629 /* PBL pointer points to PTE table. */
13630 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING4_LVL_LVL_1 \
13632 /* PBL pointer points to PDE table with each entry pointing to PTE tables. */
13633 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING4_LVL_LVL_2 \
13635 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING4_LVL_LAST \
13636 HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING4_LVL_LVL_2
13637 /* TQM ring 4 page size. */
13638 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING4_PG_SIZE_MASK \
13640 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING4_PG_SIZE_SFT 4
13642 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING4_PG_SIZE_PG_4K \
13643 (UINT32_C(0x0) << 4)
13645 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING4_PG_SIZE_PG_8K \
13646 (UINT32_C(0x1) << 4)
13648 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING4_PG_SIZE_PG_64K \
13649 (UINT32_C(0x2) << 4)
13651 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING4_PG_SIZE_PG_2M \
13652 (UINT32_C(0x3) << 4)
13654 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING4_PG_SIZE_PG_8M \
13655 (UINT32_C(0x4) << 4)
13657 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING4_PG_SIZE_PG_1G \
13658 (UINT32_C(0x5) << 4)
13659 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING4_PG_SIZE_LAST \
13660 HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING4_PG_SIZE_PG_1G
13661 /* TQM ring 5 page size and level. */
13662 uint8_t tqm_ring5_pg_size_tqm_ring5_lvl;
13663 /* TQM ring 5 PBL indirect levels. */
13664 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING5_LVL_MASK \
13666 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING5_LVL_SFT 0
13667 /* PBL pointer is physical start address. */
13668 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING5_LVL_LVL_0 \
13670 /* PBL pointer points to PTE table. */
13671 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING5_LVL_LVL_1 \
13673 /* PBL pointer points to PDE table with each entry pointing to PTE tables. */
13674 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING5_LVL_LVL_2 \
13676 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING5_LVL_LAST \
13677 HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING5_LVL_LVL_2
13678 /* TQM ring 5 page size. */
13679 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING5_PG_SIZE_MASK \
13681 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING5_PG_SIZE_SFT 4
13683 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING5_PG_SIZE_PG_4K \
13684 (UINT32_C(0x0) << 4)
13686 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING5_PG_SIZE_PG_8K \
13687 (UINT32_C(0x1) << 4)
13689 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING5_PG_SIZE_PG_64K \
13690 (UINT32_C(0x2) << 4)
13692 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING5_PG_SIZE_PG_2M \
13693 (UINT32_C(0x3) << 4)
13695 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING5_PG_SIZE_PG_8M \
13696 (UINT32_C(0x4) << 4)
13698 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING5_PG_SIZE_PG_1G \
13699 (UINT32_C(0x5) << 4)
13700 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING5_PG_SIZE_LAST \
13701 HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING5_PG_SIZE_PG_1G
13702 /* TQM ring 6 page size and level. */
13703 uint8_t tqm_ring6_pg_size_tqm_ring6_lvl;
13704 /* TQM ring 6 PBL indirect levels. */
13705 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING6_LVL_MASK \
13707 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING6_LVL_SFT 0
13708 /* PBL pointer is physical start address. */
13709 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING6_LVL_LVL_0 \
13711 /* PBL pointer points to PTE table. */
13712 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING6_LVL_LVL_1 \
13714 /* PBL pointer points to PDE table with each entry pointing to PTE tables. */
13715 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING6_LVL_LVL_2 \
13717 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING6_LVL_LAST \
13718 HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING6_LVL_LVL_2
13719 /* TQM ring 6 page size. */
13720 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING6_PG_SIZE_MASK \
13722 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING6_PG_SIZE_SFT 4
13724 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING6_PG_SIZE_PG_4K \
13725 (UINT32_C(0x0) << 4)
13727 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING6_PG_SIZE_PG_8K \
13728 (UINT32_C(0x1) << 4)
13730 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING6_PG_SIZE_PG_64K \
13731 (UINT32_C(0x2) << 4)
13733 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING6_PG_SIZE_PG_2M \
13734 (UINT32_C(0x3) << 4)
13736 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING6_PG_SIZE_PG_8M \
13737 (UINT32_C(0x4) << 4)
13739 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING6_PG_SIZE_PG_1G \
13740 (UINT32_C(0x5) << 4)
13741 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING6_PG_SIZE_LAST \
13742 HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING6_PG_SIZE_PG_1G
13743 /* TQM ring 7 page size and level. */
13744 uint8_t tqm_ring7_pg_size_tqm_ring7_lvl;
13745 /* TQM ring 7 PBL indirect levels. */
13746 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING7_LVL_MASK \
13748 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING7_LVL_SFT 0
13749 /* PBL pointer is physical start address. */
13750 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING7_LVL_LVL_0 \
13752 /* PBL pointer points to PTE table. */
13753 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING7_LVL_LVL_1 \
13755 /* PBL pointer points to PDE table with each entry pointing to PTE tables. */
13756 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING7_LVL_LVL_2 \
13758 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING7_LVL_LAST \
13759 HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING7_LVL_LVL_2
13760 /* TQM ring 7 page size. */
13761 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING7_PG_SIZE_MASK \
13763 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING7_PG_SIZE_SFT 4
13765 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING7_PG_SIZE_PG_4K \
13766 (UINT32_C(0x0) << 4)
13768 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING7_PG_SIZE_PG_8K \
13769 (UINT32_C(0x1) << 4)
13771 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING7_PG_SIZE_PG_64K \
13772 (UINT32_C(0x2) << 4)
13774 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING7_PG_SIZE_PG_2M \
13775 (UINT32_C(0x3) << 4)
13777 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING7_PG_SIZE_PG_8M \
13778 (UINT32_C(0x4) << 4)
13780 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING7_PG_SIZE_PG_1G \
13781 (UINT32_C(0x5) << 4)
13782 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING7_PG_SIZE_LAST \
13783 HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING7_PG_SIZE_PG_1G
13784 /* MR/AV page size and level. */
13785 uint8_t mrav_pg_size_mrav_lvl;
13786 /* MR/AV PBL indirect levels. */
13787 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_MRAV_LVL_MASK \
13789 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_MRAV_LVL_SFT 0
13790 /* PBL pointer is physical start address. */
13791 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_MRAV_LVL_LVL_0 \
13793 /* PBL pointer points to PTE table. */
13794 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_MRAV_LVL_LVL_1 \
13796 /* PBL pointer points to PDE table with each entry pointing to PTE tables. */
13797 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_MRAV_LVL_LVL_2 \
13799 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_MRAV_LVL_LAST \
13800 HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_MRAV_LVL_LVL_2
13801 /* MR/AV page size. */
13802 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_MRAV_PG_SIZE_MASK \
13804 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_MRAV_PG_SIZE_SFT 4
13806 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_MRAV_PG_SIZE_PG_4K \
13807 (UINT32_C(0x0) << 4)
13809 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_MRAV_PG_SIZE_PG_8K \
13810 (UINT32_C(0x1) << 4)
13812 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_MRAV_PG_SIZE_PG_64K \
13813 (UINT32_C(0x2) << 4)
13815 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_MRAV_PG_SIZE_PG_2M \
13816 (UINT32_C(0x3) << 4)
13818 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_MRAV_PG_SIZE_PG_8M \
13819 (UINT32_C(0x4) << 4)
13821 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_MRAV_PG_SIZE_PG_1G \
13822 (UINT32_C(0x5) << 4)
13823 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_MRAV_PG_SIZE_LAST \
13824 HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_MRAV_PG_SIZE_PG_1G
13825 /* Timer page size and level. */
13826 uint8_t tim_pg_size_tim_lvl;
13827 /* Timer PBL indirect levels. */
13828 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TIM_LVL_MASK \
13830 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TIM_LVL_SFT 0
13831 /* PBL pointer is physical start address. */
13832 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TIM_LVL_LVL_0 \
13834 /* PBL pointer points to PTE table. */
13835 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TIM_LVL_LVL_1 \
13837 /* PBL pointer points to PDE table with each entry pointing to PTE tables. */
13838 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TIM_LVL_LVL_2 \
13840 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TIM_LVL_LAST \
13841 HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TIM_LVL_LVL_2
13842 /* Timer page size. */
13843 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TIM_PG_SIZE_MASK \
13845 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TIM_PG_SIZE_SFT 4
13847 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TIM_PG_SIZE_PG_4K \
13848 (UINT32_C(0x0) << 4)
13850 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TIM_PG_SIZE_PG_8K \
13851 (UINT32_C(0x1) << 4)
13853 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TIM_PG_SIZE_PG_64K \
13854 (UINT32_C(0x2) << 4)
13856 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TIM_PG_SIZE_PG_2M \
13857 (UINT32_C(0x3) << 4)
13859 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TIM_PG_SIZE_PG_8M \
13860 (UINT32_C(0x4) << 4)
13862 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TIM_PG_SIZE_PG_1G \
13863 (UINT32_C(0x5) << 4)
13864 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TIM_PG_SIZE_LAST \
13865 HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TIM_PG_SIZE_PG_1G
13866 /* QP page directory. */
13867 uint64_t qpc_page_dir;
13868 /* SRQ page directory. */
13869 uint64_t srq_page_dir;
13870 /* CQ page directory. */
13871 uint64_t cq_page_dir;
13872 /* VNIC page directory. */
13873 uint64_t vnic_page_dir;
13874 /* Stat page directory. */
13875 uint64_t stat_page_dir;
13876 /* TQM slowpath page directory. */
13877 uint64_t tqm_sp_page_dir;
13878 /* TQM ring 0 page directory. */
13879 uint64_t tqm_ring0_page_dir;
13880 /* TQM ring 1 page directory. */
13881 uint64_t tqm_ring1_page_dir;
13882 /* TQM ring 2 page directory. */
13883 uint64_t tqm_ring2_page_dir;
13884 /* TQM ring 3 page directory. */
13885 uint64_t tqm_ring3_page_dir;
13886 /* TQM ring 4 page directory. */
13887 uint64_t tqm_ring4_page_dir;
13888 /* TQM ring 5 page directory. */
13889 uint64_t tqm_ring5_page_dir;
13890 /* TQM ring 6 page directory. */
13891 uint64_t tqm_ring6_page_dir;
13892 /* TQM ring 7 page directory. */
13893 uint64_t tqm_ring7_page_dir;
13894 /* MR/AV page directory. */
13895 uint64_t mrav_page_dir;
13896 /* Timer page directory. */
13897 uint64_t tim_page_dir;
13898 /* Number of entries to reserve for QP1 */
13899 uint16_t qp_num_qp1_entries;
13900 /* Number of entries to reserve for L2 */
13901 uint16_t qp_num_l2_entries;
13902 /* Number of QPs. */
13903 uint32_t qp_num_entries;
13904 /* Number of SRQs. */
13905 uint32_t srq_num_entries;
13906 /* Number of entries to reserve for L2 */
13907 uint16_t srq_num_l2_entries;
13908 /* Number of entries to reserve for L2 */
13909 uint16_t cq_num_l2_entries;
13910 /* Number of CQs. */
13911 uint32_t cq_num_entries;
13912 /* Number of entries to reserve for VNIC entries */
13913 uint16_t vnic_num_vnic_entries;
13914 /* Number of entries to reserve for Ring table entries */
13915 uint16_t vnic_num_ring_table_entries;
13916 /* Number of Stats. */
13917 uint32_t stat_num_entries;
13918 /* Number of TQM slowpath entries. */
13919 uint32_t tqm_sp_num_entries;
13920 /* Number of TQM ring 0 entries. */
13921 uint32_t tqm_ring0_num_entries;
13922 /* Number of TQM ring 1 entries. */
13923 uint32_t tqm_ring1_num_entries;
13924 /* Number of TQM ring 2 entries. */
13925 uint32_t tqm_ring2_num_entries;
13926 /* Number of TQM ring 3 entries. */
13927 uint32_t tqm_ring3_num_entries;
13928 /* Number of TQM ring 4 entries. */
13929 uint32_t tqm_ring4_num_entries;
13930 /* Number of TQM ring 5 entries. */
13931 uint32_t tqm_ring5_num_entries;
13932 /* Number of TQM ring 6 entries. */
13933 uint32_t tqm_ring6_num_entries;
13934 /* Number of TQM ring 7 entries. */
13935 uint32_t tqm_ring7_num_entries;
13937 * If the MR/AV split reservation flag is not set, then this field
13938 * represents the total number of MR plus AV entries. For versions
13939 * of firmware that support the split reservation, when it is not
13940 * specified half of the entries will be reserved for MRs and the
13941 * other half for AVs.
13943 * If the MR/AV split reservation flag is set, then this
13944 * field is logically divided into two 16b fields. Bits `[31:16]`
13945 * represents the `mr_num_entries` and bits `[15:0]` represents
13946 * `av_num_entries`. The granularity of these values is defined by
13947 * the `mrav_num_entries_unit` field returned by the
13948 * `backing_store_qcaps` command.
13950 uint32_t mrav_num_entries;
13951 /* Number of Timer entries. */
13952 uint32_t tim_num_entries;
13953 uint8_t unused_1[7];
13955 * This field is used in Output records to indicate that the output
13956 * is completely written to RAM. This field should be read as 1
13957 * to indicate that the output has been completely written.
13958 * When writing a command completion or response to an internal
13959 * processor, the order of writes has to be such that this field
13965 /****************************
13966 * hwrm_error_recovery_qcfg *
13967 ****************************/
13970 /* hwrm_error_recovery_qcfg_input (size:192b/24B) */
13971 struct hwrm_error_recovery_qcfg_input {
13972 /* The HWRM command request type. */
13975 * The completion ring to send the completion event on. This should
13976 * be the NQ ID returned from the `nq_alloc` HWRM command.
13978 uint16_t cmpl_ring;
13980 * The sequence ID is used by the driver for tracking multiple
13981 * commands. This ID is treated as opaque data by the firmware and
13982 * the value is returned in the `hwrm_resp_hdr` upon completion.
13986 * The target ID of the command:
13987 * * 0x0-0xFFF8 - The function ID
13988 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
13989 * * 0xFFFD - Reserved for user-space HWRM interface
13992 uint16_t target_id;
13994 * A physical address pointer pointing to a host buffer that the
13995 * command's response data will be written. This can be either a host
13996 * physical address (HPA) or a guest physical address (GPA) and must
13997 * point to a physically contiguous block of memory.
13999 uint64_t resp_addr;
14000 uint8_t unused_0[8];
14003 /* hwrm_error_recovery_qcfg_output (size:1664b/208B) */
14004 struct hwrm_error_recovery_qcfg_output {
14005 /* The specific error status for the command. */
14006 uint16_t error_code;
14007 /* The HWRM command request type. */
14009 /* The sequence ID from the original command. */
14011 /* The length of the response data in number of bytes. */
14015 * When this flag is set to 1, error recovery will be initiated
14016 * through master function driver.
14018 #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FLAGS_HOST UINT32_C(0x1)
14020 * When this flag is set to 1, error recovery will be performed
14021 * through Co processor.
14023 #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FLAGS_CO_CPU UINT32_C(0x2)
14025 * Driver Polling frequency. This value is in units of 100msec.
14026 * Typical value would be 10 to indicate 1sec.
14027 * Drivers can poll FW health status, Heartbeat, reset_counter with
14030 uint32_t driver_polling_freq;
14032 * This value is in units of 100msec.
14033 * Typical value would be 30 to indicate 3sec.
14034 * Master function wait period from detecting a fatal error to
14035 * initiating reset. In this time period Master PF expects every
14036 * active driver will detect fatal error.
14038 uint32_t master_func_wait_period;
14040 * This value is in units of 100msec.
14041 * Typical value would be 50 to indicate 5sec.
14042 * Normal function wait period from fatal error detection to
14043 * polling FW health status. In this time period, drivers should not
14044 * do any PCIe MMIO transaction and should not send any HWRM commands.
14046 uint32_t normal_func_wait_period;
14048 * This value is in units of 100msec.
14049 * Typical value would be 20 to indicate 2sec.
14050 * This field indicates that, master function wait period after chip
14051 * reset. After this time, master function should reinitialize with
14054 uint32_t master_func_wait_period_after_reset;
14056 * This value is in units of 100msec.
14057 * Typical value would be 60 to indicate 6sec.
14058 * This field is applicable to both master and normal functions.
14059 * Even after chip reset, if FW status not changed to ready,
14060 * then all the functions can poll for this much time and bailout.
14062 uint32_t max_bailout_time_after_reset;
14064 * FW health status register.
14065 * Lower 2 bits indicates address space location and upper 30 bits
14066 * indicates upper 30bits of the register address.
14067 * A value of 0xFFFF-FFFF indicates this register does not exist.
14069 uint32_t fw_health_status_reg;
14070 /* Lower 2 bits indicates address space location. */
14071 #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FW_HEALTH_STATUS_REG_ADDR_SPACE_MASK \
14073 #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FW_HEALTH_STATUS_REG_ADDR_SPACE_SFT \
14076 * If value is 0, this register is located in PCIe config space.
14077 * Drivers have to map appropriate window to access this
14080 #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FW_HEALTH_STATUS_REG_ADDR_SPACE_PCIE_CFG \
14083 * If value is 1, this register is located in GRC address space.
14084 * Drivers have to map appropriate window to access this
14087 #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FW_HEALTH_STATUS_REG_ADDR_SPACE_GRC \
14090 * If value is 2, this register is located in first BAR address
14091 * space. Drivers have to map appropriate window to access this
14094 #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FW_HEALTH_STATUS_REG_ADDR_SPACE_BAR0 \
14097 * If value is 3, this register is located in second BAR address
14098 * space. Drivers have to map appropriate window to access this
14099 * Drivers have to map appropriate window to access this
14102 #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FW_HEALTH_STATUS_REG_ADDR_SPACE_BAR1 \
14104 #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FW_HEALTH_STATUS_REG_ADDR_SPACE_LAST \
14105 HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FW_HEALTH_STATUS_REG_ADDR_SPACE_BAR1
14106 /* Upper 30bits of the register address. */
14107 #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FW_HEALTH_STATUS_REG_ADDR_MASK \
14108 UINT32_C(0xfffffffc)
14109 #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FW_HEALTH_STATUS_REG_ADDR_SFT \
14112 * FW HeartBeat register.
14113 * Lower 2 bits indicates address space location and upper 30 bits
14114 * indicates actual address.
14115 * A value of 0xFFFF-FFFF indicates this register does not exist.
14117 uint32_t fw_heartbeat_reg;
14118 /* Lower 2 bits indicates address space location. */
14119 #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FW_HEARTBEAT_REG_ADDR_SPACE_MASK \
14121 #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FW_HEARTBEAT_REG_ADDR_SPACE_SFT \
14124 * If value is 0, this register is located in PCIe config space.
14125 * Drivers have to map appropriate window to access this
14128 #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FW_HEARTBEAT_REG_ADDR_SPACE_PCIE_CFG \
14131 * If value is 1, this register is located in GRC address space.
14132 * Drivers have to map appropriate window to access this
14135 #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FW_HEARTBEAT_REG_ADDR_SPACE_GRC \
14138 * If value is 2, this register is located in first BAR address
14139 * space. Drivers have to map appropriate window to access this
14142 #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FW_HEARTBEAT_REG_ADDR_SPACE_BAR0 \
14145 * If value is 3, this register is located in second BAR address
14146 * space. Drivers have to map appropriate window to access this
14149 #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FW_HEARTBEAT_REG_ADDR_SPACE_BAR1 \
14151 #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FW_HEARTBEAT_REG_ADDR_SPACE_LAST \
14152 HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FW_HEARTBEAT_REG_ADDR_SPACE_BAR1
14153 /* Upper 30bits of the register address. */
14154 #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FW_HEARTBEAT_REG_ADDR_MASK \
14155 UINT32_C(0xfffffffc)
14156 #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FW_HEARTBEAT_REG_ADDR_SFT \
14159 * FW reset counter.
14160 * Lower 2 bits indicates address space location and upper 30 bits
14161 * indicates actual address.
14162 * A value of 0xFFFF-FFFF indicates this register does not exist.
14164 uint32_t fw_reset_cnt_reg;
14165 /* Lower 2 bits indicates address space location. */
14166 #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FW_RESET_CNT_REG_ADDR_SPACE_MASK \
14168 #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FW_RESET_CNT_REG_ADDR_SPACE_SFT \
14171 * If value is 0, this register is located in PCIe config space.
14172 * Drivers have to map appropriate window to access this
14175 #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FW_RESET_CNT_REG_ADDR_SPACE_PCIE_CFG \
14178 * If value is 1, this register is located in GRC address space.
14179 * Drivers have to map appropriate window to access this
14182 #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FW_RESET_CNT_REG_ADDR_SPACE_GRC \
14185 * If value is 2, this register is located in first BAR address
14186 * space. Drivers have to map appropriate window to access this
14189 #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FW_RESET_CNT_REG_ADDR_SPACE_BAR0 \
14192 * If value is 3, this register is located in second BAR address
14193 * space. Drivers have to map appropriate window to access this
14196 #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FW_RESET_CNT_REG_ADDR_SPACE_BAR1 \
14198 #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FW_RESET_CNT_REG_ADDR_SPACE_LAST \
14199 HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FW_RESET_CNT_REG_ADDR_SPACE_BAR1
14200 /* Upper 30bits of the register address. */
14201 #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FW_RESET_CNT_REG_ADDR_MASK \
14202 UINT32_C(0xfffffffc)
14203 #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FW_RESET_CNT_REG_ADDR_SFT \
14206 * Reset Inprogress Register address for PFs.
14207 * Lower 2 bits indicates address space location and upper 30 bits
14208 * indicates actual address.
14209 * A value of 0xFFFF-FFFF indicates this register does not exist.
14211 uint32_t reset_inprogress_reg;
14212 /* Lower 2 bits indicates address space location. */
14213 #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_RESET_INPROGRESS_REG_ADDR_SPACE_MASK \
14215 #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_RESET_INPROGRESS_REG_ADDR_SPACE_SFT \
14218 * If value is 0, this register is located in PCIe config space.
14219 * Drivers have to map appropriate window to access this
14222 #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_RESET_INPROGRESS_REG_ADDR_SPACE_PCIE_CFG \
14225 * If value is 1, this register is located in GRC address space.
14226 * Drivers have to map appropriate window to access this
14229 #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_RESET_INPROGRESS_REG_ADDR_SPACE_GRC \
14232 * If value is 2, this register is located in first BAR address
14233 * space. Drivers have to map appropriate window to access this
14236 #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_RESET_INPROGRESS_REG_ADDR_SPACE_BAR0 \
14239 * If value is 3, this register is located in second BAR address
14240 * space. Drivers have to map appropriate window to access this
14243 #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_RESET_INPROGRESS_REG_ADDR_SPACE_BAR1 \
14245 #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_RESET_INPROGRESS_REG_ADDR_SPACE_LAST \
14246 HWRM_ERROR_RECOVERY_QCFG_OUTPUT_RESET_INPROGRESS_REG_ADDR_SPACE_BAR1
14247 /* Upper 30bits of the register address. */
14248 #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_RESET_INPROGRESS_REG_ADDR_MASK \
14249 UINT32_C(0xfffffffc)
14250 #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_RESET_INPROGRESS_REG_ADDR_SFT \
14252 /* This field indicates the mask value for reset_inprogress_reg. */
14253 uint32_t reset_inprogress_reg_mask;
14254 uint8_t unused_0[3];
14256 * Array of registers and value count to reset the Chip
14257 * Each array count has reset_reg, reset_reg_val, delay_after_reset
14258 * in TLV format. Depending upon Chip type, number of reset registers
14259 * will vary. Drivers have to write reset_reg_val in the reset_reg
14260 * location in the same sequence in order to recover from a fatal
14263 uint8_t reg_array_cnt;
14266 * Lower 2 bits indicates address space location and upper 30 bits
14267 * indicates actual address.
14268 * A value of 0xFFFF-FFFF indicates this register does not exist.
14270 uint32_t reset_reg[16];
14271 /* Lower 2 bits indicates address space location. */
14272 #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_RESET_REG_ADDR_SPACE_MASK \
14274 #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_RESET_REG_ADDR_SPACE_SFT 0
14276 * If value is 0, this register is located in PCIe config space.
14277 * Drivers have to map appropriate window to access this
14280 #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_RESET_REG_ADDR_SPACE_PCIE_CFG \
14283 * If value is 1, this register is located in GRC address space.
14284 * Drivers have to map appropriate window to access this
14287 #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_RESET_REG_ADDR_SPACE_GRC \
14290 * If value is 2, this register is located in first BAR address
14291 * space. Drivers have to map appropriate window to access this
14294 #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_RESET_REG_ADDR_SPACE_BAR0 \
14297 * If value is 3, this register is located in second BAR address
14298 * space. Drivers have to map appropriate window to access this
14301 #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_RESET_REG_ADDR_SPACE_BAR1 \
14303 #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_RESET_REG_ADDR_SPACE_LAST \
14304 HWRM_ERROR_RECOVERY_QCFG_OUTPUT_RESET_REG_ADDR_SPACE_BAR1
14305 /* Upper 30bits of the register address. */
14306 #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_RESET_REG_ADDR_MASK \
14307 UINT32_C(0xfffffffc)
14308 #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_RESET_REG_ADDR_SFT 2
14309 /* Value to be written in reset_reg to reset the controller. */
14310 uint32_t reset_reg_val[16];
14312 * This value is in units of 1msec.
14313 * Typical value would be 10 to indicate 10msec.
14314 * Some of the operations like Core reset require delay before
14315 * accessing PCIE MMIO register space.
14316 * If this value is non-zero, drivers have to wait for
14317 * this much time after writing reset_reg_val in reset_reg.
14319 uint8_t delay_after_reset[16];
14321 * Error recovery counter.
14322 * Lower 2 bits indicates address space location and upper 30 bits
14323 * indicates actual address.
14324 * A value of 0xFFFF-FFFF indicates this register does not exist.
14326 uint32_t err_recovery_cnt_reg;
14327 /* Lower 2 bits indicates address space location. */
14328 #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_ERR_RECOVERY_CNT_REG_ADDR_SPACE_MASK \
14330 #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_ERR_RECOVERY_CNT_REG_ADDR_SPACE_SFT \
14333 * If value is 0, this register is located in PCIe config space.
14334 * Drivers have to map appropriate window to access this
14337 #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_ERR_RECOVERY_CNT_REG_ADDR_SPACE_PCIE_CFG \
14340 * If value is 1, this register is located in GRC address space.
14341 * Drivers have to map appropriate window to access this
14344 #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_ERR_RECOVERY_CNT_REG_ADDR_SPACE_GRC \
14347 * If value is 2, this register is located in first BAR address
14348 * space. Drivers have to map appropriate window to access this
14351 #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_ERR_RECOVERY_CNT_REG_ADDR_SPACE_BAR0 \
14354 * If value is 3, this register is located in second BAR address
14355 * space. Drivers have to map appropriate window to access this
14358 #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_ERR_RECOVERY_CNT_REG_ADDR_SPACE_BAR1 \
14360 #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_ERR_RECOVERY_CNT_REG_ADDR_SPACE_LAST \
14361 HWRM_ERROR_RECOVERY_QCFG_OUTPUT_ERR_RECOVERY_CNT_REG_ADDR_SPACE_BAR1
14362 /* Upper 30bits of the register address. */
14363 #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_ERR_RECOVERY_CNT_REG_ADDR_MASK \
14364 UINT32_C(0xfffffffc)
14365 #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_ERR_RECOVERY_CNT_REG_ADDR_SFT \
14367 uint8_t unused_1[3];
14369 * This field is used in Output records to indicate that the output
14370 * is completely written to RAM. This field should be read as '1'
14371 * to indicate that the output has been completely written.
14372 * When writing a command completion or response to an internal
14373 * processor, the order of writes has to be such that this field
14379 /***********************
14380 * hwrm_func_vlan_qcfg *
14381 ***********************/
14384 /* hwrm_func_vlan_qcfg_input (size:192b/24B) */
14385 struct hwrm_func_vlan_qcfg_input {
14386 /* The HWRM command request type. */
14389 * The completion ring to send the completion event on. This should
14390 * be the NQ ID returned from the `nq_alloc` HWRM command.
14392 uint16_t cmpl_ring;
14394 * The sequence ID is used by the driver for tracking multiple
14395 * commands. This ID is treated as opaque data by the firmware and
14396 * the value is returned in the `hwrm_resp_hdr` upon completion.
14400 * The target ID of the command:
14401 * * 0x0-0xFFF8 - The function ID
14402 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
14403 * * 0xFFFD - Reserved for user-space HWRM interface
14406 uint16_t target_id;
14408 * A physical address pointer pointing to a host buffer that the
14409 * command's response data will be written. This can be either a host
14410 * physical address (HPA) or a guest physical address (GPA) and must
14411 * point to a physically contiguous block of memory.
14413 uint64_t resp_addr;
14415 * Function ID of the function that is being
14417 * If set to 0xFF... (All Fs), then the configuration is
14418 * for the requesting function.
14421 uint8_t unused_0[6];
14424 /* hwrm_func_vlan_qcfg_output (size:320b/40B) */
14425 struct hwrm_func_vlan_qcfg_output {
14426 /* The specific error status for the command. */
14427 uint16_t error_code;
14428 /* The HWRM command request type. */
14430 /* The sequence ID from the original command. */
14432 /* The length of the response data in number of bytes. */
14435 /* S-TAG VLAN identifier configured for the function. */
14437 /* S-TAG PCP value configured for the function. */
14441 * S-TAG TPID value configured for the function. This field is specified in
14442 * network byte order.
14444 uint16_t stag_tpid;
14445 /* C-TAG VLAN identifier configured for the function. */
14447 /* C-TAG PCP value configured for the function. */
14451 * C-TAG TPID value configured for the function. This field is specified in
14452 * network byte order.
14454 uint16_t ctag_tpid;
14459 uint8_t unused_3[3];
14461 * This field is used in Output records to indicate that the output
14462 * is completely written to RAM. This field should be read as '1'
14463 * to indicate that the output has been completely written.
14464 * When writing a command completion or response to an internal processor,
14465 * the order of writes has to be such that this field is written last.
14470 /**********************
14471 * hwrm_func_vlan_cfg *
14472 **********************/
14475 /* hwrm_func_vlan_cfg_input (size:384b/48B) */
14476 struct hwrm_func_vlan_cfg_input {
14477 /* The HWRM command request type. */
14480 * The completion ring to send the completion event on. This should
14481 * be the NQ ID returned from the `nq_alloc` HWRM command.
14483 uint16_t cmpl_ring;
14485 * The sequence ID is used by the driver for tracking multiple
14486 * commands. This ID is treated as opaque data by the firmware and
14487 * the value is returned in the `hwrm_resp_hdr` upon completion.
14491 * The target ID of the command:
14492 * * 0x0-0xFFF8 - The function ID
14493 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
14494 * * 0xFFFD - Reserved for user-space HWRM interface
14497 uint16_t target_id;
14499 * A physical address pointer pointing to a host buffer that the
14500 * command's response data will be written. This can be either a host
14501 * physical address (HPA) or a guest physical address (GPA) and must
14502 * point to a physically contiguous block of memory.
14504 uint64_t resp_addr;
14506 * Function ID of the function that is being
14508 * If set to 0xFF... (All Fs), then the configuration is
14509 * for the requesting function.
14512 uint8_t unused_0[2];
14515 * This bit must be '1' for the stag_vid field to be
14518 #define HWRM_FUNC_VLAN_CFG_INPUT_ENABLES_STAG_VID UINT32_C(0x1)
14520 * This bit must be '1' for the ctag_vid field to be
14523 #define HWRM_FUNC_VLAN_CFG_INPUT_ENABLES_CTAG_VID UINT32_C(0x2)
14525 * This bit must be '1' for the stag_pcp field to be
14528 #define HWRM_FUNC_VLAN_CFG_INPUT_ENABLES_STAG_PCP UINT32_C(0x4)
14530 * This bit must be '1' for the ctag_pcp field to be
14533 #define HWRM_FUNC_VLAN_CFG_INPUT_ENABLES_CTAG_PCP UINT32_C(0x8)
14535 * This bit must be '1' for the stag_tpid field to be
14538 #define HWRM_FUNC_VLAN_CFG_INPUT_ENABLES_STAG_TPID UINT32_C(0x10)
14540 * This bit must be '1' for the ctag_tpid field to be
14543 #define HWRM_FUNC_VLAN_CFG_INPUT_ENABLES_CTAG_TPID UINT32_C(0x20)
14544 /* S-TAG VLAN identifier configured for the function. */
14546 /* S-TAG PCP value configured for the function. */
14550 * S-TAG TPID value configured for the function. This field is specified in
14551 * network byte order.
14553 uint16_t stag_tpid;
14554 /* C-TAG VLAN identifier configured for the function. */
14556 /* C-TAG PCP value configured for the function. */
14560 * C-TAG TPID value configured for the function. This field is specified in
14561 * network byte order.
14563 uint16_t ctag_tpid;
14568 uint8_t unused_3[4];
14571 /* hwrm_func_vlan_cfg_output (size:128b/16B) */
14572 struct hwrm_func_vlan_cfg_output {
14573 /* The specific error status for the command. */
14574 uint16_t error_code;
14575 /* The HWRM command request type. */
14577 /* The sequence ID from the original command. */
14579 /* The length of the response data in number of bytes. */
14581 uint8_t unused_0[7];
14583 * This field is used in Output records to indicate that the output
14584 * is completely written to RAM. This field should be read as '1'
14585 * to indicate that the output has been completely written.
14586 * When writing a command completion or response to an internal processor,
14587 * the order of writes has to be such that this field is written last.
14592 /*******************************
14593 * hwrm_func_vf_vnic_ids_query *
14594 *******************************/
14597 /* hwrm_func_vf_vnic_ids_query_input (size:256b/32B) */
14598 struct hwrm_func_vf_vnic_ids_query_input {
14599 /* The HWRM command request type. */
14602 * The completion ring to send the completion event on. This should
14603 * be the NQ ID returned from the `nq_alloc` HWRM command.
14605 uint16_t cmpl_ring;
14607 * The sequence ID is used by the driver for tracking multiple
14608 * commands. This ID is treated as opaque data by the firmware and
14609 * the value is returned in the `hwrm_resp_hdr` upon completion.
14613 * The target ID of the command:
14614 * * 0x0-0xFFF8 - The function ID
14615 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
14616 * * 0xFFFD - Reserved for user-space HWRM interface
14619 uint16_t target_id;
14621 * A physical address pointer pointing to a host buffer that the
14622 * command's response data will be written. This can be either a host
14623 * physical address (HPA) or a guest physical address (GPA) and must
14624 * point to a physically contiguous block of memory.
14626 uint64_t resp_addr;
14628 * This value is used to identify a Virtual Function (VF).
14629 * The scope of VF ID is local within a PF.
14632 uint8_t unused_0[2];
14633 /* Max number of vnic ids in vnic id table */
14634 uint32_t max_vnic_id_cnt;
14635 /* This is the address for VF VNIC ID table */
14636 uint64_t vnic_id_tbl_addr;
14639 /* hwrm_func_vf_vnic_ids_query_output (size:128b/16B) */
14640 struct hwrm_func_vf_vnic_ids_query_output {
14641 /* The specific error status for the command. */
14642 uint16_t error_code;
14643 /* The HWRM command request type. */
14645 /* The sequence ID from the original command. */
14647 /* The length of the response data in number of bytes. */
14650 * Actual number of vnic ids
14652 * Each VNIC ID is written as a 32-bit number.
14654 uint32_t vnic_id_cnt;
14655 uint8_t unused_0[3];
14657 * This field is used in Output records to indicate that the output
14658 * is completely written to RAM. This field should be read as '1'
14659 * to indicate that the output has been completely written.
14660 * When writing a command completion or response to an internal processor,
14661 * the order of writes has to be such that this field is written last.
14666 /***********************
14667 * hwrm_func_vf_bw_cfg *
14668 ***********************/
14671 /* hwrm_func_vf_bw_cfg_input (size:960b/120B) */
14672 struct hwrm_func_vf_bw_cfg_input {
14673 /* The HWRM command request type. */
14676 * The completion ring to send the completion event on. This should
14677 * be the NQ ID returned from the `nq_alloc` HWRM command.
14679 uint16_t cmpl_ring;
14681 * The sequence ID is used by the driver for tracking multiple
14682 * commands. This ID is treated as opaque data by the firmware and
14683 * the value is returned in the `hwrm_resp_hdr` upon completion.
14687 * The target ID of the command:
14688 * * 0x0-0xFFF8 - The function ID
14689 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
14690 * * 0xFFFD - Reserved for user-space HWRM interface
14693 uint16_t target_id;
14695 * A physical address pointer pointing to a host buffer that the
14696 * command's response data will be written. This can be either a host
14697 * physical address (HPA) or a guest physical address (GPA) and must
14698 * point to a physically contiguous block of memory.
14700 uint64_t resp_addr;
14702 * The number of VF functions that are being configured.
14703 * The cmd space allows up to 50 VFs' BW to be configured with one cmd.
14706 uint16_t unused[3];
14707 /* These 16-bit fields contain the VF fid and the rate scale percentage. */
14709 /* The physical VF id the adjustment will be made to. */
14710 #define HWRM_FUNC_VF_BW_CFG_INPUT_VFN_VFID_MASK UINT32_C(0xfff)
14711 #define HWRM_FUNC_VF_BW_CFG_INPUT_VFN_VFID_SFT 0
14713 * This field configures the rate scale percentage of the VF as specified
14714 * by the physical VF id.
14716 #define HWRM_FUNC_VF_BW_CFG_INPUT_VFN_RATE_MASK UINT32_C(0xf000)
14717 #define HWRM_FUNC_VF_BW_CFG_INPUT_VFN_RATE_SFT 12
14718 /* 0% of the max tx rate */
14719 #define HWRM_FUNC_VF_BW_CFG_INPUT_VFN_RATE_PCT_0 \
14720 (UINT32_C(0x0) << 12)
14721 /* 6.66% of the max tx rate */
14722 #define HWRM_FUNC_VF_BW_CFG_INPUT_VFN_RATE_PCT_6_66 \
14723 (UINT32_C(0x1) << 12)
14724 /* 13.33% of the max tx rate */
14725 #define HWRM_FUNC_VF_BW_CFG_INPUT_VFN_RATE_PCT_13_33 \
14726 (UINT32_C(0x2) << 12)
14727 /* 20% of the max tx rate */
14728 #define HWRM_FUNC_VF_BW_CFG_INPUT_VFN_RATE_PCT_20 \
14729 (UINT32_C(0x3) << 12)
14730 /* 26.66% of the max tx rate */
14731 #define HWRM_FUNC_VF_BW_CFG_INPUT_VFN_RATE_PCT_26_66 \
14732 (UINT32_C(0x4) << 12)
14733 /* 33% of the max tx rate */
14734 #define HWRM_FUNC_VF_BW_CFG_INPUT_VFN_RATE_PCT_33_33 \
14735 (UINT32_C(0x5) << 12)
14736 /* 40% of the max tx rate */
14737 #define HWRM_FUNC_VF_BW_CFG_INPUT_VFN_RATE_PCT_40 \
14738 (UINT32_C(0x6) << 12)
14739 /* 46.66% of the max tx rate */
14740 #define HWRM_FUNC_VF_BW_CFG_INPUT_VFN_RATE_PCT_46_66 \
14741 (UINT32_C(0x7) << 12)
14742 /* 53.33% of the max tx rate */
14743 #define HWRM_FUNC_VF_BW_CFG_INPUT_VFN_RATE_PCT_53_33 \
14744 (UINT32_C(0x8) << 12)
14745 /* 60% of the max tx rate */
14746 #define HWRM_FUNC_VF_BW_CFG_INPUT_VFN_RATE_PCT_60 \
14747 (UINT32_C(0x9) << 12)
14748 /* 66.66% of the max tx rate */
14749 #define HWRM_FUNC_VF_BW_CFG_INPUT_VFN_RATE_PCT_66_66 \
14750 (UINT32_C(0xa) << 12)
14751 /* 53.33% of the max tx rate */
14752 #define HWRM_FUNC_VF_BW_CFG_INPUT_VFN_RATE_PCT_73_33 \
14753 (UINT32_C(0xb) << 12)
14754 /* 80% of the max tx rate */
14755 #define HWRM_FUNC_VF_BW_CFG_INPUT_VFN_RATE_PCT_80 \
14756 (UINT32_C(0xc) << 12)
14757 /* 86.66% of the max tx rate */
14758 #define HWRM_FUNC_VF_BW_CFG_INPUT_VFN_RATE_PCT_86_66 \
14759 (UINT32_C(0xd) << 12)
14760 /* 93.33% of the max tx rate */
14761 #define HWRM_FUNC_VF_BW_CFG_INPUT_VFN_RATE_PCT_93_33 \
14762 (UINT32_C(0xe) << 12)
14763 /* 100% of the max tx rate */
14764 #define HWRM_FUNC_VF_BW_CFG_INPUT_VFN_RATE_PCT_100 \
14765 (UINT32_C(0xf) << 12)
14766 #define HWRM_FUNC_VF_BW_CFG_INPUT_VFN_RATE_LAST \
14767 HWRM_FUNC_VF_BW_CFG_INPUT_VFN_RATE_PCT_100
14770 /* hwrm_func_vf_bw_cfg_output (size:128b/16B) */
14771 struct hwrm_func_vf_bw_cfg_output {
14772 /* The specific error status for the command. */
14773 uint16_t error_code;
14774 /* The HWRM command request type. */
14776 /* The sequence ID from the original command. */
14778 /* The length of the response data in number of bytes. */
14780 uint8_t unused_0[7];
14782 * This field is used in Output records to indicate that the output
14783 * is completely written to RAM. This field should be read as '1'
14784 * to indicate that the output has been completely written.
14785 * When writing a command completion or response to an internal processor,
14786 * the order of writes has to be such that this field is written last.
14791 /************************
14792 * hwrm_func_vf_bw_qcfg *
14793 ************************/
14796 /* hwrm_func_vf_bw_qcfg_input (size:960b/120B) */
14797 struct hwrm_func_vf_bw_qcfg_input {
14798 /* The HWRM command request type. */
14801 * The completion ring to send the completion event on. This should
14802 * be the NQ ID returned from the `nq_alloc` HWRM command.
14804 uint16_t cmpl_ring;
14806 * The sequence ID is used by the driver for tracking multiple
14807 * commands. This ID is treated as opaque data by the firmware and
14808 * the value is returned in the `hwrm_resp_hdr` upon completion.
14812 * The target ID of the command:
14813 * * 0x0-0xFFF8 - The function ID
14814 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
14815 * * 0xFFFD - Reserved for user-space HWRM interface
14818 uint16_t target_id;
14820 * A physical address pointer pointing to a host buffer that the
14821 * command's response data will be written. This can be either a host
14822 * physical address (HPA) or a guest physical address (GPA) and must
14823 * point to a physically contiguous block of memory.
14825 uint64_t resp_addr;
14827 * The number of VF functions that are being queried.
14828 * The inline response space allows the host to query up to 50 VFs'
14829 * rate scale percentage
14832 uint16_t unused[3];
14833 /* These 16-bit fields contain the VF fid */
14835 /* The physical VF id of interest */
14836 #define HWRM_FUNC_VF_BW_QCFG_INPUT_VFN_VFID_MASK UINT32_C(0xfff)
14837 #define HWRM_FUNC_VF_BW_QCFG_INPUT_VFN_VFID_SFT 0
14840 /* hwrm_func_vf_bw_qcfg_output (size:960b/120B) */
14841 struct hwrm_func_vf_bw_qcfg_output {
14842 /* The specific error status for the command. */
14843 uint16_t error_code;
14844 /* The HWRM command request type. */
14846 /* The sequence ID from the original command. */
14848 /* The length of the response data in number of bytes. */
14851 * The number of VF functions that are being queried.
14852 * The inline response space allows the host to query up to 50 VFs' rate
14856 uint16_t unused[3];
14857 /* These 16-bit fields contain the VF fid and the rate scale percentage. */
14859 /* The physical VF id the adjustment will be made to. */
14860 #define HWRM_FUNC_VF_BW_QCFG_OUTPUT_VFN_VFID_MASK UINT32_C(0xfff)
14861 #define HWRM_FUNC_VF_BW_QCFG_OUTPUT_VFN_VFID_SFT 0
14863 * This field configures the rate scale percentage of the VF as specified
14864 * by the physical VF id.
14866 #define HWRM_FUNC_VF_BW_QCFG_OUTPUT_VFN_RATE_MASK UINT32_C(0xf000)
14867 #define HWRM_FUNC_VF_BW_QCFG_OUTPUT_VFN_RATE_SFT 12
14868 /* 0% of the max tx rate */
14869 #define HWRM_FUNC_VF_BW_QCFG_OUTPUT_VFN_RATE_PCT_0 \
14870 (UINT32_C(0x0) << 12)
14871 /* 6.66% of the max tx rate */
14872 #define HWRM_FUNC_VF_BW_QCFG_OUTPUT_VFN_RATE_PCT_6_66 \
14873 (UINT32_C(0x1) << 12)
14874 /* 13.33% of the max tx rate */
14875 #define HWRM_FUNC_VF_BW_QCFG_OUTPUT_VFN_RATE_PCT_13_33 \
14876 (UINT32_C(0x2) << 12)
14877 /* 20% of the max tx rate */
14878 #define HWRM_FUNC_VF_BW_QCFG_OUTPUT_VFN_RATE_PCT_20 \
14879 (UINT32_C(0x3) << 12)
14880 /* 26.66% of the max tx rate */
14881 #define HWRM_FUNC_VF_BW_QCFG_OUTPUT_VFN_RATE_PCT_26_66 \
14882 (UINT32_C(0x4) << 12)
14883 /* 33% of the max tx rate */
14884 #define HWRM_FUNC_VF_BW_QCFG_OUTPUT_VFN_RATE_PCT_33_33 \
14885 (UINT32_C(0x5) << 12)
14886 /* 40% of the max tx rate */
14887 #define HWRM_FUNC_VF_BW_QCFG_OUTPUT_VFN_RATE_PCT_40 \
14888 (UINT32_C(0x6) << 12)
14889 /* 46.66% of the max tx rate */
14890 #define HWRM_FUNC_VF_BW_QCFG_OUTPUT_VFN_RATE_PCT_46_66 \
14891 (UINT32_C(0x7) << 12)
14892 /* 53.33% of the max tx rate */
14893 #define HWRM_FUNC_VF_BW_QCFG_OUTPUT_VFN_RATE_PCT_53_33 \
14894 (UINT32_C(0x8) << 12)
14895 /* 60% of the max tx rate */
14896 #define HWRM_FUNC_VF_BW_QCFG_OUTPUT_VFN_RATE_PCT_60 \
14897 (UINT32_C(0x9) << 12)
14898 /* 66.66% of the max tx rate */
14899 #define HWRM_FUNC_VF_BW_QCFG_OUTPUT_VFN_RATE_PCT_66_66 \
14900 (UINT32_C(0xa) << 12)
14901 /* 53.33% of the max tx rate */
14902 #define HWRM_FUNC_VF_BW_QCFG_OUTPUT_VFN_RATE_PCT_73_33 \
14903 (UINT32_C(0xb) << 12)
14904 /* 80% of the max tx rate */
14905 #define HWRM_FUNC_VF_BW_QCFG_OUTPUT_VFN_RATE_PCT_80 \
14906 (UINT32_C(0xc) << 12)
14907 /* 86.66% of the max tx rate */
14908 #define HWRM_FUNC_VF_BW_QCFG_OUTPUT_VFN_RATE_PCT_86_66 \
14909 (UINT32_C(0xd) << 12)
14910 /* 93.33% of the max tx rate */
14911 #define HWRM_FUNC_VF_BW_QCFG_OUTPUT_VFN_RATE_PCT_93_33 \
14912 (UINT32_C(0xe) << 12)
14913 /* 100% of the max tx rate */
14914 #define HWRM_FUNC_VF_BW_QCFG_OUTPUT_VFN_RATE_PCT_100 \
14915 (UINT32_C(0xf) << 12)
14916 #define HWRM_FUNC_VF_BW_QCFG_OUTPUT_VFN_RATE_LAST \
14917 HWRM_FUNC_VF_BW_QCFG_OUTPUT_VFN_RATE_PCT_100
14918 uint8_t unused_0[7];
14920 * This field is used in Output records to indicate that the output
14921 * is completely written to RAM. This field should be read as '1'
14922 * to indicate that the output has been completely written.
14923 * When writing a command completion or response to an internal processor,
14924 * the order of writes has to be such that this field is written last.
14929 /***************************
14930 * hwrm_func_drv_if_change *
14931 ***************************/
14934 /* hwrm_func_drv_if_change_input (size:192b/24B) */
14935 struct hwrm_func_drv_if_change_input {
14936 /* The HWRM command request type. */
14939 * The completion ring to send the completion event on. This should
14940 * be the NQ ID returned from the `nq_alloc` HWRM command.
14942 uint16_t cmpl_ring;
14944 * The sequence ID is used by the driver for tracking multiple
14945 * commands. This ID is treated as opaque data by the firmware and
14946 * the value is returned in the `hwrm_resp_hdr` upon completion.
14950 * The target ID of the command:
14951 * * 0x0-0xFFF8 - The function ID
14952 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
14953 * * 0xFFFD - Reserved for user-space HWRM interface
14956 uint16_t target_id;
14958 * A physical address pointer pointing to a host buffer that the
14959 * command's response data will be written. This can be either a host
14960 * physical address (HPA) or a guest physical address (GPA) and must
14961 * point to a physically contiguous block of memory.
14963 uint64_t resp_addr;
14966 * When this bit is '1', the function driver is indicating
14967 * that the IF state is changing to UP state. The call should
14968 * be made at the beginning of the driver's open call before
14969 * resources are allocated. After making the call, the driver
14970 * should check the response to see if any resources may have
14971 * changed (see the response below). If the driver fails
14972 * the open call, the driver should make this call again with
14973 * this bit cleared to indicate that the IF state is not UP.
14974 * During the driver's close call when the IF state is changing
14975 * to DOWN, the driver should make this call with the bit cleared
14976 * after all resources have been freed.
14978 #define HWRM_FUNC_DRV_IF_CHANGE_INPUT_FLAGS_UP UINT32_C(0x1)
14982 /* hwrm_func_drv_if_change_output (size:128b/16B) */
14983 struct hwrm_func_drv_if_change_output {
14984 /* The specific error status for the command. */
14985 uint16_t error_code;
14986 /* The HWRM command request type. */
14988 /* The sequence ID from the original command. */
14990 /* The length of the response data in number of bytes. */
14994 * When this bit is '1', it indicates that the resources reserved
14995 * for this function may have changed. The driver should check
14996 * resource capabilities and reserve resources again before
14997 * allocating resources.
14999 #define HWRM_FUNC_DRV_IF_CHANGE_OUTPUT_FLAGS_RESC_CHANGE \
15002 * When this bit is '1', it indicates that the firmware got changed / reset.
15003 * The driver should do complete re-initialization when that bit is set.
15005 #define HWRM_FUNC_DRV_IF_CHANGE_OUTPUT_FLAGS_HOT_FW_RESET_DONE \
15007 uint8_t unused_0[3];
15009 * This field is used in Output records to indicate that the output
15010 * is completely written to RAM. This field should be read as '1'
15011 * to indicate that the output has been completely written.
15012 * When writing a command completion or response to an internal processor,
15013 * the order of writes has to be such that this field is written last.
15018 /*******************************
15019 * hwrm_func_host_pf_ids_query *
15020 *******************************/
15023 /* hwrm_func_host_pf_ids_query_input (size:192b/24B) */
15024 struct hwrm_func_host_pf_ids_query_input {
15025 /* The HWRM command request type. */
15028 * The completion ring to send the completion event on. This should
15029 * be the NQ ID returned from the `nq_alloc` HWRM command.
15031 uint16_t cmpl_ring;
15033 * The sequence ID is used by the driver for tracking multiple
15034 * commands. This ID is treated as opaque data by the firmware and
15035 * the value is returned in the `hwrm_resp_hdr` upon completion.
15039 * The target ID of the command:
15040 * * 0x0-0xFFF8 - The function ID
15041 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
15042 * * 0xFFFD - Reserved for user-space HWRM interface
15045 uint16_t target_id;
15047 * A physical address pointer pointing to a host buffer that the
15048 * command's response data will be written. This can be either a host
15049 * physical address (HPA) or a guest physical address (GPA) and must
15050 * point to a physically contiguous block of memory.
15052 uint64_t resp_addr;
15055 * # If this bit is set to '1', the query will contain PF(s)
15056 * belongs to SOC host.
15058 #define HWRM_FUNC_HOST_PF_IDS_QUERY_INPUT_HOST_SOC UINT32_C(0x1)
15060 * # If this bit is set to '1', the query will contain PF(s)
15061 * belongs to EP0 host.
15063 #define HWRM_FUNC_HOST_PF_IDS_QUERY_INPUT_HOST_EP_0 UINT32_C(0x2)
15065 * # If this bit is set to '1', the query will contain PF(s)
15066 * belongs to EP1 host.
15068 #define HWRM_FUNC_HOST_PF_IDS_QUERY_INPUT_HOST_EP_1 UINT32_C(0x4)
15070 * # If this bit is set to '1', the query will contain PF(s)
15071 * belongs to EP2 host.
15073 #define HWRM_FUNC_HOST_PF_IDS_QUERY_INPUT_HOST_EP_2 UINT32_C(0x8)
15075 * # If this bit is set to '1', the query will contain PF(s)
15076 * belongs to EP3 host.
15078 #define HWRM_FUNC_HOST_PF_IDS_QUERY_INPUT_HOST_EP_3 UINT32_C(0x10)
15080 * This provides a filter of what PF(s) will be returned in the
15085 * all available PF(s) belong to the host(s) (defined in the
15086 * host field). This includes the hidden PFs.
15088 #define HWRM_FUNC_HOST_PF_IDS_QUERY_INPUT_FILTER_ALL UINT32_C(0x0)
15090 * all available PF(s) belong to the host(s) (defined in the
15091 * host field) that is available for L2 traffic.
15093 #define HWRM_FUNC_HOST_PF_IDS_QUERY_INPUT_FILTER_L2 UINT32_C(0x1)
15095 * all available PF(s) belong to the host(s) (defined in the
15096 * host field) that is available for ROCE traffic.
15098 #define HWRM_FUNC_HOST_PF_IDS_QUERY_INPUT_FILTER_ROCE UINT32_C(0x2)
15099 #define HWRM_FUNC_HOST_PF_IDS_QUERY_INPUT_FILTER_LAST \
15100 HWRM_FUNC_HOST_PF_IDS_QUERY_INPUT_FILTER_ROCE
15101 uint8_t unused_1[6];
15104 /* hwrm_func_host_pf_ids_query_output (size:128b/16B) */
15105 struct hwrm_func_host_pf_ids_query_output {
15106 /* The specific error status for the command. */
15107 uint16_t error_code;
15108 /* The HWRM command request type. */
15110 /* The sequence ID from the original command. */
15112 /* The length of the response data in number of bytes. */
15114 /* This provides the first PF ID of the device. */
15115 uint16_t first_pf_id;
15116 uint16_t pf_ordinal_mask;
15118 * When this bit is '1', it indicates first PF belongs to one of
15119 * the hosts defined in the input request.
15121 #define HWRM_FUNC_HOST_PF_IDS_QUERY_OUTPUT_PF_ORDINAL_MASK_FUNC_0 \
15124 * When this bit is '1', it indicates 2nd PF belongs to one of the
15125 * hosts defined in the input request.
15127 #define HWRM_FUNC_HOST_PF_IDS_QUERY_OUTPUT_PF_ORDINAL_MASK_FUNC_1 \
15130 * When this bit is '1', it indicates 3rd PF belongs to one of the
15131 * hosts defined in the input request.
15133 #define HWRM_FUNC_HOST_PF_IDS_QUERY_OUTPUT_PF_ORDINAL_MASK_FUNC_2 \
15136 * When this bit is '1', it indicates 4th PF belongs to one of the
15137 * hosts defined in the input request.
15139 #define HWRM_FUNC_HOST_PF_IDS_QUERY_OUTPUT_PF_ORDINAL_MASK_FUNC_3 \
15142 * When this bit is '1', it indicates 5th PF belongs to one of the
15143 * hosts defined in the input request.
15145 #define HWRM_FUNC_HOST_PF_IDS_QUERY_OUTPUT_PF_ORDINAL_MASK_FUNC_4 \
15148 * When this bit is '1', it indicates 6th PF belongs to one of the
15149 * hosts defined in the input request.
15151 #define HWRM_FUNC_HOST_PF_IDS_QUERY_OUTPUT_PF_ORDINAL_MASK_FUNC_5 \
15154 * When this bit is '1', it indicates 7th PF belongs to one of the
15155 * hosts defined in the input request.
15157 #define HWRM_FUNC_HOST_PF_IDS_QUERY_OUTPUT_PF_ORDINAL_MASK_FUNC_6 \
15160 * When this bit is '1', it indicates 8th PF belongs to one of the
15161 * hosts defined in the input request.
15163 #define HWRM_FUNC_HOST_PF_IDS_QUERY_OUTPUT_PF_ORDINAL_MASK_FUNC_7 \
15166 * When this bit is '1', it indicates 9th PF belongs to one of the
15167 * hosts defined in the input request.
15169 #define HWRM_FUNC_HOST_PF_IDS_QUERY_OUTPUT_PF_ORDINAL_MASK_FUNC_8 \
15172 * When this bit is '1', it indicates 10th PF belongs to one of the
15173 * hosts defined in the input request.
15175 #define HWRM_FUNC_HOST_PF_IDS_QUERY_OUTPUT_PF_ORDINAL_MASK_FUNC_9 \
15178 * When this bit is '1', it indicates 11th PF belongs to one of the
15179 * hosts defined in the input request.
15181 #define HWRM_FUNC_HOST_PF_IDS_QUERY_OUTPUT_PF_ORDINAL_MASK_FUNC_10 \
15184 * When this bit is '1', it indicates 12th PF belongs to one of the
15185 * hosts defined in the input request.
15187 #define HWRM_FUNC_HOST_PF_IDS_QUERY_OUTPUT_PF_ORDINAL_MASK_FUNC_11 \
15190 * When this bit is '1', it indicates 13th PF belongs to one of the
15191 * hosts defined in the input request.
15193 #define HWRM_FUNC_HOST_PF_IDS_QUERY_OUTPUT_PF_ORDINAL_MASK_FUNC_12 \
15196 * When this bit is '1', it indicates 14th PF belongs to one of the
15197 * hosts defined in the input request.
15199 #define HWRM_FUNC_HOST_PF_IDS_QUERY_OUTPUT_PF_ORDINAL_MASK_FUNC_13 \
15202 * When this bit is '1', it indicates 15th PF belongs to one of the
15203 * hosts defined in the input request.
15205 #define HWRM_FUNC_HOST_PF_IDS_QUERY_OUTPUT_PF_ORDINAL_MASK_FUNC_14 \
15208 * When this bit is '1', it indicates 16th PF belongs to one of the
15209 * hosts defined in the input request.
15211 #define HWRM_FUNC_HOST_PF_IDS_QUERY_OUTPUT_PF_ORDINAL_MASK_FUNC_15 \
15213 uint8_t unused_1[3];
15215 * This field is used in Output records to indicate that the output
15216 * is completely written to RAM. This field should be read as '1'
15217 * to indicate that the output has been completely written.
15218 * When writing a command completion or response to an internal processor,
15219 * the order of writes has to be such that this field is written last.
15224 /*********************
15225 * hwrm_port_phy_cfg *
15226 *********************/
15229 /* hwrm_port_phy_cfg_input (size:448b/56B) */
15230 struct hwrm_port_phy_cfg_input {
15231 /* The HWRM command request type. */
15234 * The completion ring to send the completion event on. This should
15235 * be the NQ ID returned from the `nq_alloc` HWRM command.
15237 uint16_t cmpl_ring;
15239 * The sequence ID is used by the driver for tracking multiple
15240 * commands. This ID is treated as opaque data by the firmware and
15241 * the value is returned in the `hwrm_resp_hdr` upon completion.
15245 * The target ID of the command:
15246 * * 0x0-0xFFF8 - The function ID
15247 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
15248 * * 0xFFFD - Reserved for user-space HWRM interface
15251 uint16_t target_id;
15253 * A physical address pointer pointing to a host buffer that the
15254 * command's response data will be written. This can be either a host
15255 * physical address (HPA) or a guest physical address (GPA) and must
15256 * point to a physically contiguous block of memory.
15258 uint64_t resp_addr;
15261 * When this bit is set to '1', the PHY for the port shall
15264 * # If this bit is set to 1, then the HWRM shall reset the
15265 * PHY after applying PHY configuration changes specified
15267 * # In order to guarantee that PHY configuration changes
15268 * specified in this command take effect, the HWRM
15269 * client should set this flag to 1.
15270 * # If this bit is not set to 1, then the HWRM may reset
15271 * the PHY depending on the current PHY configuration and
15272 * settings specified in this command.
15274 #define HWRM_PORT_PHY_CFG_INPUT_FLAGS_RESET_PHY \
15276 /* deprecated bit. Do not use!!! */
15277 #define HWRM_PORT_PHY_CFG_INPUT_FLAGS_DEPRECATED \
15280 * When this bit is set to '1', and the force_pam4_link_speed
15281 * bit in the 'enables' field is '0', the link shall be forced
15282 * to the force_link_speed value.
15284 * When this bit is set to '1', and the force_pam4_link_speed
15285 * bit in the 'enables' field is '1', the link shall be forced
15286 * to the force_pam4_link_speed value.
15288 * When this bit is set to '1', the HWRM client should
15289 * not enable any of the auto negotiation related
15290 * fields represented by auto_XXX fields in this command.
15291 * When this bit is set to '1' and the HWRM client has
15292 * enabled a auto_XXX field in this command, then the
15293 * HWRM shall ignore the enabled auto_XXX field.
15295 * When this bit is set to zero, the link
15296 * shall be allowed to autoneg.
15298 #define HWRM_PORT_PHY_CFG_INPUT_FLAGS_FORCE \
15301 * When this bit is set to '1', the auto-negotiation process
15302 * shall be restarted on the link.
15304 #define HWRM_PORT_PHY_CFG_INPUT_FLAGS_RESTART_AUTONEG \
15307 * When this bit is set to '1', Energy Efficient Ethernet
15308 * (EEE) is requested to be enabled on this link.
15309 * If EEE is not supported on this port, then this flag
15310 * shall be ignored by the HWRM.
15312 #define HWRM_PORT_PHY_CFG_INPUT_FLAGS_EEE_ENABLE \
15315 * When this bit is set to '1', Energy Efficient Ethernet
15316 * (EEE) is requested to be disabled on this link.
15317 * If EEE is not supported on this port, then this flag
15318 * shall be ignored by the HWRM.
15320 #define HWRM_PORT_PHY_CFG_INPUT_FLAGS_EEE_DISABLE \
15323 * When this bit is set to '1' and EEE is enabled on this
15324 * link, then TX LPI is requested to be enabled on the link.
15325 * If EEE is not supported on this port, then this flag
15326 * shall be ignored by the HWRM.
15327 * If EEE is disabled on this port, then this flag shall be
15328 * ignored by the HWRM.
15330 #define HWRM_PORT_PHY_CFG_INPUT_FLAGS_EEE_TX_LPI_ENABLE \
15333 * When this bit is set to '1' and EEE is enabled on this
15334 * link, then TX LPI is requested to be disabled on the link.
15335 * If EEE is not supported on this port, then this flag
15336 * shall be ignored by the HWRM.
15337 * If EEE is disabled on this port, then this flag shall be
15338 * ignored by the HWRM.
15340 #define HWRM_PORT_PHY_CFG_INPUT_FLAGS_EEE_TX_LPI_DISABLE \
15343 * When set to 1, then the HWRM shall enable FEC autonegotitation
15344 * on this port if supported. When enabled, at least one of the
15345 * FEC modes must be advertised by enabling the fec_clause_74_enable,
15346 * fec_clause_91_enable, fec_rs544_1xn_enable, or fec_rs544_2xn_enable
15347 * flag. If none of the FEC mode is currently enabled, the HWRM
15348 * shall choose a default advertisement setting.
15349 * The default advertisement setting can be queried by calling
15350 * hwrm_port_phy_qcfg. Note that the link speed must be
15351 * in autonegotiation mode for FEC autonegotiation to take effect.
15352 * When set to 0, then this flag shall be ignored.
15353 * If FEC autonegotiation is not supported, then the HWRM shall ignore this
15356 #define HWRM_PORT_PHY_CFG_INPUT_FLAGS_FEC_AUTONEG_ENABLE \
15359 * When set to 1, then the HWRM shall disable FEC autonegotiation
15360 * on this port if supported.
15361 * When set to 0, then this flag shall be ignored.
15362 * If FEC autonegotiation is not supported, then the HWRM shall ignore this
15365 #define HWRM_PORT_PHY_CFG_INPUT_FLAGS_FEC_AUTONEG_DISABLE \
15368 * When set to 1, then the HWRM shall enable FEC CLAUSE 74 (Fire Code)
15369 * on this port if supported, by advertising FEC CLAUSE 74 if
15370 * FEC autonegotiation is enabled or force enabled otherwise.
15371 * When set to 0, then this flag shall be ignored.
15372 * If FEC CLAUSE 74 is not supported, then the HWRM shall ignore this
15375 #define HWRM_PORT_PHY_CFG_INPUT_FLAGS_FEC_CLAUSE74_ENABLE \
15378 * When set to 1, then the HWRM shall disable FEC CLAUSE 74 (Fire Code)
15379 * on this port if supported, by not advertising FEC CLAUSE 74 if
15380 * FEC autonegotiation is enabled or force disabled otherwise.
15381 * When set to 0, then this flag shall be ignored.
15382 * If FEC CLAUSE 74 is not supported, then the HWRM shall ignore this
15385 #define HWRM_PORT_PHY_CFG_INPUT_FLAGS_FEC_CLAUSE74_DISABLE \
15388 * When set to 1, then the HWRM shall enable FEC CLAUSE 91 (Reed Solomon)
15389 * on this port if supported, by advertising FEC CLAUSE 91 if
15390 * FEC autonegotiation is enabled or force enabled otherwise.
15391 * When set to 0, then this flag shall be ignored.
15392 * If FEC CLAUSE 91 is not supported, then the HWRM shall ignore this
15395 #define HWRM_PORT_PHY_CFG_INPUT_FLAGS_FEC_CLAUSE91_ENABLE \
15398 * When set to 1, then the HWRM shall disable FEC CLAUSE 91 (Reed Solomon)
15399 * on this port if supported, by not advertising FEC CLAUSE 91 if
15400 * FEC autonegotiation is enabled or force disabled otherwise.
15401 * When set to 0, then this flag shall be ignored.
15402 * If FEC CLAUSE 91 is not supported, then the HWRM shall ignore this
15405 #define HWRM_PORT_PHY_CFG_INPUT_FLAGS_FEC_CLAUSE91_DISABLE \
15408 * When this bit is set to '1', the link shall be forced to
15411 * # When this bit is set to '1", all other
15412 * command input settings related to the link speed shall
15414 * Once the link state is forced down, it can be
15415 * explicitly cleared from that state by setting this flag
15417 * # If this flag is set to '0', then the link shall be
15418 * cleared from forced down state if the link is in forced
15420 * There may be conditions (e.g. out-of-band or sideband
15421 * configuration changes for the link) outside the scope
15422 * of the HWRM implementation that may clear forced down
15425 #define HWRM_PORT_PHY_CFG_INPUT_FLAGS_FORCE_LINK_DWN \
15428 * When set to 1, then the HWRM shall enable FEC RS544_1XN
15429 * on this port if supported, by advertising FEC RS544_1XN if
15430 * FEC autonegotiation is enabled or force enabled otherwise.
15431 * When set to 0, then this flag shall be ignored.
15432 * If FEC RS544_1XN is not supported, then the HWRM shall ignore this
15435 #define HWRM_PORT_PHY_CFG_INPUT_FLAGS_FEC_RS544_1XN_ENABLE \
15438 * When set to 1, then the HWRM shall disable FEC RS544_1XN
15439 * on this port if supported, by not advertising FEC RS544_1XN if
15440 * FEC autonegotiation is enabled or force disabled otherwise.
15441 * When set to 0, then this flag shall be ignored.
15442 * If FEC RS544_1XN is not supported, then the HWRM shall ignore this
15445 #define HWRM_PORT_PHY_CFG_INPUT_FLAGS_FEC_RS544_1XN_DISABLE \
15448 * When set to 1, then the HWRM shall enable FEC RS544_2XN
15449 * on this port if supported, by advertising FEC RS544_2XN if
15450 * FEC autonegotiation is enabled or force enabled otherwise.
15451 * When set to 0, then this flag shall be ignored.
15452 * If FEC RS544_2XN is not supported, then the HWRM shall ignore this
15455 #define HWRM_PORT_PHY_CFG_INPUT_FLAGS_FEC_RS544_2XN_ENABLE \
15458 * When set to 1, then the HWRM shall disable FEC RS544_2XN
15459 * on this port if supported, by not advertising FEC RS544_2XN if
15460 * FEC autonegotiation is enabled or force disabled otherwise.
15461 * When set to 0, then this flag shall be ignored.
15462 * If FEC RS544_2XN is not supported, then the HWRM shall ignore this
15465 #define HWRM_PORT_PHY_CFG_INPUT_FLAGS_FEC_RS544_2XN_DISABLE \
15469 * This bit must be '1' for the auto_mode field to be
15472 #define HWRM_PORT_PHY_CFG_INPUT_ENABLES_AUTO_MODE \
15475 * This bit must be '1' for the auto_duplex field to be
15478 #define HWRM_PORT_PHY_CFG_INPUT_ENABLES_AUTO_DUPLEX \
15481 * This bit must be '1' for the auto_pause field to be
15484 #define HWRM_PORT_PHY_CFG_INPUT_ENABLES_AUTO_PAUSE \
15487 * This bit must be '1' for the auto_link_speed field to be
15490 #define HWRM_PORT_PHY_CFG_INPUT_ENABLES_AUTO_LINK_SPEED \
15493 * This bit must be '1' for the auto_link_speed_mask field to be
15496 #define HWRM_PORT_PHY_CFG_INPUT_ENABLES_AUTO_LINK_SPEED_MASK \
15499 * This bit must be '1' for the wirespeed field to be
15502 #define HWRM_PORT_PHY_CFG_INPUT_ENABLES_WIRESPEED \
15505 * This bit must be '1' for the lpbk field to be
15508 #define HWRM_PORT_PHY_CFG_INPUT_ENABLES_LPBK \
15511 * This bit must be '1' for the preemphasis field to be
15514 #define HWRM_PORT_PHY_CFG_INPUT_ENABLES_PREEMPHASIS \
15517 * This bit must be '1' for the force_pause field to be
15520 #define HWRM_PORT_PHY_CFG_INPUT_ENABLES_FORCE_PAUSE \
15523 * This bit must be '1' for the eee_link_speed_mask field to be
15526 #define HWRM_PORT_PHY_CFG_INPUT_ENABLES_EEE_LINK_SPEED_MASK \
15529 * This bit must be '1' for the tx_lpi_timer field to be
15532 #define HWRM_PORT_PHY_CFG_INPUT_ENABLES_TX_LPI_TIMER \
15534 /* Port ID of port that is to be configured. */
15537 * This is the speed that will be used if the force
15538 * bit is '1'. If unsupported speed is selected, an error
15539 * will be generated.
15541 uint16_t force_link_speed;
15542 /* 100Mb link speed */
15543 #define HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_100MB UINT32_C(0x1)
15544 /* 1Gb link speed */
15545 #define HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_1GB UINT32_C(0xa)
15546 /* 2Gb link speed */
15547 #define HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_2GB UINT32_C(0x14)
15548 /* 25Gb link speed */
15549 #define HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_2_5GB UINT32_C(0x19)
15550 /* 10Gb link speed */
15551 #define HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_10GB UINT32_C(0x64)
15552 /* 20Mb link speed */
15553 #define HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_20GB UINT32_C(0xc8)
15554 /* 25Gb link speed */
15555 #define HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_25GB UINT32_C(0xfa)
15556 /* 40Gb link speed */
15557 #define HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_40GB UINT32_C(0x190)
15558 /* 50Gb link speed */
15559 #define HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_50GB UINT32_C(0x1f4)
15560 /* 100Gb link speed */
15561 #define HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_100GB UINT32_C(0x3e8)
15562 /* 200Gb link speed */
15563 #define HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_200GB UINT32_C(0x7d0)
15564 /* 10Mb link speed */
15565 #define HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_10MB UINT32_C(0xffff)
15566 #define HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_LAST \
15567 HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_10MB
15569 * This value is used to identify what autoneg mode is
15570 * used when the link speed is not being forced.
15573 /* Disable autoneg or autoneg disabled. No speeds are selected. */
15574 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_MODE_NONE UINT32_C(0x0)
15575 /* Select all possible speeds for autoneg mode. */
15576 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_MODE_ALL_SPEEDS UINT32_C(0x1)
15578 * Select only the auto_link_speed speed for autoneg mode. This mode has
15579 * been DEPRECATED. An HWRM client should not use this mode.
15581 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_MODE_ONE_SPEED UINT32_C(0x2)
15583 * Select the auto_link_speed or any speed below that speed for autoneg.
15584 * This mode has been DEPRECATED. An HWRM client should not use this mode.
15586 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_MODE_ONE_OR_BELOW UINT32_C(0x3)
15588 * Select the speeds based on the corresponding link speed mask value
15589 * that is provided.
15591 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_MODE_SPEED_MASK UINT32_C(0x4)
15592 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_MODE_LAST \
15593 HWRM_PORT_PHY_CFG_INPUT_AUTO_MODE_SPEED_MASK
15595 * This is the duplex setting that will be used if the autoneg_mode
15596 * is "one_speed" or "one_or_below".
15598 uint8_t auto_duplex;
15599 /* Half Duplex will be requested. */
15600 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_HALF UINT32_C(0x0)
15601 /* Full duplex will be requested. */
15602 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_FULL UINT32_C(0x1)
15603 /* Both Half and Full dupex will be requested. */
15604 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_BOTH UINT32_C(0x2)
15605 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_LAST \
15606 HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_BOTH
15608 * This value is used to configure the pause that will be
15609 * used for autonegotiation.
15610 * Add text on the usage of auto_pause and force_pause.
15612 uint8_t auto_pause;
15614 * When this bit is '1', Generation of tx pause messages
15615 * has been requested. Disabled otherwise.
15617 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_TX \
15620 * When this bit is '1', Reception of rx pause messages
15621 * has been requested. Disabled otherwise.
15623 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_RX \
15626 * When set to 1, the advertisement of pause is enabled.
15628 * # When the auto_mode is not set to none and this flag is
15629 * set to 1, then the auto_pause bits on this port are being
15630 * advertised and autoneg pause results are being interpreted.
15631 * # When the auto_mode is not set to none and this
15632 * flag is set to 0, the pause is forced as indicated in
15633 * force_pause, and also advertised as auto_pause bits, but
15634 * the autoneg results are not interpreted since the pause
15635 * configuration is being forced.
15636 * # When the auto_mode is set to none and this flag is set to
15637 * 1, auto_pause bits should be ignored and should be set to 0.
15639 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_AUTONEG_PAUSE \
15643 * This is the speed that will be used if the autoneg_mode
15644 * is "one_speed" or "one_or_below". If an unsupported speed
15645 * is selected, an error will be generated.
15647 uint16_t auto_link_speed;
15648 /* 100Mb link speed */
15649 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_100MB UINT32_C(0x1)
15650 /* 1Gb link speed */
15651 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_1GB UINT32_C(0xa)
15652 /* 2Gb link speed */
15653 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_2GB UINT32_C(0x14)
15654 /* 25Gb link speed */
15655 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_2_5GB UINT32_C(0x19)
15656 /* 10Gb link speed */
15657 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_10GB UINT32_C(0x64)
15658 /* 20Mb link speed */
15659 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_20GB UINT32_C(0xc8)
15660 /* 25Gb link speed */
15661 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_25GB UINT32_C(0xfa)
15662 /* 40Gb link speed */
15663 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_40GB UINT32_C(0x190)
15664 /* 50Gb link speed */
15665 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_50GB UINT32_C(0x1f4)
15666 /* 100Gb link speed */
15667 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_100GB UINT32_C(0x3e8)
15668 /* 200Gb link speed */
15669 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_200GB UINT32_C(0x7d0)
15670 /* 10Mb link speed */
15671 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_10MB UINT32_C(0xffff)
15672 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_LAST \
15673 HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_10MB
15675 * This is a mask of link speeds that will be used if
15676 * autoneg_mode is "mask". If unsupported speed is enabled
15677 * an error will be generated.
15679 uint16_t auto_link_speed_mask;
15680 /* 100Mb link speed (Half-duplex) */
15681 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_100MBHD \
15683 /* 100Mb link speed (Full-duplex) */
15684 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_100MB \
15686 /* 1Gb link speed (Half-duplex) */
15687 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_1GBHD \
15689 /* 1Gb link speed (Full-duplex) */
15690 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_1GB \
15692 /* 2Gb link speed */
15693 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_2GB \
15695 /* 25Gb link speed */
15696 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_2_5GB \
15698 /* 10Gb link speed */
15699 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_10GB \
15701 /* 20Gb link speed */
15702 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_20GB \
15704 /* 25Gb link speed */
15705 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_25GB \
15707 /* 40Gb link speed */
15708 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_40GB \
15710 /* 50Gb link speed */
15711 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_50GB \
15713 /* 100Gb link speed */
15714 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_100GB \
15716 /* 10Mb link speed (Half-duplex) */
15717 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_10MBHD \
15719 /* 10Mb link speed (Full-duplex) */
15720 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_10MB \
15722 /* 200Gb link speed */
15723 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_200GB \
15725 /* This value controls the wirespeed feature. */
15727 /* Wirespeed feature is disabled. */
15728 #define HWRM_PORT_PHY_CFG_INPUT_WIRESPEED_OFF UINT32_C(0x0)
15729 /* Wirespeed feature is enabled. */
15730 #define HWRM_PORT_PHY_CFG_INPUT_WIRESPEED_ON UINT32_C(0x1)
15731 #define HWRM_PORT_PHY_CFG_INPUT_WIRESPEED_LAST \
15732 HWRM_PORT_PHY_CFG_INPUT_WIRESPEED_ON
15733 /* This value controls the loopback setting for the PHY. */
15735 /* No loopback is selected. Normal operation. */
15736 #define HWRM_PORT_PHY_CFG_INPUT_LPBK_NONE UINT32_C(0x0)
15738 * The HW will be configured with local loopback such that
15739 * host data is sent back to the host without modification.
15741 #define HWRM_PORT_PHY_CFG_INPUT_LPBK_LOCAL UINT32_C(0x1)
15743 * The HW will be configured with remote loopback such that
15744 * port logic will send packets back out the transmitter that
15747 #define HWRM_PORT_PHY_CFG_INPUT_LPBK_REMOTE UINT32_C(0x2)
15749 * The HW will be configured with external loopback such that
15750 * host data is sent on the transmitter and based on the external
15751 * loopback connection the data will be received without modification.
15753 #define HWRM_PORT_PHY_CFG_INPUT_LPBK_EXTERNAL UINT32_C(0x3)
15754 #define HWRM_PORT_PHY_CFG_INPUT_LPBK_LAST \
15755 HWRM_PORT_PHY_CFG_INPUT_LPBK_EXTERNAL
15757 * This value is used to configure the pause that will be
15758 * used for force mode.
15760 uint8_t force_pause;
15762 * When this bit is '1', Generation of tx pause messages
15763 * is supported. Disabled otherwise.
15765 #define HWRM_PORT_PHY_CFG_INPUT_FORCE_PAUSE_TX UINT32_C(0x1)
15767 * When this bit is '1', Reception of rx pause messages
15768 * is supported. Disabled otherwise.
15770 #define HWRM_PORT_PHY_CFG_INPUT_FORCE_PAUSE_RX UINT32_C(0x2)
15773 * This value controls the pre-emphasis to be used for the
15774 * link. Driver should not set this value (use
15775 * enable.preemphasis = 0) unless driver is sure of setting.
15776 * Normally HWRM FW will determine proper pre-emphasis.
15778 uint32_t preemphasis;
15780 * Setting for link speed mask that is used to
15781 * advertise speeds during autonegotiation when EEE is enabled.
15782 * This field is valid only when EEE is enabled.
15783 * The speeds specified in this field shall be a subset of
15784 * speeds specified in auto_link_speed_mask.
15785 * If EEE is enabled,then at least one speed shall be provided
15788 uint16_t eee_link_speed_mask;
15790 #define HWRM_PORT_PHY_CFG_INPUT_EEE_LINK_SPEED_MASK_RSVD1 \
15792 /* 100Mb link speed (Full-duplex) */
15793 #define HWRM_PORT_PHY_CFG_INPUT_EEE_LINK_SPEED_MASK_100MB \
15796 #define HWRM_PORT_PHY_CFG_INPUT_EEE_LINK_SPEED_MASK_RSVD2 \
15798 /* 1Gb link speed (Full-duplex) */
15799 #define HWRM_PORT_PHY_CFG_INPUT_EEE_LINK_SPEED_MASK_1GB \
15802 #define HWRM_PORT_PHY_CFG_INPUT_EEE_LINK_SPEED_MASK_RSVD3 \
15805 #define HWRM_PORT_PHY_CFG_INPUT_EEE_LINK_SPEED_MASK_RSVD4 \
15807 /* 10Gb link speed */
15808 #define HWRM_PORT_PHY_CFG_INPUT_EEE_LINK_SPEED_MASK_10GB \
15811 * This is the speed that will be used if the force and force_pam4
15812 * bits are '1'. If unsupported speed is selected, an error
15813 * will be generated.
15815 uint16_t force_pam4_link_speed;
15816 /* 50Gb link speed */
15817 #define HWRM_PORT_PHY_CFG_INPUT_FORCE_PAM4_LINK_SPEED_50GB \
15819 /* 100Gb link speed */
15820 #define HWRM_PORT_PHY_CFG_INPUT_FORCE_PAM4_LINK_SPEED_100GB \
15822 /* 200Gb link speed */
15823 #define HWRM_PORT_PHY_CFG_INPUT_FORCE_PAM4_LINK_SPEED_200GB \
15825 #define HWRM_PORT_PHY_CFG_INPUT_FORCE_PAM4_LINK_SPEED_LAST \
15826 HWRM_PORT_PHY_CFG_INPUT_FORCE_PAM4_LINK_SPEED_200GB
15828 * Requested setting of TX LPI timer in microseconds.
15829 * This field is valid only when EEE is enabled and TX LPI is
15832 uint32_t tx_lpi_timer;
15833 #define HWRM_PORT_PHY_CFG_INPUT_TX_LPI_TIMER_MASK UINT32_C(0xffffff)
15834 #define HWRM_PORT_PHY_CFG_INPUT_TX_LPI_TIMER_SFT 0
15838 /* hwrm_port_phy_cfg_output (size:128b/16B) */
15839 struct hwrm_port_phy_cfg_output {
15840 /* The specific error status for the command. */
15841 uint16_t error_code;
15842 /* The HWRM command request type. */
15844 /* The sequence ID from the original command. */
15846 /* The length of the response data in number of bytes. */
15848 uint8_t unused_0[7];
15850 * This field is used in Output records to indicate that the output
15851 * is completely written to RAM. This field should be read as '1'
15852 * to indicate that the output has been completely written.
15853 * When writing a command completion or response to an internal processor,
15854 * the order of writes has to be such that this field is written last.
15859 /* hwrm_port_phy_cfg_cmd_err (size:64b/8B) */
15860 struct hwrm_port_phy_cfg_cmd_err {
15862 * command specific error codes that goes to
15863 * the cmd_err field in Common HWRM Error Response.
15866 /* Unknown error */
15867 #define HWRM_PORT_PHY_CFG_CMD_ERR_CODE_UNKNOWN UINT32_C(0x0)
15868 /* Unable to complete operation due to invalid speed */
15869 #define HWRM_PORT_PHY_CFG_CMD_ERR_CODE_ILLEGAL_SPEED UINT32_C(0x1)
15871 * retry the command since the phy is not ready.
15872 * retry count is returned in opaque_0.
15873 * This is only valid for the first command and
15874 * this value will not change for successive calls.
15875 * but if a 0 is returned at any time then this should
15876 * be treated as an un recoverable failure,
15878 * retry interval in milli seconds is returned in opaque_1.
15879 * This specifies the time that user should wait before
15880 * issuing the next port_phy_cfg command.
15882 #define HWRM_PORT_PHY_CFG_CMD_ERR_CODE_RETRY UINT32_C(0x2)
15883 #define HWRM_PORT_PHY_CFG_CMD_ERR_CODE_LAST \
15884 HWRM_PORT_PHY_CFG_CMD_ERR_CODE_RETRY
15885 uint8_t unused_0[7];
15888 /**********************
15889 * hwrm_port_phy_qcfg *
15890 **********************/
15893 /* hwrm_port_phy_qcfg_input (size:192b/24B) */
15894 struct hwrm_port_phy_qcfg_input {
15895 /* The HWRM command request type. */
15898 * The completion ring to send the completion event on. This should
15899 * be the NQ ID returned from the `nq_alloc` HWRM command.
15901 uint16_t cmpl_ring;
15903 * The sequence ID is used by the driver for tracking multiple
15904 * commands. This ID is treated as opaque data by the firmware and
15905 * the value is returned in the `hwrm_resp_hdr` upon completion.
15909 * The target ID of the command:
15910 * * 0x0-0xFFF8 - The function ID
15911 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
15912 * * 0xFFFD - Reserved for user-space HWRM interface
15915 uint16_t target_id;
15917 * A physical address pointer pointing to a host buffer that the
15918 * command's response data will be written. This can be either a host
15919 * physical address (HPA) or a guest physical address (GPA) and must
15920 * point to a physically contiguous block of memory.
15922 uint64_t resp_addr;
15923 /* Port ID of port that is to be queried. */
15925 uint8_t unused_0[6];
15928 /* hwrm_port_phy_qcfg_output (size:768b/96B) */
15929 struct hwrm_port_phy_qcfg_output {
15930 /* The specific error status for the command. */
15931 uint16_t error_code;
15932 /* The HWRM command request type. */
15934 /* The sequence ID from the original command. */
15936 /* The length of the response data in number of bytes. */
15938 /* This value indicates the current link status. */
15940 /* There is no link or cable detected. */
15941 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_NO_LINK UINT32_C(0x0)
15942 /* There is no link, but a cable has been detected. */
15943 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SIGNAL UINT32_C(0x1)
15944 /* There is a link. */
15945 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_LINK UINT32_C(0x2)
15946 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_LAST \
15947 HWRM_PORT_PHY_QCFG_OUTPUT_LINK_LINK
15949 /* This value indicates the current link speed of the connection. */
15950 uint16_t link_speed;
15951 /* 100Mb link speed */
15952 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_100MB UINT32_C(0x1)
15953 /* 1Gb link speed */
15954 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_1GB UINT32_C(0xa)
15955 /* 2Gb link speed */
15956 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_2GB UINT32_C(0x14)
15957 /* 25Gb link speed */
15958 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_2_5GB UINT32_C(0x19)
15959 /* 10Gb link speed */
15960 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_10GB UINT32_C(0x64)
15961 /* 20Mb link speed */
15962 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_20GB UINT32_C(0xc8)
15963 /* 25Gb link speed */
15964 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_25GB UINT32_C(0xfa)
15965 /* 40Gb link speed */
15966 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_40GB UINT32_C(0x190)
15967 /* 50Gb link speed */
15968 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_50GB UINT32_C(0x1f4)
15969 /* 100Gb link speed */
15970 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_100GB UINT32_C(0x3e8)
15971 /* 200Gb link speed */
15972 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_200GB UINT32_C(0x7d0)
15973 /* 10Mb link speed */
15974 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_10MB UINT32_C(0xffff)
15975 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_LAST \
15976 HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_10MB
15978 * This value is indicates the duplex of the current
15981 uint8_t duplex_cfg;
15982 /* Half Duplex connection. */
15983 #define HWRM_PORT_PHY_QCFG_OUTPUT_DUPLEX_CFG_HALF UINT32_C(0x0)
15984 /* Full duplex connection. */
15985 #define HWRM_PORT_PHY_QCFG_OUTPUT_DUPLEX_CFG_FULL UINT32_C(0x1)
15986 #define HWRM_PORT_PHY_QCFG_OUTPUT_DUPLEX_CFG_LAST \
15987 HWRM_PORT_PHY_QCFG_OUTPUT_DUPLEX_CFG_FULL
15989 * This value is used to indicate the current
15990 * pause configuration. When autoneg is enabled, this value
15991 * represents the autoneg results of pause configuration.
15995 * When this bit is '1', Generation of tx pause messages
15996 * is supported. Disabled otherwise.
15998 #define HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_TX UINT32_C(0x1)
16000 * When this bit is '1', Reception of rx pause messages
16001 * is supported. Disabled otherwise.
16003 #define HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_RX UINT32_C(0x2)
16005 * The supported speeds for the port. This is a bit mask.
16006 * For each speed that is supported, the corrresponding
16007 * bit will be set to '1'.
16009 uint16_t support_speeds;
16010 /* 100Mb link speed (Half-duplex) */
16011 #define HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_100MBHD \
16013 /* 100Mb link speed (Full-duplex) */
16014 #define HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_100MB \
16016 /* 1Gb link speed (Half-duplex) */
16017 #define HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_1GBHD \
16019 /* 1Gb link speed (Full-duplex) */
16020 #define HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_1GB \
16022 /* 2Gb link speed */
16023 #define HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_2GB \
16025 /* 25Gb link speed */
16026 #define HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_2_5GB \
16028 /* 10Gb link speed */
16029 #define HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_10GB \
16031 /* 20Gb link speed */
16032 #define HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_20GB \
16034 /* 25Gb link speed */
16035 #define HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_25GB \
16037 /* 40Gb link speed */
16038 #define HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_40GB \
16040 /* 50Gb link speed */
16041 #define HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_50GB \
16043 /* 100Gb link speed */
16044 #define HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_100GB \
16046 /* 10Mb link speed (Half-duplex) */
16047 #define HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_10MBHD \
16049 /* 10Mb link speed (Full-duplex) */
16050 #define HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_10MB \
16052 /* 200Gb link speed */
16053 #define HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_200GB \
16056 * Current setting of forced link speed.
16057 * When the link speed is not being forced, this
16058 * value shall be set to 0.
16060 uint16_t force_link_speed;
16061 /* 100Mb link speed */
16062 #define HWRM_PORT_PHY_QCFG_OUTPUT_FORCE_LINK_SPEED_100MB UINT32_C(0x1)
16063 /* 1Gb link speed */
16064 #define HWRM_PORT_PHY_QCFG_OUTPUT_FORCE_LINK_SPEED_1GB UINT32_C(0xa)
16065 /* 2Gb link speed */
16066 #define HWRM_PORT_PHY_QCFG_OUTPUT_FORCE_LINK_SPEED_2GB UINT32_C(0x14)
16067 /* 25Gb link speed */
16068 #define HWRM_PORT_PHY_QCFG_OUTPUT_FORCE_LINK_SPEED_2_5GB UINT32_C(0x19)
16069 /* 10Gb link speed */
16070 #define HWRM_PORT_PHY_QCFG_OUTPUT_FORCE_LINK_SPEED_10GB UINT32_C(0x64)
16071 /* 20Mb link speed */
16072 #define HWRM_PORT_PHY_QCFG_OUTPUT_FORCE_LINK_SPEED_20GB UINT32_C(0xc8)
16073 /* 25Gb link speed */
16074 #define HWRM_PORT_PHY_QCFG_OUTPUT_FORCE_LINK_SPEED_25GB UINT32_C(0xfa)
16075 /* 40Gb link speed */
16076 #define HWRM_PORT_PHY_QCFG_OUTPUT_FORCE_LINK_SPEED_40GB \
16078 /* 50Gb link speed */
16079 #define HWRM_PORT_PHY_QCFG_OUTPUT_FORCE_LINK_SPEED_50GB \
16081 /* 100Gb link speed */
16082 #define HWRM_PORT_PHY_QCFG_OUTPUT_FORCE_LINK_SPEED_100GB \
16084 /* 200Gb link speed */
16085 #define HWRM_PORT_PHY_QCFG_OUTPUT_FORCE_LINK_SPEED_200GB \
16087 /* 10Mb link speed */
16088 #define HWRM_PORT_PHY_QCFG_OUTPUT_FORCE_LINK_SPEED_10MB \
16090 #define HWRM_PORT_PHY_QCFG_OUTPUT_FORCE_LINK_SPEED_LAST \
16091 HWRM_PORT_PHY_QCFG_OUTPUT_FORCE_LINK_SPEED_10MB
16092 /* Current setting of auto negotiation mode. */
16094 /* Disable autoneg or autoneg disabled. No speeds are selected. */
16095 #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_MODE_NONE UINT32_C(0x0)
16096 /* Select all possible speeds for autoneg mode. */
16097 #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_MODE_ALL_SPEEDS UINT32_C(0x1)
16099 * Select only the auto_link_speed speed for autoneg mode. This mode has
16100 * been DEPRECATED. An HWRM client should not use this mode.
16102 #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_MODE_ONE_SPEED UINT32_C(0x2)
16104 * Select the auto_link_speed or any speed below that speed for autoneg.
16105 * This mode has been DEPRECATED. An HWRM client should not use this mode.
16107 #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_MODE_ONE_OR_BELOW UINT32_C(0x3)
16109 * Select the speeds based on the corresponding link speed mask value
16110 * that is provided.
16112 #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_MODE_SPEED_MASK UINT32_C(0x4)
16113 #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_MODE_LAST \
16114 HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_MODE_SPEED_MASK
16116 * Current setting of pause autonegotiation.
16117 * Move autoneg_pause flag here.
16119 uint8_t auto_pause;
16121 * When this bit is '1', Generation of tx pause messages
16122 * has been requested. Disabled otherwise.
16124 #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_PAUSE_TX \
16127 * When this bit is '1', Reception of rx pause messages
16128 * has been requested. Disabled otherwise.
16130 #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_PAUSE_RX \
16133 * When set to 1, the advertisement of pause is enabled.
16135 * # When the auto_mode is not set to none and this flag is
16136 * set to 1, then the auto_pause bits on this port are being
16137 * advertised and autoneg pause results are being interpreted.
16138 * # When the auto_mode is not set to none and this
16139 * flag is set to 0, the pause is forced as indicated in
16140 * force_pause, and also advertised as auto_pause bits, but
16141 * the autoneg results are not interpreted since the pause
16142 * configuration is being forced.
16143 * # When the auto_mode is set to none and this flag is set to
16144 * 1, auto_pause bits should be ignored and should be set to 0.
16146 #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_PAUSE_AUTONEG_PAUSE \
16149 * Current setting for auto_link_speed. This field is only
16150 * valid when auto_mode is set to "one_speed" or "one_or_below".
16152 uint16_t auto_link_speed;
16153 /* 100Mb link speed */
16154 #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_100MB UINT32_C(0x1)
16155 /* 1Gb link speed */
16156 #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_1GB UINT32_C(0xa)
16157 /* 2Gb link speed */
16158 #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_2GB UINT32_C(0x14)
16159 /* 25Gb link speed */
16160 #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_2_5GB UINT32_C(0x19)
16161 /* 10Gb link speed */
16162 #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_10GB UINT32_C(0x64)
16163 /* 20Mb link speed */
16164 #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_20GB UINT32_C(0xc8)
16165 /* 25Gb link speed */
16166 #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_25GB UINT32_C(0xfa)
16167 /* 40Gb link speed */
16168 #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_40GB UINT32_C(0x190)
16169 /* 50Gb link speed */
16170 #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_50GB UINT32_C(0x1f4)
16171 /* 100Gb link speed */
16172 #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_100GB UINT32_C(0x3e8)
16173 /* 200Gb link speed */
16174 #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_200GB UINT32_C(0x7d0)
16175 /* 10Mb link speed */
16176 #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_10MB \
16178 #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_LAST \
16179 HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_10MB
16181 * Current setting for auto_link_speed_mask that is used to
16182 * advertise speeds during autonegotiation.
16183 * This field is only valid when auto_mode is set to "mask".
16184 * The speeds specified in this field shall be a subset of
16185 * supported speeds on this port.
16187 uint16_t auto_link_speed_mask;
16188 /* 100Mb link speed (Half-duplex) */
16189 #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_MASK_100MBHD \
16191 /* 100Mb link speed (Full-duplex) */
16192 #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_MASK_100MB \
16194 /* 1Gb link speed (Half-duplex) */
16195 #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_MASK_1GBHD \
16197 /* 1Gb link speed (Full-duplex) */
16198 #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_MASK_1GB \
16200 /* 2Gb link speed */
16201 #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_MASK_2GB \
16203 /* 25Gb link speed */
16204 #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_MASK_2_5GB \
16206 /* 10Gb link speed */
16207 #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_MASK_10GB \
16209 /* 20Gb link speed */
16210 #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_MASK_20GB \
16212 /* 25Gb link speed */
16213 #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_MASK_25GB \
16215 /* 40Gb link speed */
16216 #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_MASK_40GB \
16218 /* 50Gb link speed */
16219 #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_MASK_50GB \
16221 /* 100Gb link speed */
16222 #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_MASK_100GB \
16224 /* 10Mb link speed (Half-duplex) */
16225 #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_MASK_10MBHD \
16227 /* 10Mb link speed (Full-duplex) */
16228 #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_MASK_10MB \
16230 /* 200Gb link speed */
16231 #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_MASK_200GB \
16233 /* Current setting for wirespeed. */
16235 /* Wirespeed feature is disabled. */
16236 #define HWRM_PORT_PHY_QCFG_OUTPUT_WIRESPEED_OFF UINT32_C(0x0)
16237 /* Wirespeed feature is enabled. */
16238 #define HWRM_PORT_PHY_QCFG_OUTPUT_WIRESPEED_ON UINT32_C(0x1)
16239 #define HWRM_PORT_PHY_QCFG_OUTPUT_WIRESPEED_LAST \
16240 HWRM_PORT_PHY_QCFG_OUTPUT_WIRESPEED_ON
16241 /* Current setting for loopback. */
16243 /* No loopback is selected. Normal operation. */
16244 #define HWRM_PORT_PHY_QCFG_OUTPUT_LPBK_NONE UINT32_C(0x0)
16246 * The HW will be configured with local loopback such that
16247 * host data is sent back to the host without modification.
16249 #define HWRM_PORT_PHY_QCFG_OUTPUT_LPBK_LOCAL UINT32_C(0x1)
16251 * The HW will be configured with remote loopback such that
16252 * port logic will send packets back out the transmitter that
16255 #define HWRM_PORT_PHY_QCFG_OUTPUT_LPBK_REMOTE UINT32_C(0x2)
16257 * The HW will be configured with external loopback such that
16258 * host data is sent on the transmitter and based on the external
16259 * loopback connection the data will be received without modification.
16261 #define HWRM_PORT_PHY_QCFG_OUTPUT_LPBK_EXTERNAL UINT32_C(0x3)
16262 #define HWRM_PORT_PHY_QCFG_OUTPUT_LPBK_LAST \
16263 HWRM_PORT_PHY_QCFG_OUTPUT_LPBK_EXTERNAL
16265 * Current setting of forced pause.
16266 * When the pause configuration is not being forced, then
16267 * this value shall be set to 0.
16269 uint8_t force_pause;
16271 * When this bit is '1', Generation of tx pause messages
16272 * is supported. Disabled otherwise.
16274 #define HWRM_PORT_PHY_QCFG_OUTPUT_FORCE_PAUSE_TX UINT32_C(0x1)
16276 * When this bit is '1', Reception of rx pause messages
16277 * is supported. Disabled otherwise.
16279 #define HWRM_PORT_PHY_QCFG_OUTPUT_FORCE_PAUSE_RX UINT32_C(0x2)
16281 * This value indicates the current status of the optics module on
16284 uint8_t module_status;
16285 /* Module is inserted and accepted */
16286 #define HWRM_PORT_PHY_QCFG_OUTPUT_MODULE_STATUS_NONE \
16288 /* Module is rejected and transmit side Laser is disabled. */
16289 #define HWRM_PORT_PHY_QCFG_OUTPUT_MODULE_STATUS_DISABLETX \
16291 /* Module mismatch warning. */
16292 #define HWRM_PORT_PHY_QCFG_OUTPUT_MODULE_STATUS_WARNINGMSG \
16294 /* Module is rejected and powered down. */
16295 #define HWRM_PORT_PHY_QCFG_OUTPUT_MODULE_STATUS_PWRDOWN \
16297 /* Module is not inserted. */
16298 #define HWRM_PORT_PHY_QCFG_OUTPUT_MODULE_STATUS_NOTINSERTED \
16300 /* Module is powered down because of over current fault. */
16301 #define HWRM_PORT_PHY_QCFG_OUTPUT_MODULE_STATUS_CURRENTFAULT \
16303 /* Module status is not applicable. */
16304 #define HWRM_PORT_PHY_QCFG_OUTPUT_MODULE_STATUS_NOTAPPLICABLE \
16306 #define HWRM_PORT_PHY_QCFG_OUTPUT_MODULE_STATUS_LAST \
16307 HWRM_PORT_PHY_QCFG_OUTPUT_MODULE_STATUS_NOTAPPLICABLE
16308 /* Current setting for preemphasis. */
16309 uint32_t preemphasis;
16310 /* This field represents the major version of the PHY. */
16312 /* This field represents the minor version of the PHY. */
16314 /* This field represents the build version of the PHY. */
16316 /* This value represents a PHY type. */
16319 #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_UNKNOWN \
16322 #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_BASECR \
16324 /* BASE-KR4 (Deprecated) */
16325 #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_BASEKR4 \
16328 #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_BASELR \
16331 #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_BASESR \
16333 /* BASE-KR2 (Deprecated) */
16334 #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_BASEKR2 \
16337 #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_BASEKX \
16340 #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_BASEKR \
16343 #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_BASET \
16345 /* EEE capable BASE-T */
16346 #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_BASETE \
16348 /* SGMII connected external PHY */
16349 #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_SGMIIEXTPHY \
16351 /* 25G_BASECR_CA_L */
16352 #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_25G_BASECR_CA_L \
16354 /* 25G_BASECR_CA_S */
16355 #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_25G_BASECR_CA_S \
16357 /* 25G_BASECR_CA_N */
16358 #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_25G_BASECR_CA_N \
16361 #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_25G_BASESR \
16364 #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_100G_BASECR4 \
16367 #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_100G_BASESR4 \
16370 #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_100G_BASELR4 \
16373 #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_100G_BASEER4 \
16375 /* 100G_BASESR10 */
16376 #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_100G_BASESR10 \
16379 #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_40G_BASECR4 \
16382 #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_40G_BASESR4 \
16385 #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_40G_BASELR4 \
16388 #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_40G_BASEER4 \
16390 /* 40G_ACTIVE_CABLE */
16391 #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_40G_ACTIVE_CABLE \
16394 #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_1G_BASET \
16397 #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_1G_BASESX \
16400 #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_1G_BASECX \
16403 #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_200G_BASECR4 \
16406 #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_200G_BASESR4 \
16409 #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_200G_BASELR4 \
16412 #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_200G_BASEER4 \
16414 #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_LAST \
16415 HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_200G_BASEER4
16416 /* This value represents a media type. */
16417 uint8_t media_type;
16419 #define HWRM_PORT_PHY_QCFG_OUTPUT_MEDIA_TYPE_UNKNOWN UINT32_C(0x0)
16421 #define HWRM_PORT_PHY_QCFG_OUTPUT_MEDIA_TYPE_TP UINT32_C(0x1)
16422 /* Direct Attached Copper */
16423 #define HWRM_PORT_PHY_QCFG_OUTPUT_MEDIA_TYPE_DAC UINT32_C(0x2)
16425 #define HWRM_PORT_PHY_QCFG_OUTPUT_MEDIA_TYPE_FIBRE UINT32_C(0x3)
16426 #define HWRM_PORT_PHY_QCFG_OUTPUT_MEDIA_TYPE_LAST \
16427 HWRM_PORT_PHY_QCFG_OUTPUT_MEDIA_TYPE_FIBRE
16428 /* This value represents a transceiver type. */
16429 uint8_t xcvr_pkg_type;
16430 /* PHY and MAC are in the same package */
16431 #define HWRM_PORT_PHY_QCFG_OUTPUT_XCVR_PKG_TYPE_XCVR_INTERNAL \
16433 /* PHY and MAC are in different packages */
16434 #define HWRM_PORT_PHY_QCFG_OUTPUT_XCVR_PKG_TYPE_XCVR_EXTERNAL \
16436 #define HWRM_PORT_PHY_QCFG_OUTPUT_XCVR_PKG_TYPE_LAST \
16437 HWRM_PORT_PHY_QCFG_OUTPUT_XCVR_PKG_TYPE_XCVR_EXTERNAL
16438 uint8_t eee_config_phy_addr;
16439 /* This field represents PHY address. */
16440 #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_ADDR_MASK \
16442 #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_ADDR_SFT 0
16444 * This field represents flags related to EEE configuration.
16445 * These EEE configuration flags are valid only when the
16446 * auto_mode is not set to none (in other words autonegotiation
16449 #define HWRM_PORT_PHY_QCFG_OUTPUT_EEE_CONFIG_MASK \
16451 #define HWRM_PORT_PHY_QCFG_OUTPUT_EEE_CONFIG_SFT 5
16453 * When set to 1, Energy Efficient Ethernet (EEE) mode is enabled.
16454 * Speeds for autoneg with EEE mode enabled
16455 * are based on eee_link_speed_mask.
16457 #define HWRM_PORT_PHY_QCFG_OUTPUT_EEE_CONFIG_EEE_ENABLED \
16460 * This flag is valid only when eee_enabled is set to 1.
16462 * # If eee_enabled is set to 0, then EEE mode is disabled
16463 * and this flag shall be ignored.
16464 * # If eee_enabled is set to 1 and this flag is set to 1,
16465 * then Energy Efficient Ethernet (EEE) mode is enabled
16467 * # If eee_enabled is set to 1 and this flag is set to 0,
16468 * then Energy Efficient Ethernet (EEE) mode is enabled
16469 * but is currently not in use.
16471 #define HWRM_PORT_PHY_QCFG_OUTPUT_EEE_CONFIG_EEE_ACTIVE \
16474 * This flag is valid only when eee_enabled is set to 1.
16476 * # If eee_enabled is set to 0, then EEE mode is disabled
16477 * and this flag shall be ignored.
16478 * # If eee_enabled is set to 1 and this flag is set to 1,
16479 * then Energy Efficient Ethernet (EEE) mode is enabled
16480 * and TX LPI is enabled.
16481 * # If eee_enabled is set to 1 and this flag is set to 0,
16482 * then Energy Efficient Ethernet (EEE) mode is enabled
16483 * but TX LPI is disabled.
16485 #define HWRM_PORT_PHY_QCFG_OUTPUT_EEE_CONFIG_EEE_TX_LPI \
16488 * When set to 1, the parallel detection is used to determine
16489 * the speed of the link partner.
16491 * Parallel detection is used when a autonegotiation capable
16492 * device is connected to a link parter that is not capable
16493 * of autonegotiation.
16495 uint8_t parallel_detect;
16497 * When set to 1, the parallel detection is used to determine
16498 * the speed of the link partner.
16500 * Parallel detection is used when a autonegotiation capable
16501 * device is connected to a link parter that is not capable
16502 * of autonegotiation.
16504 #define HWRM_PORT_PHY_QCFG_OUTPUT_PARALLEL_DETECT UINT32_C(0x1)
16506 * The advertised speeds for the port by the link partner.
16507 * Each advertised speed will be set to '1'.
16509 uint16_t link_partner_adv_speeds;
16510 /* 100Mb link speed (Half-duplex) */
16511 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_SPEEDS_100MBHD \
16513 /* 100Mb link speed (Full-duplex) */
16514 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_SPEEDS_100MB \
16516 /* 1Gb link speed (Half-duplex) */
16517 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_SPEEDS_1GBHD \
16519 /* 1Gb link speed (Full-duplex) */
16520 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_SPEEDS_1GB \
16522 /* 2Gb link speed */
16523 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_SPEEDS_2GB \
16525 /* 25Gb link speed */
16526 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_SPEEDS_2_5GB \
16528 /* 10Gb link speed */
16529 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_SPEEDS_10GB \
16531 /* 20Gb link speed */
16532 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_SPEEDS_20GB \
16534 /* 25Gb link speed */
16535 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_SPEEDS_25GB \
16537 /* 40Gb link speed */
16538 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_SPEEDS_40GB \
16540 /* 50Gb link speed */
16541 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_SPEEDS_50GB \
16543 /* 100Gb link speed */
16544 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_SPEEDS_100GB \
16546 /* 10Mb link speed (Half-duplex) */
16547 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_SPEEDS_10MBHD \
16549 /* 10Mb link speed (Full-duplex) */
16550 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_SPEEDS_10MB \
16553 * The advertised autoneg for the port by the link partner.
16554 * This field is deprecated and should be set to 0.
16556 uint8_t link_partner_adv_auto_mode;
16557 /* Disable autoneg or autoneg disabled. No speeds are selected. */
16558 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_AUTO_MODE_NONE \
16560 /* Select all possible speeds for autoneg mode. */
16561 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_AUTO_MODE_ALL_SPEEDS \
16564 * Select only the auto_link_speed speed for autoneg mode. This mode has
16565 * been DEPRECATED. An HWRM client should not use this mode.
16567 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_AUTO_MODE_ONE_SPEED \
16570 * Select the auto_link_speed or any speed below that speed for autoneg.
16571 * This mode has been DEPRECATED. An HWRM client should not use this mode.
16573 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_AUTO_MODE_ONE_OR_BELOW \
16576 * Select the speeds based on the corresponding link speed mask value
16577 * that is provided.
16579 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_AUTO_MODE_SPEED_MASK \
16581 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_AUTO_MODE_LAST \
16582 HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_AUTO_MODE_SPEED_MASK
16583 /* The advertised pause settings on the port by the link partner. */
16584 uint8_t link_partner_adv_pause;
16586 * When this bit is '1', Generation of tx pause messages
16587 * is supported. Disabled otherwise.
16589 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_PAUSE_TX \
16592 * When this bit is '1', Reception of rx pause messages
16593 * is supported. Disabled otherwise.
16595 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_PAUSE_RX \
16598 * Current setting for link speed mask that is used to
16599 * advertise speeds during autonegotiation when EEE is enabled.
16600 * This field is valid only when eee_enabled flags is set to 1.
16601 * The speeds specified in this field shall be a subset of
16602 * speeds specified in auto_link_speed_mask.
16604 uint16_t adv_eee_link_speed_mask;
16606 #define HWRM_PORT_PHY_QCFG_OUTPUT_ADV_EEE_LINK_SPEED_MASK_RSVD1 \
16608 /* 100Mb link speed (Full-duplex) */
16609 #define HWRM_PORT_PHY_QCFG_OUTPUT_ADV_EEE_LINK_SPEED_MASK_100MB \
16612 #define HWRM_PORT_PHY_QCFG_OUTPUT_ADV_EEE_LINK_SPEED_MASK_RSVD2 \
16614 /* 1Gb link speed (Full-duplex) */
16615 #define HWRM_PORT_PHY_QCFG_OUTPUT_ADV_EEE_LINK_SPEED_MASK_1GB \
16618 #define HWRM_PORT_PHY_QCFG_OUTPUT_ADV_EEE_LINK_SPEED_MASK_RSVD3 \
16621 #define HWRM_PORT_PHY_QCFG_OUTPUT_ADV_EEE_LINK_SPEED_MASK_RSVD4 \
16623 /* 10Gb link speed */
16624 #define HWRM_PORT_PHY_QCFG_OUTPUT_ADV_EEE_LINK_SPEED_MASK_10GB \
16627 * Current setting for link speed mask that is advertised by
16628 * the link partner when EEE is enabled.
16629 * This field is valid only when eee_enabled flags is set to 1.
16631 uint16_t link_partner_adv_eee_link_speed_mask;
16633 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_EEE_LINK_SPEED_MASK_RSVD1 \
16635 /* 100Mb link speed (Full-duplex) */
16636 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_EEE_LINK_SPEED_MASK_100MB \
16639 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_EEE_LINK_SPEED_MASK_RSVD2 \
16641 /* 1Gb link speed (Full-duplex) */
16642 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_EEE_LINK_SPEED_MASK_1GB \
16645 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_EEE_LINK_SPEED_MASK_RSVD3 \
16648 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_EEE_LINK_SPEED_MASK_RSVD4 \
16650 /* 10Gb link speed */
16651 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_EEE_LINK_SPEED_MASK_10GB \
16653 uint32_t xcvr_identifier_type_tx_lpi_timer;
16655 * Current setting of TX LPI timer in microseconds.
16656 * This field is valid only when_eee_enabled flag is set to 1
16657 * and tx_lpi_enabled is set to 1.
16659 #define HWRM_PORT_PHY_QCFG_OUTPUT_TX_LPI_TIMER_MASK \
16661 #define HWRM_PORT_PHY_QCFG_OUTPUT_TX_LPI_TIMER_SFT 0
16662 /* This value represents transceiver identifier type. */
16663 #define HWRM_PORT_PHY_QCFG_OUTPUT_XCVR_IDENTIFIER_TYPE_MASK \
16664 UINT32_C(0xff000000)
16665 #define HWRM_PORT_PHY_QCFG_OUTPUT_XCVR_IDENTIFIER_TYPE_SFT 24
16667 #define HWRM_PORT_PHY_QCFG_OUTPUT_XCVR_IDENTIFIER_TYPE_UNKNOWN \
16668 (UINT32_C(0x0) << 24)
16669 /* SFP/SFP+/SFP28 */
16670 #define HWRM_PORT_PHY_QCFG_OUTPUT_XCVR_IDENTIFIER_TYPE_SFP \
16671 (UINT32_C(0x3) << 24)
16673 #define HWRM_PORT_PHY_QCFG_OUTPUT_XCVR_IDENTIFIER_TYPE_QSFP \
16674 (UINT32_C(0xc) << 24)
16676 #define HWRM_PORT_PHY_QCFG_OUTPUT_XCVR_IDENTIFIER_TYPE_QSFPPLUS \
16677 (UINT32_C(0xd) << 24)
16679 #define HWRM_PORT_PHY_QCFG_OUTPUT_XCVR_IDENTIFIER_TYPE_QSFP28 \
16680 (UINT32_C(0x11) << 24)
16681 #define HWRM_PORT_PHY_QCFG_OUTPUT_XCVR_IDENTIFIER_TYPE_LAST \
16682 HWRM_PORT_PHY_QCFG_OUTPUT_XCVR_IDENTIFIER_TYPE_QSFP28
16684 * This value represents the current configuration of
16685 * Forward Error Correction (FEC) on the port.
16689 * When set to 1, then FEC is not supported on this port. If this flag
16690 * is set to 1, then all other FEC configuration flags shall be ignored.
16691 * When set to 0, then FEC is supported as indicated by other
16692 * configuration flags.
16694 #define HWRM_PORT_PHY_QCFG_OUTPUT_FEC_CFG_FEC_NONE_SUPPORTED \
16697 * When set to 1, then FEC autonegotiation is supported on this port.
16698 * When set to 0, then FEC autonegotiation is not supported on this port.
16700 #define HWRM_PORT_PHY_QCFG_OUTPUT_FEC_CFG_FEC_AUTONEG_SUPPORTED \
16703 * When set to 1, then FEC autonegotiation is enabled on this port.
16704 * When set to 0, then FEC autonegotiation is disabled if supported.
16705 * This flag should be ignored if FEC autonegotiation is not supported on this port.
16707 #define HWRM_PORT_PHY_QCFG_OUTPUT_FEC_CFG_FEC_AUTONEG_ENABLED \
16710 * When set to 1, then FEC CLAUSE 74 (Fire Code) is supported on this port.
16711 * When set to 0, then FEC CLAUSE 74 (Fire Code) is not supported on this port.
16713 #define HWRM_PORT_PHY_QCFG_OUTPUT_FEC_CFG_FEC_CLAUSE74_SUPPORTED \
16716 * When set to 1, then FEC CLAUSE 74 (Fire Code) is enabled on this
16717 * port. This means that FEC CLAUSE 74 is either advertised if
16718 * FEC autonegotiation is enabled or FEC CLAUSE 74 is force enabled.
16719 * When set to 0, then FEC CLAUSE 74 (Fire Code) is disabled if supported.
16720 * This flag should be ignored if FEC CLAUSE 74 is not supported on this port.
16722 #define HWRM_PORT_PHY_QCFG_OUTPUT_FEC_CFG_FEC_CLAUSE74_ENABLED \
16725 * When set to 1, then FEC CLAUSE 91 (Reed Solomon) is supported on this port.
16726 * When set to 0, then FEC CLAUSE 91 (Reed Solomon) is not supported on this port.
16728 #define HWRM_PORT_PHY_QCFG_OUTPUT_FEC_CFG_FEC_CLAUSE91_SUPPORTED \
16731 * When set to 1, then FEC CLAUSE 91 (Reed Solomon) is enabled on this
16732 * port. This means that FEC CLAUSE 91 is either advertised if
16733 * FEC autonegotiation is enabled or FEC CLAUSE 91 is force enabled.
16734 * When set to 0, then FEC CLAUSE 91 (Reed Solomon) is disabled if supported.
16735 * This flag should be ignored if FEC CLAUSE 91 is not supported on this port.
16737 #define HWRM_PORT_PHY_QCFG_OUTPUT_FEC_CFG_FEC_CLAUSE91_ENABLED \
16740 * When set to 1, then FEC RS544_1XN is supported on this port.
16741 * When set to 0, then FEC RS544_1XN is not supported on this port.
16743 #define HWRM_PORT_PHY_QCFG_OUTPUT_FEC_CFG_FEC_RS544_1XN_SUPPORTED \
16746 * When set to 1, then RS544_1XN is enabled on this
16747 * port. This means that FEC RS544_1XN is either advertised if
16748 * FEC autonegotiation is enabled or FEC RS544_1XN is force enabled.
16749 * When set to 0, then FEC RS544_1XN is disabled if supported.
16750 * This flag should be ignored if FEC RS544_1XN is not supported on this port.
16752 #define HWRM_PORT_PHY_QCFG_OUTPUT_FEC_CFG_FEC_RS544_1XN_ENABLED \
16755 * When set to 1, then FEC RS544_2XN is supported on this port.
16756 * When set to 0, then FEC RS544_2XN is not supported on this port.
16758 #define HWRM_PORT_PHY_QCFG_OUTPUT_FEC_CFG_FEC_RS544_2XN_SUPPORTED \
16761 * When set to 1, then RS544_2XN is enabled on this
16762 * port. This means that FEC RS544_2XN is either advertised if
16763 * FEC autonegotiation is enabled or FEC RS544_2XN is force enabled.
16764 * When set to 0, then FEC RS544_2XN is disabled if supported.
16765 * This flag should be ignored if FEC RS544_2XN is not supported on this port.
16767 #define HWRM_PORT_PHY_QCFG_OUTPUT_FEC_CFG_FEC_RS544_2XN_ENABLED \
16770 * When set to 1, then FEC CLAUSE 74 (Fire Code) is active on this
16771 * port, either successfully autonegoatiated or forced.
16772 * When set to 0, then FEC CLAUSE 74 (Fire Code) is not active.
16773 * This flag is only valid when link is up on this port.
16774 * At most only one active FEC flags (fec_clause74_active,
16775 * fec_clause91_active, fec_rs544_1xn, fec_rs544_2xn) can be set.
16777 #define HWRM_PORT_PHY_QCFG_OUTPUT_FEC_CFG_FEC_CLAUSE74_ACTIVE \
16780 * When set to 1, then FEC CLAUSE 91 (Reed Solomon) is active on this
16781 * port, either successfully autonegoatiated or forced.
16782 * When set to 0, then FEC CLAUSE 91 (Reed Solomon) is not active.
16783 * This flag is only valid when link is up on this port.
16784 * At most only one active FEC flags (fec_clause74_active,
16785 * fec_clause91_active, fec_rs544_1xn, fec_rs544_2xn) can be set.
16787 #define HWRM_PORT_PHY_QCFG_OUTPUT_FEC_CFG_FEC_CLAUSE91_ACTIVE \
16790 * When set to 1, then FEC RS544_1XN is active on this
16791 * port, either successfully autonegoatiated or forced.
16792 * When set to 0, then FEC RS544_1XN is not active.
16793 * This flag is only valid when link is up on this port.
16794 * At most only one active FEC flags (fec_clause74_active,
16795 * fec_clause91_active, fec_rs544_1xn, fec_rs544_2xn) can be set.
16797 #define HWRM_PORT_PHY_QCFG_OUTPUT_FEC_CFG_FEC_RS544_1XN_ACTIVE \
16800 * When set to 1, then FEC RS544_2XN is active on this
16801 * port, either successfully autonegoatiated or forced.
16802 * When set to 0, then FEC RS544_2XN is not active.
16803 * This flag is only valid when link is up on this port.
16804 * At most only one active FEC flags (fec_clause74_active,
16805 * fec_clause91_active, fec_rs544_1xn, fec_rs544_2xn) can be set.
16807 #define HWRM_PORT_PHY_QCFG_OUTPUT_FEC_CFG_FEC_RS544_2XN_ACTIVE \
16810 * This value is indicates the duplex of the current
16811 * connection state.
16813 uint8_t duplex_state;
16814 /* Half Duplex connection. */
16815 #define HWRM_PORT_PHY_QCFG_OUTPUT_DUPLEX_STATE_HALF UINT32_C(0x0)
16816 /* Full duplex connection. */
16817 #define HWRM_PORT_PHY_QCFG_OUTPUT_DUPLEX_STATE_FULL UINT32_C(0x1)
16818 #define HWRM_PORT_PHY_QCFG_OUTPUT_DUPLEX_STATE_LAST \
16819 HWRM_PORT_PHY_QCFG_OUTPUT_DUPLEX_STATE_FULL
16820 /* Option flags fields. */
16821 uint8_t option_flags;
16822 /* When this bit is '1', Media auto detect is enabled. */
16823 #define HWRM_PORT_PHY_QCFG_OUTPUT_OPTION_FLAGS_MEDIA_AUTO_DETECT \
16826 * Up to 16 bytes of null padded ASCII string representing
16828 * If the string is set to null, then the vendor name is not
16831 char phy_vendor_name[16];
16833 * Up to 16 bytes of null padded ASCII string that
16834 * identifies vendor specific part number of the PHY.
16835 * If the string is set to null, then the vendor specific
16836 * part number is not available.
16838 char phy_vendor_partnumber[16];
16839 uint8_t unused_2[7];
16841 * This field is used in Output records to indicate that the output
16842 * is completely written to RAM. This field should be read as '1'
16843 * to indicate that the output has been completely written.
16844 * When writing a command completion or response to an internal processor,
16845 * the order of writes has to be such that this field is written last.
16850 /*********************
16851 * hwrm_port_mac_cfg *
16852 *********************/
16855 /* hwrm_port_mac_cfg_input (size:384b/48B) */
16856 struct hwrm_port_mac_cfg_input {
16857 /* The HWRM command request type. */
16860 * The completion ring to send the completion event on. This should
16861 * be the NQ ID returned from the `nq_alloc` HWRM command.
16863 uint16_t cmpl_ring;
16865 * The sequence ID is used by the driver for tracking multiple
16866 * commands. This ID is treated as opaque data by the firmware and
16867 * the value is returned in the `hwrm_resp_hdr` upon completion.
16871 * The target ID of the command:
16872 * * 0x0-0xFFF8 - The function ID
16873 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
16874 * * 0xFFFD - Reserved for user-space HWRM interface
16877 uint16_t target_id;
16879 * A physical address pointer pointing to a host buffer that the
16880 * command's response data will be written. This can be either a host
16881 * physical address (HPA) or a guest physical address (GPA) and must
16882 * point to a physically contiguous block of memory.
16884 uint64_t resp_addr;
16886 * In this field, there are a number of CoS mappings related flags
16887 * that are used to configure CoS mappings and their corresponding
16888 * priorities in the hardware.
16889 * For the priorities of CoS mappings, the HWRM uses the following
16890 * priority order (high to low) by default:
16893 * # tunnel_vlan_pri
16896 * A subset of CoS mappings can be enabled.
16897 * If a priority is not specified for an enabled CoS mapping, the
16898 * priority will be assigned in the above order for the enabled CoS
16899 * mappings. For example, if vlan_pri and ip_dscp CoS mappings are
16900 * enabled and their priorities are not specified, the following
16901 * priority order (high to low) will be used by the HWRM:
16906 * vlan_pri CoS mapping together with default CoS with lower priority
16907 * are enabled by default by the HWRM.
16911 * When this bit is '1', this command will configure
16912 * the MAC to match the current link state of the PHY.
16913 * If the link is not established on the PHY, then this
16914 * bit has no effect.
16916 #define HWRM_PORT_MAC_CFG_INPUT_FLAGS_MATCH_LINK \
16919 * When this bit is set to '1', the inner VLAN PRI to CoS mapping
16920 * is requested to be enabled.
16922 #define HWRM_PORT_MAC_CFG_INPUT_FLAGS_VLAN_PRI2COS_ENABLE \
16925 * When this bit is set to '1', tunnel VLAN PRI field to
16926 * CoS mapping is requested to be enabled.
16928 #define HWRM_PORT_MAC_CFG_INPUT_FLAGS_TUNNEL_PRI2COS_ENABLE \
16931 * When this bit is set to '1', the IP DSCP to CoS mapping is
16932 * requested to be enabled.
16934 #define HWRM_PORT_MAC_CFG_INPUT_FLAGS_IP_DSCP2COS_ENABLE \
16937 * When this bit is '1', the HWRM is requested to
16938 * enable timestamp capture capability on the receive side
16941 #define HWRM_PORT_MAC_CFG_INPUT_FLAGS_PTP_RX_TS_CAPTURE_ENABLE \
16944 * When this bit is '1', the HWRM is requested to
16945 * disable timestamp capture capability on the receive side
16948 #define HWRM_PORT_MAC_CFG_INPUT_FLAGS_PTP_RX_TS_CAPTURE_DISABLE \
16951 * When this bit is '1', the HWRM is requested to
16952 * enable timestamp capture capability on the transmit side
16955 #define HWRM_PORT_MAC_CFG_INPUT_FLAGS_PTP_TX_TS_CAPTURE_ENABLE \
16958 * When this bit is '1', the HWRM is requested to
16959 * disable timestamp capture capability on the transmit side
16962 #define HWRM_PORT_MAC_CFG_INPUT_FLAGS_PTP_TX_TS_CAPTURE_DISABLE \
16965 * When this bit is '1', the Out-Of-Box WoL is requested to
16966 * be enabled on this port.
16968 #define HWRM_PORT_MAC_CFG_INPUT_FLAGS_OOB_WOL_ENABLE \
16971 * When this bit is '1', the Out-Of-Box WoL is requested to
16972 * be disabled on this port.
16974 #define HWRM_PORT_MAC_CFG_INPUT_FLAGS_OOB_WOL_DISABLE \
16977 * When this bit is set to '1', the inner VLAN PRI to CoS mapping
16978 * is requested to be disabled.
16980 #define HWRM_PORT_MAC_CFG_INPUT_FLAGS_VLAN_PRI2COS_DISABLE \
16983 * When this bit is set to '1', tunnel VLAN PRI field to
16984 * CoS mapping is requested to be disabled.
16986 #define HWRM_PORT_MAC_CFG_INPUT_FLAGS_TUNNEL_PRI2COS_DISABLE \
16989 * When this bit is set to '1', the IP DSCP to CoS mapping is
16990 * requested to be disabled.
16992 #define HWRM_PORT_MAC_CFG_INPUT_FLAGS_IP_DSCP2COS_DISABLE \
16995 * When this bit is set to '1', and the ptp_tx_ts_capture_enable
16996 * bit is set, then the device uses one step Tx timestamping.
16997 * This bit is temporary and used for experimental purposes.
16999 #define HWRM_PORT_MAC_CFG_INPUT_FLAGS_PTP_ONE_STEP_TX_TS \
17003 * This bit must be '1' for the ipg field to be
17006 #define HWRM_PORT_MAC_CFG_INPUT_ENABLES_IPG \
17009 * This bit must be '1' for the lpbk field to be
17012 #define HWRM_PORT_MAC_CFG_INPUT_ENABLES_LPBK \
17015 * This bit must be '1' for the vlan_pri2cos_map_pri field to be
17018 #define HWRM_PORT_MAC_CFG_INPUT_ENABLES_VLAN_PRI2COS_MAP_PRI \
17021 * This bit must be '1' for the tunnel_pri2cos_map_pri field to be
17024 #define HWRM_PORT_MAC_CFG_INPUT_ENABLES_TUNNEL_PRI2COS_MAP_PRI \
17027 * This bit must be '1' for the dscp2cos_map_pri field to be
17030 #define HWRM_PORT_MAC_CFG_INPUT_ENABLES_DSCP2COS_MAP_PRI \
17033 * This bit must be '1' for the rx_ts_capture_ptp_msg_type field to be
17036 #define HWRM_PORT_MAC_CFG_INPUT_ENABLES_RX_TS_CAPTURE_PTP_MSG_TYPE \
17039 * This bit must be '1' for the tx_ts_capture_ptp_msg_type field to be
17042 #define HWRM_PORT_MAC_CFG_INPUT_ENABLES_TX_TS_CAPTURE_PTP_MSG_TYPE \
17045 * This bit must be '1' for the cos_field_cfg field to be
17048 #define HWRM_PORT_MAC_CFG_INPUT_ENABLES_COS_FIELD_CFG \
17051 * This bit must be '1' for the ptp_freq_adj_ppb field to be
17054 #define HWRM_PORT_MAC_CFG_INPUT_ENABLES_PTP_FREQ_ADJ_PPB \
17056 /* Port ID of port that is to be configured. */
17059 * This value is used to configure the minimum IPG that will
17060 * be sent between packets by this port.
17063 /* This value controls the loopback setting for the MAC. */
17065 /* No loopback is selected. Normal operation. */
17066 #define HWRM_PORT_MAC_CFG_INPUT_LPBK_NONE UINT32_C(0x0)
17068 * The HW will be configured with local loopback such that
17069 * host data is sent back to the host without modification.
17071 #define HWRM_PORT_MAC_CFG_INPUT_LPBK_LOCAL UINT32_C(0x1)
17073 * The HW will be configured with remote loopback such that
17074 * port logic will send packets back out the transmitter that
17077 #define HWRM_PORT_MAC_CFG_INPUT_LPBK_REMOTE UINT32_C(0x2)
17078 #define HWRM_PORT_MAC_CFG_INPUT_LPBK_LAST \
17079 HWRM_PORT_MAC_CFG_INPUT_LPBK_REMOTE
17081 * This value controls the priority setting of VLAN PRI to CoS
17082 * mapping based on VLAN Tags of inner packet headers of
17083 * tunneled packets or packet headers of non-tunneled packets.
17085 * # Each XXX_pri variable shall have a unique priority value
17086 * when it is being specified.
17087 * # When comparing priorities of mappings, higher value
17088 * indicates higher priority.
17089 * For example, a value of 0-3 is returned where 0 is being
17090 * the lowest priority and 3 is being the highest priority.
17092 uint8_t vlan_pri2cos_map_pri;
17093 /* Reserved field. */
17096 * This value controls the priority setting of VLAN PRI to CoS
17097 * mapping based on VLAN Tags of tunneled header.
17098 * This mapping only applies when tunneled headers
17101 * # Each XXX_pri variable shall have a unique priority value
17102 * when it is being specified.
17103 * # When comparing priorities of mappings, higher value
17104 * indicates higher priority.
17105 * For example, a value of 0-3 is returned where 0 is being
17106 * the lowest priority and 3 is being the highest priority.
17108 uint8_t tunnel_pri2cos_map_pri;
17110 * This value controls the priority setting of IP DSCP to CoS
17111 * mapping based on inner IP header of tunneled packets or
17112 * IP header of non-tunneled packets.
17114 * # Each XXX_pri variable shall have a unique priority value
17115 * when it is being specified.
17116 * # When comparing priorities of mappings, higher value
17117 * indicates higher priority.
17118 * For example, a value of 0-3 is returned where 0 is being
17119 * the lowest priority and 3 is being the highest priority.
17121 uint8_t dscp2pri_map_pri;
17123 * This is a 16-bit bit mask that is used to request a
17124 * specific configuration of time stamp capture of PTP messages
17125 * on the receive side of this port.
17126 * This field shall be ignored if the ptp_rx_ts_capture_enable
17127 * flag is not set in this command.
17128 * Otherwise, if bit 'i' is set, then the HWRM is being
17129 * requested to configure the receive side of the port to
17130 * capture the time stamp of every received PTP message
17131 * with messageType field value set to i.
17133 uint16_t rx_ts_capture_ptp_msg_type;
17135 * This is a 16-bit bit mask that is used to request a
17136 * specific configuration of time stamp capture of PTP messages
17137 * on the transmit side of this port.
17138 * This field shall be ignored if the ptp_tx_ts_capture_enable
17139 * flag is not set in this command.
17140 * Otherwise, if bit 'i' is set, then the HWRM is being
17141 * requested to configure the transmit side of the port to
17142 * capture the time stamp of every transmitted PTP message
17143 * with messageType field value set to i.
17145 uint16_t tx_ts_capture_ptp_msg_type;
17146 /* Configuration of CoS fields. */
17147 uint8_t cos_field_cfg;
17149 #define HWRM_PORT_MAC_CFG_INPUT_COS_FIELD_CFG_RSVD1 \
17152 * This field is used to specify selection of VLAN PRI value
17153 * based on whether one or two VLAN Tags are present in
17154 * the inner packet headers of tunneled packets or
17155 * non-tunneled packets.
17156 * This field is valid only if inner VLAN PRI to CoS mapping
17158 * If VLAN PRI to CoS mapping is not enabled, then this
17159 * field shall be ignored.
17161 #define HWRM_PORT_MAC_CFG_INPUT_COS_FIELD_CFG_VLAN_PRI_SEL_MASK \
17163 #define HWRM_PORT_MAC_CFG_INPUT_COS_FIELD_CFG_VLAN_PRI_SEL_SFT \
17166 * Select inner VLAN PRI when 1 or 2 VLAN Tags are
17167 * present in the inner packet headers
17169 #define HWRM_PORT_MAC_CFG_INPUT_COS_FIELD_CFG_VLAN_PRI_SEL_INNERMOST \
17170 (UINT32_C(0x0) << 1)
17172 * Select outer VLAN Tag PRI when 2 VLAN Tags are
17173 * present in the inner packet headers.
17174 * No VLAN PRI shall be selected for this configuration
17175 * if only one VLAN Tag is present in the inner
17178 #define HWRM_PORT_MAC_CFG_INPUT_COS_FIELD_CFG_VLAN_PRI_SEL_OUTER \
17179 (UINT32_C(0x1) << 1)
17181 * Select outermost VLAN PRI when 1 or 2 VLAN Tags
17182 * are present in the inner packet headers
17184 #define HWRM_PORT_MAC_CFG_INPUT_COS_FIELD_CFG_VLAN_PRI_SEL_OUTERMOST \
17185 (UINT32_C(0x2) << 1)
17187 #define HWRM_PORT_MAC_CFG_INPUT_COS_FIELD_CFG_VLAN_PRI_SEL_UNSPECIFIED \
17188 (UINT32_C(0x3) << 1)
17189 #define HWRM_PORT_MAC_CFG_INPUT_COS_FIELD_CFG_VLAN_PRI_SEL_LAST \
17190 HWRM_PORT_MAC_CFG_INPUT_COS_FIELD_CFG_VLAN_PRI_SEL_UNSPECIFIED
17192 * This field is used to specify selection of tunnel VLAN
17193 * PRI value based on whether one or two VLAN Tags are
17194 * present in tunnel headers.
17195 * This field is valid only if tunnel VLAN PRI to CoS mapping
17197 * If tunnel VLAN PRI to CoS mapping is not enabled, then this
17198 * field shall be ignored.
17200 #define HWRM_PORT_MAC_CFG_INPUT_COS_FIELD_CFG_T_VLAN_PRI_SEL_MASK \
17202 #define HWRM_PORT_MAC_CFG_INPUT_COS_FIELD_CFG_T_VLAN_PRI_SEL_SFT \
17205 * Select inner VLAN PRI when 1 or 2 VLAN Tags are
17206 * present in the tunnel packet headers
17208 #define HWRM_PORT_MAC_CFG_INPUT_COS_FIELD_CFG_T_VLAN_PRI_SEL_INNERMOST \
17209 (UINT32_C(0x0) << 3)
17211 * Select outer VLAN Tag PRI when 2 VLAN Tags are
17212 * present in the tunnel packet headers.
17213 * No tunnel VLAN PRI shall be selected for this
17214 * configuration if only one VLAN Tag is present in
17215 * the tunnel packet headers.
17217 #define HWRM_PORT_MAC_CFG_INPUT_COS_FIELD_CFG_T_VLAN_PRI_SEL_OUTER \
17218 (UINT32_C(0x1) << 3)
17220 * Select outermost VLAN PRI when 1 or 2 VLAN Tags
17221 * are present in the tunnel packet headers
17223 #define HWRM_PORT_MAC_CFG_INPUT_COS_FIELD_CFG_T_VLAN_PRI_SEL_OUTERMOST \
17224 (UINT32_C(0x2) << 3)
17226 #define HWRM_PORT_MAC_CFG_INPUT_COS_FIELD_CFG_T_VLAN_PRI_SEL_UNSPECIFIED \
17227 (UINT32_C(0x3) << 3)
17228 #define HWRM_PORT_MAC_CFG_INPUT_COS_FIELD_CFG_T_VLAN_PRI_SEL_LAST \
17229 HWRM_PORT_MAC_CFG_INPUT_COS_FIELD_CFG_T_VLAN_PRI_SEL_UNSPECIFIED
17231 * This field shall be used to provide default CoS value
17232 * that has been configured on this port.
17233 * This field is valid only if default CoS mapping
17235 * If default CoS mapping is not enabled, then this
17236 * field shall be ignored.
17238 #define HWRM_PORT_MAC_CFG_INPUT_COS_FIELD_CFG_DEFAULT_COS_MASK \
17240 #define HWRM_PORT_MAC_CFG_INPUT_COS_FIELD_CFG_DEFAULT_COS_SFT \
17242 uint8_t unused_0[3];
17244 * This signed field specifies by how much to adjust the frequency
17245 * of sync timer updates (measured in parts per billion).
17247 int32_t ptp_freq_adj_ppb;
17248 uint8_t unused_1[4];
17251 /* hwrm_port_mac_cfg_output (size:128b/16B) */
17252 struct hwrm_port_mac_cfg_output {
17253 /* The specific error status for the command. */
17254 uint16_t error_code;
17255 /* The HWRM command request type. */
17257 /* The sequence ID from the original command. */
17259 /* The length of the response data in number of bytes. */
17262 * This is the configured maximum length of Ethernet packet
17263 * payload that is allowed to be received on the port.
17264 * This value does not include the number of bytes used by
17265 * Ethernet header and trailer (CRC).
17269 * This is the configured maximum length of Ethernet packet
17270 * payload that is allowed to be transmitted on the port.
17271 * This value does not include the number of bytes used by
17272 * Ethernet header and trailer (CRC).
17275 /* Current configuration of the IPG value. */
17277 /* Current value of the loopback value. */
17279 /* No loopback is selected. Normal operation. */
17280 #define HWRM_PORT_MAC_CFG_OUTPUT_LPBK_NONE UINT32_C(0x0)
17282 * The HW will be configured with local loopback such that
17283 * host data is sent back to the host without modification.
17285 #define HWRM_PORT_MAC_CFG_OUTPUT_LPBK_LOCAL UINT32_C(0x1)
17287 * The HW will be configured with remote loopback such that
17288 * port logic will send packets back out the transmitter that
17291 #define HWRM_PORT_MAC_CFG_OUTPUT_LPBK_REMOTE UINT32_C(0x2)
17292 #define HWRM_PORT_MAC_CFG_OUTPUT_LPBK_LAST \
17293 HWRM_PORT_MAC_CFG_OUTPUT_LPBK_REMOTE
17296 * This field is used in Output records to indicate that the output
17297 * is completely written to RAM. This field should be read as '1'
17298 * to indicate that the output has been completely written.
17299 * When writing a command completion or response to an internal processor,
17300 * the order of writes has to be such that this field is written last.
17305 /**********************
17306 * hwrm_port_mac_qcfg *
17307 **********************/
17310 /* hwrm_port_mac_qcfg_input (size:192b/24B) */
17311 struct hwrm_port_mac_qcfg_input {
17312 /* The HWRM command request type. */
17315 * The completion ring to send the completion event on. This should
17316 * be the NQ ID returned from the `nq_alloc` HWRM command.
17318 uint16_t cmpl_ring;
17320 * The sequence ID is used by the driver for tracking multiple
17321 * commands. This ID is treated as opaque data by the firmware and
17322 * the value is returned in the `hwrm_resp_hdr` upon completion.
17326 * The target ID of the command:
17327 * * 0x0-0xFFF8 - The function ID
17328 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
17329 * * 0xFFFD - Reserved for user-space HWRM interface
17332 uint16_t target_id;
17334 * A physical address pointer pointing to a host buffer that the
17335 * command's response data will be written. This can be either a host
17336 * physical address (HPA) or a guest physical address (GPA) and must
17337 * point to a physically contiguous block of memory.
17339 uint64_t resp_addr;
17340 /* Port ID of port that is to be configured. */
17342 uint8_t unused_0[6];
17345 /* hwrm_port_mac_qcfg_output (size:256b/32B) */
17346 struct hwrm_port_mac_qcfg_output {
17347 /* The specific error status for the command. */
17348 uint16_t error_code;
17349 /* The HWRM command request type. */
17351 /* The sequence ID from the original command. */
17353 /* The length of the response data in number of bytes. */
17356 * This is the configured maximum length of Ethernet packet
17357 * payload that is allowed to be received on the port.
17358 * This value does not include the number of bytes used by the
17359 * Ethernet header and trailer (CRC).
17363 * This is the configured maximum length of Ethernet packet
17364 * payload that is allowed to be transmitted on the port.
17365 * This value does not include the number of bytes used by the
17366 * Ethernet header and trailer (CRC).
17370 * The minimum IPG that will
17371 * be sent between packets by this port.
17374 /* The loopback setting for the MAC. */
17376 /* No loopback is selected. Normal operation. */
17377 #define HWRM_PORT_MAC_QCFG_OUTPUT_LPBK_NONE UINT32_C(0x0)
17379 * The HW will be configured with local loopback such that
17380 * host data is sent back to the host without modification.
17382 #define HWRM_PORT_MAC_QCFG_OUTPUT_LPBK_LOCAL UINT32_C(0x1)
17384 * The HW will be configured with remote loopback such that
17385 * port logic will send packets back out the transmitter that
17388 #define HWRM_PORT_MAC_QCFG_OUTPUT_LPBK_REMOTE UINT32_C(0x2)
17389 #define HWRM_PORT_MAC_QCFG_OUTPUT_LPBK_LAST \
17390 HWRM_PORT_MAC_QCFG_OUTPUT_LPBK_REMOTE
17392 * Priority setting for VLAN PRI to CoS mapping.
17393 * # Each XXX_pri variable shall have a unique priority value
17394 * when it is being used.
17395 * # When comparing priorities of mappings, higher value
17396 * indicates higher priority.
17397 * For example, a value of 0-3 is returned where 0 is being
17398 * the lowest priority and 3 is being the highest priority.
17399 * # If the correspoding CoS mapping is not enabled, then this
17400 * field should be ignored.
17401 * # This value indicates the normalized priority value retained
17404 uint8_t vlan_pri2cos_map_pri;
17406 * In this field, a number of CoS mappings related flags
17407 * are used to indicate configured CoS mappings.
17411 * When this bit is set to '1', the inner VLAN PRI to CoS mapping
17414 #define HWRM_PORT_MAC_QCFG_OUTPUT_FLAGS_VLAN_PRI2COS_ENABLE \
17417 * When this bit is set to '1', tunnel VLAN PRI field to
17418 * CoS mapping is enabled.
17420 #define HWRM_PORT_MAC_QCFG_OUTPUT_FLAGS_TUNNEL_PRI2COS_ENABLE \
17423 * When this bit is set to '1', the IP DSCP to CoS mapping is
17426 #define HWRM_PORT_MAC_QCFG_OUTPUT_FLAGS_IP_DSCP2COS_ENABLE \
17429 * When this bit is '1', the Out-Of-Box WoL is enabled on this
17432 #define HWRM_PORT_MAC_QCFG_OUTPUT_FLAGS_OOB_WOL_ENABLE \
17434 /* When this bit is '1', PTP is enabled for RX on this port. */
17435 #define HWRM_PORT_MAC_QCFG_OUTPUT_FLAGS_PTP_RX_TS_CAPTURE_ENABLE \
17437 /* When this bit is '1', PTP is enabled for TX on this port. */
17438 #define HWRM_PORT_MAC_QCFG_OUTPUT_FLAGS_PTP_TX_TS_CAPTURE_ENABLE \
17441 * Priority setting for tunnel VLAN PRI to CoS mapping.
17442 * # Each XXX_pri variable shall have a unique priority value
17443 * when it is being used.
17444 * # When comparing priorities of mappings, higher value
17445 * indicates higher priority.
17446 * For example, a value of 0-3 is returned where 0 is being
17447 * the lowest priority and 3 is being the highest priority.
17448 * # If the correspoding CoS mapping is not enabled, then this
17449 * field should be ignored.
17450 * # This value indicates the normalized priority value retained
17453 uint8_t tunnel_pri2cos_map_pri;
17455 * Priority setting for DSCP to PRI mapping.
17456 * # Each XXX_pri variable shall have a unique priority value
17457 * when it is being used.
17458 * # When comparing priorities of mappings, higher value
17459 * indicates higher priority.
17460 * For example, a value of 0-3 is returned where 0 is being
17461 * the lowest priority and 3 is being the highest priority.
17462 * # If the correspoding CoS mapping is not enabled, then this
17463 * field should be ignored.
17464 * # This value indicates the normalized priority value retained
17467 uint8_t dscp2pri_map_pri;
17469 * This is a 16-bit bit mask that represents the
17470 * current configuration of time stamp capture of PTP messages
17471 * on the receive side of this port.
17472 * If bit 'i' is set, then the receive side of the port
17473 * is configured to capture the time stamp of every
17474 * received PTP message with messageType field value set
17476 * If all bits are set to 0 (i.e. field value set 0),
17477 * then the receive side of the port is not configured
17478 * to capture timestamp for PTP messages.
17479 * If all bits are set to 1, then the receive side of the
17480 * port is configured to capture timestamp for all PTP
17483 uint16_t rx_ts_capture_ptp_msg_type;
17485 * This is a 16-bit bit mask that represents the
17486 * current configuration of time stamp capture of PTP messages
17487 * on the transmit side of this port.
17488 * If bit 'i' is set, then the transmit side of the port
17489 * is configured to capture the time stamp of every
17490 * received PTP message with messageType field value set
17492 * If all bits are set to 0 (i.e. field value set 0),
17493 * then the transmit side of the port is not configured
17494 * to capture timestamp for PTP messages.
17495 * If all bits are set to 1, then the transmit side of the
17496 * port is configured to capture timestamp for all PTP
17499 uint16_t tx_ts_capture_ptp_msg_type;
17500 /* Configuration of CoS fields. */
17501 uint8_t cos_field_cfg;
17503 #define HWRM_PORT_MAC_QCFG_OUTPUT_COS_FIELD_CFG_RSVD \
17506 * This field is used for selecting VLAN PRI value
17507 * based on whether one or two VLAN Tags are present in
17508 * the inner packet headers of tunneled packets or
17509 * non-tunneled packets.
17511 #define HWRM_PORT_MAC_QCFG_OUTPUT_COS_FIELD_CFG_VLAN_PRI_SEL_MASK \
17513 #define HWRM_PORT_MAC_QCFG_OUTPUT_COS_FIELD_CFG_VLAN_PRI_SEL_SFT \
17516 * Select inner VLAN PRI when 1 or 2 VLAN Tags are
17517 * present in the inner packet headers
17519 #define HWRM_PORT_MAC_QCFG_OUTPUT_COS_FIELD_CFG_VLAN_PRI_SEL_INNERMOST \
17520 (UINT32_C(0x0) << 1)
17522 * Select outer VLAN Tag PRI when 2 VLAN Tags are
17523 * present in the inner packet headers.
17524 * No VLAN PRI is selected for this configuration
17525 * if only one VLAN Tag is present in the inner
17528 #define HWRM_PORT_MAC_QCFG_OUTPUT_COS_FIELD_CFG_VLAN_PRI_SEL_OUTER \
17529 (UINT32_C(0x1) << 1)
17531 * Select outermost VLAN PRI when 1 or 2 VLAN Tags
17532 * are present in the inner packet headers
17534 #define HWRM_PORT_MAC_QCFG_OUTPUT_COS_FIELD_CFG_VLAN_PRI_SEL_OUTERMOST \
17535 (UINT32_C(0x2) << 1)
17537 #define HWRM_PORT_MAC_QCFG_OUTPUT_COS_FIELD_CFG_VLAN_PRI_SEL_UNSPECIFIED \
17538 (UINT32_C(0x3) << 1)
17539 #define HWRM_PORT_MAC_QCFG_OUTPUT_COS_FIELD_CFG_VLAN_PRI_SEL_LAST \
17540 HWRM_PORT_MAC_QCFG_OUTPUT_COS_FIELD_CFG_VLAN_PRI_SEL_UNSPECIFIED
17542 * This field is used for selecting tunnel VLAN PRI value
17543 * based on whether one or two VLAN Tags are present in
17544 * the tunnel headers of tunneled packets. This selection
17545 * does not apply to non-tunneled packets.
17547 #define HWRM_PORT_MAC_QCFG_OUTPUT_COS_FIELD_CFG_T_VLAN_PRI_SEL_MASK \
17549 #define HWRM_PORT_MAC_QCFG_OUTPUT_COS_FIELD_CFG_T_VLAN_PRI_SEL_SFT \
17552 * Select inner VLAN PRI when 1 or 2 VLAN Tags are
17553 * present in the tunnel packet headers
17555 #define HWRM_PORT_MAC_QCFG_OUTPUT_COS_FIELD_CFG_T_VLAN_PRI_SEL_INNERMOST \
17556 (UINT32_C(0x0) << 3)
17558 * Select outer VLAN Tag PRI when 2 VLAN Tags are
17559 * present in the tunnel packet headers.
17560 * No VLAN PRI is selected for this configuration
17561 * if only one VLAN Tag is present in the tunnel
17564 #define HWRM_PORT_MAC_QCFG_OUTPUT_COS_FIELD_CFG_T_VLAN_PRI_SEL_OUTER \
17565 (UINT32_C(0x1) << 3)
17567 * Select outermost VLAN PRI when 1 or 2 VLAN Tags
17568 * are present in the tunnel packet headers
17570 #define HWRM_PORT_MAC_QCFG_OUTPUT_COS_FIELD_CFG_T_VLAN_PRI_SEL_OUTERMOST \
17571 (UINT32_C(0x2) << 3)
17573 #define HWRM_PORT_MAC_QCFG_OUTPUT_COS_FIELD_CFG_T_VLAN_PRI_SEL_UNSPECIFIED \
17574 (UINT32_C(0x3) << 3)
17575 #define HWRM_PORT_MAC_QCFG_OUTPUT_COS_FIELD_CFG_T_VLAN_PRI_SEL_LAST \
17576 HWRM_PORT_MAC_QCFG_OUTPUT_COS_FIELD_CFG_T_VLAN_PRI_SEL_UNSPECIFIED
17578 * This field is used to provide default CoS value that
17579 * has been configured on this port.
17581 #define HWRM_PORT_MAC_QCFG_OUTPUT_COS_FIELD_CFG_DEFAULT_COS_MASK \
17583 #define HWRM_PORT_MAC_QCFG_OUTPUT_COS_FIELD_CFG_DEFAULT_COS_SFT \
17586 uint16_t port_svif_info;
17588 * This field specifies the source virtual interface of the port being
17589 * queried. Drivers can use this to program port svif field in the
17592 #define HWRM_PORT_MAC_QCFG_OUTPUT_PORT_SVIF_INFO_PORT_SVIF_MASK \
17594 #define HWRM_PORT_MAC_QCFG_OUTPUT_PORT_SVIF_INFO_PORT_SVIF_SFT 0
17595 /* This field specifies whether port_svif is valid or not */
17596 #define HWRM_PORT_MAC_QCFG_OUTPUT_PORT_SVIF_INFO_PORT_SVIF_VALID \
17598 uint8_t unused_2[5];
17600 * This field is used in Output records to indicate that the output
17601 * is completely written to RAM. This field should be read as '1'
17602 * to indicate that the output has been completely written.
17603 * When writing a command completion or response to an internal processor,
17604 * the order of writes has to be such that this field is written last.
17609 /**************************
17610 * hwrm_port_mac_ptp_qcfg *
17611 **************************/
17614 /* hwrm_port_mac_ptp_qcfg_input (size:192b/24B) */
17615 struct hwrm_port_mac_ptp_qcfg_input {
17616 /* The HWRM command request type. */
17619 * The completion ring to send the completion event on. This should
17620 * be the NQ ID returned from the `nq_alloc` HWRM command.
17622 uint16_t cmpl_ring;
17624 * The sequence ID is used by the driver for tracking multiple
17625 * commands. This ID is treated as opaque data by the firmware and
17626 * the value is returned in the `hwrm_resp_hdr` upon completion.
17630 * The target ID of the command:
17631 * * 0x0-0xFFF8 - The function ID
17632 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
17633 * * 0xFFFD - Reserved for user-space HWRM interface
17636 uint16_t target_id;
17638 * A physical address pointer pointing to a host buffer that the
17639 * command's response data will be written. This can be either a host
17640 * physical address (HPA) or a guest physical address (GPA) and must
17641 * point to a physically contiguous block of memory.
17643 uint64_t resp_addr;
17644 /* Port ID of port that is being queried. */
17646 uint8_t unused_0[6];
17649 /* hwrm_port_mac_ptp_qcfg_output (size:640b/80B) */
17650 struct hwrm_port_mac_ptp_qcfg_output {
17651 /* The specific error status for the command. */
17652 uint16_t error_code;
17653 /* The HWRM command request type. */
17655 /* The sequence ID from the original command. */
17657 /* The length of the response data in number of bytes. */
17660 * In this field, a number of PTP related flags
17661 * are used to indicate configured PTP capabilities.
17665 * When this bit is set to '1', the PTP related registers are
17666 * directly accessible by the host.
17668 #define HWRM_PORT_MAC_PTP_QCFG_OUTPUT_FLAGS_DIRECT_ACCESS \
17671 * When this bit is set to '1', the device supports one-step
17674 #define HWRM_PORT_MAC_PTP_QCFG_OUTPUT_FLAGS_ONE_STEP_TX_TS \
17677 * When this bit is set to '1', the PTP information is accessible
17678 * via HWRM commands.
17680 #define HWRM_PORT_MAC_PTP_QCFG_OUTPUT_FLAGS_HWRM_ACCESS \
17682 uint8_t unused_0[3];
17683 /* Offset of the PTP register for the lower 32 bits of timestamp for RX. */
17684 uint32_t rx_ts_reg_off_lower;
17685 /* Offset of the PTP register for the upper 32 bits of timestamp for RX. */
17686 uint32_t rx_ts_reg_off_upper;
17687 /* Offset of the PTP register for the sequence ID for RX. */
17688 uint32_t rx_ts_reg_off_seq_id;
17689 /* Offset of the first PTP source ID for RX. */
17690 uint32_t rx_ts_reg_off_src_id_0;
17691 /* Offset of the second PTP source ID for RX. */
17692 uint32_t rx_ts_reg_off_src_id_1;
17693 /* Offset of the third PTP source ID for RX. */
17694 uint32_t rx_ts_reg_off_src_id_2;
17695 /* Offset of the domain ID for RX. */
17696 uint32_t rx_ts_reg_off_domain_id;
17697 /* Offset of the PTP FIFO register for RX. */
17698 uint32_t rx_ts_reg_off_fifo;
17699 /* Offset of the PTP advance FIFO register for RX. */
17700 uint32_t rx_ts_reg_off_fifo_adv;
17701 /* PTP timestamp granularity for RX. */
17702 uint32_t rx_ts_reg_off_granularity;
17703 /* Offset of the PTP register for the lower 32 bits of timestamp for TX. */
17704 uint32_t tx_ts_reg_off_lower;
17705 /* Offset of the PTP register for the upper 32 bits of timestamp for TX. */
17706 uint32_t tx_ts_reg_off_upper;
17707 /* Offset of the PTP register for the sequence ID for TX. */
17708 uint32_t tx_ts_reg_off_seq_id;
17709 /* Offset of the PTP FIFO register for TX. */
17710 uint32_t tx_ts_reg_off_fifo;
17711 /* PTP timestamp granularity for TX. */
17712 uint32_t tx_ts_reg_off_granularity;
17713 uint8_t unused_1[7];
17715 * This field is used in Output records to indicate that the output
17716 * is completely written to RAM. This field should be read as '1'
17717 * to indicate that the output has been completely written.
17718 * When writing a command completion or response to an internal processor,
17719 * the order of writes has to be such that this field is written last.
17724 /* Port Tx Statistics Format */
17725 /* tx_port_stats (size:3264b/408B) */
17726 struct tx_port_stats {
17727 /* Total Number of 64 Bytes frames transmitted */
17728 uint64_t tx_64b_frames;
17729 /* Total Number of 65-127 Bytes frames transmitted */
17730 uint64_t tx_65b_127b_frames;
17731 /* Total Number of 128-255 Bytes frames transmitted */
17732 uint64_t tx_128b_255b_frames;
17733 /* Total Number of 256-511 Bytes frames transmitted */
17734 uint64_t tx_256b_511b_frames;
17735 /* Total Number of 512-1023 Bytes frames transmitted */
17736 uint64_t tx_512b_1023b_frames;
17737 /* Total Number of 1024-1518 Bytes frames transmitted */
17738 uint64_t tx_1024b_1518b_frames;
17740 * Total Number of each good VLAN (exludes FCS errors)
17741 * frame transmitted which is 1519 to 1522 bytes in length
17742 * inclusive (excluding framing bits but including FCS bytes).
17744 uint64_t tx_good_vlan_frames;
17745 /* Total Number of 1519-2047 Bytes frames transmitted */
17746 uint64_t tx_1519b_2047b_frames;
17747 /* Total Number of 2048-4095 Bytes frames transmitted */
17748 uint64_t tx_2048b_4095b_frames;
17749 /* Total Number of 4096-9216 Bytes frames transmitted */
17750 uint64_t tx_4096b_9216b_frames;
17751 /* Total Number of 9217-16383 Bytes frames transmitted */
17752 uint64_t tx_9217b_16383b_frames;
17753 /* Total Number of good frames transmitted */
17754 uint64_t tx_good_frames;
17755 /* Total Number of frames transmitted */
17756 uint64_t tx_total_frames;
17757 /* Total number of unicast frames transmitted */
17758 uint64_t tx_ucast_frames;
17759 /* Total number of multicast frames transmitted */
17760 uint64_t tx_mcast_frames;
17761 /* Total number of broadcast frames transmitted */
17762 uint64_t tx_bcast_frames;
17763 /* Total number of PAUSE control frames transmitted */
17764 uint64_t tx_pause_frames;
17766 * Total number of PFC/per-priority PAUSE
17767 * control frames transmitted
17769 uint64_t tx_pfc_frames;
17770 /* Total number of jabber frames transmitted */
17771 uint64_t tx_jabber_frames;
17772 /* Total number of frames transmitted with FCS error */
17773 uint64_t tx_fcs_err_frames;
17774 /* Total number of control frames transmitted */
17775 uint64_t tx_control_frames;
17776 /* Total number of over-sized frames transmitted */
17777 uint64_t tx_oversz_frames;
17778 /* Total number of frames with single deferral */
17779 uint64_t tx_single_dfrl_frames;
17780 /* Total number of frames with multiple deferrals */
17781 uint64_t tx_multi_dfrl_frames;
17782 /* Total number of frames with single collision */
17783 uint64_t tx_single_coll_frames;
17784 /* Total number of frames with multiple collisions */
17785 uint64_t tx_multi_coll_frames;
17786 /* Total number of frames with late collisions */
17787 uint64_t tx_late_coll_frames;
17788 /* Total number of frames with excessive collisions */
17789 uint64_t tx_excessive_coll_frames;
17790 /* Total number of fragmented frames transmitted */
17791 uint64_t tx_frag_frames;
17792 /* Total number of transmit errors */
17794 /* Total number of single VLAN tagged frames transmitted */
17795 uint64_t tx_tagged_frames;
17796 /* Total number of double VLAN tagged frames transmitted */
17797 uint64_t tx_dbl_tagged_frames;
17798 /* Total number of runt frames transmitted */
17799 uint64_t tx_runt_frames;
17800 /* Total number of TX FIFO under runs */
17801 uint64_t tx_fifo_underruns;
17803 * Total number of PFC frames with PFC enabled bit for
17804 * Pri 0 transmitted
17806 uint64_t tx_pfc_ena_frames_pri0;
17808 * Total number of PFC frames with PFC enabled bit for
17809 * Pri 1 transmitted
17811 uint64_t tx_pfc_ena_frames_pri1;
17813 * Total number of PFC frames with PFC enabled bit for
17814 * Pri 2 transmitted
17816 uint64_t tx_pfc_ena_frames_pri2;
17818 * Total number of PFC frames with PFC enabled bit for
17819 * Pri 3 transmitted
17821 uint64_t tx_pfc_ena_frames_pri3;
17823 * Total number of PFC frames with PFC enabled bit for
17824 * Pri 4 transmitted
17826 uint64_t tx_pfc_ena_frames_pri4;
17828 * Total number of PFC frames with PFC enabled bit for
17829 * Pri 5 transmitted
17831 uint64_t tx_pfc_ena_frames_pri5;
17833 * Total number of PFC frames with PFC enabled bit for
17834 * Pri 6 transmitted
17836 uint64_t tx_pfc_ena_frames_pri6;
17838 * Total number of PFC frames with PFC enabled bit for
17839 * Pri 7 transmitted
17841 uint64_t tx_pfc_ena_frames_pri7;
17842 /* Total number of EEE LPI Events on TX */
17843 uint64_t tx_eee_lpi_events;
17844 /* EEE LPI Duration Counter on TX */
17845 uint64_t tx_eee_lpi_duration;
17847 * Total number of Link Level Flow Control (LLFC) messages
17850 uint64_t tx_llfc_logical_msgs;
17851 /* Total number of HCFC messages transmitted */
17852 uint64_t tx_hcfc_msgs;
17853 /* Total number of TX collisions */
17854 uint64_t tx_total_collisions;
17855 /* Total number of transmitted bytes */
17857 /* Total number of end-to-end HOL frames */
17858 uint64_t tx_xthol_frames;
17859 /* Total Tx Drops per Port reported by STATS block */
17860 uint64_t tx_stat_discard;
17861 /* Total Tx Error Drops per Port reported by STATS block */
17862 uint64_t tx_stat_error;
17865 /* Port Rx Statistics Format */
17866 /* rx_port_stats (size:4224b/528B) */
17867 struct rx_port_stats {
17868 /* Total Number of 64 Bytes frames received */
17869 uint64_t rx_64b_frames;
17870 /* Total Number of 65-127 Bytes frames received */
17871 uint64_t rx_65b_127b_frames;
17872 /* Total Number of 128-255 Bytes frames received */
17873 uint64_t rx_128b_255b_frames;
17874 /* Total Number of 256-511 Bytes frames received */
17875 uint64_t rx_256b_511b_frames;
17876 /* Total Number of 512-1023 Bytes frames received */
17877 uint64_t rx_512b_1023b_frames;
17878 /* Total Number of 1024-1518 Bytes frames received */
17879 uint64_t rx_1024b_1518b_frames;
17881 * Total Number of each good VLAN (exludes FCS errors)
17882 * frame received which is 1519 to 1522 bytes in length
17883 * inclusive (excluding framing bits but including FCS bytes).
17885 uint64_t rx_good_vlan_frames;
17886 /* Total Number of 1519-2047 Bytes frames received */
17887 uint64_t rx_1519b_2047b_frames;
17888 /* Total Number of 2048-4095 Bytes frames received */
17889 uint64_t rx_2048b_4095b_frames;
17890 /* Total Number of 4096-9216 Bytes frames received */
17891 uint64_t rx_4096b_9216b_frames;
17892 /* Total Number of 9217-16383 Bytes frames received */
17893 uint64_t rx_9217b_16383b_frames;
17894 /* Total number of frames received */
17895 uint64_t rx_total_frames;
17896 /* Total number of unicast frames received */
17897 uint64_t rx_ucast_frames;
17898 /* Total number of multicast frames received */
17899 uint64_t rx_mcast_frames;
17900 /* Total number of broadcast frames received */
17901 uint64_t rx_bcast_frames;
17902 /* Total number of received frames with FCS error */
17903 uint64_t rx_fcs_err_frames;
17904 /* Total number of control frames received */
17905 uint64_t rx_ctrl_frames;
17906 /* Total number of PAUSE frames received */
17907 uint64_t rx_pause_frames;
17908 /* Total number of PFC frames received */
17909 uint64_t rx_pfc_frames;
17911 * Total number of frames received with an unsupported
17914 uint64_t rx_unsupported_opcode_frames;
17916 * Total number of frames received with an unsupported
17917 * DA for pause and PFC
17919 uint64_t rx_unsupported_da_pausepfc_frames;
17920 /* Total number of frames received with an unsupported SA */
17921 uint64_t rx_wrong_sa_frames;
17922 /* Total number of received packets with alignment error */
17923 uint64_t rx_align_err_frames;
17924 /* Total number of received frames with out-of-range length */
17925 uint64_t rx_oor_len_frames;
17926 /* Total number of received frames with error termination */
17927 uint64_t rx_code_err_frames;
17929 * Total number of received frames with a false carrier is
17930 * detected during idle, as defined by RX_ER samples active
17931 * and RXD is 0xE. The event is reported along with the
17932 * statistics generated on the next received frame. Only
17933 * one false carrier condition can be detected and logged
17936 * Carrier event, valid for 10M/100M speed modes only.
17938 uint64_t rx_false_carrier_frames;
17939 /* Total number of over-sized frames received */
17940 uint64_t rx_ovrsz_frames;
17941 /* Total number of jabber packets received */
17942 uint64_t rx_jbr_frames;
17943 /* Total number of received frames with MTU error */
17944 uint64_t rx_mtu_err_frames;
17945 /* Total number of received frames with CRC match */
17946 uint64_t rx_match_crc_frames;
17947 /* Total number of frames received promiscuously */
17948 uint64_t rx_promiscuous_frames;
17950 * Total number of received frames with one or two VLAN
17953 uint64_t rx_tagged_frames;
17954 /* Total number of received frames with two VLAN tags */
17955 uint64_t rx_double_tagged_frames;
17956 /* Total number of truncated frames received */
17957 uint64_t rx_trunc_frames;
17958 /* Total number of good frames (without errors) received */
17959 uint64_t rx_good_frames;
17961 * Total number of received PFC frames with transition from
17962 * XON to XOFF on Pri 0
17964 uint64_t rx_pfc_xon2xoff_frames_pri0;
17966 * Total number of received PFC frames with transition from
17967 * XON to XOFF on Pri 1
17969 uint64_t rx_pfc_xon2xoff_frames_pri1;
17971 * Total number of received PFC frames with transition from
17972 * XON to XOFF on Pri 2
17974 uint64_t rx_pfc_xon2xoff_frames_pri2;
17976 * Total number of received PFC frames with transition from
17977 * XON to XOFF on Pri 3
17979 uint64_t rx_pfc_xon2xoff_frames_pri3;
17981 * Total number of received PFC frames with transition from
17982 * XON to XOFF on Pri 4
17984 uint64_t rx_pfc_xon2xoff_frames_pri4;
17986 * Total number of received PFC frames with transition from
17987 * XON to XOFF on Pri 5
17989 uint64_t rx_pfc_xon2xoff_frames_pri5;
17991 * Total number of received PFC frames with transition from
17992 * XON to XOFF on Pri 6
17994 uint64_t rx_pfc_xon2xoff_frames_pri6;
17996 * Total number of received PFC frames with transition from
17997 * XON to XOFF on Pri 7
17999 uint64_t rx_pfc_xon2xoff_frames_pri7;
18001 * Total number of received PFC frames with PFC enabled
18004 uint64_t rx_pfc_ena_frames_pri0;
18006 * Total number of received PFC frames with PFC enabled
18009 uint64_t rx_pfc_ena_frames_pri1;
18011 * Total number of received PFC frames with PFC enabled
18014 uint64_t rx_pfc_ena_frames_pri2;
18016 * Total number of received PFC frames with PFC enabled
18019 uint64_t rx_pfc_ena_frames_pri3;
18021 * Total number of received PFC frames with PFC enabled
18024 uint64_t rx_pfc_ena_frames_pri4;
18026 * Total number of received PFC frames with PFC enabled
18029 uint64_t rx_pfc_ena_frames_pri5;
18031 * Total number of received PFC frames with PFC enabled
18034 uint64_t rx_pfc_ena_frames_pri6;
18036 * Total number of received PFC frames with PFC enabled
18039 uint64_t rx_pfc_ena_frames_pri7;
18040 /* Total Number of frames received with SCH CRC error */
18041 uint64_t rx_sch_crc_err_frames;
18042 /* Total Number of under-sized frames received */
18043 uint64_t rx_undrsz_frames;
18044 /* Total Number of fragmented frames received */
18045 uint64_t rx_frag_frames;
18046 /* Total number of RX EEE LPI Events */
18047 uint64_t rx_eee_lpi_events;
18048 /* EEE LPI Duration Counter on RX */
18049 uint64_t rx_eee_lpi_duration;
18051 * Total number of physical type Link Level Flow Control
18052 * (LLFC) messages received
18054 uint64_t rx_llfc_physical_msgs;
18056 * Total number of logical type Link Level Flow Control
18057 * (LLFC) messages received
18059 uint64_t rx_llfc_logical_msgs;
18061 * Total number of logical type Link Level Flow Control
18062 * (LLFC) messages received with CRC error
18064 uint64_t rx_llfc_msgs_with_crc_err;
18065 /* Total number of HCFC messages received */
18066 uint64_t rx_hcfc_msgs;
18067 /* Total number of HCFC messages received with CRC error */
18068 uint64_t rx_hcfc_msgs_with_crc_err;
18069 /* Total number of received bytes */
18071 /* Total number of bytes received in runt frames */
18072 uint64_t rx_runt_bytes;
18073 /* Total number of runt frames received */
18074 uint64_t rx_runt_frames;
18075 /* Total Rx Discards per Port reported by STATS block */
18076 uint64_t rx_stat_discard;
18077 uint64_t rx_stat_err;
18080 /********************
18081 * hwrm_port_qstats *
18082 ********************/
18085 /* hwrm_port_qstats_input (size:320b/40B) */
18086 struct hwrm_port_qstats_input {
18087 /* The HWRM command request type. */
18090 * The completion ring to send the completion event on. This should
18091 * be the NQ ID returned from the `nq_alloc` HWRM command.
18093 uint16_t cmpl_ring;
18095 * The sequence ID is used by the driver for tracking multiple
18096 * commands. This ID is treated as opaque data by the firmware and
18097 * the value is returned in the `hwrm_resp_hdr` upon completion.
18101 * The target ID of the command:
18102 * * 0x0-0xFFF8 - The function ID
18103 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
18104 * * 0xFFFD - Reserved for user-space HWRM interface
18107 uint16_t target_id;
18109 * A physical address pointer pointing to a host buffer that the
18110 * command's response data will be written. This can be either a host
18111 * physical address (HPA) or a guest physical address (GPA) and must
18112 * point to a physically contiguous block of memory.
18114 uint64_t resp_addr;
18115 /* Port ID of port that is being queried. */
18118 /* This value is not used to avoid backward compatibility issues. */
18119 #define HWRM_PORT_QSTATS_INPUT_FLAGS_UNUSED UINT32_C(0x0)
18121 * This bit is set to 1 when request is for a counter mask,
18122 * representing the width of each of the stats counters, rather
18123 * than counters themselves.
18125 #define HWRM_PORT_QSTATS_INPUT_FLAGS_COUNTER_MASK UINT32_C(0x1)
18126 #define HWRM_PORT_QSTATS_INPUT_FLAGS_LAST \
18127 HWRM_PORT_QSTATS_INPUT_FLAGS_COUNTER_MASK
18128 uint8_t unused_0[5];
18130 * This is the host address where
18131 * Tx port statistics will be stored
18133 uint64_t tx_stat_host_addr;
18135 * This is the host address where
18136 * Rx port statistics will be stored
18138 uint64_t rx_stat_host_addr;
18141 /* hwrm_port_qstats_output (size:128b/16B) */
18142 struct hwrm_port_qstats_output {
18143 /* The specific error status for the command. */
18144 uint16_t error_code;
18145 /* The HWRM command request type. */
18147 /* The sequence ID from the original command. */
18149 /* The length of the response data in number of bytes. */
18151 /* The size of TX port statistics block in bytes. */
18152 uint16_t tx_stat_size;
18153 /* The size of RX port statistics block in bytes. */
18154 uint16_t rx_stat_size;
18155 uint8_t unused_0[3];
18157 * This field is used in Output records to indicate that the output
18158 * is completely written to RAM. This field should be read as '1'
18159 * to indicate that the output has been completely written.
18160 * When writing a command completion or response to an internal processor,
18161 * the order of writes has to be such that this field is written last.
18166 /* Port Tx Statistics extended Format */
18167 /* tx_port_stats_ext (size:2048b/256B) */
18168 struct tx_port_stats_ext {
18169 /* Total number of tx bytes count on cos queue 0 */
18170 uint64_t tx_bytes_cos0;
18171 /* Total number of tx bytes count on cos queue 1 */
18172 uint64_t tx_bytes_cos1;
18173 /* Total number of tx bytes count on cos queue 2 */
18174 uint64_t tx_bytes_cos2;
18175 /* Total number of tx bytes count on cos queue 3 */
18176 uint64_t tx_bytes_cos3;
18177 /* Total number of tx bytes count on cos queue 4 */
18178 uint64_t tx_bytes_cos4;
18179 /* Total number of tx bytes count on cos queue 5 */
18180 uint64_t tx_bytes_cos5;
18181 /* Total number of tx bytes count on cos queue 6 */
18182 uint64_t tx_bytes_cos6;
18183 /* Total number of tx bytes count on cos queue 7 */
18184 uint64_t tx_bytes_cos7;
18185 /* Total number of tx packets count on cos queue 0 */
18186 uint64_t tx_packets_cos0;
18187 /* Total number of tx packets count on cos queue 1 */
18188 uint64_t tx_packets_cos1;
18189 /* Total number of tx packets count on cos queue 2 */
18190 uint64_t tx_packets_cos2;
18191 /* Total number of tx packets count on cos queue 3 */
18192 uint64_t tx_packets_cos3;
18193 /* Total number of tx packets count on cos queue 4 */
18194 uint64_t tx_packets_cos4;
18195 /* Total number of tx packets count on cos queue 5 */
18196 uint64_t tx_packets_cos5;
18197 /* Total number of tx packets count on cos queue 6 */
18198 uint64_t tx_packets_cos6;
18199 /* Total number of tx packets count on cos queue 7 */
18200 uint64_t tx_packets_cos7;
18201 /* time duration between transmitting a XON -> XOFF and a subsequent XOFF -> XON for priority 0 */
18202 uint64_t pfc_pri0_tx_duration_us;
18203 /* Number of times, a XON -> XOFF and XOFF -> XON transitions occur for priority 0 */
18204 uint64_t pfc_pri0_tx_transitions;
18205 /* time duration between transmitting a XON -> XOFF and a subsequent XOFF -> XON for priority 1 */
18206 uint64_t pfc_pri1_tx_duration_us;
18207 /* Number of times, a XON -> XOFF and XOFF -> XON transitions occur for priority 1 */
18208 uint64_t pfc_pri1_tx_transitions;
18209 /* time duration between transmitting a XON -> XOFF and a subsequent XOFF -> XON for priority 2 */
18210 uint64_t pfc_pri2_tx_duration_us;
18211 /* Number of times, a XON -> XOFF and XOFF -> XON transitions occur for priority 2 */
18212 uint64_t pfc_pri2_tx_transitions;
18213 /* time duration between transmitting a XON -> XOFF and a subsequent XOFF -> XON for priority 3 */
18214 uint64_t pfc_pri3_tx_duration_us;
18215 /* Number of times, a XON -> XOFF and XOFF -> XON transitions occur for priority 3 */
18216 uint64_t pfc_pri3_tx_transitions;
18217 /* time duration between transmitting a XON -> XOFF and a subsequent XOFF -> XON for priority 4 */
18218 uint64_t pfc_pri4_tx_duration_us;
18219 /* Number of times, a XON -> XOFF and XOFF -> XON transitions occur for priority 4 */
18220 uint64_t pfc_pri4_tx_transitions;
18221 /* time duration between transmitting a XON -> XOFF and a subsequent XOFF -> XON for priority 5 */
18222 uint64_t pfc_pri5_tx_duration_us;
18223 /* Number of times, a XON -> XOFF and XOFF -> XON transitions occur for priority 5 */
18224 uint64_t pfc_pri5_tx_transitions;
18225 /* time duration between transmitting a XON -> XOFF and a subsequent XOFF -> XON for priority 6 */
18226 uint64_t pfc_pri6_tx_duration_us;
18227 /* Number of times, a XON -> XOFF and XOFF -> XON transitions occur for priority 6 */
18228 uint64_t pfc_pri6_tx_transitions;
18229 /* time duration between transmitting a XON -> XOFF and a subsequent XOFF -> XON for priority 7 */
18230 uint64_t pfc_pri7_tx_duration_us;
18231 /* Number of times, a XON -> XOFF and XOFF -> XON transitions occur for priority 7 */
18232 uint64_t pfc_pri7_tx_transitions;
18235 /* Port Rx Statistics extended Format */
18236 /* rx_port_stats_ext (size:3648b/456B) */
18237 struct rx_port_stats_ext {
18238 /* Number of times link state changed to down */
18239 uint64_t link_down_events;
18240 /* Number of times the idle rings with pause bit are found */
18241 uint64_t continuous_pause_events;
18242 /* Number of times the active rings pause bit resumed back */
18243 uint64_t resume_pause_events;
18244 /* Number of times, the ROCE cos queue PFC is disabled to avoid pause flood/burst */
18245 uint64_t continuous_roce_pause_events;
18246 /* Number of times, the ROCE cos queue PFC is enabled back */
18247 uint64_t resume_roce_pause_events;
18248 /* Total number of rx bytes count on cos queue 0 */
18249 uint64_t rx_bytes_cos0;
18250 /* Total number of rx bytes count on cos queue 1 */
18251 uint64_t rx_bytes_cos1;
18252 /* Total number of rx bytes count on cos queue 2 */
18253 uint64_t rx_bytes_cos2;
18254 /* Total number of rx bytes count on cos queue 3 */
18255 uint64_t rx_bytes_cos3;
18256 /* Total number of rx bytes count on cos queue 4 */
18257 uint64_t rx_bytes_cos4;
18258 /* Total number of rx bytes count on cos queue 5 */
18259 uint64_t rx_bytes_cos5;
18260 /* Total number of rx bytes count on cos queue 6 */
18261 uint64_t rx_bytes_cos6;
18262 /* Total number of rx bytes count on cos queue 7 */
18263 uint64_t rx_bytes_cos7;
18264 /* Total number of rx packets count on cos queue 0 */
18265 uint64_t rx_packets_cos0;
18266 /* Total number of rx packets count on cos queue 1 */
18267 uint64_t rx_packets_cos1;
18268 /* Total number of rx packets count on cos queue 2 */
18269 uint64_t rx_packets_cos2;
18270 /* Total number of rx packets count on cos queue 3 */
18271 uint64_t rx_packets_cos3;
18272 /* Total number of rx packets count on cos queue 4 */
18273 uint64_t rx_packets_cos4;
18274 /* Total number of rx packets count on cos queue 5 */
18275 uint64_t rx_packets_cos5;
18276 /* Total number of rx packets count on cos queue 6 */
18277 uint64_t rx_packets_cos6;
18278 /* Total number of rx packets count on cos queue 7 */
18279 uint64_t rx_packets_cos7;
18280 /* time duration receiving a XON -> XOFF and a subsequent XOFF -> XON for priority 0 */
18281 uint64_t pfc_pri0_rx_duration_us;
18282 /* Number of times, a XON -> XOFF and XOFF -> XON transitions occur for priority 0 */
18283 uint64_t pfc_pri0_rx_transitions;
18284 /* time duration receiving a XON -> XOFF and a subsequent XOFF -> XON for priority 1 */
18285 uint64_t pfc_pri1_rx_duration_us;
18286 /* Number of times, a XON -> XOFF and XOFF -> XON transitions occur for priority 1 */
18287 uint64_t pfc_pri1_rx_transitions;
18288 /* time duration receiving a XON -> XOFF and a subsequent XOFF -> XON for priority 2 */
18289 uint64_t pfc_pri2_rx_duration_us;
18290 /* Number of times, a XON -> XOFF and XOFF -> XON transitions occur for priority 2 */
18291 uint64_t pfc_pri2_rx_transitions;
18292 /* time duration receiving a XON -> XOFF and a subsequent XOFF -> XON for priority 3 */
18293 uint64_t pfc_pri3_rx_duration_us;
18294 /* Number of times, a XON -> XOFF and XOFF -> XON transitions occur for priority 3 */
18295 uint64_t pfc_pri3_rx_transitions;
18296 /* time duration receiving a XON -> XOFF and a subsequent XOFF -> XON for priority 4 */
18297 uint64_t pfc_pri4_rx_duration_us;
18298 /* Number of times, a XON -> XOFF and XOFF -> XON transitions occur for priority 4 */
18299 uint64_t pfc_pri4_rx_transitions;
18300 /* time duration receiving a XON -> XOFF and a subsequent XOFF -> XON for priority 5 */
18301 uint64_t pfc_pri5_rx_duration_us;
18302 /* Number of times, a XON -> XOFF and XOFF -> XON transitions occur for priority 5 */
18303 uint64_t pfc_pri5_rx_transitions;
18304 /* time duration receiving a XON -> XOFF and a subsequent XOFF -> XON for priority 6 */
18305 uint64_t pfc_pri6_rx_duration_us;
18306 /* Number of times, a XON -> XOFF and XOFF -> XON transitions occur for priority 6 */
18307 uint64_t pfc_pri6_rx_transitions;
18308 /* time duration receiving a XON -> XOFF and a subsequent XOFF -> XON for priority 7 */
18309 uint64_t pfc_pri7_rx_duration_us;
18310 /* Number of times, a XON -> XOFF and XOFF -> XON transitions occur for priority 7 */
18311 uint64_t pfc_pri7_rx_transitions;
18312 /* Total number of received bits */
18314 /* The number of events where the port receive buffer was over 85% full */
18315 uint64_t rx_buffer_passed_threshold;
18317 * The number of symbol errors that wasn't corrected by FEC correction
18320 uint64_t rx_pcs_symbol_err;
18321 /* The number of corrected bits on the port according to active FEC */
18322 uint64_t rx_corrected_bits;
18323 /* Total number of rx discard bytes count on cos queue 0 */
18324 uint64_t rx_discard_bytes_cos0;
18325 /* Total number of rx discard bytes count on cos queue 1 */
18326 uint64_t rx_discard_bytes_cos1;
18327 /* Total number of rx discard bytes count on cos queue 2 */
18328 uint64_t rx_discard_bytes_cos2;
18329 /* Total number of rx discard bytes count on cos queue 3 */
18330 uint64_t rx_discard_bytes_cos3;
18331 /* Total number of rx discard bytes count on cos queue 4 */
18332 uint64_t rx_discard_bytes_cos4;
18333 /* Total number of rx discard bytes count on cos queue 5 */
18334 uint64_t rx_discard_bytes_cos5;
18335 /* Total number of rx discard bytes count on cos queue 6 */
18336 uint64_t rx_discard_bytes_cos6;
18337 /* Total number of rx discard bytes count on cos queue 7 */
18338 uint64_t rx_discard_bytes_cos7;
18339 /* Total number of rx discard packets count on cos queue 0 */
18340 uint64_t rx_discard_packets_cos0;
18341 /* Total number of rx discard packets count on cos queue 1 */
18342 uint64_t rx_discard_packets_cos1;
18343 /* Total number of rx discard packets count on cos queue 2 */
18344 uint64_t rx_discard_packets_cos2;
18345 /* Total number of rx discard packets count on cos queue 3 */
18346 uint64_t rx_discard_packets_cos3;
18347 /* Total number of rx discard packets count on cos queue 4 */
18348 uint64_t rx_discard_packets_cos4;
18349 /* Total number of rx discard packets count on cos queue 5 */
18350 uint64_t rx_discard_packets_cos5;
18351 /* Total number of rx discard packets count on cos queue 6 */
18352 uint64_t rx_discard_packets_cos6;
18353 /* Total number of rx discard packets count on cos queue 7 */
18354 uint64_t rx_discard_packets_cos7;
18358 * Port Rx Statistics extended PFC WatchDog Format.
18359 * StormDetect and StormRevert event determination is based
18360 * on an integration period and a percentage threshold.
18361 * StormDetect event - when percentage of XOFF frames received
18362 * within an integration period exceeds the configured threshold.
18363 * StormRevert event - when percentage of XON frames received
18364 * within an integration period exceeds the configured threshold.
18365 * Actual number of XOFF/XON frames for the events to be triggered
18366 * depends on both configured integration period and sampling rate.
18367 * The statistics in this structure represent counts of specified
18368 * events from the moment the feature (PFC WatchDog) is enabled via
18369 * hwrm_queue_pfc_enable_cfg call.
18371 /* rx_port_stats_ext_pfc_wd (size:5120b/640B) */
18372 struct rx_port_stats_ext_pfc_wd {
18374 * Total number of PFC WatchDog StormDetect events detected
18377 uint64_t rx_pfc_watchdog_storms_detected_pri0;
18379 * Total number of PFC WatchDog StormDetect events detected
18382 uint64_t rx_pfc_watchdog_storms_detected_pri1;
18384 * Total number of PFC WatchDog StormDetect events detected
18387 uint64_t rx_pfc_watchdog_storms_detected_pri2;
18389 * Total number of PFC WatchDog StormDetect events detected
18392 uint64_t rx_pfc_watchdog_storms_detected_pri3;
18394 * Total number of PFC WatchDog StormDetect events detected
18397 uint64_t rx_pfc_watchdog_storms_detected_pri4;
18399 * Total number of PFC WatchDog StormDetect events detected
18402 uint64_t rx_pfc_watchdog_storms_detected_pri5;
18404 * Total number of PFC WatchDog StormDetect events detected
18407 uint64_t rx_pfc_watchdog_storms_detected_pri6;
18409 * Total number of PFC WatchDog StormDetect events detected
18412 uint64_t rx_pfc_watchdog_storms_detected_pri7;
18414 * Total number of PFC WatchDog StormRevert events detected
18417 uint64_t rx_pfc_watchdog_storms_reverted_pri0;
18419 * Total number of PFC WatchDog StormRevert events detected
18422 uint64_t rx_pfc_watchdog_storms_reverted_pri1;
18424 * Total number of PFC WatchDog StormRevert events detected
18427 uint64_t rx_pfc_watchdog_storms_reverted_pri2;
18429 * Total number of PFC WatchDog StormRevert events detected
18432 uint64_t rx_pfc_watchdog_storms_reverted_pri3;
18434 * Total number of PFC WatchDog StormRevert events detected
18437 uint64_t rx_pfc_watchdog_storms_reverted_pri4;
18439 * Total number of PFC WatchDog StormRevert events detected
18442 uint64_t rx_pfc_watchdog_storms_reverted_pri5;
18444 * Total number of PFC WatchDog StormRevert events detected
18447 uint64_t rx_pfc_watchdog_storms_reverted_pri6;
18449 * Total number of PFC WatchDog StormRevert events detected
18452 uint64_t rx_pfc_watchdog_storms_reverted_pri7;
18454 * Total number of packets received during PFC watchdog storm
18457 uint64_t rx_pfc_watchdog_storms_rx_packets_pri0;
18459 * Total number of packets received during PFC watchdog storm
18462 uint64_t rx_pfc_watchdog_storms_rx_packets_pri1;
18464 * Total number of packets received during PFC watchdog storm
18467 uint64_t rx_pfc_watchdog_storms_rx_packets_pri2;
18469 * Total number of packets received during PFC watchdog storm
18472 uint64_t rx_pfc_watchdog_storms_rx_packets_pri3;
18474 * Total number of packets received during PFC watchdog storm
18477 uint64_t rx_pfc_watchdog_storms_rx_packets_pri4;
18479 * Total number of packets received during PFC watchdog storm
18482 uint64_t rx_pfc_watchdog_storms_rx_packets_pri5;
18484 * Total number of packets received during PFC watchdog storm
18487 uint64_t rx_pfc_watchdog_storms_rx_packets_pri6;
18489 * Total number of packets received during PFC watchdog storm
18492 uint64_t rx_pfc_watchdog_storms_rx_packets_pri7;
18494 * Total number of bytes received during PFC watchdog storm
18497 uint64_t rx_pfc_watchdog_storms_rx_bytes_pri0;
18499 * Total number of bytes received during PFC watchdog storm
18502 uint64_t rx_pfc_watchdog_storms_rx_bytes_pri1;
18504 * Total number of bytes received during PFC watchdog storm
18507 uint64_t rx_pfc_watchdog_storms_rx_bytes_pri2;
18509 * Total number of bytes received during PFC watchdog storm
18512 uint64_t rx_pfc_watchdog_storms_rx_bytes_pri3;
18514 * Total number of bytes received during PFC watchdog storm
18517 uint64_t rx_pfc_watchdog_storms_rx_bytes_pri4;
18519 * Total number of bytes received during PFC watchdog storm
18522 uint64_t rx_pfc_watchdog_storms_rx_bytes_pri5;
18524 * Total number of bytes received during PFC watchdog storm
18527 uint64_t rx_pfc_watchdog_storms_rx_bytes_pri6;
18529 * Total number of bytes received during PFC watchdog storm
18532 uint64_t rx_pfc_watchdog_storms_rx_bytes_pri7;
18534 * Total number of packets dropped on rx during PFC watchdog storm
18537 uint64_t rx_pfc_watchdog_storms_rx_packets_dropped_pri0;
18539 * Total number of packets dropped on rx during PFC watchdog storm
18542 uint64_t rx_pfc_watchdog_storms_rx_packets_dropped_pri1;
18544 * Total number of packets dropped on rx during PFC watchdog storm
18547 uint64_t rx_pfc_watchdog_storms_rx_packets_dropped_pri2;
18549 * Total number of packets dropped on rx during PFC watchdog storm
18552 uint64_t rx_pfc_watchdog_storms_rx_packets_dropped_pri3;
18554 * Total number of packets dropped on rx during PFC watchdog storm
18557 uint64_t rx_pfc_watchdog_storms_rx_packets_dropped_pri4;
18559 * Total number of packets dropped on rx during PFC watchdog storm
18562 uint64_t rx_pfc_watchdog_storms_rx_packets_dropped_pri5;
18564 * Total number of packets dropped on rx during PFC watchdog storm
18567 uint64_t rx_pfc_watchdog_storms_rx_packets_dropped_pri6;
18569 * Total number of packets dropped on rx during PFC watchdog storm
18572 uint64_t rx_pfc_watchdog_storms_rx_packets_dropped_pri7;
18574 * Total number of bytes dropped on rx during PFC watchdog storm
18577 uint64_t rx_pfc_watchdog_storms_rx_bytes_dropped_pri0;
18579 * Total number of bytes dropped on rx during PFC watchdog storm
18582 uint64_t rx_pfc_watchdog_storms_rx_bytes_dropped_pri1;
18584 * Total number of bytes dropped on rx during PFC watchdog storm
18587 uint64_t rx_pfc_watchdog_storms_rx_bytes_dropped_pri2;
18589 * Total number of bytes dropped on rx during PFC watchdog storm
18592 uint64_t rx_pfc_watchdog_storms_rx_bytes_dropped_pri3;
18594 * Total number of bytes dropped on rx during PFC watchdog storm
18597 uint64_t rx_pfc_watchdog_storms_rx_bytes_dropped_pri4;
18599 * Total number of bytes dropped on rx during PFC watchdog storm
18602 uint64_t rx_pfc_watchdog_storms_rx_bytes_dropped_pri5;
18604 * Total number of bytes dropped on rx during PFC watchdog storm
18607 uint64_t rx_pfc_watchdog_storms_rx_bytes_dropped_pri6;
18609 * Total number of bytes dropped on rx during PFC watchdog storm
18612 uint64_t rx_pfc_watchdog_storms_rx_bytes_dropped_pri7;
18614 * Number of packets received during last PFC watchdog storm
18617 uint64_t rx_pfc_watchdog_last_storm_rx_packets_pri0;
18619 * Number of packets received during last PFC watchdog storm
18622 uint64_t rx_pfc_watchdog_last_storm_rx_packets_pri1;
18624 * Number of packets received during last PFC watchdog storm
18627 uint64_t rx_pfc_watchdog_last_storm_rx_packets_pri2;
18629 * Number of packets received during last PFC watchdog storm
18632 uint64_t rx_pfc_watchdog_last_storm_rx_packets_pri3;
18634 * Number of packets received during last PFC watchdog storm
18637 uint64_t rx_pfc_watchdog_last_storm_rx_packets_pri4;
18639 * Number of packets received during last PFC watchdog storm
18642 uint64_t rx_pfc_watchdog_last_storm_rx_packets_pri5;
18644 * Number of packets received during last PFC watchdog storm
18647 uint64_t rx_pfc_watchdog_last_storm_rx_packets_pri6;
18649 * Number of packets received during last PFC watchdog storm
18652 uint64_t rx_pfc_watchdog_last_storm_rx_packets_pri7;
18654 * Number of bytes received during last PFC watchdog storm
18657 uint64_t rx_pfc_watchdog_last_storm_rx_bytes_pri0;
18659 * Number of bytes received during last PFC watchdog storm
18662 uint64_t rx_pfc_watchdog_last_storm_rx_bytes_pri1;
18664 * Number of bytes received during last PFC watchdog storm
18667 uint64_t rx_pfc_watchdog_last_storm_rx_bytes_pri2;
18669 * Number of bytes received during last PFC watchdog storm
18672 uint64_t rx_pfc_watchdog_last_storm_rx_bytes_pri3;
18674 * Number of bytes received during last PFC watchdog storm
18677 uint64_t rx_pfc_watchdog_last_storm_rx_bytes_pri4;
18679 * Number of bytes received during last PFC watchdog storm
18682 uint64_t rx_pfc_watchdog_last_storm_rx_bytes_pri5;
18684 * Number of bytes received during last PFC watchdog storm
18687 uint64_t rx_pfc_watchdog_last_storm_rx_bytes_pri6;
18689 * Number of bytes received during last PFC watchdog storm
18692 uint64_t rx_pfc_watchdog_last_storm_rx_bytes_pri7;
18694 * Number of packets dropped on rx during last PFC watchdog storm
18697 uint64_t rx_pfc_watchdog_last_storm_rx_packets_dropped_pri0;
18699 * Number of packets dropped on rx during last PFC watchdog storm
18702 uint64_t rx_pfc_watchdog_last_storm_rx_packets_dropped_pri1;
18704 * Number of packets dropped on rx during last PFC watchdog storm
18707 uint64_t rx_pfc_watchdog_last_storm_rx_packets_dropped_pri2;
18709 * Number of packets dropped on rx during last PFC watchdog storm
18712 uint64_t rx_pfc_watchdog_last_storm_rx_packets_dropped_pri3;
18714 * Number of packets dropped on rx during last PFC watchdog storm
18717 uint64_t rx_pfc_watchdog_last_storm_rx_packets_dropped_pri4;
18719 * Number of packets dropped on rx during last PFC watchdog storm
18722 uint64_t rx_pfc_watchdog_last_storm_rx_packets_dropped_pri5;
18724 * Number of packets dropped on rx during last PFC watchdog storm
18727 uint64_t rx_pfc_watchdog_last_storm_rx_packets_dropped_pri6;
18729 * Number of packets dropped on rx during last PFC watchdog storm
18732 uint64_t rx_pfc_watchdog_last_storm_rx_packets_dropped_pri7;
18734 * Total number of bytes dropped on rx during PFC watchdog storm
18737 uint64_t rx_pfc_watchdog_last_storm_rx_bytes_dropped_pri0;
18739 * Number of bytes dropped on rx during last PFC watchdog storm
18742 uint64_t rx_pfc_watchdog_last_storm_rx_bytes_dropped_pri1;
18744 * Number of bytes dropped on rx during last PFC watchdog storm
18747 uint64_t rx_pfc_watchdog_last_storm_rx_bytes_dropped_pri2;
18749 * Number of bytes dropped on rx during last PFC watchdog storm
18752 uint64_t rx_pfc_watchdog_last_storm_rx_bytes_dropped_pri3;
18754 * Number of bytes dropped on rx during last PFC watchdog storm
18757 uint64_t rx_pfc_watchdog_last_storm_rx_bytes_dropped_pri4;
18759 * Number of bytes dropped on rx during last PFC watchdog storm
18762 uint64_t rx_pfc_watchdog_last_storm_rx_bytes_dropped_pri5;
18764 * Number of bytes dropped on rx during last PFC watchdog storm
18767 uint64_t rx_pfc_watchdog_last_storm_rx_bytes_dropped_pri6;
18769 * Number of bytes dropped on rx during last PFC watchdog storm
18772 uint64_t rx_pfc_watchdog_last_storm_rx_bytes_dropped_pri7;
18775 /************************
18776 * hwrm_port_qstats_ext *
18777 ************************/
18780 /* hwrm_port_qstats_ext_input (size:320b/40B) */
18781 struct hwrm_port_qstats_ext_input {
18782 /* The HWRM command request type. */
18785 * The completion ring to send the completion event on. This should
18786 * be the NQ ID returned from the `nq_alloc` HWRM command.
18788 uint16_t cmpl_ring;
18790 * The sequence ID is used by the driver for tracking multiple
18791 * commands. This ID is treated as opaque data by the firmware and
18792 * the value is returned in the `hwrm_resp_hdr` upon completion.
18796 * The target ID of the command:
18797 * * 0x0-0xFFF8 - The function ID
18798 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
18799 * * 0xFFFD - Reserved for user-space HWRM interface
18802 uint16_t target_id;
18804 * A physical address pointer pointing to a host buffer that the
18805 * command's response data will be written. This can be either a host
18806 * physical address (HPA) or a guest physical address (GPA) and must
18807 * point to a physically contiguous block of memory.
18809 uint64_t resp_addr;
18810 /* Port ID of port that is being queried. */
18813 * The size of TX port extended
18814 * statistics block in bytes.
18816 uint16_t tx_stat_size;
18818 * The size of RX port extended
18819 * statistics block in bytes
18821 uint16_t rx_stat_size;
18823 /* This value is not used to avoid backward compatibility issues. */
18824 #define HWRM_PORT_QSTATS_EXT_INPUT_FLAGS_UNUSED UINT32_C(0x0)
18826 * This bit is set to 1 when request is for the counter mask,
18827 * representing width of each of the stats counters, rather than
18828 * counters themselves.
18830 #define HWRM_PORT_QSTATS_EXT_INPUT_FLAGS_COUNTER_MASK UINT32_C(0x1)
18831 #define HWRM_PORT_QSTATS_EXT_INPUT_FLAGS_LAST \
18832 HWRM_PORT_QSTATS_EXT_INPUT_FLAGS_COUNTER_MASK
18835 * This is the host address where
18836 * Tx port statistics will be stored
18838 uint64_t tx_stat_host_addr;
18840 * This is the host address where
18841 * Rx port statistics will be stored
18843 uint64_t rx_stat_host_addr;
18846 /* hwrm_port_qstats_ext_output (size:128b/16B) */
18847 struct hwrm_port_qstats_ext_output {
18848 /* The specific error status for the command. */
18849 uint16_t error_code;
18850 /* The HWRM command request type. */
18852 /* The sequence ID from the original command. */
18854 /* The length of the response data in number of bytes. */
18856 /* The size of TX port statistics block in bytes. */
18857 uint16_t tx_stat_size;
18858 /* The size of RX port statistics block in bytes. */
18859 uint16_t rx_stat_size;
18860 /* Total number of active cos queues available. */
18861 uint16_t total_active_cos_queues;
18864 * If set to 1, then this field indicates that clear
18865 * roce specific counters is supported.
18867 #define HWRM_PORT_QSTATS_EXT_OUTPUT_FLAGS_CLEAR_ROCE_COUNTERS_SUPPORTED \
18870 * This field is used in Output records to indicate that the output
18871 * is completely written to RAM. This field should be read as '1'
18872 * to indicate that the output has been completely written.
18873 * When writing a command completion or response to an internal processor,
18874 * the order of writes has to be such that this field is written last.
18879 /*******************************
18880 * hwrm_port_qstats_ext_pfc_wd *
18881 *******************************/
18884 /* hwrm_port_qstats_ext_pfc_wd_input (size:256b/32B) */
18885 struct hwrm_port_qstats_ext_pfc_wd_input {
18886 /* The HWRM command request type. */
18889 * The completion ring to send the completion event on. This should
18890 * be the NQ ID returned from the `nq_alloc` HWRM command.
18892 uint16_t cmpl_ring;
18894 * The sequence ID is used by the driver for tracking multiple
18895 * commands. This ID is treated as opaque data by the firmware and
18896 * the value is returned in the `hwrm_resp_hdr` upon completion.
18900 * The target ID of the command:
18901 * * 0x0-0xFFF8 - The function ID
18902 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
18903 * * 0xFFFD - Reserved for user-space HWRM interface
18906 uint16_t target_id;
18908 * A physical address pointer pointing to a host buffer that the
18909 * command's response data will be written. This can be either a host
18910 * physical address (HPA) or a guest physical address (GPA) and must
18911 * point to a physically contiguous block of memory.
18913 uint64_t resp_addr;
18914 /* Port ID of port that is being queried. */
18917 * The size of rx_port_stats_ext_pfc_wd
18920 uint16_t pfc_wd_stat_size;
18921 uint8_t unused_0[4];
18923 * This is the host address where
18924 * rx_port_stats_ext_pfc_wd will be stored
18926 uint64_t pfc_wd_stat_host_addr;
18929 /* hwrm_port_qstats_ext_pfc_wd_output (size:128b/16B) */
18930 struct hwrm_port_qstats_ext_pfc_wd_output {
18931 /* The specific error status for the command. */
18932 uint16_t error_code;
18933 /* The HWRM command request type. */
18935 /* The sequence ID from the original command. */
18937 /* The length of the response data in number of bytes. */
18940 * The size of rx_port_stats_ext_pfc_wd
18941 * statistics block in bytes.
18943 uint16_t pfc_wd_stat_size;
18946 * This field is used in Output records to indicate that the output
18947 * is completely written to RAM. This field should be read as '1'
18948 * to indicate that the output has been completely written.
18949 * When writing a command completion or response to an internal processor,
18950 * the order of writes has to be such that this field is written last.
18953 uint8_t unused_0[4];
18956 /*************************
18957 * hwrm_port_lpbk_qstats *
18958 *************************/
18961 /* hwrm_port_lpbk_qstats_input (size:128b/16B) */
18962 struct hwrm_port_lpbk_qstats_input {
18963 /* The HWRM command request type. */
18966 * The completion ring to send the completion event on. This should
18967 * be the NQ ID returned from the `nq_alloc` HWRM command.
18969 uint16_t cmpl_ring;
18971 * The sequence ID is used by the driver for tracking multiple
18972 * commands. This ID is treated as opaque data by the firmware and
18973 * the value is returned in the `hwrm_resp_hdr` upon completion.
18977 * The target ID of the command:
18978 * * 0x0-0xFFF8 - The function ID
18979 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
18980 * * 0xFFFD - Reserved for user-space HWRM interface
18983 uint16_t target_id;
18985 * A physical address pointer pointing to a host buffer that the
18986 * command's response data will be written. This can be either a host
18987 * physical address (HPA) or a guest physical address (GPA) and must
18988 * point to a physically contiguous block of memory.
18990 uint64_t resp_addr;
18993 /* hwrm_port_lpbk_qstats_output (size:768b/96B) */
18994 struct hwrm_port_lpbk_qstats_output {
18995 /* The specific error status for the command. */
18996 uint16_t error_code;
18997 /* The HWRM command request type. */
18999 /* The sequence ID from the original command. */
19001 /* The length of the response data in number of bytes. */
19003 /* Number of transmitted unicast frames */
19004 uint64_t lpbk_ucast_frames;
19005 /* Number of transmitted multicast frames */
19006 uint64_t lpbk_mcast_frames;
19007 /* Number of transmitted broadcast frames */
19008 uint64_t lpbk_bcast_frames;
19009 /* Number of transmitted bytes for unicast traffic */
19010 uint64_t lpbk_ucast_bytes;
19011 /* Number of transmitted bytes for multicast traffic */
19012 uint64_t lpbk_mcast_bytes;
19013 /* Number of transmitted bytes for broadcast traffic */
19014 uint64_t lpbk_bcast_bytes;
19015 /* Total Tx Drops for loopback traffic reported by STATS block */
19016 uint64_t tx_stat_discard;
19017 /* Total Tx Error Drops for loopback traffic reported by STATS block */
19018 uint64_t tx_stat_error;
19019 /* Total Rx Drops for loopback traffic reported by STATS block */
19020 uint64_t rx_stat_discard;
19021 /* Total Rx Error Drops for loopback traffic reported by STATS block */
19022 uint64_t rx_stat_error;
19023 uint8_t unused_0[7];
19025 * This field is used in Output records to indicate that the output
19026 * is completely written to RAM. This field should be read as '1'
19027 * to indicate that the output has been completely written.
19028 * When writing a command completion or response to an internal processor,
19029 * the order of writes has to be such that this field is written last.
19034 /************************
19035 * hwrm_port_ecn_qstats *
19036 ************************/
19039 /* hwrm_port_ecn_qstats_input (size:192b/24B) */
19040 struct hwrm_port_ecn_qstats_input {
19041 /* The HWRM command request type. */
19044 * The completion ring to send the completion event on. This should
19045 * be the NQ ID returned from the `nq_alloc` HWRM command.
19047 uint16_t cmpl_ring;
19049 * The sequence ID is used by the driver for tracking multiple
19050 * commands. This ID is treated as opaque data by the firmware and
19051 * the value is returned in the `hwrm_resp_hdr` upon completion.
19055 * The target ID of the command:
19056 * * 0x0-0xFFF8 - The function ID
19057 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
19058 * * 0xFFFD - Reserved for user-space HWRM interface
19061 uint16_t target_id;
19063 * A physical address pointer pointing to a host buffer that the
19064 * command's response data will be written. This can be either a host
19065 * physical address (HPA) or a guest physical address (GPA) and must
19066 * point to a physically contiguous block of memory.
19068 uint64_t resp_addr;
19070 * Port ID of port that is being queried. Unused if NIC is in
19074 uint8_t unused_0[6];
19077 /* hwrm_port_ecn_qstats_output (size:384b/48B) */
19078 struct hwrm_port_ecn_qstats_output {
19079 /* The specific error status for the command. */
19080 uint16_t error_code;
19081 /* The HWRM command request type. */
19083 /* The sequence ID from the original command. */
19085 /* The length of the response data in number of bytes. */
19087 /* Number of packets marked in CoS queue 0. */
19088 uint32_t mark_cnt_cos0;
19089 /* Number of packets marked in CoS queue 1. */
19090 uint32_t mark_cnt_cos1;
19091 /* Number of packets marked in CoS queue 2. */
19092 uint32_t mark_cnt_cos2;
19093 /* Number of packets marked in CoS queue 3. */
19094 uint32_t mark_cnt_cos3;
19095 /* Number of packets marked in CoS queue 4. */
19096 uint32_t mark_cnt_cos4;
19097 /* Number of packets marked in CoS queue 5. */
19098 uint32_t mark_cnt_cos5;
19099 /* Number of packets marked in CoS queue 6. */
19100 uint32_t mark_cnt_cos6;
19101 /* Number of packets marked in CoS queue 7. */
19102 uint32_t mark_cnt_cos7;
19104 * Bitmask that indicates which CoS queues have ECN marking enabled.
19105 * Bit i corresponds to CoS queue i.
19108 uint8_t unused_0[6];
19110 * This field is used in Output records to indicate that the output
19111 * is completely written to RAM. This field should be read as '1'
19112 * to indicate that the output has been completely written.
19113 * When writing a command completion or response to an internal processor,
19114 * the order of writes has to be such that this field is written last.
19119 /***********************
19120 * hwrm_port_clr_stats *
19121 ***********************/
19124 /* hwrm_port_clr_stats_input (size:192b/24B) */
19125 struct hwrm_port_clr_stats_input {
19126 /* The HWRM command request type. */
19129 * The completion ring to send the completion event on. This should
19130 * be the NQ ID returned from the `nq_alloc` HWRM command.
19132 uint16_t cmpl_ring;
19134 * The sequence ID is used by the driver for tracking multiple
19135 * commands. This ID is treated as opaque data by the firmware and
19136 * the value is returned in the `hwrm_resp_hdr` upon completion.
19140 * The target ID of the command:
19141 * * 0x0-0xFFF8 - The function ID
19142 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
19143 * * 0xFFFD - Reserved for user-space HWRM interface
19146 uint16_t target_id;
19148 * A physical address pointer pointing to a host buffer that the
19149 * command's response data will be written. This can be either a host
19150 * physical address (HPA) or a guest physical address (GPA) and must
19151 * point to a physically contiguous block of memory.
19153 uint64_t resp_addr;
19154 /* Port ID of port that is being queried. */
19158 * If set to 1, then this field indicates clear the following RoCE
19159 * specific counters.
19160 * RoCE associated TX/RX cos counters
19161 * CNP associated TX/RX cos counters
19162 * RoCE/CNP specific TX/RX flow counters
19163 * Firmware will determine the RoCE/CNP cos queue based on qos profile.
19164 * This flag is honored only when RoCE is enabled on that port.
19166 #define HWRM_PORT_CLR_STATS_INPUT_FLAGS_ROCE_COUNTERS UINT32_C(0x1)
19167 uint8_t unused_0[5];
19170 /* hwrm_port_clr_stats_output (size:128b/16B) */
19171 struct hwrm_port_clr_stats_output {
19172 /* The specific error status for the command. */
19173 uint16_t error_code;
19174 /* The HWRM command request type. */
19176 /* The sequence ID from the original command. */
19178 /* The length of the response data in number of bytes. */
19180 uint8_t unused_0[7];
19182 * This field is used in Output records to indicate that the output
19183 * is completely written to RAM. This field should be read as '1'
19184 * to indicate that the output has been completely written.
19185 * When writing a command completion or response to an internal processor,
19186 * the order of writes has to be such that this field is written last.
19191 /***********************
19192 * hwrm_port_phy_qcaps *
19193 ***********************/
19196 /* hwrm_port_phy_qcaps_input (size:192b/24B) */
19197 struct hwrm_port_phy_qcaps_input {
19198 /* The HWRM command request type. */
19201 * The completion ring to send the completion event on. This should
19202 * be the NQ ID returned from the `nq_alloc` HWRM command.
19204 uint16_t cmpl_ring;
19206 * The sequence ID is used by the driver for tracking multiple
19207 * commands. This ID is treated as opaque data by the firmware and
19208 * the value is returned in the `hwrm_resp_hdr` upon completion.
19212 * The target ID of the command:
19213 * * 0x0-0xFFF8 - The function ID
19214 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
19215 * * 0xFFFD - Reserved for user-space HWRM interface
19218 uint16_t target_id;
19220 * A physical address pointer pointing to a host buffer that the
19221 * command's response data will be written. This can be either a host
19222 * physical address (HPA) or a guest physical address (GPA) and must
19223 * point to a physically contiguous block of memory.
19225 uint64_t resp_addr;
19226 /* Port ID of port that is being queried. */
19228 uint8_t unused_0[6];
19231 /* hwrm_port_phy_qcaps_output (size:192b/24B) */
19232 struct hwrm_port_phy_qcaps_output {
19233 /* The specific error status for the command. */
19234 uint16_t error_code;
19235 /* The HWRM command request type. */
19237 /* The sequence ID from the original command. */
19239 /* The length of the response data in number of bytes. */
19241 /* PHY capability flags */
19244 * If set to 1, then this field indicates that the
19245 * link is capable of supporting EEE.
19247 #define HWRM_PORT_PHY_QCAPS_OUTPUT_FLAGS_EEE_SUPPORTED \
19250 * If set to 1, then this field indicates that the
19251 * PHY is capable of supporting external loopback.
19253 #define HWRM_PORT_PHY_QCAPS_OUTPUT_FLAGS_EXTERNAL_LPBK_SUPPORTED \
19256 * If set to 1, then this field indicates that the
19257 * PHY is capable of supporting loopback in autoneg mode.
19259 #define HWRM_PORT_PHY_QCAPS_OUTPUT_FLAGS_AUTONEG_LPBK_SUPPORTED \
19262 * Indicates if the configuration of shared PHY settings is supported.
19263 * In cases where a physical port is shared by multiple functions
19264 * (e.g. NPAR, multihost, etc), the configuration of PHY
19265 * settings may not be allowed. Callers to HWRM_PORT_PHY_CFG will
19266 * get an HWRM_ERR_CODE_RESOURCE_ACCESS_DENIED error in this case.
19268 #define HWRM_PORT_PHY_QCAPS_OUTPUT_FLAGS_SHARED_PHY_CFG_SUPPORTED \
19271 * If set to 1, it indicates that the port counters and extended
19272 * port counters will not reset when the firmware shuts down or
19273 * resets the PHY. These counters will only be reset during power
19274 * cycle or by calling HWRM_PORT_CLR_STATS.
19275 * If set to 0, the state of the counters is unspecified when
19276 * firmware shuts down or resets the PHY.
19278 #define HWRM_PORT_PHY_QCAPS_OUTPUT_FLAGS_CUMULATIVE_COUNTERS_ON_RESET \
19281 * Reserved field. The HWRM shall set this field to 0.
19282 * An HWRM client shall ignore this field.
19284 #define HWRM_PORT_PHY_QCAPS_OUTPUT_FLAGS_RSVD1_MASK \
19286 #define HWRM_PORT_PHY_QCAPS_OUTPUT_FLAGS_RSVD1_SFT \
19288 /* Number of front panel ports for this device. */
19290 /* Not supported or unknown */
19291 #define HWRM_PORT_PHY_QCAPS_OUTPUT_PORT_CNT_UNKNOWN UINT32_C(0x0)
19292 /* single port device */
19293 #define HWRM_PORT_PHY_QCAPS_OUTPUT_PORT_CNT_1 UINT32_C(0x1)
19294 /* 2-port device */
19295 #define HWRM_PORT_PHY_QCAPS_OUTPUT_PORT_CNT_2 UINT32_C(0x2)
19296 /* 3-port device */
19297 #define HWRM_PORT_PHY_QCAPS_OUTPUT_PORT_CNT_3 UINT32_C(0x3)
19298 /* 4-port device */
19299 #define HWRM_PORT_PHY_QCAPS_OUTPUT_PORT_CNT_4 UINT32_C(0x4)
19300 #define HWRM_PORT_PHY_QCAPS_OUTPUT_PORT_CNT_LAST \
19301 HWRM_PORT_PHY_QCAPS_OUTPUT_PORT_CNT_4
19303 * This is a bit mask to indicate what speeds are supported
19304 * as forced speeds on this link.
19305 * For each speed that can be forced on this link, the
19306 * corresponding mask bit shall be set to '1'.
19308 uint16_t supported_speeds_force_mode;
19309 /* 100Mb link speed (Half-duplex) */
19310 #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_FORCE_MODE_100MBHD \
19312 /* 100Mb link speed (Full-duplex) */
19313 #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_FORCE_MODE_100MB \
19315 /* 1Gb link speed (Half-duplex) */
19316 #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_FORCE_MODE_1GBHD \
19318 /* 1Gb link speed (Full-duplex) */
19319 #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_FORCE_MODE_1GB \
19321 /* 2Gb link speed */
19322 #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_FORCE_MODE_2GB \
19324 /* 25Gb link speed */
19325 #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_FORCE_MODE_2_5GB \
19327 /* 10Gb link speed */
19328 #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_FORCE_MODE_10GB \
19330 /* 20Gb link speed */
19331 #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_FORCE_MODE_20GB \
19333 /* 25Gb link speed */
19334 #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_FORCE_MODE_25GB \
19336 /* 40Gb link speed */
19337 #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_FORCE_MODE_40GB \
19339 /* 50Gb link speed */
19340 #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_FORCE_MODE_50GB \
19342 /* 100Gb link speed */
19343 #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_FORCE_MODE_100GB \
19345 /* 10Mb link speed (Half-duplex) */
19346 #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_FORCE_MODE_10MBHD \
19348 /* 10Mb link speed (Full-duplex) */
19349 #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_FORCE_MODE_10MB \
19351 /* 200Gb link speed */
19352 #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_FORCE_MODE_200GB \
19355 * This is a bit mask to indicate what speeds are supported
19356 * for autonegotiation on this link.
19357 * For each speed that can be autonegotiated on this link, the
19358 * corresponding mask bit shall be set to '1'.
19360 uint16_t supported_speeds_auto_mode;
19361 /* 100Mb link speed (Half-duplex) */
19362 #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_AUTO_MODE_100MBHD \
19364 /* 100Mb link speed (Full-duplex) */
19365 #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_AUTO_MODE_100MB \
19367 /* 1Gb link speed (Half-duplex) */
19368 #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_AUTO_MODE_1GBHD \
19370 /* 1Gb link speed (Full-duplex) */
19371 #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_AUTO_MODE_1GB \
19373 /* 2Gb link speed */
19374 #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_AUTO_MODE_2GB \
19376 /* 25Gb link speed */
19377 #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_AUTO_MODE_2_5GB \
19379 /* 10Gb link speed */
19380 #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_AUTO_MODE_10GB \
19382 /* 20Gb link speed */
19383 #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_AUTO_MODE_20GB \
19385 /* 25Gb link speed */
19386 #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_AUTO_MODE_25GB \
19388 /* 40Gb link speed */
19389 #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_AUTO_MODE_40GB \
19391 /* 50Gb link speed */
19392 #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_AUTO_MODE_50GB \
19394 /* 100Gb link speed */
19395 #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_AUTO_MODE_100GB \
19397 /* 10Mb link speed (Half-duplex) */
19398 #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_AUTO_MODE_10MBHD \
19400 /* 10Mb link speed (Full-duplex) */
19401 #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_AUTO_MODE_10MB \
19403 /* 200Gb link speed */
19404 #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_AUTO_MODE_200GB \
19407 * This is a bit mask to indicate what speeds are supported
19408 * for EEE on this link.
19409 * For each speed that can be autonegotiated when EEE is enabled
19410 * on this link, the corresponding mask bit shall be set to '1'.
19411 * This field is only valid when the eee_suppotred is set to '1'.
19413 uint16_t supported_speeds_eee_mode;
19415 #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_EEE_MODE_RSVD1 \
19417 /* 100Mb link speed (Full-duplex) */
19418 #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_EEE_MODE_100MB \
19421 #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_EEE_MODE_RSVD2 \
19423 /* 1Gb link speed (Full-duplex) */
19424 #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_EEE_MODE_1GB \
19427 #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_EEE_MODE_RSVD3 \
19430 #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_EEE_MODE_RSVD4 \
19432 /* 10Gb link speed */
19433 #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_EEE_MODE_10GB \
19435 uint32_t tx_lpi_timer_low;
19437 * The lowest value of TX LPI timer that can be set on this link
19438 * when EEE is enabled. This value is in microseconds.
19439 * This field is valid only when_eee_supported is set to '1'.
19441 #define HWRM_PORT_PHY_QCAPS_OUTPUT_TX_LPI_TIMER_LOW_MASK \
19443 #define HWRM_PORT_PHY_QCAPS_OUTPUT_TX_LPI_TIMER_LOW_SFT 0
19445 * Reserved field. The HWRM shall set this field to 0.
19446 * An HWRM client shall ignore this field.
19448 #define HWRM_PORT_PHY_QCAPS_OUTPUT_RSVD2_MASK \
19449 UINT32_C(0xff000000)
19450 #define HWRM_PORT_PHY_QCAPS_OUTPUT_RSVD2_SFT 24
19451 uint32_t valid_tx_lpi_timer_high;
19453 * The highest value of TX LPI timer that can be set on this link
19454 * when EEE is enabled. This value is in microseconds.
19455 * This field is valid only when_eee_supported is set to '1'.
19457 #define HWRM_PORT_PHY_QCAPS_OUTPUT_TX_LPI_TIMER_HIGH_MASK \
19459 #define HWRM_PORT_PHY_QCAPS_OUTPUT_TX_LPI_TIMER_HIGH_SFT 0
19461 * This field is used in Output records to indicate that the output
19462 * is completely written to RAM. This field should be read as '1'
19463 * to indicate that the output has been completely written.
19464 * When writing a command completion or response to an internal processor,
19465 * the order of writes has to be such that this field is written last.
19467 #define HWRM_PORT_PHY_QCAPS_OUTPUT_VALID_MASK \
19468 UINT32_C(0xff000000)
19469 #define HWRM_PORT_PHY_QCAPS_OUTPUT_VALID_SFT 24
19472 /****************************
19473 * hwrm_port_phy_mdio_write *
19474 ****************************/
19477 /* hwrm_port_phy_mdio_write_input (size:320b/40B) */
19478 struct hwrm_port_phy_mdio_write_input {
19479 /* The HWRM command request type. */
19482 * The completion ring to send the completion event on. This should
19483 * be the NQ ID returned from the `nq_alloc` HWRM command.
19485 uint16_t cmpl_ring;
19487 * The sequence ID is used by the driver for tracking multiple
19488 * commands. This ID is treated as opaque data by the firmware and
19489 * the value is returned in the `hwrm_resp_hdr` upon completion.
19493 * The target ID of the command:
19494 * * 0x0-0xFFF8 - The function ID
19495 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
19496 * * 0xFFFD - Reserved for user-space HWRM interface
19499 uint16_t target_id;
19501 * A physical address pointer pointing to a host buffer that the
19502 * command's response data will be written. This can be either a host
19503 * physical address (HPA) or a guest physical address (GPA) and must
19504 * point to a physically contiguous block of memory.
19506 uint64_t resp_addr;
19507 /* Reserved for future use. */
19508 uint32_t unused_0[2];
19509 /* Port ID of port. */
19511 /* If phy_address is 0xFF, port_id will be used to derive phy_addr. */
19513 /* 8-bit device address. */
19515 /* 16-bit register address. */
19517 /* 16-bit register data. */
19520 * When this bit is set to 1 a Clause 45 mdio access is done.
19521 * when this bit is set to 0 a Clause 22 mdio access is done.
19525 uint8_t unused_1[7];
19528 /* hwrm_port_phy_mdio_write_output (size:128b/16B) */
19529 struct hwrm_port_phy_mdio_write_output {
19530 /* The specific error status for the command. */
19531 uint16_t error_code;
19532 /* The HWRM command request type. */
19534 /* The sequence ID from the original command. */
19536 /* The length of the response data in number of bytes. */
19538 uint8_t unused_0[7];
19540 * This field is used in Output records to indicate that the output
19541 * is completely written to RAM. This field should be read as '1'
19542 * to indicate that the output has been completely written.
19543 * When writing a command completion or response to an internal processor,
19544 * the order of writes has to be such that this field is written last.
19549 /***************************
19550 * hwrm_port_phy_mdio_read *
19551 ***************************/
19554 /* hwrm_port_phy_mdio_read_input (size:256b/32B) */
19555 struct hwrm_port_phy_mdio_read_input {
19556 /* The HWRM command request type. */
19559 * The completion ring to send the completion event on. This should
19560 * be the NQ ID returned from the `nq_alloc` HWRM command.
19562 uint16_t cmpl_ring;
19564 * The sequence ID is used by the driver for tracking multiple
19565 * commands. This ID is treated as opaque data by the firmware and
19566 * the value is returned in the `hwrm_resp_hdr` upon completion.
19570 * The target ID of the command:
19571 * * 0x0-0xFFF8 - The function ID
19572 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
19573 * * 0xFFFD - Reserved for user-space HWRM interface
19576 uint16_t target_id;
19578 * A physical address pointer pointing to a host buffer that the
19579 * command's response data will be written. This can be either a host
19580 * physical address (HPA) or a guest physical address (GPA) and must
19581 * point to a physically contiguous block of memory.
19583 uint64_t resp_addr;
19584 /* Reserved for future use. */
19585 uint32_t unused_0[2];
19586 /* Port ID of port. */
19588 /* If phy_address is 0xFF, port_id will be used to derive phy_addr. */
19590 /* 8-bit device address. */
19592 /* 16-bit register address. */
19595 * When this bit is set to 1 a Clause 45 mdio access is done.
19596 * when this bit is set to 0 a Clause 22 mdio access is done.
19603 /* hwrm_port_phy_mdio_read_output (size:128b/16B) */
19604 struct hwrm_port_phy_mdio_read_output {
19605 /* The specific error status for the command. */
19606 uint16_t error_code;
19607 /* The HWRM command request type. */
19609 /* The sequence ID from the original command. */
19611 /* The length of the response data in number of bytes. */
19613 /* 16-bit register data. */
19615 uint8_t unused_0[5];
19617 * This field is used in Output records to indicate that the output
19618 * is completely written to RAM. This field should be read as '1'
19619 * to indicate that the output has been completely written.
19620 * When writing a command completion or response to an internal processor,
19621 * the order of writes has to be such that this field is written last.
19626 /*********************
19627 * hwrm_port_led_cfg *
19628 *********************/
19631 /* hwrm_port_led_cfg_input (size:512b/64B) */
19632 struct hwrm_port_led_cfg_input {
19633 /* The HWRM command request type. */
19636 * The completion ring to send the completion event on. This should
19637 * be the NQ ID returned from the `nq_alloc` HWRM command.
19639 uint16_t cmpl_ring;
19641 * The sequence ID is used by the driver for tracking multiple
19642 * commands. This ID is treated as opaque data by the firmware and
19643 * the value is returned in the `hwrm_resp_hdr` upon completion.
19647 * The target ID of the command:
19648 * * 0x0-0xFFF8 - The function ID
19649 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
19650 * * 0xFFFD - Reserved for user-space HWRM interface
19653 uint16_t target_id;
19655 * A physical address pointer pointing to a host buffer that the
19656 * command's response data will be written. This can be either a host
19657 * physical address (HPA) or a guest physical address (GPA) and must
19658 * point to a physically contiguous block of memory.
19660 uint64_t resp_addr;
19663 * This bit must be '1' for the led0_id field to be
19666 #define HWRM_PORT_LED_CFG_INPUT_ENABLES_LED0_ID \
19669 * This bit must be '1' for the led0_state field to be
19672 #define HWRM_PORT_LED_CFG_INPUT_ENABLES_LED0_STATE \
19675 * This bit must be '1' for the led0_color field to be
19678 #define HWRM_PORT_LED_CFG_INPUT_ENABLES_LED0_COLOR \
19681 * This bit must be '1' for the led0_blink_on field to be
19684 #define HWRM_PORT_LED_CFG_INPUT_ENABLES_LED0_BLINK_ON \
19687 * This bit must be '1' for the led0_blink_off field to be
19690 #define HWRM_PORT_LED_CFG_INPUT_ENABLES_LED0_BLINK_OFF \
19693 * This bit must be '1' for the led0_group_id field to be
19696 #define HWRM_PORT_LED_CFG_INPUT_ENABLES_LED0_GROUP_ID \
19699 * This bit must be '1' for the led1_id field to be
19702 #define HWRM_PORT_LED_CFG_INPUT_ENABLES_LED1_ID \
19705 * This bit must be '1' for the led1_state field to be
19708 #define HWRM_PORT_LED_CFG_INPUT_ENABLES_LED1_STATE \
19711 * This bit must be '1' for the led1_color field to be
19714 #define HWRM_PORT_LED_CFG_INPUT_ENABLES_LED1_COLOR \
19717 * This bit must be '1' for the led1_blink_on field to be
19720 #define HWRM_PORT_LED_CFG_INPUT_ENABLES_LED1_BLINK_ON \
19723 * This bit must be '1' for the led1_blink_off field to be
19726 #define HWRM_PORT_LED_CFG_INPUT_ENABLES_LED1_BLINK_OFF \
19729 * This bit must be '1' for the led1_group_id field to be
19732 #define HWRM_PORT_LED_CFG_INPUT_ENABLES_LED1_GROUP_ID \
19735 * This bit must be '1' for the led2_id field to be
19738 #define HWRM_PORT_LED_CFG_INPUT_ENABLES_LED2_ID \
19741 * This bit must be '1' for the led2_state field to be
19744 #define HWRM_PORT_LED_CFG_INPUT_ENABLES_LED2_STATE \
19747 * This bit must be '1' for the led2_color field to be
19750 #define HWRM_PORT_LED_CFG_INPUT_ENABLES_LED2_COLOR \
19753 * This bit must be '1' for the led2_blink_on field to be
19756 #define HWRM_PORT_LED_CFG_INPUT_ENABLES_LED2_BLINK_ON \
19759 * This bit must be '1' for the led2_blink_off field to be
19762 #define HWRM_PORT_LED_CFG_INPUT_ENABLES_LED2_BLINK_OFF \
19765 * This bit must be '1' for the led2_group_id field to be
19768 #define HWRM_PORT_LED_CFG_INPUT_ENABLES_LED2_GROUP_ID \
19771 * This bit must be '1' for the led3_id field to be
19774 #define HWRM_PORT_LED_CFG_INPUT_ENABLES_LED3_ID \
19777 * This bit must be '1' for the led3_state field to be
19780 #define HWRM_PORT_LED_CFG_INPUT_ENABLES_LED3_STATE \
19783 * This bit must be '1' for the led3_color field to be
19786 #define HWRM_PORT_LED_CFG_INPUT_ENABLES_LED3_COLOR \
19789 * This bit must be '1' for the led3_blink_on field to be
19792 #define HWRM_PORT_LED_CFG_INPUT_ENABLES_LED3_BLINK_ON \
19795 * This bit must be '1' for the led3_blink_off field to be
19798 #define HWRM_PORT_LED_CFG_INPUT_ENABLES_LED3_BLINK_OFF \
19801 * This bit must be '1' for the led3_group_id field to be
19804 #define HWRM_PORT_LED_CFG_INPUT_ENABLES_LED3_GROUP_ID \
19806 /* Port ID of port whose LEDs are configured. */
19809 * The number of LEDs that are being configured.
19810 * Up to 4 LEDs can be configured with this command.
19813 /* Reserved field. */
19815 /* An identifier for the LED #0. */
19817 /* The requested state of the LED #0. */
19818 uint8_t led0_state;
19819 /* Default state of the LED */
19820 #define HWRM_PORT_LED_CFG_INPUT_LED0_STATE_DEFAULT UINT32_C(0x0)
19822 #define HWRM_PORT_LED_CFG_INPUT_LED0_STATE_OFF UINT32_C(0x1)
19824 #define HWRM_PORT_LED_CFG_INPUT_LED0_STATE_ON UINT32_C(0x2)
19826 #define HWRM_PORT_LED_CFG_INPUT_LED0_STATE_BLINK UINT32_C(0x3)
19827 /* Blink Alternately */
19828 #define HWRM_PORT_LED_CFG_INPUT_LED0_STATE_BLINKALT UINT32_C(0x4)
19829 #define HWRM_PORT_LED_CFG_INPUT_LED0_STATE_LAST \
19830 HWRM_PORT_LED_CFG_INPUT_LED0_STATE_BLINKALT
19831 /* The requested color of LED #0. */
19832 uint8_t led0_color;
19834 #define HWRM_PORT_LED_CFG_INPUT_LED0_COLOR_DEFAULT UINT32_C(0x0)
19836 #define HWRM_PORT_LED_CFG_INPUT_LED0_COLOR_AMBER UINT32_C(0x1)
19838 #define HWRM_PORT_LED_CFG_INPUT_LED0_COLOR_GREEN UINT32_C(0x2)
19839 /* Green or Amber */
19840 #define HWRM_PORT_LED_CFG_INPUT_LED0_COLOR_GREENAMBER UINT32_C(0x3)
19841 #define HWRM_PORT_LED_CFG_INPUT_LED0_COLOR_LAST \
19842 HWRM_PORT_LED_CFG_INPUT_LED0_COLOR_GREENAMBER
19845 * If the LED #0 state is "blink" or "blinkalt", then
19846 * this field represents the requested time in milliseconds
19847 * to keep LED on between cycles.
19849 uint16_t led0_blink_on;
19851 * If the LED #0 state is "blink" or "blinkalt", then
19852 * this field represents the requested time in milliseconds
19853 * to keep LED off between cycles.
19855 uint16_t led0_blink_off;
19857 * An identifier for the group of LEDs that LED #0 belongs
19859 * If set to 0, then the LED #0 shall not be grouped and
19860 * shall be treated as an individual resource.
19861 * For all other non-zero values of this field, LED #0 shall
19862 * be grouped together with the LEDs with the same group ID
19865 uint8_t led0_group_id;
19866 /* Reserved field. */
19868 /* An identifier for the LED #1. */
19870 /* The requested state of the LED #1. */
19871 uint8_t led1_state;
19872 /* Default state of the LED */
19873 #define HWRM_PORT_LED_CFG_INPUT_LED1_STATE_DEFAULT UINT32_C(0x0)
19875 #define HWRM_PORT_LED_CFG_INPUT_LED1_STATE_OFF UINT32_C(0x1)
19877 #define HWRM_PORT_LED_CFG_INPUT_LED1_STATE_ON UINT32_C(0x2)
19879 #define HWRM_PORT_LED_CFG_INPUT_LED1_STATE_BLINK UINT32_C(0x3)
19880 /* Blink Alternately */
19881 #define HWRM_PORT_LED_CFG_INPUT_LED1_STATE_BLINKALT UINT32_C(0x4)
19882 #define HWRM_PORT_LED_CFG_INPUT_LED1_STATE_LAST \
19883 HWRM_PORT_LED_CFG_INPUT_LED1_STATE_BLINKALT
19884 /* The requested color of LED #1. */
19885 uint8_t led1_color;
19887 #define HWRM_PORT_LED_CFG_INPUT_LED1_COLOR_DEFAULT UINT32_C(0x0)
19889 #define HWRM_PORT_LED_CFG_INPUT_LED1_COLOR_AMBER UINT32_C(0x1)
19891 #define HWRM_PORT_LED_CFG_INPUT_LED1_COLOR_GREEN UINT32_C(0x2)
19892 /* Green or Amber */
19893 #define HWRM_PORT_LED_CFG_INPUT_LED1_COLOR_GREENAMBER UINT32_C(0x3)
19894 #define HWRM_PORT_LED_CFG_INPUT_LED1_COLOR_LAST \
19895 HWRM_PORT_LED_CFG_INPUT_LED1_COLOR_GREENAMBER
19898 * If the LED #1 state is "blink" or "blinkalt", then
19899 * this field represents the requested time in milliseconds
19900 * to keep LED on between cycles.
19902 uint16_t led1_blink_on;
19904 * If the LED #1 state is "blink" or "blinkalt", then
19905 * this field represents the requested time in milliseconds
19906 * to keep LED off between cycles.
19908 uint16_t led1_blink_off;
19910 * An identifier for the group of LEDs that LED #1 belongs
19912 * If set to 0, then the LED #1 shall not be grouped and
19913 * shall be treated as an individual resource.
19914 * For all other non-zero values of this field, LED #1 shall
19915 * be grouped together with the LEDs with the same group ID
19918 uint8_t led1_group_id;
19919 /* Reserved field. */
19921 /* An identifier for the LED #2. */
19923 /* The requested state of the LED #2. */
19924 uint8_t led2_state;
19925 /* Default state of the LED */
19926 #define HWRM_PORT_LED_CFG_INPUT_LED2_STATE_DEFAULT UINT32_C(0x0)
19928 #define HWRM_PORT_LED_CFG_INPUT_LED2_STATE_OFF UINT32_C(0x1)
19930 #define HWRM_PORT_LED_CFG_INPUT_LED2_STATE_ON UINT32_C(0x2)
19932 #define HWRM_PORT_LED_CFG_INPUT_LED2_STATE_BLINK UINT32_C(0x3)
19933 /* Blink Alternately */
19934 #define HWRM_PORT_LED_CFG_INPUT_LED2_STATE_BLINKALT UINT32_C(0x4)
19935 #define HWRM_PORT_LED_CFG_INPUT_LED2_STATE_LAST \
19936 HWRM_PORT_LED_CFG_INPUT_LED2_STATE_BLINKALT
19937 /* The requested color of LED #2. */
19938 uint8_t led2_color;
19940 #define HWRM_PORT_LED_CFG_INPUT_LED2_COLOR_DEFAULT UINT32_C(0x0)
19942 #define HWRM_PORT_LED_CFG_INPUT_LED2_COLOR_AMBER UINT32_C(0x1)
19944 #define HWRM_PORT_LED_CFG_INPUT_LED2_COLOR_GREEN UINT32_C(0x2)
19945 /* Green or Amber */
19946 #define HWRM_PORT_LED_CFG_INPUT_LED2_COLOR_GREENAMBER UINT32_C(0x3)
19947 #define HWRM_PORT_LED_CFG_INPUT_LED2_COLOR_LAST \
19948 HWRM_PORT_LED_CFG_INPUT_LED2_COLOR_GREENAMBER
19951 * If the LED #2 state is "blink" or "blinkalt", then
19952 * this field represents the requested time in milliseconds
19953 * to keep LED on between cycles.
19955 uint16_t led2_blink_on;
19957 * If the LED #2 state is "blink" or "blinkalt", then
19958 * this field represents the requested time in milliseconds
19959 * to keep LED off between cycles.
19961 uint16_t led2_blink_off;
19963 * An identifier for the group of LEDs that LED #2 belongs
19965 * If set to 0, then the LED #2 shall not be grouped and
19966 * shall be treated as an individual resource.
19967 * For all other non-zero values of this field, LED #2 shall
19968 * be grouped together with the LEDs with the same group ID
19971 uint8_t led2_group_id;
19972 /* Reserved field. */
19974 /* An identifier for the LED #3. */
19976 /* The requested state of the LED #3. */
19977 uint8_t led3_state;
19978 /* Default state of the LED */
19979 #define HWRM_PORT_LED_CFG_INPUT_LED3_STATE_DEFAULT UINT32_C(0x0)
19981 #define HWRM_PORT_LED_CFG_INPUT_LED3_STATE_OFF UINT32_C(0x1)
19983 #define HWRM_PORT_LED_CFG_INPUT_LED3_STATE_ON UINT32_C(0x2)
19985 #define HWRM_PORT_LED_CFG_INPUT_LED3_STATE_BLINK UINT32_C(0x3)
19986 /* Blink Alternately */
19987 #define HWRM_PORT_LED_CFG_INPUT_LED3_STATE_BLINKALT UINT32_C(0x4)
19988 #define HWRM_PORT_LED_CFG_INPUT_LED3_STATE_LAST \
19989 HWRM_PORT_LED_CFG_INPUT_LED3_STATE_BLINKALT
19990 /* The requested color of LED #3. */
19991 uint8_t led3_color;
19993 #define HWRM_PORT_LED_CFG_INPUT_LED3_COLOR_DEFAULT UINT32_C(0x0)
19995 #define HWRM_PORT_LED_CFG_INPUT_LED3_COLOR_AMBER UINT32_C(0x1)
19997 #define HWRM_PORT_LED_CFG_INPUT_LED3_COLOR_GREEN UINT32_C(0x2)
19998 /* Green or Amber */
19999 #define HWRM_PORT_LED_CFG_INPUT_LED3_COLOR_GREENAMBER UINT32_C(0x3)
20000 #define HWRM_PORT_LED_CFG_INPUT_LED3_COLOR_LAST \
20001 HWRM_PORT_LED_CFG_INPUT_LED3_COLOR_GREENAMBER
20004 * If the LED #3 state is "blink" or "blinkalt", then
20005 * this field represents the requested time in milliseconds
20006 * to keep LED on between cycles.
20008 uint16_t led3_blink_on;
20010 * If the LED #3 state is "blink" or "blinkalt", then
20011 * this field represents the requested time in milliseconds
20012 * to keep LED off between cycles.
20014 uint16_t led3_blink_off;
20016 * An identifier for the group of LEDs that LED #3 belongs
20018 * If set to 0, then the LED #3 shall not be grouped and
20019 * shall be treated as an individual resource.
20020 * For all other non-zero values of this field, LED #3 shall
20021 * be grouped together with the LEDs with the same group ID
20024 uint8_t led3_group_id;
20025 /* Reserved field. */
20029 /* hwrm_port_led_cfg_output (size:128b/16B) */
20030 struct hwrm_port_led_cfg_output {
20031 /* The specific error status for the command. */
20032 uint16_t error_code;
20033 /* The HWRM command request type. */
20035 /* The sequence ID from the original command. */
20037 /* The length of the response data in number of bytes. */
20039 uint8_t unused_0[7];
20041 * This field is used in Output records to indicate that the output
20042 * is completely written to RAM. This field should be read as '1'
20043 * to indicate that the output has been completely written.
20044 * When writing a command completion or response to an internal processor,
20045 * the order of writes has to be such that this field is written last.
20050 /**********************
20051 * hwrm_port_led_qcfg *
20052 **********************/
20055 /* hwrm_port_led_qcfg_input (size:192b/24B) */
20056 struct hwrm_port_led_qcfg_input {
20057 /* The HWRM command request type. */
20060 * The completion ring to send the completion event on. This should
20061 * be the NQ ID returned from the `nq_alloc` HWRM command.
20063 uint16_t cmpl_ring;
20065 * The sequence ID is used by the driver for tracking multiple
20066 * commands. This ID is treated as opaque data by the firmware and
20067 * the value is returned in the `hwrm_resp_hdr` upon completion.
20071 * The target ID of the command:
20072 * * 0x0-0xFFF8 - The function ID
20073 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
20074 * * 0xFFFD - Reserved for user-space HWRM interface
20077 uint16_t target_id;
20079 * A physical address pointer pointing to a host buffer that the
20080 * command's response data will be written. This can be either a host
20081 * physical address (HPA) or a guest physical address (GPA) and must
20082 * point to a physically contiguous block of memory.
20084 uint64_t resp_addr;
20085 /* Port ID of port whose LED configuration is being queried. */
20087 uint8_t unused_0[6];
20090 /* hwrm_port_led_qcfg_output (size:448b/56B) */
20091 struct hwrm_port_led_qcfg_output {
20092 /* The specific error status for the command. */
20093 uint16_t error_code;
20094 /* The HWRM command request type. */
20096 /* The sequence ID from the original command. */
20098 /* The length of the response data in number of bytes. */
20101 * The number of LEDs that are configured on this port.
20102 * Up to 4 LEDs can be returned in the response.
20105 /* An identifier for the LED #0. */
20107 /* The type of LED #0. */
20110 #define HWRM_PORT_LED_QCFG_OUTPUT_LED0_TYPE_SPEED UINT32_C(0x0)
20112 #define HWRM_PORT_LED_QCFG_OUTPUT_LED0_TYPE_ACTIVITY UINT32_C(0x1)
20114 #define HWRM_PORT_LED_QCFG_OUTPUT_LED0_TYPE_INVALID UINT32_C(0xff)
20115 #define HWRM_PORT_LED_QCFG_OUTPUT_LED0_TYPE_LAST \
20116 HWRM_PORT_LED_QCFG_OUTPUT_LED0_TYPE_INVALID
20117 /* The current state of the LED #0. */
20118 uint8_t led0_state;
20119 /* Default state of the LED */
20120 #define HWRM_PORT_LED_QCFG_OUTPUT_LED0_STATE_DEFAULT UINT32_C(0x0)
20122 #define HWRM_PORT_LED_QCFG_OUTPUT_LED0_STATE_OFF UINT32_C(0x1)
20124 #define HWRM_PORT_LED_QCFG_OUTPUT_LED0_STATE_ON UINT32_C(0x2)
20126 #define HWRM_PORT_LED_QCFG_OUTPUT_LED0_STATE_BLINK UINT32_C(0x3)
20127 /* Blink Alternately */
20128 #define HWRM_PORT_LED_QCFG_OUTPUT_LED0_STATE_BLINKALT UINT32_C(0x4)
20129 #define HWRM_PORT_LED_QCFG_OUTPUT_LED0_STATE_LAST \
20130 HWRM_PORT_LED_QCFG_OUTPUT_LED0_STATE_BLINKALT
20131 /* The color of LED #0. */
20132 uint8_t led0_color;
20134 #define HWRM_PORT_LED_QCFG_OUTPUT_LED0_COLOR_DEFAULT UINT32_C(0x0)
20136 #define HWRM_PORT_LED_QCFG_OUTPUT_LED0_COLOR_AMBER UINT32_C(0x1)
20138 #define HWRM_PORT_LED_QCFG_OUTPUT_LED0_COLOR_GREEN UINT32_C(0x2)
20139 /* Green or Amber */
20140 #define HWRM_PORT_LED_QCFG_OUTPUT_LED0_COLOR_GREENAMBER UINT32_C(0x3)
20141 #define HWRM_PORT_LED_QCFG_OUTPUT_LED0_COLOR_LAST \
20142 HWRM_PORT_LED_QCFG_OUTPUT_LED0_COLOR_GREENAMBER
20145 * If the LED #0 state is "blink" or "blinkalt", then
20146 * this field represents the requested time in milliseconds
20147 * to keep LED on between cycles.
20149 uint16_t led0_blink_on;
20151 * If the LED #0 state is "blink" or "blinkalt", then
20152 * this field represents the requested time in milliseconds
20153 * to keep LED off between cycles.
20155 uint16_t led0_blink_off;
20157 * An identifier for the group of LEDs that LED #0 belongs
20159 * If set to 0, then the LED #0 is not grouped.
20160 * For all other non-zero values of this field, LED #0 is
20161 * grouped together with the LEDs with the same group ID
20164 uint8_t led0_group_id;
20165 /* An identifier for the LED #1. */
20167 /* The type of LED #1. */
20170 #define HWRM_PORT_LED_QCFG_OUTPUT_LED1_TYPE_SPEED UINT32_C(0x0)
20172 #define HWRM_PORT_LED_QCFG_OUTPUT_LED1_TYPE_ACTIVITY UINT32_C(0x1)
20174 #define HWRM_PORT_LED_QCFG_OUTPUT_LED1_TYPE_INVALID UINT32_C(0xff)
20175 #define HWRM_PORT_LED_QCFG_OUTPUT_LED1_TYPE_LAST \
20176 HWRM_PORT_LED_QCFG_OUTPUT_LED1_TYPE_INVALID
20177 /* The current state of the LED #1. */
20178 uint8_t led1_state;
20179 /* Default state of the LED */
20180 #define HWRM_PORT_LED_QCFG_OUTPUT_LED1_STATE_DEFAULT UINT32_C(0x0)
20182 #define HWRM_PORT_LED_QCFG_OUTPUT_LED1_STATE_OFF UINT32_C(0x1)
20184 #define HWRM_PORT_LED_QCFG_OUTPUT_LED1_STATE_ON UINT32_C(0x2)
20186 #define HWRM_PORT_LED_QCFG_OUTPUT_LED1_STATE_BLINK UINT32_C(0x3)
20187 /* Blink Alternately */
20188 #define HWRM_PORT_LED_QCFG_OUTPUT_LED1_STATE_BLINKALT UINT32_C(0x4)
20189 #define HWRM_PORT_LED_QCFG_OUTPUT_LED1_STATE_LAST \
20190 HWRM_PORT_LED_QCFG_OUTPUT_LED1_STATE_BLINKALT
20191 /* The color of LED #1. */
20192 uint8_t led1_color;
20194 #define HWRM_PORT_LED_QCFG_OUTPUT_LED1_COLOR_DEFAULT UINT32_C(0x0)
20196 #define HWRM_PORT_LED_QCFG_OUTPUT_LED1_COLOR_AMBER UINT32_C(0x1)
20198 #define HWRM_PORT_LED_QCFG_OUTPUT_LED1_COLOR_GREEN UINT32_C(0x2)
20199 /* Green or Amber */
20200 #define HWRM_PORT_LED_QCFG_OUTPUT_LED1_COLOR_GREENAMBER UINT32_C(0x3)
20201 #define HWRM_PORT_LED_QCFG_OUTPUT_LED1_COLOR_LAST \
20202 HWRM_PORT_LED_QCFG_OUTPUT_LED1_COLOR_GREENAMBER
20205 * If the LED #1 state is "blink" or "blinkalt", then
20206 * this field represents the requested time in milliseconds
20207 * to keep LED on between cycles.
20209 uint16_t led1_blink_on;
20211 * If the LED #1 state is "blink" or "blinkalt", then
20212 * this field represents the requested time in milliseconds
20213 * to keep LED off between cycles.
20215 uint16_t led1_blink_off;
20217 * An identifier for the group of LEDs that LED #1 belongs
20219 * If set to 0, then the LED #1 is not grouped.
20220 * For all other non-zero values of this field, LED #1 is
20221 * grouped together with the LEDs with the same group ID
20224 uint8_t led1_group_id;
20225 /* An identifier for the LED #2. */
20227 /* The type of LED #2. */
20230 #define HWRM_PORT_LED_QCFG_OUTPUT_LED2_TYPE_SPEED UINT32_C(0x0)
20232 #define HWRM_PORT_LED_QCFG_OUTPUT_LED2_TYPE_ACTIVITY UINT32_C(0x1)
20234 #define HWRM_PORT_LED_QCFG_OUTPUT_LED2_TYPE_INVALID UINT32_C(0xff)
20235 #define HWRM_PORT_LED_QCFG_OUTPUT_LED2_TYPE_LAST \
20236 HWRM_PORT_LED_QCFG_OUTPUT_LED2_TYPE_INVALID
20237 /* The current state of the LED #2. */
20238 uint8_t led2_state;
20239 /* Default state of the LED */
20240 #define HWRM_PORT_LED_QCFG_OUTPUT_LED2_STATE_DEFAULT UINT32_C(0x0)
20242 #define HWRM_PORT_LED_QCFG_OUTPUT_LED2_STATE_OFF UINT32_C(0x1)
20244 #define HWRM_PORT_LED_QCFG_OUTPUT_LED2_STATE_ON UINT32_C(0x2)
20246 #define HWRM_PORT_LED_QCFG_OUTPUT_LED2_STATE_BLINK UINT32_C(0x3)
20247 /* Blink Alternately */
20248 #define HWRM_PORT_LED_QCFG_OUTPUT_LED2_STATE_BLINKALT UINT32_C(0x4)
20249 #define HWRM_PORT_LED_QCFG_OUTPUT_LED2_STATE_LAST \
20250 HWRM_PORT_LED_QCFG_OUTPUT_LED2_STATE_BLINKALT
20251 /* The color of LED #2. */
20252 uint8_t led2_color;
20254 #define HWRM_PORT_LED_QCFG_OUTPUT_LED2_COLOR_DEFAULT UINT32_C(0x0)
20256 #define HWRM_PORT_LED_QCFG_OUTPUT_LED2_COLOR_AMBER UINT32_C(0x1)
20258 #define HWRM_PORT_LED_QCFG_OUTPUT_LED2_COLOR_GREEN UINT32_C(0x2)
20259 /* Green or Amber */
20260 #define HWRM_PORT_LED_QCFG_OUTPUT_LED2_COLOR_GREENAMBER UINT32_C(0x3)
20261 #define HWRM_PORT_LED_QCFG_OUTPUT_LED2_COLOR_LAST \
20262 HWRM_PORT_LED_QCFG_OUTPUT_LED2_COLOR_GREENAMBER
20265 * If the LED #2 state is "blink" or "blinkalt", then
20266 * this field represents the requested time in milliseconds
20267 * to keep LED on between cycles.
20269 uint16_t led2_blink_on;
20271 * If the LED #2 state is "blink" or "blinkalt", then
20272 * this field represents the requested time in milliseconds
20273 * to keep LED off between cycles.
20275 uint16_t led2_blink_off;
20277 * An identifier for the group of LEDs that LED #2 belongs
20279 * If set to 0, then the LED #2 is not grouped.
20280 * For all other non-zero values of this field, LED #2 is
20281 * grouped together with the LEDs with the same group ID
20284 uint8_t led2_group_id;
20285 /* An identifier for the LED #3. */
20287 /* The type of LED #3. */
20290 #define HWRM_PORT_LED_QCFG_OUTPUT_LED3_TYPE_SPEED UINT32_C(0x0)
20292 #define HWRM_PORT_LED_QCFG_OUTPUT_LED3_TYPE_ACTIVITY UINT32_C(0x1)
20294 #define HWRM_PORT_LED_QCFG_OUTPUT_LED3_TYPE_INVALID UINT32_C(0xff)
20295 #define HWRM_PORT_LED_QCFG_OUTPUT_LED3_TYPE_LAST \
20296 HWRM_PORT_LED_QCFG_OUTPUT_LED3_TYPE_INVALID
20297 /* The current state of the LED #3. */
20298 uint8_t led3_state;
20299 /* Default state of the LED */
20300 #define HWRM_PORT_LED_QCFG_OUTPUT_LED3_STATE_DEFAULT UINT32_C(0x0)
20302 #define HWRM_PORT_LED_QCFG_OUTPUT_LED3_STATE_OFF UINT32_C(0x1)
20304 #define HWRM_PORT_LED_QCFG_OUTPUT_LED3_STATE_ON UINT32_C(0x2)
20306 #define HWRM_PORT_LED_QCFG_OUTPUT_LED3_STATE_BLINK UINT32_C(0x3)
20307 /* Blink Alternately */
20308 #define HWRM_PORT_LED_QCFG_OUTPUT_LED3_STATE_BLINKALT UINT32_C(0x4)
20309 #define HWRM_PORT_LED_QCFG_OUTPUT_LED3_STATE_LAST \
20310 HWRM_PORT_LED_QCFG_OUTPUT_LED3_STATE_BLINKALT
20311 /* The color of LED #3. */
20312 uint8_t led3_color;
20314 #define HWRM_PORT_LED_QCFG_OUTPUT_LED3_COLOR_DEFAULT UINT32_C(0x0)
20316 #define HWRM_PORT_LED_QCFG_OUTPUT_LED3_COLOR_AMBER UINT32_C(0x1)
20318 #define HWRM_PORT_LED_QCFG_OUTPUT_LED3_COLOR_GREEN UINT32_C(0x2)
20319 /* Green or Amber */
20320 #define HWRM_PORT_LED_QCFG_OUTPUT_LED3_COLOR_GREENAMBER UINT32_C(0x3)
20321 #define HWRM_PORT_LED_QCFG_OUTPUT_LED3_COLOR_LAST \
20322 HWRM_PORT_LED_QCFG_OUTPUT_LED3_COLOR_GREENAMBER
20325 * If the LED #3 state is "blink" or "blinkalt", then
20326 * this field represents the requested time in milliseconds
20327 * to keep LED on between cycles.
20329 uint16_t led3_blink_on;
20331 * If the LED #3 state is "blink" or "blinkalt", then
20332 * this field represents the requested time in milliseconds
20333 * to keep LED off between cycles.
20335 uint16_t led3_blink_off;
20337 * An identifier for the group of LEDs that LED #3 belongs
20339 * If set to 0, then the LED #3 is not grouped.
20340 * For all other non-zero values of this field, LED #3 is
20341 * grouped together with the LEDs with the same group ID
20344 uint8_t led3_group_id;
20345 uint8_t unused_4[6];
20347 * This field is used in Output records to indicate that the output
20348 * is completely written to RAM. This field should be read as '1'
20349 * to indicate that the output has been completely written.
20350 * When writing a command completion or response to an internal processor,
20351 * the order of writes has to be such that this field is written last.
20356 /***********************
20357 * hwrm_port_led_qcaps *
20358 ***********************/
20361 /* hwrm_port_led_qcaps_input (size:192b/24B) */
20362 struct hwrm_port_led_qcaps_input {
20363 /* The HWRM command request type. */
20366 * The completion ring to send the completion event on. This should
20367 * be the NQ ID returned from the `nq_alloc` HWRM command.
20369 uint16_t cmpl_ring;
20371 * The sequence ID is used by the driver for tracking multiple
20372 * commands. This ID is treated as opaque data by the firmware and
20373 * the value is returned in the `hwrm_resp_hdr` upon completion.
20377 * The target ID of the command:
20378 * * 0x0-0xFFF8 - The function ID
20379 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
20380 * * 0xFFFD - Reserved for user-space HWRM interface
20383 uint16_t target_id;
20385 * A physical address pointer pointing to a host buffer that the
20386 * command's response data will be written. This can be either a host
20387 * physical address (HPA) or a guest physical address (GPA) and must
20388 * point to a physically contiguous block of memory.
20390 uint64_t resp_addr;
20391 /* Port ID of port whose LED configuration is being queried. */
20393 uint8_t unused_0[6];
20396 /* hwrm_port_led_qcaps_output (size:384b/48B) */
20397 struct hwrm_port_led_qcaps_output {
20398 /* The specific error status for the command. */
20399 uint16_t error_code;
20400 /* The HWRM command request type. */
20402 /* The sequence ID from the original command. */
20404 /* The length of the response data in number of bytes. */
20407 * The number of LEDs that are configured on this port.
20408 * Up to 4 LEDs can be returned in the response.
20411 /* Reserved for future use. */
20413 /* An identifier for the LED #0. */
20415 /* The type of LED #0. */
20418 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED0_TYPE_SPEED UINT32_C(0x0)
20420 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED0_TYPE_ACTIVITY UINT32_C(0x1)
20422 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED0_TYPE_INVALID UINT32_C(0xff)
20423 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED0_TYPE_LAST \
20424 HWRM_PORT_LED_QCAPS_OUTPUT_LED0_TYPE_INVALID
20426 * An identifier for the group of LEDs that LED #0 belongs
20428 * If set to 0, then the LED #0 cannot be grouped.
20429 * For all other non-zero values of this field, LED #0 is
20430 * grouped together with the LEDs with the same group ID
20433 uint8_t led0_group_id;
20435 /* The states supported by LED #0. */
20436 uint16_t led0_state_caps;
20438 * If set to 1, this LED is enabled.
20439 * If set to 0, this LED is disabled.
20441 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED0_STATE_CAPS_ENABLED \
20444 * If set to 1, off state is supported on this LED.
20445 * If set to 0, off state is not supported on this LED.
20447 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED0_STATE_CAPS_OFF_SUPPORTED \
20450 * If set to 1, on state is supported on this LED.
20451 * If set to 0, on state is not supported on this LED.
20453 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED0_STATE_CAPS_ON_SUPPORTED \
20456 * If set to 1, blink state is supported on this LED.
20457 * If set to 0, blink state is not supported on this LED.
20459 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED0_STATE_CAPS_BLINK_SUPPORTED \
20462 * If set to 1, blink_alt state is supported on this LED.
20463 * If set to 0, blink_alt state is not supported on this LED.
20465 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED0_STATE_CAPS_BLINK_ALT_SUPPORTED \
20467 /* The colors supported by LED #0. */
20468 uint16_t led0_color_caps;
20470 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED0_COLOR_CAPS_RSVD \
20473 * If set to 1, Amber color is supported on this LED.
20474 * If set to 0, Amber color is not supported on this LED.
20476 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED0_COLOR_CAPS_AMBER_SUPPORTED \
20479 * If set to 1, Green color is supported on this LED.
20480 * If set to 0, Green color is not supported on this LED.
20482 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED0_COLOR_CAPS_GREEN_SUPPORTED \
20484 /* An identifier for the LED #1. */
20486 /* The type of LED #1. */
20489 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED1_TYPE_SPEED UINT32_C(0x0)
20491 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED1_TYPE_ACTIVITY UINT32_C(0x1)
20493 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED1_TYPE_INVALID UINT32_C(0xff)
20494 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED1_TYPE_LAST \
20495 HWRM_PORT_LED_QCAPS_OUTPUT_LED1_TYPE_INVALID
20497 * An identifier for the group of LEDs that LED #1 belongs
20499 * If set to 0, then the LED #0 cannot be grouped.
20500 * For all other non-zero values of this field, LED #0 is
20501 * grouped together with the LEDs with the same group ID
20504 uint8_t led1_group_id;
20506 /* The states supported by LED #1. */
20507 uint16_t led1_state_caps;
20509 * If set to 1, this LED is enabled.
20510 * If set to 0, this LED is disabled.
20512 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED1_STATE_CAPS_ENABLED \
20515 * If set to 1, off state is supported on this LED.
20516 * If set to 0, off state is not supported on this LED.
20518 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED1_STATE_CAPS_OFF_SUPPORTED \
20521 * If set to 1, on state is supported on this LED.
20522 * If set to 0, on state is not supported on this LED.
20524 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED1_STATE_CAPS_ON_SUPPORTED \
20527 * If set to 1, blink state is supported on this LED.
20528 * If set to 0, blink state is not supported on this LED.
20530 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED1_STATE_CAPS_BLINK_SUPPORTED \
20533 * If set to 1, blink_alt state is supported on this LED.
20534 * If set to 0, blink_alt state is not supported on this LED.
20536 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED1_STATE_CAPS_BLINK_ALT_SUPPORTED \
20538 /* The colors supported by LED #1. */
20539 uint16_t led1_color_caps;
20541 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED1_COLOR_CAPS_RSVD \
20544 * If set to 1, Amber color is supported on this LED.
20545 * If set to 0, Amber color is not supported on this LED.
20547 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED1_COLOR_CAPS_AMBER_SUPPORTED \
20550 * If set to 1, Green color is supported on this LED.
20551 * If set to 0, Green color is not supported on this LED.
20553 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED1_COLOR_CAPS_GREEN_SUPPORTED \
20555 /* An identifier for the LED #2. */
20557 /* The type of LED #2. */
20560 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED2_TYPE_SPEED UINT32_C(0x0)
20562 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED2_TYPE_ACTIVITY UINT32_C(0x1)
20564 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED2_TYPE_INVALID UINT32_C(0xff)
20565 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED2_TYPE_LAST \
20566 HWRM_PORT_LED_QCAPS_OUTPUT_LED2_TYPE_INVALID
20568 * An identifier for the group of LEDs that LED #0 belongs
20570 * If set to 0, then the LED #0 cannot be grouped.
20571 * For all other non-zero values of this field, LED #0 is
20572 * grouped together with the LEDs with the same group ID
20575 uint8_t led2_group_id;
20577 /* The states supported by LED #2. */
20578 uint16_t led2_state_caps;
20580 * If set to 1, this LED is enabled.
20581 * If set to 0, this LED is disabled.
20583 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED2_STATE_CAPS_ENABLED \
20586 * If set to 1, off state is supported on this LED.
20587 * If set to 0, off state is not supported on this LED.
20589 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED2_STATE_CAPS_OFF_SUPPORTED \
20592 * If set to 1, on state is supported on this LED.
20593 * If set to 0, on state is not supported on this LED.
20595 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED2_STATE_CAPS_ON_SUPPORTED \
20598 * If set to 1, blink state is supported on this LED.
20599 * If set to 0, blink state is not supported on this LED.
20601 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED2_STATE_CAPS_BLINK_SUPPORTED \
20604 * If set to 1, blink_alt state is supported on this LED.
20605 * If set to 0, blink_alt state is not supported on this LED.
20607 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED2_STATE_CAPS_BLINK_ALT_SUPPORTED \
20609 /* The colors supported by LED #2. */
20610 uint16_t led2_color_caps;
20612 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED2_COLOR_CAPS_RSVD \
20615 * If set to 1, Amber color is supported on this LED.
20616 * If set to 0, Amber color is not supported on this LED.
20618 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED2_COLOR_CAPS_AMBER_SUPPORTED \
20621 * If set to 1, Green color is supported on this LED.
20622 * If set to 0, Green color is not supported on this LED.
20624 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED2_COLOR_CAPS_GREEN_SUPPORTED \
20626 /* An identifier for the LED #3. */
20628 /* The type of LED #3. */
20631 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED3_TYPE_SPEED UINT32_C(0x0)
20633 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED3_TYPE_ACTIVITY UINT32_C(0x1)
20635 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED3_TYPE_INVALID UINT32_C(0xff)
20636 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED3_TYPE_LAST \
20637 HWRM_PORT_LED_QCAPS_OUTPUT_LED3_TYPE_INVALID
20639 * An identifier for the group of LEDs that LED #3 belongs
20641 * If set to 0, then the LED #0 cannot be grouped.
20642 * For all other non-zero values of this field, LED #0 is
20643 * grouped together with the LEDs with the same group ID
20646 uint8_t led3_group_id;
20648 /* The states supported by LED #3. */
20649 uint16_t led3_state_caps;
20651 * If set to 1, this LED is enabled.
20652 * If set to 0, this LED is disabled.
20654 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED3_STATE_CAPS_ENABLED \
20657 * If set to 1, off state is supported on this LED.
20658 * If set to 0, off state is not supported on this LED.
20660 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED3_STATE_CAPS_OFF_SUPPORTED \
20663 * If set to 1, on state is supported on this LED.
20664 * If set to 0, on state is not supported on this LED.
20666 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED3_STATE_CAPS_ON_SUPPORTED \
20669 * If set to 1, blink state is supported on this LED.
20670 * If set to 0, blink state is not supported on this LED.
20672 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED3_STATE_CAPS_BLINK_SUPPORTED \
20675 * If set to 1, blink_alt state is supported on this LED.
20676 * If set to 0, blink_alt state is not supported on this LED.
20678 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED3_STATE_CAPS_BLINK_ALT_SUPPORTED \
20680 /* The colors supported by LED #3. */
20681 uint16_t led3_color_caps;
20683 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED3_COLOR_CAPS_RSVD \
20686 * If set to 1, Amber color is supported on this LED.
20687 * If set to 0, Amber color is not supported on this LED.
20689 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED3_COLOR_CAPS_AMBER_SUPPORTED \
20692 * If set to 1, Green color is supported on this LED.
20693 * If set to 0, Green color is not supported on this LED.
20695 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED3_COLOR_CAPS_GREEN_SUPPORTED \
20697 uint8_t unused_4[3];
20699 * This field is used in Output records to indicate that the output
20700 * is completely written to RAM. This field should be read as '1'
20701 * to indicate that the output has been completely written.
20702 * When writing a command completion or response to an internal processor,
20703 * the order of writes has to be such that this field is written last.
20708 /***********************
20709 * hwrm_port_prbs_test *
20710 ***********************/
20713 /* hwrm_port_prbs_test_input (size:384b/48B) */
20714 struct hwrm_port_prbs_test_input {
20715 /* The HWRM command request type. */
20718 * The completion ring to send the completion event on. This should
20719 * be the NQ ID returned from the `nq_alloc` HWRM command.
20721 uint16_t cmpl_ring;
20723 * The sequence ID is used by the driver for tracking multiple
20724 * commands. This ID is treated as opaque data by the firmware and
20725 * the value is returned in the `hwrm_resp_hdr` upon completion.
20729 * The target ID of the command:
20730 * * 0x0-0xFFF8 - The function ID
20731 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
20732 * * 0xFFFD - Reserved for user-space HWRM interface
20735 uint16_t target_id;
20737 * A physical address pointer pointing to a host buffer that the
20738 * command's response data will be written. This can be either a host
20739 * physical address (HPA) or a guest physical address (GPA) and must
20740 * point to a physically contiguous block of memory.
20742 uint64_t resp_addr;
20743 /* Host address data is to DMA'd to. */
20744 uint64_t resp_data_addr;
20746 * Size of the buffer pointed to by resp_data_addr. The firmware may
20747 * use this entire buffer or less than the entire buffer, but never more.
20752 /* Port ID of port where PRBS test to be run. */
20754 /* Polynomial selection for PRBS test. */
20757 #define HWRM_PORT_PRBS_TEST_INPUT_POLY_PRBS7 UINT32_C(0x0)
20759 #define HWRM_PORT_PRBS_TEST_INPUT_POLY_PRBS9 UINT32_C(0x1)
20761 #define HWRM_PORT_PRBS_TEST_INPUT_POLY_PRBS11 UINT32_C(0x2)
20763 #define HWRM_PORT_PRBS_TEST_INPUT_POLY_PRBS15 UINT32_C(0x3)
20765 #define HWRM_PORT_PRBS_TEST_INPUT_POLY_PRBS23 UINT32_C(0x4)
20767 #define HWRM_PORT_PRBS_TEST_INPUT_POLY_PRBS31 UINT32_C(0x5)
20769 #define HWRM_PORT_PRBS_TEST_INPUT_POLY_PRBS58 UINT32_C(0x6)
20771 #define HWRM_PORT_PRBS_TEST_INPUT_POLY_INVALID UINT32_C(0xff)
20772 #define HWRM_PORT_PRBS_TEST_INPUT_POLY_LAST \
20773 HWRM_PORT_PRBS_TEST_INPUT_POLY_INVALID
20775 * Configuration bits for PRBS test.
20776 * Use enable bit to start/stop test.
20777 * Use tx/rx lane map bits to run test on specific lanes,
20778 * if set to 0 test will be run on all lanes.
20780 uint16_t prbs_config;
20782 * Set 0 to stop test currently in progress
20783 * Set 1 to start test with configuration provided.
20785 #define HWRM_PORT_PRBS_TEST_INPUT_PRBS_CONFIG_START_STOP \
20788 * If set to 1, tx_lane_map bitmap should have lane bits set.
20789 * If set to 0, test will be run on all lanes for this port.
20791 #define HWRM_PORT_PRBS_TEST_INPUT_PRBS_CONFIG_TX_LANE_MAP_VALID \
20794 * If set to 1, rx_lane_map bitmap should have lane bits set.
20795 * If set to 0, test will be run on all lanes for this port.
20797 #define HWRM_PORT_PRBS_TEST_INPUT_PRBS_CONFIG_RX_LANE_MAP_VALID \
20799 /* Duration in seconds to run the PRBS test. */
20802 * If tx_lane_map_valid is set to 1, this field is a bitmap
20803 * of tx lanes to run PRBS test. bit0 = lane0,
20804 * bit1 = lane1 ..bit31 = lane31
20806 uint32_t tx_lane_map;
20808 * If rx_lane_map_valid is set to 1, this field is a bitmap
20809 * of rx lanes to run PRBS test. bit0 = lane0,
20810 * bit1 = lane1 ..bit31 = lane31
20812 uint32_t rx_lane_map;
20815 /* hwrm_port_prbs_test_output (size:128b/16B) */
20816 struct hwrm_port_prbs_test_output {
20817 /* The specific error status for the command. */
20818 uint16_t error_code;
20819 /* The HWRM command request type. */
20821 /* The sequence ID from the original command. */
20823 /* The length of the response data in number of bytes. */
20825 /* Total length of stored data. */
20826 uint16_t total_data_len;
20828 uint8_t unused_1[3];
20830 * This field is used in Output records to indicate that the output
20831 * is completely written to RAM. This field should be read as '1'
20832 * to indicate that the output has been completely written.
20833 * When writing a command completion or response to an internal processor,
20834 * the order of writes has to be such that this field is written last.
20839 /**********************
20840 * hwrm_port_dsc_dump *
20841 **********************/
20844 /* hwrm_port_dsc_dump_input (size:320b/40B) */
20845 struct hwrm_port_dsc_dump_input {
20846 /* The HWRM command request type. */
20849 * The completion ring to send the completion event on. This should
20850 * be the NQ ID returned from the `nq_alloc` HWRM command.
20852 uint16_t cmpl_ring;
20854 * The sequence ID is used by the driver for tracking multiple
20855 * commands. This ID is treated as opaque data by the firmware and
20856 * the value is returned in the `hwrm_resp_hdr` upon completion.
20860 * The target ID of the command:
20861 * * 0x0-0xFFF8 - The function ID
20862 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
20863 * * 0xFFFD - Reserved for user-space HWRM interface
20866 uint16_t target_id;
20868 * A physical address pointer pointing to a host buffer that the
20869 * command's response data will be written. This can be either a host
20870 * physical address (HPA) or a guest physical address (GPA) and must
20871 * point to a physically contiguous block of memory.
20873 uint64_t resp_addr;
20874 /* Host address where response diagnostic data is returned. */
20875 uint64_t resp_data_addr;
20877 * Size of the buffer pointed to by resp_data_addr. The firmware
20878 * may use this entire buffer or less than the entire buffer, but
20884 /* Port ID of port where dsc dump to be collected. */
20886 /* Diag level specified by the user */
20887 uint16_t diag_level;
20888 /* SRDS_DIAG_LANE */
20889 #define HWRM_PORT_DSC_DUMP_INPUT_DIAG_LEVEL_SRDS_DIAG_LANE \
20891 /* SRDS_DIAG_CORE */
20892 #define HWRM_PORT_DSC_DUMP_INPUT_DIAG_LEVEL_SRDS_DIAG_CORE \
20894 /* SRDS_DIAG_EVENT */
20895 #define HWRM_PORT_DSC_DUMP_INPUT_DIAG_LEVEL_SRDS_DIAG_EVENT \
20897 /* SRDS_DIAG_EYE */
20898 #define HWRM_PORT_DSC_DUMP_INPUT_DIAG_LEVEL_SRDS_DIAG_EYE \
20900 /* SRDS_DIAG_REG_CORE */
20901 #define HWRM_PORT_DSC_DUMP_INPUT_DIAG_LEVEL_SRDS_DIAG_REG_CORE \
20903 /* SRDS_DIAG_REG_LANE */
20904 #define HWRM_PORT_DSC_DUMP_INPUT_DIAG_LEVEL_SRDS_DIAG_REG_LANE \
20906 /* SRDS_DIAG_UC_CORE */
20907 #define HWRM_PORT_DSC_DUMP_INPUT_DIAG_LEVEL_SRDS_DIAG_UC_CORE \
20909 /* SRDS_DIAG_UC_LANE */
20910 #define HWRM_PORT_DSC_DUMP_INPUT_DIAG_LEVEL_SRDS_DIAG_UC_LANE \
20912 /* SRDS_DIAG_LANE_DEBUG */
20913 #define HWRM_PORT_DSC_DUMP_INPUT_DIAG_LEVEL_SRDS_DIAG_LANE_DEBUG \
20915 /* SRDS_DIAG_BER_VERT */
20916 #define HWRM_PORT_DSC_DUMP_INPUT_DIAG_LEVEL_SRDS_DIAG_BER_VERT \
20918 /* SRDS_DIAG_BER_HORZ */
20919 #define HWRM_PORT_DSC_DUMP_INPUT_DIAG_LEVEL_SRDS_DIAG_BER_HORZ \
20921 /* SRDS_DIAG_EVENT_SAFE */
20922 #define HWRM_PORT_DSC_DUMP_INPUT_DIAG_LEVEL_SRDS_DIAG_EVENT_SAFE \
20924 /* SRDS_DIAG_TIMESTAMP */
20925 #define HWRM_PORT_DSC_DUMP_INPUT_DIAG_LEVEL_SRDS_DIAG_TIMESTAMP \
20927 #define HWRM_PORT_DSC_DUMP_INPUT_DIAG_LEVEL_LAST \
20928 HWRM_PORT_DSC_DUMP_INPUT_DIAG_LEVEL_SRDS_DIAG_TIMESTAMP
20930 * This field is a lane number
20931 * on which to collect the dsc dump
20933 uint16_t lane_number;
20935 * Configuration bits.
20936 * Use enable bit to start dsc dump or retrieve dump
20938 uint16_t dsc_dump_config;
20940 * Set 0 to retrieve the dsc dump
20941 * Set 1 to start the dsc dump
20943 #define HWRM_PORT_DSC_DUMP_INPUT_DSC_DUMP_CONFIG_START_RETRIEVE \
20947 /* hwrm_port_dsc_dump_output (size:128b/16B) */
20948 struct hwrm_port_dsc_dump_output {
20949 /* The specific error status for the command. */
20950 uint16_t error_code;
20951 /* The HWRM command request type. */
20953 /* The sequence ID from the original command. */
20955 /* The length of the response data in number of bytes. */
20957 /* Total length of stored data. */
20958 uint16_t total_data_len;
20960 uint8_t unused_1[3];
20962 * This field is used in Output records to indicate that the output
20963 * is completely written to RAM. This field should be read as '1'
20964 * to indicate that the output has been completely written.
20965 * When writing a command completion or response to an internal processor,
20966 * the order of writes has to be such that this field is written last.
20971 /******************************
20972 * hwrm_port_sfp_sideband_cfg *
20973 ******************************/
20976 /* hwrm_port_sfp_sideband_cfg_input (size:256b/32B) */
20977 struct hwrm_port_sfp_sideband_cfg_input {
20978 /* The HWRM command request type. */
20981 * The completion ring to send the completion event on. This should
20982 * be the NQ ID returned from the `nq_alloc` HWRM command.
20984 uint16_t cmpl_ring;
20986 * The sequence ID is used by the driver for tracking multiple
20987 * commands. This ID is treated as opaque data by the firmware and
20988 * the value is returned in the `hwrm_resp_hdr` upon completion.
20992 * The target ID of the command:
20993 * * 0x0-0xFFF8 - The function ID
20994 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
20995 * * 0xFFFD - Reserved for user-space HWRM interface
20998 uint16_t target_id;
21000 * A physical address pointer pointing to a host buffer that the
21001 * command's response data will be written. This can be either a host
21002 * physical address (HPA) or a guest physical address (GPA) and must
21003 * point to a physically contiguous block of memory.
21005 uint64_t resp_addr;
21006 /* Port ID of port that is to be queried. */
21008 uint8_t unused_0[6];
21010 * This bitfield is used to specify which bits from the 'flags'
21011 * fields are being configured by the caller.
21014 /* This bit must be '1' for rs0 to be configured. */
21015 #define HWRM_PORT_SFP_SIDEBAND_CFG_INPUT_ENABLES_RS0 \
21017 /* This bit must be '1' for rs1 to be configured. */
21018 #define HWRM_PORT_SFP_SIDEBAND_CFG_INPUT_ENABLES_RS1 \
21020 /* This bit must be '1' for tx_disable to be configured. */
21021 #define HWRM_PORT_SFP_SIDEBAND_CFG_INPUT_ENABLES_TX_DIS \
21024 * This bit must be '1' for mod_sel to be configured.
21025 * Valid only on QSFP modules
21027 #define HWRM_PORT_SFP_SIDEBAND_CFG_INPUT_ENABLES_MOD_SEL \
21029 /* This bit must be '1' for reset_l to be configured. */
21030 #define HWRM_PORT_SFP_SIDEBAND_CFG_INPUT_ENABLES_RESET_L \
21032 /* This bit must be '1' for lp_mode to be configured. */
21033 #define HWRM_PORT_SFP_SIDEBAND_CFG_INPUT_ENABLES_LP_MODE \
21035 /* This bit must be '1' for pwr_disable to be configured. */
21036 #define HWRM_PORT_SFP_SIDEBAND_CFG_INPUT_ENABLES_PWR_DIS \
21039 * Only bits that have corresponding bits in the 'enables'
21040 * bitfield are processed by the firmware, all other bits
21041 * of 'flags' are ignored.
21045 * This bit along with rs1 configures the current speed of the dual
21046 * rate module. If these pins are GNDed then the speed can be changed
21047 * by driectly writing to EEPROM.
21049 #define HWRM_PORT_SFP_SIDEBAND_CFG_INPUT_FLAGS_RS0 \
21052 * This bit along with rs0 configures the current speed of the dual
21053 * rate module. If these pins are GNDed then the speed can be changed
21054 * by driectly writing to EEPROM.
21056 #define HWRM_PORT_SFP_SIDEBAND_CFG_INPUT_FLAGS_RS1 \
21059 * When this bit is set to '1', tx_disable is set.
21060 * On a 1G BASE-T module, if this bit is set,
21061 * module PHY registers will not be accessible.
21063 #define HWRM_PORT_SFP_SIDEBAND_CFG_INPUT_FLAGS_TX_DIS \
21066 * When this bit is set to '1', this module is selected.
21067 * Valid only on QSFP modules
21069 #define HWRM_PORT_SFP_SIDEBAND_CFG_INPUT_FLAGS_MOD_SEL \
21072 * If reset_l is set to 0, Module will be taken out of reset
21073 * and other signals will be set to their requested state once
21074 * the module is out of reset.
21075 * Valid only on QSFP modules
21077 #define HWRM_PORT_SFP_SIDEBAND_CFG_INPUT_FLAGS_RESET_L \
21080 * When this bit is set to '1', the module will be configured
21081 * in low power mode.
21082 * Valid only on QSFP modules
21084 #define HWRM_PORT_SFP_SIDEBAND_CFG_INPUT_FLAGS_LP_MODE \
21086 /* When this bit is set to '1', the module will be powered down. */
21087 #define HWRM_PORT_SFP_SIDEBAND_CFG_INPUT_FLAGS_PWR_DIS \
21091 /* hwrm_port_sfp_sideband_cfg_output (size:128b/16B) */
21092 struct hwrm_port_sfp_sideband_cfg_output {
21093 /* The specific error status for the command. */
21094 uint16_t error_code;
21095 /* The HWRM command request type. */
21097 /* The sequence ID from the original command. */
21099 /* The length of the response data in number of bytes. */
21103 * This field is used in Output records to indicate that the output
21104 * is completely written to RAM. This field should be read as '1'
21105 * to indicate that the output has been completely written. When
21106 * writing a command completion or response to an internal processor,
21107 * the order of writes has to be such that this field is written last.
21112 /*******************************
21113 * hwrm_port_sfp_sideband_qcfg *
21114 *******************************/
21117 /* hwrm_port_sfp_sideband_qcfg_input (size:192b/24B) */
21118 struct hwrm_port_sfp_sideband_qcfg_input {
21119 /* The HWRM command request type. */
21122 * The completion ring to send the completion event on. This should
21123 * be the NQ ID returned from the `nq_alloc` HWRM command.
21125 uint16_t cmpl_ring;
21127 * The sequence ID is used by the driver for tracking multiple
21128 * commands. This ID is treated as opaque data by the firmware and
21129 * the value is returned in the `hwrm_resp_hdr` upon completion.
21133 * The target ID of the command:
21134 * * 0x0-0xFFF8 - The function ID
21135 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
21136 * * 0xFFFD - Reserved for user-space HWRM interface
21139 uint16_t target_id;
21141 * A physical address pointer pointing to a host buffer that the
21142 * command's response data will be written. This can be either a host
21143 * physical address (HPA) or a guest physical address (GPA) and must
21144 * point to a physically contiguous block of memory.
21146 uint64_t resp_addr;
21147 /* Port ID of port that is to be queried. */
21149 uint8_t unused_0[6];
21152 /* hwrm_port_sfp_sideband_qcfg_output (size:192b/24B) */
21153 struct hwrm_port_sfp_sideband_qcfg_output {
21154 /* The specific error status for the command. */
21155 uint16_t error_code;
21156 /* The HWRM command request type. */
21158 /* The sequence ID from the original command. */
21160 /* The length of the response data in number of bytes. */
21163 * Bitmask indicating which sideband signals are valid.
21164 * This is based on the board and nvm cfg that is present on the board.
21166 uint32_t supported_mask;
21167 uint32_t sideband_signals;
21168 /* When this bit is set to '1', the Module is absent. */
21169 #define HWRM_PORT_SFP_SIDEBAND_QCFG_OUTPUT_SIDEBAND_SIGNALS_MOD_ABS \
21172 * When this bit is set to '1', there is no valid signal on RX.
21173 * This signal is a filtered version of Signal Detect.
21175 #define HWRM_PORT_SFP_SIDEBAND_QCFG_OUTPUT_SIDEBAND_SIGNALS_RX_LOS \
21178 * This bit along with rs1 indiactes the current speed of the dual
21179 * rate module.If these pins are grounded then the speed can be
21180 * changed by driectky writing to EEPROM.
21182 #define HWRM_PORT_SFP_SIDEBAND_QCFG_OUTPUT_SIDEBAND_SIGNALS_RS0 \
21185 * This bit along with rs0 indiactes the current speed of the dual
21186 * rate module.If these pins are grounded then the speed can be
21187 * changed by driectky writing to EEPROM.
21189 #define HWRM_PORT_SFP_SIDEBAND_QCFG_OUTPUT_SIDEBAND_SIGNALS_RS1 \
21192 * When this bit is set to '1', tx_disable is set.
21193 * On a 1G BASE-T module, if this bit is set, module PHY
21194 * registers will not be accessible.
21196 #define HWRM_PORT_SFP_SIDEBAND_QCFG_OUTPUT_SIDEBAND_SIGNALS_TX_DIS \
21198 /* When this bit is set to '1', tx_fault is set. */
21199 #define HWRM_PORT_SFP_SIDEBAND_QCFG_OUTPUT_SIDEBAND_SIGNALS_TX_FAULT \
21202 * When this bit is set to '1', module is selected.
21203 * Valid only on QSFP modules
21205 #define HWRM_PORT_SFP_SIDEBAND_QCFG_OUTPUT_SIDEBAND_SIGNALS_MOD_SEL \
21208 * When this bit is set to '0', the module is held in reset.
21209 * if reset_l is set to 1,first module is taken out of reset
21210 * and other signals will be set to their requested state.
21211 * Valid only on QSFP modules.
21213 #define HWRM_PORT_SFP_SIDEBAND_QCFG_OUTPUT_SIDEBAND_SIGNALS_RESET_L \
21216 * When this bit is set to '1', the module is in low power mode.
21217 * Valid only on QSFP modules
21219 #define HWRM_PORT_SFP_SIDEBAND_QCFG_OUTPUT_SIDEBAND_SIGNALS_LP_MODE \
21221 /* When this bit is set to '1', module is in power down state. */
21222 #define HWRM_PORT_SFP_SIDEBAND_QCFG_OUTPUT_SIDEBAND_SIGNALS_PWR_DIS \
21226 * This field is used in Output records to indicate that the output
21227 * is completely written to RAM. This field should be read as '1'
21228 * to indicate that the output has been completely written. When
21229 * writing a command completion or response to an internal processor,
21230 * the order of writes has to be such that this field is written last.
21235 /**********************************
21236 * hwrm_port_phy_mdio_bus_acquire *
21237 **********************************/
21240 /* hwrm_port_phy_mdio_bus_acquire_input (size:192b/24B) */
21241 struct hwrm_port_phy_mdio_bus_acquire_input {
21242 /* The HWRM command request type. */
21245 * The completion ring to send the completion event on. This should
21246 * be the NQ ID returned from the `nq_alloc` HWRM command.
21248 uint16_t cmpl_ring;
21250 * The sequence ID is used by the driver for tracking multiple
21251 * commands. This ID is treated as opaque data by the firmware and
21252 * the value is returned in the `hwrm_resp_hdr` upon completion.
21256 * The target ID of the command:
21257 * * 0x0-0xFFF8 - The function ID
21258 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
21259 * * 0xFFFD - Reserved for user-space HWRM interface
21262 uint16_t target_id;
21264 * A physical address pointer pointing to a host buffer that the
21265 * command's response data will be written. This can be either a host
21266 * physical address (HPA) or a guest physical address (GPA) and must
21267 * point to a physically contiguous block of memory.
21269 uint64_t resp_addr;
21270 /* Port ID of the port. */
21273 * client_id of the client requesting BUS access.
21274 * Any value from 0x10 to 0xFFFF can be used.
21275 * Client should make sure that the returned client_id
21276 * in response matches the client_id in request.
21277 * 0-0xF are reserved for internal use.
21279 uint16_t client_id;
21281 * Timeout in milli seconds, MDIO BUS will be released automatically
21282 * after this time, if another mdio acquire command is not received
21283 * within the timeout window from the same client.
21284 * A 0xFFFF will hold the bus until this bus is released.
21286 uint16_t mdio_bus_timeout;
21287 uint8_t unused_0[2];
21290 /* hwrm_port_phy_mdio_bus_acquire_output (size:128b/16B) */
21291 struct hwrm_port_phy_mdio_bus_acquire_output {
21292 /* The specific error status for the command. */
21293 uint16_t error_code;
21294 /* The HWRM command request type. */
21296 /* The sequence ID from the original command. */
21298 /* The length of the response data in number of bytes. */
21302 * client_id of the module holding the BUS.
21303 * 0-0xF are reserved for internal use.
21305 uint16_t client_id;
21306 uint8_t unused_1[3];
21308 * This field is used in Output records to indicate that the output
21309 * is completely written to RAM. This field should be read as '1'
21310 * to indicate that the output has been completely written.
21311 * When writing a command completion or response to an internal processor,
21312 * the order of writes has to be such that this field is written last.
21317 /**********************************
21318 * hwrm_port_phy_mdio_bus_release *
21319 **********************************/
21322 /* hwrm_port_phy_mdio_bus_release_input (size:192b/24B) */
21323 struct hwrm_port_phy_mdio_bus_release_input {
21324 /* The HWRM command request type. */
21327 * The completion ring to send the completion event on. This should
21328 * be the NQ ID returned from the `nq_alloc` HWRM command.
21330 uint16_t cmpl_ring;
21332 * The sequence ID is used by the driver for tracking multiple
21333 * commands. This ID is treated as opaque data by the firmware and
21334 * the value is returned in the `hwrm_resp_hdr` upon completion.
21338 * The target ID of the command:
21339 * * 0x0-0xFFF8 - The function ID
21340 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
21341 * * 0xFFFD - Reserved for user-space HWRM interface
21344 uint16_t target_id;
21346 * A physical address pointer pointing to a host buffer that the
21347 * command's response data will be written. This can be either a host
21348 * physical address (HPA) or a guest physical address (GPA) and must
21349 * point to a physically contiguous block of memory.
21351 uint64_t resp_addr;
21352 /* Port ID of the port. */
21355 * client_id of the client requesting BUS release.
21356 * A client should not release any other clients BUS.
21358 uint16_t client_id;
21359 uint8_t unused_0[4];
21362 /* hwrm_port_phy_mdio_bus_release_output (size:128b/16B) */
21363 struct hwrm_port_phy_mdio_bus_release_output {
21364 /* The specific error status for the command. */
21365 uint16_t error_code;
21366 /* The HWRM command request type. */
21368 /* The sequence ID from the original command. */
21370 /* The length of the response data in number of bytes. */
21373 /* The BUS is released if client_id matches the client_id in request. */
21374 uint16_t clients_id;
21375 uint8_t unused_1[3];
21377 * This field is used in Output records to indicate that the output
21378 * is completely written to RAM. This field should be read as '1'
21379 * to indicate that the output has been completely written.
21380 * When writing a command completion or response to an internal processor,
21381 * the order of writes has to be such that this field is written last.
21386 /***********************
21387 * hwrm_queue_qportcfg *
21388 ***********************/
21391 /* hwrm_queue_qportcfg_input (size:192b/24B) */
21392 struct hwrm_queue_qportcfg_input {
21393 /* The HWRM command request type. */
21396 * The completion ring to send the completion event on. This should
21397 * be the NQ ID returned from the `nq_alloc` HWRM command.
21399 uint16_t cmpl_ring;
21401 * The sequence ID is used by the driver for tracking multiple
21402 * commands. This ID is treated as opaque data by the firmware and
21403 * the value is returned in the `hwrm_resp_hdr` upon completion.
21407 * The target ID of the command:
21408 * * 0x0-0xFFF8 - The function ID
21409 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
21410 * * 0xFFFD - Reserved for user-space HWRM interface
21413 uint16_t target_id;
21415 * A physical address pointer pointing to a host buffer that the
21416 * command's response data will be written. This can be either a host
21417 * physical address (HPA) or a guest physical address (GPA) and must
21418 * point to a physically contiguous block of memory.
21420 uint64_t resp_addr;
21423 * Enumeration denoting the RX, TX type of the resource.
21424 * This enumeration is used for resources that are similar for both
21425 * TX and RX paths of the chip.
21427 #define HWRM_QUEUE_QPORTCFG_INPUT_FLAGS_PATH UINT32_C(0x1)
21429 #define HWRM_QUEUE_QPORTCFG_INPUT_FLAGS_PATH_TX UINT32_C(0x0)
21431 #define HWRM_QUEUE_QPORTCFG_INPUT_FLAGS_PATH_RX UINT32_C(0x1)
21432 #define HWRM_QUEUE_QPORTCFG_INPUT_FLAGS_PATH_LAST \
21433 HWRM_QUEUE_QPORTCFG_INPUT_FLAGS_PATH_RX
21435 * Port ID of port for which the queue configuration is being
21436 * queried. This field is only required when sent by IPC.
21440 * Drivers will set this capability when it can use
21441 * queue_idx_service_profile to map the queues to application.
21443 uint8_t drv_qmap_cap;
21445 #define HWRM_QUEUE_QPORTCFG_INPUT_DRV_QMAP_CAP_DISABLED UINT32_C(0x0)
21447 #define HWRM_QUEUE_QPORTCFG_INPUT_DRV_QMAP_CAP_ENABLED UINT32_C(0x1)
21448 #define HWRM_QUEUE_QPORTCFG_INPUT_DRV_QMAP_CAP_LAST \
21449 HWRM_QUEUE_QPORTCFG_INPUT_DRV_QMAP_CAP_ENABLED
21453 /* hwrm_queue_qportcfg_output (size:1344b/168B) */
21454 struct hwrm_queue_qportcfg_output {
21455 /* The specific error status for the command. */
21456 uint16_t error_code;
21457 /* The HWRM command request type. */
21459 /* The sequence ID from the original command. */
21461 /* The length of the response data in number of bytes. */
21464 * The maximum number of queues that can be configured on this
21466 * Valid values range from 1 through 8.
21468 uint8_t max_configurable_queues;
21470 * The maximum number of lossless queues that can be configured
21472 * Valid values range from 0 through 8.
21474 uint8_t max_configurable_lossless_queues;
21476 * Bitmask indicating which queues can be configured by the
21477 * hwrm_queue_cfg command.
21479 * Each bit represents a specific queue where bit 0 represents
21480 * queue 0 and bit 7 represents queue 7.
21481 * # A value of 0 indicates that the queue is not configurable
21482 * by the hwrm_queue_cfg command.
21483 * # A value of 1 indicates that the queue is configurable.
21484 * # A hwrm_queue_cfg command shall return error when trying to
21485 * configure a queue not configurable.
21487 uint8_t queue_cfg_allowed;
21488 /* Information about queue configuration. */
21489 uint8_t queue_cfg_info;
21491 * If this flag is set to '1', then the queues are
21492 * configured asymmetrically on TX and RX sides.
21493 * If this flag is set to '0', then the queues are
21494 * configured symmetrically on TX and RX sides. For
21495 * symmetric configuration, the queue configuration
21496 * including queue ids and service profiles on the
21497 * TX side is the same as the corresponding queue
21498 * configuration on the RX side.
21500 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_CFG_INFO_ASYM_CFG \
21503 * Bitmask indicating which queues can be configured by the
21504 * hwrm_queue_pfcenable_cfg command.
21506 * Each bit represents a specific priority where bit 0 represents
21507 * priority 0 and bit 7 represents priority 7.
21508 * # A value of 0 indicates that the priority is not configurable by
21509 * the hwrm_queue_pfcenable_cfg command.
21510 * # A value of 1 indicates that the priority is configurable.
21511 * # A hwrm_queue_pfcenable_cfg command shall return error when
21512 * trying to configure a priority that is not configurable.
21514 uint8_t queue_pfcenable_cfg_allowed;
21516 * Bitmask indicating which queues can be configured by the
21517 * hwrm_queue_pri2cos_cfg command.
21519 * Each bit represents a specific queue where bit 0 represents
21520 * queue 0 and bit 7 represents queue 7.
21521 * # A value of 0 indicates that the queue is not configurable
21522 * by the hwrm_queue_pri2cos_cfg command.
21523 * # A value of 1 indicates that the queue is configurable.
21524 * # A hwrm_queue_pri2cos_cfg command shall return error when
21525 * trying to configure a queue that is not configurable.
21527 uint8_t queue_pri2cos_cfg_allowed;
21529 * Bitmask indicating which queues can be configured by the
21530 * hwrm_queue_pri2cos_cfg command.
21532 * Each bit represents a specific queue where bit 0 represents
21533 * queue 0 and bit 7 represents queue 7.
21534 * # A value of 0 indicates that the queue is not configurable
21535 * by the hwrm_queue_pri2cos_cfg command.
21536 * # A value of 1 indicates that the queue is configurable.
21537 * # A hwrm_queue_pri2cos_cfg command shall return error when
21538 * trying to configure a queue not configurable.
21540 uint8_t queue_cos2bw_cfg_allowed;
21542 * ID of CoS Queue 0.
21545 * # This ID can be used on any subsequent call to an hwrm command
21546 * that takes a queue id.
21547 * # IDs must always be queried by this command before any use
21548 * by the driver or software.
21549 * # Any driver or software should not make any assumptions about
21551 * # A value of 0xff indicates that the queue is not available.
21552 * # Available queues may not be in sequential order.
21555 /* This value is applicable to CoS queues only. */
21556 uint8_t queue_id0_service_profile;
21557 /* Lossy (best-effort) */
21558 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID0_SERVICE_PROFILE_LOSSY \
21560 /* Lossless (legacy) */
21561 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID0_SERVICE_PROFILE_LOSSLESS \
21563 /* Lossless RoCE */
21564 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID0_SERVICE_PROFILE_LOSSLESS_ROCE \
21566 /* Lossy RoCE CNP */
21567 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID0_SERVICE_PROFILE_LOSSY_ROCE_CNP \
21570 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID0_SERVICE_PROFILE_LOSSLESS_NIC \
21572 /* Set to 0xFF... (All Fs) if there is no service profile specified */
21573 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID0_SERVICE_PROFILE_UNKNOWN \
21575 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID0_SERVICE_PROFILE_LAST \
21576 HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID0_SERVICE_PROFILE_UNKNOWN
21578 * ID of CoS Queue 1.
21581 * # This ID can be used on any subsequent call to an hwrm command
21582 * that takes a queue id.
21583 * # IDs must always be queried by this command before any use
21584 * by the driver or software.
21585 * # Any driver or software should not make any assumptions about
21587 * # A value of 0xff indicates that the queue is not available.
21588 * # Available queues may not be in sequential order.
21591 /* This value is applicable to CoS queues only. */
21592 uint8_t queue_id1_service_profile;
21593 /* Lossy (best-effort) */
21594 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID1_SERVICE_PROFILE_LOSSY \
21596 /* Lossless (legacy) */
21597 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID1_SERVICE_PROFILE_LOSSLESS \
21599 /* Lossless RoCE */
21600 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID1_SERVICE_PROFILE_LOSSLESS_ROCE \
21602 /* Lossy RoCE CNP */
21603 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID1_SERVICE_PROFILE_LOSSY_ROCE_CNP \
21606 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID1_SERVICE_PROFILE_LOSSLESS_NIC \
21608 /* Set to 0xFF... (All Fs) if there is no service profile specified */
21609 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID1_SERVICE_PROFILE_UNKNOWN \
21611 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID1_SERVICE_PROFILE_LAST \
21612 HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID1_SERVICE_PROFILE_UNKNOWN
21614 * ID of CoS Queue 2.
21617 * # This ID can be used on any subsequent call to an hwrm command
21618 * that takes a queue id.
21619 * # IDs must always be queried by this command before any use
21620 * by the driver or software.
21621 * # Any driver or software should not make any assumptions about
21623 * # A value of 0xff indicates that the queue is not available.
21624 * # Available queues may not be in sequential order.
21627 /* This value is applicable to CoS queues only. */
21628 uint8_t queue_id2_service_profile;
21629 /* Lossy (best-effort) */
21630 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID2_SERVICE_PROFILE_LOSSY \
21632 /* Lossless (legacy) */
21633 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID2_SERVICE_PROFILE_LOSSLESS \
21635 /* Lossless RoCE */
21636 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID2_SERVICE_PROFILE_LOSSLESS_ROCE \
21638 /* Lossy RoCE CNP */
21639 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID2_SERVICE_PROFILE_LOSSY_ROCE_CNP \
21642 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID2_SERVICE_PROFILE_LOSSLESS_NIC \
21644 /* Set to 0xFF... (All Fs) if there is no service profile specified */
21645 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID2_SERVICE_PROFILE_UNKNOWN \
21647 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID2_SERVICE_PROFILE_LAST \
21648 HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID2_SERVICE_PROFILE_UNKNOWN
21650 * ID of CoS Queue 3.
21653 * # This ID can be used on any subsequent call to an hwrm command
21654 * that takes a queue id.
21655 * # IDs must always be queried by this command before any use
21656 * by the driver or software.
21657 * # Any driver or software should not make any assumptions about
21659 * # A value of 0xff indicates that the queue is not available.
21660 * # Available queues may not be in sequential order.
21663 /* This value is applicable to CoS queues only. */
21664 uint8_t queue_id3_service_profile;
21665 /* Lossy (best-effort) */
21666 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID3_SERVICE_PROFILE_LOSSY \
21668 /* Lossless (legacy) */
21669 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID3_SERVICE_PROFILE_LOSSLESS \
21671 /* Lossless RoCE */
21672 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID3_SERVICE_PROFILE_LOSSLESS_ROCE \
21674 /* Lossy RoCE CNP */
21675 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID3_SERVICE_PROFILE_LOSSY_ROCE_CNP \
21678 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID3_SERVICE_PROFILE_LOSSLESS_NIC \
21680 /* Set to 0xFF... (All Fs) if there is no service profile specified */
21681 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID3_SERVICE_PROFILE_UNKNOWN \
21683 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID3_SERVICE_PROFILE_LAST \
21684 HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID3_SERVICE_PROFILE_UNKNOWN
21686 * ID of CoS Queue 4.
21689 * # This ID can be used on any subsequent call to an hwrm command
21690 * that takes a queue id.
21691 * # IDs must always be queried by this command before any use
21692 * by the driver or software.
21693 * # Any driver or software should not make any assumptions about
21695 * # A value of 0xff indicates that the queue is not available.
21696 * # Available queues may not be in sequential order.
21699 /* This value is applicable to CoS queues only. */
21700 uint8_t queue_id4_service_profile;
21701 /* Lossy (best-effort) */
21702 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID4_SERVICE_PROFILE_LOSSY \
21704 /* Lossless (legacy) */
21705 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID4_SERVICE_PROFILE_LOSSLESS \
21707 /* Lossless RoCE */
21708 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID4_SERVICE_PROFILE_LOSSLESS_ROCE \
21710 /* Lossy RoCE CNP */
21711 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID4_SERVICE_PROFILE_LOSSY_ROCE_CNP \
21714 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID4_SERVICE_PROFILE_LOSSLESS_NIC \
21716 /* Set to 0xFF... (All Fs) if there is no service profile specified */
21717 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID4_SERVICE_PROFILE_UNKNOWN \
21719 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID4_SERVICE_PROFILE_LAST \
21720 HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID4_SERVICE_PROFILE_UNKNOWN
21722 * ID of CoS Queue 5.
21725 * # This ID can be used on any subsequent call to an hwrm command
21726 * that takes a queue id.
21727 * # IDs must always be queried by this command before any use
21728 * by the driver or software.
21729 * # Any driver or software should not make any assumptions about
21731 * # A value of 0xff indicates that the queue is not available.
21732 * # Available queues may not be in sequential order.
21735 /* This value is applicable to CoS queues only. */
21736 uint8_t queue_id5_service_profile;
21737 /* Lossy (best-effort) */
21738 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID5_SERVICE_PROFILE_LOSSY \
21740 /* Lossless (legacy) */
21741 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID5_SERVICE_PROFILE_LOSSLESS \
21743 /* Lossless RoCE */
21744 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID5_SERVICE_PROFILE_LOSSLESS_ROCE \
21746 /* Lossy RoCE CNP */
21747 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID5_SERVICE_PROFILE_LOSSY_ROCE_CNP \
21750 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID5_SERVICE_PROFILE_LOSSLESS_NIC \
21752 /* Set to 0xFF... (All Fs) if there is no service profile specified */
21753 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID5_SERVICE_PROFILE_UNKNOWN \
21755 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID5_SERVICE_PROFILE_LAST \
21756 HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID5_SERVICE_PROFILE_UNKNOWN
21758 * ID of CoS Queue 6.
21761 * # This ID can be used on any subsequent call to an hwrm command
21762 * that takes a queue id.
21763 * # IDs must always be queried by this command before any use
21764 * by the driver or software.
21765 * # Any driver or software should not make any assumptions about
21767 * # A value of 0xff indicates that the queue is not available.
21768 * # Available queues may not be in sequential order.
21771 /* This value is applicable to CoS queues only. */
21772 uint8_t queue_id6_service_profile;
21773 /* Lossy (best-effort) */
21774 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID6_SERVICE_PROFILE_LOSSY \
21776 /* Lossless (legacy) */
21777 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID6_SERVICE_PROFILE_LOSSLESS \
21779 /* Lossless RoCE */
21780 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID6_SERVICE_PROFILE_LOSSLESS_ROCE \
21782 /* Lossy RoCE CNP */
21783 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID6_SERVICE_PROFILE_LOSSY_ROCE_CNP \
21786 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID6_SERVICE_PROFILE_LOSSLESS_NIC \
21788 /* Set to 0xFF... (All Fs) if there is no service profile specified */
21789 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID6_SERVICE_PROFILE_UNKNOWN \
21791 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID6_SERVICE_PROFILE_LAST \
21792 HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID6_SERVICE_PROFILE_UNKNOWN
21794 * ID of CoS Queue 7.
21797 * # This ID can be used on any subsequent call to an hwrm command
21798 * that takes a queue id.
21799 * # IDs must always be queried by this command before any use
21800 * by the driver or software.
21801 * # Any driver or software should not make any assumptions about
21803 * # A value of 0xff indicates that the queue is not available.
21804 * # Available queues may not be in sequential order.
21807 /* This value is applicable to CoS queues only. */
21808 uint8_t queue_id7_service_profile;
21809 /* Lossy (best-effort) */
21810 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID7_SERVICE_PROFILE_LOSSY \
21812 /* Lossless (legacy) */
21813 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID7_SERVICE_PROFILE_LOSSLESS \
21815 /* Lossless RoCE */
21816 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID7_SERVICE_PROFILE_LOSSLESS_ROCE \
21818 /* Lossy RoCE CNP */
21819 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID7_SERVICE_PROFILE_LOSSY_ROCE_CNP \
21822 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID7_SERVICE_PROFILE_LOSSLESS_NIC \
21824 /* Set to 0xFF... (All Fs) if there is no service profile specified */
21825 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID7_SERVICE_PROFILE_UNKNOWN \
21827 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID7_SERVICE_PROFILE_LAST \
21828 HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID7_SERVICE_PROFILE_UNKNOWN
21831 * Up to 16 bytes of null padded ASCII string describing this queue.
21832 * The queue name includes a CoS queue index and, in some cases, text
21833 * that distinguishes the queue from other queues in the group.
21835 char qid0_name[16];
21836 /* Up to 16 bytes of null padded ASCII string describing this queue. */
21837 char qid1_name[16];
21838 /* Up to 16 bytes of null padded ASCII string describing this queue. */
21839 char qid2_name[16];
21840 /* Up to 16 bytes of null padded ASCII string describing this queue. */
21841 char qid3_name[16];
21842 /* Up to 16 bytes of null padded ASCII string describing this queue. */
21843 char qid4_name[16];
21844 /* Up to 16 bytes of null padded ASCII string describing this queue. */
21845 char qid5_name[16];
21846 /* Up to 16 bytes of null padded ASCII string describing this queue. */
21847 char qid6_name[16];
21848 /* Up to 16 bytes of null padded ASCII string describing this queue. */
21849 char qid7_name[16];
21850 uint8_t unused_1[7];
21852 * This field is used in Output records to indicate that the output
21853 * is completely written to RAM. This field should be read as '1'
21854 * to indicate that the output has been completely written.
21855 * When writing a command completion or response to an internal processor,
21856 * the order of writes has to be such that this field is written last.
21861 /*******************
21862 * hwrm_queue_qcfg *
21863 *******************/
21866 /* hwrm_queue_qcfg_input (size:192b/24B) */
21867 struct hwrm_queue_qcfg_input {
21868 /* The HWRM command request type. */
21871 * The completion ring to send the completion event on. This should
21872 * be the NQ ID returned from the `nq_alloc` HWRM command.
21874 uint16_t cmpl_ring;
21876 * The sequence ID is used by the driver for tracking multiple
21877 * commands. This ID is treated as opaque data by the firmware and
21878 * the value is returned in the `hwrm_resp_hdr` upon completion.
21882 * The target ID of the command:
21883 * * 0x0-0xFFF8 - The function ID
21884 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
21885 * * 0xFFFD - Reserved for user-space HWRM interface
21888 uint16_t target_id;
21890 * A physical address pointer pointing to a host buffer that the
21891 * command's response data will be written. This can be either a host
21892 * physical address (HPA) or a guest physical address (GPA) and must
21893 * point to a physically contiguous block of memory.
21895 uint64_t resp_addr;
21898 * Enumeration denoting the RX, TX type of the resource.
21899 * This enumeration is used for resources that are similar for both
21900 * TX and RX paths of the chip.
21902 #define HWRM_QUEUE_QCFG_INPUT_FLAGS_PATH UINT32_C(0x1)
21904 #define HWRM_QUEUE_QCFG_INPUT_FLAGS_PATH_TX UINT32_C(0x0)
21906 #define HWRM_QUEUE_QCFG_INPUT_FLAGS_PATH_RX UINT32_C(0x1)
21907 #define HWRM_QUEUE_QCFG_INPUT_FLAGS_PATH_LAST \
21908 HWRM_QUEUE_QCFG_INPUT_FLAGS_PATH_RX
21909 /* Queue ID of the queue. */
21913 /* hwrm_queue_qcfg_output (size:128b/16B) */
21914 struct hwrm_queue_qcfg_output {
21915 /* The specific error status for the command. */
21916 uint16_t error_code;
21917 /* The HWRM command request type. */
21919 /* The sequence ID from the original command. */
21921 /* The length of the response data in number of bytes. */
21924 * This value is the estimate packet length used in the
21927 uint32_t queue_len;
21928 /* This value is applicable to CoS queues only. */
21929 uint8_t service_profile;
21930 /* Lossy (best-effort) */
21931 #define HWRM_QUEUE_QCFG_OUTPUT_SERVICE_PROFILE_LOSSY UINT32_C(0x0)
21933 #define HWRM_QUEUE_QCFG_OUTPUT_SERVICE_PROFILE_LOSSLESS UINT32_C(0x1)
21934 /* Set to 0xFF... (All Fs) if there is no service profile specified */
21935 #define HWRM_QUEUE_QCFG_OUTPUT_SERVICE_PROFILE_UNKNOWN UINT32_C(0xff)
21936 #define HWRM_QUEUE_QCFG_OUTPUT_SERVICE_PROFILE_LAST \
21937 HWRM_QUEUE_QCFG_OUTPUT_SERVICE_PROFILE_UNKNOWN
21938 /* Information about queue configuration. */
21939 uint8_t queue_cfg_info;
21941 * If this flag is set to '1', then the queue is
21942 * configured asymmetrically on TX and RX sides.
21943 * If this flag is set to '0', then this queue is
21944 * configured symmetrically on TX and RX sides.
21946 #define HWRM_QUEUE_QCFG_OUTPUT_QUEUE_CFG_INFO_ASYM_CFG \
21950 * This field is used in Output records to indicate that the output
21951 * is completely written to RAM. This field should be read as '1'
21952 * to indicate that the output has been completely written.
21953 * When writing a command completion or response to an internal processor,
21954 * the order of writes has to be such that this field is written last.
21959 /******************
21961 ******************/
21964 /* hwrm_queue_cfg_input (size:320b/40B) */
21965 struct hwrm_queue_cfg_input {
21966 /* The HWRM command request type. */
21969 * The completion ring to send the completion event on. This should
21970 * be the NQ ID returned from the `nq_alloc` HWRM command.
21972 uint16_t cmpl_ring;
21974 * The sequence ID is used by the driver for tracking multiple
21975 * commands. This ID is treated as opaque data by the firmware and
21976 * the value is returned in the `hwrm_resp_hdr` upon completion.
21980 * The target ID of the command:
21981 * * 0x0-0xFFF8 - The function ID
21982 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
21983 * * 0xFFFD - Reserved for user-space HWRM interface
21986 uint16_t target_id;
21988 * A physical address pointer pointing to a host buffer that the
21989 * command's response data will be written. This can be either a host
21990 * physical address (HPA) or a guest physical address (GPA) and must
21991 * point to a physically contiguous block of memory.
21993 uint64_t resp_addr;
21996 * Enumeration denoting the RX, TX, or both directions applicable to the resource.
21997 * This enumeration is used for resources that are similar for both
21998 * TX and RX paths of the chip.
22000 #define HWRM_QUEUE_CFG_INPUT_FLAGS_PATH_MASK UINT32_C(0x3)
22001 #define HWRM_QUEUE_CFG_INPUT_FLAGS_PATH_SFT 0
22003 #define HWRM_QUEUE_CFG_INPUT_FLAGS_PATH_TX UINT32_C(0x0)
22005 #define HWRM_QUEUE_CFG_INPUT_FLAGS_PATH_RX UINT32_C(0x1)
22006 /* Bi-directional (Symmetrically applicable to TX and RX paths) */
22007 #define HWRM_QUEUE_CFG_INPUT_FLAGS_PATH_BIDIR UINT32_C(0x2)
22008 #define HWRM_QUEUE_CFG_INPUT_FLAGS_PATH_LAST \
22009 HWRM_QUEUE_CFG_INPUT_FLAGS_PATH_BIDIR
22012 * This bit must be '1' for the dflt_len field to be
22015 #define HWRM_QUEUE_CFG_INPUT_ENABLES_DFLT_LEN UINT32_C(0x1)
22017 * This bit must be '1' for the service_profile field to be
22020 #define HWRM_QUEUE_CFG_INPUT_ENABLES_SERVICE_PROFILE UINT32_C(0x2)
22021 /* Queue ID of queue that is to be configured by this function. */
22024 * This value is a the estimate packet length used in the
22026 * Set to 0xFF... (All Fs) to not adjust this value.
22029 /* This value is applicable to CoS queues only. */
22030 uint8_t service_profile;
22031 /* Lossy (best-effort) */
22032 #define HWRM_QUEUE_CFG_INPUT_SERVICE_PROFILE_LOSSY UINT32_C(0x0)
22034 #define HWRM_QUEUE_CFG_INPUT_SERVICE_PROFILE_LOSSLESS UINT32_C(0x1)
22035 /* Set to 0xFF... (All Fs) if there is no service profile specified */
22036 #define HWRM_QUEUE_CFG_INPUT_SERVICE_PROFILE_UNKNOWN UINT32_C(0xff)
22037 #define HWRM_QUEUE_CFG_INPUT_SERVICE_PROFILE_LAST \
22038 HWRM_QUEUE_CFG_INPUT_SERVICE_PROFILE_UNKNOWN
22039 uint8_t unused_0[7];
22042 /* hwrm_queue_cfg_output (size:128b/16B) */
22043 struct hwrm_queue_cfg_output {
22044 /* The specific error status for the command. */
22045 uint16_t error_code;
22046 /* The HWRM command request type. */
22048 /* The sequence ID from the original command. */
22050 /* The length of the response data in number of bytes. */
22052 uint8_t unused_0[7];
22054 * This field is used in Output records to indicate that the output
22055 * is completely written to RAM. This field should be read as '1'
22056 * to indicate that the output has been completely written.
22057 * When writing a command completion or response to an internal processor,
22058 * the order of writes has to be such that this field is written last.
22063 /*****************************
22064 * hwrm_queue_pfcenable_qcfg *
22065 *****************************/
22068 /* hwrm_queue_pfcenable_qcfg_input (size:192b/24B) */
22069 struct hwrm_queue_pfcenable_qcfg_input {
22070 /* The HWRM command request type. */
22073 * The completion ring to send the completion event on. This should
22074 * be the NQ ID returned from the `nq_alloc` HWRM command.
22076 uint16_t cmpl_ring;
22078 * The sequence ID is used by the driver for tracking multiple
22079 * commands. This ID is treated as opaque data by the firmware and
22080 * the value is returned in the `hwrm_resp_hdr` upon completion.
22084 * The target ID of the command:
22085 * * 0x0-0xFFF8 - The function ID
22086 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
22087 * * 0xFFFD - Reserved for user-space HWRM interface
22090 uint16_t target_id;
22092 * A physical address pointer pointing to a host buffer that the
22093 * command's response data will be written. This can be either a host
22094 * physical address (HPA) or a guest physical address (GPA) and must
22095 * point to a physically contiguous block of memory.
22097 uint64_t resp_addr;
22099 * Port ID of port for which the table is being configured.
22100 * The HWRM needs to check whether this function is allowed
22101 * to configure pri2cos mapping on this port.
22104 uint8_t unused_0[6];
22107 /* hwrm_queue_pfcenable_qcfg_output (size:128b/16B) */
22108 struct hwrm_queue_pfcenable_qcfg_output {
22109 /* The specific error status for the command. */
22110 uint16_t error_code;
22111 /* The HWRM command request type. */
22113 /* The sequence ID from the original command. */
22115 /* The length of the response data in number of bytes. */
22118 /* If set to 1, then PFC is enabled on PRI 0. */
22119 #define HWRM_QUEUE_PFCENABLE_QCFG_OUTPUT_FLAGS_PRI0_PFC_ENABLED \
22121 /* If set to 1, then PFC is enabled on PRI 1. */
22122 #define HWRM_QUEUE_PFCENABLE_QCFG_OUTPUT_FLAGS_PRI1_PFC_ENABLED \
22124 /* If set to 1, then PFC is enabled on PRI 2. */
22125 #define HWRM_QUEUE_PFCENABLE_QCFG_OUTPUT_FLAGS_PRI2_PFC_ENABLED \
22127 /* If set to 1, then PFC is enabled on PRI 3. */
22128 #define HWRM_QUEUE_PFCENABLE_QCFG_OUTPUT_FLAGS_PRI3_PFC_ENABLED \
22130 /* If set to 1, then PFC is enabled on PRI 4. */
22131 #define HWRM_QUEUE_PFCENABLE_QCFG_OUTPUT_FLAGS_PRI4_PFC_ENABLED \
22133 /* If set to 1, then PFC is enabled on PRI 5. */
22134 #define HWRM_QUEUE_PFCENABLE_QCFG_OUTPUT_FLAGS_PRI5_PFC_ENABLED \
22136 /* If set to 1, then PFC is enabled on PRI 6. */
22137 #define HWRM_QUEUE_PFCENABLE_QCFG_OUTPUT_FLAGS_PRI6_PFC_ENABLED \
22139 /* If set to 1, then PFC is enabled on PRI 7. */
22140 #define HWRM_QUEUE_PFCENABLE_QCFG_OUTPUT_FLAGS_PRI7_PFC_ENABLED \
22142 /* If set to 1, then PFC WatchDog is requested to be enabled on PRI0. */
22143 #define HWRM_QUEUE_PFCENABLE_QCFG_OUTPUT_FLAGS_PRI0_PFC_WATCHDOG_ENABLED \
22145 /* If set to 1, then PFC WatchDog is requested to be enabled on PRI1. */
22146 #define HWRM_QUEUE_PFCENABLE_QCFG_OUTPUT_FLAGS_PRI1_PFC_WATCHDOG_ENABLED \
22148 /* If set to 1, then PFC WatchDog is requested to be enabled on PRI2. */
22149 #define HWRM_QUEUE_PFCENABLE_QCFG_OUTPUT_FLAGS_PRI2_PFC_WATCHDOG_ENABLED \
22151 /* If set to 1, then PFC WatchDog is requested to be enabled on PRI3. */
22152 #define HWRM_QUEUE_PFCENABLE_QCFG_OUTPUT_FLAGS_PRI3_PFC_WATCHDOG_ENABLED \
22154 /* If set to 1, then PFC WatchDog is requested to be enabled on PRI4. */
22155 #define HWRM_QUEUE_PFCENABLE_QCFG_OUTPUT_FLAGS_PRI4_PFC_WATCHDOG_ENABLED \
22157 /* If set to 1, then PFC WatchDog is requested to be enabled on PRI5. */
22158 #define HWRM_QUEUE_PFCENABLE_QCFG_OUTPUT_FLAGS_PRI5_PFC_WATCHDOG_ENABLED \
22160 /* If set to 1, then PFC WatchDog is requested to be enabled on PRI6. */
22161 #define HWRM_QUEUE_PFCENABLE_QCFG_OUTPUT_FLAGS_PRI6_PFC_WATCHDOG_ENABLED \
22163 /* If set to 1, then PFC WatchDog is requested to be enabled on PRI7. */
22164 #define HWRM_QUEUE_PFCENABLE_QCFG_OUTPUT_FLAGS_PRI7_PFC_WATCHDOG_ENABLED \
22166 uint8_t unused_0[3];
22168 * This field is used in Output records to indicate that the output
22169 * is completely written to RAM. This field should be read as '1'
22170 * to indicate that the output has been completely written.
22171 * When writing a command completion or response to an internal processor,
22172 * the order of writes has to be such that this field is written last.
22177 /****************************
22178 * hwrm_queue_pfcenable_cfg *
22179 ****************************/
22182 /* hwrm_queue_pfcenable_cfg_input (size:192b/24B) */
22183 struct hwrm_queue_pfcenable_cfg_input {
22184 /* The HWRM command request type. */
22187 * The completion ring to send the completion event on. This should
22188 * be the NQ ID returned from the `nq_alloc` HWRM command.
22190 uint16_t cmpl_ring;
22192 * The sequence ID is used by the driver for tracking multiple
22193 * commands. This ID is treated as opaque data by the firmware and
22194 * the value is returned in the `hwrm_resp_hdr` upon completion.
22198 * The target ID of the command:
22199 * * 0x0-0xFFF8 - The function ID
22200 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
22201 * * 0xFFFD - Reserved for user-space HWRM interface
22204 uint16_t target_id;
22206 * A physical address pointer pointing to a host buffer that the
22207 * command's response data will be written. This can be either a host
22208 * physical address (HPA) or a guest physical address (GPA) and must
22209 * point to a physically contiguous block of memory.
22211 uint64_t resp_addr;
22213 /* If set to 1, then PFC is requested to be enabled on PRI 0. */
22214 #define HWRM_QUEUE_PFCENABLE_CFG_INPUT_FLAGS_PRI0_PFC_ENABLED \
22216 /* If set to 1, then PFC is requested to be enabled on PRI 1. */
22217 #define HWRM_QUEUE_PFCENABLE_CFG_INPUT_FLAGS_PRI1_PFC_ENABLED \
22219 /* If set to 1, then PFC is requested to be enabled on PRI 2. */
22220 #define HWRM_QUEUE_PFCENABLE_CFG_INPUT_FLAGS_PRI2_PFC_ENABLED \
22222 /* If set to 1, then PFC is requested to be enabled on PRI 3. */
22223 #define HWRM_QUEUE_PFCENABLE_CFG_INPUT_FLAGS_PRI3_PFC_ENABLED \
22225 /* If set to 1, then PFC is requested to be enabled on PRI 4. */
22226 #define HWRM_QUEUE_PFCENABLE_CFG_INPUT_FLAGS_PRI4_PFC_ENABLED \
22228 /* If set to 1, then PFC is requested to be enabled on PRI 5. */
22229 #define HWRM_QUEUE_PFCENABLE_CFG_INPUT_FLAGS_PRI5_PFC_ENABLED \
22231 /* If set to 1, then PFC is requested to be enabled on PRI 6. */
22232 #define HWRM_QUEUE_PFCENABLE_CFG_INPUT_FLAGS_PRI6_PFC_ENABLED \
22234 /* If set to 1, then PFC is requested to be enabled on PRI 7. */
22235 #define HWRM_QUEUE_PFCENABLE_CFG_INPUT_FLAGS_PRI7_PFC_ENABLED \
22237 /* If set to 1, then PFC WatchDog is requested to be enabled on PRI0. */
22238 #define HWRM_QUEUE_PFCENABLE_CFG_INPUT_FLAGS_PRI0_PFC_WATCHDOG_ENABLED \
22240 /* If set to 1, then PFC WatchDog is requested to be enabled on PRI1. */
22241 #define HWRM_QUEUE_PFCENABLE_CFG_INPUT_FLAGS_PRI1_PFC_WATCHDOG_ENABLED \
22243 /* If set to 1, then PFC WatchDog is requested to be enabled on PRI2. */
22244 #define HWRM_QUEUE_PFCENABLE_CFG_INPUT_FLAGS_PRI2_PFC_WATCHDOG_ENABLED \
22246 /* If set to 1, then PFC WatchDog is requested to be enabled on PRI3. */
22247 #define HWRM_QUEUE_PFCENABLE_CFG_INPUT_FLAGS_PRI3_PFC_WATCHDOG_ENABLED \
22249 /* If set to 1, then PFC WatchDog is requested to be enabled on PRI4. */
22250 #define HWRM_QUEUE_PFCENABLE_CFG_INPUT_FLAGS_PRI4_PFC_WATCHDOG_ENABLED \
22252 /* If set to 1, then PFC WatchDog is requested to be enabled on PRI5. */
22253 #define HWRM_QUEUE_PFCENABLE_CFG_INPUT_FLAGS_PRI5_PFC_WATCHDOG_ENABLED \
22255 /* If set to 1, then PFC WatchDog is requested to be enabled on PRI6. */
22256 #define HWRM_QUEUE_PFCENABLE_CFG_INPUT_FLAGS_PRI6_PFC_WATCHDOG_ENABLED \
22258 /* If set to 1, then PFC WatchDog is requested to be enabled on PRI7. */
22259 #define HWRM_QUEUE_PFCENABLE_CFG_INPUT_FLAGS_PRI7_PFC_WATCHDOG_ENABLED \
22262 * Port ID of port for which the table is being configured.
22263 * The HWRM needs to check whether this function is allowed
22264 * to configure pri2cos mapping on this port.
22267 uint8_t unused_0[2];
22270 /* hwrm_queue_pfcenable_cfg_output (size:128b/16B) */
22271 struct hwrm_queue_pfcenable_cfg_output {
22272 /* The specific error status for the command. */
22273 uint16_t error_code;
22274 /* The HWRM command request type. */
22276 /* The sequence ID from the original command. */
22278 /* The length of the response data in number of bytes. */
22280 uint8_t unused_0[7];
22282 * This field is used in Output records to indicate that the output
22283 * is completely written to RAM. This field should be read as '1'
22284 * to indicate that the output has been completely written.
22285 * When writing a command completion or response to an internal processor,
22286 * the order of writes has to be such that this field is written last.
22291 /***************************
22292 * hwrm_queue_pri2cos_qcfg *
22293 ***************************/
22296 /* hwrm_queue_pri2cos_qcfg_input (size:192b/24B) */
22297 struct hwrm_queue_pri2cos_qcfg_input {
22298 /* The HWRM command request type. */
22301 * The completion ring to send the completion event on. This should
22302 * be the NQ ID returned from the `nq_alloc` HWRM command.
22304 uint16_t cmpl_ring;
22306 * The sequence ID is used by the driver for tracking multiple
22307 * commands. This ID is treated as opaque data by the firmware and
22308 * the value is returned in the `hwrm_resp_hdr` upon completion.
22312 * The target ID of the command:
22313 * * 0x0-0xFFF8 - The function ID
22314 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
22315 * * 0xFFFD - Reserved for user-space HWRM interface
22318 uint16_t target_id;
22320 * A physical address pointer pointing to a host buffer that the
22321 * command's response data will be written. This can be either a host
22322 * physical address (HPA) or a guest physical address (GPA) and must
22323 * point to a physically contiguous block of memory.
22325 uint64_t resp_addr;
22328 * Enumeration denoting the RX, TX type of the resource.
22329 * This enumeration is used for resources that are similar for both
22330 * TX and RX paths of the chip.
22332 #define HWRM_QUEUE_PRI2COS_QCFG_INPUT_FLAGS_PATH UINT32_C(0x1)
22334 #define HWRM_QUEUE_PRI2COS_QCFG_INPUT_FLAGS_PATH_TX UINT32_C(0x0)
22336 #define HWRM_QUEUE_PRI2COS_QCFG_INPUT_FLAGS_PATH_RX UINT32_C(0x1)
22337 #define HWRM_QUEUE_PRI2COS_QCFG_INPUT_FLAGS_PATH_LAST \
22338 HWRM_QUEUE_PRI2COS_QCFG_INPUT_FLAGS_PATH_RX
22340 * When this bit is set to '0', the query is
22341 * for PRI from tunnel headers.
22342 * When this bit is set to '1', the query is
22343 * for PRI from inner packet headers.
22345 #define HWRM_QUEUE_PRI2COS_QCFG_INPUT_FLAGS_IVLAN UINT32_C(0x2)
22347 * Port ID of port for which the table is being configured.
22348 * The HWRM needs to check whether this function is allowed
22349 * to configure pri2cos mapping on this port.
22352 uint8_t unused_0[3];
22355 /* hwrm_queue_pri2cos_qcfg_output (size:192b/24B) */
22356 struct hwrm_queue_pri2cos_qcfg_output {
22357 /* The specific error status for the command. */
22358 uint16_t error_code;
22359 /* The HWRM command request type. */
22361 /* The sequence ID from the original command. */
22363 /* The length of the response data in number of bytes. */
22366 * CoS Queue assigned to priority 0. This value can only
22367 * be changed before traffic has started.
22368 * A value of 0xff indicates that no CoS queue is assigned to the
22369 * specified priority.
22371 uint8_t pri0_cos_queue_id;
22373 * CoS Queue assigned to priority 1. This value can only
22374 * be changed before traffic has started.
22375 * A value of 0xff indicates that no CoS queue is assigned to the
22376 * specified priority.
22378 uint8_t pri1_cos_queue_id;
22380 * CoS Queue assigned to priority 2. This value can only
22381 * be changed before traffic has started.
22382 * A value of 0xff indicates that no CoS queue is assigned to the
22383 * specified priority.
22385 uint8_t pri2_cos_queue_id;
22387 * CoS Queue assigned to priority 3. This value can only
22388 * be changed before traffic has started.
22389 * A value of 0xff indicates that no CoS queue is assigned to the
22390 * specified priority.
22392 uint8_t pri3_cos_queue_id;
22394 * CoS Queue assigned to priority 4. This value can only
22395 * be changed before traffic has started.
22396 * A value of 0xff indicates that no CoS queue is assigned to the
22397 * specified priority.
22399 uint8_t pri4_cos_queue_id;
22401 * CoS Queue assigned to priority 5. This value can only
22402 * be changed before traffic has started.
22403 * A value of 0xff indicates that no CoS queue is assigned to the
22404 * specified priority.
22406 uint8_t pri5_cos_queue_id;
22408 * CoS Queue assigned to priority 6. This value can only
22409 * be changed before traffic has started.
22410 * A value of 0xff indicates that no CoS queue is assigned to the
22411 * specified priority.
22413 uint8_t pri6_cos_queue_id;
22415 * CoS Queue assigned to priority 7. This value can only
22416 * be changed before traffic has started.
22417 * A value of 0xff indicates that no CoS queue is assigned to the
22418 * specified priority.
22420 uint8_t pri7_cos_queue_id;
22421 /* Information about queue configuration. */
22422 uint8_t queue_cfg_info;
22424 * If this flag is set to '1', then the PRI to CoS
22425 * configuration is asymmetric on TX and RX sides.
22426 * If this flag is set to '0', then PRI to CoS configuration
22427 * is symmetric on TX and RX sides.
22429 #define HWRM_QUEUE_PRI2COS_QCFG_OUTPUT_QUEUE_CFG_INFO_ASYM_CFG \
22431 uint8_t unused_0[6];
22433 * This field is used in Output records to indicate that the output
22434 * is completely written to RAM. This field should be read as '1'
22435 * to indicate that the output has been completely written.
22436 * When writing a command completion or response to an internal processor,
22437 * the order of writes has to be such that this field is written last.
22442 /**************************
22443 * hwrm_queue_pri2cos_cfg *
22444 **************************/
22447 /* hwrm_queue_pri2cos_cfg_input (size:320b/40B) */
22448 struct hwrm_queue_pri2cos_cfg_input {
22449 /* The HWRM command request type. */
22452 * The completion ring to send the completion event on. This should
22453 * be the NQ ID returned from the `nq_alloc` HWRM command.
22455 uint16_t cmpl_ring;
22457 * The sequence ID is used by the driver for tracking multiple
22458 * commands. This ID is treated as opaque data by the firmware and
22459 * the value is returned in the `hwrm_resp_hdr` upon completion.
22463 * The target ID of the command:
22464 * * 0x0-0xFFF8 - The function ID
22465 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
22466 * * 0xFFFD - Reserved for user-space HWRM interface
22469 uint16_t target_id;
22471 * A physical address pointer pointing to a host buffer that the
22472 * command's response data will be written. This can be either a host
22473 * physical address (HPA) or a guest physical address (GPA) and must
22474 * point to a physically contiguous block of memory.
22476 uint64_t resp_addr;
22479 * Enumeration denoting the RX, TX, or both directions applicable to the resource.
22480 * This enumeration is used for resources that are similar for both
22481 * TX and RX paths of the chip.
22483 #define HWRM_QUEUE_PRI2COS_CFG_INPUT_FLAGS_PATH_MASK UINT32_C(0x3)
22484 #define HWRM_QUEUE_PRI2COS_CFG_INPUT_FLAGS_PATH_SFT 0
22486 #define HWRM_QUEUE_PRI2COS_CFG_INPUT_FLAGS_PATH_TX UINT32_C(0x0)
22488 #define HWRM_QUEUE_PRI2COS_CFG_INPUT_FLAGS_PATH_RX UINT32_C(0x1)
22489 /* Bi-directional (Symmetrically applicable to TX and RX paths) */
22490 #define HWRM_QUEUE_PRI2COS_CFG_INPUT_FLAGS_PATH_BIDIR UINT32_C(0x2)
22491 #define HWRM_QUEUE_PRI2COS_CFG_INPUT_FLAGS_PATH_LAST \
22492 HWRM_QUEUE_PRI2COS_CFG_INPUT_FLAGS_PATH_BIDIR
22494 * When this bit is set to '0', the mapping is requested
22495 * for PRI from tunnel headers.
22496 * When this bit is set to '1', the mapping is requested
22497 * for PRI from inner packet headers.
22499 #define HWRM_QUEUE_PRI2COS_CFG_INPUT_FLAGS_IVLAN UINT32_C(0x4)
22502 * This bit must be '1' for the pri0_cos_queue_id field to be
22505 #define HWRM_QUEUE_PRI2COS_CFG_INPUT_ENABLES_PRI0_COS_QUEUE_ID \
22508 * This bit must be '1' for the pri1_cos_queue_id field to be
22511 #define HWRM_QUEUE_PRI2COS_CFG_INPUT_ENABLES_PRI1_COS_QUEUE_ID \
22514 * This bit must be '1' for the pri2_cos_queue_id field to be
22517 #define HWRM_QUEUE_PRI2COS_CFG_INPUT_ENABLES_PRI2_COS_QUEUE_ID \
22520 * This bit must be '1' for the pri3_cos_queue_id field to be
22523 #define HWRM_QUEUE_PRI2COS_CFG_INPUT_ENABLES_PRI3_COS_QUEUE_ID \
22526 * This bit must be '1' for the pri4_cos_queue_id field to be
22529 #define HWRM_QUEUE_PRI2COS_CFG_INPUT_ENABLES_PRI4_COS_QUEUE_ID \
22532 * This bit must be '1' for the pri5_cos_queue_id field to be
22535 #define HWRM_QUEUE_PRI2COS_CFG_INPUT_ENABLES_PRI5_COS_QUEUE_ID \
22538 * This bit must be '1' for the pri6_cos_queue_id field to be
22541 #define HWRM_QUEUE_PRI2COS_CFG_INPUT_ENABLES_PRI6_COS_QUEUE_ID \
22544 * This bit must be '1' for the pri7_cos_queue_id field to be
22547 #define HWRM_QUEUE_PRI2COS_CFG_INPUT_ENABLES_PRI7_COS_QUEUE_ID \
22550 * Port ID of port for which the table is being configured.
22551 * The HWRM needs to check whether this function is allowed
22552 * to configure pri2cos mapping on this port.
22556 * CoS Queue assigned to priority 0. This value can only
22557 * be changed before traffic has started.
22559 uint8_t pri0_cos_queue_id;
22561 * CoS Queue assigned to priority 1. This value can only
22562 * be changed before traffic has started.
22564 uint8_t pri1_cos_queue_id;
22566 * CoS Queue assigned to priority 2 This value can only
22567 * be changed before traffic has started.
22569 uint8_t pri2_cos_queue_id;
22571 * CoS Queue assigned to priority 3. This value can only
22572 * be changed before traffic has started.
22574 uint8_t pri3_cos_queue_id;
22576 * CoS Queue assigned to priority 4. This value can only
22577 * be changed before traffic has started.
22579 uint8_t pri4_cos_queue_id;
22581 * CoS Queue assigned to priority 5. This value can only
22582 * be changed before traffic has started.
22584 uint8_t pri5_cos_queue_id;
22586 * CoS Queue assigned to priority 6. This value can only
22587 * be changed before traffic has started.
22589 uint8_t pri6_cos_queue_id;
22591 * CoS Queue assigned to priority 7. This value can only
22592 * be changed before traffic has started.
22594 uint8_t pri7_cos_queue_id;
22595 uint8_t unused_0[7];
22598 /* hwrm_queue_pri2cos_cfg_output (size:128b/16B) */
22599 struct hwrm_queue_pri2cos_cfg_output {
22600 /* The specific error status for the command. */
22601 uint16_t error_code;
22602 /* The HWRM command request type. */
22604 /* The sequence ID from the original command. */
22606 /* The length of the response data in number of bytes. */
22608 uint8_t unused_0[7];
22610 * This field is used in Output records to indicate that the output
22611 * is completely written to RAM. This field should be read as '1'
22612 * to indicate that the output has been completely written.
22613 * When writing a command completion or response to an internal processor,
22614 * the order of writes has to be such that this field is written last.
22619 /**************************
22620 * hwrm_queue_cos2bw_qcfg *
22621 **************************/
22624 /* hwrm_queue_cos2bw_qcfg_input (size:192b/24B) */
22625 struct hwrm_queue_cos2bw_qcfg_input {
22626 /* The HWRM command request type. */
22629 * The completion ring to send the completion event on. This should
22630 * be the NQ ID returned from the `nq_alloc` HWRM command.
22632 uint16_t cmpl_ring;
22634 * The sequence ID is used by the driver for tracking multiple
22635 * commands. This ID is treated as opaque data by the firmware and
22636 * the value is returned in the `hwrm_resp_hdr` upon completion.
22640 * The target ID of the command:
22641 * * 0x0-0xFFF8 - The function ID
22642 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
22643 * * 0xFFFD - Reserved for user-space HWRM interface
22646 uint16_t target_id;
22648 * A physical address pointer pointing to a host buffer that the
22649 * command's response data will be written. This can be either a host
22650 * physical address (HPA) or a guest physical address (GPA) and must
22651 * point to a physically contiguous block of memory.
22653 uint64_t resp_addr;
22655 * Port ID of port for which the table is being configured.
22656 * The HWRM needs to check whether this function is allowed
22657 * to configure TC BW assignment on this port.
22660 uint8_t unused_0[6];
22663 /* hwrm_queue_cos2bw_qcfg_output (size:896b/112B) */
22664 struct hwrm_queue_cos2bw_qcfg_output {
22665 /* The specific error status for the command. */
22666 uint16_t error_code;
22667 /* The HWRM command request type. */
22669 /* The sequence ID from the original command. */
22671 /* The length of the response data in number of bytes. */
22673 /* ID of CoS Queue 0. */
22678 * Minimum BW allocated to CoS Queue.
22679 * The HWRM will translate this value into byte counter and
22680 * time interval used for this COS inside the device.
22682 uint32_t queue_id0_min_bw;
22683 /* The bandwidth value. */
22684 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MIN_BW_BW_VALUE_MASK \
22685 UINT32_C(0xfffffff)
22686 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MIN_BW_BW_VALUE_SFT \
22688 /* The granularity of the value (bits or bytes). */
22689 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MIN_BW_SCALE \
22690 UINT32_C(0x10000000)
22691 /* Value is in bits. */
22692 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MIN_BW_SCALE_BITS \
22693 (UINT32_C(0x0) << 28)
22694 /* Value is in bytes. */
22695 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MIN_BW_SCALE_BYTES \
22696 (UINT32_C(0x1) << 28)
22697 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MIN_BW_SCALE_LAST \
22698 HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MIN_BW_SCALE_BYTES
22699 /* bw_value_unit is 3 b */
22700 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_MASK \
22701 UINT32_C(0xe0000000)
22702 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_SFT \
22704 /* Value is in Mb or MB (base 10). */
22705 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_MEGA \
22706 (UINT32_C(0x0) << 29)
22707 /* Value is in Kb or KB (base 10). */
22708 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_KILO \
22709 (UINT32_C(0x2) << 29)
22710 /* Value is in bits or bytes. */
22711 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_BASE \
22712 (UINT32_C(0x4) << 29)
22713 /* Value is in Gb or GB (base 10). */
22714 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_GIGA \
22715 (UINT32_C(0x6) << 29)
22716 /* Value is in 1/100th of a percentage of total bandwidth. */
22717 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 \
22718 (UINT32_C(0x1) << 29)
22720 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_INVALID \
22721 (UINT32_C(0x7) << 29)
22722 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_LAST \
22723 HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_INVALID
22725 * Maximum BW allocated to CoS Queue.
22726 * The HWRM will translate this value into byte counter and
22727 * time interval used for this COS inside the device.
22729 uint32_t queue_id0_max_bw;
22730 /* The bandwidth value. */
22731 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MAX_BW_BW_VALUE_MASK \
22732 UINT32_C(0xfffffff)
22733 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MAX_BW_BW_VALUE_SFT \
22735 /* The granularity of the value (bits or bytes). */
22736 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MAX_BW_SCALE \
22737 UINT32_C(0x10000000)
22738 /* Value is in bits. */
22739 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MAX_BW_SCALE_BITS \
22740 (UINT32_C(0x0) << 28)
22741 /* Value is in bytes. */
22742 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MAX_BW_SCALE_BYTES \
22743 (UINT32_C(0x1) << 28)
22744 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MAX_BW_SCALE_LAST \
22745 HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MAX_BW_SCALE_BYTES
22746 /* bw_value_unit is 3 b */
22747 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_MASK \
22748 UINT32_C(0xe0000000)
22749 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_SFT \
22751 /* Value is in Mb or MB (base 10). */
22752 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_MEGA \
22753 (UINT32_C(0x0) << 29)
22754 /* Value is in Kb or KB (base 10). */
22755 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_KILO \
22756 (UINT32_C(0x2) << 29)
22757 /* Value is in bits or bytes. */
22758 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_BASE \
22759 (UINT32_C(0x4) << 29)
22760 /* Value is in Gb or GB (base 10). */
22761 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_GIGA \
22762 (UINT32_C(0x6) << 29)
22763 /* Value is in 1/100th of a percentage of total bandwidth. */
22764 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 \
22765 (UINT32_C(0x1) << 29)
22767 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_INVALID \
22768 (UINT32_C(0x7) << 29)
22769 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_LAST \
22770 HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_INVALID
22771 /* Transmission Selection Algorithm (TSA) for CoS Queue. */
22772 uint8_t queue_id0_tsa_assign;
22773 /* Strict Priority */
22774 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_TSA_ASSIGN_SP \
22776 /* Enhanced Transmission Selection */
22777 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_TSA_ASSIGN_ETS \
22780 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_TSA_ASSIGN_RESERVED_FIRST \
22783 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_TSA_ASSIGN_RESERVED_LAST \
22786 * Priority level for strict priority. Valid only when the
22787 * tsa_assign is 0 - Strict Priority (SP)
22788 * 0..7 - Valid values.
22789 * 8..255 - Reserved.
22791 uint8_t queue_id0_pri_lvl;
22793 * Weight used to allocate remaining BW for this COS after
22794 * servicing guaranteed bandwidths for all COS.
22796 uint8_t queue_id0_bw_weight;
22797 /* ID of CoS Queue 1. */
22800 * Minimum BW allocated to CoS Queue.
22801 * The HWRM will translate this value into byte counter and
22802 * time interval used for this COS inside the device.
22804 uint32_t queue_id1_min_bw;
22805 /* The bandwidth value. */
22806 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MIN_BW_BW_VALUE_MASK \
22807 UINT32_C(0xfffffff)
22808 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MIN_BW_BW_VALUE_SFT \
22810 /* The granularity of the value (bits or bytes). */
22811 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MIN_BW_SCALE \
22812 UINT32_C(0x10000000)
22813 /* Value is in bits. */
22814 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MIN_BW_SCALE_BITS \
22815 (UINT32_C(0x0) << 28)
22816 /* Value is in bytes. */
22817 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MIN_BW_SCALE_BYTES \
22818 (UINT32_C(0x1) << 28)
22819 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MIN_BW_SCALE_LAST \
22820 HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MIN_BW_SCALE_BYTES
22821 /* bw_value_unit is 3 b */
22822 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_MASK \
22823 UINT32_C(0xe0000000)
22824 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_SFT \
22826 /* Value is in Mb or MB (base 10). */
22827 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_MEGA \
22828 (UINT32_C(0x0) << 29)
22829 /* Value is in Kb or KB (base 10). */
22830 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_KILO \
22831 (UINT32_C(0x2) << 29)
22832 /* Value is in bits or bytes. */
22833 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_BASE \
22834 (UINT32_C(0x4) << 29)
22835 /* Value is in Gb or GB (base 10). */
22836 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_GIGA \
22837 (UINT32_C(0x6) << 29)
22838 /* Value is in 1/100th of a percentage of total bandwidth. */
22839 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 \
22840 (UINT32_C(0x1) << 29)
22842 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_INVALID \
22843 (UINT32_C(0x7) << 29)
22844 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_LAST \
22845 HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_INVALID
22847 * Maximum BW allocated to CoS queue.
22848 * The HWRM will translate this value into byte counter and
22849 * time interval used for this COS inside the device.
22851 uint32_t queue_id1_max_bw;
22852 /* The bandwidth value. */
22853 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MAX_BW_BW_VALUE_MASK \
22854 UINT32_C(0xfffffff)
22855 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MAX_BW_BW_VALUE_SFT \
22857 /* The granularity of the value (bits or bytes). */
22858 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MAX_BW_SCALE \
22859 UINT32_C(0x10000000)
22860 /* Value is in bits. */
22861 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MAX_BW_SCALE_BITS \
22862 (UINT32_C(0x0) << 28)
22863 /* Value is in bytes. */
22864 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MAX_BW_SCALE_BYTES \
22865 (UINT32_C(0x1) << 28)
22866 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MAX_BW_SCALE_LAST \
22867 HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MAX_BW_SCALE_BYTES
22868 /* bw_value_unit is 3 b */
22869 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_MASK \
22870 UINT32_C(0xe0000000)
22871 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_SFT \
22873 /* Value is in Mb or MB (base 10). */
22874 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_MEGA \
22875 (UINT32_C(0x0) << 29)
22876 /* Value is in Kb or KB (base 10). */
22877 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_KILO \
22878 (UINT32_C(0x2) << 29)
22879 /* Value is in bits or bytes. */
22880 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_BASE \
22881 (UINT32_C(0x4) << 29)
22882 /* Value is in Gb or GB (base 10). */
22883 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_GIGA \
22884 (UINT32_C(0x6) << 29)
22885 /* Value is in 1/100th of a percentage of total bandwidth. */
22886 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 \
22887 (UINT32_C(0x1) << 29)
22889 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_INVALID \
22890 (UINT32_C(0x7) << 29)
22891 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_LAST \
22892 HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_INVALID
22893 /* Transmission Selection Algorithm (TSA) for CoS Queue. */
22894 uint8_t queue_id1_tsa_assign;
22895 /* Strict Priority */
22896 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_TSA_ASSIGN_SP \
22898 /* Enhanced Transmission Selection */
22899 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_TSA_ASSIGN_ETS \
22902 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_TSA_ASSIGN_RESERVED_FIRST \
22905 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_TSA_ASSIGN_RESERVED_LAST \
22908 * Priority level for strict priority. Valid only when the
22909 * tsa_assign is 0 - Strict Priority (SP)
22910 * 0..7 - Valid values.
22911 * 8..255 - Reserved.
22913 uint8_t queue_id1_pri_lvl;
22915 * Weight used to allocate remaining BW for this COS after
22916 * servicing guaranteed bandwidths for all COS.
22918 uint8_t queue_id1_bw_weight;
22919 /* ID of CoS Queue 2. */
22922 * Minimum BW allocated to CoS Queue.
22923 * The HWRM will translate this value into byte counter and
22924 * time interval used for this COS inside the device.
22926 uint32_t queue_id2_min_bw;
22927 /* The bandwidth value. */
22928 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MIN_BW_BW_VALUE_MASK \
22929 UINT32_C(0xfffffff)
22930 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MIN_BW_BW_VALUE_SFT \
22932 /* The granularity of the value (bits or bytes). */
22933 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MIN_BW_SCALE \
22934 UINT32_C(0x10000000)
22935 /* Value is in bits. */
22936 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MIN_BW_SCALE_BITS \
22937 (UINT32_C(0x0) << 28)
22938 /* Value is in bytes. */
22939 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MIN_BW_SCALE_BYTES \
22940 (UINT32_C(0x1) << 28)
22941 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MIN_BW_SCALE_LAST \
22942 HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MIN_BW_SCALE_BYTES
22943 /* bw_value_unit is 3 b */
22944 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_MASK \
22945 UINT32_C(0xe0000000)
22946 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_SFT \
22948 /* Value is in Mb or MB (base 10). */
22949 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_MEGA \
22950 (UINT32_C(0x0) << 29)
22951 /* Value is in Kb or KB (base 10). */
22952 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_KILO \
22953 (UINT32_C(0x2) << 29)
22954 /* Value is in bits or bytes. */
22955 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_BASE \
22956 (UINT32_C(0x4) << 29)
22957 /* Value is in Gb or GB (base 10). */
22958 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_GIGA \
22959 (UINT32_C(0x6) << 29)
22960 /* Value is in 1/100th of a percentage of total bandwidth. */
22961 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 \
22962 (UINT32_C(0x1) << 29)
22964 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_INVALID \
22965 (UINT32_C(0x7) << 29)
22966 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_LAST \
22967 HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_INVALID
22969 * Maximum BW allocated to CoS queue.
22970 * The HWRM will translate this value into byte counter and
22971 * time interval used for this COS inside the device.
22973 uint32_t queue_id2_max_bw;
22974 /* The bandwidth value. */
22975 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MAX_BW_BW_VALUE_MASK \
22976 UINT32_C(0xfffffff)
22977 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MAX_BW_BW_VALUE_SFT \
22979 /* The granularity of the value (bits or bytes). */
22980 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MAX_BW_SCALE \
22981 UINT32_C(0x10000000)
22982 /* Value is in bits. */
22983 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MAX_BW_SCALE_BITS \
22984 (UINT32_C(0x0) << 28)
22985 /* Value is in bytes. */
22986 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MAX_BW_SCALE_BYTES \
22987 (UINT32_C(0x1) << 28)
22988 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MAX_BW_SCALE_LAST \
22989 HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MAX_BW_SCALE_BYTES
22990 /* bw_value_unit is 3 b */
22991 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_MASK \
22992 UINT32_C(0xe0000000)
22993 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_SFT \
22995 /* Value is in Mb or MB (base 10). */
22996 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_MEGA \
22997 (UINT32_C(0x0) << 29)
22998 /* Value is in Kb or KB (base 10). */
22999 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_KILO \
23000 (UINT32_C(0x2) << 29)
23001 /* Value is in bits or bytes. */
23002 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_BASE \
23003 (UINT32_C(0x4) << 29)
23004 /* Value is in Gb or GB (base 10). */
23005 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_GIGA \
23006 (UINT32_C(0x6) << 29)
23007 /* Value is in 1/100th of a percentage of total bandwidth. */
23008 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 \
23009 (UINT32_C(0x1) << 29)
23011 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_INVALID \
23012 (UINT32_C(0x7) << 29)
23013 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_LAST \
23014 HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_INVALID
23015 /* Transmission Selection Algorithm (TSA) for CoS Queue. */
23016 uint8_t queue_id2_tsa_assign;
23017 /* Strict Priority */
23018 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_TSA_ASSIGN_SP \
23020 /* Enhanced Transmission Selection */
23021 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_TSA_ASSIGN_ETS \
23024 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_TSA_ASSIGN_RESERVED_FIRST \
23027 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_TSA_ASSIGN_RESERVED_LAST \
23030 * Priority level for strict priority. Valid only when the
23031 * tsa_assign is 0 - Strict Priority (SP)
23032 * 0..7 - Valid values.
23033 * 8..255 - Reserved.
23035 uint8_t queue_id2_pri_lvl;
23037 * Weight used to allocate remaining BW for this COS after
23038 * servicing guaranteed bandwidths for all COS.
23040 uint8_t queue_id2_bw_weight;
23041 /* ID of CoS Queue 3. */
23044 * Minimum BW allocated to CoS Queue.
23045 * The HWRM will translate this value into byte counter and
23046 * time interval used for this COS inside the device.
23048 uint32_t queue_id3_min_bw;
23049 /* The bandwidth value. */
23050 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MIN_BW_BW_VALUE_MASK \
23051 UINT32_C(0xfffffff)
23052 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MIN_BW_BW_VALUE_SFT \
23054 /* The granularity of the value (bits or bytes). */
23055 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MIN_BW_SCALE \
23056 UINT32_C(0x10000000)
23057 /* Value is in bits. */
23058 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MIN_BW_SCALE_BITS \
23059 (UINT32_C(0x0) << 28)
23060 /* Value is in bytes. */
23061 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MIN_BW_SCALE_BYTES \
23062 (UINT32_C(0x1) << 28)
23063 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MIN_BW_SCALE_LAST \
23064 HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MIN_BW_SCALE_BYTES
23065 /* bw_value_unit is 3 b */
23066 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_MASK \
23067 UINT32_C(0xe0000000)
23068 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_SFT \
23070 /* Value is in Mb or MB (base 10). */
23071 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_MEGA \
23072 (UINT32_C(0x0) << 29)
23073 /* Value is in Kb or KB (base 10). */
23074 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_KILO \
23075 (UINT32_C(0x2) << 29)
23076 /* Value is in bits or bytes. */
23077 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_BASE \
23078 (UINT32_C(0x4) << 29)
23079 /* Value is in Gb or GB (base 10). */
23080 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_GIGA \
23081 (UINT32_C(0x6) << 29)
23082 /* Value is in 1/100th of a percentage of total bandwidth. */
23083 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 \
23084 (UINT32_C(0x1) << 29)
23086 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_INVALID \
23087 (UINT32_C(0x7) << 29)
23088 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_LAST \
23089 HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_INVALID
23091 * Maximum BW allocated to CoS queue.
23092 * The HWRM will translate this value into byte counter and
23093 * time interval used for this COS inside the device.
23095 uint32_t queue_id3_max_bw;
23096 /* The bandwidth value. */
23097 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MAX_BW_BW_VALUE_MASK \
23098 UINT32_C(0xfffffff)
23099 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MAX_BW_BW_VALUE_SFT \
23101 /* The granularity of the value (bits or bytes). */
23102 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MAX_BW_SCALE \
23103 UINT32_C(0x10000000)
23104 /* Value is in bits. */
23105 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MAX_BW_SCALE_BITS \
23106 (UINT32_C(0x0) << 28)
23107 /* Value is in bytes. */
23108 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MAX_BW_SCALE_BYTES \
23109 (UINT32_C(0x1) << 28)
23110 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MAX_BW_SCALE_LAST \
23111 HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MAX_BW_SCALE_BYTES
23112 /* bw_value_unit is 3 b */
23113 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_MASK \
23114 UINT32_C(0xe0000000)
23115 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_SFT \
23117 /* Value is in Mb or MB (base 10). */
23118 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_MEGA \
23119 (UINT32_C(0x0) << 29)
23120 /* Value is in Kb or KB (base 10). */
23121 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_KILO \
23122 (UINT32_C(0x2) << 29)
23123 /* Value is in bits or bytes. */
23124 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_BASE \
23125 (UINT32_C(0x4) << 29)
23126 /* Value is in Gb or GB (base 10). */
23127 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_GIGA \
23128 (UINT32_C(0x6) << 29)
23129 /* Value is in 1/100th of a percentage of total bandwidth. */
23130 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 \
23131 (UINT32_C(0x1) << 29)
23133 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_INVALID \
23134 (UINT32_C(0x7) << 29)
23135 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_LAST \
23136 HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_INVALID
23137 /* Transmission Selection Algorithm (TSA) for CoS Queue. */
23138 uint8_t queue_id3_tsa_assign;
23139 /* Strict Priority */
23140 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_TSA_ASSIGN_SP \
23142 /* Enhanced Transmission Selection */
23143 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_TSA_ASSIGN_ETS \
23146 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_TSA_ASSIGN_RESERVED_FIRST \
23149 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_TSA_ASSIGN_RESERVED_LAST \
23152 * Priority level for strict priority. Valid only when the
23153 * tsa_assign is 0 - Strict Priority (SP)
23154 * 0..7 - Valid values.
23155 * 8..255 - Reserved.
23157 uint8_t queue_id3_pri_lvl;
23159 * Weight used to allocate remaining BW for this COS after
23160 * servicing guaranteed bandwidths for all COS.
23162 uint8_t queue_id3_bw_weight;
23163 /* ID of CoS Queue 4. */
23166 * Minimum BW allocated to CoS Queue.
23167 * The HWRM will translate this value into byte counter and
23168 * time interval used for this COS inside the device.
23170 uint32_t queue_id4_min_bw;
23171 /* The bandwidth value. */
23172 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MIN_BW_BW_VALUE_MASK \
23173 UINT32_C(0xfffffff)
23174 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MIN_BW_BW_VALUE_SFT \
23176 /* The granularity of the value (bits or bytes). */
23177 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MIN_BW_SCALE \
23178 UINT32_C(0x10000000)
23179 /* Value is in bits. */
23180 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MIN_BW_SCALE_BITS \
23181 (UINT32_C(0x0) << 28)
23182 /* Value is in bytes. */
23183 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MIN_BW_SCALE_BYTES \
23184 (UINT32_C(0x1) << 28)
23185 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MIN_BW_SCALE_LAST \
23186 HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MIN_BW_SCALE_BYTES
23187 /* bw_value_unit is 3 b */
23188 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_MASK \
23189 UINT32_C(0xe0000000)
23190 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_SFT \
23192 /* Value is in Mb or MB (base 10). */
23193 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_MEGA \
23194 (UINT32_C(0x0) << 29)
23195 /* Value is in Kb or KB (base 10). */
23196 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_KILO \
23197 (UINT32_C(0x2) << 29)
23198 /* Value is in bits or bytes. */
23199 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_BASE \
23200 (UINT32_C(0x4) << 29)
23201 /* Value is in Gb or GB (base 10). */
23202 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_GIGA \
23203 (UINT32_C(0x6) << 29)
23204 /* Value is in 1/100th of a percentage of total bandwidth. */
23205 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 \
23206 (UINT32_C(0x1) << 29)
23208 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_INVALID \
23209 (UINT32_C(0x7) << 29)
23210 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_LAST \
23211 HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_INVALID
23213 * Maximum BW allocated to CoS queue.
23214 * The HWRM will translate this value into byte counter and
23215 * time interval used for this COS inside the device.
23217 uint32_t queue_id4_max_bw;
23218 /* The bandwidth value. */
23219 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MAX_BW_BW_VALUE_MASK \
23220 UINT32_C(0xfffffff)
23221 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MAX_BW_BW_VALUE_SFT \
23223 /* The granularity of the value (bits or bytes). */
23224 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MAX_BW_SCALE \
23225 UINT32_C(0x10000000)
23226 /* Value is in bits. */
23227 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MAX_BW_SCALE_BITS \
23228 (UINT32_C(0x0) << 28)
23229 /* Value is in bytes. */
23230 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MAX_BW_SCALE_BYTES \
23231 (UINT32_C(0x1) << 28)
23232 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MAX_BW_SCALE_LAST \
23233 HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MAX_BW_SCALE_BYTES
23234 /* bw_value_unit is 3 b */
23235 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_MASK \
23236 UINT32_C(0xe0000000)
23237 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_SFT \
23239 /* Value is in Mb or MB (base 10). */
23240 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_MEGA \
23241 (UINT32_C(0x0) << 29)
23242 /* Value is in Kb or KB (base 10). */
23243 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_KILO \
23244 (UINT32_C(0x2) << 29)
23245 /* Value is in bits or bytes. */
23246 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_BASE \
23247 (UINT32_C(0x4) << 29)
23248 /* Value is in Gb or GB (base 10). */
23249 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_GIGA \
23250 (UINT32_C(0x6) << 29)
23251 /* Value is in 1/100th of a percentage of total bandwidth. */
23252 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 \
23253 (UINT32_C(0x1) << 29)
23255 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_INVALID \
23256 (UINT32_C(0x7) << 29)
23257 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_LAST \
23258 HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_INVALID
23259 /* Transmission Selection Algorithm (TSA) for CoS Queue. */
23260 uint8_t queue_id4_tsa_assign;
23261 /* Strict Priority */
23262 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_TSA_ASSIGN_SP \
23264 /* Enhanced Transmission Selection */
23265 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_TSA_ASSIGN_ETS \
23268 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_TSA_ASSIGN_RESERVED_FIRST \
23271 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_TSA_ASSIGN_RESERVED_LAST \
23274 * Priority level for strict priority. Valid only when the
23275 * tsa_assign is 0 - Strict Priority (SP)
23276 * 0..7 - Valid values.
23277 * 8..255 - Reserved.
23279 uint8_t queue_id4_pri_lvl;
23281 * Weight used to allocate remaining BW for this COS after
23282 * servicing guaranteed bandwidths for all COS.
23284 uint8_t queue_id4_bw_weight;
23285 /* ID of CoS Queue 5. */
23288 * Minimum BW allocated to CoS Queue.
23289 * The HWRM will translate this value into byte counter and
23290 * time interval used for this COS inside the device.
23292 uint32_t queue_id5_min_bw;
23293 /* The bandwidth value. */
23294 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MIN_BW_BW_VALUE_MASK \
23295 UINT32_C(0xfffffff)
23296 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MIN_BW_BW_VALUE_SFT \
23298 /* The granularity of the value (bits or bytes). */
23299 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MIN_BW_SCALE \
23300 UINT32_C(0x10000000)
23301 /* Value is in bits. */
23302 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MIN_BW_SCALE_BITS \
23303 (UINT32_C(0x0) << 28)
23304 /* Value is in bytes. */
23305 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MIN_BW_SCALE_BYTES \
23306 (UINT32_C(0x1) << 28)
23307 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MIN_BW_SCALE_LAST \
23308 HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MIN_BW_SCALE_BYTES
23309 /* bw_value_unit is 3 b */
23310 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_MASK \
23311 UINT32_C(0xe0000000)
23312 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_SFT \
23314 /* Value is in Mb or MB (base 10). */
23315 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_MEGA \
23316 (UINT32_C(0x0) << 29)
23317 /* Value is in Kb or KB (base 10). */
23318 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_KILO \
23319 (UINT32_C(0x2) << 29)
23320 /* Value is in bits or bytes. */
23321 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_BASE \
23322 (UINT32_C(0x4) << 29)
23323 /* Value is in Gb or GB (base 10). */
23324 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_GIGA \
23325 (UINT32_C(0x6) << 29)
23326 /* Value is in 1/100th of a percentage of total bandwidth. */
23327 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 \
23328 (UINT32_C(0x1) << 29)
23330 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_INVALID \
23331 (UINT32_C(0x7) << 29)
23332 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_LAST \
23333 HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_INVALID
23335 * Maximum BW allocated to CoS queue.
23336 * The HWRM will translate this value into byte counter and
23337 * time interval used for this COS inside the device.
23339 uint32_t queue_id5_max_bw;
23340 /* The bandwidth value. */
23341 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MAX_BW_BW_VALUE_MASK \
23342 UINT32_C(0xfffffff)
23343 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MAX_BW_BW_VALUE_SFT \
23345 /* The granularity of the value (bits or bytes). */
23346 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MAX_BW_SCALE \
23347 UINT32_C(0x10000000)
23348 /* Value is in bits. */
23349 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MAX_BW_SCALE_BITS \
23350 (UINT32_C(0x0) << 28)
23351 /* Value is in bytes. */
23352 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MAX_BW_SCALE_BYTES \
23353 (UINT32_C(0x1) << 28)
23354 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MAX_BW_SCALE_LAST \
23355 HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MAX_BW_SCALE_BYTES
23356 /* bw_value_unit is 3 b */
23357 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_MASK \
23358 UINT32_C(0xe0000000)
23359 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_SFT \
23361 /* Value is in Mb or MB (base 10). */
23362 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_MEGA \
23363 (UINT32_C(0x0) << 29)
23364 /* Value is in Kb or KB (base 10). */
23365 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_KILO \
23366 (UINT32_C(0x2) << 29)
23367 /* Value is in bits or bytes. */
23368 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_BASE \
23369 (UINT32_C(0x4) << 29)
23370 /* Value is in Gb or GB (base 10). */
23371 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_GIGA \
23372 (UINT32_C(0x6) << 29)
23373 /* Value is in 1/100th of a percentage of total bandwidth. */
23374 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 \
23375 (UINT32_C(0x1) << 29)
23377 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_INVALID \
23378 (UINT32_C(0x7) << 29)
23379 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_LAST \
23380 HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_INVALID
23381 /* Transmission Selection Algorithm (TSA) for CoS Queue. */
23382 uint8_t queue_id5_tsa_assign;
23383 /* Strict Priority */
23384 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_TSA_ASSIGN_SP \
23386 /* Enhanced Transmission Selection */
23387 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_TSA_ASSIGN_ETS \
23390 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_TSA_ASSIGN_RESERVED_FIRST \
23393 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_TSA_ASSIGN_RESERVED_LAST \
23396 * Priority level for strict priority. Valid only when the
23397 * tsa_assign is 0 - Strict Priority (SP)
23398 * 0..7 - Valid values.
23399 * 8..255 - Reserved.
23401 uint8_t queue_id5_pri_lvl;
23403 * Weight used to allocate remaining BW for this COS after
23404 * servicing guaranteed bandwidths for all COS.
23406 uint8_t queue_id5_bw_weight;
23407 /* ID of CoS Queue 6. */
23410 * Minimum BW allocated to CoS Queue.
23411 * The HWRM will translate this value into byte counter and
23412 * time interval used for this COS inside the device.
23414 uint32_t queue_id6_min_bw;
23415 /* The bandwidth value. */
23416 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MIN_BW_BW_VALUE_MASK \
23417 UINT32_C(0xfffffff)
23418 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MIN_BW_BW_VALUE_SFT \
23420 /* The granularity of the value (bits or bytes). */
23421 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MIN_BW_SCALE \
23422 UINT32_C(0x10000000)
23423 /* Value is in bits. */
23424 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MIN_BW_SCALE_BITS \
23425 (UINT32_C(0x0) << 28)
23426 /* Value is in bytes. */
23427 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MIN_BW_SCALE_BYTES \
23428 (UINT32_C(0x1) << 28)
23429 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MIN_BW_SCALE_LAST \
23430 HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MIN_BW_SCALE_BYTES
23431 /* bw_value_unit is 3 b */
23432 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_MASK \
23433 UINT32_C(0xe0000000)
23434 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_SFT \
23436 /* Value is in Mb or MB (base 10). */
23437 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_MEGA \
23438 (UINT32_C(0x0) << 29)
23439 /* Value is in Kb or KB (base 10). */
23440 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_KILO \
23441 (UINT32_C(0x2) << 29)
23442 /* Value is in bits or bytes. */
23443 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_BASE \
23444 (UINT32_C(0x4) << 29)
23445 /* Value is in Gb or GB (base 10). */
23446 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_GIGA \
23447 (UINT32_C(0x6) << 29)
23448 /* Value is in 1/100th of a percentage of total bandwidth. */
23449 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 \
23450 (UINT32_C(0x1) << 29)
23452 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_INVALID \
23453 (UINT32_C(0x7) << 29)
23454 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_LAST \
23455 HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_INVALID
23457 * Maximum BW allocated to CoS queue.
23458 * The HWRM will translate this value into byte counter and
23459 * time interval used for this COS inside the device.
23461 uint32_t queue_id6_max_bw;
23462 /* The bandwidth value. */
23463 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MAX_BW_BW_VALUE_MASK \
23464 UINT32_C(0xfffffff)
23465 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MAX_BW_BW_VALUE_SFT \
23467 /* The granularity of the value (bits or bytes). */
23468 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MAX_BW_SCALE \
23469 UINT32_C(0x10000000)
23470 /* Value is in bits. */
23471 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MAX_BW_SCALE_BITS \
23472 (UINT32_C(0x0) << 28)
23473 /* Value is in bytes. */
23474 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MAX_BW_SCALE_BYTES \
23475 (UINT32_C(0x1) << 28)
23476 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MAX_BW_SCALE_LAST \
23477 HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MAX_BW_SCALE_BYTES
23478 /* bw_value_unit is 3 b */
23479 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_MASK \
23480 UINT32_C(0xe0000000)
23481 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_SFT \
23483 /* Value is in Mb or MB (base 10). */
23484 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_MEGA \
23485 (UINT32_C(0x0) << 29)
23486 /* Value is in Kb or KB (base 10). */
23487 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_KILO \
23488 (UINT32_C(0x2) << 29)
23489 /* Value is in bits or bytes. */
23490 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_BASE \
23491 (UINT32_C(0x4) << 29)
23492 /* Value is in Gb or GB (base 10). */
23493 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_GIGA \
23494 (UINT32_C(0x6) << 29)
23495 /* Value is in 1/100th of a percentage of total bandwidth. */
23496 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 \
23497 (UINT32_C(0x1) << 29)
23499 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_INVALID \
23500 (UINT32_C(0x7) << 29)
23501 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_LAST \
23502 HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_INVALID
23503 /* Transmission Selection Algorithm (TSA) for CoS Queue. */
23504 uint8_t queue_id6_tsa_assign;
23505 /* Strict Priority */
23506 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_TSA_ASSIGN_SP \
23508 /* Enhanced Transmission Selection */
23509 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_TSA_ASSIGN_ETS \
23512 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_TSA_ASSIGN_RESERVED_FIRST \
23515 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_TSA_ASSIGN_RESERVED_LAST \
23518 * Priority level for strict priority. Valid only when the
23519 * tsa_assign is 0 - Strict Priority (SP)
23520 * 0..7 - Valid values.
23521 * 8..255 - Reserved.
23523 uint8_t queue_id6_pri_lvl;
23525 * Weight used to allocate remaining BW for this COS after
23526 * servicing guaranteed bandwidths for all COS.
23528 uint8_t queue_id6_bw_weight;
23529 /* ID of CoS Queue 7. */
23532 * Minimum BW allocated to CoS Queue.
23533 * The HWRM will translate this value into byte counter and
23534 * time interval used for this COS inside the device.
23536 uint32_t queue_id7_min_bw;
23537 /* The bandwidth value. */
23538 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MIN_BW_BW_VALUE_MASK \
23539 UINT32_C(0xfffffff)
23540 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MIN_BW_BW_VALUE_SFT \
23542 /* The granularity of the value (bits or bytes). */
23543 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MIN_BW_SCALE \
23544 UINT32_C(0x10000000)
23545 /* Value is in bits. */
23546 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MIN_BW_SCALE_BITS \
23547 (UINT32_C(0x0) << 28)
23548 /* Value is in bytes. */
23549 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MIN_BW_SCALE_BYTES \
23550 (UINT32_C(0x1) << 28)
23551 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MIN_BW_SCALE_LAST \
23552 HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MIN_BW_SCALE_BYTES
23553 /* bw_value_unit is 3 b */
23554 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_MASK \
23555 UINT32_C(0xe0000000)
23556 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_SFT \
23558 /* Value is in Mb or MB (base 10). */
23559 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_MEGA \
23560 (UINT32_C(0x0) << 29)
23561 /* Value is in Kb or KB (base 10). */
23562 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_KILO \
23563 (UINT32_C(0x2) << 29)
23564 /* Value is in bits or bytes. */
23565 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_BASE \
23566 (UINT32_C(0x4) << 29)
23567 /* Value is in Gb or GB (base 10). */
23568 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_GIGA \
23569 (UINT32_C(0x6) << 29)
23570 /* Value is in 1/100th of a percentage of total bandwidth. */
23571 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 \
23572 (UINT32_C(0x1) << 29)
23574 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_INVALID \
23575 (UINT32_C(0x7) << 29)
23576 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_LAST \
23577 HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_INVALID
23579 * Maximum BW allocated to CoS queue.
23580 * The HWRM will translate this value into byte counter and
23581 * time interval used for this COS inside the device.
23583 uint32_t queue_id7_max_bw;
23584 /* The bandwidth value. */
23585 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MAX_BW_BW_VALUE_MASK \
23586 UINT32_C(0xfffffff)
23587 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MAX_BW_BW_VALUE_SFT \
23589 /* The granularity of the value (bits or bytes). */
23590 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MAX_BW_SCALE \
23591 UINT32_C(0x10000000)
23592 /* Value is in bits. */
23593 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MAX_BW_SCALE_BITS \
23594 (UINT32_C(0x0) << 28)
23595 /* Value is in bytes. */
23596 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MAX_BW_SCALE_BYTES \
23597 (UINT32_C(0x1) << 28)
23598 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MAX_BW_SCALE_LAST \
23599 HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MAX_BW_SCALE_BYTES
23600 /* bw_value_unit is 3 b */
23601 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_MASK \
23602 UINT32_C(0xe0000000)
23603 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_SFT \
23605 /* Value is in Mb or MB (base 10). */
23606 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_MEGA \
23607 (UINT32_C(0x0) << 29)
23608 /* Value is in Kb or KB (base 10). */
23609 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_KILO \
23610 (UINT32_C(0x2) << 29)
23611 /* Value is in bits or bytes. */
23612 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_BASE \
23613 (UINT32_C(0x4) << 29)
23614 /* Value is in Gb or GB (base 10). */
23615 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_GIGA \
23616 (UINT32_C(0x6) << 29)
23617 /* Value is in 1/100th of a percentage of total bandwidth. */
23618 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 \
23619 (UINT32_C(0x1) << 29)
23621 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_INVALID \
23622 (UINT32_C(0x7) << 29)
23623 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_LAST \
23624 HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_INVALID
23625 /* Transmission Selection Algorithm (TSA) for CoS Queue. */
23626 uint8_t queue_id7_tsa_assign;
23627 /* Strict Priority */
23628 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_TSA_ASSIGN_SP \
23630 /* Enhanced Transmission Selection */
23631 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_TSA_ASSIGN_ETS \
23634 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_TSA_ASSIGN_RESERVED_FIRST \
23637 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_TSA_ASSIGN_RESERVED_LAST \
23640 * Priority level for strict priority. Valid only when the
23641 * tsa_assign is 0 - Strict Priority (SP)
23642 * 0..7 - Valid values.
23643 * 8..255 - Reserved.
23645 uint8_t queue_id7_pri_lvl;
23647 * Weight used to allocate remaining BW for this COS after
23648 * servicing guaranteed bandwidths for all COS.
23650 uint8_t queue_id7_bw_weight;
23651 uint8_t unused_2[4];
23653 * This field is used in Output records to indicate that the output
23654 * is completely written to RAM. This field should be read as '1'
23655 * to indicate that the output has been completely written.
23656 * When writing a command completion or response to an internal processor,
23657 * the order of writes has to be such that this field is written last.
23662 /*************************
23663 * hwrm_queue_cos2bw_cfg *
23664 *************************/
23667 /* hwrm_queue_cos2bw_cfg_input (size:1024b/128B) */
23668 struct hwrm_queue_cos2bw_cfg_input {
23669 /* The HWRM command request type. */
23672 * The completion ring to send the completion event on. This should
23673 * be the NQ ID returned from the `nq_alloc` HWRM command.
23675 uint16_t cmpl_ring;
23677 * The sequence ID is used by the driver for tracking multiple
23678 * commands. This ID is treated as opaque data by the firmware and
23679 * the value is returned in the `hwrm_resp_hdr` upon completion.
23683 * The target ID of the command:
23684 * * 0x0-0xFFF8 - The function ID
23685 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
23686 * * 0xFFFD - Reserved for user-space HWRM interface
23689 uint16_t target_id;
23691 * A physical address pointer pointing to a host buffer that the
23692 * command's response data will be written. This can be either a host
23693 * physical address (HPA) or a guest physical address (GPA) and must
23694 * point to a physically contiguous block of memory.
23696 uint64_t resp_addr;
23700 * If this bit is set to 1, then all queue_id0 related
23701 * parameters in this command are valid.
23703 #define HWRM_QUEUE_COS2BW_CFG_INPUT_ENABLES_COS_QUEUE_ID0_VALID \
23706 * If this bit is set to 1, then all queue_id1 related
23707 * parameters in this command are valid.
23709 #define HWRM_QUEUE_COS2BW_CFG_INPUT_ENABLES_COS_QUEUE_ID1_VALID \
23712 * If this bit is set to 1, then all queue_id2 related
23713 * parameters in this command are valid.
23715 #define HWRM_QUEUE_COS2BW_CFG_INPUT_ENABLES_COS_QUEUE_ID2_VALID \
23718 * If this bit is set to 1, then all queue_id3 related
23719 * parameters in this command are valid.
23721 #define HWRM_QUEUE_COS2BW_CFG_INPUT_ENABLES_COS_QUEUE_ID3_VALID \
23724 * If this bit is set to 1, then all queue_id4 related
23725 * parameters in this command are valid.
23727 #define HWRM_QUEUE_COS2BW_CFG_INPUT_ENABLES_COS_QUEUE_ID4_VALID \
23730 * If this bit is set to 1, then all queue_id5 related
23731 * parameters in this command are valid.
23733 #define HWRM_QUEUE_COS2BW_CFG_INPUT_ENABLES_COS_QUEUE_ID5_VALID \
23736 * If this bit is set to 1, then all queue_id6 related
23737 * parameters in this command are valid.
23739 #define HWRM_QUEUE_COS2BW_CFG_INPUT_ENABLES_COS_QUEUE_ID6_VALID \
23742 * If this bit is set to 1, then all queue_id7 related
23743 * parameters in this command are valid.
23745 #define HWRM_QUEUE_COS2BW_CFG_INPUT_ENABLES_COS_QUEUE_ID7_VALID \
23748 * Port ID of port for which the table is being configured.
23749 * The HWRM needs to check whether this function is allowed
23750 * to configure TC BW assignment on this port.
23753 /* ID of CoS Queue 0. */
23757 * Minimum BW allocated to CoS Queue.
23758 * The HWRM will translate this value into byte counter and
23759 * time interval used for this COS inside the device.
23761 uint32_t queue_id0_min_bw;
23762 /* The bandwidth value. */
23763 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MIN_BW_BW_VALUE_MASK \
23764 UINT32_C(0xfffffff)
23765 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MIN_BW_BW_VALUE_SFT \
23767 /* The granularity of the value (bits or bytes). */
23768 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MIN_BW_SCALE \
23769 UINT32_C(0x10000000)
23770 /* Value is in bits. */
23771 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MIN_BW_SCALE_BITS \
23772 (UINT32_C(0x0) << 28)
23773 /* Value is in bytes. */
23774 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MIN_BW_SCALE_BYTES \
23775 (UINT32_C(0x1) << 28)
23776 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MIN_BW_SCALE_LAST \
23777 HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MIN_BW_SCALE_BYTES
23778 /* bw_value_unit is 3 b */
23779 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_MASK \
23780 UINT32_C(0xe0000000)
23781 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_SFT \
23783 /* Value is in Mb or MB (base 10). */
23784 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_MEGA \
23785 (UINT32_C(0x0) << 29)
23786 /* Value is in Kb or KB (base 10). */
23787 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_KILO \
23788 (UINT32_C(0x2) << 29)
23789 /* Value is in bits or bytes. */
23790 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_BASE \
23791 (UINT32_C(0x4) << 29)
23792 /* Value is in Gb or GB (base 10). */
23793 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_GIGA \
23794 (UINT32_C(0x6) << 29)
23795 /* Value is in 1/100th of a percentage of total bandwidth. */
23796 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 \
23797 (UINT32_C(0x1) << 29)
23799 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_INVALID \
23800 (UINT32_C(0x7) << 29)
23801 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_LAST \
23802 HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_INVALID
23804 * Maximum BW allocated to CoS Queue.
23805 * The HWRM will translate this value into byte counter and
23806 * time interval used for this COS inside the device.
23808 uint32_t queue_id0_max_bw;
23809 /* The bandwidth value. */
23810 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MAX_BW_BW_VALUE_MASK \
23811 UINT32_C(0xfffffff)
23812 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MAX_BW_BW_VALUE_SFT \
23814 /* The granularity of the value (bits or bytes). */
23815 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MAX_BW_SCALE \
23816 UINT32_C(0x10000000)
23817 /* Value is in bits. */
23818 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MAX_BW_SCALE_BITS \
23819 (UINT32_C(0x0) << 28)
23820 /* Value is in bytes. */
23821 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MAX_BW_SCALE_BYTES \
23822 (UINT32_C(0x1) << 28)
23823 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MAX_BW_SCALE_LAST \
23824 HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MAX_BW_SCALE_BYTES
23825 /* bw_value_unit is 3 b */
23826 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_MASK \
23827 UINT32_C(0xe0000000)
23828 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_SFT \
23830 /* Value is in Mb or MB (base 10). */
23831 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_MEGA \
23832 (UINT32_C(0x0) << 29)
23833 /* Value is in Kb or KB (base 10). */
23834 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_KILO \
23835 (UINT32_C(0x2) << 29)
23836 /* Value is in bits or bytes. */
23837 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_BASE \
23838 (UINT32_C(0x4) << 29)
23839 /* Value is in Gb or GB (base 10). */
23840 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_GIGA \
23841 (UINT32_C(0x6) << 29)
23842 /* Value is in 1/100th of a percentage of total bandwidth. */
23843 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 \
23844 (UINT32_C(0x1) << 29)
23846 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_INVALID \
23847 (UINT32_C(0x7) << 29)
23848 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_LAST \
23849 HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_INVALID
23850 /* Transmission Selection Algorithm (TSA) for CoS Queue. */
23851 uint8_t queue_id0_tsa_assign;
23852 /* Strict Priority */
23853 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_TSA_ASSIGN_SP \
23855 /* Enhanced Transmission Selection */
23856 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_TSA_ASSIGN_ETS \
23859 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_TSA_ASSIGN_RESERVED_FIRST \
23862 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_TSA_ASSIGN_RESERVED_LAST \
23865 * Priority level for strict priority. Valid only when the
23866 * tsa_assign is 0 - Strict Priority (SP)
23867 * 0..7 - Valid values.
23868 * 8..255 - Reserved.
23870 uint8_t queue_id0_pri_lvl;
23872 * Weight used to allocate remaining BW for this COS after
23873 * servicing guaranteed bandwidths for all COS.
23875 uint8_t queue_id0_bw_weight;
23876 /* ID of CoS Queue 1. */
23879 * Minimum BW allocated to CoS Queue.
23880 * The HWRM will translate this value into byte counter and
23881 * time interval used for this COS inside the device.
23883 uint32_t queue_id1_min_bw;
23884 /* The bandwidth value. */
23885 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MIN_BW_BW_VALUE_MASK \
23886 UINT32_C(0xfffffff)
23887 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MIN_BW_BW_VALUE_SFT \
23889 /* The granularity of the value (bits or bytes). */
23890 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MIN_BW_SCALE \
23891 UINT32_C(0x10000000)
23892 /* Value is in bits. */
23893 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MIN_BW_SCALE_BITS \
23894 (UINT32_C(0x0) << 28)
23895 /* Value is in bytes. */
23896 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MIN_BW_SCALE_BYTES \
23897 (UINT32_C(0x1) << 28)
23898 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MIN_BW_SCALE_LAST \
23899 HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MIN_BW_SCALE_BYTES
23900 /* bw_value_unit is 3 b */
23901 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_MASK \
23902 UINT32_C(0xe0000000)
23903 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_SFT \
23905 /* Value is in Mb or MB (base 10). */
23906 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_MEGA \
23907 (UINT32_C(0x0) << 29)
23908 /* Value is in Kb or KB (base 10). */
23909 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_KILO \
23910 (UINT32_C(0x2) << 29)
23911 /* Value is in bits or bytes. */
23912 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_BASE \
23913 (UINT32_C(0x4) << 29)
23914 /* Value is in Gb or GB (base 10). */
23915 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_GIGA \
23916 (UINT32_C(0x6) << 29)
23917 /* Value is in 1/100th of a percentage of total bandwidth. */
23918 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 \
23919 (UINT32_C(0x1) << 29)
23921 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_INVALID \
23922 (UINT32_C(0x7) << 29)
23923 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_LAST \
23924 HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_INVALID
23926 * Maximum BW allocated to CoS queue.
23927 * The HWRM will translate this value into byte counter and
23928 * time interval used for this COS inside the device.
23930 uint32_t queue_id1_max_bw;
23931 /* The bandwidth value. */
23932 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MAX_BW_BW_VALUE_MASK \
23933 UINT32_C(0xfffffff)
23934 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MAX_BW_BW_VALUE_SFT \
23936 /* The granularity of the value (bits or bytes). */
23937 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MAX_BW_SCALE \
23938 UINT32_C(0x10000000)
23939 /* Value is in bits. */
23940 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MAX_BW_SCALE_BITS \
23941 (UINT32_C(0x0) << 28)
23942 /* Value is in bytes. */
23943 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MAX_BW_SCALE_BYTES \
23944 (UINT32_C(0x1) << 28)
23945 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MAX_BW_SCALE_LAST \
23946 HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MAX_BW_SCALE_BYTES
23947 /* bw_value_unit is 3 b */
23948 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_MASK \
23949 UINT32_C(0xe0000000)
23950 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_SFT \
23952 /* Value is in Mb or MB (base 10). */
23953 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_MEGA \
23954 (UINT32_C(0x0) << 29)
23955 /* Value is in Kb or KB (base 10). */
23956 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_KILO \
23957 (UINT32_C(0x2) << 29)
23958 /* Value is in bits or bytes. */
23959 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_BASE \
23960 (UINT32_C(0x4) << 29)
23961 /* Value is in Gb or GB (base 10). */
23962 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_GIGA \
23963 (UINT32_C(0x6) << 29)
23964 /* Value is in 1/100th of a percentage of total bandwidth. */
23965 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 \
23966 (UINT32_C(0x1) << 29)
23968 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_INVALID \
23969 (UINT32_C(0x7) << 29)
23970 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_LAST \
23971 HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_INVALID
23972 /* Transmission Selection Algorithm (TSA) for CoS Queue. */
23973 uint8_t queue_id1_tsa_assign;
23974 /* Strict Priority */
23975 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_TSA_ASSIGN_SP \
23977 /* Enhanced Transmission Selection */
23978 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_TSA_ASSIGN_ETS \
23981 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_TSA_ASSIGN_RESERVED_FIRST \
23984 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_TSA_ASSIGN_RESERVED_LAST \
23987 * Priority level for strict priority. Valid only when the
23988 * tsa_assign is 0 - Strict Priority (SP)
23989 * 0..7 - Valid values.
23990 * 8..255 - Reserved.
23992 uint8_t queue_id1_pri_lvl;
23994 * Weight used to allocate remaining BW for this COS after
23995 * servicing guaranteed bandwidths for all COS.
23997 uint8_t queue_id1_bw_weight;
23998 /* ID of CoS Queue 2. */
24001 * Minimum BW allocated to CoS Queue.
24002 * The HWRM will translate this value into byte counter and
24003 * time interval used for this COS inside the device.
24005 uint32_t queue_id2_min_bw;
24006 /* The bandwidth value. */
24007 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MIN_BW_BW_VALUE_MASK \
24008 UINT32_C(0xfffffff)
24009 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MIN_BW_BW_VALUE_SFT \
24011 /* The granularity of the value (bits or bytes). */
24012 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MIN_BW_SCALE \
24013 UINT32_C(0x10000000)
24014 /* Value is in bits. */
24015 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MIN_BW_SCALE_BITS \
24016 (UINT32_C(0x0) << 28)
24017 /* Value is in bytes. */
24018 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MIN_BW_SCALE_BYTES \
24019 (UINT32_C(0x1) << 28)
24020 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MIN_BW_SCALE_LAST \
24021 HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MIN_BW_SCALE_BYTES
24022 /* bw_value_unit is 3 b */
24023 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_MASK \
24024 UINT32_C(0xe0000000)
24025 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_SFT \
24027 /* Value is in Mb or MB (base 10). */
24028 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_MEGA \
24029 (UINT32_C(0x0) << 29)
24030 /* Value is in Kb or KB (base 10). */
24031 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_KILO \
24032 (UINT32_C(0x2) << 29)
24033 /* Value is in bits or bytes. */
24034 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_BASE \
24035 (UINT32_C(0x4) << 29)
24036 /* Value is in Gb or GB (base 10). */
24037 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_GIGA \
24038 (UINT32_C(0x6) << 29)
24039 /* Value is in 1/100th of a percentage of total bandwidth. */
24040 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 \
24041 (UINT32_C(0x1) << 29)
24043 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_INVALID \
24044 (UINT32_C(0x7) << 29)
24045 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_LAST \
24046 HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_INVALID
24048 * Maximum BW allocated to CoS queue.
24049 * The HWRM will translate this value into byte counter and
24050 * time interval used for this COS inside the device.
24052 uint32_t queue_id2_max_bw;
24053 /* The bandwidth value. */
24054 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MAX_BW_BW_VALUE_MASK \
24055 UINT32_C(0xfffffff)
24056 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MAX_BW_BW_VALUE_SFT \
24058 /* The granularity of the value (bits or bytes). */
24059 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MAX_BW_SCALE \
24060 UINT32_C(0x10000000)
24061 /* Value is in bits. */
24062 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MAX_BW_SCALE_BITS \
24063 (UINT32_C(0x0) << 28)
24064 /* Value is in bytes. */
24065 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MAX_BW_SCALE_BYTES \
24066 (UINT32_C(0x1) << 28)
24067 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MAX_BW_SCALE_LAST \
24068 HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MAX_BW_SCALE_BYTES
24069 /* bw_value_unit is 3 b */
24070 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_MASK \
24071 UINT32_C(0xe0000000)
24072 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_SFT \
24074 /* Value is in Mb or MB (base 10). */
24075 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_MEGA \
24076 (UINT32_C(0x0) << 29)
24077 /* Value is in Kb or KB (base 10). */
24078 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_KILO \
24079 (UINT32_C(0x2) << 29)
24080 /* Value is in bits or bytes. */
24081 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_BASE \
24082 (UINT32_C(0x4) << 29)
24083 /* Value is in Gb or GB (base 10). */
24084 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_GIGA \
24085 (UINT32_C(0x6) << 29)
24086 /* Value is in 1/100th of a percentage of total bandwidth. */
24087 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 \
24088 (UINT32_C(0x1) << 29)
24090 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_INVALID \
24091 (UINT32_C(0x7) << 29)
24092 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_LAST \
24093 HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_INVALID
24094 /* Transmission Selection Algorithm (TSA) for CoS Queue. */
24095 uint8_t queue_id2_tsa_assign;
24096 /* Strict Priority */
24097 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_TSA_ASSIGN_SP \
24099 /* Enhanced Transmission Selection */
24100 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_TSA_ASSIGN_ETS \
24103 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_TSA_ASSIGN_RESERVED_FIRST \
24106 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_TSA_ASSIGN_RESERVED_LAST \
24109 * Priority level for strict priority. Valid only when the
24110 * tsa_assign is 0 - Strict Priority (SP)
24111 * 0..7 - Valid values.
24112 * 8..255 - Reserved.
24114 uint8_t queue_id2_pri_lvl;
24116 * Weight used to allocate remaining BW for this COS after
24117 * servicing guaranteed bandwidths for all COS.
24119 uint8_t queue_id2_bw_weight;
24120 /* ID of CoS Queue 3. */
24123 * Minimum BW allocated to CoS Queue.
24124 * The HWRM will translate this value into byte counter and
24125 * time interval used for this COS inside the device.
24127 uint32_t queue_id3_min_bw;
24128 /* The bandwidth value. */
24129 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MIN_BW_BW_VALUE_MASK \
24130 UINT32_C(0xfffffff)
24131 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MIN_BW_BW_VALUE_SFT \
24133 /* The granularity of the value (bits or bytes). */
24134 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MIN_BW_SCALE \
24135 UINT32_C(0x10000000)
24136 /* Value is in bits. */
24137 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MIN_BW_SCALE_BITS \
24138 (UINT32_C(0x0) << 28)
24139 /* Value is in bytes. */
24140 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MIN_BW_SCALE_BYTES \
24141 (UINT32_C(0x1) << 28)
24142 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MIN_BW_SCALE_LAST \
24143 HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MIN_BW_SCALE_BYTES
24144 /* bw_value_unit is 3 b */
24145 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_MASK \
24146 UINT32_C(0xe0000000)
24147 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_SFT \
24149 /* Value is in Mb or MB (base 10). */
24150 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_MEGA \
24151 (UINT32_C(0x0) << 29)
24152 /* Value is in Kb or KB (base 10). */
24153 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_KILO \
24154 (UINT32_C(0x2) << 29)
24155 /* Value is in bits or bytes. */
24156 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_BASE \
24157 (UINT32_C(0x4) << 29)
24158 /* Value is in Gb or GB (base 10). */
24159 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_GIGA \
24160 (UINT32_C(0x6) << 29)
24161 /* Value is in 1/100th of a percentage of total bandwidth. */
24162 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 \
24163 (UINT32_C(0x1) << 29)
24165 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_INVALID \
24166 (UINT32_C(0x7) << 29)
24167 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_LAST \
24168 HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_INVALID
24170 * Maximum BW allocated to CoS queue.
24171 * The HWRM will translate this value into byte counter and
24172 * time interval used for this COS inside the device.
24174 uint32_t queue_id3_max_bw;
24175 /* The bandwidth value. */
24176 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MAX_BW_BW_VALUE_MASK \
24177 UINT32_C(0xfffffff)
24178 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MAX_BW_BW_VALUE_SFT \
24180 /* The granularity of the value (bits or bytes). */
24181 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MAX_BW_SCALE \
24182 UINT32_C(0x10000000)
24183 /* Value is in bits. */
24184 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MAX_BW_SCALE_BITS \
24185 (UINT32_C(0x0) << 28)
24186 /* Value is in bytes. */
24187 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MAX_BW_SCALE_BYTES \
24188 (UINT32_C(0x1) << 28)
24189 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MAX_BW_SCALE_LAST \
24190 HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MAX_BW_SCALE_BYTES
24191 /* bw_value_unit is 3 b */
24192 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_MASK \
24193 UINT32_C(0xe0000000)
24194 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_SFT \
24196 /* Value is in Mb or MB (base 10). */
24197 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_MEGA \
24198 (UINT32_C(0x0) << 29)
24199 /* Value is in Kb or KB (base 10). */
24200 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_KILO \
24201 (UINT32_C(0x2) << 29)
24202 /* Value is in bits or bytes. */
24203 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_BASE \
24204 (UINT32_C(0x4) << 29)
24205 /* Value is in Gb or GB (base 10). */
24206 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_GIGA \
24207 (UINT32_C(0x6) << 29)
24208 /* Value is in 1/100th of a percentage of total bandwidth. */
24209 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 \
24210 (UINT32_C(0x1) << 29)
24212 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_INVALID \
24213 (UINT32_C(0x7) << 29)
24214 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_LAST \
24215 HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_INVALID
24216 /* Transmission Selection Algorithm (TSA) for CoS Queue. */
24217 uint8_t queue_id3_tsa_assign;
24218 /* Strict Priority */
24219 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_TSA_ASSIGN_SP \
24221 /* Enhanced Transmission Selection */
24222 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_TSA_ASSIGN_ETS \
24225 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_TSA_ASSIGN_RESERVED_FIRST \
24228 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_TSA_ASSIGN_RESERVED_LAST \
24231 * Priority level for strict priority. Valid only when the
24232 * tsa_assign is 0 - Strict Priority (SP)
24233 * 0..7 - Valid values.
24234 * 8..255 - Reserved.
24236 uint8_t queue_id3_pri_lvl;
24238 * Weight used to allocate remaining BW for this COS after
24239 * servicing guaranteed bandwidths for all COS.
24241 uint8_t queue_id3_bw_weight;
24242 /* ID of CoS Queue 4. */
24245 * Minimum BW allocated to CoS Queue.
24246 * The HWRM will translate this value into byte counter and
24247 * time interval used for this COS inside the device.
24249 uint32_t queue_id4_min_bw;
24250 /* The bandwidth value. */
24251 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MIN_BW_BW_VALUE_MASK \
24252 UINT32_C(0xfffffff)
24253 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MIN_BW_BW_VALUE_SFT \
24255 /* The granularity of the value (bits or bytes). */
24256 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MIN_BW_SCALE \
24257 UINT32_C(0x10000000)
24258 /* Value is in bits. */
24259 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MIN_BW_SCALE_BITS \
24260 (UINT32_C(0x0) << 28)
24261 /* Value is in bytes. */
24262 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MIN_BW_SCALE_BYTES \
24263 (UINT32_C(0x1) << 28)
24264 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MIN_BW_SCALE_LAST \
24265 HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MIN_BW_SCALE_BYTES
24266 /* bw_value_unit is 3 b */
24267 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_MASK \
24268 UINT32_C(0xe0000000)
24269 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_SFT \
24271 /* Value is in Mb or MB (base 10). */
24272 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_MEGA \
24273 (UINT32_C(0x0) << 29)
24274 /* Value is in Kb or KB (base 10). */
24275 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_KILO \
24276 (UINT32_C(0x2) << 29)
24277 /* Value is in bits or bytes. */
24278 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_BASE \
24279 (UINT32_C(0x4) << 29)
24280 /* Value is in Gb or GB (base 10). */
24281 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_GIGA \
24282 (UINT32_C(0x6) << 29)
24283 /* Value is in 1/100th of a percentage of total bandwidth. */
24284 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 \
24285 (UINT32_C(0x1) << 29)
24287 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_INVALID \
24288 (UINT32_C(0x7) << 29)
24289 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_LAST \
24290 HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_INVALID
24292 * Maximum BW allocated to CoS queue.
24293 * The HWRM will translate this value into byte counter and
24294 * time interval used for this COS inside the device.
24296 uint32_t queue_id4_max_bw;
24297 /* The bandwidth value. */
24298 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MAX_BW_BW_VALUE_MASK \
24299 UINT32_C(0xfffffff)
24300 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MAX_BW_BW_VALUE_SFT \
24302 /* The granularity of the value (bits or bytes). */
24303 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MAX_BW_SCALE \
24304 UINT32_C(0x10000000)
24305 /* Value is in bits. */
24306 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MAX_BW_SCALE_BITS \
24307 (UINT32_C(0x0) << 28)
24308 /* Value is in bytes. */
24309 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MAX_BW_SCALE_BYTES \
24310 (UINT32_C(0x1) << 28)
24311 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MAX_BW_SCALE_LAST \
24312 HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MAX_BW_SCALE_BYTES
24313 /* bw_value_unit is 3 b */
24314 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_MASK \
24315 UINT32_C(0xe0000000)
24316 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_SFT \
24318 /* Value is in Mb or MB (base 10). */
24319 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_MEGA \
24320 (UINT32_C(0x0) << 29)
24321 /* Value is in Kb or KB (base 10). */
24322 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_KILO \
24323 (UINT32_C(0x2) << 29)
24324 /* Value is in bits or bytes. */
24325 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_BASE \
24326 (UINT32_C(0x4) << 29)
24327 /* Value is in Gb or GB (base 10). */
24328 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_GIGA \
24329 (UINT32_C(0x6) << 29)
24330 /* Value is in 1/100th of a percentage of total bandwidth. */
24331 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 \
24332 (UINT32_C(0x1) << 29)
24334 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_INVALID \
24335 (UINT32_C(0x7) << 29)
24336 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_LAST \
24337 HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_INVALID
24338 /* Transmission Selection Algorithm (TSA) for CoS Queue. */
24339 uint8_t queue_id4_tsa_assign;
24340 /* Strict Priority */
24341 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_TSA_ASSIGN_SP \
24343 /* Enhanced Transmission Selection */
24344 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_TSA_ASSIGN_ETS \
24347 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_TSA_ASSIGN_RESERVED_FIRST \
24350 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_TSA_ASSIGN_RESERVED_LAST \
24353 * Priority level for strict priority. Valid only when the
24354 * tsa_assign is 0 - Strict Priority (SP)
24355 * 0..7 - Valid values.
24356 * 8..255 - Reserved.
24358 uint8_t queue_id4_pri_lvl;
24360 * Weight used to allocate remaining BW for this COS after
24361 * servicing guaranteed bandwidths for all COS.
24363 uint8_t queue_id4_bw_weight;
24364 /* ID of CoS Queue 5. */
24367 * Minimum BW allocated to CoS Queue.
24368 * The HWRM will translate this value into byte counter and
24369 * time interval used for this COS inside the device.
24371 uint32_t queue_id5_min_bw;
24372 /* The bandwidth value. */
24373 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MIN_BW_BW_VALUE_MASK \
24374 UINT32_C(0xfffffff)
24375 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MIN_BW_BW_VALUE_SFT \
24377 /* The granularity of the value (bits or bytes). */
24378 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MIN_BW_SCALE \
24379 UINT32_C(0x10000000)
24380 /* Value is in bits. */
24381 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MIN_BW_SCALE_BITS \
24382 (UINT32_C(0x0) << 28)
24383 /* Value is in bytes. */
24384 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MIN_BW_SCALE_BYTES \
24385 (UINT32_C(0x1) << 28)
24386 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MIN_BW_SCALE_LAST \
24387 HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MIN_BW_SCALE_BYTES
24388 /* bw_value_unit is 3 b */
24389 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_MASK \
24390 UINT32_C(0xe0000000)
24391 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_SFT \
24393 /* Value is in Mb or MB (base 10). */
24394 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_MEGA \
24395 (UINT32_C(0x0) << 29)
24396 /* Value is in Kb or KB (base 10). */
24397 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_KILO \
24398 (UINT32_C(0x2) << 29)
24399 /* Value is in bits or bytes. */
24400 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_BASE \
24401 (UINT32_C(0x4) << 29)
24402 /* Value is in Gb or GB (base 10). */
24403 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_GIGA \
24404 (UINT32_C(0x6) << 29)
24405 /* Value is in 1/100th of a percentage of total bandwidth. */
24406 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 \
24407 (UINT32_C(0x1) << 29)
24409 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_INVALID \
24410 (UINT32_C(0x7) << 29)
24411 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_LAST \
24412 HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_INVALID
24414 * Maximum BW allocated to CoS queue.
24415 * The HWRM will translate this value into byte counter and
24416 * time interval used for this COS inside the device.
24418 uint32_t queue_id5_max_bw;
24419 /* The bandwidth value. */
24420 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MAX_BW_BW_VALUE_MASK \
24421 UINT32_C(0xfffffff)
24422 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MAX_BW_BW_VALUE_SFT \
24424 /* The granularity of the value (bits or bytes). */
24425 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MAX_BW_SCALE \
24426 UINT32_C(0x10000000)
24427 /* Value is in bits. */
24428 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MAX_BW_SCALE_BITS \
24429 (UINT32_C(0x0) << 28)
24430 /* Value is in bytes. */
24431 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MAX_BW_SCALE_BYTES \
24432 (UINT32_C(0x1) << 28)
24433 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MAX_BW_SCALE_LAST \
24434 HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MAX_BW_SCALE_BYTES
24435 /* bw_value_unit is 3 b */
24436 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_MASK \
24437 UINT32_C(0xe0000000)
24438 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_SFT \
24440 /* Value is in Mb or MB (base 10). */
24441 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_MEGA \
24442 (UINT32_C(0x0) << 29)
24443 /* Value is in Kb or KB (base 10). */
24444 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_KILO \
24445 (UINT32_C(0x2) << 29)
24446 /* Value is in bits or bytes. */
24447 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_BASE \
24448 (UINT32_C(0x4) << 29)
24449 /* Value is in Gb or GB (base 10). */
24450 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_GIGA \
24451 (UINT32_C(0x6) << 29)
24452 /* Value is in 1/100th of a percentage of total bandwidth. */
24453 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 \
24454 (UINT32_C(0x1) << 29)
24456 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_INVALID \
24457 (UINT32_C(0x7) << 29)
24458 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_LAST \
24459 HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_INVALID
24460 /* Transmission Selection Algorithm (TSA) for CoS Queue. */
24461 uint8_t queue_id5_tsa_assign;
24462 /* Strict Priority */
24463 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_TSA_ASSIGN_SP \
24465 /* Enhanced Transmission Selection */
24466 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_TSA_ASSIGN_ETS \
24469 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_TSA_ASSIGN_RESERVED_FIRST \
24472 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_TSA_ASSIGN_RESERVED_LAST \
24475 * Priority level for strict priority. Valid only when the
24476 * tsa_assign is 0 - Strict Priority (SP)
24477 * 0..7 - Valid values.
24478 * 8..255 - Reserved.
24480 uint8_t queue_id5_pri_lvl;
24482 * Weight used to allocate remaining BW for this COS after
24483 * servicing guaranteed bandwidths for all COS.
24485 uint8_t queue_id5_bw_weight;
24486 /* ID of CoS Queue 6. */
24489 * Minimum BW allocated to CoS Queue.
24490 * The HWRM will translate this value into byte counter and
24491 * time interval used for this COS inside the device.
24493 uint32_t queue_id6_min_bw;
24494 /* The bandwidth value. */
24495 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MIN_BW_BW_VALUE_MASK \
24496 UINT32_C(0xfffffff)
24497 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MIN_BW_BW_VALUE_SFT \
24499 /* The granularity of the value (bits or bytes). */
24500 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MIN_BW_SCALE \
24501 UINT32_C(0x10000000)
24502 /* Value is in bits. */
24503 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MIN_BW_SCALE_BITS \
24504 (UINT32_C(0x0) << 28)
24505 /* Value is in bytes. */
24506 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MIN_BW_SCALE_BYTES \
24507 (UINT32_C(0x1) << 28)
24508 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MIN_BW_SCALE_LAST \
24509 HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MIN_BW_SCALE_BYTES
24510 /* bw_value_unit is 3 b */
24511 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_MASK \
24512 UINT32_C(0xe0000000)
24513 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_SFT \
24515 /* Value is in Mb or MB (base 10). */
24516 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_MEGA \
24517 (UINT32_C(0x0) << 29)
24518 /* Value is in Kb or KB (base 10). */
24519 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_KILO \
24520 (UINT32_C(0x2) << 29)
24521 /* Value is in bits or bytes. */
24522 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_BASE \
24523 (UINT32_C(0x4) << 29)
24524 /* Value is in Gb or GB (base 10). */
24525 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_GIGA \
24526 (UINT32_C(0x6) << 29)
24527 /* Value is in 1/100th of a percentage of total bandwidth. */
24528 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 \
24529 (UINT32_C(0x1) << 29)
24531 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_INVALID \
24532 (UINT32_C(0x7) << 29)
24533 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_LAST \
24534 HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_INVALID
24536 * Maximum BW allocated to CoS queue.
24537 * The HWRM will translate this value into byte counter and
24538 * time interval used for this COS inside the device.
24540 uint32_t queue_id6_max_bw;
24541 /* The bandwidth value. */
24542 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MAX_BW_BW_VALUE_MASK \
24543 UINT32_C(0xfffffff)
24544 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MAX_BW_BW_VALUE_SFT \
24546 /* The granularity of the value (bits or bytes). */
24547 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MAX_BW_SCALE \
24548 UINT32_C(0x10000000)
24549 /* Value is in bits. */
24550 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MAX_BW_SCALE_BITS \
24551 (UINT32_C(0x0) << 28)
24552 /* Value is in bytes. */
24553 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MAX_BW_SCALE_BYTES \
24554 (UINT32_C(0x1) << 28)
24555 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MAX_BW_SCALE_LAST \
24556 HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MAX_BW_SCALE_BYTES
24557 /* bw_value_unit is 3 b */
24558 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_MASK \
24559 UINT32_C(0xe0000000)
24560 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_SFT \
24562 /* Value is in Mb or MB (base 10). */
24563 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_MEGA \
24564 (UINT32_C(0x0) << 29)
24565 /* Value is in Kb or KB (base 10). */
24566 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_KILO \
24567 (UINT32_C(0x2) << 29)
24568 /* Value is in bits or bytes. */
24569 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_BASE \
24570 (UINT32_C(0x4) << 29)
24571 /* Value is in Gb or GB (base 10). */
24572 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_GIGA \
24573 (UINT32_C(0x6) << 29)
24574 /* Value is in 1/100th of a percentage of total bandwidth. */
24575 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 \
24576 (UINT32_C(0x1) << 29)
24578 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_INVALID \
24579 (UINT32_C(0x7) << 29)
24580 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_LAST \
24581 HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_INVALID
24582 /* Transmission Selection Algorithm (TSA) for CoS Queue. */
24583 uint8_t queue_id6_tsa_assign;
24584 /* Strict Priority */
24585 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_TSA_ASSIGN_SP \
24587 /* Enhanced Transmission Selection */
24588 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_TSA_ASSIGN_ETS \
24591 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_TSA_ASSIGN_RESERVED_FIRST \
24594 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_TSA_ASSIGN_RESERVED_LAST \
24597 * Priority level for strict priority. Valid only when the
24598 * tsa_assign is 0 - Strict Priority (SP)
24599 * 0..7 - Valid values.
24600 * 8..255 - Reserved.
24602 uint8_t queue_id6_pri_lvl;
24604 * Weight used to allocate remaining BW for this COS after
24605 * servicing guaranteed bandwidths for all COS.
24607 uint8_t queue_id6_bw_weight;
24608 /* ID of CoS Queue 7. */
24611 * Minimum BW allocated to CoS Queue.
24612 * The HWRM will translate this value into byte counter and
24613 * time interval used for this COS inside the device.
24615 uint32_t queue_id7_min_bw;
24616 /* The bandwidth value. */
24617 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MIN_BW_BW_VALUE_MASK \
24618 UINT32_C(0xfffffff)
24619 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MIN_BW_BW_VALUE_SFT \
24621 /* The granularity of the value (bits or bytes). */
24622 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MIN_BW_SCALE \
24623 UINT32_C(0x10000000)
24624 /* Value is in bits. */
24625 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MIN_BW_SCALE_BITS \
24626 (UINT32_C(0x0) << 28)
24627 /* Value is in bytes. */
24628 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MIN_BW_SCALE_BYTES \
24629 (UINT32_C(0x1) << 28)
24630 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MIN_BW_SCALE_LAST \
24631 HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MIN_BW_SCALE_BYTES
24632 /* bw_value_unit is 3 b */
24633 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_MASK \
24634 UINT32_C(0xe0000000)
24635 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_SFT \
24637 /* Value is in Mb or MB (base 10). */
24638 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_MEGA \
24639 (UINT32_C(0x0) << 29)
24640 /* Value is in Kb or KB (base 10). */
24641 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_KILO \
24642 (UINT32_C(0x2) << 29)
24643 /* Value is in bits or bytes. */
24644 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_BASE \
24645 (UINT32_C(0x4) << 29)
24646 /* Value is in Gb or GB (base 10). */
24647 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_GIGA \
24648 (UINT32_C(0x6) << 29)
24649 /* Value is in 1/100th of a percentage of total bandwidth. */
24650 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 \
24651 (UINT32_C(0x1) << 29)
24653 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_INVALID \
24654 (UINT32_C(0x7) << 29)
24655 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_LAST \
24656 HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_INVALID
24658 * Maximum BW allocated to CoS queue.
24659 * The HWRM will translate this value into byte counter and
24660 * time interval used for this COS inside the device.
24662 uint32_t queue_id7_max_bw;
24663 /* The bandwidth value. */
24664 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MAX_BW_BW_VALUE_MASK \
24665 UINT32_C(0xfffffff)
24666 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MAX_BW_BW_VALUE_SFT \
24668 /* The granularity of the value (bits or bytes). */
24669 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MAX_BW_SCALE \
24670 UINT32_C(0x10000000)
24671 /* Value is in bits. */
24672 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MAX_BW_SCALE_BITS \
24673 (UINT32_C(0x0) << 28)
24674 /* Value is in bytes. */
24675 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MAX_BW_SCALE_BYTES \
24676 (UINT32_C(0x1) << 28)
24677 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MAX_BW_SCALE_LAST \
24678 HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MAX_BW_SCALE_BYTES
24679 /* bw_value_unit is 3 b */
24680 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_MASK \
24681 UINT32_C(0xe0000000)
24682 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_SFT \
24684 /* Value is in Mb or MB (base 10). */
24685 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_MEGA \
24686 (UINT32_C(0x0) << 29)
24687 /* Value is in Kb or KB (base 10). */
24688 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_KILO \
24689 (UINT32_C(0x2) << 29)
24690 /* Value is in bits or bytes. */
24691 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_BASE \
24692 (UINT32_C(0x4) << 29)
24693 /* Value is in Gb or GB (base 10). */
24694 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_GIGA \
24695 (UINT32_C(0x6) << 29)
24696 /* Value is in 1/100th of a percentage of total bandwidth. */
24697 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 \
24698 (UINT32_C(0x1) << 29)
24700 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_INVALID \
24701 (UINT32_C(0x7) << 29)
24702 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_LAST \
24703 HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_INVALID
24704 /* Transmission Selection Algorithm (TSA) for CoS Queue. */
24705 uint8_t queue_id7_tsa_assign;
24706 /* Strict Priority */
24707 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_TSA_ASSIGN_SP \
24709 /* Enhanced Transmission Selection */
24710 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_TSA_ASSIGN_ETS \
24713 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_TSA_ASSIGN_RESERVED_FIRST \
24716 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_TSA_ASSIGN_RESERVED_LAST \
24719 * Priority level for strict priority. Valid only when the
24720 * tsa_assign is 0 - Strict Priority (SP)
24721 * 0..7 - Valid values.
24722 * 8..255 - Reserved.
24724 uint8_t queue_id7_pri_lvl;
24726 * Weight used to allocate remaining BW for this COS after
24727 * servicing guaranteed bandwidths for all COS.
24729 uint8_t queue_id7_bw_weight;
24730 uint8_t unused_1[5];
24733 /* hwrm_queue_cos2bw_cfg_output (size:128b/16B) */
24734 struct hwrm_queue_cos2bw_cfg_output {
24735 /* The specific error status for the command. */
24736 uint16_t error_code;
24737 /* The HWRM command request type. */
24739 /* The sequence ID from the original command. */
24741 /* The length of the response data in number of bytes. */
24743 uint8_t unused_0[7];
24745 * This field is used in Output records to indicate that the output
24746 * is completely written to RAM. This field should be read as '1'
24747 * to indicate that the output has been completely written.
24748 * When writing a command completion or response to an internal processor,
24749 * the order of writes has to be such that this field is written last.
24754 /*************************
24755 * hwrm_queue_dscp_qcaps *
24756 *************************/
24759 /* hwrm_queue_dscp_qcaps_input (size:192b/24B) */
24760 struct hwrm_queue_dscp_qcaps_input {
24761 /* The HWRM command request type. */
24764 * The completion ring to send the completion event on. This should
24765 * be the NQ ID returned from the `nq_alloc` HWRM command.
24767 uint16_t cmpl_ring;
24769 * The sequence ID is used by the driver for tracking multiple
24770 * commands. This ID is treated as opaque data by the firmware and
24771 * the value is returned in the `hwrm_resp_hdr` upon completion.
24775 * The target ID of the command:
24776 * * 0x0-0xFFF8 - The function ID
24777 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
24778 * * 0xFFFD - Reserved for user-space HWRM interface
24781 uint16_t target_id;
24783 * A physical address pointer pointing to a host buffer that the
24784 * command's response data will be written. This can be either a host
24785 * physical address (HPA) or a guest physical address (GPA) and must
24786 * point to a physically contiguous block of memory.
24788 uint64_t resp_addr;
24790 * Port ID of port for which the table is being configured.
24791 * The HWRM needs to check whether this function is allowed
24792 * to configure pri2cos mapping on this port.
24795 uint8_t unused_0[7];
24798 /* hwrm_queue_dscp_qcaps_output (size:128b/16B) */
24799 struct hwrm_queue_dscp_qcaps_output {
24800 /* The specific error status for the command. */
24801 uint16_t error_code;
24802 /* The HWRM command request type. */
24804 /* The sequence ID from the original command. */
24806 /* The length of the response data in number of bytes. */
24808 /* The number of bits provided by the hardware for the DSCP value. */
24809 uint8_t num_dscp_bits;
24811 /* Max number of DSCP-MASK-PRI entries supported. */
24812 uint16_t max_entries;
24813 uint8_t unused_1[3];
24815 * This field is used in Output records to indicate that the output
24816 * is completely written to RAM. This field should be read as '1'
24817 * to indicate that the output has been completely written.
24818 * When writing a command completion or response to an internal processor,
24819 * the order of writes has to be such that this field is written last.
24824 /****************************
24825 * hwrm_queue_dscp2pri_qcfg *
24826 ****************************/
24829 /* hwrm_queue_dscp2pri_qcfg_input (size:256b/32B) */
24830 struct hwrm_queue_dscp2pri_qcfg_input {
24831 /* The HWRM command request type. */
24834 * The completion ring to send the completion event on. This should
24835 * be the NQ ID returned from the `nq_alloc` HWRM command.
24837 uint16_t cmpl_ring;
24839 * The sequence ID is used by the driver for tracking multiple
24840 * commands. This ID is treated as opaque data by the firmware and
24841 * the value is returned in the `hwrm_resp_hdr` upon completion.
24845 * The target ID of the command:
24846 * * 0x0-0xFFF8 - The function ID
24847 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
24848 * * 0xFFFD - Reserved for user-space HWRM interface
24851 uint16_t target_id;
24853 * A physical address pointer pointing to a host buffer that the
24854 * command's response data will be written. This can be either a host
24855 * physical address (HPA) or a guest physical address (GPA) and must
24856 * point to a physically contiguous block of memory.
24858 uint64_t resp_addr;
24860 * This is the host address where the 24-bits DSCP-MASK-PRI
24861 * tuple(s) will be copied to.
24863 uint64_t dest_data_addr;
24865 * Port ID of port for which the table is being configured.
24866 * The HWRM needs to check whether this function is allowed
24867 * to configure pri2cos mapping on this port.
24871 /* Size of the buffer pointed to by dest_data_addr. */
24872 uint16_t dest_data_buffer_size;
24873 uint8_t unused_1[4];
24876 /* hwrm_queue_dscp2pri_qcfg_output (size:128b/16B) */
24877 struct hwrm_queue_dscp2pri_qcfg_output {
24878 /* The specific error status for the command. */
24879 uint16_t error_code;
24880 /* The HWRM command request type. */
24882 /* The sequence ID from the original command. */
24884 /* The length of the response data in number of bytes. */
24887 * A count of the number of DSCP-MASK-PRI tuple(s) pointed to
24888 * by the dest_data_addr.
24890 uint16_t entry_cnt;
24892 * This is the default PRI which un-initialized DSCP values are
24895 uint8_t default_pri;
24896 uint8_t unused_0[4];
24898 * This field is used in Output records to indicate that the output
24899 * is completely written to RAM. This field should be read as '1'
24900 * to indicate that the output has been completely written.
24901 * When writing a command completion or response to an internal processor,
24902 * the order of writes has to be such that this field is written last.
24907 /***************************
24908 * hwrm_queue_dscp2pri_cfg *
24909 ***************************/
24912 /* hwrm_queue_dscp2pri_cfg_input (size:320b/40B) */
24913 struct hwrm_queue_dscp2pri_cfg_input {
24914 /* The HWRM command request type. */
24917 * The completion ring to send the completion event on. This should
24918 * be the NQ ID returned from the `nq_alloc` HWRM command.
24920 uint16_t cmpl_ring;
24922 * The sequence ID is used by the driver for tracking multiple
24923 * commands. This ID is treated as opaque data by the firmware and
24924 * the value is returned in the `hwrm_resp_hdr` upon completion.
24928 * The target ID of the command:
24929 * * 0x0-0xFFF8 - The function ID
24930 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
24931 * * 0xFFFD - Reserved for user-space HWRM interface
24934 uint16_t target_id;
24936 * A physical address pointer pointing to a host buffer that the
24937 * command's response data will be written. This can be either a host
24938 * physical address (HPA) or a guest physical address (GPA) and must
24939 * point to a physically contiguous block of memory.
24941 uint64_t resp_addr;
24943 * This is the host address where the 24-bits DSCP-MASK-PRI tuple
24944 * will be copied from.
24946 uint64_t src_data_addr;
24948 /* use_hw_default_pri is 1 b */
24949 #define HWRM_QUEUE_DSCP2PRI_CFG_INPUT_FLAGS_USE_HW_DEFAULT_PRI \
24953 * This bit must be '1' for the default_pri field to be
24956 #define HWRM_QUEUE_DSCP2PRI_CFG_INPUT_ENABLES_DEFAULT_PRI \
24959 * Port ID of port for which the table is being configured.
24960 * The HWRM needs to check whether this function is allowed
24961 * to configure pri2cos mapping on this port.
24965 * This is the default PRI which un-initialized DSCP values will be
24968 uint8_t default_pri;
24970 * A count of the number of DSCP-MASK-PRI tuple(s) in the data pointed
24971 * to by src_data_addr.
24973 uint16_t entry_cnt;
24974 uint8_t unused_0[4];
24977 /* hwrm_queue_dscp2pri_cfg_output (size:128b/16B) */
24978 struct hwrm_queue_dscp2pri_cfg_output {
24979 /* The specific error status for the command. */
24980 uint16_t error_code;
24981 /* The HWRM command request type. */
24983 /* The sequence ID from the original command. */
24985 /* The length of the response data in number of bytes. */
24987 uint8_t unused_0[7];
24989 * This field is used in Output records to indicate that the output
24990 * is completely written to RAM. This field should be read as '1'
24991 * to indicate that the output has been completely written.
24992 * When writing a command completion or response to an internal processor,
24993 * the order of writes has to be such that this field is written last.
24998 /*************************
24999 * hwrm_queue_mpls_qcaps *
25000 *************************/
25003 /* hwrm_queue_mpls_qcaps_input (size:192b/24B) */
25004 struct hwrm_queue_mpls_qcaps_input {
25005 /* The HWRM command request type. */
25008 * The completion ring to send the completion event on. This should
25009 * be the NQ ID returned from the `nq_alloc` HWRM command.
25011 uint16_t cmpl_ring;
25013 * The sequence ID is used by the driver for tracking multiple
25014 * commands. This ID is treated as opaque data by the firmware and
25015 * the value is returned in the `hwrm_resp_hdr` upon completion.
25019 * The target ID of the command:
25020 * * 0x0-0xFFF8 - The function ID
25021 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
25022 * * 0xFFFD - Reserved for user-space HWRM interface
25025 uint16_t target_id;
25027 * A physical address pointer pointing to a host buffer that the
25028 * command's response data will be written. This can be either a host
25029 * physical address (HPA) or a guest physical address (GPA) and must
25030 * point to a physically contiguous block of memory.
25032 uint64_t resp_addr;
25034 * Port ID of port for which the table is being configured.
25035 * The HWRM needs to check whether this function is allowed
25036 * to configure MPLS TC(EXP) to pri mapping on this port.
25039 uint8_t unused_0[7];
25042 /* hwrm_queue_mpls_qcaps_output (size:128b/16B) */
25043 struct hwrm_queue_mpls_qcaps_output {
25044 /* The specific error status for the command. */
25045 uint16_t error_code;
25046 /* The HWRM command request type. */
25048 /* The sequence ID from the original command. */
25050 /* The length of the response data in number of bytes. */
25053 * Bitmask indicating which queues can be configured by the
25054 * hwrm_queue_mplstc2pri_cfg command.
25056 * Each bit represents a specific pri where bit 0 represents
25057 * pri 0 and bit 7 represents pri 7.
25058 * # A value of 0 indicates that the pri is not configurable
25059 * by the hwrm_queue_mplstc2pri_cfg command.
25060 * # A value of 1 indicates that the pri is configurable.
25061 * # A hwrm_queue_mplstc2pri_cfg command shall return error when
25062 * trying to configure a pri that is not configurable.
25064 uint8_t queue_mplstc2pri_cfg_allowed;
25066 * This is the default PRI which un-initialized MPLS values will be
25069 uint8_t hw_default_pri;
25070 uint8_t unused_0[5];
25072 * This field is used in Output records to indicate that the output
25073 * is completely written to RAM. This field should be read as '1'
25074 * to indicate that the output has been completely written.
25075 * When writing a command completion or response to an internal processor,
25076 * the order of writes has to be such that this field is written last.
25081 /******************************
25082 * hwrm_queue_mplstc2pri_qcfg *
25083 ******************************/
25086 /* hwrm_queue_mplstc2pri_qcfg_input (size:192b/24B) */
25087 struct hwrm_queue_mplstc2pri_qcfg_input {
25088 /* The HWRM command request type. */
25091 * The completion ring to send the completion event on. This should
25092 * be the NQ ID returned from the `nq_alloc` HWRM command.
25094 uint16_t cmpl_ring;
25096 * The sequence ID is used by the driver for tracking multiple
25097 * commands. This ID is treated as opaque data by the firmware and
25098 * the value is returned in the `hwrm_resp_hdr` upon completion.
25102 * The target ID of the command:
25103 * * 0x0-0xFFF8 - The function ID
25104 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
25105 * * 0xFFFD - Reserved for user-space HWRM interface
25108 uint16_t target_id;
25110 * A physical address pointer pointing to a host buffer that the
25111 * command's response data will be written. This can be either a host
25112 * physical address (HPA) or a guest physical address (GPA) and must
25113 * point to a physically contiguous block of memory.
25115 uint64_t resp_addr;
25117 * Port ID of port for which the table is being configured.
25118 * The HWRM needs to check whether this function is allowed
25119 * to configure MPLS TC(EXP) to pri mapping on this port.
25122 uint8_t unused_0[7];
25125 /* hwrm_queue_mplstc2pri_qcfg_output (size:192b/24B) */
25126 struct hwrm_queue_mplstc2pri_qcfg_output {
25127 /* The specific error status for the command. */
25128 uint16_t error_code;
25129 /* The HWRM command request type. */
25131 /* The sequence ID from the original command. */
25133 /* The length of the response data in number of bytes. */
25136 * pri assigned to MPLS TC(EXP) 0. This value can only be changed
25137 * before traffic has started.
25138 * A value of 0xff indicates that no pri is assigned to the
25141 uint8_t tc0_pri_queue_id;
25143 * pri assigned to MPLS TC(EXP) 1. This value can only be changed
25144 * before traffic has started.
25145 * A value of 0xff indicates that no pri is assigned to the
25148 uint8_t tc1_pri_queue_id;
25150 * pri assigned to MPLS TC(EXP) 2. This value can only be changed
25151 * before traffic has started.
25152 * A value of 0xff indicates that no pri is assigned to the
25155 uint8_t tc2_pri_queue_id;
25157 * pri assigned to MPLS TC(EXP) 3. This value can only be changed
25158 * before traffic has started.
25159 * A value of 0xff indicates that no pri is assigned to the
25162 uint8_t tc3_pri_queue_id;
25164 * pri assigned to MPLS TC(EXP) 4. This value can only be changed
25165 * before traffic has started.
25166 * A value of 0xff indicates that no pri is assigned to the
25169 uint8_t tc4_pri_queue_id;
25171 * pri assigned to MPLS TC(EXP) 5. This value can only be changed
25172 * before traffic has started.
25173 * A value of 0xff indicates that no pri is assigned to the
25176 uint8_t tc5_pri_queue_id;
25178 * pri assigned to MPLS TC(EXP) 6. This value can only
25179 * be changed before traffic has started.
25180 * A value of 0xff indicates that no pri is assigned to the
25183 uint8_t tc6_pri_queue_id;
25185 * pri assigned to MPLS TC(EXP) 7. This value can only
25186 * be changed before traffic has started.
25187 * A value of 0xff indicates that no pri is assigned to the
25190 uint8_t tc7_pri_queue_id;
25191 uint8_t unused_0[7];
25193 * This field is used in Output records to indicate that the output
25194 * is completely written to RAM. This field should be read as '1'
25195 * to indicate that the output has been completely written.
25196 * When writing a command completion or response to an internal processor,
25197 * the order of writes has to be such that this field is written last.
25202 /*****************************
25203 * hwrm_queue_mplstc2pri_cfg *
25204 *****************************/
25207 /* hwrm_queue_mplstc2pri_cfg_input (size:256b/32B) */
25208 struct hwrm_queue_mplstc2pri_cfg_input {
25209 /* The HWRM command request type. */
25212 * The completion ring to send the completion event on. This should
25213 * be the NQ ID returned from the `nq_alloc` HWRM command.
25215 uint16_t cmpl_ring;
25217 * The sequence ID is used by the driver for tracking multiple
25218 * commands. This ID is treated as opaque data by the firmware and
25219 * the value is returned in the `hwrm_resp_hdr` upon completion.
25223 * The target ID of the command:
25224 * * 0x0-0xFFF8 - The function ID
25225 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
25226 * * 0xFFFD - Reserved for user-space HWRM interface
25229 uint16_t target_id;
25231 * A physical address pointer pointing to a host buffer that the
25232 * command's response data will be written. This can be either a host
25233 * physical address (HPA) or a guest physical address (GPA) and must
25234 * point to a physically contiguous block of memory.
25236 uint64_t resp_addr;
25239 * This bit must be '1' for the mplstc0_pri_queue_id field to be
25242 #define HWRM_QUEUE_MPLSTC2PRI_CFG_INPUT_ENABLES_TC0_PRI_QUEUE_ID \
25245 * This bit must be '1' for the mplstc1_pri_queue_id field to be
25248 #define HWRM_QUEUE_MPLSTC2PRI_CFG_INPUT_ENABLES_TC1_PRI_QUEUE_ID \
25251 * This bit must be '1' for the mplstc2_pri_queue_id field to be
25254 #define HWRM_QUEUE_MPLSTC2PRI_CFG_INPUT_ENABLES_TC2_PRI_QUEUE_ID \
25257 * This bit must be '1' for the mplstc3_pri_queue_id field to be
25260 #define HWRM_QUEUE_MPLSTC2PRI_CFG_INPUT_ENABLES_TC3_PRI_QUEUE_ID \
25263 * This bit must be '1' for the mplstc4_pri_queue_id field to be
25266 #define HWRM_QUEUE_MPLSTC2PRI_CFG_INPUT_ENABLES_TC4_PRI_QUEUE_ID \
25269 * This bit must be '1' for the mplstc5_pri_queue_id field to be
25272 #define HWRM_QUEUE_MPLSTC2PRI_CFG_INPUT_ENABLES_TC5_PRI_QUEUE_ID \
25275 * This bit must be '1' for the mplstc6_pri_queue_id field to be
25278 #define HWRM_QUEUE_MPLSTC2PRI_CFG_INPUT_ENABLES_TC6_PRI_QUEUE_ID \
25281 * This bit must be '1' for the mplstc7_pri_queue_id field to be
25284 #define HWRM_QUEUE_MPLSTC2PRI_CFG_INPUT_ENABLES_TC7_PRI_QUEUE_ID \
25287 * Port ID of port for which the table is being configured.
25288 * The HWRM needs to check whether this function is allowed
25289 * to configure MPLS TC(EXP)to pri mapping on this port.
25292 uint8_t unused_0[3];
25294 * pri assigned to MPLS TC(EXP) 0. This value can only
25295 * be changed before traffic has started.
25297 uint8_t tc0_pri_queue_id;
25299 * pri assigned to MPLS TC(EXP) 1. This value can only
25300 * be changed before traffic has started.
25302 uint8_t tc1_pri_queue_id;
25304 * pri assigned to MPLS TC(EXP) 2 This value can only
25305 * be changed before traffic has started.
25307 uint8_t tc2_pri_queue_id;
25309 * pri assigned to MPLS TC(EXP) 3. This value can only
25310 * be changed before traffic has started.
25312 uint8_t tc3_pri_queue_id;
25314 * pri assigned to MPLS TC(EXP) 4. This value can only
25315 * be changed before traffic has started.
25317 uint8_t tc4_pri_queue_id;
25319 * pri assigned to MPLS TC(EXP) 5. This value can only
25320 * be changed before traffic has started.
25322 uint8_t tc5_pri_queue_id;
25324 * pri assigned to MPLS TC(EXP) 6. This value can only
25325 * be changed before traffic has started.
25327 uint8_t tc6_pri_queue_id;
25329 * pri assigned to MPLS TC(EXP) 7. This value can only
25330 * be changed before traffic has started.
25332 uint8_t tc7_pri_queue_id;
25335 /* hwrm_queue_mplstc2pri_cfg_output (size:128b/16B) */
25336 struct hwrm_queue_mplstc2pri_cfg_output {
25337 /* The specific error status for the command. */
25338 uint16_t error_code;
25339 /* The HWRM command request type. */
25341 /* The sequence ID from the original command. */
25343 /* The length of the response data in number of bytes. */
25345 uint8_t unused_0[7];
25347 * This field is used in Output records to indicate that the output
25348 * is completely written to RAM. This field should be read as '1'
25349 * to indicate that the output has been completely written.
25350 * When writing a command completion or response to an internal processor,
25351 * the order of writes has to be such that this field is written last.
25356 /*******************
25357 * hwrm_vnic_alloc *
25358 *******************/
25361 /* hwrm_vnic_alloc_input (size:192b/24B) */
25362 struct hwrm_vnic_alloc_input {
25363 /* The HWRM command request type. */
25366 * The completion ring to send the completion event on. This should
25367 * be the NQ ID returned from the `nq_alloc` HWRM command.
25369 uint16_t cmpl_ring;
25371 * The sequence ID is used by the driver for tracking multiple
25372 * commands. This ID is treated as opaque data by the firmware and
25373 * the value is returned in the `hwrm_resp_hdr` upon completion.
25377 * The target ID of the command:
25378 * * 0x0-0xFFF8 - The function ID
25379 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
25380 * * 0xFFFD - Reserved for user-space HWRM interface
25383 uint16_t target_id;
25385 * A physical address pointer pointing to a host buffer that the
25386 * command's response data will be written. This can be either a host
25387 * physical address (HPA) or a guest physical address (GPA) and must
25388 * point to a physically contiguous block of memory.
25390 uint64_t resp_addr;
25393 * When this bit is '1', this VNIC is requested to
25394 * be the default VNIC for this function.
25396 #define HWRM_VNIC_ALLOC_INPUT_FLAGS_DEFAULT UINT32_C(0x1)
25397 uint8_t unused_0[4];
25400 /* hwrm_vnic_alloc_output (size:128b/16B) */
25401 struct hwrm_vnic_alloc_output {
25402 /* The specific error status for the command. */
25403 uint16_t error_code;
25404 /* The HWRM command request type. */
25406 /* The sequence ID from the original command. */
25408 /* The length of the response data in number of bytes. */
25410 /* Logical vnic ID */
25412 uint8_t unused_0[3];
25414 * This field is used in Output records to indicate that the output
25415 * is completely written to RAM. This field should be read as '1'
25416 * to indicate that the output has been completely written.
25417 * When writing a command completion or response to an internal processor,
25418 * the order of writes has to be such that this field is written last.
25423 /******************
25425 ******************/
25428 /* hwrm_vnic_free_input (size:192b/24B) */
25429 struct hwrm_vnic_free_input {
25430 /* The HWRM command request type. */
25433 * The completion ring to send the completion event on. This should
25434 * be the NQ ID returned from the `nq_alloc` HWRM command.
25436 uint16_t cmpl_ring;
25438 * The sequence ID is used by the driver for tracking multiple
25439 * commands. This ID is treated as opaque data by the firmware and
25440 * the value is returned in the `hwrm_resp_hdr` upon completion.
25444 * The target ID of the command:
25445 * * 0x0-0xFFF8 - The function ID
25446 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
25447 * * 0xFFFD - Reserved for user-space HWRM interface
25450 uint16_t target_id;
25452 * A physical address pointer pointing to a host buffer that the
25453 * command's response data will be written. This can be either a host
25454 * physical address (HPA) or a guest physical address (GPA) and must
25455 * point to a physically contiguous block of memory.
25457 uint64_t resp_addr;
25458 /* Logical vnic ID */
25460 uint8_t unused_0[4];
25463 /* hwrm_vnic_free_output (size:128b/16B) */
25464 struct hwrm_vnic_free_output {
25465 /* The specific error status for the command. */
25466 uint16_t error_code;
25467 /* The HWRM command request type. */
25469 /* The sequence ID from the original command. */
25471 /* The length of the response data in number of bytes. */
25473 uint8_t unused_0[7];
25475 * This field is used in Output records to indicate that the output
25476 * is completely written to RAM. This field should be read as '1'
25477 * to indicate that the output has been completely written.
25478 * When writing a command completion or response to an internal processor,
25479 * the order of writes has to be such that this field is written last.
25489 /* hwrm_vnic_cfg_input (size:384b/48B) */
25490 struct hwrm_vnic_cfg_input {
25491 /* The HWRM command request type. */
25494 * The completion ring to send the completion event on. This should
25495 * be the NQ ID returned from the `nq_alloc` HWRM command.
25497 uint16_t cmpl_ring;
25499 * The sequence ID is used by the driver for tracking multiple
25500 * commands. This ID is treated as opaque data by the firmware and
25501 * the value is returned in the `hwrm_resp_hdr` upon completion.
25505 * The target ID of the command:
25506 * * 0x0-0xFFF8 - The function ID
25507 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
25508 * * 0xFFFD - Reserved for user-space HWRM interface
25511 uint16_t target_id;
25513 * A physical address pointer pointing to a host buffer that the
25514 * command's response data will be written. This can be either a host
25515 * physical address (HPA) or a guest physical address (GPA) and must
25516 * point to a physically contiguous block of memory.
25518 uint64_t resp_addr;
25521 * When this bit is '1', the VNIC is requested to
25522 * be the default VNIC for the function.
25524 #define HWRM_VNIC_CFG_INPUT_FLAGS_DEFAULT \
25527 * When this bit is '1', the VNIC is being configured to
25528 * strip VLAN in the RX path.
25529 * If set to '0', then VLAN stripping is disabled on
25532 #define HWRM_VNIC_CFG_INPUT_FLAGS_VLAN_STRIP_MODE \
25535 * When this bit is '1', the VNIC is being configured to
25536 * buffer receive packets in the hardware until the host
25537 * posts new receive buffers.
25538 * If set to '0', then bd_stall is being configured to be
25539 * disabled on this VNIC.
25541 #define HWRM_VNIC_CFG_INPUT_FLAGS_BD_STALL_MODE \
25544 * When this bit is '1', the VNIC is being configured to
25545 * receive both RoCE and non-RoCE traffic.
25546 * If set to '0', then this VNIC is not configured to be
25547 * operating in dual VNIC mode.
25549 #define HWRM_VNIC_CFG_INPUT_FLAGS_ROCE_DUAL_VNIC_MODE \
25552 * When this flag is set to '1', the VNIC is requested to
25553 * be configured to receive only RoCE traffic.
25554 * If this flag is set to '0', then this flag shall be
25555 * ignored by the HWRM.
25556 * If roce_dual_vnic_mode flag is set to '1'
25557 * or roce_mirroring_capable_vnic_mode flag to 1,
25558 * then the HWRM client shall not set this flag to '1'.
25560 #define HWRM_VNIC_CFG_INPUT_FLAGS_ROCE_ONLY_VNIC_MODE \
25563 * When a VNIC uses one destination ring group for certain
25564 * application (e.g. Receive Flow Steering) where
25565 * exact match is used to direct packets to a VNIC with one
25566 * destination ring group only, there is no need to configure
25567 * RSS indirection table for that VNIC as only one destination
25568 * ring group is used.
25570 * This flag is used to enable a mode where
25571 * RSS is enabled in the VNIC using a RSS context
25572 * for computing RSS hash but the RSS indirection table is
25573 * not configured using hwrm_vnic_rss_cfg.
25575 * If this mode is enabled, then the driver should not program
25576 * RSS indirection table for the RSS context that is used for
25577 * computing RSS hash only.
25579 #define HWRM_VNIC_CFG_INPUT_FLAGS_RSS_DFLT_CR_MODE \
25582 * When this bit is '1', the VNIC is being configured to
25583 * receive both RoCE and non-RoCE traffic, but forward only the
25584 * RoCE traffic further. Also, RoCE traffic can be mirrored to
25587 #define HWRM_VNIC_CFG_INPUT_FLAGS_ROCE_MIRRORING_CAPABLE_VNIC_MODE \
25591 * This bit must be '1' for the dflt_ring_grp field to be
25594 #define HWRM_VNIC_CFG_INPUT_ENABLES_DFLT_RING_GRP \
25597 * This bit must be '1' for the rss_rule field to be
25600 #define HWRM_VNIC_CFG_INPUT_ENABLES_RSS_RULE \
25603 * This bit must be '1' for the cos_rule field to be
25606 #define HWRM_VNIC_CFG_INPUT_ENABLES_COS_RULE \
25609 * This bit must be '1' for the lb_rule field to be
25612 #define HWRM_VNIC_CFG_INPUT_ENABLES_LB_RULE \
25615 * This bit must be '1' for the mru field to be
25618 #define HWRM_VNIC_CFG_INPUT_ENABLES_MRU \
25621 * This bit must be '1' for the default_rx_ring_id field to be
25624 #define HWRM_VNIC_CFG_INPUT_ENABLES_DEFAULT_RX_RING_ID \
25627 * This bit must be '1' for the default_cmpl_ring_id field to be
25630 #define HWRM_VNIC_CFG_INPUT_ENABLES_DEFAULT_CMPL_RING_ID \
25632 /* This bit must be '1' for the queue_id field to be configured. */
25633 #define HWRM_VNIC_CFG_INPUT_ENABLES_QUEUE_ID \
25635 /* This bit must be '1' for the rx_csum_v2_mode field to be configured. */
25636 #define HWRM_VNIC_CFG_INPUT_ENABLES_RX_CSUM_V2_MODE \
25638 /* Logical vnic ID */
25641 * Default Completion ring for the VNIC. This ring will
25642 * be chosen if packet does not match any RSS rules and if
25643 * there is no COS rule.
25645 uint16_t dflt_ring_grp;
25647 * RSS ID for RSS rule/table structure. 0xFF... (All Fs) if
25648 * there is no RSS rule.
25652 * RSS ID for COS rule/table structure. 0xFF... (All Fs) if
25653 * there is no COS rule.
25657 * RSS ID for load balancing rule/table structure.
25658 * 0xFF... (All Fs) if there is no LB rule.
25662 * The maximum receive unit of the vnic.
25663 * Each vnic is associated with a function.
25664 * The vnic mru value overwrites the mru setting of the
25665 * associated function.
25666 * The HWRM shall make sure that vnic mru does not exceed
25667 * the mru of the port the function is associated with.
25671 * Default Rx ring for the VNIC. This ring will
25672 * be chosen if packet does not match any RSS rules.
25673 * The aggregation ring associated with the Rx ring is
25674 * implied based on the Rx ring specified when the
25675 * aggregation ring was allocated.
25677 uint16_t default_rx_ring_id;
25679 * Default completion ring for the VNIC. This ring will
25680 * be chosen if packet does not match any RSS rules.
25682 uint16_t default_cmpl_ring_id;
25684 * When specified, only incoming packets classified to the specified CoS
25685 * queue ID will be arriving on this VNIC. Packet priority to CoS mapping
25686 * rules can be specified using HWRM_QUEUE_PRI2COS_CFG. In this mode,
25687 * ntuple filters with VNIC destination specified are invalid since they
25688 * conflict with the the CoS to VNIC steering rules in this mode.
25690 * If this field is not specified, packet to VNIC steering will be
25691 * subject to the standard L2 filter rules and any additional ntuple
25692 * filter rules with destination VNIC specified.
25696 * If the device supports the RX V2 and RX TPA start V2 completion
25697 * records as indicated by the HWRM_VNIC_QCAPS command, this field is
25698 * used to specify the two RX checksum modes supported by these
25699 * completion records.
25701 uint8_t rx_csum_v2_mode;
25703 * When configured with this checksum mode, the number of header
25704 * groups in the delivered packet with a valid IP checksum and
25705 * the number of header groups in the delivered packet with a valid
25706 * L4 checksum are reported. Valid checksums are counted from the
25707 * outermost header group to the innermost header group, stopping at
25708 * the first error. This is the default checksum mode supported if
25709 * the driver doesn't explicitly configure the RX checksum mode.
25711 #define HWRM_VNIC_CFG_INPUT_RX_CSUM_V2_MODE_DEFAULT UINT32_C(0x0)
25713 * When configured with this checksum mode, the checksum status is
25714 * reported using 'all ok' mode. In the RX completion record, one
25715 * bit indicates if the IP checksum is valid for all the parsed
25716 * header groups with an IP checksum. Another bit indicates if the
25717 * L4 checksum is valid for all the parsed header groups with an L4
25718 * checksum. The number of header groups that were parsed by the
25719 * chip and passed in the delivered packet is also reported.
25721 #define HWRM_VNIC_CFG_INPUT_RX_CSUM_V2_MODE_ALL_OK UINT32_C(0x1)
25723 * Any rx_csum_v2_mode value larger than or equal to this is not
25726 #define HWRM_VNIC_CFG_INPUT_RX_CSUM_V2_MODE_MAX UINT32_C(0x2)
25727 #define HWRM_VNIC_CFG_INPUT_RX_CSUM_V2_MODE_LAST \
25728 HWRM_VNIC_CFG_INPUT_RX_CSUM_V2_MODE_MAX
25729 uint8_t unused0[5];
25732 /* hwrm_vnic_cfg_output (size:128b/16B) */
25733 struct hwrm_vnic_cfg_output {
25734 /* The specific error status for the command. */
25735 uint16_t error_code;
25736 /* The HWRM command request type. */
25738 /* The sequence ID from the original command. */
25740 /* The length of the response data in number of bytes. */
25742 uint8_t unused_0[7];
25744 * This field is used in Output records to indicate that the output
25745 * is completely written to RAM. This field should be read as '1'
25746 * to indicate that the output has been completely written.
25747 * When writing a command completion or response to an internal processor,
25748 * the order of writes has to be such that this field is written last.
25753 /******************
25755 ******************/
25758 /* hwrm_vnic_qcfg_input (size:256b/32B) */
25759 struct hwrm_vnic_qcfg_input {
25760 /* The HWRM command request type. */
25763 * The completion ring to send the completion event on. This should
25764 * be the NQ ID returned from the `nq_alloc` HWRM command.
25766 uint16_t cmpl_ring;
25768 * The sequence ID is used by the driver for tracking multiple
25769 * commands. This ID is treated as opaque data by the firmware and
25770 * the value is returned in the `hwrm_resp_hdr` upon completion.
25774 * The target ID of the command:
25775 * * 0x0-0xFFF8 - The function ID
25776 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
25777 * * 0xFFFD - Reserved for user-space HWRM interface
25780 uint16_t target_id;
25782 * A physical address pointer pointing to a host buffer that the
25783 * command's response data will be written. This can be either a host
25784 * physical address (HPA) or a guest physical address (GPA) and must
25785 * point to a physically contiguous block of memory.
25787 uint64_t resp_addr;
25790 * This bit must be '1' for the vf_id_valid field to be
25793 #define HWRM_VNIC_QCFG_INPUT_ENABLES_VF_ID_VALID UINT32_C(0x1)
25794 /* Logical vnic ID */
25796 /* ID of Virtual Function whose VNIC resource is being queried. */
25798 uint8_t unused_0[6];
25801 /* hwrm_vnic_qcfg_output (size:256b/32B) */
25802 struct hwrm_vnic_qcfg_output {
25803 /* The specific error status for the command. */
25804 uint16_t error_code;
25805 /* The HWRM command request type. */
25807 /* The sequence ID from the original command. */
25809 /* The length of the response data in number of bytes. */
25811 /* Default Completion ring for the VNIC. */
25812 uint16_t dflt_ring_grp;
25814 * RSS ID for RSS rule/table structure. 0xFF... (All Fs) if
25815 * there is no RSS rule.
25819 * RSS ID for COS rule/table structure. 0xFF... (All Fs) if
25820 * there is no COS rule.
25824 * RSS ID for load balancing rule/table structure.
25825 * 0xFF... (All Fs) if there is no LB rule.
25828 /* The maximum receive unit of the vnic. */
25830 uint8_t unused_0[2];
25833 * When this bit is '1', the VNIC is the default VNIC for
25836 #define HWRM_VNIC_QCFG_OUTPUT_FLAGS_DEFAULT \
25839 * When this bit is '1', the VNIC is configured to
25840 * strip VLAN in the RX path.
25841 * If set to '0', then VLAN stripping is disabled on
25844 #define HWRM_VNIC_QCFG_OUTPUT_FLAGS_VLAN_STRIP_MODE \
25847 * When this bit is '1', the VNIC is configured to
25848 * buffer receive packets in the hardware until the host
25849 * posts new receive buffers.
25850 * If set to '0', then bd_stall is disabled on
25853 #define HWRM_VNIC_QCFG_OUTPUT_FLAGS_BD_STALL_MODE \
25856 * When this bit is '1', the VNIC is configured to
25857 * receive both RoCE and non-RoCE traffic.
25858 * If set to '0', then this VNIC is not configured to
25859 * operate in dual VNIC mode.
25861 #define HWRM_VNIC_QCFG_OUTPUT_FLAGS_ROCE_DUAL_VNIC_MODE \
25864 * When this flag is set to '1', the VNIC is configured to
25865 * receive only RoCE traffic.
25866 * When this flag is set to '0', the VNIC is not configured
25867 * to receive only RoCE traffic.
25868 * If roce_dual_vnic_mode flag and this flag both are set
25869 * to '1', then it is an invalid configuration of the
25870 * VNIC. The HWRM should not allow that type of
25871 * mis-configuration by HWRM clients.
25873 #define HWRM_VNIC_QCFG_OUTPUT_FLAGS_ROCE_ONLY_VNIC_MODE \
25876 * When a VNIC uses one destination ring group for certain
25877 * application (e.g. Receive Flow Steering) where
25878 * exact match is used to direct packets to a VNIC with one
25879 * destination ring group only, there is no need to configure
25880 * RSS indirection table for that VNIC as only one destination
25881 * ring group is used.
25883 * When this bit is set to '1', then the VNIC is enabled in a
25884 * mode where RSS is enabled in the VNIC using a RSS context
25885 * for computing RSS hash but the RSS indirection table is
25888 #define HWRM_VNIC_QCFG_OUTPUT_FLAGS_RSS_DFLT_CR_MODE \
25891 * When this bit is '1', the VNIC is configured to
25892 * receive both RoCE and non-RoCE traffic, but forward only
25893 * RoCE traffic further. Also RoCE traffic can be mirrored to
25896 #define HWRM_VNIC_QCFG_OUTPUT_FLAGS_ROCE_MIRRORING_CAPABLE_VNIC_MODE \
25899 * When returned with a valid CoS Queue id, the CoS Queue/VNIC association
25900 * is valid. Otherwise it will return 0xFFFF to indicate no VNIC/CoS
25901 * queue association.
25905 * If the device supports the RX V2 and RX TPA start V2 completion
25906 * records as indicated by the HWRM_VNIC_QCAPS command, this field is
25907 * used to specify the current RX checksum mode configured for all the
25908 * RX rings of a VNIC.
25910 uint8_t rx_csum_v2_mode;
25912 * This value indicates that the VNIC is configured to use the
25913 * default RX checksum mode for all the rings associated with this
25916 #define HWRM_VNIC_QCFG_OUTPUT_RX_CSUM_V2_MODE_DEFAULT UINT32_C(0x0)
25918 * This value indicates that the VNIC is configured to use the RX
25919 * checksum ‘all_ok’ mode for all the rings associated with this
25922 #define HWRM_VNIC_QCFG_OUTPUT_RX_CSUM_V2_MODE_ALL_OK UINT32_C(0x1)
25924 * Any rx_csum_v2_mode value larger than or equal to this is not
25927 #define HWRM_VNIC_QCFG_OUTPUT_RX_CSUM_V2_MODE_MAX UINT32_C(0x2)
25928 #define HWRM_VNIC_QCFG_OUTPUT_RX_CSUM_V2_MODE_LAST \
25929 HWRM_VNIC_QCFG_OUTPUT_RX_CSUM_V2_MODE_MAX
25930 uint8_t unused_1[4];
25932 * This field is used in Output records to indicate that the output
25933 * is completely written to RAM. This field should be read as '1'
25934 * to indicate that the output has been completely written.
25935 * When writing a command completion or response to an internal processor,
25936 * the order of writes has to be such that this field is written last.
25941 /*******************
25942 * hwrm_vnic_qcaps *
25943 *******************/
25946 /* hwrm_vnic_qcaps_input (size:192b/24B) */
25947 struct hwrm_vnic_qcaps_input {
25948 /* The HWRM command request type. */
25951 * The completion ring to send the completion event on. This should
25952 * be the NQ ID returned from the `nq_alloc` HWRM command.
25954 uint16_t cmpl_ring;
25956 * The sequence ID is used by the driver for tracking multiple
25957 * commands. This ID is treated as opaque data by the firmware and
25958 * the value is returned in the `hwrm_resp_hdr` upon completion.
25962 * The target ID of the command:
25963 * * 0x0-0xFFF8 - The function ID
25964 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
25965 * * 0xFFFD - Reserved for user-space HWRM interface
25968 uint16_t target_id;
25970 * A physical address pointer pointing to a host buffer that the
25971 * command's response data will be written. This can be either a host
25972 * physical address (HPA) or a guest physical address (GPA) and must
25973 * point to a physically contiguous block of memory.
25975 uint64_t resp_addr;
25977 uint8_t unused_0[4];
25980 /* hwrm_vnic_qcaps_output (size:192b/24B) */
25981 struct hwrm_vnic_qcaps_output {
25982 /* The specific error status for the command. */
25983 uint16_t error_code;
25984 /* The HWRM command request type. */
25986 /* The sequence ID from the original command. */
25988 /* The length of the response data in number of bytes. */
25990 /* The maximum receive unit that is settable on a vnic. */
25992 uint8_t unused_0[2];
25995 #define HWRM_VNIC_QCAPS_OUTPUT_FLAGS_UNUSED \
25998 * When this bit is '1', the capability of stripping VLAN in
25999 * the RX path is supported on VNIC(s).
26000 * If set to '0', then VLAN stripping capability is
26001 * not supported on VNIC(s).
26003 #define HWRM_VNIC_QCAPS_OUTPUT_FLAGS_VLAN_STRIP_CAP \
26006 * When this bit is '1', the capability to buffer receive
26007 * packets in the hardware until the host posts new receive buffers
26008 * is supported on VNIC(s).
26009 * If set to '0', then bd_stall capability is not supported
26012 #define HWRM_VNIC_QCAPS_OUTPUT_FLAGS_BD_STALL_CAP \
26015 * When this bit is '1', the capability to
26016 * receive both RoCE and non-RoCE traffic on VNIC(s) is
26018 * If set to '0', then the capability to receive
26019 * both RoCE and non-RoCE traffic on VNIC(s) is
26022 #define HWRM_VNIC_QCAPS_OUTPUT_FLAGS_ROCE_DUAL_VNIC_CAP \
26025 * When this bit is set to '1', the capability to configure
26026 * a VNIC to receive only RoCE traffic is supported.
26027 * When this flag is set to '0', the VNIC capability to
26028 * configure to receive only RoCE traffic is not supported.
26030 #define HWRM_VNIC_QCAPS_OUTPUT_FLAGS_ROCE_ONLY_VNIC_CAP \
26033 * When this bit is set to '1', then the capability to enable
26034 * a VNIC in a mode where RSS context without configuring
26035 * RSS indirection table is supported (for RSS hash computation).
26036 * When this bit is set to '0', then a VNIC can not be configured
26037 * with a mode to enable RSS context without configuring RSS
26038 * indirection table.
26040 #define HWRM_VNIC_QCAPS_OUTPUT_FLAGS_RSS_DFLT_CR_CAP \
26043 * When this bit is '1', the capability to
26044 * mirror the the RoCE traffic is supported.
26045 * If set to '0', then the capability to mirror the
26046 * RoCE traffic is not supported.
26048 #define HWRM_VNIC_QCAPS_OUTPUT_FLAGS_ROCE_MIRRORING_CAPABLE_VNIC_CAP \
26051 * When this bit is '1', the outermost RSS hashing capability
26052 * is supported. If set to '0', then the outermost RSS hashing
26053 * capability is not supported.
26055 #define HWRM_VNIC_QCAPS_OUTPUT_FLAGS_OUTERMOST_RSS_CAP \
26058 * When this bit is '1', it indicates that firmware supports the
26059 * ability to steer incoming packets from one CoS queue to one
26060 * VNIC. This optional feature can then be enabled
26061 * using HWRM_VNIC_CFG on any VNIC. This feature is only
26062 * available when NVM option “enable_cos_classfication” is set
26063 * to 1. If set to '0', firmware does not support this feature.
26065 #define HWRM_VNIC_QCAPS_OUTPUT_FLAGS_COS_ASSIGNMENT_CAP \
26068 * When this bit is '1', it indicates that HW and firmware supports
26069 * the use of RX V2 and RX TPA start V2 completion records for all
26070 * the RX rings of a VNIC. Once set, this feature is mandatory to
26071 * be used for the RX rings of the VNIC. Additionally, two new RX
26072 * checksum features supported by these ompletion records can be
26073 * configured using the HWRM_VNIC_CFG on a VNIC. If set to '0', the
26074 * HW and the firmware does not support this feature.
26076 #define HWRM_VNIC_QCAPS_OUTPUT_FLAGS_RX_CMPL_V2_CAP \
26079 * This field advertises the maximum concurrent TPA aggregations
26080 * supported by the VNIC on new devices that support TPA v2.
26081 * '0' means that TPA v2 is not supported.
26083 uint16_t max_aggs_supported;
26084 uint8_t unused_1[5];
26086 * This field is used in Output records to indicate that the output
26087 * is completely written to RAM. This field should be read as '1'
26088 * to indicate that the output has been completely written.
26089 * When writing a command completion or response to an internal processor,
26090 * the order of writes has to be such that this field is written last.
26095 /*********************
26096 * hwrm_vnic_tpa_cfg *
26097 *********************/
26100 /* hwrm_vnic_tpa_cfg_input (size:320b/40B) */
26101 struct hwrm_vnic_tpa_cfg_input {
26102 /* The HWRM command request type. */
26105 * The completion ring to send the completion event on. This should
26106 * be the NQ ID returned from the `nq_alloc` HWRM command.
26108 uint16_t cmpl_ring;
26110 * The sequence ID is used by the driver for tracking multiple
26111 * commands. This ID is treated as opaque data by the firmware and
26112 * the value is returned in the `hwrm_resp_hdr` upon completion.
26116 * The target ID of the command:
26117 * * 0x0-0xFFF8 - The function ID
26118 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
26119 * * 0xFFFD - Reserved for user-space HWRM interface
26122 uint16_t target_id;
26124 * A physical address pointer pointing to a host buffer that the
26125 * command's response data will be written. This can be either a host
26126 * physical address (HPA) or a guest physical address (GPA) and must
26127 * point to a physically contiguous block of memory.
26129 uint64_t resp_addr;
26132 * When this bit is '1', the VNIC shall be configured to
26133 * perform transparent packet aggregation (TPA) of
26134 * non-tunneled TCP packets.
26136 #define HWRM_VNIC_TPA_CFG_INPUT_FLAGS_TPA \
26139 * When this bit is '1', the VNIC shall be configured to
26140 * perform transparent packet aggregation (TPA) of
26141 * tunneled TCP packets.
26143 #define HWRM_VNIC_TPA_CFG_INPUT_FLAGS_ENCAP_TPA \
26146 * When this bit is '1', the VNIC shall be configured to
26147 * perform transparent packet aggregation (TPA) according
26148 * to Windows Receive Segment Coalescing (RSC) rules.
26150 #define HWRM_VNIC_TPA_CFG_INPUT_FLAGS_RSC_WND_UPDATE \
26153 * When this bit is '1', the VNIC shall be configured to
26154 * perform transparent packet aggregation (TPA) according
26155 * to Linux Generic Receive Offload (GRO) rules.
26157 #define HWRM_VNIC_TPA_CFG_INPUT_FLAGS_GRO \
26160 * When this bit is '1', the VNIC shall be configured to
26161 * perform transparent packet aggregation (TPA) for TCP
26162 * packets with IP ECN set to non-zero.
26164 #define HWRM_VNIC_TPA_CFG_INPUT_FLAGS_AGG_WITH_ECN \
26167 * When this bit is '1', the VNIC shall be configured to
26168 * perform transparent packet aggregation (TPA) for
26169 * GRE tunneled TCP packets only if all packets have the
26170 * same GRE sequence.
26172 #define HWRM_VNIC_TPA_CFG_INPUT_FLAGS_AGG_WITH_SAME_GRE_SEQ \
26175 * When this bit is '1' and the GRO mode is enabled,
26176 * the VNIC shall be configured to
26177 * perform transparent packet aggregation (TPA) for
26178 * TCP/IPv4 packets with consecutively increasing IPIDs.
26179 * In other words, the last packet that is being
26180 * aggregated to an already existing aggregation context
26181 * shall have IPID 1 more than the IPID of the last packet
26182 * that was aggregated in that aggregation context.
26184 #define HWRM_VNIC_TPA_CFG_INPUT_FLAGS_GRO_IPID_CHECK \
26187 * When this bit is '1' and the GRO mode is enabled,
26188 * the VNIC shall be configured to
26189 * perform transparent packet aggregation (TPA) for
26190 * TCP packets with the same TTL (IPv4) or Hop limit (IPv6)
26193 #define HWRM_VNIC_TPA_CFG_INPUT_FLAGS_GRO_TTL_CHECK \
26196 * When this bit is '1' and the GRO mode is enabled,
26197 * the VNIC shall DMA payload data using GRO rules.
26198 * When this bit is '0', the VNIC shall DMA payload data
26199 * using the more efficient LRO rules of filling all
26200 * aggregation buffers.
26202 #define HWRM_VNIC_TPA_CFG_INPUT_FLAGS_AGG_PACK_AS_GRO \
26206 * This bit must be '1' for the max_agg_segs field to be
26209 #define HWRM_VNIC_TPA_CFG_INPUT_ENABLES_MAX_AGG_SEGS UINT32_C(0x1)
26211 * This bit must be '1' for the max_aggs field to be
26214 #define HWRM_VNIC_TPA_CFG_INPUT_ENABLES_MAX_AGGS UINT32_C(0x2)
26216 * This bit must be '1' for the max_agg_timer field to be
26219 #define HWRM_VNIC_TPA_CFG_INPUT_ENABLES_MAX_AGG_TIMER UINT32_C(0x4)
26220 /* deprecated bit. Do not use!!! */
26221 #define HWRM_VNIC_TPA_CFG_INPUT_ENABLES_MIN_AGG_LEN UINT32_C(0x8)
26222 /* Logical vnic ID */
26225 * This is the maximum number of TCP segments that can
26226 * be aggregated (unit is Log2). Max value is 31. On new
26227 * devices supporting TPA v2, the unit is multiples of 4 and
26228 * valid values are > 0 and <= 63.
26230 uint16_t max_agg_segs;
26232 #define HWRM_VNIC_TPA_CFG_INPUT_MAX_AGG_SEGS_1 UINT32_C(0x0)
26234 #define HWRM_VNIC_TPA_CFG_INPUT_MAX_AGG_SEGS_2 UINT32_C(0x1)
26236 #define HWRM_VNIC_TPA_CFG_INPUT_MAX_AGG_SEGS_4 UINT32_C(0x2)
26238 #define HWRM_VNIC_TPA_CFG_INPUT_MAX_AGG_SEGS_8 UINT32_C(0x3)
26239 /* Any segment size larger than this is not valid */
26240 #define HWRM_VNIC_TPA_CFG_INPUT_MAX_AGG_SEGS_MAX UINT32_C(0x1f)
26241 #define HWRM_VNIC_TPA_CFG_INPUT_MAX_AGG_SEGS_LAST \
26242 HWRM_VNIC_TPA_CFG_INPUT_MAX_AGG_SEGS_MAX
26244 * This is the maximum number of aggregations this VNIC is
26245 * allowed (unit is Log2). Max value is 7. On new devices
26246 * supporting TPA v2, this is in unit of 1 and must be > 0
26247 * and <= max_aggs_supported in the hwrm_vnic_qcaps response
26248 * to enable TPA v2.
26251 /* 1 aggregation */
26252 #define HWRM_VNIC_TPA_CFG_INPUT_MAX_AGGS_1 UINT32_C(0x0)
26253 /* 2 aggregations */
26254 #define HWRM_VNIC_TPA_CFG_INPUT_MAX_AGGS_2 UINT32_C(0x1)
26255 /* 4 aggregations */
26256 #define HWRM_VNIC_TPA_CFG_INPUT_MAX_AGGS_4 UINT32_C(0x2)
26257 /* 8 aggregations */
26258 #define HWRM_VNIC_TPA_CFG_INPUT_MAX_AGGS_8 UINT32_C(0x3)
26259 /* 16 aggregations */
26260 #define HWRM_VNIC_TPA_CFG_INPUT_MAX_AGGS_16 UINT32_C(0x4)
26261 /* Any aggregation size larger than this is not valid */
26262 #define HWRM_VNIC_TPA_CFG_INPUT_MAX_AGGS_MAX UINT32_C(0x7)
26263 #define HWRM_VNIC_TPA_CFG_INPUT_MAX_AGGS_LAST \
26264 HWRM_VNIC_TPA_CFG_INPUT_MAX_AGGS_MAX
26265 uint8_t unused_0[2];
26267 * This is the maximum amount of time allowed for
26268 * an aggregation context to complete after it was initiated.
26270 uint32_t max_agg_timer;
26272 * This is the minimum amount of payload length required to
26273 * start an aggregation context. This field is deprecated and
26274 * should be set to 0. The minimum length is set by firmware
26275 * and can be queried using hwrm_vnic_tpa_qcfg.
26277 uint32_t min_agg_len;
26280 /* hwrm_vnic_tpa_cfg_output (size:128b/16B) */
26281 struct hwrm_vnic_tpa_cfg_output {
26282 /* The specific error status for the command. */
26283 uint16_t error_code;
26284 /* The HWRM command request type. */
26286 /* The sequence ID from the original command. */
26288 /* The length of the response data in number of bytes. */
26290 uint8_t unused_0[7];
26292 * This field is used in Output records to indicate that the output
26293 * is completely written to RAM. This field should be read as '1'
26294 * to indicate that the output has been completely written.
26295 * When writing a command completion or response to an internal processor,
26296 * the order of writes has to be such that this field is written last.
26301 /*********************
26302 * hwrm_vnic_rss_cfg *
26303 *********************/
26306 /* hwrm_vnic_rss_cfg_input (size:384b/48B) */
26307 struct hwrm_vnic_rss_cfg_input {
26308 /* The HWRM command request type. */
26311 * The completion ring to send the completion event on. This should
26312 * be the NQ ID returned from the `nq_alloc` HWRM command.
26314 uint16_t cmpl_ring;
26316 * The sequence ID is used by the driver for tracking multiple
26317 * commands. This ID is treated as opaque data by the firmware and
26318 * the value is returned in the `hwrm_resp_hdr` upon completion.
26322 * The target ID of the command:
26323 * * 0x0-0xFFF8 - The function ID
26324 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
26325 * * 0xFFFD - Reserved for user-space HWRM interface
26328 uint16_t target_id;
26330 * A physical address pointer pointing to a host buffer that the
26331 * command's response data will be written. This can be either a host
26332 * physical address (HPA) or a guest physical address (GPA) and must
26333 * point to a physically contiguous block of memory.
26335 uint64_t resp_addr;
26336 uint32_t hash_type;
26338 * When this bit is '1', the RSS hash shall be computed
26339 * over source and destination IPv4 addresses of IPv4
26342 #define HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV4 UINT32_C(0x1)
26344 * When this bit is '1', the RSS hash shall be computed
26345 * over source/destination IPv4 addresses and
26346 * source/destination ports of TCP/IPv4 packets.
26348 #define HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV4 UINT32_C(0x2)
26350 * When this bit is '1', the RSS hash shall be computed
26351 * over source/destination IPv4 addresses and
26352 * source/destination ports of UDP/IPv4 packets.
26354 #define HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV4 UINT32_C(0x4)
26356 * When this bit is '1', the RSS hash shall be computed
26357 * over source and destination IPv4 addresses of IPv6
26360 #define HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV6 UINT32_C(0x8)
26362 * When this bit is '1', the RSS hash shall be computed
26363 * over source/destination IPv6 addresses and
26364 * source/destination ports of TCP/IPv6 packets.
26366 #define HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV6 UINT32_C(0x10)
26368 * When this bit is '1', the RSS hash shall be computed
26369 * over source/destination IPv6 addresses and
26370 * source/destination ports of UDP/IPv6 packets.
26372 #define HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV6 UINT32_C(0x20)
26373 /* VNIC ID of VNIC associated with RSS table being configured. */
26376 * Specifies which VNIC ring table pair to configure.
26377 * Valid values range from 0 to 7.
26379 uint8_t ring_table_pair_index;
26380 /* Flags to specify different RSS hash modes. */
26381 uint8_t hash_mode_flags;
26383 * When this bit is '1', it indicates using current RSS
26384 * hash mode setting configured in the device.
26386 #define HWRM_VNIC_RSS_CFG_INPUT_HASH_MODE_FLAGS_DEFAULT \
26389 * When this bit is '1', it indicates requesting support of
26390 * RSS hashing over innermost 4 tuples {l3.src, l3.dest,
26391 * l4.src, l4.dest} for tunnel packets. For none-tunnel
26392 * packets, the RSS hash is computed over the normal
26393 * src/dest l3 and src/dest l4 headers.
26395 #define HWRM_VNIC_RSS_CFG_INPUT_HASH_MODE_FLAGS_INNERMOST_4 \
26398 * When this bit is '1', it indicates requesting support of
26399 * RSS hashing over innermost 2 tuples {l3.src, l3.dest} for
26400 * tunnel packets. For none-tunnel packets, the RSS hash is
26401 * computed over the normal src/dest l3 headers.
26403 #define HWRM_VNIC_RSS_CFG_INPUT_HASH_MODE_FLAGS_INNERMOST_2 \
26406 * When this bit is '1', it indicates requesting support of
26407 * RSS hashing over outermost 4 tuples {t_l3.src, t_l3.dest,
26408 * t_l4.src, t_l4.dest} for tunnel packets. For none-tunnel
26409 * packets, the RSS hash is computed over the normal
26410 * src/dest l3 and src/dest l4 headers.
26412 #define HWRM_VNIC_RSS_CFG_INPUT_HASH_MODE_FLAGS_OUTERMOST_4 \
26415 * When this bit is '1', it indicates requesting support of
26416 * RSS hashing over outermost 2 tuples {t_l3.src, t_l3.dest} for
26417 * tunnel packets. For none-tunnel packets, the RSS hash is
26418 * computed over the normal src/dest l3 headers.
26420 #define HWRM_VNIC_RSS_CFG_INPUT_HASH_MODE_FLAGS_OUTERMOST_2 \
26422 /* This is the address for rss ring group table */
26423 uint64_t ring_grp_tbl_addr;
26424 /* This is the address for rss hash key table */
26425 uint64_t hash_key_tbl_addr;
26426 /* Index to the rss indirection table. */
26427 uint16_t rss_ctx_idx;
26428 uint8_t unused_1[6];
26431 /* hwrm_vnic_rss_cfg_output (size:128b/16B) */
26432 struct hwrm_vnic_rss_cfg_output {
26433 /* The specific error status for the command. */
26434 uint16_t error_code;
26435 /* The HWRM command request type. */
26437 /* The sequence ID from the original command. */
26439 /* The length of the response data in number of bytes. */
26441 uint8_t unused_0[7];
26443 * This field is used in Output records to indicate that the output
26444 * is completely written to RAM. This field should be read as '1'
26445 * to indicate that the output has been completely written.
26446 * When writing a command completion or response to an internal processor,
26447 * the order of writes has to be such that this field is written last.
26452 /* hwrm_vnic_rss_cfg_cmd_err (size:64b/8B) */
26453 struct hwrm_vnic_rss_cfg_cmd_err {
26455 * command specific error codes that goes to
26456 * the cmd_err field in Common HWRM Error Response.
26459 /* Unknown error */
26460 #define HWRM_VNIC_RSS_CFG_CMD_ERR_CODE_UNKNOWN \
26463 * Unable to change global RSS mode to outer due to all active
26464 * interfaces are not ready to support outer RSS hashing.
26466 #define HWRM_VNIC_RSS_CFG_CMD_ERR_CODE_INTERFACE_NOT_READY \
26468 #define HWRM_VNIC_RSS_CFG_CMD_ERR_CODE_LAST \
26469 HWRM_VNIC_RSS_CFG_CMD_ERR_CODE_INTERFACE_NOT_READY
26470 uint8_t unused_0[7];
26473 /**********************
26474 * hwrm_vnic_rss_qcfg *
26475 **********************/
26478 /* hwrm_vnic_rss_qcfg_input (size:192b/24B) */
26479 struct hwrm_vnic_rss_qcfg_input {
26480 /* The HWRM command request type. */
26483 * The completion ring to send the completion event on. This should
26484 * be the NQ ID returned from the `nq_alloc` HWRM command.
26486 uint16_t cmpl_ring;
26488 * The sequence ID is used by the driver for tracking multiple
26489 * commands. This ID is treated as opaque data by the firmware and
26490 * the value is returned in the `hwrm_resp_hdr` upon completion.
26494 * The target ID of the command:
26495 * * 0x0-0xFFF8 - The function ID
26496 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
26497 * * 0xFFFD - Reserved for user-space HWRM interface
26500 uint16_t target_id;
26502 * A physical address pointer pointing to a host buffer that the
26503 * command's response data will be written. This can be either a host
26504 * physical address (HPA) or a guest physical address (GPA) and must
26505 * point to a physically contiguous block of memory.
26507 uint64_t resp_addr;
26508 /* Index to the rss indirection table. */
26509 uint16_t rss_ctx_idx;
26510 uint8_t unused_0[6];
26513 /* hwrm_vnic_rss_qcfg_output (size:512b/64B) */
26514 struct hwrm_vnic_rss_qcfg_output {
26515 /* The specific error status for the command. */
26516 uint16_t error_code;
26517 /* The HWRM command request type. */
26519 /* The sequence ID from the original command. */
26521 /* The length of the response data in number of bytes. */
26523 uint32_t hash_type;
26525 * When this bit is '1', the RSS hash shall be computed
26526 * over source and destination IPv4 addresses of IPv4
26529 #define HWRM_VNIC_RSS_QCFG_OUTPUT_HASH_TYPE_IPV4 UINT32_C(0x1)
26531 * When this bit is '1', the RSS hash shall be computed
26532 * over source/destination IPv4 addresses and
26533 * source/destination ports of TCP/IPv4 packets.
26535 #define HWRM_VNIC_RSS_QCFG_OUTPUT_HASH_TYPE_TCP_IPV4 UINT32_C(0x2)
26537 * When this bit is '1', the RSS hash shall be computed
26538 * over source/destination IPv4 addresses and
26539 * source/destination ports of UDP/IPv4 packets.
26541 #define HWRM_VNIC_RSS_QCFG_OUTPUT_HASH_TYPE_UDP_IPV4 UINT32_C(0x4)
26543 * When this bit is '1', the RSS hash shall be computed
26544 * over source and destination IPv4 addresses of IPv6
26547 #define HWRM_VNIC_RSS_QCFG_OUTPUT_HASH_TYPE_IPV6 UINT32_C(0x8)
26549 * When this bit is '1', the RSS hash shall be computed
26550 * over source/destination IPv6 addresses and
26551 * source/destination ports of TCP/IPv6 packets.
26553 #define HWRM_VNIC_RSS_QCFG_OUTPUT_HASH_TYPE_TCP_IPV6 UINT32_C(0x10)
26555 * When this bit is '1', the RSS hash shall be computed
26556 * over source/destination IPv6 addresses and
26557 * source/destination ports of UDP/IPv6 packets.
26559 #define HWRM_VNIC_RSS_QCFG_OUTPUT_HASH_TYPE_UDP_IPV6 UINT32_C(0x20)
26560 uint8_t unused_0[4];
26561 /* This is the value of rss hash key */
26562 uint32_t hash_key[10];
26563 /* Flags to specify different RSS hash modes. */
26564 uint8_t hash_mode_flags;
26566 * When this bit is '1', it indicates using current RSS
26567 * hash mode setting configured in the device.
26569 #define HWRM_VNIC_RSS_QCFG_OUTPUT_HASH_MODE_FLAGS_DEFAULT \
26572 * When this bit is '1', it indicates requesting support of
26573 * RSS hashing over innermost 4 tuples {l3.src, l3.dest,
26574 * l4.src, l4.dest} for tunnel packets. For none-tunnel
26575 * packets, the RSS hash is computed over the normal
26576 * src/dest l3 and src/dest l4 headers.
26578 #define HWRM_VNIC_RSS_QCFG_OUTPUT_HASH_MODE_FLAGS_INNERMOST_4 \
26581 * When this bit is '1', it indicates requesting support of
26582 * RSS hashing over innermost 2 tuples {l3.src, l3.dest} for
26583 * tunnel packets. For none-tunnel packets, the RSS hash is
26584 * computed over the normal src/dest l3 headers.
26586 #define HWRM_VNIC_RSS_QCFG_OUTPUT_HASH_MODE_FLAGS_INNERMOST_2 \
26589 * When this bit is '1', it indicates requesting support of
26590 * RSS hashing over outermost 4 tuples {t_l3.src, t_l3.dest,
26591 * t_l4.src, t_l4.dest} for tunnel packets. For none-tunnel
26592 * packets, the RSS hash is computed over the normal
26593 * src/dest l3 and src/dest l4 headers.
26595 #define HWRM_VNIC_RSS_QCFG_OUTPUT_HASH_MODE_FLAGS_OUTERMOST_4 \
26598 * When this bit is '1', it indicates requesting support of
26599 * RSS hashing over outermost 2 tuples {t_l3.src, t_l3.dest} for
26600 * tunnel packets. For none-tunnel packets, the RSS hash is
26601 * computed over the normal src/dest l3 headers.
26603 #define HWRM_VNIC_RSS_QCFG_OUTPUT_HASH_MODE_FLAGS_OUTERMOST_2 \
26605 uint8_t unused_1[6];
26607 * This field is used in Output records to indicate that the output
26608 * is completely written to RAM. This field should be read as '1'
26609 * to indicate that the output has been completely written.
26610 * When writing a command completion or response to an internal processor,
26611 * the order of writes has to be such that this field is written last.
26616 /**************************
26617 * hwrm_vnic_plcmodes_cfg *
26618 **************************/
26621 /* hwrm_vnic_plcmodes_cfg_input (size:320b/40B) */
26622 struct hwrm_vnic_plcmodes_cfg_input {
26623 /* The HWRM command request type. */
26626 * The completion ring to send the completion event on. This should
26627 * be the NQ ID returned from the `nq_alloc` HWRM command.
26629 uint16_t cmpl_ring;
26631 * The sequence ID is used by the driver for tracking multiple
26632 * commands. This ID is treated as opaque data by the firmware and
26633 * the value is returned in the `hwrm_resp_hdr` upon completion.
26637 * The target ID of the command:
26638 * * 0x0-0xFFF8 - The function ID
26639 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
26640 * * 0xFFFD - Reserved for user-space HWRM interface
26643 uint16_t target_id;
26645 * A physical address pointer pointing to a host buffer that the
26646 * command's response data will be written. This can be either a host
26647 * physical address (HPA) or a guest physical address (GPA) and must
26648 * point to a physically contiguous block of memory.
26650 uint64_t resp_addr;
26653 * When this bit is '1', the VNIC shall be configured to
26654 * use regular placement algorithm.
26655 * By default, the regular placement algorithm shall be
26656 * enabled on the VNIC.
26658 #define HWRM_VNIC_PLCMODES_CFG_INPUT_FLAGS_REGULAR_PLACEMENT \
26661 * When this bit is '1', the VNIC shall be configured
26662 * use the jumbo placement algorithm.
26664 #define HWRM_VNIC_PLCMODES_CFG_INPUT_FLAGS_JUMBO_PLACEMENT \
26667 * When this bit is '1', the VNIC shall be configured
26668 * to enable Header-Data split for IPv4 packets according
26669 * to the following rules:
26670 * # If the packet is identified as TCP/IPv4, then the
26671 * packet is split at the beginning of the TCP payload.
26672 * # If the packet is identified as UDP/IPv4, then the
26673 * packet is split at the beginning of UDP payload.
26674 * # If the packet is identified as non-TCP and non-UDP
26675 * IPv4 packet, then the packet is split at the beginning
26676 * of the upper layer protocol header carried in the IPv4
26679 #define HWRM_VNIC_PLCMODES_CFG_INPUT_FLAGS_HDS_IPV4 \
26682 * When this bit is '1', the VNIC shall be configured
26683 * to enable Header-Data split for IPv6 packets according
26684 * to the following rules:
26685 * # If the packet is identified as TCP/IPv6, then the
26686 * packet is split at the beginning of the TCP payload.
26687 * # If the packet is identified as UDP/IPv6, then the
26688 * packet is split at the beginning of UDP payload.
26689 * # If the packet is identified as non-TCP and non-UDP
26690 * IPv6 packet, then the packet is split at the beginning
26691 * of the upper layer protocol header carried in the IPv6
26694 #define HWRM_VNIC_PLCMODES_CFG_INPUT_FLAGS_HDS_IPV6 \
26697 * When this bit is '1', the VNIC shall be configured
26698 * to enable Header-Data split for FCoE packets at the
26699 * beginning of FC payload.
26701 #define HWRM_VNIC_PLCMODES_CFG_INPUT_FLAGS_HDS_FCOE \
26704 * When this bit is '1', the VNIC shall be configured
26705 * to enable Header-Data split for RoCE packets at the
26706 * beginning of RoCE payload (after BTH/GRH headers).
26708 #define HWRM_VNIC_PLCMODES_CFG_INPUT_FLAGS_HDS_ROCE \
26711 * When this bit is '1', the VNIC shall be configured use the virtio
26712 * placement algorithm. This feature can only be configured when
26713 * proxy mode is supported on the function.
26715 #define HWRM_VNIC_PLCMODES_CFG_INPUT_FLAGS_VIRTIO_PLACEMENT \
26719 * This bit must be '1' for the jumbo_thresh_valid field to be
26722 #define HWRM_VNIC_PLCMODES_CFG_INPUT_ENABLES_JUMBO_THRESH_VALID \
26725 * This bit must be '1' for the hds_offset_valid field to be
26728 #define HWRM_VNIC_PLCMODES_CFG_INPUT_ENABLES_HDS_OFFSET_VALID \
26731 * This bit must be '1' for the hds_threshold_valid field to be
26734 #define HWRM_VNIC_PLCMODES_CFG_INPUT_ENABLES_HDS_THRESHOLD_VALID \
26737 * This bit must be '1' for the max_bds_valid field to be
26740 #define HWRM_VNIC_PLCMODES_CFG_INPUT_ENABLES_MAX_BDS_VALID \
26742 /* Logical vnic ID */
26745 * When jumbo placement algorithm is enabled, this value
26746 * is used to determine the threshold for jumbo placement.
26747 * Packets with length larger than this value will be
26748 * placed according to the jumbo placement algorithm.
26750 uint16_t jumbo_thresh;
26752 * This value is used to determine the offset into
26753 * packet buffer where the split data (payload) will be
26754 * placed according to one of HDS placement algorithm.
26756 * The lengths of packet buffers provided for split data
26757 * shall be larger than this value.
26759 uint16_t hds_offset;
26761 * When one of the HDS placement algorithm is enabled, this
26762 * value is used to determine the threshold for HDS
26764 * Packets with length larger than this value will be
26765 * placed according to the HDS placement algorithm.
26766 * This value shall be in multiple of 4 bytes.
26768 uint16_t hds_threshold;
26770 * When virtio placement algorithm is enabled, this
26771 * value is used to determine the the maximum number of BDs
26772 * that can be used to place an Rx Packet.
26773 * If an incoming packet does not fit in the buffers described
26774 * by the max BDs, the packet will be dropped and an error
26775 * will be reported in the completion. Valid values for this
26776 * field are between 1 and 8. If the VNIC uses header-data-
26777 * separation and/or TPA with buffer spanning enabled, valid
26778 * values for this field are between 2 and 8.
26779 * This feature can only be configured when proxy mode is
26780 * supported on the function.
26783 uint8_t unused_0[4];
26786 /* hwrm_vnic_plcmodes_cfg_output (size:128b/16B) */
26787 struct hwrm_vnic_plcmodes_cfg_output {
26788 /* The specific error status for the command. */
26789 uint16_t error_code;
26790 /* The HWRM command request type. */
26792 /* The sequence ID from the original command. */
26794 /* The length of the response data in number of bytes. */
26796 uint8_t unused_0[7];
26798 * This field is used in Output records to indicate that the output
26799 * is completely written to RAM. This field should be read as '1'
26800 * to indicate that the output has been completely written.
26801 * When writing a command completion or response to an internal
26802 * processor, the order of writes has to be such that this field is
26808 /***************************
26809 * hwrm_vnic_plcmodes_qcfg *
26810 ***************************/
26813 /* hwrm_vnic_plcmodes_qcfg_input (size:192b/24B) */
26814 struct hwrm_vnic_plcmodes_qcfg_input {
26815 /* The HWRM command request type. */
26818 * The completion ring to send the completion event on. This should
26819 * be the NQ ID returned from the `nq_alloc` HWRM command.
26821 uint16_t cmpl_ring;
26823 * The sequence ID is used by the driver for tracking multiple
26824 * commands. This ID is treated as opaque data by the firmware and
26825 * the value is returned in the `hwrm_resp_hdr` upon completion.
26829 * The target ID of the command:
26830 * * 0x0-0xFFF8 - The function ID
26831 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
26832 * * 0xFFFD - Reserved for user-space HWRM interface
26835 uint16_t target_id;
26837 * A physical address pointer pointing to a host buffer that the
26838 * command's response data will be written. This can be either a host
26839 * physical address (HPA) or a guest physical address (GPA) and must
26840 * point to a physically contiguous block of memory.
26842 uint64_t resp_addr;
26843 /* Logical vnic ID */
26845 uint8_t unused_0[4];
26848 /* hwrm_vnic_plcmodes_qcfg_output (size:192b/24B) */
26849 struct hwrm_vnic_plcmodes_qcfg_output {
26850 /* The specific error status for the command. */
26851 uint16_t error_code;
26852 /* The HWRM command request type. */
26854 /* The sequence ID from the original command. */
26856 /* The length of the response data in number of bytes. */
26860 * When this bit is '1', the VNIC is configured to
26861 * use regular placement algorithm.
26863 #define HWRM_VNIC_PLCMODES_QCFG_OUTPUT_FLAGS_REGULAR_PLACEMENT \
26866 * When this bit is '1', the VNIC is configured to
26867 * use the jumbo placement algorithm.
26869 #define HWRM_VNIC_PLCMODES_QCFG_OUTPUT_FLAGS_JUMBO_PLACEMENT \
26872 * When this bit is '1', the VNIC is configured
26873 * to enable Header-Data split for IPv4 packets.
26875 #define HWRM_VNIC_PLCMODES_QCFG_OUTPUT_FLAGS_HDS_IPV4 \
26878 * When this bit is '1', the VNIC is configured
26879 * to enable Header-Data split for IPv6 packets.
26881 #define HWRM_VNIC_PLCMODES_QCFG_OUTPUT_FLAGS_HDS_IPV6 \
26884 * When this bit is '1', the VNIC is configured
26885 * to enable Header-Data split for FCoE packets.
26887 #define HWRM_VNIC_PLCMODES_QCFG_OUTPUT_FLAGS_HDS_FCOE \
26890 * When this bit is '1', the VNIC is configured
26891 * to enable Header-Data split for RoCE packets.
26893 #define HWRM_VNIC_PLCMODES_QCFG_OUTPUT_FLAGS_HDS_ROCE \
26896 * When this bit is '1', the VNIC is configured
26897 * to be the default VNIC of the requesting function.
26899 #define HWRM_VNIC_PLCMODES_QCFG_OUTPUT_FLAGS_DFLT_VNIC \
26902 * When this bit is '1', the VNIC is configured to use the virtio
26903 * placement algorithm. This feature can only be configured when
26904 * proxy mode is supported on the function.
26906 #define HWRM_VNIC_PLCMODES_QCFG_OUTPUT_FLAGS_VIRTIO_PLACEMENT \
26909 * When jumbo placement algorithm is enabled, this value
26910 * is used to determine the threshold for jumbo placement.
26911 * Packets with length larger than this value will be
26912 * placed according to the jumbo placement algorithm.
26914 uint16_t jumbo_thresh;
26916 * This value is used to determine the offset into
26917 * packet buffer where the split data (payload) will be
26918 * placed according to one of HDS placement algorithm.
26920 * The lengths of packet buffers provided for split data
26921 * shall be larger than this value.
26923 uint16_t hds_offset;
26925 * When one of the HDS placement algorithm is enabled, this
26926 * value is used to determine the threshold for HDS
26928 * Packets with length larger than this value will be
26929 * placed according to the HDS placement algorithm.
26930 * This value shall be in multiple of 4 bytes.
26932 uint16_t hds_threshold;
26934 * When virtio placement algorithm is enabled, this
26935 * value is used to determine the the maximum number of BDs
26936 * that can be used to place an Rx Packet.
26937 * If an incoming packet does not fit in the buffers described
26938 * by the max BDs, the packet will be dropped and an error
26939 * will be reported in the completion. Valid values for this
26940 * field are between 1 and 8. If the VNIC uses header-data-
26941 * separation and/or TPA with buffer spanning enabled, valid
26942 * values for this field are between 2 and 8.
26943 * This feature can only be configured when proxy mode is supported
26947 uint8_t unused_0[3];
26949 * This field is used in Output records to indicate that the output
26950 * is completely written to RAM. This field should be read as '1'
26951 * to indicate that the output has been completely written.
26952 * When writing a command completion or response to an internal
26953 * processor, the order of writes has to be such that this field is
26959 /**********************************
26960 * hwrm_vnic_rss_cos_lb_ctx_alloc *
26961 **********************************/
26964 /* hwrm_vnic_rss_cos_lb_ctx_alloc_input (size:128b/16B) */
26965 struct hwrm_vnic_rss_cos_lb_ctx_alloc_input {
26966 /* The HWRM command request type. */
26969 * The completion ring to send the completion event on. This should
26970 * be the NQ ID returned from the `nq_alloc` HWRM command.
26972 uint16_t cmpl_ring;
26974 * The sequence ID is used by the driver for tracking multiple
26975 * commands. This ID is treated as opaque data by the firmware and
26976 * the value is returned in the `hwrm_resp_hdr` upon completion.
26980 * The target ID of the command:
26981 * * 0x0-0xFFF8 - The function ID
26982 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
26983 * * 0xFFFD - Reserved for user-space HWRM interface
26986 uint16_t target_id;
26988 * A physical address pointer pointing to a host buffer that the
26989 * command's response data will be written. This can be either a host
26990 * physical address (HPA) or a guest physical address (GPA) and must
26991 * point to a physically contiguous block of memory.
26993 uint64_t resp_addr;
26996 /* hwrm_vnic_rss_cos_lb_ctx_alloc_output (size:128b/16B) */
26997 struct hwrm_vnic_rss_cos_lb_ctx_alloc_output {
26998 /* The specific error status for the command. */
26999 uint16_t error_code;
27000 /* The HWRM command request type. */
27002 /* The sequence ID from the original command. */
27004 /* The length of the response data in number of bytes. */
27006 /* rss_cos_lb_ctx_id is 16 b */
27007 uint16_t rss_cos_lb_ctx_id;
27008 uint8_t unused_0[5];
27010 * This field is used in Output records to indicate that the output
27011 * is completely written to RAM. This field should be read as '1'
27012 * to indicate that the output has been completely written.
27013 * When writing a command completion or response to an internal processor,
27014 * the order of writes has to be such that this field is written last.
27019 /*********************************
27020 * hwrm_vnic_rss_cos_lb_ctx_free *
27021 *********************************/
27024 /* hwrm_vnic_rss_cos_lb_ctx_free_input (size:192b/24B) */
27025 struct hwrm_vnic_rss_cos_lb_ctx_free_input {
27026 /* The HWRM command request type. */
27029 * The completion ring to send the completion event on. This should
27030 * be the NQ ID returned from the `nq_alloc` HWRM command.
27032 uint16_t cmpl_ring;
27034 * The sequence ID is used by the driver for tracking multiple
27035 * commands. This ID is treated as opaque data by the firmware and
27036 * the value is returned in the `hwrm_resp_hdr` upon completion.
27040 * The target ID of the command:
27041 * * 0x0-0xFFF8 - The function ID
27042 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
27043 * * 0xFFFD - Reserved for user-space HWRM interface
27046 uint16_t target_id;
27048 * A physical address pointer pointing to a host buffer that the
27049 * command's response data will be written. This can be either a host
27050 * physical address (HPA) or a guest physical address (GPA) and must
27051 * point to a physically contiguous block of memory.
27053 uint64_t resp_addr;
27054 /* rss_cos_lb_ctx_id is 16 b */
27055 uint16_t rss_cos_lb_ctx_id;
27056 uint8_t unused_0[6];
27059 /* hwrm_vnic_rss_cos_lb_ctx_free_output (size:128b/16B) */
27060 struct hwrm_vnic_rss_cos_lb_ctx_free_output {
27061 /* The specific error status for the command. */
27062 uint16_t error_code;
27063 /* The HWRM command request type. */
27065 /* The sequence ID from the original command. */
27067 /* The length of the response data in number of bytes. */
27069 uint8_t unused_0[7];
27071 * This field is used in Output records to indicate that the output
27072 * is completely written to RAM. This field should be read as '1'
27073 * to indicate that the output has been completely written.
27074 * When writing a command completion or response to an internal processor,
27075 * the order of writes has to be such that this field is written last.
27080 /*******************
27081 * hwrm_ring_alloc *
27082 *******************/
27085 /* hwrm_ring_alloc_input (size:704b/88B) */
27086 struct hwrm_ring_alloc_input {
27087 /* The HWRM command request type. */
27090 * The completion ring to send the completion event on. This should
27091 * be the NQ ID returned from the `nq_alloc` HWRM command.
27093 uint16_t cmpl_ring;
27095 * The sequence ID is used by the driver for tracking multiple
27096 * commands. This ID is treated as opaque data by the firmware and
27097 * the value is returned in the `hwrm_resp_hdr` upon completion.
27101 * The target ID of the command:
27102 * * 0x0-0xFFF8 - The function ID
27103 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
27104 * * 0xFFFD - Reserved for user-space HWRM interface
27107 uint16_t target_id;
27109 * A physical address pointer pointing to a host buffer that the
27110 * command's response data will be written. This can be either a host
27111 * physical address (HPA) or a guest physical address (GPA) and must
27112 * point to a physically contiguous block of memory.
27114 uint64_t resp_addr;
27117 * This bit must be '1' for the ring_arb_cfg field to be
27120 #define HWRM_RING_ALLOC_INPUT_ENABLES_RING_ARB_CFG \
27123 * This bit must be '1' for the stat_ctx_id_valid field to be
27126 #define HWRM_RING_ALLOC_INPUT_ENABLES_STAT_CTX_ID_VALID \
27129 * This bit must be '1' for the max_bw_valid field to be
27132 #define HWRM_RING_ALLOC_INPUT_ENABLES_MAX_BW_VALID \
27135 * This bit must be '1' for the rx_ring_id field to be
27138 #define HWRM_RING_ALLOC_INPUT_ENABLES_RX_RING_ID_VALID \
27141 * This bit must be '1' for the nq_ring_id field to be
27144 #define HWRM_RING_ALLOC_INPUT_ENABLES_NQ_RING_ID_VALID \
27147 * This bit must be '1' for the rx_buf_size field to be
27150 #define HWRM_RING_ALLOC_INPUT_ENABLES_RX_BUF_SIZE_VALID \
27153 * This bit must be '1' for the schq_id field to be
27156 #define HWRM_RING_ALLOC_INPUT_ENABLES_SCHQ_ID \
27160 /* L2 Completion Ring (CR) */
27161 #define HWRM_RING_ALLOC_INPUT_RING_TYPE_L2_CMPL UINT32_C(0x0)
27163 #define HWRM_RING_ALLOC_INPUT_RING_TYPE_TX UINT32_C(0x1)
27165 #define HWRM_RING_ALLOC_INPUT_RING_TYPE_RX UINT32_C(0x2)
27166 /* RoCE Notification Completion Ring (ROCE_CR) */
27167 #define HWRM_RING_ALLOC_INPUT_RING_TYPE_ROCE_CMPL UINT32_C(0x3)
27168 /* RX Aggregation Ring */
27169 #define HWRM_RING_ALLOC_INPUT_RING_TYPE_RX_AGG UINT32_C(0x4)
27170 /* Notification Queue */
27171 #define HWRM_RING_ALLOC_INPUT_RING_TYPE_NQ UINT32_C(0x5)
27172 #define HWRM_RING_ALLOC_INPUT_RING_TYPE_LAST \
27173 HWRM_RING_ALLOC_INPUT_RING_TYPE_NQ
27175 /* Ring allocation flags. */
27178 * For Rx rings, the incoming packet data can be placed at either
27179 * a 0B or 2B offset from the start of the Rx packet buffer. When
27180 * '1', the received packet will be padded with 2B of zeros at the
27181 * front of the packet. Note that this flag is only used for
27182 * Rx rings and is ignored for all other rings included Rx
27183 * Aggregation rings.
27185 #define HWRM_RING_ALLOC_INPUT_FLAGS_RX_SOP_PAD UINT32_C(0x1)
27187 * This value is a pointer to the page table for the
27190 uint64_t page_tbl_addr;
27191 /* First Byte Offset of the first entry in the first page. */
27194 * Actual page size in 2^page_size. The supported range is increments
27195 * in powers of 2 from 16 bytes to 1GB.
27197 * Page size is 16 B.
27199 * Page size is 4 KB.
27201 * Page size is 8 KB.
27203 * Page size is 64 KB.
27205 * Page size is 2 MB.
27207 * Page size is 4 MB.
27209 * Page size is 1 GB.
27213 * This value indicates the depth of page table.
27214 * For this version of the specification, value other than 0 or
27215 * 1 shall be considered as an invalid value.
27216 * When the page_tbl_depth = 0, then it is treated as a
27217 * special case with the following.
27218 * 1. FBO and page size fields are not valid.
27219 * 2. page_tbl_addr is the physical address of the first
27220 * element of the ring.
27222 uint8_t page_tbl_depth;
27223 /* Used by a PF driver to associate a SCHQ with one of its TX rings. */
27226 * Number of 16B units in the ring. Minimum size for
27227 * a ring is 16 16B entries.
27231 * Logical ring number for the ring to be allocated.
27232 * This value determines the position in the doorbell
27233 * area where the update to the ring will be made.
27235 * For completion rings, this value is also the MSI-X
27236 * vector number for the function the completion ring is
27239 uint16_t logical_id;
27241 * This field is used only when ring_type is a TX ring.
27242 * This value indicates what completion ring the TX ring
27243 * is associated with.
27245 uint16_t cmpl_ring_id;
27247 * This field is used only when ring_type is a TX ring.
27248 * This value indicates what CoS queue the TX ring
27249 * is associated with.
27253 * When allocating a Rx ring or Rx aggregation ring, this field
27254 * specifies the size of the buffer descriptors posted to the ring.
27256 uint16_t rx_buf_size;
27258 * When allocating an Rx aggregation ring, this field
27259 * specifies the associated Rx ring ID.
27261 uint16_t rx_ring_id;
27263 * When allocating a completion ring, this field
27264 * specifies the associated NQ ring ID.
27266 uint16_t nq_ring_id;
27268 * This field is used only when ring_type is a TX ring.
27269 * This field is used to configure arbitration related
27270 * parameters for a TX ring.
27272 uint16_t ring_arb_cfg;
27273 /* Arbitration policy used for the ring. */
27274 #define HWRM_RING_ALLOC_INPUT_RING_ARB_CFG_ARB_POLICY_MASK \
27276 #define HWRM_RING_ALLOC_INPUT_RING_ARB_CFG_ARB_POLICY_SFT 0
27278 * Use strict priority for the TX ring.
27279 * Priority value is specified in arb_policy_param
27281 #define HWRM_RING_ALLOC_INPUT_RING_ARB_CFG_ARB_POLICY_SP \
27284 * Use weighted fair queue arbitration for the TX ring.
27285 * Weight is specified in arb_policy_param
27287 #define HWRM_RING_ALLOC_INPUT_RING_ARB_CFG_ARB_POLICY_WFQ \
27289 #define HWRM_RING_ALLOC_INPUT_RING_ARB_CFG_ARB_POLICY_LAST \
27290 HWRM_RING_ALLOC_INPUT_RING_ARB_CFG_ARB_POLICY_WFQ
27291 /* Reserved field. */
27292 #define HWRM_RING_ALLOC_INPUT_RING_ARB_CFG_RSVD_MASK \
27294 #define HWRM_RING_ALLOC_INPUT_RING_ARB_CFG_RSVD_SFT 4
27296 * Arbitration policy specific parameter.
27297 * # For strict priority arbitration policy, this field
27298 * represents a priority value. If set to 0, then the priority
27299 * is not specified and the HWRM is allowed to select
27300 * any priority for this TX ring.
27301 * # For weighted fair queue arbitration policy, this field
27302 * represents a weight value. If set to 0, then the weight
27303 * is not specified and the HWRM is allowed to select
27304 * any weight for this TX ring.
27306 #define HWRM_RING_ALLOC_INPUT_RING_ARB_CFG_ARB_POLICY_PARAM_MASK \
27308 #define HWRM_RING_ALLOC_INPUT_RING_ARB_CFG_ARB_POLICY_PARAM_SFT 8
27311 * This field is reserved for the future use.
27312 * It shall be set to 0.
27314 uint32_t reserved3;
27316 * This field is used only when ring_type is a TX ring.
27317 * This input indicates what statistics context this ring
27318 * should be associated with.
27320 uint32_t stat_ctx_id;
27322 * This field is reserved for the future use.
27323 * It shall be set to 0.
27325 uint32_t reserved4;
27327 * This field is used only when ring_type is a TX ring
27328 * to specify maximum BW allocated to the TX ring.
27329 * The HWRM will translate this value into byte counter and
27330 * time interval used for this ring inside the device.
27333 /* The bandwidth value. */
27334 #define HWRM_RING_ALLOC_INPUT_MAX_BW_BW_VALUE_MASK \
27335 UINT32_C(0xfffffff)
27336 #define HWRM_RING_ALLOC_INPUT_MAX_BW_BW_VALUE_SFT 0
27337 /* The granularity of the value (bits or bytes). */
27338 #define HWRM_RING_ALLOC_INPUT_MAX_BW_SCALE \
27339 UINT32_C(0x10000000)
27340 /* Value is in bits. */
27341 #define HWRM_RING_ALLOC_INPUT_MAX_BW_SCALE_BITS \
27342 (UINT32_C(0x0) << 28)
27343 /* Value is in bytes. */
27344 #define HWRM_RING_ALLOC_INPUT_MAX_BW_SCALE_BYTES \
27345 (UINT32_C(0x1) << 28)
27346 #define HWRM_RING_ALLOC_INPUT_MAX_BW_SCALE_LAST \
27347 HWRM_RING_ALLOC_INPUT_MAX_BW_SCALE_BYTES
27348 /* bw_value_unit is 3 b */
27349 #define HWRM_RING_ALLOC_INPUT_MAX_BW_BW_VALUE_UNIT_MASK \
27350 UINT32_C(0xe0000000)
27351 #define HWRM_RING_ALLOC_INPUT_MAX_BW_BW_VALUE_UNIT_SFT 29
27352 /* Value is in Mb or MB (base 10). */
27353 #define HWRM_RING_ALLOC_INPUT_MAX_BW_BW_VALUE_UNIT_MEGA \
27354 (UINT32_C(0x0) << 29)
27355 /* Value is in Kb or KB (base 10). */
27356 #define HWRM_RING_ALLOC_INPUT_MAX_BW_BW_VALUE_UNIT_KILO \
27357 (UINT32_C(0x2) << 29)
27358 /* Value is in bits or bytes. */
27359 #define HWRM_RING_ALLOC_INPUT_MAX_BW_BW_VALUE_UNIT_BASE \
27360 (UINT32_C(0x4) << 29)
27361 /* Value is in Gb or GB (base 10). */
27362 #define HWRM_RING_ALLOC_INPUT_MAX_BW_BW_VALUE_UNIT_GIGA \
27363 (UINT32_C(0x6) << 29)
27364 /* Value is in 1/100th of a percentage of total bandwidth. */
27365 #define HWRM_RING_ALLOC_INPUT_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 \
27366 (UINT32_C(0x1) << 29)
27368 #define HWRM_RING_ALLOC_INPUT_MAX_BW_BW_VALUE_UNIT_INVALID \
27369 (UINT32_C(0x7) << 29)
27370 #define HWRM_RING_ALLOC_INPUT_MAX_BW_BW_VALUE_UNIT_LAST \
27371 HWRM_RING_ALLOC_INPUT_MAX_BW_BW_VALUE_UNIT_INVALID
27373 * This field is used only when ring_type is a Completion ring.
27374 * This value indicates what interrupt mode should be used
27375 * on this completion ring.
27376 * Note: In the legacy interrupt mode, no more than 16
27377 * completion rings are allowed.
27381 #define HWRM_RING_ALLOC_INPUT_INT_MODE_LEGACY UINT32_C(0x0)
27383 #define HWRM_RING_ALLOC_INPUT_INT_MODE_RSVD UINT32_C(0x1)
27385 #define HWRM_RING_ALLOC_INPUT_INT_MODE_MSIX UINT32_C(0x2)
27386 /* No Interrupt - Polled mode */
27387 #define HWRM_RING_ALLOC_INPUT_INT_MODE_POLL UINT32_C(0x3)
27388 #define HWRM_RING_ALLOC_INPUT_INT_MODE_LAST \
27389 HWRM_RING_ALLOC_INPUT_INT_MODE_POLL
27390 uint8_t unused_4[3];
27392 * The cq_handle is specified when allocating a completion ring. For
27393 * devices that support NQs, this cq_handle will be included in the
27394 * NQE to specify which CQ should be read to retrieve the completion
27397 uint64_t cq_handle;
27400 /* hwrm_ring_alloc_output (size:128b/16B) */
27401 struct hwrm_ring_alloc_output {
27402 /* The specific error status for the command. */
27403 uint16_t error_code;
27404 /* The HWRM command request type. */
27406 /* The sequence ID from the original command. */
27408 /* The length of the response data in number of bytes. */
27411 * Physical number of ring allocated.
27412 * This value shall be unique for a ring type.
27415 /* Logical number of ring allocated. */
27416 uint16_t logical_ring_id;
27417 uint8_t unused_0[3];
27419 * This field is used in Output records to indicate that the output
27420 * is completely written to RAM. This field should be read as '1'
27421 * to indicate that the output has been completely written.
27422 * When writing a command completion or response to an internal processor,
27423 * the order of writes has to be such that this field is written last.
27428 /******************
27430 ******************/
27433 /* hwrm_ring_free_input (size:192b/24B) */
27434 struct hwrm_ring_free_input {
27435 /* The HWRM command request type. */
27438 * The completion ring to send the completion event on. This should
27439 * be the NQ ID returned from the `nq_alloc` HWRM command.
27441 uint16_t cmpl_ring;
27443 * The sequence ID is used by the driver for tracking multiple
27444 * commands. This ID is treated as opaque data by the firmware and
27445 * the value is returned in the `hwrm_resp_hdr` upon completion.
27449 * The target ID of the command:
27450 * * 0x0-0xFFF8 - The function ID
27451 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
27452 * * 0xFFFD - Reserved for user-space HWRM interface
27455 uint16_t target_id;
27457 * A physical address pointer pointing to a host buffer that the
27458 * command's response data will be written. This can be either a host
27459 * physical address (HPA) or a guest physical address (GPA) and must
27460 * point to a physically contiguous block of memory.
27462 uint64_t resp_addr;
27465 /* L2 Completion Ring (CR) */
27466 #define HWRM_RING_FREE_INPUT_RING_TYPE_L2_CMPL UINT32_C(0x0)
27468 #define HWRM_RING_FREE_INPUT_RING_TYPE_TX UINT32_C(0x1)
27470 #define HWRM_RING_FREE_INPUT_RING_TYPE_RX UINT32_C(0x2)
27471 /* RoCE Notification Completion Ring (ROCE_CR) */
27472 #define HWRM_RING_FREE_INPUT_RING_TYPE_ROCE_CMPL UINT32_C(0x3)
27473 /* RX Aggregation Ring */
27474 #define HWRM_RING_FREE_INPUT_RING_TYPE_RX_AGG UINT32_C(0x4)
27475 /* Notification Queue */
27476 #define HWRM_RING_FREE_INPUT_RING_TYPE_NQ UINT32_C(0x5)
27477 #define HWRM_RING_FREE_INPUT_RING_TYPE_LAST \
27478 HWRM_RING_FREE_INPUT_RING_TYPE_NQ
27480 /* Physical number of ring allocated. */
27482 uint8_t unused_1[4];
27485 /* hwrm_ring_free_output (size:128b/16B) */
27486 struct hwrm_ring_free_output {
27487 /* The specific error status for the command. */
27488 uint16_t error_code;
27489 /* The HWRM command request type. */
27491 /* The sequence ID from the original command. */
27493 /* The length of the response data in number of bytes. */
27495 uint8_t unused_0[7];
27497 * This field is used in Output records to indicate that the output
27498 * is completely written to RAM. This field should be read as '1'
27499 * to indicate that the output has been completely written.
27500 * When writing a command completion or response to an internal processor,
27501 * the order of writes has to be such that this field is written last.
27506 /*******************
27507 * hwrm_ring_reset *
27508 *******************/
27511 /* hwrm_ring_reset_input (size:192b/24B) */
27512 struct hwrm_ring_reset_input {
27513 /* The HWRM command request type. */
27516 * The completion ring to send the completion event on. This should
27517 * be the NQ ID returned from the `nq_alloc` HWRM command.
27519 uint16_t cmpl_ring;
27521 * The sequence ID is used by the driver for tracking multiple
27522 * commands. This ID is treated as opaque data by the firmware and
27523 * the value is returned in the `hwrm_resp_hdr` upon completion.
27527 * The target ID of the command:
27528 * * 0x0-0xFFF8 - The function ID
27529 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
27530 * * 0xFFFD - Reserved for user-space HWRM interface
27533 uint16_t target_id;
27535 * A physical address pointer pointing to a host buffer that the
27536 * command's response data will be written. This can be either a host
27537 * physical address (HPA) or a guest physical address (GPA) and must
27538 * point to a physically contiguous block of memory.
27540 uint64_t resp_addr;
27543 /* L2 Completion Ring (CR) */
27544 #define HWRM_RING_RESET_INPUT_RING_TYPE_L2_CMPL UINT32_C(0x0)
27546 #define HWRM_RING_RESET_INPUT_RING_TYPE_TX UINT32_C(0x1)
27548 #define HWRM_RING_RESET_INPUT_RING_TYPE_RX UINT32_C(0x2)
27549 /* RoCE Notification Completion Ring (ROCE_CR) */
27550 #define HWRM_RING_RESET_INPUT_RING_TYPE_ROCE_CMPL UINT32_C(0x3)
27552 * Rx Ring Group. This is to reset rx and aggregation in an atomic
27553 * operation. Completion ring associated with this ring group is
27556 #define HWRM_RING_RESET_INPUT_RING_TYPE_RX_RING_GRP UINT32_C(0x6)
27557 #define HWRM_RING_RESET_INPUT_RING_TYPE_LAST \
27558 HWRM_RING_RESET_INPUT_RING_TYPE_RX_RING_GRP
27561 * Physical number of the ring. When ring type is rx_ring_grp, ring id
27562 * actually refers to ring group id.
27565 uint8_t unused_1[4];
27568 /* hwrm_ring_reset_output (size:128b/16B) */
27569 struct hwrm_ring_reset_output {
27570 /* The specific error status for the command. */
27571 uint16_t error_code;
27572 /* The HWRM command request type. */
27574 /* The sequence ID from the original command. */
27576 /* The length of the response data in number of bytes. */
27578 uint8_t unused_0[4];
27579 /* Position of consumer index after ring reset completes. */
27580 uint8_t consumer_idx[3];
27582 * This field is used in Output records to indicate that the output
27583 * is completely written to RAM. This field should be read as '1'
27584 * to indicate that the output has been completely written.
27585 * When writing a command completion or response to an internal processor,
27586 * the order of writes has to be such that this field is written last.
27596 /* hwrm_ring_cfg_input (size:256b/32B) */
27597 struct hwrm_ring_cfg_input {
27598 /* The HWRM command request type. */
27601 * The completion ring to send the completion event on. This should
27602 * be the NQ ID returned from the `nq_alloc` HWRM command.
27604 uint16_t cmpl_ring;
27606 * The sequence ID is used by the driver for tracking multiple
27607 * commands. This ID is treated as opaque data by the firmware and
27608 * the value is returned in the `hwrm_resp_hdr` upon completion.
27612 * The target ID of the command:
27613 * * 0x0-0xFFF8 - The function ID
27614 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
27615 * * 0xFFFD - Reserved for user-space HWRM interface
27618 uint16_t target_id;
27620 * A physical address pointer pointing to a host buffer that the
27621 * command's response data will be written. This can be either a host
27622 * physical address (HPA) or a guest physical address (GPA) and must
27623 * point to a physically contiguous block of memory.
27625 uint64_t resp_addr;
27629 #define HWRM_RING_CFG_INPUT_RING_TYPE_TX UINT32_C(0x1)
27631 #define HWRM_RING_CFG_INPUT_RING_TYPE_RX UINT32_C(0x2)
27632 #define HWRM_RING_CFG_INPUT_RING_TYPE_LAST \
27633 HWRM_RING_CFG_INPUT_RING_TYPE_RX
27635 /* Physical number of the ring. */
27637 /* Ring config enable bits. */
27640 * For Rx rings, the incoming packet data can be placed at either
27641 * a 0B, 2B, 10B or 12B offset from the start of the Rx packet
27643 * When '1', the received packet will be padded with 2B, 10B or 12B
27644 * of zeros at the front of the packet. The exact offset is specified
27645 * by rx_sop_pad_bytes parameter.
27646 * When '0', the received packet will not be padded.
27647 * Note that this flag is only used for Rx rings and is ignored
27648 * for all other rings included Rx Aggregation rings.
27650 #define HWRM_RING_CFG_INPUT_ENABLES_RX_SOP_PAD_ENABLE \
27653 * Proxy mode enable, for Tx, Rx and Rx aggregation rings only.
27654 * When rings are allocated, the PCI function on which driver issues
27655 * HWRM_RING_CFG command is assumed to own the rings. Hardware takes
27656 * the buffer descriptors (BDs) from those rings is assumed to issue
27657 * packet payload DMA using same PCI function. When proxy mode is
27658 * enabled, hardware can perform payload DMA using another PCI
27659 * function on same or different host.
27660 * When set to '0', the PCI function on which driver issues
27661 * HWRM_RING_CFG command is used for host payload DMA operation.
27662 * When set to '1', the host PCI function specified by proxy_fid is
27663 * used for host payload DMA operation.
27665 #define HWRM_RING_CFG_INPUT_ENABLES_PROXY_MODE_ENABLE \
27668 * Tx ring packet source interface override, for Tx rings only.
27669 * When TX rings are allocated, the PCI function on which driver
27670 * issues HWRM_RING_CFG is assumed to be source interface of
27671 * packets sent from TX ring.
27672 * When set to '1', the host PCI function specified by proxy_fid
27673 * is used as source interface of the transmitted packets.
27675 #define HWRM_RING_CFG_INPUT_ENABLES_TX_PROXY_SRC_INTF_OVERRIDE \
27677 /* The schq_id field is valid */
27678 #define HWRM_RING_CFG_INPUT_ENABLES_SCHQ_ID \
27680 /* Update completion ring ID associated with Tx or Rx ring. */
27681 #define HWRM_RING_CFG_INPUT_ENABLES_CMPL_RING_ID_UPDATE \
27684 * Proxy function FID value.
27685 * This value is only used when either proxy_mode_enable flag or
27686 * tx_proxy_svif_override is set to '1'.
27687 * When proxy_mode_enable is set to '1', it identifies a host PCI
27688 * function used for host payload DMA operations.
27689 * When tx_proxy_src_intf is set to '1', it identifies a host PCI
27690 * function as source interface for all transmitted packets from
27693 uint16_t proxy_fid;
27695 * Identifies the new scheduler queue (SCHQ) to associate with the
27696 * ring. Only valid for Tx rings.
27697 * A value of zero indicates that the Tx ring should be associated
27698 * with the default scheduler queue (SCHQ).
27702 * This field is valid for TX or Rx rings. This value identifies the
27703 * new completion ring ID to associate with the TX or Rx ring.
27705 uint16_t cmpl_ring_id;
27707 * Rx SOP padding amount in bytes.
27708 * This value is only used when rx_sop_pad_enable flag is set to '1'.
27710 uint8_t rx_sop_pad_bytes;
27711 uint8_t unused_1[3];
27714 /* hwrm_ring_cfg_output (size:128b/16B) */
27715 struct hwrm_ring_cfg_output {
27716 /* The specific error status for the command. */
27717 uint16_t error_code;
27718 /* The HWRM command request type. */
27720 /* The sequence ID from the original command. */
27722 /* The length of the response data in number of bytes. */
27724 uint8_t unused_0[7];
27726 * This field is used in Output records to indicate that the output
27727 * is completely written to RAM. This field should be read as '1'
27728 * to indicate that the output has been completely written.
27729 * When writing a command completion or response to an internal
27730 * processor, the order of writes has to be such that this field is
27736 /******************
27738 ******************/
27741 /* hwrm_ring_qcfg_input (size:192b/24B) */
27742 struct hwrm_ring_qcfg_input {
27743 /* The HWRM command request type. */
27746 * The completion ring to send the completion event on. This should
27747 * be the NQ ID returned from the `nq_alloc` HWRM command.
27749 uint16_t cmpl_ring;
27751 * The sequence ID is used by the driver for tracking multiple
27752 * commands. This ID is treated as opaque data by the firmware and
27753 * the value is returned in the `hwrm_resp_hdr` upon completion.
27757 * The target ID of the command:
27758 * * 0x0-0xFFF8 - The function ID
27759 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
27760 * * 0xFFFD - Reserved for user-space HWRM interface
27763 uint16_t target_id;
27765 * A physical address pointer pointing to a host buffer that the
27766 * command's response data will be written. This can be either a host
27767 * physical address (HPA) or a guest physical address (GPA) and must
27768 * point to a physically contiguous block of memory.
27770 uint64_t resp_addr;
27774 #define HWRM_RING_QCFG_INPUT_RING_TYPE_TX UINT32_C(0x1)
27776 #define HWRM_RING_QCFG_INPUT_RING_TYPE_RX UINT32_C(0x2)
27777 #define HWRM_RING_QCFG_INPUT_RING_TYPE_LAST \
27778 HWRM_RING_QCFG_INPUT_RING_TYPE_RX
27779 uint8_t unused_0[5];
27780 /* Physical number of the ring. */
27784 /* hwrm_ring_qcfg_output (size:192b/24B) */
27785 struct hwrm_ring_qcfg_output {
27786 /* The specific error status for the command. */
27787 uint16_t error_code;
27788 /* The HWRM command request type. */
27790 /* The sequence ID from the original command. */
27792 /* The length of the response data in number of bytes. */
27794 /* Ring config enable bits. */
27797 * For Rx rings, the incoming packet data can be placed at either
27798 * a 0B, 2B, 10B or 12B offset from the start of the Rx packet
27800 * When '1', the received packet will be padded with 2B, 10B or 12B
27801 * of zeros at the front of the packet. The exact offset is specified
27802 * by rx_sop_pad_bytes parameter.
27803 * When '0', the received packet will not be padded.
27804 * Note that this flag is only used for Rx rings and is ignored
27805 * for all other rings included Rx Aggregation rings.
27807 #define HWRM_RING_QCFG_OUTPUT_ENABLES_RX_SOP_PAD_ENABLE \
27810 * Proxy mode enable, for Tx, Rx and Rx aggregation rings only.
27811 * When rings are allocated, the PCI function on which driver issues
27812 * HWRM_RING_CFG command is assumed to own the rings. Hardware takes
27813 * the buffer descriptors (BDs) from those rings is assumed to issue
27814 * packet payload DMA using same PCI function. When proxy mode is
27815 * enabled, hardware can perform payload DMA using another PCI
27816 * function on same or different host.
27817 * When set to '0', the PCI function on which driver issues
27818 * HWRM_RING_CFG command is used for host payload DMA operation.
27819 * When set to '1', the host PCI function specified by proxy_fid is
27820 * used for host payload DMA operation.
27822 #define HWRM_RING_QCFG_OUTPUT_ENABLES_PROXY_MODE_ENABLE \
27825 * Tx ring packet source interface override, for Tx rings only.
27826 * When TX rings are allocated, the PCI function on which driver
27827 * issues HWRM_RING_CFG is assumed to be source interface of
27828 * packets sent from TX ring.
27829 * When set to '1', the host PCI function specified by proxy_fid is
27830 * used as source interface of the transmitted packets.
27832 #define HWRM_RING_QCFG_OUTPUT_ENABLES_TX_PROXY_SRC_INTF_OVERRIDE \
27835 * Proxy function FID value.
27836 * This value is only used when either proxy_mode_enable flag or
27837 * tx_proxy_svif_override is set to '1'.
27838 * When proxy_mode_enable is set to '1', it identifies a host PCI
27839 * function used for host payload DMA operations.
27840 * When tx_proxy_src_intf is set to '1', it identifies a host PCI
27841 * function as source interface for all transmitted packets from the TX
27844 uint16_t proxy_fid;
27846 * Identifies the new scheduler queue (SCHQ) to associate with the
27847 * ring. Only valid for Tx rings.
27848 * A value of zero indicates that the Tx ring should be associated with
27849 * the default scheduler queue (SCHQ).
27853 * This field is used when ring_type is a TX or Rx ring.
27854 * This value indicates what completion ring the TX or Rx ring
27855 * is associated with.
27857 uint16_t cmpl_ring_id;
27859 * Rx SOP padding amount in bytes.
27860 * This value is only used when rx_sop_pad_enable flag is set to '1'.
27862 uint8_t rx_sop_pad_bytes;
27863 uint8_t unused_0[6];
27865 * This field is used in Output records to indicate that the output
27866 * is completely written to RAM. This field should be read as '1'
27867 * to indicate that the output has been completely written.
27868 * When writing a command completion or response to an internal
27869 * processor, the order of writes has to be such that this field is
27875 /**************************
27876 * hwrm_ring_aggint_qcaps *
27877 **************************/
27880 /* hwrm_ring_aggint_qcaps_input (size:128b/16B) */
27881 struct hwrm_ring_aggint_qcaps_input {
27882 /* The HWRM command request type. */
27885 * The completion ring to send the completion event on. This should
27886 * be the NQ ID returned from the `nq_alloc` HWRM command.
27888 uint16_t cmpl_ring;
27890 * The sequence ID is used by the driver for tracking multiple
27891 * commands. This ID is treated as opaque data by the firmware and
27892 * the value is returned in the `hwrm_resp_hdr` upon completion.
27896 * The target ID of the command:
27897 * * 0x0-0xFFF8 - The function ID
27898 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
27899 * * 0xFFFD - Reserved for user-space HWRM interface
27902 uint16_t target_id;
27904 * A physical address pointer pointing to a host buffer that the
27905 * command's response data will be written. This can be either a host
27906 * physical address (HPA) or a guest physical address (GPA) and must
27907 * point to a physically contiguous block of memory.
27909 uint64_t resp_addr;
27912 /* hwrm_ring_aggint_qcaps_output (size:384b/48B) */
27913 struct hwrm_ring_aggint_qcaps_output {
27914 /* The specific error status for the command. */
27915 uint16_t error_code;
27916 /* The HWRM command request type. */
27918 /* The sequence ID from the original command. */
27920 /* The length of the response data in number of bytes. */
27922 uint32_t cmpl_params;
27924 * When this bit is set to '1', int_lat_tmr_min can be configured
27925 * on completion rings.
27927 #define HWRM_RING_AGGINT_QCAPS_OUTPUT_CMPL_PARAMS_INT_LAT_TMR_MIN \
27930 * When this bit is set to '1', int_lat_tmr_max can be configured
27931 * on completion rings.
27933 #define HWRM_RING_AGGINT_QCAPS_OUTPUT_CMPL_PARAMS_INT_LAT_TMR_MAX \
27936 * When this bit is set to '1', timer_reset can be enabled
27937 * on completion rings.
27939 #define HWRM_RING_AGGINT_QCAPS_OUTPUT_CMPL_PARAMS_TIMER_RESET \
27942 * When this bit is set to '1', ring_idle can be enabled
27943 * on completion rings.
27945 #define HWRM_RING_AGGINT_QCAPS_OUTPUT_CMPL_PARAMS_RING_IDLE \
27948 * When this bit is set to '1', num_cmpl_dma_aggr can be configured
27949 * on completion rings.
27951 #define HWRM_RING_AGGINT_QCAPS_OUTPUT_CMPL_PARAMS_NUM_CMPL_DMA_AGGR \
27954 * When this bit is set to '1', num_cmpl_dma_aggr_during_int can be configured
27955 * on completion rings.
27957 #define HWRM_RING_AGGINT_QCAPS_OUTPUT_CMPL_PARAMS_NUM_CMPL_DMA_AGGR_DURING_INT \
27960 * When this bit is set to '1', cmpl_aggr_dma_tmr can be configured
27961 * on completion rings.
27963 #define HWRM_RING_AGGINT_QCAPS_OUTPUT_CMPL_PARAMS_CMPL_AGGR_DMA_TMR \
27966 * When this bit is set to '1', cmpl_aggr_dma_tmr_during_int can be configured
27967 * on completion rings.
27969 #define HWRM_RING_AGGINT_QCAPS_OUTPUT_CMPL_PARAMS_CMPL_AGGR_DMA_TMR_DURING_INT \
27972 * When this bit is set to '1', num_cmpl_aggr_int can be configured
27973 * on completion rings.
27975 #define HWRM_RING_AGGINT_QCAPS_OUTPUT_CMPL_PARAMS_NUM_CMPL_AGGR_INT \
27977 uint32_t nq_params;
27979 * When this bit is set to '1', int_lat_tmr_min can be configured
27980 * on notification queues.
27982 #define HWRM_RING_AGGINT_QCAPS_OUTPUT_NQ_PARAMS_INT_LAT_TMR_MIN \
27984 /* Minimum value for num_cmpl_dma_aggr */
27985 uint16_t num_cmpl_dma_aggr_min;
27986 /* Maximum value for num_cmpl_dma_aggr */
27987 uint16_t num_cmpl_dma_aggr_max;
27988 /* Minimum value for num_cmpl_dma_aggr_during_int */
27989 uint16_t num_cmpl_dma_aggr_during_int_min;
27990 /* Maximum value for num_cmpl_dma_aggr_during_int */
27991 uint16_t num_cmpl_dma_aggr_during_int_max;
27992 /* Minimum value for cmpl_aggr_dma_tmr */
27993 uint16_t cmpl_aggr_dma_tmr_min;
27994 /* Maximum value for cmpl_aggr_dma_tmr */
27995 uint16_t cmpl_aggr_dma_tmr_max;
27996 /* Minimum value for cmpl_aggr_dma_tmr_during_int */
27997 uint16_t cmpl_aggr_dma_tmr_during_int_min;
27998 /* Maximum value for cmpl_aggr_dma_tmr_during_int */
27999 uint16_t cmpl_aggr_dma_tmr_during_int_max;
28000 /* Minimum value for int_lat_tmr_min */
28001 uint16_t int_lat_tmr_min_min;
28002 /* Maximum value for int_lat_tmr_min */
28003 uint16_t int_lat_tmr_min_max;
28004 /* Minimum value for int_lat_tmr_max */
28005 uint16_t int_lat_tmr_max_min;
28006 /* Maximum value for int_lat_tmr_max */
28007 uint16_t int_lat_tmr_max_max;
28008 /* Minimum value for num_cmpl_aggr_int */
28009 uint16_t num_cmpl_aggr_int_min;
28010 /* Maximum value for num_cmpl_aggr_int */
28011 uint16_t num_cmpl_aggr_int_max;
28012 /* The units for timer parameters, in nanoseconds. */
28013 uint16_t timer_units;
28014 uint8_t unused_0[1];
28016 * This field is used in Output records to indicate that the output
28017 * is completely written to RAM. This field should be read as '1'
28018 * to indicate that the output has been completely written.
28019 * When writing a command completion or response to an internal processor,
28020 * the order of writes has to be such that this field is written last.
28025 /**************************************
28026 * hwrm_ring_cmpl_ring_qaggint_params *
28027 **************************************/
28030 /* hwrm_ring_cmpl_ring_qaggint_params_input (size:192b/24B) */
28031 struct hwrm_ring_cmpl_ring_qaggint_params_input {
28032 /* The HWRM command request type. */
28035 * The completion ring to send the completion event on. This should
28036 * be the NQ ID returned from the `nq_alloc` HWRM command.
28038 uint16_t cmpl_ring;
28040 * The sequence ID is used by the driver for tracking multiple
28041 * commands. This ID is treated as opaque data by the firmware and
28042 * the value is returned in the `hwrm_resp_hdr` upon completion.
28046 * The target ID of the command:
28047 * * 0x0-0xFFF8 - The function ID
28048 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
28049 * * 0xFFFD - Reserved for user-space HWRM interface
28052 uint16_t target_id;
28054 * A physical address pointer pointing to a host buffer that the
28055 * command's response data will be written. This can be either a host
28056 * physical address (HPA) or a guest physical address (GPA) and must
28057 * point to a physically contiguous block of memory.
28059 uint64_t resp_addr;
28060 /* Physical number of completion ring. */
28063 #define HWRM_RING_CMPL_RING_QAGGINT_PARAMS_INPUT_FLAGS_UNUSED_0_MASK \
28065 #define HWRM_RING_CMPL_RING_QAGGINT_PARAMS_INPUT_FLAGS_UNUSED_0_SFT 0
28067 * Set this flag to 1 when querying parameters on a notification
28068 * queue. Set this flag to 0 when querying parameters on a
28069 * completion queue or completion ring.
28071 #define HWRM_RING_CMPL_RING_QAGGINT_PARAMS_INPUT_FLAGS_IS_NQ \
28073 uint8_t unused_0[4];
28076 /* hwrm_ring_cmpl_ring_qaggint_params_output (size:256b/32B) */
28077 struct hwrm_ring_cmpl_ring_qaggint_params_output {
28078 /* The specific error status for the command. */
28079 uint16_t error_code;
28080 /* The HWRM command request type. */
28082 /* The sequence ID from the original command. */
28084 /* The length of the response data in number of bytes. */
28088 * When this bit is set to '1', interrupt max
28089 * timer is reset whenever a completion is received.
28091 #define HWRM_RING_CMPL_RING_QAGGINT_PARAMS_OUTPUT_FLAGS_TIMER_RESET \
28094 * When this bit is set to '1', ring idle mode
28095 * aggregation will be enabled.
28097 #define HWRM_RING_CMPL_RING_QAGGINT_PARAMS_OUTPUT_FLAGS_RING_IDLE \
28100 * Number of completions to aggregate before DMA
28101 * during the normal mode.
28103 uint16_t num_cmpl_dma_aggr;
28105 * Number of completions to aggregate before DMA
28106 * during the interrupt mode.
28108 uint16_t num_cmpl_dma_aggr_during_int;
28110 * Timer used to aggregate completions before
28111 * DMA during the normal mode (not in interrupt mode).
28113 uint16_t cmpl_aggr_dma_tmr;
28115 * Timer used to aggregate completions before
28116 * DMA when in interrupt mode.
28118 uint16_t cmpl_aggr_dma_tmr_during_int;
28119 /* Minimum time between two interrupts. */
28120 uint16_t int_lat_tmr_min;
28122 * Maximum wait time spent aggregating
28123 * completions before signaling the interrupt after the
28124 * interrupt is enabled.
28126 uint16_t int_lat_tmr_max;
28128 * Minimum number of completions aggregated before signaling
28131 uint16_t num_cmpl_aggr_int;
28132 uint8_t unused_0[7];
28134 * This field is used in Output records to indicate that the output
28135 * is completely written to RAM. This field should be read as '1'
28136 * to indicate that the output has been completely written.
28137 * When writing a command completion or response to an internal processor,
28138 * the order of writes has to be such that this field is written last.
28143 /*****************************************
28144 * hwrm_ring_cmpl_ring_cfg_aggint_params *
28145 *****************************************/
28148 /* hwrm_ring_cmpl_ring_cfg_aggint_params_input (size:320b/40B) */
28149 struct hwrm_ring_cmpl_ring_cfg_aggint_params_input {
28150 /* The HWRM command request type. */
28153 * The completion ring to send the completion event on. This should
28154 * be the NQ ID returned from the `nq_alloc` HWRM command.
28156 uint16_t cmpl_ring;
28158 * The sequence ID is used by the driver for tracking multiple
28159 * commands. This ID is treated as opaque data by the firmware and
28160 * the value is returned in the `hwrm_resp_hdr` upon completion.
28164 * The target ID of the command:
28165 * * 0x0-0xFFF8 - The function ID
28166 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
28167 * * 0xFFFD - Reserved for user-space HWRM interface
28170 uint16_t target_id;
28172 * A physical address pointer pointing to a host buffer that the
28173 * command's response data will be written. This can be either a host
28174 * physical address (HPA) or a guest physical address (GPA) and must
28175 * point to a physically contiguous block of memory.
28177 uint64_t resp_addr;
28178 /* Physical number of completion ring. */
28182 * When this bit is set to '1', interrupt latency max
28183 * timer is reset whenever a completion is received.
28185 #define HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_FLAGS_TIMER_RESET \
28188 * When this bit is set to '1', ring idle mode
28189 * aggregation will be enabled.
28191 #define HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_FLAGS_RING_IDLE \
28194 * Set this flag to 1 when configuring parameters on a
28195 * notification queue. Set this flag to 0 when configuring
28196 * parameters on a completion queue or completion ring.
28198 #define HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_FLAGS_IS_NQ \
28201 * Number of completions to aggregate before DMA
28202 * during the normal mode.
28204 uint16_t num_cmpl_dma_aggr;
28206 * Number of completions to aggregate before DMA
28207 * during the interrupt mode.
28209 uint16_t num_cmpl_dma_aggr_during_int;
28211 * Timer used to aggregate completions before
28212 * DMA during the normal mode (not in interrupt mode).
28214 uint16_t cmpl_aggr_dma_tmr;
28216 * Timer used to aggregate completions before
28217 * DMA while in interrupt mode.
28219 uint16_t cmpl_aggr_dma_tmr_during_int;
28220 /* Minimum time between two interrupts. */
28221 uint16_t int_lat_tmr_min;
28223 * Maximum wait time spent aggregating
28224 * completions before signaling the interrupt after the
28225 * interrupt is enabled.
28227 uint16_t int_lat_tmr_max;
28229 * Minimum number of completions aggregated before signaling
28232 uint16_t num_cmpl_aggr_int;
28234 * Bitfield that indicates which parameters are to be applied. Only
28235 * required when configuring devices with notification queues, and
28236 * used in that case to set certain parameters on completion queues
28237 * and others on notification queues.
28241 * This bit must be '1' for the num_cmpl_dma_aggr field to be
28244 #define HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_ENABLES_NUM_CMPL_DMA_AGGR \
28247 * This bit must be '1' for the num_cmpl_dma_aggr_during_int field to be
28250 #define HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_ENABLES_NUM_CMPL_DMA_AGGR_DURING_INT \
28253 * This bit must be '1' for the cmpl_aggr_dma_tmr field to be
28256 #define HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_ENABLES_CMPL_AGGR_DMA_TMR \
28259 * This bit must be '1' for the int_lat_tmr_min field to be
28262 #define HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_ENABLES_INT_LAT_TMR_MIN \
28265 * This bit must be '1' for the int_lat_tmr_max field to be
28268 #define HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_ENABLES_INT_LAT_TMR_MAX \
28271 * This bit must be '1' for the num_cmpl_aggr_int field to be
28274 #define HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_ENABLES_NUM_CMPL_AGGR_INT \
28276 uint8_t unused_0[4];
28279 /* hwrm_ring_cmpl_ring_cfg_aggint_params_output (size:128b/16B) */
28280 struct hwrm_ring_cmpl_ring_cfg_aggint_params_output {
28281 /* The specific error status for the command. */
28282 uint16_t error_code;
28283 /* The HWRM command request type. */
28285 /* The sequence ID from the original command. */
28287 /* The length of the response data in number of bytes. */
28289 uint8_t unused_0[7];
28291 * This field is used in Output records to indicate that the output
28292 * is completely written to RAM. This field should be read as '1'
28293 * to indicate that the output has been completely written.
28294 * When writing a command completion or response to an internal processor,
28295 * the order of writes has to be such that this field is written last.
28300 /***********************
28301 * hwrm_ring_grp_alloc *
28302 ***********************/
28305 /* hwrm_ring_grp_alloc_input (size:192b/24B) */
28306 struct hwrm_ring_grp_alloc_input {
28307 /* The HWRM command request type. */
28310 * The completion ring to send the completion event on. This should
28311 * be the NQ ID returned from the `nq_alloc` HWRM command.
28313 uint16_t cmpl_ring;
28315 * The sequence ID is used by the driver for tracking multiple
28316 * commands. This ID is treated as opaque data by the firmware and
28317 * the value is returned in the `hwrm_resp_hdr` upon completion.
28321 * The target ID of the command:
28322 * * 0x0-0xFFF8 - The function ID
28323 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
28324 * * 0xFFFD - Reserved for user-space HWRM interface
28327 uint16_t target_id;
28329 * A physical address pointer pointing to a host buffer that the
28330 * command's response data will be written. This can be either a host
28331 * physical address (HPA) or a guest physical address (GPA) and must
28332 * point to a physically contiguous block of memory.
28334 uint64_t resp_addr;
28336 * This value identifies the CR associated with the ring
28341 * This value identifies the main RR associated with the ring
28346 * This value identifies the aggregation RR associated with
28347 * the ring group. If this value is 0xFF... (All Fs), then no
28348 * Aggregation ring will be set.
28352 * This value identifies the statistics context associated
28353 * with the ring group.
28358 /* hwrm_ring_grp_alloc_output (size:128b/16B) */
28359 struct hwrm_ring_grp_alloc_output {
28360 /* The specific error status for the command. */
28361 uint16_t error_code;
28362 /* The HWRM command request type. */
28364 /* The sequence ID from the original command. */
28366 /* The length of the response data in number of bytes. */
28369 * This is the ring group ID value. Use this value to program
28370 * the default ring group for the VNIC or as table entries
28371 * in an RSS/COS context.
28373 uint32_t ring_group_id;
28374 uint8_t unused_0[3];
28376 * This field is used in Output records to indicate that the output
28377 * is completely written to RAM. This field should be read as '1'
28378 * to indicate that the output has been completely written.
28379 * When writing a command completion or response to an internal processor,
28380 * the order of writes has to be such that this field is written last.
28385 /**********************
28386 * hwrm_ring_grp_free *
28387 **********************/
28390 /* hwrm_ring_grp_free_input (size:192b/24B) */
28391 struct hwrm_ring_grp_free_input {
28392 /* The HWRM command request type. */
28395 * The completion ring to send the completion event on. This should
28396 * be the NQ ID returned from the `nq_alloc` HWRM command.
28398 uint16_t cmpl_ring;
28400 * The sequence ID is used by the driver for tracking multiple
28401 * commands. This ID is treated as opaque data by the firmware and
28402 * the value is returned in the `hwrm_resp_hdr` upon completion.
28406 * The target ID of the command:
28407 * * 0x0-0xFFF8 - The function ID
28408 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
28409 * * 0xFFFD - Reserved for user-space HWRM interface
28412 uint16_t target_id;
28414 * A physical address pointer pointing to a host buffer that the
28415 * command's response data will be written. This can be either a host
28416 * physical address (HPA) or a guest physical address (GPA) and must
28417 * point to a physically contiguous block of memory.
28419 uint64_t resp_addr;
28420 /* This is the ring group ID value. */
28421 uint32_t ring_group_id;
28422 uint8_t unused_0[4];
28425 /* hwrm_ring_grp_free_output (size:128b/16B) */
28426 struct hwrm_ring_grp_free_output {
28427 /* The specific error status for the command. */
28428 uint16_t error_code;
28429 /* The HWRM command request type. */
28431 /* The sequence ID from the original command. */
28433 /* The length of the response data in number of bytes. */
28435 uint8_t unused_0[7];
28437 * This field is used in Output records to indicate that the output
28438 * is completely written to RAM. This field should be read as '1'
28439 * to indicate that the output has been completely written.
28440 * When writing a command completion or response to an internal processor,
28441 * the order of writes has to be such that this field is written last.
28446 /************************
28447 * hwrm_ring_schq_alloc *
28448 ************************/
28451 /* hwrm_ring_schq_alloc_input (size:1088b/136B) */
28452 struct hwrm_ring_schq_alloc_input {
28453 /* The HWRM command request type. */
28456 * The completion ring to send the completion event on. This should
28457 * be the NQ ID returned from the `nq_alloc` HWRM command.
28459 uint16_t cmpl_ring;
28461 * The sequence ID is used by the driver for tracking multiple
28462 * commands. This ID is treated as opaque data by the firmware and
28463 * the value is returned in the `hwrm_resp_hdr` upon completion.
28467 * The target ID of the command:
28468 * * 0x0-0xFFF8 - The function ID
28469 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
28470 * * 0xFFFD - Reserved for user-space HWRM interface
28473 uint16_t target_id;
28475 * A physical address pointer pointing to a host buffer that the
28476 * command's response data will be written. This can be either a host
28477 * physical address (HPA) or a guest physical address (GPA) and must
28478 * point to a physically contiguous block of memory.
28480 uint64_t resp_addr;
28483 * This bit must be '1' for the tqm_ring0 fields to be
28486 #define HWRM_RING_SCHQ_ALLOC_INPUT_ENABLES_TQM_RING0 UINT32_C(0x1)
28488 * This bit must be '1' for the tqm_ring1 fields to be
28491 #define HWRM_RING_SCHQ_ALLOC_INPUT_ENABLES_TQM_RING1 UINT32_C(0x2)
28493 * This bit must be '1' for the tqm_ring2 fields to be
28496 #define HWRM_RING_SCHQ_ALLOC_INPUT_ENABLES_TQM_RING2 UINT32_C(0x4)
28498 * This bit must be '1' for the tqm_ring3 fields to be
28501 #define HWRM_RING_SCHQ_ALLOC_INPUT_ENABLES_TQM_RING3 UINT32_C(0x8)
28503 * This bit must be '1' for the tqm_ring4 fields to be
28506 #define HWRM_RING_SCHQ_ALLOC_INPUT_ENABLES_TQM_RING4 UINT32_C(0x10)
28508 * This bit must be '1' for the tqm_ring5 fields to be
28511 #define HWRM_RING_SCHQ_ALLOC_INPUT_ENABLES_TQM_RING5 UINT32_C(0x20)
28513 * This bit must be '1' for the tqm_ring6 fields to be
28516 #define HWRM_RING_SCHQ_ALLOC_INPUT_ENABLES_TQM_RING6 UINT32_C(0x40)
28518 * This bit must be '1' for the tqm_ring7 fields to be
28521 #define HWRM_RING_SCHQ_ALLOC_INPUT_ENABLES_TQM_RING7 UINT32_C(0x80)
28522 /* Reserved for future use. */
28524 /* TQM ring 0 page size and level. */
28525 uint8_t tqm_ring0_pg_size_tqm_ring0_lvl;
28526 /* TQM ring 0 PBL indirect levels. */
28527 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING0_LVL_MASK \
28529 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING0_LVL_SFT 0
28530 /* PBL pointer is physical start address. */
28531 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING0_LVL_LVL_0 \
28533 /* PBL pointer points to PTE table. */
28534 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING0_LVL_LVL_1 \
28537 * PBL pointer points to PDE table with each entry pointing to PTE
28540 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING0_LVL_LVL_2 \
28542 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING0_LVL_LAST \
28543 HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING0_LVL_LVL_2
28544 /* TQM ring 0 page size. */
28545 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING0_PG_SIZE_MASK \
28547 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING0_PG_SIZE_SFT 4
28549 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING0_PG_SIZE_PG_4K \
28550 (UINT32_C(0x0) << 4)
28552 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING0_PG_SIZE_PG_8K \
28553 (UINT32_C(0x1) << 4)
28555 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING0_PG_SIZE_PG_64K \
28556 (UINT32_C(0x2) << 4)
28558 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING0_PG_SIZE_PG_2M \
28559 (UINT32_C(0x3) << 4)
28561 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING0_PG_SIZE_PG_8M \
28562 (UINT32_C(0x4) << 4)
28564 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING0_PG_SIZE_PG_1G \
28565 (UINT32_C(0x5) << 4)
28566 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING0_PG_SIZE_LAST \
28567 HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING0_PG_SIZE_PG_1G
28568 /* TQM ring 1 page size and level. */
28569 uint8_t tqm_ring1_pg_size_tqm_ring1_lvl;
28570 /* TQM ring 1 PBL indirect levels. */
28571 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING1_LVL_MASK \
28573 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING1_LVL_SFT 0
28574 /* PBL pointer is physical start address. */
28575 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING1_LVL_LVL_0 \
28577 /* PBL pointer points to PTE table. */
28578 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING1_LVL_LVL_1 \
28581 * PBL pointer points to PDE table with each entry pointing to PTE
28584 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING1_LVL_LVL_2 \
28586 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING1_LVL_LAST \
28587 HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING1_LVL_LVL_2
28588 /* TQM ring 1 page size. */
28589 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING1_PG_SIZE_MASK \
28591 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING1_PG_SIZE_SFT 4
28593 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING1_PG_SIZE_PG_4K \
28594 (UINT32_C(0x0) << 4)
28596 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING1_PG_SIZE_PG_8K \
28597 (UINT32_C(0x1) << 4)
28599 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING1_PG_SIZE_PG_64K \
28600 (UINT32_C(0x2) << 4)
28602 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING1_PG_SIZE_PG_2M \
28603 (UINT32_C(0x3) << 4)
28605 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING1_PG_SIZE_PG_8M \
28606 (UINT32_C(0x4) << 4)
28608 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING1_PG_SIZE_PG_1G \
28609 (UINT32_C(0x5) << 4)
28610 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING1_PG_SIZE_LAST \
28611 HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING1_PG_SIZE_PG_1G
28612 /* TQM ring 2 page size and level. */
28613 uint8_t tqm_ring2_pg_size_tqm_ring2_lvl;
28614 /* TQM ring 2 PBL indirect levels. */
28615 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING2_LVL_MASK \
28617 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING2_LVL_SFT 0
28618 /* PBL pointer is physical start address. */
28619 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING2_LVL_LVL_0 \
28621 /* PBL pointer points to PTE table. */
28622 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING2_LVL_LVL_1 \
28625 * PBL pointer points to PDE table with each entry pointing to PTE
28628 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING2_LVL_LVL_2 \
28630 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING2_LVL_LAST \
28631 HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING2_LVL_LVL_2
28632 /* TQM ring 2 page size. */
28633 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING2_PG_SIZE_MASK \
28635 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING2_PG_SIZE_SFT 4
28637 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING2_PG_SIZE_PG_4K \
28638 (UINT32_C(0x0) << 4)
28640 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING2_PG_SIZE_PG_8K \
28641 (UINT32_C(0x1) << 4)
28643 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING2_PG_SIZE_PG_64K \
28644 (UINT32_C(0x2) << 4)
28646 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING2_PG_SIZE_PG_2M \
28647 (UINT32_C(0x3) << 4)
28649 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING2_PG_SIZE_PG_8M \
28650 (UINT32_C(0x4) << 4)
28652 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING2_PG_SIZE_PG_1G \
28653 (UINT32_C(0x5) << 4)
28654 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING2_PG_SIZE_LAST \
28655 HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING2_PG_SIZE_PG_1G
28656 /* TQM ring 3 page size and level. */
28657 uint8_t tqm_ring3_pg_size_tqm_ring3_lvl;
28658 /* TQM ring 3 PBL indirect levels. */
28659 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING3_LVL_MASK \
28661 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING3_LVL_SFT 0
28662 /* PBL pointer is physical start address. */
28663 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING3_LVL_LVL_0 \
28665 /* PBL pointer points to PTE table. */
28666 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING3_LVL_LVL_1 \
28669 * PBL pointer points to PDE table with each entry pointing to PTE
28672 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING3_LVL_LVL_2 \
28674 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING3_LVL_LAST \
28675 HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING3_LVL_LVL_2
28676 /* TQM ring 3 page size. */
28677 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING3_PG_SIZE_MASK \
28679 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING3_PG_SIZE_SFT 4
28681 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING3_PG_SIZE_PG_4K \
28682 (UINT32_C(0x0) << 4)
28684 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING3_PG_SIZE_PG_8K \
28685 (UINT32_C(0x1) << 4)
28687 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING3_PG_SIZE_PG_64K \
28688 (UINT32_C(0x2) << 4)
28690 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING3_PG_SIZE_PG_2M \
28691 (UINT32_C(0x3) << 4)
28693 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING3_PG_SIZE_PG_8M \
28694 (UINT32_C(0x4) << 4)
28696 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING3_PG_SIZE_PG_1G \
28697 (UINT32_C(0x5) << 4)
28698 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING3_PG_SIZE_LAST \
28699 HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING3_PG_SIZE_PG_1G
28700 /* TQM ring 4 page size and level. */
28701 uint8_t tqm_ring4_pg_size_tqm_ring4_lvl;
28702 /* TQM ring 4 PBL indirect levels. */
28703 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING4_LVL_MASK \
28705 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING4_LVL_SFT 0
28706 /* PBL pointer is physical start address. */
28707 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING4_LVL_LVL_0 \
28709 /* PBL pointer points to PTE table. */
28710 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING4_LVL_LVL_1 \
28713 * PBL pointer points to PDE table with each entry pointing to PTE
28716 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING4_LVL_LVL_2 \
28718 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING4_LVL_LAST \
28719 HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING4_LVL_LVL_2
28720 /* TQM ring 4 page size. */
28721 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING4_PG_SIZE_MASK \
28723 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING4_PG_SIZE_SFT 4
28725 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING4_PG_SIZE_PG_4K \
28726 (UINT32_C(0x0) << 4)
28728 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING4_PG_SIZE_PG_8K \
28729 (UINT32_C(0x1) << 4)
28731 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING4_PG_SIZE_PG_64K \
28732 (UINT32_C(0x2) << 4)
28734 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING4_PG_SIZE_PG_2M \
28735 (UINT32_C(0x3) << 4)
28737 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING4_PG_SIZE_PG_8M \
28738 (UINT32_C(0x4) << 4)
28740 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING4_PG_SIZE_PG_1G \
28741 (UINT32_C(0x5) << 4)
28742 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING4_PG_SIZE_LAST \
28743 HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING4_PG_SIZE_PG_1G
28744 /* TQM ring 5 page size and level. */
28745 uint8_t tqm_ring5_pg_size_tqm_ring5_lvl;
28746 /* TQM ring 5 PBL indirect levels. */
28747 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING5_LVL_MASK \
28749 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING5_LVL_SFT 0
28750 /* PBL pointer is physical start address. */
28751 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING5_LVL_LVL_0 \
28753 /* PBL pointer points to PTE table. */
28754 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING5_LVL_LVL_1 \
28757 * PBL pointer points to PDE table with each entry pointing to PTE
28760 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING5_LVL_LVL_2 \
28762 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING5_LVL_LAST \
28763 HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING5_LVL_LVL_2
28764 /* TQM ring 5 page size. */
28765 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING5_PG_SIZE_MASK \
28767 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING5_PG_SIZE_SFT 4
28769 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING5_PG_SIZE_PG_4K \
28770 (UINT32_C(0x0) << 4)
28772 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING5_PG_SIZE_PG_8K \
28773 (UINT32_C(0x1) << 4)
28775 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING5_PG_SIZE_PG_64K \
28776 (UINT32_C(0x2) << 4)
28778 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING5_PG_SIZE_PG_2M \
28779 (UINT32_C(0x3) << 4)
28781 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING5_PG_SIZE_PG_8M \
28782 (UINT32_C(0x4) << 4)
28784 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING5_PG_SIZE_PG_1G \
28785 (UINT32_C(0x5) << 4)
28786 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING5_PG_SIZE_LAST \
28787 HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING5_PG_SIZE_PG_1G
28788 /* TQM ring 6 page size and level. */
28789 uint8_t tqm_ring6_pg_size_tqm_ring6_lvl;
28790 /* TQM ring 6 PBL indirect levels. */
28791 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING6_LVL_MASK \
28793 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING6_LVL_SFT 0
28794 /* PBL pointer is physical start address. */
28795 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING6_LVL_LVL_0 \
28797 /* PBL pointer points to PTE table. */
28798 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING6_LVL_LVL_1 \
28801 * PBL pointer points to PDE table with each entry pointing to PTE
28804 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING6_LVL_LVL_2 \
28806 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING6_LVL_LAST \
28807 HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING6_LVL_LVL_2
28808 /* TQM ring 6 page size. */
28809 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING6_PG_SIZE_MASK \
28811 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING6_PG_SIZE_SFT 4
28813 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING6_PG_SIZE_PG_4K \
28814 (UINT32_C(0x0) << 4)
28816 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING6_PG_SIZE_PG_8K \
28817 (UINT32_C(0x1) << 4)
28819 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING6_PG_SIZE_PG_64K \
28820 (UINT32_C(0x2) << 4)
28822 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING6_PG_SIZE_PG_2M \
28823 (UINT32_C(0x3) << 4)
28825 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING6_PG_SIZE_PG_8M \
28826 (UINT32_C(0x4) << 4)
28828 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING6_PG_SIZE_PG_1G \
28829 (UINT32_C(0x5) << 4)
28830 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING6_PG_SIZE_LAST \
28831 HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING6_PG_SIZE_PG_1G
28832 /* TQM ring 7 page size and level. */
28833 uint8_t tqm_ring7_pg_size_tqm_ring7_lvl;
28834 /* TQM ring 7 PBL indirect levels. */
28835 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING7_LVL_MASK \
28837 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING7_LVL_SFT 0
28838 /* PBL pointer is physical start address. */
28839 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING7_LVL_LVL_0 \
28841 /* PBL pointer points to PTE table. */
28842 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING7_LVL_LVL_1 \
28845 * PBL pointer points to PDE table with each entry pointing to PTE
28848 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING7_LVL_LVL_2 \
28850 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING7_LVL_LAST \
28851 HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING7_LVL_LVL_2
28852 /* TQM ring 7 page size. */
28853 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING7_PG_SIZE_MASK \
28855 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING7_PG_SIZE_SFT 4
28857 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING7_PG_SIZE_PG_4K \
28858 (UINT32_C(0x0) << 4)
28860 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING7_PG_SIZE_PG_8K \
28861 (UINT32_C(0x1) << 4)
28863 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING7_PG_SIZE_PG_64K \
28864 (UINT32_C(0x2) << 4)
28866 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING7_PG_SIZE_PG_2M \
28867 (UINT32_C(0x3) << 4)
28869 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING7_PG_SIZE_PG_8M \
28870 (UINT32_C(0x4) << 4)
28872 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING7_PG_SIZE_PG_1G \
28873 (UINT32_C(0x5) << 4)
28874 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING7_PG_SIZE_LAST \
28875 HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING7_PG_SIZE_PG_1G
28876 /* TQM ring 0 page directory. */
28877 uint64_t tqm_ring0_page_dir;
28878 /* TQM ring 1 page directory. */
28879 uint64_t tqm_ring1_page_dir;
28880 /* TQM ring 2 page directory. */
28881 uint64_t tqm_ring2_page_dir;
28882 /* TQM ring 3 page directory. */
28883 uint64_t tqm_ring3_page_dir;
28884 /* TQM ring 4 page directory. */
28885 uint64_t tqm_ring4_page_dir;
28886 /* TQM ring 5 page directory. */
28887 uint64_t tqm_ring5_page_dir;
28888 /* TQM ring 6 page directory. */
28889 uint64_t tqm_ring6_page_dir;
28890 /* TQM ring 7 page directory. */
28891 uint64_t tqm_ring7_page_dir;
28893 * Number of TQM ring 0 entries.
28895 * TQM fastpath rings should be sized large enough to accommodate the
28896 * maximum number of QPs (either L2 or RoCE, or both if shared)
28897 * that can be enqueued to the TQM ring.
28899 * Note that TQM ring sizes cannot be extended while the system is
28900 * operational. If a PF driver needs to extend a TQM ring, it needs
28901 * to delete the SCHQ and then reallocate it.
28903 uint32_t tqm_ring0_num_entries;
28905 * Number of TQM ring 1 entries.
28907 * TQM fastpath rings should be sized large enough to accommodate the
28908 * maximum number of QPs (either L2 or RoCE, or both if shared)
28909 * that can be enqueued to the TQM ring.
28911 * Note that TQM ring sizes cannot be extended while the system is
28912 * operational. If a PF driver needs to extend a TQM ring, it needs
28913 * to delete the SCHQ and then reallocate it.
28915 uint32_t tqm_ring1_num_entries;
28917 * Number of TQM ring 2 entries.
28919 * TQM fastpath rings should be sized large enough to accommodate the
28920 * maximum number of QPs (either L2 or RoCE, or both if shared)
28921 * that can be enqueued to the TQM ring.
28923 * Note that TQM ring sizes cannot be extended while the system is
28924 * operational. If a PF driver needs to extend a TQM ring, it needs
28925 * to delete the SCHQ and then reallocate it.
28927 uint32_t tqm_ring2_num_entries;
28929 * Number of TQM ring 3 entries.
28931 * TQM fastpath rings should be sized large enough to accommodate the
28932 * maximum number of QPs (either L2 or RoCE, or both if shared)
28933 * that can be enqueued to the TQM ring.
28935 * Note that TQM ring sizes cannot be extended while the system is
28936 * operational. If a PF driver needs to extend a TQM ring, it needs
28937 * to delete the SCHQ and then reallocate it.
28939 uint32_t tqm_ring3_num_entries;
28941 * Number of TQM ring 4 entries.
28943 * TQM fastpath rings should be sized large enough to accommodate the
28944 * maximum number of QPs (either L2 or RoCE, or both if shared)
28945 * that can be enqueued to the TQM ring.
28947 * Note that TQM ring sizes cannot be extended while the system is
28948 * operational. If a PF driver needs to extend a TQM ring, it needs
28949 * to delete the SCHQ and then reallocate it.
28951 uint32_t tqm_ring4_num_entries;
28953 * Number of TQM ring 5 entries.
28955 * TQM fastpath rings should be sized large enough to accommodate the
28956 * maximum number of QPs (either L2 or RoCE, or both if shared)
28957 * that can be enqueued to the TQM ring.
28959 * Note that TQM ring sizes cannot be extended while the system is
28960 * operational. If a PF driver needs to extend a TQM ring, it needs
28961 * to delete the SCHQ and then reallocate it.
28963 uint32_t tqm_ring5_num_entries;
28965 * Number of TQM ring 6 entries.
28967 * TQM fastpath rings should be sized large enough to accommodate the
28968 * maximum number of QPs (either L2 or RoCE, or both if shared)
28969 * that can be enqueued to the TQM ring.
28971 * Note that TQM ring sizes cannot be extended while the system is
28972 * operational. If a PF driver needs to extend a TQM ring, it needs
28973 * to delete the SCHQ and then reallocate it.
28975 uint32_t tqm_ring6_num_entries;
28977 * Number of TQM ring 7 entries.
28979 * TQM fastpath rings should be sized large enough to accommodate the
28980 * maximum number of QPs (either L2 or RoCE, or both if shared)
28981 * that can be enqueued to the TQM ring.
28983 * Note that TQM ring sizes cannot be extended while the system is
28984 * operational. If a PF driver needs to extend a TQM ring, it needs
28985 * to delete the SCHQ and then reallocate it.
28987 uint32_t tqm_ring7_num_entries;
28988 /* Number of bytes that have been allocated for each context entry. */
28989 uint16_t tqm_entry_size;
28990 uint8_t unused_0[6];
28993 /* hwrm_ring_schq_alloc_output (size:128b/16B) */
28994 struct hwrm_ring_schq_alloc_output {
28995 /* The specific error status for the command. */
28996 uint16_t error_code;
28997 /* The HWRM command request type. */
28999 /* The sequence ID from the original command. */
29001 /* The length of the response data in number of bytes. */
29004 * This is an identifier for the SCHQ to be used in other HWRM commands
29005 * that need to reference this SCHQ. This value is greater than zero
29006 * (i.e. a schq_id of zero references the default SCHQ).
29009 uint8_t unused_0[5];
29011 * This field is used in Output records to indicate that the output
29012 * is completely written to RAM. This field should be read as '1'
29013 * to indicate that the output has been completely written.
29014 * When writing a command completion or response to an internal processor,
29015 * the order of writes has to be such that this field is written last.
29020 /**********************
29021 * hwrm_ring_schq_cfg *
29022 **********************/
29025 /* hwrm_ring_schq_cfg_input (size:768b/96B) */
29026 struct hwrm_ring_schq_cfg_input {
29027 /* The HWRM command request type. */
29030 * The completion ring to send the completion event on. This should
29031 * be the NQ ID returned from the `nq_alloc` HWRM command.
29033 uint16_t cmpl_ring;
29035 * The sequence ID is used by the driver for tracking multiple
29036 * commands. This ID is treated as opaque data by the firmware and
29037 * the value is returned in the `hwrm_resp_hdr` upon completion.
29041 * The target ID of the command:
29042 * * 0x0-0xFFF8 - The function ID
29043 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
29044 * * 0xFFFD - Reserved for user-space HWRM interface
29047 uint16_t target_id;
29049 * A physical address pointer pointing to a host buffer that the
29050 * command's response data will be written. This can be either a host
29051 * physical address (HPA) or a guest physical address (GPA) and must
29052 * point to a physically contiguous block of memory.
29054 uint64_t resp_addr;
29056 * Identifies the SCHQ being configured. A schq_id of zero refers to
29057 * the default SCHQ.
29061 * This field is an 8 bit bitmap that indicates which TCs are enabled
29062 * in this SCHQ. Bit 0 represents traffic class 0 and bit 7 represents
29065 uint8_t tc_enabled;
29068 /* The tc_max_bw array and the max_bw parameters are valid */
29069 #define HWRM_RING_SCHQ_CFG_INPUT_FLAGS_TC_MAX_BW_ENABLED \
29071 /* The tc_min_bw array is valid */
29072 #define HWRM_RING_SCHQ_CFG_INPUT_FLAGS_TC_MIN_BW_ENABLED \
29074 /* Maximum bandwidth of the traffic class, specified in Mbps. */
29075 uint32_t max_bw_tc0;
29076 /* Maximum bandwidth of the traffic class, specified in Mbps. */
29077 uint32_t max_bw_tc1;
29078 /* Maximum bandwidth of the traffic class, specified in Mbps. */
29079 uint32_t max_bw_tc2;
29080 /* Maximum bandwidth of the traffic class, specified in Mbps. */
29081 uint32_t max_bw_tc3;
29082 /* Maximum bandwidth of the traffic class, specified in Mbps. */
29083 uint32_t max_bw_tc4;
29084 /* Maximum bandwidth of the traffic class, specified in Mbps. */
29085 uint32_t max_bw_tc5;
29086 /* Maximum bandwidth of the traffic class, specified in Mbps. */
29087 uint32_t max_bw_tc6;
29088 /* Maximum bandwidth of the traffic class, specified in Mbps. */
29089 uint32_t max_bw_tc7;
29091 * Bandwidth reservation for the traffic class, specified in Mbps.
29092 * A value of zero signifies that traffic belonging to this class
29093 * shares the bandwidth reservation for the same traffic class of
29094 * the default SCHQ.
29096 uint32_t min_bw_tc0;
29098 * Bandwidth reservation for the traffic class, specified in Mbps.
29099 * A value of zero signifies that traffic belonging to this class
29100 * shares the bandwidth reservation for the same traffic class of
29101 * the default SCHQ.
29103 uint32_t min_bw_tc1;
29105 * Bandwidth reservation for the traffic class, specified in Mbps.
29106 * A value of zero signifies that traffic belonging to this class
29107 * shares the bandwidth reservation for the same traffic class of
29108 * the default SCHQ.
29110 uint32_t min_bw_tc2;
29112 * Bandwidth reservation for the traffic class, specified in Mbps.
29113 * A value of zero signifies that traffic belonging to this class
29114 * shares the bandwidth reservation for the same traffic class of
29115 * the default SCHQ.
29117 uint32_t min_bw_tc3;
29119 * Bandwidth reservation for the traffic class, specified in Mbps.
29120 * A value of zero signifies that traffic belonging to this class
29121 * shares the bandwidth reservation for the same traffic class of
29122 * the default SCHQ.
29124 uint32_t min_bw_tc4;
29126 * Bandwidth reservation for the traffic class, specified in Mbps.
29127 * A value of zero signifies that traffic belonging to this class
29128 * shares the bandwidth reservation for the same traffic class of
29129 * the default SCHQ.
29131 uint32_t min_bw_tc5;
29133 * Bandwidth reservation for the traffic class, specified in Mbps.
29134 * A value of zero signifies that traffic belonging to this class
29135 * shares the bandwidth reservation for the same traffic class of
29136 * the default SCHQ.
29138 uint32_t min_bw_tc6;
29140 * Bandwidth reservation for the traffic class, specified in Mbps.
29141 * A value of zero signifies that traffic belonging to this class
29142 * shares the bandwidth reservation for the same traffic class of
29143 * the default SCHQ.
29145 uint32_t min_bw_tc7;
29147 * Indicates the max bandwidth for all enabled traffic classes in
29148 * this SCHQ, specified in Mbps.
29151 uint8_t unused_1[4];
29154 /* hwrm_ring_schq_cfg_output (size:128b/16B) */
29155 struct hwrm_ring_schq_cfg_output {
29156 /* The specific error status for the command. */
29157 uint16_t error_code;
29158 /* The HWRM command request type. */
29160 /* The sequence ID from the original command. */
29162 /* The length of the response data in number of bytes. */
29164 uint8_t unused_0[7];
29166 * This field is used in Output records to indicate that the output
29167 * is completely written to RAM. This field should be read as '1'
29168 * to indicate that the output has been completely written.
29169 * When writing a command completion or response to an internal processor,
29170 * the order of writes has to be such that this field is written last.
29175 /***********************
29176 * hwrm_ring_schq_free *
29177 ***********************/
29180 /* hwrm_ring_schq_free_input (size:192b/24B) */
29181 struct hwrm_ring_schq_free_input {
29182 /* The HWRM command request type. */
29185 * The completion ring to send the completion event on. This should
29186 * be the NQ ID returned from the `nq_alloc` HWRM command.
29188 uint16_t cmpl_ring;
29190 * The sequence ID is used by the driver for tracking multiple
29191 * commands. This ID is treated as opaque data by the firmware and
29192 * the value is returned in the `hwrm_resp_hdr` upon completion.
29196 * The target ID of the command:
29197 * * 0x0-0xFFF8 - The function ID
29198 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
29199 * * 0xFFFD - Reserved for user-space HWRM interface
29202 uint16_t target_id;
29204 * A physical address pointer pointing to a host buffer that the
29205 * command's response data will be written. This can be either a host
29206 * physical address (HPA) or a guest physical address (GPA) and must
29207 * point to a physically contiguous block of memory.
29209 uint64_t resp_addr;
29210 /* Identifies the SCHQ being freed. */
29212 uint8_t unused_0[6];
29215 /* hwrm_ring_schq_free_output (size:128b/16B) */
29216 struct hwrm_ring_schq_free_output {
29217 /* The specific error status for the command. */
29218 uint16_t error_code;
29219 /* The HWRM command request type. */
29221 /* The sequence ID from the original command. */
29223 /* The length of the response data in number of bytes. */
29225 uint8_t unused_0[7];
29227 * This field is used in Output records to indicate that the output
29228 * is completely written to RAM. This field should be read as '1'
29229 * to indicate that the output has been completely written.
29230 * When writing a command completion or response to an internal processor,
29231 * the order of writes has to be such that this field is written last.
29236 * special reserved flow ID to identify per function default
29237 * flows for vSwitch offload
29239 #define DEFAULT_FLOW_ID 0xFFFFFFFFUL
29241 * special reserved flow ID to identify per function RoCEv1
29244 #define ROCEV1_FLOW_ID 0xFFFFFFFEUL
29246 * special reserved flow ID to identify per function RoCEv2
29249 #define ROCEV2_FLOW_ID 0xFFFFFFFDUL
29251 * special reserved flow ID to identify per function RoCEv2
29254 #define ROCEV2_CNP_FLOW_ID 0xFFFFFFFCUL
29256 /****************************
29257 * hwrm_cfa_l2_filter_alloc *
29258 ****************************/
29261 /* hwrm_cfa_l2_filter_alloc_input (size:768b/96B) */
29262 struct hwrm_cfa_l2_filter_alloc_input {
29263 /* The HWRM command request type. */
29266 * The completion ring to send the completion event on. This should
29267 * be the NQ ID returned from the `nq_alloc` HWRM command.
29269 uint16_t cmpl_ring;
29271 * The sequence ID is used by the driver for tracking multiple
29272 * commands. This ID is treated as opaque data by the firmware and
29273 * the value is returned in the `hwrm_resp_hdr` upon completion.
29277 * The target ID of the command:
29278 * * 0x0-0xFFF8 - The function ID
29279 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
29280 * * 0xFFFD - Reserved for user-space HWRM interface
29283 uint16_t target_id;
29285 * A physical address pointer pointing to a host buffer that the
29286 * command's response data will be written. This can be either a host
29287 * physical address (HPA) or a guest physical address (GPA) and must
29288 * point to a physically contiguous block of memory.
29290 uint64_t resp_addr;
29293 * Enumeration denoting the RX, TX type of the resource.
29294 * This enumeration is used for resources that are similar for both
29295 * TX and RX paths of the chip.
29297 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_PATH \
29300 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_PATH_TX \
29303 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_PATH_RX \
29305 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_PATH_LAST \
29306 HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_PATH_RX
29307 /* Setting of this flag indicates the applicability to the loopback path. */
29308 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_LOOPBACK \
29311 * Setting of this flag indicates drop action. If this flag is not set,
29312 * then it should be considered accept action.
29314 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_DROP \
29317 * If this flag is set, all t_l2_* fields are invalid
29318 * and they should not be specified.
29319 * If this flag is set, then l2_* fields refer to
29320 * fields of outermost L2 header.
29322 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_OUTERMOST \
29325 * Enumeration denoting NO_ROCE_L2 to support old drivers.
29326 * New driver L2 for only L2 traffic, ROCE for roce and l2 traffic
29328 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_TRAFFIC_MASK \
29330 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_TRAFFIC_SFT 4
29331 /* To support old drivers */
29332 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_TRAFFIC_NO_ROCE_L2 \
29333 (UINT32_C(0x0) << 4)
29334 /* Only L2 traffic */
29335 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_TRAFFIC_L2 \
29336 (UINT32_C(0x1) << 4)
29337 /* Roce & L2 traffic */
29338 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_TRAFFIC_ROCE \
29339 (UINT32_C(0x2) << 4)
29340 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_TRAFFIC_LAST \
29341 HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_TRAFFIC_ROCE
29343 * Setting of this flag indicates that no XDP filter is created with
29345 * 0 - legacy behavior, XDP filter is created with L2 filter
29346 * 1 - XDP filter won't be created with L2 filter
29348 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_XDP_DISABLE \
29351 * Setting this flag to 1 indicate the L2 fields in this command
29352 * pertain to source fields. Setting this flag to 0 indicate the
29353 * L2 fields in this command pertain to the destination fields
29354 * and this is the default/legacy behavior.
29356 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_SOURCE_VALID \
29360 * This bit must be '1' for the l2_addr field to be
29363 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_ADDR \
29366 * This bit must be '1' for the l2_addr_mask field to be
29369 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_ADDR_MASK \
29372 * This bit must be '1' for the l2_ovlan field to be
29375 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_OVLAN \
29378 * This bit must be '1' for the l2_ovlan_mask field to be
29381 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_OVLAN_MASK \
29384 * This bit must be '1' for the l2_ivlan field to be
29387 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN \
29390 * This bit must be '1' for the l2_ivlan_mask field to be
29393 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN_MASK \
29396 * This bit must be '1' for the t_l2_addr field to be
29399 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_T_L2_ADDR \
29402 * This bit must be '1' for the t_l2_addr_mask field to be
29405 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_T_L2_ADDR_MASK \
29408 * This bit must be '1' for the t_l2_ovlan field to be
29411 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_T_L2_OVLAN \
29414 * This bit must be '1' for the t_l2_ovlan_mask field to be
29417 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_T_L2_OVLAN_MASK \
29420 * This bit must be '1' for the t_l2_ivlan field to be
29423 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_T_L2_IVLAN \
29426 * This bit must be '1' for the t_l2_ivlan_mask field to be
29429 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_T_L2_IVLAN_MASK \
29432 * This bit must be '1' for the src_type field to be
29435 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_SRC_TYPE \
29438 * This bit must be '1' for the src_id field to be
29441 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_SRC_ID \
29444 * This bit must be '1' for the tunnel_type field to be
29447 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_TUNNEL_TYPE \
29450 * This bit must be '1' for the dst_id field to be
29453 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_DST_ID \
29456 * This bit must be '1' for the mirror_vnic_id field to be
29459 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_MIRROR_VNIC_ID \
29462 * This bit must be '1' for the num_vlans field to be
29465 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_NUM_VLANS \
29468 * This bit must be '1' for the t_num_vlans field to be
29471 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_T_NUM_VLANS \
29474 * This value sets the match value for the L2 MAC address.
29475 * Destination MAC address for RX path.
29476 * Source MAC address for TX path.
29478 uint8_t l2_addr[6];
29479 /* This value sets the match value for the number of VLANs. */
29482 * This value sets the match value for the number of VLANs
29483 * in the tunnel headers.
29485 uint8_t t_num_vlans;
29487 * This value sets the mask value for the L2 address.
29488 * A value of 0 will mask the corresponding bit from
29491 uint8_t l2_addr_mask[6];
29492 /* This value sets VLAN ID value for outer VLAN. */
29495 * This value sets the mask value for the ovlan id.
29496 * A value of 0 will mask the corresponding bit from
29499 uint16_t l2_ovlan_mask;
29500 /* This value sets VLAN ID value for inner VLAN. */
29503 * This value sets the mask value for the ivlan id.
29504 * A value of 0 will mask the corresponding bit from
29507 uint16_t l2_ivlan_mask;
29508 uint8_t unused_1[2];
29510 * This value sets the match value for the tunnel
29512 * Destination MAC address for RX path.
29513 * Source MAC address for TX path.
29515 uint8_t t_l2_addr[6];
29516 uint8_t unused_2[2];
29518 * This value sets the mask value for the tunnel L2
29520 * A value of 0 will mask the corresponding bit from
29523 uint8_t t_l2_addr_mask[6];
29524 /* This value sets VLAN ID value for tunnel outer VLAN. */
29525 uint16_t t_l2_ovlan;
29527 * This value sets the mask value for the tunnel ovlan id.
29528 * A value of 0 will mask the corresponding bit from
29531 uint16_t t_l2_ovlan_mask;
29532 /* This value sets VLAN ID value for tunnel inner VLAN. */
29533 uint16_t t_l2_ivlan;
29535 * This value sets the mask value for the tunnel ivlan id.
29536 * A value of 0 will mask the corresponding bit from
29539 uint16_t t_l2_ivlan_mask;
29540 /* This value identifies the type of source of the packet. */
29543 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_SRC_TYPE_NPORT UINT32_C(0x0)
29544 /* Physical function */
29545 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_SRC_TYPE_PF UINT32_C(0x1)
29546 /* Virtual function */
29547 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_SRC_TYPE_VF UINT32_C(0x2)
29548 /* Virtual NIC of a function */
29549 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_SRC_TYPE_VNIC UINT32_C(0x3)
29550 /* Embedded processor for CFA management */
29551 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_SRC_TYPE_KONG UINT32_C(0x4)
29552 /* Embedded processor for OOB management */
29553 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_SRC_TYPE_APE UINT32_C(0x5)
29554 /* Embedded processor for RoCE */
29555 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_SRC_TYPE_BONO UINT32_C(0x6)
29556 /* Embedded processor for network proxy functions */
29557 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_SRC_TYPE_TANG UINT32_C(0x7)
29558 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_SRC_TYPE_LAST \
29559 HWRM_CFA_L2_FILTER_ALLOC_INPUT_SRC_TYPE_TANG
29562 * This value is the id of the source.
29563 * For a network port, it represents port_id.
29564 * For a physical function, it represents fid.
29565 * For a virtual function, it represents vf_id.
29566 * For a vnic, it represents vnic_id.
29567 * For embedded processors, this id is not valid.
29570 * 1. The function ID is implied if it src_id is
29571 * not provided for a src_type that is either
29575 uint8_t tunnel_type;
29577 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_TUNNEL_TYPE_NONTUNNEL \
29579 /* Virtual eXtensible Local Area Network (VXLAN) */
29580 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_TUNNEL_TYPE_VXLAN \
29582 /* Network Virtualization Generic Routing Encapsulation (NVGRE) */
29583 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_TUNNEL_TYPE_NVGRE \
29585 /* Generic Routing Encapsulation (GRE) inside Ethernet payload */
29586 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_TUNNEL_TYPE_L2GRE \
29589 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_TUNNEL_TYPE_IPIP \
29591 /* Generic Network Virtualization Encapsulation (Geneve) */
29592 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_TUNNEL_TYPE_GENEVE \
29594 /* Multi-Protocol Label Switching (MPLS) */
29595 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_TUNNEL_TYPE_MPLS \
29597 /* Stateless Transport Tunnel (STT) */
29598 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_TUNNEL_TYPE_STT \
29600 /* Generic Routing Encapsulation (GRE) inside IP datagram payload */
29601 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_TUNNEL_TYPE_IPGRE \
29603 /* IPV4 over virtual eXtensible Local Area Network (IPV4oVXLAN) */
29604 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_TUNNEL_TYPE_VXLAN_V4 \
29606 /* Enhance Generic Routing Encapsulation (GRE version 1) inside IP datagram payload */
29607 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_TUNNEL_TYPE_IPGRE_V1 \
29609 /* Use fixed layer 2 ether type of 0xFFFF */
29610 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_TUNNEL_TYPE_L2_ETYPE \
29612 /* IPV6 over virtual eXtensible Local Area Network with GPE header (IPV6oVXLANGPE) */
29613 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_TUNNEL_TYPE_VXLAN_GPE_V6 \
29615 /* Any tunneled traffic */
29616 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_TUNNEL_TYPE_ANYTUNNEL \
29618 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_TUNNEL_TYPE_LAST \
29619 HWRM_CFA_L2_FILTER_ALLOC_INPUT_TUNNEL_TYPE_ANYTUNNEL
29622 * If set, this value shall represent the
29623 * Logical VNIC ID of the destination VNIC for the RX
29624 * path and network port id of the destination port for
29629 * Logical VNIC ID of the VNIC where traffic is
29632 uint16_t mirror_vnic_id;
29634 * This hint is provided to help in placing
29635 * the filter in the filter table.
29638 /* No preference */
29639 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_PRI_HINT_NO_PREFER \
29641 /* Above the given filter */
29642 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_PRI_HINT_ABOVE_FILTER \
29644 /* Below the given filter */
29645 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_PRI_HINT_BELOW_FILTER \
29647 /* As high as possible */
29648 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_PRI_HINT_MAX \
29650 /* As low as possible */
29651 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_PRI_HINT_MIN \
29653 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_PRI_HINT_LAST \
29654 HWRM_CFA_L2_FILTER_ALLOC_INPUT_PRI_HINT_MIN
29658 * This is the ID of the filter that goes along with
29661 * This field is valid only for the following values.
29662 * 1 - Above the given filter
29663 * 2 - Below the given filter
29665 uint64_t l2_filter_id_hint;
29668 /* hwrm_cfa_l2_filter_alloc_output (size:192b/24B) */
29669 struct hwrm_cfa_l2_filter_alloc_output {
29670 /* The specific error status for the command. */
29671 uint16_t error_code;
29672 /* The HWRM command request type. */
29674 /* The sequence ID from the original command. */
29676 /* The length of the response data in number of bytes. */
29679 * This value identifies a set of CFA data structures used for an L2
29682 uint64_t l2_filter_id;
29684 * The flow id value in bit 0-29 is the actual ID of the flow
29685 * associated with this filter and it shall be used to match
29686 * and associate the flow identifier returned in completion
29687 * records. A value of 0xFFFFFFFF in the 32-bit flow_id field
29688 * shall indicate no valid flow id.
29691 /* Indicate the flow id value. */
29692 #define HWRM_CFA_L2_FILTER_ALLOC_OUTPUT_FLOW_ID_VALUE_MASK \
29693 UINT32_C(0x3fffffff)
29694 #define HWRM_CFA_L2_FILTER_ALLOC_OUTPUT_FLOW_ID_VALUE_SFT 0
29695 /* Indicate type of the flow. */
29696 #define HWRM_CFA_L2_FILTER_ALLOC_OUTPUT_FLOW_ID_TYPE \
29697 UINT32_C(0x40000000)
29699 * If this bit set to 0, then it indicates that the flow is
29702 #define HWRM_CFA_L2_FILTER_ALLOC_OUTPUT_FLOW_ID_TYPE_INT \
29703 (UINT32_C(0x0) << 30)
29705 * If this bit is set to 1, then it indicates that the flow is
29708 #define HWRM_CFA_L2_FILTER_ALLOC_OUTPUT_FLOW_ID_TYPE_EXT \
29709 (UINT32_C(0x1) << 30)
29710 #define HWRM_CFA_L2_FILTER_ALLOC_OUTPUT_FLOW_ID_TYPE_LAST \
29711 HWRM_CFA_L2_FILTER_ALLOC_OUTPUT_FLOW_ID_TYPE_EXT
29712 /* Indicate the flow direction. */
29713 #define HWRM_CFA_L2_FILTER_ALLOC_OUTPUT_FLOW_ID_DIR \
29714 UINT32_C(0x80000000)
29715 /* If this bit set to 0, then it indicates rx flow. */
29716 #define HWRM_CFA_L2_FILTER_ALLOC_OUTPUT_FLOW_ID_DIR_RX \
29717 (UINT32_C(0x0) << 31)
29718 /* If this bit is set to 1, then it indicates that tx flow. */
29719 #define HWRM_CFA_L2_FILTER_ALLOC_OUTPUT_FLOW_ID_DIR_TX \
29720 (UINT32_C(0x1) << 31)
29721 #define HWRM_CFA_L2_FILTER_ALLOC_OUTPUT_FLOW_ID_DIR_LAST \
29722 HWRM_CFA_L2_FILTER_ALLOC_OUTPUT_FLOW_ID_DIR_TX
29723 uint8_t unused_0[3];
29725 * This field is used in Output records to indicate that the output
29726 * is completely written to RAM. This field should be read as '1'
29727 * to indicate that the output has been completely written.
29728 * When writing a command completion or response to an internal processor,
29729 * the order of writes has to be such that this field is written last.
29734 /***************************
29735 * hwrm_cfa_l2_filter_free *
29736 ***************************/
29739 /* hwrm_cfa_l2_filter_free_input (size:192b/24B) */
29740 struct hwrm_cfa_l2_filter_free_input {
29741 /* The HWRM command request type. */
29744 * The completion ring to send the completion event on. This should
29745 * be the NQ ID returned from the `nq_alloc` HWRM command.
29747 uint16_t cmpl_ring;
29749 * The sequence ID is used by the driver for tracking multiple
29750 * commands. This ID is treated as opaque data by the firmware and
29751 * the value is returned in the `hwrm_resp_hdr` upon completion.
29755 * The target ID of the command:
29756 * * 0x0-0xFFF8 - The function ID
29757 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
29758 * * 0xFFFD - Reserved for user-space HWRM interface
29761 uint16_t target_id;
29763 * A physical address pointer pointing to a host buffer that the
29764 * command's response data will be written. This can be either a host
29765 * physical address (HPA) or a guest physical address (GPA) and must
29766 * point to a physically contiguous block of memory.
29768 uint64_t resp_addr;
29770 * This value identifies a set of CFA data structures used for an L2
29773 uint64_t l2_filter_id;
29776 /* hwrm_cfa_l2_filter_free_output (size:128b/16B) */
29777 struct hwrm_cfa_l2_filter_free_output {
29778 /* The specific error status for the command. */
29779 uint16_t error_code;
29780 /* The HWRM command request type. */
29782 /* The sequence ID from the original command. */
29784 /* The length of the response data in number of bytes. */
29786 uint8_t unused_0[7];
29788 * This field is used in Output records to indicate that the output
29789 * is completely written to RAM. This field should be read as '1'
29790 * to indicate that the output has been completely written.
29791 * When writing a command completion or response to an internal processor,
29792 * the order of writes has to be such that this field is written last.
29797 /**************************
29798 * hwrm_cfa_l2_filter_cfg *
29799 **************************/
29802 /* hwrm_cfa_l2_filter_cfg_input (size:320b/40B) */
29803 struct hwrm_cfa_l2_filter_cfg_input {
29804 /* The HWRM command request type. */
29807 * The completion ring to send the completion event on. This should
29808 * be the NQ ID returned from the `nq_alloc` HWRM command.
29810 uint16_t cmpl_ring;
29812 * The sequence ID is used by the driver for tracking multiple
29813 * commands. This ID is treated as opaque data by the firmware and
29814 * the value is returned in the `hwrm_resp_hdr` upon completion.
29818 * The target ID of the command:
29819 * * 0x0-0xFFF8 - The function ID
29820 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
29821 * * 0xFFFD - Reserved for user-space HWRM interface
29824 uint16_t target_id;
29826 * A physical address pointer pointing to a host buffer that the
29827 * command's response data will be written. This can be either a host
29828 * physical address (HPA) or a guest physical address (GPA) and must
29829 * point to a physically contiguous block of memory.
29831 uint64_t resp_addr;
29834 * Enumeration denoting the RX, TX type of the resource.
29835 * This enumeration is used for resources that are similar for both
29836 * TX and RX paths of the chip.
29838 #define HWRM_CFA_L2_FILTER_CFG_INPUT_FLAGS_PATH \
29841 #define HWRM_CFA_L2_FILTER_CFG_INPUT_FLAGS_PATH_TX \
29844 #define HWRM_CFA_L2_FILTER_CFG_INPUT_FLAGS_PATH_RX \
29846 #define HWRM_CFA_L2_FILTER_CFG_INPUT_FLAGS_PATH_LAST \
29847 HWRM_CFA_L2_FILTER_CFG_INPUT_FLAGS_PATH_RX
29849 * Setting of this flag indicates drop action. If this flag is not set,
29850 * then it should be considered accept action.
29852 #define HWRM_CFA_L2_FILTER_CFG_INPUT_FLAGS_DROP \
29855 * Enumeration denoting NO_ROCE_L2 to support old drivers.
29856 * New driver L2 for only L2 traffic, ROCE for roce and l2 traffic
29858 #define HWRM_CFA_L2_FILTER_CFG_INPUT_FLAGS_TRAFFIC_MASK \
29860 #define HWRM_CFA_L2_FILTER_CFG_INPUT_FLAGS_TRAFFIC_SFT 2
29861 /* To support old drivers */
29862 #define HWRM_CFA_L2_FILTER_CFG_INPUT_FLAGS_TRAFFIC_NO_ROCE_L2 \
29863 (UINT32_C(0x0) << 2)
29864 /* Only L2 traffic */
29865 #define HWRM_CFA_L2_FILTER_CFG_INPUT_FLAGS_TRAFFIC_L2 \
29866 (UINT32_C(0x1) << 2)
29867 /* Roce & L2 traffic */
29868 #define HWRM_CFA_L2_FILTER_CFG_INPUT_FLAGS_TRAFFIC_ROCE \
29869 (UINT32_C(0x2) << 2)
29870 #define HWRM_CFA_L2_FILTER_CFG_INPUT_FLAGS_TRAFFIC_LAST \
29871 HWRM_CFA_L2_FILTER_CFG_INPUT_FLAGS_TRAFFIC_ROCE
29874 * This bit must be '1' for the dst_id field to be
29877 #define HWRM_CFA_L2_FILTER_CFG_INPUT_ENABLES_DST_ID \
29880 * This bit must be '1' for the new_mirror_vnic_id field to be
29883 #define HWRM_CFA_L2_FILTER_CFG_INPUT_ENABLES_NEW_MIRROR_VNIC_ID \
29886 * This value identifies a set of CFA data structures used for an L2
29889 uint64_t l2_filter_id;
29891 * If set, this value shall represent the
29892 * Logical VNIC ID of the destination VNIC for the RX
29893 * path and network port id of the destination port for
29898 * New Logical VNIC ID of the VNIC where traffic is
29901 uint32_t new_mirror_vnic_id;
29904 /* hwrm_cfa_l2_filter_cfg_output (size:128b/16B) */
29905 struct hwrm_cfa_l2_filter_cfg_output {
29906 /* The specific error status for the command. */
29907 uint16_t error_code;
29908 /* The HWRM command request type. */
29910 /* The sequence ID from the original command. */
29912 /* The length of the response data in number of bytes. */
29914 uint8_t unused_0[7];
29916 * This field is used in Output records to indicate that the output
29917 * is completely written to RAM. This field should be read as '1'
29918 * to indicate that the output has been completely written.
29919 * When writing a command completion or response to an internal processor,
29920 * the order of writes has to be such that this field is written last.
29925 /***************************
29926 * hwrm_cfa_l2_set_rx_mask *
29927 ***************************/
29930 /* hwrm_cfa_l2_set_rx_mask_input (size:448b/56B) */
29931 struct hwrm_cfa_l2_set_rx_mask_input {
29932 /* The HWRM command request type. */
29935 * The completion ring to send the completion event on. This should
29936 * be the NQ ID returned from the `nq_alloc` HWRM command.
29938 uint16_t cmpl_ring;
29940 * The sequence ID is used by the driver for tracking multiple
29941 * commands. This ID is treated as opaque data by the firmware and
29942 * the value is returned in the `hwrm_resp_hdr` upon completion.
29946 * The target ID of the command:
29947 * * 0x0-0xFFF8 - The function ID
29948 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
29949 * * 0xFFFD - Reserved for user-space HWRM interface
29952 uint16_t target_id;
29954 * A physical address pointer pointing to a host buffer that the
29955 * command's response data will be written. This can be either a host
29956 * physical address (HPA) or a guest physical address (GPA) and must
29957 * point to a physically contiguous block of memory.
29959 uint64_t resp_addr;
29964 * When this bit is '1', the function is requested to accept
29965 * multi-cast packets specified by the multicast addr table.
29967 #define HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_MCAST \
29970 * When this bit is '1', the function is requested to accept
29971 * all multi-cast packets.
29973 #define HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_ALL_MCAST \
29976 * When this bit is '1', the function is requested to accept
29977 * broadcast packets.
29979 #define HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_BCAST \
29982 * When this bit is '1', the function is requested to be
29983 * put in the promiscuous mode.
29985 * The HWRM should accept any function to set up
29986 * promiscuous mode.
29988 * The HWRM shall follow the semantics below for the
29989 * promiscuous mode support.
29990 * # When partitioning is not enabled on a port
29991 * (i.e. single PF on the port), then the PF shall
29992 * be allowed to be in the promiscuous mode. When the
29993 * PF is in the promiscuous mode, then it shall
29994 * receive all host bound traffic on that port.
29995 * # When partitioning is enabled on a port
29996 * (i.e. multiple PFs per port) and a PF on that
29997 * port is in the promiscuous mode, then the PF
29998 * receives all traffic within that partition as
29999 * identified by a unique identifier for the
30000 * PF (e.g. S-Tag). If a unique outer VLAN
30001 * for the PF is specified, then the setting of
30002 * promiscuous mode on that PF shall result in the
30003 * PF receiving all host bound traffic with matching
30005 * # A VF shall can be set in the promiscuous mode.
30006 * In the promiscuous mode, the VF does not receive any
30007 * traffic unless a unique outer VLAN for the
30008 * VF is specified. If a unique outer VLAN
30009 * for the VF is specified, then the setting of
30010 * promiscuous mode on that VF shall result in the
30011 * VF receiving all host bound traffic with the
30012 * matching outer VLAN.
30013 * # The HWRM shall allow the setting of promiscuous
30014 * mode on a function independently from the
30015 * promiscuous mode settings on other functions.
30017 #define HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_PROMISCUOUS \
30020 * If this flag is set, the corresponding RX
30021 * filters shall be set up to cover multicast/broadcast
30022 * filters for the outermost Layer 2 destination MAC
30025 #define HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_OUTERMOST \
30028 * If this flag is set, the corresponding RX
30029 * filters shall be set up to cover multicast/broadcast
30030 * filters for the VLAN-tagged packets that match the
30031 * TPID and VID fields of VLAN tags in the VLAN tag
30032 * table specified in this command.
30034 #define HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_VLANONLY \
30037 * If this flag is set, the corresponding RX
30038 * filters shall be set up to cover multicast/broadcast
30039 * filters for non-VLAN tagged packets and VLAN-tagged
30040 * packets that match the TPID and VID fields of VLAN
30041 * tags in the VLAN tag table specified in this command.
30043 #define HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_VLAN_NONVLAN \
30046 * If this flag is set, the corresponding RX
30047 * filters shall be set up to cover multicast/broadcast
30048 * filters for non-VLAN tagged packets and VLAN-tagged
30049 * packets matching any VLAN tag.
30051 * If this flag is set, then the HWRM shall ignore
30052 * VLAN tags specified in vlan_tag_tbl.
30054 * If none of vlanonly, vlan_nonvlan, and anyvlan_nonvlan
30055 * flags is set, then the HWRM shall ignore
30056 * VLAN tags specified in vlan_tag_tbl.
30058 * The HWRM client shall set at most one flag out of
30059 * vlanonly, vlan_nonvlan, and anyvlan_nonvlan.
30061 #define HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_ANYVLAN_NONVLAN \
30063 /* This is the address for mcast address tbl. */
30064 uint64_t mc_tbl_addr;
30066 * This value indicates how many entries in mc_tbl are valid.
30067 * Each entry is 6 bytes.
30069 uint32_t num_mc_entries;
30070 uint8_t unused_0[4];
30072 * This is the address for VLAN tag table.
30073 * Each VLAN entry in the table is 4 bytes of a VLAN tag
30074 * including TPID, PCP, DEI, and VID fields in network byte
30077 uint64_t vlan_tag_tbl_addr;
30079 * This value indicates how many entries in vlan_tag_tbl are
30080 * valid. Each entry is 4 bytes.
30082 uint32_t num_vlan_tags;
30083 uint8_t unused_1[4];
30086 /* hwrm_cfa_l2_set_rx_mask_output (size:128b/16B) */
30087 struct hwrm_cfa_l2_set_rx_mask_output {
30088 /* The specific error status for the command. */
30089 uint16_t error_code;
30090 /* The HWRM command request type. */
30092 /* The sequence ID from the original command. */
30094 /* The length of the response data in number of bytes. */
30096 uint8_t unused_0[7];
30098 * This field is used in Output records to indicate that the output
30099 * is completely written to RAM. This field should be read as '1'
30100 * to indicate that the output has been completely written.
30101 * When writing a command completion or response to an internal processor,
30102 * the order of writes has to be such that this field is written last.
30107 /* hwrm_cfa_l2_set_rx_mask_cmd_err (size:64b/8B) */
30108 struct hwrm_cfa_l2_set_rx_mask_cmd_err {
30110 * command specific error codes that goes to
30111 * the cmd_err field in Common HWRM Error Response.
30114 /* Unknown error */
30115 #define HWRM_CFA_L2_SET_RX_MASK_CMD_ERR_CODE_UNKNOWN \
30117 /* Unable to complete operation due to conflict with Ntuple Filter */
30118 #define HWRM_CFA_L2_SET_RX_MASK_CMD_ERR_CODE_NTUPLE_FILTER_CONFLICT_ERR \
30120 #define HWRM_CFA_L2_SET_RX_MASK_CMD_ERR_CODE_LAST \
30121 HWRM_CFA_L2_SET_RX_MASK_CMD_ERR_CODE_NTUPLE_FILTER_CONFLICT_ERR
30122 uint8_t unused_0[7];
30125 /*******************************
30126 * hwrm_cfa_vlan_antispoof_cfg *
30127 *******************************/
30130 /* hwrm_cfa_vlan_antispoof_cfg_input (size:256b/32B) */
30131 struct hwrm_cfa_vlan_antispoof_cfg_input {
30132 /* The HWRM command request type. */
30135 * The completion ring to send the completion event on. This should
30136 * be the NQ ID returned from the `nq_alloc` HWRM command.
30138 uint16_t cmpl_ring;
30140 * The sequence ID is used by the driver for tracking multiple
30141 * commands. This ID is treated as opaque data by the firmware and
30142 * the value is returned in the `hwrm_resp_hdr` upon completion.
30146 * The target ID of the command:
30147 * * 0x0-0xFFF8 - The function ID
30148 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
30149 * * 0xFFFD - Reserved for user-space HWRM interface
30152 uint16_t target_id;
30154 * A physical address pointer pointing to a host buffer that the
30155 * command's response data will be written. This can be either a host
30156 * physical address (HPA) or a guest physical address (GPA) and must
30157 * point to a physically contiguous block of memory.
30159 uint64_t resp_addr;
30161 * Function ID of the function that is being configured.
30162 * Only valid for a VF FID configured by the PF.
30165 uint8_t unused_0[2];
30166 /* Number of VLAN entries in the vlan_tag_mask_tbl. */
30167 uint32_t num_vlan_entries;
30169 * The vlan_tag_mask_tbl_addr is the DMA address of the VLAN
30170 * antispoof table. Each table entry contains the 16-bit TPID
30171 * (0x8100 or 0x88a8 only), 16-bit VLAN ID, and a 16-bit mask,
30172 * all in network order to match hwrm_cfa_l2_set_rx_mask.
30173 * For an individual VLAN entry, the mask value should be 0xfff
30174 * for the 12-bit VLAN ID.
30176 uint64_t vlan_tag_mask_tbl_addr;
30179 /* hwrm_cfa_vlan_antispoof_cfg_output (size:128b/16B) */
30180 struct hwrm_cfa_vlan_antispoof_cfg_output {
30181 /* The specific error status for the command. */
30182 uint16_t error_code;
30183 /* The HWRM command request type. */
30185 /* The sequence ID from the original command. */
30187 /* The length of the response data in number of bytes. */
30189 uint8_t unused_0[7];
30191 * This field is used in Output records to indicate that the output
30192 * is completely written to RAM. This field should be read as '1'
30193 * to indicate that the output has been completely written.
30194 * When writing a command completion or response to an internal processor,
30195 * the order of writes has to be such that this field is written last.
30200 /********************************
30201 * hwrm_cfa_vlan_antispoof_qcfg *
30202 ********************************/
30205 /* hwrm_cfa_vlan_antispoof_qcfg_input (size:256b/32B) */
30206 struct hwrm_cfa_vlan_antispoof_qcfg_input {
30207 /* The HWRM command request type. */
30210 * The completion ring to send the completion event on. This should
30211 * be the NQ ID returned from the `nq_alloc` HWRM command.
30213 uint16_t cmpl_ring;
30215 * The sequence ID is used by the driver for tracking multiple
30216 * commands. This ID is treated as opaque data by the firmware and
30217 * the value is returned in the `hwrm_resp_hdr` upon completion.
30221 * The target ID of the command:
30222 * * 0x0-0xFFF8 - The function ID
30223 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
30224 * * 0xFFFD - Reserved for user-space HWRM interface
30227 uint16_t target_id;
30229 * A physical address pointer pointing to a host buffer that the
30230 * command's response data will be written. This can be either a host
30231 * physical address (HPA) or a guest physical address (GPA) and must
30232 * point to a physically contiguous block of memory.
30234 uint64_t resp_addr;
30236 * Function ID of the function that is being queried.
30237 * Only valid for a VF FID queried by the PF.
30240 uint8_t unused_0[2];
30242 * Maximum number of VLAN entries the firmware is allowed to DMA
30243 * to vlan_tag_mask_tbl.
30245 uint32_t max_vlan_entries;
30247 * The vlan_tag_mask_tbl_addr is the DMA address of the VLAN
30248 * antispoof table to which firmware will DMA to. Each table
30249 * entry will contain the 16-bit TPID (0x8100 or 0x88a8 only),
30250 * 16-bit VLAN ID, and a 16-bit mask, all in network order to
30251 * match hwrm_cfa_l2_set_rx_mask. For an individual VLAN entry,
30252 * the mask value should be 0xfff for the 12-bit VLAN ID.
30254 uint64_t vlan_tag_mask_tbl_addr;
30257 /* hwrm_cfa_vlan_antispoof_qcfg_output (size:128b/16B) */
30258 struct hwrm_cfa_vlan_antispoof_qcfg_output {
30259 /* The specific error status for the command. */
30260 uint16_t error_code;
30261 /* The HWRM command request type. */
30263 /* The sequence ID from the original command. */
30265 /* The length of the response data in number of bytes. */
30267 /* Number of valid entries DMAd by firmware to vlan_tag_mask_tbl. */
30268 uint32_t num_vlan_entries;
30269 uint8_t unused_0[3];
30271 * This field is used in Output records to indicate that the output
30272 * is completely written to RAM. This field should be read as '1'
30273 * to indicate that the output has been completely written.
30274 * When writing a command completion or response to an internal processor,
30275 * the order of writes has to be such that this field is written last.
30280 /********************************
30281 * hwrm_cfa_tunnel_filter_alloc *
30282 ********************************/
30285 /* hwrm_cfa_tunnel_filter_alloc_input (size:704b/88B) */
30286 struct hwrm_cfa_tunnel_filter_alloc_input {
30287 /* The HWRM command request type. */
30290 * The completion ring to send the completion event on. This should
30291 * be the NQ ID returned from the `nq_alloc` HWRM command.
30293 uint16_t cmpl_ring;
30295 * The sequence ID is used by the driver for tracking multiple
30296 * commands. This ID is treated as opaque data by the firmware and
30297 * the value is returned in the `hwrm_resp_hdr` upon completion.
30301 * The target ID of the command:
30302 * * 0x0-0xFFF8 - The function ID
30303 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
30304 * * 0xFFFD - Reserved for user-space HWRM interface
30307 uint16_t target_id;
30309 * A physical address pointer pointing to a host buffer that the
30310 * command's response data will be written. This can be either a host
30311 * physical address (HPA) or a guest physical address (GPA) and must
30312 * point to a physically contiguous block of memory.
30314 uint64_t resp_addr;
30316 /* Setting of this flag indicates the applicability to the loopback path. */
30317 #define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_FLAGS_LOOPBACK \
30321 * This bit must be '1' for the l2_filter_id field to be
30324 #define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_ENABLES_L2_FILTER_ID \
30327 * This bit must be '1' for the l2_addr field to be
30330 #define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_ENABLES_L2_ADDR \
30333 * This bit must be '1' for the l2_ivlan field to be
30336 #define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN \
30339 * This bit must be '1' for the l3_addr field to be
30342 #define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_ENABLES_L3_ADDR \
30345 * This bit must be '1' for the l3_addr_type field to be
30348 #define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_ENABLES_L3_ADDR_TYPE \
30351 * This bit must be '1' for the t_l3_addr_type field to be
30354 #define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_ENABLES_T_L3_ADDR_TYPE \
30357 * This bit must be '1' for the t_l3_addr field to be
30360 #define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_ENABLES_T_L3_ADDR \
30363 * This bit must be '1' for the tunnel_type field to be
30366 #define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_ENABLES_TUNNEL_TYPE \
30369 * This bit must be '1' for the vni field to be
30372 #define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_ENABLES_VNI \
30375 * This bit must be '1' for the dst_vnic_id field to be
30378 #define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_ENABLES_DST_VNIC_ID \
30381 * This bit must be '1' for the mirror_vnic_id field to be
30384 #define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_ENABLES_MIRROR_VNIC_ID \
30387 * This value identifies a set of CFA data structures used for an L2
30390 uint64_t l2_filter_id;
30392 * This value sets the match value for the inner L2
30394 * Destination MAC address for RX path.
30395 * Source MAC address for TX path.
30397 uint8_t l2_addr[6];
30399 * This value sets VLAN ID value for inner VLAN.
30400 * Only 12-bits of VLAN ID are used in setting the filter.
30404 * The value of inner destination IP address to be used in filtering.
30405 * For IPv4, first four bytes represent the IP address.
30407 uint32_t l3_addr[4];
30409 * The value of tunnel destination IP address to be used in filtering.
30410 * For IPv4, first four bytes represent the IP address.
30412 uint32_t t_l3_addr[4];
30414 * This value indicates the type of inner IP address.
30417 * All others are invalid.
30419 uint8_t l3_addr_type;
30421 * This value indicates the type of tunnel IP address.
30424 * All others are invalid.
30426 uint8_t t_l3_addr_type;
30428 uint8_t tunnel_type;
30430 #define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_TUNNEL_TYPE_NONTUNNEL \
30432 /* Virtual eXtensible Local Area Network (VXLAN) */
30433 #define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_TUNNEL_TYPE_VXLAN \
30435 /* Network Virtualization Generic Routing Encapsulation (NVGRE) */
30436 #define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_TUNNEL_TYPE_NVGRE \
30438 /* Generic Routing Encapsulation (GRE) inside Ethernet payload */
30439 #define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_TUNNEL_TYPE_L2GRE \
30442 #define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_TUNNEL_TYPE_IPIP \
30444 /* Generic Network Virtualization Encapsulation (Geneve) */
30445 #define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_TUNNEL_TYPE_GENEVE \
30447 /* Multi-Protocol Label Switching (MPLS) */
30448 #define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_TUNNEL_TYPE_MPLS \
30450 /* Stateless Transport Tunnel (STT) */
30451 #define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_TUNNEL_TYPE_STT \
30453 /* Generic Routing Encapsulation (GRE) inside IP datagram payload */
30454 #define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_TUNNEL_TYPE_IPGRE \
30456 /* IPV4 over virtual eXtensible Local Area Network (IPV4oVXLAN) */
30457 #define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_TUNNEL_TYPE_VXLAN_V4 \
30459 /* Enhance Generic Routing Encapsulation (GRE version 1) inside IP datagram payload */
30460 #define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_TUNNEL_TYPE_IPGRE_V1 \
30462 /* Use fixed layer 2 ether type of 0xFFFF */
30463 #define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_TUNNEL_TYPE_L2_ETYPE \
30465 /* IPV6 over virtual eXtensible Local Area Network with GPE header (IPV6oVXLANGPE) */
30466 #define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_TUNNEL_TYPE_VXLAN_GPE_V6 \
30468 /* Any tunneled traffic */
30469 #define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_TUNNEL_TYPE_ANYTUNNEL \
30471 #define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_TUNNEL_TYPE_LAST \
30472 HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_TUNNEL_TYPE_ANYTUNNEL
30474 * tunnel_flags allows the user to indicate the tunnel tag detection
30475 * for the tunnel type specified in tunnel_type.
30477 uint8_t tunnel_flags;
30479 * If the tunnel_type is geneve, then this bit indicates if we
30480 * need to match the geneve OAM packet.
30481 * If the tunnel_type is nvgre or gre, then this bit indicates if
30482 * we need to detect checksum present bit in geneve header.
30483 * If the tunnel_type is mpls, then this bit indicates if we need
30484 * to match mpls packet with explicit IPV4/IPV6 null header.
30486 #define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_TUNNEL_FLAGS_TUN_FLAGS_OAM_CHECKSUM_EXPLHDR \
30489 * If the tunnel_type is geneve, then this bit indicates if we
30490 * need to detect the critical option bit set in the oam packet.
30491 * If the tunnel_type is nvgre or gre, then this bit indicates
30492 * if we need to match nvgre packets with key present bit set in
30494 * If the tunnel_type is mpls, then this bit indicates if we
30495 * need to match mpls packet with S bit from inner/second label.
30497 #define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_TUNNEL_FLAGS_TUN_FLAGS_CRITICAL_OPT_S1 \
30500 * If the tunnel_type is geneve, then this bit indicates if we
30501 * need to match geneve packet with extended header bit set in
30503 * If the tunnel_type is nvgre or gre, then this bit indicates
30504 * if we need to match nvgre packets with sequence number
30505 * present bit set in gre header.
30506 * If the tunnel_type is mpls, then this bit indicates if we
30507 * need to match mpls packet with S bit from out/first label.
30509 #define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_TUNNEL_FLAGS_TUN_FLAGS_EXTHDR_SEQNUM_S0 \
30512 * Virtual Network Identifier (VNI). Only valid with
30513 * tunnel_types VXLAN, NVGRE, and Geneve.
30514 * Only lower 24-bits of VNI field are used
30515 * in setting up the filter.
30518 /* Logical VNIC ID of the destination VNIC. */
30519 uint32_t dst_vnic_id;
30521 * Logical VNIC ID of the VNIC where traffic is
30524 uint32_t mirror_vnic_id;
30527 /* hwrm_cfa_tunnel_filter_alloc_output (size:192b/24B) */
30528 struct hwrm_cfa_tunnel_filter_alloc_output {
30529 /* The specific error status for the command. */
30530 uint16_t error_code;
30531 /* The HWRM command request type. */
30533 /* The sequence ID from the original command. */
30535 /* The length of the response data in number of bytes. */
30537 /* This value is an opaque id into CFA data structures. */
30538 uint64_t tunnel_filter_id;
30540 * The flow id value in bit 0-29 is the actual ID of the flow
30541 * associated with this filter and it shall be used to match
30542 * and associate the flow identifier returned in completion
30543 * records. A value of 0xFFFFFFFF in the 32-bit flow_id field
30544 * shall indicate no valid flow id.
30547 /* Indicate the flow id value. */
30548 #define HWRM_CFA_TUNNEL_FILTER_ALLOC_OUTPUT_FLOW_ID_VALUE_MASK \
30549 UINT32_C(0x3fffffff)
30550 #define HWRM_CFA_TUNNEL_FILTER_ALLOC_OUTPUT_FLOW_ID_VALUE_SFT 0
30551 /* Indicate type of the flow. */
30552 #define HWRM_CFA_TUNNEL_FILTER_ALLOC_OUTPUT_FLOW_ID_TYPE \
30553 UINT32_C(0x40000000)
30555 * If this bit set to 0, then it indicates that the flow is
30558 #define HWRM_CFA_TUNNEL_FILTER_ALLOC_OUTPUT_FLOW_ID_TYPE_INT \
30559 (UINT32_C(0x0) << 30)
30561 * If this bit is set to 1, then it indicates that the flow is
30564 #define HWRM_CFA_TUNNEL_FILTER_ALLOC_OUTPUT_FLOW_ID_TYPE_EXT \
30565 (UINT32_C(0x1) << 30)
30566 #define HWRM_CFA_TUNNEL_FILTER_ALLOC_OUTPUT_FLOW_ID_TYPE_LAST \
30567 HWRM_CFA_TUNNEL_FILTER_ALLOC_OUTPUT_FLOW_ID_TYPE_EXT
30568 /* Indicate the flow direction. */
30569 #define HWRM_CFA_TUNNEL_FILTER_ALLOC_OUTPUT_FLOW_ID_DIR \
30570 UINT32_C(0x80000000)
30571 /* If this bit set to 0, then it indicates rx flow. */
30572 #define HWRM_CFA_TUNNEL_FILTER_ALLOC_OUTPUT_FLOW_ID_DIR_RX \
30573 (UINT32_C(0x0) << 31)
30574 /* If this bit is set to 1, then it indicates that tx flow. */
30575 #define HWRM_CFA_TUNNEL_FILTER_ALLOC_OUTPUT_FLOW_ID_DIR_TX \
30576 (UINT32_C(0x1) << 31)
30577 #define HWRM_CFA_TUNNEL_FILTER_ALLOC_OUTPUT_FLOW_ID_DIR_LAST \
30578 HWRM_CFA_TUNNEL_FILTER_ALLOC_OUTPUT_FLOW_ID_DIR_TX
30579 uint8_t unused_0[3];
30581 * This field is used in Output records to indicate that the output
30582 * is completely written to RAM. This field should be read as '1'
30583 * to indicate that the output has been completely written.
30584 * When writing a command completion or response to an internal processor,
30585 * the order of writes has to be such that this field is written last.
30590 /*******************************
30591 * hwrm_cfa_tunnel_filter_free *
30592 *******************************/
30595 /* hwrm_cfa_tunnel_filter_free_input (size:192b/24B) */
30596 struct hwrm_cfa_tunnel_filter_free_input {
30597 /* The HWRM command request type. */
30600 * The completion ring to send the completion event on. This should
30601 * be the NQ ID returned from the `nq_alloc` HWRM command.
30603 uint16_t cmpl_ring;
30605 * The sequence ID is used by the driver for tracking multiple
30606 * commands. This ID is treated as opaque data by the firmware and
30607 * the value is returned in the `hwrm_resp_hdr` upon completion.
30611 * The target ID of the command:
30612 * * 0x0-0xFFF8 - The function ID
30613 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
30614 * * 0xFFFD - Reserved for user-space HWRM interface
30617 uint16_t target_id;
30619 * A physical address pointer pointing to a host buffer that the
30620 * command's response data will be written. This can be either a host
30621 * physical address (HPA) or a guest physical address (GPA) and must
30622 * point to a physically contiguous block of memory.
30624 uint64_t resp_addr;
30625 /* This value is an opaque id into CFA data structures. */
30626 uint64_t tunnel_filter_id;
30629 /* hwrm_cfa_tunnel_filter_free_output (size:128b/16B) */
30630 struct hwrm_cfa_tunnel_filter_free_output {
30631 /* The specific error status for the command. */
30632 uint16_t error_code;
30633 /* The HWRM command request type. */
30635 /* The sequence ID from the original command. */
30637 /* The length of the response data in number of bytes. */
30639 uint8_t unused_0[7];
30641 * This field is used in Output records to indicate that the output
30642 * is completely written to RAM. This field should be read as '1'
30643 * to indicate that the output has been completely written.
30644 * When writing a command completion or response to an internal processor,
30645 * the order of writes has to be such that this field is written last.
30650 /***************************************
30651 * hwrm_cfa_redirect_tunnel_type_alloc *
30652 ***************************************/
30655 /* hwrm_cfa_redirect_tunnel_type_alloc_input (size:192b/24B) */
30656 struct hwrm_cfa_redirect_tunnel_type_alloc_input {
30657 /* The HWRM command request type. */
30660 * The completion ring to send the completion event on. This should
30661 * be the NQ ID returned from the `nq_alloc` HWRM command.
30663 uint16_t cmpl_ring;
30665 * The sequence ID is used by the driver for tracking multiple
30666 * commands. This ID is treated as opaque data by the firmware and
30667 * the value is returned in the `hwrm_resp_hdr` upon completion.
30671 * The target ID of the command:
30672 * * 0x0-0xFFF8 - The function ID
30673 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
30674 * * 0xFFFD - Reserved for user-space HWRM interface
30677 uint16_t target_id;
30679 * A physical address pointer pointing to a host buffer that the
30680 * command's response data will be written. This can be either a host
30681 * physical address (HPA) or a guest physical address (GPA) and must
30682 * point to a physically contiguous block of memory.
30684 uint64_t resp_addr;
30685 /* The destination function id, to whom the traffic is redirected. */
30688 uint8_t tunnel_type;
30690 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_ALLOC_INPUT_TUNNEL_TYPE_NONTUNNEL \
30692 /* Virtual eXtensible Local Area Network (VXLAN) */
30693 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_ALLOC_INPUT_TUNNEL_TYPE_VXLAN \
30695 /* Network Virtualization Generic Routing Encapsulation (NVGRE) */
30696 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_ALLOC_INPUT_TUNNEL_TYPE_NVGRE \
30698 /* Generic Routing Encapsulation (GRE) inside Ethernet payload */
30699 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_ALLOC_INPUT_TUNNEL_TYPE_L2GRE \
30702 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_ALLOC_INPUT_TUNNEL_TYPE_IPIP \
30704 /* Generic Network Virtualization Encapsulation (Geneve) */
30705 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_ALLOC_INPUT_TUNNEL_TYPE_GENEVE \
30707 /* Multi-Protocol Label Switching (MPLS) */
30708 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_ALLOC_INPUT_TUNNEL_TYPE_MPLS \
30710 /* Stateless Transport Tunnel (STT) */
30711 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_ALLOC_INPUT_TUNNEL_TYPE_STT \
30713 /* Generic Routing Encapsulation (GRE) inside IP datagram payload */
30714 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_ALLOC_INPUT_TUNNEL_TYPE_IPGRE \
30716 /* IPV4 over virtual eXtensible Local Area Network (IPV4oVXLAN) */
30717 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_ALLOC_INPUT_TUNNEL_TYPE_VXLAN_V4 \
30719 /* Enhance Generic Routing Encapsulation (GRE version 1) inside IP datagram payload */
30720 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_ALLOC_INPUT_TUNNEL_TYPE_IPGRE_V1 \
30722 /* Use fixed layer 2 ether type of 0xFFFF */
30723 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_ALLOC_INPUT_TUNNEL_TYPE_L2_ETYPE \
30725 /* IPV6 over virtual eXtensible Local Area Network with GPE header (IPV6oVXLANGPE) */
30726 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_ALLOC_INPUT_TUNNEL_TYPE_VXLAN_GPE_V6 \
30728 /* Any tunneled traffic */
30729 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_ALLOC_INPUT_TUNNEL_TYPE_ANYTUNNEL \
30731 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_ALLOC_INPUT_TUNNEL_TYPE_LAST \
30732 HWRM_CFA_REDIRECT_TUNNEL_TYPE_ALLOC_INPUT_TUNNEL_TYPE_ANYTUNNEL
30733 /* Tunnel alloc flags. */
30735 /* Setting of this flag indicates modify existing redirect tunnel to new destination function ID. */
30736 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_ALLOC_INPUT_FLAGS_MODIFY_DST \
30738 uint8_t unused_0[4];
30741 /* hwrm_cfa_redirect_tunnel_type_alloc_output (size:128b/16B) */
30742 struct hwrm_cfa_redirect_tunnel_type_alloc_output {
30743 /* The specific error status for the command. */
30744 uint16_t error_code;
30745 /* The HWRM command request type. */
30747 /* The sequence ID from the original command. */
30749 /* The length of the response data in number of bytes. */
30751 uint8_t unused_0[7];
30753 * This field is used in Output records to indicate that the output
30754 * is completely written to RAM. This field should be read as '1'
30755 * to indicate that the output has been completely written.
30756 * When writing a command completion or response to an internal processor,
30757 * the order of writes has to be such that this field is written last.
30762 /**************************************
30763 * hwrm_cfa_redirect_tunnel_type_free *
30764 **************************************/
30767 /* hwrm_cfa_redirect_tunnel_type_free_input (size:192b/24B) */
30768 struct hwrm_cfa_redirect_tunnel_type_free_input {
30769 /* The HWRM command request type. */
30772 * The completion ring to send the completion event on. This should
30773 * be the NQ ID returned from the `nq_alloc` HWRM command.
30775 uint16_t cmpl_ring;
30777 * The sequence ID is used by the driver for tracking multiple
30778 * commands. This ID is treated as opaque data by the firmware and
30779 * the value is returned in the `hwrm_resp_hdr` upon completion.
30783 * The target ID of the command:
30784 * * 0x0-0xFFF8 - The function ID
30785 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
30786 * * 0xFFFD - Reserved for user-space HWRM interface
30789 uint16_t target_id;
30791 * A physical address pointer pointing to a host buffer that the
30792 * command's response data will be written. This can be either a host
30793 * physical address (HPA) or a guest physical address (GPA) and must
30794 * point to a physically contiguous block of memory.
30796 uint64_t resp_addr;
30797 /* The destination function id, to whom the traffic is redirected. */
30800 uint8_t tunnel_type;
30802 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_FREE_INPUT_TUNNEL_TYPE_NONTUNNEL \
30804 /* Virtual eXtensible Local Area Network (VXLAN) */
30805 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_FREE_INPUT_TUNNEL_TYPE_VXLAN \
30807 /* Network Virtualization Generic Routing Encapsulation (NVGRE) */
30808 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_FREE_INPUT_TUNNEL_TYPE_NVGRE \
30810 /* Generic Routing Encapsulation (GRE) inside Ethernet payload */
30811 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_FREE_INPUT_TUNNEL_TYPE_L2GRE \
30814 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_FREE_INPUT_TUNNEL_TYPE_IPIP \
30816 /* Generic Network Virtualization Encapsulation (Geneve) */
30817 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_FREE_INPUT_TUNNEL_TYPE_GENEVE \
30819 /* Multi-Protocol Label Switching (MPLS) */
30820 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_FREE_INPUT_TUNNEL_TYPE_MPLS \
30822 /* Stateless Transport Tunnel (STT) */
30823 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_FREE_INPUT_TUNNEL_TYPE_STT \
30825 /* Generic Routing Encapsulation (GRE) inside IP datagram payload */
30826 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_FREE_INPUT_TUNNEL_TYPE_IPGRE \
30828 /* IPV4 over virtual eXtensible Local Area Network (IPV4oVXLAN) */
30829 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_FREE_INPUT_TUNNEL_TYPE_VXLAN_V4 \
30831 /* Enhance Generic Routing Encapsulation (GRE version 1) inside IP datagram payload */
30832 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_FREE_INPUT_TUNNEL_TYPE_IPGRE_V1 \
30834 /* Use fixed layer 2 ether type of 0xFFFF */
30835 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_FREE_INPUT_TUNNEL_TYPE_L2_ETYPE \
30837 /* IPV6 over virtual eXtensible Local Area Network with GPE header (IPV6oVXLANGPE) */
30838 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_FREE_INPUT_TUNNEL_TYPE_VXLAN_GPE_V6 \
30840 /* Any tunneled traffic */
30841 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_FREE_INPUT_TUNNEL_TYPE_ANYTUNNEL \
30843 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_FREE_INPUT_TUNNEL_TYPE_LAST \
30844 HWRM_CFA_REDIRECT_TUNNEL_TYPE_FREE_INPUT_TUNNEL_TYPE_ANYTUNNEL
30845 uint8_t unused_0[5];
30848 /* hwrm_cfa_redirect_tunnel_type_free_output (size:128b/16B) */
30849 struct hwrm_cfa_redirect_tunnel_type_free_output {
30850 /* The specific error status for the command. */
30851 uint16_t error_code;
30852 /* The HWRM command request type. */
30854 /* The sequence ID from the original command. */
30856 /* The length of the response data in number of bytes. */
30858 uint8_t unused_0[7];
30860 * This field is used in Output records to indicate that the output
30861 * is completely written to RAM. This field should be read as '1'
30862 * to indicate that the output has been completely written.
30863 * When writing a command completion or response to an internal processor,
30864 * the order of writes has to be such that this field is written last.
30869 /**************************************
30870 * hwrm_cfa_redirect_tunnel_type_info *
30871 **************************************/
30874 /* hwrm_cfa_redirect_tunnel_type_info_input (size:192b/24B) */
30875 struct hwrm_cfa_redirect_tunnel_type_info_input {
30876 /* The HWRM command request type. */
30879 * The completion ring to send the completion event on. This should
30880 * be the NQ ID returned from the `nq_alloc` HWRM command.
30882 uint16_t cmpl_ring;
30884 * The sequence ID is used by the driver for tracking multiple
30885 * commands. This ID is treated as opaque data by the firmware and
30886 * the value is returned in the `hwrm_resp_hdr` upon completion.
30890 * The target ID of the command:
30891 * * 0x0-0xFFF8 - The function ID
30892 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
30893 * * 0xFFFD - Reserved for user-space HWRM interface
30896 uint16_t target_id;
30898 * A physical address pointer pointing to a host buffer that the
30899 * command's response data will be written. This can be either a host
30900 * physical address (HPA) or a guest physical address (GPA) and must
30901 * point to a physically contiguous block of memory.
30903 uint64_t resp_addr;
30904 /* The source function id. */
30907 uint8_t tunnel_type;
30909 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_INFO_INPUT_TUNNEL_TYPE_NONTUNNEL \
30911 /* Virtual eXtensible Local Area Network (VXLAN) */
30912 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_INFO_INPUT_TUNNEL_TYPE_VXLAN \
30914 /* Network Virtualization Generic Routing Encapsulation (NVGRE) */
30915 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_INFO_INPUT_TUNNEL_TYPE_NVGRE \
30917 /* Generic Routing Encapsulation (GRE) inside Ethernet payload */
30918 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_INFO_INPUT_TUNNEL_TYPE_L2GRE \
30921 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_INFO_INPUT_TUNNEL_TYPE_IPIP \
30923 /* Generic Network Virtualization Encapsulation (Geneve) */
30924 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_INFO_INPUT_TUNNEL_TYPE_GENEVE \
30926 /* Multi-Protocol Label Switching (MPLS) */
30927 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_INFO_INPUT_TUNNEL_TYPE_MPLS \
30929 /* Stateless Transport Tunnel (STT) */
30930 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_INFO_INPUT_TUNNEL_TYPE_STT \
30932 /* Generic Routing Encapsulation (GRE) inside IP datagram payload */
30933 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_INFO_INPUT_TUNNEL_TYPE_IPGRE \
30935 /* IPV4 over virtual eXtensible Local Area Network (IPV4oVXLAN) */
30936 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_INFO_INPUT_TUNNEL_TYPE_VXLAN_V4 \
30938 /* Enhance Generic Routing Encapsulation (GRE version 1) inside IP datagram payload */
30939 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_INFO_INPUT_TUNNEL_TYPE_IPGRE_V1 \
30941 /* Use fixed layer 2 ether type of 0xFFFF */
30942 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_INFO_INPUT_TUNNEL_TYPE_L2_ETYPE \
30944 /* IPV6 over virtual eXtensible Local Area Network with GPE header (IPV6oVXLANGPE) */
30945 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_INFO_INPUT_TUNNEL_TYPE_VXLAN_GPE_V6 \
30947 /* Any tunneled traffic */
30948 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_INFO_INPUT_TUNNEL_TYPE_ANYTUNNEL \
30950 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_INFO_INPUT_TUNNEL_TYPE_LAST \
30951 HWRM_CFA_REDIRECT_TUNNEL_TYPE_INFO_INPUT_TUNNEL_TYPE_ANYTUNNEL
30952 uint8_t unused_0[5];
30955 /* hwrm_cfa_redirect_tunnel_type_info_output (size:128b/16B) */
30956 struct hwrm_cfa_redirect_tunnel_type_info_output {
30957 /* The specific error status for the command. */
30958 uint16_t error_code;
30959 /* The HWRM command request type. */
30961 /* The sequence ID from the original command. */
30963 /* The length of the response data in number of bytes. */
30965 /* The destination function id, to whom the traffic is redirected. */
30967 uint8_t unused_0[5];
30969 * This field is used in Output records to indicate that the output
30970 * is completely written to RAM. This field should be read as '1'
30971 * to indicate that the output has been completely written.
30972 * When writing a command completion or response to an internal processor,
30973 * the order of writes has to be such that this field is written last.
30978 /* hwrm_vxlan_ipv4_hdr (size:128b/16B) */
30979 struct hwrm_vxlan_ipv4_hdr {
30980 /* IPv4 version and header length. */
30982 /* IPv4 header length */
30983 #define HWRM_VXLAN_IPV4_HDR_VER_HLEN_HEADER_LENGTH_MASK UINT32_C(0xf)
30984 #define HWRM_VXLAN_IPV4_HDR_VER_HLEN_HEADER_LENGTH_SFT 0
30986 #define HWRM_VXLAN_IPV4_HDR_VER_HLEN_VERSION_MASK UINT32_C(0xf0)
30987 #define HWRM_VXLAN_IPV4_HDR_VER_HLEN_VERSION_SFT 4
30988 /* IPv4 type of service. */
30990 /* IPv4 identification. */
30992 /* IPv4 flags and offset. */
30993 uint16_t flags_frag_offset;
30996 /* IPv4 protocol. */
30998 /* IPv4 source address. */
30999 uint32_t src_ip_addr;
31000 /* IPv4 destination address. */
31001 uint32_t dest_ip_addr;
31004 /* hwrm_vxlan_ipv6_hdr (size:320b/40B) */
31005 struct hwrm_vxlan_ipv6_hdr {
31006 /* IPv6 version, traffic class and flow label. */
31007 uint32_t ver_tc_flow_label;
31008 /* IPv6 version shift */
31009 #define HWRM_VXLAN_IPV6_HDR_VER_TC_FLOW_LABEL_VER_SFT \
31011 /* IPv6 version mask */
31012 #define HWRM_VXLAN_IPV6_HDR_VER_TC_FLOW_LABEL_VER_MASK \
31013 UINT32_C(0xf0000000)
31014 /* IPv6 TC shift */
31015 #define HWRM_VXLAN_IPV6_HDR_VER_TC_FLOW_LABEL_TC_SFT \
31018 #define HWRM_VXLAN_IPV6_HDR_VER_TC_FLOW_LABEL_TC_MASK \
31019 UINT32_C(0xff00000)
31020 /* IPv6 flow label shift */
31021 #define HWRM_VXLAN_IPV6_HDR_VER_TC_FLOW_LABEL_FLOW_LABEL_SFT \
31023 /* IPv6 flow label mask */
31024 #define HWRM_VXLAN_IPV6_HDR_VER_TC_FLOW_LABEL_FLOW_LABEL_MASK \
31026 #define HWRM_VXLAN_IPV6_HDR_VER_TC_FLOW_LABEL_LAST \
31027 HWRM_VXLAN_IPV6_HDR_VER_TC_FLOW_LABEL_FLOW_LABEL_MASK
31028 /* IPv6 payload length. */
31029 uint16_t payload_len;
31030 /* IPv6 next header. */
31034 /* IPv6 source address. */
31035 uint32_t src_ip_addr[4];
31036 /* IPv6 destination address. */
31037 uint32_t dest_ip_addr[4];
31040 /* hwrm_cfa_encap_data_vxlan (size:640b/80B) */
31041 struct hwrm_cfa_encap_data_vxlan {
31042 /* Source MAC address. */
31043 uint8_t src_mac_addr[6];
31046 /* Destination MAC address. */
31047 uint8_t dst_mac_addr[6];
31048 /* Number of VLAN tags. */
31049 uint8_t num_vlan_tags;
31052 /* Outer VLAN TPID. */
31053 uint16_t ovlan_tpid;
31054 /* Outer VLAN TCI. */
31055 uint16_t ovlan_tci;
31056 /* Inner VLAN TPID. */
31057 uint16_t ivlan_tpid;
31058 /* Inner VLAN TCI. */
31059 uint16_t ivlan_tci;
31060 /* L3 header fields. */
31062 /* IP version mask. */
31063 #define HWRM_CFA_ENCAP_DATA_VXLAN_L3_VER_MASK UINT32_C(0xf)
31064 /* IP version 4. */
31065 #define HWRM_CFA_ENCAP_DATA_VXLAN_L3_VER_IPV4 UINT32_C(0x4)
31066 /* IP version 6. */
31067 #define HWRM_CFA_ENCAP_DATA_VXLAN_L3_VER_IPV6 UINT32_C(0x6)
31068 #define HWRM_CFA_ENCAP_DATA_VXLAN_L3_LAST \
31069 HWRM_CFA_ENCAP_DATA_VXLAN_L3_VER_IPV6
31070 /* UDP source port. */
31072 /* UDP destination port. */
31074 /* VXLAN Network Identifier. */
31076 /* 3 bytes VXLAN header reserve fields from 1st dword of the VXLAN header. */
31077 uint8_t hdr_rsvd0[3];
31078 /* 1 byte VXLAN header reserve field from 2nd dword of the VXLAN header. */
31080 /* VXLAN header flags field. */
31085 /*******************************
31086 * hwrm_cfa_encap_record_alloc *
31087 *******************************/
31090 /* hwrm_cfa_encap_record_alloc_input (size:832b/104B) */
31091 struct hwrm_cfa_encap_record_alloc_input {
31092 /* The HWRM command request type. */
31095 * The completion ring to send the completion event on. This should
31096 * be the NQ ID returned from the `nq_alloc` HWRM command.
31098 uint16_t cmpl_ring;
31100 * The sequence ID is used by the driver for tracking multiple
31101 * commands. This ID is treated as opaque data by the firmware and
31102 * the value is returned in the `hwrm_resp_hdr` upon completion.
31106 * The target ID of the command:
31107 * * 0x0-0xFFF8 - The function ID
31108 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
31109 * * 0xFFFD - Reserved for user-space HWRM interface
31112 uint16_t target_id;
31114 * A physical address pointer pointing to a host buffer that the
31115 * command's response data will be written. This can be either a host
31116 * physical address (HPA) or a guest physical address (GPA) and must
31117 * point to a physically contiguous block of memory.
31119 uint64_t resp_addr;
31121 /* Setting of this flag indicates the applicability to the loopback path. */
31122 #define HWRM_CFA_ENCAP_RECORD_ALLOC_INPUT_FLAGS_LOOPBACK \
31125 * Setting of this flag indicates this encap record is external encap record.
31126 * Resetting of this flag indicates this flag is internal encap record and
31127 * this is the default setting.
31129 #define HWRM_CFA_ENCAP_RECORD_ALLOC_INPUT_FLAGS_EXTERNAL \
31131 /* Encapsulation Type. */
31132 uint8_t encap_type;
31133 /* Virtual eXtensible Local Area Network (VXLAN) */
31134 #define HWRM_CFA_ENCAP_RECORD_ALLOC_INPUT_ENCAP_TYPE_VXLAN \
31136 /* Network Virtualization Generic Routing Encapsulation (NVGRE) */
31137 #define HWRM_CFA_ENCAP_RECORD_ALLOC_INPUT_ENCAP_TYPE_NVGRE \
31139 /* Generic Routing Encapsulation (GRE) after inside Ethernet payload */
31140 #define HWRM_CFA_ENCAP_RECORD_ALLOC_INPUT_ENCAP_TYPE_L2GRE \
31143 #define HWRM_CFA_ENCAP_RECORD_ALLOC_INPUT_ENCAP_TYPE_IPIP \
31145 /* Generic Network Virtualization Encapsulation (Geneve) */
31146 #define HWRM_CFA_ENCAP_RECORD_ALLOC_INPUT_ENCAP_TYPE_GENEVE \
31148 /* Multi-Protocol Label Switching (MPLS) */
31149 #define HWRM_CFA_ENCAP_RECORD_ALLOC_INPUT_ENCAP_TYPE_MPLS \
31152 #define HWRM_CFA_ENCAP_RECORD_ALLOC_INPUT_ENCAP_TYPE_VLAN \
31154 /* Generic Routing Encapsulation (GRE) inside IP datagram payload */
31155 #define HWRM_CFA_ENCAP_RECORD_ALLOC_INPUT_ENCAP_TYPE_IPGRE \
31157 /* IPV4 over virtual eXtensible Local Area Network (IPV4oVXLAN) */
31158 #define HWRM_CFA_ENCAP_RECORD_ALLOC_INPUT_ENCAP_TYPE_VXLAN_V4 \
31160 /* Enhance Generic Routing Encapsulation (GRE version 1) inside IP datagram payload */
31161 #define HWRM_CFA_ENCAP_RECORD_ALLOC_INPUT_ENCAP_TYPE_IPGRE_V1 \
31163 /* Use fixed layer 2 ether type of 0xFFFF */
31164 #define HWRM_CFA_ENCAP_RECORD_ALLOC_INPUT_ENCAP_TYPE_L2_ETYPE \
31166 /* IPV6 over virtual eXtensible Local Area Network with GPE header (IPV6oVXLANGPE) */
31167 #define HWRM_CFA_ENCAP_RECORD_ALLOC_INPUT_ENCAP_TYPE_VXLAN_GPE_V6 \
31169 #define HWRM_CFA_ENCAP_RECORD_ALLOC_INPUT_ENCAP_TYPE_LAST \
31170 HWRM_CFA_ENCAP_RECORD_ALLOC_INPUT_ENCAP_TYPE_VXLAN_GPE_V6
31171 uint8_t unused_0[3];
31172 /* This value is encap data used for the given encap type. */
31173 uint32_t encap_data[20];
31176 /* hwrm_cfa_encap_record_alloc_output (size:128b/16B) */
31177 struct hwrm_cfa_encap_record_alloc_output {
31178 /* The specific error status for the command. */
31179 uint16_t error_code;
31180 /* The HWRM command request type. */
31182 /* The sequence ID from the original command. */
31184 /* The length of the response data in number of bytes. */
31186 /* This value is an opaque id into CFA data structures. */
31187 uint32_t encap_record_id;
31188 uint8_t unused_0[3];
31190 * This field is used in Output records to indicate that the output
31191 * is completely written to RAM. This field should be read as '1'
31192 * to indicate that the output has been completely written.
31193 * When writing a command completion or response to an internal processor,
31194 * the order of writes has to be such that this field is written last.
31199 /******************************
31200 * hwrm_cfa_encap_record_free *
31201 ******************************/
31204 /* hwrm_cfa_encap_record_free_input (size:192b/24B) */
31205 struct hwrm_cfa_encap_record_free_input {
31206 /* The HWRM command request type. */
31209 * The completion ring to send the completion event on. This should
31210 * be the NQ ID returned from the `nq_alloc` HWRM command.
31212 uint16_t cmpl_ring;
31214 * The sequence ID is used by the driver for tracking multiple
31215 * commands. This ID is treated as opaque data by the firmware and
31216 * the value is returned in the `hwrm_resp_hdr` upon completion.
31220 * The target ID of the command:
31221 * * 0x0-0xFFF8 - The function ID
31222 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
31223 * * 0xFFFD - Reserved for user-space HWRM interface
31226 uint16_t target_id;
31228 * A physical address pointer pointing to a host buffer that the
31229 * command's response data will be written. This can be either a host
31230 * physical address (HPA) or a guest physical address (GPA) and must
31231 * point to a physically contiguous block of memory.
31233 uint64_t resp_addr;
31234 /* This value is an opaque id into CFA data structures. */
31235 uint32_t encap_record_id;
31236 uint8_t unused_0[4];
31239 /* hwrm_cfa_encap_record_free_output (size:128b/16B) */
31240 struct hwrm_cfa_encap_record_free_output {
31241 /* The specific error status for the command. */
31242 uint16_t error_code;
31243 /* The HWRM command request type. */
31245 /* The sequence ID from the original command. */
31247 /* The length of the response data in number of bytes. */
31249 uint8_t unused_0[7];
31251 * This field is used in Output records to indicate that the output
31252 * is completely written to RAM. This field should be read as '1'
31253 * to indicate that the output has been completely written.
31254 * When writing a command completion or response to an internal processor,
31255 * the order of writes has to be such that this field is written last.
31260 /********************************
31261 * hwrm_cfa_ntuple_filter_alloc *
31262 ********************************/
31265 /* hwrm_cfa_ntuple_filter_alloc_input (size:1024b/128B) */
31266 struct hwrm_cfa_ntuple_filter_alloc_input {
31267 /* The HWRM command request type. */
31270 * The completion ring to send the completion event on. This should
31271 * be the NQ ID returned from the `nq_alloc` HWRM command.
31273 uint16_t cmpl_ring;
31275 * The sequence ID is used by the driver for tracking multiple
31276 * commands. This ID is treated as opaque data by the firmware and
31277 * the value is returned in the `hwrm_resp_hdr` upon completion.
31281 * The target ID of the command:
31282 * * 0x0-0xFFF8 - The function ID
31283 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
31284 * * 0xFFFD - Reserved for user-space HWRM interface
31287 uint16_t target_id;
31289 * A physical address pointer pointing to a host buffer that the
31290 * command's response data will be written. This can be either a host
31291 * physical address (HPA) or a guest physical address (GPA) and must
31292 * point to a physically contiguous block of memory.
31294 uint64_t resp_addr;
31296 /* Setting of this flag indicates the applicability to the loopback path. */
31297 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_FLAGS_LOOPBACK \
31300 * Setting of this flag indicates drop action. If this flag is not set,
31301 * then it should be considered accept action.
31303 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_FLAGS_DROP \
31306 * Setting of this flag indicates that a meter is expected to be attached
31307 * to this flow. This hint can be used when choosing the action record
31308 * format required for the flow.
31310 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_FLAGS_METER \
31313 * Setting of this flag indicates that the dst_id field contains function ID.
31314 * If this is not set it indicates dest_id is VNIC or VPORT.
31316 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_FLAGS_DEST_FID \
31319 * Setting of this flag indicates match on arp reply when ethertype is 0x0806.
31320 * If this is not set it indicates no specific arp opcode matching.
31322 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_FLAGS_ARP_REPLY \
31325 * Setting of this flag indicates that the dst_id field contains RFS ring
31326 * table index. If this is not set it indicates dst_id is VNIC or VPORT
31327 * or function ID. Note dest_fid and dest_rfs_ring_idx can’t be set at
31330 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_FLAGS_DEST_RFS_RING_IDX \
31334 * This bit must be '1' for the l2_filter_id field to be
31337 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_L2_FILTER_ID \
31340 * This bit must be '1' for the ethertype field to be
31343 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_ETHERTYPE \
31346 * This bit must be '1' for the tunnel_type field to be
31349 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_TUNNEL_TYPE \
31352 * This bit must be '1' for the src_macaddr field to be
31355 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_SRC_MACADDR \
31358 * This bit must be '1' for the ipaddr_type field to be
31361 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_IPADDR_TYPE \
31364 * This bit must be '1' for the src_ipaddr field to be
31367 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_SRC_IPADDR \
31370 * This bit must be '1' for the src_ipaddr_mask field to be
31373 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_SRC_IPADDR_MASK \
31376 * This bit must be '1' for the dst_ipaddr field to be
31379 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_IPADDR \
31382 * This bit must be '1' for the dst_ipaddr_mask field to be
31385 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_IPADDR_MASK \
31388 * This bit must be '1' for the ip_protocol field to be
31391 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_IP_PROTOCOL \
31394 * This bit must be '1' for the src_port field to be
31397 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_SRC_PORT \
31400 * This bit must be '1' for the src_port_mask field to be
31403 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_SRC_PORT_MASK \
31406 * This bit must be '1' for the dst_port field to be
31409 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_PORT \
31412 * This bit must be '1' for the dst_port_mask field to be
31415 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_PORT_MASK \
31418 * This bit must be '1' for the pri_hint field to be
31421 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_PRI_HINT \
31424 * This bit must be '1' for the ntuple_filter_id field to be
31427 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_NTUPLE_FILTER_ID \
31430 * This bit must be '1' for the dst_id field to be
31433 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_ID \
31436 * This bit must be '1' for the mirror_vnic_id field to be
31439 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_MIRROR_VNIC_ID \
31442 * This bit must be '1' for the dst_macaddr field to be
31445 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_MACADDR \
31447 /* This flag is deprecated. */
31448 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_RFS_RING_TBL_IDX \
31451 * This value identifies a set of CFA data structures used for an L2
31454 uint64_t l2_filter_id;
31456 * This value indicates the source MAC address in
31457 * the Ethernet header.
31459 uint8_t src_macaddr[6];
31460 /* This value indicates the ethertype in the Ethernet header. */
31461 uint16_t ethertype;
31463 * This value indicates the type of IP address.
31466 * All others are invalid.
31468 uint8_t ip_addr_type;
31470 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_IP_ADDR_TYPE_UNKNOWN \
31473 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_IP_ADDR_TYPE_IPV4 \
31476 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_IP_ADDR_TYPE_IPV6 \
31478 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_IP_ADDR_TYPE_LAST \
31479 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_IP_ADDR_TYPE_IPV6
31481 * The value of protocol filed in IP header.
31482 * Applies to UDP and TCP traffic.
31486 uint8_t ip_protocol;
31488 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_IP_PROTOCOL_UNKNOWN \
31491 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_IP_PROTOCOL_TCP \
31494 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_IP_PROTOCOL_UDP \
31496 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_IP_PROTOCOL_LAST \
31497 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_IP_PROTOCOL_UDP
31499 * If set, this value shall represent the
31500 * Logical VNIC ID of the destination VNIC for the RX
31501 * path and network port id of the destination port for
31506 * Logical VNIC ID of the VNIC where traffic is
31509 uint16_t mirror_vnic_id;
31511 * This value indicates the tunnel type for this filter.
31512 * If this field is not specified, then the filter shall
31513 * apply to both non-tunneled and tunneled packets.
31514 * If this field conflicts with the tunnel_type specified
31515 * in the l2_filter_id, then the HWRM shall return an
31516 * error for this command.
31518 uint8_t tunnel_type;
31520 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_TUNNEL_TYPE_NONTUNNEL \
31522 /* Virtual eXtensible Local Area Network (VXLAN) */
31523 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_TUNNEL_TYPE_VXLAN \
31525 /* Network Virtualization Generic Routing Encapsulation (NVGRE) */
31526 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_TUNNEL_TYPE_NVGRE \
31528 /* Generic Routing Encapsulation (GRE) inside Ethernet payload */
31529 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_TUNNEL_TYPE_L2GRE \
31532 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_TUNNEL_TYPE_IPIP \
31534 /* Generic Network Virtualization Encapsulation (Geneve) */
31535 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_TUNNEL_TYPE_GENEVE \
31537 /* Multi-Protocol Label Switching (MPLS) */
31538 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_TUNNEL_TYPE_MPLS \
31540 /* Stateless Transport Tunnel (STT) */
31541 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_TUNNEL_TYPE_STT \
31543 /* Generic Routing Encapsulation (GRE) inside IP datagram payload */
31544 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_TUNNEL_TYPE_IPGRE \
31546 /* IPV4 over virtual eXtensible Local Area Network (IPV4oVXLAN) */
31547 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_TUNNEL_TYPE_VXLAN_V4 \
31549 /* Enhance Generic Routing Encapsulation (GRE version 1) inside IP datagram payload */
31550 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_TUNNEL_TYPE_IPGRE_V1 \
31552 /* Use fixed layer 2 ether type of 0xFFFF */
31553 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_TUNNEL_TYPE_L2_ETYPE \
31555 /* IPV6 over virtual eXtensible Local Area Network with GPE header (IPV6oVXLANGPE) */
31556 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_TUNNEL_TYPE_VXLAN_GPE_V6 \
31558 /* Any tunneled traffic */
31559 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_TUNNEL_TYPE_ANYTUNNEL \
31561 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_TUNNEL_TYPE_LAST \
31562 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_TUNNEL_TYPE_ANYTUNNEL
31564 * This hint is provided to help in placing
31565 * the filter in the filter table.
31568 /* No preference */
31569 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_PRI_HINT_NO_PREFER \
31571 /* Above the given filter */
31572 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_PRI_HINT_ABOVE \
31574 /* Below the given filter */
31575 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_PRI_HINT_BELOW \
31577 /* As high as possible */
31578 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_PRI_HINT_HIGHEST \
31580 /* As low as possible */
31581 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_PRI_HINT_LOWEST \
31583 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_PRI_HINT_LAST \
31584 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_PRI_HINT_LOWEST
31586 * The value of source IP address to be used in filtering.
31587 * For IPv4, first four bytes represent the IP address.
31589 uint32_t src_ipaddr[4];
31591 * The value of source IP address mask to be used in
31593 * For IPv4, first four bytes represent the IP address mask.
31595 uint32_t src_ipaddr_mask[4];
31597 * The value of destination IP address to be used in filtering.
31598 * For IPv4, first four bytes represent the IP address.
31600 uint32_t dst_ipaddr[4];
31602 * The value of destination IP address mask to be used in
31604 * For IPv4, first four bytes represent the IP address mask.
31606 uint32_t dst_ipaddr_mask[4];
31608 * The value of source port to be used in filtering.
31609 * Applies to UDP and TCP traffic.
31613 * The value of source port mask to be used in filtering.
31614 * Applies to UDP and TCP traffic.
31616 uint16_t src_port_mask;
31618 * The value of destination port to be used in filtering.
31619 * Applies to UDP and TCP traffic.
31623 * The value of destination port mask to be used in
31625 * Applies to UDP and TCP traffic.
31627 uint16_t dst_port_mask;
31629 * This is the ID of the filter that goes along with
31632 uint64_t ntuple_filter_id_hint;
31635 /* hwrm_cfa_ntuple_filter_alloc_output (size:192b/24B) */
31636 struct hwrm_cfa_ntuple_filter_alloc_output {
31637 /* The specific error status for the command. */
31638 uint16_t error_code;
31639 /* The HWRM command request type. */
31641 /* The sequence ID from the original command. */
31643 /* The length of the response data in number of bytes. */
31645 /* This value is an opaque id into CFA data structures. */
31646 uint64_t ntuple_filter_id;
31648 * The flow id value in bit 0-29 is the actual ID of the flow
31649 * associated with this filter and it shall be used to match
31650 * and associate the flow identifier returned in completion
31651 * records. A value of 0xFFFFFFFF in the 32-bit flow_id field
31652 * shall indicate no valid flow id.
31655 /* Indicate the flow id value. */
31656 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_OUTPUT_FLOW_ID_VALUE_MASK \
31657 UINT32_C(0x3fffffff)
31658 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_OUTPUT_FLOW_ID_VALUE_SFT 0
31659 /* Indicate type of the flow. */
31660 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_OUTPUT_FLOW_ID_TYPE \
31661 UINT32_C(0x40000000)
31663 * If this bit set to 0, then it indicates that the flow is
31666 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_OUTPUT_FLOW_ID_TYPE_INT \
31667 (UINT32_C(0x0) << 30)
31669 * If this bit is set to 1, then it indicates that the flow is
31672 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_OUTPUT_FLOW_ID_TYPE_EXT \
31673 (UINT32_C(0x1) << 30)
31674 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_OUTPUT_FLOW_ID_TYPE_LAST \
31675 HWRM_CFA_NTUPLE_FILTER_ALLOC_OUTPUT_FLOW_ID_TYPE_EXT
31676 /* Indicate the flow direction. */
31677 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_OUTPUT_FLOW_ID_DIR \
31678 UINT32_C(0x80000000)
31679 /* If this bit set to 0, then it indicates rx flow. */
31680 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_OUTPUT_FLOW_ID_DIR_RX \
31681 (UINT32_C(0x0) << 31)
31682 /* If this bit is set to 1, then it indicates that tx flow. */
31683 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_OUTPUT_FLOW_ID_DIR_TX \
31684 (UINT32_C(0x1) << 31)
31685 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_OUTPUT_FLOW_ID_DIR_LAST \
31686 HWRM_CFA_NTUPLE_FILTER_ALLOC_OUTPUT_FLOW_ID_DIR_TX
31687 uint8_t unused_0[3];
31689 * This field is used in Output records to indicate that the output
31690 * is completely written to RAM. This field should be read as '1'
31691 * to indicate that the output has been completely written.
31692 * When writing a command completion or response to an internal processor,
31693 * the order of writes has to be such that this field is written last.
31698 /* hwrm_cfa_ntuple_filter_alloc_cmd_err (size:64b/8B) */
31699 struct hwrm_cfa_ntuple_filter_alloc_cmd_err {
31701 * command specific error codes that goes to
31702 * the cmd_err field in Common HWRM Error Response.
31705 /* Unknown error */
31706 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_CMD_ERR_CODE_UNKNOWN \
31708 /* Unable to complete operation due to conflict with Rx Mask VLAN */
31709 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_CMD_ERR_CODE_RX_MASK_VLAN_CONFLICT_ERR \
31711 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_CMD_ERR_CODE_LAST \
31712 HWRM_CFA_NTUPLE_FILTER_ALLOC_CMD_ERR_CODE_RX_MASK_VLAN_CONFLICT_ERR
31713 uint8_t unused_0[7];
31716 /*******************************
31717 * hwrm_cfa_ntuple_filter_free *
31718 *******************************/
31721 /* hwrm_cfa_ntuple_filter_free_input (size:192b/24B) */
31722 struct hwrm_cfa_ntuple_filter_free_input {
31723 /* The HWRM command request type. */
31726 * The completion ring to send the completion event on. This should
31727 * be the NQ ID returned from the `nq_alloc` HWRM command.
31729 uint16_t cmpl_ring;
31731 * The sequence ID is used by the driver for tracking multiple
31732 * commands. This ID is treated as opaque data by the firmware and
31733 * the value is returned in the `hwrm_resp_hdr` upon completion.
31737 * The target ID of the command:
31738 * * 0x0-0xFFF8 - The function ID
31739 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
31740 * * 0xFFFD - Reserved for user-space HWRM interface
31743 uint16_t target_id;
31745 * A physical address pointer pointing to a host buffer that the
31746 * command's response data will be written. This can be either a host
31747 * physical address (HPA) or a guest physical address (GPA) and must
31748 * point to a physically contiguous block of memory.
31750 uint64_t resp_addr;
31751 /* This value is an opaque id into CFA data structures. */
31752 uint64_t ntuple_filter_id;
31755 /* hwrm_cfa_ntuple_filter_free_output (size:128b/16B) */
31756 struct hwrm_cfa_ntuple_filter_free_output {
31757 /* The specific error status for the command. */
31758 uint16_t error_code;
31759 /* The HWRM command request type. */
31761 /* The sequence ID from the original command. */
31763 /* The length of the response data in number of bytes. */
31765 uint8_t unused_0[7];
31767 * This field is used in Output records to indicate that the output
31768 * is completely written to RAM. This field should be read as '1'
31769 * to indicate that the output has been completely written.
31770 * When writing a command completion or response to an internal processor,
31771 * the order of writes has to be such that this field is written last.
31776 /******************************
31777 * hwrm_cfa_ntuple_filter_cfg *
31778 ******************************/
31781 /* hwrm_cfa_ntuple_filter_cfg_input (size:384b/48B) */
31782 struct hwrm_cfa_ntuple_filter_cfg_input {
31783 /* The HWRM command request type. */
31786 * The completion ring to send the completion event on. This should
31787 * be the NQ ID returned from the `nq_alloc` HWRM command.
31789 uint16_t cmpl_ring;
31791 * The sequence ID is used by the driver for tracking multiple
31792 * commands. This ID is treated as opaque data by the firmware and
31793 * the value is returned in the `hwrm_resp_hdr` upon completion.
31797 * The target ID of the command:
31798 * * 0x0-0xFFF8 - The function ID
31799 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
31800 * * 0xFFFD - Reserved for user-space HWRM interface
31803 uint16_t target_id;
31805 * A physical address pointer pointing to a host buffer that the
31806 * command's response data will be written. This can be either a host
31807 * physical address (HPA) or a guest physical address (GPA) and must
31808 * point to a physically contiguous block of memory.
31810 uint64_t resp_addr;
31813 * This bit must be '1' for the new_dst_id field to be
31816 #define HWRM_CFA_NTUPLE_FILTER_CFG_INPUT_ENABLES_NEW_DST_ID \
31819 * This bit must be '1' for the new_mirror_vnic_id field to be
31822 #define HWRM_CFA_NTUPLE_FILTER_CFG_INPUT_ENABLES_NEW_MIRROR_VNIC_ID \
31825 * This bit must be '1' for the new_meter_instance_id field to be
31828 #define HWRM_CFA_NTUPLE_FILTER_CFG_INPUT_ENABLES_NEW_METER_INSTANCE_ID \
31832 * Setting this bit to 1 indicates that dest_id field contains FID.
31833 * Setting this to 0 indicates that dest_id field contains VNIC or VPORT.
31835 #define HWRM_CFA_NTUPLE_FILTER_CFG_INPUT_FLAGS_DEST_FID \
31838 * Setting of this flag indicates that the new_dst_id field contains
31839 * RFS ring table index. If this is not set it indicates new_dst_id is
31840 * VNIC or VPORT or function ID. Note dest_fid and dest_rfs_ring_idx
31841 * can’t be set at the same time.
31843 #define HWRM_CFA_NTUPLE_FILTER_CFG_INPUT_FLAGS_DEST_RFS_RING_IDX \
31845 /* This value is an opaque id into CFA data structures. */
31846 uint64_t ntuple_filter_id;
31848 * If set, this value shall represent the new
31849 * Logical VNIC ID of the destination VNIC for the RX
31850 * path and new network port id of the destination port for
31853 uint32_t new_dst_id;
31855 * New Logical VNIC ID of the VNIC where traffic is
31858 uint32_t new_mirror_vnic_id;
31860 * New meter to attach to the flow. Specifying the
31861 * invalid instance ID is used to remove any existing
31862 * meter from the flow.
31864 uint16_t new_meter_instance_id;
31866 * A value of 0xfff is considered invalid and implies the
31867 * instance is not configured.
31869 #define HWRM_CFA_NTUPLE_FILTER_CFG_INPUT_NEW_METER_INSTANCE_ID_INVALID \
31871 #define HWRM_CFA_NTUPLE_FILTER_CFG_INPUT_NEW_METER_INSTANCE_ID_LAST \
31872 HWRM_CFA_NTUPLE_FILTER_CFG_INPUT_NEW_METER_INSTANCE_ID_INVALID
31873 uint8_t unused_1[6];
31876 /* hwrm_cfa_ntuple_filter_cfg_output (size:128b/16B) */
31877 struct hwrm_cfa_ntuple_filter_cfg_output {
31878 /* The specific error status for the command. */
31879 uint16_t error_code;
31880 /* The HWRM command request type. */
31882 /* The sequence ID from the original command. */
31884 /* The length of the response data in number of bytes. */
31886 uint8_t unused_0[7];
31888 * This field is used in Output records to indicate that the output
31889 * is completely written to RAM. This field should be read as '1'
31890 * to indicate that the output has been completely written.
31891 * When writing a command completion or response to an internal processor,
31892 * the order of writes has to be such that this field is written last.
31897 /**************************
31898 * hwrm_cfa_em_flow_alloc *
31899 **************************/
31902 /* hwrm_cfa_em_flow_alloc_input (size:896b/112B) */
31903 struct hwrm_cfa_em_flow_alloc_input {
31904 /* The HWRM command request type. */
31907 * The completion ring to send the completion event on. This should
31908 * be the NQ ID returned from the `nq_alloc` HWRM command.
31910 uint16_t cmpl_ring;
31912 * The sequence ID is used by the driver for tracking multiple
31913 * commands. This ID is treated as opaque data by the firmware and
31914 * the value is returned in the `hwrm_resp_hdr` upon completion.
31918 * The target ID of the command:
31919 * * 0x0-0xFFF8 - The function ID
31920 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
31921 * * 0xFFFD - Reserved for user-space HWRM interface
31924 uint16_t target_id;
31926 * A physical address pointer pointing to a host buffer that the
31927 * command's response data will be written. This can be either a host
31928 * physical address (HPA) or a guest physical address (GPA) and must
31929 * point to a physically contiguous block of memory.
31931 uint64_t resp_addr;
31934 * Enumeration denoting the RX, TX type of the resource.
31935 * This enumeration is used for resources that are similar for both
31936 * TX and RX paths of the chip.
31938 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_FLAGS_PATH UINT32_C(0x1)
31940 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_FLAGS_PATH_TX UINT32_C(0x0)
31942 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_FLAGS_PATH_RX UINT32_C(0x1)
31943 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_FLAGS_PATH_LAST \
31944 HWRM_CFA_EM_FLOW_ALLOC_INPUT_FLAGS_PATH_RX
31946 * Setting of this flag indicates enabling of a byte counter for a given
31949 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_FLAGS_BYTE_CTR UINT32_C(0x2)
31951 * Setting of this flag indicates enabling of a packet counter for a given
31954 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_FLAGS_PKT_CTR UINT32_C(0x4)
31955 /* Setting of this flag indicates de-capsulation action for the given flow. */
31956 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_FLAGS_DECAP UINT32_C(0x8)
31957 /* Setting of this flag indicates encapsulation action for the given flow. */
31958 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_FLAGS_ENCAP UINT32_C(0x10)
31960 * Setting of this flag indicates drop action. If this flag is not set,
31961 * then it should be considered accept action.
31963 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_FLAGS_DROP UINT32_C(0x20)
31965 * Setting of this flag indicates that a meter is expected to be attached
31966 * to this flow. This hint can be used when choosing the action record
31967 * format required for the flow.
31969 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_FLAGS_METER UINT32_C(0x40)
31972 * This bit must be '1' for the l2_filter_id field to be
31975 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_L2_FILTER_ID \
31978 * This bit must be '1' for the tunnel_type field to be
31981 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_TUNNEL_TYPE \
31984 * This bit must be '1' for the tunnel_id field to be
31987 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_TUNNEL_ID \
31990 * This bit must be '1' for the src_macaddr field to be
31993 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_SRC_MACADDR \
31996 * This bit must be '1' for the dst_macaddr field to be
31999 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_DST_MACADDR \
32002 * This bit must be '1' for the ovlan_vid field to be
32005 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_OVLAN_VID \
32008 * This bit must be '1' for the ivlan_vid field to be
32011 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_IVLAN_VID \
32014 * This bit must be '1' for the ethertype field to be
32017 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_ETHERTYPE \
32020 * This bit must be '1' for the src_ipaddr field to be
32023 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_SRC_IPADDR \
32026 * This bit must be '1' for the dst_ipaddr field to be
32029 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_DST_IPADDR \
32032 * This bit must be '1' for the ipaddr_type field to be
32035 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_IPADDR_TYPE \
32038 * This bit must be '1' for the ip_protocol field to be
32041 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_IP_PROTOCOL \
32044 * This bit must be '1' for the src_port field to be
32047 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_SRC_PORT \
32050 * This bit must be '1' for the dst_port field to be
32053 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_DST_PORT \
32056 * This bit must be '1' for the dst_id field to be
32059 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_DST_ID \
32062 * This bit must be '1' for the mirror_vnic_id field to be
32065 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_MIRROR_VNIC_ID \
32068 * This bit must be '1' for the encap_record_id field to be
32071 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_ENCAP_RECORD_ID \
32074 * This bit must be '1' for the meter_instance_id field to be
32077 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_METER_INSTANCE_ID \
32080 * This value identifies a set of CFA data structures used for an L2
32083 uint64_t l2_filter_id;
32085 uint8_t tunnel_type;
32087 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_TUNNEL_TYPE_NONTUNNEL \
32089 /* Virtual eXtensible Local Area Network (VXLAN) */
32090 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_TUNNEL_TYPE_VXLAN \
32092 /* Network Virtualization Generic Routing Encapsulation (NVGRE) */
32093 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_TUNNEL_TYPE_NVGRE \
32095 /* Generic Routing Encapsulation (GRE) inside Ethernet payload */
32096 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_TUNNEL_TYPE_L2GRE \
32099 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_TUNNEL_TYPE_IPIP \
32101 /* Generic Network Virtualization Encapsulation (Geneve) */
32102 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_TUNNEL_TYPE_GENEVE \
32104 /* Multi-Protocol Label Switching (MPLS) */
32105 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_TUNNEL_TYPE_MPLS \
32107 /* Stateless Transport Tunnel (STT) */
32108 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_TUNNEL_TYPE_STT \
32110 /* Generic Routing Encapsulation (GRE) inside IP datagram payload */
32111 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_TUNNEL_TYPE_IPGRE \
32113 /* IPV4 over virtual eXtensible Local Area Network (IPV4oVXLAN) */
32114 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_TUNNEL_TYPE_VXLAN_V4 \
32116 /* Enhance Generic Routing Encapsulation (GRE version 1) inside IP datagram payload */
32117 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_TUNNEL_TYPE_IPGRE_V1 \
32119 /* Use fixed layer 2 ether type of 0xFFFF */
32120 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_TUNNEL_TYPE_L2_ETYPE \
32122 /* IPV6 over virtual eXtensible Local Area Network with GPE header (IPV6oVXLANGPE) */
32123 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_TUNNEL_TYPE_VXLAN_GPE_V6 \
32125 /* Any tunneled traffic */
32126 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_TUNNEL_TYPE_ANYTUNNEL \
32128 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_TUNNEL_TYPE_LAST \
32129 HWRM_CFA_EM_FLOW_ALLOC_INPUT_TUNNEL_TYPE_ANYTUNNEL
32130 uint8_t unused_0[3];
32132 * Tunnel identifier.
32133 * Virtual Network Identifier (VNI). Only valid with
32134 * tunnel_types VXLAN, NVGRE, and Geneve.
32135 * Only lower 24-bits of VNI field are used
32136 * in setting up the filter.
32138 uint32_t tunnel_id;
32140 * This value indicates the source MAC address in
32141 * the Ethernet header.
32143 uint8_t src_macaddr[6];
32144 /* The meter instance to attach to the flow. */
32145 uint16_t meter_instance_id;
32147 * A value of 0xfff is considered invalid and implies the
32148 * instance is not configured.
32150 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_METER_INSTANCE_ID_INVALID \
32152 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_METER_INSTANCE_ID_LAST \
32153 HWRM_CFA_EM_FLOW_ALLOC_INPUT_METER_INSTANCE_ID_INVALID
32155 * This value indicates the destination MAC address in
32156 * the Ethernet header.
32158 uint8_t dst_macaddr[6];
32160 * This value indicates the VLAN ID of the outer VLAN tag
32161 * in the Ethernet header.
32163 uint16_t ovlan_vid;
32165 * This value indicates the VLAN ID of the inner VLAN tag
32166 * in the Ethernet header.
32168 uint16_t ivlan_vid;
32169 /* This value indicates the ethertype in the Ethernet header. */
32170 uint16_t ethertype;
32172 * This value indicates the type of IP address.
32175 * All others are invalid.
32177 uint8_t ip_addr_type;
32179 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_IP_ADDR_TYPE_UNKNOWN UINT32_C(0x0)
32181 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_IP_ADDR_TYPE_IPV4 UINT32_C(0x4)
32183 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_IP_ADDR_TYPE_IPV6 UINT32_C(0x6)
32184 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_IP_ADDR_TYPE_LAST \
32185 HWRM_CFA_EM_FLOW_ALLOC_INPUT_IP_ADDR_TYPE_IPV6
32187 * The value of protocol filed in IP header.
32188 * Applies to UDP and TCP traffic.
32192 uint8_t ip_protocol;
32194 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_IP_PROTOCOL_UNKNOWN UINT32_C(0x0)
32196 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_IP_PROTOCOL_TCP UINT32_C(0x6)
32198 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_IP_PROTOCOL_UDP UINT32_C(0x11)
32199 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_IP_PROTOCOL_LAST \
32200 HWRM_CFA_EM_FLOW_ALLOC_INPUT_IP_PROTOCOL_UDP
32201 uint8_t unused_1[2];
32203 * The value of source IP address to be used in filtering.
32204 * For IPv4, first four bytes represent the IP address.
32206 uint32_t src_ipaddr[4];
32208 * big_endian = True
32209 * The value of destination IP address to be used in filtering.
32210 * For IPv4, first four bytes represent the IP address.
32212 uint32_t dst_ipaddr[4];
32214 * The value of source port to be used in filtering.
32215 * Applies to UDP and TCP traffic.
32219 * The value of destination port to be used in filtering.
32220 * Applies to UDP and TCP traffic.
32224 * If set, this value shall represent the
32225 * Logical VNIC ID of the destination VNIC for the RX
32226 * path and network port id of the destination port for
32231 * Logical VNIC ID of the VNIC where traffic is
32234 uint16_t mirror_vnic_id;
32235 /* Logical ID of the encapsulation record. */
32236 uint32_t encap_record_id;
32237 uint8_t unused_2[4];
32240 /* hwrm_cfa_em_flow_alloc_output (size:192b/24B) */
32241 struct hwrm_cfa_em_flow_alloc_output {
32242 /* The specific error status for the command. */
32243 uint16_t error_code;
32244 /* The HWRM command request type. */
32246 /* The sequence ID from the original command. */
32248 /* The length of the response data in number of bytes. */
32250 /* This value is an opaque id into CFA data structures. */
32251 uint64_t em_filter_id;
32253 * The flow id value in bit 0-29 is the actual ID of the flow
32254 * associated with this filter and it shall be used to match
32255 * and associate the flow identifier returned in completion
32256 * records. A value of 0xFFFFFFFF in the 32-bit flow_id field
32257 * shall indicate no valid flow id.
32260 /* Indicate the flow id value. */
32261 #define HWRM_CFA_EM_FLOW_ALLOC_OUTPUT_FLOW_ID_VALUE_MASK \
32262 UINT32_C(0x3fffffff)
32263 #define HWRM_CFA_EM_FLOW_ALLOC_OUTPUT_FLOW_ID_VALUE_SFT 0
32264 /* Indicate type of the flow. */
32265 #define HWRM_CFA_EM_FLOW_ALLOC_OUTPUT_FLOW_ID_TYPE \
32266 UINT32_C(0x40000000)
32268 * If this bit set to 0, then it indicates that the flow is
32271 #define HWRM_CFA_EM_FLOW_ALLOC_OUTPUT_FLOW_ID_TYPE_INT \
32272 (UINT32_C(0x0) << 30)
32274 * If this bit is set to 1, then it indicates that the flow is
32277 #define HWRM_CFA_EM_FLOW_ALLOC_OUTPUT_FLOW_ID_TYPE_EXT \
32278 (UINT32_C(0x1) << 30)
32279 #define HWRM_CFA_EM_FLOW_ALLOC_OUTPUT_FLOW_ID_TYPE_LAST \
32280 HWRM_CFA_EM_FLOW_ALLOC_OUTPUT_FLOW_ID_TYPE_EXT
32281 /* Indicate the flow direction. */
32282 #define HWRM_CFA_EM_FLOW_ALLOC_OUTPUT_FLOW_ID_DIR \
32283 UINT32_C(0x80000000)
32284 /* If this bit set to 0, then it indicates rx flow. */
32285 #define HWRM_CFA_EM_FLOW_ALLOC_OUTPUT_FLOW_ID_DIR_RX \
32286 (UINT32_C(0x0) << 31)
32287 /* If this bit is set to 1, then it indicates that tx flow. */
32288 #define HWRM_CFA_EM_FLOW_ALLOC_OUTPUT_FLOW_ID_DIR_TX \
32289 (UINT32_C(0x1) << 31)
32290 #define HWRM_CFA_EM_FLOW_ALLOC_OUTPUT_FLOW_ID_DIR_LAST \
32291 HWRM_CFA_EM_FLOW_ALLOC_OUTPUT_FLOW_ID_DIR_TX
32292 uint8_t unused_0[3];
32294 * This field is used in Output records to indicate that the output
32295 * is completely written to RAM. This field should be read as '1'
32296 * to indicate that the output has been completely written.
32297 * When writing a command completion or response to an internal processor,
32298 * the order of writes has to be such that this field is written last.
32303 /*************************
32304 * hwrm_cfa_em_flow_free *
32305 *************************/
32308 /* hwrm_cfa_em_flow_free_input (size:192b/24B) */
32309 struct hwrm_cfa_em_flow_free_input {
32310 /* The HWRM command request type. */
32313 * The completion ring to send the completion event on. This should
32314 * be the NQ ID returned from the `nq_alloc` HWRM command.
32316 uint16_t cmpl_ring;
32318 * The sequence ID is used by the driver for tracking multiple
32319 * commands. This ID is treated as opaque data by the firmware and
32320 * the value is returned in the `hwrm_resp_hdr` upon completion.
32324 * The target ID of the command:
32325 * * 0x0-0xFFF8 - The function ID
32326 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
32327 * * 0xFFFD - Reserved for user-space HWRM interface
32330 uint16_t target_id;
32332 * A physical address pointer pointing to a host buffer that the
32333 * command's response data will be written. This can be either a host
32334 * physical address (HPA) or a guest physical address (GPA) and must
32335 * point to a physically contiguous block of memory.
32337 uint64_t resp_addr;
32338 /* This value is an opaque id into CFA data structures. */
32339 uint64_t em_filter_id;
32342 /* hwrm_cfa_em_flow_free_output (size:128b/16B) */
32343 struct hwrm_cfa_em_flow_free_output {
32344 /* The specific error status for the command. */
32345 uint16_t error_code;
32346 /* The HWRM command request type. */
32348 /* The sequence ID from the original command. */
32350 /* The length of the response data in number of bytes. */
32352 uint8_t unused_0[7];
32354 * This field is used in Output records to indicate that the output
32355 * is completely written to RAM. This field should be read as '1'
32356 * to indicate that the output has been completely written.
32357 * When writing a command completion or response to an internal processor,
32358 * the order of writes has to be such that this field is written last.
32363 /************************
32364 * hwrm_cfa_meter_qcaps *
32365 ************************/
32368 /* hwrm_cfa_meter_qcaps_input (size:128b/16B) */
32369 struct hwrm_cfa_meter_qcaps_input {
32370 /* The HWRM command request type. */
32373 * The completion ring to send the completion event on. This should
32374 * be the NQ ID returned from the `nq_alloc` HWRM command.
32376 uint16_t cmpl_ring;
32378 * The sequence ID is used by the driver for tracking multiple
32379 * commands. This ID is treated as opaque data by the firmware and
32380 * the value is returned in the `hwrm_resp_hdr` upon completion.
32384 * The target ID of the command:
32385 * * 0x0-0xFFF8 - The function ID
32386 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
32387 * * 0xFFFD - Reserved for user-space HWRM interface
32390 uint16_t target_id;
32392 * A physical address pointer pointing to a host buffer that the
32393 * command's response data will be written. This can be either a host
32394 * physical address (HPA) or a guest physical address (GPA) and must
32395 * point to a physically contiguous block of memory.
32397 uint64_t resp_addr;
32400 /* hwrm_cfa_meter_qcaps_output (size:320b/40B) */
32401 struct hwrm_cfa_meter_qcaps_output {
32402 /* The specific error status for the command. */
32403 uint16_t error_code;
32404 /* The HWRM command request type. */
32406 /* The sequence ID from the original command. */
32408 /* The length of the response data in number of bytes. */
32412 * Enumeration denoting the clock at which the Meter is running with.
32413 * This enumeration is used for resources that are similar for both
32414 * TX and RX paths of the chip.
32416 #define HWRM_CFA_METER_QCAPS_OUTPUT_FLAGS_CLOCK_MASK UINT32_C(0xf)
32417 #define HWRM_CFA_METER_QCAPS_OUTPUT_FLAGS_CLOCK_SFT 0
32419 #define HWRM_CFA_METER_QCAPS_OUTPUT_FLAGS_CLOCK_375MHZ UINT32_C(0x0)
32421 #define HWRM_CFA_METER_QCAPS_OUTPUT_FLAGS_CLOCK_625MHZ UINT32_C(0x1)
32422 #define HWRM_CFA_METER_QCAPS_OUTPUT_FLAGS_CLOCK_LAST \
32423 HWRM_CFA_METER_QCAPS_OUTPUT_FLAGS_CLOCK_625MHZ
32424 uint8_t unused_0[4];
32426 * The minimum guaranteed number of tx meter profiles supported
32427 * for this function.
32429 uint16_t min_tx_profile;
32431 * The maximum non-guaranteed number of tx meter profiles supported
32432 * for this function.
32434 uint16_t max_tx_profile;
32436 * The minimum guaranteed number of rx meter profiles supported
32437 * for this function.
32439 uint16_t min_rx_profile;
32441 * The maximum non-guaranteed number of rx meter profiles supported
32442 * for this function.
32444 uint16_t max_rx_profile;
32446 * The minimum guaranteed number of tx meter instances supported
32447 * for this function.
32449 uint16_t min_tx_instance;
32451 * The maximum non-guaranteed number of tx meter instances supported
32452 * for this function.
32454 uint16_t max_tx_instance;
32456 * The minimum guaranteed number of rx meter instances supported
32457 * for this function.
32459 uint16_t min_rx_instance;
32461 * The maximum non-guaranteed number of rx meter instances supported
32462 * for this function.
32464 uint16_t max_rx_instance;
32465 uint8_t unused_1[7];
32467 * This field is used in Output records to indicate that the output
32468 * is completely written to RAM. This field should be read as '1'
32469 * to indicate that the output has been completely written.
32470 * When writing a command completion or response to an internal processor,
32471 * the order of writes has to be such that this field is written last.
32476 /********************************
32477 * hwrm_cfa_meter_profile_alloc *
32478 ********************************/
32481 /* hwrm_cfa_meter_profile_alloc_input (size:320b/40B) */
32482 struct hwrm_cfa_meter_profile_alloc_input {
32483 /* The HWRM command request type. */
32486 * The completion ring to send the completion event on. This should
32487 * be the NQ ID returned from the `nq_alloc` HWRM command.
32489 uint16_t cmpl_ring;
32491 * The sequence ID is used by the driver for tracking multiple
32492 * commands. This ID is treated as opaque data by the firmware and
32493 * the value is returned in the `hwrm_resp_hdr` upon completion.
32497 * The target ID of the command:
32498 * * 0x0-0xFFF8 - The function ID
32499 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
32500 * * 0xFFFD - Reserved for user-space HWRM interface
32503 uint16_t target_id;
32505 * A physical address pointer pointing to a host buffer that the
32506 * command's response data will be written. This can be either a host
32507 * physical address (HPA) or a guest physical address (GPA) and must
32508 * point to a physically contiguous block of memory.
32510 uint64_t resp_addr;
32513 * Enumeration denoting the RX, TX type of the resource.
32514 * This enumeration is used for resources that are similar for both
32515 * TX and RX paths of the chip.
32517 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_FLAGS_PATH UINT32_C(0x1)
32519 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_FLAGS_PATH_TX \
32522 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_FLAGS_PATH_RX \
32524 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_FLAGS_PATH_LAST \
32525 HWRM_CFA_METER_PROFILE_ALLOC_INPUT_FLAGS_PATH_RX
32526 /* The meter algorithm type. */
32527 uint8_t meter_type;
32528 /* RFC 2697 (srTCM) */
32529 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_METER_TYPE_RFC2697 \
32531 /* RFC 2698 (trTCM) */
32532 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_METER_TYPE_RFC2698 \
32534 /* RFC 4115 (trTCM) */
32535 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_METER_TYPE_RFC4115 \
32537 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_METER_TYPE_LAST \
32538 HWRM_CFA_METER_PROFILE_ALLOC_INPUT_METER_TYPE_RFC4115
32540 * This field is reserved for the future use.
32541 * It shall be set to 0.
32543 uint16_t reserved1;
32545 * This field is reserved for the future use.
32546 * It shall be set to 0.
32548 uint32_t reserved2;
32549 /* A meter rate specified in bytes-per-second. */
32550 uint32_t commit_rate;
32551 /* The bandwidth value. */
32552 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_RATE_BW_VALUE_MASK \
32553 UINT32_C(0xfffffff)
32554 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_RATE_BW_VALUE_SFT \
32556 /* The granularity of the value (bits or bytes). */
32557 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_RATE_SCALE \
32558 UINT32_C(0x10000000)
32559 /* Value is in bits. */
32560 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_RATE_SCALE_BITS \
32561 (UINT32_C(0x0) << 28)
32562 /* Value is in bytes. */
32563 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_RATE_SCALE_BYTES \
32564 (UINT32_C(0x1) << 28)
32565 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_RATE_SCALE_LAST \
32566 HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_RATE_SCALE_BYTES
32567 /* bw_value_unit is 3 b */
32568 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_RATE_BW_VALUE_UNIT_MASK \
32569 UINT32_C(0xe0000000)
32570 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_RATE_BW_VALUE_UNIT_SFT \
32572 /* Value is in Mb or MB (base 10). */
32573 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_RATE_BW_VALUE_UNIT_MEGA \
32574 (UINT32_C(0x0) << 29)
32575 /* Value is in Kb or KB (base 10). */
32576 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_RATE_BW_VALUE_UNIT_KILO \
32577 (UINT32_C(0x2) << 29)
32578 /* Value is in bits or bytes. */
32579 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_RATE_BW_VALUE_UNIT_BASE \
32580 (UINT32_C(0x4) << 29)
32581 /* Value is in Gb or GB (base 10). */
32582 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_RATE_BW_VALUE_UNIT_GIGA \
32583 (UINT32_C(0x6) << 29)
32584 /* Value is in 1/100th of a percentage of total bandwidth. */
32585 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_RATE_BW_VALUE_UNIT_PERCENT1_100 \
32586 (UINT32_C(0x1) << 29)
32588 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_RATE_BW_VALUE_UNIT_RAW \
32589 (UINT32_C(0x7) << 29)
32590 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_RATE_BW_VALUE_UNIT_LAST \
32591 HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_RATE_BW_VALUE_UNIT_RAW
32592 /* A meter burst size specified in bytes. */
32593 uint32_t commit_burst;
32594 /* The bandwidth value. */
32595 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_BURST_BW_VALUE_MASK \
32596 UINT32_C(0xfffffff)
32597 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_BURST_BW_VALUE_SFT \
32599 /* The granularity of the value (bits or bytes). */
32600 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_BURST_SCALE \
32601 UINT32_C(0x10000000)
32602 /* Value is in bits. */
32603 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_BURST_SCALE_BITS \
32604 (UINT32_C(0x0) << 28)
32605 /* Value is in bytes. */
32606 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_BURST_SCALE_BYTES \
32607 (UINT32_C(0x1) << 28)
32608 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_BURST_SCALE_LAST \
32609 HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_BURST_SCALE_BYTES
32610 /* bw_value_unit is 3 b */
32611 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_BURST_BW_VALUE_UNIT_MASK \
32612 UINT32_C(0xe0000000)
32613 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_BURST_BW_VALUE_UNIT_SFT \
32615 /* Value is in Mb or MB (base 10). */
32616 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_BURST_BW_VALUE_UNIT_MEGA \
32617 (UINT32_C(0x0) << 29)
32618 /* Value is in Kb or KB (base 10). */
32619 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_BURST_BW_VALUE_UNIT_KILO \
32620 (UINT32_C(0x2) << 29)
32621 /* Value is in bits or bytes. */
32622 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_BURST_BW_VALUE_UNIT_BASE \
32623 (UINT32_C(0x4) << 29)
32624 /* Value is in Gb or GB (base 10). */
32625 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_BURST_BW_VALUE_UNIT_GIGA \
32626 (UINT32_C(0x6) << 29)
32627 /* Value is in 1/100th of a percentage of total bandwidth. */
32628 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_BURST_BW_VALUE_UNIT_PERCENT1_100 \
32629 (UINT32_C(0x1) << 29)
32630 /* Invalid value */
32631 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_BURST_BW_VALUE_UNIT_INVALID \
32632 (UINT32_C(0x7) << 29)
32633 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_BURST_BW_VALUE_UNIT_LAST \
32634 HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_BURST_BW_VALUE_UNIT_INVALID
32635 /* A meter rate specified in bytes-per-second. */
32636 uint32_t excess_peak_rate;
32637 /* The bandwidth value. */
32638 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_RATE_BW_VALUE_MASK \
32639 UINT32_C(0xfffffff)
32640 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_RATE_BW_VALUE_SFT \
32642 /* The granularity of the value (bits or bytes). */
32643 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_RATE_SCALE \
32644 UINT32_C(0x10000000)
32645 /* Value is in bits. */
32646 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_RATE_SCALE_BITS \
32647 (UINT32_C(0x0) << 28)
32648 /* Value is in bytes. */
32649 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_RATE_SCALE_BYTES \
32650 (UINT32_C(0x1) << 28)
32651 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_RATE_SCALE_LAST \
32652 HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_RATE_SCALE_BYTES
32653 /* bw_value_unit is 3 b */
32654 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_RATE_BW_VALUE_UNIT_MASK \
32655 UINT32_C(0xe0000000)
32656 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_RATE_BW_VALUE_UNIT_SFT \
32658 /* Value is in Mb or MB (base 10). */
32659 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_RATE_BW_VALUE_UNIT_MEGA \
32660 (UINT32_C(0x0) << 29)
32661 /* Value is in Kb or KB (base 10). */
32662 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_RATE_BW_VALUE_UNIT_KILO \
32663 (UINT32_C(0x2) << 29)
32664 /* Value is in bits or bytes. */
32665 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_RATE_BW_VALUE_UNIT_BASE \
32666 (UINT32_C(0x4) << 29)
32667 /* Value is in Gb or GB (base 10). */
32668 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_RATE_BW_VALUE_UNIT_GIGA \
32669 (UINT32_C(0x6) << 29)
32670 /* Value is in 1/100th of a percentage of total bandwidth. */
32671 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_RATE_BW_VALUE_UNIT_PERCENT1_100 \
32672 (UINT32_C(0x1) << 29)
32674 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_RATE_BW_VALUE_UNIT_RAW \
32675 (UINT32_C(0x7) << 29)
32676 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_RATE_BW_VALUE_UNIT_LAST \
32677 HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_RATE_BW_VALUE_UNIT_RAW
32678 /* A meter burst size specified in bytes. */
32679 uint32_t excess_peak_burst;
32680 /* The bandwidth value. */
32681 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_BURST_BW_VALUE_MASK \
32682 UINT32_C(0xfffffff)
32683 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_BURST_BW_VALUE_SFT \
32685 /* The granularity of the value (bits or bytes). */
32686 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_BURST_SCALE \
32687 UINT32_C(0x10000000)
32688 /* Value is in bits. */
32689 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_BURST_SCALE_BITS \
32690 (UINT32_C(0x0) << 28)
32691 /* Value is in bytes. */
32692 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_BURST_SCALE_BYTES \
32693 (UINT32_C(0x1) << 28)
32694 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_BURST_SCALE_LAST \
32695 HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_BURST_SCALE_BYTES
32696 /* bw_value_unit is 3 b */
32697 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_BURST_BW_VALUE_UNIT_MASK \
32698 UINT32_C(0xe0000000)
32699 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_BURST_BW_VALUE_UNIT_SFT \
32701 /* Value is in Mb or MB (base 10). */
32702 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_BURST_BW_VALUE_UNIT_MEGA \
32703 (UINT32_C(0x0) << 29)
32704 /* Value is in Kb or KB (base 10). */
32705 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_BURST_BW_VALUE_UNIT_KILO \
32706 (UINT32_C(0x2) << 29)
32707 /* Value is in bits or bytes. */
32708 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_BURST_BW_VALUE_UNIT_BASE \
32709 (UINT32_C(0x4) << 29)
32710 /* Value is in Gb or GB (base 10). */
32711 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_BURST_BW_VALUE_UNIT_GIGA \
32712 (UINT32_C(0x6) << 29)
32713 /* Value is in 1/100th of a percentage of total bandwidth. */
32714 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_BURST_BW_VALUE_UNIT_PERCENT1_100 \
32715 (UINT32_C(0x1) << 29)
32717 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_BURST_BW_VALUE_UNIT_INVALID \
32718 (UINT32_C(0x7) << 29)
32719 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_BURST_BW_VALUE_UNIT_LAST \
32720 HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_BURST_BW_VALUE_UNIT_INVALID
32723 /* hwrm_cfa_meter_profile_alloc_output (size:128b/16B) */
32724 struct hwrm_cfa_meter_profile_alloc_output {
32725 /* The specific error status for the command. */
32726 uint16_t error_code;
32727 /* The HWRM command request type. */
32729 /* The sequence ID from the original command. */
32731 /* The length of the response data in number of bytes. */
32733 /* This value identifies a meter profile in CFA. */
32734 uint16_t meter_profile_id;
32736 * A value of 0xfff is considered invalid and implies the
32737 * profile is not configured.
32739 #define HWRM_CFA_METER_PROFILE_ALLOC_OUTPUT_METER_PROFILE_ID_INVALID \
32741 #define HWRM_CFA_METER_PROFILE_ALLOC_OUTPUT_METER_PROFILE_ID_LAST \
32742 HWRM_CFA_METER_PROFILE_ALLOC_OUTPUT_METER_PROFILE_ID_INVALID
32743 uint8_t unused_0[5];
32745 * This field is used in Output records to indicate that the output
32746 * is completely written to RAM. This field should be read as '1'
32747 * to indicate that the output has been completely written.
32748 * When writing a command completion or response to an internal processor,
32749 * the order of writes has to be such that this field is written last.
32754 /*******************************
32755 * hwrm_cfa_meter_profile_free *
32756 *******************************/
32759 /* hwrm_cfa_meter_profile_free_input (size:192b/24B) */
32760 struct hwrm_cfa_meter_profile_free_input {
32761 /* The HWRM command request type. */
32764 * The completion ring to send the completion event on. This should
32765 * be the NQ ID returned from the `nq_alloc` HWRM command.
32767 uint16_t cmpl_ring;
32769 * The sequence ID is used by the driver for tracking multiple
32770 * commands. This ID is treated as opaque data by the firmware and
32771 * the value is returned in the `hwrm_resp_hdr` upon completion.
32775 * The target ID of the command:
32776 * * 0x0-0xFFF8 - The function ID
32777 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
32778 * * 0xFFFD - Reserved for user-space HWRM interface
32781 uint16_t target_id;
32783 * A physical address pointer pointing to a host buffer that the
32784 * command's response data will be written. This can be either a host
32785 * physical address (HPA) or a guest physical address (GPA) and must
32786 * point to a physically contiguous block of memory.
32788 uint64_t resp_addr;
32791 * Enumeration denoting the RX, TX type of the resource.
32792 * This enumeration is used for resources that are similar for both
32793 * TX and RX paths of the chip.
32795 #define HWRM_CFA_METER_PROFILE_FREE_INPUT_FLAGS_PATH UINT32_C(0x1)
32797 #define HWRM_CFA_METER_PROFILE_FREE_INPUT_FLAGS_PATH_TX \
32800 #define HWRM_CFA_METER_PROFILE_FREE_INPUT_FLAGS_PATH_RX \
32802 #define HWRM_CFA_METER_PROFILE_FREE_INPUT_FLAGS_PATH_LAST \
32803 HWRM_CFA_METER_PROFILE_FREE_INPUT_FLAGS_PATH_RX
32805 /* This value identifies a meter profile in CFA. */
32806 uint16_t meter_profile_id;
32808 * A value of 0xfff is considered invalid and implies the
32809 * profile is not configured.
32811 #define HWRM_CFA_METER_PROFILE_FREE_INPUT_METER_PROFILE_ID_INVALID \
32813 #define HWRM_CFA_METER_PROFILE_FREE_INPUT_METER_PROFILE_ID_LAST \
32814 HWRM_CFA_METER_PROFILE_FREE_INPUT_METER_PROFILE_ID_INVALID
32815 uint8_t unused_1[4];
32818 /* hwrm_cfa_meter_profile_free_output (size:128b/16B) */
32819 struct hwrm_cfa_meter_profile_free_output {
32820 /* The specific error status for the command. */
32821 uint16_t error_code;
32822 /* The HWRM command request type. */
32824 /* The sequence ID from the original command. */
32826 /* The length of the response data in number of bytes. */
32828 uint8_t unused_0[7];
32830 * This field is used in Output records to indicate that the output
32831 * is completely written to RAM. This field should be read as '1'
32832 * to indicate that the output has been completely written.
32833 * When writing a command completion or response to an internal processor,
32834 * the order of writes has to be such that this field is written last.
32839 /******************************
32840 * hwrm_cfa_meter_profile_cfg *
32841 ******************************/
32844 /* hwrm_cfa_meter_profile_cfg_input (size:320b/40B) */
32845 struct hwrm_cfa_meter_profile_cfg_input {
32846 /* The HWRM command request type. */
32849 * The completion ring to send the completion event on. This should
32850 * be the NQ ID returned from the `nq_alloc` HWRM command.
32852 uint16_t cmpl_ring;
32854 * The sequence ID is used by the driver for tracking multiple
32855 * commands. This ID is treated as opaque data by the firmware and
32856 * the value is returned in the `hwrm_resp_hdr` upon completion.
32860 * The target ID of the command:
32861 * * 0x0-0xFFF8 - The function ID
32862 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
32863 * * 0xFFFD - Reserved for user-space HWRM interface
32866 uint16_t target_id;
32868 * A physical address pointer pointing to a host buffer that the
32869 * command's response data will be written. This can be either a host
32870 * physical address (HPA) or a guest physical address (GPA) and must
32871 * point to a physically contiguous block of memory.
32873 uint64_t resp_addr;
32876 * Enumeration denoting the RX, TX type of the resource.
32877 * This enumeration is used for resources that are similar for both
32878 * TX and RX paths of the chip.
32880 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_FLAGS_PATH UINT32_C(0x1)
32882 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_FLAGS_PATH_TX UINT32_C(0x0)
32884 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_FLAGS_PATH_RX UINT32_C(0x1)
32885 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_FLAGS_PATH_LAST \
32886 HWRM_CFA_METER_PROFILE_CFG_INPUT_FLAGS_PATH_RX
32887 /* The meter algorithm type. */
32888 uint8_t meter_type;
32889 /* RFC 2697 (srTCM) */
32890 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_METER_TYPE_RFC2697 \
32892 /* RFC 2698 (trTCM) */
32893 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_METER_TYPE_RFC2698 \
32895 /* RFC 4115 (trTCM) */
32896 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_METER_TYPE_RFC4115 \
32898 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_METER_TYPE_LAST \
32899 HWRM_CFA_METER_PROFILE_CFG_INPUT_METER_TYPE_RFC4115
32900 /* This value identifies a meter profile in CFA. */
32901 uint16_t meter_profile_id;
32903 * A value of 0xfff is considered invalid and implies the
32904 * profile is not configured.
32906 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_METER_PROFILE_ID_INVALID \
32908 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_METER_PROFILE_ID_LAST \
32909 HWRM_CFA_METER_PROFILE_CFG_INPUT_METER_PROFILE_ID_INVALID
32911 * This field is reserved for the future use.
32912 * It shall be set to 0.
32915 /* A meter rate specified in bytes-per-second. */
32916 uint32_t commit_rate;
32917 /* The bandwidth value. */
32918 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_RATE_BW_VALUE_MASK \
32919 UINT32_C(0xfffffff)
32920 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_RATE_BW_VALUE_SFT \
32922 /* The granularity of the value (bits or bytes). */
32923 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_RATE_SCALE \
32924 UINT32_C(0x10000000)
32925 /* Value is in bits. */
32926 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_RATE_SCALE_BITS \
32927 (UINT32_C(0x0) << 28)
32928 /* Value is in bytes. */
32929 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_RATE_SCALE_BYTES \
32930 (UINT32_C(0x1) << 28)
32931 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_RATE_SCALE_LAST \
32932 HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_RATE_SCALE_BYTES
32933 /* bw_value_unit is 3 b */
32934 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_RATE_BW_VALUE_UNIT_MASK \
32935 UINT32_C(0xe0000000)
32936 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_RATE_BW_VALUE_UNIT_SFT \
32938 /* Value is in Mb or MB (base 10). */
32939 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_RATE_BW_VALUE_UNIT_MEGA \
32940 (UINT32_C(0x0) << 29)
32941 /* Value is in Kb or KB (base 10). */
32942 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_RATE_BW_VALUE_UNIT_KILO \
32943 (UINT32_C(0x2) << 29)
32944 /* Value is in bits or bytes. */
32945 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_RATE_BW_VALUE_UNIT_BASE \
32946 (UINT32_C(0x4) << 29)
32947 /* Value is in Gb or GB (base 10). */
32948 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_RATE_BW_VALUE_UNIT_GIGA \
32949 (UINT32_C(0x6) << 29)
32950 /* Value is in 1/100th of a percentage of total bandwidth. */
32951 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_RATE_BW_VALUE_UNIT_PERCENT1_100 \
32952 (UINT32_C(0x1) << 29)
32954 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_RATE_BW_VALUE_UNIT_RAW \
32955 (UINT32_C(0x7) << 29)
32956 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_RATE_BW_VALUE_UNIT_LAST \
32957 HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_RATE_BW_VALUE_UNIT_RAW
32958 /* A meter burst size specified in bytes. */
32959 uint32_t commit_burst;
32960 /* The bandwidth value. */
32961 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_BURST_BW_VALUE_MASK \
32962 UINT32_C(0xfffffff)
32963 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_BURST_BW_VALUE_SFT \
32965 /* The granularity of the value (bits or bytes). */
32966 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_BURST_SCALE \
32967 UINT32_C(0x10000000)
32968 /* Value is in bits. */
32969 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_BURST_SCALE_BITS \
32970 (UINT32_C(0x0) << 28)
32971 /* Value is in bytes. */
32972 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_BURST_SCALE_BYTES \
32973 (UINT32_C(0x1) << 28)
32974 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_BURST_SCALE_LAST \
32975 HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_BURST_SCALE_BYTES
32976 /* bw_value_unit is 3 b */
32977 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_BURST_BW_VALUE_UNIT_MASK \
32978 UINT32_C(0xe0000000)
32979 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_BURST_BW_VALUE_UNIT_SFT \
32981 /* Value is in Mb or MB (base 10). */
32982 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_BURST_BW_VALUE_UNIT_MEGA \
32983 (UINT32_C(0x0) << 29)
32984 /* Value is in Kb or KB (base 10). */
32985 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_BURST_BW_VALUE_UNIT_KILO \
32986 (UINT32_C(0x2) << 29)
32987 /* Value is in bits or bytes. */
32988 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_BURST_BW_VALUE_UNIT_BASE \
32989 (UINT32_C(0x4) << 29)
32990 /* Value is in Gb or GB (base 10). */
32991 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_BURST_BW_VALUE_UNIT_GIGA \
32992 (UINT32_C(0x6) << 29)
32993 /* Value is in 1/100th of a percentage of total bandwidth. */
32994 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_BURST_BW_VALUE_UNIT_PERCENT1_100 \
32995 (UINT32_C(0x1) << 29)
32996 /* Invalid value */
32997 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_BURST_BW_VALUE_UNIT_INVALID \
32998 (UINT32_C(0x7) << 29)
32999 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_BURST_BW_VALUE_UNIT_LAST \
33000 HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_BURST_BW_VALUE_UNIT_INVALID
33001 /* A meter rate specified in bytes-per-second. */
33002 uint32_t excess_peak_rate;
33003 /* The bandwidth value. */
33004 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_RATE_BW_VALUE_MASK \
33005 UINT32_C(0xfffffff)
33006 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_RATE_BW_VALUE_SFT \
33008 /* The granularity of the value (bits or bytes). */
33009 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_RATE_SCALE \
33010 UINT32_C(0x10000000)
33011 /* Value is in bits. */
33012 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_RATE_SCALE_BITS \
33013 (UINT32_C(0x0) << 28)
33014 /* Value is in bytes. */
33015 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_RATE_SCALE_BYTES \
33016 (UINT32_C(0x1) << 28)
33017 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_RATE_SCALE_LAST \
33018 HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_RATE_SCALE_BYTES
33019 /* bw_value_unit is 3 b */
33020 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_RATE_BW_VALUE_UNIT_MASK \
33021 UINT32_C(0xe0000000)
33022 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_RATE_BW_VALUE_UNIT_SFT \
33024 /* Value is in Mb or MB (base 10). */
33025 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_RATE_BW_VALUE_UNIT_MEGA \
33026 (UINT32_C(0x0) << 29)
33027 /* Value is in Kb or KB (base 10). */
33028 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_RATE_BW_VALUE_UNIT_KILO \
33029 (UINT32_C(0x2) << 29)
33030 /* Value is in bits or bytes. */
33031 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_RATE_BW_VALUE_UNIT_BASE \
33032 (UINT32_C(0x4) << 29)
33033 /* Value is in Gb or GB (base 10). */
33034 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_RATE_BW_VALUE_UNIT_GIGA \
33035 (UINT32_C(0x6) << 29)
33036 /* Value is in 1/100th of a percentage of total bandwidth. */
33037 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_RATE_BW_VALUE_UNIT_PERCENT1_100 \
33038 (UINT32_C(0x1) << 29)
33040 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_RATE_BW_VALUE_UNIT_RAW \
33041 (UINT32_C(0x7) << 29)
33042 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_RATE_BW_VALUE_UNIT_LAST \
33043 HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_RATE_BW_VALUE_UNIT_RAW
33044 /* A meter burst size specified in bytes. */
33045 uint32_t excess_peak_burst;
33046 /* The bandwidth value. */
33047 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_BURST_BW_VALUE_MASK \
33048 UINT32_C(0xfffffff)
33049 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_BURST_BW_VALUE_SFT \
33051 /* The granularity of the value (bits or bytes). */
33052 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_BURST_SCALE \
33053 UINT32_C(0x10000000)
33054 /* Value is in bits. */
33055 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_BURST_SCALE_BITS \
33056 (UINT32_C(0x0) << 28)
33057 /* Value is in bytes. */
33058 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_BURST_SCALE_BYTES \
33059 (UINT32_C(0x1) << 28)
33060 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_BURST_SCALE_LAST \
33061 HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_BURST_SCALE_BYTES
33062 /* bw_value_unit is 3 b */
33063 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_BURST_BW_VALUE_UNIT_MASK \
33064 UINT32_C(0xe0000000)
33065 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_BURST_BW_VALUE_UNIT_SFT \
33067 /* Value is in Mb or MB (base 10). */
33068 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_BURST_BW_VALUE_UNIT_MEGA \
33069 (UINT32_C(0x0) << 29)
33070 /* Value is in Kb or KB (base 10). */
33071 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_BURST_BW_VALUE_UNIT_KILO \
33072 (UINT32_C(0x2) << 29)
33073 /* Value is in bits or bytes. */
33074 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_BURST_BW_VALUE_UNIT_BASE \
33075 (UINT32_C(0x4) << 29)
33076 /* Value is in Gb or GB (base 10). */
33077 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_BURST_BW_VALUE_UNIT_GIGA \
33078 (UINT32_C(0x6) << 29)
33079 /* Value is in 1/100th of a percentage of total bandwidth. */
33080 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_BURST_BW_VALUE_UNIT_PERCENT1_100 \
33081 (UINT32_C(0x1) << 29)
33083 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_BURST_BW_VALUE_UNIT_INVALID \
33084 (UINT32_C(0x7) << 29)
33085 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_BURST_BW_VALUE_UNIT_LAST \
33086 HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_BURST_BW_VALUE_UNIT_INVALID
33089 /* hwrm_cfa_meter_profile_cfg_output (size:128b/16B) */
33090 struct hwrm_cfa_meter_profile_cfg_output {
33091 /* The specific error status for the command. */
33092 uint16_t error_code;
33093 /* The HWRM command request type. */
33095 /* The sequence ID from the original command. */
33097 /* The length of the response data in number of bytes. */
33099 uint8_t unused_0[7];
33101 * This field is used in Output records to indicate that the output
33102 * is completely written to RAM. This field should be read as '1'
33103 * to indicate that the output has been completely written.
33104 * When writing a command completion or response to an internal processor,
33105 * the order of writes has to be such that this field is written last.
33110 /*********************************
33111 * hwrm_cfa_meter_instance_alloc *
33112 *********************************/
33115 /* hwrm_cfa_meter_instance_alloc_input (size:192b/24B) */
33116 struct hwrm_cfa_meter_instance_alloc_input {
33117 /* The HWRM command request type. */
33120 * The completion ring to send the completion event on. This should
33121 * be the NQ ID returned from the `nq_alloc` HWRM command.
33123 uint16_t cmpl_ring;
33125 * The sequence ID is used by the driver for tracking multiple
33126 * commands. This ID is treated as opaque data by the firmware and
33127 * the value is returned in the `hwrm_resp_hdr` upon completion.
33131 * The target ID of the command:
33132 * * 0x0-0xFFF8 - The function ID
33133 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
33134 * * 0xFFFD - Reserved for user-space HWRM interface
33137 uint16_t target_id;
33139 * A physical address pointer pointing to a host buffer that the
33140 * command's response data will be written. This can be either a host
33141 * physical address (HPA) or a guest physical address (GPA) and must
33142 * point to a physically contiguous block of memory.
33144 uint64_t resp_addr;
33147 * Enumeration denoting the RX, TX type of the resource.
33148 * This enumeration is used for resources that are similar for both
33149 * TX and RX paths of the chip.
33151 #define HWRM_CFA_METER_INSTANCE_ALLOC_INPUT_FLAGS_PATH \
33154 #define HWRM_CFA_METER_INSTANCE_ALLOC_INPUT_FLAGS_PATH_TX \
33157 #define HWRM_CFA_METER_INSTANCE_ALLOC_INPUT_FLAGS_PATH_RX \
33159 #define HWRM_CFA_METER_INSTANCE_ALLOC_INPUT_FLAGS_PATH_LAST \
33160 HWRM_CFA_METER_INSTANCE_ALLOC_INPUT_FLAGS_PATH_RX
33162 /* This value identifies a meter profile in CFA. */
33163 uint16_t meter_profile_id;
33165 * A value of 0xffff is considered invalid and implies the
33166 * profile is not configured.
33168 #define HWRM_CFA_METER_INSTANCE_ALLOC_INPUT_METER_PROFILE_ID_INVALID \
33170 #define HWRM_CFA_METER_INSTANCE_ALLOC_INPUT_METER_PROFILE_ID_LAST \
33171 HWRM_CFA_METER_INSTANCE_ALLOC_INPUT_METER_PROFILE_ID_INVALID
33172 uint8_t unused_1[4];
33175 /* hwrm_cfa_meter_instance_alloc_output (size:128b/16B) */
33176 struct hwrm_cfa_meter_instance_alloc_output {
33177 /* The specific error status for the command. */
33178 uint16_t error_code;
33179 /* The HWRM command request type. */
33181 /* The sequence ID from the original command. */
33183 /* The length of the response data in number of bytes. */
33185 /* This value identifies a meter instance in CFA. */
33186 uint16_t meter_instance_id;
33188 * A value of 0xffff is considered invalid and implies the
33189 * instance is not configured.
33191 #define HWRM_CFA_METER_INSTANCE_ALLOC_OUTPUT_METER_INSTANCE_ID_INVALID \
33193 #define HWRM_CFA_METER_INSTANCE_ALLOC_OUTPUT_METER_INSTANCE_ID_LAST \
33194 HWRM_CFA_METER_INSTANCE_ALLOC_OUTPUT_METER_INSTANCE_ID_INVALID
33195 uint8_t unused_0[5];
33197 * This field is used in Output records to indicate that the output
33198 * is completely written to RAM. This field should be read as '1'
33199 * to indicate that the output has been completely written.
33200 * When writing a command completion or response to an internal processor,
33201 * the order of writes has to be such that this field is written last.
33206 /*******************************
33207 * hwrm_cfa_meter_instance_cfg *
33208 *******************************/
33211 /* hwrm_cfa_meter_instance_cfg_input (size:192b/24B) */
33212 struct hwrm_cfa_meter_instance_cfg_input {
33213 /* The HWRM command request type. */
33216 * The completion ring to send the completion event on. This should
33217 * be the NQ ID returned from the `nq_alloc` HWRM command.
33219 uint16_t cmpl_ring;
33221 * The sequence ID is used by the driver for tracking multiple
33222 * commands. This ID is treated as opaque data by the firmware and
33223 * the value is returned in the `hwrm_resp_hdr` upon completion.
33227 * The target ID of the command:
33228 * * 0x0-0xFFF8 - The function ID
33229 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
33230 * * 0xFFFD - Reserved for user-space HWRM interface
33233 uint16_t target_id;
33235 * A physical address pointer pointing to a host buffer that the
33236 * command's response data will be written. This can be either a host
33237 * physical address (HPA) or a guest physical address (GPA) and must
33238 * point to a physically contiguous block of memory.
33240 uint64_t resp_addr;
33243 * Enumeration denoting the RX, TX type of the resource.
33244 * This enumeration is used for resources that are similar for both
33245 * TX and RX paths of the chip.
33247 #define HWRM_CFA_METER_INSTANCE_CFG_INPUT_FLAGS_PATH UINT32_C(0x1)
33249 #define HWRM_CFA_METER_INSTANCE_CFG_INPUT_FLAGS_PATH_TX \
33252 #define HWRM_CFA_METER_INSTANCE_CFG_INPUT_FLAGS_PATH_RX \
33254 #define HWRM_CFA_METER_INSTANCE_CFG_INPUT_FLAGS_PATH_LAST \
33255 HWRM_CFA_METER_INSTANCE_CFG_INPUT_FLAGS_PATH_RX
33258 * This value identifies a new meter profile to be associated with
33259 * the meter instance specified in this command.
33261 uint16_t meter_profile_id;
33263 * A value of 0xffff is considered invalid and implies the
33264 * profile is not configured.
33266 #define HWRM_CFA_METER_INSTANCE_CFG_INPUT_METER_PROFILE_ID_INVALID \
33268 #define HWRM_CFA_METER_INSTANCE_CFG_INPUT_METER_PROFILE_ID_LAST \
33269 HWRM_CFA_METER_INSTANCE_CFG_INPUT_METER_PROFILE_ID_INVALID
33271 * This value identifies the ID of a meter instance that needs to be updated with
33272 * a new meter profile specified in this command.
33274 uint16_t meter_instance_id;
33275 uint8_t unused_1[2];
33278 /* hwrm_cfa_meter_instance_cfg_output (size:128b/16B) */
33279 struct hwrm_cfa_meter_instance_cfg_output {
33280 /* The specific error status for the command. */
33281 uint16_t error_code;
33282 /* The HWRM command request type. */
33284 /* The sequence ID from the original command. */
33286 /* The length of the response data in number of bytes. */
33288 uint8_t unused_0[7];
33290 * This field is used in Output records to indicate that the output
33291 * is completely written to RAM. This field should be read as '1'
33292 * to indicate that the output has been completely written.
33293 * When writing a command completion or response to an internal processor,
33294 * the order of writes has to be such that this field is written last.
33299 /********************************
33300 * hwrm_cfa_meter_instance_free *
33301 ********************************/
33304 /* hwrm_cfa_meter_instance_free_input (size:192b/24B) */
33305 struct hwrm_cfa_meter_instance_free_input {
33306 /* The HWRM command request type. */
33309 * The completion ring to send the completion event on. This should
33310 * be the NQ ID returned from the `nq_alloc` HWRM command.
33312 uint16_t cmpl_ring;
33314 * The sequence ID is used by the driver for tracking multiple
33315 * commands. This ID is treated as opaque data by the firmware and
33316 * the value is returned in the `hwrm_resp_hdr` upon completion.
33320 * The target ID of the command:
33321 * * 0x0-0xFFF8 - The function ID
33322 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
33323 * * 0xFFFD - Reserved for user-space HWRM interface
33326 uint16_t target_id;
33328 * A physical address pointer pointing to a host buffer that the
33329 * command's response data will be written. This can be either a host
33330 * physical address (HPA) or a guest physical address (GPA) and must
33331 * point to a physically contiguous block of memory.
33333 uint64_t resp_addr;
33336 * Enumeration denoting the RX, TX type of the resource.
33337 * This enumeration is used for resources that are similar for both
33338 * TX and RX paths of the chip.
33340 #define HWRM_CFA_METER_INSTANCE_FREE_INPUT_FLAGS_PATH UINT32_C(0x1)
33342 #define HWRM_CFA_METER_INSTANCE_FREE_INPUT_FLAGS_PATH_TX \
33345 #define HWRM_CFA_METER_INSTANCE_FREE_INPUT_FLAGS_PATH_RX \
33347 #define HWRM_CFA_METER_INSTANCE_FREE_INPUT_FLAGS_PATH_LAST \
33348 HWRM_CFA_METER_INSTANCE_FREE_INPUT_FLAGS_PATH_RX
33350 /* This value identifies a meter instance in CFA. */
33351 uint16_t meter_instance_id;
33353 * A value of 0xfff is considered invalid and implies the
33354 * instance is not configured.
33356 #define HWRM_CFA_METER_INSTANCE_FREE_INPUT_METER_INSTANCE_ID_INVALID \
33358 #define HWRM_CFA_METER_INSTANCE_FREE_INPUT_METER_INSTANCE_ID_LAST \
33359 HWRM_CFA_METER_INSTANCE_FREE_INPUT_METER_INSTANCE_ID_INVALID
33360 uint8_t unused_1[4];
33363 /* hwrm_cfa_meter_instance_free_output (size:128b/16B) */
33364 struct hwrm_cfa_meter_instance_free_output {
33365 /* The specific error status for the command. */
33366 uint16_t error_code;
33367 /* The HWRM command request type. */
33369 /* The sequence ID from the original command. */
33371 /* The length of the response data in number of bytes. */
33373 uint8_t unused_0[7];
33375 * This field is used in Output records to indicate that the output
33376 * is completely written to RAM. This field should be read as '1'
33377 * to indicate that the output has been completely written.
33378 * When writing a command completion or response to an internal processor,
33379 * the order of writes has to be such that this field is written last.
33384 /*******************************
33385 * hwrm_cfa_decap_filter_alloc *
33386 *******************************/
33389 /* hwrm_cfa_decap_filter_alloc_input (size:832b/104B) */
33390 struct hwrm_cfa_decap_filter_alloc_input {
33391 /* The HWRM command request type. */
33394 * The completion ring to send the completion event on. This should
33395 * be the NQ ID returned from the `nq_alloc` HWRM command.
33397 uint16_t cmpl_ring;
33399 * The sequence ID is used by the driver for tracking multiple
33400 * commands. This ID is treated as opaque data by the firmware and
33401 * the value is returned in the `hwrm_resp_hdr` upon completion.
33405 * The target ID of the command:
33406 * * 0x0-0xFFF8 - The function ID
33407 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
33408 * * 0xFFFD - Reserved for user-space HWRM interface
33411 uint16_t target_id;
33413 * A physical address pointer pointing to a host buffer that the
33414 * command's response data will be written. This can be either a host
33415 * physical address (HPA) or a guest physical address (GPA) and must
33416 * point to a physically contiguous block of memory.
33418 uint64_t resp_addr;
33420 /* ovs_tunnel is 1 b */
33421 #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_FLAGS_OVS_TUNNEL \
33425 * This bit must be '1' for the tunnel_type field to be
33428 #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_ENABLES_TUNNEL_TYPE \
33431 * This bit must be '1' for the tunnel_id field to be
33434 #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_ENABLES_TUNNEL_ID \
33437 * This bit must be '1' for the src_macaddr field to be
33440 #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_ENABLES_SRC_MACADDR \
33443 * This bit must be '1' for the dst_macaddr field to be
33446 #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_ENABLES_DST_MACADDR \
33449 * This bit must be '1' for the ovlan_vid field to be
33452 #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_ENABLES_OVLAN_VID \
33455 * This bit must be '1' for the ivlan_vid field to be
33458 #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_ENABLES_IVLAN_VID \
33461 * This bit must be '1' for the t_ovlan_vid field to be
33464 #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_ENABLES_T_OVLAN_VID \
33467 * This bit must be '1' for the t_ivlan_vid field to be
33470 #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_ENABLES_T_IVLAN_VID \
33473 * This bit must be '1' for the ethertype field to be
33476 #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_ENABLES_ETHERTYPE \
33479 * This bit must be '1' for the src_ipaddr field to be
33482 #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_ENABLES_SRC_IPADDR \
33485 * This bit must be '1' for the dst_ipaddr field to be
33488 #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_ENABLES_DST_IPADDR \
33491 * This bit must be '1' for the ipaddr_type field to be
33494 #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_ENABLES_IPADDR_TYPE \
33497 * This bit must be '1' for the ip_protocol field to be
33500 #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_ENABLES_IP_PROTOCOL \
33503 * This bit must be '1' for the src_port field to be
33506 #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_ENABLES_SRC_PORT \
33509 * This bit must be '1' for the dst_port field to be
33512 #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_ENABLES_DST_PORT \
33515 * This bit must be '1' for the dst_id field to be
33518 #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_ENABLES_DST_ID \
33521 * This bit must be '1' for the mirror_vnic_id field to be
33524 #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_ENABLES_MIRROR_VNIC_ID \
33527 * Tunnel identifier.
33528 * Virtual Network Identifier (VNI). Only valid with
33529 * tunnel_types VXLAN, NVGRE, and Geneve.
33530 * Only lower 24-bits of VNI field are used
33531 * in setting up the filter.
33533 uint32_t tunnel_id;
33535 uint8_t tunnel_type;
33537 #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_TUNNEL_TYPE_NONTUNNEL \
33539 /* Virtual eXtensible Local Area Network (VXLAN) */
33540 #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_TUNNEL_TYPE_VXLAN \
33542 /* Network Virtualization Generic Routing Encapsulation (NVGRE) */
33543 #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_TUNNEL_TYPE_NVGRE \
33545 /* Generic Routing Encapsulation (GRE) inside Ethernet payload */
33546 #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_TUNNEL_TYPE_L2GRE \
33549 #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_TUNNEL_TYPE_IPIP \
33551 /* Generic Network Virtualization Encapsulation (Geneve) */
33552 #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_TUNNEL_TYPE_GENEVE \
33554 /* Multi-Protocol Label Switching (MPLS) */
33555 #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_TUNNEL_TYPE_MPLS \
33557 /* Stateless Transport Tunnel (STT) */
33558 #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_TUNNEL_TYPE_STT \
33560 /* Generic Routing Encapsulation (GRE) inside IP datagram payload */
33561 #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_TUNNEL_TYPE_IPGRE \
33563 /* IPV4 over virtual eXtensible Local Area Network (IPV4oVXLAN) */
33564 #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_TUNNEL_TYPE_VXLAN_V4 \
33566 /* Enhance Generic Routing Encapsulation (GRE version 1) inside IP datagram payload */
33567 #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_TUNNEL_TYPE_IPGRE_V1 \
33569 /* Use fixed layer 2 ether type of 0xFFFF */
33570 #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_TUNNEL_TYPE_L2_ETYPE \
33572 /* IPV6 over virtual eXtensible Local Area Network with GPE header (IPV6oVXLANGPE) */
33573 #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_TUNNEL_TYPE_VXLAN_GPE_V6 \
33575 /* Any tunneled traffic */
33576 #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_TUNNEL_TYPE_ANYTUNNEL \
33578 #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_TUNNEL_TYPE_LAST \
33579 HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_TUNNEL_TYPE_ANYTUNNEL
33583 * This value indicates the source MAC address in
33584 * the Ethernet header.
33586 uint8_t src_macaddr[6];
33587 uint8_t unused_2[2];
33589 * This value indicates the destination MAC address in
33590 * the Ethernet header.
33592 uint8_t dst_macaddr[6];
33594 * This value indicates the VLAN ID of the outer VLAN tag
33595 * in the Ethernet header.
33597 uint16_t ovlan_vid;
33599 * This value indicates the VLAN ID of the inner VLAN tag
33600 * in the Ethernet header.
33602 uint16_t ivlan_vid;
33604 * This value indicates the VLAN ID of the outer VLAN tag
33605 * in the tunnel Ethernet header.
33607 uint16_t t_ovlan_vid;
33609 * This value indicates the VLAN ID of the inner VLAN tag
33610 * in the tunnel Ethernet header.
33612 uint16_t t_ivlan_vid;
33613 /* This value indicates the ethertype in the Ethernet header. */
33614 uint16_t ethertype;
33616 * This value indicates the type of IP address.
33619 * All others are invalid.
33621 uint8_t ip_addr_type;
33623 #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_IP_ADDR_TYPE_UNKNOWN \
33626 #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_IP_ADDR_TYPE_IPV4 \
33629 #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_IP_ADDR_TYPE_IPV6 \
33631 #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_IP_ADDR_TYPE_LAST \
33632 HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_IP_ADDR_TYPE_IPV6
33634 * The value of protocol filed in IP header.
33635 * Applies to UDP and TCP traffic.
33639 uint8_t ip_protocol;
33641 #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_IP_PROTOCOL_UNKNOWN \
33644 #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_IP_PROTOCOL_TCP \
33647 #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_IP_PROTOCOL_UDP \
33649 #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_IP_PROTOCOL_LAST \
33650 HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_IP_PROTOCOL_UDP
33654 * The value of source IP address to be used in filtering.
33655 * For IPv4, first four bytes represent the IP address.
33657 uint32_t src_ipaddr[4];
33659 * The value of destination IP address to be used in filtering.
33660 * For IPv4, first four bytes represent the IP address.
33662 uint32_t dst_ipaddr[4];
33664 * The value of source port to be used in filtering.
33665 * Applies to UDP and TCP traffic.
33669 * The value of destination port to be used in filtering.
33670 * Applies to UDP and TCP traffic.
33674 * If set, this value shall represent the
33675 * Logical VNIC ID of the destination VNIC for the RX
33680 * If set, this value shall represent the L2 context that matches the L2
33681 * information of the decap filter.
33683 uint16_t l2_ctxt_ref_id;
33686 /* hwrm_cfa_decap_filter_alloc_output (size:128b/16B) */
33687 struct hwrm_cfa_decap_filter_alloc_output {
33688 /* The specific error status for the command. */
33689 uint16_t error_code;
33690 /* The HWRM command request type. */
33692 /* The sequence ID from the original command. */
33694 /* The length of the response data in number of bytes. */
33696 /* This value is an opaque id into CFA data structures. */
33697 uint32_t decap_filter_id;
33698 uint8_t unused_0[3];
33700 * This field is used in Output records to indicate that the output
33701 * is completely written to RAM. This field should be read as '1'
33702 * to indicate that the output has been completely written.
33703 * When writing a command completion or response to an internal processor,
33704 * the order of writes has to be such that this field is written last.
33709 /******************************
33710 * hwrm_cfa_decap_filter_free *
33711 ******************************/
33714 /* hwrm_cfa_decap_filter_free_input (size:192b/24B) */
33715 struct hwrm_cfa_decap_filter_free_input {
33716 /* The HWRM command request type. */
33719 * The completion ring to send the completion event on. This should
33720 * be the NQ ID returned from the `nq_alloc` HWRM command.
33722 uint16_t cmpl_ring;
33724 * The sequence ID is used by the driver for tracking multiple
33725 * commands. This ID is treated as opaque data by the firmware and
33726 * the value is returned in the `hwrm_resp_hdr` upon completion.
33730 * The target ID of the command:
33731 * * 0x0-0xFFF8 - The function ID
33732 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
33733 * * 0xFFFD - Reserved for user-space HWRM interface
33736 uint16_t target_id;
33738 * A physical address pointer pointing to a host buffer that the
33739 * command's response data will be written. This can be either a host
33740 * physical address (HPA) or a guest physical address (GPA) and must
33741 * point to a physically contiguous block of memory.
33743 uint64_t resp_addr;
33744 /* This value is an opaque id into CFA data structures. */
33745 uint32_t decap_filter_id;
33746 uint8_t unused_0[4];
33749 /* hwrm_cfa_decap_filter_free_output (size:128b/16B) */
33750 struct hwrm_cfa_decap_filter_free_output {
33751 /* The specific error status for the command. */
33752 uint16_t error_code;
33753 /* The HWRM command request type. */
33755 /* The sequence ID from the original command. */
33757 /* The length of the response data in number of bytes. */
33759 uint8_t unused_0[7];
33761 * This field is used in Output records to indicate that the output
33762 * is completely written to RAM. This field should be read as '1'
33763 * to indicate that the output has been completely written.
33764 * When writing a command completion or response to an internal processor,
33765 * the order of writes has to be such that this field is written last.
33770 /***********************
33771 * hwrm_cfa_flow_alloc *
33772 ***********************/
33775 /* hwrm_cfa_flow_alloc_input (size:1024b/128B) */
33776 struct hwrm_cfa_flow_alloc_input {
33777 /* The HWRM command request type. */
33780 * The completion ring to send the completion event on. This should
33781 * be the NQ ID returned from the `nq_alloc` HWRM command.
33783 uint16_t cmpl_ring;
33785 * The sequence ID is used by the driver for tracking multiple
33786 * commands. This ID is treated as opaque data by the firmware and
33787 * the value is returned in the `hwrm_resp_hdr` upon completion.
33791 * The target ID of the command:
33792 * * 0x0-0xFFF8 - The function ID
33793 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
33794 * * 0xFFFD - Reserved for user-space HWRM interface
33797 uint16_t target_id;
33799 * A physical address pointer pointing to a host buffer that the
33800 * command's response data will be written. This can be either a host
33801 * physical address (HPA) or a guest physical address (GPA) and must
33802 * point to a physically contiguous block of memory.
33804 uint64_t resp_addr;
33806 /* tunnel is 1 b */
33807 #define HWRM_CFA_FLOW_ALLOC_INPUT_FLAGS_TUNNEL \
33809 /* num_vlan is 2 b */
33810 #define HWRM_CFA_FLOW_ALLOC_INPUT_FLAGS_NUM_VLAN_MASK \
33812 #define HWRM_CFA_FLOW_ALLOC_INPUT_FLAGS_NUM_VLAN_SFT 1
33814 #define HWRM_CFA_FLOW_ALLOC_INPUT_FLAGS_NUM_VLAN_NONE \
33815 (UINT32_C(0x0) << 1)
33817 #define HWRM_CFA_FLOW_ALLOC_INPUT_FLAGS_NUM_VLAN_ONE \
33818 (UINT32_C(0x1) << 1)
33820 #define HWRM_CFA_FLOW_ALLOC_INPUT_FLAGS_NUM_VLAN_TWO \
33821 (UINT32_C(0x2) << 1)
33822 #define HWRM_CFA_FLOW_ALLOC_INPUT_FLAGS_NUM_VLAN_LAST \
33823 HWRM_CFA_FLOW_ALLOC_INPUT_FLAGS_NUM_VLAN_TWO
33824 /* Enumeration denoting the Flow Type. */
33825 #define HWRM_CFA_FLOW_ALLOC_INPUT_FLAGS_FLOWTYPE_MASK \
33827 #define HWRM_CFA_FLOW_ALLOC_INPUT_FLAGS_FLOWTYPE_SFT 3
33829 #define HWRM_CFA_FLOW_ALLOC_INPUT_FLAGS_FLOWTYPE_L2 \
33830 (UINT32_C(0x0) << 3)
33832 #define HWRM_CFA_FLOW_ALLOC_INPUT_FLAGS_FLOWTYPE_IPV4 \
33833 (UINT32_C(0x1) << 3)
33835 #define HWRM_CFA_FLOW_ALLOC_INPUT_FLAGS_FLOWTYPE_IPV6 \
33836 (UINT32_C(0x2) << 3)
33837 #define HWRM_CFA_FLOW_ALLOC_INPUT_FLAGS_FLOWTYPE_LAST \
33838 HWRM_CFA_FLOW_ALLOC_INPUT_FLAGS_FLOWTYPE_IPV6
33840 * when set to 1, indicates TX flow offload for function specified in src_fid and
33841 * the dst_fid should be set to invalid value. To indicate a VM to VM flow, both
33842 * of the path_tx and path_rx flags need to be set. For virtio vSwitch offload
33843 * case, the src_fid and dst_fid is set to the same fid value. For the SRIOV
33844 * vSwitch offload case, the src_fid and dst_fid must be set to the same VF FID
33845 * belong to the children VFs of the same PF to indicate VM to VM flow.
33847 #define HWRM_CFA_FLOW_ALLOC_INPUT_FLAGS_PATH_TX \
33850 * when set to 1, indicates RX flow offload for function specified in dst_fid and
33851 * the src_fid should be set to invalid value.
33853 #define HWRM_CFA_FLOW_ALLOC_INPUT_FLAGS_PATH_RX \
33856 * Set to 1 to indicate matching of VXLAN VNI from the custom vxlan header is
33857 * required and the VXLAN VNI value is stored in the first 24 bits of the dmac field.
33858 * This flag is only valid when the flow direction is RX.
33860 #define HWRM_CFA_FLOW_ALLOC_INPUT_FLAGS_MATCH_VXLAN_IP_VNI \
33862 /* Set to 1 to indicate vhost_id is specified in the outer_vlan_tci field. */
33863 #define HWRM_CFA_FLOW_ALLOC_INPUT_FLAGS_VHOST_ID_USE_VLAN \
33870 /* Tunnel handle valid when tunnel flag is set. */
33871 uint32_t tunnel_handle;
33872 uint16_t action_flags;
33874 * Setting of this flag indicates drop action. If this flag is not set,
33875 * then it should be considered accept action.
33877 #define HWRM_CFA_FLOW_ALLOC_INPUT_ACTION_FLAGS_FWD \
33879 /* recycle is 1 b */
33880 #define HWRM_CFA_FLOW_ALLOC_INPUT_ACTION_FLAGS_RECYCLE \
33883 * Setting of this flag indicates drop action. If this flag is not set,
33884 * then it should be considered accept action.
33886 #define HWRM_CFA_FLOW_ALLOC_INPUT_ACTION_FLAGS_DROP \
33889 #define HWRM_CFA_FLOW_ALLOC_INPUT_ACTION_FLAGS_METER \
33891 /* tunnel is 1 b */
33892 #define HWRM_CFA_FLOW_ALLOC_INPUT_ACTION_FLAGS_TUNNEL \
33894 /* nat_src is 1 b */
33895 #define HWRM_CFA_FLOW_ALLOC_INPUT_ACTION_FLAGS_NAT_SRC \
33897 /* nat_dest is 1 b */
33898 #define HWRM_CFA_FLOW_ALLOC_INPUT_ACTION_FLAGS_NAT_DEST \
33900 /* nat_ipv4_address is 1 b */
33901 #define HWRM_CFA_FLOW_ALLOC_INPUT_ACTION_FLAGS_NAT_IPV4_ADDRESS \
33903 /* l2_header_rewrite is 1 b */
33904 #define HWRM_CFA_FLOW_ALLOC_INPUT_ACTION_FLAGS_L2_HEADER_REWRITE \
33906 /* ttl_decrement is 1 b */
33907 #define HWRM_CFA_FLOW_ALLOC_INPUT_ACTION_FLAGS_TTL_DECREMENT \
33910 * If set to 1 and flow direction is TX, it indicates decap of L2 header
33911 * and encap of tunnel header. If set to 1 and flow direction is RX, it
33912 * indicates decap of tunnel header and encap L2 header. The type of tunnel
33913 * is specified in the tunnel_type field.
33915 #define HWRM_CFA_FLOW_ALLOC_INPUT_ACTION_FLAGS_TUNNEL_IP \
33917 /* If set to 1, flow aging is enabled for this flow. */
33918 #define HWRM_CFA_FLOW_ALLOC_INPUT_ACTION_FLAGS_FLOW_AGING_ENABLED \
33921 * If set to 1 an attempt will be made to try to offload this flow to the
33922 * most optimal flow table resource. If set to 0, the flow will be
33923 * placed to the default flow table resource.
33925 #define HWRM_CFA_FLOW_ALLOC_INPUT_ACTION_FLAGS_PRI_HINT \
33928 * If set to 1 there will be no attempt to allocate an on-chip try to
33929 * offload this flow. If set to 0, which will keep compatibility with the
33930 * older drivers, will cause the FW to attempt to allocate an on-chip flow
33931 * counter for the newly created flow. This will keep the existing behavior
33932 * with EM flows which always had an associated flow counter.
33934 #define HWRM_CFA_FLOW_ALLOC_INPUT_ACTION_FLAGS_NO_FLOW_COUNTER_ALLOC \
33937 * Tx Flow: pf or vf fid.
33941 /* VLAN tpid, valid when push_vlan flag is set. */
33942 uint16_t l2_rewrite_vlan_tpid;
33943 /* VLAN tci, valid when push_vlan flag is set. */
33944 uint16_t l2_rewrite_vlan_tci;
33945 /* Meter id, valid when meter flag is set. */
33946 uint16_t act_meter_id;
33947 /* Flow with the same l2 context tcam key. */
33948 uint16_t ref_flow_handle;
33949 /* This value sets the match value for the ethertype. */
33950 uint16_t ethertype;
33951 /* valid when num tags is 1 or 2. */
33952 uint16_t outer_vlan_tci;
33953 /* This value sets the match value for the Destination MAC address. */
33955 /* valid when num tags is 2. */
33956 uint16_t inner_vlan_tci;
33957 /* This value sets the match value for the Source MAC address. */
33959 /* The bit length of destination IP address mask. */
33960 uint8_t ip_dst_mask_len;
33961 /* The bit length of source IP address mask. */
33962 uint8_t ip_src_mask_len;
33963 /* The value of destination IPv4/IPv6 address. */
33964 uint32_t ip_dst[4];
33965 /* The source IPv4/IPv6 address. */
33966 uint32_t ip_src[4];
33968 * The value of source port.
33969 * Applies to UDP and TCP traffic.
33971 uint16_t l4_src_port;
33973 * The value of source port mask.
33974 * Applies to UDP and TCP traffic.
33976 uint16_t l4_src_port_mask;
33978 * The value of destination port.
33979 * Applies to UDP and TCP traffic.
33981 uint16_t l4_dst_port;
33983 * The value of destination port mask.
33984 * Applies to UDP and TCP traffic.
33986 uint16_t l4_dst_port_mask;
33988 * NAT IPv4/6 address based on address type flag.
33989 * 0 values are ignored.
33991 uint32_t nat_ip_address[4];
33992 /* L2 header re-write Destination MAC address. */
33993 uint16_t l2_rewrite_dmac[3];
33995 * The NAT source/destination port based on direction flag.
33996 * Applies to UDP and TCP traffic.
33997 * 0 values are ignored.
34000 /* L2 header re-write Source MAC address. */
34001 uint16_t l2_rewrite_smac[3];
34002 /* The value of ip protocol. */
34005 uint8_t tunnel_type;
34007 #define HWRM_CFA_FLOW_ALLOC_INPUT_TUNNEL_TYPE_NONTUNNEL \
34009 /* Virtual eXtensible Local Area Network (VXLAN) */
34010 #define HWRM_CFA_FLOW_ALLOC_INPUT_TUNNEL_TYPE_VXLAN \
34012 /* Network Virtualization Generic Routing Encapsulation (NVGRE) */
34013 #define HWRM_CFA_FLOW_ALLOC_INPUT_TUNNEL_TYPE_NVGRE \
34015 /* Generic Routing Encapsulation (GRE) inside Ethernet payload */
34016 #define HWRM_CFA_FLOW_ALLOC_INPUT_TUNNEL_TYPE_L2GRE \
34019 #define HWRM_CFA_FLOW_ALLOC_INPUT_TUNNEL_TYPE_IPIP \
34021 /* Generic Network Virtualization Encapsulation (Geneve) */
34022 #define HWRM_CFA_FLOW_ALLOC_INPUT_TUNNEL_TYPE_GENEVE \
34024 /* Multi-Protocol Label Switching (MPLS) */
34025 #define HWRM_CFA_FLOW_ALLOC_INPUT_TUNNEL_TYPE_MPLS \
34027 /* Stateless Transport Tunnel (STT) */
34028 #define HWRM_CFA_FLOW_ALLOC_INPUT_TUNNEL_TYPE_STT \
34030 /* Generic Routing Encapsulation (GRE) inside IP datagram payload */
34031 #define HWRM_CFA_FLOW_ALLOC_INPUT_TUNNEL_TYPE_IPGRE \
34033 /* IPV4 over virtual eXtensible Local Area Network (IPV4oVXLAN) */
34034 #define HWRM_CFA_FLOW_ALLOC_INPUT_TUNNEL_TYPE_VXLAN_V4 \
34036 /* Enhance Generic Routing Encapsulation (GRE version 1) inside IP datagram payload */
34037 #define HWRM_CFA_FLOW_ALLOC_INPUT_TUNNEL_TYPE_IPGRE_V1 \
34039 /* Use fixed layer 2 ether type of 0xFFFF */
34040 #define HWRM_CFA_FLOW_ALLOC_INPUT_TUNNEL_TYPE_L2_ETYPE \
34042 /* IPV6 over virtual eXtensible Local Area Network with GPE header (IPV6oVXLANGPE) */
34043 #define HWRM_CFA_FLOW_ALLOC_INPUT_TUNNEL_TYPE_VXLAN_GPE_V6 \
34045 /* Any tunneled traffic */
34046 #define HWRM_CFA_FLOW_ALLOC_INPUT_TUNNEL_TYPE_ANYTUNNEL \
34048 #define HWRM_CFA_FLOW_ALLOC_INPUT_TUNNEL_TYPE_LAST \
34049 HWRM_CFA_FLOW_ALLOC_INPUT_TUNNEL_TYPE_ANYTUNNEL
34052 /* hwrm_cfa_flow_alloc_output (size:256b/32B) */
34053 struct hwrm_cfa_flow_alloc_output {
34054 /* The specific error status for the command. */
34055 uint16_t error_code;
34056 /* The HWRM command request type. */
34058 /* The sequence ID from the original command. */
34060 /* The length of the response data in number of bytes. */
34062 /* Flow record index. */
34063 uint16_t flow_handle;
34064 uint8_t unused_0[2];
34066 * The flow id value in bit 0-29 is the actual ID of the flow
34067 * associated with this filter and it shall be used to match
34068 * and associate the flow identifier returned in completion
34069 * records. A value of 0xFFFFFFFF in the 32-bit flow_id field
34070 * shall indicate no valid flow id.
34073 /* Indicate the flow id value. */
34074 #define HWRM_CFA_FLOW_ALLOC_OUTPUT_FLOW_ID_VALUE_MASK \
34075 UINT32_C(0x3fffffff)
34076 #define HWRM_CFA_FLOW_ALLOC_OUTPUT_FLOW_ID_VALUE_SFT 0
34077 /* Indicate type of the flow. */
34078 #define HWRM_CFA_FLOW_ALLOC_OUTPUT_FLOW_ID_TYPE \
34079 UINT32_C(0x40000000)
34081 * If this bit set to 0, then it indicates that the flow is
34084 #define HWRM_CFA_FLOW_ALLOC_OUTPUT_FLOW_ID_TYPE_INT \
34085 (UINT32_C(0x0) << 30)
34087 * If this bit is set to 1, then it indicates that the flow is
34090 #define HWRM_CFA_FLOW_ALLOC_OUTPUT_FLOW_ID_TYPE_EXT \
34091 (UINT32_C(0x1) << 30)
34092 #define HWRM_CFA_FLOW_ALLOC_OUTPUT_FLOW_ID_TYPE_LAST \
34093 HWRM_CFA_FLOW_ALLOC_OUTPUT_FLOW_ID_TYPE_EXT
34094 /* Indicate the flow direction. */
34095 #define HWRM_CFA_FLOW_ALLOC_OUTPUT_FLOW_ID_DIR \
34096 UINT32_C(0x80000000)
34097 /* If this bit set to 0, then it indicates rx flow. */
34098 #define HWRM_CFA_FLOW_ALLOC_OUTPUT_FLOW_ID_DIR_RX \
34099 (UINT32_C(0x0) << 31)
34100 /* If this bit is set to 1, then it indicates that tx flow. */
34101 #define HWRM_CFA_FLOW_ALLOC_OUTPUT_FLOW_ID_DIR_TX \
34102 (UINT32_C(0x1) << 31)
34103 #define HWRM_CFA_FLOW_ALLOC_OUTPUT_FLOW_ID_DIR_LAST \
34104 HWRM_CFA_FLOW_ALLOC_OUTPUT_FLOW_ID_DIR_TX
34105 /* This value identifies a set of CFA data structures used for a flow. */
34106 uint64_t ext_flow_handle;
34107 uint32_t flow_counter_id;
34108 uint8_t unused_1[3];
34110 * This field is used in Output records to indicate that the output
34111 * is completely written to RAM. This field should be read as '1'
34112 * to indicate that the output has been completely written.
34113 * When writing a command completion or response to an internal processor,
34114 * the order of writes has to be such that this field is written last.
34119 /* hwrm_cfa_flow_alloc_cmd_err (size:64b/8B) */
34120 struct hwrm_cfa_flow_alloc_cmd_err {
34122 * command specific error codes that goes to
34123 * the cmd_err field in Common HWRM Error Response.
34126 /* Unknown error */
34127 #define HWRM_CFA_FLOW_ALLOC_CMD_ERR_CODE_UNKNOWN UINT32_C(0x0)
34128 /* No more L2 Context TCAM */
34129 #define HWRM_CFA_FLOW_ALLOC_CMD_ERR_CODE_L2_CONTEXT_TCAM UINT32_C(0x1)
34130 /* No more action records */
34131 #define HWRM_CFA_FLOW_ALLOC_CMD_ERR_CODE_ACTION_RECORD UINT32_C(0x2)
34132 /* No more flow counters */
34133 #define HWRM_CFA_FLOW_ALLOC_CMD_ERR_CODE_FLOW_COUNTER UINT32_C(0x3)
34134 /* No more wild-card TCAM */
34135 #define HWRM_CFA_FLOW_ALLOC_CMD_ERR_CODE_WILD_CARD_TCAM UINT32_C(0x4)
34136 /* Hash collsion in exact match tables */
34137 #define HWRM_CFA_FLOW_ALLOC_CMD_ERR_CODE_HASH_COLLISION UINT32_C(0x5)
34138 /* Key is already installed */
34139 #define HWRM_CFA_FLOW_ALLOC_CMD_ERR_CODE_KEY_EXISTS UINT32_C(0x6)
34140 /* Flow Context DB is out of resource */
34141 #define HWRM_CFA_FLOW_ALLOC_CMD_ERR_CODE_FLOW_CTXT_DB UINT32_C(0x7)
34142 #define HWRM_CFA_FLOW_ALLOC_CMD_ERR_CODE_LAST \
34143 HWRM_CFA_FLOW_ALLOC_CMD_ERR_CODE_FLOW_CTXT_DB
34144 uint8_t unused_0[7];
34147 /**********************
34148 * hwrm_cfa_flow_free *
34149 **********************/
34152 /* hwrm_cfa_flow_free_input (size:256b/32B) */
34153 struct hwrm_cfa_flow_free_input {
34154 /* The HWRM command request type. */
34157 * The completion ring to send the completion event on. This should
34158 * be the NQ ID returned from the `nq_alloc` HWRM command.
34160 uint16_t cmpl_ring;
34162 * The sequence ID is used by the driver for tracking multiple
34163 * commands. This ID is treated as opaque data by the firmware and
34164 * the value is returned in the `hwrm_resp_hdr` upon completion.
34168 * The target ID of the command:
34169 * * 0x0-0xFFF8 - The function ID
34170 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
34171 * * 0xFFFD - Reserved for user-space HWRM interface
34174 uint16_t target_id;
34176 * A physical address pointer pointing to a host buffer that the
34177 * command's response data will be written. This can be either a host
34178 * physical address (HPA) or a guest physical address (GPA) and must
34179 * point to a physically contiguous block of memory.
34181 uint64_t resp_addr;
34182 /* Flow record index. */
34183 uint16_t flow_handle;
34185 /* Flow counter id to be freed. */
34186 uint32_t flow_counter_id;
34187 /* This value identifies a set of CFA data structures used for a flow. */
34188 uint64_t ext_flow_handle;
34191 /* hwrm_cfa_flow_free_output (size:256b/32B) */
34192 struct hwrm_cfa_flow_free_output {
34193 /* The specific error status for the command. */
34194 uint16_t error_code;
34195 /* The HWRM command request type. */
34197 /* The sequence ID from the original command. */
34199 /* The length of the response data in number of bytes. */
34201 /* packet is 64 b */
34205 uint8_t unused_0[7];
34207 * This field is used in Output records to indicate that the output
34208 * is completely written to RAM. This field should be read as '1'
34209 * to indicate that the output has been completely written.
34210 * When writing a command completion or response to an internal processor,
34211 * the order of writes has to be such that this field is written last.
34216 /* hwrm_cfa_flow_action_data (size:960b/120B) */
34217 struct hwrm_cfa_flow_action_data {
34218 uint16_t action_flags;
34219 /* Setting of this flag indicates accept action. */
34220 #define HWRM_CFA_FLOW_ACTION_DATA_ACTION_FLAGS_FWD \
34222 /* Setting of this flag indicates recycle action. */
34223 #define HWRM_CFA_FLOW_ACTION_DATA_ACTION_FLAGS_RECYCLE \
34225 /* Setting of this flag indicates drop action. */
34226 #define HWRM_CFA_FLOW_ACTION_DATA_ACTION_FLAGS_DROP \
34228 /* Setting of this flag indicates meter action. */
34229 #define HWRM_CFA_FLOW_ACTION_DATA_ACTION_FLAGS_METER \
34231 /* Setting of this flag indicates tunnel action. */
34232 #define HWRM_CFA_FLOW_ACTION_DATA_ACTION_FLAGS_TUNNEL \
34235 * If set to 1 and flow direction is TX, it indicates decap of L2 header
34236 * and encap of tunnel header. If set to 1 and flow direction is RX, it
34237 * indicates decap of tunnel header and encap L2 header.
34239 #define HWRM_CFA_FLOW_ACTION_DATA_ACTION_FLAGS_TUNNEL_IP \
34241 /* Setting of this flag indicates ttl decrement action. */
34242 #define HWRM_CFA_FLOW_ACTION_DATA_ACTION_FLAGS_TTL_DECREMENT \
34244 /* If set to 1, flow aging is enabled for this flow. */
34245 #define HWRM_CFA_FLOW_ACTION_DATA_ACTION_FLAGS_FLOW_AGING_ENABLED \
34247 /* Setting of this flag indicates encap action. */
34248 #define HWRM_CFA_FLOW_ACTION_DATA_ACTION_FLAGS_ENCAP \
34250 /* Setting of this flag indicates decap action. */
34251 #define HWRM_CFA_FLOW_ACTION_DATA_ACTION_FLAGS_DECAP \
34254 uint16_t act_meter_id;
34257 /* vport number. */
34259 /* The NAT source/destination. */
34261 uint16_t unused_0[3];
34262 /* NAT IPv4/IPv6 address. */
34263 uint32_t nat_ip_address[4];
34264 /* Encapsulation Type. */
34265 uint8_t encap_type;
34266 /* Virtual eXtensible Local Area Network (VXLAN) */
34267 #define HWRM_CFA_FLOW_ACTION_DATA_ENCAP_TYPE_VXLAN UINT32_C(0x1)
34268 /* Network Virtualization Generic Routing Encapsulation (NVGRE) */
34269 #define HWRM_CFA_FLOW_ACTION_DATA_ENCAP_TYPE_NVGRE UINT32_C(0x2)
34270 /* Generic Routing Encapsulation (GRE) after inside Ethernet payload */
34271 #define HWRM_CFA_FLOW_ACTION_DATA_ENCAP_TYPE_L2GRE UINT32_C(0x3)
34273 #define HWRM_CFA_FLOW_ACTION_DATA_ENCAP_TYPE_IPIP UINT32_C(0x4)
34274 /* Generic Network Virtualization Encapsulation (Geneve) */
34275 #define HWRM_CFA_FLOW_ACTION_DATA_ENCAP_TYPE_GENEVE UINT32_C(0x5)
34276 /* Multi-Protocol Label Switching (MPLS) */
34277 #define HWRM_CFA_FLOW_ACTION_DATA_ENCAP_TYPE_MPLS UINT32_C(0x6)
34279 #define HWRM_CFA_FLOW_ACTION_DATA_ENCAP_TYPE_VLAN UINT32_C(0x7)
34280 /* Generic Routing Encapsulation (GRE) inside IP datagram payload */
34281 #define HWRM_CFA_FLOW_ACTION_DATA_ENCAP_TYPE_IPGRE UINT32_C(0x8)
34282 /* IPV4 over virtual eXtensible Local Area Network (IPV4oVXLAN) */
34283 #define HWRM_CFA_FLOW_ACTION_DATA_ENCAP_TYPE_VXLAN_V4 UINT32_C(0x9)
34284 /* Enhance Generic Routing Encapsulation (GRE version 1) inside IP datagram payload */
34285 #define HWRM_CFA_FLOW_ACTION_DATA_ENCAP_TYPE_IPGRE_V1 UINT32_C(0xa)
34286 /* Use fixed layer 2 ether type of 0xFFFF */
34287 #define HWRM_CFA_FLOW_ACTION_DATA_ENCAP_TYPE_L2_ETYPE UINT32_C(0xb)
34288 /* IPV6 over virtual eXtensible Local Area Network with GPE header (IPV6oVXLANGPE) */
34289 #define HWRM_CFA_FLOW_ACTION_DATA_ENCAP_TYPE_VXLAN_GPE_V6 UINT32_C(0xc)
34290 #define HWRM_CFA_FLOW_ACTION_DATA_ENCAP_TYPE_LAST \
34291 HWRM_CFA_FLOW_ACTION_DATA_ENCAP_TYPE_VXLAN_GPE_V6
34293 /* This value is encap data for the associated encap type. */
34294 uint32_t encap_data[20];
34297 /* hwrm_cfa_flow_tunnel_hdr_data (size:64b/8B) */
34298 struct hwrm_cfa_flow_tunnel_hdr_data {
34300 uint8_t tunnel_type;
34302 #define HWRM_CFA_FLOW_TUNNEL_HDR_DATA_TUNNEL_TYPE_NONTUNNEL \
34304 /* Virtual eXtensible Local Area Network (VXLAN) */
34305 #define HWRM_CFA_FLOW_TUNNEL_HDR_DATA_TUNNEL_TYPE_VXLAN \
34307 /* Network Virtualization Generic Routing Encapsulation (NVGRE) */
34308 #define HWRM_CFA_FLOW_TUNNEL_HDR_DATA_TUNNEL_TYPE_NVGRE \
34310 /* Generic Routing Encapsulation (GRE) inside Ethernet payload */
34311 #define HWRM_CFA_FLOW_TUNNEL_HDR_DATA_TUNNEL_TYPE_L2GRE \
34314 #define HWRM_CFA_FLOW_TUNNEL_HDR_DATA_TUNNEL_TYPE_IPIP \
34316 /* Generic Network Virtualization Encapsulation (Geneve) */
34317 #define HWRM_CFA_FLOW_TUNNEL_HDR_DATA_TUNNEL_TYPE_GENEVE \
34319 /* Multi-Protocol Label Switching (MPLS) */
34320 #define HWRM_CFA_FLOW_TUNNEL_HDR_DATA_TUNNEL_TYPE_MPLS \
34322 /* Stateless Transport Tunnel (STT) */
34323 #define HWRM_CFA_FLOW_TUNNEL_HDR_DATA_TUNNEL_TYPE_STT \
34325 /* Generic Routing Encapsulation (GRE) inside IP datagram payload */
34326 #define HWRM_CFA_FLOW_TUNNEL_HDR_DATA_TUNNEL_TYPE_IPGRE \
34328 /* IPV4 over virtual eXtensible Local Area Network (IPV4oVXLAN) */
34329 #define HWRM_CFA_FLOW_TUNNEL_HDR_DATA_TUNNEL_TYPE_VXLAN_V4 \
34331 /* Enhance Generic Routing Encapsulation (GRE version 1) inside IP datagram payload */
34332 #define HWRM_CFA_FLOW_TUNNEL_HDR_DATA_TUNNEL_TYPE_IPGRE_V1 \
34334 /* Use fixed layer 2 ether type of 0xFFFF */
34335 #define HWRM_CFA_FLOW_TUNNEL_HDR_DATA_TUNNEL_TYPE_L2_ETYPE \
34337 /* IPV6 over virtual eXtensible Local Area Network with GPE header (IPV6oVXLANGPE) */
34338 #define HWRM_CFA_FLOW_TUNNEL_HDR_DATA_TUNNEL_TYPE_VXLAN_GPE_V6 \
34340 /* Any tunneled traffic */
34341 #define HWRM_CFA_FLOW_TUNNEL_HDR_DATA_TUNNEL_TYPE_ANYTUNNEL \
34343 #define HWRM_CFA_FLOW_TUNNEL_HDR_DATA_TUNNEL_TYPE_LAST \
34344 HWRM_CFA_FLOW_TUNNEL_HDR_DATA_TUNNEL_TYPE_ANYTUNNEL
34347 * Tunnel identifier.
34348 * Virtual Network Identifier (VNI).
34350 uint32_t tunnel_id;
34353 /* hwrm_cfa_flow_l4_key_data (size:64b/8B) */
34354 struct hwrm_cfa_flow_l4_key_data {
34355 /* The value of source port. */
34356 uint16_t l4_src_port;
34357 /* The value of destination port. */
34358 uint16_t l4_dst_port;
34362 /* hwrm_cfa_flow_l3_key_data (size:512b/64B) */
34363 struct hwrm_cfa_flow_l3_key_data {
34364 /* The value of ip protocol. */
34365 uint8_t ip_protocol;
34366 uint8_t unused_0[7];
34367 /* The value of destination IPv4/IPv6 address. */
34368 uint32_t ip_dst[4];
34369 /* The source IPv4/IPv6 address. */
34370 uint32_t ip_src[4];
34371 /* NAT IPv4/IPv6 address. */
34372 uint32_t nat_ip_address[4];
34373 uint32_t unused[2];
34376 /* hwrm_cfa_flow_l2_key_data (size:448b/56B) */
34377 struct hwrm_cfa_flow_l2_key_data {
34378 /* Destination MAC address. */
34381 /* Source MAC address. */
34384 /* L2 header re-write Destination MAC address. */
34385 uint16_t l2_rewrite_dmac[3];
34387 /* L2 header re-write Source MAC address. */
34388 uint16_t l2_rewrite_smac[3];
34390 uint16_t ethertype;
34391 /* Number of VLAN tags. */
34392 uint16_t num_vlan_tags;
34394 uint16_t l2_rewrite_vlan_tpid;
34396 uint16_t l2_rewrite_vlan_tci;
34397 uint8_t unused_3[2];
34398 /* Outer VLAN TPID. */
34399 uint16_t ovlan_tpid;
34400 /* Outer VLAN TCI. */
34401 uint16_t ovlan_tci;
34402 /* Inner VLAN TPID. */
34403 uint16_t ivlan_tpid;
34404 /* Inner VLAN TCI. */
34405 uint16_t ivlan_tci;
34409 /* hwrm_cfa_flow_key_data (size:4160b/520B) */
34410 struct hwrm_cfa_flow_key_data {
34411 /* Flow associated tunnel L2 header key info. */
34412 uint32_t t_l2_key_data[14];
34413 /* Flow associated tunnel L2 header mask info. */
34414 uint32_t t_l2_key_mask[14];
34415 /* Flow associated tunnel L3 header key info. */
34416 uint32_t t_l3_key_data[16];
34417 /* Flow associated tunnel L3 header mask info. */
34418 uint32_t t_l3_key_mask[16];
34419 /* Flow associated tunnel L4 header key info. */
34420 uint32_t t_l4_key_data[2];
34421 /* Flow associated tunnel L4 header mask info. */
34422 uint32_t t_l4_key_mask[2];
34423 /* Flow associated tunnel header info. */
34424 uint32_t tunnel_hdr[2];
34425 /* Flow associated L2 header key info. */
34426 uint32_t l2_key_data[14];
34427 /* Flow associated L2 header mask info. */
34428 uint32_t l2_key_mask[14];
34429 /* Flow associated L3 header key info. */
34430 uint32_t l3_key_data[16];
34431 /* Flow associated L3 header mask info. */
34432 uint32_t l3_key_mask[16];
34433 /* Flow associated L4 header key info. */
34434 uint32_t l4_key_data[2];
34435 /* Flow associated L4 header mask info. */
34436 uint32_t l4_key_mask[2];
34439 /**********************
34440 * hwrm_cfa_flow_info *
34441 **********************/
34444 /* hwrm_cfa_flow_info_input (size:256b/32B) */
34445 struct hwrm_cfa_flow_info_input {
34446 /* The HWRM command request type. */
34449 * The completion ring to send the completion event on. This should
34450 * be the NQ ID returned from the `nq_alloc` HWRM command.
34452 uint16_t cmpl_ring;
34454 * The sequence ID is used by the driver for tracking multiple
34455 * commands. This ID is treated as opaque data by the firmware and
34456 * the value is returned in the `hwrm_resp_hdr` upon completion.
34460 * The target ID of the command:
34461 * * 0x0-0xFFF8 - The function ID
34462 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
34463 * * 0xFFFD - Reserved for user-space HWRM interface
34466 uint16_t target_id;
34468 * A physical address pointer pointing to a host buffer that the
34469 * command's response data will be written. This can be either a host
34470 * physical address (HPA) or a guest physical address (GPA) and must
34471 * point to a physically contiguous block of memory.
34473 uint64_t resp_addr;
34474 /* Flow record index. */
34475 uint16_t flow_handle;
34476 /* Max flow handle */
34477 #define HWRM_CFA_FLOW_INFO_INPUT_FLOW_HANDLE_MAX_MASK \
34479 #define HWRM_CFA_FLOW_INFO_INPUT_FLOW_HANDLE_MAX_SFT 0
34480 /* CNP flow handle */
34481 #define HWRM_CFA_FLOW_INFO_INPUT_FLOW_HANDLE_CNP_CNT \
34483 /* RoCEv1 flow handle */
34484 #define HWRM_CFA_FLOW_INFO_INPUT_FLOW_HANDLE_ROCEV1_CNT \
34486 /* RoCEv2 flow handle */
34487 #define HWRM_CFA_FLOW_INFO_INPUT_FLOW_HANDLE_ROCEV2_CNT \
34489 /* Direction rx = 1 */
34490 #define HWRM_CFA_FLOW_INFO_INPUT_FLOW_HANDLE_DIR_RX \
34492 uint8_t unused_0[6];
34493 /* This value identifies a set of CFA data structures used for a flow. */
34494 uint64_t ext_flow_handle;
34497 /* hwrm_cfa_flow_info_output (size:5632b/704B) */
34498 struct hwrm_cfa_flow_info_output {
34499 /* The specific error status for the command. */
34500 uint16_t error_code;
34501 /* The HWRM command request type. */
34503 /* The sequence ID from the original command. */
34505 /* The length of the response data in number of bytes. */
34508 /* When set to 1, indicates the configuration is the TX flow. */
34509 #define HWRM_CFA_FLOW_INFO_OUTPUT_FLAGS_PATH_TX UINT32_C(0x1)
34510 /* When set to 1, indicates the configuration is the RX flow. */
34511 #define HWRM_CFA_FLOW_INFO_OUTPUT_FLAGS_PATH_RX UINT32_C(0x2)
34512 /* profile is 8 b */
34514 /* src_fid is 16 b */
34516 /* dst_fid is 16 b */
34518 /* l2_ctxt_id is 16 b */
34519 uint16_t l2_ctxt_id;
34520 /* em_info is 64 b */
34522 /* tcam_info is 64 b */
34523 uint64_t tcam_info;
34524 /* vfp_tcam_info is 64 b */
34525 uint64_t vfp_tcam_info;
34526 /* ar_id is 16 b */
34528 /* flow_handle is 16 b */
34529 uint16_t flow_handle;
34530 /* tunnel_handle is 32 b */
34531 uint32_t tunnel_handle;
34532 /* The flow aging timer for the flow, the unit is 100 milliseconds */
34533 uint16_t flow_timer;
34534 uint8_t unused_0[6];
34535 /* Flow associated L2, L3 and L4 headers info. */
34536 uint32_t flow_key_data[130];
34537 /* Flow associated action record info. */
34538 uint32_t flow_action_info[30];
34539 uint8_t unused_1[7];
34541 * This field is used in Output records to indicate that the output
34542 * is completely written to RAM. This field should be read as '1'
34543 * to indicate that the output has been completely written.
34544 * When writing a command completion or response to an internal processor,
34545 * the order of writes has to be such that this field is written last.
34550 /***********************
34551 * hwrm_cfa_flow_flush *
34552 ***********************/
34555 /* hwrm_cfa_flow_flush_input (size:256b/32B) */
34556 struct hwrm_cfa_flow_flush_input {
34557 /* The HWRM command request type. */
34560 * The completion ring to send the completion event on. This should
34561 * be the NQ ID returned from the `nq_alloc` HWRM command.
34563 uint16_t cmpl_ring;
34565 * The sequence ID is used by the driver for tracking multiple
34566 * commands. This ID is treated as opaque data by the firmware and
34567 * the value is returned in the `hwrm_resp_hdr` upon completion.
34571 * The target ID of the command:
34572 * * 0x0-0xFFF8 - The function ID
34573 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
34574 * * 0xFFFD - Reserved for user-space HWRM interface
34577 uint16_t target_id;
34579 * A physical address pointer pointing to a host buffer that the
34580 * command's response data will be written. This can be either a host
34581 * physical address (HPA) or a guest physical address (GPA) and must
34582 * point to a physically contiguous block of memory.
34584 uint64_t resp_addr;
34585 /* flags is 32 b */
34588 * Set to 1 to indicate the page size, page layers, and flow_handle_table_dma_addr
34589 * fields are valid. The flow flush operation should only flush the flows from the
34590 * flow table specified. This flag is set to 0 by older driver. For older firmware,
34591 * setting this flag has no effect.
34593 #define HWRM_CFA_FLOW_FLUSH_INPUT_FLAGS_FLOW_TABLE_VALID \
34596 * Set to 1 to indicate flow flush operation to cleanup all the flows, meters, CFA
34597 * context memory tables etc. This flag is set to 0 by older driver. For older firmware,
34598 * setting this flag has no effect.
34600 #define HWRM_CFA_FLOW_FLUSH_INPUT_FLAGS_FLOW_RESET_ALL \
34603 * Set to 1 to indicate flow flush operation to cleanup all the flows by the caller.
34604 * This flag is set to 0 by older driver. For older firmware, setting this flag has no effect.
34606 #define HWRM_CFA_FLOW_FLUSH_INPUT_FLAGS_FLOW_RESET_PORT \
34608 /* Set to 1 to indicate the flow counter IDs are included in the flow table. */
34609 #define HWRM_CFA_FLOW_FLUSH_INPUT_FLAGS_FLOW_HANDLE_INCL_FC \
34610 UINT32_C(0x8000000)
34612 * This specifies the size of flow handle entries provided by the driver
34613 * in the flow table specified below. Only two flow handle size enums are defined.
34615 #define HWRM_CFA_FLOW_FLUSH_INPUT_FLAGS_FLOW_HANDLE_ENTRY_SIZE_MASK \
34616 UINT32_C(0xc0000000)
34617 #define HWRM_CFA_FLOW_FLUSH_INPUT_FLAGS_FLOW_HANDLE_ENTRY_SIZE_SFT \
34619 /* The flow handle is 16bit */
34620 #define HWRM_CFA_FLOW_FLUSH_INPUT_FLAGS_FLOW_HANDLE_ENTRY_SIZE_FLOW_HND_16BIT \
34621 (UINT32_C(0x0) << 30)
34622 /* The flow handle is 64bit */
34623 #define HWRM_CFA_FLOW_FLUSH_INPUT_FLAGS_FLOW_HANDLE_ENTRY_SIZE_FLOW_HND_64BIT \
34624 (UINT32_C(0x1) << 30)
34625 #define HWRM_CFA_FLOW_FLUSH_INPUT_FLAGS_FLOW_HANDLE_ENTRY_SIZE_LAST \
34626 HWRM_CFA_FLOW_FLUSH_INPUT_FLAGS_FLOW_HANDLE_ENTRY_SIZE_FLOW_HND_64BIT
34627 /* Specify page size of the flow table memory. */
34629 /* The page size is 4K */
34630 #define HWRM_CFA_FLOW_FLUSH_INPUT_PAGE_SIZE_4K UINT32_C(0x0)
34631 /* The page size is 8K */
34632 #define HWRM_CFA_FLOW_FLUSH_INPUT_PAGE_SIZE_8K UINT32_C(0x1)
34633 /* The page size is 64K */
34634 #define HWRM_CFA_FLOW_FLUSH_INPUT_PAGE_SIZE_64K UINT32_C(0x4)
34635 /* The page size is 256K */
34636 #define HWRM_CFA_FLOW_FLUSH_INPUT_PAGE_SIZE_256K UINT32_C(0x6)
34637 /* The page size is 1M */
34638 #define HWRM_CFA_FLOW_FLUSH_INPUT_PAGE_SIZE_1M UINT32_C(0x8)
34639 /* The page size is 2M */
34640 #define HWRM_CFA_FLOW_FLUSH_INPUT_PAGE_SIZE_2M UINT32_C(0x9)
34641 /* The page size is 4M */
34642 #define HWRM_CFA_FLOW_FLUSH_INPUT_PAGE_SIZE_4M UINT32_C(0xa)
34643 /* The page size is 1G */
34644 #define HWRM_CFA_FLOW_FLUSH_INPUT_PAGE_SIZE_1G UINT32_C(0x12)
34645 #define HWRM_CFA_FLOW_FLUSH_INPUT_PAGE_SIZE_LAST \
34646 HWRM_CFA_FLOW_FLUSH_INPUT_PAGE_SIZE_1G
34647 /* FLow table memory indirect levels. */
34648 uint8_t page_level;
34649 /* PBL pointer is physical start address. */
34650 #define HWRM_CFA_FLOW_FLUSH_INPUT_PAGE_LEVEL_LVL_0 UINT32_C(0x0)
34651 /* PBL pointer points to PTE table. */
34652 #define HWRM_CFA_FLOW_FLUSH_INPUT_PAGE_LEVEL_LVL_1 UINT32_C(0x1)
34653 /* PBL pointer points to PDE table with each entry pointing to PTE tables. */
34654 #define HWRM_CFA_FLOW_FLUSH_INPUT_PAGE_LEVEL_LVL_2 UINT32_C(0x2)
34655 #define HWRM_CFA_FLOW_FLUSH_INPUT_PAGE_LEVEL_LAST \
34656 HWRM_CFA_FLOW_FLUSH_INPUT_PAGE_LEVEL_LVL_2
34657 /* number of flows in the flow table */
34658 uint16_t num_flows;
34659 /* Pointer to the PBL, or PDL depending on number of levels */
34663 /* hwrm_cfa_flow_flush_output (size:128b/16B) */
34664 struct hwrm_cfa_flow_flush_output {
34665 /* The specific error status for the command. */
34666 uint16_t error_code;
34667 /* The HWRM command request type. */
34669 /* The sequence ID from the original command. */
34671 /* The length of the response data in number of bytes. */
34673 uint8_t unused_0[7];
34675 * This field is used in Output records to indicate that the output
34676 * is completely written to RAM. This field should be read as '1'
34677 * to indicate that the output has been completely written.
34678 * When writing a command completion or response to an internal processor,
34679 * the order of writes has to be such that this field is written last.
34684 /***********************
34685 * hwrm_cfa_flow_stats *
34686 ***********************/
34689 /* hwrm_cfa_flow_stats_input (size:640b/80B) */
34690 struct hwrm_cfa_flow_stats_input {
34691 /* The HWRM command request type. */
34694 * The completion ring to send the completion event on. This should
34695 * be the NQ ID returned from the `nq_alloc` HWRM command.
34697 uint16_t cmpl_ring;
34699 * The sequence ID is used by the driver for tracking multiple
34700 * commands. This ID is treated as opaque data by the firmware and
34701 * the value is returned in the `hwrm_resp_hdr` upon completion.
34705 * The target ID of the command:
34706 * * 0x0-0xFFF8 - The function ID
34707 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
34708 * * 0xFFFD - Reserved for user-space HWRM interface
34711 uint16_t target_id;
34713 * A physical address pointer pointing to a host buffer that the
34714 * command's response data will be written. This can be either a host
34715 * physical address (HPA) or a guest physical address (GPA) and must
34716 * point to a physically contiguous block of memory.
34718 uint64_t resp_addr;
34720 uint16_t num_flows;
34722 uint16_t flow_handle_0;
34724 uint16_t flow_handle_1;
34726 uint16_t flow_handle_2;
34728 uint16_t flow_handle_3;
34730 uint16_t flow_handle_4;
34732 uint16_t flow_handle_5;
34734 uint16_t flow_handle_6;
34736 uint16_t flow_handle_7;
34738 uint16_t flow_handle_8;
34740 uint16_t flow_handle_9;
34741 uint8_t unused_0[2];
34742 /* Flow ID of a flow. */
34743 uint32_t flow_id_0;
34744 /* Flow ID of a flow. */
34745 uint32_t flow_id_1;
34746 /* Flow ID of a flow. */
34747 uint32_t flow_id_2;
34748 /* Flow ID of a flow. */
34749 uint32_t flow_id_3;
34750 /* Flow ID of a flow. */
34751 uint32_t flow_id_4;
34752 /* Flow ID of a flow. */
34753 uint32_t flow_id_5;
34754 /* Flow ID of a flow. */
34755 uint32_t flow_id_6;
34756 /* Flow ID of a flow. */
34757 uint32_t flow_id_7;
34758 /* Flow ID of a flow. */
34759 uint32_t flow_id_8;
34760 /* Flow ID of a flow. */
34761 uint32_t flow_id_9;
34764 /* hwrm_cfa_flow_stats_output (size:1408b/176B) */
34765 struct hwrm_cfa_flow_stats_output {
34766 /* The specific error status for the command. */
34767 uint16_t error_code;
34768 /* The HWRM command request type. */
34770 /* The sequence ID from the original command. */
34772 /* The length of the response data in number of bytes. */
34774 /* packet_0 is 64 b */
34776 /* packet_1 is 64 b */
34778 /* packet_2 is 64 b */
34780 /* packet_3 is 64 b */
34782 /* packet_4 is 64 b */
34784 /* packet_5 is 64 b */
34786 /* packet_6 is 64 b */
34788 /* packet_7 is 64 b */
34790 /* packet_8 is 64 b */
34792 /* packet_9 is 64 b */
34794 /* byte_0 is 64 b */
34796 /* byte_1 is 64 b */
34798 /* byte_2 is 64 b */
34800 /* byte_3 is 64 b */
34802 /* byte_4 is 64 b */
34804 /* byte_5 is 64 b */
34806 /* byte_6 is 64 b */
34808 /* byte_7 is 64 b */
34810 /* byte_8 is 64 b */
34812 /* byte_9 is 64 b */
34814 uint8_t unused_0[7];
34816 * This field is used in Output records to indicate that the output
34817 * is completely written to RAM. This field should be read as '1'
34818 * to indicate that the output has been completely written.
34819 * When writing a command completion or response to an internal processor,
34820 * the order of writes has to be such that this field is written last.
34825 /***********************************
34826 * hwrm_cfa_flow_aging_timer_reset *
34827 ***********************************/
34830 /* hwrm_cfa_flow_aging_timer_reset_input (size:256b/32B) */
34831 struct hwrm_cfa_flow_aging_timer_reset_input {
34832 /* The HWRM command request type. */
34835 * The completion ring to send the completion event on. This should
34836 * be the NQ ID returned from the `nq_alloc` HWRM command.
34838 uint16_t cmpl_ring;
34840 * The sequence ID is used by the driver for tracking multiple
34841 * commands. This ID is treated as opaque data by the firmware and
34842 * the value is returned in the `hwrm_resp_hdr` upon completion.
34846 * The target ID of the command:
34847 * * 0x0-0xFFF8 - The function ID
34848 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
34849 * * 0xFFFD - Reserved for user-space HWRM interface
34852 uint16_t target_id;
34854 * A physical address pointer pointing to a host buffer that the
34855 * command's response data will be written. This can be either a host
34856 * physical address (HPA) or a guest physical address (GPA) and must
34857 * point to a physically contiguous block of memory.
34859 uint64_t resp_addr;
34860 /* Flow record index. */
34861 uint16_t flow_handle;
34862 uint8_t unused_0[2];
34864 * New flow timer value for the flow specified in the ext_flow_handle.
34865 * The flow timer unit is 100ms.
34867 uint32_t flow_timer;
34868 /* This value identifies a set of CFA data structures used for a flow. */
34869 uint64_t ext_flow_handle;
34872 /* hwrm_cfa_flow_aging_timer_reset_output (size:128b/16B) */
34873 struct hwrm_cfa_flow_aging_timer_reset_output {
34874 /* The specific error status for the command. */
34875 uint16_t error_code;
34876 /* The HWRM command request type. */
34878 /* The sequence ID from the original command. */
34880 /* The length of the response data in number of bytes. */
34882 uint8_t unused_0[7];
34884 * This field is used in Output records to indicate that the output
34885 * is completely written to RAM. This field should be read as '1'
34886 * to indicate that the output has been completely written.
34887 * When writing a command completion or response to an internal processor,
34888 * the order of writes has to be such that this field is written last.
34893 /***************************
34894 * hwrm_cfa_flow_aging_cfg *
34895 ***************************/
34898 /* hwrm_cfa_flow_aging_cfg_input (size:384b/48B) */
34899 struct hwrm_cfa_flow_aging_cfg_input {
34900 /* The HWRM command request type. */
34903 * The completion ring to send the completion event on. This should
34904 * be the NQ ID returned from the `nq_alloc` HWRM command.
34906 uint16_t cmpl_ring;
34908 * The sequence ID is used by the driver for tracking multiple
34909 * commands. This ID is treated as opaque data by the firmware and
34910 * the value is returned in the `hwrm_resp_hdr` upon completion.
34914 * The target ID of the command:
34915 * * 0x0-0xFFF8 - The function ID
34916 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
34917 * * 0xFFFD - Reserved for user-space HWRM interface
34920 uint16_t target_id;
34922 * A physical address pointer pointing to a host buffer that the
34923 * command's response data will be written. This can be either a host
34924 * physical address (HPA) or a guest physical address (GPA) and must
34925 * point to a physically contiguous block of memory.
34927 uint64_t resp_addr;
34928 /* The bit field to enable per flow aging configuration. */
34930 /* This bit must be '1' for the tcp flow timer field to be configured */
34931 #define HWRM_CFA_FLOW_AGING_CFG_INPUT_ENABLES_TCP_FLOW_TIMER \
34933 /* This bit must be '1' for the tcp finish timer field to be configured */
34934 #define HWRM_CFA_FLOW_AGING_CFG_INPUT_ENABLES_TCP_FIN_TIMER \
34936 /* This bit must be '1' for the udp flow timer field to be configured */
34937 #define HWRM_CFA_FLOW_AGING_CFG_INPUT_ENABLES_UDP_FLOW_TIMER \
34939 /* This bit must be '1' for the eem dma interval field to be configured */
34940 #define HWRM_CFA_FLOW_AGING_CFG_INPUT_ENABLES_EEM_DMA_INTERVAL \
34942 /* This bit must be '1' for the eem notice interval field to be configured */
34943 #define HWRM_CFA_FLOW_AGING_CFG_INPUT_ENABLES_EEM_NOTICE_INTERVAL \
34945 /* This bit must be '1' for the eem context memory maximum entries field to be configured */
34946 #define HWRM_CFA_FLOW_AGING_CFG_INPUT_ENABLES_EEM_CTX_MAX_ENTRIES \
34948 /* This bit must be '1' for the eem context memory ID field to be configured */
34949 #define HWRM_CFA_FLOW_AGING_CFG_INPUT_ENABLES_EEM_CTX_ID \
34951 /* This bit must be '1' for the eem context memory type field to be configured */
34952 #define HWRM_CFA_FLOW_AGING_CFG_INPUT_ENABLES_EEM_CTX_MEM_TYPE \
34955 /* Enumeration denoting the RX, TX type of the resource. */
34956 #define HWRM_CFA_FLOW_AGING_CFG_INPUT_FLAGS_PATH UINT32_C(0x1)
34958 #define HWRM_CFA_FLOW_AGING_CFG_INPUT_FLAGS_PATH_TX UINT32_C(0x0)
34960 #define HWRM_CFA_FLOW_AGING_CFG_INPUT_FLAGS_PATH_RX UINT32_C(0x1)
34961 #define HWRM_CFA_FLOW_AGING_CFG_INPUT_FLAGS_PATH_LAST \
34962 HWRM_CFA_FLOW_AGING_CFG_INPUT_FLAGS_PATH_RX
34963 /* Enumeration denoting the enable, disable eem flow aging configuration. */
34964 #define HWRM_CFA_FLOW_AGING_CFG_INPUT_FLAGS_EEM UINT32_C(0x2)
34966 #define HWRM_CFA_FLOW_AGING_CFG_INPUT_FLAGS_EEM_DISABLE \
34967 (UINT32_C(0x0) << 1)
34969 #define HWRM_CFA_FLOW_AGING_CFG_INPUT_FLAGS_EEM_ENABLE \
34970 (UINT32_C(0x1) << 1)
34971 #define HWRM_CFA_FLOW_AGING_CFG_INPUT_FLAGS_EEM_LAST \
34972 HWRM_CFA_FLOW_AGING_CFG_INPUT_FLAGS_EEM_ENABLE
34974 /* The flow aging timer for all TCP flows, the unit is 100 milliseconds. */
34975 uint32_t tcp_flow_timer;
34976 /* The TCP finished timer for all TCP flows, the unit is 100 milliseconds. */
34977 uint32_t tcp_fin_timer;
34978 /* The flow aging timer for all UDP flows, the unit is 100 milliseconds. */
34979 uint32_t udp_flow_timer;
34980 /* The interval to dma eem ejection data to host memory, the unit is milliseconds. */
34981 uint16_t eem_dma_interval;
34982 /* The interval to notify driver to read the eem ejection data, the unit is milliseconds. */
34983 uint16_t eem_notice_interval;
34984 /* The maximum entries number in the eem context memory. */
34985 uint32_t eem_ctx_max_entries;
34986 /* The context memory ID for eem flow aging. */
34987 uint16_t eem_ctx_id;
34988 uint16_t eem_ctx_mem_type;
34989 /* The content of context memory is eem ejection data, the size of each entry is 4 bytes. */
34990 #define HWRM_CFA_FLOW_AGING_CFG_INPUT_EEM_CTX_MEM_TYPE_EJECTION_DATA \
34992 #define HWRM_CFA_FLOW_AGING_CFG_INPUT_EEM_CTX_MEM_TYPE_LAST \
34993 HWRM_CFA_FLOW_AGING_CFG_INPUT_EEM_CTX_MEM_TYPE_EJECTION_DATA
34994 uint8_t unused_1[4];
34997 /* hwrm_cfa_flow_aging_cfg_output (size:128b/16B) */
34998 struct hwrm_cfa_flow_aging_cfg_output {
34999 /* The specific error status for the command. */
35000 uint16_t error_code;
35001 /* The HWRM command request type. */
35003 /* The sequence ID from the original command. */
35005 /* The length of the response data in number of bytes. */
35007 uint8_t unused_0[7];
35009 * This field is used in Output records to indicate that the output
35010 * is completely written to RAM. This field should be read as '1'
35011 * to indicate that the output has been completely written.
35012 * When writing a command completion or response to an internal processor,
35013 * the order of writes has to be such that this field is written last.
35018 /****************************
35019 * hwrm_cfa_flow_aging_qcfg *
35020 ****************************/
35023 /* hwrm_cfa_flow_aging_qcfg_input (size:192b/24B) */
35024 struct hwrm_cfa_flow_aging_qcfg_input {
35025 /* The HWRM command request type. */
35028 * The completion ring to send the completion event on. This should
35029 * be the NQ ID returned from the `nq_alloc` HWRM command.
35031 uint16_t cmpl_ring;
35033 * The sequence ID is used by the driver for tracking multiple
35034 * commands. This ID is treated as opaque data by the firmware and
35035 * the value is returned in the `hwrm_resp_hdr` upon completion.
35039 * The target ID of the command:
35040 * * 0x0-0xFFF8 - The function ID
35041 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
35042 * * 0xFFFD - Reserved for user-space HWRM interface
35045 uint16_t target_id;
35047 * A physical address pointer pointing to a host buffer that the
35048 * command's response data will be written. This can be either a host
35049 * physical address (HPA) or a guest physical address (GPA) and must
35050 * point to a physically contiguous block of memory.
35052 uint64_t resp_addr;
35053 /* The direction for the flow aging configuration, 1 is rx path, 2 is tx path. */
35055 /* Enumeration denoting the RX, TX type of the resource. */
35056 #define HWRM_CFA_FLOW_AGING_QCFG_INPUT_FLAGS_PATH UINT32_C(0x1)
35058 #define HWRM_CFA_FLOW_AGING_QCFG_INPUT_FLAGS_PATH_TX UINT32_C(0x0)
35060 #define HWRM_CFA_FLOW_AGING_QCFG_INPUT_FLAGS_PATH_RX UINT32_C(0x1)
35061 #define HWRM_CFA_FLOW_AGING_QCFG_INPUT_FLAGS_PATH_LAST \
35062 HWRM_CFA_FLOW_AGING_QCFG_INPUT_FLAGS_PATH_RX
35063 uint8_t unused_0[7];
35066 /* hwrm_cfa_flow_aging_qcfg_output (size:320b/40B) */
35067 struct hwrm_cfa_flow_aging_qcfg_output {
35068 /* The specific error status for the command. */
35069 uint16_t error_code;
35070 /* The HWRM command request type. */
35072 /* The sequence ID from the original command. */
35074 /* The length of the response data in number of bytes. */
35076 /* The current flow aging timer for all TCP flows, the unit is 100 millisecond. */
35077 uint32_t tcp_flow_timer;
35078 /* The current TCP finished timer for all TCP flows, the unit is 100 millisecond. */
35079 uint32_t tcp_fin_timer;
35080 /* The current flow aging timer for all UDP flows, the unit is 100 millisecond. */
35081 uint32_t udp_flow_timer;
35082 /* The interval to dma eem ejection data to host memory, the unit is milliseconds. */
35083 uint16_t eem_dma_interval;
35084 /* The interval to notify driver to read the eem ejection data, the unit is milliseconds. */
35085 uint16_t eem_notice_interval;
35086 /* The maximum entries number in the eem context memory. */
35087 uint32_t eem_ctx_max_entries;
35088 /* The context memory ID for eem flow aging. */
35089 uint16_t eem_ctx_id;
35090 /* The context memory type for eem flow aging. */
35091 uint16_t eem_ctx_mem_type;
35092 uint8_t unused_0[7];
35094 * This field is used in Output records to indicate that the output
35095 * is completely written to RAM. This field should be read as '1'
35096 * to indicate that the output has been completely written.
35097 * When writing a command completion or response to an internal processor,
35098 * the order of writes has to be such that this field is written last.
35103 /*****************************
35104 * hwrm_cfa_flow_aging_qcaps *
35105 *****************************/
35108 /* hwrm_cfa_flow_aging_qcaps_input (size:192b/24B) */
35109 struct hwrm_cfa_flow_aging_qcaps_input {
35110 /* The HWRM command request type. */
35113 * The completion ring to send the completion event on. This should
35114 * be the NQ ID returned from the `nq_alloc` HWRM command.
35116 uint16_t cmpl_ring;
35118 * The sequence ID is used by the driver for tracking multiple
35119 * commands. This ID is treated as opaque data by the firmware and
35120 * the value is returned in the `hwrm_resp_hdr` upon completion.
35124 * The target ID of the command:
35125 * * 0x0-0xFFF8 - The function ID
35126 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
35127 * * 0xFFFD - Reserved for user-space HWRM interface
35130 uint16_t target_id;
35132 * A physical address pointer pointing to a host buffer that the
35133 * command's response data will be written. This can be either a host
35134 * physical address (HPA) or a guest physical address (GPA) and must
35135 * point to a physically contiguous block of memory.
35137 uint64_t resp_addr;
35138 /* The direction for the flow aging configuration, 1 is rx path, 2 is tx path. */
35140 /* Enumeration denoting the RX, TX type of the resource. */
35141 #define HWRM_CFA_FLOW_AGING_QCAPS_INPUT_FLAGS_PATH UINT32_C(0x1)
35143 #define HWRM_CFA_FLOW_AGING_QCAPS_INPUT_FLAGS_PATH_TX UINT32_C(0x0)
35145 #define HWRM_CFA_FLOW_AGING_QCAPS_INPUT_FLAGS_PATH_RX UINT32_C(0x1)
35146 #define HWRM_CFA_FLOW_AGING_QCAPS_INPUT_FLAGS_PATH_LAST \
35147 HWRM_CFA_FLOW_AGING_QCAPS_INPUT_FLAGS_PATH_RX
35148 uint8_t unused_0[7];
35151 /* hwrm_cfa_flow_aging_qcaps_output (size:256b/32B) */
35152 struct hwrm_cfa_flow_aging_qcaps_output {
35153 /* The specific error status for the command. */
35154 uint16_t error_code;
35155 /* The HWRM command request type. */
35157 /* The sequence ID from the original command. */
35159 /* The length of the response data in number of bytes. */
35161 /* The maximum flow aging timer for all TCP flows, the unit is 100 millisecond. */
35162 uint32_t max_tcp_flow_timer;
35163 /* The maximum TCP finished timer for all TCP flows, the unit is 100 millisecond. */
35164 uint32_t max_tcp_fin_timer;
35165 /* The maximum flow aging timer for all UDP flows, the unit is 100 millisecond. */
35166 uint32_t max_udp_flow_timer;
35167 /* The maximum aging flows that HW can support. */
35168 uint32_t max_aging_flows;
35169 uint8_t unused_0[7];
35171 * This field is used in Output records to indicate that the output
35172 * is completely written to RAM. This field should be read as '1'
35173 * to indicate that the output has been completely written.
35174 * When writing a command completion or response to an internal processor,
35175 * the order of writes has to be such that this field is written last.
35180 /**********************************
35181 * hwrm_cfa_tcp_flag_process_qcfg *
35182 **********************************/
35185 /* hwrm_cfa_tcp_flag_process_qcfg_input (size:128b/16B) */
35186 struct hwrm_cfa_tcp_flag_process_qcfg_input {
35187 /* The HWRM command request type. */
35190 * The completion ring to send the completion event on. This should
35191 * be the NQ ID returned from the `nq_alloc` HWRM command.
35193 uint16_t cmpl_ring;
35195 * The sequence ID is used by the driver for tracking multiple
35196 * commands. This ID is treated as opaque data by the firmware and
35197 * the value is returned in the `hwrm_resp_hdr` upon completion.
35201 * The target ID of the command:
35202 * * 0x0-0xFFF8 - The function ID
35203 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
35204 * * 0xFFFD - Reserved for user-space HWRM interface
35207 uint16_t target_id;
35209 * A physical address pointer pointing to a host buffer that the
35210 * command's response data will be written. This can be either a host
35211 * physical address (HPA) or a guest physical address (GPA) and must
35212 * point to a physically contiguous block of memory.
35214 uint64_t resp_addr;
35217 /* hwrm_cfa_tcp_flag_process_qcfg_output (size:192b/24B) */
35218 struct hwrm_cfa_tcp_flag_process_qcfg_output {
35219 /* The specific error status for the command. */
35220 uint16_t error_code;
35221 /* The HWRM command request type. */
35223 /* The sequence ID from the original command. */
35225 /* The length of the response data in number of bytes. */
35227 /* The port 0 RX mirror action record ID. */
35228 uint16_t rx_ar_id_port0;
35229 /* The port 1 RX mirror action record ID. */
35230 uint16_t rx_ar_id_port1;
35231 /* The port 0 RX action record ID for TX TCP flag packets from loopback path. */
35232 uint16_t tx_ar_id_port0;
35233 /* The port 1 RX action record ID for TX TCP flag packets from loopback path. */
35234 uint16_t tx_ar_id_port1;
35235 uint8_t unused_0[7];
35237 * This field is used in Output records to indicate that the output
35238 * is completely written to RAM. This field should be read as '1'
35239 * to indicate that the output has been completely written.
35240 * When writing a command completion or response to an internal processor,
35241 * the order of writes has to be such that this field is written last.
35246 /**********************
35247 * hwrm_cfa_pair_info *
35248 **********************/
35251 /* hwrm_cfa_pair_info_input (size:448b/56B) */
35252 struct hwrm_cfa_pair_info_input {
35253 /* The HWRM command request type. */
35256 * The completion ring to send the completion event on. This should
35257 * be the NQ ID returned from the `nq_alloc` HWRM command.
35259 uint16_t cmpl_ring;
35261 * The sequence ID is used by the driver for tracking multiple
35262 * commands. This ID is treated as opaque data by the firmware and
35263 * the value is returned in the `hwrm_resp_hdr` upon completion.
35267 * The target ID of the command:
35268 * * 0x0-0xFFF8 - The function ID
35269 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
35270 * * 0xFFFD - Reserved for user-space HWRM interface
35273 uint16_t target_id;
35275 * A physical address pointer pointing to a host buffer that the
35276 * command's response data will be written. This can be either a host
35277 * physical address (HPA) or a guest physical address (GPA) and must
35278 * point to a physically contiguous block of memory.
35280 uint64_t resp_addr;
35282 /* If this flag is set, lookup by name else lookup by index. */
35283 #define HWRM_CFA_PAIR_INFO_INPUT_FLAGS_LOOKUP_TYPE UINT32_C(0x1)
35284 /* If this flag is set, lookup by PF id and VF id. */
35285 #define HWRM_CFA_PAIR_INFO_INPUT_FLAGS_LOOKUP_REPRE UINT32_C(0x2)
35286 /* Pair table index. */
35287 uint16_t pair_index;
35288 /* Pair pf index. */
35290 /* Pair vf index. */
35292 /* Pair name (32 byte string). */
35293 char pair_name[32];
35296 /* hwrm_cfa_pair_info_output (size:576b/72B) */
35297 struct hwrm_cfa_pair_info_output {
35298 /* The specific error status for the command. */
35299 uint16_t error_code;
35300 /* The HWRM command request type. */
35302 /* The sequence ID from the original command. */
35304 /* The length of the response data in number of bytes. */
35306 /* Pair table index. */
35307 uint16_t next_pair_index;
35308 /* Pair member a's fid. */
35310 /* Logical host number. */
35311 uint8_t host_a_index;
35312 /* Logical PF number. */
35313 uint8_t pf_a_index;
35314 /* Pair member a's Linux logical VF number. */
35315 uint16_t vf_a_index;
35317 uint16_t rx_cfa_code_a;
35318 /* Tx CFA action. */
35319 uint16_t tx_cfa_action_a;
35320 /* Pair member b's fid. */
35322 /* Logical host number. */
35323 uint8_t host_b_index;
35324 /* Logical PF number. */
35325 uint8_t pf_b_index;
35326 /* Pair member a's Linux logical VF number. */
35327 uint16_t vf_b_index;
35329 uint16_t rx_cfa_code_b;
35330 /* Tx CFA action. */
35331 uint16_t tx_cfa_action_b;
35332 /* Pair mode (0-vf2fn, 1-rep2fn, 2-rep2rep, 3-proxy, 4-pfpair). */
35334 /* Pair between VF on local host with PF or VF on specified host. */
35335 #define HWRM_CFA_PAIR_INFO_OUTPUT_PAIR_MODE_VF2FN UINT32_C(0x0)
35336 /* Pair between REP on local host with PF or VF on specified host. */
35337 #define HWRM_CFA_PAIR_INFO_OUTPUT_PAIR_MODE_REP2FN UINT32_C(0x1)
35338 /* Pair between REP on local host with REP on specified host. */
35339 #define HWRM_CFA_PAIR_INFO_OUTPUT_PAIR_MODE_REP2REP UINT32_C(0x2)
35340 /* Pair for the proxy interface. */
35341 #define HWRM_CFA_PAIR_INFO_OUTPUT_PAIR_MODE_PROXY UINT32_C(0x3)
35342 /* Pair for the PF interface. */
35343 #define HWRM_CFA_PAIR_INFO_OUTPUT_PAIR_MODE_PFPAIR UINT32_C(0x4)
35344 #define HWRM_CFA_PAIR_INFO_OUTPUT_PAIR_MODE_LAST \
35345 HWRM_CFA_PAIR_INFO_OUTPUT_PAIR_MODE_PFPAIR
35347 uint8_t pair_state;
35348 /* Pair has been allocated */
35349 #define HWRM_CFA_PAIR_INFO_OUTPUT_PAIR_STATE_ALLOCATED UINT32_C(0x1)
35350 /* Both pair members are active */
35351 #define HWRM_CFA_PAIR_INFO_OUTPUT_PAIR_STATE_ACTIVE UINT32_C(0x2)
35352 #define HWRM_CFA_PAIR_INFO_OUTPUT_PAIR_STATE_LAST \
35353 HWRM_CFA_PAIR_INFO_OUTPUT_PAIR_STATE_ACTIVE
35354 /* Pair name (32 byte string). */
35355 char pair_name[32];
35356 uint8_t unused_0[7];
35358 * This field is used in Output records to indicate that the output
35359 * is completely written to RAM. This field should be read as '1'
35360 * to indicate that the output has been completely written.
35361 * When writing a command completion or response to an internal processor,
35362 * the order of writes has to be such that this field is written last.
35367 /**********************
35368 * hwrm_cfa_vfr_alloc *
35369 **********************/
35372 /* hwrm_cfa_vfr_alloc_input (size:448b/56B) */
35373 struct hwrm_cfa_vfr_alloc_input {
35374 /* The HWRM command request type. */
35377 * The completion ring to send the completion event on. This should
35378 * be the NQ ID returned from the `nq_alloc` HWRM command.
35380 uint16_t cmpl_ring;
35382 * The sequence ID is used by the driver for tracking multiple
35383 * commands. This ID is treated as opaque data by the firmware and
35384 * the value is returned in the `hwrm_resp_hdr` upon completion.
35388 * The target ID of the command:
35389 * * 0x0-0xFFF8 - The function ID
35390 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
35391 * * 0xFFFD - Reserved for user-space HWRM interface
35394 uint16_t target_id;
35396 * A physical address pointer pointing to a host buffer that the
35397 * command's response data will be written. This can be either a host
35398 * physical address (HPA) or a guest physical address (GPA) and must
35399 * point to a physically contiguous block of memory.
35401 uint64_t resp_addr;
35402 /* Logical VF number (range: 0 -> MAX_VFS -1). */
35405 * This field is reserved for the future use.
35406 * It shall be set to 0.
35409 uint8_t unused_0[4];
35410 /* VF Representor name (32 byte string). */
35414 /* hwrm_cfa_vfr_alloc_output (size:128b/16B) */
35415 struct hwrm_cfa_vfr_alloc_output {
35416 /* The specific error status for the command. */
35417 uint16_t error_code;
35418 /* The HWRM command request type. */
35420 /* The sequence ID from the original command. */
35422 /* The length of the response data in number of bytes. */
35425 uint16_t rx_cfa_code;
35426 /* Tx CFA action. */
35427 uint16_t tx_cfa_action;
35428 uint8_t unused_0[3];
35430 * This field is used in Output records to indicate that the output
35431 * is completely written to RAM. This field should be read as '1'
35432 * to indicate that the output has been completely written.
35433 * When writing a command completion or response to an internal processor,
35434 * the order of writes has to be such that this field is written last.
35439 /*********************
35440 * hwrm_cfa_vfr_free *
35441 *********************/
35444 /* hwrm_cfa_vfr_free_input (size:448b/56B) */
35445 struct hwrm_cfa_vfr_free_input {
35446 /* The HWRM command request type. */
35449 * The completion ring to send the completion event on. This should
35450 * be the NQ ID returned from the `nq_alloc` HWRM command.
35452 uint16_t cmpl_ring;
35454 * The sequence ID is used by the driver for tracking multiple
35455 * commands. This ID is treated as opaque data by the firmware and
35456 * the value is returned in the `hwrm_resp_hdr` upon completion.
35460 * The target ID of the command:
35461 * * 0x0-0xFFF8 - The function ID
35462 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
35463 * * 0xFFFD - Reserved for user-space HWRM interface
35466 uint16_t target_id;
35468 * A physical address pointer pointing to a host buffer that the
35469 * command's response data will be written. This can be either a host
35470 * physical address (HPA) or a guest physical address (GPA) and must
35471 * point to a physically contiguous block of memory.
35473 uint64_t resp_addr;
35474 /* VF Representor name (32 byte string). */
35476 /* Logical VF number (range: 0 -> MAX_VFS -1). */
35479 uint8_t unused_0[4];
35482 /* hwrm_cfa_vfr_free_output (size:128b/16B) */
35483 struct hwrm_cfa_vfr_free_output {
35484 /* The specific error status for the command. */
35485 uint16_t error_code;
35486 /* The HWRM command request type. */
35488 /* The sequence ID from the original command. */
35490 /* The length of the response data in number of bytes. */
35492 uint8_t unused_0[7];
35494 * This field is used in Output records to indicate that the output
35495 * is completely written to RAM. This field should be read as '1'
35496 * to indicate that the output has been completely written.
35497 * When writing a command completion or response to an internal processor,
35498 * the order of writes has to be such that this field is written last.
35505 /***************************************
35506 * hwrm_cfa_redirect_query_tunnel_type *
35507 ***************************************/
35510 /* hwrm_cfa_redirect_query_tunnel_type_input (size:192b/24B) */
35511 struct hwrm_cfa_redirect_query_tunnel_type_input {
35512 /* The HWRM command request type. */
35515 * The completion ring to send the completion event on. This should
35516 * be the NQ ID returned from the `nq_alloc` HWRM command.
35518 uint16_t cmpl_ring;
35520 * The sequence ID is used by the driver for tracking multiple
35521 * commands. This ID is treated as opaque data by the firmware and
35522 * the value is returned in the `hwrm_resp_hdr` upon completion.
35526 * The target ID of the command:
35527 * * 0x0-0xFFF8 - The function ID
35528 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
35529 * * 0xFFFD - Reserved for user-space HWRM interface
35532 uint16_t target_id;
35534 * A physical address pointer pointing to a host buffer that the
35535 * command's response data will be written. This can be either a host
35536 * physical address (HPA) or a guest physical address (GPA) and must
35537 * point to a physically contiguous block of memory.
35539 uint64_t resp_addr;
35540 /* The source function id. */
35542 uint8_t unused_0[6];
35545 /* hwrm_cfa_redirect_query_tunnel_type_output (size:128b/16B) */
35546 struct hwrm_cfa_redirect_query_tunnel_type_output {
35547 /* The specific error status for the command. */
35548 uint16_t error_code;
35549 /* The HWRM command request type. */
35551 /* The sequence ID from the original command. */
35553 /* The length of the response data in number of bytes. */
35556 uint32_t tunnel_mask;
35558 #define HWRM_CFA_REDIRECT_QUERY_TUNNEL_TYPE_OUTPUT_TUNNEL_MASK_NONTUNNEL \
35560 /* Virtual eXtensible Local Area Network (VXLAN) */
35561 #define HWRM_CFA_REDIRECT_QUERY_TUNNEL_TYPE_OUTPUT_TUNNEL_MASK_VXLAN \
35563 /* Network Virtualization Generic Routing Encapsulation (NVGRE) */
35564 #define HWRM_CFA_REDIRECT_QUERY_TUNNEL_TYPE_OUTPUT_TUNNEL_MASK_NVGRE \
35566 /* Generic Routing Encapsulation (GRE) inside Ethernet payload */
35567 #define HWRM_CFA_REDIRECT_QUERY_TUNNEL_TYPE_OUTPUT_TUNNEL_MASK_L2GRE \
35570 #define HWRM_CFA_REDIRECT_QUERY_TUNNEL_TYPE_OUTPUT_TUNNEL_MASK_IPIP \
35572 /* Generic Network Virtualization Encapsulation (Geneve) */
35573 #define HWRM_CFA_REDIRECT_QUERY_TUNNEL_TYPE_OUTPUT_TUNNEL_MASK_GENEVE \
35575 /* Multi-Protocol Label Switching (MPLS) */
35576 #define HWRM_CFA_REDIRECT_QUERY_TUNNEL_TYPE_OUTPUT_TUNNEL_MASK_MPLS \
35578 /* Stateless Transport Tunnel (STT) */
35579 #define HWRM_CFA_REDIRECT_QUERY_TUNNEL_TYPE_OUTPUT_TUNNEL_MASK_STT \
35581 /* Generic Routing Encapsulation (GRE) inside IP datagram payload */
35582 #define HWRM_CFA_REDIRECT_QUERY_TUNNEL_TYPE_OUTPUT_TUNNEL_MASK_IPGRE \
35584 /* IPV4 over virtual eXtensible Local Area Network (IPV4oVXLAN) */
35585 #define HWRM_CFA_REDIRECT_QUERY_TUNNEL_TYPE_OUTPUT_TUNNEL_MASK_VXLAN_V4 \
35587 /* Enhance Generic Routing Encapsulation (GRE version 1) inside IP datagram payload */
35588 #define HWRM_CFA_REDIRECT_QUERY_TUNNEL_TYPE_OUTPUT_TUNNEL_MASK_IPGRE_V1 \
35590 /* Any tunneled traffic */
35591 #define HWRM_CFA_REDIRECT_QUERY_TUNNEL_TYPE_OUTPUT_TUNNEL_MASK_ANYTUNNEL \
35593 /* Use fixed layer 2 ether type of 0xFFFF */
35594 #define HWRM_CFA_REDIRECT_QUERY_TUNNEL_TYPE_OUTPUT_TUNNEL_MASK_L2_ETYPE \
35596 /* IPV6 over virtual eXtensible Local Area Network with GPE header (IPV6oVXLANGPE) */
35597 #define HWRM_CFA_REDIRECT_QUERY_TUNNEL_TYPE_OUTPUT_TUNNEL_MASK_VXLAN_GPE_V6 \
35599 uint8_t unused_0[3];
35601 * This field is used in Output records to indicate that the output
35602 * is completely written to RAM. This field should be read as '1'
35603 * to indicate that the output has been completely written.
35604 * When writing a command completion or response to an internal processor,
35605 * the order of writes has to be such that this field is written last.
35610 /*************************
35611 * hwrm_cfa_ctx_mem_rgtr *
35612 *************************/
35615 /* hwrm_cfa_ctx_mem_rgtr_input (size:256b/32B) */
35616 struct hwrm_cfa_ctx_mem_rgtr_input {
35617 /* The HWRM command request type. */
35620 * The completion ring to send the completion event on. This should
35621 * be the NQ ID returned from the `nq_alloc` HWRM command.
35623 uint16_t cmpl_ring;
35625 * The sequence ID is used by the driver for tracking multiple
35626 * commands. This ID is treated as opaque data by the firmware and
35627 * the value is returned in the `hwrm_resp_hdr` upon completion.
35631 * The target ID of the command:
35632 * * 0x0-0xFFF8 - The function ID
35633 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
35634 * * 0xFFFD - Reserved for user-space HWRM interface
35637 uint16_t target_id;
35639 * A physical address pointer pointing to a host buffer that the
35640 * command's response data will be written. This can be either a host
35641 * physical address (HPA) or a guest physical address (GPA) and must
35642 * point to a physically contiguous block of memory.
35644 uint64_t resp_addr;
35646 /* Counter PBL indirect levels. */
35647 uint8_t page_level;
35648 /* PBL pointer is physical start address. */
35649 #define HWRM_CFA_CTX_MEM_RGTR_INPUT_PAGE_LEVEL_LVL_0 UINT32_C(0x0)
35650 /* PBL pointer points to PTE table. */
35651 #define HWRM_CFA_CTX_MEM_RGTR_INPUT_PAGE_LEVEL_LVL_1 UINT32_C(0x1)
35652 /* PBL pointer points to PDE table with each entry pointing to PTE tables. */
35653 #define HWRM_CFA_CTX_MEM_RGTR_INPUT_PAGE_LEVEL_LVL_2 UINT32_C(0x2)
35654 #define HWRM_CFA_CTX_MEM_RGTR_INPUT_PAGE_LEVEL_LAST \
35655 HWRM_CFA_CTX_MEM_RGTR_INPUT_PAGE_LEVEL_LVL_2
35658 /* 4KB page size. */
35659 #define HWRM_CFA_CTX_MEM_RGTR_INPUT_PAGE_SIZE_4K UINT32_C(0x0)
35660 /* 8KB page size. */
35661 #define HWRM_CFA_CTX_MEM_RGTR_INPUT_PAGE_SIZE_8K UINT32_C(0x1)
35662 /* 64KB page size. */
35663 #define HWRM_CFA_CTX_MEM_RGTR_INPUT_PAGE_SIZE_64K UINT32_C(0x4)
35664 /* 256KB page size. */
35665 #define HWRM_CFA_CTX_MEM_RGTR_INPUT_PAGE_SIZE_256K UINT32_C(0x6)
35666 /* 1MB page size. */
35667 #define HWRM_CFA_CTX_MEM_RGTR_INPUT_PAGE_SIZE_1M UINT32_C(0x8)
35668 /* 2MB page size. */
35669 #define HWRM_CFA_CTX_MEM_RGTR_INPUT_PAGE_SIZE_2M UINT32_C(0x9)
35670 /* 4MB page size. */
35671 #define HWRM_CFA_CTX_MEM_RGTR_INPUT_PAGE_SIZE_4M UINT32_C(0xa)
35672 /* 1GB page size. */
35673 #define HWRM_CFA_CTX_MEM_RGTR_INPUT_PAGE_SIZE_1G UINT32_C(0x12)
35674 #define HWRM_CFA_CTX_MEM_RGTR_INPUT_PAGE_SIZE_LAST \
35675 HWRM_CFA_CTX_MEM_RGTR_INPUT_PAGE_SIZE_1G
35677 /* Pointer to the PBL, or PDL depending on number of levels */
35681 /* hwrm_cfa_ctx_mem_rgtr_output (size:128b/16B) */
35682 struct hwrm_cfa_ctx_mem_rgtr_output {
35683 /* The specific error status for the command. */
35684 uint16_t error_code;
35685 /* The HWRM command request type. */
35687 /* The sequence ID from the original command. */
35689 /* The length of the response data in number of bytes. */
35692 * Id/Handle to the recently register context memory. This handle is passed
35693 * to the CFA feature.
35696 uint8_t unused_0[5];
35698 * This field is used in Output records to indicate that the output
35699 * is completely written to RAM. This field should be read as '1'
35700 * to indicate that the output has been completely written.
35701 * When writing a command completion or response to an internal processor,
35702 * the order of writes has to be such that this field is written last.
35707 /***************************
35708 * hwrm_cfa_ctx_mem_unrgtr *
35709 ***************************/
35712 /* hwrm_cfa_ctx_mem_unrgtr_input (size:192b/24B) */
35713 struct hwrm_cfa_ctx_mem_unrgtr_input {
35714 /* The HWRM command request type. */
35717 * The completion ring to send the completion event on. This should
35718 * be the NQ ID returned from the `nq_alloc` HWRM command.
35720 uint16_t cmpl_ring;
35722 * The sequence ID is used by the driver for tracking multiple
35723 * commands. This ID is treated as opaque data by the firmware and
35724 * the value is returned in the `hwrm_resp_hdr` upon completion.
35728 * The target ID of the command:
35729 * * 0x0-0xFFF8 - The function ID
35730 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
35731 * * 0xFFFD - Reserved for user-space HWRM interface
35734 uint16_t target_id;
35736 * A physical address pointer pointing to a host buffer that the
35737 * command's response data will be written. This can be either a host
35738 * physical address (HPA) or a guest physical address (GPA) and must
35739 * point to a physically contiguous block of memory.
35741 uint64_t resp_addr;
35743 * Id/Handle to the recently register context memory. This handle is passed
35744 * to the CFA feature.
35747 uint8_t unused_0[6];
35750 /* hwrm_cfa_ctx_mem_unrgtr_output (size:128b/16B) */
35751 struct hwrm_cfa_ctx_mem_unrgtr_output {
35752 /* The specific error status for the command. */
35753 uint16_t error_code;
35754 /* The HWRM command request type. */
35756 /* The sequence ID from the original command. */
35758 /* The length of the response data in number of bytes. */
35760 uint8_t unused_0[7];
35762 * This field is used in Output records to indicate that the output
35763 * is completely written to RAM. This field should be read as '1'
35764 * to indicate that the output has been completely written.
35765 * When writing a command completion or response to an internal processor,
35766 * the order of writes has to be such that this field is written last.
35771 /*************************
35772 * hwrm_cfa_ctx_mem_qctx *
35773 *************************/
35776 /* hwrm_cfa_ctx_mem_qctx_input (size:192b/24B) */
35777 struct hwrm_cfa_ctx_mem_qctx_input {
35778 /* The HWRM command request type. */
35781 * The completion ring to send the completion event on. This should
35782 * be the NQ ID returned from the `nq_alloc` HWRM command.
35784 uint16_t cmpl_ring;
35786 * The sequence ID is used by the driver for tracking multiple
35787 * commands. This ID is treated as opaque data by the firmware and
35788 * the value is returned in the `hwrm_resp_hdr` upon completion.
35792 * The target ID of the command:
35793 * * 0x0-0xFFF8 - The function ID
35794 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
35795 * * 0xFFFD - Reserved for user-space HWRM interface
35798 uint16_t target_id;
35800 * A physical address pointer pointing to a host buffer that the
35801 * command's response data will be written. This can be either a host
35802 * physical address (HPA) or a guest physical address (GPA) and must
35803 * point to a physically contiguous block of memory.
35805 uint64_t resp_addr;
35807 * Id/Handle to the recently register context memory. This handle is passed
35808 * to the CFA feature.
35811 uint8_t unused_0[6];
35814 /* hwrm_cfa_ctx_mem_qctx_output (size:256b/32B) */
35815 struct hwrm_cfa_ctx_mem_qctx_output {
35816 /* The specific error status for the command. */
35817 uint16_t error_code;
35818 /* The HWRM command request type. */
35820 /* The sequence ID from the original command. */
35822 /* The length of the response data in number of bytes. */
35825 /* Counter PBL indirect levels. */
35826 uint8_t page_level;
35827 /* PBL pointer is physical start address. */
35828 #define HWRM_CFA_CTX_MEM_QCTX_OUTPUT_PAGE_LEVEL_LVL_0 UINT32_C(0x0)
35829 /* PBL pointer points to PTE table. */
35830 #define HWRM_CFA_CTX_MEM_QCTX_OUTPUT_PAGE_LEVEL_LVL_1 UINT32_C(0x1)
35831 /* PBL pointer points to PDE table with each entry pointing to PTE tables. */
35832 #define HWRM_CFA_CTX_MEM_QCTX_OUTPUT_PAGE_LEVEL_LVL_2 UINT32_C(0x2)
35833 #define HWRM_CFA_CTX_MEM_QCTX_OUTPUT_PAGE_LEVEL_LAST \
35834 HWRM_CFA_CTX_MEM_QCTX_OUTPUT_PAGE_LEVEL_LVL_2
35837 /* 4KB page size. */
35838 #define HWRM_CFA_CTX_MEM_QCTX_OUTPUT_PAGE_SIZE_4K UINT32_C(0x0)
35839 /* 8KB page size. */
35840 #define HWRM_CFA_CTX_MEM_QCTX_OUTPUT_PAGE_SIZE_8K UINT32_C(0x1)
35841 /* 64KB page size. */
35842 #define HWRM_CFA_CTX_MEM_QCTX_OUTPUT_PAGE_SIZE_64K UINT32_C(0x4)
35843 /* 256KB page size. */
35844 #define HWRM_CFA_CTX_MEM_QCTX_OUTPUT_PAGE_SIZE_256K UINT32_C(0x6)
35845 /* 1MB page size. */
35846 #define HWRM_CFA_CTX_MEM_QCTX_OUTPUT_PAGE_SIZE_1M UINT32_C(0x8)
35847 /* 2MB page size. */
35848 #define HWRM_CFA_CTX_MEM_QCTX_OUTPUT_PAGE_SIZE_2M UINT32_C(0x9)
35849 /* 4MB page size. */
35850 #define HWRM_CFA_CTX_MEM_QCTX_OUTPUT_PAGE_SIZE_4M UINT32_C(0xa)
35851 /* 1GB page size. */
35852 #define HWRM_CFA_CTX_MEM_QCTX_OUTPUT_PAGE_SIZE_1G UINT32_C(0x12)
35853 #define HWRM_CFA_CTX_MEM_QCTX_OUTPUT_PAGE_SIZE_LAST \
35854 HWRM_CFA_CTX_MEM_QCTX_OUTPUT_PAGE_SIZE_1G
35855 uint8_t unused_0[4];
35856 /* Pointer to the PBL, or PDL depending on number of levels */
35858 uint8_t unused_1[7];
35860 * This field is used in Output records to indicate that the output
35861 * is completely written to RAM. This field should be read as '1'
35862 * to indicate that the output has been completely written.
35863 * When writing a command completion or response to an internal processor,
35864 * the order of writes has to be such that this field is written last.
35869 /**************************
35870 * hwrm_cfa_ctx_mem_qcaps *
35871 **************************/
35874 /* hwrm_cfa_ctx_mem_qcaps_input (size:128b/16B) */
35875 struct hwrm_cfa_ctx_mem_qcaps_input {
35876 /* The HWRM command request type. */
35879 * The completion ring to send the completion event on. This should
35880 * be the NQ ID returned from the `nq_alloc` HWRM command.
35882 uint16_t cmpl_ring;
35884 * The sequence ID is used by the driver for tracking multiple
35885 * commands. This ID is treated as opaque data by the firmware and
35886 * the value is returned in the `hwrm_resp_hdr` upon completion.
35890 * The target ID of the command:
35891 * * 0x0-0xFFF8 - The function ID
35892 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
35893 * * 0xFFFD - Reserved for user-space HWRM interface
35896 uint16_t target_id;
35898 * A physical address pointer pointing to a host buffer that the
35899 * command's response data will be written. This can be either a host
35900 * physical address (HPA) or a guest physical address (GPA) and must
35901 * point to a physically contiguous block of memory.
35903 uint64_t resp_addr;
35906 /* hwrm_cfa_ctx_mem_qcaps_output (size:128b/16B) */
35907 struct hwrm_cfa_ctx_mem_qcaps_output {
35908 /* The specific error status for the command. */
35909 uint16_t error_code;
35910 /* The HWRM command request type. */
35912 /* The sequence ID from the original command. */
35914 /* The length of the response data in number of bytes. */
35916 /* Indicates the maximum number of context memory which can be registered. */
35917 uint16_t max_entries;
35918 uint8_t unused_0[5];
35920 * This field is used in Output records to indicate that the output
35921 * is completely written to RAM. This field should be read as '1'
35922 * to indicate that the output has been completely written.
35923 * When writing a command completion or response to an internal processor,
35924 * the order of writes has to be such that this field is written last.
35929 /**********************
35930 * hwrm_cfa_eem_qcaps *
35931 **********************/
35934 /* hwrm_cfa_eem_qcaps_input (size:192b/24B) */
35935 struct hwrm_cfa_eem_qcaps_input {
35936 /* The HWRM command request type. */
35939 * The completion ring to send the completion event on. This should
35940 * be the NQ ID returned from the `nq_alloc` HWRM command.
35942 uint16_t cmpl_ring;
35944 * The sequence ID is used by the driver for tracking multiple
35945 * commands. This ID is treated as opaque data by the firmware and
35946 * the value is returned in the `hwrm_resp_hdr` upon completion.
35950 * The target ID of the command:
35951 * * 0x0-0xFFF8 - The function ID
35952 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
35953 * * 0xFFFD - Reserved for user-space HWRM interface
35956 uint16_t target_id;
35958 * A physical address pointer pointing to a host buffer that the
35959 * command's response data will be written. This can be either a host
35960 * physical address (HPA) or a guest physical address (GPA) and must
35961 * point to a physically contiguous block of memory.
35963 uint64_t resp_addr;
35966 * When set to 1, indicates the configuration will apply to TX flows
35967 * which are to be offloaded.
35968 * Note if this bit is set then the path_rx bit can't be set.
35970 #define HWRM_CFA_EEM_QCAPS_INPUT_FLAGS_PATH_TX \
35973 * When set to 1, indicates the configuration will apply to RX flows
35974 * which are to be offloaded.
35975 * Note if this bit is set then the path_tx bit can't be set.
35977 #define HWRM_CFA_EEM_QCAPS_INPUT_FLAGS_PATH_RX \
35979 /* When set to 1, all offloaded flows will be sent to EEM. */
35980 #define HWRM_CFA_EEM_QCAPS_INPUT_FLAGS_PREFERRED_OFFLOAD \
35985 /* hwrm_cfa_eem_qcaps_output (size:320b/40B) */
35986 struct hwrm_cfa_eem_qcaps_output {
35987 /* The specific error status for the command. */
35988 uint16_t error_code;
35989 /* The HWRM command request type. */
35991 /* The sequence ID from the original command. */
35993 /* The length of the response data in number of bytes. */
35997 * When set to 1, indicates the configuration will apply to TX flows
35998 * which are to be offloaded.
35999 * Note if this bit is set then the path_rx bit can't be set.
36001 #define HWRM_CFA_EEM_QCAPS_OUTPUT_FLAGS_PATH_TX \
36004 * When set to 1, indicates the configuration will apply to RX flows
36005 * which are to be offloaded.
36006 * Note if this bit is set then the path_tx bit can't be set.
36008 #define HWRM_CFA_EEM_QCAPS_OUTPUT_FLAGS_PATH_RX \
36011 * When set to 1, indicates the the FW supports the Centralized
36012 * Memory Model. The concept designates one entity for the
36013 * memory allocation while all others ‘subscribe’ to it.
36015 #define HWRM_CFA_EEM_QCAPS_OUTPUT_FLAGS_CENTRALIZED_MEMORY_MODEL_SUPPORTED \
36018 * When set to 1, indicates the the FW supports the Detached
36019 * Centralized Memory Model. The memory is allocated and managed
36020 * as a separate entity. All PFs and VFs will be granted direct
36021 * or semi-direct access to the allocated memory while none of
36022 * which can interfere with the management of the memory.
36024 #define HWRM_CFA_EEM_QCAPS_OUTPUT_FLAGS_DETACHED_CENTRALIZED_MEMORY_MODEL_SUPPORTED \
36027 uint32_t supported;
36029 * If set to 1, then EEM KEY0 table is supported using crc32 hash.
36030 * If set to 0, EEM KEY0 table is not supported.
36032 #define HWRM_CFA_EEM_QCAPS_OUTPUT_SUPPORTED_KEY0_TABLE \
36035 * If set to 1, then EEM KEY1 table is supported using lookup3 hash.
36036 * If set to 0, EEM KEY1 table is not supported.
36038 #define HWRM_CFA_EEM_QCAPS_OUTPUT_SUPPORTED_KEY1_TABLE \
36041 * If set to 1, then EEM External Record table is supported.
36042 * If set to 0, EEM External Record table is not supported.
36043 * (This table includes action record, EFC pointers, encap pointers)
36045 #define HWRM_CFA_EEM_QCAPS_OUTPUT_SUPPORTED_EXTERNAL_RECORD_TABLE \
36048 * If set to 1, then EEM External Flow Counters table is supported.
36049 * If set to 0, EEM External Flow Counters table is not supported.
36051 #define HWRM_CFA_EEM_QCAPS_OUTPUT_SUPPORTED_EXTERNAL_FLOW_COUNTERS_TABLE \
36054 * If set to 1, then FID table used for implicit flow flush is supported.
36055 * If set to 0, then FID table used for implicit flow flush is not supported.
36057 #define HWRM_CFA_EEM_QCAPS_OUTPUT_SUPPORTED_FID_TABLE \
36060 * The maximum number of entries supported by EEM. When configuring the host memory
36061 * the number of numbers of entries that can supported are -
36062 * 32k, 64k 128k, 256k, 512k, 1M, 2M, 4M, 8M, 32M, 64M, 128M entries.
36063 * Any value that are not these values, the FW will round down to the closest support
36064 * number of entries.
36066 uint32_t max_entries_supported;
36067 /* The entry size in bytes of each entry in the EEM KEY0/KEY1 tables. */
36068 uint16_t key_entry_size;
36069 /* The entry size in bytes of each entry in the EEM RECORD tables. */
36070 uint16_t record_entry_size;
36071 /* The entry size in bytes of each entry in the EEM EFC tables. */
36072 uint16_t efc_entry_size;
36073 /* The FID size in bytes of each entry in the EEM FID tables. */
36074 uint16_t fid_entry_size;
36075 uint8_t unused_1[7];
36077 * This field is used in Output records to indicate that the output
36078 * is completely written to RAM. This field should be read as '1'
36079 * to indicate that the output has been completely written.
36080 * When writing a command completion or response to an internal processor,
36081 * the order of writes has to be such that this field is written last.
36086 /********************
36087 * hwrm_cfa_eem_cfg *
36088 ********************/
36091 /* hwrm_cfa_eem_cfg_input (size:384b/48B) */
36092 struct hwrm_cfa_eem_cfg_input {
36093 /* The HWRM command request type. */
36096 * The completion ring to send the completion event on. This should
36097 * be the NQ ID returned from the `nq_alloc` HWRM command.
36099 uint16_t cmpl_ring;
36101 * The sequence ID is used by the driver for tracking multiple
36102 * commands. This ID is treated as opaque data by the firmware and
36103 * the value is returned in the `hwrm_resp_hdr` upon completion.
36107 * The target ID of the command:
36108 * * 0x0-0xFFF8 - The function ID
36109 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
36110 * * 0xFFFD - Reserved for user-space HWRM interface
36113 uint16_t target_id;
36115 * A physical address pointer pointing to a host buffer that the
36116 * command's response data will be written. This can be either a host
36117 * physical address (HPA) or a guest physical address (GPA) and must
36118 * point to a physically contiguous block of memory.
36120 uint64_t resp_addr;
36123 * When set to 1, indicates the configuration will apply to TX flows
36124 * which are to be offloaded.
36125 * Note if this bit is set then the path_rx bit can't be set.
36127 #define HWRM_CFA_EEM_CFG_INPUT_FLAGS_PATH_TX \
36130 * When set to 1, indicates the configuration will apply to RX flows
36131 * which are to be offloaded.
36132 * Note if this bit is set then the path_tx bit can't be set.
36134 #define HWRM_CFA_EEM_CFG_INPUT_FLAGS_PATH_RX \
36136 /* When set to 1, all offloaded flows will be sent to EEM. */
36137 #define HWRM_CFA_EEM_CFG_INPUT_FLAGS_PREFERRED_OFFLOAD \
36139 /* When set to 1, secondary, 0 means primary. */
36140 #define HWRM_CFA_EEM_CFG_INPUT_FLAGS_SECONDARY_PF \
36143 * Group_id which used by Firmware to identify memory pools belonging
36144 * to certain group.
36149 * Configured EEM with the given number of entries. All the EEM tables KEY0, KEY1,
36150 * RECORD, EFC all have the same number of entries and all tables will be configured
36151 * using this value. Current minimum value is 32k. Current maximum value is 128M.
36153 uint32_t num_entries;
36155 /* Configured EEM with the given context if for KEY0 table. */
36156 uint16_t key0_ctx_id;
36157 /* Configured EEM with the given context if for KEY1 table. */
36158 uint16_t key1_ctx_id;
36159 /* Configured EEM with the given context if for RECORD table. */
36160 uint16_t record_ctx_id;
36161 /* Configured EEM with the given context if for EFC table. */
36162 uint16_t efc_ctx_id;
36163 /* Configured EEM with the given context if for EFC table. */
36164 uint16_t fid_ctx_id;
36169 /* hwrm_cfa_eem_cfg_output (size:128b/16B) */
36170 struct hwrm_cfa_eem_cfg_output {
36171 /* The specific error status for the command. */
36172 uint16_t error_code;
36173 /* The HWRM command request type. */
36175 /* The sequence ID from the original command. */
36177 /* The length of the response data in number of bytes. */
36179 uint8_t unused_0[7];
36181 * This field is used in Output records to indicate that the output
36182 * is completely written to RAM. This field should be read as '1'
36183 * to indicate that the output has been completely written.
36184 * When writing a command completion or response to an internal processor,
36185 * the order of writes has to be such that this field is written last.
36190 /*********************
36191 * hwrm_cfa_eem_qcfg *
36192 *********************/
36195 /* hwrm_cfa_eem_qcfg_input (size:192b/24B) */
36196 struct hwrm_cfa_eem_qcfg_input {
36197 /* The HWRM command request type. */
36200 * The completion ring to send the completion event on. This should
36201 * be the NQ ID returned from the `nq_alloc` HWRM command.
36203 uint16_t cmpl_ring;
36205 * The sequence ID is used by the driver for tracking multiple
36206 * commands. This ID is treated as opaque data by the firmware and
36207 * the value is returned in the `hwrm_resp_hdr` upon completion.
36211 * The target ID of the command:
36212 * * 0x0-0xFFF8 - The function ID
36213 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
36214 * * 0xFFFD - Reserved for user-space HWRM interface
36217 uint16_t target_id;
36219 * A physical address pointer pointing to a host buffer that the
36220 * command's response data will be written. This can be either a host
36221 * physical address (HPA) or a guest physical address (GPA) and must
36222 * point to a physically contiguous block of memory.
36224 uint64_t resp_addr;
36226 /* When set to 1, indicates the configuration is the TX flow. */
36227 #define HWRM_CFA_EEM_QCFG_INPUT_FLAGS_PATH_TX UINT32_C(0x1)
36228 /* When set to 1, indicates the configuration is the RX flow. */
36229 #define HWRM_CFA_EEM_QCFG_INPUT_FLAGS_PATH_RX UINT32_C(0x2)
36233 /* hwrm_cfa_eem_qcfg_output (size:256b/32B) */
36234 struct hwrm_cfa_eem_qcfg_output {
36235 /* The specific error status for the command. */
36236 uint16_t error_code;
36237 /* The HWRM command request type. */
36239 /* The sequence ID from the original command. */
36241 /* The length of the response data in number of bytes. */
36244 /* When set to 1, indicates the configuration is the TX flow. */
36245 #define HWRM_CFA_EEM_QCFG_OUTPUT_FLAGS_PATH_TX \
36247 /* When set to 1, indicates the configuration is the RX flow. */
36248 #define HWRM_CFA_EEM_QCFG_OUTPUT_FLAGS_PATH_RX \
36250 /* When set to 1, all offloaded flows will be sent to EEM. */
36251 #define HWRM_CFA_EEM_QCFG_OUTPUT_FLAGS_PREFERRED_OFFLOAD \
36253 /* The number of entries the FW has configured for EEM. */
36254 uint32_t num_entries;
36255 /* Configured EEM with the given context if for KEY0 table. */
36256 uint16_t key0_ctx_id;
36257 /* Configured EEM with the given context if for KEY1 table. */
36258 uint16_t key1_ctx_id;
36259 /* Configured EEM with the given context if for RECORD table. */
36260 uint16_t record_ctx_id;
36261 /* Configured EEM with the given context if for EFC table. */
36262 uint16_t efc_ctx_id;
36263 /* Configured EEM with the given context if for EFC table. */
36264 uint16_t fid_ctx_id;
36265 uint8_t unused_2[5];
36267 * This field is used in Output records to indicate that the output
36268 * is completely written to RAM. This field should be read as '1'
36269 * to indicate that the output has been completely written.
36270 * When writing a command completion or response to an internal processor,
36271 * the order of writes has to be such that this field is written last.
36276 /*******************
36277 * hwrm_cfa_eem_op *
36278 *******************/
36281 /* hwrm_cfa_eem_op_input (size:192b/24B) */
36282 struct hwrm_cfa_eem_op_input {
36283 /* The HWRM command request type. */
36286 * The completion ring to send the completion event on. This should
36287 * be the NQ ID returned from the `nq_alloc` HWRM command.
36289 uint16_t cmpl_ring;
36291 * The sequence ID is used by the driver for tracking multiple
36292 * commands. This ID is treated as opaque data by the firmware and
36293 * the value is returned in the `hwrm_resp_hdr` upon completion.
36297 * The target ID of the command:
36298 * * 0x0-0xFFF8 - The function ID
36299 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
36300 * * 0xFFFD - Reserved for user-space HWRM interface
36303 uint16_t target_id;
36305 * A physical address pointer pointing to a host buffer that the
36306 * command's response data will be written. This can be either a host
36307 * physical address (HPA) or a guest physical address (GPA) and must
36308 * point to a physically contiguous block of memory.
36310 uint64_t resp_addr;
36313 * When set to 1, indicates the host memory which is passed will be
36314 * used for the TX flow offload function specified in fid.
36315 * Note if this bit is set then the path_rx bit can't be set.
36317 #define HWRM_CFA_EEM_OP_INPUT_FLAGS_PATH_TX UINT32_C(0x1)
36319 * When set to 1, indicates the host memory which is passed will be
36320 * used for the RX flow offload function specified in fid.
36321 * Note if this bit is set then the path_tx bit can't be set.
36323 #define HWRM_CFA_EEM_OP_INPUT_FLAGS_PATH_RX UINT32_C(0x2)
36325 /* The number of EEM key table entries to be configured. */
36327 /* This value is reserved and should not be used. */
36328 #define HWRM_CFA_EEM_OP_INPUT_OP_RESERVED UINT32_C(0x0)
36330 * To properly stop EEM and ensure there are no DMA's, the caller
36331 * must disable EEM for the given PF, using this call. This will
36332 * safely disable EEM and ensure that all DMA'ed to the
36333 * keys/records/efc have been completed.
36335 #define HWRM_CFA_EEM_OP_INPUT_OP_EEM_DISABLE UINT32_C(0x1)
36337 * Once the EEM host memory has been configured, EEM options have
36338 * been configured. Then the caller should enable EEM for the given
36339 * PF. Note once this call has been made, then the EEM mechanism
36340 * will be active and DMA's will occur as packets are processed.
36342 #define HWRM_CFA_EEM_OP_INPUT_OP_EEM_ENABLE UINT32_C(0x2)
36344 * Clear EEM settings for the given PF so that the register values
36345 * are reset back to there initial state.
36347 #define HWRM_CFA_EEM_OP_INPUT_OP_EEM_CLEANUP UINT32_C(0x3)
36348 #define HWRM_CFA_EEM_OP_INPUT_OP_LAST \
36349 HWRM_CFA_EEM_OP_INPUT_OP_EEM_CLEANUP
36352 /* hwrm_cfa_eem_op_output (size:128b/16B) */
36353 struct hwrm_cfa_eem_op_output {
36354 /* The specific error status for the command. */
36355 uint16_t error_code;
36356 /* The HWRM command request type. */
36358 /* The sequence ID from the original command. */
36360 /* The length of the response data in number of bytes. */
36362 uint8_t unused_0[7];
36364 * This field is used in Output records to indicate that the output
36365 * is completely written to RAM. This field should be read as '1'
36366 * to indicate that the output has been completely written.
36367 * When writing a command completion or response to an internal processor,
36368 * the order of writes has to be such that this field is written last.
36373 /********************************
36374 * hwrm_cfa_adv_flow_mgnt_qcaps *
36375 ********************************/
36378 /* hwrm_cfa_adv_flow_mgnt_qcaps_input (size:256b/32B) */
36379 struct hwrm_cfa_adv_flow_mgnt_qcaps_input {
36380 /* The HWRM command request type. */
36383 * The completion ring to send the completion event on. This should
36384 * be the NQ ID returned from the `nq_alloc` HWRM command.
36386 uint16_t cmpl_ring;
36388 * The sequence ID is used by the driver for tracking multiple
36389 * commands. This ID is treated as opaque data by the firmware and
36390 * the value is returned in the `hwrm_resp_hdr` upon completion.
36394 * The target ID of the command:
36395 * * 0x0-0xFFF8 - The function ID
36396 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
36397 * * 0xFFFD - Reserved for user-space HWRM interface
36400 uint16_t target_id;
36402 * A physical address pointer pointing to a host buffer that the
36403 * command's response data will be written. This can be either a host
36404 * physical address (HPA) or a guest physical address (GPA) and must
36405 * point to a physically contiguous block of memory.
36407 uint64_t resp_addr;
36408 uint32_t unused_0[4];
36411 /* hwrm_cfa_adv_flow_mgnt_qcaps_output (size:128b/16B) */
36412 struct hwrm_cfa_adv_flow_mgnt_qcaps_output {
36413 /* The specific error status for the command. */
36414 uint16_t error_code;
36415 /* The HWRM command request type. */
36417 /* The sequence ID from the original command. */
36419 /* The length of the response data in number of bytes. */
36423 * Value of 1 to indicate firmware support 16-bit flow handle.
36424 * Value of 0 to indicate firmware not support 16-bit flow handle.
36426 #define HWRM_CFA_ADV_FLOW_MGNT_QCAPS_OUTPUT_FLAGS_FLOW_HND_16BIT_SUPPORTED \
36429 * Value of 1 to indicate firmware support 64-bit flow handle.
36430 * Value of 0 to indicate firmware not support 64-bit flow handle.
36432 #define HWRM_CFA_ADV_FLOW_MGNT_QCAPS_OUTPUT_FLAGS_FLOW_HND_64BIT_SUPPORTED \
36435 * Value of 1 to indicate firmware support flow batch delete operation through
36436 * HWRM_CFA_FLOW_FLUSH command.
36437 * Value of 0 to indicate that the firmware does not support flow batch delete
36440 #define HWRM_CFA_ADV_FLOW_MGNT_QCAPS_OUTPUT_FLAGS_FLOW_BATCH_DELETE_SUPPORTED \
36443 * Value of 1 to indicate that the firmware support flow reset all operation through
36444 * HWRM_CFA_FLOW_FLUSH command.
36445 * Value of 0 indicates firmware does not support flow reset all operation.
36447 #define HWRM_CFA_ADV_FLOW_MGNT_QCAPS_OUTPUT_FLAGS_FLOW_RESET_ALL_SUPPORTED \
36450 * Value of 1 to indicate that firmware supports use of FID as dest_id in
36451 * HWRM_CFA_NTUPLE_ALLOC/CFG commands.
36452 * Value of 0 indicates firmware does not support use of FID as dest_id.
36454 #define HWRM_CFA_ADV_FLOW_MGNT_QCAPS_OUTPUT_FLAGS_NTUPLE_FLOW_DEST_FUNC_SUPPORTED \
36457 * Value of 1 to indicate that firmware supports TX EEM flows.
36458 * Value of 0 indicates firmware does not support TX EEM flows.
36460 #define HWRM_CFA_ADV_FLOW_MGNT_QCAPS_OUTPUT_FLAGS_TX_EEM_FLOW_SUPPORTED \
36463 * Value of 1 to indicate that firmware supports RX EEM flows.
36464 * Value of 0 indicates firmware does not support RX EEM flows.
36466 #define HWRM_CFA_ADV_FLOW_MGNT_QCAPS_OUTPUT_FLAGS_RX_EEM_FLOW_SUPPORTED \
36469 * Value of 1 to indicate that firmware supports the dynamic allocation of an
36470 * on-chip flow counter which can be used for EEM flows.
36471 * Value of 0 indicates firmware does not support the dynamic allocation of an
36472 * on-chip flow counter.
36474 #define HWRM_CFA_ADV_FLOW_MGNT_QCAPS_OUTPUT_FLAGS_FLOW_COUNTER_ALLOC_SUPPORTED \
36477 * Value of 1 to indicate that firmware supports setting of
36478 * rfs_ring_tbl_idx in HWRM_CFA_NTUPLE_ALLOC command.
36479 * Value of 0 indicates firmware does not support rfs_ring_tbl_idx.
36481 #define HWRM_CFA_ADV_FLOW_MGNT_QCAPS_OUTPUT_FLAGS_RFS_RING_TBL_IDX_SUPPORTED \
36484 * Value of 1 to indicate that firmware supports untagged matching
36485 * criteria on HWRM_CFA_L2_FILTER_ALLOC command. Value of 0
36486 * indicates firmware does not support untagged matching.
36488 #define HWRM_CFA_ADV_FLOW_MGNT_QCAPS_OUTPUT_FLAGS_UNTAGGED_VLAN_SUPPORTED \
36491 * Value of 1 to indicate that firmware supports XDP filter. Value
36492 * of 0 indicates firmware does not support XDP filter.
36494 #define HWRM_CFA_ADV_FLOW_MGNT_QCAPS_OUTPUT_FLAGS_XDP_SUPPORTED \
36497 * Value of 1 to indicate that the firmware support L2 header source
36498 * fields matching criteria on HWRM_CFA_L2_FILTER_ALLOC command.
36499 * Value of 0 indicates firmware does not support L2 header source
36502 #define HWRM_CFA_ADV_FLOW_MGNT_QCAPS_OUTPUT_FLAGS_L2_HEADER_SOURCE_FIELDS_SUPPORTED \
36505 * If set to 1, firmware is capable of supporting ARP ethertype as
36506 * matching criteria for HWRM_CFA_NTUPLE_FILTER_ALLOC command on the
36507 * RX direction. By default, this flag should be 0 for older version
36510 #define HWRM_CFA_ADV_FLOW_MGNT_QCAPS_OUTPUT_FLAGS_NTUPLE_FLOW_RX_ARP_SUPPORTED \
36513 * Value of 1 to indicate that firmware supports setting of
36514 * rfs_ring_tbl_idx in dst_id field of the HWRM_CFA_NTUPLE_ALLOC
36515 * command. Value of 0 indicates firmware does not support
36516 * rfs_ring_tbl_idx in dst_id field.
36518 #define HWRM_CFA_ADV_FLOW_MGNT_QCAPS_OUTPUT_FLAGS_RFS_RING_TBL_IDX_V2_SUPPORTED \
36521 * If set to 1, firmware is capable of supporting IPv4/IPv6 as
36522 * ethertype in HWRM_CFA_NTUPLE_FILTER_ALLOC command on the RX
36523 * direction. By default, this flag should be 0 for older version
36526 #define HWRM_CFA_ADV_FLOW_MGNT_QCAPS_OUTPUT_FLAGS_NTUPLE_FLOW_RX_ETHERTYPE_IP_SUPPORTED \
36528 uint8_t unused_0[3];
36530 * This field is used in Output records to indicate that the output
36531 * is completely written to RAM. This field should be read as '1'
36532 * to indicate that the output has been completely written.
36533 * When writing a command completion or response to an internal processor,
36534 * the order of writes has to be such that this field is written last.
36539 /******************
36541 ******************/
36544 /* hwrm_cfa_tflib_input (size:1024b/128B) */
36545 struct hwrm_cfa_tflib_input {
36546 /* The HWRM command request type. */
36549 * The completion ring to send the completion event on. This should
36550 * be the NQ ID returned from the `nq_alloc` HWRM command.
36552 uint16_t cmpl_ring;
36554 * The sequence ID is used by the driver for tracking multiple
36555 * commands. This ID is treated as opaque data by the firmware and
36556 * the value is returned in the `hwrm_resp_hdr` upon completion.
36560 * The target ID of the command:
36561 * * 0x0-0xFFF8 - The function ID
36562 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
36563 * * 0xFFFD - Reserved for user-space HWRM interface
36566 uint16_t target_id;
36568 * A physical address pointer pointing to a host buffer that the
36569 * command's response data will be written. This can be either a host
36570 * physical address (HPA) or a guest physical address (GPA) and must
36571 * point to a physically contiguous block of memory.
36573 uint64_t resp_addr;
36574 /* TFLIB message type. */
36576 /* TFLIB message subtype. */
36577 uint16_t tf_subtype;
36579 uint8_t unused0[4];
36580 /* TFLIB request data. */
36581 uint32_t tf_req[26];
36584 /* hwrm_cfa_tflib_output (size:5632b/704B) */
36585 struct hwrm_cfa_tflib_output {
36586 /* The specific error status for the command. */
36587 uint16_t error_code;
36588 /* The HWRM command request type. */
36590 /* The sequence ID from the original command. */
36592 /* The length of the response data in number of bytes. */
36594 /* TFLIB message type. */
36596 /* TFLIB message subtype. */
36597 uint16_t tf_subtype;
36598 /* TFLIB response code */
36599 uint32_t tf_resp_code;
36600 /* TFLIB response data. */
36601 uint32_t tf_resp[170];
36603 uint8_t unused1[7];
36605 * This field is used in Output records to indicate that the output
36606 * is completely written to RAM. This field should be read as '1'
36607 * to indicate that the output has been completely written.
36608 * When writing a command completion or response to an internal processor,
36609 * the order of writes has to be such that this field is written last.
36619 /* hwrm_tf_input (size:1024b/128B) */
36620 struct hwrm_tf_input {
36621 /* The HWRM command request type. */
36624 * The completion ring to send the completion event on. This should
36625 * be the NQ ID returned from the `nq_alloc` HWRM command.
36627 uint16_t cmpl_ring;
36629 * The sequence ID is used by the driver for tracking multiple
36630 * commands. This ID is treated as opaque data by the firmware and
36631 * the value is returned in the `hwrm_resp_hdr` upon completion.
36635 * The target ID of the command:
36636 * * 0x0-0xFFF8 - The function ID
36637 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
36638 * * 0xFFFD - Reserved for user-space HWRM interface
36641 uint16_t target_id;
36643 * A physical address pointer pointing to a host buffer that the
36644 * command's response data will be written. This can be either a host
36645 * physical address (HPA) or a guest physical address (GPA) and must
36646 * point to a physically contiguous block of memory.
36648 uint64_t resp_addr;
36649 /* TF message type. */
36651 /* TF message subtype. */
36654 uint8_t unused0[4];
36655 /* TF request data. */
36659 /* hwrm_tf_output (size:5632b/704B) */
36660 struct hwrm_tf_output {
36661 /* The specific error status for the command. */
36662 uint16_t error_code;
36663 /* The HWRM command request type. */
36665 /* The sequence ID from the original command. */
36667 /* The length of the response data in number of bytes. */
36669 /* TF message type. */
36671 /* TF message subtype. */
36673 /* TF response code */
36674 uint32_t resp_code;
36675 /* TF response data. */
36676 uint32_t resp[170];
36678 uint8_t unused1[7];
36680 * This field is used in Output records to indicate that the
36681 * output is completely written to RAM. This field should be
36682 * read as '1' to indicate that the output has been
36683 * completely written. When writing a command completion or
36684 * response to an internal processor, the order of writes has
36685 * to be such that this field is written last.
36690 /***********************
36691 * hwrm_tf_version_get *
36692 ***********************/
36695 /* hwrm_tf_version_get_input (size:128b/16B) */
36696 struct hwrm_tf_version_get_input {
36697 /* The HWRM command request type. */
36700 * The completion ring to send the completion event on. This should
36701 * be the NQ ID returned from the `nq_alloc` HWRM command.
36703 uint16_t cmpl_ring;
36705 * The sequence ID is used by the driver for tracking multiple
36706 * commands. This ID is treated as opaque data by the firmware and
36707 * the value is returned in the `hwrm_resp_hdr` upon completion.
36711 * The target ID of the command:
36712 * * 0x0-0xFFF8 - The function ID
36713 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
36714 * * 0xFFFD - Reserved for user-space HWRM interface
36717 uint16_t target_id;
36719 * A physical address pointer pointing to a host buffer that the
36720 * command's response data will be written. This can be either a host
36721 * physical address (HPA) or a guest physical address (GPA) and must
36722 * point to a physically contiguous block of memory.
36724 uint64_t resp_addr;
36727 /* hwrm_tf_version_get_output (size:128b/16B) */
36728 struct hwrm_tf_version_get_output {
36729 /* The specific error status for the command. */
36730 uint16_t error_code;
36731 /* The HWRM command request type. */
36733 /* The sequence ID from the original command. */
36735 /* The length of the response data in number of bytes. */
36737 /* Version Major number. */
36739 /* Version Minor number. */
36741 /* Version Update number. */
36744 uint8_t unused0[4];
36746 * This field is used in Output records to indicate that the output
36747 * is completely written to RAM. This field should be read as '1'
36748 * to indicate that the output has been completely written.
36749 * When writing a command completion or response to an internal
36750 * processor, the order of writes has to be such that this field is
36756 /************************
36757 * hwrm_tf_session_open *
36758 ************************/
36761 /* hwrm_tf_session_open_input (size:640b/80B) */
36762 struct hwrm_tf_session_open_input {
36763 /* The HWRM command request type. */
36766 * The completion ring to send the completion event on. This should
36767 * be the NQ ID returned from the `nq_alloc` HWRM command.
36769 uint16_t cmpl_ring;
36771 * The sequence ID is used by the driver for tracking multiple
36772 * commands. This ID is treated as opaque data by the firmware and
36773 * the value is returned in the `hwrm_resp_hdr` upon completion.
36777 * The target ID of the command:
36778 * * 0x0-0xFFF8 - The function ID
36779 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
36780 * * 0xFFFD - Reserved for user-space HWRM interface
36783 uint16_t target_id;
36785 * A physical address pointer pointing to a host buffer that the
36786 * command's response data will be written. This can be either a host
36787 * physical address (HPA) or a guest physical address (GPA) and must
36788 * point to a physically contiguous block of memory.
36790 uint64_t resp_addr;
36791 /* Name of the session. */
36792 uint8_t session_name[64];
36795 /* hwrm_tf_session_open_output (size:192b/24B) */
36796 struct hwrm_tf_session_open_output {
36797 /* The specific error status for the command. */
36798 uint16_t error_code;
36799 /* The HWRM command request type. */
36801 /* The sequence ID from the original command. */
36803 /* The length of the response data in number of bytes. */
36806 * Unique session identifier for the session created by the
36809 uint32_t fw_session_id;
36811 * Unique session client identifier for the first client on
36812 * the newly created session.
36814 uint32_t fw_session_client_id;
36818 uint8_t unused1[3];
36820 * This field is used in Output records to indicate that the output
36821 * is completely written to RAM. This field should be read as '1'
36822 * to indicate that the output has been completely written.
36823 * When writing a command completion or response to an internal
36824 * processor, the order of writes has to be such that this field is
36830 /**************************
36831 * hwrm_tf_session_attach *
36832 **************************/
36835 /* hwrm_tf_session_attach_input (size:704b/88B) */
36836 struct hwrm_tf_session_attach_input {
36837 /* The HWRM command request type. */
36840 * The completion ring to send the completion event on. This should
36841 * be the NQ ID returned from the `nq_alloc` HWRM command.
36843 uint16_t cmpl_ring;
36845 * The sequence ID is used by the driver for tracking multiple
36846 * commands. This ID is treated as opaque data by the firmware and
36847 * the value is returned in the `hwrm_resp_hdr` upon completion.
36851 * The target ID of the command:
36852 * * 0x0-0xFFF8 - The function ID
36853 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
36854 * * 0xFFFD - Reserved for user-space HWRM interface
36857 uint16_t target_id;
36859 * A physical address pointer pointing to a host buffer that the
36860 * command's response data will be written. This can be either a host
36861 * physical address (HPA) or a guest physical address (GPA) and must
36862 * point to a physically contiguous block of memory.
36864 uint64_t resp_addr;
36866 * Unique session identifier for the session that the attach
36867 * request want to attach to. This value originates from the
36868 * shared session memory that the attach request opened by
36869 * way of the 'attach name' that was passed in to the core
36871 * The fw_session_id of the attach session includes PCIe bus
36872 * info to distinguish the PF and session info to identify
36873 * the associated TruFlow session.
36875 uint32_t attach_fw_session_id;
36878 /* Name of the session it self. */
36879 uint8_t session_name[64];
36882 /* hwrm_tf_session_attach_output (size:128b/16B) */
36883 struct hwrm_tf_session_attach_output {
36884 /* The specific error status for the command. */
36885 uint16_t error_code;
36886 /* The HWRM command request type. */
36888 /* The sequence ID from the original command. */
36890 /* The length of the response data in number of bytes. */
36893 * Unique session identifier for the session created by the
36894 * firmware. It includes PCIe bus info to distinguish the PF
36895 * and session info to identify the associated TruFlow
36896 * session. This fw_session_id is unique to the attach
36899 uint32_t fw_session_id;
36901 uint8_t unused0[3];
36903 * This field is used in Output records to indicate that the output
36904 * is completely written to RAM. This field should be read as '1'
36905 * to indicate that the output has been completely written.
36906 * When writing a command completion or response to an internal
36907 * processor, the order of writes has to be such that this field is
36913 /****************************
36914 * hwrm_tf_session_register *
36915 ****************************/
36918 /* hwrm_tf_session_register_input (size:704b/88B) */
36919 struct hwrm_tf_session_register_input {
36920 /* The HWRM command request type. */
36923 * The completion ring to send the completion event on. This should
36924 * be the NQ ID returned from the `nq_alloc` HWRM command.
36926 uint16_t cmpl_ring;
36928 * The sequence ID is used by the driver for tracking multiple
36929 * commands. This ID is treated as opaque data by the firmware and
36930 * the value is returned in the `hwrm_resp_hdr` upon completion.
36934 * The target ID of the command:
36935 * * 0x0-0xFFF8 - The function ID
36936 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
36937 * * 0xFFFD - Reserved for user-space HWRM interface
36940 uint16_t target_id;
36942 * A physical address pointer pointing to a host buffer that the
36943 * command's response data will be written. This can be either a host
36944 * physical address (HPA) or a guest physical address (GPA) and must
36945 * point to a physically contiguous block of memory.
36947 uint64_t resp_addr;
36949 * Unique session identifier for the session that the
36950 * register request want to create a new client on. This
36951 * value originates from the first open request.
36952 * The fw_session_id of the attach session includes PCIe bus
36953 * info to distinguish the PF and session info to identify
36954 * the associated TruFlow session.
36956 uint32_t fw_session_id;
36959 /* Name of the session client. */
36960 uint8_t session_client_name[64];
36963 /* hwrm_tf_session_register_output (size:128b/16B) */
36964 struct hwrm_tf_session_register_output {
36965 /* The specific error status for the command. */
36966 uint16_t error_code;
36967 /* The HWRM command request type. */
36969 /* The sequence ID from the original command. */
36971 /* The length of the response data in number of bytes. */
36974 * Unique session client identifier for the session created
36975 * by the firmware. It includes the session the client it
36976 * attached to and session client info.
36978 uint32_t fw_session_client_id;
36980 uint8_t unused0[3];
36982 * This field is used in Output records to indicate that the output
36983 * is completely written to RAM. This field should be read as '1'
36984 * to indicate that the output has been completely written.
36985 * When writing a command completion or response to an internal
36986 * processor, the order of writes has to be such that this field is
36992 /******************************
36993 * hwrm_tf_session_unregister *
36994 ******************************/
36997 /* hwrm_tf_session_unregister_input (size:192b/24B) */
36998 struct hwrm_tf_session_unregister_input {
36999 /* The HWRM command request type. */
37002 * The completion ring to send the completion event on. This should
37003 * be the NQ ID returned from the `nq_alloc` HWRM command.
37005 uint16_t cmpl_ring;
37007 * The sequence ID is used by the driver for tracking multiple
37008 * commands. This ID is treated as opaque data by the firmware and
37009 * the value is returned in the `hwrm_resp_hdr` upon completion.
37013 * The target ID of the command:
37014 * * 0x0-0xFFF8 - The function ID
37015 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
37016 * * 0xFFFD - Reserved for user-space HWRM interface
37019 uint16_t target_id;
37021 * A physical address pointer pointing to a host buffer that the
37022 * command's response data will be written. This can be either a host
37023 * physical address (HPA) or a guest physical address (GPA) and must
37024 * point to a physically contiguous block of memory.
37026 uint64_t resp_addr;
37028 * Unique session identifier for the session that the
37029 * unregister request want to close a session client on.
37031 uint32_t fw_session_id;
37033 * Unique session client identifier for the session that the
37034 * unregister request want to close.
37036 uint32_t fw_session_client_id;
37039 /* hwrm_tf_session_unregister_output (size:128b/16B) */
37040 struct hwrm_tf_session_unregister_output {
37041 /* The specific error status for the command. */
37042 uint16_t error_code;
37043 /* The HWRM command request type. */
37045 /* The sequence ID from the original command. */
37047 /* The length of the response data in number of bytes. */
37050 uint8_t unused0[7];
37052 * This field is used in Output records to indicate that the output
37053 * is completely written to RAM. This field should be read as '1'
37054 * to indicate that the output has been completely written.
37055 * When writing a command completion or response to an internal
37056 * processor, the order of writes has to be such that this field is
37062 /*************************
37063 * hwrm_tf_session_close *
37064 *************************/
37067 /* hwrm_tf_session_close_input (size:192b/24B) */
37068 struct hwrm_tf_session_close_input {
37069 /* The HWRM command request type. */
37072 * The completion ring to send the completion event on. This should
37073 * be the NQ ID returned from the `nq_alloc` HWRM command.
37075 uint16_t cmpl_ring;
37077 * The sequence ID is used by the driver for tracking multiple
37078 * commands. This ID is treated as opaque data by the firmware and
37079 * the value is returned in the `hwrm_resp_hdr` upon completion.
37083 * The target ID of the command:
37084 * * 0x0-0xFFF8 - The function ID
37085 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
37086 * * 0xFFFD - Reserved for user-space HWRM interface
37089 uint16_t target_id;
37091 * A physical address pointer pointing to a host buffer that the
37092 * command's response data will be written. This can be either a host
37093 * physical address (HPA) or a guest physical address (GPA) and must
37094 * point to a physically contiguous block of memory.
37096 uint64_t resp_addr;
37097 /* Firmware session id returned when HWRM_TF_SESSION_OPEN is sent. */
37098 uint32_t fw_session_id;
37100 uint8_t unused0[4];
37103 /* hwrm_tf_session_close_output (size:128b/16B) */
37104 struct hwrm_tf_session_close_output {
37105 /* The specific error status for the command. */
37106 uint16_t error_code;
37107 /* The HWRM command request type. */
37109 /* The sequence ID from the original command. */
37111 /* The length of the response data in number of bytes. */
37114 uint8_t unused0[7];
37116 * This field is used in Output records to indicate that the output
37117 * is completely written to RAM. This field should be read as '1'
37118 * to indicate that the output has been completely written.
37119 * When writing a command completion or response to an internal
37120 * processor, the order of writes has to be such that this field
37126 /************************
37127 * hwrm_tf_session_qcfg *
37128 ************************/
37131 /* hwrm_tf_session_qcfg_input (size:192b/24B) */
37132 struct hwrm_tf_session_qcfg_input {
37133 /* The HWRM command request type. */
37136 * The completion ring to send the completion event on. This should
37137 * be the NQ ID returned from the `nq_alloc` HWRM command.
37139 uint16_t cmpl_ring;
37141 * The sequence ID is used by the driver for tracking multiple
37142 * commands. This ID is treated as opaque data by the firmware and
37143 * the value is returned in the `hwrm_resp_hdr` upon completion.
37147 * The target ID of the command:
37148 * * 0x0-0xFFF8 - The function ID
37149 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
37150 * * 0xFFFD - Reserved for user-space HWRM interface
37153 uint16_t target_id;
37155 * A physical address pointer pointing to a host buffer that the
37156 * command's response data will be written. This can be either a host
37157 * physical address (HPA) or a guest physical address (GPA) and must
37158 * point to a physically contiguous block of memory.
37160 uint64_t resp_addr;
37161 /* Firmware session id returned when HWRM_TF_SESSION_OPEN is sent. */
37162 uint32_t fw_session_id;
37164 uint8_t unused0[4];
37167 /* hwrm_tf_session_qcfg_output (size:128b/16B) */
37168 struct hwrm_tf_session_qcfg_output {
37169 /* The specific error status for the command. */
37170 uint16_t error_code;
37171 /* The HWRM command request type. */
37173 /* The sequence ID from the original command. */
37175 /* The length of the response data in number of bytes. */
37177 /* RX action control settings flags. */
37178 uint8_t rx_act_flags;
37180 * A value of 1 in this field indicates that Global Flow ID
37181 * reporting into cfa_code and cfa_metadata is enabled.
37183 #define HWRM_TF_SESSION_QCFG_OUTPUT_RX_ACT_FLAGS_ABCR_GFID_EN \
37186 * A value of 1 in this field indicates that both inner and outer
37187 * are stripped and inner tag is passed.
37190 #define HWRM_TF_SESSION_QCFG_OUTPUT_RX_ACT_FLAGS_ABCR_VTAG_DLT_BOTH \
37193 * A value of 1 in this field indicates that the re-use of
37194 * existing tunnel L2 header SMAC is enabled for
37195 * Non-tunnel L2, L2-L3 and IP-IP tunnel.
37197 #define HWRM_TF_SESSION_QCFG_OUTPUT_RX_ACT_FLAGS_TECT_SMAC_OVR_RUTNSL2 \
37199 /* TX Action control settings flags. */
37200 uint8_t tx_act_flags;
37202 #define HWRM_TF_SESSION_QCFG_OUTPUT_TX_ACT_FLAGS_ABCR_VEB_EN \
37205 * When set to 1 any GRE tunnels will include the
37206 * optional Key field.
37208 #define HWRM_TF_SESSION_QCFG_OUTPUT_TX_ACT_FLAGS_TECT_GRE_SET_K \
37211 * When set to 1, for GRE tunnels, the IPV6 Traffic Class (TC)
37212 * field of the outer header is inherited from the inner header
37213 * (if present) or the fixed value as taken from the encap
37216 #define HWRM_TF_SESSION_QCFG_OUTPUT_TX_ACT_FLAGS_TECT_IPV6_TC_IH \
37219 * When set to 1, for GRE tunnels, the IPV4 Type Of Service (TOS)
37220 * field of the outer header is inherited from the inner header
37221 * (if present) or the fixed value as taken from the encap record.
37223 #define HWRM_TF_SESSION_QCFG_OUTPUT_TX_ACT_FLAGS_TECT_IPV4_TOS_IH \
37226 uint8_t unused0[5];
37228 * This field is used in Output records to indicate that the output
37229 * is completely written to RAM. This field should be read as '1'
37230 * to indicate that the output has been completely written.
37231 * When writing a command completion or response to an internal
37232 * processor, the order of writes has to be such that this field
37238 /******************************
37239 * hwrm_tf_session_resc_qcaps *
37240 ******************************/
37243 /* hwrm_tf_session_resc_qcaps_input (size:256b/32B) */
37244 struct hwrm_tf_session_resc_qcaps_input {
37245 /* The HWRM command request type. */
37248 * The completion ring to send the completion event on. This should
37249 * be the NQ ID returned from the `nq_alloc` HWRM command.
37251 uint16_t cmpl_ring;
37253 * The sequence ID is used by the driver for tracking multiple
37254 * commands. This ID is treated as opaque data by the firmware and
37255 * the value is returned in the `hwrm_resp_hdr` upon completion.
37259 * The target ID of the command:
37260 * * 0x0-0xFFF8 - The function ID
37261 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
37262 * * 0xFFFD - Reserved for user-space HWRM interface
37265 uint16_t target_id;
37267 * A physical address pointer pointing to a host buffer that the
37268 * command's response data will be written. This can be either a host
37269 * physical address (HPA) or a guest physical address (GPA) and must
37270 * point to a physically contiguous block of memory.
37272 uint64_t resp_addr;
37273 /* Firmware session id returned when HWRM_TF_SESSION_OPEN is sent. */
37274 uint32_t fw_session_id;
37275 /* Control flags. */
37277 /* Indicates the flow direction. */
37278 #define HWRM_TF_SESSION_RESC_QCAPS_INPUT_FLAGS_DIR UINT32_C(0x1)
37279 /* If this bit set to 0, then it indicates rx flow. */
37280 #define HWRM_TF_SESSION_RESC_QCAPS_INPUT_FLAGS_DIR_RX UINT32_C(0x0)
37281 /* If this bit is set to 1, then it indicates that tx flow. */
37282 #define HWRM_TF_SESSION_RESC_QCAPS_INPUT_FLAGS_DIR_TX UINT32_C(0x1)
37283 #define HWRM_TF_SESSION_RESC_QCAPS_INPUT_FLAGS_DIR_LAST \
37284 HWRM_TF_SESSION_RESC_QCAPS_INPUT_FLAGS_DIR_TX
37286 * Defines the size of the provided qcaps_addr array
37287 * buffer. The size should be set to the Resource Manager
37288 * provided max number of qcaps entries which is device
37289 * specific. Resource Manager gets the max size from HCAPI
37292 uint16_t qcaps_size;
37294 * This is the DMA address for the qcaps output data array
37295 * buffer. Array is of tf_rm_resc_req_entry type and is
37298 uint64_t qcaps_addr;
37301 /* hwrm_tf_session_resc_qcaps_output (size:192b/24B) */
37302 struct hwrm_tf_session_resc_qcaps_output {
37303 /* The specific error status for the command. */
37304 uint16_t error_code;
37305 /* The HWRM command request type. */
37307 /* The sequence ID from the original command. */
37309 /* The length of the response data in number of bytes. */
37311 /* Control flags. */
37313 /* Session reservation strategy. */
37314 #define HWRM_TF_SESSION_RESC_QCAPS_OUTPUT_FLAGS_SESS_RESV_STRATEGY_MASK \
37316 #define HWRM_TF_SESSION_RESC_QCAPS_OUTPUT_FLAGS_SESS_RESV_STRATEGY_SFT \
37318 /* Static partitioning. */
37319 #define HWRM_TF_SESSION_RESC_QCAPS_OUTPUT_FLAGS_SESS_RESV_STRATEGY_STATIC \
37322 #define HWRM_TF_SESSION_RESC_QCAPS_OUTPUT_FLAGS_SESS_RESV_STRATEGY_1 \
37325 #define HWRM_TF_SESSION_RESC_QCAPS_OUTPUT_FLAGS_SESS_RESV_STRATEGY_2 \
37328 #define HWRM_TF_SESSION_RESC_QCAPS_OUTPUT_FLAGS_SESS_RESV_STRATEGY_3 \
37330 #define HWRM_TF_SESSION_RESC_QCAPS_OUTPUT_FLAGS_SESS_RESV_STRATEGY_LAST \
37331 HWRM_TF_SESSION_RESC_QCAPS_OUTPUT_FLAGS_SESS_RESV_STRATEGY_3
37333 * Size of the returned qcaps_addr data array buffer. The
37334 * value cannot exceed the size defined by the input msg,
37341 uint8_t unused1[7];
37343 * This field is used in Output records to indicate that the output
37344 * is completely written to RAM. This field should be read as '1'
37345 * to indicate that the output has been completely written.
37346 * When writing a command completion or response to an internal
37347 * processor, the order of writes has to be such that this field is
37353 /******************************
37354 * hwrm_tf_session_resc_alloc *
37355 ******************************/
37358 /* hwrm_tf_session_resc_alloc_input (size:320b/40B) */
37359 struct hwrm_tf_session_resc_alloc_input {
37360 /* The HWRM command request type. */
37363 * The completion ring to send the completion event on. This should
37364 * be the NQ ID returned from the `nq_alloc` HWRM command.
37366 uint16_t cmpl_ring;
37368 * The sequence ID is used by the driver for tracking multiple
37369 * commands. This ID is treated as opaque data by the firmware and
37370 * the value is returned in the `hwrm_resp_hdr` upon completion.
37374 * The target ID of the command:
37375 * * 0x0-0xFFF8 - The function ID
37376 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
37377 * * 0xFFFD - Reserved for user-space HWRM interface
37380 uint16_t target_id;
37382 * A physical address pointer pointing to a host buffer that the
37383 * command's response data will be written. This can be either a host
37384 * physical address (HPA) or a guest physical address (GPA) and must
37385 * point to a physically contiguous block of memory.
37387 uint64_t resp_addr;
37388 /* Firmware session id returned when HWRM_TF_SESSION_OPEN is sent. */
37389 uint32_t fw_session_id;
37390 /* Control flags. */
37392 /* Indicates the flow direction. */
37393 #define HWRM_TF_SESSION_RESC_ALLOC_INPUT_FLAGS_DIR UINT32_C(0x1)
37394 /* If this bit set to 0, then it indicates rx flow. */
37395 #define HWRM_TF_SESSION_RESC_ALLOC_INPUT_FLAGS_DIR_RX UINT32_C(0x0)
37396 /* If this bit is set to 1, then it indicates that tx flow. */
37397 #define HWRM_TF_SESSION_RESC_ALLOC_INPUT_FLAGS_DIR_TX UINT32_C(0x1)
37398 #define HWRM_TF_SESSION_RESC_ALLOC_INPUT_FLAGS_DIR_LAST \
37399 HWRM_TF_SESSION_RESC_ALLOC_INPUT_FLAGS_DIR_TX
37401 * Defines the array size of the provided req_addr and
37402 * resv_addr array buffers. Should be set to the number of
37407 * This is the DMA address for the request input data array
37408 * buffer. Array is of tf_rm_resc_req_entry type. Size of the
37409 * array buffer is provided by the 'req_size' field in this
37414 * This is the DMA address for the resc output data array
37415 * buffer. Array is of tf_rm_resc_entry type. Size of the array
37416 * buffer is provided by the 'req_size' field in this
37419 uint64_t resc_addr;
37422 /* hwrm_tf_session_resc_alloc_output (size:128b/16B) */
37423 struct hwrm_tf_session_resc_alloc_output {
37424 /* The specific error status for the command. */
37425 uint16_t error_code;
37426 /* The HWRM command request type. */
37428 /* The sequence ID from the original command. */
37430 /* The length of the response data in number of bytes. */
37433 * Size of the returned tf_rm_resc_entry data array. The value
37434 * cannot exceed the req_size defined by the input msg. The data
37435 * array is returned using the resv_addr specified DMA
37436 * address also provided by the input msg.
37440 uint8_t unused0[5];
37442 * This field is used in Output records to indicate that the output
37443 * is completely written to RAM. This field should be read as '1'
37444 * to indicate that the output has been completely written.
37445 * When writing a command completion or response to an internal
37446 * processor, the order of writes has to be such that this field is
37452 /*****************************
37453 * hwrm_tf_session_resc_free *
37454 *****************************/
37457 /* hwrm_tf_session_resc_free_input (size:256b/32B) */
37458 struct hwrm_tf_session_resc_free_input {
37459 /* The HWRM command request type. */
37462 * The completion ring to send the completion event on. This should
37463 * be the NQ ID returned from the `nq_alloc` HWRM command.
37465 uint16_t cmpl_ring;
37467 * The sequence ID is used by the driver for tracking multiple
37468 * commands. This ID is treated as opaque data by the firmware and
37469 * the value is returned in the `hwrm_resp_hdr` upon completion.
37473 * The target ID of the command:
37474 * * 0x0-0xFFF8 - The function ID
37475 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
37476 * * 0xFFFD - Reserved for user-space HWRM interface
37479 uint16_t target_id;
37481 * A physical address pointer pointing to a host buffer that the
37482 * command's response data will be written. This can be either a host
37483 * physical address (HPA) or a guest physical address (GPA) and must
37484 * point to a physically contiguous block of memory.
37486 uint64_t resp_addr;
37487 /* Firmware session id returned when HWRM_TF_SESSION_OPEN is sent. */
37488 uint32_t fw_session_id;
37489 /* Control flags. */
37491 /* Indicates the flow direction. */
37492 #define HWRM_TF_SESSION_RESC_FREE_INPUT_FLAGS_DIR UINT32_C(0x1)
37493 /* If this bit set to 0, then it indicates rx flow. */
37494 #define HWRM_TF_SESSION_RESC_FREE_INPUT_FLAGS_DIR_RX UINT32_C(0x0)
37495 /* If this bit is set to 1, then it indicates that tx flow. */
37496 #define HWRM_TF_SESSION_RESC_FREE_INPUT_FLAGS_DIR_TX UINT32_C(0x1)
37497 #define HWRM_TF_SESSION_RESC_FREE_INPUT_FLAGS_DIR_LAST \
37498 HWRM_TF_SESSION_RESC_FREE_INPUT_FLAGS_DIR_TX
37500 * Defines the size, in bytes, of the provided free_addr
37503 uint16_t free_size;
37505 * This is the DMA address for the free input data array
37506 * buffer. Array is of tf_rm_resc_entry type. Size of the
37507 * buffer is provided by the 'free_size' field of this
37510 uint64_t free_addr;
37513 /* hwrm_tf_session_resc_free_output (size:128b/16B) */
37514 struct hwrm_tf_session_resc_free_output {
37515 /* The specific error status for the command. */
37516 uint16_t error_code;
37517 /* The HWRM command request type. */
37519 /* The sequence ID from the original command. */
37521 /* The length of the response data in number of bytes. */
37524 uint8_t unused0[7];
37526 * This field is used in Output records to indicate that the output
37527 * is completely written to RAM. This field should be read as '1'
37528 * to indicate that the output has been completely written.
37529 * When writing a command completion or response to an internal
37530 * processor, the order of writes has to be such that this field is
37536 /******************************
37537 * hwrm_tf_session_resc_flush *
37538 ******************************/
37541 /* hwrm_tf_session_resc_flush_input (size:256b/32B) */
37542 struct hwrm_tf_session_resc_flush_input {
37543 /* The HWRM command request type. */
37546 * The completion ring to send the completion event on. This should
37547 * be the NQ ID returned from the `nq_alloc` HWRM command.
37549 uint16_t cmpl_ring;
37551 * The sequence ID is used by the driver for tracking multiple
37552 * commands. This ID is treated as opaque data by the firmware and
37553 * the value is returned in the `hwrm_resp_hdr` upon completion.
37557 * The target ID of the command:
37558 * * 0x0-0xFFF8 - The function ID
37559 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
37560 * * 0xFFFD - Reserved for user-space HWRM interface
37563 uint16_t target_id;
37565 * A physical address pointer pointing to a host buffer that the
37566 * command's response data will be written. This can be either a host
37567 * physical address (HPA) or a guest physical address (GPA) and must
37568 * point to a physically contiguous block of memory.
37570 uint64_t resp_addr;
37571 /* Firmware session id returned when HWRM_TF_SESSION_OPEN is sent. */
37572 uint32_t fw_session_id;
37573 /* Control flags. */
37575 /* Indicates the flow direction. */
37576 #define HWRM_TF_SESSION_RESC_FLUSH_INPUT_FLAGS_DIR UINT32_C(0x1)
37577 /* If this bit set to 0, then it indicates rx flow. */
37578 #define HWRM_TF_SESSION_RESC_FLUSH_INPUT_FLAGS_DIR_RX UINT32_C(0x0)
37579 /* If this bit is set to 1, then it indicates that tx flow. */
37580 #define HWRM_TF_SESSION_RESC_FLUSH_INPUT_FLAGS_DIR_TX UINT32_C(0x1)
37581 #define HWRM_TF_SESSION_RESC_FLUSH_INPUT_FLAGS_DIR_LAST \
37582 HWRM_TF_SESSION_RESC_FLUSH_INPUT_FLAGS_DIR_TX
37584 * Defines the size, in bytes, of the provided flush_addr
37587 uint16_t flush_size;
37589 * This is the DMA address for the flush input data array
37590 * buffer. Array of tf_rm_resc_entry type. Size of the
37591 * buffer is provided by the 'flush_size' field in this
37594 uint64_t flush_addr;
37597 /* hwrm_tf_session_resc_flush_output (size:128b/16B) */
37598 struct hwrm_tf_session_resc_flush_output {
37599 /* The specific error status for the command. */
37600 uint16_t error_code;
37601 /* The HWRM command request type. */
37603 /* The sequence ID from the original command. */
37605 /* The length of the response data in number of bytes. */
37608 uint8_t unused0[7];
37610 * This field is used in Output records to indicate that the output
37611 * is completely written to RAM. This field should be read as '1'
37612 * to indicate that the output has been completely written.
37613 * When writing a command completion or response to an internal
37614 * processor, the order of writes has to be such that this field is
37620 /* TruFlow RM capability of a resource. */
37621 /* tf_rm_resc_req_entry (size:64b/8B) */
37622 struct tf_rm_resc_req_entry {
37623 /* Type of the resource, defined globally in HCAPI RM. */
37625 /* Minimum value. */
37627 /* Maximum value. */
37631 /* TruFlow RM reservation information. */
37632 /* tf_rm_resc_entry (size:64b/8B) */
37633 struct tf_rm_resc_entry {
37634 /* Type of the resource, defined globally in HCAPI RM. */
37636 /* Start offset. */
37638 /* Number of resources. */
37642 /************************
37643 * hwrm_tf_tbl_type_get *
37644 ************************/
37647 /* hwrm_tf_tbl_type_get_input (size:256b/32B) */
37648 struct hwrm_tf_tbl_type_get_input {
37649 /* The HWRM command request type. */
37652 * The completion ring to send the completion event on. This should
37653 * be the NQ ID returned from the `nq_alloc` HWRM command.
37655 uint16_t cmpl_ring;
37657 * The sequence ID is used by the driver for tracking multiple
37658 * commands. This ID is treated as opaque data by the firmware and
37659 * the value is returned in the `hwrm_resp_hdr` upon completion.
37663 * The target ID of the command:
37664 * * 0x0-0xFFF8 - The function ID
37665 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
37666 * * 0xFFFD - Reserved for user-space HWRM interface
37669 uint16_t target_id;
37671 * A physical address pointer pointing to a host buffer that the
37672 * command's response data will be written. This can be either a host
37673 * physical address (HPA) or a guest physical address (GPA) and must
37674 * point to a physically contiguous block of memory.
37676 uint64_t resp_addr;
37677 /* Firmware session id returned when HWRM_TF_SESSION_OPEN is sent. */
37678 uint32_t fw_session_id;
37679 /* Control flags. */
37681 /* Indicates the flow direction. */
37682 #define HWRM_TF_TBL_TYPE_GET_INPUT_FLAGS_DIR UINT32_C(0x1)
37683 /* If this bit set to 0, then it indicates rx flow. */
37684 #define HWRM_TF_TBL_TYPE_GET_INPUT_FLAGS_DIR_RX UINT32_C(0x0)
37685 /* If this bit is set to 1, then it indicates that tx flow. */
37686 #define HWRM_TF_TBL_TYPE_GET_INPUT_FLAGS_DIR_TX UINT32_C(0x1)
37687 #define HWRM_TF_TBL_TYPE_GET_INPUT_FLAGS_DIR_LAST \
37688 HWRM_TF_TBL_TYPE_GET_INPUT_FLAGS_DIR_TX
37690 uint8_t unused0[2];
37692 * Type of the resource, defined globally in the
37693 * hwrm_tf_resc_type enum.
37696 /* Index of the type to retrieve. */
37700 /* hwrm_tf_tbl_type_get_output (size:1216b/152B) */
37701 struct hwrm_tf_tbl_type_get_output {
37702 /* The specific error status for the command. */
37703 uint16_t error_code;
37704 /* The HWRM command request type. */
37706 /* The sequence ID from the original command. */
37708 /* The length of the response data in number of bytes. */
37710 /* Response code. */
37711 uint32_t resp_code;
37712 /* Response size. */
37716 /* Response data. */
37719 uint8_t unused1[7];
37721 * This field is used in Output records to indicate that the output
37722 * is completely written to RAM. This field should be read as '1'
37723 * to indicate that the output has been completely written.
37724 * When writing a command completion or response to an internal
37725 * processor, the order of writes has to be such that this field
37731 /************************
37732 * hwrm_tf_tbl_type_set *
37733 ************************/
37736 /* hwrm_tf_tbl_type_set_input (size:1024b/128B) */
37737 struct hwrm_tf_tbl_type_set_input {
37738 /* The HWRM command request type. */
37741 * The completion ring to send the completion event on. This should
37742 * be the NQ ID returned from the `nq_alloc` HWRM command.
37744 uint16_t cmpl_ring;
37746 * The sequence ID is used by the driver for tracking multiple
37747 * commands. This ID is treated as opaque data by the firmware and
37748 * the value is returned in the `hwrm_resp_hdr` upon completion.
37752 * The target ID of the command:
37753 * * 0x0-0xFFF8 - The function ID
37754 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
37755 * * 0xFFFD - Reserved for user-space HWRM interface
37758 uint16_t target_id;
37760 * A physical address pointer pointing to a host buffer that the
37761 * command's response data will be written. This can be either a host
37762 * physical address (HPA) or a guest physical address (GPA) and must
37763 * point to a physically contiguous block of memory.
37765 uint64_t resp_addr;
37766 /* Firmware session id returned when HWRM_TF_SESSION_OPEN is sent. */
37767 uint32_t fw_session_id;
37768 /* Control flags. */
37770 /* Indicates the flow direction. */
37771 #define HWRM_TF_TBL_TYPE_SET_INPUT_FLAGS_DIR UINT32_C(0x1)
37772 /* If this bit set to 0, then it indicates rx flow. */
37773 #define HWRM_TF_TBL_TYPE_SET_INPUT_FLAGS_DIR_RX UINT32_C(0x0)
37774 /* If this bit is set to 1, then it indicates that tx flow. */
37775 #define HWRM_TF_TBL_TYPE_SET_INPUT_FLAGS_DIR_TX UINT32_C(0x1)
37776 #define HWRM_TF_TBL_TYPE_SET_INPUT_FLAGS_DIR_LAST \
37777 HWRM_TF_TBL_TYPE_SET_INPUT_FLAGS_DIR_TX
37779 uint8_t unused0[2];
37781 * Type of the resource, defined globally in the
37782 * hwrm_tf_resc_type enum.
37785 /* Index of the type to retrieve. */
37787 /* Size of the data to set. */
37790 uint8_t unused1[6];
37791 /* Data to be set. */
37795 /* hwrm_tf_tbl_type_set_output (size:128b/16B) */
37796 struct hwrm_tf_tbl_type_set_output {
37797 /* The specific error status for the command. */
37798 uint16_t error_code;
37799 /* The HWRM command request type. */
37801 /* The sequence ID from the original command. */
37803 /* The length of the response data in number of bytes. */
37806 uint8_t unused0[7];
37808 * This field is used in Output records to indicate that the output
37809 * is completely written to RAM. This field should be read as '1'
37810 * to indicate that the output has been completely written.
37811 * When writing a command completion or response to an internal
37812 * processor, the order of writes has to be such that this field
37818 /*************************
37819 * hwrm_tf_ctxt_mem_rgtr *
37820 *************************/
37823 /* hwrm_tf_ctxt_mem_rgtr_input (size:256b/32B) */
37824 struct hwrm_tf_ctxt_mem_rgtr_input {
37825 /* The HWRM command request type. */
37828 * The completion ring to send the completion event on. This should
37829 * be the NQ ID returned from the `nq_alloc` HWRM command.
37831 uint16_t cmpl_ring;
37833 * The sequence ID is used by the driver for tracking multiple
37834 * commands. This ID is treated as opaque data by the firmware and
37835 * the value is returned in the `hwrm_resp_hdr` upon completion.
37839 * The target ID of the command:
37840 * * 0x0-0xFFF8 - The function ID
37841 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
37842 * * 0xFFFD - Reserved for user-space HWRM interface
37845 uint16_t target_id;
37847 * A physical address pointer pointing to a host buffer that the
37848 * command's response data will be written. This can be either a host
37849 * physical address (HPA) or a guest physical address (GPA) and must
37850 * point to a physically contiguous block of memory.
37852 uint64_t resp_addr;
37853 /* Control flags. */
37855 /* Counter PBL indirect levels. */
37856 uint8_t page_level;
37857 /* PBL pointer is physical start address. */
37858 #define HWRM_TF_CTXT_MEM_RGTR_INPUT_PAGE_LEVEL_LVL_0 UINT32_C(0x0)
37859 /* PBL pointer points to PTE table. */
37860 #define HWRM_TF_CTXT_MEM_RGTR_INPUT_PAGE_LEVEL_LVL_1 UINT32_C(0x1)
37862 * PBL pointer points to PDE table with each entry pointing
37865 #define HWRM_TF_CTXT_MEM_RGTR_INPUT_PAGE_LEVEL_LVL_2 UINT32_C(0x2)
37866 #define HWRM_TF_CTXT_MEM_RGTR_INPUT_PAGE_LEVEL_LAST \
37867 HWRM_TF_CTXT_MEM_RGTR_INPUT_PAGE_LEVEL_LVL_2
37870 /* 4KB page size. */
37871 #define HWRM_TF_CTXT_MEM_RGTR_INPUT_PAGE_SIZE_4K UINT32_C(0x0)
37872 /* 8KB page size. */
37873 #define HWRM_TF_CTXT_MEM_RGTR_INPUT_PAGE_SIZE_8K UINT32_C(0x1)
37874 /* 64KB page size. */
37875 #define HWRM_TF_CTXT_MEM_RGTR_INPUT_PAGE_SIZE_64K UINT32_C(0x4)
37876 /* 256KB page size. */
37877 #define HWRM_TF_CTXT_MEM_RGTR_INPUT_PAGE_SIZE_256K UINT32_C(0x6)
37878 /* 1MB page size. */
37879 #define HWRM_TF_CTXT_MEM_RGTR_INPUT_PAGE_SIZE_1M UINT32_C(0x8)
37880 /* 2MB page size. */
37881 #define HWRM_TF_CTXT_MEM_RGTR_INPUT_PAGE_SIZE_2M UINT32_C(0x9)
37882 /* 4MB page size. */
37883 #define HWRM_TF_CTXT_MEM_RGTR_INPUT_PAGE_SIZE_4M UINT32_C(0xa)
37884 /* 1GB page size. */
37885 #define HWRM_TF_CTXT_MEM_RGTR_INPUT_PAGE_SIZE_1G UINT32_C(0x12)
37886 #define HWRM_TF_CTXT_MEM_RGTR_INPUT_PAGE_SIZE_LAST \
37887 HWRM_TF_CTXT_MEM_RGTR_INPUT_PAGE_SIZE_1G
37890 /* Pointer to the PBL, or PDL depending on number of levels */
37894 /* hwrm_tf_ctxt_mem_rgtr_output (size:128b/16B) */
37895 struct hwrm_tf_ctxt_mem_rgtr_output {
37896 /* The specific error status for the command. */
37897 uint16_t error_code;
37898 /* The HWRM command request type. */
37900 /* The sequence ID from the original command. */
37902 /* The length of the response data in number of bytes. */
37905 * Id/Handle to the recently register context memory. This
37906 * handle is passed to the TF session.
37910 uint8_t unused0[5];
37912 * This field is used in Output records to indicate that the
37913 * output is completely written to RAM. This field should be
37914 * read as '1' to indicate that the output has been
37915 * completely written. When writing a command completion or
37916 * response to an internal processor, the order of writes has
37917 * to be such that this field is written last.
37922 /***************************
37923 * hwrm_tf_ctxt_mem_unrgtr *
37924 ***************************/
37927 /* hwrm_tf_ctxt_mem_unrgtr_input (size:192b/24B) */
37928 struct hwrm_tf_ctxt_mem_unrgtr_input {
37929 /* The HWRM command request type. */
37932 * The completion ring to send the completion event on. This should
37933 * be the NQ ID returned from the `nq_alloc` HWRM command.
37935 uint16_t cmpl_ring;
37937 * The sequence ID is used by the driver for tracking multiple
37938 * commands. This ID is treated as opaque data by the firmware and
37939 * the value is returned in the `hwrm_resp_hdr` upon completion.
37943 * The target ID of the command:
37944 * * 0x0-0xFFF8 - The function ID
37945 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
37946 * * 0xFFFD - Reserved for user-space HWRM interface
37949 uint16_t target_id;
37951 * A physical address pointer pointing to a host buffer that the
37952 * command's response data will be written. This can be either a host
37953 * physical address (HPA) or a guest physical address (GPA) and must
37954 * point to a physically contiguous block of memory.
37956 uint64_t resp_addr;
37958 * Id/Handle to the recently register context memory. This
37959 * handle is passed to the TF session.
37963 uint8_t unused0[6];
37966 /* hwrm_tf_ctxt_mem_unrgtr_output (size:128b/16B) */
37967 struct hwrm_tf_ctxt_mem_unrgtr_output {
37968 /* The specific error status for the command. */
37969 uint16_t error_code;
37970 /* The HWRM command request type. */
37972 /* The sequence ID from the original command. */
37974 /* The length of the response data in number of bytes. */
37977 uint8_t unused0[7];
37979 * This field is used in Output records to indicate that the
37980 * output is completely written to RAM. This field should be
37981 * read as '1' to indicate that the output has been
37982 * completely written. When writing a command completion or
37983 * response to an internal processor, the order of writes has
37984 * to be such that this field is written last.
37989 /************************
37990 * hwrm_tf_ext_em_qcaps *
37991 ************************/
37994 /* hwrm_tf_ext_em_qcaps_input (size:192b/24B) */
37995 struct hwrm_tf_ext_em_qcaps_input {
37996 /* The HWRM command request type. */
37999 * The completion ring to send the completion event on. This should
38000 * be the NQ ID returned from the `nq_alloc` HWRM command.
38002 uint16_t cmpl_ring;
38004 * The sequence ID is used by the driver for tracking multiple
38005 * commands. This ID is treated as opaque data by the firmware and
38006 * the value is returned in the `hwrm_resp_hdr` upon completion.
38010 * The target ID of the command:
38011 * * 0x0-0xFFF8 - The function ID
38012 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
38013 * * 0xFFFD - Reserved for user-space HWRM interface
38016 uint16_t target_id;
38018 * A physical address pointer pointing to a host buffer that the
38019 * command's response data will be written. This can be either a host
38020 * physical address (HPA) or a guest physical address (GPA) and must
38021 * point to a physically contiguous block of memory.
38023 uint64_t resp_addr;
38024 /* Control flags. */
38026 /* Indicates the flow direction. */
38027 #define HWRM_TF_EXT_EM_QCAPS_INPUT_FLAGS_DIR \
38029 /* If this bit set to 0, then it indicates rx flow. */
38030 #define HWRM_TF_EXT_EM_QCAPS_INPUT_FLAGS_DIR_RX \
38032 /* If this bit is set to 1, then it indicates that tx flow. */
38033 #define HWRM_TF_EXT_EM_QCAPS_INPUT_FLAGS_DIR_TX \
38035 #define HWRM_TF_EXT_EM_QCAPS_INPUT_FLAGS_DIR_LAST \
38036 HWRM_TF_EXT_EM_QCAPS_INPUT_FLAGS_DIR_TX
38037 /* When set to 1, all offloaded flows will be sent to EXT EM. */
38038 #define HWRM_TF_EXT_EM_QCAPS_INPUT_FLAGS_PREFERRED_OFFLOAD \
38044 /* hwrm_tf_ext_em_qcaps_output (size:320b/40B) */
38045 struct hwrm_tf_ext_em_qcaps_output {
38046 /* The specific error status for the command. */
38047 uint16_t error_code;
38048 /* The HWRM command request type. */
38050 /* The sequence ID from the original command. */
38052 /* The length of the response data in number of bytes. */
38056 * When set to 1, indicates the the FW supports the Centralized
38057 * Memory Model. The concept designates one entity for the
38058 * memory allocation while all others ‘subscribe’ to it.
38060 #define HWRM_TF_EXT_EM_QCAPS_OUTPUT_FLAGS_CENTRALIZED_MEMORY_MODEL_SUPPORTED \
38063 * When set to 1, indicates the the FW supports the Detached
38064 * Centralized Memory Model. The memory is allocated and managed
38065 * as a separate entity. All PFs and VFs will be granted direct
38066 * or semi-direct access to the allocated memory while none of
38067 * which can interfere with the management of the memory.
38069 #define HWRM_TF_EXT_EM_QCAPS_OUTPUT_FLAGS_DETACHED_CENTRALIZED_MEMORY_MODEL_SUPPORTED \
38073 /* Support flags. */
38074 uint32_t supported;
38076 * If set to 1, then EXT EM KEY0 table is supported using
38078 * If set to 0, EXT EM KEY0 table is not supported.
38080 #define HWRM_TF_EXT_EM_QCAPS_OUTPUT_SUPPORTED_KEY0_TABLE \
38083 * If set to 1, then EXT EM KEY1 table is supported using
38085 * If set to 0, EXT EM KEY1 table is not supported.
38087 #define HWRM_TF_EXT_EM_QCAPS_OUTPUT_SUPPORTED_KEY1_TABLE \
38090 * If set to 1, then EXT EM External Record table is supported.
38091 * If set to 0, EXT EM External Record table is not
38092 * supported. (This table includes action record, EFC
38093 * pointers, encap pointers)
38095 #define HWRM_TF_EXT_EM_QCAPS_OUTPUT_SUPPORTED_EXTERNAL_RECORD_TABLE \
38098 * If set to 1, then EXT EM External Flow Counters table is
38100 * If set to 0, EXT EM External Flow Counters table is not
38103 #define HWRM_TF_EXT_EM_QCAPS_OUTPUT_SUPPORTED_EXTERNAL_FLOW_COUNTERS_TABLE \
38106 * If set to 1, then FID table used for implicit flow flush
38108 * If set to 0, then FID table used for implicit flow flush
38109 * is not supported.
38111 #define HWRM_TF_EXT_EM_QCAPS_OUTPUT_SUPPORTED_FID_TABLE \
38114 * The maximum number of entries supported by EXT EM. When
38115 * configuring the host memory the number of numbers of
38116 * entries that can supported are -
38117 * 32k, 64k 128k, 256k, 512k, 1M, 2M, 4M, 8M, 32M, 64M,
38119 * Any value that are not these values, the FW will round
38120 * down to the closest support number of entries.
38122 uint32_t max_entries_supported;
38124 * The entry size in bytes of each entry in the EXT EM
38125 * KEY0/KEY1 tables.
38127 uint16_t key_entry_size;
38129 * The entry size in bytes of each entry in the EXT EM RECORD
38132 uint16_t record_entry_size;
38133 /* The entry size in bytes of each entry in the EXT EM EFC tables. */
38134 uint16_t efc_entry_size;
38135 /* The FID size in bytes of each entry in the EXT EM FID tables. */
38136 uint16_t fid_entry_size;
38138 uint8_t unused1[7];
38140 * This field is used in Output records to indicate that the
38141 * output is completely written to RAM. This field should be
38142 * read as '1' to indicate that the output has been
38143 * completely written. When writing a command completion or
38144 * response to an internal processor, the order of writes has
38145 * to be such that this field is written last.
38150 /*********************
38151 * hwrm_tf_ext_em_op *
38152 *********************/
38155 /* hwrm_tf_ext_em_op_input (size:192b/24B) */
38156 struct hwrm_tf_ext_em_op_input {
38157 /* The HWRM command request type. */
38160 * The completion ring to send the completion event on. This should
38161 * be the NQ ID returned from the `nq_alloc` HWRM command.
38163 uint16_t cmpl_ring;
38165 * The sequence ID is used by the driver for tracking multiple
38166 * commands. This ID is treated as opaque data by the firmware and
38167 * the value is returned in the `hwrm_resp_hdr` upon completion.
38171 * The target ID of the command:
38172 * * 0x0-0xFFF8 - The function ID
38173 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
38174 * * 0xFFFD - Reserved for user-space HWRM interface
38177 uint16_t target_id;
38179 * A physical address pointer pointing to a host buffer that the
38180 * command's response data will be written. This can be either a host
38181 * physical address (HPA) or a guest physical address (GPA) and must
38182 * point to a physically contiguous block of memory.
38184 uint64_t resp_addr;
38185 /* Control flags. */
38187 /* Indicates the flow direction. */
38188 #define HWRM_TF_EXT_EM_OP_INPUT_FLAGS_DIR UINT32_C(0x1)
38189 /* If this bit set to 0, then it indicates rx flow. */
38190 #define HWRM_TF_EXT_EM_OP_INPUT_FLAGS_DIR_RX UINT32_C(0x0)
38191 /* If this bit is set to 1, then it indicates that tx flow. */
38192 #define HWRM_TF_EXT_EM_OP_INPUT_FLAGS_DIR_TX UINT32_C(0x1)
38193 #define HWRM_TF_EXT_EM_OP_INPUT_FLAGS_DIR_LAST \
38194 HWRM_TF_EXT_EM_OP_INPUT_FLAGS_DIR_TX
38197 /* The number of EXT EM key table entries to be configured. */
38199 /* This value is reserved and should not be used. */
38200 #define HWRM_TF_EXT_EM_OP_INPUT_OP_RESERVED UINT32_C(0x0)
38202 * To properly stop EXT EM and ensure there are no DMA's,
38203 * the caller must disable EXT EM for the given PF, using
38204 * this call. This will safely disable EXT EM and ensure
38205 * that all DMA'ed to the keys/records/efc have been
38208 #define HWRM_TF_EXT_EM_OP_INPUT_OP_EXT_EM_DISABLE UINT32_C(0x1)
38210 * Once the EXT EM host memory has been configured, EXT EM
38211 * options have been configured. Then the caller should
38212 * enable EXT EM for the given PF. Note once this call has
38213 * been made, then the EXT EM mechanism will be active and
38214 * DMA's will occur as packets are processed.
38216 #define HWRM_TF_EXT_EM_OP_INPUT_OP_EXT_EM_ENABLE UINT32_C(0x2)
38218 * Clear EXT EM settings for the given PF so that the
38219 * register values are reset back to their initial state.
38221 #define HWRM_TF_EXT_EM_OP_INPUT_OP_EXT_EM_CLEANUP UINT32_C(0x3)
38222 #define HWRM_TF_EXT_EM_OP_INPUT_OP_LAST \
38223 HWRM_TF_EXT_EM_OP_INPUT_OP_EXT_EM_CLEANUP
38228 /* hwrm_tf_ext_em_op_output (size:128b/16B) */
38229 struct hwrm_tf_ext_em_op_output {
38230 /* The specific error status for the command. */
38231 uint16_t error_code;
38232 /* The HWRM command request type. */
38234 /* The sequence ID from the original command. */
38236 /* The length of the response data in number of bytes. */
38239 uint8_t unused0[7];
38241 * This field is used in Output records to indicate that the
38242 * output is completely written to RAM. This field should be
38243 * read as '1' to indicate that the output has been
38244 * completely written. When writing a command completion or
38245 * response to an internal processor, the order of writes has
38246 * to be such that this field is written last.
38251 /**********************
38252 * hwrm_tf_ext_em_cfg *
38253 **********************/
38256 /* hwrm_tf_ext_em_cfg_input (size:384b/48B) */
38257 struct hwrm_tf_ext_em_cfg_input {
38258 /* The HWRM command request type. */
38261 * The completion ring to send the completion event on. This should
38262 * be the NQ ID returned from the `nq_alloc` HWRM command.
38264 uint16_t cmpl_ring;
38266 * The sequence ID is used by the driver for tracking multiple
38267 * commands. This ID is treated as opaque data by the firmware and
38268 * the value is returned in the `hwrm_resp_hdr` upon completion.
38272 * The target ID of the command:
38273 * * 0x0-0xFFF8 - The function ID
38274 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
38275 * * 0xFFFD - Reserved for user-space HWRM interface
38278 uint16_t target_id;
38280 * A physical address pointer pointing to a host buffer that the
38281 * command's response data will be written. This can be either a host
38282 * physical address (HPA) or a guest physical address (GPA) and must
38283 * point to a physically contiguous block of memory.
38285 uint64_t resp_addr;
38286 /* Control flags. */
38288 /* Indicates the flow direction. */
38289 #define HWRM_TF_EXT_EM_CFG_INPUT_FLAGS_DIR \
38291 /* If this bit set to 0, then it indicates rx flow. */
38292 #define HWRM_TF_EXT_EM_CFG_INPUT_FLAGS_DIR_RX \
38294 /* If this bit is set to 1, then it indicates that tx flow. */
38295 #define HWRM_TF_EXT_EM_CFG_INPUT_FLAGS_DIR_TX \
38297 #define HWRM_TF_EXT_EM_CFG_INPUT_FLAGS_DIR_LAST \
38298 HWRM_TF_EXT_EM_CFG_INPUT_FLAGS_DIR_TX
38299 /* When set to 1, all offloaded flows will be sent to EXT EM. */
38300 #define HWRM_TF_EXT_EM_CFG_INPUT_FLAGS_PREFERRED_OFFLOAD \
38302 /* When set to 1, secondary, 0 means primary. */
38303 #define HWRM_TF_EXT_EM_CFG_INPUT_FLAGS_SECONDARY_PF \
38306 * Group_id which used by Firmware to identify memory pools belonging
38307 * to certain group.
38311 * Dynamically reconfigure EEM pending cache every 1/10th of second.
38312 * If set to 0 it will disable the EEM HW flush of the pending cache.
38314 uint8_t flush_interval;
38318 * Configured EXT EM with the given number of entries. All
38319 * the EXT EM tables KEY0, KEY1, RECORD, EFC all have the
38320 * same number of entries and all tables will be configured
38321 * using this value. Current minimum value is 32k. Current
38322 * maximum value is 128M.
38324 uint32_t num_entries;
38327 /* Configured EXT EM with the given context if for KEY0 table. */
38328 uint16_t key0_ctx_id;
38329 /* Configured EXT EM with the given context if for KEY1 table. */
38330 uint16_t key1_ctx_id;
38331 /* Configured EXT EM with the given context if for RECORD table. */
38332 uint16_t record_ctx_id;
38333 /* Configured EXT EM with the given context if for EFC table. */
38334 uint16_t efc_ctx_id;
38335 /* Configured EXT EM with the given context if for EFC table. */
38336 uint16_t fid_ctx_id;
38343 /* hwrm_tf_ext_em_cfg_output (size:128b/16B) */
38344 struct hwrm_tf_ext_em_cfg_output {
38345 /* The specific error status for the command. */
38346 uint16_t error_code;
38347 /* The HWRM command request type. */
38349 /* The sequence ID from the original command. */
38351 /* The length of the response data in number of bytes. */
38354 uint8_t unused0[7];
38356 * This field is used in Output records to indicate that the
38357 * output is completely written to RAM. This field should be
38358 * read as '1' to indicate that the output has been
38359 * completely written. When writing a command completion or
38360 * response to an internal processor, the order of writes has
38361 * to be such that this field is written last.
38366 /***********************
38367 * hwrm_tf_ext_em_qcfg *
38368 ***********************/
38371 /* hwrm_tf_ext_em_qcfg_input (size:192b/24B) */
38372 struct hwrm_tf_ext_em_qcfg_input {
38373 /* The HWRM command request type. */
38376 * The completion ring to send the completion event on. This should
38377 * be the NQ ID returned from the `nq_alloc` HWRM command.
38379 uint16_t cmpl_ring;
38381 * The sequence ID is used by the driver for tracking multiple
38382 * commands. This ID is treated as opaque data by the firmware and
38383 * the value is returned in the `hwrm_resp_hdr` upon completion.
38387 * The target ID of the command:
38388 * * 0x0-0xFFF8 - The function ID
38389 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
38390 * * 0xFFFD - Reserved for user-space HWRM interface
38393 uint16_t target_id;
38395 * A physical address pointer pointing to a host buffer that the
38396 * command's response data will be written. This can be either a host
38397 * physical address (HPA) or a guest physical address (GPA) and must
38398 * point to a physically contiguous block of memory.
38400 uint64_t resp_addr;
38401 /* Control flags. */
38403 /* Indicates the flow direction. */
38404 #define HWRM_TF_EXT_EM_QCFG_INPUT_FLAGS_DIR UINT32_C(0x1)
38405 /* If this bit set to 0, then it indicates rx flow. */
38406 #define HWRM_TF_EXT_EM_QCFG_INPUT_FLAGS_DIR_RX UINT32_C(0x0)
38407 /* If this bit is set to 1, then it indicates that tx flow. */
38408 #define HWRM_TF_EXT_EM_QCFG_INPUT_FLAGS_DIR_TX UINT32_C(0x1)
38409 #define HWRM_TF_EXT_EM_QCFG_INPUT_FLAGS_DIR_LAST \
38410 HWRM_TF_EXT_EM_QCFG_INPUT_FLAGS_DIR_TX
38415 /* hwrm_tf_ext_em_qcfg_output (size:256b/32B) */
38416 struct hwrm_tf_ext_em_qcfg_output {
38417 /* The specific error status for the command. */
38418 uint16_t error_code;
38419 /* The HWRM command request type. */
38421 /* The sequence ID from the original command. */
38423 /* The length of the response data in number of bytes. */
38425 /* Control flags. */
38427 /* Indicates the flow direction. */
38428 #define HWRM_TF_EXT_EM_QCFG_OUTPUT_FLAGS_DIR \
38430 /* If this bit set to 0, then it indicates rx flow. */
38431 #define HWRM_TF_EXT_EM_QCFG_OUTPUT_FLAGS_DIR_RX \
38433 /* If this bit is set to 1, then it indicates that tx flow. */
38434 #define HWRM_TF_EXT_EM_QCFG_OUTPUT_FLAGS_DIR_TX \
38436 #define HWRM_TF_EXT_EM_QCFG_OUTPUT_FLAGS_DIR_LAST \
38437 HWRM_TF_EXT_EM_QCFG_OUTPUT_FLAGS_DIR_TX
38438 /* When set to 1, all offloaded flows will be sent to EXT EM. */
38439 #define HWRM_TF_EXT_EM_QCFG_OUTPUT_FLAGS_PREFERRED_OFFLOAD \
38441 /* The number of entries the FW has configured for EXT EM. */
38442 uint32_t num_entries;
38443 /* Configured EXT EM with the given context if for KEY0 table. */
38444 uint16_t key0_ctx_id;
38445 /* Configured EXT EM with the given context if for KEY1 table. */
38446 uint16_t key1_ctx_id;
38447 /* Configured EXT EM with the given context if for RECORD table. */
38448 uint16_t record_ctx_id;
38449 /* Configured EXT EM with the given context if for EFC table. */
38450 uint16_t efc_ctx_id;
38451 /* Configured EXT EM with the given context if for EFC table. */
38452 uint16_t fid_ctx_id;
38454 uint8_t unused0[5];
38456 * This field is used in Output records to indicate that the
38457 * output is completely written to RAM. This field should be
38458 * read as '1' to indicate that the output has been
38459 * completely written. When writing a command completion or
38460 * response to an internal processor, the order of writes has
38461 * to be such that this field is written last.
38466 /*********************
38467 * hwrm_tf_em_insert *
38468 *********************/
38471 /* hwrm_tf_em_insert_input (size:832b/104B) */
38472 struct hwrm_tf_em_insert_input {
38473 /* The HWRM command request type. */
38476 * The completion ring to send the completion event on. This should
38477 * be the NQ ID returned from the `nq_alloc` HWRM command.
38479 uint16_t cmpl_ring;
38481 * The sequence ID is used by the driver for tracking multiple
38482 * commands. This ID is treated as opaque data by the firmware and
38483 * the value is returned in the `hwrm_resp_hdr` upon completion.
38487 * The target ID of the command:
38488 * * 0x0-0xFFF8 - The function ID
38489 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
38490 * * 0xFFFD - Reserved for user-space HWRM interface
38493 uint16_t target_id;
38495 * A physical address pointer pointing to a host buffer that the
38496 * command's response data will be written. This can be either a host
38497 * physical address (HPA) or a guest physical address (GPA) and must
38498 * point to a physically contiguous block of memory.
38500 uint64_t resp_addr;
38501 /* Firmware Session Id. */
38502 uint32_t fw_session_id;
38503 /* Control Flags. */
38505 /* Indicates the flow direction. */
38506 #define HWRM_TF_EM_INSERT_INPUT_FLAGS_DIR UINT32_C(0x1)
38507 /* If this bit set to 0, then it indicates rx flow. */
38508 #define HWRM_TF_EM_INSERT_INPUT_FLAGS_DIR_RX UINT32_C(0x0)
38509 /* If this bit is set to 1, then it indicates that tx flow. */
38510 #define HWRM_TF_EM_INSERT_INPUT_FLAGS_DIR_TX UINT32_C(0x1)
38511 #define HWRM_TF_EM_INSERT_INPUT_FLAGS_DIR_LAST \
38512 HWRM_TF_EM_INSERT_INPUT_FLAGS_DIR_TX
38513 /* Reported match strength. */
38515 /* Index to action. */
38516 uint32_t action_ptr;
38517 /* Index of EM record. */
38518 uint32_t em_record_idx;
38519 /* EM Key value. */
38520 uint64_t em_key[8];
38521 /* Number of bits in em_key. */
38522 uint16_t em_key_bitlen;
38524 uint16_t unused0[3];
38527 /* hwrm_tf_em_insert_output (size:128b/16B) */
38528 struct hwrm_tf_em_insert_output {
38529 /* The specific error status for the command. */
38530 uint16_t error_code;
38531 /* The HWRM command request type. */
38533 /* The sequence ID from the original command. */
38535 /* The length of the response data in number of bytes. */
38537 /* EM record pointer index. */
38538 uint16_t rptr_index;
38539 /* EM record offset 0~3. */
38540 uint8_t rptr_entry;
38541 /* Number of word entries consumed by the key. */
38542 uint8_t num_of_entries;
38547 /*********************
38548 * hwrm_tf_em_delete *
38549 *********************/
38552 /* hwrm_tf_em_delete_input (size:832b/104B) */
38553 struct hwrm_tf_em_delete_input {
38554 /* The HWRM command request type. */
38557 * The completion ring to send the completion event on. This should
38558 * be the NQ ID returned from the `nq_alloc` HWRM command.
38560 uint16_t cmpl_ring;
38562 * The sequence ID is used by the driver for tracking multiple
38563 * commands. This ID is treated as opaque data by the firmware and
38564 * the value is returned in the `hwrm_resp_hdr` upon completion.
38568 * The target ID of the command:
38569 * * 0x0-0xFFF8 - The function ID
38570 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
38571 * * 0xFFFD - Reserved for user-space HWRM interface
38574 uint16_t target_id;
38576 * A physical address pointer pointing to a host buffer that the
38577 * command's response data will be written. This can be either a host
38578 * physical address (HPA) or a guest physical address (GPA) and must
38579 * point to a physically contiguous block of memory.
38581 uint64_t resp_addr;
38583 uint32_t fw_session_id;
38584 /* Control flags. */
38586 /* Indicates the flow direction. */
38587 #define HWRM_TF_EM_DELETE_INPUT_FLAGS_DIR UINT32_C(0x1)
38588 /* If this bit set to 0, then it indicates rx flow. */
38589 #define HWRM_TF_EM_DELETE_INPUT_FLAGS_DIR_RX UINT32_C(0x0)
38590 /* If this bit is set to 1, then it indicates that tx flow. */
38591 #define HWRM_TF_EM_DELETE_INPUT_FLAGS_DIR_TX UINT32_C(0x1)
38592 #define HWRM_TF_EM_DELETE_INPUT_FLAGS_DIR_LAST \
38593 HWRM_TF_EM_DELETE_INPUT_FLAGS_DIR_TX
38596 /* EM internal flow hanndle. */
38597 uint64_t flow_handle;
38599 uint64_t em_key[8];
38600 /* Number of bits in em_key. */
38601 uint16_t em_key_bitlen;
38603 uint16_t unused1[3];
38606 /* hwrm_tf_em_delete_output (size:128b/16B) */
38607 struct hwrm_tf_em_delete_output {
38608 /* The specific error status for the command. */
38609 uint16_t error_code;
38610 /* The HWRM command request type. */
38612 /* The sequence ID from the original command. */
38614 /* The length of the response data in number of bytes. */
38616 /* Original stack allocation index. */
38619 uint16_t unused0[3];
38622 /********************
38623 * hwrm_tf_tcam_set *
38624 ********************/
38627 /* hwrm_tf_tcam_set_input (size:1024b/128B) */
38628 struct hwrm_tf_tcam_set_input {
38629 /* The HWRM command request type. */
38632 * The completion ring to send the completion event on. This should
38633 * be the NQ ID returned from the `nq_alloc` HWRM command.
38635 uint16_t cmpl_ring;
38637 * The sequence ID is used by the driver for tracking multiple
38638 * commands. This ID is treated as opaque data by the firmware and
38639 * the value is returned in the `hwrm_resp_hdr` upon completion.
38643 * The target ID of the command:
38644 * * 0x0-0xFFF8 - The function ID
38645 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
38646 * * 0xFFFD - Reserved for user-space HWRM interface
38649 uint16_t target_id;
38651 * A physical address pointer pointing to a host buffer that the
38652 * command's response data will be written. This can be either a host
38653 * physical address (HPA) or a guest physical address (GPA) and must
38654 * point to a physically contiguous block of memory.
38656 uint64_t resp_addr;
38657 /* Firmware session id returned when HWRM_TF_SESSION_OPEN is sent. */
38658 uint32_t fw_session_id;
38659 /* Control flags. */
38661 /* Indicates the flow direction. */
38662 #define HWRM_TF_TCAM_SET_INPUT_FLAGS_DIR UINT32_C(0x1)
38663 /* If this bit set to 0, then it indicates rx flow. */
38664 #define HWRM_TF_TCAM_SET_INPUT_FLAGS_DIR_RX UINT32_C(0x0)
38665 /* If this bit is set to 1, then it indicates that tx flow. */
38666 #define HWRM_TF_TCAM_SET_INPUT_FLAGS_DIR_TX UINT32_C(0x1)
38667 #define HWRM_TF_TCAM_SET_INPUT_FLAGS_DIR_LAST \
38668 HWRM_TF_TCAM_SET_INPUT_FLAGS_DIR_TX
38670 * Indicate device data is being sent via DMA, the device
38671 * data is packing does not change.
38673 #define HWRM_TF_TCAM_SET_INPUT_FLAGS_DMA UINT32_C(0x2)
38675 * TCAM type of the resource, defined globally in the
38676 * hwrm_tf_resc_type enum.
38679 /* Index of TCAM entry. */
38681 /* Number of bytes in the TCAM key. */
38683 /* Number of bytes in the TCAM result. */
38684 uint8_t result_size;
38686 * Offset from which the mask bytes start in the device data
38687 * array, key offset is always 0.
38689 uint8_t mask_offset;
38690 /* Offset from which the result bytes start in the device data array. */
38691 uint8_t result_offset;
38693 uint8_t unused0[6];
38695 * TCAM key located at offset 0, mask located at mask_offsec
38696 * and result at result_offsec for the device.
38698 uint8_t dev_data[88];
38701 /* hwrm_tf_tcam_set_output (size:128b/16B) */
38702 struct hwrm_tf_tcam_set_output {
38703 /* The specific error status for the command. */
38704 uint16_t error_code;
38705 /* The HWRM command request type. */
38707 /* The sequence ID from the original command. */
38709 /* The length of the response data in number of bytes. */
38712 uint8_t unused0[7];
38714 * This field is used in Output records to indicate that the
38715 * output is completely written to RAM. This field should be
38716 * read as '1' to indicate that the output has been
38717 * completely written. When writing a command completion or
38718 * response to an internal processor, the order of writes has
38719 * to be such that this field is written last.
38724 /********************
38725 * hwrm_tf_tcam_get *
38726 ********************/
38729 /* hwrm_tf_tcam_get_input (size:256b/32B) */
38730 struct hwrm_tf_tcam_get_input {
38731 /* The HWRM command request type. */
38734 * The completion ring to send the completion event on. This should
38735 * be the NQ ID returned from the `nq_alloc` HWRM command.
38737 uint16_t cmpl_ring;
38739 * The sequence ID is used by the driver for tracking multiple
38740 * commands. This ID is treated as opaque data by the firmware and
38741 * the value is returned in the `hwrm_resp_hdr` upon completion.
38745 * The target ID of the command:
38746 * * 0x0-0xFFF8 - The function ID
38747 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
38748 * * 0xFFFD - Reserved for user-space HWRM interface
38751 uint16_t target_id;
38753 * A physical address pointer pointing to a host buffer that the
38754 * command's response data will be written. This can be either a host
38755 * physical address (HPA) or a guest physical address (GPA) and must
38756 * point to a physically contiguous block of memory.
38758 uint64_t resp_addr;
38759 /* Firmware session id returned when HWRM_TF_SESSION_OPEN is sent. */
38760 uint32_t fw_session_id;
38761 /* Control flags. */
38763 /* Indicates the flow direction. */
38764 #define HWRM_TF_TCAM_GET_INPUT_FLAGS_DIR UINT32_C(0x1)
38765 /* If this bit set to 0, then it indicates rx flow. */
38766 #define HWRM_TF_TCAM_GET_INPUT_FLAGS_DIR_RX UINT32_C(0x0)
38767 /* If this bit is set to 1, then it indicates that tx flow. */
38768 #define HWRM_TF_TCAM_GET_INPUT_FLAGS_DIR_TX UINT32_C(0x1)
38769 #define HWRM_TF_TCAM_GET_INPUT_FLAGS_DIR_LAST \
38770 HWRM_TF_TCAM_GET_INPUT_FLAGS_DIR_TX
38772 * TCAM type of the resource, defined globally in the
38773 * hwrm_tf_resc_type enum.
38776 /* Index of a TCAM entry. */
38782 /* hwrm_tf_tcam_get_output (size:2368b/296B) */
38783 struct hwrm_tf_tcam_get_output {
38784 /* The specific error status for the command. */
38785 uint16_t error_code;
38786 /* The HWRM command request type. */
38788 /* The sequence ID from the original command. */
38790 /* The length of the response data in number of bytes. */
38792 /* Number of bytes in the TCAM key. */
38794 /* Number of bytes in the TCAM entry. */
38795 uint8_t result_size;
38796 /* Offset from which the mask bytes start in the device data array. */
38797 uint8_t mask_offset;
38798 /* Offset from which the result bytes start in the device data array. */
38799 uint8_t result_offset;
38801 uint8_t unused0[4];
38803 * TCAM key located at offset 0, mask located at mask_offsec
38804 * and result at result_offsec for the device.
38806 uint8_t dev_data[272];
38808 uint8_t unused1[7];
38810 * This field is used in Output records to indicate that the
38811 * output is completely written to RAM. This field should be
38812 * read as '1' to indicate that the output has been
38813 * completely written. When writing a command completion or
38814 * response to an internal processor, the order of writes has
38815 * to be such that this field is written last.
38820 /*********************
38821 * hwrm_tf_tcam_move *
38822 *********************/
38825 /* hwrm_tf_tcam_move_input (size:1024b/128B) */
38826 struct hwrm_tf_tcam_move_input {
38827 /* The HWRM command request type. */
38830 * The completion ring to send the completion event on. This should
38831 * be the NQ ID returned from the `nq_alloc` HWRM command.
38833 uint16_t cmpl_ring;
38835 * The sequence ID is used by the driver for tracking multiple
38836 * commands. This ID is treated as opaque data by the firmware and
38837 * the value is returned in the `hwrm_resp_hdr` upon completion.
38841 * The target ID of the command:
38842 * * 0x0-0xFFF8 - The function ID
38843 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
38844 * * 0xFFFD - Reserved for user-space HWRM interface
38847 uint16_t target_id;
38849 * A physical address pointer pointing to a host buffer that the
38850 * command's response data will be written. This can be either a host
38851 * physical address (HPA) or a guest physical address (GPA) and must
38852 * point to a physically contiguous block of memory.
38854 uint64_t resp_addr;
38855 /* Firmware session id returned when HWRM_TF_SESSION_OPEN is sent. */
38856 uint32_t fw_session_id;
38857 /* Control flags. */
38859 /* Indicates the flow direction. */
38860 #define HWRM_TF_TCAM_MOVE_INPUT_FLAGS_DIR UINT32_C(0x1)
38861 /* If this bit set to 0, then it indicates rx flow. */
38862 #define HWRM_TF_TCAM_MOVE_INPUT_FLAGS_DIR_RX UINT32_C(0x0)
38863 /* If this bit is set to 1, then it indicates that tx flow. */
38864 #define HWRM_TF_TCAM_MOVE_INPUT_FLAGS_DIR_TX UINT32_C(0x1)
38865 #define HWRM_TF_TCAM_MOVE_INPUT_FLAGS_DIR_LAST \
38866 HWRM_TF_TCAM_MOVE_INPUT_FLAGS_DIR_TX
38868 * TCAM type of the resource, defined globally in the
38869 * hwrm_tf_resc_type enum.
38872 /* Number of TCAM index pairs to be swapped for the device. */
38876 /* TCAM index pairs to be swapped for the device. */
38877 uint16_t idx_pairs[48];
38880 /* hwrm_tf_tcam_move_output (size:128b/16B) */
38881 struct hwrm_tf_tcam_move_output {
38882 /* The specific error status for the command. */
38883 uint16_t error_code;
38884 /* The HWRM command request type. */
38886 /* The sequence ID from the original command. */
38888 /* The length of the response data in number of bytes. */
38891 uint8_t unused0[7];
38893 * This field is used in Output records to indicate that the
38894 * output is completely written to RAM. This field should be
38895 * read as '1' to indicate that the output has been
38896 * completely written. When writing a command completion or
38897 * response to an internal processor, the order of writes has
38898 * to be such that this field is written last.
38903 /*********************
38904 * hwrm_tf_tcam_free *
38905 *********************/
38908 /* hwrm_tf_tcam_free_input (size:1024b/128B) */
38909 struct hwrm_tf_tcam_free_input {
38910 /* The HWRM command request type. */
38913 * The completion ring to send the completion event on. This should
38914 * be the NQ ID returned from the `nq_alloc` HWRM command.
38916 uint16_t cmpl_ring;
38918 * The sequence ID is used by the driver for tracking multiple
38919 * commands. This ID is treated as opaque data by the firmware and
38920 * the value is returned in the `hwrm_resp_hdr` upon completion.
38924 * The target ID of the command:
38925 * * 0x0-0xFFF8 - The function ID
38926 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
38927 * * 0xFFFD - Reserved for user-space HWRM interface
38930 uint16_t target_id;
38932 * A physical address pointer pointing to a host buffer that the
38933 * command's response data will be written. This can be either a host
38934 * physical address (HPA) or a guest physical address (GPA) and must
38935 * point to a physically contiguous block of memory.
38937 uint64_t resp_addr;
38938 /* Firmware session id returned when HWRM_TF_SESSION_OPEN is sent. */
38939 uint32_t fw_session_id;
38940 /* Control flags. */
38942 /* Indicates the flow direction. */
38943 #define HWRM_TF_TCAM_FREE_INPUT_FLAGS_DIR UINT32_C(0x1)
38944 /* If this bit set to 0, then it indicates rx flow. */
38945 #define HWRM_TF_TCAM_FREE_INPUT_FLAGS_DIR_RX UINT32_C(0x0)
38946 /* If this bit is set to 1, then it indicates that tx flow. */
38947 #define HWRM_TF_TCAM_FREE_INPUT_FLAGS_DIR_TX UINT32_C(0x1)
38948 #define HWRM_TF_TCAM_FREE_INPUT_FLAGS_DIR_LAST \
38949 HWRM_TF_TCAM_FREE_INPUT_FLAGS_DIR_TX
38951 * TCAM type of the resource, defined globally in the
38952 * hwrm_tf_resc_type enum.
38955 /* Number of TCAM index to be deleted for the device. */
38959 /* TCAM index list to be deleted for the device. */
38960 uint16_t idx_list[48];
38963 /* hwrm_tf_tcam_free_output (size:128b/16B) */
38964 struct hwrm_tf_tcam_free_output {
38965 /* The specific error status for the command. */
38966 uint16_t error_code;
38967 /* The HWRM command request type. */
38969 /* The sequence ID from the original command. */
38971 /* The length of the response data in number of bytes. */
38974 uint8_t unused0[7];
38976 * This field is used in Output records to indicate that the
38977 * output is completely written to RAM. This field should be
38978 * read as '1' to indicate that the output has been
38979 * completely written. When writing a command completion or
38980 * response to an internal processor, the order of writes has
38981 * to be such that this field is written last.
38986 /**************************
38987 * hwrm_tf_global_cfg_set *
38988 **************************/
38991 /* hwrm_tf_global_cfg_set_input (size:448b/56B) */
38992 struct hwrm_tf_global_cfg_set_input {
38993 /* The HWRM command request type. */
38996 * The completion ring to send the completion event on. This should
38997 * be the NQ ID returned from the `nq_alloc` HWRM command.
38999 uint16_t cmpl_ring;
39001 * The sequence ID is used by the driver for tracking multiple
39002 * commands. This ID is treated as opaque data by the firmware and
39003 * the value is returned in the `hwrm_resp_hdr` upon completion.
39007 * The target ID of the command:
39008 * * 0x0-0xFFF8 - The function ID
39009 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
39010 * * 0xFFFD - Reserved for user-space HWRM interface
39013 uint16_t target_id;
39015 * A physical address pointer pointing to a host buffer that the
39016 * command's response data will be written. This can be either a host
39017 * physical address (HPA) or a guest physical address (GPA) and must
39018 * point to a physically contiguous block of memory.
39020 uint64_t resp_addr;
39021 /* Firmware session id returned when HWRM_TF_SESSION_OPEN is sent. */
39022 uint32_t fw_session_id;
39023 /* Control flags. */
39025 /* Indicates the flow direction. */
39026 #define HWRM_TF_GLOBAL_CFG_SET_INPUT_FLAGS_DIR UINT32_C(0x1)
39027 /* If this bit set to 0, then it indicates rx flow. */
39028 #define HWRM_TF_GLOBAL_CFG_SET_INPUT_FLAGS_DIR_RX UINT32_C(0x0)
39029 /* If this bit is set to 1, then it indicates that tx flow. */
39030 #define HWRM_TF_GLOBAL_CFG_SET_INPUT_FLAGS_DIR_TX UINT32_C(0x1)
39031 #define HWRM_TF_GLOBAL_CFG_SET_INPUT_FLAGS_DIR_LAST \
39032 HWRM_TF_GLOBAL_CFG_SET_INPUT_FLAGS_DIR_TX
39033 /* Global Cfg type */
39035 /* Offset of the type */
39037 /* Size of the data to set in bytes */
39040 uint8_t unused0[6];
39043 /* Mask of data to set, 0 indicates no mask */
39047 /* hwrm_tf_global_cfg_set_output (size:128b/16B) */
39048 struct hwrm_tf_global_cfg_set_output {
39049 /* The specific error status for the command. */
39050 uint16_t error_code;
39051 /* The HWRM command request type. */
39053 /* The sequence ID from the original command. */
39055 /* The length of the response data in number of bytes. */
39058 uint8_t unused0[7];
39060 * This field is used in Output records to indicate that the
39061 * output is completely written to RAM. This field should be
39062 * read as '1' to indicate that the output has been
39063 * completely written. When writing a command completion or
39064 * response to an internal processor, the order of writes has
39065 * to be such that this field is written last.
39070 /**************************
39071 * hwrm_tf_global_cfg_get *
39072 **************************/
39075 /* hwrm_tf_global_cfg_get_input (size:320b/40B) */
39076 struct hwrm_tf_global_cfg_get_input {
39077 /* The HWRM command request type. */
39080 * The completion ring to send the completion event on. This should
39081 * be the NQ ID returned from the `nq_alloc` HWRM command.
39083 uint16_t cmpl_ring;
39085 * The sequence ID is used by the driver for tracking multiple
39086 * commands. This ID is treated as opaque data by the firmware and
39087 * the value is returned in the `hwrm_resp_hdr` upon completion.
39091 * The target ID of the command:
39092 * * 0x0-0xFFF8 - The function ID
39093 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
39094 * * 0xFFFD - Reserved for user-space HWRM interface
39097 uint16_t target_id;
39099 * A physical address pointer pointing to a host buffer that the
39100 * command's response data will be written. This can be either a host
39101 * physical address (HPA) or a guest physical address (GPA) and must
39102 * point to a physically contiguous block of memory.
39104 uint64_t resp_addr;
39105 /* Firmware session id returned when HWRM_TF_SESSION_OPEN is sent. */
39106 uint32_t fw_session_id;
39107 /* Control flags. */
39109 /* Indicates the flow direction. */
39110 #define HWRM_TF_GLOBAL_CFG_GET_INPUT_FLAGS_DIR UINT32_C(0x1)
39111 /* If this bit set to 0, then it indicates rx flow. */
39112 #define HWRM_TF_GLOBAL_CFG_GET_INPUT_FLAGS_DIR_RX UINT32_C(0x0)
39113 /* If this bit is set to 1, then it indicates that tx flow. */
39114 #define HWRM_TF_GLOBAL_CFG_GET_INPUT_FLAGS_DIR_TX UINT32_C(0x1)
39115 #define HWRM_TF_GLOBAL_CFG_GET_INPUT_FLAGS_DIR_LAST \
39116 HWRM_TF_GLOBAL_CFG_GET_INPUT_FLAGS_DIR_TX
39117 /* Global Cfg type */
39119 /* Offset of the type */
39121 /* Size of the data to set in bytes */
39124 uint8_t unused0[6];
39127 /* hwrm_tf_global_cfg_get_output (size:256b/32B) */
39128 struct hwrm_tf_global_cfg_get_output {
39129 /* The specific error status for the command. */
39130 uint16_t error_code;
39131 /* The HWRM command request type. */
39133 /* The sequence ID from the original command. */
39135 /* The length of the response data in number of bytes. */
39137 /* Size of the data read in bytes */
39140 uint8_t unused0[6];
39145 /**********************
39146 * hwrm_tf_if_tbl_get *
39147 **********************/
39150 /* hwrm_tf_if_tbl_get_input (size:256b/32B) */
39151 struct hwrm_tf_if_tbl_get_input {
39152 /* The HWRM command request type. */
39155 * The completion ring to send the completion event on. This should
39156 * be the NQ ID returned from the `nq_alloc` HWRM command.
39158 uint16_t cmpl_ring;
39160 * The sequence ID is used by the driver for tracking multiple
39161 * commands. This ID is treated as opaque data by the firmware and
39162 * the value is returned in the `hwrm_resp_hdr` upon completion.
39166 * The target ID of the command:
39167 * * 0x0-0xFFF8 - The function ID
39168 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
39169 * * 0xFFFD - Reserved for user-space HWRM interface
39172 uint16_t target_id;
39174 * A physical address pointer pointing to a host buffer that the
39175 * command's response data will be written. This can be either a host
39176 * physical address (HPA) or a guest physical address (GPA) and must
39177 * point to a physically contiguous block of memory.
39179 uint64_t resp_addr;
39180 /* Firmware session id returned when HWRM_TF_SESSION_OPEN is sent. */
39181 uint32_t fw_session_id;
39182 /* Control flags. */
39184 /* Indicates the flow direction. */
39185 #define HWRM_TF_IF_TBL_GET_INPUT_FLAGS_DIR UINT32_C(0x1)
39186 /* If this bit set to 0, then it indicates rx flow. */
39187 #define HWRM_TF_IF_TBL_GET_INPUT_FLAGS_DIR_RX UINT32_C(0x0)
39188 /* If this bit is set to 1, then it indicates that tx flow. */
39189 #define HWRM_TF_IF_TBL_GET_INPUT_FLAGS_DIR_TX UINT32_C(0x1)
39190 #define HWRM_TF_IF_TBL_GET_INPUT_FLAGS_DIR_LAST \
39191 HWRM_TF_IF_TBL_GET_INPUT_FLAGS_DIR_TX
39192 /* Size of the data to set. */
39195 * Type of the resource, defined globally in the
39196 * hwrm_tf_resc_type enum.
39199 /* Index of the type to retrieve. */
39203 /* hwrm_tf_if_tbl_get_output (size:256b/32B) */
39204 struct hwrm_tf_if_tbl_get_output {
39205 /* The specific error status for the command. */
39206 uint16_t error_code;
39207 /* The HWRM command request type. */
39209 /* The sequence ID from the original command. */
39211 /* The length of the response data in number of bytes. */
39213 /* Response code. */
39214 uint32_t resp_code;
39215 /* Response size. */
39219 /* Response data. */
39222 uint8_t unused1[7];
39224 * This field is used in Output records to indicate that the output
39225 * is completely written to RAM. This field should be read as '1'
39226 * to indicate that the output has been completely written.
39227 * When writing a command completion or response to an internal
39228 * processor, the order of writes has to be such that this field
39234 /***************************
39235 * hwrm_tf_if_tbl_type_set *
39236 ***************************/
39239 /* hwrm_tf_if_tbl_set_input (size:384b/48B) */
39240 struct hwrm_tf_if_tbl_set_input {
39241 /* The HWRM command request type. */
39244 * The completion ring to send the completion event on. This should
39245 * be the NQ ID returned from the `nq_alloc` HWRM command.
39247 uint16_t cmpl_ring;
39249 * The sequence ID is used by the driver for tracking multiple
39250 * commands. This ID is treated as opaque data by the firmware and
39251 * the value is returned in the `hwrm_resp_hdr` upon completion.
39255 * The target ID of the command:
39256 * * 0x0-0xFFF8 - The function ID
39257 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
39258 * * 0xFFFD - Reserved for user-space HWRM interface
39261 uint16_t target_id;
39263 * A physical address pointer pointing to a host buffer that the
39264 * command's response data will be written. This can be either a host
39265 * physical address (HPA) or a guest physical address (GPA) and must
39266 * point to a physically contiguous block of memory.
39268 uint64_t resp_addr;
39269 /* Firmware session id returned when HWRM_TF_SESSION_OPEN is sent. */
39270 uint32_t fw_session_id;
39271 /* Control flags. */
39273 /* Indicates the flow direction. */
39274 #define HWRM_TF_IF_TBL_SET_INPUT_FLAGS_DIR UINT32_C(0x1)
39275 /* If this bit set to 0, then it indicates rx flow. */
39276 #define HWRM_TF_IF_TBL_SET_INPUT_FLAGS_DIR_RX UINT32_C(0x0)
39277 /* If this bit is set to 1, then it indicates that tx flow. */
39278 #define HWRM_TF_IF_TBL_SET_INPUT_FLAGS_DIR_TX UINT32_C(0x1)
39279 #define HWRM_TF_IF_TBL_SET_INPUT_FLAGS_DIR_LAST \
39280 HWRM_TF_IF_TBL_SET_INPUT_FLAGS_DIR_TX
39282 uint8_t unused0[2];
39284 * Type of the resource, defined globally in the
39285 * hwrm_tf_resc_type enum.
39288 /* Index of the type to set. */
39290 /* Size of the data to set. */
39293 uint8_t unused1[6];
39294 /* Data to be set. */
39298 /* hwrm_tf_if_tbl_set_output (size:128b/16B) */
39299 struct hwrm_tf_if_tbl_set_output {
39300 /* The specific error status for the command. */
39301 uint16_t error_code;
39302 /* The HWRM command request type. */
39304 /* The sequence ID from the original command. */
39306 /* The length of the response data in number of bytes. */
39309 uint8_t unused0[7];
39311 * This field is used in Output records to indicate that the output
39312 * is completely written to RAM. This field should be read as '1'
39313 * to indicate that the output has been completely written.
39314 * When writing a command completion or response to an internal
39315 * processor, the order of writes has to be such that this field
39321 /******************************
39322 * hwrm_tunnel_dst_port_query *
39323 ******************************/
39326 /* hwrm_tunnel_dst_port_query_input (size:192b/24B) */
39327 struct hwrm_tunnel_dst_port_query_input {
39328 /* The HWRM command request type. */
39331 * The completion ring to send the completion event on. This should
39332 * be the NQ ID returned from the `nq_alloc` HWRM command.
39334 uint16_t cmpl_ring;
39336 * The sequence ID is used by the driver for tracking multiple
39337 * commands. This ID is treated as opaque data by the firmware and
39338 * the value is returned in the `hwrm_resp_hdr` upon completion.
39342 * The target ID of the command:
39343 * * 0x0-0xFFF8 - The function ID
39344 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
39345 * * 0xFFFD - Reserved for user-space HWRM interface
39348 uint16_t target_id;
39350 * A physical address pointer pointing to a host buffer that the
39351 * command's response data will be written. This can be either a host
39352 * physical address (HPA) or a guest physical address (GPA) and must
39353 * point to a physically contiguous block of memory.
39355 uint64_t resp_addr;
39357 uint8_t tunnel_type;
39358 /* Virtual eXtensible Local Area Network (VXLAN) */
39359 #define HWRM_TUNNEL_DST_PORT_QUERY_INPUT_TUNNEL_TYPE_VXLAN \
39361 /* Generic Network Virtualization Encapsulation (Geneve) */
39362 #define HWRM_TUNNEL_DST_PORT_QUERY_INPUT_TUNNEL_TYPE_GENEVE \
39364 /* IPV4 over virtual eXtensible Local Area Network (IPV4oVXLAN) */
39365 #define HWRM_TUNNEL_DST_PORT_QUERY_INPUT_TUNNEL_TYPE_VXLAN_V4 \
39367 /* Enhance Generic Routing Encapsulation (GRE version 1) inside IP datagram payload */
39368 #define HWRM_TUNNEL_DST_PORT_QUERY_INPUT_TUNNEL_TYPE_IPGRE_V1 \
39370 /* Use fixed layer 2 ether type of 0xFFFF */
39371 #define HWRM_TUNNEL_DST_PORT_QUERY_INPUT_TUNNEL_TYPE_L2_ETYPE \
39373 /* IPV6 over virtual eXtensible Local Area Network with GPE header (IPV6oVXLANGPE) */
39374 #define HWRM_TUNNEL_DST_PORT_QUERY_INPUT_TUNNEL_TYPE_VXLAN_GPE_V6 \
39376 #define HWRM_TUNNEL_DST_PORT_QUERY_INPUT_TUNNEL_TYPE_LAST \
39377 HWRM_TUNNEL_DST_PORT_QUERY_INPUT_TUNNEL_TYPE_VXLAN_GPE_V6
39378 uint8_t unused_0[7];
39381 /* hwrm_tunnel_dst_port_query_output (size:128b/16B) */
39382 struct hwrm_tunnel_dst_port_query_output {
39383 /* The specific error status for the command. */
39384 uint16_t error_code;
39385 /* The HWRM command request type. */
39387 /* The sequence ID from the original command. */
39389 /* The length of the response data in number of bytes. */
39392 * This field represents the identifier of L4 destination port
39393 * used for the given tunnel type. This field is valid for
39394 * specific tunnel types that use layer 4 (e.g. UDP)
39395 * transports for tunneling.
39397 uint16_t tunnel_dst_port_id;
39399 * This field represents the value of L4 destination port
39400 * identified by tunnel_dst_port_id. This field is valid for
39401 * specific tunnel types that use layer 4 (e.g. UDP)
39402 * transports for tunneling.
39403 * This field is in network byte order.
39405 * A value of 0 means that the destination port is not
39408 uint16_t tunnel_dst_port_val;
39409 uint8_t unused_0[3];
39411 * This field is used in Output records to indicate that the output
39412 * is completely written to RAM. This field should be read as '1'
39413 * to indicate that the output has been completely written.
39414 * When writing a command completion or response to an internal processor,
39415 * the order of writes has to be such that this field is written last.
39420 /******************************
39421 * hwrm_tunnel_dst_port_alloc *
39422 ******************************/
39425 /* hwrm_tunnel_dst_port_alloc_input (size:192b/24B) */
39426 struct hwrm_tunnel_dst_port_alloc_input {
39427 /* The HWRM command request type. */
39430 * The completion ring to send the completion event on. This should
39431 * be the NQ ID returned from the `nq_alloc` HWRM command.
39433 uint16_t cmpl_ring;
39435 * The sequence ID is used by the driver for tracking multiple
39436 * commands. This ID is treated as opaque data by the firmware and
39437 * the value is returned in the `hwrm_resp_hdr` upon completion.
39441 * The target ID of the command:
39442 * * 0x0-0xFFF8 - The function ID
39443 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
39444 * * 0xFFFD - Reserved for user-space HWRM interface
39447 uint16_t target_id;
39449 * A physical address pointer pointing to a host buffer that the
39450 * command's response data will be written. This can be either a host
39451 * physical address (HPA) or a guest physical address (GPA) and must
39452 * point to a physically contiguous block of memory.
39454 uint64_t resp_addr;
39456 uint8_t tunnel_type;
39457 /* Virtual eXtensible Local Area Network (VXLAN) */
39458 #define HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_VXLAN \
39460 /* Generic Network Virtualization Encapsulation (Geneve) */
39461 #define HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_GENEVE \
39463 /* IPV4 over virtual eXtensible Local Area Network (IPV4oVXLAN) */
39464 #define HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_VXLAN_V4 \
39466 /* Enhance Generic Routing Encapsulation (GRE version 1) inside IP datagram payload */
39467 #define HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_IPGRE_V1 \
39469 /* Use fixed layer 2 ether type of 0xFFFF */
39470 #define HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_L2_ETYPE \
39472 /* IPV6 over virtual eXtensible Local Area Network with GPE header (IPV6oVXLANGPE) */
39473 #define HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_VXLAN_GPE_V6 \
39475 #define HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_LAST \
39476 HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_VXLAN_GPE_V6
39479 * This field represents the value of L4 destination port used
39480 * for the given tunnel type. This field is valid for
39481 * specific tunnel types that use layer 4 (e.g. UDP)
39482 * transports for tunneling.
39484 * This field is in network byte order.
39486 * A value of 0 shall fail the command.
39488 uint16_t tunnel_dst_port_val;
39489 uint8_t unused_1[4];
39492 /* hwrm_tunnel_dst_port_alloc_output (size:128b/16B) */
39493 struct hwrm_tunnel_dst_port_alloc_output {
39494 /* The specific error status for the command. */
39495 uint16_t error_code;
39496 /* The HWRM command request type. */
39498 /* The sequence ID from the original command. */
39500 /* The length of the response data in number of bytes. */
39503 * Identifier of a tunnel L4 destination port value. Only applies to tunnel
39504 * types that has l4 destination port parameters.
39506 uint16_t tunnel_dst_port_id;
39507 uint8_t unused_0[5];
39509 * This field is used in Output records to indicate that the output
39510 * is completely written to RAM. This field should be read as '1'
39511 * to indicate that the output has been completely written.
39512 * When writing a command completion or response to an internal processor,
39513 * the order of writes has to be such that this field is written last.
39518 /*****************************
39519 * hwrm_tunnel_dst_port_free *
39520 *****************************/
39523 /* hwrm_tunnel_dst_port_free_input (size:192b/24B) */
39524 struct hwrm_tunnel_dst_port_free_input {
39525 /* The HWRM command request type. */
39528 * The completion ring to send the completion event on. This should
39529 * be the NQ ID returned from the `nq_alloc` HWRM command.
39531 uint16_t cmpl_ring;
39533 * The sequence ID is used by the driver for tracking multiple
39534 * commands. This ID is treated as opaque data by the firmware and
39535 * the value is returned in the `hwrm_resp_hdr` upon completion.
39539 * The target ID of the command:
39540 * * 0x0-0xFFF8 - The function ID
39541 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
39542 * * 0xFFFD - Reserved for user-space HWRM interface
39545 uint16_t target_id;
39547 * A physical address pointer pointing to a host buffer that the
39548 * command's response data will be written. This can be either a host
39549 * physical address (HPA) or a guest physical address (GPA) and must
39550 * point to a physically contiguous block of memory.
39552 uint64_t resp_addr;
39554 uint8_t tunnel_type;
39555 /* Virtual eXtensible Local Area Network (VXLAN) */
39556 #define HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_VXLAN \
39558 /* Generic Network Virtualization Encapsulation (Geneve) */
39559 #define HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_GENEVE \
39561 /* IPV4 over virtual eXtensible Local Area Network (IPV4oVXLAN) */
39562 #define HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_VXLAN_V4 \
39564 /* Enhance Generic Routing Encapsulation (GRE version 1) inside IP datagram payload */
39565 #define HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_IPGRE_V1 \
39567 /* Use fixed layer 2 ether type of 0xFFFF */
39568 #define HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_L2_ETYPE \
39570 /* IPV6 over virtual eXtensible Local Area Network with GPE header (IPV6oVXLANGPE) */
39571 #define HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_VXLAN_GPE_V6 \
39573 #define HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_LAST \
39574 HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_VXLAN_GPE_V6
39577 * Identifier of a tunnel L4 destination port value. Only applies to tunnel
39578 * types that has l4 destination port parameters.
39580 uint16_t tunnel_dst_port_id;
39581 uint8_t unused_1[4];
39584 /* hwrm_tunnel_dst_port_free_output (size:128b/16B) */
39585 struct hwrm_tunnel_dst_port_free_output {
39586 /* The specific error status for the command. */
39587 uint16_t error_code;
39588 /* The HWRM command request type. */
39590 /* The sequence ID from the original command. */
39592 /* The length of the response data in number of bytes. */
39594 uint8_t unused_1[7];
39596 * This field is used in Output records to indicate that the output
39597 * is completely written to RAM. This field should be read as '1'
39598 * to indicate that the output has been completely written.
39599 * When writing a command completion or response to an internal processor,
39600 * the order of writes has to be such that this field is written last.
39605 /* Periodic statistics context DMA to host. */
39606 /* ctx_hw_stats (size:1280b/160B) */
39607 struct ctx_hw_stats {
39608 /* Number of received unicast packets */
39609 uint64_t rx_ucast_pkts;
39610 /* Number of received multicast packets */
39611 uint64_t rx_mcast_pkts;
39612 /* Number of received broadcast packets */
39613 uint64_t rx_bcast_pkts;
39614 /* Number of discarded packets on receive path */
39615 uint64_t rx_discard_pkts;
39616 /* Number of packets on receive path with error */
39617 uint64_t rx_error_pkts;
39618 /* Number of received bytes for unicast traffic */
39619 uint64_t rx_ucast_bytes;
39620 /* Number of received bytes for multicast traffic */
39621 uint64_t rx_mcast_bytes;
39622 /* Number of received bytes for broadcast traffic */
39623 uint64_t rx_bcast_bytes;
39624 /* Number of transmitted unicast packets */
39625 uint64_t tx_ucast_pkts;
39626 /* Number of transmitted multicast packets */
39627 uint64_t tx_mcast_pkts;
39628 /* Number of transmitted broadcast packets */
39629 uint64_t tx_bcast_pkts;
39630 /* Number of packets on transmit path with error */
39631 uint64_t tx_error_pkts;
39632 /* Number of discarded packets on transmit path */
39633 uint64_t tx_discard_pkts;
39634 /* Number of transmitted bytes for unicast traffic */
39635 uint64_t tx_ucast_bytes;
39636 /* Number of transmitted bytes for multicast traffic */
39637 uint64_t tx_mcast_bytes;
39638 /* Number of transmitted bytes for broadcast traffic */
39639 uint64_t tx_bcast_bytes;
39640 /* Number of TPA packets */
39642 /* Number of TPA bytes */
39643 uint64_t tpa_bytes;
39644 /* Number of TPA events */
39645 uint64_t tpa_events;
39646 /* Number of TPA aborts */
39647 uint64_t tpa_aborts;
39651 * Extended periodic statistics context DMA to host. On cards that
39652 * support TPA v2, additional TPA related stats exist and can be retrieved
39653 * by DMA of ctx_hw_stats_ext, rather than legacy ctx_hw_stats structure.
39655 /* ctx_hw_stats_ext (size:1344b/168B) */
39656 struct ctx_hw_stats_ext {
39657 /* Number of received unicast packets */
39658 uint64_t rx_ucast_pkts;
39659 /* Number of received multicast packets */
39660 uint64_t rx_mcast_pkts;
39661 /* Number of received broadcast packets */
39662 uint64_t rx_bcast_pkts;
39663 /* Number of discarded packets on receive path */
39664 uint64_t rx_discard_pkts;
39665 /* Number of packets on receive path with error */
39666 uint64_t rx_error_pkts;
39667 /* Number of received bytes for unicast traffic */
39668 uint64_t rx_ucast_bytes;
39669 /* Number of received bytes for multicast traffic */
39670 uint64_t rx_mcast_bytes;
39671 /* Number of received bytes for broadcast traffic */
39672 uint64_t rx_bcast_bytes;
39673 /* Number of transmitted unicast packets */
39674 uint64_t tx_ucast_pkts;
39675 /* Number of transmitted multicast packets */
39676 uint64_t tx_mcast_pkts;
39677 /* Number of transmitted broadcast packets */
39678 uint64_t tx_bcast_pkts;
39679 /* Number of packets on transmit path with error */
39680 uint64_t tx_error_pkts;
39681 /* Number of discarded packets on transmit path */
39682 uint64_t tx_discard_pkts;
39683 /* Number of transmitted bytes for unicast traffic */
39684 uint64_t tx_ucast_bytes;
39685 /* Number of transmitted bytes for multicast traffic */
39686 uint64_t tx_mcast_bytes;
39687 /* Number of transmitted bytes for broadcast traffic */
39688 uint64_t tx_bcast_bytes;
39689 /* Number of TPA eligible packets */
39690 uint64_t rx_tpa_eligible_pkt;
39691 /* Number of TPA eligible bytes */
39692 uint64_t rx_tpa_eligible_bytes;
39693 /* Number of TPA packets */
39694 uint64_t rx_tpa_pkt;
39695 /* Number of TPA bytes */
39696 uint64_t rx_tpa_bytes;
39697 /* Number of TPA errors */
39698 uint64_t rx_tpa_errors;
39701 /* Periodic Engine statistics context DMA to host. */
39702 /* ctx_eng_stats (size:512b/64B) */
39703 struct ctx_eng_stats {
39705 * Count of data bytes into the Engine.
39706 * This includes any user supplied prefix,
39707 * but does not include any predefined
39710 uint64_t eng_bytes_in;
39711 /* Count of data bytes out of the Engine. */
39712 uint64_t eng_bytes_out;
39714 * Count, in 4-byte (dword) units, of bytes
39715 * that are input as auxiliary data.
39716 * This includes the aux_cmd data.
39718 uint64_t aux_bytes_in;
39720 * Count, in 4-byte (dword) units, of bytes
39721 * that are output as auxiliary data.
39722 * This count is the buffer space for aux_data
39723 * output provided in the RQE, not the actual
39726 uint64_t aux_bytes_out;
39727 /* Count of number of commands executed. */
39730 * Count of number of error commands.
39731 * These are the commands with a
39732 * non-zero status value.
39734 uint64_t error_commands;
39736 * Compression/Encryption Engine usage,
39737 * the unit is count of clock cycles
39739 uint64_t cce_engine_usage;
39741 * De-Compression/De-cryption Engine usage,
39742 * the unit is count of clock cycles
39744 uint64_t cdd_engine_usage;
39747 /***********************
39748 * hwrm_stat_ctx_alloc *
39749 ***********************/
39752 /* hwrm_stat_ctx_alloc_input (size:256b/32B) */
39753 struct hwrm_stat_ctx_alloc_input {
39754 /* The HWRM command request type. */
39757 * The completion ring to send the completion event on. This should
39758 * be the NQ ID returned from the `nq_alloc` HWRM command.
39760 uint16_t cmpl_ring;
39762 * The sequence ID is used by the driver for tracking multiple
39763 * commands. This ID is treated as opaque data by the firmware and
39764 * the value is returned in the `hwrm_resp_hdr` upon completion.
39768 * The target ID of the command:
39769 * * 0x0-0xFFF8 - The function ID
39770 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
39771 * * 0xFFFD - Reserved for user-space HWRM interface
39774 uint16_t target_id;
39776 * A physical address pointer pointing to a host buffer that the
39777 * command's response data will be written. This can be either a host
39778 * physical address (HPA) or a guest physical address (GPA) and must
39779 * point to a physically contiguous block of memory.
39781 uint64_t resp_addr;
39783 * This is the address for statistic block.
39784 * > For new versions of the chip, this address should be 128B
39787 uint64_t stats_dma_addr;
39789 * The statistic block update period in ms.
39790 * e.g. 250ms, 500ms, 750ms, 1000ms.
39791 * If update_period_ms is 0, then the stats update
39792 * shall be never done and the DMA address shall not be used.
39793 * In this case, the stat block can only be read by
39794 * hwrm_stat_ctx_query command.
39795 * On Ethernet/L2 based devices:
39796 * if tpa v2 supported (hwrm_vnic_qcaps[max_aggs_supported]>0),
39797 * ctx_hw_stats_ext is used for DMA,
39799 * ctx_hw_stats is used for DMA.
39801 uint32_t update_period_ms;
39803 * This field is used to specify statistics context specific
39804 * configuration flags.
39806 uint8_t stat_ctx_flags;
39808 * When this bit is set to '1', the statistics context shall be
39809 * allocated for RoCE traffic only. In this case, traffic other
39810 * than offloaded RoCE traffic shall not be included in this
39811 * statistic context.
39812 * When this bit is set to '0', the statistics context shall be
39813 * used for network traffic or engine traffic.
39815 #define HWRM_STAT_CTX_ALLOC_INPUT_STAT_CTX_FLAGS_ROCE UINT32_C(0x1)
39818 * This is the size of the structure (ctx_hw_stats or
39819 * ctx_hw_stats_ext) that the driver has allocated to be used
39820 * for the periodic DMA updates.
39822 uint16_t stats_dma_length;
39825 /* hwrm_stat_ctx_alloc_output (size:128b/16B) */
39826 struct hwrm_stat_ctx_alloc_output {
39827 /* The specific error status for the command. */
39828 uint16_t error_code;
39829 /* The HWRM command request type. */
39831 /* The sequence ID from the original command. */
39833 /* The length of the response data in number of bytes. */
39835 /* This is the statistics context ID value. */
39836 uint32_t stat_ctx_id;
39837 uint8_t unused_0[3];
39839 * This field is used in Output records to indicate that the output
39840 * is completely written to RAM. This field should be read as '1'
39841 * to indicate that the output has been completely written.
39842 * When writing a command completion or response to an internal processor,
39843 * the order of writes has to be such that this field is written last.
39848 /**********************
39849 * hwrm_stat_ctx_free *
39850 **********************/
39853 /* hwrm_stat_ctx_free_input (size:192b/24B) */
39854 struct hwrm_stat_ctx_free_input {
39855 /* The HWRM command request type. */
39858 * The completion ring to send the completion event on. This should
39859 * be the NQ ID returned from the `nq_alloc` HWRM command.
39861 uint16_t cmpl_ring;
39863 * The sequence ID is used by the driver for tracking multiple
39864 * commands. This ID is treated as opaque data by the firmware and
39865 * the value is returned in the `hwrm_resp_hdr` upon completion.
39869 * The target ID of the command:
39870 * * 0x0-0xFFF8 - The function ID
39871 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
39872 * * 0xFFFD - Reserved for user-space HWRM interface
39875 uint16_t target_id;
39877 * A physical address pointer pointing to a host buffer that the
39878 * command's response data will be written. This can be either a host
39879 * physical address (HPA) or a guest physical address (GPA) and must
39880 * point to a physically contiguous block of memory.
39882 uint64_t resp_addr;
39883 /* ID of the statistics context that is being queried. */
39884 uint32_t stat_ctx_id;
39885 uint8_t unused_0[4];
39888 /* hwrm_stat_ctx_free_output (size:128b/16B) */
39889 struct hwrm_stat_ctx_free_output {
39890 /* The specific error status for the command. */
39891 uint16_t error_code;
39892 /* The HWRM command request type. */
39894 /* The sequence ID from the original command. */
39896 /* The length of the response data in number of bytes. */
39898 /* This is the statistics context ID value. */
39899 uint32_t stat_ctx_id;
39900 uint8_t unused_0[3];
39902 * This field is used in Output records to indicate that the output
39903 * is completely written to RAM. This field should be read as '1'
39904 * to indicate that the output has been completely written.
39905 * When writing a command completion or response to an internal processor,
39906 * the order of writes has to be such that this field is written last.
39911 /***********************
39912 * hwrm_stat_ctx_query *
39913 ***********************/
39916 /* hwrm_stat_ctx_query_input (size:192b/24B) */
39917 struct hwrm_stat_ctx_query_input {
39918 /* The HWRM command request type. */
39921 * The completion ring to send the completion event on. This should
39922 * be the NQ ID returned from the `nq_alloc` HWRM command.
39924 uint16_t cmpl_ring;
39926 * The sequence ID is used by the driver for tracking multiple
39927 * commands. This ID is treated as opaque data by the firmware and
39928 * the value is returned in the `hwrm_resp_hdr` upon completion.
39932 * The target ID of the command:
39933 * * 0x0-0xFFF8 - The function ID
39934 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
39935 * * 0xFFFD - Reserved for user-space HWRM interface
39938 uint16_t target_id;
39940 * A physical address pointer pointing to a host buffer that the
39941 * command's response data will be written. This can be either a host
39942 * physical address (HPA) or a guest physical address (GPA) and must
39943 * point to a physically contiguous block of memory.
39945 uint64_t resp_addr;
39946 /* ID of the statistics context that is being queried. */
39947 uint32_t stat_ctx_id;
39950 * This bit is set to 1 when request is for a counter mask,
39951 * representing the width of each of the stats counters, rather
39952 * than counters themselves.
39954 #define HWRM_STAT_CTX_QUERY_INPUT_FLAGS_COUNTER_MASK UINT32_C(0x1)
39955 uint8_t unused_0[3];
39958 /* hwrm_stat_ctx_query_output (size:1408b/176B) */
39959 struct hwrm_stat_ctx_query_output {
39960 /* The specific error status for the command. */
39961 uint16_t error_code;
39962 /* The HWRM command request type. */
39964 /* The sequence ID from the original command. */
39966 /* The length of the response data in number of bytes. */
39968 /* Number of transmitted unicast packets */
39969 uint64_t tx_ucast_pkts;
39970 /* Number of transmitted multicast packets */
39971 uint64_t tx_mcast_pkts;
39972 /* Number of transmitted broadcast packets */
39973 uint64_t tx_bcast_pkts;
39974 /* Number of transmitted packets with error */
39975 uint64_t tx_err_pkts;
39976 /* Number of dropped packets on transmit path */
39977 uint64_t tx_drop_pkts;
39978 /* Number of transmitted bytes for unicast traffic */
39979 uint64_t tx_ucast_bytes;
39980 /* Number of transmitted bytes for multicast traffic */
39981 uint64_t tx_mcast_bytes;
39982 /* Number of transmitted bytes for broadcast traffic */
39983 uint64_t tx_bcast_bytes;
39984 /* Number of received unicast packets */
39985 uint64_t rx_ucast_pkts;
39986 /* Number of received multicast packets */
39987 uint64_t rx_mcast_pkts;
39988 /* Number of received broadcast packets */
39989 uint64_t rx_bcast_pkts;
39990 /* Number of received packets with error */
39991 uint64_t rx_err_pkts;
39992 /* Number of dropped packets on receive path */
39993 uint64_t rx_drop_pkts;
39994 /* Number of received bytes for unicast traffic */
39995 uint64_t rx_ucast_bytes;
39996 /* Number of received bytes for multicast traffic */
39997 uint64_t rx_mcast_bytes;
39998 /* Number of received bytes for broadcast traffic */
39999 uint64_t rx_bcast_bytes;
40000 /* Number of aggregated unicast packets */
40001 uint64_t rx_agg_pkts;
40002 /* Number of aggregated unicast bytes */
40003 uint64_t rx_agg_bytes;
40004 /* Number of aggregation events */
40005 uint64_t rx_agg_events;
40006 /* Number of aborted aggregations */
40007 uint64_t rx_agg_aborts;
40008 uint8_t unused_0[7];
40010 * This field is used in Output records to indicate that the output
40011 * is completely written to RAM. This field should be read as '1'
40012 * to indicate that the output has been completely written.
40013 * When writing a command completion or response to an internal processor,
40014 * the order of writes has to be such that this field is written last.
40019 /***************************
40020 * hwrm_stat_ext_ctx_query *
40021 ***************************/
40024 /* hwrm_stat_ext_ctx_query_input (size:192b/24B) */
40025 struct hwrm_stat_ext_ctx_query_input {
40026 /* The HWRM command request type. */
40029 * The completion ring to send the completion event on. This should
40030 * be the NQ ID returned from the `nq_alloc` HWRM command.
40032 uint16_t cmpl_ring;
40034 * The sequence ID is used by the driver for tracking multiple
40035 * commands. This ID is treated as opaque data by the firmware and
40036 * the value is returned in the `hwrm_resp_hdr` upon completion.
40040 * The target ID of the command:
40041 * * 0x0-0xFFF8 - The function ID
40042 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
40043 * * 0xFFFD - Reserved for user-space HWRM interface
40046 uint16_t target_id;
40048 * A physical address pointer pointing to a host buffer that the
40049 * command's response data will be written. This can be either a host
40050 * physical address (HPA) or a guest physical address (GPA) and must
40051 * point to a physically contiguous block of memory.
40053 uint64_t resp_addr;
40054 /* ID of the extended statistics context that is being queried. */
40055 uint32_t stat_ctx_id;
40058 * This bit is set to 1 when request is for a counter mask,
40059 * representing the width of each of the stats counters, rather
40060 * than counters themselves.
40062 #define HWRM_STAT_EXT_CTX_QUERY_INPUT_FLAGS_COUNTER_MASK \
40064 uint8_t unused_0[3];
40067 /* hwrm_stat_ext_ctx_query_output (size:1472b/184B) */
40068 struct hwrm_stat_ext_ctx_query_output {
40069 /* The specific error status for the command. */
40070 uint16_t error_code;
40071 /* The HWRM command request type. */
40073 /* The sequence ID from the original command. */
40075 /* The length of the response data in number of bytes. */
40077 /* Number of received unicast packets */
40078 uint64_t rx_ucast_pkts;
40079 /* Number of received multicast packets */
40080 uint64_t rx_mcast_pkts;
40081 /* Number of received broadcast packets */
40082 uint64_t rx_bcast_pkts;
40083 /* Number of discarded packets on receive path */
40084 uint64_t rx_discard_pkts;
40085 /* Number of packets on receive path with error */
40086 uint64_t rx_error_pkts;
40087 /* Number of received bytes for unicast traffic */
40088 uint64_t rx_ucast_bytes;
40089 /* Number of received bytes for multicast traffic */
40090 uint64_t rx_mcast_bytes;
40091 /* Number of received bytes for broadcast traffic */
40092 uint64_t rx_bcast_bytes;
40093 /* Number of transmitted unicast packets */
40094 uint64_t tx_ucast_pkts;
40095 /* Number of transmitted multicast packets */
40096 uint64_t tx_mcast_pkts;
40097 /* Number of transmitted broadcast packets */
40098 uint64_t tx_bcast_pkts;
40099 /* Number of packets on transmit path with error */
40100 uint64_t tx_error_pkts;
40101 /* Number of discarded packets on transmit path */
40102 uint64_t tx_discard_pkts;
40103 /* Number of transmitted bytes for unicast traffic */
40104 uint64_t tx_ucast_bytes;
40105 /* Number of transmitted bytes for multicast traffic */
40106 uint64_t tx_mcast_bytes;
40107 /* Number of transmitted bytes for broadcast traffic */
40108 uint64_t tx_bcast_bytes;
40109 /* Number of TPA eligible packets */
40110 uint64_t rx_tpa_eligible_pkt;
40111 /* Number of TPA eligible bytes */
40112 uint64_t rx_tpa_eligible_bytes;
40113 /* Number of TPA packets */
40114 uint64_t rx_tpa_pkt;
40115 /* Number of TPA bytes */
40116 uint64_t rx_tpa_bytes;
40117 /* Number of TPA errors */
40118 uint64_t rx_tpa_errors;
40119 uint8_t unused_0[7];
40121 * This field is used in Output records to indicate that the output
40122 * is completely written to RAM. This field should be read as '1'
40123 * to indicate that the output has been completely written.
40124 * When writing a command completion or response to an internal processor,
40125 * the order of writes has to be such that this field is written last.
40130 /***************************
40131 * hwrm_stat_ctx_eng_query *
40132 ***************************/
40135 /* hwrm_stat_ctx_eng_query_input (size:192b/24B) */
40136 struct hwrm_stat_ctx_eng_query_input {
40137 /* The HWRM command request type. */
40140 * The completion ring to send the completion event on. This should
40141 * be the NQ ID returned from the `nq_alloc` HWRM command.
40143 uint16_t cmpl_ring;
40145 * The sequence ID is used by the driver for tracking multiple
40146 * commands. This ID is treated as opaque data by the firmware and
40147 * the value is returned in the `hwrm_resp_hdr` upon completion.
40151 * The target ID of the command:
40152 * * 0x0-0xFFF8 - The function ID
40153 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
40154 * * 0xFFFD - Reserved for user-space HWRM interface
40157 uint16_t target_id;
40159 * A physical address pointer pointing to a host buffer that the
40160 * command's response data will be written. This can be either a host
40161 * physical address (HPA) or a guest physical address (GPA) and must
40162 * point to a physically contiguous block of memory.
40164 uint64_t resp_addr;
40165 /* ID of the statistics context that is being queried. */
40166 uint32_t stat_ctx_id;
40167 uint8_t unused_0[4];
40170 /* hwrm_stat_ctx_eng_query_output (size:640b/80B) */
40171 struct hwrm_stat_ctx_eng_query_output {
40172 /* The specific error status for the command. */
40173 uint16_t error_code;
40174 /* The HWRM command request type. */
40176 /* The sequence ID from the original command. */
40178 /* The length of the response data in number of bytes. */
40181 * Count of data bytes into the Engine.
40182 * This includes any user supplied prefix,
40183 * but does not include any predefined
40186 uint64_t eng_bytes_in;
40187 /* Count of data bytes out of the Engine. */
40188 uint64_t eng_bytes_out;
40190 * Count, in 4-byte (dword) units, of bytes
40191 * that are input as auxiliary data.
40192 * This includes the aux_cmd data.
40194 uint64_t aux_bytes_in;
40196 * Count, in 4-byte (dword) units, of bytes
40197 * that are output as auxiliary data.
40198 * This count is the buffer space for aux_data
40199 * output provided in the RQE, not the actual
40202 uint64_t aux_bytes_out;
40203 /* Count of number of commands executed. */
40206 * Count of number of error commands.
40207 * These are the commands with a
40208 * non-zero status value.
40210 uint64_t error_commands;
40212 * Compression/Encryption Engine usage,
40213 * the unit is count of clock cycles
40215 uint64_t cce_engine_usage;
40217 * De-Compression/De-cryption Engine usage,
40218 * the unit is count of clock cycles
40220 uint64_t cdd_engine_usage;
40221 uint8_t unused_0[7];
40223 * This field is used in Output records to indicate that the output
40224 * is completely written to RAM. This field should be read as '1'
40225 * to indicate that the output has been completely written.
40226 * When writing a command completion or response to an internal processor,
40227 * the order of writes has to be such that this field is written last.
40232 /***************************
40233 * hwrm_stat_ctx_clr_stats *
40234 ***************************/
40237 /* hwrm_stat_ctx_clr_stats_input (size:192b/24B) */
40238 struct hwrm_stat_ctx_clr_stats_input {
40239 /* The HWRM command request type. */
40242 * The completion ring to send the completion event on. This should
40243 * be the NQ ID returned from the `nq_alloc` HWRM command.
40245 uint16_t cmpl_ring;
40247 * The sequence ID is used by the driver for tracking multiple
40248 * commands. This ID is treated as opaque data by the firmware and
40249 * the value is returned in the `hwrm_resp_hdr` upon completion.
40253 * The target ID of the command:
40254 * * 0x0-0xFFF8 - The function ID
40255 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
40256 * * 0xFFFD - Reserved for user-space HWRM interface
40259 uint16_t target_id;
40261 * A physical address pointer pointing to a host buffer that the
40262 * command's response data will be written. This can be either a host
40263 * physical address (HPA) or a guest physical address (GPA) and must
40264 * point to a physically contiguous block of memory.
40266 uint64_t resp_addr;
40267 /* ID of the statistics context that is being queried. */
40268 uint32_t stat_ctx_id;
40269 uint8_t unused_0[4];
40272 /* hwrm_stat_ctx_clr_stats_output (size:128b/16B) */
40273 struct hwrm_stat_ctx_clr_stats_output {
40274 /* The specific error status for the command. */
40275 uint16_t error_code;
40276 /* The HWRM command request type. */
40278 /* The sequence ID from the original command. */
40280 /* The length of the response data in number of bytes. */
40282 uint8_t unused_0[7];
40284 * This field is used in Output records to indicate that the output
40285 * is completely written to RAM. This field should be read as '1'
40286 * to indicate that the output has been completely written.
40287 * When writing a command completion or response to an internal processor,
40288 * the order of writes has to be such that this field is written last.
40293 /********************
40294 * hwrm_pcie_qstats *
40295 ********************/
40298 /* hwrm_pcie_qstats_input (size:256b/32B) */
40299 struct hwrm_pcie_qstats_input {
40300 /* The HWRM command request type. */
40303 * The completion ring to send the completion event on. This should
40304 * be the NQ ID returned from the `nq_alloc` HWRM command.
40306 uint16_t cmpl_ring;
40308 * The sequence ID is used by the driver for tracking multiple
40309 * commands. This ID is treated as opaque data by the firmware and
40310 * the value is returned in the `hwrm_resp_hdr` upon completion.
40314 * The target ID of the command:
40315 * * 0x0-0xFFF8 - The function ID
40316 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
40317 * * 0xFFFD - Reserved for user-space HWRM interface
40320 uint16_t target_id;
40322 * A physical address pointer pointing to a host buffer that the
40323 * command's response data will be written. This can be either a host
40324 * physical address (HPA) or a guest physical address (GPA) and must
40325 * point to a physically contiguous block of memory.
40327 uint64_t resp_addr;
40329 * The size of PCIe statistics block in bytes.
40330 * Firmware will DMA the PCIe statistics to
40331 * the host with this field size in the response.
40333 uint16_t pcie_stat_size;
40334 uint8_t unused_0[6];
40336 * This is the host address where
40337 * PCIe statistics will be stored
40339 uint64_t pcie_stat_host_addr;
40342 /* hwrm_pcie_qstats_output (size:128b/16B) */
40343 struct hwrm_pcie_qstats_output {
40344 /* The specific error status for the command. */
40345 uint16_t error_code;
40346 /* The HWRM command request type. */
40348 /* The sequence ID from the original command. */
40350 /* The length of the response data in number of bytes. */
40352 /* The size of PCIe statistics block in bytes. */
40353 uint16_t pcie_stat_size;
40354 uint8_t unused_0[5];
40356 * This field is used in Output records to indicate that the output
40357 * is completely written to RAM. This field should be read as '1'
40358 * to indicate that the output has been completely written.
40359 * When writing a command completion or response to an internal processor,
40360 * the order of writes has to be such that this field is written last.
40365 /* PCIe Statistics Formats */
40366 /* pcie_ctx_hw_stats (size:768b/96B) */
40367 struct pcie_ctx_hw_stats {
40368 /* Number of physical layer receiver errors */
40369 uint64_t pcie_pl_signal_integrity;
40370 /* Number of DLLP CRC errors detected by Data Link Layer */
40371 uint64_t pcie_dl_signal_integrity;
40373 * Number of TLP LCRC and sequence number errors detected
40374 * by Data Link Layer
40376 uint64_t pcie_tl_signal_integrity;
40377 /* Number of times LTSSM entered Recovery state */
40378 uint64_t pcie_link_integrity;
40379 /* Report number of TLP bits that have been transmitted in Mbps */
40380 uint64_t pcie_tx_traffic_rate;
40381 /* Report number of TLP bits that have been received in Mbps */
40382 uint64_t pcie_rx_traffic_rate;
40383 /* Number of DLLP bytes that have been transmitted */
40384 uint64_t pcie_tx_dllp_statistics;
40385 /* Number of DLLP bytes that have been received */
40386 uint64_t pcie_rx_dllp_statistics;
40388 * Number of times spent in each phase of gen3
40391 uint64_t pcie_equalization_time;
40392 /* Records the last 16 transitions of the LTSSM */
40393 uint32_t pcie_ltssm_histogram[4];
40395 * Record the last 8 reasons on why LTSSM transitioned
40398 uint64_t pcie_recovery_histogram;
40401 /**********************
40402 * hwrm_exec_fwd_resp *
40403 **********************/
40406 /* hwrm_exec_fwd_resp_input (size:1024b/128B) */
40407 struct hwrm_exec_fwd_resp_input {
40408 /* The HWRM command request type. */
40411 * The completion ring to send the completion event on. This should
40412 * be the NQ ID returned from the `nq_alloc` HWRM command.
40414 uint16_t cmpl_ring;
40416 * The sequence ID is used by the driver for tracking multiple
40417 * commands. This ID is treated as opaque data by the firmware and
40418 * the value is returned in the `hwrm_resp_hdr` upon completion.
40422 * The target ID of the command:
40423 * * 0x0-0xFFF8 - The function ID
40424 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
40425 * * 0xFFFD - Reserved for user-space HWRM interface
40428 uint16_t target_id;
40430 * A physical address pointer pointing to a host buffer that the
40431 * command's response data will be written. This can be either a host
40432 * physical address (HPA) or a guest physical address (GPA) and must
40433 * point to a physically contiguous block of memory.
40435 uint64_t resp_addr;
40437 * This is an encapsulated request. This request should
40438 * be executed by the HWRM and the response should be
40439 * provided in the response buffer inside the encapsulated
40442 uint32_t encap_request[26];
40444 * This value indicates the target id of the response to
40445 * the encapsulated request.
40446 * 0x0 - 0xFFF8 - Used for function ids
40447 * 0xFFF8 - 0xFFFE - Reserved for internal processors
40450 uint16_t encap_resp_target_id;
40451 uint8_t unused_0[6];
40454 /* hwrm_exec_fwd_resp_output (size:128b/16B) */
40455 struct hwrm_exec_fwd_resp_output {
40456 /* The specific error status for the command. */
40457 uint16_t error_code;
40458 /* The HWRM command request type. */
40460 /* The sequence ID from the original command. */
40462 /* The length of the response data in number of bytes. */
40464 uint8_t unused_0[7];
40466 * This field is used in Output records to indicate that the output
40467 * is completely written to RAM. This field should be read as '1'
40468 * to indicate that the output has been completely written.
40469 * When writing a command completion or response to an internal processor,
40470 * the order of writes has to be such that this field is written last.
40475 /************************
40476 * hwrm_reject_fwd_resp *
40477 ************************/
40480 /* hwrm_reject_fwd_resp_input (size:1024b/128B) */
40481 struct hwrm_reject_fwd_resp_input {
40482 /* The HWRM command request type. */
40485 * The completion ring to send the completion event on. This should
40486 * be the NQ ID returned from the `nq_alloc` HWRM command.
40488 uint16_t cmpl_ring;
40490 * The sequence ID is used by the driver for tracking multiple
40491 * commands. This ID is treated as opaque data by the firmware and
40492 * the value is returned in the `hwrm_resp_hdr` upon completion.
40496 * The target ID of the command:
40497 * * 0x0-0xFFF8 - The function ID
40498 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
40499 * * 0xFFFD - Reserved for user-space HWRM interface
40502 uint16_t target_id;
40504 * A physical address pointer pointing to a host buffer that the
40505 * command's response data will be written. This can be either a host
40506 * physical address (HPA) or a guest physical address (GPA) and must
40507 * point to a physically contiguous block of memory.
40509 uint64_t resp_addr;
40511 * This is an encapsulated request. This request should
40512 * be rejected by the HWRM and the error response should be
40513 * provided in the response buffer inside the encapsulated
40516 uint32_t encap_request[26];
40518 * This value indicates the target id of the response to
40519 * the encapsulated request.
40520 * 0x0 - 0xFFF8 - Used for function ids
40521 * 0xFFF8 - 0xFFFE - Reserved for internal processors
40524 uint16_t encap_resp_target_id;
40525 uint8_t unused_0[6];
40528 /* hwrm_reject_fwd_resp_output (size:128b/16B) */
40529 struct hwrm_reject_fwd_resp_output {
40530 /* The specific error status for the command. */
40531 uint16_t error_code;
40532 /* The HWRM command request type. */
40534 /* The sequence ID from the original command. */
40536 /* The length of the response data in number of bytes. */
40538 uint8_t unused_0[7];
40540 * This field is used in Output records to indicate that the output
40541 * is completely written to RAM. This field should be read as '1'
40542 * to indicate that the output has been completely written.
40543 * When writing a command completion or response to an internal processor,
40544 * the order of writes has to be such that this field is written last.
40554 /* hwrm_fwd_resp_input (size:1024b/128B) */
40555 struct hwrm_fwd_resp_input {
40556 /* The HWRM command request type. */
40559 * The completion ring to send the completion event on. This should
40560 * be the NQ ID returned from the `nq_alloc` HWRM command.
40562 uint16_t cmpl_ring;
40564 * The sequence ID is used by the driver for tracking multiple
40565 * commands. This ID is treated as opaque data by the firmware and
40566 * the value is returned in the `hwrm_resp_hdr` upon completion.
40570 * The target ID of the command:
40571 * * 0x0-0xFFF8 - The function ID
40572 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
40573 * * 0xFFFD - Reserved for user-space HWRM interface
40576 uint16_t target_id;
40578 * A physical address pointer pointing to a host buffer that the
40579 * command's response data will be written. This can be either a host
40580 * physical address (HPA) or a guest physical address (GPA) and must
40581 * point to a physically contiguous block of memory.
40583 uint64_t resp_addr;
40585 * This value indicates the target id of the encapsulated
40587 * 0x0 - 0xFFF8 - Used for function ids
40588 * 0xFFF8 - 0xFFFE - Reserved for internal processors
40591 uint16_t encap_resp_target_id;
40593 * This value indicates the completion ring the encapsulated
40594 * response will be optionally completed on. If the value is
40595 * -1, then no CR completion shall be generated for the
40596 * encapsulated response. Any other value must be a
40597 * valid CR ring_id value. If a valid encap_resp_cmpl_ring
40598 * is provided, then a CR completion shall be generated for
40599 * the encapsulated response.
40601 uint16_t encap_resp_cmpl_ring;
40602 /* This field indicates the length of encapsulated response. */
40603 uint16_t encap_resp_len;
40607 * This is the host address where the encapsulated response
40609 * This area must be 16B aligned and must be cleared to zero
40610 * before the original request is made.
40612 uint64_t encap_resp_addr;
40613 /* This is an encapsulated response. */
40614 uint32_t encap_resp[24];
40617 /* hwrm_fwd_resp_output (size:128b/16B) */
40618 struct hwrm_fwd_resp_output {
40619 /* The specific error status for the command. */
40620 uint16_t error_code;
40621 /* The HWRM command request type. */
40623 /* The sequence ID from the original command. */
40625 /* The length of the response data in number of bytes. */
40627 uint8_t unused_0[7];
40629 * This field is used in Output records to indicate that the output
40630 * is completely written to RAM. This field should be read as '1'
40631 * to indicate that the output has been completely written.
40632 * When writing a command completion or response to an internal processor,
40633 * the order of writes has to be such that this field is written last.
40638 /*****************************
40639 * hwrm_fwd_async_event_cmpl *
40640 *****************************/
40643 /* hwrm_fwd_async_event_cmpl_input (size:320b/40B) */
40644 struct hwrm_fwd_async_event_cmpl_input {
40645 /* The HWRM command request type. */
40648 * The completion ring to send the completion event on. This should
40649 * be the NQ ID returned from the `nq_alloc` HWRM command.
40651 uint16_t cmpl_ring;
40653 * The sequence ID is used by the driver for tracking multiple
40654 * commands. This ID is treated as opaque data by the firmware and
40655 * the value is returned in the `hwrm_resp_hdr` upon completion.
40659 * The target ID of the command:
40660 * * 0x0-0xFFF8 - The function ID
40661 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
40662 * * 0xFFFD - Reserved for user-space HWRM interface
40665 uint16_t target_id;
40667 * A physical address pointer pointing to a host buffer that the
40668 * command's response data will be written. This can be either a host
40669 * physical address (HPA) or a guest physical address (GPA) and must
40670 * point to a physically contiguous block of memory.
40672 uint64_t resp_addr;
40674 * This value indicates the target id of the encapsulated
40675 * asynchronous event.
40676 * 0x0 - 0xFFF8 - Used for function ids
40677 * 0xFFF8 - 0xFFFE - Reserved for internal processors
40678 * 0xFFFF - Broadcast to all children VFs (only applicable when
40679 * a PF is the requester)
40681 uint16_t encap_async_event_target_id;
40682 uint8_t unused_0[6];
40683 /* This is an encapsulated asynchronous event completion. */
40684 uint32_t encap_async_event_cmpl[4];
40687 /* hwrm_fwd_async_event_cmpl_output (size:128b/16B) */
40688 struct hwrm_fwd_async_event_cmpl_output {
40689 /* The specific error status for the command. */
40690 uint16_t error_code;
40691 /* The HWRM command request type. */
40693 /* The sequence ID from the original command. */
40695 /* The length of the response data in number of bytes. */
40697 uint8_t unused_0[7];
40699 * This field is used in Output records to indicate that the output
40700 * is completely written to RAM. This field should be read as '1'
40701 * to indicate that the output has been completely written.
40702 * When writing a command completion or response to an internal processor,
40703 * the order of writes has to be such that this field is written last.
40708 /**************************
40709 * hwrm_nvm_raw_write_blk *
40710 **************************/
40713 /* hwrm_nvm_raw_write_blk_input (size:256b/32B) */
40714 struct hwrm_nvm_raw_write_blk_input {
40715 /* The HWRM command request type. */
40718 * The completion ring to send the completion event on. This should
40719 * be the NQ ID returned from the `nq_alloc` HWRM command.
40721 uint16_t cmpl_ring;
40723 * The sequence ID is used by the driver for tracking multiple
40724 * commands. This ID is treated as opaque data by the firmware and
40725 * the value is returned in the `hwrm_resp_hdr` upon completion.
40729 * The target ID of the command:
40730 * * 0x0-0xFFF8 - The function ID
40731 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
40732 * * 0xFFFD - Reserved for user-space HWRM interface
40735 uint16_t target_id;
40737 * A physical address pointer pointing to a host buffer that the
40738 * command's response data will be written. This can be either a host
40739 * physical address (HPA) or a guest physical address (GPA) and must
40740 * point to a physically contiguous block of memory.
40742 uint64_t resp_addr;
40744 * 64-bit Host Source Address.
40745 * This is the location of the source data to be written.
40747 uint64_t host_src_addr;
40749 * 32-bit Destination Address.
40750 * This is the NVRAM byte-offset where the source data will be written to.
40752 uint32_t dest_addr;
40753 /* Length of data to be written, in bytes. */
40757 /* hwrm_nvm_raw_write_blk_output (size:128b/16B) */
40758 struct hwrm_nvm_raw_write_blk_output {
40759 /* The specific error status for the command. */
40760 uint16_t error_code;
40761 /* The HWRM command request type. */
40763 /* The sequence ID from the original command. */
40765 /* The length of the response data in number of bytes. */
40767 uint8_t unused_0[7];
40769 * This field is used in Output records to indicate that the output
40770 * is completely written to RAM. This field should be read as '1'
40771 * to indicate that the output has been completely written.
40772 * When writing a command completion or response to an internal processor,
40773 * the order of writes has to be such that this field is written last.
40783 /* hwrm_nvm_read_input (size:320b/40B) */
40784 struct hwrm_nvm_read_input {
40785 /* The HWRM command request type. */
40788 * The completion ring to send the completion event on. This should
40789 * be the NQ ID returned from the `nq_alloc` HWRM command.
40791 uint16_t cmpl_ring;
40793 * The sequence ID is used by the driver for tracking multiple
40794 * commands. This ID is treated as opaque data by the firmware and
40795 * the value is returned in the `hwrm_resp_hdr` upon completion.
40799 * The target ID of the command:
40800 * * 0x0-0xFFF8 - The function ID
40801 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
40802 * * 0xFFFD - Reserved for user-space HWRM interface
40805 uint16_t target_id;
40807 * A physical address pointer pointing to a host buffer that the
40808 * command's response data will be written. This can be either a host
40809 * physical address (HPA) or a guest physical address (GPA) and must
40810 * point to a physically contiguous block of memory.
40812 uint64_t resp_addr;
40814 * 64-bit Host Destination Address.
40815 * This is the host address where the data will be written to.
40817 uint64_t host_dest_addr;
40818 /* The 0-based index of the directory entry. */
40820 uint8_t unused_0[2];
40821 /* The NVRAM byte-offset to read from. */
40823 /* The length of the data to be read, in bytes. */
40825 uint8_t unused_1[4];
40828 /* hwrm_nvm_read_output (size:128b/16B) */
40829 struct hwrm_nvm_read_output {
40830 /* The specific error status for the command. */
40831 uint16_t error_code;
40832 /* The HWRM command request type. */
40834 /* The sequence ID from the original command. */
40836 /* The length of the response data in number of bytes. */
40838 uint8_t unused_0[7];
40840 * This field is used in Output records to indicate that the output
40841 * is completely written to RAM. This field should be read as '1'
40842 * to indicate that the output has been completely written.
40843 * When writing a command completion or response to an internal processor,
40844 * the order of writes has to be such that this field is written last.
40849 /*********************
40850 * hwrm_nvm_raw_dump *
40851 *********************/
40854 /* hwrm_nvm_raw_dump_input (size:256b/32B) */
40855 struct hwrm_nvm_raw_dump_input {
40856 /* The HWRM command request type. */
40859 * The completion ring to send the completion event on. This should
40860 * be the NQ ID returned from the `nq_alloc` HWRM command.
40862 uint16_t cmpl_ring;
40864 * The sequence ID is used by the driver for tracking multiple
40865 * commands. This ID is treated as opaque data by the firmware and
40866 * the value is returned in the `hwrm_resp_hdr` upon completion.
40870 * The target ID of the command:
40871 * * 0x0-0xFFF8 - The function ID
40872 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
40873 * * 0xFFFD - Reserved for user-space HWRM interface
40876 uint16_t target_id;
40878 * A physical address pointer pointing to a host buffer that the
40879 * command's response data will be written. This can be either a host
40880 * physical address (HPA) or a guest physical address (GPA) and must
40881 * point to a physically contiguous block of memory.
40883 uint64_t resp_addr;
40885 * 64-bit Host Destination Address.
40886 * This is the host address where the data will be written to.
40888 uint64_t host_dest_addr;
40889 /* 32-bit NVRAM byte-offset to read from. */
40891 /* Total length of NVRAM contents to be read, in bytes. */
40895 /* hwrm_nvm_raw_dump_output (size:128b/16B) */
40896 struct hwrm_nvm_raw_dump_output {
40897 /* The specific error status for the command. */
40898 uint16_t error_code;
40899 /* The HWRM command request type. */
40901 /* The sequence ID from the original command. */
40903 /* The length of the response data in number of bytes. */
40905 uint8_t unused_0[7];
40907 * This field is used in Output records to indicate that the output
40908 * is completely written to RAM. This field should be read as '1'
40909 * to indicate that the output has been completely written.
40910 * When writing a command completion or response to an internal processor,
40911 * the order of writes has to be such that this field is written last.
40916 /****************************
40917 * hwrm_nvm_get_dir_entries *
40918 ****************************/
40921 /* hwrm_nvm_get_dir_entries_input (size:192b/24B) */
40922 struct hwrm_nvm_get_dir_entries_input {
40923 /* The HWRM command request type. */
40926 * The completion ring to send the completion event on. This should
40927 * be the NQ ID returned from the `nq_alloc` HWRM command.
40929 uint16_t cmpl_ring;
40931 * The sequence ID is used by the driver for tracking multiple
40932 * commands. This ID is treated as opaque data by the firmware and
40933 * the value is returned in the `hwrm_resp_hdr` upon completion.
40937 * The target ID of the command:
40938 * * 0x0-0xFFF8 - The function ID
40939 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
40940 * * 0xFFFD - Reserved for user-space HWRM interface
40943 uint16_t target_id;
40945 * A physical address pointer pointing to a host buffer that the
40946 * command's response data will be written. This can be either a host
40947 * physical address (HPA) or a guest physical address (GPA) and must
40948 * point to a physically contiguous block of memory.
40950 uint64_t resp_addr;
40952 * 64-bit Host Destination Address.
40953 * This is the host address where the directory will be written.
40955 uint64_t host_dest_addr;
40958 /* hwrm_nvm_get_dir_entries_output (size:128b/16B) */
40959 struct hwrm_nvm_get_dir_entries_output {
40960 /* The specific error status for the command. */
40961 uint16_t error_code;
40962 /* The HWRM command request type. */
40964 /* The sequence ID from the original command. */
40966 /* The length of the response data in number of bytes. */
40968 uint8_t unused_0[7];
40970 * This field is used in Output records to indicate that the output
40971 * is completely written to RAM. This field should be read as '1'
40972 * to indicate that the output has been completely written.
40973 * When writing a command completion or response to an internal processor,
40974 * the order of writes has to be such that this field is written last.
40979 /*************************
40980 * hwrm_nvm_get_dir_info *
40981 *************************/
40984 /* hwrm_nvm_get_dir_info_input (size:128b/16B) */
40985 struct hwrm_nvm_get_dir_info_input {
40986 /* The HWRM command request type. */
40989 * The completion ring to send the completion event on. This should
40990 * be the NQ ID returned from the `nq_alloc` HWRM command.
40992 uint16_t cmpl_ring;
40994 * The sequence ID is used by the driver for tracking multiple
40995 * commands. This ID is treated as opaque data by the firmware and
40996 * the value is returned in the `hwrm_resp_hdr` upon completion.
41000 * The target ID of the command:
41001 * * 0x0-0xFFF8 - The function ID
41002 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
41003 * * 0xFFFD - Reserved for user-space HWRM interface
41006 uint16_t target_id;
41008 * A physical address pointer pointing to a host buffer that the
41009 * command's response data will be written. This can be either a host
41010 * physical address (HPA) or a guest physical address (GPA) and must
41011 * point to a physically contiguous block of memory.
41013 uint64_t resp_addr;
41016 /* hwrm_nvm_get_dir_info_output (size:192b/24B) */
41017 struct hwrm_nvm_get_dir_info_output {
41018 /* The specific error status for the command. */
41019 uint16_t error_code;
41020 /* The HWRM command request type. */
41022 /* The sequence ID from the original command. */
41024 /* The length of the response data in number of bytes. */
41026 /* Number of directory entries in the directory. */
41028 /* Size of each directory entry, in bytes. */
41029 uint32_t entry_length;
41030 uint8_t unused_0[7];
41032 * This field is used in Output records to indicate that the output
41033 * is completely written to RAM. This field should be read as '1'
41034 * to indicate that the output has been completely written.
41035 * When writing a command completion or response to an internal processor,
41036 * the order of writes has to be such that this field is written last.
41041 /******************
41043 ******************/
41046 /* hwrm_nvm_write_input (size:384b/48B) */
41047 struct hwrm_nvm_write_input {
41048 /* The HWRM command request type. */
41051 * The completion ring to send the completion event on. This should
41052 * be the NQ ID returned from the `nq_alloc` HWRM command.
41054 uint16_t cmpl_ring;
41056 * The sequence ID is used by the driver for tracking multiple
41057 * commands. This ID is treated as opaque data by the firmware and
41058 * the value is returned in the `hwrm_resp_hdr` upon completion.
41062 * The target ID of the command:
41063 * * 0x0-0xFFF8 - The function ID
41064 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
41065 * * 0xFFFD - Reserved for user-space HWRM interface
41068 uint16_t target_id;
41070 * A physical address pointer pointing to a host buffer that the
41071 * command's response data will be written. This can be either a host
41072 * physical address (HPA) or a guest physical address (GPA) and must
41073 * point to a physically contiguous block of memory.
41075 uint64_t resp_addr;
41077 * 64-bit Host Source Address.
41078 * This is where the source data is.
41080 uint64_t host_src_addr;
41081 /* The Directory Entry Type (valid values are defined in the bnxnvm_directory_type enum defined in the file bnxnvm_defs.h). */
41084 * Directory ordinal.
41085 * The 0-based instance of the combined Directory Entry Type and Extension.
41087 uint16_t dir_ordinal;
41088 /* The Directory Entry Extension flags (see BNX_DIR_EXT_* in the file bnxnvm_defs.h). */
41090 /* Directory Entry Attribute flags (see BNX_DIR_ATTR_* in the file bnxnvm_defs.h). */
41093 * Length of data to write, in bytes. May be less than or equal to the allocated size for the directory entry.
41094 * The data length stored in the directory entry will be updated to reflect this value once the write is complete.
41096 uint32_t dir_data_length;
41101 * When this bit is '1', the original active image
41102 * will not be removed. TBD: what purpose is this?
41104 #define HWRM_NVM_WRITE_INPUT_FLAGS_KEEP_ORIG_ACTIVE_IMG \
41107 * The requested length of the allocated NVM for the item, in bytes. This value may be greater than or equal to the specified data length (dir_data_length).
41108 * If this value is less than the specified data length, it will be ignored.
41109 * The response will contain the actual allocated item length, which may be greater than the requested item length.
41110 * The purpose for allocating more than the required number of bytes for an item's data is to pre-allocate extra storage (padding) to accommodate
41111 * the potential future growth of an item (e.g. upgraded firmware with a size increase, log growth, expanded configuration data).
41113 uint32_t dir_item_length;
41117 /* hwrm_nvm_write_output (size:128b/16B) */
41118 struct hwrm_nvm_write_output {
41119 /* The specific error status for the command. */
41120 uint16_t error_code;
41121 /* The HWRM command request type. */
41123 /* The sequence ID from the original command. */
41125 /* The length of the response data in number of bytes. */
41128 * Length of the allocated NVM for the item, in bytes. The value may be greater than or equal to the specified data length or the requested item length.
41129 * The actual item length used when creating a new directory entry will be a multiple of an NVM block size.
41131 uint32_t dir_item_length;
41132 /* The directory index of the created or modified item. */
41136 * This field is used in Output records to indicate that the output
41137 * is completely written to RAM. This field should be read as '1'
41138 * to indicate that the output has been completely written.
41139 * When writing a command completion or response to an internal processor,
41140 * the order of writes has to be such that this field is written last.
41145 /* hwrm_nvm_write_cmd_err (size:64b/8B) */
41146 struct hwrm_nvm_write_cmd_err {
41148 * command specific error codes that goes to
41149 * the cmd_err field in Common HWRM Error Response.
41152 /* Unknown error */
41153 #define HWRM_NVM_WRITE_CMD_ERR_CODE_UNKNOWN UINT32_C(0x0)
41154 /* Unable to complete operation due to fragmentation */
41155 #define HWRM_NVM_WRITE_CMD_ERR_CODE_FRAG_ERR UINT32_C(0x1)
41156 /* nvm is completely full. */
41157 #define HWRM_NVM_WRITE_CMD_ERR_CODE_NO_SPACE UINT32_C(0x2)
41158 #define HWRM_NVM_WRITE_CMD_ERR_CODE_LAST \
41159 HWRM_NVM_WRITE_CMD_ERR_CODE_NO_SPACE
41160 uint8_t unused_0[7];
41163 /*******************
41164 * hwrm_nvm_modify *
41165 *******************/
41168 /* hwrm_nvm_modify_input (size:320b/40B) */
41169 struct hwrm_nvm_modify_input {
41170 /* The HWRM command request type. */
41173 * The completion ring to send the completion event on. This should
41174 * be the NQ ID returned from the `nq_alloc` HWRM command.
41176 uint16_t cmpl_ring;
41178 * The sequence ID is used by the driver for tracking multiple
41179 * commands. This ID is treated as opaque data by the firmware and
41180 * the value is returned in the `hwrm_resp_hdr` upon completion.
41184 * The target ID of the command:
41185 * * 0x0-0xFFF8 - The function ID
41186 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
41187 * * 0xFFFD - Reserved for user-space HWRM interface
41190 uint16_t target_id;
41192 * A physical address pointer pointing to a host buffer that the
41193 * command's response data will be written. This can be either a host
41194 * physical address (HPA) or a guest physical address (GPA) and must
41195 * point to a physically contiguous block of memory.
41197 uint64_t resp_addr;
41199 * 64-bit Host Source Address.
41200 * This is where the modified data is.
41202 uint64_t host_src_addr;
41203 /* 16-bit directory entry index. */
41207 * This flag indicates the sender wants to modify a continuous NVRAM
41208 * area using a batch of this HWRM requests. The offset of a request
41209 * must be continuous to the end of previous request's. Firmware does
41210 * not update the directory entry until receiving the last request,
41211 * which is indicated by the batch_last flag.
41212 * This flag is set usually when a sender does not have a block of
41213 * memory that is big enough to hold the entire NVRAM data for send
41216 #define HWRM_NVM_MODIFY_INPUT_FLAGS_BATCH_MODE UINT32_C(0x1)
41218 * This flag can be used only when the batch_mode flag is set.
41219 * It indicates this request is the last of batch requests.
41221 #define HWRM_NVM_MODIFY_INPUT_FLAGS_BATCH_LAST UINT32_C(0x2)
41222 /* 32-bit NVRAM byte-offset to modify content from. */
41225 * Length of data to be modified, in bytes. The length shall
41229 uint8_t unused_1[4];
41232 /* hwrm_nvm_modify_output (size:128b/16B) */
41233 struct hwrm_nvm_modify_output {
41234 /* The specific error status for the command. */
41235 uint16_t error_code;
41236 /* The HWRM command request type. */
41238 /* The sequence ID from the original command. */
41240 /* The length of the response data in number of bytes. */
41242 uint8_t unused_0[7];
41244 * This field is used in Output records to indicate that the output
41245 * is completely written to RAM. This field should be read as '1'
41246 * to indicate that the output has been completely written.
41247 * When writing a command completion or response to an internal processor,
41248 * the order of writes has to be such that this field is written last.
41253 /***************************
41254 * hwrm_nvm_find_dir_entry *
41255 ***************************/
41258 /* hwrm_nvm_find_dir_entry_input (size:256b/32B) */
41259 struct hwrm_nvm_find_dir_entry_input {
41260 /* The HWRM command request type. */
41263 * The completion ring to send the completion event on. This should
41264 * be the NQ ID returned from the `nq_alloc` HWRM command.
41266 uint16_t cmpl_ring;
41268 * The sequence ID is used by the driver for tracking multiple
41269 * commands. This ID is treated as opaque data by the firmware and
41270 * the value is returned in the `hwrm_resp_hdr` upon completion.
41274 * The target ID of the command:
41275 * * 0x0-0xFFF8 - The function ID
41276 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
41277 * * 0xFFFD - Reserved for user-space HWRM interface
41280 uint16_t target_id;
41282 * A physical address pointer pointing to a host buffer that the
41283 * command's response data will be written. This can be either a host
41284 * physical address (HPA) or a guest physical address (GPA) and must
41285 * point to a physically contiguous block of memory.
41287 uint64_t resp_addr;
41290 * This bit must be '1' for the dir_idx_valid field to be
41293 #define HWRM_NVM_FIND_DIR_ENTRY_INPUT_ENABLES_DIR_IDX_VALID \
41295 /* Directory Entry Index */
41297 /* Directory Entry (Image) Type */
41300 * Directory ordinal.
41301 * The instance of this Directory Type
41303 uint16_t dir_ordinal;
41304 /* The Directory Entry Extension flags. */
41306 /* This value indicates the search option using dir_ordinal. */
41307 uint8_t opt_ordinal;
41308 /* This value indicates the search option using dir_ordinal. */
41309 #define HWRM_NVM_FIND_DIR_ENTRY_INPUT_OPT_ORDINAL_MASK UINT32_C(0x3)
41310 #define HWRM_NVM_FIND_DIR_ENTRY_INPUT_OPT_ORDINAL_SFT 0
41311 /* Equal to specified ordinal value. */
41312 #define HWRM_NVM_FIND_DIR_ENTRY_INPUT_OPT_ORDINAL_EQ UINT32_C(0x0)
41313 /* Greater than or equal to specified ordinal value */
41314 #define HWRM_NVM_FIND_DIR_ENTRY_INPUT_OPT_ORDINAL_GE UINT32_C(0x1)
41315 /* Greater than specified ordinal value */
41316 #define HWRM_NVM_FIND_DIR_ENTRY_INPUT_OPT_ORDINAL_GT UINT32_C(0x2)
41317 #define HWRM_NVM_FIND_DIR_ENTRY_INPUT_OPT_ORDINAL_LAST \
41318 HWRM_NVM_FIND_DIR_ENTRY_INPUT_OPT_ORDINAL_GT
41319 uint8_t unused_0[3];
41322 /* hwrm_nvm_find_dir_entry_output (size:256b/32B) */
41323 struct hwrm_nvm_find_dir_entry_output {
41324 /* The specific error status for the command. */
41325 uint16_t error_code;
41326 /* The HWRM command request type. */
41328 /* The sequence ID from the original command. */
41330 /* The length of the response data in number of bytes. */
41332 /* Allocated NVRAM for this directory entry, in bytes. */
41333 uint32_t dir_item_length;
41334 /* Size of the stored data for this directory entry, in bytes. */
41335 uint32_t dir_data_length;
41337 * Firmware version.
41338 * Only valid if the directory entry is for embedded firmware stored in APE_BIN Format.
41341 /* Directory ordinal. */
41342 uint16_t dir_ordinal;
41343 /* Directory Entry Index */
41345 uint8_t unused_0[7];
41347 * This field is used in Output records to indicate that the output
41348 * is completely written to RAM. This field should be read as '1'
41349 * to indicate that the output has been completely written.
41350 * When writing a command completion or response to an internal processor,
41351 * the order of writes has to be such that this field is written last.
41356 /****************************
41357 * hwrm_nvm_erase_dir_entry *
41358 ****************************/
41361 /* hwrm_nvm_erase_dir_entry_input (size:192b/24B) */
41362 struct hwrm_nvm_erase_dir_entry_input {
41363 /* The HWRM command request type. */
41366 * The completion ring to send the completion event on. This should
41367 * be the NQ ID returned from the `nq_alloc` HWRM command.
41369 uint16_t cmpl_ring;
41371 * The sequence ID is used by the driver for tracking multiple
41372 * commands. This ID is treated as opaque data by the firmware and
41373 * the value is returned in the `hwrm_resp_hdr` upon completion.
41377 * The target ID of the command:
41378 * * 0x0-0xFFF8 - The function ID
41379 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
41380 * * 0xFFFD - Reserved for user-space HWRM interface
41383 uint16_t target_id;
41385 * A physical address pointer pointing to a host buffer that the
41386 * command's response data will be written. This can be either a host
41387 * physical address (HPA) or a guest physical address (GPA) and must
41388 * point to a physically contiguous block of memory.
41390 uint64_t resp_addr;
41391 /* Directory Entry Index */
41393 uint8_t unused_0[6];
41396 /* hwrm_nvm_erase_dir_entry_output (size:128b/16B) */
41397 struct hwrm_nvm_erase_dir_entry_output {
41398 /* The specific error status for the command. */
41399 uint16_t error_code;
41400 /* The HWRM command request type. */
41402 /* The sequence ID from the original command. */
41404 /* The length of the response data in number of bytes. */
41406 uint8_t unused_0[7];
41408 * This field is used in Output records to indicate that the output
41409 * is completely written to RAM. This field should be read as '1'
41410 * to indicate that the output has been completely written.
41411 * When writing a command completion or response to an internal processor,
41412 * the order of writes has to be such that this field is written last.
41417 /*************************
41418 * hwrm_nvm_get_dev_info *
41419 *************************/
41422 /* hwrm_nvm_get_dev_info_input (size:128b/16B) */
41423 struct hwrm_nvm_get_dev_info_input {
41424 /* The HWRM command request type. */
41427 * The completion ring to send the completion event on. This should
41428 * be the NQ ID returned from the `nq_alloc` HWRM command.
41430 uint16_t cmpl_ring;
41432 * The sequence ID is used by the driver for tracking multiple
41433 * commands. This ID is treated as opaque data by the firmware and
41434 * the value is returned in the `hwrm_resp_hdr` upon completion.
41438 * The target ID of the command:
41439 * * 0x0-0xFFF8 - The function ID
41440 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
41441 * * 0xFFFD - Reserved for user-space HWRM interface
41444 uint16_t target_id;
41446 * A physical address pointer pointing to a host buffer that the
41447 * command's response data will be written. This can be either a host
41448 * physical address (HPA) or a guest physical address (GPA) and must
41449 * point to a physically contiguous block of memory.
41451 uint64_t resp_addr;
41454 /* hwrm_nvm_get_dev_info_output (size:256b/32B) */
41455 struct hwrm_nvm_get_dev_info_output {
41456 /* The specific error status for the command. */
41457 uint16_t error_code;
41458 /* The HWRM command request type. */
41460 /* The sequence ID from the original command. */
41462 /* The length of the response data in number of bytes. */
41464 /* Manufacturer ID. */
41465 uint16_t manufacturer_id;
41467 uint16_t device_id;
41468 /* Sector size of the NVRAM device. */
41469 uint32_t sector_size;
41470 /* Total size, in bytes of the NVRAM device. */
41471 uint32_t nvram_size;
41472 uint32_t reserved_size;
41473 /* Available size that can be used, in bytes. Available size is the NVRAM size take away the used size and reserved size. */
41474 uint32_t available_size;
41475 /* This field represents the major version of NVM cfg */
41476 uint8_t nvm_cfg_ver_maj;
41477 /* This field represents the minor version of NVM cfg */
41478 uint8_t nvm_cfg_ver_min;
41479 /* This field represents the update version of NVM cfg */
41480 uint8_t nvm_cfg_ver_upd;
41482 * This field is used in Output records to indicate that the output
41483 * is completely written to RAM. This field should be read as '1'
41484 * to indicate that the output has been completely written.
41485 * When writing a command completion or response to an internal processor,
41486 * the order of writes has to be such that this field is written last.
41491 /**************************
41492 * hwrm_nvm_mod_dir_entry *
41493 **************************/
41496 /* hwrm_nvm_mod_dir_entry_input (size:256b/32B) */
41497 struct hwrm_nvm_mod_dir_entry_input {
41498 /* The HWRM command request type. */
41501 * The completion ring to send the completion event on. This should
41502 * be the NQ ID returned from the `nq_alloc` HWRM command.
41504 uint16_t cmpl_ring;
41506 * The sequence ID is used by the driver for tracking multiple
41507 * commands. This ID is treated as opaque data by the firmware and
41508 * the value is returned in the `hwrm_resp_hdr` upon completion.
41512 * The target ID of the command:
41513 * * 0x0-0xFFF8 - The function ID
41514 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
41515 * * 0xFFFD - Reserved for user-space HWRM interface
41518 uint16_t target_id;
41520 * A physical address pointer pointing to a host buffer that the
41521 * command's response data will be written. This can be either a host
41522 * physical address (HPA) or a guest physical address (GPA) and must
41523 * point to a physically contiguous block of memory.
41525 uint64_t resp_addr;
41528 * This bit must be '1' for the checksum field to be
41531 #define HWRM_NVM_MOD_DIR_ENTRY_INPUT_ENABLES_CHECKSUM UINT32_C(0x1)
41532 /* Directory Entry Index */
41535 * Directory ordinal.
41536 * The (0-based) instance of this Directory Type.
41538 uint16_t dir_ordinal;
41539 /* The Directory Entry Extension flags (see BNX_DIR_EXT_* for extension flag definitions). */
41541 /* Directory Entry Attribute flags (see BNX_DIR_ATTR_* for attribute flag definitions). */
41544 * If valid, then this field updates the checksum
41545 * value of the content in the directory entry.
41550 /* hwrm_nvm_mod_dir_entry_output (size:128b/16B) */
41551 struct hwrm_nvm_mod_dir_entry_output {
41552 /* The specific error status for the command. */
41553 uint16_t error_code;
41554 /* The HWRM command request type. */
41556 /* The sequence ID from the original command. */
41558 /* The length of the response data in number of bytes. */
41560 uint8_t unused_0[7];
41562 * This field is used in Output records to indicate that the output
41563 * is completely written to RAM. This field should be read as '1'
41564 * to indicate that the output has been completely written.
41565 * When writing a command completion or response to an internal processor,
41566 * the order of writes has to be such that this field is written last.
41571 /**************************
41572 * hwrm_nvm_verify_update *
41573 **************************/
41576 /* hwrm_nvm_verify_update_input (size:192b/24B) */
41577 struct hwrm_nvm_verify_update_input {
41578 /* The HWRM command request type. */
41581 * The completion ring to send the completion event on. This should
41582 * be the NQ ID returned from the `nq_alloc` HWRM command.
41584 uint16_t cmpl_ring;
41586 * The sequence ID is used by the driver for tracking multiple
41587 * commands. This ID is treated as opaque data by the firmware and
41588 * the value is returned in the `hwrm_resp_hdr` upon completion.
41592 * The target ID of the command:
41593 * * 0x0-0xFFF8 - The function ID
41594 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
41595 * * 0xFFFD - Reserved for user-space HWRM interface
41598 uint16_t target_id;
41600 * A physical address pointer pointing to a host buffer that the
41601 * command's response data will be written. This can be either a host
41602 * physical address (HPA) or a guest physical address (GPA) and must
41603 * point to a physically contiguous block of memory.
41605 uint64_t resp_addr;
41606 /* Directory Entry Type, to be verified. */
41609 * Directory ordinal.
41610 * The instance of the Directory Type to be verified.
41612 uint16_t dir_ordinal;
41614 * The Directory Entry Extension flags.
41615 * The "UPDATE" extension flag must be set in this value.
41616 * A corresponding directory entry with the same type and ordinal values but *without*
41617 * the "UPDATE" extension flag must also exist. The other flags of the extension must
41618 * be identical between the active and update entries.
41621 uint8_t unused_0[2];
41624 /* hwrm_nvm_verify_update_output (size:128b/16B) */
41625 struct hwrm_nvm_verify_update_output {
41626 /* The specific error status for the command. */
41627 uint16_t error_code;
41628 /* The HWRM command request type. */
41630 /* The sequence ID from the original command. */
41632 /* The length of the response data in number of bytes. */
41634 uint8_t unused_0[7];
41636 * This field is used in Output records to indicate that the output
41637 * is completely written to RAM. This field should be read as '1'
41638 * to indicate that the output has been completely written.
41639 * When writing a command completion or response to an internal processor,
41640 * the order of writes has to be such that this field is written last.
41645 /***************************
41646 * hwrm_nvm_install_update *
41647 ***************************/
41650 /* hwrm_nvm_install_update_input (size:192b/24B) */
41651 struct hwrm_nvm_install_update_input {
41652 /* The HWRM command request type. */
41655 * The completion ring to send the completion event on. This should
41656 * be the NQ ID returned from the `nq_alloc` HWRM command.
41658 uint16_t cmpl_ring;
41660 * The sequence ID is used by the driver for tracking multiple
41661 * commands. This ID is treated as opaque data by the firmware and
41662 * the value is returned in the `hwrm_resp_hdr` upon completion.
41666 * The target ID of the command:
41667 * * 0x0-0xFFF8 - The function ID
41668 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
41669 * * 0xFFFD - Reserved for user-space HWRM interface
41672 uint16_t target_id;
41674 * A physical address pointer pointing to a host buffer that the
41675 * command's response data will be written. This can be either a host
41676 * physical address (HPA) or a guest physical address (GPA) and must
41677 * point to a physically contiguous block of memory.
41679 uint64_t resp_addr;
41681 * Installation type. If the value 3 through 0xffff is used,
41682 * only packaged items with that type value will be installed and
41683 * conditional installation directives for those packaged items
41684 * will be over-ridden (i.e. 'create' or 'replace' will be treated
41687 uint32_t install_type;
41689 * Perform a normal package installation. Conditional installation
41690 * directives (e.g. 'create' and 'replace') of packaged items
41691 * will be followed.
41693 #define HWRM_NVM_INSTALL_UPDATE_INPUT_INSTALL_TYPE_NORMAL UINT32_C(0x0)
41695 * Install all packaged items regardless of installation directive
41696 * (i.e. treat all packaged items as though they have an installation
41697 * directive of 'install').
41699 #define HWRM_NVM_INSTALL_UPDATE_INPUT_INSTALL_TYPE_ALL \
41700 UINT32_C(0xffffffff)
41701 #define HWRM_NVM_INSTALL_UPDATE_INPUT_INSTALL_TYPE_LAST \
41702 HWRM_NVM_INSTALL_UPDATE_INPUT_INSTALL_TYPE_ALL
41704 /* If set to 1, then securely erase all unused locations in persistent storage. */
41705 #define HWRM_NVM_INSTALL_UPDATE_INPUT_FLAGS_ERASE_UNUSED_SPACE \
41708 * If set to 1, then unspecified images, images not in the package file, will be safely deleted.
41709 * When combined with erase_unused_space then unspecified images will be securely erased.
41711 #define HWRM_NVM_INSTALL_UPDATE_INPUT_FLAGS_REMOVE_UNUSED_PKG \
41714 * If set to 1, FW will defragment the NVM if defragmentation is required for the update.
41715 * Allow additional time for this command to complete if this bit is set to 1.
41717 #define HWRM_NVM_INSTALL_UPDATE_INPUT_FLAGS_ALLOWED_TO_DEFRAG \
41720 * If set to 1, FW will verify the package in the "UPDATE" NVM item
41721 * without installing it. This flag is for FW internal use only.
41722 * Users should not set this flag. The request will otherwise fail.
41724 #define HWRM_NVM_INSTALL_UPDATE_INPUT_FLAGS_VERIFY_ONLY \
41726 uint8_t unused_0[2];
41729 /* hwrm_nvm_install_update_output (size:192b/24B) */
41730 struct hwrm_nvm_install_update_output {
41731 /* The specific error status for the command. */
41732 uint16_t error_code;
41733 /* The HWRM command request type. */
41735 /* The sequence ID from the original command. */
41737 /* The length of the response data in number of bytes. */
41740 * Bit-mask of successfully installed items.
41741 * Bit-0 corresponding to the first packaged item, Bit-1 for the second item, etc.
41742 * A value of 0 indicates that no items were successfully installed.
41744 uint64_t installed_items;
41745 /* result is 8 b */
41747 /* There was no problem with the package installation. */
41748 #define HWRM_NVM_INSTALL_UPDATE_OUTPUT_RESULT_SUCCESS UINT32_C(0x0)
41749 #define HWRM_NVM_INSTALL_UPDATE_OUTPUT_RESULT_LAST \
41750 HWRM_NVM_INSTALL_UPDATE_OUTPUT_RESULT_SUCCESS
41751 /* problem_item is 8 b */
41752 uint8_t problem_item;
41753 /* There was no problem with any packaged items. */
41754 #define HWRM_NVM_INSTALL_UPDATE_OUTPUT_PROBLEM_ITEM_NONE \
41756 /* There was a problem with the NVM package itself. */
41757 #define HWRM_NVM_INSTALL_UPDATE_OUTPUT_PROBLEM_ITEM_PACKAGE \
41759 #define HWRM_NVM_INSTALL_UPDATE_OUTPUT_PROBLEM_ITEM_LAST \
41760 HWRM_NVM_INSTALL_UPDATE_OUTPUT_PROBLEM_ITEM_PACKAGE
41761 /* reset_required is 8 b */
41762 uint8_t reset_required;
41764 * No reset is required for installed/updated firmware or
41765 * microcode to take effect.
41767 #define HWRM_NVM_INSTALL_UPDATE_OUTPUT_RESET_REQUIRED_NONE \
41770 * A PCIe reset (e.g. system reboot) is
41771 * required for newly installed/updated firmware or
41772 * microcode to take effect.
41774 #define HWRM_NVM_INSTALL_UPDATE_OUTPUT_RESET_REQUIRED_PCI \
41777 * A controller power reset (e.g. system power-cycle) is
41778 * required for newly installed/updated firmware or
41779 * microcode to take effect. Some newly installed/updated
41780 * firmware or microcode may still take effect upon the
41783 #define HWRM_NVM_INSTALL_UPDATE_OUTPUT_RESET_REQUIRED_POWER \
41785 #define HWRM_NVM_INSTALL_UPDATE_OUTPUT_RESET_REQUIRED_LAST \
41786 HWRM_NVM_INSTALL_UPDATE_OUTPUT_RESET_REQUIRED_POWER
41787 uint8_t unused_0[4];
41789 * This field is used in Output records to indicate that the output
41790 * is completely written to RAM. This field should be read as '1'
41791 * to indicate that the output has been completely written.
41792 * When writing a command completion or response to an internal processor,
41793 * the order of writes has to be such that this field is written last.
41798 /* hwrm_nvm_install_update_cmd_err (size:64b/8B) */
41799 struct hwrm_nvm_install_update_cmd_err {
41801 * command specific error codes that goes to
41802 * the cmd_err field in Common HWRM Error Response.
41805 /* Unknown error */
41806 #define HWRM_NVM_INSTALL_UPDATE_CMD_ERR_CODE_UNKNOWN UINT32_C(0x0)
41807 /* Unable to complete operation due to fragmentation */
41808 #define HWRM_NVM_INSTALL_UPDATE_CMD_ERR_CODE_FRAG_ERR UINT32_C(0x1)
41809 /* nvm is completely full. */
41810 #define HWRM_NVM_INSTALL_UPDATE_CMD_ERR_CODE_NO_SPACE UINT32_C(0x2)
41811 #define HWRM_NVM_INSTALL_UPDATE_CMD_ERR_CODE_LAST \
41812 HWRM_NVM_INSTALL_UPDATE_CMD_ERR_CODE_NO_SPACE
41813 uint8_t unused_0[7];
41816 /******************
41818 ******************/
41821 /* hwrm_nvm_flush_input (size:128b/16B) */
41822 struct hwrm_nvm_flush_input {
41823 /* The HWRM command request type. */
41826 * The completion ring to send the completion event on. This should
41827 * be the NQ ID returned from the `nq_alloc` HWRM command.
41829 uint16_t cmpl_ring;
41831 * The sequence ID is used by the driver for tracking multiple
41832 * commands. This ID is treated as opaque data by the firmware and
41833 * the value is returned in the `hwrm_resp_hdr` upon completion.
41837 * The target ID of the command:
41838 * * 0x0-0xFFF8 - The function ID
41839 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
41840 * * 0xFFFD - Reserved for user-space HWRM interface
41843 uint16_t target_id;
41845 * A physical address pointer pointing to a host buffer that the
41846 * command's response data will be written. This can be either a host
41847 * physical address (HPA) or a guest physical address (GPA) and must
41848 * point to a physically contiguous block of memory.
41850 uint64_t resp_addr;
41853 /* hwrm_nvm_flush_output (size:128b/16B) */
41854 struct hwrm_nvm_flush_output {
41855 /* The specific error status for the command. */
41856 uint16_t error_code;
41857 /* The HWRM command request type. */
41859 /* The sequence ID from the original command. */
41861 /* The length of the response data in number of bytes. */
41863 uint8_t unused_0[7];
41865 * This field is used in Output records to indicate that the output
41866 * is completely written to RAM. This field should be read as '1'
41867 * to indicate that the output has been completely written.
41868 * When writing a command completion or response to an internal processor,
41869 * the order of writes has to be such that this field is written last.
41874 /* hwrm_nvm_flush_cmd_err (size:64b/8B) */
41875 struct hwrm_nvm_flush_cmd_err {
41877 * command specific error codes that goes to
41878 * the cmd_err field in Common HWRM Error Response.
41881 /* Unknown error */
41882 #define HWRM_NVM_FLUSH_CMD_ERR_CODE_UNKNOWN UINT32_C(0x0)
41883 /* flush could not be performed */
41884 #define HWRM_NVM_FLUSH_CMD_ERR_CODE_FAIL UINT32_C(0x1)
41885 #define HWRM_NVM_FLUSH_CMD_ERR_CODE_LAST \
41886 HWRM_NVM_FLUSH_CMD_ERR_CODE_FAIL
41887 uint8_t unused_0[7];
41890 /*************************
41891 * hwrm_nvm_get_variable *
41892 *************************/
41895 /* hwrm_nvm_get_variable_input (size:320b/40B) */
41896 struct hwrm_nvm_get_variable_input {
41897 /* The HWRM command request type. */
41900 * The completion ring to send the completion event on. This should
41901 * be the NQ ID returned from the `nq_alloc` HWRM command.
41903 uint16_t cmpl_ring;
41905 * The sequence ID is used by the driver for tracking multiple
41906 * commands. This ID is treated as opaque data by the firmware and
41907 * the value is returned in the `hwrm_resp_hdr` upon completion.
41911 * The target ID of the command:
41912 * * 0x0-0xFFF8 - The function ID
41913 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
41914 * * 0xFFFD - Reserved for user-space HWRM interface
41917 uint16_t target_id;
41919 * A physical address pointer pointing to a host buffer that the
41920 * command's response data will be written. This can be either a host
41921 * physical address (HPA) or a guest physical address (GPA) and must
41922 * point to a physically contiguous block of memory.
41924 uint64_t resp_addr;
41926 * This is the host address where
41927 * nvm variable will be stored
41929 uint64_t dest_data_addr;
41930 /* size of data in bits */
41932 /* nvm cfg option number */
41933 uint16_t option_num;
41935 #define HWRM_NVM_GET_VARIABLE_INPUT_OPTION_NUM_RSVD_0 UINT32_C(0x0)
41937 #define HWRM_NVM_GET_VARIABLE_INPUT_OPTION_NUM_RSVD_FFFF \
41939 #define HWRM_NVM_GET_VARIABLE_INPUT_OPTION_NUM_LAST \
41940 HWRM_NVM_GET_VARIABLE_INPUT_OPTION_NUM_RSVD_FFFF
41942 * Number of dimensions for this nvm configuration variable.
41943 * This value indicates how many of the indexN values to use.
41944 * A value of 0 means that none of the indexN values are valid.
41945 * A value of 1 requires at index0 is valued, a value of 2
41946 * requires that index0 and index1 are valid, and so forth
41948 uint16_t dimensions;
41949 /* index for the 1st dimensions */
41951 /* index for the 2nd dimensions */
41953 /* index for the 3rd dimensions */
41955 /* index for the 4th dimensions */
41959 * When this bit is set to 1, the factory default value will be returned,
41960 * 0 returns the operational value.
41962 #define HWRM_NVM_GET_VARIABLE_INPUT_FLAGS_FACTORY_DFLT \
41967 /* hwrm_nvm_get_variable_output (size:128b/16B) */
41968 struct hwrm_nvm_get_variable_output {
41969 /* The specific error status for the command. */
41970 uint16_t error_code;
41971 /* The HWRM command request type. */
41973 /* The sequence ID from the original command. */
41975 /* The length of the response data in number of bytes. */
41977 /* size of data of the actual variable retrieved in bits */
41980 * option_num is the option number for the data retrieved. It is possible in the
41981 * future that the option number returned would be different than requested. This
41982 * condition could occur if an option is deprecated and a new option id is defined
41983 * with similar characteristics, but has a slightly different definition. This
41984 * also makes it convenient for the caller to identify the variable result with
41985 * the option id from the response.
41987 uint16_t option_num;
41989 #define HWRM_NVM_GET_VARIABLE_OUTPUT_OPTION_NUM_RSVD_0 UINT32_C(0x0)
41991 #define HWRM_NVM_GET_VARIABLE_OUTPUT_OPTION_NUM_RSVD_FFFF \
41993 #define HWRM_NVM_GET_VARIABLE_OUTPUT_OPTION_NUM_LAST \
41994 HWRM_NVM_GET_VARIABLE_OUTPUT_OPTION_NUM_RSVD_FFFF
41995 uint8_t unused_0[3];
41997 * This field is used in Output records to indicate that the output
41998 * is completely written to RAM. This field should be read as '1'
41999 * to indicate that the output has been completely written.
42000 * When writing a command completion or response to an internal processor,
42001 * the order of writes has to be such that this field is written last.
42006 /* hwrm_nvm_get_variable_cmd_err (size:64b/8B) */
42007 struct hwrm_nvm_get_variable_cmd_err {
42009 * command specific error codes that goes to
42010 * the cmd_err field in Common HWRM Error Response.
42013 /* Unknown error */
42014 #define HWRM_NVM_GET_VARIABLE_CMD_ERR_CODE_UNKNOWN UINT32_C(0x0)
42015 /* variable does not exist */
42016 #define HWRM_NVM_GET_VARIABLE_CMD_ERR_CODE_VAR_NOT_EXIST UINT32_C(0x1)
42017 /* configuration is corrupted and the variable cannot be saved */
42018 #define HWRM_NVM_GET_VARIABLE_CMD_ERR_CODE_CORRUPT_VAR UINT32_C(0x2)
42019 /* length specified is too small */
42020 #define HWRM_NVM_GET_VARIABLE_CMD_ERR_CODE_LEN_TOO_SHORT UINT32_C(0x3)
42021 #define HWRM_NVM_GET_VARIABLE_CMD_ERR_CODE_LAST \
42022 HWRM_NVM_GET_VARIABLE_CMD_ERR_CODE_LEN_TOO_SHORT
42023 uint8_t unused_0[7];
42026 /*************************
42027 * hwrm_nvm_set_variable *
42028 *************************/
42031 /* hwrm_nvm_set_variable_input (size:320b/40B) */
42032 struct hwrm_nvm_set_variable_input {
42033 /* The HWRM command request type. */
42036 * The completion ring to send the completion event on. This should
42037 * be the NQ ID returned from the `nq_alloc` HWRM command.
42039 uint16_t cmpl_ring;
42041 * The sequence ID is used by the driver for tracking multiple
42042 * commands. This ID is treated as opaque data by the firmware and
42043 * the value is returned in the `hwrm_resp_hdr` upon completion.
42047 * The target ID of the command:
42048 * * 0x0-0xFFF8 - The function ID
42049 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
42050 * * 0xFFFD - Reserved for user-space HWRM interface
42053 uint16_t target_id;
42055 * A physical address pointer pointing to a host buffer that the
42056 * command's response data will be written. This can be either a host
42057 * physical address (HPA) or a guest physical address (GPA) and must
42058 * point to a physically contiguous block of memory.
42060 uint64_t resp_addr;
42062 * This is the host address where
42063 * nvm variable will be copied from
42065 uint64_t src_data_addr;
42066 /* size of data in bits */
42068 /* nvm cfg option number */
42069 uint16_t option_num;
42071 #define HWRM_NVM_SET_VARIABLE_INPUT_OPTION_NUM_RSVD_0 UINT32_C(0x0)
42073 #define HWRM_NVM_SET_VARIABLE_INPUT_OPTION_NUM_RSVD_FFFF \
42075 #define HWRM_NVM_SET_VARIABLE_INPUT_OPTION_NUM_LAST \
42076 HWRM_NVM_SET_VARIABLE_INPUT_OPTION_NUM_RSVD_FFFF
42078 * Number of dimensions for this nvm configuration variable.
42079 * This value indicates how many of the indexN values to use.
42080 * A value of 0 means that none of the indexN values are valid.
42081 * A value of 1 requires at index0 is valued, a value of 2
42082 * requires that index0 and index1 are valid, and so forth
42084 uint16_t dimensions;
42085 /* index for the 1st dimensions */
42087 /* index for the 2nd dimensions */
42089 /* index for the 3rd dimensions */
42091 /* index for the 4th dimensions */
42094 /* When this bit is 1, flush internal cache after this write operation (see hwrm_nvm_flush command.) */
42095 #define HWRM_NVM_SET_VARIABLE_INPUT_FLAGS_FORCE_FLUSH \
42097 /* encryption method */
42098 #define HWRM_NVM_SET_VARIABLE_INPUT_FLAGS_ENCRYPT_MODE_MASK \
42100 #define HWRM_NVM_SET_VARIABLE_INPUT_FLAGS_ENCRYPT_MODE_SFT 1
42101 /* No encryption. */
42102 #define HWRM_NVM_SET_VARIABLE_INPUT_FLAGS_ENCRYPT_MODE_NONE \
42103 (UINT32_C(0x0) << 1)
42104 /* one-way encryption. */
42105 #define HWRM_NVM_SET_VARIABLE_INPUT_FLAGS_ENCRYPT_MODE_HMAC_SHA1 \
42106 (UINT32_C(0x1) << 1)
42107 /* symmetric AES256 encryption. */
42108 #define HWRM_NVM_SET_VARIABLE_INPUT_FLAGS_ENCRYPT_MODE_AES256 \
42109 (UINT32_C(0x2) << 1)
42110 /* SHA1 digest appended to plaintext contents, for authentication */
42111 #define HWRM_NVM_SET_VARIABLE_INPUT_FLAGS_ENCRYPT_MODE_HMAC_SHA1_AUTH \
42112 (UINT32_C(0x3) << 1)
42113 #define HWRM_NVM_SET_VARIABLE_INPUT_FLAGS_ENCRYPT_MODE_LAST \
42114 HWRM_NVM_SET_VARIABLE_INPUT_FLAGS_ENCRYPT_MODE_HMAC_SHA1_AUTH
42115 #define HWRM_NVM_SET_VARIABLE_INPUT_FLAGS_FLAGS_UNUSED_0_MASK \
42117 #define HWRM_NVM_SET_VARIABLE_INPUT_FLAGS_FLAGS_UNUSED_0_SFT 4
42118 /* When this bit is 1, update the factory default region */
42119 #define HWRM_NVM_SET_VARIABLE_INPUT_FLAGS_FACTORY_DEFAULT \
42124 /* hwrm_nvm_set_variable_output (size:128b/16B) */
42125 struct hwrm_nvm_set_variable_output {
42126 /* The specific error status for the command. */
42127 uint16_t error_code;
42128 /* The HWRM command request type. */
42130 /* The sequence ID from the original command. */
42132 /* The length of the response data in number of bytes. */
42134 uint8_t unused_0[7];
42136 * This field is used in Output records to indicate that the output
42137 * is completely written to RAM. This field should be read as '1'
42138 * to indicate that the output has been completely written.
42139 * When writing a command completion or response to an internal processor,
42140 * the order of writes has to be such that this field is written last.
42145 /* hwrm_nvm_set_variable_cmd_err (size:64b/8B) */
42146 struct hwrm_nvm_set_variable_cmd_err {
42148 * command specific error codes that goes to
42149 * the cmd_err field in Common HWRM Error Response.
42152 /* Unknown error */
42153 #define HWRM_NVM_SET_VARIABLE_CMD_ERR_CODE_UNKNOWN UINT32_C(0x0)
42154 /* variable does not exist */
42155 #define HWRM_NVM_SET_VARIABLE_CMD_ERR_CODE_VAR_NOT_EXIST UINT32_C(0x1)
42156 /* configuration is corrupted and the variable cannot be saved */
42157 #define HWRM_NVM_SET_VARIABLE_CMD_ERR_CODE_CORRUPT_VAR UINT32_C(0x2)
42158 #define HWRM_NVM_SET_VARIABLE_CMD_ERR_CODE_LAST \
42159 HWRM_NVM_SET_VARIABLE_CMD_ERR_CODE_CORRUPT_VAR
42160 uint8_t unused_0[7];
42163 /****************************
42164 * hwrm_nvm_validate_option *
42165 ****************************/
42168 /* hwrm_nvm_validate_option_input (size:320b/40B) */
42169 struct hwrm_nvm_validate_option_input {
42170 /* The HWRM command request type. */
42173 * The completion ring to send the completion event on. This should
42174 * be the NQ ID returned from the `nq_alloc` HWRM command.
42176 uint16_t cmpl_ring;
42178 * The sequence ID is used by the driver for tracking multiple
42179 * commands. This ID is treated as opaque data by the firmware and
42180 * the value is returned in the `hwrm_resp_hdr` upon completion.
42184 * The target ID of the command:
42185 * * 0x0-0xFFF8 - The function ID
42186 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
42187 * * 0xFFFD - Reserved for user-space HWRM interface
42190 uint16_t target_id;
42192 * A physical address pointer pointing to a host buffer that the
42193 * command's response data will be written. This can be either a host
42194 * physical address (HPA) or a guest physical address (GPA) and must
42195 * point to a physically contiguous block of memory.
42197 uint64_t resp_addr;
42199 * This is the host address where
42200 * nvm variable will be copied from
42202 uint64_t src_data_addr;
42203 /* size of data in bits */
42205 /* nvm cfg option number */
42206 uint16_t option_num;
42208 #define HWRM_NVM_VALIDATE_OPTION_INPUT_OPTION_NUM_RSVD_0 \
42211 #define HWRM_NVM_VALIDATE_OPTION_INPUT_OPTION_NUM_RSVD_FFFF \
42213 #define HWRM_NVM_VALIDATE_OPTION_INPUT_OPTION_NUM_LAST \
42214 HWRM_NVM_VALIDATE_OPTION_INPUT_OPTION_NUM_RSVD_FFFF
42216 * Number of dimensions for this nvm configuration variable.
42217 * This value indicates how many of the indexN values to use.
42218 * A value of 0 means that none of the indexN values are valid.
42219 * A value of 1 requires at index0 is valued, a value of 2
42220 * requires that index0 and index1 are valid, and so forth
42222 uint16_t dimensions;
42223 /* index for the 1st dimensions */
42225 /* index for the 2nd dimensions */
42227 /* index for the 3rd dimensions */
42229 /* index for the 4th dimensions */
42231 uint8_t unused_0[2];
42234 /* hwrm_nvm_validate_option_output (size:128b/16B) */
42235 struct hwrm_nvm_validate_option_output {
42236 /* The specific error status for the command. */
42237 uint16_t error_code;
42238 /* The HWRM command request type. */
42240 /* The sequence ID from the original command. */
42242 /* The length of the response data in number of bytes. */
42245 /* indicates that the value provided for the option is not matching with the saved data. */
42246 #define HWRM_NVM_VALIDATE_OPTION_OUTPUT_RESULT_NOT_MATCH UINT32_C(0x0)
42247 /* indicates that the value provided for the option is matching the saved data. */
42248 #define HWRM_NVM_VALIDATE_OPTION_OUTPUT_RESULT_MATCH UINT32_C(0x1)
42249 #define HWRM_NVM_VALIDATE_OPTION_OUTPUT_RESULT_LAST \
42250 HWRM_NVM_VALIDATE_OPTION_OUTPUT_RESULT_MATCH
42251 uint8_t unused_0[6];
42253 * This field is used in Output records to indicate that the output
42254 * is completely written to RAM. This field should be read as '1'
42255 * to indicate that the output has been completely written.
42256 * When writing a command completion or response to an internal processor,
42257 * the order of writes has to be such that this field is written last.
42262 /* hwrm_nvm_validate_option_cmd_err (size:64b/8B) */
42263 struct hwrm_nvm_validate_option_cmd_err {
42265 * command specific error codes that goes to
42266 * the cmd_err field in Common HWRM Error Response.
42269 /* Unknown error */
42270 #define HWRM_NVM_VALIDATE_OPTION_CMD_ERR_CODE_UNKNOWN UINT32_C(0x0)
42271 #define HWRM_NVM_VALIDATE_OPTION_CMD_ERR_CODE_LAST \
42272 HWRM_NVM_VALIDATE_OPTION_CMD_ERR_CODE_UNKNOWN
42273 uint8_t unused_0[7];
42281 /* hwrm_oem_cmd_input (size:1024b/128B) */
42282 struct hwrm_oem_cmd_input {
42283 /* The HWRM command request type. */
42286 * The completion ring to send the completion event on. This should
42287 * be the NQ ID returned from the `nq_alloc` HWRM command.
42289 uint16_t cmpl_ring;
42291 * The sequence ID is used by the driver for tracking multiple
42292 * commands. This ID is treated as opaque data by the firmware and
42293 * the value is returned in the `hwrm_resp_hdr` upon completion.
42297 * The target ID of the command:
42298 * * 0x0-0xFFF8 - The function ID
42299 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
42300 * * 0xFFFD - Reserved for user-space HWRM interface
42303 uint16_t target_id;
42305 * A physical address pointer pointing to a host buffer that the
42306 * command's response data will be written. This can be either a host
42307 * physical address (HPA) or a guest physical address (GPA) and must
42308 * point to a physically contiguous block of memory.
42310 uint64_t resp_addr;
42313 /* This field contains the vendor specific command data. */
42314 uint32_t oem_data[26];
42317 /* hwrm_oem_cmd_output (size:768b/96B) */
42318 struct hwrm_oem_cmd_output {
42319 /* The specific error status for the command. */
42320 uint16_t error_code;
42321 /* The HWRM command request type. */
42323 /* The sequence ID from the original command. */
42325 /* The length of the response data in number of bytes. */
42329 /* This field contains the vendor specific response data. */
42330 uint32_t oem_data[18];
42331 uint8_t unused_1[7];
42333 * This field is used in Output records to indicate that the output
42334 * is completely written to RAM. This field should be read as '1'
42335 * to indicate that the output has been completely written.
42336 * When writing a command completion or response to an internal processor,
42337 * the order of writes has to be such that this field is written last.
42344 ******************/
42347 /* hwrm_fw_reset_input (size:192b/24B) */
42348 struct hwrm_fw_reset_input {
42349 /* The HWRM command request type. */
42352 * The completion ring to send the completion event on. This should
42353 * be the NQ ID returned from the `nq_alloc` HWRM command.
42355 uint16_t cmpl_ring;
42357 * The sequence ID is used by the driver for tracking multiple
42358 * commands. This ID is treated as opaque data by the firmware and
42359 * the value is returned in the `hwrm_resp_hdr` upon completion.
42363 * The target ID of the command:
42364 * * 0x0-0xFFF8 - The function ID
42365 * * 0xFFF8-0xFFFE - Reserved for internal processors
42368 uint16_t target_id;
42370 * A physical address pointer pointing to a host buffer that the
42371 * command's response data will be written. This can be either a host
42372 * physical address (HPA) or a guest physical address (GPA) and must
42373 * point to a physically contiguous block of memory.
42375 uint64_t resp_addr;
42376 /* Type of embedded processor. */
42377 uint8_t embedded_proc_type;
42378 /* Boot Processor */
42379 #define HWRM_FW_RESET_INPUT_EMBEDDED_PROC_TYPE_BOOT \
42381 /* Management Processor */
42382 #define HWRM_FW_RESET_INPUT_EMBEDDED_PROC_TYPE_MGMT \
42384 /* Network control processor */
42385 #define HWRM_FW_RESET_INPUT_EMBEDDED_PROC_TYPE_NETCTRL \
42387 /* RoCE control processor */
42388 #define HWRM_FW_RESET_INPUT_EMBEDDED_PROC_TYPE_ROCE \
42391 * Host (in multi-host environment): This is only valid if requester is IPC.
42392 * Reinit host hardware resources and PCIe.
42394 #define HWRM_FW_RESET_INPUT_EMBEDDED_PROC_TYPE_HOST \
42396 /* AP processor complex (in multi-host environment). Use host_idx to control which core is reset */
42397 #define HWRM_FW_RESET_INPUT_EMBEDDED_PROC_TYPE_AP \
42399 /* Reset all blocks of the chip (including all processors) */
42400 #define HWRM_FW_RESET_INPUT_EMBEDDED_PROC_TYPE_CHIP \
42403 * Host (in multi-host environment): This is only valid if requester is IPC.
42404 * Reinit host hardware resources.
42406 #define HWRM_FW_RESET_INPUT_EMBEDDED_PROC_TYPE_HOST_RESOURCE_REINIT \
42408 #define HWRM_FW_RESET_INPUT_EMBEDDED_PROC_TYPE_LAST \
42409 HWRM_FW_RESET_INPUT_EMBEDDED_PROC_TYPE_HOST_RESOURCE_REINIT
42410 /* Type of self reset. */
42411 uint8_t selfrst_status;
42412 /* No Self Reset */
42413 #define HWRM_FW_RESET_INPUT_SELFRST_STATUS_SELFRSTNONE \
42415 /* Self Reset as soon as possible to do so safely */
42416 #define HWRM_FW_RESET_INPUT_SELFRST_STATUS_SELFRSTASAP \
42418 /* Self Reset on PCIe Reset */
42419 #define HWRM_FW_RESET_INPUT_SELFRST_STATUS_SELFRSTPCIERST \
42421 /* Self Reset immediately after notification to all clients. */
42422 #define HWRM_FW_RESET_INPUT_SELFRST_STATUS_SELFRSTIMMEDIATE \
42424 #define HWRM_FW_RESET_INPUT_SELFRST_STATUS_LAST \
42425 HWRM_FW_RESET_INPUT_SELFRST_STATUS_SELFRSTIMMEDIATE
42427 * Indicate which host is being reset. 0 means first host.
42428 * Only valid when embedded_proc_type is host in multihost
42434 * When this bit is '1', then the core firmware initiates
42435 * the reset only after graceful shut down of all registered instances.
42436 * If not, the device will continue with the existing firmware.
42438 #define HWRM_FW_RESET_INPUT_FLAGS_RESET_GRACEFUL UINT32_C(0x1)
42439 uint8_t unused_0[4];
42442 /* hwrm_fw_reset_output (size:128b/16B) */
42443 struct hwrm_fw_reset_output {
42444 /* The specific error status for the command. */
42445 uint16_t error_code;
42446 /* The HWRM command request type. */
42448 /* The sequence ID from the original command. */
42450 /* The length of the response data in number of bytes. */
42452 /* Type of self reset. */
42453 uint8_t selfrst_status;
42454 /* No Self Reset */
42455 #define HWRM_FW_RESET_OUTPUT_SELFRST_STATUS_SELFRSTNONE \
42457 /* Self Reset as soon as possible to do so safely */
42458 #define HWRM_FW_RESET_OUTPUT_SELFRST_STATUS_SELFRSTASAP \
42460 /* Self Reset on PCIe Reset */
42461 #define HWRM_FW_RESET_OUTPUT_SELFRST_STATUS_SELFRSTPCIERST \
42463 /* Self Reset immediately after notification to all clients. */
42464 #define HWRM_FW_RESET_OUTPUT_SELFRST_STATUS_SELFRSTIMMEDIATE \
42466 #define HWRM_FW_RESET_OUTPUT_SELFRST_STATUS_LAST \
42467 HWRM_FW_RESET_OUTPUT_SELFRST_STATUS_SELFRSTIMMEDIATE
42468 uint8_t unused_0[6];
42470 * This field is used in Output records to indicate that the output
42471 * is completely written to RAM. This field should be read as '1'
42472 * to indicate that the output has been completely written.
42473 * When writing a command completion or response to an internal processor,
42474 * the order of writes has to be such that this field is written last.
42479 /**********************
42480 * hwrm_port_ts_query *
42481 ***********************/
42484 /* hwrm_port_ts_query_input (size:192b/24B) */
42485 struct hwrm_port_ts_query_input {
42486 /* The HWRM command request type. */
42489 * The completion ring to send the completion event on. This should
42490 * be the NQ ID returned from the `nq_alloc` HWRM command.
42492 uint16_t cmpl_ring;
42494 * The sequence ID is used by the driver for tracking multiple
42495 * commands. This ID is treated as opaque data by the firmware and
42496 * the value is returned in the `hwrm_resp_hdr` upon completion.
42500 * The target ID of the command:
42501 * * 0x0-0xFFF8 - The function ID
42502 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
42503 * * 0xFFFD - Reserved for user-space HWRM interface
42506 uint16_t target_id;
42508 * A physical address pointer pointing to a host buffer that the
42509 * command's response data will be written. This can be either a host
42510 * physical address (HPA) or a guest physical address (GPA) and must
42511 * point to a physically contiguous block of memory.
42513 uint64_t resp_addr;
42516 * Enumeration denoting the RX, TX type of the resource.
42517 * This enumeration is used for resources that are similar for both
42518 * TX and RX paths of the chip.
42520 #define HWRM_PORT_TS_QUERY_INPUT_FLAGS_PATH 0x1UL
42522 #define HWRM_PORT_TS_QUERY_INPUT_FLAGS_PATH_TX 0x0UL
42524 #define HWRM_PORT_TS_QUERY_INPUT_FLAGS_PATH_RX 0x1UL
42525 #define HWRM_PORT_TS_QUERY_INPUT_FLAGS_PATH_LAST \
42526 HWRM_PORT_TS_QUERY_INPUT_FLAGS_PATH_RX
42528 * If set, the response includes the current value of the free
42531 #define HWRM_PORT_TS_QUERY_INPUT_FLAGS_CURRENT_TIME 0x2UL
42532 /* Port ID of port that is being queried. */
42534 uint8_t unused_0[2];
42537 /* hwrm_port_ts_query_output (size:192b/24B) */
42538 struct hwrm_port_ts_query_output {
42539 /* The specific error status for the command. */
42540 uint16_t error_code;
42541 /* The HWRM command request type. */
42543 /* The sequence ID from the original command. */
42545 /* The length of the response data in number of bytes. */
42548 * Timestamp value of PTP message captured, or current value of
42549 * free running timer.
42551 uint32_t ptp_msg_ts[2];
42552 /* Sequence ID of the PTP message captured. */
42553 uint16_t ptp_msg_seqid;
42554 uint8_t unused_0[5];
42556 * This field is used in Output records to indicate that the output
42557 * is completely written to RAM. This field should be read as '1'
42558 * to indicate that the output has been completely written.
42559 * When writing a command completion or response to an internal processor,
42560 * the order of writes has to be such that this field is written last.
42566 * This structure is fixed at the beginning of the ChiMP SRAM (GRC
42567 * offset: 0x31001F0). Host software is expected to read from this
42568 * location for a defined signature. If it exists, the software can
42569 * assume the presence of this structure and the validity of the
42570 * FW_STATUS location in the next field.
42572 /* hcomm_status (size:64b/8B) */
42573 struct hcomm_status {
42576 * This field defines the version of the structure. The latest
42577 * version value is 1.
42579 #define HCOMM_STATUS_VER_MASK UINT32_C(0xff)
42580 #define HCOMM_STATUS_VER_SFT 0
42581 #define HCOMM_STATUS_VER_LATEST UINT32_C(0x1)
42582 #define HCOMM_STATUS_VER_LAST HCOMM_STATUS_VER_LATEST
42584 * This field is to store the signature value to indicate the
42585 * presence of the structure.
42587 #define HCOMM_STATUS_SIGNATURE_MASK UINT32_C(0xffffff00)
42588 #define HCOMM_STATUS_SIGNATURE_SFT 8
42589 #define HCOMM_STATUS_SIGNATURE_VAL (UINT32_C(0x484353) << 8)
42590 #define HCOMM_STATUS_SIGNATURE_LAST HCOMM_STATUS_SIGNATURE_VAL
42591 uint32_t fw_status_loc;
42592 #define HCOMM_STATUS_TRUE_ADDR_SPACE_MASK UINT32_C(0x3)
42593 #define HCOMM_STATUS_TRUE_ADDR_SPACE_SFT 0
42594 /* PCIE configuration space */
42595 #define HCOMM_STATUS_FW_STATUS_LOC_ADDR_SPACE_PCIE_CFG UINT32_C(0x0)
42597 #define HCOMM_STATUS_FW_STATUS_LOC_ADDR_SPACE_GRC UINT32_C(0x1)
42599 #define HCOMM_STATUS_FW_STATUS_LOC_ADDR_SPACE_BAR0 UINT32_C(0x2)
42601 #define HCOMM_STATUS_FW_STATUS_LOC_ADDR_SPACE_BAR1 UINT32_C(0x3)
42602 #define HCOMM_STATUS_FW_STATUS_LOC_ADDR_SPACE_LAST \
42603 HCOMM_STATUS_FW_STATUS_LOC_ADDR_SPACE_BAR1
42605 * This offset where the fw_status register is located. The value
42606 * is generally 4-byte aligned.
42608 #define HCOMM_STATUS_TRUE_OFFSET_MASK UINT32_C(0xfffffffc)
42609 #define HCOMM_STATUS_TRUE_OFFSET_SFT 2
42611 /* This is the GRC offset where the hcomm_status struct resides. */
42612 #define HCOMM_STATUS_STRUCT_LOC 0x31001F0UL
42614 /**************************
42615 * hwrm_cfa_counter_qcaps *
42616 **************************/
42619 /* hwrm_cfa_counter_qcaps_input (size:128b/16B) */
42620 struct hwrm_cfa_counter_qcaps_input {
42621 /* The HWRM command request type. */
42624 * The completion ring to send the completion event on. This should
42625 * be the NQ ID returned from the `nq_alloc` HWRM command.
42627 uint16_t cmpl_ring;
42629 * The sequence ID is used by the driver for tracking multiple
42630 * commands. This ID is treated as opaque data by the firmware and
42631 * the value is returned in the `hwrm_resp_hdr` upon completion.
42635 * The target ID of the command:
42636 * * 0x0-0xFFF8 - The function ID
42637 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
42638 * * 0xFFFD - Reserved for user-space HWRM interface
42641 uint16_t target_id;
42643 * A physical address pointer pointing to a host buffer that the
42644 * command's response data will be written. This can be either a host
42645 * physical address (HPA) or a guest physical address (GPA) and must
42646 * point to a physically contiguous block of memory.
42648 uint64_t resp_addr;
42651 /* hwrm_cfa_counter_qcaps_output (size:576b/72B) */
42652 struct hwrm_cfa_counter_qcaps_output {
42653 /* The specific error status for the command. */
42654 uint16_t error_code;
42655 /* The HWRM command request type. */
42657 /* The sequence ID from the original command. */
42659 /* The length of the response data in number of bytes. */
42662 /* Enumeration denoting the supported CFA counter format. */
42663 #define HWRM_CFA_COUNTER_QCAPS_OUTPUT_FLAGS_COUNTER_FORMAT \
42665 /* CFA counter types are not supported. */
42666 #define HWRM_CFA_COUNTER_QCAPS_OUTPUT_FLAGS_COUNTER_FORMAT_NONE \
42668 /* 64-bit packet counters followed by 64-bit byte counters format. */
42669 #define HWRM_CFA_COUNTER_QCAPS_OUTPUT_FLAGS_COUNTER_FORMAT_64_BIT \
42671 #define HWRM_CFA_COUNTER_QCAPS_OUTPUT_FLAGS_COUNTER_FORMAT_LAST \
42672 HWRM_CFA_COUNTER_QCAPS_OUTPUT_FLAGS_COUNTER_FORMAT_64_BIT
42674 /* Minimum guaranteed number of flow counters supported for this function, in RX direction. */
42675 uint32_t min_rx_fc;
42676 /* Maximum non-guaranteed number of flow counters supported for this function, in RX direction. */
42677 uint32_t max_rx_fc;
42678 /* Minimum guaranteed number of flow counters supported for this function, in TX direction. */
42679 uint32_t min_tx_fc;
42680 /* Maximum non-guaranteed number of flow counters supported for this function, in TX direction. */
42681 uint32_t max_tx_fc;
42682 /* Minimum guaranteed number of extension flow counters supported for this function, in RX direction. */
42683 uint32_t min_rx_efc;
42684 /* Maximum non-guaranteed number of extension flow counters supported for this function, in RX direction. */
42685 uint32_t max_rx_efc;
42686 /* Minimum guaranteed number of extension flow counters supported for this function, in TX direction. */
42687 uint32_t min_tx_efc;
42688 /* Maximum non-guaranteed number of extension flow counters supported for this function, in TX direction. */
42689 uint32_t max_tx_efc;
42690 /* Minimum guaranteed number of meter drop counters supported for this function, in RX direction. */
42691 uint32_t min_rx_mdc;
42692 /* Maximum non-guaranteed number of meter drop counters supported for this function, in RX direction. */
42693 uint32_t max_rx_mdc;
42694 /* Minimum guaranteed number of meter drop counters supported for this function, in TX direction. */
42695 uint32_t min_tx_mdc;
42696 /* Maximum non-guaranteed number of meter drop counters supported for this function, in TX direction. */
42697 uint32_t max_tx_mdc;
42698 /* Maximum guaranteed number of flow counters which can be used during flow alloc. */
42699 uint32_t max_flow_alloc_fc;
42700 uint8_t unused_1[3];
42702 * This field is used in Output records to indicate that the output
42703 * is completely written to RAM. This field should be read as '1'
42704 * to indicate that the output has been completely written.
42705 * When writing a command completion or response to an internal processor,
42706 * the order of writes has to be such that this field is written last.
42711 /************************
42712 * hwrm_cfa_counter_cfg *
42713 ************************/
42716 /* hwrm_cfa_counter_cfg_input (size:256b/32B) */
42717 struct hwrm_cfa_counter_cfg_input {
42718 /* The HWRM command request type. */
42721 * The completion ring to send the completion event on. This should
42722 * be the NQ ID returned from the `nq_alloc` HWRM command.
42724 uint16_t cmpl_ring;
42726 * The sequence ID is used by the driver for tracking multiple
42727 * commands. This ID is treated as opaque data by the firmware and
42728 * the value is returned in the `hwrm_resp_hdr` upon completion.
42732 * The target ID of the command:
42733 * * 0x0-0xFFF8 - The function ID
42734 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
42735 * * 0xFFFD - Reserved for user-space HWRM interface
42738 uint16_t target_id;
42740 * A physical address pointer pointing to a host buffer that the
42741 * command's response data will be written. This can be either a host
42742 * physical address (HPA) or a guest physical address (GPA) and must
42743 * point to a physically contiguous block of memory.
42745 uint64_t resp_addr;
42747 /* Enumeration denoting the configuration mode. */
42748 #define HWRM_CFA_COUNTER_CFG_INPUT_FLAGS_CFG_MODE \
42750 /* Disable the configuration mode. */
42751 #define HWRM_CFA_COUNTER_CFG_INPUT_FLAGS_CFG_MODE_DISABLE \
42753 /* Enable the configuration mode. */
42754 #define HWRM_CFA_COUNTER_CFG_INPUT_FLAGS_CFG_MODE_ENABLE \
42756 #define HWRM_CFA_COUNTER_CFG_INPUT_FLAGS_CFG_MODE_LAST \
42757 HWRM_CFA_COUNTER_CFG_INPUT_FLAGS_CFG_MODE_ENABLE
42758 /* Enumeration denoting the RX, TX type of the resource. */
42759 #define HWRM_CFA_COUNTER_CFG_INPUT_FLAGS_PATH \
42762 #define HWRM_CFA_COUNTER_CFG_INPUT_FLAGS_PATH_TX \
42763 (UINT32_C(0x0) << 1)
42765 #define HWRM_CFA_COUNTER_CFG_INPUT_FLAGS_PATH_RX \
42766 (UINT32_C(0x1) << 1)
42767 #define HWRM_CFA_COUNTER_CFG_INPUT_FLAGS_PATH_LAST \
42768 HWRM_CFA_COUNTER_CFG_INPUT_FLAGS_PATH_RX
42769 /* Enumeration denoting the data transfer mode. */
42770 #define HWRM_CFA_COUNTER_CFG_INPUT_FLAGS_DATA_TRANSFER_MODE_MASK \
42772 #define HWRM_CFA_COUNTER_CFG_INPUT_FLAGS_DATA_TRANSFER_MODE_SFT 2
42774 #define HWRM_CFA_COUNTER_CFG_INPUT_FLAGS_DATA_TRANSFER_MODE_PUSH \
42775 (UINT32_C(0x0) << 2)
42777 #define HWRM_CFA_COUNTER_CFG_INPUT_FLAGS_DATA_TRANSFER_MODE_PULL \
42778 (UINT32_C(0x1) << 2)
42779 /* Pull on async update. */
42780 #define HWRM_CFA_COUNTER_CFG_INPUT_FLAGS_DATA_TRANSFER_MODE_PULL_ASYNC \
42781 (UINT32_C(0x2) << 2)
42782 #define HWRM_CFA_COUNTER_CFG_INPUT_FLAGS_DATA_TRANSFER_MODE_LAST \
42783 HWRM_CFA_COUNTER_CFG_INPUT_FLAGS_DATA_TRANSFER_MODE_PULL_ASYNC
42784 uint16_t counter_type;
42785 /* Flow counters. */
42786 #define HWRM_CFA_COUNTER_CFG_INPUT_COUNTER_TYPE_FC UINT32_C(0x0)
42787 /* Extended flow counters. */
42788 #define HWRM_CFA_COUNTER_CFG_INPUT_COUNTER_TYPE_EFC UINT32_C(0x1)
42789 /* Meter drop counters. */
42790 #define HWRM_CFA_COUNTER_CFG_INPUT_COUNTER_TYPE_MDC UINT32_C(0x2)
42791 #define HWRM_CFA_COUNTER_CFG_INPUT_COUNTER_TYPE_LAST \
42792 HWRM_CFA_COUNTER_CFG_INPUT_COUNTER_TYPE_MDC
42793 /* Ctx memory handle to be used for the counter. */
42795 /* Counter update cadence hint (only in Push mode). */
42796 uint16_t update_tmr_ms;
42797 /* Total number of entries. */
42798 uint32_t num_entries;
42802 /* hwrm_cfa_counter_cfg_output (size:128b/16B) */
42803 struct hwrm_cfa_counter_cfg_output {
42804 /* The specific error status for the command. */
42805 uint16_t error_code;
42806 /* The HWRM command request type. */
42808 /* The sequence ID from the original command. */
42810 /* The length of the response data in number of bytes. */
42812 uint8_t unused_0[7];
42814 * This field is used in Output records to indicate that the output
42815 * is completely written to RAM. This field should be read as '1'
42816 * to indicate that the output has been completely written.
42817 * When writing a command completion or response to an internal processor,
42818 * the order of writes has to be such that this field is written last.
42823 /***************************
42824 * hwrm_cfa_counter_qstats *
42825 ***************************/
42828 /* hwrm_cfa_counter_qstats_input (size:320b/40B) */
42829 struct hwrm_cfa_counter_qstats_input {
42830 /* The HWRM command request type. */
42833 * The completion ring to send the completion event on. This should
42834 * be the NQ ID returned from the `nq_alloc` HWRM command.
42836 uint16_t cmpl_ring;
42838 * The sequence ID is used by the driver for tracking multiple
42839 * commands. This ID is treated as opaque data by the firmware and
42840 * the value is returned in the `hwrm_resp_hdr` upon completion.
42844 * The target ID of the command:
42845 * * 0x0-0xFFF8 - The function ID
42846 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
42847 * * 0xFFFD - Reserved for user-space HWRM interface
42850 uint16_t target_id;
42852 * A physical address pointer pointing to a host buffer that the
42853 * command's response data will be written. This can be either a host
42854 * physical address (HPA) or a guest physical address (GPA) and must
42855 * point to a physically contiguous block of memory.
42857 uint64_t resp_addr;
42859 /* Enumeration denoting the RX, TX type of the resource. */
42860 #define HWRM_CFA_COUNTER_QSTATS_INPUT_FLAGS_PATH UINT32_C(0x1)
42862 #define HWRM_CFA_COUNTER_QSTATS_INPUT_FLAGS_PATH_TX UINT32_C(0x0)
42864 #define HWRM_CFA_COUNTER_QSTATS_INPUT_FLAGS_PATH_RX UINT32_C(0x1)
42865 #define HWRM_CFA_COUNTER_QSTATS_INPUT_FLAGS_PATH_LAST \
42866 HWRM_CFA_COUNTER_QSTATS_INPUT_FLAGS_PATH_RX
42867 uint16_t counter_type;
42868 uint16_t input_flow_ctx_id;
42869 uint16_t num_entries;
42870 uint16_t delta_time_ms;
42871 uint16_t meter_instance_id;
42872 uint16_t mdc_ctx_id;
42873 uint8_t unused_0[2];
42874 uint64_t expected_count;
42877 /* hwrm_cfa_counter_qstats_output (size:128b/16B) */
42878 struct hwrm_cfa_counter_qstats_output {
42879 /* The specific error status for the command. */
42880 uint16_t error_code;
42881 /* The HWRM command request type. */
42883 /* The sequence ID from the original command. */
42885 /* The length of the response data in number of bytes. */
42887 uint8_t unused_0[7];
42889 * This field is used in Output records to indicate that the output
42890 * is completely written to RAM. This field should be read as '1'
42891 * to indicate that the output has been completely written.
42892 * When writing a command completion or response to an internal processor,
42893 * the order of writes has to be such that this field is written last.
42898 #endif /* _HSI_STRUCT_DEF_DPDK_H_ */