1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright (c) 2014-2020 Broadcom Inc.
5 * DO NOT MODIFY!!! This file is automatically generated.
8 #ifndef _HSI_STRUCT_DEF_DPDK_H_
9 #define _HSI_STRUCT_DEF_DPDK_H_
11 /* This is the HWRM command header. */
12 /* hwrm_cmd_hdr (size:128b/16B) */
14 /* The HWRM command request type. */
17 * The completion ring to send the completion event on. This should
18 * be the NQ ID returned from the `nq_alloc` HWRM command.
22 * The sequence ID is used by the driver for tracking multiple
23 * commands. This ID is treated as opaque data by the firmware and
24 * the value is returned in the `hwrm_resp_hdr` upon completion.
28 * The target ID of the command:
29 * * 0x0-0xFFF8 - The function ID
30 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
31 * * 0xFFFD - Reserved for user-space HWRM interface
36 * A physical address pointer pointing to a host buffer that the
37 * command's response data will be written. This can be either a host
38 * physical address (HPA) or a guest physical address (GPA) and must
39 * point to a physically contiguous block of memory.
44 /* This is the HWRM response header. */
45 /* hwrm_resp_hdr (size:64b/8B) */
46 struct hwrm_resp_hdr {
47 /* The specific error status for the command. */
49 /* The HWRM command request type. */
51 /* The sequence ID from the original command. */
53 /* The length of the response data in number of bytes. */
58 * TLV encapsulated message. Use the TLV type field of the
59 * TLV to determine the type of message encapsulated.
61 #define CMD_DISCR_TLV_ENCAP UINT32_C(0x8000)
62 #define CMD_DISCR_LAST CMD_DISCR_TLV_ENCAP
65 /* HWRM request message */
66 #define TLV_TYPE_HWRM_REQUEST UINT32_C(0x1)
67 /* HWRM response message */
68 #define TLV_TYPE_HWRM_RESPONSE UINT32_C(0x2)
69 /* RoCE slow path command */
70 #define TLV_TYPE_ROCE_SP_COMMAND UINT32_C(0x3)
71 /* RoCE slow path command to query CC Gen1 support. */
72 #define TLV_TYPE_QUERY_ROCE_CC_GEN1 UINT32_C(0x4)
73 /* RoCE slow path command to modify CC Gen1 support. */
74 #define TLV_TYPE_MODIFY_ROCE_CC_GEN1 UINT32_C(0x5)
75 /* Engine CKV - The Alias key EC curve and ECC public key information. */
76 #define TLV_TYPE_ENGINE_CKV_ALIAS_ECC_PUBLIC_KEY UINT32_C(0x8001)
77 /* Engine CKV - Initialization vector. */
78 #define TLV_TYPE_ENGINE_CKV_IV UINT32_C(0x8003)
79 /* Engine CKV - Authentication tag. */
80 #define TLV_TYPE_ENGINE_CKV_AUTH_TAG UINT32_C(0x8004)
81 /* Engine CKV - The encrypted data. */
82 #define TLV_TYPE_ENGINE_CKV_CIPHERTEXT UINT32_C(0x8005)
83 /* Engine CKV - Supported host_algorithms. */
84 #define TLV_TYPE_ENGINE_CKV_HOST_ALGORITHMS UINT32_C(0x8006)
85 /* Engine CKV - The Host EC curve name and ECC public key information. */
86 #define TLV_TYPE_ENGINE_CKV_HOST_ECC_PUBLIC_KEY UINT32_C(0x8007)
87 /* Engine CKV - The ECDSA signature. */
88 #define TLV_TYPE_ENGINE_CKV_ECDSA_SIGNATURE UINT32_C(0x8008)
89 /* Engine CKV - The firmware EC curve name and ECC public key information. */
90 #define TLV_TYPE_ENGINE_CKV_FW_ECC_PUBLIC_KEY UINT32_C(0x8009)
91 /* Engine CKV - Supported firmware algorithms. */
92 #define TLV_TYPE_ENGINE_CKV_FW_ALGORITHMS UINT32_C(0x800a)
93 #define TLV_TYPE_LAST \
94 TLV_TYPE_ENGINE_CKV_FW_ALGORITHMS
97 /* tlv (size:64b/8B) */
100 * The command discriminator is used to differentiate between various
101 * types of HWRM messages. This includes legacy HWRM and RoCE slowpath
102 * command messages as well as newer TLV encapsulated HWRM commands.
104 * For TLV encapsulated messages this field must be 0x8000.
110 * Indicates the presence of additional TLV encapsulated data
113 #define TLV_FLAGS_MORE UINT32_C(0x1)
114 /* Last TLV in a sequence of TLVs. */
115 #define TLV_FLAGS_MORE_LAST UINT32_C(0x0)
116 /* More TLVs follow this TLV. */
117 #define TLV_FLAGS_MORE_NOT_LAST UINT32_C(0x1)
119 * When an HWRM receiver detects a TLV type that it does not
120 * support with the TLV required flag set, the receiver must
121 * reject the HWRM message with an error code indicating an
122 * unsupported TLV type.
124 #define TLV_FLAGS_REQUIRED UINT32_C(0x2)
126 #define TLV_FLAGS_REQUIRED_NO (UINT32_C(0x0) << 1)
128 #define TLV_FLAGS_REQUIRED_YES (UINT32_C(0x1) << 1)
129 #define TLV_FLAGS_REQUIRED_LAST TLV_FLAGS_REQUIRED_YES
131 * This field defines the TLV type value which is divided into
132 * two ranges to differentiate between global and local TLV types.
133 * Global TLV types must be unique across all defined TLV types.
134 * Local TLV types are valid only for extensions to a given
135 * HWRM message and may be repeated across different HWRM message
136 * types. There is a direct correlation of each HWRM message type
137 * to a single global TLV type value.
139 * Global TLV range: `0 - (63k-1)`
141 * Local TLV range: `63k - (64k-1)`
145 * Length of the message data encapsulated by this TLV in bytes.
146 * This length does not include the size of the TLV header itself
147 * and it must be an integer multiple of 8B.
153 /* input (size:128b/16B) */
156 * This value indicates what type of request this is. The format
157 * for the rest of the command is determined by this field.
161 * This value indicates the what completion ring the request will
162 * be optionally completed on. If the value is -1, then no
163 * CR completion will be generated. Any other value must be a
164 * valid CR ring_id value for this function.
167 /* This value indicates the command sequence number. */
170 * Target ID of this command.
172 * 0x0 - 0xFFF8 - Used for function ids
173 * 0xFFF8 - 0xFFFE - Reserved for internal processors
178 * This is the host address where the response will be written
179 * when the request is complete. This area must be 16B aligned
180 * and must be cleared to zero before the request is made.
186 /* output (size:64b/8B) */
189 * Pass/Fail or error type
191 * Note: receiver to verify the in parameters, and fail the call
192 * with an error when appropriate
195 /* This field returns the type of original request. */
197 /* This field provides original sequence number of the command. */
200 * This field is the length of the response in bytes. The
201 * last byte of the response is a valid flag that will read
202 * as '1' when the command has been completely written to
208 /* Short Command Structure */
209 /* hwrm_short_input (size:128b/16B) */
210 struct hwrm_short_input {
212 * This field indicates the type of request in the request buffer.
213 * The format for the rest of the command (request) is determined
218 * This field indicates a signature that is used to identify short
219 * form of the command listed here. This field shall be set to
223 /* Signature indicating this is a short form of HWRM command */
224 #define HWRM_SHORT_INPUT_SIGNATURE_SHORT_CMD UINT32_C(0x4321)
225 #define HWRM_SHORT_INPUT_SIGNATURE_LAST \
226 HWRM_SHORT_INPUT_SIGNATURE_SHORT_CMD
227 /* The target ID of the command */
229 /* Default target_id (0x0) to maintain compatibility with old driver */
230 #define HWRM_SHORT_INPUT_TARGET_ID_DEFAULT UINT32_C(0x0)
231 /* Reserved for user-space HWRM interface */
232 #define HWRM_SHORT_INPUT_TARGET_ID_TOOLS UINT32_C(0xfffd)
233 #define HWRM_SHORT_INPUT_TARGET_ID_LAST \
234 HWRM_SHORT_INPUT_TARGET_ID_TOOLS
235 /* This value indicates the length of the request. */
238 * This is the host address where the request was written.
239 * This area must be 16B aligned.
246 * # NOTE - definitions already in hwrm_req_type, in hwrm_types.yaml
247 * # So only structure definition is provided here.
249 /* cmd_nums (size:64b/8B) */
252 * This version of the specification defines the commands listed in
253 * the table below. The following are general implementation
254 * requirements for these commands:
256 * # All commands listed below that are marked neither
257 * reserved nor experimental shall be implemented by the HWRM.
258 * # A HWRM client compliant to this specification should not use
259 * commands outside of the list below.
260 * # A HWRM client compliant to this specification should not use
261 * command numbers marked reserved below.
262 * # A command marked experimental below may not be implemented
264 * # A command marked experimental may change in the
265 * future version of the HWRM specification.
266 * # A command not listed below may be implemented by the HWRM.
267 * The behavior of commands that are not listed below is outside
268 * the scope of this specification.
271 #define HWRM_VER_GET UINT32_C(0x0)
272 #define HWRM_ERROR_RECOVERY_QCFG UINT32_C(0xc)
273 #define HWRM_FUNC_DRV_IF_CHANGE UINT32_C(0xd)
274 #define HWRM_FUNC_BUF_UNRGTR UINT32_C(0xe)
275 #define HWRM_FUNC_VF_CFG UINT32_C(0xf)
276 /* Reserved for future use. */
277 #define HWRM_RESERVED1 UINT32_C(0x10)
278 #define HWRM_FUNC_RESET UINT32_C(0x11)
279 #define HWRM_FUNC_GETFID UINT32_C(0x12)
280 #define HWRM_FUNC_VF_ALLOC UINT32_C(0x13)
281 #define HWRM_FUNC_VF_FREE UINT32_C(0x14)
282 #define HWRM_FUNC_QCAPS UINT32_C(0x15)
283 #define HWRM_FUNC_QCFG UINT32_C(0x16)
284 #define HWRM_FUNC_CFG UINT32_C(0x17)
285 #define HWRM_FUNC_QSTATS UINT32_C(0x18)
286 #define HWRM_FUNC_CLR_STATS UINT32_C(0x19)
287 #define HWRM_FUNC_DRV_UNRGTR UINT32_C(0x1a)
288 #define HWRM_FUNC_VF_RESC_FREE UINT32_C(0x1b)
289 #define HWRM_FUNC_VF_VNIC_IDS_QUERY UINT32_C(0x1c)
290 #define HWRM_FUNC_DRV_RGTR UINT32_C(0x1d)
291 #define HWRM_FUNC_DRV_QVER UINT32_C(0x1e)
292 #define HWRM_FUNC_BUF_RGTR UINT32_C(0x1f)
293 #define HWRM_PORT_PHY_CFG UINT32_C(0x20)
294 #define HWRM_PORT_MAC_CFG UINT32_C(0x21)
296 #define HWRM_PORT_TS_QUERY UINT32_C(0x22)
297 #define HWRM_PORT_QSTATS UINT32_C(0x23)
298 #define HWRM_PORT_LPBK_QSTATS UINT32_C(0x24)
300 #define HWRM_PORT_CLR_STATS UINT32_C(0x25)
302 #define HWRM_PORT_LPBK_CLR_STATS UINT32_C(0x26)
303 #define HWRM_PORT_PHY_QCFG UINT32_C(0x27)
304 #define HWRM_PORT_MAC_QCFG UINT32_C(0x28)
306 #define HWRM_PORT_MAC_PTP_QCFG UINT32_C(0x29)
307 #define HWRM_PORT_PHY_QCAPS UINT32_C(0x2a)
308 #define HWRM_PORT_PHY_I2C_WRITE UINT32_C(0x2b)
309 #define HWRM_PORT_PHY_I2C_READ UINT32_C(0x2c)
310 #define HWRM_PORT_LED_CFG UINT32_C(0x2d)
311 #define HWRM_PORT_LED_QCFG UINT32_C(0x2e)
312 #define HWRM_PORT_LED_QCAPS UINT32_C(0x2f)
313 #define HWRM_QUEUE_QPORTCFG UINT32_C(0x30)
314 #define HWRM_QUEUE_QCFG UINT32_C(0x31)
315 #define HWRM_QUEUE_CFG UINT32_C(0x32)
316 #define HWRM_FUNC_VLAN_CFG UINT32_C(0x33)
317 #define HWRM_FUNC_VLAN_QCFG UINT32_C(0x34)
318 #define HWRM_QUEUE_PFCENABLE_QCFG UINT32_C(0x35)
319 #define HWRM_QUEUE_PFCENABLE_CFG UINT32_C(0x36)
320 #define HWRM_QUEUE_PRI2COS_QCFG UINT32_C(0x37)
321 #define HWRM_QUEUE_PRI2COS_CFG UINT32_C(0x38)
322 #define HWRM_QUEUE_COS2BW_QCFG UINT32_C(0x39)
323 #define HWRM_QUEUE_COS2BW_CFG UINT32_C(0x3a)
324 #define HWRM_QUEUE_DSCP_QCAPS UINT32_C(0x3b)
325 #define HWRM_QUEUE_DSCP2PRI_QCFG UINT32_C(0x3c)
326 #define HWRM_QUEUE_DSCP2PRI_CFG UINT32_C(0x3d)
327 #define HWRM_VNIC_ALLOC UINT32_C(0x40)
328 #define HWRM_VNIC_FREE UINT32_C(0x41)
329 #define HWRM_VNIC_CFG UINT32_C(0x42)
330 #define HWRM_VNIC_QCFG UINT32_C(0x43)
331 #define HWRM_VNIC_TPA_CFG UINT32_C(0x44)
333 #define HWRM_VNIC_TPA_QCFG UINT32_C(0x45)
334 #define HWRM_VNIC_RSS_CFG UINT32_C(0x46)
335 #define HWRM_VNIC_RSS_QCFG UINT32_C(0x47)
336 #define HWRM_VNIC_PLCMODES_CFG UINT32_C(0x48)
337 #define HWRM_VNIC_PLCMODES_QCFG UINT32_C(0x49)
338 #define HWRM_VNIC_QCAPS UINT32_C(0x4a)
339 #define HWRM_RING_ALLOC UINT32_C(0x50)
340 #define HWRM_RING_FREE UINT32_C(0x51)
341 #define HWRM_RING_CMPL_RING_QAGGINT_PARAMS UINT32_C(0x52)
342 #define HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS UINT32_C(0x53)
343 #define HWRM_RING_AGGINT_QCAPS UINT32_C(0x54)
344 #define HWRM_RING_RESET UINT32_C(0x5e)
345 #define HWRM_RING_GRP_ALLOC UINT32_C(0x60)
346 #define HWRM_RING_GRP_FREE UINT32_C(0x61)
347 /* Reserved for future use. */
348 #define HWRM_RESERVED5 UINT32_C(0x64)
349 /* Reserved for future use. */
350 #define HWRM_RESERVED6 UINT32_C(0x65)
351 #define HWRM_VNIC_RSS_COS_LB_CTX_ALLOC UINT32_C(0x70)
352 #define HWRM_VNIC_RSS_COS_LB_CTX_FREE UINT32_C(0x71)
353 #define HWRM_QUEUE_MPLS_QCAPS UINT32_C(0x80)
354 #define HWRM_QUEUE_MPLSTC2PRI_QCFG UINT32_C(0x81)
355 #define HWRM_QUEUE_MPLSTC2PRI_CFG UINT32_C(0x82)
356 #define HWRM_CFA_L2_FILTER_ALLOC UINT32_C(0x90)
357 #define HWRM_CFA_L2_FILTER_FREE UINT32_C(0x91)
358 #define HWRM_CFA_L2_FILTER_CFG UINT32_C(0x92)
359 #define HWRM_CFA_L2_SET_RX_MASK UINT32_C(0x93)
360 #define HWRM_CFA_VLAN_ANTISPOOF_CFG UINT32_C(0x94)
361 #define HWRM_CFA_TUNNEL_FILTER_ALLOC UINT32_C(0x95)
362 #define HWRM_CFA_TUNNEL_FILTER_FREE UINT32_C(0x96)
364 #define HWRM_CFA_ENCAP_RECORD_ALLOC UINT32_C(0x97)
366 #define HWRM_CFA_ENCAP_RECORD_FREE UINT32_C(0x98)
367 #define HWRM_CFA_NTUPLE_FILTER_ALLOC UINT32_C(0x99)
368 #define HWRM_CFA_NTUPLE_FILTER_FREE UINT32_C(0x9a)
369 #define HWRM_CFA_NTUPLE_FILTER_CFG UINT32_C(0x9b)
371 #define HWRM_CFA_EM_FLOW_ALLOC UINT32_C(0x9c)
373 #define HWRM_CFA_EM_FLOW_FREE UINT32_C(0x9d)
375 #define HWRM_CFA_EM_FLOW_CFG UINT32_C(0x9e)
376 #define HWRM_TUNNEL_DST_PORT_QUERY UINT32_C(0xa0)
377 #define HWRM_TUNNEL_DST_PORT_ALLOC UINT32_C(0xa1)
378 #define HWRM_TUNNEL_DST_PORT_FREE UINT32_C(0xa2)
379 #define HWRM_STAT_CTX_ENG_QUERY UINT32_C(0xaf)
380 #define HWRM_STAT_CTX_ALLOC UINT32_C(0xb0)
381 #define HWRM_STAT_CTX_FREE UINT32_C(0xb1)
382 #define HWRM_STAT_CTX_QUERY UINT32_C(0xb2)
383 #define HWRM_STAT_CTX_CLR_STATS UINT32_C(0xb3)
384 #define HWRM_PORT_QSTATS_EXT UINT32_C(0xb4)
385 #define HWRM_PORT_PHY_MDIO_WRITE UINT32_C(0xb5)
386 #define HWRM_PORT_PHY_MDIO_READ UINT32_C(0xb6)
387 #define HWRM_PORT_PHY_MDIO_BUS_ACQUIRE UINT32_C(0xb7)
388 #define HWRM_PORT_PHY_MDIO_BUS_RELEASE UINT32_C(0xb8)
389 #define HWRM_PORT_QSTATS_EXT_PFC_WD UINT32_C(0xb9)
390 #define HWRM_PORT_ECN_QSTATS UINT32_C(0xba)
391 #define HWRM_FW_RESET UINT32_C(0xc0)
392 #define HWRM_FW_QSTATUS UINT32_C(0xc1)
393 #define HWRM_FW_HEALTH_CHECK UINT32_C(0xc2)
394 #define HWRM_FW_SYNC UINT32_C(0xc3)
395 #define HWRM_FW_STATE_QCAPS UINT32_C(0xc4)
396 #define HWRM_FW_STATE_QUIESCE UINT32_C(0xc5)
397 #define HWRM_FW_STATE_BACKUP UINT32_C(0xc6)
398 #define HWRM_FW_STATE_RESTORE UINT32_C(0xc7)
400 #define HWRM_FW_SET_TIME UINT32_C(0xc8)
402 #define HWRM_FW_GET_TIME UINT32_C(0xc9)
404 #define HWRM_FW_SET_STRUCTURED_DATA UINT32_C(0xca)
406 #define HWRM_FW_GET_STRUCTURED_DATA UINT32_C(0xcb)
408 #define HWRM_FW_IPC_MAILBOX UINT32_C(0xcc)
409 #define HWRM_FW_ECN_CFG UINT32_C(0xcd)
410 #define HWRM_FW_ECN_QCFG UINT32_C(0xce)
411 #define HWRM_EXEC_FWD_RESP UINT32_C(0xd0)
412 #define HWRM_REJECT_FWD_RESP UINT32_C(0xd1)
413 #define HWRM_FWD_RESP UINT32_C(0xd2)
414 #define HWRM_FWD_ASYNC_EVENT_CMPL UINT32_C(0xd3)
415 #define HWRM_OEM_CMD UINT32_C(0xd4)
416 /* Tells the fw to run PRBS test on a given port and lane. */
417 #define HWRM_PORT_PRBS_TEST UINT32_C(0xd5)
418 #define HWRM_PORT_SFP_SIDEBAND_CFG UINT32_C(0xd6)
419 #define HWRM_PORT_SFP_SIDEBAND_QCFG UINT32_C(0xd7)
420 #define HWRM_FW_STATE_UNQUIESCE UINT32_C(0xd8)
421 /* Tells the fw to collect dsc dump on a given port and lane. */
422 #define HWRM_PORT_DSC_DUMP UINT32_C(0xd9)
423 #define HWRM_TEMP_MONITOR_QUERY UINT32_C(0xe0)
424 #define HWRM_REG_POWER_QUERY UINT32_C(0xe1)
425 #define HWRM_CORE_FREQUENCY_QUERY UINT32_C(0xe2)
426 #define HWRM_REG_POWER_HISTOGRAM UINT32_C(0xe3)
427 #define HWRM_WOL_FILTER_ALLOC UINT32_C(0xf0)
428 #define HWRM_WOL_FILTER_FREE UINT32_C(0xf1)
429 #define HWRM_WOL_FILTER_QCFG UINT32_C(0xf2)
430 #define HWRM_WOL_REASON_QCFG UINT32_C(0xf3)
432 #define HWRM_CFA_METER_QCAPS UINT32_C(0xf4)
434 #define HWRM_CFA_METER_PROFILE_ALLOC UINT32_C(0xf5)
436 #define HWRM_CFA_METER_PROFILE_FREE UINT32_C(0xf6)
438 #define HWRM_CFA_METER_PROFILE_CFG UINT32_C(0xf7)
440 #define HWRM_CFA_METER_INSTANCE_ALLOC UINT32_C(0xf8)
442 #define HWRM_CFA_METER_INSTANCE_FREE UINT32_C(0xf9)
444 #define HWRM_CFA_METER_INSTANCE_CFG UINT32_C(0xfa)
446 #define HWRM_CFA_VFR_ALLOC UINT32_C(0xfd)
448 #define HWRM_CFA_VFR_FREE UINT32_C(0xfe)
450 #define HWRM_CFA_VF_PAIR_ALLOC UINT32_C(0x100)
452 #define HWRM_CFA_VF_PAIR_FREE UINT32_C(0x101)
454 #define HWRM_CFA_VF_PAIR_INFO UINT32_C(0x102)
456 #define HWRM_CFA_FLOW_ALLOC UINT32_C(0x103)
458 #define HWRM_CFA_FLOW_FREE UINT32_C(0x104)
460 #define HWRM_CFA_FLOW_FLUSH UINT32_C(0x105)
462 #define HWRM_CFA_FLOW_STATS UINT32_C(0x106)
464 #define HWRM_CFA_FLOW_INFO UINT32_C(0x107)
466 #define HWRM_CFA_DECAP_FILTER_ALLOC UINT32_C(0x108)
468 #define HWRM_CFA_DECAP_FILTER_FREE UINT32_C(0x109)
469 #define HWRM_CFA_VLAN_ANTISPOOF_QCFG UINT32_C(0x10a)
470 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_ALLOC UINT32_C(0x10b)
471 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_FREE UINT32_C(0x10c)
473 #define HWRM_CFA_PAIR_ALLOC UINT32_C(0x10d)
475 #define HWRM_CFA_PAIR_FREE UINT32_C(0x10e)
477 #define HWRM_CFA_PAIR_INFO UINT32_C(0x10f)
479 #define HWRM_FW_IPC_MSG UINT32_C(0x110)
480 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_INFO UINT32_C(0x111)
481 #define HWRM_CFA_REDIRECT_QUERY_TUNNEL_TYPE UINT32_C(0x112)
483 #define HWRM_CFA_FLOW_AGING_TIMER_RESET UINT32_C(0x113)
485 #define HWRM_CFA_FLOW_AGING_CFG UINT32_C(0x114)
487 #define HWRM_CFA_FLOW_AGING_QCFG UINT32_C(0x115)
489 #define HWRM_CFA_FLOW_AGING_QCAPS UINT32_C(0x116)
491 #define HWRM_CFA_CTX_MEM_RGTR UINT32_C(0x117)
493 #define HWRM_CFA_CTX_MEM_UNRGTR UINT32_C(0x118)
495 #define HWRM_CFA_CTX_MEM_QCTX UINT32_C(0x119)
497 #define HWRM_CFA_CTX_MEM_QCAPS UINT32_C(0x11a)
499 #define HWRM_CFA_COUNTER_QCAPS UINT32_C(0x11b)
501 #define HWRM_CFA_COUNTER_CFG UINT32_C(0x11c)
503 #define HWRM_CFA_COUNTER_QCFG UINT32_C(0x11d)
505 #define HWRM_CFA_COUNTER_QSTATS UINT32_C(0x11e)
507 #define HWRM_CFA_TCP_FLAG_PROCESS_QCFG UINT32_C(0x11f)
509 #define HWRM_CFA_EEM_QCAPS UINT32_C(0x120)
511 #define HWRM_CFA_EEM_CFG UINT32_C(0x121)
513 #define HWRM_CFA_EEM_QCFG UINT32_C(0x122)
515 #define HWRM_CFA_EEM_OP UINT32_C(0x123)
517 #define HWRM_CFA_ADV_FLOW_MGNT_QCAPS UINT32_C(0x124)
518 /* Experimental - DEPRECATED */
519 #define HWRM_CFA_TFLIB UINT32_C(0x125)
520 /* Engine CKV - Get the current allocation status of keys provisioned in the key vault. */
521 #define HWRM_ENGINE_CKV_STATUS UINT32_C(0x12e)
522 /* Engine CKV - Add a new CKEK used to encrypt keys. */
523 #define HWRM_ENGINE_CKV_CKEK_ADD UINT32_C(0x12f)
524 /* Engine CKV - Delete a previously added CKEK. */
525 #define HWRM_ENGINE_CKV_CKEK_DELETE UINT32_C(0x130)
526 /* Engine CKV - Add a new key to the key vault. */
527 #define HWRM_ENGINE_CKV_KEY_ADD UINT32_C(0x131)
528 /* Engine CKV - Delete a key from the key vault. */
529 #define HWRM_ENGINE_CKV_KEY_DELETE UINT32_C(0x132)
530 /* Engine CKV - Delete all keys from the key vault. */
531 #define HWRM_ENGINE_CKV_FLUSH UINT32_C(0x133)
532 /* Engine CKV - Get random data. */
533 #define HWRM_ENGINE_CKV_RNG_GET UINT32_C(0x134)
534 /* Engine CKV - Generate and encrypt a new AES key. */
535 #define HWRM_ENGINE_CKV_KEY_GEN UINT32_C(0x135)
536 /* Engine CKV - Configure a label index with a label value. */
537 #define HWRM_ENGINE_CKV_KEY_LABEL_CFG UINT32_C(0x136)
538 /* Engine CKV - Query a label */
539 #define HWRM_ENGINE_CKV_KEY_LABEL_QCFG UINT32_C(0x137)
540 /* Engine - Query the available queue groups configuration. */
541 #define HWRM_ENGINE_QG_CONFIG_QUERY UINT32_C(0x13c)
542 /* Engine - Query the queue groups assigned to a function. */
543 #define HWRM_ENGINE_QG_QUERY UINT32_C(0x13d)
544 /* Engine - Query the available queue group meter profile configuration. */
545 #define HWRM_ENGINE_QG_METER_PROFILE_CONFIG_QUERY UINT32_C(0x13e)
546 /* Engine - Query the configuration of a queue group meter profile. */
547 #define HWRM_ENGINE_QG_METER_PROFILE_QUERY UINT32_C(0x13f)
548 /* Engine - Allocate a queue group meter profile. */
549 #define HWRM_ENGINE_QG_METER_PROFILE_ALLOC UINT32_C(0x140)
550 /* Engine - Free a queue group meter profile. */
551 #define HWRM_ENGINE_QG_METER_PROFILE_FREE UINT32_C(0x141)
552 /* Engine - Query the meters assigned to a queue group. */
553 #define HWRM_ENGINE_QG_METER_QUERY UINT32_C(0x142)
554 /* Engine - Bind a queue group meter profile to a queue group. */
555 #define HWRM_ENGINE_QG_METER_BIND UINT32_C(0x143)
556 /* Engine - Unbind a queue group meter profile from a queue group. */
557 #define HWRM_ENGINE_QG_METER_UNBIND UINT32_C(0x144)
558 /* Engine - Bind a queue group to a function. */
559 #define HWRM_ENGINE_QG_FUNC_BIND UINT32_C(0x145)
560 /* Engine - Query the scheduling group configuration. */
561 #define HWRM_ENGINE_SG_CONFIG_QUERY UINT32_C(0x146)
562 /* Engine - Query the queue groups assigned to a scheduling group. */
563 #define HWRM_ENGINE_SG_QUERY UINT32_C(0x147)
564 /* Engine - Query the configuration of a scheduling group's meter profiles. */
565 #define HWRM_ENGINE_SG_METER_QUERY UINT32_C(0x148)
566 /* Engine - Configure a scheduling group's meter profiles. */
567 #define HWRM_ENGINE_SG_METER_CONFIG UINT32_C(0x149)
568 /* Engine - Bind a queue group to a scheduling group. */
569 #define HWRM_ENGINE_SG_QG_BIND UINT32_C(0x14a)
570 /* Engine - Unbind a queue group from its scheduling group. */
571 #define HWRM_ENGINE_QG_SG_UNBIND UINT32_C(0x14b)
572 /* Engine - Query the Engine configuration. */
573 #define HWRM_ENGINE_CONFIG_QUERY UINT32_C(0x154)
574 /* Engine - Configure the statistics accumulator for an Engine. */
575 #define HWRM_ENGINE_STATS_CONFIG UINT32_C(0x155)
576 /* Engine - Clear the statistics accumulator for an Engine. */
577 #define HWRM_ENGINE_STATS_CLEAR UINT32_C(0x156)
578 /* Engine - Query the statistics accumulator for an Engine. */
579 #define HWRM_ENGINE_STATS_QUERY UINT32_C(0x157)
580 /* Engine - Query statistics counters for continuous errors from all CDDIP Engines. */
581 #define HWRM_ENGINE_STATS_QUERY_CONTINUOUS_ERROR UINT32_C(0x158)
582 /* Engine - Allocate an Engine RQ. */
583 #define HWRM_ENGINE_RQ_ALLOC UINT32_C(0x15e)
584 /* Engine - Free an Engine RQ. */
585 #define HWRM_ENGINE_RQ_FREE UINT32_C(0x15f)
586 /* Engine - Allocate an Engine CQ. */
587 #define HWRM_ENGINE_CQ_ALLOC UINT32_C(0x160)
588 /* Engine - Free an Engine CQ. */
589 #define HWRM_ENGINE_CQ_FREE UINT32_C(0x161)
590 /* Engine - Allocate an NQ. */
591 #define HWRM_ENGINE_NQ_ALLOC UINT32_C(0x162)
592 /* Engine - Free an NQ. */
593 #define HWRM_ENGINE_NQ_FREE UINT32_C(0x163)
594 /* Engine - Set the on-die RQE credit update location. */
595 #define HWRM_ENGINE_ON_DIE_RQE_CREDITS UINT32_C(0x164)
596 /* Engine - Query the engine function configuration. */
597 #define HWRM_ENGINE_FUNC_QCFG UINT32_C(0x165)
599 #define HWRM_FUNC_RESOURCE_QCAPS UINT32_C(0x190)
601 #define HWRM_FUNC_VF_RESOURCE_CFG UINT32_C(0x191)
603 #define HWRM_FUNC_BACKING_STORE_QCAPS UINT32_C(0x192)
605 #define HWRM_FUNC_BACKING_STORE_CFG UINT32_C(0x193)
607 #define HWRM_FUNC_BACKING_STORE_QCFG UINT32_C(0x194)
608 /* Configures the BW of any VF */
609 #define HWRM_FUNC_VF_BW_CFG UINT32_C(0x195)
610 /* Queries the BW of any VF */
611 #define HWRM_FUNC_VF_BW_QCFG UINT32_C(0x196)
612 /* Queries pf ids belong to specified host(s) */
613 #define HWRM_FUNC_HOST_PF_IDS_QUERY UINT32_C(0x197)
615 #define HWRM_SELFTEST_QLIST UINT32_C(0x200)
617 #define HWRM_SELFTEST_EXEC UINT32_C(0x201)
619 #define HWRM_SELFTEST_IRQ UINT32_C(0x202)
621 #define HWRM_SELFTEST_RETRIEVE_SERDES_DATA UINT32_C(0x203)
623 #define HWRM_PCIE_QSTATS UINT32_C(0x204)
625 #define HWRM_MFG_FRU_WRITE_CONTROL UINT32_C(0x205)
626 /* Returns the current value of a free running counter from the device. */
627 #define HWRM_MFG_TIMERS_QUERY UINT32_C(0x206)
629 #define HWRM_MFG_OTP_CFG UINT32_C(0x207)
631 #define HWRM_MFG_OTP_QCFG UINT32_C(0x208)
633 * Tells the fw to run the DMA read from the host and DMA write
636 #define HWRM_MFG_HDMA_TEST UINT32_C(0x209)
637 /* Tells the fw to program the fru memory */
638 #define HWRM_MFG_FRU_EEPROM_WRITE UINT32_C(0x20a)
639 /* Tells the fw to read the fru memory */
640 #define HWRM_MFG_FRU_EEPROM_READ UINT32_C(0x20b)
642 #define HWRM_TF UINT32_C(0x2bc)
644 #define HWRM_TF_VERSION_GET UINT32_C(0x2bd)
646 #define HWRM_TF_SESSION_OPEN UINT32_C(0x2c6)
648 #define HWRM_TF_SESSION_ATTACH UINT32_C(0x2c7)
650 #define HWRM_TF_SESSION_CLOSE UINT32_C(0x2c8)
652 #define HWRM_TF_SESSION_QCFG UINT32_C(0x2c9)
654 #define HWRM_TF_SESSION_RESC_QCAPS UINT32_C(0x2ca)
656 #define HWRM_TF_SESSION_RESC_ALLOC UINT32_C(0x2cb)
658 #define HWRM_TF_SESSION_RESC_FREE UINT32_C(0x2cc)
660 #define HWRM_TF_SESSION_RESC_FLUSH UINT32_C(0x2cd)
662 #define HWRM_TF_TBL_TYPE_GET UINT32_C(0x2d0)
664 #define HWRM_TF_TBL_TYPE_SET UINT32_C(0x2d1)
666 #define HWRM_TF_CTXT_MEM_RGTR UINT32_C(0x2da)
668 #define HWRM_TF_CTXT_MEM_UNRGTR UINT32_C(0x2db)
670 #define HWRM_TF_EXT_EM_QCAPS UINT32_C(0x2dc)
672 #define HWRM_TF_EXT_EM_OP UINT32_C(0x2dd)
674 #define HWRM_TF_EXT_EM_CFG UINT32_C(0x2de)
676 #define HWRM_TF_EXT_EM_QCFG UINT32_C(0x2df)
678 #define HWRM_TF_TCAM_SET UINT32_C(0x2ee)
680 #define HWRM_TF_TCAM_GET UINT32_C(0x2ef)
682 #define HWRM_TF_TCAM_MOVE UINT32_C(0x2f0)
684 #define HWRM_TF_TCAM_FREE UINT32_C(0x2f1)
686 #define HWRM_SV UINT32_C(0x400)
688 #define HWRM_DBG_READ_DIRECT UINT32_C(0xff10)
690 #define HWRM_DBG_READ_INDIRECT UINT32_C(0xff11)
692 #define HWRM_DBG_WRITE_DIRECT UINT32_C(0xff12)
694 #define HWRM_DBG_WRITE_INDIRECT UINT32_C(0xff13)
695 #define HWRM_DBG_DUMP UINT32_C(0xff14)
697 #define HWRM_DBG_ERASE_NVM UINT32_C(0xff15)
699 #define HWRM_DBG_CFG UINT32_C(0xff16)
701 #define HWRM_DBG_COREDUMP_LIST UINT32_C(0xff17)
703 #define HWRM_DBG_COREDUMP_INITIATE UINT32_C(0xff18)
705 #define HWRM_DBG_COREDUMP_RETRIEVE UINT32_C(0xff19)
707 #define HWRM_DBG_FW_CLI UINT32_C(0xff1a)
709 #define HWRM_DBG_I2C_CMD UINT32_C(0xff1b)
711 #define HWRM_DBG_RING_INFO_GET UINT32_C(0xff1c)
713 #define HWRM_DBG_CRASHDUMP_HEADER UINT32_C(0xff1d)
715 #define HWRM_DBG_CRASHDUMP_ERASE UINT32_C(0xff1e)
716 /* Send driver debug information to firmware */
717 #define HWRM_DBG_DRV_TRACE UINT32_C(0xff1f)
719 #define HWRM_NVM_FACTORY_DEFAULTS UINT32_C(0xffee)
720 #define HWRM_NVM_VALIDATE_OPTION UINT32_C(0xffef)
721 #define HWRM_NVM_FLUSH UINT32_C(0xfff0)
722 #define HWRM_NVM_GET_VARIABLE UINT32_C(0xfff1)
723 #define HWRM_NVM_SET_VARIABLE UINT32_C(0xfff2)
724 #define HWRM_NVM_INSTALL_UPDATE UINT32_C(0xfff3)
725 #define HWRM_NVM_MODIFY UINT32_C(0xfff4)
726 #define HWRM_NVM_VERIFY_UPDATE UINT32_C(0xfff5)
727 #define HWRM_NVM_GET_DEV_INFO UINT32_C(0xfff6)
728 #define HWRM_NVM_ERASE_DIR_ENTRY UINT32_C(0xfff7)
729 #define HWRM_NVM_MOD_DIR_ENTRY UINT32_C(0xfff8)
730 #define HWRM_NVM_FIND_DIR_ENTRY UINT32_C(0xfff9)
731 #define HWRM_NVM_GET_DIR_ENTRIES UINT32_C(0xfffa)
732 #define HWRM_NVM_GET_DIR_INFO UINT32_C(0xfffb)
733 #define HWRM_NVM_RAW_DUMP UINT32_C(0xfffc)
734 #define HWRM_NVM_READ UINT32_C(0xfffd)
735 #define HWRM_NVM_WRITE UINT32_C(0xfffe)
736 #define HWRM_NVM_RAW_WRITE_BLK UINT32_C(0xffff)
737 #define HWRM_LAST HWRM_NVM_RAW_WRITE_BLK
738 uint16_t unused_0[3];
742 /* ret_codes (size:64b/8B) */
745 /* Request was successfully executed by the HWRM. */
746 #define HWRM_ERR_CODE_SUCCESS UINT32_C(0x0)
747 /* The HWRM failed to execute the request. */
748 #define HWRM_ERR_CODE_FAIL UINT32_C(0x1)
750 * The request contains invalid argument(s) or input
753 #define HWRM_ERR_CODE_INVALID_PARAMS UINT32_C(0x2)
755 * The requester is not allowed to access the requested
756 * resource. This error code shall be provided in a
757 * response to a request to query or modify an existing
758 * resource that is not accessible by the requester.
760 #define HWRM_ERR_CODE_RESOURCE_ACCESS_DENIED UINT32_C(0x3)
762 * The HWRM is unable to allocate the requested resource.
763 * This code only applies to requests for HWRM resource
766 #define HWRM_ERR_CODE_RESOURCE_ALLOC_ERROR UINT32_C(0x4)
768 * Invalid combination of flags is specified in the
771 #define HWRM_ERR_CODE_INVALID_FLAGS UINT32_C(0x5)
773 * Invalid combination of enables fields is specified in
776 #define HWRM_ERR_CODE_INVALID_ENABLES UINT32_C(0x6)
778 * Request contains a required TLV that is not supported by
779 * the installed version of firmware.
781 #define HWRM_ERR_CODE_UNSUPPORTED_TLV UINT32_C(0x7)
783 * No firmware buffer available to accept the request. Driver
784 * should retry the request.
786 #define HWRM_ERR_CODE_NO_BUFFER UINT32_C(0x8)
788 * This error code is only reported by firmware when some
789 * sub-option of a supported HWRM command is unsupported.
791 #define HWRM_ERR_CODE_UNSUPPORTED_OPTION_ERR UINT32_C(0x9)
793 * This error code is only reported by firmware when the specific
794 * request is not able to process when the HOT reset in progress.
796 #define HWRM_ERR_CODE_HOT_RESET_PROGRESS UINT32_C(0xa)
798 * This error code is only reported by firmware when the registered
799 * driver instances are not capable of hot reset.
801 #define HWRM_ERR_CODE_HOT_RESET_FAIL UINT32_C(0xb)
803 * This error code is only reported by the firmware when during
804 * flow allocation when a request for a flow counter fails because
805 * the number of flow counters are exhausted.
807 #define HWRM_ERR_CODE_NO_FLOW_COUNTER_DURING_ALLOC UINT32_C(0xc)
809 * This error code is only reported by firmware when the registered
810 * driver instances requested to offloaded a flow but was unable to because
811 * the requested key's hash collides with the installed keys.
813 #define HWRM_ERR_CODE_KEY_HASH_COLLISION UINT32_C(0xd)
815 * This error code is only reported by firmware when the registered
816 * driver instances requested to offloaded a flow but was unable to because
817 * the same key has already been installed.
819 #define HWRM_ERR_CODE_KEY_ALREADY_EXISTS UINT32_C(0xe)
821 * Generic HWRM execution error that represents an
824 #define HWRM_ERR_CODE_HWRM_ERROR UINT32_C(0xf)
826 * Firmware is unable to service the request at the present time. Caller
827 * may try again later.
829 #define HWRM_ERR_CODE_BUSY UINT32_C(0x10)
831 * This value indicates that the HWRM response is in TLV format and
832 * should be interpreted as one or more TLVs starting with the
833 * hwrm_resp_hdr TLV. This value is not an indication of any error
834 * by itself, just an indication that the response should be parsed
835 * as TLV and the actual error code will be in the hwrm_resp_hdr TLV.
837 #define HWRM_ERR_CODE_TLV_ENCAPSULATED_RESPONSE UINT32_C(0x8000)
839 #define HWRM_ERR_CODE_UNKNOWN_ERR UINT32_C(0xfffe)
840 /* Unsupported or invalid command */
841 #define HWRM_ERR_CODE_CMD_NOT_SUPPORTED UINT32_C(0xffff)
842 #define HWRM_ERR_CODE_LAST \
843 HWRM_ERR_CODE_CMD_NOT_SUPPORTED
844 uint16_t unused_0[3];
848 /* hwrm_err_output (size:128b/16B) */
849 struct hwrm_err_output {
851 * Pass/Fail or error type
853 * Note: receiver to verify the in parameters, and fail the call
854 * with an error when appropriate
857 /* This field returns the type of original request. */
859 /* This field provides original sequence number of the command. */
862 * This field is the length of the response in bytes. The
863 * last byte of the response is a valid flag that will read
864 * as '1' when the command has been completely written to
868 /* debug info for this error response. */
870 /* debug info for this error response. */
873 * In the case of an error response, command specific error
874 * code is returned in this field.
878 * This field is used in Output records to indicate that the output
879 * is completely written to RAM. This field should be read as '1'
880 * to indicate that the output has been completely written.
881 * When writing a command completion or response to an internal processor,
882 * the order of writes has to be such that this field is written last.
887 * Following is the signature for HWRM message field that indicates not
888 * applicable (All F's). Need to cast it the size of the field if needed.
890 #define HWRM_NA_SIGNATURE ((uint32_t)(-1))
891 /* hwrm_func_buf_rgtr */
892 #define HWRM_MAX_REQ_LEN 128
893 /* hwrm_cfa_flow_info */
894 #define HWRM_MAX_RESP_LEN 704
895 /* 7 bit indirection table index. */
896 #define HW_HASH_INDEX_SIZE 0x80
897 #define HW_HASH_KEY_SIZE 40
898 /* valid key for HWRM response */
899 #define HWRM_RESP_VALID_KEY 1
900 /* Reserved for BONO processor */
901 #define HWRM_TARGET_ID_BONO 0xFFF8
902 /* Reserved for KONG processor */
903 #define HWRM_TARGET_ID_KONG 0xFFF9
904 /* Reserved for APE processor */
905 #define HWRM_TARGET_ID_APE 0xFFFA
907 * This value will be used by tools for User-space HWRM Interface.
908 * When tool execute any HWRM command with this target_id, firmware
909 * will copy the response and/or data payload via register space instead
912 #define HWRM_TARGET_ID_TOOLS 0xFFFD
913 #define HWRM_VERSION_MAJOR 1
914 #define HWRM_VERSION_MINOR 10
915 #define HWRM_VERSION_UPDATE 1
916 /* non-zero means beta version */
917 #define HWRM_VERSION_RSVD 30
918 #define HWRM_VERSION_STR "1.10.1.30"
925 /* hwrm_ver_get_input (size:192b/24B) */
926 struct hwrm_ver_get_input {
927 /* The HWRM command request type. */
930 * The completion ring to send the completion event on. This should
931 * be the NQ ID returned from the `nq_alloc` HWRM command.
935 * The sequence ID is used by the driver for tracking multiple
936 * commands. This ID is treated as opaque data by the firmware and
937 * the value is returned in the `hwrm_resp_hdr` upon completion.
941 * The target ID of the command:
942 * * 0x0-0xFFF8 - The function ID
943 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
944 * * 0xFFFD - Reserved for user-space HWRM interface
949 * A physical address pointer pointing to a host buffer that the
950 * command's response data will be written. This can be either a host
951 * physical address (HPA) or a guest physical address (GPA) and must
952 * point to a physically contiguous block of memory.
956 * This field represents the major version of HWRM interface
957 * specification supported by the driver HWRM implementation.
958 * The interface major version is intended to change only when
959 * non backward compatible changes are made to the HWRM
960 * interface specification.
962 uint8_t hwrm_intf_maj;
964 * This field represents the minor version of HWRM interface
965 * specification supported by the driver HWRM implementation.
966 * A change in interface minor version is used to reflect
967 * significant backward compatible modification to HWRM
968 * interface specification.
969 * This can be due to addition or removal of functionality.
970 * HWRM interface specifications with the same major version
971 * but different minor versions are compatible.
973 uint8_t hwrm_intf_min;
975 * This field represents the update version of HWRM interface
976 * specification supported by the driver HWRM implementation.
977 * The interface update version is used to reflect minor
978 * changes or bug fixes to a released HWRM interface
981 uint8_t hwrm_intf_upd;
985 /* hwrm_ver_get_output (size:1408b/176B) */
986 struct hwrm_ver_get_output {
987 /* The specific error status for the command. */
989 /* The HWRM command request type. */
991 /* The sequence ID from the original command. */
993 /* The length of the response data in number of bytes. */
996 * This field represents the major version of HWRM interface
997 * specification supported by the HWRM implementation.
998 * The interface major version is intended to change only when
999 * non backward compatible changes are made to the HWRM
1000 * interface specification.
1001 * A HWRM implementation that is compliant with this
1002 * specification shall provide value of 1 in this field.
1004 uint8_t hwrm_intf_maj_8b;
1006 * This field represents the minor version of HWRM interface
1007 * specification supported by the HWRM implementation.
1008 * A change in interface minor version is used to reflect
1009 * significant backward compatible modification to HWRM
1010 * interface specification.
1011 * This can be due to addition or removal of functionality.
1012 * HWRM interface specifications with the same major version
1013 * but different minor versions are compatible.
1014 * A HWRM implementation that is compliant with this
1015 * specification shall provide value of 2 in this field.
1017 uint8_t hwrm_intf_min_8b;
1019 * This field represents the update version of HWRM interface
1020 * specification supported by the HWRM implementation.
1021 * The interface update version is used to reflect minor
1022 * changes or bug fixes to a released HWRM interface
1024 * A HWRM implementation that is compliant with this
1025 * specification shall provide value of 2 in this field.
1027 uint8_t hwrm_intf_upd_8b;
1028 uint8_t hwrm_intf_rsvd_8b;
1030 * This field represents the major version of HWRM firmware.
1031 * A change in firmware major version represents a major
1034 uint8_t hwrm_fw_maj_8b;
1036 * This field represents the minor version of HWRM firmware.
1037 * A change in firmware minor version represents significant
1038 * firmware functionality changes.
1040 uint8_t hwrm_fw_min_8b;
1042 * This field represents the build version of HWRM firmware.
1043 * A change in firmware build version represents bug fixes
1044 * to a released firmware.
1046 uint8_t hwrm_fw_bld_8b;
1048 * This field is a reserved field. This field can be used to
1049 * represent firmware branches or customer specific releases
1050 * tied to a specific (major,minor,update) version of the
1053 uint8_t hwrm_fw_rsvd_8b;
1055 * This field represents the major version of mgmt firmware.
1056 * A change in major version represents a major release.
1058 uint8_t mgmt_fw_maj_8b;
1060 * This field represents the minor version of mgmt firmware.
1061 * A change in minor version represents significant
1062 * functionality changes.
1064 uint8_t mgmt_fw_min_8b;
1066 * This field represents the build version of mgmt firmware.
1067 * A change in update version represents bug fixes.
1069 uint8_t mgmt_fw_bld_8b;
1071 * This field is a reserved field. This field can be used to
1072 * represent firmware branches or customer specific releases
1073 * tied to a specific (major,minor,update) version
1075 uint8_t mgmt_fw_rsvd_8b;
1077 * This field represents the major version of network
1079 * A change in major version represents a major release.
1081 uint8_t netctrl_fw_maj_8b;
1083 * This field represents the minor version of network
1085 * A change in minor version represents significant
1086 * functionality changes.
1088 uint8_t netctrl_fw_min_8b;
1090 * This field represents the build version of network
1092 * A change in update version represents bug fixes.
1094 uint8_t netctrl_fw_bld_8b;
1096 * This field is a reserved field. This field can be used to
1097 * represent firmware branches or customer specific releases
1098 * tied to a specific (major,minor,update) version
1100 uint8_t netctrl_fw_rsvd_8b;
1102 * This field is used to indicate device's capabilities and
1105 uint32_t dev_caps_cfg;
1107 * If set to 1, then secure firmware update behavior
1109 * If set to 0, then secure firmware update behavior is
1112 #define HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_SECURE_FW_UPD_SUPPORTED \
1115 * If set to 1, then firmware based DCBX agent is supported.
1116 * If set to 0, then firmware based DCBX agent capability
1117 * is not supported on this device.
1119 #define HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_FW_DCBX_AGENT_SUPPORTED \
1122 * If set to 1, then HWRM short command format is supported.
1123 * If set to 0, then HWRM short command format is not supported.
1125 #define HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_SHORT_CMD_SUPPORTED \
1128 * If set to 1, then HWRM short command format is required.
1129 * If set to 0, then HWRM short command format is not required.
1131 #define HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_SHORT_CMD_REQUIRED \
1134 * If set to 1, then the KONG host mailbox channel is supported.
1135 * If set to 0, then the KONG host mailbox channel is not supported.
1136 * By default, this flag should be 0 for older version of core firmware.
1138 #define HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_KONG_MB_CHNL_SUPPORTED \
1141 * If set to 1, then the 64bit flow handle is supported in addition to the
1142 * legacy 16bit flow handle. If set to 0, then the 64bit flow handle is not
1143 * supported. By default, this flag should be 0 for older version of core firmware.
1145 #define HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_FLOW_HANDLE_64BIT_SUPPORTED \
1148 * If set to 1, then filter type can be provided in filter_alloc or filter_cfg
1149 * filter types like L2 for l2 traffic and ROCE for roce & l2 traffic.
1150 * If set to 0, then filter types not supported.
1151 * By default, this flag should be 0 for older version of core firmware.
1153 #define HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_L2_FILTER_TYPES_ROCE_OR_L2_SUPPORTED \
1156 * If set to 1, firmware is capable to support virtio vSwitch offload model.
1157 * If set to 0, firmware can't supported virtio vSwitch offload model.
1158 * By default, this flag should be 0 for older version of core firmware.
1160 #define HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_VIRTIO_VSWITCH_OFFLOAD_SUPPORTED \
1163 * If set to 1, firmware is capable to support trusted VF.
1164 * If set to 0, firmware is not capable to support trusted VF.
1165 * By default, this flag should be 0 for older version of core firmware.
1167 #define HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_TRUSTED_VF_SUPPORTED \
1170 * If set to 1, firmware is capable to support flow aging.
1171 * If set to 0, firmware is not capable to support flow aging.
1172 * By default, this flag should be 0 for older version of core firmware.
1174 #define HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_FLOW_AGING_SUPPORTED \
1177 * If set to 1, firmware is capable to support advanced flow counters like,
1178 * Meter drop counters and EEM counters.
1179 * If set to 0, firmware is not capable to support advanced flow counters.
1180 * By default, this flag should be 0 for older version of core firmware.
1182 #define HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_ADV_FLOW_COUNTERS_SUPPORTED \
1185 * If set to 1, the firmware is able to support the use of the CFA
1186 * Extended Exact Match(EEM) feature.
1187 * If set to 0, firmware is not capable to support the use of the
1189 * By default, this flag should be 0 for older version of core firmware.
1191 #define HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_CFA_EEM_SUPPORTED \
1194 * If set to 1, the firmware is able to support advance CFA flow management
1195 * features reported in the HWRM_CFA_FLOW_MGNT_QCAPS.
1196 * If set to 0, then the firmware doesn’t support the advance CFA flow management
1198 * By default, this flag should be 0 for older version of core firmware.
1200 #define HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_CFA_ADV_FLOW_MGNT_SUPPORTED \
1203 * Deprecated and replaced with cfa_truflow_supported.
1204 * If set to 1, the firmware is able to support TFLIB features.
1205 * If set to 0, then the firmware doesn’t support TFLIB features.
1206 * By default, this flag should be 0 for older version of core firmware.
1208 #define HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_CFA_TFLIB_SUPPORTED \
1211 * If set to 1, the firmware is able to support TruFlow features.
1212 * If set to 0, then the firmware doesn’t support TruFlow features.
1213 * By default, this flag should be 0 for older version of
1216 #define HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_CFA_TRUFLOW_SUPPORTED \
1219 * This field represents the major version of RoCE firmware.
1220 * A change in major version represents a major release.
1222 uint8_t roce_fw_maj_8b;
1224 * This field represents the minor version of RoCE firmware.
1225 * A change in minor version represents significant
1226 * functionality changes.
1228 uint8_t roce_fw_min_8b;
1230 * This field represents the build version of RoCE firmware.
1231 * A change in update version represents bug fixes.
1233 uint8_t roce_fw_bld_8b;
1235 * This field is a reserved field. This field can be used to
1236 * represent firmware branches or customer specific releases
1237 * tied to a specific (major,minor,update) version
1239 uint8_t roce_fw_rsvd_8b;
1241 * This field represents the name of HWRM FW (ASCII chars
1242 * with NULL at the end).
1244 char hwrm_fw_name[16];
1246 * This field represents the name of mgmt FW (ASCII chars
1247 * with NULL at the end).
1249 char mgmt_fw_name[16];
1251 * This field represents the name of network control
1252 * firmware (ASCII chars with NULL at the end).
1254 char netctrl_fw_name[16];
1255 /* This field represents the active board package name. */
1256 char active_pkg_name[16];
1258 * This field represents the name of RoCE FW (ASCII chars
1259 * with NULL at the end).
1261 char roce_fw_name[16];
1262 /* This field returns the chip number. */
1264 /* This field returns the revision of chip. */
1266 /* This field returns the chip metal number. */
1268 /* This field returns the bond id of the chip. */
1269 uint8_t chip_bond_id;
1270 /* This value indicates the type of platform used for chip implementation. */
1271 uint8_t chip_platform_type;
1273 #define HWRM_VER_GET_OUTPUT_CHIP_PLATFORM_TYPE_ASIC UINT32_C(0x0)
1274 /* FPGA platform of the chip. */
1275 #define HWRM_VER_GET_OUTPUT_CHIP_PLATFORM_TYPE_FPGA UINT32_C(0x1)
1276 /* Palladium platform of the chip. */
1277 #define HWRM_VER_GET_OUTPUT_CHIP_PLATFORM_TYPE_PALLADIUM UINT32_C(0x2)
1278 #define HWRM_VER_GET_OUTPUT_CHIP_PLATFORM_TYPE_LAST \
1279 HWRM_VER_GET_OUTPUT_CHIP_PLATFORM_TYPE_PALLADIUM
1281 * This field returns the maximum value of request window that
1282 * is supported by the HWRM. The request window is mapped
1283 * into device address space using MMIO.
1285 uint16_t max_req_win_len;
1287 * This field returns the maximum value of response buffer in
1290 uint16_t max_resp_len;
1292 * This field returns the default request timeout value in
1295 uint16_t def_req_timeout;
1297 * This field will indicate if any subsystems is not fully
1302 * If set to 1, it will indicate to host drivers that firmware is
1303 * not ready to start full blown HWRM commands. Host drivers should
1304 * re-try HWRM_VER_GET with some timeout period. The timeout period
1305 * can be selected up to 5 seconds.
1306 * For Example, PCIe hot-plug:
1307 * Hot plug timing is system dependent. It generally takes up to
1308 * 600 miliseconds for firmware to clear DEV_NOT_RDY flag.
1309 * If set to 0, device is ready to accept all HWRM commands.
1311 #define HWRM_VER_GET_OUTPUT_FLAGS_DEV_NOT_RDY UINT32_C(0x1)
1313 * If set to 1, external version present.
1314 * If set to 0, external version not present.
1316 #define HWRM_VER_GET_OUTPUT_FLAGS_EXT_VER_AVAIL UINT32_C(0x2)
1317 uint8_t unused_0[2];
1319 * For backward compatibility this field must be set to 1.
1320 * Older drivers might look for this field to be 1 before
1321 * processing the message.
1325 * This field represents the major version of HWRM interface
1326 * specification supported by the HWRM implementation.
1327 * The interface major version is intended to change only when
1328 * non backward compatible changes are made to the HWRM
1329 * interface specification. A HWRM implementation that is
1330 * compliant with this specification shall provide value of 1
1333 uint16_t hwrm_intf_major;
1335 * This field represents the minor version of HWRM interface
1336 * specification supported by the HWRM implementation.
1337 * A change in interface minor version is used to reflect
1338 * significant backward compatible modification to HWRM
1339 * interface specification. This can be due to addition or
1340 * removal of functionality. HWRM interface specifications
1341 * with the same major version but different minor versions are
1342 * compatible. A HWRM implementation that is compliant with
1343 * this specification shall provide value of 2 in this field.
1345 uint16_t hwrm_intf_minor;
1347 * This field represents the update version of HWRM interface
1348 * specification supported by the HWRM implementation. The
1349 * interface update version is used to reflect minor changes or
1350 * bug fixes to a released HWRM interface specification.
1351 * A HWRM implementation that is compliant with this
1352 * specification shall provide value of 2 in this field.
1354 uint16_t hwrm_intf_build;
1356 * This field represents the patch version of HWRM interface
1357 * specification supported by the HWRM implementation.
1359 uint16_t hwrm_intf_patch;
1361 * This field represents the major version of HWRM firmware.
1362 * A change in firmware major version represents a major
1365 uint16_t hwrm_fw_major;
1367 * This field represents the minor version of HWRM firmware.
1368 * A change in firmware minor version represents significant
1369 * firmware functionality changes.
1371 uint16_t hwrm_fw_minor;
1373 * This field represents the build version of HWRM firmware.
1374 * A change in firmware build version represents bug fixes to
1375 * a released firmware.
1377 uint16_t hwrm_fw_build;
1379 * This field is a reserved field.
1380 * This field can be used to represent firmware branches or customer
1381 * specific releases tied to a specific (major,minor,update) version
1382 * of the HWRM firmware.
1384 uint16_t hwrm_fw_patch;
1386 * This field represents the major version of mgmt firmware.
1387 * A change in major version represents a major release.
1389 uint16_t mgmt_fw_major;
1391 * This field represents the minor version of HWRM firmware.
1392 * A change in firmware minor version represents significant
1393 * firmware functionality changes.
1395 uint16_t mgmt_fw_minor;
1397 * This field represents the build version of mgmt firmware.
1398 * A change in update version represents bug fixes.
1400 uint16_t mgmt_fw_build;
1402 * This field is a reserved field. This field can be used to
1403 * represent firmware branches or customer specific releases
1404 * tied to a specific (major,minor,update) version.
1406 uint16_t mgmt_fw_patch;
1408 * This field represents the major version of network control
1409 * firmware. A change in major version represents
1412 uint16_t netctrl_fw_major;
1414 * This field represents the minor version of network control
1415 * firmware. A change in minor version represents significant
1416 * functionality changes.
1418 uint16_t netctrl_fw_minor;
1420 * This field represents the build version of network control
1421 * firmware. A change in update version represents bug fixes.
1423 uint16_t netctrl_fw_build;
1425 * This field is a reserved field. This field can be used to
1426 * represent firmware branches or customer specific releases
1427 * tied to a specific (major,minor,update) version
1429 uint16_t netctrl_fw_patch;
1431 * This field represents the major version of RoCE firmware.
1432 * A change in major version represents a major release.
1434 uint16_t roce_fw_major;
1436 * This field represents the minor version of RoCE firmware.
1437 * A change in minor version represents significant
1438 * functionality changes.
1440 uint16_t roce_fw_minor;
1442 * This field represents the build version of RoCE firmware.
1443 * A change in update version represents bug fixes.
1445 uint16_t roce_fw_build;
1447 * This field is a reserved field. This field can be used to
1448 * represent firmware branches or customer specific releases
1449 * tied to a specific (major,minor,update) version
1451 uint16_t roce_fw_patch;
1453 * This field returns the maximum extended request length acceptable
1454 * by the device which allows requests greater than mailbox size when
1455 * used with the short cmd request format.
1457 uint16_t max_ext_req_len;
1458 uint8_t unused_1[5];
1460 * This field is used in Output records to indicate that the output
1461 * is completely written to RAM. This field should be read as '1'
1462 * to indicate that the output has been completely written.
1463 * When writing a command completion or response to an internal processor,
1464 * the order of writes has to be such that this field is written last.
1469 /* bd_base (size:64b/8B) */
1472 /* This value identifies the type of buffer descriptor. */
1473 #define BD_BASE_TYPE_MASK UINT32_C(0x3f)
1474 #define BD_BASE_TYPE_SFT 0
1476 * Indicates that this BD is 16B long and is used for
1477 * normal L2 packet transmission.
1479 #define BD_BASE_TYPE_TX_BD_SHORT UINT32_C(0x0)
1481 * Indicates that this BD is 1BB long and is an empty
1482 * TX BD. Not valid for use by the driver.
1484 #define BD_BASE_TYPE_TX_BD_EMPTY UINT32_C(0x1)
1486 * Indicates that this BD is 16B long and is an RX Producer
1487 * (i.e. empty) buffer descriptor.
1489 #define BD_BASE_TYPE_RX_PROD_PKT UINT32_C(0x4)
1491 * Indicates that this BD is 16B long and is an RX
1492 * Producer Buffer BD.
1494 #define BD_BASE_TYPE_RX_PROD_BFR UINT32_C(0x5)
1496 * Indicates that this BD is 16B long and is an
1497 * RX Producer Assembly Buffer Descriptor.
1499 #define BD_BASE_TYPE_RX_PROD_AGG UINT32_C(0x6)
1501 * Indicates that this BD is 32B long and is used for
1502 * normal L2 packet transmission.
1504 #define BD_BASE_TYPE_TX_BD_LONG UINT32_C(0x10)
1506 * Indicates that this BD is 32B long and is used for
1507 * L2 packet transmission for small packets that require
1510 #define BD_BASE_TYPE_TX_BD_LONG_INLINE UINT32_C(0x11)
1511 #define BD_BASE_TYPE_LAST BD_BASE_TYPE_TX_BD_LONG_INLINE
1512 uint8_t unused_1[7];
1515 /* tx_bd_short (size:128b/16B) */
1516 struct tx_bd_short {
1518 * All bits in this field must be valid on the first BD of a packet.
1519 * Only the packet_end bit must be valid for the remaining BDs
1522 uint16_t flags_type;
1523 /* This value identifies the type of buffer descriptor. */
1524 #define TX_BD_SHORT_TYPE_MASK UINT32_C(0x3f)
1525 #define TX_BD_SHORT_TYPE_SFT 0
1527 * Indicates that this BD is 16B long and is used for
1528 * normal L2 packet transmission.
1530 #define TX_BD_SHORT_TYPE_TX_BD_SHORT UINT32_C(0x0)
1531 #define TX_BD_SHORT_TYPE_LAST TX_BD_SHORT_TYPE_TX_BD_SHORT
1533 * All bits in this field must be valid on the first BD of a packet.
1534 * Only the packet_end bit must be valid for the remaining BDs
1537 #define TX_BD_SHORT_FLAGS_MASK UINT32_C(0xffc0)
1538 #define TX_BD_SHORT_FLAGS_SFT 6
1540 * If set to 1, the packet ends with the data in the buffer
1541 * pointed to by this descriptor. This flag must be
1542 * valid on every BD.
1544 #define TX_BD_SHORT_FLAGS_PACKET_END UINT32_C(0x40)
1546 * If set to 1, the device will not generate a completion for
1547 * this transmit packet unless there is an error in it's
1550 * is set to 0, then the packet will be completed normally.
1552 * This bit must be valid only on the first BD of a packet.
1554 #define TX_BD_SHORT_FLAGS_NO_CMPL UINT32_C(0x80)
1556 * This value indicates how many 16B BD locations are consumed
1557 * in the ring by this packet.
1558 * A value of 1 indicates that this BD is the only BD (and that
1559 * it is a short BD). A value
1560 * of 3 indicates either 3 short BDs or 1 long BD and one short
1561 * BD in the packet. A value of 0 indicates
1562 * that there are 32 BD locations in the packet (the maximum).
1564 * This field is valid only on the first BD of a packet.
1566 #define TX_BD_SHORT_FLAGS_BD_CNT_MASK UINT32_C(0x1f00)
1567 #define TX_BD_SHORT_FLAGS_BD_CNT_SFT 8
1569 * This value is a hint for the length of the entire packet.
1570 * It is used by the chip to optimize internal processing.
1572 * The packet will be dropped if the hint is too short.
1574 * This field is valid only on the first BD of a packet.
1576 #define TX_BD_SHORT_FLAGS_LHINT_MASK UINT32_C(0x6000)
1577 #define TX_BD_SHORT_FLAGS_LHINT_SFT 13
1578 /* indicates packet length < 512B */
1579 #define TX_BD_SHORT_FLAGS_LHINT_LT512 (UINT32_C(0x0) << 13)
1580 /* indicates 512 <= packet length < 1KB */
1581 #define TX_BD_SHORT_FLAGS_LHINT_LT1K (UINT32_C(0x1) << 13)
1582 /* indicates 1KB <= packet length < 2KB */
1583 #define TX_BD_SHORT_FLAGS_LHINT_LT2K (UINT32_C(0x2) << 13)
1584 /* indicates packet length >= 2KB */
1585 #define TX_BD_SHORT_FLAGS_LHINT_GTE2K (UINT32_C(0x3) << 13)
1586 #define TX_BD_SHORT_FLAGS_LHINT_LAST \
1587 TX_BD_SHORT_FLAGS_LHINT_GTE2K
1589 * If set to 1, the device immediately updates the Send Consumer
1590 * Index after the buffer associated with this descriptor has
1591 * been transferred via DMA to NIC memory from host memory. An
1592 * interrupt may or may not be generated according to the state
1593 * of the interrupt avoidance mechanisms. If this bit
1594 * is set to 0, then the Consumer Index is only updated as soon
1595 * as one of the host interrupt coalescing conditions has been met.
1597 * This bit must be valid on the first BD of a packet.
1599 #define TX_BD_SHORT_FLAGS_COAL_NOW UINT32_C(0x8000)
1601 * This is the length of the host physical buffer this BD describes
1604 * This field must be valid on all BDs of a packet.
1608 * The opaque data field is pass through to the completion and can be
1609 * used for any data that the driver wants to associate with the
1612 * This field must be valid on the first BD of a packet.
1616 * This is the host physical address for the portion of the packet
1617 * described by this TX BD.
1619 * This value must be valid on all BDs of a packet.
1624 /* tx_bd_long (size:128b/16B) */
1626 /* This value identifies the type of buffer descriptor. */
1627 uint16_t flags_type;
1629 * This value indicates the type of buffer descriptor.
1632 #define TX_BD_LONG_TYPE_MASK UINT32_C(0x3f)
1633 #define TX_BD_LONG_TYPE_SFT 0
1635 * Indicates that this BD is 32B long and is used for
1636 * normal L2 packet transmission.
1638 #define TX_BD_LONG_TYPE_TX_BD_LONG UINT32_C(0x10)
1639 #define TX_BD_LONG_TYPE_LAST TX_BD_LONG_TYPE_TX_BD_LONG
1641 * All bits in this field must be valid on the first BD of a packet.
1642 * Only the packet_end bit must be valid for the remaining BDs
1645 #define TX_BD_LONG_FLAGS_MASK UINT32_C(0xffc0)
1646 #define TX_BD_LONG_FLAGS_SFT 6
1648 * If set to 1, the packet ends with the data in the buffer
1649 * pointed to by this descriptor. This flag must be
1650 * valid on every BD.
1652 #define TX_BD_LONG_FLAGS_PACKET_END UINT32_C(0x40)
1654 * If set to 1, the device will not generate a completion for
1655 * this transmit packet unless there is an error in it's
1658 * is set to 0, then the packet will be completed normally.
1660 * This bit must be valid only on the first BD of a packet.
1662 #define TX_BD_LONG_FLAGS_NO_CMPL UINT32_C(0x80)
1664 * This value indicates how many 16B BD locations are consumed
1665 * in the ring by this packet.
1666 * A value of 1 indicates that this BD is the only BD (and that
1667 * it is a short BD). A value
1668 * of 3 indicates either 3 short BDs or 1 long BD and one short
1669 * BD in the packet. A value of 0 indicates
1670 * that there are 32 BD locations in the packet (the maximum).
1672 * This field is valid only on the first BD of a packet.
1674 #define TX_BD_LONG_FLAGS_BD_CNT_MASK UINT32_C(0x1f00)
1675 #define TX_BD_LONG_FLAGS_BD_CNT_SFT 8
1677 * This value is a hint for the length of the entire packet.
1678 * It is used by the chip to optimize internal processing.
1680 * The packet will be dropped if the hint is too short.
1682 * This field is valid only on the first BD of a packet.
1684 #define TX_BD_LONG_FLAGS_LHINT_MASK UINT32_C(0x6000)
1685 #define TX_BD_LONG_FLAGS_LHINT_SFT 13
1686 /* indicates packet length < 512B */
1687 #define TX_BD_LONG_FLAGS_LHINT_LT512 (UINT32_C(0x0) << 13)
1688 /* indicates 512 <= packet length < 1KB */
1689 #define TX_BD_LONG_FLAGS_LHINT_LT1K (UINT32_C(0x1) << 13)
1690 /* indicates 1KB <= packet length < 2KB */
1691 #define TX_BD_LONG_FLAGS_LHINT_LT2K (UINT32_C(0x2) << 13)
1692 /* indicates packet length >= 2KB */
1693 #define TX_BD_LONG_FLAGS_LHINT_GTE2K (UINT32_C(0x3) << 13)
1694 #define TX_BD_LONG_FLAGS_LHINT_LAST TX_BD_LONG_FLAGS_LHINT_GTE2K
1696 * If set to 1, the device immediately updates the Send Consumer
1697 * Index after the buffer associated with this descriptor has
1698 * been transferred via DMA to NIC memory from host memory. An
1699 * interrupt may or may not be generated according to the state
1700 * of the interrupt avoidance mechanisms. If this bit
1701 * is set to 0, then the Consumer Index is only updated as soon
1702 * as one of the host interrupt coalescing conditions has been met.
1704 * This bit must be valid on the first BD of a packet.
1706 #define TX_BD_LONG_FLAGS_COAL_NOW UINT32_C(0x8000)
1708 * This is the length of the host physical buffer this BD describes
1711 * This field must be valid on all BDs of a packet.
1715 * The opaque data field is pass through to the completion and can be
1716 * used for any data that the driver wants to associate with the
1719 * This field must be valid on the first BD of a packet.
1723 * This is the host physical address for the portion of the packet
1724 * described by this TX BD.
1726 * This value must be valid on all BDs of a packet.
1731 /* Last 16 bytes of tx_bd_long. */
1732 /* tx_bd_long_hi (size:128b/16B) */
1733 struct tx_bd_long_hi {
1735 * All bits in this field must be valid on the first BD of a packet.
1736 * Their value on other BDs of the packet will be ignored.
1740 * If set to 1, the controller replaces the TCP/UPD checksum
1741 * fields of normal TCP/UPD checksum, or the inner TCP/UDP
1742 * checksum field of the encapsulated TCP/UDP packets with the
1743 * hardware calculated TCP/UDP checksum for the packet associated
1744 * with this descriptor. The flag is ignored if the LSO flag is set.
1746 * This bit must be valid on the first BD of a packet.
1748 #define TX_BD_LONG_LFLAGS_TCP_UDP_CHKSUM UINT32_C(0x1)
1750 * If set to 1, the controller replaces the IP checksum of the
1751 * normal packets, or the inner IP checksum of the encapsulated
1752 * packets with the hardware calculated IP checksum for the
1753 * packet associated with this descriptor.
1755 * This bit must be valid on the first BD of a packet.
1757 #define TX_BD_LONG_LFLAGS_IP_CHKSUM UINT32_C(0x2)
1759 * If set to 1, the controller will not append an Ethernet CRC
1760 * to the end of the frame.
1762 * This bit must be valid on the first BD of a packet.
1764 * Packet must be 64B or longer when this flag is set. It is not
1765 * useful to use this bit with any form of TX offload such as
1766 * CSO or LSO. The intent is that the packet from the host already
1767 * has a valid Ethernet CRC on the packet.
1769 #define TX_BD_LONG_LFLAGS_NOCRC UINT32_C(0x4)
1771 * If set to 1, the device will record the time at which the packet
1772 * was actually transmitted at the TX MAC.
1774 * This bit must be valid on the first BD of a packet.
1776 #define TX_BD_LONG_LFLAGS_STAMP UINT32_C(0x8)
1778 * If set to 1, The controller replaces the tunnel IP checksum
1779 * field with hardware calculated IP checksum for the IP header
1780 * of the packet associated with this descriptor.
1782 * For outer UDP checksum, global outer UDP checksum TE_NIC register
1783 * needs to be enabled. If the global outer UDP checksum TE_NIC register
1784 * bit is set, outer UDP checksum will be calculated for the following
1786 * 1. Packets with tcp_udp_chksum flag set to offload checksum for inner
1787 * packet AND the inner packet is TCP/UDP. If the inner packet is ICMP for
1788 * example (non-TCP/UDP), even if the tcp_udp_chksum is set, the outer UDP
1789 * checksum will not be calculated.
1790 * 2. Packets with lso flag set which implies inner TCP checksum calculation
1791 * as part of LSO operation.
1793 #define TX_BD_LONG_LFLAGS_T_IP_CHKSUM UINT32_C(0x10)
1795 * If set to 1, the device will treat this packet with LSO(Large
1796 * Send Offload) processing for both normal or encapsulated
1797 * packets, which is a form of TCP segmentation. When this bit
1798 * is 1, the hdr_size and mss fields must be valid. The driver
1799 * doesn't need to set t_ip_chksum, ip_chksum, and tcp_udp_chksum
1800 * flags since the controller will replace the appropriate
1801 * checksum fields for segmented packets.
1803 * When this bit is 1, the hdr_size and mss fields must be valid.
1805 #define TX_BD_LONG_LFLAGS_LSO UINT32_C(0x20)
1807 * If set to zero when LSO is '1', then the IPID will be treated
1808 * as a 16b number and will be wrapped if it exceeds a value of
1811 * If set to one when LSO is '1', then the IPID will be treated
1812 * as a 15b number and will be wrapped if it exceeds a value 0f
1815 #define TX_BD_LONG_LFLAGS_IPID_FMT UINT32_C(0x40)
1817 * If set to zero when LSO is '1', then the IPID of the tunnel
1818 * IP header will not be modified during LSO operations.
1820 * If set to one when LSO is '1', then the IPID of the tunnel
1821 * IP header will be incremented for each subsequent segment of an
1824 * The flag is ignored if the LSO packet is a normal (non-tunneled)
1827 #define TX_BD_LONG_LFLAGS_T_IPID UINT32_C(0x80)
1829 * If set to '1', then the RoCE ICRC will be appended to the
1830 * packet. Packet must be a valid RoCE format packet.
1832 #define TX_BD_LONG_LFLAGS_ROCE_CRC UINT32_C(0x100)
1834 * If set to '1', then the FCoE CRC will be appended to the
1835 * packet. Packet must be a valid FCoE format packet.
1837 #define TX_BD_LONG_LFLAGS_FCOE_CRC UINT32_C(0x200)
1840 * When LSO is '1', this field must contain the offset of the
1841 * TCP payload from the beginning of the packet in as
1842 * 16b words. In case of encapsulated/tunneling packet, this field
1843 * contains the offset of the inner TCP payload from beginning of the
1844 * packet as 16-bit words.
1846 * This value must be valid on the first BD of a packet.
1848 #define TX_BD_LONG_HDR_SIZE_MASK UINT32_C(0x1ff)
1849 #define TX_BD_LONG_HDR_SIZE_SFT 0
1852 * This is the MSS value that will be used to do the LSO processing.
1853 * The value is the length in bytes of the TCP payload for each
1854 * segment generated by the LSO operation.
1856 * This value must be valid on the first BD of a packet.
1858 #define TX_BD_LONG_MSS_MASK UINT32_C(0x7fff)
1859 #define TX_BD_LONG_MSS_SFT 0
1862 * This value selects a CFA action to perform on the packet.
1863 * Set this value to zero if no CFA action is desired.
1865 * This value must be valid on the first BD of a packet.
1867 uint16_t cfa_action;
1869 * This value is action meta-data that defines CFA edit operations
1870 * that are done in addition to any action editing.
1873 /* When key=1, This is the VLAN tag VID value. */
1874 #define TX_BD_LONG_CFA_META_VLAN_VID_MASK UINT32_C(0xfff)
1875 #define TX_BD_LONG_CFA_META_VLAN_VID_SFT 0
1876 /* When key=1, This is the VLAN tag DE value. */
1877 #define TX_BD_LONG_CFA_META_VLAN_DE UINT32_C(0x1000)
1878 /* When key=1, This is the VLAN tag PRI value. */
1879 #define TX_BD_LONG_CFA_META_VLAN_PRI_MASK UINT32_C(0xe000)
1880 #define TX_BD_LONG_CFA_META_VLAN_PRI_SFT 13
1881 /* When key=1, This is the VLAN tag TPID select value. */
1882 #define TX_BD_LONG_CFA_META_VLAN_TPID_MASK UINT32_C(0x70000)
1883 #define TX_BD_LONG_CFA_META_VLAN_TPID_SFT 16
1885 #define TX_BD_LONG_CFA_META_VLAN_TPID_TPID88A8 (UINT32_C(0x0) << 16)
1887 #define TX_BD_LONG_CFA_META_VLAN_TPID_TPID8100 (UINT32_C(0x1) << 16)
1889 #define TX_BD_LONG_CFA_META_VLAN_TPID_TPID9100 (UINT32_C(0x2) << 16)
1891 #define TX_BD_LONG_CFA_META_VLAN_TPID_TPID9200 (UINT32_C(0x3) << 16)
1893 #define TX_BD_LONG_CFA_META_VLAN_TPID_TPID9300 (UINT32_C(0x4) << 16)
1894 /* Value programmed in CFA VLANTPID register. */
1895 #define TX_BD_LONG_CFA_META_VLAN_TPID_TPIDCFG (UINT32_C(0x5) << 16)
1896 #define TX_BD_LONG_CFA_META_VLAN_TPID_LAST \
1897 TX_BD_LONG_CFA_META_VLAN_TPID_TPIDCFG
1898 /* When key=1, This is the VLAN tag TPID select value. */
1899 #define TX_BD_LONG_CFA_META_VLAN_RESERVED_MASK UINT32_C(0xff80000)
1900 #define TX_BD_LONG_CFA_META_VLAN_RESERVED_SFT 19
1902 * This field identifies the type of edit to be performed
1905 * This value must be valid on the first BD of a packet.
1907 #define TX_BD_LONG_CFA_META_KEY_MASK UINT32_C(0xf0000000)
1908 #define TX_BD_LONG_CFA_META_KEY_SFT 28
1910 #define TX_BD_LONG_CFA_META_KEY_NONE (UINT32_C(0x0) << 28)
1912 * - meta[17:16] - TPID select value (0 = 0x8100).
1913 * - meta[15:12] - PRI/DE value.
1914 * - meta[11:0] - VID value.
1916 #define TX_BD_LONG_CFA_META_KEY_VLAN_TAG (UINT32_C(0x1) << 28)
1917 #define TX_BD_LONG_CFA_META_KEY_LAST \
1918 TX_BD_LONG_CFA_META_KEY_VLAN_TAG
1922 * This structure is used to inform the NIC of packet data that needs to be
1923 * transmitted with additional processing that requires extra data such as
1924 * VLAN insertion plus attached inline data. This BD type may be used to
1925 * improve latency for small packets needing the additional extended features
1926 * supported by long BDs.
1928 /* tx_bd_long_inline (size:256b/32B) */
1929 struct tx_bd_long_inline {
1930 uint16_t flags_type;
1931 /* This value identifies the type of buffer descriptor. */
1932 #define TX_BD_LONG_INLINE_TYPE_MASK UINT32_C(0x3f)
1933 #define TX_BD_LONG_INLINE_TYPE_SFT 0
1935 * This type of BD is 32B long and is used for inline L2 packet
1938 #define TX_BD_LONG_INLINE_TYPE_TX_BD_LONG_INLINE UINT32_C(0x11)
1939 #define TX_BD_LONG_INLINE_TYPE_LAST \
1940 TX_BD_LONG_INLINE_TYPE_TX_BD_LONG_INLINE
1942 * All bits in this field may be set on the first BD of a packet.
1943 * Only the packet_end bit may be set in non-first BDs.
1945 #define TX_BD_LONG_INLINE_FLAGS_MASK UINT32_C(0xffc0)
1946 #define TX_BD_LONG_INLINE_FLAGS_SFT 6
1948 * If set to 1, the packet ends with the data in the buffer
1949 * pointed to by this descriptor. This flag must be
1950 * valid on every BD.
1952 #define TX_BD_LONG_INLINE_FLAGS_PACKET_END UINT32_C(0x40)
1954 * If set to 1, the device will not generate a completion for
1955 * this transmit packet unless there is an error in its processing.
1956 * If this bit is set to 0, then the packet will be completed
1959 * This bit may be set only on the first BD of a packet.
1961 #define TX_BD_LONG_INLINE_FLAGS_NO_CMPL UINT32_C(0x80)
1963 * This value indicates how many 16B BD locations are consumed
1964 * in the ring by this packet, including the BD and inline
1967 #define TX_BD_LONG_INLINE_FLAGS_BD_CNT_MASK UINT32_C(0x1f00)
1968 #define TX_BD_LONG_INLINE_FLAGS_BD_CNT_SFT 8
1969 /* This field is deprecated. */
1970 #define TX_BD_LONG_INLINE_FLAGS_LHINT_MASK UINT32_C(0x6000)
1971 #define TX_BD_LONG_INLINE_FLAGS_LHINT_SFT 13
1973 * If set to 1, the device immediately updates the Send Consumer
1974 * Index after the buffer associated with this descriptor has
1975 * been transferred via DMA to NIC memory from host memory. An
1976 * interrupt may or may not be generated according to the state
1977 * of the interrupt avoidance mechanisms. If this bit
1978 * is set to 0, then the Consumer Index is only updated as soon
1979 * as one of the host interrupt coalescing conditions has been met.
1981 * This bit must be valid on the first BD of a packet.
1983 #define TX_BD_LONG_INLINE_FLAGS_COAL_NOW UINT32_C(0x8000)
1985 * This is the length of the inline data, not including BD length, in
1987 * The maximum value is 480.
1989 * This field must be valid on all BDs of a packet.
1993 * The opaque data field is passed through to the completion and can be
1994 * used for any data that the driver wants to associate with the transmit
1997 * This field must be valid on the first BD of a packet.
2002 * All bits in this field must be valid on the first BD of a packet.
2003 * Their value on other BDs of the packet is ignored.
2007 * If set to 1, the controller replaces the TCP/UPD checksum
2008 * fields of normal TCP/UPD checksum, or the inner TCP/UDP
2009 * checksum field of the encapsulated TCP/UDP packets with the
2010 * hardware calculated TCP/UDP checksum for the packet associated
2011 * with this descriptor. The flag is ignored if the LSO flag is set.
2013 #define TX_BD_LONG_INLINE_LFLAGS_TCP_UDP_CHKSUM UINT32_C(0x1)
2015 * If set to 1, the controller replaces the IP checksum of the
2016 * normal packets, or the inner IP checksum of the encapsulated
2017 * packets with the hardware calculated IP checksum for the
2018 * packet associated with this descriptor.
2020 #define TX_BD_LONG_INLINE_LFLAGS_IP_CHKSUM UINT32_C(0x2)
2022 * If set to 1, the controller will not append an Ethernet CRC
2023 * to the end of the frame.
2025 * Packet must be 64B or longer when this flag is set. It is not
2026 * useful to use this bit with any form of TX offload such as
2027 * CSO or LSO. The intent is that the packet from the host already
2028 * has a valid Ethernet CRC on the packet.
2030 #define TX_BD_LONG_INLINE_LFLAGS_NOCRC UINT32_C(0x4)
2032 * If set to 1, the device will record the time at which the packet
2033 * was actually transmitted at the TX MAC.
2035 #define TX_BD_LONG_INLINE_LFLAGS_STAMP UINT32_C(0x8)
2037 * If set to 1, the controller replaces the tunnel IP checksum
2038 * field with hardware calculated IP checksum for the IP header
2039 * of the packet associated with this descriptor. The hardware
2040 * updates an outer UDP checksum if it is non-zero.
2042 #define TX_BD_LONG_INLINE_LFLAGS_T_IP_CHKSUM UINT32_C(0x10)
2044 * This bit must be 0 for BDs of this type. LSO is not supported with
2047 #define TX_BD_LONG_INLINE_LFLAGS_LSO UINT32_C(0x20)
2048 /* Since LSO is not supported with inline BDs, this bit is not used. */
2049 #define TX_BD_LONG_INLINE_LFLAGS_IPID_FMT UINT32_C(0x40)
2050 /* Since LSO is not supported with inline BDs, this bit is not used. */
2051 #define TX_BD_LONG_INLINE_LFLAGS_T_IPID UINT32_C(0x80)
2053 * If set to '1', then the RoCE ICRC will be appended to the
2054 * packet. Packet must be a valid RoCE format packet.
2056 #define TX_BD_LONG_INLINE_LFLAGS_ROCE_CRC UINT32_C(0x100)
2058 * If set to '1', then the FCoE CRC will be appended to the
2059 * packet. Packet must be a valid FCoE format packet.
2061 #define TX_BD_LONG_INLINE_LFLAGS_FCOE_CRC UINT32_C(0x200)
2066 * This value selects a CFA action to perform on the packet.
2067 * Set this value to zero if no CFA action is desired.
2069 * This value must be valid on the first BD of a packet.
2071 uint16_t cfa_action;
2073 * This value is action meta-data that defines CFA edit operations
2074 * that are done in addition to any action editing.
2077 /* When key = 1, this is the VLAN tag VID value. */
2078 #define TX_BD_LONG_INLINE_CFA_META_VLAN_VID_MASK UINT32_C(0xfff)
2079 #define TX_BD_LONG_INLINE_CFA_META_VLAN_VID_SFT 0
2080 /* When key = 1, this is the VLAN tag DE value. */
2081 #define TX_BD_LONG_INLINE_CFA_META_VLAN_DE UINT32_C(0x1000)
2082 /* When key = 1, this is the VLAN tag PRI value. */
2083 #define TX_BD_LONG_INLINE_CFA_META_VLAN_PRI_MASK UINT32_C(0xe000)
2084 #define TX_BD_LONG_INLINE_CFA_META_VLAN_PRI_SFT 13
2085 /* When key = 1, this is the VLAN tag TPID select value. */
2086 #define TX_BD_LONG_INLINE_CFA_META_VLAN_TPID_MASK UINT32_C(0x70000)
2087 #define TX_BD_LONG_INLINE_CFA_META_VLAN_TPID_SFT 16
2089 #define TX_BD_LONG_INLINE_CFA_META_VLAN_TPID_TPID88A8 \
2090 (UINT32_C(0x0) << 16)
2092 #define TX_BD_LONG_INLINE_CFA_META_VLAN_TPID_TPID8100 \
2093 (UINT32_C(0x1) << 16)
2095 #define TX_BD_LONG_INLINE_CFA_META_VLAN_TPID_TPID9100 \
2096 (UINT32_C(0x2) << 16)
2098 #define TX_BD_LONG_INLINE_CFA_META_VLAN_TPID_TPID9200 \
2099 (UINT32_C(0x3) << 16)
2101 #define TX_BD_LONG_INLINE_CFA_META_VLAN_TPID_TPID9300 \
2102 (UINT32_C(0x4) << 16)
2103 /* Value programmed in CFA VLANTPID register. */
2104 #define TX_BD_LONG_INLINE_CFA_META_VLAN_TPID_TPIDCFG \
2105 (UINT32_C(0x5) << 16)
2106 #define TX_BD_LONG_INLINE_CFA_META_VLAN_TPID_LAST \
2107 TX_BD_LONG_INLINE_CFA_META_VLAN_TPID_TPIDCFG
2108 #define TX_BD_LONG_INLINE_CFA_META_VLAN_RESERVED_MASK \
2110 #define TX_BD_LONG_INLINE_CFA_META_VLAN_RESERVED_SFT 19
2112 * This field identifies the type of edit to be performed
2115 * This value must be valid on the first BD of a packet.
2117 #define TX_BD_LONG_INLINE_CFA_META_KEY_MASK \
2118 UINT32_C(0xf0000000)
2119 #define TX_BD_LONG_INLINE_CFA_META_KEY_SFT 28
2121 #define TX_BD_LONG_INLINE_CFA_META_KEY_NONE \
2122 (UINT32_C(0x0) << 28)
2124 * - meta[17:16] - TPID select value (0 = 0x8100).
2125 * - meta[15:12] - PRI/DE value.
2126 * - meta[11:0] - VID value.
2128 #define TX_BD_LONG_INLINE_CFA_META_KEY_VLAN_TAG \
2129 (UINT32_C(0x1) << 28)
2130 #define TX_BD_LONG_INLINE_CFA_META_KEY_LAST \
2131 TX_BD_LONG_INLINE_CFA_META_KEY_VLAN_TAG
2134 /* tx_bd_empty (size:128b/16B) */
2135 struct tx_bd_empty {
2136 /* This value identifies the type of buffer descriptor. */
2138 #define TX_BD_EMPTY_TYPE_MASK UINT32_C(0x3f)
2139 #define TX_BD_EMPTY_TYPE_SFT 0
2141 * Indicates that this BD is 1BB long and is an empty
2142 * TX BD. Not valid for use by the driver.
2144 #define TX_BD_EMPTY_TYPE_TX_BD_EMPTY UINT32_C(0x1)
2145 #define TX_BD_EMPTY_TYPE_LAST TX_BD_EMPTY_TYPE_TX_BD_EMPTY
2146 uint8_t unused_1[3];
2148 uint8_t unused_3[3];
2149 uint8_t unused_4[8];
2152 /* rx_prod_pkt_bd (size:128b/16B) */
2153 struct rx_prod_pkt_bd {
2154 /* This value identifies the type of buffer descriptor. */
2155 uint16_t flags_type;
2156 /* This value identifies the type of buffer descriptor. */
2157 #define RX_PROD_PKT_BD_TYPE_MASK UINT32_C(0x3f)
2158 #define RX_PROD_PKT_BD_TYPE_SFT 0
2160 * Indicates that this BD is 16B long and is an RX Producer
2161 * (i.e. empty) buffer descriptor.
2163 #define RX_PROD_PKT_BD_TYPE_RX_PROD_PKT UINT32_C(0x4)
2164 #define RX_PROD_PKT_BD_TYPE_LAST \
2165 RX_PROD_PKT_BD_TYPE_RX_PROD_PKT
2166 #define RX_PROD_PKT_BD_FLAGS_MASK UINT32_C(0xffc0)
2167 #define RX_PROD_PKT_BD_FLAGS_SFT 6
2169 * If set to 1, the packet will be placed at the address plus
2170 * 2B. The 2 Bytes of padding will be written as zero.
2172 #define RX_PROD_PKT_BD_FLAGS_SOP_PAD UINT32_C(0x40)
2174 * If set to 1, the packet write will be padded out to the
2175 * nearest cache-line with zero value padding.
2177 #define RX_PROD_PKT_BD_FLAGS_EOP_PAD UINT32_C(0x80)
2179 * This value is the number of additional buffers in the ring that
2180 * describe the buffer space to be consumed for this packet.
2181 * If the value is zero, then the packet must fit within the
2182 * space described by this BD. If this value is 1 or more, it
2183 * indicates how many additional "buffer" BDs are in the ring
2184 * immediately following this BD to be used for the same
2187 * Even if the packet to be placed does not need all the
2188 * additional buffers, they will be consumed anyway.
2190 #define RX_PROD_PKT_BD_FLAGS_BUFFERS_MASK UINT32_C(0x300)
2191 #define RX_PROD_PKT_BD_FLAGS_BUFFERS_SFT 8
2193 * This is the length in Bytes of the host physical buffer where
2194 * data for the packet may be placed in host memory.
2198 * The opaque data field is pass through to the completion and can be
2199 * used for any data that the driver wants to associate with this
2200 * receive buffer set.
2204 * This is the host physical address where data for the packet may
2205 * be placed in host memory.
2210 /* rx_prod_bfr_bd (size:128b/16B) */
2211 struct rx_prod_bfr_bd {
2212 /* This value identifies the type of buffer descriptor. */
2213 uint16_t flags_type;
2214 /* This value identifies the type of buffer descriptor. */
2215 #define RX_PROD_BFR_BD_TYPE_MASK UINT32_C(0x3f)
2216 #define RX_PROD_BFR_BD_TYPE_SFT 0
2218 * Indicates that this BD is 16B long and is an RX
2219 * Producer Buffer BD.
2221 #define RX_PROD_BFR_BD_TYPE_RX_PROD_BFR UINT32_C(0x5)
2222 #define RX_PROD_BFR_BD_TYPE_LAST RX_PROD_BFR_BD_TYPE_RX_PROD_BFR
2223 #define RX_PROD_BFR_BD_FLAGS_MASK UINT32_C(0xffc0)
2224 #define RX_PROD_BFR_BD_FLAGS_SFT 6
2226 * This is the length in Bytes of the host physical buffer where
2227 * data for the packet may be placed in host memory.
2230 /* This field is not used. */
2233 * This is the host physical address where data for the packet may
2234 * be placed in host memory.
2239 /* rx_prod_agg_bd (size:128b/16B) */
2240 struct rx_prod_agg_bd {
2241 /* This value identifies the type of buffer descriptor. */
2242 uint16_t flags_type;
2243 /* This value identifies the type of buffer descriptor. */
2244 #define RX_PROD_AGG_BD_TYPE_MASK UINT32_C(0x3f)
2245 #define RX_PROD_AGG_BD_TYPE_SFT 0
2247 * Indicates that this BD is 16B long and is an
2248 * RX Producer Assembly Buffer Descriptor.
2250 #define RX_PROD_AGG_BD_TYPE_RX_PROD_AGG UINT32_C(0x6)
2251 #define RX_PROD_AGG_BD_TYPE_LAST \
2252 RX_PROD_AGG_BD_TYPE_RX_PROD_AGG
2253 #define RX_PROD_AGG_BD_FLAGS_MASK UINT32_C(0xffc0)
2254 #define RX_PROD_AGG_BD_FLAGS_SFT 6
2256 * If set to 1, the packet write will be padded out to the
2257 * nearest cache-line with zero value padding.
2259 #define RX_PROD_AGG_BD_FLAGS_EOP_PAD UINT32_C(0x40)
2261 * This is the length in Bytes of the host physical buffer where
2262 * data for the packet may be placed in host memory.
2266 * The opaque data field is pass through to the completion and can be
2267 * used for any data that the driver wants to associate with this
2268 * receive assembly buffer.
2272 * This is the host physical address where data for the packet may
2273 * be placed in host memory.
2278 /* cmpl_base (size:128b/16B) */
2282 * This field indicates the exact type of the completion.
2283 * By convention, the LSB identifies the length of the
2284 * record in 16B units. Even values indicate 16B
2285 * records. Odd values indicate 32B
2288 #define CMPL_BASE_TYPE_MASK UINT32_C(0x3f)
2289 #define CMPL_BASE_TYPE_SFT 0
2292 * Completion of TX packet. Length = 16B
2294 #define CMPL_BASE_TYPE_TX_L2 UINT32_C(0x0)
2297 * Completion of and L2 RX packet. Length = 32B
2299 #define CMPL_BASE_TYPE_RX_L2 UINT32_C(0x11)
2301 * RX Aggregation Buffer completion :
2302 * Completion of an L2 aggregation buffer in support of
2303 * TPA, HDS, or Jumbo packet completion. Length = 16B
2305 #define CMPL_BASE_TYPE_RX_AGG UINT32_C(0x12)
2307 * RX L2 TPA Start Completion:
2308 * Completion at the beginning of a TPA operation.
2311 #define CMPL_BASE_TYPE_RX_TPA_START UINT32_C(0x13)
2313 * RX L2 TPA End Completion:
2314 * Completion at the end of a TPA operation.
2317 #define CMPL_BASE_TYPE_RX_TPA_END UINT32_C(0x15)
2319 * Statistics Ejection Completion:
2320 * Completion of statistics data ejection buffer.
2323 #define CMPL_BASE_TYPE_STAT_EJECT UINT32_C(0x1a)
2325 * HWRM Command Completion:
2326 * Completion of an HWRM command.
2328 #define CMPL_BASE_TYPE_HWRM_DONE UINT32_C(0x20)
2329 /* Forwarded HWRM Request */
2330 #define CMPL_BASE_TYPE_HWRM_FWD_REQ UINT32_C(0x22)
2331 /* Forwarded HWRM Response */
2332 #define CMPL_BASE_TYPE_HWRM_FWD_RESP UINT32_C(0x24)
2333 /* HWRM Asynchronous Event Information */
2334 #define CMPL_BASE_TYPE_HWRM_ASYNC_EVENT UINT32_C(0x2e)
2335 /* CQ Notification */
2336 #define CMPL_BASE_TYPE_CQ_NOTIFICATION UINT32_C(0x30)
2337 /* SRQ Threshold Event */
2338 #define CMPL_BASE_TYPE_SRQ_EVENT UINT32_C(0x32)
2339 /* DBQ Threshold Event */
2340 #define CMPL_BASE_TYPE_DBQ_EVENT UINT32_C(0x34)
2341 /* QP Async Notification */
2342 #define CMPL_BASE_TYPE_QP_EVENT UINT32_C(0x38)
2343 /* Function Async Notification */
2344 #define CMPL_BASE_TYPE_FUNC_EVENT UINT32_C(0x3a)
2345 #define CMPL_BASE_TYPE_LAST CMPL_BASE_TYPE_FUNC_EVENT
2351 * This value is written by the NIC such that it will be different
2352 * for each pass through the completion queue. The even passes
2353 * will write 1. The odd passes will write 0.
2356 #define CMPL_BASE_V UINT32_C(0x1)
2357 #define CMPL_BASE_INFO3_MASK UINT32_C(0xfffffffe)
2358 #define CMPL_BASE_INFO3_SFT 1
2363 /* tx_cmpl (size:128b/16B) */
2365 uint16_t flags_type;
2367 * This field indicates the exact type of the completion.
2368 * By convention, the LSB identifies the length of the
2369 * record in 16B units. Even values indicate 16B
2370 * records. Odd values indicate 32B
2373 #define TX_CMPL_TYPE_MASK UINT32_C(0x3f)
2374 #define TX_CMPL_TYPE_SFT 0
2377 * Completion of TX packet. Length = 16B
2379 #define TX_CMPL_TYPE_TX_L2 UINT32_C(0x0)
2380 #define TX_CMPL_TYPE_LAST TX_CMPL_TYPE_TX_L2
2381 #define TX_CMPL_FLAGS_MASK UINT32_C(0xffc0)
2382 #define TX_CMPL_FLAGS_SFT 6
2384 * When this bit is '1', it indicates a packet that has an
2385 * error of some type. Type of error is indicated in
2388 #define TX_CMPL_FLAGS_ERROR UINT32_C(0x40)
2390 * When this bit is '1', it indicates that the packet completed
2391 * was transmitted using the push acceleration data provided
2392 * by the driver. When this bit is '0', it indicates that the
2393 * packet had not push acceleration data written or was executed
2394 * as a normal packet even though push data was provided.
2396 #define TX_CMPL_FLAGS_PUSH UINT32_C(0x80)
2397 /* unused1 is 16 b */
2400 * This is a copy of the opaque field from the first TX BD of this
2401 * transmitted packet.
2406 * This value is written by the NIC such that it will be different
2407 * for each pass through the completion queue. The even passes
2408 * will write 1. The odd passes will write 0.
2410 #define TX_CMPL_V UINT32_C(0x1)
2411 #define TX_CMPL_ERRORS_MASK UINT32_C(0xfffe)
2412 #define TX_CMPL_ERRORS_SFT 1
2414 * This error indicates that there was some sort of problem
2415 * with the BDs for the packet.
2417 #define TX_CMPL_ERRORS_BUFFER_ERROR_MASK UINT32_C(0xe)
2418 #define TX_CMPL_ERRORS_BUFFER_ERROR_SFT 1
2420 #define TX_CMPL_ERRORS_BUFFER_ERROR_NO_ERROR (UINT32_C(0x0) << 1)
2423 * BDs were not formatted correctly.
2425 #define TX_CMPL_ERRORS_BUFFER_ERROR_BAD_FMT (UINT32_C(0x2) << 1)
2426 #define TX_CMPL_ERRORS_BUFFER_ERROR_LAST \
2427 TX_CMPL_ERRORS_BUFFER_ERROR_BAD_FMT
2429 * When this bit is '1', it indicates that the length of
2430 * the packet was zero. No packet was transmitted.
2432 #define TX_CMPL_ERRORS_ZERO_LENGTH_PKT UINT32_C(0x10)
2434 * When this bit is '1', it indicates that the packet
2435 * was longer than the programmed limit in TDI. No
2436 * packet was transmitted.
2438 #define TX_CMPL_ERRORS_EXCESSIVE_BD_LENGTH UINT32_C(0x20)
2440 * When this bit is '1', it indicates that one or more of the
2441 * BDs associated with this packet generated a PCI error.
2442 * This probably means the address was not valid.
2444 #define TX_CMPL_ERRORS_DMA_ERROR UINT32_C(0x40)
2446 * When this bit is '1', it indicates that the packet was longer
2447 * than indicated by the hint. No packet was transmitted.
2449 #define TX_CMPL_ERRORS_HINT_TOO_SHORT UINT32_C(0x80)
2451 * When this bit is '1', it indicates that the packet was
2452 * dropped due to Poison TLP error on one or more of the
2453 * TLPs in the PXP completion.
2455 #define TX_CMPL_ERRORS_POISON_TLP_ERROR UINT32_C(0x100)
2456 /* unused2 is 16 b */
2458 /* unused3 is 32 b */
2462 /* rx_pkt_cmpl (size:128b/16B) */
2463 struct rx_pkt_cmpl {
2464 uint16_t flags_type;
2466 * This field indicates the exact type of the completion.
2467 * By convention, the LSB identifies the length of the
2468 * record in 16B units. Even values indicate 16B
2469 * records. Odd values indicate 32B
2472 #define RX_PKT_CMPL_TYPE_MASK UINT32_C(0x3f)
2473 #define RX_PKT_CMPL_TYPE_SFT 0
2476 * Completion of and L2 RX packet. Length = 32B
2478 #define RX_PKT_CMPL_TYPE_RX_L2 UINT32_C(0x11)
2479 #define RX_PKT_CMPL_TYPE_LAST RX_PKT_CMPL_TYPE_RX_L2
2480 #define RX_PKT_CMPL_FLAGS_MASK UINT32_C(0xffc0)
2481 #define RX_PKT_CMPL_FLAGS_SFT 6
2483 * When this bit is '1', it indicates a packet that has an
2484 * error of some type. Type of error is indicated in
2487 #define RX_PKT_CMPL_FLAGS_ERROR UINT32_C(0x40)
2488 /* This field indicates how the packet was placed in the buffer. */
2489 #define RX_PKT_CMPL_FLAGS_PLACEMENT_MASK UINT32_C(0x380)
2490 #define RX_PKT_CMPL_FLAGS_PLACEMENT_SFT 7
2493 * Packet was placed using normal algorithm.
2495 #define RX_PKT_CMPL_FLAGS_PLACEMENT_NORMAL (UINT32_C(0x0) << 7)
2498 * Packet was placed using jumbo algorithm.
2500 #define RX_PKT_CMPL_FLAGS_PLACEMENT_JUMBO (UINT32_C(0x1) << 7)
2502 * Header/Data Separation:
2503 * Packet was placed using Header/Data separation algorithm.
2504 * The separation location is indicated by the itype field.
2506 #define RX_PKT_CMPL_FLAGS_PLACEMENT_HDS (UINT32_C(0x2) << 7)
2507 #define RX_PKT_CMPL_FLAGS_PLACEMENT_LAST \
2508 RX_PKT_CMPL_FLAGS_PLACEMENT_HDS
2509 /* This bit is '1' if the RSS field in this completion is valid. */
2510 #define RX_PKT_CMPL_FLAGS_RSS_VALID UINT32_C(0x400)
2512 #define RX_PKT_CMPL_FLAGS_UNUSED UINT32_C(0x800)
2514 * This value indicates what the inner packet determined for the
2517 #define RX_PKT_CMPL_FLAGS_ITYPE_MASK UINT32_C(0xf000)
2518 #define RX_PKT_CMPL_FLAGS_ITYPE_SFT 12
2521 * Indicates that the packet type was not known.
2523 #define RX_PKT_CMPL_FLAGS_ITYPE_NOT_KNOWN \
2524 (UINT32_C(0x0) << 12)
2527 * Indicates that the packet was an IP packet, but further
2528 * classification was not possible.
2530 #define RX_PKT_CMPL_FLAGS_ITYPE_IP \
2531 (UINT32_C(0x1) << 12)
2534 * Indicates that the packet was IP and TCP.
2535 * This indicates that the payload_offset field is valid.
2537 #define RX_PKT_CMPL_FLAGS_ITYPE_TCP \
2538 (UINT32_C(0x2) << 12)
2541 * Indicates that the packet was IP and UDP.
2542 * This indicates that the payload_offset field is valid.
2544 #define RX_PKT_CMPL_FLAGS_ITYPE_UDP \
2545 (UINT32_C(0x3) << 12)
2548 * Indicates that the packet was recognized as a FCoE.
2549 * This also indicates that the payload_offset field is valid.
2551 #define RX_PKT_CMPL_FLAGS_ITYPE_FCOE \
2552 (UINT32_C(0x4) << 12)
2555 * Indicates that the packet was recognized as a RoCE.
2556 * This also indicates that the payload_offset field is valid.
2558 #define RX_PKT_CMPL_FLAGS_ITYPE_ROCE \
2559 (UINT32_C(0x5) << 12)
2562 * Indicates that the packet was recognized as ICMP.
2563 * This indicates that the payload_offset field is valid.
2565 #define RX_PKT_CMPL_FLAGS_ITYPE_ICMP \
2566 (UINT32_C(0x7) << 12)
2568 * PtP packet wo/timestamp:
2569 * Indicates that the packet was recognized as a PtP
2572 #define RX_PKT_CMPL_FLAGS_ITYPE_PTP_WO_TIMESTAMP \
2573 (UINT32_C(0x8) << 12)
2575 * PtP packet w/timestamp:
2576 * Indicates that the packet was recognized as a PtP
2577 * packet and that a timestamp was taken for the packet.
2579 #define RX_PKT_CMPL_FLAGS_ITYPE_PTP_W_TIMESTAMP \
2580 (UINT32_C(0x9) << 12)
2581 #define RX_PKT_CMPL_FLAGS_ITYPE_LAST \
2582 RX_PKT_CMPL_FLAGS_ITYPE_PTP_W_TIMESTAMP
2584 * This is the length of the data for the packet stored in the
2585 * buffer(s) identified by the opaque value. This includes
2586 * the packet BD and any associated buffer BDs. This does not include
2587 * the length of any data places in aggregation BDs.
2591 * This is a copy of the opaque field from the RX BD this completion
2595 uint8_t agg_bufs_v1;
2597 * This value is written by the NIC such that it will be different
2598 * for each pass through the completion queue. The even passes
2599 * will write 1. The odd passes will write 0.
2601 #define RX_PKT_CMPL_V1 UINT32_C(0x1)
2603 * This value is the number of aggregation buffers that follow this
2604 * entry in the completion ring that are a part of this packet.
2605 * If the value is zero, then the packet is completely contained
2606 * in the buffer space provided for the packet in the RX ring.
2608 #define RX_PKT_CMPL_AGG_BUFS_MASK UINT32_C(0x3e)
2609 #define RX_PKT_CMPL_AGG_BUFS_SFT 1
2610 /* unused1 is 2 b */
2611 #define RX_PKT_CMPL_UNUSED1_MASK UINT32_C(0xc0)
2612 #define RX_PKT_CMPL_UNUSED1_SFT 6
2614 * This is the RSS hash type for the packet. The value is packed
2615 * {tuple_extrac_op[1:0],rss_profile_id[4:0],tuple_extrac_op[2]}.
2617 * The value of tuple_extrac_op provides the information about
2618 * what fields the hash was computed on.
2619 * * 0: The RSS hash was computed over source IP address,
2620 * destination IP address, source port, and destination port of inner
2621 * IP and TCP or UDP headers. Note: For non-tunneled packets,
2622 * the packet headers are considered inner packet headers for the RSS
2623 * hash computation purpose.
2624 * * 1: The RSS hash was computed over source IP address and destination
2625 * IP address of inner IP header. Note: For non-tunneled packets,
2626 * the packet headers are considered inner packet headers for the RSS
2627 * hash computation purpose.
2628 * * 2: The RSS hash was computed over source IP address,
2629 * destination IP address, source port, and destination port of
2630 * IP and TCP or UDP headers of outer tunnel headers.
2631 * Note: For non-tunneled packets, this value is not applicable.
2632 * * 3: The RSS hash was computed over source IP address and
2633 * destination IP address of IP header of outer tunnel headers.
2634 * Note: For non-tunneled packets, this value is not applicable.
2636 * Note that 4-tuples values listed above are applicable
2637 * for layer 4 protocols supported and enabled for RSS in the hardware,
2638 * HWRM firmware, and drivers. For example, if RSS hash is supported and
2639 * enabled for TCP traffic only, then the values of tuple_extract_op
2640 * corresponding to 4-tuples are only valid for TCP traffic.
2642 uint8_t rss_hash_type;
2644 * This value indicates the offset in bytes from the beginning of the packet
2645 * where the inner payload starts. This value is valid for TCP, UDP,
2646 * FCoE, and RoCE packets.
2648 * A value of zero indicates that header is 256B into the packet.
2650 uint8_t payload_offset;
2651 /* unused2 is 8 b */
2654 * This value is the RSS hash value calculated for the packet
2655 * based on the mode bits and key value in the VNIC.
2660 /* Last 16 bytes of rx_pkt_cmpl. */
2661 /* rx_pkt_cmpl_hi (size:128b/16B) */
2662 struct rx_pkt_cmpl_hi {
2665 * This indicates that the ip checksum was calculated for the
2666 * inner packet and that the ip_cs_error field indicates if there
2669 #define RX_PKT_CMPL_FLAGS2_IP_CS_CALC UINT32_C(0x1)
2671 * This indicates that the TCP, UDP or ICMP checksum was
2672 * calculated for the inner packet and that the l4_cs_error field
2673 * indicates if there was an error.
2675 #define RX_PKT_CMPL_FLAGS2_L4_CS_CALC UINT32_C(0x2)
2677 * This indicates that the ip checksum was calculated for the
2678 * tunnel header and that the t_ip_cs_error field indicates if there
2681 #define RX_PKT_CMPL_FLAGS2_T_IP_CS_CALC UINT32_C(0x4)
2683 * This indicates that the UDP checksum was
2684 * calculated for the tunnel packet and that the t_l4_cs_error field
2685 * indicates if there was an error.
2687 #define RX_PKT_CMPL_FLAGS2_T_L4_CS_CALC UINT32_C(0x8)
2688 /* This value indicates what format the metadata field is. */
2689 #define RX_PKT_CMPL_FLAGS2_META_FORMAT_MASK UINT32_C(0xf0)
2690 #define RX_PKT_CMPL_FLAGS2_META_FORMAT_SFT 4
2691 /* No metadata information. Value is zero. */
2692 #define RX_PKT_CMPL_FLAGS2_META_FORMAT_NONE \
2693 (UINT32_C(0x0) << 4)
2695 * The metadata field contains the VLAN tag and TPID value.
2696 * - metadata[11:0] contains the vlan VID value.
2697 * - metadata[12] contains the vlan DE value.
2698 * - metadata[15:13] contains the vlan PRI value.
2699 * - metadata[31:16] contains the vlan TPID value.
2701 #define RX_PKT_CMPL_FLAGS2_META_FORMAT_VLAN \
2702 (UINT32_C(0x1) << 4)
2704 * If ext_meta_format is equal to 1, the metadata field
2705 * contains the lower 16b of the tunnel ID value, justified
2707 * - VXLAN = VNI[23:0] -> VXLAN Network ID
2708 * - Geneve (NGE) = VNI[23:0] a-> Virtual Network Identifier.
2709 * - NVGRE = TNI[23:0] -> Tenant Network ID
2710 * - GRE = KEY[31:0] -> key field with bit mask. zero if K = 0
2711 * - IPV4 = 0 (not populated)
2712 * - IPV6 = Flow Label[19:0]
2713 * - PPPoE = sessionID[15:0]
2714 * - MPLs = Outer label[19:0]
2715 * - UPAR = Selected[31:0] with bit mask
2717 #define RX_PKT_CMPL_FLAGS2_META_FORMAT_TUNNEL_ID \
2718 (UINT32_C(0x2) << 4)
2720 * if ext_meta_format is equal to 1, metadata field contains
2721 * 16b metadata from the prepended header (chdr_data).
2723 #define RX_PKT_CMPL_FLAGS2_META_FORMAT_CHDR_DATA \
2724 (UINT32_C(0x3) << 4)
2726 * If ext_meta_format is equal to 1, the metadata field contains
2727 * the outer_l3_offset, inner_l2_offset, inner_l3_offset and
2729 * - metadata[8:0] contains the outer_l3_offset.
2730 * - metadata[17:9] contains the inner_l2_offset.
2731 * - metadata[26:18] contains the inner_l3_offset.
2732 * - metadata[31:27] contains the inner_l4_size.
2734 #define RX_PKT_CMPL_FLAGS2_META_FORMAT_HDR_OFFSET \
2735 (UINT32_C(0x4) << 4)
2736 #define RX_PKT_CMPL_FLAGS2_META_FORMAT_LAST \
2737 RX_PKT_CMPL_FLAGS2_META_FORMAT_HDR_OFFSET
2739 * This field indicates the IP type for the inner-most IP header.
2740 * A value of '0' indicates IPv4. A value of '1' indicates IPv6.
2741 * This value is only valid if itype indicates a packet
2742 * with an IP header.
2744 #define RX_PKT_CMPL_FLAGS2_IP_TYPE UINT32_C(0x100)
2746 * This indicates that the complete 1's complement checksum was
2747 * calculated for the packet.
2749 #define RX_PKT_CMPL_FLAGS2_COMPLETE_CHECKSUM_CALC UINT32_C(0x200)
2751 * The combination of this value and meta_format indicated what
2752 * format the metadata field is.
2754 #define RX_PKT_CMPL_FLAGS2_EXT_META_FORMAT_MASK UINT32_C(0xc00)
2755 #define RX_PKT_CMPL_FLAGS2_EXT_META_FORMAT_SFT 10
2757 * This value is the complete 1's complement checksum calculated from
2758 * the start of the outer L3 header to the end of the packet (not
2759 * including the ethernet crc). It is valid when the
2760 * 'complete_checksum_calc' flag is set.
2762 #define RX_PKT_CMPL_FLAGS2_COMPLETE_CHECKSUM_MASK \
2763 UINT32_C(0xffff0000)
2764 #define RX_PKT_CMPL_FLAGS2_COMPLETE_CHECKSUM_SFT 16
2766 * This is data from the CFA block as indicated by the meta_format
2770 /* When meta_format=1, this value is the VLAN VID. */
2771 #define RX_PKT_CMPL_METADATA_VID_MASK UINT32_C(0xfff)
2772 #define RX_PKT_CMPL_METADATA_VID_SFT 0
2773 /* When meta_format=1, this value is the VLAN DE. */
2774 #define RX_PKT_CMPL_METADATA_DE UINT32_C(0x1000)
2775 /* When meta_format=1, this value is the VLAN PRI. */
2776 #define RX_PKT_CMPL_METADATA_PRI_MASK UINT32_C(0xe000)
2777 #define RX_PKT_CMPL_METADATA_PRI_SFT 13
2778 /* When meta_format=1, this value is the VLAN TPID. */
2779 #define RX_PKT_CMPL_METADATA_TPID_MASK UINT32_C(0xffff0000)
2780 #define RX_PKT_CMPL_METADATA_TPID_SFT 16
2783 * This value is written by the NIC such that it will be different
2784 * for each pass through the completion queue. The even passes
2785 * will write 1. The odd passes will write 0.
2787 #define RX_PKT_CMPL_V2 \
2789 #define RX_PKT_CMPL_ERRORS_MASK \
2791 #define RX_PKT_CMPL_ERRORS_SFT 1
2793 * This error indicates that there was some sort of problem with
2794 * the BDs for the packet that was found after part of the
2795 * packet was already placed. The packet should be treated as
2798 #define RX_PKT_CMPL_ERRORS_BUFFER_ERROR_MASK \
2800 #define RX_PKT_CMPL_ERRORS_BUFFER_ERROR_SFT 1
2801 /* No buffer error */
2802 #define RX_PKT_CMPL_ERRORS_BUFFER_ERROR_NO_BUFFER \
2803 (UINT32_C(0x0) << 1)
2806 * Packet did not fit into packet buffer provided.
2807 * For regular placement, this means the packet did not fit
2808 * in the buffer provided. For HDS and jumbo placement, this
2809 * means that the packet could not be placed into 7 physical
2812 #define RX_PKT_CMPL_ERRORS_BUFFER_ERROR_DID_NOT_FIT \
2813 (UINT32_C(0x1) << 1)
2816 * All BDs needed for the packet were not on-chip when
2817 * the packet arrived.
2819 #define RX_PKT_CMPL_ERRORS_BUFFER_ERROR_NOT_ON_CHIP \
2820 (UINT32_C(0x2) << 1)
2823 * BDs were not formatted correctly.
2825 #define RX_PKT_CMPL_ERRORS_BUFFER_ERROR_BAD_FORMAT \
2826 (UINT32_C(0x3) << 1)
2829 * There was a bad_format error on the previous operation
2831 #define RX_PKT_CMPL_ERRORS_BUFFER_ERROR_FLUSH \
2832 (UINT32_C(0x5) << 1)
2833 #define RX_PKT_CMPL_ERRORS_BUFFER_ERROR_LAST \
2834 RX_PKT_CMPL_ERRORS_BUFFER_ERROR_FLUSH
2836 * This indicates that there was an error in the IP header
2839 #define RX_PKT_CMPL_ERRORS_IP_CS_ERROR \
2842 * This indicates that there was an error in the TCP, UDP
2845 #define RX_PKT_CMPL_ERRORS_L4_CS_ERROR \
2848 * This indicates that there was an error in the tunnel
2849 * IP header checksum.
2851 #define RX_PKT_CMPL_ERRORS_T_IP_CS_ERROR \
2854 * This indicates that there was an error in the tunnel
2857 #define RX_PKT_CMPL_ERRORS_T_L4_CS_ERROR \
2860 * This indicates that there was a CRC error on either an FCoE
2861 * or RoCE packet. The itype indicates the packet type.
2863 #define RX_PKT_CMPL_ERRORS_CRC_ERROR \
2866 * This indicates that there was an error in the tunnel
2867 * portion of the packet when this
2868 * field is non-zero.
2870 #define RX_PKT_CMPL_ERRORS_T_PKT_ERROR_MASK \
2872 #define RX_PKT_CMPL_ERRORS_T_PKT_ERROR_SFT 9
2874 * No additional error occurred on the tunnel portion
2875 * or the packet of the packet does not have a tunnel.
2877 #define RX_PKT_CMPL_ERRORS_T_PKT_ERROR_NO_ERROR \
2878 (UINT32_C(0x0) << 9)
2880 * Indicates that IP header version does not match
2881 * expectation from L2 Ethertype for IPv4 and IPv6
2882 * in the tunnel header.
2884 #define RX_PKT_CMPL_ERRORS_T_PKT_ERROR_T_L3_BAD_VERSION \
2885 (UINT32_C(0x1) << 9)
2887 * Indicates that header length is out of range in the
2888 * tunnel header. Valid for
2891 #define RX_PKT_CMPL_ERRORS_T_PKT_ERROR_T_L3_BAD_HDR_LEN \
2892 (UINT32_C(0x2) << 9)
2894 * Indicates that the physical packet is shorter than that
2895 * claimed by the PPPoE header length for a tunnel PPPoE
2898 #define RX_PKT_CMPL_ERRORS_T_PKT_ERROR_TUNNEL_TOTAL_ERROR \
2899 (UINT32_C(0x3) << 9)
2901 * Indicates that physical packet is shorter than that claimed
2902 * by the tunnel l3 header length. Valid for IPv4, or IPv6
2903 * tunnel packet packets.
2905 #define RX_PKT_CMPL_ERRORS_T_PKT_ERROR_T_IP_TOTAL_ERROR \
2906 (UINT32_C(0x4) << 9)
2908 * Indicates that the physical packet is shorter than that
2909 * claimed by the tunnel UDP header length for a tunnel
2910 * UDP packet that is not fragmented.
2912 #define RX_PKT_CMPL_ERRORS_T_PKT_ERROR_T_UDP_TOTAL_ERROR \
2913 (UINT32_C(0x5) << 9)
2915 * indicates that the IPv4 TTL or IPv6 hop limit check
2916 * have failed (e.g. TTL = 0) in the tunnel header. Valid
2917 * for IPv4, and IPv6.
2919 #define RX_PKT_CMPL_ERRORS_T_PKT_ERROR_T_L3_BAD_TTL \
2920 (UINT32_C(0x6) << 9)
2921 #define RX_PKT_CMPL_ERRORS_T_PKT_ERROR_LAST \
2922 RX_PKT_CMPL_ERRORS_T_PKT_ERROR_T_L3_BAD_TTL
2924 * This indicates that there was an error in the inner
2925 * portion of the packet when this
2926 * field is non-zero.
2928 #define RX_PKT_CMPL_ERRORS_PKT_ERROR_MASK \
2930 #define RX_PKT_CMPL_ERRORS_PKT_ERROR_SFT 12
2932 * No additional error occurred on the tunnel portion
2933 * or the packet of the packet does not have a tunnel.
2935 #define RX_PKT_CMPL_ERRORS_PKT_ERROR_NO_ERROR \
2936 (UINT32_C(0x0) << 12)
2938 * Indicates that IP header version does not match
2939 * expectation from L2 Ethertype for IPv4 and IPv6 or that
2940 * option other than VFT was parsed on
2943 #define RX_PKT_CMPL_ERRORS_PKT_ERROR_L3_BAD_VERSION \
2944 (UINT32_C(0x1) << 12)
2946 * indicates that header length is out of range. Valid for
2949 #define RX_PKT_CMPL_ERRORS_PKT_ERROR_L3_BAD_HDR_LEN \
2950 (UINT32_C(0x2) << 12)
2952 * indicates that the IPv4 TTL or IPv6 hop limit check
2953 * have failed (e.g. TTL = 0). Valid for IPv4, and IPv6
2955 #define RX_PKT_CMPL_ERRORS_PKT_ERROR_L3_BAD_TTL \
2956 (UINT32_C(0x3) << 12)
2958 * Indicates that physical packet is shorter than that
2959 * claimed by the l3 header length. Valid for IPv4,
2960 * IPv6 packet or RoCE packets.
2962 #define RX_PKT_CMPL_ERRORS_PKT_ERROR_IP_TOTAL_ERROR \
2963 (UINT32_C(0x4) << 12)
2965 * Indicates that the physical packet is shorter than that
2966 * claimed by the UDP header length for a UDP packet that is
2969 #define RX_PKT_CMPL_ERRORS_PKT_ERROR_UDP_TOTAL_ERROR \
2970 (UINT32_C(0x5) << 12)
2972 * Indicates that TCP header length > IP payload. Valid for
2975 #define RX_PKT_CMPL_ERRORS_PKT_ERROR_L4_BAD_HDR_LEN \
2976 (UINT32_C(0x6) << 12)
2977 /* Indicates that TCP header length < 5. Valid for TCP. */
2978 #define RX_PKT_CMPL_ERRORS_PKT_ERROR_L4_BAD_HDR_LEN_TOO_SMALL \
2979 (UINT32_C(0x7) << 12)
2981 * Indicates that TCP option headers result in a TCP header
2982 * size that does not match data offset in TCP header. Valid
2985 #define RX_PKT_CMPL_ERRORS_PKT_ERROR_L4_BAD_OPT_LEN \
2986 (UINT32_C(0x8) << 12)
2987 #define RX_PKT_CMPL_ERRORS_PKT_ERROR_LAST \
2988 RX_PKT_CMPL_ERRORS_PKT_ERROR_L4_BAD_OPT_LEN
2990 * This field identifies the CFA action rule that was used for this
2996 * This value holds the reordering sequence number for the packet.
2997 * If the reordering sequence is not valid, then this value is zero.
2998 * The reordering domain for the packet is in the bottom 8 to 10b of
2999 * the rss_hash value. The bottom 20b of this value contain the
3000 * ordering domain value for the packet.
3002 #define RX_PKT_CMPL_REORDER_MASK UINT32_C(0xffffff)
3003 #define RX_PKT_CMPL_REORDER_SFT 0
3007 * This TPA completion structure is used on devices where the
3008 * `hwrm_vnic_qcaps.max_aggs_supported` value is 0.
3010 /* rx_tpa_start_cmpl (size:128b/16B) */
3011 struct rx_tpa_start_cmpl {
3012 uint16_t flags_type;
3014 * This field indicates the exact type of the completion.
3015 * By convention, the LSB identifies the length of the
3016 * record in 16B units. Even values indicate 16B
3017 * records. Odd values indicate 32B
3020 #define RX_TPA_START_CMPL_TYPE_MASK UINT32_C(0x3f)
3021 #define RX_TPA_START_CMPL_TYPE_SFT 0
3023 * RX L2 TPA Start Completion:
3024 * Completion at the beginning of a TPA operation.
3027 #define RX_TPA_START_CMPL_TYPE_RX_TPA_START UINT32_C(0x13)
3028 #define RX_TPA_START_CMPL_TYPE_LAST \
3029 RX_TPA_START_CMPL_TYPE_RX_TPA_START
3030 #define RX_TPA_START_CMPL_FLAGS_MASK UINT32_C(0xffc0)
3031 #define RX_TPA_START_CMPL_FLAGS_SFT 6
3032 /* This bit will always be '0' for TPA start completions. */
3033 #define RX_TPA_START_CMPL_FLAGS_ERROR UINT32_C(0x40)
3034 /* This field indicates how the packet was placed in the buffer. */
3035 #define RX_TPA_START_CMPL_FLAGS_PLACEMENT_MASK UINT32_C(0x380)
3036 #define RX_TPA_START_CMPL_FLAGS_PLACEMENT_SFT 7
3039 * TPA Packet was placed using jumbo algorithm. This means
3040 * that the first buffer will be filled with data before
3041 * moving to aggregation buffers. Each aggregation buffer
3042 * will be filled before moving to the next aggregation
3045 #define RX_TPA_START_CMPL_FLAGS_PLACEMENT_JUMBO \
3046 (UINT32_C(0x1) << 7)
3048 * Header/Data Separation:
3049 * Packet was placed using Header/Data separation algorithm.
3050 * The separation location is indicated by the itype field.
3052 #define RX_TPA_START_CMPL_FLAGS_PLACEMENT_HDS \
3053 (UINT32_C(0x2) << 7)
3056 * Packet will be placed using GRO/Jumbo where the first
3057 * packet is filled with data. Subsequent packets will be
3058 * placed such that any one packet does not span two
3059 * aggregation buffers unless it starts at the beginning of
3060 * an aggregation buffer.
3062 #define RX_TPA_START_CMPL_FLAGS_PLACEMENT_GRO_JUMBO \
3063 (UINT32_C(0x5) << 7)
3065 * GRO/Header-Data Separation:
3066 * Packet will be placed using GRO/HDS where the header
3067 * is in the first packet.
3068 * Payload of each packet will be
3069 * placed such that any one packet does not span two
3070 * aggregation buffers unless it starts at the beginning of
3071 * an aggregation buffer.
3073 #define RX_TPA_START_CMPL_FLAGS_PLACEMENT_GRO_HDS \
3074 (UINT32_C(0x6) << 7)
3075 #define RX_TPA_START_CMPL_FLAGS_PLACEMENT_LAST \
3076 RX_TPA_START_CMPL_FLAGS_PLACEMENT_GRO_HDS
3077 /* This bit is '1' if the RSS field in this completion is valid. */
3078 #define RX_TPA_START_CMPL_FLAGS_RSS_VALID UINT32_C(0x400)
3080 #define RX_TPA_START_CMPL_FLAGS_UNUSED UINT32_C(0x800)
3082 * This value indicates what the inner packet determined for the
3085 #define RX_TPA_START_CMPL_FLAGS_ITYPE_MASK UINT32_C(0xf000)
3086 #define RX_TPA_START_CMPL_FLAGS_ITYPE_SFT 12
3089 * Indicates that the packet was IP and TCP.
3091 #define RX_TPA_START_CMPL_FLAGS_ITYPE_TCP \
3092 (UINT32_C(0x2) << 12)
3093 #define RX_TPA_START_CMPL_FLAGS_ITYPE_LAST \
3094 RX_TPA_START_CMPL_FLAGS_ITYPE_TCP
3096 * This value indicates the amount of packet data written to the
3097 * buffer the opaque field in this completion corresponds to.
3101 * This is a copy of the opaque field from the RX BD this completion
3106 * This value is written by the NIC such that it will be different
3107 * for each pass through the completion queue. The even passes
3108 * will write 1. The odd passes will write 0.
3112 * This value is written by the NIC such that it will be different
3113 * for each pass through the completion queue. The even passes
3114 * will write 1. The odd passes will write 0.
3116 #define RX_TPA_START_CMPL_V1 UINT32_C(0x1)
3117 #define RX_TPA_START_CMPL_LAST RX_TPA_START_CMPL_V1
3119 * This is the RSS hash type for the packet. The value is packed
3120 * {tuple_extrac_op[1:0],rss_profile_id[4:0],tuple_extrac_op[2]}.
3122 * The value of tuple_extrac_op provides the information about
3123 * what fields the hash was computed on.
3124 * * 0: The RSS hash was computed over source IP address,
3125 * destination IP address, source port, and destination port of inner
3126 * IP and TCP or UDP headers. Note: For non-tunneled packets,
3127 * the packet headers are considered inner packet headers for the RSS
3128 * hash computation purpose.
3129 * * 1: The RSS hash was computed over source IP address and destination
3130 * IP address of inner IP header. Note: For non-tunneled packets,
3131 * the packet headers are considered inner packet headers for the RSS
3132 * hash computation purpose.
3133 * * 2: The RSS hash was computed over source IP address,
3134 * destination IP address, source port, and destination port of
3135 * IP and TCP or UDP headers of outer tunnel headers.
3136 * Note: For non-tunneled packets, this value is not applicable.
3137 * * 3: The RSS hash was computed over source IP address and
3138 * destination IP address of IP header of outer tunnel headers.
3139 * Note: For non-tunneled packets, this value is not applicable.
3141 * Note that 4-tuples values listed above are applicable
3142 * for layer 4 protocols supported and enabled for RSS in the hardware,
3143 * HWRM firmware, and drivers. For example, if RSS hash is supported and
3144 * enabled for TCP traffic only, then the values of tuple_extract_op
3145 * corresponding to 4-tuples are only valid for TCP traffic.
3147 uint8_t rss_hash_type;
3149 * This is the aggregation ID that the completion is associated
3150 * with. Use this number to correlate the TPA start completion
3151 * with the TPA end completion.
3154 /* unused2 is 9 b */
3155 #define RX_TPA_START_CMPL_UNUSED2_MASK UINT32_C(0x1ff)
3156 #define RX_TPA_START_CMPL_UNUSED2_SFT 0
3158 * This is the aggregation ID that the completion is associated
3159 * with. Use this number to correlate the TPA start completion
3160 * with the TPA end completion.
3162 #define RX_TPA_START_CMPL_AGG_ID_MASK UINT32_C(0xfe00)
3163 #define RX_TPA_START_CMPL_AGG_ID_SFT 9
3165 * This value is the RSS hash value calculated for the packet
3166 * based on the mode bits and key value in the VNIC.
3172 * Last 16 bytes of rx_tpa_start_cmpl.
3174 * This TPA completion structure is used on devices where the
3175 * `hwrm_vnic_qcaps.max_aggs_supported` value is 0.
3177 /* rx_tpa_start_cmpl_hi (size:128b/16B) */
3178 struct rx_tpa_start_cmpl_hi {
3181 * This indicates that the ip checksum was calculated for the
3182 * inner packet and that the sum passed for all segments
3183 * included in the aggregation.
3185 #define RX_TPA_START_CMPL_FLAGS2_IP_CS_CALC UINT32_C(0x1)
3187 * This indicates that the TCP, UDP or ICMP checksum was
3188 * calculated for the inner packet and that the sum passed
3189 * for all segments included in the aggregation.
3191 #define RX_TPA_START_CMPL_FLAGS2_L4_CS_CALC UINT32_C(0x2)
3193 * This indicates that the ip checksum was calculated for the
3194 * tunnel header and that the sum passed for all segments
3195 * included in the aggregation.
3197 #define RX_TPA_START_CMPL_FLAGS2_T_IP_CS_CALC UINT32_C(0x4)
3199 * This indicates that the UDP checksum was
3200 * calculated for the tunnel packet and that the sum passed for
3201 * all segments included in the aggregation.
3203 #define RX_TPA_START_CMPL_FLAGS2_T_L4_CS_CALC UINT32_C(0x8)
3204 /* This value indicates what format the metadata field is. */
3205 #define RX_TPA_START_CMPL_FLAGS2_META_FORMAT_MASK UINT32_C(0xf0)
3206 #define RX_TPA_START_CMPL_FLAGS2_META_FORMAT_SFT 4
3207 /* No metadata information. Value is zero. */
3208 #define RX_TPA_START_CMPL_FLAGS2_META_FORMAT_NONE \
3209 (UINT32_C(0x0) << 4)
3211 * The metadata field contains the VLAN tag and TPID value.
3212 * - metadata[11:0] contains the vlan VID value.
3213 * - metadata[12] contains the vlan DE value.
3214 * - metadata[15:13] contains the vlan PRI value.
3215 * - metadata[31:16] contains the vlan TPID value.
3217 #define RX_TPA_START_CMPL_FLAGS2_META_FORMAT_VLAN \
3218 (UINT32_C(0x1) << 4)
3219 #define RX_TPA_START_CMPL_FLAGS2_META_FORMAT_LAST \
3220 RX_TPA_START_CMPL_FLAGS2_META_FORMAT_VLAN
3222 * This field indicates the IP type for the inner-most IP header.
3223 * A value of '0' indicates IPv4. A value of '1' indicates IPv6.
3225 #define RX_TPA_START_CMPL_FLAGS2_IP_TYPE UINT32_C(0x100)
3227 * This is data from the CFA block as indicated by the meta_format
3231 /* When meta_format=1, this value is the VLAN VID. */
3232 #define RX_TPA_START_CMPL_METADATA_VID_MASK UINT32_C(0xfff)
3233 #define RX_TPA_START_CMPL_METADATA_VID_SFT 0
3234 /* When meta_format=1, this value is the VLAN DE. */
3235 #define RX_TPA_START_CMPL_METADATA_DE UINT32_C(0x1000)
3236 /* When meta_format=1, this value is the VLAN PRI. */
3237 #define RX_TPA_START_CMPL_METADATA_PRI_MASK UINT32_C(0xe000)
3238 #define RX_TPA_START_CMPL_METADATA_PRI_SFT 13
3239 /* When meta_format=1, this value is the VLAN TPID. */
3240 #define RX_TPA_START_CMPL_METADATA_TPID_MASK UINT32_C(0xffff0000)
3241 #define RX_TPA_START_CMPL_METADATA_TPID_SFT 16
3244 * This value is written by the NIC such that it will be different
3245 * for each pass through the completion queue. The even passes
3246 * will write 1. The odd passes will write 0.
3248 #define RX_TPA_START_CMPL_V2 UINT32_C(0x1)
3250 * This field identifies the CFA action rule that was used for this
3255 * This is the size in bytes of the inner most L4 header.
3256 * This can be subtracted from the payload_offset to determine
3257 * the start of the inner most L4 header.
3259 uint32_t inner_l4_size_inner_l3_offset_inner_l2_offset_outer_l3_offset;
3261 * This is the offset from the beginning of the packet in bytes for
3262 * the outer L3 header. If there is no outer L3 header, then this
3265 #define RX_TPA_START_CMPL_OUTER_L3_OFFSET_MASK UINT32_C(0x1ff)
3266 #define RX_TPA_START_CMPL_OUTER_L3_OFFSET_SFT 0
3268 * This is the offset from the beginning of the packet in bytes for
3269 * the inner most L2 header.
3271 #define RX_TPA_START_CMPL_INNER_L2_OFFSET_MASK UINT32_C(0x3fe00)
3272 #define RX_TPA_START_CMPL_INNER_L2_OFFSET_SFT 9
3274 * This is the offset from the beginning of the packet in bytes for
3275 * the inner most L3 header.
3277 #define RX_TPA_START_CMPL_INNER_L3_OFFSET_MASK UINT32_C(0x7fc0000)
3278 #define RX_TPA_START_CMPL_INNER_L3_OFFSET_SFT 18
3280 * This is the size in bytes of the inner most L4 header.
3281 * This can be subtracted from the payload_offset to determine
3282 * the start of the inner most L4 header.
3284 #define RX_TPA_START_CMPL_INNER_L4_SIZE_MASK UINT32_C(0xf8000000)
3285 #define RX_TPA_START_CMPL_INNER_L4_SIZE_SFT 27
3289 * This TPA completion structure is used on devices where the
3290 * `hwrm_vnic_qcaps.max_aggs_supported` value is 0.
3292 /* rx_tpa_end_cmpl (size:128b/16B) */
3293 struct rx_tpa_end_cmpl {
3294 uint16_t flags_type;
3296 * This field indicates the exact type of the completion.
3297 * By convention, the LSB identifies the length of the
3298 * record in 16B units. Even values indicate 16B
3299 * records. Odd values indicate 32B
3302 #define RX_TPA_END_CMPL_TYPE_MASK UINT32_C(0x3f)
3303 #define RX_TPA_END_CMPL_TYPE_SFT 0
3305 * RX L2 TPA End Completion:
3306 * Completion at the end of a TPA operation.
3309 #define RX_TPA_END_CMPL_TYPE_RX_TPA_END UINT32_C(0x15)
3310 #define RX_TPA_END_CMPL_TYPE_LAST \
3311 RX_TPA_END_CMPL_TYPE_RX_TPA_END
3312 #define RX_TPA_END_CMPL_FLAGS_MASK UINT32_C(0xffc0)
3313 #define RX_TPA_END_CMPL_FLAGS_SFT 6
3315 * When this bit is '1', it indicates a packet that has an
3316 * error of some type. Type of error is indicated in
3319 #define RX_TPA_END_CMPL_FLAGS_ERROR UINT32_C(0x40)
3320 /* This field indicates how the packet was placed in the buffer. */
3321 #define RX_TPA_END_CMPL_FLAGS_PLACEMENT_MASK UINT32_C(0x380)
3322 #define RX_TPA_END_CMPL_FLAGS_PLACEMENT_SFT 7
3325 * TPA Packet was placed using jumbo algorithm. This means
3326 * that the first buffer will be filled with data before
3327 * moving to aggregation buffers. Each aggregation buffer
3328 * will be filled before moving to the next aggregation
3331 #define RX_TPA_END_CMPL_FLAGS_PLACEMENT_JUMBO \
3332 (UINT32_C(0x1) << 7)
3334 * Header/Data Separation:
3335 * Packet was placed using Header/Data separation algorithm.
3336 * The separation location is indicated by the itype field.
3338 #define RX_TPA_END_CMPL_FLAGS_PLACEMENT_HDS \
3339 (UINT32_C(0x2) << 7)
3342 * Packet will be placed using GRO/Jumbo where the first
3343 * packet is filled with data. Subsequent packets will be
3344 * placed such that any one packet does not span two
3345 * aggregation buffers unless it starts at the beginning of
3346 * an aggregation buffer.
3348 #define RX_TPA_END_CMPL_FLAGS_PLACEMENT_GRO_JUMBO \
3349 (UINT32_C(0x5) << 7)
3351 * GRO/Header-Data Separation:
3352 * Packet will be placed using GRO/HDS where the header
3353 * is in the first packet.
3354 * Payload of each packet will be
3355 * placed such that any one packet does not span two
3356 * aggregation buffers unless it starts at the beginning of
3357 * an aggregation buffer.
3359 #define RX_TPA_END_CMPL_FLAGS_PLACEMENT_GRO_HDS \
3360 (UINT32_C(0x6) << 7)
3361 #define RX_TPA_END_CMPL_FLAGS_PLACEMENT_LAST \
3362 RX_TPA_END_CMPL_FLAGS_PLACEMENT_GRO_HDS
3364 #define RX_TPA_END_CMPL_FLAGS_UNUSED_MASK UINT32_C(0xc00)
3365 #define RX_TPA_END_CMPL_FLAGS_UNUSED_SFT 10
3367 * This value indicates what the inner packet determined for the
3370 * Indicates that the packet was IP and TCP. This indicates
3371 * that the ip_cs field is valid and that the tcp_udp_cs
3372 * field is valid and contains the TCP checksum.
3373 * This also indicates that the payload_offset field is valid.
3375 #define RX_TPA_END_CMPL_FLAGS_ITYPE_MASK UINT32_C(0xf000)
3376 #define RX_TPA_END_CMPL_FLAGS_ITYPE_SFT 12
3378 * This value is zero for TPA End completions.
3379 * There is no data in the buffer that corresponds to the opaque
3380 * value in this completion.
3384 * This is a copy of the opaque field from the RX BD this completion
3389 * This value is written by the NIC such that it will be different
3390 * for each pass through the completion queue. The even passes
3391 * will write 1. The odd passes will write 0.
3393 uint8_t agg_bufs_v1;
3395 * This value is written by the NIC such that it will be different
3396 * for each pass through the completion queue. The even passes
3397 * will write 1. The odd passes will write 0.
3399 #define RX_TPA_END_CMPL_V1 UINT32_C(0x1)
3401 * This value is the number of aggregation buffers that follow this
3402 * entry in the completion ring that are a part of this aggregation
3404 * If the value is zero, then the packet is completely contained
3405 * in the buffer space provided in the aggregation start completion.
3407 #define RX_TPA_END_CMPL_AGG_BUFS_MASK UINT32_C(0x7e)
3408 #define RX_TPA_END_CMPL_AGG_BUFS_SFT 1
3409 /* This value is the number of segments in the TPA operation. */
3412 * This value indicates the offset in bytes from the beginning of the packet
3413 * where the inner payload starts. This value is valid for TCP, UDP,
3414 * FCoE, and RoCE packets.
3416 * A value of zero indicates an offset of 256 bytes.
3418 uint8_t payload_offset;
3420 /* unused2 is 1 b */
3421 #define RX_TPA_END_CMPL_UNUSED2 UINT32_C(0x1)
3423 * This is the aggregation ID that the completion is associated
3424 * with. Use this number to correlate the TPA start completion
3425 * with the TPA end completion.
3427 #define RX_TPA_END_CMPL_AGG_ID_MASK UINT32_C(0xfe)
3428 #define RX_TPA_END_CMPL_AGG_ID_SFT 1
3430 * For non-GRO packets, this value is the
3431 * timestamp delta between earliest and latest timestamp values for
3432 * TPA packet. If packets were not time stamped, then delta will be
3435 * For GRO packets, this field is zero except for the following
3438 * Timestamp present indication. When '0', no Timestamp
3439 * option is in the packet. When '1', then a Timestamp
3440 * option is present in the packet.
3446 * Last 16 bytes of rx_tpa_end_cmpl.
3448 * This TPA completion structure is used on devices where the
3449 * `hwrm_vnic_qcaps.max_aggs_supported` value is 0.
3451 /* rx_tpa_end_cmpl_hi (size:128b/16B) */
3452 struct rx_tpa_end_cmpl_hi {
3453 uint32_t tpa_dup_acks;
3455 * This value is the number of duplicate ACKs that have been
3456 * received as part of the TPA operation.
3458 #define RX_TPA_END_CMPL_TPA_DUP_ACKS_MASK UINT32_C(0xf)
3459 #define RX_TPA_END_CMPL_TPA_DUP_ACKS_SFT 0
3461 * This value is the valid when TPA completion is active. It
3462 * indicates the length of the longest segment of the TPA operation
3463 * for LRO mode and the length of the first segment in GRO mode.
3465 * This value may be used by GRO software to re-construct the original
3466 * packet stream from the TPA packet. This is the length of all
3467 * but the last segment for GRO. In LRO mode this value may be used
3468 * to indicate MSS size to the stack.
3470 uint16_t tpa_seg_len;
3471 /* unused4 is 16 b */
3475 * This value is written by the NIC such that it will be different
3476 * for each pass through the completion queue. The even passes
3477 * will write 1. The odd passes will write 0.
3479 #define RX_TPA_END_CMPL_V2 UINT32_C(0x1)
3480 #define RX_TPA_END_CMPL_ERRORS_MASK UINT32_C(0xfffe)
3481 #define RX_TPA_END_CMPL_ERRORS_SFT 1
3483 * This error indicates that there was some sort of problem with
3484 * the BDs for the packet that was found after part of the
3485 * packet was already placed. The packet should be treated as
3488 #define RX_TPA_END_CMPL_ERRORS_BUFFER_ERROR_MASK UINT32_C(0xe)
3489 #define RX_TPA_END_CMPL_ERRORS_BUFFER_ERROR_SFT 1
3491 * This error occurs when there is a fatal HW problem in
3492 * the chip only. It indicates that there were not
3493 * BDs on chip but that there was adequate reservation.
3494 * provided by the TPA block.
3496 #define RX_TPA_END_CMPL_ERRORS_BUFFER_ERROR_NOT_ON_CHIP \
3497 (UINT32_C(0x2) << 1)
3499 * This error occurs when TPA block was not configured to
3500 * reserve adequate BDs for TPA operations on this RX
3501 * ring. All data for the TPA operation was not placed.
3503 * This error can also be generated when the number of
3504 * segments is not programmed correctly in TPA and the
3505 * 33 total aggregation buffers allowed for the TPA
3506 * operation has been exceeded.
3508 #define RX_TPA_END_CMPL_ERRORS_BUFFER_ERROR_RSV_ERROR \
3509 (UINT32_C(0x4) << 1)
3510 #define RX_TPA_END_CMPL_ERRORS_BUFFER_ERROR_LAST \
3511 RX_TPA_END_CMPL_ERRORS_BUFFER_ERROR_RSV_ERROR
3512 /* unused5 is 16 b */
3515 * This is the opaque value that was completed for the TPA start
3516 * completion that corresponds to this TPA end completion.
3518 uint32_t start_opaque;
3522 * This TPA completion structure is used on devices where the
3523 * `hwrm_vnic_qcaps.max_aggs_supported` value is greater than 0.
3525 /* rx_tpa_v2_start_cmpl (size:128b/16B) */
3526 struct rx_tpa_v2_start_cmpl {
3527 uint16_t flags_type;
3529 * This field indicates the exact type of the completion.
3530 * By convention, the LSB identifies the length of the
3531 * record in 16B units. Even values indicate 16B
3532 * records. Odd values indicate 32B
3535 #define RX_TPA_V2_START_CMPL_TYPE_MASK \
3537 #define RX_TPA_V2_START_CMPL_TYPE_SFT 0
3539 * RX L2 TPA Start Completion:
3540 * Completion at the beginning of a TPA operation.
3543 #define RX_TPA_V2_START_CMPL_TYPE_RX_TPA_START \
3545 #define RX_TPA_V2_START_CMPL_TYPE_LAST \
3546 RX_TPA_V2_START_CMPL_TYPE_RX_TPA_START
3547 #define RX_TPA_V2_START_CMPL_FLAGS_MASK \
3549 #define RX_TPA_V2_START_CMPL_FLAGS_SFT 6
3550 /* This bit will always be '0' for TPA start completions. */
3551 #define RX_TPA_V2_START_CMPL_FLAGS_ERROR \
3553 /* This field indicates how the packet was placed in the buffer. */
3554 #define RX_TPA_V2_START_CMPL_FLAGS_PLACEMENT_MASK \
3556 #define RX_TPA_V2_START_CMPL_FLAGS_PLACEMENT_SFT 7
3559 * TPA Packet was placed using jumbo algorithm. This means
3560 * that the first buffer will be filled with data before
3561 * moving to aggregation buffers. Each aggregation buffer
3562 * will be filled before moving to the next aggregation
3565 #define RX_TPA_V2_START_CMPL_FLAGS_PLACEMENT_JUMBO \
3566 (UINT32_C(0x1) << 7)
3568 * Header/Data Separation:
3569 * Packet was placed using Header/Data separation algorithm.
3570 * The separation location is indicated by the itype field.
3572 #define RX_TPA_V2_START_CMPL_FLAGS_PLACEMENT_HDS \
3573 (UINT32_C(0x2) << 7)
3576 * Packet will be placed using GRO/Jumbo where the first
3577 * packet is filled with data. Subsequent packets will be
3578 * placed such that any one packet does not span two
3579 * aggregation buffers unless it starts at the beginning of
3580 * an aggregation buffer.
3582 #define RX_TPA_V2_START_CMPL_FLAGS_PLACEMENT_GRO_JUMBO \
3583 (UINT32_C(0x5) << 7)
3585 * GRO/Header-Data Separation:
3586 * Packet will be placed using GRO/HDS where the header
3587 * is in the first packet.
3588 * Payload of each packet will be
3589 * placed such that any one packet does not span two
3590 * aggregation buffers unless it starts at the beginning of
3591 * an aggregation buffer.
3593 #define RX_TPA_V2_START_CMPL_FLAGS_PLACEMENT_GRO_HDS \
3594 (UINT32_C(0x6) << 7)
3595 #define RX_TPA_V2_START_CMPL_FLAGS_PLACEMENT_LAST \
3596 RX_TPA_V2_START_CMPL_FLAGS_PLACEMENT_GRO_HDS
3597 /* This bit is '1' if the RSS field in this completion is valid. */
3598 #define RX_TPA_V2_START_CMPL_FLAGS_RSS_VALID \
3601 * For devices that support timestamps, when this bit is cleared the
3602 * `inner_l4_size_inner_l3_offset_inner_l2_offset_outer_l3_offset`
3603 * field contains the 32b timestamp for
3604 * the packet from the MAC. When this bit is set, the
3605 * `inner_l4_size_inner_l3_offset_inner_l2_offset_outer_l3_offset`
3606 * field contains the outer_l3_offset, inner_l2_offset,
3607 * inner_l3_offset, and inner_l4_size.
3609 #define RX_TPA_V2_START_CMPL_FLAGS_TIMESTAMP_FLD_FORMAT \
3612 * This value indicates what the inner packet determined for the
3615 #define RX_TPA_V2_START_CMPL_FLAGS_ITYPE_MASK \
3617 #define RX_TPA_V2_START_CMPL_FLAGS_ITYPE_SFT 12
3620 * Indicates that the packet was IP and TCP.
3622 #define RX_TPA_V2_START_CMPL_FLAGS_ITYPE_TCP \
3623 (UINT32_C(0x2) << 12)
3624 #define RX_TPA_V2_START_CMPL_FLAGS_ITYPE_LAST \
3625 RX_TPA_V2_START_CMPL_FLAGS_ITYPE_TCP
3627 * This value indicates the amount of packet data written to the
3628 * buffer the opaque field in this completion corresponds to.
3632 * This is a copy of the opaque field from the RX BD this completion
3637 * This value is written by the NIC such that it will be different
3638 * for each pass through the completion queue. The even passes
3639 * will write 1. The odd passes will write 0.
3643 * This value is written by the NIC such that it will be different
3644 * for each pass through the completion queue. The even passes
3645 * will write 1. The odd passes will write 0.
3647 #define RX_TPA_V2_START_CMPL_V1 UINT32_C(0x1)
3648 #define RX_TPA_V2_START_CMPL_LAST RX_TPA_V2_START_CMPL_V1
3650 * This is the RSS hash type for the packet. The value is packed
3651 * {tuple_extrac_op[1:0],rss_profile_id[4:0],tuple_extrac_op[2]}.
3653 * The value of tuple_extrac_op provides the information about
3654 * what fields the hash was computed on.
3655 * * 0: The RSS hash was computed over source IP address,
3656 * destination IP address, source port, and destination port of inner
3657 * IP and TCP or UDP headers. Note: For non-tunneled packets,
3658 * the packet headers are considered inner packet headers for the RSS
3659 * hash computation purpose.
3660 * * 1: The RSS hash was computed over source IP address and destination
3661 * IP address of inner IP header. Note: For non-tunneled packets,
3662 * the packet headers are considered inner packet headers for the RSS
3663 * hash computation purpose.
3664 * * 2: The RSS hash was computed over source IP address,
3665 * destination IP address, source port, and destination port of
3666 * IP and TCP or UDP headers of outer tunnel headers.
3667 * Note: For non-tunneled packets, this value is not applicable.
3668 * * 3: The RSS hash was computed over source IP address and
3669 * destination IP address of IP header of outer tunnel headers.
3670 * Note: For non-tunneled packets, this value is not applicable.
3672 * Note that 4-tuples values listed above are applicable
3673 * for layer 4 protocols supported and enabled for RSS in the hardware,
3674 * HWRM firmware, and drivers. For example, if RSS hash is supported and
3675 * enabled for TCP traffic only, then the values of tuple_extract_op
3676 * corresponding to 4-tuples are only valid for TCP traffic.
3678 uint8_t rss_hash_type;
3680 * This is the aggregation ID that the completion is associated
3681 * with. Use this number to correlate the TPA start completion
3682 * with the TPA end completion.
3686 * This value is the RSS hash value calculated for the packet
3687 * based on the mode bits and key value in the VNIC.
3693 * Last 16 bytes of rx_tpa_v2_start_cmpl.
3695 * This TPA completion structure is used on devices where the
3696 * `hwrm_vnic_qcaps.max_aggs_supported` value is greater than 0.
3698 /* rx_tpa_v2_start_cmpl_hi (size:128b/16B) */
3699 struct rx_tpa_v2_start_cmpl_hi {
3702 * This indicates that the ip checksum was calculated for the
3703 * inner packet and that the sum passed for all segments
3704 * included in the aggregation.
3706 #define RX_TPA_V2_START_CMPL_FLAGS2_IP_CS_CALC \
3709 * This indicates that the TCP, UDP or ICMP checksum was
3710 * calculated for the inner packet and that the sum passed
3711 * for all segments included in the aggregation.
3713 #define RX_TPA_V2_START_CMPL_FLAGS2_L4_CS_CALC \
3716 * This indicates that the ip checksum was calculated for the
3717 * tunnel header and that the sum passed for all segments
3718 * included in the aggregation.
3720 #define RX_TPA_V2_START_CMPL_FLAGS2_T_IP_CS_CALC \
3723 * This indicates that the UDP checksum was
3724 * calculated for the tunnel packet and that the sum passed for
3725 * all segments included in the aggregation.
3727 #define RX_TPA_V2_START_CMPL_FLAGS2_T_L4_CS_CALC \
3729 /* This value indicates what format the metadata field is. */
3730 #define RX_TPA_V2_START_CMPL_FLAGS2_META_FORMAT_MASK \
3732 #define RX_TPA_V2_START_CMPL_FLAGS2_META_FORMAT_SFT 4
3733 /* No metadata informtaion. Value is zero. */
3734 #define RX_TPA_V2_START_CMPL_FLAGS2_META_FORMAT_NONE \
3735 (UINT32_C(0x0) << 4)
3737 * The metadata field contains the VLAN tag and TPID value.
3738 * - metadata[11:0] contains the vlan VID value.
3739 * - metadata[12] contains the vlan DE value.
3740 * - metadata[15:13] contains the vlan PRI value.
3741 * - metadata[31:16] contains the vlan TPID value.
3743 #define RX_TPA_V2_START_CMPL_FLAGS2_META_FORMAT_VLAN \
3744 (UINT32_C(0x1) << 4)
3746 * If ext_meta_format is equal to 1, the metadata field
3747 * contains the lower 16b of the tunnel ID value, justified
3749 * - VXLAN = VNI[23:0] -> VXLAN Network ID
3750 * - Geneve (NGE) = VNI[23:0] a-> Virtual Network Identifier.
3751 * - NVGRE = TNI[23:0] -> Tenant Network ID
3752 * - GRE = KEY[31:0 -> key fieled with bit mask. zero if K = 0
3753 * - IPV4 = 0 (not populated)
3754 * - IPV6 = Flow Label[19:0]
3755 * - PPPoE = sessionID[15:0]
3756 * - MPLs = Outer label[19:0]
3757 * - UPAR = Selected[31:0] with bit mask
3759 #define RX_TPA_V2_START_CMPL_FLAGS2_META_FORMAT_TUNNEL_ID \
3760 (UINT32_C(0x2) << 4)
3762 * if ext_meta_format is equal to 1, metadata field contains
3763 * 16b metadata from the prepended header (chdr_data).
3765 #define RX_TPA_V2_START_CMPL_FLAGS2_META_FORMAT_CHDR_DATA \
3766 (UINT32_C(0x3) << 4)
3768 * If ext_meta_format is equal to 1, the metadata field contains
3769 * the outer_l3_offset, inner_l2_offset, inner_l3_offset and
3771 * - metadata[8:0] contains the outer_l3_offset.
3772 * - metadata[17:9] contains the inner_l2_offset.
3773 * - metadata[26:18] contains the inner_l3_offset.
3774 * - metadata[31:27] contains the inner_l4_size.
3776 #define RX_TPA_V2_START_CMPL_FLAGS2_META_FORMAT_HDR_OFFSET \
3777 (UINT32_C(0x4) << 4)
3778 #define RX_TPA_V2_START_CMPL_FLAGS2_META_FORMAT_LAST \
3779 RX_TPA_V2_START_CMPL_FLAGS2_META_FORMAT_HDR_OFFSET
3781 * This field indicates the IP type for the inner-most IP header.
3782 * A value of '0' indicates IPv4. A value of '1' indicates IPv6.
3784 #define RX_TPA_V2_START_CMPL_FLAGS2_IP_TYPE \
3787 * This indicates that the complete 1's complement checksum was
3788 * calculated for the packet.
3790 #define RX_TPA_V2_START_CMPL_FLAGS2_COMPLETE_CHECKSUM_CALC \
3793 * The combination of this value and meta_format indicated what
3794 * format the metadata field is.
3796 #define RX_TPA_V2_START_CMPL_FLAGS2_EXT_META_FORMAT_MASK \
3798 #define RX_TPA_V2_START_CMPL_FLAGS2_EXT_META_FORMAT_SFT 10
3800 * This value is the complete 1's complement checksum calculated from
3801 * the start of the outer L3 header to the end of the packet (not
3802 * including the ethernet crc). It is valid when the
3803 * 'complete_checksum_calc' flag is set. For TPA Start completions,
3804 * the complete checksum is calculated for the first packet in the
3807 #define RX_TPA_V2_START_CMPL_FLAGS2_COMPLETE_CHECKSUM_MASK \
3808 UINT32_C(0xffff0000)
3809 #define RX_TPA_V2_START_CMPL_FLAGS2_COMPLETE_CHECKSUM_SFT 16
3811 * This is data from the CFA block as indicated by the meta_format
3815 /* When {ext_meta_format,meta_format}=1, this value is the VLAN VID. */
3816 #define RX_TPA_V2_START_CMPL_METADATA_VID_MASK UINT32_C(0xfff)
3817 #define RX_TPA_V2_START_CMPL_METADATA_VID_SFT 0
3818 /* When {ext_meta_format,meta_format}=1, this value is the VLAN DE. */
3819 #define RX_TPA_V2_START_CMPL_METADATA_DE UINT32_C(0x1000)
3820 /* When {ext_meta_format,meta_format}=1, this value is the VLAN PRI. */
3821 #define RX_TPA_V2_START_CMPL_METADATA_PRI_MASK UINT32_C(0xe000)
3822 #define RX_TPA_V2_START_CMPL_METADATA_PRI_SFT 13
3823 /* When {ext_meta_format,meta_format}=1, this value is the VLAN TPID. */
3824 #define RX_TPA_V2_START_CMPL_METADATA_TPID_MASK UINT32_C(0xffff0000)
3825 #define RX_TPA_V2_START_CMPL_METADATA_TPID_SFT 16
3828 * This value is written by the NIC such that it will be different
3829 * for each pass through the completion queue. The even passes
3830 * will write 1. The odd passes will write 0.
3832 #define RX_TPA_V2_START_CMPL_V2 \
3834 #define RX_TPA_V2_START_CMPL_ERRORS_MASK \
3836 #define RX_TPA_V2_START_CMPL_ERRORS_SFT 1
3838 * This error indicates that there was some sort of problem with
3839 * the BDs for the packet that was found after part of the
3840 * packet was already placed. The packet should be treated as
3843 #define RX_TPA_V2_START_CMPL_ERRORS_BUFFER_ERROR_MASK \
3845 #define RX_TPA_V2_START_CMPL_ERRORS_BUFFER_ERROR_SFT 1
3846 /* No buffer error */
3847 #define RX_TPA_V2_START_CMPL_ERRORS_BUFFER_ERROR_NO_BUFFER \
3848 (UINT32_C(0x0) << 1)
3851 * BDs were not formatted correctly.
3853 #define RX_TPA_V2_START_CMPL_ERRORS_BUFFER_ERROR_BAD_FORMAT \
3854 (UINT32_C(0x3) << 1)
3857 * There was a bad_format error on the previous operation
3859 #define RX_TPA_V2_START_CMPL_ERRORS_BUFFER_ERROR_FLUSH \
3860 (UINT32_C(0x5) << 1)
3861 #define RX_TPA_V2_START_CMPL_ERRORS_BUFFER_ERROR_LAST \
3862 RX_TPA_V2_START_CMPL_ERRORS_BUFFER_ERROR_FLUSH
3864 * This field identifies the CFA action rule that was used for this
3869 * For devices that support timestamps this field is overridden
3870 * with the timestamp value. When `flags.timestamp_fld_format` is
3871 * cleared, this field contains the 32b timestamp for the packet from the
3874 * When `flags.timestamp_fld_format` is set, this field contains the
3875 * outer_l3_offset, inner_l2_offset, inner_l3_offset, and inner_l4_size
3878 uint32_t inner_l4_size_inner_l3_offset_inner_l2_offset_outer_l3_offset;
3880 * This is the offset from the beginning of the packet in bytes for
3881 * the outer L3 header. If there is no outer L3 header, then this
3884 #define RX_TPA_V2_START_CMPL_OUTER_L3_OFFSET_MASK UINT32_C(0x1ff)
3885 #define RX_TPA_V2_START_CMPL_OUTER_L3_OFFSET_SFT 0
3887 * This is the offset from the beginning of the packet in bytes for
3888 * the inner most L2 header.
3890 #define RX_TPA_V2_START_CMPL_INNER_L2_OFFSET_MASK UINT32_C(0x3fe00)
3891 #define RX_TPA_V2_START_CMPL_INNER_L2_OFFSET_SFT 9
3893 * This is the offset from the beginning of the packet in bytes for
3894 * the inner most L3 header.
3896 #define RX_TPA_V2_START_CMPL_INNER_L3_OFFSET_MASK UINT32_C(0x7fc0000)
3897 #define RX_TPA_V2_START_CMPL_INNER_L3_OFFSET_SFT 18
3899 * This is the size in bytes of the inner most L4 header.
3900 * This can be subtracted from the payload_offset to determine
3901 * the start of the inner most L4 header.
3903 #define RX_TPA_V2_START_CMPL_INNER_L4_SIZE_MASK UINT32_C(0xf8000000)
3904 #define RX_TPA_V2_START_CMPL_INNER_L4_SIZE_SFT 27
3908 * This TPA completion structure is used on devices where the
3909 * `hwrm_vnic_qcaps.max_aggs_supported` value is greater than 0.
3911 /* rx_tpa_v2_end_cmpl (size:128b/16B) */
3912 struct rx_tpa_v2_end_cmpl {
3913 uint16_t flags_type;
3915 * This field indicates the exact type of the completion.
3916 * By convention, the LSB identifies the length of the
3917 * record in 16B units. Even values indicate 16B
3918 * records. Odd values indicate 32B
3921 #define RX_TPA_V2_END_CMPL_TYPE_MASK UINT32_C(0x3f)
3922 #define RX_TPA_V2_END_CMPL_TYPE_SFT 0
3924 * RX L2 TPA End Completion:
3925 * Completion at the end of a TPA operation.
3928 #define RX_TPA_V2_END_CMPL_TYPE_RX_TPA_END UINT32_C(0x15)
3929 #define RX_TPA_V2_END_CMPL_TYPE_LAST \
3930 RX_TPA_V2_END_CMPL_TYPE_RX_TPA_END
3931 #define RX_TPA_V2_END_CMPL_FLAGS_MASK UINT32_C(0xffc0)
3932 #define RX_TPA_V2_END_CMPL_FLAGS_SFT 6
3934 * When this bit is '1', it indicates a packet that has an
3935 * error of some type. Type of error is indicated in
3938 #define RX_TPA_V2_END_CMPL_FLAGS_ERROR UINT32_C(0x40)
3939 /* This field indicates how the packet was placed in the buffer. */
3940 #define RX_TPA_V2_END_CMPL_FLAGS_PLACEMENT_MASK UINT32_C(0x380)
3941 #define RX_TPA_V2_END_CMPL_FLAGS_PLACEMENT_SFT 7
3944 * TPA Packet was placed using jumbo algorithm. This means
3945 * that the first buffer will be filled with data before
3946 * moving to aggregation buffers. Each aggregation buffer
3947 * will be filled before moving to the next aggregation
3950 #define RX_TPA_V2_END_CMPL_FLAGS_PLACEMENT_JUMBO \
3951 (UINT32_C(0x1) << 7)
3953 * Header/Data Separation:
3954 * Packet was placed using Header/Data separation algorithm.
3955 * The separation location is indicated by the itype field.
3957 #define RX_TPA_V2_END_CMPL_FLAGS_PLACEMENT_HDS \
3958 (UINT32_C(0x2) << 7)
3961 * Packet will be placed using GRO/Jumbo where the first
3962 * packet is filled with data. Subsequent packets will be
3963 * placed such that any one packet does not span two
3964 * aggregation buffers unless it starts at the beginning of
3965 * an aggregation buffer.
3967 #define RX_TPA_V2_END_CMPL_FLAGS_PLACEMENT_GRO_JUMBO \
3968 (UINT32_C(0x5) << 7)
3970 * GRO/Header-Data Separation:
3971 * Packet will be placed using GRO/HDS where the header
3972 * is in the first packet.
3973 * Payload of each packet will be
3974 * placed such that any one packet does not span two
3975 * aggregation buffers unless it starts at the beginning of
3976 * an aggregation buffer.
3978 #define RX_TPA_V2_END_CMPL_FLAGS_PLACEMENT_GRO_HDS \
3979 (UINT32_C(0x6) << 7)
3980 #define RX_TPA_V2_END_CMPL_FLAGS_PLACEMENT_LAST \
3981 RX_TPA_V2_END_CMPL_FLAGS_PLACEMENT_GRO_HDS
3983 #define RX_TPA_V2_END_CMPL_FLAGS_UNUSED_MASK UINT32_C(0xc00)
3984 #define RX_TPA_V2_END_CMPL_FLAGS_UNUSED_SFT 10
3986 * This value indicates what the inner packet determined for the
3989 * Indicates that the packet was IP and TCP. This indicates
3990 * that the ip_cs field is valid and that the tcp_udp_cs
3991 * field is valid and contains the TCP checksum.
3992 * This also indicates that the payload_offset field is valid.
3994 #define RX_TPA_V2_END_CMPL_FLAGS_ITYPE_MASK UINT32_C(0xf000)
3995 #define RX_TPA_V2_END_CMPL_FLAGS_ITYPE_SFT 12
3997 * This value is zero for TPA End completions.
3998 * There is no data in the buffer that corresponds to the opaque
3999 * value in this completion.
4003 * This is a copy of the opaque field from the RX BD this completion
4009 * This value is written by the NIC such that it will be different
4010 * for each pass through the completion queue. The even passes
4011 * will write 1. The odd passes will write 0.
4013 #define RX_TPA_V2_END_CMPL_V1 UINT32_C(0x1)
4014 /* This value is the number of segments in the TPA operation. */
4017 * This is the aggregation ID that the completion is associated
4018 * with. Use this number to correlate the TPA start completion
4019 * with the TPA end completion.
4023 * For non-GRO packets, this value is the
4024 * timestamp delta between earliest and latest timestamp values for
4025 * TPA packet. If packets were not time stamped, then delta will be
4028 * For GRO packets, this field is zero except for the following
4031 * Timestamp present indication. When '0', no Timestamp
4032 * option is in the packet. When '1', then a Timestamp
4033 * option is present in the packet.
4039 * Last 16 bytes of rx_tpa_v2_end_cmpl.
4041 * This TPA completion structure is used on devices where the
4042 * `hwrm_vnic_qcaps.max_aggs_supported` value is greater than 0.
4044 /* rx_tpa_v2_end_cmpl_hi (size:128b/16B) */
4045 struct rx_tpa_v2_end_cmpl_hi {
4047 * This value is the number of duplicate ACKs that have been
4048 * received as part of the TPA operation.
4050 uint16_t tpa_dup_acks;
4052 * This value is the number of duplicate ACKs that have been
4053 * received as part of the TPA operation.
4055 #define RX_TPA_V2_END_CMPL_TPA_DUP_ACKS_MASK UINT32_C(0xf)
4056 #define RX_TPA_V2_END_CMPL_TPA_DUP_ACKS_SFT 0
4058 * This value indicated the offset in bytes from the beginning of
4059 * the packet where the inner payload starts. This value is valid
4060 * for TCP, UDP, FCoE and RoCE packets
4062 uint8_t payload_offset;
4064 * The value is the total number of aggregation buffers that were
4065 * used in the TPA operation. All TPA aggregation buffer completions
4066 * precede the TPA End completion. If the value is zero, then the
4067 * aggregation is completely contained in the buffer space provided
4068 * in the aggregation start completion.
4069 * Note that the field is simply provided as a cross check.
4071 uint8_t tpa_agg_bufs;
4073 * This value is the valid when TPA completion is active. It
4074 * indicates the length of the longest segment of the TPA operation
4075 * for LRO mode and the length of the first segment in GRO mode.
4077 * This value may be used by GRO software to re-construct the original
4078 * packet stream from the TPA packet. This is the length of all
4079 * but the last segment for GRO. In LRO mode this value may be used
4080 * to indicate MSS size to the stack.
4082 uint16_t tpa_seg_len;
4086 * This value is written by the NIC such that it will be different
4087 * for each pass through the completion queue. The even passes
4088 * will write 1. The odd passes will write 0.
4090 #define RX_TPA_V2_END_CMPL_V2 UINT32_C(0x1)
4091 #define RX_TPA_V2_END_CMPL_ERRORS_MASK \
4093 #define RX_TPA_V2_END_CMPL_ERRORS_SFT 1
4095 * This error indicates that there was some sort of problem with
4096 * the BDs for the packet that was found after part of the
4097 * packet was already placed. The packet should be treated as
4100 #define RX_TPA_V2_END_CMPL_ERRORS_BUFFER_ERROR_MASK \
4102 #define RX_TPA_V2_END_CMPL_ERRORS_BUFFER_ERROR_SFT 1
4103 /* No buffer error */
4104 #define RX_TPA_V2_END_CMPL_ERRORS_BUFFER_ERROR_NO_BUFFER \
4105 (UINT32_C(0x0) << 1)
4107 * This error occurs when there is a fatal HW problem in
4108 * the chip only. It indicates that there were not
4109 * BDs on chip but that there was adequate reservation.
4110 * provided by the TPA block.
4112 #define RX_TPA_V2_END_CMPL_ERRORS_BUFFER_ERROR_NOT_ON_CHIP \
4113 (UINT32_C(0x2) << 1)
4116 * BDs were not formatted correctly.
4118 #define RX_TPA_V2_END_CMPL_ERRORS_BUFFER_ERROR_BAD_FORMAT \
4119 (UINT32_C(0x3) << 1)
4121 * This error occurs when TPA block was not configured to
4122 * reserve adequate BDs for TPA operations on this RX
4123 * ring. All data for the TPA operation was not placed.
4125 * This error can also be generated when the number of
4126 * segments is not programmed correctly in TPA and the
4127 * 33 total aggregation buffers allowed for the TPA
4128 * operation has been exceeded.
4130 #define RX_TPA_V2_END_CMPL_ERRORS_BUFFER_ERROR_RSV_ERROR \
4131 (UINT32_C(0x4) << 1)
4134 * There was a bad_format error on the previous operation
4136 #define RX_TPA_V2_END_CMPL_ERRORS_BUFFER_ERROR_FLUSH \
4137 (UINT32_C(0x5) << 1)
4138 #define RX_TPA_V2_END_CMPL_ERRORS_BUFFER_ERROR_LAST \
4139 RX_TPA_V2_END_CMPL_ERRORS_BUFFER_ERROR_FLUSH
4142 * This is the opaque value that was completed for the TPA start
4143 * completion that corresponds to this TPA end completion.
4145 uint32_t start_opaque;
4149 * This TPA completion structure is used on devices where the
4150 * `hwrm_vnic_qcaps.max_aggs_supported` value is greater than 0.
4152 /* rx_tpa_v2_abuf_cmpl (size:128b/16B) */
4153 struct rx_tpa_v2_abuf_cmpl {
4156 * This field indicates the exact type of the completion.
4157 * By convention, the LSB identifies the length of the
4158 * record in 16B units. Even values indicate 16B
4159 * records. Odd values indicate 32B
4162 #define RX_TPA_V2_ABUF_CMPL_TYPE_MASK UINT32_C(0x3f)
4163 #define RX_TPA_V2_ABUF_CMPL_TYPE_SFT 0
4165 * RX TPA Aggregation Buffer completion :
4166 * Completion of an L2 aggregation buffer in support of
4167 * TPA packet completion. Length = 16B
4169 #define RX_TPA_V2_ABUF_CMPL_TYPE_RX_TPA_AGG UINT32_C(0x16)
4170 #define RX_TPA_V2_ABUF_CMPL_TYPE_LAST \
4171 RX_TPA_V2_ABUF_CMPL_TYPE_RX_TPA_AGG
4173 * This is the length of the data for the packet stored in this
4174 * aggregation buffer identified by the opaque value. This does not
4175 * include the length of any
4176 * data placed in other aggregation BDs or in the packet or buffer
4177 * BDs. This length does not include any space added due to
4178 * hdr_offset register during HDS placement mode.
4182 * This is a copy of the opaque field from the RX BD this aggregation
4183 * buffer corresponds to.
4188 * This value is written by the NIC such that it will be different
4189 * for each pass through the completion queue. The even passes
4190 * will write 1. The odd passes will write 0.
4192 #define RX_TPA_V2_ABUF_CMPL_V UINT32_C(0x1)
4194 * This is the aggregation ID that the completion is associated with. Use
4195 * this number to correlate the TPA agg completion with the TPA start
4196 * completion and the TPA end completion.
4202 /* rx_abuf_cmpl (size:128b/16B) */
4203 struct rx_abuf_cmpl {
4206 * This field indicates the exact type of the completion.
4207 * By convention, the LSB identifies the length of the
4208 * record in 16B units. Even values indicate 16B
4209 * records. Odd values indicate 32B
4212 #define RX_ABUF_CMPL_TYPE_MASK UINT32_C(0x3f)
4213 #define RX_ABUF_CMPL_TYPE_SFT 0
4215 * RX Aggregation Buffer completion :
4216 * Completion of an L2 aggregation buffer in support of
4217 * TPA, HDS, or Jumbo packet completion. Length = 16B
4219 #define RX_ABUF_CMPL_TYPE_RX_AGG UINT32_C(0x12)
4220 #define RX_ABUF_CMPL_TYPE_LAST RX_ABUF_CMPL_TYPE_RX_AGG
4222 * This is the length of the data for the packet stored in this
4223 * aggregation buffer identified by the opaque value. This does not
4224 * include the length of any
4225 * data placed in other aggregation BDs or in the packet or buffer
4226 * BDs. This length does not include any space added due to
4227 * hdr_offset register during HDS placement mode.
4231 * This is a copy of the opaque field from the RX BD this aggregation
4232 * buffer corresponds to.
4237 * This value is written by the NIC such that it will be different
4238 * for each pass through the completion queue. The even passes
4239 * will write 1. The odd passes will write 0.
4241 #define RX_ABUF_CMPL_V UINT32_C(0x1)
4242 /* unused3 is 32 b */
4246 /* eject_cmpl (size:128b/16B) */
4250 * This field indicates the exact type of the completion.
4251 * By convention, the LSB identifies the length of the
4252 * record in 16B units. Even values indicate 16B
4253 * records. Odd values indicate 32B
4256 #define EJECT_CMPL_TYPE_MASK UINT32_C(0x3f)
4257 #define EJECT_CMPL_TYPE_SFT 0
4259 * Statistics Ejection Completion:
4260 * Completion of statistics data ejection buffer.
4263 #define EJECT_CMPL_TYPE_STAT_EJECT UINT32_C(0x1a)
4264 #define EJECT_CMPL_TYPE_LAST EJECT_CMPL_TYPE_STAT_EJECT
4265 #define EJECT_CMPL_FLAGS_MASK UINT32_C(0xffc0)
4266 #define EJECT_CMPL_FLAGS_SFT 6
4268 * When this bit is '1', it indicates a packet that has an
4269 * error of some type. Type of error is indicated in
4272 #define EJECT_CMPL_FLAGS_ERROR UINT32_C(0x40)
4274 * This is the length of the statistics data stored in this
4279 * This is a copy of the opaque field from the RX BD this ejection
4280 * buffer corresponds to.
4285 * This value is written by the NIC such that it will be different
4286 * for each pass through the completion queue. The even passes
4287 * will write 1. The odd passes will write 0.
4289 #define EJECT_CMPL_V UINT32_C(0x1)
4290 #define EJECT_CMPL_ERRORS_MASK UINT32_C(0xfffe)
4291 #define EJECT_CMPL_ERRORS_SFT 1
4293 * This error indicates that there was some sort of problem with
4294 * the BDs for statistics ejection. The statistics ejection should
4295 * be treated as invalid
4297 #define EJECT_CMPL_ERRORS_BUFFER_ERROR_MASK UINT32_C(0xe)
4298 #define EJECT_CMPL_ERRORS_BUFFER_ERROR_SFT 1
4299 /* No buffer error */
4300 #define EJECT_CMPL_ERRORS_BUFFER_ERROR_NO_BUFFER \
4301 (UINT32_C(0x0) << 1)
4304 * Statistics did not fit into aggregation buffer provided.
4306 #define EJECT_CMPL_ERRORS_BUFFER_ERROR_DID_NOT_FIT \
4307 (UINT32_C(0x1) << 1)
4310 * BDs were not formatted correctly.
4312 #define EJECT_CMPL_ERRORS_BUFFER_ERROR_BAD_FORMAT \
4313 (UINT32_C(0x3) << 1)
4316 * There was a bad_format error on the previous operation
4318 #define EJECT_CMPL_ERRORS_BUFFER_ERROR_FLUSH \
4319 (UINT32_C(0x5) << 1)
4320 #define EJECT_CMPL_ERRORS_BUFFER_ERROR_LAST \
4321 EJECT_CMPL_ERRORS_BUFFER_ERROR_FLUSH
4322 /* reserved16 is 16 b */
4323 uint16_t reserved16;
4324 /* unused3 is 32 b */
4328 /* hwrm_cmpl (size:128b/16B) */
4332 * This field indicates the exact type of the completion.
4333 * By convention, the LSB identifies the length of the
4334 * record in 16B units. Even values indicate 16B
4335 * records. Odd values indicate 32B
4338 #define HWRM_CMPL_TYPE_MASK UINT32_C(0x3f)
4339 #define HWRM_CMPL_TYPE_SFT 0
4341 * HWRM Command Completion:
4342 * Completion of an HWRM command.
4344 #define HWRM_CMPL_TYPE_HWRM_DONE UINT32_C(0x20)
4345 #define HWRM_CMPL_TYPE_LAST HWRM_CMPL_TYPE_HWRM_DONE
4346 /* This is the sequence_id of the HWRM command that has completed. */
4347 uint16_t sequence_id;
4348 /* unused2 is 32 b */
4352 * This value is written by the NIC such that it will be different
4353 * for each pass through the completion queue. The even passes
4354 * will write 1. The odd passes will write 0.
4356 #define HWRM_CMPL_V UINT32_C(0x1)
4357 /* unused4 is 32 b */
4361 /* hwrm_fwd_req_cmpl (size:128b/16B) */
4362 struct hwrm_fwd_req_cmpl {
4364 * This field indicates the exact type of the completion.
4365 * By convention, the LSB identifies the length of the
4366 * record in 16B units. Even values indicate 16B
4367 * records. Odd values indicate 32B
4370 uint16_t req_len_type;
4372 * This field indicates the exact type of the completion.
4373 * By convention, the LSB identifies the length of the
4374 * record in 16B units. Even values indicate 16B
4375 * records. Odd values indicate 32B
4378 #define HWRM_FWD_REQ_CMPL_TYPE_MASK UINT32_C(0x3f)
4379 #define HWRM_FWD_REQ_CMPL_TYPE_SFT 0
4380 /* Forwarded HWRM Request */
4381 #define HWRM_FWD_REQ_CMPL_TYPE_HWRM_FWD_REQ UINT32_C(0x22)
4382 #define HWRM_FWD_REQ_CMPL_TYPE_LAST \
4383 HWRM_FWD_REQ_CMPL_TYPE_HWRM_FWD_REQ
4384 /* Length of forwarded request in bytes. */
4385 #define HWRM_FWD_REQ_CMPL_REQ_LEN_MASK UINT32_C(0xffc0)
4386 #define HWRM_FWD_REQ_CMPL_REQ_LEN_SFT 6
4388 * Source ID of this request.
4389 * Typically used in forwarding requests and responses.
4390 * 0x0 - 0xFFF8 - Used for function ids
4391 * 0xFFF8 - 0xFFFE - Reserved for internal processors
4395 /* unused1 is 32 b */
4397 /* Address of forwarded request. */
4398 uint32_t req_buf_addr_v[2];
4400 * This value is written by the NIC such that it will be different
4401 * for each pass through the completion queue. The even passes
4402 * will write 1. The odd passes will write 0.
4404 #define HWRM_FWD_REQ_CMPL_V UINT32_C(0x1)
4405 /* Address of forwarded request. */
4406 #define HWRM_FWD_REQ_CMPL_REQ_BUF_ADDR_MASK UINT32_C(0xfffffffe)
4407 #define HWRM_FWD_REQ_CMPL_REQ_BUF_ADDR_SFT 1
4410 /* hwrm_fwd_resp_cmpl (size:128b/16B) */
4411 struct hwrm_fwd_resp_cmpl {
4414 * This field indicates the exact type of the completion.
4415 * By convention, the LSB identifies the length of the
4416 * record in 16B units. Even values indicate 16B
4417 * records. Odd values indicate 32B
4420 #define HWRM_FWD_RESP_CMPL_TYPE_MASK UINT32_C(0x3f)
4421 #define HWRM_FWD_RESP_CMPL_TYPE_SFT 0
4422 /* Forwarded HWRM Response */
4423 #define HWRM_FWD_RESP_CMPL_TYPE_HWRM_FWD_RESP UINT32_C(0x24)
4424 #define HWRM_FWD_RESP_CMPL_TYPE_LAST \
4425 HWRM_FWD_RESP_CMPL_TYPE_HWRM_FWD_RESP
4427 * Source ID of this response.
4428 * Typically used in forwarding requests and responses.
4429 * 0x0 - 0xFFF8 - Used for function ids
4430 * 0xFFF8 - 0xFFFE - Reserved for internal processors
4434 /* Length of forwarded response in bytes. */
4436 /* unused2 is 16 b */
4438 /* Address of forwarded request. */
4439 uint32_t resp_buf_addr_v[2];
4441 * This value is written by the NIC such that it will be different
4442 * for each pass through the completion queue. The even passes
4443 * will write 1. The odd passes will write 0.
4445 #define HWRM_FWD_RESP_CMPL_V UINT32_C(0x1)
4446 /* Address of forwarded request. */
4447 #define HWRM_FWD_RESP_CMPL_RESP_BUF_ADDR_MASK UINT32_C(0xfffffffe)
4448 #define HWRM_FWD_RESP_CMPL_RESP_BUF_ADDR_SFT 1
4451 /* hwrm_async_event_cmpl (size:128b/16B) */
4452 struct hwrm_async_event_cmpl {
4455 * This field indicates the exact type of the completion.
4456 * By convention, the LSB identifies the length of the
4457 * record in 16B units. Even values indicate 16B
4458 * records. Odd values indicate 32B
4461 #define HWRM_ASYNC_EVENT_CMPL_TYPE_MASK UINT32_C(0x3f)
4462 #define HWRM_ASYNC_EVENT_CMPL_TYPE_SFT 0
4463 /* HWRM Asynchronous Event Information */
4464 #define HWRM_ASYNC_EVENT_CMPL_TYPE_HWRM_ASYNC_EVENT UINT32_C(0x2e)
4465 #define HWRM_ASYNC_EVENT_CMPL_TYPE_LAST \
4466 HWRM_ASYNC_EVENT_CMPL_TYPE_HWRM_ASYNC_EVENT
4467 /* Identifiers of events. */
4469 /* Link status changed */
4470 #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_LINK_STATUS_CHANGE \
4472 /* Link MTU changed */
4473 #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_LINK_MTU_CHANGE \
4475 /* Link speed changed */
4476 #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_LINK_SPEED_CHANGE \
4478 /* DCB Configuration changed */
4479 #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_DCB_CONFIG_CHANGE \
4481 /* Port connection not allowed */
4482 #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_PORT_CONN_NOT_ALLOWED \
4484 /* Link speed configuration was not allowed */
4485 #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_LINK_SPEED_CFG_NOT_ALLOWED \
4487 /* Link speed configuration change */
4488 #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_LINK_SPEED_CFG_CHANGE \
4490 /* Port PHY configuration change */
4491 #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_PORT_PHY_CFG_CHANGE \
4493 /* Reset notification to clients */
4494 #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_RESET_NOTIFY \
4496 /* Master function selection event */
4497 #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_ERROR_RECOVERY \
4499 /* Function driver unloaded */
4500 #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_FUNC_DRVR_UNLOAD \
4502 /* Function driver loaded */
4503 #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_FUNC_DRVR_LOAD \
4505 /* Function FLR related processing has completed */
4506 #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_FUNC_FLR_PROC_CMPLT \
4508 /* PF driver unloaded */
4509 #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_PF_DRVR_UNLOAD \
4511 /* PF driver loaded */
4512 #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_PF_DRVR_LOAD \
4514 /* VF Function Level Reset (FLR) */
4515 #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_VF_FLR \
4517 /* VF MAC Address Change */
4518 #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_VF_MAC_ADDR_CHANGE \
4520 /* PF-VF communication channel status change. */
4521 #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_PF_VF_COMM_STATUS_CHANGE \
4523 /* VF Configuration Change */
4524 #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_VF_CFG_CHANGE \
4526 /* LLFC/PFC Configuration Change */
4527 #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_LLFC_PFC_CHANGE \
4529 /* Default VNIC Configuration Change */
4530 #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_DEFAULT_VNIC_CHANGE \
4533 #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_HW_FLOW_AGED \
4536 * A debug notification being posted to the driver. These
4537 * notifications are purely for diagnostic purpose and should not be
4538 * used for functional purpose. The driver is not supposed to act
4539 * on these messages except to log/record it.
4541 #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_DEBUG_NOTIFICATION \
4544 * An EEM flow cached memory flush for all flows request event being
4545 * posted to the PF driver.
4547 #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_EEM_CACHE_FLUSH_REQ \
4550 * An EEM flow cache memory flush completion event being posted to the
4551 * firmware by the PF driver. This is indication that host EEM flush
4552 * has completed by the PF.
4554 #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_EEM_CACHE_FLUSH_DONE \
4557 * A tcp flag action change event being posted to the PF or trusted VF
4558 * driver by the firmware. The PF or trusted VF driver should query
4559 * the firmware for the new TCP flag action update after receiving
4562 #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_TCP_FLAG_ACTION_CHANGE \
4565 * An EEM flow active event being posted to the PF or trusted VF driver
4566 * by the firmware. The PF or trusted VF driver should update the
4567 * flow's aging timer after receiving this async event.
4569 #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_EEM_FLOW_ACTIVE \
4572 * A eem cfg change event being posted to the trusted VF driver by the
4573 * firmware if the parent PF EEM configuration changed.
4575 #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_EEM_CFG_CHANGE \
4579 * TFLIB unique default VNIC Configuration Change
4581 #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_TFLIB_DEFAULT_VNIC_CHANGE \
4585 * TFLIB unique link status changed
4587 #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_TFLIB_LINK_STATUS_CHANGE \
4590 * An event signifying completion for HWRM_FW_STATE_QUIESCE
4591 * (completion, timeout, or error)
4593 #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_QUIESCE_DONE \
4596 * An event signifying a HWRM command is in progress and its
4597 * response will be deferred. This event is used on crypto controllers
4600 #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_DEFERRED_RESPONSE \
4603 * An event signifying that a PFC WatchDog configuration
4604 * has changed on any port / cos.
4606 #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_PFC_WATCHDOG_CFG_CHANGE \
4609 * A trace log message. This contains firmware trace logs string
4610 * embedded in the asynchronous message. This is an experimental
4611 * event, not meant for production use at this time.
4613 #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_FW_TRACE_MSG \
4616 #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_HWRM_ERROR \
4618 #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_LAST \
4619 HWRM_ASYNC_EVENT_CMPL_EVENT_ID_HWRM_ERROR
4620 /* Event specific data */
4621 uint32_t event_data2;
4624 * This value is written by the NIC such that it will be different
4625 * for each pass through the completion queue. The even passes
4626 * will write 1. The odd passes will write 0.
4628 #define HWRM_ASYNC_EVENT_CMPL_V UINT32_C(0x1)
4630 #define HWRM_ASYNC_EVENT_CMPL_OPAQUE_MASK UINT32_C(0xfe)
4631 #define HWRM_ASYNC_EVENT_CMPL_OPAQUE_SFT 1
4632 /* 8-lsb timestamp from POR (100-msec resolution) */
4633 uint8_t timestamp_lo;
4634 /* 16-lsb timestamp from POR (100-msec resolution) */
4635 uint16_t timestamp_hi;
4636 /* Event specific data */
4637 uint32_t event_data1;
4640 /* hwrm_async_event_cmpl_link_status_change (size:128b/16B) */
4641 struct hwrm_async_event_cmpl_link_status_change {
4644 * This field indicates the exact type of the completion.
4645 * By convention, the LSB identifies the length of the
4646 * record in 16B units. Even values indicate 16B
4647 * records. Odd values indicate 32B
4650 #define HWRM_ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_TYPE_MASK \
4652 #define HWRM_ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_TYPE_SFT 0
4653 /* HWRM Asynchronous Event Information */
4654 #define HWRM_ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_TYPE_HWRM_ASYNC_EVENT \
4656 #define HWRM_ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_TYPE_LAST \
4657 HWRM_ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_TYPE_HWRM_ASYNC_EVENT
4658 /* Identifiers of events. */
4660 /* Link status changed */
4661 #define HWRM_ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_ID_LINK_STATUS_CHANGE \
4663 #define HWRM_ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_ID_LAST \
4664 HWRM_ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_ID_LINK_STATUS_CHANGE
4665 /* Event specific data */
4666 uint32_t event_data2;
4669 * This value is written by the NIC such that it will be different
4670 * for each pass through the completion queue. The even passes
4671 * will write 1. The odd passes will write 0.
4673 #define HWRM_ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_V \
4676 #define HWRM_ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_OPAQUE_MASK \
4678 #define HWRM_ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_OPAQUE_SFT 1
4679 /* 8-lsb timestamp from POR (100-msec resolution) */
4680 uint8_t timestamp_lo;
4681 /* 16-lsb timestamp from POR (100-msec resolution) */
4682 uint16_t timestamp_hi;
4683 /* Event specific data */
4684 uint32_t event_data1;
4685 /* Indicates link status change */
4686 #define HWRM_ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_DATA1_LINK_CHANGE \
4689 * If this bit set to 0, then it indicates that the link
4690 * was up and it went down.
4692 #define HWRM_ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_DATA1_LINK_CHANGE_DOWN \
4695 * If this bit is set to 1, then it indicates that the link
4696 * was down and it went up.
4698 #define HWRM_ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_DATA1_LINK_CHANGE_UP \
4700 #define HWRM_ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_DATA1_LINK_CHANGE_LAST \
4701 HWRM_ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_DATA1_LINK_CHANGE_UP
4702 /* Indicates the physical port this link status change occur */
4703 #define HWRM_ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_DATA1_PORT_MASK \
4705 #define HWRM_ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_DATA1_PORT_SFT \
4708 #define HWRM_ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_DATA1_PORT_ID_MASK \
4710 #define HWRM_ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_DATA1_PORT_ID_SFT \
4712 /* Indicates the physical function this event occurred on. */
4713 #define HWRM_ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_DATA1_PF_ID_MASK \
4715 #define HWRM_ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_DATA1_PF_ID_SFT \
4719 /* hwrm_async_event_cmpl_link_mtu_change (size:128b/16B) */
4720 struct hwrm_async_event_cmpl_link_mtu_change {
4723 * This field indicates the exact type of the completion.
4724 * By convention, the LSB identifies the length of the
4725 * record in 16B units. Even values indicate 16B
4726 * records. Odd values indicate 32B
4729 #define HWRM_ASYNC_EVENT_CMPL_LINK_MTU_CHANGE_TYPE_MASK \
4731 #define HWRM_ASYNC_EVENT_CMPL_LINK_MTU_CHANGE_TYPE_SFT 0
4732 /* HWRM Asynchronous Event Information */
4733 #define HWRM_ASYNC_EVENT_CMPL_LINK_MTU_CHANGE_TYPE_HWRM_ASYNC_EVENT \
4735 #define HWRM_ASYNC_EVENT_CMPL_LINK_MTU_CHANGE_TYPE_LAST \
4736 HWRM_ASYNC_EVENT_CMPL_LINK_MTU_CHANGE_TYPE_HWRM_ASYNC_EVENT
4737 /* Identifiers of events. */
4739 /* Link MTU changed */
4740 #define HWRM_ASYNC_EVENT_CMPL_LINK_MTU_CHANGE_EVENT_ID_LINK_MTU_CHANGE \
4742 #define HWRM_ASYNC_EVENT_CMPL_LINK_MTU_CHANGE_EVENT_ID_LAST \
4743 HWRM_ASYNC_EVENT_CMPL_LINK_MTU_CHANGE_EVENT_ID_LINK_MTU_CHANGE
4744 /* Event specific data */
4745 uint32_t event_data2;
4748 * This value is written by the NIC such that it will be different
4749 * for each pass through the completion queue. The even passes
4750 * will write 1. The odd passes will write 0.
4752 #define HWRM_ASYNC_EVENT_CMPL_LINK_MTU_CHANGE_V UINT32_C(0x1)
4754 #define HWRM_ASYNC_EVENT_CMPL_LINK_MTU_CHANGE_OPAQUE_MASK \
4756 #define HWRM_ASYNC_EVENT_CMPL_LINK_MTU_CHANGE_OPAQUE_SFT 1
4757 /* 8-lsb timestamp from POR (100-msec resolution) */
4758 uint8_t timestamp_lo;
4759 /* 16-lsb timestamp from POR (100-msec resolution) */
4760 uint16_t timestamp_hi;
4761 /* Event specific data */
4762 uint32_t event_data1;
4763 /* The new MTU of the link in bytes. */
4764 #define HWRM_ASYNC_EVENT_CMPL_LINK_MTU_CHANGE_EVENT_DATA1_NEW_MTU_MASK \
4766 #define HWRM_ASYNC_EVENT_CMPL_LINK_MTU_CHANGE_EVENT_DATA1_NEW_MTU_SFT 0
4769 /* hwrm_async_event_cmpl_link_speed_change (size:128b/16B) */
4770 struct hwrm_async_event_cmpl_link_speed_change {
4773 * This field indicates the exact type of the completion.
4774 * By convention, the LSB identifies the length of the
4775 * record in 16B units. Even values indicate 16B
4776 * records. Odd values indicate 32B
4779 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_TYPE_MASK \
4781 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_TYPE_SFT 0
4782 /* HWRM Asynchronous Event Information */
4783 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_TYPE_HWRM_ASYNC_EVENT \
4785 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_TYPE_LAST \
4786 HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_TYPE_HWRM_ASYNC_EVENT
4787 /* Identifiers of events. */
4789 /* Link speed changed */
4790 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_EVENT_ID_LINK_SPEED_CHANGE \
4792 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_EVENT_ID_LAST \
4793 HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_EVENT_ID_LINK_SPEED_CHANGE
4794 /* Event specific data */
4795 uint32_t event_data2;
4798 * This value is written by the NIC such that it will be different
4799 * for each pass through the completion queue. The even passes
4800 * will write 1. The odd passes will write 0.
4802 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_V \
4805 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_OPAQUE_MASK \
4807 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_OPAQUE_SFT 1
4808 /* 8-lsb timestamp from POR (100-msec resolution) */
4809 uint8_t timestamp_lo;
4810 /* 16-lsb timestamp from POR (100-msec resolution) */
4811 uint16_t timestamp_hi;
4812 /* Event specific data */
4813 uint32_t event_data1;
4815 * When this bit is '1', the link was forced to the
4816 * force_link_speed value.
4818 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_EVENT_DATA1_FORCE \
4820 /* The new link speed in 100 Mbps units. */
4821 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_EVENT_DATA1_NEW_LINK_SPEED_100MBPS_MASK \
4823 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_EVENT_DATA1_NEW_LINK_SPEED_100MBPS_SFT \
4825 /* 100Mb link speed */
4826 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_EVENT_DATA1_NEW_LINK_SPEED_100MBPS_100MB \
4827 (UINT32_C(0x1) << 1)
4828 /* 1Gb link speed */
4829 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_EVENT_DATA1_NEW_LINK_SPEED_100MBPS_1GB \
4830 (UINT32_C(0xa) << 1)
4831 /* 2Gb link speed */
4832 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_EVENT_DATA1_NEW_LINK_SPEED_100MBPS_2GB \
4833 (UINT32_C(0x14) << 1)
4834 /* 25Gb link speed */
4835 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_EVENT_DATA1_NEW_LINK_SPEED_100MBPS_2_5GB \
4836 (UINT32_C(0x19) << 1)
4837 /* 10Gb link speed */
4838 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_EVENT_DATA1_NEW_LINK_SPEED_100MBPS_10GB \
4839 (UINT32_C(0x64) << 1)
4840 /* 20Mb link speed */
4841 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_EVENT_DATA1_NEW_LINK_SPEED_100MBPS_20GB \
4842 (UINT32_C(0xc8) << 1)
4843 /* 25Gb link speed */
4844 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_EVENT_DATA1_NEW_LINK_SPEED_100MBPS_25GB \
4845 (UINT32_C(0xfa) << 1)
4846 /* 40Gb link speed */
4847 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_EVENT_DATA1_NEW_LINK_SPEED_100MBPS_40GB \
4848 (UINT32_C(0x190) << 1)
4849 /* 50Gb link speed */
4850 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_EVENT_DATA1_NEW_LINK_SPEED_100MBPS_50GB \
4851 (UINT32_C(0x1f4) << 1)
4852 /* 100Gb link speed */
4853 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_EVENT_DATA1_NEW_LINK_SPEED_100MBPS_100GB \
4854 (UINT32_C(0x3e8) << 1)
4855 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_EVENT_DATA1_NEW_LINK_SPEED_100MBPS_LAST \
4856 HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_EVENT_DATA1_NEW_LINK_SPEED_100MBPS_100GB
4858 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_EVENT_DATA1_PORT_ID_MASK \
4859 UINT32_C(0xffff0000)
4860 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_EVENT_DATA1_PORT_ID_SFT \
4864 /* hwrm_async_event_cmpl_dcb_config_change (size:128b/16B) */
4865 struct hwrm_async_event_cmpl_dcb_config_change {
4868 * This field indicates the exact type of the completion.
4869 * By convention, the LSB identifies the length of the
4870 * record in 16B units. Even values indicate 16B
4871 * records. Odd values indicate 32B
4874 #define HWRM_ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_TYPE_MASK \
4876 #define HWRM_ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_TYPE_SFT 0
4877 /* HWRM Asynchronous Event Information */
4878 #define HWRM_ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_TYPE_HWRM_ASYNC_EVENT \
4880 #define HWRM_ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_TYPE_LAST \
4881 HWRM_ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_TYPE_HWRM_ASYNC_EVENT
4882 /* Identifiers of events. */
4884 /* DCB Configuration changed */
4885 #define HWRM_ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_EVENT_ID_DCB_CONFIG_CHANGE \
4887 #define HWRM_ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_EVENT_ID_LAST \
4888 HWRM_ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_EVENT_ID_DCB_CONFIG_CHANGE
4889 /* Event specific data */
4890 uint32_t event_data2;
4891 /* ETS configuration change */
4892 #define HWRM_ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_EVENT_DATA2_ETS \
4894 /* PFC configuration change */
4895 #define HWRM_ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_EVENT_DATA2_PFC \
4897 /* APP configuration change */
4898 #define HWRM_ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_EVENT_DATA2_APP \
4902 * This value is written by the NIC such that it will be different
4903 * for each pass through the completion queue. The even passes
4904 * will write 1. The odd passes will write 0.
4906 #define HWRM_ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_V \
4909 #define HWRM_ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_OPAQUE_MASK \
4911 #define HWRM_ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_OPAQUE_SFT 1
4912 /* 8-lsb timestamp from POR (100-msec resolution) */
4913 uint8_t timestamp_lo;
4914 /* 16-lsb timestamp from POR (100-msec resolution) */
4915 uint16_t timestamp_hi;
4916 /* Event specific data */
4917 uint32_t event_data1;
4919 #define HWRM_ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_EVENT_DATA1_PORT_ID_MASK \
4921 #define HWRM_ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_EVENT_DATA1_PORT_ID_SFT \
4923 /* Priority recommended for RoCE traffic */
4924 #define HWRM_ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_EVENT_DATA1_RECOMMEND_ROCE_PRIORITY_MASK \
4926 #define HWRM_ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_EVENT_DATA1_RECOMMEND_ROCE_PRIORITY_SFT \
4929 #define HWRM_ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_EVENT_DATA1_RECOMMEND_ROCE_PRIORITY_NONE \
4930 (UINT32_C(0xff) << 16)
4931 #define HWRM_ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_EVENT_DATA1_RECOMMEND_ROCE_PRIORITY_LAST \
4932 HWRM_ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_EVENT_DATA1_RECOMMEND_ROCE_PRIORITY_NONE
4933 /* Priority recommended for L2 traffic */
4934 #define HWRM_ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_EVENT_DATA1_RECOMMEND_L2_PRIORITY_MASK \
4935 UINT32_C(0xff000000)
4936 #define HWRM_ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_EVENT_DATA1_RECOMMEND_L2_PRIORITY_SFT \
4939 #define HWRM_ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_EVENT_DATA1_RECOMMEND_L2_PRIORITY_NONE \
4940 (UINT32_C(0xff) << 24)
4941 #define HWRM_ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_EVENT_DATA1_RECOMMEND_L2_PRIORITY_LAST \
4942 HWRM_ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_EVENT_DATA1_RECOMMEND_L2_PRIORITY_NONE
4945 /* hwrm_async_event_cmpl_port_conn_not_allowed (size:128b/16B) */
4946 struct hwrm_async_event_cmpl_port_conn_not_allowed {
4949 * This field indicates the exact type of the completion.
4950 * By convention, the LSB identifies the length of the
4951 * record in 16B units. Even values indicate 16B
4952 * records. Odd values indicate 32B
4955 #define HWRM_ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_TYPE_MASK \
4957 #define HWRM_ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_TYPE_SFT \
4959 /* HWRM Asynchronous Event Information */
4960 #define HWRM_ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_TYPE_HWRM_ASYNC_EVENT \
4962 #define HWRM_ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_TYPE_LAST \
4963 HWRM_ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_TYPE_HWRM_ASYNC_EVENT
4964 /* Identifiers of events. */
4966 /* Port connection not allowed */
4967 #define HWRM_ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_ID_PORT_CONN_NOT_ALLOWED \
4969 #define HWRM_ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_ID_LAST \
4970 HWRM_ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_ID_PORT_CONN_NOT_ALLOWED
4971 /* Event specific data */
4972 uint32_t event_data2;
4975 * This value is written by the NIC such that it will be different
4976 * for each pass through the completion queue. The even passes
4977 * will write 1. The odd passes will write 0.
4979 #define HWRM_ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_V \
4982 #define HWRM_ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_OPAQUE_MASK \
4984 #define HWRM_ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_OPAQUE_SFT 1
4985 /* 8-lsb timestamp from POR (100-msec resolution) */
4986 uint8_t timestamp_lo;
4987 /* 16-lsb timestamp from POR (100-msec resolution) */
4988 uint16_t timestamp_hi;
4989 /* Event specific data */
4990 uint32_t event_data1;
4992 #define HWRM_ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_PORT_ID_MASK \
4994 #define HWRM_ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_PORT_ID_SFT \
4997 * This value indicates the current port level enforcement policy
4998 * for the optics module when there is an optical module mismatch
4999 * and port is not connected.
5001 #define HWRM_ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_ENFORCEMENT_POLICY_MASK \
5003 #define HWRM_ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_ENFORCEMENT_POLICY_SFT \
5005 /* No enforcement */
5006 #define HWRM_ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_ENFORCEMENT_POLICY_NONE \
5007 (UINT32_C(0x0) << 16)
5008 /* Disable Transmit side Laser. */
5009 #define HWRM_ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_ENFORCEMENT_POLICY_DISABLETX \
5010 (UINT32_C(0x1) << 16)
5011 /* Raise a warning message. */
5012 #define HWRM_ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_ENFORCEMENT_POLICY_WARNINGMSG \
5013 (UINT32_C(0x2) << 16)
5014 /* Power down the module. */
5015 #define HWRM_ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_ENFORCEMENT_POLICY_PWRDOWN \
5016 (UINT32_C(0x3) << 16)
5017 #define HWRM_ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_ENFORCEMENT_POLICY_LAST \
5018 HWRM_ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_ENFORCEMENT_POLICY_PWRDOWN
5021 /* hwrm_async_event_cmpl_link_speed_cfg_not_allowed (size:128b/16B) */
5022 struct hwrm_async_event_cmpl_link_speed_cfg_not_allowed {
5025 * This field indicates the exact type of the completion.
5026 * By convention, the LSB identifies the length of the
5027 * record in 16B units. Even values indicate 16B
5028 * records. Odd values indicate 32B
5031 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_NOT_ALLOWED_TYPE_MASK \
5033 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_NOT_ALLOWED_TYPE_SFT \
5035 /* HWRM Asynchronous Event Information */
5036 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_NOT_ALLOWED_TYPE_HWRM_ASYNC_EVENT \
5038 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_NOT_ALLOWED_TYPE_LAST \
5039 HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_NOT_ALLOWED_TYPE_HWRM_ASYNC_EVENT
5040 /* Identifiers of events. */
5042 /* Link speed configuration was not allowed */
5043 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_NOT_ALLOWED_EVENT_ID_LINK_SPEED_CFG_NOT_ALLOWED \
5045 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_NOT_ALLOWED_EVENT_ID_LAST \
5046 HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_NOT_ALLOWED_EVENT_ID_LINK_SPEED_CFG_NOT_ALLOWED
5047 /* Event specific data */
5048 uint32_t event_data2;
5051 * This value is written by the NIC such that it will be different
5052 * for each pass through the completion queue. The even passes
5053 * will write 1. The odd passes will write 0.
5055 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_NOT_ALLOWED_V \
5058 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_NOT_ALLOWED_OPAQUE_MASK \
5060 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_NOT_ALLOWED_OPAQUE_SFT 1
5061 /* 8-lsb timestamp from POR (100-msec resolution) */
5062 uint8_t timestamp_lo;
5063 /* 16-lsb timestamp from POR (100-msec resolution) */
5064 uint16_t timestamp_hi;
5065 /* Event specific data */
5066 uint32_t event_data1;
5068 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_NOT_ALLOWED_EVENT_DATA1_PORT_ID_MASK \
5070 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_NOT_ALLOWED_EVENT_DATA1_PORT_ID_SFT \
5074 /* hwrm_async_event_cmpl_link_speed_cfg_change (size:128b/16B) */
5075 struct hwrm_async_event_cmpl_link_speed_cfg_change {
5078 * This field indicates the exact type of the completion.
5079 * By convention, the LSB identifies the length of the
5080 * record in 16B units. Even values indicate 16B
5081 * records. Odd values indicate 32B
5084 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_TYPE_MASK \
5086 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_TYPE_SFT \
5088 /* HWRM Asynchronous Event Information */
5089 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_TYPE_HWRM_ASYNC_EVENT \
5091 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_TYPE_LAST \
5092 HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_TYPE_HWRM_ASYNC_EVENT
5093 /* Identifiers of events. */
5095 /* Link speed configuration change */
5096 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_EVENT_ID_LINK_SPEED_CFG_CHANGE \
5098 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_EVENT_ID_LAST \
5099 HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_EVENT_ID_LINK_SPEED_CFG_CHANGE
5100 /* Event specific data */
5101 uint32_t event_data2;
5104 * This value is written by the NIC such that it will be different
5105 * for each pass through the completion queue. The even passes
5106 * will write 1. The odd passes will write 0.
5108 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_V \
5111 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_OPAQUE_MASK \
5113 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_OPAQUE_SFT 1
5114 /* 8-lsb timestamp from POR (100-msec resolution) */
5115 uint8_t timestamp_lo;
5116 /* 16-lsb timestamp from POR (100-msec resolution) */
5117 uint16_t timestamp_hi;
5118 /* Event specific data */
5119 uint32_t event_data1;
5121 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_EVENT_DATA1_PORT_ID_MASK \
5123 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_EVENT_DATA1_PORT_ID_SFT \
5126 * If set to 1, it indicates that the supported link speeds
5127 * configuration on the port has changed.
5128 * If set to 0, then there is no change in supported link speeds
5131 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_EVENT_DATA1_SUPPORTED_LINK_SPEEDS_CHANGE \
5134 * If set to 1, it indicates that the link speed configuration
5135 * on the port has become illegal or invalid.
5136 * If set to 0, then the link speed configuration on the port is
5139 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_EVENT_DATA1_ILLEGAL_LINK_SPEED_CFG \
5143 /* hwrm_async_event_cmpl_port_phy_cfg_change (size:128b/16B) */
5144 struct hwrm_async_event_cmpl_port_phy_cfg_change {
5147 * This field indicates the exact type of the completion.
5148 * By convention, the LSB identifies the length of the
5149 * record in 16B units. Even values indicate 16B
5150 * records. Odd values indicate 32B
5153 #define HWRM_ASYNC_EVENT_CMPL_PORT_PHY_CFG_CHANGE_TYPE_MASK \
5155 #define HWRM_ASYNC_EVENT_CMPL_PORT_PHY_CFG_CHANGE_TYPE_SFT \
5157 /* HWRM Asynchronous Event Information */
5158 #define HWRM_ASYNC_EVENT_CMPL_PORT_PHY_CFG_CHANGE_TYPE_HWRM_ASYNC_EVENT \
5160 #define HWRM_ASYNC_EVENT_CMPL_PORT_PHY_CFG_CHANGE_TYPE_LAST \
5161 HWRM_ASYNC_EVENT_CMPL_PORT_PHY_CFG_CHANGE_TYPE_HWRM_ASYNC_EVENT
5162 /* Identifiers of events. */
5164 /* Port PHY configuration change */
5165 #define HWRM_ASYNC_EVENT_CMPL_PORT_PHY_CFG_CHANGE_EVENT_ID_PORT_PHY_CFG_CHANGE \
5167 #define HWRM_ASYNC_EVENT_CMPL_PORT_PHY_CFG_CHANGE_EVENT_ID_LAST \
5168 HWRM_ASYNC_EVENT_CMPL_PORT_PHY_CFG_CHANGE_EVENT_ID_PORT_PHY_CFG_CHANGE
5169 /* Event specific data */
5170 uint32_t event_data2;
5173 * This value is written by the NIC such that it will be different
5174 * for each pass through the completion queue. The even passes
5175 * will write 1. The odd passes will write 0.
5177 #define HWRM_ASYNC_EVENT_CMPL_PORT_PHY_CFG_CHANGE_V \
5180 #define HWRM_ASYNC_EVENT_CMPL_PORT_PHY_CFG_CHANGE_OPAQUE_MASK \
5182 #define HWRM_ASYNC_EVENT_CMPL_PORT_PHY_CFG_CHANGE_OPAQUE_SFT 1
5183 /* 8-lsb timestamp from POR (100-msec resolution) */
5184 uint8_t timestamp_lo;
5185 /* 16-lsb timestamp from POR (100-msec resolution) */
5186 uint16_t timestamp_hi;
5187 /* Event specific data */
5188 uint32_t event_data1;
5190 #define HWRM_ASYNC_EVENT_CMPL_PORT_PHY_CFG_CHANGE_EVENT_DATA1_PORT_ID_MASK \
5192 #define HWRM_ASYNC_EVENT_CMPL_PORT_PHY_CFG_CHANGE_EVENT_DATA1_PORT_ID_SFT \
5195 * If set to 1, it indicates that the FEC
5196 * configuration on the port has changed.
5197 * If set to 0, then there is no change in FEC configuration.
5199 #define HWRM_ASYNC_EVENT_CMPL_PORT_PHY_CFG_CHANGE_EVENT_DATA1_FEC_CFG_CHANGE \
5202 * If set to 1, it indicates that the EEE configuration
5203 * on the port has changed.
5204 * If set to 0, then there is no change in EEE configuration
5207 #define HWRM_ASYNC_EVENT_CMPL_PORT_PHY_CFG_CHANGE_EVENT_DATA1_EEE_CFG_CHANGE \
5210 * If set to 1, it indicates that the pause configuration
5211 * on the PHY has changed.
5212 * If set to 0, then there is no change in the pause
5213 * configuration on the PHY.
5215 #define HWRM_ASYNC_EVENT_CMPL_PORT_PHY_CFG_CHANGE_EVENT_DATA1_PAUSE_CFG_CHANGE \
5219 /* hwrm_async_event_cmpl_reset_notify (size:128b/16B) */
5220 struct hwrm_async_event_cmpl_reset_notify {
5223 * This field indicates the exact type of the completion.
5224 * By convention, the LSB identifies the length of the
5225 * record in 16B units. Even values indicate 16B
5226 * records. Odd values indicate 32B
5229 #define HWRM_ASYNC_EVENT_CMPL_RESET_NOTIFY_TYPE_MASK \
5231 #define HWRM_ASYNC_EVENT_CMPL_RESET_NOTIFY_TYPE_SFT 0
5232 /* HWRM Asynchronous Event Information */
5233 #define HWRM_ASYNC_EVENT_CMPL_RESET_NOTIFY_TYPE_HWRM_ASYNC_EVENT \
5235 #define HWRM_ASYNC_EVENT_CMPL_RESET_NOTIFY_TYPE_LAST \
5236 HWRM_ASYNC_EVENT_CMPL_RESET_NOTIFY_TYPE_HWRM_ASYNC_EVENT
5237 /* Identifiers of events. */
5239 /* Notify clients of imminent reset. */
5240 #define HWRM_ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_ID_RESET_NOTIFY \
5242 #define HWRM_ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_ID_LAST \
5243 HWRM_ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_ID_RESET_NOTIFY
5244 /* Event specific data */
5245 uint32_t event_data2;
5248 * This value is written by the NIC such that it will be different
5249 * for each pass through the completion queue. The even passes
5250 * will write 1. The odd passes will write 0.
5252 #define HWRM_ASYNC_EVENT_CMPL_RESET_NOTIFY_V UINT32_C(0x1)
5254 #define HWRM_ASYNC_EVENT_CMPL_RESET_NOTIFY_OPAQUE_MASK UINT32_C(0xfe)
5255 #define HWRM_ASYNC_EVENT_CMPL_RESET_NOTIFY_OPAQUE_SFT 1
5257 * 8-lsb timestamp (100-msec resolution)
5258 * The Minimum time required for the Firmware readiness after sending this
5259 * notification to the driver instances.
5261 uint8_t timestamp_lo;
5263 * 16-lsb timestamp (100-msec resolution)
5264 * The Maximum Firmware Reset bail out value in the order of 100
5265 * milli seconds. The driver instances will use this value to re-initiate the
5266 * registration process again if the core firmware didn’t set the ready
5269 uint16_t timestamp_hi;
5270 /* Event specific data */
5271 uint32_t event_data1;
5272 /* Indicates driver action requested */
5273 #define HWRM_ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_DRIVER_ACTION_MASK \
5275 #define HWRM_ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_DRIVER_ACTION_SFT \
5278 * If set to 1, it indicates that the l2 client should
5279 * stop sending in band traffic to Nitro.
5280 * if set to 0, there is no change in L2 client behavior.
5282 #define HWRM_ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_DRIVER_ACTION_DRIVER_STOP_TX_QUEUE \
5285 * If set to 1, it indicates that the L2 client should
5286 * bring down the interface.
5287 * If set to 0, then there is no change in L2 client behavior.
5289 #define HWRM_ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_DRIVER_ACTION_DRIVER_IFDOWN \
5291 #define HWRM_ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_DRIVER_ACTION_LAST \
5292 HWRM_ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_DRIVER_ACTION_DRIVER_IFDOWN
5293 /* Indicates reason for reset. */
5294 #define HWRM_ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_REASON_CODE_MASK \
5296 #define HWRM_ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_REASON_CODE_SFT \
5298 /* A management client has requested reset. */
5299 #define HWRM_ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_REASON_CODE_MANAGEMENT_RESET_REQUEST \
5300 (UINT32_C(0x1) << 8)
5301 /* A fatal firmware exception has occurred. */
5302 #define HWRM_ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_REASON_CODE_FW_EXCEPTION_FATAL \
5303 (UINT32_C(0x2) << 8)
5304 /* A non-fatal firmware exception has occurred. */
5305 #define HWRM_ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_REASON_CODE_FW_EXCEPTION_NON_FATAL \
5306 (UINT32_C(0x3) << 8)
5307 #define HWRM_ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_REASON_CODE_LAST \
5308 HWRM_ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_REASON_CODE_FW_EXCEPTION_NON_FATAL
5310 * Minimum time before driver should attempt access - units 100ms ticks.
5313 #define HWRM_ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_DELAY_IN_100MS_TICKS_MASK \
5314 UINT32_C(0xffff0000)
5315 #define HWRM_ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_DELAY_IN_100MS_TICKS_SFT \
5319 /* hwrm_async_event_cmpl_error_recovery (size:128b/16B) */
5320 struct hwrm_async_event_cmpl_error_recovery {
5323 * This field indicates the exact type of the completion.
5324 * By convention, the LSB identifies the length of the
5325 * record in 16B units. Even values indicate 16B
5326 * records. Odd values indicate 32B
5329 #define HWRM_ASYNC_EVENT_CMPL_ERROR_RECOVERY_TYPE_MASK \
5331 #define HWRM_ASYNC_EVENT_CMPL_ERROR_RECOVERY_TYPE_SFT 0
5332 /* HWRM Asynchronous Event Information */
5333 #define HWRM_ASYNC_EVENT_CMPL_ERROR_RECOVERY_TYPE_HWRM_ASYNC_EVENT \
5335 #define HWRM_ASYNC_EVENT_CMPL_ERROR_RECOVERY_TYPE_LAST \
5336 HWRM_ASYNC_EVENT_CMPL_ERROR_RECOVERY_TYPE_HWRM_ASYNC_EVENT
5337 /* Identifiers of events. */
5340 * This async notification message can be used for selecting or
5341 * deselecting master function for error recovery,
5342 * and to communicate to all the functions whether error recovery
5343 * was enabled/disabled.
5345 #define HWRM_ASYNC_EVENT_CMPL_ERROR_RECOVERY_EVENT_ID_ERROR_RECOVERY \
5347 #define HWRM_ASYNC_EVENT_CMPL_ERROR_RECOVERY_EVENT_ID_LAST \
5348 HWRM_ASYNC_EVENT_CMPL_ERROR_RECOVERY_EVENT_ID_ERROR_RECOVERY
5349 /* Event specific data */
5350 uint32_t event_data2;
5353 * This value is written by the NIC such that it will be different
5354 * for each pass through the completion queue. The even passes
5355 * will write 1. The odd passes will write 0.
5357 #define HWRM_ASYNC_EVENT_CMPL_ERROR_RECOVERY_V UINT32_C(0x1)
5359 #define HWRM_ASYNC_EVENT_CMPL_ERROR_RECOVERY_OPAQUE_MASK UINT32_C(0xfe)
5360 #define HWRM_ASYNC_EVENT_CMPL_ERROR_RECOVERY_OPAQUE_SFT 1
5361 /* 8-lsb timestamp (100-msec resolution) */
5362 uint8_t timestamp_lo;
5363 /* 16-lsb timestamp (100-msec resolution) */
5364 uint16_t timestamp_hi;
5365 /* Event specific data */
5366 uint32_t event_data1;
5367 /* Indicates driver action requested */
5368 #define HWRM_ASYNC_EVENT_CMPL_ERROR_RECOVERY_EVENT_DATA1_FLAGS_MASK \
5370 #define HWRM_ASYNC_EVENT_CMPL_ERROR_RECOVERY_EVENT_DATA1_FLAGS_SFT \
5373 * If set to 1, this function is selected as Master function.
5374 * This function has responsibility to do 'chip reset' when it
5375 * detects a fatal error. If set to 0, master function functionality
5376 * is disabled on this function.
5378 #define HWRM_ASYNC_EVENT_CMPL_ERROR_RECOVERY_EVENT_DATA1_FLAGS_MASTER_FUNC \
5381 * If set to 1, error recovery is enabled.
5382 * If set to 0, error recovery is disabled.
5384 #define HWRM_ASYNC_EVENT_CMPL_ERROR_RECOVERY_EVENT_DATA1_FLAGS_RECOVERY_ENABLED \
5388 /* hwrm_async_event_cmpl_func_drvr_unload (size:128b/16B) */
5389 struct hwrm_async_event_cmpl_func_drvr_unload {
5392 * This field indicates the exact type of the completion.
5393 * By convention, the LSB identifies the length of the
5394 * record in 16B units. Even values indicate 16B
5395 * records. Odd values indicate 32B
5398 #define HWRM_ASYNC_EVENT_CMPL_FUNC_DRVR_UNLOAD_TYPE_MASK \
5400 #define HWRM_ASYNC_EVENT_CMPL_FUNC_DRVR_UNLOAD_TYPE_SFT 0
5401 /* HWRM Asynchronous Event Information */
5402 #define HWRM_ASYNC_EVENT_CMPL_FUNC_DRVR_UNLOAD_TYPE_HWRM_ASYNC_EVENT \
5404 #define HWRM_ASYNC_EVENT_CMPL_FUNC_DRVR_UNLOAD_TYPE_LAST \
5405 HWRM_ASYNC_EVENT_CMPL_FUNC_DRVR_UNLOAD_TYPE_HWRM_ASYNC_EVENT
5406 /* Identifiers of events. */
5408 /* Function driver unloaded */
5409 #define HWRM_ASYNC_EVENT_CMPL_FUNC_DRVR_UNLOAD_EVENT_ID_FUNC_DRVR_UNLOAD \
5411 #define HWRM_ASYNC_EVENT_CMPL_FUNC_DRVR_UNLOAD_EVENT_ID_LAST \
5412 HWRM_ASYNC_EVENT_CMPL_FUNC_DRVR_UNLOAD_EVENT_ID_FUNC_DRVR_UNLOAD
5413 /* Event specific data */
5414 uint32_t event_data2;
5417 * This value is written by the NIC such that it will be different
5418 * for each pass through the completion queue. The even passes
5419 * will write 1. The odd passes will write 0.
5421 #define HWRM_ASYNC_EVENT_CMPL_FUNC_DRVR_UNLOAD_V UINT32_C(0x1)
5423 #define HWRM_ASYNC_EVENT_CMPL_FUNC_DRVR_UNLOAD_OPAQUE_MASK \
5425 #define HWRM_ASYNC_EVENT_CMPL_FUNC_DRVR_UNLOAD_OPAQUE_SFT 1
5426 /* 8-lsb timestamp from POR (100-msec resolution) */
5427 uint8_t timestamp_lo;
5428 /* 16-lsb timestamp from POR (100-msec resolution) */
5429 uint16_t timestamp_hi;
5430 /* Event specific data */
5431 uint32_t event_data1;
5433 #define HWRM_ASYNC_EVENT_CMPL_FUNC_DRVR_UNLOAD_EVENT_DATA1_FUNC_ID_MASK \
5435 #define HWRM_ASYNC_EVENT_CMPL_FUNC_DRVR_UNLOAD_EVENT_DATA1_FUNC_ID_SFT \
5439 /* hwrm_async_event_cmpl_func_drvr_load (size:128b/16B) */
5440 struct hwrm_async_event_cmpl_func_drvr_load {
5443 * This field indicates the exact type of the completion.
5444 * By convention, the LSB identifies the length of the
5445 * record in 16B units. Even values indicate 16B
5446 * records. Odd values indicate 32B
5449 #define HWRM_ASYNC_EVENT_CMPL_FUNC_DRVR_LOAD_TYPE_MASK \
5451 #define HWRM_ASYNC_EVENT_CMPL_FUNC_DRVR_LOAD_TYPE_SFT 0
5452 /* HWRM Asynchronous Event Information */
5453 #define HWRM_ASYNC_EVENT_CMPL_FUNC_DRVR_LOAD_TYPE_HWRM_ASYNC_EVENT \
5455 #define HWRM_ASYNC_EVENT_CMPL_FUNC_DRVR_LOAD_TYPE_LAST \
5456 HWRM_ASYNC_EVENT_CMPL_FUNC_DRVR_LOAD_TYPE_HWRM_ASYNC_EVENT
5457 /* Identifiers of events. */
5459 /* Function driver loaded */
5460 #define HWRM_ASYNC_EVENT_CMPL_FUNC_DRVR_LOAD_EVENT_ID_FUNC_DRVR_LOAD \
5462 #define HWRM_ASYNC_EVENT_CMPL_FUNC_DRVR_LOAD_EVENT_ID_LAST \
5463 HWRM_ASYNC_EVENT_CMPL_FUNC_DRVR_LOAD_EVENT_ID_FUNC_DRVR_LOAD
5464 /* Event specific data */
5465 uint32_t event_data2;
5468 * This value is written by the NIC such that it will be different
5469 * for each pass through the completion queue. The even passes
5470 * will write 1. The odd passes will write 0.
5472 #define HWRM_ASYNC_EVENT_CMPL_FUNC_DRVR_LOAD_V UINT32_C(0x1)
5474 #define HWRM_ASYNC_EVENT_CMPL_FUNC_DRVR_LOAD_OPAQUE_MASK UINT32_C(0xfe)
5475 #define HWRM_ASYNC_EVENT_CMPL_FUNC_DRVR_LOAD_OPAQUE_SFT 1
5476 /* 8-lsb timestamp from POR (100-msec resolution) */
5477 uint8_t timestamp_lo;
5478 /* 16-lsb timestamp from POR (100-msec resolution) */
5479 uint16_t timestamp_hi;
5480 /* Event specific data */
5481 uint32_t event_data1;
5483 #define HWRM_ASYNC_EVENT_CMPL_FUNC_DRVR_LOAD_EVENT_DATA1_FUNC_ID_MASK \
5485 #define HWRM_ASYNC_EVENT_CMPL_FUNC_DRVR_LOAD_EVENT_DATA1_FUNC_ID_SFT 0
5488 /* hwrm_async_event_cmpl_func_flr_proc_cmplt (size:128b/16B) */
5489 struct hwrm_async_event_cmpl_func_flr_proc_cmplt {
5492 * This field indicates the exact type of the completion.
5493 * By convention, the LSB identifies the length of the
5494 * record in 16B units. Even values indicate 16B
5495 * records. Odd values indicate 32B
5498 #define HWRM_ASYNC_EVENT_CMPL_FUNC_FLR_PROC_CMPLT_TYPE_MASK \
5500 #define HWRM_ASYNC_EVENT_CMPL_FUNC_FLR_PROC_CMPLT_TYPE_SFT \
5502 /* HWRM Asynchronous Event Information */
5503 #define HWRM_ASYNC_EVENT_CMPL_FUNC_FLR_PROC_CMPLT_TYPE_HWRM_ASYNC_EVENT \
5505 #define HWRM_ASYNC_EVENT_CMPL_FUNC_FLR_PROC_CMPLT_TYPE_LAST \
5506 HWRM_ASYNC_EVENT_CMPL_FUNC_FLR_PROC_CMPLT_TYPE_HWRM_ASYNC_EVENT
5507 /* Identifiers of events. */
5509 /* Function FLR related processing has completed */
5510 #define HWRM_ASYNC_EVENT_CMPL_FUNC_FLR_PROC_CMPLT_EVENT_ID_FUNC_FLR_PROC_CMPLT \
5512 #define HWRM_ASYNC_EVENT_CMPL_FUNC_FLR_PROC_CMPLT_EVENT_ID_LAST \
5513 HWRM_ASYNC_EVENT_CMPL_FUNC_FLR_PROC_CMPLT_EVENT_ID_FUNC_FLR_PROC_CMPLT
5514 /* Event specific data */
5515 uint32_t event_data2;
5518 * This value is written by the NIC such that it will be different
5519 * for each pass through the completion queue. The even passes
5520 * will write 1. The odd passes will write 0.
5522 #define HWRM_ASYNC_EVENT_CMPL_FUNC_FLR_PROC_CMPLT_V \
5525 #define HWRM_ASYNC_EVENT_CMPL_FUNC_FLR_PROC_CMPLT_OPAQUE_MASK \
5527 #define HWRM_ASYNC_EVENT_CMPL_FUNC_FLR_PROC_CMPLT_OPAQUE_SFT 1
5528 /* 8-lsb timestamp from POR (100-msec resolution) */
5529 uint8_t timestamp_lo;
5530 /* 16-lsb timestamp from POR (100-msec resolution) */
5531 uint16_t timestamp_hi;
5532 /* Event specific data */
5533 uint32_t event_data1;
5535 #define HWRM_ASYNC_EVENT_CMPL_FUNC_FLR_PROC_CMPLT_EVENT_DATA1_FUNC_ID_MASK \
5537 #define HWRM_ASYNC_EVENT_CMPL_FUNC_FLR_PROC_CMPLT_EVENT_DATA1_FUNC_ID_SFT \
5541 /* hwrm_async_event_cmpl_pf_drvr_unload (size:128b/16B) */
5542 struct hwrm_async_event_cmpl_pf_drvr_unload {
5545 * This field indicates the exact type of the completion.
5546 * By convention, the LSB identifies the length of the
5547 * record in 16B units. Even values indicate 16B
5548 * records. Odd values indicate 32B
5551 #define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_UNLOAD_TYPE_MASK \
5553 #define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_UNLOAD_TYPE_SFT 0
5554 /* HWRM Asynchronous Event Information */
5555 #define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_UNLOAD_TYPE_HWRM_ASYNC_EVENT \
5557 #define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_UNLOAD_TYPE_LAST \
5558 HWRM_ASYNC_EVENT_CMPL_PF_DRVR_UNLOAD_TYPE_HWRM_ASYNC_EVENT
5559 /* Identifiers of events. */
5561 /* PF driver unloaded */
5562 #define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_UNLOAD_EVENT_ID_PF_DRVR_UNLOAD \
5564 #define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_UNLOAD_EVENT_ID_LAST \
5565 HWRM_ASYNC_EVENT_CMPL_PF_DRVR_UNLOAD_EVENT_ID_PF_DRVR_UNLOAD
5566 /* Event specific data */
5567 uint32_t event_data2;
5570 * This value is written by the NIC such that it will be different
5571 * for each pass through the completion queue. The even passes
5572 * will write 1. The odd passes will write 0.
5574 #define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_UNLOAD_V UINT32_C(0x1)
5576 #define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_UNLOAD_OPAQUE_MASK UINT32_C(0xfe)
5577 #define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_UNLOAD_OPAQUE_SFT 1
5578 /* 8-lsb timestamp from POR (100-msec resolution) */
5579 uint8_t timestamp_lo;
5580 /* 16-lsb timestamp from POR (100-msec resolution) */
5581 uint16_t timestamp_hi;
5582 /* Event specific data */
5583 uint32_t event_data1;
5585 #define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_UNLOAD_EVENT_DATA1_FUNC_ID_MASK \
5587 #define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_UNLOAD_EVENT_DATA1_FUNC_ID_SFT 0
5588 /* Indicates the physical port this pf belongs to */
5589 #define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_UNLOAD_EVENT_DATA1_PORT_MASK \
5591 #define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_UNLOAD_EVENT_DATA1_PORT_SFT 16
5594 /* hwrm_async_event_cmpl_pf_drvr_load (size:128b/16B) */
5595 struct hwrm_async_event_cmpl_pf_drvr_load {
5598 * This field indicates the exact type of the completion.
5599 * By convention, the LSB identifies the length of the
5600 * record in 16B units. Even values indicate 16B
5601 * records. Odd values indicate 32B
5604 #define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_LOAD_TYPE_MASK \
5606 #define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_LOAD_TYPE_SFT 0
5607 /* HWRM Asynchronous Event Information */
5608 #define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_LOAD_TYPE_HWRM_ASYNC_EVENT \
5610 #define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_LOAD_TYPE_LAST \
5611 HWRM_ASYNC_EVENT_CMPL_PF_DRVR_LOAD_TYPE_HWRM_ASYNC_EVENT
5612 /* Identifiers of events. */
5614 /* PF driver loaded */
5615 #define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_LOAD_EVENT_ID_PF_DRVR_LOAD \
5617 #define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_LOAD_EVENT_ID_LAST \
5618 HWRM_ASYNC_EVENT_CMPL_PF_DRVR_LOAD_EVENT_ID_PF_DRVR_LOAD
5619 /* Event specific data */
5620 uint32_t event_data2;
5623 * This value is written by the NIC such that it will be different
5624 * for each pass through the completion queue. The even passes
5625 * will write 1. The odd passes will write 0.
5627 #define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_LOAD_V UINT32_C(0x1)
5629 #define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_LOAD_OPAQUE_MASK UINT32_C(0xfe)
5630 #define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_LOAD_OPAQUE_SFT 1
5631 /* 8-lsb timestamp from POR (100-msec resolution) */
5632 uint8_t timestamp_lo;
5633 /* 16-lsb timestamp from POR (100-msec resolution) */
5634 uint16_t timestamp_hi;
5635 /* Event specific data */
5636 uint32_t event_data1;
5638 #define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_LOAD_EVENT_DATA1_FUNC_ID_MASK \
5640 #define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_LOAD_EVENT_DATA1_FUNC_ID_SFT 0
5641 /* Indicates the physical port this pf belongs to */
5642 #define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_LOAD_EVENT_DATA1_PORT_MASK \
5644 #define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_LOAD_EVENT_DATA1_PORT_SFT 16
5647 /* hwrm_async_event_cmpl_vf_flr (size:128b/16B) */
5648 struct hwrm_async_event_cmpl_vf_flr {
5651 * This field indicates the exact type of the completion.
5652 * By convention, the LSB identifies the length of the
5653 * record in 16B units. Even values indicate 16B
5654 * records. Odd values indicate 32B
5657 #define HWRM_ASYNC_EVENT_CMPL_VF_FLR_TYPE_MASK \
5659 #define HWRM_ASYNC_EVENT_CMPL_VF_FLR_TYPE_SFT 0
5660 /* HWRM Asynchronous Event Information */
5661 #define HWRM_ASYNC_EVENT_CMPL_VF_FLR_TYPE_HWRM_ASYNC_EVENT \
5663 #define HWRM_ASYNC_EVENT_CMPL_VF_FLR_TYPE_LAST \
5664 HWRM_ASYNC_EVENT_CMPL_VF_FLR_TYPE_HWRM_ASYNC_EVENT
5665 /* Identifiers of events. */
5667 /* VF Function Level Reset (FLR) */
5668 #define HWRM_ASYNC_EVENT_CMPL_VF_FLR_EVENT_ID_VF_FLR UINT32_C(0x30)
5669 #define HWRM_ASYNC_EVENT_CMPL_VF_FLR_EVENT_ID_LAST \
5670 HWRM_ASYNC_EVENT_CMPL_VF_FLR_EVENT_ID_VF_FLR
5671 /* Event specific data */
5672 uint32_t event_data2;
5675 * This value is written by the NIC such that it will be different
5676 * for each pass through the completion queue. The even passes
5677 * will write 1. The odd passes will write 0.
5679 #define HWRM_ASYNC_EVENT_CMPL_VF_FLR_V UINT32_C(0x1)
5681 #define HWRM_ASYNC_EVENT_CMPL_VF_FLR_OPAQUE_MASK UINT32_C(0xfe)
5682 #define HWRM_ASYNC_EVENT_CMPL_VF_FLR_OPAQUE_SFT 1
5683 /* 8-lsb timestamp from POR (100-msec resolution) */
5684 uint8_t timestamp_lo;
5685 /* 16-lsb timestamp from POR (100-msec resolution) */
5686 uint16_t timestamp_hi;
5687 /* Event specific data */
5688 uint32_t event_data1;
5690 #define HWRM_ASYNC_EVENT_CMPL_VF_FLR_EVENT_DATA1_VF_ID_MASK \
5692 #define HWRM_ASYNC_EVENT_CMPL_VF_FLR_EVENT_DATA1_VF_ID_SFT 0
5693 /* Indicates the physical function this event occurred on. */
5694 #define HWRM_ASYNC_EVENT_CMPL_VF_FLR_EVENT_DATA1_PF_ID_MASK \
5696 #define HWRM_ASYNC_EVENT_CMPL_VF_FLR_EVENT_DATA1_PF_ID_SFT 16
5699 /* hwrm_async_event_cmpl_vf_mac_addr_change (size:128b/16B) */
5700 struct hwrm_async_event_cmpl_vf_mac_addr_change {
5703 * This field indicates the exact type of the completion.
5704 * By convention, the LSB identifies the length of the
5705 * record in 16B units. Even values indicate 16B
5706 * records. Odd values indicate 32B
5709 #define HWRM_ASYNC_EVENT_CMPL_VF_MAC_ADDR_CHANGE_TYPE_MASK \
5711 #define HWRM_ASYNC_EVENT_CMPL_VF_MAC_ADDR_CHANGE_TYPE_SFT 0
5712 /* HWRM Asynchronous Event Information */
5713 #define HWRM_ASYNC_EVENT_CMPL_VF_MAC_ADDR_CHANGE_TYPE_HWRM_ASYNC_EVENT \
5715 #define HWRM_ASYNC_EVENT_CMPL_VF_MAC_ADDR_CHANGE_TYPE_LAST \
5716 HWRM_ASYNC_EVENT_CMPL_VF_MAC_ADDR_CHANGE_TYPE_HWRM_ASYNC_EVENT
5717 /* Identifiers of events. */
5719 /* VF MAC Address Change */
5720 #define HWRM_ASYNC_EVENT_CMPL_VF_MAC_ADDR_CHANGE_EVENT_ID_VF_MAC_ADDR_CHANGE \
5722 #define HWRM_ASYNC_EVENT_CMPL_VF_MAC_ADDR_CHANGE_EVENT_ID_LAST \
5723 HWRM_ASYNC_EVENT_CMPL_VF_MAC_ADDR_CHANGE_EVENT_ID_VF_MAC_ADDR_CHANGE
5724 /* Event specific data */
5725 uint32_t event_data2;
5728 * This value is written by the NIC such that it will be different
5729 * for each pass through the completion queue. The even passes
5730 * will write 1. The odd passes will write 0.
5732 #define HWRM_ASYNC_EVENT_CMPL_VF_MAC_ADDR_CHANGE_V \
5735 #define HWRM_ASYNC_EVENT_CMPL_VF_MAC_ADDR_CHANGE_OPAQUE_MASK \
5737 #define HWRM_ASYNC_EVENT_CMPL_VF_MAC_ADDR_CHANGE_OPAQUE_SFT 1
5738 /* 8-lsb timestamp from POR (100-msec resolution) */
5739 uint8_t timestamp_lo;
5740 /* 16-lsb timestamp from POR (100-msec resolution) */
5741 uint16_t timestamp_hi;
5742 /* Event specific data */
5743 uint32_t event_data1;
5745 #define HWRM_ASYNC_EVENT_CMPL_VF_MAC_ADDR_CHANGE_EVENT_DATA1_VF_ID_MASK \
5747 #define HWRM_ASYNC_EVENT_CMPL_VF_MAC_ADDR_CHANGE_EVENT_DATA1_VF_ID_SFT \
5751 /* hwrm_async_event_cmpl_pf_vf_comm_status_change (size:128b/16B) */
5752 struct hwrm_async_event_cmpl_pf_vf_comm_status_change {
5755 * This field indicates the exact type of the completion.
5756 * By convention, the LSB identifies the length of the
5757 * record in 16B units. Even values indicate 16B
5758 * records. Odd values indicate 32B
5761 #define HWRM_ASYNC_EVENT_CMPL_PF_VF_COMM_STATUS_CHANGE_TYPE_MASK \
5763 #define HWRM_ASYNC_EVENT_CMPL_PF_VF_COMM_STATUS_CHANGE_TYPE_SFT \
5765 /* HWRM Asynchronous Event Information */
5766 #define HWRM_ASYNC_EVENT_CMPL_PF_VF_COMM_STATUS_CHANGE_TYPE_HWRM_ASYNC_EVENT \
5768 #define HWRM_ASYNC_EVENT_CMPL_PF_VF_COMM_STATUS_CHANGE_TYPE_LAST \
5769 HWRM_ASYNC_EVENT_CMPL_PF_VF_COMM_STATUS_CHANGE_TYPE_HWRM_ASYNC_EVENT
5770 /* Identifiers of events. */
5772 /* PF-VF communication channel status change. */
5773 #define HWRM_ASYNC_EVENT_CMPL_PF_VF_COMM_STATUS_CHANGE_EVENT_ID_PF_VF_COMM_STATUS_CHANGE \
5775 #define HWRM_ASYNC_EVENT_CMPL_PF_VF_COMM_STATUS_CHANGE_EVENT_ID_LAST \
5776 HWRM_ASYNC_EVENT_CMPL_PF_VF_COMM_STATUS_CHANGE_EVENT_ID_PF_VF_COMM_STATUS_CHANGE
5777 /* Event specific data */
5778 uint32_t event_data2;
5781 * This value is written by the NIC such that it will be different
5782 * for each pass through the completion queue. The even passes
5783 * will write 1. The odd passes will write 0.
5785 #define HWRM_ASYNC_EVENT_CMPL_PF_VF_COMM_STATUS_CHANGE_V \
5788 #define HWRM_ASYNC_EVENT_CMPL_PF_VF_COMM_STATUS_CHANGE_OPAQUE_MASK \
5790 #define HWRM_ASYNC_EVENT_CMPL_PF_VF_COMM_STATUS_CHANGE_OPAQUE_SFT 1
5791 /* 8-lsb timestamp from POR (100-msec resolution) */
5792 uint8_t timestamp_lo;
5793 /* 16-lsb timestamp from POR (100-msec resolution) */
5794 uint16_t timestamp_hi;
5795 /* Event specific data */
5796 uint32_t event_data1;
5798 * If this bit is set to 1, then it indicates that the PF-VF
5799 * communication was lost and it is established.
5800 * If this bit set to 0, then it indicates that the PF-VF
5801 * communication was established and it is lost.
5803 #define HWRM_ASYNC_EVENT_CMPL_PF_VF_COMM_STATUS_CHANGE_EVENT_DATA1_COMM_ESTABLISHED \
5807 /* hwrm_async_event_cmpl_vf_cfg_change (size:128b/16B) */
5808 struct hwrm_async_event_cmpl_vf_cfg_change {
5811 * This field indicates the exact type of the completion.
5812 * By convention, the LSB identifies the length of the
5813 * record in 16B units. Even values indicate 16B
5814 * records. Odd values indicate 32B
5817 #define HWRM_ASYNC_EVENT_CMPL_VF_CFG_CHANGE_TYPE_MASK \
5819 #define HWRM_ASYNC_EVENT_CMPL_VF_CFG_CHANGE_TYPE_SFT 0
5820 /* HWRM Asynchronous Event Information */
5821 #define HWRM_ASYNC_EVENT_CMPL_VF_CFG_CHANGE_TYPE_HWRM_ASYNC_EVENT \
5823 #define HWRM_ASYNC_EVENT_CMPL_VF_CFG_CHANGE_TYPE_LAST \
5824 HWRM_ASYNC_EVENT_CMPL_VF_CFG_CHANGE_TYPE_HWRM_ASYNC_EVENT
5825 /* Identifiers of events. */
5827 /* VF Configuration Change */
5828 #define HWRM_ASYNC_EVENT_CMPL_VF_CFG_CHANGE_EVENT_ID_VF_CFG_CHANGE \
5830 #define HWRM_ASYNC_EVENT_CMPL_VF_CFG_CHANGE_EVENT_ID_LAST \
5831 HWRM_ASYNC_EVENT_CMPL_VF_CFG_CHANGE_EVENT_ID_VF_CFG_CHANGE
5832 /* Event specific data */
5833 uint32_t event_data2;
5836 * This value is written by the NIC such that it will be different
5837 * for each pass through the completion queue. The even passes
5838 * will write 1. The odd passes will write 0.
5840 #define HWRM_ASYNC_EVENT_CMPL_VF_CFG_CHANGE_V UINT32_C(0x1)
5842 #define HWRM_ASYNC_EVENT_CMPL_VF_CFG_CHANGE_OPAQUE_MASK UINT32_C(0xfe)
5843 #define HWRM_ASYNC_EVENT_CMPL_VF_CFG_CHANGE_OPAQUE_SFT 1
5844 /* 8-lsb timestamp from POR (100-msec resolution) */
5845 uint8_t timestamp_lo;
5846 /* 16-lsb timestamp from POR (100-msec resolution) */
5847 uint16_t timestamp_hi;
5849 * Each flag provided in this field indicates a specific VF
5850 * configuration change. At least one of these flags shall be set to 1
5851 * when an asynchronous event completion of this type is provided
5854 uint32_t event_data1;
5856 * If this bit is set to 1, then the value of MTU
5857 * was changed on this VF.
5858 * If set to 0, then this bit should be ignored.
5860 #define HWRM_ASYNC_EVENT_CMPL_VF_CFG_CHANGE_EVENT_DATA1_MTU_CHANGE \
5863 * If this bit is set to 1, then the value of MRU
5864 * was changed on this VF.
5865 * If set to 0, then this bit should be ignored.
5867 #define HWRM_ASYNC_EVENT_CMPL_VF_CFG_CHANGE_EVENT_DATA1_MRU_CHANGE \
5870 * If this bit is set to 1, then the value of default MAC
5871 * address was changed on this VF.
5872 * If set to 0, then this bit should be ignored.
5874 #define HWRM_ASYNC_EVENT_CMPL_VF_CFG_CHANGE_EVENT_DATA1_DFLT_MAC_ADDR_CHANGE \
5877 * If this bit is set to 1, then the value of default VLAN
5878 * was changed on this VF.
5879 * If set to 0, then this bit should be ignored.
5881 #define HWRM_ASYNC_EVENT_CMPL_VF_CFG_CHANGE_EVENT_DATA1_DFLT_VLAN_CHANGE \
5884 * If this bit is set to 1, then the value of trusted VF enable
5885 * was changed on this VF.
5886 * If set to 0, then this bit should be ignored.
5888 #define HWRM_ASYNC_EVENT_CMPL_VF_CFG_CHANGE_EVENT_DATA1_TRUSTED_VF_CFG_CHANGE \
5892 /* hwrm_async_event_cmpl_llfc_pfc_change (size:128b/16B) */
5893 struct hwrm_async_event_cmpl_llfc_pfc_change {
5896 * This field indicates the exact type of the completion.
5897 * By convention, the LSB identifies the length of the
5898 * record in 16B units. Even values indicate 16B
5899 * records. Odd values indicate 32B
5902 #define HWRM_ASYNC_EVENT_CMPL_LLFC_PFC_CHANGE_TYPE_MASK \
5904 #define HWRM_ASYNC_EVENT_CMPL_LLFC_PFC_CHANGE_TYPE_SFT 0
5905 /* HWRM Asynchronous Event Information */
5906 #define HWRM_ASYNC_EVENT_CMPL_LLFC_PFC_CHANGE_TYPE_HWRM_ASYNC_EVENT \
5908 #define HWRM_ASYNC_EVENT_CMPL_LLFC_PFC_CHANGE_TYPE_LAST \
5909 HWRM_ASYNC_EVENT_CMPL_LLFC_PFC_CHANGE_TYPE_HWRM_ASYNC_EVENT
5910 /* unused1 is 10 b */
5911 #define HWRM_ASYNC_EVENT_CMPL_LLFC_PFC_CHANGE_UNUSED1_MASK \
5913 #define HWRM_ASYNC_EVENT_CMPL_LLFC_PFC_CHANGE_UNUSED1_SFT 6
5914 /* Identifiers of events. */
5916 /* LLFC/PFC Configuration Change */
5917 #define HWRM_ASYNC_EVENT_CMPL_LLFC_PFC_CHANGE_EVENT_ID_LLFC_PFC_CHANGE \
5919 #define HWRM_ASYNC_EVENT_CMPL_LLFC_PFC_CHANGE_EVENT_ID_LAST \
5920 HWRM_ASYNC_EVENT_CMPL_LLFC_PFC_CHANGE_EVENT_ID_LLFC_PFC_CHANGE
5921 /* Event specific data */
5922 uint32_t event_data2;
5925 * This value is written by the NIC such that it will be different
5926 * for each pass through the completion queue. The even passes
5927 * will write 1. The odd passes will write 0.
5929 #define HWRM_ASYNC_EVENT_CMPL_LLFC_PFC_CHANGE_V UINT32_C(0x1)
5931 #define HWRM_ASYNC_EVENT_CMPL_LLFC_PFC_CHANGE_OPAQUE_MASK \
5933 #define HWRM_ASYNC_EVENT_CMPL_LLFC_PFC_CHANGE_OPAQUE_SFT 1
5934 /* 8-lsb timestamp from POR (100-msec resolution) */
5935 uint8_t timestamp_lo;
5936 /* 16-lsb timestamp from POR (100-msec resolution) */
5937 uint16_t timestamp_hi;
5938 /* Event specific data */
5939 uint32_t event_data1;
5940 /* Indicates llfc pfc status change */
5941 #define HWRM_ASYNC_EVENT_CMPL_LLFC_PFC_CHANGE_EVENT_DATA1_LLFC_PFC_MASK \
5943 #define HWRM_ASYNC_EVENT_CMPL_LLFC_PFC_CHANGE_EVENT_DATA1_LLFC_PFC_SFT \
5946 * If this field set to 1, then it indicates that llfc is
5949 #define HWRM_ASYNC_EVENT_CMPL_LLFC_PFC_CHANGE_EVENT_DATA1_LLFC_PFC_LLFC \
5952 * If this field is set to 2, then it indicates that pfc
5955 #define HWRM_ASYNC_EVENT_CMPL_LLFC_PFC_CHANGE_EVENT_DATA1_LLFC_PFC_PFC \
5957 #define HWRM_ASYNC_EVENT_CMPL_LLFC_PFC_CHANGE_EVENT_DATA1_LLFC_PFC_LAST \
5958 HWRM_ASYNC_EVENT_CMPL_LLFC_PFC_CHANGE_EVENT_DATA1_LLFC_PFC_PFC
5959 /* Indicates the physical port this llfc pfc change occur */
5960 #define HWRM_ASYNC_EVENT_CMPL_LLFC_PFC_CHANGE_EVENT_DATA1_PORT_MASK \
5962 #define HWRM_ASYNC_EVENT_CMPL_LLFC_PFC_CHANGE_EVENT_DATA1_PORT_SFT \
5965 #define HWRM_ASYNC_EVENT_CMPL_LLFC_PFC_CHANGE_EVENT_DATA1_PORT_ID_MASK \
5967 #define HWRM_ASYNC_EVENT_CMPL_LLFC_PFC_CHANGE_EVENT_DATA1_PORT_ID_SFT \
5971 /* hwrm_async_event_cmpl_default_vnic_change (size:128b/16B) */
5972 struct hwrm_async_event_cmpl_default_vnic_change {
5975 * This field indicates the exact type of the completion.
5976 * By convention, the LSB identifies the length of the
5977 * record in 16B units. Even values indicate 16B
5978 * records. Odd values indicate 32B
5981 #define HWRM_ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_TYPE_MASK \
5983 #define HWRM_ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_TYPE_SFT \
5985 /* HWRM Asynchronous Event Information */
5986 #define HWRM_ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_TYPE_HWRM_ASYNC_EVENT \
5988 #define HWRM_ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_TYPE_LAST \
5989 HWRM_ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_TYPE_HWRM_ASYNC_EVENT
5990 /* unused1 is 10 b */
5991 #define HWRM_ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_UNUSED1_MASK \
5993 #define HWRM_ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_UNUSED1_SFT \
5995 /* Identifiers of events. */
5997 /* Notification of a default vnic allocation or free */
5998 #define HWRM_ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_EVENT_ID_ALLOC_FREE_NOTIFICATION \
6000 #define HWRM_ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_EVENT_ID_LAST \
6001 HWRM_ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_EVENT_ID_ALLOC_FREE_NOTIFICATION
6002 /* Event specific data */
6003 uint32_t event_data2;
6006 * This value is written by the NIC such that it will be different
6007 * for each pass through the completion queue. The even passes
6008 * will write 1. The odd passes will write 0.
6010 #define HWRM_ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_V \
6013 #define HWRM_ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_OPAQUE_MASK \
6015 #define HWRM_ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_OPAQUE_SFT 1
6016 /* 8-lsb timestamp from POR (100-msec resolution) */
6017 uint8_t timestamp_lo;
6018 /* 16-lsb timestamp from POR (100-msec resolution) */
6019 uint16_t timestamp_hi;
6020 /* Event specific data */
6021 uint32_t event_data1;
6022 /* Indicates default vnic configuration change */
6023 #define HWRM_ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_EVENT_DATA1_DEF_VNIC_STATE_MASK \
6025 #define HWRM_ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_EVENT_DATA1_DEF_VNIC_STATE_SFT \
6028 * If this field is set to 1, then it indicates that
6029 * a default VNIC has been allocate.
6031 #define HWRM_ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_EVENT_DATA1_DEF_VNIC_STATE_DEF_VNIC_ALLOC \
6034 * If this field is set to 2, then it indicates that
6035 * a default VNIC has been freed.
6037 #define HWRM_ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_EVENT_DATA1_DEF_VNIC_STATE_DEF_VNIC_FREE \
6039 #define HWRM_ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_EVENT_DATA1_DEF_VNIC_STATE_LAST \
6040 HWRM_ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_EVENT_DATA1_DEF_VNIC_STATE_DEF_VNIC_FREE
6041 /* Indicates the physical function this event occurred on. */
6042 #define HWRM_ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_EVENT_DATA1_PF_ID_MASK \
6044 #define HWRM_ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_EVENT_DATA1_PF_ID_SFT \
6046 /* Indicates the virtual function this event occurred on */
6047 #define HWRM_ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_EVENT_DATA1_VF_ID_MASK \
6049 #define HWRM_ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_EVENT_DATA1_VF_ID_SFT \
6053 /* hwrm_async_event_cmpl_hw_flow_aged (size:128b/16B) */
6054 struct hwrm_async_event_cmpl_hw_flow_aged {
6057 * This field indicates the exact type of the completion.
6058 * By convention, the LSB identifies the length of the
6059 * record in 16B units. Even values indicate 16B
6060 * records. Odd values indicate 32B
6063 #define HWRM_ASYNC_EVENT_CMPL_HW_FLOW_AGED_TYPE_MASK \
6065 #define HWRM_ASYNC_EVENT_CMPL_HW_FLOW_AGED_TYPE_SFT 0
6066 /* HWRM Asynchronous Event Information */
6067 #define HWRM_ASYNC_EVENT_CMPL_HW_FLOW_AGED_TYPE_HWRM_ASYNC_EVENT \
6069 #define HWRM_ASYNC_EVENT_CMPL_HW_FLOW_AGED_TYPE_LAST \
6070 HWRM_ASYNC_EVENT_CMPL_HW_FLOW_AGED_TYPE_HWRM_ASYNC_EVENT
6071 /* Identifiers of events. */
6073 /* Notification of a hw flow aged */
6074 #define HWRM_ASYNC_EVENT_CMPL_HW_FLOW_AGED_EVENT_ID_HW_FLOW_AGED \
6076 #define HWRM_ASYNC_EVENT_CMPL_HW_FLOW_AGED_EVENT_ID_LAST \
6077 HWRM_ASYNC_EVENT_CMPL_HW_FLOW_AGED_EVENT_ID_HW_FLOW_AGED
6078 /* Event specific data */
6079 uint32_t event_data2;
6082 * This value is written by the NIC such that it will be different
6083 * for each pass through the completion queue. The even passes
6084 * will write 1. The odd passes will write 0.
6086 #define HWRM_ASYNC_EVENT_CMPL_HW_FLOW_AGED_V UINT32_C(0x1)
6088 #define HWRM_ASYNC_EVENT_CMPL_HW_FLOW_AGED_OPAQUE_MASK UINT32_C(0xfe)
6089 #define HWRM_ASYNC_EVENT_CMPL_HW_FLOW_AGED_OPAQUE_SFT 1
6090 /* 8-lsb timestamp from POR (100-msec resolution) */
6091 uint8_t timestamp_lo;
6092 /* 16-lsb timestamp from POR (100-msec resolution) */
6093 uint16_t timestamp_hi;
6094 /* Event specific data */
6095 uint32_t event_data1;
6096 /* Indicates flow ID this event occurred on. */
6097 #define HWRM_ASYNC_EVENT_CMPL_HW_FLOW_AGED_EVENT_DATA1_FLOW_ID_MASK \
6098 UINT32_C(0x7fffffff)
6099 #define HWRM_ASYNC_EVENT_CMPL_HW_FLOW_AGED_EVENT_DATA1_FLOW_ID_SFT \
6101 /* Indicates flow direction this event occurred on. */
6102 #define HWRM_ASYNC_EVENT_CMPL_HW_FLOW_AGED_EVENT_DATA1_FLOW_DIRECTION \
6103 UINT32_C(0x80000000)
6105 * If this bit set to 0, then it indicates that the aged
6106 * event was rx flow.
6108 #define HWRM_ASYNC_EVENT_CMPL_HW_FLOW_AGED_EVENT_DATA1_FLOW_DIRECTION_RX \
6109 (UINT32_C(0x0) << 31)
6111 * If this bit is set to 1, then it indicates that the aged
6112 * event was tx flow.
6114 #define HWRM_ASYNC_EVENT_CMPL_HW_FLOW_AGED_EVENT_DATA1_FLOW_DIRECTION_TX \
6115 (UINT32_C(0x1) << 31)
6116 #define HWRM_ASYNC_EVENT_CMPL_HW_FLOW_AGED_EVENT_DATA1_FLOW_DIRECTION_LAST \
6117 HWRM_ASYNC_EVENT_CMPL_HW_FLOW_AGED_EVENT_DATA1_FLOW_DIRECTION_TX
6120 /* hwrm_async_event_cmpl_eem_cache_flush_req (size:128b/16B) */
6121 struct hwrm_async_event_cmpl_eem_cache_flush_req {
6124 * This field indicates the exact type of the completion.
6125 * By convention, the LSB identifies the length of the
6126 * record in 16B units. Even values indicate 16B
6127 * records. Odd values indicate 32B
6130 #define HWRM_ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_REQ_TYPE_MASK \
6132 #define HWRM_ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_REQ_TYPE_SFT \
6134 /* HWRM Asynchronous Event Information */
6135 #define HWRM_ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_REQ_TYPE_HWRM_ASYNC_EVENT \
6137 #define HWRM_ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_REQ_TYPE_LAST \
6138 HWRM_ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_REQ_TYPE_HWRM_ASYNC_EVENT
6139 /* Identifiers of events. */
6141 /* Notification of a eem_cache_flush request */
6142 #define HWRM_ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_REQ_EVENT_ID_EEM_CACHE_FLUSH_REQ \
6144 #define HWRM_ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_REQ_EVENT_ID_LAST \
6145 HWRM_ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_REQ_EVENT_ID_EEM_CACHE_FLUSH_REQ
6146 /* Event specific data */
6147 uint32_t event_data2;
6150 * This value is written by the NIC such that it will be different
6151 * for each pass through the completion queue. The even passes
6152 * will write 1. The odd passes will write 0.
6154 #define HWRM_ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_REQ_V \
6157 #define HWRM_ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_REQ_OPAQUE_MASK \
6159 #define HWRM_ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_REQ_OPAQUE_SFT 1
6160 /* 8-lsb timestamp from POR (100-msec resolution) */
6161 uint8_t timestamp_lo;
6162 /* 16-lsb timestamp from POR (100-msec resolution) */
6163 uint16_t timestamp_hi;
6164 /* Event specific data */
6165 uint32_t event_data1;
6168 /* hwrm_async_event_cmpl_eem_cache_flush_done (size:128b/16B) */
6169 struct hwrm_async_event_cmpl_eem_cache_flush_done {
6172 * This field indicates the exact type of the completion.
6173 * By convention, the LSB identifies the length of the
6174 * record in 16B units. Even values indicate 16B
6175 * records. Odd values indicate 32B
6178 #define HWRM_ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_DONE_TYPE_MASK \
6180 #define HWRM_ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_DONE_TYPE_SFT \
6182 /* HWRM Asynchronous Event Information */
6183 #define HWRM_ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_DONE_TYPE_HWRM_ASYNC_EVENT \
6185 #define HWRM_ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_DONE_TYPE_LAST \
6186 HWRM_ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_DONE_TYPE_HWRM_ASYNC_EVENT
6187 /* Identifiers of events. */
6190 * Notification of a host eem_cache_flush has completed. This event
6191 * is generated by the host driver.
6193 #define HWRM_ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_DONE_EVENT_ID_EEM_CACHE_FLUSH_DONE \
6195 #define HWRM_ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_DONE_EVENT_ID_LAST \
6196 HWRM_ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_DONE_EVENT_ID_EEM_CACHE_FLUSH_DONE
6197 /* Event specific data */
6198 uint32_t event_data2;
6201 * This value is written by the NIC such that it will be different
6202 * for each pass through the completion queue. The even passes
6203 * will write 1. The odd passes will write 0.
6205 #define HWRM_ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_DONE_V \
6208 #define HWRM_ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_DONE_OPAQUE_MASK \
6210 #define HWRM_ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_DONE_OPAQUE_SFT 1
6211 /* 8-lsb timestamp from POR (100-msec resolution) */
6212 uint8_t timestamp_lo;
6213 /* 16-lsb timestamp from POR (100-msec resolution) */
6214 uint16_t timestamp_hi;
6215 /* Event specific data */
6216 uint32_t event_data1;
6217 /* Indicates function ID that this event occurred on. */
6218 #define HWRM_ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_DONE_EVENT_DATA1_FID_MASK \
6220 #define HWRM_ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_DONE_EVENT_DATA1_FID_SFT \
6224 /* hwrm_async_event_cmpl_tcp_flag_action_change (size:128b/16B) */
6225 struct hwrm_async_event_cmpl_tcp_flag_action_change {
6228 * This field indicates the exact type of the completion.
6229 * By convention, the LSB identifies the length of the
6230 * record in 16B units. Even values indicate 16B
6231 * records. Odd values indicate 32B
6234 #define HWRM_ASYNC_EVENT_CMPL_TCP_FLAG_ACTION_CHANGE_TYPE_MASK \
6236 #define HWRM_ASYNC_EVENT_CMPL_TCP_FLAG_ACTION_CHANGE_TYPE_SFT \
6238 /* HWRM Asynchronous Event Information */
6239 #define HWRM_ASYNC_EVENT_CMPL_TCP_FLAG_ACTION_CHANGE_TYPE_HWRM_ASYNC_EVENT \
6241 #define HWRM_ASYNC_EVENT_CMPL_TCP_FLAG_ACTION_CHANGE_TYPE_LAST \
6242 HWRM_ASYNC_EVENT_CMPL_TCP_FLAG_ACTION_CHANGE_TYPE_HWRM_ASYNC_EVENT
6243 /* Identifiers of events. */
6245 /* Notification of tcp flag action change */
6246 #define HWRM_ASYNC_EVENT_CMPL_TCP_FLAG_ACTION_CHANGE_EVENT_ID_TCP_FLAG_ACTION_CHANGE \
6248 #define HWRM_ASYNC_EVENT_CMPL_TCP_FLAG_ACTION_CHANGE_EVENT_ID_LAST \
6249 HWRM_ASYNC_EVENT_CMPL_TCP_FLAG_ACTION_CHANGE_EVENT_ID_TCP_FLAG_ACTION_CHANGE
6250 /* Event specific data */
6251 uint32_t event_data2;
6254 * This value is written by the NIC such that it will be different
6255 * for each pass through the completion queue. The even passes
6256 * will write 1. The odd passes will write 0.
6258 #define HWRM_ASYNC_EVENT_CMPL_TCP_FLAG_ACTION_CHANGE_V \
6261 #define HWRM_ASYNC_EVENT_CMPL_TCP_FLAG_ACTION_CHANGE_OPAQUE_MASK \
6263 #define HWRM_ASYNC_EVENT_CMPL_TCP_FLAG_ACTION_CHANGE_OPAQUE_SFT 1
6264 /* 8-lsb timestamp from POR (100-msec resolution) */
6265 uint8_t timestamp_lo;
6266 /* 16-lsb timestamp from POR (100-msec resolution) */
6267 uint16_t timestamp_hi;
6268 /* Event specific data */
6269 uint32_t event_data1;
6272 /* hwrm_async_event_cmpl_eem_flow_active (size:128b/16B) */
6273 struct hwrm_async_event_cmpl_eem_flow_active {
6276 * This field indicates the exact type of the completion.
6277 * By convention, the LSB identifies the length of the
6278 * record in 16B units. Even values indicate 16B
6279 * records. Odd values indicate 32B
6282 #define HWRM_ASYNC_EVENT_CMPL_EEM_FLOW_ACTIVE_TYPE_MASK \
6284 #define HWRM_ASYNC_EVENT_CMPL_EEM_FLOW_ACTIVE_TYPE_SFT 0
6285 /* HWRM Asynchronous Event Information */
6286 #define HWRM_ASYNC_EVENT_CMPL_EEM_FLOW_ACTIVE_TYPE_HWRM_ASYNC_EVENT \
6288 #define HWRM_ASYNC_EVENT_CMPL_EEM_FLOW_ACTIVE_TYPE_LAST \
6289 HWRM_ASYNC_EVENT_CMPL_EEM_FLOW_ACTIVE_TYPE_HWRM_ASYNC_EVENT
6290 /* Identifiers of events. */
6292 /* Notification of an active eem flow */
6293 #define HWRM_ASYNC_EVENT_CMPL_EEM_FLOW_ACTIVE_EVENT_ID_EEM_FLOW_ACTIVE \
6295 #define HWRM_ASYNC_EVENT_CMPL_EEM_FLOW_ACTIVE_EVENT_ID_LAST \
6296 HWRM_ASYNC_EVENT_CMPL_EEM_FLOW_ACTIVE_EVENT_ID_EEM_FLOW_ACTIVE
6297 /* Event specific data */
6298 uint32_t event_data2;
6299 /* Indicates the 2nd global id this event occurred on. */
6300 #define HWRM_ASYNC_EVENT_CMPL_EEM_FLOW_ACTIVE_EVENT_DATA2_GLOBAL_ID_2_MASK \
6301 UINT32_C(0x3fffffff)
6302 #define HWRM_ASYNC_EVENT_CMPL_EEM_FLOW_ACTIVE_EVENT_DATA2_GLOBAL_ID_2_SFT \
6305 * Indicates flow direction of the flow identified by
6308 #define HWRM_ASYNC_EVENT_CMPL_EEM_FLOW_ACTIVE_EVENT_DATA2_FLOW_DIRECTION \
6309 UINT32_C(0x40000000)
6310 /* If this bit is set to 0, then it indicates that this rx flow. */
6311 #define HWRM_ASYNC_EVENT_CMPL_EEM_FLOW_ACTIVE_EVENT_DATA2_FLOW_DIRECTION_RX \
6312 (UINT32_C(0x0) << 30)
6313 /* If this bit is set to 1, then it indicates that this tx flow. */
6314 #define HWRM_ASYNC_EVENT_CMPL_EEM_FLOW_ACTIVE_EVENT_DATA2_FLOW_DIRECTION_TX \
6315 (UINT32_C(0x1) << 30)
6316 #define HWRM_ASYNC_EVENT_CMPL_EEM_FLOW_ACTIVE_EVENT_DATA2_FLOW_DIRECTION_LAST \
6317 HWRM_ASYNC_EVENT_CMPL_EEM_FLOW_ACTIVE_EVENT_DATA2_FLOW_DIRECTION_TX
6320 * This value is written by the NIC such that it will be different
6321 * for each pass through the completion queue. The even passes
6322 * will write 1. The odd passes will write 0.
6324 #define HWRM_ASYNC_EVENT_CMPL_EEM_FLOW_ACTIVE_V UINT32_C(0x1)
6326 #define HWRM_ASYNC_EVENT_CMPL_EEM_FLOW_ACTIVE_OPAQUE_MASK \
6328 #define HWRM_ASYNC_EVENT_CMPL_EEM_FLOW_ACTIVE_OPAQUE_SFT 1
6329 /* 8-lsb timestamp from POR (100-msec resolution) */
6330 uint8_t timestamp_lo;
6331 /* 16-lsb timestamp from POR (100-msec resolution) */
6332 uint16_t timestamp_hi;
6333 /* Event specific data */
6334 uint32_t event_data1;
6335 /* Indicates the 1st global id this event occurred on. */
6336 #define HWRM_ASYNC_EVENT_CMPL_EEM_FLOW_ACTIVE_EVENT_DATA1_GLOBAL_ID_1_MASK \
6337 UINT32_C(0x3fffffff)
6338 #define HWRM_ASYNC_EVENT_CMPL_EEM_FLOW_ACTIVE_EVENT_DATA1_GLOBAL_ID_1_SFT \
6341 * Indicates flow direction of the flow identified by the
6344 #define HWRM_ASYNC_EVENT_CMPL_EEM_FLOW_ACTIVE_EVENT_DATA1_FLOW_DIRECTION \
6345 UINT32_C(0x40000000)
6346 /* If this bit is set to 0, then it indicates that this is rx flow. */
6347 #define HWRM_ASYNC_EVENT_CMPL_EEM_FLOW_ACTIVE_EVENT_DATA1_FLOW_DIRECTION_RX \
6348 (UINT32_C(0x0) << 30)
6349 /* If this bit is set to 1, then it indicates that this is tx flow. */
6350 #define HWRM_ASYNC_EVENT_CMPL_EEM_FLOW_ACTIVE_EVENT_DATA1_FLOW_DIRECTION_TX \
6351 (UINT32_C(0x1) << 30)
6352 #define HWRM_ASYNC_EVENT_CMPL_EEM_FLOW_ACTIVE_EVENT_DATA1_FLOW_DIRECTION_LAST \
6353 HWRM_ASYNC_EVENT_CMPL_EEM_FLOW_ACTIVE_EVENT_DATA1_FLOW_DIRECTION_TX
6355 * Indicates EEM flow aging mode this event occurred on. If
6356 * this bit is set to 0, the event_data1 is the EEM global
6357 * ID. If this bit is set to 1, the event_data1 is the number
6358 * of global ID in the context memory.
6360 #define HWRM_ASYNC_EVENT_CMPL_EEM_FLOW_ACTIVE_EVENT_DATA1_MODE \
6361 UINT32_C(0x80000000)
6362 /* EEM flow aging mode 0. */
6363 #define HWRM_ASYNC_EVENT_CMPL_EEM_FLOW_ACTIVE_EVENT_DATA1_MODE_0 \
6364 (UINT32_C(0x0) << 31)
6365 /* EEM flow aging mode 1. */
6366 #define HWRM_ASYNC_EVENT_CMPL_EEM_FLOW_ACTIVE_EVENT_DATA1_MODE_1 \
6367 (UINT32_C(0x1) << 31)
6368 #define HWRM_ASYNC_EVENT_CMPL_EEM_FLOW_ACTIVE_EVENT_DATA1_MODE_LAST \
6369 HWRM_ASYNC_EVENT_CMPL_EEM_FLOW_ACTIVE_EVENT_DATA1_MODE_1
6372 /* hwrm_async_event_cmpl_eem_cfg_change (size:128b/16B) */
6373 struct hwrm_async_event_cmpl_eem_cfg_change {
6376 * This field indicates the exact type of the completion.
6377 * By convention, the LSB identifies the length of the
6378 * record in 16B units. Even values indicate 16B
6379 * records. Odd values indicate 32B
6382 #define HWRM_ASYNC_EVENT_CMPL_EEM_CFG_CHANGE_TYPE_MASK \
6384 #define HWRM_ASYNC_EVENT_CMPL_EEM_CFG_CHANGE_TYPE_SFT 0
6385 /* HWRM Asynchronous Event Information */
6386 #define HWRM_ASYNC_EVENT_CMPL_EEM_CFG_CHANGE_TYPE_HWRM_ASYNC_EVENT \
6388 #define HWRM_ASYNC_EVENT_CMPL_EEM_CFG_CHANGE_TYPE_LAST \
6389 HWRM_ASYNC_EVENT_CMPL_EEM_CFG_CHANGE_TYPE_HWRM_ASYNC_EVENT
6390 /* Identifiers of events. */
6392 /* Notification of EEM configuration change */
6393 #define HWRM_ASYNC_EVENT_CMPL_EEM_CFG_CHANGE_EVENT_ID_EEM_CFG_CHANGE \
6395 #define HWRM_ASYNC_EVENT_CMPL_EEM_CFG_CHANGE_EVENT_ID_LAST \
6396 HWRM_ASYNC_EVENT_CMPL_EEM_CFG_CHANGE_EVENT_ID_EEM_CFG_CHANGE
6397 /* Event specific data */
6398 uint32_t event_data2;
6401 * This value is written by the NIC such that it will be different
6402 * for each pass through the completion queue. The even passes
6403 * will write 1. The odd passes will write 0.
6405 #define HWRM_ASYNC_EVENT_CMPL_EEM_CFG_CHANGE_V UINT32_C(0x1)
6407 #define HWRM_ASYNC_EVENT_CMPL_EEM_CFG_CHANGE_OPAQUE_MASK UINT32_C(0xfe)
6408 #define HWRM_ASYNC_EVENT_CMPL_EEM_CFG_CHANGE_OPAQUE_SFT 1
6409 /* 8-lsb timestamp from POR (100-msec resolution) */
6410 uint8_t timestamp_lo;
6411 /* 16-lsb timestamp from POR (100-msec resolution) */
6412 uint16_t timestamp_hi;
6413 /* Event specific data */
6414 uint32_t event_data1;
6416 * Value of 1 to indicate EEM TX configuration is enabled. Value of
6417 * 0 to indicate the EEM TX configuration is disabled.
6419 #define HWRM_ASYNC_EVENT_CMPL_EEM_CFG_CHANGE_EVENT_DATA1_EEM_TX_ENABLE \
6422 * Value of 1 to indicate EEM RX configuration is enabled. Value of 0
6423 * to indicate the EEM RX configuration is disabled.
6425 #define HWRM_ASYNC_EVENT_CMPL_EEM_CFG_CHANGE_EVENT_DATA1_EEM_RX_ENABLE \
6429 /* hwrm_async_event_cmpl_quiesce_done (size:128b/16B) */
6430 struct hwrm_async_event_cmpl_quiesce_done {
6433 * This field indicates the exact type of the completion.
6434 * By convention, the LSB identifies the length of the
6435 * record in 16B units. Even values indicate 16B
6436 * records. Odd values indicate 32B
6439 #define HWRM_ASYNC_EVENT_CMPL_QUIESCE_DONE_TYPE_MASK \
6441 #define HWRM_ASYNC_EVENT_CMPL_QUIESCE_DONE_TYPE_SFT 0
6442 /* HWRM Asynchronous Event Information */
6443 #define HWRM_ASYNC_EVENT_CMPL_QUIESCE_DONE_TYPE_HWRM_ASYNC_EVENT \
6445 #define HWRM_ASYNC_EVENT_CMPL_QUIESCE_DONE_TYPE_LAST \
6446 HWRM_ASYNC_EVENT_CMPL_QUIESCE_DONE_TYPE_HWRM_ASYNC_EVENT
6447 /* Identifiers of events. */
6449 /* An event signifying completion of HWRM_FW_STATE_QUIESCE */
6450 #define HWRM_ASYNC_EVENT_CMPL_QUIESCE_DONE_EVENT_ID_QUIESCE_DONE \
6452 #define HWRM_ASYNC_EVENT_CMPL_QUIESCE_DONE_EVENT_ID_LAST \
6453 HWRM_ASYNC_EVENT_CMPL_QUIESCE_DONE_EVENT_ID_QUIESCE_DONE
6454 /* Event specific data */
6455 uint32_t event_data2;
6456 /* Status of HWRM_FW_STATE_QUIESCE completion */
6457 #define HWRM_ASYNC_EVENT_CMPL_QUIESCE_DONE_EVENT_DATA2_QUIESCE_STATUS_MASK \
6459 #define HWRM_ASYNC_EVENT_CMPL_QUIESCE_DONE_EVENT_DATA2_QUIESCE_STATUS_SFT \
6462 * The quiesce operation started by HWRM_FW_STATE_QUIESCE
6463 * completed successfully.
6465 #define HWRM_ASYNC_EVENT_CMPL_QUIESCE_DONE_EVENT_DATA2_QUIESCE_STATUS_SUCCESS \
6468 * The quiesce operation started by HWRM_FW_STATE_QUIESCE timed
6471 #define HWRM_ASYNC_EVENT_CMPL_QUIESCE_DONE_EVENT_DATA2_QUIESCE_STATUS_TIMEOUT \
6474 * The quiesce operation started by HWRM_FW_STATE_QUIESCE
6475 * encountered an error.
6477 #define HWRM_ASYNC_EVENT_CMPL_QUIESCE_DONE_EVENT_DATA2_QUIESCE_STATUS_ERROR \
6479 #define HWRM_ASYNC_EVENT_CMPL_QUIESCE_DONE_EVENT_DATA2_QUIESCE_STATUS_LAST \
6480 HWRM_ASYNC_EVENT_CMPL_QUIESCE_DONE_EVENT_DATA2_QUIESCE_STATUS_ERROR
6482 #define HWRM_ASYNC_EVENT_CMPL_QUIESCE_DONE_EVENT_DATA2_OPAQUE_MASK \
6484 #define HWRM_ASYNC_EVENT_CMPL_QUIESCE_DONE_EVENT_DATA2_OPAQUE_SFT \
6487 * Additional information about internal hardware state related to
6488 * idle/quiesce state. QUIESCE may succeed per quiesce_status
6489 * regardless of idle_state_flags. If QUIESCE fails, the host may
6490 * inspect idle_state_flags to determine whether a retry is warranted.
6492 #define HWRM_ASYNC_EVENT_CMPL_QUIESCE_DONE_EVENT_DATA2_IDLE_STATE_FLAGS_MASK \
6494 #define HWRM_ASYNC_EVENT_CMPL_QUIESCE_DONE_EVENT_DATA2_IDLE_STATE_FLAGS_SFT \
6497 * Failure to quiesce is caused by host not updating the NQ consumer
6500 #define HWRM_ASYNC_EVENT_CMPL_QUIESCE_DONE_EVENT_DATA2_IDLE_STATE_FLAGS_INCOMPLETE_NQ \
6502 /* Flag 1 indicating partial non-idle state. */
6503 #define HWRM_ASYNC_EVENT_CMPL_QUIESCE_DONE_EVENT_DATA2_IDLE_STATE_FLAGS_IDLE_STATUS_1 \
6505 /* Flag 2 indicating partial non-idle state. */
6506 #define HWRM_ASYNC_EVENT_CMPL_QUIESCE_DONE_EVENT_DATA2_IDLE_STATE_FLAGS_IDLE_STATUS_2 \
6508 /* Flag 3 indicating partial non-idle state. */
6509 #define HWRM_ASYNC_EVENT_CMPL_QUIESCE_DONE_EVENT_DATA2_IDLE_STATE_FLAGS_IDLE_STATUS_3 \
6513 * This value is written by the NIC such that it will be different
6514 * for each pass through the completion queue. The even passes
6515 * will write 1. The odd passes will write 0.
6517 #define HWRM_ASYNC_EVENT_CMPL_QUIESCE_DONE_V UINT32_C(0x1)
6519 #define HWRM_ASYNC_EVENT_CMPL_QUIESCE_DONE_OPAQUE_MASK UINT32_C(0xfe)
6520 #define HWRM_ASYNC_EVENT_CMPL_QUIESCE_DONE_OPAQUE_SFT 1
6521 /* 8-lsb timestamp from POR (100-msec resolution) */
6522 uint8_t timestamp_lo;
6523 /* 16-lsb timestamp from POR (100-msec resolution) */
6524 uint16_t timestamp_hi;
6525 /* Event specific data */
6526 uint32_t event_data1;
6527 /* Time stamp for error event */
6528 #define HWRM_ASYNC_EVENT_CMPL_QUIESCE_DONE_EVENT_DATA1_TIMESTAMP \
6532 /* hwrm_async_event_cmpl_deferred_response (size:128b/16B) */
6533 struct hwrm_async_event_cmpl_deferred_response {
6536 * This field indicates the exact type of the completion.
6537 * By convention, the LSB identifies the length of the
6538 * record in 16B units. Even values indicate 16B
6539 * records. Odd values indicate 32B
6542 #define HWRM_ASYNC_EVENT_CMPL_DEFERRED_RESPONSE_TYPE_MASK \
6544 #define HWRM_ASYNC_EVENT_CMPL_DEFERRED_RESPONSE_TYPE_SFT 0
6545 /* HWRM Asynchronous Event Information */
6546 #define HWRM_ASYNC_EVENT_CMPL_DEFERRED_RESPONSE_TYPE_HWRM_ASYNC_EVENT \
6548 #define HWRM_ASYNC_EVENT_CMPL_DEFERRED_RESPONSE_TYPE_LAST \
6549 HWRM_ASYNC_EVENT_CMPL_DEFERRED_RESPONSE_TYPE_HWRM_ASYNC_EVENT
6550 /* Identifiers of events. */
6553 * An event signifying a HWRM command is in progress and its
6554 * response will be deferred
6556 #define HWRM_ASYNC_EVENT_CMPL_DEFERRED_RESPONSE_EVENT_ID_DEFERRED_RESPONSE \
6558 #define HWRM_ASYNC_EVENT_CMPL_DEFERRED_RESPONSE_EVENT_ID_LAST \
6559 HWRM_ASYNC_EVENT_CMPL_DEFERRED_RESPONSE_EVENT_ID_DEFERRED_RESPONSE
6560 /* Event specific data */
6561 uint32_t event_data2;
6563 * The PF's mailbox is clear to issue another command.
6564 * A command with this seq_id is still in progress
6565 * and will return a regular HWRM completion when done.
6566 * 'event_data1' field, if non-zero, contains the estimated
6567 * execution time for the command.
6569 #define HWRM_ASYNC_EVENT_CMPL_DEFERRED_RESPONSE_EVENT_DATA2_SEQ_ID_MASK \
6571 #define HWRM_ASYNC_EVENT_CMPL_DEFERRED_RESPONSE_EVENT_DATA2_SEQ_ID_SFT \
6575 * This value is written by the NIC such that it will be different
6576 * for each pass through the completion queue. The even passes
6577 * will write 1. The odd passes will write 0.
6579 #define HWRM_ASYNC_EVENT_CMPL_DEFERRED_RESPONSE_V \
6582 #define HWRM_ASYNC_EVENT_CMPL_DEFERRED_RESPONSE_OPAQUE_MASK \
6584 #define HWRM_ASYNC_EVENT_CMPL_DEFERRED_RESPONSE_OPAQUE_SFT 1
6585 /* 8-lsb timestamp from POR (100-msec resolution) */
6586 uint8_t timestamp_lo;
6587 /* 16-lsb timestamp from POR (100-msec resolution) */
6588 uint16_t timestamp_hi;
6589 /* Estimated remaining time of command execution in ms (if not zero) */
6590 uint32_t event_data1;
6593 /* hwrm_async_event_cmpl_pfc_watchdog_cfg_change (size:128b/16B) */
6594 struct hwrm_async_event_cmpl_pfc_watchdog_cfg_change {
6597 * This field indicates the exact type of the completion.
6598 * By convention, the LSB identifies the length of the
6599 * record in 16B units. Even values indicate 16B
6600 * records. Odd values indicate 32B
6603 #define HWRM_ASYNC_EVENT_CMPL_PFC_WATCHDOG_CFG_CHANGE_TYPE_MASK \
6605 #define HWRM_ASYNC_EVENT_CMPL_PFC_WATCHDOG_CFG_CHANGE_TYPE_SFT \
6607 /* HWRM Asynchronous Event Information */
6608 #define HWRM_ASYNC_EVENT_CMPL_PFC_WATCHDOG_CFG_CHANGE_TYPE_HWRM_ASYNC_EVENT \
6610 #define HWRM_ASYNC_EVENT_CMPL_PFC_WATCHDOG_CFG_CHANGE_TYPE_LAST \
6611 HWRM_ASYNC_EVENT_CMPL_PFC_WATCHDOG_CFG_CHANGE_TYPE_HWRM_ASYNC_EVENT
6612 /* Identifiers of events. */
6614 /* PFC watchdog configuration change for given port/cos */
6615 #define HWRM_ASYNC_EVENT_CMPL_PFC_WATCHDOG_CFG_CHANGE_EVENT_ID_PFC_WATCHDOG_CFG_CHANGE \
6617 #define HWRM_ASYNC_EVENT_CMPL_PFC_WATCHDOG_CFG_CHANGE_EVENT_ID_LAST \
6618 HWRM_ASYNC_EVENT_CMPL_PFC_WATCHDOG_CFG_CHANGE_EVENT_ID_PFC_WATCHDOG_CFG_CHANGE
6619 /* Event specific data */
6620 uint32_t event_data2;
6623 * This value is written by the NIC such that it will be different
6624 * for each pass through the completion queue. The even passes
6625 * will write 1. The odd passes will write 0.
6627 #define HWRM_ASYNC_EVENT_CMPL_PFC_WATCHDOG_CFG_CHANGE_V \
6630 #define HWRM_ASYNC_EVENT_CMPL_PFC_WATCHDOG_CFG_CHANGE_OPAQUE_MASK \
6632 #define HWRM_ASYNC_EVENT_CMPL_PFC_WATCHDOG_CFG_CHANGE_OPAQUE_SFT 1
6633 /* 8-lsb timestamp from POR (100-msec resolution) */
6634 uint8_t timestamp_lo;
6635 /* 16-lsb timestamp from POR (100-msec resolution) */
6636 uint16_t timestamp_hi;
6637 /* Event specific data */
6638 uint32_t event_data1;
6640 * 1 in bit position X indicates PFC watchdog should
6643 #define HWRM_ASYNC_EVENT_CMPL_PFC_WATCHDOG_CFG_CHANGE_EVENT_DATA1_PFC_WD_COS_MASK \
6645 #define HWRM_ASYNC_EVENT_CMPL_PFC_WATCHDOG_CFG_CHANGE_EVENT_DATA1_PFC_WD_COS_SFT \
6647 /* 1 means PFC WD for COS0 is on, 0 - off. */
6648 #define HWRM_ASYNC_EVENT_CMPL_PFC_WATCHDOG_CFG_CHANGE_EVENT_DATA1_PFC_WD_COS_PFC_WD_COS0 \
6650 /* 1 means PFC WD for COS1 is on, 0 - off. */
6651 #define HWRM_ASYNC_EVENT_CMPL_PFC_WATCHDOG_CFG_CHANGE_EVENT_DATA1_PFC_WD_COS_PFC_WD_COS1 \
6653 /* 1 means PFC WD for COS2 is on, 0 - off. */
6654 #define HWRM_ASYNC_EVENT_CMPL_PFC_WATCHDOG_CFG_CHANGE_EVENT_DATA1_PFC_WD_COS_PFC_WD_COS2 \
6656 /* 1 means PFC WD for COS3 is on, 0 - off. */
6657 #define HWRM_ASYNC_EVENT_CMPL_PFC_WATCHDOG_CFG_CHANGE_EVENT_DATA1_PFC_WD_COS_PFC_WD_COS3 \
6659 /* 1 means PFC WD for COS4 is on, 0 - off. */
6660 #define HWRM_ASYNC_EVENT_CMPL_PFC_WATCHDOG_CFG_CHANGE_EVENT_DATA1_PFC_WD_COS_PFC_WD_COS4 \
6662 /* 1 means PFC WD for COS5 is on, 0 - off. */
6663 #define HWRM_ASYNC_EVENT_CMPL_PFC_WATCHDOG_CFG_CHANGE_EVENT_DATA1_PFC_WD_COS_PFC_WD_COS5 \
6665 /* 1 means PFC WD for COS6 is on, 0 - off. */
6666 #define HWRM_ASYNC_EVENT_CMPL_PFC_WATCHDOG_CFG_CHANGE_EVENT_DATA1_PFC_WD_COS_PFC_WD_COS6 \
6668 /* 1 means PFC WD for COS7 is on, 0 - off. */
6669 #define HWRM_ASYNC_EVENT_CMPL_PFC_WATCHDOG_CFG_CHANGE_EVENT_DATA1_PFC_WD_COS_PFC_WD_COS7 \
6672 #define HWRM_ASYNC_EVENT_CMPL_PFC_WATCHDOG_CFG_CHANGE_EVENT_DATA1_PORT_ID_MASK \
6674 #define HWRM_ASYNC_EVENT_CMPL_PFC_WATCHDOG_CFG_CHANGE_EVENT_DATA1_PORT_ID_SFT \
6678 /* hwrm_async_event_cmpl_fw_trace_msg (size:128b/16B) */
6679 struct hwrm_async_event_cmpl_fw_trace_msg {
6682 * This field indicates the exact type of the completion.
6683 * By convention, the LSB identifies the length of the
6684 * record in 16B units. Even values indicate 16B
6685 * records. Odd values indicate 32B
6688 #define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_TYPE_MASK \
6690 #define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_TYPE_SFT 0
6691 /* HWRM Asynchronous Event Information */
6692 #define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_TYPE_HWRM_ASYNC_EVENT \
6694 #define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_TYPE_LAST \
6695 HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_TYPE_HWRM_ASYNC_EVENT
6696 /* Identifiers of events. */
6698 /* Firmware trace log message */
6699 #define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_EVENT_ID_FW_TRACE_MSG \
6701 #define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_EVENT_ID_LAST \
6702 HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_EVENT_ID_FW_TRACE_MSG
6703 /* Trace byte 0 to 3 */
6704 uint32_t event_data2;
6706 #define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_EVENT_DATA2_BYTE0_MASK \
6708 #define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_EVENT_DATA2_BYTE0_SFT 0
6710 #define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_EVENT_DATA2_BYTE1_MASK \
6712 #define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_EVENT_DATA2_BYTE1_SFT 8
6714 #define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_EVENT_DATA2_BYTE2_MASK \
6716 #define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_EVENT_DATA2_BYTE2_SFT 16
6718 #define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_EVENT_DATA2_BYTE3_MASK \
6719 UINT32_C(0xff000000)
6720 #define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_EVENT_DATA2_BYTE3_SFT 24
6723 * This value is written by the NIC such that it will be different
6724 * for each pass through the completion queue. The even passes
6725 * will write 1. The odd passes will write 0.
6727 #define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_V UINT32_C(0x1)
6729 #define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_OPAQUE_MASK UINT32_C(0xfe)
6730 #define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_OPAQUE_SFT 1
6732 uint8_t timestamp_lo;
6733 /* Indicates if the string is partial or complete. */
6734 #define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_TIMESTAMP_LO_STRING \
6736 /* Complete string */
6737 #define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_TIMESTAMP_LO_STRING_COMPLETE \
6739 /* Partial string */
6740 #define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_TIMESTAMP_LO_STRING_PARTIAL \
6742 #define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_TIMESTAMP_LO_STRING_LAST \
6743 HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_TIMESTAMP_LO_STRING_PARTIAL
6744 /* Indicates the firmware that sent the trace message. */
6745 #define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_TIMESTAMP_LO_FIRMWARE \
6747 /* Primary firmware */
6748 #define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_TIMESTAMP_LO_FIRMWARE_PRIMARY \
6749 (UINT32_C(0x0) << 1)
6750 /* Secondary firmware */
6751 #define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_TIMESTAMP_LO_FIRMWARE_SECONDARY \
6752 (UINT32_C(0x1) << 1)
6753 #define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_TIMESTAMP_LO_FIRMWARE_LAST \
6754 HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_TIMESTAMP_LO_FIRMWARE_SECONDARY
6755 /* Trace byte 4 to 5 */
6756 uint16_t timestamp_hi;
6758 #define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_TIMESTAMP_HI_BYTE4_MASK \
6760 #define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_TIMESTAMP_HI_BYTE4_SFT 0
6762 #define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_TIMESTAMP_HI_BYTE5_MASK \
6764 #define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_TIMESTAMP_HI_BYTE5_SFT 8
6765 /* Trace byte 6 to 9 */
6766 uint32_t event_data1;
6768 #define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_EVENT_DATA1_BYTE6_MASK \
6770 #define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_EVENT_DATA1_BYTE6_SFT 0
6772 #define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_EVENT_DATA1_BYTE7_MASK \
6774 #define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_EVENT_DATA1_BYTE7_SFT 8
6776 #define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_EVENT_DATA1_BYTE8_MASK \
6778 #define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_EVENT_DATA1_BYTE8_SFT 16
6780 #define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_EVENT_DATA1_BYTE9_MASK \
6781 UINT32_C(0xff000000)
6782 #define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_EVENT_DATA1_BYTE9_SFT 24
6785 /* hwrm_async_event_cmpl_hwrm_error (size:128b/16B) */
6786 struct hwrm_async_event_cmpl_hwrm_error {
6789 * This field indicates the exact type of the completion.
6790 * By convention, the LSB identifies the length of the
6791 * record in 16B units. Even values indicate 16B
6792 * records. Odd values indicate 32B
6795 #define HWRM_ASYNC_EVENT_CMPL_HWRM_ERROR_TYPE_MASK \
6797 #define HWRM_ASYNC_EVENT_CMPL_HWRM_ERROR_TYPE_SFT 0
6798 /* HWRM Asynchronous Event Information */
6799 #define HWRM_ASYNC_EVENT_CMPL_HWRM_ERROR_TYPE_HWRM_ASYNC_EVENT \
6801 #define HWRM_ASYNC_EVENT_CMPL_HWRM_ERROR_TYPE_LAST \
6802 HWRM_ASYNC_EVENT_CMPL_HWRM_ERROR_TYPE_HWRM_ASYNC_EVENT
6803 /* Identifiers of events. */
6806 #define HWRM_ASYNC_EVENT_CMPL_HWRM_ERROR_EVENT_ID_HWRM_ERROR \
6808 #define HWRM_ASYNC_EVENT_CMPL_HWRM_ERROR_EVENT_ID_LAST \
6809 HWRM_ASYNC_EVENT_CMPL_HWRM_ERROR_EVENT_ID_HWRM_ERROR
6810 /* Event specific data */
6811 uint32_t event_data2;
6812 /* Severity of HWRM Error */
6813 #define HWRM_ASYNC_EVENT_CMPL_HWRM_ERROR_EVENT_DATA2_SEVERITY_MASK \
6815 #define HWRM_ASYNC_EVENT_CMPL_HWRM_ERROR_EVENT_DATA2_SEVERITY_SFT 0
6817 #define HWRM_ASYNC_EVENT_CMPL_HWRM_ERROR_EVENT_DATA2_SEVERITY_WARNING \
6819 /* Non-fatal Error */
6820 #define HWRM_ASYNC_EVENT_CMPL_HWRM_ERROR_EVENT_DATA2_SEVERITY_NONFATAL \
6823 #define HWRM_ASYNC_EVENT_CMPL_HWRM_ERROR_EVENT_DATA2_SEVERITY_FATAL \
6825 #define HWRM_ASYNC_EVENT_CMPL_HWRM_ERROR_EVENT_DATA2_SEVERITY_LAST \
6826 HWRM_ASYNC_EVENT_CMPL_HWRM_ERROR_EVENT_DATA2_SEVERITY_FATAL
6829 * This value is written by the NIC such that it will be different
6830 * for each pass through the completion queue. The even passes
6831 * will write 1. The odd passes will write 0.
6833 #define HWRM_ASYNC_EVENT_CMPL_HWRM_ERROR_V UINT32_C(0x1)
6835 #define HWRM_ASYNC_EVENT_CMPL_HWRM_ERROR_OPAQUE_MASK UINT32_C(0xfe)
6836 #define HWRM_ASYNC_EVENT_CMPL_HWRM_ERROR_OPAQUE_SFT 1
6837 /* 8-lsb timestamp from POR (100-msec resolution) */
6838 uint8_t timestamp_lo;
6839 /* 16-lsb timestamp from POR (100-msec resolution) */
6840 uint16_t timestamp_hi;
6841 /* Event specific data */
6842 uint32_t event_data1;
6843 /* Time stamp for error event */
6844 #define HWRM_ASYNC_EVENT_CMPL_HWRM_ERROR_EVENT_DATA1_TIMESTAMP \
6848 /*******************
6850 *******************/
6853 /* hwrm_func_reset_input (size:192b/24B) */
6854 struct hwrm_func_reset_input {
6855 /* The HWRM command request type. */
6858 * The completion ring to send the completion event on. This should
6859 * be the NQ ID returned from the `nq_alloc` HWRM command.
6863 * The sequence ID is used by the driver for tracking multiple
6864 * commands. This ID is treated as opaque data by the firmware and
6865 * the value is returned in the `hwrm_resp_hdr` upon completion.
6869 * The target ID of the command:
6870 * * 0x0-0xFFF8 - The function ID
6871 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
6872 * * 0xFFFD - Reserved for user-space HWRM interface
6877 * A physical address pointer pointing to a host buffer that the
6878 * command's response data will be written. This can be either a host
6879 * physical address (HPA) or a guest physical address (GPA) and must
6880 * point to a physically contiguous block of memory.
6885 * This bit must be '1' for the vf_id_valid field to be
6888 #define HWRM_FUNC_RESET_INPUT_ENABLES_VF_ID_VALID UINT32_C(0x1)
6890 * The ID of the VF that this PF is trying to reset.
6891 * Only the parent PF shall be allowed to reset a child VF.
6893 * A parent PF driver shall use this field only when a specific child VF
6894 * is requested to be reset.
6897 /* This value indicates the level of a function reset. */
6898 uint8_t func_reset_level;
6900 * Reset the caller function and its children VFs (if any). If no
6901 * children functions exist, then reset the caller function only.
6903 #define HWRM_FUNC_RESET_INPUT_FUNC_RESET_LEVEL_RESETALL \
6905 /* Reset the caller function only */
6906 #define HWRM_FUNC_RESET_INPUT_FUNC_RESET_LEVEL_RESETME \
6909 * Reset all children VFs of the caller function driver if the
6910 * caller is a PF driver.
6911 * It is an error to specify this level by a VF driver.
6912 * It is an error to specify this level by a PF driver with
6915 #define HWRM_FUNC_RESET_INPUT_FUNC_RESET_LEVEL_RESETCHILDREN \
6918 * Reset a specific VF of the caller function driver if the caller
6919 * is the parent PF driver.
6920 * It is an error to specify this level by a VF driver.
6921 * It is an error to specify this level by a PF driver that is not
6922 * the parent of the VF that is being requested to reset.
6924 #define HWRM_FUNC_RESET_INPUT_FUNC_RESET_LEVEL_RESETVF \
6926 #define HWRM_FUNC_RESET_INPUT_FUNC_RESET_LEVEL_LAST \
6927 HWRM_FUNC_RESET_INPUT_FUNC_RESET_LEVEL_RESETVF
6931 /* hwrm_func_reset_output (size:128b/16B) */
6932 struct hwrm_func_reset_output {
6933 /* The specific error status for the command. */
6934 uint16_t error_code;
6935 /* The HWRM command request type. */
6937 /* The sequence ID from the original command. */
6939 /* The length of the response data in number of bytes. */
6941 uint8_t unused_0[7];
6943 * This field is used in Output records to indicate that the output
6944 * is completely written to RAM. This field should be read as '1'
6945 * to indicate that the output has been completely written.
6946 * When writing a command completion or response to an internal processor,
6947 * the order of writes has to be such that this field is written last.
6952 /********************
6953 * hwrm_func_getfid *
6954 ********************/
6957 /* hwrm_func_getfid_input (size:192b/24B) */
6958 struct hwrm_func_getfid_input {
6959 /* The HWRM command request type. */
6962 * The completion ring to send the completion event on. This should
6963 * be the NQ ID returned from the `nq_alloc` HWRM command.
6967 * The sequence ID is used by the driver for tracking multiple
6968 * commands. This ID is treated as opaque data by the firmware and
6969 * the value is returned in the `hwrm_resp_hdr` upon completion.
6973 * The target ID of the command:
6974 * * 0x0-0xFFF8 - The function ID
6975 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
6976 * * 0xFFFD - Reserved for user-space HWRM interface
6981 * A physical address pointer pointing to a host buffer that the
6982 * command's response data will be written. This can be either a host
6983 * physical address (HPA) or a guest physical address (GPA) and must
6984 * point to a physically contiguous block of memory.
6989 * This bit must be '1' for the pci_id field to be
6992 #define HWRM_FUNC_GETFID_INPUT_ENABLES_PCI_ID UINT32_C(0x1)
6994 * This value is the PCI ID of the queried function.
6995 * If ARI is enabled, then it is
6996 * Bus Number (8b):Function Number(8b). Otherwise, it is
6997 * Bus Number (8b):Device Number (5b):Function Number(3b).
7000 uint8_t unused_0[2];
7003 /* hwrm_func_getfid_output (size:128b/16B) */
7004 struct hwrm_func_getfid_output {
7005 /* The specific error status for the command. */
7006 uint16_t error_code;
7007 /* The HWRM command request type. */
7009 /* The sequence ID from the original command. */
7011 /* The length of the response data in number of bytes. */
7014 * FID value. This value is used to identify operations on the PCI
7015 * bus as belonging to a particular PCI function.
7018 uint8_t unused_0[5];
7020 * This field is used in Output records to indicate that the output
7021 * is completely written to RAM. This field should be read as '1'
7022 * to indicate that the output has been completely written.
7023 * When writing a command completion or response to an internal processor,
7024 * the order of writes has to be such that this field is written last.
7029 /**********************
7030 * hwrm_func_vf_alloc *
7031 **********************/
7034 /* hwrm_func_vf_alloc_input (size:192b/24B) */
7035 struct hwrm_func_vf_alloc_input {
7036 /* The HWRM command request type. */
7039 * The completion ring to send the completion event on. This should
7040 * be the NQ ID returned from the `nq_alloc` HWRM command.
7044 * The sequence ID is used by the driver for tracking multiple
7045 * commands. This ID is treated as opaque data by the firmware and
7046 * the value is returned in the `hwrm_resp_hdr` upon completion.
7050 * The target ID of the command:
7051 * * 0x0-0xFFF8 - The function ID
7052 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
7053 * * 0xFFFD - Reserved for user-space HWRM interface
7058 * A physical address pointer pointing to a host buffer that the
7059 * command's response data will be written. This can be either a host
7060 * physical address (HPA) or a guest physical address (GPA) and must
7061 * point to a physically contiguous block of memory.
7066 * This bit must be '1' for the first_vf_id field to be
7069 #define HWRM_FUNC_VF_ALLOC_INPUT_ENABLES_FIRST_VF_ID UINT32_C(0x1)
7071 * This value is used to identify a Virtual Function (VF).
7072 * The scope of VF ID is local within a PF.
7074 uint16_t first_vf_id;
7075 /* The number of virtual functions requested. */
7079 /* hwrm_func_vf_alloc_output (size:128b/16B) */
7080 struct hwrm_func_vf_alloc_output {
7081 /* The specific error status for the command. */
7082 uint16_t error_code;
7083 /* The HWRM command request type. */
7085 /* The sequence ID from the original command. */
7087 /* The length of the response data in number of bytes. */
7089 /* The ID of the first VF allocated. */
7090 uint16_t first_vf_id;
7091 uint8_t unused_0[5];
7093 * This field is used in Output records to indicate that the output
7094 * is completely written to RAM. This field should be read as '1'
7095 * to indicate that the output has been completely written.
7096 * When writing a command completion or response to an internal processor,
7097 * the order of writes has to be such that this field is written last.
7102 /*********************
7103 * hwrm_func_vf_free *
7104 *********************/
7107 /* hwrm_func_vf_free_input (size:192b/24B) */
7108 struct hwrm_func_vf_free_input {
7109 /* The HWRM command request type. */
7112 * The completion ring to send the completion event on. This should
7113 * be the NQ ID returned from the `nq_alloc` HWRM command.
7117 * The sequence ID is used by the driver for tracking multiple
7118 * commands. This ID is treated as opaque data by the firmware and
7119 * the value is returned in the `hwrm_resp_hdr` upon completion.
7123 * The target ID of the command:
7124 * * 0x0-0xFFF8 - The function ID
7125 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
7126 * * 0xFFFD - Reserved for user-space HWRM interface
7131 * A physical address pointer pointing to a host buffer that the
7132 * command's response data will be written. This can be either a host
7133 * physical address (HPA) or a guest physical address (GPA) and must
7134 * point to a physically contiguous block of memory.
7139 * This bit must be '1' for the first_vf_id field to be
7142 #define HWRM_FUNC_VF_FREE_INPUT_ENABLES_FIRST_VF_ID UINT32_C(0x1)
7144 * This value is used to identify a Virtual Function (VF).
7145 * The scope of VF ID is local within a PF.
7147 uint16_t first_vf_id;
7149 * The number of virtual functions requested.
7150 * 0xFFFF - Cleanup all children of this PF.
7155 /* hwrm_func_vf_free_output (size:128b/16B) */
7156 struct hwrm_func_vf_free_output {
7157 /* The specific error status for the command. */
7158 uint16_t error_code;
7159 /* The HWRM command request type. */
7161 /* The sequence ID from the original command. */
7163 /* The length of the response data in number of bytes. */
7165 uint8_t unused_0[7];
7167 * This field is used in Output records to indicate that the output
7168 * is completely written to RAM. This field should be read as '1'
7169 * to indicate that the output has been completely written.
7170 * When writing a command completion or response to an internal processor,
7171 * the order of writes has to be such that this field is written last.
7176 /********************
7177 * hwrm_func_vf_cfg *
7178 ********************/
7181 /* hwrm_func_vf_cfg_input (size:448b/56B) */
7182 struct hwrm_func_vf_cfg_input {
7183 /* The HWRM command request type. */
7186 * The completion ring to send the completion event on. This should
7187 * be the NQ ID returned from the `nq_alloc` HWRM command.
7191 * The sequence ID is used by the driver for tracking multiple
7192 * commands. This ID is treated as opaque data by the firmware and
7193 * the value is returned in the `hwrm_resp_hdr` upon completion.
7197 * The target ID of the command:
7198 * * 0x0-0xFFF8 - The function ID
7199 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
7200 * * 0xFFFD - Reserved for user-space HWRM interface
7205 * A physical address pointer pointing to a host buffer that the
7206 * command's response data will be written. This can be either a host
7207 * physical address (HPA) or a guest physical address (GPA) and must
7208 * point to a physically contiguous block of memory.
7213 * This bit must be '1' for the mtu field to be
7216 #define HWRM_FUNC_VF_CFG_INPUT_ENABLES_MTU \
7219 * This bit must be '1' for the guest_vlan field to be
7222 #define HWRM_FUNC_VF_CFG_INPUT_ENABLES_GUEST_VLAN \
7225 * This bit must be '1' for the async_event_cr field to be
7228 #define HWRM_FUNC_VF_CFG_INPUT_ENABLES_ASYNC_EVENT_CR \
7231 * This bit must be '1' for the dflt_mac_addr field to be
7234 #define HWRM_FUNC_VF_CFG_INPUT_ENABLES_DFLT_MAC_ADDR \
7237 * This bit must be '1' for the num_rsscos_ctxs field to be
7240 #define HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_RSSCOS_CTXS \
7243 * This bit must be '1' for the num_cmpl_rings field to be
7246 #define HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_CMPL_RINGS \
7249 * This bit must be '1' for the num_tx_rings field to be
7252 #define HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_TX_RINGS \
7255 * This bit must be '1' for the num_rx_rings field to be
7258 #define HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_RX_RINGS \
7261 * This bit must be '1' for the num_l2_ctxs field to be
7264 #define HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_L2_CTXS \
7267 * This bit must be '1' for the num_vnics field to be
7270 #define HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_VNICS \
7273 * This bit must be '1' for the num_stat_ctxs field to be
7276 #define HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_STAT_CTXS \
7279 * This bit must be '1' for the num_hw_ring_grps field to be
7282 #define HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_HW_RING_GRPS \
7285 * The maximum transmission unit requested on the function.
7286 * The HWRM should make sure that the mtu of
7287 * the function does not exceed the mtu of the physical
7288 * port that this function is associated with.
7290 * In addition to requesting mtu per function, it is
7291 * possible to configure mtu per transmit ring.
7292 * By default, the mtu of each transmit ring associated
7293 * with a function is equal to the mtu of the function.
7294 * The HWRM should make sure that the mtu of each transmit
7295 * ring that is assigned to a function has a valid mtu.
7299 * The guest VLAN for the function being configured.
7300 * This field's format is same as 802.1Q Tag's
7301 * Tag Control Information (TCI) format that includes both
7302 * Priority Code Point (PCP) and VLAN Identifier (VID).
7304 uint16_t guest_vlan;
7306 * ID of the target completion ring for receiving asynchronous
7307 * event completions. If this field is not valid, then the
7308 * HWRM shall use the default completion ring of the function
7309 * that is being configured as the target completion ring for
7310 * providing any asynchronous event completions for that
7312 * If this field is valid, then the HWRM shall use the
7313 * completion ring identified by this ID as the target
7314 * completion ring for providing any asynchronous event
7315 * completions for the function that is being configured.
7317 uint16_t async_event_cr;
7319 * This value is the current MAC address requested by the VF
7320 * driver to be configured on this VF. A value of
7321 * 00-00-00-00-00-00 indicates no MAC address configuration
7322 * is requested by the VF driver.
7323 * The parent PF driver may reject or overwrite this
7326 uint8_t dflt_mac_addr[6];
7329 * This bit requests that the firmware test to see if all the assets
7330 * requested in this command (i.e. number of TX rings) are available.
7331 * The firmware will return an error if the requested assets are
7332 * not available. The firwmare will NOT reserve the assets if they
7335 #define HWRM_FUNC_VF_CFG_INPUT_FLAGS_TX_ASSETS_TEST \
7338 * This bit requests that the firmware test to see if all the assets
7339 * requested in this command (i.e. number of RX rings) are available.
7340 * The firmware will return an error if the requested assets are
7341 * not available. The firwmare will NOT reserve the assets if they
7344 #define HWRM_FUNC_VF_CFG_INPUT_FLAGS_RX_ASSETS_TEST \
7347 * This bit requests that the firmware test to see if all the assets
7348 * requested in this command (i.e. number of CMPL rings) are available.
7349 * The firmware will return an error if the requested assets are
7350 * not available. The firwmare will NOT reserve the assets if they
7353 #define HWRM_FUNC_VF_CFG_INPUT_FLAGS_CMPL_ASSETS_TEST \
7356 * This bit requests that the firmware test to see if all the assets
7357 * requested in this command (i.e. number of RSS ctx) are available.
7358 * The firmware will return an error if the requested assets are
7359 * not available. The firwmare will NOT reserve the assets if they
7362 #define HWRM_FUNC_VF_CFG_INPUT_FLAGS_RSSCOS_CTX_ASSETS_TEST \
7365 * This bit requests that the firmware test to see if all the assets
7366 * requested in this command (i.e. number of ring groups) are available.
7367 * The firmware will return an error if the requested assets are
7368 * not available. The firwmare will NOT reserve the assets if they
7371 #define HWRM_FUNC_VF_CFG_INPUT_FLAGS_RING_GRP_ASSETS_TEST \
7374 * This bit requests that the firmware test to see if all the assets
7375 * requested in this command (i.e. number of stat ctx) are available.
7376 * The firmware will return an error if the requested assets are
7377 * not available. The firwmare will NOT reserve the assets if they
7380 #define HWRM_FUNC_VF_CFG_INPUT_FLAGS_STAT_CTX_ASSETS_TEST \
7383 * This bit requests that the firmware test to see if all the assets
7384 * requested in this command (i.e. number of VNICs) are available.
7385 * The firmware will return an error if the requested assets are
7386 * not available. The firwmare will NOT reserve the assets if they
7389 #define HWRM_FUNC_VF_CFG_INPUT_FLAGS_VNIC_ASSETS_TEST \
7392 * This bit requests that the firmware test to see if all the assets
7393 * requested in this command (i.e. number of L2 ctx) are available.
7394 * The firmware will return an error if the requested assets are
7395 * not available. The firwmare will NOT reserve the assets if they
7398 #define HWRM_FUNC_VF_CFG_INPUT_FLAGS_L2_CTX_ASSETS_TEST \
7400 /* The number of RSS/COS contexts requested for the VF. */
7401 uint16_t num_rsscos_ctxs;
7402 /* The number of completion rings requested for the VF. */
7403 uint16_t num_cmpl_rings;
7404 /* The number of transmit rings requested for the VF. */
7405 uint16_t num_tx_rings;
7406 /* The number of receive rings requested for the VF. */
7407 uint16_t num_rx_rings;
7408 /* The number of L2 contexts requested for the VF. */
7409 uint16_t num_l2_ctxs;
7410 /* The number of vnics requested for the VF. */
7412 /* The number of statistic contexts requested for the VF. */
7413 uint16_t num_stat_ctxs;
7414 /* The number of HW ring groups requested for the VF. */
7415 uint16_t num_hw_ring_grps;
7416 uint8_t unused_0[4];
7419 /* hwrm_func_vf_cfg_output (size:128b/16B) */
7420 struct hwrm_func_vf_cfg_output {
7421 /* The specific error status for the command. */
7422 uint16_t error_code;
7423 /* The HWRM command request type. */
7425 /* The sequence ID from the original command. */
7427 /* The length of the response data in number of bytes. */
7429 uint8_t unused_0[7];
7431 * This field is used in Output records to indicate that the output
7432 * is completely written to RAM. This field should be read as '1'
7433 * to indicate that the output has been completely written.
7434 * When writing a command completion or response to an internal processor,
7435 * the order of writes has to be such that this field is written last.
7440 /*******************
7442 *******************/
7445 /* hwrm_func_qcaps_input (size:192b/24B) */
7446 struct hwrm_func_qcaps_input {
7447 /* The HWRM command request type. */
7450 * The completion ring to send the completion event on. This should
7451 * be the NQ ID returned from the `nq_alloc` HWRM command.
7455 * The sequence ID is used by the driver for tracking multiple
7456 * commands. This ID is treated as opaque data by the firmware and
7457 * the value is returned in the `hwrm_resp_hdr` upon completion.
7461 * The target ID of the command:
7462 * * 0x0-0xFFF8 - The function ID
7463 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
7464 * * 0xFFFD - Reserved for user-space HWRM interface
7469 * A physical address pointer pointing to a host buffer that the
7470 * command's response data will be written. This can be either a host
7471 * physical address (HPA) or a guest physical address (GPA) and must
7472 * point to a physically contiguous block of memory.
7476 * Function ID of the function that is being queried.
7477 * 0xFF... (All Fs) if the query is for the requesting
7481 uint8_t unused_0[6];
7484 /* hwrm_func_qcaps_output (size:704b/88B) */
7485 struct hwrm_func_qcaps_output {
7486 /* The specific error status for the command. */
7487 uint16_t error_code;
7488 /* The HWRM command request type. */
7490 /* The sequence ID from the original command. */
7492 /* The length of the response data in number of bytes. */
7495 * FID value. This value is used to identify operations on the PCI
7496 * bus as belonging to a particular PCI function.
7500 * Port ID of port that this function is associated with.
7501 * Valid only for the PF.
7502 * 0xFF... (All Fs) if this function is not associated with
7504 * 0xFF... (All Fs) if this function is called from a VF.
7508 /* If 1, then Push mode is supported on this function. */
7509 #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_PUSH_MODE_SUPPORTED \
7512 * If 1, then the global MSI-X auto-masking is enabled for the
7515 #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_GLOBAL_MSIX_AUTOMASKING \
7518 * If 1, then the Precision Time Protocol (PTP) processing
7519 * is supported on this function.
7520 * The HWRM should enable PTP on only a single Physical
7521 * Function (PF) per port.
7523 #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_PTP_SUPPORTED \
7526 * If 1, then RDMA over Converged Ethernet (RoCE) v1
7527 * is supported on this function.
7529 #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_ROCE_V1_SUPPORTED \
7532 * If 1, then RDMA over Converged Ethernet (RoCE) v2
7533 * is supported on this function.
7535 #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_ROCE_V2_SUPPORTED \
7538 * If 1, then control and configuration of WoL magic packet
7539 * are supported on this function.
7541 #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_WOL_MAGICPKT_SUPPORTED \
7544 * If 1, then control and configuration of bitmap pattern
7545 * packet are supported on this function.
7547 #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_WOL_BMP_SUPPORTED \
7550 * If set to 1, then the control and configuration of rate limit
7551 * of an allocated TX ring on the queried function is supported.
7553 #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_TX_RING_RL_SUPPORTED \
7556 * If 1, then control and configuration of minimum and
7557 * maximum bandwidths are supported on the queried function.
7559 #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_TX_BW_CFG_SUPPORTED \
7562 * If the query is for a VF, then this flag shall be ignored.
7563 * If this query is for a PF and this flag is set to 1,
7564 * then the PF has the capability to set the rate limits
7565 * on the TX rings of its children VFs.
7566 * If this query is for a PF and this flag is set to 0, then
7567 * the PF does not have the capability to set the rate limits
7568 * on the TX rings of its children VFs.
7570 #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_VF_TX_RING_RL_SUPPORTED \
7573 * If the query is for a VF, then this flag shall be ignored.
7574 * If this query is for a PF and this flag is set to 1,
7575 * then the PF has the capability to set the minimum and/or
7576 * maximum bandwidths for its children VFs.
7577 * If this query is for a PF and this flag is set to 0, then
7578 * the PF does not have the capability to set the minimum or
7579 * maximum bandwidths for its children VFs.
7581 #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_VF_BW_CFG_SUPPORTED \
7584 * Standard TX Ring mode is used for the allocation of TX ring
7585 * and underlying scheduling resources that allow bandwidth
7586 * reservation and limit settings on the queried function.
7587 * If set to 1, then standard TX ring mode is supported
7588 * on the queried function.
7589 * If set to 0, then standard TX ring mode is not available
7590 * on the queried function.
7592 #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_STD_TX_RING_MODE_SUPPORTED \
7595 * If the query is for a VF, then this flag shall be ignored,
7596 * If this query is for a PF and this flag is set to 1,
7597 * then the PF has the capability to detect GENEVE tunnel
7600 #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_GENEVE_TUN_FLAGS_SUPPORTED \
7603 * If the query is for a VF, then this flag shall be ignored,
7604 * If this query is for a PF and this flag is set to 1,
7605 * then the PF has the capability to detect NVGRE tunnel
7608 #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_NVGRE_TUN_FLAGS_SUPPORTED \
7611 * If the query is for a VF, then this flag shall be ignored,
7612 * If this query is for a PF and this flag is set to 1,
7613 * then the PF has the capability to detect GRE tunnel
7616 #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_GRE_TUN_FLAGS_SUPPORTED \
7619 * If the query is for a VF, then this flag shall be ignored,
7620 * If this query is for a PF and this flag is set to 1,
7621 * then the PF has the capability to detect MPLS tunnel
7624 #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_MPLS_TUN_FLAGS_SUPPORTED \
7627 * If the query is for a VF, then this flag shall be ignored,
7628 * If this query is for a PF and this flag is set to 1,
7629 * then the PF has the capability to support pcie stats.
7631 #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_PCIE_STATS_SUPPORTED \
7634 * If the query is for a VF, then this flag shall be ignored,
7635 * If this query is for a PF and this flag is set to 1,
7636 * then the PF has the capability to adopt the VF's belonging
7639 #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_ADOPTED_PF_SUPPORTED \
7642 * If the query is for a VF, then this flag shall be ignored,
7643 * If this query is for a PF and this flag is set to 1,
7644 * then the PF has the administrative privilege to configure another PF
7646 #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_ADMIN_PF_SUPPORTED \
7649 * If the query is for a VF, then this flag shall be ignored.
7650 * If this query is for a PF and this flag is set to 1, then
7651 * the PF will know that the firmware has the capability to track
7652 * the virtual link status.
7654 #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_LINK_ADMIN_STATUS_SUPPORTED \
7657 * If 1, then this function supports the push mode that uses
7658 * write combine buffers and the long inline tx buffer descriptor.
7660 #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_WCB_PUSH_MODE \
7663 * If 1, then FW has capability to allocate TX rings dynamically
7664 * in ring alloc even if PF reserved pool is zero.
7665 * This bit will be used only for PFs.
7667 #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_DYNAMIC_TX_RING_ALLOC \
7670 * When this bit is '1', it indicates that core firmware is
7671 * capable of Hot Reset.
7673 #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_HOT_RESET_CAPABLE \
7676 * This flag will be set to 1 by the FW if FW supports adapter error
7679 #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_ERROR_RECOVERY_CAPABLE \
7682 * If the query is for a VF, then this flag shall be ignored.
7683 * If this query is for a PF and this flag is set to 1, then
7684 * the PF has the capability to support extended stats.
7686 #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_EXT_STATS_SUPPORTED \
7689 * If the query is for a VF, then this flag shall be ignored.
7690 * If this query is for a PF and this flag is set to 1, then host
7691 * must initiate reset or reload (or fastboot) the firmware image
7692 * upon detection of device shutdown state.
7694 #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_ERR_RECOVER_RELOAD \
7697 * If the query is for a VF, then this flag (always set to 0) shall
7698 * be ignored. If this query is for a PF and this flag is set to 1,
7699 * host, when registered for the default vnic change async event,
7700 * receives async notification whenever a default vnic state is
7701 * changed for any of child or adopted VFs.
7703 #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_NOTIFY_VF_DEF_VNIC_CHNG_SUPPORTED \
7705 /* If set to 1, then the vlan acceleration for TX is disabled. */
7706 #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_VLAN_ACCELERATION_TX_DISABLED \
7709 * When this bit is '1', it indicates that core firmware supports
7710 * DBG_COREDUMP_XXX commands.
7712 #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_COREDUMP_CMD_SUPPORTED \
7713 UINT32_C(0x10000000)
7715 * When this bit is '1', it indicates that core firmware supports
7716 * DBG_CRASHDUMP_XXX commands.
7718 #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_CRASHDUMP_CMD_SUPPORTED \
7719 UINT32_C(0x20000000)
7721 * If the query is for a VF, then this flag should be ignored.
7722 * If the query is for a PF and this flag is set to 1, then
7723 * the PF has the capability to support retrieval of
7724 * rx_port_stats_ext_pfc_wd statistics (supported by the PFC
7725 * WatchDog feature) via the hwrm_port_qstats_ext_pfc_wd command.
7726 * If this flag is set to 1, only that (supported) command should
7727 * be used for retrieval of PFC related statistics (rather than
7728 * hwrm_port_qstats_ext command, which could previously be used).
7730 #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_PFC_WD_STATS_SUPPORTED \
7731 UINT32_C(0x40000000)
7733 * This value is current MAC address configured for this
7734 * function. A value of 00-00-00-00-00-00 indicates no
7735 * MAC address is currently configured.
7737 uint8_t mac_address[6];
7739 * The maximum number of RSS/COS contexts that can be
7740 * allocated to the function.
7742 uint16_t max_rsscos_ctx;
7744 * The maximum number of completion rings that can be
7745 * allocated to the function.
7747 uint16_t max_cmpl_rings;
7749 * The maximum number of transmit rings that can be
7750 * allocated to the function.
7752 uint16_t max_tx_rings;
7754 * The maximum number of receive rings that can be
7755 * allocated to the function.
7757 uint16_t max_rx_rings;
7759 * The maximum number of L2 contexts that can be
7760 * allocated to the function.
7762 uint16_t max_l2_ctxs;
7764 * The maximum number of VNICs that can be
7765 * allocated to the function.
7769 * The identifier for the first VF enabled on a PF. This
7770 * is valid only on the PF with SR-IOV enabled.
7771 * 0xFF... (All Fs) if this command is called on a PF with
7772 * SR-IOV disabled or on a VF.
7774 uint16_t first_vf_id;
7776 * The maximum number of VFs that can be
7777 * allocated to the function. This is valid only on the
7778 * PF with SR-IOV enabled. 0xFF... (All Fs) if this
7779 * command is called on a PF with SR-IOV disabled or
7784 * The maximum number of statistic contexts that can be
7785 * allocated to the function.
7787 uint16_t max_stat_ctx;
7789 * The maximum number of Encapsulation records that can be
7790 * offloaded by this function.
7792 uint32_t max_encap_records;
7794 * The maximum number of decapsulation records that can
7795 * be offloaded by this function.
7797 uint32_t max_decap_records;
7799 * The maximum number of Exact Match (EM) flows that can be
7800 * offloaded by this function on the TX side.
7802 uint32_t max_tx_em_flows;
7804 * The maximum number of Wildcard Match (WM) flows that can
7805 * be offloaded by this function on the TX side.
7807 uint32_t max_tx_wm_flows;
7809 * The maximum number of Exact Match (EM) flows that can be
7810 * offloaded by this function on the RX side.
7812 uint32_t max_rx_em_flows;
7814 * The maximum number of Wildcard Match (WM) flows that can
7815 * be offloaded by this function on the RX side.
7817 uint32_t max_rx_wm_flows;
7819 * The maximum number of multicast filters that can
7820 * be supported by this function on the RX side.
7822 uint32_t max_mcast_filters;
7824 * The maximum value of flow_id that can be supported
7825 * in completion records.
7827 uint32_t max_flow_id;
7829 * The maximum number of HW ring groups that can be
7830 * supported on this function.
7832 uint32_t max_hw_ring_grps;
7834 * The maximum number of strict priority transmit rings
7835 * that can be allocated to the function.
7836 * This number indicates the maximum number of TX rings
7837 * that can be assigned strict priorities out of the
7838 * maximum number of TX rings that can be allocated
7839 * (max_tx_rings) to the function.
7841 uint16_t max_sp_tx_rings;
7842 uint8_t unused_0[2];
7845 * If 1, the device can be configured to set the ECN bits in the
7846 * IP header of received packets if the receive queue length
7847 * exceeds a given threshold.
7849 #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_EXT_ECN_MARK_SUPPORTED \
7852 * If 1, the device can report the number of received packets
7853 * that it marked as having experienced congestion.
7855 #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_EXT_ECN_STATS_SUPPORTED \
7857 uint8_t unused_1[3];
7859 * This field is used in Output records to indicate that the output
7860 * is completely written to RAM. This field should be read as '1'
7861 * to indicate that the output has been completely written.
7862 * When writing a command completion or response to an internal processor,
7863 * the order of writes has to be such that this field is written last.
7873 /* hwrm_func_qcfg_input (size:192b/24B) */
7874 struct hwrm_func_qcfg_input {
7875 /* The HWRM command request type. */
7878 * The completion ring to send the completion event on. This should
7879 * be the NQ ID returned from the `nq_alloc` HWRM command.
7883 * The sequence ID is used by the driver for tracking multiple
7884 * commands. This ID is treated as opaque data by the firmware and
7885 * the value is returned in the `hwrm_resp_hdr` upon completion.
7889 * The target ID of the command:
7890 * * 0x0-0xFFF8 - The function ID
7891 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
7892 * * 0xFFFD - Reserved for user-space HWRM interface
7897 * A physical address pointer pointing to a host buffer that the
7898 * command's response data will be written. This can be either a host
7899 * physical address (HPA) or a guest physical address (GPA) and must
7900 * point to a physically contiguous block of memory.
7904 * Function ID of the function that is being queried.
7905 * 0xFF... (All Fs) if the query is for the requesting
7909 uint8_t unused_0[6];
7912 /* hwrm_func_qcfg_output (size:768b/96B) */
7913 struct hwrm_func_qcfg_output {
7914 /* The specific error status for the command. */
7915 uint16_t error_code;
7916 /* The HWRM command request type. */
7918 /* The sequence ID from the original command. */
7920 /* The length of the response data in number of bytes. */
7923 * FID value. This value is used to identify operations on the PCI
7924 * bus as belonging to a particular PCI function.
7928 * Port ID of port that this function is associated with.
7929 * 0xFF... (All Fs) if this function is not associated with
7934 * This value is the current VLAN setting for this
7935 * function. The value of 0 for this field indicates
7936 * no priority tagging or VLAN is used.
7937 * This field's format is same as 802.1Q Tag's
7938 * Tag Control Information (TCI) format that includes both
7939 * Priority Code Point (PCP) and VLAN Identifier (VID).
7944 * If 1, then magic packet based Out-Of-Box WoL is enabled on
7945 * the port associated with this function.
7947 #define HWRM_FUNC_QCFG_OUTPUT_FLAGS_OOB_WOL_MAGICPKT_ENABLED \
7950 * If 1, then bitmap pattern based Out-Of-Box WoL packet is enabled
7951 * on the port associated with this function.
7953 #define HWRM_FUNC_QCFG_OUTPUT_FLAGS_OOB_WOL_BMP_ENABLED \
7956 * If set to 1, then FW based DCBX agent is enabled and running on
7957 * the port associated with this function.
7958 * If set to 0, then DCBX agent is not running in the firmware.
7960 #define HWRM_FUNC_QCFG_OUTPUT_FLAGS_FW_DCBX_AGENT_ENABLED \
7963 * Standard TX Ring mode is used for the allocation of TX ring
7964 * and underlying scheduling resources that allow bandwidth
7965 * reservation and limit settings on the queried function.
7966 * If set to 1, then standard TX ring mode is enabled
7967 * on the queried function.
7968 * If set to 0, then the standard TX ring mode is disabled
7969 * on the queried function. In this extended TX ring resource
7970 * mode, the minimum and maximum bandwidth settings are not
7971 * supported to allow the allocation of TX rings to span multiple
7974 #define HWRM_FUNC_QCFG_OUTPUT_FLAGS_STD_TX_RING_MODE_ENABLED \
7977 * If set to 1 then FW based LLDP agent is enabled and running on
7978 * the port associated with this function.
7979 * If set to 0 then the LLDP agent is not running in the firmware.
7981 #define HWRM_FUNC_QCFG_OUTPUT_FLAGS_FW_LLDP_AGENT_ENABLED \
7984 * If set to 1, then multi-host mode is active for this function.
7985 * If set to 0, then multi-host mode is inactive for this function
7986 * or not applicable for this device.
7988 #define HWRM_FUNC_QCFG_OUTPUT_FLAGS_MULTI_HOST \
7991 * If the function that is being queried is a PF, then the HWRM shall
7992 * set this field to 0 and the HWRM client shall ignore this field.
7993 * If the function that is being queried is a VF, then the HWRM shall
7994 * set this field to 1 if the queried VF is trusted, otherwise the HWRM
7995 * shall set this field to 0.
7997 #define HWRM_FUNC_QCFG_OUTPUT_FLAGS_TRUSTED_VF \
8000 * If set to 1, then secure mode is enabled for this function or device.
8001 * If set to 0, then secure mode is disabled (or normal mode) for this
8002 * function or device.
8004 #define HWRM_FUNC_QCFG_OUTPUT_FLAGS_SECURE_MODE_ENABLED \
8007 * If set to 1, then this PF is enabled with a preboot driver that
8008 * requires access to the legacy L2 ring model and legacy 32b
8009 * doorbells. If set to 0, then this PF is not allowed to use
8010 * the legacy L2 rings. This feature is not allowed on VFs and
8011 * is only relevant for devices that require a context backing
8014 #define HWRM_FUNC_QCFG_OUTPUT_FLAGS_PREBOOT_LEGACY_L2_RINGS \
8017 * This value is current MAC address configured for this
8018 * function. A value of 00-00-00-00-00-00 indicates no
8019 * MAC address is currently configured.
8021 uint8_t mac_address[6];
8023 * This value is current PCI ID of this
8024 * function. If ARI is enabled, then it is
8025 * Bus Number (8b):Function Number(8b). Otherwise, it is
8026 * Bus Number (8b):Device Number (4b):Function Number(4b).
8027 * If multi-host mode is active, the 4 lsb will indicate
8028 * the PF index for this function.
8032 * The number of RSS/COS contexts currently
8033 * allocated to the function.
8035 uint16_t alloc_rsscos_ctx;
8037 * The number of completion rings currently allocated to
8038 * the function. This does not include the rings allocated
8039 * to any children functions if any.
8041 uint16_t alloc_cmpl_rings;
8043 * The number of transmit rings currently allocated to
8044 * the function. This does not include the rings allocated
8045 * to any children functions if any.
8047 uint16_t alloc_tx_rings;
8049 * The number of receive rings currently allocated to
8050 * the function. This does not include the rings allocated
8051 * to any children functions if any.
8053 uint16_t alloc_rx_rings;
8054 /* The allocated number of L2 contexts to the function. */
8055 uint16_t alloc_l2_ctx;
8056 /* The allocated number of vnics to the function. */
8057 uint16_t alloc_vnics;
8059 * The maximum transmission unit of the function.
8060 * If the reported mtu value is non-zero then it will used for the
8061 * rings allocated on this function. otherwise the default
8062 * value is used if ring MTU is not specified.
8066 * The maximum receive unit of the function.
8067 * For vnics allocated on this function, this default
8068 * value is used if vnic MRU is not specified.
8071 /* The statistics context assigned to a function. */
8072 uint16_t stat_ctx_id;
8074 * The HWRM shall return Unknown value for this field
8075 * when this command is used to query VF's configuration.
8077 uint8_t port_partition_type;
8078 /* Single physical function */
8079 #define HWRM_FUNC_QCFG_OUTPUT_PORT_PARTITION_TYPE_SPF UINT32_C(0x0)
8080 /* Multiple physical functions */
8081 #define HWRM_FUNC_QCFG_OUTPUT_PORT_PARTITION_TYPE_MPFS UINT32_C(0x1)
8082 /* Network Partitioning 1.0 */
8083 #define HWRM_FUNC_QCFG_OUTPUT_PORT_PARTITION_TYPE_NPAR1_0 UINT32_C(0x2)
8084 /* Network Partitioning 1.5 */
8085 #define HWRM_FUNC_QCFG_OUTPUT_PORT_PARTITION_TYPE_NPAR1_5 UINT32_C(0x3)
8086 /* Network Partitioning 2.0 */
8087 #define HWRM_FUNC_QCFG_OUTPUT_PORT_PARTITION_TYPE_NPAR2_0 UINT32_C(0x4)
8089 #define HWRM_FUNC_QCFG_OUTPUT_PORT_PARTITION_TYPE_UNKNOWN \
8091 #define HWRM_FUNC_QCFG_OUTPUT_PORT_PARTITION_TYPE_LAST \
8092 HWRM_FUNC_QCFG_OUTPUT_PORT_PARTITION_TYPE_UNKNOWN
8094 * This field will indicate number of physical functions on this port_partition.
8095 * HWRM shall return unavail (i.e. value of 0) for this field
8096 * when this command is used to query VF's configuration or
8097 * from older firmware that doesn't support this field.
8099 uint8_t port_pf_cnt;
8100 /* number of PFs is not available */
8101 #define HWRM_FUNC_QCFG_OUTPUT_PORT_PF_CNT_UNAVAIL UINT32_C(0x0)
8102 #define HWRM_FUNC_QCFG_OUTPUT_PORT_PF_CNT_LAST \
8103 HWRM_FUNC_QCFG_OUTPUT_PORT_PF_CNT_UNAVAIL
8105 * The default VNIC ID assigned to a function that is
8108 uint16_t dflt_vnic_id;
8109 uint16_t max_mtu_configured;
8111 * Minimum BW allocated for this function.
8112 * The HWRM will translate this value into byte counter and
8113 * time interval used for the scheduler inside the device.
8114 * A value of 0 indicates the minimum bandwidth is not
8118 /* The bandwidth value. */
8119 #define HWRM_FUNC_QCFG_OUTPUT_MIN_BW_BW_VALUE_MASK \
8121 #define HWRM_FUNC_QCFG_OUTPUT_MIN_BW_BW_VALUE_SFT 0
8122 /* The granularity of the value (bits or bytes). */
8123 #define HWRM_FUNC_QCFG_OUTPUT_MIN_BW_SCALE \
8124 UINT32_C(0x10000000)
8125 /* Value is in bits. */
8126 #define HWRM_FUNC_QCFG_OUTPUT_MIN_BW_SCALE_BITS \
8127 (UINT32_C(0x0) << 28)
8128 /* Value is in bytes. */
8129 #define HWRM_FUNC_QCFG_OUTPUT_MIN_BW_SCALE_BYTES \
8130 (UINT32_C(0x1) << 28)
8131 #define HWRM_FUNC_QCFG_OUTPUT_MIN_BW_SCALE_LAST \
8132 HWRM_FUNC_QCFG_OUTPUT_MIN_BW_SCALE_BYTES
8133 /* bw_value_unit is 3 b */
8134 #define HWRM_FUNC_QCFG_OUTPUT_MIN_BW_BW_VALUE_UNIT_MASK \
8135 UINT32_C(0xe0000000)
8136 #define HWRM_FUNC_QCFG_OUTPUT_MIN_BW_BW_VALUE_UNIT_SFT 29
8137 /* Value is in Mb or MB (base 10). */
8138 #define HWRM_FUNC_QCFG_OUTPUT_MIN_BW_BW_VALUE_UNIT_MEGA \
8139 (UINT32_C(0x0) << 29)
8140 /* Value is in Kb or KB (base 10). */
8141 #define HWRM_FUNC_QCFG_OUTPUT_MIN_BW_BW_VALUE_UNIT_KILO \
8142 (UINT32_C(0x2) << 29)
8143 /* Value is in bits or bytes. */
8144 #define HWRM_FUNC_QCFG_OUTPUT_MIN_BW_BW_VALUE_UNIT_BASE \
8145 (UINT32_C(0x4) << 29)
8146 /* Value is in Gb or GB (base 10). */
8147 #define HWRM_FUNC_QCFG_OUTPUT_MIN_BW_BW_VALUE_UNIT_GIGA \
8148 (UINT32_C(0x6) << 29)
8149 /* Value is in 1/100th of a percentage of total bandwidth. */
8150 #define HWRM_FUNC_QCFG_OUTPUT_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 \
8151 (UINT32_C(0x1) << 29)
8153 #define HWRM_FUNC_QCFG_OUTPUT_MIN_BW_BW_VALUE_UNIT_INVALID \
8154 (UINT32_C(0x7) << 29)
8155 #define HWRM_FUNC_QCFG_OUTPUT_MIN_BW_BW_VALUE_UNIT_LAST \
8156 HWRM_FUNC_QCFG_OUTPUT_MIN_BW_BW_VALUE_UNIT_INVALID
8158 * Maximum BW allocated for this function.
8159 * The HWRM will translate this value into byte counter and
8160 * time interval used for the scheduler inside the device.
8161 * A value of 0 indicates that the maximum bandwidth is not
8165 /* The bandwidth value. */
8166 #define HWRM_FUNC_QCFG_OUTPUT_MAX_BW_BW_VALUE_MASK \
8168 #define HWRM_FUNC_QCFG_OUTPUT_MAX_BW_BW_VALUE_SFT 0
8169 /* The granularity of the value (bits or bytes). */
8170 #define HWRM_FUNC_QCFG_OUTPUT_MAX_BW_SCALE \
8171 UINT32_C(0x10000000)
8172 /* Value is in bits. */
8173 #define HWRM_FUNC_QCFG_OUTPUT_MAX_BW_SCALE_BITS \
8174 (UINT32_C(0x0) << 28)
8175 /* Value is in bytes. */
8176 #define HWRM_FUNC_QCFG_OUTPUT_MAX_BW_SCALE_BYTES \
8177 (UINT32_C(0x1) << 28)
8178 #define HWRM_FUNC_QCFG_OUTPUT_MAX_BW_SCALE_LAST \
8179 HWRM_FUNC_QCFG_OUTPUT_MAX_BW_SCALE_BYTES
8180 /* bw_value_unit is 3 b */
8181 #define HWRM_FUNC_QCFG_OUTPUT_MAX_BW_BW_VALUE_UNIT_MASK \
8182 UINT32_C(0xe0000000)
8183 #define HWRM_FUNC_QCFG_OUTPUT_MAX_BW_BW_VALUE_UNIT_SFT 29
8184 /* Value is in Mb or MB (base 10). */
8185 #define HWRM_FUNC_QCFG_OUTPUT_MAX_BW_BW_VALUE_UNIT_MEGA \
8186 (UINT32_C(0x0) << 29)
8187 /* Value is in Kb or KB (base 10). */
8188 #define HWRM_FUNC_QCFG_OUTPUT_MAX_BW_BW_VALUE_UNIT_KILO \
8189 (UINT32_C(0x2) << 29)
8190 /* Value is in bits or bytes. */
8191 #define HWRM_FUNC_QCFG_OUTPUT_MAX_BW_BW_VALUE_UNIT_BASE \
8192 (UINT32_C(0x4) << 29)
8193 /* Value is in Gb or GB (base 10). */
8194 #define HWRM_FUNC_QCFG_OUTPUT_MAX_BW_BW_VALUE_UNIT_GIGA \
8195 (UINT32_C(0x6) << 29)
8196 /* Value is in 1/100th of a percentage of total bandwidth. */
8197 #define HWRM_FUNC_QCFG_OUTPUT_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 \
8198 (UINT32_C(0x1) << 29)
8200 #define HWRM_FUNC_QCFG_OUTPUT_MAX_BW_BW_VALUE_UNIT_INVALID \
8201 (UINT32_C(0x7) << 29)
8202 #define HWRM_FUNC_QCFG_OUTPUT_MAX_BW_BW_VALUE_UNIT_LAST \
8203 HWRM_FUNC_QCFG_OUTPUT_MAX_BW_BW_VALUE_UNIT_INVALID
8205 * This value indicates the Edge virtual bridge mode for the
8206 * domain that this function belongs to.
8209 /* No Edge Virtual Bridging (EVB) */
8210 #define HWRM_FUNC_QCFG_OUTPUT_EVB_MODE_NO_EVB UINT32_C(0x0)
8211 /* Virtual Ethernet Bridge (VEB) */
8212 #define HWRM_FUNC_QCFG_OUTPUT_EVB_MODE_VEB UINT32_C(0x1)
8213 /* Virtual Ethernet Port Aggregator (VEPA) */
8214 #define HWRM_FUNC_QCFG_OUTPUT_EVB_MODE_VEPA UINT32_C(0x2)
8215 #define HWRM_FUNC_QCFG_OUTPUT_EVB_MODE_LAST \
8216 HWRM_FUNC_QCFG_OUTPUT_EVB_MODE_VEPA
8219 * This value indicates the PCIE device cache line size.
8220 * The cache line size allows the DMA writes to terminate and
8221 * start at the cache boundary.
8223 #define HWRM_FUNC_QCFG_OUTPUT_OPTIONS_CACHE_LINESIZE_MASK \
8225 #define HWRM_FUNC_QCFG_OUTPUT_OPTIONS_CACHE_LINESIZE_SFT 0
8226 /* Cache Line Size 64 bytes */
8227 #define HWRM_FUNC_QCFG_OUTPUT_OPTIONS_CACHE_LINESIZE_SIZE_64 \
8229 /* Cache Line Size 128 bytes */
8230 #define HWRM_FUNC_QCFG_OUTPUT_OPTIONS_CACHE_LINESIZE_SIZE_128 \
8232 #define HWRM_FUNC_QCFG_OUTPUT_OPTIONS_CACHE_LINESIZE_LAST \
8233 HWRM_FUNC_QCFG_OUTPUT_OPTIONS_CACHE_LINESIZE_SIZE_128
8234 /* This value is the virtual link admin state setting. */
8235 #define HWRM_FUNC_QCFG_OUTPUT_OPTIONS_LINK_ADMIN_STATE_MASK \
8237 #define HWRM_FUNC_QCFG_OUTPUT_OPTIONS_LINK_ADMIN_STATE_SFT 2
8238 /* Admin link state is in forced down mode. */
8239 #define HWRM_FUNC_QCFG_OUTPUT_OPTIONS_LINK_ADMIN_STATE_FORCED_DOWN \
8240 (UINT32_C(0x0) << 2)
8241 /* Admin link state is in forced up mode. */
8242 #define HWRM_FUNC_QCFG_OUTPUT_OPTIONS_LINK_ADMIN_STATE_FORCED_UP \
8243 (UINT32_C(0x1) << 2)
8244 /* Admin link state is in auto mode - follows the physical link state. */
8245 #define HWRM_FUNC_QCFG_OUTPUT_OPTIONS_LINK_ADMIN_STATE_AUTO \
8246 (UINT32_C(0x2) << 2)
8247 #define HWRM_FUNC_QCFG_OUTPUT_OPTIONS_LINK_ADMIN_STATE_LAST \
8248 HWRM_FUNC_QCFG_OUTPUT_OPTIONS_LINK_ADMIN_STATE_AUTO
8249 /* Reserved for future. */
8250 #define HWRM_FUNC_QCFG_OUTPUT_OPTIONS_RSVD_MASK \
8252 #define HWRM_FUNC_QCFG_OUTPUT_OPTIONS_RSVD_SFT 4
8254 * The number of VFs that are allocated to the function.
8255 * This is valid only on the PF with SR-IOV enabled.
8256 * 0xFF... (All Fs) if this command is called on a PF with
8257 * SR-IOV disabled or on a VF.
8261 * The number of allocated multicast filters for this
8262 * function on the RX side.
8264 uint32_t alloc_mcast_filters;
8266 * The number of allocated HW ring groups for this
8269 uint32_t alloc_hw_ring_grps;
8271 * The number of strict priority transmit rings out of
8272 * currently allocated TX rings to the function
8275 uint16_t alloc_sp_tx_rings;
8277 * The number of statistics contexts
8278 * currently reserved for the function.
8280 uint16_t alloc_stat_ctx;
8282 * This field specifies how many NQs are reserved for the PF.
8283 * Remaining NQs that belong to the PF are available for VFs.
8284 * Once a PF has created VFs, it cannot change how many NQs are
8285 * reserved for itself (since the NQs must be contiguous in HW).
8287 uint16_t alloc_msix;
8289 * The number of registered VF’s associated with the PF. This field
8290 * should be ignored when the request received on the VF interface.
8291 * This field will be updated on the PF interface to initiate
8292 * the unregister request on PF in the HOT Reset Process.
8294 uint16_t registered_vfs;
8296 * The size of the doorbell BAR in KBytes reserved for L2 including
8297 * any area that is shared between L2 and RoCE. The L2 driver
8298 * should only map the L2 portion of the doorbell BAR. Any rounding
8299 * of the BAR size to the native CPU page size should be performed
8300 * by the driver. If the value is zero, no special partitioning
8301 * of the doorbell BAR between L2 and RoCE is required.
8303 uint16_t l2_doorbell_bar_size_kb;
8306 * For backward compatibility this field must be set to 1.
8307 * Older drivers might look for this field to be 1 before
8308 * processing the message.
8312 * This GRC address location is used by the Host driver interfaces to poll
8313 * the adapter ready state to re-initiate the registration process again
8314 * after receiving the RESET Notify event.
8316 uint32_t reset_addr_poll;
8318 * This field specifies legacy L2 doorbell size in KBytes. Drivers should use
8319 * this value to find out the doorbell page offset from the BAR.
8321 uint16_t legacy_l2_db_size_kb;
8324 * This field specifies the source virtual interface of the function being
8325 * queried. Drivers can use this to program svif field in the L2 context
8328 #define HWRM_FUNC_QCFG_OUTPUT_SVIF_INFO_SVIF_MASK UINT32_C(0x7fff)
8329 #define HWRM_FUNC_QCFG_OUTPUT_SVIF_INFO_SVIF_SFT 0
8330 /* This field specifies whether svif is valid or not */
8331 #define HWRM_FUNC_QCFG_OUTPUT_SVIF_INFO_SVIF_VALID UINT32_C(0x8000)
8332 uint8_t unused_2[7];
8334 * This field is used in Output records to indicate that the output
8335 * is completely written to RAM. This field should be read as '1'
8336 * to indicate that the output has been completely written.
8337 * When writing a command completion or response to an internal processor,
8338 * the order of writes has to be such that this field is written last.
8348 /* hwrm_func_cfg_input (size:704b/88B) */
8349 struct hwrm_func_cfg_input {
8350 /* The HWRM command request type. */
8353 * The completion ring to send the completion event on. This should
8354 * be the NQ ID returned from the `nq_alloc` HWRM command.
8358 * The sequence ID is used by the driver for tracking multiple
8359 * commands. This ID is treated as opaque data by the firmware and
8360 * the value is returned in the `hwrm_resp_hdr` upon completion.
8364 * The target ID of the command:
8365 * * 0x0-0xFFF8 - The function ID
8366 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
8367 * * 0xFFFD - Reserved for user-space HWRM interface
8372 * A physical address pointer pointing to a host buffer that the
8373 * command's response data will be written. This can be either a host
8374 * physical address (HPA) or a guest physical address (GPA) and must
8375 * point to a physically contiguous block of memory.
8379 * Function ID of the function that is being
8381 * If set to 0xFF... (All Fs), then the the configuration is
8382 * for the requesting function.
8386 * This field specifies how many NQs will be reserved for the PF.
8387 * Remaining NQs that belong to the PF become available for VFs.
8388 * Once a PF has created VFs, it cannot change how many NQs are
8389 * reserved for itself (since the NQs must be contiguous in HW).
8394 * When this bit is '1', the function is disabled with
8395 * source MAC address check.
8396 * This is an anti-spoofing check. If this flag is set,
8397 * then the function shall be configured to disallow
8398 * transmission of frames with the source MAC address that
8399 * is configured for this function.
8401 #define HWRM_FUNC_CFG_INPUT_FLAGS_SRC_MAC_ADDR_CHECK_DISABLE \
8404 * When this bit is '1', the function is enabled with
8405 * source MAC address check.
8406 * This is an anti-spoofing check. If this flag is set,
8407 * then the function shall be configured to allow
8408 * transmission of frames with the source MAC address that
8409 * is configured for this function.
8411 #define HWRM_FUNC_CFG_INPUT_FLAGS_SRC_MAC_ADDR_CHECK_ENABLE \
8414 #define HWRM_FUNC_CFG_INPUT_FLAGS_RSVD_MASK \
8416 #define HWRM_FUNC_CFG_INPUT_FLAGS_RSVD_SFT 2
8418 * Standard TX Ring mode is used for the allocation of TX ring
8419 * and underlying scheduling resources that allow bandwidth
8420 * reservation and limit settings on the queried function.
8421 * If set to 1, then standard TX ring mode is requested to be
8422 * enabled on the function being configured.
8424 #define HWRM_FUNC_CFG_INPUT_FLAGS_STD_TX_RING_MODE_ENABLE \
8427 * Standard TX Ring mode is used for the allocation of TX ring
8428 * and underlying scheduling resources that allow bandwidth
8429 * reservation and limit settings on the queried function.
8430 * If set to 1, then the standard TX ring mode is requested to
8431 * be disabled on the function being configured. In this extended
8432 * TX ring resource mode, the minimum and maximum bandwidth settings
8433 * are not supported to allow the allocation of TX rings to
8434 * span multiple scheduler nodes.
8436 #define HWRM_FUNC_CFG_INPUT_FLAGS_STD_TX_RING_MODE_DISABLE \
8439 * If this bit is set, virtual mac address configured
8440 * in this command will be persistent over warm boot.
8442 #define HWRM_FUNC_CFG_INPUT_FLAGS_VIRT_MAC_PERSIST \
8445 * This bit only applies to the VF. If this bit is set, the statistic
8446 * context counters will not be cleared when the statistic context is freed
8447 * or a function reset is called on VF. This bit will be cleared when the PF
8448 * is unloaded or a function reset is called on the PF.
8450 #define HWRM_FUNC_CFG_INPUT_FLAGS_NO_AUTOCLEAR_STATISTIC \
8453 * This bit requests that the firmware test to see if all the assets
8454 * requested in this command (i.e. number of TX rings) are available.
8455 * The firmware will return an error if the requested assets are
8456 * not available. The firwmare will NOT reserve the assets if they
8459 #define HWRM_FUNC_CFG_INPUT_FLAGS_TX_ASSETS_TEST \
8462 * This bit requests that the firmware test to see if all the assets
8463 * requested in this command (i.e. number of RX rings) are available.
8464 * The firmware will return an error if the requested assets are
8465 * not available. The firwmare will NOT reserve the assets if they
8468 #define HWRM_FUNC_CFG_INPUT_FLAGS_RX_ASSETS_TEST \
8471 * This bit requests that the firmware test to see if all the assets
8472 * requested in this command (i.e. number of CMPL rings) are available.
8473 * The firmware will return an error if the requested assets are
8474 * not available. The firwmare will NOT reserve the assets if they
8477 #define HWRM_FUNC_CFG_INPUT_FLAGS_CMPL_ASSETS_TEST \
8480 * This bit requests that the firmware test to see if all the assets
8481 * requested in this command (i.e. number of RSS ctx) are available.
8482 * The firmware will return an error if the requested assets are
8483 * not available. The firwmare will NOT reserve the assets if they
8486 #define HWRM_FUNC_CFG_INPUT_FLAGS_RSSCOS_CTX_ASSETS_TEST \
8489 * This bit requests that the firmware test to see if all the assets
8490 * requested in this command (i.e. number of ring groups) are available.
8491 * The firmware will return an error if the requested assets are
8492 * not available. The firwmare will NOT reserve the assets if they
8495 #define HWRM_FUNC_CFG_INPUT_FLAGS_RING_GRP_ASSETS_TEST \
8498 * This bit requests that the firmware test to see if all the assets
8499 * requested in this command (i.e. number of stat ctx) are available.
8500 * The firmware will return an error if the requested assets are
8501 * not available. The firwmare will NOT reserve the assets if they
8504 #define HWRM_FUNC_CFG_INPUT_FLAGS_STAT_CTX_ASSETS_TEST \
8507 * This bit requests that the firmware test to see if all the assets
8508 * requested in this command (i.e. number of VNICs) are available.
8509 * The firmware will return an error if the requested assets are
8510 * not available. The firwmare will NOT reserve the assets if they
8513 #define HWRM_FUNC_CFG_INPUT_FLAGS_VNIC_ASSETS_TEST \
8516 * This bit requests that the firmware test to see if all the assets
8517 * requested in this command (i.e. number of L2 ctx) are available.
8518 * The firmware will return an error if the requested assets are
8519 * not available. The firwmare will NOT reserve the assets if they
8522 #define HWRM_FUNC_CFG_INPUT_FLAGS_L2_CTX_ASSETS_TEST \
8525 * This configuration change can be initiated by a PF driver. This
8526 * configuration request shall be targeted to a VF. From local host
8527 * resident HWRM clients, only the parent PF driver shall be allowed
8528 * to initiate this change on one of its children VFs. If this bit is
8529 * set to 1, then the VF that is being configured is requested to be
8532 #define HWRM_FUNC_CFG_INPUT_FLAGS_TRUSTED_VF_ENABLE \
8535 * When this bit it set, even if PF reserved pool size is zero,
8536 * FW will allow driver to create TX rings in ring alloc,
8537 * by reserving TX ring, S3 node dynamically.
8539 #define HWRM_FUNC_CFG_INPUT_FLAGS_DYNAMIC_TX_RING_ALLOC \
8542 * This bit requests that the firmware test to see if all the assets
8543 * requested in this command (i.e. number of NQ rings) are available.
8544 * The firmware will return an error if the requested assets are
8545 * not available. The firwmare will NOT reserve the assets if they
8548 #define HWRM_FUNC_CFG_INPUT_FLAGS_NQ_ASSETS_TEST \
8551 * This configuration change can be initiated by a PF driver. This
8552 * configuration request shall be targeted to a VF. From local host
8553 * resident HWRM clients, only the parent PF driver shall be allowed
8554 * to initiate this change on one of its children VFs. If this bit is
8555 * set to 1, then the VF that is being configured is requested to be
8558 #define HWRM_FUNC_CFG_INPUT_FLAGS_TRUSTED_VF_DISABLE \
8561 * This bit is used by preboot drivers on a PF that require access
8562 * to the legacy L2 ring model and legacy 32b doorbells. This
8563 * feature is not allowed on VFs and is only relevant for devices
8564 * that require a context backing store.
8566 #define HWRM_FUNC_CFG_INPUT_FLAGS_PREBOOT_LEGACY_L2_RINGS \
8570 * This bit must be '1' for the mtu field to be
8573 #define HWRM_FUNC_CFG_INPUT_ENABLES_MTU \
8576 * This bit must be '1' for the mru field to be
8579 #define HWRM_FUNC_CFG_INPUT_ENABLES_MRU \
8582 * This bit must be '1' for the num_rsscos_ctxs field to be
8585 #define HWRM_FUNC_CFG_INPUT_ENABLES_NUM_RSSCOS_CTXS \
8588 * This bit must be '1' for the num_cmpl_rings field to be
8591 #define HWRM_FUNC_CFG_INPUT_ENABLES_NUM_CMPL_RINGS \
8594 * This bit must be '1' for the num_tx_rings field to be
8597 #define HWRM_FUNC_CFG_INPUT_ENABLES_NUM_TX_RINGS \
8600 * This bit must be '1' for the num_rx_rings field to be
8603 #define HWRM_FUNC_CFG_INPUT_ENABLES_NUM_RX_RINGS \
8606 * This bit must be '1' for the num_l2_ctxs field to be
8609 #define HWRM_FUNC_CFG_INPUT_ENABLES_NUM_L2_CTXS \
8612 * This bit must be '1' for the num_vnics field to be
8615 #define HWRM_FUNC_CFG_INPUT_ENABLES_NUM_VNICS \
8618 * This bit must be '1' for the num_stat_ctxs field to be
8621 #define HWRM_FUNC_CFG_INPUT_ENABLES_NUM_STAT_CTXS \
8624 * This bit must be '1' for the dflt_mac_addr field to be
8627 #define HWRM_FUNC_CFG_INPUT_ENABLES_DFLT_MAC_ADDR \
8630 * This bit must be '1' for the dflt_vlan field to be
8633 #define HWRM_FUNC_CFG_INPUT_ENABLES_DFLT_VLAN \
8636 * This bit must be '1' for the dflt_ip_addr field to be
8639 #define HWRM_FUNC_CFG_INPUT_ENABLES_DFLT_IP_ADDR \
8642 * This bit must be '1' for the min_bw field to be
8645 #define HWRM_FUNC_CFG_INPUT_ENABLES_MIN_BW \
8648 * This bit must be '1' for the max_bw field to be
8651 #define HWRM_FUNC_CFG_INPUT_ENABLES_MAX_BW \
8654 * This bit must be '1' for the async_event_cr field to be
8657 #define HWRM_FUNC_CFG_INPUT_ENABLES_ASYNC_EVENT_CR \
8660 * This bit must be '1' for the vlan_antispoof_mode field to be
8663 #define HWRM_FUNC_CFG_INPUT_ENABLES_VLAN_ANTISPOOF_MODE \
8666 * This bit must be '1' for the allowed_vlan_pris field to be
8669 #define HWRM_FUNC_CFG_INPUT_ENABLES_ALLOWED_VLAN_PRIS \
8672 * This bit must be '1' for the evb_mode field to be
8675 #define HWRM_FUNC_CFG_INPUT_ENABLES_EVB_MODE \
8678 * This bit must be '1' for the num_mcast_filters field to be
8681 #define HWRM_FUNC_CFG_INPUT_ENABLES_NUM_MCAST_FILTERS \
8684 * This bit must be '1' for the num_hw_ring_grps field to be
8687 #define HWRM_FUNC_CFG_INPUT_ENABLES_NUM_HW_RING_GRPS \
8690 * This bit must be '1' for the cache_linesize field to be
8693 #define HWRM_FUNC_CFG_INPUT_ENABLES_CACHE_LINESIZE \
8696 * This bit must be '1' for the num_msix field to be
8699 #define HWRM_FUNC_CFG_INPUT_ENABLES_NUM_MSIX \
8702 * This bit must be '1' for the link admin state field to be
8705 #define HWRM_FUNC_CFG_INPUT_ENABLES_ADMIN_LINK_STATE \
8708 * The maximum transmission unit of the function.
8709 * The HWRM should make sure that the mtu of
8710 * the function does not exceed the mtu of the physical
8711 * port that this function is associated with.
8713 * In addition to configuring mtu per function, it is
8714 * possible to configure mtu per transmit ring.
8715 * By default, the mtu of each transmit ring associated
8716 * with a function is equal to the mtu of the function.
8717 * The HWRM should make sure that the mtu of each transmit
8718 * ring that is assigned to a function has a valid mtu.
8722 * The maximum receive unit of the function.
8723 * The HWRM should make sure that the mru of
8724 * the function does not exceed the mru of the physical
8725 * port that this function is associated with.
8727 * In addition to configuring mru per function, it is
8728 * possible to configure mru per vnic.
8729 * By default, the mru of each vnic associated
8730 * with a function is equal to the mru of the function.
8731 * The HWRM should make sure that the mru of each vnic
8732 * that is assigned to a function has a valid mru.
8736 * The number of RSS/COS contexts requested for the
8739 uint16_t num_rsscos_ctxs;
8741 * The number of completion rings requested for the
8742 * function. This does not include the rings allocated
8743 * to any children functions if any.
8745 uint16_t num_cmpl_rings;
8747 * The number of transmit rings requested for the function.
8748 * This does not include the rings allocated to any
8749 * children functions if any.
8751 uint16_t num_tx_rings;
8753 * The number of receive rings requested for the function.
8754 * This does not include the rings allocated
8755 * to any children functions if any.
8757 uint16_t num_rx_rings;
8758 /* The requested number of L2 contexts for the function. */
8759 uint16_t num_l2_ctxs;
8760 /* The requested number of vnics for the function. */
8762 /* The requested number of statistic contexts for the function. */
8763 uint16_t num_stat_ctxs;
8765 * The number of HW ring groups that should
8766 * be reserved for this function.
8768 uint16_t num_hw_ring_grps;
8769 /* The default MAC address for the function being configured. */
8770 uint8_t dflt_mac_addr[6];
8772 * The default VLAN for the function being configured.
8773 * This field's format is same as 802.1Q Tag's
8774 * Tag Control Information (TCI) format that includes both
8775 * Priority Code Point (PCP) and VLAN Identifier (VID).
8779 * The default IP address for the function being configured.
8780 * This address is only used in enabling source property check.
8782 uint32_t dflt_ip_addr[4];
8784 * Minimum BW allocated for this function.
8785 * The HWRM will translate this value into byte counter and
8786 * time interval used for the scheduler inside the device.
8789 /* The bandwidth value. */
8790 #define HWRM_FUNC_CFG_INPUT_MIN_BW_BW_VALUE_MASK \
8792 #define HWRM_FUNC_CFG_INPUT_MIN_BW_BW_VALUE_SFT 0
8793 /* The granularity of the value (bits or bytes). */
8794 #define HWRM_FUNC_CFG_INPUT_MIN_BW_SCALE \
8795 UINT32_C(0x10000000)
8796 /* Value is in bits. */
8797 #define HWRM_FUNC_CFG_INPUT_MIN_BW_SCALE_BITS \
8798 (UINT32_C(0x0) << 28)
8799 /* Value is in bytes. */
8800 #define HWRM_FUNC_CFG_INPUT_MIN_BW_SCALE_BYTES \
8801 (UINT32_C(0x1) << 28)
8802 #define HWRM_FUNC_CFG_INPUT_MIN_BW_SCALE_LAST \
8803 HWRM_FUNC_CFG_INPUT_MIN_BW_SCALE_BYTES
8804 /* bw_value_unit is 3 b */
8805 #define HWRM_FUNC_CFG_INPUT_MIN_BW_BW_VALUE_UNIT_MASK \
8806 UINT32_C(0xe0000000)
8807 #define HWRM_FUNC_CFG_INPUT_MIN_BW_BW_VALUE_UNIT_SFT 29
8808 /* Value is in Mb or MB (base 10). */
8809 #define HWRM_FUNC_CFG_INPUT_MIN_BW_BW_VALUE_UNIT_MEGA \
8810 (UINT32_C(0x0) << 29)
8811 /* Value is in Kb or KB (base 10). */
8812 #define HWRM_FUNC_CFG_INPUT_MIN_BW_BW_VALUE_UNIT_KILO \
8813 (UINT32_C(0x2) << 29)
8814 /* Value is in bits or bytes. */
8815 #define HWRM_FUNC_CFG_INPUT_MIN_BW_BW_VALUE_UNIT_BASE \
8816 (UINT32_C(0x4) << 29)
8817 /* Value is in Gb or GB (base 10). */
8818 #define HWRM_FUNC_CFG_INPUT_MIN_BW_BW_VALUE_UNIT_GIGA \
8819 (UINT32_C(0x6) << 29)
8820 /* Value is in 1/100th of a percentage of total bandwidth. */
8821 #define HWRM_FUNC_CFG_INPUT_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 \
8822 (UINT32_C(0x1) << 29)
8824 #define HWRM_FUNC_CFG_INPUT_MIN_BW_BW_VALUE_UNIT_INVALID \
8825 (UINT32_C(0x7) << 29)
8826 #define HWRM_FUNC_CFG_INPUT_MIN_BW_BW_VALUE_UNIT_LAST \
8827 HWRM_FUNC_CFG_INPUT_MIN_BW_BW_VALUE_UNIT_INVALID
8829 * Maximum BW allocated for this function.
8830 * The HWRM will translate this value into byte counter and
8831 * time interval used for the scheduler inside the device.
8834 /* The bandwidth value. */
8835 #define HWRM_FUNC_CFG_INPUT_MAX_BW_BW_VALUE_MASK \
8837 #define HWRM_FUNC_CFG_INPUT_MAX_BW_BW_VALUE_SFT 0
8838 /* The granularity of the value (bits or bytes). */
8839 #define HWRM_FUNC_CFG_INPUT_MAX_BW_SCALE \
8840 UINT32_C(0x10000000)
8841 /* Value is in bits. */
8842 #define HWRM_FUNC_CFG_INPUT_MAX_BW_SCALE_BITS \
8843 (UINT32_C(0x0) << 28)
8844 /* Value is in bytes. */
8845 #define HWRM_FUNC_CFG_INPUT_MAX_BW_SCALE_BYTES \
8846 (UINT32_C(0x1) << 28)
8847 #define HWRM_FUNC_CFG_INPUT_MAX_BW_SCALE_LAST \
8848 HWRM_FUNC_CFG_INPUT_MAX_BW_SCALE_BYTES
8849 /* bw_value_unit is 3 b */
8850 #define HWRM_FUNC_CFG_INPUT_MAX_BW_BW_VALUE_UNIT_MASK \
8851 UINT32_C(0xe0000000)
8852 #define HWRM_FUNC_CFG_INPUT_MAX_BW_BW_VALUE_UNIT_SFT 29
8853 /* Value is in Mb or MB (base 10). */
8854 #define HWRM_FUNC_CFG_INPUT_MAX_BW_BW_VALUE_UNIT_MEGA \
8855 (UINT32_C(0x0) << 29)
8856 /* Value is in Kb or KB (base 10). */
8857 #define HWRM_FUNC_CFG_INPUT_MAX_BW_BW_VALUE_UNIT_KILO \
8858 (UINT32_C(0x2) << 29)
8859 /* Value is in bits or bytes. */
8860 #define HWRM_FUNC_CFG_INPUT_MAX_BW_BW_VALUE_UNIT_BASE \
8861 (UINT32_C(0x4) << 29)
8862 /* Value is in Gb or GB (base 10). */
8863 #define HWRM_FUNC_CFG_INPUT_MAX_BW_BW_VALUE_UNIT_GIGA \
8864 (UINT32_C(0x6) << 29)
8865 /* Value is in 1/100th of a percentage of total bandwidth. */
8866 #define HWRM_FUNC_CFG_INPUT_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 \
8867 (UINT32_C(0x1) << 29)
8869 #define HWRM_FUNC_CFG_INPUT_MAX_BW_BW_VALUE_UNIT_INVALID \
8870 (UINT32_C(0x7) << 29)
8871 #define HWRM_FUNC_CFG_INPUT_MAX_BW_BW_VALUE_UNIT_LAST \
8872 HWRM_FUNC_CFG_INPUT_MAX_BW_BW_VALUE_UNIT_INVALID
8874 * ID of the target completion ring for receiving asynchronous
8875 * event completions. If this field is not valid, then the
8876 * HWRM shall use the default completion ring of the function
8877 * that is being configured as the target completion ring for
8878 * providing any asynchronous event completions for that
8880 * If this field is valid, then the HWRM shall use the
8881 * completion ring identified by this ID as the target
8882 * completion ring for providing any asynchronous event
8883 * completions for the function that is being configured.
8885 uint16_t async_event_cr;
8886 /* VLAN Anti-spoofing mode. */
8887 uint8_t vlan_antispoof_mode;
8888 /* No VLAN anti-spoofing checks are enabled */
8889 #define HWRM_FUNC_CFG_INPUT_VLAN_ANTISPOOF_MODE_NOCHECK \
8891 /* Validate VLAN against the configured VLAN(s) */
8892 #define HWRM_FUNC_CFG_INPUT_VLAN_ANTISPOOF_MODE_VALIDATE_VLAN \
8894 /* Insert VLAN if it does not exist, otherwise discard */
8895 #define HWRM_FUNC_CFG_INPUT_VLAN_ANTISPOOF_MODE_INSERT_IF_VLANDNE \
8897 /* Insert VLAN if it does not exist, override VLAN if it exists */
8898 #define HWRM_FUNC_CFG_INPUT_VLAN_ANTISPOOF_MODE_INSERT_OR_OVERRIDE_VLAN \
8900 #define HWRM_FUNC_CFG_INPUT_VLAN_ANTISPOOF_MODE_LAST \
8901 HWRM_FUNC_CFG_INPUT_VLAN_ANTISPOOF_MODE_INSERT_OR_OVERRIDE_VLAN
8903 * This bit field defines VLAN PRIs that are allowed on
8905 * If nth bit is set, then VLAN PRI n is allowed on this
8908 uint8_t allowed_vlan_pris;
8910 * The HWRM shall allow a PF driver to change EVB mode for the
8911 * partition it belongs to.
8912 * The HWRM shall not allow a VF driver to change the EVB mode.
8913 * The HWRM shall take into account the switching of EVB mode
8914 * from one to another and reconfigure hardware resources as
8916 * The switching from VEB to VEPA mode requires
8917 * the disabling of the loopback traffic. Additionally,
8918 * source knock outs are handled differently in VEB and VEPA
8922 /* No Edge Virtual Bridging (EVB) */
8923 #define HWRM_FUNC_CFG_INPUT_EVB_MODE_NO_EVB UINT32_C(0x0)
8924 /* Virtual Ethernet Bridge (VEB) */
8925 #define HWRM_FUNC_CFG_INPUT_EVB_MODE_VEB UINT32_C(0x1)
8926 /* Virtual Ethernet Port Aggregator (VEPA) */
8927 #define HWRM_FUNC_CFG_INPUT_EVB_MODE_VEPA UINT32_C(0x2)
8928 #define HWRM_FUNC_CFG_INPUT_EVB_MODE_LAST \
8929 HWRM_FUNC_CFG_INPUT_EVB_MODE_VEPA
8932 * This value indicates the PCIE device cache line size.
8933 * The cache line size allows the DMA writes to terminate and
8934 * start at the cache boundary.
8936 #define HWRM_FUNC_CFG_INPUT_OPTIONS_CACHE_LINESIZE_MASK \
8938 #define HWRM_FUNC_CFG_INPUT_OPTIONS_CACHE_LINESIZE_SFT 0
8939 /* Cache Line Size 64 bytes */
8940 #define HWRM_FUNC_CFG_INPUT_OPTIONS_CACHE_LINESIZE_SIZE_64 \
8942 /* Cache Line Size 128 bytes */
8943 #define HWRM_FUNC_CFG_INPUT_OPTIONS_CACHE_LINESIZE_SIZE_128 \
8945 #define HWRM_FUNC_CFG_INPUT_OPTIONS_CACHE_LINESIZE_LAST \
8946 HWRM_FUNC_CFG_INPUT_OPTIONS_CACHE_LINESIZE_SIZE_128
8947 /* This value is the virtual link admin state setting. */
8948 #define HWRM_FUNC_CFG_INPUT_OPTIONS_LINK_ADMIN_STATE_MASK \
8950 #define HWRM_FUNC_CFG_INPUT_OPTIONS_LINK_ADMIN_STATE_SFT 2
8951 /* Admin state is forced down. */
8952 #define HWRM_FUNC_CFG_INPUT_OPTIONS_LINK_ADMIN_STATE_FORCED_DOWN \
8953 (UINT32_C(0x0) << 2)
8954 /* Admin state is forced up. */
8955 #define HWRM_FUNC_CFG_INPUT_OPTIONS_LINK_ADMIN_STATE_FORCED_UP \
8956 (UINT32_C(0x1) << 2)
8957 /* Admin state is in auto mode - is to follow the physical link state. */
8958 #define HWRM_FUNC_CFG_INPUT_OPTIONS_LINK_ADMIN_STATE_AUTO \
8959 (UINT32_C(0x2) << 2)
8960 #define HWRM_FUNC_CFG_INPUT_OPTIONS_LINK_ADMIN_STATE_LAST \
8961 HWRM_FUNC_CFG_INPUT_OPTIONS_LINK_ADMIN_STATE_AUTO
8962 /* Reserved for future. */
8963 #define HWRM_FUNC_CFG_INPUT_OPTIONS_RSVD_MASK \
8965 #define HWRM_FUNC_CFG_INPUT_OPTIONS_RSVD_SFT 4
8967 * The number of multicast filters that should
8968 * be reserved for this function on the RX side.
8970 uint16_t num_mcast_filters;
8973 /* hwrm_func_cfg_output (size:128b/16B) */
8974 struct hwrm_func_cfg_output {
8975 /* The specific error status for the command. */
8976 uint16_t error_code;
8977 /* The HWRM command request type. */
8979 /* The sequence ID from the original command. */
8981 /* The length of the response data in number of bytes. */
8983 uint8_t unused_0[7];
8985 * This field is used in Output records to indicate that the output
8986 * is completely written to RAM. This field should be read as '1'
8987 * to indicate that the output has been completely written.
8988 * When writing a command completion or response to an internal processor,
8989 * the order of writes has to be such that this field is written last.
8994 /********************
8995 * hwrm_func_qstats *
8996 ********************/
8999 /* hwrm_func_qstats_input (size:192b/24B) */
9000 struct hwrm_func_qstats_input {
9001 /* The HWRM command request type. */
9004 * The completion ring to send the completion event on. This should
9005 * be the NQ ID returned from the `nq_alloc` HWRM command.
9009 * The sequence ID is used by the driver for tracking multiple
9010 * commands. This ID is treated as opaque data by the firmware and
9011 * the value is returned in the `hwrm_resp_hdr` upon completion.
9015 * The target ID of the command:
9016 * * 0x0-0xFFF8 - The function ID
9017 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
9018 * * 0xFFFD - Reserved for user-space HWRM interface
9023 * A physical address pointer pointing to a host buffer that the
9024 * command's response data will be written. This can be either a host
9025 * physical address (HPA) or a guest physical address (GPA) and must
9026 * point to a physically contiguous block of memory.
9030 * Function ID of the function that is being queried.
9031 * 0xFF... (All Fs) if the query is for the requesting
9033 * A privileged PF can query for other function's statistics.
9036 /* This flags indicates the type of statistics request. */
9038 /* This value is not used to avoid backward compatibility issues. */
9039 #define HWRM_FUNC_QSTATS_INPUT_FLAGS_UNUSED UINT32_C(0x0)
9041 * flags should be set to 1 when request is for only RoCE statistics.
9042 * This will be honored only if the caller_fid is a privileged PF.
9043 * In all other cases FID and caller_fid should be the same.
9045 #define HWRM_FUNC_QSTATS_INPUT_FLAGS_ROCE_ONLY UINT32_C(0x1)
9046 #define HWRM_FUNC_QSTATS_INPUT_FLAGS_LAST \
9047 HWRM_FUNC_QSTATS_INPUT_FLAGS_ROCE_ONLY
9048 uint8_t unused_0[5];
9051 /* hwrm_func_qstats_output (size:1408b/176B) */
9052 struct hwrm_func_qstats_output {
9053 /* The specific error status for the command. */
9054 uint16_t error_code;
9055 /* The HWRM command request type. */
9057 /* The sequence ID from the original command. */
9059 /* The length of the response data in number of bytes. */
9061 /* Number of transmitted unicast packets on the function. */
9062 uint64_t tx_ucast_pkts;
9063 /* Number of transmitted multicast packets on the function. */
9064 uint64_t tx_mcast_pkts;
9065 /* Number of transmitted broadcast packets on the function. */
9066 uint64_t tx_bcast_pkts;
9068 * Number of transmitted packets that were discarded due to
9069 * internal NIC resource problems. For transmit, this
9070 * can only happen if TMP is configured to allow dropping
9071 * in HOL blocking conditions, which is not a normal
9074 uint64_t tx_discard_pkts;
9076 * Number of dropped packets on transmit path on the function.
9077 * These are packets that have been marked for drop by
9078 * the TE CFA block or are packets that exceeded the
9079 * transmit MTU limit for the function.
9081 uint64_t tx_drop_pkts;
9082 /* Number of transmitted bytes for unicast traffic on the function. */
9083 uint64_t tx_ucast_bytes;
9084 /* Number of transmitted bytes for multicast traffic on the function. */
9085 uint64_t tx_mcast_bytes;
9086 /* Number of transmitted bytes for broadcast traffic on the function. */
9087 uint64_t tx_bcast_bytes;
9088 /* Number of received unicast packets on the function. */
9089 uint64_t rx_ucast_pkts;
9090 /* Number of received multicast packets on the function. */
9091 uint64_t rx_mcast_pkts;
9092 /* Number of received broadcast packets on the function. */
9093 uint64_t rx_bcast_pkts;
9095 * Number of received packets that were discarded on the function
9096 * due to resource limitations. This can happen for 3 reasons.
9097 * # The BD used for the packet has a bad format.
9098 * # There were no BDs available in the ring for the packet.
9099 * # There were no BDs available on-chip for the packet.
9101 uint64_t rx_discard_pkts;
9103 * Number of dropped packets on received path on the function.
9104 * These are packets that have been marked for drop by the
9107 uint64_t rx_drop_pkts;
9108 /* Number of received bytes for unicast traffic on the function. */
9109 uint64_t rx_ucast_bytes;
9110 /* Number of received bytes for multicast traffic on the function. */
9111 uint64_t rx_mcast_bytes;
9112 /* Number of received bytes for broadcast traffic on the function. */
9113 uint64_t rx_bcast_bytes;
9114 /* Number of aggregated unicast packets on the function. */
9115 uint64_t rx_agg_pkts;
9116 /* Number of aggregated unicast bytes on the function. */
9117 uint64_t rx_agg_bytes;
9118 /* Number of aggregation events on the function. */
9119 uint64_t rx_agg_events;
9120 /* Number of aborted aggregations on the function. */
9121 uint64_t rx_agg_aborts;
9122 uint8_t unused_0[7];
9124 * This field is used in Output records to indicate that the output
9125 * is completely written to RAM. This field should be read as '1'
9126 * to indicate that the output has been completely written.
9127 * When writing a command completion or response to an internal processor,
9128 * the order of writes has to be such that this field is written last.
9133 /***********************
9134 * hwrm_func_clr_stats *
9135 ***********************/
9138 /* hwrm_func_clr_stats_input (size:192b/24B) */
9139 struct hwrm_func_clr_stats_input {
9140 /* The HWRM command request type. */
9143 * The completion ring to send the completion event on. This should
9144 * be the NQ ID returned from the `nq_alloc` HWRM command.
9148 * The sequence ID is used by the driver for tracking multiple
9149 * commands. This ID is treated as opaque data by the firmware and
9150 * the value is returned in the `hwrm_resp_hdr` upon completion.
9154 * The target ID of the command:
9155 * * 0x0-0xFFF8 - The function ID
9156 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
9157 * * 0xFFFD - Reserved for user-space HWRM interface
9162 * A physical address pointer pointing to a host buffer that the
9163 * command's response data will be written. This can be either a host
9164 * physical address (HPA) or a guest physical address (GPA) and must
9165 * point to a physically contiguous block of memory.
9169 * Function ID of the function.
9170 * 0xFF... (All Fs) if the query is for the requesting
9174 uint8_t unused_0[6];
9177 /* hwrm_func_clr_stats_output (size:128b/16B) */
9178 struct hwrm_func_clr_stats_output {
9179 /* The specific error status for the command. */
9180 uint16_t error_code;
9181 /* The HWRM command request type. */
9183 /* The sequence ID from the original command. */
9185 /* The length of the response data in number of bytes. */
9187 uint8_t unused_0[7];
9189 * This field is used in Output records to indicate that the output
9190 * is completely written to RAM. This field should be read as '1'
9191 * to indicate that the output has been completely written.
9192 * When writing a command completion or response to an internal processor,
9193 * the order of writes has to be such that this field is written last.
9198 /**************************
9199 * hwrm_func_vf_resc_free *
9200 **************************/
9203 /* hwrm_func_vf_resc_free_input (size:192b/24B) */
9204 struct hwrm_func_vf_resc_free_input {
9205 /* The HWRM command request type. */
9208 * The completion ring to send the completion event on. This should
9209 * be the NQ ID returned from the `nq_alloc` HWRM command.
9213 * The sequence ID is used by the driver for tracking multiple
9214 * commands. This ID is treated as opaque data by the firmware and
9215 * the value is returned in the `hwrm_resp_hdr` upon completion.
9219 * The target ID of the command:
9220 * * 0x0-0xFFF8 - The function ID
9221 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
9222 * * 0xFFFD - Reserved for user-space HWRM interface
9227 * A physical address pointer pointing to a host buffer that the
9228 * command's response data will be written. This can be either a host
9229 * physical address (HPA) or a guest physical address (GPA) and must
9230 * point to a physically contiguous block of memory.
9234 * This value is used to identify a Virtual Function (VF).
9235 * The scope of VF ID is local within a PF.
9238 uint8_t unused_0[6];
9241 /* hwrm_func_vf_resc_free_output (size:128b/16B) */
9242 struct hwrm_func_vf_resc_free_output {
9243 /* The specific error status for the command. */
9244 uint16_t error_code;
9245 /* The HWRM command request type. */
9247 /* The sequence ID from the original command. */
9249 /* The length of the response data in number of bytes. */
9251 uint8_t unused_0[7];
9253 * This field is used in Output records to indicate that the output
9254 * is completely written to RAM. This field should be read as '1'
9255 * to indicate that the output has been completely written.
9256 * When writing a command completion or response to an internal processor,
9257 * the order of writes has to be such that this field is written last.
9262 /**********************
9263 * hwrm_func_drv_rgtr *
9264 **********************/
9267 /* hwrm_func_drv_rgtr_input (size:896b/112B) */
9268 struct hwrm_func_drv_rgtr_input {
9269 /* The HWRM command request type. */
9272 * The completion ring to send the completion event on. This should
9273 * be the NQ ID returned from the `nq_alloc` HWRM command.
9277 * The sequence ID is used by the driver for tracking multiple
9278 * commands. This ID is treated as opaque data by the firmware and
9279 * the value is returned in the `hwrm_resp_hdr` upon completion.
9283 * The target ID of the command:
9284 * * 0x0-0xFFF8 - The function ID
9285 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
9286 * * 0xFFFD - Reserved for user-space HWRM interface
9291 * A physical address pointer pointing to a host buffer that the
9292 * command's response data will be written. This can be either a host
9293 * physical address (HPA) or a guest physical address (GPA) and must
9294 * point to a physically contiguous block of memory.
9299 * When this bit is '1', the function driver is requesting
9300 * all requests from its children VF drivers to be
9301 * forwarded to itself.
9302 * This flag can only be set by the PF driver.
9303 * If a VF driver sets this flag, it should be ignored
9306 #define HWRM_FUNC_DRV_RGTR_INPUT_FLAGS_FWD_ALL_MODE \
9309 * When this bit is '1', the function is requesting none of
9310 * the requests from its children VF drivers to be
9311 * forwarded to itself.
9312 * This flag can only be set by the PF driver.
9313 * If a VF driver sets this flag, it should be ignored
9316 #define HWRM_FUNC_DRV_RGTR_INPUT_FLAGS_FWD_NONE_MODE \
9319 * When this bit is '1', then ver_maj_8b, ver_min_8b, ver_upd_8b
9320 * fields shall be ignored and ver_maj, ver_min, ver_upd
9321 * and ver_patch shall be used for the driver version information.
9322 * When this bit is '0', then ver_maj_8b, ver_min_8b, ver_upd_8b
9323 * fields shall be used for the driver version information and
9324 * ver_maj, ver_min, ver_upd and ver_patch shall be ignored.
9326 #define HWRM_FUNC_DRV_RGTR_INPUT_FLAGS_16BIT_VER_MODE \
9329 * When this bit is '1', the function is indicating support of
9330 * 64bit flow handle. The firmware that only supports 64bit flow
9331 * handle should check this bit before allowing processing of
9332 * HWRM_CFA_FLOW_XXX commands from the requesting function as firmware
9333 * with 64bit flow handle support can only be compatible with drivers
9334 * that support 64bit flow handle. The legacy drivers that don't support
9335 * 64bit flow handle won't be able to use HWRM_CFA_FLOW_XXX commands when
9336 * running with new firmware that only supports 64bit flow handle. The new
9337 * firmware support 64bit flow handle returns HWRM_ERR_CODE_CMD_NOT_SUPPORTED
9338 * status to the legacy driver when encounters these commands.
9340 #define HWRM_FUNC_DRV_RGTR_INPUT_FLAGS_FLOW_HANDLE_64BIT_MODE \
9343 * When this bit is '1', the function is indicating support of
9344 * Hot Reset. The driver interface will destroy the resources,
9345 * unregister the function and register again up on receiving
9346 * the RESET_NOTIFY Async notification from the core firmware.
9347 * The core firmware will this use flag and trigger the Hot Reset
9348 * process only if all the registered driver instances are capable
9351 #define HWRM_FUNC_DRV_RGTR_INPUT_FLAGS_HOT_RESET_SUPPORT \
9354 * When this bit is 1, the function is indicating the support of the
9355 * error recovery capability. Error recovery support will be used by
9356 * firmware only if all the driver instances support error recovery
9357 * process. By setting this bit, driver is indicating support for
9358 * corresponding async event completion message. These will be
9359 * delivered to the driver even if they did not register for it.
9360 * If supported, after receiving reset notify async event with fatal
9361 * flag set in event data1, then all the drivers have to tear down
9362 * their resources without sending any HWRM commands to FW.
9364 #define HWRM_FUNC_DRV_RGTR_INPUT_FLAGS_ERROR_RECOVERY_SUPPORT \
9367 * When this bit is 1, the function is indicating the support of the
9368 * Master capability. The Firmware will use this capability to select the
9369 * Master function. The master function will be used to initiate
9370 * designated functionality like error recovery etc… If none of the
9371 * registered PF’s or trusted VF’s indicate this support, then
9372 * firmware will select the 1st registered PF as Master capable instance.
9374 #define HWRM_FUNC_DRV_RGTR_INPUT_FLAGS_MASTER_SUPPORT \
9378 * This bit must be '1' for the os_type field to be
9381 #define HWRM_FUNC_DRV_RGTR_INPUT_ENABLES_OS_TYPE \
9384 * This bit must be '1' for the ver field to be
9387 #define HWRM_FUNC_DRV_RGTR_INPUT_ENABLES_VER \
9390 * This bit must be '1' for the timestamp field to be
9393 #define HWRM_FUNC_DRV_RGTR_INPUT_ENABLES_TIMESTAMP \
9396 * This bit must be '1' for the vf_req_fwd field to be
9399 #define HWRM_FUNC_DRV_RGTR_INPUT_ENABLES_VF_REQ_FWD \
9402 * This bit must be '1' for the async_event_fwd field to be
9405 #define HWRM_FUNC_DRV_RGTR_INPUT_ENABLES_ASYNC_EVENT_FWD \
9407 /* This value indicates the type of OS. The values are based on CIM_OperatingSystem.mof file as published by the DMTF. */
9410 #define HWRM_FUNC_DRV_RGTR_INPUT_OS_TYPE_UNKNOWN UINT32_C(0x0)
9411 /* Other OS not listed below. */
9412 #define HWRM_FUNC_DRV_RGTR_INPUT_OS_TYPE_OTHER UINT32_C(0x1)
9414 #define HWRM_FUNC_DRV_RGTR_INPUT_OS_TYPE_MSDOS UINT32_C(0xe)
9416 #define HWRM_FUNC_DRV_RGTR_INPUT_OS_TYPE_WINDOWS UINT32_C(0x12)
9418 #define HWRM_FUNC_DRV_RGTR_INPUT_OS_TYPE_SOLARIS UINT32_C(0x1d)
9420 #define HWRM_FUNC_DRV_RGTR_INPUT_OS_TYPE_LINUX UINT32_C(0x24)
9422 #define HWRM_FUNC_DRV_RGTR_INPUT_OS_TYPE_FREEBSD UINT32_C(0x2a)
9423 /* VMware ESXi OS. */
9424 #define HWRM_FUNC_DRV_RGTR_INPUT_OS_TYPE_ESXI UINT32_C(0x68)
9425 /* Microsoft Windows 8 64-bit OS. */
9426 #define HWRM_FUNC_DRV_RGTR_INPUT_OS_TYPE_WIN864 UINT32_C(0x73)
9427 /* Microsoft Windows Server 2012 R2 OS. */
9428 #define HWRM_FUNC_DRV_RGTR_INPUT_OS_TYPE_WIN2012R2 UINT32_C(0x74)
9430 #define HWRM_FUNC_DRV_RGTR_INPUT_OS_TYPE_UEFI UINT32_C(0x8000)
9431 #define HWRM_FUNC_DRV_RGTR_INPUT_OS_TYPE_LAST \
9432 HWRM_FUNC_DRV_RGTR_INPUT_OS_TYPE_UEFI
9433 /* This is the 8bit major version of the driver. */
9435 /* This is the 8bit minor version of the driver. */
9437 /* This is the 8bit update version of the driver. */
9439 uint8_t unused_0[3];
9441 * This is a 32-bit timestamp provided by the driver for
9443 * The timestamp is in multiples of 1ms.
9446 uint8_t unused_1[4];
9448 * This is a 256-bit bit mask provided by the PF driver for
9449 * letting the HWRM know what commands issued by the VF driver
9450 * to the HWRM should be forwarded to the PF driver.
9451 * Nth bit refers to the Nth req_type.
9453 * Setting Nth bit to 1 indicates that requests from the
9454 * VF driver with req_type equal to N shall be forwarded to
9455 * the parent PF driver.
9457 * This field is not valid for the VF driver.
9459 uint32_t vf_req_fwd[8];
9461 * This is a 256-bit bit mask provided by the function driver
9462 * (PF or VF driver) to indicate the list of asynchronous event
9463 * completions to be forwarded.
9465 * Nth bit refers to the Nth event_id.
9467 * Setting Nth bit to 1 by the function driver shall result in
9468 * the HWRM forwarding asynchronous event completion with
9469 * event_id equal to N.
9471 * If all bits are set to 0 (value of 0), then the HWRM shall
9472 * not forward any asynchronous event completion to this
9475 uint32_t async_event_fwd[8];
9476 /* This is the 16bit major version of the driver. */
9478 /* This is the 16bit minor version of the driver. */
9480 /* This is the 16bit update version of the driver. */
9482 /* This is the 16bit patch version of the driver. */
9486 /* hwrm_func_drv_rgtr_output (size:128b/16B) */
9487 struct hwrm_func_drv_rgtr_output {
9488 /* The specific error status for the command. */
9489 uint16_t error_code;
9490 /* The HWRM command request type. */
9492 /* The sequence ID from the original command. */
9494 /* The length of the response data in number of bytes. */
9498 * When this bit is '1', it indicates that the
9499 * HWRM_FUNC_DRV_IF_CHANGE call is supported.
9501 #define HWRM_FUNC_DRV_RGTR_OUTPUT_FLAGS_IF_CHANGE_SUPPORTED \
9503 uint8_t unused_0[3];
9505 * This field is used in Output records to indicate that the output
9506 * is completely written to RAM. This field should be read as '1'
9507 * to indicate that the output has been completely written.
9508 * When writing a command completion or response to an internal processor,
9509 * the order of writes has to be such that this field is written last.
9514 /************************
9515 * hwrm_func_drv_unrgtr *
9516 ************************/
9519 /* hwrm_func_drv_unrgtr_input (size:192b/24B) */
9520 struct hwrm_func_drv_unrgtr_input {
9521 /* The HWRM command request type. */
9524 * The completion ring to send the completion event on. This should
9525 * be the NQ ID returned from the `nq_alloc` HWRM command.
9529 * The sequence ID is used by the driver for tracking multiple
9530 * commands. This ID is treated as opaque data by the firmware and
9531 * the value is returned in the `hwrm_resp_hdr` upon completion.
9535 * The target ID of the command:
9536 * * 0x0-0xFFF8 - The function ID
9537 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
9538 * * 0xFFFD - Reserved for user-space HWRM interface
9543 * A physical address pointer pointing to a host buffer that the
9544 * command's response data will be written. This can be either a host
9545 * physical address (HPA) or a guest physical address (GPA) and must
9546 * point to a physically contiguous block of memory.
9551 * When this bit is '1', the function driver is notifying
9552 * the HWRM to prepare for the shutdown.
9554 #define HWRM_FUNC_DRV_UNRGTR_INPUT_FLAGS_PREPARE_FOR_SHUTDOWN \
9556 uint8_t unused_0[4];
9559 /* hwrm_func_drv_unrgtr_output (size:128b/16B) */
9560 struct hwrm_func_drv_unrgtr_output {
9561 /* The specific error status for the command. */
9562 uint16_t error_code;
9563 /* The HWRM command request type. */
9565 /* The sequence ID from the original command. */
9567 /* The length of the response data in number of bytes. */
9569 uint8_t unused_0[7];
9571 * This field is used in Output records to indicate that the output
9572 * is completely written to RAM. This field should be read as '1'
9573 * to indicate that the output has been completely written.
9574 * When writing a command completion or response to an internal processor,
9575 * the order of writes has to be such that this field is written last.
9580 /**********************
9581 * hwrm_func_buf_rgtr *
9582 **********************/
9585 /* hwrm_func_buf_rgtr_input (size:1024b/128B) */
9586 struct hwrm_func_buf_rgtr_input {
9587 /* The HWRM command request type. */
9590 * The completion ring to send the completion event on. This should
9591 * be the NQ ID returned from the `nq_alloc` HWRM command.
9595 * The sequence ID is used by the driver for tracking multiple
9596 * commands. This ID is treated as opaque data by the firmware and
9597 * the value is returned in the `hwrm_resp_hdr` upon completion.
9601 * The target ID of the command:
9602 * * 0x0-0xFFF8 - The function ID
9603 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
9604 * * 0xFFFD - Reserved for user-space HWRM interface
9609 * A physical address pointer pointing to a host buffer that the
9610 * command's response data will be written. This can be either a host
9611 * physical address (HPA) or a guest physical address (GPA) and must
9612 * point to a physically contiguous block of memory.
9617 * This bit must be '1' for the vf_id field to be
9620 #define HWRM_FUNC_BUF_RGTR_INPUT_ENABLES_VF_ID UINT32_C(0x1)
9622 * This bit must be '1' for the err_buf_addr field to be
9625 #define HWRM_FUNC_BUF_RGTR_INPUT_ENABLES_ERR_BUF_ADDR UINT32_C(0x2)
9627 * This value is used to identify a Virtual Function (VF).
9628 * The scope of VF ID is local within a PF.
9632 * This field represents the number of pages used for request
9635 uint16_t req_buf_num_pages;
9637 * This field represents the page size used for request
9640 uint16_t req_buf_page_size;
9642 #define HWRM_FUNC_BUF_RGTR_INPUT_REQ_BUF_PAGE_SIZE_16B UINT32_C(0x4)
9644 #define HWRM_FUNC_BUF_RGTR_INPUT_REQ_BUF_PAGE_SIZE_4K UINT32_C(0xc)
9646 #define HWRM_FUNC_BUF_RGTR_INPUT_REQ_BUF_PAGE_SIZE_8K UINT32_C(0xd)
9648 #define HWRM_FUNC_BUF_RGTR_INPUT_REQ_BUF_PAGE_SIZE_64K UINT32_C(0x10)
9650 #define HWRM_FUNC_BUF_RGTR_INPUT_REQ_BUF_PAGE_SIZE_2M UINT32_C(0x15)
9652 #define HWRM_FUNC_BUF_RGTR_INPUT_REQ_BUF_PAGE_SIZE_4M UINT32_C(0x16)
9654 #define HWRM_FUNC_BUF_RGTR_INPUT_REQ_BUF_PAGE_SIZE_1G UINT32_C(0x1e)
9655 #define HWRM_FUNC_BUF_RGTR_INPUT_REQ_BUF_PAGE_SIZE_LAST \
9656 HWRM_FUNC_BUF_RGTR_INPUT_REQ_BUF_PAGE_SIZE_1G
9657 /* The length of the request buffer per VF in bytes. */
9658 uint16_t req_buf_len;
9659 /* The length of the response buffer in bytes. */
9660 uint16_t resp_buf_len;
9661 uint8_t unused_0[2];
9662 /* This field represents the page address of page #0. */
9663 uint64_t req_buf_page_addr0;
9664 /* This field represents the page address of page #1. */
9665 uint64_t req_buf_page_addr1;
9666 /* This field represents the page address of page #2. */
9667 uint64_t req_buf_page_addr2;
9668 /* This field represents the page address of page #3. */
9669 uint64_t req_buf_page_addr3;
9670 /* This field represents the page address of page #4. */
9671 uint64_t req_buf_page_addr4;
9672 /* This field represents the page address of page #5. */
9673 uint64_t req_buf_page_addr5;
9674 /* This field represents the page address of page #6. */
9675 uint64_t req_buf_page_addr6;
9676 /* This field represents the page address of page #7. */
9677 uint64_t req_buf_page_addr7;
9678 /* This field represents the page address of page #8. */
9679 uint64_t req_buf_page_addr8;
9680 /* This field represents the page address of page #9. */
9681 uint64_t req_buf_page_addr9;
9683 * This field is used to receive the error reporting from
9684 * the chipset. Only applicable for PFs.
9686 uint64_t error_buf_addr;
9688 * This field is used to receive the response forwarded by the
9691 uint64_t resp_buf_addr;
9694 /* hwrm_func_buf_rgtr_output (size:128b/16B) */
9695 struct hwrm_func_buf_rgtr_output {
9696 /* The specific error status for the command. */
9697 uint16_t error_code;
9698 /* The HWRM command request type. */
9700 /* The sequence ID from the original command. */
9702 /* The length of the response data in number of bytes. */
9704 uint8_t unused_0[7];
9706 * This field is used in Output records to indicate that the output
9707 * is completely written to RAM. This field should be read as '1'
9708 * to indicate that the output has been completely written.
9709 * When writing a command completion or response to an internal processor,
9710 * the order of writes has to be such that this field is written last.
9715 /************************
9716 * hwrm_func_buf_unrgtr *
9717 ************************/
9720 /* hwrm_func_buf_unrgtr_input (size:192b/24B) */
9721 struct hwrm_func_buf_unrgtr_input {
9722 /* The HWRM command request type. */
9725 * The completion ring to send the completion event on. This should
9726 * be the NQ ID returned from the `nq_alloc` HWRM command.
9730 * The sequence ID is used by the driver for tracking multiple
9731 * commands. This ID is treated as opaque data by the firmware and
9732 * the value is returned in the `hwrm_resp_hdr` upon completion.
9736 * The target ID of the command:
9737 * * 0x0-0xFFF8 - The function ID
9738 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
9739 * * 0xFFFD - Reserved for user-space HWRM interface
9744 * A physical address pointer pointing to a host buffer that the
9745 * command's response data will be written. This can be either a host
9746 * physical address (HPA) or a guest physical address (GPA) and must
9747 * point to a physically contiguous block of memory.
9752 * This bit must be '1' for the vf_id field to be
9755 #define HWRM_FUNC_BUF_UNRGTR_INPUT_ENABLES_VF_ID UINT32_C(0x1)
9757 * This value is used to identify a Virtual Function (VF).
9758 * The scope of VF ID is local within a PF.
9761 uint8_t unused_0[2];
9764 /* hwrm_func_buf_unrgtr_output (size:128b/16B) */
9765 struct hwrm_func_buf_unrgtr_output {
9766 /* The specific error status for the command. */
9767 uint16_t error_code;
9768 /* The HWRM command request type. */
9770 /* The sequence ID from the original command. */
9772 /* The length of the response data in number of bytes. */
9774 uint8_t unused_0[7];
9776 * This field is used in Output records to indicate that the output
9777 * is completely written to RAM. This field should be read as '1'
9778 * to indicate that the output has been completely written.
9779 * When writing a command completion or response to an internal processor,
9780 * the order of writes has to be such that this field is written last.
9785 /**********************
9786 * hwrm_func_drv_qver *
9787 **********************/
9790 /* hwrm_func_drv_qver_input (size:192b/24B) */
9791 struct hwrm_func_drv_qver_input {
9792 /* The HWRM command request type. */
9795 * The completion ring to send the completion event on. This should
9796 * be the NQ ID returned from the `nq_alloc` HWRM command.
9800 * The sequence ID is used by the driver for tracking multiple
9801 * commands. This ID is treated as opaque data by the firmware and
9802 * the value is returned in the `hwrm_resp_hdr` upon completion.
9806 * The target ID of the command:
9807 * * 0x0-0xFFF8 - The function ID
9808 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
9809 * * 0xFFFD - Reserved for user-space HWRM interface
9814 * A physical address pointer pointing to a host buffer that the
9815 * command's response data will be written. This can be either a host
9816 * physical address (HPA) or a guest physical address (GPA) and must
9817 * point to a physically contiguous block of memory.
9820 /* Reserved for future use. */
9823 * Function ID of the function that is being queried.
9824 * 0xFF... (All Fs) if the query is for the requesting
9828 uint8_t unused_0[2];
9831 /* hwrm_func_drv_qver_output (size:256b/32B) */
9832 struct hwrm_func_drv_qver_output {
9833 /* The specific error status for the command. */
9834 uint16_t error_code;
9835 /* The HWRM command request type. */
9837 /* The sequence ID from the original command. */
9839 /* The length of the response data in number of bytes. */
9841 /* This value indicates the type of OS. The values are based on CIM_OperatingSystem.mof file as published by the DMTF. */
9844 #define HWRM_FUNC_DRV_QVER_OUTPUT_OS_TYPE_UNKNOWN UINT32_C(0x0)
9845 /* Other OS not listed below. */
9846 #define HWRM_FUNC_DRV_QVER_OUTPUT_OS_TYPE_OTHER UINT32_C(0x1)
9848 #define HWRM_FUNC_DRV_QVER_OUTPUT_OS_TYPE_MSDOS UINT32_C(0xe)
9850 #define HWRM_FUNC_DRV_QVER_OUTPUT_OS_TYPE_WINDOWS UINT32_C(0x12)
9852 #define HWRM_FUNC_DRV_QVER_OUTPUT_OS_TYPE_SOLARIS UINT32_C(0x1d)
9854 #define HWRM_FUNC_DRV_QVER_OUTPUT_OS_TYPE_LINUX UINT32_C(0x24)
9856 #define HWRM_FUNC_DRV_QVER_OUTPUT_OS_TYPE_FREEBSD UINT32_C(0x2a)
9857 /* VMware ESXi OS. */
9858 #define HWRM_FUNC_DRV_QVER_OUTPUT_OS_TYPE_ESXI UINT32_C(0x68)
9859 /* Microsoft Windows 8 64-bit OS. */
9860 #define HWRM_FUNC_DRV_QVER_OUTPUT_OS_TYPE_WIN864 UINT32_C(0x73)
9861 /* Microsoft Windows Server 2012 R2 OS. */
9862 #define HWRM_FUNC_DRV_QVER_OUTPUT_OS_TYPE_WIN2012R2 UINT32_C(0x74)
9864 #define HWRM_FUNC_DRV_QVER_OUTPUT_OS_TYPE_UEFI UINT32_C(0x8000)
9865 #define HWRM_FUNC_DRV_QVER_OUTPUT_OS_TYPE_LAST \
9866 HWRM_FUNC_DRV_QVER_OUTPUT_OS_TYPE_UEFI
9867 /* This is the 8bit major version of the driver. */
9869 /* This is the 8bit minor version of the driver. */
9871 /* This is the 8bit update version of the driver. */
9873 uint8_t unused_0[3];
9874 /* This is the 16bit major version of the driver. */
9876 /* This is the 16bit minor version of the driver. */
9878 /* This is the 16bit update version of the driver. */
9880 /* This is the 16bit patch version of the driver. */
9882 uint8_t unused_1[7];
9884 * This field is used in Output records to indicate that the output
9885 * is completely written to RAM. This field should be read as '1'
9886 * to indicate that the output has been completely written.
9887 * When writing a command completion or response to an internal processor,
9888 * the order of writes has to be such that this field is written last.
9893 /****************************
9894 * hwrm_func_resource_qcaps *
9895 ****************************/
9898 /* hwrm_func_resource_qcaps_input (size:192b/24B) */
9899 struct hwrm_func_resource_qcaps_input {
9900 /* The HWRM command request type. */
9903 * The completion ring to send the completion event on. This should
9904 * be the NQ ID returned from the `nq_alloc` HWRM command.
9908 * The sequence ID is used by the driver for tracking multiple
9909 * commands. This ID is treated as opaque data by the firmware and
9910 * the value is returned in the `hwrm_resp_hdr` upon completion.
9914 * The target ID of the command:
9915 * * 0x0-0xFFF8 - The function ID
9916 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
9917 * * 0xFFFD - Reserved for user-space HWRM interface
9922 * A physical address pointer pointing to a host buffer that the
9923 * command's response data will be written. This can be either a host
9924 * physical address (HPA) or a guest physical address (GPA) and must
9925 * point to a physically contiguous block of memory.
9929 * Function ID of the function that is being queried.
9930 * 0xFF... (All Fs) if the query is for the requesting
9934 uint8_t unused_0[6];
9937 /* hwrm_func_resource_qcaps_output (size:448b/56B) */
9938 struct hwrm_func_resource_qcaps_output {
9939 /* The specific error status for the command. */
9940 uint16_t error_code;
9941 /* The HWRM command request type. */
9943 /* The sequence ID from the original command. */
9945 /* The length of the response data in number of bytes. */
9947 /* Maximum guaranteed number of VFs supported by PF. Not applicable for VFs. */
9949 /* Maximum guaranteed number of MSI-X vectors supported by function */
9951 /* Hint of strategy to be used by PF driver to reserve resources for its VF */
9952 uint16_t vf_reservation_strategy;
9953 /* The PF driver should evenly divide its remaining resources among all VFs. */
9954 #define HWRM_FUNC_RESOURCE_QCAPS_OUTPUT_VF_RESERVATION_STRATEGY_MAXIMAL \
9956 /* The PF driver should only reserve minimal resources for each VF. */
9957 #define HWRM_FUNC_RESOURCE_QCAPS_OUTPUT_VF_RESERVATION_STRATEGY_MINIMAL \
9960 * The PF driver should not reserve any resources for each VF until the
9961 * the VF interface is brought up.
9963 #define HWRM_FUNC_RESOURCE_QCAPS_OUTPUT_VF_RESERVATION_STRATEGY_MINIMAL_STATIC \
9965 #define HWRM_FUNC_RESOURCE_QCAPS_OUTPUT_VF_RESERVATION_STRATEGY_LAST \
9966 HWRM_FUNC_RESOURCE_QCAPS_OUTPUT_VF_RESERVATION_STRATEGY_MINIMAL_STATIC
9967 /* Minimum guaranteed number of RSS/COS contexts */
9968 uint16_t min_rsscos_ctx;
9969 /* Maximum non-guaranteed number of RSS/COS contexts */
9970 uint16_t max_rsscos_ctx;
9971 /* Minimum guaranteed number of completion rings */
9972 uint16_t min_cmpl_rings;
9973 /* Maximum non-guaranteed number of completion rings */
9974 uint16_t max_cmpl_rings;
9975 /* Minimum guaranteed number of transmit rings */
9976 uint16_t min_tx_rings;
9977 /* Maximum non-guaranteed number of transmit rings */
9978 uint16_t max_tx_rings;
9979 /* Minimum guaranteed number of receive rings */
9980 uint16_t min_rx_rings;
9981 /* Maximum non-guaranteed number of receive rings */
9982 uint16_t max_rx_rings;
9983 /* Minimum guaranteed number of L2 contexts */
9984 uint16_t min_l2_ctxs;
9985 /* Maximum non-guaranteed number of L2 contexts */
9986 uint16_t max_l2_ctxs;
9987 /* Minimum guaranteed number of VNICs */
9989 /* Maximum non-guaranteed number of VNICs */
9991 /* Minimum guaranteed number of statistic contexts */
9992 uint16_t min_stat_ctx;
9993 /* Maximum non-guaranteed number of statistic contexts */
9994 uint16_t max_stat_ctx;
9995 /* Minimum guaranteed number of ring groups */
9996 uint16_t min_hw_ring_grps;
9997 /* Maximum non-guaranteed number of ring groups */
9998 uint16_t max_hw_ring_grps;
10000 * Maximum number of inputs into the transmit scheduler for this function.
10001 * The number of TX rings assigned to the function cannot exceed this value.
10003 uint16_t max_tx_scheduler_inputs;
10006 * When this bit is '1', it indicates that VF_RESOURCE_CFG supports
10007 * feature to reserve all minimum resources when minimum >= 1, otherwise
10008 * returns an error.
10010 #define HWRM_FUNC_RESOURCE_QCAPS_OUTPUT_FLAGS_MIN_GUARANTEED \
10012 uint8_t unused_0[5];
10014 * This field is used in Output records to indicate that the output
10015 * is completely written to RAM. This field should be read as '1'
10016 * to indicate that the output has been completely written.
10017 * When writing a command completion or response to an internal processor,
10018 * the order of writes has to be such that this field is written last.
10023 /*********************************
10024 * hwrm_func_backing_store_qcaps *
10025 *********************************/
10028 /* hwrm_func_backing_store_qcaps_input (size:128b/16B) */
10029 struct hwrm_func_backing_store_qcaps_input {
10030 /* The HWRM command request type. */
10033 * The completion ring to send the completion event on. This should
10034 * be the NQ ID returned from the `nq_alloc` HWRM command.
10036 uint16_t cmpl_ring;
10038 * The sequence ID is used by the driver for tracking multiple
10039 * commands. This ID is treated as opaque data by the firmware and
10040 * the value is returned in the `hwrm_resp_hdr` upon completion.
10044 * The target ID of the command:
10045 * * 0x0-0xFFF8 - The function ID
10046 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
10047 * * 0xFFFD - Reserved for user-space HWRM interface
10050 uint16_t target_id;
10052 * A physical address pointer pointing to a host buffer that the
10053 * command's response data will be written. This can be either a host
10054 * physical address (HPA) or a guest physical address (GPA) and must
10055 * point to a physically contiguous block of memory.
10057 uint64_t resp_addr;
10060 /* hwrm_func_backing_store_qcaps_output (size:640b/80B) */
10061 struct hwrm_func_backing_store_qcaps_output {
10062 /* The specific error status for the command. */
10063 uint16_t error_code;
10064 /* The HWRM command request type. */
10066 /* The sequence ID from the original command. */
10068 /* The length of the response data in number of bytes. */
10070 /* Maximum number of QP context entries supported for this function. */
10071 uint32_t qp_max_entries;
10073 * Minimum number of QP context entries that are needed to be reserved
10074 * for QP1 for the PF and its VFs. PF drivers must allocate at least
10075 * this many QP context entries, even if RoCE will not be used.
10077 uint16_t qp_min_qp1_entries;
10078 /* Maximum number of QP context entries that can be used for L2. */
10079 uint16_t qp_max_l2_entries;
10080 /* Number of bytes that must be allocated for each context entry. */
10081 uint16_t qp_entry_size;
10082 /* Maximum number of SRQ context entries that can be used for L2. */
10083 uint16_t srq_max_l2_entries;
10084 /* Maximum number of SRQ context entries supported for this function. */
10085 uint32_t srq_max_entries;
10086 /* Number of bytes that must be allocated for each context entry. */
10087 uint16_t srq_entry_size;
10088 /* Maximum number of CQ context entries that can be used for L2. */
10089 uint16_t cq_max_l2_entries;
10090 /* Maximum number of CQ context entries supported for this function. */
10091 uint32_t cq_max_entries;
10092 /* Number of bytes that must be allocated for each context entry. */
10093 uint16_t cq_entry_size;
10094 /* Maximum number of VNIC context entries supported for this function. */
10095 uint16_t vnic_max_vnic_entries;
10096 /* Maximum number of Ring table context entries supported for this function. */
10097 uint16_t vnic_max_ring_table_entries;
10098 /* Number of bytes that must be allocated for each context entry. */
10099 uint16_t vnic_entry_size;
10100 /* Maximum number of statistic context entries supported for this function. */
10101 uint32_t stat_max_entries;
10102 /* Number of bytes that must be allocated for each context entry. */
10103 uint16_t stat_entry_size;
10104 /* Number of bytes that must be allocated for each context entry. */
10105 uint16_t tqm_entry_size;
10106 /* Minimum number of TQM context entries required per ring. */
10107 uint32_t tqm_min_entries_per_ring;
10109 * Maximum number of TQM context entries supported per ring. This is
10110 * actually a recommended TQM queue size based on worst case usage of
10113 * TQM fastpath rings should be sized large enough to accommodate the
10114 * maximum number of QPs (either L2 or RoCE, or both if shared)
10115 * that can be enqueued to the TQM ring.
10117 * TQM slowpath rings should be sized as follows:
10119 * num_entries = num_vnics + num_l2_tx_rings + num_roce_qps + tqm_min_size
10122 * num_vnics is the number of VNICs allocated in the VNIC backing store
10123 * num_l2_tx_rings is the number of L2 rings in the QP backing store
10124 * num_roce_qps is the number of RoCE QPs in the QP backing store
10125 * tqm_min_size is tqm_min_entries_per_ring reported by
10126 * HWRM_FUNC_BACKING_STORE_QCAPS
10128 * Note that TQM ring sizes cannot be extended while the system is
10129 * operational. If a PF driver needs to extend a TQM ring, it needs
10130 * to reset the function (e.g. HWRM_FUNC_RESET) and then reallocate
10131 * the backing store.
10133 uint32_t tqm_max_entries_per_ring;
10135 * Maximum number of MR plus AV context entries supported for this
10138 uint32_t mrav_max_entries;
10139 /* Number of bytes that must be allocated for each context entry. */
10140 uint16_t mrav_entry_size;
10141 /* Number of bytes that must be allocated for each context entry. */
10142 uint16_t tim_entry_size;
10143 /* Maximum number of Timer context entries supported for this function. */
10144 uint32_t tim_max_entries;
10146 * When this field is zero, the 32b `mrav_num_entries` field in the
10147 * `backing_store_cfg` and `backing_store_qcfg` commands represents
10148 * the total number of MR plus AV entries allowed in the MR/AV backing
10151 * When this field is non-zero, the 32b `mrav_num_entries` field in
10152 * the `backing_store_cfg` and `backing_store_qcfg` commands is
10153 * logically divided into two 16b fields. Bits `[31:16]` represents
10154 * the `mr_num_entries` and bits `[15:0]` represents `av_num_entries`.
10155 * Both of these values are represented in a unit granularity
10156 * specified by this field. For example, if this field is 16 and
10157 * `mrav_num_entries` is `0x02000100`, then the number of MR entries
10158 * is 8192 and the number of AV entries is 4096.
10160 uint16_t mrav_num_entries_units;
10162 * The number of entries specified for any TQM ring must be a
10163 * multiple of this value to prevent any resource allocation
10166 uint8_t tqm_entries_multiple;
10168 * Initializer to be used by drivers
10169 * to initialize context memory to ensure
10170 * context subsystem flags an error for an attack
10171 * before the first time context load.
10173 uint8_t ctx_kind_initializer;
10174 /* Reserved for future. */
10176 /* Reserved for future. */
10179 * Count of TQM fastpath rings to be used for allocating backing store.
10180 * Backing store configuration must be specified for each TQM ring from
10181 * this count in `backing_store_cfg`.
10183 uint8_t tqm_fp_rings_count;
10185 * This field is used in Output records to indicate that the output
10186 * is completely written to RAM. This field should be read as '1'
10187 * to indicate that the output has been completely written.
10188 * When writing a command completion or response to an internal processor,
10189 * the order of writes has to be such that this field is written last.
10194 /*******************************
10195 * hwrm_func_backing_store_cfg *
10196 *******************************/
10199 /* hwrm_func_backing_store_cfg_input (size:2048b/256B) */
10200 struct hwrm_func_backing_store_cfg_input {
10201 /* The HWRM command request type. */
10204 * The completion ring to send the completion event on. This should
10205 * be the NQ ID returned from the `nq_alloc` HWRM command.
10207 uint16_t cmpl_ring;
10209 * The sequence ID is used by the driver for tracking multiple
10210 * commands. This ID is treated as opaque data by the firmware and
10211 * the value is returned in the `hwrm_resp_hdr` upon completion.
10215 * The target ID of the command:
10216 * * 0x0-0xFFF8 - The function ID
10217 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
10218 * * 0xFFFD - Reserved for user-space HWRM interface
10221 uint16_t target_id;
10223 * A physical address pointer pointing to a host buffer that the
10224 * command's response data will be written. This can be either a host
10225 * physical address (HPA) or a guest physical address (GPA) and must
10226 * point to a physically contiguous block of memory.
10228 uint64_t resp_addr;
10231 * When set, the firmware only uses on-chip resources and does not
10232 * expect any backing store to be provided by the host driver. This
10233 * mode provides minimal L2 functionality (e.g. limited L2 resources,
10236 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_FLAGS_PREBOOT_MODE \
10239 * When set, the 32b `mrav_num_entries` field is logically divided
10240 * into two 16b fields, `mr_num_entries` and `av_num_entries`.
10242 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_FLAGS_MRAV_RESERVATION_SPLIT \
10246 * This bit must be '1' for the qp fields to be
10249 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_QP \
10252 * This bit must be '1' for the srq fields to be
10255 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_SRQ \
10258 * This bit must be '1' for the cq fields to be
10261 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_CQ \
10264 * This bit must be '1' for the vnic fields to be
10267 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_VNIC \
10270 * This bit must be '1' for the stat fields to be
10273 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_STAT \
10276 * This bit must be '1' for the tqm_sp fields to be
10279 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_TQM_SP \
10282 * This bit must be '1' for the tqm_ring0 fields to be
10285 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_TQM_RING0 \
10288 * This bit must be '1' for the tqm_ring1 fields to be
10291 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_TQM_RING1 \
10294 * This bit must be '1' for the tqm_ring2 fields to be
10297 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_TQM_RING2 \
10300 * This bit must be '1' for the tqm_ring3 fields to be
10303 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_TQM_RING3 \
10306 * This bit must be '1' for the tqm_ring4 fields to be
10309 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_TQM_RING4 \
10312 * This bit must be '1' for the tqm_ring5 fields to be
10315 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_TQM_RING5 \
10318 * This bit must be '1' for the tqm_ring6 fields to be
10321 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_TQM_RING6 \
10324 * This bit must be '1' for the tqm_ring7 fields to be
10327 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_TQM_RING7 \
10330 * This bit must be '1' for the mrav fields to be
10333 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_MRAV \
10336 * This bit must be '1' for the tim fields to be
10339 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_TIM \
10341 /* QPC page size and level. */
10342 uint8_t qpc_pg_size_qpc_lvl;
10343 /* QPC PBL indirect levels. */
10344 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_QPC_LVL_MASK \
10346 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_QPC_LVL_SFT 0
10347 /* PBL pointer is physical start address. */
10348 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_QPC_LVL_LVL_0 \
10350 /* PBL pointer points to PTE table. */
10351 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_QPC_LVL_LVL_1 \
10353 /* PBL pointer points to PDE table with each entry pointing to PTE tables. */
10354 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_QPC_LVL_LVL_2 \
10356 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_QPC_LVL_LAST \
10357 HWRM_FUNC_BACKING_STORE_CFG_INPUT_QPC_LVL_LVL_2
10358 /* QPC page size. */
10359 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_QPC_PG_SIZE_MASK \
10361 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_QPC_PG_SIZE_SFT 4
10363 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_QPC_PG_SIZE_PG_4K \
10364 (UINT32_C(0x0) << 4)
10366 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_QPC_PG_SIZE_PG_8K \
10367 (UINT32_C(0x1) << 4)
10369 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_QPC_PG_SIZE_PG_64K \
10370 (UINT32_C(0x2) << 4)
10372 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_QPC_PG_SIZE_PG_2M \
10373 (UINT32_C(0x3) << 4)
10375 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_QPC_PG_SIZE_PG_8M \
10376 (UINT32_C(0x4) << 4)
10378 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_QPC_PG_SIZE_PG_1G \
10379 (UINT32_C(0x5) << 4)
10380 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_QPC_PG_SIZE_LAST \
10381 HWRM_FUNC_BACKING_STORE_CFG_INPUT_QPC_PG_SIZE_PG_1G
10382 /* SRQ page size and level. */
10383 uint8_t srq_pg_size_srq_lvl;
10384 /* SRQ PBL indirect levels. */
10385 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_SRQ_LVL_MASK \
10387 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_SRQ_LVL_SFT 0
10388 /* PBL pointer is physical start address. */
10389 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_SRQ_LVL_LVL_0 \
10391 /* PBL pointer points to PTE table. */
10392 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_SRQ_LVL_LVL_1 \
10394 /* PBL pointer points to PDE table with each entry pointing to PTE tables. */
10395 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_SRQ_LVL_LVL_2 \
10397 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_SRQ_LVL_LAST \
10398 HWRM_FUNC_BACKING_STORE_CFG_INPUT_SRQ_LVL_LVL_2
10399 /* SRQ page size. */
10400 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_SRQ_PG_SIZE_MASK \
10402 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_SRQ_PG_SIZE_SFT 4
10404 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_SRQ_PG_SIZE_PG_4K \
10405 (UINT32_C(0x0) << 4)
10407 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_SRQ_PG_SIZE_PG_8K \
10408 (UINT32_C(0x1) << 4)
10410 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_SRQ_PG_SIZE_PG_64K \
10411 (UINT32_C(0x2) << 4)
10413 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_SRQ_PG_SIZE_PG_2M \
10414 (UINT32_C(0x3) << 4)
10416 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_SRQ_PG_SIZE_PG_8M \
10417 (UINT32_C(0x4) << 4)
10419 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_SRQ_PG_SIZE_PG_1G \
10420 (UINT32_C(0x5) << 4)
10421 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_SRQ_PG_SIZE_LAST \
10422 HWRM_FUNC_BACKING_STORE_CFG_INPUT_SRQ_PG_SIZE_PG_1G
10423 /* CQ page size and level. */
10424 uint8_t cq_pg_size_cq_lvl;
10425 /* CQ PBL indirect levels. */
10426 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_CQ_LVL_MASK \
10428 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_CQ_LVL_SFT 0
10429 /* PBL pointer is physical start address. */
10430 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_CQ_LVL_LVL_0 \
10432 /* PBL pointer points to PTE table. */
10433 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_CQ_LVL_LVL_1 \
10435 /* PBL pointer points to PDE table with each entry pointing to PTE tables. */
10436 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_CQ_LVL_LVL_2 \
10438 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_CQ_LVL_LAST \
10439 HWRM_FUNC_BACKING_STORE_CFG_INPUT_CQ_LVL_LVL_2
10440 /* CQ page size. */
10441 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_CQ_PG_SIZE_MASK \
10443 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_CQ_PG_SIZE_SFT 4
10445 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_CQ_PG_SIZE_PG_4K \
10446 (UINT32_C(0x0) << 4)
10448 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_CQ_PG_SIZE_PG_8K \
10449 (UINT32_C(0x1) << 4)
10451 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_CQ_PG_SIZE_PG_64K \
10452 (UINT32_C(0x2) << 4)
10454 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_CQ_PG_SIZE_PG_2M \
10455 (UINT32_C(0x3) << 4)
10457 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_CQ_PG_SIZE_PG_8M \
10458 (UINT32_C(0x4) << 4)
10460 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_CQ_PG_SIZE_PG_1G \
10461 (UINT32_C(0x5) << 4)
10462 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_CQ_PG_SIZE_LAST \
10463 HWRM_FUNC_BACKING_STORE_CFG_INPUT_CQ_PG_SIZE_PG_1G
10464 /* VNIC page size and level. */
10465 uint8_t vnic_pg_size_vnic_lvl;
10466 /* VNIC PBL indirect levels. */
10467 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_VNIC_LVL_MASK \
10469 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_VNIC_LVL_SFT 0
10470 /* PBL pointer is physical start address. */
10471 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_VNIC_LVL_LVL_0 \
10473 /* PBL pointer points to PTE table. */
10474 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_VNIC_LVL_LVL_1 \
10476 /* PBL pointer points to PDE table with each entry pointing to PTE tables. */
10477 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_VNIC_LVL_LVL_2 \
10479 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_VNIC_LVL_LAST \
10480 HWRM_FUNC_BACKING_STORE_CFG_INPUT_VNIC_LVL_LVL_2
10481 /* VNIC page size. */
10482 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_VNIC_PG_SIZE_MASK \
10484 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_VNIC_PG_SIZE_SFT 4
10486 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_VNIC_PG_SIZE_PG_4K \
10487 (UINT32_C(0x0) << 4)
10489 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_VNIC_PG_SIZE_PG_8K \
10490 (UINT32_C(0x1) << 4)
10492 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_VNIC_PG_SIZE_PG_64K \
10493 (UINT32_C(0x2) << 4)
10495 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_VNIC_PG_SIZE_PG_2M \
10496 (UINT32_C(0x3) << 4)
10498 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_VNIC_PG_SIZE_PG_8M \
10499 (UINT32_C(0x4) << 4)
10501 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_VNIC_PG_SIZE_PG_1G \
10502 (UINT32_C(0x5) << 4)
10503 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_VNIC_PG_SIZE_LAST \
10504 HWRM_FUNC_BACKING_STORE_CFG_INPUT_VNIC_PG_SIZE_PG_1G
10505 /* Stat page size and level. */
10506 uint8_t stat_pg_size_stat_lvl;
10507 /* Stat PBL indirect levels. */
10508 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_STAT_LVL_MASK \
10510 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_STAT_LVL_SFT 0
10511 /* PBL pointer is physical start address. */
10512 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_STAT_LVL_LVL_0 \
10514 /* PBL pointer points to PTE table. */
10515 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_STAT_LVL_LVL_1 \
10517 /* PBL pointer points to PDE table with each entry pointing to PTE tables. */
10518 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_STAT_LVL_LVL_2 \
10520 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_STAT_LVL_LAST \
10521 HWRM_FUNC_BACKING_STORE_CFG_INPUT_STAT_LVL_LVL_2
10522 /* Stat page size. */
10523 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_STAT_PG_SIZE_MASK \
10525 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_STAT_PG_SIZE_SFT 4
10527 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_STAT_PG_SIZE_PG_4K \
10528 (UINT32_C(0x0) << 4)
10530 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_STAT_PG_SIZE_PG_8K \
10531 (UINT32_C(0x1) << 4)
10533 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_STAT_PG_SIZE_PG_64K \
10534 (UINT32_C(0x2) << 4)
10536 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_STAT_PG_SIZE_PG_2M \
10537 (UINT32_C(0x3) << 4)
10539 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_STAT_PG_SIZE_PG_8M \
10540 (UINT32_C(0x4) << 4)
10542 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_STAT_PG_SIZE_PG_1G \
10543 (UINT32_C(0x5) << 4)
10544 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_STAT_PG_SIZE_LAST \
10545 HWRM_FUNC_BACKING_STORE_CFG_INPUT_STAT_PG_SIZE_PG_1G
10546 /* TQM slow path page size and level. */
10547 uint8_t tqm_sp_pg_size_tqm_sp_lvl;
10548 /* TQM slow path PBL indirect levels. */
10549 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_SP_LVL_MASK \
10551 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_SP_LVL_SFT 0
10552 /* PBL pointer is physical start address. */
10553 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_SP_LVL_LVL_0 \
10555 /* PBL pointer points to PTE table. */
10556 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_SP_LVL_LVL_1 \
10558 /* PBL pointer points to PDE table with each entry pointing to PTE tables. */
10559 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_SP_LVL_LVL_2 \
10561 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_SP_LVL_LAST \
10562 HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_SP_LVL_LVL_2
10563 /* TQM slow path page size. */
10564 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_SP_PG_SIZE_MASK \
10566 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_SP_PG_SIZE_SFT 4
10568 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_SP_PG_SIZE_PG_4K \
10569 (UINT32_C(0x0) << 4)
10571 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_SP_PG_SIZE_PG_8K \
10572 (UINT32_C(0x1) << 4)
10574 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_SP_PG_SIZE_PG_64K \
10575 (UINT32_C(0x2) << 4)
10577 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_SP_PG_SIZE_PG_2M \
10578 (UINT32_C(0x3) << 4)
10580 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_SP_PG_SIZE_PG_8M \
10581 (UINT32_C(0x4) << 4)
10583 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_SP_PG_SIZE_PG_1G \
10584 (UINT32_C(0x5) << 4)
10585 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_SP_PG_SIZE_LAST \
10586 HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_SP_PG_SIZE_PG_1G
10587 /* TQM ring 0 page size and level. */
10588 uint8_t tqm_ring0_pg_size_tqm_ring0_lvl;
10589 /* TQM ring 0 PBL indirect levels. */
10590 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING0_LVL_MASK \
10592 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING0_LVL_SFT 0
10593 /* PBL pointer is physical start address. */
10594 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING0_LVL_LVL_0 \
10596 /* PBL pointer points to PTE table. */
10597 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING0_LVL_LVL_1 \
10599 /* PBL pointer points to PDE table with each entry pointing to PTE tables. */
10600 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING0_LVL_LVL_2 \
10602 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING0_LVL_LAST \
10603 HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING0_LVL_LVL_2
10604 /* TQM ring 0 page size. */
10605 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING0_PG_SIZE_MASK \
10607 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING0_PG_SIZE_SFT 4
10609 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING0_PG_SIZE_PG_4K \
10610 (UINT32_C(0x0) << 4)
10612 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING0_PG_SIZE_PG_8K \
10613 (UINT32_C(0x1) << 4)
10615 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING0_PG_SIZE_PG_64K \
10616 (UINT32_C(0x2) << 4)
10618 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING0_PG_SIZE_PG_2M \
10619 (UINT32_C(0x3) << 4)
10621 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING0_PG_SIZE_PG_8M \
10622 (UINT32_C(0x4) << 4)
10624 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING0_PG_SIZE_PG_1G \
10625 (UINT32_C(0x5) << 4)
10626 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING0_PG_SIZE_LAST \
10627 HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING0_PG_SIZE_PG_1G
10628 /* TQM ring 1 page size and level. */
10629 uint8_t tqm_ring1_pg_size_tqm_ring1_lvl;
10630 /* TQM ring 1 PBL indirect levels. */
10631 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING1_LVL_MASK \
10633 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING1_LVL_SFT 0
10634 /* PBL pointer is physical start address. */
10635 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING1_LVL_LVL_0 \
10637 /* PBL pointer points to PTE table. */
10638 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING1_LVL_LVL_1 \
10640 /* PBL pointer points to PDE table with each entry pointing to PTE tables. */
10641 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING1_LVL_LVL_2 \
10643 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING1_LVL_LAST \
10644 HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING1_LVL_LVL_2
10645 /* TQM ring 1 page size. */
10646 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING1_PG_SIZE_MASK \
10648 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING1_PG_SIZE_SFT 4
10650 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING1_PG_SIZE_PG_4K \
10651 (UINT32_C(0x0) << 4)
10653 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING1_PG_SIZE_PG_8K \
10654 (UINT32_C(0x1) << 4)
10656 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING1_PG_SIZE_PG_64K \
10657 (UINT32_C(0x2) << 4)
10659 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING1_PG_SIZE_PG_2M \
10660 (UINT32_C(0x3) << 4)
10662 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING1_PG_SIZE_PG_8M \
10663 (UINT32_C(0x4) << 4)
10665 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING1_PG_SIZE_PG_1G \
10666 (UINT32_C(0x5) << 4)
10667 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING1_PG_SIZE_LAST \
10668 HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING1_PG_SIZE_PG_1G
10669 /* TQM ring 2 page size and level. */
10670 uint8_t tqm_ring2_pg_size_tqm_ring2_lvl;
10671 /* TQM ring 2 PBL indirect levels. */
10672 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING2_LVL_MASK \
10674 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING2_LVL_SFT 0
10675 /* PBL pointer is physical start address. */
10676 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING2_LVL_LVL_0 \
10678 /* PBL pointer points to PTE table. */
10679 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING2_LVL_LVL_1 \
10681 /* PBL pointer points to PDE table with each entry pointing to PTE tables. */
10682 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING2_LVL_LVL_2 \
10684 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING2_LVL_LAST \
10685 HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING2_LVL_LVL_2
10686 /* TQM ring 2 page size. */
10687 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING2_PG_SIZE_MASK \
10689 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING2_PG_SIZE_SFT 4
10691 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING2_PG_SIZE_PG_4K \
10692 (UINT32_C(0x0) << 4)
10694 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING2_PG_SIZE_PG_8K \
10695 (UINT32_C(0x1) << 4)
10697 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING2_PG_SIZE_PG_64K \
10698 (UINT32_C(0x2) << 4)
10700 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING2_PG_SIZE_PG_2M \
10701 (UINT32_C(0x3) << 4)
10703 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING2_PG_SIZE_PG_8M \
10704 (UINT32_C(0x4) << 4)
10706 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING2_PG_SIZE_PG_1G \
10707 (UINT32_C(0x5) << 4)
10708 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING2_PG_SIZE_LAST \
10709 HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING2_PG_SIZE_PG_1G
10710 /* TQM ring 3 page size and level. */
10711 uint8_t tqm_ring3_pg_size_tqm_ring3_lvl;
10712 /* TQM ring 3 PBL indirect levels. */
10713 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING3_LVL_MASK \
10715 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING3_LVL_SFT 0
10716 /* PBL pointer is physical start address. */
10717 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING3_LVL_LVL_0 \
10719 /* PBL pointer points to PTE table. */
10720 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING3_LVL_LVL_1 \
10722 /* PBL pointer points to PDE table with each entry pointing to PTE tables. */
10723 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING3_LVL_LVL_2 \
10725 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING3_LVL_LAST \
10726 HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING3_LVL_LVL_2
10727 /* TQM ring 3 page size. */
10728 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING3_PG_SIZE_MASK \
10730 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING3_PG_SIZE_SFT 4
10732 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING3_PG_SIZE_PG_4K \
10733 (UINT32_C(0x0) << 4)
10735 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING3_PG_SIZE_PG_8K \
10736 (UINT32_C(0x1) << 4)
10738 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING3_PG_SIZE_PG_64K \
10739 (UINT32_C(0x2) << 4)
10741 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING3_PG_SIZE_PG_2M \
10742 (UINT32_C(0x3) << 4)
10744 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING3_PG_SIZE_PG_8M \
10745 (UINT32_C(0x4) << 4)
10747 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING3_PG_SIZE_PG_1G \
10748 (UINT32_C(0x5) << 4)
10749 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING3_PG_SIZE_LAST \
10750 HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING3_PG_SIZE_PG_1G
10751 /* TQM ring 4 page size and level. */
10752 uint8_t tqm_ring4_pg_size_tqm_ring4_lvl;
10753 /* TQM ring 4 PBL indirect levels. */
10754 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING4_LVL_MASK \
10756 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING4_LVL_SFT 0
10757 /* PBL pointer is physical start address. */
10758 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING4_LVL_LVL_0 \
10760 /* PBL pointer points to PTE table. */
10761 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING4_LVL_LVL_1 \
10763 /* PBL pointer points to PDE table with each entry pointing to PTE tables. */
10764 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING4_LVL_LVL_2 \
10766 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING4_LVL_LAST \
10767 HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING4_LVL_LVL_2
10768 /* TQM ring 4 page size. */
10769 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING4_PG_SIZE_MASK \
10771 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING4_PG_SIZE_SFT 4
10773 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING4_PG_SIZE_PG_4K \
10774 (UINT32_C(0x0) << 4)
10776 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING4_PG_SIZE_PG_8K \
10777 (UINT32_C(0x1) << 4)
10779 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING4_PG_SIZE_PG_64K \
10780 (UINT32_C(0x2) << 4)
10782 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING4_PG_SIZE_PG_2M \
10783 (UINT32_C(0x3) << 4)
10785 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING4_PG_SIZE_PG_8M \
10786 (UINT32_C(0x4) << 4)
10788 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING4_PG_SIZE_PG_1G \
10789 (UINT32_C(0x5) << 4)
10790 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING4_PG_SIZE_LAST \
10791 HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING4_PG_SIZE_PG_1G
10792 /* TQM ring 5 page size and level. */
10793 uint8_t tqm_ring5_pg_size_tqm_ring5_lvl;
10794 /* TQM ring 5 PBL indirect levels. */
10795 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING5_LVL_MASK \
10797 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING5_LVL_SFT 0
10798 /* PBL pointer is physical start address. */
10799 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING5_LVL_LVL_0 \
10801 /* PBL pointer points to PTE table. */
10802 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING5_LVL_LVL_1 \
10804 /* PBL pointer points to PDE table with each entry pointing to PTE tables. */
10805 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING5_LVL_LVL_2 \
10807 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING5_LVL_LAST \
10808 HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING5_LVL_LVL_2
10809 /* TQM ring 5 page size. */
10810 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING5_PG_SIZE_MASK \
10812 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING5_PG_SIZE_SFT 4
10814 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING5_PG_SIZE_PG_4K \
10815 (UINT32_C(0x0) << 4)
10817 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING5_PG_SIZE_PG_8K \
10818 (UINT32_C(0x1) << 4)
10820 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING5_PG_SIZE_PG_64K \
10821 (UINT32_C(0x2) << 4)
10823 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING5_PG_SIZE_PG_2M \
10824 (UINT32_C(0x3) << 4)
10826 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING5_PG_SIZE_PG_8M \
10827 (UINT32_C(0x4) << 4)
10829 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING5_PG_SIZE_PG_1G \
10830 (UINT32_C(0x5) << 4)
10831 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING5_PG_SIZE_LAST \
10832 HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING5_PG_SIZE_PG_1G
10833 /* TQM ring 6 page size and level. */
10834 uint8_t tqm_ring6_pg_size_tqm_ring6_lvl;
10835 /* TQM ring 6 PBL indirect levels. */
10836 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING6_LVL_MASK \
10838 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING6_LVL_SFT 0
10839 /* PBL pointer is physical start address. */
10840 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING6_LVL_LVL_0 \
10842 /* PBL pointer points to PTE table. */
10843 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING6_LVL_LVL_1 \
10845 /* PBL pointer points to PDE table with each entry pointing to PTE tables. */
10846 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING6_LVL_LVL_2 \
10848 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING6_LVL_LAST \
10849 HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING6_LVL_LVL_2
10850 /* TQM ring 6 page size. */
10851 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING6_PG_SIZE_MASK \
10853 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING6_PG_SIZE_SFT 4
10855 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING6_PG_SIZE_PG_4K \
10856 (UINT32_C(0x0) << 4)
10858 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING6_PG_SIZE_PG_8K \
10859 (UINT32_C(0x1) << 4)
10861 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING6_PG_SIZE_PG_64K \
10862 (UINT32_C(0x2) << 4)
10864 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING6_PG_SIZE_PG_2M \
10865 (UINT32_C(0x3) << 4)
10867 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING6_PG_SIZE_PG_8M \
10868 (UINT32_C(0x4) << 4)
10870 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING6_PG_SIZE_PG_1G \
10871 (UINT32_C(0x5) << 4)
10872 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING6_PG_SIZE_LAST \
10873 HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING6_PG_SIZE_PG_1G
10874 /* TQM ring 7 page size and level. */
10875 uint8_t tqm_ring7_pg_size_tqm_ring7_lvl;
10876 /* TQM ring 7 PBL indirect levels. */
10877 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING7_LVL_MASK \
10879 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING7_LVL_SFT 0
10880 /* PBL pointer is physical start address. */
10881 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING7_LVL_LVL_0 \
10883 /* PBL pointer points to PTE table. */
10884 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING7_LVL_LVL_1 \
10886 /* PBL pointer points to PDE table with each entry pointing to PTE tables. */
10887 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING7_LVL_LVL_2 \
10889 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING7_LVL_LAST \
10890 HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING7_LVL_LVL_2
10891 /* TQM ring 7 page size. */
10892 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING7_PG_SIZE_MASK \
10894 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING7_PG_SIZE_SFT 4
10896 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING7_PG_SIZE_PG_4K \
10897 (UINT32_C(0x0) << 4)
10899 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING7_PG_SIZE_PG_8K \
10900 (UINT32_C(0x1) << 4)
10902 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING7_PG_SIZE_PG_64K \
10903 (UINT32_C(0x2) << 4)
10905 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING7_PG_SIZE_PG_2M \
10906 (UINT32_C(0x3) << 4)
10908 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING7_PG_SIZE_PG_8M \
10909 (UINT32_C(0x4) << 4)
10911 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING7_PG_SIZE_PG_1G \
10912 (UINT32_C(0x5) << 4)
10913 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING7_PG_SIZE_LAST \
10914 HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING7_PG_SIZE_PG_1G
10915 /* MR/AV page size and level. */
10916 uint8_t mrav_pg_size_mrav_lvl;
10917 /* MR/AV PBL indirect levels. */
10918 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_MRAV_LVL_MASK \
10920 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_MRAV_LVL_SFT 0
10921 /* PBL pointer is physical start address. */
10922 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_MRAV_LVL_LVL_0 \
10924 /* PBL pointer points to PTE table. */
10925 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_MRAV_LVL_LVL_1 \
10927 /* PBL pointer points to PDE table with each entry pointing to PTE tables. */
10928 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_MRAV_LVL_LVL_2 \
10930 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_MRAV_LVL_LAST \
10931 HWRM_FUNC_BACKING_STORE_CFG_INPUT_MRAV_LVL_LVL_2
10932 /* MR/AV page size. */
10933 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_MRAV_PG_SIZE_MASK \
10935 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_MRAV_PG_SIZE_SFT 4
10937 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_MRAV_PG_SIZE_PG_4K \
10938 (UINT32_C(0x0) << 4)
10940 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_MRAV_PG_SIZE_PG_8K \
10941 (UINT32_C(0x1) << 4)
10943 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_MRAV_PG_SIZE_PG_64K \
10944 (UINT32_C(0x2) << 4)
10946 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_MRAV_PG_SIZE_PG_2M \
10947 (UINT32_C(0x3) << 4)
10949 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_MRAV_PG_SIZE_PG_8M \
10950 (UINT32_C(0x4) << 4)
10952 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_MRAV_PG_SIZE_PG_1G \
10953 (UINT32_C(0x5) << 4)
10954 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_MRAV_PG_SIZE_LAST \
10955 HWRM_FUNC_BACKING_STORE_CFG_INPUT_MRAV_PG_SIZE_PG_1G
10956 /* Timer page size and level. */
10957 uint8_t tim_pg_size_tim_lvl;
10958 /* Timer PBL indirect levels. */
10959 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TIM_LVL_MASK \
10961 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TIM_LVL_SFT 0
10962 /* PBL pointer is physical start address. */
10963 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TIM_LVL_LVL_0 \
10965 /* PBL pointer points to PTE table. */
10966 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TIM_LVL_LVL_1 \
10968 /* PBL pointer points to PDE table with each entry pointing to PTE tables. */
10969 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TIM_LVL_LVL_2 \
10971 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TIM_LVL_LAST \
10972 HWRM_FUNC_BACKING_STORE_CFG_INPUT_TIM_LVL_LVL_2
10973 /* Timer page size. */
10974 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TIM_PG_SIZE_MASK \
10976 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TIM_PG_SIZE_SFT 4
10978 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TIM_PG_SIZE_PG_4K \
10979 (UINT32_C(0x0) << 4)
10981 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TIM_PG_SIZE_PG_8K \
10982 (UINT32_C(0x1) << 4)
10984 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TIM_PG_SIZE_PG_64K \
10985 (UINT32_C(0x2) << 4)
10987 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TIM_PG_SIZE_PG_2M \
10988 (UINT32_C(0x3) << 4)
10990 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TIM_PG_SIZE_PG_8M \
10991 (UINT32_C(0x4) << 4)
10993 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TIM_PG_SIZE_PG_1G \
10994 (UINT32_C(0x5) << 4)
10995 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TIM_PG_SIZE_LAST \
10996 HWRM_FUNC_BACKING_STORE_CFG_INPUT_TIM_PG_SIZE_PG_1G
10997 /* QP page directory. */
10998 uint64_t qpc_page_dir;
10999 /* SRQ page directory. */
11000 uint64_t srq_page_dir;
11001 /* CQ page directory. */
11002 uint64_t cq_page_dir;
11003 /* VNIC page directory. */
11004 uint64_t vnic_page_dir;
11005 /* Stat page directory. */
11006 uint64_t stat_page_dir;
11007 /* TQM slowpath page directory. */
11008 uint64_t tqm_sp_page_dir;
11009 /* TQM ring 0 page directory. */
11010 uint64_t tqm_ring0_page_dir;
11011 /* TQM ring 1 page directory. */
11012 uint64_t tqm_ring1_page_dir;
11013 /* TQM ring 2 page directory. */
11014 uint64_t tqm_ring2_page_dir;
11015 /* TQM ring 3 page directory. */
11016 uint64_t tqm_ring3_page_dir;
11017 /* TQM ring 4 page directory. */
11018 uint64_t tqm_ring4_page_dir;
11019 /* TQM ring 5 page directory. */
11020 uint64_t tqm_ring5_page_dir;
11021 /* TQM ring 6 page directory. */
11022 uint64_t tqm_ring6_page_dir;
11023 /* TQM ring 7 page directory. */
11024 uint64_t tqm_ring7_page_dir;
11025 /* MR/AV page directory. */
11026 uint64_t mrav_page_dir;
11027 /* Timer page directory. */
11028 uint64_t tim_page_dir;
11029 /* Number of QPs. */
11030 uint32_t qp_num_entries;
11031 /* Number of SRQs. */
11032 uint32_t srq_num_entries;
11033 /* Number of CQs. */
11034 uint32_t cq_num_entries;
11035 /* Number of Stats. */
11036 uint32_t stat_num_entries;
11038 * Number of TQM slowpath entries.
11040 * TQM slowpath rings should be sized as follows:
11042 * num_entries = num_vnics + num_l2_tx_rings + num_roce_qps + tqm_min_size
11045 * num_vnics is the number of VNICs allocated in the VNIC backing store
11046 * num_l2_tx_rings is the number of L2 rings in the QP backing store
11047 * num_roce_qps is the number of RoCE QPs in the QP backing store
11048 * tqm_min_size is tqm_min_entries_per_ring reported by
11049 * HWRM_FUNC_BACKING_STORE_QCAPS
11051 * Note that TQM ring sizes cannot be extended while the system is
11052 * operational. If a PF driver needs to extend a TQM ring, it needs
11053 * to reset the function (e.g. HWRM_FUNC_RESET) and then reallocate
11054 * the backing store.
11056 uint32_t tqm_sp_num_entries;
11058 * Number of TQM ring 0 entries.
11060 * TQM fastpath rings should be sized large enough to accommodate the
11061 * maximum number of QPs (either L2 or RoCE, or both if shared)
11062 * that can be enqueued to the TQM ring.
11064 * Note that TQM ring sizes cannot be extended while the system is
11065 * operational. If a PF driver needs to extend a TQM ring, it needs
11066 * to reset the function (e.g. HWRM_FUNC_RESET) and then reallocate
11067 * the backing store.
11069 uint32_t tqm_ring0_num_entries;
11071 * Number of TQM ring 1 entries.
11073 * TQM fastpath rings should be sized large enough to accommodate the
11074 * maximum number of QPs (either L2 or RoCE, or both if shared)
11075 * that can be enqueued to the TQM ring.
11077 * Note that TQM ring sizes cannot be extended while the system is
11078 * operational. If a PF driver needs to extend a TQM ring, it needs
11079 * to reset the function (e.g. HWRM_FUNC_RESET) and then reallocate
11080 * the backing store.
11082 uint32_t tqm_ring1_num_entries;
11084 * Number of TQM ring 2 entries.
11086 * TQM fastpath rings should be sized large enough to accommodate the
11087 * maximum number of QPs (either L2 or RoCE, or both if shared)
11088 * that can be enqueued to the TQM ring.
11090 * Note that TQM ring sizes cannot be extended while the system is
11091 * operational. If a PF driver needs to extend a TQM ring, it needs
11092 * to reset the function (e.g. HWRM_FUNC_RESET) and then reallocate
11093 * the backing store.
11095 uint32_t tqm_ring2_num_entries;
11097 * Number of TQM ring 3 entries.
11099 * TQM fastpath rings should be sized large enough to accommodate the
11100 * maximum number of QPs (either L2 or RoCE, or both if shared)
11101 * that can be enqueued to the TQM ring.
11103 * Note that TQM ring sizes cannot be extended while the system is
11104 * operational. If a PF driver needs to extend a TQM ring, it needs
11105 * to reset the function (e.g. HWRM_FUNC_RESET) and then reallocate
11106 * the backing store.
11108 uint32_t tqm_ring3_num_entries;
11110 * Number of TQM ring 4 entries.
11112 * TQM fastpath rings should be sized large enough to accommodate the
11113 * maximum number of QPs (either L2 or RoCE, or both if shared)
11114 * that can be enqueued to the TQM ring.
11116 * Note that TQM ring sizes cannot be extended while the system is
11117 * operational. If a PF driver needs to extend a TQM ring, it needs
11118 * to reset the function (e.g. HWRM_FUNC_RESET) and then reallocate
11119 * the backing store.
11121 uint32_t tqm_ring4_num_entries;
11123 * Number of TQM ring 5 entries.
11125 * TQM fastpath rings should be sized large enough to accommodate the
11126 * maximum number of QPs (either L2 or RoCE, or both if shared)
11127 * that can be enqueued to the TQM ring.
11129 * Note that TQM ring sizes cannot be extended while the system is
11130 * operational. If a PF driver needs to extend a TQM ring, it needs
11131 * to reset the function (e.g. HWRM_FUNC_RESET) and then reallocate
11132 * the backing store.
11134 uint32_t tqm_ring5_num_entries;
11136 * Number of TQM ring 6 entries.
11138 * TQM fastpath rings should be sized large enough to accommodate the
11139 * maximum number of QPs (either L2 or RoCE, or both if shared)
11140 * that can be enqueued to the TQM ring.
11142 * Note that TQM ring sizes cannot be extended while the system is
11143 * operational. If a PF driver needs to extend a TQM ring, it needs
11144 * to reset the function (e.g. HWRM_FUNC_RESET) and then reallocate
11145 * the backing store.
11147 uint32_t tqm_ring6_num_entries;
11149 * Number of TQM ring 7 entries.
11151 * TQM fastpath rings should be sized large enough to accommodate the
11152 * maximum number of QPs (either L2 or RoCE, or both if shared)
11153 * that can be enqueued to the TQM ring.
11155 * Note that TQM ring sizes cannot be extended while the system is
11156 * operational. If a PF driver needs to extend a TQM ring, it needs
11157 * to reset the function (e.g. HWRM_FUNC_RESET) and then reallocate
11158 * the backing store.
11160 uint32_t tqm_ring7_num_entries;
11162 * If the MR/AV split reservation flag is not set, then this field
11163 * represents the total number of MR plus AV entries. For versions
11164 * of firmware that support the split reservation, when it is not
11165 * specified half of the entries will be reserved for MRs and the
11166 * other half for AVs.
11168 * If the MR/AV split reservation flag is set, then this
11169 * field is logically divided into two 16b fields. Bits `[31:16]`
11170 * represents the `mr_num_entries` and bits `[15:0]` represents
11171 * `av_num_entries`. The granularity of these values is defined by
11172 * the `mrav_num_entries_unit` field returned by the
11173 * `backing_store_qcaps` command.
11175 uint32_t mrav_num_entries;
11176 /* Number of Timer entries. */
11177 uint32_t tim_num_entries;
11178 /* Number of entries to reserve for QP1 */
11179 uint16_t qp_num_qp1_entries;
11180 /* Number of entries to reserve for L2 */
11181 uint16_t qp_num_l2_entries;
11182 /* Number of bytes that have been allocated for each context entry. */
11183 uint16_t qp_entry_size;
11184 /* Number of entries to reserve for L2 */
11185 uint16_t srq_num_l2_entries;
11186 /* Number of bytes that have been allocated for each context entry. */
11187 uint16_t srq_entry_size;
11188 /* Number of entries to reserve for L2 */
11189 uint16_t cq_num_l2_entries;
11190 /* Number of bytes that have been allocated for each context entry. */
11191 uint16_t cq_entry_size;
11192 /* Number of entries to reserve for VNIC entries */
11193 uint16_t vnic_num_vnic_entries;
11194 /* Number of entries to reserve for Ring table entries */
11195 uint16_t vnic_num_ring_table_entries;
11196 /* Number of bytes that have been allocated for each context entry. */
11197 uint16_t vnic_entry_size;
11198 /* Number of bytes that have been allocated for each context entry. */
11199 uint16_t stat_entry_size;
11200 /* Number of bytes that have been allocated for each context entry. */
11201 uint16_t tqm_entry_size;
11202 /* Number of bytes that have been allocated for each context entry. */
11203 uint16_t mrav_entry_size;
11204 /* Number of bytes that have been allocated for each context entry. */
11205 uint16_t tim_entry_size;
11208 /* hwrm_func_backing_store_cfg_output (size:128b/16B) */
11209 struct hwrm_func_backing_store_cfg_output {
11210 /* The specific error status for the command. */
11211 uint16_t error_code;
11212 /* The HWRM command request type. */
11214 /* The sequence ID from the original command. */
11216 /* The length of the response data in number of bytes. */
11218 uint8_t unused_0[7];
11220 * This field is used in Output records to indicate that the output
11221 * is completely written to RAM. This field should be read as '1'
11222 * to indicate that the output has been completely written.
11223 * When writing a command completion or response to an internal processor,
11224 * the order of writes has to be such that this field is written last.
11229 /********************************
11230 * hwrm_func_backing_store_qcfg *
11231 ********************************/
11234 /* hwrm_func_backing_store_qcfg_input (size:128b/16B) */
11235 struct hwrm_func_backing_store_qcfg_input {
11236 /* The HWRM command request type. */
11239 * The completion ring to send the completion event on. This should
11240 * be the NQ ID returned from the `nq_alloc` HWRM command.
11242 uint16_t cmpl_ring;
11244 * The sequence ID is used by the driver for tracking multiple
11245 * commands. This ID is treated as opaque data by the firmware and
11246 * the value is returned in the `hwrm_resp_hdr` upon completion.
11250 * The target ID of the command:
11251 * * 0x0-0xFFF8 - The function ID
11252 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
11253 * * 0xFFFD - Reserved for user-space HWRM interface
11256 uint16_t target_id;
11258 * A physical address pointer pointing to a host buffer that the
11259 * command's response data will be written. This can be either a host
11260 * physical address (HPA) or a guest physical address (GPA) and must
11261 * point to a physically contiguous block of memory.
11263 uint64_t resp_addr;
11266 /* hwrm_func_backing_store_qcfg_output (size:1920b/240B) */
11267 struct hwrm_func_backing_store_qcfg_output {
11268 /* The specific error status for the command. */
11269 uint16_t error_code;
11270 /* The HWRM command request type. */
11272 /* The sequence ID from the original command. */
11274 /* The length of the response data in number of bytes. */
11278 * When set, the firmware only uses on-chip resources and does not
11279 * expect any backing store to be provided by the host driver. This
11280 * mode provides minimal L2 functionality (e.g. limited L2 resources,
11283 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_FLAGS_PREBOOT_MODE \
11286 * When set, the 32b `mrav_num_entries` field is logically divided
11287 * into two 16b fields, `mr_num_entries` and `av_num_entries`.
11289 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_FLAGS_MRAV_RESERVATION_SPLIT \
11291 uint8_t unused_0[4];
11293 * This bit must be '1' for the qp fields to be
11296 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_UNUSED_0_QP \
11299 * This bit must be '1' for the srq fields to be
11302 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_UNUSED_0_SRQ \
11305 * This bit must be '1' for the cq fields to be
11308 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_UNUSED_0_CQ \
11311 * This bit must be '1' for the vnic fields to be
11314 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_UNUSED_0_VNIC \
11317 * This bit must be '1' for the stat fields to be
11320 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_UNUSED_0_STAT \
11323 * This bit must be '1' for the tqm_sp fields to be
11326 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_UNUSED_0_TQM_SP \
11329 * This bit must be '1' for the tqm_ring0 fields to be
11332 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_UNUSED_0_TQM_RING0 \
11335 * This bit must be '1' for the tqm_ring1 fields to be
11338 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_UNUSED_0_TQM_RING1 \
11341 * This bit must be '1' for the tqm_ring2 fields to be
11344 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_UNUSED_0_TQM_RING2 \
11347 * This bit must be '1' for the tqm_ring3 fields to be
11350 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_UNUSED_0_TQM_RING3 \
11353 * This bit must be '1' for the tqm_ring4 fields to be
11356 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_UNUSED_0_TQM_RING4 \
11359 * This bit must be '1' for the tqm_ring5 fields to be
11362 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_UNUSED_0_TQM_RING5 \
11365 * This bit must be '1' for the tqm_ring6 fields to be
11368 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_UNUSED_0_TQM_RING6 \
11371 * This bit must be '1' for the tqm_ring7 fields to be
11374 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_UNUSED_0_TQM_RING7 \
11377 * This bit must be '1' for the mrav fields to be
11380 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_UNUSED_0_MRAV \
11383 * This bit must be '1' for the tim fields to be
11386 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_UNUSED_0_TIM \
11388 /* QPC page size and level. */
11389 uint8_t qpc_pg_size_qpc_lvl;
11390 /* QPC PBL indirect levels. */
11391 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_QPC_LVL_MASK \
11393 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_QPC_LVL_SFT 0
11394 /* PBL pointer is physical start address. */
11395 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_QPC_LVL_LVL_0 \
11397 /* PBL pointer points to PTE table. */
11398 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_QPC_LVL_LVL_1 \
11400 /* PBL pointer points to PDE table with each entry pointing to PTE tables. */
11401 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_QPC_LVL_LVL_2 \
11403 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_QPC_LVL_LAST \
11404 HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_QPC_LVL_LVL_2
11405 /* QPC page size. */
11406 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_QPC_PG_SIZE_MASK \
11408 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_QPC_PG_SIZE_SFT 4
11410 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_QPC_PG_SIZE_PG_4K \
11411 (UINT32_C(0x0) << 4)
11413 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_QPC_PG_SIZE_PG_8K \
11414 (UINT32_C(0x1) << 4)
11416 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_QPC_PG_SIZE_PG_64K \
11417 (UINT32_C(0x2) << 4)
11419 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_QPC_PG_SIZE_PG_2M \
11420 (UINT32_C(0x3) << 4)
11422 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_QPC_PG_SIZE_PG_8M \
11423 (UINT32_C(0x4) << 4)
11425 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_QPC_PG_SIZE_PG_1G \
11426 (UINT32_C(0x5) << 4)
11427 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_QPC_PG_SIZE_LAST \
11428 HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_QPC_PG_SIZE_PG_1G
11429 /* SRQ page size and level. */
11430 uint8_t srq_pg_size_srq_lvl;
11431 /* SRQ PBL indirect levels. */
11432 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_SRQ_LVL_MASK \
11434 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_SRQ_LVL_SFT 0
11435 /* PBL pointer is physical start address. */
11436 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_SRQ_LVL_LVL_0 \
11438 /* PBL pointer points to PTE table. */
11439 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_SRQ_LVL_LVL_1 \
11441 /* PBL pointer points to PDE table with each entry pointing to PTE tables. */
11442 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_SRQ_LVL_LVL_2 \
11444 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_SRQ_LVL_LAST \
11445 HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_SRQ_LVL_LVL_2
11446 /* SRQ page size. */
11447 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_SRQ_PG_SIZE_MASK \
11449 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_SRQ_PG_SIZE_SFT 4
11451 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_SRQ_PG_SIZE_PG_4K \
11452 (UINT32_C(0x0) << 4)
11454 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_SRQ_PG_SIZE_PG_8K \
11455 (UINT32_C(0x1) << 4)
11457 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_SRQ_PG_SIZE_PG_64K \
11458 (UINT32_C(0x2) << 4)
11460 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_SRQ_PG_SIZE_PG_2M \
11461 (UINT32_C(0x3) << 4)
11463 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_SRQ_PG_SIZE_PG_8M \
11464 (UINT32_C(0x4) << 4)
11466 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_SRQ_PG_SIZE_PG_1G \
11467 (UINT32_C(0x5) << 4)
11468 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_SRQ_PG_SIZE_LAST \
11469 HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_SRQ_PG_SIZE_PG_1G
11470 /* CQ page size and level. */
11471 uint8_t cq_pg_size_cq_lvl;
11472 /* CQ PBL indirect levels. */
11473 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_CQ_LVL_MASK \
11475 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_CQ_LVL_SFT 0
11476 /* PBL pointer is physical start address. */
11477 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_CQ_LVL_LVL_0 \
11479 /* PBL pointer points to PTE table. */
11480 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_CQ_LVL_LVL_1 \
11482 /* PBL pointer points to PDE table with each entry pointing to PTE tables. */
11483 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_CQ_LVL_LVL_2 \
11485 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_CQ_LVL_LAST \
11486 HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_CQ_LVL_LVL_2
11487 /* CQ page size. */
11488 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_CQ_PG_SIZE_MASK \
11490 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_CQ_PG_SIZE_SFT 4
11492 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_CQ_PG_SIZE_PG_4K \
11493 (UINT32_C(0x0) << 4)
11495 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_CQ_PG_SIZE_PG_8K \
11496 (UINT32_C(0x1) << 4)
11498 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_CQ_PG_SIZE_PG_64K \
11499 (UINT32_C(0x2) << 4)
11501 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_CQ_PG_SIZE_PG_2M \
11502 (UINT32_C(0x3) << 4)
11504 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_CQ_PG_SIZE_PG_8M \
11505 (UINT32_C(0x4) << 4)
11507 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_CQ_PG_SIZE_PG_1G \
11508 (UINT32_C(0x5) << 4)
11509 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_CQ_PG_SIZE_LAST \
11510 HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_CQ_PG_SIZE_PG_1G
11511 /* VNIC page size and level. */
11512 uint8_t vnic_pg_size_vnic_lvl;
11513 /* VNIC PBL indirect levels. */
11514 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_VNIC_LVL_MASK \
11516 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_VNIC_LVL_SFT 0
11517 /* PBL pointer is physical start address. */
11518 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_VNIC_LVL_LVL_0 \
11520 /* PBL pointer points to PTE table. */
11521 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_VNIC_LVL_LVL_1 \
11523 /* PBL pointer points to PDE table with each entry pointing to PTE tables. */
11524 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_VNIC_LVL_LVL_2 \
11526 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_VNIC_LVL_LAST \
11527 HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_VNIC_LVL_LVL_2
11528 /* VNIC page size. */
11529 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_VNIC_PG_SIZE_MASK \
11531 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_VNIC_PG_SIZE_SFT 4
11533 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_VNIC_PG_SIZE_PG_4K \
11534 (UINT32_C(0x0) << 4)
11536 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_VNIC_PG_SIZE_PG_8K \
11537 (UINT32_C(0x1) << 4)
11539 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_VNIC_PG_SIZE_PG_64K \
11540 (UINT32_C(0x2) << 4)
11542 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_VNIC_PG_SIZE_PG_2M \
11543 (UINT32_C(0x3) << 4)
11545 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_VNIC_PG_SIZE_PG_8M \
11546 (UINT32_C(0x4) << 4)
11548 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_VNIC_PG_SIZE_PG_1G \
11549 (UINT32_C(0x5) << 4)
11550 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_VNIC_PG_SIZE_LAST \
11551 HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_VNIC_PG_SIZE_PG_1G
11552 /* Stat page size and level. */
11553 uint8_t stat_pg_size_stat_lvl;
11554 /* Stat PBL indirect levels. */
11555 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_STAT_LVL_MASK \
11557 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_STAT_LVL_SFT 0
11558 /* PBL pointer is physical start address. */
11559 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_STAT_LVL_LVL_0 \
11561 /* PBL pointer points to PTE table. */
11562 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_STAT_LVL_LVL_1 \
11564 /* PBL pointer points to PDE table with each entry pointing to PTE tables. */
11565 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_STAT_LVL_LVL_2 \
11567 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_STAT_LVL_LAST \
11568 HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_STAT_LVL_LVL_2
11569 /* Stat page size. */
11570 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_STAT_PG_SIZE_MASK \
11572 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_STAT_PG_SIZE_SFT 4
11574 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_STAT_PG_SIZE_PG_4K \
11575 (UINT32_C(0x0) << 4)
11577 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_STAT_PG_SIZE_PG_8K \
11578 (UINT32_C(0x1) << 4)
11580 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_STAT_PG_SIZE_PG_64K \
11581 (UINT32_C(0x2) << 4)
11583 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_STAT_PG_SIZE_PG_2M \
11584 (UINT32_C(0x3) << 4)
11586 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_STAT_PG_SIZE_PG_8M \
11587 (UINT32_C(0x4) << 4)
11589 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_STAT_PG_SIZE_PG_1G \
11590 (UINT32_C(0x5) << 4)
11591 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_STAT_PG_SIZE_LAST \
11592 HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_STAT_PG_SIZE_PG_1G
11593 /* TQM slow path page size and level. */
11594 uint8_t tqm_sp_pg_size_tqm_sp_lvl;
11595 /* TQM slow path PBL indirect levels. */
11596 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_SP_LVL_MASK \
11598 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_SP_LVL_SFT 0
11599 /* PBL pointer is physical start address. */
11600 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_SP_LVL_LVL_0 \
11602 /* PBL pointer points to PTE table. */
11603 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_SP_LVL_LVL_1 \
11605 /* PBL pointer points to PDE table with each entry pointing to PTE tables. */
11606 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_SP_LVL_LVL_2 \
11608 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_SP_LVL_LAST \
11609 HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_SP_LVL_LVL_2
11610 /* TQM slow path page size. */
11611 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_SP_PG_SIZE_MASK \
11613 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_SP_PG_SIZE_SFT 4
11615 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_SP_PG_SIZE_PG_4K \
11616 (UINT32_C(0x0) << 4)
11618 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_SP_PG_SIZE_PG_8K \
11619 (UINT32_C(0x1) << 4)
11621 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_SP_PG_SIZE_PG_64K \
11622 (UINT32_C(0x2) << 4)
11624 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_SP_PG_SIZE_PG_2M \
11625 (UINT32_C(0x3) << 4)
11627 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_SP_PG_SIZE_PG_8M \
11628 (UINT32_C(0x4) << 4)
11630 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_SP_PG_SIZE_PG_1G \
11631 (UINT32_C(0x5) << 4)
11632 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_SP_PG_SIZE_LAST \
11633 HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_SP_PG_SIZE_PG_1G
11634 /* TQM ring 0 page size and level. */
11635 uint8_t tqm_ring0_pg_size_tqm_ring0_lvl;
11636 /* TQM ring 0 PBL indirect levels. */
11637 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING0_LVL_MASK \
11639 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING0_LVL_SFT 0
11640 /* PBL pointer is physical start address. */
11641 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING0_LVL_LVL_0 \
11643 /* PBL pointer points to PTE table. */
11644 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING0_LVL_LVL_1 \
11646 /* PBL pointer points to PDE table with each entry pointing to PTE tables. */
11647 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING0_LVL_LVL_2 \
11649 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING0_LVL_LAST \
11650 HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING0_LVL_LVL_2
11651 /* TQM ring 0 page size. */
11652 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING0_PG_SIZE_MASK \
11654 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING0_PG_SIZE_SFT 4
11656 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING0_PG_SIZE_PG_4K \
11657 (UINT32_C(0x0) << 4)
11659 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING0_PG_SIZE_PG_8K \
11660 (UINT32_C(0x1) << 4)
11662 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING0_PG_SIZE_PG_64K \
11663 (UINT32_C(0x2) << 4)
11665 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING0_PG_SIZE_PG_2M \
11666 (UINT32_C(0x3) << 4)
11668 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING0_PG_SIZE_PG_8M \
11669 (UINT32_C(0x4) << 4)
11671 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING0_PG_SIZE_PG_1G \
11672 (UINT32_C(0x5) << 4)
11673 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING0_PG_SIZE_LAST \
11674 HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING0_PG_SIZE_PG_1G
11675 /* TQM ring 1 page size and level. */
11676 uint8_t tqm_ring1_pg_size_tqm_ring1_lvl;
11677 /* TQM ring 1 PBL indirect levels. */
11678 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING1_LVL_MASK \
11680 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING1_LVL_SFT 0
11681 /* PBL pointer is physical start address. */
11682 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING1_LVL_LVL_0 \
11684 /* PBL pointer points to PTE table. */
11685 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING1_LVL_LVL_1 \
11687 /* PBL pointer points to PDE table with each entry pointing to PTE tables. */
11688 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING1_LVL_LVL_2 \
11690 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING1_LVL_LAST \
11691 HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING1_LVL_LVL_2
11692 /* TQM ring 1 page size. */
11693 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING1_PG_SIZE_MASK \
11695 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING1_PG_SIZE_SFT 4
11697 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING1_PG_SIZE_PG_4K \
11698 (UINT32_C(0x0) << 4)
11700 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING1_PG_SIZE_PG_8K \
11701 (UINT32_C(0x1) << 4)
11703 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING1_PG_SIZE_PG_64K \
11704 (UINT32_C(0x2) << 4)
11706 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING1_PG_SIZE_PG_2M \
11707 (UINT32_C(0x3) << 4)
11709 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING1_PG_SIZE_PG_8M \
11710 (UINT32_C(0x4) << 4)
11712 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING1_PG_SIZE_PG_1G \
11713 (UINT32_C(0x5) << 4)
11714 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING1_PG_SIZE_LAST \
11715 HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING1_PG_SIZE_PG_1G
11716 /* TQM ring 2 page size and level. */
11717 uint8_t tqm_ring2_pg_size_tqm_ring2_lvl;
11718 /* TQM ring 2 PBL indirect levels. */
11719 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING2_LVL_MASK \
11721 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING2_LVL_SFT 0
11722 /* PBL pointer is physical start address. */
11723 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING2_LVL_LVL_0 \
11725 /* PBL pointer points to PTE table. */
11726 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING2_LVL_LVL_1 \
11728 /* PBL pointer points to PDE table with each entry pointing to PTE tables. */
11729 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING2_LVL_LVL_2 \
11731 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING2_LVL_LAST \
11732 HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING2_LVL_LVL_2
11733 /* TQM ring 2 page size. */
11734 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING2_PG_SIZE_MASK \
11736 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING2_PG_SIZE_SFT 4
11738 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING2_PG_SIZE_PG_4K \
11739 (UINT32_C(0x0) << 4)
11741 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING2_PG_SIZE_PG_8K \
11742 (UINT32_C(0x1) << 4)
11744 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING2_PG_SIZE_PG_64K \
11745 (UINT32_C(0x2) << 4)
11747 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING2_PG_SIZE_PG_2M \
11748 (UINT32_C(0x3) << 4)
11750 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING2_PG_SIZE_PG_8M \
11751 (UINT32_C(0x4) << 4)
11753 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING2_PG_SIZE_PG_1G \
11754 (UINT32_C(0x5) << 4)
11755 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING2_PG_SIZE_LAST \
11756 HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING2_PG_SIZE_PG_1G
11757 /* TQM ring 3 page size and level. */
11758 uint8_t tqm_ring3_pg_size_tqm_ring3_lvl;
11759 /* TQM ring 3 PBL indirect levels. */
11760 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING3_LVL_MASK \
11762 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING3_LVL_SFT 0
11763 /* PBL pointer is physical start address. */
11764 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING3_LVL_LVL_0 \
11766 /* PBL pointer points to PTE table. */
11767 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING3_LVL_LVL_1 \
11769 /* PBL pointer points to PDE table with each entry pointing to PTE tables. */
11770 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING3_LVL_LVL_2 \
11772 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING3_LVL_LAST \
11773 HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING3_LVL_LVL_2
11774 /* TQM ring 3 page size. */
11775 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING3_PG_SIZE_MASK \
11777 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING3_PG_SIZE_SFT 4
11779 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING3_PG_SIZE_PG_4K \
11780 (UINT32_C(0x0) << 4)
11782 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING3_PG_SIZE_PG_8K \
11783 (UINT32_C(0x1) << 4)
11785 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING3_PG_SIZE_PG_64K \
11786 (UINT32_C(0x2) << 4)
11788 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING3_PG_SIZE_PG_2M \
11789 (UINT32_C(0x3) << 4)
11791 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING3_PG_SIZE_PG_8M \
11792 (UINT32_C(0x4) << 4)
11794 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING3_PG_SIZE_PG_1G \
11795 (UINT32_C(0x5) << 4)
11796 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING3_PG_SIZE_LAST \
11797 HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING3_PG_SIZE_PG_1G
11798 /* TQM ring 4 page size and level. */
11799 uint8_t tqm_ring4_pg_size_tqm_ring4_lvl;
11800 /* TQM ring 4 PBL indirect levels. */
11801 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING4_LVL_MASK \
11803 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING4_LVL_SFT 0
11804 /* PBL pointer is physical start address. */
11805 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING4_LVL_LVL_0 \
11807 /* PBL pointer points to PTE table. */
11808 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING4_LVL_LVL_1 \
11810 /* PBL pointer points to PDE table with each entry pointing to PTE tables. */
11811 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING4_LVL_LVL_2 \
11813 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING4_LVL_LAST \
11814 HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING4_LVL_LVL_2
11815 /* TQM ring 4 page size. */
11816 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING4_PG_SIZE_MASK \
11818 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING4_PG_SIZE_SFT 4
11820 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING4_PG_SIZE_PG_4K \
11821 (UINT32_C(0x0) << 4)
11823 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING4_PG_SIZE_PG_8K \
11824 (UINT32_C(0x1) << 4)
11826 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING4_PG_SIZE_PG_64K \
11827 (UINT32_C(0x2) << 4)
11829 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING4_PG_SIZE_PG_2M \
11830 (UINT32_C(0x3) << 4)
11832 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING4_PG_SIZE_PG_8M \
11833 (UINT32_C(0x4) << 4)
11835 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING4_PG_SIZE_PG_1G \
11836 (UINT32_C(0x5) << 4)
11837 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING4_PG_SIZE_LAST \
11838 HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING4_PG_SIZE_PG_1G
11839 /* TQM ring 5 page size and level. */
11840 uint8_t tqm_ring5_pg_size_tqm_ring5_lvl;
11841 /* TQM ring 5 PBL indirect levels. */
11842 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING5_LVL_MASK \
11844 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING5_LVL_SFT 0
11845 /* PBL pointer is physical start address. */
11846 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING5_LVL_LVL_0 \
11848 /* PBL pointer points to PTE table. */
11849 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING5_LVL_LVL_1 \
11851 /* PBL pointer points to PDE table with each entry pointing to PTE tables. */
11852 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING5_LVL_LVL_2 \
11854 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING5_LVL_LAST \
11855 HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING5_LVL_LVL_2
11856 /* TQM ring 5 page size. */
11857 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING5_PG_SIZE_MASK \
11859 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING5_PG_SIZE_SFT 4
11861 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING5_PG_SIZE_PG_4K \
11862 (UINT32_C(0x0) << 4)
11864 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING5_PG_SIZE_PG_8K \
11865 (UINT32_C(0x1) << 4)
11867 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING5_PG_SIZE_PG_64K \
11868 (UINT32_C(0x2) << 4)
11870 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING5_PG_SIZE_PG_2M \
11871 (UINT32_C(0x3) << 4)
11873 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING5_PG_SIZE_PG_8M \
11874 (UINT32_C(0x4) << 4)
11876 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING5_PG_SIZE_PG_1G \
11877 (UINT32_C(0x5) << 4)
11878 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING5_PG_SIZE_LAST \
11879 HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING5_PG_SIZE_PG_1G
11880 /* TQM ring 6 page size and level. */
11881 uint8_t tqm_ring6_pg_size_tqm_ring6_lvl;
11882 /* TQM ring 6 PBL indirect levels. */
11883 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING6_LVL_MASK \
11885 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING6_LVL_SFT 0
11886 /* PBL pointer is physical start address. */
11887 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING6_LVL_LVL_0 \
11889 /* PBL pointer points to PTE table. */
11890 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING6_LVL_LVL_1 \
11892 /* PBL pointer points to PDE table with each entry pointing to PTE tables. */
11893 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING6_LVL_LVL_2 \
11895 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING6_LVL_LAST \
11896 HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING6_LVL_LVL_2
11897 /* TQM ring 6 page size. */
11898 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING6_PG_SIZE_MASK \
11900 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING6_PG_SIZE_SFT 4
11902 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING6_PG_SIZE_PG_4K \
11903 (UINT32_C(0x0) << 4)
11905 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING6_PG_SIZE_PG_8K \
11906 (UINT32_C(0x1) << 4)
11908 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING6_PG_SIZE_PG_64K \
11909 (UINT32_C(0x2) << 4)
11911 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING6_PG_SIZE_PG_2M \
11912 (UINT32_C(0x3) << 4)
11914 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING6_PG_SIZE_PG_8M \
11915 (UINT32_C(0x4) << 4)
11917 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING6_PG_SIZE_PG_1G \
11918 (UINT32_C(0x5) << 4)
11919 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING6_PG_SIZE_LAST \
11920 HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING6_PG_SIZE_PG_1G
11921 /* TQM ring 7 page size and level. */
11922 uint8_t tqm_ring7_pg_size_tqm_ring7_lvl;
11923 /* TQM ring 7 PBL indirect levels. */
11924 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING7_LVL_MASK \
11926 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING7_LVL_SFT 0
11927 /* PBL pointer is physical start address. */
11928 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING7_LVL_LVL_0 \
11930 /* PBL pointer points to PTE table. */
11931 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING7_LVL_LVL_1 \
11933 /* PBL pointer points to PDE table with each entry pointing to PTE tables. */
11934 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING7_LVL_LVL_2 \
11936 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING7_LVL_LAST \
11937 HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING7_LVL_LVL_2
11938 /* TQM ring 7 page size. */
11939 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING7_PG_SIZE_MASK \
11941 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING7_PG_SIZE_SFT 4
11943 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING7_PG_SIZE_PG_4K \
11944 (UINT32_C(0x0) << 4)
11946 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING7_PG_SIZE_PG_8K \
11947 (UINT32_C(0x1) << 4)
11949 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING7_PG_SIZE_PG_64K \
11950 (UINT32_C(0x2) << 4)
11952 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING7_PG_SIZE_PG_2M \
11953 (UINT32_C(0x3) << 4)
11955 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING7_PG_SIZE_PG_8M \
11956 (UINT32_C(0x4) << 4)
11958 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING7_PG_SIZE_PG_1G \
11959 (UINT32_C(0x5) << 4)
11960 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING7_PG_SIZE_LAST \
11961 HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING7_PG_SIZE_PG_1G
11962 /* MR/AV page size and level. */
11963 uint8_t mrav_pg_size_mrav_lvl;
11964 /* MR/AV PBL indirect levels. */
11965 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_MRAV_LVL_MASK \
11967 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_MRAV_LVL_SFT 0
11968 /* PBL pointer is physical start address. */
11969 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_MRAV_LVL_LVL_0 \
11971 /* PBL pointer points to PTE table. */
11972 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_MRAV_LVL_LVL_1 \
11974 /* PBL pointer points to PDE table with each entry pointing to PTE tables. */
11975 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_MRAV_LVL_LVL_2 \
11977 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_MRAV_LVL_LAST \
11978 HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_MRAV_LVL_LVL_2
11979 /* MR/AV page size. */
11980 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_MRAV_PG_SIZE_MASK \
11982 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_MRAV_PG_SIZE_SFT 4
11984 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_MRAV_PG_SIZE_PG_4K \
11985 (UINT32_C(0x0) << 4)
11987 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_MRAV_PG_SIZE_PG_8K \
11988 (UINT32_C(0x1) << 4)
11990 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_MRAV_PG_SIZE_PG_64K \
11991 (UINT32_C(0x2) << 4)
11993 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_MRAV_PG_SIZE_PG_2M \
11994 (UINT32_C(0x3) << 4)
11996 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_MRAV_PG_SIZE_PG_8M \
11997 (UINT32_C(0x4) << 4)
11999 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_MRAV_PG_SIZE_PG_1G \
12000 (UINT32_C(0x5) << 4)
12001 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_MRAV_PG_SIZE_LAST \
12002 HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_MRAV_PG_SIZE_PG_1G
12003 /* Timer page size and level. */
12004 uint8_t tim_pg_size_tim_lvl;
12005 /* Timer PBL indirect levels. */
12006 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TIM_LVL_MASK \
12008 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TIM_LVL_SFT 0
12009 /* PBL pointer is physical start address. */
12010 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TIM_LVL_LVL_0 \
12012 /* PBL pointer points to PTE table. */
12013 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TIM_LVL_LVL_1 \
12015 /* PBL pointer points to PDE table with each entry pointing to PTE tables. */
12016 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TIM_LVL_LVL_2 \
12018 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TIM_LVL_LAST \
12019 HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TIM_LVL_LVL_2
12020 /* Timer page size. */
12021 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TIM_PG_SIZE_MASK \
12023 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TIM_PG_SIZE_SFT 4
12025 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TIM_PG_SIZE_PG_4K \
12026 (UINT32_C(0x0) << 4)
12028 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TIM_PG_SIZE_PG_8K \
12029 (UINT32_C(0x1) << 4)
12031 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TIM_PG_SIZE_PG_64K \
12032 (UINT32_C(0x2) << 4)
12034 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TIM_PG_SIZE_PG_2M \
12035 (UINT32_C(0x3) << 4)
12037 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TIM_PG_SIZE_PG_8M \
12038 (UINT32_C(0x4) << 4)
12040 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TIM_PG_SIZE_PG_1G \
12041 (UINT32_C(0x5) << 4)
12042 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TIM_PG_SIZE_LAST \
12043 HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TIM_PG_SIZE_PG_1G
12044 /* QP page directory. */
12045 uint64_t qpc_page_dir;
12046 /* SRQ page directory. */
12047 uint64_t srq_page_dir;
12048 /* CQ page directory. */
12049 uint64_t cq_page_dir;
12050 /* VNIC page directory. */
12051 uint64_t vnic_page_dir;
12052 /* Stat page directory. */
12053 uint64_t stat_page_dir;
12054 /* TQM slowpath page directory. */
12055 uint64_t tqm_sp_page_dir;
12056 /* TQM ring 0 page directory. */
12057 uint64_t tqm_ring0_page_dir;
12058 /* TQM ring 1 page directory. */
12059 uint64_t tqm_ring1_page_dir;
12060 /* TQM ring 2 page directory. */
12061 uint64_t tqm_ring2_page_dir;
12062 /* TQM ring 3 page directory. */
12063 uint64_t tqm_ring3_page_dir;
12064 /* TQM ring 4 page directory. */
12065 uint64_t tqm_ring4_page_dir;
12066 /* TQM ring 5 page directory. */
12067 uint64_t tqm_ring5_page_dir;
12068 /* TQM ring 6 page directory. */
12069 uint64_t tqm_ring6_page_dir;
12070 /* TQM ring 7 page directory. */
12071 uint64_t tqm_ring7_page_dir;
12072 /* MR/AV page directory. */
12073 uint64_t mrav_page_dir;
12074 /* Timer page directory. */
12075 uint64_t tim_page_dir;
12076 /* Number of entries to reserve for QP1 */
12077 uint16_t qp_num_qp1_entries;
12078 /* Number of entries to reserve for L2 */
12079 uint16_t qp_num_l2_entries;
12080 /* Number of QPs. */
12081 uint32_t qp_num_entries;
12082 /* Number of SRQs. */
12083 uint32_t srq_num_entries;
12084 /* Number of entries to reserve for L2 */
12085 uint16_t srq_num_l2_entries;
12086 /* Number of entries to reserve for L2 */
12087 uint16_t cq_num_l2_entries;
12088 /* Number of CQs. */
12089 uint32_t cq_num_entries;
12090 /* Number of entries to reserve for VNIC entries */
12091 uint16_t vnic_num_vnic_entries;
12092 /* Number of entries to reserve for Ring table entries */
12093 uint16_t vnic_num_ring_table_entries;
12094 /* Number of Stats. */
12095 uint32_t stat_num_entries;
12096 /* Number of TQM slowpath entries. */
12097 uint32_t tqm_sp_num_entries;
12098 /* Number of TQM ring 0 entries. */
12099 uint32_t tqm_ring0_num_entries;
12100 /* Number of TQM ring 1 entries. */
12101 uint32_t tqm_ring1_num_entries;
12102 /* Number of TQM ring 2 entries. */
12103 uint32_t tqm_ring2_num_entries;
12104 /* Number of TQM ring 3 entries. */
12105 uint32_t tqm_ring3_num_entries;
12106 /* Number of TQM ring 4 entries. */
12107 uint32_t tqm_ring4_num_entries;
12108 /* Number of TQM ring 5 entries. */
12109 uint32_t tqm_ring5_num_entries;
12110 /* Number of TQM ring 6 entries. */
12111 uint32_t tqm_ring6_num_entries;
12112 /* Number of TQM ring 7 entries. */
12113 uint32_t tqm_ring7_num_entries;
12115 * If the MR/AV split reservation flag is not set, then this field
12116 * represents the total number of MR plus AV entries. For versions
12117 * of firmware that support the split reservation, when it is not
12118 * specified half of the entries will be reserved for MRs and the
12119 * other half for AVs.
12121 * If the MR/AV split reservation flag is set, then this
12122 * field is logically divided into two 16b fields. Bits `[31:16]`
12123 * represents the `mr_num_entries` and bits `[15:0]` represents
12124 * `av_num_entries`. The granularity of these values is defined by
12125 * the `mrav_num_entries_unit` field returned by the
12126 * `backing_store_qcaps` command.
12128 uint32_t mrav_num_entries;
12129 /* Number of Timer entries. */
12130 uint32_t tim_num_entries;
12131 uint8_t unused_1[7];
12133 * This field is used in Output records to indicate that the output
12134 * is completely written to RAM. This field should be read as 1
12135 * to indicate that the output has been completely written.
12136 * When writing a command completion or response to an internal
12137 * processor, the order of writes has to be such that this field
12143 /****************************
12144 * hwrm_error_recovery_qcfg *
12145 ****************************/
12148 /* hwrm_error_recovery_qcfg_input (size:192b/24B) */
12149 struct hwrm_error_recovery_qcfg_input {
12150 /* The HWRM command request type. */
12153 * The completion ring to send the completion event on. This should
12154 * be the NQ ID returned from the `nq_alloc` HWRM command.
12156 uint16_t cmpl_ring;
12158 * The sequence ID is used by the driver for tracking multiple
12159 * commands. This ID is treated as opaque data by the firmware and
12160 * the value is returned in the `hwrm_resp_hdr` upon completion.
12164 * The target ID of the command:
12165 * * 0x0-0xFFF8 - The function ID
12166 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
12167 * * 0xFFFD - Reserved for user-space HWRM interface
12170 uint16_t target_id;
12172 * A physical address pointer pointing to a host buffer that the
12173 * command's response data will be written. This can be either a host
12174 * physical address (HPA) or a guest physical address (GPA) and must
12175 * point to a physically contiguous block of memory.
12177 uint64_t resp_addr;
12178 uint8_t unused_0[8];
12181 /* hwrm_error_recovery_qcfg_output (size:1664b/208B) */
12182 struct hwrm_error_recovery_qcfg_output {
12183 /* The specific error status for the command. */
12184 uint16_t error_code;
12185 /* The HWRM command request type. */
12187 /* The sequence ID from the original command. */
12189 /* The length of the response data in number of bytes. */
12193 * When this flag is set to 1, error recovery will be initiated
12194 * through master function driver.
12196 #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FLAGS_HOST UINT32_C(0x1)
12198 * When this flag is set to 1, error recovery will be performed
12199 * through Co processor.
12201 #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FLAGS_CO_CPU UINT32_C(0x2)
12203 * Driver Polling frequency. This value is in units of 100msec.
12204 * Typical value would be 10 to indicate 1sec.
12205 * Drivers can poll FW health status, Heartbeat, reset_counter with
12208 uint32_t driver_polling_freq;
12210 * This value is in units of 100msec.
12211 * Typical value would be 30 to indicate 3sec.
12212 * Master function wait period from detecting a fatal error to
12213 * initiating reset. In this time period Master PF expects every
12214 * active driver will detect fatal error.
12216 uint32_t master_func_wait_period;
12218 * This value is in units of 100msec.
12219 * Typical value would be 50 to indicate 5sec.
12220 * Normal function wait period from fatal error detection to
12221 * polling FW health status. In this time period, drivers should not
12222 * do any PCIe MMIO transaction and should not send any HWRM commands.
12224 uint32_t normal_func_wait_period;
12226 * This value is in units of 100msec.
12227 * Typical value would be 20 to indicate 2sec.
12228 * This field indicates that, master function wait period after chip
12229 * reset. After this time, master function should reinitialize with
12232 uint32_t master_func_wait_period_after_reset;
12234 * This value is in units of 100msec.
12235 * Typical value would be 60 to indicate 6sec.
12236 * This field is applicable to both master and normal functions.
12237 * Even after chip reset, if FW status not changed to ready,
12238 * then all the functions can poll for this much time and bailout.
12240 uint32_t max_bailout_time_after_reset;
12242 * FW health status register.
12243 * Lower 2 bits indicates address space location and upper 30 bits
12244 * indicates upper 30bits of the register address.
12245 * A value of 0xFFFF-FFFF indicates this register does not exist.
12247 uint32_t fw_health_status_reg;
12248 /* Lower 2 bits indicates address space location. */
12249 #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FW_HEALTH_STATUS_REG_ADDR_SPACE_MASK \
12251 #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FW_HEALTH_STATUS_REG_ADDR_SPACE_SFT \
12254 * If value is 0, this register is located in PCIe config space.
12255 * Drivers have to map appropriate window to access this
12258 #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FW_HEALTH_STATUS_REG_ADDR_SPACE_PCIE_CFG \
12261 * If value is 1, this register is located in GRC address space.
12262 * Drivers have to map appropriate window to access this
12265 #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FW_HEALTH_STATUS_REG_ADDR_SPACE_GRC \
12268 * If value is 2, this register is located in first BAR address
12269 * space. Drivers have to map appropriate window to access this
12272 #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FW_HEALTH_STATUS_REG_ADDR_SPACE_BAR0 \
12275 * If value is 3, this register is located in second BAR address
12276 * space. Drivers have to map appropriate window to access this
12277 * Drivers have to map appropriate window to access this
12280 #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FW_HEALTH_STATUS_REG_ADDR_SPACE_BAR1 \
12282 #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FW_HEALTH_STATUS_REG_ADDR_SPACE_LAST \
12283 HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FW_HEALTH_STATUS_REG_ADDR_SPACE_BAR1
12284 /* Upper 30bits of the register address. */
12285 #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FW_HEALTH_STATUS_REG_ADDR_MASK \
12286 UINT32_C(0xfffffffc)
12287 #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FW_HEALTH_STATUS_REG_ADDR_SFT \
12290 * FW HeartBeat register.
12291 * Lower 2 bits indicates address space location and upper 30 bits
12292 * indicates actual address.
12293 * A value of 0xFFFF-FFFF indicates this register does not exist.
12295 uint32_t fw_heartbeat_reg;
12296 /* Lower 2 bits indicates address space location. */
12297 #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FW_HEARTBEAT_REG_ADDR_SPACE_MASK \
12299 #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FW_HEARTBEAT_REG_ADDR_SPACE_SFT \
12302 * If value is 0, this register is located in PCIe config space.
12303 * Drivers have to map appropriate window to access this
12306 #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FW_HEARTBEAT_REG_ADDR_SPACE_PCIE_CFG \
12309 * If value is 1, this register is located in GRC address space.
12310 * Drivers have to map appropriate window to access this
12313 #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FW_HEARTBEAT_REG_ADDR_SPACE_GRC \
12316 * If value is 2, this register is located in first BAR address
12317 * space. Drivers have to map appropriate window to access this
12320 #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FW_HEARTBEAT_REG_ADDR_SPACE_BAR0 \
12323 * If value is 3, this register is located in second BAR address
12324 * space. Drivers have to map appropriate window to access this
12327 #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FW_HEARTBEAT_REG_ADDR_SPACE_BAR1 \
12329 #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FW_HEARTBEAT_REG_ADDR_SPACE_LAST \
12330 HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FW_HEARTBEAT_REG_ADDR_SPACE_BAR1
12331 /* Upper 30bits of the register address. */
12332 #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FW_HEARTBEAT_REG_ADDR_MASK \
12333 UINT32_C(0xfffffffc)
12334 #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FW_HEARTBEAT_REG_ADDR_SFT \
12337 * FW reset counter.
12338 * Lower 2 bits indicates address space location and upper 30 bits
12339 * indicates actual address.
12340 * A value of 0xFFFF-FFFF indicates this register does not exist.
12342 uint32_t fw_reset_cnt_reg;
12343 /* Lower 2 bits indicates address space location. */
12344 #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FW_RESET_CNT_REG_ADDR_SPACE_MASK \
12346 #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FW_RESET_CNT_REG_ADDR_SPACE_SFT \
12349 * If value is 0, this register is located in PCIe config space.
12350 * Drivers have to map appropriate window to access this
12353 #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FW_RESET_CNT_REG_ADDR_SPACE_PCIE_CFG \
12356 * If value is 1, this register is located in GRC address space.
12357 * Drivers have to map appropriate window to access this
12360 #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FW_RESET_CNT_REG_ADDR_SPACE_GRC \
12363 * If value is 2, this register is located in first BAR address
12364 * space. Drivers have to map appropriate window to access this
12367 #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FW_RESET_CNT_REG_ADDR_SPACE_BAR0 \
12370 * If value is 3, this register is located in second BAR address
12371 * space. Drivers have to map appropriate window to access this
12374 #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FW_RESET_CNT_REG_ADDR_SPACE_BAR1 \
12376 #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FW_RESET_CNT_REG_ADDR_SPACE_LAST \
12377 HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FW_RESET_CNT_REG_ADDR_SPACE_BAR1
12378 /* Upper 30bits of the register address. */
12379 #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FW_RESET_CNT_REG_ADDR_MASK \
12380 UINT32_C(0xfffffffc)
12381 #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FW_RESET_CNT_REG_ADDR_SFT \
12384 * Reset Inprogress Register address for PFs.
12385 * Lower 2 bits indicates address space location and upper 30 bits
12386 * indicates actual address.
12387 * A value of 0xFFFF-FFFF indicates this register does not exist.
12389 uint32_t reset_inprogress_reg;
12390 /* Lower 2 bits indicates address space location. */
12391 #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_RESET_INPROGRESS_REG_ADDR_SPACE_MASK \
12393 #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_RESET_INPROGRESS_REG_ADDR_SPACE_SFT \
12396 * If value is 0, this register is located in PCIe config space.
12397 * Drivers have to map appropriate window to access this
12400 #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_RESET_INPROGRESS_REG_ADDR_SPACE_PCIE_CFG \
12403 * If value is 1, this register is located in GRC address space.
12404 * Drivers have to map appropriate window to access this
12407 #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_RESET_INPROGRESS_REG_ADDR_SPACE_GRC \
12410 * If value is 2, this register is located in first BAR address
12411 * space. Drivers have to map appropriate window to access this
12414 #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_RESET_INPROGRESS_REG_ADDR_SPACE_BAR0 \
12417 * If value is 3, this register is located in second BAR address
12418 * space. Drivers have to map appropriate window to access this
12421 #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_RESET_INPROGRESS_REG_ADDR_SPACE_BAR1 \
12423 #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_RESET_INPROGRESS_REG_ADDR_SPACE_LAST \
12424 HWRM_ERROR_RECOVERY_QCFG_OUTPUT_RESET_INPROGRESS_REG_ADDR_SPACE_BAR1
12425 /* Upper 30bits of the register address. */
12426 #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_RESET_INPROGRESS_REG_ADDR_MASK \
12427 UINT32_C(0xfffffffc)
12428 #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_RESET_INPROGRESS_REG_ADDR_SFT \
12430 /* This field indicates the mask value for reset_inprogress_reg. */
12431 uint32_t reset_inprogress_reg_mask;
12432 uint8_t unused_0[3];
12434 * Array of registers and value count to reset the Chip
12435 * Each array count has reset_reg, reset_reg_val, delay_after_reset
12436 * in TLV format. Depending upon Chip type, number of reset registers
12437 * will vary. Drivers have to write reset_reg_val in the reset_reg
12438 * location in the same sequence in order to recover from a fatal
12441 uint8_t reg_array_cnt;
12444 * Lower 2 bits indicates address space location and upper 30 bits
12445 * indicates actual address.
12446 * A value of 0xFFFF-FFFF indicates this register does not exist.
12448 uint32_t reset_reg[16];
12449 /* Lower 2 bits indicates address space location. */
12450 #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_RESET_REG_ADDR_SPACE_MASK \
12452 #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_RESET_REG_ADDR_SPACE_SFT 0
12454 * If value is 0, this register is located in PCIe config space.
12455 * Drivers have to map appropriate window to access this
12458 #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_RESET_REG_ADDR_SPACE_PCIE_CFG \
12461 * If value is 1, this register is located in GRC address space.
12462 * Drivers have to map appropriate window to access this
12465 #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_RESET_REG_ADDR_SPACE_GRC \
12468 * If value is 2, this register is located in first BAR address
12469 * space. Drivers have to map appropriate window to access this
12472 #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_RESET_REG_ADDR_SPACE_BAR0 \
12475 * If value is 3, this register is located in second BAR address
12476 * space. Drivers have to map appropriate window to access this
12479 #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_RESET_REG_ADDR_SPACE_BAR1 \
12481 #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_RESET_REG_ADDR_SPACE_LAST \
12482 HWRM_ERROR_RECOVERY_QCFG_OUTPUT_RESET_REG_ADDR_SPACE_BAR1
12483 /* Upper 30bits of the register address. */
12484 #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_RESET_REG_ADDR_MASK \
12485 UINT32_C(0xfffffffc)
12486 #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_RESET_REG_ADDR_SFT 2
12487 /* Value to be written in reset_reg to reset the controller. */
12488 uint32_t reset_reg_val[16];
12490 * This value is in units of 1msec.
12491 * Typical value would be 10 to indicate 10msec.
12492 * Some of the operations like Core reset require delay before
12493 * accessing PCIE MMIO register space.
12494 * If this value is non-zero, drivers have to wait for
12495 * this much time after writing reset_reg_val in reset_reg.
12497 uint8_t delay_after_reset[16];
12499 * Error recovery counter.
12500 * Lower 2 bits indicates address space location and upper 30 bits
12501 * indicates actual address.
12502 * A value of 0xFFFF-FFFF indicates this register does not exist.
12504 uint32_t err_recovery_cnt_reg;
12505 /* Lower 2 bits indicates address space location. */
12506 #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_ERR_RECOVERY_CNT_REG_ADDR_SPACE_MASK \
12508 #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_ERR_RECOVERY_CNT_REG_ADDR_SPACE_SFT \
12511 * If value is 0, this register is located in PCIe config space.
12512 * Drivers have to map appropriate window to access this
12515 #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_ERR_RECOVERY_CNT_REG_ADDR_SPACE_PCIE_CFG \
12518 * If value is 1, this register is located in GRC address space.
12519 * Drivers have to map appropriate window to access this
12522 #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_ERR_RECOVERY_CNT_REG_ADDR_SPACE_GRC \
12525 * If value is 2, this register is located in first BAR address
12526 * space. Drivers have to map appropriate window to access this
12529 #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_ERR_RECOVERY_CNT_REG_ADDR_SPACE_BAR0 \
12532 * If value is 3, this register is located in second BAR address
12533 * space. Drivers have to map appropriate window to access this
12536 #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_ERR_RECOVERY_CNT_REG_ADDR_SPACE_BAR1 \
12538 #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_ERR_RECOVERY_CNT_REG_ADDR_SPACE_LAST \
12539 HWRM_ERROR_RECOVERY_QCFG_OUTPUT_ERR_RECOVERY_CNT_REG_ADDR_SPACE_BAR1
12540 /* Upper 30bits of the register address. */
12541 #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_ERR_RECOVERY_CNT_REG_ADDR_MASK \
12542 UINT32_C(0xfffffffc)
12543 #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_ERR_RECOVERY_CNT_REG_ADDR_SFT \
12545 uint8_t unused_1[3];
12547 * This field is used in Output records to indicate that the output
12548 * is completely written to RAM. This field should be read as '1'
12549 * to indicate that the output has been completely written.
12550 * When writing a command completion or response to an internal
12551 * processor, the order of writes has to be such that this field
12557 /***********************
12558 * hwrm_func_vlan_qcfg *
12559 ***********************/
12562 /* hwrm_func_vlan_qcfg_input (size:192b/24B) */
12563 struct hwrm_func_vlan_qcfg_input {
12564 /* The HWRM command request type. */
12567 * The completion ring to send the completion event on. This should
12568 * be the NQ ID returned from the `nq_alloc` HWRM command.
12570 uint16_t cmpl_ring;
12572 * The sequence ID is used by the driver for tracking multiple
12573 * commands. This ID is treated as opaque data by the firmware and
12574 * the value is returned in the `hwrm_resp_hdr` upon completion.
12578 * The target ID of the command:
12579 * * 0x0-0xFFF8 - The function ID
12580 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
12581 * * 0xFFFD - Reserved for user-space HWRM interface
12584 uint16_t target_id;
12586 * A physical address pointer pointing to a host buffer that the
12587 * command's response data will be written. This can be either a host
12588 * physical address (HPA) or a guest physical address (GPA) and must
12589 * point to a physically contiguous block of memory.
12591 uint64_t resp_addr;
12593 * Function ID of the function that is being
12595 * If set to 0xFF... (All Fs), then the configuration is
12596 * for the requesting function.
12599 uint8_t unused_0[6];
12602 /* hwrm_func_vlan_qcfg_output (size:320b/40B) */
12603 struct hwrm_func_vlan_qcfg_output {
12604 /* The specific error status for the command. */
12605 uint16_t error_code;
12606 /* The HWRM command request type. */
12608 /* The sequence ID from the original command. */
12610 /* The length of the response data in number of bytes. */
12613 /* S-TAG VLAN identifier configured for the function. */
12615 /* S-TAG PCP value configured for the function. */
12619 * S-TAG TPID value configured for the function. This field is specified in
12620 * network byte order.
12622 uint16_t stag_tpid;
12623 /* C-TAG VLAN identifier configured for the function. */
12625 /* C-TAG PCP value configured for the function. */
12629 * C-TAG TPID value configured for the function. This field is specified in
12630 * network byte order.
12632 uint16_t ctag_tpid;
12637 uint8_t unused_3[3];
12639 * This field is used in Output records to indicate that the output
12640 * is completely written to RAM. This field should be read as '1'
12641 * to indicate that the output has been completely written.
12642 * When writing a command completion or response to an internal processor,
12643 * the order of writes has to be such that this field is written last.
12648 /**********************
12649 * hwrm_func_vlan_cfg *
12650 **********************/
12653 /* hwrm_func_vlan_cfg_input (size:384b/48B) */
12654 struct hwrm_func_vlan_cfg_input {
12655 /* The HWRM command request type. */
12658 * The completion ring to send the completion event on. This should
12659 * be the NQ ID returned from the `nq_alloc` HWRM command.
12661 uint16_t cmpl_ring;
12663 * The sequence ID is used by the driver for tracking multiple
12664 * commands. This ID is treated as opaque data by the firmware and
12665 * the value is returned in the `hwrm_resp_hdr` upon completion.
12669 * The target ID of the command:
12670 * * 0x0-0xFFF8 - The function ID
12671 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
12672 * * 0xFFFD - Reserved for user-space HWRM interface
12675 uint16_t target_id;
12677 * A physical address pointer pointing to a host buffer that the
12678 * command's response data will be written. This can be either a host
12679 * physical address (HPA) or a guest physical address (GPA) and must
12680 * point to a physically contiguous block of memory.
12682 uint64_t resp_addr;
12684 * Function ID of the function that is being
12686 * If set to 0xFF... (All Fs), then the configuration is
12687 * for the requesting function.
12690 uint8_t unused_0[2];
12693 * This bit must be '1' for the stag_vid field to be
12696 #define HWRM_FUNC_VLAN_CFG_INPUT_ENABLES_STAG_VID UINT32_C(0x1)
12698 * This bit must be '1' for the ctag_vid field to be
12701 #define HWRM_FUNC_VLAN_CFG_INPUT_ENABLES_CTAG_VID UINT32_C(0x2)
12703 * This bit must be '1' for the stag_pcp field to be
12706 #define HWRM_FUNC_VLAN_CFG_INPUT_ENABLES_STAG_PCP UINT32_C(0x4)
12708 * This bit must be '1' for the ctag_pcp field to be
12711 #define HWRM_FUNC_VLAN_CFG_INPUT_ENABLES_CTAG_PCP UINT32_C(0x8)
12713 * This bit must be '1' for the stag_tpid field to be
12716 #define HWRM_FUNC_VLAN_CFG_INPUT_ENABLES_STAG_TPID UINT32_C(0x10)
12718 * This bit must be '1' for the ctag_tpid field to be
12721 #define HWRM_FUNC_VLAN_CFG_INPUT_ENABLES_CTAG_TPID UINT32_C(0x20)
12722 /* S-TAG VLAN identifier configured for the function. */
12724 /* S-TAG PCP value configured for the function. */
12728 * S-TAG TPID value configured for the function. This field is specified in
12729 * network byte order.
12731 uint16_t stag_tpid;
12732 /* C-TAG VLAN identifier configured for the function. */
12734 /* C-TAG PCP value configured for the function. */
12738 * C-TAG TPID value configured for the function. This field is specified in
12739 * network byte order.
12741 uint16_t ctag_tpid;
12746 uint8_t unused_3[4];
12749 /* hwrm_func_vlan_cfg_output (size:128b/16B) */
12750 struct hwrm_func_vlan_cfg_output {
12751 /* The specific error status for the command. */
12752 uint16_t error_code;
12753 /* The HWRM command request type. */
12755 /* The sequence ID from the original command. */
12757 /* The length of the response data in number of bytes. */
12759 uint8_t unused_0[7];
12761 * This field is used in Output records to indicate that the output
12762 * is completely written to RAM. This field should be read as '1'
12763 * to indicate that the output has been completely written.
12764 * When writing a command completion or response to an internal processor,
12765 * the order of writes has to be such that this field is written last.
12770 /*******************************
12771 * hwrm_func_vf_vnic_ids_query *
12772 *******************************/
12775 /* hwrm_func_vf_vnic_ids_query_input (size:256b/32B) */
12776 struct hwrm_func_vf_vnic_ids_query_input {
12777 /* The HWRM command request type. */
12780 * The completion ring to send the completion event on. This should
12781 * be the NQ ID returned from the `nq_alloc` HWRM command.
12783 uint16_t cmpl_ring;
12785 * The sequence ID is used by the driver for tracking multiple
12786 * commands. This ID is treated as opaque data by the firmware and
12787 * the value is returned in the `hwrm_resp_hdr` upon completion.
12791 * The target ID of the command:
12792 * * 0x0-0xFFF8 - The function ID
12793 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
12794 * * 0xFFFD - Reserved for user-space HWRM interface
12797 uint16_t target_id;
12799 * A physical address pointer pointing to a host buffer that the
12800 * command's response data will be written. This can be either a host
12801 * physical address (HPA) or a guest physical address (GPA) and must
12802 * point to a physically contiguous block of memory.
12804 uint64_t resp_addr;
12806 * This value is used to identify a Virtual Function (VF).
12807 * The scope of VF ID is local within a PF.
12810 uint8_t unused_0[2];
12811 /* Max number of vnic ids in vnic id table */
12812 uint32_t max_vnic_id_cnt;
12813 /* This is the address for VF VNIC ID table */
12814 uint64_t vnic_id_tbl_addr;
12817 /* hwrm_func_vf_vnic_ids_query_output (size:128b/16B) */
12818 struct hwrm_func_vf_vnic_ids_query_output {
12819 /* The specific error status for the command. */
12820 uint16_t error_code;
12821 /* The HWRM command request type. */
12823 /* The sequence ID from the original command. */
12825 /* The length of the response data in number of bytes. */
12828 * Actual number of vnic ids
12830 * Each VNIC ID is written as a 32-bit number.
12832 uint32_t vnic_id_cnt;
12833 uint8_t unused_0[3];
12835 * This field is used in Output records to indicate that the output
12836 * is completely written to RAM. This field should be read as '1'
12837 * to indicate that the output has been completely written.
12838 * When writing a command completion or response to an internal processor,
12839 * the order of writes has to be such that this field is written last.
12844 /***********************
12845 * hwrm_func_vf_bw_cfg *
12846 ***********************/
12849 /* hwrm_func_vf_bw_cfg_input (size:960b/120B) */
12850 struct hwrm_func_vf_bw_cfg_input {
12851 /* The HWRM command request type. */
12854 * The completion ring to send the completion event on. This should
12855 * be the NQ ID returned from the `nq_alloc` HWRM command.
12857 uint16_t cmpl_ring;
12859 * The sequence ID is used by the driver for tracking multiple
12860 * commands. This ID is treated as opaque data by the firmware and
12861 * the value is returned in the `hwrm_resp_hdr` upon completion.
12865 * The target ID of the command:
12866 * * 0x0-0xFFF8 - The function ID
12867 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
12868 * * 0xFFFD - Reserved for user-space HWRM interface
12871 uint16_t target_id;
12873 * A physical address pointer pointing to a host buffer that the
12874 * command's response data will be written. This can be either a host
12875 * physical address (HPA) or a guest physical address (GPA) and must
12876 * point to a physically contiguous block of memory.
12878 uint64_t resp_addr;
12880 * The number of VF functions that are being configured.
12881 * The cmd space allows up to 50 VFs' BW to be configured with one cmd.
12884 uint16_t unused[3];
12885 /* These 16-bit fields contain the VF fid and the rate scale percentage. */
12887 /* The physical VF id the adjustment will be made to. */
12888 #define HWRM_FUNC_VF_BW_CFG_INPUT_VFN_VFID_MASK UINT32_C(0xfff)
12889 #define HWRM_FUNC_VF_BW_CFG_INPUT_VFN_VFID_SFT 0
12891 * This field configures the rate scale percentage of the VF as specified
12892 * by the physical VF id.
12894 #define HWRM_FUNC_VF_BW_CFG_INPUT_VFN_RATE_MASK UINT32_C(0xf000)
12895 #define HWRM_FUNC_VF_BW_CFG_INPUT_VFN_RATE_SFT 12
12896 /* 0% of the max tx rate */
12897 #define HWRM_FUNC_VF_BW_CFG_INPUT_VFN_RATE_PCT_0 \
12898 (UINT32_C(0x0) << 12)
12899 /* 6.66% of the max tx rate */
12900 #define HWRM_FUNC_VF_BW_CFG_INPUT_VFN_RATE_PCT_6_66 \
12901 (UINT32_C(0x1) << 12)
12902 /* 13.33% of the max tx rate */
12903 #define HWRM_FUNC_VF_BW_CFG_INPUT_VFN_RATE_PCT_13_33 \
12904 (UINT32_C(0x2) << 12)
12905 /* 20% of the max tx rate */
12906 #define HWRM_FUNC_VF_BW_CFG_INPUT_VFN_RATE_PCT_20 \
12907 (UINT32_C(0x3) << 12)
12908 /* 26.66% of the max tx rate */
12909 #define HWRM_FUNC_VF_BW_CFG_INPUT_VFN_RATE_PCT_26_66 \
12910 (UINT32_C(0x4) << 12)
12911 /* 33% of the max tx rate */
12912 #define HWRM_FUNC_VF_BW_CFG_INPUT_VFN_RATE_PCT_33_33 \
12913 (UINT32_C(0x5) << 12)
12914 /* 40% of the max tx rate */
12915 #define HWRM_FUNC_VF_BW_CFG_INPUT_VFN_RATE_PCT_40 \
12916 (UINT32_C(0x6) << 12)
12917 /* 46.66% of the max tx rate */
12918 #define HWRM_FUNC_VF_BW_CFG_INPUT_VFN_RATE_PCT_46_66 \
12919 (UINT32_C(0x7) << 12)
12920 /* 53.33% of the max tx rate */
12921 #define HWRM_FUNC_VF_BW_CFG_INPUT_VFN_RATE_PCT_53_33 \
12922 (UINT32_C(0x8) << 12)
12923 /* 60% of the max tx rate */
12924 #define HWRM_FUNC_VF_BW_CFG_INPUT_VFN_RATE_PCT_60 \
12925 (UINT32_C(0x9) << 12)
12926 /* 66.66% of the max tx rate */
12927 #define HWRM_FUNC_VF_BW_CFG_INPUT_VFN_RATE_PCT_66_66 \
12928 (UINT32_C(0xa) << 12)
12929 /* 53.33% of the max tx rate */
12930 #define HWRM_FUNC_VF_BW_CFG_INPUT_VFN_RATE_PCT_73_33 \
12931 (UINT32_C(0xb) << 12)
12932 /* 80% of the max tx rate */
12933 #define HWRM_FUNC_VF_BW_CFG_INPUT_VFN_RATE_PCT_80 \
12934 (UINT32_C(0xc) << 12)
12935 /* 86.66% of the max tx rate */
12936 #define HWRM_FUNC_VF_BW_CFG_INPUT_VFN_RATE_PCT_86_66 \
12937 (UINT32_C(0xd) << 12)
12938 /* 93.33% of the max tx rate */
12939 #define HWRM_FUNC_VF_BW_CFG_INPUT_VFN_RATE_PCT_93_33 \
12940 (UINT32_C(0xe) << 12)
12941 /* 100% of the max tx rate */
12942 #define HWRM_FUNC_VF_BW_CFG_INPUT_VFN_RATE_PCT_100 \
12943 (UINT32_C(0xf) << 12)
12944 #define HWRM_FUNC_VF_BW_CFG_INPUT_VFN_RATE_LAST \
12945 HWRM_FUNC_VF_BW_CFG_INPUT_VFN_RATE_PCT_100
12948 /* hwrm_func_vf_bw_cfg_output (size:128b/16B) */
12949 struct hwrm_func_vf_bw_cfg_output {
12950 /* The specific error status for the command. */
12951 uint16_t error_code;
12952 /* The HWRM command request type. */
12954 /* The sequence ID from the original command. */
12956 /* The length of the response data in number of bytes. */
12958 uint8_t unused_0[7];
12960 * This field is used in Output records to indicate that the output
12961 * is completely written to RAM. This field should be read as '1'
12962 * to indicate that the output has been completely written.
12963 * When writing a command completion or response to an internal processor,
12964 * the order of writes has to be such that this field is written last.
12969 /************************
12970 * hwrm_func_vf_bw_qcfg *
12971 ************************/
12974 /* hwrm_func_vf_bw_qcfg_input (size:960b/120B) */
12975 struct hwrm_func_vf_bw_qcfg_input {
12976 /* The HWRM command request type. */
12979 * The completion ring to send the completion event on. This should
12980 * be the NQ ID returned from the `nq_alloc` HWRM command.
12982 uint16_t cmpl_ring;
12984 * The sequence ID is used by the driver for tracking multiple
12985 * commands. This ID is treated as opaque data by the firmware and
12986 * the value is returned in the `hwrm_resp_hdr` upon completion.
12990 * The target ID of the command:
12991 * * 0x0-0xFFF8 - The function ID
12992 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
12993 * * 0xFFFD - Reserved for user-space HWRM interface
12996 uint16_t target_id;
12998 * A physical address pointer pointing to a host buffer that the
12999 * command's response data will be written. This can be either a host
13000 * physical address (HPA) or a guest physical address (GPA) and must
13001 * point to a physically contiguous block of memory.
13003 uint64_t resp_addr;
13005 * The number of VF functions that are being queried.
13006 * The inline response space allows the host to query up to 50 VFs'
13007 * rate scale percentage
13010 uint16_t unused[3];
13011 /* These 16-bit fields contain the VF fid */
13013 /* The physical VF id of interest */
13014 #define HWRM_FUNC_VF_BW_QCFG_INPUT_VFN_VFID_MASK UINT32_C(0xfff)
13015 #define HWRM_FUNC_VF_BW_QCFG_INPUT_VFN_VFID_SFT 0
13018 /* hwrm_func_vf_bw_qcfg_output (size:960b/120B) */
13019 struct hwrm_func_vf_bw_qcfg_output {
13020 /* The specific error status for the command. */
13021 uint16_t error_code;
13022 /* The HWRM command request type. */
13024 /* The sequence ID from the original command. */
13026 /* The length of the response data in number of bytes. */
13029 * The number of VF functions that are being queried.
13030 * The inline response space allows the host to query up to 50 VFs' rate
13034 uint16_t unused[3];
13035 /* These 16-bit fields contain the VF fid and the rate scale percentage. */
13037 /* The physical VF id the adjustment will be made to. */
13038 #define HWRM_FUNC_VF_BW_QCFG_OUTPUT_VFN_VFID_MASK UINT32_C(0xfff)
13039 #define HWRM_FUNC_VF_BW_QCFG_OUTPUT_VFN_VFID_SFT 0
13041 * This field configures the rate scale percentage of the VF as specified
13042 * by the physical VF id.
13044 #define HWRM_FUNC_VF_BW_QCFG_OUTPUT_VFN_RATE_MASK UINT32_C(0xf000)
13045 #define HWRM_FUNC_VF_BW_QCFG_OUTPUT_VFN_RATE_SFT 12
13046 /* 0% of the max tx rate */
13047 #define HWRM_FUNC_VF_BW_QCFG_OUTPUT_VFN_RATE_PCT_0 \
13048 (UINT32_C(0x0) << 12)
13049 /* 6.66% of the max tx rate */
13050 #define HWRM_FUNC_VF_BW_QCFG_OUTPUT_VFN_RATE_PCT_6_66 \
13051 (UINT32_C(0x1) << 12)
13052 /* 13.33% of the max tx rate */
13053 #define HWRM_FUNC_VF_BW_QCFG_OUTPUT_VFN_RATE_PCT_13_33 \
13054 (UINT32_C(0x2) << 12)
13055 /* 20% of the max tx rate */
13056 #define HWRM_FUNC_VF_BW_QCFG_OUTPUT_VFN_RATE_PCT_20 \
13057 (UINT32_C(0x3) << 12)
13058 /* 26.66% of the max tx rate */
13059 #define HWRM_FUNC_VF_BW_QCFG_OUTPUT_VFN_RATE_PCT_26_66 \
13060 (UINT32_C(0x4) << 12)
13061 /* 33% of the max tx rate */
13062 #define HWRM_FUNC_VF_BW_QCFG_OUTPUT_VFN_RATE_PCT_33_33 \
13063 (UINT32_C(0x5) << 12)
13064 /* 40% of the max tx rate */
13065 #define HWRM_FUNC_VF_BW_QCFG_OUTPUT_VFN_RATE_PCT_40 \
13066 (UINT32_C(0x6) << 12)
13067 /* 46.66% of the max tx rate */
13068 #define HWRM_FUNC_VF_BW_QCFG_OUTPUT_VFN_RATE_PCT_46_66 \
13069 (UINT32_C(0x7) << 12)
13070 /* 53.33% of the max tx rate */
13071 #define HWRM_FUNC_VF_BW_QCFG_OUTPUT_VFN_RATE_PCT_53_33 \
13072 (UINT32_C(0x8) << 12)
13073 /* 60% of the max tx rate */
13074 #define HWRM_FUNC_VF_BW_QCFG_OUTPUT_VFN_RATE_PCT_60 \
13075 (UINT32_C(0x9) << 12)
13076 /* 66.66% of the max tx rate */
13077 #define HWRM_FUNC_VF_BW_QCFG_OUTPUT_VFN_RATE_PCT_66_66 \
13078 (UINT32_C(0xa) << 12)
13079 /* 53.33% of the max tx rate */
13080 #define HWRM_FUNC_VF_BW_QCFG_OUTPUT_VFN_RATE_PCT_73_33 \
13081 (UINT32_C(0xb) << 12)
13082 /* 80% of the max tx rate */
13083 #define HWRM_FUNC_VF_BW_QCFG_OUTPUT_VFN_RATE_PCT_80 \
13084 (UINT32_C(0xc) << 12)
13085 /* 86.66% of the max tx rate */
13086 #define HWRM_FUNC_VF_BW_QCFG_OUTPUT_VFN_RATE_PCT_86_66 \
13087 (UINT32_C(0xd) << 12)
13088 /* 93.33% of the max tx rate */
13089 #define HWRM_FUNC_VF_BW_QCFG_OUTPUT_VFN_RATE_PCT_93_33 \
13090 (UINT32_C(0xe) << 12)
13091 /* 100% of the max tx rate */
13092 #define HWRM_FUNC_VF_BW_QCFG_OUTPUT_VFN_RATE_PCT_100 \
13093 (UINT32_C(0xf) << 12)
13094 #define HWRM_FUNC_VF_BW_QCFG_OUTPUT_VFN_RATE_LAST \
13095 HWRM_FUNC_VF_BW_QCFG_OUTPUT_VFN_RATE_PCT_100
13096 uint8_t unused_0[7];
13098 * This field is used in Output records to indicate that the output
13099 * is completely written to RAM. This field should be read as '1'
13100 * to indicate that the output has been completely written.
13101 * When writing a command completion or response to an internal processor,
13102 * the order of writes has to be such that this field is written last.
13107 /***************************
13108 * hwrm_func_drv_if_change *
13109 ***************************/
13112 /* hwrm_func_drv_if_change_input (size:192b/24B) */
13113 struct hwrm_func_drv_if_change_input {
13114 /* The HWRM command request type. */
13117 * The completion ring to send the completion event on. This should
13118 * be the NQ ID returned from the `nq_alloc` HWRM command.
13120 uint16_t cmpl_ring;
13122 * The sequence ID is used by the driver for tracking multiple
13123 * commands. This ID is treated as opaque data by the firmware and
13124 * the value is returned in the `hwrm_resp_hdr` upon completion.
13128 * The target ID of the command:
13129 * * 0x0-0xFFF8 - The function ID
13130 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
13131 * * 0xFFFD - Reserved for user-space HWRM interface
13134 uint16_t target_id;
13136 * A physical address pointer pointing to a host buffer that the
13137 * command's response data will be written. This can be either a host
13138 * physical address (HPA) or a guest physical address (GPA) and must
13139 * point to a physically contiguous block of memory.
13141 uint64_t resp_addr;
13144 * When this bit is '1', the function driver is indicating
13145 * that the IF state is changing to UP state. The call should
13146 * be made at the beginning of the driver's open call before
13147 * resources are allocated. After making the call, the driver
13148 * should check the response to see if any resources may have
13149 * changed (see the response below). If the driver fails
13150 * the open call, the driver should make this call again with
13151 * this bit cleared to indicate that the IF state is not UP.
13152 * During the driver's close call when the IF state is changing
13153 * to DOWN, the driver should make this call with the bit cleared
13154 * after all resources have been freed.
13156 #define HWRM_FUNC_DRV_IF_CHANGE_INPUT_FLAGS_UP UINT32_C(0x1)
13160 /* hwrm_func_drv_if_change_output (size:128b/16B) */
13161 struct hwrm_func_drv_if_change_output {
13162 /* The specific error status for the command. */
13163 uint16_t error_code;
13164 /* The HWRM command request type. */
13166 /* The sequence ID from the original command. */
13168 /* The length of the response data in number of bytes. */
13172 * When this bit is '1', it indicates that the resources reserved
13173 * for this function may have changed. The driver should check
13174 * resource capabilities and reserve resources again before
13175 * allocating resources.
13177 #define HWRM_FUNC_DRV_IF_CHANGE_OUTPUT_FLAGS_RESC_CHANGE \
13180 * When this bit is '1', it indicates that the firmware got changed / reset.
13181 * The driver should do complete re-initialization when that bit is set.
13183 #define HWRM_FUNC_DRV_IF_CHANGE_OUTPUT_FLAGS_HOT_FW_RESET_DONE \
13185 uint8_t unused_0[3];
13187 * This field is used in Output records to indicate that the output
13188 * is completely written to RAM. This field should be read as '1'
13189 * to indicate that the output has been completely written.
13190 * When writing a command completion or response to an internal processor,
13191 * the order of writes has to be such that this field is written last.
13196 /*******************************
13197 * hwrm_func_host_pf_ids_query *
13198 *******************************/
13201 /* hwrm_func_host_pf_ids_query_input (size:192b/24B) */
13202 struct hwrm_func_host_pf_ids_query_input {
13203 /* The HWRM command request type. */
13206 * The completion ring to send the completion event on. This should
13207 * be the NQ ID returned from the `nq_alloc` HWRM command.
13209 uint16_t cmpl_ring;
13211 * The sequence ID is used by the driver for tracking multiple
13212 * commands. This ID is treated as opaque data by the firmware and
13213 * the value is returned in the `hwrm_resp_hdr` upon completion.
13217 * The target ID of the command:
13218 * * 0x0-0xFFF8 - The function ID
13219 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
13220 * * 0xFFFD - Reserved for user-space HWRM interface
13223 uint16_t target_id;
13225 * A physical address pointer pointing to a host buffer that the
13226 * command's response data will be written. This can be either a host
13227 * physical address (HPA) or a guest physical address (GPA) and must
13228 * point to a physically contiguous block of memory.
13230 uint64_t resp_addr;
13233 * # If this bit is set to '1', the query will contain PF(s)
13234 * belongs to SOC host.
13236 #define HWRM_FUNC_HOST_PF_IDS_QUERY_INPUT_HOST_SOC UINT32_C(0x1)
13238 * # If this bit is set to '1', the query will contain PF(s)
13239 * belongs to EP0 host.
13241 #define HWRM_FUNC_HOST_PF_IDS_QUERY_INPUT_HOST_EP_0 UINT32_C(0x2)
13243 * # If this bit is set to '1', the query will contain PF(s)
13244 * belongs to EP1 host.
13246 #define HWRM_FUNC_HOST_PF_IDS_QUERY_INPUT_HOST_EP_1 UINT32_C(0x4)
13248 * # If this bit is set to '1', the query will contain PF(s)
13249 * belongs to EP2 host.
13251 #define HWRM_FUNC_HOST_PF_IDS_QUERY_INPUT_HOST_EP_2 UINT32_C(0x8)
13253 * # If this bit is set to '1', the query will contain PF(s)
13254 * belongs to EP3 host.
13256 #define HWRM_FUNC_HOST_PF_IDS_QUERY_INPUT_HOST_EP_3 UINT32_C(0x10)
13258 * This provides a filter of what PF(s) will be returned in the
13263 * all available PF(s) belong to the host(s) (defined in the
13264 * host field). This includes the hidden PFs.
13266 #define HWRM_FUNC_HOST_PF_IDS_QUERY_INPUT_FILTER_ALL UINT32_C(0x0)
13268 * all available PF(s) belong to the host(s) (defined in the
13269 * host field) that is available for L2 traffic.
13271 #define HWRM_FUNC_HOST_PF_IDS_QUERY_INPUT_FILTER_L2 UINT32_C(0x1)
13273 * all available PF(s) belong to the host(s) (defined in the
13274 * host field) that is available for ROCE traffic.
13276 #define HWRM_FUNC_HOST_PF_IDS_QUERY_INPUT_FILTER_ROCE UINT32_C(0x2)
13277 #define HWRM_FUNC_HOST_PF_IDS_QUERY_INPUT_FILTER_LAST \
13278 HWRM_FUNC_HOST_PF_IDS_QUERY_INPUT_FILTER_ROCE
13279 uint8_t unused_1[6];
13282 /* hwrm_func_host_pf_ids_query_output (size:128b/16B) */
13283 struct hwrm_func_host_pf_ids_query_output {
13284 /* The specific error status for the command. */
13285 uint16_t error_code;
13286 /* The HWRM command request type. */
13288 /* The sequence ID from the original command. */
13290 /* The length of the response data in number of bytes. */
13292 /* This provides the first PF ID of the device. */
13293 uint16_t first_pf_id;
13294 uint16_t pf_ordinal_mask;
13296 * When this bit is '1', it indicates first PF belongs to one of
13297 * the hosts defined in the input request.
13299 #define HWRM_FUNC_HOST_PF_IDS_QUERY_OUTPUT_PF_ORDINAL_MASK_FUNC_0 \
13302 * When this bit is '1', it indicates 2nd PF belongs to one of the
13303 * hosts defined in the input request.
13305 #define HWRM_FUNC_HOST_PF_IDS_QUERY_OUTPUT_PF_ORDINAL_MASK_FUNC_1 \
13308 * When this bit is '1', it indicates 3rd PF belongs to one of the
13309 * hosts defined in the input request.
13311 #define HWRM_FUNC_HOST_PF_IDS_QUERY_OUTPUT_PF_ORDINAL_MASK_FUNC_2 \
13314 * When this bit is '1', it indicates 4th PF belongs to one of the
13315 * hosts defined in the input request.
13317 #define HWRM_FUNC_HOST_PF_IDS_QUERY_OUTPUT_PF_ORDINAL_MASK_FUNC_3 \
13320 * When this bit is '1', it indicates 5th PF belongs to one of the
13321 * hosts defined in the input request.
13323 #define HWRM_FUNC_HOST_PF_IDS_QUERY_OUTPUT_PF_ORDINAL_MASK_FUNC_4 \
13326 * When this bit is '1', it indicates 6th PF belongs to one of the
13327 * hosts defined in the input request.
13329 #define HWRM_FUNC_HOST_PF_IDS_QUERY_OUTPUT_PF_ORDINAL_MASK_FUNC_5 \
13332 * When this bit is '1', it indicates 7th PF belongs to one of the
13333 * hosts defined in the input request.
13335 #define HWRM_FUNC_HOST_PF_IDS_QUERY_OUTPUT_PF_ORDINAL_MASK_FUNC_6 \
13338 * When this bit is '1', it indicates 8th PF belongs to one of the
13339 * hosts defined in the input request.
13341 #define HWRM_FUNC_HOST_PF_IDS_QUERY_OUTPUT_PF_ORDINAL_MASK_FUNC_7 \
13344 * When this bit is '1', it indicates 9th PF belongs to one of the
13345 * hosts defined in the input request.
13347 #define HWRM_FUNC_HOST_PF_IDS_QUERY_OUTPUT_PF_ORDINAL_MASK_FUNC_8 \
13350 * When this bit is '1', it indicates 10th PF belongs to one of the
13351 * hosts defined in the input request.
13353 #define HWRM_FUNC_HOST_PF_IDS_QUERY_OUTPUT_PF_ORDINAL_MASK_FUNC_9 \
13356 * When this bit is '1', it indicates 11th PF belongs to one of the
13357 * hosts defined in the input request.
13359 #define HWRM_FUNC_HOST_PF_IDS_QUERY_OUTPUT_PF_ORDINAL_MASK_FUNC_10 \
13362 * When this bit is '1', it indicates 12th PF belongs to one of the
13363 * hosts defined in the input request.
13365 #define HWRM_FUNC_HOST_PF_IDS_QUERY_OUTPUT_PF_ORDINAL_MASK_FUNC_11 \
13368 * When this bit is '1', it indicates 13th PF belongs to one of the
13369 * hosts defined in the input request.
13371 #define HWRM_FUNC_HOST_PF_IDS_QUERY_OUTPUT_PF_ORDINAL_MASK_FUNC_12 \
13374 * When this bit is '1', it indicates 14th PF belongs to one of the
13375 * hosts defined in the input request.
13377 #define HWRM_FUNC_HOST_PF_IDS_QUERY_OUTPUT_PF_ORDINAL_MASK_FUNC_13 \
13380 * When this bit is '1', it indicates 15th PF belongs to one of the
13381 * hosts defined in the input request.
13383 #define HWRM_FUNC_HOST_PF_IDS_QUERY_OUTPUT_PF_ORDINAL_MASK_FUNC_14 \
13386 * When this bit is '1', it indicates 16th PF belongs to one of the
13387 * hosts defined in the input request.
13389 #define HWRM_FUNC_HOST_PF_IDS_QUERY_OUTPUT_PF_ORDINAL_MASK_FUNC_15 \
13391 uint8_t unused_1[3];
13393 * This field is used in Output records to indicate that the output
13394 * is completely written to RAM. This field should be read as '1'
13395 * to indicate that the output has been completely written.
13396 * When writing a command completion or response to an internal processor,
13397 * the order of writes has to be such that this field is written last.
13402 /*********************
13403 * hwrm_port_phy_cfg *
13404 *********************/
13407 /* hwrm_port_phy_cfg_input (size:448b/56B) */
13408 struct hwrm_port_phy_cfg_input {
13409 /* The HWRM command request type. */
13412 * The completion ring to send the completion event on. This should
13413 * be the NQ ID returned from the `nq_alloc` HWRM command.
13415 uint16_t cmpl_ring;
13417 * The sequence ID is used by the driver for tracking multiple
13418 * commands. This ID is treated as opaque data by the firmware and
13419 * the value is returned in the `hwrm_resp_hdr` upon completion.
13423 * The target ID of the command:
13424 * * 0x0-0xFFF8 - The function ID
13425 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
13426 * * 0xFFFD - Reserved for user-space HWRM interface
13429 uint16_t target_id;
13431 * A physical address pointer pointing to a host buffer that the
13432 * command's response data will be written. This can be either a host
13433 * physical address (HPA) or a guest physical address (GPA) and must
13434 * point to a physically contiguous block of memory.
13436 uint64_t resp_addr;
13439 * When this bit is set to '1', the PHY for the port shall
13442 * # If this bit is set to 1, then the HWRM shall reset the
13443 * PHY after applying PHY configuration changes specified
13445 * # In order to guarantee that PHY configuration changes
13446 * specified in this command take effect, the HWRM
13447 * client should set this flag to 1.
13448 * # If this bit is not set to 1, then the HWRM may reset
13449 * the PHY depending on the current PHY configuration and
13450 * settings specified in this command.
13452 #define HWRM_PORT_PHY_CFG_INPUT_FLAGS_RESET_PHY \
13454 /* deprecated bit. Do not use!!! */
13455 #define HWRM_PORT_PHY_CFG_INPUT_FLAGS_DEPRECATED \
13458 * When this bit is set to '1', the link shall be forced to
13459 * the force_link_speed value.
13461 * When this bit is set to '1', the HWRM client should
13462 * not enable any of the auto negotiation related
13463 * fields represented by auto_XXX fields in this command.
13464 * When this bit is set to '1' and the HWRM client has
13465 * enabled a auto_XXX field in this command, then the
13466 * HWRM shall ignore the enabled auto_XXX field.
13468 * When this bit is set to zero, the link
13469 * shall be allowed to autoneg.
13471 #define HWRM_PORT_PHY_CFG_INPUT_FLAGS_FORCE \
13474 * When this bit is set to '1', the auto-negotiation process
13475 * shall be restarted on the link.
13477 #define HWRM_PORT_PHY_CFG_INPUT_FLAGS_RESTART_AUTONEG \
13480 * When this bit is set to '1', Energy Efficient Ethernet
13481 * (EEE) is requested to be enabled on this link.
13482 * If EEE is not supported on this port, then this flag
13483 * shall be ignored by the HWRM.
13485 #define HWRM_PORT_PHY_CFG_INPUT_FLAGS_EEE_ENABLE \
13488 * When this bit is set to '1', Energy Efficient Ethernet
13489 * (EEE) is requested to be disabled on this link.
13490 * If EEE is not supported on this port, then this flag
13491 * shall be ignored by the HWRM.
13493 #define HWRM_PORT_PHY_CFG_INPUT_FLAGS_EEE_DISABLE \
13496 * When this bit is set to '1' and EEE is enabled on this
13497 * link, then TX LPI is requested to be enabled on the link.
13498 * If EEE is not supported on this port, then this flag
13499 * shall be ignored by the HWRM.
13500 * If EEE is disabled on this port, then this flag shall be
13501 * ignored by the HWRM.
13503 #define HWRM_PORT_PHY_CFG_INPUT_FLAGS_EEE_TX_LPI_ENABLE \
13506 * When this bit is set to '1' and EEE is enabled on this
13507 * link, then TX LPI is requested to be disabled on the link.
13508 * If EEE is not supported on this port, then this flag
13509 * shall be ignored by the HWRM.
13510 * If EEE is disabled on this port, then this flag shall be
13511 * ignored by the HWRM.
13513 #define HWRM_PORT_PHY_CFG_INPUT_FLAGS_EEE_TX_LPI_DISABLE \
13516 * When set to 1, then the HWRM shall enable FEC autonegotitation
13517 * on this port if supported.
13518 * When set to 0, then this flag shall be ignored.
13519 * If FEC autonegotiation is not supported, then the HWRM shall ignore this
13522 #define HWRM_PORT_PHY_CFG_INPUT_FLAGS_FEC_AUTONEG_ENABLE \
13525 * When set to 1, then the HWRM shall disable FEC autonegotiation
13526 * on this port if supported.
13527 * When set to 0, then this flag shall be ignored.
13528 * If FEC autonegotiation is not supported, then the HWRM shall ignore this
13531 #define HWRM_PORT_PHY_CFG_INPUT_FLAGS_FEC_AUTONEG_DISABLE \
13534 * When set to 1, then the HWRM shall enable FEC CLAUSE 74 (Fire Code)
13535 * on this port if supported.
13536 * When set to 0, then this flag shall be ignored.
13537 * If FEC CLAUSE 74 is not supported, then the HWRM shall ignore this
13540 #define HWRM_PORT_PHY_CFG_INPUT_FLAGS_FEC_CLAUSE74_ENABLE \
13543 * When set to 1, then the HWRM shall disable FEC CLAUSE 74 (Fire Code)
13544 * on this port if supported.
13545 * When set to 0, then this flag shall be ignored.
13546 * If FEC CLAUSE 74 is not supported, then the HWRM shall ignore this
13549 #define HWRM_PORT_PHY_CFG_INPUT_FLAGS_FEC_CLAUSE74_DISABLE \
13552 * When set to 1, then the HWRM shall enable FEC CLAUSE 91 (Reed Solomon)
13553 * on this port if supported.
13554 * When set to 0, then this flag shall be ignored.
13555 * If FEC CLAUSE 91 is not supported, then the HWRM shall ignore this
13558 #define HWRM_PORT_PHY_CFG_INPUT_FLAGS_FEC_CLAUSE91_ENABLE \
13561 * When set to 1, then the HWRM shall disable FEC CLAUSE 91 (Reed Solomon)
13562 * on this port if supported.
13563 * When set to 0, then this flag shall be ignored.
13564 * If FEC CLAUSE 91 is not supported, then the HWRM shall ignore this
13567 #define HWRM_PORT_PHY_CFG_INPUT_FLAGS_FEC_CLAUSE91_DISABLE \
13570 * When this bit is set to '1', the link shall be forced to
13573 * # When this bit is set to '1", all other
13574 * command input settings related to the link speed shall
13576 * Once the link state is forced down, it can be
13577 * explicitly cleared from that state by setting this flag
13579 * # If this flag is set to '0', then the link shall be
13580 * cleared from forced down state if the link is in forced
13582 * There may be conditions (e.g. out-of-band or sideband
13583 * configuration changes for the link) outside the scope
13584 * of the HWRM implementation that may clear forced down
13587 #define HWRM_PORT_PHY_CFG_INPUT_FLAGS_FORCE_LINK_DWN \
13591 * This bit must be '1' for the auto_mode field to be
13594 #define HWRM_PORT_PHY_CFG_INPUT_ENABLES_AUTO_MODE \
13597 * This bit must be '1' for the auto_duplex field to be
13600 #define HWRM_PORT_PHY_CFG_INPUT_ENABLES_AUTO_DUPLEX \
13603 * This bit must be '1' for the auto_pause field to be
13606 #define HWRM_PORT_PHY_CFG_INPUT_ENABLES_AUTO_PAUSE \
13609 * This bit must be '1' for the auto_link_speed field to be
13612 #define HWRM_PORT_PHY_CFG_INPUT_ENABLES_AUTO_LINK_SPEED \
13615 * This bit must be '1' for the auto_link_speed_mask field to be
13618 #define HWRM_PORT_PHY_CFG_INPUT_ENABLES_AUTO_LINK_SPEED_MASK \
13621 * This bit must be '1' for the wirespeed field to be
13624 #define HWRM_PORT_PHY_CFG_INPUT_ENABLES_WIRESPEED \
13627 * This bit must be '1' for the lpbk field to be
13630 #define HWRM_PORT_PHY_CFG_INPUT_ENABLES_LPBK \
13633 * This bit must be '1' for the preemphasis field to be
13636 #define HWRM_PORT_PHY_CFG_INPUT_ENABLES_PREEMPHASIS \
13639 * This bit must be '1' for the force_pause field to be
13642 #define HWRM_PORT_PHY_CFG_INPUT_ENABLES_FORCE_PAUSE \
13645 * This bit must be '1' for the eee_link_speed_mask field to be
13648 #define HWRM_PORT_PHY_CFG_INPUT_ENABLES_EEE_LINK_SPEED_MASK \
13651 * This bit must be '1' for the tx_lpi_timer field to be
13654 #define HWRM_PORT_PHY_CFG_INPUT_ENABLES_TX_LPI_TIMER \
13656 /* Port ID of port that is to be configured. */
13659 * This is the speed that will be used if the force
13660 * bit is '1'. If unsupported speed is selected, an error
13661 * will be generated.
13663 uint16_t force_link_speed;
13664 /* 100Mb link speed */
13665 #define HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_100MB UINT32_C(0x1)
13666 /* 1Gb link speed */
13667 #define HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_1GB UINT32_C(0xa)
13668 /* 2Gb link speed */
13669 #define HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_2GB UINT32_C(0x14)
13670 /* 25Gb link speed */
13671 #define HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_2_5GB UINT32_C(0x19)
13672 /* 10Gb link speed */
13673 #define HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_10GB UINT32_C(0x64)
13674 /* 20Mb link speed */
13675 #define HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_20GB UINT32_C(0xc8)
13676 /* 25Gb link speed */
13677 #define HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_25GB UINT32_C(0xfa)
13678 /* 40Gb link speed */
13679 #define HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_40GB UINT32_C(0x190)
13680 /* 50Gb link speed */
13681 #define HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_50GB UINT32_C(0x1f4)
13682 /* 100Gb link speed */
13683 #define HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_100GB UINT32_C(0x3e8)
13684 /* 200Gb link speed */
13685 #define HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_200GB UINT32_C(0x7d0)
13686 /* 10Mb link speed */
13687 #define HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_10MB UINT32_C(0xffff)
13688 #define HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_LAST \
13689 HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_10MB
13691 * This value is used to identify what autoneg mode is
13692 * used when the link speed is not being forced.
13695 /* Disable autoneg or autoneg disabled. No speeds are selected. */
13696 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_MODE_NONE UINT32_C(0x0)
13697 /* Select all possible speeds for autoneg mode. */
13698 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_MODE_ALL_SPEEDS UINT32_C(0x1)
13700 * Select only the auto_link_speed speed for autoneg mode. This mode has
13701 * been DEPRECATED. An HWRM client should not use this mode.
13703 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_MODE_ONE_SPEED UINT32_C(0x2)
13705 * Select the auto_link_speed or any speed below that speed for autoneg.
13706 * This mode has been DEPRECATED. An HWRM client should not use this mode.
13708 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_MODE_ONE_OR_BELOW UINT32_C(0x3)
13710 * Select the speeds based on the corresponding link speed mask value
13711 * that is provided.
13713 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_MODE_SPEED_MASK UINT32_C(0x4)
13714 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_MODE_LAST \
13715 HWRM_PORT_PHY_CFG_INPUT_AUTO_MODE_SPEED_MASK
13717 * This is the duplex setting that will be used if the autoneg_mode
13718 * is "one_speed" or "one_or_below".
13720 uint8_t auto_duplex;
13721 /* Half Duplex will be requested. */
13722 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_HALF UINT32_C(0x0)
13723 /* Full duplex will be requested. */
13724 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_FULL UINT32_C(0x1)
13725 /* Both Half and Full dupex will be requested. */
13726 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_BOTH UINT32_C(0x2)
13727 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_LAST \
13728 HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_BOTH
13730 * This value is used to configure the pause that will be
13731 * used for autonegotiation.
13732 * Add text on the usage of auto_pause and force_pause.
13734 uint8_t auto_pause;
13736 * When this bit is '1', Generation of tx pause messages
13737 * has been requested. Disabled otherwise.
13739 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_TX \
13742 * When this bit is '1', Reception of rx pause messages
13743 * has been requested. Disabled otherwise.
13745 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_RX \
13748 * When set to 1, the advertisement of pause is enabled.
13750 * # When the auto_mode is not set to none and this flag is
13751 * set to 1, then the auto_pause bits on this port are being
13752 * advertised and autoneg pause results are being interpreted.
13753 * # When the auto_mode is not set to none and this
13754 * flag is set to 0, the pause is forced as indicated in
13755 * force_pause, and also advertised as auto_pause bits, but
13756 * the autoneg results are not interpreted since the pause
13757 * configuration is being forced.
13758 * # When the auto_mode is set to none and this flag is set to
13759 * 1, auto_pause bits should be ignored and should be set to 0.
13761 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_AUTONEG_PAUSE \
13765 * This is the speed that will be used if the autoneg_mode
13766 * is "one_speed" or "one_or_below". If an unsupported speed
13767 * is selected, an error will be generated.
13769 uint16_t auto_link_speed;
13770 /* 100Mb link speed */
13771 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_100MB UINT32_C(0x1)
13772 /* 1Gb link speed */
13773 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_1GB UINT32_C(0xa)
13774 /* 2Gb link speed */
13775 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_2GB UINT32_C(0x14)
13776 /* 25Gb link speed */
13777 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_2_5GB UINT32_C(0x19)
13778 /* 10Gb link speed */
13779 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_10GB UINT32_C(0x64)
13780 /* 20Mb link speed */
13781 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_20GB UINT32_C(0xc8)
13782 /* 25Gb link speed */
13783 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_25GB UINT32_C(0xfa)
13784 /* 40Gb link speed */
13785 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_40GB UINT32_C(0x190)
13786 /* 50Gb link speed */
13787 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_50GB UINT32_C(0x1f4)
13788 /* 100Gb link speed */
13789 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_100GB UINT32_C(0x3e8)
13790 /* 200Gb link speed */
13791 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_200GB UINT32_C(0x7d0)
13792 /* 10Mb link speed */
13793 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_10MB UINT32_C(0xffff)
13794 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_LAST \
13795 HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_10MB
13797 * This is a mask of link speeds that will be used if
13798 * autoneg_mode is "mask". If unsupported speed is enabled
13799 * an error will be generated.
13801 uint16_t auto_link_speed_mask;
13802 /* 100Mb link speed (Half-duplex) */
13803 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_100MBHD \
13805 /* 100Mb link speed (Full-duplex) */
13806 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_100MB \
13808 /* 1Gb link speed (Half-duplex) */
13809 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_1GBHD \
13811 /* 1Gb link speed (Full-duplex) */
13812 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_1GB \
13814 /* 2Gb link speed */
13815 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_2GB \
13817 /* 25Gb link speed */
13818 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_2_5GB \
13820 /* 10Gb link speed */
13821 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_10GB \
13823 /* 20Gb link speed */
13824 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_20GB \
13826 /* 25Gb link speed */
13827 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_25GB \
13829 /* 40Gb link speed */
13830 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_40GB \
13832 /* 50Gb link speed */
13833 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_50GB \
13835 /* 100Gb link speed */
13836 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_100GB \
13838 /* 10Mb link speed (Half-duplex) */
13839 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_10MBHD \
13841 /* 10Mb link speed (Full-duplex) */
13842 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_10MB \
13844 /* 200Gb link speed */
13845 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_200GB \
13847 /* This value controls the wirespeed feature. */
13849 /* Wirespeed feature is disabled. */
13850 #define HWRM_PORT_PHY_CFG_INPUT_WIRESPEED_OFF UINT32_C(0x0)
13851 /* Wirespeed feature is enabled. */
13852 #define HWRM_PORT_PHY_CFG_INPUT_WIRESPEED_ON UINT32_C(0x1)
13853 #define HWRM_PORT_PHY_CFG_INPUT_WIRESPEED_LAST \
13854 HWRM_PORT_PHY_CFG_INPUT_WIRESPEED_ON
13855 /* This value controls the loopback setting for the PHY. */
13857 /* No loopback is selected. Normal operation. */
13858 #define HWRM_PORT_PHY_CFG_INPUT_LPBK_NONE UINT32_C(0x0)
13860 * The HW will be configured with local loopback such that
13861 * host data is sent back to the host without modification.
13863 #define HWRM_PORT_PHY_CFG_INPUT_LPBK_LOCAL UINT32_C(0x1)
13865 * The HW will be configured with remote loopback such that
13866 * port logic will send packets back out the transmitter that
13869 #define HWRM_PORT_PHY_CFG_INPUT_LPBK_REMOTE UINT32_C(0x2)
13871 * The HW will be configured with external loopback such that
13872 * host data is sent on the transmitter and based on the external
13873 * loopback connection the data will be received without modification.
13875 #define HWRM_PORT_PHY_CFG_INPUT_LPBK_EXTERNAL UINT32_C(0x3)
13876 #define HWRM_PORT_PHY_CFG_INPUT_LPBK_LAST \
13877 HWRM_PORT_PHY_CFG_INPUT_LPBK_EXTERNAL
13879 * This value is used to configure the pause that will be
13880 * used for force mode.
13882 uint8_t force_pause;
13884 * When this bit is '1', Generation of tx pause messages
13885 * is supported. Disabled otherwise.
13887 #define HWRM_PORT_PHY_CFG_INPUT_FORCE_PAUSE_TX UINT32_C(0x1)
13889 * When this bit is '1', Reception of rx pause messages
13890 * is supported. Disabled otherwise.
13892 #define HWRM_PORT_PHY_CFG_INPUT_FORCE_PAUSE_RX UINT32_C(0x2)
13895 * This value controls the pre-emphasis to be used for the
13896 * link. Driver should not set this value (use
13897 * enable.preemphasis = 0) unless driver is sure of setting.
13898 * Normally HWRM FW will determine proper pre-emphasis.
13900 uint32_t preemphasis;
13902 * Setting for link speed mask that is used to
13903 * advertise speeds during autonegotiation when EEE is enabled.
13904 * This field is valid only when EEE is enabled.
13905 * The speeds specified in this field shall be a subset of
13906 * speeds specified in auto_link_speed_mask.
13907 * If EEE is enabled,then at least one speed shall be provided
13910 uint16_t eee_link_speed_mask;
13912 #define HWRM_PORT_PHY_CFG_INPUT_EEE_LINK_SPEED_MASK_RSVD1 \
13914 /* 100Mb link speed (Full-duplex) */
13915 #define HWRM_PORT_PHY_CFG_INPUT_EEE_LINK_SPEED_MASK_100MB \
13918 #define HWRM_PORT_PHY_CFG_INPUT_EEE_LINK_SPEED_MASK_RSVD2 \
13920 /* 1Gb link speed (Full-duplex) */
13921 #define HWRM_PORT_PHY_CFG_INPUT_EEE_LINK_SPEED_MASK_1GB \
13924 #define HWRM_PORT_PHY_CFG_INPUT_EEE_LINK_SPEED_MASK_RSVD3 \
13927 #define HWRM_PORT_PHY_CFG_INPUT_EEE_LINK_SPEED_MASK_RSVD4 \
13929 /* 10Gb link speed */
13930 #define HWRM_PORT_PHY_CFG_INPUT_EEE_LINK_SPEED_MASK_10GB \
13932 uint8_t unused_2[2];
13934 * Requested setting of TX LPI timer in microseconds.
13935 * This field is valid only when EEE is enabled and TX LPI is
13938 uint32_t tx_lpi_timer;
13939 #define HWRM_PORT_PHY_CFG_INPUT_TX_LPI_TIMER_MASK UINT32_C(0xffffff)
13940 #define HWRM_PORT_PHY_CFG_INPUT_TX_LPI_TIMER_SFT 0
13944 /* hwrm_port_phy_cfg_output (size:128b/16B) */
13945 struct hwrm_port_phy_cfg_output {
13946 /* The specific error status for the command. */
13947 uint16_t error_code;
13948 /* The HWRM command request type. */
13950 /* The sequence ID from the original command. */
13952 /* The length of the response data in number of bytes. */
13954 uint8_t unused_0[7];
13956 * This field is used in Output records to indicate that the output
13957 * is completely written to RAM. This field should be read as '1'
13958 * to indicate that the output has been completely written.
13959 * When writing a command completion or response to an internal processor,
13960 * the order of writes has to be such that this field is written last.
13965 /* hwrm_port_phy_cfg_cmd_err (size:64b/8B) */
13966 struct hwrm_port_phy_cfg_cmd_err {
13968 * command specific error codes that goes to
13969 * the cmd_err field in Common HWRM Error Response.
13972 /* Unknown error */
13973 #define HWRM_PORT_PHY_CFG_CMD_ERR_CODE_UNKNOWN UINT32_C(0x0)
13974 /* Unable to complete operation due to invalid speed */
13975 #define HWRM_PORT_PHY_CFG_CMD_ERR_CODE_ILLEGAL_SPEED UINT32_C(0x1)
13977 * retry the command since the phy is not ready.
13978 * retry count is returned in opaque_0.
13979 * This is only valid for the first command and
13980 * this value will not change for successive calls.
13981 * but if a 0 is returned at any time then this should
13982 * be treated as an un recoverable failure,
13984 * retry interval in milli seconds is returned in opaque_1.
13985 * This specifies the time that user should wait before
13986 * issuing the next port_phy_cfg command.
13988 #define HWRM_PORT_PHY_CFG_CMD_ERR_CODE_RETRY UINT32_C(0x2)
13989 #define HWRM_PORT_PHY_CFG_CMD_ERR_CODE_LAST \
13990 HWRM_PORT_PHY_CFG_CMD_ERR_CODE_RETRY
13991 uint8_t unused_0[7];
13994 /**********************
13995 * hwrm_port_phy_qcfg *
13996 **********************/
13999 /* hwrm_port_phy_qcfg_input (size:192b/24B) */
14000 struct hwrm_port_phy_qcfg_input {
14001 /* The HWRM command request type. */
14004 * The completion ring to send the completion event on. This should
14005 * be the NQ ID returned from the `nq_alloc` HWRM command.
14007 uint16_t cmpl_ring;
14009 * The sequence ID is used by the driver for tracking multiple
14010 * commands. This ID is treated as opaque data by the firmware and
14011 * the value is returned in the `hwrm_resp_hdr` upon completion.
14015 * The target ID of the command:
14016 * * 0x0-0xFFF8 - The function ID
14017 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
14018 * * 0xFFFD - Reserved for user-space HWRM interface
14021 uint16_t target_id;
14023 * A physical address pointer pointing to a host buffer that the
14024 * command's response data will be written. This can be either a host
14025 * physical address (HPA) or a guest physical address (GPA) and must
14026 * point to a physically contiguous block of memory.
14028 uint64_t resp_addr;
14029 /* Port ID of port that is to be queried. */
14031 uint8_t unused_0[6];
14034 /* hwrm_port_phy_qcfg_output (size:768b/96B) */
14035 struct hwrm_port_phy_qcfg_output {
14036 /* The specific error status for the command. */
14037 uint16_t error_code;
14038 /* The HWRM command request type. */
14040 /* The sequence ID from the original command. */
14042 /* The length of the response data in number of bytes. */
14044 /* This value indicates the current link status. */
14046 /* There is no link or cable detected. */
14047 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_NO_LINK UINT32_C(0x0)
14048 /* There is no link, but a cable has been detected. */
14049 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SIGNAL UINT32_C(0x1)
14050 /* There is a link. */
14051 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_LINK UINT32_C(0x2)
14052 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_LAST \
14053 HWRM_PORT_PHY_QCFG_OUTPUT_LINK_LINK
14055 /* This value indicates the current link speed of the connection. */
14056 uint16_t link_speed;
14057 /* 100Mb link speed */
14058 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_100MB UINT32_C(0x1)
14059 /* 1Gb link speed */
14060 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_1GB UINT32_C(0xa)
14061 /* 2Gb link speed */
14062 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_2GB UINT32_C(0x14)
14063 /* 25Gb link speed */
14064 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_2_5GB UINT32_C(0x19)
14065 /* 10Gb link speed */
14066 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_10GB UINT32_C(0x64)
14067 /* 20Mb link speed */
14068 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_20GB UINT32_C(0xc8)
14069 /* 25Gb link speed */
14070 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_25GB UINT32_C(0xfa)
14071 /* 40Gb link speed */
14072 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_40GB UINT32_C(0x190)
14073 /* 50Gb link speed */
14074 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_50GB UINT32_C(0x1f4)
14075 /* 100Gb link speed */
14076 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_100GB UINT32_C(0x3e8)
14077 /* 200Gb link speed */
14078 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_200GB UINT32_C(0x7d0)
14079 /* 10Mb link speed */
14080 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_10MB UINT32_C(0xffff)
14081 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_LAST \
14082 HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_10MB
14084 * This value is indicates the duplex of the current
14087 uint8_t duplex_cfg;
14088 /* Half Duplex connection. */
14089 #define HWRM_PORT_PHY_QCFG_OUTPUT_DUPLEX_CFG_HALF UINT32_C(0x0)
14090 /* Full duplex connection. */
14091 #define HWRM_PORT_PHY_QCFG_OUTPUT_DUPLEX_CFG_FULL UINT32_C(0x1)
14092 #define HWRM_PORT_PHY_QCFG_OUTPUT_DUPLEX_CFG_LAST \
14093 HWRM_PORT_PHY_QCFG_OUTPUT_DUPLEX_CFG_FULL
14095 * This value is used to indicate the current
14096 * pause configuration. When autoneg is enabled, this value
14097 * represents the autoneg results of pause configuration.
14101 * When this bit is '1', Generation of tx pause messages
14102 * is supported. Disabled otherwise.
14104 #define HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_TX UINT32_C(0x1)
14106 * When this bit is '1', Reception of rx pause messages
14107 * is supported. Disabled otherwise.
14109 #define HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_RX UINT32_C(0x2)
14111 * The supported speeds for the port. This is a bit mask.
14112 * For each speed that is supported, the corrresponding
14113 * bit will be set to '1'.
14115 uint16_t support_speeds;
14116 /* 100Mb link speed (Half-duplex) */
14117 #define HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_100MBHD \
14119 /* 100Mb link speed (Full-duplex) */
14120 #define HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_100MB \
14122 /* 1Gb link speed (Half-duplex) */
14123 #define HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_1GBHD \
14125 /* 1Gb link speed (Full-duplex) */
14126 #define HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_1GB \
14128 /* 2Gb link speed */
14129 #define HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_2GB \
14131 /* 25Gb link speed */
14132 #define HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_2_5GB \
14134 /* 10Gb link speed */
14135 #define HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_10GB \
14137 /* 20Gb link speed */
14138 #define HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_20GB \
14140 /* 25Gb link speed */
14141 #define HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_25GB \
14143 /* 40Gb link speed */
14144 #define HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_40GB \
14146 /* 50Gb link speed */
14147 #define HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_50GB \
14149 /* 100Gb link speed */
14150 #define HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_100GB \
14152 /* 10Mb link speed (Half-duplex) */
14153 #define HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_10MBHD \
14155 /* 10Mb link speed (Full-duplex) */
14156 #define HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_10MB \
14158 /* 200Gb link speed */
14159 #define HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_200GB \
14162 * Current setting of forced link speed.
14163 * When the link speed is not being forced, this
14164 * value shall be set to 0.
14166 uint16_t force_link_speed;
14167 /* 100Mb link speed */
14168 #define HWRM_PORT_PHY_QCFG_OUTPUT_FORCE_LINK_SPEED_100MB UINT32_C(0x1)
14169 /* 1Gb link speed */
14170 #define HWRM_PORT_PHY_QCFG_OUTPUT_FORCE_LINK_SPEED_1GB UINT32_C(0xa)
14171 /* 2Gb link speed */
14172 #define HWRM_PORT_PHY_QCFG_OUTPUT_FORCE_LINK_SPEED_2GB UINT32_C(0x14)
14173 /* 25Gb link speed */
14174 #define HWRM_PORT_PHY_QCFG_OUTPUT_FORCE_LINK_SPEED_2_5GB UINT32_C(0x19)
14175 /* 10Gb link speed */
14176 #define HWRM_PORT_PHY_QCFG_OUTPUT_FORCE_LINK_SPEED_10GB UINT32_C(0x64)
14177 /* 20Mb link speed */
14178 #define HWRM_PORT_PHY_QCFG_OUTPUT_FORCE_LINK_SPEED_20GB UINT32_C(0xc8)
14179 /* 25Gb link speed */
14180 #define HWRM_PORT_PHY_QCFG_OUTPUT_FORCE_LINK_SPEED_25GB UINT32_C(0xfa)
14181 /* 40Gb link speed */
14182 #define HWRM_PORT_PHY_QCFG_OUTPUT_FORCE_LINK_SPEED_40GB \
14184 /* 50Gb link speed */
14185 #define HWRM_PORT_PHY_QCFG_OUTPUT_FORCE_LINK_SPEED_50GB \
14187 /* 100Gb link speed */
14188 #define HWRM_PORT_PHY_QCFG_OUTPUT_FORCE_LINK_SPEED_100GB \
14190 /* 200Gb link speed */
14191 #define HWRM_PORT_PHY_QCFG_OUTPUT_FORCE_LINK_SPEED_200GB \
14193 /* 10Mb link speed */
14194 #define HWRM_PORT_PHY_QCFG_OUTPUT_FORCE_LINK_SPEED_10MB \
14196 #define HWRM_PORT_PHY_QCFG_OUTPUT_FORCE_LINK_SPEED_LAST \
14197 HWRM_PORT_PHY_QCFG_OUTPUT_FORCE_LINK_SPEED_10MB
14198 /* Current setting of auto negotiation mode. */
14200 /* Disable autoneg or autoneg disabled. No speeds are selected. */
14201 #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_MODE_NONE UINT32_C(0x0)
14202 /* Select all possible speeds for autoneg mode. */
14203 #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_MODE_ALL_SPEEDS UINT32_C(0x1)
14205 * Select only the auto_link_speed speed for autoneg mode. This mode has
14206 * been DEPRECATED. An HWRM client should not use this mode.
14208 #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_MODE_ONE_SPEED UINT32_C(0x2)
14210 * Select the auto_link_speed or any speed below that speed for autoneg.
14211 * This mode has been DEPRECATED. An HWRM client should not use this mode.
14213 #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_MODE_ONE_OR_BELOW UINT32_C(0x3)
14215 * Select the speeds based on the corresponding link speed mask value
14216 * that is provided.
14218 #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_MODE_SPEED_MASK UINT32_C(0x4)
14219 #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_MODE_LAST \
14220 HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_MODE_SPEED_MASK
14222 * Current setting of pause autonegotiation.
14223 * Move autoneg_pause flag here.
14225 uint8_t auto_pause;
14227 * When this bit is '1', Generation of tx pause messages
14228 * has been requested. Disabled otherwise.
14230 #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_PAUSE_TX \
14233 * When this bit is '1', Reception of rx pause messages
14234 * has been requested. Disabled otherwise.
14236 #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_PAUSE_RX \
14239 * When set to 1, the advertisement of pause is enabled.
14241 * # When the auto_mode is not set to none and this flag is
14242 * set to 1, then the auto_pause bits on this port are being
14243 * advertised and autoneg pause results are being interpreted.
14244 * # When the auto_mode is not set to none and this
14245 * flag is set to 0, the pause is forced as indicated in
14246 * force_pause, and also advertised as auto_pause bits, but
14247 * the autoneg results are not interpreted since the pause
14248 * configuration is being forced.
14249 * # When the auto_mode is set to none and this flag is set to
14250 * 1, auto_pause bits should be ignored and should be set to 0.
14252 #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_PAUSE_AUTONEG_PAUSE \
14255 * Current setting for auto_link_speed. This field is only
14256 * valid when auto_mode is set to "one_speed" or "one_or_below".
14258 uint16_t auto_link_speed;
14259 /* 100Mb link speed */
14260 #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_100MB UINT32_C(0x1)
14261 /* 1Gb link speed */
14262 #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_1GB UINT32_C(0xa)
14263 /* 2Gb link speed */
14264 #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_2GB UINT32_C(0x14)
14265 /* 25Gb link speed */
14266 #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_2_5GB UINT32_C(0x19)
14267 /* 10Gb link speed */
14268 #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_10GB UINT32_C(0x64)
14269 /* 20Mb link speed */
14270 #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_20GB UINT32_C(0xc8)
14271 /* 25Gb link speed */
14272 #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_25GB UINT32_C(0xfa)
14273 /* 40Gb link speed */
14274 #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_40GB UINT32_C(0x190)
14275 /* 50Gb link speed */
14276 #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_50GB UINT32_C(0x1f4)
14277 /* 100Gb link speed */
14278 #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_100GB UINT32_C(0x3e8)
14279 /* 200Gb link speed */
14280 #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_200GB UINT32_C(0x7d0)
14281 /* 10Mb link speed */
14282 #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_10MB \
14284 #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_LAST \
14285 HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_10MB
14287 * Current setting for auto_link_speed_mask that is used to
14288 * advertise speeds during autonegotiation.
14289 * This field is only valid when auto_mode is set to "mask".
14290 * The speeds specified in this field shall be a subset of
14291 * supported speeds on this port.
14293 uint16_t auto_link_speed_mask;
14294 /* 100Mb link speed (Half-duplex) */
14295 #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_MASK_100MBHD \
14297 /* 100Mb link speed (Full-duplex) */
14298 #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_MASK_100MB \
14300 /* 1Gb link speed (Half-duplex) */
14301 #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_MASK_1GBHD \
14303 /* 1Gb link speed (Full-duplex) */
14304 #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_MASK_1GB \
14306 /* 2Gb link speed */
14307 #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_MASK_2GB \
14309 /* 25Gb link speed */
14310 #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_MASK_2_5GB \
14312 /* 10Gb link speed */
14313 #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_MASK_10GB \
14315 /* 20Gb link speed */
14316 #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_MASK_20GB \
14318 /* 25Gb link speed */
14319 #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_MASK_25GB \
14321 /* 40Gb link speed */
14322 #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_MASK_40GB \
14324 /* 50Gb link speed */
14325 #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_MASK_50GB \
14327 /* 100Gb link speed */
14328 #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_MASK_100GB \
14330 /* 10Mb link speed (Half-duplex) */
14331 #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_MASK_10MBHD \
14333 /* 10Mb link speed (Full-duplex) */
14334 #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_MASK_10MB \
14336 /* 200Gb link speed */
14337 #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_MASK_200GB \
14339 /* Current setting for wirespeed. */
14341 /* Wirespeed feature is disabled. */
14342 #define HWRM_PORT_PHY_QCFG_OUTPUT_WIRESPEED_OFF UINT32_C(0x0)
14343 /* Wirespeed feature is enabled. */
14344 #define HWRM_PORT_PHY_QCFG_OUTPUT_WIRESPEED_ON UINT32_C(0x1)
14345 #define HWRM_PORT_PHY_QCFG_OUTPUT_WIRESPEED_LAST \
14346 HWRM_PORT_PHY_QCFG_OUTPUT_WIRESPEED_ON
14347 /* Current setting for loopback. */
14349 /* No loopback is selected. Normal operation. */
14350 #define HWRM_PORT_PHY_QCFG_OUTPUT_LPBK_NONE UINT32_C(0x0)
14352 * The HW will be configured with local loopback such that
14353 * host data is sent back to the host without modification.
14355 #define HWRM_PORT_PHY_QCFG_OUTPUT_LPBK_LOCAL UINT32_C(0x1)
14357 * The HW will be configured with remote loopback such that
14358 * port logic will send packets back out the transmitter that
14361 #define HWRM_PORT_PHY_QCFG_OUTPUT_LPBK_REMOTE UINT32_C(0x2)
14363 * The HW will be configured with external loopback such that
14364 * host data is sent on the transmitter and based on the external
14365 * loopback connection the data will be received without modification.
14367 #define HWRM_PORT_PHY_QCFG_OUTPUT_LPBK_EXTERNAL UINT32_C(0x3)
14368 #define HWRM_PORT_PHY_QCFG_OUTPUT_LPBK_LAST \
14369 HWRM_PORT_PHY_QCFG_OUTPUT_LPBK_EXTERNAL
14371 * Current setting of forced pause.
14372 * When the pause configuration is not being forced, then
14373 * this value shall be set to 0.
14375 uint8_t force_pause;
14377 * When this bit is '1', Generation of tx pause messages
14378 * is supported. Disabled otherwise.
14380 #define HWRM_PORT_PHY_QCFG_OUTPUT_FORCE_PAUSE_TX UINT32_C(0x1)
14382 * When this bit is '1', Reception of rx pause messages
14383 * is supported. Disabled otherwise.
14385 #define HWRM_PORT_PHY_QCFG_OUTPUT_FORCE_PAUSE_RX UINT32_C(0x2)
14387 * This value indicates the current status of the optics module on
14390 uint8_t module_status;
14391 /* Module is inserted and accepted */
14392 #define HWRM_PORT_PHY_QCFG_OUTPUT_MODULE_STATUS_NONE \
14394 /* Module is rejected and transmit side Laser is disabled. */
14395 #define HWRM_PORT_PHY_QCFG_OUTPUT_MODULE_STATUS_DISABLETX \
14397 /* Module mismatch warning. */
14398 #define HWRM_PORT_PHY_QCFG_OUTPUT_MODULE_STATUS_WARNINGMSG \
14400 /* Module is rejected and powered down. */
14401 #define HWRM_PORT_PHY_QCFG_OUTPUT_MODULE_STATUS_PWRDOWN \
14403 /* Module is not inserted. */
14404 #define HWRM_PORT_PHY_QCFG_OUTPUT_MODULE_STATUS_NOTINSERTED \
14406 /* Module is powered down because of over current fault. */
14407 #define HWRM_PORT_PHY_QCFG_OUTPUT_MODULE_STATUS_CURRENTFAULT \
14409 /* Module status is not applicable. */
14410 #define HWRM_PORT_PHY_QCFG_OUTPUT_MODULE_STATUS_NOTAPPLICABLE \
14412 #define HWRM_PORT_PHY_QCFG_OUTPUT_MODULE_STATUS_LAST \
14413 HWRM_PORT_PHY_QCFG_OUTPUT_MODULE_STATUS_NOTAPPLICABLE
14414 /* Current setting for preemphasis. */
14415 uint32_t preemphasis;
14416 /* This field represents the major version of the PHY. */
14418 /* This field represents the minor version of the PHY. */
14420 /* This field represents the build version of the PHY. */
14422 /* This value represents a PHY type. */
14425 #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_UNKNOWN \
14428 #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_BASECR \
14430 /* BASE-KR4 (Deprecated) */
14431 #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_BASEKR4 \
14434 #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_BASELR \
14437 #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_BASESR \
14439 /* BASE-KR2 (Deprecated) */
14440 #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_BASEKR2 \
14443 #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_BASEKX \
14446 #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_BASEKR \
14449 #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_BASET \
14451 /* EEE capable BASE-T */
14452 #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_BASETE \
14454 /* SGMII connected external PHY */
14455 #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_SGMIIEXTPHY \
14457 /* 25G_BASECR_CA_L */
14458 #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_25G_BASECR_CA_L \
14460 /* 25G_BASECR_CA_S */
14461 #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_25G_BASECR_CA_S \
14463 /* 25G_BASECR_CA_N */
14464 #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_25G_BASECR_CA_N \
14467 #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_25G_BASESR \
14470 #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_100G_BASECR4 \
14473 #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_100G_BASESR4 \
14476 #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_100G_BASELR4 \
14479 #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_100G_BASEER4 \
14481 /* 100G_BASESR10 */
14482 #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_100G_BASESR10 \
14485 #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_40G_BASECR4 \
14488 #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_40G_BASESR4 \
14491 #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_40G_BASELR4 \
14494 #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_40G_BASEER4 \
14496 /* 40G_ACTIVE_CABLE */
14497 #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_40G_ACTIVE_CABLE \
14500 #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_1G_BASET \
14503 #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_1G_BASESX \
14506 #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_1G_BASECX \
14509 #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_200G_BASECR4 \
14512 #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_200G_BASESR4 \
14515 #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_200G_BASELR4 \
14518 #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_200G_BASEER4 \
14520 #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_LAST \
14521 HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_200G_BASEER4
14522 /* This value represents a media type. */
14523 uint8_t media_type;
14525 #define HWRM_PORT_PHY_QCFG_OUTPUT_MEDIA_TYPE_UNKNOWN UINT32_C(0x0)
14527 #define HWRM_PORT_PHY_QCFG_OUTPUT_MEDIA_TYPE_TP UINT32_C(0x1)
14528 /* Direct Attached Copper */
14529 #define HWRM_PORT_PHY_QCFG_OUTPUT_MEDIA_TYPE_DAC UINT32_C(0x2)
14531 #define HWRM_PORT_PHY_QCFG_OUTPUT_MEDIA_TYPE_FIBRE UINT32_C(0x3)
14532 #define HWRM_PORT_PHY_QCFG_OUTPUT_MEDIA_TYPE_LAST \
14533 HWRM_PORT_PHY_QCFG_OUTPUT_MEDIA_TYPE_FIBRE
14534 /* This value represents a transceiver type. */
14535 uint8_t xcvr_pkg_type;
14536 /* PHY and MAC are in the same package */
14537 #define HWRM_PORT_PHY_QCFG_OUTPUT_XCVR_PKG_TYPE_XCVR_INTERNAL \
14539 /* PHY and MAC are in different packages */
14540 #define HWRM_PORT_PHY_QCFG_OUTPUT_XCVR_PKG_TYPE_XCVR_EXTERNAL \
14542 #define HWRM_PORT_PHY_QCFG_OUTPUT_XCVR_PKG_TYPE_LAST \
14543 HWRM_PORT_PHY_QCFG_OUTPUT_XCVR_PKG_TYPE_XCVR_EXTERNAL
14544 uint8_t eee_config_phy_addr;
14545 /* This field represents PHY address. */
14546 #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_ADDR_MASK \
14548 #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_ADDR_SFT 0
14550 * This field represents flags related to EEE configuration.
14551 * These EEE configuration flags are valid only when the
14552 * auto_mode is not set to none (in other words autonegotiation
14555 #define HWRM_PORT_PHY_QCFG_OUTPUT_EEE_CONFIG_MASK \
14557 #define HWRM_PORT_PHY_QCFG_OUTPUT_EEE_CONFIG_SFT 5
14559 * When set to 1, Energy Efficient Ethernet (EEE) mode is enabled.
14560 * Speeds for autoneg with EEE mode enabled
14561 * are based on eee_link_speed_mask.
14563 #define HWRM_PORT_PHY_QCFG_OUTPUT_EEE_CONFIG_EEE_ENABLED \
14566 * This flag is valid only when eee_enabled is set to 1.
14568 * # If eee_enabled is set to 0, then EEE mode is disabled
14569 * and this flag shall be ignored.
14570 * # If eee_enabled is set to 1 and this flag is set to 1,
14571 * then Energy Efficient Ethernet (EEE) mode is enabled
14573 * # If eee_enabled is set to 1 and this flag is set to 0,
14574 * then Energy Efficient Ethernet (EEE) mode is enabled
14575 * but is currently not in use.
14577 #define HWRM_PORT_PHY_QCFG_OUTPUT_EEE_CONFIG_EEE_ACTIVE \
14580 * This flag is valid only when eee_enabled is set to 1.
14582 * # If eee_enabled is set to 0, then EEE mode is disabled
14583 * and this flag shall be ignored.
14584 * # If eee_enabled is set to 1 and this flag is set to 1,
14585 * then Energy Efficient Ethernet (EEE) mode is enabled
14586 * and TX LPI is enabled.
14587 * # If eee_enabled is set to 1 and this flag is set to 0,
14588 * then Energy Efficient Ethernet (EEE) mode is enabled
14589 * but TX LPI is disabled.
14591 #define HWRM_PORT_PHY_QCFG_OUTPUT_EEE_CONFIG_EEE_TX_LPI \
14594 * When set to 1, the parallel detection is used to determine
14595 * the speed of the link partner.
14597 * Parallel detection is used when a autonegotiation capable
14598 * device is connected to a link parter that is not capable
14599 * of autonegotiation.
14601 uint8_t parallel_detect;
14603 * When set to 1, the parallel detection is used to determine
14604 * the speed of the link partner.
14606 * Parallel detection is used when a autonegotiation capable
14607 * device is connected to a link parter that is not capable
14608 * of autonegotiation.
14610 #define HWRM_PORT_PHY_QCFG_OUTPUT_PARALLEL_DETECT UINT32_C(0x1)
14612 * The advertised speeds for the port by the link partner.
14613 * Each advertised speed will be set to '1'.
14615 uint16_t link_partner_adv_speeds;
14616 /* 100Mb link speed (Half-duplex) */
14617 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_SPEEDS_100MBHD \
14619 /* 100Mb link speed (Full-duplex) */
14620 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_SPEEDS_100MB \
14622 /* 1Gb link speed (Half-duplex) */
14623 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_SPEEDS_1GBHD \
14625 /* 1Gb link speed (Full-duplex) */
14626 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_SPEEDS_1GB \
14628 /* 2Gb link speed */
14629 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_SPEEDS_2GB \
14631 /* 25Gb link speed */
14632 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_SPEEDS_2_5GB \
14634 /* 10Gb link speed */
14635 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_SPEEDS_10GB \
14637 /* 20Gb link speed */
14638 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_SPEEDS_20GB \
14640 /* 25Gb link speed */
14641 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_SPEEDS_25GB \
14643 /* 40Gb link speed */
14644 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_SPEEDS_40GB \
14646 /* 50Gb link speed */
14647 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_SPEEDS_50GB \
14649 /* 100Gb link speed */
14650 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_SPEEDS_100GB \
14652 /* 10Mb link speed (Half-duplex) */
14653 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_SPEEDS_10MBHD \
14655 /* 10Mb link speed (Full-duplex) */
14656 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_SPEEDS_10MB \
14659 * The advertised autoneg for the port by the link partner.
14660 * This field is deprecated and should be set to 0.
14662 uint8_t link_partner_adv_auto_mode;
14663 /* Disable autoneg or autoneg disabled. No speeds are selected. */
14664 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_AUTO_MODE_NONE \
14666 /* Select all possible speeds for autoneg mode. */
14667 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_AUTO_MODE_ALL_SPEEDS \
14670 * Select only the auto_link_speed speed for autoneg mode. This mode has
14671 * been DEPRECATED. An HWRM client should not use this mode.
14673 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_AUTO_MODE_ONE_SPEED \
14676 * Select the auto_link_speed or any speed below that speed for autoneg.
14677 * This mode has been DEPRECATED. An HWRM client should not use this mode.
14679 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_AUTO_MODE_ONE_OR_BELOW \
14682 * Select the speeds based on the corresponding link speed mask value
14683 * that is provided.
14685 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_AUTO_MODE_SPEED_MASK \
14687 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_AUTO_MODE_LAST \
14688 HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_AUTO_MODE_SPEED_MASK
14689 /* The advertised pause settings on the port by the link partner. */
14690 uint8_t link_partner_adv_pause;
14692 * When this bit is '1', Generation of tx pause messages
14693 * is supported. Disabled otherwise.
14695 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_PAUSE_TX \
14698 * When this bit is '1', Reception of rx pause messages
14699 * is supported. Disabled otherwise.
14701 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_PAUSE_RX \
14704 * Current setting for link speed mask that is used to
14705 * advertise speeds during autonegotiation when EEE is enabled.
14706 * This field is valid only when eee_enabled flags is set to 1.
14707 * The speeds specified in this field shall be a subset of
14708 * speeds specified in auto_link_speed_mask.
14710 uint16_t adv_eee_link_speed_mask;
14712 #define HWRM_PORT_PHY_QCFG_OUTPUT_ADV_EEE_LINK_SPEED_MASK_RSVD1 \
14714 /* 100Mb link speed (Full-duplex) */
14715 #define HWRM_PORT_PHY_QCFG_OUTPUT_ADV_EEE_LINK_SPEED_MASK_100MB \
14718 #define HWRM_PORT_PHY_QCFG_OUTPUT_ADV_EEE_LINK_SPEED_MASK_RSVD2 \
14720 /* 1Gb link speed (Full-duplex) */
14721 #define HWRM_PORT_PHY_QCFG_OUTPUT_ADV_EEE_LINK_SPEED_MASK_1GB \
14724 #define HWRM_PORT_PHY_QCFG_OUTPUT_ADV_EEE_LINK_SPEED_MASK_RSVD3 \
14727 #define HWRM_PORT_PHY_QCFG_OUTPUT_ADV_EEE_LINK_SPEED_MASK_RSVD4 \
14729 /* 10Gb link speed */
14730 #define HWRM_PORT_PHY_QCFG_OUTPUT_ADV_EEE_LINK_SPEED_MASK_10GB \
14733 * Current setting for link speed mask that is advertised by
14734 * the link partner when EEE is enabled.
14735 * This field is valid only when eee_enabled flags is set to 1.
14737 uint16_t link_partner_adv_eee_link_speed_mask;
14739 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_EEE_LINK_SPEED_MASK_RSVD1 \
14741 /* 100Mb link speed (Full-duplex) */
14742 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_EEE_LINK_SPEED_MASK_100MB \
14745 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_EEE_LINK_SPEED_MASK_RSVD2 \
14747 /* 1Gb link speed (Full-duplex) */
14748 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_EEE_LINK_SPEED_MASK_1GB \
14751 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_EEE_LINK_SPEED_MASK_RSVD3 \
14754 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_EEE_LINK_SPEED_MASK_RSVD4 \
14756 /* 10Gb link speed */
14757 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_EEE_LINK_SPEED_MASK_10GB \
14759 uint32_t xcvr_identifier_type_tx_lpi_timer;
14761 * Current setting of TX LPI timer in microseconds.
14762 * This field is valid only when_eee_enabled flag is set to 1
14763 * and tx_lpi_enabled is set to 1.
14765 #define HWRM_PORT_PHY_QCFG_OUTPUT_TX_LPI_TIMER_MASK \
14767 #define HWRM_PORT_PHY_QCFG_OUTPUT_TX_LPI_TIMER_SFT 0
14768 /* This value represents transceiver identifier type. */
14769 #define HWRM_PORT_PHY_QCFG_OUTPUT_XCVR_IDENTIFIER_TYPE_MASK \
14770 UINT32_C(0xff000000)
14771 #define HWRM_PORT_PHY_QCFG_OUTPUT_XCVR_IDENTIFIER_TYPE_SFT 24
14773 #define HWRM_PORT_PHY_QCFG_OUTPUT_XCVR_IDENTIFIER_TYPE_UNKNOWN \
14774 (UINT32_C(0x0) << 24)
14775 /* SFP/SFP+/SFP28 */
14776 #define HWRM_PORT_PHY_QCFG_OUTPUT_XCVR_IDENTIFIER_TYPE_SFP \
14777 (UINT32_C(0x3) << 24)
14779 #define HWRM_PORT_PHY_QCFG_OUTPUT_XCVR_IDENTIFIER_TYPE_QSFP \
14780 (UINT32_C(0xc) << 24)
14782 #define HWRM_PORT_PHY_QCFG_OUTPUT_XCVR_IDENTIFIER_TYPE_QSFPPLUS \
14783 (UINT32_C(0xd) << 24)
14785 #define HWRM_PORT_PHY_QCFG_OUTPUT_XCVR_IDENTIFIER_TYPE_QSFP28 \
14786 (UINT32_C(0x11) << 24)
14787 #define HWRM_PORT_PHY_QCFG_OUTPUT_XCVR_IDENTIFIER_TYPE_LAST \
14788 HWRM_PORT_PHY_QCFG_OUTPUT_XCVR_IDENTIFIER_TYPE_QSFP28
14790 * This value represents the current configuration of
14791 * Forward Error Correction (FEC) on the port.
14795 * When set to 1, then FEC is not supported on this port. If this flag
14796 * is set to 1, then all other FEC configuration flags shall be ignored.
14797 * When set to 0, then FEC is supported as indicated by other
14798 * configuration flags.
14799 * If no cable is attached and the HWRM does not yet know the FEC
14800 * capability, then the HWRM shall set this flag to 1 when reporting
14803 #define HWRM_PORT_PHY_QCFG_OUTPUT_FEC_CFG_FEC_NONE_SUPPORTED \
14806 * When set to 1, then FEC autonegotiation is supported on this port.
14807 * When set to 0, then FEC autonegotiation is not supported on this port.
14809 #define HWRM_PORT_PHY_QCFG_OUTPUT_FEC_CFG_FEC_AUTONEG_SUPPORTED \
14812 * When set to 1, then FEC autonegotiation is enabled on this port.
14813 * When set to 0, then FEC autonegotiation is disabled if supported.
14814 * This flag should be ignored if FEC autonegotiation is not supported on this port.
14816 #define HWRM_PORT_PHY_QCFG_OUTPUT_FEC_CFG_FEC_AUTONEG_ENABLED \
14819 * When set to 1, then FEC CLAUSE 74 (Fire Code) is supported on this port.
14820 * When set to 0, then FEC CLAUSE 74 (Fire Code) is not supported on this port.
14822 #define HWRM_PORT_PHY_QCFG_OUTPUT_FEC_CFG_FEC_CLAUSE74_SUPPORTED \
14825 * When set to 1, then FEC CLAUSE 74 (Fire Code) is enabled on this port.
14826 * When set to 0, then FEC CLAUSE 74 (Fire Code) is disabled if supported.
14827 * This flag should be ignored if FEC CLAUSE 74 is not supported on this port.
14829 #define HWRM_PORT_PHY_QCFG_OUTPUT_FEC_CFG_FEC_CLAUSE74_ENABLED \
14832 * When set to 1, then FEC CLAUSE 91 (Reed Solomon) is supported on this port.
14833 * When set to 0, then FEC CLAUSE 91 (Reed Solomon) is not supported on this port.
14835 #define HWRM_PORT_PHY_QCFG_OUTPUT_FEC_CFG_FEC_CLAUSE91_SUPPORTED \
14838 * When set to 1, then FEC CLAUSE 91 (Reed Solomon) is enabled on this port.
14839 * When set to 0, then FEC CLAUSE 91 (Reed Solomon) is disabled if supported.
14840 * This flag should be ignored if FEC CLAUSE 91 is not supported on this port.
14842 #define HWRM_PORT_PHY_QCFG_OUTPUT_FEC_CFG_FEC_CLAUSE91_ENABLED \
14845 * This value is indicates the duplex of the current
14846 * connection state.
14848 uint8_t duplex_state;
14849 /* Half Duplex connection. */
14850 #define HWRM_PORT_PHY_QCFG_OUTPUT_DUPLEX_STATE_HALF UINT32_C(0x0)
14851 /* Full duplex connection. */
14852 #define HWRM_PORT_PHY_QCFG_OUTPUT_DUPLEX_STATE_FULL UINT32_C(0x1)
14853 #define HWRM_PORT_PHY_QCFG_OUTPUT_DUPLEX_STATE_LAST \
14854 HWRM_PORT_PHY_QCFG_OUTPUT_DUPLEX_STATE_FULL
14855 /* Option flags fields. */
14856 uint8_t option_flags;
14857 /* When this bit is '1', Media auto detect is enabled. */
14858 #define HWRM_PORT_PHY_QCFG_OUTPUT_OPTION_FLAGS_MEDIA_AUTO_DETECT \
14861 * Up to 16 bytes of null padded ASCII string representing
14863 * If the string is set to null, then the vendor name is not
14866 char phy_vendor_name[16];
14868 * Up to 16 bytes of null padded ASCII string that
14869 * identifies vendor specific part number of the PHY.
14870 * If the string is set to null, then the vendor specific
14871 * part number is not available.
14873 char phy_vendor_partnumber[16];
14874 uint8_t unused_2[7];
14876 * This field is used in Output records to indicate that the output
14877 * is completely written to RAM. This field should be read as '1'
14878 * to indicate that the output has been completely written.
14879 * When writing a command completion or response to an internal processor,
14880 * the order of writes has to be such that this field is written last.
14885 /*********************
14886 * hwrm_port_mac_cfg *
14887 *********************/
14890 /* hwrm_port_mac_cfg_input (size:384b/48B) */
14891 struct hwrm_port_mac_cfg_input {
14892 /* The HWRM command request type. */
14895 * The completion ring to send the completion event on. This should
14896 * be the NQ ID returned from the `nq_alloc` HWRM command.
14898 uint16_t cmpl_ring;
14900 * The sequence ID is used by the driver for tracking multiple
14901 * commands. This ID is treated as opaque data by the firmware and
14902 * the value is returned in the `hwrm_resp_hdr` upon completion.
14906 * The target ID of the command:
14907 * * 0x0-0xFFF8 - The function ID
14908 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
14909 * * 0xFFFD - Reserved for user-space HWRM interface
14912 uint16_t target_id;
14914 * A physical address pointer pointing to a host buffer that the
14915 * command's response data will be written. This can be either a host
14916 * physical address (HPA) or a guest physical address (GPA) and must
14917 * point to a physically contiguous block of memory.
14919 uint64_t resp_addr;
14921 * In this field, there are a number of CoS mappings related flags
14922 * that are used to configure CoS mappings and their corresponding
14923 * priorities in the hardware.
14924 * For the priorities of CoS mappings, the HWRM uses the following
14925 * priority order (high to low) by default:
14928 * # tunnel_vlan_pri
14931 * A subset of CoS mappings can be enabled.
14932 * If a priority is not specified for an enabled CoS mapping, the
14933 * priority will be assigned in the above order for the enabled CoS
14934 * mappings. For example, if vlan_pri and ip_dscp CoS mappings are
14935 * enabled and their priorities are not specified, the following
14936 * priority order (high to low) will be used by the HWRM:
14941 * vlan_pri CoS mapping together with default CoS with lower priority
14942 * are enabled by default by the HWRM.
14946 * When this bit is '1', this command will configure
14947 * the MAC to match the current link state of the PHY.
14948 * If the link is not established on the PHY, then this
14949 * bit has no effect.
14951 #define HWRM_PORT_MAC_CFG_INPUT_FLAGS_MATCH_LINK \
14954 * When this bit is set to '1', the inner VLAN PRI to CoS mapping
14955 * is requested to be enabled.
14957 #define HWRM_PORT_MAC_CFG_INPUT_FLAGS_VLAN_PRI2COS_ENABLE \
14960 * When this bit is set to '1', tunnel VLAN PRI field to
14961 * CoS mapping is requested to be enabled.
14963 #define HWRM_PORT_MAC_CFG_INPUT_FLAGS_TUNNEL_PRI2COS_ENABLE \
14966 * When this bit is set to '1', the IP DSCP to CoS mapping is
14967 * requested to be enabled.
14969 #define HWRM_PORT_MAC_CFG_INPUT_FLAGS_IP_DSCP2COS_ENABLE \
14972 * When this bit is '1', the HWRM is requested to
14973 * enable timestamp capture capability on the receive side
14976 #define HWRM_PORT_MAC_CFG_INPUT_FLAGS_PTP_RX_TS_CAPTURE_ENABLE \
14979 * When this bit is '1', the HWRM is requested to
14980 * disable timestamp capture capability on the receive side
14983 #define HWRM_PORT_MAC_CFG_INPUT_FLAGS_PTP_RX_TS_CAPTURE_DISABLE \
14986 * When this bit is '1', the HWRM is requested to
14987 * enable timestamp capture capability on the transmit side
14990 #define HWRM_PORT_MAC_CFG_INPUT_FLAGS_PTP_TX_TS_CAPTURE_ENABLE \
14993 * When this bit is '1', the HWRM is requested to
14994 * disable timestamp capture capability on the transmit side
14997 #define HWRM_PORT_MAC_CFG_INPUT_FLAGS_PTP_TX_TS_CAPTURE_DISABLE \
15000 * When this bit is '1', the Out-Of-Box WoL is requested to
15001 * be enabled on this port.
15003 #define HWRM_PORT_MAC_CFG_INPUT_FLAGS_OOB_WOL_ENABLE \
15006 * When this bit is '1', the Out-Of-Box WoL is requested to
15007 * be disabled on this port.
15009 #define HWRM_PORT_MAC_CFG_INPUT_FLAGS_OOB_WOL_DISABLE \
15012 * When this bit is set to '1', the inner VLAN PRI to CoS mapping
15013 * is requested to be disabled.
15015 #define HWRM_PORT_MAC_CFG_INPUT_FLAGS_VLAN_PRI2COS_DISABLE \
15018 * When this bit is set to '1', tunnel VLAN PRI field to
15019 * CoS mapping is requested to be disabled.
15021 #define HWRM_PORT_MAC_CFG_INPUT_FLAGS_TUNNEL_PRI2COS_DISABLE \
15024 * When this bit is set to '1', the IP DSCP to CoS mapping is
15025 * requested to be disabled.
15027 #define HWRM_PORT_MAC_CFG_INPUT_FLAGS_IP_DSCP2COS_DISABLE \
15030 * When this bit is set to '1', and the ptp_tx_ts_capture_enable
15031 * bit is set, then the device uses one step Tx timestamping.
15032 * This bit is temporary and used for experimental purposes.
15034 #define HWRM_PORT_MAC_CFG_INPUT_FLAGS_PTP_ONE_STEP_TX_TS \
15038 * This bit must be '1' for the ipg field to be
15041 #define HWRM_PORT_MAC_CFG_INPUT_ENABLES_IPG \
15044 * This bit must be '1' for the lpbk field to be
15047 #define HWRM_PORT_MAC_CFG_INPUT_ENABLES_LPBK \
15050 * This bit must be '1' for the vlan_pri2cos_map_pri field to be
15053 #define HWRM_PORT_MAC_CFG_INPUT_ENABLES_VLAN_PRI2COS_MAP_PRI \
15056 * This bit must be '1' for the tunnel_pri2cos_map_pri field to be
15059 #define HWRM_PORT_MAC_CFG_INPUT_ENABLES_TUNNEL_PRI2COS_MAP_PRI \
15062 * This bit must be '1' for the dscp2cos_map_pri field to be
15065 #define HWRM_PORT_MAC_CFG_INPUT_ENABLES_DSCP2COS_MAP_PRI \
15068 * This bit must be '1' for the rx_ts_capture_ptp_msg_type field to be
15071 #define HWRM_PORT_MAC_CFG_INPUT_ENABLES_RX_TS_CAPTURE_PTP_MSG_TYPE \
15074 * This bit must be '1' for the tx_ts_capture_ptp_msg_type field to be
15077 #define HWRM_PORT_MAC_CFG_INPUT_ENABLES_TX_TS_CAPTURE_PTP_MSG_TYPE \
15080 * This bit must be '1' for the cos_field_cfg field to be
15083 #define HWRM_PORT_MAC_CFG_INPUT_ENABLES_COS_FIELD_CFG \
15086 * This bit must be '1' for the ptp_freq_adj_ppb field to be
15089 #define HWRM_PORT_MAC_CFG_INPUT_ENABLES_PTP_FREQ_ADJ_PPB \
15091 /* Port ID of port that is to be configured. */
15094 * This value is used to configure the minimum IPG that will
15095 * be sent between packets by this port.
15098 /* This value controls the loopback setting for the MAC. */
15100 /* No loopback is selected. Normal operation. */
15101 #define HWRM_PORT_MAC_CFG_INPUT_LPBK_NONE UINT32_C(0x0)
15103 * The HW will be configured with local loopback such that
15104 * host data is sent back to the host without modification.
15106 #define HWRM_PORT_MAC_CFG_INPUT_LPBK_LOCAL UINT32_C(0x1)
15108 * The HW will be configured with remote loopback such that
15109 * port logic will send packets back out the transmitter that
15112 #define HWRM_PORT_MAC_CFG_INPUT_LPBK_REMOTE UINT32_C(0x2)
15113 #define HWRM_PORT_MAC_CFG_INPUT_LPBK_LAST \
15114 HWRM_PORT_MAC_CFG_INPUT_LPBK_REMOTE
15116 * This value controls the priority setting of VLAN PRI to CoS
15117 * mapping based on VLAN Tags of inner packet headers of
15118 * tunneled packets or packet headers of non-tunneled packets.
15120 * # Each XXX_pri variable shall have a unique priority value
15121 * when it is being specified.
15122 * # When comparing priorities of mappings, higher value
15123 * indicates higher priority.
15124 * For example, a value of 0-3 is returned where 0 is being
15125 * the lowest priority and 3 is being the highest priority.
15127 uint8_t vlan_pri2cos_map_pri;
15128 /* Reserved field. */
15131 * This value controls the priority setting of VLAN PRI to CoS
15132 * mapping based on VLAN Tags of tunneled header.
15133 * This mapping only applies when tunneled headers
15136 * # Each XXX_pri variable shall have a unique priority value
15137 * when it is being specified.
15138 * # When comparing priorities of mappings, higher value
15139 * indicates higher priority.
15140 * For example, a value of 0-3 is returned where 0 is being
15141 * the lowest priority and 3 is being the highest priority.
15143 uint8_t tunnel_pri2cos_map_pri;
15145 * This value controls the priority setting of IP DSCP to CoS
15146 * mapping based on inner IP header of tunneled packets or
15147 * IP header of non-tunneled packets.
15149 * # Each XXX_pri variable shall have a unique priority value
15150 * when it is being specified.
15151 * # When comparing priorities of mappings, higher value
15152 * indicates higher priority.
15153 * For example, a value of 0-3 is returned where 0 is being
15154 * the lowest priority and 3 is being the highest priority.
15156 uint8_t dscp2pri_map_pri;
15158 * This is a 16-bit bit mask that is used to request a
15159 * specific configuration of time stamp capture of PTP messages
15160 * on the receive side of this port.
15161 * This field shall be ignored if the ptp_rx_ts_capture_enable
15162 * flag is not set in this command.
15163 * Otherwise, if bit 'i' is set, then the HWRM is being
15164 * requested to configure the receive side of the port to
15165 * capture the time stamp of every received PTP message
15166 * with messageType field value set to i.
15168 uint16_t rx_ts_capture_ptp_msg_type;
15170 * This is a 16-bit bit mask that is used to request a
15171 * specific configuration of time stamp capture of PTP messages
15172 * on the transmit side of this port.
15173 * This field shall be ignored if the ptp_tx_ts_capture_enable
15174 * flag is not set in this command.
15175 * Otherwise, if bit 'i' is set, then the HWRM is being
15176 * requested to configure the transmit side of the port to
15177 * capture the time stamp of every transmitted PTP message
15178 * with messageType field value set to i.
15180 uint16_t tx_ts_capture_ptp_msg_type;
15181 /* Configuration of CoS fields. */
15182 uint8_t cos_field_cfg;
15184 #define HWRM_PORT_MAC_CFG_INPUT_COS_FIELD_CFG_RSVD1 \
15187 * This field is used to specify selection of VLAN PRI value
15188 * based on whether one or two VLAN Tags are present in
15189 * the inner packet headers of tunneled packets or
15190 * non-tunneled packets.
15191 * This field is valid only if inner VLAN PRI to CoS mapping
15193 * If VLAN PRI to CoS mapping is not enabled, then this
15194 * field shall be ignored.
15196 #define HWRM_PORT_MAC_CFG_INPUT_COS_FIELD_CFG_VLAN_PRI_SEL_MASK \
15198 #define HWRM_PORT_MAC_CFG_INPUT_COS_FIELD_CFG_VLAN_PRI_SEL_SFT \
15201 * Select inner VLAN PRI when 1 or 2 VLAN Tags are
15202 * present in the inner packet headers
15204 #define HWRM_PORT_MAC_CFG_INPUT_COS_FIELD_CFG_VLAN_PRI_SEL_INNERMOST \
15205 (UINT32_C(0x0) << 1)
15207 * Select outer VLAN Tag PRI when 2 VLAN Tags are
15208 * present in the inner packet headers.
15209 * No VLAN PRI shall be selected for this configuration
15210 * if only one VLAN Tag is present in the inner
15213 #define HWRM_PORT_MAC_CFG_INPUT_COS_FIELD_CFG_VLAN_PRI_SEL_OUTER \
15214 (UINT32_C(0x1) << 1)
15216 * Select outermost VLAN PRI when 1 or 2 VLAN Tags
15217 * are present in the inner packet headers
15219 #define HWRM_PORT_MAC_CFG_INPUT_COS_FIELD_CFG_VLAN_PRI_SEL_OUTERMOST \
15220 (UINT32_C(0x2) << 1)
15222 #define HWRM_PORT_MAC_CFG_INPUT_COS_FIELD_CFG_VLAN_PRI_SEL_UNSPECIFIED \
15223 (UINT32_C(0x3) << 1)
15224 #define HWRM_PORT_MAC_CFG_INPUT_COS_FIELD_CFG_VLAN_PRI_SEL_LAST \
15225 HWRM_PORT_MAC_CFG_INPUT_COS_FIELD_CFG_VLAN_PRI_SEL_UNSPECIFIED
15227 * This field is used to specify selection of tunnel VLAN
15228 * PRI value based on whether one or two VLAN Tags are
15229 * present in tunnel headers.
15230 * This field is valid only if tunnel VLAN PRI to CoS mapping
15232 * If tunnel VLAN PRI to CoS mapping is not enabled, then this
15233 * field shall be ignored.
15235 #define HWRM_PORT_MAC_CFG_INPUT_COS_FIELD_CFG_T_VLAN_PRI_SEL_MASK \
15237 #define HWRM_PORT_MAC_CFG_INPUT_COS_FIELD_CFG_T_VLAN_PRI_SEL_SFT \
15240 * Select inner VLAN PRI when 1 or 2 VLAN Tags are
15241 * present in the tunnel packet headers
15243 #define HWRM_PORT_MAC_CFG_INPUT_COS_FIELD_CFG_T_VLAN_PRI_SEL_INNERMOST \
15244 (UINT32_C(0x0) << 3)
15246 * Select outer VLAN Tag PRI when 2 VLAN Tags are
15247 * present in the tunnel packet headers.
15248 * No tunnel VLAN PRI shall be selected for this
15249 * configuration if only one VLAN Tag is present in
15250 * the tunnel packet headers.
15252 #define HWRM_PORT_MAC_CFG_INPUT_COS_FIELD_CFG_T_VLAN_PRI_SEL_OUTER \
15253 (UINT32_C(0x1) << 3)
15255 * Select outermost VLAN PRI when 1 or 2 VLAN Tags
15256 * are present in the tunnel packet headers
15258 #define HWRM_PORT_MAC_CFG_INPUT_COS_FIELD_CFG_T_VLAN_PRI_SEL_OUTERMOST \
15259 (UINT32_C(0x2) << 3)
15261 #define HWRM_PORT_MAC_CFG_INPUT_COS_FIELD_CFG_T_VLAN_PRI_SEL_UNSPECIFIED \
15262 (UINT32_C(0x3) << 3)
15263 #define HWRM_PORT_MAC_CFG_INPUT_COS_FIELD_CFG_T_VLAN_PRI_SEL_LAST \
15264 HWRM_PORT_MAC_CFG_INPUT_COS_FIELD_CFG_T_VLAN_PRI_SEL_UNSPECIFIED
15266 * This field shall be used to provide default CoS value
15267 * that has been configured on this port.
15268 * This field is valid only if default CoS mapping
15270 * If default CoS mapping is not enabled, then this
15271 * field shall be ignored.
15273 #define HWRM_PORT_MAC_CFG_INPUT_COS_FIELD_CFG_DEFAULT_COS_MASK \
15275 #define HWRM_PORT_MAC_CFG_INPUT_COS_FIELD_CFG_DEFAULT_COS_SFT \
15277 uint8_t unused_0[3];
15279 * This signed field specifies by how much to adjust the frequency
15280 * of sync timer updates (measured in parts per billion).
15282 int32_t ptp_freq_adj_ppb;
15283 uint8_t unused_1[4];
15286 /* hwrm_port_mac_cfg_output (size:128b/16B) */
15287 struct hwrm_port_mac_cfg_output {
15288 /* The specific error status for the command. */
15289 uint16_t error_code;
15290 /* The HWRM command request type. */
15292 /* The sequence ID from the original command. */
15294 /* The length of the response data in number of bytes. */
15297 * This is the configured maximum length of Ethernet packet
15298 * payload that is allowed to be received on the port.
15299 * This value does not include the number of bytes used by
15300 * Ethernet header and trailer (CRC).
15304 * This is the configured maximum length of Ethernet packet
15305 * payload that is allowed to be transmitted on the port.
15306 * This value does not include the number of bytes used by
15307 * Ethernet header and trailer (CRC).
15310 /* Current configuration of the IPG value. */
15312 /* Current value of the loopback value. */
15314 /* No loopback is selected. Normal operation. */
15315 #define HWRM_PORT_MAC_CFG_OUTPUT_LPBK_NONE UINT32_C(0x0)
15317 * The HW will be configured with local loopback such that
15318 * host data is sent back to the host without modification.
15320 #define HWRM_PORT_MAC_CFG_OUTPUT_LPBK_LOCAL UINT32_C(0x1)
15322 * The HW will be configured with remote loopback such that
15323 * port logic will send packets back out the transmitter that
15326 #define HWRM_PORT_MAC_CFG_OUTPUT_LPBK_REMOTE UINT32_C(0x2)
15327 #define HWRM_PORT_MAC_CFG_OUTPUT_LPBK_LAST \
15328 HWRM_PORT_MAC_CFG_OUTPUT_LPBK_REMOTE
15331 * This field is used in Output records to indicate that the output
15332 * is completely written to RAM. This field should be read as '1'
15333 * to indicate that the output has been completely written.
15334 * When writing a command completion or response to an internal processor,
15335 * the order of writes has to be such that this field is written last.
15340 /**********************
15341 * hwrm_port_mac_qcfg *
15342 **********************/
15345 /* hwrm_port_mac_qcfg_input (size:192b/24B) */
15346 struct hwrm_port_mac_qcfg_input {
15347 /* The HWRM command request type. */
15350 * The completion ring to send the completion event on. This should
15351 * be the NQ ID returned from the `nq_alloc` HWRM command.
15353 uint16_t cmpl_ring;
15355 * The sequence ID is used by the driver for tracking multiple
15356 * commands. This ID is treated as opaque data by the firmware and
15357 * the value is returned in the `hwrm_resp_hdr` upon completion.
15361 * The target ID of the command:
15362 * * 0x0-0xFFF8 - The function ID
15363 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
15364 * * 0xFFFD - Reserved for user-space HWRM interface
15367 uint16_t target_id;
15369 * A physical address pointer pointing to a host buffer that the
15370 * command's response data will be written. This can be either a host
15371 * physical address (HPA) or a guest physical address (GPA) and must
15372 * point to a physically contiguous block of memory.
15374 uint64_t resp_addr;
15375 /* Port ID of port that is to be configured. */
15377 uint8_t unused_0[6];
15380 /* hwrm_port_mac_qcfg_output (size:256b/32B) */
15381 struct hwrm_port_mac_qcfg_output {
15382 /* The specific error status for the command. */
15383 uint16_t error_code;
15384 /* The HWRM command request type. */
15386 /* The sequence ID from the original command. */
15388 /* The length of the response data in number of bytes. */
15391 * This is the configured maximum length of Ethernet packet
15392 * payload that is allowed to be received on the port.
15393 * This value does not include the number of bytes used by the
15394 * Ethernet header and trailer (CRC).
15398 * This is the configured maximum length of Ethernet packet
15399 * payload that is allowed to be transmitted on the port.
15400 * This value does not include the number of bytes used by the
15401 * Ethernet header and trailer (CRC).
15405 * The minimum IPG that will
15406 * be sent between packets by this port.
15409 /* The loopback setting for the MAC. */
15411 /* No loopback is selected. Normal operation. */
15412 #define HWRM_PORT_MAC_QCFG_OUTPUT_LPBK_NONE UINT32_C(0x0)
15414 * The HW will be configured with local loopback such that
15415 * host data is sent back to the host without modification.
15417 #define HWRM_PORT_MAC_QCFG_OUTPUT_LPBK_LOCAL UINT32_C(0x1)
15419 * The HW will be configured with remote loopback such that
15420 * port logic will send packets back out the transmitter that
15423 #define HWRM_PORT_MAC_QCFG_OUTPUT_LPBK_REMOTE UINT32_C(0x2)
15424 #define HWRM_PORT_MAC_QCFG_OUTPUT_LPBK_LAST \
15425 HWRM_PORT_MAC_QCFG_OUTPUT_LPBK_REMOTE
15427 * Priority setting for VLAN PRI to CoS mapping.
15428 * # Each XXX_pri variable shall have a unique priority value
15429 * when it is being used.
15430 * # When comparing priorities of mappings, higher value
15431 * indicates higher priority.
15432 * For example, a value of 0-3 is returned where 0 is being
15433 * the lowest priority and 3 is being the highest priority.
15434 * # If the correspoding CoS mapping is not enabled, then this
15435 * field should be ignored.
15436 * # This value indicates the normalized priority value retained
15439 uint8_t vlan_pri2cos_map_pri;
15441 * In this field, a number of CoS mappings related flags
15442 * are used to indicate configured CoS mappings.
15446 * When this bit is set to '1', the inner VLAN PRI to CoS mapping
15449 #define HWRM_PORT_MAC_QCFG_OUTPUT_FLAGS_VLAN_PRI2COS_ENABLE \
15452 * When this bit is set to '1', tunnel VLAN PRI field to
15453 * CoS mapping is enabled.
15455 #define HWRM_PORT_MAC_QCFG_OUTPUT_FLAGS_TUNNEL_PRI2COS_ENABLE \
15458 * When this bit is set to '1', the IP DSCP to CoS mapping is
15461 #define HWRM_PORT_MAC_QCFG_OUTPUT_FLAGS_IP_DSCP2COS_ENABLE \
15464 * When this bit is '1', the Out-Of-Box WoL is enabled on this
15467 #define HWRM_PORT_MAC_QCFG_OUTPUT_FLAGS_OOB_WOL_ENABLE \
15469 /* When this bit is '1', PTP is enabled for RX on this port. */
15470 #define HWRM_PORT_MAC_QCFG_OUTPUT_FLAGS_PTP_RX_TS_CAPTURE_ENABLE \
15472 /* When this bit is '1', PTP is enabled for TX on this port. */
15473 #define HWRM_PORT_MAC_QCFG_OUTPUT_FLAGS_PTP_TX_TS_CAPTURE_ENABLE \
15476 * Priority setting for tunnel VLAN PRI to CoS mapping.
15477 * # Each XXX_pri variable shall have a unique priority value
15478 * when it is being used.
15479 * # When comparing priorities of mappings, higher value
15480 * indicates higher priority.
15481 * For example, a value of 0-3 is returned where 0 is being
15482 * the lowest priority and 3 is being the highest priority.
15483 * # If the correspoding CoS mapping is not enabled, then this
15484 * field should be ignored.
15485 * # This value indicates the normalized priority value retained
15488 uint8_t tunnel_pri2cos_map_pri;
15490 * Priority setting for DSCP to PRI mapping.
15491 * # Each XXX_pri variable shall have a unique priority value
15492 * when it is being used.
15493 * # When comparing priorities of mappings, higher value
15494 * indicates higher priority.
15495 * For example, a value of 0-3 is returned where 0 is being
15496 * the lowest priority and 3 is being the highest priority.
15497 * # If the correspoding CoS mapping is not enabled, then this
15498 * field should be ignored.
15499 * # This value indicates the normalized priority value retained
15502 uint8_t dscp2pri_map_pri;
15504 * This is a 16-bit bit mask that represents the
15505 * current configuration of time stamp capture of PTP messages
15506 * on the receive side of this port.
15507 * If bit 'i' is set, then the receive side of the port
15508 * is configured to capture the time stamp of every
15509 * received PTP message with messageType field value set
15511 * If all bits are set to 0 (i.e. field value set 0),
15512 * then the receive side of the port is not configured
15513 * to capture timestamp for PTP messages.
15514 * If all bits are set to 1, then the receive side of the
15515 * port is configured to capture timestamp for all PTP
15518 uint16_t rx_ts_capture_ptp_msg_type;
15520 * This is a 16-bit bit mask that represents the
15521 * current configuration of time stamp capture of PTP messages
15522 * on the transmit side of this port.
15523 * If bit 'i' is set, then the transmit side of the port
15524 * is configured to capture the time stamp of every
15525 * received PTP message with messageType field value set
15527 * If all bits are set to 0 (i.e. field value set 0),
15528 * then the transmit side of the port is not configured
15529 * to capture timestamp for PTP messages.
15530 * If all bits are set to 1, then the transmit side of the
15531 * port is configured to capture timestamp for all PTP
15534 uint16_t tx_ts_capture_ptp_msg_type;
15535 /* Configuration of CoS fields. */
15536 uint8_t cos_field_cfg;
15538 #define HWRM_PORT_MAC_QCFG_OUTPUT_COS_FIELD_CFG_RSVD \
15541 * This field is used for selecting VLAN PRI value
15542 * based on whether one or two VLAN Tags are present in
15543 * the inner packet headers of tunneled packets or
15544 * non-tunneled packets.
15546 #define HWRM_PORT_MAC_QCFG_OUTPUT_COS_FIELD_CFG_VLAN_PRI_SEL_MASK \
15548 #define HWRM_PORT_MAC_QCFG_OUTPUT_COS_FIELD_CFG_VLAN_PRI_SEL_SFT \
15551 * Select inner VLAN PRI when 1 or 2 VLAN Tags are
15552 * present in the inner packet headers
15554 #define HWRM_PORT_MAC_QCFG_OUTPUT_COS_FIELD_CFG_VLAN_PRI_SEL_INNERMOST \
15555 (UINT32_C(0x0) << 1)
15557 * Select outer VLAN Tag PRI when 2 VLAN Tags are
15558 * present in the inner packet headers.
15559 * No VLAN PRI is selected for this configuration
15560 * if only one VLAN Tag is present in the inner
15563 #define HWRM_PORT_MAC_QCFG_OUTPUT_COS_FIELD_CFG_VLAN_PRI_SEL_OUTER \
15564 (UINT32_C(0x1) << 1)
15566 * Select outermost VLAN PRI when 1 or 2 VLAN Tags
15567 * are present in the inner packet headers
15569 #define HWRM_PORT_MAC_QCFG_OUTPUT_COS_FIELD_CFG_VLAN_PRI_SEL_OUTERMOST \
15570 (UINT32_C(0x2) << 1)
15572 #define HWRM_PORT_MAC_QCFG_OUTPUT_COS_FIELD_CFG_VLAN_PRI_SEL_UNSPECIFIED \
15573 (UINT32_C(0x3) << 1)
15574 #define HWRM_PORT_MAC_QCFG_OUTPUT_COS_FIELD_CFG_VLAN_PRI_SEL_LAST \
15575 HWRM_PORT_MAC_QCFG_OUTPUT_COS_FIELD_CFG_VLAN_PRI_SEL_UNSPECIFIED
15577 * This field is used for selecting tunnel VLAN PRI value
15578 * based on whether one or two VLAN Tags are present in
15579 * the tunnel headers of tunneled packets. This selection
15580 * does not apply to non-tunneled packets.
15582 #define HWRM_PORT_MAC_QCFG_OUTPUT_COS_FIELD_CFG_T_VLAN_PRI_SEL_MASK \
15584 #define HWRM_PORT_MAC_QCFG_OUTPUT_COS_FIELD_CFG_T_VLAN_PRI_SEL_SFT \
15587 * Select inner VLAN PRI when 1 or 2 VLAN Tags are
15588 * present in the tunnel packet headers
15590 #define HWRM_PORT_MAC_QCFG_OUTPUT_COS_FIELD_CFG_T_VLAN_PRI_SEL_INNERMOST \
15591 (UINT32_C(0x0) << 3)
15593 * Select outer VLAN Tag PRI when 2 VLAN Tags are
15594 * present in the tunnel packet headers.
15595 * No VLAN PRI is selected for this configuration
15596 * if only one VLAN Tag is present in the tunnel
15599 #define HWRM_PORT_MAC_QCFG_OUTPUT_COS_FIELD_CFG_T_VLAN_PRI_SEL_OUTER \
15600 (UINT32_C(0x1) << 3)
15602 * Select outermost VLAN PRI when 1 or 2 VLAN Tags
15603 * are present in the tunnel packet headers
15605 #define HWRM_PORT_MAC_QCFG_OUTPUT_COS_FIELD_CFG_T_VLAN_PRI_SEL_OUTERMOST \
15606 (UINT32_C(0x2) << 3)
15608 #define HWRM_PORT_MAC_QCFG_OUTPUT_COS_FIELD_CFG_T_VLAN_PRI_SEL_UNSPECIFIED \
15609 (UINT32_C(0x3) << 3)
15610 #define HWRM_PORT_MAC_QCFG_OUTPUT_COS_FIELD_CFG_T_VLAN_PRI_SEL_LAST \
15611 HWRM_PORT_MAC_QCFG_OUTPUT_COS_FIELD_CFG_T_VLAN_PRI_SEL_UNSPECIFIED
15613 * This field is used to provide default CoS value that
15614 * has been configured on this port.
15616 #define HWRM_PORT_MAC_QCFG_OUTPUT_COS_FIELD_CFG_DEFAULT_COS_MASK \
15618 #define HWRM_PORT_MAC_QCFG_OUTPUT_COS_FIELD_CFG_DEFAULT_COS_SFT \
15621 uint16_t port_svif_info;
15623 * This field specifies the source virtual interface of the port being
15624 * queried. Drivers can use this to program port svif field in the
15627 #define HWRM_PORT_MAC_QCFG_OUTPUT_PORT_SVIF_INFO_PORT_SVIF_MASK \
15629 #define HWRM_PORT_MAC_QCFG_OUTPUT_PORT_SVIF_INFO_PORT_SVIF_SFT 0
15630 /* This field specifies whether port_svif is valid or not */
15631 #define HWRM_PORT_MAC_QCFG_OUTPUT_PORT_SVIF_INFO_PORT_SVIF_VALID \
15633 uint8_t unused_2[5];
15635 * This field is used in Output records to indicate that the output
15636 * is completely written to RAM. This field should be read as '1'
15637 * to indicate that the output has been completely written.
15638 * When writing a command completion or response to an internal processor,
15639 * the order of writes has to be such that this field is written last.
15644 /**************************
15645 * hwrm_port_mac_ptp_qcfg *
15646 **************************/
15649 /* hwrm_port_mac_ptp_qcfg_input (size:192b/24B) */
15650 struct hwrm_port_mac_ptp_qcfg_input {
15651 /* The HWRM command request type. */
15654 * The completion ring to send the completion event on. This should
15655 * be the NQ ID returned from the `nq_alloc` HWRM command.
15657 uint16_t cmpl_ring;
15659 * The sequence ID is used by the driver for tracking multiple
15660 * commands. This ID is treated as opaque data by the firmware and
15661 * the value is returned in the `hwrm_resp_hdr` upon completion.
15665 * The target ID of the command:
15666 * * 0x0-0xFFF8 - The function ID
15667 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
15668 * * 0xFFFD - Reserved for user-space HWRM interface
15671 uint16_t target_id;
15673 * A physical address pointer pointing to a host buffer that the
15674 * command's response data will be written. This can be either a host
15675 * physical address (HPA) or a guest physical address (GPA) and must
15676 * point to a physically contiguous block of memory.
15678 uint64_t resp_addr;
15679 /* Port ID of port that is being queried. */
15681 uint8_t unused_0[6];
15684 /* hwrm_port_mac_ptp_qcfg_output (size:640b/80B) */
15685 struct hwrm_port_mac_ptp_qcfg_output {
15686 /* The specific error status for the command. */
15687 uint16_t error_code;
15688 /* The HWRM command request type. */
15690 /* The sequence ID from the original command. */
15692 /* The length of the response data in number of bytes. */
15695 * In this field, a number of PTP related flags
15696 * are used to indicate configured PTP capabilities.
15700 * When this bit is set to '1', the PTP related registers are
15701 * directly accessible by the host.
15703 #define HWRM_PORT_MAC_PTP_QCFG_OUTPUT_FLAGS_DIRECT_ACCESS \
15706 * When this bit is set to '1', the device supports one-step
15709 #define HWRM_PORT_MAC_PTP_QCFG_OUTPUT_FLAGS_ONE_STEP_TX_TS \
15712 * When this bit is set to '1', the PTP information is accessible
15713 * via HWRM commands.
15715 #define HWRM_PORT_MAC_PTP_QCFG_OUTPUT_FLAGS_HWRM_ACCESS \
15717 uint8_t unused_0[3];
15718 /* Offset of the PTP register for the lower 32 bits of timestamp for RX. */
15719 uint32_t rx_ts_reg_off_lower;
15720 /* Offset of the PTP register for the upper 32 bits of timestamp for RX. */
15721 uint32_t rx_ts_reg_off_upper;
15722 /* Offset of the PTP register for the sequence ID for RX. */
15723 uint32_t rx_ts_reg_off_seq_id;
15724 /* Offset of the first PTP source ID for RX. */
15725 uint32_t rx_ts_reg_off_src_id_0;
15726 /* Offset of the second PTP source ID for RX. */
15727 uint32_t rx_ts_reg_off_src_id_1;
15728 /* Offset of the third PTP source ID for RX. */
15729 uint32_t rx_ts_reg_off_src_id_2;
15730 /* Offset of the domain ID for RX. */
15731 uint32_t rx_ts_reg_off_domain_id;
15732 /* Offset of the PTP FIFO register for RX. */
15733 uint32_t rx_ts_reg_off_fifo;
15734 /* Offset of the PTP advance FIFO register for RX. */
15735 uint32_t rx_ts_reg_off_fifo_adv;
15736 /* PTP timestamp granularity for RX. */
15737 uint32_t rx_ts_reg_off_granularity;
15738 /* Offset of the PTP register for the lower 32 bits of timestamp for TX. */
15739 uint32_t tx_ts_reg_off_lower;
15740 /* Offset of the PTP register for the upper 32 bits of timestamp for TX. */
15741 uint32_t tx_ts_reg_off_upper;
15742 /* Offset of the PTP register for the sequence ID for TX. */
15743 uint32_t tx_ts_reg_off_seq_id;
15744 /* Offset of the PTP FIFO register for TX. */
15745 uint32_t tx_ts_reg_off_fifo;
15746 /* PTP timestamp granularity for TX. */
15747 uint32_t tx_ts_reg_off_granularity;
15748 uint8_t unused_1[7];
15750 * This field is used in Output records to indicate that the output
15751 * is completely written to RAM. This field should be read as '1'
15752 * to indicate that the output has been completely written.
15753 * When writing a command completion or response to an internal processor,
15754 * the order of writes has to be such that this field is written last.
15759 /* Port Tx Statistics Format */
15760 /* tx_port_stats (size:3264b/408B) */
15761 struct tx_port_stats {
15762 /* Total Number of 64 Bytes frames transmitted */
15763 uint64_t tx_64b_frames;
15764 /* Total Number of 65-127 Bytes frames transmitted */
15765 uint64_t tx_65b_127b_frames;
15766 /* Total Number of 128-255 Bytes frames transmitted */
15767 uint64_t tx_128b_255b_frames;
15768 /* Total Number of 256-511 Bytes frames transmitted */
15769 uint64_t tx_256b_511b_frames;
15770 /* Total Number of 512-1023 Bytes frames transmitted */
15771 uint64_t tx_512b_1023b_frames;
15772 /* Total Number of 1024-1518 Bytes frames transmitted */
15773 uint64_t tx_1024b_1518b_frames;
15775 * Total Number of each good VLAN (exludes FCS errors)
15776 * frame transmitted which is 1519 to 1522 bytes in length
15777 * inclusive (excluding framing bits but including FCS bytes).
15779 uint64_t tx_good_vlan_frames;
15780 /* Total Number of 1519-2047 Bytes frames transmitted */
15781 uint64_t tx_1519b_2047b_frames;
15782 /* Total Number of 2048-4095 Bytes frames transmitted */
15783 uint64_t tx_2048b_4095b_frames;
15784 /* Total Number of 4096-9216 Bytes frames transmitted */
15785 uint64_t tx_4096b_9216b_frames;
15786 /* Total Number of 9217-16383 Bytes frames transmitted */
15787 uint64_t tx_9217b_16383b_frames;
15788 /* Total Number of good frames transmitted */
15789 uint64_t tx_good_frames;
15790 /* Total Number of frames transmitted */
15791 uint64_t tx_total_frames;
15792 /* Total number of unicast frames transmitted */
15793 uint64_t tx_ucast_frames;
15794 /* Total number of multicast frames transmitted */
15795 uint64_t tx_mcast_frames;
15796 /* Total number of broadcast frames transmitted */
15797 uint64_t tx_bcast_frames;
15798 /* Total number of PAUSE control frames transmitted */
15799 uint64_t tx_pause_frames;
15801 * Total number of PFC/per-priority PAUSE
15802 * control frames transmitted
15804 uint64_t tx_pfc_frames;
15805 /* Total number of jabber frames transmitted */
15806 uint64_t tx_jabber_frames;
15807 /* Total number of frames transmitted with FCS error */
15808 uint64_t tx_fcs_err_frames;
15809 /* Total number of control frames transmitted */
15810 uint64_t tx_control_frames;
15811 /* Total number of over-sized frames transmitted */
15812 uint64_t tx_oversz_frames;
15813 /* Total number of frames with single deferral */
15814 uint64_t tx_single_dfrl_frames;
15815 /* Total number of frames with multiple deferrals */
15816 uint64_t tx_multi_dfrl_frames;
15817 /* Total number of frames with single collision */
15818 uint64_t tx_single_coll_frames;
15819 /* Total number of frames with multiple collisions */
15820 uint64_t tx_multi_coll_frames;
15821 /* Total number of frames with late collisions */
15822 uint64_t tx_late_coll_frames;
15823 /* Total number of frames with excessive collisions */
15824 uint64_t tx_excessive_coll_frames;
15825 /* Total number of fragmented frames transmitted */
15826 uint64_t tx_frag_frames;
15827 /* Total number of transmit errors */
15829 /* Total number of single VLAN tagged frames transmitted */
15830 uint64_t tx_tagged_frames;
15831 /* Total number of double VLAN tagged frames transmitted */
15832 uint64_t tx_dbl_tagged_frames;
15833 /* Total number of runt frames transmitted */
15834 uint64_t tx_runt_frames;
15835 /* Total number of TX FIFO under runs */
15836 uint64_t tx_fifo_underruns;
15838 * Total number of PFC frames with PFC enabled bit for
15839 * Pri 0 transmitted
15841 uint64_t tx_pfc_ena_frames_pri0;
15843 * Total number of PFC frames with PFC enabled bit for
15844 * Pri 1 transmitted
15846 uint64_t tx_pfc_ena_frames_pri1;
15848 * Total number of PFC frames with PFC enabled bit for
15849 * Pri 2 transmitted
15851 uint64_t tx_pfc_ena_frames_pri2;
15853 * Total number of PFC frames with PFC enabled bit for
15854 * Pri 3 transmitted
15856 uint64_t tx_pfc_ena_frames_pri3;
15858 * Total number of PFC frames with PFC enabled bit for
15859 * Pri 4 transmitted
15861 uint64_t tx_pfc_ena_frames_pri4;
15863 * Total number of PFC frames with PFC enabled bit for
15864 * Pri 5 transmitted
15866 uint64_t tx_pfc_ena_frames_pri5;
15868 * Total number of PFC frames with PFC enabled bit for
15869 * Pri 6 transmitted
15871 uint64_t tx_pfc_ena_frames_pri6;
15873 * Total number of PFC frames with PFC enabled bit for
15874 * Pri 7 transmitted
15876 uint64_t tx_pfc_ena_frames_pri7;
15877 /* Total number of EEE LPI Events on TX */
15878 uint64_t tx_eee_lpi_events;
15879 /* EEE LPI Duration Counter on TX */
15880 uint64_t tx_eee_lpi_duration;
15882 * Total number of Link Level Flow Control (LLFC) messages
15885 uint64_t tx_llfc_logical_msgs;
15886 /* Total number of HCFC messages transmitted */
15887 uint64_t tx_hcfc_msgs;
15888 /* Total number of TX collisions */
15889 uint64_t tx_total_collisions;
15890 /* Total number of transmitted bytes */
15892 /* Total number of end-to-end HOL frames */
15893 uint64_t tx_xthol_frames;
15894 /* Total Tx Drops per Port reported by STATS block */
15895 uint64_t tx_stat_discard;
15896 /* Total Tx Error Drops per Port reported by STATS block */
15897 uint64_t tx_stat_error;
15900 /* Port Rx Statistics Format */
15901 /* rx_port_stats (size:4224b/528B) */
15902 struct rx_port_stats {
15903 /* Total Number of 64 Bytes frames received */
15904 uint64_t rx_64b_frames;
15905 /* Total Number of 65-127 Bytes frames received */
15906 uint64_t rx_65b_127b_frames;
15907 /* Total Number of 128-255 Bytes frames received */
15908 uint64_t rx_128b_255b_frames;
15909 /* Total Number of 256-511 Bytes frames received */
15910 uint64_t rx_256b_511b_frames;
15911 /* Total Number of 512-1023 Bytes frames received */
15912 uint64_t rx_512b_1023b_frames;
15913 /* Total Number of 1024-1518 Bytes frames received */
15914 uint64_t rx_1024b_1518b_frames;
15916 * Total Number of each good VLAN (exludes FCS errors)
15917 * frame received which is 1519 to 1522 bytes in length
15918 * inclusive (excluding framing bits but including FCS bytes).
15920 uint64_t rx_good_vlan_frames;
15921 /* Total Number of 1519-2047 Bytes frames received */
15922 uint64_t rx_1519b_2047b_frames;
15923 /* Total Number of 2048-4095 Bytes frames received */
15924 uint64_t rx_2048b_4095b_frames;
15925 /* Total Number of 4096-9216 Bytes frames received */
15926 uint64_t rx_4096b_9216b_frames;
15927 /* Total Number of 9217-16383 Bytes frames received */
15928 uint64_t rx_9217b_16383b_frames;
15929 /* Total number of frames received */
15930 uint64_t rx_total_frames;
15931 /* Total number of unicast frames received */
15932 uint64_t rx_ucast_frames;
15933 /* Total number of multicast frames received */
15934 uint64_t rx_mcast_frames;
15935 /* Total number of broadcast frames received */
15936 uint64_t rx_bcast_frames;
15937 /* Total number of received frames with FCS error */
15938 uint64_t rx_fcs_err_frames;
15939 /* Total number of control frames received */
15940 uint64_t rx_ctrl_frames;
15941 /* Total number of PAUSE frames received */
15942 uint64_t rx_pause_frames;
15943 /* Total number of PFC frames received */
15944 uint64_t rx_pfc_frames;
15946 * Total number of frames received with an unsupported
15949 uint64_t rx_unsupported_opcode_frames;
15951 * Total number of frames received with an unsupported
15952 * DA for pause and PFC
15954 uint64_t rx_unsupported_da_pausepfc_frames;
15955 /* Total number of frames received with an unsupported SA */
15956 uint64_t rx_wrong_sa_frames;
15957 /* Total number of received packets with alignment error */
15958 uint64_t rx_align_err_frames;
15959 /* Total number of received frames with out-of-range length */
15960 uint64_t rx_oor_len_frames;
15961 /* Total number of received frames with error termination */
15962 uint64_t rx_code_err_frames;
15964 * Total number of received frames with a false carrier is
15965 * detected during idle, as defined by RX_ER samples active
15966 * and RXD is 0xE. The event is reported along with the
15967 * statistics generated on the next received frame. Only
15968 * one false carrier condition can be detected and logged
15971 * Carrier event, valid for 10M/100M speed modes only.
15973 uint64_t rx_false_carrier_frames;
15974 /* Total number of over-sized frames received */
15975 uint64_t rx_ovrsz_frames;
15976 /* Total number of jabber packets received */
15977 uint64_t rx_jbr_frames;
15978 /* Total number of received frames with MTU error */
15979 uint64_t rx_mtu_err_frames;
15980 /* Total number of received frames with CRC match */
15981 uint64_t rx_match_crc_frames;
15982 /* Total number of frames received promiscuously */
15983 uint64_t rx_promiscuous_frames;
15985 * Total number of received frames with one or two VLAN
15988 uint64_t rx_tagged_frames;
15989 /* Total number of received frames with two VLAN tags */
15990 uint64_t rx_double_tagged_frames;
15991 /* Total number of truncated frames received */
15992 uint64_t rx_trunc_frames;
15993 /* Total number of good frames (without errors) received */
15994 uint64_t rx_good_frames;
15996 * Total number of received PFC frames with transition from
15997 * XON to XOFF on Pri 0
15999 uint64_t rx_pfc_xon2xoff_frames_pri0;
16001 * Total number of received PFC frames with transition from
16002 * XON to XOFF on Pri 1
16004 uint64_t rx_pfc_xon2xoff_frames_pri1;
16006 * Total number of received PFC frames with transition from
16007 * XON to XOFF on Pri 2
16009 uint64_t rx_pfc_xon2xoff_frames_pri2;
16011 * Total number of received PFC frames with transition from
16012 * XON to XOFF on Pri 3
16014 uint64_t rx_pfc_xon2xoff_frames_pri3;
16016 * Total number of received PFC frames with transition from
16017 * XON to XOFF on Pri 4
16019 uint64_t rx_pfc_xon2xoff_frames_pri4;
16021 * Total number of received PFC frames with transition from
16022 * XON to XOFF on Pri 5
16024 uint64_t rx_pfc_xon2xoff_frames_pri5;
16026 * Total number of received PFC frames with transition from
16027 * XON to XOFF on Pri 6
16029 uint64_t rx_pfc_xon2xoff_frames_pri6;
16031 * Total number of received PFC frames with transition from
16032 * XON to XOFF on Pri 7
16034 uint64_t rx_pfc_xon2xoff_frames_pri7;
16036 * Total number of received PFC frames with PFC enabled
16039 uint64_t rx_pfc_ena_frames_pri0;
16041 * Total number of received PFC frames with PFC enabled
16044 uint64_t rx_pfc_ena_frames_pri1;
16046 * Total number of received PFC frames with PFC enabled
16049 uint64_t rx_pfc_ena_frames_pri2;
16051 * Total number of received PFC frames with PFC enabled
16054 uint64_t rx_pfc_ena_frames_pri3;
16056 * Total number of received PFC frames with PFC enabled
16059 uint64_t rx_pfc_ena_frames_pri4;
16061 * Total number of received PFC frames with PFC enabled
16064 uint64_t rx_pfc_ena_frames_pri5;
16066 * Total number of received PFC frames with PFC enabled
16069 uint64_t rx_pfc_ena_frames_pri6;
16071 * Total number of received PFC frames with PFC enabled
16074 uint64_t rx_pfc_ena_frames_pri7;
16075 /* Total Number of frames received with SCH CRC error */
16076 uint64_t rx_sch_crc_err_frames;
16077 /* Total Number of under-sized frames received */
16078 uint64_t rx_undrsz_frames;
16079 /* Total Number of fragmented frames received */
16080 uint64_t rx_frag_frames;
16081 /* Total number of RX EEE LPI Events */
16082 uint64_t rx_eee_lpi_events;
16083 /* EEE LPI Duration Counter on RX */
16084 uint64_t rx_eee_lpi_duration;
16086 * Total number of physical type Link Level Flow Control
16087 * (LLFC) messages received
16089 uint64_t rx_llfc_physical_msgs;
16091 * Total number of logical type Link Level Flow Control
16092 * (LLFC) messages received
16094 uint64_t rx_llfc_logical_msgs;
16096 * Total number of logical type Link Level Flow Control
16097 * (LLFC) messages received with CRC error
16099 uint64_t rx_llfc_msgs_with_crc_err;
16100 /* Total number of HCFC messages received */
16101 uint64_t rx_hcfc_msgs;
16102 /* Total number of HCFC messages received with CRC error */
16103 uint64_t rx_hcfc_msgs_with_crc_err;
16104 /* Total number of received bytes */
16106 /* Total number of bytes received in runt frames */
16107 uint64_t rx_runt_bytes;
16108 /* Total number of runt frames received */
16109 uint64_t rx_runt_frames;
16110 /* Total Rx Discards per Port reported by STATS block */
16111 uint64_t rx_stat_discard;
16112 uint64_t rx_stat_err;
16115 /********************
16116 * hwrm_port_qstats *
16117 ********************/
16120 /* hwrm_port_qstats_input (size:320b/40B) */
16121 struct hwrm_port_qstats_input {
16122 /* The HWRM command request type. */
16125 * The completion ring to send the completion event on. This should
16126 * be the NQ ID returned from the `nq_alloc` HWRM command.
16128 uint16_t cmpl_ring;
16130 * The sequence ID is used by the driver for tracking multiple
16131 * commands. This ID is treated as opaque data by the firmware and
16132 * the value is returned in the `hwrm_resp_hdr` upon completion.
16136 * The target ID of the command:
16137 * * 0x0-0xFFF8 - The function ID
16138 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
16139 * * 0xFFFD - Reserved for user-space HWRM interface
16142 uint16_t target_id;
16144 * A physical address pointer pointing to a host buffer that the
16145 * command's response data will be written. This can be either a host
16146 * physical address (HPA) or a guest physical address (GPA) and must
16147 * point to a physically contiguous block of memory.
16149 uint64_t resp_addr;
16150 /* Port ID of port that is being queried. */
16152 uint8_t unused_0[6];
16154 * This is the host address where
16155 * Tx port statistics will be stored
16157 uint64_t tx_stat_host_addr;
16159 * This is the host address where
16160 * Rx port statistics will be stored
16162 uint64_t rx_stat_host_addr;
16165 /* hwrm_port_qstats_output (size:128b/16B) */
16166 struct hwrm_port_qstats_output {
16167 /* The specific error status for the command. */
16168 uint16_t error_code;
16169 /* The HWRM command request type. */
16171 /* The sequence ID from the original command. */
16173 /* The length of the response data in number of bytes. */
16175 /* The size of TX port statistics block in bytes. */
16176 uint16_t tx_stat_size;
16177 /* The size of RX port statistics block in bytes. */
16178 uint16_t rx_stat_size;
16179 uint8_t unused_0[3];
16181 * This field is used in Output records to indicate that the output
16182 * is completely written to RAM. This field should be read as '1'
16183 * to indicate that the output has been completely written.
16184 * When writing a command completion or response to an internal processor,
16185 * the order of writes has to be such that this field is written last.
16190 /* Port Tx Statistics extended Format */
16191 /* tx_port_stats_ext (size:2048b/256B) */
16192 struct tx_port_stats_ext {
16193 /* Total number of tx bytes count on cos queue 0 */
16194 uint64_t tx_bytes_cos0;
16195 /* Total number of tx bytes count on cos queue 1 */
16196 uint64_t tx_bytes_cos1;
16197 /* Total number of tx bytes count on cos queue 2 */
16198 uint64_t tx_bytes_cos2;
16199 /* Total number of tx bytes count on cos queue 3 */
16200 uint64_t tx_bytes_cos3;
16201 /* Total number of tx bytes count on cos queue 4 */
16202 uint64_t tx_bytes_cos4;
16203 /* Total number of tx bytes count on cos queue 5 */
16204 uint64_t tx_bytes_cos5;
16205 /* Total number of tx bytes count on cos queue 6 */
16206 uint64_t tx_bytes_cos6;
16207 /* Total number of tx bytes count on cos queue 7 */
16208 uint64_t tx_bytes_cos7;
16209 /* Total number of tx packets count on cos queue 0 */
16210 uint64_t tx_packets_cos0;
16211 /* Total number of tx packets count on cos queue 1 */
16212 uint64_t tx_packets_cos1;
16213 /* Total number of tx packets count on cos queue 2 */
16214 uint64_t tx_packets_cos2;
16215 /* Total number of tx packets count on cos queue 3 */
16216 uint64_t tx_packets_cos3;
16217 /* Total number of tx packets count on cos queue 4 */
16218 uint64_t tx_packets_cos4;
16219 /* Total number of tx packets count on cos queue 5 */
16220 uint64_t tx_packets_cos5;
16221 /* Total number of tx packets count on cos queue 6 */
16222 uint64_t tx_packets_cos6;
16223 /* Total number of tx packets count on cos queue 7 */
16224 uint64_t tx_packets_cos7;
16225 /* time duration between transmitting a XON -> XOFF and a subsequent XOFF -> XON for priority 0 */
16226 uint64_t pfc_pri0_tx_duration_us;
16227 /* Number of times, a XON -> XOFF and XOFF -> XON transitions occur for priority 0 */
16228 uint64_t pfc_pri0_tx_transitions;
16229 /* time duration between transmitting a XON -> XOFF and a subsequent XOFF -> XON for priority 1 */
16230 uint64_t pfc_pri1_tx_duration_us;
16231 /* Number of times, a XON -> XOFF and XOFF -> XON transitions occur for priority 1 */
16232 uint64_t pfc_pri1_tx_transitions;
16233 /* time duration between transmitting a XON -> XOFF and a subsequent XOFF -> XON for priority 2 */
16234 uint64_t pfc_pri2_tx_duration_us;
16235 /* Number of times, a XON -> XOFF and XOFF -> XON transitions occur for priority 2 */
16236 uint64_t pfc_pri2_tx_transitions;
16237 /* time duration between transmitting a XON -> XOFF and a subsequent XOFF -> XON for priority 3 */
16238 uint64_t pfc_pri3_tx_duration_us;
16239 /* Number of times, a XON -> XOFF and XOFF -> XON transitions occur for priority 3 */
16240 uint64_t pfc_pri3_tx_transitions;
16241 /* time duration between transmitting a XON -> XOFF and a subsequent XOFF -> XON for priority 4 */
16242 uint64_t pfc_pri4_tx_duration_us;
16243 /* Number of times, a XON -> XOFF and XOFF -> XON transitions occur for priority 4 */
16244 uint64_t pfc_pri4_tx_transitions;
16245 /* time duration between transmitting a XON -> XOFF and a subsequent XOFF -> XON for priority 5 */
16246 uint64_t pfc_pri5_tx_duration_us;
16247 /* Number of times, a XON -> XOFF and XOFF -> XON transitions occur for priority 5 */
16248 uint64_t pfc_pri5_tx_transitions;
16249 /* time duration between transmitting a XON -> XOFF and a subsequent XOFF -> XON for priority 6 */
16250 uint64_t pfc_pri6_tx_duration_us;
16251 /* Number of times, a XON -> XOFF and XOFF -> XON transitions occur for priority 6 */
16252 uint64_t pfc_pri6_tx_transitions;
16253 /* time duration between transmitting a XON -> XOFF and a subsequent XOFF -> XON for priority 7 */
16254 uint64_t pfc_pri7_tx_duration_us;
16255 /* Number of times, a XON -> XOFF and XOFF -> XON transitions occur for priority 7 */
16256 uint64_t pfc_pri7_tx_transitions;
16259 /* Port Rx Statistics extended Format */
16260 /* rx_port_stats_ext (size:3648b/456B) */
16261 struct rx_port_stats_ext {
16262 /* Number of times link state changed to down */
16263 uint64_t link_down_events;
16264 /* Number of times the idle rings with pause bit are found */
16265 uint64_t continuous_pause_events;
16266 /* Number of times the active rings pause bit resumed back */
16267 uint64_t resume_pause_events;
16268 /* Number of times, the ROCE cos queue PFC is disabled to avoid pause flood/burst */
16269 uint64_t continuous_roce_pause_events;
16270 /* Number of times, the ROCE cos queue PFC is enabled back */
16271 uint64_t resume_roce_pause_events;
16272 /* Total number of rx bytes count on cos queue 0 */
16273 uint64_t rx_bytes_cos0;
16274 /* Total number of rx bytes count on cos queue 1 */
16275 uint64_t rx_bytes_cos1;
16276 /* Total number of rx bytes count on cos queue 2 */
16277 uint64_t rx_bytes_cos2;
16278 /* Total number of rx bytes count on cos queue 3 */
16279 uint64_t rx_bytes_cos3;
16280 /* Total number of rx bytes count on cos queue 4 */
16281 uint64_t rx_bytes_cos4;
16282 /* Total number of rx bytes count on cos queue 5 */
16283 uint64_t rx_bytes_cos5;
16284 /* Total number of rx bytes count on cos queue 6 */
16285 uint64_t rx_bytes_cos6;
16286 /* Total number of rx bytes count on cos queue 7 */
16287 uint64_t rx_bytes_cos7;
16288 /* Total number of rx packets count on cos queue 0 */
16289 uint64_t rx_packets_cos0;
16290 /* Total number of rx packets count on cos queue 1 */
16291 uint64_t rx_packets_cos1;
16292 /* Total number of rx packets count on cos queue 2 */
16293 uint64_t rx_packets_cos2;
16294 /* Total number of rx packets count on cos queue 3 */
16295 uint64_t rx_packets_cos3;
16296 /* Total number of rx packets count on cos queue 4 */
16297 uint64_t rx_packets_cos4;
16298 /* Total number of rx packets count on cos queue 5 */
16299 uint64_t rx_packets_cos5;
16300 /* Total number of rx packets count on cos queue 6 */
16301 uint64_t rx_packets_cos6;
16302 /* Total number of rx packets count on cos queue 7 */
16303 uint64_t rx_packets_cos7;
16304 /* time duration receiving a XON -> XOFF and a subsequent XOFF -> XON for priority 0 */
16305 uint64_t pfc_pri0_rx_duration_us;
16306 /* Number of times, a XON -> XOFF and XOFF -> XON transitions occur for priority 0 */
16307 uint64_t pfc_pri0_rx_transitions;
16308 /* time duration receiving a XON -> XOFF and a subsequent XOFF -> XON for priority 1 */
16309 uint64_t pfc_pri1_rx_duration_us;
16310 /* Number of times, a XON -> XOFF and XOFF -> XON transitions occur for priority 1 */
16311 uint64_t pfc_pri1_rx_transitions;
16312 /* time duration receiving a XON -> XOFF and a subsequent XOFF -> XON for priority 2 */
16313 uint64_t pfc_pri2_rx_duration_us;
16314 /* Number of times, a XON -> XOFF and XOFF -> XON transitions occur for priority 2 */
16315 uint64_t pfc_pri2_rx_transitions;
16316 /* time duration receiving a XON -> XOFF and a subsequent XOFF -> XON for priority 3 */
16317 uint64_t pfc_pri3_rx_duration_us;
16318 /* Number of times, a XON -> XOFF and XOFF -> XON transitions occur for priority 3 */
16319 uint64_t pfc_pri3_rx_transitions;
16320 /* time duration receiving a XON -> XOFF and a subsequent XOFF -> XON for priority 4 */
16321 uint64_t pfc_pri4_rx_duration_us;
16322 /* Number of times, a XON -> XOFF and XOFF -> XON transitions occur for priority 4 */
16323 uint64_t pfc_pri4_rx_transitions;
16324 /* time duration receiving a XON -> XOFF and a subsequent XOFF -> XON for priority 5 */
16325 uint64_t pfc_pri5_rx_duration_us;
16326 /* Number of times, a XON -> XOFF and XOFF -> XON transitions occur for priority 5 */
16327 uint64_t pfc_pri5_rx_transitions;
16328 /* time duration receiving a XON -> XOFF and a subsequent XOFF -> XON for priority 6 */
16329 uint64_t pfc_pri6_rx_duration_us;
16330 /* Number of times, a XON -> XOFF and XOFF -> XON transitions occur for priority 6 */
16331 uint64_t pfc_pri6_rx_transitions;
16332 /* time duration receiving a XON -> XOFF and a subsequent XOFF -> XON for priority 7 */
16333 uint64_t pfc_pri7_rx_duration_us;
16334 /* Number of times, a XON -> XOFF and XOFF -> XON transitions occur for priority 7 */
16335 uint64_t pfc_pri7_rx_transitions;
16336 /* Total number of received bits */
16338 /* The number of events where the port receive buffer was over 85% full */
16339 uint64_t rx_buffer_passed_threshold;
16341 * The number of symbol errors that wasn't corrected by FEC correction
16344 uint64_t rx_pcs_symbol_err;
16345 /* The number of corrected bits on the port according to active FEC */
16346 uint64_t rx_corrected_bits;
16347 /* Total number of rx discard bytes count on cos queue 0 */
16348 uint64_t rx_discard_bytes_cos0;
16349 /* Total number of rx discard bytes count on cos queue 1 */
16350 uint64_t rx_discard_bytes_cos1;
16351 /* Total number of rx discard bytes count on cos queue 2 */
16352 uint64_t rx_discard_bytes_cos2;
16353 /* Total number of rx discard bytes count on cos queue 3 */
16354 uint64_t rx_discard_bytes_cos3;
16355 /* Total number of rx discard bytes count on cos queue 4 */
16356 uint64_t rx_discard_bytes_cos4;
16357 /* Total number of rx discard bytes count on cos queue 5 */
16358 uint64_t rx_discard_bytes_cos5;
16359 /* Total number of rx discard bytes count on cos queue 6 */
16360 uint64_t rx_discard_bytes_cos6;
16361 /* Total number of rx discard bytes count on cos queue 7 */
16362 uint64_t rx_discard_bytes_cos7;
16363 /* Total number of rx discard packets count on cos queue 0 */
16364 uint64_t rx_discard_packets_cos0;
16365 /* Total number of rx discard packets count on cos queue 1 */
16366 uint64_t rx_discard_packets_cos1;
16367 /* Total number of rx discard packets count on cos queue 2 */
16368 uint64_t rx_discard_packets_cos2;
16369 /* Total number of rx discard packets count on cos queue 3 */
16370 uint64_t rx_discard_packets_cos3;
16371 /* Total number of rx discard packets count on cos queue 4 */
16372 uint64_t rx_discard_packets_cos4;
16373 /* Total number of rx discard packets count on cos queue 5 */
16374 uint64_t rx_discard_packets_cos5;
16375 /* Total number of rx discard packets count on cos queue 6 */
16376 uint64_t rx_discard_packets_cos6;
16377 /* Total number of rx discard packets count on cos queue 7 */
16378 uint64_t rx_discard_packets_cos7;
16382 * Port Rx Statistics extended PFC WatchDog Format.
16383 * StormDetect and StormRevert event determination is based
16384 * on an integration period and a percentage threshold.
16385 * StormDetect event - when percentage of XOFF frames received
16386 * within an integration period exceeds the configured threshold.
16387 * StormRevert event - when percentage of XON frames received
16388 * within an integration period exceeds the configured threshold.
16389 * Actual number of XOFF/XON frames for the events to be triggered
16390 * depends on both configured integration period and sampling rate.
16391 * The statistics in this structure represent counts of specified
16392 * events from the moment the feature (PFC WatchDog) is enabled via
16393 * hwrm_queue_pfc_enable_cfg call.
16395 /* rx_port_stats_ext_pfc_wd (size:5120b/640B) */
16396 struct rx_port_stats_ext_pfc_wd {
16398 * Total number of PFC WatchDog StormDetect events detected
16401 uint64_t rx_pfc_watchdog_storms_detected_pri0;
16403 * Total number of PFC WatchDog StormDetect events detected
16406 uint64_t rx_pfc_watchdog_storms_detected_pri1;
16408 * Total number of PFC WatchDog StormDetect events detected
16411 uint64_t rx_pfc_watchdog_storms_detected_pri2;
16413 * Total number of PFC WatchDog StormDetect events detected
16416 uint64_t rx_pfc_watchdog_storms_detected_pri3;
16418 * Total number of PFC WatchDog StormDetect events detected
16421 uint64_t rx_pfc_watchdog_storms_detected_pri4;
16423 * Total number of PFC WatchDog StormDetect events detected
16426 uint64_t rx_pfc_watchdog_storms_detected_pri5;
16428 * Total number of PFC WatchDog StormDetect events detected
16431 uint64_t rx_pfc_watchdog_storms_detected_pri6;
16433 * Total number of PFC WatchDog StormDetect events detected
16436 uint64_t rx_pfc_watchdog_storms_detected_pri7;
16438 * Total number of PFC WatchDog StormRevert events detected
16441 uint64_t rx_pfc_watchdog_storms_reverted_pri0;
16443 * Total number of PFC WatchDog StormRevert events detected
16446 uint64_t rx_pfc_watchdog_storms_reverted_pri1;
16448 * Total number of PFC WatchDog StormRevert events detected
16451 uint64_t rx_pfc_watchdog_storms_reverted_pri2;
16453 * Total number of PFC WatchDog StormRevert events detected
16456 uint64_t rx_pfc_watchdog_storms_reverted_pri3;
16458 * Total number of PFC WatchDog StormRevert events detected
16461 uint64_t rx_pfc_watchdog_storms_reverted_pri4;
16463 * Total number of PFC WatchDog StormRevert events detected
16466 uint64_t rx_pfc_watchdog_storms_reverted_pri5;
16468 * Total number of PFC WatchDog StormRevert events detected
16471 uint64_t rx_pfc_watchdog_storms_reverted_pri6;
16473 * Total number of PFC WatchDog StormRevert events detected
16476 uint64_t rx_pfc_watchdog_storms_reverted_pri7;
16478 * Total number of packets received during PFC watchdog storm
16481 uint64_t rx_pfc_watchdog_storms_rx_packets_pri0;
16483 * Total number of packets received during PFC watchdog storm
16486 uint64_t rx_pfc_watchdog_storms_rx_packets_pri1;
16488 * Total number of packets received during PFC watchdog storm
16491 uint64_t rx_pfc_watchdog_storms_rx_packets_pri2;
16493 * Total number of packets received during PFC watchdog storm
16496 uint64_t rx_pfc_watchdog_storms_rx_packets_pri3;
16498 * Total number of packets received during PFC watchdog storm
16501 uint64_t rx_pfc_watchdog_storms_rx_packets_pri4;
16503 * Total number of packets received during PFC watchdog storm
16506 uint64_t rx_pfc_watchdog_storms_rx_packets_pri5;
16508 * Total number of packets received during PFC watchdog storm
16511 uint64_t rx_pfc_watchdog_storms_rx_packets_pri6;
16513 * Total number of packets received during PFC watchdog storm
16516 uint64_t rx_pfc_watchdog_storms_rx_packets_pri7;
16518 * Total number of bytes received during PFC watchdog storm
16521 uint64_t rx_pfc_watchdog_storms_rx_bytes_pri0;
16523 * Total number of bytes received during PFC watchdog storm
16526 uint64_t rx_pfc_watchdog_storms_rx_bytes_pri1;
16528 * Total number of bytes received during PFC watchdog storm
16531 uint64_t rx_pfc_watchdog_storms_rx_bytes_pri2;
16533 * Total number of bytes received during PFC watchdog storm
16536 uint64_t rx_pfc_watchdog_storms_rx_bytes_pri3;
16538 * Total number of bytes received during PFC watchdog storm
16541 uint64_t rx_pfc_watchdog_storms_rx_bytes_pri4;
16543 * Total number of bytes received during PFC watchdog storm
16546 uint64_t rx_pfc_watchdog_storms_rx_bytes_pri5;
16548 * Total number of bytes received during PFC watchdog storm
16551 uint64_t rx_pfc_watchdog_storms_rx_bytes_pri6;
16553 * Total number of bytes received during PFC watchdog storm
16556 uint64_t rx_pfc_watchdog_storms_rx_bytes_pri7;
16558 * Total number of packets dropped on rx during PFC watchdog storm
16561 uint64_t rx_pfc_watchdog_storms_rx_packets_dropped_pri0;
16563 * Total number of packets dropped on rx during PFC watchdog storm
16566 uint64_t rx_pfc_watchdog_storms_rx_packets_dropped_pri1;
16568 * Total number of packets dropped on rx during PFC watchdog storm
16571 uint64_t rx_pfc_watchdog_storms_rx_packets_dropped_pri2;
16573 * Total number of packets dropped on rx during PFC watchdog storm
16576 uint64_t rx_pfc_watchdog_storms_rx_packets_dropped_pri3;
16578 * Total number of packets dropped on rx during PFC watchdog storm
16581 uint64_t rx_pfc_watchdog_storms_rx_packets_dropped_pri4;
16583 * Total number of packets dropped on rx during PFC watchdog storm
16586 uint64_t rx_pfc_watchdog_storms_rx_packets_dropped_pri5;
16588 * Total number of packets dropped on rx during PFC watchdog storm
16591 uint64_t rx_pfc_watchdog_storms_rx_packets_dropped_pri6;
16593 * Total number of packets dropped on rx during PFC watchdog storm
16596 uint64_t rx_pfc_watchdog_storms_rx_packets_dropped_pri7;
16598 * Total number of bytes dropped on rx during PFC watchdog storm
16601 uint64_t rx_pfc_watchdog_storms_rx_bytes_dropped_pri0;
16603 * Total number of bytes dropped on rx during PFC watchdog storm
16606 uint64_t rx_pfc_watchdog_storms_rx_bytes_dropped_pri1;
16608 * Total number of bytes dropped on rx during PFC watchdog storm
16611 uint64_t rx_pfc_watchdog_storms_rx_bytes_dropped_pri2;
16613 * Total number of bytes dropped on rx during PFC watchdog storm
16616 uint64_t rx_pfc_watchdog_storms_rx_bytes_dropped_pri3;
16618 * Total number of bytes dropped on rx during PFC watchdog storm
16621 uint64_t rx_pfc_watchdog_storms_rx_bytes_dropped_pri4;
16623 * Total number of bytes dropped on rx during PFC watchdog storm
16626 uint64_t rx_pfc_watchdog_storms_rx_bytes_dropped_pri5;
16628 * Total number of bytes dropped on rx during PFC watchdog storm
16631 uint64_t rx_pfc_watchdog_storms_rx_bytes_dropped_pri6;
16633 * Total number of bytes dropped on rx during PFC watchdog storm
16636 uint64_t rx_pfc_watchdog_storms_rx_bytes_dropped_pri7;
16638 * Number of packets received during last PFC watchdog storm
16641 uint64_t rx_pfc_watchdog_last_storm_rx_packets_pri0;
16643 * Number of packets received during last PFC watchdog storm
16646 uint64_t rx_pfc_watchdog_last_storm_rx_packets_pri1;
16648 * Number of packets received during last PFC watchdog storm
16651 uint64_t rx_pfc_watchdog_last_storm_rx_packets_pri2;
16653 * Number of packets received during last PFC watchdog storm
16656 uint64_t rx_pfc_watchdog_last_storm_rx_packets_pri3;
16658 * Number of packets received during last PFC watchdog storm
16661 uint64_t rx_pfc_watchdog_last_storm_rx_packets_pri4;
16663 * Number of packets received during last PFC watchdog storm
16666 uint64_t rx_pfc_watchdog_last_storm_rx_packets_pri5;
16668 * Number of packets received during last PFC watchdog storm
16671 uint64_t rx_pfc_watchdog_last_storm_rx_packets_pri6;
16673 * Number of packets received during last PFC watchdog storm
16676 uint64_t rx_pfc_watchdog_last_storm_rx_packets_pri7;
16678 * Number of bytes received during last PFC watchdog storm
16681 uint64_t rx_pfc_watchdog_last_storm_rx_bytes_pri0;
16683 * Number of bytes received during last PFC watchdog storm
16686 uint64_t rx_pfc_watchdog_last_storm_rx_bytes_pri1;
16688 * Number of bytes received during last PFC watchdog storm
16691 uint64_t rx_pfc_watchdog_last_storm_rx_bytes_pri2;
16693 * Number of bytes received during last PFC watchdog storm
16696 uint64_t rx_pfc_watchdog_last_storm_rx_bytes_pri3;
16698 * Number of bytes received during last PFC watchdog storm
16701 uint64_t rx_pfc_watchdog_last_storm_rx_bytes_pri4;
16703 * Number of bytes received during last PFC watchdog storm
16706 uint64_t rx_pfc_watchdog_last_storm_rx_bytes_pri5;
16708 * Number of bytes received during last PFC watchdog storm
16711 uint64_t rx_pfc_watchdog_last_storm_rx_bytes_pri6;
16713 * Number of bytes received during last PFC watchdog storm
16716 uint64_t rx_pfc_watchdog_last_storm_rx_bytes_pri7;
16718 * Number of packets dropped on rx during last PFC watchdog storm
16721 uint64_t rx_pfc_watchdog_last_storm_rx_packets_dropped_pri0;
16723 * Number of packets dropped on rx during last PFC watchdog storm
16726 uint64_t rx_pfc_watchdog_last_storm_rx_packets_dropped_pri1;
16728 * Number of packets dropped on rx during last PFC watchdog storm
16731 uint64_t rx_pfc_watchdog_last_storm_rx_packets_dropped_pri2;
16733 * Number of packets dropped on rx during last PFC watchdog storm
16736 uint64_t rx_pfc_watchdog_last_storm_rx_packets_dropped_pri3;
16738 * Number of packets dropped on rx during last PFC watchdog storm
16741 uint64_t rx_pfc_watchdog_last_storm_rx_packets_dropped_pri4;
16743 * Number of packets dropped on rx during last PFC watchdog storm
16746 uint64_t rx_pfc_watchdog_last_storm_rx_packets_dropped_pri5;
16748 * Number of packets dropped on rx during last PFC watchdog storm
16751 uint64_t rx_pfc_watchdog_last_storm_rx_packets_dropped_pri6;
16753 * Number of packets dropped on rx during last PFC watchdog storm
16756 uint64_t rx_pfc_watchdog_last_storm_rx_packets_dropped_pri7;
16758 * Total number of bytes dropped on rx during PFC watchdog storm
16761 uint64_t rx_pfc_watchdog_last_storm_rx_bytes_dropped_pri0;
16763 * Number of bytes dropped on rx during last PFC watchdog storm
16766 uint64_t rx_pfc_watchdog_last_storm_rx_bytes_dropped_pri1;
16768 * Number of bytes dropped on rx during last PFC watchdog storm
16771 uint64_t rx_pfc_watchdog_last_storm_rx_bytes_dropped_pri2;
16773 * Number of bytes dropped on rx during last PFC watchdog storm
16776 uint64_t rx_pfc_watchdog_last_storm_rx_bytes_dropped_pri3;
16778 * Number of bytes dropped on rx during last PFC watchdog storm
16781 uint64_t rx_pfc_watchdog_last_storm_rx_bytes_dropped_pri4;
16783 * Number of bytes dropped on rx during last PFC watchdog storm
16786 uint64_t rx_pfc_watchdog_last_storm_rx_bytes_dropped_pri5;
16788 * Number of bytes dropped on rx during last PFC watchdog storm
16791 uint64_t rx_pfc_watchdog_last_storm_rx_bytes_dropped_pri6;
16793 * Number of bytes dropped on rx during last PFC watchdog storm
16796 uint64_t rx_pfc_watchdog_last_storm_rx_bytes_dropped_pri7;
16799 /************************
16800 * hwrm_port_qstats_ext *
16801 ************************/
16804 /* hwrm_port_qstats_ext_input (size:320b/40B) */
16805 struct hwrm_port_qstats_ext_input {
16806 /* The HWRM command request type. */
16809 * The completion ring to send the completion event on. This should
16810 * be the NQ ID returned from the `nq_alloc` HWRM command.
16812 uint16_t cmpl_ring;
16814 * The sequence ID is used by the driver for tracking multiple
16815 * commands. This ID is treated as opaque data by the firmware and
16816 * the value is returned in the `hwrm_resp_hdr` upon completion.
16820 * The target ID of the command:
16821 * * 0x0-0xFFF8 - The function ID
16822 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
16823 * * 0xFFFD - Reserved for user-space HWRM interface
16826 uint16_t target_id;
16828 * A physical address pointer pointing to a host buffer that the
16829 * command's response data will be written. This can be either a host
16830 * physical address (HPA) or a guest physical address (GPA) and must
16831 * point to a physically contiguous block of memory.
16833 uint64_t resp_addr;
16834 /* Port ID of port that is being queried. */
16837 * The size of TX port extended
16838 * statistics block in bytes.
16840 uint16_t tx_stat_size;
16842 * The size of RX port extended
16843 * statistics block in bytes
16845 uint16_t rx_stat_size;
16846 uint8_t unused_0[2];
16848 * This is the host address where
16849 * Tx port statistics will be stored
16851 uint64_t tx_stat_host_addr;
16853 * This is the host address where
16854 * Rx port statistics will be stored
16856 uint64_t rx_stat_host_addr;
16859 /* hwrm_port_qstats_ext_output (size:128b/16B) */
16860 struct hwrm_port_qstats_ext_output {
16861 /* The specific error status for the command. */
16862 uint16_t error_code;
16863 /* The HWRM command request type. */
16865 /* The sequence ID from the original command. */
16867 /* The length of the response data in number of bytes. */
16869 /* The size of TX port statistics block in bytes. */
16870 uint16_t tx_stat_size;
16871 /* The size of RX port statistics block in bytes. */
16872 uint16_t rx_stat_size;
16873 /* Total number of active cos queues available. */
16874 uint16_t total_active_cos_queues;
16877 * If set to 1, then this field indicates that clear
16878 * roce specific counters is supported.
16880 #define HWRM_PORT_QSTATS_EXT_OUTPUT_FLAGS_CLEAR_ROCE_COUNTERS_SUPPORTED \
16883 * This field is used in Output records to indicate that the output
16884 * is completely written to RAM. This field should be read as '1'
16885 * to indicate that the output has been completely written.
16886 * When writing a command completion or response to an internal processor,
16887 * the order of writes has to be such that this field is written last.
16892 /*******************************
16893 * hwrm_port_qstats_ext_pfc_wd *
16894 *******************************/
16897 /* hwrm_port_qstats_ext_pfc_wd_input (size:256b/32B) */
16898 struct hwrm_port_qstats_ext_pfc_wd_input {
16899 /* The HWRM command request type. */
16902 * The completion ring to send the completion event on. This should
16903 * be the NQ ID returned from the `nq_alloc` HWRM command.
16905 uint16_t cmpl_ring;
16907 * The sequence ID is used by the driver for tracking multiple
16908 * commands. This ID is treated as opaque data by the firmware and
16909 * the value is returned in the `hwrm_resp_hdr` upon completion.
16913 * The target ID of the command:
16914 * * 0x0-0xFFF8 - The function ID
16915 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
16916 * * 0xFFFD - Reserved for user-space HWRM interface
16919 uint16_t target_id;
16921 * A physical address pointer pointing to a host buffer that the
16922 * command's response data will be written. This can be either a host
16923 * physical address (HPA) or a guest physical address (GPA) and must
16924 * point to a physically contiguous block of memory.
16926 uint64_t resp_addr;
16927 /* Port ID of port that is being queried. */
16930 * The size of rx_port_stats_ext_pfc_wd
16933 uint16_t pfc_wd_stat_size;
16934 uint8_t unused_0[4];
16936 * This is the host address where
16937 * rx_port_stats_ext_pfc_wd will be stored
16939 uint64_t pfc_wd_stat_host_addr;
16942 /* hwrm_port_qstats_ext_pfc_wd_output (size:128b/16B) */
16943 struct hwrm_port_qstats_ext_pfc_wd_output {
16944 /* The specific error status for the command. */
16945 uint16_t error_code;
16946 /* The HWRM command request type. */
16948 /* The sequence ID from the original command. */
16950 /* The length of the response data in number of bytes. */
16953 * The size of rx_port_stats_ext_pfc_wd
16954 * statistics block in bytes.
16956 uint16_t pfc_wd_stat_size;
16959 * This field is used in Output records to indicate that the output
16960 * is completely written to RAM. This field should be read as '1'
16961 * to indicate that the output has been completely written.
16962 * When writing a command completion or response to an internal processor,
16963 * the order of writes has to be such that this field is written last.
16966 uint8_t unused_0[4];
16969 /*************************
16970 * hwrm_port_lpbk_qstats *
16971 *************************/
16974 /* hwrm_port_lpbk_qstats_input (size:128b/16B) */
16975 struct hwrm_port_lpbk_qstats_input {
16976 /* The HWRM command request type. */
16979 * The completion ring to send the completion event on. This should
16980 * be the NQ ID returned from the `nq_alloc` HWRM command.
16982 uint16_t cmpl_ring;
16984 * The sequence ID is used by the driver for tracking multiple
16985 * commands. This ID is treated as opaque data by the firmware and
16986 * the value is returned in the `hwrm_resp_hdr` upon completion.
16990 * The target ID of the command:
16991 * * 0x0-0xFFF8 - The function ID
16992 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
16993 * * 0xFFFD - Reserved for user-space HWRM interface
16996 uint16_t target_id;
16998 * A physical address pointer pointing to a host buffer that the
16999 * command's response data will be written. This can be either a host
17000 * physical address (HPA) or a guest physical address (GPA) and must
17001 * point to a physically contiguous block of memory.
17003 uint64_t resp_addr;
17006 /* hwrm_port_lpbk_qstats_output (size:768b/96B) */
17007 struct hwrm_port_lpbk_qstats_output {
17008 /* The specific error status for the command. */
17009 uint16_t error_code;
17010 /* The HWRM command request type. */
17012 /* The sequence ID from the original command. */
17014 /* The length of the response data in number of bytes. */
17016 /* Number of transmitted unicast frames */
17017 uint64_t lpbk_ucast_frames;
17018 /* Number of transmitted multicast frames */
17019 uint64_t lpbk_mcast_frames;
17020 /* Number of transmitted broadcast frames */
17021 uint64_t lpbk_bcast_frames;
17022 /* Number of transmitted bytes for unicast traffic */
17023 uint64_t lpbk_ucast_bytes;
17024 /* Number of transmitted bytes for multicast traffic */
17025 uint64_t lpbk_mcast_bytes;
17026 /* Number of transmitted bytes for broadcast traffic */
17027 uint64_t lpbk_bcast_bytes;
17028 /* Total Tx Drops for loopback traffic reported by STATS block */
17029 uint64_t tx_stat_discard;
17030 /* Total Tx Error Drops for loopback traffic reported by STATS block */
17031 uint64_t tx_stat_error;
17032 /* Total Rx Drops for loopback traffic reported by STATS block */
17033 uint64_t rx_stat_discard;
17034 /* Total Rx Error Drops for loopback traffic reported by STATS block */
17035 uint64_t rx_stat_error;
17036 uint8_t unused_0[7];
17038 * This field is used in Output records to indicate that the output
17039 * is completely written to RAM. This field should be read as '1'
17040 * to indicate that the output has been completely written.
17041 * When writing a command completion or response to an internal processor,
17042 * the order of writes has to be such that this field is written last.
17047 /************************
17048 * hwrm_port_ecn_qstats *
17049 ************************/
17052 /* hwrm_port_ecn_qstats_input (size:192b/24B) */
17053 struct hwrm_port_ecn_qstats_input {
17054 /* The HWRM command request type. */
17057 * The completion ring to send the completion event on. This should
17058 * be the NQ ID returned from the `nq_alloc` HWRM command.
17060 uint16_t cmpl_ring;
17062 * The sequence ID is used by the driver for tracking multiple
17063 * commands. This ID is treated as opaque data by the firmware and
17064 * the value is returned in the `hwrm_resp_hdr` upon completion.
17068 * The target ID of the command:
17069 * * 0x0-0xFFF8 - The function ID
17070 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
17071 * * 0xFFFD - Reserved for user-space HWRM interface
17074 uint16_t target_id;
17076 * A physical address pointer pointing to a host buffer that the
17077 * command's response data will be written. This can be either a host
17078 * physical address (HPA) or a guest physical address (GPA) and must
17079 * point to a physically contiguous block of memory.
17081 uint64_t resp_addr;
17083 * Port ID of port that is being queried. Unused if NIC is in
17087 uint8_t unused_0[6];
17090 /* hwrm_port_ecn_qstats_output (size:384b/48B) */
17091 struct hwrm_port_ecn_qstats_output {
17092 /* The specific error status for the command. */
17093 uint16_t error_code;
17094 /* The HWRM command request type. */
17096 /* The sequence ID from the original command. */
17098 /* The length of the response data in number of bytes. */
17100 /* Number of packets marked in CoS queue 0. */
17101 uint32_t mark_cnt_cos0;
17102 /* Number of packets marked in CoS queue 1. */
17103 uint32_t mark_cnt_cos1;
17104 /* Number of packets marked in CoS queue 2. */
17105 uint32_t mark_cnt_cos2;
17106 /* Number of packets marked in CoS queue 3. */
17107 uint32_t mark_cnt_cos3;
17108 /* Number of packets marked in CoS queue 4. */
17109 uint32_t mark_cnt_cos4;
17110 /* Number of packets marked in CoS queue 5. */
17111 uint32_t mark_cnt_cos5;
17112 /* Number of packets marked in CoS queue 6. */
17113 uint32_t mark_cnt_cos6;
17114 /* Number of packets marked in CoS queue 7. */
17115 uint32_t mark_cnt_cos7;
17117 * Bitmask that indicates which CoS queues have ECN marking enabled.
17118 * Bit i corresponds to CoS queue i.
17121 uint8_t unused_0[6];
17123 * This field is used in Output records to indicate that the output
17124 * is completely written to RAM. This field should be read as '1'
17125 * to indicate that the output has been completely written.
17126 * When writing a command completion or response to an internal processor,
17127 * the order of writes has to be such that this field is written last.
17132 /***********************
17133 * hwrm_port_clr_stats *
17134 ***********************/
17137 /* hwrm_port_clr_stats_input (size:192b/24B) */
17138 struct hwrm_port_clr_stats_input {
17139 /* The HWRM command request type. */
17142 * The completion ring to send the completion event on. This should
17143 * be the NQ ID returned from the `nq_alloc` HWRM command.
17145 uint16_t cmpl_ring;
17147 * The sequence ID is used by the driver for tracking multiple
17148 * commands. This ID is treated as opaque data by the firmware and
17149 * the value is returned in the `hwrm_resp_hdr` upon completion.
17153 * The target ID of the command:
17154 * * 0x0-0xFFF8 - The function ID
17155 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
17156 * * 0xFFFD - Reserved for user-space HWRM interface
17159 uint16_t target_id;
17161 * A physical address pointer pointing to a host buffer that the
17162 * command's response data will be written. This can be either a host
17163 * physical address (HPA) or a guest physical address (GPA) and must
17164 * point to a physically contiguous block of memory.
17166 uint64_t resp_addr;
17167 /* Port ID of port that is being queried. */
17171 * If set to 1, then this field indicates clear the following RoCE
17172 * specific counters.
17173 * RoCE associated TX/RX cos counters
17174 * CNP associated TX/RX cos counters
17175 * RoCE/CNP specific TX/RX flow counters
17176 * Firmware will determine the RoCE/CNP cos queue based on qos profile.
17177 * This flag is honored only when RoCE is enabled on that port.
17179 #define HWRM_PORT_CLR_STATS_INPUT_FLAGS_ROCE_COUNTERS UINT32_C(0x1)
17180 uint8_t unused_0[5];
17183 /* hwrm_port_clr_stats_output (size:128b/16B) */
17184 struct hwrm_port_clr_stats_output {
17185 /* The specific error status for the command. */
17186 uint16_t error_code;
17187 /* The HWRM command request type. */
17189 /* The sequence ID from the original command. */
17191 /* The length of the response data in number of bytes. */
17193 uint8_t unused_0[7];
17195 * This field is used in Output records to indicate that the output
17196 * is completely written to RAM. This field should be read as '1'
17197 * to indicate that the output has been completely written.
17198 * When writing a command completion or response to an internal processor,
17199 * the order of writes has to be such that this field is written last.
17204 /***********************
17205 * hwrm_port_phy_qcaps *
17206 ***********************/
17209 /* hwrm_port_phy_qcaps_input (size:192b/24B) */
17210 struct hwrm_port_phy_qcaps_input {
17211 /* The HWRM command request type. */
17214 * The completion ring to send the completion event on. This should
17215 * be the NQ ID returned from the `nq_alloc` HWRM command.
17217 uint16_t cmpl_ring;
17219 * The sequence ID is used by the driver for tracking multiple
17220 * commands. This ID is treated as opaque data by the firmware and
17221 * the value is returned in the `hwrm_resp_hdr` upon completion.
17225 * The target ID of the command:
17226 * * 0x0-0xFFF8 - The function ID
17227 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
17228 * * 0xFFFD - Reserved for user-space HWRM interface
17231 uint16_t target_id;
17233 * A physical address pointer pointing to a host buffer that the
17234 * command's response data will be written. This can be either a host
17235 * physical address (HPA) or a guest physical address (GPA) and must
17236 * point to a physically contiguous block of memory.
17238 uint64_t resp_addr;
17239 /* Port ID of port that is being queried. */
17241 uint8_t unused_0[6];
17244 /* hwrm_port_phy_qcaps_output (size:192b/24B) */
17245 struct hwrm_port_phy_qcaps_output {
17246 /* The specific error status for the command. */
17247 uint16_t error_code;
17248 /* The HWRM command request type. */
17250 /* The sequence ID from the original command. */
17252 /* The length of the response data in number of bytes. */
17254 /* PHY capability flags */
17257 * If set to 1, then this field indicates that the
17258 * link is capable of supporting EEE.
17260 #define HWRM_PORT_PHY_QCAPS_OUTPUT_FLAGS_EEE_SUPPORTED \
17263 * If set to 1, then this field indicates that the
17264 * PHY is capable of supporting external loopback.
17266 #define HWRM_PORT_PHY_QCAPS_OUTPUT_FLAGS_EXTERNAL_LPBK_SUPPORTED \
17269 * If set to 1, then this field indicates that the
17270 * PHY is capable of supporting loopback in autoneg mode.
17272 #define HWRM_PORT_PHY_QCAPS_OUTPUT_FLAGS_AUTONEG_LPBK_SUPPORTED \
17275 * Indicates if the configuration of shared PHY settings is supported.
17276 * In cases where a physical port is shared by multiple functions
17277 * (e.g. NPAR, multihost, etc), the configuration of PHY
17278 * settings may not be allowed. Callers to HWRM_PORT_PHY_CFG will
17279 * get an HWRM_ERR_CODE_RESOURCE_ACCESS_DENIED error in this case.
17281 #define HWRM_PORT_PHY_QCAPS_OUTPUT_FLAGS_SHARED_PHY_CFG_SUPPORTED \
17284 * Reserved field. The HWRM shall set this field to 0.
17285 * An HWRM client shall ignore this field.
17287 #define HWRM_PORT_PHY_QCAPS_OUTPUT_FLAGS_RSVD1_MASK \
17289 #define HWRM_PORT_PHY_QCAPS_OUTPUT_FLAGS_RSVD1_SFT 4
17290 /* Number of front panel ports for this device. */
17292 /* Not supported or unknown */
17293 #define HWRM_PORT_PHY_QCAPS_OUTPUT_PORT_CNT_UNKNOWN UINT32_C(0x0)
17294 /* single port device */
17295 #define HWRM_PORT_PHY_QCAPS_OUTPUT_PORT_CNT_1 UINT32_C(0x1)
17296 /* 2-port device */
17297 #define HWRM_PORT_PHY_QCAPS_OUTPUT_PORT_CNT_2 UINT32_C(0x2)
17298 /* 3-port device */
17299 #define HWRM_PORT_PHY_QCAPS_OUTPUT_PORT_CNT_3 UINT32_C(0x3)
17300 /* 4-port device */
17301 #define HWRM_PORT_PHY_QCAPS_OUTPUT_PORT_CNT_4 UINT32_C(0x4)
17302 #define HWRM_PORT_PHY_QCAPS_OUTPUT_PORT_CNT_LAST \
17303 HWRM_PORT_PHY_QCAPS_OUTPUT_PORT_CNT_4
17305 * This is a bit mask to indicate what speeds are supported
17306 * as forced speeds on this link.
17307 * For each speed that can be forced on this link, the
17308 * corresponding mask bit shall be set to '1'.
17310 uint16_t supported_speeds_force_mode;
17311 /* 100Mb link speed (Half-duplex) */
17312 #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_FORCE_MODE_100MBHD \
17314 /* 100Mb link speed (Full-duplex) */
17315 #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_FORCE_MODE_100MB \
17317 /* 1Gb link speed (Half-duplex) */
17318 #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_FORCE_MODE_1GBHD \
17320 /* 1Gb link speed (Full-duplex) */
17321 #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_FORCE_MODE_1GB \
17323 /* 2Gb link speed */
17324 #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_FORCE_MODE_2GB \
17326 /* 25Gb link speed */
17327 #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_FORCE_MODE_2_5GB \
17329 /* 10Gb link speed */
17330 #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_FORCE_MODE_10GB \
17332 /* 20Gb link speed */
17333 #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_FORCE_MODE_20GB \
17335 /* 25Gb link speed */
17336 #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_FORCE_MODE_25GB \
17338 /* 40Gb link speed */
17339 #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_FORCE_MODE_40GB \
17341 /* 50Gb link speed */
17342 #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_FORCE_MODE_50GB \
17344 /* 100Gb link speed */
17345 #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_FORCE_MODE_100GB \
17347 /* 10Mb link speed (Half-duplex) */
17348 #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_FORCE_MODE_10MBHD \
17350 /* 10Mb link speed (Full-duplex) */
17351 #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_FORCE_MODE_10MB \
17353 /* 200Gb link speed */
17354 #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_FORCE_MODE_200GB \
17357 * This is a bit mask to indicate what speeds are supported
17358 * for autonegotiation on this link.
17359 * For each speed that can be autonegotiated on this link, the
17360 * corresponding mask bit shall be set to '1'.
17362 uint16_t supported_speeds_auto_mode;
17363 /* 100Mb link speed (Half-duplex) */
17364 #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_AUTO_MODE_100MBHD \
17366 /* 100Mb link speed (Full-duplex) */
17367 #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_AUTO_MODE_100MB \
17369 /* 1Gb link speed (Half-duplex) */
17370 #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_AUTO_MODE_1GBHD \
17372 /* 1Gb link speed (Full-duplex) */
17373 #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_AUTO_MODE_1GB \
17375 /* 2Gb link speed */
17376 #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_AUTO_MODE_2GB \
17378 /* 25Gb link speed */
17379 #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_AUTO_MODE_2_5GB \
17381 /* 10Gb link speed */
17382 #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_AUTO_MODE_10GB \
17384 /* 20Gb link speed */
17385 #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_AUTO_MODE_20GB \
17387 /* 25Gb link speed */
17388 #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_AUTO_MODE_25GB \
17390 /* 40Gb link speed */
17391 #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_AUTO_MODE_40GB \
17393 /* 50Gb link speed */
17394 #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_AUTO_MODE_50GB \
17396 /* 100Gb link speed */
17397 #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_AUTO_MODE_100GB \
17399 /* 10Mb link speed (Half-duplex) */
17400 #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_AUTO_MODE_10MBHD \
17402 /* 10Mb link speed (Full-duplex) */
17403 #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_AUTO_MODE_10MB \
17405 /* 200Gb link speed */
17406 #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_AUTO_MODE_200GB \
17409 * This is a bit mask to indicate what speeds are supported
17410 * for EEE on this link.
17411 * For each speed that can be autonegotiated when EEE is enabled
17412 * on this link, the corresponding mask bit shall be set to '1'.
17413 * This field is only valid when the eee_suppotred is set to '1'.
17415 uint16_t supported_speeds_eee_mode;
17417 #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_EEE_MODE_RSVD1 \
17419 /* 100Mb link speed (Full-duplex) */
17420 #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_EEE_MODE_100MB \
17423 #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_EEE_MODE_RSVD2 \
17425 /* 1Gb link speed (Full-duplex) */
17426 #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_EEE_MODE_1GB \
17429 #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_EEE_MODE_RSVD3 \
17432 #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_EEE_MODE_RSVD4 \
17434 /* 10Gb link speed */
17435 #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_EEE_MODE_10GB \
17437 uint32_t tx_lpi_timer_low;
17439 * The lowest value of TX LPI timer that can be set on this link
17440 * when EEE is enabled. This value is in microseconds.
17441 * This field is valid only when_eee_supported is set to '1'.
17443 #define HWRM_PORT_PHY_QCAPS_OUTPUT_TX_LPI_TIMER_LOW_MASK \
17445 #define HWRM_PORT_PHY_QCAPS_OUTPUT_TX_LPI_TIMER_LOW_SFT 0
17447 * Reserved field. The HWRM shall set this field to 0.
17448 * An HWRM client shall ignore this field.
17450 #define HWRM_PORT_PHY_QCAPS_OUTPUT_RSVD2_MASK \
17451 UINT32_C(0xff000000)
17452 #define HWRM_PORT_PHY_QCAPS_OUTPUT_RSVD2_SFT 24
17453 uint32_t valid_tx_lpi_timer_high;
17455 * The highest value of TX LPI timer that can be set on this link
17456 * when EEE is enabled. This value is in microseconds.
17457 * This field is valid only when_eee_supported is set to '1'.
17459 #define HWRM_PORT_PHY_QCAPS_OUTPUT_TX_LPI_TIMER_HIGH_MASK \
17461 #define HWRM_PORT_PHY_QCAPS_OUTPUT_TX_LPI_TIMER_HIGH_SFT 0
17463 * This field is used in Output records to indicate that the output
17464 * is completely written to RAM. This field should be read as '1'
17465 * to indicate that the output has been completely written.
17466 * When writing a command completion or response to an internal processor,
17467 * the order of writes has to be such that this field is written last.
17469 #define HWRM_PORT_PHY_QCAPS_OUTPUT_VALID_MASK \
17470 UINT32_C(0xff000000)
17471 #define HWRM_PORT_PHY_QCAPS_OUTPUT_VALID_SFT 24
17474 /****************************
17475 * hwrm_port_phy_mdio_write *
17476 ****************************/
17479 /* hwrm_port_phy_mdio_write_input (size:320b/40B) */
17480 struct hwrm_port_phy_mdio_write_input {
17481 /* The HWRM command request type. */
17484 * The completion ring to send the completion event on. This should
17485 * be the NQ ID returned from the `nq_alloc` HWRM command.
17487 uint16_t cmpl_ring;
17489 * The sequence ID is used by the driver for tracking multiple
17490 * commands. This ID is treated as opaque data by the firmware and
17491 * the value is returned in the `hwrm_resp_hdr` upon completion.
17495 * The target ID of the command:
17496 * * 0x0-0xFFF8 - The function ID
17497 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
17498 * * 0xFFFD - Reserved for user-space HWRM interface
17501 uint16_t target_id;
17503 * A physical address pointer pointing to a host buffer that the
17504 * command's response data will be written. This can be either a host
17505 * physical address (HPA) or a guest physical address (GPA) and must
17506 * point to a physically contiguous block of memory.
17508 uint64_t resp_addr;
17509 /* Reserved for future use. */
17510 uint32_t unused_0[2];
17511 /* Port ID of port. */
17513 /* If phy_address is 0xFF, port_id will be used to derive phy_addr. */
17515 /* 8-bit device address. */
17517 /* 16-bit register address. */
17519 /* 16-bit register data. */
17522 * When this bit is set to 1 a Clause 45 mdio access is done.
17523 * when this bit is set to 0 a Clause 22 mdio access is done.
17527 uint8_t unused_1[7];
17530 /* hwrm_port_phy_mdio_write_output (size:128b/16B) */
17531 struct hwrm_port_phy_mdio_write_output {
17532 /* The specific error status for the command. */
17533 uint16_t error_code;
17534 /* The HWRM command request type. */
17536 /* The sequence ID from the original command. */
17538 /* The length of the response data in number of bytes. */
17540 uint8_t unused_0[7];
17542 * This field is used in Output records to indicate that the output
17543 * is completely written to RAM. This field should be read as '1'
17544 * to indicate that the output has been completely written.
17545 * When writing a command completion or response to an internal processor,
17546 * the order of writes has to be such that this field is written last.
17551 /***************************
17552 * hwrm_port_phy_mdio_read *
17553 ***************************/
17556 /* hwrm_port_phy_mdio_read_input (size:256b/32B) */
17557 struct hwrm_port_phy_mdio_read_input {
17558 /* The HWRM command request type. */
17561 * The completion ring to send the completion event on. This should
17562 * be the NQ ID returned from the `nq_alloc` HWRM command.
17564 uint16_t cmpl_ring;
17566 * The sequence ID is used by the driver for tracking multiple
17567 * commands. This ID is treated as opaque data by the firmware and
17568 * the value is returned in the `hwrm_resp_hdr` upon completion.
17572 * The target ID of the command:
17573 * * 0x0-0xFFF8 - The function ID
17574 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
17575 * * 0xFFFD - Reserved for user-space HWRM interface
17578 uint16_t target_id;
17580 * A physical address pointer pointing to a host buffer that the
17581 * command's response data will be written. This can be either a host
17582 * physical address (HPA) or a guest physical address (GPA) and must
17583 * point to a physically contiguous block of memory.
17585 uint64_t resp_addr;
17586 /* Reserved for future use. */
17587 uint32_t unused_0[2];
17588 /* Port ID of port. */
17590 /* If phy_address is 0xFF, port_id will be used to derive phy_addr. */
17592 /* 8-bit device address. */
17594 /* 16-bit register address. */
17597 * When this bit is set to 1 a Clause 45 mdio access is done.
17598 * when this bit is set to 0 a Clause 22 mdio access is done.
17605 /* hwrm_port_phy_mdio_read_output (size:128b/16B) */
17606 struct hwrm_port_phy_mdio_read_output {
17607 /* The specific error status for the command. */
17608 uint16_t error_code;
17609 /* The HWRM command request type. */
17611 /* The sequence ID from the original command. */
17613 /* The length of the response data in number of bytes. */
17615 /* 16-bit register data. */
17617 uint8_t unused_0[5];
17619 * This field is used in Output records to indicate that the output
17620 * is completely written to RAM. This field should be read as '1'
17621 * to indicate that the output has been completely written.
17622 * When writing a command completion or response to an internal processor,
17623 * the order of writes has to be such that this field is written last.
17628 /*********************
17629 * hwrm_port_led_cfg *
17630 *********************/
17633 /* hwrm_port_led_cfg_input (size:512b/64B) */
17634 struct hwrm_port_led_cfg_input {
17635 /* The HWRM command request type. */
17638 * The completion ring to send the completion event on. This should
17639 * be the NQ ID returned from the `nq_alloc` HWRM command.
17641 uint16_t cmpl_ring;
17643 * The sequence ID is used by the driver for tracking multiple
17644 * commands. This ID is treated as opaque data by the firmware and
17645 * the value is returned in the `hwrm_resp_hdr` upon completion.
17649 * The target ID of the command:
17650 * * 0x0-0xFFF8 - The function ID
17651 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
17652 * * 0xFFFD - Reserved for user-space HWRM interface
17655 uint16_t target_id;
17657 * A physical address pointer pointing to a host buffer that the
17658 * command's response data will be written. This can be either a host
17659 * physical address (HPA) or a guest physical address (GPA) and must
17660 * point to a physically contiguous block of memory.
17662 uint64_t resp_addr;
17665 * This bit must be '1' for the led0_id field to be
17668 #define HWRM_PORT_LED_CFG_INPUT_ENABLES_LED0_ID \
17671 * This bit must be '1' for the led0_state field to be
17674 #define HWRM_PORT_LED_CFG_INPUT_ENABLES_LED0_STATE \
17677 * This bit must be '1' for the led0_color field to be
17680 #define HWRM_PORT_LED_CFG_INPUT_ENABLES_LED0_COLOR \
17683 * This bit must be '1' for the led0_blink_on field to be
17686 #define HWRM_PORT_LED_CFG_INPUT_ENABLES_LED0_BLINK_ON \
17689 * This bit must be '1' for the led0_blink_off field to be
17692 #define HWRM_PORT_LED_CFG_INPUT_ENABLES_LED0_BLINK_OFF \
17695 * This bit must be '1' for the led0_group_id field to be
17698 #define HWRM_PORT_LED_CFG_INPUT_ENABLES_LED0_GROUP_ID \
17701 * This bit must be '1' for the led1_id field to be
17704 #define HWRM_PORT_LED_CFG_INPUT_ENABLES_LED1_ID \
17707 * This bit must be '1' for the led1_state field to be
17710 #define HWRM_PORT_LED_CFG_INPUT_ENABLES_LED1_STATE \
17713 * This bit must be '1' for the led1_color field to be
17716 #define HWRM_PORT_LED_CFG_INPUT_ENABLES_LED1_COLOR \
17719 * This bit must be '1' for the led1_blink_on field to be
17722 #define HWRM_PORT_LED_CFG_INPUT_ENABLES_LED1_BLINK_ON \
17725 * This bit must be '1' for the led1_blink_off field to be
17728 #define HWRM_PORT_LED_CFG_INPUT_ENABLES_LED1_BLINK_OFF \
17731 * This bit must be '1' for the led1_group_id field to be
17734 #define HWRM_PORT_LED_CFG_INPUT_ENABLES_LED1_GROUP_ID \
17737 * This bit must be '1' for the led2_id field to be
17740 #define HWRM_PORT_LED_CFG_INPUT_ENABLES_LED2_ID \
17743 * This bit must be '1' for the led2_state field to be
17746 #define HWRM_PORT_LED_CFG_INPUT_ENABLES_LED2_STATE \
17749 * This bit must be '1' for the led2_color field to be
17752 #define HWRM_PORT_LED_CFG_INPUT_ENABLES_LED2_COLOR \
17755 * This bit must be '1' for the led2_blink_on field to be
17758 #define HWRM_PORT_LED_CFG_INPUT_ENABLES_LED2_BLINK_ON \
17761 * This bit must be '1' for the led2_blink_off field to be
17764 #define HWRM_PORT_LED_CFG_INPUT_ENABLES_LED2_BLINK_OFF \
17767 * This bit must be '1' for the led2_group_id field to be
17770 #define HWRM_PORT_LED_CFG_INPUT_ENABLES_LED2_GROUP_ID \
17773 * This bit must be '1' for the led3_id field to be
17776 #define HWRM_PORT_LED_CFG_INPUT_ENABLES_LED3_ID \
17779 * This bit must be '1' for the led3_state field to be
17782 #define HWRM_PORT_LED_CFG_INPUT_ENABLES_LED3_STATE \
17785 * This bit must be '1' for the led3_color field to be
17788 #define HWRM_PORT_LED_CFG_INPUT_ENABLES_LED3_COLOR \
17791 * This bit must be '1' for the led3_blink_on field to be
17794 #define HWRM_PORT_LED_CFG_INPUT_ENABLES_LED3_BLINK_ON \
17797 * This bit must be '1' for the led3_blink_off field to be
17800 #define HWRM_PORT_LED_CFG_INPUT_ENABLES_LED3_BLINK_OFF \
17803 * This bit must be '1' for the led3_group_id field to be
17806 #define HWRM_PORT_LED_CFG_INPUT_ENABLES_LED3_GROUP_ID \
17808 /* Port ID of port whose LEDs are configured. */
17811 * The number of LEDs that are being configured.
17812 * Up to 4 LEDs can be configured with this command.
17815 /* Reserved field. */
17817 /* An identifier for the LED #0. */
17819 /* The requested state of the LED #0. */
17820 uint8_t led0_state;
17821 /* Default state of the LED */
17822 #define HWRM_PORT_LED_CFG_INPUT_LED0_STATE_DEFAULT UINT32_C(0x0)
17824 #define HWRM_PORT_LED_CFG_INPUT_LED0_STATE_OFF UINT32_C(0x1)
17826 #define HWRM_PORT_LED_CFG_INPUT_LED0_STATE_ON UINT32_C(0x2)
17828 #define HWRM_PORT_LED_CFG_INPUT_LED0_STATE_BLINK UINT32_C(0x3)
17829 /* Blink Alternately */
17830 #define HWRM_PORT_LED_CFG_INPUT_LED0_STATE_BLINKALT UINT32_C(0x4)
17831 #define HWRM_PORT_LED_CFG_INPUT_LED0_STATE_LAST \
17832 HWRM_PORT_LED_CFG_INPUT_LED0_STATE_BLINKALT
17833 /* The requested color of LED #0. */
17834 uint8_t led0_color;
17836 #define HWRM_PORT_LED_CFG_INPUT_LED0_COLOR_DEFAULT UINT32_C(0x0)
17838 #define HWRM_PORT_LED_CFG_INPUT_LED0_COLOR_AMBER UINT32_C(0x1)
17840 #define HWRM_PORT_LED_CFG_INPUT_LED0_COLOR_GREEN UINT32_C(0x2)
17841 /* Green or Amber */
17842 #define HWRM_PORT_LED_CFG_INPUT_LED0_COLOR_GREENAMBER UINT32_C(0x3)
17843 #define HWRM_PORT_LED_CFG_INPUT_LED0_COLOR_LAST \
17844 HWRM_PORT_LED_CFG_INPUT_LED0_COLOR_GREENAMBER
17847 * If the LED #0 state is "blink" or "blinkalt", then
17848 * this field represents the requested time in milliseconds
17849 * to keep LED on between cycles.
17851 uint16_t led0_blink_on;
17853 * If the LED #0 state is "blink" or "blinkalt", then
17854 * this field represents the requested time in milliseconds
17855 * to keep LED off between cycles.
17857 uint16_t led0_blink_off;
17859 * An identifier for the group of LEDs that LED #0 belongs
17861 * If set to 0, then the LED #0 shall not be grouped and
17862 * shall be treated as an individual resource.
17863 * For all other non-zero values of this field, LED #0 shall
17864 * be grouped together with the LEDs with the same group ID
17867 uint8_t led0_group_id;
17868 /* Reserved field. */
17870 /* An identifier for the LED #1. */
17872 /* The requested state of the LED #1. */
17873 uint8_t led1_state;
17874 /* Default state of the LED */
17875 #define HWRM_PORT_LED_CFG_INPUT_LED1_STATE_DEFAULT UINT32_C(0x0)
17877 #define HWRM_PORT_LED_CFG_INPUT_LED1_STATE_OFF UINT32_C(0x1)
17879 #define HWRM_PORT_LED_CFG_INPUT_LED1_STATE_ON UINT32_C(0x2)
17881 #define HWRM_PORT_LED_CFG_INPUT_LED1_STATE_BLINK UINT32_C(0x3)
17882 /* Blink Alternately */
17883 #define HWRM_PORT_LED_CFG_INPUT_LED1_STATE_BLINKALT UINT32_C(0x4)
17884 #define HWRM_PORT_LED_CFG_INPUT_LED1_STATE_LAST \
17885 HWRM_PORT_LED_CFG_INPUT_LED1_STATE_BLINKALT
17886 /* The requested color of LED #1. */
17887 uint8_t led1_color;
17889 #define HWRM_PORT_LED_CFG_INPUT_LED1_COLOR_DEFAULT UINT32_C(0x0)
17891 #define HWRM_PORT_LED_CFG_INPUT_LED1_COLOR_AMBER UINT32_C(0x1)
17893 #define HWRM_PORT_LED_CFG_INPUT_LED1_COLOR_GREEN UINT32_C(0x2)
17894 /* Green or Amber */
17895 #define HWRM_PORT_LED_CFG_INPUT_LED1_COLOR_GREENAMBER UINT32_C(0x3)
17896 #define HWRM_PORT_LED_CFG_INPUT_LED1_COLOR_LAST \
17897 HWRM_PORT_LED_CFG_INPUT_LED1_COLOR_GREENAMBER
17900 * If the LED #1 state is "blink" or "blinkalt", then
17901 * this field represents the requested time in milliseconds
17902 * to keep LED on between cycles.
17904 uint16_t led1_blink_on;
17906 * If the LED #1 state is "blink" or "blinkalt", then
17907 * this field represents the requested time in milliseconds
17908 * to keep LED off between cycles.
17910 uint16_t led1_blink_off;
17912 * An identifier for the group of LEDs that LED #1 belongs
17914 * If set to 0, then the LED #1 shall not be grouped and
17915 * shall be treated as an individual resource.
17916 * For all other non-zero values of this field, LED #1 shall
17917 * be grouped together with the LEDs with the same group ID
17920 uint8_t led1_group_id;
17921 /* Reserved field. */
17923 /* An identifier for the LED #2. */
17925 /* The requested state of the LED #2. */
17926 uint8_t led2_state;
17927 /* Default state of the LED */
17928 #define HWRM_PORT_LED_CFG_INPUT_LED2_STATE_DEFAULT UINT32_C(0x0)
17930 #define HWRM_PORT_LED_CFG_INPUT_LED2_STATE_OFF UINT32_C(0x1)
17932 #define HWRM_PORT_LED_CFG_INPUT_LED2_STATE_ON UINT32_C(0x2)
17934 #define HWRM_PORT_LED_CFG_INPUT_LED2_STATE_BLINK UINT32_C(0x3)
17935 /* Blink Alternately */
17936 #define HWRM_PORT_LED_CFG_INPUT_LED2_STATE_BLINKALT UINT32_C(0x4)
17937 #define HWRM_PORT_LED_CFG_INPUT_LED2_STATE_LAST \
17938 HWRM_PORT_LED_CFG_INPUT_LED2_STATE_BLINKALT
17939 /* The requested color of LED #2. */
17940 uint8_t led2_color;
17942 #define HWRM_PORT_LED_CFG_INPUT_LED2_COLOR_DEFAULT UINT32_C(0x0)
17944 #define HWRM_PORT_LED_CFG_INPUT_LED2_COLOR_AMBER UINT32_C(0x1)
17946 #define HWRM_PORT_LED_CFG_INPUT_LED2_COLOR_GREEN UINT32_C(0x2)
17947 /* Green or Amber */
17948 #define HWRM_PORT_LED_CFG_INPUT_LED2_COLOR_GREENAMBER UINT32_C(0x3)
17949 #define HWRM_PORT_LED_CFG_INPUT_LED2_COLOR_LAST \
17950 HWRM_PORT_LED_CFG_INPUT_LED2_COLOR_GREENAMBER
17953 * If the LED #2 state is "blink" or "blinkalt", then
17954 * this field represents the requested time in milliseconds
17955 * to keep LED on between cycles.
17957 uint16_t led2_blink_on;
17959 * If the LED #2 state is "blink" or "blinkalt", then
17960 * this field represents the requested time in milliseconds
17961 * to keep LED off between cycles.
17963 uint16_t led2_blink_off;
17965 * An identifier for the group of LEDs that LED #2 belongs
17967 * If set to 0, then the LED #2 shall not be grouped and
17968 * shall be treated as an individual resource.
17969 * For all other non-zero values of this field, LED #2 shall
17970 * be grouped together with the LEDs with the same group ID
17973 uint8_t led2_group_id;
17974 /* Reserved field. */
17976 /* An identifier for the LED #3. */
17978 /* The requested state of the LED #3. */
17979 uint8_t led3_state;
17980 /* Default state of the LED */
17981 #define HWRM_PORT_LED_CFG_INPUT_LED3_STATE_DEFAULT UINT32_C(0x0)
17983 #define HWRM_PORT_LED_CFG_INPUT_LED3_STATE_OFF UINT32_C(0x1)
17985 #define HWRM_PORT_LED_CFG_INPUT_LED3_STATE_ON UINT32_C(0x2)
17987 #define HWRM_PORT_LED_CFG_INPUT_LED3_STATE_BLINK UINT32_C(0x3)
17988 /* Blink Alternately */
17989 #define HWRM_PORT_LED_CFG_INPUT_LED3_STATE_BLINKALT UINT32_C(0x4)
17990 #define HWRM_PORT_LED_CFG_INPUT_LED3_STATE_LAST \
17991 HWRM_PORT_LED_CFG_INPUT_LED3_STATE_BLINKALT
17992 /* The requested color of LED #3. */
17993 uint8_t led3_color;
17995 #define HWRM_PORT_LED_CFG_INPUT_LED3_COLOR_DEFAULT UINT32_C(0x0)
17997 #define HWRM_PORT_LED_CFG_INPUT_LED3_COLOR_AMBER UINT32_C(0x1)
17999 #define HWRM_PORT_LED_CFG_INPUT_LED3_COLOR_GREEN UINT32_C(0x2)
18000 /* Green or Amber */
18001 #define HWRM_PORT_LED_CFG_INPUT_LED3_COLOR_GREENAMBER UINT32_C(0x3)
18002 #define HWRM_PORT_LED_CFG_INPUT_LED3_COLOR_LAST \
18003 HWRM_PORT_LED_CFG_INPUT_LED3_COLOR_GREENAMBER
18006 * If the LED #3 state is "blink" or "blinkalt", then
18007 * this field represents the requested time in milliseconds
18008 * to keep LED on between cycles.
18010 uint16_t led3_blink_on;
18012 * If the LED #3 state is "blink" or "blinkalt", then
18013 * this field represents the requested time in milliseconds
18014 * to keep LED off between cycles.
18016 uint16_t led3_blink_off;
18018 * An identifier for the group of LEDs that LED #3 belongs
18020 * If set to 0, then the LED #3 shall not be grouped and
18021 * shall be treated as an individual resource.
18022 * For all other non-zero values of this field, LED #3 shall
18023 * be grouped together with the LEDs with the same group ID
18026 uint8_t led3_group_id;
18027 /* Reserved field. */
18031 /* hwrm_port_led_cfg_output (size:128b/16B) */
18032 struct hwrm_port_led_cfg_output {
18033 /* The specific error status for the command. */
18034 uint16_t error_code;
18035 /* The HWRM command request type. */
18037 /* The sequence ID from the original command. */
18039 /* The length of the response data in number of bytes. */
18041 uint8_t unused_0[7];
18043 * This field is used in Output records to indicate that the output
18044 * is completely written to RAM. This field should be read as '1'
18045 * to indicate that the output has been completely written.
18046 * When writing a command completion or response to an internal processor,
18047 * the order of writes has to be such that this field is written last.
18052 /**********************
18053 * hwrm_port_led_qcfg *
18054 **********************/
18057 /* hwrm_port_led_qcfg_input (size:192b/24B) */
18058 struct hwrm_port_led_qcfg_input {
18059 /* The HWRM command request type. */
18062 * The completion ring to send the completion event on. This should
18063 * be the NQ ID returned from the `nq_alloc` HWRM command.
18065 uint16_t cmpl_ring;
18067 * The sequence ID is used by the driver for tracking multiple
18068 * commands. This ID is treated as opaque data by the firmware and
18069 * the value is returned in the `hwrm_resp_hdr` upon completion.
18073 * The target ID of the command:
18074 * * 0x0-0xFFF8 - The function ID
18075 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
18076 * * 0xFFFD - Reserved for user-space HWRM interface
18079 uint16_t target_id;
18081 * A physical address pointer pointing to a host buffer that the
18082 * command's response data will be written. This can be either a host
18083 * physical address (HPA) or a guest physical address (GPA) and must
18084 * point to a physically contiguous block of memory.
18086 uint64_t resp_addr;
18087 /* Port ID of port whose LED configuration is being queried. */
18089 uint8_t unused_0[6];
18092 /* hwrm_port_led_qcfg_output (size:448b/56B) */
18093 struct hwrm_port_led_qcfg_output {
18094 /* The specific error status for the command. */
18095 uint16_t error_code;
18096 /* The HWRM command request type. */
18098 /* The sequence ID from the original command. */
18100 /* The length of the response data in number of bytes. */
18103 * The number of LEDs that are configured on this port.
18104 * Up to 4 LEDs can be returned in the response.
18107 /* An identifier for the LED #0. */
18109 /* The type of LED #0. */
18112 #define HWRM_PORT_LED_QCFG_OUTPUT_LED0_TYPE_SPEED UINT32_C(0x0)
18114 #define HWRM_PORT_LED_QCFG_OUTPUT_LED0_TYPE_ACTIVITY UINT32_C(0x1)
18116 #define HWRM_PORT_LED_QCFG_OUTPUT_LED0_TYPE_INVALID UINT32_C(0xff)
18117 #define HWRM_PORT_LED_QCFG_OUTPUT_LED0_TYPE_LAST \
18118 HWRM_PORT_LED_QCFG_OUTPUT_LED0_TYPE_INVALID
18119 /* The current state of the LED #0. */
18120 uint8_t led0_state;
18121 /* Default state of the LED */
18122 #define HWRM_PORT_LED_QCFG_OUTPUT_LED0_STATE_DEFAULT UINT32_C(0x0)
18124 #define HWRM_PORT_LED_QCFG_OUTPUT_LED0_STATE_OFF UINT32_C(0x1)
18126 #define HWRM_PORT_LED_QCFG_OUTPUT_LED0_STATE_ON UINT32_C(0x2)
18128 #define HWRM_PORT_LED_QCFG_OUTPUT_LED0_STATE_BLINK UINT32_C(0x3)
18129 /* Blink Alternately */
18130 #define HWRM_PORT_LED_QCFG_OUTPUT_LED0_STATE_BLINKALT UINT32_C(0x4)
18131 #define HWRM_PORT_LED_QCFG_OUTPUT_LED0_STATE_LAST \
18132 HWRM_PORT_LED_QCFG_OUTPUT_LED0_STATE_BLINKALT
18133 /* The color of LED #0. */
18134 uint8_t led0_color;
18136 #define HWRM_PORT_LED_QCFG_OUTPUT_LED0_COLOR_DEFAULT UINT32_C(0x0)
18138 #define HWRM_PORT_LED_QCFG_OUTPUT_LED0_COLOR_AMBER UINT32_C(0x1)
18140 #define HWRM_PORT_LED_QCFG_OUTPUT_LED0_COLOR_GREEN UINT32_C(0x2)
18141 /* Green or Amber */
18142 #define HWRM_PORT_LED_QCFG_OUTPUT_LED0_COLOR_GREENAMBER UINT32_C(0x3)
18143 #define HWRM_PORT_LED_QCFG_OUTPUT_LED0_COLOR_LAST \
18144 HWRM_PORT_LED_QCFG_OUTPUT_LED0_COLOR_GREENAMBER
18147 * If the LED #0 state is "blink" or "blinkalt", then
18148 * this field represents the requested time in milliseconds
18149 * to keep LED on between cycles.
18151 uint16_t led0_blink_on;
18153 * If the LED #0 state is "blink" or "blinkalt", then
18154 * this field represents the requested time in milliseconds
18155 * to keep LED off between cycles.
18157 uint16_t led0_blink_off;
18159 * An identifier for the group of LEDs that LED #0 belongs
18161 * If set to 0, then the LED #0 is not grouped.
18162 * For all other non-zero values of this field, LED #0 is
18163 * grouped together with the LEDs with the same group ID
18166 uint8_t led0_group_id;
18167 /* An identifier for the LED #1. */
18169 /* The type of LED #1. */
18172 #define HWRM_PORT_LED_QCFG_OUTPUT_LED1_TYPE_SPEED UINT32_C(0x0)
18174 #define HWRM_PORT_LED_QCFG_OUTPUT_LED1_TYPE_ACTIVITY UINT32_C(0x1)
18176 #define HWRM_PORT_LED_QCFG_OUTPUT_LED1_TYPE_INVALID UINT32_C(0xff)
18177 #define HWRM_PORT_LED_QCFG_OUTPUT_LED1_TYPE_LAST \
18178 HWRM_PORT_LED_QCFG_OUTPUT_LED1_TYPE_INVALID
18179 /* The current state of the LED #1. */
18180 uint8_t led1_state;
18181 /* Default state of the LED */
18182 #define HWRM_PORT_LED_QCFG_OUTPUT_LED1_STATE_DEFAULT UINT32_C(0x0)
18184 #define HWRM_PORT_LED_QCFG_OUTPUT_LED1_STATE_OFF UINT32_C(0x1)
18186 #define HWRM_PORT_LED_QCFG_OUTPUT_LED1_STATE_ON UINT32_C(0x2)
18188 #define HWRM_PORT_LED_QCFG_OUTPUT_LED1_STATE_BLINK UINT32_C(0x3)
18189 /* Blink Alternately */
18190 #define HWRM_PORT_LED_QCFG_OUTPUT_LED1_STATE_BLINKALT UINT32_C(0x4)
18191 #define HWRM_PORT_LED_QCFG_OUTPUT_LED1_STATE_LAST \
18192 HWRM_PORT_LED_QCFG_OUTPUT_LED1_STATE_BLINKALT
18193 /* The color of LED #1. */
18194 uint8_t led1_color;
18196 #define HWRM_PORT_LED_QCFG_OUTPUT_LED1_COLOR_DEFAULT UINT32_C(0x0)
18198 #define HWRM_PORT_LED_QCFG_OUTPUT_LED1_COLOR_AMBER UINT32_C(0x1)
18200 #define HWRM_PORT_LED_QCFG_OUTPUT_LED1_COLOR_GREEN UINT32_C(0x2)
18201 /* Green or Amber */
18202 #define HWRM_PORT_LED_QCFG_OUTPUT_LED1_COLOR_GREENAMBER UINT32_C(0x3)
18203 #define HWRM_PORT_LED_QCFG_OUTPUT_LED1_COLOR_LAST \
18204 HWRM_PORT_LED_QCFG_OUTPUT_LED1_COLOR_GREENAMBER
18207 * If the LED #1 state is "blink" or "blinkalt", then
18208 * this field represents the requested time in milliseconds
18209 * to keep LED on between cycles.
18211 uint16_t led1_blink_on;
18213 * If the LED #1 state is "blink" or "blinkalt", then
18214 * this field represents the requested time in milliseconds
18215 * to keep LED off between cycles.
18217 uint16_t led1_blink_off;
18219 * An identifier for the group of LEDs that LED #1 belongs
18221 * If set to 0, then the LED #1 is not grouped.
18222 * For all other non-zero values of this field, LED #1 is
18223 * grouped together with the LEDs with the same group ID
18226 uint8_t led1_group_id;
18227 /* An identifier for the LED #2. */
18229 /* The type of LED #2. */
18232 #define HWRM_PORT_LED_QCFG_OUTPUT_LED2_TYPE_SPEED UINT32_C(0x0)
18234 #define HWRM_PORT_LED_QCFG_OUTPUT_LED2_TYPE_ACTIVITY UINT32_C(0x1)
18236 #define HWRM_PORT_LED_QCFG_OUTPUT_LED2_TYPE_INVALID UINT32_C(0xff)
18237 #define HWRM_PORT_LED_QCFG_OUTPUT_LED2_TYPE_LAST \
18238 HWRM_PORT_LED_QCFG_OUTPUT_LED2_TYPE_INVALID
18239 /* The current state of the LED #2. */
18240 uint8_t led2_state;
18241 /* Default state of the LED */
18242 #define HWRM_PORT_LED_QCFG_OUTPUT_LED2_STATE_DEFAULT UINT32_C(0x0)
18244 #define HWRM_PORT_LED_QCFG_OUTPUT_LED2_STATE_OFF UINT32_C(0x1)
18246 #define HWRM_PORT_LED_QCFG_OUTPUT_LED2_STATE_ON UINT32_C(0x2)
18248 #define HWRM_PORT_LED_QCFG_OUTPUT_LED2_STATE_BLINK UINT32_C(0x3)
18249 /* Blink Alternately */
18250 #define HWRM_PORT_LED_QCFG_OUTPUT_LED2_STATE_BLINKALT UINT32_C(0x4)
18251 #define HWRM_PORT_LED_QCFG_OUTPUT_LED2_STATE_LAST \
18252 HWRM_PORT_LED_QCFG_OUTPUT_LED2_STATE_BLINKALT
18253 /* The color of LED #2. */
18254 uint8_t led2_color;
18256 #define HWRM_PORT_LED_QCFG_OUTPUT_LED2_COLOR_DEFAULT UINT32_C(0x0)
18258 #define HWRM_PORT_LED_QCFG_OUTPUT_LED2_COLOR_AMBER UINT32_C(0x1)
18260 #define HWRM_PORT_LED_QCFG_OUTPUT_LED2_COLOR_GREEN UINT32_C(0x2)
18261 /* Green or Amber */
18262 #define HWRM_PORT_LED_QCFG_OUTPUT_LED2_COLOR_GREENAMBER UINT32_C(0x3)
18263 #define HWRM_PORT_LED_QCFG_OUTPUT_LED2_COLOR_LAST \
18264 HWRM_PORT_LED_QCFG_OUTPUT_LED2_COLOR_GREENAMBER
18267 * If the LED #2 state is "blink" or "blinkalt", then
18268 * this field represents the requested time in milliseconds
18269 * to keep LED on between cycles.
18271 uint16_t led2_blink_on;
18273 * If the LED #2 state is "blink" or "blinkalt", then
18274 * this field represents the requested time in milliseconds
18275 * to keep LED off between cycles.
18277 uint16_t led2_blink_off;
18279 * An identifier for the group of LEDs that LED #2 belongs
18281 * If set to 0, then the LED #2 is not grouped.
18282 * For all other non-zero values of this field, LED #2 is
18283 * grouped together with the LEDs with the same group ID
18286 uint8_t led2_group_id;
18287 /* An identifier for the LED #3. */
18289 /* The type of LED #3. */
18292 #define HWRM_PORT_LED_QCFG_OUTPUT_LED3_TYPE_SPEED UINT32_C(0x0)
18294 #define HWRM_PORT_LED_QCFG_OUTPUT_LED3_TYPE_ACTIVITY UINT32_C(0x1)
18296 #define HWRM_PORT_LED_QCFG_OUTPUT_LED3_TYPE_INVALID UINT32_C(0xff)
18297 #define HWRM_PORT_LED_QCFG_OUTPUT_LED3_TYPE_LAST \
18298 HWRM_PORT_LED_QCFG_OUTPUT_LED3_TYPE_INVALID
18299 /* The current state of the LED #3. */
18300 uint8_t led3_state;
18301 /* Default state of the LED */
18302 #define HWRM_PORT_LED_QCFG_OUTPUT_LED3_STATE_DEFAULT UINT32_C(0x0)
18304 #define HWRM_PORT_LED_QCFG_OUTPUT_LED3_STATE_OFF UINT32_C(0x1)
18306 #define HWRM_PORT_LED_QCFG_OUTPUT_LED3_STATE_ON UINT32_C(0x2)
18308 #define HWRM_PORT_LED_QCFG_OUTPUT_LED3_STATE_BLINK UINT32_C(0x3)
18309 /* Blink Alternately */
18310 #define HWRM_PORT_LED_QCFG_OUTPUT_LED3_STATE_BLINKALT UINT32_C(0x4)
18311 #define HWRM_PORT_LED_QCFG_OUTPUT_LED3_STATE_LAST \
18312 HWRM_PORT_LED_QCFG_OUTPUT_LED3_STATE_BLINKALT
18313 /* The color of LED #3. */
18314 uint8_t led3_color;
18316 #define HWRM_PORT_LED_QCFG_OUTPUT_LED3_COLOR_DEFAULT UINT32_C(0x0)
18318 #define HWRM_PORT_LED_QCFG_OUTPUT_LED3_COLOR_AMBER UINT32_C(0x1)
18320 #define HWRM_PORT_LED_QCFG_OUTPUT_LED3_COLOR_GREEN UINT32_C(0x2)
18321 /* Green or Amber */
18322 #define HWRM_PORT_LED_QCFG_OUTPUT_LED3_COLOR_GREENAMBER UINT32_C(0x3)
18323 #define HWRM_PORT_LED_QCFG_OUTPUT_LED3_COLOR_LAST \
18324 HWRM_PORT_LED_QCFG_OUTPUT_LED3_COLOR_GREENAMBER
18327 * If the LED #3 state is "blink" or "blinkalt", then
18328 * this field represents the requested time in milliseconds
18329 * to keep LED on between cycles.
18331 uint16_t led3_blink_on;
18333 * If the LED #3 state is "blink" or "blinkalt", then
18334 * this field represents the requested time in milliseconds
18335 * to keep LED off between cycles.
18337 uint16_t led3_blink_off;
18339 * An identifier for the group of LEDs that LED #3 belongs
18341 * If set to 0, then the LED #3 is not grouped.
18342 * For all other non-zero values of this field, LED #3 is
18343 * grouped together with the LEDs with the same group ID
18346 uint8_t led3_group_id;
18347 uint8_t unused_4[6];
18349 * This field is used in Output records to indicate that the output
18350 * is completely written to RAM. This field should be read as '1'
18351 * to indicate that the output has been completely written.
18352 * When writing a command completion or response to an internal processor,
18353 * the order of writes has to be such that this field is written last.
18358 /***********************
18359 * hwrm_port_led_qcaps *
18360 ***********************/
18363 /* hwrm_port_led_qcaps_input (size:192b/24B) */
18364 struct hwrm_port_led_qcaps_input {
18365 /* The HWRM command request type. */
18368 * The completion ring to send the completion event on. This should
18369 * be the NQ ID returned from the `nq_alloc` HWRM command.
18371 uint16_t cmpl_ring;
18373 * The sequence ID is used by the driver for tracking multiple
18374 * commands. This ID is treated as opaque data by the firmware and
18375 * the value is returned in the `hwrm_resp_hdr` upon completion.
18379 * The target ID of the command:
18380 * * 0x0-0xFFF8 - The function ID
18381 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
18382 * * 0xFFFD - Reserved for user-space HWRM interface
18385 uint16_t target_id;
18387 * A physical address pointer pointing to a host buffer that the
18388 * command's response data will be written. This can be either a host
18389 * physical address (HPA) or a guest physical address (GPA) and must
18390 * point to a physically contiguous block of memory.
18392 uint64_t resp_addr;
18393 /* Port ID of port whose LED configuration is being queried. */
18395 uint8_t unused_0[6];
18398 /* hwrm_port_led_qcaps_output (size:384b/48B) */
18399 struct hwrm_port_led_qcaps_output {
18400 /* The specific error status for the command. */
18401 uint16_t error_code;
18402 /* The HWRM command request type. */
18404 /* The sequence ID from the original command. */
18406 /* The length of the response data in number of bytes. */
18409 * The number of LEDs that are configured on this port.
18410 * Up to 4 LEDs can be returned in the response.
18413 /* Reserved for future use. */
18415 /* An identifier for the LED #0. */
18417 /* The type of LED #0. */
18420 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED0_TYPE_SPEED UINT32_C(0x0)
18422 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED0_TYPE_ACTIVITY UINT32_C(0x1)
18424 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED0_TYPE_INVALID UINT32_C(0xff)
18425 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED0_TYPE_LAST \
18426 HWRM_PORT_LED_QCAPS_OUTPUT_LED0_TYPE_INVALID
18428 * An identifier for the group of LEDs that LED #0 belongs
18430 * If set to 0, then the LED #0 cannot be grouped.
18431 * For all other non-zero values of this field, LED #0 is
18432 * grouped together with the LEDs with the same group ID
18435 uint8_t led0_group_id;
18437 /* The states supported by LED #0. */
18438 uint16_t led0_state_caps;
18440 * If set to 1, this LED is enabled.
18441 * If set to 0, this LED is disabled.
18443 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED0_STATE_CAPS_ENABLED \
18446 * If set to 1, off state is supported on this LED.
18447 * If set to 0, off state is not supported on this LED.
18449 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED0_STATE_CAPS_OFF_SUPPORTED \
18452 * If set to 1, on state is supported on this LED.
18453 * If set to 0, on state is not supported on this LED.
18455 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED0_STATE_CAPS_ON_SUPPORTED \
18458 * If set to 1, blink state is supported on this LED.
18459 * If set to 0, blink state is not supported on this LED.
18461 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED0_STATE_CAPS_BLINK_SUPPORTED \
18464 * If set to 1, blink_alt state is supported on this LED.
18465 * If set to 0, blink_alt state is not supported on this LED.
18467 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED0_STATE_CAPS_BLINK_ALT_SUPPORTED \
18469 /* The colors supported by LED #0. */
18470 uint16_t led0_color_caps;
18472 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED0_COLOR_CAPS_RSVD \
18475 * If set to 1, Amber color is supported on this LED.
18476 * If set to 0, Amber color is not supported on this LED.
18478 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED0_COLOR_CAPS_AMBER_SUPPORTED \
18481 * If set to 1, Green color is supported on this LED.
18482 * If set to 0, Green color is not supported on this LED.
18484 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED0_COLOR_CAPS_GREEN_SUPPORTED \
18486 /* An identifier for the LED #1. */
18488 /* The type of LED #1. */
18491 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED1_TYPE_SPEED UINT32_C(0x0)
18493 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED1_TYPE_ACTIVITY UINT32_C(0x1)
18495 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED1_TYPE_INVALID UINT32_C(0xff)
18496 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED1_TYPE_LAST \
18497 HWRM_PORT_LED_QCAPS_OUTPUT_LED1_TYPE_INVALID
18499 * An identifier for the group of LEDs that LED #1 belongs
18501 * If set to 0, then the LED #0 cannot be grouped.
18502 * For all other non-zero values of this field, LED #0 is
18503 * grouped together with the LEDs with the same group ID
18506 uint8_t led1_group_id;
18508 /* The states supported by LED #1. */
18509 uint16_t led1_state_caps;
18511 * If set to 1, this LED is enabled.
18512 * If set to 0, this LED is disabled.
18514 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED1_STATE_CAPS_ENABLED \
18517 * If set to 1, off state is supported on this LED.
18518 * If set to 0, off state is not supported on this LED.
18520 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED1_STATE_CAPS_OFF_SUPPORTED \
18523 * If set to 1, on state is supported on this LED.
18524 * If set to 0, on state is not supported on this LED.
18526 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED1_STATE_CAPS_ON_SUPPORTED \
18529 * If set to 1, blink state is supported on this LED.
18530 * If set to 0, blink state is not supported on this LED.
18532 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED1_STATE_CAPS_BLINK_SUPPORTED \
18535 * If set to 1, blink_alt state is supported on this LED.
18536 * If set to 0, blink_alt state is not supported on this LED.
18538 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED1_STATE_CAPS_BLINK_ALT_SUPPORTED \
18540 /* The colors supported by LED #1. */
18541 uint16_t led1_color_caps;
18543 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED1_COLOR_CAPS_RSVD \
18546 * If set to 1, Amber color is supported on this LED.
18547 * If set to 0, Amber color is not supported on this LED.
18549 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED1_COLOR_CAPS_AMBER_SUPPORTED \
18552 * If set to 1, Green color is supported on this LED.
18553 * If set to 0, Green color is not supported on this LED.
18555 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED1_COLOR_CAPS_GREEN_SUPPORTED \
18557 /* An identifier for the LED #2. */
18559 /* The type of LED #2. */
18562 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED2_TYPE_SPEED UINT32_C(0x0)
18564 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED2_TYPE_ACTIVITY UINT32_C(0x1)
18566 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED2_TYPE_INVALID UINT32_C(0xff)
18567 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED2_TYPE_LAST \
18568 HWRM_PORT_LED_QCAPS_OUTPUT_LED2_TYPE_INVALID
18570 * An identifier for the group of LEDs that LED #0 belongs
18572 * If set to 0, then the LED #0 cannot be grouped.
18573 * For all other non-zero values of this field, LED #0 is
18574 * grouped together with the LEDs with the same group ID
18577 uint8_t led2_group_id;
18579 /* The states supported by LED #2. */
18580 uint16_t led2_state_caps;
18582 * If set to 1, this LED is enabled.
18583 * If set to 0, this LED is disabled.
18585 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED2_STATE_CAPS_ENABLED \
18588 * If set to 1, off state is supported on this LED.
18589 * If set to 0, off state is not supported on this LED.
18591 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED2_STATE_CAPS_OFF_SUPPORTED \
18594 * If set to 1, on state is supported on this LED.
18595 * If set to 0, on state is not supported on this LED.
18597 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED2_STATE_CAPS_ON_SUPPORTED \
18600 * If set to 1, blink state is supported on this LED.
18601 * If set to 0, blink state is not supported on this LED.
18603 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED2_STATE_CAPS_BLINK_SUPPORTED \
18606 * If set to 1, blink_alt state is supported on this LED.
18607 * If set to 0, blink_alt state is not supported on this LED.
18609 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED2_STATE_CAPS_BLINK_ALT_SUPPORTED \
18611 /* The colors supported by LED #2. */
18612 uint16_t led2_color_caps;
18614 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED2_COLOR_CAPS_RSVD \
18617 * If set to 1, Amber color is supported on this LED.
18618 * If set to 0, Amber color is not supported on this LED.
18620 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED2_COLOR_CAPS_AMBER_SUPPORTED \
18623 * If set to 1, Green color is supported on this LED.
18624 * If set to 0, Green color is not supported on this LED.
18626 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED2_COLOR_CAPS_GREEN_SUPPORTED \
18628 /* An identifier for the LED #3. */
18630 /* The type of LED #3. */
18633 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED3_TYPE_SPEED UINT32_C(0x0)
18635 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED3_TYPE_ACTIVITY UINT32_C(0x1)
18637 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED3_TYPE_INVALID UINT32_C(0xff)
18638 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED3_TYPE_LAST \
18639 HWRM_PORT_LED_QCAPS_OUTPUT_LED3_TYPE_INVALID
18641 * An identifier for the group of LEDs that LED #3 belongs
18643 * If set to 0, then the LED #0 cannot be grouped.
18644 * For all other non-zero values of this field, LED #0 is
18645 * grouped together with the LEDs with the same group ID
18648 uint8_t led3_group_id;
18650 /* The states supported by LED #3. */
18651 uint16_t led3_state_caps;
18653 * If set to 1, this LED is enabled.
18654 * If set to 0, this LED is disabled.
18656 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED3_STATE_CAPS_ENABLED \
18659 * If set to 1, off state is supported on this LED.
18660 * If set to 0, off state is not supported on this LED.
18662 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED3_STATE_CAPS_OFF_SUPPORTED \
18665 * If set to 1, on state is supported on this LED.
18666 * If set to 0, on state is not supported on this LED.
18668 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED3_STATE_CAPS_ON_SUPPORTED \
18671 * If set to 1, blink state is supported on this LED.
18672 * If set to 0, blink state is not supported on this LED.
18674 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED3_STATE_CAPS_BLINK_SUPPORTED \
18677 * If set to 1, blink_alt state is supported on this LED.
18678 * If set to 0, blink_alt state is not supported on this LED.
18680 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED3_STATE_CAPS_BLINK_ALT_SUPPORTED \
18682 /* The colors supported by LED #3. */
18683 uint16_t led3_color_caps;
18685 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED3_COLOR_CAPS_RSVD \
18688 * If set to 1, Amber color is supported on this LED.
18689 * If set to 0, Amber color is not supported on this LED.
18691 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED3_COLOR_CAPS_AMBER_SUPPORTED \
18694 * If set to 1, Green color is supported on this LED.
18695 * If set to 0, Green color is not supported on this LED.
18697 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED3_COLOR_CAPS_GREEN_SUPPORTED \
18699 uint8_t unused_4[3];
18701 * This field is used in Output records to indicate that the output
18702 * is completely written to RAM. This field should be read as '1'
18703 * to indicate that the output has been completely written.
18704 * When writing a command completion or response to an internal processor,
18705 * the order of writes has to be such that this field is written last.
18710 /***********************
18711 * hwrm_port_prbs_test *
18712 ***********************/
18715 /* hwrm_port_prbs_test_input (size:384b/48B) */
18716 struct hwrm_port_prbs_test_input {
18717 /* The HWRM command request type. */
18720 * The completion ring to send the completion event on. This should
18721 * be the NQ ID returned from the `nq_alloc` HWRM command.
18723 uint16_t cmpl_ring;
18725 * The sequence ID is used by the driver for tracking multiple
18726 * commands. This ID is treated as opaque data by the firmware and
18727 * the value is returned in the `hwrm_resp_hdr` upon completion.
18731 * The target ID of the command:
18732 * * 0x0-0xFFF8 - The function ID
18733 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
18734 * * 0xFFFD - Reserved for user-space HWRM interface
18737 uint16_t target_id;
18739 * A physical address pointer pointing to a host buffer that the
18740 * command's response data will be written. This can be either a host
18741 * physical address (HPA) or a guest physical address (GPA) and must
18742 * point to a physically contiguous block of memory.
18744 uint64_t resp_addr;
18745 /* Host address data is to DMA'd to. */
18746 uint64_t resp_data_addr;
18748 * Size of the buffer pointed to by resp_data_addr. The firmware may
18749 * use this entire buffer or less than the entire buffer, but never more.
18754 /* Port ID of port where PRBS test to be run. */
18756 /* Polynomial selection for PRBS test. */
18759 #define HWRM_PORT_PRBS_TEST_INPUT_POLY_PRBS7 UINT32_C(0x0)
18761 #define HWRM_PORT_PRBS_TEST_INPUT_POLY_PRBS9 UINT32_C(0x1)
18763 #define HWRM_PORT_PRBS_TEST_INPUT_POLY_PRBS11 UINT32_C(0x2)
18765 #define HWRM_PORT_PRBS_TEST_INPUT_POLY_PRBS15 UINT32_C(0x3)
18767 #define HWRM_PORT_PRBS_TEST_INPUT_POLY_PRBS23 UINT32_C(0x4)
18769 #define HWRM_PORT_PRBS_TEST_INPUT_POLY_PRBS31 UINT32_C(0x5)
18771 #define HWRM_PORT_PRBS_TEST_INPUT_POLY_PRBS58 UINT32_C(0x6)
18773 #define HWRM_PORT_PRBS_TEST_INPUT_POLY_INVALID UINT32_C(0xff)
18774 #define HWRM_PORT_PRBS_TEST_INPUT_POLY_LAST \
18775 HWRM_PORT_PRBS_TEST_INPUT_POLY_INVALID
18777 * Configuration bits for PRBS test.
18778 * Use enable bit to start/stop test.
18779 * Use tx/rx lane map bits to run test on specific lanes,
18780 * if set to 0 test will be run on all lanes.
18782 uint16_t prbs_config;
18784 * Set 0 to stop test currently in progress
18785 * Set 1 to start test with configuration provided.
18787 #define HWRM_PORT_PRBS_TEST_INPUT_PRBS_CONFIG_START_STOP \
18790 * If set to 1, tx_lane_map bitmap should have lane bits set.
18791 * If set to 0, test will be run on all lanes for this port.
18793 #define HWRM_PORT_PRBS_TEST_INPUT_PRBS_CONFIG_TX_LANE_MAP_VALID \
18796 * If set to 1, rx_lane_map bitmap should have lane bits set.
18797 * If set to 0, test will be run on all lanes for this port.
18799 #define HWRM_PORT_PRBS_TEST_INPUT_PRBS_CONFIG_RX_LANE_MAP_VALID \
18801 /* Duration in seconds to run the PRBS test. */
18804 * If tx_lane_map_valid is set to 1, this field is a bitmap
18805 * of tx lanes to run PRBS test. bit0 = lane0,
18806 * bit1 = lane1 ..bit31 = lane31
18808 uint32_t tx_lane_map;
18810 * If rx_lane_map_valid is set to 1, this field is a bitmap
18811 * of rx lanes to run PRBS test. bit0 = lane0,
18812 * bit1 = lane1 ..bit31 = lane31
18814 uint32_t rx_lane_map;
18817 /* hwrm_port_prbs_test_output (size:128b/16B) */
18818 struct hwrm_port_prbs_test_output {
18819 /* The specific error status for the command. */
18820 uint16_t error_code;
18821 /* The HWRM command request type. */
18823 /* The sequence ID from the original command. */
18825 /* The length of the response data in number of bytes. */
18827 /* Total length of stored data. */
18828 uint16_t total_data_len;
18830 uint8_t unused_1[3];
18832 * This field is used in Output records to indicate that the output
18833 * is completely written to RAM. This field should be read as '1'
18834 * to indicate that the output has been completely written.
18835 * When writing a command completion or response to an internal processor,
18836 * the order of writes has to be such that this field is written last.
18841 /**********************
18842 * hwrm_port_dsc_dump *
18843 **********************/
18846 /* hwrm_port_dsc_dump_input (size:320b/40B) */
18847 struct hwrm_port_dsc_dump_input {
18848 /* The HWRM command request type. */
18851 * The completion ring to send the completion event on. This should
18852 * be the NQ ID returned from the `nq_alloc` HWRM command.
18854 uint16_t cmpl_ring;
18856 * The sequence ID is used by the driver for tracking multiple
18857 * commands. This ID is treated as opaque data by the firmware and
18858 * the value is returned in the `hwrm_resp_hdr` upon completion.
18862 * The target ID of the command:
18863 * * 0x0-0xFFF8 - The function ID
18864 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
18865 * * 0xFFFD - Reserved for user-space HWRM interface
18868 uint16_t target_id;
18870 * A physical address pointer pointing to a host buffer that the
18871 * command's response data will be written. This can be either a host
18872 * physical address (HPA) or a guest physical address (GPA) and must
18873 * point to a physically contiguous block of memory.
18875 uint64_t resp_addr;
18876 /* Host address where response diagnostic data is returned. */
18877 uint64_t resp_data_addr;
18879 * Size of the buffer pointed to by resp_data_addr. The firmware
18880 * may use this entire buffer or less than the entire buffer, but
18886 /* Port ID of port where dsc dump to be collected. */
18888 /* Diag level specified by the user */
18889 uint16_t diag_level;
18890 /* SRDS_DIAG_LANE */
18891 #define HWRM_PORT_DSC_DUMP_INPUT_DIAG_LEVEL_SRDS_DIAG_LANE \
18893 /* SRDS_DIAG_CORE */
18894 #define HWRM_PORT_DSC_DUMP_INPUT_DIAG_LEVEL_SRDS_DIAG_CORE \
18896 /* SRDS_DIAG_EVENT */
18897 #define HWRM_PORT_DSC_DUMP_INPUT_DIAG_LEVEL_SRDS_DIAG_EVENT \
18899 /* SRDS_DIAG_EYE */
18900 #define HWRM_PORT_DSC_DUMP_INPUT_DIAG_LEVEL_SRDS_DIAG_EYE \
18902 /* SRDS_DIAG_REG_CORE */
18903 #define HWRM_PORT_DSC_DUMP_INPUT_DIAG_LEVEL_SRDS_DIAG_REG_CORE \
18905 /* SRDS_DIAG_REG_LANE */
18906 #define HWRM_PORT_DSC_DUMP_INPUT_DIAG_LEVEL_SRDS_DIAG_REG_LANE \
18908 /* SRDS_DIAG_UC_CORE */
18909 #define HWRM_PORT_DSC_DUMP_INPUT_DIAG_LEVEL_SRDS_DIAG_UC_CORE \
18911 /* SRDS_DIAG_UC_LANE */
18912 #define HWRM_PORT_DSC_DUMP_INPUT_DIAG_LEVEL_SRDS_DIAG_UC_LANE \
18914 /* SRDS_DIAG_LANE_DEBUG */
18915 #define HWRM_PORT_DSC_DUMP_INPUT_DIAG_LEVEL_SRDS_DIAG_LANE_DEBUG \
18917 /* SRDS_DIAG_BER_VERT */
18918 #define HWRM_PORT_DSC_DUMP_INPUT_DIAG_LEVEL_SRDS_DIAG_BER_VERT \
18920 /* SRDS_DIAG_BER_HORZ */
18921 #define HWRM_PORT_DSC_DUMP_INPUT_DIAG_LEVEL_SRDS_DIAG_BER_HORZ \
18923 /* SRDS_DIAG_EVENT_SAFE */
18924 #define HWRM_PORT_DSC_DUMP_INPUT_DIAG_LEVEL_SRDS_DIAG_EVENT_SAFE \
18926 /* SRDS_DIAG_TIMESTAMP */
18927 #define HWRM_PORT_DSC_DUMP_INPUT_DIAG_LEVEL_SRDS_DIAG_TIMESTAMP \
18929 #define HWRM_PORT_DSC_DUMP_INPUT_DIAG_LEVEL_LAST \
18930 HWRM_PORT_DSC_DUMP_INPUT_DIAG_LEVEL_SRDS_DIAG_TIMESTAMP
18932 * This field is a lane number
18933 * on which to collect the dsc dump
18935 uint16_t lane_number;
18937 * Configuration bits.
18938 * Use enable bit to start dsc dump or retrieve dump
18940 uint16_t dsc_dump_config;
18942 * Set 0 to retrieve the dsc dump
18943 * Set 1 to start the dsc dump
18945 #define HWRM_PORT_DSC_DUMP_INPUT_DSC_DUMP_CONFIG_START_RETRIEVE \
18949 /* hwrm_port_dsc_dump_output (size:128b/16B) */
18950 struct hwrm_port_dsc_dump_output {
18951 /* The specific error status for the command. */
18952 uint16_t error_code;
18953 /* The HWRM command request type. */
18955 /* The sequence ID from the original command. */
18957 /* The length of the response data in number of bytes. */
18959 /* Total length of stored data. */
18960 uint16_t total_data_len;
18962 uint8_t unused_1[3];
18964 * This field is used in Output records to indicate that the output
18965 * is completely written to RAM. This field should be read as '1'
18966 * to indicate that the output has been completely written.
18967 * When writing a command completion or response to an internal processor,
18968 * the order of writes has to be such that this field is written last.
18973 /******************************
18974 * hwrm_port_sfp_sideband_cfg *
18975 ******************************/
18978 /* hwrm_port_sfp_sideband_cfg_input (size:256b/32B) */
18979 struct hwrm_port_sfp_sideband_cfg_input {
18980 /* The HWRM command request type. */
18983 * The completion ring to send the completion event on. This should
18984 * be the NQ ID returned from the `nq_alloc` HWRM command.
18986 uint16_t cmpl_ring;
18988 * The sequence ID is used by the driver for tracking multiple
18989 * commands. This ID is treated as opaque data by the firmware and
18990 * the value is returned in the `hwrm_resp_hdr` upon completion.
18994 * The target ID of the command:
18995 * * 0x0-0xFFF8 - The function ID
18996 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
18997 * * 0xFFFD - Reserved for user-space HWRM interface
19000 uint16_t target_id;
19002 * A physical address pointer pointing to a host buffer that the
19003 * command's response data will be written. This can be either a host
19004 * physical address (HPA) or a guest physical address (GPA) and must
19005 * point to a physically contiguous block of memory.
19007 uint64_t resp_addr;
19008 /* Port ID of port that is to be queried. */
19010 uint8_t unused_0[6];
19012 * This bitfield is used to specify which bits from the 'flags'
19013 * fields are being configured by the caller.
19016 /* This bit must be '1' for rs0 to be configured. */
19017 #define HWRM_PORT_SFP_SIDEBAND_CFG_INPUT_ENABLES_RS0 \
19019 /* This bit must be '1' for rs1 to be configured. */
19020 #define HWRM_PORT_SFP_SIDEBAND_CFG_INPUT_ENABLES_RS1 \
19022 /* This bit must be '1' for tx_disable to be configured. */
19023 #define HWRM_PORT_SFP_SIDEBAND_CFG_INPUT_ENABLES_TX_DIS \
19026 * This bit must be '1' for mod_sel to be configured.
19027 * Valid only on QSFP modules
19029 #define HWRM_PORT_SFP_SIDEBAND_CFG_INPUT_ENABLES_MOD_SEL \
19031 /* This bit must be '1' for reset_l to be configured. */
19032 #define HWRM_PORT_SFP_SIDEBAND_CFG_INPUT_ENABLES_RESET_L \
19034 /* This bit must be '1' for lp_mode to be configured. */
19035 #define HWRM_PORT_SFP_SIDEBAND_CFG_INPUT_ENABLES_LP_MODE \
19037 /* This bit must be '1' for pwr_disable to be configured. */
19038 #define HWRM_PORT_SFP_SIDEBAND_CFG_INPUT_ENABLES_PWR_DIS \
19041 * Only bits that have corresponding bits in the 'enables'
19042 * bitfield are processed by the firmware, all other bits
19043 * of 'flags' are ignored.
19047 * This bit along with rs1 configures the current speed of the dual
19048 * rate module. If these pins are GNDed then the speed can be changed
19049 * by driectly writing to EEPROM.
19051 #define HWRM_PORT_SFP_SIDEBAND_CFG_INPUT_FLAGS_RS0 \
19054 * This bit along with rs0 configures the current speed of the dual
19055 * rate module. If these pins are GNDed then the speed can be changed
19056 * by driectly writing to EEPROM.
19058 #define HWRM_PORT_SFP_SIDEBAND_CFG_INPUT_FLAGS_RS1 \
19061 * When this bit is set to '1', tx_disable is set.
19062 * On a 1G BASE-T module, if this bit is set,
19063 * module PHY registers will not be accessible.
19065 #define HWRM_PORT_SFP_SIDEBAND_CFG_INPUT_FLAGS_TX_DIS \
19068 * When this bit is set to '1', this module is selected.
19069 * Valid only on QSFP modules
19071 #define HWRM_PORT_SFP_SIDEBAND_CFG_INPUT_FLAGS_MOD_SEL \
19074 * If reset_l is set to 0, Module will be taken out of reset
19075 * and other signals will be set to their requested state once
19076 * the module is out of reset.
19077 * Valid only on QSFP modules
19079 #define HWRM_PORT_SFP_SIDEBAND_CFG_INPUT_FLAGS_RESET_L \
19082 * When this bit is set to '1', the module will be configured
19083 * in low power mode.
19084 * Valid only on QSFP modules
19086 #define HWRM_PORT_SFP_SIDEBAND_CFG_INPUT_FLAGS_LP_MODE \
19088 /* When this bit is set to '1', the module will be powered down. */
19089 #define HWRM_PORT_SFP_SIDEBAND_CFG_INPUT_FLAGS_PWR_DIS \
19093 /* hwrm_port_sfp_sideband_cfg_output (size:128b/16B) */
19094 struct hwrm_port_sfp_sideband_cfg_output {
19095 /* The specific error status for the command. */
19096 uint16_t error_code;
19097 /* The HWRM command request type. */
19099 /* The sequence ID from the original command. */
19101 /* The length of the response data in number of bytes. */
19105 * This field is used in Output records to indicate that the output
19106 * is completely written to RAM. This field should be read as '1'
19107 * to indicate that the output has been completely written. When
19108 * writing a command completion or response to an internal processor,
19109 * the order of writes has to be such that this field is written last.
19114 /*******************************
19115 * hwrm_port_sfp_sideband_qcfg *
19116 *******************************/
19119 /* hwrm_port_sfp_sideband_qcfg_input (size:192b/24B) */
19120 struct hwrm_port_sfp_sideband_qcfg_input {
19121 /* The HWRM command request type. */
19124 * The completion ring to send the completion event on. This should
19125 * be the NQ ID returned from the `nq_alloc` HWRM command.
19127 uint16_t cmpl_ring;
19129 * The sequence ID is used by the driver for tracking multiple
19130 * commands. This ID is treated as opaque data by the firmware and
19131 * the value is returned in the `hwrm_resp_hdr` upon completion.
19135 * The target ID of the command:
19136 * * 0x0-0xFFF8 - The function ID
19137 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
19138 * * 0xFFFD - Reserved for user-space HWRM interface
19141 uint16_t target_id;
19143 * A physical address pointer pointing to a host buffer that the
19144 * command's response data will be written. This can be either a host
19145 * physical address (HPA) or a guest physical address (GPA) and must
19146 * point to a physically contiguous block of memory.
19148 uint64_t resp_addr;
19149 /* Port ID of port that is to be queried. */
19151 uint8_t unused_0[6];
19154 /* hwrm_port_sfp_sideband_qcfg_output (size:192b/24B) */
19155 struct hwrm_port_sfp_sideband_qcfg_output {
19156 /* The specific error status for the command. */
19157 uint16_t error_code;
19158 /* The HWRM command request type. */
19160 /* The sequence ID from the original command. */
19162 /* The length of the response data in number of bytes. */
19165 * Bitmask indicating which sideband signals are valid.
19166 * This is based on the board and nvm cfg that is present on the board.
19168 uint32_t supported_mask;
19169 uint32_t sideband_signals;
19170 /* When this bit is set to '1', the Module is absent. */
19171 #define HWRM_PORT_SFP_SIDEBAND_QCFG_OUTPUT_SIDEBAND_SIGNALS_MOD_ABS \
19174 * When this bit is set to '1', there is no valid signal on RX.
19175 * This signal is a filtered version of Signal Detect.
19177 #define HWRM_PORT_SFP_SIDEBAND_QCFG_OUTPUT_SIDEBAND_SIGNALS_RX_LOS \
19180 * This bit along with rs1 indiactes the current speed of the dual
19181 * rate module.If these pins are grounded then the speed can be
19182 * changed by driectky writing to EEPROM.
19184 #define HWRM_PORT_SFP_SIDEBAND_QCFG_OUTPUT_SIDEBAND_SIGNALS_RS0 \
19187 * This bit along with rs0 indiactes the current speed of the dual
19188 * rate module.If these pins are grounded then the speed can be
19189 * changed by driectky writing to EEPROM.
19191 #define HWRM_PORT_SFP_SIDEBAND_QCFG_OUTPUT_SIDEBAND_SIGNALS_RS1 \
19194 * When this bit is set to '1', tx_disable is set.
19195 * On a 1G BASE-T module, if this bit is set, module PHY
19196 * registers will not be accessible.
19198 #define HWRM_PORT_SFP_SIDEBAND_QCFG_OUTPUT_SIDEBAND_SIGNALS_TX_DIS \
19200 /* When this bit is set to '1', tx_fault is set. */
19201 #define HWRM_PORT_SFP_SIDEBAND_QCFG_OUTPUT_SIDEBAND_SIGNALS_TX_FAULT \
19204 * When this bit is set to '1', module is selected.
19205 * Valid only on QSFP modules
19207 #define HWRM_PORT_SFP_SIDEBAND_QCFG_OUTPUT_SIDEBAND_SIGNALS_MOD_SEL \
19210 * When this bit is set to '0', the module is held in reset.
19211 * if reset_l is set to 1,first module is taken out of reset
19212 * and other signals will be set to their requested state.
19213 * Valid only on QSFP modules.
19215 #define HWRM_PORT_SFP_SIDEBAND_QCFG_OUTPUT_SIDEBAND_SIGNALS_RESET_L \
19218 * When this bit is set to '1', the module is in low power mode.
19219 * Valid only on QSFP modules
19221 #define HWRM_PORT_SFP_SIDEBAND_QCFG_OUTPUT_SIDEBAND_SIGNALS_LP_MODE \
19223 /* When this bit is set to '1', module is in power down state. */
19224 #define HWRM_PORT_SFP_SIDEBAND_QCFG_OUTPUT_SIDEBAND_SIGNALS_PWR_DIS \
19228 * This field is used in Output records to indicate that the output
19229 * is completely written to RAM. This field should be read as '1'
19230 * to indicate that the output has been completely written. When
19231 * writing a command completion or response to an internal processor,
19232 * the order of writes has to be such that this field is written last.
19237 /**********************************
19238 * hwrm_port_phy_mdio_bus_acquire *
19239 **********************************/
19242 /* hwrm_port_phy_mdio_bus_acquire_input (size:192b/24B) */
19243 struct hwrm_port_phy_mdio_bus_acquire_input {
19244 /* The HWRM command request type. */
19247 * The completion ring to send the completion event on. This should
19248 * be the NQ ID returned from the `nq_alloc` HWRM command.
19250 uint16_t cmpl_ring;
19252 * The sequence ID is used by the driver for tracking multiple
19253 * commands. This ID is treated as opaque data by the firmware and
19254 * the value is returned in the `hwrm_resp_hdr` upon completion.
19258 * The target ID of the command:
19259 * * 0x0-0xFFF8 - The function ID
19260 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
19261 * * 0xFFFD - Reserved for user-space HWRM interface
19264 uint16_t target_id;
19266 * A physical address pointer pointing to a host buffer that the
19267 * command's response data will be written. This can be either a host
19268 * physical address (HPA) or a guest physical address (GPA) and must
19269 * point to a physically contiguous block of memory.
19271 uint64_t resp_addr;
19272 /* Port ID of the port. */
19275 * client_id of the client requesting BUS access.
19276 * Any value from 0x10 to 0xFFFF can be used.
19277 * Client should make sure that the returned client_id
19278 * in response matches the client_id in request.
19279 * 0-0xF are reserved for internal use.
19281 uint16_t client_id;
19283 * Timeout in milli seconds, MDIO BUS will be released automatically
19284 * after this time, if another mdio acquire command is not received
19285 * within the timeout window from the same client.
19286 * A 0xFFFF will hold the bus until this bus is released.
19288 uint16_t mdio_bus_timeout;
19289 uint8_t unused_0[2];
19292 /* hwrm_port_phy_mdio_bus_acquire_output (size:128b/16B) */
19293 struct hwrm_port_phy_mdio_bus_acquire_output {
19294 /* The specific error status for the command. */
19295 uint16_t error_code;
19296 /* The HWRM command request type. */
19298 /* The sequence ID from the original command. */
19300 /* The length of the response data in number of bytes. */
19304 * client_id of the module holding the BUS.
19305 * 0-0xF are reserved for internal use.
19307 uint16_t client_id;
19308 uint8_t unused_1[3];
19310 * This field is used in Output records to indicate that the output
19311 * is completely written to RAM. This field should be read as '1'
19312 * to indicate that the output has been completely written.
19313 * When writing a command completion or response to an internal processor,
19314 * the order of writes has to be such that this field is written last.
19319 /**********************************
19320 * hwrm_port_phy_mdio_bus_release *
19321 **********************************/
19324 /* hwrm_port_phy_mdio_bus_release_input (size:192b/24B) */
19325 struct hwrm_port_phy_mdio_bus_release_input {
19326 /* The HWRM command request type. */
19329 * The completion ring to send the completion event on. This should
19330 * be the NQ ID returned from the `nq_alloc` HWRM command.
19332 uint16_t cmpl_ring;
19334 * The sequence ID is used by the driver for tracking multiple
19335 * commands. This ID is treated as opaque data by the firmware and
19336 * the value is returned in the `hwrm_resp_hdr` upon completion.
19340 * The target ID of the command:
19341 * * 0x0-0xFFF8 - The function ID
19342 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
19343 * * 0xFFFD - Reserved for user-space HWRM interface
19346 uint16_t target_id;
19348 * A physical address pointer pointing to a host buffer that the
19349 * command's response data will be written. This can be either a host
19350 * physical address (HPA) or a guest physical address (GPA) and must
19351 * point to a physically contiguous block of memory.
19353 uint64_t resp_addr;
19354 /* Port ID of the port. */
19357 * client_id of the client requesting BUS release.
19358 * A client should not release any other clients BUS.
19360 uint16_t client_id;
19361 uint8_t unused_0[4];
19364 /* hwrm_port_phy_mdio_bus_release_output (size:128b/16B) */
19365 struct hwrm_port_phy_mdio_bus_release_output {
19366 /* The specific error status for the command. */
19367 uint16_t error_code;
19368 /* The HWRM command request type. */
19370 /* The sequence ID from the original command. */
19372 /* The length of the response data in number of bytes. */
19375 /* The BUS is released if client_id matches the client_id in request. */
19376 uint16_t clients_id;
19377 uint8_t unused_1[3];
19379 * This field is used in Output records to indicate that the output
19380 * is completely written to RAM. This field should be read as '1'
19381 * to indicate that the output has been completely written.
19382 * When writing a command completion or response to an internal processor,
19383 * the order of writes has to be such that this field is written last.
19388 /***********************
19389 * hwrm_queue_qportcfg *
19390 ***********************/
19393 /* hwrm_queue_qportcfg_input (size:192b/24B) */
19394 struct hwrm_queue_qportcfg_input {
19395 /* The HWRM command request type. */
19398 * The completion ring to send the completion event on. This should
19399 * be the NQ ID returned from the `nq_alloc` HWRM command.
19401 uint16_t cmpl_ring;
19403 * The sequence ID is used by the driver for tracking multiple
19404 * commands. This ID is treated as opaque data by the firmware and
19405 * the value is returned in the `hwrm_resp_hdr` upon completion.
19409 * The target ID of the command:
19410 * * 0x0-0xFFF8 - The function ID
19411 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
19412 * * 0xFFFD - Reserved for user-space HWRM interface
19415 uint16_t target_id;
19417 * A physical address pointer pointing to a host buffer that the
19418 * command's response data will be written. This can be either a host
19419 * physical address (HPA) or a guest physical address (GPA) and must
19420 * point to a physically contiguous block of memory.
19422 uint64_t resp_addr;
19425 * Enumeration denoting the RX, TX type of the resource.
19426 * This enumeration is used for resources that are similar for both
19427 * TX and RX paths of the chip.
19429 #define HWRM_QUEUE_QPORTCFG_INPUT_FLAGS_PATH UINT32_C(0x1)
19431 #define HWRM_QUEUE_QPORTCFG_INPUT_FLAGS_PATH_TX UINT32_C(0x0)
19433 #define HWRM_QUEUE_QPORTCFG_INPUT_FLAGS_PATH_RX UINT32_C(0x1)
19434 #define HWRM_QUEUE_QPORTCFG_INPUT_FLAGS_PATH_LAST \
19435 HWRM_QUEUE_QPORTCFG_INPUT_FLAGS_PATH_RX
19437 * Port ID of port for which the queue configuration is being
19438 * queried. This field is only required when sent by IPC.
19442 * Drivers will set this capability when it can use
19443 * queue_idx_service_profile to map the queues to application.
19445 uint8_t drv_qmap_cap;
19447 #define HWRM_QUEUE_QPORTCFG_INPUT_DRV_QMAP_CAP_DISABLED UINT32_C(0x0)
19449 #define HWRM_QUEUE_QPORTCFG_INPUT_DRV_QMAP_CAP_ENABLED UINT32_C(0x1)
19450 #define HWRM_QUEUE_QPORTCFG_INPUT_DRV_QMAP_CAP_LAST \
19451 HWRM_QUEUE_QPORTCFG_INPUT_DRV_QMAP_CAP_ENABLED
19455 /* hwrm_queue_qportcfg_output (size:256b/32B) */
19456 struct hwrm_queue_qportcfg_output {
19457 /* The specific error status for the command. */
19458 uint16_t error_code;
19459 /* The HWRM command request type. */
19461 /* The sequence ID from the original command. */
19463 /* The length of the response data in number of bytes. */
19466 * The maximum number of queues that can be configured on this
19468 * Valid values range from 1 through 8.
19470 uint8_t max_configurable_queues;
19472 * The maximum number of lossless queues that can be configured
19474 * Valid values range from 0 through 8.
19476 uint8_t max_configurable_lossless_queues;
19478 * Bitmask indicating which queues can be configured by the
19479 * hwrm_queue_cfg command.
19481 * Each bit represents a specific queue where bit 0 represents
19482 * queue 0 and bit 7 represents queue 7.
19483 * # A value of 0 indicates that the queue is not configurable
19484 * by the hwrm_queue_cfg command.
19485 * # A value of 1 indicates that the queue is configurable.
19486 * # A hwrm_queue_cfg command shall return error when trying to
19487 * configure a queue not configurable.
19489 uint8_t queue_cfg_allowed;
19490 /* Information about queue configuration. */
19491 uint8_t queue_cfg_info;
19493 * If this flag is set to '1', then the queues are
19494 * configured asymmetrically on TX and RX sides.
19495 * If this flag is set to '0', then the queues are
19496 * configured symmetrically on TX and RX sides. For
19497 * symmetric configuration, the queue configuration
19498 * including queue ids and service profiles on the
19499 * TX side is the same as the corresponding queue
19500 * configuration on the RX side.
19502 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_CFG_INFO_ASYM_CFG \
19505 * Bitmask indicating which queues can be configured by the
19506 * hwrm_queue_pfcenable_cfg command.
19508 * Each bit represents a specific priority where bit 0 represents
19509 * priority 0 and bit 7 represents priority 7.
19510 * # A value of 0 indicates that the priority is not configurable by
19511 * the hwrm_queue_pfcenable_cfg command.
19512 * # A value of 1 indicates that the priority is configurable.
19513 * # A hwrm_queue_pfcenable_cfg command shall return error when
19514 * trying to configure a priority that is not configurable.
19516 uint8_t queue_pfcenable_cfg_allowed;
19518 * Bitmask indicating which queues can be configured by the
19519 * hwrm_queue_pri2cos_cfg command.
19521 * Each bit represents a specific queue where bit 0 represents
19522 * queue 0 and bit 7 represents queue 7.
19523 * # A value of 0 indicates that the queue is not configurable
19524 * by the hwrm_queue_pri2cos_cfg command.
19525 * # A value of 1 indicates that the queue is configurable.
19526 * # A hwrm_queue_pri2cos_cfg command shall return error when
19527 * trying to configure a queue that is not configurable.
19529 uint8_t queue_pri2cos_cfg_allowed;
19531 * Bitmask indicating which queues can be configured by the
19532 * hwrm_queue_pri2cos_cfg command.
19534 * Each bit represents a specific queue where bit 0 represents
19535 * queue 0 and bit 7 represents queue 7.
19536 * # A value of 0 indicates that the queue is not configurable
19537 * by the hwrm_queue_pri2cos_cfg command.
19538 * # A value of 1 indicates that the queue is configurable.
19539 * # A hwrm_queue_pri2cos_cfg command shall return error when
19540 * trying to configure a queue not configurable.
19542 uint8_t queue_cos2bw_cfg_allowed;
19544 * ID of CoS Queue 0.
19547 * # This ID can be used on any subsequent call to an hwrm command
19548 * that takes a queue id.
19549 * # IDs must always be queried by this command before any use
19550 * by the driver or software.
19551 * # Any driver or software should not make any assumptions about
19553 * # A value of 0xff indicates that the queue is not available.
19554 * # Available queues may not be in sequential order.
19557 /* This value is applicable to CoS queues only. */
19558 uint8_t queue_id0_service_profile;
19559 /* Lossy (best-effort) */
19560 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID0_SERVICE_PROFILE_LOSSY \
19562 /* Lossless (legacy) */
19563 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID0_SERVICE_PROFILE_LOSSLESS \
19565 /* Lossless RoCE */
19566 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID0_SERVICE_PROFILE_LOSSLESS_ROCE \
19568 /* Lossy RoCE CNP */
19569 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID0_SERVICE_PROFILE_LOSSY_ROCE_CNP \
19572 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID0_SERVICE_PROFILE_LOSSLESS_NIC \
19574 /* Set to 0xFF... (All Fs) if there is no service profile specified */
19575 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID0_SERVICE_PROFILE_UNKNOWN \
19577 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID0_SERVICE_PROFILE_LAST \
19578 HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID0_SERVICE_PROFILE_UNKNOWN
19580 * ID of CoS Queue 1.
19583 * # This ID can be used on any subsequent call to an hwrm command
19584 * that takes a queue id.
19585 * # IDs must always be queried by this command before any use
19586 * by the driver or software.
19587 * # Any driver or software should not make any assumptions about
19589 * # A value of 0xff indicates that the queue is not available.
19590 * # Available queues may not be in sequential order.
19593 /* This value is applicable to CoS queues only. */
19594 uint8_t queue_id1_service_profile;
19595 /* Lossy (best-effort) */
19596 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID1_SERVICE_PROFILE_LOSSY \
19598 /* Lossless (legacy) */
19599 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID1_SERVICE_PROFILE_LOSSLESS \
19601 /* Lossless RoCE */
19602 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID1_SERVICE_PROFILE_LOSSLESS_ROCE \
19604 /* Lossy RoCE CNP */
19605 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID1_SERVICE_PROFILE_LOSSY_ROCE_CNP \
19608 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID1_SERVICE_PROFILE_LOSSLESS_NIC \
19610 /* Set to 0xFF... (All Fs) if there is no service profile specified */
19611 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID1_SERVICE_PROFILE_UNKNOWN \
19613 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID1_SERVICE_PROFILE_LAST \
19614 HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID1_SERVICE_PROFILE_UNKNOWN
19616 * ID of CoS Queue 2.
19619 * # This ID can be used on any subsequent call to an hwrm command
19620 * that takes a queue id.
19621 * # IDs must always be queried by this command before any use
19622 * by the driver or software.
19623 * # Any driver or software should not make any assumptions about
19625 * # A value of 0xff indicates that the queue is not available.
19626 * # Available queues may not be in sequential order.
19629 /* This value is applicable to CoS queues only. */
19630 uint8_t queue_id2_service_profile;
19631 /* Lossy (best-effort) */
19632 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID2_SERVICE_PROFILE_LOSSY \
19634 /* Lossless (legacy) */
19635 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID2_SERVICE_PROFILE_LOSSLESS \
19637 /* Lossless RoCE */
19638 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID2_SERVICE_PROFILE_LOSSLESS_ROCE \
19640 /* Lossy RoCE CNP */
19641 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID2_SERVICE_PROFILE_LOSSY_ROCE_CNP \
19644 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID2_SERVICE_PROFILE_LOSSLESS_NIC \
19646 /* Set to 0xFF... (All Fs) if there is no service profile specified */
19647 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID2_SERVICE_PROFILE_UNKNOWN \
19649 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID2_SERVICE_PROFILE_LAST \
19650 HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID2_SERVICE_PROFILE_UNKNOWN
19652 * ID of CoS Queue 3.
19655 * # This ID can be used on any subsequent call to an hwrm command
19656 * that takes a queue id.
19657 * # IDs must always be queried by this command before any use
19658 * by the driver or software.
19659 * # Any driver or software should not make any assumptions about
19661 * # A value of 0xff indicates that the queue is not available.
19662 * # Available queues may not be in sequential order.
19665 /* This value is applicable to CoS queues only. */
19666 uint8_t queue_id3_service_profile;
19667 /* Lossy (best-effort) */
19668 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID3_SERVICE_PROFILE_LOSSY \
19670 /* Lossless (legacy) */
19671 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID3_SERVICE_PROFILE_LOSSLESS \
19673 /* Lossless RoCE */
19674 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID3_SERVICE_PROFILE_LOSSLESS_ROCE \
19676 /* Lossy RoCE CNP */
19677 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID3_SERVICE_PROFILE_LOSSY_ROCE_CNP \
19680 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID3_SERVICE_PROFILE_LOSSLESS_NIC \
19682 /* Set to 0xFF... (All Fs) if there is no service profile specified */
19683 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID3_SERVICE_PROFILE_UNKNOWN \
19685 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID3_SERVICE_PROFILE_LAST \
19686 HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID3_SERVICE_PROFILE_UNKNOWN
19688 * ID of CoS Queue 4.
19691 * # This ID can be used on any subsequent call to an hwrm command
19692 * that takes a queue id.
19693 * # IDs must always be queried by this command before any use
19694 * by the driver or software.
19695 * # Any driver or software should not make any assumptions about
19697 * # A value of 0xff indicates that the queue is not available.
19698 * # Available queues may not be in sequential order.
19701 /* This value is applicable to CoS queues only. */
19702 uint8_t queue_id4_service_profile;
19703 /* Lossy (best-effort) */
19704 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID4_SERVICE_PROFILE_LOSSY \
19706 /* Lossless (legacy) */
19707 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID4_SERVICE_PROFILE_LOSSLESS \
19709 /* Lossless RoCE */
19710 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID4_SERVICE_PROFILE_LOSSLESS_ROCE \
19712 /* Lossy RoCE CNP */
19713 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID4_SERVICE_PROFILE_LOSSY_ROCE_CNP \
19716 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID4_SERVICE_PROFILE_LOSSLESS_NIC \
19718 /* Set to 0xFF... (All Fs) if there is no service profile specified */
19719 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID4_SERVICE_PROFILE_UNKNOWN \
19721 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID4_SERVICE_PROFILE_LAST \
19722 HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID4_SERVICE_PROFILE_UNKNOWN
19724 * ID of CoS Queue 5.
19727 * # This ID can be used on any subsequent call to an hwrm command
19728 * that takes a queue id.
19729 * # IDs must always be queried by this command before any use
19730 * by the driver or software.
19731 * # Any driver or software should not make any assumptions about
19733 * # A value of 0xff indicates that the queue is not available.
19734 * # Available queues may not be in sequential order.
19737 /* This value is applicable to CoS queues only. */
19738 uint8_t queue_id5_service_profile;
19739 /* Lossy (best-effort) */
19740 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID5_SERVICE_PROFILE_LOSSY \
19742 /* Lossless (legacy) */
19743 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID5_SERVICE_PROFILE_LOSSLESS \
19745 /* Lossless RoCE */
19746 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID5_SERVICE_PROFILE_LOSSLESS_ROCE \
19748 /* Lossy RoCE CNP */
19749 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID5_SERVICE_PROFILE_LOSSY_ROCE_CNP \
19752 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID5_SERVICE_PROFILE_LOSSLESS_NIC \
19754 /* Set to 0xFF... (All Fs) if there is no service profile specified */
19755 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID5_SERVICE_PROFILE_UNKNOWN \
19757 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID5_SERVICE_PROFILE_LAST \
19758 HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID5_SERVICE_PROFILE_UNKNOWN
19760 * ID of CoS Queue 6.
19763 * # This ID can be used on any subsequent call to an hwrm command
19764 * that takes a queue id.
19765 * # IDs must always be queried by this command before any use
19766 * by the driver or software.
19767 * # Any driver or software should not make any assumptions about
19769 * # A value of 0xff indicates that the queue is not available.
19770 * # Available queues may not be in sequential order.
19773 /* This value is applicable to CoS queues only. */
19774 uint8_t queue_id6_service_profile;
19775 /* Lossy (best-effort) */
19776 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID6_SERVICE_PROFILE_LOSSY \
19778 /* Lossless (legacy) */
19779 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID6_SERVICE_PROFILE_LOSSLESS \
19781 /* Lossless RoCE */
19782 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID6_SERVICE_PROFILE_LOSSLESS_ROCE \
19784 /* Lossy RoCE CNP */
19785 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID6_SERVICE_PROFILE_LOSSY_ROCE_CNP \
19788 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID6_SERVICE_PROFILE_LOSSLESS_NIC \
19790 /* Set to 0xFF... (All Fs) if there is no service profile specified */
19791 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID6_SERVICE_PROFILE_UNKNOWN \
19793 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID6_SERVICE_PROFILE_LAST \
19794 HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID6_SERVICE_PROFILE_UNKNOWN
19796 * ID of CoS Queue 7.
19799 * # This ID can be used on any subsequent call to an hwrm command
19800 * that takes a queue id.
19801 * # IDs must always be queried by this command before any use
19802 * by the driver or software.
19803 * # Any driver or software should not make any assumptions about
19805 * # A value of 0xff indicates that the queue is not available.
19806 * # Available queues may not be in sequential order.
19809 /* This value is applicable to CoS queues only. */
19810 uint8_t queue_id7_service_profile;
19811 /* Lossy (best-effort) */
19812 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID7_SERVICE_PROFILE_LOSSY \
19814 /* Lossless (legacy) */
19815 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID7_SERVICE_PROFILE_LOSSLESS \
19817 /* Lossless RoCE */
19818 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID7_SERVICE_PROFILE_LOSSLESS_ROCE \
19820 /* Lossy RoCE CNP */
19821 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID7_SERVICE_PROFILE_LOSSY_ROCE_CNP \
19824 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID7_SERVICE_PROFILE_LOSSLESS_NIC \
19826 /* Set to 0xFF... (All Fs) if there is no service profile specified */
19827 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID7_SERVICE_PROFILE_UNKNOWN \
19829 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID7_SERVICE_PROFILE_LAST \
19830 HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID7_SERVICE_PROFILE_UNKNOWN
19832 * This field is used in Output records to indicate that the output
19833 * is completely written to RAM. This field should be read as '1'
19834 * to indicate that the output has been completely written.
19835 * When writing a command completion or response to an internal processor,
19836 * the order of writes has to be such that this field is written last.
19841 /*******************
19842 * hwrm_queue_qcfg *
19843 *******************/
19846 /* hwrm_queue_qcfg_input (size:192b/24B) */
19847 struct hwrm_queue_qcfg_input {
19848 /* The HWRM command request type. */
19851 * The completion ring to send the completion event on. This should
19852 * be the NQ ID returned from the `nq_alloc` HWRM command.
19854 uint16_t cmpl_ring;
19856 * The sequence ID is used by the driver for tracking multiple
19857 * commands. This ID is treated as opaque data by the firmware and
19858 * the value is returned in the `hwrm_resp_hdr` upon completion.
19862 * The target ID of the command:
19863 * * 0x0-0xFFF8 - The function ID
19864 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
19865 * * 0xFFFD - Reserved for user-space HWRM interface
19868 uint16_t target_id;
19870 * A physical address pointer pointing to a host buffer that the
19871 * command's response data will be written. This can be either a host
19872 * physical address (HPA) or a guest physical address (GPA) and must
19873 * point to a physically contiguous block of memory.
19875 uint64_t resp_addr;
19878 * Enumeration denoting the RX, TX type of the resource.
19879 * This enumeration is used for resources that are similar for both
19880 * TX and RX paths of the chip.
19882 #define HWRM_QUEUE_QCFG_INPUT_FLAGS_PATH UINT32_C(0x1)
19884 #define HWRM_QUEUE_QCFG_INPUT_FLAGS_PATH_TX UINT32_C(0x0)
19886 #define HWRM_QUEUE_QCFG_INPUT_FLAGS_PATH_RX UINT32_C(0x1)
19887 #define HWRM_QUEUE_QCFG_INPUT_FLAGS_PATH_LAST \
19888 HWRM_QUEUE_QCFG_INPUT_FLAGS_PATH_RX
19889 /* Queue ID of the queue. */
19893 /* hwrm_queue_qcfg_output (size:128b/16B) */
19894 struct hwrm_queue_qcfg_output {
19895 /* The specific error status for the command. */
19896 uint16_t error_code;
19897 /* The HWRM command request type. */
19899 /* The sequence ID from the original command. */
19901 /* The length of the response data in number of bytes. */
19904 * This value is the estimate packet length used in the
19907 uint32_t queue_len;
19908 /* This value is applicable to CoS queues only. */
19909 uint8_t service_profile;
19910 /* Lossy (best-effort) */
19911 #define HWRM_QUEUE_QCFG_OUTPUT_SERVICE_PROFILE_LOSSY UINT32_C(0x0)
19913 #define HWRM_QUEUE_QCFG_OUTPUT_SERVICE_PROFILE_LOSSLESS UINT32_C(0x1)
19914 /* Set to 0xFF... (All Fs) if there is no service profile specified */
19915 #define HWRM_QUEUE_QCFG_OUTPUT_SERVICE_PROFILE_UNKNOWN UINT32_C(0xff)
19916 #define HWRM_QUEUE_QCFG_OUTPUT_SERVICE_PROFILE_LAST \
19917 HWRM_QUEUE_QCFG_OUTPUT_SERVICE_PROFILE_UNKNOWN
19918 /* Information about queue configuration. */
19919 uint8_t queue_cfg_info;
19921 * If this flag is set to '1', then the queue is
19922 * configured asymmetrically on TX and RX sides.
19923 * If this flag is set to '0', then this queue is
19924 * configured symmetrically on TX and RX sides.
19926 #define HWRM_QUEUE_QCFG_OUTPUT_QUEUE_CFG_INFO_ASYM_CFG \
19930 * This field is used in Output records to indicate that the output
19931 * is completely written to RAM. This field should be read as '1'
19932 * to indicate that the output has been completely written.
19933 * When writing a command completion or response to an internal processor,
19934 * the order of writes has to be such that this field is written last.
19939 /******************
19941 ******************/
19944 /* hwrm_queue_cfg_input (size:320b/40B) */
19945 struct hwrm_queue_cfg_input {
19946 /* The HWRM command request type. */
19949 * The completion ring to send the completion event on. This should
19950 * be the NQ ID returned from the `nq_alloc` HWRM command.
19952 uint16_t cmpl_ring;
19954 * The sequence ID is used by the driver for tracking multiple
19955 * commands. This ID is treated as opaque data by the firmware and
19956 * the value is returned in the `hwrm_resp_hdr` upon completion.
19960 * The target ID of the command:
19961 * * 0x0-0xFFF8 - The function ID
19962 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
19963 * * 0xFFFD - Reserved for user-space HWRM interface
19966 uint16_t target_id;
19968 * A physical address pointer pointing to a host buffer that the
19969 * command's response data will be written. This can be either a host
19970 * physical address (HPA) or a guest physical address (GPA) and must
19971 * point to a physically contiguous block of memory.
19973 uint64_t resp_addr;
19976 * Enumeration denoting the RX, TX, or both directions applicable to the resource.
19977 * This enumeration is used for resources that are similar for both
19978 * TX and RX paths of the chip.
19980 #define HWRM_QUEUE_CFG_INPUT_FLAGS_PATH_MASK UINT32_C(0x3)
19981 #define HWRM_QUEUE_CFG_INPUT_FLAGS_PATH_SFT 0
19983 #define HWRM_QUEUE_CFG_INPUT_FLAGS_PATH_TX UINT32_C(0x0)
19985 #define HWRM_QUEUE_CFG_INPUT_FLAGS_PATH_RX UINT32_C(0x1)
19986 /* Bi-directional (Symmetrically applicable to TX and RX paths) */
19987 #define HWRM_QUEUE_CFG_INPUT_FLAGS_PATH_BIDIR UINT32_C(0x2)
19988 #define HWRM_QUEUE_CFG_INPUT_FLAGS_PATH_LAST \
19989 HWRM_QUEUE_CFG_INPUT_FLAGS_PATH_BIDIR
19992 * This bit must be '1' for the dflt_len field to be
19995 #define HWRM_QUEUE_CFG_INPUT_ENABLES_DFLT_LEN UINT32_C(0x1)
19997 * This bit must be '1' for the service_profile field to be
20000 #define HWRM_QUEUE_CFG_INPUT_ENABLES_SERVICE_PROFILE UINT32_C(0x2)
20001 /* Queue ID of queue that is to be configured by this function. */
20004 * This value is a the estimate packet length used in the
20006 * Set to 0xFF... (All Fs) to not adjust this value.
20009 /* This value is applicable to CoS queues only. */
20010 uint8_t service_profile;
20011 /* Lossy (best-effort) */
20012 #define HWRM_QUEUE_CFG_INPUT_SERVICE_PROFILE_LOSSY UINT32_C(0x0)
20014 #define HWRM_QUEUE_CFG_INPUT_SERVICE_PROFILE_LOSSLESS UINT32_C(0x1)
20015 /* Set to 0xFF... (All Fs) if there is no service profile specified */
20016 #define HWRM_QUEUE_CFG_INPUT_SERVICE_PROFILE_UNKNOWN UINT32_C(0xff)
20017 #define HWRM_QUEUE_CFG_INPUT_SERVICE_PROFILE_LAST \
20018 HWRM_QUEUE_CFG_INPUT_SERVICE_PROFILE_UNKNOWN
20019 uint8_t unused_0[7];
20022 /* hwrm_queue_cfg_output (size:128b/16B) */
20023 struct hwrm_queue_cfg_output {
20024 /* The specific error status for the command. */
20025 uint16_t error_code;
20026 /* The HWRM command request type. */
20028 /* The sequence ID from the original command. */
20030 /* The length of the response data in number of bytes. */
20032 uint8_t unused_0[7];
20034 * This field is used in Output records to indicate that the output
20035 * is completely written to RAM. This field should be read as '1'
20036 * to indicate that the output has been completely written.
20037 * When writing a command completion or response to an internal processor,
20038 * the order of writes has to be such that this field is written last.
20043 /*****************************
20044 * hwrm_queue_pfcenable_qcfg *
20045 *****************************/
20048 /* hwrm_queue_pfcenable_qcfg_input (size:192b/24B) */
20049 struct hwrm_queue_pfcenable_qcfg_input {
20050 /* The HWRM command request type. */
20053 * The completion ring to send the completion event on. This should
20054 * be the NQ ID returned from the `nq_alloc` HWRM command.
20056 uint16_t cmpl_ring;
20058 * The sequence ID is used by the driver for tracking multiple
20059 * commands. This ID is treated as opaque data by the firmware and
20060 * the value is returned in the `hwrm_resp_hdr` upon completion.
20064 * The target ID of the command:
20065 * * 0x0-0xFFF8 - The function ID
20066 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
20067 * * 0xFFFD - Reserved for user-space HWRM interface
20070 uint16_t target_id;
20072 * A physical address pointer pointing to a host buffer that the
20073 * command's response data will be written. This can be either a host
20074 * physical address (HPA) or a guest physical address (GPA) and must
20075 * point to a physically contiguous block of memory.
20077 uint64_t resp_addr;
20079 * Port ID of port for which the table is being configured.
20080 * The HWRM needs to check whether this function is allowed
20081 * to configure pri2cos mapping on this port.
20084 uint8_t unused_0[6];
20087 /* hwrm_queue_pfcenable_qcfg_output (size:128b/16B) */
20088 struct hwrm_queue_pfcenable_qcfg_output {
20089 /* The specific error status for the command. */
20090 uint16_t error_code;
20091 /* The HWRM command request type. */
20093 /* The sequence ID from the original command. */
20095 /* The length of the response data in number of bytes. */
20098 /* If set to 1, then PFC is enabled on PRI 0. */
20099 #define HWRM_QUEUE_PFCENABLE_QCFG_OUTPUT_FLAGS_PRI0_PFC_ENABLED \
20101 /* If set to 1, then PFC is enabled on PRI 1. */
20102 #define HWRM_QUEUE_PFCENABLE_QCFG_OUTPUT_FLAGS_PRI1_PFC_ENABLED \
20104 /* If set to 1, then PFC is enabled on PRI 2. */
20105 #define HWRM_QUEUE_PFCENABLE_QCFG_OUTPUT_FLAGS_PRI2_PFC_ENABLED \
20107 /* If set to 1, then PFC is enabled on PRI 3. */
20108 #define HWRM_QUEUE_PFCENABLE_QCFG_OUTPUT_FLAGS_PRI3_PFC_ENABLED \
20110 /* If set to 1, then PFC is enabled on PRI 4. */
20111 #define HWRM_QUEUE_PFCENABLE_QCFG_OUTPUT_FLAGS_PRI4_PFC_ENABLED \
20113 /* If set to 1, then PFC is enabled on PRI 5. */
20114 #define HWRM_QUEUE_PFCENABLE_QCFG_OUTPUT_FLAGS_PRI5_PFC_ENABLED \
20116 /* If set to 1, then PFC is enabled on PRI 6. */
20117 #define HWRM_QUEUE_PFCENABLE_QCFG_OUTPUT_FLAGS_PRI6_PFC_ENABLED \
20119 /* If set to 1, then PFC is enabled on PRI 7. */
20120 #define HWRM_QUEUE_PFCENABLE_QCFG_OUTPUT_FLAGS_PRI7_PFC_ENABLED \
20122 /* If set to 1, then PFC WatchDog is requested to be enabled on PRI0. */
20123 #define HWRM_QUEUE_PFCENABLE_QCFG_OUTPUT_FLAGS_PRI0_PFC_WATCHDOG_ENABLED \
20125 /* If set to 1, then PFC WatchDog is requested to be enabled on PRI1. */
20126 #define HWRM_QUEUE_PFCENABLE_QCFG_OUTPUT_FLAGS_PRI1_PFC_WATCHDOG_ENABLED \
20128 /* If set to 1, then PFC WatchDog is requested to be enabled on PRI2. */
20129 #define HWRM_QUEUE_PFCENABLE_QCFG_OUTPUT_FLAGS_PRI2_PFC_WATCHDOG_ENABLED \
20131 /* If set to 1, then PFC WatchDog is requested to be enabled on PRI3. */
20132 #define HWRM_QUEUE_PFCENABLE_QCFG_OUTPUT_FLAGS_PRI3_PFC_WATCHDOG_ENABLED \
20134 /* If set to 1, then PFC WatchDog is requested to be enabled on PRI4. */
20135 #define HWRM_QUEUE_PFCENABLE_QCFG_OUTPUT_FLAGS_PRI4_PFC_WATCHDOG_ENABLED \
20137 /* If set to 1, then PFC WatchDog is requested to be enabled on PRI5. */
20138 #define HWRM_QUEUE_PFCENABLE_QCFG_OUTPUT_FLAGS_PRI5_PFC_WATCHDOG_ENABLED \
20140 /* If set to 1, then PFC WatchDog is requested to be enabled on PRI6. */
20141 #define HWRM_QUEUE_PFCENABLE_QCFG_OUTPUT_FLAGS_PRI6_PFC_WATCHDOG_ENABLED \
20143 /* If set to 1, then PFC WatchDog is requested to be enabled on PRI7. */
20144 #define HWRM_QUEUE_PFCENABLE_QCFG_OUTPUT_FLAGS_PRI7_PFC_WATCHDOG_ENABLED \
20146 uint8_t unused_0[3];
20148 * This field is used in Output records to indicate that the output
20149 * is completely written to RAM. This field should be read as '1'
20150 * to indicate that the output has been completely written.
20151 * When writing a command completion or response to an internal processor,
20152 * the order of writes has to be such that this field is written last.
20157 /****************************
20158 * hwrm_queue_pfcenable_cfg *
20159 ****************************/
20162 /* hwrm_queue_pfcenable_cfg_input (size:192b/24B) */
20163 struct hwrm_queue_pfcenable_cfg_input {
20164 /* The HWRM command request type. */
20167 * The completion ring to send the completion event on. This should
20168 * be the NQ ID returned from the `nq_alloc` HWRM command.
20170 uint16_t cmpl_ring;
20172 * The sequence ID is used by the driver for tracking multiple
20173 * commands. This ID is treated as opaque data by the firmware and
20174 * the value is returned in the `hwrm_resp_hdr` upon completion.
20178 * The target ID of the command:
20179 * * 0x0-0xFFF8 - The function ID
20180 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
20181 * * 0xFFFD - Reserved for user-space HWRM interface
20184 uint16_t target_id;
20186 * A physical address pointer pointing to a host buffer that the
20187 * command's response data will be written. This can be either a host
20188 * physical address (HPA) or a guest physical address (GPA) and must
20189 * point to a physically contiguous block of memory.
20191 uint64_t resp_addr;
20193 /* If set to 1, then PFC is requested to be enabled on PRI 0. */
20194 #define HWRM_QUEUE_PFCENABLE_CFG_INPUT_FLAGS_PRI0_PFC_ENABLED \
20196 /* If set to 1, then PFC is requested to be enabled on PRI 1. */
20197 #define HWRM_QUEUE_PFCENABLE_CFG_INPUT_FLAGS_PRI1_PFC_ENABLED \
20199 /* If set to 1, then PFC is requested to be enabled on PRI 2. */
20200 #define HWRM_QUEUE_PFCENABLE_CFG_INPUT_FLAGS_PRI2_PFC_ENABLED \
20202 /* If set to 1, then PFC is requested to be enabled on PRI 3. */
20203 #define HWRM_QUEUE_PFCENABLE_CFG_INPUT_FLAGS_PRI3_PFC_ENABLED \
20205 /* If set to 1, then PFC is requested to be enabled on PRI 4. */
20206 #define HWRM_QUEUE_PFCENABLE_CFG_INPUT_FLAGS_PRI4_PFC_ENABLED \
20208 /* If set to 1, then PFC is requested to be enabled on PRI 5. */
20209 #define HWRM_QUEUE_PFCENABLE_CFG_INPUT_FLAGS_PRI5_PFC_ENABLED \
20211 /* If set to 1, then PFC is requested to be enabled on PRI 6. */
20212 #define HWRM_QUEUE_PFCENABLE_CFG_INPUT_FLAGS_PRI6_PFC_ENABLED \
20214 /* If set to 1, then PFC is requested to be enabled on PRI 7. */
20215 #define HWRM_QUEUE_PFCENABLE_CFG_INPUT_FLAGS_PRI7_PFC_ENABLED \
20217 /* If set to 1, then PFC WatchDog is requested to be enabled on PRI0. */
20218 #define HWRM_QUEUE_PFCENABLE_CFG_INPUT_FLAGS_PRI0_PFC_WATCHDOG_ENABLED \
20220 /* If set to 1, then PFC WatchDog is requested to be enabled on PRI1. */
20221 #define HWRM_QUEUE_PFCENABLE_CFG_INPUT_FLAGS_PRI1_PFC_WATCHDOG_ENABLED \
20223 /* If set to 1, then PFC WatchDog is requested to be enabled on PRI2. */
20224 #define HWRM_QUEUE_PFCENABLE_CFG_INPUT_FLAGS_PRI2_PFC_WATCHDOG_ENABLED \
20226 /* If set to 1, then PFC WatchDog is requested to be enabled on PRI3. */
20227 #define HWRM_QUEUE_PFCENABLE_CFG_INPUT_FLAGS_PRI3_PFC_WATCHDOG_ENABLED \
20229 /* If set to 1, then PFC WatchDog is requested to be enabled on PRI4. */
20230 #define HWRM_QUEUE_PFCENABLE_CFG_INPUT_FLAGS_PRI4_PFC_WATCHDOG_ENABLED \
20232 /* If set to 1, then PFC WatchDog is requested to be enabled on PRI5. */
20233 #define HWRM_QUEUE_PFCENABLE_CFG_INPUT_FLAGS_PRI5_PFC_WATCHDOG_ENABLED \
20235 /* If set to 1, then PFC WatchDog is requested to be enabled on PRI6. */
20236 #define HWRM_QUEUE_PFCENABLE_CFG_INPUT_FLAGS_PRI6_PFC_WATCHDOG_ENABLED \
20238 /* If set to 1, then PFC WatchDog is requested to be enabled on PRI7. */
20239 #define HWRM_QUEUE_PFCENABLE_CFG_INPUT_FLAGS_PRI7_PFC_WATCHDOG_ENABLED \
20242 * Port ID of port for which the table is being configured.
20243 * The HWRM needs to check whether this function is allowed
20244 * to configure pri2cos mapping on this port.
20247 uint8_t unused_0[2];
20250 /* hwrm_queue_pfcenable_cfg_output (size:128b/16B) */
20251 struct hwrm_queue_pfcenable_cfg_output {
20252 /* The specific error status for the command. */
20253 uint16_t error_code;
20254 /* The HWRM command request type. */
20256 /* The sequence ID from the original command. */
20258 /* The length of the response data in number of bytes. */
20260 uint8_t unused_0[7];
20262 * This field is used in Output records to indicate that the output
20263 * is completely written to RAM. This field should be read as '1'
20264 * to indicate that the output has been completely written.
20265 * When writing a command completion or response to an internal processor,
20266 * the order of writes has to be such that this field is written last.
20271 /***************************
20272 * hwrm_queue_pri2cos_qcfg *
20273 ***************************/
20276 /* hwrm_queue_pri2cos_qcfg_input (size:192b/24B) */
20277 struct hwrm_queue_pri2cos_qcfg_input {
20278 /* The HWRM command request type. */
20281 * The completion ring to send the completion event on. This should
20282 * be the NQ ID returned from the `nq_alloc` HWRM command.
20284 uint16_t cmpl_ring;
20286 * The sequence ID is used by the driver for tracking multiple
20287 * commands. This ID is treated as opaque data by the firmware and
20288 * the value is returned in the `hwrm_resp_hdr` upon completion.
20292 * The target ID of the command:
20293 * * 0x0-0xFFF8 - The function ID
20294 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
20295 * * 0xFFFD - Reserved for user-space HWRM interface
20298 uint16_t target_id;
20300 * A physical address pointer pointing to a host buffer that the
20301 * command's response data will be written. This can be either a host
20302 * physical address (HPA) or a guest physical address (GPA) and must
20303 * point to a physically contiguous block of memory.
20305 uint64_t resp_addr;
20308 * Enumeration denoting the RX, TX type of the resource.
20309 * This enumeration is used for resources that are similar for both
20310 * TX and RX paths of the chip.
20312 #define HWRM_QUEUE_PRI2COS_QCFG_INPUT_FLAGS_PATH UINT32_C(0x1)
20314 #define HWRM_QUEUE_PRI2COS_QCFG_INPUT_FLAGS_PATH_TX UINT32_C(0x0)
20316 #define HWRM_QUEUE_PRI2COS_QCFG_INPUT_FLAGS_PATH_RX UINT32_C(0x1)
20317 #define HWRM_QUEUE_PRI2COS_QCFG_INPUT_FLAGS_PATH_LAST \
20318 HWRM_QUEUE_PRI2COS_QCFG_INPUT_FLAGS_PATH_RX
20320 * When this bit is set to '0', the query is
20321 * for PRI from tunnel headers.
20322 * When this bit is set to '1', the query is
20323 * for PRI from inner packet headers.
20325 #define HWRM_QUEUE_PRI2COS_QCFG_INPUT_FLAGS_IVLAN UINT32_C(0x2)
20327 * Port ID of port for which the table is being configured.
20328 * The HWRM needs to check whether this function is allowed
20329 * to configure pri2cos mapping on this port.
20332 uint8_t unused_0[3];
20335 /* hwrm_queue_pri2cos_qcfg_output (size:192b/24B) */
20336 struct hwrm_queue_pri2cos_qcfg_output {
20337 /* The specific error status for the command. */
20338 uint16_t error_code;
20339 /* The HWRM command request type. */
20341 /* The sequence ID from the original command. */
20343 /* The length of the response data in number of bytes. */
20346 * CoS Queue assigned to priority 0. This value can only
20347 * be changed before traffic has started.
20348 * A value of 0xff indicates that no CoS queue is assigned to the
20349 * specified priority.
20351 uint8_t pri0_cos_queue_id;
20353 * CoS Queue assigned to priority 1. This value can only
20354 * be changed before traffic has started.
20355 * A value of 0xff indicates that no CoS queue is assigned to the
20356 * specified priority.
20358 uint8_t pri1_cos_queue_id;
20360 * CoS Queue assigned to priority 2. This value can only
20361 * be changed before traffic has started.
20362 * A value of 0xff indicates that no CoS queue is assigned to the
20363 * specified priority.
20365 uint8_t pri2_cos_queue_id;
20367 * CoS Queue assigned to priority 3. This value can only
20368 * be changed before traffic has started.
20369 * A value of 0xff indicates that no CoS queue is assigned to the
20370 * specified priority.
20372 uint8_t pri3_cos_queue_id;
20374 * CoS Queue assigned to priority 4. This value can only
20375 * be changed before traffic has started.
20376 * A value of 0xff indicates that no CoS queue is assigned to the
20377 * specified priority.
20379 uint8_t pri4_cos_queue_id;
20381 * CoS Queue assigned to priority 5. This value can only
20382 * be changed before traffic has started.
20383 * A value of 0xff indicates that no CoS queue is assigned to the
20384 * specified priority.
20386 uint8_t pri5_cos_queue_id;
20388 * CoS Queue assigned to priority 6. This value can only
20389 * be changed before traffic has started.
20390 * A value of 0xff indicates that no CoS queue is assigned to the
20391 * specified priority.
20393 uint8_t pri6_cos_queue_id;
20395 * CoS Queue assigned to priority 7. This value can only
20396 * be changed before traffic has started.
20397 * A value of 0xff indicates that no CoS queue is assigned to the
20398 * specified priority.
20400 uint8_t pri7_cos_queue_id;
20401 /* Information about queue configuration. */
20402 uint8_t queue_cfg_info;
20404 * If this flag is set to '1', then the PRI to CoS
20405 * configuration is asymmetric on TX and RX sides.
20406 * If this flag is set to '0', then PRI to CoS configuration
20407 * is symmetric on TX and RX sides.
20409 #define HWRM_QUEUE_PRI2COS_QCFG_OUTPUT_QUEUE_CFG_INFO_ASYM_CFG \
20411 uint8_t unused_0[6];
20413 * This field is used in Output records to indicate that the output
20414 * is completely written to RAM. This field should be read as '1'
20415 * to indicate that the output has been completely written.
20416 * When writing a command completion or response to an internal processor,
20417 * the order of writes has to be such that this field is written last.
20422 /**************************
20423 * hwrm_queue_pri2cos_cfg *
20424 **************************/
20427 /* hwrm_queue_pri2cos_cfg_input (size:320b/40B) */
20428 struct hwrm_queue_pri2cos_cfg_input {
20429 /* The HWRM command request type. */
20432 * The completion ring to send the completion event on. This should
20433 * be the NQ ID returned from the `nq_alloc` HWRM command.
20435 uint16_t cmpl_ring;
20437 * The sequence ID is used by the driver for tracking multiple
20438 * commands. This ID is treated as opaque data by the firmware and
20439 * the value is returned in the `hwrm_resp_hdr` upon completion.
20443 * The target ID of the command:
20444 * * 0x0-0xFFF8 - The function ID
20445 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
20446 * * 0xFFFD - Reserved for user-space HWRM interface
20449 uint16_t target_id;
20451 * A physical address pointer pointing to a host buffer that the
20452 * command's response data will be written. This can be either a host
20453 * physical address (HPA) or a guest physical address (GPA) and must
20454 * point to a physically contiguous block of memory.
20456 uint64_t resp_addr;
20459 * Enumeration denoting the RX, TX, or both directions applicable to the resource.
20460 * This enumeration is used for resources that are similar for both
20461 * TX and RX paths of the chip.
20463 #define HWRM_QUEUE_PRI2COS_CFG_INPUT_FLAGS_PATH_MASK UINT32_C(0x3)
20464 #define HWRM_QUEUE_PRI2COS_CFG_INPUT_FLAGS_PATH_SFT 0
20466 #define HWRM_QUEUE_PRI2COS_CFG_INPUT_FLAGS_PATH_TX UINT32_C(0x0)
20468 #define HWRM_QUEUE_PRI2COS_CFG_INPUT_FLAGS_PATH_RX UINT32_C(0x1)
20469 /* Bi-directional (Symmetrically applicable to TX and RX paths) */
20470 #define HWRM_QUEUE_PRI2COS_CFG_INPUT_FLAGS_PATH_BIDIR UINT32_C(0x2)
20471 #define HWRM_QUEUE_PRI2COS_CFG_INPUT_FLAGS_PATH_LAST \
20472 HWRM_QUEUE_PRI2COS_CFG_INPUT_FLAGS_PATH_BIDIR
20474 * When this bit is set to '0', the mapping is requested
20475 * for PRI from tunnel headers.
20476 * When this bit is set to '1', the mapping is requested
20477 * for PRI from inner packet headers.
20479 #define HWRM_QUEUE_PRI2COS_CFG_INPUT_FLAGS_IVLAN UINT32_C(0x4)
20482 * This bit must be '1' for the pri0_cos_queue_id field to be
20485 #define HWRM_QUEUE_PRI2COS_CFG_INPUT_ENABLES_PRI0_COS_QUEUE_ID \
20488 * This bit must be '1' for the pri1_cos_queue_id field to be
20491 #define HWRM_QUEUE_PRI2COS_CFG_INPUT_ENABLES_PRI1_COS_QUEUE_ID \
20494 * This bit must be '1' for the pri2_cos_queue_id field to be
20497 #define HWRM_QUEUE_PRI2COS_CFG_INPUT_ENABLES_PRI2_COS_QUEUE_ID \
20500 * This bit must be '1' for the pri3_cos_queue_id field to be
20503 #define HWRM_QUEUE_PRI2COS_CFG_INPUT_ENABLES_PRI3_COS_QUEUE_ID \
20506 * This bit must be '1' for the pri4_cos_queue_id field to be
20509 #define HWRM_QUEUE_PRI2COS_CFG_INPUT_ENABLES_PRI4_COS_QUEUE_ID \
20512 * This bit must be '1' for the pri5_cos_queue_id field to be
20515 #define HWRM_QUEUE_PRI2COS_CFG_INPUT_ENABLES_PRI5_COS_QUEUE_ID \
20518 * This bit must be '1' for the pri6_cos_queue_id field to be
20521 #define HWRM_QUEUE_PRI2COS_CFG_INPUT_ENABLES_PRI6_COS_QUEUE_ID \
20524 * This bit must be '1' for the pri7_cos_queue_id field to be
20527 #define HWRM_QUEUE_PRI2COS_CFG_INPUT_ENABLES_PRI7_COS_QUEUE_ID \
20530 * Port ID of port for which the table is being configured.
20531 * The HWRM needs to check whether this function is allowed
20532 * to configure pri2cos mapping on this port.
20536 * CoS Queue assigned to priority 0. This value can only
20537 * be changed before traffic has started.
20539 uint8_t pri0_cos_queue_id;
20541 * CoS Queue assigned to priority 1. This value can only
20542 * be changed before traffic has started.
20544 uint8_t pri1_cos_queue_id;
20546 * CoS Queue assigned to priority 2 This value can only
20547 * be changed before traffic has started.
20549 uint8_t pri2_cos_queue_id;
20551 * CoS Queue assigned to priority 3. This value can only
20552 * be changed before traffic has started.
20554 uint8_t pri3_cos_queue_id;
20556 * CoS Queue assigned to priority 4. This value can only
20557 * be changed before traffic has started.
20559 uint8_t pri4_cos_queue_id;
20561 * CoS Queue assigned to priority 5. This value can only
20562 * be changed before traffic has started.
20564 uint8_t pri5_cos_queue_id;
20566 * CoS Queue assigned to priority 6. This value can only
20567 * be changed before traffic has started.
20569 uint8_t pri6_cos_queue_id;
20571 * CoS Queue assigned to priority 7. This value can only
20572 * be changed before traffic has started.
20574 uint8_t pri7_cos_queue_id;
20575 uint8_t unused_0[7];
20578 /* hwrm_queue_pri2cos_cfg_output (size:128b/16B) */
20579 struct hwrm_queue_pri2cos_cfg_output {
20580 /* The specific error status for the command. */
20581 uint16_t error_code;
20582 /* The HWRM command request type. */
20584 /* The sequence ID from the original command. */
20586 /* The length of the response data in number of bytes. */
20588 uint8_t unused_0[7];
20590 * This field is used in Output records to indicate that the output
20591 * is completely written to RAM. This field should be read as '1'
20592 * to indicate that the output has been completely written.
20593 * When writing a command completion or response to an internal processor,
20594 * the order of writes has to be such that this field is written last.
20599 /**************************
20600 * hwrm_queue_cos2bw_qcfg *
20601 **************************/
20604 /* hwrm_queue_cos2bw_qcfg_input (size:192b/24B) */
20605 struct hwrm_queue_cos2bw_qcfg_input {
20606 /* The HWRM command request type. */
20609 * The completion ring to send the completion event on. This should
20610 * be the NQ ID returned from the `nq_alloc` HWRM command.
20612 uint16_t cmpl_ring;
20614 * The sequence ID is used by the driver for tracking multiple
20615 * commands. This ID is treated as opaque data by the firmware and
20616 * the value is returned in the `hwrm_resp_hdr` upon completion.
20620 * The target ID of the command:
20621 * * 0x0-0xFFF8 - The function ID
20622 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
20623 * * 0xFFFD - Reserved for user-space HWRM interface
20626 uint16_t target_id;
20628 * A physical address pointer pointing to a host buffer that the
20629 * command's response data will be written. This can be either a host
20630 * physical address (HPA) or a guest physical address (GPA) and must
20631 * point to a physically contiguous block of memory.
20633 uint64_t resp_addr;
20635 * Port ID of port for which the table is being configured.
20636 * The HWRM needs to check whether this function is allowed
20637 * to configure TC BW assignment on this port.
20640 uint8_t unused_0[6];
20643 /* hwrm_queue_cos2bw_qcfg_output (size:896b/112B) */
20644 struct hwrm_queue_cos2bw_qcfg_output {
20645 /* The specific error status for the command. */
20646 uint16_t error_code;
20647 /* The HWRM command request type. */
20649 /* The sequence ID from the original command. */
20651 /* The length of the response data in number of bytes. */
20653 /* ID of CoS Queue 0. */
20658 * Minimum BW allocated to CoS Queue.
20659 * The HWRM will translate this value into byte counter and
20660 * time interval used for this COS inside the device.
20662 uint32_t queue_id0_min_bw;
20663 /* The bandwidth value. */
20664 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MIN_BW_BW_VALUE_MASK \
20665 UINT32_C(0xfffffff)
20666 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MIN_BW_BW_VALUE_SFT \
20668 /* The granularity of the value (bits or bytes). */
20669 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MIN_BW_SCALE \
20670 UINT32_C(0x10000000)
20671 /* Value is in bits. */
20672 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MIN_BW_SCALE_BITS \
20673 (UINT32_C(0x0) << 28)
20674 /* Value is in bytes. */
20675 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MIN_BW_SCALE_BYTES \
20676 (UINT32_C(0x1) << 28)
20677 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MIN_BW_SCALE_LAST \
20678 HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MIN_BW_SCALE_BYTES
20679 /* bw_value_unit is 3 b */
20680 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_MASK \
20681 UINT32_C(0xe0000000)
20682 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_SFT \
20684 /* Value is in Mb or MB (base 10). */
20685 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_MEGA \
20686 (UINT32_C(0x0) << 29)
20687 /* Value is in Kb or KB (base 10). */
20688 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_KILO \
20689 (UINT32_C(0x2) << 29)
20690 /* Value is in bits or bytes. */
20691 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_BASE \
20692 (UINT32_C(0x4) << 29)
20693 /* Value is in Gb or GB (base 10). */
20694 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_GIGA \
20695 (UINT32_C(0x6) << 29)
20696 /* Value is in 1/100th of a percentage of total bandwidth. */
20697 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 \
20698 (UINT32_C(0x1) << 29)
20700 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_INVALID \
20701 (UINT32_C(0x7) << 29)
20702 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_LAST \
20703 HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_INVALID
20705 * Maximum BW allocated to CoS Queue.
20706 * The HWRM will translate this value into byte counter and
20707 * time interval used for this COS inside the device.
20709 uint32_t queue_id0_max_bw;
20710 /* The bandwidth value. */
20711 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MAX_BW_BW_VALUE_MASK \
20712 UINT32_C(0xfffffff)
20713 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MAX_BW_BW_VALUE_SFT \
20715 /* The granularity of the value (bits or bytes). */
20716 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MAX_BW_SCALE \
20717 UINT32_C(0x10000000)
20718 /* Value is in bits. */
20719 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MAX_BW_SCALE_BITS \
20720 (UINT32_C(0x0) << 28)
20721 /* Value is in bytes. */
20722 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MAX_BW_SCALE_BYTES \
20723 (UINT32_C(0x1) << 28)
20724 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MAX_BW_SCALE_LAST \
20725 HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MAX_BW_SCALE_BYTES
20726 /* bw_value_unit is 3 b */
20727 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_MASK \
20728 UINT32_C(0xe0000000)
20729 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_SFT \
20731 /* Value is in Mb or MB (base 10). */
20732 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_MEGA \
20733 (UINT32_C(0x0) << 29)
20734 /* Value is in Kb or KB (base 10). */
20735 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_KILO \
20736 (UINT32_C(0x2) << 29)
20737 /* Value is in bits or bytes. */
20738 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_BASE \
20739 (UINT32_C(0x4) << 29)
20740 /* Value is in Gb or GB (base 10). */
20741 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_GIGA \
20742 (UINT32_C(0x6) << 29)
20743 /* Value is in 1/100th of a percentage of total bandwidth. */
20744 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 \
20745 (UINT32_C(0x1) << 29)
20747 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_INVALID \
20748 (UINT32_C(0x7) << 29)
20749 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_LAST \
20750 HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_INVALID
20751 /* Transmission Selection Algorithm (TSA) for CoS Queue. */
20752 uint8_t queue_id0_tsa_assign;
20753 /* Strict Priority */
20754 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_TSA_ASSIGN_SP \
20756 /* Enhanced Transmission Selection */
20757 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_TSA_ASSIGN_ETS \
20760 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_TSA_ASSIGN_RESERVED_FIRST \
20763 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_TSA_ASSIGN_RESERVED_LAST \
20766 * Priority level for strict priority. Valid only when the
20767 * tsa_assign is 0 - Strict Priority (SP)
20768 * 0..7 - Valid values.
20769 * 8..255 - Reserved.
20771 uint8_t queue_id0_pri_lvl;
20773 * Weight used to allocate remaining BW for this COS after
20774 * servicing guaranteed bandwidths for all COS.
20776 uint8_t queue_id0_bw_weight;
20777 /* ID of CoS Queue 1. */
20780 * Minimum BW allocated to CoS Queue.
20781 * The HWRM will translate this value into byte counter and
20782 * time interval used for this COS inside the device.
20784 uint32_t queue_id1_min_bw;
20785 /* The bandwidth value. */
20786 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MIN_BW_BW_VALUE_MASK \
20787 UINT32_C(0xfffffff)
20788 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MIN_BW_BW_VALUE_SFT \
20790 /* The granularity of the value (bits or bytes). */
20791 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MIN_BW_SCALE \
20792 UINT32_C(0x10000000)
20793 /* Value is in bits. */
20794 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MIN_BW_SCALE_BITS \
20795 (UINT32_C(0x0) << 28)
20796 /* Value is in bytes. */
20797 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MIN_BW_SCALE_BYTES \
20798 (UINT32_C(0x1) << 28)
20799 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MIN_BW_SCALE_LAST \
20800 HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MIN_BW_SCALE_BYTES
20801 /* bw_value_unit is 3 b */
20802 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_MASK \
20803 UINT32_C(0xe0000000)
20804 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_SFT \
20806 /* Value is in Mb or MB (base 10). */
20807 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_MEGA \
20808 (UINT32_C(0x0) << 29)
20809 /* Value is in Kb or KB (base 10). */
20810 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_KILO \
20811 (UINT32_C(0x2) << 29)
20812 /* Value is in bits or bytes. */
20813 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_BASE \
20814 (UINT32_C(0x4) << 29)
20815 /* Value is in Gb or GB (base 10). */
20816 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_GIGA \
20817 (UINT32_C(0x6) << 29)
20818 /* Value is in 1/100th of a percentage of total bandwidth. */
20819 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 \
20820 (UINT32_C(0x1) << 29)
20822 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_INVALID \
20823 (UINT32_C(0x7) << 29)
20824 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_LAST \
20825 HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_INVALID
20827 * Maximum BW allocated to CoS queue.
20828 * The HWRM will translate this value into byte counter and
20829 * time interval used for this COS inside the device.
20831 uint32_t queue_id1_max_bw;
20832 /* The bandwidth value. */
20833 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MAX_BW_BW_VALUE_MASK \
20834 UINT32_C(0xfffffff)
20835 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MAX_BW_BW_VALUE_SFT \
20837 /* The granularity of the value (bits or bytes). */
20838 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MAX_BW_SCALE \
20839 UINT32_C(0x10000000)
20840 /* Value is in bits. */
20841 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MAX_BW_SCALE_BITS \
20842 (UINT32_C(0x0) << 28)
20843 /* Value is in bytes. */
20844 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MAX_BW_SCALE_BYTES \
20845 (UINT32_C(0x1) << 28)
20846 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MAX_BW_SCALE_LAST \
20847 HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MAX_BW_SCALE_BYTES
20848 /* bw_value_unit is 3 b */
20849 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_MASK \
20850 UINT32_C(0xe0000000)
20851 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_SFT \
20853 /* Value is in Mb or MB (base 10). */
20854 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_MEGA \
20855 (UINT32_C(0x0) << 29)
20856 /* Value is in Kb or KB (base 10). */
20857 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_KILO \
20858 (UINT32_C(0x2) << 29)
20859 /* Value is in bits or bytes. */
20860 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_BASE \
20861 (UINT32_C(0x4) << 29)
20862 /* Value is in Gb or GB (base 10). */
20863 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_GIGA \
20864 (UINT32_C(0x6) << 29)
20865 /* Value is in 1/100th of a percentage of total bandwidth. */
20866 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 \
20867 (UINT32_C(0x1) << 29)
20869 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_INVALID \
20870 (UINT32_C(0x7) << 29)
20871 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_LAST \
20872 HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_INVALID
20873 /* Transmission Selection Algorithm (TSA) for CoS Queue. */
20874 uint8_t queue_id1_tsa_assign;
20875 /* Strict Priority */
20876 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_TSA_ASSIGN_SP \
20878 /* Enhanced Transmission Selection */
20879 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_TSA_ASSIGN_ETS \
20882 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_TSA_ASSIGN_RESERVED_FIRST \
20885 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_TSA_ASSIGN_RESERVED_LAST \
20888 * Priority level for strict priority. Valid only when the
20889 * tsa_assign is 0 - Strict Priority (SP)
20890 * 0..7 - Valid values.
20891 * 8..255 - Reserved.
20893 uint8_t queue_id1_pri_lvl;
20895 * Weight used to allocate remaining BW for this COS after
20896 * servicing guaranteed bandwidths for all COS.
20898 uint8_t queue_id1_bw_weight;
20899 /* ID of CoS Queue 2. */
20902 * Minimum BW allocated to CoS Queue.
20903 * The HWRM will translate this value into byte counter and
20904 * time interval used for this COS inside the device.
20906 uint32_t queue_id2_min_bw;
20907 /* The bandwidth value. */
20908 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MIN_BW_BW_VALUE_MASK \
20909 UINT32_C(0xfffffff)
20910 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MIN_BW_BW_VALUE_SFT \
20912 /* The granularity of the value (bits or bytes). */
20913 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MIN_BW_SCALE \
20914 UINT32_C(0x10000000)
20915 /* Value is in bits. */
20916 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MIN_BW_SCALE_BITS \
20917 (UINT32_C(0x0) << 28)
20918 /* Value is in bytes. */
20919 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MIN_BW_SCALE_BYTES \
20920 (UINT32_C(0x1) << 28)
20921 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MIN_BW_SCALE_LAST \
20922 HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MIN_BW_SCALE_BYTES
20923 /* bw_value_unit is 3 b */
20924 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_MASK \
20925 UINT32_C(0xe0000000)
20926 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_SFT \
20928 /* Value is in Mb or MB (base 10). */
20929 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_MEGA \
20930 (UINT32_C(0x0) << 29)
20931 /* Value is in Kb or KB (base 10). */
20932 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_KILO \
20933 (UINT32_C(0x2) << 29)
20934 /* Value is in bits or bytes. */
20935 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_BASE \
20936 (UINT32_C(0x4) << 29)
20937 /* Value is in Gb or GB (base 10). */
20938 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_GIGA \
20939 (UINT32_C(0x6) << 29)
20940 /* Value is in 1/100th of a percentage of total bandwidth. */
20941 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 \
20942 (UINT32_C(0x1) << 29)
20944 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_INVALID \
20945 (UINT32_C(0x7) << 29)
20946 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_LAST \
20947 HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_INVALID
20949 * Maximum BW allocated to CoS queue.
20950 * The HWRM will translate this value into byte counter and
20951 * time interval used for this COS inside the device.
20953 uint32_t queue_id2_max_bw;
20954 /* The bandwidth value. */
20955 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MAX_BW_BW_VALUE_MASK \
20956 UINT32_C(0xfffffff)
20957 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MAX_BW_BW_VALUE_SFT \
20959 /* The granularity of the value (bits or bytes). */
20960 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MAX_BW_SCALE \
20961 UINT32_C(0x10000000)
20962 /* Value is in bits. */
20963 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MAX_BW_SCALE_BITS \
20964 (UINT32_C(0x0) << 28)
20965 /* Value is in bytes. */
20966 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MAX_BW_SCALE_BYTES \
20967 (UINT32_C(0x1) << 28)
20968 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MAX_BW_SCALE_LAST \
20969 HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MAX_BW_SCALE_BYTES
20970 /* bw_value_unit is 3 b */
20971 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_MASK \
20972 UINT32_C(0xe0000000)
20973 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_SFT \
20975 /* Value is in Mb or MB (base 10). */
20976 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_MEGA \
20977 (UINT32_C(0x0) << 29)
20978 /* Value is in Kb or KB (base 10). */
20979 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_KILO \
20980 (UINT32_C(0x2) << 29)
20981 /* Value is in bits or bytes. */
20982 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_BASE \
20983 (UINT32_C(0x4) << 29)
20984 /* Value is in Gb or GB (base 10). */
20985 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_GIGA \
20986 (UINT32_C(0x6) << 29)
20987 /* Value is in 1/100th of a percentage of total bandwidth. */
20988 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 \
20989 (UINT32_C(0x1) << 29)
20991 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_INVALID \
20992 (UINT32_C(0x7) << 29)
20993 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_LAST \
20994 HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_INVALID
20995 /* Transmission Selection Algorithm (TSA) for CoS Queue. */
20996 uint8_t queue_id2_tsa_assign;
20997 /* Strict Priority */
20998 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_TSA_ASSIGN_SP \
21000 /* Enhanced Transmission Selection */
21001 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_TSA_ASSIGN_ETS \
21004 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_TSA_ASSIGN_RESERVED_FIRST \
21007 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_TSA_ASSIGN_RESERVED_LAST \
21010 * Priority level for strict priority. Valid only when the
21011 * tsa_assign is 0 - Strict Priority (SP)
21012 * 0..7 - Valid values.
21013 * 8..255 - Reserved.
21015 uint8_t queue_id2_pri_lvl;
21017 * Weight used to allocate remaining BW for this COS after
21018 * servicing guaranteed bandwidths for all COS.
21020 uint8_t queue_id2_bw_weight;
21021 /* ID of CoS Queue 3. */
21024 * Minimum BW allocated to CoS Queue.
21025 * The HWRM will translate this value into byte counter and
21026 * time interval used for this COS inside the device.
21028 uint32_t queue_id3_min_bw;
21029 /* The bandwidth value. */
21030 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MIN_BW_BW_VALUE_MASK \
21031 UINT32_C(0xfffffff)
21032 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MIN_BW_BW_VALUE_SFT \
21034 /* The granularity of the value (bits or bytes). */
21035 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MIN_BW_SCALE \
21036 UINT32_C(0x10000000)
21037 /* Value is in bits. */
21038 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MIN_BW_SCALE_BITS \
21039 (UINT32_C(0x0) << 28)
21040 /* Value is in bytes. */
21041 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MIN_BW_SCALE_BYTES \
21042 (UINT32_C(0x1) << 28)
21043 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MIN_BW_SCALE_LAST \
21044 HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MIN_BW_SCALE_BYTES
21045 /* bw_value_unit is 3 b */
21046 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_MASK \
21047 UINT32_C(0xe0000000)
21048 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_SFT \
21050 /* Value is in Mb or MB (base 10). */
21051 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_MEGA \
21052 (UINT32_C(0x0) << 29)
21053 /* Value is in Kb or KB (base 10). */
21054 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_KILO \
21055 (UINT32_C(0x2) << 29)
21056 /* Value is in bits or bytes. */
21057 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_BASE \
21058 (UINT32_C(0x4) << 29)
21059 /* Value is in Gb or GB (base 10). */
21060 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_GIGA \
21061 (UINT32_C(0x6) << 29)
21062 /* Value is in 1/100th of a percentage of total bandwidth. */
21063 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 \
21064 (UINT32_C(0x1) << 29)
21066 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_INVALID \
21067 (UINT32_C(0x7) << 29)
21068 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_LAST \
21069 HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_INVALID
21071 * Maximum BW allocated to CoS queue.
21072 * The HWRM will translate this value into byte counter and
21073 * time interval used for this COS inside the device.
21075 uint32_t queue_id3_max_bw;
21076 /* The bandwidth value. */
21077 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MAX_BW_BW_VALUE_MASK \
21078 UINT32_C(0xfffffff)
21079 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MAX_BW_BW_VALUE_SFT \
21081 /* The granularity of the value (bits or bytes). */
21082 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MAX_BW_SCALE \
21083 UINT32_C(0x10000000)
21084 /* Value is in bits. */
21085 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MAX_BW_SCALE_BITS \
21086 (UINT32_C(0x0) << 28)
21087 /* Value is in bytes. */
21088 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MAX_BW_SCALE_BYTES \
21089 (UINT32_C(0x1) << 28)
21090 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MAX_BW_SCALE_LAST \
21091 HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MAX_BW_SCALE_BYTES
21092 /* bw_value_unit is 3 b */
21093 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_MASK \
21094 UINT32_C(0xe0000000)
21095 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_SFT \
21097 /* Value is in Mb or MB (base 10). */
21098 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_MEGA \
21099 (UINT32_C(0x0) << 29)
21100 /* Value is in Kb or KB (base 10). */
21101 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_KILO \
21102 (UINT32_C(0x2) << 29)
21103 /* Value is in bits or bytes. */
21104 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_BASE \
21105 (UINT32_C(0x4) << 29)
21106 /* Value is in Gb or GB (base 10). */
21107 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_GIGA \
21108 (UINT32_C(0x6) << 29)
21109 /* Value is in 1/100th of a percentage of total bandwidth. */
21110 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 \
21111 (UINT32_C(0x1) << 29)
21113 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_INVALID \
21114 (UINT32_C(0x7) << 29)
21115 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_LAST \
21116 HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_INVALID
21117 /* Transmission Selection Algorithm (TSA) for CoS Queue. */
21118 uint8_t queue_id3_tsa_assign;
21119 /* Strict Priority */
21120 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_TSA_ASSIGN_SP \
21122 /* Enhanced Transmission Selection */
21123 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_TSA_ASSIGN_ETS \
21126 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_TSA_ASSIGN_RESERVED_FIRST \
21129 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_TSA_ASSIGN_RESERVED_LAST \
21132 * Priority level for strict priority. Valid only when the
21133 * tsa_assign is 0 - Strict Priority (SP)
21134 * 0..7 - Valid values.
21135 * 8..255 - Reserved.
21137 uint8_t queue_id3_pri_lvl;
21139 * Weight used to allocate remaining BW for this COS after
21140 * servicing guaranteed bandwidths for all COS.
21142 uint8_t queue_id3_bw_weight;
21143 /* ID of CoS Queue 4. */
21146 * Minimum BW allocated to CoS Queue.
21147 * The HWRM will translate this value into byte counter and
21148 * time interval used for this COS inside the device.
21150 uint32_t queue_id4_min_bw;
21151 /* The bandwidth value. */
21152 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MIN_BW_BW_VALUE_MASK \
21153 UINT32_C(0xfffffff)
21154 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MIN_BW_BW_VALUE_SFT \
21156 /* The granularity of the value (bits or bytes). */
21157 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MIN_BW_SCALE \
21158 UINT32_C(0x10000000)
21159 /* Value is in bits. */
21160 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MIN_BW_SCALE_BITS \
21161 (UINT32_C(0x0) << 28)
21162 /* Value is in bytes. */
21163 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MIN_BW_SCALE_BYTES \
21164 (UINT32_C(0x1) << 28)
21165 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MIN_BW_SCALE_LAST \
21166 HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MIN_BW_SCALE_BYTES
21167 /* bw_value_unit is 3 b */
21168 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_MASK \
21169 UINT32_C(0xe0000000)
21170 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_SFT \
21172 /* Value is in Mb or MB (base 10). */
21173 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_MEGA \
21174 (UINT32_C(0x0) << 29)
21175 /* Value is in Kb or KB (base 10). */
21176 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_KILO \
21177 (UINT32_C(0x2) << 29)
21178 /* Value is in bits or bytes. */
21179 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_BASE \
21180 (UINT32_C(0x4) << 29)
21181 /* Value is in Gb or GB (base 10). */
21182 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_GIGA \
21183 (UINT32_C(0x6) << 29)
21184 /* Value is in 1/100th of a percentage of total bandwidth. */
21185 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 \
21186 (UINT32_C(0x1) << 29)
21188 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_INVALID \
21189 (UINT32_C(0x7) << 29)
21190 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_LAST \
21191 HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_INVALID
21193 * Maximum BW allocated to CoS queue.
21194 * The HWRM will translate this value into byte counter and
21195 * time interval used for this COS inside the device.
21197 uint32_t queue_id4_max_bw;
21198 /* The bandwidth value. */
21199 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MAX_BW_BW_VALUE_MASK \
21200 UINT32_C(0xfffffff)
21201 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MAX_BW_BW_VALUE_SFT \
21203 /* The granularity of the value (bits or bytes). */
21204 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MAX_BW_SCALE \
21205 UINT32_C(0x10000000)
21206 /* Value is in bits. */
21207 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MAX_BW_SCALE_BITS \
21208 (UINT32_C(0x0) << 28)
21209 /* Value is in bytes. */
21210 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MAX_BW_SCALE_BYTES \
21211 (UINT32_C(0x1) << 28)
21212 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MAX_BW_SCALE_LAST \
21213 HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MAX_BW_SCALE_BYTES
21214 /* bw_value_unit is 3 b */
21215 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_MASK \
21216 UINT32_C(0xe0000000)
21217 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_SFT \
21219 /* Value is in Mb or MB (base 10). */
21220 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_MEGA \
21221 (UINT32_C(0x0) << 29)
21222 /* Value is in Kb or KB (base 10). */
21223 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_KILO \
21224 (UINT32_C(0x2) << 29)
21225 /* Value is in bits or bytes. */
21226 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_BASE \
21227 (UINT32_C(0x4) << 29)
21228 /* Value is in Gb or GB (base 10). */
21229 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_GIGA \
21230 (UINT32_C(0x6) << 29)
21231 /* Value is in 1/100th of a percentage of total bandwidth. */
21232 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 \
21233 (UINT32_C(0x1) << 29)
21235 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_INVALID \
21236 (UINT32_C(0x7) << 29)
21237 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_LAST \
21238 HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_INVALID
21239 /* Transmission Selection Algorithm (TSA) for CoS Queue. */
21240 uint8_t queue_id4_tsa_assign;
21241 /* Strict Priority */
21242 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_TSA_ASSIGN_SP \
21244 /* Enhanced Transmission Selection */
21245 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_TSA_ASSIGN_ETS \
21248 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_TSA_ASSIGN_RESERVED_FIRST \
21251 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_TSA_ASSIGN_RESERVED_LAST \
21254 * Priority level for strict priority. Valid only when the
21255 * tsa_assign is 0 - Strict Priority (SP)
21256 * 0..7 - Valid values.
21257 * 8..255 - Reserved.
21259 uint8_t queue_id4_pri_lvl;
21261 * Weight used to allocate remaining BW for this COS after
21262 * servicing guaranteed bandwidths for all COS.
21264 uint8_t queue_id4_bw_weight;
21265 /* ID of CoS Queue 5. */
21268 * Minimum BW allocated to CoS Queue.
21269 * The HWRM will translate this value into byte counter and
21270 * time interval used for this COS inside the device.
21272 uint32_t queue_id5_min_bw;
21273 /* The bandwidth value. */
21274 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MIN_BW_BW_VALUE_MASK \
21275 UINT32_C(0xfffffff)
21276 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MIN_BW_BW_VALUE_SFT \
21278 /* The granularity of the value (bits or bytes). */
21279 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MIN_BW_SCALE \
21280 UINT32_C(0x10000000)
21281 /* Value is in bits. */
21282 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MIN_BW_SCALE_BITS \
21283 (UINT32_C(0x0) << 28)
21284 /* Value is in bytes. */
21285 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MIN_BW_SCALE_BYTES \
21286 (UINT32_C(0x1) << 28)
21287 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MIN_BW_SCALE_LAST \
21288 HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MIN_BW_SCALE_BYTES
21289 /* bw_value_unit is 3 b */
21290 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_MASK \
21291 UINT32_C(0xe0000000)
21292 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_SFT \
21294 /* Value is in Mb or MB (base 10). */
21295 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_MEGA \
21296 (UINT32_C(0x0) << 29)
21297 /* Value is in Kb or KB (base 10). */
21298 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_KILO \
21299 (UINT32_C(0x2) << 29)
21300 /* Value is in bits or bytes. */
21301 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_BASE \
21302 (UINT32_C(0x4) << 29)
21303 /* Value is in Gb or GB (base 10). */
21304 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_GIGA \
21305 (UINT32_C(0x6) << 29)
21306 /* Value is in 1/100th of a percentage of total bandwidth. */
21307 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 \
21308 (UINT32_C(0x1) << 29)
21310 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_INVALID \
21311 (UINT32_C(0x7) << 29)
21312 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_LAST \
21313 HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_INVALID
21315 * Maximum BW allocated to CoS queue.
21316 * The HWRM will translate this value into byte counter and
21317 * time interval used for this COS inside the device.
21319 uint32_t queue_id5_max_bw;
21320 /* The bandwidth value. */
21321 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MAX_BW_BW_VALUE_MASK \
21322 UINT32_C(0xfffffff)
21323 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MAX_BW_BW_VALUE_SFT \
21325 /* The granularity of the value (bits or bytes). */
21326 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MAX_BW_SCALE \
21327 UINT32_C(0x10000000)
21328 /* Value is in bits. */
21329 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MAX_BW_SCALE_BITS \
21330 (UINT32_C(0x0) << 28)
21331 /* Value is in bytes. */
21332 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MAX_BW_SCALE_BYTES \
21333 (UINT32_C(0x1) << 28)
21334 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MAX_BW_SCALE_LAST \
21335 HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MAX_BW_SCALE_BYTES
21336 /* bw_value_unit is 3 b */
21337 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_MASK \
21338 UINT32_C(0xe0000000)
21339 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_SFT \
21341 /* Value is in Mb or MB (base 10). */
21342 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_MEGA \
21343 (UINT32_C(0x0) << 29)
21344 /* Value is in Kb or KB (base 10). */
21345 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_KILO \
21346 (UINT32_C(0x2) << 29)
21347 /* Value is in bits or bytes. */
21348 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_BASE \
21349 (UINT32_C(0x4) << 29)
21350 /* Value is in Gb or GB (base 10). */
21351 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_GIGA \
21352 (UINT32_C(0x6) << 29)
21353 /* Value is in 1/100th of a percentage of total bandwidth. */
21354 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 \
21355 (UINT32_C(0x1) << 29)
21357 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_INVALID \
21358 (UINT32_C(0x7) << 29)
21359 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_LAST \
21360 HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_INVALID
21361 /* Transmission Selection Algorithm (TSA) for CoS Queue. */
21362 uint8_t queue_id5_tsa_assign;
21363 /* Strict Priority */
21364 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_TSA_ASSIGN_SP \
21366 /* Enhanced Transmission Selection */
21367 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_TSA_ASSIGN_ETS \
21370 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_TSA_ASSIGN_RESERVED_FIRST \
21373 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_TSA_ASSIGN_RESERVED_LAST \
21376 * Priority level for strict priority. Valid only when the
21377 * tsa_assign is 0 - Strict Priority (SP)
21378 * 0..7 - Valid values.
21379 * 8..255 - Reserved.
21381 uint8_t queue_id5_pri_lvl;
21383 * Weight used to allocate remaining BW for this COS after
21384 * servicing guaranteed bandwidths for all COS.
21386 uint8_t queue_id5_bw_weight;
21387 /* ID of CoS Queue 6. */
21390 * Minimum BW allocated to CoS Queue.
21391 * The HWRM will translate this value into byte counter and
21392 * time interval used for this COS inside the device.
21394 uint32_t queue_id6_min_bw;
21395 /* The bandwidth value. */
21396 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MIN_BW_BW_VALUE_MASK \
21397 UINT32_C(0xfffffff)
21398 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MIN_BW_BW_VALUE_SFT \
21400 /* The granularity of the value (bits or bytes). */
21401 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MIN_BW_SCALE \
21402 UINT32_C(0x10000000)
21403 /* Value is in bits. */
21404 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MIN_BW_SCALE_BITS \
21405 (UINT32_C(0x0) << 28)
21406 /* Value is in bytes. */
21407 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MIN_BW_SCALE_BYTES \
21408 (UINT32_C(0x1) << 28)
21409 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MIN_BW_SCALE_LAST \
21410 HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MIN_BW_SCALE_BYTES
21411 /* bw_value_unit is 3 b */
21412 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_MASK \
21413 UINT32_C(0xe0000000)
21414 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_SFT \
21416 /* Value is in Mb or MB (base 10). */
21417 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_MEGA \
21418 (UINT32_C(0x0) << 29)
21419 /* Value is in Kb or KB (base 10). */
21420 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_KILO \
21421 (UINT32_C(0x2) << 29)
21422 /* Value is in bits or bytes. */
21423 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_BASE \
21424 (UINT32_C(0x4) << 29)
21425 /* Value is in Gb or GB (base 10). */
21426 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_GIGA \
21427 (UINT32_C(0x6) << 29)
21428 /* Value is in 1/100th of a percentage of total bandwidth. */
21429 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 \
21430 (UINT32_C(0x1) << 29)
21432 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_INVALID \
21433 (UINT32_C(0x7) << 29)
21434 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_LAST \
21435 HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_INVALID
21437 * Maximum BW allocated to CoS queue.
21438 * The HWRM will translate this value into byte counter and
21439 * time interval used for this COS inside the device.
21441 uint32_t queue_id6_max_bw;
21442 /* The bandwidth value. */
21443 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MAX_BW_BW_VALUE_MASK \
21444 UINT32_C(0xfffffff)
21445 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MAX_BW_BW_VALUE_SFT \
21447 /* The granularity of the value (bits or bytes). */
21448 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MAX_BW_SCALE \
21449 UINT32_C(0x10000000)
21450 /* Value is in bits. */
21451 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MAX_BW_SCALE_BITS \
21452 (UINT32_C(0x0) << 28)
21453 /* Value is in bytes. */
21454 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MAX_BW_SCALE_BYTES \
21455 (UINT32_C(0x1) << 28)
21456 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MAX_BW_SCALE_LAST \
21457 HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MAX_BW_SCALE_BYTES
21458 /* bw_value_unit is 3 b */
21459 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_MASK \
21460 UINT32_C(0xe0000000)
21461 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_SFT \
21463 /* Value is in Mb or MB (base 10). */
21464 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_MEGA \
21465 (UINT32_C(0x0) << 29)
21466 /* Value is in Kb or KB (base 10). */
21467 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_KILO \
21468 (UINT32_C(0x2) << 29)
21469 /* Value is in bits or bytes. */
21470 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_BASE \
21471 (UINT32_C(0x4) << 29)
21472 /* Value is in Gb or GB (base 10). */
21473 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_GIGA \
21474 (UINT32_C(0x6) << 29)
21475 /* Value is in 1/100th of a percentage of total bandwidth. */
21476 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 \
21477 (UINT32_C(0x1) << 29)
21479 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_INVALID \
21480 (UINT32_C(0x7) << 29)
21481 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_LAST \
21482 HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_INVALID
21483 /* Transmission Selection Algorithm (TSA) for CoS Queue. */
21484 uint8_t queue_id6_tsa_assign;
21485 /* Strict Priority */
21486 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_TSA_ASSIGN_SP \
21488 /* Enhanced Transmission Selection */
21489 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_TSA_ASSIGN_ETS \
21492 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_TSA_ASSIGN_RESERVED_FIRST \
21495 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_TSA_ASSIGN_RESERVED_LAST \
21498 * Priority level for strict priority. Valid only when the
21499 * tsa_assign is 0 - Strict Priority (SP)
21500 * 0..7 - Valid values.
21501 * 8..255 - Reserved.
21503 uint8_t queue_id6_pri_lvl;
21505 * Weight used to allocate remaining BW for this COS after
21506 * servicing guaranteed bandwidths for all COS.
21508 uint8_t queue_id6_bw_weight;
21509 /* ID of CoS Queue 7. */
21512 * Minimum BW allocated to CoS Queue.
21513 * The HWRM will translate this value into byte counter and
21514 * time interval used for this COS inside the device.
21516 uint32_t queue_id7_min_bw;
21517 /* The bandwidth value. */
21518 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MIN_BW_BW_VALUE_MASK \
21519 UINT32_C(0xfffffff)
21520 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MIN_BW_BW_VALUE_SFT \
21522 /* The granularity of the value (bits or bytes). */
21523 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MIN_BW_SCALE \
21524 UINT32_C(0x10000000)
21525 /* Value is in bits. */
21526 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MIN_BW_SCALE_BITS \
21527 (UINT32_C(0x0) << 28)
21528 /* Value is in bytes. */
21529 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MIN_BW_SCALE_BYTES \
21530 (UINT32_C(0x1) << 28)
21531 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MIN_BW_SCALE_LAST \
21532 HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MIN_BW_SCALE_BYTES
21533 /* bw_value_unit is 3 b */
21534 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_MASK \
21535 UINT32_C(0xe0000000)
21536 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_SFT \
21538 /* Value is in Mb or MB (base 10). */
21539 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_MEGA \
21540 (UINT32_C(0x0) << 29)
21541 /* Value is in Kb or KB (base 10). */
21542 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_KILO \
21543 (UINT32_C(0x2) << 29)
21544 /* Value is in bits or bytes. */
21545 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_BASE \
21546 (UINT32_C(0x4) << 29)
21547 /* Value is in Gb or GB (base 10). */
21548 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_GIGA \
21549 (UINT32_C(0x6) << 29)
21550 /* Value is in 1/100th of a percentage of total bandwidth. */
21551 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 \
21552 (UINT32_C(0x1) << 29)
21554 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_INVALID \
21555 (UINT32_C(0x7) << 29)
21556 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_LAST \
21557 HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_INVALID
21559 * Maximum BW allocated to CoS queue.
21560 * The HWRM will translate this value into byte counter and
21561 * time interval used for this COS inside the device.
21563 uint32_t queue_id7_max_bw;
21564 /* The bandwidth value. */
21565 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MAX_BW_BW_VALUE_MASK \
21566 UINT32_C(0xfffffff)
21567 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MAX_BW_BW_VALUE_SFT \
21569 /* The granularity of the value (bits or bytes). */
21570 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MAX_BW_SCALE \
21571 UINT32_C(0x10000000)
21572 /* Value is in bits. */
21573 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MAX_BW_SCALE_BITS \
21574 (UINT32_C(0x0) << 28)
21575 /* Value is in bytes. */
21576 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MAX_BW_SCALE_BYTES \
21577 (UINT32_C(0x1) << 28)
21578 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MAX_BW_SCALE_LAST \
21579 HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MAX_BW_SCALE_BYTES
21580 /* bw_value_unit is 3 b */
21581 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_MASK \
21582 UINT32_C(0xe0000000)
21583 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_SFT \
21585 /* Value is in Mb or MB (base 10). */
21586 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_MEGA \
21587 (UINT32_C(0x0) << 29)
21588 /* Value is in Kb or KB (base 10). */
21589 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_KILO \
21590 (UINT32_C(0x2) << 29)
21591 /* Value is in bits or bytes. */
21592 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_BASE \
21593 (UINT32_C(0x4) << 29)
21594 /* Value is in Gb or GB (base 10). */
21595 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_GIGA \
21596 (UINT32_C(0x6) << 29)
21597 /* Value is in 1/100th of a percentage of total bandwidth. */
21598 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 \
21599 (UINT32_C(0x1) << 29)
21601 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_INVALID \
21602 (UINT32_C(0x7) << 29)
21603 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_LAST \
21604 HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_INVALID
21605 /* Transmission Selection Algorithm (TSA) for CoS Queue. */
21606 uint8_t queue_id7_tsa_assign;
21607 /* Strict Priority */
21608 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_TSA_ASSIGN_SP \
21610 /* Enhanced Transmission Selection */
21611 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_TSA_ASSIGN_ETS \
21614 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_TSA_ASSIGN_RESERVED_FIRST \
21617 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_TSA_ASSIGN_RESERVED_LAST \
21620 * Priority level for strict priority. Valid only when the
21621 * tsa_assign is 0 - Strict Priority (SP)
21622 * 0..7 - Valid values.
21623 * 8..255 - Reserved.
21625 uint8_t queue_id7_pri_lvl;
21627 * Weight used to allocate remaining BW for this COS after
21628 * servicing guaranteed bandwidths for all COS.
21630 uint8_t queue_id7_bw_weight;
21631 uint8_t unused_2[4];
21633 * This field is used in Output records to indicate that the output
21634 * is completely written to RAM. This field should be read as '1'
21635 * to indicate that the output has been completely written.
21636 * When writing a command completion or response to an internal processor,
21637 * the order of writes has to be such that this field is written last.
21642 /*************************
21643 * hwrm_queue_cos2bw_cfg *
21644 *************************/
21647 /* hwrm_queue_cos2bw_cfg_input (size:1024b/128B) */
21648 struct hwrm_queue_cos2bw_cfg_input {
21649 /* The HWRM command request type. */
21652 * The completion ring to send the completion event on. This should
21653 * be the NQ ID returned from the `nq_alloc` HWRM command.
21655 uint16_t cmpl_ring;
21657 * The sequence ID is used by the driver for tracking multiple
21658 * commands. This ID is treated as opaque data by the firmware and
21659 * the value is returned in the `hwrm_resp_hdr` upon completion.
21663 * The target ID of the command:
21664 * * 0x0-0xFFF8 - The function ID
21665 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
21666 * * 0xFFFD - Reserved for user-space HWRM interface
21669 uint16_t target_id;
21671 * A physical address pointer pointing to a host buffer that the
21672 * command's response data will be written. This can be either a host
21673 * physical address (HPA) or a guest physical address (GPA) and must
21674 * point to a physically contiguous block of memory.
21676 uint64_t resp_addr;
21680 * If this bit is set to 1, then all queue_id0 related
21681 * parameters in this command are valid.
21683 #define HWRM_QUEUE_COS2BW_CFG_INPUT_ENABLES_COS_QUEUE_ID0_VALID \
21686 * If this bit is set to 1, then all queue_id1 related
21687 * parameters in this command are valid.
21689 #define HWRM_QUEUE_COS2BW_CFG_INPUT_ENABLES_COS_QUEUE_ID1_VALID \
21692 * If this bit is set to 1, then all queue_id2 related
21693 * parameters in this command are valid.
21695 #define HWRM_QUEUE_COS2BW_CFG_INPUT_ENABLES_COS_QUEUE_ID2_VALID \
21698 * If this bit is set to 1, then all queue_id3 related
21699 * parameters in this command are valid.
21701 #define HWRM_QUEUE_COS2BW_CFG_INPUT_ENABLES_COS_QUEUE_ID3_VALID \
21704 * If this bit is set to 1, then all queue_id4 related
21705 * parameters in this command are valid.
21707 #define HWRM_QUEUE_COS2BW_CFG_INPUT_ENABLES_COS_QUEUE_ID4_VALID \
21710 * If this bit is set to 1, then all queue_id5 related
21711 * parameters in this command are valid.
21713 #define HWRM_QUEUE_COS2BW_CFG_INPUT_ENABLES_COS_QUEUE_ID5_VALID \
21716 * If this bit is set to 1, then all queue_id6 related
21717 * parameters in this command are valid.
21719 #define HWRM_QUEUE_COS2BW_CFG_INPUT_ENABLES_COS_QUEUE_ID6_VALID \
21722 * If this bit is set to 1, then all queue_id7 related
21723 * parameters in this command are valid.
21725 #define HWRM_QUEUE_COS2BW_CFG_INPUT_ENABLES_COS_QUEUE_ID7_VALID \
21728 * Port ID of port for which the table is being configured.
21729 * The HWRM needs to check whether this function is allowed
21730 * to configure TC BW assignment on this port.
21733 /* ID of CoS Queue 0. */
21737 * Minimum BW allocated to CoS Queue.
21738 * The HWRM will translate this value into byte counter and
21739 * time interval used for this COS inside the device.
21741 uint32_t queue_id0_min_bw;
21742 /* The bandwidth value. */
21743 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MIN_BW_BW_VALUE_MASK \
21744 UINT32_C(0xfffffff)
21745 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MIN_BW_BW_VALUE_SFT \
21747 /* The granularity of the value (bits or bytes). */
21748 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MIN_BW_SCALE \
21749 UINT32_C(0x10000000)
21750 /* Value is in bits. */
21751 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MIN_BW_SCALE_BITS \
21752 (UINT32_C(0x0) << 28)
21753 /* Value is in bytes. */
21754 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MIN_BW_SCALE_BYTES \
21755 (UINT32_C(0x1) << 28)
21756 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MIN_BW_SCALE_LAST \
21757 HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MIN_BW_SCALE_BYTES
21758 /* bw_value_unit is 3 b */
21759 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_MASK \
21760 UINT32_C(0xe0000000)
21761 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_SFT \
21763 /* Value is in Mb or MB (base 10). */
21764 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_MEGA \
21765 (UINT32_C(0x0) << 29)
21766 /* Value is in Kb or KB (base 10). */
21767 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_KILO \
21768 (UINT32_C(0x2) << 29)
21769 /* Value is in bits or bytes. */
21770 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_BASE \
21771 (UINT32_C(0x4) << 29)
21772 /* Value is in Gb or GB (base 10). */
21773 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_GIGA \
21774 (UINT32_C(0x6) << 29)
21775 /* Value is in 1/100th of a percentage of total bandwidth. */
21776 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 \
21777 (UINT32_C(0x1) << 29)
21779 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_INVALID \
21780 (UINT32_C(0x7) << 29)
21781 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_LAST \
21782 HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_INVALID
21784 * Maximum BW allocated to CoS Queue.
21785 * The HWRM will translate this value into byte counter and
21786 * time interval used for this COS inside the device.
21788 uint32_t queue_id0_max_bw;
21789 /* The bandwidth value. */
21790 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MAX_BW_BW_VALUE_MASK \
21791 UINT32_C(0xfffffff)
21792 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MAX_BW_BW_VALUE_SFT \
21794 /* The granularity of the value (bits or bytes). */
21795 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MAX_BW_SCALE \
21796 UINT32_C(0x10000000)
21797 /* Value is in bits. */
21798 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MAX_BW_SCALE_BITS \
21799 (UINT32_C(0x0) << 28)
21800 /* Value is in bytes. */
21801 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MAX_BW_SCALE_BYTES \
21802 (UINT32_C(0x1) << 28)
21803 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MAX_BW_SCALE_LAST \
21804 HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MAX_BW_SCALE_BYTES
21805 /* bw_value_unit is 3 b */
21806 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_MASK \
21807 UINT32_C(0xe0000000)
21808 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_SFT \
21810 /* Value is in Mb or MB (base 10). */
21811 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_MEGA \
21812 (UINT32_C(0x0) << 29)
21813 /* Value is in Kb or KB (base 10). */
21814 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_KILO \
21815 (UINT32_C(0x2) << 29)
21816 /* Value is in bits or bytes. */
21817 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_BASE \
21818 (UINT32_C(0x4) << 29)
21819 /* Value is in Gb or GB (base 10). */
21820 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_GIGA \
21821 (UINT32_C(0x6) << 29)
21822 /* Value is in 1/100th of a percentage of total bandwidth. */
21823 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 \
21824 (UINT32_C(0x1) << 29)
21826 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_INVALID \
21827 (UINT32_C(0x7) << 29)
21828 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_LAST \
21829 HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_INVALID
21830 /* Transmission Selection Algorithm (TSA) for CoS Queue. */
21831 uint8_t queue_id0_tsa_assign;
21832 /* Strict Priority */
21833 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_TSA_ASSIGN_SP \
21835 /* Enhanced Transmission Selection */
21836 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_TSA_ASSIGN_ETS \
21839 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_TSA_ASSIGN_RESERVED_FIRST \
21842 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_TSA_ASSIGN_RESERVED_LAST \
21845 * Priority level for strict priority. Valid only when the
21846 * tsa_assign is 0 - Strict Priority (SP)
21847 * 0..7 - Valid values.
21848 * 8..255 - Reserved.
21850 uint8_t queue_id0_pri_lvl;
21852 * Weight used to allocate remaining BW for this COS after
21853 * servicing guaranteed bandwidths for all COS.
21855 uint8_t queue_id0_bw_weight;
21856 /* ID of CoS Queue 1. */
21859 * Minimum BW allocated to CoS Queue.
21860 * The HWRM will translate this value into byte counter and
21861 * time interval used for this COS inside the device.
21863 uint32_t queue_id1_min_bw;
21864 /* The bandwidth value. */
21865 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MIN_BW_BW_VALUE_MASK \
21866 UINT32_C(0xfffffff)
21867 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MIN_BW_BW_VALUE_SFT \
21869 /* The granularity of the value (bits or bytes). */
21870 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MIN_BW_SCALE \
21871 UINT32_C(0x10000000)
21872 /* Value is in bits. */
21873 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MIN_BW_SCALE_BITS \
21874 (UINT32_C(0x0) << 28)
21875 /* Value is in bytes. */
21876 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MIN_BW_SCALE_BYTES \
21877 (UINT32_C(0x1) << 28)
21878 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MIN_BW_SCALE_LAST \
21879 HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MIN_BW_SCALE_BYTES
21880 /* bw_value_unit is 3 b */
21881 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_MASK \
21882 UINT32_C(0xe0000000)
21883 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_SFT \
21885 /* Value is in Mb or MB (base 10). */
21886 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_MEGA \
21887 (UINT32_C(0x0) << 29)
21888 /* Value is in Kb or KB (base 10). */
21889 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_KILO \
21890 (UINT32_C(0x2) << 29)
21891 /* Value is in bits or bytes. */
21892 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_BASE \
21893 (UINT32_C(0x4) << 29)
21894 /* Value is in Gb or GB (base 10). */
21895 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_GIGA \
21896 (UINT32_C(0x6) << 29)
21897 /* Value is in 1/100th of a percentage of total bandwidth. */
21898 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 \
21899 (UINT32_C(0x1) << 29)
21901 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_INVALID \
21902 (UINT32_C(0x7) << 29)
21903 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_LAST \
21904 HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_INVALID
21906 * Maximum BW allocated to CoS queue.
21907 * The HWRM will translate this value into byte counter and
21908 * time interval used for this COS inside the device.
21910 uint32_t queue_id1_max_bw;
21911 /* The bandwidth value. */
21912 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MAX_BW_BW_VALUE_MASK \
21913 UINT32_C(0xfffffff)
21914 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MAX_BW_BW_VALUE_SFT \
21916 /* The granularity of the value (bits or bytes). */
21917 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MAX_BW_SCALE \
21918 UINT32_C(0x10000000)
21919 /* Value is in bits. */
21920 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MAX_BW_SCALE_BITS \
21921 (UINT32_C(0x0) << 28)
21922 /* Value is in bytes. */
21923 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MAX_BW_SCALE_BYTES \
21924 (UINT32_C(0x1) << 28)
21925 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MAX_BW_SCALE_LAST \
21926 HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MAX_BW_SCALE_BYTES
21927 /* bw_value_unit is 3 b */
21928 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_MASK \
21929 UINT32_C(0xe0000000)
21930 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_SFT \
21932 /* Value is in Mb or MB (base 10). */
21933 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_MEGA \
21934 (UINT32_C(0x0) << 29)
21935 /* Value is in Kb or KB (base 10). */
21936 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_KILO \
21937 (UINT32_C(0x2) << 29)
21938 /* Value is in bits or bytes. */
21939 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_BASE \
21940 (UINT32_C(0x4) << 29)
21941 /* Value is in Gb or GB (base 10). */
21942 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_GIGA \
21943 (UINT32_C(0x6) << 29)
21944 /* Value is in 1/100th of a percentage of total bandwidth. */
21945 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 \
21946 (UINT32_C(0x1) << 29)
21948 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_INVALID \
21949 (UINT32_C(0x7) << 29)
21950 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_LAST \
21951 HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_INVALID
21952 /* Transmission Selection Algorithm (TSA) for CoS Queue. */
21953 uint8_t queue_id1_tsa_assign;
21954 /* Strict Priority */
21955 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_TSA_ASSIGN_SP \
21957 /* Enhanced Transmission Selection */
21958 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_TSA_ASSIGN_ETS \
21961 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_TSA_ASSIGN_RESERVED_FIRST \
21964 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_TSA_ASSIGN_RESERVED_LAST \
21967 * Priority level for strict priority. Valid only when the
21968 * tsa_assign is 0 - Strict Priority (SP)
21969 * 0..7 - Valid values.
21970 * 8..255 - Reserved.
21972 uint8_t queue_id1_pri_lvl;
21974 * Weight used to allocate remaining BW for this COS after
21975 * servicing guaranteed bandwidths for all COS.
21977 uint8_t queue_id1_bw_weight;
21978 /* ID of CoS Queue 2. */
21981 * Minimum BW allocated to CoS Queue.
21982 * The HWRM will translate this value into byte counter and
21983 * time interval used for this COS inside the device.
21985 uint32_t queue_id2_min_bw;
21986 /* The bandwidth value. */
21987 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MIN_BW_BW_VALUE_MASK \
21988 UINT32_C(0xfffffff)
21989 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MIN_BW_BW_VALUE_SFT \
21991 /* The granularity of the value (bits or bytes). */
21992 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MIN_BW_SCALE \
21993 UINT32_C(0x10000000)
21994 /* Value is in bits. */
21995 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MIN_BW_SCALE_BITS \
21996 (UINT32_C(0x0) << 28)
21997 /* Value is in bytes. */
21998 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MIN_BW_SCALE_BYTES \
21999 (UINT32_C(0x1) << 28)
22000 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MIN_BW_SCALE_LAST \
22001 HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MIN_BW_SCALE_BYTES
22002 /* bw_value_unit is 3 b */
22003 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_MASK \
22004 UINT32_C(0xe0000000)
22005 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_SFT \
22007 /* Value is in Mb or MB (base 10). */
22008 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_MEGA \
22009 (UINT32_C(0x0) << 29)
22010 /* Value is in Kb or KB (base 10). */
22011 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_KILO \
22012 (UINT32_C(0x2) << 29)
22013 /* Value is in bits or bytes. */
22014 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_BASE \
22015 (UINT32_C(0x4) << 29)
22016 /* Value is in Gb or GB (base 10). */
22017 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_GIGA \
22018 (UINT32_C(0x6) << 29)
22019 /* Value is in 1/100th of a percentage of total bandwidth. */
22020 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 \
22021 (UINT32_C(0x1) << 29)
22023 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_INVALID \
22024 (UINT32_C(0x7) << 29)
22025 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_LAST \
22026 HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_INVALID
22028 * Maximum BW allocated to CoS queue.
22029 * The HWRM will translate this value into byte counter and
22030 * time interval used for this COS inside the device.
22032 uint32_t queue_id2_max_bw;
22033 /* The bandwidth value. */
22034 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MAX_BW_BW_VALUE_MASK \
22035 UINT32_C(0xfffffff)
22036 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MAX_BW_BW_VALUE_SFT \
22038 /* The granularity of the value (bits or bytes). */
22039 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MAX_BW_SCALE \
22040 UINT32_C(0x10000000)
22041 /* Value is in bits. */
22042 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MAX_BW_SCALE_BITS \
22043 (UINT32_C(0x0) << 28)
22044 /* Value is in bytes. */
22045 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MAX_BW_SCALE_BYTES \
22046 (UINT32_C(0x1) << 28)
22047 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MAX_BW_SCALE_LAST \
22048 HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MAX_BW_SCALE_BYTES
22049 /* bw_value_unit is 3 b */
22050 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_MASK \
22051 UINT32_C(0xe0000000)
22052 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_SFT \
22054 /* Value is in Mb or MB (base 10). */
22055 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_MEGA \
22056 (UINT32_C(0x0) << 29)
22057 /* Value is in Kb or KB (base 10). */
22058 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_KILO \
22059 (UINT32_C(0x2) << 29)
22060 /* Value is in bits or bytes. */
22061 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_BASE \
22062 (UINT32_C(0x4) << 29)
22063 /* Value is in Gb or GB (base 10). */
22064 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_GIGA \
22065 (UINT32_C(0x6) << 29)
22066 /* Value is in 1/100th of a percentage of total bandwidth. */
22067 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 \
22068 (UINT32_C(0x1) << 29)
22070 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_INVALID \
22071 (UINT32_C(0x7) << 29)
22072 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_LAST \
22073 HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_INVALID
22074 /* Transmission Selection Algorithm (TSA) for CoS Queue. */
22075 uint8_t queue_id2_tsa_assign;
22076 /* Strict Priority */
22077 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_TSA_ASSIGN_SP \
22079 /* Enhanced Transmission Selection */
22080 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_TSA_ASSIGN_ETS \
22083 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_TSA_ASSIGN_RESERVED_FIRST \
22086 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_TSA_ASSIGN_RESERVED_LAST \
22089 * Priority level for strict priority. Valid only when the
22090 * tsa_assign is 0 - Strict Priority (SP)
22091 * 0..7 - Valid values.
22092 * 8..255 - Reserved.
22094 uint8_t queue_id2_pri_lvl;
22096 * Weight used to allocate remaining BW for this COS after
22097 * servicing guaranteed bandwidths for all COS.
22099 uint8_t queue_id2_bw_weight;
22100 /* ID of CoS Queue 3. */
22103 * Minimum BW allocated to CoS Queue.
22104 * The HWRM will translate this value into byte counter and
22105 * time interval used for this COS inside the device.
22107 uint32_t queue_id3_min_bw;
22108 /* The bandwidth value. */
22109 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MIN_BW_BW_VALUE_MASK \
22110 UINT32_C(0xfffffff)
22111 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MIN_BW_BW_VALUE_SFT \
22113 /* The granularity of the value (bits or bytes). */
22114 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MIN_BW_SCALE \
22115 UINT32_C(0x10000000)
22116 /* Value is in bits. */
22117 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MIN_BW_SCALE_BITS \
22118 (UINT32_C(0x0) << 28)
22119 /* Value is in bytes. */
22120 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MIN_BW_SCALE_BYTES \
22121 (UINT32_C(0x1) << 28)
22122 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MIN_BW_SCALE_LAST \
22123 HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MIN_BW_SCALE_BYTES
22124 /* bw_value_unit is 3 b */
22125 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_MASK \
22126 UINT32_C(0xe0000000)
22127 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_SFT \
22129 /* Value is in Mb or MB (base 10). */
22130 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_MEGA \
22131 (UINT32_C(0x0) << 29)
22132 /* Value is in Kb or KB (base 10). */
22133 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_KILO \
22134 (UINT32_C(0x2) << 29)
22135 /* Value is in bits or bytes. */
22136 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_BASE \
22137 (UINT32_C(0x4) << 29)
22138 /* Value is in Gb or GB (base 10). */
22139 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_GIGA \
22140 (UINT32_C(0x6) << 29)
22141 /* Value is in 1/100th of a percentage of total bandwidth. */
22142 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 \
22143 (UINT32_C(0x1) << 29)
22145 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_INVALID \
22146 (UINT32_C(0x7) << 29)
22147 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_LAST \
22148 HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_INVALID
22150 * Maximum BW allocated to CoS queue.
22151 * The HWRM will translate this value into byte counter and
22152 * time interval used for this COS inside the device.
22154 uint32_t queue_id3_max_bw;
22155 /* The bandwidth value. */
22156 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MAX_BW_BW_VALUE_MASK \
22157 UINT32_C(0xfffffff)
22158 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MAX_BW_BW_VALUE_SFT \
22160 /* The granularity of the value (bits or bytes). */
22161 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MAX_BW_SCALE \
22162 UINT32_C(0x10000000)
22163 /* Value is in bits. */
22164 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MAX_BW_SCALE_BITS \
22165 (UINT32_C(0x0) << 28)
22166 /* Value is in bytes. */
22167 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MAX_BW_SCALE_BYTES \
22168 (UINT32_C(0x1) << 28)
22169 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MAX_BW_SCALE_LAST \
22170 HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MAX_BW_SCALE_BYTES
22171 /* bw_value_unit is 3 b */
22172 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_MASK \
22173 UINT32_C(0xe0000000)
22174 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_SFT \
22176 /* Value is in Mb or MB (base 10). */
22177 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_MEGA \
22178 (UINT32_C(0x0) << 29)
22179 /* Value is in Kb or KB (base 10). */
22180 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_KILO \
22181 (UINT32_C(0x2) << 29)
22182 /* Value is in bits or bytes. */
22183 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_BASE \
22184 (UINT32_C(0x4) << 29)
22185 /* Value is in Gb or GB (base 10). */
22186 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_GIGA \
22187 (UINT32_C(0x6) << 29)
22188 /* Value is in 1/100th of a percentage of total bandwidth. */
22189 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 \
22190 (UINT32_C(0x1) << 29)
22192 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_INVALID \
22193 (UINT32_C(0x7) << 29)
22194 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_LAST \
22195 HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_INVALID
22196 /* Transmission Selection Algorithm (TSA) for CoS Queue. */
22197 uint8_t queue_id3_tsa_assign;
22198 /* Strict Priority */
22199 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_TSA_ASSIGN_SP \
22201 /* Enhanced Transmission Selection */
22202 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_TSA_ASSIGN_ETS \
22205 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_TSA_ASSIGN_RESERVED_FIRST \
22208 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_TSA_ASSIGN_RESERVED_LAST \
22211 * Priority level for strict priority. Valid only when the
22212 * tsa_assign is 0 - Strict Priority (SP)
22213 * 0..7 - Valid values.
22214 * 8..255 - Reserved.
22216 uint8_t queue_id3_pri_lvl;
22218 * Weight used to allocate remaining BW for this COS after
22219 * servicing guaranteed bandwidths for all COS.
22221 uint8_t queue_id3_bw_weight;
22222 /* ID of CoS Queue 4. */
22225 * Minimum BW allocated to CoS Queue.
22226 * The HWRM will translate this value into byte counter and
22227 * time interval used for this COS inside the device.
22229 uint32_t queue_id4_min_bw;
22230 /* The bandwidth value. */
22231 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MIN_BW_BW_VALUE_MASK \
22232 UINT32_C(0xfffffff)
22233 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MIN_BW_BW_VALUE_SFT \
22235 /* The granularity of the value (bits or bytes). */
22236 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MIN_BW_SCALE \
22237 UINT32_C(0x10000000)
22238 /* Value is in bits. */
22239 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MIN_BW_SCALE_BITS \
22240 (UINT32_C(0x0) << 28)
22241 /* Value is in bytes. */
22242 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MIN_BW_SCALE_BYTES \
22243 (UINT32_C(0x1) << 28)
22244 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MIN_BW_SCALE_LAST \
22245 HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MIN_BW_SCALE_BYTES
22246 /* bw_value_unit is 3 b */
22247 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_MASK \
22248 UINT32_C(0xe0000000)
22249 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_SFT \
22251 /* Value is in Mb or MB (base 10). */
22252 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_MEGA \
22253 (UINT32_C(0x0) << 29)
22254 /* Value is in Kb or KB (base 10). */
22255 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_KILO \
22256 (UINT32_C(0x2) << 29)
22257 /* Value is in bits or bytes. */
22258 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_BASE \
22259 (UINT32_C(0x4) << 29)
22260 /* Value is in Gb or GB (base 10). */
22261 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_GIGA \
22262 (UINT32_C(0x6) << 29)
22263 /* Value is in 1/100th of a percentage of total bandwidth. */
22264 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 \
22265 (UINT32_C(0x1) << 29)
22267 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_INVALID \
22268 (UINT32_C(0x7) << 29)
22269 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_LAST \
22270 HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_INVALID
22272 * Maximum BW allocated to CoS queue.
22273 * The HWRM will translate this value into byte counter and
22274 * time interval used for this COS inside the device.
22276 uint32_t queue_id4_max_bw;
22277 /* The bandwidth value. */
22278 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MAX_BW_BW_VALUE_MASK \
22279 UINT32_C(0xfffffff)
22280 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MAX_BW_BW_VALUE_SFT \
22282 /* The granularity of the value (bits or bytes). */
22283 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MAX_BW_SCALE \
22284 UINT32_C(0x10000000)
22285 /* Value is in bits. */
22286 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MAX_BW_SCALE_BITS \
22287 (UINT32_C(0x0) << 28)
22288 /* Value is in bytes. */
22289 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MAX_BW_SCALE_BYTES \
22290 (UINT32_C(0x1) << 28)
22291 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MAX_BW_SCALE_LAST \
22292 HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MAX_BW_SCALE_BYTES
22293 /* bw_value_unit is 3 b */
22294 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_MASK \
22295 UINT32_C(0xe0000000)
22296 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_SFT \
22298 /* Value is in Mb or MB (base 10). */
22299 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_MEGA \
22300 (UINT32_C(0x0) << 29)
22301 /* Value is in Kb or KB (base 10). */
22302 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_KILO \
22303 (UINT32_C(0x2) << 29)
22304 /* Value is in bits or bytes. */
22305 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_BASE \
22306 (UINT32_C(0x4) << 29)
22307 /* Value is in Gb or GB (base 10). */
22308 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_GIGA \
22309 (UINT32_C(0x6) << 29)
22310 /* Value is in 1/100th of a percentage of total bandwidth. */
22311 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 \
22312 (UINT32_C(0x1) << 29)
22314 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_INVALID \
22315 (UINT32_C(0x7) << 29)
22316 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_LAST \
22317 HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_INVALID
22318 /* Transmission Selection Algorithm (TSA) for CoS Queue. */
22319 uint8_t queue_id4_tsa_assign;
22320 /* Strict Priority */
22321 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_TSA_ASSIGN_SP \
22323 /* Enhanced Transmission Selection */
22324 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_TSA_ASSIGN_ETS \
22327 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_TSA_ASSIGN_RESERVED_FIRST \
22330 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_TSA_ASSIGN_RESERVED_LAST \
22333 * Priority level for strict priority. Valid only when the
22334 * tsa_assign is 0 - Strict Priority (SP)
22335 * 0..7 - Valid values.
22336 * 8..255 - Reserved.
22338 uint8_t queue_id4_pri_lvl;
22340 * Weight used to allocate remaining BW for this COS after
22341 * servicing guaranteed bandwidths for all COS.
22343 uint8_t queue_id4_bw_weight;
22344 /* ID of CoS Queue 5. */
22347 * Minimum BW allocated to CoS Queue.
22348 * The HWRM will translate this value into byte counter and
22349 * time interval used for this COS inside the device.
22351 uint32_t queue_id5_min_bw;
22352 /* The bandwidth value. */
22353 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MIN_BW_BW_VALUE_MASK \
22354 UINT32_C(0xfffffff)
22355 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MIN_BW_BW_VALUE_SFT \
22357 /* The granularity of the value (bits or bytes). */
22358 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MIN_BW_SCALE \
22359 UINT32_C(0x10000000)
22360 /* Value is in bits. */
22361 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MIN_BW_SCALE_BITS \
22362 (UINT32_C(0x0) << 28)
22363 /* Value is in bytes. */
22364 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MIN_BW_SCALE_BYTES \
22365 (UINT32_C(0x1) << 28)
22366 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MIN_BW_SCALE_LAST \
22367 HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MIN_BW_SCALE_BYTES
22368 /* bw_value_unit is 3 b */
22369 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_MASK \
22370 UINT32_C(0xe0000000)
22371 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_SFT \
22373 /* Value is in Mb or MB (base 10). */
22374 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_MEGA \
22375 (UINT32_C(0x0) << 29)
22376 /* Value is in Kb or KB (base 10). */
22377 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_KILO \
22378 (UINT32_C(0x2) << 29)
22379 /* Value is in bits or bytes. */
22380 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_BASE \
22381 (UINT32_C(0x4) << 29)
22382 /* Value is in Gb or GB (base 10). */
22383 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_GIGA \
22384 (UINT32_C(0x6) << 29)
22385 /* Value is in 1/100th of a percentage of total bandwidth. */
22386 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 \
22387 (UINT32_C(0x1) << 29)
22389 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_INVALID \
22390 (UINT32_C(0x7) << 29)
22391 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_LAST \
22392 HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_INVALID
22394 * Maximum BW allocated to CoS queue.
22395 * The HWRM will translate this value into byte counter and
22396 * time interval used for this COS inside the device.
22398 uint32_t queue_id5_max_bw;
22399 /* The bandwidth value. */
22400 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MAX_BW_BW_VALUE_MASK \
22401 UINT32_C(0xfffffff)
22402 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MAX_BW_BW_VALUE_SFT \
22404 /* The granularity of the value (bits or bytes). */
22405 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MAX_BW_SCALE \
22406 UINT32_C(0x10000000)
22407 /* Value is in bits. */
22408 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MAX_BW_SCALE_BITS \
22409 (UINT32_C(0x0) << 28)
22410 /* Value is in bytes. */
22411 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MAX_BW_SCALE_BYTES \
22412 (UINT32_C(0x1) << 28)
22413 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MAX_BW_SCALE_LAST \
22414 HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MAX_BW_SCALE_BYTES
22415 /* bw_value_unit is 3 b */
22416 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_MASK \
22417 UINT32_C(0xe0000000)
22418 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_SFT \
22420 /* Value is in Mb or MB (base 10). */
22421 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_MEGA \
22422 (UINT32_C(0x0) << 29)
22423 /* Value is in Kb or KB (base 10). */
22424 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_KILO \
22425 (UINT32_C(0x2) << 29)
22426 /* Value is in bits or bytes. */
22427 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_BASE \
22428 (UINT32_C(0x4) << 29)
22429 /* Value is in Gb or GB (base 10). */
22430 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_GIGA \
22431 (UINT32_C(0x6) << 29)
22432 /* Value is in 1/100th of a percentage of total bandwidth. */
22433 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 \
22434 (UINT32_C(0x1) << 29)
22436 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_INVALID \
22437 (UINT32_C(0x7) << 29)
22438 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_LAST \
22439 HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_INVALID
22440 /* Transmission Selection Algorithm (TSA) for CoS Queue. */
22441 uint8_t queue_id5_tsa_assign;
22442 /* Strict Priority */
22443 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_TSA_ASSIGN_SP \
22445 /* Enhanced Transmission Selection */
22446 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_TSA_ASSIGN_ETS \
22449 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_TSA_ASSIGN_RESERVED_FIRST \
22452 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_TSA_ASSIGN_RESERVED_LAST \
22455 * Priority level for strict priority. Valid only when the
22456 * tsa_assign is 0 - Strict Priority (SP)
22457 * 0..7 - Valid values.
22458 * 8..255 - Reserved.
22460 uint8_t queue_id5_pri_lvl;
22462 * Weight used to allocate remaining BW for this COS after
22463 * servicing guaranteed bandwidths for all COS.
22465 uint8_t queue_id5_bw_weight;
22466 /* ID of CoS Queue 6. */
22469 * Minimum BW allocated to CoS Queue.
22470 * The HWRM will translate this value into byte counter and
22471 * time interval used for this COS inside the device.
22473 uint32_t queue_id6_min_bw;
22474 /* The bandwidth value. */
22475 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MIN_BW_BW_VALUE_MASK \
22476 UINT32_C(0xfffffff)
22477 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MIN_BW_BW_VALUE_SFT \
22479 /* The granularity of the value (bits or bytes). */
22480 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MIN_BW_SCALE \
22481 UINT32_C(0x10000000)
22482 /* Value is in bits. */
22483 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MIN_BW_SCALE_BITS \
22484 (UINT32_C(0x0) << 28)
22485 /* Value is in bytes. */
22486 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MIN_BW_SCALE_BYTES \
22487 (UINT32_C(0x1) << 28)
22488 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MIN_BW_SCALE_LAST \
22489 HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MIN_BW_SCALE_BYTES
22490 /* bw_value_unit is 3 b */
22491 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_MASK \
22492 UINT32_C(0xe0000000)
22493 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_SFT \
22495 /* Value is in Mb or MB (base 10). */
22496 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_MEGA \
22497 (UINT32_C(0x0) << 29)
22498 /* Value is in Kb or KB (base 10). */
22499 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_KILO \
22500 (UINT32_C(0x2) << 29)
22501 /* Value is in bits or bytes. */
22502 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_BASE \
22503 (UINT32_C(0x4) << 29)
22504 /* Value is in Gb or GB (base 10). */
22505 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_GIGA \
22506 (UINT32_C(0x6) << 29)
22507 /* Value is in 1/100th of a percentage of total bandwidth. */
22508 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 \
22509 (UINT32_C(0x1) << 29)
22511 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_INVALID \
22512 (UINT32_C(0x7) << 29)
22513 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_LAST \
22514 HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_INVALID
22516 * Maximum BW allocated to CoS queue.
22517 * The HWRM will translate this value into byte counter and
22518 * time interval used for this COS inside the device.
22520 uint32_t queue_id6_max_bw;
22521 /* The bandwidth value. */
22522 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MAX_BW_BW_VALUE_MASK \
22523 UINT32_C(0xfffffff)
22524 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MAX_BW_BW_VALUE_SFT \
22526 /* The granularity of the value (bits or bytes). */
22527 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MAX_BW_SCALE \
22528 UINT32_C(0x10000000)
22529 /* Value is in bits. */
22530 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MAX_BW_SCALE_BITS \
22531 (UINT32_C(0x0) << 28)
22532 /* Value is in bytes. */
22533 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MAX_BW_SCALE_BYTES \
22534 (UINT32_C(0x1) << 28)
22535 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MAX_BW_SCALE_LAST \
22536 HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MAX_BW_SCALE_BYTES
22537 /* bw_value_unit is 3 b */
22538 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_MASK \
22539 UINT32_C(0xe0000000)
22540 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_SFT \
22542 /* Value is in Mb or MB (base 10). */
22543 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_MEGA \
22544 (UINT32_C(0x0) << 29)
22545 /* Value is in Kb or KB (base 10). */
22546 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_KILO \
22547 (UINT32_C(0x2) << 29)
22548 /* Value is in bits or bytes. */
22549 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_BASE \
22550 (UINT32_C(0x4) << 29)
22551 /* Value is in Gb or GB (base 10). */
22552 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_GIGA \
22553 (UINT32_C(0x6) << 29)
22554 /* Value is in 1/100th of a percentage of total bandwidth. */
22555 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 \
22556 (UINT32_C(0x1) << 29)
22558 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_INVALID \
22559 (UINT32_C(0x7) << 29)
22560 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_LAST \
22561 HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_INVALID
22562 /* Transmission Selection Algorithm (TSA) for CoS Queue. */
22563 uint8_t queue_id6_tsa_assign;
22564 /* Strict Priority */
22565 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_TSA_ASSIGN_SP \
22567 /* Enhanced Transmission Selection */
22568 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_TSA_ASSIGN_ETS \
22571 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_TSA_ASSIGN_RESERVED_FIRST \
22574 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_TSA_ASSIGN_RESERVED_LAST \
22577 * Priority level for strict priority. Valid only when the
22578 * tsa_assign is 0 - Strict Priority (SP)
22579 * 0..7 - Valid values.
22580 * 8..255 - Reserved.
22582 uint8_t queue_id6_pri_lvl;
22584 * Weight used to allocate remaining BW for this COS after
22585 * servicing guaranteed bandwidths for all COS.
22587 uint8_t queue_id6_bw_weight;
22588 /* ID of CoS Queue 7. */
22591 * Minimum BW allocated to CoS Queue.
22592 * The HWRM will translate this value into byte counter and
22593 * time interval used for this COS inside the device.
22595 uint32_t queue_id7_min_bw;
22596 /* The bandwidth value. */
22597 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MIN_BW_BW_VALUE_MASK \
22598 UINT32_C(0xfffffff)
22599 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MIN_BW_BW_VALUE_SFT \
22601 /* The granularity of the value (bits or bytes). */
22602 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MIN_BW_SCALE \
22603 UINT32_C(0x10000000)
22604 /* Value is in bits. */
22605 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MIN_BW_SCALE_BITS \
22606 (UINT32_C(0x0) << 28)
22607 /* Value is in bytes. */
22608 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MIN_BW_SCALE_BYTES \
22609 (UINT32_C(0x1) << 28)
22610 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MIN_BW_SCALE_LAST \
22611 HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MIN_BW_SCALE_BYTES
22612 /* bw_value_unit is 3 b */
22613 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_MASK \
22614 UINT32_C(0xe0000000)
22615 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_SFT \
22617 /* Value is in Mb or MB (base 10). */
22618 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_MEGA \
22619 (UINT32_C(0x0) << 29)
22620 /* Value is in Kb or KB (base 10). */
22621 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_KILO \
22622 (UINT32_C(0x2) << 29)
22623 /* Value is in bits or bytes. */
22624 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_BASE \
22625 (UINT32_C(0x4) << 29)
22626 /* Value is in Gb or GB (base 10). */
22627 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_GIGA \
22628 (UINT32_C(0x6) << 29)
22629 /* Value is in 1/100th of a percentage of total bandwidth. */
22630 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 \
22631 (UINT32_C(0x1) << 29)
22633 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_INVALID \
22634 (UINT32_C(0x7) << 29)
22635 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_LAST \
22636 HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_INVALID
22638 * Maximum BW allocated to CoS queue.
22639 * The HWRM will translate this value into byte counter and
22640 * time interval used for this COS inside the device.
22642 uint32_t queue_id7_max_bw;
22643 /* The bandwidth value. */
22644 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MAX_BW_BW_VALUE_MASK \
22645 UINT32_C(0xfffffff)
22646 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MAX_BW_BW_VALUE_SFT \
22648 /* The granularity of the value (bits or bytes). */
22649 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MAX_BW_SCALE \
22650 UINT32_C(0x10000000)
22651 /* Value is in bits. */
22652 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MAX_BW_SCALE_BITS \
22653 (UINT32_C(0x0) << 28)
22654 /* Value is in bytes. */
22655 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MAX_BW_SCALE_BYTES \
22656 (UINT32_C(0x1) << 28)
22657 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MAX_BW_SCALE_LAST \
22658 HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MAX_BW_SCALE_BYTES
22659 /* bw_value_unit is 3 b */
22660 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_MASK \
22661 UINT32_C(0xe0000000)
22662 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_SFT \
22664 /* Value is in Mb or MB (base 10). */
22665 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_MEGA \
22666 (UINT32_C(0x0) << 29)
22667 /* Value is in Kb or KB (base 10). */
22668 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_KILO \
22669 (UINT32_C(0x2) << 29)
22670 /* Value is in bits or bytes. */
22671 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_BASE \
22672 (UINT32_C(0x4) << 29)
22673 /* Value is in Gb or GB (base 10). */
22674 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_GIGA \
22675 (UINT32_C(0x6) << 29)
22676 /* Value is in 1/100th of a percentage of total bandwidth. */
22677 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 \
22678 (UINT32_C(0x1) << 29)
22680 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_INVALID \
22681 (UINT32_C(0x7) << 29)
22682 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_LAST \
22683 HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_INVALID
22684 /* Transmission Selection Algorithm (TSA) for CoS Queue. */
22685 uint8_t queue_id7_tsa_assign;
22686 /* Strict Priority */
22687 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_TSA_ASSIGN_SP \
22689 /* Enhanced Transmission Selection */
22690 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_TSA_ASSIGN_ETS \
22693 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_TSA_ASSIGN_RESERVED_FIRST \
22696 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_TSA_ASSIGN_RESERVED_LAST \
22699 * Priority level for strict priority. Valid only when the
22700 * tsa_assign is 0 - Strict Priority (SP)
22701 * 0..7 - Valid values.
22702 * 8..255 - Reserved.
22704 uint8_t queue_id7_pri_lvl;
22706 * Weight used to allocate remaining BW for this COS after
22707 * servicing guaranteed bandwidths for all COS.
22709 uint8_t queue_id7_bw_weight;
22710 uint8_t unused_1[5];
22713 /* hwrm_queue_cos2bw_cfg_output (size:128b/16B) */
22714 struct hwrm_queue_cos2bw_cfg_output {
22715 /* The specific error status for the command. */
22716 uint16_t error_code;
22717 /* The HWRM command request type. */
22719 /* The sequence ID from the original command. */
22721 /* The length of the response data in number of bytes. */
22723 uint8_t unused_0[7];
22725 * This field is used in Output records to indicate that the output
22726 * is completely written to RAM. This field should be read as '1'
22727 * to indicate that the output has been completely written.
22728 * When writing a command completion or response to an internal processor,
22729 * the order of writes has to be such that this field is written last.
22734 /*************************
22735 * hwrm_queue_dscp_qcaps *
22736 *************************/
22739 /* hwrm_queue_dscp_qcaps_input (size:192b/24B) */
22740 struct hwrm_queue_dscp_qcaps_input {
22741 /* The HWRM command request type. */
22744 * The completion ring to send the completion event on. This should
22745 * be the NQ ID returned from the `nq_alloc` HWRM command.
22747 uint16_t cmpl_ring;
22749 * The sequence ID is used by the driver for tracking multiple
22750 * commands. This ID is treated as opaque data by the firmware and
22751 * the value is returned in the `hwrm_resp_hdr` upon completion.
22755 * The target ID of the command:
22756 * * 0x0-0xFFF8 - The function ID
22757 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
22758 * * 0xFFFD - Reserved for user-space HWRM interface
22761 uint16_t target_id;
22763 * A physical address pointer pointing to a host buffer that the
22764 * command's response data will be written. This can be either a host
22765 * physical address (HPA) or a guest physical address (GPA) and must
22766 * point to a physically contiguous block of memory.
22768 uint64_t resp_addr;
22770 * Port ID of port for which the table is being configured.
22771 * The HWRM needs to check whether this function is allowed
22772 * to configure pri2cos mapping on this port.
22775 uint8_t unused_0[7];
22778 /* hwrm_queue_dscp_qcaps_output (size:128b/16B) */
22779 struct hwrm_queue_dscp_qcaps_output {
22780 /* The specific error status for the command. */
22781 uint16_t error_code;
22782 /* The HWRM command request type. */
22784 /* The sequence ID from the original command. */
22786 /* The length of the response data in number of bytes. */
22788 /* The number of bits provided by the hardware for the DSCP value. */
22789 uint8_t num_dscp_bits;
22791 /* Max number of DSCP-MASK-PRI entries supported. */
22792 uint16_t max_entries;
22793 uint8_t unused_1[3];
22795 * This field is used in Output records to indicate that the output
22796 * is completely written to RAM. This field should be read as '1'
22797 * to indicate that the output has been completely written.
22798 * When writing a command completion or response to an internal processor,
22799 * the order of writes has to be such that this field is written last.
22804 /****************************
22805 * hwrm_queue_dscp2pri_qcfg *
22806 ****************************/
22809 /* hwrm_queue_dscp2pri_qcfg_input (size:256b/32B) */
22810 struct hwrm_queue_dscp2pri_qcfg_input {
22811 /* The HWRM command request type. */
22814 * The completion ring to send the completion event on. This should
22815 * be the NQ ID returned from the `nq_alloc` HWRM command.
22817 uint16_t cmpl_ring;
22819 * The sequence ID is used by the driver for tracking multiple
22820 * commands. This ID is treated as opaque data by the firmware and
22821 * the value is returned in the `hwrm_resp_hdr` upon completion.
22825 * The target ID of the command:
22826 * * 0x0-0xFFF8 - The function ID
22827 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
22828 * * 0xFFFD - Reserved for user-space HWRM interface
22831 uint16_t target_id;
22833 * A physical address pointer pointing to a host buffer that the
22834 * command's response data will be written. This can be either a host
22835 * physical address (HPA) or a guest physical address (GPA) and must
22836 * point to a physically contiguous block of memory.
22838 uint64_t resp_addr;
22840 * This is the host address where the 24-bits DSCP-MASK-PRI
22841 * tuple(s) will be copied to.
22843 uint64_t dest_data_addr;
22845 * Port ID of port for which the table is being configured.
22846 * The HWRM needs to check whether this function is allowed
22847 * to configure pri2cos mapping on this port.
22851 /* Size of the buffer pointed to by dest_data_addr. */
22852 uint16_t dest_data_buffer_size;
22853 uint8_t unused_1[4];
22856 /* hwrm_queue_dscp2pri_qcfg_output (size:128b/16B) */
22857 struct hwrm_queue_dscp2pri_qcfg_output {
22858 /* The specific error status for the command. */
22859 uint16_t error_code;
22860 /* The HWRM command request type. */
22862 /* The sequence ID from the original command. */
22864 /* The length of the response data in number of bytes. */
22867 * A count of the number of DSCP-MASK-PRI tuple(s) pointed to
22868 * by the dest_data_addr.
22870 uint16_t entry_cnt;
22872 * This is the default PRI which un-initialized DSCP values are
22875 uint8_t default_pri;
22876 uint8_t unused_0[4];
22878 * This field is used in Output records to indicate that the output
22879 * is completely written to RAM. This field should be read as '1'
22880 * to indicate that the output has been completely written.
22881 * When writing a command completion or response to an internal processor,
22882 * the order of writes has to be such that this field is written last.
22887 /***************************
22888 * hwrm_queue_dscp2pri_cfg *
22889 ***************************/
22892 /* hwrm_queue_dscp2pri_cfg_input (size:320b/40B) */
22893 struct hwrm_queue_dscp2pri_cfg_input {
22894 /* The HWRM command request type. */
22897 * The completion ring to send the completion event on. This should
22898 * be the NQ ID returned from the `nq_alloc` HWRM command.
22900 uint16_t cmpl_ring;
22902 * The sequence ID is used by the driver for tracking multiple
22903 * commands. This ID is treated as opaque data by the firmware and
22904 * the value is returned in the `hwrm_resp_hdr` upon completion.
22908 * The target ID of the command:
22909 * * 0x0-0xFFF8 - The function ID
22910 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
22911 * * 0xFFFD - Reserved for user-space HWRM interface
22914 uint16_t target_id;
22916 * A physical address pointer pointing to a host buffer that the
22917 * command's response data will be written. This can be either a host
22918 * physical address (HPA) or a guest physical address (GPA) and must
22919 * point to a physically contiguous block of memory.
22921 uint64_t resp_addr;
22923 * This is the host address where the 24-bits DSCP-MASK-PRI tuple
22924 * will be copied from.
22926 uint64_t src_data_addr;
22928 /* use_hw_default_pri is 1 b */
22929 #define HWRM_QUEUE_DSCP2PRI_CFG_INPUT_FLAGS_USE_HW_DEFAULT_PRI \
22933 * This bit must be '1' for the default_pri field to be
22936 #define HWRM_QUEUE_DSCP2PRI_CFG_INPUT_ENABLES_DEFAULT_PRI \
22939 * Port ID of port for which the table is being configured.
22940 * The HWRM needs to check whether this function is allowed
22941 * to configure pri2cos mapping on this port.
22945 * This is the default PRI which un-initialized DSCP values will be
22948 uint8_t default_pri;
22950 * A count of the number of DSCP-MASK-PRI tuple(s) in the data pointed
22951 * to by src_data_addr.
22953 uint16_t entry_cnt;
22954 uint8_t unused_0[4];
22957 /* hwrm_queue_dscp2pri_cfg_output (size:128b/16B) */
22958 struct hwrm_queue_dscp2pri_cfg_output {
22959 /* The specific error status for the command. */
22960 uint16_t error_code;
22961 /* The HWRM command request type. */
22963 /* The sequence ID from the original command. */
22965 /* The length of the response data in number of bytes. */
22967 uint8_t unused_0[7];
22969 * This field is used in Output records to indicate that the output
22970 * is completely written to RAM. This field should be read as '1'
22971 * to indicate that the output has been completely written.
22972 * When writing a command completion or response to an internal processor,
22973 * the order of writes has to be such that this field is written last.
22978 /*************************
22979 * hwrm_queue_mpls_qcaps *
22980 *************************/
22983 /* hwrm_queue_mpls_qcaps_input (size:192b/24B) */
22984 struct hwrm_queue_mpls_qcaps_input {
22985 /* The HWRM command request type. */
22988 * The completion ring to send the completion event on. This should
22989 * be the NQ ID returned from the `nq_alloc` HWRM command.
22991 uint16_t cmpl_ring;
22993 * The sequence ID is used by the driver for tracking multiple
22994 * commands. This ID is treated as opaque data by the firmware and
22995 * the value is returned in the `hwrm_resp_hdr` upon completion.
22999 * The target ID of the command:
23000 * * 0x0-0xFFF8 - The function ID
23001 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
23002 * * 0xFFFD - Reserved for user-space HWRM interface
23005 uint16_t target_id;
23007 * A physical address pointer pointing to a host buffer that the
23008 * command's response data will be written. This can be either a host
23009 * physical address (HPA) or a guest physical address (GPA) and must
23010 * point to a physically contiguous block of memory.
23012 uint64_t resp_addr;
23014 * Port ID of port for which the table is being configured.
23015 * The HWRM needs to check whether this function is allowed
23016 * to configure MPLS TC(EXP) to pri mapping on this port.
23019 uint8_t unused_0[7];
23022 /* hwrm_queue_mpls_qcaps_output (size:128b/16B) */
23023 struct hwrm_queue_mpls_qcaps_output {
23024 /* The specific error status for the command. */
23025 uint16_t error_code;
23026 /* The HWRM command request type. */
23028 /* The sequence ID from the original command. */
23030 /* The length of the response data in number of bytes. */
23033 * Bitmask indicating which queues can be configured by the
23034 * hwrm_queue_mplstc2pri_cfg command.
23036 * Each bit represents a specific pri where bit 0 represents
23037 * pri 0 and bit 7 represents pri 7.
23038 * # A value of 0 indicates that the pri is not configurable
23039 * by the hwrm_queue_mplstc2pri_cfg command.
23040 * # A value of 1 indicates that the pri is configurable.
23041 * # A hwrm_queue_mplstc2pri_cfg command shall return error when
23042 * trying to configure a pri that is not configurable.
23044 uint8_t queue_mplstc2pri_cfg_allowed;
23046 * This is the default PRI which un-initialized MPLS values will be
23049 uint8_t hw_default_pri;
23050 uint8_t unused_0[5];
23052 * This field is used in Output records to indicate that the output
23053 * is completely written to RAM. This field should be read as '1'
23054 * to indicate that the output has been completely written.
23055 * When writing a command completion or response to an internal processor,
23056 * the order of writes has to be such that this field is written last.
23061 /******************************
23062 * hwrm_queue_mplstc2pri_qcfg *
23063 ******************************/
23066 /* hwrm_queue_mplstc2pri_qcfg_input (size:192b/24B) */
23067 struct hwrm_queue_mplstc2pri_qcfg_input {
23068 /* The HWRM command request type. */
23071 * The completion ring to send the completion event on. This should
23072 * be the NQ ID returned from the `nq_alloc` HWRM command.
23074 uint16_t cmpl_ring;
23076 * The sequence ID is used by the driver for tracking multiple
23077 * commands. This ID is treated as opaque data by the firmware and
23078 * the value is returned in the `hwrm_resp_hdr` upon completion.
23082 * The target ID of the command:
23083 * * 0x0-0xFFF8 - The function ID
23084 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
23085 * * 0xFFFD - Reserved for user-space HWRM interface
23088 uint16_t target_id;
23090 * A physical address pointer pointing to a host buffer that the
23091 * command's response data will be written. This can be either a host
23092 * physical address (HPA) or a guest physical address (GPA) and must
23093 * point to a physically contiguous block of memory.
23095 uint64_t resp_addr;
23097 * Port ID of port for which the table is being configured.
23098 * The HWRM needs to check whether this function is allowed
23099 * to configure MPLS TC(EXP) to pri mapping on this port.
23102 uint8_t unused_0[7];
23105 /* hwrm_queue_mplstc2pri_qcfg_output (size:192b/24B) */
23106 struct hwrm_queue_mplstc2pri_qcfg_output {
23107 /* The specific error status for the command. */
23108 uint16_t error_code;
23109 /* The HWRM command request type. */
23111 /* The sequence ID from the original command. */
23113 /* The length of the response data in number of bytes. */
23116 * pri assigned to MPLS TC(EXP) 0. This value can only be changed
23117 * before traffic has started.
23118 * A value of 0xff indicates that no pri is assigned to the
23121 uint8_t tc0_pri_queue_id;
23123 * pri assigned to MPLS TC(EXP) 1. This value can only be changed
23124 * before traffic has started.
23125 * A value of 0xff indicates that no pri is assigned to the
23128 uint8_t tc1_pri_queue_id;
23130 * pri assigned to MPLS TC(EXP) 2. This value can only be changed
23131 * before traffic has started.
23132 * A value of 0xff indicates that no pri is assigned to the
23135 uint8_t tc2_pri_queue_id;
23137 * pri assigned to MPLS TC(EXP) 3. This value can only be changed
23138 * before traffic has started.
23139 * A value of 0xff indicates that no pri is assigned to the
23142 uint8_t tc3_pri_queue_id;
23144 * pri assigned to MPLS TC(EXP) 4. This value can only be changed
23145 * before traffic has started.
23146 * A value of 0xff indicates that no pri is assigned to the
23149 uint8_t tc4_pri_queue_id;
23151 * pri assigned to MPLS TC(EXP) 5. This value can only be changed
23152 * before traffic has started.
23153 * A value of 0xff indicates that no pri is assigned to the
23156 uint8_t tc5_pri_queue_id;
23158 * pri assigned to MPLS TC(EXP) 6. This value can only
23159 * be changed before traffic has started.
23160 * A value of 0xff indicates that no pri is assigned to the
23163 uint8_t tc6_pri_queue_id;
23165 * pri assigned to MPLS TC(EXP) 7. This value can only
23166 * be changed before traffic has started.
23167 * A value of 0xff indicates that no pri is assigned to the
23170 uint8_t tc7_pri_queue_id;
23171 uint8_t unused_0[7];
23173 * This field is used in Output records to indicate that the output
23174 * is completely written to RAM. This field should be read as '1'
23175 * to indicate that the output has been completely written.
23176 * When writing a command completion or response to an internal processor,
23177 * the order of writes has to be such that this field is written last.
23182 /*****************************
23183 * hwrm_queue_mplstc2pri_cfg *
23184 *****************************/
23187 /* hwrm_queue_mplstc2pri_cfg_input (size:256b/32B) */
23188 struct hwrm_queue_mplstc2pri_cfg_input {
23189 /* The HWRM command request type. */
23192 * The completion ring to send the completion event on. This should
23193 * be the NQ ID returned from the `nq_alloc` HWRM command.
23195 uint16_t cmpl_ring;
23197 * The sequence ID is used by the driver for tracking multiple
23198 * commands. This ID is treated as opaque data by the firmware and
23199 * the value is returned in the `hwrm_resp_hdr` upon completion.
23203 * The target ID of the command:
23204 * * 0x0-0xFFF8 - The function ID
23205 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
23206 * * 0xFFFD - Reserved for user-space HWRM interface
23209 uint16_t target_id;
23211 * A physical address pointer pointing to a host buffer that the
23212 * command's response data will be written. This can be either a host
23213 * physical address (HPA) or a guest physical address (GPA) and must
23214 * point to a physically contiguous block of memory.
23216 uint64_t resp_addr;
23219 * This bit must be '1' for the mplstc0_pri_queue_id field to be
23222 #define HWRM_QUEUE_MPLSTC2PRI_CFG_INPUT_ENABLES_TC0_PRI_QUEUE_ID \
23225 * This bit must be '1' for the mplstc1_pri_queue_id field to be
23228 #define HWRM_QUEUE_MPLSTC2PRI_CFG_INPUT_ENABLES_TC1_PRI_QUEUE_ID \
23231 * This bit must be '1' for the mplstc2_pri_queue_id field to be
23234 #define HWRM_QUEUE_MPLSTC2PRI_CFG_INPUT_ENABLES_TC2_PRI_QUEUE_ID \
23237 * This bit must be '1' for the mplstc3_pri_queue_id field to be
23240 #define HWRM_QUEUE_MPLSTC2PRI_CFG_INPUT_ENABLES_TC3_PRI_QUEUE_ID \
23243 * This bit must be '1' for the mplstc4_pri_queue_id field to be
23246 #define HWRM_QUEUE_MPLSTC2PRI_CFG_INPUT_ENABLES_TC4_PRI_QUEUE_ID \
23249 * This bit must be '1' for the mplstc5_pri_queue_id field to be
23252 #define HWRM_QUEUE_MPLSTC2PRI_CFG_INPUT_ENABLES_TC5_PRI_QUEUE_ID \
23255 * This bit must be '1' for the mplstc6_pri_queue_id field to be
23258 #define HWRM_QUEUE_MPLSTC2PRI_CFG_INPUT_ENABLES_TC6_PRI_QUEUE_ID \
23261 * This bit must be '1' for the mplstc7_pri_queue_id field to be
23264 #define HWRM_QUEUE_MPLSTC2PRI_CFG_INPUT_ENABLES_TC7_PRI_QUEUE_ID \
23267 * Port ID of port for which the table is being configured.
23268 * The HWRM needs to check whether this function is allowed
23269 * to configure MPLS TC(EXP)to pri mapping on this port.
23272 uint8_t unused_0[3];
23274 * pri assigned to MPLS TC(EXP) 0. This value can only
23275 * be changed before traffic has started.
23277 uint8_t tc0_pri_queue_id;
23279 * pri assigned to MPLS TC(EXP) 1. This value can only
23280 * be changed before traffic has started.
23282 uint8_t tc1_pri_queue_id;
23284 * pri assigned to MPLS TC(EXP) 2 This value can only
23285 * be changed before traffic has started.
23287 uint8_t tc2_pri_queue_id;
23289 * pri assigned to MPLS TC(EXP) 3. This value can only
23290 * be changed before traffic has started.
23292 uint8_t tc3_pri_queue_id;
23294 * pri assigned to MPLS TC(EXP) 4. This value can only
23295 * be changed before traffic has started.
23297 uint8_t tc4_pri_queue_id;
23299 * pri assigned to MPLS TC(EXP) 5. This value can only
23300 * be changed before traffic has started.
23302 uint8_t tc5_pri_queue_id;
23304 * pri assigned to MPLS TC(EXP) 6. This value can only
23305 * be changed before traffic has started.
23307 uint8_t tc6_pri_queue_id;
23309 * pri assigned to MPLS TC(EXP) 7. This value can only
23310 * be changed before traffic has started.
23312 uint8_t tc7_pri_queue_id;
23315 /* hwrm_queue_mplstc2pri_cfg_output (size:128b/16B) */
23316 struct hwrm_queue_mplstc2pri_cfg_output {
23317 /* The specific error status for the command. */
23318 uint16_t error_code;
23319 /* The HWRM command request type. */
23321 /* The sequence ID from the original command. */
23323 /* The length of the response data in number of bytes. */
23325 uint8_t unused_0[7];
23327 * This field is used in Output records to indicate that the output
23328 * is completely written to RAM. This field should be read as '1'
23329 * to indicate that the output has been completely written.
23330 * When writing a command completion or response to an internal processor,
23331 * the order of writes has to be such that this field is written last.
23336 /*******************
23337 * hwrm_vnic_alloc *
23338 *******************/
23341 /* hwrm_vnic_alloc_input (size:192b/24B) */
23342 struct hwrm_vnic_alloc_input {
23343 /* The HWRM command request type. */
23346 * The completion ring to send the completion event on. This should
23347 * be the NQ ID returned from the `nq_alloc` HWRM command.
23349 uint16_t cmpl_ring;
23351 * The sequence ID is used by the driver for tracking multiple
23352 * commands. This ID is treated as opaque data by the firmware and
23353 * the value is returned in the `hwrm_resp_hdr` upon completion.
23357 * The target ID of the command:
23358 * * 0x0-0xFFF8 - The function ID
23359 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
23360 * * 0xFFFD - Reserved for user-space HWRM interface
23363 uint16_t target_id;
23365 * A physical address pointer pointing to a host buffer that the
23366 * command's response data will be written. This can be either a host
23367 * physical address (HPA) or a guest physical address (GPA) and must
23368 * point to a physically contiguous block of memory.
23370 uint64_t resp_addr;
23373 * When this bit is '1', this VNIC is requested to
23374 * be the default VNIC for this function.
23376 #define HWRM_VNIC_ALLOC_INPUT_FLAGS_DEFAULT UINT32_C(0x1)
23377 uint8_t unused_0[4];
23380 /* hwrm_vnic_alloc_output (size:128b/16B) */
23381 struct hwrm_vnic_alloc_output {
23382 /* The specific error status for the command. */
23383 uint16_t error_code;
23384 /* The HWRM command request type. */
23386 /* The sequence ID from the original command. */
23388 /* The length of the response data in number of bytes. */
23390 /* Logical vnic ID */
23392 uint8_t unused_0[3];
23394 * This field is used in Output records to indicate that the output
23395 * is completely written to RAM. This field should be read as '1'
23396 * to indicate that the output has been completely written.
23397 * When writing a command completion or response to an internal processor,
23398 * the order of writes has to be such that this field is written last.
23403 /******************
23405 ******************/
23408 /* hwrm_vnic_free_input (size:192b/24B) */
23409 struct hwrm_vnic_free_input {
23410 /* The HWRM command request type. */
23413 * The completion ring to send the completion event on. This should
23414 * be the NQ ID returned from the `nq_alloc` HWRM command.
23416 uint16_t cmpl_ring;
23418 * The sequence ID is used by the driver for tracking multiple
23419 * commands. This ID is treated as opaque data by the firmware and
23420 * the value is returned in the `hwrm_resp_hdr` upon completion.
23424 * The target ID of the command:
23425 * * 0x0-0xFFF8 - The function ID
23426 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
23427 * * 0xFFFD - Reserved for user-space HWRM interface
23430 uint16_t target_id;
23432 * A physical address pointer pointing to a host buffer that the
23433 * command's response data will be written. This can be either a host
23434 * physical address (HPA) or a guest physical address (GPA) and must
23435 * point to a physically contiguous block of memory.
23437 uint64_t resp_addr;
23438 /* Logical vnic ID */
23440 uint8_t unused_0[4];
23443 /* hwrm_vnic_free_output (size:128b/16B) */
23444 struct hwrm_vnic_free_output {
23445 /* The specific error status for the command. */
23446 uint16_t error_code;
23447 /* The HWRM command request type. */
23449 /* The sequence ID from the original command. */
23451 /* The length of the response data in number of bytes. */
23453 uint8_t unused_0[7];
23455 * This field is used in Output records to indicate that the output
23456 * is completely written to RAM. This field should be read as '1'
23457 * to indicate that the output has been completely written.
23458 * When writing a command completion or response to an internal processor,
23459 * the order of writes has to be such that this field is written last.
23469 /* hwrm_vnic_cfg_input (size:384b/48B) */
23470 struct hwrm_vnic_cfg_input {
23471 /* The HWRM command request type. */
23474 * The completion ring to send the completion event on. This should
23475 * be the NQ ID returned from the `nq_alloc` HWRM command.
23477 uint16_t cmpl_ring;
23479 * The sequence ID is used by the driver for tracking multiple
23480 * commands. This ID is treated as opaque data by the firmware and
23481 * the value is returned in the `hwrm_resp_hdr` upon completion.
23485 * The target ID of the command:
23486 * * 0x0-0xFFF8 - The function ID
23487 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
23488 * * 0xFFFD - Reserved for user-space HWRM interface
23491 uint16_t target_id;
23493 * A physical address pointer pointing to a host buffer that the
23494 * command's response data will be written. This can be either a host
23495 * physical address (HPA) or a guest physical address (GPA) and must
23496 * point to a physically contiguous block of memory.
23498 uint64_t resp_addr;
23501 * When this bit is '1', the VNIC is requested to
23502 * be the default VNIC for the function.
23504 #define HWRM_VNIC_CFG_INPUT_FLAGS_DEFAULT \
23507 * When this bit is '1', the VNIC is being configured to
23508 * strip VLAN in the RX path.
23509 * If set to '0', then VLAN stripping is disabled on
23512 #define HWRM_VNIC_CFG_INPUT_FLAGS_VLAN_STRIP_MODE \
23515 * When this bit is '1', the VNIC is being configured to
23516 * buffer receive packets in the hardware until the host
23517 * posts new receive buffers.
23518 * If set to '0', then bd_stall is being configured to be
23519 * disabled on this VNIC.
23521 #define HWRM_VNIC_CFG_INPUT_FLAGS_BD_STALL_MODE \
23524 * When this bit is '1', the VNIC is being configured to
23525 * receive both RoCE and non-RoCE traffic.
23526 * If set to '0', then this VNIC is not configured to be
23527 * operating in dual VNIC mode.
23529 #define HWRM_VNIC_CFG_INPUT_FLAGS_ROCE_DUAL_VNIC_MODE \
23532 * When this flag is set to '1', the VNIC is requested to
23533 * be configured to receive only RoCE traffic.
23534 * If this flag is set to '0', then this flag shall be
23535 * ignored by the HWRM.
23536 * If roce_dual_vnic_mode flag is set to '1'
23537 * or roce_mirroring_capable_vnic_mode flag to 1,
23538 * then the HWRM client shall not set this flag to '1'.
23540 #define HWRM_VNIC_CFG_INPUT_FLAGS_ROCE_ONLY_VNIC_MODE \
23543 * When a VNIC uses one destination ring group for certain
23544 * application (e.g. Receive Flow Steering) where
23545 * exact match is used to direct packets to a VNIC with one
23546 * destination ring group only, there is no need to configure
23547 * RSS indirection table for that VNIC as only one destination
23548 * ring group is used.
23550 * This flag is used to enable a mode where
23551 * RSS is enabled in the VNIC using a RSS context
23552 * for computing RSS hash but the RSS indirection table is
23553 * not configured using hwrm_vnic_rss_cfg.
23555 * If this mode is enabled, then the driver should not program
23556 * RSS indirection table for the RSS context that is used for
23557 * computing RSS hash only.
23559 #define HWRM_VNIC_CFG_INPUT_FLAGS_RSS_DFLT_CR_MODE \
23562 * When this bit is '1', the VNIC is being configured to
23563 * receive both RoCE and non-RoCE traffic, but forward only the
23564 * RoCE traffic further. Also, RoCE traffic can be mirrored to
23567 #define HWRM_VNIC_CFG_INPUT_FLAGS_ROCE_MIRRORING_CAPABLE_VNIC_MODE \
23571 * This bit must be '1' for the dflt_ring_grp field to be
23574 #define HWRM_VNIC_CFG_INPUT_ENABLES_DFLT_RING_GRP \
23577 * This bit must be '1' for the rss_rule field to be
23580 #define HWRM_VNIC_CFG_INPUT_ENABLES_RSS_RULE \
23583 * This bit must be '1' for the cos_rule field to be
23586 #define HWRM_VNIC_CFG_INPUT_ENABLES_COS_RULE \
23589 * This bit must be '1' for the lb_rule field to be
23592 #define HWRM_VNIC_CFG_INPUT_ENABLES_LB_RULE \
23595 * This bit must be '1' for the mru field to be
23598 #define HWRM_VNIC_CFG_INPUT_ENABLES_MRU \
23601 * This bit must be '1' for the default_rx_ring_id field to be
23604 #define HWRM_VNIC_CFG_INPUT_ENABLES_DEFAULT_RX_RING_ID \
23607 * This bit must be '1' for the default_cmpl_ring_id field to be
23610 #define HWRM_VNIC_CFG_INPUT_ENABLES_DEFAULT_CMPL_RING_ID \
23612 /* This bit must be '1' for the queue_id field to be configured. */
23613 #define HWRM_VNIC_CFG_INPUT_ENABLES_QUEUE_ID \
23615 /* Logical vnic ID */
23618 * Default Completion ring for the VNIC. This ring will
23619 * be chosen if packet does not match any RSS rules and if
23620 * there is no COS rule.
23622 uint16_t dflt_ring_grp;
23624 * RSS ID for RSS rule/table structure. 0xFF... (All Fs) if
23625 * there is no RSS rule.
23629 * RSS ID for COS rule/table structure. 0xFF... (All Fs) if
23630 * there is no COS rule.
23634 * RSS ID for load balancing rule/table structure.
23635 * 0xFF... (All Fs) if there is no LB rule.
23639 * The maximum receive unit of the vnic.
23640 * Each vnic is associated with a function.
23641 * The vnic mru value overwrites the mru setting of the
23642 * associated function.
23643 * The HWRM shall make sure that vnic mru does not exceed
23644 * the mru of the port the function is associated with.
23648 * Default Rx ring for the VNIC. This ring will
23649 * be chosen if packet does not match any RSS rules.
23650 * The aggregation ring associated with the Rx ring is
23651 * implied based on the Rx ring specified when the
23652 * aggregation ring was allocated.
23654 uint16_t default_rx_ring_id;
23656 * Default completion ring for the VNIC. This ring will
23657 * be chosen if packet does not match any RSS rules.
23659 uint16_t default_cmpl_ring_id;
23661 * When specified, only incoming packets classified to the specified CoS
23662 * queue ID will be arriving on this VNIC. Packet priority to CoS mapping
23663 * rules can be specified using HWRM_QUEUE_PRI2COS_CFG. In this mode,
23664 * ntuple filters with VNIC destination specified are invalid since they
23665 * conflict with the the CoS to VNIC steering rules in this mode.
23667 * If this field is not specified, packet to VNIC steering will be
23668 * subject to the standard L2 filter rules and any additional ntuple
23669 * filter rules with destination VNIC specified.
23672 uint8_t unused0[6];
23675 /* hwrm_vnic_cfg_output (size:128b/16B) */
23676 struct hwrm_vnic_cfg_output {
23677 /* The specific error status for the command. */
23678 uint16_t error_code;
23679 /* The HWRM command request type. */
23681 /* The sequence ID from the original command. */
23683 /* The length of the response data in number of bytes. */
23685 uint8_t unused_0[7];
23687 * This field is used in Output records to indicate that the output
23688 * is completely written to RAM. This field should be read as '1'
23689 * to indicate that the output has been completely written.
23690 * When writing a command completion or response to an internal processor,
23691 * the order of writes has to be such that this field is written last.
23696 /******************
23698 ******************/
23701 /* hwrm_vnic_qcfg_input (size:256b/32B) */
23702 struct hwrm_vnic_qcfg_input {
23703 /* The HWRM command request type. */
23706 * The completion ring to send the completion event on. This should
23707 * be the NQ ID returned from the `nq_alloc` HWRM command.
23709 uint16_t cmpl_ring;
23711 * The sequence ID is used by the driver for tracking multiple
23712 * commands. This ID is treated as opaque data by the firmware and
23713 * the value is returned in the `hwrm_resp_hdr` upon completion.
23717 * The target ID of the command:
23718 * * 0x0-0xFFF8 - The function ID
23719 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
23720 * * 0xFFFD - Reserved for user-space HWRM interface
23723 uint16_t target_id;
23725 * A physical address pointer pointing to a host buffer that the
23726 * command's response data will be written. This can be either a host
23727 * physical address (HPA) or a guest physical address (GPA) and must
23728 * point to a physically contiguous block of memory.
23730 uint64_t resp_addr;
23733 * This bit must be '1' for the vf_id_valid field to be
23736 #define HWRM_VNIC_QCFG_INPUT_ENABLES_VF_ID_VALID UINT32_C(0x1)
23737 /* Logical vnic ID */
23739 /* ID of Virtual Function whose VNIC resource is being queried. */
23741 uint8_t unused_0[6];
23744 /* hwrm_vnic_qcfg_output (size:256b/32B) */
23745 struct hwrm_vnic_qcfg_output {
23746 /* The specific error status for the command. */
23747 uint16_t error_code;
23748 /* The HWRM command request type. */
23750 /* The sequence ID from the original command. */
23752 /* The length of the response data in number of bytes. */
23754 /* Default Completion ring for the VNIC. */
23755 uint16_t dflt_ring_grp;
23757 * RSS ID for RSS rule/table structure. 0xFF... (All Fs) if
23758 * there is no RSS rule.
23762 * RSS ID for COS rule/table structure. 0xFF... (All Fs) if
23763 * there is no COS rule.
23767 * RSS ID for load balancing rule/table structure.
23768 * 0xFF... (All Fs) if there is no LB rule.
23771 /* The maximum receive unit of the vnic. */
23773 uint8_t unused_0[2];
23776 * When this bit is '1', the VNIC is the default VNIC for
23779 #define HWRM_VNIC_QCFG_OUTPUT_FLAGS_DEFAULT \
23782 * When this bit is '1', the VNIC is configured to
23783 * strip VLAN in the RX path.
23784 * If set to '0', then VLAN stripping is disabled on
23787 #define HWRM_VNIC_QCFG_OUTPUT_FLAGS_VLAN_STRIP_MODE \
23790 * When this bit is '1', the VNIC is configured to
23791 * buffer receive packets in the hardware until the host
23792 * posts new receive buffers.
23793 * If set to '0', then bd_stall is disabled on
23796 #define HWRM_VNIC_QCFG_OUTPUT_FLAGS_BD_STALL_MODE \
23799 * When this bit is '1', the VNIC is configured to
23800 * receive both RoCE and non-RoCE traffic.
23801 * If set to '0', then this VNIC is not configured to
23802 * operate in dual VNIC mode.
23804 #define HWRM_VNIC_QCFG_OUTPUT_FLAGS_ROCE_DUAL_VNIC_MODE \
23807 * When this flag is set to '1', the VNIC is configured to
23808 * receive only RoCE traffic.
23809 * When this flag is set to '0', the VNIC is not configured
23810 * to receive only RoCE traffic.
23811 * If roce_dual_vnic_mode flag and this flag both are set
23812 * to '1', then it is an invalid configuration of the
23813 * VNIC. The HWRM should not allow that type of
23814 * mis-configuration by HWRM clients.
23816 #define HWRM_VNIC_QCFG_OUTPUT_FLAGS_ROCE_ONLY_VNIC_MODE \
23819 * When a VNIC uses one destination ring group for certain
23820 * application (e.g. Receive Flow Steering) where
23821 * exact match is used to direct packets to a VNIC with one
23822 * destination ring group only, there is no need to configure
23823 * RSS indirection table for that VNIC as only one destination
23824 * ring group is used.
23826 * When this bit is set to '1', then the VNIC is enabled in a
23827 * mode where RSS is enabled in the VNIC using a RSS context
23828 * for computing RSS hash but the RSS indirection table is
23831 #define HWRM_VNIC_QCFG_OUTPUT_FLAGS_RSS_DFLT_CR_MODE \
23834 * When this bit is '1', the VNIC is configured to
23835 * receive both RoCE and non-RoCE traffic, but forward only
23836 * RoCE traffic further. Also RoCE traffic can be mirrored to
23839 #define HWRM_VNIC_QCFG_OUTPUT_FLAGS_ROCE_MIRRORING_CAPABLE_VNIC_MODE \
23842 * When returned with a valid CoS Queue id, the CoS Queue/VNIC association
23843 * is valid. Otherwise it will return 0xFFFF to indicate no VNIC/CoS
23844 * queue association.
23847 uint8_t unused_1[5];
23849 * This field is used in Output records to indicate that the output
23850 * is completely written to RAM. This field should be read as '1'
23851 * to indicate that the output has been completely written.
23852 * When writing a command completion or response to an internal processor,
23853 * the order of writes has to be such that this field is written last.
23858 /*******************
23859 * hwrm_vnic_qcaps *
23860 *******************/
23863 /* hwrm_vnic_qcaps_input (size:192b/24B) */
23864 struct hwrm_vnic_qcaps_input {
23865 /* The HWRM command request type. */
23868 * The completion ring to send the completion event on. This should
23869 * be the NQ ID returned from the `nq_alloc` HWRM command.
23871 uint16_t cmpl_ring;
23873 * The sequence ID is used by the driver for tracking multiple
23874 * commands. This ID is treated as opaque data by the firmware and
23875 * the value is returned in the `hwrm_resp_hdr` upon completion.
23879 * The target ID of the command:
23880 * * 0x0-0xFFF8 - The function ID
23881 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
23882 * * 0xFFFD - Reserved for user-space HWRM interface
23885 uint16_t target_id;
23887 * A physical address pointer pointing to a host buffer that the
23888 * command's response data will be written. This can be either a host
23889 * physical address (HPA) or a guest physical address (GPA) and must
23890 * point to a physically contiguous block of memory.
23892 uint64_t resp_addr;
23894 uint8_t unused_0[4];
23897 /* hwrm_vnic_qcaps_output (size:192b/24B) */
23898 struct hwrm_vnic_qcaps_output {
23899 /* The specific error status for the command. */
23900 uint16_t error_code;
23901 /* The HWRM command request type. */
23903 /* The sequence ID from the original command. */
23905 /* The length of the response data in number of bytes. */
23907 /* The maximum receive unit that is settable on a vnic. */
23909 uint8_t unused_0[2];
23912 #define HWRM_VNIC_QCAPS_OUTPUT_FLAGS_UNUSED \
23915 * When this bit is '1', the capability of stripping VLAN in
23916 * the RX path is supported on VNIC(s).
23917 * If set to '0', then VLAN stripping capability is
23918 * not supported on VNIC(s).
23920 #define HWRM_VNIC_QCAPS_OUTPUT_FLAGS_VLAN_STRIP_CAP \
23923 * When this bit is '1', the capability to buffer receive
23924 * packets in the hardware until the host posts new receive buffers
23925 * is supported on VNIC(s).
23926 * If set to '0', then bd_stall capability is not supported
23929 #define HWRM_VNIC_QCAPS_OUTPUT_FLAGS_BD_STALL_CAP \
23932 * When this bit is '1', the capability to
23933 * receive both RoCE and non-RoCE traffic on VNIC(s) is
23935 * If set to '0', then the capability to receive
23936 * both RoCE and non-RoCE traffic on VNIC(s) is
23939 #define HWRM_VNIC_QCAPS_OUTPUT_FLAGS_ROCE_DUAL_VNIC_CAP \
23942 * When this bit is set to '1', the capability to configure
23943 * a VNIC to receive only RoCE traffic is supported.
23944 * When this flag is set to '0', the VNIC capability to
23945 * configure to receive only RoCE traffic is not supported.
23947 #define HWRM_VNIC_QCAPS_OUTPUT_FLAGS_ROCE_ONLY_VNIC_CAP \
23950 * When this bit is set to '1', then the capability to enable
23951 * a VNIC in a mode where RSS context without configuring
23952 * RSS indirection table is supported (for RSS hash computation).
23953 * When this bit is set to '0', then a VNIC can not be configured
23954 * with a mode to enable RSS context without configuring RSS
23955 * indirection table.
23957 #define HWRM_VNIC_QCAPS_OUTPUT_FLAGS_RSS_DFLT_CR_CAP \
23960 * When this bit is '1', the capability to
23961 * mirror the the RoCE traffic is supported.
23962 * If set to '0', then the capability to mirror the
23963 * RoCE traffic is not supported.
23965 #define HWRM_VNIC_QCAPS_OUTPUT_FLAGS_ROCE_MIRRORING_CAPABLE_VNIC_CAP \
23968 * When this bit is '1', the outermost RSS hashing capability
23969 * is supported. If set to '0', then the outermost RSS hashing
23970 * capability is not supported.
23972 #define HWRM_VNIC_QCAPS_OUTPUT_FLAGS_OUTERMOST_RSS_CAP \
23975 * When this bit is '1', it indicates that firmware supports the
23976 * ability to steer incoming packets from one CoS queue to one
23977 * VNIC. This optional feature can then be enabled
23978 * using HWRM_VNIC_CFG on any VNIC. This feature is only
23979 * available when NVM option “enable_cos_classfication” is set
23980 * to 1. If set to '0', firmware does not support this feature.
23982 #define HWRM_VNIC_QCAPS_OUTPUT_FLAGS_COS_ASSIGNMENT_CAP \
23985 * This field advertises the maximum concurrent TPA aggregations
23986 * supported by the VNIC on new devices that support TPA v2.
23987 * '0' means that TPA v2 is not supported.
23989 uint16_t max_aggs_supported;
23990 uint8_t unused_1[5];
23992 * This field is used in Output records to indicate that the output
23993 * is completely written to RAM. This field should be read as '1'
23994 * to indicate that the output has been completely written.
23995 * When writing a command completion or response to an internal processor,
23996 * the order of writes has to be such that this field is written last.
24001 /*********************
24002 * hwrm_vnic_tpa_cfg *
24003 *********************/
24006 /* hwrm_vnic_tpa_cfg_input (size:320b/40B) */
24007 struct hwrm_vnic_tpa_cfg_input {
24008 /* The HWRM command request type. */
24011 * The completion ring to send the completion event on. This should
24012 * be the NQ ID returned from the `nq_alloc` HWRM command.
24014 uint16_t cmpl_ring;
24016 * The sequence ID is used by the driver for tracking multiple
24017 * commands. This ID is treated as opaque data by the firmware and
24018 * the value is returned in the `hwrm_resp_hdr` upon completion.
24022 * The target ID of the command:
24023 * * 0x0-0xFFF8 - The function ID
24024 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
24025 * * 0xFFFD - Reserved for user-space HWRM interface
24028 uint16_t target_id;
24030 * A physical address pointer pointing to a host buffer that the
24031 * command's response data will be written. This can be either a host
24032 * physical address (HPA) or a guest physical address (GPA) and must
24033 * point to a physically contiguous block of memory.
24035 uint64_t resp_addr;
24038 * When this bit is '1', the VNIC shall be configured to
24039 * perform transparent packet aggregation (TPA) of
24040 * non-tunneled TCP packets.
24042 #define HWRM_VNIC_TPA_CFG_INPUT_FLAGS_TPA \
24045 * When this bit is '1', the VNIC shall be configured to
24046 * perform transparent packet aggregation (TPA) of
24047 * tunneled TCP packets.
24049 #define HWRM_VNIC_TPA_CFG_INPUT_FLAGS_ENCAP_TPA \
24052 * When this bit is '1', the VNIC shall be configured to
24053 * perform transparent packet aggregation (TPA) according
24054 * to Windows Receive Segment Coalescing (RSC) rules.
24056 #define HWRM_VNIC_TPA_CFG_INPUT_FLAGS_RSC_WND_UPDATE \
24059 * When this bit is '1', the VNIC shall be configured to
24060 * perform transparent packet aggregation (TPA) according
24061 * to Linux Generic Receive Offload (GRO) rules.
24063 #define HWRM_VNIC_TPA_CFG_INPUT_FLAGS_GRO \
24066 * When this bit is '1', the VNIC shall be configured to
24067 * perform transparent packet aggregation (TPA) for TCP
24068 * packets with IP ECN set to non-zero.
24070 #define HWRM_VNIC_TPA_CFG_INPUT_FLAGS_AGG_WITH_ECN \
24073 * When this bit is '1', the VNIC shall be configured to
24074 * perform transparent packet aggregation (TPA) for
24075 * GRE tunneled TCP packets only if all packets have the
24076 * same GRE sequence.
24078 #define HWRM_VNIC_TPA_CFG_INPUT_FLAGS_AGG_WITH_SAME_GRE_SEQ \
24081 * When this bit is '1' and the GRO mode is enabled,
24082 * the VNIC shall be configured to
24083 * perform transparent packet aggregation (TPA) for
24084 * TCP/IPv4 packets with consecutively increasing IPIDs.
24085 * In other words, the last packet that is being
24086 * aggregated to an already existing aggregation context
24087 * shall have IPID 1 more than the IPID of the last packet
24088 * that was aggregated in that aggregation context.
24090 #define HWRM_VNIC_TPA_CFG_INPUT_FLAGS_GRO_IPID_CHECK \
24093 * When this bit is '1' and the GRO mode is enabled,
24094 * the VNIC shall be configured to
24095 * perform transparent packet aggregation (TPA) for
24096 * TCP packets with the same TTL (IPv4) or Hop limit (IPv6)
24099 #define HWRM_VNIC_TPA_CFG_INPUT_FLAGS_GRO_TTL_CHECK \
24102 * When this bit is '1' and the GRO mode is enabled,
24103 * the VNIC shall DMA payload data using GRO rules.
24104 * When this bit is '0', the VNIC shall DMA payload data
24105 * using the more efficient LRO rules of filling all
24106 * aggregation buffers.
24108 #define HWRM_VNIC_TPA_CFG_INPUT_FLAGS_AGG_PACK_AS_GRO \
24112 * This bit must be '1' for the max_agg_segs field to be
24115 #define HWRM_VNIC_TPA_CFG_INPUT_ENABLES_MAX_AGG_SEGS UINT32_C(0x1)
24117 * This bit must be '1' for the max_aggs field to be
24120 #define HWRM_VNIC_TPA_CFG_INPUT_ENABLES_MAX_AGGS UINT32_C(0x2)
24122 * This bit must be '1' for the max_agg_timer field to be
24125 #define HWRM_VNIC_TPA_CFG_INPUT_ENABLES_MAX_AGG_TIMER UINT32_C(0x4)
24126 /* deprecated bit. Do not use!!! */
24127 #define HWRM_VNIC_TPA_CFG_INPUT_ENABLES_MIN_AGG_LEN UINT32_C(0x8)
24128 /* Logical vnic ID */
24131 * This is the maximum number of TCP segments that can
24132 * be aggregated (unit is Log2). Max value is 31. On new
24133 * devices supporting TPA v2, the unit is multiples of 4 and
24134 * valid values are > 0 and <= 63.
24136 uint16_t max_agg_segs;
24138 #define HWRM_VNIC_TPA_CFG_INPUT_MAX_AGG_SEGS_1 UINT32_C(0x0)
24140 #define HWRM_VNIC_TPA_CFG_INPUT_MAX_AGG_SEGS_2 UINT32_C(0x1)
24142 #define HWRM_VNIC_TPA_CFG_INPUT_MAX_AGG_SEGS_4 UINT32_C(0x2)
24144 #define HWRM_VNIC_TPA_CFG_INPUT_MAX_AGG_SEGS_8 UINT32_C(0x3)
24145 /* Any segment size larger than this is not valid */
24146 #define HWRM_VNIC_TPA_CFG_INPUT_MAX_AGG_SEGS_MAX UINT32_C(0x1f)
24147 #define HWRM_VNIC_TPA_CFG_INPUT_MAX_AGG_SEGS_LAST \
24148 HWRM_VNIC_TPA_CFG_INPUT_MAX_AGG_SEGS_MAX
24150 * This is the maximum number of aggregations this VNIC is
24151 * allowed (unit is Log2). Max value is 7. On new devices
24152 * supporting TPA v2, this is in unit of 1 and must be > 0
24153 * and <= max_aggs_supported in the hwrm_vnic_qcaps response
24154 * to enable TPA v2.
24157 /* 1 aggregation */
24158 #define HWRM_VNIC_TPA_CFG_INPUT_MAX_AGGS_1 UINT32_C(0x0)
24159 /* 2 aggregations */
24160 #define HWRM_VNIC_TPA_CFG_INPUT_MAX_AGGS_2 UINT32_C(0x1)
24161 /* 4 aggregations */
24162 #define HWRM_VNIC_TPA_CFG_INPUT_MAX_AGGS_4 UINT32_C(0x2)
24163 /* 8 aggregations */
24164 #define HWRM_VNIC_TPA_CFG_INPUT_MAX_AGGS_8 UINT32_C(0x3)
24165 /* 16 aggregations */
24166 #define HWRM_VNIC_TPA_CFG_INPUT_MAX_AGGS_16 UINT32_C(0x4)
24167 /* Any aggregation size larger than this is not valid */
24168 #define HWRM_VNIC_TPA_CFG_INPUT_MAX_AGGS_MAX UINT32_C(0x7)
24169 #define HWRM_VNIC_TPA_CFG_INPUT_MAX_AGGS_LAST \
24170 HWRM_VNIC_TPA_CFG_INPUT_MAX_AGGS_MAX
24171 uint8_t unused_0[2];
24173 * This is the maximum amount of time allowed for
24174 * an aggregation context to complete after it was initiated.
24176 uint32_t max_agg_timer;
24178 * This is the minimum amount of payload length required to
24179 * start an aggregation context. This field is deprecated and
24180 * should be set to 0. The minimum length is set by firmware
24181 * and can be queried using hwrm_vnic_tpa_qcfg.
24183 uint32_t min_agg_len;
24186 /* hwrm_vnic_tpa_cfg_output (size:128b/16B) */
24187 struct hwrm_vnic_tpa_cfg_output {
24188 /* The specific error status for the command. */
24189 uint16_t error_code;
24190 /* The HWRM command request type. */
24192 /* The sequence ID from the original command. */
24194 /* The length of the response data in number of bytes. */
24196 uint8_t unused_0[7];
24198 * This field is used in Output records to indicate that the output
24199 * is completely written to RAM. This field should be read as '1'
24200 * to indicate that the output has been completely written.
24201 * When writing a command completion or response to an internal processor,
24202 * the order of writes has to be such that this field is written last.
24207 /*********************
24208 * hwrm_vnic_rss_cfg *
24209 *********************/
24212 /* hwrm_vnic_rss_cfg_input (size:384b/48B) */
24213 struct hwrm_vnic_rss_cfg_input {
24214 /* The HWRM command request type. */
24217 * The completion ring to send the completion event on. This should
24218 * be the NQ ID returned from the `nq_alloc` HWRM command.
24220 uint16_t cmpl_ring;
24222 * The sequence ID is used by the driver for tracking multiple
24223 * commands. This ID is treated as opaque data by the firmware and
24224 * the value is returned in the `hwrm_resp_hdr` upon completion.
24228 * The target ID of the command:
24229 * * 0x0-0xFFF8 - The function ID
24230 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
24231 * * 0xFFFD - Reserved for user-space HWRM interface
24234 uint16_t target_id;
24236 * A physical address pointer pointing to a host buffer that the
24237 * command's response data will be written. This can be either a host
24238 * physical address (HPA) or a guest physical address (GPA) and must
24239 * point to a physically contiguous block of memory.
24241 uint64_t resp_addr;
24242 uint32_t hash_type;
24244 * When this bit is '1', the RSS hash shall be computed
24245 * over source and destination IPv4 addresses of IPv4
24248 #define HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV4 UINT32_C(0x1)
24250 * When this bit is '1', the RSS hash shall be computed
24251 * over source/destination IPv4 addresses and
24252 * source/destination ports of TCP/IPv4 packets.
24254 #define HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV4 UINT32_C(0x2)
24256 * When this bit is '1', the RSS hash shall be computed
24257 * over source/destination IPv4 addresses and
24258 * source/destination ports of UDP/IPv4 packets.
24260 #define HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV4 UINT32_C(0x4)
24262 * When this bit is '1', the RSS hash shall be computed
24263 * over source and destination IPv4 addresses of IPv6
24266 #define HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV6 UINT32_C(0x8)
24268 * When this bit is '1', the RSS hash shall be computed
24269 * over source/destination IPv6 addresses and
24270 * source/destination ports of TCP/IPv6 packets.
24272 #define HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV6 UINT32_C(0x10)
24274 * When this bit is '1', the RSS hash shall be computed
24275 * over source/destination IPv6 addresses and
24276 * source/destination ports of UDP/IPv6 packets.
24278 #define HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV6 UINT32_C(0x20)
24279 /* VNIC ID of VNIC associated with RSS table being configured. */
24282 * Specifies which VNIC ring table pair to configure.
24283 * Valid values range from 0 to 7.
24285 uint8_t ring_table_pair_index;
24286 /* Flags to specify different RSS hash modes. */
24287 uint8_t hash_mode_flags;
24289 * When this bit is '1', it indicates using current RSS
24290 * hash mode setting configured in the device.
24292 #define HWRM_VNIC_RSS_CFG_INPUT_HASH_MODE_FLAGS_DEFAULT \
24295 * When this bit is '1', it indicates requesting support of
24296 * RSS hashing over innermost 4 tuples {l3.src, l3.dest,
24297 * l4.src, l4.dest} for tunnel packets. For none-tunnel
24298 * packets, the RSS hash is computed over the normal
24299 * src/dest l3 and src/dest l4 headers.
24301 #define HWRM_VNIC_RSS_CFG_INPUT_HASH_MODE_FLAGS_INNERMOST_4 \
24304 * When this bit is '1', it indicates requesting support of
24305 * RSS hashing over innermost 2 tuples {l3.src, l3.dest} for
24306 * tunnel packets. For none-tunnel packets, the RSS hash is
24307 * computed over the normal src/dest l3 headers.
24309 #define HWRM_VNIC_RSS_CFG_INPUT_HASH_MODE_FLAGS_INNERMOST_2 \
24312 * When this bit is '1', it indicates requesting support of
24313 * RSS hashing over outermost 4 tuples {t_l3.src, t_l3.dest,
24314 * t_l4.src, t_l4.dest} for tunnel packets. For none-tunnel
24315 * packets, the RSS hash is computed over the normal
24316 * src/dest l3 and src/dest l4 headers.
24318 #define HWRM_VNIC_RSS_CFG_INPUT_HASH_MODE_FLAGS_OUTERMOST_4 \
24321 * When this bit is '1', it indicates requesting support of
24322 * RSS hashing over outermost 2 tuples {t_l3.src, t_l3.dest} for
24323 * tunnel packets. For none-tunnel packets, the RSS hash is
24324 * computed over the normal src/dest l3 headers.
24326 #define HWRM_VNIC_RSS_CFG_INPUT_HASH_MODE_FLAGS_OUTERMOST_2 \
24328 /* This is the address for rss ring group table */
24329 uint64_t ring_grp_tbl_addr;
24330 /* This is the address for rss hash key table */
24331 uint64_t hash_key_tbl_addr;
24332 /* Index to the rss indirection table. */
24333 uint16_t rss_ctx_idx;
24334 uint8_t unused_1[6];
24337 /* hwrm_vnic_rss_cfg_output (size:128b/16B) */
24338 struct hwrm_vnic_rss_cfg_output {
24339 /* The specific error status for the command. */
24340 uint16_t error_code;
24341 /* The HWRM command request type. */
24343 /* The sequence ID from the original command. */
24345 /* The length of the response data in number of bytes. */
24347 uint8_t unused_0[7];
24349 * This field is used in Output records to indicate that the output
24350 * is completely written to RAM. This field should be read as '1'
24351 * to indicate that the output has been completely written.
24352 * When writing a command completion or response to an internal processor,
24353 * the order of writes has to be such that this field is written last.
24358 /* hwrm_vnic_rss_cfg_cmd_err (size:64b/8B) */
24359 struct hwrm_vnic_rss_cfg_cmd_err {
24361 * command specific error codes that goes to
24362 * the cmd_err field in Common HWRM Error Response.
24365 /* Unknown error */
24366 #define HWRM_VNIC_RSS_CFG_CMD_ERR_CODE_UNKNOWN \
24369 * Unable to change global RSS mode to outer due to all active
24370 * interfaces are not ready to support outer RSS hashing.
24372 #define HWRM_VNIC_RSS_CFG_CMD_ERR_CODE_INTERFACE_NOT_READY \
24374 #define HWRM_VNIC_RSS_CFG_CMD_ERR_CODE_LAST \
24375 HWRM_VNIC_RSS_CFG_CMD_ERR_CODE_INTERFACE_NOT_READY
24376 uint8_t unused_0[7];
24379 /**********************
24380 * hwrm_vnic_rss_qcfg *
24381 **********************/
24384 /* hwrm_vnic_rss_qcfg_input (size:192b/24B) */
24385 struct hwrm_vnic_rss_qcfg_input {
24386 /* The HWRM command request type. */
24389 * The completion ring to send the completion event on. This should
24390 * be the NQ ID returned from the `nq_alloc` HWRM command.
24392 uint16_t cmpl_ring;
24394 * The sequence ID is used by the driver for tracking multiple
24395 * commands. This ID is treated as opaque data by the firmware and
24396 * the value is returned in the `hwrm_resp_hdr` upon completion.
24400 * The target ID of the command:
24401 * * 0x0-0xFFF8 - The function ID
24402 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
24403 * * 0xFFFD - Reserved for user-space HWRM interface
24406 uint16_t target_id;
24408 * A physical address pointer pointing to a host buffer that the
24409 * command's response data will be written. This can be either a host
24410 * physical address (HPA) or a guest physical address (GPA) and must
24411 * point to a physically contiguous block of memory.
24413 uint64_t resp_addr;
24414 /* Index to the rss indirection table. */
24415 uint16_t rss_ctx_idx;
24416 uint8_t unused_0[6];
24419 /* hwrm_vnic_rss_qcfg_output (size:512b/64B) */
24420 struct hwrm_vnic_rss_qcfg_output {
24421 /* The specific error status for the command. */
24422 uint16_t error_code;
24423 /* The HWRM command request type. */
24425 /* The sequence ID from the original command. */
24427 /* The length of the response data in number of bytes. */
24429 uint32_t hash_type;
24431 * When this bit is '1', the RSS hash shall be computed
24432 * over source and destination IPv4 addresses of IPv4
24435 #define HWRM_VNIC_RSS_QCFG_OUTPUT_HASH_TYPE_IPV4 UINT32_C(0x1)
24437 * When this bit is '1', the RSS hash shall be computed
24438 * over source/destination IPv4 addresses and
24439 * source/destination ports of TCP/IPv4 packets.
24441 #define HWRM_VNIC_RSS_QCFG_OUTPUT_HASH_TYPE_TCP_IPV4 UINT32_C(0x2)
24443 * When this bit is '1', the RSS hash shall be computed
24444 * over source/destination IPv4 addresses and
24445 * source/destination ports of UDP/IPv4 packets.
24447 #define HWRM_VNIC_RSS_QCFG_OUTPUT_HASH_TYPE_UDP_IPV4 UINT32_C(0x4)
24449 * When this bit is '1', the RSS hash shall be computed
24450 * over source and destination IPv4 addresses of IPv6
24453 #define HWRM_VNIC_RSS_QCFG_OUTPUT_HASH_TYPE_IPV6 UINT32_C(0x8)
24455 * When this bit is '1', the RSS hash shall be computed
24456 * over source/destination IPv6 addresses and
24457 * source/destination ports of TCP/IPv6 packets.
24459 #define HWRM_VNIC_RSS_QCFG_OUTPUT_HASH_TYPE_TCP_IPV6 UINT32_C(0x10)
24461 * When this bit is '1', the RSS hash shall be computed
24462 * over source/destination IPv6 addresses and
24463 * source/destination ports of UDP/IPv6 packets.
24465 #define HWRM_VNIC_RSS_QCFG_OUTPUT_HASH_TYPE_UDP_IPV6 UINT32_C(0x20)
24466 uint8_t unused_0[4];
24467 /* This is the value of rss hash key */
24468 uint32_t hash_key[10];
24469 /* Flags to specify different RSS hash modes. */
24470 uint8_t hash_mode_flags;
24472 * When this bit is '1', it indicates using current RSS
24473 * hash mode setting configured in the device.
24475 #define HWRM_VNIC_RSS_QCFG_OUTPUT_HASH_MODE_FLAGS_DEFAULT \
24478 * When this bit is '1', it indicates requesting support of
24479 * RSS hashing over innermost 4 tuples {l3.src, l3.dest,
24480 * l4.src, l4.dest} for tunnel packets. For none-tunnel
24481 * packets, the RSS hash is computed over the normal
24482 * src/dest l3 and src/dest l4 headers.
24484 #define HWRM_VNIC_RSS_QCFG_OUTPUT_HASH_MODE_FLAGS_INNERMOST_4 \
24487 * When this bit is '1', it indicates requesting support of
24488 * RSS hashing over innermost 2 tuples {l3.src, l3.dest} for
24489 * tunnel packets. For none-tunnel packets, the RSS hash is
24490 * computed over the normal src/dest l3 headers.
24492 #define HWRM_VNIC_RSS_QCFG_OUTPUT_HASH_MODE_FLAGS_INNERMOST_2 \
24495 * When this bit is '1', it indicates requesting support of
24496 * RSS hashing over outermost 4 tuples {t_l3.src, t_l3.dest,
24497 * t_l4.src, t_l4.dest} for tunnel packets. For none-tunnel
24498 * packets, the RSS hash is computed over the normal
24499 * src/dest l3 and src/dest l4 headers.
24501 #define HWRM_VNIC_RSS_QCFG_OUTPUT_HASH_MODE_FLAGS_OUTERMOST_4 \
24504 * When this bit is '1', it indicates requesting support of
24505 * RSS hashing over outermost 2 tuples {t_l3.src, t_l3.dest} for
24506 * tunnel packets. For none-tunnel packets, the RSS hash is
24507 * computed over the normal src/dest l3 headers.
24509 #define HWRM_VNIC_RSS_QCFG_OUTPUT_HASH_MODE_FLAGS_OUTERMOST_2 \
24511 uint8_t unused_1[6];
24513 * This field is used in Output records to indicate that the output
24514 * is completely written to RAM. This field should be read as '1'
24515 * to indicate that the output has been completely written.
24516 * When writing a command completion or response to an internal processor,
24517 * the order of writes has to be such that this field is written last.
24522 /**************************
24523 * hwrm_vnic_plcmodes_cfg *
24524 **************************/
24527 /* hwrm_vnic_plcmodes_cfg_input (size:320b/40B) */
24528 struct hwrm_vnic_plcmodes_cfg_input {
24529 /* The HWRM command request type. */
24532 * The completion ring to send the completion event on. This should
24533 * be the NQ ID returned from the `nq_alloc` HWRM command.
24535 uint16_t cmpl_ring;
24537 * The sequence ID is used by the driver for tracking multiple
24538 * commands. This ID is treated as opaque data by the firmware and
24539 * the value is returned in the `hwrm_resp_hdr` upon completion.
24543 * The target ID of the command:
24544 * * 0x0-0xFFF8 - The function ID
24545 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
24546 * * 0xFFFD - Reserved for user-space HWRM interface
24549 uint16_t target_id;
24551 * A physical address pointer pointing to a host buffer that the
24552 * command's response data will be written. This can be either a host
24553 * physical address (HPA) or a guest physical address (GPA) and must
24554 * point to a physically contiguous block of memory.
24556 uint64_t resp_addr;
24559 * When this bit is '1', the VNIC shall be configured to
24560 * use regular placement algorithm.
24561 * By default, the regular placement algorithm shall be
24562 * enabled on the VNIC.
24564 #define HWRM_VNIC_PLCMODES_CFG_INPUT_FLAGS_REGULAR_PLACEMENT \
24567 * When this bit is '1', the VNIC shall be configured
24568 * use the jumbo placement algorithm.
24570 #define HWRM_VNIC_PLCMODES_CFG_INPUT_FLAGS_JUMBO_PLACEMENT \
24573 * When this bit is '1', the VNIC shall be configured
24574 * to enable Header-Data split for IPv4 packets according
24575 * to the following rules:
24576 * # If the packet is identified as TCP/IPv4, then the
24577 * packet is split at the beginning of the TCP payload.
24578 * # If the packet is identified as UDP/IPv4, then the
24579 * packet is split at the beginning of UDP payload.
24580 * # If the packet is identified as non-TCP and non-UDP
24581 * IPv4 packet, then the packet is split at the beginning
24582 * of the upper layer protocol header carried in the IPv4
24585 #define HWRM_VNIC_PLCMODES_CFG_INPUT_FLAGS_HDS_IPV4 \
24588 * When this bit is '1', the VNIC shall be configured
24589 * to enable Header-Data split for IPv6 packets according
24590 * to the following rules:
24591 * # If the packet is identified as TCP/IPv6, then the
24592 * packet is split at the beginning of the TCP payload.
24593 * # If the packet is identified as UDP/IPv6, then the
24594 * packet is split at the beginning of UDP payload.
24595 * # If the packet is identified as non-TCP and non-UDP
24596 * IPv6 packet, then the packet is split at the beginning
24597 * of the upper layer protocol header carried in the IPv6
24600 #define HWRM_VNIC_PLCMODES_CFG_INPUT_FLAGS_HDS_IPV6 \
24603 * When this bit is '1', the VNIC shall be configured
24604 * to enable Header-Data split for FCoE packets at the
24605 * beginning of FC payload.
24607 #define HWRM_VNIC_PLCMODES_CFG_INPUT_FLAGS_HDS_FCOE \
24610 * When this bit is '1', the VNIC shall be configured
24611 * to enable Header-Data split for RoCE packets at the
24612 * beginning of RoCE payload (after BTH/GRH headers).
24614 #define HWRM_VNIC_PLCMODES_CFG_INPUT_FLAGS_HDS_ROCE \
24618 * This bit must be '1' for the jumbo_thresh_valid field to be
24621 #define HWRM_VNIC_PLCMODES_CFG_INPUT_ENABLES_JUMBO_THRESH_VALID \
24624 * This bit must be '1' for the hds_offset_valid field to be
24627 #define HWRM_VNIC_PLCMODES_CFG_INPUT_ENABLES_HDS_OFFSET_VALID \
24630 * This bit must be '1' for the hds_threshold_valid field to be
24633 #define HWRM_VNIC_PLCMODES_CFG_INPUT_ENABLES_HDS_THRESHOLD_VALID \
24635 /* Logical vnic ID */
24638 * When jumbo placement algorithm is enabled, this value
24639 * is used to determine the threshold for jumbo placement.
24640 * Packets with length larger than this value will be
24641 * placed according to the jumbo placement algorithm.
24643 uint16_t jumbo_thresh;
24645 * This value is used to determine the offset into
24646 * packet buffer where the split data (payload) will be
24647 * placed according to one of HDS placement algorithm.
24649 * The lengths of packet buffers provided for split data
24650 * shall be larger than this value.
24652 uint16_t hds_offset;
24654 * When one of the HDS placement algorithm is enabled, this
24655 * value is used to determine the threshold for HDS
24657 * Packets with length larger than this value will be
24658 * placed according to the HDS placement algorithm.
24659 * This value shall be in multiple of 4 bytes.
24661 uint16_t hds_threshold;
24662 uint8_t unused_0[6];
24665 /* hwrm_vnic_plcmodes_cfg_output (size:128b/16B) */
24666 struct hwrm_vnic_plcmodes_cfg_output {
24667 /* The specific error status for the command. */
24668 uint16_t error_code;
24669 /* The HWRM command request type. */
24671 /* The sequence ID from the original command. */
24673 /* The length of the response data in number of bytes. */
24675 uint8_t unused_0[7];
24677 * This field is used in Output records to indicate that the output
24678 * is completely written to RAM. This field should be read as '1'
24679 * to indicate that the output has been completely written.
24680 * When writing a command completion or response to an internal processor,
24681 * the order of writes has to be such that this field is written last.
24686 /***************************
24687 * hwrm_vnic_plcmodes_qcfg *
24688 ***************************/
24691 /* hwrm_vnic_plcmodes_qcfg_input (size:192b/24B) */
24692 struct hwrm_vnic_plcmodes_qcfg_input {
24693 /* The HWRM command request type. */
24696 * The completion ring to send the completion event on. This should
24697 * be the NQ ID returned from the `nq_alloc` HWRM command.
24699 uint16_t cmpl_ring;
24701 * The sequence ID is used by the driver for tracking multiple
24702 * commands. This ID is treated as opaque data by the firmware and
24703 * the value is returned in the `hwrm_resp_hdr` upon completion.
24707 * The target ID of the command:
24708 * * 0x0-0xFFF8 - The function ID
24709 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
24710 * * 0xFFFD - Reserved for user-space HWRM interface
24713 uint16_t target_id;
24715 * A physical address pointer pointing to a host buffer that the
24716 * command's response data will be written. This can be either a host
24717 * physical address (HPA) or a guest physical address (GPA) and must
24718 * point to a physically contiguous block of memory.
24720 uint64_t resp_addr;
24721 /* Logical vnic ID */
24723 uint8_t unused_0[4];
24726 /* hwrm_vnic_plcmodes_qcfg_output (size:192b/24B) */
24727 struct hwrm_vnic_plcmodes_qcfg_output {
24728 /* The specific error status for the command. */
24729 uint16_t error_code;
24730 /* The HWRM command request type. */
24732 /* The sequence ID from the original command. */
24734 /* The length of the response data in number of bytes. */
24738 * When this bit is '1', the VNIC is configured to
24739 * use regular placement algorithm.
24741 #define HWRM_VNIC_PLCMODES_QCFG_OUTPUT_FLAGS_REGULAR_PLACEMENT \
24744 * When this bit is '1', the VNIC is configured to
24745 * use the jumbo placement algorithm.
24747 #define HWRM_VNIC_PLCMODES_QCFG_OUTPUT_FLAGS_JUMBO_PLACEMENT \
24750 * When this bit is '1', the VNIC is configured
24751 * to enable Header-Data split for IPv4 packets.
24753 #define HWRM_VNIC_PLCMODES_QCFG_OUTPUT_FLAGS_HDS_IPV4 \
24756 * When this bit is '1', the VNIC is configured
24757 * to enable Header-Data split for IPv6 packets.
24759 #define HWRM_VNIC_PLCMODES_QCFG_OUTPUT_FLAGS_HDS_IPV6 \
24762 * When this bit is '1', the VNIC is configured
24763 * to enable Header-Data split for FCoE packets.
24765 #define HWRM_VNIC_PLCMODES_QCFG_OUTPUT_FLAGS_HDS_FCOE \
24768 * When this bit is '1', the VNIC is configured
24769 * to enable Header-Data split for RoCE packets.
24771 #define HWRM_VNIC_PLCMODES_QCFG_OUTPUT_FLAGS_HDS_ROCE \
24774 * When this bit is '1', the VNIC is configured
24775 * to be the default VNIC of the requesting function.
24777 #define HWRM_VNIC_PLCMODES_QCFG_OUTPUT_FLAGS_DFLT_VNIC \
24780 * When jumbo placement algorithm is enabled, this value
24781 * is used to determine the threshold for jumbo placement.
24782 * Packets with length larger than this value will be
24783 * placed according to the jumbo placement algorithm.
24785 uint16_t jumbo_thresh;
24787 * This value is used to determine the offset into
24788 * packet buffer where the split data (payload) will be
24789 * placed according to one of HDS placement algorithm.
24791 * The lengths of packet buffers provided for split data
24792 * shall be larger than this value.
24794 uint16_t hds_offset;
24796 * When one of the HDS placement algorithm is enabled, this
24797 * value is used to determine the threshold for HDS
24799 * Packets with length larger than this value will be
24800 * placed according to the HDS placement algorithm.
24801 * This value shall be in multiple of 4 bytes.
24803 uint16_t hds_threshold;
24804 uint8_t unused_0[5];
24806 * This field is used in Output records to indicate that the output
24807 * is completely written to RAM. This field should be read as '1'
24808 * to indicate that the output has been completely written.
24809 * When writing a command completion or response to an internal processor,
24810 * the order of writes has to be such that this field is written last.
24815 /**********************************
24816 * hwrm_vnic_rss_cos_lb_ctx_alloc *
24817 **********************************/
24820 /* hwrm_vnic_rss_cos_lb_ctx_alloc_input (size:128b/16B) */
24821 struct hwrm_vnic_rss_cos_lb_ctx_alloc_input {
24822 /* The HWRM command request type. */
24825 * The completion ring to send the completion event on. This should
24826 * be the NQ ID returned from the `nq_alloc` HWRM command.
24828 uint16_t cmpl_ring;
24830 * The sequence ID is used by the driver for tracking multiple
24831 * commands. This ID is treated as opaque data by the firmware and
24832 * the value is returned in the `hwrm_resp_hdr` upon completion.
24836 * The target ID of the command:
24837 * * 0x0-0xFFF8 - The function ID
24838 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
24839 * * 0xFFFD - Reserved for user-space HWRM interface
24842 uint16_t target_id;
24844 * A physical address pointer pointing to a host buffer that the
24845 * command's response data will be written. This can be either a host
24846 * physical address (HPA) or a guest physical address (GPA) and must
24847 * point to a physically contiguous block of memory.
24849 uint64_t resp_addr;
24852 /* hwrm_vnic_rss_cos_lb_ctx_alloc_output (size:128b/16B) */
24853 struct hwrm_vnic_rss_cos_lb_ctx_alloc_output {
24854 /* The specific error status for the command. */
24855 uint16_t error_code;
24856 /* The HWRM command request type. */
24858 /* The sequence ID from the original command. */
24860 /* The length of the response data in number of bytes. */
24862 /* rss_cos_lb_ctx_id is 16 b */
24863 uint16_t rss_cos_lb_ctx_id;
24864 uint8_t unused_0[5];
24866 * This field is used in Output records to indicate that the output
24867 * is completely written to RAM. This field should be read as '1'
24868 * to indicate that the output has been completely written.
24869 * When writing a command completion or response to an internal processor,
24870 * the order of writes has to be such that this field is written last.
24875 /*********************************
24876 * hwrm_vnic_rss_cos_lb_ctx_free *
24877 *********************************/
24880 /* hwrm_vnic_rss_cos_lb_ctx_free_input (size:192b/24B) */
24881 struct hwrm_vnic_rss_cos_lb_ctx_free_input {
24882 /* The HWRM command request type. */
24885 * The completion ring to send the completion event on. This should
24886 * be the NQ ID returned from the `nq_alloc` HWRM command.
24888 uint16_t cmpl_ring;
24890 * The sequence ID is used by the driver for tracking multiple
24891 * commands. This ID is treated as opaque data by the firmware and
24892 * the value is returned in the `hwrm_resp_hdr` upon completion.
24896 * The target ID of the command:
24897 * * 0x0-0xFFF8 - The function ID
24898 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
24899 * * 0xFFFD - Reserved for user-space HWRM interface
24902 uint16_t target_id;
24904 * A physical address pointer pointing to a host buffer that the
24905 * command's response data will be written. This can be either a host
24906 * physical address (HPA) or a guest physical address (GPA) and must
24907 * point to a physically contiguous block of memory.
24909 uint64_t resp_addr;
24910 /* rss_cos_lb_ctx_id is 16 b */
24911 uint16_t rss_cos_lb_ctx_id;
24912 uint8_t unused_0[6];
24915 /* hwrm_vnic_rss_cos_lb_ctx_free_output (size:128b/16B) */
24916 struct hwrm_vnic_rss_cos_lb_ctx_free_output {
24917 /* The specific error status for the command. */
24918 uint16_t error_code;
24919 /* The HWRM command request type. */
24921 /* The sequence ID from the original command. */
24923 /* The length of the response data in number of bytes. */
24925 uint8_t unused_0[7];
24927 * This field is used in Output records to indicate that the output
24928 * is completely written to RAM. This field should be read as '1'
24929 * to indicate that the output has been completely written.
24930 * When writing a command completion or response to an internal processor,
24931 * the order of writes has to be such that this field is written last.
24936 /*******************
24937 * hwrm_ring_alloc *
24938 *******************/
24941 /* hwrm_ring_alloc_input (size:704b/88B) */
24942 struct hwrm_ring_alloc_input {
24943 /* The HWRM command request type. */
24946 * The completion ring to send the completion event on. This should
24947 * be the NQ ID returned from the `nq_alloc` HWRM command.
24949 uint16_t cmpl_ring;
24951 * The sequence ID is used by the driver for tracking multiple
24952 * commands. This ID is treated as opaque data by the firmware and
24953 * the value is returned in the `hwrm_resp_hdr` upon completion.
24957 * The target ID of the command:
24958 * * 0x0-0xFFF8 - The function ID
24959 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
24960 * * 0xFFFD - Reserved for user-space HWRM interface
24963 uint16_t target_id;
24965 * A physical address pointer pointing to a host buffer that the
24966 * command's response data will be written. This can be either a host
24967 * physical address (HPA) or a guest physical address (GPA) and must
24968 * point to a physically contiguous block of memory.
24970 uint64_t resp_addr;
24973 * This bit must be '1' for the ring_arb_cfg field to be
24976 #define HWRM_RING_ALLOC_INPUT_ENABLES_RING_ARB_CFG \
24979 * This bit must be '1' for the stat_ctx_id_valid field to be
24982 #define HWRM_RING_ALLOC_INPUT_ENABLES_STAT_CTX_ID_VALID \
24985 * This bit must be '1' for the max_bw_valid field to be
24988 #define HWRM_RING_ALLOC_INPUT_ENABLES_MAX_BW_VALID \
24991 * This bit must be '1' for the rx_ring_id field to be
24994 #define HWRM_RING_ALLOC_INPUT_ENABLES_RX_RING_ID_VALID \
24997 * This bit must be '1' for the nq_ring_id field to be
25000 #define HWRM_RING_ALLOC_INPUT_ENABLES_NQ_RING_ID_VALID \
25003 * This bit must be '1' for the rx_buf_size field to be
25006 #define HWRM_RING_ALLOC_INPUT_ENABLES_RX_BUF_SIZE_VALID \
25010 /* L2 Completion Ring (CR) */
25011 #define HWRM_RING_ALLOC_INPUT_RING_TYPE_L2_CMPL UINT32_C(0x0)
25013 #define HWRM_RING_ALLOC_INPUT_RING_TYPE_TX UINT32_C(0x1)
25015 #define HWRM_RING_ALLOC_INPUT_RING_TYPE_RX UINT32_C(0x2)
25016 /* RoCE Notification Completion Ring (ROCE_CR) */
25017 #define HWRM_RING_ALLOC_INPUT_RING_TYPE_ROCE_CMPL UINT32_C(0x3)
25018 /* RX Aggregation Ring */
25019 #define HWRM_RING_ALLOC_INPUT_RING_TYPE_RX_AGG UINT32_C(0x4)
25020 /* Notification Queue */
25021 #define HWRM_RING_ALLOC_INPUT_RING_TYPE_NQ UINT32_C(0x5)
25022 #define HWRM_RING_ALLOC_INPUT_RING_TYPE_LAST \
25023 HWRM_RING_ALLOC_INPUT_RING_TYPE_NQ
25025 /* Ring allocation flags. */
25028 * For Rx rings, the incoming packet data can be placed at either
25029 * a 0B or 2B offset from the start of the Rx packet buffer. When
25030 * '1', the received packet will be padded with 2B of zeros at the
25031 * front of the packet. Note that this flag is only used for
25032 * Rx rings and is ignored for all other rings included Rx
25033 * Aggregation rings.
25035 #define HWRM_RING_ALLOC_INPUT_FLAGS_RX_SOP_PAD UINT32_C(0x1)
25037 * This value is a pointer to the page table for the
25040 uint64_t page_tbl_addr;
25041 /* First Byte Offset of the first entry in the first page. */
25044 * Actual page size in 2^page_size. The supported range is increments
25045 * in powers of 2 from 16 bytes to 1GB.
25047 * Page size is 16 B.
25049 * Page size is 4 KB.
25051 * Page size is 8 KB.
25053 * Page size is 64 KB.
25055 * Page size is 2 MB.
25057 * Page size is 4 MB.
25059 * Page size is 1 GB.
25063 * This value indicates the depth of page table.
25064 * For this version of the specification, value other than 0 or
25065 * 1 shall be considered as an invalid value.
25066 * When the page_tbl_depth = 0, then it is treated as a
25067 * special case with the following.
25068 * 1. FBO and page size fields are not valid.
25069 * 2. page_tbl_addr is the physical address of the first
25070 * element of the ring.
25072 uint8_t page_tbl_depth;
25073 uint8_t unused_1[2];
25075 * Number of 16B units in the ring. Minimum size for
25076 * a ring is 16 16B entries.
25080 * Logical ring number for the ring to be allocated.
25081 * This value determines the position in the doorbell
25082 * area where the update to the ring will be made.
25084 * For completion rings, this value is also the MSI-X
25085 * vector number for the function the completion ring is
25088 uint16_t logical_id;
25090 * This field is used only when ring_type is a TX ring.
25091 * This value indicates what completion ring the TX ring
25092 * is associated with.
25094 uint16_t cmpl_ring_id;
25096 * This field is used only when ring_type is a TX ring.
25097 * This value indicates what CoS queue the TX ring
25098 * is associated with.
25102 * When allocating a Rx ring or Rx aggregation ring, this field
25103 * specifies the size of the buffer descriptors posted to the ring.
25105 uint16_t rx_buf_size;
25107 * When allocating an Rx aggregation ring, this field
25108 * specifies the associated Rx ring ID.
25110 uint16_t rx_ring_id;
25112 * When allocating a completion ring, this field
25113 * specifies the associated NQ ring ID.
25115 uint16_t nq_ring_id;
25117 * This field is used only when ring_type is a TX ring.
25118 * This field is used to configure arbitration related
25119 * parameters for a TX ring.
25121 uint16_t ring_arb_cfg;
25122 /* Arbitration policy used for the ring. */
25123 #define HWRM_RING_ALLOC_INPUT_RING_ARB_CFG_ARB_POLICY_MASK \
25125 #define HWRM_RING_ALLOC_INPUT_RING_ARB_CFG_ARB_POLICY_SFT 0
25127 * Use strict priority for the TX ring.
25128 * Priority value is specified in arb_policy_param
25130 #define HWRM_RING_ALLOC_INPUT_RING_ARB_CFG_ARB_POLICY_SP \
25133 * Use weighted fair queue arbitration for the TX ring.
25134 * Weight is specified in arb_policy_param
25136 #define HWRM_RING_ALLOC_INPUT_RING_ARB_CFG_ARB_POLICY_WFQ \
25138 #define HWRM_RING_ALLOC_INPUT_RING_ARB_CFG_ARB_POLICY_LAST \
25139 HWRM_RING_ALLOC_INPUT_RING_ARB_CFG_ARB_POLICY_WFQ
25140 /* Reserved field. */
25141 #define HWRM_RING_ALLOC_INPUT_RING_ARB_CFG_RSVD_MASK \
25143 #define HWRM_RING_ALLOC_INPUT_RING_ARB_CFG_RSVD_SFT 4
25145 * Arbitration policy specific parameter.
25146 * # For strict priority arbitration policy, this field
25147 * represents a priority value. If set to 0, then the priority
25148 * is not specified and the HWRM is allowed to select
25149 * any priority for this TX ring.
25150 * # For weighted fair queue arbitration policy, this field
25151 * represents a weight value. If set to 0, then the weight
25152 * is not specified and the HWRM is allowed to select
25153 * any weight for this TX ring.
25155 #define HWRM_RING_ALLOC_INPUT_RING_ARB_CFG_ARB_POLICY_PARAM_MASK \
25157 #define HWRM_RING_ALLOC_INPUT_RING_ARB_CFG_ARB_POLICY_PARAM_SFT 8
25160 * This field is reserved for the future use.
25161 * It shall be set to 0.
25163 uint32_t reserved3;
25165 * This field is used only when ring_type is a TX ring.
25166 * This input indicates what statistics context this ring
25167 * should be associated with.
25169 uint32_t stat_ctx_id;
25171 * This field is reserved for the future use.
25172 * It shall be set to 0.
25174 uint32_t reserved4;
25176 * This field is used only when ring_type is a TX ring
25177 * to specify maximum BW allocated to the TX ring.
25178 * The HWRM will translate this value into byte counter and
25179 * time interval used for this ring inside the device.
25182 /* The bandwidth value. */
25183 #define HWRM_RING_ALLOC_INPUT_MAX_BW_BW_VALUE_MASK \
25184 UINT32_C(0xfffffff)
25185 #define HWRM_RING_ALLOC_INPUT_MAX_BW_BW_VALUE_SFT 0
25186 /* The granularity of the value (bits or bytes). */
25187 #define HWRM_RING_ALLOC_INPUT_MAX_BW_SCALE \
25188 UINT32_C(0x10000000)
25189 /* Value is in bits. */
25190 #define HWRM_RING_ALLOC_INPUT_MAX_BW_SCALE_BITS \
25191 (UINT32_C(0x0) << 28)
25192 /* Value is in bytes. */
25193 #define HWRM_RING_ALLOC_INPUT_MAX_BW_SCALE_BYTES \
25194 (UINT32_C(0x1) << 28)
25195 #define HWRM_RING_ALLOC_INPUT_MAX_BW_SCALE_LAST \
25196 HWRM_RING_ALLOC_INPUT_MAX_BW_SCALE_BYTES
25197 /* bw_value_unit is 3 b */
25198 #define HWRM_RING_ALLOC_INPUT_MAX_BW_BW_VALUE_UNIT_MASK \
25199 UINT32_C(0xe0000000)
25200 #define HWRM_RING_ALLOC_INPUT_MAX_BW_BW_VALUE_UNIT_SFT 29
25201 /* Value is in Mb or MB (base 10). */
25202 #define HWRM_RING_ALLOC_INPUT_MAX_BW_BW_VALUE_UNIT_MEGA \
25203 (UINT32_C(0x0) << 29)
25204 /* Value is in Kb or KB (base 10). */
25205 #define HWRM_RING_ALLOC_INPUT_MAX_BW_BW_VALUE_UNIT_KILO \
25206 (UINT32_C(0x2) << 29)
25207 /* Value is in bits or bytes. */
25208 #define HWRM_RING_ALLOC_INPUT_MAX_BW_BW_VALUE_UNIT_BASE \
25209 (UINT32_C(0x4) << 29)
25210 /* Value is in Gb or GB (base 10). */
25211 #define HWRM_RING_ALLOC_INPUT_MAX_BW_BW_VALUE_UNIT_GIGA \
25212 (UINT32_C(0x6) << 29)
25213 /* Value is in 1/100th of a percentage of total bandwidth. */
25214 #define HWRM_RING_ALLOC_INPUT_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 \
25215 (UINT32_C(0x1) << 29)
25217 #define HWRM_RING_ALLOC_INPUT_MAX_BW_BW_VALUE_UNIT_INVALID \
25218 (UINT32_C(0x7) << 29)
25219 #define HWRM_RING_ALLOC_INPUT_MAX_BW_BW_VALUE_UNIT_LAST \
25220 HWRM_RING_ALLOC_INPUT_MAX_BW_BW_VALUE_UNIT_INVALID
25222 * This field is used only when ring_type is a Completion ring.
25223 * This value indicates what interrupt mode should be used
25224 * on this completion ring.
25225 * Note: In the legacy interrupt mode, no more than 16
25226 * completion rings are allowed.
25230 #define HWRM_RING_ALLOC_INPUT_INT_MODE_LEGACY UINT32_C(0x0)
25232 #define HWRM_RING_ALLOC_INPUT_INT_MODE_RSVD UINT32_C(0x1)
25234 #define HWRM_RING_ALLOC_INPUT_INT_MODE_MSIX UINT32_C(0x2)
25235 /* No Interrupt - Polled mode */
25236 #define HWRM_RING_ALLOC_INPUT_INT_MODE_POLL UINT32_C(0x3)
25237 #define HWRM_RING_ALLOC_INPUT_INT_MODE_LAST \
25238 HWRM_RING_ALLOC_INPUT_INT_MODE_POLL
25239 uint8_t unused_4[3];
25241 * The cq_handle is specified when allocating a completion ring. For
25242 * devices that support NQs, this cq_handle will be included in the
25243 * NQE to specify which CQ should be read to retrieve the completion
25246 uint64_t cq_handle;
25249 /* hwrm_ring_alloc_output (size:128b/16B) */
25250 struct hwrm_ring_alloc_output {
25251 /* The specific error status for the command. */
25252 uint16_t error_code;
25253 /* The HWRM command request type. */
25255 /* The sequence ID from the original command. */
25257 /* The length of the response data in number of bytes. */
25260 * Physical number of ring allocated.
25261 * This value shall be unique for a ring type.
25264 /* Logical number of ring allocated. */
25265 uint16_t logical_ring_id;
25266 uint8_t unused_0[3];
25268 * This field is used in Output records to indicate that the output
25269 * is completely written to RAM. This field should be read as '1'
25270 * to indicate that the output has been completely written.
25271 * When writing a command completion or response to an internal processor,
25272 * the order of writes has to be such that this field is written last.
25277 /******************
25279 ******************/
25282 /* hwrm_ring_free_input (size:192b/24B) */
25283 struct hwrm_ring_free_input {
25284 /* The HWRM command request type. */
25287 * The completion ring to send the completion event on. This should
25288 * be the NQ ID returned from the `nq_alloc` HWRM command.
25290 uint16_t cmpl_ring;
25292 * The sequence ID is used by the driver for tracking multiple
25293 * commands. This ID is treated as opaque data by the firmware and
25294 * the value is returned in the `hwrm_resp_hdr` upon completion.
25298 * The target ID of the command:
25299 * * 0x0-0xFFF8 - The function ID
25300 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
25301 * * 0xFFFD - Reserved for user-space HWRM interface
25304 uint16_t target_id;
25306 * A physical address pointer pointing to a host buffer that the
25307 * command's response data will be written. This can be either a host
25308 * physical address (HPA) or a guest physical address (GPA) and must
25309 * point to a physically contiguous block of memory.
25311 uint64_t resp_addr;
25314 /* L2 Completion Ring (CR) */
25315 #define HWRM_RING_FREE_INPUT_RING_TYPE_L2_CMPL UINT32_C(0x0)
25317 #define HWRM_RING_FREE_INPUT_RING_TYPE_TX UINT32_C(0x1)
25319 #define HWRM_RING_FREE_INPUT_RING_TYPE_RX UINT32_C(0x2)
25320 /* RoCE Notification Completion Ring (ROCE_CR) */
25321 #define HWRM_RING_FREE_INPUT_RING_TYPE_ROCE_CMPL UINT32_C(0x3)
25322 /* RX Aggregation Ring */
25323 #define HWRM_RING_FREE_INPUT_RING_TYPE_RX_AGG UINT32_C(0x4)
25324 /* Notification Queue */
25325 #define HWRM_RING_FREE_INPUT_RING_TYPE_NQ UINT32_C(0x5)
25326 #define HWRM_RING_FREE_INPUT_RING_TYPE_LAST \
25327 HWRM_RING_FREE_INPUT_RING_TYPE_NQ
25329 /* Physical number of ring allocated. */
25331 uint8_t unused_1[4];
25334 /* hwrm_ring_free_output (size:128b/16B) */
25335 struct hwrm_ring_free_output {
25336 /* The specific error status for the command. */
25337 uint16_t error_code;
25338 /* The HWRM command request type. */
25340 /* The sequence ID from the original command. */
25342 /* The length of the response data in number of bytes. */
25344 uint8_t unused_0[7];
25346 * This field is used in Output records to indicate that the output
25347 * is completely written to RAM. This field should be read as '1'
25348 * to indicate that the output has been completely written.
25349 * When writing a command completion or response to an internal processor,
25350 * the order of writes has to be such that this field is written last.
25355 /*******************
25356 * hwrm_ring_reset *
25357 *******************/
25360 /* hwrm_ring_reset_input (size:192b/24B) */
25361 struct hwrm_ring_reset_input {
25362 /* The HWRM command request type. */
25365 * The completion ring to send the completion event on. This should
25366 * be the NQ ID returned from the `nq_alloc` HWRM command.
25368 uint16_t cmpl_ring;
25370 * The sequence ID is used by the driver for tracking multiple
25371 * commands. This ID is treated as opaque data by the firmware and
25372 * the value is returned in the `hwrm_resp_hdr` upon completion.
25376 * The target ID of the command:
25377 * * 0x0-0xFFF8 - The function ID
25378 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
25379 * * 0xFFFD - Reserved for user-space HWRM interface
25382 uint16_t target_id;
25384 * A physical address pointer pointing to a host buffer that the
25385 * command's response data will be written. This can be either a host
25386 * physical address (HPA) or a guest physical address (GPA) and must
25387 * point to a physically contiguous block of memory.
25389 uint64_t resp_addr;
25392 /* L2 Completion Ring (CR) */
25393 #define HWRM_RING_RESET_INPUT_RING_TYPE_L2_CMPL UINT32_C(0x0)
25395 #define HWRM_RING_RESET_INPUT_RING_TYPE_TX UINT32_C(0x1)
25397 #define HWRM_RING_RESET_INPUT_RING_TYPE_RX UINT32_C(0x2)
25398 /* RoCE Notification Completion Ring (ROCE_CR) */
25399 #define HWRM_RING_RESET_INPUT_RING_TYPE_ROCE_CMPL UINT32_C(0x3)
25400 #define HWRM_RING_RESET_INPUT_RING_TYPE_LAST \
25401 HWRM_RING_RESET_INPUT_RING_TYPE_ROCE_CMPL
25403 /* Physical number of the ring. */
25405 uint8_t unused_1[4];
25408 /* hwrm_ring_reset_output (size:128b/16B) */
25409 struct hwrm_ring_reset_output {
25410 /* The specific error status for the command. */
25411 uint16_t error_code;
25412 /* The HWRM command request type. */
25414 /* The sequence ID from the original command. */
25416 /* The length of the response data in number of bytes. */
25418 uint8_t unused_0[4];
25419 /* Position of consumer index after ring reset completes. */
25420 uint8_t consumer_idx[3];
25422 * This field is used in Output records to indicate that the output
25423 * is completely written to RAM. This field should be read as '1'
25424 * to indicate that the output has been completely written.
25425 * When writing a command completion or response to an internal processor,
25426 * the order of writes has to be such that this field is written last.
25431 /**************************
25432 * hwrm_ring_aggint_qcaps *
25433 **************************/
25436 /* hwrm_ring_aggint_qcaps_input (size:128b/16B) */
25437 struct hwrm_ring_aggint_qcaps_input {
25438 /* The HWRM command request type. */
25441 * The completion ring to send the completion event on. This should
25442 * be the NQ ID returned from the `nq_alloc` HWRM command.
25444 uint16_t cmpl_ring;
25446 * The sequence ID is used by the driver for tracking multiple
25447 * commands. This ID is treated as opaque data by the firmware and
25448 * the value is returned in the `hwrm_resp_hdr` upon completion.
25452 * The target ID of the command:
25453 * * 0x0-0xFFF8 - The function ID
25454 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
25455 * * 0xFFFD - Reserved for user-space HWRM interface
25458 uint16_t target_id;
25460 * A physical address pointer pointing to a host buffer that the
25461 * command's response data will be written. This can be either a host
25462 * physical address (HPA) or a guest physical address (GPA) and must
25463 * point to a physically contiguous block of memory.
25465 uint64_t resp_addr;
25468 /* hwrm_ring_aggint_qcaps_output (size:384b/48B) */
25469 struct hwrm_ring_aggint_qcaps_output {
25470 /* The specific error status for the command. */
25471 uint16_t error_code;
25472 /* The HWRM command request type. */
25474 /* The sequence ID from the original command. */
25476 /* The length of the response data in number of bytes. */
25478 uint32_t cmpl_params;
25480 * When this bit is set to '1', int_lat_tmr_min can be configured
25481 * on completion rings.
25483 #define HWRM_RING_AGGINT_QCAPS_OUTPUT_CMPL_PARAMS_INT_LAT_TMR_MIN \
25486 * When this bit is set to '1', int_lat_tmr_max can be configured
25487 * on completion rings.
25489 #define HWRM_RING_AGGINT_QCAPS_OUTPUT_CMPL_PARAMS_INT_LAT_TMR_MAX \
25492 * When this bit is set to '1', timer_reset can be enabled
25493 * on completion rings.
25495 #define HWRM_RING_AGGINT_QCAPS_OUTPUT_CMPL_PARAMS_TIMER_RESET \
25498 * When this bit is set to '1', ring_idle can be enabled
25499 * on completion rings.
25501 #define HWRM_RING_AGGINT_QCAPS_OUTPUT_CMPL_PARAMS_RING_IDLE \
25504 * When this bit is set to '1', num_cmpl_dma_aggr can be configured
25505 * on completion rings.
25507 #define HWRM_RING_AGGINT_QCAPS_OUTPUT_CMPL_PARAMS_NUM_CMPL_DMA_AGGR \
25510 * When this bit is set to '1', num_cmpl_dma_aggr_during_int can be configured
25511 * on completion rings.
25513 #define HWRM_RING_AGGINT_QCAPS_OUTPUT_CMPL_PARAMS_NUM_CMPL_DMA_AGGR_DURING_INT \
25516 * When this bit is set to '1', cmpl_aggr_dma_tmr can be configured
25517 * on completion rings.
25519 #define HWRM_RING_AGGINT_QCAPS_OUTPUT_CMPL_PARAMS_CMPL_AGGR_DMA_TMR \
25522 * When this bit is set to '1', cmpl_aggr_dma_tmr_during_int can be configured
25523 * on completion rings.
25525 #define HWRM_RING_AGGINT_QCAPS_OUTPUT_CMPL_PARAMS_CMPL_AGGR_DMA_TMR_DURING_INT \
25528 * When this bit is set to '1', num_cmpl_aggr_int can be configured
25529 * on completion rings.
25531 #define HWRM_RING_AGGINT_QCAPS_OUTPUT_CMPL_PARAMS_NUM_CMPL_AGGR_INT \
25533 uint32_t nq_params;
25535 * When this bit is set to '1', int_lat_tmr_min can be configured
25536 * on notification queues.
25538 #define HWRM_RING_AGGINT_QCAPS_OUTPUT_NQ_PARAMS_INT_LAT_TMR_MIN \
25540 /* Minimum value for num_cmpl_dma_aggr */
25541 uint16_t num_cmpl_dma_aggr_min;
25542 /* Maximum value for num_cmpl_dma_aggr */
25543 uint16_t num_cmpl_dma_aggr_max;
25544 /* Minimum value for num_cmpl_dma_aggr_during_int */
25545 uint16_t num_cmpl_dma_aggr_during_int_min;
25546 /* Maximum value for num_cmpl_dma_aggr_during_int */
25547 uint16_t num_cmpl_dma_aggr_during_int_max;
25548 /* Minimum value for cmpl_aggr_dma_tmr */
25549 uint16_t cmpl_aggr_dma_tmr_min;
25550 /* Maximum value for cmpl_aggr_dma_tmr */
25551 uint16_t cmpl_aggr_dma_tmr_max;
25552 /* Minimum value for cmpl_aggr_dma_tmr_during_int */
25553 uint16_t cmpl_aggr_dma_tmr_during_int_min;
25554 /* Maximum value for cmpl_aggr_dma_tmr_during_int */
25555 uint16_t cmpl_aggr_dma_tmr_during_int_max;
25556 /* Minimum value for int_lat_tmr_min */
25557 uint16_t int_lat_tmr_min_min;
25558 /* Maximum value for int_lat_tmr_min */
25559 uint16_t int_lat_tmr_min_max;
25560 /* Minimum value for int_lat_tmr_max */
25561 uint16_t int_lat_tmr_max_min;
25562 /* Maximum value for int_lat_tmr_max */
25563 uint16_t int_lat_tmr_max_max;
25564 /* Minimum value for num_cmpl_aggr_int */
25565 uint16_t num_cmpl_aggr_int_min;
25566 /* Maximum value for num_cmpl_aggr_int */
25567 uint16_t num_cmpl_aggr_int_max;
25568 /* The units for timer parameters, in nanoseconds. */
25569 uint16_t timer_units;
25570 uint8_t unused_0[1];
25572 * This field is used in Output records to indicate that the output
25573 * is completely written to RAM. This field should be read as '1'
25574 * to indicate that the output has been completely written.
25575 * When writing a command completion or response to an internal processor,
25576 * the order of writes has to be such that this field is written last.
25581 /**************************************
25582 * hwrm_ring_cmpl_ring_qaggint_params *
25583 **************************************/
25586 /* hwrm_ring_cmpl_ring_qaggint_params_input (size:192b/24B) */
25587 struct hwrm_ring_cmpl_ring_qaggint_params_input {
25588 /* The HWRM command request type. */
25591 * The completion ring to send the completion event on. This should
25592 * be the NQ ID returned from the `nq_alloc` HWRM command.
25594 uint16_t cmpl_ring;
25596 * The sequence ID is used by the driver for tracking multiple
25597 * commands. This ID is treated as opaque data by the firmware and
25598 * the value is returned in the `hwrm_resp_hdr` upon completion.
25602 * The target ID of the command:
25603 * * 0x0-0xFFF8 - The function ID
25604 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
25605 * * 0xFFFD - Reserved for user-space HWRM interface
25608 uint16_t target_id;
25610 * A physical address pointer pointing to a host buffer that the
25611 * command's response data will be written. This can be either a host
25612 * physical address (HPA) or a guest physical address (GPA) and must
25613 * point to a physically contiguous block of memory.
25615 uint64_t resp_addr;
25616 /* Physical number of completion ring. */
25618 uint8_t unused_0[6];
25621 /* hwrm_ring_cmpl_ring_qaggint_params_output (size:256b/32B) */
25622 struct hwrm_ring_cmpl_ring_qaggint_params_output {
25623 /* The specific error status for the command. */
25624 uint16_t error_code;
25625 /* The HWRM command request type. */
25627 /* The sequence ID from the original command. */
25629 /* The length of the response data in number of bytes. */
25633 * When this bit is set to '1', interrupt max
25634 * timer is reset whenever a completion is received.
25636 #define HWRM_RING_CMPL_RING_QAGGINT_PARAMS_OUTPUT_FLAGS_TIMER_RESET \
25639 * When this bit is set to '1', ring idle mode
25640 * aggregation will be enabled.
25642 #define HWRM_RING_CMPL_RING_QAGGINT_PARAMS_OUTPUT_FLAGS_RING_IDLE \
25645 * Number of completions to aggregate before DMA
25646 * during the normal mode.
25648 uint16_t num_cmpl_dma_aggr;
25650 * Number of completions to aggregate before DMA
25651 * during the interrupt mode.
25653 uint16_t num_cmpl_dma_aggr_during_int;
25655 * Timer in unit of 80-nsec used to aggregate completions before
25656 * DMA during the normal mode (not in interrupt mode).
25658 uint16_t cmpl_aggr_dma_tmr;
25660 * Timer in unit of 80-nsec used to aggregate completions before
25661 * DMA during the interrupt mode.
25663 uint16_t cmpl_aggr_dma_tmr_during_int;
25664 /* Minimum time (in unit of 80-nsec) between two interrupts. */
25665 uint16_t int_lat_tmr_min;
25667 * Maximum wait time (in unit of 80-nsec) spent aggregating
25668 * completions before signaling the interrupt after the
25669 * interrupt is enabled.
25671 uint16_t int_lat_tmr_max;
25673 * Minimum number of completions aggregated before signaling
25676 uint16_t num_cmpl_aggr_int;
25677 uint8_t unused_0[7];
25679 * This field is used in Output records to indicate that the output
25680 * is completely written to RAM. This field should be read as '1'
25681 * to indicate that the output has been completely written.
25682 * When writing a command completion or response to an internal processor,
25683 * the order of writes has to be such that this field is written last.
25688 /*****************************************
25689 * hwrm_ring_cmpl_ring_cfg_aggint_params *
25690 *****************************************/
25693 /* hwrm_ring_cmpl_ring_cfg_aggint_params_input (size:320b/40B) */
25694 struct hwrm_ring_cmpl_ring_cfg_aggint_params_input {
25695 /* The HWRM command request type. */
25698 * The completion ring to send the completion event on. This should
25699 * be the NQ ID returned from the `nq_alloc` HWRM command.
25701 uint16_t cmpl_ring;
25703 * The sequence ID is used by the driver for tracking multiple
25704 * commands. This ID is treated as opaque data by the firmware and
25705 * the value is returned in the `hwrm_resp_hdr` upon completion.
25709 * The target ID of the command:
25710 * * 0x0-0xFFF8 - The function ID
25711 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
25712 * * 0xFFFD - Reserved for user-space HWRM interface
25715 uint16_t target_id;
25717 * A physical address pointer pointing to a host buffer that the
25718 * command's response data will be written. This can be either a host
25719 * physical address (HPA) or a guest physical address (GPA) and must
25720 * point to a physically contiguous block of memory.
25722 uint64_t resp_addr;
25723 /* Physical number of completion ring. */
25727 * When this bit is set to '1', interrupt latency max
25728 * timer is reset whenever a completion is received.
25730 #define HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_FLAGS_TIMER_RESET \
25733 * When this bit is set to '1', ring idle mode
25734 * aggregation will be enabled.
25736 #define HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_FLAGS_RING_IDLE \
25739 * Set this flag to 1 when configuring parameters on a
25740 * notification queue. Set this flag to 0 when configuring
25741 * parameters on a completion queue.
25743 #define HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_FLAGS_IS_NQ \
25746 * Number of completions to aggregate before DMA
25747 * during the normal mode.
25749 uint16_t num_cmpl_dma_aggr;
25751 * Number of completions to aggregate before DMA
25752 * during the interrupt mode.
25754 uint16_t num_cmpl_dma_aggr_during_int;
25756 * Timer in unit of 80-nsec used to aggregate completions before
25757 * DMA during the normal mode (not in interrupt mode).
25759 uint16_t cmpl_aggr_dma_tmr;
25761 * Timer in unit of 80-nsec used to aggregate completions before
25762 * DMA during the interrupt mode.
25764 uint16_t cmpl_aggr_dma_tmr_during_int;
25765 /* Minimum time (in unit of 80-nsec) between two interrupts. */
25766 uint16_t int_lat_tmr_min;
25768 * Maximum wait time (in unit of 80-nsec) spent aggregating
25769 * cmpls before signaling the interrupt after the
25770 * interrupt is enabled.
25772 uint16_t int_lat_tmr_max;
25774 * Minimum number of completions aggregated before signaling
25777 uint16_t num_cmpl_aggr_int;
25779 * Bitfield that indicates which parameters are to be applied. Only
25780 * required when configuring devices with notification queues, and
25781 * used in that case to set certain parameters on completion queues
25782 * and others on notification queues.
25786 * This bit must be '1' for the num_cmpl_dma_aggr field to be
25789 #define HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_ENABLES_NUM_CMPL_DMA_AGGR \
25792 * This bit must be '1' for the num_cmpl_dma_aggr_during_int field to be
25795 #define HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_ENABLES_NUM_CMPL_DMA_AGGR_DURING_INT \
25798 * This bit must be '1' for the cmpl_aggr_dma_tmr field to be
25801 #define HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_ENABLES_CMPL_AGGR_DMA_TMR \
25804 * This bit must be '1' for the int_lat_tmr_min field to be
25807 #define HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_ENABLES_INT_LAT_TMR_MIN \
25810 * This bit must be '1' for the int_lat_tmr_max field to be
25813 #define HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_ENABLES_INT_LAT_TMR_MAX \
25816 * This bit must be '1' for the num_cmpl_aggr_int field to be
25819 #define HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_ENABLES_NUM_CMPL_AGGR_INT \
25821 uint8_t unused_0[4];
25824 /* hwrm_ring_cmpl_ring_cfg_aggint_params_output (size:128b/16B) */
25825 struct hwrm_ring_cmpl_ring_cfg_aggint_params_output {
25826 /* The specific error status for the command. */
25827 uint16_t error_code;
25828 /* The HWRM command request type. */
25830 /* The sequence ID from the original command. */
25832 /* The length of the response data in number of bytes. */
25834 uint8_t unused_0[7];
25836 * This field is used in Output records to indicate that the output
25837 * is completely written to RAM. This field should be read as '1'
25838 * to indicate that the output has been completely written.
25839 * When writing a command completion or response to an internal processor,
25840 * the order of writes has to be such that this field is written last.
25845 /***********************
25846 * hwrm_ring_grp_alloc *
25847 ***********************/
25850 /* hwrm_ring_grp_alloc_input (size:192b/24B) */
25851 struct hwrm_ring_grp_alloc_input {
25852 /* The HWRM command request type. */
25855 * The completion ring to send the completion event on. This should
25856 * be the NQ ID returned from the `nq_alloc` HWRM command.
25858 uint16_t cmpl_ring;
25860 * The sequence ID is used by the driver for tracking multiple
25861 * commands. This ID is treated as opaque data by the firmware and
25862 * the value is returned in the `hwrm_resp_hdr` upon completion.
25866 * The target ID of the command:
25867 * * 0x0-0xFFF8 - The function ID
25868 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
25869 * * 0xFFFD - Reserved for user-space HWRM interface
25872 uint16_t target_id;
25874 * A physical address pointer pointing to a host buffer that the
25875 * command's response data will be written. This can be either a host
25876 * physical address (HPA) or a guest physical address (GPA) and must
25877 * point to a physically contiguous block of memory.
25879 uint64_t resp_addr;
25881 * This value identifies the CR associated with the ring
25886 * This value identifies the main RR associated with the ring
25891 * This value identifies the aggregation RR associated with
25892 * the ring group. If this value is 0xFF... (All Fs), then no
25893 * Aggregation ring will be set.
25897 * This value identifies the statistics context associated
25898 * with the ring group.
25903 /* hwrm_ring_grp_alloc_output (size:128b/16B) */
25904 struct hwrm_ring_grp_alloc_output {
25905 /* The specific error status for the command. */
25906 uint16_t error_code;
25907 /* The HWRM command request type. */
25909 /* The sequence ID from the original command. */
25911 /* The length of the response data in number of bytes. */
25914 * This is the ring group ID value. Use this value to program
25915 * the default ring group for the VNIC or as table entries
25916 * in an RSS/COS context.
25918 uint32_t ring_group_id;
25919 uint8_t unused_0[3];
25921 * This field is used in Output records to indicate that the output
25922 * is completely written to RAM. This field should be read as '1'
25923 * to indicate that the output has been completely written.
25924 * When writing a command completion or response to an internal processor,
25925 * the order of writes has to be such that this field is written last.
25930 /**********************
25931 * hwrm_ring_grp_free *
25932 **********************/
25935 /* hwrm_ring_grp_free_input (size:192b/24B) */
25936 struct hwrm_ring_grp_free_input {
25937 /* The HWRM command request type. */
25940 * The completion ring to send the completion event on. This should
25941 * be the NQ ID returned from the `nq_alloc` HWRM command.
25943 uint16_t cmpl_ring;
25945 * The sequence ID is used by the driver for tracking multiple
25946 * commands. This ID is treated as opaque data by the firmware and
25947 * the value is returned in the `hwrm_resp_hdr` upon completion.
25951 * The target ID of the command:
25952 * * 0x0-0xFFF8 - The function ID
25953 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
25954 * * 0xFFFD - Reserved for user-space HWRM interface
25957 uint16_t target_id;
25959 * A physical address pointer pointing to a host buffer that the
25960 * command's response data will be written. This can be either a host
25961 * physical address (HPA) or a guest physical address (GPA) and must
25962 * point to a physically contiguous block of memory.
25964 uint64_t resp_addr;
25965 /* This is the ring group ID value. */
25966 uint32_t ring_group_id;
25967 uint8_t unused_0[4];
25970 /* hwrm_ring_grp_free_output (size:128b/16B) */
25971 struct hwrm_ring_grp_free_output {
25972 /* The specific error status for the command. */
25973 uint16_t error_code;
25974 /* The HWRM command request type. */
25976 /* The sequence ID from the original command. */
25978 /* The length of the response data in number of bytes. */
25980 uint8_t unused_0[7];
25982 * This field is used in Output records to indicate that the output
25983 * is completely written to RAM. This field should be read as '1'
25984 * to indicate that the output has been completely written.
25985 * When writing a command completion or response to an internal processor,
25986 * the order of writes has to be such that this field is written last.
25991 * special reserved flow ID to identify per function default
25992 * flows for vSwitch offload
25994 #define DEFAULT_FLOW_ID 0xFFFFFFFFUL
25996 * special reserved flow ID to identify per function RoCEv1
25999 #define ROCEV1_FLOW_ID 0xFFFFFFFEUL
26001 * special reserved flow ID to identify per function RoCEv2
26004 #define ROCEV2_FLOW_ID 0xFFFFFFFDUL
26006 * special reserved flow ID to identify per function RoCEv2
26009 #define ROCEV2_CNP_FLOW_ID 0xFFFFFFFCUL
26011 /****************************
26012 * hwrm_cfa_l2_filter_alloc *
26013 ****************************/
26016 /* hwrm_cfa_l2_filter_alloc_input (size:768b/96B) */
26017 struct hwrm_cfa_l2_filter_alloc_input {
26018 /* The HWRM command request type. */
26021 * The completion ring to send the completion event on. This should
26022 * be the NQ ID returned from the `nq_alloc` HWRM command.
26024 uint16_t cmpl_ring;
26026 * The sequence ID is used by the driver for tracking multiple
26027 * commands. This ID is treated as opaque data by the firmware and
26028 * the value is returned in the `hwrm_resp_hdr` upon completion.
26032 * The target ID of the command:
26033 * * 0x0-0xFFF8 - The function ID
26034 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
26035 * * 0xFFFD - Reserved for user-space HWRM interface
26038 uint16_t target_id;
26040 * A physical address pointer pointing to a host buffer that the
26041 * command's response data will be written. This can be either a host
26042 * physical address (HPA) or a guest physical address (GPA) and must
26043 * point to a physically contiguous block of memory.
26045 uint64_t resp_addr;
26048 * Enumeration denoting the RX, TX type of the resource.
26049 * This enumeration is used for resources that are similar for both
26050 * TX and RX paths of the chip.
26052 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_PATH \
26055 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_PATH_TX \
26058 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_PATH_RX \
26060 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_PATH_LAST \
26061 HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_PATH_RX
26062 /* Setting of this flag indicates the applicability to the loopback path. */
26063 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_LOOPBACK \
26066 * Setting of this flag indicates drop action. If this flag is not set,
26067 * then it should be considered accept action.
26069 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_DROP \
26072 * If this flag is set, all t_l2_* fields are invalid
26073 * and they should not be specified.
26074 * If this flag is set, then l2_* fields refer to
26075 * fields of outermost L2 header.
26077 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_OUTERMOST \
26080 * Enumeration denoting NO_ROCE_L2 to support old drivers.
26081 * New driver L2 for only L2 traffic, ROCE for roce and l2 traffic
26083 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_TRAFFIC_MASK \
26085 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_TRAFFIC_SFT 4
26086 /* To support old drivers */
26087 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_TRAFFIC_NO_ROCE_L2 \
26088 (UINT32_C(0x0) << 4)
26089 /* Only L2 traffic */
26090 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_TRAFFIC_L2 \
26091 (UINT32_C(0x1) << 4)
26092 /* Roce & L2 traffic */
26093 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_TRAFFIC_ROCE \
26094 (UINT32_C(0x2) << 4)
26095 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_TRAFFIC_LAST \
26096 HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_TRAFFIC_ROCE
26098 * Setting of this flag indicates that no XDP filter is created with
26100 * 0 - legacy behavior, XDP filter is created with L2 filter
26101 * 1 - XDP filter won't be created with L2 filter
26103 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_XDP_DISABLE \
26106 * Setting this flag to 1 indicate the L2 fields in this command
26107 * pertain to source fields. Setting this flag to 0 indicate the
26108 * L2 fields in this command pertain to the destination fields
26109 * and this is the default/legacy behavior.
26111 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_SOURCE_VALID \
26115 * This bit must be '1' for the l2_addr field to be
26118 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_ADDR \
26121 * This bit must be '1' for the l2_addr_mask field to be
26124 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_ADDR_MASK \
26127 * This bit must be '1' for the l2_ovlan field to be
26130 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_OVLAN \
26133 * This bit must be '1' for the l2_ovlan_mask field to be
26136 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_OVLAN_MASK \
26139 * This bit must be '1' for the l2_ivlan field to be
26142 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN \
26145 * This bit must be '1' for the l2_ivlan_mask field to be
26148 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN_MASK \
26151 * This bit must be '1' for the t_l2_addr field to be
26154 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_T_L2_ADDR \
26157 * This bit must be '1' for the t_l2_addr_mask field to be
26160 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_T_L2_ADDR_MASK \
26163 * This bit must be '1' for the t_l2_ovlan field to be
26166 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_T_L2_OVLAN \
26169 * This bit must be '1' for the t_l2_ovlan_mask field to be
26172 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_T_L2_OVLAN_MASK \
26175 * This bit must be '1' for the t_l2_ivlan field to be
26178 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_T_L2_IVLAN \
26181 * This bit must be '1' for the t_l2_ivlan_mask field to be
26184 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_T_L2_IVLAN_MASK \
26187 * This bit must be '1' for the src_type field to be
26190 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_SRC_TYPE \
26193 * This bit must be '1' for the src_id field to be
26196 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_SRC_ID \
26199 * This bit must be '1' for the tunnel_type field to be
26202 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_TUNNEL_TYPE \
26205 * This bit must be '1' for the dst_id field to be
26208 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_DST_ID \
26211 * This bit must be '1' for the mirror_vnic_id field to be
26214 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_MIRROR_VNIC_ID \
26217 * This bit must be '1' for the num_vlans field to be
26220 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_NUM_VLANS \
26223 * This bit must be '1' for the t_num_vlans field to be
26226 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_T_NUM_VLANS \
26229 * This value sets the match value for the L2 MAC address.
26230 * Destination MAC address for RX path.
26231 * Source MAC address for TX path.
26233 uint8_t l2_addr[6];
26234 /* This value sets the match value for the number of VLANs. */
26237 * This value sets the match value for the number of VLANs
26238 * in the tunnel headers.
26240 uint8_t t_num_vlans;
26242 * This value sets the mask value for the L2 address.
26243 * A value of 0 will mask the corresponding bit from
26246 uint8_t l2_addr_mask[6];
26247 /* This value sets VLAN ID value for outer VLAN. */
26250 * This value sets the mask value for the ovlan id.
26251 * A value of 0 will mask the corresponding bit from
26254 uint16_t l2_ovlan_mask;
26255 /* This value sets VLAN ID value for inner VLAN. */
26258 * This value sets the mask value for the ivlan id.
26259 * A value of 0 will mask the corresponding bit from
26262 uint16_t l2_ivlan_mask;
26263 uint8_t unused_1[2];
26265 * This value sets the match value for the tunnel
26267 * Destination MAC address for RX path.
26268 * Source MAC address for TX path.
26270 uint8_t t_l2_addr[6];
26271 uint8_t unused_2[2];
26273 * This value sets the mask value for the tunnel L2
26275 * A value of 0 will mask the corresponding bit from
26278 uint8_t t_l2_addr_mask[6];
26279 /* This value sets VLAN ID value for tunnel outer VLAN. */
26280 uint16_t t_l2_ovlan;
26282 * This value sets the mask value for the tunnel ovlan id.
26283 * A value of 0 will mask the corresponding bit from
26286 uint16_t t_l2_ovlan_mask;
26287 /* This value sets VLAN ID value for tunnel inner VLAN. */
26288 uint16_t t_l2_ivlan;
26290 * This value sets the mask value for the tunnel ivlan id.
26291 * A value of 0 will mask the corresponding bit from
26294 uint16_t t_l2_ivlan_mask;
26295 /* This value identifies the type of source of the packet. */
26298 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_SRC_TYPE_NPORT UINT32_C(0x0)
26299 /* Physical function */
26300 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_SRC_TYPE_PF UINT32_C(0x1)
26301 /* Virtual function */
26302 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_SRC_TYPE_VF UINT32_C(0x2)
26303 /* Virtual NIC of a function */
26304 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_SRC_TYPE_VNIC UINT32_C(0x3)
26305 /* Embedded processor for CFA management */
26306 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_SRC_TYPE_KONG UINT32_C(0x4)
26307 /* Embedded processor for OOB management */
26308 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_SRC_TYPE_APE UINT32_C(0x5)
26309 /* Embedded processor for RoCE */
26310 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_SRC_TYPE_BONO UINT32_C(0x6)
26311 /* Embedded processor for network proxy functions */
26312 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_SRC_TYPE_TANG UINT32_C(0x7)
26313 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_SRC_TYPE_LAST \
26314 HWRM_CFA_L2_FILTER_ALLOC_INPUT_SRC_TYPE_TANG
26317 * This value is the id of the source.
26318 * For a network port, it represents port_id.
26319 * For a physical function, it represents fid.
26320 * For a virtual function, it represents vf_id.
26321 * For a vnic, it represents vnic_id.
26322 * For embedded processors, this id is not valid.
26325 * 1. The function ID is implied if it src_id is
26326 * not provided for a src_type that is either
26330 uint8_t tunnel_type;
26332 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_TUNNEL_TYPE_NONTUNNEL \
26334 /* Virtual eXtensible Local Area Network (VXLAN) */
26335 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_TUNNEL_TYPE_VXLAN \
26337 /* Network Virtualization Generic Routing Encapsulation (NVGRE) */
26338 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_TUNNEL_TYPE_NVGRE \
26340 /* Generic Routing Encapsulation (GRE) inside Ethernet payload */
26341 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_TUNNEL_TYPE_L2GRE \
26344 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_TUNNEL_TYPE_IPIP \
26346 /* Generic Network Virtualization Encapsulation (Geneve) */
26347 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_TUNNEL_TYPE_GENEVE \
26349 /* Multi-Protocol Label Switching (MPLS) */
26350 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_TUNNEL_TYPE_MPLS \
26352 /* Stateless Transport Tunnel (STT) */
26353 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_TUNNEL_TYPE_STT \
26355 /* Generic Routing Encapsulation (GRE) inside IP datagram payload */
26356 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_TUNNEL_TYPE_IPGRE \
26358 /* IPV4 over virtual eXtensible Local Area Network (IPV4oVXLAN) */
26359 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_TUNNEL_TYPE_VXLAN_V4 \
26361 /* Enhance Generic Routing Encapsulation (GRE version 1) inside IP datagram payload */
26362 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_TUNNEL_TYPE_IPGRE_V1 \
26364 /* Use fixed layer 2 ether type of 0xFFFF */
26365 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_TUNNEL_TYPE_L2_ETYPE \
26367 /* IPV6 over virtual eXtensible Local Area Network with GPE header (IPV6oVXLANGPE) */
26368 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_TUNNEL_TYPE_VXLAN_GPE_V6 \
26370 /* Any tunneled traffic */
26371 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_TUNNEL_TYPE_ANYTUNNEL \
26373 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_TUNNEL_TYPE_LAST \
26374 HWRM_CFA_L2_FILTER_ALLOC_INPUT_TUNNEL_TYPE_ANYTUNNEL
26377 * If set, this value shall represent the
26378 * Logical VNIC ID of the destination VNIC for the RX
26379 * path and network port id of the destination port for
26384 * Logical VNIC ID of the VNIC where traffic is
26387 uint16_t mirror_vnic_id;
26389 * This hint is provided to help in placing
26390 * the filter in the filter table.
26393 /* No preference */
26394 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_PRI_HINT_NO_PREFER \
26396 /* Above the given filter */
26397 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_PRI_HINT_ABOVE_FILTER \
26399 /* Below the given filter */
26400 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_PRI_HINT_BELOW_FILTER \
26402 /* As high as possible */
26403 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_PRI_HINT_MAX \
26405 /* As low as possible */
26406 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_PRI_HINT_MIN \
26408 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_PRI_HINT_LAST \
26409 HWRM_CFA_L2_FILTER_ALLOC_INPUT_PRI_HINT_MIN
26413 * This is the ID of the filter that goes along with
26416 * This field is valid only for the following values.
26417 * 1 - Above the given filter
26418 * 2 - Below the given filter
26420 uint64_t l2_filter_id_hint;
26423 /* hwrm_cfa_l2_filter_alloc_output (size:192b/24B) */
26424 struct hwrm_cfa_l2_filter_alloc_output {
26425 /* The specific error status for the command. */
26426 uint16_t error_code;
26427 /* The HWRM command request type. */
26429 /* The sequence ID from the original command. */
26431 /* The length of the response data in number of bytes. */
26434 * This value identifies a set of CFA data structures used for an L2
26437 uint64_t l2_filter_id;
26439 * The flow id value in bit 0-29 is the actual ID of the flow
26440 * associated with this filter and it shall be used to match
26441 * and associate the flow identifier returned in completion
26442 * records. A value of 0xFFFFFFFF in the 32-bit flow_id field
26443 * shall indicate no valid flow id.
26446 /* Indicate the flow id value. */
26447 #define HWRM_CFA_L2_FILTER_ALLOC_OUTPUT_FLOW_ID_VALUE_MASK \
26448 UINT32_C(0x3fffffff)
26449 #define HWRM_CFA_L2_FILTER_ALLOC_OUTPUT_FLOW_ID_VALUE_SFT 0
26450 /* Indicate type of the flow. */
26451 #define HWRM_CFA_L2_FILTER_ALLOC_OUTPUT_FLOW_ID_TYPE \
26452 UINT32_C(0x40000000)
26454 * If this bit set to 0, then it indicates that the flow is
26457 #define HWRM_CFA_L2_FILTER_ALLOC_OUTPUT_FLOW_ID_TYPE_INT \
26458 (UINT32_C(0x0) << 30)
26460 * If this bit is set to 1, then it indicates that the flow is
26463 #define HWRM_CFA_L2_FILTER_ALLOC_OUTPUT_FLOW_ID_TYPE_EXT \
26464 (UINT32_C(0x1) << 30)
26465 #define HWRM_CFA_L2_FILTER_ALLOC_OUTPUT_FLOW_ID_TYPE_LAST \
26466 HWRM_CFA_L2_FILTER_ALLOC_OUTPUT_FLOW_ID_TYPE_EXT
26467 /* Indicate the flow direction. */
26468 #define HWRM_CFA_L2_FILTER_ALLOC_OUTPUT_FLOW_ID_DIR \
26469 UINT32_C(0x80000000)
26470 /* If this bit set to 0, then it indicates rx flow. */
26471 #define HWRM_CFA_L2_FILTER_ALLOC_OUTPUT_FLOW_ID_DIR_RX \
26472 (UINT32_C(0x0) << 31)
26473 /* If this bit is set to 1, then it indicates that tx flow. */
26474 #define HWRM_CFA_L2_FILTER_ALLOC_OUTPUT_FLOW_ID_DIR_TX \
26475 (UINT32_C(0x1) << 31)
26476 #define HWRM_CFA_L2_FILTER_ALLOC_OUTPUT_FLOW_ID_DIR_LAST \
26477 HWRM_CFA_L2_FILTER_ALLOC_OUTPUT_FLOW_ID_DIR_TX
26478 uint8_t unused_0[3];
26480 * This field is used in Output records to indicate that the output
26481 * is completely written to RAM. This field should be read as '1'
26482 * to indicate that the output has been completely written.
26483 * When writing a command completion or response to an internal processor,
26484 * the order of writes has to be such that this field is written last.
26489 /***************************
26490 * hwrm_cfa_l2_filter_free *
26491 ***************************/
26494 /* hwrm_cfa_l2_filter_free_input (size:192b/24B) */
26495 struct hwrm_cfa_l2_filter_free_input {
26496 /* The HWRM command request type. */
26499 * The completion ring to send the completion event on. This should
26500 * be the NQ ID returned from the `nq_alloc` HWRM command.
26502 uint16_t cmpl_ring;
26504 * The sequence ID is used by the driver for tracking multiple
26505 * commands. This ID is treated as opaque data by the firmware and
26506 * the value is returned in the `hwrm_resp_hdr` upon completion.
26510 * The target ID of the command:
26511 * * 0x0-0xFFF8 - The function ID
26512 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
26513 * * 0xFFFD - Reserved for user-space HWRM interface
26516 uint16_t target_id;
26518 * A physical address pointer pointing to a host buffer that the
26519 * command's response data will be written. This can be either a host
26520 * physical address (HPA) or a guest physical address (GPA) and must
26521 * point to a physically contiguous block of memory.
26523 uint64_t resp_addr;
26525 * This value identifies a set of CFA data structures used for an L2
26528 uint64_t l2_filter_id;
26531 /* hwrm_cfa_l2_filter_free_output (size:128b/16B) */
26532 struct hwrm_cfa_l2_filter_free_output {
26533 /* The specific error status for the command. */
26534 uint16_t error_code;
26535 /* The HWRM command request type. */
26537 /* The sequence ID from the original command. */
26539 /* The length of the response data in number of bytes. */
26541 uint8_t unused_0[7];
26543 * This field is used in Output records to indicate that the output
26544 * is completely written to RAM. This field should be read as '1'
26545 * to indicate that the output has been completely written.
26546 * When writing a command completion or response to an internal processor,
26547 * the order of writes has to be such that this field is written last.
26552 /**************************
26553 * hwrm_cfa_l2_filter_cfg *
26554 **************************/
26557 /* hwrm_cfa_l2_filter_cfg_input (size:320b/40B) */
26558 struct hwrm_cfa_l2_filter_cfg_input {
26559 /* The HWRM command request type. */
26562 * The completion ring to send the completion event on. This should
26563 * be the NQ ID returned from the `nq_alloc` HWRM command.
26565 uint16_t cmpl_ring;
26567 * The sequence ID is used by the driver for tracking multiple
26568 * commands. This ID is treated as opaque data by the firmware and
26569 * the value is returned in the `hwrm_resp_hdr` upon completion.
26573 * The target ID of the command:
26574 * * 0x0-0xFFF8 - The function ID
26575 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
26576 * * 0xFFFD - Reserved for user-space HWRM interface
26579 uint16_t target_id;
26581 * A physical address pointer pointing to a host buffer that the
26582 * command's response data will be written. This can be either a host
26583 * physical address (HPA) or a guest physical address (GPA) and must
26584 * point to a physically contiguous block of memory.
26586 uint64_t resp_addr;
26589 * Enumeration denoting the RX, TX type of the resource.
26590 * This enumeration is used for resources that are similar for both
26591 * TX and RX paths of the chip.
26593 #define HWRM_CFA_L2_FILTER_CFG_INPUT_FLAGS_PATH \
26596 #define HWRM_CFA_L2_FILTER_CFG_INPUT_FLAGS_PATH_TX \
26599 #define HWRM_CFA_L2_FILTER_CFG_INPUT_FLAGS_PATH_RX \
26601 #define HWRM_CFA_L2_FILTER_CFG_INPUT_FLAGS_PATH_LAST \
26602 HWRM_CFA_L2_FILTER_CFG_INPUT_FLAGS_PATH_RX
26604 * Setting of this flag indicates drop action. If this flag is not set,
26605 * then it should be considered accept action.
26607 #define HWRM_CFA_L2_FILTER_CFG_INPUT_FLAGS_DROP \
26610 * Enumeration denoting NO_ROCE_L2 to support old drivers.
26611 * New driver L2 for only L2 traffic, ROCE for roce and l2 traffic
26613 #define HWRM_CFA_L2_FILTER_CFG_INPUT_FLAGS_TRAFFIC_MASK \
26615 #define HWRM_CFA_L2_FILTER_CFG_INPUT_FLAGS_TRAFFIC_SFT 2
26616 /* To support old drivers */
26617 #define HWRM_CFA_L2_FILTER_CFG_INPUT_FLAGS_TRAFFIC_NO_ROCE_L2 \
26618 (UINT32_C(0x0) << 2)
26619 /* Only L2 traffic */
26620 #define HWRM_CFA_L2_FILTER_CFG_INPUT_FLAGS_TRAFFIC_L2 \
26621 (UINT32_C(0x1) << 2)
26622 /* Roce & L2 traffic */
26623 #define HWRM_CFA_L2_FILTER_CFG_INPUT_FLAGS_TRAFFIC_ROCE \
26624 (UINT32_C(0x2) << 2)
26625 #define HWRM_CFA_L2_FILTER_CFG_INPUT_FLAGS_TRAFFIC_LAST \
26626 HWRM_CFA_L2_FILTER_CFG_INPUT_FLAGS_TRAFFIC_ROCE
26629 * This bit must be '1' for the dst_id field to be
26632 #define HWRM_CFA_L2_FILTER_CFG_INPUT_ENABLES_DST_ID \
26635 * This bit must be '1' for the new_mirror_vnic_id field to be
26638 #define HWRM_CFA_L2_FILTER_CFG_INPUT_ENABLES_NEW_MIRROR_VNIC_ID \
26641 * This value identifies a set of CFA data structures used for an L2
26644 uint64_t l2_filter_id;
26646 * If set, this value shall represent the
26647 * Logical VNIC ID of the destination VNIC for the RX
26648 * path and network port id of the destination port for
26653 * New Logical VNIC ID of the VNIC where traffic is
26656 uint32_t new_mirror_vnic_id;
26659 /* hwrm_cfa_l2_filter_cfg_output (size:128b/16B) */
26660 struct hwrm_cfa_l2_filter_cfg_output {
26661 /* The specific error status for the command. */
26662 uint16_t error_code;
26663 /* The HWRM command request type. */
26665 /* The sequence ID from the original command. */
26667 /* The length of the response data in number of bytes. */
26669 uint8_t unused_0[7];
26671 * This field is used in Output records to indicate that the output
26672 * is completely written to RAM. This field should be read as '1'
26673 * to indicate that the output has been completely written.
26674 * When writing a command completion or response to an internal processor,
26675 * the order of writes has to be such that this field is written last.
26680 /***************************
26681 * hwrm_cfa_l2_set_rx_mask *
26682 ***************************/
26685 /* hwrm_cfa_l2_set_rx_mask_input (size:448b/56B) */
26686 struct hwrm_cfa_l2_set_rx_mask_input {
26687 /* The HWRM command request type. */
26690 * The completion ring to send the completion event on. This should
26691 * be the NQ ID returned from the `nq_alloc` HWRM command.
26693 uint16_t cmpl_ring;
26695 * The sequence ID is used by the driver for tracking multiple
26696 * commands. This ID is treated as opaque data by the firmware and
26697 * the value is returned in the `hwrm_resp_hdr` upon completion.
26701 * The target ID of the command:
26702 * * 0x0-0xFFF8 - The function ID
26703 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
26704 * * 0xFFFD - Reserved for user-space HWRM interface
26707 uint16_t target_id;
26709 * A physical address pointer pointing to a host buffer that the
26710 * command's response data will be written. This can be either a host
26711 * physical address (HPA) or a guest physical address (GPA) and must
26712 * point to a physically contiguous block of memory.
26714 uint64_t resp_addr;
26719 * When this bit is '1', the function is requested to accept
26720 * multi-cast packets specified by the multicast addr table.
26722 #define HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_MCAST \
26725 * When this bit is '1', the function is requested to accept
26726 * all multi-cast packets.
26728 #define HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_ALL_MCAST \
26731 * When this bit is '1', the function is requested to accept
26732 * broadcast packets.
26734 #define HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_BCAST \
26737 * When this bit is '1', the function is requested to be
26738 * put in the promiscuous mode.
26740 * The HWRM should accept any function to set up
26741 * promiscuous mode.
26743 * The HWRM shall follow the semantics below for the
26744 * promiscuous mode support.
26745 * # When partitioning is not enabled on a port
26746 * (i.e. single PF on the port), then the PF shall
26747 * be allowed to be in the promiscuous mode. When the
26748 * PF is in the promiscuous mode, then it shall
26749 * receive all host bound traffic on that port.
26750 * # When partitioning is enabled on a port
26751 * (i.e. multiple PFs per port) and a PF on that
26752 * port is in the promiscuous mode, then the PF
26753 * receives all traffic within that partition as
26754 * identified by a unique identifier for the
26755 * PF (e.g. S-Tag). If a unique outer VLAN
26756 * for the PF is specified, then the setting of
26757 * promiscuous mode on that PF shall result in the
26758 * PF receiving all host bound traffic with matching
26760 * # A VF shall can be set in the promiscuous mode.
26761 * In the promiscuous mode, the VF does not receive any
26762 * traffic unless a unique outer VLAN for the
26763 * VF is specified. If a unique outer VLAN
26764 * for the VF is specified, then the setting of
26765 * promiscuous mode on that VF shall result in the
26766 * VF receiving all host bound traffic with the
26767 * matching outer VLAN.
26768 * # The HWRM shall allow the setting of promiscuous
26769 * mode on a function independently from the
26770 * promiscuous mode settings on other functions.
26772 #define HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_PROMISCUOUS \
26775 * If this flag is set, the corresponding RX
26776 * filters shall be set up to cover multicast/broadcast
26777 * filters for the outermost Layer 2 destination MAC
26780 #define HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_OUTERMOST \
26783 * If this flag is set, the corresponding RX
26784 * filters shall be set up to cover multicast/broadcast
26785 * filters for the VLAN-tagged packets that match the
26786 * TPID and VID fields of VLAN tags in the VLAN tag
26787 * table specified in this command.
26789 #define HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_VLANONLY \
26792 * If this flag is set, the corresponding RX
26793 * filters shall be set up to cover multicast/broadcast
26794 * filters for non-VLAN tagged packets and VLAN-tagged
26795 * packets that match the TPID and VID fields of VLAN
26796 * tags in the VLAN tag table specified in this command.
26798 #define HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_VLAN_NONVLAN \
26801 * If this flag is set, the corresponding RX
26802 * filters shall be set up to cover multicast/broadcast
26803 * filters for non-VLAN tagged packets and VLAN-tagged
26804 * packets matching any VLAN tag.
26806 * If this flag is set, then the HWRM shall ignore
26807 * VLAN tags specified in vlan_tag_tbl.
26809 * If none of vlanonly, vlan_nonvlan, and anyvlan_nonvlan
26810 * flags is set, then the HWRM shall ignore
26811 * VLAN tags specified in vlan_tag_tbl.
26813 * The HWRM client shall set at most one flag out of
26814 * vlanonly, vlan_nonvlan, and anyvlan_nonvlan.
26816 #define HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_ANYVLAN_NONVLAN \
26818 /* This is the address for mcast address tbl. */
26819 uint64_t mc_tbl_addr;
26821 * This value indicates how many entries in mc_tbl are valid.
26822 * Each entry is 6 bytes.
26824 uint32_t num_mc_entries;
26825 uint8_t unused_0[4];
26827 * This is the address for VLAN tag table.
26828 * Each VLAN entry in the table is 4 bytes of a VLAN tag
26829 * including TPID, PCP, DEI, and VID fields in network byte
26832 uint64_t vlan_tag_tbl_addr;
26834 * This value indicates how many entries in vlan_tag_tbl are
26835 * valid. Each entry is 4 bytes.
26837 uint32_t num_vlan_tags;
26838 uint8_t unused_1[4];
26841 /* hwrm_cfa_l2_set_rx_mask_output (size:128b/16B) */
26842 struct hwrm_cfa_l2_set_rx_mask_output {
26843 /* The specific error status for the command. */
26844 uint16_t error_code;
26845 /* The HWRM command request type. */
26847 /* The sequence ID from the original command. */
26849 /* The length of the response data in number of bytes. */
26851 uint8_t unused_0[7];
26853 * This field is used in Output records to indicate that the output
26854 * is completely written to RAM. This field should be read as '1'
26855 * to indicate that the output has been completely written.
26856 * When writing a command completion or response to an internal processor,
26857 * the order of writes has to be such that this field is written last.
26862 /* hwrm_cfa_l2_set_rx_mask_cmd_err (size:64b/8B) */
26863 struct hwrm_cfa_l2_set_rx_mask_cmd_err {
26865 * command specific error codes that goes to
26866 * the cmd_err field in Common HWRM Error Response.
26869 /* Unknown error */
26870 #define HWRM_CFA_L2_SET_RX_MASK_CMD_ERR_CODE_UNKNOWN \
26872 /* Unable to complete operation due to conflict with Ntuple Filter */
26873 #define HWRM_CFA_L2_SET_RX_MASK_CMD_ERR_CODE_NTUPLE_FILTER_CONFLICT_ERR \
26875 #define HWRM_CFA_L2_SET_RX_MASK_CMD_ERR_CODE_LAST \
26876 HWRM_CFA_L2_SET_RX_MASK_CMD_ERR_CODE_NTUPLE_FILTER_CONFLICT_ERR
26877 uint8_t unused_0[7];
26880 /*******************************
26881 * hwrm_cfa_vlan_antispoof_cfg *
26882 *******************************/
26885 /* hwrm_cfa_vlan_antispoof_cfg_input (size:256b/32B) */
26886 struct hwrm_cfa_vlan_antispoof_cfg_input {
26887 /* The HWRM command request type. */
26890 * The completion ring to send the completion event on. This should
26891 * be the NQ ID returned from the `nq_alloc` HWRM command.
26893 uint16_t cmpl_ring;
26895 * The sequence ID is used by the driver for tracking multiple
26896 * commands. This ID is treated as opaque data by the firmware and
26897 * the value is returned in the `hwrm_resp_hdr` upon completion.
26901 * The target ID of the command:
26902 * * 0x0-0xFFF8 - The function ID
26903 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
26904 * * 0xFFFD - Reserved for user-space HWRM interface
26907 uint16_t target_id;
26909 * A physical address pointer pointing to a host buffer that the
26910 * command's response data will be written. This can be either a host
26911 * physical address (HPA) or a guest physical address (GPA) and must
26912 * point to a physically contiguous block of memory.
26914 uint64_t resp_addr;
26916 * Function ID of the function that is being configured.
26917 * Only valid for a VF FID configured by the PF.
26920 uint8_t unused_0[2];
26921 /* Number of VLAN entries in the vlan_tag_mask_tbl. */
26922 uint32_t num_vlan_entries;
26924 * The vlan_tag_mask_tbl_addr is the DMA address of the VLAN
26925 * antispoof table. Each table entry contains the 16-bit TPID
26926 * (0x8100 or 0x88a8 only), 16-bit VLAN ID, and a 16-bit mask,
26927 * all in network order to match hwrm_cfa_l2_set_rx_mask.
26928 * For an individual VLAN entry, the mask value should be 0xfff
26929 * for the 12-bit VLAN ID.
26931 uint64_t vlan_tag_mask_tbl_addr;
26934 /* hwrm_cfa_vlan_antispoof_cfg_output (size:128b/16B) */
26935 struct hwrm_cfa_vlan_antispoof_cfg_output {
26936 /* The specific error status for the command. */
26937 uint16_t error_code;
26938 /* The HWRM command request type. */
26940 /* The sequence ID from the original command. */
26942 /* The length of the response data in number of bytes. */
26944 uint8_t unused_0[7];
26946 * This field is used in Output records to indicate that the output
26947 * is completely written to RAM. This field should be read as '1'
26948 * to indicate that the output has been completely written.
26949 * When writing a command completion or response to an internal processor,
26950 * the order of writes has to be such that this field is written last.
26955 /********************************
26956 * hwrm_cfa_vlan_antispoof_qcfg *
26957 ********************************/
26960 /* hwrm_cfa_vlan_antispoof_qcfg_input (size:256b/32B) */
26961 struct hwrm_cfa_vlan_antispoof_qcfg_input {
26962 /* The HWRM command request type. */
26965 * The completion ring to send the completion event on. This should
26966 * be the NQ ID returned from the `nq_alloc` HWRM command.
26968 uint16_t cmpl_ring;
26970 * The sequence ID is used by the driver for tracking multiple
26971 * commands. This ID is treated as opaque data by the firmware and
26972 * the value is returned in the `hwrm_resp_hdr` upon completion.
26976 * The target ID of the command:
26977 * * 0x0-0xFFF8 - The function ID
26978 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
26979 * * 0xFFFD - Reserved for user-space HWRM interface
26982 uint16_t target_id;
26984 * A physical address pointer pointing to a host buffer that the
26985 * command's response data will be written. This can be either a host
26986 * physical address (HPA) or a guest physical address (GPA) and must
26987 * point to a physically contiguous block of memory.
26989 uint64_t resp_addr;
26991 * Function ID of the function that is being queried.
26992 * Only valid for a VF FID queried by the PF.
26995 uint8_t unused_0[2];
26997 * Maximum number of VLAN entries the firmware is allowed to DMA
26998 * to vlan_tag_mask_tbl.
27000 uint32_t max_vlan_entries;
27002 * The vlan_tag_mask_tbl_addr is the DMA address of the VLAN
27003 * antispoof table to which firmware will DMA to. Each table
27004 * entry will contain the 16-bit TPID (0x8100 or 0x88a8 only),
27005 * 16-bit VLAN ID, and a 16-bit mask, all in network order to
27006 * match hwrm_cfa_l2_set_rx_mask. For an individual VLAN entry,
27007 * the mask value should be 0xfff for the 12-bit VLAN ID.
27009 uint64_t vlan_tag_mask_tbl_addr;
27012 /* hwrm_cfa_vlan_antispoof_qcfg_output (size:128b/16B) */
27013 struct hwrm_cfa_vlan_antispoof_qcfg_output {
27014 /* The specific error status for the command. */
27015 uint16_t error_code;
27016 /* The HWRM command request type. */
27018 /* The sequence ID from the original command. */
27020 /* The length of the response data in number of bytes. */
27022 /* Number of valid entries DMAd by firmware to vlan_tag_mask_tbl. */
27023 uint32_t num_vlan_entries;
27024 uint8_t unused_0[3];
27026 * This field is used in Output records to indicate that the output
27027 * is completely written to RAM. This field should be read as '1'
27028 * to indicate that the output has been completely written.
27029 * When writing a command completion or response to an internal processor,
27030 * the order of writes has to be such that this field is written last.
27035 /********************************
27036 * hwrm_cfa_tunnel_filter_alloc *
27037 ********************************/
27040 /* hwrm_cfa_tunnel_filter_alloc_input (size:704b/88B) */
27041 struct hwrm_cfa_tunnel_filter_alloc_input {
27042 /* The HWRM command request type. */
27045 * The completion ring to send the completion event on. This should
27046 * be the NQ ID returned from the `nq_alloc` HWRM command.
27048 uint16_t cmpl_ring;
27050 * The sequence ID is used by the driver for tracking multiple
27051 * commands. This ID is treated as opaque data by the firmware and
27052 * the value is returned in the `hwrm_resp_hdr` upon completion.
27056 * The target ID of the command:
27057 * * 0x0-0xFFF8 - The function ID
27058 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
27059 * * 0xFFFD - Reserved for user-space HWRM interface
27062 uint16_t target_id;
27064 * A physical address pointer pointing to a host buffer that the
27065 * command's response data will be written. This can be either a host
27066 * physical address (HPA) or a guest physical address (GPA) and must
27067 * point to a physically contiguous block of memory.
27069 uint64_t resp_addr;
27071 /* Setting of this flag indicates the applicability to the loopback path. */
27072 #define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_FLAGS_LOOPBACK \
27076 * This bit must be '1' for the l2_filter_id field to be
27079 #define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_ENABLES_L2_FILTER_ID \
27082 * This bit must be '1' for the l2_addr field to be
27085 #define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_ENABLES_L2_ADDR \
27088 * This bit must be '1' for the l2_ivlan field to be
27091 #define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN \
27094 * This bit must be '1' for the l3_addr field to be
27097 #define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_ENABLES_L3_ADDR \
27100 * This bit must be '1' for the l3_addr_type field to be
27103 #define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_ENABLES_L3_ADDR_TYPE \
27106 * This bit must be '1' for the t_l3_addr_type field to be
27109 #define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_ENABLES_T_L3_ADDR_TYPE \
27112 * This bit must be '1' for the t_l3_addr field to be
27115 #define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_ENABLES_T_L3_ADDR \
27118 * This bit must be '1' for the tunnel_type field to be
27121 #define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_ENABLES_TUNNEL_TYPE \
27124 * This bit must be '1' for the vni field to be
27127 #define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_ENABLES_VNI \
27130 * This bit must be '1' for the dst_vnic_id field to be
27133 #define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_ENABLES_DST_VNIC_ID \
27136 * This bit must be '1' for the mirror_vnic_id field to be
27139 #define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_ENABLES_MIRROR_VNIC_ID \
27142 * This value identifies a set of CFA data structures used for an L2
27145 uint64_t l2_filter_id;
27147 * This value sets the match value for the inner L2
27149 * Destination MAC address for RX path.
27150 * Source MAC address for TX path.
27152 uint8_t l2_addr[6];
27154 * This value sets VLAN ID value for inner VLAN.
27155 * Only 12-bits of VLAN ID are used in setting the filter.
27159 * The value of inner destination IP address to be used in filtering.
27160 * For IPv4, first four bytes represent the IP address.
27162 uint32_t l3_addr[4];
27164 * The value of tunnel destination IP address to be used in filtering.
27165 * For IPv4, first four bytes represent the IP address.
27167 uint32_t t_l3_addr[4];
27169 * This value indicates the type of inner IP address.
27172 * All others are invalid.
27174 uint8_t l3_addr_type;
27176 * This value indicates the type of tunnel IP address.
27179 * All others are invalid.
27181 uint8_t t_l3_addr_type;
27183 uint8_t tunnel_type;
27185 #define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_TUNNEL_TYPE_NONTUNNEL \
27187 /* Virtual eXtensible Local Area Network (VXLAN) */
27188 #define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_TUNNEL_TYPE_VXLAN \
27190 /* Network Virtualization Generic Routing Encapsulation (NVGRE) */
27191 #define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_TUNNEL_TYPE_NVGRE \
27193 /* Generic Routing Encapsulation (GRE) inside Ethernet payload */
27194 #define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_TUNNEL_TYPE_L2GRE \
27197 #define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_TUNNEL_TYPE_IPIP \
27199 /* Generic Network Virtualization Encapsulation (Geneve) */
27200 #define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_TUNNEL_TYPE_GENEVE \
27202 /* Multi-Protocol Label Switching (MPLS) */
27203 #define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_TUNNEL_TYPE_MPLS \
27205 /* Stateless Transport Tunnel (STT) */
27206 #define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_TUNNEL_TYPE_STT \
27208 /* Generic Routing Encapsulation (GRE) inside IP datagram payload */
27209 #define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_TUNNEL_TYPE_IPGRE \
27211 /* IPV4 over virtual eXtensible Local Area Network (IPV4oVXLAN) */
27212 #define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_TUNNEL_TYPE_VXLAN_V4 \
27214 /* Enhance Generic Routing Encapsulation (GRE version 1) inside IP datagram payload */
27215 #define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_TUNNEL_TYPE_IPGRE_V1 \
27217 /* Use fixed layer 2 ether type of 0xFFFF */
27218 #define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_TUNNEL_TYPE_L2_ETYPE \
27220 /* IPV6 over virtual eXtensible Local Area Network with GPE header (IPV6oVXLANGPE) */
27221 #define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_TUNNEL_TYPE_VXLAN_GPE_V6 \
27223 /* Any tunneled traffic */
27224 #define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_TUNNEL_TYPE_ANYTUNNEL \
27226 #define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_TUNNEL_TYPE_LAST \
27227 HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_TUNNEL_TYPE_ANYTUNNEL
27229 * tunnel_flags allows the user to indicate the tunnel tag detection
27230 * for the tunnel type specified in tunnel_type.
27232 uint8_t tunnel_flags;
27234 * If the tunnel_type is geneve, then this bit indicates if we
27235 * need to match the geneve OAM packet.
27236 * If the tunnel_type is nvgre or gre, then this bit indicates if
27237 * we need to detect checksum present bit in geneve header.
27238 * If the tunnel_type is mpls, then this bit indicates if we need
27239 * to match mpls packet with explicit IPV4/IPV6 null header.
27241 #define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_TUNNEL_FLAGS_TUN_FLAGS_OAM_CHECKSUM_EXPLHDR \
27244 * If the tunnel_type is geneve, then this bit indicates if we
27245 * need to detect the critical option bit set in the oam packet.
27246 * If the tunnel_type is nvgre or gre, then this bit indicates
27247 * if we need to match nvgre packets with key present bit set in
27249 * If the tunnel_type is mpls, then this bit indicates if we
27250 * need to match mpls packet with S bit from inner/second label.
27252 #define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_TUNNEL_FLAGS_TUN_FLAGS_CRITICAL_OPT_S1 \
27255 * If the tunnel_type is geneve, then this bit indicates if we
27256 * need to match geneve packet with extended header bit set in
27258 * If the tunnel_type is nvgre or gre, then this bit indicates
27259 * if we need to match nvgre packets with sequence number
27260 * present bit set in gre header.
27261 * If the tunnel_type is mpls, then this bit indicates if we
27262 * need to match mpls packet with S bit from out/first label.
27264 #define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_TUNNEL_FLAGS_TUN_FLAGS_EXTHDR_SEQNUM_S0 \
27267 * Virtual Network Identifier (VNI). Only valid with
27268 * tunnel_types VXLAN, NVGRE, and Geneve.
27269 * Only lower 24-bits of VNI field are used
27270 * in setting up the filter.
27273 /* Logical VNIC ID of the destination VNIC. */
27274 uint32_t dst_vnic_id;
27276 * Logical VNIC ID of the VNIC where traffic is
27279 uint32_t mirror_vnic_id;
27282 /* hwrm_cfa_tunnel_filter_alloc_output (size:192b/24B) */
27283 struct hwrm_cfa_tunnel_filter_alloc_output {
27284 /* The specific error status for the command. */
27285 uint16_t error_code;
27286 /* The HWRM command request type. */
27288 /* The sequence ID from the original command. */
27290 /* The length of the response data in number of bytes. */
27292 /* This value is an opaque id into CFA data structures. */
27293 uint64_t tunnel_filter_id;
27295 * The flow id value in bit 0-29 is the actual ID of the flow
27296 * associated with this filter and it shall be used to match
27297 * and associate the flow identifier returned in completion
27298 * records. A value of 0xFFFFFFFF in the 32-bit flow_id field
27299 * shall indicate no valid flow id.
27302 /* Indicate the flow id value. */
27303 #define HWRM_CFA_TUNNEL_FILTER_ALLOC_OUTPUT_FLOW_ID_VALUE_MASK \
27304 UINT32_C(0x3fffffff)
27305 #define HWRM_CFA_TUNNEL_FILTER_ALLOC_OUTPUT_FLOW_ID_VALUE_SFT 0
27306 /* Indicate type of the flow. */
27307 #define HWRM_CFA_TUNNEL_FILTER_ALLOC_OUTPUT_FLOW_ID_TYPE \
27308 UINT32_C(0x40000000)
27310 * If this bit set to 0, then it indicates that the flow is
27313 #define HWRM_CFA_TUNNEL_FILTER_ALLOC_OUTPUT_FLOW_ID_TYPE_INT \
27314 (UINT32_C(0x0) << 30)
27316 * If this bit is set to 1, then it indicates that the flow is
27319 #define HWRM_CFA_TUNNEL_FILTER_ALLOC_OUTPUT_FLOW_ID_TYPE_EXT \
27320 (UINT32_C(0x1) << 30)
27321 #define HWRM_CFA_TUNNEL_FILTER_ALLOC_OUTPUT_FLOW_ID_TYPE_LAST \
27322 HWRM_CFA_TUNNEL_FILTER_ALLOC_OUTPUT_FLOW_ID_TYPE_EXT
27323 /* Indicate the flow direction. */
27324 #define HWRM_CFA_TUNNEL_FILTER_ALLOC_OUTPUT_FLOW_ID_DIR \
27325 UINT32_C(0x80000000)
27326 /* If this bit set to 0, then it indicates rx flow. */
27327 #define HWRM_CFA_TUNNEL_FILTER_ALLOC_OUTPUT_FLOW_ID_DIR_RX \
27328 (UINT32_C(0x0) << 31)
27329 /* If this bit is set to 1, then it indicates that tx flow. */
27330 #define HWRM_CFA_TUNNEL_FILTER_ALLOC_OUTPUT_FLOW_ID_DIR_TX \
27331 (UINT32_C(0x1) << 31)
27332 #define HWRM_CFA_TUNNEL_FILTER_ALLOC_OUTPUT_FLOW_ID_DIR_LAST \
27333 HWRM_CFA_TUNNEL_FILTER_ALLOC_OUTPUT_FLOW_ID_DIR_TX
27334 uint8_t unused_0[3];
27336 * This field is used in Output records to indicate that the output
27337 * is completely written to RAM. This field should be read as '1'
27338 * to indicate that the output has been completely written.
27339 * When writing a command completion or response to an internal processor,
27340 * the order of writes has to be such that this field is written last.
27345 /*******************************
27346 * hwrm_cfa_tunnel_filter_free *
27347 *******************************/
27350 /* hwrm_cfa_tunnel_filter_free_input (size:192b/24B) */
27351 struct hwrm_cfa_tunnel_filter_free_input {
27352 /* The HWRM command request type. */
27355 * The completion ring to send the completion event on. This should
27356 * be the NQ ID returned from the `nq_alloc` HWRM command.
27358 uint16_t cmpl_ring;
27360 * The sequence ID is used by the driver for tracking multiple
27361 * commands. This ID is treated as opaque data by the firmware and
27362 * the value is returned in the `hwrm_resp_hdr` upon completion.
27366 * The target ID of the command:
27367 * * 0x0-0xFFF8 - The function ID
27368 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
27369 * * 0xFFFD - Reserved for user-space HWRM interface
27372 uint16_t target_id;
27374 * A physical address pointer pointing to a host buffer that the
27375 * command's response data will be written. This can be either a host
27376 * physical address (HPA) or a guest physical address (GPA) and must
27377 * point to a physically contiguous block of memory.
27379 uint64_t resp_addr;
27380 /* This value is an opaque id into CFA data structures. */
27381 uint64_t tunnel_filter_id;
27384 /* hwrm_cfa_tunnel_filter_free_output (size:128b/16B) */
27385 struct hwrm_cfa_tunnel_filter_free_output {
27386 /* The specific error status for the command. */
27387 uint16_t error_code;
27388 /* The HWRM command request type. */
27390 /* The sequence ID from the original command. */
27392 /* The length of the response data in number of bytes. */
27394 uint8_t unused_0[7];
27396 * This field is used in Output records to indicate that the output
27397 * is completely written to RAM. This field should be read as '1'
27398 * to indicate that the output has been completely written.
27399 * When writing a command completion or response to an internal processor,
27400 * the order of writes has to be such that this field is written last.
27405 /***************************************
27406 * hwrm_cfa_redirect_tunnel_type_alloc *
27407 ***************************************/
27410 /* hwrm_cfa_redirect_tunnel_type_alloc_input (size:192b/24B) */
27411 struct hwrm_cfa_redirect_tunnel_type_alloc_input {
27412 /* The HWRM command request type. */
27415 * The completion ring to send the completion event on. This should
27416 * be the NQ ID returned from the `nq_alloc` HWRM command.
27418 uint16_t cmpl_ring;
27420 * The sequence ID is used by the driver for tracking multiple
27421 * commands. This ID is treated as opaque data by the firmware and
27422 * the value is returned in the `hwrm_resp_hdr` upon completion.
27426 * The target ID of the command:
27427 * * 0x0-0xFFF8 - The function ID
27428 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
27429 * * 0xFFFD - Reserved for user-space HWRM interface
27432 uint16_t target_id;
27434 * A physical address pointer pointing to a host buffer that the
27435 * command's response data will be written. This can be either a host
27436 * physical address (HPA) or a guest physical address (GPA) and must
27437 * point to a physically contiguous block of memory.
27439 uint64_t resp_addr;
27440 /* The destination function id, to whom the traffic is redirected. */
27443 uint8_t tunnel_type;
27445 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_ALLOC_INPUT_TUNNEL_TYPE_NONTUNNEL \
27447 /* Virtual eXtensible Local Area Network (VXLAN) */
27448 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_ALLOC_INPUT_TUNNEL_TYPE_VXLAN \
27450 /* Network Virtualization Generic Routing Encapsulation (NVGRE) */
27451 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_ALLOC_INPUT_TUNNEL_TYPE_NVGRE \
27453 /* Generic Routing Encapsulation (GRE) inside Ethernet payload */
27454 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_ALLOC_INPUT_TUNNEL_TYPE_L2GRE \
27457 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_ALLOC_INPUT_TUNNEL_TYPE_IPIP \
27459 /* Generic Network Virtualization Encapsulation (Geneve) */
27460 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_ALLOC_INPUT_TUNNEL_TYPE_GENEVE \
27462 /* Multi-Protocol Label Switching (MPLS) */
27463 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_ALLOC_INPUT_TUNNEL_TYPE_MPLS \
27465 /* Stateless Transport Tunnel (STT) */
27466 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_ALLOC_INPUT_TUNNEL_TYPE_STT \
27468 /* Generic Routing Encapsulation (GRE) inside IP datagram payload */
27469 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_ALLOC_INPUT_TUNNEL_TYPE_IPGRE \
27471 /* IPV4 over virtual eXtensible Local Area Network (IPV4oVXLAN) */
27472 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_ALLOC_INPUT_TUNNEL_TYPE_VXLAN_V4 \
27474 /* Enhance Generic Routing Encapsulation (GRE version 1) inside IP datagram payload */
27475 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_ALLOC_INPUT_TUNNEL_TYPE_IPGRE_V1 \
27477 /* Use fixed layer 2 ether type of 0xFFFF */
27478 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_ALLOC_INPUT_TUNNEL_TYPE_L2_ETYPE \
27480 /* IPV6 over virtual eXtensible Local Area Network with GPE header (IPV6oVXLANGPE) */
27481 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_ALLOC_INPUT_TUNNEL_TYPE_VXLAN_GPE_V6 \
27483 /* Any tunneled traffic */
27484 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_ALLOC_INPUT_TUNNEL_TYPE_ANYTUNNEL \
27486 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_ALLOC_INPUT_TUNNEL_TYPE_LAST \
27487 HWRM_CFA_REDIRECT_TUNNEL_TYPE_ALLOC_INPUT_TUNNEL_TYPE_ANYTUNNEL
27488 /* Tunnel alloc flags. */
27490 /* Setting of this flag indicates modify existing redirect tunnel to new destination function ID. */
27491 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_ALLOC_INPUT_FLAGS_MODIFY_DST \
27493 uint8_t unused_0[4];
27496 /* hwrm_cfa_redirect_tunnel_type_alloc_output (size:128b/16B) */
27497 struct hwrm_cfa_redirect_tunnel_type_alloc_output {
27498 /* The specific error status for the command. */
27499 uint16_t error_code;
27500 /* The HWRM command request type. */
27502 /* The sequence ID from the original command. */
27504 /* The length of the response data in number of bytes. */
27506 uint8_t unused_0[7];
27508 * This field is used in Output records to indicate that the output
27509 * is completely written to RAM. This field should be read as '1'
27510 * to indicate that the output has been completely written.
27511 * When writing a command completion or response to an internal processor,
27512 * the order of writes has to be such that this field is written last.
27517 /**************************************
27518 * hwrm_cfa_redirect_tunnel_type_free *
27519 **************************************/
27522 /* hwrm_cfa_redirect_tunnel_type_free_input (size:192b/24B) */
27523 struct hwrm_cfa_redirect_tunnel_type_free_input {
27524 /* The HWRM command request type. */
27527 * The completion ring to send the completion event on. This should
27528 * be the NQ ID returned from the `nq_alloc` HWRM command.
27530 uint16_t cmpl_ring;
27532 * The sequence ID is used by the driver for tracking multiple
27533 * commands. This ID is treated as opaque data by the firmware and
27534 * the value is returned in the `hwrm_resp_hdr` upon completion.
27538 * The target ID of the command:
27539 * * 0x0-0xFFF8 - The function ID
27540 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
27541 * * 0xFFFD - Reserved for user-space HWRM interface
27544 uint16_t target_id;
27546 * A physical address pointer pointing to a host buffer that the
27547 * command's response data will be written. This can be either a host
27548 * physical address (HPA) or a guest physical address (GPA) and must
27549 * point to a physically contiguous block of memory.
27551 uint64_t resp_addr;
27552 /* The destination function id, to whom the traffic is redirected. */
27555 uint8_t tunnel_type;
27557 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_FREE_INPUT_TUNNEL_TYPE_NONTUNNEL \
27559 /* Virtual eXtensible Local Area Network (VXLAN) */
27560 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_FREE_INPUT_TUNNEL_TYPE_VXLAN \
27562 /* Network Virtualization Generic Routing Encapsulation (NVGRE) */
27563 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_FREE_INPUT_TUNNEL_TYPE_NVGRE \
27565 /* Generic Routing Encapsulation (GRE) inside Ethernet payload */
27566 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_FREE_INPUT_TUNNEL_TYPE_L2GRE \
27569 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_FREE_INPUT_TUNNEL_TYPE_IPIP \
27571 /* Generic Network Virtualization Encapsulation (Geneve) */
27572 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_FREE_INPUT_TUNNEL_TYPE_GENEVE \
27574 /* Multi-Protocol Label Switching (MPLS) */
27575 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_FREE_INPUT_TUNNEL_TYPE_MPLS \
27577 /* Stateless Transport Tunnel (STT) */
27578 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_FREE_INPUT_TUNNEL_TYPE_STT \
27580 /* Generic Routing Encapsulation (GRE) inside IP datagram payload */
27581 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_FREE_INPUT_TUNNEL_TYPE_IPGRE \
27583 /* IPV4 over virtual eXtensible Local Area Network (IPV4oVXLAN) */
27584 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_FREE_INPUT_TUNNEL_TYPE_VXLAN_V4 \
27586 /* Enhance Generic Routing Encapsulation (GRE version 1) inside IP datagram payload */
27587 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_FREE_INPUT_TUNNEL_TYPE_IPGRE_V1 \
27589 /* Use fixed layer 2 ether type of 0xFFFF */
27590 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_FREE_INPUT_TUNNEL_TYPE_L2_ETYPE \
27592 /* IPV6 over virtual eXtensible Local Area Network with GPE header (IPV6oVXLANGPE) */
27593 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_FREE_INPUT_TUNNEL_TYPE_VXLAN_GPE_V6 \
27595 /* Any tunneled traffic */
27596 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_FREE_INPUT_TUNNEL_TYPE_ANYTUNNEL \
27598 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_FREE_INPUT_TUNNEL_TYPE_LAST \
27599 HWRM_CFA_REDIRECT_TUNNEL_TYPE_FREE_INPUT_TUNNEL_TYPE_ANYTUNNEL
27600 uint8_t unused_0[5];
27603 /* hwrm_cfa_redirect_tunnel_type_free_output (size:128b/16B) */
27604 struct hwrm_cfa_redirect_tunnel_type_free_output {
27605 /* The specific error status for the command. */
27606 uint16_t error_code;
27607 /* The HWRM command request type. */
27609 /* The sequence ID from the original command. */
27611 /* The length of the response data in number of bytes. */
27613 uint8_t unused_0[7];
27615 * This field is used in Output records to indicate that the output
27616 * is completely written to RAM. This field should be read as '1'
27617 * to indicate that the output has been completely written.
27618 * When writing a command completion or response to an internal processor,
27619 * the order of writes has to be such that this field is written last.
27624 /**************************************
27625 * hwrm_cfa_redirect_tunnel_type_info *
27626 **************************************/
27629 /* hwrm_cfa_redirect_tunnel_type_info_input (size:192b/24B) */
27630 struct hwrm_cfa_redirect_tunnel_type_info_input {
27631 /* The HWRM command request type. */
27634 * The completion ring to send the completion event on. This should
27635 * be the NQ ID returned from the `nq_alloc` HWRM command.
27637 uint16_t cmpl_ring;
27639 * The sequence ID is used by the driver for tracking multiple
27640 * commands. This ID is treated as opaque data by the firmware and
27641 * the value is returned in the `hwrm_resp_hdr` upon completion.
27645 * The target ID of the command:
27646 * * 0x0-0xFFF8 - The function ID
27647 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
27648 * * 0xFFFD - Reserved for user-space HWRM interface
27651 uint16_t target_id;
27653 * A physical address pointer pointing to a host buffer that the
27654 * command's response data will be written. This can be either a host
27655 * physical address (HPA) or a guest physical address (GPA) and must
27656 * point to a physically contiguous block of memory.
27658 uint64_t resp_addr;
27659 /* The source function id. */
27662 uint8_t tunnel_type;
27664 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_INFO_INPUT_TUNNEL_TYPE_NONTUNNEL \
27666 /* Virtual eXtensible Local Area Network (VXLAN) */
27667 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_INFO_INPUT_TUNNEL_TYPE_VXLAN \
27669 /* Network Virtualization Generic Routing Encapsulation (NVGRE) */
27670 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_INFO_INPUT_TUNNEL_TYPE_NVGRE \
27672 /* Generic Routing Encapsulation (GRE) inside Ethernet payload */
27673 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_INFO_INPUT_TUNNEL_TYPE_L2GRE \
27676 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_INFO_INPUT_TUNNEL_TYPE_IPIP \
27678 /* Generic Network Virtualization Encapsulation (Geneve) */
27679 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_INFO_INPUT_TUNNEL_TYPE_GENEVE \
27681 /* Multi-Protocol Label Switching (MPLS) */
27682 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_INFO_INPUT_TUNNEL_TYPE_MPLS \
27684 /* Stateless Transport Tunnel (STT) */
27685 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_INFO_INPUT_TUNNEL_TYPE_STT \
27687 /* Generic Routing Encapsulation (GRE) inside IP datagram payload */
27688 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_INFO_INPUT_TUNNEL_TYPE_IPGRE \
27690 /* IPV4 over virtual eXtensible Local Area Network (IPV4oVXLAN) */
27691 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_INFO_INPUT_TUNNEL_TYPE_VXLAN_V4 \
27693 /* Enhance Generic Routing Encapsulation (GRE version 1) inside IP datagram payload */
27694 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_INFO_INPUT_TUNNEL_TYPE_IPGRE_V1 \
27696 /* Use fixed layer 2 ether type of 0xFFFF */
27697 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_INFO_INPUT_TUNNEL_TYPE_L2_ETYPE \
27699 /* IPV6 over virtual eXtensible Local Area Network with GPE header (IPV6oVXLANGPE) */
27700 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_INFO_INPUT_TUNNEL_TYPE_VXLAN_GPE_V6 \
27702 /* Any tunneled traffic */
27703 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_INFO_INPUT_TUNNEL_TYPE_ANYTUNNEL \
27705 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_INFO_INPUT_TUNNEL_TYPE_LAST \
27706 HWRM_CFA_REDIRECT_TUNNEL_TYPE_INFO_INPUT_TUNNEL_TYPE_ANYTUNNEL
27707 uint8_t unused_0[5];
27710 /* hwrm_cfa_redirect_tunnel_type_info_output (size:128b/16B) */
27711 struct hwrm_cfa_redirect_tunnel_type_info_output {
27712 /* The specific error status for the command. */
27713 uint16_t error_code;
27714 /* The HWRM command request type. */
27716 /* The sequence ID from the original command. */
27718 /* The length of the response data in number of bytes. */
27720 /* The destination function id, to whom the traffic is redirected. */
27722 uint8_t unused_0[5];
27724 * This field is used in Output records to indicate that the output
27725 * is completely written to RAM. This field should be read as '1'
27726 * to indicate that the output has been completely written.
27727 * When writing a command completion or response to an internal processor,
27728 * the order of writes has to be such that this field is written last.
27733 /* hwrm_vxlan_ipv4_hdr (size:128b/16B) */
27734 struct hwrm_vxlan_ipv4_hdr {
27735 /* IPv4 version and header length. */
27737 /* IPv4 header length */
27738 #define HWRM_VXLAN_IPV4_HDR_VER_HLEN_HEADER_LENGTH_MASK UINT32_C(0xf)
27739 #define HWRM_VXLAN_IPV4_HDR_VER_HLEN_HEADER_LENGTH_SFT 0
27741 #define HWRM_VXLAN_IPV4_HDR_VER_HLEN_VERSION_MASK UINT32_C(0xf0)
27742 #define HWRM_VXLAN_IPV4_HDR_VER_HLEN_VERSION_SFT 4
27743 /* IPv4 type of service. */
27745 /* IPv4 identification. */
27747 /* IPv4 flags and offset. */
27748 uint16_t flags_frag_offset;
27751 /* IPv4 protocol. */
27753 /* IPv4 source address. */
27754 uint32_t src_ip_addr;
27755 /* IPv4 destination address. */
27756 uint32_t dest_ip_addr;
27759 /* hwrm_vxlan_ipv6_hdr (size:320b/40B) */
27760 struct hwrm_vxlan_ipv6_hdr {
27761 /* IPv6 version, traffic class and flow label. */
27762 uint32_t ver_tc_flow_label;
27763 /* IPv6 version shift */
27764 #define HWRM_VXLAN_IPV6_HDR_VER_TC_FLOW_LABEL_VER_SFT \
27766 /* IPv6 version mask */
27767 #define HWRM_VXLAN_IPV6_HDR_VER_TC_FLOW_LABEL_VER_MASK \
27768 UINT32_C(0xf0000000)
27769 /* IPv6 TC shift */
27770 #define HWRM_VXLAN_IPV6_HDR_VER_TC_FLOW_LABEL_TC_SFT \
27773 #define HWRM_VXLAN_IPV6_HDR_VER_TC_FLOW_LABEL_TC_MASK \
27774 UINT32_C(0xff00000)
27775 /* IPv6 flow label shift */
27776 #define HWRM_VXLAN_IPV6_HDR_VER_TC_FLOW_LABEL_FLOW_LABEL_SFT \
27778 /* IPv6 flow label mask */
27779 #define HWRM_VXLAN_IPV6_HDR_VER_TC_FLOW_LABEL_FLOW_LABEL_MASK \
27781 #define HWRM_VXLAN_IPV6_HDR_VER_TC_FLOW_LABEL_LAST \
27782 HWRM_VXLAN_IPV6_HDR_VER_TC_FLOW_LABEL_FLOW_LABEL_MASK
27783 /* IPv6 payload length. */
27784 uint16_t payload_len;
27785 /* IPv6 next header. */
27789 /* IPv6 source address. */
27790 uint32_t src_ip_addr[4];
27791 /* IPv6 destination address. */
27792 uint32_t dest_ip_addr[4];
27795 /* hwrm_cfa_encap_data_vxlan (size:640b/80B) */
27796 struct hwrm_cfa_encap_data_vxlan {
27797 /* Source MAC address. */
27798 uint8_t src_mac_addr[6];
27801 /* Destination MAC address. */
27802 uint8_t dst_mac_addr[6];
27803 /* Number of VLAN tags. */
27804 uint8_t num_vlan_tags;
27807 /* Outer VLAN TPID. */
27808 uint16_t ovlan_tpid;
27809 /* Outer VLAN TCI. */
27810 uint16_t ovlan_tci;
27811 /* Inner VLAN TPID. */
27812 uint16_t ivlan_tpid;
27813 /* Inner VLAN TCI. */
27814 uint16_t ivlan_tci;
27815 /* L3 header fields. */
27817 /* IP version mask. */
27818 #define HWRM_CFA_ENCAP_DATA_VXLAN_L3_VER_MASK UINT32_C(0xf)
27819 /* IP version 4. */
27820 #define HWRM_CFA_ENCAP_DATA_VXLAN_L3_VER_IPV4 UINT32_C(0x4)
27821 /* IP version 6. */
27822 #define HWRM_CFA_ENCAP_DATA_VXLAN_L3_VER_IPV6 UINT32_C(0x6)
27823 #define HWRM_CFA_ENCAP_DATA_VXLAN_L3_LAST \
27824 HWRM_CFA_ENCAP_DATA_VXLAN_L3_VER_IPV6
27825 /* UDP source port. */
27827 /* UDP destination port. */
27829 /* VXLAN Network Identifier. */
27831 /* 3 bytes VXLAN header reserve fields from 1st dword of the VXLAN header. */
27832 uint8_t hdr_rsvd0[3];
27833 /* 1 byte VXLAN header reserve field from 2nd dword of the VXLAN header. */
27835 /* VXLAN header flags field. */
27840 /*******************************
27841 * hwrm_cfa_encap_record_alloc *
27842 *******************************/
27845 /* hwrm_cfa_encap_record_alloc_input (size:832b/104B) */
27846 struct hwrm_cfa_encap_record_alloc_input {
27847 /* The HWRM command request type. */
27850 * The completion ring to send the completion event on. This should
27851 * be the NQ ID returned from the `nq_alloc` HWRM command.
27853 uint16_t cmpl_ring;
27855 * The sequence ID is used by the driver for tracking multiple
27856 * commands. This ID is treated as opaque data by the firmware and
27857 * the value is returned in the `hwrm_resp_hdr` upon completion.
27861 * The target ID of the command:
27862 * * 0x0-0xFFF8 - The function ID
27863 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
27864 * * 0xFFFD - Reserved for user-space HWRM interface
27867 uint16_t target_id;
27869 * A physical address pointer pointing to a host buffer that the
27870 * command's response data will be written. This can be either a host
27871 * physical address (HPA) or a guest physical address (GPA) and must
27872 * point to a physically contiguous block of memory.
27874 uint64_t resp_addr;
27876 /* Setting of this flag indicates the applicability to the loopback path. */
27877 #define HWRM_CFA_ENCAP_RECORD_ALLOC_INPUT_FLAGS_LOOPBACK \
27880 * Setting of this flag indicates this encap record is external encap record.
27881 * Resetting of this flag indicates this flag is internal encap record and
27882 * this is the default setting.
27884 #define HWRM_CFA_ENCAP_RECORD_ALLOC_INPUT_FLAGS_EXTERNAL \
27886 /* Encapsulation Type. */
27887 uint8_t encap_type;
27888 /* Virtual eXtensible Local Area Network (VXLAN) */
27889 #define HWRM_CFA_ENCAP_RECORD_ALLOC_INPUT_ENCAP_TYPE_VXLAN \
27891 /* Network Virtualization Generic Routing Encapsulation (NVGRE) */
27892 #define HWRM_CFA_ENCAP_RECORD_ALLOC_INPUT_ENCAP_TYPE_NVGRE \
27894 /* Generic Routing Encapsulation (GRE) after inside Ethernet payload */
27895 #define HWRM_CFA_ENCAP_RECORD_ALLOC_INPUT_ENCAP_TYPE_L2GRE \
27898 #define HWRM_CFA_ENCAP_RECORD_ALLOC_INPUT_ENCAP_TYPE_IPIP \
27900 /* Generic Network Virtualization Encapsulation (Geneve) */
27901 #define HWRM_CFA_ENCAP_RECORD_ALLOC_INPUT_ENCAP_TYPE_GENEVE \
27903 /* Multi-Protocol Label Switching (MPLS) */
27904 #define HWRM_CFA_ENCAP_RECORD_ALLOC_INPUT_ENCAP_TYPE_MPLS \
27907 #define HWRM_CFA_ENCAP_RECORD_ALLOC_INPUT_ENCAP_TYPE_VLAN \
27909 /* Generic Routing Encapsulation (GRE) inside IP datagram payload */
27910 #define HWRM_CFA_ENCAP_RECORD_ALLOC_INPUT_ENCAP_TYPE_IPGRE \
27912 /* IPV4 over virtual eXtensible Local Area Network (IPV4oVXLAN) */
27913 #define HWRM_CFA_ENCAP_RECORD_ALLOC_INPUT_ENCAP_TYPE_VXLAN_V4 \
27915 /* Enhance Generic Routing Encapsulation (GRE version 1) inside IP datagram payload */
27916 #define HWRM_CFA_ENCAP_RECORD_ALLOC_INPUT_ENCAP_TYPE_IPGRE_V1 \
27918 /* Use fixed layer 2 ether type of 0xFFFF */
27919 #define HWRM_CFA_ENCAP_RECORD_ALLOC_INPUT_ENCAP_TYPE_L2_ETYPE \
27921 /* IPV6 over virtual eXtensible Local Area Network with GPE header (IPV6oVXLANGPE) */
27922 #define HWRM_CFA_ENCAP_RECORD_ALLOC_INPUT_ENCAP_TYPE_VXLAN_GPE_V6 \
27924 #define HWRM_CFA_ENCAP_RECORD_ALLOC_INPUT_ENCAP_TYPE_LAST \
27925 HWRM_CFA_ENCAP_RECORD_ALLOC_INPUT_ENCAP_TYPE_VXLAN_GPE_V6
27926 uint8_t unused_0[3];
27927 /* This value is encap data used for the given encap type. */
27928 uint32_t encap_data[20];
27931 /* hwrm_cfa_encap_record_alloc_output (size:128b/16B) */
27932 struct hwrm_cfa_encap_record_alloc_output {
27933 /* The specific error status for the command. */
27934 uint16_t error_code;
27935 /* The HWRM command request type. */
27937 /* The sequence ID from the original command. */
27939 /* The length of the response data in number of bytes. */
27941 /* This value is an opaque id into CFA data structures. */
27942 uint32_t encap_record_id;
27943 uint8_t unused_0[3];
27945 * This field is used in Output records to indicate that the output
27946 * is completely written to RAM. This field should be read as '1'
27947 * to indicate that the output has been completely written.
27948 * When writing a command completion or response to an internal processor,
27949 * the order of writes has to be such that this field is written last.
27954 /******************************
27955 * hwrm_cfa_encap_record_free *
27956 ******************************/
27959 /* hwrm_cfa_encap_record_free_input (size:192b/24B) */
27960 struct hwrm_cfa_encap_record_free_input {
27961 /* The HWRM command request type. */
27964 * The completion ring to send the completion event on. This should
27965 * be the NQ ID returned from the `nq_alloc` HWRM command.
27967 uint16_t cmpl_ring;
27969 * The sequence ID is used by the driver for tracking multiple
27970 * commands. This ID is treated as opaque data by the firmware and
27971 * the value is returned in the `hwrm_resp_hdr` upon completion.
27975 * The target ID of the command:
27976 * * 0x0-0xFFF8 - The function ID
27977 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
27978 * * 0xFFFD - Reserved for user-space HWRM interface
27981 uint16_t target_id;
27983 * A physical address pointer pointing to a host buffer that the
27984 * command's response data will be written. This can be either a host
27985 * physical address (HPA) or a guest physical address (GPA) and must
27986 * point to a physically contiguous block of memory.
27988 uint64_t resp_addr;
27989 /* This value is an opaque id into CFA data structures. */
27990 uint32_t encap_record_id;
27991 uint8_t unused_0[4];
27994 /* hwrm_cfa_encap_record_free_output (size:128b/16B) */
27995 struct hwrm_cfa_encap_record_free_output {
27996 /* The specific error status for the command. */
27997 uint16_t error_code;
27998 /* The HWRM command request type. */
28000 /* The sequence ID from the original command. */
28002 /* The length of the response data in number of bytes. */
28004 uint8_t unused_0[7];
28006 * This field is used in Output records to indicate that the output
28007 * is completely written to RAM. This field should be read as '1'
28008 * to indicate that the output has been completely written.
28009 * When writing a command completion or response to an internal processor,
28010 * the order of writes has to be such that this field is written last.
28015 /********************************
28016 * hwrm_cfa_ntuple_filter_alloc *
28017 ********************************/
28020 /* hwrm_cfa_ntuple_filter_alloc_input (size:1024b/128B) */
28021 struct hwrm_cfa_ntuple_filter_alloc_input {
28022 /* The HWRM command request type. */
28025 * The completion ring to send the completion event on. This should
28026 * be the NQ ID returned from the `nq_alloc` HWRM command.
28028 uint16_t cmpl_ring;
28030 * The sequence ID is used by the driver for tracking multiple
28031 * commands. This ID is treated as opaque data by the firmware and
28032 * the value is returned in the `hwrm_resp_hdr` upon completion.
28036 * The target ID of the command:
28037 * * 0x0-0xFFF8 - The function ID
28038 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
28039 * * 0xFFFD - Reserved for user-space HWRM interface
28042 uint16_t target_id;
28044 * A physical address pointer pointing to a host buffer that the
28045 * command's response data will be written. This can be either a host
28046 * physical address (HPA) or a guest physical address (GPA) and must
28047 * point to a physically contiguous block of memory.
28049 uint64_t resp_addr;
28051 /* Setting of this flag indicates the applicability to the loopback path. */
28052 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_FLAGS_LOOPBACK \
28055 * Setting of this flag indicates drop action. If this flag is not set,
28056 * then it should be considered accept action.
28058 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_FLAGS_DROP \
28061 * Setting of this flag indicates that a meter is expected to be attached
28062 * to this flow. This hint can be used when choosing the action record
28063 * format required for the flow.
28065 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_FLAGS_METER \
28068 * Setting of this flag indicates that the dst_id field contains function ID.
28069 * If this is not set it indicates dest_id is VNIC or VPORT.
28071 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_FLAGS_DEST_FID \
28074 * Setting of this flag indicates match on arp reply when ethertype is 0x0806.
28075 * If this is not set it indicates no specific arp opcode matching.
28077 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_FLAGS_ARP_REPLY \
28080 * Setting of this flag indicates that the dst_id field contains RFS ring
28081 * table index. If this is not set it indicates dst_id is VNIC or VPORT
28082 * or function ID. Note dest_fid and dest_rfs_ring_idx can’t be set at
28085 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_FLAGS_DEST_RFS_RING_IDX \
28089 * This bit must be '1' for the l2_filter_id field to be
28092 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_L2_FILTER_ID \
28095 * This bit must be '1' for the ethertype field to be
28098 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_ETHERTYPE \
28101 * This bit must be '1' for the tunnel_type field to be
28104 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_TUNNEL_TYPE \
28107 * This bit must be '1' for the src_macaddr field to be
28110 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_SRC_MACADDR \
28113 * This bit must be '1' for the ipaddr_type field to be
28116 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_IPADDR_TYPE \
28119 * This bit must be '1' for the src_ipaddr field to be
28122 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_SRC_IPADDR \
28125 * This bit must be '1' for the src_ipaddr_mask field to be
28128 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_SRC_IPADDR_MASK \
28131 * This bit must be '1' for the dst_ipaddr field to be
28134 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_IPADDR \
28137 * This bit must be '1' for the dst_ipaddr_mask field to be
28140 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_IPADDR_MASK \
28143 * This bit must be '1' for the ip_protocol field to be
28146 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_IP_PROTOCOL \
28149 * This bit must be '1' for the src_port field to be
28152 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_SRC_PORT \
28155 * This bit must be '1' for the src_port_mask field to be
28158 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_SRC_PORT_MASK \
28161 * This bit must be '1' for the dst_port field to be
28164 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_PORT \
28167 * This bit must be '1' for the dst_port_mask field to be
28170 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_PORT_MASK \
28173 * This bit must be '1' for the pri_hint field to be
28176 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_PRI_HINT \
28179 * This bit must be '1' for the ntuple_filter_id field to be
28182 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_NTUPLE_FILTER_ID \
28185 * This bit must be '1' for the dst_id field to be
28188 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_ID \
28191 * This bit must be '1' for the mirror_vnic_id field to be
28194 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_MIRROR_VNIC_ID \
28197 * This bit must be '1' for the dst_macaddr field to be
28200 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_MACADDR \
28202 /* This flag is deprecated. */
28203 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_RFS_RING_TBL_IDX \
28206 * This value identifies a set of CFA data structures used for an L2
28209 uint64_t l2_filter_id;
28211 * This value indicates the source MAC address in
28212 * the Ethernet header.
28214 uint8_t src_macaddr[6];
28215 /* This value indicates the ethertype in the Ethernet header. */
28216 uint16_t ethertype;
28218 * This value indicates the type of IP address.
28221 * All others are invalid.
28223 uint8_t ip_addr_type;
28225 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_IP_ADDR_TYPE_UNKNOWN \
28228 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_IP_ADDR_TYPE_IPV4 \
28231 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_IP_ADDR_TYPE_IPV6 \
28233 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_IP_ADDR_TYPE_LAST \
28234 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_IP_ADDR_TYPE_IPV6
28236 * The value of protocol filed in IP header.
28237 * Applies to UDP and TCP traffic.
28241 uint8_t ip_protocol;
28243 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_IP_PROTOCOL_UNKNOWN \
28246 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_IP_PROTOCOL_TCP \
28249 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_IP_PROTOCOL_UDP \
28251 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_IP_PROTOCOL_LAST \
28252 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_IP_PROTOCOL_UDP
28254 * If set, this value shall represent the
28255 * Logical VNIC ID of the destination VNIC for the RX
28256 * path and network port id of the destination port for
28261 * Logical VNIC ID of the VNIC where traffic is
28264 uint16_t mirror_vnic_id;
28266 * This value indicates the tunnel type for this filter.
28267 * If this field is not specified, then the filter shall
28268 * apply to both non-tunneled and tunneled packets.
28269 * If this field conflicts with the tunnel_type specified
28270 * in the l2_filter_id, then the HWRM shall return an
28271 * error for this command.
28273 uint8_t tunnel_type;
28275 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_TUNNEL_TYPE_NONTUNNEL \
28277 /* Virtual eXtensible Local Area Network (VXLAN) */
28278 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_TUNNEL_TYPE_VXLAN \
28280 /* Network Virtualization Generic Routing Encapsulation (NVGRE) */
28281 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_TUNNEL_TYPE_NVGRE \
28283 /* Generic Routing Encapsulation (GRE) inside Ethernet payload */
28284 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_TUNNEL_TYPE_L2GRE \
28287 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_TUNNEL_TYPE_IPIP \
28289 /* Generic Network Virtualization Encapsulation (Geneve) */
28290 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_TUNNEL_TYPE_GENEVE \
28292 /* Multi-Protocol Label Switching (MPLS) */
28293 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_TUNNEL_TYPE_MPLS \
28295 /* Stateless Transport Tunnel (STT) */
28296 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_TUNNEL_TYPE_STT \
28298 /* Generic Routing Encapsulation (GRE) inside IP datagram payload */
28299 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_TUNNEL_TYPE_IPGRE \
28301 /* IPV4 over virtual eXtensible Local Area Network (IPV4oVXLAN) */
28302 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_TUNNEL_TYPE_VXLAN_V4 \
28304 /* Enhance Generic Routing Encapsulation (GRE version 1) inside IP datagram payload */
28305 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_TUNNEL_TYPE_IPGRE_V1 \
28307 /* Use fixed layer 2 ether type of 0xFFFF */
28308 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_TUNNEL_TYPE_L2_ETYPE \
28310 /* IPV6 over virtual eXtensible Local Area Network with GPE header (IPV6oVXLANGPE) */
28311 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_TUNNEL_TYPE_VXLAN_GPE_V6 \
28313 /* Any tunneled traffic */
28314 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_TUNNEL_TYPE_ANYTUNNEL \
28316 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_TUNNEL_TYPE_LAST \
28317 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_TUNNEL_TYPE_ANYTUNNEL
28319 * This hint is provided to help in placing
28320 * the filter in the filter table.
28323 /* No preference */
28324 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_PRI_HINT_NO_PREFER \
28326 /* Above the given filter */
28327 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_PRI_HINT_ABOVE \
28329 /* Below the given filter */
28330 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_PRI_HINT_BELOW \
28332 /* As high as possible */
28333 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_PRI_HINT_HIGHEST \
28335 /* As low as possible */
28336 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_PRI_HINT_LOWEST \
28338 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_PRI_HINT_LAST \
28339 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_PRI_HINT_LOWEST
28341 * The value of source IP address to be used in filtering.
28342 * For IPv4, first four bytes represent the IP address.
28344 uint32_t src_ipaddr[4];
28346 * The value of source IP address mask to be used in
28348 * For IPv4, first four bytes represent the IP address mask.
28350 uint32_t src_ipaddr_mask[4];
28352 * The value of destination IP address to be used in filtering.
28353 * For IPv4, first four bytes represent the IP address.
28355 uint32_t dst_ipaddr[4];
28357 * The value of destination IP address mask to be used in
28359 * For IPv4, first four bytes represent the IP address mask.
28361 uint32_t dst_ipaddr_mask[4];
28363 * The value of source port to be used in filtering.
28364 * Applies to UDP and TCP traffic.
28368 * The value of source port mask to be used in filtering.
28369 * Applies to UDP and TCP traffic.
28371 uint16_t src_port_mask;
28373 * The value of destination port to be used in filtering.
28374 * Applies to UDP and TCP traffic.
28378 * The value of destination port mask to be used in
28380 * Applies to UDP and TCP traffic.
28382 uint16_t dst_port_mask;
28384 * This is the ID of the filter that goes along with
28387 uint64_t ntuple_filter_id_hint;
28390 /* hwrm_cfa_ntuple_filter_alloc_output (size:192b/24B) */
28391 struct hwrm_cfa_ntuple_filter_alloc_output {
28392 /* The specific error status for the command. */
28393 uint16_t error_code;
28394 /* The HWRM command request type. */
28396 /* The sequence ID from the original command. */
28398 /* The length of the response data in number of bytes. */
28400 /* This value is an opaque id into CFA data structures. */
28401 uint64_t ntuple_filter_id;
28403 * The flow id value in bit 0-29 is the actual ID of the flow
28404 * associated with this filter and it shall be used to match
28405 * and associate the flow identifier returned in completion
28406 * records. A value of 0xFFFFFFFF in the 32-bit flow_id field
28407 * shall indicate no valid flow id.
28410 /* Indicate the flow id value. */
28411 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_OUTPUT_FLOW_ID_VALUE_MASK \
28412 UINT32_C(0x3fffffff)
28413 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_OUTPUT_FLOW_ID_VALUE_SFT 0
28414 /* Indicate type of the flow. */
28415 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_OUTPUT_FLOW_ID_TYPE \
28416 UINT32_C(0x40000000)
28418 * If this bit set to 0, then it indicates that the flow is
28421 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_OUTPUT_FLOW_ID_TYPE_INT \
28422 (UINT32_C(0x0) << 30)
28424 * If this bit is set to 1, then it indicates that the flow is
28427 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_OUTPUT_FLOW_ID_TYPE_EXT \
28428 (UINT32_C(0x1) << 30)
28429 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_OUTPUT_FLOW_ID_TYPE_LAST \
28430 HWRM_CFA_NTUPLE_FILTER_ALLOC_OUTPUT_FLOW_ID_TYPE_EXT
28431 /* Indicate the flow direction. */
28432 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_OUTPUT_FLOW_ID_DIR \
28433 UINT32_C(0x80000000)
28434 /* If this bit set to 0, then it indicates rx flow. */
28435 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_OUTPUT_FLOW_ID_DIR_RX \
28436 (UINT32_C(0x0) << 31)
28437 /* If this bit is set to 1, then it indicates that tx flow. */
28438 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_OUTPUT_FLOW_ID_DIR_TX \
28439 (UINT32_C(0x1) << 31)
28440 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_OUTPUT_FLOW_ID_DIR_LAST \
28441 HWRM_CFA_NTUPLE_FILTER_ALLOC_OUTPUT_FLOW_ID_DIR_TX
28442 uint8_t unused_0[3];
28444 * This field is used in Output records to indicate that the output
28445 * is completely written to RAM. This field should be read as '1'
28446 * to indicate that the output has been completely written.
28447 * When writing a command completion or response to an internal processor,
28448 * the order of writes has to be such that this field is written last.
28453 /* hwrm_cfa_ntuple_filter_alloc_cmd_err (size:64b/8B) */
28454 struct hwrm_cfa_ntuple_filter_alloc_cmd_err {
28456 * command specific error codes that goes to
28457 * the cmd_err field in Common HWRM Error Response.
28460 /* Unknown error */
28461 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_CMD_ERR_CODE_UNKNOWN \
28463 /* Unable to complete operation due to conflict with Rx Mask VLAN */
28464 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_CMD_ERR_CODE_RX_MASK_VLAN_CONFLICT_ERR \
28466 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_CMD_ERR_CODE_LAST \
28467 HWRM_CFA_NTUPLE_FILTER_ALLOC_CMD_ERR_CODE_RX_MASK_VLAN_CONFLICT_ERR
28468 uint8_t unused_0[7];
28471 /*******************************
28472 * hwrm_cfa_ntuple_filter_free *
28473 *******************************/
28476 /* hwrm_cfa_ntuple_filter_free_input (size:192b/24B) */
28477 struct hwrm_cfa_ntuple_filter_free_input {
28478 /* The HWRM command request type. */
28481 * The completion ring to send the completion event on. This should
28482 * be the NQ ID returned from the `nq_alloc` HWRM command.
28484 uint16_t cmpl_ring;
28486 * The sequence ID is used by the driver for tracking multiple
28487 * commands. This ID is treated as opaque data by the firmware and
28488 * the value is returned in the `hwrm_resp_hdr` upon completion.
28492 * The target ID of the command:
28493 * * 0x0-0xFFF8 - The function ID
28494 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
28495 * * 0xFFFD - Reserved for user-space HWRM interface
28498 uint16_t target_id;
28500 * A physical address pointer pointing to a host buffer that the
28501 * command's response data will be written. This can be either a host
28502 * physical address (HPA) or a guest physical address (GPA) and must
28503 * point to a physically contiguous block of memory.
28505 uint64_t resp_addr;
28506 /* This value is an opaque id into CFA data structures. */
28507 uint64_t ntuple_filter_id;
28510 /* hwrm_cfa_ntuple_filter_free_output (size:128b/16B) */
28511 struct hwrm_cfa_ntuple_filter_free_output {
28512 /* The specific error status for the command. */
28513 uint16_t error_code;
28514 /* The HWRM command request type. */
28516 /* The sequence ID from the original command. */
28518 /* The length of the response data in number of bytes. */
28520 uint8_t unused_0[7];
28522 * This field is used in Output records to indicate that the output
28523 * is completely written to RAM. This field should be read as '1'
28524 * to indicate that the output has been completely written.
28525 * When writing a command completion or response to an internal processor,
28526 * the order of writes has to be such that this field is written last.
28531 /******************************
28532 * hwrm_cfa_ntuple_filter_cfg *
28533 ******************************/
28536 /* hwrm_cfa_ntuple_filter_cfg_input (size:384b/48B) */
28537 struct hwrm_cfa_ntuple_filter_cfg_input {
28538 /* The HWRM command request type. */
28541 * The completion ring to send the completion event on. This should
28542 * be the NQ ID returned from the `nq_alloc` HWRM command.
28544 uint16_t cmpl_ring;
28546 * The sequence ID is used by the driver for tracking multiple
28547 * commands. This ID is treated as opaque data by the firmware and
28548 * the value is returned in the `hwrm_resp_hdr` upon completion.
28552 * The target ID of the command:
28553 * * 0x0-0xFFF8 - The function ID
28554 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
28555 * * 0xFFFD - Reserved for user-space HWRM interface
28558 uint16_t target_id;
28560 * A physical address pointer pointing to a host buffer that the
28561 * command's response data will be written. This can be either a host
28562 * physical address (HPA) or a guest physical address (GPA) and must
28563 * point to a physically contiguous block of memory.
28565 uint64_t resp_addr;
28568 * This bit must be '1' for the new_dst_id field to be
28571 #define HWRM_CFA_NTUPLE_FILTER_CFG_INPUT_ENABLES_NEW_DST_ID \
28574 * This bit must be '1' for the new_mirror_vnic_id field to be
28577 #define HWRM_CFA_NTUPLE_FILTER_CFG_INPUT_ENABLES_NEW_MIRROR_VNIC_ID \
28580 * This bit must be '1' for the new_meter_instance_id field to be
28583 #define HWRM_CFA_NTUPLE_FILTER_CFG_INPUT_ENABLES_NEW_METER_INSTANCE_ID \
28587 * Setting this bit to 1 indicates that dest_id field contains FID.
28588 * Setting this to 0 indicates that dest_id field contains VNIC or VPORT.
28590 #define HWRM_CFA_NTUPLE_FILTER_CFG_INPUT_FLAGS_DEST_FID \
28593 * Setting of this flag indicates that the new_dst_id field contains
28594 * RFS ring table index. If this is not set it indicates new_dst_id is
28595 * VNIC or VPORT or function ID. Note dest_fid and dest_rfs_ring_idx
28596 * can’t be set at the same time.
28598 #define HWRM_CFA_NTUPLE_FILTER_CFG_INPUT_FLAGS_DEST_RFS_RING_IDX \
28600 /* This value is an opaque id into CFA data structures. */
28601 uint64_t ntuple_filter_id;
28603 * If set, this value shall represent the new
28604 * Logical VNIC ID of the destination VNIC for the RX
28605 * path and new network port id of the destination port for
28608 uint32_t new_dst_id;
28610 * New Logical VNIC ID of the VNIC where traffic is
28613 uint32_t new_mirror_vnic_id;
28615 * New meter to attach to the flow. Specifying the
28616 * invalid instance ID is used to remove any existing
28617 * meter from the flow.
28619 uint16_t new_meter_instance_id;
28621 * A value of 0xfff is considered invalid and implies the
28622 * instance is not configured.
28624 #define HWRM_CFA_NTUPLE_FILTER_CFG_INPUT_NEW_METER_INSTANCE_ID_INVALID \
28626 #define HWRM_CFA_NTUPLE_FILTER_CFG_INPUT_NEW_METER_INSTANCE_ID_LAST \
28627 HWRM_CFA_NTUPLE_FILTER_CFG_INPUT_NEW_METER_INSTANCE_ID_INVALID
28628 uint8_t unused_1[6];
28631 /* hwrm_cfa_ntuple_filter_cfg_output (size:128b/16B) */
28632 struct hwrm_cfa_ntuple_filter_cfg_output {
28633 /* The specific error status for the command. */
28634 uint16_t error_code;
28635 /* The HWRM command request type. */
28637 /* The sequence ID from the original command. */
28639 /* The length of the response data in number of bytes. */
28641 uint8_t unused_0[7];
28643 * This field is used in Output records to indicate that the output
28644 * is completely written to RAM. This field should be read as '1'
28645 * to indicate that the output has been completely written.
28646 * When writing a command completion or response to an internal processor,
28647 * the order of writes has to be such that this field is written last.
28652 /**************************
28653 * hwrm_cfa_em_flow_alloc *
28654 **************************/
28657 /* hwrm_cfa_em_flow_alloc_input (size:896b/112B) */
28658 struct hwrm_cfa_em_flow_alloc_input {
28659 /* The HWRM command request type. */
28662 * The completion ring to send the completion event on. This should
28663 * be the NQ ID returned from the `nq_alloc` HWRM command.
28665 uint16_t cmpl_ring;
28667 * The sequence ID is used by the driver for tracking multiple
28668 * commands. This ID is treated as opaque data by the firmware and
28669 * the value is returned in the `hwrm_resp_hdr` upon completion.
28673 * The target ID of the command:
28674 * * 0x0-0xFFF8 - The function ID
28675 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
28676 * * 0xFFFD - Reserved for user-space HWRM interface
28679 uint16_t target_id;
28681 * A physical address pointer pointing to a host buffer that the
28682 * command's response data will be written. This can be either a host
28683 * physical address (HPA) or a guest physical address (GPA) and must
28684 * point to a physically contiguous block of memory.
28686 uint64_t resp_addr;
28689 * Enumeration denoting the RX, TX type of the resource.
28690 * This enumeration is used for resources that are similar for both
28691 * TX and RX paths of the chip.
28693 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_FLAGS_PATH UINT32_C(0x1)
28695 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_FLAGS_PATH_TX UINT32_C(0x0)
28697 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_FLAGS_PATH_RX UINT32_C(0x1)
28698 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_FLAGS_PATH_LAST \
28699 HWRM_CFA_EM_FLOW_ALLOC_INPUT_FLAGS_PATH_RX
28701 * Setting of this flag indicates enabling of a byte counter for a given
28704 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_FLAGS_BYTE_CTR UINT32_C(0x2)
28706 * Setting of this flag indicates enabling of a packet counter for a given
28709 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_FLAGS_PKT_CTR UINT32_C(0x4)
28710 /* Setting of this flag indicates de-capsulation action for the given flow. */
28711 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_FLAGS_DECAP UINT32_C(0x8)
28712 /* Setting of this flag indicates encapsulation action for the given flow. */
28713 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_FLAGS_ENCAP UINT32_C(0x10)
28715 * Setting of this flag indicates drop action. If this flag is not set,
28716 * then it should be considered accept action.
28718 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_FLAGS_DROP UINT32_C(0x20)
28720 * Setting of this flag indicates that a meter is expected to be attached
28721 * to this flow. This hint can be used when choosing the action record
28722 * format required for the flow.
28724 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_FLAGS_METER UINT32_C(0x40)
28727 * This bit must be '1' for the l2_filter_id field to be
28730 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_L2_FILTER_ID \
28733 * This bit must be '1' for the tunnel_type field to be
28736 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_TUNNEL_TYPE \
28739 * This bit must be '1' for the tunnel_id field to be
28742 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_TUNNEL_ID \
28745 * This bit must be '1' for the src_macaddr field to be
28748 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_SRC_MACADDR \
28751 * This bit must be '1' for the dst_macaddr field to be
28754 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_DST_MACADDR \
28757 * This bit must be '1' for the ovlan_vid field to be
28760 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_OVLAN_VID \
28763 * This bit must be '1' for the ivlan_vid field to be
28766 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_IVLAN_VID \
28769 * This bit must be '1' for the ethertype field to be
28772 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_ETHERTYPE \
28775 * This bit must be '1' for the src_ipaddr field to be
28778 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_SRC_IPADDR \
28781 * This bit must be '1' for the dst_ipaddr field to be
28784 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_DST_IPADDR \
28787 * This bit must be '1' for the ipaddr_type field to be
28790 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_IPADDR_TYPE \
28793 * This bit must be '1' for the ip_protocol field to be
28796 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_IP_PROTOCOL \
28799 * This bit must be '1' for the src_port field to be
28802 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_SRC_PORT \
28805 * This bit must be '1' for the dst_port field to be
28808 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_DST_PORT \
28811 * This bit must be '1' for the dst_id field to be
28814 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_DST_ID \
28817 * This bit must be '1' for the mirror_vnic_id field to be
28820 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_MIRROR_VNIC_ID \
28823 * This bit must be '1' for the encap_record_id field to be
28826 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_ENCAP_RECORD_ID \
28829 * This bit must be '1' for the meter_instance_id field to be
28832 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_METER_INSTANCE_ID \
28835 * This value identifies a set of CFA data structures used for an L2
28838 uint64_t l2_filter_id;
28840 uint8_t tunnel_type;
28842 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_TUNNEL_TYPE_NONTUNNEL \
28844 /* Virtual eXtensible Local Area Network (VXLAN) */
28845 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_TUNNEL_TYPE_VXLAN \
28847 /* Network Virtualization Generic Routing Encapsulation (NVGRE) */
28848 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_TUNNEL_TYPE_NVGRE \
28850 /* Generic Routing Encapsulation (GRE) inside Ethernet payload */
28851 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_TUNNEL_TYPE_L2GRE \
28854 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_TUNNEL_TYPE_IPIP \
28856 /* Generic Network Virtualization Encapsulation (Geneve) */
28857 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_TUNNEL_TYPE_GENEVE \
28859 /* Multi-Protocol Label Switching (MPLS) */
28860 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_TUNNEL_TYPE_MPLS \
28862 /* Stateless Transport Tunnel (STT) */
28863 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_TUNNEL_TYPE_STT \
28865 /* Generic Routing Encapsulation (GRE) inside IP datagram payload */
28866 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_TUNNEL_TYPE_IPGRE \
28868 /* IPV4 over virtual eXtensible Local Area Network (IPV4oVXLAN) */
28869 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_TUNNEL_TYPE_VXLAN_V4 \
28871 /* Enhance Generic Routing Encapsulation (GRE version 1) inside IP datagram payload */
28872 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_TUNNEL_TYPE_IPGRE_V1 \
28874 /* Use fixed layer 2 ether type of 0xFFFF */
28875 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_TUNNEL_TYPE_L2_ETYPE \
28877 /* IPV6 over virtual eXtensible Local Area Network with GPE header (IPV6oVXLANGPE) */
28878 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_TUNNEL_TYPE_VXLAN_GPE_V6 \
28880 /* Any tunneled traffic */
28881 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_TUNNEL_TYPE_ANYTUNNEL \
28883 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_TUNNEL_TYPE_LAST \
28884 HWRM_CFA_EM_FLOW_ALLOC_INPUT_TUNNEL_TYPE_ANYTUNNEL
28885 uint8_t unused_0[3];
28887 * Tunnel identifier.
28888 * Virtual Network Identifier (VNI). Only valid with
28889 * tunnel_types VXLAN, NVGRE, and Geneve.
28890 * Only lower 24-bits of VNI field are used
28891 * in setting up the filter.
28893 uint32_t tunnel_id;
28895 * This value indicates the source MAC address in
28896 * the Ethernet header.
28898 uint8_t src_macaddr[6];
28899 /* The meter instance to attach to the flow. */
28900 uint16_t meter_instance_id;
28902 * A value of 0xfff is considered invalid and implies the
28903 * instance is not configured.
28905 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_METER_INSTANCE_ID_INVALID \
28907 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_METER_INSTANCE_ID_LAST \
28908 HWRM_CFA_EM_FLOW_ALLOC_INPUT_METER_INSTANCE_ID_INVALID
28910 * This value indicates the destination MAC address in
28911 * the Ethernet header.
28913 uint8_t dst_macaddr[6];
28915 * This value indicates the VLAN ID of the outer VLAN tag
28916 * in the Ethernet header.
28918 uint16_t ovlan_vid;
28920 * This value indicates the VLAN ID of the inner VLAN tag
28921 * in the Ethernet header.
28923 uint16_t ivlan_vid;
28924 /* This value indicates the ethertype in the Ethernet header. */
28925 uint16_t ethertype;
28927 * This value indicates the type of IP address.
28930 * All others are invalid.
28932 uint8_t ip_addr_type;
28934 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_IP_ADDR_TYPE_UNKNOWN UINT32_C(0x0)
28936 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_IP_ADDR_TYPE_IPV4 UINT32_C(0x4)
28938 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_IP_ADDR_TYPE_IPV6 UINT32_C(0x6)
28939 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_IP_ADDR_TYPE_LAST \
28940 HWRM_CFA_EM_FLOW_ALLOC_INPUT_IP_ADDR_TYPE_IPV6
28942 * The value of protocol filed in IP header.
28943 * Applies to UDP and TCP traffic.
28947 uint8_t ip_protocol;
28949 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_IP_PROTOCOL_UNKNOWN UINT32_C(0x0)
28951 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_IP_PROTOCOL_TCP UINT32_C(0x6)
28953 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_IP_PROTOCOL_UDP UINT32_C(0x11)
28954 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_IP_PROTOCOL_LAST \
28955 HWRM_CFA_EM_FLOW_ALLOC_INPUT_IP_PROTOCOL_UDP
28956 uint8_t unused_1[2];
28958 * The value of source IP address to be used in filtering.
28959 * For IPv4, first four bytes represent the IP address.
28961 uint32_t src_ipaddr[4];
28963 * big_endian = True
28964 * The value of destination IP address to be used in filtering.
28965 * For IPv4, first four bytes represent the IP address.
28967 uint32_t dst_ipaddr[4];
28969 * The value of source port to be used in filtering.
28970 * Applies to UDP and TCP traffic.
28974 * The value of destination port to be used in filtering.
28975 * Applies to UDP and TCP traffic.
28979 * If set, this value shall represent the
28980 * Logical VNIC ID of the destination VNIC for the RX
28981 * path and network port id of the destination port for
28986 * Logical VNIC ID of the VNIC where traffic is
28989 uint16_t mirror_vnic_id;
28990 /* Logical ID of the encapsulation record. */
28991 uint32_t encap_record_id;
28992 uint8_t unused_2[4];
28995 /* hwrm_cfa_em_flow_alloc_output (size:192b/24B) */
28996 struct hwrm_cfa_em_flow_alloc_output {
28997 /* The specific error status for the command. */
28998 uint16_t error_code;
28999 /* The HWRM command request type. */
29001 /* The sequence ID from the original command. */
29003 /* The length of the response data in number of bytes. */
29005 /* This value is an opaque id into CFA data structures. */
29006 uint64_t em_filter_id;
29008 * The flow id value in bit 0-29 is the actual ID of the flow
29009 * associated with this filter and it shall be used to match
29010 * and associate the flow identifier returned in completion
29011 * records. A value of 0xFFFFFFFF in the 32-bit flow_id field
29012 * shall indicate no valid flow id.
29015 /* Indicate the flow id value. */
29016 #define HWRM_CFA_EM_FLOW_ALLOC_OUTPUT_FLOW_ID_VALUE_MASK \
29017 UINT32_C(0x3fffffff)
29018 #define HWRM_CFA_EM_FLOW_ALLOC_OUTPUT_FLOW_ID_VALUE_SFT 0
29019 /* Indicate type of the flow. */
29020 #define HWRM_CFA_EM_FLOW_ALLOC_OUTPUT_FLOW_ID_TYPE \
29021 UINT32_C(0x40000000)
29023 * If this bit set to 0, then it indicates that the flow is
29026 #define HWRM_CFA_EM_FLOW_ALLOC_OUTPUT_FLOW_ID_TYPE_INT \
29027 (UINT32_C(0x0) << 30)
29029 * If this bit is set to 1, then it indicates that the flow is
29032 #define HWRM_CFA_EM_FLOW_ALLOC_OUTPUT_FLOW_ID_TYPE_EXT \
29033 (UINT32_C(0x1) << 30)
29034 #define HWRM_CFA_EM_FLOW_ALLOC_OUTPUT_FLOW_ID_TYPE_LAST \
29035 HWRM_CFA_EM_FLOW_ALLOC_OUTPUT_FLOW_ID_TYPE_EXT
29036 /* Indicate the flow direction. */
29037 #define HWRM_CFA_EM_FLOW_ALLOC_OUTPUT_FLOW_ID_DIR \
29038 UINT32_C(0x80000000)
29039 /* If this bit set to 0, then it indicates rx flow. */
29040 #define HWRM_CFA_EM_FLOW_ALLOC_OUTPUT_FLOW_ID_DIR_RX \
29041 (UINT32_C(0x0) << 31)
29042 /* If this bit is set to 1, then it indicates that tx flow. */
29043 #define HWRM_CFA_EM_FLOW_ALLOC_OUTPUT_FLOW_ID_DIR_TX \
29044 (UINT32_C(0x1) << 31)
29045 #define HWRM_CFA_EM_FLOW_ALLOC_OUTPUT_FLOW_ID_DIR_LAST \
29046 HWRM_CFA_EM_FLOW_ALLOC_OUTPUT_FLOW_ID_DIR_TX
29047 uint8_t unused_0[3];
29049 * This field is used in Output records to indicate that the output
29050 * is completely written to RAM. This field should be read as '1'
29051 * to indicate that the output has been completely written.
29052 * When writing a command completion or response to an internal processor,
29053 * the order of writes has to be such that this field is written last.
29058 /*************************
29059 * hwrm_cfa_em_flow_free *
29060 *************************/
29063 /* hwrm_cfa_em_flow_free_input (size:192b/24B) */
29064 struct hwrm_cfa_em_flow_free_input {
29065 /* The HWRM command request type. */
29068 * The completion ring to send the completion event on. This should
29069 * be the NQ ID returned from the `nq_alloc` HWRM command.
29071 uint16_t cmpl_ring;
29073 * The sequence ID is used by the driver for tracking multiple
29074 * commands. This ID is treated as opaque data by the firmware and
29075 * the value is returned in the `hwrm_resp_hdr` upon completion.
29079 * The target ID of the command:
29080 * * 0x0-0xFFF8 - The function ID
29081 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
29082 * * 0xFFFD - Reserved for user-space HWRM interface
29085 uint16_t target_id;
29087 * A physical address pointer pointing to a host buffer that the
29088 * command's response data will be written. This can be either a host
29089 * physical address (HPA) or a guest physical address (GPA) and must
29090 * point to a physically contiguous block of memory.
29092 uint64_t resp_addr;
29093 /* This value is an opaque id into CFA data structures. */
29094 uint64_t em_filter_id;
29097 /* hwrm_cfa_em_flow_free_output (size:128b/16B) */
29098 struct hwrm_cfa_em_flow_free_output {
29099 /* The specific error status for the command. */
29100 uint16_t error_code;
29101 /* The HWRM command request type. */
29103 /* The sequence ID from the original command. */
29105 /* The length of the response data in number of bytes. */
29107 uint8_t unused_0[7];
29109 * This field is used in Output records to indicate that the output
29110 * is completely written to RAM. This field should be read as '1'
29111 * to indicate that the output has been completely written.
29112 * When writing a command completion or response to an internal processor,
29113 * the order of writes has to be such that this field is written last.
29118 /************************
29119 * hwrm_cfa_meter_qcaps *
29120 ************************/
29123 /* hwrm_cfa_meter_qcaps_input (size:128b/16B) */
29124 struct hwrm_cfa_meter_qcaps_input {
29125 /* The HWRM command request type. */
29128 * The completion ring to send the completion event on. This should
29129 * be the NQ ID returned from the `nq_alloc` HWRM command.
29131 uint16_t cmpl_ring;
29133 * The sequence ID is used by the driver for tracking multiple
29134 * commands. This ID is treated as opaque data by the firmware and
29135 * the value is returned in the `hwrm_resp_hdr` upon completion.
29139 * The target ID of the command:
29140 * * 0x0-0xFFF8 - The function ID
29141 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
29142 * * 0xFFFD - Reserved for user-space HWRM interface
29145 uint16_t target_id;
29147 * A physical address pointer pointing to a host buffer that the
29148 * command's response data will be written. This can be either a host
29149 * physical address (HPA) or a guest physical address (GPA) and must
29150 * point to a physically contiguous block of memory.
29152 uint64_t resp_addr;
29155 /* hwrm_cfa_meter_qcaps_output (size:320b/40B) */
29156 struct hwrm_cfa_meter_qcaps_output {
29157 /* The specific error status for the command. */
29158 uint16_t error_code;
29159 /* The HWRM command request type. */
29161 /* The sequence ID from the original command. */
29163 /* The length of the response data in number of bytes. */
29167 * Enumeration denoting the clock at which the Meter is running with.
29168 * This enumeration is used for resources that are similar for both
29169 * TX and RX paths of the chip.
29171 #define HWRM_CFA_METER_QCAPS_OUTPUT_FLAGS_CLOCK_MASK UINT32_C(0xf)
29172 #define HWRM_CFA_METER_QCAPS_OUTPUT_FLAGS_CLOCK_SFT 0
29174 #define HWRM_CFA_METER_QCAPS_OUTPUT_FLAGS_CLOCK_375MHZ UINT32_C(0x0)
29176 #define HWRM_CFA_METER_QCAPS_OUTPUT_FLAGS_CLOCK_625MHZ UINT32_C(0x1)
29177 #define HWRM_CFA_METER_QCAPS_OUTPUT_FLAGS_CLOCK_LAST \
29178 HWRM_CFA_METER_QCAPS_OUTPUT_FLAGS_CLOCK_625MHZ
29179 uint8_t unused_0[4];
29181 * The minimum guaranteed number of tx meter profiles supported
29182 * for this function.
29184 uint16_t min_tx_profile;
29186 * The maximum non-guaranteed number of tx meter profiles supported
29187 * for this function.
29189 uint16_t max_tx_profile;
29191 * The minimum guaranteed number of rx meter profiles supported
29192 * for this function.
29194 uint16_t min_rx_profile;
29196 * The maximum non-guaranteed number of rx meter profiles supported
29197 * for this function.
29199 uint16_t max_rx_profile;
29201 * The minimum guaranteed number of tx meter instances supported
29202 * for this function.
29204 uint16_t min_tx_instance;
29206 * The maximum non-guaranteed number of tx meter instances supported
29207 * for this function.
29209 uint16_t max_tx_instance;
29211 * The minimum guaranteed number of rx meter instances supported
29212 * for this function.
29214 uint16_t min_rx_instance;
29216 * The maximum non-guaranteed number of rx meter instances supported
29217 * for this function.
29219 uint16_t max_rx_instance;
29220 uint8_t unused_1[7];
29222 * This field is used in Output records to indicate that the output
29223 * is completely written to RAM. This field should be read as '1'
29224 * to indicate that the output has been completely written.
29225 * When writing a command completion or response to an internal processor,
29226 * the order of writes has to be such that this field is written last.
29231 /********************************
29232 * hwrm_cfa_meter_profile_alloc *
29233 ********************************/
29236 /* hwrm_cfa_meter_profile_alloc_input (size:320b/40B) */
29237 struct hwrm_cfa_meter_profile_alloc_input {
29238 /* The HWRM command request type. */
29241 * The completion ring to send the completion event on. This should
29242 * be the NQ ID returned from the `nq_alloc` HWRM command.
29244 uint16_t cmpl_ring;
29246 * The sequence ID is used by the driver for tracking multiple
29247 * commands. This ID is treated as opaque data by the firmware and
29248 * the value is returned in the `hwrm_resp_hdr` upon completion.
29252 * The target ID of the command:
29253 * * 0x0-0xFFF8 - The function ID
29254 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
29255 * * 0xFFFD - Reserved for user-space HWRM interface
29258 uint16_t target_id;
29260 * A physical address pointer pointing to a host buffer that the
29261 * command's response data will be written. This can be either a host
29262 * physical address (HPA) or a guest physical address (GPA) and must
29263 * point to a physically contiguous block of memory.
29265 uint64_t resp_addr;
29268 * Enumeration denoting the RX, TX type of the resource.
29269 * This enumeration is used for resources that are similar for both
29270 * TX and RX paths of the chip.
29272 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_FLAGS_PATH UINT32_C(0x1)
29274 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_FLAGS_PATH_TX \
29277 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_FLAGS_PATH_RX \
29279 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_FLAGS_PATH_LAST \
29280 HWRM_CFA_METER_PROFILE_ALLOC_INPUT_FLAGS_PATH_RX
29281 /* The meter algorithm type. */
29282 uint8_t meter_type;
29283 /* RFC 2697 (srTCM) */
29284 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_METER_TYPE_RFC2697 \
29286 /* RFC 2698 (trTCM) */
29287 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_METER_TYPE_RFC2698 \
29289 /* RFC 4115 (trTCM) */
29290 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_METER_TYPE_RFC4115 \
29292 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_METER_TYPE_LAST \
29293 HWRM_CFA_METER_PROFILE_ALLOC_INPUT_METER_TYPE_RFC4115
29295 * This field is reserved for the future use.
29296 * It shall be set to 0.
29298 uint16_t reserved1;
29300 * This field is reserved for the future use.
29301 * It shall be set to 0.
29303 uint32_t reserved2;
29304 /* A meter rate specified in bytes-per-second. */
29305 uint32_t commit_rate;
29306 /* The bandwidth value. */
29307 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_RATE_BW_VALUE_MASK \
29308 UINT32_C(0xfffffff)
29309 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_RATE_BW_VALUE_SFT \
29311 /* The granularity of the value (bits or bytes). */
29312 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_RATE_SCALE \
29313 UINT32_C(0x10000000)
29314 /* Value is in bits. */
29315 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_RATE_SCALE_BITS \
29316 (UINT32_C(0x0) << 28)
29317 /* Value is in bytes. */
29318 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_RATE_SCALE_BYTES \
29319 (UINT32_C(0x1) << 28)
29320 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_RATE_SCALE_LAST \
29321 HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_RATE_SCALE_BYTES
29322 /* bw_value_unit is 3 b */
29323 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_RATE_BW_VALUE_UNIT_MASK \
29324 UINT32_C(0xe0000000)
29325 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_RATE_BW_VALUE_UNIT_SFT \
29327 /* Value is in Mb or MB (base 10). */
29328 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_RATE_BW_VALUE_UNIT_MEGA \
29329 (UINT32_C(0x0) << 29)
29330 /* Value is in Kb or KB (base 10). */
29331 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_RATE_BW_VALUE_UNIT_KILO \
29332 (UINT32_C(0x2) << 29)
29333 /* Value is in bits or bytes. */
29334 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_RATE_BW_VALUE_UNIT_BASE \
29335 (UINT32_C(0x4) << 29)
29336 /* Value is in Gb or GB (base 10). */
29337 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_RATE_BW_VALUE_UNIT_GIGA \
29338 (UINT32_C(0x6) << 29)
29339 /* Value is in 1/100th of a percentage of total bandwidth. */
29340 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_RATE_BW_VALUE_UNIT_PERCENT1_100 \
29341 (UINT32_C(0x1) << 29)
29343 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_RATE_BW_VALUE_UNIT_RAW \
29344 (UINT32_C(0x7) << 29)
29345 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_RATE_BW_VALUE_UNIT_LAST \
29346 HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_RATE_BW_VALUE_UNIT_RAW
29347 /* A meter burst size specified in bytes. */
29348 uint32_t commit_burst;
29349 /* The bandwidth value. */
29350 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_BURST_BW_VALUE_MASK \
29351 UINT32_C(0xfffffff)
29352 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_BURST_BW_VALUE_SFT \
29354 /* The granularity of the value (bits or bytes). */
29355 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_BURST_SCALE \
29356 UINT32_C(0x10000000)
29357 /* Value is in bits. */
29358 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_BURST_SCALE_BITS \
29359 (UINT32_C(0x0) << 28)
29360 /* Value is in bytes. */
29361 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_BURST_SCALE_BYTES \
29362 (UINT32_C(0x1) << 28)
29363 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_BURST_SCALE_LAST \
29364 HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_BURST_SCALE_BYTES
29365 /* bw_value_unit is 3 b */
29366 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_BURST_BW_VALUE_UNIT_MASK \
29367 UINT32_C(0xe0000000)
29368 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_BURST_BW_VALUE_UNIT_SFT \
29370 /* Value is in Mb or MB (base 10). */
29371 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_BURST_BW_VALUE_UNIT_MEGA \
29372 (UINT32_C(0x0) << 29)
29373 /* Value is in Kb or KB (base 10). */
29374 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_BURST_BW_VALUE_UNIT_KILO \
29375 (UINT32_C(0x2) << 29)
29376 /* Value is in bits or bytes. */
29377 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_BURST_BW_VALUE_UNIT_BASE \
29378 (UINT32_C(0x4) << 29)
29379 /* Value is in Gb or GB (base 10). */
29380 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_BURST_BW_VALUE_UNIT_GIGA \
29381 (UINT32_C(0x6) << 29)
29382 /* Value is in 1/100th of a percentage of total bandwidth. */
29383 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_BURST_BW_VALUE_UNIT_PERCENT1_100 \
29384 (UINT32_C(0x1) << 29)
29385 /* Invalid value */
29386 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_BURST_BW_VALUE_UNIT_INVALID \
29387 (UINT32_C(0x7) << 29)
29388 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_BURST_BW_VALUE_UNIT_LAST \
29389 HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_BURST_BW_VALUE_UNIT_INVALID
29390 /* A meter rate specified in bytes-per-second. */
29391 uint32_t excess_peak_rate;
29392 /* The bandwidth value. */
29393 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_RATE_BW_VALUE_MASK \
29394 UINT32_C(0xfffffff)
29395 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_RATE_BW_VALUE_SFT \
29397 /* The granularity of the value (bits or bytes). */
29398 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_RATE_SCALE \
29399 UINT32_C(0x10000000)
29400 /* Value is in bits. */
29401 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_RATE_SCALE_BITS \
29402 (UINT32_C(0x0) << 28)
29403 /* Value is in bytes. */
29404 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_RATE_SCALE_BYTES \
29405 (UINT32_C(0x1) << 28)
29406 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_RATE_SCALE_LAST \
29407 HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_RATE_SCALE_BYTES
29408 /* bw_value_unit is 3 b */
29409 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_RATE_BW_VALUE_UNIT_MASK \
29410 UINT32_C(0xe0000000)
29411 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_RATE_BW_VALUE_UNIT_SFT \
29413 /* Value is in Mb or MB (base 10). */
29414 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_RATE_BW_VALUE_UNIT_MEGA \
29415 (UINT32_C(0x0) << 29)
29416 /* Value is in Kb or KB (base 10). */
29417 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_RATE_BW_VALUE_UNIT_KILO \
29418 (UINT32_C(0x2) << 29)
29419 /* Value is in bits or bytes. */
29420 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_RATE_BW_VALUE_UNIT_BASE \
29421 (UINT32_C(0x4) << 29)
29422 /* Value is in Gb or GB (base 10). */
29423 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_RATE_BW_VALUE_UNIT_GIGA \
29424 (UINT32_C(0x6) << 29)
29425 /* Value is in 1/100th of a percentage of total bandwidth. */
29426 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_RATE_BW_VALUE_UNIT_PERCENT1_100 \
29427 (UINT32_C(0x1) << 29)
29429 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_RATE_BW_VALUE_UNIT_RAW \
29430 (UINT32_C(0x7) << 29)
29431 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_RATE_BW_VALUE_UNIT_LAST \
29432 HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_RATE_BW_VALUE_UNIT_RAW
29433 /* A meter burst size specified in bytes. */
29434 uint32_t excess_peak_burst;
29435 /* The bandwidth value. */
29436 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_BURST_BW_VALUE_MASK \
29437 UINT32_C(0xfffffff)
29438 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_BURST_BW_VALUE_SFT \
29440 /* The granularity of the value (bits or bytes). */
29441 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_BURST_SCALE \
29442 UINT32_C(0x10000000)
29443 /* Value is in bits. */
29444 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_BURST_SCALE_BITS \
29445 (UINT32_C(0x0) << 28)
29446 /* Value is in bytes. */
29447 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_BURST_SCALE_BYTES \
29448 (UINT32_C(0x1) << 28)
29449 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_BURST_SCALE_LAST \
29450 HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_BURST_SCALE_BYTES
29451 /* bw_value_unit is 3 b */
29452 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_BURST_BW_VALUE_UNIT_MASK \
29453 UINT32_C(0xe0000000)
29454 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_BURST_BW_VALUE_UNIT_SFT \
29456 /* Value is in Mb or MB (base 10). */
29457 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_BURST_BW_VALUE_UNIT_MEGA \
29458 (UINT32_C(0x0) << 29)
29459 /* Value is in Kb or KB (base 10). */
29460 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_BURST_BW_VALUE_UNIT_KILO \
29461 (UINT32_C(0x2) << 29)
29462 /* Value is in bits or bytes. */
29463 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_BURST_BW_VALUE_UNIT_BASE \
29464 (UINT32_C(0x4) << 29)
29465 /* Value is in Gb or GB (base 10). */
29466 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_BURST_BW_VALUE_UNIT_GIGA \
29467 (UINT32_C(0x6) << 29)
29468 /* Value is in 1/100th of a percentage of total bandwidth. */
29469 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_BURST_BW_VALUE_UNIT_PERCENT1_100 \
29470 (UINT32_C(0x1) << 29)
29472 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_BURST_BW_VALUE_UNIT_INVALID \
29473 (UINT32_C(0x7) << 29)
29474 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_BURST_BW_VALUE_UNIT_LAST \
29475 HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_BURST_BW_VALUE_UNIT_INVALID
29478 /* hwrm_cfa_meter_profile_alloc_output (size:128b/16B) */
29479 struct hwrm_cfa_meter_profile_alloc_output {
29480 /* The specific error status for the command. */
29481 uint16_t error_code;
29482 /* The HWRM command request type. */
29484 /* The sequence ID from the original command. */
29486 /* The length of the response data in number of bytes. */
29488 /* This value identifies a meter profile in CFA. */
29489 uint16_t meter_profile_id;
29491 * A value of 0xfff is considered invalid and implies the
29492 * profile is not configured.
29494 #define HWRM_CFA_METER_PROFILE_ALLOC_OUTPUT_METER_PROFILE_ID_INVALID \
29496 #define HWRM_CFA_METER_PROFILE_ALLOC_OUTPUT_METER_PROFILE_ID_LAST \
29497 HWRM_CFA_METER_PROFILE_ALLOC_OUTPUT_METER_PROFILE_ID_INVALID
29498 uint8_t unused_0[5];
29500 * This field is used in Output records to indicate that the output
29501 * is completely written to RAM. This field should be read as '1'
29502 * to indicate that the output has been completely written.
29503 * When writing a command completion or response to an internal processor,
29504 * the order of writes has to be such that this field is written last.
29509 /*******************************
29510 * hwrm_cfa_meter_profile_free *
29511 *******************************/
29514 /* hwrm_cfa_meter_profile_free_input (size:192b/24B) */
29515 struct hwrm_cfa_meter_profile_free_input {
29516 /* The HWRM command request type. */
29519 * The completion ring to send the completion event on. This should
29520 * be the NQ ID returned from the `nq_alloc` HWRM command.
29522 uint16_t cmpl_ring;
29524 * The sequence ID is used by the driver for tracking multiple
29525 * commands. This ID is treated as opaque data by the firmware and
29526 * the value is returned in the `hwrm_resp_hdr` upon completion.
29530 * The target ID of the command:
29531 * * 0x0-0xFFF8 - The function ID
29532 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
29533 * * 0xFFFD - Reserved for user-space HWRM interface
29536 uint16_t target_id;
29538 * A physical address pointer pointing to a host buffer that the
29539 * command's response data will be written. This can be either a host
29540 * physical address (HPA) or a guest physical address (GPA) and must
29541 * point to a physically contiguous block of memory.
29543 uint64_t resp_addr;
29546 * Enumeration denoting the RX, TX type of the resource.
29547 * This enumeration is used for resources that are similar for both
29548 * TX and RX paths of the chip.
29550 #define HWRM_CFA_METER_PROFILE_FREE_INPUT_FLAGS_PATH UINT32_C(0x1)
29552 #define HWRM_CFA_METER_PROFILE_FREE_INPUT_FLAGS_PATH_TX \
29555 #define HWRM_CFA_METER_PROFILE_FREE_INPUT_FLAGS_PATH_RX \
29557 #define HWRM_CFA_METER_PROFILE_FREE_INPUT_FLAGS_PATH_LAST \
29558 HWRM_CFA_METER_PROFILE_FREE_INPUT_FLAGS_PATH_RX
29560 /* This value identifies a meter profile in CFA. */
29561 uint16_t meter_profile_id;
29563 * A value of 0xfff is considered invalid and implies the
29564 * profile is not configured.
29566 #define HWRM_CFA_METER_PROFILE_FREE_INPUT_METER_PROFILE_ID_INVALID \
29568 #define HWRM_CFA_METER_PROFILE_FREE_INPUT_METER_PROFILE_ID_LAST \
29569 HWRM_CFA_METER_PROFILE_FREE_INPUT_METER_PROFILE_ID_INVALID
29570 uint8_t unused_1[4];
29573 /* hwrm_cfa_meter_profile_free_output (size:128b/16B) */
29574 struct hwrm_cfa_meter_profile_free_output {
29575 /* The specific error status for the command. */
29576 uint16_t error_code;
29577 /* The HWRM command request type. */
29579 /* The sequence ID from the original command. */
29581 /* The length of the response data in number of bytes. */
29583 uint8_t unused_0[7];
29585 * This field is used in Output records to indicate that the output
29586 * is completely written to RAM. This field should be read as '1'
29587 * to indicate that the output has been completely written.
29588 * When writing a command completion or response to an internal processor,
29589 * the order of writes has to be such that this field is written last.
29594 /******************************
29595 * hwrm_cfa_meter_profile_cfg *
29596 ******************************/
29599 /* hwrm_cfa_meter_profile_cfg_input (size:320b/40B) */
29600 struct hwrm_cfa_meter_profile_cfg_input {
29601 /* The HWRM command request type. */
29604 * The completion ring to send the completion event on. This should
29605 * be the NQ ID returned from the `nq_alloc` HWRM command.
29607 uint16_t cmpl_ring;
29609 * The sequence ID is used by the driver for tracking multiple
29610 * commands. This ID is treated as opaque data by the firmware and
29611 * the value is returned in the `hwrm_resp_hdr` upon completion.
29615 * The target ID of the command:
29616 * * 0x0-0xFFF8 - The function ID
29617 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
29618 * * 0xFFFD - Reserved for user-space HWRM interface
29621 uint16_t target_id;
29623 * A physical address pointer pointing to a host buffer that the
29624 * command's response data will be written. This can be either a host
29625 * physical address (HPA) or a guest physical address (GPA) and must
29626 * point to a physically contiguous block of memory.
29628 uint64_t resp_addr;
29631 * Enumeration denoting the RX, TX type of the resource.
29632 * This enumeration is used for resources that are similar for both
29633 * TX and RX paths of the chip.
29635 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_FLAGS_PATH UINT32_C(0x1)
29637 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_FLAGS_PATH_TX UINT32_C(0x0)
29639 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_FLAGS_PATH_RX UINT32_C(0x1)
29640 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_FLAGS_PATH_LAST \
29641 HWRM_CFA_METER_PROFILE_CFG_INPUT_FLAGS_PATH_RX
29642 /* The meter algorithm type. */
29643 uint8_t meter_type;
29644 /* RFC 2697 (srTCM) */
29645 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_METER_TYPE_RFC2697 \
29647 /* RFC 2698 (trTCM) */
29648 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_METER_TYPE_RFC2698 \
29650 /* RFC 4115 (trTCM) */
29651 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_METER_TYPE_RFC4115 \
29653 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_METER_TYPE_LAST \
29654 HWRM_CFA_METER_PROFILE_CFG_INPUT_METER_TYPE_RFC4115
29655 /* This value identifies a meter profile in CFA. */
29656 uint16_t meter_profile_id;
29658 * A value of 0xfff is considered invalid and implies the
29659 * profile is not configured.
29661 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_METER_PROFILE_ID_INVALID \
29663 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_METER_PROFILE_ID_LAST \
29664 HWRM_CFA_METER_PROFILE_CFG_INPUT_METER_PROFILE_ID_INVALID
29666 * This field is reserved for the future use.
29667 * It shall be set to 0.
29670 /* A meter rate specified in bytes-per-second. */
29671 uint32_t commit_rate;
29672 /* The bandwidth value. */
29673 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_RATE_BW_VALUE_MASK \
29674 UINT32_C(0xfffffff)
29675 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_RATE_BW_VALUE_SFT \
29677 /* The granularity of the value (bits or bytes). */
29678 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_RATE_SCALE \
29679 UINT32_C(0x10000000)
29680 /* Value is in bits. */
29681 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_RATE_SCALE_BITS \
29682 (UINT32_C(0x0) << 28)
29683 /* Value is in bytes. */
29684 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_RATE_SCALE_BYTES \
29685 (UINT32_C(0x1) << 28)
29686 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_RATE_SCALE_LAST \
29687 HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_RATE_SCALE_BYTES
29688 /* bw_value_unit is 3 b */
29689 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_RATE_BW_VALUE_UNIT_MASK \
29690 UINT32_C(0xe0000000)
29691 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_RATE_BW_VALUE_UNIT_SFT \
29693 /* Value is in Mb or MB (base 10). */
29694 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_RATE_BW_VALUE_UNIT_MEGA \
29695 (UINT32_C(0x0) << 29)
29696 /* Value is in Kb or KB (base 10). */
29697 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_RATE_BW_VALUE_UNIT_KILO \
29698 (UINT32_C(0x2) << 29)
29699 /* Value is in bits or bytes. */
29700 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_RATE_BW_VALUE_UNIT_BASE \
29701 (UINT32_C(0x4) << 29)
29702 /* Value is in Gb or GB (base 10). */
29703 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_RATE_BW_VALUE_UNIT_GIGA \
29704 (UINT32_C(0x6) << 29)
29705 /* Value is in 1/100th of a percentage of total bandwidth. */
29706 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_RATE_BW_VALUE_UNIT_PERCENT1_100 \
29707 (UINT32_C(0x1) << 29)
29709 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_RATE_BW_VALUE_UNIT_RAW \
29710 (UINT32_C(0x7) << 29)
29711 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_RATE_BW_VALUE_UNIT_LAST \
29712 HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_RATE_BW_VALUE_UNIT_RAW
29713 /* A meter burst size specified in bytes. */
29714 uint32_t commit_burst;
29715 /* The bandwidth value. */
29716 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_BURST_BW_VALUE_MASK \
29717 UINT32_C(0xfffffff)
29718 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_BURST_BW_VALUE_SFT \
29720 /* The granularity of the value (bits or bytes). */
29721 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_BURST_SCALE \
29722 UINT32_C(0x10000000)
29723 /* Value is in bits. */
29724 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_BURST_SCALE_BITS \
29725 (UINT32_C(0x0) << 28)
29726 /* Value is in bytes. */
29727 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_BURST_SCALE_BYTES \
29728 (UINT32_C(0x1) << 28)
29729 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_BURST_SCALE_LAST \
29730 HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_BURST_SCALE_BYTES
29731 /* bw_value_unit is 3 b */
29732 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_BURST_BW_VALUE_UNIT_MASK \
29733 UINT32_C(0xe0000000)
29734 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_BURST_BW_VALUE_UNIT_SFT \
29736 /* Value is in Mb or MB (base 10). */
29737 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_BURST_BW_VALUE_UNIT_MEGA \
29738 (UINT32_C(0x0) << 29)
29739 /* Value is in Kb or KB (base 10). */
29740 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_BURST_BW_VALUE_UNIT_KILO \
29741 (UINT32_C(0x2) << 29)
29742 /* Value is in bits or bytes. */
29743 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_BURST_BW_VALUE_UNIT_BASE \
29744 (UINT32_C(0x4) << 29)
29745 /* Value is in Gb or GB (base 10). */
29746 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_BURST_BW_VALUE_UNIT_GIGA \
29747 (UINT32_C(0x6) << 29)
29748 /* Value is in 1/100th of a percentage of total bandwidth. */
29749 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_BURST_BW_VALUE_UNIT_PERCENT1_100 \
29750 (UINT32_C(0x1) << 29)
29751 /* Invalid value */
29752 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_BURST_BW_VALUE_UNIT_INVALID \
29753 (UINT32_C(0x7) << 29)
29754 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_BURST_BW_VALUE_UNIT_LAST \
29755 HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_BURST_BW_VALUE_UNIT_INVALID
29756 /* A meter rate specified in bytes-per-second. */
29757 uint32_t excess_peak_rate;
29758 /* The bandwidth value. */
29759 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_RATE_BW_VALUE_MASK \
29760 UINT32_C(0xfffffff)
29761 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_RATE_BW_VALUE_SFT \
29763 /* The granularity of the value (bits or bytes). */
29764 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_RATE_SCALE \
29765 UINT32_C(0x10000000)
29766 /* Value is in bits. */
29767 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_RATE_SCALE_BITS \
29768 (UINT32_C(0x0) << 28)
29769 /* Value is in bytes. */
29770 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_RATE_SCALE_BYTES \
29771 (UINT32_C(0x1) << 28)
29772 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_RATE_SCALE_LAST \
29773 HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_RATE_SCALE_BYTES
29774 /* bw_value_unit is 3 b */
29775 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_RATE_BW_VALUE_UNIT_MASK \
29776 UINT32_C(0xe0000000)
29777 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_RATE_BW_VALUE_UNIT_SFT \
29779 /* Value is in Mb or MB (base 10). */
29780 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_RATE_BW_VALUE_UNIT_MEGA \
29781 (UINT32_C(0x0) << 29)
29782 /* Value is in Kb or KB (base 10). */
29783 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_RATE_BW_VALUE_UNIT_KILO \
29784 (UINT32_C(0x2) << 29)
29785 /* Value is in bits or bytes. */
29786 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_RATE_BW_VALUE_UNIT_BASE \
29787 (UINT32_C(0x4) << 29)
29788 /* Value is in Gb or GB (base 10). */
29789 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_RATE_BW_VALUE_UNIT_GIGA \
29790 (UINT32_C(0x6) << 29)
29791 /* Value is in 1/100th of a percentage of total bandwidth. */
29792 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_RATE_BW_VALUE_UNIT_PERCENT1_100 \
29793 (UINT32_C(0x1) << 29)
29795 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_RATE_BW_VALUE_UNIT_RAW \
29796 (UINT32_C(0x7) << 29)
29797 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_RATE_BW_VALUE_UNIT_LAST \
29798 HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_RATE_BW_VALUE_UNIT_RAW
29799 /* A meter burst size specified in bytes. */
29800 uint32_t excess_peak_burst;
29801 /* The bandwidth value. */
29802 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_BURST_BW_VALUE_MASK \
29803 UINT32_C(0xfffffff)
29804 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_BURST_BW_VALUE_SFT \
29806 /* The granularity of the value (bits or bytes). */
29807 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_BURST_SCALE \
29808 UINT32_C(0x10000000)
29809 /* Value is in bits. */
29810 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_BURST_SCALE_BITS \
29811 (UINT32_C(0x0) << 28)
29812 /* Value is in bytes. */
29813 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_BURST_SCALE_BYTES \
29814 (UINT32_C(0x1) << 28)
29815 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_BURST_SCALE_LAST \
29816 HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_BURST_SCALE_BYTES
29817 /* bw_value_unit is 3 b */
29818 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_BURST_BW_VALUE_UNIT_MASK \
29819 UINT32_C(0xe0000000)
29820 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_BURST_BW_VALUE_UNIT_SFT \
29822 /* Value is in Mb or MB (base 10). */
29823 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_BURST_BW_VALUE_UNIT_MEGA \
29824 (UINT32_C(0x0) << 29)
29825 /* Value is in Kb or KB (base 10). */
29826 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_BURST_BW_VALUE_UNIT_KILO \
29827 (UINT32_C(0x2) << 29)
29828 /* Value is in bits or bytes. */
29829 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_BURST_BW_VALUE_UNIT_BASE \
29830 (UINT32_C(0x4) << 29)
29831 /* Value is in Gb or GB (base 10). */
29832 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_BURST_BW_VALUE_UNIT_GIGA \
29833 (UINT32_C(0x6) << 29)
29834 /* Value is in 1/100th of a percentage of total bandwidth. */
29835 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_BURST_BW_VALUE_UNIT_PERCENT1_100 \
29836 (UINT32_C(0x1) << 29)
29838 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_BURST_BW_VALUE_UNIT_INVALID \
29839 (UINT32_C(0x7) << 29)
29840 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_BURST_BW_VALUE_UNIT_LAST \
29841 HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_BURST_BW_VALUE_UNIT_INVALID
29844 /* hwrm_cfa_meter_profile_cfg_output (size:128b/16B) */
29845 struct hwrm_cfa_meter_profile_cfg_output {
29846 /* The specific error status for the command. */
29847 uint16_t error_code;
29848 /* The HWRM command request type. */
29850 /* The sequence ID from the original command. */
29852 /* The length of the response data in number of bytes. */
29854 uint8_t unused_0[7];
29856 * This field is used in Output records to indicate that the output
29857 * is completely written to RAM. This field should be read as '1'
29858 * to indicate that the output has been completely written.
29859 * When writing a command completion or response to an internal processor,
29860 * the order of writes has to be such that this field is written last.
29865 /*********************************
29866 * hwrm_cfa_meter_instance_alloc *
29867 *********************************/
29870 /* hwrm_cfa_meter_instance_alloc_input (size:192b/24B) */
29871 struct hwrm_cfa_meter_instance_alloc_input {
29872 /* The HWRM command request type. */
29875 * The completion ring to send the completion event on. This should
29876 * be the NQ ID returned from the `nq_alloc` HWRM command.
29878 uint16_t cmpl_ring;
29880 * The sequence ID is used by the driver for tracking multiple
29881 * commands. This ID is treated as opaque data by the firmware and
29882 * the value is returned in the `hwrm_resp_hdr` upon completion.
29886 * The target ID of the command:
29887 * * 0x0-0xFFF8 - The function ID
29888 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
29889 * * 0xFFFD - Reserved for user-space HWRM interface
29892 uint16_t target_id;
29894 * A physical address pointer pointing to a host buffer that the
29895 * command's response data will be written. This can be either a host
29896 * physical address (HPA) or a guest physical address (GPA) and must
29897 * point to a physically contiguous block of memory.
29899 uint64_t resp_addr;
29902 * Enumeration denoting the RX, TX type of the resource.
29903 * This enumeration is used for resources that are similar for both
29904 * TX and RX paths of the chip.
29906 #define HWRM_CFA_METER_INSTANCE_ALLOC_INPUT_FLAGS_PATH \
29909 #define HWRM_CFA_METER_INSTANCE_ALLOC_INPUT_FLAGS_PATH_TX \
29912 #define HWRM_CFA_METER_INSTANCE_ALLOC_INPUT_FLAGS_PATH_RX \
29914 #define HWRM_CFA_METER_INSTANCE_ALLOC_INPUT_FLAGS_PATH_LAST \
29915 HWRM_CFA_METER_INSTANCE_ALLOC_INPUT_FLAGS_PATH_RX
29917 /* This value identifies a meter profile in CFA. */
29918 uint16_t meter_profile_id;
29920 * A value of 0xffff is considered invalid and implies the
29921 * profile is not configured.
29923 #define HWRM_CFA_METER_INSTANCE_ALLOC_INPUT_METER_PROFILE_ID_INVALID \
29925 #define HWRM_CFA_METER_INSTANCE_ALLOC_INPUT_METER_PROFILE_ID_LAST \
29926 HWRM_CFA_METER_INSTANCE_ALLOC_INPUT_METER_PROFILE_ID_INVALID
29927 uint8_t unused_1[4];
29930 /* hwrm_cfa_meter_instance_alloc_output (size:128b/16B) */
29931 struct hwrm_cfa_meter_instance_alloc_output {
29932 /* The specific error status for the command. */
29933 uint16_t error_code;
29934 /* The HWRM command request type. */
29936 /* The sequence ID from the original command. */
29938 /* The length of the response data in number of bytes. */
29940 /* This value identifies a meter instance in CFA. */
29941 uint16_t meter_instance_id;
29943 * A value of 0xffff is considered invalid and implies the
29944 * instance is not configured.
29946 #define HWRM_CFA_METER_INSTANCE_ALLOC_OUTPUT_METER_INSTANCE_ID_INVALID \
29948 #define HWRM_CFA_METER_INSTANCE_ALLOC_OUTPUT_METER_INSTANCE_ID_LAST \
29949 HWRM_CFA_METER_INSTANCE_ALLOC_OUTPUT_METER_INSTANCE_ID_INVALID
29950 uint8_t unused_0[5];
29952 * This field is used in Output records to indicate that the output
29953 * is completely written to RAM. This field should be read as '1'
29954 * to indicate that the output has been completely written.
29955 * When writing a command completion or response to an internal processor,
29956 * the order of writes has to be such that this field is written last.
29961 /*******************************
29962 * hwrm_cfa_meter_instance_cfg *
29963 *******************************/
29966 /* hwrm_cfa_meter_instance_cfg_input (size:192b/24B) */
29967 struct hwrm_cfa_meter_instance_cfg_input {
29968 /* The HWRM command request type. */
29971 * The completion ring to send the completion event on. This should
29972 * be the NQ ID returned from the `nq_alloc` HWRM command.
29974 uint16_t cmpl_ring;
29976 * The sequence ID is used by the driver for tracking multiple
29977 * commands. This ID is treated as opaque data by the firmware and
29978 * the value is returned in the `hwrm_resp_hdr` upon completion.
29982 * The target ID of the command:
29983 * * 0x0-0xFFF8 - The function ID
29984 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
29985 * * 0xFFFD - Reserved for user-space HWRM interface
29988 uint16_t target_id;
29990 * A physical address pointer pointing to a host buffer that the
29991 * command's response data will be written. This can be either a host
29992 * physical address (HPA) or a guest physical address (GPA) and must
29993 * point to a physically contiguous block of memory.
29995 uint64_t resp_addr;
29998 * Enumeration denoting the RX, TX type of the resource.
29999 * This enumeration is used for resources that are similar for both
30000 * TX and RX paths of the chip.
30002 #define HWRM_CFA_METER_INSTANCE_CFG_INPUT_FLAGS_PATH UINT32_C(0x1)
30004 #define HWRM_CFA_METER_INSTANCE_CFG_INPUT_FLAGS_PATH_TX \
30007 #define HWRM_CFA_METER_INSTANCE_CFG_INPUT_FLAGS_PATH_RX \
30009 #define HWRM_CFA_METER_INSTANCE_CFG_INPUT_FLAGS_PATH_LAST \
30010 HWRM_CFA_METER_INSTANCE_CFG_INPUT_FLAGS_PATH_RX
30013 * This value identifies a new meter profile to be associated with
30014 * the meter instance specified in this command.
30016 uint16_t meter_profile_id;
30018 * A value of 0xffff is considered invalid and implies the
30019 * profile is not configured.
30021 #define HWRM_CFA_METER_INSTANCE_CFG_INPUT_METER_PROFILE_ID_INVALID \
30023 #define HWRM_CFA_METER_INSTANCE_CFG_INPUT_METER_PROFILE_ID_LAST \
30024 HWRM_CFA_METER_INSTANCE_CFG_INPUT_METER_PROFILE_ID_INVALID
30026 * This value identifies the ID of a meter instance that needs to be updated with
30027 * a new meter profile specified in this command.
30029 uint16_t meter_instance_id;
30030 uint8_t unused_1[2];
30033 /* hwrm_cfa_meter_instance_cfg_output (size:128b/16B) */
30034 struct hwrm_cfa_meter_instance_cfg_output {
30035 /* The specific error status for the command. */
30036 uint16_t error_code;
30037 /* The HWRM command request type. */
30039 /* The sequence ID from the original command. */
30041 /* The length of the response data in number of bytes. */
30043 uint8_t unused_0[7];
30045 * This field is used in Output records to indicate that the output
30046 * is completely written to RAM. This field should be read as '1'
30047 * to indicate that the output has been completely written.
30048 * When writing a command completion or response to an internal processor,
30049 * the order of writes has to be such that this field is written last.
30054 /********************************
30055 * hwrm_cfa_meter_instance_free *
30056 ********************************/
30059 /* hwrm_cfa_meter_instance_free_input (size:192b/24B) */
30060 struct hwrm_cfa_meter_instance_free_input {
30061 /* The HWRM command request type. */
30064 * The completion ring to send the completion event on. This should
30065 * be the NQ ID returned from the `nq_alloc` HWRM command.
30067 uint16_t cmpl_ring;
30069 * The sequence ID is used by the driver for tracking multiple
30070 * commands. This ID is treated as opaque data by the firmware and
30071 * the value is returned in the `hwrm_resp_hdr` upon completion.
30075 * The target ID of the command:
30076 * * 0x0-0xFFF8 - The function ID
30077 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
30078 * * 0xFFFD - Reserved for user-space HWRM interface
30081 uint16_t target_id;
30083 * A physical address pointer pointing to a host buffer that the
30084 * command's response data will be written. This can be either a host
30085 * physical address (HPA) or a guest physical address (GPA) and must
30086 * point to a physically contiguous block of memory.
30088 uint64_t resp_addr;
30091 * Enumeration denoting the RX, TX type of the resource.
30092 * This enumeration is used for resources that are similar for both
30093 * TX and RX paths of the chip.
30095 #define HWRM_CFA_METER_INSTANCE_FREE_INPUT_FLAGS_PATH UINT32_C(0x1)
30097 #define HWRM_CFA_METER_INSTANCE_FREE_INPUT_FLAGS_PATH_TX \
30100 #define HWRM_CFA_METER_INSTANCE_FREE_INPUT_FLAGS_PATH_RX \
30102 #define HWRM_CFA_METER_INSTANCE_FREE_INPUT_FLAGS_PATH_LAST \
30103 HWRM_CFA_METER_INSTANCE_FREE_INPUT_FLAGS_PATH_RX
30105 /* This value identifies a meter instance in CFA. */
30106 uint16_t meter_instance_id;
30108 * A value of 0xfff is considered invalid and implies the
30109 * instance is not configured.
30111 #define HWRM_CFA_METER_INSTANCE_FREE_INPUT_METER_INSTANCE_ID_INVALID \
30113 #define HWRM_CFA_METER_INSTANCE_FREE_INPUT_METER_INSTANCE_ID_LAST \
30114 HWRM_CFA_METER_INSTANCE_FREE_INPUT_METER_INSTANCE_ID_INVALID
30115 uint8_t unused_1[4];
30118 /* hwrm_cfa_meter_instance_free_output (size:128b/16B) */
30119 struct hwrm_cfa_meter_instance_free_output {
30120 /* The specific error status for the command. */
30121 uint16_t error_code;
30122 /* The HWRM command request type. */
30124 /* The sequence ID from the original command. */
30126 /* The length of the response data in number of bytes. */
30128 uint8_t unused_0[7];
30130 * This field is used in Output records to indicate that the output
30131 * is completely written to RAM. This field should be read as '1'
30132 * to indicate that the output has been completely written.
30133 * When writing a command completion or response to an internal processor,
30134 * the order of writes has to be such that this field is written last.
30139 /*******************************
30140 * hwrm_cfa_decap_filter_alloc *
30141 *******************************/
30144 /* hwrm_cfa_decap_filter_alloc_input (size:832b/104B) */
30145 struct hwrm_cfa_decap_filter_alloc_input {
30146 /* The HWRM command request type. */
30149 * The completion ring to send the completion event on. This should
30150 * be the NQ ID returned from the `nq_alloc` HWRM command.
30152 uint16_t cmpl_ring;
30154 * The sequence ID is used by the driver for tracking multiple
30155 * commands. This ID is treated as opaque data by the firmware and
30156 * the value is returned in the `hwrm_resp_hdr` upon completion.
30160 * The target ID of the command:
30161 * * 0x0-0xFFF8 - The function ID
30162 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
30163 * * 0xFFFD - Reserved for user-space HWRM interface
30166 uint16_t target_id;
30168 * A physical address pointer pointing to a host buffer that the
30169 * command's response data will be written. This can be either a host
30170 * physical address (HPA) or a guest physical address (GPA) and must
30171 * point to a physically contiguous block of memory.
30173 uint64_t resp_addr;
30175 /* ovs_tunnel is 1 b */
30176 #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_FLAGS_OVS_TUNNEL \
30180 * This bit must be '1' for the tunnel_type field to be
30183 #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_ENABLES_TUNNEL_TYPE \
30186 * This bit must be '1' for the tunnel_id field to be
30189 #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_ENABLES_TUNNEL_ID \
30192 * This bit must be '1' for the src_macaddr field to be
30195 #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_ENABLES_SRC_MACADDR \
30198 * This bit must be '1' for the dst_macaddr field to be
30201 #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_ENABLES_DST_MACADDR \
30204 * This bit must be '1' for the ovlan_vid field to be
30207 #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_ENABLES_OVLAN_VID \
30210 * This bit must be '1' for the ivlan_vid field to be
30213 #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_ENABLES_IVLAN_VID \
30216 * This bit must be '1' for the t_ovlan_vid field to be
30219 #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_ENABLES_T_OVLAN_VID \
30222 * This bit must be '1' for the t_ivlan_vid field to be
30225 #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_ENABLES_T_IVLAN_VID \
30228 * This bit must be '1' for the ethertype field to be
30231 #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_ENABLES_ETHERTYPE \
30234 * This bit must be '1' for the src_ipaddr field to be
30237 #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_ENABLES_SRC_IPADDR \
30240 * This bit must be '1' for the dst_ipaddr field to be
30243 #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_ENABLES_DST_IPADDR \
30246 * This bit must be '1' for the ipaddr_type field to be
30249 #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_ENABLES_IPADDR_TYPE \
30252 * This bit must be '1' for the ip_protocol field to be
30255 #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_ENABLES_IP_PROTOCOL \
30258 * This bit must be '1' for the src_port field to be
30261 #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_ENABLES_SRC_PORT \
30264 * This bit must be '1' for the dst_port field to be
30267 #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_ENABLES_DST_PORT \
30270 * This bit must be '1' for the dst_id field to be
30273 #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_ENABLES_DST_ID \
30276 * This bit must be '1' for the mirror_vnic_id field to be
30279 #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_ENABLES_MIRROR_VNIC_ID \
30282 * Tunnel identifier.
30283 * Virtual Network Identifier (VNI). Only valid with
30284 * tunnel_types VXLAN, NVGRE, and Geneve.
30285 * Only lower 24-bits of VNI field are used
30286 * in setting up the filter.
30288 uint32_t tunnel_id;
30290 uint8_t tunnel_type;
30292 #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_TUNNEL_TYPE_NONTUNNEL \
30294 /* Virtual eXtensible Local Area Network (VXLAN) */
30295 #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_TUNNEL_TYPE_VXLAN \
30297 /* Network Virtualization Generic Routing Encapsulation (NVGRE) */
30298 #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_TUNNEL_TYPE_NVGRE \
30300 /* Generic Routing Encapsulation (GRE) inside Ethernet payload */
30301 #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_TUNNEL_TYPE_L2GRE \
30304 #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_TUNNEL_TYPE_IPIP \
30306 /* Generic Network Virtualization Encapsulation (Geneve) */
30307 #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_TUNNEL_TYPE_GENEVE \
30309 /* Multi-Protocol Label Switching (MPLS) */
30310 #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_TUNNEL_TYPE_MPLS \
30312 /* Stateless Transport Tunnel (STT) */
30313 #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_TUNNEL_TYPE_STT \
30315 /* Generic Routing Encapsulation (GRE) inside IP datagram payload */
30316 #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_TUNNEL_TYPE_IPGRE \
30318 /* IPV4 over virtual eXtensible Local Area Network (IPV4oVXLAN) */
30319 #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_TUNNEL_TYPE_VXLAN_V4 \
30321 /* Enhance Generic Routing Encapsulation (GRE version 1) inside IP datagram payload */
30322 #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_TUNNEL_TYPE_IPGRE_V1 \
30324 /* Use fixed layer 2 ether type of 0xFFFF */
30325 #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_TUNNEL_TYPE_L2_ETYPE \
30327 /* IPV6 over virtual eXtensible Local Area Network with GPE header (IPV6oVXLANGPE) */
30328 #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_TUNNEL_TYPE_VXLAN_GPE_V6 \
30330 /* Any tunneled traffic */
30331 #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_TUNNEL_TYPE_ANYTUNNEL \
30333 #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_TUNNEL_TYPE_LAST \
30334 HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_TUNNEL_TYPE_ANYTUNNEL
30338 * This value indicates the source MAC address in
30339 * the Ethernet header.
30341 uint8_t src_macaddr[6];
30342 uint8_t unused_2[2];
30344 * This value indicates the destination MAC address in
30345 * the Ethernet header.
30347 uint8_t dst_macaddr[6];
30349 * This value indicates the VLAN ID of the outer VLAN tag
30350 * in the Ethernet header.
30352 uint16_t ovlan_vid;
30354 * This value indicates the VLAN ID of the inner VLAN tag
30355 * in the Ethernet header.
30357 uint16_t ivlan_vid;
30359 * This value indicates the VLAN ID of the outer VLAN tag
30360 * in the tunnel Ethernet header.
30362 uint16_t t_ovlan_vid;
30364 * This value indicates the VLAN ID of the inner VLAN tag
30365 * in the tunnel Ethernet header.
30367 uint16_t t_ivlan_vid;
30368 /* This value indicates the ethertype in the Ethernet header. */
30369 uint16_t ethertype;
30371 * This value indicates the type of IP address.
30374 * All others are invalid.
30376 uint8_t ip_addr_type;
30378 #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_IP_ADDR_TYPE_UNKNOWN \
30381 #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_IP_ADDR_TYPE_IPV4 \
30384 #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_IP_ADDR_TYPE_IPV6 \
30386 #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_IP_ADDR_TYPE_LAST \
30387 HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_IP_ADDR_TYPE_IPV6
30389 * The value of protocol filed in IP header.
30390 * Applies to UDP and TCP traffic.
30394 uint8_t ip_protocol;
30396 #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_IP_PROTOCOL_UNKNOWN \
30399 #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_IP_PROTOCOL_TCP \
30402 #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_IP_PROTOCOL_UDP \
30404 #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_IP_PROTOCOL_LAST \
30405 HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_IP_PROTOCOL_UDP
30409 * The value of source IP address to be used in filtering.
30410 * For IPv4, first four bytes represent the IP address.
30412 uint32_t src_ipaddr[4];
30414 * The value of destination IP address to be used in filtering.
30415 * For IPv4, first four bytes represent the IP address.
30417 uint32_t dst_ipaddr[4];
30419 * The value of source port to be used in filtering.
30420 * Applies to UDP and TCP traffic.
30424 * The value of destination port to be used in filtering.
30425 * Applies to UDP and TCP traffic.
30429 * If set, this value shall represent the
30430 * Logical VNIC ID of the destination VNIC for the RX
30435 * If set, this value shall represent the L2 context that matches the L2
30436 * information of the decap filter.
30438 uint16_t l2_ctxt_ref_id;
30441 /* hwrm_cfa_decap_filter_alloc_output (size:128b/16B) */
30442 struct hwrm_cfa_decap_filter_alloc_output {
30443 /* The specific error status for the command. */
30444 uint16_t error_code;
30445 /* The HWRM command request type. */
30447 /* The sequence ID from the original command. */
30449 /* The length of the response data in number of bytes. */
30451 /* This value is an opaque id into CFA data structures. */
30452 uint32_t decap_filter_id;
30453 uint8_t unused_0[3];
30455 * This field is used in Output records to indicate that the output
30456 * is completely written to RAM. This field should be read as '1'
30457 * to indicate that the output has been completely written.
30458 * When writing a command completion or response to an internal processor,
30459 * the order of writes has to be such that this field is written last.
30464 /******************************
30465 * hwrm_cfa_decap_filter_free *
30466 ******************************/
30469 /* hwrm_cfa_decap_filter_free_input (size:192b/24B) */
30470 struct hwrm_cfa_decap_filter_free_input {
30471 /* The HWRM command request type. */
30474 * The completion ring to send the completion event on. This should
30475 * be the NQ ID returned from the `nq_alloc` HWRM command.
30477 uint16_t cmpl_ring;
30479 * The sequence ID is used by the driver for tracking multiple
30480 * commands. This ID is treated as opaque data by the firmware and
30481 * the value is returned in the `hwrm_resp_hdr` upon completion.
30485 * The target ID of the command:
30486 * * 0x0-0xFFF8 - The function ID
30487 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
30488 * * 0xFFFD - Reserved for user-space HWRM interface
30491 uint16_t target_id;
30493 * A physical address pointer pointing to a host buffer that the
30494 * command's response data will be written. This can be either a host
30495 * physical address (HPA) or a guest physical address (GPA) and must
30496 * point to a physically contiguous block of memory.
30498 uint64_t resp_addr;
30499 /* This value is an opaque id into CFA data structures. */
30500 uint32_t decap_filter_id;
30501 uint8_t unused_0[4];
30504 /* hwrm_cfa_decap_filter_free_output (size:128b/16B) */
30505 struct hwrm_cfa_decap_filter_free_output {
30506 /* The specific error status for the command. */
30507 uint16_t error_code;
30508 /* The HWRM command request type. */
30510 /* The sequence ID from the original command. */
30512 /* The length of the response data in number of bytes. */
30514 uint8_t unused_0[7];
30516 * This field is used in Output records to indicate that the output
30517 * is completely written to RAM. This field should be read as '1'
30518 * to indicate that the output has been completely written.
30519 * When writing a command completion or response to an internal processor,
30520 * the order of writes has to be such that this field is written last.
30525 /***********************
30526 * hwrm_cfa_flow_alloc *
30527 ***********************/
30530 /* hwrm_cfa_flow_alloc_input (size:1024b/128B) */
30531 struct hwrm_cfa_flow_alloc_input {
30532 /* The HWRM command request type. */
30535 * The completion ring to send the completion event on. This should
30536 * be the NQ ID returned from the `nq_alloc` HWRM command.
30538 uint16_t cmpl_ring;
30540 * The sequence ID is used by the driver for tracking multiple
30541 * commands. This ID is treated as opaque data by the firmware and
30542 * the value is returned in the `hwrm_resp_hdr` upon completion.
30546 * The target ID of the command:
30547 * * 0x0-0xFFF8 - The function ID
30548 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
30549 * * 0xFFFD - Reserved for user-space HWRM interface
30552 uint16_t target_id;
30554 * A physical address pointer pointing to a host buffer that the
30555 * command's response data will be written. This can be either a host
30556 * physical address (HPA) or a guest physical address (GPA) and must
30557 * point to a physically contiguous block of memory.
30559 uint64_t resp_addr;
30561 /* tunnel is 1 b */
30562 #define HWRM_CFA_FLOW_ALLOC_INPUT_FLAGS_TUNNEL \
30564 /* num_vlan is 2 b */
30565 #define HWRM_CFA_FLOW_ALLOC_INPUT_FLAGS_NUM_VLAN_MASK \
30567 #define HWRM_CFA_FLOW_ALLOC_INPUT_FLAGS_NUM_VLAN_SFT 1
30569 #define HWRM_CFA_FLOW_ALLOC_INPUT_FLAGS_NUM_VLAN_NONE \
30570 (UINT32_C(0x0) << 1)
30572 #define HWRM_CFA_FLOW_ALLOC_INPUT_FLAGS_NUM_VLAN_ONE \
30573 (UINT32_C(0x1) << 1)
30575 #define HWRM_CFA_FLOW_ALLOC_INPUT_FLAGS_NUM_VLAN_TWO \
30576 (UINT32_C(0x2) << 1)
30577 #define HWRM_CFA_FLOW_ALLOC_INPUT_FLAGS_NUM_VLAN_LAST \
30578 HWRM_CFA_FLOW_ALLOC_INPUT_FLAGS_NUM_VLAN_TWO
30579 /* Enumeration denoting the Flow Type. */
30580 #define HWRM_CFA_FLOW_ALLOC_INPUT_FLAGS_FLOWTYPE_MASK \
30582 #define HWRM_CFA_FLOW_ALLOC_INPUT_FLAGS_FLOWTYPE_SFT 3
30584 #define HWRM_CFA_FLOW_ALLOC_INPUT_FLAGS_FLOWTYPE_L2 \
30585 (UINT32_C(0x0) << 3)
30587 #define HWRM_CFA_FLOW_ALLOC_INPUT_FLAGS_FLOWTYPE_IPV4 \
30588 (UINT32_C(0x1) << 3)
30590 #define HWRM_CFA_FLOW_ALLOC_INPUT_FLAGS_FLOWTYPE_IPV6 \
30591 (UINT32_C(0x2) << 3)
30592 #define HWRM_CFA_FLOW_ALLOC_INPUT_FLAGS_FLOWTYPE_LAST \
30593 HWRM_CFA_FLOW_ALLOC_INPUT_FLAGS_FLOWTYPE_IPV6
30595 * when set to 1, indicates TX flow offload for function specified in src_fid and
30596 * the dst_fid should be set to invalid value. To indicate a VM to VM flow, both
30597 * of the path_tx and path_rx flags need to be set. For virtio vSwitch offload
30598 * case, the src_fid and dst_fid is set to the same fid value. For the SRIOV
30599 * vSwitch offload case, the src_fid and dst_fid must be set to the same VF FID
30600 * belong to the children VFs of the same PF to indicate VM to VM flow.
30602 #define HWRM_CFA_FLOW_ALLOC_INPUT_FLAGS_PATH_TX \
30605 * when set to 1, indicates RX flow offload for function specified in dst_fid and
30606 * the src_fid should be set to invalid value.
30608 #define HWRM_CFA_FLOW_ALLOC_INPUT_FLAGS_PATH_RX \
30611 * Set to 1 to indicate matching of VXLAN VNI from the custom vxlan header is
30612 * required and the VXLAN VNI value is stored in the first 24 bits of the dmac field.
30613 * This flag is only valid when the flow direction is RX.
30615 #define HWRM_CFA_FLOW_ALLOC_INPUT_FLAGS_MATCH_VXLAN_IP_VNI \
30617 /* Set to 1 to indicate vhost_id is specified in the outer_vlan_tci field. */
30618 #define HWRM_CFA_FLOW_ALLOC_INPUT_FLAGS_VHOST_ID_USE_VLAN \
30625 /* Tunnel handle valid when tunnel flag is set. */
30626 uint32_t tunnel_handle;
30627 uint16_t action_flags;
30629 * Setting of this flag indicates drop action. If this flag is not set,
30630 * then it should be considered accept action.
30632 #define HWRM_CFA_FLOW_ALLOC_INPUT_ACTION_FLAGS_FWD \
30634 /* recycle is 1 b */
30635 #define HWRM_CFA_FLOW_ALLOC_INPUT_ACTION_FLAGS_RECYCLE \
30638 * Setting of this flag indicates drop action. If this flag is not set,
30639 * then it should be considered accept action.
30641 #define HWRM_CFA_FLOW_ALLOC_INPUT_ACTION_FLAGS_DROP \
30644 #define HWRM_CFA_FLOW_ALLOC_INPUT_ACTION_FLAGS_METER \
30646 /* tunnel is 1 b */
30647 #define HWRM_CFA_FLOW_ALLOC_INPUT_ACTION_FLAGS_TUNNEL \
30649 /* nat_src is 1 b */
30650 #define HWRM_CFA_FLOW_ALLOC_INPUT_ACTION_FLAGS_NAT_SRC \
30652 /* nat_dest is 1 b */
30653 #define HWRM_CFA_FLOW_ALLOC_INPUT_ACTION_FLAGS_NAT_DEST \
30655 /* nat_ipv4_address is 1 b */
30656 #define HWRM_CFA_FLOW_ALLOC_INPUT_ACTION_FLAGS_NAT_IPV4_ADDRESS \
30658 /* l2_header_rewrite is 1 b */
30659 #define HWRM_CFA_FLOW_ALLOC_INPUT_ACTION_FLAGS_L2_HEADER_REWRITE \
30661 /* ttl_decrement is 1 b */
30662 #define HWRM_CFA_FLOW_ALLOC_INPUT_ACTION_FLAGS_TTL_DECREMENT \
30665 * If set to 1 and flow direction is TX, it indicates decap of L2 header
30666 * and encap of tunnel header. If set to 1 and flow direction is RX, it
30667 * indicates decap of tunnel header and encap L2 header. The type of tunnel
30668 * is specified in the tunnel_type field.
30670 #define HWRM_CFA_FLOW_ALLOC_INPUT_ACTION_FLAGS_TUNNEL_IP \
30672 /* If set to 1, flow aging is enabled for this flow. */
30673 #define HWRM_CFA_FLOW_ALLOC_INPUT_ACTION_FLAGS_FLOW_AGING_ENABLED \
30676 * If set to 1 an attempt will be made to try to offload this flow to the
30677 * most optimal flow table resource. If set to 0, the flow will be
30678 * placed to the default flow table resource.
30680 #define HWRM_CFA_FLOW_ALLOC_INPUT_ACTION_FLAGS_PRI_HINT \
30683 * If set to 1 there will be no attempt to allocate an on-chip try to
30684 * offload this flow. If set to 0, which will keep compatibility with the
30685 * older drivers, will cause the FW to attempt to allocate an on-chip flow
30686 * counter for the newly created flow. This will keep the existing behavior
30687 * with EM flows which always had an associated flow counter.
30689 #define HWRM_CFA_FLOW_ALLOC_INPUT_ACTION_FLAGS_NO_FLOW_COUNTER_ALLOC \
30692 * Tx Flow: pf or vf fid.
30696 /* VLAN tpid, valid when push_vlan flag is set. */
30697 uint16_t l2_rewrite_vlan_tpid;
30698 /* VLAN tci, valid when push_vlan flag is set. */
30699 uint16_t l2_rewrite_vlan_tci;
30700 /* Meter id, valid when meter flag is set. */
30701 uint16_t act_meter_id;
30702 /* Flow with the same l2 context tcam key. */
30703 uint16_t ref_flow_handle;
30704 /* This value sets the match value for the ethertype. */
30705 uint16_t ethertype;
30706 /* valid when num tags is 1 or 2. */
30707 uint16_t outer_vlan_tci;
30708 /* This value sets the match value for the Destination MAC address. */
30710 /* valid when num tags is 2. */
30711 uint16_t inner_vlan_tci;
30712 /* This value sets the match value for the Source MAC address. */
30714 /* The bit length of destination IP address mask. */
30715 uint8_t ip_dst_mask_len;
30716 /* The bit length of source IP address mask. */
30717 uint8_t ip_src_mask_len;
30718 /* The value of destination IPv4/IPv6 address. */
30719 uint32_t ip_dst[4];
30720 /* The source IPv4/IPv6 address. */
30721 uint32_t ip_src[4];
30723 * The value of source port.
30724 * Applies to UDP and TCP traffic.
30726 uint16_t l4_src_port;
30728 * The value of source port mask.
30729 * Applies to UDP and TCP traffic.
30731 uint16_t l4_src_port_mask;
30733 * The value of destination port.
30734 * Applies to UDP and TCP traffic.
30736 uint16_t l4_dst_port;
30738 * The value of destination port mask.
30739 * Applies to UDP and TCP traffic.
30741 uint16_t l4_dst_port_mask;
30743 * NAT IPv4/6 address based on address type flag.
30744 * 0 values are ignored.
30746 uint32_t nat_ip_address[4];
30747 /* L2 header re-write Destination MAC address. */
30748 uint16_t l2_rewrite_dmac[3];
30750 * The NAT source/destination port based on direction flag.
30751 * Applies to UDP and TCP traffic.
30752 * 0 values are ignored.
30755 /* L2 header re-write Source MAC address. */
30756 uint16_t l2_rewrite_smac[3];
30757 /* The value of ip protocol. */
30760 uint8_t tunnel_type;
30762 #define HWRM_CFA_FLOW_ALLOC_INPUT_TUNNEL_TYPE_NONTUNNEL \
30764 /* Virtual eXtensible Local Area Network (VXLAN) */
30765 #define HWRM_CFA_FLOW_ALLOC_INPUT_TUNNEL_TYPE_VXLAN \
30767 /* Network Virtualization Generic Routing Encapsulation (NVGRE) */
30768 #define HWRM_CFA_FLOW_ALLOC_INPUT_TUNNEL_TYPE_NVGRE \
30770 /* Generic Routing Encapsulation (GRE) inside Ethernet payload */
30771 #define HWRM_CFA_FLOW_ALLOC_INPUT_TUNNEL_TYPE_L2GRE \
30774 #define HWRM_CFA_FLOW_ALLOC_INPUT_TUNNEL_TYPE_IPIP \
30776 /* Generic Network Virtualization Encapsulation (Geneve) */
30777 #define HWRM_CFA_FLOW_ALLOC_INPUT_TUNNEL_TYPE_GENEVE \
30779 /* Multi-Protocol Label Switching (MPLS) */
30780 #define HWRM_CFA_FLOW_ALLOC_INPUT_TUNNEL_TYPE_MPLS \
30782 /* Stateless Transport Tunnel (STT) */
30783 #define HWRM_CFA_FLOW_ALLOC_INPUT_TUNNEL_TYPE_STT \
30785 /* Generic Routing Encapsulation (GRE) inside IP datagram payload */
30786 #define HWRM_CFA_FLOW_ALLOC_INPUT_TUNNEL_TYPE_IPGRE \
30788 /* IPV4 over virtual eXtensible Local Area Network (IPV4oVXLAN) */
30789 #define HWRM_CFA_FLOW_ALLOC_INPUT_TUNNEL_TYPE_VXLAN_V4 \
30791 /* Enhance Generic Routing Encapsulation (GRE version 1) inside IP datagram payload */
30792 #define HWRM_CFA_FLOW_ALLOC_INPUT_TUNNEL_TYPE_IPGRE_V1 \
30794 /* Use fixed layer 2 ether type of 0xFFFF */
30795 #define HWRM_CFA_FLOW_ALLOC_INPUT_TUNNEL_TYPE_L2_ETYPE \
30797 /* IPV6 over virtual eXtensible Local Area Network with GPE header (IPV6oVXLANGPE) */
30798 #define HWRM_CFA_FLOW_ALLOC_INPUT_TUNNEL_TYPE_VXLAN_GPE_V6 \
30800 /* Any tunneled traffic */
30801 #define HWRM_CFA_FLOW_ALLOC_INPUT_TUNNEL_TYPE_ANYTUNNEL \
30803 #define HWRM_CFA_FLOW_ALLOC_INPUT_TUNNEL_TYPE_LAST \
30804 HWRM_CFA_FLOW_ALLOC_INPUT_TUNNEL_TYPE_ANYTUNNEL
30807 /* hwrm_cfa_flow_alloc_output (size:256b/32B) */
30808 struct hwrm_cfa_flow_alloc_output {
30809 /* The specific error status for the command. */
30810 uint16_t error_code;
30811 /* The HWRM command request type. */
30813 /* The sequence ID from the original command. */
30815 /* The length of the response data in number of bytes. */
30817 /* Flow record index. */
30818 uint16_t flow_handle;
30819 uint8_t unused_0[2];
30821 * The flow id value in bit 0-29 is the actual ID of the flow
30822 * associated with this filter and it shall be used to match
30823 * and associate the flow identifier returned in completion
30824 * records. A value of 0xFFFFFFFF in the 32-bit flow_id field
30825 * shall indicate no valid flow id.
30828 /* Indicate the flow id value. */
30829 #define HWRM_CFA_FLOW_ALLOC_OUTPUT_FLOW_ID_VALUE_MASK \
30830 UINT32_C(0x3fffffff)
30831 #define HWRM_CFA_FLOW_ALLOC_OUTPUT_FLOW_ID_VALUE_SFT 0
30832 /* Indicate type of the flow. */
30833 #define HWRM_CFA_FLOW_ALLOC_OUTPUT_FLOW_ID_TYPE \
30834 UINT32_C(0x40000000)
30836 * If this bit set to 0, then it indicates that the flow is
30839 #define HWRM_CFA_FLOW_ALLOC_OUTPUT_FLOW_ID_TYPE_INT \
30840 (UINT32_C(0x0) << 30)
30842 * If this bit is set to 1, then it indicates that the flow is
30845 #define HWRM_CFA_FLOW_ALLOC_OUTPUT_FLOW_ID_TYPE_EXT \
30846 (UINT32_C(0x1) << 30)
30847 #define HWRM_CFA_FLOW_ALLOC_OUTPUT_FLOW_ID_TYPE_LAST \
30848 HWRM_CFA_FLOW_ALLOC_OUTPUT_FLOW_ID_TYPE_EXT
30849 /* Indicate the flow direction. */
30850 #define HWRM_CFA_FLOW_ALLOC_OUTPUT_FLOW_ID_DIR \
30851 UINT32_C(0x80000000)
30852 /* If this bit set to 0, then it indicates rx flow. */
30853 #define HWRM_CFA_FLOW_ALLOC_OUTPUT_FLOW_ID_DIR_RX \
30854 (UINT32_C(0x0) << 31)
30855 /* If this bit is set to 1, then it indicates that tx flow. */
30856 #define HWRM_CFA_FLOW_ALLOC_OUTPUT_FLOW_ID_DIR_TX \
30857 (UINT32_C(0x1) << 31)
30858 #define HWRM_CFA_FLOW_ALLOC_OUTPUT_FLOW_ID_DIR_LAST \
30859 HWRM_CFA_FLOW_ALLOC_OUTPUT_FLOW_ID_DIR_TX
30860 /* This value identifies a set of CFA data structures used for a flow. */
30861 uint64_t ext_flow_handle;
30862 uint32_t flow_counter_id;
30863 uint8_t unused_1[3];
30865 * This field is used in Output records to indicate that the output
30866 * is completely written to RAM. This field should be read as '1'
30867 * to indicate that the output has been completely written.
30868 * When writing a command completion or response to an internal processor,
30869 * the order of writes has to be such that this field is written last.
30874 /* hwrm_cfa_flow_alloc_cmd_err (size:64b/8B) */
30875 struct hwrm_cfa_flow_alloc_cmd_err {
30877 * command specific error codes that goes to
30878 * the cmd_err field in Common HWRM Error Response.
30881 /* Unknown error */
30882 #define HWRM_CFA_FLOW_ALLOC_CMD_ERR_CODE_UNKNOWN UINT32_C(0x0)
30883 /* No more L2 Context TCAM */
30884 #define HWRM_CFA_FLOW_ALLOC_CMD_ERR_CODE_L2_CONTEXT_TCAM UINT32_C(0x1)
30885 /* No more action records */
30886 #define HWRM_CFA_FLOW_ALLOC_CMD_ERR_CODE_ACTION_RECORD UINT32_C(0x2)
30887 /* No more flow counters */
30888 #define HWRM_CFA_FLOW_ALLOC_CMD_ERR_CODE_FLOW_COUNTER UINT32_C(0x3)
30889 /* No more wild-card TCAM */
30890 #define HWRM_CFA_FLOW_ALLOC_CMD_ERR_CODE_WILD_CARD_TCAM UINT32_C(0x4)
30891 /* Hash collsion in exact match tables */
30892 #define HWRM_CFA_FLOW_ALLOC_CMD_ERR_CODE_HASH_COLLISION UINT32_C(0x5)
30893 /* Key is already installed */
30894 #define HWRM_CFA_FLOW_ALLOC_CMD_ERR_CODE_KEY_EXISTS UINT32_C(0x6)
30895 /* Flow Context DB is out of resource */
30896 #define HWRM_CFA_FLOW_ALLOC_CMD_ERR_CODE_FLOW_CTXT_DB UINT32_C(0x7)
30897 #define HWRM_CFA_FLOW_ALLOC_CMD_ERR_CODE_LAST \
30898 HWRM_CFA_FLOW_ALLOC_CMD_ERR_CODE_FLOW_CTXT_DB
30899 uint8_t unused_0[7];
30902 /**********************
30903 * hwrm_cfa_flow_free *
30904 **********************/
30907 /* hwrm_cfa_flow_free_input (size:256b/32B) */
30908 struct hwrm_cfa_flow_free_input {
30909 /* The HWRM command request type. */
30912 * The completion ring to send the completion event on. This should
30913 * be the NQ ID returned from the `nq_alloc` HWRM command.
30915 uint16_t cmpl_ring;
30917 * The sequence ID is used by the driver for tracking multiple
30918 * commands. This ID is treated as opaque data by the firmware and
30919 * the value is returned in the `hwrm_resp_hdr` upon completion.
30923 * The target ID of the command:
30924 * * 0x0-0xFFF8 - The function ID
30925 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
30926 * * 0xFFFD - Reserved for user-space HWRM interface
30929 uint16_t target_id;
30931 * A physical address pointer pointing to a host buffer that the
30932 * command's response data will be written. This can be either a host
30933 * physical address (HPA) or a guest physical address (GPA) and must
30934 * point to a physically contiguous block of memory.
30936 uint64_t resp_addr;
30937 /* Flow record index. */
30938 uint16_t flow_handle;
30940 /* Flow counter id to be freed. */
30941 uint32_t flow_counter_id;
30942 /* This value identifies a set of CFA data structures used for a flow. */
30943 uint64_t ext_flow_handle;
30946 /* hwrm_cfa_flow_free_output (size:256b/32B) */
30947 struct hwrm_cfa_flow_free_output {
30948 /* The specific error status for the command. */
30949 uint16_t error_code;
30950 /* The HWRM command request type. */
30952 /* The sequence ID from the original command. */
30954 /* The length of the response data in number of bytes. */
30956 /* packet is 64 b */
30960 uint8_t unused_0[7];
30962 * This field is used in Output records to indicate that the output
30963 * is completely written to RAM. This field should be read as '1'
30964 * to indicate that the output has been completely written.
30965 * When writing a command completion or response to an internal processor,
30966 * the order of writes has to be such that this field is written last.
30971 /* hwrm_cfa_flow_action_data (size:960b/120B) */
30972 struct hwrm_cfa_flow_action_data {
30973 uint16_t action_flags;
30974 /* Setting of this flag indicates accept action. */
30975 #define HWRM_CFA_FLOW_ACTION_DATA_ACTION_FLAGS_FWD \
30977 /* Setting of this flag indicates recycle action. */
30978 #define HWRM_CFA_FLOW_ACTION_DATA_ACTION_FLAGS_RECYCLE \
30980 /* Setting of this flag indicates drop action. */
30981 #define HWRM_CFA_FLOW_ACTION_DATA_ACTION_FLAGS_DROP \
30983 /* Setting of this flag indicates meter action. */
30984 #define HWRM_CFA_FLOW_ACTION_DATA_ACTION_FLAGS_METER \
30986 /* Setting of this flag indicates tunnel action. */
30987 #define HWRM_CFA_FLOW_ACTION_DATA_ACTION_FLAGS_TUNNEL \
30990 * If set to 1 and flow direction is TX, it indicates decap of L2 header
30991 * and encap of tunnel header. If set to 1 and flow direction is RX, it
30992 * indicates decap of tunnel header and encap L2 header.
30994 #define HWRM_CFA_FLOW_ACTION_DATA_ACTION_FLAGS_TUNNEL_IP \
30996 /* Setting of this flag indicates ttl decrement action. */
30997 #define HWRM_CFA_FLOW_ACTION_DATA_ACTION_FLAGS_TTL_DECREMENT \
30999 /* If set to 1, flow aging is enabled for this flow. */
31000 #define HWRM_CFA_FLOW_ACTION_DATA_ACTION_FLAGS_FLOW_AGING_ENABLED \
31002 /* Setting of this flag indicates encap action. */
31003 #define HWRM_CFA_FLOW_ACTION_DATA_ACTION_FLAGS_ENCAP \
31005 /* Setting of this flag indicates decap action. */
31006 #define HWRM_CFA_FLOW_ACTION_DATA_ACTION_FLAGS_DECAP \
31009 uint16_t act_meter_id;
31012 /* vport number. */
31014 /* The NAT source/destination. */
31016 uint16_t unused_0[3];
31017 /* NAT IPv4/IPv6 address. */
31018 uint32_t nat_ip_address[4];
31019 /* Encapsulation Type. */
31020 uint8_t encap_type;
31021 /* Virtual eXtensible Local Area Network (VXLAN) */
31022 #define HWRM_CFA_FLOW_ACTION_DATA_ENCAP_TYPE_VXLAN UINT32_C(0x1)
31023 /* Network Virtualization Generic Routing Encapsulation (NVGRE) */
31024 #define HWRM_CFA_FLOW_ACTION_DATA_ENCAP_TYPE_NVGRE UINT32_C(0x2)
31025 /* Generic Routing Encapsulation (GRE) after inside Ethernet payload */
31026 #define HWRM_CFA_FLOW_ACTION_DATA_ENCAP_TYPE_L2GRE UINT32_C(0x3)
31028 #define HWRM_CFA_FLOW_ACTION_DATA_ENCAP_TYPE_IPIP UINT32_C(0x4)
31029 /* Generic Network Virtualization Encapsulation (Geneve) */
31030 #define HWRM_CFA_FLOW_ACTION_DATA_ENCAP_TYPE_GENEVE UINT32_C(0x5)
31031 /* Multi-Protocol Label Switching (MPLS) */
31032 #define HWRM_CFA_FLOW_ACTION_DATA_ENCAP_TYPE_MPLS UINT32_C(0x6)
31034 #define HWRM_CFA_FLOW_ACTION_DATA_ENCAP_TYPE_VLAN UINT32_C(0x7)
31035 /* Generic Routing Encapsulation (GRE) inside IP datagram payload */
31036 #define HWRM_CFA_FLOW_ACTION_DATA_ENCAP_TYPE_IPGRE UINT32_C(0x8)
31037 /* IPV4 over virtual eXtensible Local Area Network (IPV4oVXLAN) */
31038 #define HWRM_CFA_FLOW_ACTION_DATA_ENCAP_TYPE_VXLAN_V4 UINT32_C(0x9)
31039 /* Enhance Generic Routing Encapsulation (GRE version 1) inside IP datagram payload */
31040 #define HWRM_CFA_FLOW_ACTION_DATA_ENCAP_TYPE_IPGRE_V1 UINT32_C(0xa)
31041 /* Use fixed layer 2 ether type of 0xFFFF */
31042 #define HWRM_CFA_FLOW_ACTION_DATA_ENCAP_TYPE_L2_ETYPE UINT32_C(0xb)
31043 /* IPV6 over virtual eXtensible Local Area Network with GPE header (IPV6oVXLANGPE) */
31044 #define HWRM_CFA_FLOW_ACTION_DATA_ENCAP_TYPE_VXLAN_GPE_V6 UINT32_C(0xc)
31045 #define HWRM_CFA_FLOW_ACTION_DATA_ENCAP_TYPE_LAST \
31046 HWRM_CFA_FLOW_ACTION_DATA_ENCAP_TYPE_VXLAN_GPE_V6
31048 /* This value is encap data for the associated encap type. */
31049 uint32_t encap_data[20];
31052 /* hwrm_cfa_flow_tunnel_hdr_data (size:64b/8B) */
31053 struct hwrm_cfa_flow_tunnel_hdr_data {
31055 uint8_t tunnel_type;
31057 #define HWRM_CFA_FLOW_TUNNEL_HDR_DATA_TUNNEL_TYPE_NONTUNNEL \
31059 /* Virtual eXtensible Local Area Network (VXLAN) */
31060 #define HWRM_CFA_FLOW_TUNNEL_HDR_DATA_TUNNEL_TYPE_VXLAN \
31062 /* Network Virtualization Generic Routing Encapsulation (NVGRE) */
31063 #define HWRM_CFA_FLOW_TUNNEL_HDR_DATA_TUNNEL_TYPE_NVGRE \
31065 /* Generic Routing Encapsulation (GRE) inside Ethernet payload */
31066 #define HWRM_CFA_FLOW_TUNNEL_HDR_DATA_TUNNEL_TYPE_L2GRE \
31069 #define HWRM_CFA_FLOW_TUNNEL_HDR_DATA_TUNNEL_TYPE_IPIP \
31071 /* Generic Network Virtualization Encapsulation (Geneve) */
31072 #define HWRM_CFA_FLOW_TUNNEL_HDR_DATA_TUNNEL_TYPE_GENEVE \
31074 /* Multi-Protocol Label Switching (MPLS) */
31075 #define HWRM_CFA_FLOW_TUNNEL_HDR_DATA_TUNNEL_TYPE_MPLS \
31077 /* Stateless Transport Tunnel (STT) */
31078 #define HWRM_CFA_FLOW_TUNNEL_HDR_DATA_TUNNEL_TYPE_STT \
31080 /* Generic Routing Encapsulation (GRE) inside IP datagram payload */
31081 #define HWRM_CFA_FLOW_TUNNEL_HDR_DATA_TUNNEL_TYPE_IPGRE \
31083 /* IPV4 over virtual eXtensible Local Area Network (IPV4oVXLAN) */
31084 #define HWRM_CFA_FLOW_TUNNEL_HDR_DATA_TUNNEL_TYPE_VXLAN_V4 \
31086 /* Enhance Generic Routing Encapsulation (GRE version 1) inside IP datagram payload */
31087 #define HWRM_CFA_FLOW_TUNNEL_HDR_DATA_TUNNEL_TYPE_IPGRE_V1 \
31089 /* Use fixed layer 2 ether type of 0xFFFF */
31090 #define HWRM_CFA_FLOW_TUNNEL_HDR_DATA_TUNNEL_TYPE_L2_ETYPE \
31092 /* IPV6 over virtual eXtensible Local Area Network with GPE header (IPV6oVXLANGPE) */
31093 #define HWRM_CFA_FLOW_TUNNEL_HDR_DATA_TUNNEL_TYPE_VXLAN_GPE_V6 \
31095 /* Any tunneled traffic */
31096 #define HWRM_CFA_FLOW_TUNNEL_HDR_DATA_TUNNEL_TYPE_ANYTUNNEL \
31098 #define HWRM_CFA_FLOW_TUNNEL_HDR_DATA_TUNNEL_TYPE_LAST \
31099 HWRM_CFA_FLOW_TUNNEL_HDR_DATA_TUNNEL_TYPE_ANYTUNNEL
31102 * Tunnel identifier.
31103 * Virtual Network Identifier (VNI).
31105 uint32_t tunnel_id;
31108 /* hwrm_cfa_flow_l4_key_data (size:64b/8B) */
31109 struct hwrm_cfa_flow_l4_key_data {
31110 /* The value of source port. */
31111 uint16_t l4_src_port;
31112 /* The value of destination port. */
31113 uint16_t l4_dst_port;
31117 /* hwrm_cfa_flow_l3_key_data (size:512b/64B) */
31118 struct hwrm_cfa_flow_l3_key_data {
31119 /* The value of ip protocol. */
31120 uint8_t ip_protocol;
31121 uint8_t unused_0[7];
31122 /* The value of destination IPv4/IPv6 address. */
31123 uint32_t ip_dst[4];
31124 /* The source IPv4/IPv6 address. */
31125 uint32_t ip_src[4];
31126 /* NAT IPv4/IPv6 address. */
31127 uint32_t nat_ip_address[4];
31128 uint32_t unused[2];
31131 /* hwrm_cfa_flow_l2_key_data (size:448b/56B) */
31132 struct hwrm_cfa_flow_l2_key_data {
31133 /* Destination MAC address. */
31136 /* Source MAC address. */
31139 /* L2 header re-write Destination MAC address. */
31140 uint16_t l2_rewrite_dmac[3];
31142 /* L2 header re-write Source MAC address. */
31143 uint16_t l2_rewrite_smac[3];
31145 uint16_t ethertype;
31146 /* Number of VLAN tags. */
31147 uint16_t num_vlan_tags;
31149 uint16_t l2_rewrite_vlan_tpid;
31151 uint16_t l2_rewrite_vlan_tci;
31152 uint8_t unused_3[2];
31153 /* Outer VLAN TPID. */
31154 uint16_t ovlan_tpid;
31155 /* Outer VLAN TCI. */
31156 uint16_t ovlan_tci;
31157 /* Inner VLAN TPID. */
31158 uint16_t ivlan_tpid;
31159 /* Inner VLAN TCI. */
31160 uint16_t ivlan_tci;
31164 /* hwrm_cfa_flow_key_data (size:4160b/520B) */
31165 struct hwrm_cfa_flow_key_data {
31166 /* Flow associated tunnel L2 header key info. */
31167 uint32_t t_l2_key_data[14];
31168 /* Flow associated tunnel L2 header mask info. */
31169 uint32_t t_l2_key_mask[14];
31170 /* Flow associated tunnel L3 header key info. */
31171 uint32_t t_l3_key_data[16];
31172 /* Flow associated tunnel L3 header mask info. */
31173 uint32_t t_l3_key_mask[16];
31174 /* Flow associated tunnel L4 header key info. */
31175 uint32_t t_l4_key_data[2];
31176 /* Flow associated tunnel L4 header mask info. */
31177 uint32_t t_l4_key_mask[2];
31178 /* Flow associated tunnel header info. */
31179 uint32_t tunnel_hdr[2];
31180 /* Flow associated L2 header key info. */
31181 uint32_t l2_key_data[14];
31182 /* Flow associated L2 header mask info. */
31183 uint32_t l2_key_mask[14];
31184 /* Flow associated L3 header key info. */
31185 uint32_t l3_key_data[16];
31186 /* Flow associated L3 header mask info. */
31187 uint32_t l3_key_mask[16];
31188 /* Flow associated L4 header key info. */
31189 uint32_t l4_key_data[2];
31190 /* Flow associated L4 header mask info. */
31191 uint32_t l4_key_mask[2];
31194 /**********************
31195 * hwrm_cfa_flow_info *
31196 **********************/
31199 /* hwrm_cfa_flow_info_input (size:256b/32B) */
31200 struct hwrm_cfa_flow_info_input {
31201 /* The HWRM command request type. */
31204 * The completion ring to send the completion event on. This should
31205 * be the NQ ID returned from the `nq_alloc` HWRM command.
31207 uint16_t cmpl_ring;
31209 * The sequence ID is used by the driver for tracking multiple
31210 * commands. This ID is treated as opaque data by the firmware and
31211 * the value is returned in the `hwrm_resp_hdr` upon completion.
31215 * The target ID of the command:
31216 * * 0x0-0xFFF8 - The function ID
31217 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
31218 * * 0xFFFD - Reserved for user-space HWRM interface
31221 uint16_t target_id;
31223 * A physical address pointer pointing to a host buffer that the
31224 * command's response data will be written. This can be either a host
31225 * physical address (HPA) or a guest physical address (GPA) and must
31226 * point to a physically contiguous block of memory.
31228 uint64_t resp_addr;
31229 /* Flow record index. */
31230 uint16_t flow_handle;
31231 /* Max flow handle */
31232 #define HWRM_CFA_FLOW_INFO_INPUT_FLOW_HANDLE_MAX_MASK \
31234 #define HWRM_CFA_FLOW_INFO_INPUT_FLOW_HANDLE_MAX_SFT 0
31235 /* CNP flow handle */
31236 #define HWRM_CFA_FLOW_INFO_INPUT_FLOW_HANDLE_CNP_CNT \
31238 /* RoCEv1 flow handle */
31239 #define HWRM_CFA_FLOW_INFO_INPUT_FLOW_HANDLE_ROCEV1_CNT \
31241 /* RoCEv2 flow handle */
31242 #define HWRM_CFA_FLOW_INFO_INPUT_FLOW_HANDLE_ROCEV2_CNT \
31244 /* Direction rx = 1 */
31245 #define HWRM_CFA_FLOW_INFO_INPUT_FLOW_HANDLE_DIR_RX \
31247 uint8_t unused_0[6];
31248 /* This value identifies a set of CFA data structures used for a flow. */
31249 uint64_t ext_flow_handle;
31252 /* hwrm_cfa_flow_info_output (size:5632b/704B) */
31253 struct hwrm_cfa_flow_info_output {
31254 /* The specific error status for the command. */
31255 uint16_t error_code;
31256 /* The HWRM command request type. */
31258 /* The sequence ID from the original command. */
31260 /* The length of the response data in number of bytes. */
31263 /* When set to 1, indicates the configuration is the TX flow. */
31264 #define HWRM_CFA_FLOW_INFO_OUTPUT_FLAGS_PATH_TX UINT32_C(0x1)
31265 /* When set to 1, indicates the configuration is the RX flow. */
31266 #define HWRM_CFA_FLOW_INFO_OUTPUT_FLAGS_PATH_RX UINT32_C(0x2)
31267 /* profile is 8 b */
31269 /* src_fid is 16 b */
31271 /* dst_fid is 16 b */
31273 /* l2_ctxt_id is 16 b */
31274 uint16_t l2_ctxt_id;
31275 /* em_info is 64 b */
31277 /* tcam_info is 64 b */
31278 uint64_t tcam_info;
31279 /* vfp_tcam_info is 64 b */
31280 uint64_t vfp_tcam_info;
31281 /* ar_id is 16 b */
31283 /* flow_handle is 16 b */
31284 uint16_t flow_handle;
31285 /* tunnel_handle is 32 b */
31286 uint32_t tunnel_handle;
31287 /* The flow aging timer for the flow, the unit is 100 milliseconds */
31288 uint16_t flow_timer;
31289 uint8_t unused_0[6];
31290 /* Flow associated L2, L3 and L4 headers info. */
31291 uint32_t flow_key_data[130];
31292 /* Flow associated action record info. */
31293 uint32_t flow_action_info[30];
31294 uint8_t unused_1[7];
31296 * This field is used in Output records to indicate that the output
31297 * is completely written to RAM. This field should be read as '1'
31298 * to indicate that the output has been completely written.
31299 * When writing a command completion or response to an internal processor,
31300 * the order of writes has to be such that this field is written last.
31305 /***********************
31306 * hwrm_cfa_flow_flush *
31307 ***********************/
31310 /* hwrm_cfa_flow_flush_input (size:256b/32B) */
31311 struct hwrm_cfa_flow_flush_input {
31312 /* The HWRM command request type. */
31315 * The completion ring to send the completion event on. This should
31316 * be the NQ ID returned from the `nq_alloc` HWRM command.
31318 uint16_t cmpl_ring;
31320 * The sequence ID is used by the driver for tracking multiple
31321 * commands. This ID is treated as opaque data by the firmware and
31322 * the value is returned in the `hwrm_resp_hdr` upon completion.
31326 * The target ID of the command:
31327 * * 0x0-0xFFF8 - The function ID
31328 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
31329 * * 0xFFFD - Reserved for user-space HWRM interface
31332 uint16_t target_id;
31334 * A physical address pointer pointing to a host buffer that the
31335 * command's response data will be written. This can be either a host
31336 * physical address (HPA) or a guest physical address (GPA) and must
31337 * point to a physically contiguous block of memory.
31339 uint64_t resp_addr;
31340 /* flags is 32 b */
31343 * Set to 1 to indicate the page size, page layers, and flow_handle_table_dma_addr
31344 * fields are valid. The flow flush operation should only flush the flows from the
31345 * flow table specified. This flag is set to 0 by older driver. For older firmware,
31346 * setting this flag has no effect.
31348 #define HWRM_CFA_FLOW_FLUSH_INPUT_FLAGS_FLOW_TABLE_VALID \
31351 * Set to 1 to indicate flow flush operation to cleanup all the flows, meters, CFA
31352 * context memory tables etc. This flag is set to 0 by older driver. For older firmware,
31353 * setting this flag has no effect.
31355 #define HWRM_CFA_FLOW_FLUSH_INPUT_FLAGS_FLOW_RESET_ALL \
31358 * Set to 1 to indicate flow flush operation to cleanup all the flows by the caller.
31359 * This flag is set to 0 by older driver. For older firmware, setting this flag has no effect.
31361 #define HWRM_CFA_FLOW_FLUSH_INPUT_FLAGS_FLOW_RESET_PORT \
31363 /* Set to 1 to indicate the flow counter IDs are included in the flow table. */
31364 #define HWRM_CFA_FLOW_FLUSH_INPUT_FLAGS_FLOW_HANDLE_INCL_FC \
31365 UINT32_C(0x8000000)
31367 * This specifies the size of flow handle entries provided by the driver
31368 * in the flow table specified below. Only two flow handle size enums are defined.
31370 #define HWRM_CFA_FLOW_FLUSH_INPUT_FLAGS_FLOW_HANDLE_ENTRY_SIZE_MASK \
31371 UINT32_C(0xc0000000)
31372 #define HWRM_CFA_FLOW_FLUSH_INPUT_FLAGS_FLOW_HANDLE_ENTRY_SIZE_SFT \
31374 /* The flow handle is 16bit */
31375 #define HWRM_CFA_FLOW_FLUSH_INPUT_FLAGS_FLOW_HANDLE_ENTRY_SIZE_FLOW_HND_16BIT \
31376 (UINT32_C(0x0) << 30)
31377 /* The flow handle is 64bit */
31378 #define HWRM_CFA_FLOW_FLUSH_INPUT_FLAGS_FLOW_HANDLE_ENTRY_SIZE_FLOW_HND_64BIT \
31379 (UINT32_C(0x1) << 30)
31380 #define HWRM_CFA_FLOW_FLUSH_INPUT_FLAGS_FLOW_HANDLE_ENTRY_SIZE_LAST \
31381 HWRM_CFA_FLOW_FLUSH_INPUT_FLAGS_FLOW_HANDLE_ENTRY_SIZE_FLOW_HND_64BIT
31382 /* Specify page size of the flow table memory. */
31384 /* The page size is 4K */
31385 #define HWRM_CFA_FLOW_FLUSH_INPUT_PAGE_SIZE_4K UINT32_C(0x0)
31386 /* The page size is 8K */
31387 #define HWRM_CFA_FLOW_FLUSH_INPUT_PAGE_SIZE_8K UINT32_C(0x1)
31388 /* The page size is 64K */
31389 #define HWRM_CFA_FLOW_FLUSH_INPUT_PAGE_SIZE_64K UINT32_C(0x4)
31390 /* The page size is 256K */
31391 #define HWRM_CFA_FLOW_FLUSH_INPUT_PAGE_SIZE_256K UINT32_C(0x6)
31392 /* The page size is 1M */
31393 #define HWRM_CFA_FLOW_FLUSH_INPUT_PAGE_SIZE_1M UINT32_C(0x8)
31394 /* The page size is 2M */
31395 #define HWRM_CFA_FLOW_FLUSH_INPUT_PAGE_SIZE_2M UINT32_C(0x9)
31396 /* The page size is 4M */
31397 #define HWRM_CFA_FLOW_FLUSH_INPUT_PAGE_SIZE_4M UINT32_C(0xa)
31398 /* The page size is 1G */
31399 #define HWRM_CFA_FLOW_FLUSH_INPUT_PAGE_SIZE_1G UINT32_C(0x12)
31400 #define HWRM_CFA_FLOW_FLUSH_INPUT_PAGE_SIZE_LAST \
31401 HWRM_CFA_FLOW_FLUSH_INPUT_PAGE_SIZE_1G
31402 /* FLow table memory indirect levels. */
31403 uint8_t page_level;
31404 /* PBL pointer is physical start address. */
31405 #define HWRM_CFA_FLOW_FLUSH_INPUT_PAGE_LEVEL_LVL_0 UINT32_C(0x0)
31406 /* PBL pointer points to PTE table. */
31407 #define HWRM_CFA_FLOW_FLUSH_INPUT_PAGE_LEVEL_LVL_1 UINT32_C(0x1)
31408 /* PBL pointer points to PDE table with each entry pointing to PTE tables. */
31409 #define HWRM_CFA_FLOW_FLUSH_INPUT_PAGE_LEVEL_LVL_2 UINT32_C(0x2)
31410 #define HWRM_CFA_FLOW_FLUSH_INPUT_PAGE_LEVEL_LAST \
31411 HWRM_CFA_FLOW_FLUSH_INPUT_PAGE_LEVEL_LVL_2
31412 /* number of flows in the flow table */
31413 uint16_t num_flows;
31414 /* Pointer to the PBL, or PDL depending on number of levels */
31418 /* hwrm_cfa_flow_flush_output (size:128b/16B) */
31419 struct hwrm_cfa_flow_flush_output {
31420 /* The specific error status for the command. */
31421 uint16_t error_code;
31422 /* The HWRM command request type. */
31424 /* The sequence ID from the original command. */
31426 /* The length of the response data in number of bytes. */
31428 uint8_t unused_0[7];
31430 * This field is used in Output records to indicate that the output
31431 * is completely written to RAM. This field should be read as '1'
31432 * to indicate that the output has been completely written.
31433 * When writing a command completion or response to an internal processor,
31434 * the order of writes has to be such that this field is written last.
31439 /***********************
31440 * hwrm_cfa_flow_stats *
31441 ***********************/
31444 /* hwrm_cfa_flow_stats_input (size:640b/80B) */
31445 struct hwrm_cfa_flow_stats_input {
31446 /* The HWRM command request type. */
31449 * The completion ring to send the completion event on. This should
31450 * be the NQ ID returned from the `nq_alloc` HWRM command.
31452 uint16_t cmpl_ring;
31454 * The sequence ID is used by the driver for tracking multiple
31455 * commands. This ID is treated as opaque data by the firmware and
31456 * the value is returned in the `hwrm_resp_hdr` upon completion.
31460 * The target ID of the command:
31461 * * 0x0-0xFFF8 - The function ID
31462 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
31463 * * 0xFFFD - Reserved for user-space HWRM interface
31466 uint16_t target_id;
31468 * A physical address pointer pointing to a host buffer that the
31469 * command's response data will be written. This can be either a host
31470 * physical address (HPA) or a guest physical address (GPA) and must
31471 * point to a physically contiguous block of memory.
31473 uint64_t resp_addr;
31475 uint16_t num_flows;
31477 uint16_t flow_handle_0;
31479 uint16_t flow_handle_1;
31481 uint16_t flow_handle_2;
31483 uint16_t flow_handle_3;
31485 uint16_t flow_handle_4;
31487 uint16_t flow_handle_5;
31489 uint16_t flow_handle_6;
31491 uint16_t flow_handle_7;
31493 uint16_t flow_handle_8;
31495 uint16_t flow_handle_9;
31496 uint8_t unused_0[2];
31497 /* Flow ID of a flow. */
31498 uint32_t flow_id_0;
31499 /* Flow ID of a flow. */
31500 uint32_t flow_id_1;
31501 /* Flow ID of a flow. */
31502 uint32_t flow_id_2;
31503 /* Flow ID of a flow. */
31504 uint32_t flow_id_3;
31505 /* Flow ID of a flow. */
31506 uint32_t flow_id_4;
31507 /* Flow ID of a flow. */
31508 uint32_t flow_id_5;
31509 /* Flow ID of a flow. */
31510 uint32_t flow_id_6;
31511 /* Flow ID of a flow. */
31512 uint32_t flow_id_7;
31513 /* Flow ID of a flow. */
31514 uint32_t flow_id_8;
31515 /* Flow ID of a flow. */
31516 uint32_t flow_id_9;
31519 /* hwrm_cfa_flow_stats_output (size:1408b/176B) */
31520 struct hwrm_cfa_flow_stats_output {
31521 /* The specific error status for the command. */
31522 uint16_t error_code;
31523 /* The HWRM command request type. */
31525 /* The sequence ID from the original command. */
31527 /* The length of the response data in number of bytes. */
31529 /* packet_0 is 64 b */
31531 /* packet_1 is 64 b */
31533 /* packet_2 is 64 b */
31535 /* packet_3 is 64 b */
31537 /* packet_4 is 64 b */
31539 /* packet_5 is 64 b */
31541 /* packet_6 is 64 b */
31543 /* packet_7 is 64 b */
31545 /* packet_8 is 64 b */
31547 /* packet_9 is 64 b */
31549 /* byte_0 is 64 b */
31551 /* byte_1 is 64 b */
31553 /* byte_2 is 64 b */
31555 /* byte_3 is 64 b */
31557 /* byte_4 is 64 b */
31559 /* byte_5 is 64 b */
31561 /* byte_6 is 64 b */
31563 /* byte_7 is 64 b */
31565 /* byte_8 is 64 b */
31567 /* byte_9 is 64 b */
31569 uint8_t unused_0[7];
31571 * This field is used in Output records to indicate that the output
31572 * is completely written to RAM. This field should be read as '1'
31573 * to indicate that the output has been completely written.
31574 * When writing a command completion or response to an internal processor,
31575 * the order of writes has to be such that this field is written last.
31580 /***********************************
31581 * hwrm_cfa_flow_aging_timer_reset *
31582 ***********************************/
31585 /* hwrm_cfa_flow_aging_timer_reset_input (size:256b/32B) */
31586 struct hwrm_cfa_flow_aging_timer_reset_input {
31587 /* The HWRM command request type. */
31590 * The completion ring to send the completion event on. This should
31591 * be the NQ ID returned from the `nq_alloc` HWRM command.
31593 uint16_t cmpl_ring;
31595 * The sequence ID is used by the driver for tracking multiple
31596 * commands. This ID is treated as opaque data by the firmware and
31597 * the value is returned in the `hwrm_resp_hdr` upon completion.
31601 * The target ID of the command:
31602 * * 0x0-0xFFF8 - The function ID
31603 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
31604 * * 0xFFFD - Reserved for user-space HWRM interface
31607 uint16_t target_id;
31609 * A physical address pointer pointing to a host buffer that the
31610 * command's response data will be written. This can be either a host
31611 * physical address (HPA) or a guest physical address (GPA) and must
31612 * point to a physically contiguous block of memory.
31614 uint64_t resp_addr;
31615 /* Flow record index. */
31616 uint16_t flow_handle;
31617 uint8_t unused_0[2];
31619 * New flow timer value for the flow specified in the ext_flow_handle.
31620 * The flow timer unit is 100ms.
31622 uint32_t flow_timer;
31623 /* This value identifies a set of CFA data structures used for a flow. */
31624 uint64_t ext_flow_handle;
31627 /* hwrm_cfa_flow_aging_timer_reset_output (size:128b/16B) */
31628 struct hwrm_cfa_flow_aging_timer_reset_output {
31629 /* The specific error status for the command. */
31630 uint16_t error_code;
31631 /* The HWRM command request type. */
31633 /* The sequence ID from the original command. */
31635 /* The length of the response data in number of bytes. */
31637 uint8_t unused_0[7];
31639 * This field is used in Output records to indicate that the output
31640 * is completely written to RAM. This field should be read as '1'
31641 * to indicate that the output has been completely written.
31642 * When writing a command completion or response to an internal processor,
31643 * the order of writes has to be such that this field is written last.
31648 /***************************
31649 * hwrm_cfa_flow_aging_cfg *
31650 ***************************/
31653 /* hwrm_cfa_flow_aging_cfg_input (size:384b/48B) */
31654 struct hwrm_cfa_flow_aging_cfg_input {
31655 /* The HWRM command request type. */
31658 * The completion ring to send the completion event on. This should
31659 * be the NQ ID returned from the `nq_alloc` HWRM command.
31661 uint16_t cmpl_ring;
31663 * The sequence ID is used by the driver for tracking multiple
31664 * commands. This ID is treated as opaque data by the firmware and
31665 * the value is returned in the `hwrm_resp_hdr` upon completion.
31669 * The target ID of the command:
31670 * * 0x0-0xFFF8 - The function ID
31671 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
31672 * * 0xFFFD - Reserved for user-space HWRM interface
31675 uint16_t target_id;
31677 * A physical address pointer pointing to a host buffer that the
31678 * command's response data will be written. This can be either a host
31679 * physical address (HPA) or a guest physical address (GPA) and must
31680 * point to a physically contiguous block of memory.
31682 uint64_t resp_addr;
31683 /* The bit field to enable per flow aging configuration. */
31685 /* This bit must be '1' for the tcp flow timer field to be configured */
31686 #define HWRM_CFA_FLOW_AGING_CFG_INPUT_ENABLES_TCP_FLOW_TIMER \
31688 /* This bit must be '1' for the tcp finish timer field to be configured */
31689 #define HWRM_CFA_FLOW_AGING_CFG_INPUT_ENABLES_TCP_FIN_TIMER \
31691 /* This bit must be '1' for the udp flow timer field to be configured */
31692 #define HWRM_CFA_FLOW_AGING_CFG_INPUT_ENABLES_UDP_FLOW_TIMER \
31694 /* This bit must be '1' for the eem dma interval field to be configured */
31695 #define HWRM_CFA_FLOW_AGING_CFG_INPUT_ENABLES_EEM_DMA_INTERVAL \
31697 /* This bit must be '1' for the eem notice interval field to be configured */
31698 #define HWRM_CFA_FLOW_AGING_CFG_INPUT_ENABLES_EEM_NOTICE_INTERVAL \
31700 /* This bit must be '1' for the eem context memory maximum entries field to be configured */
31701 #define HWRM_CFA_FLOW_AGING_CFG_INPUT_ENABLES_EEM_CTX_MAX_ENTRIES \
31703 /* This bit must be '1' for the eem context memory ID field to be configured */
31704 #define HWRM_CFA_FLOW_AGING_CFG_INPUT_ENABLES_EEM_CTX_ID \
31706 /* This bit must be '1' for the eem context memory type field to be configured */
31707 #define HWRM_CFA_FLOW_AGING_CFG_INPUT_ENABLES_EEM_CTX_MEM_TYPE \
31710 /* Enumeration denoting the RX, TX type of the resource. */
31711 #define HWRM_CFA_FLOW_AGING_CFG_INPUT_FLAGS_PATH UINT32_C(0x1)
31713 #define HWRM_CFA_FLOW_AGING_CFG_INPUT_FLAGS_PATH_TX UINT32_C(0x0)
31715 #define HWRM_CFA_FLOW_AGING_CFG_INPUT_FLAGS_PATH_RX UINT32_C(0x1)
31716 #define HWRM_CFA_FLOW_AGING_CFG_INPUT_FLAGS_PATH_LAST \
31717 HWRM_CFA_FLOW_AGING_CFG_INPUT_FLAGS_PATH_RX
31718 /* Enumeration denoting the enable, disable eem flow aging configuration. */
31719 #define HWRM_CFA_FLOW_AGING_CFG_INPUT_FLAGS_EEM UINT32_C(0x2)
31721 #define HWRM_CFA_FLOW_AGING_CFG_INPUT_FLAGS_EEM_DISABLE \
31722 (UINT32_C(0x0) << 1)
31724 #define HWRM_CFA_FLOW_AGING_CFG_INPUT_FLAGS_EEM_ENABLE \
31725 (UINT32_C(0x1) << 1)
31726 #define HWRM_CFA_FLOW_AGING_CFG_INPUT_FLAGS_EEM_LAST \
31727 HWRM_CFA_FLOW_AGING_CFG_INPUT_FLAGS_EEM_ENABLE
31729 /* The flow aging timer for all TCP flows, the unit is 100 milliseconds. */
31730 uint32_t tcp_flow_timer;
31731 /* The TCP finished timer for all TCP flows, the unit is 100 milliseconds. */
31732 uint32_t tcp_fin_timer;
31733 /* The flow aging timer for all UDP flows, the unit is 100 milliseconds. */
31734 uint32_t udp_flow_timer;
31735 /* The interval to dma eem ejection data to host memory, the unit is milliseconds. */
31736 uint16_t eem_dma_interval;
31737 /* The interval to notify driver to read the eem ejection data, the unit is milliseconds. */
31738 uint16_t eem_notice_interval;
31739 /* The maximum entries number in the eem context memory. */
31740 uint32_t eem_ctx_max_entries;
31741 /* The context memory ID for eem flow aging. */
31742 uint16_t eem_ctx_id;
31743 uint16_t eem_ctx_mem_type;
31744 /* The content of context memory is eem ejection data, the size of each entry is 4 bytes. */
31745 #define HWRM_CFA_FLOW_AGING_CFG_INPUT_EEM_CTX_MEM_TYPE_EJECTION_DATA \
31747 #define HWRM_CFA_FLOW_AGING_CFG_INPUT_EEM_CTX_MEM_TYPE_LAST \
31748 HWRM_CFA_FLOW_AGING_CFG_INPUT_EEM_CTX_MEM_TYPE_EJECTION_DATA
31749 uint8_t unused_1[4];
31752 /* hwrm_cfa_flow_aging_cfg_output (size:128b/16B) */
31753 struct hwrm_cfa_flow_aging_cfg_output {
31754 /* The specific error status for the command. */
31755 uint16_t error_code;
31756 /* The HWRM command request type. */
31758 /* The sequence ID from the original command. */
31760 /* The length of the response data in number of bytes. */
31762 uint8_t unused_0[7];
31764 * This field is used in Output records to indicate that the output
31765 * is completely written to RAM. This field should be read as '1'
31766 * to indicate that the output has been completely written.
31767 * When writing a command completion or response to an internal processor,
31768 * the order of writes has to be such that this field is written last.
31773 /****************************
31774 * hwrm_cfa_flow_aging_qcfg *
31775 ****************************/
31778 /* hwrm_cfa_flow_aging_qcfg_input (size:192b/24B) */
31779 struct hwrm_cfa_flow_aging_qcfg_input {
31780 /* The HWRM command request type. */
31783 * The completion ring to send the completion event on. This should
31784 * be the NQ ID returned from the `nq_alloc` HWRM command.
31786 uint16_t cmpl_ring;
31788 * The sequence ID is used by the driver for tracking multiple
31789 * commands. This ID is treated as opaque data by the firmware and
31790 * the value is returned in the `hwrm_resp_hdr` upon completion.
31794 * The target ID of the command:
31795 * * 0x0-0xFFF8 - The function ID
31796 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
31797 * * 0xFFFD - Reserved for user-space HWRM interface
31800 uint16_t target_id;
31802 * A physical address pointer pointing to a host buffer that the
31803 * command's response data will be written. This can be either a host
31804 * physical address (HPA) or a guest physical address (GPA) and must
31805 * point to a physically contiguous block of memory.
31807 uint64_t resp_addr;
31808 /* The direction for the flow aging configuration, 1 is rx path, 2 is tx path. */
31810 /* Enumeration denoting the RX, TX type of the resource. */
31811 #define HWRM_CFA_FLOW_AGING_QCFG_INPUT_FLAGS_PATH UINT32_C(0x1)
31813 #define HWRM_CFA_FLOW_AGING_QCFG_INPUT_FLAGS_PATH_TX UINT32_C(0x0)
31815 #define HWRM_CFA_FLOW_AGING_QCFG_INPUT_FLAGS_PATH_RX UINT32_C(0x1)
31816 #define HWRM_CFA_FLOW_AGING_QCFG_INPUT_FLAGS_PATH_LAST \
31817 HWRM_CFA_FLOW_AGING_QCFG_INPUT_FLAGS_PATH_RX
31818 uint8_t unused_0[7];
31821 /* hwrm_cfa_flow_aging_qcfg_output (size:320b/40B) */
31822 struct hwrm_cfa_flow_aging_qcfg_output {
31823 /* The specific error status for the command. */
31824 uint16_t error_code;
31825 /* The HWRM command request type. */
31827 /* The sequence ID from the original command. */
31829 /* The length of the response data in number of bytes. */
31831 /* The current flow aging timer for all TCP flows, the unit is 100 millisecond. */
31832 uint32_t tcp_flow_timer;
31833 /* The current TCP finished timer for all TCP flows, the unit is 100 millisecond. */
31834 uint32_t tcp_fin_timer;
31835 /* The current flow aging timer for all UDP flows, the unit is 100 millisecond. */
31836 uint32_t udp_flow_timer;
31837 /* The interval to dma eem ejection data to host memory, the unit is milliseconds. */
31838 uint16_t eem_dma_interval;
31839 /* The interval to notify driver to read the eem ejection data, the unit is milliseconds. */
31840 uint16_t eem_notice_interval;
31841 /* The maximum entries number in the eem context memory. */
31842 uint32_t eem_ctx_max_entries;
31843 /* The context memory ID for eem flow aging. */
31844 uint16_t eem_ctx_id;
31845 /* The context memory type for eem flow aging. */
31846 uint16_t eem_ctx_mem_type;
31847 uint8_t unused_0[7];
31849 * This field is used in Output records to indicate that the output
31850 * is completely written to RAM. This field should be read as '1'
31851 * to indicate that the output has been completely written.
31852 * When writing a command completion or response to an internal processor,
31853 * the order of writes has to be such that this field is written last.
31858 /*****************************
31859 * hwrm_cfa_flow_aging_qcaps *
31860 *****************************/
31863 /* hwrm_cfa_flow_aging_qcaps_input (size:192b/24B) */
31864 struct hwrm_cfa_flow_aging_qcaps_input {
31865 /* The HWRM command request type. */
31868 * The completion ring to send the completion event on. This should
31869 * be the NQ ID returned from the `nq_alloc` HWRM command.
31871 uint16_t cmpl_ring;
31873 * The sequence ID is used by the driver for tracking multiple
31874 * commands. This ID is treated as opaque data by the firmware and
31875 * the value is returned in the `hwrm_resp_hdr` upon completion.
31879 * The target ID of the command:
31880 * * 0x0-0xFFF8 - The function ID
31881 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
31882 * * 0xFFFD - Reserved for user-space HWRM interface
31885 uint16_t target_id;
31887 * A physical address pointer pointing to a host buffer that the
31888 * command's response data will be written. This can be either a host
31889 * physical address (HPA) or a guest physical address (GPA) and must
31890 * point to a physically contiguous block of memory.
31892 uint64_t resp_addr;
31893 /* The direction for the flow aging configuration, 1 is rx path, 2 is tx path. */
31895 /* Enumeration denoting the RX, TX type of the resource. */
31896 #define HWRM_CFA_FLOW_AGING_QCAPS_INPUT_FLAGS_PATH UINT32_C(0x1)
31898 #define HWRM_CFA_FLOW_AGING_QCAPS_INPUT_FLAGS_PATH_TX UINT32_C(0x0)
31900 #define HWRM_CFA_FLOW_AGING_QCAPS_INPUT_FLAGS_PATH_RX UINT32_C(0x1)
31901 #define HWRM_CFA_FLOW_AGING_QCAPS_INPUT_FLAGS_PATH_LAST \
31902 HWRM_CFA_FLOW_AGING_QCAPS_INPUT_FLAGS_PATH_RX
31903 uint8_t unused_0[7];
31906 /* hwrm_cfa_flow_aging_qcaps_output (size:256b/32B) */
31907 struct hwrm_cfa_flow_aging_qcaps_output {
31908 /* The specific error status for the command. */
31909 uint16_t error_code;
31910 /* The HWRM command request type. */
31912 /* The sequence ID from the original command. */
31914 /* The length of the response data in number of bytes. */
31916 /* The maximum flow aging timer for all TCP flows, the unit is 100 millisecond. */
31917 uint32_t max_tcp_flow_timer;
31918 /* The maximum TCP finished timer for all TCP flows, the unit is 100 millisecond. */
31919 uint32_t max_tcp_fin_timer;
31920 /* The maximum flow aging timer for all UDP flows, the unit is 100 millisecond. */
31921 uint32_t max_udp_flow_timer;
31922 /* The maximum aging flows that HW can support. */
31923 uint32_t max_aging_flows;
31924 uint8_t unused_0[7];
31926 * This field is used in Output records to indicate that the output
31927 * is completely written to RAM. This field should be read as '1'
31928 * to indicate that the output has been completely written.
31929 * When writing a command completion or response to an internal processor,
31930 * the order of writes has to be such that this field is written last.
31935 /**********************************
31936 * hwrm_cfa_tcp_flag_process_qcfg *
31937 **********************************/
31940 /* hwrm_cfa_tcp_flag_process_qcfg_input (size:128b/16B) */
31941 struct hwrm_cfa_tcp_flag_process_qcfg_input {
31942 /* The HWRM command request type. */
31945 * The completion ring to send the completion event on. This should
31946 * be the NQ ID returned from the `nq_alloc` HWRM command.
31948 uint16_t cmpl_ring;
31950 * The sequence ID is used by the driver for tracking multiple
31951 * commands. This ID is treated as opaque data by the firmware and
31952 * the value is returned in the `hwrm_resp_hdr` upon completion.
31956 * The target ID of the command:
31957 * * 0x0-0xFFF8 - The function ID
31958 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
31959 * * 0xFFFD - Reserved for user-space HWRM interface
31962 uint16_t target_id;
31964 * A physical address pointer pointing to a host buffer that the
31965 * command's response data will be written. This can be either a host
31966 * physical address (HPA) or a guest physical address (GPA) and must
31967 * point to a physically contiguous block of memory.
31969 uint64_t resp_addr;
31972 /* hwrm_cfa_tcp_flag_process_qcfg_output (size:192b/24B) */
31973 struct hwrm_cfa_tcp_flag_process_qcfg_output {
31974 /* The specific error status for the command. */
31975 uint16_t error_code;
31976 /* The HWRM command request type. */
31978 /* The sequence ID from the original command. */
31980 /* The length of the response data in number of bytes. */
31982 /* The port 0 RX mirror action record ID. */
31983 uint16_t rx_ar_id_port0;
31984 /* The port 1 RX mirror action record ID. */
31985 uint16_t rx_ar_id_port1;
31986 /* The port 0 RX action record ID for TX TCP flag packets from loopback path. */
31987 uint16_t tx_ar_id_port0;
31988 /* The port 1 RX action record ID for TX TCP flag packets from loopback path. */
31989 uint16_t tx_ar_id_port1;
31990 uint8_t unused_0[7];
31992 * This field is used in Output records to indicate that the output
31993 * is completely written to RAM. This field should be read as '1'
31994 * to indicate that the output has been completely written.
31995 * When writing a command completion or response to an internal processor,
31996 * the order of writes has to be such that this field is written last.
32001 /**********************
32002 * hwrm_cfa_pair_info *
32003 **********************/
32006 /* hwrm_cfa_pair_info_input (size:448b/56B) */
32007 struct hwrm_cfa_pair_info_input {
32008 /* The HWRM command request type. */
32011 * The completion ring to send the completion event on. This should
32012 * be the NQ ID returned from the `nq_alloc` HWRM command.
32014 uint16_t cmpl_ring;
32016 * The sequence ID is used by the driver for tracking multiple
32017 * commands. This ID is treated as opaque data by the firmware and
32018 * the value is returned in the `hwrm_resp_hdr` upon completion.
32022 * The target ID of the command:
32023 * * 0x0-0xFFF8 - The function ID
32024 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
32025 * * 0xFFFD - Reserved for user-space HWRM interface
32028 uint16_t target_id;
32030 * A physical address pointer pointing to a host buffer that the
32031 * command's response data will be written. This can be either a host
32032 * physical address (HPA) or a guest physical address (GPA) and must
32033 * point to a physically contiguous block of memory.
32035 uint64_t resp_addr;
32037 /* If this flag is set, lookup by name else lookup by index. */
32038 #define HWRM_CFA_PAIR_INFO_INPUT_FLAGS_LOOKUP_TYPE UINT32_C(0x1)
32039 /* If this flag is set, lookup by PF id and VF id. */
32040 #define HWRM_CFA_PAIR_INFO_INPUT_FLAGS_LOOKUP_REPRE UINT32_C(0x2)
32041 /* Pair table index. */
32042 uint16_t pair_index;
32043 /* Pair pf index. */
32045 /* Pair vf index. */
32047 /* Pair name (32 byte string). */
32048 char pair_name[32];
32051 /* hwrm_cfa_pair_info_output (size:576b/72B) */
32052 struct hwrm_cfa_pair_info_output {
32053 /* The specific error status for the command. */
32054 uint16_t error_code;
32055 /* The HWRM command request type. */
32057 /* The sequence ID from the original command. */
32059 /* The length of the response data in number of bytes. */
32061 /* Pair table index. */
32062 uint16_t next_pair_index;
32063 /* Pair member a's fid. */
32065 /* Logical host number. */
32066 uint8_t host_a_index;
32067 /* Logical PF number. */
32068 uint8_t pf_a_index;
32069 /* Pair member a's Linux logical VF number. */
32070 uint16_t vf_a_index;
32072 uint16_t rx_cfa_code_a;
32073 /* Tx CFA action. */
32074 uint16_t tx_cfa_action_a;
32075 /* Pair member b's fid. */
32077 /* Logical host number. */
32078 uint8_t host_b_index;
32079 /* Logical PF number. */
32080 uint8_t pf_b_index;
32081 /* Pair member a's Linux logical VF number. */
32082 uint16_t vf_b_index;
32084 uint16_t rx_cfa_code_b;
32085 /* Tx CFA action. */
32086 uint16_t tx_cfa_action_b;
32087 /* Pair mode (0-vf2fn, 1-rep2fn, 2-rep2rep, 3-proxy, 4-pfpair). */
32089 /* Pair between VF on local host with PF or VF on specified host. */
32090 #define HWRM_CFA_PAIR_INFO_OUTPUT_PAIR_MODE_VF2FN UINT32_C(0x0)
32091 /* Pair between REP on local host with PF or VF on specified host. */
32092 #define HWRM_CFA_PAIR_INFO_OUTPUT_PAIR_MODE_REP2FN UINT32_C(0x1)
32093 /* Pair between REP on local host with REP on specified host. */
32094 #define HWRM_CFA_PAIR_INFO_OUTPUT_PAIR_MODE_REP2REP UINT32_C(0x2)
32095 /* Pair for the proxy interface. */
32096 #define HWRM_CFA_PAIR_INFO_OUTPUT_PAIR_MODE_PROXY UINT32_C(0x3)
32097 /* Pair for the PF interface. */
32098 #define HWRM_CFA_PAIR_INFO_OUTPUT_PAIR_MODE_PFPAIR UINT32_C(0x4)
32099 #define HWRM_CFA_PAIR_INFO_OUTPUT_PAIR_MODE_LAST \
32100 HWRM_CFA_PAIR_INFO_OUTPUT_PAIR_MODE_PFPAIR
32102 uint8_t pair_state;
32103 /* Pair has been allocated */
32104 #define HWRM_CFA_PAIR_INFO_OUTPUT_PAIR_STATE_ALLOCATED UINT32_C(0x1)
32105 /* Both pair members are active */
32106 #define HWRM_CFA_PAIR_INFO_OUTPUT_PAIR_STATE_ACTIVE UINT32_C(0x2)
32107 #define HWRM_CFA_PAIR_INFO_OUTPUT_PAIR_STATE_LAST \
32108 HWRM_CFA_PAIR_INFO_OUTPUT_PAIR_STATE_ACTIVE
32109 /* Pair name (32 byte string). */
32110 char pair_name[32];
32111 uint8_t unused_0[7];
32113 * This field is used in Output records to indicate that the output
32114 * is completely written to RAM. This field should be read as '1'
32115 * to indicate that the output has been completely written.
32116 * When writing a command completion or response to an internal processor,
32117 * the order of writes has to be such that this field is written last.
32122 /***************************************
32123 * hwrm_cfa_redirect_query_tunnel_type *
32124 ***************************************/
32127 /* hwrm_cfa_redirect_query_tunnel_type_input (size:192b/24B) */
32128 struct hwrm_cfa_redirect_query_tunnel_type_input {
32129 /* The HWRM command request type. */
32132 * The completion ring to send the completion event on. This should
32133 * be the NQ ID returned from the `nq_alloc` HWRM command.
32135 uint16_t cmpl_ring;
32137 * The sequence ID is used by the driver for tracking multiple
32138 * commands. This ID is treated as opaque data by the firmware and
32139 * the value is returned in the `hwrm_resp_hdr` upon completion.
32143 * The target ID of the command:
32144 * * 0x0-0xFFF8 - The function ID
32145 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
32146 * * 0xFFFD - Reserved for user-space HWRM interface
32149 uint16_t target_id;
32151 * A physical address pointer pointing to a host buffer that the
32152 * command's response data will be written. This can be either a host
32153 * physical address (HPA) or a guest physical address (GPA) and must
32154 * point to a physically contiguous block of memory.
32156 uint64_t resp_addr;
32157 /* The source function id. */
32159 uint8_t unused_0[6];
32162 /* hwrm_cfa_redirect_query_tunnel_type_output (size:128b/16B) */
32163 struct hwrm_cfa_redirect_query_tunnel_type_output {
32164 /* The specific error status for the command. */
32165 uint16_t error_code;
32166 /* The HWRM command request type. */
32168 /* The sequence ID from the original command. */
32170 /* The length of the response data in number of bytes. */
32173 uint32_t tunnel_mask;
32175 #define HWRM_CFA_REDIRECT_QUERY_TUNNEL_TYPE_OUTPUT_TUNNEL_MASK_NONTUNNEL \
32177 /* Virtual eXtensible Local Area Network (VXLAN) */
32178 #define HWRM_CFA_REDIRECT_QUERY_TUNNEL_TYPE_OUTPUT_TUNNEL_MASK_VXLAN \
32180 /* Network Virtualization Generic Routing Encapsulation (NVGRE) */
32181 #define HWRM_CFA_REDIRECT_QUERY_TUNNEL_TYPE_OUTPUT_TUNNEL_MASK_NVGRE \
32183 /* Generic Routing Encapsulation (GRE) inside Ethernet payload */
32184 #define HWRM_CFA_REDIRECT_QUERY_TUNNEL_TYPE_OUTPUT_TUNNEL_MASK_L2GRE \
32187 #define HWRM_CFA_REDIRECT_QUERY_TUNNEL_TYPE_OUTPUT_TUNNEL_MASK_IPIP \
32189 /* Generic Network Virtualization Encapsulation (Geneve) */
32190 #define HWRM_CFA_REDIRECT_QUERY_TUNNEL_TYPE_OUTPUT_TUNNEL_MASK_GENEVE \
32192 /* Multi-Protocol Label Switching (MPLS) */
32193 #define HWRM_CFA_REDIRECT_QUERY_TUNNEL_TYPE_OUTPUT_TUNNEL_MASK_MPLS \
32195 /* Stateless Transport Tunnel (STT) */
32196 #define HWRM_CFA_REDIRECT_QUERY_TUNNEL_TYPE_OUTPUT_TUNNEL_MASK_STT \
32198 /* Generic Routing Encapsulation (GRE) inside IP datagram payload */
32199 #define HWRM_CFA_REDIRECT_QUERY_TUNNEL_TYPE_OUTPUT_TUNNEL_MASK_IPGRE \
32201 /* IPV4 over virtual eXtensible Local Area Network (IPV4oVXLAN) */
32202 #define HWRM_CFA_REDIRECT_QUERY_TUNNEL_TYPE_OUTPUT_TUNNEL_MASK_VXLAN_V4 \
32204 /* Enhance Generic Routing Encapsulation (GRE version 1) inside IP datagram payload */
32205 #define HWRM_CFA_REDIRECT_QUERY_TUNNEL_TYPE_OUTPUT_TUNNEL_MASK_IPGRE_V1 \
32207 /* Any tunneled traffic */
32208 #define HWRM_CFA_REDIRECT_QUERY_TUNNEL_TYPE_OUTPUT_TUNNEL_MASK_ANYTUNNEL \
32210 /* Use fixed layer 2 ether type of 0xFFFF */
32211 #define HWRM_CFA_REDIRECT_QUERY_TUNNEL_TYPE_OUTPUT_TUNNEL_MASK_L2_ETYPE \
32213 /* IPV6 over virtual eXtensible Local Area Network with GPE header (IPV6oVXLANGPE) */
32214 #define HWRM_CFA_REDIRECT_QUERY_TUNNEL_TYPE_OUTPUT_TUNNEL_MASK_VXLAN_GPE_V6 \
32216 uint8_t unused_0[3];
32218 * This field is used in Output records to indicate that the output
32219 * is completely written to RAM. This field should be read as '1'
32220 * to indicate that the output has been completely written.
32221 * When writing a command completion or response to an internal processor,
32222 * the order of writes has to be such that this field is written last.
32227 /*************************
32228 * hwrm_cfa_ctx_mem_rgtr *
32229 *************************/
32232 /* hwrm_cfa_ctx_mem_rgtr_input (size:256b/32B) */
32233 struct hwrm_cfa_ctx_mem_rgtr_input {
32234 /* The HWRM command request type. */
32237 * The completion ring to send the completion event on. This should
32238 * be the NQ ID returned from the `nq_alloc` HWRM command.
32240 uint16_t cmpl_ring;
32242 * The sequence ID is used by the driver for tracking multiple
32243 * commands. This ID is treated as opaque data by the firmware and
32244 * the value is returned in the `hwrm_resp_hdr` upon completion.
32248 * The target ID of the command:
32249 * * 0x0-0xFFF8 - The function ID
32250 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
32251 * * 0xFFFD - Reserved for user-space HWRM interface
32254 uint16_t target_id;
32256 * A physical address pointer pointing to a host buffer that the
32257 * command's response data will be written. This can be either a host
32258 * physical address (HPA) or a guest physical address (GPA) and must
32259 * point to a physically contiguous block of memory.
32261 uint64_t resp_addr;
32263 /* Counter PBL indirect levels. */
32264 uint8_t page_level;
32265 /* PBL pointer is physical start address. */
32266 #define HWRM_CFA_CTX_MEM_RGTR_INPUT_PAGE_LEVEL_LVL_0 UINT32_C(0x0)
32267 /* PBL pointer points to PTE table. */
32268 #define HWRM_CFA_CTX_MEM_RGTR_INPUT_PAGE_LEVEL_LVL_1 UINT32_C(0x1)
32269 /* PBL pointer points to PDE table with each entry pointing to PTE tables. */
32270 #define HWRM_CFA_CTX_MEM_RGTR_INPUT_PAGE_LEVEL_LVL_2 UINT32_C(0x2)
32271 #define HWRM_CFA_CTX_MEM_RGTR_INPUT_PAGE_LEVEL_LAST \
32272 HWRM_CFA_CTX_MEM_RGTR_INPUT_PAGE_LEVEL_LVL_2
32275 /* 4KB page size. */
32276 #define HWRM_CFA_CTX_MEM_RGTR_INPUT_PAGE_SIZE_4K UINT32_C(0x0)
32277 /* 8KB page size. */
32278 #define HWRM_CFA_CTX_MEM_RGTR_INPUT_PAGE_SIZE_8K UINT32_C(0x1)
32279 /* 64KB page size. */
32280 #define HWRM_CFA_CTX_MEM_RGTR_INPUT_PAGE_SIZE_64K UINT32_C(0x4)
32281 /* 256KB page size. */
32282 #define HWRM_CFA_CTX_MEM_RGTR_INPUT_PAGE_SIZE_256K UINT32_C(0x6)
32283 /* 1MB page size. */
32284 #define HWRM_CFA_CTX_MEM_RGTR_INPUT_PAGE_SIZE_1M UINT32_C(0x8)
32285 /* 2MB page size. */
32286 #define HWRM_CFA_CTX_MEM_RGTR_INPUT_PAGE_SIZE_2M UINT32_C(0x9)
32287 /* 4MB page size. */
32288 #define HWRM_CFA_CTX_MEM_RGTR_INPUT_PAGE_SIZE_4M UINT32_C(0xa)
32289 /* 1GB page size. */
32290 #define HWRM_CFA_CTX_MEM_RGTR_INPUT_PAGE_SIZE_1G UINT32_C(0x12)
32291 #define HWRM_CFA_CTX_MEM_RGTR_INPUT_PAGE_SIZE_LAST \
32292 HWRM_CFA_CTX_MEM_RGTR_INPUT_PAGE_SIZE_1G
32294 /* Pointer to the PBL, or PDL depending on number of levels */
32298 /* hwrm_cfa_ctx_mem_rgtr_output (size:128b/16B) */
32299 struct hwrm_cfa_ctx_mem_rgtr_output {
32300 /* The specific error status for the command. */
32301 uint16_t error_code;
32302 /* The HWRM command request type. */
32304 /* The sequence ID from the original command. */
32306 /* The length of the response data in number of bytes. */
32309 * Id/Handle to the recently register context memory. This handle is passed
32310 * to the CFA feature.
32313 uint8_t unused_0[5];
32315 * This field is used in Output records to indicate that the output
32316 * is completely written to RAM. This field should be read as '1'
32317 * to indicate that the output has been completely written.
32318 * When writing a command completion or response to an internal processor,
32319 * the order of writes has to be such that this field is written last.
32324 /***************************
32325 * hwrm_cfa_ctx_mem_unrgtr *
32326 ***************************/
32329 /* hwrm_cfa_ctx_mem_unrgtr_input (size:192b/24B) */
32330 struct hwrm_cfa_ctx_mem_unrgtr_input {
32331 /* The HWRM command request type. */
32334 * The completion ring to send the completion event on. This should
32335 * be the NQ ID returned from the `nq_alloc` HWRM command.
32337 uint16_t cmpl_ring;
32339 * The sequence ID is used by the driver for tracking multiple
32340 * commands. This ID is treated as opaque data by the firmware and
32341 * the value is returned in the `hwrm_resp_hdr` upon completion.
32345 * The target ID of the command:
32346 * * 0x0-0xFFF8 - The function ID
32347 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
32348 * * 0xFFFD - Reserved for user-space HWRM interface
32351 uint16_t target_id;
32353 * A physical address pointer pointing to a host buffer that the
32354 * command's response data will be written. This can be either a host
32355 * physical address (HPA) or a guest physical address (GPA) and must
32356 * point to a physically contiguous block of memory.
32358 uint64_t resp_addr;
32360 * Id/Handle to the recently register context memory. This handle is passed
32361 * to the CFA feature.
32364 uint8_t unused_0[6];
32367 /* hwrm_cfa_ctx_mem_unrgtr_output (size:128b/16B) */
32368 struct hwrm_cfa_ctx_mem_unrgtr_output {
32369 /* The specific error status for the command. */
32370 uint16_t error_code;
32371 /* The HWRM command request type. */
32373 /* The sequence ID from the original command. */
32375 /* The length of the response data in number of bytes. */
32377 uint8_t unused_0[7];
32379 * This field is used in Output records to indicate that the output
32380 * is completely written to RAM. This field should be read as '1'
32381 * to indicate that the output has been completely written.
32382 * When writing a command completion or response to an internal processor,
32383 * the order of writes has to be such that this field is written last.
32388 /*************************
32389 * hwrm_cfa_ctx_mem_qctx *
32390 *************************/
32393 /* hwrm_cfa_ctx_mem_qctx_input (size:192b/24B) */
32394 struct hwrm_cfa_ctx_mem_qctx_input {
32395 /* The HWRM command request type. */
32398 * The completion ring to send the completion event on. This should
32399 * be the NQ ID returned from the `nq_alloc` HWRM command.
32401 uint16_t cmpl_ring;
32403 * The sequence ID is used by the driver for tracking multiple
32404 * commands. This ID is treated as opaque data by the firmware and
32405 * the value is returned in the `hwrm_resp_hdr` upon completion.
32409 * The target ID of the command:
32410 * * 0x0-0xFFF8 - The function ID
32411 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
32412 * * 0xFFFD - Reserved for user-space HWRM interface
32415 uint16_t target_id;
32417 * A physical address pointer pointing to a host buffer that the
32418 * command's response data will be written. This can be either a host
32419 * physical address (HPA) or a guest physical address (GPA) and must
32420 * point to a physically contiguous block of memory.
32422 uint64_t resp_addr;
32424 * Id/Handle to the recently register context memory. This handle is passed
32425 * to the CFA feature.
32428 uint8_t unused_0[6];
32431 /* hwrm_cfa_ctx_mem_qctx_output (size:256b/32B) */
32432 struct hwrm_cfa_ctx_mem_qctx_output {
32433 /* The specific error status for the command. */
32434 uint16_t error_code;
32435 /* The HWRM command request type. */
32437 /* The sequence ID from the original command. */
32439 /* The length of the response data in number of bytes. */
32442 /* Counter PBL indirect levels. */
32443 uint8_t page_level;
32444 /* PBL pointer is physical start address. */
32445 #define HWRM_CFA_CTX_MEM_QCTX_OUTPUT_PAGE_LEVEL_LVL_0 UINT32_C(0x0)
32446 /* PBL pointer points to PTE table. */
32447 #define HWRM_CFA_CTX_MEM_QCTX_OUTPUT_PAGE_LEVEL_LVL_1 UINT32_C(0x1)
32448 /* PBL pointer points to PDE table with each entry pointing to PTE tables. */
32449 #define HWRM_CFA_CTX_MEM_QCTX_OUTPUT_PAGE_LEVEL_LVL_2 UINT32_C(0x2)
32450 #define HWRM_CFA_CTX_MEM_QCTX_OUTPUT_PAGE_LEVEL_LAST \
32451 HWRM_CFA_CTX_MEM_QCTX_OUTPUT_PAGE_LEVEL_LVL_2
32454 /* 4KB page size. */
32455 #define HWRM_CFA_CTX_MEM_QCTX_OUTPUT_PAGE_SIZE_4K UINT32_C(0x0)
32456 /* 8KB page size. */
32457 #define HWRM_CFA_CTX_MEM_QCTX_OUTPUT_PAGE_SIZE_8K UINT32_C(0x1)
32458 /* 64KB page size. */
32459 #define HWRM_CFA_CTX_MEM_QCTX_OUTPUT_PAGE_SIZE_64K UINT32_C(0x4)
32460 /* 256KB page size. */
32461 #define HWRM_CFA_CTX_MEM_QCTX_OUTPUT_PAGE_SIZE_256K UINT32_C(0x6)
32462 /* 1MB page size. */
32463 #define HWRM_CFA_CTX_MEM_QCTX_OUTPUT_PAGE_SIZE_1M UINT32_C(0x8)
32464 /* 2MB page size. */
32465 #define HWRM_CFA_CTX_MEM_QCTX_OUTPUT_PAGE_SIZE_2M UINT32_C(0x9)
32466 /* 4MB page size. */
32467 #define HWRM_CFA_CTX_MEM_QCTX_OUTPUT_PAGE_SIZE_4M UINT32_C(0xa)
32468 /* 1GB page size. */
32469 #define HWRM_CFA_CTX_MEM_QCTX_OUTPUT_PAGE_SIZE_1G UINT32_C(0x12)
32470 #define HWRM_CFA_CTX_MEM_QCTX_OUTPUT_PAGE_SIZE_LAST \
32471 HWRM_CFA_CTX_MEM_QCTX_OUTPUT_PAGE_SIZE_1G
32472 uint8_t unused_0[4];
32473 /* Pointer to the PBL, or PDL depending on number of levels */
32475 uint8_t unused_1[7];
32477 * This field is used in Output records to indicate that the output
32478 * is completely written to RAM. This field should be read as '1'
32479 * to indicate that the output has been completely written.
32480 * When writing a command completion or response to an internal processor,
32481 * the order of writes has to be such that this field is written last.
32486 /**************************
32487 * hwrm_cfa_ctx_mem_qcaps *
32488 **************************/
32491 /* hwrm_cfa_ctx_mem_qcaps_input (size:128b/16B) */
32492 struct hwrm_cfa_ctx_mem_qcaps_input {
32493 /* The HWRM command request type. */
32496 * The completion ring to send the completion event on. This should
32497 * be the NQ ID returned from the `nq_alloc` HWRM command.
32499 uint16_t cmpl_ring;
32501 * The sequence ID is used by the driver for tracking multiple
32502 * commands. This ID is treated as opaque data by the firmware and
32503 * the value is returned in the `hwrm_resp_hdr` upon completion.
32507 * The target ID of the command:
32508 * * 0x0-0xFFF8 - The function ID
32509 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
32510 * * 0xFFFD - Reserved for user-space HWRM interface
32513 uint16_t target_id;
32515 * A physical address pointer pointing to a host buffer that the
32516 * command's response data will be written. This can be either a host
32517 * physical address (HPA) or a guest physical address (GPA) and must
32518 * point to a physically contiguous block of memory.
32520 uint64_t resp_addr;
32523 /* hwrm_cfa_ctx_mem_qcaps_output (size:128b/16B) */
32524 struct hwrm_cfa_ctx_mem_qcaps_output {
32525 /* The specific error status for the command. */
32526 uint16_t error_code;
32527 /* The HWRM command request type. */
32529 /* The sequence ID from the original command. */
32531 /* The length of the response data in number of bytes. */
32533 /* Indicates the maximum number of context memory which can be registered. */
32534 uint16_t max_entries;
32535 uint8_t unused_0[5];
32537 * This field is used in Output records to indicate that the output
32538 * is completely written to RAM. This field should be read as '1'
32539 * to indicate that the output has been completely written.
32540 * When writing a command completion or response to an internal processor,
32541 * the order of writes has to be such that this field is written last.
32546 /**********************
32547 * hwrm_cfa_eem_qcaps *
32548 **********************/
32551 /* hwrm_cfa_eem_qcaps_input (size:192b/24B) */
32552 struct hwrm_cfa_eem_qcaps_input {
32553 /* The HWRM command request type. */
32556 * The completion ring to send the completion event on. This should
32557 * be the NQ ID returned from the `nq_alloc` HWRM command.
32559 uint16_t cmpl_ring;
32561 * The sequence ID is used by the driver for tracking multiple
32562 * commands. This ID is treated as opaque data by the firmware and
32563 * the value is returned in the `hwrm_resp_hdr` upon completion.
32567 * The target ID of the command:
32568 * * 0x0-0xFFF8 - The function ID
32569 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
32570 * * 0xFFFD - Reserved for user-space HWRM interface
32573 uint16_t target_id;
32575 * A physical address pointer pointing to a host buffer that the
32576 * command's response data will be written. This can be either a host
32577 * physical address (HPA) or a guest physical address (GPA) and must
32578 * point to a physically contiguous block of memory.
32580 uint64_t resp_addr;
32583 * When set to 1, indicates the configuration will apply to TX flows
32584 * which are to be offloaded.
32585 * Note if this bit is set then the path_rx bit can't be set.
32587 #define HWRM_CFA_EEM_QCAPS_INPUT_FLAGS_PATH_TX \
32590 * When set to 1, indicates the configuration will apply to RX flows
32591 * which are to be offloaded.
32592 * Note if this bit is set then the path_tx bit can't be set.
32594 #define HWRM_CFA_EEM_QCAPS_INPUT_FLAGS_PATH_RX \
32596 /* When set to 1, all offloaded flows will be sent to EEM. */
32597 #define HWRM_CFA_EEM_QCAPS_INPUT_FLAGS_PREFERRED_OFFLOAD \
32602 /* hwrm_cfa_eem_qcaps_output (size:320b/40B) */
32603 struct hwrm_cfa_eem_qcaps_output {
32604 /* The specific error status for the command. */
32605 uint16_t error_code;
32606 /* The HWRM command request type. */
32608 /* The sequence ID from the original command. */
32610 /* The length of the response data in number of bytes. */
32614 * When set to 1, indicates the configuration will apply to TX flows
32615 * which are to be offloaded.
32616 * Note if this bit is set then the path_rx bit can't be set.
32618 #define HWRM_CFA_EEM_QCAPS_OUTPUT_FLAGS_PATH_TX \
32621 * When set to 1, indicates the configuration will apply to RX flows
32622 * which are to be offloaded.
32623 * Note if this bit is set then the path_tx bit can't be set.
32625 #define HWRM_CFA_EEM_QCAPS_OUTPUT_FLAGS_PATH_RX \
32628 * When set to 1, indicates the the FW supports the Centralized
32629 * Memory Model. The concept designates one entity for the
32630 * memory allocation while all others ‘subscribe’ to it.
32632 #define HWRM_CFA_EEM_QCAPS_OUTPUT_FLAGS_CENTRALIZED_MEMORY_MODEL_SUPPORTED \
32635 * When set to 1, indicates the the FW supports the Detached
32636 * Centralized Memory Model. The memory is allocated and managed
32637 * as a separate entity. All PFs and VFs will be granted direct
32638 * or semi-direct access to the allocated memory while none of
32639 * which can interfere with the management of the memory.
32641 #define HWRM_CFA_EEM_QCAPS_OUTPUT_FLAGS_DETACHED_CENTRALIZED_MEMORY_MODEL_SUPPORTED \
32644 uint32_t supported;
32646 * If set to 1, then EEM KEY0 table is supported using crc32 hash.
32647 * If set to 0, EEM KEY0 table is not supported.
32649 #define HWRM_CFA_EEM_QCAPS_OUTPUT_SUPPORTED_KEY0_TABLE \
32652 * If set to 1, then EEM KEY1 table is supported using lookup3 hash.
32653 * If set to 0, EEM KEY1 table is not supported.
32655 #define HWRM_CFA_EEM_QCAPS_OUTPUT_SUPPORTED_KEY1_TABLE \
32658 * If set to 1, then EEM External Record table is supported.
32659 * If set to 0, EEM External Record table is not supported.
32660 * (This table includes action record, EFC pointers, encap pointers)
32662 #define HWRM_CFA_EEM_QCAPS_OUTPUT_SUPPORTED_EXTERNAL_RECORD_TABLE \
32665 * If set to 1, then EEM External Flow Counters table is supported.
32666 * If set to 0, EEM External Flow Counters table is not supported.
32668 #define HWRM_CFA_EEM_QCAPS_OUTPUT_SUPPORTED_EXTERNAL_FLOW_COUNTERS_TABLE \
32671 * If set to 1, then FID table used for implicit flow flush is supported.
32672 * If set to 0, then FID table used for implicit flow flush is not supported.
32674 #define HWRM_CFA_EEM_QCAPS_OUTPUT_SUPPORTED_FID_TABLE \
32677 * The maximum number of entries supported by EEM. When configuring the host memory
32678 * the number of numbers of entries that can supported are -
32679 * 32k, 64k 128k, 256k, 512k, 1M, 2M, 4M, 8M, 32M, 64M, 128M entries.
32680 * Any value that are not these values, the FW will round down to the closest support
32681 * number of entries.
32683 uint32_t max_entries_supported;
32684 /* The entry size in bytes of each entry in the EEM KEY0/KEY1 tables. */
32685 uint16_t key_entry_size;
32686 /* The entry size in bytes of each entry in the EEM RECORD tables. */
32687 uint16_t record_entry_size;
32688 /* The entry size in bytes of each entry in the EEM EFC tables. */
32689 uint16_t efc_entry_size;
32690 /* The FID size in bytes of each entry in the EEM FID tables. */
32691 uint16_t fid_entry_size;
32692 uint8_t unused_1[7];
32694 * This field is used in Output records to indicate that the output
32695 * is completely written to RAM. This field should be read as '1'
32696 * to indicate that the output has been completely written.
32697 * When writing a command completion or response to an internal processor,
32698 * the order of writes has to be such that this field is written last.
32703 /********************
32704 * hwrm_cfa_eem_cfg *
32705 ********************/
32708 /* hwrm_cfa_eem_cfg_input (size:384b/48B) */
32709 struct hwrm_cfa_eem_cfg_input {
32710 /* The HWRM command request type. */
32713 * The completion ring to send the completion event on. This should
32714 * be the NQ ID returned from the `nq_alloc` HWRM command.
32716 uint16_t cmpl_ring;
32718 * The sequence ID is used by the driver for tracking multiple
32719 * commands. This ID is treated as opaque data by the firmware and
32720 * the value is returned in the `hwrm_resp_hdr` upon completion.
32724 * The target ID of the command:
32725 * * 0x0-0xFFF8 - The function ID
32726 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
32727 * * 0xFFFD - Reserved for user-space HWRM interface
32730 uint16_t target_id;
32732 * A physical address pointer pointing to a host buffer that the
32733 * command's response data will be written. This can be either a host
32734 * physical address (HPA) or a guest physical address (GPA) and must
32735 * point to a physically contiguous block of memory.
32737 uint64_t resp_addr;
32740 * When set to 1, indicates the configuration will apply to TX flows
32741 * which are to be offloaded.
32742 * Note if this bit is set then the path_rx bit can't be set.
32744 #define HWRM_CFA_EEM_CFG_INPUT_FLAGS_PATH_TX \
32747 * When set to 1, indicates the configuration will apply to RX flows
32748 * which are to be offloaded.
32749 * Note if this bit is set then the path_tx bit can't be set.
32751 #define HWRM_CFA_EEM_CFG_INPUT_FLAGS_PATH_RX \
32753 /* When set to 1, all offloaded flows will be sent to EEM. */
32754 #define HWRM_CFA_EEM_CFG_INPUT_FLAGS_PREFERRED_OFFLOAD \
32756 /* When set to 1, secondary, 0 means primary. */
32757 #define HWRM_CFA_EEM_CFG_INPUT_FLAGS_SECONDARY_PF \
32760 * Group_id which used by Firmware to identify memory pools belonging
32761 * to certain group.
32766 * Configured EEM with the given number of entries. All the EEM tables KEY0, KEY1,
32767 * RECORD, EFC all have the same number of entries and all tables will be configured
32768 * using this value. Current minimum value is 32k. Current maximum value is 128M.
32770 uint32_t num_entries;
32772 /* Configured EEM with the given context if for KEY0 table. */
32773 uint16_t key0_ctx_id;
32774 /* Configured EEM with the given context if for KEY1 table. */
32775 uint16_t key1_ctx_id;
32776 /* Configured EEM with the given context if for RECORD table. */
32777 uint16_t record_ctx_id;
32778 /* Configured EEM with the given context if for EFC table. */
32779 uint16_t efc_ctx_id;
32780 /* Configured EEM with the given context if for EFC table. */
32781 uint16_t fid_ctx_id;
32786 /* hwrm_cfa_eem_cfg_output (size:128b/16B) */
32787 struct hwrm_cfa_eem_cfg_output {
32788 /* The specific error status for the command. */
32789 uint16_t error_code;
32790 /* The HWRM command request type. */
32792 /* The sequence ID from the original command. */
32794 /* The length of the response data in number of bytes. */
32796 uint8_t unused_0[7];
32798 * This field is used in Output records to indicate that the output
32799 * is completely written to RAM. This field should be read as '1'
32800 * to indicate that the output has been completely written.
32801 * When writing a command completion or response to an internal processor,
32802 * the order of writes has to be such that this field is written last.
32807 /*********************
32808 * hwrm_cfa_eem_qcfg *
32809 *********************/
32812 /* hwrm_cfa_eem_qcfg_input (size:192b/24B) */
32813 struct hwrm_cfa_eem_qcfg_input {
32814 /* The HWRM command request type. */
32817 * The completion ring to send the completion event on. This should
32818 * be the NQ ID returned from the `nq_alloc` HWRM command.
32820 uint16_t cmpl_ring;
32822 * The sequence ID is used by the driver for tracking multiple
32823 * commands. This ID is treated as opaque data by the firmware and
32824 * the value is returned in the `hwrm_resp_hdr` upon completion.
32828 * The target ID of the command:
32829 * * 0x0-0xFFF8 - The function ID
32830 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
32831 * * 0xFFFD - Reserved for user-space HWRM interface
32834 uint16_t target_id;
32836 * A physical address pointer pointing to a host buffer that the
32837 * command's response data will be written. This can be either a host
32838 * physical address (HPA) or a guest physical address (GPA) and must
32839 * point to a physically contiguous block of memory.
32841 uint64_t resp_addr;
32843 /* When set to 1, indicates the configuration is the TX flow. */
32844 #define HWRM_CFA_EEM_QCFG_INPUT_FLAGS_PATH_TX UINT32_C(0x1)
32845 /* When set to 1, indicates the configuration is the RX flow. */
32846 #define HWRM_CFA_EEM_QCFG_INPUT_FLAGS_PATH_RX UINT32_C(0x2)
32850 /* hwrm_cfa_eem_qcfg_output (size:256b/32B) */
32851 struct hwrm_cfa_eem_qcfg_output {
32852 /* The specific error status for the command. */
32853 uint16_t error_code;
32854 /* The HWRM command request type. */
32856 /* The sequence ID from the original command. */
32858 /* The length of the response data in number of bytes. */
32861 /* When set to 1, indicates the configuration is the TX flow. */
32862 #define HWRM_CFA_EEM_QCFG_OUTPUT_FLAGS_PATH_TX \
32864 /* When set to 1, indicates the configuration is the RX flow. */
32865 #define HWRM_CFA_EEM_QCFG_OUTPUT_FLAGS_PATH_RX \
32867 /* When set to 1, all offloaded flows will be sent to EEM. */
32868 #define HWRM_CFA_EEM_QCFG_OUTPUT_FLAGS_PREFERRED_OFFLOAD \
32870 /* The number of entries the FW has configured for EEM. */
32871 uint32_t num_entries;
32872 /* Configured EEM with the given context if for KEY0 table. */
32873 uint16_t key0_ctx_id;
32874 /* Configured EEM with the given context if for KEY1 table. */
32875 uint16_t key1_ctx_id;
32876 /* Configured EEM with the given context if for RECORD table. */
32877 uint16_t record_ctx_id;
32878 /* Configured EEM with the given context if for EFC table. */
32879 uint16_t efc_ctx_id;
32880 /* Configured EEM with the given context if for EFC table. */
32881 uint16_t fid_ctx_id;
32882 uint8_t unused_2[5];
32884 * This field is used in Output records to indicate that the output
32885 * is completely written to RAM. This field should be read as '1'
32886 * to indicate that the output has been completely written.
32887 * When writing a command completion or response to an internal processor,
32888 * the order of writes has to be such that this field is written last.
32893 /*******************
32894 * hwrm_cfa_eem_op *
32895 *******************/
32898 /* hwrm_cfa_eem_op_input (size:192b/24B) */
32899 struct hwrm_cfa_eem_op_input {
32900 /* The HWRM command request type. */
32903 * The completion ring to send the completion event on. This should
32904 * be the NQ ID returned from the `nq_alloc` HWRM command.
32906 uint16_t cmpl_ring;
32908 * The sequence ID is used by the driver for tracking multiple
32909 * commands. This ID is treated as opaque data by the firmware and
32910 * the value is returned in the `hwrm_resp_hdr` upon completion.
32914 * The target ID of the command:
32915 * * 0x0-0xFFF8 - The function ID
32916 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
32917 * * 0xFFFD - Reserved for user-space HWRM interface
32920 uint16_t target_id;
32922 * A physical address pointer pointing to a host buffer that the
32923 * command's response data will be written. This can be either a host
32924 * physical address (HPA) or a guest physical address (GPA) and must
32925 * point to a physically contiguous block of memory.
32927 uint64_t resp_addr;
32930 * When set to 1, indicates the host memory which is passed will be
32931 * used for the TX flow offload function specified in fid.
32932 * Note if this bit is set then the path_rx bit can't be set.
32934 #define HWRM_CFA_EEM_OP_INPUT_FLAGS_PATH_TX UINT32_C(0x1)
32936 * When set to 1, indicates the host memory which is passed will be
32937 * used for the RX flow offload function specified in fid.
32938 * Note if this bit is set then the path_tx bit can't be set.
32940 #define HWRM_CFA_EEM_OP_INPUT_FLAGS_PATH_RX UINT32_C(0x2)
32942 /* The number of EEM key table entries to be configured. */
32944 /* This value is reserved and should not be used. */
32945 #define HWRM_CFA_EEM_OP_INPUT_OP_RESERVED UINT32_C(0x0)
32947 * To properly stop EEM and ensure there are no DMA's, the caller
32948 * must disable EEM for the given PF, using this call. This will
32949 * safely disable EEM and ensure that all DMA'ed to the
32950 * keys/records/efc have been completed.
32952 #define HWRM_CFA_EEM_OP_INPUT_OP_EEM_DISABLE UINT32_C(0x1)
32954 * Once the EEM host memory has been configured, EEM options have
32955 * been configured. Then the caller should enable EEM for the given
32956 * PF. Note once this call has been made, then the EEM mechanism
32957 * will be active and DMA's will occur as packets are processed.
32959 #define HWRM_CFA_EEM_OP_INPUT_OP_EEM_ENABLE UINT32_C(0x2)
32961 * Clear EEM settings for the given PF so that the register values
32962 * are reset back to there initial state.
32964 #define HWRM_CFA_EEM_OP_INPUT_OP_EEM_CLEANUP UINT32_C(0x3)
32965 #define HWRM_CFA_EEM_OP_INPUT_OP_LAST \
32966 HWRM_CFA_EEM_OP_INPUT_OP_EEM_CLEANUP
32969 /* hwrm_cfa_eem_op_output (size:128b/16B) */
32970 struct hwrm_cfa_eem_op_output {
32971 /* The specific error status for the command. */
32972 uint16_t error_code;
32973 /* The HWRM command request type. */
32975 /* The sequence ID from the original command. */
32977 /* The length of the response data in number of bytes. */
32979 uint8_t unused_0[7];
32981 * This field is used in Output records to indicate that the output
32982 * is completely written to RAM. This field should be read as '1'
32983 * to indicate that the output has been completely written.
32984 * When writing a command completion or response to an internal processor,
32985 * the order of writes has to be such that this field is written last.
32990 /********************************
32991 * hwrm_cfa_adv_flow_mgnt_qcaps *
32992 ********************************/
32995 /* hwrm_cfa_adv_flow_mgnt_qcaps_input (size:256b/32B) */
32996 struct hwrm_cfa_adv_flow_mgnt_qcaps_input {
32997 /* The HWRM command request type. */
33000 * The completion ring to send the completion event on. This should
33001 * be the NQ ID returned from the `nq_alloc` HWRM command.
33003 uint16_t cmpl_ring;
33005 * The sequence ID is used by the driver for tracking multiple
33006 * commands. This ID is treated as opaque data by the firmware and
33007 * the value is returned in the `hwrm_resp_hdr` upon completion.
33011 * The target ID of the command:
33012 * * 0x0-0xFFF8 - The function ID
33013 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
33014 * * 0xFFFD - Reserved for user-space HWRM interface
33017 uint16_t target_id;
33019 * A physical address pointer pointing to a host buffer that the
33020 * command's response data will be written. This can be either a host
33021 * physical address (HPA) or a guest physical address (GPA) and must
33022 * point to a physically contiguous block of memory.
33024 uint64_t resp_addr;
33025 uint32_t unused_0[4];
33028 /* hwrm_cfa_adv_flow_mgnt_qcaps_output (size:128b/16B) */
33029 struct hwrm_cfa_adv_flow_mgnt_qcaps_output {
33030 /* The specific error status for the command. */
33031 uint16_t error_code;
33032 /* The HWRM command request type. */
33034 /* The sequence ID from the original command. */
33036 /* The length of the response data in number of bytes. */
33040 * Value of 1 to indicate firmware support 16-bit flow handle.
33041 * Value of 0 to indicate firmware not support 16-bit flow handle.
33043 #define HWRM_CFA_ADV_FLOW_MGNT_QCAPS_OUTPUT_FLAGS_FLOW_HND_16BIT_SUPPORTED \
33046 * Value of 1 to indicate firmware support 64-bit flow handle.
33047 * Value of 0 to indicate firmware not support 64-bit flow handle.
33049 #define HWRM_CFA_ADV_FLOW_MGNT_QCAPS_OUTPUT_FLAGS_FLOW_HND_64BIT_SUPPORTED \
33052 * Value of 1 to indicate firmware support flow batch delete operation through
33053 * HWRM_CFA_FLOW_FLUSH command.
33054 * Value of 0 to indicate that the firmware does not support flow batch delete
33057 #define HWRM_CFA_ADV_FLOW_MGNT_QCAPS_OUTPUT_FLAGS_FLOW_BATCH_DELETE_SUPPORTED \
33060 * Value of 1 to indicate that the firmware support flow reset all operation through
33061 * HWRM_CFA_FLOW_FLUSH command.
33062 * Value of 0 indicates firmware does not support flow reset all operation.
33064 #define HWRM_CFA_ADV_FLOW_MGNT_QCAPS_OUTPUT_FLAGS_FLOW_RESET_ALL_SUPPORTED \
33067 * Value of 1 to indicate that firmware supports use of FID as dest_id in
33068 * HWRM_CFA_NTUPLE_ALLOC/CFG commands.
33069 * Value of 0 indicates firmware does not support use of FID as dest_id.
33071 #define HWRM_CFA_ADV_FLOW_MGNT_QCAPS_OUTPUT_FLAGS_NTUPLE_FLOW_DEST_FUNC_SUPPORTED \
33074 * Value of 1 to indicate that firmware supports TX EEM flows.
33075 * Value of 0 indicates firmware does not support TX EEM flows.
33077 #define HWRM_CFA_ADV_FLOW_MGNT_QCAPS_OUTPUT_FLAGS_TX_EEM_FLOW_SUPPORTED \
33080 * Value of 1 to indicate that firmware supports RX EEM flows.
33081 * Value of 0 indicates firmware does not support RX EEM flows.
33083 #define HWRM_CFA_ADV_FLOW_MGNT_QCAPS_OUTPUT_FLAGS_RX_EEM_FLOW_SUPPORTED \
33086 * Value of 1 to indicate that firmware supports the dynamic allocation of an
33087 * on-chip flow counter which can be used for EEM flows.
33088 * Value of 0 indicates firmware does not support the dynamic allocation of an
33089 * on-chip flow counter.
33091 #define HWRM_CFA_ADV_FLOW_MGNT_QCAPS_OUTPUT_FLAGS_FLOW_COUNTER_ALLOC_SUPPORTED \
33094 * Value of 1 to indicate that firmware supports setting of
33095 * rfs_ring_tbl_idx in HWRM_CFA_NTUPLE_ALLOC command.
33096 * Value of 0 indicates firmware does not support rfs_ring_tbl_idx.
33098 #define HWRM_CFA_ADV_FLOW_MGNT_QCAPS_OUTPUT_FLAGS_RFS_RING_TBL_IDX_SUPPORTED \
33101 * Value of 1 to indicate that firmware supports untagged matching
33102 * criteria on HWRM_CFA_L2_FILTER_ALLOC command. Value of 0
33103 * indicates firmware does not support untagged matching.
33105 #define HWRM_CFA_ADV_FLOW_MGNT_QCAPS_OUTPUT_FLAGS_UNTAGGED_VLAN_SUPPORTED \
33108 * Value of 1 to indicate that firmware supports XDP filter. Value
33109 * of 0 indicates firmware does not support XDP filter.
33111 #define HWRM_CFA_ADV_FLOW_MGNT_QCAPS_OUTPUT_FLAGS_XDP_SUPPORTED \
33114 * Value of 1 to indicate that the firmware support L2 header source
33115 * fields matching criteria on HWRM_CFA_L2_FILTER_ALLOC command.
33116 * Value of 0 indicates firmware does not support L2 header source
33119 #define HWRM_CFA_ADV_FLOW_MGNT_QCAPS_OUTPUT_FLAGS_L2_HEADER_SOURCE_FIELDS_SUPPORTED \
33122 * If set to 1, firmware is capable of supporting ARP ethertype as
33123 * matching criteria for HWRM_CFA_NTUPLE_FILTER_ALLOC command on the
33124 * RX direction. By default, this flag should be 0 for older version
33127 #define HWRM_CFA_ADV_FLOW_MGNT_QCAPS_OUTPUT_FLAGS_NTUPLE_FLOW_RX_ARP_SUPPORTED \
33130 * Value of 1 to indicate that firmware supports setting of
33131 * rfs_ring_tbl_idx in dst_id field of the HWRM_CFA_NTUPLE_ALLOC
33132 * command. Value of 0 indicates firmware does not support
33133 * rfs_ring_tbl_idx in dst_id field.
33135 #define HWRM_CFA_ADV_FLOW_MGNT_QCAPS_OUTPUT_FLAGS_RFS_RING_TBL_IDX_V2_SUPPORTED \
33138 * If set to 1, firmware is capable of supporting IPv4/IPv6 as
33139 * ethertype in HWRM_CFA_NTUPLE_FILTER_ALLOC command on the RX
33140 * direction. By default, this flag should be 0 for older version
33143 #define HWRM_CFA_ADV_FLOW_MGNT_QCAPS_OUTPUT_FLAGS_NTUPLE_FLOW_RX_ETHERTYPE_IP_SUPPORTED \
33145 uint8_t unused_0[3];
33147 * This field is used in Output records to indicate that the output
33148 * is completely written to RAM. This field should be read as '1'
33149 * to indicate that the output has been completely written.
33150 * When writing a command completion or response to an internal processor,
33151 * the order of writes has to be such that this field is written last.
33156 /******************
33158 ******************/
33161 /* hwrm_cfa_tflib_input (size:1024b/128B) */
33162 struct hwrm_cfa_tflib_input {
33163 /* The HWRM command request type. */
33166 * The completion ring to send the completion event on. This should
33167 * be the NQ ID returned from the `nq_alloc` HWRM command.
33169 uint16_t cmpl_ring;
33171 * The sequence ID is used by the driver for tracking multiple
33172 * commands. This ID is treated as opaque data by the firmware and
33173 * the value is returned in the `hwrm_resp_hdr` upon completion.
33177 * The target ID of the command:
33178 * * 0x0-0xFFF8 - The function ID
33179 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
33180 * * 0xFFFD - Reserved for user-space HWRM interface
33183 uint16_t target_id;
33185 * A physical address pointer pointing to a host buffer that the
33186 * command's response data will be written. This can be either a host
33187 * physical address (HPA) or a guest physical address (GPA) and must
33188 * point to a physically contiguous block of memory.
33190 uint64_t resp_addr;
33191 /* TFLIB message type. */
33193 /* TFLIB message subtype. */
33194 uint16_t tf_subtype;
33196 uint8_t unused0[4];
33197 /* TFLIB request data. */
33198 uint32_t tf_req[26];
33201 /* hwrm_cfa_tflib_output (size:5632b/704B) */
33202 struct hwrm_cfa_tflib_output {
33203 /* The specific error status for the command. */
33204 uint16_t error_code;
33205 /* The HWRM command request type. */
33207 /* The sequence ID from the original command. */
33209 /* The length of the response data in number of bytes. */
33211 /* TFLIB message type. */
33213 /* TFLIB message subtype. */
33214 uint16_t tf_subtype;
33215 /* TFLIB response code */
33216 uint32_t tf_resp_code;
33217 /* TFLIB response data. */
33218 uint32_t tf_resp[170];
33220 uint8_t unused1[7];
33222 * This field is used in Output records to indicate that the output
33223 * is completely written to RAM. This field should be read as '1'
33224 * to indicate that the output has been completely written.
33225 * When writing a command completion or response to an internal processor,
33226 * the order of writes has to be such that this field is written last.
33236 /* hwrm_tf_input (size:1024b/128B) */
33237 struct hwrm_tf_input {
33238 /* The HWRM command request type. */
33241 * The completion ring to send the completion event on. This should
33242 * be the NQ ID returned from the `nq_alloc` HWRM command.
33244 uint16_t cmpl_ring;
33246 * The sequence ID is used by the driver for tracking multiple
33247 * commands. This ID is treated as opaque data by the firmware and
33248 * the value is returned in the `hwrm_resp_hdr` upon completion.
33252 * The target ID of the command:
33253 * * 0x0-0xFFF8 - The function ID
33254 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
33255 * * 0xFFFD - Reserved for user-space HWRM interface
33258 uint16_t target_id;
33260 * A physical address pointer pointing to a host buffer that the
33261 * command's response data will be written. This can be either a host
33262 * physical address (HPA) or a guest physical address (GPA) and must
33263 * point to a physically contiguous block of memory.
33265 uint64_t resp_addr;
33266 /* TF message type. */
33268 /* TF message subtype. */
33271 uint8_t unused0[4];
33272 /* TF request data. */
33276 /* hwrm_tf_output (size:5632b/704B) */
33277 struct hwrm_tf_output {
33278 /* The specific error status for the command. */
33279 uint16_t error_code;
33280 /* The HWRM command request type. */
33282 /* The sequence ID from the original command. */
33284 /* The length of the response data in number of bytes. */
33286 /* TF message type. */
33288 /* TF message subtype. */
33290 /* TF response code */
33291 uint32_t resp_code;
33292 /* TF response data. */
33293 uint32_t resp[170];
33295 uint8_t unused1[7];
33297 * This field is used in Output records to indicate that the
33298 * output is completely written to RAM. This field should be
33299 * read as '1' to indicate that the output has been
33300 * completely written. When writing a command completion or
33301 * response to an internal processor, the order of writes has
33302 * to be such that this field is written last.
33307 /***********************
33308 * hwrm_tf_version_get *
33309 ***********************/
33312 /* hwrm_tf_version_get_input (size:128b/16B) */
33313 struct hwrm_tf_version_get_input {
33314 /* The HWRM command request type. */
33317 * The completion ring to send the completion event on. This should
33318 * be the NQ ID returned from the `nq_alloc` HWRM command.
33320 uint16_t cmpl_ring;
33322 * The sequence ID is used by the driver for tracking multiple
33323 * commands. This ID is treated as opaque data by the firmware and
33324 * the value is returned in the `hwrm_resp_hdr` upon completion.
33328 * The target ID of the command:
33329 * * 0x0-0xFFF8 - The function ID
33330 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
33331 * * 0xFFFD - Reserved for user-space HWRM interface
33334 uint16_t target_id;
33336 * A physical address pointer pointing to a host buffer that the
33337 * command's response data will be written. This can be either a host
33338 * physical address (HPA) or a guest physical address (GPA) and must
33339 * point to a physically contiguous block of memory.
33341 uint64_t resp_addr;
33344 /* hwrm_tf_version_get_output (size:128b/16B) */
33345 struct hwrm_tf_version_get_output {
33346 /* The specific error status for the command. */
33347 uint16_t error_code;
33348 /* The HWRM command request type. */
33350 /* The sequence ID from the original command. */
33352 /* The length of the response data in number of bytes. */
33354 /* Version Major number. */
33356 /* Version Minor number. */
33358 /* Version Update number. */
33361 uint8_t unused0[4];
33363 * This field is used in Output records to indicate that the output
33364 * is completely written to RAM. This field should be read as '1'
33365 * to indicate that the output has been completely written.
33366 * When writing a command completion or response to an internal
33367 * processor, the order of writes has to be such that this field is
33373 /************************
33374 * hwrm_tf_session_open *
33375 ************************/
33378 /* hwrm_tf_session_open_input (size:640b/80B) */
33379 struct hwrm_tf_session_open_input {
33380 /* The HWRM command request type. */
33383 * The completion ring to send the completion event on. This should
33384 * be the NQ ID returned from the `nq_alloc` HWRM command.
33386 uint16_t cmpl_ring;
33388 * The sequence ID is used by the driver for tracking multiple
33389 * commands. This ID is treated as opaque data by the firmware and
33390 * the value is returned in the `hwrm_resp_hdr` upon completion.
33394 * The target ID of the command:
33395 * * 0x0-0xFFF8 - The function ID
33396 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
33397 * * 0xFFFD - Reserved for user-space HWRM interface
33400 uint16_t target_id;
33402 * A physical address pointer pointing to a host buffer that the
33403 * command's response data will be written. This can be either a host
33404 * physical address (HPA) or a guest physical address (GPA) and must
33405 * point to a physically contiguous block of memory.
33407 uint64_t resp_addr;
33408 /* Name of the session. */
33409 uint8_t session_name[64];
33412 /* hwrm_tf_session_open_output (size:128b/16B) */
33413 struct hwrm_tf_session_open_output {
33414 /* The specific error status for the command. */
33415 uint16_t error_code;
33416 /* The HWRM command request type. */
33418 /* The sequence ID from the original command. */
33420 /* The length of the response data in number of bytes. */
33423 * Unique session identifier for the session created by the
33424 * firmware. It includes PCIe bus info to distinguish the PF
33425 * and session info to identify the associated TruFlow
33428 uint32_t fw_session_id;
33430 uint8_t unused0[3];
33432 * This field is used in Output records to indicate that the output
33433 * is completely written to RAM. This field should be read as '1'
33434 * to indicate that the output has been completely written.
33435 * When writing a command completion or response to an internal
33436 * processor, the order of writes has to be such that this field is
33442 /**************************
33443 * hwrm_tf_session_attach *
33444 **************************/
33447 /* hwrm_tf_session_attach_input (size:704b/88B) */
33448 struct hwrm_tf_session_attach_input {
33449 /* The HWRM command request type. */
33452 * The completion ring to send the completion event on. This should
33453 * be the NQ ID returned from the `nq_alloc` HWRM command.
33455 uint16_t cmpl_ring;
33457 * The sequence ID is used by the driver for tracking multiple
33458 * commands. This ID is treated as opaque data by the firmware and
33459 * the value is returned in the `hwrm_resp_hdr` upon completion.
33463 * The target ID of the command:
33464 * * 0x0-0xFFF8 - The function ID
33465 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
33466 * * 0xFFFD - Reserved for user-space HWRM interface
33469 uint16_t target_id;
33471 * A physical address pointer pointing to a host buffer that the
33472 * command's response data will be written. This can be either a host
33473 * physical address (HPA) or a guest physical address (GPA) and must
33474 * point to a physically contiguous block of memory.
33476 uint64_t resp_addr;
33478 * Unique session identifier for the session that the attach
33479 * request want to attach to. This value originates from the
33480 * shared session memory that the attach request opened by
33481 * way of the 'attach name' that was passed in to the core
33483 * The fw_session_id of the attach session includes PCIe bus
33484 * info to distinguish the PF and session info to identify
33485 * the associated TruFlow session.
33487 uint32_t attach_fw_session_id;
33490 /* Name of the session it self. */
33491 uint8_t session_name[64];
33494 /* hwrm_tf_session_attach_output (size:128b/16B) */
33495 struct hwrm_tf_session_attach_output {
33496 /* The specific error status for the command. */
33497 uint16_t error_code;
33498 /* The HWRM command request type. */
33500 /* The sequence ID from the original command. */
33502 /* The length of the response data in number of bytes. */
33505 * Unique session identifier for the session created by the
33506 * firmware. It includes PCIe bus info to distinguish the PF
33507 * and session info to identify the associated TruFlow
33508 * session. This fw_session_id is unique to the attach
33511 uint32_t fw_session_id;
33513 uint8_t unused0[3];
33515 * This field is used in Output records to indicate that the output
33516 * is completely written to RAM. This field should be read as '1'
33517 * to indicate that the output has been completely written.
33518 * When writing a command completion or response to an internal
33519 * processor, the order of writes has to be such that this field is
33525 /*************************
33526 * hwrm_tf_session_close *
33527 *************************/
33530 /* hwrm_tf_session_close_input (size:192b/24B) */
33531 struct hwrm_tf_session_close_input {
33532 /* The HWRM command request type. */
33535 * The completion ring to send the completion event on. This should
33536 * be the NQ ID returned from the `nq_alloc` HWRM command.
33538 uint16_t cmpl_ring;
33540 * The sequence ID is used by the driver for tracking multiple
33541 * commands. This ID is treated as opaque data by the firmware and
33542 * the value is returned in the `hwrm_resp_hdr` upon completion.
33546 * The target ID of the command:
33547 * * 0x0-0xFFF8 - The function ID
33548 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
33549 * * 0xFFFD - Reserved for user-space HWRM interface
33552 uint16_t target_id;
33554 * A physical address pointer pointing to a host buffer that the
33555 * command's response data will be written. This can be either a host
33556 * physical address (HPA) or a guest physical address (GPA) and must
33557 * point to a physically contiguous block of memory.
33559 uint64_t resp_addr;
33560 /* Firmware session id returned when HWRM_TF_SESSION_OPEN is sent. */
33561 uint32_t fw_session_id;
33563 uint8_t unused0[4];
33566 /* hwrm_tf_session_close_output (size:128b/16B) */
33567 struct hwrm_tf_session_close_output {
33568 /* The specific error status for the command. */
33569 uint16_t error_code;
33570 /* The HWRM command request type. */
33572 /* The sequence ID from the original command. */
33574 /* The length of the response data in number of bytes. */
33577 uint8_t unused0[7];
33579 * This field is used in Output records to indicate that the output
33580 * is completely written to RAM. This field should be read as '1'
33581 * to indicate that the output has been completely written.
33582 * When writing a command completion or response to an internal
33583 * processor, the order of writes has to be such that this field
33589 /************************
33590 * hwrm_tf_session_qcfg *
33591 ************************/
33594 /* hwrm_tf_session_qcfg_input (size:192b/24B) */
33595 struct hwrm_tf_session_qcfg_input {
33596 /* The HWRM command request type. */
33599 * The completion ring to send the completion event on. This should
33600 * be the NQ ID returned from the `nq_alloc` HWRM command.
33602 uint16_t cmpl_ring;
33604 * The sequence ID is used by the driver for tracking multiple
33605 * commands. This ID is treated as opaque data by the firmware and
33606 * the value is returned in the `hwrm_resp_hdr` upon completion.
33610 * The target ID of the command:
33611 * * 0x0-0xFFF8 - The function ID
33612 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
33613 * * 0xFFFD - Reserved for user-space HWRM interface
33616 uint16_t target_id;
33618 * A physical address pointer pointing to a host buffer that the
33619 * command's response data will be written. This can be either a host
33620 * physical address (HPA) or a guest physical address (GPA) and must
33621 * point to a physically contiguous block of memory.
33623 uint64_t resp_addr;
33624 /* Firmware session id returned when HWRM_TF_SESSION_OPEN is sent. */
33625 uint32_t fw_session_id;
33627 uint8_t unused0[4];
33630 /* hwrm_tf_session_qcfg_output (size:128b/16B) */
33631 struct hwrm_tf_session_qcfg_output {
33632 /* The specific error status for the command. */
33633 uint16_t error_code;
33634 /* The HWRM command request type. */
33636 /* The sequence ID from the original command. */
33638 /* The length of the response data in number of bytes. */
33640 /* RX action control settings flags. */
33641 uint8_t rx_act_flags;
33643 * A value of 1 in this field indicates that Global Flow ID
33644 * reporting into cfa_code and cfa_metadata is enabled.
33646 #define HWRM_TF_SESSION_QCFG_OUTPUT_RX_ACT_FLAGS_ABCR_GFID_EN \
33649 * A value of 1 in this field indicates that both inner and outer
33650 * are stripped and inner tag is passed.
33653 #define HWRM_TF_SESSION_QCFG_OUTPUT_RX_ACT_FLAGS_ABCR_VTAG_DLT_BOTH \
33656 * A value of 1 in this field indicates that the re-use of
33657 * existing tunnel L2 header SMAC is enabled for
33658 * Non-tunnel L2, L2-L3 and IP-IP tunnel.
33660 #define HWRM_TF_SESSION_QCFG_OUTPUT_RX_ACT_FLAGS_TECT_SMAC_OVR_RUTNSL2 \
33662 /* TX Action control settings flags. */
33663 uint8_t tx_act_flags;
33665 #define HWRM_TF_SESSION_QCFG_OUTPUT_TX_ACT_FLAGS_ABCR_VEB_EN \
33668 * When set to 1 any GRE tunnels will include the
33669 * optional Key field.
33671 #define HWRM_TF_SESSION_QCFG_OUTPUT_TX_ACT_FLAGS_TECT_GRE_SET_K \
33674 * When set to 1, for GRE tunnels, the IPV6 Traffic Class (TC)
33675 * field of the outer header is inherited from the inner header
33676 * (if present) or the fixed value as taken from the encap
33679 #define HWRM_TF_SESSION_QCFG_OUTPUT_TX_ACT_FLAGS_TECT_IPV6_TC_IH \
33682 * When set to 1, for GRE tunnels, the IPV4 Type Of Service (TOS)
33683 * field of the outer header is inherited from the inner header
33684 * (if present) or the fixed value as taken from the encap record.
33686 #define HWRM_TF_SESSION_QCFG_OUTPUT_TX_ACT_FLAGS_TECT_IPV4_TOS_IH \
33689 uint8_t unused0[5];
33691 * This field is used in Output records to indicate that the output
33692 * is completely written to RAM. This field should be read as '1'
33693 * to indicate that the output has been completely written.
33694 * When writing a command completion or response to an internal
33695 * processor, the order of writes has to be such that this field
33701 /******************************
33702 * hwrm_tf_session_resc_qcaps *
33703 ******************************/
33706 /* hwrm_tf_session_resc_qcaps_input (size:256b/32B) */
33707 struct hwrm_tf_session_resc_qcaps_input {
33708 /* The HWRM command request type. */
33711 * The completion ring to send the completion event on. This should
33712 * be the NQ ID returned from the `nq_alloc` HWRM command.
33714 uint16_t cmpl_ring;
33716 * The sequence ID is used by the driver for tracking multiple
33717 * commands. This ID is treated as opaque data by the firmware and
33718 * the value is returned in the `hwrm_resp_hdr` upon completion.
33722 * The target ID of the command:
33723 * * 0x0-0xFFF8 - The function ID
33724 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
33725 * * 0xFFFD - Reserved for user-space HWRM interface
33728 uint16_t target_id;
33730 * A physical address pointer pointing to a host buffer that the
33731 * command's response data will be written. This can be either a host
33732 * physical address (HPA) or a guest physical address (GPA) and must
33733 * point to a physically contiguous block of memory.
33735 uint64_t resp_addr;
33736 /* Firmware session id returned when HWRM_TF_SESSION_OPEN is sent. */
33737 uint32_t fw_session_id;
33738 /* Control flags. */
33740 /* Indicates the flow direction. */
33741 #define HWRM_TF_SESSION_RESC_QCAPS_INPUT_FLAGS_DIR UINT32_C(0x1)
33742 /* If this bit set to 0, then it indicates rx flow. */
33743 #define HWRM_TF_SESSION_RESC_QCAPS_INPUT_FLAGS_DIR_RX UINT32_C(0x0)
33744 /* If this bit is set to 1, then it indicates that tx flow. */
33745 #define HWRM_TF_SESSION_RESC_QCAPS_INPUT_FLAGS_DIR_TX UINT32_C(0x1)
33746 #define HWRM_TF_SESSION_RESC_QCAPS_INPUT_FLAGS_DIR_LAST \
33747 HWRM_TF_SESSION_RESC_QCAPS_INPUT_FLAGS_DIR_TX
33749 * Defines the size, in bytes, of the provided qcaps_addr
33750 * buffer. The size should be set to the Resource Manager
33751 * provided max qcaps value that is device specific. This is
33752 * the max size possible.
33756 * This is the DMA address for the qcaps output data
33757 * array. Array is of tf_rm_cap type and is device specific.
33759 uint64_t qcaps_addr;
33762 /* hwrm_tf_session_resc_qcaps_output (size:192b/24B) */
33763 struct hwrm_tf_session_resc_qcaps_output {
33764 /* The specific error status for the command. */
33765 uint16_t error_code;
33766 /* The HWRM command request type. */
33768 /* The sequence ID from the original command. */
33770 /* The length of the response data in number of bytes. */
33772 /* Control flags. */
33774 /* Session reservation strategy. */
33775 #define HWRM_TF_SESSION_RESC_QCAPS_OUTPUT_FLAGS_SESS_RES_STRATEGY_MASK \
33777 #define HWRM_TF_SESSION_RESC_QCAPS_OUTPUT_FLAGS_SESS_RES_STRATEGY_SFT \
33779 /* Static partitioning. */
33780 #define HWRM_TF_SESSION_RESC_QCAPS_OUTPUT_FLAGS_SESS_RES_STRATEGY_STATIC \
33783 #define HWRM_TF_SESSION_RESC_QCAPS_OUTPUT_FLAGS_SESS_RES_STRATEGY_1 \
33786 #define HWRM_TF_SESSION_RESC_QCAPS_OUTPUT_FLAGS_SESS_RES_STRATEGY_2 \
33789 #define HWRM_TF_SESSION_RESC_QCAPS_OUTPUT_FLAGS_SESS_RES_STRATEGY_3 \
33791 #define HWRM_TF_SESSION_RESC_QCAPS_OUTPUT_FLAGS_SESS_RES_STRATEGY_LAST \
33792 HWRM_TF_SESSION_RESC_QCAPS_OUTPUT_FLAGS_SESS_RES_STRATEGY_3
33794 * Size of the returned tf_rm_cap data array. The value
33795 * cannot exceed the size defined by the input msg. The data
33796 * array is returned using the qcaps_addr specified DMA
33797 * address also provided by the input msg.
33803 uint8_t unused1[7];
33805 * This field is used in Output records to indicate that the output
33806 * is completely written to RAM. This field should be read as '1'
33807 * to indicate that the output has been completely written.
33808 * When writing a command completion or response to an internal
33809 * processor, the order of writes has to be such that this field is
33815 /******************************
33816 * hwrm_tf_session_resc_alloc *
33817 ******************************/
33820 /* hwrm_tf_session_resc_alloc_input (size:256b/32B) */
33821 struct hwrm_tf_session_resc_alloc_input {
33822 /* The HWRM command request type. */
33825 * The completion ring to send the completion event on. This should
33826 * be the NQ ID returned from the `nq_alloc` HWRM command.
33828 uint16_t cmpl_ring;
33830 * The sequence ID is used by the driver for tracking multiple
33831 * commands. This ID is treated as opaque data by the firmware and
33832 * the value is returned in the `hwrm_resp_hdr` upon completion.
33836 * The target ID of the command:
33837 * * 0x0-0xFFF8 - The function ID
33838 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
33839 * * 0xFFFD - Reserved for user-space HWRM interface
33842 uint16_t target_id;
33844 * A physical address pointer pointing to a host buffer that the
33845 * command's response data will be written. This can be either a host
33846 * physical address (HPA) or a guest physical address (GPA) and must
33847 * point to a physically contiguous block of memory.
33849 uint64_t resp_addr;
33850 /* Firmware session id returned when HWRM_TF_SESSION_OPEN is sent. */
33851 uint32_t fw_session_id;
33852 /* Control flags. */
33854 /* Indicates the flow direction. */
33855 #define HWRM_TF_SESSION_RESC_ALLOC_INPUT_FLAGS_DIR UINT32_C(0x1)
33856 /* If this bit set to 0, then it indicates rx flow. */
33857 #define HWRM_TF_SESSION_RESC_ALLOC_INPUT_FLAGS_DIR_RX UINT32_C(0x0)
33858 /* If this bit is set to 1, then it indicates that tx flow. */
33859 #define HWRM_TF_SESSION_RESC_ALLOC_INPUT_FLAGS_DIR_TX UINT32_C(0x1)
33860 #define HWRM_TF_SESSION_RESC_ALLOC_INPUT_FLAGS_DIR_LAST \
33861 HWRM_TF_SESSION_RESC_ALLOC_INPUT_FLAGS_DIR_TX
33863 * Defines the size, in bytes, of the provided num_addr
33868 * This is the DMA address for the num input data array
33869 * buffer. Array is of tf_rm_num type. Size of the buffer is
33870 * provided by the 'size' field in this message.
33875 /* hwrm_tf_session_resc_alloc_output (size:128b/16B) */
33876 struct hwrm_tf_session_resc_alloc_output {
33877 /* The specific error status for the command. */
33878 uint16_t error_code;
33879 /* The HWRM command request type. */
33881 /* The sequence ID from the original command. */
33883 /* The length of the response data in number of bytes. */
33886 uint8_t unused0[7];
33888 * This field is used in Output records to indicate that the output
33889 * is completely written to RAM. This field should be read as '1'
33890 * to indicate that the output has been completely written.
33891 * When writing a command completion or response to an internal
33892 * processor, the order of writes has to be such that this field is
33898 /*****************************
33899 * hwrm_tf_session_resc_free *
33900 *****************************/
33903 /* hwrm_tf_session_resc_free_input (size:256b/32B) */
33904 struct hwrm_tf_session_resc_free_input {
33905 /* The HWRM command request type. */
33908 * The completion ring to send the completion event on. This should
33909 * be the NQ ID returned from the `nq_alloc` HWRM command.
33911 uint16_t cmpl_ring;
33913 * The sequence ID is used by the driver for tracking multiple
33914 * commands. This ID is treated as opaque data by the firmware and
33915 * the value is returned in the `hwrm_resp_hdr` upon completion.
33919 * The target ID of the command:
33920 * * 0x0-0xFFF8 - The function ID
33921 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
33922 * * 0xFFFD - Reserved for user-space HWRM interface
33925 uint16_t target_id;
33927 * A physical address pointer pointing to a host buffer that the
33928 * command's response data will be written. This can be either a host
33929 * physical address (HPA) or a guest physical address (GPA) and must
33930 * point to a physically contiguous block of memory.
33932 uint64_t resp_addr;
33933 /* Firmware session id returned when HWRM_TF_SESSION_OPEN is sent. */
33934 uint32_t fw_session_id;
33935 /* Control flags. */
33937 /* Indicates the flow direction. */
33938 #define HWRM_TF_SESSION_RESC_FREE_INPUT_FLAGS_DIR UINT32_C(0x1)
33939 /* If this bit set to 0, then it indicates rx flow. */
33940 #define HWRM_TF_SESSION_RESC_FREE_INPUT_FLAGS_DIR_RX UINT32_C(0x0)
33941 /* If this bit is set to 1, then it indicates that tx flow. */
33942 #define HWRM_TF_SESSION_RESC_FREE_INPUT_FLAGS_DIR_TX UINT32_C(0x1)
33943 #define HWRM_TF_SESSION_RESC_FREE_INPUT_FLAGS_DIR_LAST \
33944 HWRM_TF_SESSION_RESC_FREE_INPUT_FLAGS_DIR_TX
33946 * Defines the size, in bytes, of the provided free_addr
33951 * This is the DMA address for the free input data array
33952 * buffer. Array of tf_rm_res type. Size of the buffer is
33953 * provided by the 'size field of this message.
33955 uint64_t free_addr;
33958 /* hwrm_tf_session_resc_free_output (size:128b/16B) */
33959 struct hwrm_tf_session_resc_free_output {
33960 /* The specific error status for the command. */
33961 uint16_t error_code;
33962 /* The HWRM command request type. */
33964 /* The sequence ID from the original command. */
33966 /* The length of the response data in number of bytes. */
33969 uint8_t unused0[7];
33971 * This field is used in Output records to indicate that the output
33972 * is completely written to RAM. This field should be read as '1'
33973 * to indicate that the output has been completely written.
33974 * When writing a command completion or response to an internal
33975 * processor, the order of writes has to be such that this field is
33981 /******************************
33982 * hwrm_tf_session_resc_flush *
33983 ******************************/
33986 /* hwrm_tf_session_resc_flush_input (size:256b/32B) */
33987 struct hwrm_tf_session_resc_flush_input {
33988 /* The HWRM command request type. */
33991 * The completion ring to send the completion event on. This should
33992 * be the NQ ID returned from the `nq_alloc` HWRM command.
33994 uint16_t cmpl_ring;
33996 * The sequence ID is used by the driver for tracking multiple
33997 * commands. This ID is treated as opaque data by the firmware and
33998 * the value is returned in the `hwrm_resp_hdr` upon completion.
34002 * The target ID of the command:
34003 * * 0x0-0xFFF8 - The function ID
34004 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
34005 * * 0xFFFD - Reserved for user-space HWRM interface
34008 uint16_t target_id;
34010 * A physical address pointer pointing to a host buffer that the
34011 * command's response data will be written. This can be either a host
34012 * physical address (HPA) or a guest physical address (GPA) and must
34013 * point to a physically contiguous block of memory.
34015 uint64_t resp_addr;
34016 /* Firmware session id returned when HWRM_TF_SESSION_OPEN is sent. */
34017 uint32_t fw_session_id;
34018 /* Control flags. */
34020 /* Indicates the flow direction. */
34021 #define HWRM_TF_SESSION_RESC_FLUSH_INPUT_FLAGS_DIR UINT32_C(0x1)
34022 /* If this bit set to 0, then it indicates rx flow. */
34023 #define HWRM_TF_SESSION_RESC_FLUSH_INPUT_FLAGS_DIR_RX UINT32_C(0x0)
34024 /* If this bit is set to 1, then it indicates that tx flow. */
34025 #define HWRM_TF_SESSION_RESC_FLUSH_INPUT_FLAGS_DIR_TX UINT32_C(0x1)
34026 #define HWRM_TF_SESSION_RESC_FLUSH_INPUT_FLAGS_DIR_LAST \
34027 HWRM_TF_SESSION_RESC_FLUSH_INPUT_FLAGS_DIR_TX
34029 * Defines the size, in bytes, of the provided flush_addr
34034 * This is the DMA address for the flush input data array
34035 * buffer. Array of tf_rm_res type. Size of the buffer is
34036 * provided by the 'size' field in this message.
34038 uint64_t flush_addr;
34041 /* hwrm_tf_session_resc_flush_output (size:128b/16B) */
34042 struct hwrm_tf_session_resc_flush_output {
34043 /* The specific error status for the command. */
34044 uint16_t error_code;
34045 /* The HWRM command request type. */
34047 /* The sequence ID from the original command. */
34049 /* The length of the response data in number of bytes. */
34052 uint8_t unused0[7];
34054 * This field is used in Output records to indicate that the output
34055 * is completely written to RAM. This field should be read as '1'
34056 * to indicate that the output has been completely written.
34057 * When writing a command completion or response to an internal
34058 * processor, the order of writes has to be such that this field is
34064 /* TruFlow RM capability of a resource. */
34065 /* tf_rm_cap (size:64b/8B) */
34068 * Type of the resource, defined globally in the
34069 * hwrm_tf_resc_type enum.
34072 /* Minimum value. */
34074 /* Maximum value. */
34078 /* TruFlow RM number of a resource. */
34079 /* tf_rm_num (size:64b/8B) */
34082 * Type of the resource, defined globally in the
34083 * hwrm_tf_resc_type enum.
34086 /* Number of resources. */
34090 /* TruFlow RM reservation information. */
34091 /* tf_rm_res (size:64b/8B) */
34094 * Type of the resource, defined globally in the
34095 * hwrm_tf_resc_type enum.
34098 /* Start offset. */
34100 /* Number of resources. */
34104 /************************
34105 * hwrm_tf_tbl_type_get *
34106 ************************/
34109 /* hwrm_tf_tbl_type_get_input (size:256b/32B) */
34110 struct hwrm_tf_tbl_type_get_input {
34111 /* The HWRM command request type. */
34114 * The completion ring to send the completion event on. This should
34115 * be the NQ ID returned from the `nq_alloc` HWRM command.
34117 uint16_t cmpl_ring;
34119 * The sequence ID is used by the driver for tracking multiple
34120 * commands. This ID is treated as opaque data by the firmware and
34121 * the value is returned in the `hwrm_resp_hdr` upon completion.
34125 * The target ID of the command:
34126 * * 0x0-0xFFF8 - The function ID
34127 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
34128 * * 0xFFFD - Reserved for user-space HWRM interface
34131 uint16_t target_id;
34133 * A physical address pointer pointing to a host buffer that the
34134 * command's response data will be written. This can be either a host
34135 * physical address (HPA) or a guest physical address (GPA) and must
34136 * point to a physically contiguous block of memory.
34138 uint64_t resp_addr;
34139 /* Firmware session id returned when HWRM_TF_SESSION_OPEN is sent. */
34140 uint32_t fw_session_id;
34141 /* Control flags. */
34143 /* Indicates the flow direction. */
34144 #define HWRM_TF_TBL_TYPE_GET_INPUT_FLAGS_DIR UINT32_C(0x1)
34145 /* If this bit set to 0, then it indicates rx flow. */
34146 #define HWRM_TF_TBL_TYPE_GET_INPUT_FLAGS_DIR_RX UINT32_C(0x0)
34147 /* If this bit is set to 1, then it indicates that tx flow. */
34148 #define HWRM_TF_TBL_TYPE_GET_INPUT_FLAGS_DIR_TX UINT32_C(0x1)
34149 #define HWRM_TF_TBL_TYPE_GET_INPUT_FLAGS_DIR_LAST \
34150 HWRM_TF_TBL_TYPE_GET_INPUT_FLAGS_DIR_TX
34152 uint8_t unused0[2];
34154 * Type of the resource, defined globally in the
34155 * hwrm_tf_resc_type enum.
34158 /* Index of the type to retrieve. */
34162 /* hwrm_tf_tbl_type_get_output (size:1216b/152B) */
34163 struct hwrm_tf_tbl_type_get_output {
34164 /* The specific error status for the command. */
34165 uint16_t error_code;
34166 /* The HWRM command request type. */
34168 /* The sequence ID from the original command. */
34170 /* The length of the response data in number of bytes. */
34172 /* Response code. */
34173 uint32_t resp_code;
34174 /* Response size. */
34178 /* Response data. */
34181 uint8_t unused1[7];
34183 * This field is used in Output records to indicate that the output
34184 * is completely written to RAM. This field should be read as '1'
34185 * to indicate that the output has been completely written.
34186 * When writing a command completion or response to an internal
34187 * processor, the order of writes has to be such that this field
34193 /************************
34194 * hwrm_tf_tbl_type_set *
34195 ************************/
34198 /* hwrm_tf_tbl_type_set_input (size:1024b/128B) */
34199 struct hwrm_tf_tbl_type_set_input {
34200 /* The HWRM command request type. */
34203 * The completion ring to send the completion event on. This should
34204 * be the NQ ID returned from the `nq_alloc` HWRM command.
34206 uint16_t cmpl_ring;
34208 * The sequence ID is used by the driver for tracking multiple
34209 * commands. This ID is treated as opaque data by the firmware and
34210 * the value is returned in the `hwrm_resp_hdr` upon completion.
34214 * The target ID of the command:
34215 * * 0x0-0xFFF8 - The function ID
34216 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
34217 * * 0xFFFD - Reserved for user-space HWRM interface
34220 uint16_t target_id;
34222 * A physical address pointer pointing to a host buffer that the
34223 * command's response data will be written. This can be either a host
34224 * physical address (HPA) or a guest physical address (GPA) and must
34225 * point to a physically contiguous block of memory.
34227 uint64_t resp_addr;
34228 /* Firmware session id returned when HWRM_TF_SESSION_OPEN is sent. */
34229 uint32_t fw_session_id;
34230 /* Control flags. */
34232 /* Indicates the flow direction. */
34233 #define HWRM_TF_TBL_TYPE_SET_INPUT_FLAGS_DIR UINT32_C(0x1)
34234 /* If this bit set to 0, then it indicates rx flow. */
34235 #define HWRM_TF_TBL_TYPE_SET_INPUT_FLAGS_DIR_RX UINT32_C(0x0)
34236 /* If this bit is set to 1, then it indicates that tx flow. */
34237 #define HWRM_TF_TBL_TYPE_SET_INPUT_FLAGS_DIR_TX UINT32_C(0x1)
34238 #define HWRM_TF_TBL_TYPE_SET_INPUT_FLAGS_DIR_LAST \
34239 HWRM_TF_TBL_TYPE_SET_INPUT_FLAGS_DIR_TX
34241 uint8_t unused0[2];
34243 * Type of the resource, defined globally in the
34244 * hwrm_tf_resc_type enum.
34247 /* Index of the type to retrieve. */
34249 /* Size of the data to set. */
34252 uint8_t unused1[6];
34253 /* Data to be set. */
34257 /* hwrm_tf_tbl_type_set_output (size:128b/16B) */
34258 struct hwrm_tf_tbl_type_set_output {
34259 /* The specific error status for the command. */
34260 uint16_t error_code;
34261 /* The HWRM command request type. */
34263 /* The sequence ID from the original command. */
34265 /* The length of the response data in number of bytes. */
34268 uint8_t unused0[7];
34270 * This field is used in Output records to indicate that the output
34271 * is completely written to RAM. This field should be read as '1'
34272 * to indicate that the output has been completely written.
34273 * When writing a command completion or response to an internal
34274 * processor, the order of writes has to be such that this field
34280 /*************************
34281 * hwrm_tf_ctxt_mem_rgtr *
34282 *************************/
34285 /* hwrm_tf_ctxt_mem_rgtr_input (size:256b/32B) */
34286 struct hwrm_tf_ctxt_mem_rgtr_input {
34287 /* The HWRM command request type. */
34290 * The completion ring to send the completion event on. This should
34291 * be the NQ ID returned from the `nq_alloc` HWRM command.
34293 uint16_t cmpl_ring;
34295 * The sequence ID is used by the driver for tracking multiple
34296 * commands. This ID is treated as opaque data by the firmware and
34297 * the value is returned in the `hwrm_resp_hdr` upon completion.
34301 * The target ID of the command:
34302 * * 0x0-0xFFF8 - The function ID
34303 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
34304 * * 0xFFFD - Reserved for user-space HWRM interface
34307 uint16_t target_id;
34309 * A physical address pointer pointing to a host buffer that the
34310 * command's response data will be written. This can be either a host
34311 * physical address (HPA) or a guest physical address (GPA) and must
34312 * point to a physically contiguous block of memory.
34314 uint64_t resp_addr;
34315 /* Control flags. */
34317 /* Counter PBL indirect levels. */
34318 uint8_t page_level;
34319 /* PBL pointer is physical start address. */
34320 #define HWRM_TF_CTXT_MEM_RGTR_INPUT_PAGE_LEVEL_LVL_0 UINT32_C(0x0)
34321 /* PBL pointer points to PTE table. */
34322 #define HWRM_TF_CTXT_MEM_RGTR_INPUT_PAGE_LEVEL_LVL_1 UINT32_C(0x1)
34324 * PBL pointer points to PDE table with each entry pointing
34327 #define HWRM_TF_CTXT_MEM_RGTR_INPUT_PAGE_LEVEL_LVL_2 UINT32_C(0x2)
34328 #define HWRM_TF_CTXT_MEM_RGTR_INPUT_PAGE_LEVEL_LAST \
34329 HWRM_TF_CTXT_MEM_RGTR_INPUT_PAGE_LEVEL_LVL_2
34332 /* 4KB page size. */
34333 #define HWRM_TF_CTXT_MEM_RGTR_INPUT_PAGE_SIZE_4K UINT32_C(0x0)
34334 /* 8KB page size. */
34335 #define HWRM_TF_CTXT_MEM_RGTR_INPUT_PAGE_SIZE_8K UINT32_C(0x1)
34336 /* 64KB page size. */
34337 #define HWRM_TF_CTXT_MEM_RGTR_INPUT_PAGE_SIZE_64K UINT32_C(0x4)
34338 /* 256KB page size. */
34339 #define HWRM_TF_CTXT_MEM_RGTR_INPUT_PAGE_SIZE_256K UINT32_C(0x6)
34340 /* 1MB page size. */
34341 #define HWRM_TF_CTXT_MEM_RGTR_INPUT_PAGE_SIZE_1M UINT32_C(0x8)
34342 /* 2MB page size. */
34343 #define HWRM_TF_CTXT_MEM_RGTR_INPUT_PAGE_SIZE_2M UINT32_C(0x9)
34344 /* 4MB page size. */
34345 #define HWRM_TF_CTXT_MEM_RGTR_INPUT_PAGE_SIZE_4M UINT32_C(0xa)
34346 /* 1GB page size. */
34347 #define HWRM_TF_CTXT_MEM_RGTR_INPUT_PAGE_SIZE_1G UINT32_C(0x12)
34348 #define HWRM_TF_CTXT_MEM_RGTR_INPUT_PAGE_SIZE_LAST \
34349 HWRM_TF_CTXT_MEM_RGTR_INPUT_PAGE_SIZE_1G
34352 /* Pointer to the PBL, or PDL depending on number of levels */
34356 /* hwrm_tf_ctxt_mem_rgtr_output (size:128b/16B) */
34357 struct hwrm_tf_ctxt_mem_rgtr_output {
34358 /* The specific error status for the command. */
34359 uint16_t error_code;
34360 /* The HWRM command request type. */
34362 /* The sequence ID from the original command. */
34364 /* The length of the response data in number of bytes. */
34367 * Id/Handle to the recently register context memory. This
34368 * handle is passed to the TF session.
34372 uint8_t unused0[5];
34374 * This field is used in Output records to indicate that the
34375 * output is completely written to RAM. This field should be
34376 * read as '1' to indicate that the output has been
34377 * completely written. When writing a command completion or
34378 * response to an internal processor, the order of writes has
34379 * to be such that this field is written last.
34384 /***************************
34385 * hwrm_tf_ctxt_mem_unrgtr *
34386 ***************************/
34389 /* hwrm_tf_ctxt_mem_unrgtr_input (size:192b/24B) */
34390 struct hwrm_tf_ctxt_mem_unrgtr_input {
34391 /* The HWRM command request type. */
34394 * The completion ring to send the completion event on. This should
34395 * be the NQ ID returned from the `nq_alloc` HWRM command.
34397 uint16_t cmpl_ring;
34399 * The sequence ID is used by the driver for tracking multiple
34400 * commands. This ID is treated as opaque data by the firmware and
34401 * the value is returned in the `hwrm_resp_hdr` upon completion.
34405 * The target ID of the command:
34406 * * 0x0-0xFFF8 - The function ID
34407 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
34408 * * 0xFFFD - Reserved for user-space HWRM interface
34411 uint16_t target_id;
34413 * A physical address pointer pointing to a host buffer that the
34414 * command's response data will be written. This can be either a host
34415 * physical address (HPA) or a guest physical address (GPA) and must
34416 * point to a physically contiguous block of memory.
34418 uint64_t resp_addr;
34420 * Id/Handle to the recently register context memory. This
34421 * handle is passed to the TF session.
34425 uint8_t unused0[6];
34428 /* hwrm_tf_ctxt_mem_unrgtr_output (size:128b/16B) */
34429 struct hwrm_tf_ctxt_mem_unrgtr_output {
34430 /* The specific error status for the command. */
34431 uint16_t error_code;
34432 /* The HWRM command request type. */
34434 /* The sequence ID from the original command. */
34436 /* The length of the response data in number of bytes. */
34439 uint8_t unused0[7];
34441 * This field is used in Output records to indicate that the
34442 * output is completely written to RAM. This field should be
34443 * read as '1' to indicate that the output has been
34444 * completely written. When writing a command completion or
34445 * response to an internal processor, the order of writes has
34446 * to be such that this field is written last.
34451 /************************
34452 * hwrm_tf_ext_em_qcaps *
34453 ************************/
34456 /* hwrm_tf_ext_em_qcaps_input (size:192b/24B) */
34457 struct hwrm_tf_ext_em_qcaps_input {
34458 /* The HWRM command request type. */
34461 * The completion ring to send the completion event on. This should
34462 * be the NQ ID returned from the `nq_alloc` HWRM command.
34464 uint16_t cmpl_ring;
34466 * The sequence ID is used by the driver for tracking multiple
34467 * commands. This ID is treated as opaque data by the firmware and
34468 * the value is returned in the `hwrm_resp_hdr` upon completion.
34472 * The target ID of the command:
34473 * * 0x0-0xFFF8 - The function ID
34474 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
34475 * * 0xFFFD - Reserved for user-space HWRM interface
34478 uint16_t target_id;
34480 * A physical address pointer pointing to a host buffer that the
34481 * command's response data will be written. This can be either a host
34482 * physical address (HPA) or a guest physical address (GPA) and must
34483 * point to a physically contiguous block of memory.
34485 uint64_t resp_addr;
34486 /* Control flags. */
34488 /* Indicates the flow direction. */
34489 #define HWRM_TF_EXT_EM_QCAPS_INPUT_FLAGS_DIR \
34491 /* If this bit set to 0, then it indicates rx flow. */
34492 #define HWRM_TF_EXT_EM_QCAPS_INPUT_FLAGS_DIR_RX \
34494 /* If this bit is set to 1, then it indicates that tx flow. */
34495 #define HWRM_TF_EXT_EM_QCAPS_INPUT_FLAGS_DIR_TX \
34497 #define HWRM_TF_EXT_EM_QCAPS_INPUT_FLAGS_DIR_LAST \
34498 HWRM_TF_EXT_EM_QCAPS_INPUT_FLAGS_DIR_TX
34499 /* When set to 1, all offloaded flows will be sent to EXT EM. */
34500 #define HWRM_TF_EXT_EM_QCAPS_INPUT_FLAGS_PREFERRED_OFFLOAD \
34506 /* hwrm_tf_ext_em_qcaps_output (size:320b/40B) */
34507 struct hwrm_tf_ext_em_qcaps_output {
34508 /* The specific error status for the command. */
34509 uint16_t error_code;
34510 /* The HWRM command request type. */
34512 /* The sequence ID from the original command. */
34514 /* The length of the response data in number of bytes. */
34518 * When set to 1, indicates the the FW supports the Centralized
34519 * Memory Model. The concept designates one entity for the
34520 * memory allocation while all others ‘subscribe’ to it.
34522 #define HWRM_TF_EXT_EM_QCAPS_OUTPUT_FLAGS_CENTRALIZED_MEMORY_MODEL_SUPPORTED \
34525 * When set to 1, indicates the the FW supports the Detached
34526 * Centralized Memory Model. The memory is allocated and managed
34527 * as a separate entity. All PFs and VFs will be granted direct
34528 * or semi-direct access to the allocated memory while none of
34529 * which can interfere with the management of the memory.
34531 #define HWRM_TF_EXT_EM_QCAPS_OUTPUT_FLAGS_DETACHED_CENTRALIZED_MEMORY_MODEL_SUPPORTED \
34535 /* Support flags. */
34536 uint32_t supported;
34538 * If set to 1, then EXT EM KEY0 table is supported using
34540 * If set to 0, EXT EM KEY0 table is not supported.
34542 #define HWRM_TF_EXT_EM_QCAPS_OUTPUT_SUPPORTED_KEY0_TABLE \
34545 * If set to 1, then EXT EM KEY1 table is supported using
34547 * If set to 0, EXT EM KEY1 table is not supported.
34549 #define HWRM_TF_EXT_EM_QCAPS_OUTPUT_SUPPORTED_KEY1_TABLE \
34552 * If set to 1, then EXT EM External Record table is supported.
34553 * If set to 0, EXT EM External Record table is not
34554 * supported. (This table includes action record, EFC
34555 * pointers, encap pointers)
34557 #define HWRM_TF_EXT_EM_QCAPS_OUTPUT_SUPPORTED_EXTERNAL_RECORD_TABLE \
34560 * If set to 1, then EXT EM External Flow Counters table is
34562 * If set to 0, EXT EM External Flow Counters table is not
34565 #define HWRM_TF_EXT_EM_QCAPS_OUTPUT_SUPPORTED_EXTERNAL_FLOW_COUNTERS_TABLE \
34568 * If set to 1, then FID table used for implicit flow flush
34570 * If set to 0, then FID table used for implicit flow flush
34571 * is not supported.
34573 #define HWRM_TF_EXT_EM_QCAPS_OUTPUT_SUPPORTED_FID_TABLE \
34576 * The maximum number of entries supported by EXT EM. When
34577 * configuring the host memory the number of numbers of
34578 * entries that can supported are -
34579 * 32k, 64k 128k, 256k, 512k, 1M, 2M, 4M, 8M, 32M, 64M,
34581 * Any value that are not these values, the FW will round
34582 * down to the closest support number of entries.
34584 uint32_t max_entries_supported;
34586 * The entry size in bytes of each entry in the EXT EM
34587 * KEY0/KEY1 tables.
34589 uint16_t key_entry_size;
34591 * The entry size in bytes of each entry in the EXT EM RECORD
34594 uint16_t record_entry_size;
34595 /* The entry size in bytes of each entry in the EXT EM EFC tables. */
34596 uint16_t efc_entry_size;
34597 /* The FID size in bytes of each entry in the EXT EM FID tables. */
34598 uint16_t fid_entry_size;
34600 uint8_t unused1[7];
34602 * This field is used in Output records to indicate that the
34603 * output is completely written to RAM. This field should be
34604 * read as '1' to indicate that the output has been
34605 * completely written. When writing a command completion or
34606 * response to an internal processor, the order of writes has
34607 * to be such that this field is written last.
34612 /*********************
34613 * hwrm_tf_ext_em_op *
34614 *********************/
34617 /* hwrm_tf_ext_em_op_input (size:192b/24B) */
34618 struct hwrm_tf_ext_em_op_input {
34619 /* The HWRM command request type. */
34622 * The completion ring to send the completion event on. This should
34623 * be the NQ ID returned from the `nq_alloc` HWRM command.
34625 uint16_t cmpl_ring;
34627 * The sequence ID is used by the driver for tracking multiple
34628 * commands. This ID is treated as opaque data by the firmware and
34629 * the value is returned in the `hwrm_resp_hdr` upon completion.
34633 * The target ID of the command:
34634 * * 0x0-0xFFF8 - The function ID
34635 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
34636 * * 0xFFFD - Reserved for user-space HWRM interface
34639 uint16_t target_id;
34641 * A physical address pointer pointing to a host buffer that the
34642 * command's response data will be written. This can be either a host
34643 * physical address (HPA) or a guest physical address (GPA) and must
34644 * point to a physically contiguous block of memory.
34646 uint64_t resp_addr;
34647 /* Control flags. */
34649 /* Indicates the flow direction. */
34650 #define HWRM_TF_EXT_EM_OP_INPUT_FLAGS_DIR UINT32_C(0x1)
34651 /* If this bit set to 0, then it indicates rx flow. */
34652 #define HWRM_TF_EXT_EM_OP_INPUT_FLAGS_DIR_RX UINT32_C(0x0)
34653 /* If this bit is set to 1, then it indicates that tx flow. */
34654 #define HWRM_TF_EXT_EM_OP_INPUT_FLAGS_DIR_TX UINT32_C(0x1)
34655 #define HWRM_TF_EXT_EM_OP_INPUT_FLAGS_DIR_LAST \
34656 HWRM_TF_EXT_EM_OP_INPUT_FLAGS_DIR_TX
34659 /* The number of EXT EM key table entries to be configured. */
34661 /* This value is reserved and should not be used. */
34662 #define HWRM_TF_EXT_EM_OP_INPUT_OP_RESERVED UINT32_C(0x0)
34664 * To properly stop EXT EM and ensure there are no DMA's,
34665 * the caller must disable EXT EM for the given PF, using
34666 * this call. This will safely disable EXT EM and ensure
34667 * that all DMA'ed to the keys/records/efc have been
34670 #define HWRM_TF_EXT_EM_OP_INPUT_OP_EXT_EM_DISABLE UINT32_C(0x1)
34672 * Once the EXT EM host memory has been configured, EXT EM
34673 * options have been configured. Then the caller should
34674 * enable EXT EM for the given PF. Note once this call has
34675 * been made, then the EXT EM mechanism will be active and
34676 * DMA's will occur as packets are processed.
34678 #define HWRM_TF_EXT_EM_OP_INPUT_OP_EXT_EM_ENABLE UINT32_C(0x2)
34680 * Clear EXT EM settings for the given PF so that the
34681 * register values are reset back to their initial state.
34683 #define HWRM_TF_EXT_EM_OP_INPUT_OP_EXT_EM_CLEANUP UINT32_C(0x3)
34684 #define HWRM_TF_EXT_EM_OP_INPUT_OP_LAST \
34685 HWRM_TF_EXT_EM_OP_INPUT_OP_EXT_EM_CLEANUP
34690 /* hwrm_tf_ext_em_op_output (size:128b/16B) */
34691 struct hwrm_tf_ext_em_op_output {
34692 /* The specific error status for the command. */
34693 uint16_t error_code;
34694 /* The HWRM command request type. */
34696 /* The sequence ID from the original command. */
34698 /* The length of the response data in number of bytes. */
34701 uint8_t unused0[7];
34703 * This field is used in Output records to indicate that the
34704 * output is completely written to RAM. This field should be
34705 * read as '1' to indicate that the output has been
34706 * completely written. When writing a command completion or
34707 * response to an internal processor, the order of writes has
34708 * to be such that this field is written last.
34713 /**********************
34714 * hwrm_tf_ext_em_cfg *
34715 **********************/
34718 /* hwrm_tf_ext_em_cfg_input (size:384b/48B) */
34719 struct hwrm_tf_ext_em_cfg_input {
34720 /* The HWRM command request type. */
34723 * The completion ring to send the completion event on. This should
34724 * be the NQ ID returned from the `nq_alloc` HWRM command.
34726 uint16_t cmpl_ring;
34728 * The sequence ID is used by the driver for tracking multiple
34729 * commands. This ID is treated as opaque data by the firmware and
34730 * the value is returned in the `hwrm_resp_hdr` upon completion.
34734 * The target ID of the command:
34735 * * 0x0-0xFFF8 - The function ID
34736 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
34737 * * 0xFFFD - Reserved for user-space HWRM interface
34740 uint16_t target_id;
34742 * A physical address pointer pointing to a host buffer that the
34743 * command's response data will be written. This can be either a host
34744 * physical address (HPA) or a guest physical address (GPA) and must
34745 * point to a physically contiguous block of memory.
34747 uint64_t resp_addr;
34748 /* Control flags. */
34750 /* Indicates the flow direction. */
34751 #define HWRM_TF_EXT_EM_CFG_INPUT_FLAGS_DIR \
34753 /* If this bit set to 0, then it indicates rx flow. */
34754 #define HWRM_TF_EXT_EM_CFG_INPUT_FLAGS_DIR_RX \
34756 /* If this bit is set to 1, then it indicates that tx flow. */
34757 #define HWRM_TF_EXT_EM_CFG_INPUT_FLAGS_DIR_TX \
34759 #define HWRM_TF_EXT_EM_CFG_INPUT_FLAGS_DIR_LAST \
34760 HWRM_TF_EXT_EM_CFG_INPUT_FLAGS_DIR_TX
34761 /* When set to 1, all offloaded flows will be sent to EXT EM. */
34762 #define HWRM_TF_EXT_EM_CFG_INPUT_FLAGS_PREFERRED_OFFLOAD \
34764 /* When set to 1, secondary, 0 means primary. */
34765 #define HWRM_TF_EXT_EM_CFG_INPUT_FLAGS_SECONDARY_PF \
34768 * Group_id which used by Firmware to identify memory pools belonging
34769 * to certain group.
34773 * Dynamically reconfigure EEM pending cache every 1/10th of second.
34774 * If set to 0 it will disable the EEM HW flush of the pending cache.
34776 uint8_t flush_interval;
34780 * Configured EXT EM with the given number of entries. All
34781 * the EXT EM tables KEY0, KEY1, RECORD, EFC all have the
34782 * same number of entries and all tables will be configured
34783 * using this value. Current minimum value is 32k. Current
34784 * maximum value is 128M.
34786 uint32_t num_entries;
34789 /* Configured EXT EM with the given context if for KEY0 table. */
34790 uint16_t key0_ctx_id;
34791 /* Configured EXT EM with the given context if for KEY1 table. */
34792 uint16_t key1_ctx_id;
34793 /* Configured EXT EM with the given context if for RECORD table. */
34794 uint16_t record_ctx_id;
34795 /* Configured EXT EM with the given context if for EFC table. */
34796 uint16_t efc_ctx_id;
34797 /* Configured EXT EM with the given context if for EFC table. */
34798 uint16_t fid_ctx_id;
34805 /* hwrm_tf_ext_em_cfg_output (size:128b/16B) */
34806 struct hwrm_tf_ext_em_cfg_output {
34807 /* The specific error status for the command. */
34808 uint16_t error_code;
34809 /* The HWRM command request type. */
34811 /* The sequence ID from the original command. */
34813 /* The length of the response data in number of bytes. */
34816 uint8_t unused0[7];
34818 * This field is used in Output records to indicate that the
34819 * output is completely written to RAM. This field should be
34820 * read as '1' to indicate that the output has been
34821 * completely written. When writing a command completion or
34822 * response to an internal processor, the order of writes has
34823 * to be such that this field is written last.
34828 /***********************
34829 * hwrm_tf_ext_em_qcfg *
34830 ***********************/
34833 /* hwrm_tf_ext_em_qcfg_input (size:192b/24B) */
34834 struct hwrm_tf_ext_em_qcfg_input {
34835 /* The HWRM command request type. */
34838 * The completion ring to send the completion event on. This should
34839 * be the NQ ID returned from the `nq_alloc` HWRM command.
34841 uint16_t cmpl_ring;
34843 * The sequence ID is used by the driver for tracking multiple
34844 * commands. This ID is treated as opaque data by the firmware and
34845 * the value is returned in the `hwrm_resp_hdr` upon completion.
34849 * The target ID of the command:
34850 * * 0x0-0xFFF8 - The function ID
34851 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
34852 * * 0xFFFD - Reserved for user-space HWRM interface
34855 uint16_t target_id;
34857 * A physical address pointer pointing to a host buffer that the
34858 * command's response data will be written. This can be either a host
34859 * physical address (HPA) or a guest physical address (GPA) and must
34860 * point to a physically contiguous block of memory.
34862 uint64_t resp_addr;
34863 /* Control flags. */
34865 /* Indicates the flow direction. */
34866 #define HWRM_TF_EXT_EM_QCFG_INPUT_FLAGS_DIR UINT32_C(0x1)
34867 /* If this bit set to 0, then it indicates rx flow. */
34868 #define HWRM_TF_EXT_EM_QCFG_INPUT_FLAGS_DIR_RX UINT32_C(0x0)
34869 /* If this bit is set to 1, then it indicates that tx flow. */
34870 #define HWRM_TF_EXT_EM_QCFG_INPUT_FLAGS_DIR_TX UINT32_C(0x1)
34871 #define HWRM_TF_EXT_EM_QCFG_INPUT_FLAGS_DIR_LAST \
34872 HWRM_TF_EXT_EM_QCFG_INPUT_FLAGS_DIR_TX
34877 /* hwrm_tf_ext_em_qcfg_output (size:256b/32B) */
34878 struct hwrm_tf_ext_em_qcfg_output {
34879 /* The specific error status for the command. */
34880 uint16_t error_code;
34881 /* The HWRM command request type. */
34883 /* The sequence ID from the original command. */
34885 /* The length of the response data in number of bytes. */
34887 /* Control flags. */
34889 /* Indicates the flow direction. */
34890 #define HWRM_TF_EXT_EM_QCFG_OUTPUT_FLAGS_DIR \
34892 /* If this bit set to 0, then it indicates rx flow. */
34893 #define HWRM_TF_EXT_EM_QCFG_OUTPUT_FLAGS_DIR_RX \
34895 /* If this bit is set to 1, then it indicates that tx flow. */
34896 #define HWRM_TF_EXT_EM_QCFG_OUTPUT_FLAGS_DIR_TX \
34898 #define HWRM_TF_EXT_EM_QCFG_OUTPUT_FLAGS_DIR_LAST \
34899 HWRM_TF_EXT_EM_QCFG_OUTPUT_FLAGS_DIR_TX
34900 /* When set to 1, all offloaded flows will be sent to EXT EM. */
34901 #define HWRM_TF_EXT_EM_QCFG_OUTPUT_FLAGS_PREFERRED_OFFLOAD \
34903 /* The number of entries the FW has configured for EXT EM. */
34904 uint32_t num_entries;
34905 /* Configured EXT EM with the given context if for KEY0 table. */
34906 uint16_t key0_ctx_id;
34907 /* Configured EXT EM with the given context if for KEY1 table. */
34908 uint16_t key1_ctx_id;
34909 /* Configured EXT EM with the given context if for RECORD table. */
34910 uint16_t record_ctx_id;
34911 /* Configured EXT EM with the given context if for EFC table. */
34912 uint16_t efc_ctx_id;
34913 /* Configured EXT EM with the given context if for EFC table. */
34914 uint16_t fid_ctx_id;
34916 uint8_t unused0[5];
34918 * This field is used in Output records to indicate that the
34919 * output is completely written to RAM. This field should be
34920 * read as '1' to indicate that the output has been
34921 * completely written. When writing a command completion or
34922 * response to an internal processor, the order of writes has
34923 * to be such that this field is written last.
34928 /********************
34929 * hwrm_tf_tcam_set *
34930 ********************/
34933 /* hwrm_tf_tcam_set_input (size:1024b/128B) */
34934 struct hwrm_tf_tcam_set_input {
34935 /* The HWRM command request type. */
34938 * The completion ring to send the completion event on. This should
34939 * be the NQ ID returned from the `nq_alloc` HWRM command.
34941 uint16_t cmpl_ring;
34943 * The sequence ID is used by the driver for tracking multiple
34944 * commands. This ID is treated as opaque data by the firmware and
34945 * the value is returned in the `hwrm_resp_hdr` upon completion.
34949 * The target ID of the command:
34950 * * 0x0-0xFFF8 - The function ID
34951 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
34952 * * 0xFFFD - Reserved for user-space HWRM interface
34955 uint16_t target_id;
34957 * A physical address pointer pointing to a host buffer that the
34958 * command's response data will be written. This can be either a host
34959 * physical address (HPA) or a guest physical address (GPA) and must
34960 * point to a physically contiguous block of memory.
34962 uint64_t resp_addr;
34963 /* Firmware session id returned when HWRM_TF_SESSION_OPEN is sent. */
34964 uint32_t fw_session_id;
34965 /* Control flags. */
34967 /* Indicates the flow direction. */
34968 #define HWRM_TF_TCAM_SET_INPUT_FLAGS_DIR UINT32_C(0x1)
34969 /* If this bit set to 0, then it indicates rx flow. */
34970 #define HWRM_TF_TCAM_SET_INPUT_FLAGS_DIR_RX UINT32_C(0x0)
34971 /* If this bit is set to 1, then it indicates that tx flow. */
34972 #define HWRM_TF_TCAM_SET_INPUT_FLAGS_DIR_TX UINT32_C(0x1)
34973 #define HWRM_TF_TCAM_SET_INPUT_FLAGS_DIR_LAST \
34974 HWRM_TF_TCAM_SET_INPUT_FLAGS_DIR_TX
34976 * Indicate device data is being sent via DMA, the device
34977 * data is packing does not change.
34979 #define HWRM_TF_TCAM_SET_INPUT_FLAGS_DMA UINT32_C(0x2)
34981 * TCAM type of the resource, defined globally in the
34982 * hwrm_tf_resc_type enum.
34985 /* Index of TCAM entry. */
34987 /* Number of bytes in the TCAM key. */
34989 /* Number of bytes in the TCAM result. */
34990 uint8_t result_size;
34992 * Offset from which the mask bytes start in the device data
34993 * array, key offset is always 0.
34995 uint8_t mask_offset;
34996 /* Offset from which the result bytes start in the device data array. */
34997 uint8_t result_offset;
34999 uint8_t unused0[6];
35001 * TCAM key located at offset 0, mask located at mask_offsec
35002 * and result at result_offsec for the device.
35004 uint8_t dev_data[88];
35007 /* hwrm_tf_tcam_set_output (size:128b/16B) */
35008 struct hwrm_tf_tcam_set_output {
35009 /* The specific error status for the command. */
35010 uint16_t error_code;
35011 /* The HWRM command request type. */
35013 /* The sequence ID from the original command. */
35015 /* The length of the response data in number of bytes. */
35018 uint8_t unused0[7];
35020 * This field is used in Output records to indicate that the
35021 * output is completely written to RAM. This field should be
35022 * read as '1' to indicate that the output has been
35023 * completely written. When writing a command completion or
35024 * response to an internal processor, the order of writes has
35025 * to be such that this field is written last.
35030 /********************
35031 * hwrm_tf_tcam_get *
35032 ********************/
35035 /* hwrm_tf_tcam_get_input (size:256b/32B) */
35036 struct hwrm_tf_tcam_get_input {
35037 /* The HWRM command request type. */
35040 * The completion ring to send the completion event on. This should
35041 * be the NQ ID returned from the `nq_alloc` HWRM command.
35043 uint16_t cmpl_ring;
35045 * The sequence ID is used by the driver for tracking multiple
35046 * commands. This ID is treated as opaque data by the firmware and
35047 * the value is returned in the `hwrm_resp_hdr` upon completion.
35051 * The target ID of the command:
35052 * * 0x0-0xFFF8 - The function ID
35053 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
35054 * * 0xFFFD - Reserved for user-space HWRM interface
35057 uint16_t target_id;
35059 * A physical address pointer pointing to a host buffer that the
35060 * command's response data will be written. This can be either a host
35061 * physical address (HPA) or a guest physical address (GPA) and must
35062 * point to a physically contiguous block of memory.
35064 uint64_t resp_addr;
35065 /* Firmware session id returned when HWRM_TF_SESSION_OPEN is sent. */
35066 uint32_t fw_session_id;
35067 /* Control flags. */
35069 /* Indicates the flow direction. */
35070 #define HWRM_TF_TCAM_GET_INPUT_FLAGS_DIR UINT32_C(0x1)
35071 /* If this bit set to 0, then it indicates rx flow. */
35072 #define HWRM_TF_TCAM_GET_INPUT_FLAGS_DIR_RX UINT32_C(0x0)
35073 /* If this bit is set to 1, then it indicates that tx flow. */
35074 #define HWRM_TF_TCAM_GET_INPUT_FLAGS_DIR_TX UINT32_C(0x1)
35075 #define HWRM_TF_TCAM_GET_INPUT_FLAGS_DIR_LAST \
35076 HWRM_TF_TCAM_GET_INPUT_FLAGS_DIR_TX
35078 * TCAM type of the resource, defined globally in the
35079 * hwrm_tf_resc_type enum.
35082 /* Index of a TCAM entry. */
35088 /* hwrm_tf_tcam_get_output (size:2368b/296B) */
35089 struct hwrm_tf_tcam_get_output {
35090 /* The specific error status for the command. */
35091 uint16_t error_code;
35092 /* The HWRM command request type. */
35094 /* The sequence ID from the original command. */
35096 /* The length of the response data in number of bytes. */
35098 /* Number of bytes in the TCAM key. */
35100 /* Number of bytes in the TCAM entry. */
35101 uint8_t result_size;
35102 /* Offset from which the mask bytes start in the device data array. */
35103 uint8_t mask_offset;
35104 /* Offset from which the result bytes start in the device data array. */
35105 uint8_t result_offset;
35107 uint8_t unused0[4];
35109 * TCAM key located at offset 0, mask located at mask_offsec
35110 * and result at result_offsec for the device.
35112 uint8_t dev_data[272];
35114 uint8_t unused1[7];
35116 * This field is used in Output records to indicate that the
35117 * output is completely written to RAM. This field should be
35118 * read as '1' to indicate that the output has been
35119 * completely written. When writing a command completion or
35120 * response to an internal processor, the order of writes has
35121 * to be such that this field is written last.
35126 /*********************
35127 * hwrm_tf_tcam_move *
35128 *********************/
35131 /* hwrm_tf_tcam_move_input (size:1024b/128B) */
35132 struct hwrm_tf_tcam_move_input {
35133 /* The HWRM command request type. */
35136 * The completion ring to send the completion event on. This should
35137 * be the NQ ID returned from the `nq_alloc` HWRM command.
35139 uint16_t cmpl_ring;
35141 * The sequence ID is used by the driver for tracking multiple
35142 * commands. This ID is treated as opaque data by the firmware and
35143 * the value is returned in the `hwrm_resp_hdr` upon completion.
35147 * The target ID of the command:
35148 * * 0x0-0xFFF8 - The function ID
35149 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
35150 * * 0xFFFD - Reserved for user-space HWRM interface
35153 uint16_t target_id;
35155 * A physical address pointer pointing to a host buffer that the
35156 * command's response data will be written. This can be either a host
35157 * physical address (HPA) or a guest physical address (GPA) and must
35158 * point to a physically contiguous block of memory.
35160 uint64_t resp_addr;
35161 /* Firmware session id returned when HWRM_TF_SESSION_OPEN is sent. */
35162 uint32_t fw_session_id;
35163 /* Control flags. */
35165 /* Indicates the flow direction. */
35166 #define HWRM_TF_TCAM_MOVE_INPUT_FLAGS_DIR UINT32_C(0x1)
35167 /* If this bit set to 0, then it indicates rx flow. */
35168 #define HWRM_TF_TCAM_MOVE_INPUT_FLAGS_DIR_RX UINT32_C(0x0)
35169 /* If this bit is set to 1, then it indicates that tx flow. */
35170 #define HWRM_TF_TCAM_MOVE_INPUT_FLAGS_DIR_TX UINT32_C(0x1)
35171 #define HWRM_TF_TCAM_MOVE_INPUT_FLAGS_DIR_LAST \
35172 HWRM_TF_TCAM_MOVE_INPUT_FLAGS_DIR_TX
35174 * TCAM type of the resource, defined globally in the
35175 * hwrm_tf_resc_type enum.
35178 /* Number of TCAM index pairs to be swapped for the device. */
35182 /* TCAM index pairs to be swapped for the device. */
35183 uint16_t idx_pairs[48];
35186 /* hwrm_tf_tcam_move_output (size:128b/16B) */
35187 struct hwrm_tf_tcam_move_output {
35188 /* The specific error status for the command. */
35189 uint16_t error_code;
35190 /* The HWRM command request type. */
35192 /* The sequence ID from the original command. */
35194 /* The length of the response data in number of bytes. */
35197 uint8_t unused0[7];
35199 * This field is used in Output records to indicate that the
35200 * output is completely written to RAM. This field should be
35201 * read as '1' to indicate that the output has been
35202 * completely written. When writing a command completion or
35203 * response to an internal processor, the order of writes has
35204 * to be such that this field is written last.
35209 /*********************
35210 * hwrm_tf_tcam_free *
35211 *********************/
35214 /* hwrm_tf_tcam_free_input (size:1024b/128B) */
35215 struct hwrm_tf_tcam_free_input {
35216 /* The HWRM command request type. */
35219 * The completion ring to send the completion event on. This should
35220 * be the NQ ID returned from the `nq_alloc` HWRM command.
35222 uint16_t cmpl_ring;
35224 * The sequence ID is used by the driver for tracking multiple
35225 * commands. This ID is treated as opaque data by the firmware and
35226 * the value is returned in the `hwrm_resp_hdr` upon completion.
35230 * The target ID of the command:
35231 * * 0x0-0xFFF8 - The function ID
35232 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
35233 * * 0xFFFD - Reserved for user-space HWRM interface
35236 uint16_t target_id;
35238 * A physical address pointer pointing to a host buffer that the
35239 * command's response data will be written. This can be either a host
35240 * physical address (HPA) or a guest physical address (GPA) and must
35241 * point to a physically contiguous block of memory.
35243 uint64_t resp_addr;
35244 /* Firmware session id returned when HWRM_TF_SESSION_OPEN is sent. */
35245 uint32_t fw_session_id;
35246 /* Control flags. */
35248 /* Indicates the flow direction. */
35249 #define HWRM_TF_TCAM_FREE_INPUT_FLAGS_DIR UINT32_C(0x1)
35250 /* If this bit set to 0, then it indicates rx flow. */
35251 #define HWRM_TF_TCAM_FREE_INPUT_FLAGS_DIR_RX UINT32_C(0x0)
35252 /* If this bit is set to 1, then it indicates that tx flow. */
35253 #define HWRM_TF_TCAM_FREE_INPUT_FLAGS_DIR_TX UINT32_C(0x1)
35254 #define HWRM_TF_TCAM_FREE_INPUT_FLAGS_DIR_LAST \
35255 HWRM_TF_TCAM_FREE_INPUT_FLAGS_DIR_TX
35257 * TCAM type of the resource, defined globally in the
35258 * hwrm_tf_resc_type enum.
35261 /* Number of TCAM index to be deleted for the device. */
35265 /* TCAM index list to be deleted for the device. */
35266 uint16_t idx_list[48];
35269 /* hwrm_tf_tcam_free_output (size:128b/16B) */
35270 struct hwrm_tf_tcam_free_output {
35271 /* The specific error status for the command. */
35272 uint16_t error_code;
35273 /* The HWRM command request type. */
35275 /* The sequence ID from the original command. */
35277 /* The length of the response data in number of bytes. */
35280 uint8_t unused0[7];
35282 * This field is used in Output records to indicate that the
35283 * output is completely written to RAM. This field should be
35284 * read as '1' to indicate that the output has been
35285 * completely written. When writing a command completion or
35286 * response to an internal processor, the order of writes has
35287 * to be such that this field is written last.
35292 /******************************
35293 * hwrm_tunnel_dst_port_query *
35294 ******************************/
35297 /* hwrm_tunnel_dst_port_query_input (size:192b/24B) */
35298 struct hwrm_tunnel_dst_port_query_input {
35299 /* The HWRM command request type. */
35302 * The completion ring to send the completion event on. This should
35303 * be the NQ ID returned from the `nq_alloc` HWRM command.
35305 uint16_t cmpl_ring;
35307 * The sequence ID is used by the driver for tracking multiple
35308 * commands. This ID is treated as opaque data by the firmware and
35309 * the value is returned in the `hwrm_resp_hdr` upon completion.
35313 * The target ID of the command:
35314 * * 0x0-0xFFF8 - The function ID
35315 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
35316 * * 0xFFFD - Reserved for user-space HWRM interface
35319 uint16_t target_id;
35321 * A physical address pointer pointing to a host buffer that the
35322 * command's response data will be written. This can be either a host
35323 * physical address (HPA) or a guest physical address (GPA) and must
35324 * point to a physically contiguous block of memory.
35326 uint64_t resp_addr;
35328 uint8_t tunnel_type;
35329 /* Virtual eXtensible Local Area Network (VXLAN) */
35330 #define HWRM_TUNNEL_DST_PORT_QUERY_INPUT_TUNNEL_TYPE_VXLAN \
35332 /* Generic Network Virtualization Encapsulation (Geneve) */
35333 #define HWRM_TUNNEL_DST_PORT_QUERY_INPUT_TUNNEL_TYPE_GENEVE \
35335 /* IPV4 over virtual eXtensible Local Area Network (IPV4oVXLAN) */
35336 #define HWRM_TUNNEL_DST_PORT_QUERY_INPUT_TUNNEL_TYPE_VXLAN_V4 \
35338 /* Enhance Generic Routing Encapsulation (GRE version 1) inside IP datagram payload */
35339 #define HWRM_TUNNEL_DST_PORT_QUERY_INPUT_TUNNEL_TYPE_IPGRE_V1 \
35341 /* Use fixed layer 2 ether type of 0xFFFF */
35342 #define HWRM_TUNNEL_DST_PORT_QUERY_INPUT_TUNNEL_TYPE_L2_ETYPE \
35344 /* IPV6 over virtual eXtensible Local Area Network with GPE header (IPV6oVXLANGPE) */
35345 #define HWRM_TUNNEL_DST_PORT_QUERY_INPUT_TUNNEL_TYPE_VXLAN_GPE_V6 \
35347 #define HWRM_TUNNEL_DST_PORT_QUERY_INPUT_TUNNEL_TYPE_LAST \
35348 HWRM_TUNNEL_DST_PORT_QUERY_INPUT_TUNNEL_TYPE_VXLAN_GPE_V6
35349 uint8_t unused_0[7];
35352 /* hwrm_tunnel_dst_port_query_output (size:128b/16B) */
35353 struct hwrm_tunnel_dst_port_query_output {
35354 /* The specific error status for the command. */
35355 uint16_t error_code;
35356 /* The HWRM command request type. */
35358 /* The sequence ID from the original command. */
35360 /* The length of the response data in number of bytes. */
35363 * This field represents the identifier of L4 destination port
35364 * used for the given tunnel type. This field is valid for
35365 * specific tunnel types that use layer 4 (e.g. UDP)
35366 * transports for tunneling.
35368 uint16_t tunnel_dst_port_id;
35370 * This field represents the value of L4 destination port
35371 * identified by tunnel_dst_port_id. This field is valid for
35372 * specific tunnel types that use layer 4 (e.g. UDP)
35373 * transports for tunneling.
35374 * This field is in network byte order.
35376 * A value of 0 means that the destination port is not
35379 uint16_t tunnel_dst_port_val;
35380 uint8_t unused_0[3];
35382 * This field is used in Output records to indicate that the output
35383 * is completely written to RAM. This field should be read as '1'
35384 * to indicate that the output has been completely written.
35385 * When writing a command completion or response to an internal processor,
35386 * the order of writes has to be such that this field is written last.
35391 /******************************
35392 * hwrm_tunnel_dst_port_alloc *
35393 ******************************/
35396 /* hwrm_tunnel_dst_port_alloc_input (size:192b/24B) */
35397 struct hwrm_tunnel_dst_port_alloc_input {
35398 /* The HWRM command request type. */
35401 * The completion ring to send the completion event on. This should
35402 * be the NQ ID returned from the `nq_alloc` HWRM command.
35404 uint16_t cmpl_ring;
35406 * The sequence ID is used by the driver for tracking multiple
35407 * commands. This ID is treated as opaque data by the firmware and
35408 * the value is returned in the `hwrm_resp_hdr` upon completion.
35412 * The target ID of the command:
35413 * * 0x0-0xFFF8 - The function ID
35414 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
35415 * * 0xFFFD - Reserved for user-space HWRM interface
35418 uint16_t target_id;
35420 * A physical address pointer pointing to a host buffer that the
35421 * command's response data will be written. This can be either a host
35422 * physical address (HPA) or a guest physical address (GPA) and must
35423 * point to a physically contiguous block of memory.
35425 uint64_t resp_addr;
35427 uint8_t tunnel_type;
35428 /* Virtual eXtensible Local Area Network (VXLAN) */
35429 #define HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_VXLAN \
35431 /* Generic Network Virtualization Encapsulation (Geneve) */
35432 #define HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_GENEVE \
35434 /* IPV4 over virtual eXtensible Local Area Network (IPV4oVXLAN) */
35435 #define HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_VXLAN_V4 \
35437 /* Enhance Generic Routing Encapsulation (GRE version 1) inside IP datagram payload */
35438 #define HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_IPGRE_V1 \
35440 /* Use fixed layer 2 ether type of 0xFFFF */
35441 #define HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_L2_ETYPE \
35443 /* IPV6 over virtual eXtensible Local Area Network with GPE header (IPV6oVXLANGPE) */
35444 #define HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_VXLAN_GPE_V6 \
35446 #define HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_LAST \
35447 HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_VXLAN_GPE_V6
35450 * This field represents the value of L4 destination port used
35451 * for the given tunnel type. This field is valid for
35452 * specific tunnel types that use layer 4 (e.g. UDP)
35453 * transports for tunneling.
35455 * This field is in network byte order.
35457 * A value of 0 shall fail the command.
35459 uint16_t tunnel_dst_port_val;
35460 uint8_t unused_1[4];
35463 /* hwrm_tunnel_dst_port_alloc_output (size:128b/16B) */
35464 struct hwrm_tunnel_dst_port_alloc_output {
35465 /* The specific error status for the command. */
35466 uint16_t error_code;
35467 /* The HWRM command request type. */
35469 /* The sequence ID from the original command. */
35471 /* The length of the response data in number of bytes. */
35474 * Identifier of a tunnel L4 destination port value. Only applies to tunnel
35475 * types that has l4 destination port parameters.
35477 uint16_t tunnel_dst_port_id;
35478 uint8_t unused_0[5];
35480 * This field is used in Output records to indicate that the output
35481 * is completely written to RAM. This field should be read as '1'
35482 * to indicate that the output has been completely written.
35483 * When writing a command completion or response to an internal processor,
35484 * the order of writes has to be such that this field is written last.
35489 /*****************************
35490 * hwrm_tunnel_dst_port_free *
35491 *****************************/
35494 /* hwrm_tunnel_dst_port_free_input (size:192b/24B) */
35495 struct hwrm_tunnel_dst_port_free_input {
35496 /* The HWRM command request type. */
35499 * The completion ring to send the completion event on. This should
35500 * be the NQ ID returned from the `nq_alloc` HWRM command.
35502 uint16_t cmpl_ring;
35504 * The sequence ID is used by the driver for tracking multiple
35505 * commands. This ID is treated as opaque data by the firmware and
35506 * the value is returned in the `hwrm_resp_hdr` upon completion.
35510 * The target ID of the command:
35511 * * 0x0-0xFFF8 - The function ID
35512 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
35513 * * 0xFFFD - Reserved for user-space HWRM interface
35516 uint16_t target_id;
35518 * A physical address pointer pointing to a host buffer that the
35519 * command's response data will be written. This can be either a host
35520 * physical address (HPA) or a guest physical address (GPA) and must
35521 * point to a physically contiguous block of memory.
35523 uint64_t resp_addr;
35525 uint8_t tunnel_type;
35526 /* Virtual eXtensible Local Area Network (VXLAN) */
35527 #define HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_VXLAN \
35529 /* Generic Network Virtualization Encapsulation (Geneve) */
35530 #define HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_GENEVE \
35532 /* IPV4 over virtual eXtensible Local Area Network (IPV4oVXLAN) */
35533 #define HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_VXLAN_V4 \
35535 /* Enhance Generic Routing Encapsulation (GRE version 1) inside IP datagram payload */
35536 #define HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_IPGRE_V1 \
35538 /* Use fixed layer 2 ether type of 0xFFFF */
35539 #define HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_L2_ETYPE \
35541 /* IPV6 over virtual eXtensible Local Area Network with GPE header (IPV6oVXLANGPE) */
35542 #define HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_VXLAN_GPE_V6 \
35544 #define HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_LAST \
35545 HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_VXLAN_GPE_V6
35548 * Identifier of a tunnel L4 destination port value. Only applies to tunnel
35549 * types that has l4 destination port parameters.
35551 uint16_t tunnel_dst_port_id;
35552 uint8_t unused_1[4];
35555 /* hwrm_tunnel_dst_port_free_output (size:128b/16B) */
35556 struct hwrm_tunnel_dst_port_free_output {
35557 /* The specific error status for the command. */
35558 uint16_t error_code;
35559 /* The HWRM command request type. */
35561 /* The sequence ID from the original command. */
35563 /* The length of the response data in number of bytes. */
35565 uint8_t unused_1[7];
35567 * This field is used in Output records to indicate that the output
35568 * is completely written to RAM. This field should be read as '1'
35569 * to indicate that the output has been completely written.
35570 * When writing a command completion or response to an internal processor,
35571 * the order of writes has to be such that this field is written last.
35576 /* Periodic statistics context DMA to host. */
35577 /* ctx_hw_stats (size:1280b/160B) */
35578 struct ctx_hw_stats {
35579 /* Number of received unicast packets */
35580 uint64_t rx_ucast_pkts;
35581 /* Number of received multicast packets */
35582 uint64_t rx_mcast_pkts;
35583 /* Number of received broadcast packets */
35584 uint64_t rx_bcast_pkts;
35585 /* Number of discarded packets on received path */
35586 uint64_t rx_discard_pkts;
35587 /* Number of dropped packets on received path */
35588 uint64_t rx_drop_pkts;
35589 /* Number of received bytes for unicast traffic */
35590 uint64_t rx_ucast_bytes;
35591 /* Number of received bytes for multicast traffic */
35592 uint64_t rx_mcast_bytes;
35593 /* Number of received bytes for broadcast traffic */
35594 uint64_t rx_bcast_bytes;
35595 /* Number of transmitted unicast packets */
35596 uint64_t tx_ucast_pkts;
35597 /* Number of transmitted multicast packets */
35598 uint64_t tx_mcast_pkts;
35599 /* Number of transmitted broadcast packets */
35600 uint64_t tx_bcast_pkts;
35601 /* Number of discarded packets on transmit path */
35602 uint64_t tx_discard_pkts;
35603 /* Number of dropped packets on transmit path */
35604 uint64_t tx_drop_pkts;
35605 /* Number of transmitted bytes for unicast traffic */
35606 uint64_t tx_ucast_bytes;
35607 /* Number of transmitted bytes for multicast traffic */
35608 uint64_t tx_mcast_bytes;
35609 /* Number of transmitted bytes for broadcast traffic */
35610 uint64_t tx_bcast_bytes;
35611 /* Number of TPA packets */
35613 /* Number of TPA bytes */
35614 uint64_t tpa_bytes;
35615 /* Number of TPA events */
35616 uint64_t tpa_events;
35617 /* Number of TPA aborts */
35618 uint64_t tpa_aborts;
35621 /* Periodic statistics context DMA to host. */
35622 /* ctx_hw_stats_ext (size:1344b/168B) */
35623 struct ctx_hw_stats_ext {
35624 /* Number of received unicast packets */
35625 uint64_t rx_ucast_pkts;
35626 /* Number of received multicast packets */
35627 uint64_t rx_mcast_pkts;
35628 /* Number of received broadcast packets */
35629 uint64_t rx_bcast_pkts;
35630 /* Number of discarded packets on received path */
35631 uint64_t rx_discard_pkts;
35632 /* Number of dropped packets on received path */
35633 uint64_t rx_drop_pkts;
35634 /* Number of received bytes for unicast traffic */
35635 uint64_t rx_ucast_bytes;
35636 /* Number of received bytes for multicast traffic */
35637 uint64_t rx_mcast_bytes;
35638 /* Number of received bytes for broadcast traffic */
35639 uint64_t rx_bcast_bytes;
35640 /* Number of transmitted unicast packets */
35641 uint64_t tx_ucast_pkts;
35642 /* Number of transmitted multicast packets */
35643 uint64_t tx_mcast_pkts;
35644 /* Number of transmitted broadcast packets */
35645 uint64_t tx_bcast_pkts;
35646 /* Number of discarded packets on transmit path */
35647 uint64_t tx_discard_pkts;
35648 /* Number of dropped packets on transmit path */
35649 uint64_t tx_drop_pkts;
35650 /* Number of transmitted bytes for unicast traffic */
35651 uint64_t tx_ucast_bytes;
35652 /* Number of transmitted bytes for multicast traffic */
35653 uint64_t tx_mcast_bytes;
35654 /* Number of transmitted bytes for broadcast traffic */
35655 uint64_t tx_bcast_bytes;
35656 /* Number of TPA eligible packets */
35657 uint64_t rx_tpa_eligible_pkt;
35658 /* Number of TPA eligible bytes */
35659 uint64_t rx_tpa_eligible_bytes;
35660 /* Number of TPA packets */
35661 uint64_t rx_tpa_pkt;
35662 /* Number of TPA bytes */
35663 uint64_t rx_tpa_bytes;
35664 /* Number of TPA errors */
35665 uint64_t rx_tpa_errors;
35668 /* Periodic Engine statistics context DMA to host. */
35669 /* ctx_eng_stats (size:512b/64B) */
35670 struct ctx_eng_stats {
35672 * Count of data bytes into the Engine.
35673 * This includes any user supplied prefix,
35674 * but does not include any predefined
35677 uint64_t eng_bytes_in;
35678 /* Count of data bytes out of the Engine. */
35679 uint64_t eng_bytes_out;
35681 * Count, in 4-byte (dword) units, of bytes
35682 * that are input as auxiliary data.
35683 * This includes the aux_cmd data.
35685 uint64_t aux_bytes_in;
35687 * Count, in 4-byte (dword) units, of bytes
35688 * that are output as auxiliary data.
35689 * This count is the buffer space for aux_data
35690 * output provided in the RQE, not the actual
35693 uint64_t aux_bytes_out;
35694 /* Count of number of commands executed. */
35697 * Count of number of error commands.
35698 * These are the commands with a
35699 * non-zero status value.
35701 uint64_t error_commands;
35703 * Compression/Encryption Engine usage,
35704 * the unit is count of clock cycles
35706 uint64_t cce_engine_usage;
35708 * De-Compression/De-cryption Engine usage,
35709 * the unit is count of clock cycles
35711 uint64_t cdd_engine_usage;
35714 /***********************
35715 * hwrm_stat_ctx_alloc *
35716 ***********************/
35719 /* hwrm_stat_ctx_alloc_input (size:256b/32B) */
35720 struct hwrm_stat_ctx_alloc_input {
35721 /* The HWRM command request type. */
35724 * The completion ring to send the completion event on. This should
35725 * be the NQ ID returned from the `nq_alloc` HWRM command.
35727 uint16_t cmpl_ring;
35729 * The sequence ID is used by the driver for tracking multiple
35730 * commands. This ID is treated as opaque data by the firmware and
35731 * the value is returned in the `hwrm_resp_hdr` upon completion.
35735 * The target ID of the command:
35736 * * 0x0-0xFFF8 - The function ID
35737 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
35738 * * 0xFFFD - Reserved for user-space HWRM interface
35741 uint16_t target_id;
35743 * A physical address pointer pointing to a host buffer that the
35744 * command's response data will be written. This can be either a host
35745 * physical address (HPA) or a guest physical address (GPA) and must
35746 * point to a physically contiguous block of memory.
35748 uint64_t resp_addr;
35750 * This is the address for statistic block.
35751 * > For new versions of the chip, this address should be 128B
35754 uint64_t stats_dma_addr;
35756 * The statistic block update period in ms.
35757 * e.g. 250ms, 500ms, 750ms, 1000ms.
35758 * If update_period_ms is 0, then the stats update
35759 * shall be never done and the DMA address shall not be used.
35760 * In this case, the stat block can only be read by
35761 * hwrm_stat_ctx_query command.
35762 * On Ethernet/L2 based devices:
35763 * if tpa v2 supported (hwrm_vnic_qcaps[max_aggs_supported]>0),
35764 * ctx_hw_stats_ext is used for DMA,
35766 * ctx_hw_stats is used for DMA.
35768 uint32_t update_period_ms;
35770 * This field is used to specify statistics context specific
35771 * configuration flags.
35773 uint8_t stat_ctx_flags;
35775 * When this bit is set to '1', the statistics context shall be
35776 * allocated for RoCE traffic only. In this case, traffic other
35777 * than offloaded RoCE traffic shall not be included in this
35778 * statistic context.
35779 * When this bit is set to '0', the statistics context shall be
35780 * used for network traffic or engine traffic.
35782 #define HWRM_STAT_CTX_ALLOC_INPUT_STAT_CTX_FLAGS_ROCE UINT32_C(0x1)
35785 * This is the size of the structure (ctx_hw_stats or
35786 * ctx_hw_stats_ext) that the driver has allocated to be used
35787 * for the periodic DMA updates.
35789 uint16_t stats_dma_length;
35792 /* hwrm_stat_ctx_alloc_output (size:128b/16B) */
35793 struct hwrm_stat_ctx_alloc_output {
35794 /* The specific error status for the command. */
35795 uint16_t error_code;
35796 /* The HWRM command request type. */
35798 /* The sequence ID from the original command. */
35800 /* The length of the response data in number of bytes. */
35802 /* This is the statistics context ID value. */
35803 uint32_t stat_ctx_id;
35804 uint8_t unused_0[3];
35806 * This field is used in Output records to indicate that the output
35807 * is completely written to RAM. This field should be read as '1'
35808 * to indicate that the output has been completely written.
35809 * When writing a command completion or response to an internal processor,
35810 * the order of writes has to be such that this field is written last.
35815 /**********************
35816 * hwrm_stat_ctx_free *
35817 **********************/
35820 /* hwrm_stat_ctx_free_input (size:192b/24B) */
35821 struct hwrm_stat_ctx_free_input {
35822 /* The HWRM command request type. */
35825 * The completion ring to send the completion event on. This should
35826 * be the NQ ID returned from the `nq_alloc` HWRM command.
35828 uint16_t cmpl_ring;
35830 * The sequence ID is used by the driver for tracking multiple
35831 * commands. This ID is treated as opaque data by the firmware and
35832 * the value is returned in the `hwrm_resp_hdr` upon completion.
35836 * The target ID of the command:
35837 * * 0x0-0xFFF8 - The function ID
35838 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
35839 * * 0xFFFD - Reserved for user-space HWRM interface
35842 uint16_t target_id;
35844 * A physical address pointer pointing to a host buffer that the
35845 * command's response data will be written. This can be either a host
35846 * physical address (HPA) or a guest physical address (GPA) and must
35847 * point to a physically contiguous block of memory.
35849 uint64_t resp_addr;
35850 /* ID of the statistics context that is being queried. */
35851 uint32_t stat_ctx_id;
35852 uint8_t unused_0[4];
35855 /* hwrm_stat_ctx_free_output (size:128b/16B) */
35856 struct hwrm_stat_ctx_free_output {
35857 /* The specific error status for the command. */
35858 uint16_t error_code;
35859 /* The HWRM command request type. */
35861 /* The sequence ID from the original command. */
35863 /* The length of the response data in number of bytes. */
35865 /* This is the statistics context ID value. */
35866 uint32_t stat_ctx_id;
35867 uint8_t unused_0[3];
35869 * This field is used in Output records to indicate that the output
35870 * is completely written to RAM. This field should be read as '1'
35871 * to indicate that the output has been completely written.
35872 * When writing a command completion or response to an internal processor,
35873 * the order of writes has to be such that this field is written last.
35878 /***********************
35879 * hwrm_stat_ctx_query *
35880 ***********************/
35883 /* hwrm_stat_ctx_query_input (size:192b/24B) */
35884 struct hwrm_stat_ctx_query_input {
35885 /* The HWRM command request type. */
35888 * The completion ring to send the completion event on. This should
35889 * be the NQ ID returned from the `nq_alloc` HWRM command.
35891 uint16_t cmpl_ring;
35893 * The sequence ID is used by the driver for tracking multiple
35894 * commands. This ID is treated as opaque data by the firmware and
35895 * the value is returned in the `hwrm_resp_hdr` upon completion.
35899 * The target ID of the command:
35900 * * 0x0-0xFFF8 - The function ID
35901 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
35902 * * 0xFFFD - Reserved for user-space HWRM interface
35905 uint16_t target_id;
35907 * A physical address pointer pointing to a host buffer that the
35908 * command's response data will be written. This can be either a host
35909 * physical address (HPA) or a guest physical address (GPA) and must
35910 * point to a physically contiguous block of memory.
35912 uint64_t resp_addr;
35913 /* ID of the statistics context that is being queried. */
35914 uint32_t stat_ctx_id;
35915 uint8_t unused_0[4];
35918 /* hwrm_stat_ctx_query_output (size:1408b/176B) */
35919 struct hwrm_stat_ctx_query_output {
35920 /* The specific error status for the command. */
35921 uint16_t error_code;
35922 /* The HWRM command request type. */
35924 /* The sequence ID from the original command. */
35926 /* The length of the response data in number of bytes. */
35928 /* Number of transmitted unicast packets */
35929 uint64_t tx_ucast_pkts;
35930 /* Number of transmitted multicast packets */
35931 uint64_t tx_mcast_pkts;
35932 /* Number of transmitted broadcast packets */
35933 uint64_t tx_bcast_pkts;
35934 /* Number of transmitted packets with error */
35935 uint64_t tx_err_pkts;
35936 /* Number of dropped packets on transmit path */
35937 uint64_t tx_drop_pkts;
35938 /* Number of transmitted bytes for unicast traffic */
35939 uint64_t tx_ucast_bytes;
35940 /* Number of transmitted bytes for multicast traffic */
35941 uint64_t tx_mcast_bytes;
35942 /* Number of transmitted bytes for broadcast traffic */
35943 uint64_t tx_bcast_bytes;
35944 /* Number of received unicast packets */
35945 uint64_t rx_ucast_pkts;
35946 /* Number of received multicast packets */
35947 uint64_t rx_mcast_pkts;
35948 /* Number of received broadcast packets */
35949 uint64_t rx_bcast_pkts;
35950 /* Number of received packets with error */
35951 uint64_t rx_err_pkts;
35952 /* Number of dropped packets on received path */
35953 uint64_t rx_drop_pkts;
35954 /* Number of received bytes for unicast traffic */
35955 uint64_t rx_ucast_bytes;
35956 /* Number of received bytes for multicast traffic */
35957 uint64_t rx_mcast_bytes;
35958 /* Number of received bytes for broadcast traffic */
35959 uint64_t rx_bcast_bytes;
35960 /* Number of aggregated unicast packets */
35961 uint64_t rx_agg_pkts;
35962 /* Number of aggregated unicast bytes */
35963 uint64_t rx_agg_bytes;
35964 /* Number of aggregation events */
35965 uint64_t rx_agg_events;
35966 /* Number of aborted aggregations */
35967 uint64_t rx_agg_aborts;
35968 uint8_t unused_0[7];
35970 * This field is used in Output records to indicate that the output
35971 * is completely written to RAM. This field should be read as '1'
35972 * to indicate that the output has been completely written.
35973 * When writing a command completion or response to an internal processor,
35974 * the order of writes has to be such that this field is written last.
35979 /***************************
35980 * hwrm_stat_ctx_eng_query *
35981 ***************************/
35984 /* hwrm_stat_ctx_eng_query_input (size:192b/24B) */
35985 struct hwrm_stat_ctx_eng_query_input {
35986 /* The HWRM command request type. */
35989 * The completion ring to send the completion event on. This should
35990 * be the NQ ID returned from the `nq_alloc` HWRM command.
35992 uint16_t cmpl_ring;
35994 * The sequence ID is used by the driver for tracking multiple
35995 * commands. This ID is treated as opaque data by the firmware and
35996 * the value is returned in the `hwrm_resp_hdr` upon completion.
36000 * The target ID of the command:
36001 * * 0x0-0xFFF8 - The function ID
36002 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
36003 * * 0xFFFD - Reserved for user-space HWRM interface
36006 uint16_t target_id;
36008 * A physical address pointer pointing to a host buffer that the
36009 * command's response data will be written. This can be either a host
36010 * physical address (HPA) or a guest physical address (GPA) and must
36011 * point to a physically contiguous block of memory.
36013 uint64_t resp_addr;
36014 /* ID of the statistics context that is being queried. */
36015 uint32_t stat_ctx_id;
36016 uint8_t unused_0[4];
36019 /* hwrm_stat_ctx_eng_query_output (size:640b/80B) */
36020 struct hwrm_stat_ctx_eng_query_output {
36021 /* The specific error status for the command. */
36022 uint16_t error_code;
36023 /* The HWRM command request type. */
36025 /* The sequence ID from the original command. */
36027 /* The length of the response data in number of bytes. */
36030 * Count of data bytes into the Engine.
36031 * This includes any user supplied prefix,
36032 * but does not include any predefined
36035 uint64_t eng_bytes_in;
36036 /* Count of data bytes out of the Engine. */
36037 uint64_t eng_bytes_out;
36039 * Count, in 4-byte (dword) units, of bytes
36040 * that are input as auxiliary data.
36041 * This includes the aux_cmd data.
36043 uint64_t aux_bytes_in;
36045 * Count, in 4-byte (dword) units, of bytes
36046 * that are output as auxiliary data.
36047 * This count is the buffer space for aux_data
36048 * output provided in the RQE, not the actual
36051 uint64_t aux_bytes_out;
36052 /* Count of number of commands executed. */
36055 * Count of number of error commands.
36056 * These are the commands with a
36057 * non-zero status value.
36059 uint64_t error_commands;
36061 * Compression/Encryption Engine usage,
36062 * the unit is count of clock cycles
36064 uint64_t cce_engine_usage;
36066 * De-Compression/De-cryption Engine usage,
36067 * the unit is count of clock cycles
36069 uint64_t cdd_engine_usage;
36070 uint8_t unused_0[7];
36072 * This field is used in Output records to indicate that the output
36073 * is completely written to RAM. This field should be read as '1'
36074 * to indicate that the output has been completely written.
36075 * When writing a command completion or response to an internal processor,
36076 * the order of writes has to be such that this field is written last.
36081 /***************************
36082 * hwrm_stat_ctx_clr_stats *
36083 ***************************/
36086 /* hwrm_stat_ctx_clr_stats_input (size:192b/24B) */
36087 struct hwrm_stat_ctx_clr_stats_input {
36088 /* The HWRM command request type. */
36091 * The completion ring to send the completion event on. This should
36092 * be the NQ ID returned from the `nq_alloc` HWRM command.
36094 uint16_t cmpl_ring;
36096 * The sequence ID is used by the driver for tracking multiple
36097 * commands. This ID is treated as opaque data by the firmware and
36098 * the value is returned in the `hwrm_resp_hdr` upon completion.
36102 * The target ID of the command:
36103 * * 0x0-0xFFF8 - The function ID
36104 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
36105 * * 0xFFFD - Reserved for user-space HWRM interface
36108 uint16_t target_id;
36110 * A physical address pointer pointing to a host buffer that the
36111 * command's response data will be written. This can be either a host
36112 * physical address (HPA) or a guest physical address (GPA) and must
36113 * point to a physically contiguous block of memory.
36115 uint64_t resp_addr;
36116 /* ID of the statistics context that is being queried. */
36117 uint32_t stat_ctx_id;
36118 uint8_t unused_0[4];
36121 /* hwrm_stat_ctx_clr_stats_output (size:128b/16B) */
36122 struct hwrm_stat_ctx_clr_stats_output {
36123 /* The specific error status for the command. */
36124 uint16_t error_code;
36125 /* The HWRM command request type. */
36127 /* The sequence ID from the original command. */
36129 /* The length of the response data in number of bytes. */
36131 uint8_t unused_0[7];
36133 * This field is used in Output records to indicate that the output
36134 * is completely written to RAM. This field should be read as '1'
36135 * to indicate that the output has been completely written.
36136 * When writing a command completion or response to an internal processor,
36137 * the order of writes has to be such that this field is written last.
36142 /********************
36143 * hwrm_pcie_qstats *
36144 ********************/
36147 /* hwrm_pcie_qstats_input (size:256b/32B) */
36148 struct hwrm_pcie_qstats_input {
36149 /* The HWRM command request type. */
36152 * The completion ring to send the completion event on. This should
36153 * be the NQ ID returned from the `nq_alloc` HWRM command.
36155 uint16_t cmpl_ring;
36157 * The sequence ID is used by the driver for tracking multiple
36158 * commands. This ID is treated as opaque data by the firmware and
36159 * the value is returned in the `hwrm_resp_hdr` upon completion.
36163 * The target ID of the command:
36164 * * 0x0-0xFFF8 - The function ID
36165 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
36166 * * 0xFFFD - Reserved for user-space HWRM interface
36169 uint16_t target_id;
36171 * A physical address pointer pointing to a host buffer that the
36172 * command's response data will be written. This can be either a host
36173 * physical address (HPA) or a guest physical address (GPA) and must
36174 * point to a physically contiguous block of memory.
36176 uint64_t resp_addr;
36178 * The size of PCIe statistics block in bytes.
36179 * Firmware will DMA the PCIe statistics to
36180 * the host with this field size in the response.
36182 uint16_t pcie_stat_size;
36183 uint8_t unused_0[6];
36185 * This is the host address where
36186 * PCIe statistics will be stored
36188 uint64_t pcie_stat_host_addr;
36191 /* hwrm_pcie_qstats_output (size:128b/16B) */
36192 struct hwrm_pcie_qstats_output {
36193 /* The specific error status for the command. */
36194 uint16_t error_code;
36195 /* The HWRM command request type. */
36197 /* The sequence ID from the original command. */
36199 /* The length of the response data in number of bytes. */
36201 /* The size of PCIe statistics block in bytes. */
36202 uint16_t pcie_stat_size;
36203 uint8_t unused_0[5];
36205 * This field is used in Output records to indicate that the output
36206 * is completely written to RAM. This field should be read as '1'
36207 * to indicate that the output has been completely written.
36208 * When writing a command completion or response to an internal processor,
36209 * the order of writes has to be such that this field is written last.
36214 /* PCIe Statistics Formats */
36215 /* pcie_ctx_hw_stats (size:768b/96B) */
36216 struct pcie_ctx_hw_stats {
36217 /* Number of physical layer receiver errors */
36218 uint64_t pcie_pl_signal_integrity;
36219 /* Number of DLLP CRC errors detected by Data Link Layer */
36220 uint64_t pcie_dl_signal_integrity;
36222 * Number of TLP LCRC and sequence number errors detected
36223 * by Data Link Layer
36225 uint64_t pcie_tl_signal_integrity;
36226 /* Number of times LTSSM entered Recovery state */
36227 uint64_t pcie_link_integrity;
36228 /* Report number of TLP bits that have been transmitted in Mbps */
36229 uint64_t pcie_tx_traffic_rate;
36230 /* Report number of TLP bits that have been received in Mbps */
36231 uint64_t pcie_rx_traffic_rate;
36232 /* Number of DLLP bytes that have been transmitted */
36233 uint64_t pcie_tx_dllp_statistics;
36234 /* Number of DLLP bytes that have been received */
36235 uint64_t pcie_rx_dllp_statistics;
36237 * Number of times spent in each phase of gen3
36240 uint64_t pcie_equalization_time;
36241 /* Records the last 16 transitions of the LTSSM */
36242 uint32_t pcie_ltssm_histogram[4];
36244 * Record the last 8 reasons on why LTSSM transitioned
36247 uint64_t pcie_recovery_histogram;
36250 /**********************
36251 * hwrm_exec_fwd_resp *
36252 **********************/
36255 /* hwrm_exec_fwd_resp_input (size:1024b/128B) */
36256 struct hwrm_exec_fwd_resp_input {
36257 /* The HWRM command request type. */
36260 * The completion ring to send the completion event on. This should
36261 * be the NQ ID returned from the `nq_alloc` HWRM command.
36263 uint16_t cmpl_ring;
36265 * The sequence ID is used by the driver for tracking multiple
36266 * commands. This ID is treated as opaque data by the firmware and
36267 * the value is returned in the `hwrm_resp_hdr` upon completion.
36271 * The target ID of the command:
36272 * * 0x0-0xFFF8 - The function ID
36273 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
36274 * * 0xFFFD - Reserved for user-space HWRM interface
36277 uint16_t target_id;
36279 * A physical address pointer pointing to a host buffer that the
36280 * command's response data will be written. This can be either a host
36281 * physical address (HPA) or a guest physical address (GPA) and must
36282 * point to a physically contiguous block of memory.
36284 uint64_t resp_addr;
36286 * This is an encapsulated request. This request should
36287 * be executed by the HWRM and the response should be
36288 * provided in the response buffer inside the encapsulated
36291 uint32_t encap_request[26];
36293 * This value indicates the target id of the response to
36294 * the encapsulated request.
36295 * 0x0 - 0xFFF8 - Used for function ids
36296 * 0xFFF8 - 0xFFFE - Reserved for internal processors
36299 uint16_t encap_resp_target_id;
36300 uint8_t unused_0[6];
36303 /* hwrm_exec_fwd_resp_output (size:128b/16B) */
36304 struct hwrm_exec_fwd_resp_output {
36305 /* The specific error status for the command. */
36306 uint16_t error_code;
36307 /* The HWRM command request type. */
36309 /* The sequence ID from the original command. */
36311 /* The length of the response data in number of bytes. */
36313 uint8_t unused_0[7];
36315 * This field is used in Output records to indicate that the output
36316 * is completely written to RAM. This field should be read as '1'
36317 * to indicate that the output has been completely written.
36318 * When writing a command completion or response to an internal processor,
36319 * the order of writes has to be such that this field is written last.
36324 /************************
36325 * hwrm_reject_fwd_resp *
36326 ************************/
36329 /* hwrm_reject_fwd_resp_input (size:1024b/128B) */
36330 struct hwrm_reject_fwd_resp_input {
36331 /* The HWRM command request type. */
36334 * The completion ring to send the completion event on. This should
36335 * be the NQ ID returned from the `nq_alloc` HWRM command.
36337 uint16_t cmpl_ring;
36339 * The sequence ID is used by the driver for tracking multiple
36340 * commands. This ID is treated as opaque data by the firmware and
36341 * the value is returned in the `hwrm_resp_hdr` upon completion.
36345 * The target ID of the command:
36346 * * 0x0-0xFFF8 - The function ID
36347 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
36348 * * 0xFFFD - Reserved for user-space HWRM interface
36351 uint16_t target_id;
36353 * A physical address pointer pointing to a host buffer that the
36354 * command's response data will be written. This can be either a host
36355 * physical address (HPA) or a guest physical address (GPA) and must
36356 * point to a physically contiguous block of memory.
36358 uint64_t resp_addr;
36360 * This is an encapsulated request. This request should
36361 * be rejected by the HWRM and the error response should be
36362 * provided in the response buffer inside the encapsulated
36365 uint32_t encap_request[26];
36367 * This value indicates the target id of the response to
36368 * the encapsulated request.
36369 * 0x0 - 0xFFF8 - Used for function ids
36370 * 0xFFF8 - 0xFFFE - Reserved for internal processors
36373 uint16_t encap_resp_target_id;
36374 uint8_t unused_0[6];
36377 /* hwrm_reject_fwd_resp_output (size:128b/16B) */
36378 struct hwrm_reject_fwd_resp_output {
36379 /* The specific error status for the command. */
36380 uint16_t error_code;
36381 /* The HWRM command request type. */
36383 /* The sequence ID from the original command. */
36385 /* The length of the response data in number of bytes. */
36387 uint8_t unused_0[7];
36389 * This field is used in Output records to indicate that the output
36390 * is completely written to RAM. This field should be read as '1'
36391 * to indicate that the output has been completely written.
36392 * When writing a command completion or response to an internal processor,
36393 * the order of writes has to be such that this field is written last.
36403 /* hwrm_fwd_resp_input (size:1024b/128B) */
36404 struct hwrm_fwd_resp_input {
36405 /* The HWRM command request type. */
36408 * The completion ring to send the completion event on. This should
36409 * be the NQ ID returned from the `nq_alloc` HWRM command.
36411 uint16_t cmpl_ring;
36413 * The sequence ID is used by the driver for tracking multiple
36414 * commands. This ID is treated as opaque data by the firmware and
36415 * the value is returned in the `hwrm_resp_hdr` upon completion.
36419 * The target ID of the command:
36420 * * 0x0-0xFFF8 - The function ID
36421 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
36422 * * 0xFFFD - Reserved for user-space HWRM interface
36425 uint16_t target_id;
36427 * A physical address pointer pointing to a host buffer that the
36428 * command's response data will be written. This can be either a host
36429 * physical address (HPA) or a guest physical address (GPA) and must
36430 * point to a physically contiguous block of memory.
36432 uint64_t resp_addr;
36434 * This value indicates the target id of the encapsulated
36436 * 0x0 - 0xFFF8 - Used for function ids
36437 * 0xFFF8 - 0xFFFE - Reserved for internal processors
36440 uint16_t encap_resp_target_id;
36442 * This value indicates the completion ring the encapsulated
36443 * response will be optionally completed on. If the value is
36444 * -1, then no CR completion shall be generated for the
36445 * encapsulated response. Any other value must be a
36446 * valid CR ring_id value. If a valid encap_resp_cmpl_ring
36447 * is provided, then a CR completion shall be generated for
36448 * the encapsulated response.
36450 uint16_t encap_resp_cmpl_ring;
36451 /* This field indicates the length of encapsulated response. */
36452 uint16_t encap_resp_len;
36456 * This is the host address where the encapsulated response
36458 * This area must be 16B aligned and must be cleared to zero
36459 * before the original request is made.
36461 uint64_t encap_resp_addr;
36462 /* This is an encapsulated response. */
36463 uint32_t encap_resp[24];
36466 /* hwrm_fwd_resp_output (size:128b/16B) */
36467 struct hwrm_fwd_resp_output {
36468 /* The specific error status for the command. */
36469 uint16_t error_code;
36470 /* The HWRM command request type. */
36472 /* The sequence ID from the original command. */
36474 /* The length of the response data in number of bytes. */
36476 uint8_t unused_0[7];
36478 * This field is used in Output records to indicate that the output
36479 * is completely written to RAM. This field should be read as '1'
36480 * to indicate that the output has been completely written.
36481 * When writing a command completion or response to an internal processor,
36482 * the order of writes has to be such that this field is written last.
36487 /*****************************
36488 * hwrm_fwd_async_event_cmpl *
36489 *****************************/
36492 /* hwrm_fwd_async_event_cmpl_input (size:320b/40B) */
36493 struct hwrm_fwd_async_event_cmpl_input {
36494 /* The HWRM command request type. */
36497 * The completion ring to send the completion event on. This should
36498 * be the NQ ID returned from the `nq_alloc` HWRM command.
36500 uint16_t cmpl_ring;
36502 * The sequence ID is used by the driver for tracking multiple
36503 * commands. This ID is treated as opaque data by the firmware and
36504 * the value is returned in the `hwrm_resp_hdr` upon completion.
36508 * The target ID of the command:
36509 * * 0x0-0xFFF8 - The function ID
36510 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
36511 * * 0xFFFD - Reserved for user-space HWRM interface
36514 uint16_t target_id;
36516 * A physical address pointer pointing to a host buffer that the
36517 * command's response data will be written. This can be either a host
36518 * physical address (HPA) or a guest physical address (GPA) and must
36519 * point to a physically contiguous block of memory.
36521 uint64_t resp_addr;
36523 * This value indicates the target id of the encapsulated
36524 * asynchronous event.
36525 * 0x0 - 0xFFF8 - Used for function ids
36526 * 0xFFF8 - 0xFFFE - Reserved for internal processors
36527 * 0xFFFF - Broadcast to all children VFs (only applicable when
36528 * a PF is the requester)
36530 uint16_t encap_async_event_target_id;
36531 uint8_t unused_0[6];
36532 /* This is an encapsulated asynchronous event completion. */
36533 uint32_t encap_async_event_cmpl[4];
36536 /* hwrm_fwd_async_event_cmpl_output (size:128b/16B) */
36537 struct hwrm_fwd_async_event_cmpl_output {
36538 /* The specific error status for the command. */
36539 uint16_t error_code;
36540 /* The HWRM command request type. */
36542 /* The sequence ID from the original command. */
36544 /* The length of the response data in number of bytes. */
36546 uint8_t unused_0[7];
36548 * This field is used in Output records to indicate that the output
36549 * is completely written to RAM. This field should be read as '1'
36550 * to indicate that the output has been completely written.
36551 * When writing a command completion or response to an internal processor,
36552 * the order of writes has to be such that this field is written last.
36557 /**************************
36558 * hwrm_nvm_raw_write_blk *
36559 **************************/
36562 /* hwrm_nvm_raw_write_blk_input (size:256b/32B) */
36563 struct hwrm_nvm_raw_write_blk_input {
36564 /* The HWRM command request type. */
36567 * The completion ring to send the completion event on. This should
36568 * be the NQ ID returned from the `nq_alloc` HWRM command.
36570 uint16_t cmpl_ring;
36572 * The sequence ID is used by the driver for tracking multiple
36573 * commands. This ID is treated as opaque data by the firmware and
36574 * the value is returned in the `hwrm_resp_hdr` upon completion.
36578 * The target ID of the command:
36579 * * 0x0-0xFFF8 - The function ID
36580 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
36581 * * 0xFFFD - Reserved for user-space HWRM interface
36584 uint16_t target_id;
36586 * A physical address pointer pointing to a host buffer that the
36587 * command's response data will be written. This can be either a host
36588 * physical address (HPA) or a guest physical address (GPA) and must
36589 * point to a physically contiguous block of memory.
36591 uint64_t resp_addr;
36593 * 64-bit Host Source Address.
36594 * This is the location of the source data to be written.
36596 uint64_t host_src_addr;
36598 * 32-bit Destination Address.
36599 * This is the NVRAM byte-offset where the source data will be written to.
36601 uint32_t dest_addr;
36602 /* Length of data to be written, in bytes. */
36606 /* hwrm_nvm_raw_write_blk_output (size:128b/16B) */
36607 struct hwrm_nvm_raw_write_blk_output {
36608 /* The specific error status for the command. */
36609 uint16_t error_code;
36610 /* The HWRM command request type. */
36612 /* The sequence ID from the original command. */
36614 /* The length of the response data in number of bytes. */
36616 uint8_t unused_0[7];
36618 * This field is used in Output records to indicate that the output
36619 * is completely written to RAM. This field should be read as '1'
36620 * to indicate that the output has been completely written.
36621 * When writing a command completion or response to an internal processor,
36622 * the order of writes has to be such that this field is written last.
36632 /* hwrm_nvm_read_input (size:320b/40B) */
36633 struct hwrm_nvm_read_input {
36634 /* The HWRM command request type. */
36637 * The completion ring to send the completion event on. This should
36638 * be the NQ ID returned from the `nq_alloc` HWRM command.
36640 uint16_t cmpl_ring;
36642 * The sequence ID is used by the driver for tracking multiple
36643 * commands. This ID is treated as opaque data by the firmware and
36644 * the value is returned in the `hwrm_resp_hdr` upon completion.
36648 * The target ID of the command:
36649 * * 0x0-0xFFF8 - The function ID
36650 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
36651 * * 0xFFFD - Reserved for user-space HWRM interface
36654 uint16_t target_id;
36656 * A physical address pointer pointing to a host buffer that the
36657 * command's response data will be written. This can be either a host
36658 * physical address (HPA) or a guest physical address (GPA) and must
36659 * point to a physically contiguous block of memory.
36661 uint64_t resp_addr;
36663 * 64-bit Host Destination Address.
36664 * This is the host address where the data will be written to.
36666 uint64_t host_dest_addr;
36667 /* The 0-based index of the directory entry. */
36669 uint8_t unused_0[2];
36670 /* The NVRAM byte-offset to read from. */
36672 /* The length of the data to be read, in bytes. */
36674 uint8_t unused_1[4];
36677 /* hwrm_nvm_read_output (size:128b/16B) */
36678 struct hwrm_nvm_read_output {
36679 /* The specific error status for the command. */
36680 uint16_t error_code;
36681 /* The HWRM command request type. */
36683 /* The sequence ID from the original command. */
36685 /* The length of the response data in number of bytes. */
36687 uint8_t unused_0[7];
36689 * This field is used in Output records to indicate that the output
36690 * is completely written to RAM. This field should be read as '1'
36691 * to indicate that the output has been completely written.
36692 * When writing a command completion or response to an internal processor,
36693 * the order of writes has to be such that this field is written last.
36698 /*********************
36699 * hwrm_nvm_raw_dump *
36700 *********************/
36703 /* hwrm_nvm_raw_dump_input (size:256b/32B) */
36704 struct hwrm_nvm_raw_dump_input {
36705 /* The HWRM command request type. */
36708 * The completion ring to send the completion event on. This should
36709 * be the NQ ID returned from the `nq_alloc` HWRM command.
36711 uint16_t cmpl_ring;
36713 * The sequence ID is used by the driver for tracking multiple
36714 * commands. This ID is treated as opaque data by the firmware and
36715 * the value is returned in the `hwrm_resp_hdr` upon completion.
36719 * The target ID of the command:
36720 * * 0x0-0xFFF8 - The function ID
36721 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
36722 * * 0xFFFD - Reserved for user-space HWRM interface
36725 uint16_t target_id;
36727 * A physical address pointer pointing to a host buffer that the
36728 * command's response data will be written. This can be either a host
36729 * physical address (HPA) or a guest physical address (GPA) and must
36730 * point to a physically contiguous block of memory.
36732 uint64_t resp_addr;
36734 * 64-bit Host Destination Address.
36735 * This is the host address where the data will be written to.
36737 uint64_t host_dest_addr;
36738 /* 32-bit NVRAM byte-offset to read from. */
36740 /* Total length of NVRAM contents to be read, in bytes. */
36744 /* hwrm_nvm_raw_dump_output (size:128b/16B) */
36745 struct hwrm_nvm_raw_dump_output {
36746 /* The specific error status for the command. */
36747 uint16_t error_code;
36748 /* The HWRM command request type. */
36750 /* The sequence ID from the original command. */
36752 /* The length of the response data in number of bytes. */
36754 uint8_t unused_0[7];
36756 * This field is used in Output records to indicate that the output
36757 * is completely written to RAM. This field should be read as '1'
36758 * to indicate that the output has been completely written.
36759 * When writing a command completion or response to an internal processor,
36760 * the order of writes has to be such that this field is written last.
36765 /****************************
36766 * hwrm_nvm_get_dir_entries *
36767 ****************************/
36770 /* hwrm_nvm_get_dir_entries_input (size:192b/24B) */
36771 struct hwrm_nvm_get_dir_entries_input {
36772 /* The HWRM command request type. */
36775 * The completion ring to send the completion event on. This should
36776 * be the NQ ID returned from the `nq_alloc` HWRM command.
36778 uint16_t cmpl_ring;
36780 * The sequence ID is used by the driver for tracking multiple
36781 * commands. This ID is treated as opaque data by the firmware and
36782 * the value is returned in the `hwrm_resp_hdr` upon completion.
36786 * The target ID of the command:
36787 * * 0x0-0xFFF8 - The function ID
36788 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
36789 * * 0xFFFD - Reserved for user-space HWRM interface
36792 uint16_t target_id;
36794 * A physical address pointer pointing to a host buffer that the
36795 * command's response data will be written. This can be either a host
36796 * physical address (HPA) or a guest physical address (GPA) and must
36797 * point to a physically contiguous block of memory.
36799 uint64_t resp_addr;
36801 * 64-bit Host Destination Address.
36802 * This is the host address where the directory will be written.
36804 uint64_t host_dest_addr;
36807 /* hwrm_nvm_get_dir_entries_output (size:128b/16B) */
36808 struct hwrm_nvm_get_dir_entries_output {
36809 /* The specific error status for the command. */
36810 uint16_t error_code;
36811 /* The HWRM command request type. */
36813 /* The sequence ID from the original command. */
36815 /* The length of the response data in number of bytes. */
36817 uint8_t unused_0[7];
36819 * This field is used in Output records to indicate that the output
36820 * is completely written to RAM. This field should be read as '1'
36821 * to indicate that the output has been completely written.
36822 * When writing a command completion or response to an internal processor,
36823 * the order of writes has to be such that this field is written last.
36828 /*************************
36829 * hwrm_nvm_get_dir_info *
36830 *************************/
36833 /* hwrm_nvm_get_dir_info_input (size:128b/16B) */
36834 struct hwrm_nvm_get_dir_info_input {
36835 /* The HWRM command request type. */
36838 * The completion ring to send the completion event on. This should
36839 * be the NQ ID returned from the `nq_alloc` HWRM command.
36841 uint16_t cmpl_ring;
36843 * The sequence ID is used by the driver for tracking multiple
36844 * commands. This ID is treated as opaque data by the firmware and
36845 * the value is returned in the `hwrm_resp_hdr` upon completion.
36849 * The target ID of the command:
36850 * * 0x0-0xFFF8 - The function ID
36851 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
36852 * * 0xFFFD - Reserved for user-space HWRM interface
36855 uint16_t target_id;
36857 * A physical address pointer pointing to a host buffer that the
36858 * command's response data will be written. This can be either a host
36859 * physical address (HPA) or a guest physical address (GPA) and must
36860 * point to a physically contiguous block of memory.
36862 uint64_t resp_addr;
36865 /* hwrm_nvm_get_dir_info_output (size:192b/24B) */
36866 struct hwrm_nvm_get_dir_info_output {
36867 /* The specific error status for the command. */
36868 uint16_t error_code;
36869 /* The HWRM command request type. */
36871 /* The sequence ID from the original command. */
36873 /* The length of the response data in number of bytes. */
36875 /* Number of directory entries in the directory. */
36877 /* Size of each directory entry, in bytes. */
36878 uint32_t entry_length;
36879 uint8_t unused_0[7];
36881 * This field is used in Output records to indicate that the output
36882 * is completely written to RAM. This field should be read as '1'
36883 * to indicate that the output has been completely written.
36884 * When writing a command completion or response to an internal processor,
36885 * the order of writes has to be such that this field is written last.
36890 /******************
36892 ******************/
36895 /* hwrm_nvm_write_input (size:384b/48B) */
36896 struct hwrm_nvm_write_input {
36897 /* The HWRM command request type. */
36900 * The completion ring to send the completion event on. This should
36901 * be the NQ ID returned from the `nq_alloc` HWRM command.
36903 uint16_t cmpl_ring;
36905 * The sequence ID is used by the driver for tracking multiple
36906 * commands. This ID is treated as opaque data by the firmware and
36907 * the value is returned in the `hwrm_resp_hdr` upon completion.
36911 * The target ID of the command:
36912 * * 0x0-0xFFF8 - The function ID
36913 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
36914 * * 0xFFFD - Reserved for user-space HWRM interface
36917 uint16_t target_id;
36919 * A physical address pointer pointing to a host buffer that the
36920 * command's response data will be written. This can be either a host
36921 * physical address (HPA) or a guest physical address (GPA) and must
36922 * point to a physically contiguous block of memory.
36924 uint64_t resp_addr;
36926 * 64-bit Host Source Address.
36927 * This is where the source data is.
36929 uint64_t host_src_addr;
36930 /* The Directory Entry Type (valid values are defined in the bnxnvm_directory_type enum defined in the file bnxnvm_defs.h). */
36933 * Directory ordinal.
36934 * The 0-based instance of the combined Directory Entry Type and Extension.
36936 uint16_t dir_ordinal;
36937 /* The Directory Entry Extension flags (see BNX_DIR_EXT_* in the file bnxnvm_defs.h). */
36939 /* Directory Entry Attribute flags (see BNX_DIR_ATTR_* in the file bnxnvm_defs.h). */
36942 * Length of data to write, in bytes. May be less than or equal to the allocated size for the directory entry.
36943 * The data length stored in the directory entry will be updated to reflect this value once the write is complete.
36945 uint32_t dir_data_length;
36950 * When this bit is '1', the original active image
36951 * will not be removed. TBD: what purpose is this?
36953 #define HWRM_NVM_WRITE_INPUT_FLAGS_KEEP_ORIG_ACTIVE_IMG \
36956 * The requested length of the allocated NVM for the item, in bytes. This value may be greater than or equal to the specified data length (dir_data_length).
36957 * If this value is less than the specified data length, it will be ignored.
36958 * The response will contain the actual allocated item length, which may be greater than the requested item length.
36959 * The purpose for allocating more than the required number of bytes for an item's data is to pre-allocate extra storage (padding) to accommodate
36960 * the potential future growth of an item (e.g. upgraded firmware with a size increase, log growth, expanded configuration data).
36962 uint32_t dir_item_length;
36966 /* hwrm_nvm_write_output (size:128b/16B) */
36967 struct hwrm_nvm_write_output {
36968 /* The specific error status for the command. */
36969 uint16_t error_code;
36970 /* The HWRM command request type. */
36972 /* The sequence ID from the original command. */
36974 /* The length of the response data in number of bytes. */
36977 * Length of the allocated NVM for the item, in bytes. The value may be greater than or equal to the specified data length or the requested item length.
36978 * The actual item length used when creating a new directory entry will be a multiple of an NVM block size.
36980 uint32_t dir_item_length;
36981 /* The directory index of the created or modified item. */
36985 * This field is used in Output records to indicate that the output
36986 * is completely written to RAM. This field should be read as '1'
36987 * to indicate that the output has been completely written.
36988 * When writing a command completion or response to an internal processor,
36989 * the order of writes has to be such that this field is written last.
36994 /* hwrm_nvm_write_cmd_err (size:64b/8B) */
36995 struct hwrm_nvm_write_cmd_err {
36997 * command specific error codes that goes to
36998 * the cmd_err field in Common HWRM Error Response.
37001 /* Unknown error */
37002 #define HWRM_NVM_WRITE_CMD_ERR_CODE_UNKNOWN UINT32_C(0x0)
37003 /* Unable to complete operation due to fragmentation */
37004 #define HWRM_NVM_WRITE_CMD_ERR_CODE_FRAG_ERR UINT32_C(0x1)
37005 /* nvm is completely full. */
37006 #define HWRM_NVM_WRITE_CMD_ERR_CODE_NO_SPACE UINT32_C(0x2)
37007 #define HWRM_NVM_WRITE_CMD_ERR_CODE_LAST \
37008 HWRM_NVM_WRITE_CMD_ERR_CODE_NO_SPACE
37009 uint8_t unused_0[7];
37012 /*******************
37013 * hwrm_nvm_modify *
37014 *******************/
37017 /* hwrm_nvm_modify_input (size:320b/40B) */
37018 struct hwrm_nvm_modify_input {
37019 /* The HWRM command request type. */
37022 * The completion ring to send the completion event on. This should
37023 * be the NQ ID returned from the `nq_alloc` HWRM command.
37025 uint16_t cmpl_ring;
37027 * The sequence ID is used by the driver for tracking multiple
37028 * commands. This ID is treated as opaque data by the firmware and
37029 * the value is returned in the `hwrm_resp_hdr` upon completion.
37033 * The target ID of the command:
37034 * * 0x0-0xFFF8 - The function ID
37035 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
37036 * * 0xFFFD - Reserved for user-space HWRM interface
37039 uint16_t target_id;
37041 * A physical address pointer pointing to a host buffer that the
37042 * command's response data will be written. This can be either a host
37043 * physical address (HPA) or a guest physical address (GPA) and must
37044 * point to a physically contiguous block of memory.
37046 uint64_t resp_addr;
37048 * 64-bit Host Source Address.
37049 * This is where the modified data is.
37051 uint64_t host_src_addr;
37052 /* 16-bit directory entry index. */
37056 * This flag indicates the sender wants to modify a continuous NVRAM
37057 * area using a batch of this HWRM requests. The offset of a request
37058 * must be continuous to the end of previous request's. Firmware does
37059 * not update the directory entry until receiving the last request,
37060 * which is indicated by the batch_last flag.
37061 * This flag is set usually when a sender does not have a block of
37062 * memory that is big enough to hold the entire NVRAM data for send
37065 #define HWRM_NVM_MODIFY_INPUT_FLAGS_BATCH_MODE UINT32_C(0x1)
37067 * This flag can be used only when the batch_mode flag is set.
37068 * It indicates this request is the last of batch requests.
37070 #define HWRM_NVM_MODIFY_INPUT_FLAGS_BATCH_LAST UINT32_C(0x2)
37071 /* 32-bit NVRAM byte-offset to modify content from. */
37074 * Length of data to be modified, in bytes. The length shall
37078 uint8_t unused_1[4];
37081 /* hwrm_nvm_modify_output (size:128b/16B) */
37082 struct hwrm_nvm_modify_output {
37083 /* The specific error status for the command. */
37084 uint16_t error_code;
37085 /* The HWRM command request type. */
37087 /* The sequence ID from the original command. */
37089 /* The length of the response data in number of bytes. */
37091 uint8_t unused_0[7];
37093 * This field is used in Output records to indicate that the output
37094 * is completely written to RAM. This field should be read as '1'
37095 * to indicate that the output has been completely written.
37096 * When writing a command completion or response to an internal processor,
37097 * the order of writes has to be such that this field is written last.
37102 /***************************
37103 * hwrm_nvm_find_dir_entry *
37104 ***************************/
37107 /* hwrm_nvm_find_dir_entry_input (size:256b/32B) */
37108 struct hwrm_nvm_find_dir_entry_input {
37109 /* The HWRM command request type. */
37112 * The completion ring to send the completion event on. This should
37113 * be the NQ ID returned from the `nq_alloc` HWRM command.
37115 uint16_t cmpl_ring;
37117 * The sequence ID is used by the driver for tracking multiple
37118 * commands. This ID is treated as opaque data by the firmware and
37119 * the value is returned in the `hwrm_resp_hdr` upon completion.
37123 * The target ID of the command:
37124 * * 0x0-0xFFF8 - The function ID
37125 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
37126 * * 0xFFFD - Reserved for user-space HWRM interface
37129 uint16_t target_id;
37131 * A physical address pointer pointing to a host buffer that the
37132 * command's response data will be written. This can be either a host
37133 * physical address (HPA) or a guest physical address (GPA) and must
37134 * point to a physically contiguous block of memory.
37136 uint64_t resp_addr;
37139 * This bit must be '1' for the dir_idx_valid field to be
37142 #define HWRM_NVM_FIND_DIR_ENTRY_INPUT_ENABLES_DIR_IDX_VALID \
37144 /* Directory Entry Index */
37146 /* Directory Entry (Image) Type */
37149 * Directory ordinal.
37150 * The instance of this Directory Type
37152 uint16_t dir_ordinal;
37153 /* The Directory Entry Extension flags. */
37155 /* This value indicates the search option using dir_ordinal. */
37156 uint8_t opt_ordinal;
37157 /* This value indicates the search option using dir_ordinal. */
37158 #define HWRM_NVM_FIND_DIR_ENTRY_INPUT_OPT_ORDINAL_MASK UINT32_C(0x3)
37159 #define HWRM_NVM_FIND_DIR_ENTRY_INPUT_OPT_ORDINAL_SFT 0
37160 /* Equal to specified ordinal value. */
37161 #define HWRM_NVM_FIND_DIR_ENTRY_INPUT_OPT_ORDINAL_EQ UINT32_C(0x0)
37162 /* Greater than or equal to specified ordinal value */
37163 #define HWRM_NVM_FIND_DIR_ENTRY_INPUT_OPT_ORDINAL_GE UINT32_C(0x1)
37164 /* Greater than specified ordinal value */
37165 #define HWRM_NVM_FIND_DIR_ENTRY_INPUT_OPT_ORDINAL_GT UINT32_C(0x2)
37166 #define HWRM_NVM_FIND_DIR_ENTRY_INPUT_OPT_ORDINAL_LAST \
37167 HWRM_NVM_FIND_DIR_ENTRY_INPUT_OPT_ORDINAL_GT
37168 uint8_t unused_0[3];
37171 /* hwrm_nvm_find_dir_entry_output (size:256b/32B) */
37172 struct hwrm_nvm_find_dir_entry_output {
37173 /* The specific error status for the command. */
37174 uint16_t error_code;
37175 /* The HWRM command request type. */
37177 /* The sequence ID from the original command. */
37179 /* The length of the response data in number of bytes. */
37181 /* Allocated NVRAM for this directory entry, in bytes. */
37182 uint32_t dir_item_length;
37183 /* Size of the stored data for this directory entry, in bytes. */
37184 uint32_t dir_data_length;
37186 * Firmware version.
37187 * Only valid if the directory entry is for embedded firmware stored in APE_BIN Format.
37190 /* Directory ordinal. */
37191 uint16_t dir_ordinal;
37192 /* Directory Entry Index */
37194 uint8_t unused_0[7];
37196 * This field is used in Output records to indicate that the output
37197 * is completely written to RAM. This field should be read as '1'
37198 * to indicate that the output has been completely written.
37199 * When writing a command completion or response to an internal processor,
37200 * the order of writes has to be such that this field is written last.
37205 /****************************
37206 * hwrm_nvm_erase_dir_entry *
37207 ****************************/
37210 /* hwrm_nvm_erase_dir_entry_input (size:192b/24B) */
37211 struct hwrm_nvm_erase_dir_entry_input {
37212 /* The HWRM command request type. */
37215 * The completion ring to send the completion event on. This should
37216 * be the NQ ID returned from the `nq_alloc` HWRM command.
37218 uint16_t cmpl_ring;
37220 * The sequence ID is used by the driver for tracking multiple
37221 * commands. This ID is treated as opaque data by the firmware and
37222 * the value is returned in the `hwrm_resp_hdr` upon completion.
37226 * The target ID of the command:
37227 * * 0x0-0xFFF8 - The function ID
37228 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
37229 * * 0xFFFD - Reserved for user-space HWRM interface
37232 uint16_t target_id;
37234 * A physical address pointer pointing to a host buffer that the
37235 * command's response data will be written. This can be either a host
37236 * physical address (HPA) or a guest physical address (GPA) and must
37237 * point to a physically contiguous block of memory.
37239 uint64_t resp_addr;
37240 /* Directory Entry Index */
37242 uint8_t unused_0[6];
37245 /* hwrm_nvm_erase_dir_entry_output (size:128b/16B) */
37246 struct hwrm_nvm_erase_dir_entry_output {
37247 /* The specific error status for the command. */
37248 uint16_t error_code;
37249 /* The HWRM command request type. */
37251 /* The sequence ID from the original command. */
37253 /* The length of the response data in number of bytes. */
37255 uint8_t unused_0[7];
37257 * This field is used in Output records to indicate that the output
37258 * is completely written to RAM. This field should be read as '1'
37259 * to indicate that the output has been completely written.
37260 * When writing a command completion or response to an internal processor,
37261 * the order of writes has to be such that this field is written last.
37266 /*************************
37267 * hwrm_nvm_get_dev_info *
37268 *************************/
37271 /* hwrm_nvm_get_dev_info_input (size:128b/16B) */
37272 struct hwrm_nvm_get_dev_info_input {
37273 /* The HWRM command request type. */
37276 * The completion ring to send the completion event on. This should
37277 * be the NQ ID returned from the `nq_alloc` HWRM command.
37279 uint16_t cmpl_ring;
37281 * The sequence ID is used by the driver for tracking multiple
37282 * commands. This ID is treated as opaque data by the firmware and
37283 * the value is returned in the `hwrm_resp_hdr` upon completion.
37287 * The target ID of the command:
37288 * * 0x0-0xFFF8 - The function ID
37289 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
37290 * * 0xFFFD - Reserved for user-space HWRM interface
37293 uint16_t target_id;
37295 * A physical address pointer pointing to a host buffer that the
37296 * command's response data will be written. This can be either a host
37297 * physical address (HPA) or a guest physical address (GPA) and must
37298 * point to a physically contiguous block of memory.
37300 uint64_t resp_addr;
37303 /* hwrm_nvm_get_dev_info_output (size:256b/32B) */
37304 struct hwrm_nvm_get_dev_info_output {
37305 /* The specific error status for the command. */
37306 uint16_t error_code;
37307 /* The HWRM command request type. */
37309 /* The sequence ID from the original command. */
37311 /* The length of the response data in number of bytes. */
37313 /* Manufacturer ID. */
37314 uint16_t manufacturer_id;
37316 uint16_t device_id;
37317 /* Sector size of the NVRAM device. */
37318 uint32_t sector_size;
37319 /* Total size, in bytes of the NVRAM device. */
37320 uint32_t nvram_size;
37321 uint32_t reserved_size;
37322 /* Available size that can be used, in bytes. Available size is the NVRAM size take away the used size and reserved size. */
37323 uint32_t available_size;
37324 /* This field represents the major version of NVM cfg */
37325 uint8_t nvm_cfg_ver_maj;
37326 /* This field represents the minor version of NVM cfg */
37327 uint8_t nvm_cfg_ver_min;
37328 /* This field represents the update version of NVM cfg */
37329 uint8_t nvm_cfg_ver_upd;
37331 * This field is used in Output records to indicate that the output
37332 * is completely written to RAM. This field should be read as '1'
37333 * to indicate that the output has been completely written.
37334 * When writing a command completion or response to an internal processor,
37335 * the order of writes has to be such that this field is written last.
37340 /**************************
37341 * hwrm_nvm_mod_dir_entry *
37342 **************************/
37345 /* hwrm_nvm_mod_dir_entry_input (size:256b/32B) */
37346 struct hwrm_nvm_mod_dir_entry_input {
37347 /* The HWRM command request type. */
37350 * The completion ring to send the completion event on. This should
37351 * be the NQ ID returned from the `nq_alloc` HWRM command.
37353 uint16_t cmpl_ring;
37355 * The sequence ID is used by the driver for tracking multiple
37356 * commands. This ID is treated as opaque data by the firmware and
37357 * the value is returned in the `hwrm_resp_hdr` upon completion.
37361 * The target ID of the command:
37362 * * 0x0-0xFFF8 - The function ID
37363 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
37364 * * 0xFFFD - Reserved for user-space HWRM interface
37367 uint16_t target_id;
37369 * A physical address pointer pointing to a host buffer that the
37370 * command's response data will be written. This can be either a host
37371 * physical address (HPA) or a guest physical address (GPA) and must
37372 * point to a physically contiguous block of memory.
37374 uint64_t resp_addr;
37377 * This bit must be '1' for the checksum field to be
37380 #define HWRM_NVM_MOD_DIR_ENTRY_INPUT_ENABLES_CHECKSUM UINT32_C(0x1)
37381 /* Directory Entry Index */
37384 * Directory ordinal.
37385 * The (0-based) instance of this Directory Type.
37387 uint16_t dir_ordinal;
37388 /* The Directory Entry Extension flags (see BNX_DIR_EXT_* for extension flag definitions). */
37390 /* Directory Entry Attribute flags (see BNX_DIR_ATTR_* for attribute flag definitions). */
37393 * If valid, then this field updates the checksum
37394 * value of the content in the directory entry.
37399 /* hwrm_nvm_mod_dir_entry_output (size:128b/16B) */
37400 struct hwrm_nvm_mod_dir_entry_output {
37401 /* The specific error status for the command. */
37402 uint16_t error_code;
37403 /* The HWRM command request type. */
37405 /* The sequence ID from the original command. */
37407 /* The length of the response data in number of bytes. */
37409 uint8_t unused_0[7];
37411 * This field is used in Output records to indicate that the output
37412 * is completely written to RAM. This field should be read as '1'
37413 * to indicate that the output has been completely written.
37414 * When writing a command completion or response to an internal processor,
37415 * the order of writes has to be such that this field is written last.
37420 /**************************
37421 * hwrm_nvm_verify_update *
37422 **************************/
37425 /* hwrm_nvm_verify_update_input (size:192b/24B) */
37426 struct hwrm_nvm_verify_update_input {
37427 /* The HWRM command request type. */
37430 * The completion ring to send the completion event on. This should
37431 * be the NQ ID returned from the `nq_alloc` HWRM command.
37433 uint16_t cmpl_ring;
37435 * The sequence ID is used by the driver for tracking multiple
37436 * commands. This ID is treated as opaque data by the firmware and
37437 * the value is returned in the `hwrm_resp_hdr` upon completion.
37441 * The target ID of the command:
37442 * * 0x0-0xFFF8 - The function ID
37443 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
37444 * * 0xFFFD - Reserved for user-space HWRM interface
37447 uint16_t target_id;
37449 * A physical address pointer pointing to a host buffer that the
37450 * command's response data will be written. This can be either a host
37451 * physical address (HPA) or a guest physical address (GPA) and must
37452 * point to a physically contiguous block of memory.
37454 uint64_t resp_addr;
37455 /* Directory Entry Type, to be verified. */
37458 * Directory ordinal.
37459 * The instance of the Directory Type to be verified.
37461 uint16_t dir_ordinal;
37463 * The Directory Entry Extension flags.
37464 * The "UPDATE" extension flag must be set in this value.
37465 * A corresponding directory entry with the same type and ordinal values but *without*
37466 * the "UPDATE" extension flag must also exist. The other flags of the extension must
37467 * be identical between the active and update entries.
37470 uint8_t unused_0[2];
37473 /* hwrm_nvm_verify_update_output (size:128b/16B) */
37474 struct hwrm_nvm_verify_update_output {
37475 /* The specific error status for the command. */
37476 uint16_t error_code;
37477 /* The HWRM command request type. */
37479 /* The sequence ID from the original command. */
37481 /* The length of the response data in number of bytes. */
37483 uint8_t unused_0[7];
37485 * This field is used in Output records to indicate that the output
37486 * is completely written to RAM. This field should be read as '1'
37487 * to indicate that the output has been completely written.
37488 * When writing a command completion or response to an internal processor,
37489 * the order of writes has to be such that this field is written last.
37494 /***************************
37495 * hwrm_nvm_install_update *
37496 ***************************/
37499 /* hwrm_nvm_install_update_input (size:192b/24B) */
37500 struct hwrm_nvm_install_update_input {
37501 /* The HWRM command request type. */
37504 * The completion ring to send the completion event on. This should
37505 * be the NQ ID returned from the `nq_alloc` HWRM command.
37507 uint16_t cmpl_ring;
37509 * The sequence ID is used by the driver for tracking multiple
37510 * commands. This ID is treated as opaque data by the firmware and
37511 * the value is returned in the `hwrm_resp_hdr` upon completion.
37515 * The target ID of the command:
37516 * * 0x0-0xFFF8 - The function ID
37517 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
37518 * * 0xFFFD - Reserved for user-space HWRM interface
37521 uint16_t target_id;
37523 * A physical address pointer pointing to a host buffer that the
37524 * command's response data will be written. This can be either a host
37525 * physical address (HPA) or a guest physical address (GPA) and must
37526 * point to a physically contiguous block of memory.
37528 uint64_t resp_addr;
37530 * Installation type. If the value 3 through 0xffff is used,
37531 * only packaged items with that type value will be installed and
37532 * conditional installation directives for those packaged items
37533 * will be over-ridden (i.e. 'create' or 'replace' will be treated
37536 uint32_t install_type;
37538 * Perform a normal package installation. Conditional installation
37539 * directives (e.g. 'create' and 'replace') of packaged items
37540 * will be followed.
37542 #define HWRM_NVM_INSTALL_UPDATE_INPUT_INSTALL_TYPE_NORMAL UINT32_C(0x0)
37544 * Install all packaged items regardless of installation directive
37545 * (i.e. treat all packaged items as though they have an installation
37546 * directive of 'install').
37548 #define HWRM_NVM_INSTALL_UPDATE_INPUT_INSTALL_TYPE_ALL \
37549 UINT32_C(0xffffffff)
37550 #define HWRM_NVM_INSTALL_UPDATE_INPUT_INSTALL_TYPE_LAST \
37551 HWRM_NVM_INSTALL_UPDATE_INPUT_INSTALL_TYPE_ALL
37553 /* If set to 1, then securely erase all unused locations in persistent storage. */
37554 #define HWRM_NVM_INSTALL_UPDATE_INPUT_FLAGS_ERASE_UNUSED_SPACE \
37557 * If set to 1, then unspecified images, images not in the package file, will be safely deleted.
37558 * When combined with erase_unused_space then unspecified images will be securely erased.
37560 #define HWRM_NVM_INSTALL_UPDATE_INPUT_FLAGS_REMOVE_UNUSED_PKG \
37563 * If set to 1, FW will defragment the NVM if defragmentation is required for the update.
37564 * Allow additional time for this command to complete if this bit is set to 1.
37566 #define HWRM_NVM_INSTALL_UPDATE_INPUT_FLAGS_ALLOWED_TO_DEFRAG \
37568 uint8_t unused_0[2];
37571 /* hwrm_nvm_install_update_output (size:192b/24B) */
37572 struct hwrm_nvm_install_update_output {
37573 /* The specific error status for the command. */
37574 uint16_t error_code;
37575 /* The HWRM command request type. */
37577 /* The sequence ID from the original command. */
37579 /* The length of the response data in number of bytes. */
37582 * Bit-mask of successfully installed items.
37583 * Bit-0 corresponding to the first packaged item, Bit-1 for the second item, etc.
37584 * A value of 0 indicates that no items were successfully installed.
37586 uint64_t installed_items;
37587 /* result is 8 b */
37589 /* There was no problem with the package installation. */
37590 #define HWRM_NVM_INSTALL_UPDATE_OUTPUT_RESULT_SUCCESS UINT32_C(0x0)
37591 #define HWRM_NVM_INSTALL_UPDATE_OUTPUT_RESULT_LAST \
37592 HWRM_NVM_INSTALL_UPDATE_OUTPUT_RESULT_SUCCESS
37593 /* problem_item is 8 b */
37594 uint8_t problem_item;
37595 /* There was no problem with any packaged items. */
37596 #define HWRM_NVM_INSTALL_UPDATE_OUTPUT_PROBLEM_ITEM_NONE \
37598 /* There was a problem with the NVM package itself. */
37599 #define HWRM_NVM_INSTALL_UPDATE_OUTPUT_PROBLEM_ITEM_PACKAGE \
37601 #define HWRM_NVM_INSTALL_UPDATE_OUTPUT_PROBLEM_ITEM_LAST \
37602 HWRM_NVM_INSTALL_UPDATE_OUTPUT_PROBLEM_ITEM_PACKAGE
37603 /* reset_required is 8 b */
37604 uint8_t reset_required;
37606 * No reset is required for installed/updated firmware or
37607 * microcode to take effect.
37609 #define HWRM_NVM_INSTALL_UPDATE_OUTPUT_RESET_REQUIRED_NONE \
37612 * A PCIe reset (e.g. system reboot) is
37613 * required for newly installed/updated firmware or
37614 * microcode to take effect.
37616 #define HWRM_NVM_INSTALL_UPDATE_OUTPUT_RESET_REQUIRED_PCI \
37619 * A controller power reset (e.g. system power-cycle) is
37620 * required for newly installed/updated firmware or
37621 * microcode to take effect. Some newly installed/updated
37622 * firmware or microcode may still take effect upon the
37625 #define HWRM_NVM_INSTALL_UPDATE_OUTPUT_RESET_REQUIRED_POWER \
37627 #define HWRM_NVM_INSTALL_UPDATE_OUTPUT_RESET_REQUIRED_LAST \
37628 HWRM_NVM_INSTALL_UPDATE_OUTPUT_RESET_REQUIRED_POWER
37629 uint8_t unused_0[4];
37631 * This field is used in Output records to indicate that the output
37632 * is completely written to RAM. This field should be read as '1'
37633 * to indicate that the output has been completely written.
37634 * When writing a command completion or response to an internal processor,
37635 * the order of writes has to be such that this field is written last.
37640 /* hwrm_nvm_install_update_cmd_err (size:64b/8B) */
37641 struct hwrm_nvm_install_update_cmd_err {
37643 * command specific error codes that goes to
37644 * the cmd_err field in Common HWRM Error Response.
37647 /* Unknown error */
37648 #define HWRM_NVM_INSTALL_UPDATE_CMD_ERR_CODE_UNKNOWN UINT32_C(0x0)
37649 /* Unable to complete operation due to fragmentation */
37650 #define HWRM_NVM_INSTALL_UPDATE_CMD_ERR_CODE_FRAG_ERR UINT32_C(0x1)
37651 /* nvm is completely full. */
37652 #define HWRM_NVM_INSTALL_UPDATE_CMD_ERR_CODE_NO_SPACE UINT32_C(0x2)
37653 #define HWRM_NVM_INSTALL_UPDATE_CMD_ERR_CODE_LAST \
37654 HWRM_NVM_INSTALL_UPDATE_CMD_ERR_CODE_NO_SPACE
37655 uint8_t unused_0[7];
37658 /******************
37660 ******************/
37663 /* hwrm_nvm_flush_input (size:128b/16B) */
37664 struct hwrm_nvm_flush_input {
37665 /* The HWRM command request type. */
37668 * The completion ring to send the completion event on. This should
37669 * be the NQ ID returned from the `nq_alloc` HWRM command.
37671 uint16_t cmpl_ring;
37673 * The sequence ID is used by the driver for tracking multiple
37674 * commands. This ID is treated as opaque data by the firmware and
37675 * the value is returned in the `hwrm_resp_hdr` upon completion.
37679 * The target ID of the command:
37680 * * 0x0-0xFFF8 - The function ID
37681 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
37682 * * 0xFFFD - Reserved for user-space HWRM interface
37685 uint16_t target_id;
37687 * A physical address pointer pointing to a host buffer that the
37688 * command's response data will be written. This can be either a host
37689 * physical address (HPA) or a guest physical address (GPA) and must
37690 * point to a physically contiguous block of memory.
37692 uint64_t resp_addr;
37695 /* hwrm_nvm_flush_output (size:128b/16B) */
37696 struct hwrm_nvm_flush_output {
37697 /* The specific error status for the command. */
37698 uint16_t error_code;
37699 /* The HWRM command request type. */
37701 /* The sequence ID from the original command. */
37703 /* The length of the response data in number of bytes. */
37705 uint8_t unused_0[7];
37707 * This field is used in Output records to indicate that the output
37708 * is completely written to RAM. This field should be read as '1'
37709 * to indicate that the output has been completely written.
37710 * When writing a command completion or response to an internal processor,
37711 * the order of writes has to be such that this field is written last.
37716 /* hwrm_nvm_flush_cmd_err (size:64b/8B) */
37717 struct hwrm_nvm_flush_cmd_err {
37719 * command specific error codes that goes to
37720 * the cmd_err field in Common HWRM Error Response.
37723 /* Unknown error */
37724 #define HWRM_NVM_FLUSH_CMD_ERR_CODE_UNKNOWN UINT32_C(0x0)
37725 /* flush could not be performed */
37726 #define HWRM_NVM_FLUSH_CMD_ERR_CODE_FAIL UINT32_C(0x1)
37727 #define HWRM_NVM_FLUSH_CMD_ERR_CODE_LAST \
37728 HWRM_NVM_FLUSH_CMD_ERR_CODE_FAIL
37729 uint8_t unused_0[7];
37732 /*************************
37733 * hwrm_nvm_get_variable *
37734 *************************/
37737 /* hwrm_nvm_get_variable_input (size:320b/40B) */
37738 struct hwrm_nvm_get_variable_input {
37739 /* The HWRM command request type. */
37742 * The completion ring to send the completion event on. This should
37743 * be the NQ ID returned from the `nq_alloc` HWRM command.
37745 uint16_t cmpl_ring;
37747 * The sequence ID is used by the driver for tracking multiple
37748 * commands. This ID is treated as opaque data by the firmware and
37749 * the value is returned in the `hwrm_resp_hdr` upon completion.
37753 * The target ID of the command:
37754 * * 0x0-0xFFF8 - The function ID
37755 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
37756 * * 0xFFFD - Reserved for user-space HWRM interface
37759 uint16_t target_id;
37761 * A physical address pointer pointing to a host buffer that the
37762 * command's response data will be written. This can be either a host
37763 * physical address (HPA) or a guest physical address (GPA) and must
37764 * point to a physically contiguous block of memory.
37766 uint64_t resp_addr;
37768 * This is the host address where
37769 * nvm variable will be stored
37771 uint64_t dest_data_addr;
37772 /* size of data in bits */
37774 /* nvm cfg option number */
37775 uint16_t option_num;
37777 #define HWRM_NVM_GET_VARIABLE_INPUT_OPTION_NUM_RSVD_0 UINT32_C(0x0)
37779 #define HWRM_NVM_GET_VARIABLE_INPUT_OPTION_NUM_RSVD_FFFF \
37781 #define HWRM_NVM_GET_VARIABLE_INPUT_OPTION_NUM_LAST \
37782 HWRM_NVM_GET_VARIABLE_INPUT_OPTION_NUM_RSVD_FFFF
37784 * Number of dimensions for this nvm configuration variable.
37785 * This value indicates how many of the indexN values to use.
37786 * A value of 0 means that none of the indexN values are valid.
37787 * A value of 1 requires at index0 is valued, a value of 2
37788 * requires that index0 and index1 are valid, and so forth
37790 uint16_t dimensions;
37791 /* index for the 1st dimensions */
37793 /* index for the 2nd dimensions */
37795 /* index for the 3rd dimensions */
37797 /* index for the 4th dimensions */
37801 * When this bit is set to 1, the factory default value will be returned,
37802 * 0 returns the operational value.
37804 #define HWRM_NVM_GET_VARIABLE_INPUT_FLAGS_FACTORY_DFLT \
37809 /* hwrm_nvm_get_variable_output (size:128b/16B) */
37810 struct hwrm_nvm_get_variable_output {
37811 /* The specific error status for the command. */
37812 uint16_t error_code;
37813 /* The HWRM command request type. */
37815 /* The sequence ID from the original command. */
37817 /* The length of the response data in number of bytes. */
37819 /* size of data of the actual variable retrieved in bits */
37822 * option_num is the option number for the data retrieved. It is possible in the
37823 * future that the option number returned would be different than requested. This
37824 * condition could occur if an option is deprecated and a new option id is defined
37825 * with similar characteristics, but has a slightly different definition. This
37826 * also makes it convenient for the caller to identify the variable result with
37827 * the option id from the response.
37829 uint16_t option_num;
37831 #define HWRM_NVM_GET_VARIABLE_OUTPUT_OPTION_NUM_RSVD_0 UINT32_C(0x0)
37833 #define HWRM_NVM_GET_VARIABLE_OUTPUT_OPTION_NUM_RSVD_FFFF \
37835 #define HWRM_NVM_GET_VARIABLE_OUTPUT_OPTION_NUM_LAST \
37836 HWRM_NVM_GET_VARIABLE_OUTPUT_OPTION_NUM_RSVD_FFFF
37837 uint8_t unused_0[3];
37839 * This field is used in Output records to indicate that the output
37840 * is completely written to RAM. This field should be read as '1'
37841 * to indicate that the output has been completely written.
37842 * When writing a command completion or response to an internal processor,
37843 * the order of writes has to be such that this field is written last.
37848 /* hwrm_nvm_get_variable_cmd_err (size:64b/8B) */
37849 struct hwrm_nvm_get_variable_cmd_err {
37851 * command specific error codes that goes to
37852 * the cmd_err field in Common HWRM Error Response.
37855 /* Unknown error */
37856 #define HWRM_NVM_GET_VARIABLE_CMD_ERR_CODE_UNKNOWN UINT32_C(0x0)
37857 /* variable does not exist */
37858 #define HWRM_NVM_GET_VARIABLE_CMD_ERR_CODE_VAR_NOT_EXIST UINT32_C(0x1)
37859 /* configuration is corrupted and the variable cannot be saved */
37860 #define HWRM_NVM_GET_VARIABLE_CMD_ERR_CODE_CORRUPT_VAR UINT32_C(0x2)
37861 /* length specified is too small */
37862 #define HWRM_NVM_GET_VARIABLE_CMD_ERR_CODE_LEN_TOO_SHORT UINT32_C(0x3)
37863 #define HWRM_NVM_GET_VARIABLE_CMD_ERR_CODE_LAST \
37864 HWRM_NVM_GET_VARIABLE_CMD_ERR_CODE_LEN_TOO_SHORT
37865 uint8_t unused_0[7];
37868 /*************************
37869 * hwrm_nvm_set_variable *
37870 *************************/
37873 /* hwrm_nvm_set_variable_input (size:320b/40B) */
37874 struct hwrm_nvm_set_variable_input {
37875 /* The HWRM command request type. */
37878 * The completion ring to send the completion event on. This should
37879 * be the NQ ID returned from the `nq_alloc` HWRM command.
37881 uint16_t cmpl_ring;
37883 * The sequence ID is used by the driver for tracking multiple
37884 * commands. This ID is treated as opaque data by the firmware and
37885 * the value is returned in the `hwrm_resp_hdr` upon completion.
37889 * The target ID of the command:
37890 * * 0x0-0xFFF8 - The function ID
37891 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
37892 * * 0xFFFD - Reserved for user-space HWRM interface
37895 uint16_t target_id;
37897 * A physical address pointer pointing to a host buffer that the
37898 * command's response data will be written. This can be either a host
37899 * physical address (HPA) or a guest physical address (GPA) and must
37900 * point to a physically contiguous block of memory.
37902 uint64_t resp_addr;
37904 * This is the host address where
37905 * nvm variable will be copied from
37907 uint64_t src_data_addr;
37908 /* size of data in bits */
37910 /* nvm cfg option number */
37911 uint16_t option_num;
37913 #define HWRM_NVM_SET_VARIABLE_INPUT_OPTION_NUM_RSVD_0 UINT32_C(0x0)
37915 #define HWRM_NVM_SET_VARIABLE_INPUT_OPTION_NUM_RSVD_FFFF \
37917 #define HWRM_NVM_SET_VARIABLE_INPUT_OPTION_NUM_LAST \
37918 HWRM_NVM_SET_VARIABLE_INPUT_OPTION_NUM_RSVD_FFFF
37920 * Number of dimensions for this nvm configuration variable.
37921 * This value indicates how many of the indexN values to use.
37922 * A value of 0 means that none of the indexN values are valid.
37923 * A value of 1 requires at index0 is valued, a value of 2
37924 * requires that index0 and index1 are valid, and so forth
37926 uint16_t dimensions;
37927 /* index for the 1st dimensions */
37929 /* index for the 2nd dimensions */
37931 /* index for the 3rd dimensions */
37933 /* index for the 4th dimensions */
37936 /* When this bit is 1, flush internal cache after this write operation (see hwrm_nvm_flush command.) */
37937 #define HWRM_NVM_SET_VARIABLE_INPUT_FLAGS_FORCE_FLUSH \
37939 /* encryption method */
37940 #define HWRM_NVM_SET_VARIABLE_INPUT_FLAGS_ENCRYPT_MODE_MASK \
37942 #define HWRM_NVM_SET_VARIABLE_INPUT_FLAGS_ENCRYPT_MODE_SFT 1
37943 /* No encryption. */
37944 #define HWRM_NVM_SET_VARIABLE_INPUT_FLAGS_ENCRYPT_MODE_NONE \
37945 (UINT32_C(0x0) << 1)
37946 /* one-way encryption. */
37947 #define HWRM_NVM_SET_VARIABLE_INPUT_FLAGS_ENCRYPT_MODE_HMAC_SHA1 \
37948 (UINT32_C(0x1) << 1)
37949 /* symmetric AES256 encryption. */
37950 #define HWRM_NVM_SET_VARIABLE_INPUT_FLAGS_ENCRYPT_MODE_AES256 \
37951 (UINT32_C(0x2) << 1)
37952 /* SHA1 digest appended to plaintext contents, for authentication */
37953 #define HWRM_NVM_SET_VARIABLE_INPUT_FLAGS_ENCRYPT_MODE_HMAC_SHA1_AUTH \
37954 (UINT32_C(0x3) << 1)
37955 #define HWRM_NVM_SET_VARIABLE_INPUT_FLAGS_ENCRYPT_MODE_LAST \
37956 HWRM_NVM_SET_VARIABLE_INPUT_FLAGS_ENCRYPT_MODE_HMAC_SHA1_AUTH
37957 #define HWRM_NVM_SET_VARIABLE_INPUT_FLAGS_FLAGS_UNUSED_0_MASK \
37959 #define HWRM_NVM_SET_VARIABLE_INPUT_FLAGS_FLAGS_UNUSED_0_SFT 4
37960 /* When this bit is 1, update the factory default region */
37961 #define HWRM_NVM_SET_VARIABLE_INPUT_FLAGS_FACTORY_DEFAULT \
37966 /* hwrm_nvm_set_variable_output (size:128b/16B) */
37967 struct hwrm_nvm_set_variable_output {
37968 /* The specific error status for the command. */
37969 uint16_t error_code;
37970 /* The HWRM command request type. */
37972 /* The sequence ID from the original command. */
37974 /* The length of the response data in number of bytes. */
37976 uint8_t unused_0[7];
37978 * This field is used in Output records to indicate that the output
37979 * is completely written to RAM. This field should be read as '1'
37980 * to indicate that the output has been completely written.
37981 * When writing a command completion or response to an internal processor,
37982 * the order of writes has to be such that this field is written last.
37987 /* hwrm_nvm_set_variable_cmd_err (size:64b/8B) */
37988 struct hwrm_nvm_set_variable_cmd_err {
37990 * command specific error codes that goes to
37991 * the cmd_err field in Common HWRM Error Response.
37994 /* Unknown error */
37995 #define HWRM_NVM_SET_VARIABLE_CMD_ERR_CODE_UNKNOWN UINT32_C(0x0)
37996 /* variable does not exist */
37997 #define HWRM_NVM_SET_VARIABLE_CMD_ERR_CODE_VAR_NOT_EXIST UINT32_C(0x1)
37998 /* configuration is corrupted and the variable cannot be saved */
37999 #define HWRM_NVM_SET_VARIABLE_CMD_ERR_CODE_CORRUPT_VAR UINT32_C(0x2)
38000 #define HWRM_NVM_SET_VARIABLE_CMD_ERR_CODE_LAST \
38001 HWRM_NVM_SET_VARIABLE_CMD_ERR_CODE_CORRUPT_VAR
38002 uint8_t unused_0[7];
38005 /****************************
38006 * hwrm_nvm_validate_option *
38007 ****************************/
38010 /* hwrm_nvm_validate_option_input (size:320b/40B) */
38011 struct hwrm_nvm_validate_option_input {
38012 /* The HWRM command request type. */
38015 * The completion ring to send the completion event on. This should
38016 * be the NQ ID returned from the `nq_alloc` HWRM command.
38018 uint16_t cmpl_ring;
38020 * The sequence ID is used by the driver for tracking multiple
38021 * commands. This ID is treated as opaque data by the firmware and
38022 * the value is returned in the `hwrm_resp_hdr` upon completion.
38026 * The target ID of the command:
38027 * * 0x0-0xFFF8 - The function ID
38028 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
38029 * * 0xFFFD - Reserved for user-space HWRM interface
38032 uint16_t target_id;
38034 * A physical address pointer pointing to a host buffer that the
38035 * command's response data will be written. This can be either a host
38036 * physical address (HPA) or a guest physical address (GPA) and must
38037 * point to a physically contiguous block of memory.
38039 uint64_t resp_addr;
38041 * This is the host address where
38042 * nvm variable will be copied from
38044 uint64_t src_data_addr;
38045 /* size of data in bits */
38047 /* nvm cfg option number */
38048 uint16_t option_num;
38050 #define HWRM_NVM_VALIDATE_OPTION_INPUT_OPTION_NUM_RSVD_0 \
38053 #define HWRM_NVM_VALIDATE_OPTION_INPUT_OPTION_NUM_RSVD_FFFF \
38055 #define HWRM_NVM_VALIDATE_OPTION_INPUT_OPTION_NUM_LAST \
38056 HWRM_NVM_VALIDATE_OPTION_INPUT_OPTION_NUM_RSVD_FFFF
38058 * Number of dimensions for this nvm configuration variable.
38059 * This value indicates how many of the indexN values to use.
38060 * A value of 0 means that none of the indexN values are valid.
38061 * A value of 1 requires at index0 is valued, a value of 2
38062 * requires that index0 and index1 are valid, and so forth
38064 uint16_t dimensions;
38065 /* index for the 1st dimensions */
38067 /* index for the 2nd dimensions */
38069 /* index for the 3rd dimensions */
38071 /* index for the 4th dimensions */
38073 uint8_t unused_0[2];
38076 /* hwrm_nvm_validate_option_output (size:128b/16B) */
38077 struct hwrm_nvm_validate_option_output {
38078 /* The specific error status for the command. */
38079 uint16_t error_code;
38080 /* The HWRM command request type. */
38082 /* The sequence ID from the original command. */
38084 /* The length of the response data in number of bytes. */
38087 /* indicates that the value provided for the option is not matching with the saved data. */
38088 #define HWRM_NVM_VALIDATE_OPTION_OUTPUT_RESULT_NOT_MATCH UINT32_C(0x0)
38089 /* indicates that the value provided for the option is matching the saved data. */
38090 #define HWRM_NVM_VALIDATE_OPTION_OUTPUT_RESULT_MATCH UINT32_C(0x1)
38091 #define HWRM_NVM_VALIDATE_OPTION_OUTPUT_RESULT_LAST \
38092 HWRM_NVM_VALIDATE_OPTION_OUTPUT_RESULT_MATCH
38093 uint8_t unused_0[6];
38095 * This field is used in Output records to indicate that the output
38096 * is completely written to RAM. This field should be read as '1'
38097 * to indicate that the output has been completely written.
38098 * When writing a command completion or response to an internal processor,
38099 * the order of writes has to be such that this field is written last.
38104 /* hwrm_nvm_validate_option_cmd_err (size:64b/8B) */
38105 struct hwrm_nvm_validate_option_cmd_err {
38107 * command specific error codes that goes to
38108 * the cmd_err field in Common HWRM Error Response.
38111 /* Unknown error */
38112 #define HWRM_NVM_VALIDATE_OPTION_CMD_ERR_CODE_UNKNOWN UINT32_C(0x0)
38113 #define HWRM_NVM_VALIDATE_OPTION_CMD_ERR_CODE_LAST \
38114 HWRM_NVM_VALIDATE_OPTION_CMD_ERR_CODE_UNKNOWN
38115 uint8_t unused_0[7];
38120 ******************/
38123 /* hwrm_fw_reset_input (size:192b/24B) */
38124 struct hwrm_fw_reset_input {
38125 /* The HWRM command request type. */
38128 * The completion ring to send the completion event on. This should
38129 * be the NQ ID returned from the `nq_alloc` HWRM command.
38131 uint16_t cmpl_ring;
38133 * The sequence ID is used by the driver for tracking multiple
38134 * commands. This ID is treated as opaque data by the firmware and
38135 * the value is returned in the `hwrm_resp_hdr` upon completion.
38139 * The target ID of the command:
38140 * * 0x0-0xFFF8 - The function ID
38141 * * 0xFFF8-0xFFFE - Reserved for internal processors
38144 uint16_t target_id;
38146 * A physical address pointer pointing to a host buffer that the
38147 * command's response data will be written. This can be either a host
38148 * physical address (HPA) or a guest physical address (GPA) and must
38149 * point to a physically contiguous block of memory.
38151 uint64_t resp_addr;
38152 /* Type of embedded processor. */
38153 uint8_t embedded_proc_type;
38154 /* Boot Processor */
38155 #define HWRM_FW_RESET_INPUT_EMBEDDED_PROC_TYPE_BOOT \
38157 /* Management Processor */
38158 #define HWRM_FW_RESET_INPUT_EMBEDDED_PROC_TYPE_MGMT \
38160 /* Network control processor */
38161 #define HWRM_FW_RESET_INPUT_EMBEDDED_PROC_TYPE_NETCTRL \
38163 /* RoCE control processor */
38164 #define HWRM_FW_RESET_INPUT_EMBEDDED_PROC_TYPE_ROCE \
38167 * Host (in multi-host environment): This is only valid if requester is IPC.
38168 * Reinit host hardware resources and PCIe.
38170 #define HWRM_FW_RESET_INPUT_EMBEDDED_PROC_TYPE_HOST \
38172 /* AP processor complex (in multi-host environment). Use host_idx to control which core is reset */
38173 #define HWRM_FW_RESET_INPUT_EMBEDDED_PROC_TYPE_AP \
38175 /* Reset all blocks of the chip (including all processors) */
38176 #define HWRM_FW_RESET_INPUT_EMBEDDED_PROC_TYPE_CHIP \
38179 * Host (in multi-host environment): This is only valid if requester is IPC.
38180 * Reinit host hardware resources.
38182 #define HWRM_FW_RESET_INPUT_EMBEDDED_PROC_TYPE_HOST_RESOURCE_REINIT \
38184 #define HWRM_FW_RESET_INPUT_EMBEDDED_PROC_TYPE_LAST \
38185 HWRM_FW_RESET_INPUT_EMBEDDED_PROC_TYPE_HOST_RESOURCE_REINIT
38186 /* Type of self reset. */
38187 uint8_t selfrst_status;
38188 /* No Self Reset */
38189 #define HWRM_FW_RESET_INPUT_SELFRST_STATUS_SELFRSTNONE \
38191 /* Self Reset as soon as possible to do so safely */
38192 #define HWRM_FW_RESET_INPUT_SELFRST_STATUS_SELFRSTASAP \
38194 /* Self Reset on PCIe Reset */
38195 #define HWRM_FW_RESET_INPUT_SELFRST_STATUS_SELFRSTPCIERST \
38197 /* Self Reset immediately after notification to all clients. */
38198 #define HWRM_FW_RESET_INPUT_SELFRST_STATUS_SELFRSTIMMEDIATE \
38200 #define HWRM_FW_RESET_INPUT_SELFRST_STATUS_LAST \
38201 HWRM_FW_RESET_INPUT_SELFRST_STATUS_SELFRSTIMMEDIATE
38203 * Indicate which host is being reset. 0 means first host.
38204 * Only valid when embedded_proc_type is host in multihost
38210 * When this bit is '1', then the core firmware initiates
38211 * the reset only after graceful shut down of all registered instances.
38212 * If not, the device will continue with the existing firmware.
38214 #define HWRM_FW_RESET_INPUT_FLAGS_RESET_GRACEFUL UINT32_C(0x1)
38215 uint8_t unused_0[4];
38218 /* hwrm_fw_reset_output (size:128b/16B) */
38219 struct hwrm_fw_reset_output {
38220 /* The specific error status for the command. */
38221 uint16_t error_code;
38222 /* The HWRM command request type. */
38224 /* The sequence ID from the original command. */
38226 /* The length of the response data in number of bytes. */
38228 /* Type of self reset. */
38229 uint8_t selfrst_status;
38230 /* No Self Reset */
38231 #define HWRM_FW_RESET_OUTPUT_SELFRST_STATUS_SELFRSTNONE \
38233 /* Self Reset as soon as possible to do so safely */
38234 #define HWRM_FW_RESET_OUTPUT_SELFRST_STATUS_SELFRSTASAP \
38236 /* Self Reset on PCIe Reset */
38237 #define HWRM_FW_RESET_OUTPUT_SELFRST_STATUS_SELFRSTPCIERST \
38239 /* Self Reset immediately after notification to all clients. */
38240 #define HWRM_FW_RESET_OUTPUT_SELFRST_STATUS_SELFRSTIMMEDIATE \
38242 #define HWRM_FW_RESET_OUTPUT_SELFRST_STATUS_LAST \
38243 HWRM_FW_RESET_OUTPUT_SELFRST_STATUS_SELFRSTIMMEDIATE
38244 uint8_t unused_0[6];
38246 * This field is used in Output records to indicate that the output
38247 * is completely written to RAM. This field should be read as '1'
38248 * to indicate that the output has been completely written.
38249 * When writing a command completion or response to an internal processor,
38250 * the order of writes has to be such that this field is written last.
38255 /**********************
38256 * hwrm_port_ts_query *
38257 ***********************/
38260 /* hwrm_port_ts_query_input (size:192b/24B) */
38261 struct hwrm_port_ts_query_input {
38262 /* The HWRM command request type. */
38265 * The completion ring to send the completion event on. This should
38266 * be the NQ ID returned from the `nq_alloc` HWRM command.
38268 uint16_t cmpl_ring;
38270 * The sequence ID is used by the driver for tracking multiple
38271 * commands. This ID is treated as opaque data by the firmware and
38272 * the value is returned in the `hwrm_resp_hdr` upon completion.
38276 * The target ID of the command:
38277 * * 0x0-0xFFF8 - The function ID
38278 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
38279 * * 0xFFFD - Reserved for user-space HWRM interface
38282 uint16_t target_id;
38284 * A physical address pointer pointing to a host buffer that the
38285 * command's response data will be written. This can be either a host
38286 * physical address (HPA) or a guest physical address (GPA) and must
38287 * point to a physically contiguous block of memory.
38289 uint64_t resp_addr;
38292 * Enumeration denoting the RX, TX type of the resource.
38293 * This enumeration is used for resources that are similar for both
38294 * TX and RX paths of the chip.
38296 #define HWRM_PORT_TS_QUERY_INPUT_FLAGS_PATH 0x1UL
38298 #define HWRM_PORT_TS_QUERY_INPUT_FLAGS_PATH_TX 0x0UL
38300 #define HWRM_PORT_TS_QUERY_INPUT_FLAGS_PATH_RX 0x1UL
38301 #define HWRM_PORT_TS_QUERY_INPUT_FLAGS_PATH_LAST \
38302 HWRM_PORT_TS_QUERY_INPUT_FLAGS_PATH_RX
38304 * If set, the response includes the current value of the free
38307 #define HWRM_PORT_TS_QUERY_INPUT_FLAGS_CURRENT_TIME 0x2UL
38308 /* Port ID of port that is being queried. */
38310 uint8_t unused_0[2];
38313 /* hwrm_port_ts_query_output (size:192b/24B) */
38314 struct hwrm_port_ts_query_output {
38315 /* The specific error status for the command. */
38316 uint16_t error_code;
38317 /* The HWRM command request type. */
38319 /* The sequence ID from the original command. */
38321 /* The length of the response data in number of bytes. */
38324 * Timestamp value of PTP message captured, or current value of
38325 * free running timer.
38327 uint32_t ptp_msg_ts[2];
38328 /* Sequence ID of the PTP message captured. */
38329 uint16_t ptp_msg_seqid;
38330 uint8_t unused_0[5];
38332 * This field is used in Output records to indicate that the output
38333 * is completely written to RAM. This field should be read as '1'
38334 * to indicate that the output has been completely written.
38335 * When writing a command completion or response to an internal processor,
38336 * the order of writes has to be such that this field is written last.
38341 /**************************
38342 * hwrm_cfa_counter_qcaps *
38343 **************************/
38346 /* hwrm_cfa_counter_qcaps_input (size:128b/16B) */
38347 struct hwrm_cfa_counter_qcaps_input {
38348 /* The HWRM command request type. */
38351 * The completion ring to send the completion event on. This should
38352 * be the NQ ID returned from the `nq_alloc` HWRM command.
38354 uint16_t cmpl_ring;
38356 * The sequence ID is used by the driver for tracking multiple
38357 * commands. This ID is treated as opaque data by the firmware and
38358 * the value is returned in the `hwrm_resp_hdr` upon completion.
38362 * The target ID of the command:
38363 * * 0x0-0xFFF8 - The function ID
38364 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
38365 * * 0xFFFD - Reserved for user-space HWRM interface
38368 uint16_t target_id;
38370 * A physical address pointer pointing to a host buffer that the
38371 * command's response data will be written. This can be either a host
38372 * physical address (HPA) or a guest physical address (GPA) and must
38373 * point to a physically contiguous block of memory.
38375 uint64_t resp_addr;
38378 /* hwrm_cfa_counter_qcaps_output (size:576b/72B) */
38379 struct hwrm_cfa_counter_qcaps_output {
38380 /* The specific error status for the command. */
38381 uint16_t error_code;
38382 /* The HWRM command request type. */
38384 /* The sequence ID from the original command. */
38386 /* The length of the response data in number of bytes. */
38389 /* Enumeration denoting the supported CFA counter format. */
38390 #define HWRM_CFA_COUNTER_QCAPS_OUTPUT_FLAGS_COUNTER_FORMAT \
38392 /* CFA counter types are not supported. */
38393 #define HWRM_CFA_COUNTER_QCAPS_OUTPUT_FLAGS_COUNTER_FORMAT_NONE \
38395 /* 64-bit packet counters followed by 64-bit byte counters format. */
38396 #define HWRM_CFA_COUNTER_QCAPS_OUTPUT_FLAGS_COUNTER_FORMAT_64_BIT \
38398 #define HWRM_CFA_COUNTER_QCAPS_OUTPUT_FLAGS_COUNTER_FORMAT_LAST \
38399 HWRM_CFA_COUNTER_QCAPS_OUTPUT_FLAGS_COUNTER_FORMAT_64_BIT
38401 /* Minimum guaranteed number of flow counters supported for this function, in RX direction. */
38402 uint32_t min_rx_fc;
38403 /* Maximum non-guaranteed number of flow counters supported for this function, in RX direction. */
38404 uint32_t max_rx_fc;
38405 /* Minimum guaranteed number of flow counters supported for this function, in TX direction. */
38406 uint32_t min_tx_fc;
38407 /* Maximum non-guaranteed number of flow counters supported for this function, in TX direction. */
38408 uint32_t max_tx_fc;
38409 /* Minimum guaranteed number of extension flow counters supported for this function, in RX direction. */
38410 uint32_t min_rx_efc;
38411 /* Maximum non-guaranteed number of extension flow counters supported for this function, in RX direction. */
38412 uint32_t max_rx_efc;
38413 /* Minimum guaranteed number of extension flow counters supported for this function, in TX direction. */
38414 uint32_t min_tx_efc;
38415 /* Maximum non-guaranteed number of extension flow counters supported for this function, in TX direction. */
38416 uint32_t max_tx_efc;
38417 /* Minimum guaranteed number of meter drop counters supported for this function, in RX direction. */
38418 uint32_t min_rx_mdc;
38419 /* Maximum non-guaranteed number of meter drop counters supported for this function, in RX direction. */
38420 uint32_t max_rx_mdc;
38421 /* Minimum guaranteed number of meter drop counters supported for this function, in TX direction. */
38422 uint32_t min_tx_mdc;
38423 /* Maximum non-guaranteed number of meter drop counters supported for this function, in TX direction. */
38424 uint32_t max_tx_mdc;
38425 /* Maximum guaranteed number of flow counters which can be used during flow alloc. */
38426 uint32_t max_flow_alloc_fc;
38427 uint8_t unused_1[3];
38429 * This field is used in Output records to indicate that the output
38430 * is completely written to RAM. This field should be read as '1'
38431 * to indicate that the output has been completely written.
38432 * When writing a command completion or response to an internal processor,
38433 * the order of writes has to be such that this field is written last.
38438 /************************
38439 * hwrm_cfa_counter_cfg *
38440 ************************/
38443 /* hwrm_cfa_counter_cfg_input (size:256b/32B) */
38444 struct hwrm_cfa_counter_cfg_input {
38445 /* The HWRM command request type. */
38448 * The completion ring to send the completion event on. This should
38449 * be the NQ ID returned from the `nq_alloc` HWRM command.
38451 uint16_t cmpl_ring;
38453 * The sequence ID is used by the driver for tracking multiple
38454 * commands. This ID is treated as opaque data by the firmware and
38455 * the value is returned in the `hwrm_resp_hdr` upon completion.
38459 * The target ID of the command:
38460 * * 0x0-0xFFF8 - The function ID
38461 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
38462 * * 0xFFFD - Reserved for user-space HWRM interface
38465 uint16_t target_id;
38467 * A physical address pointer pointing to a host buffer that the
38468 * command's response data will be written. This can be either a host
38469 * physical address (HPA) or a guest physical address (GPA) and must
38470 * point to a physically contiguous block of memory.
38472 uint64_t resp_addr;
38474 /* Enumeration denoting the configuration mode. */
38475 #define HWRM_CFA_COUNTER_CFG_INPUT_FLAGS_CFG_MODE \
38477 /* Disable the configuration mode. */
38478 #define HWRM_CFA_COUNTER_CFG_INPUT_FLAGS_CFG_MODE_DISABLE \
38480 /* Enable the configuration mode. */
38481 #define HWRM_CFA_COUNTER_CFG_INPUT_FLAGS_CFG_MODE_ENABLE \
38483 #define HWRM_CFA_COUNTER_CFG_INPUT_FLAGS_CFG_MODE_LAST \
38484 HWRM_CFA_COUNTER_CFG_INPUT_FLAGS_CFG_MODE_ENABLE
38485 /* Enumeration denoting the RX, TX type of the resource. */
38486 #define HWRM_CFA_COUNTER_CFG_INPUT_FLAGS_PATH \
38489 #define HWRM_CFA_COUNTER_CFG_INPUT_FLAGS_PATH_TX \
38490 (UINT32_C(0x0) << 1)
38492 #define HWRM_CFA_COUNTER_CFG_INPUT_FLAGS_PATH_RX \
38493 (UINT32_C(0x1) << 1)
38494 #define HWRM_CFA_COUNTER_CFG_INPUT_FLAGS_PATH_LAST \
38495 HWRM_CFA_COUNTER_CFG_INPUT_FLAGS_PATH_RX
38496 /* Enumeration denoting the data transfer mode. */
38497 #define HWRM_CFA_COUNTER_CFG_INPUT_FLAGS_DATA_TRANSFER_MODE_MASK \
38499 #define HWRM_CFA_COUNTER_CFG_INPUT_FLAGS_DATA_TRANSFER_MODE_SFT 2
38501 #define HWRM_CFA_COUNTER_CFG_INPUT_FLAGS_DATA_TRANSFER_MODE_PUSH \
38502 (UINT32_C(0x0) << 2)
38504 #define HWRM_CFA_COUNTER_CFG_INPUT_FLAGS_DATA_TRANSFER_MODE_PULL \
38505 (UINT32_C(0x1) << 2)
38506 /* Pull on async update. */
38507 #define HWRM_CFA_COUNTER_CFG_INPUT_FLAGS_DATA_TRANSFER_MODE_PULL_ASYNC \
38508 (UINT32_C(0x2) << 2)
38509 #define HWRM_CFA_COUNTER_CFG_INPUT_FLAGS_DATA_TRANSFER_MODE_LAST \
38510 HWRM_CFA_COUNTER_CFG_INPUT_FLAGS_DATA_TRANSFER_MODE_PULL_ASYNC
38511 uint16_t counter_type;
38512 /* Flow counters. */
38513 #define HWRM_CFA_COUNTER_CFG_INPUT_COUNTER_TYPE_FC UINT32_C(0x0)
38514 /* Extended flow counters. */
38515 #define HWRM_CFA_COUNTER_CFG_INPUT_COUNTER_TYPE_EFC UINT32_C(0x1)
38516 /* Meter drop counters. */
38517 #define HWRM_CFA_COUNTER_CFG_INPUT_COUNTER_TYPE_MDC UINT32_C(0x2)
38518 #define HWRM_CFA_COUNTER_CFG_INPUT_COUNTER_TYPE_LAST \
38519 HWRM_CFA_COUNTER_CFG_INPUT_COUNTER_TYPE_MDC
38520 /* Ctx memory handle to be used for the counter. */
38522 /* Counter update cadence hint (only in Push mode). */
38523 uint16_t update_tmr_ms;
38524 /* Total number of entries. */
38525 uint32_t num_entries;
38529 /* hwrm_cfa_counter_cfg_output (size:128b/16B) */
38530 struct hwrm_cfa_counter_cfg_output {
38531 /* The specific error status for the command. */
38532 uint16_t error_code;
38533 /* The HWRM command request type. */
38535 /* The sequence ID from the original command. */
38537 /* The length of the response data in number of bytes. */
38539 uint8_t unused_0[7];
38541 * This field is used in Output records to indicate that the output
38542 * is completely written to RAM. This field should be read as '1'
38543 * to indicate that the output has been completely written.
38544 * When writing a command completion or response to an internal processor,
38545 * the order of writes has to be such that this field is written last.
38550 /***************************
38551 * hwrm_cfa_counter_qstats *
38552 ***************************/
38555 /* hwrm_cfa_counter_qstats_input (size:320b/40B) */
38556 struct hwrm_cfa_counter_qstats_input {
38557 /* The HWRM command request type. */
38560 * The completion ring to send the completion event on. This should
38561 * be the NQ ID returned from the `nq_alloc` HWRM command.
38563 uint16_t cmpl_ring;
38565 * The sequence ID is used by the driver for tracking multiple
38566 * commands. This ID is treated as opaque data by the firmware and
38567 * the value is returned in the `hwrm_resp_hdr` upon completion.
38571 * The target ID of the command:
38572 * * 0x0-0xFFF8 - The function ID
38573 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
38574 * * 0xFFFD - Reserved for user-space HWRM interface
38577 uint16_t target_id;
38579 * A physical address pointer pointing to a host buffer that the
38580 * command's response data will be written. This can be either a host
38581 * physical address (HPA) or a guest physical address (GPA) and must
38582 * point to a physically contiguous block of memory.
38584 uint64_t resp_addr;
38586 /* Enumeration denoting the RX, TX type of the resource. */
38587 #define HWRM_CFA_COUNTER_QSTATS_INPUT_FLAGS_PATH UINT32_C(0x1)
38589 #define HWRM_CFA_COUNTER_QSTATS_INPUT_FLAGS_PATH_TX UINT32_C(0x0)
38591 #define HWRM_CFA_COUNTER_QSTATS_INPUT_FLAGS_PATH_RX UINT32_C(0x1)
38592 #define HWRM_CFA_COUNTER_QSTATS_INPUT_FLAGS_PATH_LAST \
38593 HWRM_CFA_COUNTER_QSTATS_INPUT_FLAGS_PATH_RX
38594 uint16_t counter_type;
38595 uint16_t input_flow_ctx_id;
38596 uint16_t num_entries;
38597 uint16_t delta_time_ms;
38598 uint16_t meter_instance_id;
38599 uint16_t mdc_ctx_id;
38600 uint8_t unused_0[2];
38601 uint64_t expected_count;
38604 /* hwrm_cfa_counter_qstats_output (size:128b/16B) */
38605 struct hwrm_cfa_counter_qstats_output {
38606 /* The specific error status for the command. */
38607 uint16_t error_code;
38608 /* The HWRM command request type. */
38610 /* The sequence ID from the original command. */
38612 /* The length of the response data in number of bytes. */
38614 uint8_t unused_0[7];
38616 * This field is used in Output records to indicate that the output
38617 * is completely written to RAM. This field should be read as '1'
38618 * to indicate that the output has been completely written.
38619 * When writing a command completion or response to an internal processor,
38620 * the order of writes has to be such that this field is written last.
38626 * This structure is fixed at the beginning of the ChiMP SRAM (GRC
38627 * offset: 0x31001F0). Host software is expected to read from this
38628 * location for a defined signature. If it exists, the software can
38629 * assume the presence of this structure and the validity of the
38630 * FW_STATUS location in the next field.
38632 /* hcomm_status (size:64b/8B) */
38633 struct hcomm_status {
38636 * This field defines the version of the structure. The latest
38637 * version value is 1.
38639 #define HCOMM_STATUS_VER_MASK UINT32_C(0xff)
38640 #define HCOMM_STATUS_VER_SFT 0
38641 #define HCOMM_STATUS_VER_LATEST UINT32_C(0x1)
38642 #define HCOMM_STATUS_VER_LAST HCOMM_STATUS_VER_LATEST
38644 * This field is to store the signature value to indicate the
38645 * presence of the structure.
38647 #define HCOMM_STATUS_SIGNATURE_MASK UINT32_C(0xffffff00)
38648 #define HCOMM_STATUS_SIGNATURE_SFT 8
38649 #define HCOMM_STATUS_SIGNATURE_VAL (UINT32_C(0x484353) << 8)
38650 #define HCOMM_STATUS_SIGNATURE_LAST HCOMM_STATUS_SIGNATURE_VAL
38651 uint32_t fw_status_loc;
38652 #define HCOMM_STATUS_TRUE_ADDR_SPACE_MASK UINT32_C(0x3)
38653 #define HCOMM_STATUS_TRUE_ADDR_SPACE_SFT 0
38654 /* PCIE configuration space */
38655 #define HCOMM_STATUS_FW_STATUS_LOC_ADDR_SPACE_PCIE_CFG UINT32_C(0x0)
38657 #define HCOMM_STATUS_FW_STATUS_LOC_ADDR_SPACE_GRC UINT32_C(0x1)
38659 #define HCOMM_STATUS_FW_STATUS_LOC_ADDR_SPACE_BAR0 UINT32_C(0x2)
38661 #define HCOMM_STATUS_FW_STATUS_LOC_ADDR_SPACE_BAR1 UINT32_C(0x3)
38662 #define HCOMM_STATUS_FW_STATUS_LOC_ADDR_SPACE_LAST \
38663 HCOMM_STATUS_FW_STATUS_LOC_ADDR_SPACE_BAR1
38665 * This offset where the fw_status register is located. The value
38666 * is generally 4-byte aligned.
38668 #define HCOMM_STATUS_TRUE_OFFSET_MASK UINT32_C(0xfffffffc)
38669 #define HCOMM_STATUS_TRUE_OFFSET_SFT 2
38671 /* This is the GRC offset where the hcomm_status struct resides. */
38672 #define HCOMM_STATUS_STRUCT_LOC 0x31001F0UL
38674 #endif /* _HSI_STRUCT_DEF_DPDK_H_ */