1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright (c) 2014-2021 Broadcom Inc.
5 * DO NOT MODIFY!!! This file is automatically generated.
8 #ifndef _HSI_STRUCT_DEF_DPDK_H_
9 #define _HSI_STRUCT_DEF_DPDK_H_
11 /* This is the HWRM command header. */
12 /* hwrm_cmd_hdr (size:128b/16B) */
14 /* The HWRM command request type. */
17 * The completion ring to send the completion event on. This should
18 * be the NQ ID returned from the `nq_alloc` HWRM command.
22 * The sequence ID is used by the driver for tracking multiple
23 * commands. This ID is treated as opaque data by the firmware and
24 * the value is returned in the `hwrm_resp_hdr` upon completion.
28 * The target ID of the command:
29 * * 0x0-0xFFF8 - The function ID
30 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
31 * * 0xFFFD - Reserved for user-space HWRM interface
36 * A physical address pointer pointing to a host buffer that the
37 * command's response data will be written. This can be either a host
38 * physical address (HPA) or a guest physical address (GPA) and must
39 * point to a physically contiguous block of memory.
44 /* This is the HWRM response header. */
45 /* hwrm_resp_hdr (size:64b/8B) */
46 struct hwrm_resp_hdr {
47 /* The specific error status for the command. */
49 /* The HWRM command request type. */
51 /* The sequence ID from the original command. */
53 /* The length of the response data in number of bytes. */
58 * TLV encapsulated message. Use the TLV type field of the
59 * TLV to determine the type of message encapsulated.
61 #define CMD_DISCR_TLV_ENCAP UINT32_C(0x8000)
62 #define CMD_DISCR_LAST CMD_DISCR_TLV_ENCAP
65 /* HWRM request message */
66 #define TLV_TYPE_HWRM_REQUEST UINT32_C(0x1)
67 /* HWRM response message */
68 #define TLV_TYPE_HWRM_RESPONSE UINT32_C(0x2)
69 /* RoCE slow path command */
70 #define TLV_TYPE_ROCE_SP_COMMAND UINT32_C(0x3)
71 /* RoCE slow path command to query CC Gen1 support. */
72 #define TLV_TYPE_QUERY_ROCE_CC_GEN1 UINT32_C(0x4)
73 /* RoCE slow path command to modify CC Gen1 support. */
74 #define TLV_TYPE_MODIFY_ROCE_CC_GEN1 UINT32_C(0x5)
75 /* Engine CKV - The Alias key EC curve and ECC public key information. */
76 #define TLV_TYPE_ENGINE_CKV_ALIAS_ECC_PUBLIC_KEY UINT32_C(0x8001)
77 /* Engine CKV - Initialization vector. */
78 #define TLV_TYPE_ENGINE_CKV_IV UINT32_C(0x8003)
79 /* Engine CKV - Authentication tag. */
80 #define TLV_TYPE_ENGINE_CKV_AUTH_TAG UINT32_C(0x8004)
81 /* Engine CKV - The encrypted data. */
82 #define TLV_TYPE_ENGINE_CKV_CIPHERTEXT UINT32_C(0x8005)
83 /* Engine CKV - Supported host_algorithms. */
84 #define TLV_TYPE_ENGINE_CKV_HOST_ALGORITHMS UINT32_C(0x8006)
85 /* Engine CKV - The Host EC curve name and ECC public key information. */
86 #define TLV_TYPE_ENGINE_CKV_HOST_ECC_PUBLIC_KEY UINT32_C(0x8007)
87 /* Engine CKV - The ECDSA signature. */
88 #define TLV_TYPE_ENGINE_CKV_ECDSA_SIGNATURE UINT32_C(0x8008)
89 /* Engine CKV - The firmware EC curve name and ECC public key information. */
90 #define TLV_TYPE_ENGINE_CKV_FW_ECC_PUBLIC_KEY UINT32_C(0x8009)
91 /* Engine CKV - Supported firmware algorithms. */
92 #define TLV_TYPE_ENGINE_CKV_FW_ALGORITHMS UINT32_C(0x800a)
93 #define TLV_TYPE_LAST \
94 TLV_TYPE_ENGINE_CKV_FW_ALGORITHMS
97 /* tlv (size:64b/8B) */
100 * The command discriminator is used to differentiate between various
101 * types of HWRM messages. This includes legacy HWRM and RoCE slowpath
102 * command messages as well as newer TLV encapsulated HWRM commands.
104 * For TLV encapsulated messages this field must be 0x8000.
110 * Indicates the presence of additional TLV encapsulated data
113 #define TLV_FLAGS_MORE UINT32_C(0x1)
114 /* Last TLV in a sequence of TLVs. */
115 #define TLV_FLAGS_MORE_LAST UINT32_C(0x0)
116 /* More TLVs follow this TLV. */
117 #define TLV_FLAGS_MORE_NOT_LAST UINT32_C(0x1)
119 * When an HWRM receiver detects a TLV type that it does not
120 * support with the TLV required flag set, the receiver must
121 * reject the HWRM message with an error code indicating an
122 * unsupported TLV type.
124 #define TLV_FLAGS_REQUIRED UINT32_C(0x2)
126 #define TLV_FLAGS_REQUIRED_NO (UINT32_C(0x0) << 1)
128 #define TLV_FLAGS_REQUIRED_YES (UINT32_C(0x1) << 1)
129 #define TLV_FLAGS_REQUIRED_LAST TLV_FLAGS_REQUIRED_YES
131 * This field defines the TLV type value which is divided into
132 * two ranges to differentiate between global and local TLV types.
133 * Global TLV types must be unique across all defined TLV types.
134 * Local TLV types are valid only for extensions to a given
135 * HWRM message and may be repeated across different HWRM message
136 * types. There is a direct correlation of each HWRM message type
137 * to a single global TLV type value.
139 * Global TLV range: `0 - (63k-1)`
141 * Local TLV range: `63k - (64k-1)`
145 * Length of the message data encapsulated by this TLV in bytes.
146 * This length does not include the size of the TLV header itself
147 * and it must be an integer multiple of 8B.
153 /* input (size:128b/16B) */
156 * This value indicates what type of request this is. The format
157 * for the rest of the command is determined by this field.
161 * This value indicates the what completion ring the request will
162 * be optionally completed on. If the value is -1, then no
163 * CR completion will be generated. Any other value must be a
164 * valid CR ring_id value for this function.
167 /* This value indicates the command sequence number. */
170 * Target ID of this command.
172 * 0x0 - 0xFFF8 - Used for function ids
173 * 0xFFF8 - 0xFFFE - Reserved for internal processors
178 * This is the host address where the response will be written
179 * when the request is complete. This area must be 16B aligned
180 * and must be cleared to zero before the request is made.
186 /* output (size:64b/8B) */
189 * Pass/Fail or error type
191 * Note: receiver to verify the in parameters, and fail the call
192 * with an error when appropriate
195 /* This field returns the type of original request. */
197 /* This field provides original sequence number of the command. */
200 * This field is the length of the response in bytes. The
201 * last byte of the response is a valid flag that will read
202 * as '1' when the command has been completely written to
208 /* Short Command Structure */
209 /* hwrm_short_input (size:128b/16B) */
210 struct hwrm_short_input {
212 * This field indicates the type of request in the request buffer.
213 * The format for the rest of the command (request) is determined
218 * This field indicates a signature that is used to identify short
219 * form of the command listed here. This field shall be set to
223 /* Signature indicating this is a short form of HWRM command */
224 #define HWRM_SHORT_INPUT_SIGNATURE_SHORT_CMD UINT32_C(0x4321)
225 #define HWRM_SHORT_INPUT_SIGNATURE_LAST \
226 HWRM_SHORT_INPUT_SIGNATURE_SHORT_CMD
227 /* The target ID of the command */
229 /* Default target_id (0x0) to maintain compatibility with old driver */
230 #define HWRM_SHORT_INPUT_TARGET_ID_DEFAULT UINT32_C(0x0)
231 /* Reserved for user-space HWRM interface */
232 #define HWRM_SHORT_INPUT_TARGET_ID_TOOLS UINT32_C(0xfffd)
233 #define HWRM_SHORT_INPUT_TARGET_ID_LAST \
234 HWRM_SHORT_INPUT_TARGET_ID_TOOLS
235 /* This value indicates the length of the request. */
238 * This is the host address where the request was written.
239 * This area must be 16B aligned.
246 * # NOTE - definitions already in hwrm_req_type, in hwrm_types.yaml
247 * # So only structure definition is provided here.
249 /* cmd_nums (size:64b/8B) */
252 * This version of the specification defines the commands listed in
253 * the table below. The following are general implementation
254 * requirements for these commands:
256 * # All commands listed below that are marked neither
257 * reserved nor experimental shall be implemented by the HWRM.
258 * # A HWRM client compliant to this specification should not use
259 * commands outside of the list below.
260 * # A HWRM client compliant to this specification should not use
261 * command numbers marked reserved below.
262 * # A command marked experimental below may not be implemented
264 * # A command marked experimental may change in the
265 * future version of the HWRM specification.
266 * # A command not listed below may be implemented by the HWRM.
267 * The behavior of commands that are not listed below is outside
268 * the scope of this specification.
271 #define HWRM_VER_GET UINT32_C(0x0)
272 #define HWRM_FUNC_ECHO_RESPONSE UINT32_C(0xb)
273 #define HWRM_ERROR_RECOVERY_QCFG UINT32_C(0xc)
274 #define HWRM_FUNC_DRV_IF_CHANGE UINT32_C(0xd)
275 #define HWRM_FUNC_BUF_UNRGTR UINT32_C(0xe)
276 #define HWRM_FUNC_VF_CFG UINT32_C(0xf)
277 /* Reserved for future use. */
278 #define HWRM_RESERVED1 UINT32_C(0x10)
279 #define HWRM_FUNC_RESET UINT32_C(0x11)
280 #define HWRM_FUNC_GETFID UINT32_C(0x12)
281 #define HWRM_FUNC_VF_ALLOC UINT32_C(0x13)
282 #define HWRM_FUNC_VF_FREE UINT32_C(0x14)
283 #define HWRM_FUNC_QCAPS UINT32_C(0x15)
284 #define HWRM_FUNC_QCFG UINT32_C(0x16)
285 #define HWRM_FUNC_CFG UINT32_C(0x17)
286 #define HWRM_FUNC_QSTATS UINT32_C(0x18)
287 #define HWRM_FUNC_CLR_STATS UINT32_C(0x19)
288 #define HWRM_FUNC_DRV_UNRGTR UINT32_C(0x1a)
289 #define HWRM_FUNC_VF_RESC_FREE UINT32_C(0x1b)
290 #define HWRM_FUNC_VF_VNIC_IDS_QUERY UINT32_C(0x1c)
291 #define HWRM_FUNC_DRV_RGTR UINT32_C(0x1d)
292 #define HWRM_FUNC_DRV_QVER UINT32_C(0x1e)
293 #define HWRM_FUNC_BUF_RGTR UINT32_C(0x1f)
294 #define HWRM_PORT_PHY_CFG UINT32_C(0x20)
295 #define HWRM_PORT_MAC_CFG UINT32_C(0x21)
297 #define HWRM_PORT_TS_QUERY UINT32_C(0x22)
298 #define HWRM_PORT_QSTATS UINT32_C(0x23)
299 #define HWRM_PORT_LPBK_QSTATS UINT32_C(0x24)
301 #define HWRM_PORT_CLR_STATS UINT32_C(0x25)
303 #define HWRM_PORT_LPBK_CLR_STATS UINT32_C(0x26)
304 #define HWRM_PORT_PHY_QCFG UINT32_C(0x27)
305 #define HWRM_PORT_MAC_QCFG UINT32_C(0x28)
307 #define HWRM_PORT_MAC_PTP_QCFG UINT32_C(0x29)
308 #define HWRM_PORT_PHY_QCAPS UINT32_C(0x2a)
309 #define HWRM_PORT_PHY_I2C_WRITE UINT32_C(0x2b)
310 #define HWRM_PORT_PHY_I2C_READ UINT32_C(0x2c)
311 #define HWRM_PORT_LED_CFG UINT32_C(0x2d)
312 #define HWRM_PORT_LED_QCFG UINT32_C(0x2e)
313 #define HWRM_PORT_LED_QCAPS UINT32_C(0x2f)
314 #define HWRM_QUEUE_QPORTCFG UINT32_C(0x30)
315 #define HWRM_QUEUE_QCFG UINT32_C(0x31)
316 #define HWRM_QUEUE_CFG UINT32_C(0x32)
317 #define HWRM_FUNC_VLAN_CFG UINT32_C(0x33)
318 #define HWRM_FUNC_VLAN_QCFG UINT32_C(0x34)
319 #define HWRM_QUEUE_PFCENABLE_QCFG UINT32_C(0x35)
320 #define HWRM_QUEUE_PFCENABLE_CFG UINT32_C(0x36)
321 #define HWRM_QUEUE_PRI2COS_QCFG UINT32_C(0x37)
322 #define HWRM_QUEUE_PRI2COS_CFG UINT32_C(0x38)
323 #define HWRM_QUEUE_COS2BW_QCFG UINT32_C(0x39)
324 #define HWRM_QUEUE_COS2BW_CFG UINT32_C(0x3a)
325 #define HWRM_QUEUE_DSCP_QCAPS UINT32_C(0x3b)
326 #define HWRM_QUEUE_DSCP2PRI_QCFG UINT32_C(0x3c)
327 #define HWRM_QUEUE_DSCP2PRI_CFG UINT32_C(0x3d)
328 #define HWRM_VNIC_ALLOC UINT32_C(0x40)
329 #define HWRM_VNIC_FREE UINT32_C(0x41)
330 #define HWRM_VNIC_CFG UINT32_C(0x42)
331 #define HWRM_VNIC_QCFG UINT32_C(0x43)
332 #define HWRM_VNIC_TPA_CFG UINT32_C(0x44)
334 #define HWRM_VNIC_TPA_QCFG UINT32_C(0x45)
335 #define HWRM_VNIC_RSS_CFG UINT32_C(0x46)
336 #define HWRM_VNIC_RSS_QCFG UINT32_C(0x47)
337 #define HWRM_VNIC_PLCMODES_CFG UINT32_C(0x48)
338 #define HWRM_VNIC_PLCMODES_QCFG UINT32_C(0x49)
339 #define HWRM_VNIC_QCAPS UINT32_C(0x4a)
340 /* Updates specific fields in RX VNIC structure */
341 #define HWRM_VNIC_UPDATE UINT32_C(0x4b)
342 #define HWRM_RING_ALLOC UINT32_C(0x50)
343 #define HWRM_RING_FREE UINT32_C(0x51)
344 #define HWRM_RING_CMPL_RING_QAGGINT_PARAMS UINT32_C(0x52)
345 #define HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS UINT32_C(0x53)
346 #define HWRM_RING_AGGINT_QCAPS UINT32_C(0x54)
347 #define HWRM_RING_SCHQ_ALLOC UINT32_C(0x55)
348 #define HWRM_RING_SCHQ_CFG UINT32_C(0x56)
349 #define HWRM_RING_SCHQ_FREE UINT32_C(0x57)
350 #define HWRM_RING_RESET UINT32_C(0x5e)
351 #define HWRM_RING_GRP_ALLOC UINT32_C(0x60)
352 #define HWRM_RING_GRP_FREE UINT32_C(0x61)
353 #define HWRM_RING_CFG UINT32_C(0x62)
354 #define HWRM_RING_QCFG UINT32_C(0x63)
355 /* Reserved for future use. */
356 #define HWRM_RESERVED5 UINT32_C(0x64)
357 /* Reserved for future use. */
358 #define HWRM_RESERVED6 UINT32_C(0x65)
359 #define HWRM_VNIC_RSS_COS_LB_CTX_ALLOC UINT32_C(0x70)
360 #define HWRM_VNIC_RSS_COS_LB_CTX_FREE UINT32_C(0x71)
361 #define HWRM_QUEUE_MPLS_QCAPS UINT32_C(0x80)
362 #define HWRM_QUEUE_MPLSTC2PRI_QCFG UINT32_C(0x81)
363 #define HWRM_QUEUE_MPLSTC2PRI_CFG UINT32_C(0x82)
364 #define HWRM_QUEUE_VLANPRI_QCAPS UINT32_C(0x83)
365 #define HWRM_QUEUE_VLANPRI2PRI_QCFG UINT32_C(0x84)
366 #define HWRM_QUEUE_VLANPRI2PRI_CFG UINT32_C(0x85)
367 #define HWRM_QUEUE_GLOBAL_CFG UINT32_C(0x86)
368 #define HWRM_QUEUE_GLOBAL_QCFG UINT32_C(0x87)
369 #define HWRM_CFA_L2_FILTER_ALLOC UINT32_C(0x90)
370 #define HWRM_CFA_L2_FILTER_FREE UINT32_C(0x91)
371 #define HWRM_CFA_L2_FILTER_CFG UINT32_C(0x92)
372 #define HWRM_CFA_L2_SET_RX_MASK UINT32_C(0x93)
373 #define HWRM_CFA_VLAN_ANTISPOOF_CFG UINT32_C(0x94)
374 #define HWRM_CFA_TUNNEL_FILTER_ALLOC UINT32_C(0x95)
375 #define HWRM_CFA_TUNNEL_FILTER_FREE UINT32_C(0x96)
377 #define HWRM_CFA_ENCAP_RECORD_ALLOC UINT32_C(0x97)
379 #define HWRM_CFA_ENCAP_RECORD_FREE UINT32_C(0x98)
380 #define HWRM_CFA_NTUPLE_FILTER_ALLOC UINT32_C(0x99)
381 #define HWRM_CFA_NTUPLE_FILTER_FREE UINT32_C(0x9a)
382 #define HWRM_CFA_NTUPLE_FILTER_CFG UINT32_C(0x9b)
384 #define HWRM_CFA_EM_FLOW_ALLOC UINT32_C(0x9c)
386 #define HWRM_CFA_EM_FLOW_FREE UINT32_C(0x9d)
388 #define HWRM_CFA_EM_FLOW_CFG UINT32_C(0x9e)
389 #define HWRM_TUNNEL_DST_PORT_QUERY UINT32_C(0xa0)
390 #define HWRM_TUNNEL_DST_PORT_ALLOC UINT32_C(0xa1)
391 #define HWRM_TUNNEL_DST_PORT_FREE UINT32_C(0xa2)
392 #define HWRM_STAT_CTX_ENG_QUERY UINT32_C(0xaf)
393 #define HWRM_STAT_CTX_ALLOC UINT32_C(0xb0)
394 #define HWRM_STAT_CTX_FREE UINT32_C(0xb1)
395 #define HWRM_STAT_CTX_QUERY UINT32_C(0xb2)
396 #define HWRM_STAT_CTX_CLR_STATS UINT32_C(0xb3)
397 #define HWRM_PORT_QSTATS_EXT UINT32_C(0xb4)
398 #define HWRM_PORT_PHY_MDIO_WRITE UINT32_C(0xb5)
399 #define HWRM_PORT_PHY_MDIO_READ UINT32_C(0xb6)
400 #define HWRM_PORT_PHY_MDIO_BUS_ACQUIRE UINT32_C(0xb7)
401 #define HWRM_PORT_PHY_MDIO_BUS_RELEASE UINT32_C(0xb8)
402 #define HWRM_PORT_QSTATS_EXT_PFC_WD UINT32_C(0xb9)
404 #define HWRM_RESERVED7 UINT32_C(0xba)
405 #define HWRM_PORT_TX_FIR_CFG UINT32_C(0xbb)
406 #define HWRM_PORT_TX_FIR_QCFG UINT32_C(0xbc)
407 #define HWRM_PORT_ECN_QSTATS UINT32_C(0xbd)
408 #define HWRM_FW_LIVEPATCH_QUERY UINT32_C(0xbe)
409 #define HWRM_FW_LIVEPATCH UINT32_C(0xbf)
410 #define HWRM_FW_RESET UINT32_C(0xc0)
411 #define HWRM_FW_QSTATUS UINT32_C(0xc1)
412 #define HWRM_FW_HEALTH_CHECK UINT32_C(0xc2)
413 #define HWRM_FW_SYNC UINT32_C(0xc3)
414 #define HWRM_FW_STATE_QCAPS UINT32_C(0xc4)
415 #define HWRM_FW_STATE_QUIESCE UINT32_C(0xc5)
416 #define HWRM_FW_STATE_BACKUP UINT32_C(0xc6)
417 #define HWRM_FW_STATE_RESTORE UINT32_C(0xc7)
419 #define HWRM_FW_SET_TIME UINT32_C(0xc8)
421 #define HWRM_FW_GET_TIME UINT32_C(0xc9)
423 #define HWRM_FW_SET_STRUCTURED_DATA UINT32_C(0xca)
425 #define HWRM_FW_GET_STRUCTURED_DATA UINT32_C(0xcb)
427 #define HWRM_FW_IPC_MAILBOX UINT32_C(0xcc)
428 #define HWRM_FW_ECN_CFG UINT32_C(0xcd)
429 #define HWRM_FW_ECN_QCFG UINT32_C(0xce)
430 #define HWRM_FW_SECURE_CFG UINT32_C(0xcf)
431 #define HWRM_EXEC_FWD_RESP UINT32_C(0xd0)
432 #define HWRM_REJECT_FWD_RESP UINT32_C(0xd1)
433 #define HWRM_FWD_RESP UINT32_C(0xd2)
434 #define HWRM_FWD_ASYNC_EVENT_CMPL UINT32_C(0xd3)
435 #define HWRM_OEM_CMD UINT32_C(0xd4)
436 /* Tells the fw to run PRBS test on a given port and lane. */
437 #define HWRM_PORT_PRBS_TEST UINT32_C(0xd5)
438 #define HWRM_PORT_SFP_SIDEBAND_CFG UINT32_C(0xd6)
439 #define HWRM_PORT_SFP_SIDEBAND_QCFG UINT32_C(0xd7)
440 #define HWRM_FW_STATE_UNQUIESCE UINT32_C(0xd8)
441 /* Tells the fw to collect dsc dump on a given port and lane. */
442 #define HWRM_PORT_DSC_DUMP UINT32_C(0xd9)
443 #define HWRM_PORT_EP_TX_QCFG UINT32_C(0xda)
444 #define HWRM_PORT_EP_TX_CFG UINT32_C(0xdb)
445 #define HWRM_TEMP_MONITOR_QUERY UINT32_C(0xe0)
446 #define HWRM_REG_POWER_QUERY UINT32_C(0xe1)
447 #define HWRM_CORE_FREQUENCY_QUERY UINT32_C(0xe2)
448 #define HWRM_REG_POWER_HISTOGRAM UINT32_C(0xe3)
449 #define HWRM_WOL_FILTER_ALLOC UINT32_C(0xf0)
450 #define HWRM_WOL_FILTER_FREE UINT32_C(0xf1)
451 #define HWRM_WOL_FILTER_QCFG UINT32_C(0xf2)
452 #define HWRM_WOL_REASON_QCFG UINT32_C(0xf3)
454 #define HWRM_CFA_METER_QCAPS UINT32_C(0xf4)
456 #define HWRM_CFA_METER_PROFILE_ALLOC UINT32_C(0xf5)
458 #define HWRM_CFA_METER_PROFILE_FREE UINT32_C(0xf6)
460 #define HWRM_CFA_METER_PROFILE_CFG UINT32_C(0xf7)
462 #define HWRM_CFA_METER_INSTANCE_ALLOC UINT32_C(0xf8)
464 #define HWRM_CFA_METER_INSTANCE_FREE UINT32_C(0xf9)
466 #define HWRM_CFA_METER_INSTANCE_CFG UINT32_C(0xfa)
468 #define HWRM_CFA_VFR_ALLOC UINT32_C(0xfd)
470 #define HWRM_CFA_VFR_FREE UINT32_C(0xfe)
472 #define HWRM_CFA_VF_PAIR_ALLOC UINT32_C(0x100)
474 #define HWRM_CFA_VF_PAIR_FREE UINT32_C(0x101)
476 #define HWRM_CFA_VF_PAIR_INFO UINT32_C(0x102)
478 #define HWRM_CFA_FLOW_ALLOC UINT32_C(0x103)
480 #define HWRM_CFA_FLOW_FREE UINT32_C(0x104)
482 #define HWRM_CFA_FLOW_FLUSH UINT32_C(0x105)
484 #define HWRM_CFA_FLOW_STATS UINT32_C(0x106)
486 #define HWRM_CFA_FLOW_INFO UINT32_C(0x107)
488 #define HWRM_CFA_DECAP_FILTER_ALLOC UINT32_C(0x108)
490 #define HWRM_CFA_DECAP_FILTER_FREE UINT32_C(0x109)
491 #define HWRM_CFA_VLAN_ANTISPOOF_QCFG UINT32_C(0x10a)
492 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_ALLOC UINT32_C(0x10b)
493 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_FREE UINT32_C(0x10c)
495 #define HWRM_CFA_PAIR_ALLOC UINT32_C(0x10d)
497 #define HWRM_CFA_PAIR_FREE UINT32_C(0x10e)
499 #define HWRM_CFA_PAIR_INFO UINT32_C(0x10f)
501 #define HWRM_FW_IPC_MSG UINT32_C(0x110)
502 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_INFO UINT32_C(0x111)
503 #define HWRM_CFA_REDIRECT_QUERY_TUNNEL_TYPE UINT32_C(0x112)
505 #define HWRM_CFA_FLOW_AGING_TIMER_RESET UINT32_C(0x113)
507 #define HWRM_CFA_FLOW_AGING_CFG UINT32_C(0x114)
509 #define HWRM_CFA_FLOW_AGING_QCFG UINT32_C(0x115)
511 #define HWRM_CFA_FLOW_AGING_QCAPS UINT32_C(0x116)
513 #define HWRM_CFA_CTX_MEM_RGTR UINT32_C(0x117)
515 #define HWRM_CFA_CTX_MEM_UNRGTR UINT32_C(0x118)
517 #define HWRM_CFA_CTX_MEM_QCTX UINT32_C(0x119)
519 #define HWRM_CFA_CTX_MEM_QCAPS UINT32_C(0x11a)
521 #define HWRM_CFA_COUNTER_QCAPS UINT32_C(0x11b)
523 #define HWRM_CFA_COUNTER_CFG UINT32_C(0x11c)
525 #define HWRM_CFA_COUNTER_QCFG UINT32_C(0x11d)
527 #define HWRM_CFA_COUNTER_QSTATS UINT32_C(0x11e)
529 #define HWRM_CFA_TCP_FLAG_PROCESS_QCFG UINT32_C(0x11f)
531 #define HWRM_CFA_EEM_QCAPS UINT32_C(0x120)
533 #define HWRM_CFA_EEM_CFG UINT32_C(0x121)
535 #define HWRM_CFA_EEM_QCFG UINT32_C(0x122)
537 #define HWRM_CFA_EEM_OP UINT32_C(0x123)
539 #define HWRM_CFA_ADV_FLOW_MGNT_QCAPS UINT32_C(0x124)
540 /* Experimental - DEPRECATED */
541 #define HWRM_CFA_TFLIB UINT32_C(0x125)
543 #define HWRM_CFA_LAG_GROUP_MEMBER_RGTR UINT32_C(0x126)
545 #define HWRM_CFA_LAG_GROUP_MEMBER_UNRGTR UINT32_C(0x127)
546 /* Engine CKV - Get the current allocation status of keys provisioned in the key vault. */
547 #define HWRM_ENGINE_CKV_STATUS UINT32_C(0x12e)
548 /* Engine CKV - Add a new CKEK used to encrypt keys. */
549 #define HWRM_ENGINE_CKV_CKEK_ADD UINT32_C(0x12f)
550 /* Engine CKV - Delete a previously added CKEK. */
551 #define HWRM_ENGINE_CKV_CKEK_DELETE UINT32_C(0x130)
552 /* Engine CKV - Add a new key to the key vault. */
553 #define HWRM_ENGINE_CKV_KEY_ADD UINT32_C(0x131)
554 /* Engine CKV - Delete a key from the key vault. */
555 #define HWRM_ENGINE_CKV_KEY_DELETE UINT32_C(0x132)
556 /* Engine CKV - Delete all keys from the key vault. */
557 #define HWRM_ENGINE_CKV_FLUSH UINT32_C(0x133)
558 /* Engine CKV - Get random data. */
559 #define HWRM_ENGINE_CKV_RNG_GET UINT32_C(0x134)
560 /* Engine CKV - Generate and encrypt a new AES key. */
561 #define HWRM_ENGINE_CKV_KEY_GEN UINT32_C(0x135)
562 /* Engine CKV - Configure a label index with a label value. */
563 #define HWRM_ENGINE_CKV_KEY_LABEL_CFG UINT32_C(0x136)
564 /* Engine CKV - Query a label */
565 #define HWRM_ENGINE_CKV_KEY_LABEL_QCFG UINT32_C(0x137)
566 /* Engine - Query the available queue groups configuration. */
567 #define HWRM_ENGINE_QG_CONFIG_QUERY UINT32_C(0x13c)
568 /* Engine - Query the queue groups assigned to a function. */
569 #define HWRM_ENGINE_QG_QUERY UINT32_C(0x13d)
570 /* Engine - Query the available queue group meter profile configuration. */
571 #define HWRM_ENGINE_QG_METER_PROFILE_CONFIG_QUERY UINT32_C(0x13e)
572 /* Engine - Query the configuration of a queue group meter profile. */
573 #define HWRM_ENGINE_QG_METER_PROFILE_QUERY UINT32_C(0x13f)
574 /* Engine - Allocate a queue group meter profile. */
575 #define HWRM_ENGINE_QG_METER_PROFILE_ALLOC UINT32_C(0x140)
576 /* Engine - Free a queue group meter profile. */
577 #define HWRM_ENGINE_QG_METER_PROFILE_FREE UINT32_C(0x141)
578 /* Engine - Query the meters assigned to a queue group. */
579 #define HWRM_ENGINE_QG_METER_QUERY UINT32_C(0x142)
580 /* Engine - Bind a queue group meter profile to a queue group. */
581 #define HWRM_ENGINE_QG_METER_BIND UINT32_C(0x143)
582 /* Engine - Unbind a queue group meter profile from a queue group. */
583 #define HWRM_ENGINE_QG_METER_UNBIND UINT32_C(0x144)
584 /* Engine - Bind a queue group to a function. */
585 #define HWRM_ENGINE_QG_FUNC_BIND UINT32_C(0x145)
586 /* Engine - Query the scheduling group configuration. */
587 #define HWRM_ENGINE_SG_CONFIG_QUERY UINT32_C(0x146)
588 /* Engine - Query the queue groups assigned to a scheduling group. */
589 #define HWRM_ENGINE_SG_QUERY UINT32_C(0x147)
590 /* Engine - Query the configuration of a scheduling group's meter profiles. */
591 #define HWRM_ENGINE_SG_METER_QUERY UINT32_C(0x148)
592 /* Engine - Configure a scheduling group's meter profiles. */
593 #define HWRM_ENGINE_SG_METER_CONFIG UINT32_C(0x149)
594 /* Engine - Bind a queue group to a scheduling group. */
595 #define HWRM_ENGINE_SG_QG_BIND UINT32_C(0x14a)
596 /* Engine - Unbind a queue group from its scheduling group. */
597 #define HWRM_ENGINE_QG_SG_UNBIND UINT32_C(0x14b)
598 /* Engine - Query the Engine configuration. */
599 #define HWRM_ENGINE_CONFIG_QUERY UINT32_C(0x154)
600 /* Engine - Configure the statistics accumulator for an Engine. */
601 #define HWRM_ENGINE_STATS_CONFIG UINT32_C(0x155)
602 /* Engine - Clear the statistics accumulator for an Engine. */
603 #define HWRM_ENGINE_STATS_CLEAR UINT32_C(0x156)
604 /* Engine - Query the statistics accumulator for an Engine. */
605 #define HWRM_ENGINE_STATS_QUERY UINT32_C(0x157)
606 /* Engine - Query statistics counters for continuous errors from all CDDIP Engines. */
607 #define HWRM_ENGINE_STATS_QUERY_CONTINUOUS_ERROR UINT32_C(0x158)
608 /* Engine - Allocate an Engine RQ. */
609 #define HWRM_ENGINE_RQ_ALLOC UINT32_C(0x15e)
610 /* Engine - Free an Engine RQ. */
611 #define HWRM_ENGINE_RQ_FREE UINT32_C(0x15f)
612 /* Engine - Allocate an Engine CQ. */
613 #define HWRM_ENGINE_CQ_ALLOC UINT32_C(0x160)
614 /* Engine - Free an Engine CQ. */
615 #define HWRM_ENGINE_CQ_FREE UINT32_C(0x161)
616 /* Engine - Allocate an NQ. */
617 #define HWRM_ENGINE_NQ_ALLOC UINT32_C(0x162)
618 /* Engine - Free an NQ. */
619 #define HWRM_ENGINE_NQ_FREE UINT32_C(0x163)
620 /* Engine - Set the on-die RQE credit update location. */
621 #define HWRM_ENGINE_ON_DIE_RQE_CREDITS UINT32_C(0x164)
622 /* Engine - Query the engine function configuration. */
623 #define HWRM_ENGINE_FUNC_QCFG UINT32_C(0x165)
625 #define HWRM_FUNC_RESOURCE_QCAPS UINT32_C(0x190)
627 #define HWRM_FUNC_VF_RESOURCE_CFG UINT32_C(0x191)
629 #define HWRM_FUNC_BACKING_STORE_QCAPS UINT32_C(0x192)
631 #define HWRM_FUNC_BACKING_STORE_CFG UINT32_C(0x193)
633 #define HWRM_FUNC_BACKING_STORE_QCFG UINT32_C(0x194)
634 /* Configures the BW of any VF */
635 #define HWRM_FUNC_VF_BW_CFG UINT32_C(0x195)
636 /* Queries the BW of any VF */
637 #define HWRM_FUNC_VF_BW_QCFG UINT32_C(0x196)
638 /* Queries pf ids belong to specified host(s) */
639 #define HWRM_FUNC_HOST_PF_IDS_QUERY UINT32_C(0x197)
640 /* Queries extended stats per function */
641 #define HWRM_FUNC_QSTATS_EXT UINT32_C(0x198)
642 /* Queries extended statistics context */
643 #define HWRM_STAT_EXT_CTX_QUERY UINT32_C(0x199)
644 /* Configure SoC packet DMA settings */
645 #define HWRM_FUNC_SPD_CFG UINT32_C(0x19a)
646 /* Query SoC packet DMA settings */
647 #define HWRM_FUNC_SPD_QCFG UINT32_C(0x19b)
648 /* PTP - Queries configuration of timesync IO pins. */
649 #define HWRM_FUNC_PTP_PIN_QCFG UINT32_C(0x19c)
650 /* PTP - Configuration of timesync IO pins. */
651 #define HWRM_FUNC_PTP_PIN_CFG UINT32_C(0x19d)
652 /* PTP - Configuration for disciplining PHC. */
653 #define HWRM_FUNC_PTP_CFG UINT32_C(0x19e)
654 /* PTP - Queries for PHC timestamps. */
655 #define HWRM_FUNC_PTP_TS_QUERY UINT32_C(0x19f)
656 /* PTP - Extended PTP configuration. */
657 #define HWRM_FUNC_PTP_EXT_CFG UINT32_C(0x1a0)
658 /* PTP - Query extended PTP configuration. */
659 #define HWRM_FUNC_PTP_EXT_QCFG UINT32_C(0x1a1)
660 /* The command is used to allocate KTLS crypto key contexts. */
661 #define HWRM_FUNC_KEY_CTX_ALLOC UINT32_C(0x1a2)
662 /* The is the new API to configure backing stores. */
663 #define HWRM_FUNC_BACKING_STORE_CFG_V2 UINT32_C(0x1a3)
664 /* The is the new API to query backing store configurations. */
665 #define HWRM_FUNC_BACKING_STORE_QCFG_V2 UINT32_C(0x1a4)
667 #define HWRM_SELFTEST_QLIST UINT32_C(0x200)
669 #define HWRM_SELFTEST_EXEC UINT32_C(0x201)
671 #define HWRM_SELFTEST_IRQ UINT32_C(0x202)
673 #define HWRM_SELFTEST_RETRIEVE_SERDES_DATA UINT32_C(0x203)
675 #define HWRM_PCIE_QSTATS UINT32_C(0x204)
677 #define HWRM_MFG_FRU_WRITE_CONTROL UINT32_C(0x205)
678 /* Returns the current value of a free running counter from the device. */
679 #define HWRM_MFG_TIMERS_QUERY UINT32_C(0x206)
681 #define HWRM_MFG_OTP_CFG UINT32_C(0x207)
683 #define HWRM_MFG_OTP_QCFG UINT32_C(0x208)
685 * Tells the fw to run the DMA read from the host and DMA write
688 #define HWRM_MFG_HDMA_TEST UINT32_C(0x209)
689 /* Tells the fw to program the fru memory */
690 #define HWRM_MFG_FRU_EEPROM_WRITE UINT32_C(0x20a)
691 /* Tells the fw to read the fru memory */
692 #define HWRM_MFG_FRU_EEPROM_READ UINT32_C(0x20b)
693 /* Used to provision SoC software images */
694 #define HWRM_MFG_SOC_IMAGE UINT32_C(0x20c)
695 /* Retrieves the SoC status and image provisioning information */
696 #define HWRM_MFG_SOC_QSTATUS UINT32_C(0x20d)
697 /* Tells the fw to program the seeprom memory */
698 #define HWRM_MFG_PARAM_SEEPROM_SYNC UINT32_C(0x20e)
699 /* Tells the fw to read the seeprom memory */
700 #define HWRM_MFG_PARAM_SEEPROM_READ UINT32_C(0x20f)
701 /* Tells the fw to get the health of seeprom data */
702 #define HWRM_MFG_PARAM_SEEPROM_HEALTH UINT32_C(0x210)
704 * The command is used for certificate provisioning to export a
705 * Certificate Signing Request (CSR) from the device.
707 #define HWRM_MFG_PRVSN_EXPORT_CSR UINT32_C(0x211)
709 * The command is used for certificate provisioning to import a
710 * CA-signed certificate chain to the device.
712 #define HWRM_MFG_PRVSN_IMPORT_CERT UINT32_C(0x212)
714 * The command is used for certificate provisioning to query the
717 #define HWRM_MFG_PRVSN_GET_STATE UINT32_C(0x213)
719 * The command is used to get the hash of the NVM configuration that is
720 * calculated during firmware boot.
722 #define HWRM_MFG_GET_NVM_MEASUREMENT UINT32_C(0x214)
723 /* Retrieves the PSOC status and provisioning information. */
724 #define HWRM_MFG_PSOC_QSTATUS UINT32_C(0x215)
726 * This command allows manufacturing tool to determine which selftests
727 * are available to be run.
729 #define HWRM_MFG_SELFTEST_QLIST UINT32_C(0x216)
731 * This command allows manufacturing tool to request which selftests
734 #define HWRM_MFG_SELFTEST_EXEC UINT32_C(0x217)
736 #define HWRM_TF UINT32_C(0x2bc)
738 #define HWRM_TF_VERSION_GET UINT32_C(0x2bd)
740 #define HWRM_TF_SESSION_OPEN UINT32_C(0x2c6)
742 #define HWRM_TF_SESSION_ATTACH UINT32_C(0x2c7)
744 #define HWRM_TF_SESSION_REGISTER UINT32_C(0x2c8)
746 #define HWRM_TF_SESSION_UNREGISTER UINT32_C(0x2c9)
748 #define HWRM_TF_SESSION_CLOSE UINT32_C(0x2ca)
750 #define HWRM_TF_SESSION_QCFG UINT32_C(0x2cb)
752 #define HWRM_TF_SESSION_RESC_QCAPS UINT32_C(0x2cc)
754 #define HWRM_TF_SESSION_RESC_ALLOC UINT32_C(0x2cd)
756 #define HWRM_TF_SESSION_RESC_FREE UINT32_C(0x2ce)
758 #define HWRM_TF_SESSION_RESC_FLUSH UINT32_C(0x2cf)
760 #define HWRM_TF_SESSION_RESC_INFO UINT32_C(0x2d0)
762 #define HWRM_TF_TBL_TYPE_GET UINT32_C(0x2da)
764 #define HWRM_TF_TBL_TYPE_SET UINT32_C(0x2db)
766 #define HWRM_TF_TBL_TYPE_BULK_GET UINT32_C(0x2dc)
768 #define HWRM_TF_CTXT_MEM_ALLOC UINT32_C(0x2e2)
770 #define HWRM_TF_CTXT_MEM_FREE UINT32_C(0x2e3)
772 #define HWRM_TF_CTXT_MEM_RGTR UINT32_C(0x2e4)
774 #define HWRM_TF_CTXT_MEM_UNRGTR UINT32_C(0x2e5)
776 #define HWRM_TF_EXT_EM_QCAPS UINT32_C(0x2e6)
778 #define HWRM_TF_EXT_EM_OP UINT32_C(0x2e7)
780 #define HWRM_TF_EXT_EM_CFG UINT32_C(0x2e8)
782 #define HWRM_TF_EXT_EM_QCFG UINT32_C(0x2e9)
784 #define HWRM_TF_EM_INSERT UINT32_C(0x2ea)
786 #define HWRM_TF_EM_DELETE UINT32_C(0x2eb)
788 #define HWRM_TF_EM_HASH_INSERT UINT32_C(0x2ec)
790 #define HWRM_TF_EM_MOVE UINT32_C(0x2ed)
792 #define HWRM_TF_TCAM_SET UINT32_C(0x2f8)
794 #define HWRM_TF_TCAM_GET UINT32_C(0x2f9)
796 #define HWRM_TF_TCAM_MOVE UINT32_C(0x2fa)
798 #define HWRM_TF_TCAM_FREE UINT32_C(0x2fb)
800 #define HWRM_TF_GLOBAL_CFG_SET UINT32_C(0x2fc)
802 #define HWRM_TF_GLOBAL_CFG_GET UINT32_C(0x2fd)
804 #define HWRM_TF_IF_TBL_SET UINT32_C(0x2fe)
806 #define HWRM_TF_IF_TBL_GET UINT32_C(0x2ff)
808 #define HWRM_SV UINT32_C(0x400)
810 #define HWRM_DBG_READ_DIRECT UINT32_C(0xff10)
812 #define HWRM_DBG_READ_INDIRECT UINT32_C(0xff11)
814 #define HWRM_DBG_WRITE_DIRECT UINT32_C(0xff12)
816 #define HWRM_DBG_WRITE_INDIRECT UINT32_C(0xff13)
817 #define HWRM_DBG_DUMP UINT32_C(0xff14)
819 #define HWRM_DBG_ERASE_NVM UINT32_C(0xff15)
821 #define HWRM_DBG_CFG UINT32_C(0xff16)
823 #define HWRM_DBG_COREDUMP_LIST UINT32_C(0xff17)
825 #define HWRM_DBG_COREDUMP_INITIATE UINT32_C(0xff18)
827 #define HWRM_DBG_COREDUMP_RETRIEVE UINT32_C(0xff19)
829 #define HWRM_DBG_FW_CLI UINT32_C(0xff1a)
831 #define HWRM_DBG_I2C_CMD UINT32_C(0xff1b)
833 #define HWRM_DBG_RING_INFO_GET UINT32_C(0xff1c)
835 #define HWRM_DBG_CRASHDUMP_HEADER UINT32_C(0xff1d)
837 #define HWRM_DBG_CRASHDUMP_ERASE UINT32_C(0xff1e)
838 /* Send driver debug information to firmware */
839 #define HWRM_DBG_DRV_TRACE UINT32_C(0xff1f)
840 /* Query debug capabilities of firmware */
841 #define HWRM_DBG_QCAPS UINT32_C(0xff20)
842 /* Retrieve debug settings of firmware */
843 #define HWRM_DBG_QCFG UINT32_C(0xff21)
844 /* Set destination parameters for crashdump medium */
845 #define HWRM_DBG_CRASHDUMP_MEDIUM_CFG UINT32_C(0xff22)
847 #define HWRM_DBG_USEQ_ALLOC UINT32_C(0xff23)
849 #define HWRM_DBG_USEQ_FREE UINT32_C(0xff24)
851 #define HWRM_DBG_USEQ_FLUSH UINT32_C(0xff25)
853 #define HWRM_DBG_USEQ_QCAPS UINT32_C(0xff26)
855 #define HWRM_DBG_USEQ_CW_CFG UINT32_C(0xff27)
857 #define HWRM_DBG_USEQ_SCHED_CFG UINT32_C(0xff28)
859 #define HWRM_DBG_USEQ_RUN UINT32_C(0xff29)
861 #define HWRM_DBG_USEQ_DELIVERY_REQ UINT32_C(0xff2a)
863 #define HWRM_DBG_USEQ_RESP_HDR UINT32_C(0xff2b)
864 #define HWRM_NVM_DEFRAG UINT32_C(0xffec)
865 #define HWRM_NVM_REQ_ARBITRATION UINT32_C(0xffed)
867 #define HWRM_NVM_FACTORY_DEFAULTS UINT32_C(0xffee)
868 #define HWRM_NVM_VALIDATE_OPTION UINT32_C(0xffef)
869 #define HWRM_NVM_FLUSH UINT32_C(0xfff0)
870 #define HWRM_NVM_GET_VARIABLE UINT32_C(0xfff1)
871 #define HWRM_NVM_SET_VARIABLE UINT32_C(0xfff2)
872 #define HWRM_NVM_INSTALL_UPDATE UINT32_C(0xfff3)
873 #define HWRM_NVM_MODIFY UINT32_C(0xfff4)
874 #define HWRM_NVM_VERIFY_UPDATE UINT32_C(0xfff5)
875 #define HWRM_NVM_GET_DEV_INFO UINT32_C(0xfff6)
876 #define HWRM_NVM_ERASE_DIR_ENTRY UINT32_C(0xfff7)
877 #define HWRM_NVM_MOD_DIR_ENTRY UINT32_C(0xfff8)
878 #define HWRM_NVM_FIND_DIR_ENTRY UINT32_C(0xfff9)
879 #define HWRM_NVM_GET_DIR_ENTRIES UINT32_C(0xfffa)
880 #define HWRM_NVM_GET_DIR_INFO UINT32_C(0xfffb)
881 #define HWRM_NVM_RAW_DUMP UINT32_C(0xfffc)
882 #define HWRM_NVM_READ UINT32_C(0xfffd)
883 #define HWRM_NVM_WRITE UINT32_C(0xfffe)
884 #define HWRM_NVM_RAW_WRITE_BLK UINT32_C(0xffff)
885 #define HWRM_LAST HWRM_NVM_RAW_WRITE_BLK
886 uint16_t unused_0[3];
890 /* ret_codes (size:64b/8B) */
893 /* Request was successfully executed by the HWRM. */
894 #define HWRM_ERR_CODE_SUCCESS UINT32_C(0x0)
895 /* The HWRM failed to execute the request. */
896 #define HWRM_ERR_CODE_FAIL UINT32_C(0x1)
898 * The request contains invalid argument(s) or input
901 #define HWRM_ERR_CODE_INVALID_PARAMS UINT32_C(0x2)
903 * The requester is not allowed to access the requested
904 * resource. This error code shall be provided in a
905 * response to a request to query or modify an existing
906 * resource that is not accessible by the requester.
908 #define HWRM_ERR_CODE_RESOURCE_ACCESS_DENIED UINT32_C(0x3)
910 * The HWRM is unable to allocate the requested resource.
911 * This code only applies to requests for HWRM resource
914 #define HWRM_ERR_CODE_RESOURCE_ALLOC_ERROR UINT32_C(0x4)
916 * Invalid combination of flags is specified in the
919 #define HWRM_ERR_CODE_INVALID_FLAGS UINT32_C(0x5)
921 * Invalid combination of enables fields is specified in
924 #define HWRM_ERR_CODE_INVALID_ENABLES UINT32_C(0x6)
926 * Request contains a required TLV that is not supported by
927 * the installed version of firmware.
929 #define HWRM_ERR_CODE_UNSUPPORTED_TLV UINT32_C(0x7)
931 * No firmware buffer available to accept the request. Driver
932 * should retry the request.
934 #define HWRM_ERR_CODE_NO_BUFFER UINT32_C(0x8)
936 * This error code is only reported by firmware when some
937 * sub-option of a supported HWRM command is unsupported.
939 #define HWRM_ERR_CODE_UNSUPPORTED_OPTION_ERR UINT32_C(0x9)
941 * This error code is only reported by firmware when the specific
942 * request is not able to process when the HOT reset in progress.
944 #define HWRM_ERR_CODE_HOT_RESET_PROGRESS UINT32_C(0xa)
946 * This error code is only reported by firmware when the registered
947 * driver instances are not capable of hot reset.
949 #define HWRM_ERR_CODE_HOT_RESET_FAIL UINT32_C(0xb)
951 * This error code is only reported by the firmware when during
952 * flow allocation when a request for a flow counter fails because
953 * the number of flow counters are exhausted.
955 #define HWRM_ERR_CODE_NO_FLOW_COUNTER_DURING_ALLOC UINT32_C(0xc)
957 * This error code is only reported by firmware when the registered
958 * driver instances requested to offloaded a flow but was unable to because
959 * the requested key's hash collides with the installed keys.
961 #define HWRM_ERR_CODE_KEY_HASH_COLLISION UINT32_C(0xd)
963 * This error code is only reported by firmware when the registered
964 * driver instances requested to offloaded a flow but was unable to because
965 * the same key has already been installed.
967 #define HWRM_ERR_CODE_KEY_ALREADY_EXISTS UINT32_C(0xe)
969 * Generic HWRM execution error that represents an
972 #define HWRM_ERR_CODE_HWRM_ERROR UINT32_C(0xf)
974 * Firmware is unable to service the request at the present time. Caller
975 * may try again later.
977 #define HWRM_ERR_CODE_BUSY UINT32_C(0x10)
979 * This error code is reported by Firmware when an operation requested
980 * by the host is not allowed due to a secure lock violation.
982 #define HWRM_ERR_CODE_RESOURCE_LOCKED UINT32_C(0x11)
984 * This error code is reported by Firmware when an operation requested
985 * by a VF cannot be forwarded to the parent PF as required, either
986 * because the PF is down or otherwise doesn't have an appropriate
987 * async completion ring or associated forwarding buffers configured.
989 #define HWRM_ERR_CODE_PF_UNAVAILABLE UINT32_C(0x12)
991 * This value indicates that the HWRM response is in TLV format and
992 * should be interpreted as one or more TLVs starting with the
993 * hwrm_resp_hdr TLV. This value is not an indication of any error
994 * by itself, just an indication that the response should be parsed
995 * as TLV and the actual error code will be in the hwrm_resp_hdr TLV.
997 #define HWRM_ERR_CODE_TLV_ENCAPSULATED_RESPONSE UINT32_C(0x8000)
999 #define HWRM_ERR_CODE_UNKNOWN_ERR UINT32_C(0xfffe)
1000 /* Unsupported or invalid command */
1001 #define HWRM_ERR_CODE_CMD_NOT_SUPPORTED UINT32_C(0xffff)
1002 #define HWRM_ERR_CODE_LAST \
1003 HWRM_ERR_CODE_CMD_NOT_SUPPORTED
1004 uint16_t unused_0[3];
1008 /* hwrm_err_output (size:128b/16B) */
1009 struct hwrm_err_output {
1011 * Pass/Fail or error type
1013 * Note: receiver to verify the in parameters, and fail the call
1014 * with an error when appropriate
1016 uint16_t error_code;
1017 /* This field returns the type of original request. */
1019 /* This field provides original sequence number of the command. */
1022 * This field is the length of the response in bytes. The
1023 * last byte of the response is a valid flag that will read
1024 * as '1' when the command has been completely written to
1028 /* debug info for this error response. */
1030 /* debug info for this error response. */
1033 * In the case of an error response, command specific error
1034 * code is returned in this field.
1038 * This field is used in Output records to indicate that the output
1039 * is completely written to RAM. This field should be read as '1'
1040 * to indicate that the output has been completely written.
1041 * When writing a command completion or response to an internal processor,
1042 * the order of writes has to be such that this field is written last.
1047 * Following is the signature for HWRM message field that indicates not
1048 * applicable (All F's). Need to cast it the size of the field if needed.
1050 #define HWRM_NA_SIGNATURE ((uint32_t)(-1))
1051 /* hwrm_func_buf_rgtr */
1052 #define HWRM_MAX_REQ_LEN 128
1053 /* hwrm_cfa_flow_info */
1054 #define HWRM_MAX_RESP_LEN 704
1055 /* 7 bit indirection table index. */
1056 #define HW_HASH_INDEX_SIZE 0x80
1057 #define HW_HASH_KEY_SIZE 40
1058 /* valid key for HWRM response */
1059 #define HWRM_RESP_VALID_KEY 1
1060 /* Reserved for BONO processor */
1061 #define HWRM_TARGET_ID_BONO 0xFFF8
1062 /* Reserved for KONG processor */
1063 #define HWRM_TARGET_ID_KONG 0xFFF9
1064 /* Reserved for APE processor */
1065 #define HWRM_TARGET_ID_APE 0xFFFA
1067 * This value will be used by tools for User-space HWRM Interface.
1068 * When tool execute any HWRM command with this target_id, firmware
1069 * will copy the response and/or data payload via register space instead
1072 #define HWRM_TARGET_ID_TOOLS 0xFFFD
1073 #define HWRM_VERSION_MAJOR 1
1074 #define HWRM_VERSION_MINOR 10
1075 #define HWRM_VERSION_UPDATE 2
1076 /* non-zero means beta version */
1077 #define HWRM_VERSION_RSVD 68
1078 #define HWRM_VERSION_STR "1.10.2.68"
1085 /* hwrm_ver_get_input (size:192b/24B) */
1086 struct hwrm_ver_get_input {
1087 /* The HWRM command request type. */
1090 * The completion ring to send the completion event on. This should
1091 * be the NQ ID returned from the `nq_alloc` HWRM command.
1095 * The sequence ID is used by the driver for tracking multiple
1096 * commands. This ID is treated as opaque data by the firmware and
1097 * the value is returned in the `hwrm_resp_hdr` upon completion.
1101 * The target ID of the command:
1102 * * 0x0-0xFFF8 - The function ID
1103 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
1104 * * 0xFFFD - Reserved for user-space HWRM interface
1109 * A physical address pointer pointing to a host buffer that the
1110 * command's response data will be written. This can be either a host
1111 * physical address (HPA) or a guest physical address (GPA) and must
1112 * point to a physically contiguous block of memory.
1116 * This field represents the major version of HWRM interface
1117 * specification supported by the driver HWRM implementation.
1118 * The interface major version is intended to change only when
1119 * non backward compatible changes are made to the HWRM
1120 * interface specification.
1122 uint8_t hwrm_intf_maj;
1124 * This field represents the minor version of HWRM interface
1125 * specification supported by the driver HWRM implementation.
1126 * A change in interface minor version is used to reflect
1127 * significant backward compatible modification to HWRM
1128 * interface specification.
1129 * This can be due to addition or removal of functionality.
1130 * HWRM interface specifications with the same major version
1131 * but different minor versions are compatible.
1133 uint8_t hwrm_intf_min;
1135 * This field represents the update version of HWRM interface
1136 * specification supported by the driver HWRM implementation.
1137 * The interface update version is used to reflect minor
1138 * changes or bug fixes to a released HWRM interface
1141 uint8_t hwrm_intf_upd;
1142 uint8_t unused_0[5];
1145 /* hwrm_ver_get_output (size:1408b/176B) */
1146 struct hwrm_ver_get_output {
1147 /* The specific error status for the command. */
1148 uint16_t error_code;
1149 /* The HWRM command request type. */
1151 /* The sequence ID from the original command. */
1153 /* The length of the response data in number of bytes. */
1156 * This field represents the major version of HWRM interface
1157 * specification supported by the HWRM implementation.
1158 * The interface major version is intended to change only when
1159 * non backward compatible changes are made to the HWRM
1160 * interface specification.
1161 * A HWRM implementation that is compliant with this
1162 * specification shall provide value of 1 in this field.
1164 uint8_t hwrm_intf_maj_8b;
1166 * This field represents the minor version of HWRM interface
1167 * specification supported by the HWRM implementation.
1168 * A change in interface minor version is used to reflect
1169 * significant backward compatible modification to HWRM
1170 * interface specification.
1171 * This can be due to addition or removal of functionality.
1172 * HWRM interface specifications with the same major version
1173 * but different minor versions are compatible.
1174 * A HWRM implementation that is compliant with this
1175 * specification shall provide value of 2 in this field.
1177 uint8_t hwrm_intf_min_8b;
1179 * This field represents the update version of HWRM interface
1180 * specification supported by the HWRM implementation.
1181 * The interface update version is used to reflect minor
1182 * changes or bug fixes to a released HWRM interface
1184 * A HWRM implementation that is compliant with this
1185 * specification shall provide value of 2 in this field.
1187 uint8_t hwrm_intf_upd_8b;
1188 uint8_t hwrm_intf_rsvd_8b;
1190 * This field represents the major version of HWRM firmware.
1191 * A change in firmware major version represents a major
1194 uint8_t hwrm_fw_maj_8b;
1196 * This field represents the minor version of HWRM firmware.
1197 * A change in firmware minor version represents significant
1198 * firmware functionality changes.
1200 uint8_t hwrm_fw_min_8b;
1202 * This field represents the build version of HWRM firmware.
1203 * A change in firmware build version represents bug fixes
1204 * to a released firmware.
1206 uint8_t hwrm_fw_bld_8b;
1208 * This field is a reserved field. This field can be used to
1209 * represent firmware branches or customer specific releases
1210 * tied to a specific (major,minor,update) version of the
1213 uint8_t hwrm_fw_rsvd_8b;
1215 * This field represents the major version of mgmt firmware.
1216 * A change in major version represents a major release.
1218 uint8_t mgmt_fw_maj_8b;
1220 * This field represents the minor version of mgmt firmware.
1221 * A change in minor version represents significant
1222 * functionality changes.
1224 uint8_t mgmt_fw_min_8b;
1226 * This field represents the build version of mgmt firmware.
1227 * A change in update version represents bug fixes.
1229 uint8_t mgmt_fw_bld_8b;
1231 * This field is a reserved field. This field can be used to
1232 * represent firmware branches or customer specific releases
1233 * tied to a specific (major,minor,update) version
1235 uint8_t mgmt_fw_rsvd_8b;
1237 * This field represents the major version of network
1239 * A change in major version represents a major release.
1241 uint8_t netctrl_fw_maj_8b;
1243 * This field represents the minor version of network
1245 * A change in minor version represents significant
1246 * functionality changes.
1248 uint8_t netctrl_fw_min_8b;
1250 * This field represents the build version of network
1252 * A change in update version represents bug fixes.
1254 uint8_t netctrl_fw_bld_8b;
1256 * This field is a reserved field. This field can be used to
1257 * represent firmware branches or customer specific releases
1258 * tied to a specific (major,minor,update) version
1260 uint8_t netctrl_fw_rsvd_8b;
1262 * This field is used to indicate device's capabilities and
1265 uint32_t dev_caps_cfg;
1267 * If set to 1, then secure firmware update behavior
1269 * If set to 0, then secure firmware update behavior is
1272 #define HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_SECURE_FW_UPD_SUPPORTED \
1275 * If set to 1, then firmware based DCBX agent is supported.
1276 * If set to 0, then firmware based DCBX agent capability
1277 * is not supported on this device.
1279 #define HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_FW_DCBX_AGENT_SUPPORTED \
1282 * If set to 1, then HWRM short command format is supported.
1283 * If set to 0, then HWRM short command format is not supported.
1285 #define HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_SHORT_CMD_SUPPORTED \
1288 * If set to 1, then HWRM short command format is required.
1289 * If set to 0, then HWRM short command format is not required.
1291 #define HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_SHORT_CMD_REQUIRED \
1294 * If set to 1, then the KONG host mailbox channel is supported.
1295 * If set to 0, then the KONG host mailbox channel is not supported.
1296 * By default, this flag should be 0 for older version of core firmware.
1298 #define HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_KONG_MB_CHNL_SUPPORTED \
1301 * If set to 1, then the 64bit flow handle is supported in addition to the
1302 * legacy 16bit flow handle. If set to 0, then the 64bit flow handle is not
1303 * supported. By default, this flag should be 0 for older version of core firmware.
1305 #define HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_FLOW_HANDLE_64BIT_SUPPORTED \
1308 * If set to 1, then filter type can be provided in filter_alloc or filter_cfg
1309 * filter types like L2 for l2 traffic and ROCE for roce & l2 traffic.
1310 * If set to 0, then filter types not supported.
1311 * By default, this flag should be 0 for older version of core firmware.
1313 #define HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_L2_FILTER_TYPES_ROCE_OR_L2_SUPPORTED \
1316 * If set to 1, firmware is capable to support virtio vSwitch offload model.
1317 * If set to 0, firmware can't supported virtio vSwitch offload model.
1318 * By default, this flag should be 0 for older version of core firmware.
1320 #define HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_VIRTIO_VSWITCH_OFFLOAD_SUPPORTED \
1323 * If set to 1, firmware is capable to support trusted VF.
1324 * If set to 0, firmware is not capable to support trusted VF.
1325 * By default, this flag should be 0 for older version of core firmware.
1327 #define HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_TRUSTED_VF_SUPPORTED \
1330 * If set to 1, firmware is capable to support flow aging.
1331 * If set to 0, firmware is not capable to support flow aging.
1332 * By default, this flag should be 0 for older version of core firmware.
1334 #define HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_FLOW_AGING_SUPPORTED \
1337 * If set to 1, firmware is capable to support advanced flow counters like,
1338 * Meter drop counters and EEM counters.
1339 * If set to 0, firmware is not capable to support advanced flow counters.
1340 * By default, this flag should be 0 for older version of core firmware.
1342 #define HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_ADV_FLOW_COUNTERS_SUPPORTED \
1345 * If set to 1, the firmware is able to support the use of the CFA
1346 * Extended Exact Match(EEM) feature.
1347 * If set to 0, firmware is not capable to support the use of the
1349 * By default, this flag should be 0 for older version of core firmware.
1351 #define HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_CFA_EEM_SUPPORTED \
1354 * If set to 1, the firmware is able to support advance CFA flow management
1355 * features reported in the HWRM_CFA_FLOW_MGNT_QCAPS.
1356 * If set to 0, then the firmware doesn’t support the advance CFA flow management
1358 * By default, this flag should be 0 for older version of core firmware.
1360 #define HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_CFA_ADV_FLOW_MGNT_SUPPORTED \
1363 * Deprecated and replaced with cfa_truflow_supported.
1364 * If set to 1, the firmware is able to support TFLIB features.
1365 * If set to 0, then the firmware doesn’t support TFLIB features.
1366 * By default, this flag should be 0 for older version of core firmware.
1368 #define HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_CFA_TFLIB_SUPPORTED \
1371 * If set to 1, the firmware is able to support TruFlow features.
1372 * If set to 0, then the firmware doesn’t support TruFlow features.
1373 * By default, this flag should be 0 for older version of
1376 #define HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_CFA_TRUFLOW_SUPPORTED \
1379 * If set to 1, then firmware supports secure boot.
1380 * If set to 0, then firmware doesn't support secure boot.
1382 #define HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_SECURE_BOOT_CAPABLE \
1385 * This field represents the major version of RoCE firmware.
1386 * A change in major version represents a major release.
1388 uint8_t roce_fw_maj_8b;
1390 * This field represents the minor version of RoCE firmware.
1391 * A change in minor version represents significant
1392 * functionality changes.
1394 uint8_t roce_fw_min_8b;
1396 * This field represents the build version of RoCE firmware.
1397 * A change in update version represents bug fixes.
1399 uint8_t roce_fw_bld_8b;
1401 * This field is a reserved field. This field can be used to
1402 * represent firmware branches or customer specific releases
1403 * tied to a specific (major,minor,update) version
1405 uint8_t roce_fw_rsvd_8b;
1407 * This field represents the name of HWRM FW (ASCII chars
1408 * with NULL at the end).
1410 char hwrm_fw_name[16];
1412 * This field represents the name of mgmt FW (ASCII chars
1413 * with NULL at the end).
1415 char mgmt_fw_name[16];
1417 * This field represents the name of network control
1418 * firmware (ASCII chars with NULL at the end).
1420 char netctrl_fw_name[16];
1421 /* This field represents the active board package name. */
1422 char active_pkg_name[16];
1424 * This field represents the name of RoCE FW (ASCII chars
1425 * with NULL at the end).
1427 char roce_fw_name[16];
1428 /* This field returns the chip number. */
1430 /* This field returns the revision of chip. */
1432 /* This field returns the chip metal number. */
1434 /* This field returns the bond id of the chip. */
1435 uint8_t chip_bond_id;
1436 /* This value indicates the type of platform used for chip implementation. */
1437 uint8_t chip_platform_type;
1439 #define HWRM_VER_GET_OUTPUT_CHIP_PLATFORM_TYPE_ASIC UINT32_C(0x0)
1440 /* FPGA platform of the chip. */
1441 #define HWRM_VER_GET_OUTPUT_CHIP_PLATFORM_TYPE_FPGA UINT32_C(0x1)
1442 /* Palladium platform of the chip. */
1443 #define HWRM_VER_GET_OUTPUT_CHIP_PLATFORM_TYPE_PALLADIUM UINT32_C(0x2)
1444 #define HWRM_VER_GET_OUTPUT_CHIP_PLATFORM_TYPE_LAST \
1445 HWRM_VER_GET_OUTPUT_CHIP_PLATFORM_TYPE_PALLADIUM
1447 * This field returns the maximum value of request window that
1448 * is supported by the HWRM. The request window is mapped
1449 * into device address space using MMIO.
1451 uint16_t max_req_win_len;
1453 * This field returns the maximum value of response buffer in
1456 uint16_t max_resp_len;
1458 * This field returns the default request timeout value in
1461 uint16_t def_req_timeout;
1463 * This field will indicate if any subsystems is not fully
1468 * If set to 1, it will indicate to host drivers that firmware is
1469 * not ready to start full blown HWRM commands. Host drivers should
1470 * re-try HWRM_VER_GET with some timeout period. The timeout period
1471 * can be selected up to 5 seconds. Host drivers should also check
1472 * for dev_not_rdy_backing_store to identify if flag is set due to
1473 * backing store not been available.
1474 * For Example, PCIe hot-plug:
1475 * Hot plug timing is system dependent. It generally takes up to
1476 * 600 milliseconds for firmware to clear DEV_NOT_RDY flag.
1477 * If set to 0, device is ready to accept all HWRM commands.
1479 #define HWRM_VER_GET_OUTPUT_FLAGS_DEV_NOT_RDY \
1482 * If set to 1, external version present.
1483 * If set to 0, external version not present.
1485 #define HWRM_VER_GET_OUTPUT_FLAGS_EXT_VER_AVAIL \
1488 * Firmware sets this flag along with dev_not_rdy flag to indicate
1489 * host drivers that it has not completed resource initialization
1490 * required for data path operations. Host drivers should not send
1491 * any HWRM command that requires data path resources. Firmware will
1492 * fail those commands with HWRM_ERR_CODE_BUSY. Host drivers can retry
1493 * those commands once both the flags are cleared.
1494 * If this flag and dev_not_rdy flag are set to 0, device is ready
1495 * to accept all HWRM commands.
1497 #define HWRM_VER_GET_OUTPUT_FLAGS_DEV_NOT_RDY_BACKING_STORE \
1499 uint8_t unused_0[2];
1501 * For backward compatibility this field must be set to 1.
1502 * Older drivers might look for this field to be 1 before
1503 * processing the message.
1507 * This field represents the major version of HWRM interface
1508 * specification supported by the HWRM implementation.
1509 * The interface major version is intended to change only when
1510 * non backward compatible changes are made to the HWRM
1511 * interface specification. A HWRM implementation that is
1512 * compliant with this specification shall provide value of 1
1515 uint16_t hwrm_intf_major;
1517 * This field represents the minor version of HWRM interface
1518 * specification supported by the HWRM implementation.
1519 * A change in interface minor version is used to reflect
1520 * significant backward compatible modification to HWRM
1521 * interface specification. This can be due to addition or
1522 * removal of functionality. HWRM interface specifications
1523 * with the same major version but different minor versions are
1524 * compatible. A HWRM implementation that is compliant with
1525 * this specification shall provide value of 2 in this field.
1527 uint16_t hwrm_intf_minor;
1529 * This field represents the update version of HWRM interface
1530 * specification supported by the HWRM implementation. The
1531 * interface update version is used to reflect minor changes or
1532 * bug fixes to a released HWRM interface specification.
1533 * A HWRM implementation that is compliant with this
1534 * specification shall provide value of 2 in this field.
1536 uint16_t hwrm_intf_build;
1538 * This field represents the patch version of HWRM interface
1539 * specification supported by the HWRM implementation.
1541 uint16_t hwrm_intf_patch;
1543 * This field represents the major version of HWRM firmware.
1544 * A change in firmware major version represents a major
1547 uint16_t hwrm_fw_major;
1549 * This field represents the minor version of HWRM firmware.
1550 * A change in firmware minor version represents significant
1551 * firmware functionality changes.
1553 uint16_t hwrm_fw_minor;
1555 * This field represents the build version of HWRM firmware.
1556 * A change in firmware build version represents bug fixes to
1557 * a released firmware.
1559 uint16_t hwrm_fw_build;
1561 * This field is a reserved field.
1562 * This field can be used to represent firmware branches or customer
1563 * specific releases tied to a specific (major,minor,update) version
1564 * of the HWRM firmware.
1566 uint16_t hwrm_fw_patch;
1568 * This field represents the major version of mgmt firmware.
1569 * A change in major version represents a major release.
1571 uint16_t mgmt_fw_major;
1573 * This field represents the minor version of HWRM firmware.
1574 * A change in firmware minor version represents significant
1575 * firmware functionality changes.
1577 uint16_t mgmt_fw_minor;
1579 * This field represents the build version of mgmt firmware.
1580 * A change in update version represents bug fixes.
1582 uint16_t mgmt_fw_build;
1584 * This field is a reserved field. This field can be used to
1585 * represent firmware branches or customer specific releases
1586 * tied to a specific (major,minor,update) version.
1588 uint16_t mgmt_fw_patch;
1590 * This field represents the major version of network control
1591 * firmware. A change in major version represents
1594 uint16_t netctrl_fw_major;
1596 * This field represents the minor version of network control
1597 * firmware. A change in minor version represents significant
1598 * functionality changes.
1600 uint16_t netctrl_fw_minor;
1602 * This field represents the build version of network control
1603 * firmware. A change in update version represents bug fixes.
1605 uint16_t netctrl_fw_build;
1607 * This field is a reserved field. This field can be used to
1608 * represent firmware branches or customer specific releases
1609 * tied to a specific (major,minor,update) version
1611 uint16_t netctrl_fw_patch;
1613 * This field represents the major version of RoCE firmware.
1614 * A change in major version represents a major release.
1616 uint16_t roce_fw_major;
1618 * This field represents the minor version of RoCE firmware.
1619 * A change in minor version represents significant
1620 * functionality changes.
1622 uint16_t roce_fw_minor;
1624 * This field represents the build version of RoCE firmware.
1625 * A change in update version represents bug fixes.
1627 uint16_t roce_fw_build;
1629 * This field is a reserved field. This field can be used to
1630 * represent firmware branches or customer specific releases
1631 * tied to a specific (major,minor,update) version
1633 uint16_t roce_fw_patch;
1635 * This field returns the maximum extended request length acceptable
1636 * by the device which allows requests greater than mailbox size when
1637 * used with the short cmd request format.
1639 uint16_t max_ext_req_len;
1641 * This field returns the maximum request timeout value in seconds.
1642 * For backward compatibility, a value of zero should be interpreted
1643 * as the default value of 40 seconds. Drivers should always honor the
1644 * maximum timeout, but are permitted to warn if a longer duration than
1645 * this default is advertised. Values larger than 40 seconds should
1646 * only be used as a stopgap measure to address a device limitation or
1647 * for the purposes of test and debugging. The long term goal is for
1648 * firmware to significantly reduce this value in the passage of time.
1650 uint16_t max_req_timeout;
1651 uint8_t unused_1[3];
1653 * This field is used in Output records to indicate that the output
1654 * is completely written to RAM. This field should be read as '1'
1655 * to indicate that the output has been completely written.
1656 * When writing a command completion or response to an internal processor,
1657 * the order of writes has to be such that this field is written last.
1662 /* cfa_bds_read_cmd_data_msg (size:128b/16B) */
1663 struct cfa_bds_read_cmd_data_msg {
1664 /* This value selects the format for the mid-path command for the CFA. */
1667 * This is read command. From 32 to 128B can be read from a table
1668 * using this command.
1670 #define CFA_BDS_READ_CMD_DATA_MSG_OPCODE_READ UINT32_C(0x0)
1671 #define CFA_BDS_READ_CMD_DATA_MSG_OPCODE_LAST \
1672 CFA_BDS_READ_CMD_DATA_MSG_OPCODE_READ
1673 /* This value selects the table type to be acted upon. */
1675 /* This value selects the table type to be acted upon. */
1676 #define CFA_BDS_READ_CMD_DATA_MSG_TABLE_TYPE_MASK UINT32_C(0xf)
1677 #define CFA_BDS_READ_CMD_DATA_MSG_TABLE_TYPE_SFT 0
1678 /* This command acts on the action table of the specified scope. */
1679 #define CFA_BDS_READ_CMD_DATA_MSG_TABLE_TYPE_ACTION UINT32_C(0x0)
1680 /* This command acts on the exact match table of the specified scope. */
1681 #define CFA_BDS_READ_CMD_DATA_MSG_TABLE_TYPE_EM UINT32_C(0x1)
1682 #define CFA_BDS_READ_CMD_DATA_MSG_TABLE_TYPE_LAST \
1683 CFA_BDS_READ_CMD_DATA_MSG_TABLE_TYPE_EM
1684 /* This value selects which table scope will be accessed. */
1685 uint8_t table_scope;
1686 #define CFA_BDS_READ_CMD_DATA_MSG_TABLE_SCOPE_MASK UINT32_C(0x1f)
1687 #define CFA_BDS_READ_CMD_DATA_MSG_TABLE_SCOPE_SFT 0
1689 * This value identifies the number of 32B units will be accessed. A
1690 * value of zero is invalid. Maximum value is 4.
1693 #define CFA_BDS_READ_CMD_DATA_MSG_DATA_SIZE_MASK UINT32_C(0x7)
1694 #define CFA_BDS_READ_CMD_DATA_MSG_DATA_SIZE_SFT 0
1695 /* This is the 32B index into the selected table to access. */
1696 uint32_t table_index;
1697 #define CFA_BDS_READ_CMD_DATA_MSG_TABLE_INDEX_MASK UINT32_C(0x3ffffff)
1698 #define CFA_BDS_READ_CMD_DATA_MSG_TABLE_INDEX_SFT 0
1700 * This is the 64b host address where you want the data returned to. The
1701 * data will be written to the same function as the one that owns the SQ
1702 * this command is read from. The bottom two bits of this value must be
1703 * zero. The size of the write is controlled by the data_size field.
1705 uint64_t host_address;
1708 /* cfa_bds_write_cmd_data_msg (size:1152b/144B) */
1709 struct cfa_bds_write_cmd_data_msg {
1710 /* This value selects the format for the mid-path command for the CFA. */
1713 * This is write command. From 32 to 128B can be written to a table
1714 * using this command.
1716 #define CFA_BDS_WRITE_CMD_DATA_MSG_OPCODE_WRITE UINT32_C(0x1)
1717 #define CFA_BDS_WRITE_CMD_DATA_MSG_OPCODE_LAST \
1718 CFA_BDS_WRITE_CMD_DATA_MSG_OPCODE_WRITE
1719 /* This value selects the table type to be acted upon. */
1720 uint8_t write_thru_table_type;
1721 /* This value selects the table type to be acted upon. */
1722 #define CFA_BDS_WRITE_CMD_DATA_MSG_TABLE_TYPE_MASK UINT32_C(0xf)
1723 #define CFA_BDS_WRITE_CMD_DATA_MSG_TABLE_TYPE_SFT 0
1724 /* This command acts on the action table of the specified scope. */
1725 #define CFA_BDS_WRITE_CMD_DATA_MSG_TABLE_TYPE_ACTION UINT32_C(0x0)
1726 /* This command acts on the exact match table of the specified scope. */
1727 #define CFA_BDS_WRITE_CMD_DATA_MSG_TABLE_TYPE_EM UINT32_C(0x1)
1728 #define CFA_BDS_WRITE_CMD_DATA_MSG_TABLE_TYPE_LAST \
1729 CFA_BDS_WRITE_CMD_DATA_MSG_TABLE_TYPE_EM
1731 * Indicates write-through control. Indicates write-through when set,
1732 * or write back when cleared.
1734 #define CFA_BDS_WRITE_CMD_DATA_MSG_WRITE_THRU UINT32_C(0x10)
1735 /* This value selects which table scope will be accessed. */
1736 uint8_t table_scope;
1737 #define CFA_BDS_WRITE_CMD_DATA_MSG_TABLE_SCOPE_MASK UINT32_C(0x1f)
1738 #define CFA_BDS_WRITE_CMD_DATA_MSG_TABLE_SCOPE_SFT 0
1740 * This value identifies the number of 32B units will be accessed. A
1741 * value of zero is invalid. Maximum value is 4.
1744 #define CFA_BDS_WRITE_CMD_DATA_MSG_DATA_SIZE_MASK UINT32_C(0x7)
1745 #define CFA_BDS_WRITE_CMD_DATA_MSG_DATA_SIZE_SFT 0
1746 /* This is the 32B index into the selected table to access. */
1747 uint32_t table_index;
1748 #define CFA_BDS_WRITE_CMD_DATA_MSG_TABLE_INDEX_MASK UINT32_C(0x3ffffff)
1749 #define CFA_BDS_WRITE_CMD_DATA_MSG_TABLE_INDEX_SFT 0
1753 * This is the data to be written. Data length is determined by the
1754 * data_size field. The bd_cnt in the encapsulating BD must also be set
1755 * correctly to ensure that the BD is processed correctly and the full
1756 * WRITE_CMD message is extracted from the BD.
1761 /* cfa_bds_read_clr_cmd_data_msg (size:256b/32B) */
1762 struct cfa_bds_read_clr_cmd_data_msg {
1763 /* This value selects the format for the mid-path command for the CFA. */
1766 * This is read-clear command. 32B can be read from a table and
1767 * a 16b mask can be used to clear specific 16b units after the
1768 * read as an atomic operation.
1770 #define CFA_BDS_READ_CLR_CMD_DATA_MSG_OPCODE_READ_CLR UINT32_C(0x2)
1771 #define CFA_BDS_READ_CLR_CMD_DATA_MSG_OPCODE_LAST \
1772 CFA_BDS_READ_CLR_CMD_DATA_MSG_OPCODE_READ_CLR
1773 /* This value selects the table type to be acted upon. */
1775 /* This value selects the table type to be acted upon. */
1776 #define CFA_BDS_READ_CLR_CMD_DATA_MSG_TABLE_TYPE_MASK UINT32_C(0xf)
1777 #define CFA_BDS_READ_CLR_CMD_DATA_MSG_TABLE_TYPE_SFT 0
1778 /* This command acts on the action table of the specified scope. */
1779 #define CFA_BDS_READ_CLR_CMD_DATA_MSG_TABLE_TYPE_ACTION UINT32_C(0x0)
1780 /* This command acts on the exact match table of the specified scope. */
1781 #define CFA_BDS_READ_CLR_CMD_DATA_MSG_TABLE_TYPE_EM UINT32_C(0x1)
1782 #define CFA_BDS_READ_CLR_CMD_DATA_MSG_TABLE_TYPE_LAST \
1783 CFA_BDS_READ_CLR_CMD_DATA_MSG_TABLE_TYPE_EM
1784 /* This value selects which table scope will be accessed. */
1785 uint8_t table_scope;
1786 #define CFA_BDS_READ_CLR_CMD_DATA_MSG_TABLE_SCOPE_MASK UINT32_C(0x1f)
1787 #define CFA_BDS_READ_CLR_CMD_DATA_MSG_TABLE_SCOPE_SFT 0
1789 * This value identifies the number of 32B units will be accessed.
1790 * Always set the value to 1.
1793 #define CFA_BDS_READ_CLR_CMD_DATA_MSG_DATA_SIZE_MASK UINT32_C(0x7)
1794 #define CFA_BDS_READ_CLR_CMD_DATA_MSG_DATA_SIZE_SFT 0
1795 /* This is the 32B index into the selected table to access. */
1796 uint32_t table_index;
1797 #define CFA_BDS_READ_CLR_CMD_DATA_MSG_TABLE_INDEX_MASK \
1799 #define CFA_BDS_READ_CLR_CMD_DATA_MSG_TABLE_INDEX_SFT 0
1801 * This is the 64b host address where you want the data returned to. The
1802 * data will be written to the same function as the one that owns the SQ
1803 * this command is read from. The bottom two bits of this value must be
1804 * zero. The size of the write is controlled by the data_size field.
1806 uint64_t host_address;
1808 * This is active high clear mask for the 32B of data that this command
1809 * can read. Bit 0 of the field will clear bits 15:0 of the first word
1810 * of data read when set to '1'.
1812 uint16_t clear_mask;
1813 uint16_t unused0[3];
1814 uint16_t unused1[4];
1817 /* cfa_bds_em_insert_cmd_data_msg (size:1152b/144B) */
1818 struct cfa_bds_em_insert_cmd_data_msg {
1819 /* This value selects the format for the mid-path command for the CFA. */
1822 * An exact match table insert will be attempted into the table.
1823 * If there is a free location in the bucket, the payload will
1824 * be written to the bucket.
1826 #define CFA_BDS_EM_INSERT_CMD_DATA_MSG_OPCODE_EM_INSERT UINT32_C(0x3)
1827 #define CFA_BDS_EM_INSERT_CMD_DATA_MSG_OPCODE_LAST \
1828 CFA_BDS_EM_INSERT_CMD_DATA_MSG_OPCODE_EM_INSERT
1830 * Indicates write-through control. Indicates write-through when set,
1831 * or write back when cleared.
1834 #define CFA_BDS_EM_INSERT_CMD_DATA_MSG_UNUSED_MASK UINT32_C(0xf)
1835 #define CFA_BDS_EM_INSERT_CMD_DATA_MSG_UNUSED_SFT 0
1837 * Indicates write-through control. Indicates write-through when set,
1838 * or write back when cleared.
1840 #define CFA_BDS_EM_INSERT_CMD_DATA_MSG_WRITE_THRU UINT32_C(0x10)
1841 /* This value selects which table scope will be accessed. */
1842 uint8_t table_scope;
1843 #define CFA_BDS_EM_INSERT_CMD_DATA_MSG_TABLE_SCOPE_MASK UINT32_C(0x1f)
1844 #define CFA_BDS_EM_INSERT_CMD_DATA_MSG_TABLE_SCOPE_SFT 0
1846 * This value identifies the number of 32B units will be accessed. A
1847 * value of zero is invalid. Maximum value is 4.
1850 #define CFA_BDS_EM_INSERT_CMD_DATA_MSG_DATA_SIZE_MASK UINT32_C(0x7)
1851 #define CFA_BDS_EM_INSERT_CMD_DATA_MSG_DATA_SIZE_SFT 0
1852 /* This is the 32B index into the selected table to access. */
1853 uint32_t table_index;
1854 #define CFA_BDS_EM_INSERT_CMD_DATA_MSG_TABLE_INDEX_MASK \
1856 #define CFA_BDS_EM_INSERT_CMD_DATA_MSG_TABLE_INDEX_SFT 0
1858 * This is the 64b host address where you want the data returned to. The
1859 * data will be written to the same function as the one that owns the SQ
1861 uint64_t host_address;
1863 * This is the Exact Match Lookup Record. Data length is determined by
1864 * the data_size field. The bd_cnt in the encapsulating BD must also be
1869 /* cfa_bds_em_delete_cmd_data_msg (size:256b/32B) */
1870 struct cfa_bds_em_delete_cmd_data_msg {
1871 /* This value selects the format for the mid-path command for the CFA. */
1873 /* An exact match table delete will be attempted. */
1874 #define CFA_BDS_EM_DELETE_CMD_DATA_MSG_OPCODE_EM_DELETE UINT32_C(0x4)
1875 #define CFA_BDS_EM_DELETE_CMD_DATA_MSG_OPCODE_LAST \
1876 CFA_BDS_EM_DELETE_CMD_DATA_MSG_OPCODE_EM_DELETE
1878 * Indicates write-through control. Indicates write-through when set,
1879 * or write back when cleared.
1882 #define CFA_BDS_EM_DELETE_CMD_DATA_MSG_UNUSED_MASK UINT32_C(0xf)
1883 #define CFA_BDS_EM_DELETE_CMD_DATA_MSG_UNUSED_SFT 0
1885 * Indicates write-through control. Indicates write-through when set,
1886 * or write back when cleared.
1888 #define CFA_BDS_EM_DELETE_CMD_DATA_MSG_WRITE_THRU UINT32_C(0x10)
1889 /* This value selects which table scope will be accessed. */
1890 uint8_t table_scope;
1891 #define CFA_BDS_EM_DELETE_CMD_DATA_MSG_TABLE_SCOPE_MASK UINT32_C(0x1f)
1892 #define CFA_BDS_EM_DELETE_CMD_DATA_MSG_TABLE_SCOPE_SFT 0
1894 * This value identifies the number of 32B units will be accessed. A
1895 * value of zero is invalid. Maximum value is 4.
1898 #define CFA_BDS_EM_DELETE_CMD_DATA_MSG_DATA_SIZE_MASK UINT32_C(0x7)
1899 #define CFA_BDS_EM_DELETE_CMD_DATA_MSG_DATA_SIZE_SFT 0
1902 * This is the 64b host address where you want the data returned to. The
1903 * data will be written to the same function as the one that owns the SQ
1905 uint64_t host_address;
1907 * This is the Exact Match Lookup Record. Data length is determined by
1908 * the data_size field. The bd_cnt in the encapsulating BD must also be
1911 uint32_t unused1[2];
1914 /* cfa_bds_invalidate_cmd_data_msg (size:128b/16B) */
1915 struct cfa_bds_invalidate_cmd_data_msg {
1916 /* This value selects the format for the mid-path command for the CFA. */
1919 * The specified table area will be invalidated. If it is needed.
1920 * again, it will be read from the backing store.
1922 #define CFA_BDS_INVALIDATE_CMD_DATA_MSG_OPCODE_INVALIDATE UINT32_C(0x5)
1923 #define CFA_BDS_INVALIDATE_CMD_DATA_MSG_OPCODE_LAST \
1924 CFA_BDS_INVALIDATE_CMD_DATA_MSG_OPCODE_INVALIDATE
1925 /* This value selects the table type to be acted upon. */
1927 /* This value selects the table type to be acted upon. */
1928 #define CFA_BDS_INVALIDATE_CMD_DATA_MSG_TABLE_TYPE_MASK UINT32_C(0xf)
1929 #define CFA_BDS_INVALIDATE_CMD_DATA_MSG_TABLE_TYPE_SFT 0
1930 /* This command acts on the action table of the specified scope. */
1931 #define CFA_BDS_INVALIDATE_CMD_DATA_MSG_TABLE_TYPE_ACTION \
1933 /* This command acts on the exact match table of the specified scope. */
1934 #define CFA_BDS_INVALIDATE_CMD_DATA_MSG_TABLE_TYPE_EM \
1936 #define CFA_BDS_INVALIDATE_CMD_DATA_MSG_TABLE_TYPE_LAST \
1937 CFA_BDS_INVALIDATE_CMD_DATA_MSG_TABLE_TYPE_EM
1938 /* This value selects which table scope will be accessed. */
1939 uint8_t table_scope;
1940 #define CFA_BDS_INVALIDATE_CMD_DATA_MSG_TABLE_SCOPE_MASK UINT32_C(0x1f)
1941 #define CFA_BDS_INVALIDATE_CMD_DATA_MSG_TABLE_SCOPE_SFT 0
1942 /* This value specifies the number of cache lines to invalidate. */
1944 #define CFA_BDS_INVALIDATE_CMD_DATA_MSG_DATA_SIZE_MASK UINT32_C(0x7)
1945 #define CFA_BDS_INVALIDATE_CMD_DATA_MSG_DATA_SIZE_SFT 0
1946 /* This is the 32B index into the selected table to access. */
1947 uint32_t table_index;
1948 #define CFA_BDS_INVALIDATE_CMD_DATA_MSG_TABLE_INDEX_MASK \
1950 #define CFA_BDS_INVALIDATE_CMD_DATA_MSG_TABLE_INDEX_SFT 0
1954 /* cfa_bds_event_collect_cmd_data_msg (size:128b/16B) */
1955 struct cfa_bds_event_collect_cmd_data_msg {
1956 /* This value selects the format for the mid-path command for the CFA. */
1958 /* Reads notification messages from the Host Notification Queue. */
1959 #define CFA_BDS_EVENT_COLLECT_CMD_DATA_MSG_OPCODE_EVENT_COLLECT \
1961 #define CFA_BDS_EVENT_COLLECT_CMD_DATA_MSG_OPCODE_LAST \
1962 CFA_BDS_EVENT_COLLECT_CMD_DATA_MSG_OPCODE_EVENT_COLLECT
1964 /* This value selects which table scope will be accessed. */
1965 uint8_t table_scope;
1966 #define CFA_BDS_EVENT_COLLECT_CMD_DATA_MSG_TABLE_SCOPE_MASK \
1968 #define CFA_BDS_EVENT_COLLECT_CMD_DATA_MSG_TABLE_SCOPE_SFT 0
1970 * This value identifies the number of 32B units will be accessed. A
1971 * value of zero is invalid. Maximum value is 4.
1974 #define CFA_BDS_EVENT_COLLECT_CMD_DATA_MSG_DATA_SIZE_MASK UINT32_C(0x7)
1975 #define CFA_BDS_EVENT_COLLECT_CMD_DATA_MSG_DATA_SIZE_SFT 0
1978 * This is the 64b host address where you want the data returned to. The
1979 * data will be written to the same function as the one that owns the SQ
1981 uint64_t host_address;
1984 /* ce_bds_add_data_msg (size:512b/64B) */
1985 struct ce_bds_add_data_msg {
1986 uint32_t version_algorithm_kid_opcode;
1988 * This value selects the operation for the mid-path command for the
1991 #define CE_BDS_ADD_DATA_MSG_OPCODE_MASK UINT32_C(0xf)
1992 #define CE_BDS_ADD_DATA_MSG_OPCODE_SFT 0
1994 * This is the add command. Using this opcode, Host Driver can add
1995 * information required for kTLS processing. The information is
1996 * updated in the CFCK context.
1998 #define CE_BDS_ADD_DATA_MSG_OPCODE_ADD UINT32_C(0x1)
1999 #define CE_BDS_ADD_DATA_MSG_OPCODE_LAST \
2000 CE_BDS_ADD_DATA_MSG_OPCODE_ADD
2002 * This field is the Crypto Context ID. The KID is used to store
2003 * information used by the associated kTLS offloaded connection.
2005 #define CE_BDS_ADD_DATA_MSG_KID_MASK \
2007 #define CE_BDS_ADD_DATA_MSG_KID_SFT 4
2009 * Currently only two algorithms are supported, AES_GCM_128 and
2010 * AES_GCM_256. Additional bits for future growth.
2012 #define CE_BDS_ADD_DATA_MSG_ALGORITHM_MASK \
2014 #define CE_BDS_ADD_DATA_MSG_ALGORITHM_SFT 24
2015 /* AES_GCM_128 Algorithm */
2016 #define CE_BDS_ADD_DATA_MSG_ALGORITHM_AES_GCM_128 \
2018 /* AES_GCM_256 Algorithm */
2019 #define CE_BDS_ADD_DATA_MSG_ALGORITHM_AES_GCM_256 \
2022 * Version number of TLS connection. HW will provide registers that
2023 * converts the 4b encoded version number to 16b of actual version
2024 * number in the TLS Header. * Initialized --> By mid-path command *
2025 * Updated --> Never though another mid-path command will result in an
2028 #define CE_BDS_ADD_DATA_MSG_VERSION_MASK \
2029 UINT32_C(0xf0000000)
2030 #define CE_BDS_ADD_DATA_MSG_VERSION_SFT 28
2031 /* TLS1.2 Version */
2032 #define CE_BDS_ADD_DATA_MSG__TLS1_2 \
2033 (UINT32_C(0x0) << 28)
2034 /* TLS1.3 Version */
2035 #define CE_BDS_ADD_DATA_MSG__TLS1_3 \
2036 (UINT32_C(0x1) << 28)
2037 #define CE_BDS_ADD_DATA_MSG__LAST \
2038 CE_BDS_ADD_DATA_MSG__TLS1_3
2040 * Command Type in the TLS header. HW will provide registers that
2041 * converts the 3b encoded command type to 8b of actual command type in
2042 * the TLS Header. * Initialized --> By mid-path command * Updated -->
2043 * Never though another mid-path command will result in an update
2046 #define CE_BDS_ADD_DATA_MSG_CMD_TYPE_MASK UINT32_C(0x7)
2047 #define CE_BDS_ADD_DATA_MSG_CMD_TYPE_SFT 0
2049 #define CE_BDS_ADD_DATA_MSG_CMD_TYPE_APP UINT32_C(0x0)
2050 #define CE_BDS_ADD_DATA_MSG_CMD_TYPE_LAST \
2051 CE_BDS_ADD_DATA_MSG_CMD_TYPE_APP
2054 * Salt is part of the nonce that is used as the Initial Vector (IV) in
2055 * AES-GCM cipher suites. These are exchanged as part of the handshake
2056 * process and is either the client_write_iv (when the client is
2057 * sending) or server_write_iv (when the server is sending). In
2058 * TLS1.2, 4B of Salt is concatenated with 8B of explicit_nonce to
2059 * generate the 12B of IV. In TLS1.3, 8B of TLS record sequence number
2060 * is zero padded to 12B and then xor'ed with the 4B of salt to generate
2061 * the 12B of IV. This value is initialized by this mid-path command.
2066 * This field keeps track of the TCP sequence number that is expected as
2067 * the first byte in the next TCP packet. This field is calculated by HW
2068 * using the output of the parser. The field is initialized as part of
2069 * the Mid-path BD download/update of a kTLS connection. For every TCP
2070 * packet processed, TCE HW will update the value to Current packet TCP
2071 * sequence number + Current packet TCP Payload Length.
2073 uint32_t pkt_tcp_seq_num;
2075 * This field maintains the TCP sequence number of the first byte in the
2076 * header of the active TLS record. This field is initialized as part of
2077 * the Mid-path BD download/update of a kTLS connection. For every
2078 * record that is processed, TCE HW copies the value from the
2079 * next_tls_header_tcp_seq_num field.
2081 uint32_t tls_header_tcp_seq_num;
2083 * This is sequence number for the TLS record in a particular session.
2084 * In TLS1.2, record sequence number is part of the Associated Data (AD)
2085 * in the AEAD algorithm. In TLS1.3, record sequence number is part of
2086 * the Initial Vector (IV). The field is initialized as part of the
2087 * mid-path BD download/update of a kTLS connection. TCE HW increments
2088 * the field after that for every record processed as it parses the TCP
2091 uint32_t record_seq_num[2];
2093 * Key used for encrypting or decrypting TLS records. The Key is
2094 * exchanged during the hand-shake protocol by the client-server and
2095 * provided to HW through this mid-path BD.
2097 uint32_t session_key[8];
2100 /* ce_bds_delete_data_msg (size:64b/8B) */
2101 struct ce_bds_delete_data_msg {
2102 uint32_t kid_opcode;
2104 * This value selects the operation for the mid-path command for the
2107 #define CE_BDS_DELETE_DATA_MSG_OPCODE_MASK UINT32_C(0xf)
2108 #define CE_BDS_DELETE_DATA_MSG_OPCODE_SFT 0
2110 * This is the delete command. Using this opcode, the host Driver
2111 * can remove a key context from the CFCK. If context is deleted
2112 * and packets with the same KID come through the pipeline, the
2113 * following actions are taken. For transmit packets, no crypto
2114 * operation will be performed, payload will be zero'ed out. For
2115 * receive packets, no crypto operation will be performed,
2116 * payload will be unmodified.
2118 #define CE_BDS_DELETE_DATA_MSG_OPCODE_DELETE UINT32_C(0x2)
2119 #define CE_BDS_DELETE_DATA_MSG_OPCODE_LAST \
2120 CE_BDS_DELETE_DATA_MSG_OPCODE_DELETE
2122 * This field is the Crypto Context ID. The KID is used to store
2123 * information used by the associated kTLS offloaded connection.
2125 #define CE_BDS_DELETE_DATA_MSG_KID_MASK UINT32_C(0xfffff0)
2126 #define CE_BDS_DELETE_DATA_MSG_KID_SFT 4
2130 /* ce_bds_resync_resp_ack_msg (size:128b/16B) */
2131 struct ce_bds_resync_resp_ack_msg {
2132 uint32_t resync_status_kid_opcode;
2134 * This value selects the operation for the mid-path command for the
2137 #define CE_BDS_RESYNC_RESP_ACK_MSG_OPCODE_MASK UINT32_C(0xf)
2138 #define CE_BDS_RESYNC_RESP_ACK_MSG_OPCODE_SFT 0
2140 * This command is used by the driver as a response to the resync
2141 * request sent by the crypto engine.
2143 #define CE_BDS_RESYNC_RESP_ACK_MSG_OPCODE_RESYNC UINT32_C(0x3)
2144 #define CE_BDS_RESYNC_RESP_ACK_MSG_OPCODE_LAST \
2145 CE_BDS_RESYNC_RESP_ACK_MSG_OPCODE_RESYNC
2147 * This field is the Crypto Context ID. The KID is used to store
2148 * information used by the associated kTLS offloaded connection.
2150 #define CE_BDS_RESYNC_RESP_ACK_MSG_KID_MASK UINT32_C(0xfffff0)
2151 #define CE_BDS_RESYNC_RESP_ACK_MSG_KID_SFT 4
2153 * This field indicates if the resync request resulted in a success or
2156 #define CE_BDS_RESYNC_RESP_ACK_MSG_RESYNC_STATUS \
2159 * An ACK indicates that the driver was able to find the TLS record
2160 * associated with TCP sequence number provided by the HW
2162 #define CE_BDS_RESYNC_RESP_ACK_MSG_RESYNC_STATUS_ACK \
2163 (UINT32_C(0x0) << 24)
2164 #define CE_BDS_RESYNC_RESP_ACK_MSG_RESYNC_STATUS_LAST \
2165 CE_BDS_RESYNC_RESP_ACK_MSG_RESYNC_STATUS_ACK
2167 * This field is the echo of the TCP sequence number provided in the
2168 * resync request by the HW. If HW sent multiple resync requests, it
2169 * only tracks the latest TCP sequence number. When the response from
2170 * the Driver doesn't match the latest request, HW will drop the resync
2173 uint32_t resync_record_tcp_seq_num;
2175 * This field indicates the TLS record sequence number associated with
2176 * the resync request. HW will take this number and add the delta records
2177 * it has found since sending the resync request, update the context and
2178 * resume decrypting records.
2180 uint32_t resync_record_seq_num[2];
2183 /* ce_bds_resync_resp_nack_msg (size:64b/8B) */
2184 struct ce_bds_resync_resp_nack_msg {
2185 uint32_t resync_status_kid_opcode;
2187 * This value selects the operation for the mid-path command for the
2190 #define CE_BDS_RESYNC_RESP_NACK_MSG_OPCODE_MASK UINT32_C(0xf)
2191 #define CE_BDS_RESYNC_RESP_NACK_MSG_OPCODE_SFT 0
2193 * This command is used by the driver as a response to the resync
2194 * request sent by the crypto engine.
2196 #define CE_BDS_RESYNC_RESP_NACK_MSG_OPCODE_RESYNC UINT32_C(0x3)
2197 #define CE_BDS_RESYNC_RESP_NACK_MSG_OPCODE_LAST \
2198 CE_BDS_RESYNC_RESP_NACK_MSG_OPCODE_RESYNC
2200 * This field is the Crypto Context ID. The KID is used to store
2201 * information used by the associated kTLS offloaded connection.
2203 #define CE_BDS_RESYNC_RESP_NACK_MSG_KID_MASK \
2205 #define CE_BDS_RESYNC_RESP_NACK_MSG_KID_SFT 4
2207 * This field indicates if the resync request resulted in a success or
2210 #define CE_BDS_RESYNC_RESP_NACK_MSG_RESYNC_STATUS \
2213 * An NAK indicates that the driver wasn't able to find the TLS
2214 * record associated with TCP sequence number provided by the HW
2216 #define CE_BDS_RESYNC_RESP_NACK_MSG_RESYNC_STATUS_NACK \
2217 (UINT32_C(0x1) << 24)
2218 #define CE_BDS_RESYNC_RESP_NACK_MSG_RESYNC_STATUS_LAST \
2219 CE_BDS_RESYNC_RESP_NACK_MSG_RESYNC_STATUS_NACK
2221 * This field is the echo of the TCP sequence number provided in the
2222 * resync request by the HW. If HW sent multiple resync requests, it
2223 * only tracks the latest TCP sequence number. When the response from
2224 * the Driver doesn't match the latest request, HW will drop the resync
2227 uint32_t resync_record_tcp_seq_num;
2230 /* crypto_presync_bd_cmd (size:256b/32B) */
2231 struct crypto_presync_bd_cmd {
2234 * Typically, presync BDs are used for packet retransmissions. Source
2235 * port sends all the packets in order over the network to destination
2236 * port and packets get dropped in the network. The destination port
2237 * will request retranmission of dropped packets and source port driver
2238 * will send presync BD to setup the transmitter appropriately. It will
2239 * provide the start and end TCP sequence number of the data to be
2240 * transmitted. HW keeps two sets of context variable, one for in order
2241 * traffic and one for retransmission traffic. HW is designed to
2242 * transmit everything posted in the presync BD and return to in order
2243 * mode after that. No inorder context variables are updated in the
2244 * process. There is a special case where packets can be dropped
2245 * between the TCP stack and Device Driver (Berkeley Packet Filter for
2246 * ex) and HW still needs to transmit rest of the traffic. In this
2247 * mode, driver will send a presync BD as if it is a retransmission but
2248 * at the end of the transmission, the in order variables need to be
2249 * updated. This flag is used by driver to indicate that in order
2250 * variables needs to be updated at the end of completing the task
2251 * associated with the presync BD.
2253 #define CRYPTO_PRESYNC_BD_CMD_FLAGS_UPDATE_IN_ORDER_VAR \
2258 * This field maintains the TCP sequence number of the first byte in the
2259 * Header of the active TLS record. This field is set to 0 during
2260 * mid-path BD updates, but is set to correct value when a presync BD is
2261 * detected. For every record that is processed, the value from the
2262 * next_tls_header_tcp_seq_num field is copied.
2264 uint32_t header_tcp_seq_num;
2266 * When a retransmitted packet has a TLS authentication TAG present and
2267 * the data spans multiple TCP Packets, HW is required to read the entire
2268 * record to recalculate the TAG but only transmit what is required. This
2269 * field is the start TCP sequence number of the packet(s) that need to
2270 * be re-transmitted. This field is initialized to 0 during Mid-path BD
2271 * add command and initialized to value provided by the driver when
2272 * Pre-sync BD is detected. This field is never updated unless another
2273 * Pre-sync BD signaling a new retransmission is scheduled.
2275 uint32_t start_tcp_seq_num;
2277 * When a retransmitted packet has a TLS authentication TAG present and
2278 * the data spans multiple TCP Packets, HW is required to read the
2279 * entire record to recalculate the TAG but only transmit what is
2280 * required. This field is the end TCP sequence number of the packet(s)
2281 * that need to be re-transmitted. This field is initialized to 0 during
2282 * Mid-path BD add command and initialized to value provided by the
2283 * driver when Pre-sync BD is detected. This field is never updated
2284 * unless another Pre-sync BD signaling a new retransmission is
2287 uint32_t end_tcp_seq_num;
2289 * For TLS1.2, an explicit nonce is used as part of the IV (concatenated
2290 * with the SALT). For retrans packets, this field is extracted from the
2291 * TLS record, field right after the TLS Header and stored in the
2292 * context. This field needs to be stored in context as TCP segmentation
2293 * could have split the field into multiple TCP packets. This value is
2294 * initialized to 0 when presync BD is detected by taking the value from
2295 * the first TLS header. When subsequent TLS Headers are detected, the
2296 * value is extracted from packet.
2298 uint32_t explicit_nonce[2];
2300 * This is sequence number for the TLS record in a particular session. In
2301 * TLS1.2, record sequence number is part of the Associated Data (AD) in
2302 * the AEAD algorithm. In TLS1.3, record sequence number is part of the
2303 * Initial Vector (IV). The field is initialized to 0 during Mid-path BD
2304 * download. Is initialized to correct value when a pre-sync BD is
2305 * detected. TCE HW increments the field after that for every record
2306 * processed as it parses the TCP packet. Subsequent pre-sync BDs
2307 * delivering more retransmission instruction will also update this
2310 uint32_t record_seq_num[2];
2313 /* bd_base (size:64b/8B) */
2316 /* This value identifies the type of buffer descriptor. */
2317 #define BD_BASE_TYPE_MASK UINT32_C(0x3f)
2318 #define BD_BASE_TYPE_SFT 0
2320 * Indicates that this BD is 16B long and is used for
2321 * normal L2 packet transmission.
2323 #define BD_BASE_TYPE_TX_BD_SHORT UINT32_C(0x0)
2325 * Indicates that this BD is 1BB long and is an empty
2326 * TX BD. Not valid for use by the driver.
2328 #define BD_BASE_TYPE_TX_BD_EMPTY UINT32_C(0x1)
2330 * Indicates that this BD is 16B long and is an RX Producer
2331 * (i.e. empty) buffer descriptor.
2333 #define BD_BASE_TYPE_RX_PROD_PKT UINT32_C(0x4)
2335 * Indicates that this BD is 16B long and is an RX
2336 * Producer Buffer BD.
2338 #define BD_BASE_TYPE_RX_PROD_BFR UINT32_C(0x5)
2340 * Indicates that this BD is 16B long and is an
2341 * RX Producer Assembly Buffer Descriptor.
2343 #define BD_BASE_TYPE_RX_PROD_AGG UINT32_C(0x6)
2345 * Indicates that this BD is used to issue a command to one of
2346 * the mid-path destinations.
2348 #define BD_BASE_TYPE_TX_BD_MP_CMD UINT32_C(0x8)
2350 * Indicates that this BD is used to issue a cryptographic pre-
2351 * sync command through the fast path and destined for TCE.
2353 #define BD_BASE_TYPE_TX_BD_PRESYNC_CMD UINT32_C(0x9)
2355 * Indicates that this BD is 32B long and is used for
2356 * normal L2 packet transmission.
2358 #define BD_BASE_TYPE_TX_BD_LONG UINT32_C(0x10)
2360 * Indicates that this BD is 32B long and is used for
2361 * L2 packet transmission for small packets that require
2364 #define BD_BASE_TYPE_TX_BD_LONG_INLINE UINT32_C(0x11)
2365 #define BD_BASE_TYPE_LAST BD_BASE_TYPE_TX_BD_LONG_INLINE
2366 uint8_t unused_1[7];
2369 /* tx_bd_short (size:128b/16B) */
2370 struct tx_bd_short {
2372 * All bits in this field must be valid on the first BD of a packet.
2373 * Only the packet_end bit must be valid for the remaining BDs
2376 uint16_t flags_type;
2377 /* This value identifies the type of buffer descriptor. */
2378 #define TX_BD_SHORT_TYPE_MASK UINT32_C(0x3f)
2379 #define TX_BD_SHORT_TYPE_SFT 0
2381 * Indicates that this BD is 16B long and is used for
2382 * normal L2 packet transmission.
2384 #define TX_BD_SHORT_TYPE_TX_BD_SHORT UINT32_C(0x0)
2385 #define TX_BD_SHORT_TYPE_LAST TX_BD_SHORT_TYPE_TX_BD_SHORT
2387 * All bits in this field must be valid on the first BD of a packet.
2388 * Only the packet_end bit must be valid for the remaining BDs
2391 #define TX_BD_SHORT_FLAGS_MASK UINT32_C(0xffc0)
2392 #define TX_BD_SHORT_FLAGS_SFT 6
2394 * If set to 1, the packet ends with the data in the buffer
2395 * pointed to by this descriptor. This flag must be
2396 * valid on every BD.
2398 #define TX_BD_SHORT_FLAGS_PACKET_END UINT32_C(0x40)
2400 * If set to 1, the device will not generate a completion for
2401 * this transmit packet unless there is an error in it's
2404 * is set to 0, then the packet will be completed normally.
2406 * This bit must be valid only on the first BD of a packet.
2408 #define TX_BD_SHORT_FLAGS_NO_CMPL UINT32_C(0x80)
2410 * This value indicates how many 16B BD locations are consumed
2411 * in the ring by this packet.
2412 * A value of 1 indicates that this BD is the only BD (and that
2413 * it is a short BD). A value
2414 * of 3 indicates either 3 short BDs or 1 long BD and one short
2415 * BD in the packet. A value of 0 indicates
2416 * that there are 32 BD locations in the packet (the maximum).
2418 * This field is valid only on the first BD of a packet.
2420 #define TX_BD_SHORT_FLAGS_BD_CNT_MASK UINT32_C(0x1f00)
2421 #define TX_BD_SHORT_FLAGS_BD_CNT_SFT 8
2423 * This value is a hint for the length of the entire packet.
2424 * It is used by the chip to optimize internal processing.
2426 * The packet will be dropped if the hint is too short.
2428 * This field is valid only on the first BD of a packet.
2430 #define TX_BD_SHORT_FLAGS_LHINT_MASK UINT32_C(0x6000)
2431 #define TX_BD_SHORT_FLAGS_LHINT_SFT 13
2432 /* indicates packet length < 512B */
2433 #define TX_BD_SHORT_FLAGS_LHINT_LT512 (UINT32_C(0x0) << 13)
2434 /* indicates 512 <= packet length < 1KB */
2435 #define TX_BD_SHORT_FLAGS_LHINT_LT1K (UINT32_C(0x1) << 13)
2436 /* indicates 1KB <= packet length < 2KB */
2437 #define TX_BD_SHORT_FLAGS_LHINT_LT2K (UINT32_C(0x2) << 13)
2438 /* indicates packet length >= 2KB */
2439 #define TX_BD_SHORT_FLAGS_LHINT_GTE2K (UINT32_C(0x3) << 13)
2440 #define TX_BD_SHORT_FLAGS_LHINT_LAST \
2441 TX_BD_SHORT_FLAGS_LHINT_GTE2K
2443 * If set to 1, the device immediately updates the Send Consumer
2444 * Index after the buffer associated with this descriptor has
2445 * been transferred via DMA to NIC memory from host memory. An
2446 * interrupt may or may not be generated according to the state
2447 * of the interrupt avoidance mechanisms. If this bit
2448 * is set to 0, then the Consumer Index is only updated as soon
2449 * as one of the host interrupt coalescing conditions has been met.
2451 * This bit must be valid on the first BD of a packet.
2453 #define TX_BD_SHORT_FLAGS_COAL_NOW UINT32_C(0x8000)
2455 * This is the length of the host physical buffer this BD describes
2458 * This field must be valid on all BDs of a packet.
2462 * The opaque data field is pass through to the completion and can be
2463 * used for any data that the driver wants to associate with the
2466 * This field must be valid on the first BD of a packet. If completion
2467 * coalescing is enabled on the TX ring, it is suggested that the driver
2468 * populate the opaque field to indicate the specific TX ring with which
2469 * the completion is associated, then utilize the opaque and sq_cons_idx
2470 * fields in the coalesced completion record to determine the specific
2471 * packets that are to be completed on that ring.
2475 * This is the host physical address for the portion of the packet
2476 * described by this TX BD.
2478 * This value must be valid on all BDs of a packet.
2483 /* tx_bd_long (size:128b/16B) */
2485 /* This value identifies the type of buffer descriptor. */
2486 uint16_t flags_type;
2488 * This value indicates the type of buffer descriptor.
2491 #define TX_BD_LONG_TYPE_MASK UINT32_C(0x3f)
2492 #define TX_BD_LONG_TYPE_SFT 0
2494 * Indicates that this BD is 32B long and is used for
2495 * normal L2 packet transmission.
2497 #define TX_BD_LONG_TYPE_TX_BD_LONG UINT32_C(0x10)
2498 #define TX_BD_LONG_TYPE_LAST TX_BD_LONG_TYPE_TX_BD_LONG
2500 * All bits in this field must be valid on the first BD of a packet.
2501 * Only the packet_end bit must be valid for the remaining BDs
2504 #define TX_BD_LONG_FLAGS_MASK UINT32_C(0xffc0)
2505 #define TX_BD_LONG_FLAGS_SFT 6
2507 * If set to 1, the packet ends with the data in the buffer
2508 * pointed to by this descriptor. This flag must be
2509 * valid on every BD.
2511 #define TX_BD_LONG_FLAGS_PACKET_END UINT32_C(0x40)
2513 * If set to 1, the device will not generate a completion for
2514 * this transmit packet unless there is an error in it's
2517 * is set to 0, then the packet will be completed normally.
2519 * This bit must be valid only on the first BD of a packet.
2521 #define TX_BD_LONG_FLAGS_NO_CMPL UINT32_C(0x80)
2523 * This value indicates how many 16B BD locations are consumed
2524 * in the ring by this packet.
2525 * A value of 1 indicates that this BD is the only BD (and that
2526 * it is a short BD). A value
2527 * of 3 indicates either 3 short BDs or 1 long BD and one short
2528 * BD in the packet. A value of 0 indicates
2529 * that there are 32 BD locations in the packet (the maximum).
2531 * This field is valid only on the first BD of a packet.
2533 #define TX_BD_LONG_FLAGS_BD_CNT_MASK UINT32_C(0x1f00)
2534 #define TX_BD_LONG_FLAGS_BD_CNT_SFT 8
2536 * This value is a hint for the length of the entire packet.
2537 * It is used by the chip to optimize internal processing.
2539 * The packet will be dropped if the hint is too short.
2541 * This field is valid only on the first BD of a packet.
2543 #define TX_BD_LONG_FLAGS_LHINT_MASK UINT32_C(0x6000)
2544 #define TX_BD_LONG_FLAGS_LHINT_SFT 13
2545 /* indicates packet length < 512B */
2546 #define TX_BD_LONG_FLAGS_LHINT_LT512 (UINT32_C(0x0) << 13)
2547 /* indicates 512 <= packet length < 1KB */
2548 #define TX_BD_LONG_FLAGS_LHINT_LT1K (UINT32_C(0x1) << 13)
2549 /* indicates 1KB <= packet length < 2KB */
2550 #define TX_BD_LONG_FLAGS_LHINT_LT2K (UINT32_C(0x2) << 13)
2551 /* indicates packet length >= 2KB */
2552 #define TX_BD_LONG_FLAGS_LHINT_GTE2K (UINT32_C(0x3) << 13)
2553 #define TX_BD_LONG_FLAGS_LHINT_LAST TX_BD_LONG_FLAGS_LHINT_GTE2K
2555 * If set to 1, the device immediately updates the Send Consumer
2556 * Index after the buffer associated with this descriptor has
2557 * been transferred via DMA to NIC memory from host memory. An
2558 * interrupt may or may not be generated according to the state
2559 * of the interrupt avoidance mechanisms. If this bit
2560 * is set to 0, then the Consumer Index is only updated as soon
2561 * as one of the host interrupt coalescing conditions has been met.
2563 * This bit must be valid on the first BD of a packet.
2565 #define TX_BD_LONG_FLAGS_COAL_NOW UINT32_C(0x8000)
2567 * This is the length of the host physical buffer this BD describes
2570 * This field must be valid on all BDs of a packet.
2574 * The opaque data field is passed through to the completion and can be
2575 * used for any data that the driver wants to associate with the
2578 * This field must be valid on the first BD of a packet. If completion
2579 * coalescing is enabled on the TX ring, it is suggested that the driver
2580 * populate the opaque field to indicate the specific TX ring with which
2581 * the completion is associated, then utilize the opaque and sq_cons_idx
2582 * fields in the coalesced completion record to determine the specific
2583 * packets that are to be completed on that ring.
2587 * This is the host physical address for the portion of the packet
2588 * described by this TX BD.
2590 * This value must be valid on all BDs of a packet.
2595 /* Last 16 bytes of tx_bd_long. */
2596 /* tx_bd_long_hi (size:128b/16B) */
2597 struct tx_bd_long_hi {
2599 * All bits in this field must be valid on the first BD of a packet.
2600 * Their value on other BDs of the packet will be ignored.
2604 * If set to 1, the controller replaces the TCP/UPD checksum
2605 * fields of normal TCP/UPD checksum, or the inner TCP/UDP
2606 * checksum field of the encapsulated TCP/UDP packets with the
2607 * hardware calculated TCP/UDP checksum for the packet associated
2608 * with this descriptor. The flag is ignored if the LSO flag is set.
2610 * This bit must be valid on the first BD of a packet.
2612 #define TX_BD_LONG_LFLAGS_TCP_UDP_CHKSUM UINT32_C(0x1)
2614 * If set to 1, the controller replaces the IP checksum of the
2615 * normal packets, or the inner IP checksum of the encapsulated
2616 * packets with the hardware calculated IP checksum for the
2617 * packet associated with this descriptor.
2619 * This bit must be valid on the first BD of a packet.
2621 #define TX_BD_LONG_LFLAGS_IP_CHKSUM UINT32_C(0x2)
2623 * If set to 1, the controller will not append an Ethernet CRC
2624 * to the end of the frame.
2626 * This bit must be valid on the first BD of a packet.
2628 * Packet must be 64B or longer when this flag is set. It is not
2629 * useful to use this bit with any form of TX offload such as
2630 * CSO or LSO. The intent is that the packet from the host already
2631 * has a valid Ethernet CRC on the packet.
2633 #define TX_BD_LONG_LFLAGS_NOCRC UINT32_C(0x4)
2635 * If set to 1, the device will record the time at which the packet
2636 * was actually transmitted at the TX MAC for 2-step time sync.
2638 * This bit must be valid on the first BD of a packet.
2640 #define TX_BD_LONG_LFLAGS_STAMP UINT32_C(0x8)
2642 * If set to 1, The controller replaces the tunnel IP checksum
2643 * field with hardware calculated IP checksum for the IP header
2644 * of the packet associated with this descriptor.
2646 * For outer UDP checksum, global outer UDP checksum TE_NIC register
2647 * needs to be enabled. If the global outer UDP checksum TE_NIC register
2648 * bit is set, outer UDP checksum will be calculated for the following
2650 * 1. Packets with tcp_udp_chksum flag set to offload checksum for inner
2651 * packet AND the inner packet is TCP/UDP. If the inner packet is ICMP for
2652 * example (non-TCP/UDP), even if the tcp_udp_chksum is set, the outer UDP
2653 * checksum will not be calculated.
2654 * 2. Packets with lso flag set which implies inner TCP checksum calculation
2655 * as part of LSO operation.
2657 #define TX_BD_LONG_LFLAGS_T_IP_CHKSUM UINT32_C(0x10)
2659 * If set to 1, the device will treat this packet with LSO(Large
2660 * Send Offload) processing for both normal or encapsulated
2661 * packets, which is a form of TCP segmentation. When this bit
2662 * is 1, the hdr_size and mss fields must be valid. The driver
2663 * doesn't need to set ot_ip_chksum, t_ip_chksum, ip_chksum, and
2664 * tcp_udp_chksum flags since the controller will replace the
2665 * appropriate checksum fields for segmented packets.
2667 * When this bit is 1, the hdr_size and mss fields must be valid.
2669 #define TX_BD_LONG_LFLAGS_LSO UINT32_C(0x20)
2671 * If set to zero when LSO is '1', then the IPID will be treated
2672 * as a 16b number and will be wrapped if it exceeds a value of
2675 * If set to one when LSO is '1', then the IPID will be treated
2676 * as a 15b number and will be wrapped if it exceeds a value 0f
2679 #define TX_BD_LONG_LFLAGS_IPID_FMT UINT32_C(0x40)
2681 * If set to zero when LSO is '1', then the IPID of the tunnel
2682 * IP header will not be modified during LSO operations.
2684 * If set to one when LSO is '1', then the IPID of the tunnel
2685 * IP header will be incremented for each subsequent segment of an
2688 * The flag is ignored if the LSO packet is a normal (non-tunneled)
2691 #define TX_BD_LONG_LFLAGS_T_IPID UINT32_C(0x80)
2693 * If set to '1', then the RoCE ICRC will be appended to the
2694 * packet. Packet must be a valid RoCE format packet.
2696 #define TX_BD_LONG_LFLAGS_ROCE_CRC UINT32_C(0x100)
2698 * If set to '1', then the FCoE CRC will be appended to the
2699 * packet. Packet must be a valid FCoE format packet.
2701 #define TX_BD_LONG_LFLAGS_FCOE_CRC UINT32_C(0x200)
2703 * If set to '1', then the timestamp from the BD is used. If cleared
2704 * to 0, then TWE provides the timestamp.
2706 #define TX_BD_LONG_LFLAGS_BD_TS_EN UINT32_C(0x400)
2708 * If set to '1', this operation will cause a trace capture in each
2709 * block it passes through.
2711 #define TX_BD_LONG_LFLAGS_DEBUG_TRACE UINT32_C(0x800)
2713 * If set to '1', the device will record the time at which the packet
2714 * was actually transmitted at the TX MAC for 1-step time sync. This
2715 * bit must be valid on the first BD of a packet.
2717 #define TX_BD_LONG_LFLAGS_STAMP_1STEP UINT32_C(0x1000)
2719 * If set to '1', the controller replaces the Outer-tunnel IP checksum
2720 * field with hardware calculated IP checksum for the IP header of the
2721 * packet associated with this descriptor. For outer UDP checksum, it
2722 * will be the following behavior for all cases independent of settings
2723 * of inner LSO and checksum offload BD flags. If outer UDP checksum
2724 * is 0, then do not update it. If outer UDP checksum is non zero, then
2725 * the hardware should compute and update it.
2727 #define TX_BD_LONG_LFLAGS_OT_IP_CHKSUM UINT32_C(0x2000)
2729 * If set to zero when LSO is '1', then the IPID of the Outer-tunnel IP
2730 * header will not be modified during LSO operations. If set to one
2731 * when LSO is '1', then the IPID of the Outer-tunnel IP header will be
2732 * incremented for each subsequent segment of an LSO operation. The
2733 * flag is ignored if the LSO packet is a normal (non-tunneled) TCP
2736 #define TX_BD_LONG_LFLAGS_OT_IPID UINT32_C(0x4000)
2738 * If set to '1', When set to 1, KTLS encryption will be enabled for
2741 #define TX_BD_LONG_LFLAGS_CRYPTO_EN UINT32_C(0x8000)
2742 uint16_t kid_or_ts_low_hdr_size;
2744 * When LSO is '1', this field must contain the offset of the
2745 * TCP payload from the beginning of the packet in as
2746 * 16b words. In case of encapsulated/tunneling packet, this field
2747 * contains the offset of the inner TCP payload from beginning of the
2748 * packet as 16-bit words.
2750 * This value must be valid on the first BD of a packet.
2752 #define TX_BD_LONG_HDR_SIZE_MASK UINT32_C(0x1ff)
2753 #define TX_BD_LONG_HDR_SIZE_SFT 0
2755 * If lflags.bd_ts_en is 1, this is the lower 7 bits of the 24-bit
2756 * timestamp. If lflags.crypto_en is 1, this is the lower 7 bits of the
2759 #define TX_BD_LONG_KID_OR_TS_LOW_MASK UINT32_C(0xfe00)
2760 #define TX_BD_LONG_KID_OR_TS_LOW_SFT 9
2761 uint32_t kid_or_ts_high_mss;
2763 * This is the MSS value that will be used to do the LSO processing.
2764 * The value is the length in bytes of the TCP payload for each
2765 * segment generated by the LSO operation.
2767 * This value must be valid on the first BD of a packet.
2769 #define TX_BD_LONG_MSS_MASK UINT32_C(0x7fff)
2770 #define TX_BD_LONG_MSS_SFT 0
2772 * If lflags.bd_ts_en is 1, this is the upper 17 bits of the 24-bit
2773 * timestamp. If lflags.crypto_en is 1, the least significant 13 bits
2774 * of this field contain the upper 13 bits of the 20-bit KID.
2776 #define TX_BD_LONG_KID_OR_TS_HIGH_MASK UINT32_C(0xffff8000)
2777 #define TX_BD_LONG_KID_OR_TS_HIGH_SFT 15
2779 * This value selects bits 25:16 of the CFA action to perform on the
2780 * packet. See the cfa_action field for more information.
2782 uint16_t cfa_action_high;
2783 #define TX_BD_LONG_CFA_ACTION_HIGH_MASK UINT32_C(0x3ff)
2784 #define TX_BD_LONG_CFA_ACTION_HIGH_SFT 0
2786 * This value selects a CFA action to perform on the packet.
2787 * Set this value to zero if no CFA action is desired.
2789 * This value must be valid on the first BD of a packet.
2791 uint16_t cfa_action;
2793 * This value is action meta-data that defines CFA edit operations
2794 * that are done in addition to any action editing.
2797 /* When key=1, This is the VLAN tag VID value. */
2798 #define TX_BD_LONG_CFA_META_VLAN_VID_MASK UINT32_C(0xfff)
2799 #define TX_BD_LONG_CFA_META_VLAN_VID_SFT 0
2800 /* When key=1, This is the VLAN tag DE value. */
2801 #define TX_BD_LONG_CFA_META_VLAN_DE UINT32_C(0x1000)
2802 /* When key=1, This is the VLAN tag PRI value. */
2803 #define TX_BD_LONG_CFA_META_VLAN_PRI_MASK UINT32_C(0xe000)
2804 #define TX_BD_LONG_CFA_META_VLAN_PRI_SFT 13
2805 /* When key=1, This is the VLAN tag TPID select value. */
2806 #define TX_BD_LONG_CFA_META_VLAN_TPID_MASK UINT32_C(0x70000)
2807 #define TX_BD_LONG_CFA_META_VLAN_TPID_SFT 16
2809 #define TX_BD_LONG_CFA_META_VLAN_TPID_TPID88A8 \
2810 (UINT32_C(0x0) << 16)
2812 #define TX_BD_LONG_CFA_META_VLAN_TPID_TPID8100 \
2813 (UINT32_C(0x1) << 16)
2815 #define TX_BD_LONG_CFA_META_VLAN_TPID_TPID9100 \
2816 (UINT32_C(0x2) << 16)
2818 #define TX_BD_LONG_CFA_META_VLAN_TPID_TPID9200 \
2819 (UINT32_C(0x3) << 16)
2821 #define TX_BD_LONG_CFA_META_VLAN_TPID_TPID9300 \
2822 (UINT32_C(0x4) << 16)
2823 /* Value programmed in CFA VLANTPID register. */
2824 #define TX_BD_LONG_CFA_META_VLAN_TPID_TPIDCFG \
2825 (UINT32_C(0x5) << 16)
2826 #define TX_BD_LONG_CFA_META_VLAN_TPID_LAST \
2827 TX_BD_LONG_CFA_META_VLAN_TPID_TPIDCFG
2828 /* When key=1, This is the VLAN tag TPID select value. */
2829 #define TX_BD_LONG_CFA_META_VLAN_RESERVED_MASK UINT32_C(0xff80000)
2830 #define TX_BD_LONG_CFA_META_VLAN_RESERVED_SFT 19
2832 * This field identifies the type of edit to be performed
2835 * This value must be valid on the first BD of a packet.
2837 #define TX_BD_LONG_CFA_META_KEY_MASK UINT32_C(0xf0000000)
2838 #define TX_BD_LONG_CFA_META_KEY_SFT 28
2840 #define TX_BD_LONG_CFA_META_KEY_NONE \
2841 (UINT32_C(0x0) << 28)
2843 * - meta[17:16] - TPID select value (0 = 0x8100).
2844 * - meta[15:12] - PRI/DE value.
2845 * - meta[11:0] - VID value.
2847 #define TX_BD_LONG_CFA_META_KEY_VLAN_TAG \
2848 (UINT32_C(0x1) << 28)
2851 * - Wh+/SR - this option is not supported.
2852 * - Thor - cfa_meta[15:0] is used for metadata output if en_bd_meta
2853 * is set in the Lookup Table.
2854 * - SR2 - {4’d0, cfa_meta[27:0]} is used for metadata output if
2855 * en_bd_meta is set in the Lookup Table.
2857 #define TX_BD_LONG_CFA_META_KEY_METADATA_TRANSFER \
2858 (UINT32_C(0x2) << 28)
2859 #define TX_BD_LONG_CFA_META_KEY_LAST \
2860 TX_BD_LONG_CFA_META_KEY_METADATA_TRANSFER
2864 * This structure is used to inform the NIC of packet data that needs to be
2865 * transmitted with additional processing that requires extra data such as
2866 * VLAN insertion plus attached inline data. This BD type may be used to
2867 * improve latency for small packets needing the additional extended features
2868 * supported by long BDs.
2870 /* tx_bd_long_inline (size:256b/32B) */
2871 struct tx_bd_long_inline {
2872 uint16_t flags_type;
2873 /* This value identifies the type of buffer descriptor. */
2874 #define TX_BD_LONG_INLINE_TYPE_MASK UINT32_C(0x3f)
2875 #define TX_BD_LONG_INLINE_TYPE_SFT 0
2877 * This type of BD is 32B long and is used for inline L2 packet
2880 #define TX_BD_LONG_INLINE_TYPE_TX_BD_LONG_INLINE UINT32_C(0x11)
2881 #define TX_BD_LONG_INLINE_TYPE_LAST \
2882 TX_BD_LONG_INLINE_TYPE_TX_BD_LONG_INLINE
2884 * All bits in this field may be set on the first BD of a packet.
2885 * Only the packet_end bit may be set in non-first BDs.
2887 #define TX_BD_LONG_INLINE_FLAGS_MASK UINT32_C(0xffc0)
2888 #define TX_BD_LONG_INLINE_FLAGS_SFT 6
2890 * If set to 1, the packet ends with the data in the buffer
2891 * pointed to by this descriptor. This flag must be
2892 * valid on every BD.
2894 #define TX_BD_LONG_INLINE_FLAGS_PACKET_END UINT32_C(0x40)
2896 * If set to 1, the device will not generate a completion for
2897 * this transmit packet unless there is an error in its processing.
2898 * If this bit is set to 0, then the packet will be completed
2901 * This bit may be set only on the first BD of a packet.
2903 #define TX_BD_LONG_INLINE_FLAGS_NO_CMPL UINT32_C(0x80)
2905 * This value indicates how many 16B BD locations are consumed
2906 * in the ring by this packet, including the BD and inline
2909 #define TX_BD_LONG_INLINE_FLAGS_BD_CNT_MASK UINT32_C(0x1f00)
2910 #define TX_BD_LONG_INLINE_FLAGS_BD_CNT_SFT 8
2911 /* This field is deprecated. */
2912 #define TX_BD_LONG_INLINE_FLAGS_LHINT_MASK UINT32_C(0x6000)
2913 #define TX_BD_LONG_INLINE_FLAGS_LHINT_SFT 13
2915 * If set to 1, the device immediately updates the Send Consumer
2916 * Index after the buffer associated with this descriptor has
2917 * been transferred via DMA to NIC memory from host memory. An
2918 * interrupt may or may not be generated according to the state
2919 * of the interrupt avoidance mechanisms. If this bit
2920 * is set to 0, then the Consumer Index is only updated as soon
2921 * as one of the host interrupt coalescing conditions has been met.
2923 * This bit must be valid on the first BD of a packet.
2925 #define TX_BD_LONG_INLINE_FLAGS_COAL_NOW UINT32_C(0x8000)
2927 * This is the length of the inline data, not including BD length, in
2929 * The maximum value is 480.
2931 * This field must be valid on all BDs of a packet.
2935 * The opaque data field is passed through to the completion and can be
2936 * used for any data that the driver wants to associate with the transmit
2937 * BD. This field must be valid on the first BD of a packet. If
2938 * completion coalescing is enabled on the TX ring, it is suggested that
2939 * the driver populate the opaque field to indicate the specific TX ring
2940 * with which the completion is associated, then utilize the opaque and
2941 * sq_cons_idx fields in the coalesced completion record to determine
2942 * the specific packets that are to be completed on that ring.
2944 * This field must be valid on the first BD of a packet.
2949 * All bits in this field must be valid on the first BD of a packet.
2950 * Their value on other BDs of the packet is ignored.
2954 * If set to 1, the controller replaces the TCP/UPD checksum
2955 * fields of normal TCP/UPD checksum, or the inner TCP/UDP
2956 * checksum field of the encapsulated TCP/UDP packets with the
2957 * hardware calculated TCP/UDP checksum for the packet associated
2958 * with this descriptor. The flag is ignored if the LSO flag is set.
2960 #define TX_BD_LONG_INLINE_LFLAGS_TCP_UDP_CHKSUM UINT32_C(0x1)
2962 * If set to 1, the controller replaces the IP checksum of the
2963 * normal packets, or the inner IP checksum of the encapsulated
2964 * packets with the hardware calculated IP checksum for the
2965 * packet associated with this descriptor.
2967 #define TX_BD_LONG_INLINE_LFLAGS_IP_CHKSUM UINT32_C(0x2)
2969 * If set to 1, the controller will not append an Ethernet CRC
2970 * to the end of the frame.
2972 * Packet must be 64B or longer when this flag is set. It is not
2973 * useful to use this bit with any form of TX offload such as
2974 * CSO or LSO. The intent is that the packet from the host already
2975 * has a valid Ethernet CRC on the packet.
2977 #define TX_BD_LONG_INLINE_LFLAGS_NOCRC UINT32_C(0x4)
2979 * If set to 1, the device will record the time at which the packet
2980 * was actually transmitted at the TX MAC for 2-step time sync. This
2981 * bit must be valid on the first BD of a packet.
2983 #define TX_BD_LONG_INLINE_LFLAGS_STAMP UINT32_C(0x8)
2985 * If set to 1, the controller replaces the tunnel IP checksum
2986 * field with hardware calculated IP checksum for the IP header
2987 * of the packet associated with this descriptor. The hardware
2988 * updates an outer UDP checksum if it is non-zero.
2990 #define TX_BD_LONG_INLINE_LFLAGS_T_IP_CHKSUM UINT32_C(0x10)
2992 * This bit must be 0 for BDs of this type. LSO is not supported with
2995 #define TX_BD_LONG_INLINE_LFLAGS_LSO UINT32_C(0x20)
2996 /* Since LSO is not supported with inline BDs, this bit is not used. */
2997 #define TX_BD_LONG_INLINE_LFLAGS_IPID_FMT UINT32_C(0x40)
2998 /* Since LSO is not supported with inline BDs, this bit is not used. */
2999 #define TX_BD_LONG_INLINE_LFLAGS_T_IPID UINT32_C(0x80)
3001 * If set to '1', then the RoCE ICRC will be appended to the
3002 * packet. Packet must be a valid RoCE format packet.
3004 #define TX_BD_LONG_INLINE_LFLAGS_ROCE_CRC UINT32_C(0x100)
3006 * If set to '1', then the FCoE CRC will be appended to the
3007 * packet. Packet must be a valid FCoE format packet.
3009 #define TX_BD_LONG_INLINE_LFLAGS_FCOE_CRC UINT32_C(0x200)
3011 * If set to '1', then the timestamp from the BD is used. If cleared
3012 * to 0, then TWE provides the timestamp.
3014 #define TX_BD_LONG_INLINE_LFLAGS_BD_TS_EN UINT32_C(0x400)
3016 * If set to '1', this operation will cause a trace capture in each
3017 * block it passes through.
3019 #define TX_BD_LONG_INLINE_LFLAGS_DEBUG_TRACE UINT32_C(0x800)
3021 * If set to '1', the device will record the time at which the packet
3022 * was actually transmitted at the TX MAC for 1-step time sync. This
3023 * bit must be valid on the first BD of a packet.
3025 #define TX_BD_LONG_INLINE_LFLAGS_STAMP_1STEP UINT32_C(0x1000)
3027 * If set to '1', the controller replaces the Outer-tunnel IP checksum
3028 * field with hardware calculated IP checksum for the IP header of the
3029 * packet associated with this descriptor. For outer UDP checksum, it
3030 * will be the following behavior for all cases independent of settings
3031 * of inner LSO and checksum offload BD flags. If outer UDP checksum
3032 * is 0, then do not update it. If outer UDP checksum is non zero, then
3033 * the hardware should compute and update it.
3035 #define TX_BD_LONG_INLINE_LFLAGS_OT_IP_CHKSUM UINT32_C(0x2000)
3037 * If set to zero when LSO is '1', then the IPID of the Outer-tunnel IP
3038 * header will not be modified during LSO operations. If set to one
3039 * when LSO is '1', then the IPID of the Outer-tunnel IP header will be
3040 * incremented for each subsequent segment of an LSO operation. The
3041 * flag is ignored if the LSO packet is a normal (non-tunneled) TCP
3044 #define TX_BD_LONG_INLINE_LFLAGS_OT_IPID UINT32_C(0x4000)
3046 * If set to '1', When set to 1, KTLS encryption will be enabled for
3049 #define TX_BD_LONG_INLINE_LFLAGS_CRYPTO_EN UINT32_C(0x8000)
3051 uint8_t kid_or_ts_low;
3052 #define TX_BD_LONG_INLINE_UNUSED UINT32_C(0x1)
3054 * If lflags.bd_ts_en is 1, this is the lower 7 bits of the 24-bit
3055 * timestamp. If lflags.crypto_en is 1, this is the lower 7 bits of
3058 #define TX_BD_LONG_INLINE_KID_OR_TS_LOW_MASK UINT32_C(0xfe)
3059 #define TX_BD_LONG_INLINE_KID_OR_TS_LOW_SFT 1
3060 uint32_t kid_or_ts_high;
3061 #define TX_BD_LONG_INLINE_UNUSED_MASK UINT32_C(0x7fff)
3062 #define TX_BD_LONG_INLINE_UNUSED_SFT 0
3064 * If lflags.bd_ts_en is 1, this is the upper 17 bits of the 24-bit
3065 * timestamp. If lflags.crypto_en is 1, the least significant 13 bits
3066 * of this field contain the upper 13 bits of the 20-bit KID.
3068 #define TX_BD_LONG_INLINE_KID_OR_TS_HIGH_MASK UINT32_C(0xffff8000)
3069 #define TX_BD_LONG_INLINE_KID_OR_TS_HIGH_SFT 15
3071 * This value selects bits 25:16 of the CFA action to perform on the
3072 * packet. See the cfa_action field for more information.
3074 uint16_t cfa_action_high;
3075 #define TX_BD_LONG_INLINE_CFA_ACTION_HIGH_MASK UINT32_C(0x3ff)
3076 #define TX_BD_LONG_INLINE_CFA_ACTION_HIGH_SFT 0
3078 * This value selects a CFA action to perform on the packet.
3079 * Set this value to zero if no CFA action is desired.
3081 * This value must be valid on the first BD of a packet.
3083 uint16_t cfa_action;
3085 * This value is action meta-data that defines CFA edit operations
3086 * that are done in addition to any action editing.
3089 /* When key = 1, this is the VLAN tag VID value. */
3090 #define TX_BD_LONG_INLINE_CFA_META_VLAN_VID_MASK UINT32_C(0xfff)
3091 #define TX_BD_LONG_INLINE_CFA_META_VLAN_VID_SFT 0
3092 /* When key = 1, this is the VLAN tag DE value. */
3093 #define TX_BD_LONG_INLINE_CFA_META_VLAN_DE \
3095 /* When key = 1, this is the VLAN tag PRI value. */
3096 #define TX_BD_LONG_INLINE_CFA_META_VLAN_PRI_MASK \
3098 #define TX_BD_LONG_INLINE_CFA_META_VLAN_PRI_SFT 13
3099 /* When key = 1, this is the VLAN tag TPID select value. */
3100 #define TX_BD_LONG_INLINE_CFA_META_VLAN_TPID_MASK \
3102 #define TX_BD_LONG_INLINE_CFA_META_VLAN_TPID_SFT 16
3104 #define TX_BD_LONG_INLINE_CFA_META_VLAN_TPID_TPID88A8 \
3105 (UINT32_C(0x0) << 16)
3107 #define TX_BD_LONG_INLINE_CFA_META_VLAN_TPID_TPID8100 \
3108 (UINT32_C(0x1) << 16)
3110 #define TX_BD_LONG_INLINE_CFA_META_VLAN_TPID_TPID9100 \
3111 (UINT32_C(0x2) << 16)
3113 #define TX_BD_LONG_INLINE_CFA_META_VLAN_TPID_TPID9200 \
3114 (UINT32_C(0x3) << 16)
3116 #define TX_BD_LONG_INLINE_CFA_META_VLAN_TPID_TPID9300 \
3117 (UINT32_C(0x4) << 16)
3118 /* Value programmed in CFA VLANTPID register. */
3119 #define TX_BD_LONG_INLINE_CFA_META_VLAN_TPID_TPIDCFG \
3120 (UINT32_C(0x5) << 16)
3121 #define TX_BD_LONG_INLINE_CFA_META_VLAN_TPID_LAST \
3122 TX_BD_LONG_INLINE_CFA_META_VLAN_TPID_TPIDCFG
3123 #define TX_BD_LONG_INLINE_CFA_META_VLAN_RESERVED_MASK \
3125 #define TX_BD_LONG_INLINE_CFA_META_VLAN_RESERVED_SFT 19
3127 * This field identifies the type of edit to be performed
3130 * This value must be valid on the first BD of a packet.
3132 #define TX_BD_LONG_INLINE_CFA_META_KEY_MASK \
3133 UINT32_C(0xf0000000)
3134 #define TX_BD_LONG_INLINE_CFA_META_KEY_SFT 28
3136 #define TX_BD_LONG_INLINE_CFA_META_KEY_NONE \
3137 (UINT32_C(0x0) << 28)
3139 * - meta[17:16] - TPID select value (0 = 0x8100).
3140 * - meta[15:12] - PRI/DE value.
3141 * - meta[11:0] - VID value.
3143 #define TX_BD_LONG_INLINE_CFA_META_KEY_VLAN_TAG \
3144 (UINT32_C(0x1) << 28)
3147 * - Wh+/SR - this option is not supported.
3148 * - Thor - cfa_meta[15:0] is used for metadata output if en_bd_meta
3149 * is set in the Lookup Table.
3150 * - SR2 - {4’d0, cfa_meta[27:0]} is used for metadata output if
3151 * en_bd_meta is set in the Lookup Table.
3153 #define TX_BD_LONG_INLINE_CFA_META_KEY_METADATA_TRANSFER \
3154 (UINT32_C(0x2) << 28)
3155 #define TX_BD_LONG_INLINE_CFA_META_KEY_LAST \
3156 TX_BD_LONG_INLINE_CFA_META_KEY_METADATA_TRANSFER
3159 /* tx_bd_empty (size:128b/16B) */
3160 struct tx_bd_empty {
3161 /* This value identifies the type of buffer descriptor. */
3163 #define TX_BD_EMPTY_TYPE_MASK UINT32_C(0x3f)
3164 #define TX_BD_EMPTY_TYPE_SFT 0
3166 * Indicates that this BD is 1BB long and is an empty
3167 * TX BD. Not valid for use by the driver.
3169 #define TX_BD_EMPTY_TYPE_TX_BD_EMPTY UINT32_C(0x1)
3170 #define TX_BD_EMPTY_TYPE_LAST TX_BD_EMPTY_TYPE_TX_BD_EMPTY
3171 uint8_t unused_1[3];
3173 uint8_t unused_3[3];
3174 uint8_t unused_4[8];
3177 /* tx_bd_mp_cmd (size:128b/16B) */
3178 struct tx_bd_mp_cmd {
3179 /* Unless otherwise stated, sub-fields of this field are always valid. */
3180 uint16_t flags_type;
3181 /* This value identifies the type of buffer descriptor. */
3182 #define TX_BD_MP_CMD_TYPE_MASK UINT32_C(0x3f)
3183 #define TX_BD_MP_CMD_TYPE_SFT 0
3185 * Indicates that this BD is used to issue a command to one of
3186 * the mid-path destinations.
3188 #define TX_BD_MP_CMD_TYPE_TX_BD_MP_CMD UINT32_C(0x8)
3189 #define TX_BD_MP_CMD_TYPE_LAST TX_BD_MP_CMD_TYPE_TX_BD_MP_CMD
3190 #define TX_BD_MP_CMD_FLAGS_MASK UINT32_C(0xffc0)
3191 #define TX_BD_MP_CMD_FLAGS_SFT 6
3193 #define TX_BD_MP_CMD_FLAGS_UNUSED_MASK UINT32_C(0xc0)
3194 #define TX_BD_MP_CMD_FLAGS_UNUSED_SFT 6
3196 * This value indicates the number of 16B BD locations (slots)
3197 * consumed in the ring by this mid-path command BD, including the
3198 * BD header and the command field.
3200 #define TX_BD_MP_CMD_FLAGS_BD_CNT_MASK UINT32_C(0x1f00)
3201 #define TX_BD_MP_CMD_FLAGS_BD_CNT_SFT 8
3203 * This value defines the length of command field in bytes. The maximum
3204 * value shall be 496.
3208 * The opaque data field is pass through to the completion and can be
3209 * used for any data that the driver wants to associate with this
3210 * Tx mid-path command.
3216 /* tx_bd_presync_cmd (size:128b/16B) */
3217 struct tx_bd_presync_cmd {
3218 /* Unless otherwise stated, sub-fields of this field are always valid. */
3219 uint16_t flags_type;
3220 /* This value identifies the type of buffer descriptor. */
3221 #define TX_BD_PRESYNC_CMD_TYPE_MASK UINT32_C(0x3f)
3222 #define TX_BD_PRESYNC_CMD_TYPE_SFT 0
3224 * Indicates that this BD is used to issue a cryptographic pre-
3225 * sync command through the fast path and destined for TCE.
3227 #define TX_BD_PRESYNC_CMD_TYPE_TX_BD_PRESYNC_CMD UINT32_C(0x9)
3228 #define TX_BD_PRESYNC_CMD_TYPE_LAST \
3229 TX_BD_PRESYNC_CMD_TYPE_TX_BD_PRESYNC_CMD
3230 #define TX_BD_PRESYNC_CMD_FLAGS_MASK UINT32_C(0xffc0)
3231 #define TX_BD_PRESYNC_CMD_FLAGS_SFT 6
3233 #define TX_BD_PRESYNC_CMD_FLAGS_UNUSED_MASK UINT32_C(0xc0)
3234 #define TX_BD_PRESYNC_CMD_FLAGS_UNUSED_SFT 6
3236 * This value indicates the number of 16B BD locations (slots)
3237 * consumed in the ring by this pre-sync command BD, including the
3238 * BD header and the command field.
3240 #define TX_BD_PRESYNC_CMD_FLAGS_BD_CNT_MASK UINT32_C(0x1f00)
3241 #define TX_BD_PRESYNC_CMD_FLAGS_BD_CNT_SFT 8
3243 * This value defines the length of command field in bytes. The maximum
3244 * value shall be 496.
3248 * The opaque data field is pass through to TCE and can be used for
3253 * This field is the Crypto Context ID to which the retransmit packet is
3254 * applied. The KID references the context fields used by the
3255 * associated kTLS offloaded connection.
3259 * The KID value of all-ones is reserved for non-KTLS packets, which
3260 * only implies that this value must not be used when filling this
3261 * field for crypto packets.
3263 #define TX_BD_PRESYNC_CMD_KID_VAL_MASK UINT32_C(0xfffff)
3264 #define TX_BD_PRESYNC_CMD_KID_VAL_SFT 0
3268 /* rx_prod_pkt_bd (size:128b/16B) */
3269 struct rx_prod_pkt_bd {
3270 /* This value identifies the type of buffer descriptor. */
3271 uint16_t flags_type;
3272 /* This value identifies the type of buffer descriptor. */
3273 #define RX_PROD_PKT_BD_TYPE_MASK UINT32_C(0x3f)
3274 #define RX_PROD_PKT_BD_TYPE_SFT 0
3276 * Indicates that this BD is 16B long and is an RX Producer
3277 * (i.e. empty) buffer descriptor.
3279 #define RX_PROD_PKT_BD_TYPE_RX_PROD_PKT UINT32_C(0x4)
3280 #define RX_PROD_PKT_BD_TYPE_LAST \
3281 RX_PROD_PKT_BD_TYPE_RX_PROD_PKT
3282 #define RX_PROD_PKT_BD_FLAGS_MASK UINT32_C(0xffc0)
3283 #define RX_PROD_PKT_BD_FLAGS_SFT 6
3285 * If set to 1, the packet will be placed at the address plus
3286 * 2B. The 2 Bytes of padding will be written as zero.
3288 #define RX_PROD_PKT_BD_FLAGS_SOP_PAD UINT32_C(0x40)
3290 * If set to 1, the packet write will be padded out to the
3291 * nearest cache-line with zero value padding.
3293 #define RX_PROD_PKT_BD_FLAGS_EOP_PAD UINT32_C(0x80)
3295 * This field has been deprecated. There can be no additional
3296 * BDs for this packet from this ring.
3299 * This value is the number of additional buffers in the ring that
3300 * describe the buffer space to be consumed for this packet.
3301 * If the value is zero, then the packet must fit within the
3302 * space described by this BD. If this value is 1 or more, it
3303 * indicates how many additional "buffer" BDs are in the ring
3304 * immediately following this BD to be used for the same
3305 * network packet. Even if the packet to be placed does not need
3306 * all the additional buffers, they will be consumed anyway.
3308 #define RX_PROD_PKT_BD_FLAGS_BUFFERS_MASK UINT32_C(0x300)
3309 #define RX_PROD_PKT_BD_FLAGS_BUFFERS_SFT 8
3311 * This is the length in Bytes of the host physical buffer where
3312 * data for the packet may be placed in host memory.
3316 * The opaque data field is pass through to the completion and can be
3317 * used for any data that the driver wants to associate with this
3318 * receive buffer set.
3322 * This is the host physical address where data for the packet may
3323 * be placed in host memory.
3328 /* rx_prod_bfr_bd (size:128b/16B) */
3329 struct rx_prod_bfr_bd {
3330 /* This value identifies the type of buffer descriptor. */
3331 uint16_t flags_type;
3332 /* This value identifies the type of buffer descriptor. */
3333 #define RX_PROD_BFR_BD_TYPE_MASK UINT32_C(0x3f)
3334 #define RX_PROD_BFR_BD_TYPE_SFT 0
3336 * Indicates that this BD is 16B long and is an RX
3337 * Producer Buffer BD.
3339 #define RX_PROD_BFR_BD_TYPE_RX_PROD_BFR UINT32_C(0x5)
3340 #define RX_PROD_BFR_BD_TYPE_LAST RX_PROD_BFR_BD_TYPE_RX_PROD_BFR
3341 #define RX_PROD_BFR_BD_FLAGS_MASK UINT32_C(0xffc0)
3342 #define RX_PROD_BFR_BD_FLAGS_SFT 6
3344 * This is the length in Bytes of the host physical buffer where
3345 * data for the packet may be placed in host memory.
3348 /* This field is not used. */
3351 * This is the host physical address where data for the packet may
3352 * be placed in host memory.
3357 /* rx_prod_agg_bd (size:128b/16B) */
3358 struct rx_prod_agg_bd {
3359 /* This value identifies the type of buffer descriptor. */
3360 uint16_t flags_type;
3361 /* This value identifies the type of buffer descriptor. */
3362 #define RX_PROD_AGG_BD_TYPE_MASK UINT32_C(0x3f)
3363 #define RX_PROD_AGG_BD_TYPE_SFT 0
3365 * Indicates that this BD is 16B long and is an
3366 * RX Producer Assembly Buffer Descriptor.
3368 #define RX_PROD_AGG_BD_TYPE_RX_PROD_AGG UINT32_C(0x6)
3369 #define RX_PROD_AGG_BD_TYPE_LAST \
3370 RX_PROD_AGG_BD_TYPE_RX_PROD_AGG
3371 #define RX_PROD_AGG_BD_FLAGS_MASK UINT32_C(0xffc0)
3372 #define RX_PROD_AGG_BD_FLAGS_SFT 6
3374 * If set to 1, the packet write will be padded out to the
3375 * nearest cache-line with zero value padding.
3377 #define RX_PROD_AGG_BD_FLAGS_EOP_PAD UINT32_C(0x40)
3379 * This is the length in Bytes of the host physical buffer where
3380 * data for the packet may be placed in host memory.
3384 * The opaque data field is pass through to the completion and can be
3385 * used for any data that the driver wants to associate with this
3386 * receive assembly buffer.
3390 * This is the host physical address where data for the packet may
3391 * be placed in host memory.
3396 /* cfa_cmpls_cmp_data_msg (size:128b/16B) */
3397 struct cfa_cmpls_cmp_data_msg {
3398 uint32_t mp_client_dma_length_opcode_status_type;
3400 * This field represents the Mid-Path client that generated the
3403 #define CFA_CMPLS_CMP_DATA_MSG_TYPE_MASK UINT32_C(0x3f)
3404 #define CFA_CMPLS_CMP_DATA_MSG_TYPE_SFT 0
3405 /* Mid Path Short Completion with length = 16B. */
3406 #define CFA_CMPLS_CMP_DATA_MSG_TYPE_MID_PATH_SHORT \
3408 #define CFA_CMPLS_CMP_DATA_MSG_TYPE_LAST \
3409 CFA_CMPLS_CMP_DATA_MSG_TYPE_MID_PATH_SHORT
3410 /* This value indicates the status for the command. */
3411 #define CFA_CMPLS_CMP_DATA_MSG_STATUS_MASK UINT32_C(0x3c0)
3412 #define CFA_CMPLS_CMP_DATA_MSG_STATUS_SFT 6
3413 /* Completed without error. */
3414 #define CFA_CMPLS_CMP_DATA_MSG_STATUS_OK \
3415 (UINT32_C(0x0) << 6)
3416 /* Indicates an unsupported CFA opcode in the command. */
3417 #define CFA_CMPLS_CMP_DATA_MSG_STATUS_UNSPRT_ERR \
3418 (UINT32_C(0x1) << 6)
3420 * Indicates a CFA command formatting error. This error can occur on
3421 * any of the supported CFA commands.
3423 #define CFA_CMPLS_CMP_DATA_MSG_STATUS_FMT_ERR \
3424 (UINT32_C(0x2) << 6)
3426 * Indicates an SVIF-Table scope error. This error can occur on any
3427 * of the supported CFA commands.
3429 #define CFA_CMPLS_CMP_DATA_MSG_STATUS_SCOPE_ERR \
3430 (UINT32_C(0x3) << 6)
3432 * Indicates that the table_index is either outside of the
3433 * table_scope range set by its EM_SIZE or, for EM Insert, it is in
3434 * the static bucket range. This error can occur on EM Insert
3435 * commands. It can also occur on Read, Read Clear, Write, and
3436 * Invalidate commands if the table_type is EM.
3438 #define CFA_CMPLS_CMP_DATA_MSG_STATUS_ADDR_ERR \
3439 (UINT32_C(0x4) << 6)
3441 * Cache operation responded with an error. This error can occur on
3442 * Read, Read Clear, Write, EM Insert, and EM Delete commands.
3444 #define CFA_CMPLS_CMP_DATA_MSG_STATUS_CACHE_ERR \
3445 (UINT32_C(0x5) << 6)
3447 * Indicates failure on EM Insert or EM Delete Command. Hash index
3448 * and hash msb are returned in table_index and hash_msb fields.
3449 * Dma_length is set to 1 if the bucket is also returned (as dma
3452 #define CFA_CMPLS_CMP_DATA_MSG_STATUS_EM_FAIL \
3453 (UINT32_C(0x6) << 6)
3455 * Indicates no notifications were available on an Event Collection
3458 #define CFA_CMPLS_CMP_DATA_MSG_STATUS_EVENT_COLLECT_FAIL \
3459 (UINT32_C(0x7) << 6)
3460 #define CFA_CMPLS_CMP_DATA_MSG_STATUS_LAST \
3461 CFA_CMPLS_CMP_DATA_MSG_STATUS_EVENT_COLLECT_FAIL
3462 #define CFA_CMPLS_CMP_DATA_MSG_UNUSED0_MASK UINT32_C(0xc00)
3463 #define CFA_CMPLS_CMP_DATA_MSG_UNUSED0_SFT 10
3464 /* This is the opcode from the command. */
3465 #define CFA_CMPLS_CMP_DATA_MSG_OPCODE_MASK \
3467 #define CFA_CMPLS_CMP_DATA_MSG_OPCODE_SFT 12
3469 * This is read command. From 32 to 128B can be read from a table
3470 * using this command.
3472 #define CFA_CMPLS_CMP_DATA_MSG_OPCODE_READ \
3473 (UINT32_C(0x0) << 12)
3475 * This is write command. From 32 to 128B can be written to a table
3476 * using this command.
3478 #define CFA_CMPLS_CMP_DATA_MSG_OPCODE_WRITE \
3479 (UINT32_C(0x1) << 12)
3481 * This is read-clear command. 32B can be read from a table and a 16b
3482 * mask can be used to clear specific 16b units after the read as an
3485 #define CFA_CMPLS_CMP_DATA_MSG_OPCODE_READ_CLR \
3486 (UINT32_C(0x2) << 12)
3488 * An exact match table insert will be attempted into the table. If
3489 * there is a free location in the bucket, the payload will be
3490 * written to the bucket.
3492 #define CFA_CMPLS_CMP_DATA_MSG_OPCODE_EM_INSERT \
3493 (UINT32_C(0x3) << 12)
3494 /* An exact match table delete will be attempted. */
3495 #define CFA_CMPLS_CMP_DATA_MSG_OPCODE_EM_DELETE \
3496 (UINT32_C(0x4) << 12)
3498 * The specified table area will be invalidated. If it is needed
3499 * again, it will be read from the backing store.
3501 #define CFA_CMPLS_CMP_DATA_MSG_OPCODE_INVALIDATE \
3502 (UINT32_C(0x5) << 12)
3503 /* Reads notification messages from the Host Notification Queue. */
3504 #define CFA_CMPLS_CMP_DATA_MSG_OPCODE_EVENT_COLLECT \
3505 (UINT32_C(0x6) << 12)
3506 #define CFA_CMPLS_CMP_DATA_MSG_OPCODE_LAST \
3507 CFA_CMPLS_CMP_DATA_MSG_OPCODE_EVENT_COLLECT
3509 * This field indicates the length of the DMA that accompanies the
3510 * completion. Specified in units of DWords (32b). Valid values are
3511 * between 0 and 128. A value of zero indicates that there is no DMA
3512 * that accompanies the completion.
3514 #define CFA_CMPLS_CMP_DATA_MSG_DMA_LENGTH_MASK \
3516 #define CFA_CMPLS_CMP_DATA_MSG_DMA_LENGTH_SFT 20
3518 * This field represents the Mid-Path client that generated the
3521 #define CFA_CMPLS_CMP_DATA_MSG_MP_CLIENT_MASK \
3522 UINT32_C(0xf0000000)
3523 #define CFA_CMPLS_CMP_DATA_MSG_MP_CLIENT_SFT 28
3524 /* TX configurable flow processing block. */
3525 #define CFA_CMPLS_CMP_DATA_MSG_MP_CLIENT_TE_CFA \
3526 (UINT32_C(0x2) << 28)
3527 /* RX configurable flow processing block. */
3528 #define CFA_CMPLS_CMP_DATA_MSG_MP_CLIENT_RE_CFA \
3529 (UINT32_C(0x3) << 28)
3530 #define CFA_CMPLS_CMP_DATA_MSG_MP_CLIENT_LAST \
3531 CFA_CMPLS_CMP_DATA_MSG_MP_CLIENT_RE_CFA
3533 * This is a copy of the opaque field from the mid path BD of this
3537 uint16_t hash_msb_v;
3539 * This value is written by the NIC such that it will be different for
3540 * each pass through the completion queue. The even passes will
3541 * write 1. The odd passes will write 0.
3543 #define CFA_CMPLS_CMP_DATA_MSG_V UINT32_C(0x1)
3544 #define CFA_CMPLS_CMP_DATA_MSG_UNUSED1_MASK UINT32_C(0xe)
3545 #define CFA_CMPLS_CMP_DATA_MSG_UNUSED1_SFT 1
3547 * This is the upper 12b of the hash, returned on Exact Match
3548 * Insertion/Deletion Commands.
3550 #define CFA_CMPLS_CMP_DATA_MSG_HASH_MSB_MASK UINT32_C(0xfff0)
3551 #define CFA_CMPLS_CMP_DATA_MSG_HASH_MSB_SFT 4
3552 /* This is the table type from the command. */
3554 #define CFA_CMPLS_CMP_DATA_MSG_UNUSED2_MASK UINT32_C(0xf)
3555 #define CFA_CMPLS_CMP_DATA_MSG_UNUSED2_SFT 0
3556 #define CFA_CMPLS_CMP_DATA_MSG_TABLE_TYPE_MASK UINT32_C(0xf0)
3557 #define CFA_CMPLS_CMP_DATA_MSG_TABLE_TYPE_SFT 4
3558 /* This command acts on the action table of the specified scope. */
3559 #define CFA_CMPLS_CMP_DATA_MSG_TABLE_TYPE_ACTION (UINT32_C(0x0) << 4)
3560 /* This command acts on the exact match table of the specified scope. */
3561 #define CFA_CMPLS_CMP_DATA_MSG_TABLE_TYPE_EM (UINT32_C(0x1) << 4)
3562 #define CFA_CMPLS_CMP_DATA_MSG_TABLE_TYPE_LAST \
3563 CFA_CMPLS_CMP_DATA_MSG_TABLE_TYPE_EM
3564 uint8_t table_scope;
3565 /* This is the table scope from the command. */
3566 #define CFA_CMPLS_CMP_DATA_MSG_TABLE_SCOPE_MASK UINT32_C(0x1f)
3567 #define CFA_CMPLS_CMP_DATA_MSG_TABLE_SCOPE_SFT 0
3568 uint32_t table_index;
3570 * This is the table index from the command (if it exists). However, if
3571 * an Exact Match Insertion/Deletion command failed, then this is the
3572 * table index of the calculated static hash bucket.
3574 #define CFA_CMPLS_CMP_DATA_MSG_TABLE_INDEX_MASK UINT32_C(0x3ffffff)
3575 #define CFA_CMPLS_CMP_DATA_MSG_TABLE_INDEX_SFT 0
3578 /* CFA Mid-Path 32B DMA Message */
3579 /* cfa_dma32b_data_msg (size:256b/32B) */
3580 struct cfa_dma32b_data_msg {
3581 /* DMA data value. */
3585 /* CFA Mid-Path 64B DMA Message */
3586 /* cfa_dma64b_data_msg (size:512b/64B) */
3587 struct cfa_dma64b_data_msg {
3588 /* DMA data value. */
3592 /* CFA Mid-Path 96B DMA Message */
3593 /* cfa_dma96b_data_msg (size:768b/96B) */
3594 struct cfa_dma96b_data_msg {
3595 /* DMA data value. */
3599 /* CFA Mid-Path 128B DMA Message */
3600 /* cfa_dma128b_data_msg (size:1024b/128B) */
3601 struct cfa_dma128b_data_msg {
3602 /* DMA data value. */
3606 /* ce_cmpls_cmp_data_msg (size:128b/16B) */
3607 struct ce_cmpls_cmp_data_msg {
3608 uint16_t status_subtype_type;
3610 * This field indicates the exact type of the completion. By
3611 * convention, the LSB identifies the length of the record in 16B
3612 * units. Even values indicate 16B records. Odd values indicate 32B
3615 #define CE_CMPLS_CMP_DATA_MSG_TYPE_MASK UINT32_C(0x3f)
3616 #define CE_CMPLS_CMP_DATA_MSG_TYPE_SFT 0
3617 /* Completion of a Mid Path Command. Length = 16B */
3618 #define CE_CMPLS_CMP_DATA_MSG_TYPE_MID_PATH_SHORT UINT32_C(0x1e)
3619 #define CE_CMPLS_CMP_DATA_MSG_TYPE_LAST \
3620 CE_CMPLS_CMP_DATA_MSG_TYPE_MID_PATH_SHORT
3622 * This value indicates the CE sub-type operation that is being
3625 #define CE_CMPLS_CMP_DATA_MSG_SUBTYPE_MASK UINT32_C(0x3c0)
3626 #define CE_CMPLS_CMP_DATA_MSG_SUBTYPE_SFT 6
3627 /* Completion Response for a Solicited Command. */
3628 #define CE_CMPLS_CMP_DATA_MSG_SUBTYPE_SOLICITED (UINT32_C(0x0) << 6)
3629 /* Error Completion (Unsolicited). */
3630 #define CE_CMPLS_CMP_DATA_MSG_SUBTYPE_ERR (UINT32_C(0x1) << 6)
3631 /* Re-Sync Completion (Unsolicited) */
3632 #define CE_CMPLS_CMP_DATA_MSG_SUBTYPE_RESYNC (UINT32_C(0x2) << 6)
3633 #define CE_CMPLS_CMP_DATA_MSG_SUBTYPE_LAST \
3634 CE_CMPLS_CMP_DATA_MSG_SUBTYPE_RESYNC
3635 /* This value indicates the status for the command. */
3636 #define CE_CMPLS_CMP_DATA_MSG_STATUS_MASK UINT32_C(0x3c00)
3637 #define CE_CMPLS_CMP_DATA_MSG_STATUS_SFT 10
3638 /* Completed without error. */
3639 #define CE_CMPLS_CMP_DATA_MSG_STATUS_OK \
3640 (UINT32_C(0x0) << 10)
3641 /* CFCK load error. */
3642 #define CE_CMPLS_CMP_DATA_MSG_STATUS_CTX_LD_ERR \
3643 (UINT32_C(0x1) << 10)
3644 /* FID check error. */
3645 #define CE_CMPLS_CMP_DATA_MSG_STATUS_FID_CHK_ERR \
3646 (UINT32_C(0x2) << 10)
3647 #define CE_CMPLS_CMP_DATA_MSG_STATUS_LAST \
3648 CE_CMPLS_CMP_DATA_MSG_STATUS_FID_CHK_ERR
3651 #define CE_CMPLS_CMP_DATA_MSG_UNUSED1_MASK UINT32_C(0xf)
3652 #define CE_CMPLS_CMP_DATA_MSG_UNUSED1_SFT 0
3654 * This field represents the Mid-Path client that generated the
3657 #define CE_CMPLS_CMP_DATA_MSG_MP_CLIENTS_MASK UINT32_C(0xf0)
3658 #define CE_CMPLS_CMP_DATA_MSG_MP_CLIENTS_SFT 4
3659 /* TX crypto engine block. */
3660 #define CE_CMPLS_CMP_DATA_MSG_MP_CLIENTS_TCE (UINT32_C(0x0) << 4)
3661 /* RX crypto engine block. */
3662 #define CE_CMPLS_CMP_DATA_MSG_MP_CLIENTS_RCE (UINT32_C(0x1) << 4)
3663 #define CE_CMPLS_CMP_DATA_MSG_MP_CLIENTS_LAST \
3664 CE_CMPLS_CMP_DATA_MSG_MP_CLIENTS_RCE
3666 * This is a copy of the opaque field from the mid path BD of this
3673 * This value is written by the NIC such that it will be different
3674 * for each pass through the completion queue. The even passes will
3675 * write 1. The odd passes will write 0.
3677 #define CE_CMPLS_CMP_DATA_MSG_V UINT32_C(0x1)
3679 * This field is the Crypto Context ID. The KID is used to store
3680 * information used by the associated kTLS offloaded connection.
3682 #define CE_CMPLS_CMP_DATA_MSG_KID_MASK UINT32_C(0x1ffffe)
3683 #define CE_CMPLS_CMP_DATA_MSG_KID_SFT 1
3687 /* cmpl_base (size:128b/16B) */
3691 * This field indicates the exact type of the completion.
3692 * By convention, the LSB identifies the length of the
3693 * record in 16B units. Even values indicate 16B
3694 * records. Odd values indicate 32B
3697 #define CMPL_BASE_TYPE_MASK UINT32_C(0x3f)
3698 #define CMPL_BASE_TYPE_SFT 0
3701 * Completion of TX packet. Length = 16B
3703 #define CMPL_BASE_TYPE_TX_L2 UINT32_C(0x0)
3706 * Completion of NO-OP. Length = 16B
3708 #define CMPL_BASE_TYPE_NO_OP UINT32_C(0x1)
3710 * TX L2 coalesced completion:
3711 * Completion of coalesced TX packet. Length = 16B
3713 #define CMPL_BASE_TYPE_TX_L2_COAL UINT32_C(0x2)
3715 * TX L2 PTP completion:
3716 * Completion of PTP TX packet. Length = 32B
3718 #define CMPL_BASE_TYPE_TX_L2_PTP UINT32_C(0x3)
3720 * RX L2 TPA Start V2 Completion:
3721 * Completion of and L2 RX packet. Length = 32B
3722 * This is the new version of the RX_TPA_START completion used
3723 * in SR2 and later chips.
3725 #define CMPL_BASE_TYPE_RX_TPA_START_V2 UINT32_C(0xd)
3727 * RX L2 V2 completion:
3728 * Completion of and L2 RX packet. Length = 32B
3729 * This is the new version of the RX_L2 completion used in SR2
3732 #define CMPL_BASE_TYPE_RX_L2_V2 UINT32_C(0xf)
3735 * Completion of and L2 RX packet. Length = 32B
3737 #define CMPL_BASE_TYPE_RX_L2 UINT32_C(0x11)
3739 * RX Aggregation Buffer completion :
3740 * Completion of an L2 aggregation buffer in support of
3741 * TPA, HDS, or Jumbo packet completion. Length = 16B
3743 #define CMPL_BASE_TYPE_RX_AGG UINT32_C(0x12)
3745 * RX L2 TPA Start Completion:
3746 * Completion at the beginning of a TPA operation.
3749 #define CMPL_BASE_TYPE_RX_TPA_START UINT32_C(0x13)
3751 * RX L2 TPA End Completion:
3752 * Completion at the end of a TPA operation.
3755 #define CMPL_BASE_TYPE_RX_TPA_END UINT32_C(0x15)
3757 * Statistics Ejection Completion:
3758 * Completion of statistics data ejection buffer.
3761 #define CMPL_BASE_TYPE_STAT_EJECT UINT32_C(0x1a)
3763 * VEE Flush Completion:
3764 * This completion is inserted manually by
3765 * the Primate and processed by the VEE hardware to ensure that
3766 * all completions on a VEE function have been processed by the
3767 * VEE hardware before FLR process is completed.
3769 #define CMPL_BASE_TYPE_VEE_FLUSH UINT32_C(0x1c)
3771 * Mid Path Short Completion :
3772 * Completion of a Mid Path Command. Length = 16B
3774 #define CMPL_BASE_TYPE_MID_PATH_SHORT UINT32_C(0x1e)
3776 * Mid Path Long Completion :
3777 * Completion of a Mid Path Command. Length = 32B
3779 #define CMPL_BASE_TYPE_MID_PATH_LONG UINT32_C(0x1f)
3781 * HWRM Command Completion:
3782 * Completion of an HWRM command.
3784 #define CMPL_BASE_TYPE_HWRM_DONE UINT32_C(0x20)
3785 /* Forwarded HWRM Request */
3786 #define CMPL_BASE_TYPE_HWRM_FWD_REQ UINT32_C(0x22)
3787 /* Forwarded HWRM Response */
3788 #define CMPL_BASE_TYPE_HWRM_FWD_RESP UINT32_C(0x24)
3789 /* HWRM Asynchronous Event Information */
3790 #define CMPL_BASE_TYPE_HWRM_ASYNC_EVENT UINT32_C(0x2e)
3791 /* CQ Notification */
3792 #define CMPL_BASE_TYPE_CQ_NOTIFICATION UINT32_C(0x30)
3793 /* SRQ Threshold Event */
3794 #define CMPL_BASE_TYPE_SRQ_EVENT UINT32_C(0x32)
3795 /* DBQ Threshold Event */
3796 #define CMPL_BASE_TYPE_DBQ_EVENT UINT32_C(0x34)
3797 /* QP Async Notification */
3798 #define CMPL_BASE_TYPE_QP_EVENT UINT32_C(0x38)
3799 /* Function Async Notification */
3800 #define CMPL_BASE_TYPE_FUNC_EVENT UINT32_C(0x3a)
3801 #define CMPL_BASE_TYPE_LAST CMPL_BASE_TYPE_FUNC_EVENT
3807 * This value is written by the NIC such that it will be different
3808 * for each pass through the completion queue. The even passes
3809 * will write 1. The odd passes will write 0.
3812 #define CMPL_BASE_V UINT32_C(0x1)
3813 #define CMPL_BASE_INFO3_MASK UINT32_C(0xfffffffe)
3814 #define CMPL_BASE_INFO3_SFT 1
3819 /* tx_cmpl (size:128b/16B) */
3821 uint16_t flags_type;
3823 * This field indicates the exact type of the completion.
3824 * By convention, the LSB identifies the length of the
3825 * record in 16B units. Even values indicate 16B
3826 * records. Odd values indicate 32B
3829 #define TX_CMPL_TYPE_MASK UINT32_C(0x3f)
3830 #define TX_CMPL_TYPE_SFT 0
3833 * Completion of TX packet. Length = 16B
3835 #define TX_CMPL_TYPE_TX_L2 UINT32_C(0x0)
3836 #define TX_CMPL_TYPE_LAST TX_CMPL_TYPE_TX_L2
3837 #define TX_CMPL_FLAGS_MASK UINT32_C(0xffc0)
3838 #define TX_CMPL_FLAGS_SFT 6
3840 * When this bit is '1', it indicates a packet that has an
3841 * error of some type. Type of error is indicated in
3844 #define TX_CMPL_FLAGS_ERROR UINT32_C(0x40)
3846 * When this bit is '1', it indicates that the packet completed
3847 * was transmitted using the push acceleration data provided
3848 * by the driver. When this bit is '0', it indicates that the
3849 * packet had not push acceleration data written or was executed
3850 * as a normal packet even though push data was provided.
3852 #define TX_CMPL_FLAGS_PUSH UINT32_C(0x80)
3853 /* unused1 is 16 b */
3856 * This is a copy of the opaque field from the first TX BD of this
3857 * transmitted packet. Note that, if the packet was described by a short
3858 * CSO or short CSO inline BD, then the 16-bit opaque field from the
3859 * short CSO BD will appear in the bottom 16 bits of this field.
3864 * This value is written by the NIC such that it will be different
3865 * for each pass through the completion queue. The even passes
3866 * will write 1. The odd passes will write 0.
3868 #define TX_CMPL_V UINT32_C(0x1)
3869 #define TX_CMPL_ERRORS_MASK UINT32_C(0xfffe)
3870 #define TX_CMPL_ERRORS_SFT 1
3872 * This error indicates that there was some sort of problem
3873 * with the BDs for the packet.
3875 #define TX_CMPL_ERRORS_BUFFER_ERROR_MASK UINT32_C(0xe)
3876 #define TX_CMPL_ERRORS_BUFFER_ERROR_SFT 1
3878 #define TX_CMPL_ERRORS_BUFFER_ERROR_NO_ERROR \
3879 (UINT32_C(0x0) << 1)
3882 * BDs were not formatted correctly.
3884 #define TX_CMPL_ERRORS_BUFFER_ERROR_BAD_FMT \
3885 (UINT32_C(0x2) << 1)
3886 #define TX_CMPL_ERRORS_BUFFER_ERROR_LAST \
3887 TX_CMPL_ERRORS_BUFFER_ERROR_BAD_FMT
3889 * When this bit is '1', it indicates that the length of
3890 * the packet was zero. No packet was transmitted.
3892 #define TX_CMPL_ERRORS_ZERO_LENGTH_PKT UINT32_C(0x10)
3894 * When this bit is '1', it indicates that the packet
3895 * was longer than the programmed limit in TDI. No
3896 * packet was transmitted.
3898 #define TX_CMPL_ERRORS_EXCESSIVE_BD_LENGTH UINT32_C(0x20)
3900 * When this bit is '1', it indicates that one or more of the
3901 * BDs associated with this packet generated a PCI error.
3902 * This probably means the address was not valid.
3904 #define TX_CMPL_ERRORS_DMA_ERROR UINT32_C(0x40)
3906 * When this bit is '1', it indicates that the packet was longer
3907 * than indicated by the hint. No packet was transmitted.
3909 #define TX_CMPL_ERRORS_HINT_TOO_SHORT UINT32_C(0x80)
3911 * When this bit is '1', it indicates that the packet was
3912 * dropped due to Poison TLP error on one or more of the
3913 * TLPs in the PXP completion.
3915 #define TX_CMPL_ERRORS_POISON_TLP_ERROR UINT32_C(0x100)
3917 * When this bit is '1', it indicates that the packet was dropped
3918 * due to a transient internal error in TDC. The packet or LSO can
3919 * be retried and may transmit successfully on a subsequent attempt.
3921 #define TX_CMPL_ERRORS_INTERNAL_ERROR UINT32_C(0x200)
3923 * When this bit is '1', it was not possible to collect a a timestamp
3924 * for a PTP completion, in which case the timestamp_hi and
3925 * timestamp_lo fields are invalid. When this bit is '0' for a PTP
3926 * completion, the timestamp_hi and timestamp_lo fields are valid.
3927 * RJRN will copy the value of this bit into the field of the same
3928 * name in all TX completions, regardless of whether such completions
3929 * are PTP completions or other TX completions.
3931 #define TX_CMPL_ERRORS_TIMESTAMP_INVALID_ERROR UINT32_C(0x400)
3932 /* unused2 is 16 b */
3934 /* unused3 is 32 b */
3938 /* tx_cmpl_coal (size:128b/16B) */
3939 struct tx_cmpl_coal {
3940 uint16_t flags_type;
3942 * This field indicates the exact type of the completion.
3943 * By convention, the LSB identifies the length of the
3944 * record in 16B units. Even values indicate 16B
3945 * records. Odd values indicate 32B
3948 #define TX_CMPL_COAL_TYPE_MASK UINT32_C(0x3f)
3949 #define TX_CMPL_COAL_TYPE_SFT 0
3951 * TX L2 coalesced completion:
3952 * Completion of TX packet. Length = 16B
3954 #define TX_CMPL_COAL_TYPE_TX_L2_COAL UINT32_C(0x2)
3955 #define TX_CMPL_COAL_TYPE_LAST TX_CMPL_COAL_TYPE_TX_L2_COAL
3956 #define TX_CMPL_COAL_FLAGS_MASK UINT32_C(0xffc0)
3957 #define TX_CMPL_COAL_FLAGS_SFT 6
3959 * When this bit is '1', it indicates a packet that has an
3960 * error of some type. Type of error is indicated in
3963 #define TX_CMPL_COAL_FLAGS_ERROR UINT32_C(0x40)
3965 * When this bit is '1', it indicates that the packet completed
3966 * was transmitted using the push acceleration data provided
3967 * by the driver. When this bit is '0', it indicates that the
3968 * packet had not push acceleration data written or was executed
3969 * as a normal packet even though push data was provided.
3971 #define TX_CMPL_COAL_FLAGS_PUSH UINT32_C(0x80)
3972 /* unused1 is 16 b */
3975 * This is a copy of the opaque field from the first TX BD of the packet
3976 * which corresponds with the reported sq_cons_idx. Note that, with
3977 * coalesced completions, completions are generated for only some of the
3978 * packets. The driver will see the opaque field for only those packets.
3979 * Note that, if the packet was described by a short CSO or short CSO
3980 * inline BD, then the 16-bit opaque field from the short CSO BD will
3981 * appear in the bottom 16 bits of this field. For TX rings with
3982 * completion coalescing enabled (which would use the coalesced
3983 * completion record), it is suggested that the driver populate the
3984 * opaque field to indicate the specific TX ring with which the
3985 * completion is associated, then utilize the opaque and sq_cons_idx
3986 * fields in the coalesced completion record to determine the specific
3987 * packets that are to be completed on that ring.
3992 * This value is written by the NIC such that it will be different
3993 * for each pass through the completion queue. The even passes
3994 * will write 1. The odd passes will write 0.
3996 #define TX_CMPL_COAL_V UINT32_C(0x1)
3997 #define TX_CMPL_COAL_ERRORS_MASK \
3999 #define TX_CMPL_COAL_ERRORS_SFT 1
4001 * This error indicates that there was some sort of problem
4002 * with the BDs for the packet.
4004 #define TX_CMPL_COAL_ERRORS_BUFFER_ERROR_MASK UINT32_C(0xe)
4005 #define TX_CMPL_COAL_ERRORS_BUFFER_ERROR_SFT 1
4007 #define TX_CMPL_COAL_ERRORS_BUFFER_ERROR_NO_ERROR \
4008 (UINT32_C(0x0) << 1)
4011 * BDs were not formatted correctly.
4013 #define TX_CMPL_COAL_ERRORS_BUFFER_ERROR_BAD_FMT \
4014 (UINT32_C(0x2) << 1)
4015 #define TX_CMPL_COAL_ERRORS_BUFFER_ERROR_LAST \
4016 TX_CMPL_COAL_ERRORS_BUFFER_ERROR_BAD_FMT
4018 * When this bit is '1', it indicates that the length of
4019 * the packet was zero. No packet was transmitted.
4021 #define TX_CMPL_COAL_ERRORS_ZERO_LENGTH_PKT UINT32_C(0x10)
4023 * When this bit is '1', it indicates that the packet
4024 * was longer than the programmed limit in TDI. No
4025 * packet was transmitted.
4027 #define TX_CMPL_COAL_ERRORS_EXCESSIVE_BD_LENGTH UINT32_C(0x20)
4029 * When this bit is '1', it indicates that one or more of the
4030 * BDs associated with this packet generated a PCI error.
4031 * This probably means the address was not valid.
4033 #define TX_CMPL_COAL_ERRORS_DMA_ERROR UINT32_C(0x40)
4035 * When this bit is '1', it indicates that the packet was longer
4036 * than indicated by the hint. No packet was transmitted.
4038 #define TX_CMPL_COAL_ERRORS_HINT_TOO_SHORT UINT32_C(0x80)
4040 * When this bit is '1', it indicates that the packet was
4041 * dropped due to Poison TLP error on one or more of the
4042 * TLPs in the PXP completion.
4044 #define TX_CMPL_COAL_ERRORS_POISON_TLP_ERROR \
4047 * When this bit is '1', it indicates that the packet was dropped
4048 * due to a transient internal error in TDC. The packet or LSO can
4049 * be retried and may transmit successfully on a subsequent attempt.
4051 #define TX_CMPL_COAL_ERRORS_INTERNAL_ERROR \
4054 * When this bit is '1', it was not possible to collect a a timestamp
4055 * for a PTP completion, in which case the timestamp_hi and
4056 * timestamp_lo fields are invalid. When this bit is '0' for a PTP
4057 * completion, the timestamp_hi and timestamp_lo fields are valid.
4058 * RJRN will copy the value of this bit into the field of the same
4059 * name in all TX completions, regardless of whether such
4060 * completions are PTP completions or other TX completions.
4062 #define TX_CMPL_COAL_ERRORS_TIMESTAMP_INVALID_ERROR \
4064 /* unused2 is 16 b */
4066 uint32_t sq_cons_idx;
4068 * This value is SQ index for the start of the packet following the
4069 * last completed packet.
4071 #define TX_CMPL_COAL_SQ_CONS_IDX_MASK UINT32_C(0xffffff)
4072 #define TX_CMPL_COAL_SQ_CONS_IDX_SFT 0
4075 /* tx_cmpl_ptp (size:128b/16B) */
4076 struct tx_cmpl_ptp {
4077 uint16_t flags_type;
4079 * This field indicates the exact type of the completion.
4080 * By convention, the LSB identifies the length of the
4081 * record in 16B units. Even values indicate 16B
4082 * records. Odd values indicate 32B
4085 #define TX_CMPL_PTP_TYPE_MASK UINT32_C(0x3f)
4086 #define TX_CMPL_PTP_TYPE_SFT 0
4088 * TX L2 PTP completion:
4089 * Completion of TX packet. Length = 32B
4091 #define TX_CMPL_PTP_TYPE_TX_L2_PTP UINT32_C(0x2)
4092 #define TX_CMPL_PTP_TYPE_LAST TX_CMPL_PTP_TYPE_TX_L2_PTP
4093 #define TX_CMPL_PTP_FLAGS_MASK UINT32_C(0xffc0)
4094 #define TX_CMPL_PTP_FLAGS_SFT 6
4096 * When this bit is '1', it indicates a packet that has an
4097 * error of some type. Type of error is indicated in
4100 #define TX_CMPL_PTP_FLAGS_ERROR UINT32_C(0x40)
4102 * When this bit is '1', it indicates that the packet completed
4103 * was transmitted using the push acceleration data provided
4104 * by the driver. When this bit is '0', it indicates that the
4105 * packet had not push acceleration data written or was executed
4106 * as a normal packet even though push data was provided.
4108 #define TX_CMPL_PTP_FLAGS_PUSH UINT32_C(0x80)
4109 /* unused1 is 16 b */
4112 * This is a copy of the opaque field from the first TX BD of this
4113 * transmitted packet. Note that, if the packet was described by a short
4114 * CSO or short CSO inline BD, then the 16-bit opaque field from the
4115 * short CSO BD will appear in the bottom 16 bits of this field.
4120 * This value is written by the NIC such that it will be different
4121 * for each pass through the completion queue. The even passes
4122 * will write 1. The odd passes will write 0.
4124 #define TX_CMPL_PTP_V UINT32_C(0x1)
4125 #define TX_CMPL_PTP_ERRORS_MASK UINT32_C(0xfffe)
4126 #define TX_CMPL_PTP_ERRORS_SFT 1
4128 * This error indicates that there was some sort of problem
4129 * with the BDs for the packet.
4131 #define TX_CMPL_PTP_ERRORS_BUFFER_ERROR_MASK UINT32_C(0xe)
4132 #define TX_CMPL_PTP_ERRORS_BUFFER_ERROR_SFT 1
4134 #define TX_CMPL_PTP_ERRORS_BUFFER_ERROR_NO_ERROR \
4135 (UINT32_C(0x0) << 1)
4138 * BDs were not formatted correctly.
4140 #define TX_CMPL_PTP_ERRORS_BUFFER_ERROR_BAD_FMT \
4141 (UINT32_C(0x2) << 1)
4142 #define TX_CMPL_PTP_ERRORS_BUFFER_ERROR_LAST \
4143 TX_CMPL_PTP_ERRORS_BUFFER_ERROR_BAD_FMT
4145 * When this bit is '1', it indicates that the length of
4146 * the packet was zero. No packet was transmitted.
4148 #define TX_CMPL_PTP_ERRORS_ZERO_LENGTH_PKT UINT32_C(0x10)
4150 * When this bit is '1', it indicates that the packet
4151 * was longer than the programmed limit in TDI. No
4152 * packet was transmitted.
4154 #define TX_CMPL_PTP_ERRORS_EXCESSIVE_BD_LENGTH UINT32_C(0x20)
4156 * When this bit is '1', it indicates that one or more of the
4157 * BDs associated with this packet generated a PCI error.
4158 * This probably means the address was not valid.
4160 #define TX_CMPL_PTP_ERRORS_DMA_ERROR UINT32_C(0x40)
4162 * When this bit is '1', it indicates that the packet was longer
4163 * than indicated by the hint. No packet was transmitted.
4165 #define TX_CMPL_PTP_ERRORS_HINT_TOO_SHORT UINT32_C(0x80)
4167 * When this bit is '1', it indicates that the packet was
4168 * dropped due to Poison TLP error on one or more of the
4169 * TLPs in the PXP completion.
4171 #define TX_CMPL_PTP_ERRORS_POISON_TLP_ERROR UINT32_C(0x100)
4173 * When this bit is '1', it indicates that the packet was dropped due
4174 * to a transient internal error in TDC. The packet or LSO can be
4175 * retried and may transmit successfully on a subsequent attempt.
4177 #define TX_CMPL_PTP_ERRORS_INTERNAL_ERROR UINT32_C(0x200)
4179 * When this bit is '1', it was not possible to collect a a timestamp
4180 * for a PTP completion, in which case the timestamp_hi and
4181 * timestamp_lo fields are invalid. When this bit is '0' for a PTP
4182 * completion, the timestamp_hi and timestamp_lo fields are valid.
4183 * RJRN will copy the value of this bit into the field of the same
4184 * name in all TX completions, regardless of whether such
4185 * completions are PTP completions or other TX completions.
4187 #define TX_CMPL_PTP_ERRORS_TIMESTAMP_INVALID_ERROR UINT32_C(0x400)
4188 /* unused2 is 16 b */
4191 * This is timestamp value (lower 32bits) read from PM for the PTP
4192 * timestamp enabled packet.
4194 uint32_t timestamp_lo;
4197 /* tx_cmpl_ptp_hi (size:128b/16B) */
4198 struct tx_cmpl_ptp_hi {
4200 * This is timestamp value (lower 32bits) read from PM for the PTP
4201 * timestamp enabled packet.
4203 uint16_t timestamp_hi[3];
4204 uint16_t reserved16;
4207 * This value is written by the NIC such that it will be different for
4208 * each pass through the completion queue.The even passes will write 1.
4209 * The odd passes will write 0
4211 #define TX_CMPL_PTP_HI_V2 UINT32_C(0x1)
4214 /* rx_pkt_cmpl (size:128b/16B) */
4215 struct rx_pkt_cmpl {
4216 uint16_t flags_type;
4218 * This field indicates the exact type of the completion.
4219 * By convention, the LSB identifies the length of the
4220 * record in 16B units. Even values indicate 16B
4221 * records. Odd values indicate 32B
4224 #define RX_PKT_CMPL_TYPE_MASK UINT32_C(0x3f)
4225 #define RX_PKT_CMPL_TYPE_SFT 0
4228 * Completion of and L2 RX packet. Length = 32B
4230 #define RX_PKT_CMPL_TYPE_RX_L2 UINT32_C(0x11)
4231 #define RX_PKT_CMPL_TYPE_LAST RX_PKT_CMPL_TYPE_RX_L2
4232 #define RX_PKT_CMPL_FLAGS_MASK UINT32_C(0xffc0)
4233 #define RX_PKT_CMPL_FLAGS_SFT 6
4235 * When this bit is '1', it indicates a packet that has an
4236 * error of some type. Type of error is indicated in
4239 #define RX_PKT_CMPL_FLAGS_ERROR UINT32_C(0x40)
4240 /* This field indicates how the packet was placed in the buffer. */
4241 #define RX_PKT_CMPL_FLAGS_PLACEMENT_MASK UINT32_C(0x380)
4242 #define RX_PKT_CMPL_FLAGS_PLACEMENT_SFT 7
4245 * Packet was placed using normal algorithm.
4247 #define RX_PKT_CMPL_FLAGS_PLACEMENT_NORMAL (UINT32_C(0x0) << 7)
4250 * Packet was placed using jumbo algorithm.
4252 #define RX_PKT_CMPL_FLAGS_PLACEMENT_JUMBO (UINT32_C(0x1) << 7)
4254 * Header/Data Separation:
4255 * Packet was placed using Header/Data separation algorithm.
4256 * The separation location is indicated by the itype field.
4258 #define RX_PKT_CMPL_FLAGS_PLACEMENT_HDS (UINT32_C(0x2) << 7)
4259 #define RX_PKT_CMPL_FLAGS_PLACEMENT_LAST \
4260 RX_PKT_CMPL_FLAGS_PLACEMENT_HDS
4261 /* This bit is '1' if the RSS field in this completion is valid. */
4262 #define RX_PKT_CMPL_FLAGS_RSS_VALID UINT32_C(0x400)
4264 #define RX_PKT_CMPL_FLAGS_UNUSED UINT32_C(0x800)
4266 * This value indicates what the inner packet determined for the
4269 #define RX_PKT_CMPL_FLAGS_ITYPE_MASK UINT32_C(0xf000)
4270 #define RX_PKT_CMPL_FLAGS_ITYPE_SFT 12
4273 * Indicates that the packet type was not known.
4275 #define RX_PKT_CMPL_FLAGS_ITYPE_NOT_KNOWN \
4276 (UINT32_C(0x0) << 12)
4279 * Indicates that the packet was an IP packet, but further
4280 * classification was not possible.
4282 #define RX_PKT_CMPL_FLAGS_ITYPE_IP \
4283 (UINT32_C(0x1) << 12)
4286 * Indicates that the packet was IP and TCP.
4287 * This indicates that the payload_offset field is valid.
4289 #define RX_PKT_CMPL_FLAGS_ITYPE_TCP \
4290 (UINT32_C(0x2) << 12)
4293 * Indicates that the packet was IP and UDP.
4294 * This indicates that the payload_offset field is valid.
4296 #define RX_PKT_CMPL_FLAGS_ITYPE_UDP \
4297 (UINT32_C(0x3) << 12)
4300 * Indicates that the packet was recognized as a FCoE.
4301 * This also indicates that the payload_offset field is valid.
4303 #define RX_PKT_CMPL_FLAGS_ITYPE_FCOE \
4304 (UINT32_C(0x4) << 12)
4307 * Indicates that the packet was recognized as a RoCE.
4308 * This also indicates that the payload_offset field is valid.
4310 #define RX_PKT_CMPL_FLAGS_ITYPE_ROCE \
4311 (UINT32_C(0x5) << 12)
4314 * Indicates that the packet was recognized as ICMP.
4315 * This indicates that the payload_offset field is valid.
4317 #define RX_PKT_CMPL_FLAGS_ITYPE_ICMP \
4318 (UINT32_C(0x7) << 12)
4320 * PtP packet wo/timestamp:
4321 * Indicates that the packet was recognized as a PtP
4324 #define RX_PKT_CMPL_FLAGS_ITYPE_PTP_WO_TIMESTAMP \
4325 (UINT32_C(0x8) << 12)
4327 * PtP packet w/timestamp:
4328 * Indicates that the packet was recognized as a PtP
4329 * packet and that a timestamp was taken for the packet.
4331 #define RX_PKT_CMPL_FLAGS_ITYPE_PTP_W_TIMESTAMP \
4332 (UINT32_C(0x9) << 12)
4333 #define RX_PKT_CMPL_FLAGS_ITYPE_LAST \
4334 RX_PKT_CMPL_FLAGS_ITYPE_PTP_W_TIMESTAMP
4336 * This is the length of the data for the packet stored in the
4337 * buffer(s) identified by the opaque value. This includes
4338 * the packet BD and any associated buffer BDs. This does not include
4339 * the length of any data places in aggregation BDs.
4343 * This is a copy of the opaque field from the RX BD this completion
4347 uint8_t agg_bufs_v1;
4349 * This value is written by the NIC such that it will be different
4350 * for each pass through the completion queue. The even passes
4351 * will write 1. The odd passes will write 0.
4353 #define RX_PKT_CMPL_V1 UINT32_C(0x1)
4355 * This value is the number of aggregation buffers that follow this
4356 * entry in the completion ring that are a part of this packet.
4357 * If the value is zero, then the packet is completely contained
4358 * in the buffer space provided for the packet in the RX ring.
4360 #define RX_PKT_CMPL_AGG_BUFS_MASK UINT32_C(0x3e)
4361 #define RX_PKT_CMPL_AGG_BUFS_SFT 1
4362 /* unused1 is 2 b */
4363 #define RX_PKT_CMPL_UNUSED1_MASK UINT32_C(0xc0)
4364 #define RX_PKT_CMPL_UNUSED1_SFT 6
4366 * This is the RSS hash type for the packet. The value is packed
4367 * {tuple_extrac_op[1:0],rss_profile_id[4:0],tuple_extrac_op[2]}.
4369 * The value of tuple_extrac_op provides the information about
4370 * what fields the hash was computed on.
4371 * * 0: The RSS hash was computed over source IP address,
4372 * destination IP address, source port, and destination port of inner
4373 * IP and TCP or UDP headers. Note: For non-tunneled packets,
4374 * the packet headers are considered inner packet headers for the RSS
4375 * hash computation purpose.
4376 * * 1: The RSS hash was computed over source IP address and destination
4377 * IP address of inner IP header. Note: For non-tunneled packets,
4378 * the packet headers are considered inner packet headers for the RSS
4379 * hash computation purpose.
4380 * * 2: The RSS hash was computed over source IP address,
4381 * destination IP address, source port, and destination port of
4382 * IP and TCP or UDP headers of outer tunnel headers.
4383 * Note: For non-tunneled packets, this value is not applicable.
4384 * * 3: The RSS hash was computed over source IP address and
4385 * destination IP address of IP header of outer tunnel headers.
4386 * Note: For non-tunneled packets, this value is not applicable.
4388 * Note that 4-tuples values listed above are applicable
4389 * for layer 4 protocols supported and enabled for RSS in the hardware,
4390 * HWRM firmware, and drivers. For example, if RSS hash is supported and
4391 * enabled for TCP traffic only, then the values of tuple_extract_op
4392 * corresponding to 4-tuples are only valid for TCP traffic.
4394 uint8_t rss_hash_type;
4396 * This value indicates the offset in bytes from the beginning of the packet
4397 * where the inner payload starts. This value is valid for TCP, UDP,
4398 * FCoE, and RoCE packets.
4400 * A value of zero indicates that header is 256B into the packet.
4402 uint8_t payload_offset;
4403 /* unused2 is 8 b */
4406 * This value is the RSS hash value calculated for the packet
4407 * based on the mode bits and key value in the VNIC.
4412 /* Last 16 bytes of rx_pkt_cmpl. */
4413 /* rx_pkt_cmpl_hi (size:128b/16B) */
4414 struct rx_pkt_cmpl_hi {
4417 * This indicates that the ip checksum was calculated for the
4418 * inner packet and that the ip_cs_error field indicates if there
4421 #define RX_PKT_CMPL_FLAGS2_IP_CS_CALC UINT32_C(0x1)
4423 * This indicates that the TCP, UDP or ICMP checksum was
4424 * calculated for the inner packet and that the l4_cs_error field
4425 * indicates if there was an error.
4427 #define RX_PKT_CMPL_FLAGS2_L4_CS_CALC UINT32_C(0x2)
4429 * This indicates that the ip checksum was calculated for the
4430 * tunnel header and that the t_ip_cs_error field indicates if there
4433 #define RX_PKT_CMPL_FLAGS2_T_IP_CS_CALC UINT32_C(0x4)
4435 * This indicates that the UDP checksum was
4436 * calculated for the tunnel packet and that the t_l4_cs_error field
4437 * indicates if there was an error.
4439 #define RX_PKT_CMPL_FLAGS2_T_L4_CS_CALC UINT32_C(0x8)
4440 /* This value indicates what format the metadata field is. */
4441 #define RX_PKT_CMPL_FLAGS2_META_FORMAT_MASK UINT32_C(0xf0)
4442 #define RX_PKT_CMPL_FLAGS2_META_FORMAT_SFT 4
4443 /* No metadata information. Value is zero. */
4444 #define RX_PKT_CMPL_FLAGS2_META_FORMAT_NONE \
4445 (UINT32_C(0x0) << 4)
4447 * The metadata field contains the VLAN tag and TPID value.
4448 * - metadata[11:0] contains the vlan VID value.
4449 * - metadata[12] contains the vlan DE value.
4450 * - metadata[15:13] contains the vlan PRI value.
4451 * - metadata[31:16] contains the vlan TPID value.
4453 #define RX_PKT_CMPL_FLAGS2_META_FORMAT_VLAN \
4454 (UINT32_C(0x1) << 4)
4456 * If ext_meta_format is equal to 1, the metadata field
4457 * contains the lower 16b of the tunnel ID value, justified
4459 * - VXLAN = VNI[23:0] -> VXLAN Network ID
4460 * - Geneve (NGE) = VNI[23:0] a-> Virtual Network Identifier.
4461 * - NVGRE = TNI[23:0] -> Tenant Network ID
4462 * - GRE = KEY[31:0] -> key field with bit mask. zero if K = 0
4463 * - IPV4 = 0 (not populated)
4464 * - IPV6 = Flow Label[19:0]
4465 * - PPPoE = sessionID[15:0]
4466 * - MPLs = Outer label[19:0]
4467 * - UPAR = Selected[31:0] with bit mask
4469 #define RX_PKT_CMPL_FLAGS2_META_FORMAT_TUNNEL_ID \
4470 (UINT32_C(0x2) << 4)
4472 * if ext_meta_format is equal to 1, metadata field contains
4473 * 16b metadata from the prepended header (chdr_data).
4475 #define RX_PKT_CMPL_FLAGS2_META_FORMAT_CHDR_DATA \
4476 (UINT32_C(0x3) << 4)
4478 * If ext_meta_format is equal to 1, the metadata field contains
4479 * the outer_l3_offset, inner_l2_offset, inner_l3_offset and
4481 * - metadata[8:0] contains the outer_l3_offset.
4482 * - metadata[17:9] contains the inner_l2_offset.
4483 * - metadata[26:18] contains the inner_l3_offset.
4484 * - metadata[31:27] contains the inner_l4_size.
4486 #define RX_PKT_CMPL_FLAGS2_META_FORMAT_HDR_OFFSET \
4487 (UINT32_C(0x4) << 4)
4488 #define RX_PKT_CMPL_FLAGS2_META_FORMAT_LAST \
4489 RX_PKT_CMPL_FLAGS2_META_FORMAT_HDR_OFFSET
4491 * This field indicates the IP type for the inner-most IP header.
4492 * A value of '0' indicates IPv4. A value of '1' indicates IPv6.
4493 * This value is only valid if itype indicates a packet
4494 * with an IP header.
4496 #define RX_PKT_CMPL_FLAGS2_IP_TYPE UINT32_C(0x100)
4498 * This indicates that the complete 1's complement checksum was
4499 * calculated for the packet.
4501 #define RX_PKT_CMPL_FLAGS2_COMPLETE_CHECKSUM_CALC UINT32_C(0x200)
4503 * The combination of this value and meta_format indicated what
4504 * format the metadata field is.
4506 #define RX_PKT_CMPL_FLAGS2_EXT_META_FORMAT_MASK UINT32_C(0xc00)
4507 #define RX_PKT_CMPL_FLAGS2_EXT_META_FORMAT_SFT 10
4509 * This value is the complete 1's complement checksum calculated from
4510 * the start of the outer L3 header to the end of the packet (not
4511 * including the ethernet crc). It is valid when the
4512 * 'complete_checksum_calc' flag is set.
4514 #define RX_PKT_CMPL_FLAGS2_COMPLETE_CHECKSUM_MASK \
4515 UINT32_C(0xffff0000)
4516 #define RX_PKT_CMPL_FLAGS2_COMPLETE_CHECKSUM_SFT 16
4518 * This is data from the CFA block as indicated by the meta_format
4522 /* When meta_format=1, this value is the VLAN VID. */
4523 #define RX_PKT_CMPL_METADATA_VID_MASK UINT32_C(0xfff)
4524 #define RX_PKT_CMPL_METADATA_VID_SFT 0
4525 /* When meta_format=1, this value is the VLAN DE. */
4526 #define RX_PKT_CMPL_METADATA_DE UINT32_C(0x1000)
4527 /* When meta_format=1, this value is the VLAN PRI. */
4528 #define RX_PKT_CMPL_METADATA_PRI_MASK UINT32_C(0xe000)
4529 #define RX_PKT_CMPL_METADATA_PRI_SFT 13
4530 /* When meta_format=1, this value is the VLAN TPID. */
4531 #define RX_PKT_CMPL_METADATA_TPID_MASK UINT32_C(0xffff0000)
4532 #define RX_PKT_CMPL_METADATA_TPID_SFT 16
4535 * This value is written by the NIC such that it will be different
4536 * for each pass through the completion queue. The even passes
4537 * will write 1. The odd passes will write 0.
4539 #define RX_PKT_CMPL_V2 \
4541 #define RX_PKT_CMPL_ERRORS_MASK \
4543 #define RX_PKT_CMPL_ERRORS_SFT 1
4545 * This error indicates that there was some sort of problem with
4546 * the BDs for the packet that was found after part of the
4547 * packet was already placed. The packet should be treated as
4550 #define RX_PKT_CMPL_ERRORS_BUFFER_ERROR_MASK \
4552 #define RX_PKT_CMPL_ERRORS_BUFFER_ERROR_SFT 1
4553 /* No buffer error */
4554 #define RX_PKT_CMPL_ERRORS_BUFFER_ERROR_NO_BUFFER \
4555 (UINT32_C(0x0) << 1)
4558 * Packet did not fit into packet buffer provided.
4559 * For regular placement, this means the packet did not fit
4560 * in the buffer provided. For HDS and jumbo placement, this
4561 * means that the packet could not be placed into 7 physical
4564 #define RX_PKT_CMPL_ERRORS_BUFFER_ERROR_DID_NOT_FIT \
4565 (UINT32_C(0x1) << 1)
4568 * All BDs needed for the packet were not on-chip when
4569 * the packet arrived.
4571 #define RX_PKT_CMPL_ERRORS_BUFFER_ERROR_NOT_ON_CHIP \
4572 (UINT32_C(0x2) << 1)
4575 * BDs were not formatted correctly.
4577 #define RX_PKT_CMPL_ERRORS_BUFFER_ERROR_BAD_FORMAT \
4578 (UINT32_C(0x3) << 1)
4581 * There was a bad_format error on the previous operation
4583 #define RX_PKT_CMPL_ERRORS_BUFFER_ERROR_FLUSH \
4584 (UINT32_C(0x5) << 1)
4585 #define RX_PKT_CMPL_ERRORS_BUFFER_ERROR_LAST \
4586 RX_PKT_CMPL_ERRORS_BUFFER_ERROR_FLUSH
4588 * This indicates that there was an error in the IP header
4591 #define RX_PKT_CMPL_ERRORS_IP_CS_ERROR \
4594 * This indicates that there was an error in the TCP, UDP
4597 #define RX_PKT_CMPL_ERRORS_L4_CS_ERROR \
4600 * This indicates that there was an error in the tunnel
4601 * IP header checksum.
4603 #define RX_PKT_CMPL_ERRORS_T_IP_CS_ERROR \
4606 * This indicates that there was an error in the tunnel
4609 #define RX_PKT_CMPL_ERRORS_T_L4_CS_ERROR \
4612 * This indicates that there was a CRC error on either an FCoE
4613 * or RoCE packet. The itype indicates the packet type.
4615 #define RX_PKT_CMPL_ERRORS_CRC_ERROR \
4618 * This indicates that there was an error in the tunnel
4619 * portion of the packet when this
4620 * field is non-zero.
4622 #define RX_PKT_CMPL_ERRORS_T_PKT_ERROR_MASK \
4624 #define RX_PKT_CMPL_ERRORS_T_PKT_ERROR_SFT 9
4626 * No additional error occurred on the tunnel portion
4627 * or the packet of the packet does not have a tunnel.
4629 #define RX_PKT_CMPL_ERRORS_T_PKT_ERROR_NO_ERROR \
4630 (UINT32_C(0x0) << 9)
4632 * Indicates that IP header version does not match
4633 * expectation from L2 Ethertype for IPv4 and IPv6
4634 * in the tunnel header.
4636 #define RX_PKT_CMPL_ERRORS_T_PKT_ERROR_T_L3_BAD_VERSION \
4637 (UINT32_C(0x1) << 9)
4639 * Indicates that header length is out of range in the
4640 * tunnel header. Valid for
4643 #define RX_PKT_CMPL_ERRORS_T_PKT_ERROR_T_L3_BAD_HDR_LEN \
4644 (UINT32_C(0x2) << 9)
4646 * Indicates that the physical packet is shorter than that
4647 * claimed by the PPPoE header length for a tunnel PPPoE
4650 #define RX_PKT_CMPL_ERRORS_T_PKT_ERROR_TUNNEL_TOTAL_ERROR \
4651 (UINT32_C(0x3) << 9)
4653 * Indicates that physical packet is shorter than that claimed
4654 * by the tunnel l3 header length. Valid for IPv4, or IPv6
4655 * tunnel packet packets.
4657 #define RX_PKT_CMPL_ERRORS_T_PKT_ERROR_T_IP_TOTAL_ERROR \
4658 (UINT32_C(0x4) << 9)
4660 * Indicates that the physical packet is shorter than that
4661 * claimed by the tunnel UDP header length for a tunnel
4662 * UDP packet that is not fragmented.
4664 #define RX_PKT_CMPL_ERRORS_T_PKT_ERROR_T_UDP_TOTAL_ERROR \
4665 (UINT32_C(0x5) << 9)
4667 * indicates that the IPv4 TTL or IPv6 hop limit check
4668 * have failed (e.g. TTL = 0) in the tunnel header. Valid
4669 * for IPv4, and IPv6.
4671 #define RX_PKT_CMPL_ERRORS_T_PKT_ERROR_T_L3_BAD_TTL \
4672 (UINT32_C(0x6) << 9)
4673 #define RX_PKT_CMPL_ERRORS_T_PKT_ERROR_LAST \
4674 RX_PKT_CMPL_ERRORS_T_PKT_ERROR_T_L3_BAD_TTL
4676 * This indicates that there was an error in the inner
4677 * portion of the packet when this
4678 * field is non-zero.
4680 #define RX_PKT_CMPL_ERRORS_PKT_ERROR_MASK \
4682 #define RX_PKT_CMPL_ERRORS_PKT_ERROR_SFT 12
4684 * No additional error occurred on the tunnel portion
4685 * or the packet of the packet does not have a tunnel.
4687 #define RX_PKT_CMPL_ERRORS_PKT_ERROR_NO_ERROR \
4688 (UINT32_C(0x0) << 12)
4690 * Indicates that IP header version does not match
4691 * expectation from L2 Ethertype for IPv4 and IPv6 or that
4692 * option other than VFT was parsed on
4695 #define RX_PKT_CMPL_ERRORS_PKT_ERROR_L3_BAD_VERSION \
4696 (UINT32_C(0x1) << 12)
4698 * indicates that header length is out of range. Valid for
4701 #define RX_PKT_CMPL_ERRORS_PKT_ERROR_L3_BAD_HDR_LEN \
4702 (UINT32_C(0x2) << 12)
4704 * indicates that the IPv4 TTL or IPv6 hop limit check
4705 * have failed (e.g. TTL = 0). Valid for IPv4, and IPv6
4707 #define RX_PKT_CMPL_ERRORS_PKT_ERROR_L3_BAD_TTL \
4708 (UINT32_C(0x3) << 12)
4710 * Indicates that physical packet is shorter than that
4711 * claimed by the l3 header length. Valid for IPv4,
4712 * IPv6 packet or RoCE packets.
4714 #define RX_PKT_CMPL_ERRORS_PKT_ERROR_IP_TOTAL_ERROR \
4715 (UINT32_C(0x4) << 12)
4717 * Indicates that the physical packet is shorter than that
4718 * claimed by the UDP header length for a UDP packet that is
4721 #define RX_PKT_CMPL_ERRORS_PKT_ERROR_UDP_TOTAL_ERROR \
4722 (UINT32_C(0x5) << 12)
4724 * Indicates that TCP header length > IP payload. Valid for
4727 #define RX_PKT_CMPL_ERRORS_PKT_ERROR_L4_BAD_HDR_LEN \
4728 (UINT32_C(0x6) << 12)
4729 /* Indicates that TCP header length < 5. Valid for TCP. */
4730 #define RX_PKT_CMPL_ERRORS_PKT_ERROR_L4_BAD_HDR_LEN_TOO_SMALL \
4731 (UINT32_C(0x7) << 12)
4733 * Indicates that TCP option headers result in a TCP header
4734 * size that does not match data offset in TCP header. Valid
4737 #define RX_PKT_CMPL_ERRORS_PKT_ERROR_L4_BAD_OPT_LEN \
4738 (UINT32_C(0x8) << 12)
4739 #define RX_PKT_CMPL_ERRORS_PKT_ERROR_LAST \
4740 RX_PKT_CMPL_ERRORS_PKT_ERROR_L4_BAD_OPT_LEN
4742 * This field identifies the CFA action rule that was used for this
4748 * This value holds the reordering sequence number for the packet.
4749 * If the reordering sequence is not valid, then this value is zero.
4750 * The reordering domain for the packet is in the bottom 8 to 10b of
4751 * the rss_hash value. The bottom 20b of this value contain the
4752 * ordering domain value for the packet.
4754 #define RX_PKT_CMPL_REORDER_MASK UINT32_C(0xffffff)
4755 #define RX_PKT_CMPL_REORDER_SFT 0
4758 /* rx_pkt_v2_cmpl (size:128b/16B) */
4759 struct rx_pkt_v2_cmpl {
4760 uint16_t flags_type;
4762 * This field indicates the exact type of the completion.
4763 * By convention, the LSB identifies the length of the
4764 * record in 16B units. Even values indicate 16B
4765 * records. Odd values indicate 32B
4768 #define RX_PKT_V2_CMPL_TYPE_MASK UINT32_C(0x3f)
4769 #define RX_PKT_V2_CMPL_TYPE_SFT 0
4771 * RX L2 V2 completion:
4772 * Completion of and L2 RX packet. Length = 32B
4773 * This is the new version of the RX_L2 completion used in SR2
4776 #define RX_PKT_V2_CMPL_TYPE_RX_L2_V2 UINT32_C(0xf)
4777 #define RX_PKT_V2_CMPL_TYPE_LAST \
4778 RX_PKT_V2_CMPL_TYPE_RX_L2_V2
4779 #define RX_PKT_V2_CMPL_FLAGS_MASK UINT32_C(0xffc0)
4780 #define RX_PKT_V2_CMPL_FLAGS_SFT 6
4782 * When this bit is '1', it indicates a packet that has an
4783 * error of some type. Type of error is indicated in
4786 #define RX_PKT_V2_CMPL_FLAGS_ERROR UINT32_C(0x40)
4787 /* This field indicates how the packet was placed in the buffer. */
4788 #define RX_PKT_V2_CMPL_FLAGS_PLACEMENT_MASK UINT32_C(0x380)
4789 #define RX_PKT_V2_CMPL_FLAGS_PLACEMENT_SFT 7
4792 * Packet was placed using normal algorithm.
4794 #define RX_PKT_V2_CMPL_FLAGS_PLACEMENT_NORMAL \
4795 (UINT32_C(0x0) << 7)
4798 * Packet was placed using jumbo algorithm.
4800 #define RX_PKT_V2_CMPL_FLAGS_PLACEMENT_JUMBO \
4801 (UINT32_C(0x1) << 7)
4803 * Header/Data Separation:
4804 * Packet was placed using Header/Data separation algorithm.
4805 * The separation location is indicated by the itype field.
4807 #define RX_PKT_V2_CMPL_FLAGS_PLACEMENT_HDS \
4808 (UINT32_C(0x2) << 7)
4811 * Packet was placed using truncation algorithm. The
4812 * placed (truncated) length is indicated in the payload_offset
4813 * field. The original length is indicated in the len field.
4815 #define RX_PKT_V2_CMPL_FLAGS_PLACEMENT_TRUNCATION \
4816 (UINT32_C(0x3) << 7)
4817 #define RX_PKT_V2_CMPL_FLAGS_PLACEMENT_LAST \
4818 RX_PKT_V2_CMPL_FLAGS_PLACEMENT_TRUNCATION
4819 /* This bit is '1' if the RSS field in this completion is valid. */
4820 #define RX_PKT_V2_CMPL_FLAGS_RSS_VALID UINT32_C(0x400)
4822 * This bit is '1' if metadata has been added to the end of the
4823 * packet in host memory. Metadata starts at the first 32B boundary
4824 * after the end of the packet for regular and jumbo placement.
4825 * It starts at the first 32B boundary after the end of the header
4826 * for HDS placement. The length of the metadata is indicated in the
4829 #define RX_PKT_V2_CMPL_FLAGS_PKT_METADATA_PRESENT UINT32_C(0x800)
4831 * This value indicates what the inner packet determined for the
4834 #define RX_PKT_V2_CMPL_FLAGS_ITYPE_MASK UINT32_C(0xf000)
4835 #define RX_PKT_V2_CMPL_FLAGS_ITYPE_SFT 12
4838 * Indicates that the packet type was not known.
4840 #define RX_PKT_V2_CMPL_FLAGS_ITYPE_NOT_KNOWN \
4841 (UINT32_C(0x0) << 12)
4844 * Indicates that the packet was an IP packet, but further
4845 * classification was not possible.
4847 #define RX_PKT_V2_CMPL_FLAGS_ITYPE_IP \
4848 (UINT32_C(0x1) << 12)
4851 * Indicates that the packet was IP and TCP.
4852 * This indicates that the payload_offset field is valid.
4854 #define RX_PKT_V2_CMPL_FLAGS_ITYPE_TCP \
4855 (UINT32_C(0x2) << 12)
4858 * Indicates that the packet was IP and UDP.
4859 * This indicates that the payload_offset field is valid.
4861 #define RX_PKT_V2_CMPL_FLAGS_ITYPE_UDP \
4862 (UINT32_C(0x3) << 12)
4865 * Indicates that the packet was recognized as a FCoE.
4866 * This also indicates that the payload_offset field is valid.
4868 #define RX_PKT_V2_CMPL_FLAGS_ITYPE_FCOE \
4869 (UINT32_C(0x4) << 12)
4872 * Indicates that the packet was recognized as a RoCE.
4873 * This also indicates that the payload_offset field is valid.
4875 #define RX_PKT_V2_CMPL_FLAGS_ITYPE_ROCE \
4876 (UINT32_C(0x5) << 12)
4879 * Indicates that the packet was recognized as ICMP.
4880 * This indicates that the payload_offset field is valid.
4882 #define RX_PKT_V2_CMPL_FLAGS_ITYPE_ICMP \
4883 (UINT32_C(0x7) << 12)
4885 * PtP packet wo/timestamp:
4886 * Indicates that the packet was recognized as a PtP
4889 #define RX_PKT_V2_CMPL_FLAGS_ITYPE_PTP_WO_TIMESTAMP \
4890 (UINT32_C(0x8) << 12)
4892 * PtP packet w/timestamp:
4893 * Indicates that the packet was recognized as a PtP
4894 * packet and that a timestamp was taken for the packet.
4896 #define RX_PKT_V2_CMPL_FLAGS_ITYPE_PTP_W_TIMESTAMP \
4897 (UINT32_C(0x9) << 12)
4898 #define RX_PKT_V2_CMPL_FLAGS_ITYPE_LAST \
4899 RX_PKT_V2_CMPL_FLAGS_ITYPE_PTP_W_TIMESTAMP
4901 * This is the length of the data for the packet stored in the
4902 * buffer(s) identified by the opaque value. This includes
4903 * the packet BD and any associated buffer BDs. This does not include
4904 * the length of any data places in aggregation BDs.
4908 * This is a copy of the opaque field from the RX BD this completion
4912 uint8_t agg_bufs_v1;
4914 * This value is written by the NIC such that it will be different
4915 * for each pass through the completion queue. The even passes
4916 * will write 1. The odd passes will write 0.
4918 #define RX_PKT_V2_CMPL_V1 UINT32_C(0x1)
4920 * This value is the number of aggregation buffers that follow this
4921 * entry in the completion ring that are a part of this packet.
4922 * If the value is zero, then the packet is completely contained
4923 * in the buffer space provided for the packet in the RX ring.
4925 #define RX_PKT_V2_CMPL_AGG_BUFS_MASK UINT32_C(0x3e)
4926 #define RX_PKT_V2_CMPL_AGG_BUFS_SFT 1
4927 /* unused1 is 2 b */
4928 #define RX_PKT_V2_CMPL_UNUSED1_MASK UINT32_C(0xc0)
4929 #define RX_PKT_V2_CMPL_UNUSED1_SFT 6
4931 * This is the RSS hash type for the packet. The value is packed
4932 * {tuple_extrac_op[1:0],rss_profile_id[4:0],tuple_extrac_op[2]}.
4934 * The value of tuple_extrac_op provides the information about
4935 * what fields the hash was computed on.
4936 * * 0: The RSS hash was computed over source IP address,
4937 * destination IP address, source port, and destination port of inner
4938 * IP and TCP or UDP headers. Note: For non-tunneled packets,
4939 * the packet headers are considered inner packet headers for the RSS
4940 * hash computation purpose.
4941 * * 1: The RSS hash was computed over source IP address and destination
4942 * IP address of inner IP header. Note: For non-tunneled packets,
4943 * the packet headers are considered inner packet headers for the RSS
4944 * hash computation purpose.
4945 * * 2: The RSS hash was computed over source IP address,
4946 * destination IP address, source port, and destination port of
4947 * IP and TCP or UDP headers of outer tunnel headers.
4948 * Note: For non-tunneled packets, this value is not applicable.
4949 * * 3: The RSS hash was computed over source IP address and
4950 * destination IP address of IP header of outer tunnel headers.
4951 * Note: For non-tunneled packets, this value is not applicable.
4953 * Note that 4-tuples values listed above are applicable
4954 * for layer 4 protocols supported and enabled for RSS in the hardware,
4955 * HWRM firmware, and drivers. For example, if RSS hash is supported and
4956 * enabled for TCP traffic only, then the values of tuple_extract_op
4957 * corresponding to 4-tuples are only valid for TCP traffic.
4959 uint8_t rss_hash_type;
4960 uint16_t metadata1_payload_offset;
4962 * This is data from the CFA as indicated by the meta_format field.
4963 * If truncation placement is not used, this value indicates the offset
4964 * in bytes from the beginning of the packet where the inner payload
4965 * starts. This value is valid for TCP, UDP, FCoE, and RoCE packets. If
4966 * truncation placement is used, this value represents the placed
4967 * (truncated) length of the packet.
4969 #define RX_PKT_V2_CMPL_PAYLOAD_OFFSET_MASK UINT32_C(0x1ff)
4970 #define RX_PKT_V2_CMPL_PAYLOAD_OFFSET_SFT 0
4971 /* This is data from the CFA as indicated by the meta_format field. */
4972 #define RX_PKT_V2_CMPL_METADATA1_MASK UINT32_C(0xf000)
4973 #define RX_PKT_V2_CMPL_METADATA1_SFT 12
4974 /* When meta_format != 0, this value is the VLAN TPID_SEL. */
4975 #define RX_PKT_V2_CMPL_METADATA1_TPID_SEL_MASK UINT32_C(0x7000)
4976 #define RX_PKT_V2_CMPL_METADATA1_TPID_SEL_SFT 12
4978 #define RX_PKT_V2_CMPL_METADATA1_TPID_SEL_TPID88A8 \
4979 (UINT32_C(0x0) << 12)
4981 #define RX_PKT_V2_CMPL_METADATA1_TPID_SEL_TPID8100 \
4982 (UINT32_C(0x1) << 12)
4984 #define RX_PKT_V2_CMPL_METADATA1_TPID_SEL_TPID9100 \
4985 (UINT32_C(0x2) << 12)
4987 #define RX_PKT_V2_CMPL_METADATA1_TPID_SEL_TPID9200 \
4988 (UINT32_C(0x3) << 12)
4990 #define RX_PKT_V2_CMPL_METADATA1_TPID_SEL_TPID9300 \
4991 (UINT32_C(0x4) << 12)
4992 /* Value programmed in CFA VLANTPID register. */
4993 #define RX_PKT_V2_CMPL_METADATA1_TPID_SEL_TPIDCFG \
4994 (UINT32_C(0x5) << 12)
4995 #define RX_PKT_V2_CMPL_METADATA1_TPID_SEL_LAST \
4996 RX_PKT_V2_CMPL_METADATA1_TPID_SEL_TPIDCFG
4997 /* When meta_format != 0, this value is the VLAN valid. */
4998 #define RX_PKT_V2_CMPL_METADATA1_VALID UINT32_C(0x8000)
5000 * This value is the RSS hash value calculated for the packet
5001 * based on the mode bits and key value in the VNIC. When vee_cmpl_mode
5002 * is set in VNIC context, this is the lower 32b of the host address
5003 * from the first BD used to place the packet.
5008 /* Last 16 bytes of RX Packet V2 Completion Record */
5009 /* rx_pkt_v2_cmpl_hi (size:128b/16B) */
5010 struct rx_pkt_v2_cmpl_hi {
5013 * When this bit is '0', the cs_ok field has the following definition:-
5014 * ip_cs_ok[2:0] = The number of header groups with a valid IP checksum
5015 * in the delivered packet, counted from the outer-most header group to
5016 * the inner-most header group, stopping at the first error. -
5017 * l4_cs_ok[5:3] = The number of header groups with a valid L4 checksum
5018 * in the delivered packet, counted from the outer-most header group to
5019 * the inner-most header group, stopping at the first error. When this
5020 * bit is '1', the cs_ok field has the following definition: -
5021 * hdr_cnt[2:0] = The number of header groups that were parsed by the
5022 * chip and passed in the delivered packet. - ip_cs_all_ok[3] =This bit
5023 * will be '1' if all the parsed header groups with an IP checksum are
5024 * valid. - l4_cs_all_ok[4] = This bit will be '1' if all the parsed
5025 * header groups with an L4 checksum are valid.
5027 #define RX_PKT_V2_CMPL_HI_FLAGS2_CS_ALL_OK_MODE \
5029 /* This value indicates what format the metadata field is. */
5030 #define RX_PKT_V2_CMPL_HI_FLAGS2_META_FORMAT_MASK \
5032 #define RX_PKT_V2_CMPL_HI_FLAGS2_META_FORMAT_SFT 4
5033 /* There is no metadata information. Values are zero. */
5034 #define RX_PKT_V2_CMPL_HI_FLAGS2_META_FORMAT_NONE \
5035 (UINT32_C(0x0) << 4)
5037 * The {metadata1, metadata0} fields contain the vtag
5038 * information: - vtag[19:0] = {valid, tpid_sel[2:0], pri[2:0],
5039 * de, vid[11:0]} The metadata2 field contains the table scope
5040 * and action record pointer. - metadata2[25:0] contains the
5041 * action record pointer. - metadata2[31:26] contains the table
5044 #define RX_PKT_V2_CMPL_HI_FLAGS2_META_FORMAT_ACT_REC_PTR \
5045 (UINT32_C(0x1) << 4)
5047 * The {metadata1, metadata0} fields contain the vtag
5049 * - vtag[19:0] = {valid, tpid_sel[2:0], pri[2:0], de, vid[11:0]}
5050 * The metadata2 field contains the Tunnel ID
5051 * value, justified to LSB. i
5052 * - VXLAN = VNI[23:0] -> VXLAN Network ID
5053 * - Geneve (NGE) = VNI[23:0] a-> Virtual Network Identifier
5054 * - NVGRE = TNI[23:0] -> Tenant Network ID
5055 * - GRE = KEY[31:0] -> key field with bit mask. zero if K=0
5056 * - IPv4 = 0 (not populated)
5057 * - IPv6 = Flow Label[19:0]
5058 * - PPPoE = sessionID[15:0]
5059 * - MPLs = Outer label[19:0]
5060 * - UPAR = Selected[31:0] with bit mask
5062 #define RX_PKT_V2_CMPL_HI_FLAGS2_META_FORMAT_TUNNEL_ID \
5063 (UINT32_C(0x2) << 4)
5065 * The {metadata1, metadata0} fields contain the vtag
5067 * - vtag[19:0] = {valid, tpid_sel[2:0], pri[2:0],de, vid[11:0]}
5068 * The metadata2 field contains the 32b metadata from the prepended
5069 * header (chdr_data).
5071 #define RX_PKT_V2_CMPL_HI_FLAGS2_META_FORMAT_CHDR_DATA \
5072 (UINT32_C(0x3) << 4)
5074 * The {metadata1, metadata0} fields contain the vtag
5076 * - vtag[19:0] = {valid, tpid_sel[2:0], pri[2:0], de, vid[11:0]}
5077 * The metadata2 field contains the outer_l3_offset,
5078 * inner_l2_offset, inner_l3_offset, and inner_l4_size.
5079 * - metadata2[8:0] contains the outer_l3_offset.
5080 * - metadata2[17:9] contains the inner_l2_offset.
5081 * - metadata2[26:18] contains the inner_l3_offset.
5082 * - metadata2[31:27] contains the inner_l4_size.
5084 #define RX_PKT_V2_CMPL_HI_FLAGS2_META_FORMAT_HDR_OFFSET \
5085 (UINT32_C(0x4) << 4)
5086 #define RX_PKT_V2_CMPL_HI_FLAGS2_META_FORMAT_LAST \
5087 RX_PKT_V2_CMPL_HI_FLAGS2_META_FORMAT_HDR_OFFSET
5089 * This field indicates the IP type for the inner-most IP header.
5090 * A value of '0' indicates IPv4. A value of '1' indicates IPv6.
5091 * This value is only valid if itype indicates a packet
5092 * with an IP header.
5094 #define RX_PKT_V2_CMPL_HI_FLAGS2_IP_TYPE \
5097 * This indicates that the complete 1's complement checksum was
5098 * calculated for the packet.
5100 #define RX_PKT_V2_CMPL_HI_FLAGS2_COMPLETE_CHECKSUM_CALC \
5103 * This field indicates the status of IP and L4 CS calculations done
5104 * by the chip. The format of this field is indicated by the
5105 * cs_all_ok_mode bit.
5107 #define RX_PKT_V2_CMPL_HI_FLAGS2_CS_OK_MASK \
5109 #define RX_PKT_V2_CMPL_HI_FLAGS2_CS_OK_SFT 10
5111 * This value is the complete 1's complement checksum calculated from
5112 * the start of the outer L3 header to the end of the packet (not
5113 * including the ethernet crc). It is valid when the
5114 * 'complete_checksum_calc' flag is set.
5116 #define RX_PKT_V2_CMPL_HI_FLAGS2_COMPLETE_CHECKSUM_MASK \
5117 UINT32_C(0xffff0000)
5118 #define RX_PKT_V2_CMPL_HI_FLAGS2_COMPLETE_CHECKSUM_SFT 16
5120 * This is data from the CFA block as indicated by the meta_format
5122 * - meta_format 0 - none - metadata2 = 0 - not valid/not stripped
5123 * - meta_format 1 - act_rec_ptr - metadata2 = {table_scope[5:0],
5124 * act_rec_ptr[25:0]}
5125 * - meta_format 2 - tunnel_id - metadata2 = tunnel_id[31:0]
5126 * - meta_format 3 - chdr_data - metadata2 = updated_chdr_data[31:0]
5127 * - meta_format 4 - hdr_offsets - metadata2 = hdr_offsets[31:0]
5128 * When vee_cmpl_mode is set in VNIC context, this is the upper 32b
5129 * of the host address from the first BD used to place the packet.
5134 * This value is written by the NIC such that it will be different
5135 * for each pass through the completion queue. The even passes
5136 * will write 1. The odd passes will write 0.
5138 #define RX_PKT_V2_CMPL_HI_V2 \
5140 #define RX_PKT_V2_CMPL_HI_ERRORS_MASK \
5142 #define RX_PKT_V2_CMPL_HI_ERRORS_SFT 1
5144 * This error indicates that there was some sort of problem with
5145 * the BDs for the packet that was found after part of the
5146 * packet was already placed. The packet should be treated as
5149 #define RX_PKT_V2_CMPL_HI_ERRORS_BUFFER_ERROR_MASK \
5151 #define RX_PKT_V2_CMPL_HI_ERRORS_BUFFER_ERROR_SFT 1
5152 /* No buffer error */
5153 #define RX_PKT_V2_CMPL_HI_ERRORS_BUFFER_ERROR_NO_BUFFER \
5154 (UINT32_C(0x0) << 1)
5156 * Did Not Fit: Packet did not fit into packet buffer provided.
5157 * For regular placement, this means the packet did not fit in
5158 * the buffer provided. For HDS and jumbo placement, this means
5159 * that the packet could not be placed into 8 physical buffers
5160 * (if fixed-size buffers are used), or that the packet could
5161 * not be placed in the number of physical buffers configured
5162 * for the VNIC (if variable-size buffers are used)
5164 #define RX_PKT_V2_CMPL_HI_ERRORS_BUFFER_ERROR_DID_NOT_FIT \
5165 (UINT32_C(0x1) << 1)
5167 * Not On Chip: All BDs needed for the packet were not on-chip
5168 * when the packet arrived. For regular placement, this error is
5169 * not valid. For HDS and jumbo placement, this means that not
5170 * enough agg BDs were posted to place the packet.
5172 #define RX_PKT_V2_CMPL_HI_ERRORS_BUFFER_ERROR_NOT_ON_CHIP \
5173 (UINT32_C(0x2) << 1)
5176 * BDs were not formatted correctly.
5178 #define RX_PKT_V2_CMPL_HI_ERRORS_BUFFER_ERROR_BAD_FORMAT \
5179 (UINT32_C(0x3) << 1)
5182 * There was a bad_format error on the previous operation
5184 #define RX_PKT_V2_CMPL_HI_ERRORS_BUFFER_ERROR_FLUSH \
5185 (UINT32_C(0x5) << 1)
5186 #define RX_PKT_V2_CMPL_HI_ERRORS_BUFFER_ERROR_LAST \
5187 RX_PKT_V2_CMPL_HI_ERRORS_BUFFER_ERROR_FLUSH
5189 * This indicates that there was an error in the outer tunnel
5190 * portion of the packet when this field is non-zero.
5192 #define RX_PKT_V2_CMPL_HI_ERRORS_OT_PKT_ERROR_MASK \
5194 #define RX_PKT_V2_CMPL_HI_ERRORS_OT_PKT_ERROR_SFT 4
5196 * No additional error occurred on the outer tunnel portion
5197 * of the packet or the packet does not have a outer tunnel.
5199 #define RX_PKT_V2_CMPL_HI_ERRORS_OT_PKT_ERROR_NO_ERROR \
5200 (UINT32_C(0x0) << 4)
5202 * Indicates that IP header version does not match expectation
5203 * from L2 Ethertype for IPv4 and IPv6 in the outer tunnel header.
5205 #define RX_PKT_V2_CMPL_HI_ERRORS_OT_PKT_ERROR_OT_L3_BAD_VERSION \
5206 (UINT32_C(0x1) << 4)
5208 * Indicates that header length is out of range in the outer
5209 * tunnel header. Valid for IPv4.
5211 #define RX_PKT_V2_CMPL_HI_ERRORS_OT_PKT_ERROR_OT_L3_BAD_HDR_LEN \
5212 (UINT32_C(0x2) << 4)
5214 * Indicates that physical packet is shorter than that claimed
5215 * by the outer tunnel l3 header length. Valid for IPv4, or
5216 * IPv6 outer tunnel packets.
5218 #define RX_PKT_V2_CMPL_HI_ERRORS_OT_PKT_ERROR_OT_IP_TOTAL_ERROR \
5219 (UINT32_C(0x3) << 4)
5221 * Indicates that the physical packet is shorter than that
5222 * claimed by the outer tunnel UDP header length for a outer
5223 * tunnel UDP packet that is not fragmented.
5225 #define RX_PKT_V2_CMPL_HI_ERRORS_OT_PKT_ERROR_OT_UDP_TOTAL_ERROR \
5226 (UINT32_C(0x4) << 4)
5228 * Indicates that the IPv4 TTL or IPv6 hop limit check have
5229 * failed (e.g. TTL = 0) in the outer tunnel header. Valid for
5232 #define RX_PKT_V2_CMPL_HI_ERRORS_OT_PKT_ERROR_OT_L3_BAD_TTL \
5233 (UINT32_C(0x5) << 4)
5235 * Indicates that the IP checksum failed its check in the outer
5238 #define RX_PKT_V2_CMPL_HI_ERRORS_OT_PKT_ERROR_OT_IP_CS_ERROR \
5239 (UINT32_C(0x6) << 4)
5241 * Indicates that the L4 checksum failed its check in the outer
5244 #define RX_PKT_V2_CMPL_HI_ERRORS_OT_PKT_ERROR_OT_L4_CS_ERROR \
5245 (UINT32_C(0x7) << 4)
5246 #define RX_PKT_V2_CMPL_HI_ERRORS_OT_PKT_ERROR_LAST \
5247 RX_PKT_V2_CMPL_HI_ERRORS_OT_PKT_ERROR_OT_L4_CS_ERROR
5249 * This indicates that there was a CRC error on either an FCoE
5250 * or RoCE packet. The itype indicates the packet type.
5252 #define RX_PKT_V2_CMPL_HI_ERRORS_CRC_ERROR \
5255 * This indicates that there was an error in the tunnel portion
5256 * of the packet when this field is non-zero.
5258 #define RX_PKT_V2_CMPL_HI_ERRORS_T_PKT_ERROR_MASK \
5260 #define RX_PKT_V2_CMPL_HI_ERRORS_T_PKT_ERROR_SFT 9
5262 * No additional error occurred on the tunnel portion
5263 * of the packet or the packet does not have a tunnel.
5265 #define RX_PKT_V2_CMPL_HI_ERRORS_T_PKT_ERROR_NO_ERROR \
5266 (UINT32_C(0x0) << 9)
5268 * Indicates that IP header version does not match expectation
5269 * from L2 Ethertype for IPv4 and IPv6 in the tunnel header.
5271 #define RX_PKT_V2_CMPL_HI_ERRORS_T_PKT_ERROR_T_L3_BAD_VERSION \
5272 (UINT32_C(0x1) << 9)
5274 * Indicates that header length is out of range in the tunnel
5275 * header. Valid for IPv4.
5277 #define RX_PKT_V2_CMPL_HI_ERRORS_T_PKT_ERROR_T_L3_BAD_HDR_LEN \
5278 (UINT32_C(0x2) << 9)
5280 * Indicates that physical packet is shorter than that claimed
5281 * by the tunnel l3 header length. Valid for IPv4, or IPv6 tunnel
5284 #define RX_PKT_V2_CMPL_HI_ERRORS_T_PKT_ERROR_T_IP_TOTAL_ERROR \
5285 (UINT32_C(0x3) << 9)
5287 * Indicates that the physical packet is shorter than that claimed
5288 * by the tunnel UDP header length for a tunnel UDP packet that is
5291 #define RX_PKT_V2_CMPL_HI_ERRORS_T_PKT_ERROR_T_UDP_TOTAL_ERROR \
5292 (UINT32_C(0x4) << 9)
5294 * Indicates that the IPv4 TTL or IPv6 hop limit check have failed
5295 * (e.g. TTL = 0) in the tunnel header. Valid for IPv4, and IPv6.
5297 #define RX_PKT_V2_CMPL_HI_ERRORS_T_PKT_ERROR_T_L3_BAD_TTL \
5298 (UINT32_C(0x5) << 9)
5300 * Indicates that the IP checksum failed its check in the tunnel
5303 #define RX_PKT_V2_CMPL_HI_ERRORS_T_PKT_ERROR_T_IP_CS_ERROR \
5304 (UINT32_C(0x6) << 9)
5306 * Indicates that the L4 checksum failed its check in the tunnel
5309 #define RX_PKT_V2_CMPL_HI_ERRORS_T_PKT_ERROR_T_L4_CS_ERROR \
5310 (UINT32_C(0x7) << 9)
5311 #define RX_PKT_V2_CMPL_HI_ERRORS_T_PKT_ERROR_LAST \
5312 RX_PKT_V2_CMPL_HI_ERRORS_T_PKT_ERROR_T_L4_CS_ERROR
5314 * This indicates that there was an error in the inner
5315 * portion of the packet when this
5316 * field is non-zero.
5318 #define RX_PKT_V2_CMPL_HI_ERRORS_PKT_ERROR_MASK \
5320 #define RX_PKT_V2_CMPL_HI_ERRORS_PKT_ERROR_SFT 12
5322 * No additional error occurred on the tunnel portion
5323 * or the packet of the packet does not have a tunnel.
5325 #define RX_PKT_V2_CMPL_HI_ERRORS_PKT_ERROR_NO_ERROR \
5326 (UINT32_C(0x0) << 12)
5328 * Indicates that IP header version does not match
5329 * expectation from L2 Ethertype for IPv4 and IPv6 or that
5330 * option other than VFT was parsed on
5333 #define RX_PKT_V2_CMPL_HI_ERRORS_PKT_ERROR_L3_BAD_VERSION \
5334 (UINT32_C(0x1) << 12)
5336 * indicates that header length is out of range. Valid for
5339 #define RX_PKT_V2_CMPL_HI_ERRORS_PKT_ERROR_L3_BAD_HDR_LEN \
5340 (UINT32_C(0x2) << 12)
5342 * indicates that the IPv4 TTL or IPv6 hop limit check
5343 * have failed (e.g. TTL = 0). Valid for IPv4, and IPv6
5345 #define RX_PKT_V2_CMPL_HI_ERRORS_PKT_ERROR_L3_BAD_TTL \
5346 (UINT32_C(0x3) << 12)
5348 * Indicates that physical packet is shorter than that
5349 * claimed by the l3 header length. Valid for IPv4,
5350 * IPv6 packet or RoCE packets.
5352 #define RX_PKT_V2_CMPL_HI_ERRORS_PKT_ERROR_IP_TOTAL_ERROR \
5353 (UINT32_C(0x4) << 12)
5355 * Indicates that the physical packet is shorter than that
5356 * claimed by the UDP header length for a UDP packet that is
5359 #define RX_PKT_V2_CMPL_HI_ERRORS_PKT_ERROR_UDP_TOTAL_ERROR \
5360 (UINT32_C(0x5) << 12)
5362 * Indicates that TCP header length > IP payload. Valid for
5365 #define RX_PKT_V2_CMPL_HI_ERRORS_PKT_ERROR_L4_BAD_HDR_LEN \
5366 (UINT32_C(0x6) << 12)
5367 /* Indicates that TCP header length < 5. Valid for TCP. */
5368 #define RX_PKT_V2_CMPL_HI_ERRORS_PKT_ERROR_L4_BAD_HDR_LEN_TOO_SMALL \
5369 (UINT32_C(0x7) << 12)
5371 * Indicates that TCP option headers result in a TCP header
5372 * size that does not match data offset in TCP header. Valid
5375 #define RX_PKT_V2_CMPL_HI_ERRORS_PKT_ERROR_L4_BAD_OPT_LEN \
5376 (UINT32_C(0x8) << 12)
5378 * Indicates that the IP checksum failed its check in the
5381 #define RX_PKT_V2_CMPL_HI_ERRORS_PKT_ERROR_IP_CS_ERROR \
5382 (UINT32_C(0x9) << 12)
5384 * Indicates that the L4 checksum failed its check in the
5387 #define RX_PKT_V2_CMPL_HI_ERRORS_PKT_ERROR_L4_CS_ERROR \
5388 (UINT32_C(0xa) << 12)
5389 #define RX_PKT_V2_CMPL_HI_ERRORS_PKT_ERROR_LAST \
5390 RX_PKT_V2_CMPL_HI_ERRORS_PKT_ERROR_L4_CS_ERROR
5392 * This is data from the CFA block as indicated by the meta_format
5396 /* When meta_format=1, this value is the VLAN VID. */
5397 #define RX_PKT_V2_CMPL_HI_METADATA0_VID_MASK UINT32_C(0xfff)
5398 #define RX_PKT_V2_CMPL_HI_METADATA0_VID_SFT 0
5399 /* When meta_format=1, this value is the VLAN DE. */
5400 #define RX_PKT_V2_CMPL_HI_METADATA0_DE UINT32_C(0x1000)
5401 /* When meta_format=1, this value is the VLAN PRI. */
5402 #define RX_PKT_V2_CMPL_HI_METADATA0_PRI_MASK UINT32_C(0xe000)
5403 #define RX_PKT_V2_CMPL_HI_METADATA0_PRI_SFT 13
5405 * The timestamp field contains the 32b timestamp for the packet from
5412 * This TPA completion structure is used on devices where the
5413 * `hwrm_vnic_qcaps.max_aggs_supported` value is 0.
5415 /* rx_tpa_start_cmpl (size:128b/16B) */
5416 struct rx_tpa_start_cmpl {
5417 uint16_t flags_type;
5419 * This field indicates the exact type of the completion.
5420 * By convention, the LSB identifies the length of the
5421 * record in 16B units. Even values indicate 16B
5422 * records. Odd values indicate 32B
5425 #define RX_TPA_START_CMPL_TYPE_MASK UINT32_C(0x3f)
5426 #define RX_TPA_START_CMPL_TYPE_SFT 0
5428 * RX L2 TPA Start Completion:
5429 * Completion at the beginning of a TPA operation.
5432 #define RX_TPA_START_CMPL_TYPE_RX_TPA_START UINT32_C(0x13)
5433 #define RX_TPA_START_CMPL_TYPE_LAST \
5434 RX_TPA_START_CMPL_TYPE_RX_TPA_START
5435 #define RX_TPA_START_CMPL_FLAGS_MASK UINT32_C(0xffc0)
5436 #define RX_TPA_START_CMPL_FLAGS_SFT 6
5437 /* This bit will always be '0' for TPA start completions. */
5438 #define RX_TPA_START_CMPL_FLAGS_ERROR UINT32_C(0x40)
5439 /* This field indicates how the packet was placed in the buffer. */
5440 #define RX_TPA_START_CMPL_FLAGS_PLACEMENT_MASK UINT32_C(0x380)
5441 #define RX_TPA_START_CMPL_FLAGS_PLACEMENT_SFT 7
5444 * TPA Packet was placed using jumbo algorithm. This means
5445 * that the first buffer will be filled with data before
5446 * moving to aggregation buffers. Each aggregation buffer
5447 * will be filled before moving to the next aggregation
5450 #define RX_TPA_START_CMPL_FLAGS_PLACEMENT_JUMBO \
5451 (UINT32_C(0x1) << 7)
5453 * Header/Data Separation:
5454 * Packet was placed using Header/Data separation algorithm.
5455 * The separation location is indicated by the itype field.
5457 #define RX_TPA_START_CMPL_FLAGS_PLACEMENT_HDS \
5458 (UINT32_C(0x2) << 7)
5461 * Packet will be placed using GRO/Jumbo where the first
5462 * packet is filled with data. Subsequent packets will be
5463 * placed such that any one packet does not span two
5464 * aggregation buffers unless it starts at the beginning of
5465 * an aggregation buffer.
5467 #define RX_TPA_START_CMPL_FLAGS_PLACEMENT_GRO_JUMBO \
5468 (UINT32_C(0x5) << 7)
5470 * GRO/Header-Data Separation:
5471 * Packet will be placed using GRO/HDS where the header
5472 * is in the first packet.
5473 * Payload of each packet will be
5474 * placed such that any one packet does not span two
5475 * aggregation buffers unless it starts at the beginning of
5476 * an aggregation buffer.
5478 #define RX_TPA_START_CMPL_FLAGS_PLACEMENT_GRO_HDS \
5479 (UINT32_C(0x6) << 7)
5480 #define RX_TPA_START_CMPL_FLAGS_PLACEMENT_LAST \
5481 RX_TPA_START_CMPL_FLAGS_PLACEMENT_GRO_HDS
5482 /* This bit is '1' if the RSS field in this completion is valid. */
5483 #define RX_TPA_START_CMPL_FLAGS_RSS_VALID UINT32_C(0x400)
5485 #define RX_TPA_START_CMPL_FLAGS_UNUSED UINT32_C(0x800)
5487 * This value indicates what the inner packet determined for the
5490 #define RX_TPA_START_CMPL_FLAGS_ITYPE_MASK UINT32_C(0xf000)
5491 #define RX_TPA_START_CMPL_FLAGS_ITYPE_SFT 12
5494 * Indicates that the packet was IP and TCP.
5496 #define RX_TPA_START_CMPL_FLAGS_ITYPE_TCP \
5497 (UINT32_C(0x2) << 12)
5498 #define RX_TPA_START_CMPL_FLAGS_ITYPE_LAST \
5499 RX_TPA_START_CMPL_FLAGS_ITYPE_TCP
5501 * This value indicates the amount of packet data written to the
5502 * buffer the opaque field in this completion corresponds to.
5506 * This is a copy of the opaque field from the RX BD this completion
5511 * This value is written by the NIC such that it will be different
5512 * for each pass through the completion queue. The even passes
5513 * will write 1. The odd passes will write 0.
5517 * This value is written by the NIC such that it will be different
5518 * for each pass through the completion queue. The even passes
5519 * will write 1. The odd passes will write 0.
5521 #define RX_TPA_START_CMPL_V1 UINT32_C(0x1)
5522 #define RX_TPA_START_CMPL_LAST RX_TPA_START_CMPL_V1
5524 * This is the RSS hash type for the packet. The value is packed
5525 * {tuple_extrac_op[1:0],rss_profile_id[4:0],tuple_extrac_op[2]}.
5527 * The value of tuple_extrac_op provides the information about
5528 * what fields the hash was computed on.
5529 * * 0: The RSS hash was computed over source IP address,
5530 * destination IP address, source port, and destination port of inner
5531 * IP and TCP or UDP headers. Note: For non-tunneled packets,
5532 * the packet headers are considered inner packet headers for the RSS
5533 * hash computation purpose.
5534 * * 1: The RSS hash was computed over source IP address and destination
5535 * IP address of inner IP header. Note: For non-tunneled packets,
5536 * the packet headers are considered inner packet headers for the RSS
5537 * hash computation purpose.
5538 * * 2: The RSS hash was computed over source IP address,
5539 * destination IP address, source port, and destination port of
5540 * IP and TCP or UDP headers of outer tunnel headers.
5541 * Note: For non-tunneled packets, this value is not applicable.
5542 * * 3: The RSS hash was computed over source IP address and
5543 * destination IP address of IP header of outer tunnel headers.
5544 * Note: For non-tunneled packets, this value is not applicable.
5546 * Note that 4-tuples values listed above are applicable
5547 * for layer 4 protocols supported and enabled for RSS in the hardware,
5548 * HWRM firmware, and drivers. For example, if RSS hash is supported and
5549 * enabled for TCP traffic only, then the values of tuple_extract_op
5550 * corresponding to 4-tuples are only valid for TCP traffic.
5552 uint8_t rss_hash_type;
5554 * This is the aggregation ID that the completion is associated
5555 * with. Use this number to correlate the TPA start completion
5556 * with the TPA end completion.
5559 /* unused2 is 9 b */
5560 #define RX_TPA_START_CMPL_UNUSED2_MASK UINT32_C(0x1ff)
5561 #define RX_TPA_START_CMPL_UNUSED2_SFT 0
5563 * This is the aggregation ID that the completion is associated
5564 * with. Use this number to correlate the TPA start completion
5565 * with the TPA end completion.
5567 #define RX_TPA_START_CMPL_AGG_ID_MASK UINT32_C(0xfe00)
5568 #define RX_TPA_START_CMPL_AGG_ID_SFT 9
5570 * This value is the RSS hash value calculated for the packet
5571 * based on the mode bits and key value in the VNIC.
5577 * Last 16 bytes of rx_tpa_start_cmpl.
5579 * This TPA completion structure is used on devices where the
5580 * `hwrm_vnic_qcaps.max_aggs_supported` value is 0.
5582 /* rx_tpa_start_cmpl_hi (size:128b/16B) */
5583 struct rx_tpa_start_cmpl_hi {
5586 * This indicates that the ip checksum was calculated for the
5587 * inner packet and that the sum passed for all segments
5588 * included in the aggregation.
5590 #define RX_TPA_START_CMPL_FLAGS2_IP_CS_CALC UINT32_C(0x1)
5592 * This indicates that the TCP, UDP or ICMP checksum was
5593 * calculated for the inner packet and that the sum passed
5594 * for all segments included in the aggregation.
5596 #define RX_TPA_START_CMPL_FLAGS2_L4_CS_CALC UINT32_C(0x2)
5598 * This indicates that the ip checksum was calculated for the
5599 * tunnel header and that the sum passed for all segments
5600 * included in the aggregation.
5602 #define RX_TPA_START_CMPL_FLAGS2_T_IP_CS_CALC UINT32_C(0x4)
5604 * This indicates that the UDP checksum was
5605 * calculated for the tunnel packet and that the sum passed for
5606 * all segments included in the aggregation.
5608 #define RX_TPA_START_CMPL_FLAGS2_T_L4_CS_CALC UINT32_C(0x8)
5609 /* This value indicates what format the metadata field is. */
5610 #define RX_TPA_START_CMPL_FLAGS2_META_FORMAT_MASK UINT32_C(0xf0)
5611 #define RX_TPA_START_CMPL_FLAGS2_META_FORMAT_SFT 4
5612 /* No metadata information. Value is zero. */
5613 #define RX_TPA_START_CMPL_FLAGS2_META_FORMAT_NONE \
5614 (UINT32_C(0x0) << 4)
5616 * The metadata field contains the VLAN tag and TPID value.
5617 * - metadata[11:0] contains the vlan VID value.
5618 * - metadata[12] contains the vlan DE value.
5619 * - metadata[15:13] contains the vlan PRI value.
5620 * - metadata[31:16] contains the vlan TPID value.
5622 #define RX_TPA_START_CMPL_FLAGS2_META_FORMAT_VLAN \
5623 (UINT32_C(0x1) << 4)
5624 #define RX_TPA_START_CMPL_FLAGS2_META_FORMAT_LAST \
5625 RX_TPA_START_CMPL_FLAGS2_META_FORMAT_VLAN
5627 * This field indicates the IP type for the inner-most IP header.
5628 * A value of '0' indicates IPv4. A value of '1' indicates IPv6.
5630 #define RX_TPA_START_CMPL_FLAGS2_IP_TYPE UINT32_C(0x100)
5632 * This is data from the CFA block as indicated by the meta_format
5636 /* When meta_format=1, this value is the VLAN VID. */
5637 #define RX_TPA_START_CMPL_METADATA_VID_MASK UINT32_C(0xfff)
5638 #define RX_TPA_START_CMPL_METADATA_VID_SFT 0
5639 /* When meta_format=1, this value is the VLAN DE. */
5640 #define RX_TPA_START_CMPL_METADATA_DE UINT32_C(0x1000)
5641 /* When meta_format=1, this value is the VLAN PRI. */
5642 #define RX_TPA_START_CMPL_METADATA_PRI_MASK UINT32_C(0xe000)
5643 #define RX_TPA_START_CMPL_METADATA_PRI_SFT 13
5644 /* When meta_format=1, this value is the VLAN TPID. */
5645 #define RX_TPA_START_CMPL_METADATA_TPID_MASK UINT32_C(0xffff0000)
5646 #define RX_TPA_START_CMPL_METADATA_TPID_SFT 16
5649 * This value is written by the NIC such that it will be different
5650 * for each pass through the completion queue. The even passes
5651 * will write 1. The odd passes will write 0.
5653 #define RX_TPA_START_CMPL_V2 UINT32_C(0x1)
5655 * This field identifies the CFA action rule that was used for this
5660 * This is the size in bytes of the inner most L4 header.
5661 * This can be subtracted from the payload_offset to determine
5662 * the start of the inner most L4 header.
5664 uint32_t inner_l4_size_inner_l3_offset_inner_l2_offset_outer_l3_offset;
5666 * This is the offset from the beginning of the packet in bytes for
5667 * the outer L3 header. If there is no outer L3 header, then this
5670 #define RX_TPA_START_CMPL_OUTER_L3_OFFSET_MASK UINT32_C(0x1ff)
5671 #define RX_TPA_START_CMPL_OUTER_L3_OFFSET_SFT 0
5673 * This is the offset from the beginning of the packet in bytes for
5674 * the inner most L2 header.
5676 #define RX_TPA_START_CMPL_INNER_L2_OFFSET_MASK UINT32_C(0x3fe00)
5677 #define RX_TPA_START_CMPL_INNER_L2_OFFSET_SFT 9
5679 * This is the offset from the beginning of the packet in bytes for
5680 * the inner most L3 header.
5682 #define RX_TPA_START_CMPL_INNER_L3_OFFSET_MASK UINT32_C(0x7fc0000)
5683 #define RX_TPA_START_CMPL_INNER_L3_OFFSET_SFT 18
5685 * This is the size in bytes of the inner most L4 header.
5686 * This can be subtracted from the payload_offset to determine
5687 * the start of the inner most L4 header.
5689 #define RX_TPA_START_CMPL_INNER_L4_SIZE_MASK UINT32_C(0xf8000000)
5690 #define RX_TPA_START_CMPL_INNER_L4_SIZE_SFT 27
5694 * This TPA completion structure is used on devices where the
5695 * `hwrm_vnic_qcaps.max_aggs_supported` value is 0.
5696 * RX L2 TPA Start V2 Completion Record (32 bytes split to 2 16-byte
5699 /* rx_tpa_start_v2_cmpl (size:128b/16B) */
5700 struct rx_tpa_start_v2_cmpl {
5701 uint16_t flags_type;
5703 * This field indicates the exact type of the completion.
5704 * By convention, the LSB identifies the length of the
5705 * record in 16B units. Even values indicate 16B
5706 * records. Odd values indicate 32B
5709 #define RX_TPA_START_V2_CMPL_TYPE_MASK \
5711 #define RX_TPA_START_V2_CMPL_TYPE_SFT 0
5713 * RX L2 TPA Start V2 Completion:
5714 * Completion at the beginning of a TPA operation.
5716 * This is the new version of the RX_TPA_START completion used
5717 * in SR2 and later chips.
5719 #define RX_TPA_START_V2_CMPL_TYPE_RX_TPA_START_V2 \
5721 #define RX_TPA_START_V2_CMPL_TYPE_LAST \
5722 RX_TPA_START_V2_CMPL_TYPE_RX_TPA_START_V2
5723 #define RX_TPA_START_V2_CMPL_FLAGS_MASK \
5725 #define RX_TPA_START_V2_CMPL_FLAGS_SFT 6
5727 * When this bit is '1', it indicates a packet that has an error
5728 * of some type. Type of error is indicated in error_flags.
5730 #define RX_TPA_START_V2_CMPL_FLAGS_ERROR \
5732 /* This field indicates how the packet was placed in the buffer. */
5733 #define RX_TPA_START_V2_CMPL_FLAGS_PLACEMENT_MASK \
5735 #define RX_TPA_START_V2_CMPL_FLAGS_PLACEMENT_SFT 7
5738 * TPA Packet was placed using jumbo algorithm. This means
5739 * that the first buffer will be filled with data before
5740 * moving to aggregation buffers. Each aggregation buffer
5741 * will be filled before moving to the next aggregation
5744 #define RX_TPA_START_V2_CMPL_FLAGS_PLACEMENT_JUMBO \
5745 (UINT32_C(0x1) << 7)
5747 * Header/Data Separation:
5748 * Packet was placed using Header/Data separation algorithm.
5749 * The separation location is indicated by the itype field.
5751 #define RX_TPA_START_V2_CMPL_FLAGS_PLACEMENT_HDS \
5752 (UINT32_C(0x2) << 7)
5755 * Packet will be placed using In-Order Completion/Jumbo where
5756 * the first packet of the aggregation is placed using Jumbo
5757 * Placement. Subsequent packets will be placed such that each
5758 * packet starts at the beginning of an aggregation buffer.
5760 #define RX_TPA_START_V2_CMPL_FLAGS_PLACEMENT_IOC_JUMBO \
5761 (UINT32_C(0x4) << 7)
5764 * Packet will be placed using GRO/Jumbo where the first
5765 * packet is filled with data. Subsequent packets will be
5766 * placed such that any one packet does not span two
5767 * aggregation buffers unless it starts at the beginning of
5768 * an aggregation buffer.
5770 #define RX_TPA_START_V2_CMPL_FLAGS_PLACEMENT_GRO_JUMBO \
5771 (UINT32_C(0x5) << 7)
5773 * GRO/Header-Data Separation:
5774 * Packet will be placed using GRO/HDS where the header
5775 * is in the first packet.
5776 * Payload of each packet will be
5777 * placed such that any one packet does not span two
5778 * aggregation buffers unless it starts at the beginning of
5779 * an aggregation buffer.
5781 #define RX_TPA_START_V2_CMPL_FLAGS_PLACEMENT_GRO_HDS \
5782 (UINT32_C(0x6) << 7)
5784 * IOC/Header-Data Separation:
5785 * Packet will be placed using In-Order Completion/HDS where
5786 * the header is in the first packet buffer. Payload of each
5787 * packet will be placed such that each packet starts at the
5788 * beginning of an aggregation buffer.
5790 #define RX_TPA_START_V2_CMPL_FLAGS_PLACEMENT_IOC_HDS \
5791 (UINT32_C(0x7) << 7)
5792 #define RX_TPA_START_V2_CMPL_FLAGS_PLACEMENT_LAST \
5793 RX_TPA_START_V2_CMPL_FLAGS_PLACEMENT_IOC_HDS
5794 /* This bit is '1' if the RSS field in this completion is valid. */
5795 #define RX_TPA_START_V2_CMPL_FLAGS_RSS_VALID \
5798 * This bit is '1' if metadata has been added to the end of the
5799 * packet in host memory. Metadata starts at the first 32B boundary
5800 * after the end of the packet for regular and jumbo placement. It
5801 * starts at the first 32B boundary after the end of the header for
5802 * HDS placement. The length of the metadata is indicated in the
5805 #define RX_TPA_START_V2_CMPL_FLAGS_PKT_METADATA_PRESENT \
5808 * This value indicates what the inner packet determined for the
5811 #define RX_TPA_START_V2_CMPL_FLAGS_ITYPE_MASK \
5813 #define RX_TPA_START_V2_CMPL_FLAGS_ITYPE_SFT 12
5816 * Indicates that the packet was IP and TCP.
5818 #define RX_TPA_START_V2_CMPL_FLAGS_ITYPE_TCP \
5819 (UINT32_C(0x2) << 12)
5820 #define RX_TPA_START_V2_CMPL_FLAGS_ITYPE_LAST \
5821 RX_TPA_START_V2_CMPL_FLAGS_ITYPE_TCP
5823 * This value indicates the amount of packet data written to the
5824 * buffer the opaque field in this completion corresponds to.
5828 * This is a copy of the opaque field from the RX BD this completion
5829 * corresponds to. If the VNIC is configured to not use an Rx BD for
5830 * the TPA Start completion, then this is a copy of the opaque field
5831 * from the first BD used to place the TPA Start packet.
5835 * This value is written by the NIC such that it will be different
5836 * for each pass through the completion queue. The even passes
5837 * will write 1. The odd passes will write 0.
5841 * This value is written by the NIC such that it will be different
5842 * for each pass through the completion queue. The even passes
5843 * will write 1. The odd passes will write 0.
5845 #define RX_TPA_START_V2_CMPL_V1 UINT32_C(0x1)
5846 #define RX_TPA_START_V2_CMPL_LAST RX_TPA_START_V2_CMPL_V1
5848 * This is the RSS hash type for the packet. The value is packed
5849 * {tuple_extrac_op[1:0],rss_profile_id[4:0],tuple_extrac_op[2]}.
5851 * The value of tuple_extrac_op provides the information about
5852 * what fields the hash was computed on.
5853 * * 0: The RSS hash was computed over source IP address,
5854 * destination IP address, source port, and destination port of inner
5855 * IP and TCP or UDP headers. Note: For non-tunneled packets,
5856 * the packet headers are considered inner packet headers for the RSS
5857 * hash computation purpose.
5858 * * 1: The RSS hash was computed over source IP address and destination
5859 * IP address of inner IP header. Note: For non-tunneled packets,
5860 * the packet headers are considered inner packet headers for the RSS
5861 * hash computation purpose.
5862 * * 2: The RSS hash was computed over source IP address,
5863 * destination IP address, source port, and destination port of
5864 * IP and TCP or UDP headers of outer tunnel headers.
5865 * Note: For non-tunneled packets, this value is not applicable.
5866 * * 3: The RSS hash was computed over source IP address and
5867 * destination IP address of IP header of outer tunnel headers.
5868 * Note: For non-tunneled packets, this value is not applicable.
5870 * Note that 4-tuples values listed above are applicable
5871 * for layer 4 protocols supported and enabled for RSS in the hardware,
5872 * HWRM firmware, and drivers. For example, if RSS hash is supported and
5873 * enabled for TCP traffic only, then the values of tuple_extract_op
5874 * corresponding to 4-tuples are only valid for TCP traffic.
5876 uint8_t rss_hash_type;
5878 * This is the aggregation ID that the completion is associated
5879 * with. Use this number to correlate the TPA start completion
5880 * with the TPA end completion.
5884 * This is the aggregation ID that the completion is associated
5885 * with. Use this number to correlate the TPA start completion
5886 * with the TPA end completion.
5888 #define RX_TPA_START_V2_CMPL_AGG_ID_MASK UINT32_C(0xfff)
5889 #define RX_TPA_START_V2_CMPL_AGG_ID_SFT 0
5890 #define RX_TPA_START_V2_CMPL_METADATA1_MASK \
5892 #define RX_TPA_START_V2_CMPL_METADATA1_SFT 12
5893 /* When meta_format != 0, this value is the VLAN TPID_SEL. */
5894 #define RX_TPA_START_V2_CMPL_METADATA1_TPID_SEL_MASK \
5896 #define RX_TPA_START_V2_CMPL_METADATA1_TPID_SEL_SFT 12
5898 #define RX_TPA_START_V2_CMPL_METADATA1_TPID_SEL_TPID88A8 \
5899 (UINT32_C(0x0) << 12)
5901 #define RX_TPA_START_V2_CMPL_METADATA1_TPID_SEL_TPID8100 \
5902 (UINT32_C(0x1) << 12)
5904 #define RX_TPA_START_V2_CMPL_METADATA1_TPID_SEL_TPID9100 \
5905 (UINT32_C(0x2) << 12)
5907 #define RX_TPA_START_V2_CMPL_METADATA1_TPID_SEL_TPID9200 \
5908 (UINT32_C(0x3) << 12)
5910 #define RX_TPA_START_V2_CMPL_METADATA1_TPID_SEL_TPID9300 \
5911 (UINT32_C(0x4) << 12)
5912 /* Value programmed in CFA VLANTPID register. */
5913 #define RX_TPA_START_V2_CMPL_METADATA1_TPID_SEL_TPIDCFG \
5914 (UINT32_C(0x5) << 12)
5915 #define RX_TPA_START_V2_CMPL_METADATA1_TPID_SEL_LAST \
5916 RX_TPA_START_V2_CMPL_METADATA1_TPID_SEL_TPIDCFG
5917 /* When meta_format != 0, this value is the VLAN valid. */
5918 #define RX_TPA_START_V2_CMPL_METADATA1_VALID \
5921 * This value is the RSS hash value calculated for the packet
5922 * based on the mode bits and key value in the VNIC.
5923 * When vee_cmpl_mode is set in VNIC context, this is the lower
5924 * 32b of the host address from the first BD used to place the packet.
5930 * Last 16 bytes of RX L2 TPA Start V2 Completion Record
5932 * This TPA completion structure is used on devices where the
5933 * `hwrm_vnic_qcaps.max_aggs_supported` value is 0.
5935 /* rx_tpa_start_v2_cmpl_hi (size:128b/16B) */
5936 struct rx_tpa_start_v2_cmpl_hi {
5938 /* This indicates that the aggregation was done using GRO rules. */
5939 #define RX_TPA_START_V2_CMPL_FLAGS2_AGG_GRO \
5942 * When this bit is '0', the cs_ok field has the following definition:-
5943 * ip_cs_ok[2:0] = The number of header groups with a valid IP checksum
5944 * in the delivered packet, counted from the outer-most header group to
5945 * the inner-most header group, stopping at the first error. -
5946 * l4_cs_ok[5:3] = The number of header groups with a valid L4 checksum
5947 * in the delivered packet, counted from the outer-most header group to
5948 * the inner-most header group, stopping at the first error. When this
5949 * bit is '1', the cs_ok field has the following definition: -
5950 * hdr_cnt[2:0] = The number of header groups that were parsed by the
5951 * chip and passed in the delivered packet. - ip_cs_all_ok[3] =This bit
5952 * will be '1' if all the parsed header groups with an IP checksum are
5953 * valid. - l4_cs_all_ok[4] = This bit will be '1' if all the parsed
5954 * header groups with an L4 checksum are valid.
5956 #define RX_TPA_START_V2_CMPL_FLAGS2_CS_ALL_OK_MODE \
5958 /* This value indicates what format the metadata field is. */
5959 #define RX_TPA_START_V2_CMPL_FLAGS2_META_FORMAT_MASK \
5961 #define RX_TPA_START_V2_CMPL_FLAGS2_META_FORMAT_SFT 4
5962 /* There is no metadata information. Values are zero. */
5963 #define RX_TPA_START_V2_CMPL_FLAGS2_META_FORMAT_NONE \
5964 (UINT32_C(0x0) << 4)
5966 * The {metadata1, metadata0} fields contain the vtag
5967 * information: - vtag[19:0] = {valid, tpid_sel[2:0], pri[2:0],
5968 * de, vid[11:0]} The metadata2 field contains the table scope
5969 * and action record pointer. - metadata2[25:0] contains the
5970 * action record pointer. - metadata2[31:26] contains the table
5973 #define RX_TPA_START_V2_CMPL_FLAGS2_META_FORMAT_ACT_REC_PTR \
5974 (UINT32_C(0x1) << 4)
5976 * The {metadata1, metadata0} fields contain the vtag
5978 * - vtag[19:0] = {valid, tpid_sel[2:0], pri[2:0], de, vid[11:0]}
5979 * The metadata2 field contains the Tunnel ID
5980 * value, justified to LSB. i
5981 * - VXLAN = VNI[23:0] -> VXLAN Network ID
5982 * - Geneve (NGE) = VNI[23:0] a-> Virtual Network Identifier
5983 * - NVGRE = TNI[23:0] -> Tenant Network ID
5984 * - GRE = KEY[31:0] -> key field with bit mask. zero if K=0
5985 * - IPv4 = 0 (not populated)
5986 * - IPv6 = Flow Label[19:0]
5987 * - PPPoE = sessionID[15:0]
5988 * - MPLs = Outer label[19:0]
5989 * - UPAR = Selected[31:0] with bit mask
5991 #define RX_TPA_START_V2_CMPL_FLAGS2_META_FORMAT_TUNNEL_ID \
5992 (UINT32_C(0x2) << 4)
5994 * The {metadata1, metadata0} fields contain the vtag
5996 * - vtag[19:0] = {valid, tpid_sel[2:0], pri[2:0],de, vid[11:0]}
5997 * The metadata2 field contains the 32b metadata from the prepended
5998 * header (chdr_data).
6000 #define RX_TPA_START_V2_CMPL_FLAGS2_META_FORMAT_CHDR_DATA \
6001 (UINT32_C(0x3) << 4)
6003 * The {metadata1, metadata0} fields contain the vtag
6005 * - vtag[19:0] = {valid, tpid_sel[2:0], pri[2:0], de, vid[11:0]}
6006 * The metadata2 field contains the outer_l3_offset,
6007 * inner_l2_offset, inner_l3_offset, and inner_l4_size.
6008 * - metadata2[8:0] contains the outer_l3_offset.
6009 * - metadata2[17:9] contains the inner_l2_offset.
6010 * - metadata2[26:18] contains the inner_l3_offset.
6011 * - metadata2[31:27] contains the inner_l4_size.
6013 #define RX_TPA_START_V2_CMPL_FLAGS2_META_FORMAT_HDR_OFFSET \
6014 (UINT32_C(0x4) << 4)
6015 #define RX_TPA_START_V2_CMPL_FLAGS2_META_FORMAT_LAST \
6016 RX_TPA_START_V2_CMPL_FLAGS2_META_FORMAT_HDR_OFFSET
6018 * This field indicates the IP type for the inner-most IP header.
6019 * A value of '0' indicates IPv4. A value of '1' indicates IPv6.
6020 * This value is only valid if itype indicates a packet
6021 * with an IP header.
6023 #define RX_TPA_START_V2_CMPL_FLAGS2_IP_TYPE \
6026 * This indicates that the complete 1's complement checksum was
6027 * calculated for the packet in the affregation.
6029 #define RX_TPA_START_V2_CMPL_FLAGS2_COMPLETE_CHECKSUM_CALC \
6032 * This field indicates the status of IP and L4 CS calculations done
6033 * by the chip. The format of this field is indicated by the
6034 * cs_all_ok_mode bit.
6035 * CS status for TPA packets is always valid. This means that "all_ok"
6036 * status will always be set. The ok count status will be set
6037 * appropriately for the packet header, such that all existing CS
6040 #define RX_TPA_START_V2_CMPL_FLAGS2_CS_OK_MASK \
6042 #define RX_TPA_START_V2_CMPL_FLAGS2_CS_OK_SFT 10
6044 * This value is the complete 1's complement checksum calculated from
6045 * the start of the outer L3 header to the end of the packet (not
6046 * including the ethernet crc). It is valid when the
6047 * 'complete_checksum_calc' flag is set. For TPA Start completions,
6048 * the complete checksum is calculated for the first packet in the
6051 #define RX_TPA_START_V2_CMPL_FLAGS2_COMPLETE_CHECKSUM_MASK \
6052 UINT32_C(0xffff0000)
6053 #define RX_TPA_START_V2_CMPL_FLAGS2_COMPLETE_CHECKSUM_SFT 16
6055 * This is data from the CFA block as indicated by the meta_format
6057 * - meta_format 0 - none - metadata2 = 0 - not valid/not stripped
6058 * - meta_format 1 - act_rec_ptr - metadata2 = {table_scope[5:0],
6059 * act_rec_ptr[25:0]}
6060 * - meta_format 2 - tunnel_id - metadata2 = tunnel_id[31:0]
6061 * - meta_format 3 - chdr_data - metadata2 = updated_chdr_data[31:0]
6062 * - meta_format 4 - hdr_offsets - metadata2 = hdr_offsets[31:0]
6063 * When vee_cmpl_mode is set in VNIC context, this is the upper 32b
6064 * of the host address from the first BD used to place the packet.
6069 * This value is written by the NIC such that it will be different
6070 * for each pass through the completion queue. The even passes
6071 * will write 1. The odd passes will write 0.
6073 #define RX_TPA_START_V2_CMPL_V2 \
6075 #define RX_TPA_START_V2_CMPL_ERRORS_MASK \
6077 #define RX_TPA_START_V2_CMPL_ERRORS_SFT 1
6079 * This error indicates that there was some sort of problem with
6080 * the BDs for the packetThe packet should be treated as
6083 #define RX_TPA_START_V2_CMPL_ERRORS_BUFFER_ERROR_MASK \
6085 #define RX_TPA_START_V2_CMPL_ERRORS_BUFFER_ERROR_SFT 1
6086 /* No buffer error */
6087 #define RX_TPA_START_V2_CMPL_ERRORS_BUFFER_ERROR_NO_BUFFER \
6088 (UINT32_C(0x0) << 1)
6091 * Packet did not fit into packet buffer provided. This means
6092 * that the TPA Start packet was too big to be placed into the
6093 * per-packet maximum number of physical buffers configured for
6094 * the VNIC, or that it was too big to be placed into the
6095 * per-aggregation maximum number of physical buffers configured
6096 * for the VNIC. This error only occurs when the VNIC is
6097 * configured for variable size receive buffers.
6099 #define RX_TPA_START_V2_CMPL_ERRORS_BUFFER_ERROR_DID_NOT_FIT \
6100 (UINT32_C(0x1) << 1)
6103 * BDs were not formatted correctly.
6105 #define RX_TPA_START_V2_CMPL_ERRORS_BUFFER_ERROR_BAD_FORMAT \
6106 (UINT32_C(0x3) << 1)
6109 * There was a bad_format error on the previous operation
6111 #define RX_TPA_START_V2_CMPL_ERRORS_BUFFER_ERROR_FLUSH \
6112 (UINT32_C(0x5) << 1)
6113 #define RX_TPA_START_V2_CMPL_ERRORS_BUFFER_ERROR_LAST \
6114 RX_TPA_START_V2_CMPL_ERRORS_BUFFER_ERROR_FLUSH
6116 * This is data from the CFA block as indicated by the meta_format
6120 /* When meta_format != 0, this value is the VLAN VID. */
6121 #define RX_TPA_START_V2_CMPL_METADATA0_VID_MASK UINT32_C(0xfff)
6122 #define RX_TPA_START_V2_CMPL_METADATA0_VID_SFT 0
6123 /* When meta_format != 0, this value is the VLAN DE. */
6124 #define RX_TPA_START_V2_CMPL_METADATA0_DE UINT32_C(0x1000)
6125 /* When meta_format != 0, this value is the VLAN PRI. */
6126 #define RX_TPA_START_V2_CMPL_METADATA0_PRI_MASK UINT32_C(0xe000)
6127 #define RX_TPA_START_V2_CMPL_METADATA0_PRI_SFT 13
6129 * This field contains the outer_l3_offset, inner_l2_offset,
6130 * inner_l3_offset, and inner_l4_size.
6132 * hdr_offsets[8:0] contains the outer_l3_offset.
6133 * hdr_offsets[17:9] contains the inner_l2_offset.
6134 * hdr_offsets[26:18] contains the inner_l3_offset.
6135 * hdr_offsets[31:27] contains the inner_l4_size.
6137 uint32_t hdr_offsets;
6141 * This TPA completion structure is used on devices where the
6142 * `hwrm_vnic_qcaps.max_aggs_supported` value is 0.
6144 /* rx_tpa_end_cmpl (size:128b/16B) */
6145 struct rx_tpa_end_cmpl {
6146 uint16_t flags_type;
6148 * This field indicates the exact type of the completion.
6149 * By convention, the LSB identifies the length of the
6150 * record in 16B units. Even values indicate 16B
6151 * records. Odd values indicate 32B
6154 #define RX_TPA_END_CMPL_TYPE_MASK UINT32_C(0x3f)
6155 #define RX_TPA_END_CMPL_TYPE_SFT 0
6157 * RX L2 TPA End Completion:
6158 * Completion at the end of a TPA operation.
6161 #define RX_TPA_END_CMPL_TYPE_RX_TPA_END UINT32_C(0x15)
6162 #define RX_TPA_END_CMPL_TYPE_LAST \
6163 RX_TPA_END_CMPL_TYPE_RX_TPA_END
6164 #define RX_TPA_END_CMPL_FLAGS_MASK UINT32_C(0xffc0)
6165 #define RX_TPA_END_CMPL_FLAGS_SFT 6
6167 * When this bit is '1', it indicates a packet that has an
6168 * error of some type. Type of error is indicated in
6171 #define RX_TPA_END_CMPL_FLAGS_ERROR UINT32_C(0x40)
6172 /* This field indicates how the packet was placed in the buffer. */
6173 #define RX_TPA_END_CMPL_FLAGS_PLACEMENT_MASK UINT32_C(0x380)
6174 #define RX_TPA_END_CMPL_FLAGS_PLACEMENT_SFT 7
6177 * TPA Packet was placed using jumbo algorithm. This means
6178 * that the first buffer will be filled with data before
6179 * moving to aggregation buffers. Each aggregation buffer
6180 * will be filled before moving to the next aggregation
6183 #define RX_TPA_END_CMPL_FLAGS_PLACEMENT_JUMBO \
6184 (UINT32_C(0x1) << 7)
6186 * Header/Data Separation:
6187 * Packet was placed using Header/Data separation algorithm.
6188 * The separation location is indicated by the itype field.
6190 #define RX_TPA_END_CMPL_FLAGS_PLACEMENT_HDS \
6191 (UINT32_C(0x2) << 7)
6194 * Packet will be placed using In-Order Completion/Jumbo where
6195 * the first packet of the aggregation is placed using Jumbo
6196 * Placement. Subsequent packets will be placed such that each
6197 * packet starts at the beginning of an aggregation buffer.
6199 #define RX_TPA_END_CMPL_FLAGS_PLACEMENT_IOC_JUMBO \
6200 (UINT32_C(0x4) << 7)
6203 * Packet will be placed using GRO/Jumbo where the first
6204 * packet is filled with data. Subsequent packets will be
6205 * placed such that any one packet does not span two
6206 * aggregation buffers unless it starts at the beginning of
6207 * an aggregation buffer.
6209 #define RX_TPA_END_CMPL_FLAGS_PLACEMENT_GRO_JUMBO \
6210 (UINT32_C(0x5) << 7)
6212 * GRO/Header-Data Separation:
6213 * Packet will be placed using GRO/HDS where the header
6214 * is in the first packet.
6215 * Payload of each packet will be
6216 * placed such that any one packet does not span two
6217 * aggregation buffers unless it starts at the beginning of
6218 * an aggregation buffer.
6220 #define RX_TPA_END_CMPL_FLAGS_PLACEMENT_GRO_HDS \
6221 (UINT32_C(0x6) << 7)
6223 * IOC/Header-Data Separation:
6224 * Packet will be placed using In-Order Completion/HDS where
6225 * the header is in the first packet buffer. Payload of each
6226 * packet will be placed such that each packet starts at the
6227 * beginning of an aggregation buffer.
6229 #define RX_TPA_END_CMPL_FLAGS_PLACEMENT_IOC_HDS \
6230 (UINT32_C(0x7) << 7)
6231 #define RX_TPA_END_CMPL_FLAGS_PLACEMENT_LAST \
6232 RX_TPA_END_CMPL_FLAGS_PLACEMENT_IOC_HDS
6234 #define RX_TPA_END_CMPL_FLAGS_UNUSED UINT32_C(0x400)
6236 * This bit is '1' if metadata has been added to the end of the
6237 * packet in host memory. Metadata starts at the first 32B boundary
6238 * after the end of the packet for regular and jumbo placement.
6239 * It starts at the first 32B boundary after the end of the header
6240 * for HDS placement. The length of the metadata is indicated in the
6243 #define RX_TPA_END_CMPL_FLAGS_PKT_METADATA_PRESENT UINT32_C(0x800)
6245 * This value indicates what the inner packet determined for the
6248 * Indicates that the packet was IP and TCP. This indicates
6249 * that the ip_cs field is valid and that the tcp_udp_cs
6250 * field is valid and contains the TCP checksum.
6251 * This also indicates that the payload_offset field is valid.
6253 #define RX_TPA_END_CMPL_FLAGS_ITYPE_MASK \
6255 #define RX_TPA_END_CMPL_FLAGS_ITYPE_SFT 12
6257 * This value is zero for TPA End completions.
6258 * There is no data in the buffer that corresponds to the opaque
6259 * value in this completion.
6263 * This is a copy of the opaque field from the RX BD this completion
6268 * This value is written by the NIC such that it will be different
6269 * for each pass through the completion queue. The even passes
6270 * will write 1. The odd passes will write 0.
6272 uint8_t agg_bufs_v1;
6274 * This value is written by the NIC such that it will be different
6275 * for each pass through the completion queue. The even passes
6276 * will write 1. The odd passes will write 0.
6278 #define RX_TPA_END_CMPL_V1 UINT32_C(0x1)
6280 * This value is the number of aggregation buffers that follow this
6281 * entry in the completion ring that are a part of this aggregation
6283 * If the value is zero, then the packet is completely contained
6284 * in the buffer space provided in the aggregation start completion.
6286 #define RX_TPA_END_CMPL_AGG_BUFS_MASK UINT32_C(0x7e)
6287 #define RX_TPA_END_CMPL_AGG_BUFS_SFT 1
6288 /* This value is the number of segments in the TPA operation. */
6291 * This value indicates the offset in bytes from the beginning of the packet
6292 * where the inner payload starts. This value is valid for TCP, UDP,
6293 * FCoE, and RoCE packets.
6295 * A value of zero indicates an offset of 256 bytes.
6297 uint8_t payload_offset;
6299 /* unused2 is 1 b */
6300 #define RX_TPA_END_CMPL_UNUSED2 UINT32_C(0x1)
6302 * This is the aggregation ID that the completion is associated
6303 * with. Use this number to correlate the TPA start completion
6304 * with the TPA end completion.
6306 #define RX_TPA_END_CMPL_AGG_ID_MASK UINT32_C(0xfe)
6307 #define RX_TPA_END_CMPL_AGG_ID_SFT 1
6309 * For non-GRO packets, this value is the
6310 * timestamp delta between earliest and latest timestamp values for
6311 * TPA packet. If packets were not time stamped, then delta will be
6314 * For GRO packets, this field is zero except for the following
6317 * Timestamp present indication. When '0', no Timestamp
6318 * option is in the packet. When '1', then a Timestamp
6319 * option is present in the packet.
6325 * Last 16 bytes of rx_tpa_end_cmpl.
6327 * This TPA completion structure is used on devices where the
6328 * `hwrm_vnic_qcaps.max_aggs_supported` value is 0.
6330 /* rx_tpa_end_cmpl_hi (size:128b/16B) */
6331 struct rx_tpa_end_cmpl_hi {
6332 uint32_t tpa_dup_acks;
6334 * This value is the number of duplicate ACKs that have been
6335 * received as part of the TPA operation.
6337 #define RX_TPA_END_CMPL_TPA_DUP_ACKS_MASK UINT32_C(0xf)
6338 #define RX_TPA_END_CMPL_TPA_DUP_ACKS_SFT 0
6340 * This value is the valid when TPA completion is active. It
6341 * indicates the length of the longest segment of the TPA operation
6342 * for LRO mode and the length of the first segment in GRO mode.
6344 * This value may be used by GRO software to re-construct the original
6345 * packet stream from the TPA packet. This is the length of all
6346 * but the last segment for GRO. In LRO mode this value may be used
6347 * to indicate MSS size to the stack.
6349 uint16_t tpa_seg_len;
6350 /* unused4 is 16 b */
6354 * This value is written by the NIC such that it will be different
6355 * for each pass through the completion queue. The even passes
6356 * will write 1. The odd passes will write 0.
6358 #define RX_TPA_END_CMPL_V2 UINT32_C(0x1)
6359 #define RX_TPA_END_CMPL_ERRORS_MASK UINT32_C(0xfffe)
6360 #define RX_TPA_END_CMPL_ERRORS_SFT 1
6362 * This error indicates that there was some sort of problem with
6363 * the BDs for the packet that was found after part of the
6364 * packet was already placed. The packet should be treated as
6367 #define RX_TPA_END_CMPL_ERRORS_BUFFER_ERROR_MASK UINT32_C(0xe)
6368 #define RX_TPA_END_CMPL_ERRORS_BUFFER_ERROR_SFT 1
6370 * This error occurs when there is a fatal HW problem in
6371 * the chip only. It indicates that there were not
6372 * BDs on chip but that there was adequate reservation.
6373 * provided by the TPA block.
6375 #define RX_TPA_END_CMPL_ERRORS_BUFFER_ERROR_NOT_ON_CHIP \
6376 (UINT32_C(0x2) << 1)
6378 * This error occurs when TPA block was not configured to
6379 * reserve adequate BDs for TPA operations on this RX
6380 * ring. All data for the TPA operation was not placed.
6382 * This error can also be generated when the number of
6383 * segments is not programmed correctly in TPA and the
6384 * 33 total aggregation buffers allowed for the TPA
6385 * operation has been exceeded.
6387 #define RX_TPA_END_CMPL_ERRORS_BUFFER_ERROR_RSV_ERROR \
6388 (UINT32_C(0x4) << 1)
6389 #define RX_TPA_END_CMPL_ERRORS_BUFFER_ERROR_LAST \
6390 RX_TPA_END_CMPL_ERRORS_BUFFER_ERROR_RSV_ERROR
6391 /* unused5 is 16 b */
6394 * This is the opaque value that was completed for the TPA start
6395 * completion that corresponds to this TPA end completion.
6397 uint32_t start_opaque;
6401 * This TPA completion structure is used on devices where the
6402 * `hwrm_vnic_qcaps.max_aggs_supported` value is greater than 0.
6404 /* rx_tpa_v2_start_cmpl (size:128b/16B) */
6405 struct rx_tpa_v2_start_cmpl {
6406 uint16_t flags_type;
6408 * This field indicates the exact type of the completion.
6409 * By convention, the LSB identifies the length of the
6410 * record in 16B units. Even values indicate 16B
6411 * records. Odd values indicate 32B
6414 #define RX_TPA_V2_START_CMPL_TYPE_MASK \
6416 #define RX_TPA_V2_START_CMPL_TYPE_SFT 0
6418 * RX L2 TPA Start Completion:
6419 * Completion at the beginning of a TPA operation.
6422 #define RX_TPA_V2_START_CMPL_TYPE_RX_TPA_START \
6424 #define RX_TPA_V2_START_CMPL_TYPE_LAST \
6425 RX_TPA_V2_START_CMPL_TYPE_RX_TPA_START
6426 #define RX_TPA_V2_START_CMPL_FLAGS_MASK \
6428 #define RX_TPA_V2_START_CMPL_FLAGS_SFT 6
6429 /* This bit will always be '0' for TPA start completions. */
6430 #define RX_TPA_V2_START_CMPL_FLAGS_ERROR \
6432 /* This field indicates how the packet was placed in the buffer. */
6433 #define RX_TPA_V2_START_CMPL_FLAGS_PLACEMENT_MASK \
6435 #define RX_TPA_V2_START_CMPL_FLAGS_PLACEMENT_SFT 7
6438 * TPA Packet was placed using jumbo algorithm. This means
6439 * that the first buffer will be filled with data before
6440 * moving to aggregation buffers. Each aggregation buffer
6441 * will be filled before moving to the next aggregation
6444 #define RX_TPA_V2_START_CMPL_FLAGS_PLACEMENT_JUMBO \
6445 (UINT32_C(0x1) << 7)
6447 * Header/Data Separation:
6448 * Packet was placed using Header/Data separation algorithm.
6449 * The separation location is indicated by the itype field.
6451 #define RX_TPA_V2_START_CMPL_FLAGS_PLACEMENT_HDS \
6452 (UINT32_C(0x2) << 7)
6455 * Packet will be placed using GRO/Jumbo where the first
6456 * packet is filled with data. Subsequent packets will be
6457 * placed such that any one packet does not span two
6458 * aggregation buffers unless it starts at the beginning of
6459 * an aggregation buffer.
6461 #define RX_TPA_V2_START_CMPL_FLAGS_PLACEMENT_GRO_JUMBO \
6462 (UINT32_C(0x5) << 7)
6464 * GRO/Header-Data Separation:
6465 * Packet will be placed using GRO/HDS where the header
6466 * is in the first packet.
6467 * Payload of each packet will be
6468 * placed such that any one packet does not span two
6469 * aggregation buffers unless it starts at the beginning of
6470 * an aggregation buffer.
6472 #define RX_TPA_V2_START_CMPL_FLAGS_PLACEMENT_GRO_HDS \
6473 (UINT32_C(0x6) << 7)
6474 #define RX_TPA_V2_START_CMPL_FLAGS_PLACEMENT_LAST \
6475 RX_TPA_V2_START_CMPL_FLAGS_PLACEMENT_GRO_HDS
6476 /* This bit is '1' if the RSS field in this completion is valid. */
6477 #define RX_TPA_V2_START_CMPL_FLAGS_RSS_VALID \
6480 * For devices that support timestamps, when this bit is cleared the
6481 * `inner_l4_size_inner_l3_offset_inner_l2_offset_outer_l3_offset`
6482 * field contains the 32b timestamp for
6483 * the packet from the MAC. When this bit is set, the
6484 * `inner_l4_size_inner_l3_offset_inner_l2_offset_outer_l3_offset`
6485 * field contains the outer_l3_offset, inner_l2_offset,
6486 * inner_l3_offset, and inner_l4_size.
6488 #define RX_TPA_V2_START_CMPL_FLAGS_TIMESTAMP_FLD_FORMAT \
6491 * This value indicates what the inner packet determined for the
6494 #define RX_TPA_V2_START_CMPL_FLAGS_ITYPE_MASK \
6496 #define RX_TPA_V2_START_CMPL_FLAGS_ITYPE_SFT 12
6499 * Indicates that the packet was IP and TCP.
6501 #define RX_TPA_V2_START_CMPL_FLAGS_ITYPE_TCP \
6502 (UINT32_C(0x2) << 12)
6503 #define RX_TPA_V2_START_CMPL_FLAGS_ITYPE_LAST \
6504 RX_TPA_V2_START_CMPL_FLAGS_ITYPE_TCP
6506 * This value indicates the amount of packet data written to the
6507 * buffer the opaque field in this completion corresponds to.
6511 * This is a copy of the opaque field from the RX BD this completion
6516 * This value is written by the NIC such that it will be different
6517 * for each pass through the completion queue. The even passes
6518 * will write 1. The odd passes will write 0.
6522 * This value is written by the NIC such that it will be different
6523 * for each pass through the completion queue. The even passes
6524 * will write 1. The odd passes will write 0.
6526 #define RX_TPA_V2_START_CMPL_V1 UINT32_C(0x1)
6527 #define RX_TPA_V2_START_CMPL_LAST RX_TPA_V2_START_CMPL_V1
6529 * This is the RSS hash type for the packet. The value is packed
6530 * {tuple_extrac_op[1:0],rss_profile_id[4:0],tuple_extrac_op[2]}.
6532 * The value of tuple_extrac_op provides the information about
6533 * what fields the hash was computed on.
6534 * * 0: The RSS hash was computed over source IP address,
6535 * destination IP address, source port, and destination port of inner
6536 * IP and TCP or UDP headers. Note: For non-tunneled packets,
6537 * the packet headers are considered inner packet headers for the RSS
6538 * hash computation purpose.
6539 * * 1: The RSS hash was computed over source IP address and destination
6540 * IP address of inner IP header. Note: For non-tunneled packets,
6541 * the packet headers are considered inner packet headers for the RSS
6542 * hash computation purpose.
6543 * * 2: The RSS hash was computed over source IP address,
6544 * destination IP address, source port, and destination port of
6545 * IP and TCP or UDP headers of outer tunnel headers.
6546 * Note: For non-tunneled packets, this value is not applicable.
6547 * * 3: The RSS hash was computed over source IP address and
6548 * destination IP address of IP header of outer tunnel headers.
6549 * Note: For non-tunneled packets, this value is not applicable.
6551 * Note that 4-tuples values listed above are applicable
6552 * for layer 4 protocols supported and enabled for RSS in the hardware,
6553 * HWRM firmware, and drivers. For example, if RSS hash is supported and
6554 * enabled for TCP traffic only, then the values of tuple_extract_op
6555 * corresponding to 4-tuples are only valid for TCP traffic.
6557 uint8_t rss_hash_type;
6559 * This is the aggregation ID that the completion is associated
6560 * with. Use this number to correlate the TPA start completion
6561 * with the TPA end completion.
6565 * This value is the RSS hash value calculated for the packet
6566 * based on the mode bits and key value in the VNIC.
6572 * Last 16 bytes of rx_tpa_v2_start_cmpl.
6574 * This TPA completion structure is used on devices where the
6575 * `hwrm_vnic_qcaps.max_aggs_supported` value is greater than 0.
6577 /* rx_tpa_v2_start_cmpl_hi (size:128b/16B) */
6578 struct rx_tpa_v2_start_cmpl_hi {
6581 * This indicates that the ip checksum was calculated for the
6582 * inner packet and that the sum passed for all segments
6583 * included in the aggregation.
6585 #define RX_TPA_V2_START_CMPL_FLAGS2_IP_CS_CALC \
6588 * This indicates that the TCP, UDP or ICMP checksum was
6589 * calculated for the inner packet and that the sum passed
6590 * for all segments included in the aggregation.
6592 #define RX_TPA_V2_START_CMPL_FLAGS2_L4_CS_CALC \
6595 * This indicates that the ip checksum was calculated for the
6596 * tunnel header and that the sum passed for all segments
6597 * included in the aggregation.
6599 #define RX_TPA_V2_START_CMPL_FLAGS2_T_IP_CS_CALC \
6602 * This indicates that the UDP checksum was
6603 * calculated for the tunnel packet and that the sum passed for
6604 * all segments included in the aggregation.
6606 #define RX_TPA_V2_START_CMPL_FLAGS2_T_L4_CS_CALC \
6608 /* This value indicates what format the metadata field is. */
6609 #define RX_TPA_V2_START_CMPL_FLAGS2_META_FORMAT_MASK \
6611 #define RX_TPA_V2_START_CMPL_FLAGS2_META_FORMAT_SFT 4
6612 /* No metadata informtaion. Value is zero. */
6613 #define RX_TPA_V2_START_CMPL_FLAGS2_META_FORMAT_NONE \
6614 (UINT32_C(0x0) << 4)
6616 * The metadata field contains the VLAN tag and TPID value.
6617 * - metadata[11:0] contains the vlan VID value.
6618 * - metadata[12] contains the vlan DE value.
6619 * - metadata[15:13] contains the vlan PRI value.
6620 * - metadata[31:16] contains the vlan TPID value.
6622 #define RX_TPA_V2_START_CMPL_FLAGS2_META_FORMAT_VLAN \
6623 (UINT32_C(0x1) << 4)
6625 * If ext_meta_format is equal to 1, the metadata field
6626 * contains the lower 16b of the tunnel ID value, justified
6628 * - VXLAN = VNI[23:0] -> VXLAN Network ID
6629 * - Geneve (NGE) = VNI[23:0] a-> Virtual Network Identifier.
6630 * - NVGRE = TNI[23:0] -> Tenant Network ID
6631 * - GRE = KEY[31:0 -> key fieled with bit mask. zero if K = 0
6632 * - IPV4 = 0 (not populated)
6633 * - IPV6 = Flow Label[19:0]
6634 * - PPPoE = sessionID[15:0]
6635 * - MPLs = Outer label[19:0]
6636 * - UPAR = Selected[31:0] with bit mask
6638 #define RX_TPA_V2_START_CMPL_FLAGS2_META_FORMAT_TUNNEL_ID \
6639 (UINT32_C(0x2) << 4)
6641 * if ext_meta_format is equal to 1, metadata field contains
6642 * 16b metadata from the prepended header (chdr_data).
6644 #define RX_TPA_V2_START_CMPL_FLAGS2_META_FORMAT_CHDR_DATA \
6645 (UINT32_C(0x3) << 4)
6647 * If ext_meta_format is equal to 1, the metadata field contains
6648 * the outer_l3_offset, inner_l2_offset, inner_l3_offset and
6650 * - metadata[8:0] contains the outer_l3_offset.
6651 * - metadata[17:9] contains the inner_l2_offset.
6652 * - metadata[26:18] contains the inner_l3_offset.
6653 * - metadata[31:27] contains the inner_l4_size.
6655 #define RX_TPA_V2_START_CMPL_FLAGS2_META_FORMAT_HDR_OFFSET \
6656 (UINT32_C(0x4) << 4)
6657 #define RX_TPA_V2_START_CMPL_FLAGS2_META_FORMAT_LAST \
6658 RX_TPA_V2_START_CMPL_FLAGS2_META_FORMAT_HDR_OFFSET
6660 * This field indicates the IP type for the inner-most IP header.
6661 * A value of '0' indicates IPv4. A value of '1' indicates IPv6.
6663 #define RX_TPA_V2_START_CMPL_FLAGS2_IP_TYPE \
6666 * This indicates that the complete 1's complement checksum was
6667 * calculated for the packet.
6669 #define RX_TPA_V2_START_CMPL_FLAGS2_COMPLETE_CHECKSUM_CALC \
6672 * The combination of this value and meta_format indicated what
6673 * format the metadata field is.
6675 #define RX_TPA_V2_START_CMPL_FLAGS2_EXT_META_FORMAT_MASK \
6677 #define RX_TPA_V2_START_CMPL_FLAGS2_EXT_META_FORMAT_SFT 10
6679 * This value is the complete 1's complement checksum calculated from
6680 * the start of the outer L3 header to the end of the packet (not
6681 * including the ethernet crc). It is valid when the
6682 * 'complete_checksum_calc' flag is set. For TPA Start completions,
6683 * the complete checksum is calculated for the first packet in the
6686 #define RX_TPA_V2_START_CMPL_FLAGS2_COMPLETE_CHECKSUM_MASK \
6687 UINT32_C(0xffff0000)
6688 #define RX_TPA_V2_START_CMPL_FLAGS2_COMPLETE_CHECKSUM_SFT 16
6690 * This is data from the CFA block as indicated by the meta_format
6694 /* When {ext_meta_format,meta_format}=1, this value is the VLAN VID. */
6695 #define RX_TPA_V2_START_CMPL_METADATA_VID_MASK UINT32_C(0xfff)
6696 #define RX_TPA_V2_START_CMPL_METADATA_VID_SFT 0
6697 /* When {ext_meta_format,meta_format}=1, this value is the VLAN DE. */
6698 #define RX_TPA_V2_START_CMPL_METADATA_DE UINT32_C(0x1000)
6699 /* When {ext_meta_format,meta_format}=1, this value is the VLAN PRI. */
6700 #define RX_TPA_V2_START_CMPL_METADATA_PRI_MASK UINT32_C(0xe000)
6701 #define RX_TPA_V2_START_CMPL_METADATA_PRI_SFT 13
6702 /* When {ext_meta_format,meta_format}=1, this value is the VLAN TPID. */
6703 #define RX_TPA_V2_START_CMPL_METADATA_TPID_MASK UINT32_C(0xffff0000)
6704 #define RX_TPA_V2_START_CMPL_METADATA_TPID_SFT 16
6707 * This value is written by the NIC such that it will be different
6708 * for each pass through the completion queue. The even passes
6709 * will write 1. The odd passes will write 0.
6711 #define RX_TPA_V2_START_CMPL_V2 \
6713 #define RX_TPA_V2_START_CMPL_ERRORS_MASK \
6715 #define RX_TPA_V2_START_CMPL_ERRORS_SFT 1
6717 * This error indicates that there was some sort of problem with
6718 * the BDs for the packet that was found after part of the
6719 * packet was already placed. The packet should be treated as
6722 #define RX_TPA_V2_START_CMPL_ERRORS_BUFFER_ERROR_MASK \
6724 #define RX_TPA_V2_START_CMPL_ERRORS_BUFFER_ERROR_SFT 1
6725 /* No buffer error */
6726 #define RX_TPA_V2_START_CMPL_ERRORS_BUFFER_ERROR_NO_BUFFER \
6727 (UINT32_C(0x0) << 1)
6730 * BDs were not formatted correctly.
6732 #define RX_TPA_V2_START_CMPL_ERRORS_BUFFER_ERROR_BAD_FORMAT \
6733 (UINT32_C(0x3) << 1)
6736 * There was a bad_format error on the previous operation
6738 #define RX_TPA_V2_START_CMPL_ERRORS_BUFFER_ERROR_FLUSH \
6739 (UINT32_C(0x5) << 1)
6740 #define RX_TPA_V2_START_CMPL_ERRORS_BUFFER_ERROR_LAST \
6741 RX_TPA_V2_START_CMPL_ERRORS_BUFFER_ERROR_FLUSH
6743 * This field identifies the CFA action rule that was used for this
6748 * For devices that support timestamps this field is overridden
6749 * with the timestamp value. When `flags.timestamp_fld_format` is
6750 * cleared, this field contains the 32b timestamp for the packet from the
6753 * When `flags.timestamp_fld_format` is set, this field contains the
6754 * outer_l3_offset, inner_l2_offset, inner_l3_offset, and inner_l4_size
6757 uint32_t inner_l4_size_inner_l3_offset_inner_l2_offset_outer_l3_offset;
6759 * This is the offset from the beginning of the packet in bytes for
6760 * the outer L3 header. If there is no outer L3 header, then this
6763 #define RX_TPA_V2_START_CMPL_OUTER_L3_OFFSET_MASK UINT32_C(0x1ff)
6764 #define RX_TPA_V2_START_CMPL_OUTER_L3_OFFSET_SFT 0
6766 * This is the offset from the beginning of the packet in bytes for
6767 * the inner most L2 header.
6769 #define RX_TPA_V2_START_CMPL_INNER_L2_OFFSET_MASK UINT32_C(0x3fe00)
6770 #define RX_TPA_V2_START_CMPL_INNER_L2_OFFSET_SFT 9
6772 * This is the offset from the beginning of the packet in bytes for
6773 * the inner most L3 header.
6775 #define RX_TPA_V2_START_CMPL_INNER_L3_OFFSET_MASK UINT32_C(0x7fc0000)
6776 #define RX_TPA_V2_START_CMPL_INNER_L3_OFFSET_SFT 18
6778 * This is the size in bytes of the inner most L4 header.
6779 * This can be subtracted from the payload_offset to determine
6780 * the start of the inner most L4 header.
6782 #define RX_TPA_V2_START_CMPL_INNER_L4_SIZE_MASK UINT32_C(0xf8000000)
6783 #define RX_TPA_V2_START_CMPL_INNER_L4_SIZE_SFT 27
6787 * This TPA completion structure is used on devices where the
6788 * `hwrm_vnic_qcaps.max_aggs_supported` value is greater than 0.
6790 /* rx_tpa_v2_end_cmpl (size:128b/16B) */
6791 struct rx_tpa_v2_end_cmpl {
6792 uint16_t flags_type;
6794 * This field indicates the exact type of the completion.
6795 * By convention, the LSB identifies the length of the
6796 * record in 16B units. Even values indicate 16B
6797 * records. Odd values indicate 32B
6800 #define RX_TPA_V2_END_CMPL_TYPE_MASK \
6802 #define RX_TPA_V2_END_CMPL_TYPE_SFT 0
6804 * RX L2 TPA End Completion:
6805 * Completion at the end of a TPA operation.
6808 #define RX_TPA_V2_END_CMPL_TYPE_RX_TPA_END \
6810 #define RX_TPA_V2_END_CMPL_TYPE_LAST \
6811 RX_TPA_V2_END_CMPL_TYPE_RX_TPA_END
6812 #define RX_TPA_V2_END_CMPL_FLAGS_MASK \
6814 #define RX_TPA_V2_END_CMPL_FLAGS_SFT 6
6816 * When this bit is '1', it indicates a packet that has an
6817 * error of some type. Type of error is indicated in
6820 #define RX_TPA_V2_END_CMPL_FLAGS_ERROR \
6822 /* This field indicates how the packet was placed in the buffer. */
6823 #define RX_TPA_V2_END_CMPL_FLAGS_PLACEMENT_MASK \
6825 #define RX_TPA_V2_END_CMPL_FLAGS_PLACEMENT_SFT 7
6828 * TPA Packet was placed using jumbo algorithm. This means
6829 * that the first buffer will be filled with data before
6830 * moving to aggregation buffers. Each aggregation buffer
6831 * will be filled before moving to the next aggregation
6834 #define RX_TPA_V2_END_CMPL_FLAGS_PLACEMENT_JUMBO \
6835 (UINT32_C(0x1) << 7)
6837 * Header/Data Separation:
6838 * Packet was placed using Header/Data separation algorithm.
6839 * The separation location is indicated by the itype field.
6841 #define RX_TPA_V2_END_CMPL_FLAGS_PLACEMENT_HDS \
6842 (UINT32_C(0x2) << 7)
6845 * Packet will be placed using GRO/Jumbo where the first
6846 * packet is filled with data. Subsequent packets will be
6847 * placed such that any one packet does not span two
6848 * aggregation buffers unless it starts at the beginning of
6849 * an aggregation buffer.
6851 #define RX_TPA_V2_END_CMPL_FLAGS_PLACEMENT_GRO_JUMBO \
6852 (UINT32_C(0x5) << 7)
6854 * GRO/Header-Data Separation:
6855 * Packet will be placed using GRO/HDS where the header
6856 * is in the first packet.
6857 * Payload of each packet will be
6858 * placed such that any one packet does not span two
6859 * aggregation buffers unless it starts at the beginning of
6860 * an aggregation buffer.
6862 #define RX_TPA_V2_END_CMPL_FLAGS_PLACEMENT_GRO_HDS \
6863 (UINT32_C(0x6) << 7)
6865 * IOC/Header-Data Separation:
6866 * Packet will be placed using In-Order Completion/HDS where
6867 * the header is in the first packet buffer. Payload of each
6868 * packet will be placed such that each packet starts at the
6869 * beginning of an aggregation buffer.
6871 #define RX_TPA_V2_END_CMPL_FLAGS_PLACEMENT_IOC_HDS \
6872 (UINT32_C(0x7) << 7)
6873 #define RX_TPA_V2_END_CMPL_FLAGS_PLACEMENT_LAST \
6874 RX_TPA_V2_END_CMPL_FLAGS_PLACEMENT_IOC_HDS
6876 #define RX_TPA_V2_END_CMPL_FLAGS_UNUSED \
6879 * This bit is '1' if metadata has been added to the end of the
6880 * packet in host memory. Metadata starts at the first 32B boundary
6881 * after the end of the packet for regular and jumbo placement.
6882 * It starts at the first 32B boundary after the end of the header
6883 * for HDS placement. The length of the metadata is indicated in the
6886 #define RX_TPA_V2_END_CMPL_FLAGS_PKT_METADATA_PRESENT \
6889 * This value indicates what the inner packet determined for the
6892 * Indicates that the packet was IP and TCP. This indicates
6893 * that the ip_cs field is valid and that the tcp_udp_cs
6894 * field is valid and contains the TCP checksum.
6895 * This also indicates that the payload_offset field is valid.
6897 #define RX_TPA_V2_END_CMPL_FLAGS_ITYPE_MASK \
6899 #define RX_TPA_V2_END_CMPL_FLAGS_ITYPE_SFT 12
6901 * This value is zero for TPA End completions.
6902 * There is no data in the buffer that corresponds to the opaque
6903 * value in this completion.
6907 * This is a copy of the opaque field from the RX BD this completion
6913 * This value is written by the NIC such that it will be different
6914 * for each pass through the completion queue. The even passes
6915 * will write 1. The odd passes will write 0.
6917 #define RX_TPA_V2_END_CMPL_V1 UINT32_C(0x1)
6918 /* This value is the number of segments in the TPA operation. */
6921 * This is the aggregation ID that the completion is associated
6922 * with. Use this number to correlate the TPA start completion
6923 * with the TPA end completion.
6927 * For non-GRO packets, this value is the
6928 * timestamp delta between earliest and latest timestamp values for
6929 * TPA packet. If packets were not time stamped, then delta will be
6932 * For GRO packets, this field is zero except for the following
6935 * Timestamp present indication. When '0', no Timestamp
6936 * option is in the packet. When '1', then a Timestamp
6937 * option is present in the packet.
6943 * Last 16 bytes of rx_tpa_v2_end_cmpl.
6945 * This TPA completion structure is used on devices where the
6946 * `hwrm_vnic_qcaps.max_aggs_supported` value is greater than 0.
6948 /* rx_tpa_v2_end_cmpl_hi (size:128b/16B) */
6949 struct rx_tpa_v2_end_cmpl_hi {
6951 * This value is the number of duplicate ACKs that have been
6952 * received as part of the TPA operation.
6954 uint16_t tpa_dup_acks;
6956 * This value is the number of duplicate ACKs that have been
6957 * received as part of the TPA operation.
6959 #define RX_TPA_V2_END_CMPL_TPA_DUP_ACKS_MASK UINT32_C(0xf)
6960 #define RX_TPA_V2_END_CMPL_TPA_DUP_ACKS_SFT 0
6962 * This value indicated the offset in bytes from the beginning of
6963 * the packet where the inner payload starts. This value is valid
6964 * for TCP, UDP, FCoE and RoCE packets
6966 uint8_t payload_offset;
6968 * The value is the total number of aggregation buffers that were
6969 * used in the TPA operation. All TPA aggregation buffer completions
6970 * precede the TPA End completion. If the value is zero, then the
6971 * aggregation is completely contained in the buffer space provided
6972 * in the aggregation start completion.
6973 * Note that the field is simply provided as a cross check.
6975 uint8_t tpa_agg_bufs;
6977 * This value is the valid when TPA completion is active. It
6978 * indicates the length of the longest segment of the TPA operation
6979 * for LRO mode and the length of the first segment in GRO mode.
6981 * This value may be used by GRO software to re-construct the original
6982 * packet stream from the TPA packet. This is the length of all
6983 * but the last segment for GRO. In LRO mode this value may be used
6984 * to indicate MSS size to the stack.
6986 uint16_t tpa_seg_len;
6990 * This value is written by the NIC such that it will be different
6991 * for each pass through the completion queue. The even passes
6992 * will write 1. The odd passes will write 0.
6994 #define RX_TPA_V2_END_CMPL_V2 UINT32_C(0x1)
6995 #define RX_TPA_V2_END_CMPL_ERRORS_MASK \
6997 #define RX_TPA_V2_END_CMPL_ERRORS_SFT 1
6999 * This error indicates that there was some sort of problem with
7000 * the BDs for the packet that was found after part of the
7001 * packet was already placed. The packet should be treated as
7004 #define RX_TPA_V2_END_CMPL_ERRORS_BUFFER_ERROR_MASK \
7006 #define RX_TPA_V2_END_CMPL_ERRORS_BUFFER_ERROR_SFT 1
7007 /* No buffer error */
7008 #define RX_TPA_V2_END_CMPL_ERRORS_BUFFER_ERROR_NO_BUFFER \
7009 (UINT32_C(0x0) << 1)
7011 * This error occurs when there is a fatal HW problem in
7012 * the chip only. It indicates that there were not
7013 * BDs on chip but that there was adequate reservation.
7014 * provided by the TPA block.
7016 #define RX_TPA_V2_END_CMPL_ERRORS_BUFFER_ERROR_NOT_ON_CHIP \
7017 (UINT32_C(0x2) << 1)
7020 * BDs were not formatted correctly.
7022 #define RX_TPA_V2_END_CMPL_ERRORS_BUFFER_ERROR_BAD_FORMAT \
7023 (UINT32_C(0x3) << 1)
7025 * This error occurs when TPA block was not configured to
7026 * reserve adequate BDs for TPA operations on this RX
7027 * ring. All data for the TPA operation was not placed.
7029 * This error can also be generated when the number of
7030 * segments is not programmed correctly in TPA and the
7031 * 33 total aggregation buffers allowed for the TPA
7032 * operation has been exceeded.
7034 #define RX_TPA_V2_END_CMPL_ERRORS_BUFFER_ERROR_RSV_ERROR \
7035 (UINT32_C(0x4) << 1)
7038 * There was a bad_format error on the previous operation
7040 #define RX_TPA_V2_END_CMPL_ERRORS_BUFFER_ERROR_FLUSH \
7041 (UINT32_C(0x5) << 1)
7042 #define RX_TPA_V2_END_CMPL_ERRORS_BUFFER_ERROR_LAST \
7043 RX_TPA_V2_END_CMPL_ERRORS_BUFFER_ERROR_FLUSH
7046 * This is the opaque value that was completed for the TPA start
7047 * completion that corresponds to this TPA end completion.
7049 uint32_t start_opaque;
7053 * This TPA completion structure is used on devices where the
7054 * `hwrm_vnic_qcaps.max_aggs_supported` value is greater than 0.
7056 /* rx_tpa_v2_abuf_cmpl (size:128b/16B) */
7057 struct rx_tpa_v2_abuf_cmpl {
7060 * This field indicates the exact type of the completion.
7061 * By convention, the LSB identifies the length of the
7062 * record in 16B units. Even values indicate 16B
7063 * records. Odd values indicate 32B
7066 #define RX_TPA_V2_ABUF_CMPL_TYPE_MASK UINT32_C(0x3f)
7067 #define RX_TPA_V2_ABUF_CMPL_TYPE_SFT 0
7069 * RX TPA Aggregation Buffer completion :
7070 * Completion of an L2 aggregation buffer in support of
7071 * TPA packet completion. Length = 16B
7073 #define RX_TPA_V2_ABUF_CMPL_TYPE_RX_TPA_AGG UINT32_C(0x16)
7074 #define RX_TPA_V2_ABUF_CMPL_TYPE_LAST \
7075 RX_TPA_V2_ABUF_CMPL_TYPE_RX_TPA_AGG
7077 * This is the length of the data for the packet stored in this
7078 * aggregation buffer identified by the opaque value. This does not
7079 * include the length of any
7080 * data placed in other aggregation BDs or in the packet or buffer
7081 * BDs. This length does not include any space added due to
7082 * hdr_offset register during HDS placement mode.
7086 * This is a copy of the opaque field from the RX BD this aggregation
7087 * buffer corresponds to.
7092 * This value is written by the NIC such that it will be different
7093 * for each pass through the completion queue. The even passes
7094 * will write 1. The odd passes will write 0.
7096 #define RX_TPA_V2_ABUF_CMPL_V UINT32_C(0x1)
7098 * This is the aggregation ID that the completion is associated with. Use
7099 * this number to correlate the TPA agg completion with the TPA start
7100 * completion and the TPA end completion.
7106 /* rx_abuf_cmpl (size:128b/16B) */
7107 struct rx_abuf_cmpl {
7110 * This field indicates the exact type of the completion.
7111 * By convention, the LSB identifies the length of the
7112 * record in 16B units. Even values indicate 16B
7113 * records. Odd values indicate 32B
7116 #define RX_ABUF_CMPL_TYPE_MASK UINT32_C(0x3f)
7117 #define RX_ABUF_CMPL_TYPE_SFT 0
7119 * RX Aggregation Buffer completion :
7120 * Completion of an L2 aggregation buffer in support of
7121 * TPA, HDS, or Jumbo packet completion. Length = 16B
7123 #define RX_ABUF_CMPL_TYPE_RX_AGG UINT32_C(0x12)
7124 #define RX_ABUF_CMPL_TYPE_LAST RX_ABUF_CMPL_TYPE_RX_AGG
7126 * This is the length of the data for the packet stored in this
7127 * aggregation buffer identified by the opaque value. This does not
7128 * include the length of any
7129 * data placed in other aggregation BDs or in the packet or buffer
7130 * BDs. This length does not include any space added due to
7131 * hdr_offset register during HDS placement mode.
7135 * This is a copy of the opaque field from the RX BD this aggregation
7136 * buffer corresponds to.
7141 * This value is written by the NIC such that it will be different
7142 * for each pass through the completion queue. The even passes
7143 * will write 1. The odd passes will write 0.
7145 #define RX_ABUF_CMPL_V UINT32_C(0x1)
7146 /* unused3 is 32 b */
7150 /* VEE FLUSH Completion Record (16 bytes) */
7151 /* vee_flush (size:128b/16B) */
7153 uint32_t downstream_path_type;
7155 * This field indicates the exact type of the completion.
7156 * By convention, the LSB identifies the length of the
7157 * record in 16B units. Even values indicate 16B
7158 * records. Odd values indicate 32B
7161 #define VEE_FLUSH_TYPE_MASK UINT32_C(0x3f)
7162 #define VEE_FLUSH_TYPE_SFT 0
7164 * VEE Flush Completion:
7165 * This completion is inserted manually by the Primate and processed
7166 * by the VEE hardware to ensure that all completions on a VEE
7167 * function have been processed by the VEE hardware before FLR
7168 * process is completed.
7170 #define VEE_FLUSH_TYPE_VEE_FLUSH UINT32_C(0x1c)
7171 #define VEE_FLUSH_TYPE_LAST VEE_FLUSH_TYPE_VEE_FLUSH
7172 /* downstream_path is 1 b */
7173 #define VEE_FLUSH_DOWNSTREAM_PATH UINT32_C(0x40)
7174 /* This completion is associated with VEE Transmit */
7175 #define VEE_FLUSH_DOWNSTREAM_PATH_TX (UINT32_C(0x0) << 6)
7176 /* This completion is associated with VEE Receive */
7177 #define VEE_FLUSH_DOWNSTREAM_PATH_RX (UINT32_C(0x1) << 6)
7178 #define VEE_FLUSH_DOWNSTREAM_PATH_LAST VEE_FLUSH_DOWNSTREAM_PATH_RX
7180 * This is an opaque value that is passed through the completion
7181 * to the VEE handler SW and is used to indicate what VEE VQ or
7182 * function has completed FLR processing.
7187 * This value is written by the NIC such that it will be different
7188 * for each pass through the completion queue. The even passes will
7189 * write 1. The odd passes will write 0.
7191 #define VEE_FLUSH_V UINT32_C(0x1)
7192 /* unused3 is 32 b */
7196 /* eject_cmpl (size:128b/16B) */
7200 * This field indicates the exact type of the completion.
7201 * By convention, the LSB identifies the length of the
7202 * record in 16B units. Even values indicate 16B
7203 * records. Odd values indicate 32B
7206 #define EJECT_CMPL_TYPE_MASK UINT32_C(0x3f)
7207 #define EJECT_CMPL_TYPE_SFT 0
7209 * Statistics Ejection Completion:
7210 * Completion of statistics data ejection buffer.
7213 #define EJECT_CMPL_TYPE_STAT_EJECT UINT32_C(0x1a)
7214 #define EJECT_CMPL_TYPE_LAST EJECT_CMPL_TYPE_STAT_EJECT
7215 #define EJECT_CMPL_FLAGS_MASK UINT32_C(0xffc0)
7216 #define EJECT_CMPL_FLAGS_SFT 6
7218 * When this bit is '1', it indicates a packet that has an
7219 * error of some type. Type of error is indicated in
7222 #define EJECT_CMPL_FLAGS_ERROR UINT32_C(0x40)
7224 * This is the length of the statistics data stored in this
7229 * This is a copy of the opaque field from the RX BD this ejection
7230 * buffer corresponds to.
7235 * This value is written by the NIC such that it will be different
7236 * for each pass through the completion queue. The even passes
7237 * will write 1. The odd passes will write 0.
7239 #define EJECT_CMPL_V UINT32_C(0x1)
7240 #define EJECT_CMPL_ERRORS_MASK UINT32_C(0xfffe)
7241 #define EJECT_CMPL_ERRORS_SFT 1
7243 * This error indicates that there was some sort of problem with
7244 * the BDs for statistics ejection. The statistics ejection should
7245 * be treated as invalid
7247 #define EJECT_CMPL_ERRORS_BUFFER_ERROR_MASK UINT32_C(0xe)
7248 #define EJECT_CMPL_ERRORS_BUFFER_ERROR_SFT 1
7249 /* No buffer error */
7250 #define EJECT_CMPL_ERRORS_BUFFER_ERROR_NO_BUFFER \
7251 (UINT32_C(0x0) << 1)
7254 * Statistics did not fit into aggregation buffer provided.
7256 #define EJECT_CMPL_ERRORS_BUFFER_ERROR_DID_NOT_FIT \
7257 (UINT32_C(0x1) << 1)
7260 * BDs were not formatted correctly.
7262 #define EJECT_CMPL_ERRORS_BUFFER_ERROR_BAD_FORMAT \
7263 (UINT32_C(0x3) << 1)
7266 * There was a bad_format error on the previous operation
7268 #define EJECT_CMPL_ERRORS_BUFFER_ERROR_FLUSH \
7269 (UINT32_C(0x5) << 1)
7270 #define EJECT_CMPL_ERRORS_BUFFER_ERROR_LAST \
7271 EJECT_CMPL_ERRORS_BUFFER_ERROR_FLUSH
7272 /* reserved16 is 16 b */
7273 uint16_t reserved16;
7274 /* unused3 is 32 b */
7278 /* hwrm_cmpl (size:128b/16B) */
7282 * This field indicates the exact type of the completion.
7283 * By convention, the LSB identifies the length of the
7284 * record in 16B units. Even values indicate 16B
7285 * records. Odd values indicate 32B
7288 #define HWRM_CMPL_TYPE_MASK UINT32_C(0x3f)
7289 #define HWRM_CMPL_TYPE_SFT 0
7291 * HWRM Command Completion:
7292 * Completion of an HWRM command.
7294 #define HWRM_CMPL_TYPE_HWRM_DONE UINT32_C(0x20)
7295 #define HWRM_CMPL_TYPE_LAST HWRM_CMPL_TYPE_HWRM_DONE
7296 /* This is the sequence_id of the HWRM command that has completed. */
7297 uint16_t sequence_id;
7298 /* unused2 is 32 b */
7302 * This value is written by the NIC such that it will be different
7303 * for each pass through the completion queue. The even passes
7304 * will write 1. The odd passes will write 0.
7306 #define HWRM_CMPL_V UINT32_C(0x1)
7307 /* unused4 is 32 b */
7311 /* hwrm_fwd_req_cmpl (size:128b/16B) */
7312 struct hwrm_fwd_req_cmpl {
7314 * This field indicates the exact type of the completion.
7315 * By convention, the LSB identifies the length of the
7316 * record in 16B units. Even values indicate 16B
7317 * records. Odd values indicate 32B
7320 uint16_t req_len_type;
7322 * This field indicates the exact type of the completion.
7323 * By convention, the LSB identifies the length of the
7324 * record in 16B units. Even values indicate 16B
7325 * records. Odd values indicate 32B
7328 #define HWRM_FWD_REQ_CMPL_TYPE_MASK UINT32_C(0x3f)
7329 #define HWRM_FWD_REQ_CMPL_TYPE_SFT 0
7330 /* Forwarded HWRM Request */
7331 #define HWRM_FWD_REQ_CMPL_TYPE_HWRM_FWD_REQ UINT32_C(0x22)
7332 #define HWRM_FWD_REQ_CMPL_TYPE_LAST \
7333 HWRM_FWD_REQ_CMPL_TYPE_HWRM_FWD_REQ
7334 /* Length of forwarded request in bytes. */
7335 #define HWRM_FWD_REQ_CMPL_REQ_LEN_MASK UINT32_C(0xffc0)
7336 #define HWRM_FWD_REQ_CMPL_REQ_LEN_SFT 6
7338 * Source ID of this request.
7339 * Typically used in forwarding requests and responses.
7340 * 0x0 - 0xFFF8 - Used for function ids
7341 * 0xFFF8 - 0xFFFE - Reserved for internal processors
7345 /* unused1 is 32 b */
7347 /* Address of forwarded request. */
7348 uint32_t req_buf_addr_v[2];
7350 * This value is written by the NIC such that it will be different
7351 * for each pass through the completion queue. The even passes
7352 * will write 1. The odd passes will write 0.
7354 #define HWRM_FWD_REQ_CMPL_V UINT32_C(0x1)
7355 /* Address of forwarded request. */
7356 #define HWRM_FWD_REQ_CMPL_REQ_BUF_ADDR_MASK UINT32_C(0xfffffffe)
7357 #define HWRM_FWD_REQ_CMPL_REQ_BUF_ADDR_SFT 1
7360 /* hwrm_fwd_resp_cmpl (size:128b/16B) */
7361 struct hwrm_fwd_resp_cmpl {
7364 * This field indicates the exact type of the completion.
7365 * By convention, the LSB identifies the length of the
7366 * record in 16B units. Even values indicate 16B
7367 * records. Odd values indicate 32B
7370 #define HWRM_FWD_RESP_CMPL_TYPE_MASK UINT32_C(0x3f)
7371 #define HWRM_FWD_RESP_CMPL_TYPE_SFT 0
7372 /* Forwarded HWRM Response */
7373 #define HWRM_FWD_RESP_CMPL_TYPE_HWRM_FWD_RESP UINT32_C(0x24)
7374 #define HWRM_FWD_RESP_CMPL_TYPE_LAST \
7375 HWRM_FWD_RESP_CMPL_TYPE_HWRM_FWD_RESP
7377 * Source ID of this response.
7378 * Typically used in forwarding requests and responses.
7379 * 0x0 - 0xFFF8 - Used for function ids
7380 * 0xFFF8 - 0xFFFE - Reserved for internal processors
7384 /* Length of forwarded response in bytes. */
7386 /* unused2 is 16 b */
7388 /* Address of forwarded request. */
7389 uint32_t resp_buf_addr_v[2];
7391 * This value is written by the NIC such that it will be different
7392 * for each pass through the completion queue. The even passes
7393 * will write 1. The odd passes will write 0.
7395 #define HWRM_FWD_RESP_CMPL_V UINT32_C(0x1)
7396 /* Address of forwarded request. */
7397 #define HWRM_FWD_RESP_CMPL_RESP_BUF_ADDR_MASK UINT32_C(0xfffffffe)
7398 #define HWRM_FWD_RESP_CMPL_RESP_BUF_ADDR_SFT 1
7401 /* hwrm_async_event_cmpl (size:128b/16B) */
7402 struct hwrm_async_event_cmpl {
7405 * This field indicates the exact type of the completion.
7406 * By convention, the LSB identifies the length of the
7407 * record in 16B units. Even values indicate 16B
7408 * records. Odd values indicate 32B
7411 #define HWRM_ASYNC_EVENT_CMPL_TYPE_MASK UINT32_C(0x3f)
7412 #define HWRM_ASYNC_EVENT_CMPL_TYPE_SFT 0
7413 /* HWRM Asynchronous Event Information */
7414 #define HWRM_ASYNC_EVENT_CMPL_TYPE_HWRM_ASYNC_EVENT UINT32_C(0x2e)
7415 #define HWRM_ASYNC_EVENT_CMPL_TYPE_LAST \
7416 HWRM_ASYNC_EVENT_CMPL_TYPE_HWRM_ASYNC_EVENT
7417 /* Identifiers of events. */
7419 /* Link status changed */
7420 #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_LINK_STATUS_CHANGE \
7422 /* Link MTU changed */
7423 #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_LINK_MTU_CHANGE \
7425 /* Link speed changed */
7426 #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_LINK_SPEED_CHANGE \
7428 /* DCB Configuration changed */
7429 #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_DCB_CONFIG_CHANGE \
7431 /* Port connection not allowed */
7432 #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_PORT_CONN_NOT_ALLOWED \
7434 /* Link speed configuration was not allowed */
7435 #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_LINK_SPEED_CFG_NOT_ALLOWED \
7437 /* Link speed configuration change */
7438 #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_LINK_SPEED_CFG_CHANGE \
7440 /* Port PHY configuration change */
7441 #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_PORT_PHY_CFG_CHANGE \
7443 /* Reset notification to clients */
7444 #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_RESET_NOTIFY \
7446 /* Master function selection event */
7447 #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_ERROR_RECOVERY \
7450 * An event signifying that a ring has been disabled by
7453 #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_RING_MONITOR_MSG \
7455 /* Function driver unloaded */
7456 #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_FUNC_DRVR_UNLOAD \
7458 /* Function driver loaded */
7459 #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_FUNC_DRVR_LOAD \
7461 /* Function FLR related processing has completed */
7462 #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_FUNC_FLR_PROC_CMPLT \
7464 /* PF driver unloaded */
7465 #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_PF_DRVR_UNLOAD \
7467 /* PF driver loaded */
7468 #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_PF_DRVR_LOAD \
7470 /* VF Function Level Reset (FLR) */
7471 #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_VF_FLR \
7473 /* VF MAC Address Change */
7474 #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_VF_MAC_ADDR_CHANGE \
7476 /* PF-VF communication channel status change. */
7477 #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_PF_VF_COMM_STATUS_CHANGE \
7479 /* VF Configuration Change */
7480 #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_VF_CFG_CHANGE \
7482 /* LLFC/PFC Configuration Change */
7483 #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_LLFC_PFC_CHANGE \
7485 /* Default VNIC Configuration Change */
7486 #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_DEFAULT_VNIC_CHANGE \
7489 #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_HW_FLOW_AGED \
7492 * A debug notification being posted to the driver. These
7493 * notifications are purely for diagnostic purpose and should not be
7494 * used for functional purpose. The driver is not supposed to act
7495 * on these messages except to log/record it.
7497 #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_DEBUG_NOTIFICATION \
7500 * An EEM flow cached memory flush for all flows request event being
7501 * posted to the PF driver.
7503 #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_EEM_CACHE_FLUSH_REQ \
7506 * An EEM flow cache memory flush completion event being posted to the
7507 * firmware by the PF driver. This is indication that host EEM flush
7508 * has completed by the PF.
7510 #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_EEM_CACHE_FLUSH_DONE \
7513 * A tcp flag action change event being posted to the PF or trusted VF
7514 * driver by the firmware. The PF or trusted VF driver should query
7515 * the firmware for the new TCP flag action update after receiving
7518 #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_TCP_FLAG_ACTION_CHANGE \
7521 * An EEM flow active event being posted to the PF or trusted VF driver
7522 * by the firmware. The PF or trusted VF driver should update the
7523 * flow's aging timer after receiving this async event.
7525 #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_EEM_FLOW_ACTIVE \
7528 * A eem cfg change event being posted to the trusted VF driver by the
7529 * firmware if the parent PF EEM configuration changed.
7531 #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_EEM_CFG_CHANGE \
7535 * TFLIB unique default VNIC Configuration Change
7537 #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_TFLIB_DEFAULT_VNIC_CHANGE \
7541 * TFLIB unique link status changed
7543 #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_TFLIB_LINK_STATUS_CHANGE \
7546 * An event signifying completion for HWRM_FW_STATE_QUIESCE
7547 * (completion, timeout, or error)
7549 #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_QUIESCE_DONE \
7552 * An event signifying a HWRM command is in progress and its
7553 * response will be deferred. This event is used on crypto controllers
7556 #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_DEFERRED_RESPONSE \
7559 * An event signifying that a PFC WatchDog configuration
7560 * has changed on any port / cos.
7562 #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_PFC_WATCHDOG_CFG_CHANGE \
7565 * An echo request from the firmware. An echo response is expected by
7568 #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_ECHO_REQUEST \
7571 * An event from firmware indicating who has been selected as the
7572 * PHC Master or secondary. Also indicates the last time a failover
7575 #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_PHC_MASTER \
7578 * An event from firmware showing the last PPS timestamp that has been
7581 #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_PPS_TIMESTAMP \
7584 * An event from firmware indicating that an error has occurred.
7585 * The driver should log the event so that an administrator can be
7586 * aware that a problem has occurred that may need attention.
7588 #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_ERROR_REPORT \
7590 /* Maximum Registrable event id. */
7591 #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_MAX_RGTR_EVENT_ID \
7594 * A trace log message. This contains firmware trace logs string
7595 * embedded in the asynchronous message. This is an experimental
7596 * event, not meant for production use at this time.
7598 #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_FW_TRACE_MSG \
7601 #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_HWRM_ERROR \
7603 #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_LAST \
7604 HWRM_ASYNC_EVENT_CMPL_EVENT_ID_HWRM_ERROR
7605 /* Event specific data */
7606 uint32_t event_data2;
7609 * This value is written by the NIC such that it will be different
7610 * for each pass through the completion queue. The even passes
7611 * will write 1. The odd passes will write 0.
7613 #define HWRM_ASYNC_EVENT_CMPL_V UINT32_C(0x1)
7615 #define HWRM_ASYNC_EVENT_CMPL_OPAQUE_MASK UINT32_C(0xfe)
7616 #define HWRM_ASYNC_EVENT_CMPL_OPAQUE_SFT 1
7617 /* 8-lsb timestamp from POR (100-msec resolution) */
7618 uint8_t timestamp_lo;
7619 /* 16-lsb timestamp from POR (100-msec resolution) */
7620 uint16_t timestamp_hi;
7621 /* Event specific data */
7622 uint32_t event_data1;
7625 /* hwrm_async_event_cmpl_link_status_change (size:128b/16B) */
7626 struct hwrm_async_event_cmpl_link_status_change {
7629 * This field indicates the exact type of the completion.
7630 * By convention, the LSB identifies the length of the
7631 * record in 16B units. Even values indicate 16B
7632 * records. Odd values indicate 32B
7635 #define HWRM_ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_TYPE_MASK \
7637 #define HWRM_ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_TYPE_SFT 0
7638 /* HWRM Asynchronous Event Information */
7639 #define HWRM_ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_TYPE_HWRM_ASYNC_EVENT \
7641 #define HWRM_ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_TYPE_LAST \
7642 HWRM_ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_TYPE_HWRM_ASYNC_EVENT
7643 /* Identifiers of events. */
7645 /* Link status changed */
7646 #define HWRM_ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_ID_LINK_STATUS_CHANGE \
7648 #define HWRM_ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_ID_LAST \
7649 HWRM_ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_ID_LINK_STATUS_CHANGE
7650 /* Event specific data */
7651 uint32_t event_data2;
7654 * This value is written by the NIC such that it will be different
7655 * for each pass through the completion queue. The even passes
7656 * will write 1. The odd passes will write 0.
7658 #define HWRM_ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_V \
7661 #define HWRM_ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_OPAQUE_MASK \
7663 #define HWRM_ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_OPAQUE_SFT 1
7664 /* 8-lsb timestamp from POR (100-msec resolution) */
7665 uint8_t timestamp_lo;
7666 /* 16-lsb timestamp from POR (100-msec resolution) */
7667 uint16_t timestamp_hi;
7668 /* Event specific data */
7669 uint32_t event_data1;
7670 /* Indicates link status change */
7671 #define HWRM_ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_DATA1_LINK_CHANGE \
7674 * If this bit set to 0, then it indicates that the link
7675 * was up and it went down.
7677 #define HWRM_ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_DATA1_LINK_CHANGE_DOWN \
7680 * If this bit is set to 1, then it indicates that the link
7681 * was down and it went up.
7683 #define HWRM_ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_DATA1_LINK_CHANGE_UP \
7685 #define HWRM_ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_DATA1_LINK_CHANGE_LAST \
7686 HWRM_ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_DATA1_LINK_CHANGE_UP
7687 /* Indicates the physical port this link status change occur */
7688 #define HWRM_ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_DATA1_PORT_MASK \
7690 #define HWRM_ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_DATA1_PORT_SFT \
7693 #define HWRM_ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_DATA1_PORT_ID_MASK \
7695 #define HWRM_ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_DATA1_PORT_ID_SFT \
7697 /* Indicates the physical function this event occurred on. */
7698 #define HWRM_ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_DATA1_PF_ID_MASK \
7700 #define HWRM_ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_DATA1_PF_ID_SFT \
7704 /* hwrm_async_event_cmpl_link_mtu_change (size:128b/16B) */
7705 struct hwrm_async_event_cmpl_link_mtu_change {
7708 * This field indicates the exact type of the completion.
7709 * By convention, the LSB identifies the length of the
7710 * record in 16B units. Even values indicate 16B
7711 * records. Odd values indicate 32B
7714 #define HWRM_ASYNC_EVENT_CMPL_LINK_MTU_CHANGE_TYPE_MASK \
7716 #define HWRM_ASYNC_EVENT_CMPL_LINK_MTU_CHANGE_TYPE_SFT 0
7717 /* HWRM Asynchronous Event Information */
7718 #define HWRM_ASYNC_EVENT_CMPL_LINK_MTU_CHANGE_TYPE_HWRM_ASYNC_EVENT \
7720 #define HWRM_ASYNC_EVENT_CMPL_LINK_MTU_CHANGE_TYPE_LAST \
7721 HWRM_ASYNC_EVENT_CMPL_LINK_MTU_CHANGE_TYPE_HWRM_ASYNC_EVENT
7722 /* Identifiers of events. */
7724 /* Link MTU changed */
7725 #define HWRM_ASYNC_EVENT_CMPL_LINK_MTU_CHANGE_EVENT_ID_LINK_MTU_CHANGE \
7727 #define HWRM_ASYNC_EVENT_CMPL_LINK_MTU_CHANGE_EVENT_ID_LAST \
7728 HWRM_ASYNC_EVENT_CMPL_LINK_MTU_CHANGE_EVENT_ID_LINK_MTU_CHANGE
7729 /* Event specific data */
7730 uint32_t event_data2;
7733 * This value is written by the NIC such that it will be different
7734 * for each pass through the completion queue. The even passes
7735 * will write 1. The odd passes will write 0.
7737 #define HWRM_ASYNC_EVENT_CMPL_LINK_MTU_CHANGE_V UINT32_C(0x1)
7739 #define HWRM_ASYNC_EVENT_CMPL_LINK_MTU_CHANGE_OPAQUE_MASK \
7741 #define HWRM_ASYNC_EVENT_CMPL_LINK_MTU_CHANGE_OPAQUE_SFT 1
7742 /* 8-lsb timestamp from POR (100-msec resolution) */
7743 uint8_t timestamp_lo;
7744 /* 16-lsb timestamp from POR (100-msec resolution) */
7745 uint16_t timestamp_hi;
7746 /* Event specific data */
7747 uint32_t event_data1;
7748 /* The new MTU of the link in bytes. */
7749 #define HWRM_ASYNC_EVENT_CMPL_LINK_MTU_CHANGE_EVENT_DATA1_NEW_MTU_MASK \
7751 #define HWRM_ASYNC_EVENT_CMPL_LINK_MTU_CHANGE_EVENT_DATA1_NEW_MTU_SFT 0
7754 /* hwrm_async_event_cmpl_link_speed_change (size:128b/16B) */
7755 struct hwrm_async_event_cmpl_link_speed_change {
7758 * This field indicates the exact type of the completion.
7759 * By convention, the LSB identifies the length of the
7760 * record in 16B units. Even values indicate 16B
7761 * records. Odd values indicate 32B
7764 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_TYPE_MASK \
7766 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_TYPE_SFT 0
7767 /* HWRM Asynchronous Event Information */
7768 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_TYPE_HWRM_ASYNC_EVENT \
7770 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_TYPE_LAST \
7771 HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_TYPE_HWRM_ASYNC_EVENT
7772 /* Identifiers of events. */
7774 /* Link speed changed */
7775 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_EVENT_ID_LINK_SPEED_CHANGE \
7777 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_EVENT_ID_LAST \
7778 HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_EVENT_ID_LINK_SPEED_CHANGE
7779 /* Event specific data */
7780 uint32_t event_data2;
7783 * This value is written by the NIC such that it will be different
7784 * for each pass through the completion queue. The even passes
7785 * will write 1. The odd passes will write 0.
7787 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_V \
7790 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_OPAQUE_MASK \
7792 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_OPAQUE_SFT 1
7793 /* 8-lsb timestamp from POR (100-msec resolution) */
7794 uint8_t timestamp_lo;
7795 /* 16-lsb timestamp from POR (100-msec resolution) */
7796 uint16_t timestamp_hi;
7797 /* Event specific data */
7798 uint32_t event_data1;
7800 * When this bit is '1', the link was forced to the
7801 * force_link_speed value.
7803 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_EVENT_DATA1_FORCE \
7805 /* The new link speed in 100 Mbps units. */
7806 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_EVENT_DATA1_NEW_LINK_SPEED_100MBPS_MASK \
7808 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_EVENT_DATA1_NEW_LINK_SPEED_100MBPS_SFT \
7810 /* 100Mb link speed */
7811 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_EVENT_DATA1_NEW_LINK_SPEED_100MBPS_100MB \
7812 (UINT32_C(0x1) << 1)
7813 /* 1Gb link speed */
7814 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_EVENT_DATA1_NEW_LINK_SPEED_100MBPS_1GB \
7815 (UINT32_C(0xa) << 1)
7816 /* 2Gb link speed */
7817 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_EVENT_DATA1_NEW_LINK_SPEED_100MBPS_2GB \
7818 (UINT32_C(0x14) << 1)
7819 /* 25Gb link speed */
7820 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_EVENT_DATA1_NEW_LINK_SPEED_100MBPS_2_5GB \
7821 (UINT32_C(0x19) << 1)
7822 /* 10Gb link speed */
7823 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_EVENT_DATA1_NEW_LINK_SPEED_100MBPS_10GB \
7824 (UINT32_C(0x64) << 1)
7825 /* 20Mb link speed */
7826 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_EVENT_DATA1_NEW_LINK_SPEED_100MBPS_20GB \
7827 (UINT32_C(0xc8) << 1)
7828 /* 25Gb link speed */
7829 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_EVENT_DATA1_NEW_LINK_SPEED_100MBPS_25GB \
7830 (UINT32_C(0xfa) << 1)
7831 /* 40Gb link speed */
7832 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_EVENT_DATA1_NEW_LINK_SPEED_100MBPS_40GB \
7833 (UINT32_C(0x190) << 1)
7834 /* 50Gb link speed */
7835 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_EVENT_DATA1_NEW_LINK_SPEED_100MBPS_50GB \
7836 (UINT32_C(0x1f4) << 1)
7837 /* 100Gb link speed */
7838 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_EVENT_DATA1_NEW_LINK_SPEED_100MBPS_100GB \
7839 (UINT32_C(0x3e8) << 1)
7840 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_EVENT_DATA1_NEW_LINK_SPEED_100MBPS_LAST \
7841 HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_EVENT_DATA1_NEW_LINK_SPEED_100MBPS_100GB
7843 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_EVENT_DATA1_PORT_ID_MASK \
7844 UINT32_C(0xffff0000)
7845 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_EVENT_DATA1_PORT_ID_SFT \
7849 /* hwrm_async_event_cmpl_dcb_config_change (size:128b/16B) */
7850 struct hwrm_async_event_cmpl_dcb_config_change {
7853 * This field indicates the exact type of the completion.
7854 * By convention, the LSB identifies the length of the
7855 * record in 16B units. Even values indicate 16B
7856 * records. Odd values indicate 32B
7859 #define HWRM_ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_TYPE_MASK \
7861 #define HWRM_ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_TYPE_SFT 0
7862 /* HWRM Asynchronous Event Information */
7863 #define HWRM_ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_TYPE_HWRM_ASYNC_EVENT \
7865 #define HWRM_ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_TYPE_LAST \
7866 HWRM_ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_TYPE_HWRM_ASYNC_EVENT
7867 /* Identifiers of events. */
7869 /* DCB Configuration changed */
7870 #define HWRM_ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_EVENT_ID_DCB_CONFIG_CHANGE \
7872 #define HWRM_ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_EVENT_ID_LAST \
7873 HWRM_ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_EVENT_ID_DCB_CONFIG_CHANGE
7874 /* Event specific data */
7875 uint32_t event_data2;
7876 /* ETS configuration change */
7877 #define HWRM_ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_EVENT_DATA2_ETS \
7879 /* PFC configuration change */
7880 #define HWRM_ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_EVENT_DATA2_PFC \
7882 /* APP configuration change */
7883 #define HWRM_ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_EVENT_DATA2_APP \
7885 /* DSCP configuration change */
7886 #define HWRM_ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_EVENT_DATA2_DSCP \
7890 * This value is written by the NIC such that it will be different
7891 * for each pass through the completion queue. The even passes
7892 * will write 1. The odd passes will write 0.
7894 #define HWRM_ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_V \
7897 #define HWRM_ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_OPAQUE_MASK \
7899 #define HWRM_ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_OPAQUE_SFT 1
7900 /* 8-lsb timestamp from POR (100-msec resolution) */
7901 uint8_t timestamp_lo;
7902 /* 16-lsb timestamp from POR (100-msec resolution) */
7903 uint16_t timestamp_hi;
7904 /* Event specific data */
7905 uint32_t event_data1;
7907 #define HWRM_ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_EVENT_DATA1_PORT_ID_MASK \
7909 #define HWRM_ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_EVENT_DATA1_PORT_ID_SFT \
7911 /* Priority recommended for RoCE traffic */
7912 #define HWRM_ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_EVENT_DATA1_RECOMMEND_ROCE_PRIORITY_MASK \
7914 #define HWRM_ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_EVENT_DATA1_RECOMMEND_ROCE_PRIORITY_SFT \
7917 #define HWRM_ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_EVENT_DATA1_RECOMMEND_ROCE_PRIORITY_NONE \
7918 (UINT32_C(0xff) << 16)
7919 #define HWRM_ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_EVENT_DATA1_RECOMMEND_ROCE_PRIORITY_LAST \
7920 HWRM_ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_EVENT_DATA1_RECOMMEND_ROCE_PRIORITY_NONE
7921 /* Priority recommended for L2 traffic */
7922 #define HWRM_ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_EVENT_DATA1_RECOMMEND_L2_PRIORITY_MASK \
7923 UINT32_C(0xff000000)
7924 #define HWRM_ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_EVENT_DATA1_RECOMMEND_L2_PRIORITY_SFT \
7927 #define HWRM_ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_EVENT_DATA1_RECOMMEND_L2_PRIORITY_NONE \
7928 (UINT32_C(0xff) << 24)
7929 #define HWRM_ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_EVENT_DATA1_RECOMMEND_L2_PRIORITY_LAST \
7930 HWRM_ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_EVENT_DATA1_RECOMMEND_L2_PRIORITY_NONE
7933 /* hwrm_async_event_cmpl_port_conn_not_allowed (size:128b/16B) */
7934 struct hwrm_async_event_cmpl_port_conn_not_allowed {
7937 * This field indicates the exact type of the completion.
7938 * By convention, the LSB identifies the length of the
7939 * record in 16B units. Even values indicate 16B
7940 * records. Odd values indicate 32B
7943 #define HWRM_ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_TYPE_MASK \
7945 #define HWRM_ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_TYPE_SFT \
7947 /* HWRM Asynchronous Event Information */
7948 #define HWRM_ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_TYPE_HWRM_ASYNC_EVENT \
7950 #define HWRM_ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_TYPE_LAST \
7951 HWRM_ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_TYPE_HWRM_ASYNC_EVENT
7952 /* Identifiers of events. */
7954 /* Port connection not allowed */
7955 #define HWRM_ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_ID_PORT_CONN_NOT_ALLOWED \
7957 #define HWRM_ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_ID_LAST \
7958 HWRM_ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_ID_PORT_CONN_NOT_ALLOWED
7959 /* Event specific data */
7960 uint32_t event_data2;
7963 * This value is written by the NIC such that it will be different
7964 * for each pass through the completion queue. The even passes
7965 * will write 1. The odd passes will write 0.
7967 #define HWRM_ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_V \
7970 #define HWRM_ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_OPAQUE_MASK \
7972 #define HWRM_ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_OPAQUE_SFT 1
7973 /* 8-lsb timestamp from POR (100-msec resolution) */
7974 uint8_t timestamp_lo;
7975 /* 16-lsb timestamp from POR (100-msec resolution) */
7976 uint16_t timestamp_hi;
7977 /* Event specific data */
7978 uint32_t event_data1;
7980 #define HWRM_ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_PORT_ID_MASK \
7982 #define HWRM_ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_PORT_ID_SFT \
7985 * This value indicates the current port level enforcement policy
7986 * for the optics module when there is an optical module mismatch
7987 * and port is not connected.
7989 #define HWRM_ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_ENFORCEMENT_POLICY_MASK \
7991 #define HWRM_ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_ENFORCEMENT_POLICY_SFT \
7993 /* No enforcement */
7994 #define HWRM_ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_ENFORCEMENT_POLICY_NONE \
7995 (UINT32_C(0x0) << 16)
7996 /* Disable Transmit side Laser. */
7997 #define HWRM_ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_ENFORCEMENT_POLICY_DISABLETX \
7998 (UINT32_C(0x1) << 16)
7999 /* Raise a warning message. */
8000 #define HWRM_ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_ENFORCEMENT_POLICY_WARNINGMSG \
8001 (UINT32_C(0x2) << 16)
8002 /* Power down the module. */
8003 #define HWRM_ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_ENFORCEMENT_POLICY_PWRDOWN \
8004 (UINT32_C(0x3) << 16)
8005 #define HWRM_ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_ENFORCEMENT_POLICY_LAST \
8006 HWRM_ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_ENFORCEMENT_POLICY_PWRDOWN
8009 /* hwrm_async_event_cmpl_link_speed_cfg_not_allowed (size:128b/16B) */
8010 struct hwrm_async_event_cmpl_link_speed_cfg_not_allowed {
8013 * This field indicates the exact type of the completion.
8014 * By convention, the LSB identifies the length of the
8015 * record in 16B units. Even values indicate 16B
8016 * records. Odd values indicate 32B
8019 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_NOT_ALLOWED_TYPE_MASK \
8021 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_NOT_ALLOWED_TYPE_SFT \
8023 /* HWRM Asynchronous Event Information */
8024 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_NOT_ALLOWED_TYPE_HWRM_ASYNC_EVENT \
8026 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_NOT_ALLOWED_TYPE_LAST \
8027 HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_NOT_ALLOWED_TYPE_HWRM_ASYNC_EVENT
8028 /* Identifiers of events. */
8030 /* Link speed configuration was not allowed */
8031 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_NOT_ALLOWED_EVENT_ID_LINK_SPEED_CFG_NOT_ALLOWED \
8033 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_NOT_ALLOWED_EVENT_ID_LAST \
8034 HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_NOT_ALLOWED_EVENT_ID_LINK_SPEED_CFG_NOT_ALLOWED
8035 /* Event specific data */
8036 uint32_t event_data2;
8039 * This value is written by the NIC such that it will be different
8040 * for each pass through the completion queue. The even passes
8041 * will write 1. The odd passes will write 0.
8043 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_NOT_ALLOWED_V \
8046 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_NOT_ALLOWED_OPAQUE_MASK \
8048 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_NOT_ALLOWED_OPAQUE_SFT 1
8049 /* 8-lsb timestamp from POR (100-msec resolution) */
8050 uint8_t timestamp_lo;
8051 /* 16-lsb timestamp from POR (100-msec resolution) */
8052 uint16_t timestamp_hi;
8053 /* Event specific data */
8054 uint32_t event_data1;
8056 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_NOT_ALLOWED_EVENT_DATA1_PORT_ID_MASK \
8058 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_NOT_ALLOWED_EVENT_DATA1_PORT_ID_SFT \
8062 /* hwrm_async_event_cmpl_link_speed_cfg_change (size:128b/16B) */
8063 struct hwrm_async_event_cmpl_link_speed_cfg_change {
8066 * This field indicates the exact type of the completion.
8067 * By convention, the LSB identifies the length of the
8068 * record in 16B units. Even values indicate 16B
8069 * records. Odd values indicate 32B
8072 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_TYPE_MASK \
8074 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_TYPE_SFT \
8076 /* HWRM Asynchronous Event Information */
8077 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_TYPE_HWRM_ASYNC_EVENT \
8079 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_TYPE_LAST \
8080 HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_TYPE_HWRM_ASYNC_EVENT
8081 /* Identifiers of events. */
8083 /* Link speed configuration change */
8084 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_EVENT_ID_LINK_SPEED_CFG_CHANGE \
8086 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_EVENT_ID_LAST \
8087 HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_EVENT_ID_LINK_SPEED_CFG_CHANGE
8088 /* Event specific data */
8089 uint32_t event_data2;
8092 * This value is written by the NIC such that it will be different
8093 * for each pass through the completion queue. The even passes
8094 * will write 1. The odd passes will write 0.
8096 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_V \
8099 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_OPAQUE_MASK \
8101 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_OPAQUE_SFT 1
8102 /* 8-lsb timestamp from POR (100-msec resolution) */
8103 uint8_t timestamp_lo;
8104 /* 16-lsb timestamp from POR (100-msec resolution) */
8105 uint16_t timestamp_hi;
8106 /* Event specific data */
8107 uint32_t event_data1;
8109 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_EVENT_DATA1_PORT_ID_MASK \
8111 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_EVENT_DATA1_PORT_ID_SFT \
8114 * If set to 1, it indicates that the supported link speeds
8115 * configuration on the port has changed.
8116 * If set to 0, then there is no change in supported link speeds
8119 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_EVENT_DATA1_SUPPORTED_LINK_SPEEDS_CHANGE \
8122 * If set to 1, it indicates that the link speed configuration
8123 * on the port has become illegal or invalid.
8124 * If set to 0, then the link speed configuration on the port is
8127 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_EVENT_DATA1_ILLEGAL_LINK_SPEED_CFG \
8131 /* hwrm_async_event_cmpl_port_phy_cfg_change (size:128b/16B) */
8132 struct hwrm_async_event_cmpl_port_phy_cfg_change {
8135 * This field indicates the exact type of the completion.
8136 * By convention, the LSB identifies the length of the
8137 * record in 16B units. Even values indicate 16B
8138 * records. Odd values indicate 32B
8141 #define HWRM_ASYNC_EVENT_CMPL_PORT_PHY_CFG_CHANGE_TYPE_MASK \
8143 #define HWRM_ASYNC_EVENT_CMPL_PORT_PHY_CFG_CHANGE_TYPE_SFT \
8145 /* HWRM Asynchronous Event Information */
8146 #define HWRM_ASYNC_EVENT_CMPL_PORT_PHY_CFG_CHANGE_TYPE_HWRM_ASYNC_EVENT \
8148 #define HWRM_ASYNC_EVENT_CMPL_PORT_PHY_CFG_CHANGE_TYPE_LAST \
8149 HWRM_ASYNC_EVENT_CMPL_PORT_PHY_CFG_CHANGE_TYPE_HWRM_ASYNC_EVENT
8150 /* Identifiers of events. */
8152 /* Port PHY configuration change */
8153 #define HWRM_ASYNC_EVENT_CMPL_PORT_PHY_CFG_CHANGE_EVENT_ID_PORT_PHY_CFG_CHANGE \
8155 #define HWRM_ASYNC_EVENT_CMPL_PORT_PHY_CFG_CHANGE_EVENT_ID_LAST \
8156 HWRM_ASYNC_EVENT_CMPL_PORT_PHY_CFG_CHANGE_EVENT_ID_PORT_PHY_CFG_CHANGE
8157 /* Event specific data */
8158 uint32_t event_data2;
8161 * This value is written by the NIC such that it will be different
8162 * for each pass through the completion queue. The even passes
8163 * will write 1. The odd passes will write 0.
8165 #define HWRM_ASYNC_EVENT_CMPL_PORT_PHY_CFG_CHANGE_V \
8168 #define HWRM_ASYNC_EVENT_CMPL_PORT_PHY_CFG_CHANGE_OPAQUE_MASK \
8170 #define HWRM_ASYNC_EVENT_CMPL_PORT_PHY_CFG_CHANGE_OPAQUE_SFT 1
8171 /* 8-lsb timestamp from POR (100-msec resolution) */
8172 uint8_t timestamp_lo;
8173 /* 16-lsb timestamp from POR (100-msec resolution) */
8174 uint16_t timestamp_hi;
8175 /* Event specific data */
8176 uint32_t event_data1;
8178 #define HWRM_ASYNC_EVENT_CMPL_PORT_PHY_CFG_CHANGE_EVENT_DATA1_PORT_ID_MASK \
8180 #define HWRM_ASYNC_EVENT_CMPL_PORT_PHY_CFG_CHANGE_EVENT_DATA1_PORT_ID_SFT \
8183 * If set to 1, it indicates that the FEC
8184 * configuration on the port has changed.
8185 * If set to 0, then there is no change in FEC configuration.
8187 #define HWRM_ASYNC_EVENT_CMPL_PORT_PHY_CFG_CHANGE_EVENT_DATA1_FEC_CFG_CHANGE \
8190 * If set to 1, it indicates that the EEE configuration
8191 * on the port has changed.
8192 * If set to 0, then there is no change in EEE configuration
8195 #define HWRM_ASYNC_EVENT_CMPL_PORT_PHY_CFG_CHANGE_EVENT_DATA1_EEE_CFG_CHANGE \
8198 * If set to 1, it indicates that the pause configuration
8199 * on the PHY has changed.
8200 * If set to 0, then there is no change in the pause
8201 * configuration on the PHY.
8203 #define HWRM_ASYNC_EVENT_CMPL_PORT_PHY_CFG_CHANGE_EVENT_DATA1_PAUSE_CFG_CHANGE \
8207 /* hwrm_async_event_cmpl_reset_notify (size:128b/16B) */
8208 struct hwrm_async_event_cmpl_reset_notify {
8211 * This field indicates the exact type of the completion.
8212 * By convention, the LSB identifies the length of the
8213 * record in 16B units. Even values indicate 16B
8214 * records. Odd values indicate 32B
8217 #define HWRM_ASYNC_EVENT_CMPL_RESET_NOTIFY_TYPE_MASK \
8219 #define HWRM_ASYNC_EVENT_CMPL_RESET_NOTIFY_TYPE_SFT 0
8220 /* HWRM Asynchronous Event Information */
8221 #define HWRM_ASYNC_EVENT_CMPL_RESET_NOTIFY_TYPE_HWRM_ASYNC_EVENT \
8223 #define HWRM_ASYNC_EVENT_CMPL_RESET_NOTIFY_TYPE_LAST \
8224 HWRM_ASYNC_EVENT_CMPL_RESET_NOTIFY_TYPE_HWRM_ASYNC_EVENT
8225 /* Identifiers of events. */
8227 /* Notify clients of imminent reset. */
8228 #define HWRM_ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_ID_RESET_NOTIFY \
8230 #define HWRM_ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_ID_LAST \
8231 HWRM_ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_ID_RESET_NOTIFY
8232 /* Event specific data. The data is for internal debug use only. */
8233 uint32_t event_data2;
8235 * These bits indicate the status as being reported by the firmware.
8236 * This value is exactly the same as status code in fw_status register.
8237 * If the status code is equal to 0x8000, then the reset is initiated
8238 * by the Host using the FW_RESET command when the FW is in a healthy
8239 * state. If the status code is not equal to 0x8000, then the reset is
8240 * initiated by the FW to recover from the error or FATAL state.
8242 #define HWRM_ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA2_FW_STATUS_CODE_MASK \
8244 #define HWRM_ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA2_FW_STATUS_CODE_SFT \
8248 * This value is written by the NIC such that it will be different
8249 * for each pass through the completion queue. The even passes
8250 * will write 1. The odd passes will write 0.
8252 #define HWRM_ASYNC_EVENT_CMPL_RESET_NOTIFY_V UINT32_C(0x1)
8254 #define HWRM_ASYNC_EVENT_CMPL_RESET_NOTIFY_OPAQUE_MASK UINT32_C(0xfe)
8255 #define HWRM_ASYNC_EVENT_CMPL_RESET_NOTIFY_OPAQUE_SFT 1
8257 * 8-lsb timestamp (100-msec resolution)
8258 * The Minimum time required for the Firmware readiness after sending this
8259 * notification to the driver instances.
8261 uint8_t timestamp_lo;
8263 * 16-lsb timestamp (100-msec resolution)
8264 * The Maximum Firmware Reset bail out value in the order of 100
8265 * milli seconds. The driver instances will use this value to re-initiate the
8266 * registration process again if the core firmware didn’t set the ready
8269 uint16_t timestamp_hi;
8270 /* Event specific data */
8271 uint32_t event_data1;
8272 /* Indicates driver action requested */
8273 #define HWRM_ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_DRIVER_ACTION_MASK \
8275 #define HWRM_ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_DRIVER_ACTION_SFT \
8278 * If set to 1, it indicates that the l2 client should
8279 * stop sending in band traffic to Nitro.
8280 * if set to 0, there is no change in L2 client behavior.
8282 #define HWRM_ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_DRIVER_ACTION_DRIVER_STOP_TX_QUEUE \
8285 * If set to 1, it indicates that the L2 client should
8286 * bring down the interface.
8287 * If set to 0, then there is no change in L2 client behavior.
8289 #define HWRM_ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_DRIVER_ACTION_DRIVER_IFDOWN \
8291 #define HWRM_ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_DRIVER_ACTION_LAST \
8292 HWRM_ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_DRIVER_ACTION_DRIVER_IFDOWN
8293 /* Indicates reason for reset. */
8294 #define HWRM_ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_REASON_CODE_MASK \
8296 #define HWRM_ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_REASON_CODE_SFT \
8298 /* A management client has requested reset. */
8299 #define HWRM_ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_REASON_CODE_MANAGEMENT_RESET_REQUEST \
8300 (UINT32_C(0x1) << 8)
8301 /* A fatal firmware exception has occurred. */
8302 #define HWRM_ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_REASON_CODE_FW_EXCEPTION_FATAL \
8303 (UINT32_C(0x2) << 8)
8304 /* A non-fatal firmware exception has occurred. */
8305 #define HWRM_ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_REASON_CODE_FW_EXCEPTION_NON_FATAL \
8306 (UINT32_C(0x3) << 8)
8308 #define HWRM_ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_REASON_CODE_FAST_RESET \
8309 (UINT32_C(0x4) << 8)
8311 * Reset was a result of a firmware activation. That is, the
8312 * fw_activation flag was set in a FW_RESET operation.
8314 #define HWRM_ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_REASON_CODE_FW_ACTIVATION \
8315 (UINT32_C(0x5) << 8)
8316 #define HWRM_ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_REASON_CODE_LAST \
8317 HWRM_ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_REASON_CODE_FW_ACTIVATION
8319 * Minimum time before driver should attempt access - units 100ms ticks.
8322 #define HWRM_ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_DELAY_IN_100MS_TICKS_MASK \
8323 UINT32_C(0xffff0000)
8324 #define HWRM_ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_DELAY_IN_100MS_TICKS_SFT \
8328 /* hwrm_async_event_cmpl_error_recovery (size:128b/16B) */
8329 struct hwrm_async_event_cmpl_error_recovery {
8332 * This field indicates the exact type of the completion.
8333 * By convention, the LSB identifies the length of the
8334 * record in 16B units. Even values indicate 16B
8335 * records. Odd values indicate 32B
8338 #define HWRM_ASYNC_EVENT_CMPL_ERROR_RECOVERY_TYPE_MASK \
8340 #define HWRM_ASYNC_EVENT_CMPL_ERROR_RECOVERY_TYPE_SFT 0
8341 /* HWRM Asynchronous Event Information */
8342 #define HWRM_ASYNC_EVENT_CMPL_ERROR_RECOVERY_TYPE_HWRM_ASYNC_EVENT \
8344 #define HWRM_ASYNC_EVENT_CMPL_ERROR_RECOVERY_TYPE_LAST \
8345 HWRM_ASYNC_EVENT_CMPL_ERROR_RECOVERY_TYPE_HWRM_ASYNC_EVENT
8346 /* Identifiers of events. */
8349 * This async notification message can be used for selecting or
8350 * deselecting master function for error recovery,
8351 * and to communicate to all the functions whether error recovery
8352 * was enabled/disabled.
8354 #define HWRM_ASYNC_EVENT_CMPL_ERROR_RECOVERY_EVENT_ID_ERROR_RECOVERY \
8356 #define HWRM_ASYNC_EVENT_CMPL_ERROR_RECOVERY_EVENT_ID_LAST \
8357 HWRM_ASYNC_EVENT_CMPL_ERROR_RECOVERY_EVENT_ID_ERROR_RECOVERY
8358 /* Event specific data */
8359 uint32_t event_data2;
8362 * This value is written by the NIC such that it will be different
8363 * for each pass through the completion queue. The even passes
8364 * will write 1. The odd passes will write 0.
8366 #define HWRM_ASYNC_EVENT_CMPL_ERROR_RECOVERY_V UINT32_C(0x1)
8368 #define HWRM_ASYNC_EVENT_CMPL_ERROR_RECOVERY_OPAQUE_MASK UINT32_C(0xfe)
8369 #define HWRM_ASYNC_EVENT_CMPL_ERROR_RECOVERY_OPAQUE_SFT 1
8370 /* 8-lsb timestamp (100-msec resolution) */
8371 uint8_t timestamp_lo;
8372 /* 16-lsb timestamp (100-msec resolution) */
8373 uint16_t timestamp_hi;
8374 /* Event specific data */
8375 uint32_t event_data1;
8376 /* Indicates driver action requested */
8377 #define HWRM_ASYNC_EVENT_CMPL_ERROR_RECOVERY_EVENT_DATA1_FLAGS_MASK \
8379 #define HWRM_ASYNC_EVENT_CMPL_ERROR_RECOVERY_EVENT_DATA1_FLAGS_SFT \
8382 * If set to 1, this function is selected as Master function.
8383 * This function has responsibility to do 'chip reset' when it
8384 * detects a fatal error. If set to 0, master function functionality
8385 * is disabled on this function.
8387 #define HWRM_ASYNC_EVENT_CMPL_ERROR_RECOVERY_EVENT_DATA1_FLAGS_MASTER_FUNC \
8390 * If set to 1, error recovery is enabled.
8391 * If set to 0, error recovery is disabled.
8393 #define HWRM_ASYNC_EVENT_CMPL_ERROR_RECOVERY_EVENT_DATA1_FLAGS_RECOVERY_ENABLED \
8397 /* hwrm_async_event_cmpl_ring_monitor_msg (size:128b/16B) */
8398 struct hwrm_async_event_cmpl_ring_monitor_msg {
8401 * This field indicates the exact type of the completion.
8402 * By convention, the LSB identifies the length of the
8403 * record in 16B units. Even values indicate 16B
8404 * records. Odd values indicate 32B
8407 #define HWRM_ASYNC_EVENT_CMPL_RING_MONITOR_MSG_TYPE_MASK \
8409 #define HWRM_ASYNC_EVENT_CMPL_RING_MONITOR_MSG_TYPE_SFT 0
8410 /* HWRM Asynchronous Event Information */
8411 #define HWRM_ASYNC_EVENT_CMPL_RING_MONITOR_MSG_TYPE_HWRM_ASYNC_EVENT \
8413 #define HWRM_ASYNC_EVENT_CMPL_RING_MONITOR_MSG_TYPE_LAST \
8414 HWRM_ASYNC_EVENT_CMPL_RING_MONITOR_MSG_TYPE_HWRM_ASYNC_EVENT
8415 /* Identifiers of events. */
8417 /* Ring Monitor Message. */
8418 #define HWRM_ASYNC_EVENT_CMPL_RING_MONITOR_MSG_EVENT_ID_RING_MONITOR_MSG \
8420 #define HWRM_ASYNC_EVENT_CMPL_RING_MONITOR_MSG_EVENT_ID_LAST \
8421 HWRM_ASYNC_EVENT_CMPL_RING_MONITOR_MSG_EVENT_ID_RING_MONITOR_MSG
8422 /* Event specific data */
8423 uint32_t event_data2;
8424 /* Type of Ring disabled. */
8425 #define HWRM_ASYNC_EVENT_CMPL_RING_MONITOR_MSG_EVENT_DATA2_DISABLE_RING_TYPE_MASK \
8427 #define HWRM_ASYNC_EVENT_CMPL_RING_MONITOR_MSG_EVENT_DATA2_DISABLE_RING_TYPE_SFT \
8429 /* tx ring disabled. */
8430 #define HWRM_ASYNC_EVENT_CMPL_RING_MONITOR_MSG_EVENT_DATA2_DISABLE_RING_TYPE_TX \
8432 /* rx ring disabled. */
8433 #define HWRM_ASYNC_EVENT_CMPL_RING_MONITOR_MSG_EVENT_DATA2_DISABLE_RING_TYPE_RX \
8435 /* cmpl ring disabled. */
8436 #define HWRM_ASYNC_EVENT_CMPL_RING_MONITOR_MSG_EVENT_DATA2_DISABLE_RING_TYPE_CMPL \
8438 #define HWRM_ASYNC_EVENT_CMPL_RING_MONITOR_MSG_EVENT_DATA2_DISABLE_RING_TYPE_LAST \
8439 HWRM_ASYNC_EVENT_CMPL_RING_MONITOR_MSG_EVENT_DATA2_DISABLE_RING_TYPE_CMPL
8442 * This value is written by the NIC such that it will be different
8443 * for each pass through the completion queue. The even passes
8444 * will write 1. The odd passes will write 0.
8446 #define HWRM_ASYNC_EVENT_CMPL_RING_MONITOR_MSG_V UINT32_C(0x1)
8448 #define HWRM_ASYNC_EVENT_CMPL_RING_MONITOR_MSG_OPAQUE_MASK \
8450 #define HWRM_ASYNC_EVENT_CMPL_RING_MONITOR_MSG_OPAQUE_SFT 1
8451 /* 8-lsb timestamp from POR (100-msec resolution) */
8452 uint8_t timestamp_lo;
8453 /* 16-lsb timestamp from POR (100-msec resolution) */
8454 uint16_t timestamp_hi;
8456 * Event specific data. If ring_type_disabled indicates a tx,rx or cmpl
8457 * then this field will indicate the ring id.
8459 uint32_t event_data1;
8462 /* hwrm_async_event_cmpl_func_drvr_unload (size:128b/16B) */
8463 struct hwrm_async_event_cmpl_func_drvr_unload {
8466 * This field indicates the exact type of the completion.
8467 * By convention, the LSB identifies the length of the
8468 * record in 16B units. Even values indicate 16B
8469 * records. Odd values indicate 32B
8472 #define HWRM_ASYNC_EVENT_CMPL_FUNC_DRVR_UNLOAD_TYPE_MASK \
8474 #define HWRM_ASYNC_EVENT_CMPL_FUNC_DRVR_UNLOAD_TYPE_SFT 0
8475 /* HWRM Asynchronous Event Information */
8476 #define HWRM_ASYNC_EVENT_CMPL_FUNC_DRVR_UNLOAD_TYPE_HWRM_ASYNC_EVENT \
8478 #define HWRM_ASYNC_EVENT_CMPL_FUNC_DRVR_UNLOAD_TYPE_LAST \
8479 HWRM_ASYNC_EVENT_CMPL_FUNC_DRVR_UNLOAD_TYPE_HWRM_ASYNC_EVENT
8480 /* Identifiers of events. */
8482 /* Function driver unloaded */
8483 #define HWRM_ASYNC_EVENT_CMPL_FUNC_DRVR_UNLOAD_EVENT_ID_FUNC_DRVR_UNLOAD \
8485 #define HWRM_ASYNC_EVENT_CMPL_FUNC_DRVR_UNLOAD_EVENT_ID_LAST \
8486 HWRM_ASYNC_EVENT_CMPL_FUNC_DRVR_UNLOAD_EVENT_ID_FUNC_DRVR_UNLOAD
8487 /* Event specific data */
8488 uint32_t event_data2;
8491 * This value is written by the NIC such that it will be different
8492 * for each pass through the completion queue. The even passes
8493 * will write 1. The odd passes will write 0.
8495 #define HWRM_ASYNC_EVENT_CMPL_FUNC_DRVR_UNLOAD_V UINT32_C(0x1)
8497 #define HWRM_ASYNC_EVENT_CMPL_FUNC_DRVR_UNLOAD_OPAQUE_MASK \
8499 #define HWRM_ASYNC_EVENT_CMPL_FUNC_DRVR_UNLOAD_OPAQUE_SFT 1
8500 /* 8-lsb timestamp from POR (100-msec resolution) */
8501 uint8_t timestamp_lo;
8502 /* 16-lsb timestamp from POR (100-msec resolution) */
8503 uint16_t timestamp_hi;
8504 /* Event specific data */
8505 uint32_t event_data1;
8507 #define HWRM_ASYNC_EVENT_CMPL_FUNC_DRVR_UNLOAD_EVENT_DATA1_FUNC_ID_MASK \
8509 #define HWRM_ASYNC_EVENT_CMPL_FUNC_DRVR_UNLOAD_EVENT_DATA1_FUNC_ID_SFT \
8513 /* hwrm_async_event_cmpl_func_drvr_load (size:128b/16B) */
8514 struct hwrm_async_event_cmpl_func_drvr_load {
8517 * This field indicates the exact type of the completion.
8518 * By convention, the LSB identifies the length of the
8519 * record in 16B units. Even values indicate 16B
8520 * records. Odd values indicate 32B
8523 #define HWRM_ASYNC_EVENT_CMPL_FUNC_DRVR_LOAD_TYPE_MASK \
8525 #define HWRM_ASYNC_EVENT_CMPL_FUNC_DRVR_LOAD_TYPE_SFT 0
8526 /* HWRM Asynchronous Event Information */
8527 #define HWRM_ASYNC_EVENT_CMPL_FUNC_DRVR_LOAD_TYPE_HWRM_ASYNC_EVENT \
8529 #define HWRM_ASYNC_EVENT_CMPL_FUNC_DRVR_LOAD_TYPE_LAST \
8530 HWRM_ASYNC_EVENT_CMPL_FUNC_DRVR_LOAD_TYPE_HWRM_ASYNC_EVENT
8531 /* Identifiers of events. */
8533 /* Function driver loaded */
8534 #define HWRM_ASYNC_EVENT_CMPL_FUNC_DRVR_LOAD_EVENT_ID_FUNC_DRVR_LOAD \
8536 #define HWRM_ASYNC_EVENT_CMPL_FUNC_DRVR_LOAD_EVENT_ID_LAST \
8537 HWRM_ASYNC_EVENT_CMPL_FUNC_DRVR_LOAD_EVENT_ID_FUNC_DRVR_LOAD
8538 /* Event specific data */
8539 uint32_t event_data2;
8542 * This value is written by the NIC such that it will be different
8543 * for each pass through the completion queue. The even passes
8544 * will write 1. The odd passes will write 0.
8546 #define HWRM_ASYNC_EVENT_CMPL_FUNC_DRVR_LOAD_V UINT32_C(0x1)
8548 #define HWRM_ASYNC_EVENT_CMPL_FUNC_DRVR_LOAD_OPAQUE_MASK UINT32_C(0xfe)
8549 #define HWRM_ASYNC_EVENT_CMPL_FUNC_DRVR_LOAD_OPAQUE_SFT 1
8550 /* 8-lsb timestamp from POR (100-msec resolution) */
8551 uint8_t timestamp_lo;
8552 /* 16-lsb timestamp from POR (100-msec resolution) */
8553 uint16_t timestamp_hi;
8554 /* Event specific data */
8555 uint32_t event_data1;
8557 #define HWRM_ASYNC_EVENT_CMPL_FUNC_DRVR_LOAD_EVENT_DATA1_FUNC_ID_MASK \
8559 #define HWRM_ASYNC_EVENT_CMPL_FUNC_DRVR_LOAD_EVENT_DATA1_FUNC_ID_SFT 0
8562 /* hwrm_async_event_cmpl_func_flr_proc_cmplt (size:128b/16B) */
8563 struct hwrm_async_event_cmpl_func_flr_proc_cmplt {
8566 * This field indicates the exact type of the completion.
8567 * By convention, the LSB identifies the length of the
8568 * record in 16B units. Even values indicate 16B
8569 * records. Odd values indicate 32B
8572 #define HWRM_ASYNC_EVENT_CMPL_FUNC_FLR_PROC_CMPLT_TYPE_MASK \
8574 #define HWRM_ASYNC_EVENT_CMPL_FUNC_FLR_PROC_CMPLT_TYPE_SFT \
8576 /* HWRM Asynchronous Event Information */
8577 #define HWRM_ASYNC_EVENT_CMPL_FUNC_FLR_PROC_CMPLT_TYPE_HWRM_ASYNC_EVENT \
8579 #define HWRM_ASYNC_EVENT_CMPL_FUNC_FLR_PROC_CMPLT_TYPE_LAST \
8580 HWRM_ASYNC_EVENT_CMPL_FUNC_FLR_PROC_CMPLT_TYPE_HWRM_ASYNC_EVENT
8581 /* Identifiers of events. */
8583 /* Function FLR related processing has completed */
8584 #define HWRM_ASYNC_EVENT_CMPL_FUNC_FLR_PROC_CMPLT_EVENT_ID_FUNC_FLR_PROC_CMPLT \
8586 #define HWRM_ASYNC_EVENT_CMPL_FUNC_FLR_PROC_CMPLT_EVENT_ID_LAST \
8587 HWRM_ASYNC_EVENT_CMPL_FUNC_FLR_PROC_CMPLT_EVENT_ID_FUNC_FLR_PROC_CMPLT
8588 /* Event specific data */
8589 uint32_t event_data2;
8592 * This value is written by the NIC such that it will be different
8593 * for each pass through the completion queue. The even passes
8594 * will write 1. The odd passes will write 0.
8596 #define HWRM_ASYNC_EVENT_CMPL_FUNC_FLR_PROC_CMPLT_V \
8599 #define HWRM_ASYNC_EVENT_CMPL_FUNC_FLR_PROC_CMPLT_OPAQUE_MASK \
8601 #define HWRM_ASYNC_EVENT_CMPL_FUNC_FLR_PROC_CMPLT_OPAQUE_SFT 1
8602 /* 8-lsb timestamp from POR (100-msec resolution) */
8603 uint8_t timestamp_lo;
8604 /* 16-lsb timestamp from POR (100-msec resolution) */
8605 uint16_t timestamp_hi;
8606 /* Event specific data */
8607 uint32_t event_data1;
8609 #define HWRM_ASYNC_EVENT_CMPL_FUNC_FLR_PROC_CMPLT_EVENT_DATA1_FUNC_ID_MASK \
8611 #define HWRM_ASYNC_EVENT_CMPL_FUNC_FLR_PROC_CMPLT_EVENT_DATA1_FUNC_ID_SFT \
8615 /* hwrm_async_event_cmpl_pf_drvr_unload (size:128b/16B) */
8616 struct hwrm_async_event_cmpl_pf_drvr_unload {
8619 * This field indicates the exact type of the completion.
8620 * By convention, the LSB identifies the length of the
8621 * record in 16B units. Even values indicate 16B
8622 * records. Odd values indicate 32B
8625 #define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_UNLOAD_TYPE_MASK \
8627 #define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_UNLOAD_TYPE_SFT 0
8628 /* HWRM Asynchronous Event Information */
8629 #define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_UNLOAD_TYPE_HWRM_ASYNC_EVENT \
8631 #define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_UNLOAD_TYPE_LAST \
8632 HWRM_ASYNC_EVENT_CMPL_PF_DRVR_UNLOAD_TYPE_HWRM_ASYNC_EVENT
8633 /* Identifiers of events. */
8635 /* PF driver unloaded */
8636 #define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_UNLOAD_EVENT_ID_PF_DRVR_UNLOAD \
8638 #define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_UNLOAD_EVENT_ID_LAST \
8639 HWRM_ASYNC_EVENT_CMPL_PF_DRVR_UNLOAD_EVENT_ID_PF_DRVR_UNLOAD
8640 /* Event specific data */
8641 uint32_t event_data2;
8644 * This value is written by the NIC such that it will be different
8645 * for each pass through the completion queue. The even passes
8646 * will write 1. The odd passes will write 0.
8648 #define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_UNLOAD_V UINT32_C(0x1)
8650 #define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_UNLOAD_OPAQUE_MASK UINT32_C(0xfe)
8651 #define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_UNLOAD_OPAQUE_SFT 1
8652 /* 8-lsb timestamp from POR (100-msec resolution) */
8653 uint8_t timestamp_lo;
8654 /* 16-lsb timestamp from POR (100-msec resolution) */
8655 uint16_t timestamp_hi;
8656 /* Event specific data */
8657 uint32_t event_data1;
8659 #define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_UNLOAD_EVENT_DATA1_FUNC_ID_MASK \
8661 #define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_UNLOAD_EVENT_DATA1_FUNC_ID_SFT 0
8662 /* Indicates the physical port this pf belongs to */
8663 #define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_UNLOAD_EVENT_DATA1_PORT_MASK \
8665 #define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_UNLOAD_EVENT_DATA1_PORT_SFT 16
8668 /* hwrm_async_event_cmpl_pf_drvr_load (size:128b/16B) */
8669 struct hwrm_async_event_cmpl_pf_drvr_load {
8672 * This field indicates the exact type of the completion.
8673 * By convention, the LSB identifies the length of the
8674 * record in 16B units. Even values indicate 16B
8675 * records. Odd values indicate 32B
8678 #define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_LOAD_TYPE_MASK \
8680 #define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_LOAD_TYPE_SFT 0
8681 /* HWRM Asynchronous Event Information */
8682 #define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_LOAD_TYPE_HWRM_ASYNC_EVENT \
8684 #define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_LOAD_TYPE_LAST \
8685 HWRM_ASYNC_EVENT_CMPL_PF_DRVR_LOAD_TYPE_HWRM_ASYNC_EVENT
8686 /* Identifiers of events. */
8688 /* PF driver loaded */
8689 #define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_LOAD_EVENT_ID_PF_DRVR_LOAD \
8691 #define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_LOAD_EVENT_ID_LAST \
8692 HWRM_ASYNC_EVENT_CMPL_PF_DRVR_LOAD_EVENT_ID_PF_DRVR_LOAD
8693 /* Event specific data */
8694 uint32_t event_data2;
8697 * This value is written by the NIC such that it will be different
8698 * for each pass through the completion queue. The even passes
8699 * will write 1. The odd passes will write 0.
8701 #define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_LOAD_V UINT32_C(0x1)
8703 #define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_LOAD_OPAQUE_MASK UINT32_C(0xfe)
8704 #define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_LOAD_OPAQUE_SFT 1
8705 /* 8-lsb timestamp from POR (100-msec resolution) */
8706 uint8_t timestamp_lo;
8707 /* 16-lsb timestamp from POR (100-msec resolution) */
8708 uint16_t timestamp_hi;
8709 /* Event specific data */
8710 uint32_t event_data1;
8712 #define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_LOAD_EVENT_DATA1_FUNC_ID_MASK \
8714 #define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_LOAD_EVENT_DATA1_FUNC_ID_SFT 0
8715 /* Indicates the physical port this pf belongs to */
8716 #define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_LOAD_EVENT_DATA1_PORT_MASK \
8718 #define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_LOAD_EVENT_DATA1_PORT_SFT 16
8721 /* hwrm_async_event_cmpl_vf_flr (size:128b/16B) */
8722 struct hwrm_async_event_cmpl_vf_flr {
8725 * This field indicates the exact type of the completion.
8726 * By convention, the LSB identifies the length of the
8727 * record in 16B units. Even values indicate 16B
8728 * records. Odd values indicate 32B
8731 #define HWRM_ASYNC_EVENT_CMPL_VF_FLR_TYPE_MASK \
8733 #define HWRM_ASYNC_EVENT_CMPL_VF_FLR_TYPE_SFT 0
8734 /* HWRM Asynchronous Event Information */
8735 #define HWRM_ASYNC_EVENT_CMPL_VF_FLR_TYPE_HWRM_ASYNC_EVENT \
8737 #define HWRM_ASYNC_EVENT_CMPL_VF_FLR_TYPE_LAST \
8738 HWRM_ASYNC_EVENT_CMPL_VF_FLR_TYPE_HWRM_ASYNC_EVENT
8739 /* Identifiers of events. */
8741 /* VF Function Level Reset (FLR) */
8742 #define HWRM_ASYNC_EVENT_CMPL_VF_FLR_EVENT_ID_VF_FLR UINT32_C(0x30)
8743 #define HWRM_ASYNC_EVENT_CMPL_VF_FLR_EVENT_ID_LAST \
8744 HWRM_ASYNC_EVENT_CMPL_VF_FLR_EVENT_ID_VF_FLR
8745 /* Event specific data */
8746 uint32_t event_data2;
8749 * This value is written by the NIC such that it will be different
8750 * for each pass through the completion queue. The even passes
8751 * will write 1. The odd passes will write 0.
8753 #define HWRM_ASYNC_EVENT_CMPL_VF_FLR_V UINT32_C(0x1)
8755 #define HWRM_ASYNC_EVENT_CMPL_VF_FLR_OPAQUE_MASK UINT32_C(0xfe)
8756 #define HWRM_ASYNC_EVENT_CMPL_VF_FLR_OPAQUE_SFT 1
8757 /* 8-lsb timestamp from POR (100-msec resolution) */
8758 uint8_t timestamp_lo;
8759 /* 16-lsb timestamp from POR (100-msec resolution) */
8760 uint16_t timestamp_hi;
8761 /* Event specific data */
8762 uint32_t event_data1;
8764 #define HWRM_ASYNC_EVENT_CMPL_VF_FLR_EVENT_DATA1_VF_ID_MASK \
8766 #define HWRM_ASYNC_EVENT_CMPL_VF_FLR_EVENT_DATA1_VF_ID_SFT 0
8767 /* Indicates the physical function this event occurred on. */
8768 #define HWRM_ASYNC_EVENT_CMPL_VF_FLR_EVENT_DATA1_PF_ID_MASK \
8770 #define HWRM_ASYNC_EVENT_CMPL_VF_FLR_EVENT_DATA1_PF_ID_SFT 16
8773 /* hwrm_async_event_cmpl_vf_mac_addr_change (size:128b/16B) */
8774 struct hwrm_async_event_cmpl_vf_mac_addr_change {
8777 * This field indicates the exact type of the completion.
8778 * By convention, the LSB identifies the length of the
8779 * record in 16B units. Even values indicate 16B
8780 * records. Odd values indicate 32B
8783 #define HWRM_ASYNC_EVENT_CMPL_VF_MAC_ADDR_CHANGE_TYPE_MASK \
8785 #define HWRM_ASYNC_EVENT_CMPL_VF_MAC_ADDR_CHANGE_TYPE_SFT 0
8786 /* HWRM Asynchronous Event Information */
8787 #define HWRM_ASYNC_EVENT_CMPL_VF_MAC_ADDR_CHANGE_TYPE_HWRM_ASYNC_EVENT \
8789 #define HWRM_ASYNC_EVENT_CMPL_VF_MAC_ADDR_CHANGE_TYPE_LAST \
8790 HWRM_ASYNC_EVENT_CMPL_VF_MAC_ADDR_CHANGE_TYPE_HWRM_ASYNC_EVENT
8791 /* Identifiers of events. */
8793 /* VF MAC Address Change */
8794 #define HWRM_ASYNC_EVENT_CMPL_VF_MAC_ADDR_CHANGE_EVENT_ID_VF_MAC_ADDR_CHANGE \
8796 #define HWRM_ASYNC_EVENT_CMPL_VF_MAC_ADDR_CHANGE_EVENT_ID_LAST \
8797 HWRM_ASYNC_EVENT_CMPL_VF_MAC_ADDR_CHANGE_EVENT_ID_VF_MAC_ADDR_CHANGE
8798 /* Event specific data */
8799 uint32_t event_data2;
8802 * This value is written by the NIC such that it will be different
8803 * for each pass through the completion queue. The even passes
8804 * will write 1. The odd passes will write 0.
8806 #define HWRM_ASYNC_EVENT_CMPL_VF_MAC_ADDR_CHANGE_V \
8809 #define HWRM_ASYNC_EVENT_CMPL_VF_MAC_ADDR_CHANGE_OPAQUE_MASK \
8811 #define HWRM_ASYNC_EVENT_CMPL_VF_MAC_ADDR_CHANGE_OPAQUE_SFT 1
8812 /* 8-lsb timestamp from POR (100-msec resolution) */
8813 uint8_t timestamp_lo;
8814 /* 16-lsb timestamp from POR (100-msec resolution) */
8815 uint16_t timestamp_hi;
8816 /* Event specific data */
8817 uint32_t event_data1;
8819 #define HWRM_ASYNC_EVENT_CMPL_VF_MAC_ADDR_CHANGE_EVENT_DATA1_VF_ID_MASK \
8821 #define HWRM_ASYNC_EVENT_CMPL_VF_MAC_ADDR_CHANGE_EVENT_DATA1_VF_ID_SFT \
8825 /* hwrm_async_event_cmpl_pf_vf_comm_status_change (size:128b/16B) */
8826 struct hwrm_async_event_cmpl_pf_vf_comm_status_change {
8829 * This field indicates the exact type of the completion.
8830 * By convention, the LSB identifies the length of the
8831 * record in 16B units. Even values indicate 16B
8832 * records. Odd values indicate 32B
8835 #define HWRM_ASYNC_EVENT_CMPL_PF_VF_COMM_STATUS_CHANGE_TYPE_MASK \
8837 #define HWRM_ASYNC_EVENT_CMPL_PF_VF_COMM_STATUS_CHANGE_TYPE_SFT \
8839 /* HWRM Asynchronous Event Information */
8840 #define HWRM_ASYNC_EVENT_CMPL_PF_VF_COMM_STATUS_CHANGE_TYPE_HWRM_ASYNC_EVENT \
8842 #define HWRM_ASYNC_EVENT_CMPL_PF_VF_COMM_STATUS_CHANGE_TYPE_LAST \
8843 HWRM_ASYNC_EVENT_CMPL_PF_VF_COMM_STATUS_CHANGE_TYPE_HWRM_ASYNC_EVENT
8844 /* Identifiers of events. */
8846 /* PF-VF communication channel status change. */
8847 #define HWRM_ASYNC_EVENT_CMPL_PF_VF_COMM_STATUS_CHANGE_EVENT_ID_PF_VF_COMM_STATUS_CHANGE \
8849 #define HWRM_ASYNC_EVENT_CMPL_PF_VF_COMM_STATUS_CHANGE_EVENT_ID_LAST \
8850 HWRM_ASYNC_EVENT_CMPL_PF_VF_COMM_STATUS_CHANGE_EVENT_ID_PF_VF_COMM_STATUS_CHANGE
8851 /* Event specific data */
8852 uint32_t event_data2;
8855 * This value is written by the NIC such that it will be different
8856 * for each pass through the completion queue. The even passes
8857 * will write 1. The odd passes will write 0.
8859 #define HWRM_ASYNC_EVENT_CMPL_PF_VF_COMM_STATUS_CHANGE_V \
8862 #define HWRM_ASYNC_EVENT_CMPL_PF_VF_COMM_STATUS_CHANGE_OPAQUE_MASK \
8864 #define HWRM_ASYNC_EVENT_CMPL_PF_VF_COMM_STATUS_CHANGE_OPAQUE_SFT 1
8865 /* 8-lsb timestamp from POR (100-msec resolution) */
8866 uint8_t timestamp_lo;
8867 /* 16-lsb timestamp from POR (100-msec resolution) */
8868 uint16_t timestamp_hi;
8869 /* Event specific data */
8870 uint32_t event_data1;
8872 * If this bit is set to 1, then it indicates that the PF-VF
8873 * communication was lost and it is established.
8874 * If this bit set to 0, then it indicates that the PF-VF
8875 * communication was established and it is lost.
8877 #define HWRM_ASYNC_EVENT_CMPL_PF_VF_COMM_STATUS_CHANGE_EVENT_DATA1_COMM_ESTABLISHED \
8881 /* hwrm_async_event_cmpl_vf_cfg_change (size:128b/16B) */
8882 struct hwrm_async_event_cmpl_vf_cfg_change {
8885 * This field indicates the exact type of the completion.
8886 * By convention, the LSB identifies the length of the
8887 * record in 16B units. Even values indicate 16B
8888 * records. Odd values indicate 32B
8891 #define HWRM_ASYNC_EVENT_CMPL_VF_CFG_CHANGE_TYPE_MASK \
8893 #define HWRM_ASYNC_EVENT_CMPL_VF_CFG_CHANGE_TYPE_SFT 0
8894 /* HWRM Asynchronous Event Information */
8895 #define HWRM_ASYNC_EVENT_CMPL_VF_CFG_CHANGE_TYPE_HWRM_ASYNC_EVENT \
8897 #define HWRM_ASYNC_EVENT_CMPL_VF_CFG_CHANGE_TYPE_LAST \
8898 HWRM_ASYNC_EVENT_CMPL_VF_CFG_CHANGE_TYPE_HWRM_ASYNC_EVENT
8899 /* Identifiers of events. */
8901 /* VF Configuration Change */
8902 #define HWRM_ASYNC_EVENT_CMPL_VF_CFG_CHANGE_EVENT_ID_VF_CFG_CHANGE \
8904 #define HWRM_ASYNC_EVENT_CMPL_VF_CFG_CHANGE_EVENT_ID_LAST \
8905 HWRM_ASYNC_EVENT_CMPL_VF_CFG_CHANGE_EVENT_ID_VF_CFG_CHANGE
8906 /* Event specific data */
8907 uint32_t event_data2;
8909 * This value indicates the VF ID of the VF whose configuration
8910 * is changing if this async. event is sent to the parent PF.
8911 * The firmware supports sending this to the parent PF if the
8912 * `hwrm_func_qcaps.vf_cfg_async_for_pf_supported` value is 1.
8913 * This value is undefined when the async. event is sent to the
8916 #define HWRM_ASYNC_EVENT_CMPL_VF_CFG_CHANGE_EVENT_DATA2_VF_ID_MASK \
8918 #define HWRM_ASYNC_EVENT_CMPL_VF_CFG_CHANGE_EVENT_DATA2_VF_ID_SFT 0
8921 * This value is written by the NIC such that it will be different
8922 * for each pass through the completion queue. The even passes
8923 * will write 1. The odd passes will write 0.
8925 #define HWRM_ASYNC_EVENT_CMPL_VF_CFG_CHANGE_V UINT32_C(0x1)
8927 #define HWRM_ASYNC_EVENT_CMPL_VF_CFG_CHANGE_OPAQUE_MASK UINT32_C(0xfe)
8928 #define HWRM_ASYNC_EVENT_CMPL_VF_CFG_CHANGE_OPAQUE_SFT 1
8929 /* 8-lsb timestamp from POR (100-msec resolution) */
8930 uint8_t timestamp_lo;
8931 /* 16-lsb timestamp from POR (100-msec resolution) */
8932 uint16_t timestamp_hi;
8934 * Each flag provided in this field indicates a specific VF
8935 * configuration change. At least one of these flags shall be set to 1
8936 * when an asynchronous event completion of this type is provided
8939 uint32_t event_data1;
8941 * If this bit is set to 1, then the value of MTU
8942 * was changed on this VF.
8943 * If set to 0, then this bit should be ignored.
8945 #define HWRM_ASYNC_EVENT_CMPL_VF_CFG_CHANGE_EVENT_DATA1_MTU_CHANGE \
8948 * If this bit is set to 1, then the value of MRU
8949 * was changed on this VF.
8950 * If set to 0, then this bit should be ignored.
8952 #define HWRM_ASYNC_EVENT_CMPL_VF_CFG_CHANGE_EVENT_DATA1_MRU_CHANGE \
8955 * If this bit is set to 1, then the value of default MAC
8956 * address was changed on this VF.
8957 * If set to 0, then this bit should be ignored.
8959 #define HWRM_ASYNC_EVENT_CMPL_VF_CFG_CHANGE_EVENT_DATA1_DFLT_MAC_ADDR_CHANGE \
8962 * If this bit is set to 1, then the value of default VLAN
8963 * was changed on this VF.
8964 * If set to 0, then this bit should be ignored.
8966 #define HWRM_ASYNC_EVENT_CMPL_VF_CFG_CHANGE_EVENT_DATA1_DFLT_VLAN_CHANGE \
8969 * If this bit is set to 1, then the value of trusted VF enable
8970 * was changed on this VF.
8971 * If set to 0, then this bit should be ignored.
8973 #define HWRM_ASYNC_EVENT_CMPL_VF_CFG_CHANGE_EVENT_DATA1_TRUSTED_VF_CFG_CHANGE \
8977 /* hwrm_async_event_cmpl_llfc_pfc_change (size:128b/16B) */
8978 struct hwrm_async_event_cmpl_llfc_pfc_change {
8981 * This field indicates the exact type of the completion.
8982 * By convention, the LSB identifies the length of the
8983 * record in 16B units. Even values indicate 16B
8984 * records. Odd values indicate 32B
8987 #define HWRM_ASYNC_EVENT_CMPL_LLFC_PFC_CHANGE_TYPE_MASK \
8989 #define HWRM_ASYNC_EVENT_CMPL_LLFC_PFC_CHANGE_TYPE_SFT 0
8990 /* HWRM Asynchronous Event Information */
8991 #define HWRM_ASYNC_EVENT_CMPL_LLFC_PFC_CHANGE_TYPE_HWRM_ASYNC_EVENT \
8993 #define HWRM_ASYNC_EVENT_CMPL_LLFC_PFC_CHANGE_TYPE_LAST \
8994 HWRM_ASYNC_EVENT_CMPL_LLFC_PFC_CHANGE_TYPE_HWRM_ASYNC_EVENT
8995 /* unused1 is 10 b */
8996 #define HWRM_ASYNC_EVENT_CMPL_LLFC_PFC_CHANGE_UNUSED1_MASK \
8998 #define HWRM_ASYNC_EVENT_CMPL_LLFC_PFC_CHANGE_UNUSED1_SFT 6
8999 /* Identifiers of events. */
9001 /* LLFC/PFC Configuration Change */
9002 #define HWRM_ASYNC_EVENT_CMPL_LLFC_PFC_CHANGE_EVENT_ID_LLFC_PFC_CHANGE \
9004 #define HWRM_ASYNC_EVENT_CMPL_LLFC_PFC_CHANGE_EVENT_ID_LAST \
9005 HWRM_ASYNC_EVENT_CMPL_LLFC_PFC_CHANGE_EVENT_ID_LLFC_PFC_CHANGE
9006 /* Event specific data */
9007 uint32_t event_data2;
9010 * This value is written by the NIC such that it will be different
9011 * for each pass through the completion queue. The even passes
9012 * will write 1. The odd passes will write 0.
9014 #define HWRM_ASYNC_EVENT_CMPL_LLFC_PFC_CHANGE_V UINT32_C(0x1)
9016 #define HWRM_ASYNC_EVENT_CMPL_LLFC_PFC_CHANGE_OPAQUE_MASK \
9018 #define HWRM_ASYNC_EVENT_CMPL_LLFC_PFC_CHANGE_OPAQUE_SFT 1
9019 /* 8-lsb timestamp from POR (100-msec resolution) */
9020 uint8_t timestamp_lo;
9021 /* 16-lsb timestamp from POR (100-msec resolution) */
9022 uint16_t timestamp_hi;
9023 /* Event specific data */
9024 uint32_t event_data1;
9025 /* Indicates llfc pfc status change */
9026 #define HWRM_ASYNC_EVENT_CMPL_LLFC_PFC_CHANGE_EVENT_DATA1_LLFC_PFC_MASK \
9028 #define HWRM_ASYNC_EVENT_CMPL_LLFC_PFC_CHANGE_EVENT_DATA1_LLFC_PFC_SFT \
9031 * If this field set to 1, then it indicates that llfc is
9034 #define HWRM_ASYNC_EVENT_CMPL_LLFC_PFC_CHANGE_EVENT_DATA1_LLFC_PFC_LLFC \
9037 * If this field is set to 2, then it indicates that pfc
9040 #define HWRM_ASYNC_EVENT_CMPL_LLFC_PFC_CHANGE_EVENT_DATA1_LLFC_PFC_PFC \
9042 #define HWRM_ASYNC_EVENT_CMPL_LLFC_PFC_CHANGE_EVENT_DATA1_LLFC_PFC_LAST \
9043 HWRM_ASYNC_EVENT_CMPL_LLFC_PFC_CHANGE_EVENT_DATA1_LLFC_PFC_PFC
9044 /* Indicates the physical port this llfc pfc change occur */
9045 #define HWRM_ASYNC_EVENT_CMPL_LLFC_PFC_CHANGE_EVENT_DATA1_PORT_MASK \
9047 #define HWRM_ASYNC_EVENT_CMPL_LLFC_PFC_CHANGE_EVENT_DATA1_PORT_SFT \
9050 #define HWRM_ASYNC_EVENT_CMPL_LLFC_PFC_CHANGE_EVENT_DATA1_PORT_ID_MASK \
9052 #define HWRM_ASYNC_EVENT_CMPL_LLFC_PFC_CHANGE_EVENT_DATA1_PORT_ID_SFT \
9056 /* hwrm_async_event_cmpl_default_vnic_change (size:128b/16B) */
9057 struct hwrm_async_event_cmpl_default_vnic_change {
9060 * This field indicates the exact type of the completion.
9061 * By convention, the LSB identifies the length of the
9062 * record in 16B units. Even values indicate 16B
9063 * records. Odd values indicate 32B
9066 #define HWRM_ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_TYPE_MASK \
9068 #define HWRM_ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_TYPE_SFT \
9070 /* HWRM Asynchronous Event Information */
9071 #define HWRM_ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_TYPE_HWRM_ASYNC_EVENT \
9073 #define HWRM_ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_TYPE_LAST \
9074 HWRM_ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_TYPE_HWRM_ASYNC_EVENT
9075 /* unused1 is 10 b */
9076 #define HWRM_ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_UNUSED1_MASK \
9078 #define HWRM_ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_UNUSED1_SFT \
9080 /* Identifiers of events. */
9082 /* Notification of a default vnic allocation or free */
9083 #define HWRM_ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_EVENT_ID_ALLOC_FREE_NOTIFICATION \
9085 #define HWRM_ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_EVENT_ID_LAST \
9086 HWRM_ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_EVENT_ID_ALLOC_FREE_NOTIFICATION
9087 /* Event specific data */
9088 uint32_t event_data2;
9091 * This value is written by the NIC such that it will be different
9092 * for each pass through the completion queue. The even passes
9093 * will write 1. The odd passes will write 0.
9095 #define HWRM_ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_V \
9098 #define HWRM_ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_OPAQUE_MASK \
9100 #define HWRM_ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_OPAQUE_SFT 1
9101 /* 8-lsb timestamp from POR (100-msec resolution) */
9102 uint8_t timestamp_lo;
9103 /* 16-lsb timestamp from POR (100-msec resolution) */
9104 uint16_t timestamp_hi;
9105 /* Event specific data */
9106 uint32_t event_data1;
9107 /* Indicates default vnic configuration change */
9108 #define HWRM_ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_EVENT_DATA1_DEF_VNIC_STATE_MASK \
9110 #define HWRM_ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_EVENT_DATA1_DEF_VNIC_STATE_SFT \
9113 * If this field is set to 1, then it indicates that
9114 * a default VNIC has been allocate.
9116 #define HWRM_ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_EVENT_DATA1_DEF_VNIC_STATE_DEF_VNIC_ALLOC \
9119 * If this field is set to 2, then it indicates that
9120 * a default VNIC has been freed.
9122 #define HWRM_ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_EVENT_DATA1_DEF_VNIC_STATE_DEF_VNIC_FREE \
9124 #define HWRM_ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_EVENT_DATA1_DEF_VNIC_STATE_LAST \
9125 HWRM_ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_EVENT_DATA1_DEF_VNIC_STATE_DEF_VNIC_FREE
9126 /* Indicates the physical function this event occurred on. */
9127 #define HWRM_ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_EVENT_DATA1_PF_ID_MASK \
9129 #define HWRM_ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_EVENT_DATA1_PF_ID_SFT \
9131 /* Indicates the virtual function this event occurred on */
9132 #define HWRM_ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_EVENT_DATA1_VF_ID_MASK \
9134 #define HWRM_ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_EVENT_DATA1_VF_ID_SFT \
9138 /* hwrm_async_event_cmpl_hw_flow_aged (size:128b/16B) */
9139 struct hwrm_async_event_cmpl_hw_flow_aged {
9142 * This field indicates the exact type of the completion.
9143 * By convention, the LSB identifies the length of the
9144 * record in 16B units. Even values indicate 16B
9145 * records. Odd values indicate 32B
9148 #define HWRM_ASYNC_EVENT_CMPL_HW_FLOW_AGED_TYPE_MASK \
9150 #define HWRM_ASYNC_EVENT_CMPL_HW_FLOW_AGED_TYPE_SFT 0
9151 /* HWRM Asynchronous Event Information */
9152 #define HWRM_ASYNC_EVENT_CMPL_HW_FLOW_AGED_TYPE_HWRM_ASYNC_EVENT \
9154 #define HWRM_ASYNC_EVENT_CMPL_HW_FLOW_AGED_TYPE_LAST \
9155 HWRM_ASYNC_EVENT_CMPL_HW_FLOW_AGED_TYPE_HWRM_ASYNC_EVENT
9156 /* Identifiers of events. */
9158 /* Notification of a hw flow aged */
9159 #define HWRM_ASYNC_EVENT_CMPL_HW_FLOW_AGED_EVENT_ID_HW_FLOW_AGED \
9161 #define HWRM_ASYNC_EVENT_CMPL_HW_FLOW_AGED_EVENT_ID_LAST \
9162 HWRM_ASYNC_EVENT_CMPL_HW_FLOW_AGED_EVENT_ID_HW_FLOW_AGED
9163 /* Event specific data */
9164 uint32_t event_data2;
9167 * This value is written by the NIC such that it will be different
9168 * for each pass through the completion queue. The even passes
9169 * will write 1. The odd passes will write 0.
9171 #define HWRM_ASYNC_EVENT_CMPL_HW_FLOW_AGED_V UINT32_C(0x1)
9173 #define HWRM_ASYNC_EVENT_CMPL_HW_FLOW_AGED_OPAQUE_MASK UINT32_C(0xfe)
9174 #define HWRM_ASYNC_EVENT_CMPL_HW_FLOW_AGED_OPAQUE_SFT 1
9175 /* 8-lsb timestamp from POR (100-msec resolution) */
9176 uint8_t timestamp_lo;
9177 /* 16-lsb timestamp from POR (100-msec resolution) */
9178 uint16_t timestamp_hi;
9179 /* Event specific data */
9180 uint32_t event_data1;
9181 /* Indicates flow ID this event occurred on. */
9182 #define HWRM_ASYNC_EVENT_CMPL_HW_FLOW_AGED_EVENT_DATA1_FLOW_ID_MASK \
9183 UINT32_C(0x7fffffff)
9184 #define HWRM_ASYNC_EVENT_CMPL_HW_FLOW_AGED_EVENT_DATA1_FLOW_ID_SFT \
9186 /* Indicates flow direction this event occurred on. */
9187 #define HWRM_ASYNC_EVENT_CMPL_HW_FLOW_AGED_EVENT_DATA1_FLOW_DIRECTION \
9188 UINT32_C(0x80000000)
9190 * If this bit set to 0, then it indicates that the aged
9191 * event was rx flow.
9193 #define HWRM_ASYNC_EVENT_CMPL_HW_FLOW_AGED_EVENT_DATA1_FLOW_DIRECTION_RX \
9194 (UINT32_C(0x0) << 31)
9196 * If this bit is set to 1, then it indicates that the aged
9197 * event was tx flow.
9199 #define HWRM_ASYNC_EVENT_CMPL_HW_FLOW_AGED_EVENT_DATA1_FLOW_DIRECTION_TX \
9200 (UINT32_C(0x1) << 31)
9201 #define HWRM_ASYNC_EVENT_CMPL_HW_FLOW_AGED_EVENT_DATA1_FLOW_DIRECTION_LAST \
9202 HWRM_ASYNC_EVENT_CMPL_HW_FLOW_AGED_EVENT_DATA1_FLOW_DIRECTION_TX
9205 /* hwrm_async_event_cmpl_eem_cache_flush_req (size:128b/16B) */
9206 struct hwrm_async_event_cmpl_eem_cache_flush_req {
9209 * This field indicates the exact type of the completion.
9210 * By convention, the LSB identifies the length of the
9211 * record in 16B units. Even values indicate 16B
9212 * records. Odd values indicate 32B
9215 #define HWRM_ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_REQ_TYPE_MASK \
9217 #define HWRM_ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_REQ_TYPE_SFT \
9219 /* HWRM Asynchronous Event Information */
9220 #define HWRM_ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_REQ_TYPE_HWRM_ASYNC_EVENT \
9222 #define HWRM_ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_REQ_TYPE_LAST \
9223 HWRM_ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_REQ_TYPE_HWRM_ASYNC_EVENT
9224 /* Identifiers of events. */
9226 /* Notification of a eem_cache_flush request */
9227 #define HWRM_ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_REQ_EVENT_ID_EEM_CACHE_FLUSH_REQ \
9229 #define HWRM_ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_REQ_EVENT_ID_LAST \
9230 HWRM_ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_REQ_EVENT_ID_EEM_CACHE_FLUSH_REQ
9231 /* Event specific data */
9232 uint32_t event_data2;
9235 * This value is written by the NIC such that it will be different
9236 * for each pass through the completion queue. The even passes
9237 * will write 1. The odd passes will write 0.
9239 #define HWRM_ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_REQ_V \
9242 #define HWRM_ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_REQ_OPAQUE_MASK \
9244 #define HWRM_ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_REQ_OPAQUE_SFT 1
9245 /* 8-lsb timestamp from POR (100-msec resolution) */
9246 uint8_t timestamp_lo;
9247 /* 16-lsb timestamp from POR (100-msec resolution) */
9248 uint16_t timestamp_hi;
9249 /* Event specific data */
9250 uint32_t event_data1;
9253 /* hwrm_async_event_cmpl_eem_cache_flush_done (size:128b/16B) */
9254 struct hwrm_async_event_cmpl_eem_cache_flush_done {
9257 * This field indicates the exact type of the completion.
9258 * By convention, the LSB identifies the length of the
9259 * record in 16B units. Even values indicate 16B
9260 * records. Odd values indicate 32B
9263 #define HWRM_ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_DONE_TYPE_MASK \
9265 #define HWRM_ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_DONE_TYPE_SFT \
9267 /* HWRM Asynchronous Event Information */
9268 #define HWRM_ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_DONE_TYPE_HWRM_ASYNC_EVENT \
9270 #define HWRM_ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_DONE_TYPE_LAST \
9271 HWRM_ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_DONE_TYPE_HWRM_ASYNC_EVENT
9272 /* Identifiers of events. */
9275 * Notification of a host eem_cache_flush has completed. This event
9276 * is generated by the host driver.
9278 #define HWRM_ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_DONE_EVENT_ID_EEM_CACHE_FLUSH_DONE \
9280 #define HWRM_ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_DONE_EVENT_ID_LAST \
9281 HWRM_ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_DONE_EVENT_ID_EEM_CACHE_FLUSH_DONE
9282 /* Event specific data */
9283 uint32_t event_data2;
9286 * This value is written by the NIC such that it will be different
9287 * for each pass through the completion queue. The even passes
9288 * will write 1. The odd passes will write 0.
9290 #define HWRM_ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_DONE_V \
9293 #define HWRM_ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_DONE_OPAQUE_MASK \
9295 #define HWRM_ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_DONE_OPAQUE_SFT 1
9296 /* 8-lsb timestamp from POR (100-msec resolution) */
9297 uint8_t timestamp_lo;
9298 /* 16-lsb timestamp from POR (100-msec resolution) */
9299 uint16_t timestamp_hi;
9300 /* Event specific data */
9301 uint32_t event_data1;
9302 /* Indicates function ID that this event occurred on. */
9303 #define HWRM_ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_DONE_EVENT_DATA1_FID_MASK \
9305 #define HWRM_ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_DONE_EVENT_DATA1_FID_SFT \
9309 /* hwrm_async_event_cmpl_tcp_flag_action_change (size:128b/16B) */
9310 struct hwrm_async_event_cmpl_tcp_flag_action_change {
9313 * This field indicates the exact type of the completion.
9314 * By convention, the LSB identifies the length of the
9315 * record in 16B units. Even values indicate 16B
9316 * records. Odd values indicate 32B
9319 #define HWRM_ASYNC_EVENT_CMPL_TCP_FLAG_ACTION_CHANGE_TYPE_MASK \
9321 #define HWRM_ASYNC_EVENT_CMPL_TCP_FLAG_ACTION_CHANGE_TYPE_SFT \
9323 /* HWRM Asynchronous Event Information */
9324 #define HWRM_ASYNC_EVENT_CMPL_TCP_FLAG_ACTION_CHANGE_TYPE_HWRM_ASYNC_EVENT \
9326 #define HWRM_ASYNC_EVENT_CMPL_TCP_FLAG_ACTION_CHANGE_TYPE_LAST \
9327 HWRM_ASYNC_EVENT_CMPL_TCP_FLAG_ACTION_CHANGE_TYPE_HWRM_ASYNC_EVENT
9328 /* Identifiers of events. */
9330 /* Notification of tcp flag action change */
9331 #define HWRM_ASYNC_EVENT_CMPL_TCP_FLAG_ACTION_CHANGE_EVENT_ID_TCP_FLAG_ACTION_CHANGE \
9333 #define HWRM_ASYNC_EVENT_CMPL_TCP_FLAG_ACTION_CHANGE_EVENT_ID_LAST \
9334 HWRM_ASYNC_EVENT_CMPL_TCP_FLAG_ACTION_CHANGE_EVENT_ID_TCP_FLAG_ACTION_CHANGE
9335 /* Event specific data */
9336 uint32_t event_data2;
9339 * This value is written by the NIC such that it will be different
9340 * for each pass through the completion queue. The even passes
9341 * will write 1. The odd passes will write 0.
9343 #define HWRM_ASYNC_EVENT_CMPL_TCP_FLAG_ACTION_CHANGE_V \
9346 #define HWRM_ASYNC_EVENT_CMPL_TCP_FLAG_ACTION_CHANGE_OPAQUE_MASK \
9348 #define HWRM_ASYNC_EVENT_CMPL_TCP_FLAG_ACTION_CHANGE_OPAQUE_SFT 1
9349 /* 8-lsb timestamp from POR (100-msec resolution) */
9350 uint8_t timestamp_lo;
9351 /* 16-lsb timestamp from POR (100-msec resolution) */
9352 uint16_t timestamp_hi;
9353 /* Event specific data */
9354 uint32_t event_data1;
9357 /* hwrm_async_event_cmpl_eem_flow_active (size:128b/16B) */
9358 struct hwrm_async_event_cmpl_eem_flow_active {
9361 * This field indicates the exact type of the completion.
9362 * By convention, the LSB identifies the length of the
9363 * record in 16B units. Even values indicate 16B
9364 * records. Odd values indicate 32B
9367 #define HWRM_ASYNC_EVENT_CMPL_EEM_FLOW_ACTIVE_TYPE_MASK \
9369 #define HWRM_ASYNC_EVENT_CMPL_EEM_FLOW_ACTIVE_TYPE_SFT 0
9370 /* HWRM Asynchronous Event Information */
9371 #define HWRM_ASYNC_EVENT_CMPL_EEM_FLOW_ACTIVE_TYPE_HWRM_ASYNC_EVENT \
9373 #define HWRM_ASYNC_EVENT_CMPL_EEM_FLOW_ACTIVE_TYPE_LAST \
9374 HWRM_ASYNC_EVENT_CMPL_EEM_FLOW_ACTIVE_TYPE_HWRM_ASYNC_EVENT
9375 /* Identifiers of events. */
9377 /* Notification of an active eem flow */
9378 #define HWRM_ASYNC_EVENT_CMPL_EEM_FLOW_ACTIVE_EVENT_ID_EEM_FLOW_ACTIVE \
9380 #define HWRM_ASYNC_EVENT_CMPL_EEM_FLOW_ACTIVE_EVENT_ID_LAST \
9381 HWRM_ASYNC_EVENT_CMPL_EEM_FLOW_ACTIVE_EVENT_ID_EEM_FLOW_ACTIVE
9382 /* Event specific data */
9383 uint32_t event_data2;
9384 /* Indicates the 2nd global id this event occurred on. */
9385 #define HWRM_ASYNC_EVENT_CMPL_EEM_FLOW_ACTIVE_EVENT_DATA2_GLOBAL_ID_2_MASK \
9386 UINT32_C(0x3fffffff)
9387 #define HWRM_ASYNC_EVENT_CMPL_EEM_FLOW_ACTIVE_EVENT_DATA2_GLOBAL_ID_2_SFT \
9390 * Indicates flow direction of the flow identified by
9393 #define HWRM_ASYNC_EVENT_CMPL_EEM_FLOW_ACTIVE_EVENT_DATA2_FLOW_DIRECTION \
9394 UINT32_C(0x40000000)
9395 /* If this bit is set to 0, then it indicates that this rx flow. */
9396 #define HWRM_ASYNC_EVENT_CMPL_EEM_FLOW_ACTIVE_EVENT_DATA2_FLOW_DIRECTION_RX \
9397 (UINT32_C(0x0) << 30)
9398 /* If this bit is set to 1, then it indicates that this tx flow. */
9399 #define HWRM_ASYNC_EVENT_CMPL_EEM_FLOW_ACTIVE_EVENT_DATA2_FLOW_DIRECTION_TX \
9400 (UINT32_C(0x1) << 30)
9401 #define HWRM_ASYNC_EVENT_CMPL_EEM_FLOW_ACTIVE_EVENT_DATA2_FLOW_DIRECTION_LAST \
9402 HWRM_ASYNC_EVENT_CMPL_EEM_FLOW_ACTIVE_EVENT_DATA2_FLOW_DIRECTION_TX
9405 * This value is written by the NIC such that it will be different
9406 * for each pass through the completion queue. The even passes
9407 * will write 1. The odd passes will write 0.
9409 #define HWRM_ASYNC_EVENT_CMPL_EEM_FLOW_ACTIVE_V UINT32_C(0x1)
9411 #define HWRM_ASYNC_EVENT_CMPL_EEM_FLOW_ACTIVE_OPAQUE_MASK \
9413 #define HWRM_ASYNC_EVENT_CMPL_EEM_FLOW_ACTIVE_OPAQUE_SFT 1
9414 /* 8-lsb timestamp from POR (100-msec resolution) */
9415 uint8_t timestamp_lo;
9416 /* 16-lsb timestamp from POR (100-msec resolution) */
9417 uint16_t timestamp_hi;
9418 /* Event specific data */
9419 uint32_t event_data1;
9420 /* Indicates the 1st global id this event occurred on. */
9421 #define HWRM_ASYNC_EVENT_CMPL_EEM_FLOW_ACTIVE_EVENT_DATA1_GLOBAL_ID_1_MASK \
9422 UINT32_C(0x3fffffff)
9423 #define HWRM_ASYNC_EVENT_CMPL_EEM_FLOW_ACTIVE_EVENT_DATA1_GLOBAL_ID_1_SFT \
9426 * Indicates flow direction of the flow identified by the
9429 #define HWRM_ASYNC_EVENT_CMPL_EEM_FLOW_ACTIVE_EVENT_DATA1_FLOW_DIRECTION \
9430 UINT32_C(0x40000000)
9431 /* If this bit is set to 0, then it indicates that this is rx flow. */
9432 #define HWRM_ASYNC_EVENT_CMPL_EEM_FLOW_ACTIVE_EVENT_DATA1_FLOW_DIRECTION_RX \
9433 (UINT32_C(0x0) << 30)
9434 /* If this bit is set to 1, then it indicates that this is tx flow. */
9435 #define HWRM_ASYNC_EVENT_CMPL_EEM_FLOW_ACTIVE_EVENT_DATA1_FLOW_DIRECTION_TX \
9436 (UINT32_C(0x1) << 30)
9437 #define HWRM_ASYNC_EVENT_CMPL_EEM_FLOW_ACTIVE_EVENT_DATA1_FLOW_DIRECTION_LAST \
9438 HWRM_ASYNC_EVENT_CMPL_EEM_FLOW_ACTIVE_EVENT_DATA1_FLOW_DIRECTION_TX
9440 * Indicates EEM flow aging mode this event occurred on. If
9441 * this bit is set to 0, the event_data1 is the EEM global
9442 * ID. If this bit is set to 1, the event_data1 is the number
9443 * of global ID in the context memory.
9445 #define HWRM_ASYNC_EVENT_CMPL_EEM_FLOW_ACTIVE_EVENT_DATA1_MODE \
9446 UINT32_C(0x80000000)
9447 /* EEM flow aging mode 0. */
9448 #define HWRM_ASYNC_EVENT_CMPL_EEM_FLOW_ACTIVE_EVENT_DATA1_MODE_0 \
9449 (UINT32_C(0x0) << 31)
9450 /* EEM flow aging mode 1. */
9451 #define HWRM_ASYNC_EVENT_CMPL_EEM_FLOW_ACTIVE_EVENT_DATA1_MODE_1 \
9452 (UINT32_C(0x1) << 31)
9453 #define HWRM_ASYNC_EVENT_CMPL_EEM_FLOW_ACTIVE_EVENT_DATA1_MODE_LAST \
9454 HWRM_ASYNC_EVENT_CMPL_EEM_FLOW_ACTIVE_EVENT_DATA1_MODE_1
9457 /* hwrm_async_event_cmpl_eem_cfg_change (size:128b/16B) */
9458 struct hwrm_async_event_cmpl_eem_cfg_change {
9461 * This field indicates the exact type of the completion.
9462 * By convention, the LSB identifies the length of the
9463 * record in 16B units. Even values indicate 16B
9464 * records. Odd values indicate 32B
9467 #define HWRM_ASYNC_EVENT_CMPL_EEM_CFG_CHANGE_TYPE_MASK \
9469 #define HWRM_ASYNC_EVENT_CMPL_EEM_CFG_CHANGE_TYPE_SFT 0
9470 /* HWRM Asynchronous Event Information */
9471 #define HWRM_ASYNC_EVENT_CMPL_EEM_CFG_CHANGE_TYPE_HWRM_ASYNC_EVENT \
9473 #define HWRM_ASYNC_EVENT_CMPL_EEM_CFG_CHANGE_TYPE_LAST \
9474 HWRM_ASYNC_EVENT_CMPL_EEM_CFG_CHANGE_TYPE_HWRM_ASYNC_EVENT
9475 /* Identifiers of events. */
9477 /* Notification of EEM configuration change */
9478 #define HWRM_ASYNC_EVENT_CMPL_EEM_CFG_CHANGE_EVENT_ID_EEM_CFG_CHANGE \
9480 #define HWRM_ASYNC_EVENT_CMPL_EEM_CFG_CHANGE_EVENT_ID_LAST \
9481 HWRM_ASYNC_EVENT_CMPL_EEM_CFG_CHANGE_EVENT_ID_EEM_CFG_CHANGE
9482 /* Event specific data */
9483 uint32_t event_data2;
9486 * This value is written by the NIC such that it will be different
9487 * for each pass through the completion queue. The even passes
9488 * will write 1. The odd passes will write 0.
9490 #define HWRM_ASYNC_EVENT_CMPL_EEM_CFG_CHANGE_V UINT32_C(0x1)
9492 #define HWRM_ASYNC_EVENT_CMPL_EEM_CFG_CHANGE_OPAQUE_MASK UINT32_C(0xfe)
9493 #define HWRM_ASYNC_EVENT_CMPL_EEM_CFG_CHANGE_OPAQUE_SFT 1
9494 /* 8-lsb timestamp from POR (100-msec resolution) */
9495 uint8_t timestamp_lo;
9496 /* 16-lsb timestamp from POR (100-msec resolution) */
9497 uint16_t timestamp_hi;
9498 /* Event specific data */
9499 uint32_t event_data1;
9501 * Value of 1 to indicate EEM TX configuration is enabled. Value of
9502 * 0 to indicate the EEM TX configuration is disabled.
9504 #define HWRM_ASYNC_EVENT_CMPL_EEM_CFG_CHANGE_EVENT_DATA1_EEM_TX_ENABLE \
9507 * Value of 1 to indicate EEM RX configuration is enabled. Value of 0
9508 * to indicate the EEM RX configuration is disabled.
9510 #define HWRM_ASYNC_EVENT_CMPL_EEM_CFG_CHANGE_EVENT_DATA1_EEM_RX_ENABLE \
9514 /* hwrm_async_event_cmpl_quiesce_done (size:128b/16B) */
9515 struct hwrm_async_event_cmpl_quiesce_done {
9518 * This field indicates the exact type of the completion.
9519 * By convention, the LSB identifies the length of the
9520 * record in 16B units. Even values indicate 16B
9521 * records. Odd values indicate 32B
9524 #define HWRM_ASYNC_EVENT_CMPL_QUIESCE_DONE_TYPE_MASK \
9526 #define HWRM_ASYNC_EVENT_CMPL_QUIESCE_DONE_TYPE_SFT 0
9527 /* HWRM Asynchronous Event Information */
9528 #define HWRM_ASYNC_EVENT_CMPL_QUIESCE_DONE_TYPE_HWRM_ASYNC_EVENT \
9530 #define HWRM_ASYNC_EVENT_CMPL_QUIESCE_DONE_TYPE_LAST \
9531 HWRM_ASYNC_EVENT_CMPL_QUIESCE_DONE_TYPE_HWRM_ASYNC_EVENT
9532 /* Identifiers of events. */
9534 /* An event signifying completion of HWRM_FW_STATE_QUIESCE */
9535 #define HWRM_ASYNC_EVENT_CMPL_QUIESCE_DONE_EVENT_ID_QUIESCE_DONE \
9537 #define HWRM_ASYNC_EVENT_CMPL_QUIESCE_DONE_EVENT_ID_LAST \
9538 HWRM_ASYNC_EVENT_CMPL_QUIESCE_DONE_EVENT_ID_QUIESCE_DONE
9539 /* Event specific data */
9540 uint32_t event_data2;
9541 /* Status of HWRM_FW_STATE_QUIESCE completion */
9542 #define HWRM_ASYNC_EVENT_CMPL_QUIESCE_DONE_EVENT_DATA2_QUIESCE_STATUS_MASK \
9544 #define HWRM_ASYNC_EVENT_CMPL_QUIESCE_DONE_EVENT_DATA2_QUIESCE_STATUS_SFT \
9547 * The quiesce operation started by HWRM_FW_STATE_QUIESCE
9548 * completed successfully.
9550 #define HWRM_ASYNC_EVENT_CMPL_QUIESCE_DONE_EVENT_DATA2_QUIESCE_STATUS_SUCCESS \
9553 * The quiesce operation started by HWRM_FW_STATE_QUIESCE timed
9556 #define HWRM_ASYNC_EVENT_CMPL_QUIESCE_DONE_EVENT_DATA2_QUIESCE_STATUS_TIMEOUT \
9559 * The quiesce operation started by HWRM_FW_STATE_QUIESCE
9560 * encountered an error.
9562 #define HWRM_ASYNC_EVENT_CMPL_QUIESCE_DONE_EVENT_DATA2_QUIESCE_STATUS_ERROR \
9564 #define HWRM_ASYNC_EVENT_CMPL_QUIESCE_DONE_EVENT_DATA2_QUIESCE_STATUS_LAST \
9565 HWRM_ASYNC_EVENT_CMPL_QUIESCE_DONE_EVENT_DATA2_QUIESCE_STATUS_ERROR
9567 #define HWRM_ASYNC_EVENT_CMPL_QUIESCE_DONE_EVENT_DATA2_OPAQUE_MASK \
9569 #define HWRM_ASYNC_EVENT_CMPL_QUIESCE_DONE_EVENT_DATA2_OPAQUE_SFT \
9572 * Additional information about internal hardware state related to
9573 * idle/quiesce state. QUIESCE may succeed per quiesce_status
9574 * regardless of idle_state_flags. If QUIESCE fails, the host may
9575 * inspect idle_state_flags to determine whether a retry is warranted.
9577 #define HWRM_ASYNC_EVENT_CMPL_QUIESCE_DONE_EVENT_DATA2_IDLE_STATE_FLAGS_MASK \
9579 #define HWRM_ASYNC_EVENT_CMPL_QUIESCE_DONE_EVENT_DATA2_IDLE_STATE_FLAGS_SFT \
9582 * Failure to quiesce is caused by host not updating the NQ consumer
9585 #define HWRM_ASYNC_EVENT_CMPL_QUIESCE_DONE_EVENT_DATA2_IDLE_STATE_FLAGS_INCOMPLETE_NQ \
9587 /* Flag 1 indicating partial non-idle state. */
9588 #define HWRM_ASYNC_EVENT_CMPL_QUIESCE_DONE_EVENT_DATA2_IDLE_STATE_FLAGS_IDLE_STATUS_1 \
9590 /* Flag 2 indicating partial non-idle state. */
9591 #define HWRM_ASYNC_EVENT_CMPL_QUIESCE_DONE_EVENT_DATA2_IDLE_STATE_FLAGS_IDLE_STATUS_2 \
9593 /* Flag 3 indicating partial non-idle state. */
9594 #define HWRM_ASYNC_EVENT_CMPL_QUIESCE_DONE_EVENT_DATA2_IDLE_STATE_FLAGS_IDLE_STATUS_3 \
9598 * This value is written by the NIC such that it will be different
9599 * for each pass through the completion queue. The even passes
9600 * will write 1. The odd passes will write 0.
9602 #define HWRM_ASYNC_EVENT_CMPL_QUIESCE_DONE_V UINT32_C(0x1)
9604 #define HWRM_ASYNC_EVENT_CMPL_QUIESCE_DONE_OPAQUE_MASK UINT32_C(0xfe)
9605 #define HWRM_ASYNC_EVENT_CMPL_QUIESCE_DONE_OPAQUE_SFT 1
9606 /* 8-lsb timestamp from POR (100-msec resolution) */
9607 uint8_t timestamp_lo;
9608 /* 16-lsb timestamp from POR (100-msec resolution) */
9609 uint16_t timestamp_hi;
9610 /* Event specific data */
9611 uint32_t event_data1;
9612 /* Time stamp for error event */
9613 #define HWRM_ASYNC_EVENT_CMPL_QUIESCE_DONE_EVENT_DATA1_TIMESTAMP \
9617 /* hwrm_async_event_cmpl_deferred_response (size:128b/16B) */
9618 struct hwrm_async_event_cmpl_deferred_response {
9621 * This field indicates the exact type of the completion.
9622 * By convention, the LSB identifies the length of the
9623 * record in 16B units. Even values indicate 16B
9624 * records. Odd values indicate 32B
9627 #define HWRM_ASYNC_EVENT_CMPL_DEFERRED_RESPONSE_TYPE_MASK \
9629 #define HWRM_ASYNC_EVENT_CMPL_DEFERRED_RESPONSE_TYPE_SFT 0
9630 /* HWRM Asynchronous Event Information */
9631 #define HWRM_ASYNC_EVENT_CMPL_DEFERRED_RESPONSE_TYPE_HWRM_ASYNC_EVENT \
9633 #define HWRM_ASYNC_EVENT_CMPL_DEFERRED_RESPONSE_TYPE_LAST \
9634 HWRM_ASYNC_EVENT_CMPL_DEFERRED_RESPONSE_TYPE_HWRM_ASYNC_EVENT
9635 /* Identifiers of events. */
9638 * An event signifying a HWRM command is in progress and its
9639 * response will be deferred
9641 #define HWRM_ASYNC_EVENT_CMPL_DEFERRED_RESPONSE_EVENT_ID_DEFERRED_RESPONSE \
9643 #define HWRM_ASYNC_EVENT_CMPL_DEFERRED_RESPONSE_EVENT_ID_LAST \
9644 HWRM_ASYNC_EVENT_CMPL_DEFERRED_RESPONSE_EVENT_ID_DEFERRED_RESPONSE
9645 /* Event specific data */
9646 uint32_t event_data2;
9648 * The PF's mailbox is clear to issue another command.
9649 * A command with this seq_id is still in progress
9650 * and will return a regular HWRM completion when done.
9651 * 'event_data1' field, if non-zero, contains the estimated
9652 * execution time for the command.
9654 #define HWRM_ASYNC_EVENT_CMPL_DEFERRED_RESPONSE_EVENT_DATA2_SEQ_ID_MASK \
9656 #define HWRM_ASYNC_EVENT_CMPL_DEFERRED_RESPONSE_EVENT_DATA2_SEQ_ID_SFT \
9660 * This value is written by the NIC such that it will be different
9661 * for each pass through the completion queue. The even passes
9662 * will write 1. The odd passes will write 0.
9664 #define HWRM_ASYNC_EVENT_CMPL_DEFERRED_RESPONSE_V \
9667 #define HWRM_ASYNC_EVENT_CMPL_DEFERRED_RESPONSE_OPAQUE_MASK \
9669 #define HWRM_ASYNC_EVENT_CMPL_DEFERRED_RESPONSE_OPAQUE_SFT 1
9670 /* 8-lsb timestamp from POR (100-msec resolution) */
9671 uint8_t timestamp_lo;
9672 /* 16-lsb timestamp from POR (100-msec resolution) */
9673 uint16_t timestamp_hi;
9674 /* Estimated remaining time of command execution in ms (if not zero) */
9675 uint32_t event_data1;
9678 /* hwrm_async_event_cmpl_pfc_watchdog_cfg_change (size:128b/16B) */
9679 struct hwrm_async_event_cmpl_pfc_watchdog_cfg_change {
9682 * This field indicates the exact type of the completion.
9683 * By convention, the LSB identifies the length of the
9684 * record in 16B units. Even values indicate 16B
9685 * records. Odd values indicate 32B
9688 #define HWRM_ASYNC_EVENT_CMPL_PFC_WATCHDOG_CFG_CHANGE_TYPE_MASK \
9690 #define HWRM_ASYNC_EVENT_CMPL_PFC_WATCHDOG_CFG_CHANGE_TYPE_SFT \
9692 /* HWRM Asynchronous Event Information */
9693 #define HWRM_ASYNC_EVENT_CMPL_PFC_WATCHDOG_CFG_CHANGE_TYPE_HWRM_ASYNC_EVENT \
9695 #define HWRM_ASYNC_EVENT_CMPL_PFC_WATCHDOG_CFG_CHANGE_TYPE_LAST \
9696 HWRM_ASYNC_EVENT_CMPL_PFC_WATCHDOG_CFG_CHANGE_TYPE_HWRM_ASYNC_EVENT
9697 /* Identifiers of events. */
9699 /* PFC watchdog configuration change for given port/cos */
9700 #define HWRM_ASYNC_EVENT_CMPL_PFC_WATCHDOG_CFG_CHANGE_EVENT_ID_PFC_WATCHDOG_CFG_CHANGE \
9702 #define HWRM_ASYNC_EVENT_CMPL_PFC_WATCHDOG_CFG_CHANGE_EVENT_ID_LAST \
9703 HWRM_ASYNC_EVENT_CMPL_PFC_WATCHDOG_CFG_CHANGE_EVENT_ID_PFC_WATCHDOG_CFG_CHANGE
9704 /* Event specific data */
9705 uint32_t event_data2;
9708 * This value is written by the NIC such that it will be different
9709 * for each pass through the completion queue. The even passes
9710 * will write 1. The odd passes will write 0.
9712 #define HWRM_ASYNC_EVENT_CMPL_PFC_WATCHDOG_CFG_CHANGE_V \
9715 #define HWRM_ASYNC_EVENT_CMPL_PFC_WATCHDOG_CFG_CHANGE_OPAQUE_MASK \
9717 #define HWRM_ASYNC_EVENT_CMPL_PFC_WATCHDOG_CFG_CHANGE_OPAQUE_SFT 1
9718 /* 8-lsb timestamp from POR (100-msec resolution) */
9719 uint8_t timestamp_lo;
9720 /* 16-lsb timestamp from POR (100-msec resolution) */
9721 uint16_t timestamp_hi;
9722 /* Event specific data */
9723 uint32_t event_data1;
9725 * 1 in bit position X indicates PFC watchdog should
9728 #define HWRM_ASYNC_EVENT_CMPL_PFC_WATCHDOG_CFG_CHANGE_EVENT_DATA1_PFC_WD_COS_MASK \
9730 #define HWRM_ASYNC_EVENT_CMPL_PFC_WATCHDOG_CFG_CHANGE_EVENT_DATA1_PFC_WD_COS_SFT \
9732 /* 1 means PFC WD for COS0 is on, 0 - off. */
9733 #define HWRM_ASYNC_EVENT_CMPL_PFC_WATCHDOG_CFG_CHANGE_EVENT_DATA1_PFC_WD_COS_PFC_WD_COS0 \
9735 /* 1 means PFC WD for COS1 is on, 0 - off. */
9736 #define HWRM_ASYNC_EVENT_CMPL_PFC_WATCHDOG_CFG_CHANGE_EVENT_DATA1_PFC_WD_COS_PFC_WD_COS1 \
9738 /* 1 means PFC WD for COS2 is on, 0 - off. */
9739 #define HWRM_ASYNC_EVENT_CMPL_PFC_WATCHDOG_CFG_CHANGE_EVENT_DATA1_PFC_WD_COS_PFC_WD_COS2 \
9741 /* 1 means PFC WD for COS3 is on, 0 - off. */
9742 #define HWRM_ASYNC_EVENT_CMPL_PFC_WATCHDOG_CFG_CHANGE_EVENT_DATA1_PFC_WD_COS_PFC_WD_COS3 \
9744 /* 1 means PFC WD for COS4 is on, 0 - off. */
9745 #define HWRM_ASYNC_EVENT_CMPL_PFC_WATCHDOG_CFG_CHANGE_EVENT_DATA1_PFC_WD_COS_PFC_WD_COS4 \
9747 /* 1 means PFC WD for COS5 is on, 0 - off. */
9748 #define HWRM_ASYNC_EVENT_CMPL_PFC_WATCHDOG_CFG_CHANGE_EVENT_DATA1_PFC_WD_COS_PFC_WD_COS5 \
9750 /* 1 means PFC WD for COS6 is on, 0 - off. */
9751 #define HWRM_ASYNC_EVENT_CMPL_PFC_WATCHDOG_CFG_CHANGE_EVENT_DATA1_PFC_WD_COS_PFC_WD_COS6 \
9753 /* 1 means PFC WD for COS7 is on, 0 - off. */
9754 #define HWRM_ASYNC_EVENT_CMPL_PFC_WATCHDOG_CFG_CHANGE_EVENT_DATA1_PFC_WD_COS_PFC_WD_COS7 \
9757 #define HWRM_ASYNC_EVENT_CMPL_PFC_WATCHDOG_CFG_CHANGE_EVENT_DATA1_PORT_ID_MASK \
9759 #define HWRM_ASYNC_EVENT_CMPL_PFC_WATCHDOG_CFG_CHANGE_EVENT_DATA1_PORT_ID_SFT \
9763 /* hwrm_async_event_cmpl_echo_request (size:128b/16B) */
9764 struct hwrm_async_event_cmpl_echo_request {
9767 * This field indicates the exact type of the completion.
9768 * By convention, the LSB identifies the length of the
9769 * record in 16B units. Even values indicate 16B
9770 * records. Odd values indicate 32B
9773 #define HWRM_ASYNC_EVENT_CMPL_ECHO_REQUEST_TYPE_MASK \
9775 #define HWRM_ASYNC_EVENT_CMPL_ECHO_REQUEST_TYPE_SFT 0
9776 /* HWRM Asynchronous Event Information */
9777 #define HWRM_ASYNC_EVENT_CMPL_ECHO_REQUEST_TYPE_HWRM_ASYNC_EVENT \
9779 #define HWRM_ASYNC_EVENT_CMPL_ECHO_REQUEST_TYPE_LAST \
9780 HWRM_ASYNC_EVENT_CMPL_ECHO_REQUEST_TYPE_HWRM_ASYNC_EVENT
9781 /* Identifiers of events. */
9784 * An echo request from the firmware. An echo response is expected by
9787 #define HWRM_ASYNC_EVENT_CMPL_ECHO_REQUEST_EVENT_ID_ECHO_REQUEST \
9789 #define HWRM_ASYNC_EVENT_CMPL_ECHO_REQUEST_EVENT_ID_LAST \
9790 HWRM_ASYNC_EVENT_CMPL_ECHO_REQUEST_EVENT_ID_ECHO_REQUEST
9791 /* Event specific data that should be provided in the echo response */
9792 uint32_t event_data2;
9795 * This value is written by the NIC such that it will be different
9796 * for each pass through the completion queue. The even passes
9797 * will write 1. The odd passes will write 0.
9799 #define HWRM_ASYNC_EVENT_CMPL_ECHO_REQUEST_V UINT32_C(0x1)
9801 #define HWRM_ASYNC_EVENT_CMPL_ECHO_REQUEST_OPAQUE_MASK UINT32_C(0xfe)
9802 #define HWRM_ASYNC_EVENT_CMPL_ECHO_REQUEST_OPAQUE_SFT 1
9803 /* 8-lsb timestamp from POR (100-msec resolution) */
9804 uint8_t timestamp_lo;
9805 /* 16-lsb timestamp from POR (100-msec resolution) */
9806 uint16_t timestamp_hi;
9807 /* Event specific data that should be provided in the echo response */
9808 uint32_t event_data1;
9811 /* hwrm_async_event_cmpl_phc_master (size:128b/16B) */
9812 struct hwrm_async_event_cmpl_phc_master {
9815 * This field indicates the exact type of the completion.
9816 * By convention, the LSB identifies the length of the
9817 * record in 16B units. Even values indicate 16B
9818 * records. Odd values indicate 32B
9821 #define HWRM_ASYNC_EVENT_CMPL_PHC_MASTER_TYPE_MASK \
9823 #define HWRM_ASYNC_EVENT_CMPL_PHC_MASTER_TYPE_SFT 0
9824 /* HWRM Asynchronous Event Information */
9825 #define HWRM_ASYNC_EVENT_CMPL_PHC_MASTER_TYPE_HWRM_ASYNC_EVENT \
9827 #define HWRM_ASYNC_EVENT_CMPL_PHC_MASTER_TYPE_LAST \
9828 HWRM_ASYNC_EVENT_CMPL_PHC_MASTER_TYPE_HWRM_ASYNC_EVENT
9829 /* Identifiers of events. */
9832 * This async event is used to notify driver of changes
9833 * in PHC master. Only one master function can configure
9836 #define HWRM_ASYNC_EVENT_CMPL_PHC_MASTER_EVENT_ID_PHC_MASTER \
9838 #define HWRM_ASYNC_EVENT_CMPL_PHC_MASTER_EVENT_ID_LAST \
9839 HWRM_ASYNC_EVENT_CMPL_PHC_MASTER_EVENT_ID_PHC_MASTER
9840 /* Event specific data */
9841 uint32_t event_data2;
9842 /* This field provides the current master function. */
9843 #define HWRM_ASYNC_EVENT_CMPL_PHC_MASTER_EVENT_DATA2_PHC_MASTER_FID_MASK \
9845 #define HWRM_ASYNC_EVENT_CMPL_PHC_MASTER_EVENT_DATA2_PHC_MASTER_FID_SFT \
9847 /* This field provides the current secondary function. */
9848 #define HWRM_ASYNC_EVENT_CMPL_PHC_MASTER_EVENT_DATA2_PHC_SEC_FID_MASK \
9849 UINT32_C(0xffff0000)
9850 #define HWRM_ASYNC_EVENT_CMPL_PHC_MASTER_EVENT_DATA2_PHC_SEC_FID_SFT \
9854 * This value is written by the NIC such that it will be different
9855 * for each pass through the completion queue. The even passes
9856 * will write 1. The odd passes will write 0.
9858 #define HWRM_ASYNC_EVENT_CMPL_PHC_MASTER_V UINT32_C(0x1)
9860 #define HWRM_ASYNC_EVENT_CMPL_PHC_MASTER_OPAQUE_MASK UINT32_C(0xfe)
9861 #define HWRM_ASYNC_EVENT_CMPL_PHC_MASTER_OPAQUE_SFT 1
9862 /* 8-lsb timestamp (100-msec resolution) */
9863 uint8_t timestamp_lo;
9864 /* 16-lsb timestamp (100-msec resolution) */
9865 uint16_t timestamp_hi;
9866 /* Event specific data */
9867 uint32_t event_data1;
9868 /* Indicates to the driver the type of PHC event. */
9869 #define HWRM_ASYNC_EVENT_CMPL_PHC_MASTER_EVENT_DATA1_FLAGS_MASK \
9871 #define HWRM_ASYNC_EVENT_CMPL_PHC_MASTER_EVENT_DATA1_FLAGS_SFT \
9874 * Indicates PHC Master selection event. The master fid is
9875 * specified in event_data2.phc_master_fid.
9877 #define HWRM_ASYNC_EVENT_CMPL_PHC_MASTER_EVENT_DATA1_FLAGS_PHC_MASTER \
9880 * Indicates PHC Secondary selection event. The secondary fid is
9881 * specified in event_data2.phc_sec_fid.
9883 #define HWRM_ASYNC_EVENT_CMPL_PHC_MASTER_EVENT_DATA1_FLAGS_PHC_SECONDARY \
9886 * Indicates PHC failover event. Failover happens from
9887 * event_data2.phc_master_fid to event_data2.phc_sec_fid.
9889 #define HWRM_ASYNC_EVENT_CMPL_PHC_MASTER_EVENT_DATA1_FLAGS_PHC_FAILOVER \
9891 #define HWRM_ASYNC_EVENT_CMPL_PHC_MASTER_EVENT_DATA1_FLAGS_LAST \
9892 HWRM_ASYNC_EVENT_CMPL_PHC_MASTER_EVENT_DATA1_FLAGS_PHC_FAILOVER
9895 /* hwrm_async_event_cmpl_pps_timestamp (size:128b/16B) */
9896 struct hwrm_async_event_cmpl_pps_timestamp {
9899 * This field indicates the exact type of the completion.
9900 * By convention, the LSB identifies the length of the
9901 * record in 16B units. Even values indicate 16B
9902 * records. Odd values indicate 32B
9905 #define HWRM_ASYNC_EVENT_CMPL_PPS_TIMESTAMP_TYPE_MASK \
9907 #define HWRM_ASYNC_EVENT_CMPL_PPS_TIMESTAMP_TYPE_SFT 0
9908 /* HWRM Asynchronous Event Information */
9909 #define HWRM_ASYNC_EVENT_CMPL_PPS_TIMESTAMP_TYPE_HWRM_ASYNC_EVENT \
9911 #define HWRM_ASYNC_EVENT_CMPL_PPS_TIMESTAMP_TYPE_LAST \
9912 HWRM_ASYNC_EVENT_CMPL_PPS_TIMESTAMP_TYPE_HWRM_ASYNC_EVENT
9913 /* Identifiers of events. */
9916 * This async notification message can be used to inform
9917 * driver of the latest PPS timestamp that has been latched.
9918 * When driver enables PPS event, Firmware will generate
9919 * PPS timestamps every second, Firmware informs driver
9920 * of this timestamp through the async event.
9922 #define HWRM_ASYNC_EVENT_CMPL_PPS_TIMESTAMP_EVENT_ID_PPS_TIMESTAMP \
9924 #define HWRM_ASYNC_EVENT_CMPL_PPS_TIMESTAMP_EVENT_ID_LAST \
9925 HWRM_ASYNC_EVENT_CMPL_PPS_TIMESTAMP_EVENT_ID_PPS_TIMESTAMP
9926 /* Event specific data */
9927 uint32_t event_data2;
9928 /* Indicates the PPS event type */
9929 #define HWRM_ASYNC_EVENT_CMPL_PPS_TIMESTAMP_EVENT_DATA2_EVENT_TYPE \
9931 /* This is an internal event. */
9932 #define HWRM_ASYNC_EVENT_CMPL_PPS_TIMESTAMP_EVENT_DATA2_EVENT_TYPE_INTERNAL \
9934 /* This is an external event. */
9935 #define HWRM_ASYNC_EVENT_CMPL_PPS_TIMESTAMP_EVENT_DATA2_EVENT_TYPE_EXTERNAL \
9937 #define HWRM_ASYNC_EVENT_CMPL_PPS_TIMESTAMP_EVENT_DATA2_EVENT_TYPE_LAST \
9938 HWRM_ASYNC_EVENT_CMPL_PPS_TIMESTAMP_EVENT_DATA2_EVENT_TYPE_EXTERNAL
9940 * Indicates the pin number on which the event is
9943 #define HWRM_ASYNC_EVENT_CMPL_PPS_TIMESTAMP_EVENT_DATA2_PIN_NUMBER_MASK \
9945 #define HWRM_ASYNC_EVENT_CMPL_PPS_TIMESTAMP_EVENT_DATA2_PIN_NUMBER_SFT \
9948 * Contains bits[47:32] of the upper PPS timestamp.
9949 * Lower 32 bits are in event_data1. Together they
9950 * provide the 48 bit PPS timestamp.
9952 #define HWRM_ASYNC_EVENT_CMPL_PPS_TIMESTAMP_EVENT_DATA2_PPS_TIMESTAMP_UPPER_MASK \
9954 #define HWRM_ASYNC_EVENT_CMPL_PPS_TIMESTAMP_EVENT_DATA2_PPS_TIMESTAMP_UPPER_SFT \
9958 * This value is written by the NIC such that it will be different
9959 * for each pass through the completion queue. The even passes
9960 * will write 1. The odd passes will write 0.
9962 #define HWRM_ASYNC_EVENT_CMPL_PPS_TIMESTAMP_V UINT32_C(0x1)
9964 #define HWRM_ASYNC_EVENT_CMPL_PPS_TIMESTAMP_OPAQUE_MASK UINT32_C(0xfe)
9965 #define HWRM_ASYNC_EVENT_CMPL_PPS_TIMESTAMP_OPAQUE_SFT 1
9966 /* 8-lsb timestamp (100-msec resolution) */
9967 uint8_t timestamp_lo;
9968 /* 16-lsb timestamp (100-msec resolution) */
9969 uint16_t timestamp_hi;
9970 /* Contains the lower 32 bits of the PPS timestamp. */
9971 uint32_t event_data1;
9972 /* Contains the lower 32 bit PPS timestamp */
9973 #define HWRM_ASYNC_EVENT_CMPL_PPS_TIMESTAMP_EVENT_DATA1_PPS_TIMESTAMP_LOWER_MASK \
9974 UINT32_C(0xffffffff)
9975 #define HWRM_ASYNC_EVENT_CMPL_PPS_TIMESTAMP_EVENT_DATA1_PPS_TIMESTAMP_LOWER_SFT \
9979 /* hwrm_async_event_cmpl_error_report (size:128b/16B) */
9980 struct hwrm_async_event_cmpl_error_report {
9983 * This field indicates the exact type of the completion.
9984 * By convention, the LSB identifies the length of the
9985 * record in 16B units. Even values indicate 16B
9986 * records. Odd values indicate 32B
9989 #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_TYPE_MASK \
9991 #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_TYPE_SFT 0
9992 /* HWRM Asynchronous Event Information */
9993 #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_TYPE_HWRM_ASYNC_EVENT \
9995 #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_TYPE_LAST \
9996 HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_TYPE_HWRM_ASYNC_EVENT
9997 /* Identifiers of events. */
10000 * This async notification message is used to inform
10001 * the driver that an error has occurred which may need
10002 * the attention of the administrator.
10004 #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_EVENT_ID_ERROR_REPORT \
10006 #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_EVENT_ID_LAST \
10007 HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_EVENT_ID_ERROR_REPORT
10008 /* Event specific data. */
10009 uint32_t event_data2;
10012 * This value is written by the NIC such that it will be different
10013 * for each pass through the completion queue. The even passes
10014 * will write 1. The odd passes will write 0.
10016 #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_V UINT32_C(0x1)
10017 /* opaque is 7 b */
10018 #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_OPAQUE_MASK UINT32_C(0xfe)
10019 #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_OPAQUE_SFT 1
10020 /* 8-lsb timestamp (100-msec resolution) */
10021 uint8_t timestamp_lo;
10022 /* 16-lsb timestamp (100-msec resolution) */
10023 uint16_t timestamp_hi;
10024 /* Event specific data */
10025 uint32_t event_data1;
10027 * Indicates the type of error being reported. See section on Error
10028 * Report event error_types for details on each error.
10030 #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_EVENT_DATA1_ERROR_TYPE_MASK \
10032 #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_EVENT_DATA1_ERROR_TYPE_SFT 0
10035 /* hwrm_async_event_cmpl_fw_trace_msg (size:128b/16B) */
10036 struct hwrm_async_event_cmpl_fw_trace_msg {
10039 * This field indicates the exact type of the completion.
10040 * By convention, the LSB identifies the length of the
10041 * record in 16B units. Even values indicate 16B
10042 * records. Odd values indicate 32B
10045 #define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_TYPE_MASK \
10047 #define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_TYPE_SFT 0
10048 /* HWRM Asynchronous Event Information */
10049 #define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_TYPE_HWRM_ASYNC_EVENT \
10051 #define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_TYPE_LAST \
10052 HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_TYPE_HWRM_ASYNC_EVENT
10053 /* Identifiers of events. */
10055 /* Firmware trace log message */
10056 #define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_EVENT_ID_FW_TRACE_MSG \
10058 #define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_EVENT_ID_LAST \
10059 HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_EVENT_ID_FW_TRACE_MSG
10060 /* Trace byte 0 to 3 */
10061 uint32_t event_data2;
10063 #define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_EVENT_DATA2_BYTE0_MASK \
10065 #define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_EVENT_DATA2_BYTE0_SFT 0
10067 #define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_EVENT_DATA2_BYTE1_MASK \
10069 #define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_EVENT_DATA2_BYTE1_SFT 8
10071 #define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_EVENT_DATA2_BYTE2_MASK \
10073 #define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_EVENT_DATA2_BYTE2_SFT 16
10075 #define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_EVENT_DATA2_BYTE3_MASK \
10076 UINT32_C(0xff000000)
10077 #define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_EVENT_DATA2_BYTE3_SFT 24
10080 * This value is written by the NIC such that it will be different
10081 * for each pass through the completion queue. The even passes
10082 * will write 1. The odd passes will write 0.
10084 #define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_V UINT32_C(0x1)
10085 /* opaque is 7 b */
10086 #define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_OPAQUE_MASK UINT32_C(0xfe)
10087 #define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_OPAQUE_SFT 1
10089 uint8_t timestamp_lo;
10090 /* Indicates if the string is partial or complete. */
10091 #define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_TIMESTAMP_LO_STRING \
10093 /* Complete string */
10094 #define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_TIMESTAMP_LO_STRING_COMPLETE \
10096 /* Partial string */
10097 #define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_TIMESTAMP_LO_STRING_PARTIAL \
10099 #define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_TIMESTAMP_LO_STRING_LAST \
10100 HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_TIMESTAMP_LO_STRING_PARTIAL
10101 /* Indicates the firmware that sent the trace message. */
10102 #define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_TIMESTAMP_LO_FIRMWARE \
10104 /* Primary firmware */
10105 #define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_TIMESTAMP_LO_FIRMWARE_PRIMARY \
10106 (UINT32_C(0x0) << 1)
10107 /* Secondary firmware */
10108 #define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_TIMESTAMP_LO_FIRMWARE_SECONDARY \
10109 (UINT32_C(0x1) << 1)
10110 #define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_TIMESTAMP_LO_FIRMWARE_LAST \
10111 HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_TIMESTAMP_LO_FIRMWARE_SECONDARY
10112 /* Trace byte 4 to 5 */
10113 uint16_t timestamp_hi;
10115 #define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_TIMESTAMP_HI_BYTE4_MASK \
10117 #define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_TIMESTAMP_HI_BYTE4_SFT 0
10119 #define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_TIMESTAMP_HI_BYTE5_MASK \
10121 #define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_TIMESTAMP_HI_BYTE5_SFT 8
10122 /* Trace byte 6 to 9 */
10123 uint32_t event_data1;
10125 #define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_EVENT_DATA1_BYTE6_MASK \
10127 #define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_EVENT_DATA1_BYTE6_SFT 0
10129 #define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_EVENT_DATA1_BYTE7_MASK \
10131 #define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_EVENT_DATA1_BYTE7_SFT 8
10133 #define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_EVENT_DATA1_BYTE8_MASK \
10135 #define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_EVENT_DATA1_BYTE8_SFT 16
10137 #define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_EVENT_DATA1_BYTE9_MASK \
10138 UINT32_C(0xff000000)
10139 #define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_EVENT_DATA1_BYTE9_SFT 24
10142 /* hwrm_async_event_cmpl_hwrm_error (size:128b/16B) */
10143 struct hwrm_async_event_cmpl_hwrm_error {
10146 * This field indicates the exact type of the completion.
10147 * By convention, the LSB identifies the length of the
10148 * record in 16B units. Even values indicate 16B
10149 * records. Odd values indicate 32B
10152 #define HWRM_ASYNC_EVENT_CMPL_HWRM_ERROR_TYPE_MASK \
10154 #define HWRM_ASYNC_EVENT_CMPL_HWRM_ERROR_TYPE_SFT 0
10155 /* HWRM Asynchronous Event Information */
10156 #define HWRM_ASYNC_EVENT_CMPL_HWRM_ERROR_TYPE_HWRM_ASYNC_EVENT \
10158 #define HWRM_ASYNC_EVENT_CMPL_HWRM_ERROR_TYPE_LAST \
10159 HWRM_ASYNC_EVENT_CMPL_HWRM_ERROR_TYPE_HWRM_ASYNC_EVENT
10160 /* Identifiers of events. */
10163 #define HWRM_ASYNC_EVENT_CMPL_HWRM_ERROR_EVENT_ID_HWRM_ERROR \
10165 #define HWRM_ASYNC_EVENT_CMPL_HWRM_ERROR_EVENT_ID_LAST \
10166 HWRM_ASYNC_EVENT_CMPL_HWRM_ERROR_EVENT_ID_HWRM_ERROR
10167 /* Event specific data */
10168 uint32_t event_data2;
10169 /* Severity of HWRM Error */
10170 #define HWRM_ASYNC_EVENT_CMPL_HWRM_ERROR_EVENT_DATA2_SEVERITY_MASK \
10172 #define HWRM_ASYNC_EVENT_CMPL_HWRM_ERROR_EVENT_DATA2_SEVERITY_SFT 0
10174 #define HWRM_ASYNC_EVENT_CMPL_HWRM_ERROR_EVENT_DATA2_SEVERITY_WARNING \
10176 /* Non-fatal Error */
10177 #define HWRM_ASYNC_EVENT_CMPL_HWRM_ERROR_EVENT_DATA2_SEVERITY_NONFATAL \
10180 #define HWRM_ASYNC_EVENT_CMPL_HWRM_ERROR_EVENT_DATA2_SEVERITY_FATAL \
10182 #define HWRM_ASYNC_EVENT_CMPL_HWRM_ERROR_EVENT_DATA2_SEVERITY_LAST \
10183 HWRM_ASYNC_EVENT_CMPL_HWRM_ERROR_EVENT_DATA2_SEVERITY_FATAL
10186 * This value is written by the NIC such that it will be different
10187 * for each pass through the completion queue. The even passes
10188 * will write 1. The odd passes will write 0.
10190 #define HWRM_ASYNC_EVENT_CMPL_HWRM_ERROR_V UINT32_C(0x1)
10191 /* opaque is 7 b */
10192 #define HWRM_ASYNC_EVENT_CMPL_HWRM_ERROR_OPAQUE_MASK UINT32_C(0xfe)
10193 #define HWRM_ASYNC_EVENT_CMPL_HWRM_ERROR_OPAQUE_SFT 1
10194 /* 8-lsb timestamp from POR (100-msec resolution) */
10195 uint8_t timestamp_lo;
10196 /* 16-lsb timestamp from POR (100-msec resolution) */
10197 uint16_t timestamp_hi;
10198 /* Event specific data */
10199 uint32_t event_data1;
10200 /* Time stamp for error event */
10201 #define HWRM_ASYNC_EVENT_CMPL_HWRM_ERROR_EVENT_DATA1_TIMESTAMP \
10205 /* hwrm_async_event_cmpl_error_report_base (size:128b/16B) */
10206 struct hwrm_async_event_cmpl_error_report_base {
10209 * This field indicates the exact type of the completion.
10210 * By convention, the LSB identifies the length of the
10211 * record in 16B units. Even values indicate 16B
10212 * records. Odd values indicate 32B
10215 #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_BASE_TYPE_MASK \
10217 #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_BASE_TYPE_SFT 0
10218 /* HWRM Asynchronous Event Information */
10219 #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_BASE_TYPE_HWRM_ASYNC_EVENT \
10221 #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_BASE_TYPE_LAST \
10222 HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_BASE_TYPE_HWRM_ASYNC_EVENT
10223 /* Identifiers of events. */
10226 * This async notification message is used to inform
10227 * the driver that an error has occurred which may need
10228 * the attention of the administrator.
10230 #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_BASE_EVENT_ID_ERROR_REPORT \
10232 #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_BASE_EVENT_ID_LAST \
10233 HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_BASE_EVENT_ID_ERROR_REPORT
10234 /* Event specific data. */
10235 uint32_t event_data2;
10238 * This value is written by the NIC such that it will be different
10239 * for each pass through the completion queue. The even passes
10240 * will write 1. The odd passes will write 0.
10242 #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_BASE_V \
10244 /* opaque is 7 b */
10245 #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_BASE_OPAQUE_MASK \
10247 #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_BASE_OPAQUE_SFT 1
10248 /* 8-lsb timestamp (100-msec resolution) */
10249 uint8_t timestamp_lo;
10250 /* 16-lsb timestamp (100-msec resolution) */
10251 uint16_t timestamp_hi;
10252 /* Event specific data */
10253 uint32_t event_data1;
10254 /* Indicates the type of error being reported. */
10255 #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_BASE_EVENT_DATA1_ERROR_TYPE_MASK \
10257 #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_BASE_EVENT_DATA1_ERROR_TYPE_SFT \
10260 #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_BASE_EVENT_DATA1_ERROR_TYPE_RESERVED \
10263 * The NIC was subjected to an extended pause storm which caused it
10264 * to disable flow control in order to avoid stalling the Tx path.
10266 #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_BASE_EVENT_DATA1_ERROR_TYPE_PAUSE_STORM \
10269 * The NIC received an interrupt storm on a TSIO pin being used as
10270 * PPS_IN which caused it to disable the interrupt. The signal
10271 * should be fixed to be a proper 1 PPS signal before re-enabling
10272 * it. The pin number on which this signal was received is stored
10273 * in event_data2 as pin_id.
10275 #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_BASE_EVENT_DATA1_ERROR_TYPE_INVALID_SIGNAL \
10278 * There was a low level error with an NVM write or erase.
10279 * See nvm_err_type for more details.
10281 #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_BASE_EVENT_DATA1_ERROR_TYPE_NVM \
10284 * This indicates doorbell drop threshold was hit. When this
10285 * threshold is crossed, it indicates one or more doorbells for
10286 * the function were dropped by hardware.
10288 #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_BASE_EVENT_DATA1_ERROR_TYPE_DOORBELL_DROP_THRESHOLD \
10290 #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_BASE_EVENT_DATA1_ERROR_TYPE_LAST \
10291 HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_BASE_EVENT_DATA1_ERROR_TYPE_DOORBELL_DROP_THRESHOLD
10294 /* hwrm_async_event_cmpl_error_report_pause_storm (size:128b/16B) */
10295 struct hwrm_async_event_cmpl_error_report_pause_storm {
10298 * This field indicates the exact type of the completion.
10299 * By convention, the LSB identifies the length of the
10300 * record in 16B units. Even values indicate 16B
10301 * records. Odd values indicate 32B
10304 #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_PAUSE_STORM_TYPE_MASK \
10306 #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_PAUSE_STORM_TYPE_SFT \
10308 /* HWRM Asynchronous Event Information */
10309 #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_PAUSE_STORM_TYPE_HWRM_ASYNC_EVENT \
10311 #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_PAUSE_STORM_TYPE_LAST \
10312 HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_PAUSE_STORM_TYPE_HWRM_ASYNC_EVENT
10313 /* Identifiers of events. */
10316 * This async notification message is used to inform
10317 * the driver that an error has occurred which may need
10318 * the attention of the administrator.
10320 #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_PAUSE_STORM_EVENT_ID_ERROR_REPORT \
10322 #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_PAUSE_STORM_EVENT_ID_LAST \
10323 HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_PAUSE_STORM_EVENT_ID_ERROR_REPORT
10324 /* Event specific data. */
10325 uint32_t event_data2;
10328 * This value is written by the NIC such that it will be different
10329 * for each pass through the completion queue. The even passes
10330 * will write 1. The odd passes will write 0.
10332 #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_PAUSE_STORM_V \
10334 /* opaque is 7 b */
10335 #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_PAUSE_STORM_OPAQUE_MASK \
10337 #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_PAUSE_STORM_OPAQUE_SFT 1
10338 /* 8-lsb timestamp (100-msec resolution) */
10339 uint8_t timestamp_lo;
10340 /* 16-lsb timestamp (100-msec resolution) */
10341 uint16_t timestamp_hi;
10342 /* Event specific data */
10343 uint32_t event_data1;
10344 /* Indicates the type of error being reported. */
10345 #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_PAUSE_STORM_EVENT_DATA1_ERROR_TYPE_MASK \
10347 #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_PAUSE_STORM_EVENT_DATA1_ERROR_TYPE_SFT \
10350 * The NIC was subjected to an extended pause storm which caused it
10351 * to disable flow control in order to avoid stalling the Tx path.
10353 #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_PAUSE_STORM_EVENT_DATA1_ERROR_TYPE_PAUSE_STORM \
10355 #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_PAUSE_STORM_EVENT_DATA1_ERROR_TYPE_LAST \
10356 HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_PAUSE_STORM_EVENT_DATA1_ERROR_TYPE_PAUSE_STORM
10359 /* hwrm_async_event_cmpl_error_report_invalid_signal (size:128b/16B) */
10360 struct hwrm_async_event_cmpl_error_report_invalid_signal {
10363 * This field indicates the exact type of the completion.
10364 * By convention, the LSB identifies the length of the
10365 * record in 16B units. Even values indicate 16B
10366 * records. Odd values indicate 32B
10369 #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_INVALID_SIGNAL_TYPE_MASK \
10371 #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_INVALID_SIGNAL_TYPE_SFT \
10373 /* HWRM Asynchronous Event Information */
10374 #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_INVALID_SIGNAL_TYPE_HWRM_ASYNC_EVENT \
10376 #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_INVALID_SIGNAL_TYPE_LAST \
10377 HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_INVALID_SIGNAL_TYPE_HWRM_ASYNC_EVENT
10378 /* Identifiers of events. */
10381 * This async notification message is used to inform
10382 * the driver that an error has occurred which may need
10383 * the attention of the administrator.
10385 #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_INVALID_SIGNAL_EVENT_ID_ERROR_REPORT \
10387 #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_INVALID_SIGNAL_EVENT_ID_LAST \
10388 HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_INVALID_SIGNAL_EVENT_ID_ERROR_REPORT
10389 /* Event specific data. */
10390 uint32_t event_data2;
10391 /* Indicates the TSIO pin on which invalid signal is detected. */
10392 #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_INVALID_SIGNAL_EVENT_DATA2_PIN_ID_MASK \
10394 #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_INVALID_SIGNAL_EVENT_DATA2_PIN_ID_SFT \
10398 * This value is written by the NIC such that it will be different
10399 * for each pass through the completion queue. The even passes
10400 * will write 1. The odd passes will write 0.
10402 #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_INVALID_SIGNAL_V \
10404 /* opaque is 7 b */
10405 #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_INVALID_SIGNAL_OPAQUE_MASK \
10407 #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_INVALID_SIGNAL_OPAQUE_SFT 1
10408 /* 8-lsb timestamp (100-msec resolution) */
10409 uint8_t timestamp_lo;
10410 /* 16-lsb timestamp (100-msec resolution) */
10411 uint16_t timestamp_hi;
10412 /* Event specific data */
10413 uint32_t event_data1;
10414 /* Indicates the type of error being reported. */
10415 #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_INVALID_SIGNAL_EVENT_DATA1_ERROR_TYPE_MASK \
10417 #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_INVALID_SIGNAL_EVENT_DATA1_ERROR_TYPE_SFT \
10420 * The NIC received an interrupt storm on a TSIO pin being used as
10421 * PPS_IN which caused it to disable the interrupt. The signal
10422 * should be fixed to be a proper 1 PPS signal before re-enabling
10423 * it. The pin number on which this signal was received is stored
10424 * in event_data2 as pin_id.
10426 #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_INVALID_SIGNAL_EVENT_DATA1_ERROR_TYPE_INVALID_SIGNAL \
10428 #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_INVALID_SIGNAL_EVENT_DATA1_ERROR_TYPE_LAST \
10429 HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_INVALID_SIGNAL_EVENT_DATA1_ERROR_TYPE_INVALID_SIGNAL
10432 /* hwrm_async_event_cmpl_error_report_nvm (size:128b/16B) */
10433 struct hwrm_async_event_cmpl_error_report_nvm {
10436 * This field indicates the exact type of the completion.
10437 * By convention, the LSB identifies the length of the
10438 * record in 16B units. Even values indicate 16B
10439 * records. Odd values indicate 32B
10442 #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_NVM_TYPE_MASK \
10444 #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_NVM_TYPE_SFT 0
10445 /* HWRM Asynchronous Event Information */
10446 #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_NVM_TYPE_HWRM_ASYNC_EVENT \
10448 #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_NVM_TYPE_LAST \
10449 HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_NVM_TYPE_HWRM_ASYNC_EVENT
10450 /* Identifiers of events. */
10453 * This async notification message is used to inform
10454 * the driver that an error has occurred which may need
10455 * the attention of the administrator.
10457 #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_NVM_EVENT_ID_ERROR_REPORT \
10459 #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_NVM_EVENT_ID_LAST \
10460 HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_NVM_EVENT_ID_ERROR_REPORT
10461 /* Event specific data. */
10462 uint32_t event_data2;
10463 /* Indicates the address where error was detected */
10464 #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_NVM_EVENT_DATA2_ERR_ADDR_MASK \
10465 UINT32_C(0xffffffff)
10466 #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_NVM_EVENT_DATA2_ERR_ADDR_SFT \
10470 * This value is written by the NIC such that it will be different
10471 * for each pass through the completion queue. The even passes
10472 * will write 1. The odd passes will write 0.
10474 #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_NVM_V UINT32_C(0x1)
10475 /* opaque is 7 b */
10476 #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_NVM_OPAQUE_MASK \
10478 #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_NVM_OPAQUE_SFT 1
10479 /* 8-lsb timestamp (100-msec resolution) */
10480 uint8_t timestamp_lo;
10481 /* 16-lsb timestamp (100-msec resolution) */
10482 uint16_t timestamp_hi;
10483 /* Event specific data */
10484 uint32_t event_data1;
10485 /* Indicates the type of error being reported. */
10486 #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_NVM_EVENT_DATA1_ERROR_TYPE_MASK \
10488 #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_NVM_EVENT_DATA1_ERROR_TYPE_SFT \
10491 * There was a low level error with an NVM operation.
10492 * See nvm_err_type for more details.
10494 #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_NVM_EVENT_DATA1_ERROR_TYPE_NVM_ERROR \
10496 #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_NVM_EVENT_DATA1_ERROR_TYPE_LAST \
10497 HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_NVM_EVENT_DATA1_ERROR_TYPE_NVM_ERROR
10498 /* The specific type of NVM error */
10499 #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_NVM_EVENT_DATA1_NVM_ERR_TYPE_MASK \
10501 #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_NVM_EVENT_DATA1_NVM_ERR_TYPE_SFT \
10504 * There was a low level error with an NVM write operation.
10505 * Verification of written data did not match.
10506 * event_data2 will be the failing address.
10508 #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_NVM_EVENT_DATA1_NVM_ERR_TYPE_WRITE \
10509 (UINT32_C(0x1) << 8)
10511 * There was a low level error with an NVM erase operation.
10512 * All the bits were not erased.
10513 * event_data2 will be the failing address.
10515 #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_NVM_EVENT_DATA1_NVM_ERR_TYPE_ERASE \
10516 (UINT32_C(0x2) << 8)
10517 #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_NVM_EVENT_DATA1_NVM_ERR_TYPE_LAST \
10518 HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_NVM_EVENT_DATA1_NVM_ERR_TYPE_ERASE
10521 /* hwrm_async_event_cmpl_error_report_doorbell_drop_threshold (size:128b/16B) */
10522 struct hwrm_async_event_cmpl_error_report_doorbell_drop_threshold {
10525 * This field indicates the exact type of the completion.
10526 * By convention, the LSB identifies the length of the
10527 * record in 16B units. Even values indicate 16B
10528 * records. Odd values indicate 32B
10531 #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_DOORBELL_DROP_THRESHOLD_TYPE_MASK \
10533 #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_DOORBELL_DROP_THRESHOLD_TYPE_SFT \
10535 /* HWRM Asynchronous Event Information */
10536 #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_DOORBELL_DROP_THRESHOLD_TYPE_HWRM_ASYNC_EVENT \
10538 #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_DOORBELL_DROP_THRESHOLD_TYPE_LAST \
10539 HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_DOORBELL_DROP_THRESHOLD_TYPE_HWRM_ASYNC_EVENT
10540 /* Identifiers of events. */
10543 * This async notification message is used to inform
10544 * the driver that an error has occurred which may need
10545 * the attention of the administrator.
10547 #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_DOORBELL_DROP_THRESHOLD_EVENT_ID_ERROR_REPORT \
10549 #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_DOORBELL_DROP_THRESHOLD_EVENT_ID_LAST \
10550 HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_DOORBELL_DROP_THRESHOLD_EVENT_ID_ERROR_REPORT
10551 /* Event specific data. */
10552 uint32_t event_data2;
10555 * This value is written by the NIC such that it will be different
10556 * for each pass through the completion queue. The even passes
10557 * will write 1. The odd passes will write 0.
10559 #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_DOORBELL_DROP_THRESHOLD_V \
10561 /* opaque is 7 b */
10562 #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_DOORBELL_DROP_THRESHOLD_OPAQUE_MASK \
10564 #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_DOORBELL_DROP_THRESHOLD_OPAQUE_SFT \
10566 /* 8-lsb timestamp (100-msec resolution) */
10567 uint8_t timestamp_lo;
10568 /* 16-lsb timestamp (100-msec resolution) */
10569 uint16_t timestamp_hi;
10570 /* Event specific data */
10571 uint32_t event_data1;
10572 /* Indicates the type of error being reported. */
10573 #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_DOORBELL_DROP_THRESHOLD_EVENT_DATA1_ERROR_TYPE_MASK \
10575 #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_DOORBELL_DROP_THRESHOLD_EVENT_DATA1_ERROR_TYPE_SFT \
10578 * This indicates doorbell drop threshold was hit. When this
10579 * threshold is crossed, it indicates one or more doorbells for
10580 * the function were dropped by hardware.
10582 #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_DOORBELL_DROP_THRESHOLD_EVENT_DATA1_ERROR_TYPE_DOORBELL_DROP_THRESHOLD \
10584 #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_DOORBELL_DROP_THRESHOLD_EVENT_DATA1_ERROR_TYPE_LAST \
10585 HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_DOORBELL_DROP_THRESHOLD_EVENT_DATA1_ERROR_TYPE_DOORBELL_DROP_THRESHOLD
10588 /* metadata_base_msg (size:64b/8B) */
10589 struct metadata_base_msg {
10590 uint16_t md_type_link;
10591 /* This field classifies the data present in the meta-data. */
10592 #define METADATA_BASE_MSG_MD_TYPE_MASK UINT32_C(0x1f)
10593 #define METADATA_BASE_MSG_MD_TYPE_SFT 0
10594 /* Meta data fields are not valid */
10595 #define METADATA_BASE_MSG_MD_TYPE_NONE UINT32_C(0x0)
10597 * This setting is used when packets are coming in-order. Depending on
10598 * the state of the receive context, the meta-data will carry different
10601 #define METADATA_BASE_MSG_MD_TYPE_TLS_INSYNC UINT32_C(0x1)
10603 * With this setting HW passes the TCP sequence number of the TLS
10604 * record that it is requesting a resync on in the meta data.
10606 #define METADATA_BASE_MSG_MD_TYPE_TLS_RESYNC UINT32_C(0x2)
10607 #define METADATA_BASE_MSG_MD_TYPE_LAST \
10608 METADATA_BASE_MSG_MD_TYPE_TLS_RESYNC
10610 * This field indicates where the next metadata block starts. It is
10611 * counted in 16B units. A value of zero indicates that there is no
10614 #define METADATA_BASE_MSG_LINK_MASK UINT32_C(0x1e0)
10615 #define METADATA_BASE_MSG_LINK_SFT 5
10620 /* tls_metadata_base_msg (size:64b/8B) */
10621 struct tls_metadata_base_msg {
10622 uint32_t md_type_link_flags_kid_lo;
10623 /* This field classifies the data present in the meta-data. */
10624 #define TLS_METADATA_BASE_MSG_MD_TYPE_MASK \
10626 #define TLS_METADATA_BASE_MSG_MD_TYPE_SFT 0
10628 * This setting is used when packets are coming in-order. Depending on
10629 * the state of the receive context, the meta-data will carry different
10632 #define TLS_METADATA_BASE_MSG_MD_TYPE_TLS_INSYNC \
10635 * With this setting HW passes the TCP sequence number of the TLS
10636 * record that it is requesting a resync on in the meta data.
10638 #define TLS_METADATA_BASE_MSG_MD_TYPE_TLS_RESYNC \
10640 #define TLS_METADATA_BASE_MSG_MD_TYPE_LAST \
10641 TLS_METADATA_BASE_MSG_MD_TYPE_TLS_RESYNC
10643 * This field indicates where the next metadata block starts. It is
10644 * counted in 16B units. A value of zero indicates that there is no
10647 #define TLS_METADATA_BASE_MSG_LINK_MASK \
10649 #define TLS_METADATA_BASE_MSG_LINK_SFT 5
10650 /* These are flags present in the metadata. */
10651 #define TLS_METADATA_BASE_MSG_FLAGS_MASK \
10652 UINT32_C(0x1fffe00)
10653 #define TLS_METADATA_BASE_MSG_FLAGS_SFT 9
10655 * A value of 1 implies that the packet was decrypted by HW. Otherwise
10656 * the packet is passed on as it came in on the wire.
10658 #define TLS_METADATA_BASE_MSG_FLAGS_DECRYPTED \
10661 * This field indicates the state of the ghash field passed in the
10664 #define TLS_METADATA_BASE_MSG_FLAGS_GHASH_MASK \
10666 #define TLS_METADATA_BASE_MSG_FLAGS_GHASH_SFT 10
10668 * This enumeration states that the ghash is not valid in the
10671 #define TLS_METADATA_BASE_MSG_FLAGS_GHASH_NOT_VALID \
10672 (UINT32_C(0x0) << 10)
10674 * This enumeration indicates that this pkt contains the record's
10675 * tag and this pkt was received ooo, the partial_ghash field
10676 * contains the ghash.
10678 #define TLS_METADATA_BASE_MSG_FLAGS_GHASH_CUR_REC \
10679 (UINT32_C(0x1) << 10)
10681 * This enumeration indicates that the current record's tag wasn't
10682 * seen and the chip is moving on to the next record, the
10683 * partial_ghash field contains the ghash.
10685 #define TLS_METADATA_BASE_MSG_FLAGS_GHASH_PRIOR_REC \
10686 (UINT32_C(0x2) << 10)
10687 #define TLS_METADATA_BASE_MSG_FLAGS_GHASH_LAST \
10688 TLS_METADATA_BASE_MSG_FLAGS_GHASH_PRIOR_REC
10689 /* This field indicates the status of tag authentication. */
10690 #define TLS_METADATA_BASE_MSG_FLAGS_TAG_AUTH_STATUS_MASK \
10692 #define TLS_METADATA_BASE_MSG_FLAGS_TAG_AUTH_STATUS_SFT 12
10694 * This enumeration is set when there is no tags present in the
10697 #define TLS_METADATA_BASE_MSG_FLAGS_TAG_AUTH_STATUS_NONE \
10698 (UINT32_C(0x0) << 12)
10700 * This enumeration states that there is at least one tag in the
10701 * packet and every tag is valid.
10703 #define TLS_METADATA_BASE_MSG_FLAGS_TAG_AUTH_STATUS_SUCCESS \
10704 (UINT32_C(0x1) << 12)
10706 * This enumeration states that there is at least one tag in the
10707 * packet and at least one of the tag is invalid. The entire packet
10708 * is sent decrypted to the host.
10710 #define TLS_METADATA_BASE_MSG_FLAGS_TAG_AUTH_STATUS_FAILURE \
10711 (UINT32_C(0x2) << 12)
10712 #define TLS_METADATA_BASE_MSG_FLAGS_TAG_AUTH_STATUS_LAST \
10713 TLS_METADATA_BASE_MSG_FLAGS_TAG_AUTH_STATUS_FAILURE
10715 * A value of 1 indicates that this packet contains a record that
10716 * starts in the packet and extends beyond the packet.
10718 #define TLS_METADATA_BASE_MSG_FLAGS_HEADER_FLDS_VALID \
10721 * This value indicates the lower 7-bit of the Crypto Key ID
10722 * associated with this operation.
10724 #define TLS_METADATA_BASE_MSG_KID_LO_MASK \
10725 UINT32_C(0xfe000000)
10726 #define TLS_METADATA_BASE_MSG_KID_LO_SFT 25
10729 * This value indicates the upper 13-bit of the Crypto Key ID
10730 * associated with this operation.
10732 #define TLS_METADATA_BASE_MSG_KID_HI_MASK UINT32_C(0x1fff)
10733 #define TLS_METADATA_BASE_MSG_KID_HI_SFT 0
10737 /* tls_metadata_insync_msg (size:192b/24B) */
10738 struct tls_metadata_insync_msg {
10739 uint32_t md_type_link_flags_kid_lo;
10740 /* This field classifies the data present in the meta-data. */
10741 #define TLS_METADATA_INSYNC_MSG_MD_TYPE_MASK \
10743 #define TLS_METADATA_INSYNC_MSG_MD_TYPE_SFT 0
10745 * This setting is used when packets are coming in-order. Depending on
10746 * the state of the receive context, the meta-data will carry different
10749 #define TLS_METADATA_INSYNC_MSG_MD_TYPE_TLS_INSYNC \
10751 #define TLS_METADATA_INSYNC_MSG_MD_TYPE_LAST \
10752 TLS_METADATA_INSYNC_MSG_MD_TYPE_TLS_INSYNC
10754 * This field indicates where the next metadata block starts. It is
10755 * counted in 16B units. A value of zero indicates that there is no
10758 #define TLS_METADATA_INSYNC_MSG_LINK_MASK \
10760 #define TLS_METADATA_INSYNC_MSG_LINK_SFT 5
10761 /* These are flags present in the metadata. */
10762 #define TLS_METADATA_INSYNC_MSG_FLAGS_MASK \
10763 UINT32_C(0x1fffe00)
10764 #define TLS_METADATA_INSYNC_MSG_FLAGS_SFT 9
10766 * A value of 1 implies that the packet was decrypted by HW. Otherwise
10767 * the packet is passed on as it came in on the wire.
10769 #define TLS_METADATA_INSYNC_MSG_FLAGS_DECRYPTED \
10772 * This field indicates the state of the ghash field passed in the
10775 #define TLS_METADATA_INSYNC_MSG_FLAGS_GHASH_MASK \
10777 #define TLS_METADATA_INSYNC_MSG_FLAGS_GHASH_SFT 10
10779 * This enumeration states that the ghash is not valid in the
10782 #define TLS_METADATA_INSYNC_MSG_FLAGS_GHASH_NOT_VALID \
10783 (UINT32_C(0x0) << 10)
10785 * This enumeration indicates that this pkt contains the record's
10786 * tag and this pkt was received ooo, the partial_ghash field
10787 * contains the ghash.
10789 #define TLS_METADATA_INSYNC_MSG_FLAGS_GHASH_CUR_REC \
10790 (UINT32_C(0x1) << 10)
10792 * This enumeration indicates that the current record's tag wasn't
10793 * seen and the chip is moving on to the next record, the
10794 * partial_ghash field contains the ghash.
10796 #define TLS_METADATA_INSYNC_MSG_FLAGS_GHASH_PRIOR_REC \
10797 (UINT32_C(0x2) << 10)
10798 #define TLS_METADATA_INSYNC_MSG_FLAGS_GHASH_LAST \
10799 TLS_METADATA_INSYNC_MSG_FLAGS_GHASH_PRIOR_REC
10800 /* This field indicates the status of tag authentication. */
10801 #define TLS_METADATA_INSYNC_MSG_FLAGS_TAG_AUTH_STATUS_MASK \
10803 #define TLS_METADATA_INSYNC_MSG_FLAGS_TAG_AUTH_STATUS_SFT 12
10805 * This enumeration is set when there is no tags present in the
10808 #define TLS_METADATA_INSYNC_MSG_FLAGS_TAG_AUTH_STATUS_NONE \
10809 (UINT32_C(0x0) << 12)
10811 * This enumeration states that there is at least one tag in the
10812 * packet and every tag is valid.
10814 #define TLS_METADATA_INSYNC_MSG_FLAGS_TAG_AUTH_STATUS_SUCCESS \
10815 (UINT32_C(0x1) << 12)
10817 * This enumeration states that there is at least one tag in the
10818 * packet and at least one of the tag is invalid. The entire packet
10819 * is sent decrypted to the host.
10821 #define TLS_METADATA_INSYNC_MSG_FLAGS_TAG_AUTH_STATUS_FAILURE \
10822 (UINT32_C(0x2) << 12)
10823 #define TLS_METADATA_INSYNC_MSG_FLAGS_TAG_AUTH_STATUS_LAST \
10824 TLS_METADATA_INSYNC_MSG_FLAGS_TAG_AUTH_STATUS_FAILURE
10826 * A value of 1 indicates that this packet contains a record that
10827 * starts in the packet and extends beyond the packet.
10829 #define TLS_METADATA_INSYNC_MSG_FLAGS_HEADER_FLDS_VALID \
10832 * This value indicates the lower 7-bit of the Crypto Key ID
10833 * associated with this operation.
10835 #define TLS_METADATA_INSYNC_MSG_KID_LO_MASK \
10836 UINT32_C(0xfe000000)
10837 #define TLS_METADATA_INSYNC_MSG_KID_LO_SFT 25
10840 * This value indicates the upper 13-bit of the Crypto Key ID
10841 * associated with this operation.
10843 #define TLS_METADATA_INSYNC_MSG_KID_HI_MASK UINT32_C(0x1fff)
10844 #define TLS_METADATA_INSYNC_MSG_KID_HI_SFT 0
10846 * This field is only valid when md_type is set to tls_insync. This field
10847 * indicates the offset within the current TCP packet where the TLS header
10848 * starts. If there are multiple TLS headers in the packet, this provides
10849 * the offset of the last TLS header.
10851 * The field is calculated by subtracting TCP sequence number of the first
10852 * byte of the TCP payload of the packet from the TCP sequence number of
10853 * the last TLS header in the packet.
10855 uint16_t tls_header_offset;
10857 * This is the sequence Number of the record that was processed by the HW.
10858 * If there are multiple records in a packet, this would be the sequence
10859 * number of the last record.
10861 uint64_t record_seq_num;
10863 * This field contains cumulative partial GHASH value of all the packets
10864 * decrypted by the HW associated with a TLS record. This field is valid
10865 * on when packets belonging to have arrived out-of-order and HW could
10866 * not decrypt every packet and authenticate the record. Partial GHASH is
10867 * only sent out with packet having the TAG field.
10869 uint64_t partial_ghash;
10872 /* tls_metadata_resync_msg (size:256b/32B) */
10873 struct tls_metadata_resync_msg {
10874 uint32_t md_type_link_flags_kid_lo;
10875 /* This field classifies the data present in the meta-data. */
10876 #define TLS_METADATA_RESYNC_MSG_MD_TYPE_MASK \
10878 #define TLS_METADATA_RESYNC_MSG_MD_TYPE_SFT 0
10880 * With this setting HW passes the TCP sequence number of the TLS
10881 * record that it is requesting a resync on in the meta data.
10883 #define TLS_METADATA_RESYNC_MSG_MD_TYPE_TLS_RESYNC \
10885 #define TLS_METADATA_RESYNC_MSG_MD_TYPE_LAST \
10886 TLS_METADATA_RESYNC_MSG_MD_TYPE_TLS_RESYNC
10888 * This field indicates where the next metadata block starts. It is
10889 * counted in 16B units. A value of zero indicates that there is no
10892 #define TLS_METADATA_RESYNC_MSG_LINK_MASK \
10894 #define TLS_METADATA_RESYNC_MSG_LINK_SFT 5
10895 /* These are flags present in the metadata. */
10896 #define TLS_METADATA_RESYNC_MSG_FLAGS_MASK \
10897 UINT32_C(0x1fffe00)
10898 #define TLS_METADATA_RESYNC_MSG_FLAGS_SFT 9
10900 * A value of 1 implies that the packet was decrypted by HW. Otherwise
10901 * the packet is passed on as it came in on the wire.
10903 #define TLS_METADATA_RESYNC_MSG_FLAGS_DECRYPTED \
10906 * This field indicates the state of the ghash field passed in the
10909 #define TLS_METADATA_RESYNC_MSG_FLAGS_GHASH_MASK \
10911 #define TLS_METADATA_RESYNC_MSG_FLAGS_GHASH_SFT 10
10913 * This enumeration states that the ghash is not valid in the
10916 #define TLS_METADATA_RESYNC_MSG_FLAGS_GHASH_NOT_VALID \
10917 (UINT32_C(0x0) << 10)
10918 #define TLS_METADATA_RESYNC_MSG_FLAGS_GHASH_LAST \
10919 TLS_METADATA_RESYNC_MSG_FLAGS_GHASH_NOT_VALID
10920 /* This field indicates the status of tag authentication. */
10921 #define TLS_METADATA_RESYNC_MSG_FLAGS_TAG_AUTH_STATUS_MASK \
10923 #define TLS_METADATA_RESYNC_MSG_FLAGS_TAG_AUTH_STATUS_SFT 12
10925 * This enumeration is set when there is no tags present in the
10928 #define TLS_METADATA_RESYNC_MSG_FLAGS_TAG_AUTH_STATUS_NONE \
10929 (UINT32_C(0x0) << 12)
10930 #define TLS_METADATA_RESYNC_MSG_FLAGS_TAG_AUTH_STATUS_LAST \
10931 TLS_METADATA_RESYNC_MSG_FLAGS_TAG_AUTH_STATUS_NONE
10933 * A value of 1 indicates that this packet contains a record that
10934 * starts in the packet and extends beyond the packet.
10936 #define TLS_METADATA_RESYNC_MSG_FLAGS_HEADER_FLDS_VALID \
10939 * This value indicates the lower 7-bit of the Crypto Key ID
10940 * associated with this operation.
10942 #define TLS_METADATA_RESYNC_MSG_KID_LO_MASK \
10943 UINT32_C(0xfe000000)
10944 #define TLS_METADATA_RESYNC_MSG_KID_LO_SFT 25
10947 * This value indicates the upper 13-bit of the Crypto Key ID
10948 * associated with this operation.
10950 #define TLS_METADATA_RESYNC_MSG_KID_HI_MASK UINT32_C(0x1fff)
10951 #define TLS_METADATA_RESYNC_MSG_KID_HI_SFT 0
10952 /* This field is unused in this context. */
10953 uint16_t metadata_0;
10955 * This field indicates the TCP sequence number of the TLS record that HW
10956 * is requesting a resync on from the Driver. HW will keep a count of the
10957 * TLS records it found after this record (delta_records). Driver will
10958 * provide the TLS Record Sequence Number associated with the record. HW
10959 * will add the delta_records to the Record Sequence Number provided by
10960 * the driver and get back on sync.
10962 uint32_t resync_record_tcp_seq_num;
10964 /* This field is unused in this context. */
10965 uint64_t metadata_2;
10966 /* This field is unused in this context. */
10967 uint64_t metadata_3;
10970 /*******************
10971 * hwrm_func_reset *
10972 *******************/
10975 /* hwrm_func_reset_input (size:192b/24B) */
10976 struct hwrm_func_reset_input {
10977 /* The HWRM command request type. */
10980 * The completion ring to send the completion event on. This should
10981 * be the NQ ID returned from the `nq_alloc` HWRM command.
10983 uint16_t cmpl_ring;
10985 * The sequence ID is used by the driver for tracking multiple
10986 * commands. This ID is treated as opaque data by the firmware and
10987 * the value is returned in the `hwrm_resp_hdr` upon completion.
10991 * The target ID of the command:
10992 * * 0x0-0xFFF8 - The function ID
10993 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
10994 * * 0xFFFD - Reserved for user-space HWRM interface
10997 uint16_t target_id;
10999 * A physical address pointer pointing to a host buffer that the
11000 * command's response data will be written. This can be either a host
11001 * physical address (HPA) or a guest physical address (GPA) and must
11002 * point to a physically contiguous block of memory.
11004 uint64_t resp_addr;
11007 * This bit must be '1' for the vf_id_valid field to be
11010 #define HWRM_FUNC_RESET_INPUT_ENABLES_VF_ID_VALID UINT32_C(0x1)
11012 * The ID of the VF that this PF is trying to reset.
11013 * Only the parent PF shall be allowed to reset a child VF.
11015 * A parent PF driver shall use this field only when a specific child VF
11016 * is requested to be reset.
11019 /* This value indicates the level of a function reset. */
11020 uint8_t func_reset_level;
11022 * Reset the caller function and its children VFs (if any). If no
11023 * children functions exist, then reset the caller function only.
11025 #define HWRM_FUNC_RESET_INPUT_FUNC_RESET_LEVEL_RESETALL \
11027 /* Reset the caller function only */
11028 #define HWRM_FUNC_RESET_INPUT_FUNC_RESET_LEVEL_RESETME \
11031 * Reset all children VFs of the caller function driver if the
11032 * caller is a PF driver.
11033 * It is an error to specify this level by a VF driver.
11034 * It is an error to specify this level by a PF driver with
11037 #define HWRM_FUNC_RESET_INPUT_FUNC_RESET_LEVEL_RESETCHILDREN \
11040 * Reset a specific VF of the caller function driver if the caller
11041 * is the parent PF driver.
11042 * It is an error to specify this level by a VF driver.
11043 * It is an error to specify this level by a PF driver that is not
11044 * the parent of the VF that is being requested to reset.
11046 #define HWRM_FUNC_RESET_INPUT_FUNC_RESET_LEVEL_RESETVF \
11048 #define HWRM_FUNC_RESET_INPUT_FUNC_RESET_LEVEL_LAST \
11049 HWRM_FUNC_RESET_INPUT_FUNC_RESET_LEVEL_RESETVF
11053 /* hwrm_func_reset_output (size:128b/16B) */
11054 struct hwrm_func_reset_output {
11055 /* The specific error status for the command. */
11056 uint16_t error_code;
11057 /* The HWRM command request type. */
11059 /* The sequence ID from the original command. */
11061 /* The length of the response data in number of bytes. */
11063 uint8_t unused_0[7];
11065 * This field is used in Output records to indicate that the output
11066 * is completely written to RAM. This field should be read as '1'
11067 * to indicate that the output has been completely written.
11068 * When writing a command completion or response to an internal processor,
11069 * the order of writes has to be such that this field is written last.
11074 /********************
11075 * hwrm_func_getfid *
11076 ********************/
11079 /* hwrm_func_getfid_input (size:192b/24B) */
11080 struct hwrm_func_getfid_input {
11081 /* The HWRM command request type. */
11084 * The completion ring to send the completion event on. This should
11085 * be the NQ ID returned from the `nq_alloc` HWRM command.
11087 uint16_t cmpl_ring;
11089 * The sequence ID is used by the driver for tracking multiple
11090 * commands. This ID is treated as opaque data by the firmware and
11091 * the value is returned in the `hwrm_resp_hdr` upon completion.
11095 * The target ID of the command:
11096 * * 0x0-0xFFF8 - The function ID
11097 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
11098 * * 0xFFFD - Reserved for user-space HWRM interface
11101 uint16_t target_id;
11103 * A physical address pointer pointing to a host buffer that the
11104 * command's response data will be written. This can be either a host
11105 * physical address (HPA) or a guest physical address (GPA) and must
11106 * point to a physically contiguous block of memory.
11108 uint64_t resp_addr;
11111 * This bit must be '1' for the pci_id field to be
11114 #define HWRM_FUNC_GETFID_INPUT_ENABLES_PCI_ID UINT32_C(0x1)
11116 * This value is the PCI ID of the queried function.
11117 * If ARI is enabled, then it is
11118 * Bus Number (8b):Function Number(8b). Otherwise, it is
11119 * Bus Number (8b):Device Number (5b):Function Number(3b).
11122 uint8_t unused_0[2];
11125 /* hwrm_func_getfid_output (size:128b/16B) */
11126 struct hwrm_func_getfid_output {
11127 /* The specific error status for the command. */
11128 uint16_t error_code;
11129 /* The HWRM command request type. */
11131 /* The sequence ID from the original command. */
11133 /* The length of the response data in number of bytes. */
11136 * FID value. This value is used to identify operations on the PCI
11137 * bus as belonging to a particular PCI function.
11140 uint8_t unused_0[5];
11142 * This field is used in Output records to indicate that the output
11143 * is completely written to RAM. This field should be read as '1'
11144 * to indicate that the output has been completely written.
11145 * When writing a command completion or response to an internal processor,
11146 * the order of writes has to be such that this field is written last.
11151 /**********************
11152 * hwrm_func_vf_alloc *
11153 **********************/
11156 /* hwrm_func_vf_alloc_input (size:192b/24B) */
11157 struct hwrm_func_vf_alloc_input {
11158 /* The HWRM command request type. */
11161 * The completion ring to send the completion event on. This should
11162 * be the NQ ID returned from the `nq_alloc` HWRM command.
11164 uint16_t cmpl_ring;
11166 * The sequence ID is used by the driver for tracking multiple
11167 * commands. This ID is treated as opaque data by the firmware and
11168 * the value is returned in the `hwrm_resp_hdr` upon completion.
11172 * The target ID of the command:
11173 * * 0x0-0xFFF8 - The function ID
11174 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
11175 * * 0xFFFD - Reserved for user-space HWRM interface
11178 uint16_t target_id;
11180 * A physical address pointer pointing to a host buffer that the
11181 * command's response data will be written. This can be either a host
11182 * physical address (HPA) or a guest physical address (GPA) and must
11183 * point to a physically contiguous block of memory.
11185 uint64_t resp_addr;
11188 * This bit must be '1' for the first_vf_id field to be
11191 #define HWRM_FUNC_VF_ALLOC_INPUT_ENABLES_FIRST_VF_ID UINT32_C(0x1)
11193 * This value is used to identify a Virtual Function (VF).
11194 * The scope of VF ID is local within a PF.
11196 uint16_t first_vf_id;
11197 /* The number of virtual functions requested. */
11201 /* hwrm_func_vf_alloc_output (size:128b/16B) */
11202 struct hwrm_func_vf_alloc_output {
11203 /* The specific error status for the command. */
11204 uint16_t error_code;
11205 /* The HWRM command request type. */
11207 /* The sequence ID from the original command. */
11209 /* The length of the response data in number of bytes. */
11211 /* The ID of the first VF allocated. */
11212 uint16_t first_vf_id;
11213 uint8_t unused_0[5];
11215 * This field is used in Output records to indicate that the output
11216 * is completely written to RAM. This field should be read as '1'
11217 * to indicate that the output has been completely written.
11218 * When writing a command completion or response to an internal processor,
11219 * the order of writes has to be such that this field is written last.
11224 /*********************
11225 * hwrm_func_vf_free *
11226 *********************/
11229 /* hwrm_func_vf_free_input (size:192b/24B) */
11230 struct hwrm_func_vf_free_input {
11231 /* The HWRM command request type. */
11234 * The completion ring to send the completion event on. This should
11235 * be the NQ ID returned from the `nq_alloc` HWRM command.
11237 uint16_t cmpl_ring;
11239 * The sequence ID is used by the driver for tracking multiple
11240 * commands. This ID is treated as opaque data by the firmware and
11241 * the value is returned in the `hwrm_resp_hdr` upon completion.
11245 * The target ID of the command:
11246 * * 0x0-0xFFF8 - The function ID
11247 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
11248 * * 0xFFFD - Reserved for user-space HWRM interface
11251 uint16_t target_id;
11253 * A physical address pointer pointing to a host buffer that the
11254 * command's response data will be written. This can be either a host
11255 * physical address (HPA) or a guest physical address (GPA) and must
11256 * point to a physically contiguous block of memory.
11258 uint64_t resp_addr;
11261 * This bit must be '1' for the first_vf_id field to be
11264 #define HWRM_FUNC_VF_FREE_INPUT_ENABLES_FIRST_VF_ID UINT32_C(0x1)
11266 * This value is used to identify a Virtual Function (VF).
11267 * The scope of VF ID is local within a PF.
11269 uint16_t first_vf_id;
11271 * The number of virtual functions requested.
11272 * 0xFFFF - Cleanup all children of this PF.
11277 /* hwrm_func_vf_free_output (size:128b/16B) */
11278 struct hwrm_func_vf_free_output {
11279 /* The specific error status for the command. */
11280 uint16_t error_code;
11281 /* The HWRM command request type. */
11283 /* The sequence ID from the original command. */
11285 /* The length of the response data in number of bytes. */
11287 uint8_t unused_0[7];
11289 * This field is used in Output records to indicate that the output
11290 * is completely written to RAM. This field should be read as '1'
11291 * to indicate that the output has been completely written.
11292 * When writing a command completion or response to an internal processor,
11293 * the order of writes has to be such that this field is written last.
11298 /********************
11299 * hwrm_func_vf_cfg *
11300 ********************/
11303 /* hwrm_func_vf_cfg_input (size:448b/56B) */
11304 struct hwrm_func_vf_cfg_input {
11305 /* The HWRM command request type. */
11308 * The completion ring to send the completion event on. This should
11309 * be the NQ ID returned from the `nq_alloc` HWRM command.
11311 uint16_t cmpl_ring;
11313 * The sequence ID is used by the driver for tracking multiple
11314 * commands. This ID is treated as opaque data by the firmware and
11315 * the value is returned in the `hwrm_resp_hdr` upon completion.
11319 * The target ID of the command:
11320 * * 0x0-0xFFF8 - The function ID
11321 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
11322 * * 0xFFFD - Reserved for user-space HWRM interface
11325 uint16_t target_id;
11327 * A physical address pointer pointing to a host buffer that the
11328 * command's response data will be written. This can be either a host
11329 * physical address (HPA) or a guest physical address (GPA) and must
11330 * point to a physically contiguous block of memory.
11332 uint64_t resp_addr;
11335 * This bit must be '1' for the mtu field to be
11338 #define HWRM_FUNC_VF_CFG_INPUT_ENABLES_MTU \
11341 * This bit must be '1' for the guest_vlan field to be
11344 #define HWRM_FUNC_VF_CFG_INPUT_ENABLES_GUEST_VLAN \
11347 * This bit must be '1' for the async_event_cr field to be
11350 #define HWRM_FUNC_VF_CFG_INPUT_ENABLES_ASYNC_EVENT_CR \
11353 * This bit must be '1' for the dflt_mac_addr field to be
11356 #define HWRM_FUNC_VF_CFG_INPUT_ENABLES_DFLT_MAC_ADDR \
11359 * This bit must be '1' for the num_rsscos_ctxs field to be
11362 #define HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_RSSCOS_CTXS \
11365 * This bit must be '1' for the num_cmpl_rings field to be
11368 #define HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_CMPL_RINGS \
11371 * This bit must be '1' for the num_tx_rings field to be
11374 #define HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_TX_RINGS \
11377 * This bit must be '1' for the num_rx_rings field to be
11380 #define HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_RX_RINGS \
11383 * This bit must be '1' for the num_l2_ctxs field to be
11386 #define HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_L2_CTXS \
11389 * This bit must be '1' for the num_vnics field to be
11392 #define HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_VNICS \
11395 * This bit must be '1' for the num_stat_ctxs field to be
11398 #define HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_STAT_CTXS \
11401 * This bit must be '1' for the num_hw_ring_grps field to be
11404 #define HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_HW_RING_GRPS \
11407 * This bit must be '1' for the num_tx_key_ctxs field to be
11410 #define HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_TX_KEY_CTXS \
11413 * This bit must be '1' for the num_rx_key_ctxs field to be
11416 #define HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_RX_KEY_CTXS \
11419 * The maximum transmission unit requested on the function.
11420 * The HWRM should make sure that the mtu of
11421 * the function does not exceed the mtu of the physical
11422 * port that this function is associated with.
11424 * In addition to requesting mtu per function, it is
11425 * possible to configure mtu per transmit ring.
11426 * By default, the mtu of each transmit ring associated
11427 * with a function is equal to the mtu of the function.
11428 * The HWRM should make sure that the mtu of each transmit
11429 * ring that is assigned to a function has a valid mtu.
11433 * The guest VLAN for the function being configured.
11434 * This field's format is same as 802.1Q Tag's
11435 * Tag Control Information (TCI) format that includes both
11436 * Priority Code Point (PCP) and VLAN Identifier (VID).
11438 uint16_t guest_vlan;
11440 * ID of the target completion ring for receiving asynchronous
11441 * event completions. If this field is not valid, then the
11442 * HWRM shall use the default completion ring of the function
11443 * that is being configured as the target completion ring for
11444 * providing any asynchronous event completions for that
11446 * If this field is valid, then the HWRM shall use the
11447 * completion ring identified by this ID as the target
11448 * completion ring for providing any asynchronous event
11449 * completions for the function that is being configured.
11451 uint16_t async_event_cr;
11453 * This value is the current MAC address requested by the VF
11454 * driver to be configured on this VF. A value of
11455 * 00-00-00-00-00-00 indicates no MAC address configuration
11456 * is requested by the VF driver.
11457 * The parent PF driver may reject or overwrite this
11460 uint8_t dflt_mac_addr[6];
11463 * This bit requests that the firmware test to see if all the assets
11464 * requested in this command (i.e. number of TX rings) are available.
11465 * The firmware will return an error if the requested assets are
11466 * not available. The firwmare will NOT reserve the assets if they
11469 #define HWRM_FUNC_VF_CFG_INPUT_FLAGS_TX_ASSETS_TEST \
11472 * This bit requests that the firmware test to see if all the assets
11473 * requested in this command (i.e. number of RX rings) are available.
11474 * The firmware will return an error if the requested assets are
11475 * not available. The firwmare will NOT reserve the assets if they
11478 #define HWRM_FUNC_VF_CFG_INPUT_FLAGS_RX_ASSETS_TEST \
11481 * This bit requests that the firmware test to see if all the assets
11482 * requested in this command (i.e. number of CMPL rings) are available.
11483 * The firmware will return an error if the requested assets are
11484 * not available. The firwmare will NOT reserve the assets if they
11487 #define HWRM_FUNC_VF_CFG_INPUT_FLAGS_CMPL_ASSETS_TEST \
11490 * This bit requests that the firmware test to see if all the assets
11491 * requested in this command (i.e. number of RSS ctx) are available.
11492 * The firmware will return an error if the requested assets are
11493 * not available. The firwmare will NOT reserve the assets if they
11496 #define HWRM_FUNC_VF_CFG_INPUT_FLAGS_RSSCOS_CTX_ASSETS_TEST \
11499 * This bit requests that the firmware test to see if all the assets
11500 * requested in this command (i.e. number of ring groups) are available.
11501 * The firmware will return an error if the requested assets are
11502 * not available. The firwmare will NOT reserve the assets if they
11505 #define HWRM_FUNC_VF_CFG_INPUT_FLAGS_RING_GRP_ASSETS_TEST \
11508 * This bit requests that the firmware test to see if all the assets
11509 * requested in this command (i.e. number of stat ctx) are available.
11510 * The firmware will return an error if the requested assets are
11511 * not available. The firwmare will NOT reserve the assets if they
11514 #define HWRM_FUNC_VF_CFG_INPUT_FLAGS_STAT_CTX_ASSETS_TEST \
11517 * This bit requests that the firmware test to see if all the assets
11518 * requested in this command (i.e. number of VNICs) are available.
11519 * The firmware will return an error if the requested assets are
11520 * not available. The firwmare will NOT reserve the assets if they
11523 #define HWRM_FUNC_VF_CFG_INPUT_FLAGS_VNIC_ASSETS_TEST \
11526 * This bit requests that the firmware test to see if all the assets
11527 * requested in this command (i.e. number of L2 ctx) are available.
11528 * The firmware will return an error if the requested assets are
11529 * not available. The firwmare will NOT reserve the assets if they
11532 #define HWRM_FUNC_VF_CFG_INPUT_FLAGS_L2_CTX_ASSETS_TEST \
11535 * If this bit is set to 1, the VF driver is requesting FW to enable
11536 * PPP TX PUSH feature on all the TX rings specified in the
11537 * num_tx_rings field. By default, the PPP TX push feature is
11538 * disabled for all the TX rings of the VF. This flag is ignored if
11539 * the num_tx_rings field is not specified or the VF doesn't support
11540 * PPP tx push feature.
11542 #define HWRM_FUNC_VF_CFG_INPUT_FLAGS_PPP_PUSH_MODE_ENABLE \
11545 * If this bit is set to 1, the VF driver is requesting FW to disable
11546 * PPP TX PUSH feature on all the TX rings of the VF. This flag is
11547 * ignored if the VF doesn't support PPP tx push feature.
11549 #define HWRM_FUNC_VF_CFG_INPUT_FLAGS_PPP_PUSH_MODE_DISABLE \
11551 /* The number of RSS/COS contexts requested for the VF. */
11552 uint16_t num_rsscos_ctxs;
11553 /* The number of completion rings requested for the VF. */
11554 uint16_t num_cmpl_rings;
11555 /* The number of transmit rings requested for the VF. */
11556 uint16_t num_tx_rings;
11557 /* The number of receive rings requested for the VF. */
11558 uint16_t num_rx_rings;
11559 /* The number of L2 contexts requested for the VF. */
11560 uint16_t num_l2_ctxs;
11561 /* The number of vnics requested for the VF. */
11562 uint16_t num_vnics;
11563 /* The number of statistic contexts requested for the VF. */
11564 uint16_t num_stat_ctxs;
11565 /* The number of HW ring groups requested for the VF. */
11566 uint16_t num_hw_ring_grps;
11567 /* Number of Tx Key Contexts requested. */
11568 uint16_t num_tx_key_ctxs;
11569 /* Number of Rx Key Contexts requested. */
11570 uint16_t num_rx_key_ctxs;
11573 /* hwrm_func_vf_cfg_output (size:128b/16B) */
11574 struct hwrm_func_vf_cfg_output {
11575 /* The specific error status for the command. */
11576 uint16_t error_code;
11577 /* The HWRM command request type. */
11579 /* The sequence ID from the original command. */
11581 /* The length of the response data in number of bytes. */
11583 uint8_t unused_0[7];
11585 * This field is used in Output records to indicate that the output
11586 * is completely written to RAM. This field should be read as '1'
11587 * to indicate that the output has been completely written.
11588 * When writing a command completion or response to an internal processor,
11589 * the order of writes has to be such that this field is written last.
11594 /*******************
11595 * hwrm_func_qcaps *
11596 *******************/
11599 /* hwrm_func_qcaps_input (size:192b/24B) */
11600 struct hwrm_func_qcaps_input {
11601 /* The HWRM command request type. */
11604 * The completion ring to send the completion event on. This should
11605 * be the NQ ID returned from the `nq_alloc` HWRM command.
11607 uint16_t cmpl_ring;
11609 * The sequence ID is used by the driver for tracking multiple
11610 * commands. This ID is treated as opaque data by the firmware and
11611 * the value is returned in the `hwrm_resp_hdr` upon completion.
11615 * The target ID of the command:
11616 * * 0x0-0xFFF8 - The function ID
11617 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
11618 * * 0xFFFD - Reserved for user-space HWRM interface
11621 uint16_t target_id;
11623 * A physical address pointer pointing to a host buffer that the
11624 * command's response data will be written. This can be either a host
11625 * physical address (HPA) or a guest physical address (GPA) and must
11626 * point to a physically contiguous block of memory.
11628 uint64_t resp_addr;
11630 * Function ID of the function that is being queried.
11631 * 0xFF... (All Fs) if the query is for the requesting
11633 * 0xFFFE (REQUESTING_PARENT_FID) This is a special FID
11634 * to be used by a trusted VF to query its parent PF.
11637 uint8_t unused_0[6];
11640 /* hwrm_func_qcaps_output (size:768b/96B) */
11641 struct hwrm_func_qcaps_output {
11642 /* The specific error status for the command. */
11643 uint16_t error_code;
11644 /* The HWRM command request type. */
11646 /* The sequence ID from the original command. */
11648 /* The length of the response data in number of bytes. */
11651 * FID value. This value is used to identify operations on the PCI
11652 * bus as belonging to a particular PCI function.
11656 * Port ID of port that this function is associated with.
11657 * Valid only for the PF.
11658 * 0xFF... (All Fs) if this function is not associated with
11660 * 0xFF... (All Fs) if this function is called from a VF.
11664 /* If 1, then Push mode is supported on this function. */
11665 #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_PUSH_MODE_SUPPORTED \
11668 * If 1, then the global MSI-X auto-masking is enabled for the
11671 #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_GLOBAL_MSIX_AUTOMASKING \
11674 * If 1, then the Precision Time Protocol (PTP) processing
11675 * is supported on this function.
11676 * The HWRM should enable PTP on only a single Physical
11677 * Function (PF) per port.
11679 #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_PTP_SUPPORTED \
11682 * If 1, then RDMA over Converged Ethernet (RoCE) v1
11683 * is supported on this function.
11685 #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_ROCE_V1_SUPPORTED \
11688 * If 1, then RDMA over Converged Ethernet (RoCE) v2
11689 * is supported on this function.
11691 #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_ROCE_V2_SUPPORTED \
11694 * If 1, then control and configuration of WoL magic packet
11695 * are supported on this function.
11697 #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_WOL_MAGICPKT_SUPPORTED \
11700 * If 1, then control and configuration of bitmap pattern
11701 * packet are supported on this function.
11703 #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_WOL_BMP_SUPPORTED \
11706 * If set to 1, then the control and configuration of rate limit
11707 * of an allocated TX ring on the queried function is supported.
11709 #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_TX_RING_RL_SUPPORTED \
11712 * If 1, then control and configuration of minimum and
11713 * maximum bandwidths are supported on the queried function.
11715 #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_TX_BW_CFG_SUPPORTED \
11718 * If the query is for a VF, then this flag shall be ignored.
11719 * If this query is for a PF and this flag is set to 1,
11720 * then the PF has the capability to set the rate limits
11721 * on the TX rings of its children VFs.
11722 * If this query is for a PF and this flag is set to 0, then
11723 * the PF does not have the capability to set the rate limits
11724 * on the TX rings of its children VFs.
11726 #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_VF_TX_RING_RL_SUPPORTED \
11729 * If the query is for a VF, then this flag shall be ignored.
11730 * If this query is for a PF and this flag is set to 1,
11731 * then the PF has the capability to set the minimum and/or
11732 * maximum bandwidths for its children VFs.
11733 * If this query is for a PF and this flag is set to 0, then
11734 * the PF does not have the capability to set the minimum or
11735 * maximum bandwidths for its children VFs.
11737 #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_VF_BW_CFG_SUPPORTED \
11740 * Standard TX Ring mode is used for the allocation of TX ring
11741 * and underlying scheduling resources that allow bandwidth
11742 * reservation and limit settings on the queried function.
11743 * If set to 1, then standard TX ring mode is supported
11744 * on the queried function.
11745 * If set to 0, then standard TX ring mode is not available
11746 * on the queried function.
11748 #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_STD_TX_RING_MODE_SUPPORTED \
11751 * If the query is for a VF, then this flag shall be ignored,
11752 * If this query is for a PF and this flag is set to 1,
11753 * then the PF has the capability to detect GENEVE tunnel
11756 #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_GENEVE_TUN_FLAGS_SUPPORTED \
11759 * If the query is for a VF, then this flag shall be ignored,
11760 * If this query is for a PF and this flag is set to 1,
11761 * then the PF has the capability to detect NVGRE tunnel
11764 #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_NVGRE_TUN_FLAGS_SUPPORTED \
11767 * If the query is for a VF, then this flag shall be ignored,
11768 * If this query is for a PF and this flag is set to 1,
11769 * then the PF has the capability to detect GRE tunnel
11772 #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_GRE_TUN_FLAGS_SUPPORTED \
11775 * If the query is for a VF, then this flag shall be ignored,
11776 * If this query is for a PF and this flag is set to 1,
11777 * then the PF has the capability to detect MPLS tunnel
11780 #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_MPLS_TUN_FLAGS_SUPPORTED \
11783 * If the query is for a VF, then this flag shall be ignored,
11784 * If this query is for a PF and this flag is set to 1,
11785 * then the PF has the capability to support pcie stats.
11787 #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_PCIE_STATS_SUPPORTED \
11790 * If the query is for a VF, then this flag shall be ignored,
11791 * If this query is for a PF and this flag is set to 1,
11792 * then the PF has the capability to adopt the VF's belonging
11795 #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_ADOPTED_PF_SUPPORTED \
11798 * If the query is for a VF, then this flag shall be ignored,
11799 * If this query is for a PF and this flag is set to 1,
11800 * then the PF has the administrative privilege to configure another PF
11802 #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_ADMIN_PF_SUPPORTED \
11805 * If the query is for a VF, then this flag shall be ignored.
11806 * If this query is for a PF and this flag is set to 1, then
11807 * the PF will know that the firmware has the capability to track
11808 * the virtual link status.
11810 #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_LINK_ADMIN_STATUS_SUPPORTED \
11813 * If 1, then this function supports the push mode that uses
11814 * write combine buffers and the long inline tx buffer descriptor.
11816 #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_WCB_PUSH_MODE \
11819 * If 1, then FW has capability to allocate TX rings dynamically
11820 * in ring alloc even if PF reserved pool is zero.
11821 * This bit will be used only for PFs.
11823 #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_DYNAMIC_TX_RING_ALLOC \
11826 * When this bit is '1', it indicates that core firmware is
11827 * capable of Hot Reset.
11829 #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_HOT_RESET_CAPABLE \
11832 * This flag will be set to 1 by the FW if FW supports adapter error
11835 #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_ERROR_RECOVERY_CAPABLE \
11838 * If the query is for a VF, then this flag shall be ignored.
11839 * If this query is for a PF and this flag is set to 1, then
11840 * the PF has the capability to support extended stats.
11842 #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_EXT_STATS_SUPPORTED \
11843 UINT32_C(0x1000000)
11845 * If the query is for a VF, then this flag shall be ignored.
11846 * If this query is for a PF and this flag is set to 1, then host
11847 * must initiate reset or reload (or fastboot) the firmware image
11848 * upon detection of device shutdown state.
11850 #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_ERR_RECOVER_RELOAD \
11851 UINT32_C(0x2000000)
11853 * If the query is for a VF, then this flag (always set to 0) shall
11854 * be ignored. If this query is for a PF and this flag is set to 1,
11855 * host, when registered for the default vnic change async event,
11856 * receives async notification whenever a default vnic state is
11857 * changed for any of child or adopted VFs.
11859 #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_NOTIFY_VF_DEF_VNIC_CHNG_SUPPORTED \
11860 UINT32_C(0x4000000)
11861 /* If set to 1, then the vlan acceleration for TX is disabled. */
11862 #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_VLAN_ACCELERATION_TX_DISABLED \
11863 UINT32_C(0x8000000)
11865 * When this bit is '1', it indicates that core firmware supports
11866 * DBG_COREDUMP_XXX commands.
11868 #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_COREDUMP_CMD_SUPPORTED \
11869 UINT32_C(0x10000000)
11871 * When this bit is '1', it indicates that core firmware supports
11872 * DBG_CRASHDUMP_XXX commands.
11874 #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_CRASHDUMP_CMD_SUPPORTED \
11875 UINT32_C(0x20000000)
11877 * If the query is for a VF, then this flag should be ignored.
11878 * If the query is for a PF and this flag is set to 1, then
11879 * the PF has the capability to support retrieval of
11880 * rx_port_stats_ext_pfc_wd statistics (supported by the PFC
11881 * WatchDog feature) via the hwrm_port_qstats_ext_pfc_wd command.
11882 * If this flag is set to 1, only that (supported) command should
11883 * be used for retrieval of PFC related statistics (rather than
11884 * hwrm_port_qstats_ext command, which could previously be used).
11886 #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_PFC_WD_STATS_SUPPORTED \
11887 UINT32_C(0x40000000)
11889 * When this bit is '1', it indicates that core firmware supports
11890 * DBG_QCAPS command
11892 #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_DBG_QCAPS_CMD_SUPPORTED \
11893 UINT32_C(0x80000000)
11895 * This value is current MAC address configured for this
11896 * function. A value of 00-00-00-00-00-00 indicates no
11897 * MAC address is currently configured.
11899 uint8_t mac_address[6];
11901 * The maximum number of RSS/COS contexts that can be
11902 * allocated to the function.
11904 uint16_t max_rsscos_ctx;
11906 * The maximum number of completion rings that can be
11907 * allocated to the function.
11909 uint16_t max_cmpl_rings;
11911 * The maximum number of transmit rings that can be
11912 * allocated to the function.
11914 uint16_t max_tx_rings;
11916 * The maximum number of receive rings that can be
11917 * allocated to the function.
11919 uint16_t max_rx_rings;
11921 * The maximum number of L2 contexts that can be
11922 * allocated to the function.
11924 uint16_t max_l2_ctxs;
11926 * The maximum number of VNICs that can be
11927 * allocated to the function.
11929 uint16_t max_vnics;
11931 * The identifier for the first VF enabled on a PF. This
11932 * is valid only on the PF with SR-IOV enabled.
11933 * 0xFF... (All Fs) if this command is called on a PF with
11934 * SR-IOV disabled or on a VF.
11936 uint16_t first_vf_id;
11938 * The maximum number of VFs that can be
11939 * allocated to the function. This is valid only on the
11940 * PF with SR-IOV enabled. 0xFF... (All Fs) if this
11941 * command is called on a PF with SR-IOV disabled or
11946 * The maximum number of statistic contexts that can be
11947 * allocated to the function.
11949 uint16_t max_stat_ctx;
11951 * The maximum number of Encapsulation records that can be
11952 * offloaded by this function.
11954 uint32_t max_encap_records;
11956 * The maximum number of decapsulation records that can
11957 * be offloaded by this function.
11959 uint32_t max_decap_records;
11961 * The maximum number of Exact Match (EM) flows that can be
11962 * offloaded by this function on the TX side.
11964 uint32_t max_tx_em_flows;
11966 * The maximum number of Wildcard Match (WM) flows that can
11967 * be offloaded by this function on the TX side.
11969 uint32_t max_tx_wm_flows;
11971 * The maximum number of Exact Match (EM) flows that can be
11972 * offloaded by this function on the RX side.
11974 uint32_t max_rx_em_flows;
11976 * The maximum number of Wildcard Match (WM) flows that can
11977 * be offloaded by this function on the RX side.
11979 uint32_t max_rx_wm_flows;
11981 * The maximum number of multicast filters that can
11982 * be supported by this function on the RX side.
11984 uint32_t max_mcast_filters;
11986 * The maximum value of flow_id that can be supported
11987 * in completion records.
11989 uint32_t max_flow_id;
11991 * The maximum number of HW ring groups that can be
11992 * supported on this function.
11994 uint32_t max_hw_ring_grps;
11996 * The maximum number of strict priority transmit rings
11997 * that can be allocated to the function.
11998 * This number indicates the maximum number of TX rings
11999 * that can be assigned strict priorities out of the
12000 * maximum number of TX rings that can be allocated
12001 * (max_tx_rings) to the function.
12003 uint16_t max_sp_tx_rings;
12005 * The maximum number of MSI-X vectors that may be allocated across
12006 * all VFs for the function. This is valid only on the PF with SR-IOV
12007 * enabled. Returns zero if this command is called on a PF with
12008 * SR-IOV disabled or on a VF.
12010 uint16_t max_msix_vfs;
12011 uint32_t flags_ext;
12013 * If 1, the device can be configured to set the ECN bits in the
12014 * IP header of received packets if the receive queue length
12015 * exceeds a given threshold.
12017 #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_EXT_ECN_MARK_SUPPORTED \
12020 * If 1, the device can report the number of received packets
12021 * that it marked as having experienced congestion.
12023 #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_EXT_ECN_STATS_SUPPORTED \
12026 * If 1, the device can report extended hw statistics (including
12027 * additional tpa statistics).
12029 #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_EXT_EXT_HW_STATS_SUPPORTED \
12032 * If set to 1, then the core firmware has support to enable/
12033 * disable hot reset support for interface dynamically through
12036 #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_EXT_HOT_RESET_IF_SUPPORT \
12038 /* If 1, the proxy mode is supported on this function */
12039 #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_EXT_PROXY_MODE_SUPPORT \
12042 * If 1, the tx rings source interface override feature is supported
12043 * on this function.
12045 #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_EXT_TX_PROXY_SRC_INTF_OVERRIDE_SUPPORT \
12048 * If 1, the device supports scheduler queues. SCHQs can be managed
12049 * using RING_SCHQ_ALLOC/CFG/FREE commands.
12051 #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_EXT_SCHQ_SUPPORTED \
12054 * If set to 1, then this function supports the TX push mode that
12055 * uses ping-pong buffers from the push pages.
12057 #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_EXT_PPP_PUSH_MODE_SUPPORTED \
12060 * If set to 1, then this function doesn't have the privilege to
12061 * configure the EVB mode of the port it uses.
12063 #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_EXT_EVB_MODE_CFG_NOT_SUPPORTED \
12066 * If set to 1, then the HW and FW support the SoC packet DMA
12067 * datapath between SoC and NIC. This function can act as the
12068 * HWRM communication transport agent on behalf of the SoC SPD
12069 * software module. This capability is only advertised to the
12072 #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_EXT_SOC_SPD_SUPPORTED \
12075 * If set to 1, then this function supports FW_LIVEPATCH for
12076 * firmware livepatch commands.
12078 #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_EXT_FW_LIVEPATCH_SUPPORTED \
12081 * When this bit is '1', it indicates that core firmware is
12082 * capable of fast Reset.
12084 #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_EXT_FAST_RESET_CAPABLE \
12087 * When this bit is '1', it indicates that firmware and hardware
12088 * are capable of updating tx_metadata via hwrm_ring_cfg command.
12090 #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_EXT_TX_METADATA_CFG_CAPABLE \
12093 * If set to 1, then the device can report the action
12094 * needed to activate set nvm options.
12096 #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_EXT_NVM_OPTION_ACTION_SUPPORTED \
12099 * When this bit is '1', it indicates that the BD metadata feature
12100 * is supported for this function.
12102 #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_EXT_BD_METADATA_SUPPORTED \
12105 * When this bit is '1', it indicates that the echo request feature
12106 * is supported for this function. If the driver registers for the
12107 * echo request asynchronous event, then the firmware can send an
12108 * unsolicited echo request to the driver and expect an echo
12111 #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_EXT_ECHO_REQUEST_SUPPORTED \
12114 * When this bit is '1', it indicates that core firmware supports
12115 * NPAR 1.2 on this function.
12117 #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_EXT_NPAR_1_2_SUPPORTED \
12119 /* When this bit is '1', it indicates that PTM feature is supported. */
12120 #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_EXT_PTP_PTM_SUPPORTED \
12122 /* When this bit is '1', it indicates that PPS feature is supported. */
12123 #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_EXT_PTP_PPS_SUPPORTED \
12126 * When this bit is '1', it indicates that VF config. change
12127 * async event is supported on the parent PF if the async.
12128 * event is registered by the PF.
12130 #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_EXT_VF_CFG_ASYNC_FOR_PF_SUPPORTED \
12133 * When this bit is '1', the NIC supports configuration of
12134 * partition_min_bw and partition_max_bw. Configuration of a
12135 * minimum guaranteed bandwidth is only supported if the
12136 * min_bw_supported flag is also set.
12138 #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_EXT_PARTITION_BW_SUPPORTED \
12141 * When this bit is '1', the FW supports configuration of
12142 * PCP and TPID values of the default VLAN.
12144 #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_EXT_DFLT_VLAN_TPID_PCP_SUPPORTED \
12146 /* When this bit is '1', it indicates that HW and FW support KTLS. */
12147 #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_EXT_KTLS_SUPPORTED \
12150 * When this bit is '1', the firmware supports HWRM_PORT_EP_TX_CFG
12151 * and HWRM_PORT_EP_TX_QCFG for endpoint rate control, and additions
12152 * to HWRM_QUEUE_GLOBAL_CFG and HWRM_QUEUE_GLOBAL_QCFG for receive
12153 * rate control. Configuration of a minimum guaranteed bandwidth
12154 * is only supported if the min_bw_supported flag is also set.
12156 #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_EXT_EP_RATE_CONTROL \
12159 * When this bit is '1', the firmware supports enforcement of
12160 * minimum guaranteed bandwidth. A minimum guaranteed bandwidth
12161 * could be configured for a partition or for an endpoint. Firmware
12162 * only sets this flag if one or both of the ep_rate_control and
12163 * partition_bw_supported flags are set.
12165 #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_EXT_MIN_BW_SUPPORTED \
12166 UINT32_C(0x1000000)
12168 * When this bit is '1', HW supports TX coalesced completion
12171 #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_EXT_TX_COAL_CMPL_CAP \
12172 UINT32_C(0x2000000)
12174 * When this bit is '1', it indicates the FW has full support
12175 * for all backing store types with the BACKING_STORE_CFG/QCFG
12178 #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_EXT_BS_V2_SUPPORTED \
12179 UINT32_C(0x4000000)
12181 * When this bit is '1', it indicates the FW forces to use the
12182 * BACKING_STORE_CFG/QCFG V2 APIs.
12184 #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_EXT_BS_V2_REQUIRED \
12185 UINT32_C(0x8000000)
12186 /* The maximum number of SCHQs supported by this device. */
12188 uint8_t mpc_chnls_cap;
12190 * When this bit is '1', it indicates that HW and firmware
12191 * supports the use of a MPC channel with destination set
12192 * to the TX crypto engine block.
12194 #define HWRM_FUNC_QCAPS_OUTPUT_MPC_CHNLS_CAP_TCE UINT32_C(0x1)
12196 * When this bit is '1', it indicates that HW and firmware
12197 * supports the use of a MPC channel with destination set
12198 * to the RX crypto engine block.
12200 #define HWRM_FUNC_QCAPS_OUTPUT_MPC_CHNLS_CAP_RCE UINT32_C(0x2)
12202 * When this bit is '1', it indicates that HW and firmware
12203 * supports the use of a MPC channel with destination set
12204 * to the TX configurable flow processing block.
12206 #define HWRM_FUNC_QCAPS_OUTPUT_MPC_CHNLS_CAP_TE_CFA UINT32_C(0x4)
12208 * When this bit is '1', it indicates that HW and firmware
12209 * supports the use of a MPC channel with destination set
12210 * to the RX configurable flow processing block.
12212 #define HWRM_FUNC_QCAPS_OUTPUT_MPC_CHNLS_CAP_RE_CFA UINT32_C(0x8)
12214 * When this bit is '1', it indicates that HW and firmware
12215 * supports the use of a MPC channel with destination set
12216 * to the primate processor block.
12218 #define HWRM_FUNC_QCAPS_OUTPUT_MPC_CHNLS_CAP_PRIMATE UINT32_C(0x10)
12220 * Maximum number of Key Contexts supported per HWRM
12221 * function call for allocating Key Contexts.
12223 uint16_t max_key_ctxs_alloc;
12224 uint8_t unused_1[7];
12226 * This field is used in Output records to indicate that the output
12227 * is completely written to RAM. This field should be read as '1'
12228 * to indicate that the output has been completely written.
12229 * When writing a command completion or response to an internal
12230 * processor, the order of writes has to be such that this field is
12236 /******************
12238 ******************/
12241 /* hwrm_func_qcfg_input (size:192b/24B) */
12242 struct hwrm_func_qcfg_input {
12243 /* The HWRM command request type. */
12246 * The completion ring to send the completion event on. This should
12247 * be the NQ ID returned from the `nq_alloc` HWRM command.
12249 uint16_t cmpl_ring;
12251 * The sequence ID is used by the driver for tracking multiple
12252 * commands. This ID is treated as opaque data by the firmware and
12253 * the value is returned in the `hwrm_resp_hdr` upon completion.
12257 * The target ID of the command:
12258 * * 0x0-0xFFF8 - The function ID
12259 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
12260 * * 0xFFFD - Reserved for user-space HWRM interface
12263 uint16_t target_id;
12265 * A physical address pointer pointing to a host buffer that the
12266 * command's response data will be written. This can be either a host
12267 * physical address (HPA) or a guest physical address (GPA) and must
12268 * point to a physically contiguous block of memory.
12270 uint64_t resp_addr;
12272 * Function ID of the function that is being queried.
12273 * 0xFF... (All Fs) if the query is for the requesting
12275 * 0xFFFE (REQUESTING_PARENT_FID) This is a special FID
12276 * to be used by a trusted VF to query its parent PF.
12279 uint8_t unused_0[6];
12282 /* hwrm_func_qcfg_output (size:896b/112B) */
12283 struct hwrm_func_qcfg_output {
12284 /* The specific error status for the command. */
12285 uint16_t error_code;
12286 /* The HWRM command request type. */
12288 /* The sequence ID from the original command. */
12290 /* The length of the response data in number of bytes. */
12293 * FID value. This value is used to identify operations on the PCI
12294 * bus as belonging to a particular PCI function.
12298 * Port ID of port that this function is associated with.
12299 * 0xFF... (All Fs) if this function is not associated with
12304 * This value is the current VLAN setting for this
12305 * function. The value of 0 for this field indicates
12306 * no priority tagging or VLAN is used.
12307 * This field's format is same as 802.1Q Tag's
12308 * Tag Control Information (TCI) format that includes both
12309 * Priority Code Point (PCP) and VLAN Identifier (VID).
12314 * If 1, then magic packet based Out-Of-Box WoL is enabled on
12315 * the port associated with this function.
12317 #define HWRM_FUNC_QCFG_OUTPUT_FLAGS_OOB_WOL_MAGICPKT_ENABLED \
12320 * If 1, then bitmap pattern based Out-Of-Box WoL packet is enabled
12321 * on the port associated with this function.
12323 #define HWRM_FUNC_QCFG_OUTPUT_FLAGS_OOB_WOL_BMP_ENABLED \
12326 * If set to 1, then FW based DCBX agent is enabled and running on
12327 * the port associated with this function.
12328 * If set to 0, then DCBX agent is not running in the firmware.
12330 #define HWRM_FUNC_QCFG_OUTPUT_FLAGS_FW_DCBX_AGENT_ENABLED \
12333 * Standard TX Ring mode is used for the allocation of TX ring
12334 * and underlying scheduling resources that allow bandwidth
12335 * reservation and limit settings on the queried function.
12336 * If set to 1, then standard TX ring mode is enabled
12337 * on the queried function.
12338 * If set to 0, then the standard TX ring mode is disabled
12339 * on the queried function. In this extended TX ring resource
12340 * mode, the minimum and maximum bandwidth settings are not
12341 * supported to allow the allocation of TX rings to span multiple
12344 #define HWRM_FUNC_QCFG_OUTPUT_FLAGS_STD_TX_RING_MODE_ENABLED \
12347 * If set to 1 then FW based LLDP agent is enabled and running on
12348 * the port associated with this function.
12349 * If set to 0 then the LLDP agent is not running in the firmware.
12351 #define HWRM_FUNC_QCFG_OUTPUT_FLAGS_FW_LLDP_AGENT_ENABLED \
12354 * If set to 1, then multi-host mode is active for this function.
12355 * The NIC is attached to two or more independent host systems
12356 * through two or more PCIe endpoints.
12357 * If set to 0, then multi-host mode is inactive for this function
12358 * or not applicable for this device.
12360 #define HWRM_FUNC_QCFG_OUTPUT_FLAGS_MULTI_HOST \
12363 * If the function that is being queried is a PF, then the HWRM shall
12364 * set this field to 0 and the HWRM client shall ignore this field.
12365 * If the function that is being queried is a VF, then the HWRM shall
12366 * set this field to 1 if the queried VF is trusted, otherwise the HWRM
12367 * shall set this field to 0.
12369 #define HWRM_FUNC_QCFG_OUTPUT_FLAGS_TRUSTED_VF \
12372 * If set to 1, then secure mode is enabled for this function or device.
12373 * If set to 0, then secure mode is disabled (or normal mode) for this
12374 * function or device.
12376 #define HWRM_FUNC_QCFG_OUTPUT_FLAGS_SECURE_MODE_ENABLED \
12379 * If set to 1, then this PF is enabled with a preboot driver that
12380 * requires access to the legacy L2 ring model and legacy 32b
12381 * doorbells. If set to 0, then this PF is not allowed to use
12382 * the legacy L2 rings. This feature is not allowed on VFs and
12383 * is only relevant for devices that require a context backing
12386 #define HWRM_FUNC_QCFG_OUTPUT_FLAGS_PREBOOT_LEGACY_L2_RINGS \
12389 * If set to 1, then the firmware and all currently registered driver
12390 * instances support hot reset. The hot reset support will be updated
12391 * dynamically based on the driver interface advertisement.
12392 * If set to 0, then the adapter is not currently able to initiate
12395 #define HWRM_FUNC_QCFG_OUTPUT_FLAGS_HOT_RESET_ALLOWED \
12398 * If set to 1, then the PPP tx push mode is enabled for all the
12399 * reserved TX rings of this function. If set to 0, then PPP tx push
12400 * mode is disabled for all the reserved TX rings of this function.
12402 #define HWRM_FUNC_QCFG_OUTPUT_FLAGS_PPP_PUSH_MODE_ENABLED \
12405 * If set to 1, then the firmware will notify driver using async
12406 * event when a ring is disabled due to a Hardware error.
12408 #define HWRM_FUNC_QCFG_OUTPUT_FLAGS_RING_MONITOR_ENABLED \
12411 * If set to 1, then the firmware and all currently registered driver
12412 * instances support fast reset. The fast reset support will be
12413 * updated dynamically based on the driver interface advertisement.
12414 * If set to 0, then the adapter is not currently able to initiate
12417 #define HWRM_FUNC_QCFG_OUTPUT_FLAGS_FAST_RESET_ALLOWED \
12420 * If set to 1, then multi-root mode is active for this function.
12421 * The NIC is attached to a single host with a single operating
12422 * system, but through two or more PCIe endpoints.
12423 * If set to 0, then multi-root mode is inactive for this function
12424 * or not applicable for this device.
12426 #define HWRM_FUNC_QCFG_OUTPUT_FLAGS_MULTI_ROOT \
12429 * This flag indicates RDMA support for child VFS of
12430 * a physical function.
12431 * If set to 1, RoCE is supported on all child VFs.
12432 * If set to 0, RoCE is disabled on all child VFs.
12434 #define HWRM_FUNC_QCFG_OUTPUT_FLAGS_ENABLE_RDMA_SRIOV \
12437 * This value is current MAC address configured for this
12438 * function. A value of 00-00-00-00-00-00 indicates no
12439 * MAC address is currently configured.
12441 uint8_t mac_address[6];
12443 * This value is current PCI ID of this
12444 * function. If ARI is enabled, then it is
12445 * Bus Number (8b):Function Number(8b). Otherwise, it is
12446 * Bus Number (8b):Device Number (4b):Function Number(4b).
12447 * If multi-host mode is active, the 4 lsb will indicate
12448 * the PF index for this function.
12452 * The number of RSS/COS contexts currently
12453 * allocated to the function.
12455 uint16_t alloc_rsscos_ctx;
12457 * The number of completion rings currently allocated to
12458 * the function. This does not include the rings allocated
12459 * to any children functions if any.
12461 uint16_t alloc_cmpl_rings;
12463 * The number of transmit rings currently allocated to
12464 * the function. This does not include the rings allocated
12465 * to any children functions if any.
12467 uint16_t alloc_tx_rings;
12469 * The number of receive rings currently allocated to
12470 * the function. This does not include the rings allocated
12471 * to any children functions if any.
12473 uint16_t alloc_rx_rings;
12474 /* The allocated number of L2 contexts to the function. */
12475 uint16_t alloc_l2_ctx;
12476 /* The allocated number of vnics to the function. */
12477 uint16_t alloc_vnics;
12479 * The maximum transmission unit of the function
12480 * configured by the admin pf.
12481 * If the reported mtu value is non-zero then it will be used for the
12482 * rings allocated on this function, otherwise the default
12483 * value is used if ring MTU is not specified.
12484 * The driver cannot use any MTU bigger than this value
12485 * if it is non-zero.
12487 uint16_t admin_mtu;
12489 * The maximum receive unit of the function.
12490 * For vnics allocated on this function, this default
12491 * value is used if vnic MRU is not specified.
12494 /* The statistics context assigned to a function. */
12495 uint16_t stat_ctx_id;
12497 * The HWRM shall return Unknown value for this field
12498 * when this command is used to query VF's configuration.
12500 uint8_t port_partition_type;
12501 /* Single physical function */
12502 #define HWRM_FUNC_QCFG_OUTPUT_PORT_PARTITION_TYPE_SPF UINT32_C(0x0)
12503 /* Multiple physical functions */
12504 #define HWRM_FUNC_QCFG_OUTPUT_PORT_PARTITION_TYPE_MPFS UINT32_C(0x1)
12505 /* Network Partitioning 1.0 */
12506 #define HWRM_FUNC_QCFG_OUTPUT_PORT_PARTITION_TYPE_NPAR1_0 UINT32_C(0x2)
12507 /* Network Partitioning 1.5 */
12508 #define HWRM_FUNC_QCFG_OUTPUT_PORT_PARTITION_TYPE_NPAR1_5 UINT32_C(0x3)
12509 /* Network Partitioning 2.0 */
12510 #define HWRM_FUNC_QCFG_OUTPUT_PORT_PARTITION_TYPE_NPAR2_0 UINT32_C(0x4)
12511 /* Network Partitioning 1.2 */
12512 #define HWRM_FUNC_QCFG_OUTPUT_PORT_PARTITION_TYPE_NPAR1_2 UINT32_C(0x5)
12514 #define HWRM_FUNC_QCFG_OUTPUT_PORT_PARTITION_TYPE_UNKNOWN \
12516 #define HWRM_FUNC_QCFG_OUTPUT_PORT_PARTITION_TYPE_LAST \
12517 HWRM_FUNC_QCFG_OUTPUT_PORT_PARTITION_TYPE_UNKNOWN
12519 * This field will indicate number of physical functions on this port_partition.
12520 * HWRM shall return unavail (i.e. value of 0) for this field
12521 * when this command is used to query VF's configuration or
12522 * from older firmware that doesn't support this field.
12524 uint8_t port_pf_cnt;
12525 /* number of PFs is not available */
12526 #define HWRM_FUNC_QCFG_OUTPUT_PORT_PF_CNT_UNAVAIL UINT32_C(0x0)
12527 #define HWRM_FUNC_QCFG_OUTPUT_PORT_PF_CNT_LAST \
12528 HWRM_FUNC_QCFG_OUTPUT_PORT_PF_CNT_UNAVAIL
12530 * The default VNIC ID assigned to a function that is
12533 uint16_t dflt_vnic_id;
12534 uint16_t max_mtu_configured;
12536 * Minimum guaranteed transmit bandwidth for this function. When
12537 * specified for a PF, does not affect traffic from the PF's child VFs.
12538 * A value of 0 indicates the minimum bandwidth is not configured.
12541 /* The bandwidth value. */
12542 #define HWRM_FUNC_QCFG_OUTPUT_MIN_BW_BW_VALUE_MASK \
12543 UINT32_C(0xfffffff)
12544 #define HWRM_FUNC_QCFG_OUTPUT_MIN_BW_BW_VALUE_SFT 0
12545 /* The granularity of the value (bits or bytes). */
12546 #define HWRM_FUNC_QCFG_OUTPUT_MIN_BW_SCALE \
12547 UINT32_C(0x10000000)
12548 /* Value is in bits. */
12549 #define HWRM_FUNC_QCFG_OUTPUT_MIN_BW_SCALE_BITS \
12550 (UINT32_C(0x0) << 28)
12551 /* Value is in bytes. */
12552 #define HWRM_FUNC_QCFG_OUTPUT_MIN_BW_SCALE_BYTES \
12553 (UINT32_C(0x1) << 28)
12554 #define HWRM_FUNC_QCFG_OUTPUT_MIN_BW_SCALE_LAST \
12555 HWRM_FUNC_QCFG_OUTPUT_MIN_BW_SCALE_BYTES
12556 /* bw_value_unit is 3 b */
12557 #define HWRM_FUNC_QCFG_OUTPUT_MIN_BW_BW_VALUE_UNIT_MASK \
12558 UINT32_C(0xe0000000)
12559 #define HWRM_FUNC_QCFG_OUTPUT_MIN_BW_BW_VALUE_UNIT_SFT 29
12560 /* Value is in Mb or MB (base 10). */
12561 #define HWRM_FUNC_QCFG_OUTPUT_MIN_BW_BW_VALUE_UNIT_MEGA \
12562 (UINT32_C(0x0) << 29)
12563 /* Value is in Kb or KB (base 10). */
12564 #define HWRM_FUNC_QCFG_OUTPUT_MIN_BW_BW_VALUE_UNIT_KILO \
12565 (UINT32_C(0x2) << 29)
12566 /* Value is in bits or bytes. */
12567 #define HWRM_FUNC_QCFG_OUTPUT_MIN_BW_BW_VALUE_UNIT_BASE \
12568 (UINT32_C(0x4) << 29)
12569 /* Value is in Gb or GB (base 10). */
12570 #define HWRM_FUNC_QCFG_OUTPUT_MIN_BW_BW_VALUE_UNIT_GIGA \
12571 (UINT32_C(0x6) << 29)
12572 /* Value is in 1/100th of a percentage of link bandwidth. */
12573 #define HWRM_FUNC_QCFG_OUTPUT_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 \
12574 (UINT32_C(0x1) << 29)
12576 #define HWRM_FUNC_QCFG_OUTPUT_MIN_BW_BW_VALUE_UNIT_INVALID \
12577 (UINT32_C(0x7) << 29)
12578 #define HWRM_FUNC_QCFG_OUTPUT_MIN_BW_BW_VALUE_UNIT_LAST \
12579 HWRM_FUNC_QCFG_OUTPUT_MIN_BW_BW_VALUE_UNIT_INVALID
12581 * Maximum transmit rate for this function. When specified for a PF,
12582 * does not affect traffic from the PF's child VFs.
12583 * A value of 0 indicates that the maximum bandwidth is not configured.
12586 /* The bandwidth value. */
12587 #define HWRM_FUNC_QCFG_OUTPUT_MAX_BW_BW_VALUE_MASK \
12588 UINT32_C(0xfffffff)
12589 #define HWRM_FUNC_QCFG_OUTPUT_MAX_BW_BW_VALUE_SFT 0
12590 /* The granularity of the value (bits or bytes). */
12591 #define HWRM_FUNC_QCFG_OUTPUT_MAX_BW_SCALE \
12592 UINT32_C(0x10000000)
12593 /* Value is in bits. */
12594 #define HWRM_FUNC_QCFG_OUTPUT_MAX_BW_SCALE_BITS \
12595 (UINT32_C(0x0) << 28)
12596 /* Value is in bytes. */
12597 #define HWRM_FUNC_QCFG_OUTPUT_MAX_BW_SCALE_BYTES \
12598 (UINT32_C(0x1) << 28)
12599 #define HWRM_FUNC_QCFG_OUTPUT_MAX_BW_SCALE_LAST \
12600 HWRM_FUNC_QCFG_OUTPUT_MAX_BW_SCALE_BYTES
12601 /* bw_value_unit is 3 b */
12602 #define HWRM_FUNC_QCFG_OUTPUT_MAX_BW_BW_VALUE_UNIT_MASK \
12603 UINT32_C(0xe0000000)
12604 #define HWRM_FUNC_QCFG_OUTPUT_MAX_BW_BW_VALUE_UNIT_SFT 29
12605 /* Value is in Mb or MB (base 10). */
12606 #define HWRM_FUNC_QCFG_OUTPUT_MAX_BW_BW_VALUE_UNIT_MEGA \
12607 (UINT32_C(0x0) << 29)
12608 /* Value is in Kb or KB (base 10). */
12609 #define HWRM_FUNC_QCFG_OUTPUT_MAX_BW_BW_VALUE_UNIT_KILO \
12610 (UINT32_C(0x2) << 29)
12611 /* Value is in bits or bytes. */
12612 #define HWRM_FUNC_QCFG_OUTPUT_MAX_BW_BW_VALUE_UNIT_BASE \
12613 (UINT32_C(0x4) << 29)
12614 /* Value is in Gb or GB (base 10). */
12615 #define HWRM_FUNC_QCFG_OUTPUT_MAX_BW_BW_VALUE_UNIT_GIGA \
12616 (UINT32_C(0x6) << 29)
12617 /* Value is in 1/100th of a percentage of link bandwidth. */
12618 #define HWRM_FUNC_QCFG_OUTPUT_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 \
12619 (UINT32_C(0x1) << 29)
12621 #define HWRM_FUNC_QCFG_OUTPUT_MAX_BW_BW_VALUE_UNIT_INVALID \
12622 (UINT32_C(0x7) << 29)
12623 #define HWRM_FUNC_QCFG_OUTPUT_MAX_BW_BW_VALUE_UNIT_LAST \
12624 HWRM_FUNC_QCFG_OUTPUT_MAX_BW_BW_VALUE_UNIT_INVALID
12626 * This value indicates the Edge virtual bridge mode for the
12627 * domain that this function belongs to.
12630 /* No Edge Virtual Bridging (EVB) */
12631 #define HWRM_FUNC_QCFG_OUTPUT_EVB_MODE_NO_EVB UINT32_C(0x0)
12632 /* Virtual Ethernet Bridge (VEB) */
12633 #define HWRM_FUNC_QCFG_OUTPUT_EVB_MODE_VEB UINT32_C(0x1)
12634 /* Virtual Ethernet Port Aggregator (VEPA) */
12635 #define HWRM_FUNC_QCFG_OUTPUT_EVB_MODE_VEPA UINT32_C(0x2)
12636 #define HWRM_FUNC_QCFG_OUTPUT_EVB_MODE_LAST \
12637 HWRM_FUNC_QCFG_OUTPUT_EVB_MODE_VEPA
12640 * This value indicates the PCIE device cache line size.
12641 * The cache line size allows the DMA writes to terminate and
12642 * start at the cache boundary.
12644 #define HWRM_FUNC_QCFG_OUTPUT_OPTIONS_CACHE_LINESIZE_MASK \
12646 #define HWRM_FUNC_QCFG_OUTPUT_OPTIONS_CACHE_LINESIZE_SFT 0
12647 /* Cache Line Size 64 bytes */
12648 #define HWRM_FUNC_QCFG_OUTPUT_OPTIONS_CACHE_LINESIZE_SIZE_64 \
12650 /* Cache Line Size 128 bytes */
12651 #define HWRM_FUNC_QCFG_OUTPUT_OPTIONS_CACHE_LINESIZE_SIZE_128 \
12653 #define HWRM_FUNC_QCFG_OUTPUT_OPTIONS_CACHE_LINESIZE_LAST \
12654 HWRM_FUNC_QCFG_OUTPUT_OPTIONS_CACHE_LINESIZE_SIZE_128
12655 /* This value is the virtual link admin state setting. */
12656 #define HWRM_FUNC_QCFG_OUTPUT_OPTIONS_LINK_ADMIN_STATE_MASK \
12658 #define HWRM_FUNC_QCFG_OUTPUT_OPTIONS_LINK_ADMIN_STATE_SFT 2
12659 /* Admin link state is in forced down mode. */
12660 #define HWRM_FUNC_QCFG_OUTPUT_OPTIONS_LINK_ADMIN_STATE_FORCED_DOWN \
12661 (UINT32_C(0x0) << 2)
12662 /* Admin link state is in forced up mode. */
12663 #define HWRM_FUNC_QCFG_OUTPUT_OPTIONS_LINK_ADMIN_STATE_FORCED_UP \
12664 (UINT32_C(0x1) << 2)
12665 /* Admin link state is in auto mode - follows the physical link state. */
12666 #define HWRM_FUNC_QCFG_OUTPUT_OPTIONS_LINK_ADMIN_STATE_AUTO \
12667 (UINT32_C(0x2) << 2)
12668 #define HWRM_FUNC_QCFG_OUTPUT_OPTIONS_LINK_ADMIN_STATE_LAST \
12669 HWRM_FUNC_QCFG_OUTPUT_OPTIONS_LINK_ADMIN_STATE_AUTO
12670 /* Reserved for future. */
12671 #define HWRM_FUNC_QCFG_OUTPUT_OPTIONS_RSVD_MASK \
12673 #define HWRM_FUNC_QCFG_OUTPUT_OPTIONS_RSVD_SFT 4
12675 * The number of VFs that are allocated to the function.
12676 * This is valid only on the PF with SR-IOV enabled.
12677 * 0xFF... (All Fs) if this command is called on a PF with
12678 * SR-IOV disabled or on a VF.
12680 uint16_t alloc_vfs;
12682 * The number of allocated multicast filters for this
12683 * function on the RX side.
12685 uint32_t alloc_mcast_filters;
12687 * The number of allocated HW ring groups for this
12690 uint32_t alloc_hw_ring_grps;
12692 * The number of strict priority transmit rings out of
12693 * currently allocated TX rings to the function
12694 * (alloc_tx_rings).
12696 uint16_t alloc_sp_tx_rings;
12698 * The number of statistics contexts
12699 * currently reserved for the function.
12701 uint16_t alloc_stat_ctx;
12703 * This field specifies how many NQs are reserved for the PF.
12704 * Remaining NQs that belong to the PF are available for VFs.
12705 * Once a PF has created VFs, it cannot change how many NQs are
12706 * reserved for itself (since the NQs must be contiguous in HW).
12708 uint16_t alloc_msix;
12710 * The number of registered VF’s associated with the PF. This field
12711 * should be ignored when the request received on the VF interface.
12712 * This field will be updated on the PF interface to initiate
12713 * the unregister request on PF in the HOT Reset Process.
12715 uint16_t registered_vfs;
12717 * The size of the doorbell BAR in KBytes reserved for L2 including
12718 * any area that is shared between L2 and RoCE. The L2 driver
12719 * should only map the L2 portion of the doorbell BAR. Any rounding
12720 * of the BAR size to the native CPU page size should be performed
12721 * by the driver. If the value is zero, no special partitioning
12722 * of the doorbell BAR between L2 and RoCE is required.
12724 uint16_t l2_doorbell_bar_size_kb;
12727 * For backward compatibility this field must be set to 1.
12728 * Older drivers might look for this field to be 1 before
12729 * processing the message.
12733 * This GRC address location is used by the Host driver interfaces to poll
12734 * the adapter ready state to re-initiate the registration process again
12735 * after receiving the RESET Notify event.
12737 uint32_t reset_addr_poll;
12739 * This field specifies legacy L2 doorbell size in KBytes. Drivers should use
12740 * this value to find out the doorbell page offset from the BAR.
12742 uint16_t legacy_l2_db_size_kb;
12743 uint16_t svif_info;
12745 * This field specifies the source virtual interface of the function being
12746 * queried. Drivers can use this to program svif field in the L2 context
12749 #define HWRM_FUNC_QCFG_OUTPUT_SVIF_INFO_SVIF_MASK UINT32_C(0x7fff)
12750 #define HWRM_FUNC_QCFG_OUTPUT_SVIF_INFO_SVIF_SFT 0
12751 /* This field specifies whether svif is valid or not */
12752 #define HWRM_FUNC_QCFG_OUTPUT_SVIF_INFO_SVIF_VALID UINT32_C(0x8000)
12755 * When this bit is '1', it indicates that a MPC channel with
12756 * destination set to the TX crypto engine block is enabled.
12758 #define HWRM_FUNC_QCFG_OUTPUT_MPC_CHNLS_TCE_ENABLED \
12761 * When this bit is '1', it indicates that a MPC channel with
12762 * destination set to the RX crypto engine block is enabled.
12764 #define HWRM_FUNC_QCFG_OUTPUT_MPC_CHNLS_RCE_ENABLED \
12767 * When this bit is '1', it indicates that a MPC channel with
12768 * destination set to the TX configurable flow processing block is
12771 #define HWRM_FUNC_QCFG_OUTPUT_MPC_CHNLS_TE_CFA_ENABLED \
12774 * When this bit is '1', it indicates that a MPC channel with
12775 * destination set to the RX configurable flow processing block is
12778 #define HWRM_FUNC_QCFG_OUTPUT_MPC_CHNLS_RE_CFA_ENABLED \
12781 * When this bit is '1', it indicates that a MPC channel with
12782 * destination set to the primate processor block is enabled.
12784 #define HWRM_FUNC_QCFG_OUTPUT_MPC_CHNLS_PRIMATE_ENABLED \
12786 uint8_t unused_2[3];
12788 * Minimum guaranteed bandwidth for the network partition made up
12789 * of the caller physical function and all its child virtual
12790 * functions. The rate is specified as a percentage of the bandwidth
12791 * of the link the partition is associated with. A value of 0
12792 * indicates that no minimum bandwidth is configured.
12793 * The format of this field is defined to match min_bw, even though
12794 * the partition minimum rate is always specified as a percentage.
12796 uint32_t partition_min_bw;
12797 /* The bandwidth value. */
12798 #define HWRM_FUNC_QCFG_OUTPUT_PARTITION_MIN_BW_BW_VALUE_MASK \
12799 UINT32_C(0xfffffff)
12800 #define HWRM_FUNC_QCFG_OUTPUT_PARTITION_MIN_BW_BW_VALUE_SFT \
12803 * The granularity of the value (bits or bytes). Firmware never sets
12806 #define HWRM_FUNC_QCFG_OUTPUT_PARTITION_MIN_BW_SCALE \
12807 UINT32_C(0x10000000)
12808 /* Value is in bits. */
12809 #define HWRM_FUNC_QCFG_OUTPUT_PARTITION_MIN_BW_SCALE_BITS \
12810 (UINT32_C(0x0) << 28)
12811 /* Value is in bytes. */
12812 #define HWRM_FUNC_QCFG_OUTPUT_PARTITION_MIN_BW_SCALE_BYTES \
12813 (UINT32_C(0x1) << 28)
12814 #define HWRM_FUNC_QCFG_OUTPUT_PARTITION_MIN_BW_SCALE_LAST \
12815 HWRM_FUNC_QCFG_OUTPUT_PARTITION_MIN_BW_SCALE_BYTES
12816 /* Always percentage of link bandwidth. */
12817 #define HWRM_FUNC_QCFG_OUTPUT_PARTITION_MIN_BW_BW_VALUE_UNIT_MASK \
12818 UINT32_C(0xe0000000)
12819 #define HWRM_FUNC_QCFG_OUTPUT_PARTITION_MIN_BW_BW_VALUE_UNIT_SFT \
12821 /* Bandwidth value is in hundredths of a percent of link bandwidth. */
12822 #define HWRM_FUNC_QCFG_OUTPUT_PARTITION_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 \
12823 (UINT32_C(0x1) << 29)
12824 #define HWRM_FUNC_QCFG_OUTPUT_PARTITION_MIN_BW_BW_VALUE_UNIT_LAST \
12825 HWRM_FUNC_QCFG_OUTPUT_PARTITION_MIN_BW_BW_VALUE_UNIT_PERCENT1_100
12827 * The maximum bandwidth that may be used by the network partition
12828 * made up of the caller physical function and all its child virtual
12829 * functions. The rate is specified as a percentage of the bandwidth
12830 * of the link the partition is associated with. A value of 0
12831 * indicates that no maximum bandwidth is configured.
12832 * The format of this field is defined to match max_bw, even though
12833 * the partition bandwidth must be specified as a percentage.
12835 uint32_t partition_max_bw;
12836 /* The bandwidth value. */
12837 #define HWRM_FUNC_QCFG_OUTPUT_PARTITION_MAX_BW_BW_VALUE_MASK \
12838 UINT32_C(0xfffffff)
12839 #define HWRM_FUNC_QCFG_OUTPUT_PARTITION_MAX_BW_BW_VALUE_SFT \
12842 * The granularity of the value (bits or bytes). Firmware never sets
12845 #define HWRM_FUNC_QCFG_OUTPUT_PARTITION_MAX_BW_SCALE \
12846 UINT32_C(0x10000000)
12847 /* Value is in bits. */
12848 #define HWRM_FUNC_QCFG_OUTPUT_PARTITION_MAX_BW_SCALE_BITS \
12849 (UINT32_C(0x0) << 28)
12850 /* Value is in bytes. */
12851 #define HWRM_FUNC_QCFG_OUTPUT_PARTITION_MAX_BW_SCALE_BYTES \
12852 (UINT32_C(0x1) << 28)
12853 #define HWRM_FUNC_QCFG_OUTPUT_PARTITION_MAX_BW_SCALE_LAST \
12854 HWRM_FUNC_QCFG_OUTPUT_PARTITION_MAX_BW_SCALE_BYTES
12855 /* Always a percentage of link bandwidth. */
12856 #define HWRM_FUNC_QCFG_OUTPUT_PARTITION_MAX_BW_BW_VALUE_UNIT_MASK \
12857 UINT32_C(0xe0000000)
12858 #define HWRM_FUNC_QCFG_OUTPUT_PARTITION_MAX_BW_BW_VALUE_UNIT_SFT \
12860 /* Value is in hundredths of a percent of link bandwidth. */
12861 #define HWRM_FUNC_QCFG_OUTPUT_PARTITION_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 \
12862 (UINT32_C(0x1) << 29)
12863 #define HWRM_FUNC_QCFG_OUTPUT_PARTITION_MAX_BW_BW_VALUE_UNIT_LAST \
12864 HWRM_FUNC_QCFG_OUTPUT_PARTITION_MAX_BW_BW_VALUE_UNIT_PERCENT1_100
12866 * The maximum transmission unit of the function
12867 * configured by the host pf/vf.
12868 * If the reported mtu value is non-zero then it will be used for the
12869 * rings allocated on this function, otherwise the default
12870 * value is used if ring MTU is not specified.
12873 /* Number of Tx Key Contexts allocated. */
12874 uint16_t alloc_tx_key_ctxs;
12875 /* Number of Rx Key Contexts allocated. */
12876 uint16_t alloc_rx_key_ctxs;
12877 uint8_t unused_3[5];
12879 * This field is used in Output records to indicate that the output
12880 * is completely written to RAM. This field should be read as '1'
12881 * to indicate that the output has been completely written.
12882 * When writing a command completion or response to an internal processor,
12883 * the order of writes has to be such that this field is written last.
12893 /* hwrm_func_cfg_input (size:896b/112B) */
12894 struct hwrm_func_cfg_input {
12895 /* The HWRM command request type. */
12898 * The completion ring to send the completion event on. This should
12899 * be the NQ ID returned from the `nq_alloc` HWRM command.
12901 uint16_t cmpl_ring;
12903 * The sequence ID is used by the driver for tracking multiple
12904 * commands. This ID is treated as opaque data by the firmware and
12905 * the value is returned in the `hwrm_resp_hdr` upon completion.
12909 * The target ID of the command:
12910 * * 0x0-0xFFF8 - The function ID
12911 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
12912 * * 0xFFFD - Reserved for user-space HWRM interface
12915 uint16_t target_id;
12917 * A physical address pointer pointing to a host buffer that the
12918 * command's response data will be written. This can be either a host
12919 * physical address (HPA) or a guest physical address (GPA) and must
12920 * point to a physically contiguous block of memory.
12922 uint64_t resp_addr;
12924 * Function ID of the function that is being
12926 * If set to 0xFF... (All Fs), then the configuration is
12927 * for the requesting function.
12931 * This field specifies how many NQs will be reserved for the PF.
12932 * Remaining NQs that belong to the PF become available for VFs.
12933 * Once a PF has created VFs, it cannot change how many NQs are
12934 * reserved for itself (since the NQs must be contiguous in HW).
12939 * When this bit is '1', the function is disabled with
12940 * source MAC address check.
12941 * This is an anti-spoofing check. If this flag is set,
12942 * then the function shall be configured to disallow
12943 * transmission of frames with the source MAC address that
12944 * is configured for this function.
12946 #define HWRM_FUNC_CFG_INPUT_FLAGS_SRC_MAC_ADDR_CHECK_DISABLE \
12949 * When this bit is '1', the function is enabled with
12950 * source MAC address check.
12951 * This is an anti-spoofing check. If this flag is set,
12952 * then the function shall be configured to allow
12953 * transmission of frames with the source MAC address that
12954 * is configured for this function.
12956 #define HWRM_FUNC_CFG_INPUT_FLAGS_SRC_MAC_ADDR_CHECK_ENABLE \
12959 #define HWRM_FUNC_CFG_INPUT_FLAGS_RSVD_MASK \
12961 #define HWRM_FUNC_CFG_INPUT_FLAGS_RSVD_SFT 2
12963 * Standard TX Ring mode is used for the allocation of TX ring
12964 * and underlying scheduling resources that allow bandwidth
12965 * reservation and limit settings on the queried function.
12966 * If set to 1, then standard TX ring mode is requested to be
12967 * enabled on the function being configured.
12969 #define HWRM_FUNC_CFG_INPUT_FLAGS_STD_TX_RING_MODE_ENABLE \
12972 * Standard TX Ring mode is used for the allocation of TX ring
12973 * and underlying scheduling resources that allow bandwidth
12974 * reservation and limit settings on the queried function.
12975 * If set to 1, then the standard TX ring mode is requested to
12976 * be disabled on the function being configured. In this extended
12977 * TX ring resource mode, the minimum and maximum bandwidth settings
12978 * are not supported to allow the allocation of TX rings to
12979 * span multiple scheduler nodes.
12981 #define HWRM_FUNC_CFG_INPUT_FLAGS_STD_TX_RING_MODE_DISABLE \
12984 * If this bit is set, virtual mac address configured
12985 * in this command will be persistent over warm boot.
12987 #define HWRM_FUNC_CFG_INPUT_FLAGS_VIRT_MAC_PERSIST \
12990 * This bit only applies to the VF. If this bit is set, the statistic
12991 * context counters will not be cleared when the statistic context is freed
12992 * or a function reset is called on VF. This bit will be cleared when the PF
12993 * is unloaded or a function reset is called on the PF.
12995 #define HWRM_FUNC_CFG_INPUT_FLAGS_NO_AUTOCLEAR_STATISTIC \
12998 * This bit requests that the firmware test to see if all the assets
12999 * requested in this command (i.e. number of TX rings) are available.
13000 * The firmware will return an error if the requested assets are
13001 * not available. The firwmare will NOT reserve the assets if they
13004 #define HWRM_FUNC_CFG_INPUT_FLAGS_TX_ASSETS_TEST \
13007 * This bit requests that the firmware test to see if all the assets
13008 * requested in this command (i.e. number of RX rings) are available.
13009 * The firmware will return an error if the requested assets are
13010 * not available. The firwmare will NOT reserve the assets if they
13013 #define HWRM_FUNC_CFG_INPUT_FLAGS_RX_ASSETS_TEST \
13016 * This bit requests that the firmware test to see if all the assets
13017 * requested in this command (i.e. number of CMPL rings) are available.
13018 * The firmware will return an error if the requested assets are
13019 * not available. The firwmare will NOT reserve the assets if they
13022 #define HWRM_FUNC_CFG_INPUT_FLAGS_CMPL_ASSETS_TEST \
13025 * This bit requests that the firmware test to see if all the assets
13026 * requested in this command (i.e. number of RSS ctx) are available.
13027 * The firmware will return an error if the requested assets are
13028 * not available. The firwmare will NOT reserve the assets if they
13031 #define HWRM_FUNC_CFG_INPUT_FLAGS_RSSCOS_CTX_ASSETS_TEST \
13034 * This bit requests that the firmware test to see if all the assets
13035 * requested in this command (i.e. number of ring groups) are available.
13036 * The firmware will return an error if the requested assets are
13037 * not available. The firwmare will NOT reserve the assets if they
13040 #define HWRM_FUNC_CFG_INPUT_FLAGS_RING_GRP_ASSETS_TEST \
13043 * This bit requests that the firmware test to see if all the assets
13044 * requested in this command (i.e. number of stat ctx) are available.
13045 * The firmware will return an error if the requested assets are
13046 * not available. The firwmare will NOT reserve the assets if they
13049 #define HWRM_FUNC_CFG_INPUT_FLAGS_STAT_CTX_ASSETS_TEST \
13052 * This bit requests that the firmware test to see if all the assets
13053 * requested in this command (i.e. number of VNICs) are available.
13054 * The firmware will return an error if the requested assets are
13055 * not available. The firwmare will NOT reserve the assets if they
13058 #define HWRM_FUNC_CFG_INPUT_FLAGS_VNIC_ASSETS_TEST \
13061 * This bit requests that the firmware test to see if all the assets
13062 * requested in this command (i.e. number of L2 ctx) are available.
13063 * The firmware will return an error if the requested assets are
13064 * not available. The firwmare will NOT reserve the assets if they
13067 #define HWRM_FUNC_CFG_INPUT_FLAGS_L2_CTX_ASSETS_TEST \
13070 * This configuration change can be initiated by a PF driver. This
13071 * configuration request shall be targeted to a VF. From local host
13072 * resident HWRM clients, only the parent PF driver shall be allowed
13073 * to initiate this change on one of its children VFs. If this bit is
13074 * set to 1, then the VF that is being configured is requested to be
13077 #define HWRM_FUNC_CFG_INPUT_FLAGS_TRUSTED_VF_ENABLE \
13080 * When this bit it set, even if PF reserved pool size is zero,
13081 * FW will allow driver to create TX rings in ring alloc,
13082 * by reserving TX ring, S3 node dynamically.
13084 #define HWRM_FUNC_CFG_INPUT_FLAGS_DYNAMIC_TX_RING_ALLOC \
13087 * This bit requests that the firmware test to see if all the assets
13088 * requested in this command (i.e. number of NQ rings) are available.
13089 * The firmware will return an error if the requested assets are
13090 * not available. The firwmare will NOT reserve the assets if they
13093 #define HWRM_FUNC_CFG_INPUT_FLAGS_NQ_ASSETS_TEST \
13096 * This configuration change can be initiated by a PF driver. This
13097 * configuration request shall be targeted to a VF. From local host
13098 * resident HWRM clients, only the parent PF driver shall be allowed
13099 * to initiate this change on one of its children VFs. If this bit is
13100 * set to 1, then the VF that is being configured is requested to be
13103 #define HWRM_FUNC_CFG_INPUT_FLAGS_TRUSTED_VF_DISABLE \
13104 UINT32_C(0x1000000)
13106 * This bit is used by preboot drivers on a PF that require access
13107 * to the legacy L2 ring model and legacy 32b doorbells. This
13108 * feature is not allowed on VFs and is only relevant for devices
13109 * that require a context backing store.
13111 #define HWRM_FUNC_CFG_INPUT_FLAGS_PREBOOT_LEGACY_L2_RINGS \
13112 UINT32_C(0x2000000)
13114 * If this bit is set to 0, then the interface does not support hot
13115 * reset capability which it advertised with the hot_reset_support
13116 * flag in HWRM_FUNC_DRV_RGTR. If any of the function has set this
13117 * flag to 0, adapter cannot do the hot reset. In this state, if the
13118 * firmware receives a hot reset request, firmware must fail the
13119 * request. If this bit is set to 1, then interface is renabling the
13120 * hot reset capability.
13122 #define HWRM_FUNC_CFG_INPUT_FLAGS_HOT_RESET_IF_EN_DIS \
13123 UINT32_C(0x4000000)
13125 * If this bit is set to 1, the PF driver is requesting FW
13126 * to enable PPP TX PUSH feature on all the TX rings specified in
13127 * the num_tx_rings field. By default, the PPP TX push feature is
13128 * disabled for all the TX rings of the function. This flag is
13129 * ignored if num_tx_rings field is not specified or the function
13130 * doesn't support PPP tx push feature.
13132 #define HWRM_FUNC_CFG_INPUT_FLAGS_PPP_PUSH_MODE_ENABLE \
13133 UINT32_C(0x8000000)
13135 * If this bit is set to 1, the PF driver is requesting FW
13136 * to disable PPP TX PUSH feature on all the TX rings specified in
13137 * the num_tx_rings field. This flag is ignored if num_tx_rings
13138 * field is not specified or the function doesn't support PPP tx
13141 #define HWRM_FUNC_CFG_INPUT_FLAGS_PPP_PUSH_MODE_DISABLE \
13142 UINT32_C(0x10000000)
13144 * If this bit is set to 1, the driver is requesting FW to enable
13145 * the BD_METADATA feature for this function. The FW returns error
13146 * on this request if the TX_METADATA is enabled for this function.
13148 #define HWRM_FUNC_CFG_INPUT_FLAGS_BD_METADATA_ENABLE \
13149 UINT32_C(0x20000000)
13151 * If this bit is set to 1, the driver is requesting FW to disable
13152 * the BD_METADATA feature for this function. The FW returns error
13153 * on this request if the TX_METADATA is enabled for this function.
13155 #define HWRM_FUNC_CFG_INPUT_FLAGS_BD_METADATA_DISABLE \
13156 UINT32_C(0x40000000)
13159 * This bit must be '1' for the admin_mtu field to be
13162 #define HWRM_FUNC_CFG_INPUT_ENABLES_ADMIN_MTU \
13165 * This bit must be '1' for the mru field to be
13168 #define HWRM_FUNC_CFG_INPUT_ENABLES_MRU \
13171 * This bit must be '1' for the num_rsscos_ctxs field to be
13174 #define HWRM_FUNC_CFG_INPUT_ENABLES_NUM_RSSCOS_CTXS \
13177 * This bit must be '1' for the num_cmpl_rings field to be
13180 #define HWRM_FUNC_CFG_INPUT_ENABLES_NUM_CMPL_RINGS \
13183 * This bit must be '1' for the num_tx_rings field to be
13186 #define HWRM_FUNC_CFG_INPUT_ENABLES_NUM_TX_RINGS \
13189 * This bit must be '1' for the num_rx_rings field to be
13192 #define HWRM_FUNC_CFG_INPUT_ENABLES_NUM_RX_RINGS \
13195 * This bit must be '1' for the num_l2_ctxs field to be
13198 #define HWRM_FUNC_CFG_INPUT_ENABLES_NUM_L2_CTXS \
13201 * This bit must be '1' for the num_vnics field to be
13204 #define HWRM_FUNC_CFG_INPUT_ENABLES_NUM_VNICS \
13207 * This bit must be '1' for the num_stat_ctxs field to be
13210 #define HWRM_FUNC_CFG_INPUT_ENABLES_NUM_STAT_CTXS \
13213 * This bit must be '1' for the dflt_mac_addr field to be
13216 #define HWRM_FUNC_CFG_INPUT_ENABLES_DFLT_MAC_ADDR \
13219 * This bit must be '1' for the dflt_vlan field to be
13222 #define HWRM_FUNC_CFG_INPUT_ENABLES_DFLT_VLAN \
13225 * This bit must be '1' for the dflt_ip_addr field to be
13228 #define HWRM_FUNC_CFG_INPUT_ENABLES_DFLT_IP_ADDR \
13231 * This bit must be '1' for the min_bw field to be
13234 #define HWRM_FUNC_CFG_INPUT_ENABLES_MIN_BW \
13237 * This bit must be '1' for the max_bw field to be
13240 #define HWRM_FUNC_CFG_INPUT_ENABLES_MAX_BW \
13243 * This bit must be '1' for the async_event_cr field to be
13246 #define HWRM_FUNC_CFG_INPUT_ENABLES_ASYNC_EVENT_CR \
13249 * This bit must be '1' for the vlan_antispoof_mode field to be
13252 #define HWRM_FUNC_CFG_INPUT_ENABLES_VLAN_ANTISPOOF_MODE \
13255 * This bit must be '1' for the allowed_vlan_pris field to be
13258 #define HWRM_FUNC_CFG_INPUT_ENABLES_ALLOWED_VLAN_PRIS \
13261 * This bit must be '1' for the evb_mode field to be
13264 #define HWRM_FUNC_CFG_INPUT_ENABLES_EVB_MODE \
13267 * This bit must be '1' for the num_mcast_filters field to be
13270 #define HWRM_FUNC_CFG_INPUT_ENABLES_NUM_MCAST_FILTERS \
13273 * This bit must be '1' for the num_hw_ring_grps field to be
13276 #define HWRM_FUNC_CFG_INPUT_ENABLES_NUM_HW_RING_GRPS \
13279 * This bit must be '1' for the cache_linesize field to be
13282 #define HWRM_FUNC_CFG_INPUT_ENABLES_CACHE_LINESIZE \
13285 * This bit must be '1' for the num_msix field to be
13288 #define HWRM_FUNC_CFG_INPUT_ENABLES_NUM_MSIX \
13291 * This bit must be '1' for the link admin state field to be
13294 #define HWRM_FUNC_CFG_INPUT_ENABLES_ADMIN_LINK_STATE \
13297 * This bit must be '1' for the hot_reset_if_en_dis field to be
13300 #define HWRM_FUNC_CFG_INPUT_ENABLES_HOT_RESET_IF_SUPPORT \
13303 * This bit must be '1' for the schq_id field to be
13306 #define HWRM_FUNC_CFG_INPUT_ENABLES_SCHQ_ID \
13307 UINT32_C(0x1000000)
13309 * This bit must be '1' for the mpc_chnls field to be
13312 #define HWRM_FUNC_CFG_INPUT_ENABLES_MPC_CHNLS \
13313 UINT32_C(0x2000000)
13315 * This bit must be '1' for the partition_min_bw field to be
13318 #define HWRM_FUNC_CFG_INPUT_ENABLES_PARTITION_MIN_BW \
13319 UINT32_C(0x4000000)
13321 * This bit must be '1' for the partition_max_bw field to be
13324 #define HWRM_FUNC_CFG_INPUT_ENABLES_PARTITION_MAX_BW \
13325 UINT32_C(0x8000000)
13327 * This bit must be '1' for the tpid field to be
13328 * configured. This bit is only valid when dflt_vlan enable
13331 #define HWRM_FUNC_CFG_INPUT_ENABLES_TPID \
13332 UINT32_C(0x10000000)
13334 * This bit must be '1' for the host_mtu field to be
13337 #define HWRM_FUNC_CFG_INPUT_ENABLES_HOST_MTU \
13338 UINT32_C(0x20000000)
13340 * This bit must be '1' for the number of Tx Key Contexts
13341 * field to be configured.
13343 #define HWRM_FUNC_CFG_INPUT_ENABLES_TX_KEY_CTXS \
13344 UINT32_C(0x40000000)
13346 * This bit must be '1' for the number of Rx Key Contexts
13347 * field to be configured.
13349 #define HWRM_FUNC_CFG_INPUT_ENABLES_RX_KEY_CTXS \
13350 UINT32_C(0x80000000)
13352 * This field can be used by the admin PF to configure
13353 * mtu of foster PFs.
13354 * The maximum transmission unit of the function.
13355 * The HWRM should make sure that the mtu of
13356 * the function does not exceed the mtu of the physical
13357 * port that this function is associated with.
13359 * In addition to configuring mtu per function, it is
13360 * possible to configure mtu per transmit ring.
13361 * By default, the mtu of each transmit ring associated
13362 * with a function is equal to the mtu of the function.
13363 * The HWRM should make sure that the mtu of each transmit
13364 * ring that is assigned to a function has a valid mtu.
13366 uint16_t admin_mtu;
13368 * The maximum receive unit of the function.
13369 * The HWRM should make sure that the mru of
13370 * the function does not exceed the mru of the physical
13371 * port that this function is associated with.
13373 * In addition to configuring mru per function, it is
13374 * possible to configure mru per vnic.
13375 * By default, the mru of each vnic associated
13376 * with a function is equal to the mru of the function.
13377 * The HWRM should make sure that the mru of each vnic
13378 * that is assigned to a function has a valid mru.
13382 * The number of RSS/COS contexts requested for the
13385 uint16_t num_rsscos_ctxs;
13387 * The number of completion rings requested for the
13388 * function. This does not include the rings allocated
13389 * to any children functions if any.
13391 uint16_t num_cmpl_rings;
13393 * The number of transmit rings requested for the function.
13394 * This does not include the rings allocated to any
13395 * children functions if any.
13397 uint16_t num_tx_rings;
13399 * The number of receive rings requested for the function.
13400 * This does not include the rings allocated
13401 * to any children functions if any.
13403 uint16_t num_rx_rings;
13404 /* The requested number of L2 contexts for the function. */
13405 uint16_t num_l2_ctxs;
13406 /* The requested number of vnics for the function. */
13407 uint16_t num_vnics;
13408 /* The requested number of statistic contexts for the function. */
13409 uint16_t num_stat_ctxs;
13411 * The number of HW ring groups that should
13412 * be reserved for this function.
13414 uint16_t num_hw_ring_grps;
13415 /* The default MAC address for the function being configured. */
13416 uint8_t dflt_mac_addr[6];
13418 * The default VLAN for the function being configured.
13419 * This field's format is same as 802.1Q Tag's
13420 * Tag Control Information (TCI) format that includes both
13421 * Priority Code Point (PCP) and VLAN Identifier (VID).
13423 uint16_t dflt_vlan;
13425 * The default IP address for the function being configured.
13426 * This address is only used in enabling source property check.
13428 uint32_t dflt_ip_addr[4];
13430 * Minimum guaranteed transmit bandwidth for this function. When
13431 * specified for a PF, does not affect traffic from the PF's child VFs.
13432 * A value of 0 indicates the minimum bandwidth is not configured.
13435 /* The bandwidth value. */
13436 #define HWRM_FUNC_CFG_INPUT_MIN_BW_BW_VALUE_MASK \
13437 UINT32_C(0xfffffff)
13438 #define HWRM_FUNC_CFG_INPUT_MIN_BW_BW_VALUE_SFT 0
13439 /* The granularity of the value (bits or bytes). */
13440 #define HWRM_FUNC_CFG_INPUT_MIN_BW_SCALE \
13441 UINT32_C(0x10000000)
13442 /* Value is in bits. */
13443 #define HWRM_FUNC_CFG_INPUT_MIN_BW_SCALE_BITS \
13444 (UINT32_C(0x0) << 28)
13445 /* Value is in bytes. */
13446 #define HWRM_FUNC_CFG_INPUT_MIN_BW_SCALE_BYTES \
13447 (UINT32_C(0x1) << 28)
13448 #define HWRM_FUNC_CFG_INPUT_MIN_BW_SCALE_LAST \
13449 HWRM_FUNC_CFG_INPUT_MIN_BW_SCALE_BYTES
13450 /* bw_value_unit is 3 b */
13451 #define HWRM_FUNC_CFG_INPUT_MIN_BW_BW_VALUE_UNIT_MASK \
13452 UINT32_C(0xe0000000)
13453 #define HWRM_FUNC_CFG_INPUT_MIN_BW_BW_VALUE_UNIT_SFT 29
13454 /* Value is in Mb or MB (base 10). */
13455 #define HWRM_FUNC_CFG_INPUT_MIN_BW_BW_VALUE_UNIT_MEGA \
13456 (UINT32_C(0x0) << 29)
13457 /* Value is in Kb or KB (base 10). */
13458 #define HWRM_FUNC_CFG_INPUT_MIN_BW_BW_VALUE_UNIT_KILO \
13459 (UINT32_C(0x2) << 29)
13460 /* Value is in bits or bytes. */
13461 #define HWRM_FUNC_CFG_INPUT_MIN_BW_BW_VALUE_UNIT_BASE \
13462 (UINT32_C(0x4) << 29)
13463 /* Value is in Gb or GB (base 10). */
13464 #define HWRM_FUNC_CFG_INPUT_MIN_BW_BW_VALUE_UNIT_GIGA \
13465 (UINT32_C(0x6) << 29)
13466 /* Value is in 1/100th of a percentage of total bandwidth. */
13467 #define HWRM_FUNC_CFG_INPUT_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 \
13468 (UINT32_C(0x1) << 29)
13470 #define HWRM_FUNC_CFG_INPUT_MIN_BW_BW_VALUE_UNIT_INVALID \
13471 (UINT32_C(0x7) << 29)
13472 #define HWRM_FUNC_CFG_INPUT_MIN_BW_BW_VALUE_UNIT_LAST \
13473 HWRM_FUNC_CFG_INPUT_MIN_BW_BW_VALUE_UNIT_INVALID
13475 * Maximum transmit rate for this function. When specified for a PF,
13476 * does not affect traffic from the PF's child VFs.
13477 * A value of 0 indicates that the maximum bandwidth is not configured.
13480 /* The bandwidth value. */
13481 #define HWRM_FUNC_CFG_INPUT_MAX_BW_BW_VALUE_MASK \
13482 UINT32_C(0xfffffff)
13483 #define HWRM_FUNC_CFG_INPUT_MAX_BW_BW_VALUE_SFT 0
13484 /* The granularity of the value (bits or bytes). */
13485 #define HWRM_FUNC_CFG_INPUT_MAX_BW_SCALE \
13486 UINT32_C(0x10000000)
13487 /* Value is in bits. */
13488 #define HWRM_FUNC_CFG_INPUT_MAX_BW_SCALE_BITS \
13489 (UINT32_C(0x0) << 28)
13490 /* Value is in bytes. */
13491 #define HWRM_FUNC_CFG_INPUT_MAX_BW_SCALE_BYTES \
13492 (UINT32_C(0x1) << 28)
13493 #define HWRM_FUNC_CFG_INPUT_MAX_BW_SCALE_LAST \
13494 HWRM_FUNC_CFG_INPUT_MAX_BW_SCALE_BYTES
13495 /* bw_value_unit is 3 b */
13496 #define HWRM_FUNC_CFG_INPUT_MAX_BW_BW_VALUE_UNIT_MASK \
13497 UINT32_C(0xe0000000)
13498 #define HWRM_FUNC_CFG_INPUT_MAX_BW_BW_VALUE_UNIT_SFT 29
13499 /* Value is in Mb or MB (base 10). */
13500 #define HWRM_FUNC_CFG_INPUT_MAX_BW_BW_VALUE_UNIT_MEGA \
13501 (UINT32_C(0x0) << 29)
13502 /* Value is in Kb or KB (base 10). */
13503 #define HWRM_FUNC_CFG_INPUT_MAX_BW_BW_VALUE_UNIT_KILO \
13504 (UINT32_C(0x2) << 29)
13505 /* Value is in bits or bytes. */
13506 #define HWRM_FUNC_CFG_INPUT_MAX_BW_BW_VALUE_UNIT_BASE \
13507 (UINT32_C(0x4) << 29)
13508 /* Value is in Gb or GB (base 10). */
13509 #define HWRM_FUNC_CFG_INPUT_MAX_BW_BW_VALUE_UNIT_GIGA \
13510 (UINT32_C(0x6) << 29)
13511 /* Value is in 1/100th of a percentage of total bandwidth. */
13512 #define HWRM_FUNC_CFG_INPUT_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 \
13513 (UINT32_C(0x1) << 29)
13515 #define HWRM_FUNC_CFG_INPUT_MAX_BW_BW_VALUE_UNIT_INVALID \
13516 (UINT32_C(0x7) << 29)
13517 #define HWRM_FUNC_CFG_INPUT_MAX_BW_BW_VALUE_UNIT_LAST \
13518 HWRM_FUNC_CFG_INPUT_MAX_BW_BW_VALUE_UNIT_INVALID
13520 * ID of the target completion ring for receiving asynchronous
13521 * event completions. If this field is not valid, then the
13522 * HWRM shall use the default completion ring of the function
13523 * that is being configured as the target completion ring for
13524 * providing any asynchronous event completions for that
13526 * If this field is valid, then the HWRM shall use the
13527 * completion ring identified by this ID as the target
13528 * completion ring for providing any asynchronous event
13529 * completions for the function that is being configured.
13531 uint16_t async_event_cr;
13532 /* VLAN Anti-spoofing mode. */
13533 uint8_t vlan_antispoof_mode;
13534 /* No VLAN anti-spoofing checks are enabled */
13535 #define HWRM_FUNC_CFG_INPUT_VLAN_ANTISPOOF_MODE_NOCHECK \
13537 /* Validate VLAN against the configured VLAN(s) */
13538 #define HWRM_FUNC_CFG_INPUT_VLAN_ANTISPOOF_MODE_VALIDATE_VLAN \
13540 /* Insert VLAN if it does not exist, otherwise discard */
13541 #define HWRM_FUNC_CFG_INPUT_VLAN_ANTISPOOF_MODE_INSERT_IF_VLANDNE \
13543 /* Insert VLAN if it does not exist, override VLAN if it exists */
13544 #define HWRM_FUNC_CFG_INPUT_VLAN_ANTISPOOF_MODE_INSERT_OR_OVERRIDE_VLAN \
13546 #define HWRM_FUNC_CFG_INPUT_VLAN_ANTISPOOF_MODE_LAST \
13547 HWRM_FUNC_CFG_INPUT_VLAN_ANTISPOOF_MODE_INSERT_OR_OVERRIDE_VLAN
13549 * This bit field defines VLAN PRIs that are allowed on
13551 * If nth bit is set, then VLAN PRI n is allowed on this
13554 uint8_t allowed_vlan_pris;
13556 * The evb_mode is configured on a per port basis. The default evb_mode
13557 * is configured based on the NVM EVB mode setting upon firmware
13558 * initialization. The HWRM allows a PF driver to change EVB mode for a
13559 * port used by the PF only when one of the following conditions is
13561 * 1. The current operating mode is single function mode.
13562 * (ie. one PF per port)
13563 * 2. For SmartNIC, any one of the PAXC PFs is permitted to change the
13564 * EVB mode of the port used by the PAXC PF. None of the X86 PFs
13565 * should have privileges.
13566 * The HWRM doesn't permit any PFs to change the underlying EVB mode
13567 * when running as MHB or NPAR mode in performance NIC configuration.
13568 * The HWRM doesn't permit a VF driver to change the EVB mode.
13569 * Once the HWRM determines a function doesn't meet the conditions
13570 * to configure the EVB mode, it sets the evb_mode_cfg_not_supported
13571 * flag in HWRM_FUNC_QCAPS command response for the function.
13572 * The HWRM takes into account the switching of EVB mode from one to
13573 * another and reconfigure hardware resources as reqiured. The
13574 * switching from VEB to VEPA mode requires the disabling of the
13575 * loopback traffic. Additionally, source knockouts are handled
13576 * differently in VEB and VEPA modes.
13579 /* No Edge Virtual Bridging (EVB) */
13580 #define HWRM_FUNC_CFG_INPUT_EVB_MODE_NO_EVB UINT32_C(0x0)
13581 /* Virtual Ethernet Bridge (VEB) */
13582 #define HWRM_FUNC_CFG_INPUT_EVB_MODE_VEB UINT32_C(0x1)
13583 /* Virtual Ethernet Port Aggregator (VEPA) */
13584 #define HWRM_FUNC_CFG_INPUT_EVB_MODE_VEPA UINT32_C(0x2)
13585 #define HWRM_FUNC_CFG_INPUT_EVB_MODE_LAST \
13586 HWRM_FUNC_CFG_INPUT_EVB_MODE_VEPA
13589 * This value indicates the PCIE device cache line size.
13590 * The cache line size allows the DMA writes to terminate and
13591 * start at the cache boundary.
13593 #define HWRM_FUNC_CFG_INPUT_OPTIONS_CACHE_LINESIZE_MASK \
13595 #define HWRM_FUNC_CFG_INPUT_OPTIONS_CACHE_LINESIZE_SFT 0
13596 /* Cache Line Size 64 bytes */
13597 #define HWRM_FUNC_CFG_INPUT_OPTIONS_CACHE_LINESIZE_SIZE_64 \
13599 /* Cache Line Size 128 bytes */
13600 #define HWRM_FUNC_CFG_INPUT_OPTIONS_CACHE_LINESIZE_SIZE_128 \
13602 #define HWRM_FUNC_CFG_INPUT_OPTIONS_CACHE_LINESIZE_LAST \
13603 HWRM_FUNC_CFG_INPUT_OPTIONS_CACHE_LINESIZE_SIZE_128
13604 /* This value is the virtual link admin state setting. */
13605 #define HWRM_FUNC_CFG_INPUT_OPTIONS_LINK_ADMIN_STATE_MASK \
13607 #define HWRM_FUNC_CFG_INPUT_OPTIONS_LINK_ADMIN_STATE_SFT 2
13608 /* Admin state is forced down. */
13609 #define HWRM_FUNC_CFG_INPUT_OPTIONS_LINK_ADMIN_STATE_FORCED_DOWN \
13610 (UINT32_C(0x0) << 2)
13611 /* Admin state is forced up. */
13612 #define HWRM_FUNC_CFG_INPUT_OPTIONS_LINK_ADMIN_STATE_FORCED_UP \
13613 (UINT32_C(0x1) << 2)
13614 /* Admin state is in auto mode - is to follow the physical link state. */
13615 #define HWRM_FUNC_CFG_INPUT_OPTIONS_LINK_ADMIN_STATE_AUTO \
13616 (UINT32_C(0x2) << 2)
13617 #define HWRM_FUNC_CFG_INPUT_OPTIONS_LINK_ADMIN_STATE_LAST \
13618 HWRM_FUNC_CFG_INPUT_OPTIONS_LINK_ADMIN_STATE_AUTO
13619 /* Reserved for future. */
13620 #define HWRM_FUNC_CFG_INPUT_OPTIONS_RSVD_MASK \
13622 #define HWRM_FUNC_CFG_INPUT_OPTIONS_RSVD_SFT 4
13624 * The number of multicast filters that should
13625 * be reserved for this function on the RX side.
13627 uint16_t num_mcast_filters;
13628 /* Used by a PF driver to associate a SCHQ with a VF. */
13630 uint16_t mpc_chnls;
13632 * When this bit is '1', the caller requests to enable a MPC
13633 * channel with destination to the TX crypto engine block.
13634 * When this bit is ‘0’, this flag has no effect.
13636 #define HWRM_FUNC_CFG_INPUT_MPC_CHNLS_TCE_ENABLE UINT32_C(0x1)
13638 * When this bit is '1', the caller requests to disable a MPC
13639 * channel with destination to the TX crypto engine block.
13640 * When this bit is ‘0’, this flag has no effect.
13642 #define HWRM_FUNC_CFG_INPUT_MPC_CHNLS_TCE_DISABLE UINT32_C(0x2)
13644 * When this bit is '1', the caller requests to enable a MPC
13645 * channel with destination to the RX crypto engine block.
13646 * When this bit is ‘0’, this flag has no effect.
13648 #define HWRM_FUNC_CFG_INPUT_MPC_CHNLS_RCE_ENABLE UINT32_C(0x4)
13650 * When this bit is '1', the caller requests to disable a MPC
13651 * channel with destination to the RX crypto engine block.
13652 * When this bit is ‘0’, this flag has no effect.
13654 #define HWRM_FUNC_CFG_INPUT_MPC_CHNLS_RCE_DISABLE UINT32_C(0x8)
13656 * When this bit is '1', the caller requests to enable a MPC
13657 * channel with destination to the TX configurable flow processing
13658 * block. When this bit is ‘0’, this flag has no effect.
13660 #define HWRM_FUNC_CFG_INPUT_MPC_CHNLS_TE_CFA_ENABLE \
13663 * When this bit is '1', the caller requests to disable a MPC
13664 * channel with destination to the TX configurable flow processing
13665 * block. When this bit is ‘0’, this flag has no effect.
13667 #define HWRM_FUNC_CFG_INPUT_MPC_CHNLS_TE_CFA_DISABLE \
13670 * When this bit is '1', the caller requests to enable a MPC
13671 * channel with destination to the RX configurable flow processing
13672 * block. When this bit is ‘0’, this flag has no effect.
13674 #define HWRM_FUNC_CFG_INPUT_MPC_CHNLS_RE_CFA_ENABLE \
13677 * When this bit is '1', the caller requests to disable a MPC
13678 * channel with destination to the RX configurable flow processing
13679 * block. When this bit is ‘0’, this flag has no effect.
13681 #define HWRM_FUNC_CFG_INPUT_MPC_CHNLS_RE_CFA_DISABLE \
13684 * When this bit is '1', the caller requests to enable a MPC
13685 * channel with destination to the primate processor block.
13686 * When this bit is ‘0’, this flag has no effect.
13688 #define HWRM_FUNC_CFG_INPUT_MPC_CHNLS_PRIMATE_ENABLE \
13691 * When this bit is '1', the caller requests to disable a MPC
13692 * channel with destination to the primate processor block.
13693 * When this bit is ‘0’, this flag has no effect.
13695 #define HWRM_FUNC_CFG_INPUT_MPC_CHNLS_PRIMATE_DISABLE \
13698 * Minimum guaranteed bandwidth for the network partition made up
13699 * of the caller physical function and all its child virtual
13700 * functions. The rate is specified as a percentage of the bandwidth
13701 * of the link the partition is associated with. A value of 0
13702 * indicates that no minimum bandwidth is configured. The sum of the
13703 * minimum bandwidths for all partitions on a link must not exceed
13705 * The format of this field is defined to match min_bw, even though
13706 * it does not allow all the options for min_bw at this time.
13708 uint32_t partition_min_bw;
13709 /* The bandwidth value. */
13710 #define HWRM_FUNC_CFG_INPUT_PARTITION_MIN_BW_BW_VALUE_MASK \
13711 UINT32_C(0xfffffff)
13712 #define HWRM_FUNC_CFG_INPUT_PARTITION_MIN_BW_BW_VALUE_SFT \
13715 * The granularity of the value (bits or bytes). Firmware ignores
13718 #define HWRM_FUNC_CFG_INPUT_PARTITION_MIN_BW_SCALE \
13719 UINT32_C(0x10000000)
13720 /* Value is in bits. */
13721 #define HWRM_FUNC_CFG_INPUT_PARTITION_MIN_BW_SCALE_BITS \
13722 (UINT32_C(0x0) << 28)
13723 /* Value is in bytes. */
13724 #define HWRM_FUNC_CFG_INPUT_PARTITION_MIN_BW_SCALE_BYTES \
13725 (UINT32_C(0x1) << 28)
13726 #define HWRM_FUNC_CFG_INPUT_PARTITION_MIN_BW_SCALE_LAST \
13727 HWRM_FUNC_CFG_INPUT_PARTITION_MIN_BW_SCALE_BYTES
13728 /* Bandwidth units. Must be set to percent1_100. */
13729 #define HWRM_FUNC_CFG_INPUT_PARTITION_MIN_BW_BW_VALUE_UNIT_MASK \
13730 UINT32_C(0xe0000000)
13731 #define HWRM_FUNC_CFG_INPUT_PARTITION_MIN_BW_BW_VALUE_UNIT_SFT \
13733 /* Value is in hundredths of a percent of link bandwidth. */
13734 #define HWRM_FUNC_CFG_INPUT_PARTITION_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 \
13735 (UINT32_C(0x1) << 29)
13736 #define HWRM_FUNC_CFG_INPUT_PARTITION_MIN_BW_BW_VALUE_UNIT_LAST \
13737 HWRM_FUNC_CFG_INPUT_PARTITION_MIN_BW_BW_VALUE_UNIT_PERCENT1_100
13739 * The maximum bandwidth that may be used by the network partition
13740 * made up of the caller physical function and all its child virtual
13741 * functions. The rate is specified as a percentage of the bandwidth
13742 * of the link the partition is associated with. A value of 0
13743 * indicates that no maximum bandwidth is configured.
13744 * The format of this field is defined to match max_bw, even though it
13745 * does not allow all the options for max_bw at this time.
13747 uint32_t partition_max_bw;
13748 /* The bandwidth value. */
13749 #define HWRM_FUNC_CFG_INPUT_PARTITION_MAX_BW_BW_VALUE_MASK \
13750 UINT32_C(0xfffffff)
13751 #define HWRM_FUNC_CFG_INPUT_PARTITION_MAX_BW_BW_VALUE_SFT \
13754 * The granularity of the value (bits or bytes). Firmware ignores
13757 #define HWRM_FUNC_CFG_INPUT_PARTITION_MAX_BW_SCALE \
13758 UINT32_C(0x10000000)
13759 /* Value is in bits. */
13760 #define HWRM_FUNC_CFG_INPUT_PARTITION_MAX_BW_SCALE_BITS \
13761 (UINT32_C(0x0) << 28)
13762 /* Value is in bytes. */
13763 #define HWRM_FUNC_CFG_INPUT_PARTITION_MAX_BW_SCALE_BYTES \
13764 (UINT32_C(0x1) << 28)
13765 #define HWRM_FUNC_CFG_INPUT_PARTITION_MAX_BW_SCALE_LAST \
13766 HWRM_FUNC_CFG_INPUT_PARTITION_MAX_BW_SCALE_BYTES
13767 /* Bandwidth units. Must be set to percent1_100. */
13768 #define HWRM_FUNC_CFG_INPUT_PARTITION_MAX_BW_BW_VALUE_UNIT_MASK \
13769 UINT32_C(0xe0000000)
13770 #define HWRM_FUNC_CFG_INPUT_PARTITION_MAX_BW_BW_VALUE_UNIT_SFT \
13772 /* Value is in hundredths of a percent of link bandwidth. */
13773 #define HWRM_FUNC_CFG_INPUT_PARTITION_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 \
13774 (UINT32_C(0x1) << 29)
13775 #define HWRM_FUNC_CFG_INPUT_PARTITION_MAX_BW_BW_VALUE_UNIT_LAST \
13776 HWRM_FUNC_CFG_INPUT_PARTITION_MAX_BW_BW_VALUE_UNIT_PERCENT1_100
13778 * The TPID for the function for which default VLAN
13779 * is configured. If the dflt_vlan is not specified
13780 * with the TPID, FW returns error. If the TPID is
13781 * not specified with dflt_vlan, the default TPID of
13782 * 0x8100 will be used. This field is specified in
13783 * network byte order.
13787 * This field can be used by the host PF to configure
13789 * The maximum transmission unit of the function.
13790 * The HWRM should make sure that the mtu of
13791 * the function does not exceed the mtu of the physical
13792 * port that this function is associated with.
13794 * In addition to configuring mtu per function, it is
13795 * possible to configure mtu per transmit ring.
13796 * By default, the mtu of each transmit ring associated
13797 * with a function is equal to the mtu of the function.
13798 * The HWRM should make sure that the mtu of each transmit
13799 * ring that is assigned to a function has a valid mtu.
13802 /* Number of Tx Key Contexts requested. */
13803 uint16_t num_tx_key_ctxs;
13804 /* Number of Rx Key Contexts requested. */
13805 uint16_t num_rx_key_ctxs;
13806 uint8_t unused_0[4];
13809 /* hwrm_func_cfg_output (size:128b/16B) */
13810 struct hwrm_func_cfg_output {
13811 /* The specific error status for the command. */
13812 uint16_t error_code;
13813 /* The HWRM command request type. */
13815 /* The sequence ID from the original command. */
13817 /* The length of the response data in number of bytes. */
13819 uint8_t unused_0[7];
13821 * This field is used in Output records to indicate that the output
13822 * is completely written to RAM. This field should be read as '1'
13823 * to indicate that the output has been completely written.
13824 * When writing a command completion or response to an internal processor,
13825 * the order of writes has to be such that this field is written last.
13830 /* hwrm_func_cfg_cmd_err (size:64b/8B) */
13831 struct hwrm_func_cfg_cmd_err {
13832 /* command specific error codes for the cmd_err field in hwrm_err_output */
13834 /* Unknown error. */
13835 #define HWRM_FUNC_CFG_CMD_ERR_CODE_UNKNOWN \
13837 /* The partition minimum bandwidth is out of range. */
13838 #define HWRM_FUNC_CFG_CMD_ERR_CODE_PARTITION_MIN_BW_RANGE \
13840 /* The minimum bandwidth is more than the maximum bandwidth. */
13841 #define HWRM_FUNC_CFG_CMD_ERR_CODE_PARTITION_MIN_MORE_THAN_MAX \
13844 * The NIC does not support enforcement of a minimum guaranteed
13845 * bandwidth for a partition.
13847 #define HWRM_FUNC_CFG_CMD_ERR_CODE_PARTITION_MIN_BW_UNSUPPORTED \
13849 /* Partition bandwidths must be specified as a percentage. */
13850 #define HWRM_FUNC_CFG_CMD_ERR_CODE_PARTITION_BW_PERCENT \
13852 #define HWRM_FUNC_CFG_CMD_ERR_CODE_LAST \
13853 HWRM_FUNC_CFG_CMD_ERR_CODE_PARTITION_BW_PERCENT
13854 uint8_t unused_0[7];
13857 /********************
13858 * hwrm_func_qstats *
13859 ********************/
13862 /* hwrm_func_qstats_input (size:192b/24B) */
13863 struct hwrm_func_qstats_input {
13864 /* The HWRM command request type. */
13867 * The completion ring to send the completion event on. This should
13868 * be the NQ ID returned from the `nq_alloc` HWRM command.
13870 uint16_t cmpl_ring;
13872 * The sequence ID is used by the driver for tracking multiple
13873 * commands. This ID is treated as opaque data by the firmware and
13874 * the value is returned in the `hwrm_resp_hdr` upon completion.
13878 * The target ID of the command:
13879 * * 0x0-0xFFF8 - The function ID
13880 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
13881 * * 0xFFFD - Reserved for user-space HWRM interface
13884 uint16_t target_id;
13886 * A physical address pointer pointing to a host buffer that the
13887 * command's response data will be written. This can be either a host
13888 * physical address (HPA) or a guest physical address (GPA) and must
13889 * point to a physically contiguous block of memory.
13891 uint64_t resp_addr;
13893 * Function ID of the function that is being queried.
13894 * 0xFF... (All Fs) if the query is for the requesting
13896 * A privileged PF can query for other function's statistics.
13899 /* This flags indicates the type of statistics request. */
13901 /* This value is not used to avoid backward compatibility issues. */
13902 #define HWRM_FUNC_QSTATS_INPUT_FLAGS_UNUSED UINT32_C(0x0)
13904 * flags should be set to 1 when request is for only RoCE statistics.
13905 * This will be honored only if the caller_fid is a privileged PF.
13906 * In all other cases FID and caller_fid should be the same.
13908 #define HWRM_FUNC_QSTATS_INPUT_FLAGS_ROCE_ONLY UINT32_C(0x1)
13910 * flags should be set to 2 when request is for the counter mask,
13911 * representing the width of each of the stats counters, rather
13912 * than counters themselves.
13914 #define HWRM_FUNC_QSTATS_INPUT_FLAGS_COUNTER_MASK UINT32_C(0x2)
13915 #define HWRM_FUNC_QSTATS_INPUT_FLAGS_LAST \
13916 HWRM_FUNC_QSTATS_INPUT_FLAGS_COUNTER_MASK
13917 uint8_t unused_0[5];
13920 /* hwrm_func_qstats_output (size:1408b/176B) */
13921 struct hwrm_func_qstats_output {
13922 /* The specific error status for the command. */
13923 uint16_t error_code;
13924 /* The HWRM command request type. */
13926 /* The sequence ID from the original command. */
13928 /* The length of the response data in number of bytes. */
13930 /* Number of transmitted unicast packets on the function. */
13931 uint64_t tx_ucast_pkts;
13932 /* Number of transmitted multicast packets on the function. */
13933 uint64_t tx_mcast_pkts;
13934 /* Number of transmitted broadcast packets on the function. */
13935 uint64_t tx_bcast_pkts;
13937 * Number of transmitted packets that were discarded due to
13938 * internal NIC resource problems. For transmit, this
13939 * can only happen if TMP is configured to allow dropping
13940 * in HOL blocking conditions, which is not a normal
13943 uint64_t tx_discard_pkts;
13945 * Number of dropped packets on transmit path on the function.
13946 * These are packets that have been marked for drop by
13947 * the TE CFA block or are packets that exceeded the
13948 * transmit MTU limit for the function.
13950 uint64_t tx_drop_pkts;
13951 /* Number of transmitted bytes for unicast traffic on the function. */
13952 uint64_t tx_ucast_bytes;
13953 /* Number of transmitted bytes for multicast traffic on the function. */
13954 uint64_t tx_mcast_bytes;
13955 /* Number of transmitted bytes for broadcast traffic on the function. */
13956 uint64_t tx_bcast_bytes;
13957 /* Number of received unicast packets on the function. */
13958 uint64_t rx_ucast_pkts;
13959 /* Number of received multicast packets on the function. */
13960 uint64_t rx_mcast_pkts;
13961 /* Number of received broadcast packets on the function. */
13962 uint64_t rx_bcast_pkts;
13964 * Number of received packets that were discarded on the function
13965 * due to resource limitations. This can happen for 3 reasons.
13966 * # The BD used for the packet has a bad format.
13967 * # There were no BDs available in the ring for the packet.
13968 * # There were no BDs available on-chip for the packet.
13970 uint64_t rx_discard_pkts;
13972 * Number of dropped packets on received path on the function.
13973 * These are packets that have been marked for drop by the
13976 uint64_t rx_drop_pkts;
13977 /* Number of received bytes for unicast traffic on the function. */
13978 uint64_t rx_ucast_bytes;
13979 /* Number of received bytes for multicast traffic on the function. */
13980 uint64_t rx_mcast_bytes;
13981 /* Number of received bytes for broadcast traffic on the function. */
13982 uint64_t rx_bcast_bytes;
13983 /* Number of aggregated unicast packets on the function. */
13984 uint64_t rx_agg_pkts;
13985 /* Number of aggregated unicast bytes on the function. */
13986 uint64_t rx_agg_bytes;
13987 /* Number of aggregation events on the function. */
13988 uint64_t rx_agg_events;
13989 /* Number of aborted aggregations on the function. */
13990 uint64_t rx_agg_aborts;
13991 uint8_t unused_0[7];
13993 * This field is used in Output records to indicate that the output
13994 * is completely written to RAM. This field should be read as '1'
13995 * to indicate that the output has been completely written.
13996 * When writing a command completion or response to an internal processor,
13997 * the order of writes has to be such that this field is written last.
14002 /************************
14003 * hwrm_func_qstats_ext *
14004 ************************/
14007 /* hwrm_func_qstats_ext_input (size:256b/32B) */
14008 struct hwrm_func_qstats_ext_input {
14009 /* The HWRM command request type. */
14012 * The completion ring to send the completion event on. This should
14013 * be the NQ ID returned from the `nq_alloc` HWRM command.
14015 uint16_t cmpl_ring;
14017 * The sequence ID is used by the driver for tracking multiple
14018 * commands. This ID is treated as opaque data by the firmware and
14019 * the value is returned in the `hwrm_resp_hdr` upon completion.
14023 * The target ID of the command:
14024 * * 0x0-0xFFF8 - The function ID
14025 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
14026 * * 0xFFFD - Reserved for user-space HWRM interface
14029 uint16_t target_id;
14031 * A physical address pointer pointing to a host buffer that the
14032 * command's response data will be written. This can be either a host
14033 * physical address (HPA) or a guest physical address (GPA) and must
14034 * point to a physically contiguous block of memory.
14036 uint64_t resp_addr;
14038 * Function ID of the function that is being queried.
14039 * 0xFF... (All Fs) if the query is for the requesting
14041 * A privileged PF can query for other function's statistics.
14044 /* This flags indicates the type of statistics request. */
14046 /* This value is not used to avoid backward compatibility issues. */
14047 #define HWRM_FUNC_QSTATS_EXT_INPUT_FLAGS_UNUSED UINT32_C(0x0)
14049 * flags should be set to 1 when request is for only RoCE statistics.
14050 * This will be honored only if the caller_fid is a privileged PF.
14051 * In all other cases FID and caller_fid should be the same.
14053 #define HWRM_FUNC_QSTATS_EXT_INPUT_FLAGS_ROCE_ONLY UINT32_C(0x1)
14055 * flags should be set to 2 when request is for the counter mask
14056 * representing the width of each of the stats counters, rather
14057 * than counters themselves.
14059 #define HWRM_FUNC_QSTATS_EXT_INPUT_FLAGS_COUNTER_MASK UINT32_C(0x2)
14060 #define HWRM_FUNC_QSTATS_EXT_INPUT_FLAGS_LAST \
14061 HWRM_FUNC_QSTATS_EXT_INPUT_FLAGS_COUNTER_MASK
14062 uint8_t unused_0[1];
14065 * This bit must be '1' for the schq_id and traffic_class fields to
14068 #define HWRM_FUNC_QSTATS_EXT_INPUT_ENABLES_SCHQ_ID UINT32_C(0x1)
14069 /* Specifies the SCHQ for which to gather statistics */
14072 * Specifies the traffic class for which to gather statistics. Valid
14073 * values are 0 through (max_configurable_queues - 1), where
14074 * max_configurable_queues is in the response of HWRM_QUEUE_QPORTCFG
14076 uint16_t traffic_class;
14077 uint8_t unused_1[4];
14080 /* hwrm_func_qstats_ext_output (size:1536b/192B) */
14081 struct hwrm_func_qstats_ext_output {
14082 /* The specific error status for the command. */
14083 uint16_t error_code;
14084 /* The HWRM command request type. */
14086 /* The sequence ID from the original command. */
14088 /* The length of the response data in number of bytes. */
14090 /* Number of received unicast packets */
14091 uint64_t rx_ucast_pkts;
14092 /* Number of received multicast packets */
14093 uint64_t rx_mcast_pkts;
14094 /* Number of received broadcast packets */
14095 uint64_t rx_bcast_pkts;
14096 /* Number of discarded packets on received path */
14097 uint64_t rx_discard_pkts;
14098 /* Number of packets on receive path with error */
14099 uint64_t rx_error_pkts;
14100 /* Number of received bytes for unicast traffic */
14101 uint64_t rx_ucast_bytes;
14102 /* Number of received bytes for multicast traffic */
14103 uint64_t rx_mcast_bytes;
14104 /* Number of received bytes for broadcast traffic */
14105 uint64_t rx_bcast_bytes;
14106 /* Number of transmitted unicast packets */
14107 uint64_t tx_ucast_pkts;
14108 /* Number of transmitted multicast packets */
14109 uint64_t tx_mcast_pkts;
14110 /* Number of transmitted broadcast packets */
14111 uint64_t tx_bcast_pkts;
14112 /* Number of packets on transmit path with error */
14113 uint64_t tx_error_pkts;
14114 /* Number of discarded packets on transmit path */
14115 uint64_t tx_discard_pkts;
14116 /* Number of transmitted bytes for unicast traffic */
14117 uint64_t tx_ucast_bytes;
14118 /* Number of transmitted bytes for multicast traffic */
14119 uint64_t tx_mcast_bytes;
14120 /* Number of transmitted bytes for broadcast traffic */
14121 uint64_t tx_bcast_bytes;
14122 /* Number of TPA eligible packets */
14123 uint64_t rx_tpa_eligible_pkt;
14124 /* Number of TPA eligible bytes */
14125 uint64_t rx_tpa_eligible_bytes;
14126 /* Number of TPA packets */
14127 uint64_t rx_tpa_pkt;
14128 /* Number of TPA bytes */
14129 uint64_t rx_tpa_bytes;
14130 /* Number of TPA errors */
14131 uint64_t rx_tpa_errors;
14132 /* Number of TPA errors */
14133 uint64_t rx_tpa_events;
14134 uint8_t unused_0[7];
14136 * This field is used in Output records to indicate that the output
14137 * is completely written to RAM. This field should be read as '1'
14138 * to indicate that the output has been completely written.
14139 * When writing a command completion or response to an internal processor,
14140 * the order of writes has to be such that this field is written last.
14145 /***********************
14146 * hwrm_func_clr_stats *
14147 ***********************/
14150 /* hwrm_func_clr_stats_input (size:192b/24B) */
14151 struct hwrm_func_clr_stats_input {
14152 /* The HWRM command request type. */
14155 * The completion ring to send the completion event on. This should
14156 * be the NQ ID returned from the `nq_alloc` HWRM command.
14158 uint16_t cmpl_ring;
14160 * The sequence ID is used by the driver for tracking multiple
14161 * commands. This ID is treated as opaque data by the firmware and
14162 * the value is returned in the `hwrm_resp_hdr` upon completion.
14166 * The target ID of the command:
14167 * * 0x0-0xFFF8 - The function ID
14168 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
14169 * * 0xFFFD - Reserved for user-space HWRM interface
14172 uint16_t target_id;
14174 * A physical address pointer pointing to a host buffer that the
14175 * command's response data will be written. This can be either a host
14176 * physical address (HPA) or a guest physical address (GPA) and must
14177 * point to a physically contiguous block of memory.
14179 uint64_t resp_addr;
14181 * Function ID of the function.
14182 * 0xFF... (All Fs) if the query is for the requesting
14186 uint8_t unused_0[6];
14189 /* hwrm_func_clr_stats_output (size:128b/16B) */
14190 struct hwrm_func_clr_stats_output {
14191 /* The specific error status for the command. */
14192 uint16_t error_code;
14193 /* The HWRM command request type. */
14195 /* The sequence ID from the original command. */
14197 /* The length of the response data in number of bytes. */
14199 uint8_t unused_0[7];
14201 * This field is used in Output records to indicate that the output
14202 * is completely written to RAM. This field should be read as '1'
14203 * to indicate that the output has been completely written.
14204 * When writing a command completion or response to an internal processor,
14205 * the order of writes has to be such that this field is written last.
14210 /**************************
14211 * hwrm_func_vf_resc_free *
14212 **************************/
14215 /* hwrm_func_vf_resc_free_input (size:192b/24B) */
14216 struct hwrm_func_vf_resc_free_input {
14217 /* The HWRM command request type. */
14220 * The completion ring to send the completion event on. This should
14221 * be the NQ ID returned from the `nq_alloc` HWRM command.
14223 uint16_t cmpl_ring;
14225 * The sequence ID is used by the driver for tracking multiple
14226 * commands. This ID is treated as opaque data by the firmware and
14227 * the value is returned in the `hwrm_resp_hdr` upon completion.
14231 * The target ID of the command:
14232 * * 0x0-0xFFF8 - The function ID
14233 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
14234 * * 0xFFFD - Reserved for user-space HWRM interface
14237 uint16_t target_id;
14239 * A physical address pointer pointing to a host buffer that the
14240 * command's response data will be written. This can be either a host
14241 * physical address (HPA) or a guest physical address (GPA) and must
14242 * point to a physically contiguous block of memory.
14244 uint64_t resp_addr;
14246 * This value is used to identify a Virtual Function (VF).
14247 * The scope of VF ID is local within a PF.
14250 uint8_t unused_0[6];
14253 /* hwrm_func_vf_resc_free_output (size:128b/16B) */
14254 struct hwrm_func_vf_resc_free_output {
14255 /* The specific error status for the command. */
14256 uint16_t error_code;
14257 /* The HWRM command request type. */
14259 /* The sequence ID from the original command. */
14261 /* The length of the response data in number of bytes. */
14263 uint8_t unused_0[7];
14265 * This field is used in Output records to indicate that the output
14266 * is completely written to RAM. This field should be read as '1'
14267 * to indicate that the output has been completely written.
14268 * When writing a command completion or response to an internal processor,
14269 * the order of writes has to be such that this field is written last.
14274 /**********************
14275 * hwrm_func_drv_rgtr *
14276 **********************/
14279 /* hwrm_func_drv_rgtr_input (size:896b/112B) */
14280 struct hwrm_func_drv_rgtr_input {
14281 /* The HWRM command request type. */
14284 * The completion ring to send the completion event on. This should
14285 * be the NQ ID returned from the `nq_alloc` HWRM command.
14287 uint16_t cmpl_ring;
14289 * The sequence ID is used by the driver for tracking multiple
14290 * commands. This ID is treated as opaque data by the firmware and
14291 * the value is returned in the `hwrm_resp_hdr` upon completion.
14295 * The target ID of the command:
14296 * * 0x0-0xFFF8 - The function ID
14297 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
14298 * * 0xFFFD - Reserved for user-space HWRM interface
14301 uint16_t target_id;
14303 * A physical address pointer pointing to a host buffer that the
14304 * command's response data will be written. This can be either a host
14305 * physical address (HPA) or a guest physical address (GPA) and must
14306 * point to a physically contiguous block of memory.
14308 uint64_t resp_addr;
14311 * When this bit is '1', the function driver is requesting
14312 * all requests from its children VF drivers to be
14313 * forwarded to itself.
14314 * This flag can only be set by the PF driver.
14315 * If a VF driver sets this flag, it should be ignored
14318 #define HWRM_FUNC_DRV_RGTR_INPUT_FLAGS_FWD_ALL_MODE \
14321 * When this bit is '1', the function is requesting none of
14322 * the requests from its children VF drivers to be
14323 * forwarded to itself.
14324 * This flag can only be set by the PF driver.
14325 * If a VF driver sets this flag, it should be ignored
14328 #define HWRM_FUNC_DRV_RGTR_INPUT_FLAGS_FWD_NONE_MODE \
14331 * When this bit is '1', then ver_maj_8b, ver_min_8b, ver_upd_8b
14332 * fields shall be ignored and ver_maj, ver_min, ver_upd
14333 * and ver_patch shall be used for the driver version information.
14334 * When this bit is '0', then ver_maj_8b, ver_min_8b, ver_upd_8b
14335 * fields shall be used for the driver version information and
14336 * ver_maj, ver_min, ver_upd and ver_patch shall be ignored.
14338 #define HWRM_FUNC_DRV_RGTR_INPUT_FLAGS_16BIT_VER_MODE \
14341 * When this bit is '1', the function is indicating support of
14342 * 64bit flow handle. The firmware that only supports 64bit flow
14343 * handle should check this bit before allowing processing of
14344 * HWRM_CFA_FLOW_XXX commands from the requesting function as firmware
14345 * with 64bit flow handle support can only be compatible with drivers
14346 * that support 64bit flow handle. The legacy drivers that don't support
14347 * 64bit flow handle won't be able to use HWRM_CFA_FLOW_XXX commands when
14348 * running with new firmware that only supports 64bit flow handle. The new
14349 * firmware support 64bit flow handle returns HWRM_ERR_CODE_CMD_NOT_SUPPORTED
14350 * status to the legacy driver when encounters these commands.
14352 #define HWRM_FUNC_DRV_RGTR_INPUT_FLAGS_FLOW_HANDLE_64BIT_MODE \
14355 * When this bit is '1', the function is indicating support of
14356 * Hot Reset. The driver interface will destroy the resources,
14357 * unregister the function and register again up on receiving
14358 * the RESET_NOTIFY Async notification from the core firmware.
14359 * The core firmware will this use flag and trigger the Hot Reset
14360 * process only if all the registered driver instances are capable
14363 #define HWRM_FUNC_DRV_RGTR_INPUT_FLAGS_HOT_RESET_SUPPORT \
14366 * When this bit is 1, the function is indicating the support of the
14367 * error recovery capability. Error recovery support will be used by
14368 * firmware only if all the driver instances support error recovery
14369 * process. By setting this bit, driver is indicating support for
14370 * corresponding async event completion message. These will be
14371 * delivered to the driver even if they did not register for it.
14372 * If supported, after receiving reset notify async event with fatal
14373 * flag set in event data1, then all the drivers have to tear down
14374 * their resources without sending any HWRM commands to FW.
14376 #define HWRM_FUNC_DRV_RGTR_INPUT_FLAGS_ERROR_RECOVERY_SUPPORT \
14379 * When this bit is 1, the function is indicating the support of the
14380 * Master capability. The Firmware will use this capability to select the
14381 * Master function. The master function will be used to initiate
14382 * designated functionality like error recovery etc… If none of the
14383 * registered PF’s or trusted VF’s indicate this support, then
14384 * firmware will select the 1st registered PF as Master capable instance.
14386 #define HWRM_FUNC_DRV_RGTR_INPUT_FLAGS_MASTER_SUPPORT \
14389 * When this bit is 1, the function is indicating the support of the
14390 * fast reset capability. Fast reset support will be used by
14391 * firmware only if all the driver instances support fast reset
14392 * process. By setting this bit, driver is indicating support for
14393 * corresponding async event completion message. These will be
14394 * delivered to the driver even if they did not register for it.
14395 * If supported, after receiving reset notify async event with fast
14396 * reset flag set in event data1, then all the drivers have to tear
14397 * down their resources without sending any HWRM commands to FW.
14399 #define HWRM_FUNC_DRV_RGTR_INPUT_FLAGS_FAST_RESET_SUPPORT \
14402 * When this bit is 1, the function's driver is indicating the
14403 * support of handling the vnic_rss_cfg's INVALID_PARAM error
14404 * returned by firmware. Firmware returns error, if host driver
14405 * configures the invalid hash_types bit combination for a given
14408 #define HWRM_FUNC_DRV_RGTR_INPUT_FLAGS_RSS_STRICT_HASH_TYPE_SUPPORT \
14411 * When this bit is 1, the function's driver is indicating the
14412 * support of handling the NPAR 1.2 feature where the s-tag may be
14413 * a value other than 0x8100 or 0x88a8.
14415 #define HWRM_FUNC_DRV_RGTR_INPUT_FLAGS_NPAR_1_2_SUPPORT \
14419 * This bit must be '1' for the os_type field to be
14422 #define HWRM_FUNC_DRV_RGTR_INPUT_ENABLES_OS_TYPE \
14425 * This bit must be '1' for the ver field to be
14428 #define HWRM_FUNC_DRV_RGTR_INPUT_ENABLES_VER \
14431 * This bit must be '1' for the timestamp field to be
14434 #define HWRM_FUNC_DRV_RGTR_INPUT_ENABLES_TIMESTAMP \
14437 * This bit must be '1' for the vf_req_fwd field to be
14440 #define HWRM_FUNC_DRV_RGTR_INPUT_ENABLES_VF_REQ_FWD \
14443 * This bit must be '1' for the async_event_fwd field to be
14446 #define HWRM_FUNC_DRV_RGTR_INPUT_ENABLES_ASYNC_EVENT_FWD \
14448 /* This value indicates the type of OS. The values are based on CIM_OperatingSystem.mof file as published by the DMTF. */
14451 #define HWRM_FUNC_DRV_RGTR_INPUT_OS_TYPE_UNKNOWN UINT32_C(0x0)
14452 /* Other OS not listed below. */
14453 #define HWRM_FUNC_DRV_RGTR_INPUT_OS_TYPE_OTHER UINT32_C(0x1)
14455 #define HWRM_FUNC_DRV_RGTR_INPUT_OS_TYPE_MSDOS UINT32_C(0xe)
14457 #define HWRM_FUNC_DRV_RGTR_INPUT_OS_TYPE_WINDOWS UINT32_C(0x12)
14459 #define HWRM_FUNC_DRV_RGTR_INPUT_OS_TYPE_SOLARIS UINT32_C(0x1d)
14461 #define HWRM_FUNC_DRV_RGTR_INPUT_OS_TYPE_LINUX UINT32_C(0x24)
14463 #define HWRM_FUNC_DRV_RGTR_INPUT_OS_TYPE_FREEBSD UINT32_C(0x2a)
14464 /* VMware ESXi OS. */
14465 #define HWRM_FUNC_DRV_RGTR_INPUT_OS_TYPE_ESXI UINT32_C(0x68)
14466 /* Microsoft Windows 8 64-bit OS. */
14467 #define HWRM_FUNC_DRV_RGTR_INPUT_OS_TYPE_WIN864 UINT32_C(0x73)
14468 /* Microsoft Windows Server 2012 R2 OS. */
14469 #define HWRM_FUNC_DRV_RGTR_INPUT_OS_TYPE_WIN2012R2 UINT32_C(0x74)
14471 #define HWRM_FUNC_DRV_RGTR_INPUT_OS_TYPE_UEFI UINT32_C(0x8000)
14472 #define HWRM_FUNC_DRV_RGTR_INPUT_OS_TYPE_LAST \
14473 HWRM_FUNC_DRV_RGTR_INPUT_OS_TYPE_UEFI
14474 /* This is the 8bit major version of the driver. */
14475 uint8_t ver_maj_8b;
14476 /* This is the 8bit minor version of the driver. */
14477 uint8_t ver_min_8b;
14478 /* This is the 8bit update version of the driver. */
14479 uint8_t ver_upd_8b;
14480 uint8_t unused_0[3];
14482 * This is a 32-bit timestamp provided by the driver for
14484 * The timestamp is in multiples of 1ms.
14486 uint32_t timestamp;
14487 uint8_t unused_1[4];
14489 * This is a 256-bit bit mask provided by the PF driver for
14490 * letting the HWRM know what commands issued by the VF driver
14491 * to the HWRM should be forwarded to the PF driver.
14492 * Nth bit refers to the Nth req_type.
14494 * Setting Nth bit to 1 indicates that requests from the
14495 * VF driver with req_type equal to N shall be forwarded to
14496 * the parent PF driver.
14498 * This field is not valid for the VF driver.
14500 uint32_t vf_req_fwd[8];
14502 * This is a 256-bit bit mask provided by the function driver
14503 * (PF or VF driver) to indicate the list of asynchronous event
14504 * completions to be forwarded.
14506 * Nth bit refers to the Nth event_id.
14508 * Setting Nth bit to 1 by the function driver shall result in
14509 * the HWRM forwarding asynchronous event completion with
14510 * event_id equal to N.
14512 * If all bits are set to 0 (value of 0), then the HWRM shall
14513 * not forward any asynchronous event completion to this
14516 uint32_t async_event_fwd[8];
14517 /* This is the 16bit major version of the driver. */
14519 /* This is the 16bit minor version of the driver. */
14521 /* This is the 16bit update version of the driver. */
14523 /* This is the 16bit patch version of the driver. */
14524 uint16_t ver_patch;
14527 /* hwrm_func_drv_rgtr_output (size:128b/16B) */
14528 struct hwrm_func_drv_rgtr_output {
14529 /* The specific error status for the command. */
14530 uint16_t error_code;
14531 /* The HWRM command request type. */
14533 /* The sequence ID from the original command. */
14535 /* The length of the response data in number of bytes. */
14539 * When this bit is '1', it indicates that the
14540 * HWRM_FUNC_DRV_IF_CHANGE call is supported.
14542 #define HWRM_FUNC_DRV_RGTR_OUTPUT_FLAGS_IF_CHANGE_SUPPORTED \
14544 uint8_t unused_0[3];
14546 * This field is used in Output records to indicate that the output
14547 * is completely written to RAM. This field should be read as '1'
14548 * to indicate that the output has been completely written.
14549 * When writing a command completion or response to an internal processor,
14550 * the order of writes has to be such that this field is written last.
14555 /************************
14556 * hwrm_func_drv_unrgtr *
14557 ************************/
14560 /* hwrm_func_drv_unrgtr_input (size:192b/24B) */
14561 struct hwrm_func_drv_unrgtr_input {
14562 /* The HWRM command request type. */
14565 * The completion ring to send the completion event on. This should
14566 * be the NQ ID returned from the `nq_alloc` HWRM command.
14568 uint16_t cmpl_ring;
14570 * The sequence ID is used by the driver for tracking multiple
14571 * commands. This ID is treated as opaque data by the firmware and
14572 * the value is returned in the `hwrm_resp_hdr` upon completion.
14576 * The target ID of the command:
14577 * * 0x0-0xFFF8 - The function ID
14578 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
14579 * * 0xFFFD - Reserved for user-space HWRM interface
14582 uint16_t target_id;
14584 * A physical address pointer pointing to a host buffer that the
14585 * command's response data will be written. This can be either a host
14586 * physical address (HPA) or a guest physical address (GPA) and must
14587 * point to a physically contiguous block of memory.
14589 uint64_t resp_addr;
14592 * When this bit is '1', the function driver is notifying
14593 * the HWRM to prepare for the shutdown.
14595 #define HWRM_FUNC_DRV_UNRGTR_INPUT_FLAGS_PREPARE_FOR_SHUTDOWN \
14597 uint8_t unused_0[4];
14600 /* hwrm_func_drv_unrgtr_output (size:128b/16B) */
14601 struct hwrm_func_drv_unrgtr_output {
14602 /* The specific error status for the command. */
14603 uint16_t error_code;
14604 /* The HWRM command request type. */
14606 /* The sequence ID from the original command. */
14608 /* The length of the response data in number of bytes. */
14610 uint8_t unused_0[7];
14612 * This field is used in Output records to indicate that the output
14613 * is completely written to RAM. This field should be read as '1'
14614 * to indicate that the output has been completely written.
14615 * When writing a command completion or response to an internal processor,
14616 * the order of writes has to be such that this field is written last.
14621 /**********************
14622 * hwrm_func_buf_rgtr *
14623 **********************/
14626 /* hwrm_func_buf_rgtr_input (size:1024b/128B) */
14627 struct hwrm_func_buf_rgtr_input {
14628 /* The HWRM command request type. */
14631 * The completion ring to send the completion event on. This should
14632 * be the NQ ID returned from the `nq_alloc` HWRM command.
14634 uint16_t cmpl_ring;
14636 * The sequence ID is used by the driver for tracking multiple
14637 * commands. This ID is treated as opaque data by the firmware and
14638 * the value is returned in the `hwrm_resp_hdr` upon completion.
14642 * The target ID of the command:
14643 * * 0x0-0xFFF8 - The function ID
14644 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
14645 * * 0xFFFD - Reserved for user-space HWRM interface
14648 uint16_t target_id;
14650 * A physical address pointer pointing to a host buffer that the
14651 * command's response data will be written. This can be either a host
14652 * physical address (HPA) or a guest physical address (GPA) and must
14653 * point to a physically contiguous block of memory.
14655 uint64_t resp_addr;
14658 * This bit must be '1' for the vf_id field to be
14661 #define HWRM_FUNC_BUF_RGTR_INPUT_ENABLES_VF_ID UINT32_C(0x1)
14663 * This bit must be '1' for the err_buf_addr field to be
14666 #define HWRM_FUNC_BUF_RGTR_INPUT_ENABLES_ERR_BUF_ADDR UINT32_C(0x2)
14668 * This value is used to identify a Virtual Function (VF).
14669 * The scope of VF ID is local within a PF.
14673 * This field represents the number of pages used for request
14676 uint16_t req_buf_num_pages;
14678 * This field represents the page size used for request
14681 uint16_t req_buf_page_size;
14683 #define HWRM_FUNC_BUF_RGTR_INPUT_REQ_BUF_PAGE_SIZE_16B UINT32_C(0x4)
14685 #define HWRM_FUNC_BUF_RGTR_INPUT_REQ_BUF_PAGE_SIZE_4K UINT32_C(0xc)
14687 #define HWRM_FUNC_BUF_RGTR_INPUT_REQ_BUF_PAGE_SIZE_8K UINT32_C(0xd)
14689 #define HWRM_FUNC_BUF_RGTR_INPUT_REQ_BUF_PAGE_SIZE_64K UINT32_C(0x10)
14691 #define HWRM_FUNC_BUF_RGTR_INPUT_REQ_BUF_PAGE_SIZE_2M UINT32_C(0x15)
14693 #define HWRM_FUNC_BUF_RGTR_INPUT_REQ_BUF_PAGE_SIZE_4M UINT32_C(0x16)
14695 #define HWRM_FUNC_BUF_RGTR_INPUT_REQ_BUF_PAGE_SIZE_1G UINT32_C(0x1e)
14696 #define HWRM_FUNC_BUF_RGTR_INPUT_REQ_BUF_PAGE_SIZE_LAST \
14697 HWRM_FUNC_BUF_RGTR_INPUT_REQ_BUF_PAGE_SIZE_1G
14698 /* The length of the request buffer per VF in bytes. */
14699 uint16_t req_buf_len;
14700 /* The length of the response buffer in bytes. */
14701 uint16_t resp_buf_len;
14702 uint8_t unused_0[2];
14703 /* This field represents the page address of page #0. */
14704 uint64_t req_buf_page_addr0;
14705 /* This field represents the page address of page #1. */
14706 uint64_t req_buf_page_addr1;
14707 /* This field represents the page address of page #2. */
14708 uint64_t req_buf_page_addr2;
14709 /* This field represents the page address of page #3. */
14710 uint64_t req_buf_page_addr3;
14711 /* This field represents the page address of page #4. */
14712 uint64_t req_buf_page_addr4;
14713 /* This field represents the page address of page #5. */
14714 uint64_t req_buf_page_addr5;
14715 /* This field represents the page address of page #6. */
14716 uint64_t req_buf_page_addr6;
14717 /* This field represents the page address of page #7. */
14718 uint64_t req_buf_page_addr7;
14719 /* This field represents the page address of page #8. */
14720 uint64_t req_buf_page_addr8;
14721 /* This field represents the page address of page #9. */
14722 uint64_t req_buf_page_addr9;
14724 * This field is used to receive the error reporting from
14725 * the chipset. Only applicable for PFs.
14727 uint64_t error_buf_addr;
14729 * This field is used to receive the response forwarded by the
14732 uint64_t resp_buf_addr;
14735 /* hwrm_func_buf_rgtr_output (size:128b/16B) */
14736 struct hwrm_func_buf_rgtr_output {
14737 /* The specific error status for the command. */
14738 uint16_t error_code;
14739 /* The HWRM command request type. */
14741 /* The sequence ID from the original command. */
14743 /* The length of the response data in number of bytes. */
14745 uint8_t unused_0[7];
14747 * This field is used in Output records to indicate that the output
14748 * is completely written to RAM. This field should be read as '1'
14749 * to indicate that the output has been completely written.
14750 * When writing a command completion or response to an internal processor,
14751 * the order of writes has to be such that this field is written last.
14756 /************************
14757 * hwrm_func_buf_unrgtr *
14758 ************************/
14761 /* hwrm_func_buf_unrgtr_input (size:192b/24B) */
14762 struct hwrm_func_buf_unrgtr_input {
14763 /* The HWRM command request type. */
14766 * The completion ring to send the completion event on. This should
14767 * be the NQ ID returned from the `nq_alloc` HWRM command.
14769 uint16_t cmpl_ring;
14771 * The sequence ID is used by the driver for tracking multiple
14772 * commands. This ID is treated as opaque data by the firmware and
14773 * the value is returned in the `hwrm_resp_hdr` upon completion.
14777 * The target ID of the command:
14778 * * 0x0-0xFFF8 - The function ID
14779 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
14780 * * 0xFFFD - Reserved for user-space HWRM interface
14783 uint16_t target_id;
14785 * A physical address pointer pointing to a host buffer that the
14786 * command's response data will be written. This can be either a host
14787 * physical address (HPA) or a guest physical address (GPA) and must
14788 * point to a physically contiguous block of memory.
14790 uint64_t resp_addr;
14793 * This bit must be '1' for the vf_id field to be
14796 #define HWRM_FUNC_BUF_UNRGTR_INPUT_ENABLES_VF_ID UINT32_C(0x1)
14798 * This value is used to identify a Virtual Function (VF).
14799 * The scope of VF ID is local within a PF.
14802 uint8_t unused_0[2];
14805 /* hwrm_func_buf_unrgtr_output (size:128b/16B) */
14806 struct hwrm_func_buf_unrgtr_output {
14807 /* The specific error status for the command. */
14808 uint16_t error_code;
14809 /* The HWRM command request type. */
14811 /* The sequence ID from the original command. */
14813 /* The length of the response data in number of bytes. */
14815 uint8_t unused_0[7];
14817 * This field is used in Output records to indicate that the output
14818 * is completely written to RAM. This field should be read as '1'
14819 * to indicate that the output has been completely written.
14820 * When writing a command completion or response to an internal processor,
14821 * the order of writes has to be such that this field is written last.
14826 /**********************
14827 * hwrm_func_drv_qver *
14828 **********************/
14831 /* hwrm_func_drv_qver_input (size:192b/24B) */
14832 struct hwrm_func_drv_qver_input {
14833 /* The HWRM command request type. */
14836 * The completion ring to send the completion event on. This should
14837 * be the NQ ID returned from the `nq_alloc` HWRM command.
14839 uint16_t cmpl_ring;
14841 * The sequence ID is used by the driver for tracking multiple
14842 * commands. This ID is treated as opaque data by the firmware and
14843 * the value is returned in the `hwrm_resp_hdr` upon completion.
14847 * The target ID of the command:
14848 * * 0x0-0xFFF8 - The function ID
14849 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
14850 * * 0xFFFD - Reserved for user-space HWRM interface
14853 uint16_t target_id;
14855 * A physical address pointer pointing to a host buffer that the
14856 * command's response data will be written. This can be either a host
14857 * physical address (HPA) or a guest physical address (GPA) and must
14858 * point to a physically contiguous block of memory.
14860 uint64_t resp_addr;
14861 /* Reserved for future use. */
14864 * Function ID of the function that is being queried.
14865 * 0xFF... (All Fs) if the query is for the requesting
14869 uint8_t unused_0[2];
14872 /* hwrm_func_drv_qver_output (size:256b/32B) */
14873 struct hwrm_func_drv_qver_output {
14874 /* The specific error status for the command. */
14875 uint16_t error_code;
14876 /* The HWRM command request type. */
14878 /* The sequence ID from the original command. */
14880 /* The length of the response data in number of bytes. */
14882 /* This value indicates the type of OS. The values are based on CIM_OperatingSystem.mof file as published by the DMTF. */
14885 #define HWRM_FUNC_DRV_QVER_OUTPUT_OS_TYPE_UNKNOWN UINT32_C(0x0)
14886 /* Other OS not listed below. */
14887 #define HWRM_FUNC_DRV_QVER_OUTPUT_OS_TYPE_OTHER UINT32_C(0x1)
14889 #define HWRM_FUNC_DRV_QVER_OUTPUT_OS_TYPE_MSDOS UINT32_C(0xe)
14891 #define HWRM_FUNC_DRV_QVER_OUTPUT_OS_TYPE_WINDOWS UINT32_C(0x12)
14893 #define HWRM_FUNC_DRV_QVER_OUTPUT_OS_TYPE_SOLARIS UINT32_C(0x1d)
14895 #define HWRM_FUNC_DRV_QVER_OUTPUT_OS_TYPE_LINUX UINT32_C(0x24)
14897 #define HWRM_FUNC_DRV_QVER_OUTPUT_OS_TYPE_FREEBSD UINT32_C(0x2a)
14898 /* VMware ESXi OS. */
14899 #define HWRM_FUNC_DRV_QVER_OUTPUT_OS_TYPE_ESXI UINT32_C(0x68)
14900 /* Microsoft Windows 8 64-bit OS. */
14901 #define HWRM_FUNC_DRV_QVER_OUTPUT_OS_TYPE_WIN864 UINT32_C(0x73)
14902 /* Microsoft Windows Server 2012 R2 OS. */
14903 #define HWRM_FUNC_DRV_QVER_OUTPUT_OS_TYPE_WIN2012R2 UINT32_C(0x74)
14905 #define HWRM_FUNC_DRV_QVER_OUTPUT_OS_TYPE_UEFI UINT32_C(0x8000)
14906 #define HWRM_FUNC_DRV_QVER_OUTPUT_OS_TYPE_LAST \
14907 HWRM_FUNC_DRV_QVER_OUTPUT_OS_TYPE_UEFI
14908 /* This is the 8bit major version of the driver. */
14909 uint8_t ver_maj_8b;
14910 /* This is the 8bit minor version of the driver. */
14911 uint8_t ver_min_8b;
14912 /* This is the 8bit update version of the driver. */
14913 uint8_t ver_upd_8b;
14914 uint8_t unused_0[3];
14915 /* This is the 16bit major version of the driver. */
14917 /* This is the 16bit minor version of the driver. */
14919 /* This is the 16bit update version of the driver. */
14921 /* This is the 16bit patch version of the driver. */
14922 uint16_t ver_patch;
14923 uint8_t unused_1[7];
14925 * This field is used in Output records to indicate that the output
14926 * is completely written to RAM. This field should be read as '1'
14927 * to indicate that the output has been completely written.
14928 * When writing a command completion or response to an internal processor,
14929 * the order of writes has to be such that this field is written last.
14934 /****************************
14935 * hwrm_func_resource_qcaps *
14936 ****************************/
14939 /* hwrm_func_resource_qcaps_input (size:192b/24B) */
14940 struct hwrm_func_resource_qcaps_input {
14941 /* The HWRM command request type. */
14944 * The completion ring to send the completion event on. This should
14945 * be the NQ ID returned from the `nq_alloc` HWRM command.
14947 uint16_t cmpl_ring;
14949 * The sequence ID is used by the driver for tracking multiple
14950 * commands. This ID is treated as opaque data by the firmware and
14951 * the value is returned in the `hwrm_resp_hdr` upon completion.
14955 * The target ID of the command:
14956 * * 0x0-0xFFF8 - The function ID
14957 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
14958 * * 0xFFFD - Reserved for user-space HWRM interface
14961 uint16_t target_id;
14963 * A physical address pointer pointing to a host buffer that the
14964 * command's response data will be written. This can be either a host
14965 * physical address (HPA) or a guest physical address (GPA) and must
14966 * point to a physically contiguous block of memory.
14968 uint64_t resp_addr;
14970 * Function ID of the function that is being queried.
14971 * 0xFF... (All Fs) if the query is for the requesting
14975 uint8_t unused_0[6];
14978 /* hwrm_func_resource_qcaps_output (size:512b/64B) */
14979 struct hwrm_func_resource_qcaps_output {
14980 /* The specific error status for the command. */
14981 uint16_t error_code;
14982 /* The HWRM command request type. */
14984 /* The sequence ID from the original command. */
14986 /* The length of the response data in number of bytes. */
14988 /* Maximum guaranteed number of VFs supported by PF. Not applicable for VFs. */
14990 /* Maximum guaranteed number of MSI-X vectors supported by function */
14992 /* Hint of strategy to be used by PF driver to reserve resources for its VF */
14993 uint16_t vf_reservation_strategy;
14994 /* The PF driver should evenly divide its remaining resources among all VFs. */
14995 #define HWRM_FUNC_RESOURCE_QCAPS_OUTPUT_VF_RESERVATION_STRATEGY_MAXIMAL \
14997 /* The PF driver should only reserve minimal resources for each VF. */
14998 #define HWRM_FUNC_RESOURCE_QCAPS_OUTPUT_VF_RESERVATION_STRATEGY_MINIMAL \
15001 * The PF driver should not reserve any resources for each VF until
15002 * the VF interface is brought up.
15004 #define HWRM_FUNC_RESOURCE_QCAPS_OUTPUT_VF_RESERVATION_STRATEGY_MINIMAL_STATIC \
15006 #define HWRM_FUNC_RESOURCE_QCAPS_OUTPUT_VF_RESERVATION_STRATEGY_LAST \
15007 HWRM_FUNC_RESOURCE_QCAPS_OUTPUT_VF_RESERVATION_STRATEGY_MINIMAL_STATIC
15008 /* Minimum guaranteed number of RSS/COS contexts */
15009 uint16_t min_rsscos_ctx;
15010 /* Maximum non-guaranteed number of RSS/COS contexts */
15011 uint16_t max_rsscos_ctx;
15012 /* Minimum guaranteed number of completion rings */
15013 uint16_t min_cmpl_rings;
15014 /* Maximum non-guaranteed number of completion rings */
15015 uint16_t max_cmpl_rings;
15016 /* Minimum guaranteed number of transmit rings */
15017 uint16_t min_tx_rings;
15018 /* Maximum non-guaranteed number of transmit rings */
15019 uint16_t max_tx_rings;
15020 /* Minimum guaranteed number of receive rings */
15021 uint16_t min_rx_rings;
15022 /* Maximum non-guaranteed number of receive rings */
15023 uint16_t max_rx_rings;
15024 /* Minimum guaranteed number of L2 contexts */
15025 uint16_t min_l2_ctxs;
15026 /* Maximum non-guaranteed number of L2 contexts */
15027 uint16_t max_l2_ctxs;
15028 /* Minimum guaranteed number of VNICs */
15029 uint16_t min_vnics;
15030 /* Maximum non-guaranteed number of VNICs */
15031 uint16_t max_vnics;
15032 /* Minimum guaranteed number of statistic contexts */
15033 uint16_t min_stat_ctx;
15034 /* Maximum non-guaranteed number of statistic contexts */
15035 uint16_t max_stat_ctx;
15036 /* Minimum guaranteed number of ring groups */
15037 uint16_t min_hw_ring_grps;
15038 /* Maximum non-guaranteed number of ring groups */
15039 uint16_t max_hw_ring_grps;
15041 * Maximum number of inputs into the transmit scheduler for this function.
15042 * The number of TX rings assigned to the function cannot exceed this value.
15044 uint16_t max_tx_scheduler_inputs;
15047 * When this bit is '1', it indicates that VF_RESOURCE_CFG supports
15048 * feature to reserve all minimum resources when minimum >= 1, otherwise
15049 * returns an error.
15051 #define HWRM_FUNC_RESOURCE_QCAPS_OUTPUT_FLAGS_MIN_GUARANTEED \
15053 /* Minimum guaranteed number of Tx Key Contexts */
15054 uint16_t min_tx_key_ctxs;
15055 /* Maximum non-guaranteed number of Tx Key Contexts */
15056 uint16_t max_tx_key_ctxs;
15057 /* Minimum guaranteed number of Rx Key Contexts */
15058 uint16_t min_rx_key_ctxs;
15059 /* Maximum non-guaranteed number of Rx Key Contexts */
15060 uint16_t max_rx_key_ctxs;
15061 uint8_t unused_0[5];
15063 * This field is used in Output records to indicate that the output
15064 * is completely written to RAM. This field should be read as '1'
15065 * to indicate that the output has been completely written.
15066 * When writing a command completion or response to an internal processor,
15067 * the order of writes has to be such that this field is written last.
15072 /*****************************
15073 * hwrm_func_vf_resource_cfg *
15074 *****************************/
15077 /* hwrm_func_vf_resource_cfg_input (size:512b/64B) */
15078 struct hwrm_func_vf_resource_cfg_input {
15079 /* The HWRM command request type. */
15082 * The completion ring to send the completion event on. This should
15083 * be the NQ ID returned from the `nq_alloc` HWRM command.
15085 uint16_t cmpl_ring;
15087 * The sequence ID is used by the driver for tracking multiple
15088 * commands. This ID is treated as opaque data by the firmware and
15089 * the value is returned in the `hwrm_resp_hdr` upon completion.
15093 * The target ID of the command:
15094 * * 0x0-0xFFF8 - The function ID
15095 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
15096 * * 0xFFFD - Reserved for user-space HWRM interface
15099 uint16_t target_id;
15101 * A physical address pointer pointing to a host buffer that the
15102 * command's response data will be written. This can be either a host
15103 * physical address (HPA) or a guest physical address (GPA) and must
15104 * point to a physically contiguous block of memory.
15106 uint64_t resp_addr;
15107 /* VF ID that is being configured by PF */
15109 /* Maximum guaranteed number of MSI-X vectors for the function */
15111 /* Minimum guaranteed number of RSS/COS contexts */
15112 uint16_t min_rsscos_ctx;
15113 /* Maximum non-guaranteed number of RSS/COS contexts */
15114 uint16_t max_rsscos_ctx;
15115 /* Minimum guaranteed number of completion rings */
15116 uint16_t min_cmpl_rings;
15117 /* Maximum non-guaranteed number of completion rings */
15118 uint16_t max_cmpl_rings;
15119 /* Minimum guaranteed number of transmit rings */
15120 uint16_t min_tx_rings;
15121 /* Maximum non-guaranteed number of transmit rings */
15122 uint16_t max_tx_rings;
15123 /* Minimum guaranteed number of receive rings */
15124 uint16_t min_rx_rings;
15125 /* Maximum non-guaranteed number of receive rings */
15126 uint16_t max_rx_rings;
15127 /* Minimum guaranteed number of L2 contexts */
15128 uint16_t min_l2_ctxs;
15129 /* Maximum non-guaranteed number of L2 contexts */
15130 uint16_t max_l2_ctxs;
15131 /* Minimum guaranteed number of VNICs */
15132 uint16_t min_vnics;
15133 /* Maximum non-guaranteed number of VNICs */
15134 uint16_t max_vnics;
15135 /* Minimum guaranteed number of statistic contexts */
15136 uint16_t min_stat_ctx;
15137 /* Maximum non-guaranteed number of statistic contexts */
15138 uint16_t max_stat_ctx;
15139 /* Minimum guaranteed number of ring groups */
15140 uint16_t min_hw_ring_grps;
15141 /* Maximum non-guaranteed number of ring groups */
15142 uint16_t max_hw_ring_grps;
15145 * If this bit is set, all minimum resources requested should be
15146 * reserved if minimum >= 1, otherwise return error. In case of
15147 * error, keep all existing reservations before the call.
15149 #define HWRM_FUNC_VF_RESOURCE_CFG_INPUT_FLAGS_MIN_GUARANTEED \
15151 /* Minimum guaranteed number of Tx Key Contexts */
15152 uint16_t min_tx_key_ctxs;
15153 /* Maximum non-guaranteed number of Tx Key Contexts */
15154 uint16_t max_tx_key_ctxs;
15155 /* Minimum guaranteed number of Rx Key Contexts */
15156 uint16_t min_rx_key_ctxs;
15157 /* Maximum non-guaranteed number of Rx Key Contexts */
15158 uint16_t max_rx_key_ctxs;
15159 uint8_t unused_0[2];
15162 /* hwrm_func_vf_resource_cfg_output (size:256b/32B) */
15163 struct hwrm_func_vf_resource_cfg_output {
15164 /* The specific error status for the command. */
15165 uint16_t error_code;
15166 /* The HWRM command request type. */
15168 /* The sequence ID from the original command. */
15170 /* The length of the response data in number of bytes. */
15172 /* Reserved number of RSS/COS contexts */
15173 uint16_t reserved_rsscos_ctx;
15174 /* Reserved number of completion rings */
15175 uint16_t reserved_cmpl_rings;
15176 /* Reserved number of transmit rings */
15177 uint16_t reserved_tx_rings;
15178 /* Reserved number of receive rings */
15179 uint16_t reserved_rx_rings;
15180 /* Reserved number of L2 contexts */
15181 uint16_t reserved_l2_ctxs;
15182 /* Reserved number of VNICs */
15183 uint16_t reserved_vnics;
15184 /* Reserved number of statistic contexts */
15185 uint16_t reserved_stat_ctx;
15186 /* Reserved number of ring groups */
15187 uint16_t reserved_hw_ring_grps;
15188 /* Actual number of Tx Key Contexts reserved */
15189 uint16_t reserved_tx_key_ctxs;
15190 /* Actual number of Rx Key Contexts reserved */
15191 uint16_t reserved_rx_key_ctxs;
15192 uint8_t unused_0[3];
15194 * This field is used in Output records to indicate that the output
15195 * is completely written to RAM. This field should be read as '1'
15196 * to indicate that the output has been completely written.
15197 * When writing a command completion or response to an internal processor,
15198 * the order of writes has to be such that this field is written last.
15203 /*********************************
15204 * hwrm_func_backing_store_qcaps *
15205 *********************************/
15208 /* hwrm_func_backing_store_qcaps_input (size:128b/16B) */
15209 struct hwrm_func_backing_store_qcaps_input {
15210 /* The HWRM command request type. */
15213 * The completion ring to send the completion event on. This should
15214 * be the NQ ID returned from the `nq_alloc` HWRM command.
15216 uint16_t cmpl_ring;
15218 * The sequence ID is used by the driver for tracking multiple
15219 * commands. This ID is treated as opaque data by the firmware and
15220 * the value is returned in the `hwrm_resp_hdr` upon completion.
15224 * The target ID of the command:
15225 * * 0x0-0xFFF8 - The function ID
15226 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
15227 * * 0xFFFD - Reserved for user-space HWRM interface
15230 uint16_t target_id;
15232 * A physical address pointer pointing to a host buffer that the
15233 * command's response data will be written. This can be either a host
15234 * physical address (HPA) or a guest physical address (GPA) and must
15235 * point to a physically contiguous block of memory.
15237 uint64_t resp_addr;
15240 /* hwrm_func_backing_store_qcaps_output (size:832b/104B) */
15241 struct hwrm_func_backing_store_qcaps_output {
15242 /* The specific error status for the command. */
15243 uint16_t error_code;
15244 /* The HWRM command request type. */
15246 /* The sequence ID from the original command. */
15248 /* The length of the response data in number of bytes. */
15250 /* Maximum number of QP context entries supported for this function. */
15251 uint32_t qp_max_entries;
15253 * Minimum number of QP context entries that are needed to be reserved
15254 * for QP1 for the PF and its VFs. PF drivers must allocate at least
15255 * this many QP context entries, even if RoCE will not be used.
15257 uint16_t qp_min_qp1_entries;
15259 * Maximum number of QP context entries that can be used for L2 and
15262 uint16_t qp_max_l2_entries;
15263 /* Number of bytes that must be allocated for each context entry. */
15264 uint16_t qp_entry_size;
15265 /* Maximum number of SRQ context entries that can be used for L2. */
15266 uint16_t srq_max_l2_entries;
15267 /* Maximum number of SRQ context entries supported for this function. */
15268 uint32_t srq_max_entries;
15269 /* Number of bytes that must be allocated for each context entry. */
15270 uint16_t srq_entry_size;
15271 /* Maximum number of CQ context entries that can be used for L2. */
15272 uint16_t cq_max_l2_entries;
15273 /* Maximum number of CQ context entries supported for this function. */
15274 uint32_t cq_max_entries;
15275 /* Number of bytes that must be allocated for each context entry. */
15276 uint16_t cq_entry_size;
15277 /* Maximum number of VNIC context entries supported for this function. */
15278 uint16_t vnic_max_vnic_entries;
15279 /* Maximum number of Ring table context entries supported for this function. */
15280 uint16_t vnic_max_ring_table_entries;
15281 /* Number of bytes that must be allocated for each context entry. */
15282 uint16_t vnic_entry_size;
15283 /* Maximum number of statistic context entries supported for this function. */
15284 uint32_t stat_max_entries;
15285 /* Number of bytes that must be allocated for each context entry. */
15286 uint16_t stat_entry_size;
15287 /* Number of bytes that must be allocated for each context entry. */
15288 uint16_t tqm_entry_size;
15289 /* Minimum number of TQM context entries required per ring. */
15290 uint32_t tqm_min_entries_per_ring;
15292 * Maximum number of TQM context entries supported per ring. This is
15293 * actually a recommended TQM queue size based on worst case usage of
15296 * TQM fastpath rings should be sized large enough to accommodate the
15297 * maximum number of QPs (either L2 or RoCE, or both if shared)
15298 * that can be enqueued to the TQM ring.
15300 * TQM slowpath rings should be sized as follows:
15302 * num_entries = num_vnics + num_l2_tx_rings + 2 * num_roce_qps + tqm_min_size
15305 * num_vnics is the number of VNICs allocated in the VNIC backing store
15306 * num_l2_tx_rings is the number of L2 rings in the QP backing store
15307 * num_roce_qps is the number of RoCE QPs in the QP backing store
15308 * tqm_min_size is tqm_min_entries_per_ring reported by
15309 * HWRM_FUNC_BACKING_STORE_QCAPS
15311 * Note that TQM ring sizes cannot be extended while the system is
15312 * operational. If a PF driver needs to extend a TQM ring, it needs
15313 * to reset the function (e.g. HWRM_FUNC_RESET) and then reallocate
15314 * the backing store.
15316 uint32_t tqm_max_entries_per_ring;
15318 * Maximum number of MR plus AV context entries supported for this
15321 uint32_t mrav_max_entries;
15322 /* Number of bytes that must be allocated for each context entry. */
15323 uint16_t mrav_entry_size;
15324 /* Number of bytes that must be allocated for each context entry. */
15325 uint16_t tim_entry_size;
15326 /* Maximum number of Timer context entries supported for this function. */
15327 uint32_t tim_max_entries;
15329 * When this field is zero, the 32b `mrav_num_entries` field in the
15330 * `backing_store_cfg` and `backing_store_qcfg` commands represents
15331 * the total number of MR plus AV entries allowed in the MR/AV backing
15334 * When this field is non-zero, the 32b `mrav_num_entries` field in
15335 * the `backing_store_cfg` and `backing_store_qcfg` commands is
15336 * logically divided into two 16b fields. Bits `[31:16]` represents
15337 * the `mr_num_entries` and bits `[15:0]` represents `av_num_entries`.
15338 * Both of these values are represented in a unit granularity
15339 * specified by this field. For example, if this field is 16 and
15340 * `mrav_num_entries` is `0x02000100`, then the number of MR entries
15341 * is 8192 and the number of AV entries is 4096.
15343 uint16_t mrav_num_entries_units;
15345 * The number of entries specified for any TQM ring must be a
15346 * multiple of this value to prevent any resource allocation
15349 uint8_t tqm_entries_multiple;
15351 * Initializer to be used by drivers
15352 * to initialize context memory to ensure
15353 * context subsystem flags an error for an attack
15354 * before the first time context load.
15356 uint8_t ctx_kind_initializer;
15358 * Specifies which context kinds need to be initialized with the
15359 * ctx_kind_initializer.
15361 uint16_t ctx_init_mask;
15363 * If this bit is '1' then this context type should be initialized
15364 * with the ctx_kind_initializer at the specified offset.
15366 #define HWRM_FUNC_BACKING_STORE_QCAPS_OUTPUT_CTX_INIT_MASK_QP \
15369 * If this bit is '1' then this context type should be initialized
15370 * with the ctx_kind_initializer at the specified offset.
15372 #define HWRM_FUNC_BACKING_STORE_QCAPS_OUTPUT_CTX_INIT_MASK_SRQ \
15375 * If this bit is '1' then this context type should be initialized
15376 * with the ctx_kind_initializer at the specified offset.
15378 #define HWRM_FUNC_BACKING_STORE_QCAPS_OUTPUT_CTX_INIT_MASK_CQ \
15381 * If this bit is '1' then this context type should be initialized
15382 * with the ctx_kind_initializer at the specified offset.
15384 #define HWRM_FUNC_BACKING_STORE_QCAPS_OUTPUT_CTX_INIT_MASK_VNIC \
15387 * If this bit is '1' then this context type should be initialized
15388 * with the ctx_kind_initializer at the specified offset.
15390 #define HWRM_FUNC_BACKING_STORE_QCAPS_OUTPUT_CTX_INIT_MASK_STAT \
15393 * If this bit is '1' then this context type should be initialized
15394 * with the ctx_kind_initializer at the specified offset.
15396 #define HWRM_FUNC_BACKING_STORE_QCAPS_OUTPUT_CTX_INIT_MASK_MRAV \
15399 * If this bit is '1' then the Tx KTLS context type should be
15400 * initialized with the ctx_kind_initializer at the specified offset.
15402 #define HWRM_FUNC_BACKING_STORE_QCAPS_OUTPUT_CTX_INIT_MASK_TKC \
15405 * If this bit is '1' then the Rx KTLS context type should be
15406 * initialized with the ctx_kind_initializer at the specified offset.
15408 #define HWRM_FUNC_BACKING_STORE_QCAPS_OUTPUT_CTX_INIT_MASK_RKC \
15411 * Specifies the doubleword offset of ctx_kind_initializer for this
15414 uint8_t qp_init_offset;
15416 * Specifies the doubleword offset of ctx_kind_initializer for this
15419 uint8_t srq_init_offset;
15421 * Specifies the doubleword offset of ctx_kind_initializer for this
15424 uint8_t cq_init_offset;
15426 * Specifies the doubleword offset of ctx_kind_initializer for this
15429 uint8_t vnic_init_offset;
15431 * Count of TQM fastpath rings to be used for allocating backing store.
15432 * Backing store configuration must be specified for each TQM ring from
15433 * this count in `backing_store_cfg`.
15434 * Only first 8 TQM FP rings will be advertised with this field.
15436 uint8_t tqm_fp_rings_count;
15438 * Specifies the doubleword offset of ctx_kind_initializer for this
15441 uint8_t stat_init_offset;
15443 * Specifies the doubleword offset of ctx_kind_initializer for this
15446 uint8_t mrav_init_offset;
15448 * Count of TQM extended fastpath rings to be used for allocating
15449 * backing store beyond 8 rings(rings 9,10,11)
15450 * Backing store configuration must be specified for each TQM ring from
15451 * this count in `backing_store_cfg`.
15453 uint8_t tqm_fp_rings_count_ext;
15455 * Specifies the doubleword offset of ctx_kind_initializer for Tx
15456 * KTLS context type.
15458 uint8_t tkc_init_offset;
15460 * Specifies the doubleword offset of ctx_kind_initializer for Rx
15461 * KTLS context type.
15463 uint8_t rkc_init_offset;
15464 /* Tx KTLS context entry size in bytes. */
15465 uint16_t tkc_entry_size;
15466 /* Rx KTLS context entry size in bytes. */
15467 uint16_t rkc_entry_size;
15469 * Maximum number of Tx KTLS context entries supported for this
15472 uint32_t tkc_max_entries;
15474 * Maximum number of Rx KTLS context entries supported for this
15477 uint32_t rkc_max_entries;
15479 * Number of mid-path TQM rings to be used for allocating
15482 uint8_t mp_tqm_rings_count;
15483 /* Reserved for future. */
15486 * This field is used in Output records to indicate that the output
15487 * is completely written to RAM. This field should be read as '1'
15488 * to indicate that the output has been completely written.
15489 * When writing a command completion or response to an internal processor,
15490 * the order of writes has to be such that this field is written last.
15495 /* tqm_fp_ring_cfg (size:128b/16B) */
15496 struct tqm_fp_ring_cfg {
15497 /* TQM ring page size and level. */
15498 uint8_t tqm_ring_pg_size_tqm_ring_lvl;
15499 /* TQM ring PBL indirect levels. */
15500 #define TQM_FP_RING_CFG_TQM_RING_CFG_TQM_RING_LVL_MASK \
15502 #define TQM_FP_RING_CFG_TQM_RING_CFG_TQM_RING_LVL_SFT 0
15503 /* PBL pointer is physical start address. */
15504 #define TQM_FP_RING_CFG_TQM_RING_CFG_TQM_RING_LVL_LVL_0 \
15506 /* PBL pointer points to PTE table. */
15507 #define TQM_FP_RING_CFG_TQM_RING_CFG_TQM_RING_LVL_LVL_1 \
15510 * PBL pointer points to PDE table with each entry pointing to
15513 #define TQM_FP_RING_CFG_TQM_RING_CFG_TQM_RING_LVL_LVL_2 \
15515 #define TQM_FP_RING_CFG_TQM_RING_CFG_TQM_RING_LVL_LAST \
15516 TQM_FP_RING_CFG_TQM_RING_CFG_TQM_RING_LVL_LVL_2
15517 /* TQM ring page size. */
15518 #define TQM_FP_RING_CFG_TQM_RING_CFG_TQM_RING_PG_SIZE_MASK \
15520 #define TQM_FP_RING_CFG_TQM_RING_CFG_TQM_RING_PG_SIZE_SFT 4
15522 #define TQM_FP_RING_CFG_TQM_RING_CFG_TQM_RING_PG_SIZE_PG_4K \
15523 (UINT32_C(0x0) << 4)
15525 #define TQM_FP_RING_CFG_TQM_RING_CFG_TQM_RING_PG_SIZE_PG_8K \
15526 (UINT32_C(0x1) << 4)
15528 #define TQM_FP_RING_CFG_TQM_RING_CFG_TQM_RING_PG_SIZE_PG_64K \
15529 (UINT32_C(0x2) << 4)
15531 #define TQM_FP_RING_CFG_TQM_RING_CFG_TQM_RING_PG_SIZE_PG_2M \
15532 (UINT32_C(0x3) << 4)
15534 #define TQM_FP_RING_CFG_TQM_RING_CFG_TQM_RING_PG_SIZE_PG_8M \
15535 (UINT32_C(0x4) << 4)
15537 #define TQM_FP_RING_CFG_TQM_RING_CFG_TQM_RING_PG_SIZE_PG_1G \
15538 (UINT32_C(0x5) << 4)
15539 #define TQM_FP_RING_CFG_TQM_RING_CFG_TQM_RING_PG_SIZE_LAST \
15540 TQM_FP_RING_CFG_TQM_RING_CFG_TQM_RING_PG_SIZE_PG_1G
15542 /* Number of TQM ring entries. */
15543 uint32_t tqm_ring_num_entries;
15544 /* TQM ring page directory. */
15545 uint64_t tqm_ring_page_dir;
15548 /*******************************
15549 * hwrm_func_backing_store_cfg *
15550 *******************************/
15553 /* hwrm_func_backing_store_cfg_input (size:2688b/336B) */
15554 struct hwrm_func_backing_store_cfg_input {
15555 /* The HWRM command request type. */
15558 * The completion ring to send the completion event on. This should
15559 * be the NQ ID returned from the `nq_alloc` HWRM command.
15561 uint16_t cmpl_ring;
15563 * The sequence ID is used by the driver for tracking multiple
15564 * commands. This ID is treated as opaque data by the firmware and
15565 * the value is returned in the `hwrm_resp_hdr` upon completion.
15569 * The target ID of the command:
15570 * * 0x0-0xFFF8 - The function ID
15571 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
15572 * * 0xFFFD - Reserved for user-space HWRM interface
15575 uint16_t target_id;
15577 * A physical address pointer pointing to a host buffer that the
15578 * command's response data will be written. This can be either a host
15579 * physical address (HPA) or a guest physical address (GPA) and must
15580 * point to a physically contiguous block of memory.
15582 uint64_t resp_addr;
15585 * When set, the firmware only uses on-chip resources and does not
15586 * expect any backing store to be provided by the host driver. This
15587 * mode provides minimal L2 functionality (e.g. limited L2 resources,
15590 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_FLAGS_PREBOOT_MODE \
15593 * When set, the 32b `mrav_num_entries` field is logically divided
15594 * into two 16b fields, `mr_num_entries` and `av_num_entries`.
15596 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_FLAGS_MRAV_RESERVATION_SPLIT \
15600 * This bit must be '1' for the qp fields to be
15603 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_QP \
15606 * This bit must be '1' for the srq fields to be
15609 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_SRQ \
15612 * This bit must be '1' for the cq fields to be
15615 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_CQ \
15618 * This bit must be '1' for the vnic fields to be
15621 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_VNIC \
15624 * This bit must be '1' for the stat fields to be
15627 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_STAT \
15630 * This bit must be '1' for the tqm_sp fields to be
15633 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_TQM_SP \
15636 * This bit must be '1' for the tqm_ring0 fields to be
15639 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_TQM_RING0 \
15642 * This bit must be '1' for the tqm_ring1 fields to be
15645 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_TQM_RING1 \
15648 * This bit must be '1' for the tqm_ring2 fields to be
15651 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_TQM_RING2 \
15654 * This bit must be '1' for the tqm_ring3 fields to be
15657 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_TQM_RING3 \
15660 * This bit must be '1' for the tqm_ring4 fields to be
15663 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_TQM_RING4 \
15666 * This bit must be '1' for the tqm_ring5 fields to be
15669 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_TQM_RING5 \
15672 * This bit must be '1' for the tqm_ring6 fields to be
15675 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_TQM_RING6 \
15678 * This bit must be '1' for the tqm_ring7 fields to be
15681 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_TQM_RING7 \
15684 * This bit must be '1' for the mrav fields to be
15687 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_MRAV \
15690 * This bit must be '1' for the tim fields to be
15693 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_TIM \
15696 * This bit must be '1' for the tqm_ring8 fields to be
15699 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_TQM_RING8 \
15702 * This bit must be '1' for the tqm_ring9 fields to be
15705 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_TQM_RING9 \
15708 * This bit must be '1' for the tqm_ring10 fields to be
15711 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_TQM_RING10 \
15714 * This bit must be '1' for the Tx KTLS context
15715 * fields to be configured.
15717 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_TKC \
15720 * This bit must be '1' for the Rx KTLS context
15721 * fields to be configured.
15723 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_RKC \
15725 /* QPC page size and level. */
15726 uint8_t qpc_pg_size_qpc_lvl;
15727 /* QPC PBL indirect levels. */
15728 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_QPC_LVL_MASK \
15730 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_QPC_LVL_SFT 0
15731 /* PBL pointer is physical start address. */
15732 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_QPC_LVL_LVL_0 \
15734 /* PBL pointer points to PTE table. */
15735 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_QPC_LVL_LVL_1 \
15737 /* PBL pointer points to PDE table with each entry pointing to PTE tables. */
15738 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_QPC_LVL_LVL_2 \
15740 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_QPC_LVL_LAST \
15741 HWRM_FUNC_BACKING_STORE_CFG_INPUT_QPC_LVL_LVL_2
15742 /* QPC page size. */
15743 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_QPC_PG_SIZE_MASK \
15745 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_QPC_PG_SIZE_SFT 4
15747 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_QPC_PG_SIZE_PG_4K \
15748 (UINT32_C(0x0) << 4)
15750 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_QPC_PG_SIZE_PG_8K \
15751 (UINT32_C(0x1) << 4)
15753 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_QPC_PG_SIZE_PG_64K \
15754 (UINT32_C(0x2) << 4)
15756 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_QPC_PG_SIZE_PG_2M \
15757 (UINT32_C(0x3) << 4)
15759 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_QPC_PG_SIZE_PG_8M \
15760 (UINT32_C(0x4) << 4)
15762 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_QPC_PG_SIZE_PG_1G \
15763 (UINT32_C(0x5) << 4)
15764 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_QPC_PG_SIZE_LAST \
15765 HWRM_FUNC_BACKING_STORE_CFG_INPUT_QPC_PG_SIZE_PG_1G
15766 /* SRQ page size and level. */
15767 uint8_t srq_pg_size_srq_lvl;
15768 /* SRQ PBL indirect levels. */
15769 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_SRQ_LVL_MASK \
15771 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_SRQ_LVL_SFT 0
15772 /* PBL pointer is physical start address. */
15773 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_SRQ_LVL_LVL_0 \
15775 /* PBL pointer points to PTE table. */
15776 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_SRQ_LVL_LVL_1 \
15778 /* PBL pointer points to PDE table with each entry pointing to PTE tables. */
15779 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_SRQ_LVL_LVL_2 \
15781 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_SRQ_LVL_LAST \
15782 HWRM_FUNC_BACKING_STORE_CFG_INPUT_SRQ_LVL_LVL_2
15783 /* SRQ page size. */
15784 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_SRQ_PG_SIZE_MASK \
15786 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_SRQ_PG_SIZE_SFT 4
15788 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_SRQ_PG_SIZE_PG_4K \
15789 (UINT32_C(0x0) << 4)
15791 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_SRQ_PG_SIZE_PG_8K \
15792 (UINT32_C(0x1) << 4)
15794 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_SRQ_PG_SIZE_PG_64K \
15795 (UINT32_C(0x2) << 4)
15797 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_SRQ_PG_SIZE_PG_2M \
15798 (UINT32_C(0x3) << 4)
15800 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_SRQ_PG_SIZE_PG_8M \
15801 (UINT32_C(0x4) << 4)
15803 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_SRQ_PG_SIZE_PG_1G \
15804 (UINT32_C(0x5) << 4)
15805 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_SRQ_PG_SIZE_LAST \
15806 HWRM_FUNC_BACKING_STORE_CFG_INPUT_SRQ_PG_SIZE_PG_1G
15807 /* CQ page size and level. */
15808 uint8_t cq_pg_size_cq_lvl;
15809 /* CQ PBL indirect levels. */
15810 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_CQ_LVL_MASK \
15812 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_CQ_LVL_SFT 0
15813 /* PBL pointer is physical start address. */
15814 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_CQ_LVL_LVL_0 \
15816 /* PBL pointer points to PTE table. */
15817 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_CQ_LVL_LVL_1 \
15819 /* PBL pointer points to PDE table with each entry pointing to PTE tables. */
15820 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_CQ_LVL_LVL_2 \
15822 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_CQ_LVL_LAST \
15823 HWRM_FUNC_BACKING_STORE_CFG_INPUT_CQ_LVL_LVL_2
15824 /* CQ page size. */
15825 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_CQ_PG_SIZE_MASK \
15827 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_CQ_PG_SIZE_SFT 4
15829 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_CQ_PG_SIZE_PG_4K \
15830 (UINT32_C(0x0) << 4)
15832 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_CQ_PG_SIZE_PG_8K \
15833 (UINT32_C(0x1) << 4)
15835 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_CQ_PG_SIZE_PG_64K \
15836 (UINT32_C(0x2) << 4)
15838 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_CQ_PG_SIZE_PG_2M \
15839 (UINT32_C(0x3) << 4)
15841 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_CQ_PG_SIZE_PG_8M \
15842 (UINT32_C(0x4) << 4)
15844 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_CQ_PG_SIZE_PG_1G \
15845 (UINT32_C(0x5) << 4)
15846 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_CQ_PG_SIZE_LAST \
15847 HWRM_FUNC_BACKING_STORE_CFG_INPUT_CQ_PG_SIZE_PG_1G
15848 /* VNIC page size and level. */
15849 uint8_t vnic_pg_size_vnic_lvl;
15850 /* VNIC PBL indirect levels. */
15851 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_VNIC_LVL_MASK \
15853 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_VNIC_LVL_SFT 0
15854 /* PBL pointer is physical start address. */
15855 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_VNIC_LVL_LVL_0 \
15857 /* PBL pointer points to PTE table. */
15858 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_VNIC_LVL_LVL_1 \
15860 /* PBL pointer points to PDE table with each entry pointing to PTE tables. */
15861 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_VNIC_LVL_LVL_2 \
15863 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_VNIC_LVL_LAST \
15864 HWRM_FUNC_BACKING_STORE_CFG_INPUT_VNIC_LVL_LVL_2
15865 /* VNIC page size. */
15866 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_VNIC_PG_SIZE_MASK \
15868 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_VNIC_PG_SIZE_SFT 4
15870 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_VNIC_PG_SIZE_PG_4K \
15871 (UINT32_C(0x0) << 4)
15873 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_VNIC_PG_SIZE_PG_8K \
15874 (UINT32_C(0x1) << 4)
15876 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_VNIC_PG_SIZE_PG_64K \
15877 (UINT32_C(0x2) << 4)
15879 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_VNIC_PG_SIZE_PG_2M \
15880 (UINT32_C(0x3) << 4)
15882 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_VNIC_PG_SIZE_PG_8M \
15883 (UINT32_C(0x4) << 4)
15885 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_VNIC_PG_SIZE_PG_1G \
15886 (UINT32_C(0x5) << 4)
15887 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_VNIC_PG_SIZE_LAST \
15888 HWRM_FUNC_BACKING_STORE_CFG_INPUT_VNIC_PG_SIZE_PG_1G
15889 /* Stat page size and level. */
15890 uint8_t stat_pg_size_stat_lvl;
15891 /* Stat PBL indirect levels. */
15892 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_STAT_LVL_MASK \
15894 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_STAT_LVL_SFT 0
15895 /* PBL pointer is physical start address. */
15896 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_STAT_LVL_LVL_0 \
15898 /* PBL pointer points to PTE table. */
15899 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_STAT_LVL_LVL_1 \
15901 /* PBL pointer points to PDE table with each entry pointing to PTE tables. */
15902 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_STAT_LVL_LVL_2 \
15904 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_STAT_LVL_LAST \
15905 HWRM_FUNC_BACKING_STORE_CFG_INPUT_STAT_LVL_LVL_2
15906 /* Stat page size. */
15907 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_STAT_PG_SIZE_MASK \
15909 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_STAT_PG_SIZE_SFT 4
15911 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_STAT_PG_SIZE_PG_4K \
15912 (UINT32_C(0x0) << 4)
15914 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_STAT_PG_SIZE_PG_8K \
15915 (UINT32_C(0x1) << 4)
15917 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_STAT_PG_SIZE_PG_64K \
15918 (UINT32_C(0x2) << 4)
15920 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_STAT_PG_SIZE_PG_2M \
15921 (UINT32_C(0x3) << 4)
15923 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_STAT_PG_SIZE_PG_8M \
15924 (UINT32_C(0x4) << 4)
15926 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_STAT_PG_SIZE_PG_1G \
15927 (UINT32_C(0x5) << 4)
15928 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_STAT_PG_SIZE_LAST \
15929 HWRM_FUNC_BACKING_STORE_CFG_INPUT_STAT_PG_SIZE_PG_1G
15930 /* TQM slow path page size and level. */
15931 uint8_t tqm_sp_pg_size_tqm_sp_lvl;
15932 /* TQM slow path PBL indirect levels. */
15933 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_SP_LVL_MASK \
15935 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_SP_LVL_SFT 0
15936 /* PBL pointer is physical start address. */
15937 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_SP_LVL_LVL_0 \
15939 /* PBL pointer points to PTE table. */
15940 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_SP_LVL_LVL_1 \
15942 /* PBL pointer points to PDE table with each entry pointing to PTE tables. */
15943 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_SP_LVL_LVL_2 \
15945 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_SP_LVL_LAST \
15946 HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_SP_LVL_LVL_2
15947 /* TQM slow path page size. */
15948 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_SP_PG_SIZE_MASK \
15950 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_SP_PG_SIZE_SFT 4
15952 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_SP_PG_SIZE_PG_4K \
15953 (UINT32_C(0x0) << 4)
15955 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_SP_PG_SIZE_PG_8K \
15956 (UINT32_C(0x1) << 4)
15958 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_SP_PG_SIZE_PG_64K \
15959 (UINT32_C(0x2) << 4)
15961 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_SP_PG_SIZE_PG_2M \
15962 (UINT32_C(0x3) << 4)
15964 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_SP_PG_SIZE_PG_8M \
15965 (UINT32_C(0x4) << 4)
15967 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_SP_PG_SIZE_PG_1G \
15968 (UINT32_C(0x5) << 4)
15969 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_SP_PG_SIZE_LAST \
15970 HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_SP_PG_SIZE_PG_1G
15971 /* TQM ring 0 page size and level. */
15972 uint8_t tqm_ring0_pg_size_tqm_ring0_lvl;
15973 /* TQM ring 0 PBL indirect levels. */
15974 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING0_LVL_MASK \
15976 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING0_LVL_SFT 0
15977 /* PBL pointer is physical start address. */
15978 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING0_LVL_LVL_0 \
15980 /* PBL pointer points to PTE table. */
15981 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING0_LVL_LVL_1 \
15983 /* PBL pointer points to PDE table with each entry pointing to PTE tables. */
15984 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING0_LVL_LVL_2 \
15986 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING0_LVL_LAST \
15987 HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING0_LVL_LVL_2
15988 /* TQM ring 0 page size. */
15989 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING0_PG_SIZE_MASK \
15991 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING0_PG_SIZE_SFT 4
15993 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING0_PG_SIZE_PG_4K \
15994 (UINT32_C(0x0) << 4)
15996 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING0_PG_SIZE_PG_8K \
15997 (UINT32_C(0x1) << 4)
15999 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING0_PG_SIZE_PG_64K \
16000 (UINT32_C(0x2) << 4)
16002 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING0_PG_SIZE_PG_2M \
16003 (UINT32_C(0x3) << 4)
16005 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING0_PG_SIZE_PG_8M \
16006 (UINT32_C(0x4) << 4)
16008 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING0_PG_SIZE_PG_1G \
16009 (UINT32_C(0x5) << 4)
16010 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING0_PG_SIZE_LAST \
16011 HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING0_PG_SIZE_PG_1G
16012 /* TQM ring 1 page size and level. */
16013 uint8_t tqm_ring1_pg_size_tqm_ring1_lvl;
16014 /* TQM ring 1 PBL indirect levels. */
16015 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING1_LVL_MASK \
16017 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING1_LVL_SFT 0
16018 /* PBL pointer is physical start address. */
16019 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING1_LVL_LVL_0 \
16021 /* PBL pointer points to PTE table. */
16022 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING1_LVL_LVL_1 \
16024 /* PBL pointer points to PDE table with each entry pointing to PTE tables. */
16025 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING1_LVL_LVL_2 \
16027 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING1_LVL_LAST \
16028 HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING1_LVL_LVL_2
16029 /* TQM ring 1 page size. */
16030 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING1_PG_SIZE_MASK \
16032 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING1_PG_SIZE_SFT 4
16034 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING1_PG_SIZE_PG_4K \
16035 (UINT32_C(0x0) << 4)
16037 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING1_PG_SIZE_PG_8K \
16038 (UINT32_C(0x1) << 4)
16040 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING1_PG_SIZE_PG_64K \
16041 (UINT32_C(0x2) << 4)
16043 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING1_PG_SIZE_PG_2M \
16044 (UINT32_C(0x3) << 4)
16046 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING1_PG_SIZE_PG_8M \
16047 (UINT32_C(0x4) << 4)
16049 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING1_PG_SIZE_PG_1G \
16050 (UINT32_C(0x5) << 4)
16051 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING1_PG_SIZE_LAST \
16052 HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING1_PG_SIZE_PG_1G
16053 /* TQM ring 2 page size and level. */
16054 uint8_t tqm_ring2_pg_size_tqm_ring2_lvl;
16055 /* TQM ring 2 PBL indirect levels. */
16056 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING2_LVL_MASK \
16058 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING2_LVL_SFT 0
16059 /* PBL pointer is physical start address. */
16060 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING2_LVL_LVL_0 \
16062 /* PBL pointer points to PTE table. */
16063 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING2_LVL_LVL_1 \
16065 /* PBL pointer points to PDE table with each entry pointing to PTE tables. */
16066 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING2_LVL_LVL_2 \
16068 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING2_LVL_LAST \
16069 HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING2_LVL_LVL_2
16070 /* TQM ring 2 page size. */
16071 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING2_PG_SIZE_MASK \
16073 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING2_PG_SIZE_SFT 4
16075 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING2_PG_SIZE_PG_4K \
16076 (UINT32_C(0x0) << 4)
16078 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING2_PG_SIZE_PG_8K \
16079 (UINT32_C(0x1) << 4)
16081 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING2_PG_SIZE_PG_64K \
16082 (UINT32_C(0x2) << 4)
16084 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING2_PG_SIZE_PG_2M \
16085 (UINT32_C(0x3) << 4)
16087 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING2_PG_SIZE_PG_8M \
16088 (UINT32_C(0x4) << 4)
16090 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING2_PG_SIZE_PG_1G \
16091 (UINT32_C(0x5) << 4)
16092 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING2_PG_SIZE_LAST \
16093 HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING2_PG_SIZE_PG_1G
16094 /* TQM ring 3 page size and level. */
16095 uint8_t tqm_ring3_pg_size_tqm_ring3_lvl;
16096 /* TQM ring 3 PBL indirect levels. */
16097 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING3_LVL_MASK \
16099 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING3_LVL_SFT 0
16100 /* PBL pointer is physical start address. */
16101 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING3_LVL_LVL_0 \
16103 /* PBL pointer points to PTE table. */
16104 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING3_LVL_LVL_1 \
16106 /* PBL pointer points to PDE table with each entry pointing to PTE tables. */
16107 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING3_LVL_LVL_2 \
16109 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING3_LVL_LAST \
16110 HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING3_LVL_LVL_2
16111 /* TQM ring 3 page size. */
16112 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING3_PG_SIZE_MASK \
16114 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING3_PG_SIZE_SFT 4
16116 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING3_PG_SIZE_PG_4K \
16117 (UINT32_C(0x0) << 4)
16119 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING3_PG_SIZE_PG_8K \
16120 (UINT32_C(0x1) << 4)
16122 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING3_PG_SIZE_PG_64K \
16123 (UINT32_C(0x2) << 4)
16125 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING3_PG_SIZE_PG_2M \
16126 (UINT32_C(0x3) << 4)
16128 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING3_PG_SIZE_PG_8M \
16129 (UINT32_C(0x4) << 4)
16131 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING3_PG_SIZE_PG_1G \
16132 (UINT32_C(0x5) << 4)
16133 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING3_PG_SIZE_LAST \
16134 HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING3_PG_SIZE_PG_1G
16135 /* TQM ring 4 page size and level. */
16136 uint8_t tqm_ring4_pg_size_tqm_ring4_lvl;
16137 /* TQM ring 4 PBL indirect levels. */
16138 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING4_LVL_MASK \
16140 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING4_LVL_SFT 0
16141 /* PBL pointer is physical start address. */
16142 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING4_LVL_LVL_0 \
16144 /* PBL pointer points to PTE table. */
16145 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING4_LVL_LVL_1 \
16147 /* PBL pointer points to PDE table with each entry pointing to PTE tables. */
16148 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING4_LVL_LVL_2 \
16150 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING4_LVL_LAST \
16151 HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING4_LVL_LVL_2
16152 /* TQM ring 4 page size. */
16153 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING4_PG_SIZE_MASK \
16155 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING4_PG_SIZE_SFT 4
16157 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING4_PG_SIZE_PG_4K \
16158 (UINT32_C(0x0) << 4)
16160 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING4_PG_SIZE_PG_8K \
16161 (UINT32_C(0x1) << 4)
16163 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING4_PG_SIZE_PG_64K \
16164 (UINT32_C(0x2) << 4)
16166 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING4_PG_SIZE_PG_2M \
16167 (UINT32_C(0x3) << 4)
16169 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING4_PG_SIZE_PG_8M \
16170 (UINT32_C(0x4) << 4)
16172 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING4_PG_SIZE_PG_1G \
16173 (UINT32_C(0x5) << 4)
16174 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING4_PG_SIZE_LAST \
16175 HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING4_PG_SIZE_PG_1G
16176 /* TQM ring 5 page size and level. */
16177 uint8_t tqm_ring5_pg_size_tqm_ring5_lvl;
16178 /* TQM ring 5 PBL indirect levels. */
16179 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING5_LVL_MASK \
16181 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING5_LVL_SFT 0
16182 /* PBL pointer is physical start address. */
16183 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING5_LVL_LVL_0 \
16185 /* PBL pointer points to PTE table. */
16186 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING5_LVL_LVL_1 \
16188 /* PBL pointer points to PDE table with each entry pointing to PTE tables. */
16189 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING5_LVL_LVL_2 \
16191 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING5_LVL_LAST \
16192 HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING5_LVL_LVL_2
16193 /* TQM ring 5 page size. */
16194 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING5_PG_SIZE_MASK \
16196 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING5_PG_SIZE_SFT 4
16198 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING5_PG_SIZE_PG_4K \
16199 (UINT32_C(0x0) << 4)
16201 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING5_PG_SIZE_PG_8K \
16202 (UINT32_C(0x1) << 4)
16204 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING5_PG_SIZE_PG_64K \
16205 (UINT32_C(0x2) << 4)
16207 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING5_PG_SIZE_PG_2M \
16208 (UINT32_C(0x3) << 4)
16210 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING5_PG_SIZE_PG_8M \
16211 (UINT32_C(0x4) << 4)
16213 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING5_PG_SIZE_PG_1G \
16214 (UINT32_C(0x5) << 4)
16215 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING5_PG_SIZE_LAST \
16216 HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING5_PG_SIZE_PG_1G
16217 /* TQM ring 6 page size and level. */
16218 uint8_t tqm_ring6_pg_size_tqm_ring6_lvl;
16219 /* TQM ring 6 PBL indirect levels. */
16220 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING6_LVL_MASK \
16222 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING6_LVL_SFT 0
16223 /* PBL pointer is physical start address. */
16224 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING6_LVL_LVL_0 \
16226 /* PBL pointer points to PTE table. */
16227 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING6_LVL_LVL_1 \
16229 /* PBL pointer points to PDE table with each entry pointing to PTE tables. */
16230 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING6_LVL_LVL_2 \
16232 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING6_LVL_LAST \
16233 HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING6_LVL_LVL_2
16234 /* TQM ring 6 page size. */
16235 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING6_PG_SIZE_MASK \
16237 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING6_PG_SIZE_SFT 4
16239 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING6_PG_SIZE_PG_4K \
16240 (UINT32_C(0x0) << 4)
16242 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING6_PG_SIZE_PG_8K \
16243 (UINT32_C(0x1) << 4)
16245 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING6_PG_SIZE_PG_64K \
16246 (UINT32_C(0x2) << 4)
16248 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING6_PG_SIZE_PG_2M \
16249 (UINT32_C(0x3) << 4)
16251 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING6_PG_SIZE_PG_8M \
16252 (UINT32_C(0x4) << 4)
16254 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING6_PG_SIZE_PG_1G \
16255 (UINT32_C(0x5) << 4)
16256 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING6_PG_SIZE_LAST \
16257 HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING6_PG_SIZE_PG_1G
16258 /* TQM ring 7 page size and level. */
16259 uint8_t tqm_ring7_pg_size_tqm_ring7_lvl;
16260 /* TQM ring 7 PBL indirect levels. */
16261 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING7_LVL_MASK \
16263 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING7_LVL_SFT 0
16264 /* PBL pointer is physical start address. */
16265 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING7_LVL_LVL_0 \
16267 /* PBL pointer points to PTE table. */
16268 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING7_LVL_LVL_1 \
16270 /* PBL pointer points to PDE table with each entry pointing to PTE tables. */
16271 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING7_LVL_LVL_2 \
16273 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING7_LVL_LAST \
16274 HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING7_LVL_LVL_2
16275 /* TQM ring 7 page size. */
16276 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING7_PG_SIZE_MASK \
16278 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING7_PG_SIZE_SFT 4
16280 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING7_PG_SIZE_PG_4K \
16281 (UINT32_C(0x0) << 4)
16283 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING7_PG_SIZE_PG_8K \
16284 (UINT32_C(0x1) << 4)
16286 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING7_PG_SIZE_PG_64K \
16287 (UINT32_C(0x2) << 4)
16289 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING7_PG_SIZE_PG_2M \
16290 (UINT32_C(0x3) << 4)
16292 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING7_PG_SIZE_PG_8M \
16293 (UINT32_C(0x4) << 4)
16295 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING7_PG_SIZE_PG_1G \
16296 (UINT32_C(0x5) << 4)
16297 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING7_PG_SIZE_LAST \
16298 HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING7_PG_SIZE_PG_1G
16299 /* MR/AV page size and level. */
16300 uint8_t mrav_pg_size_mrav_lvl;
16301 /* MR/AV PBL indirect levels. */
16302 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_MRAV_LVL_MASK \
16304 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_MRAV_LVL_SFT 0
16305 /* PBL pointer is physical start address. */
16306 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_MRAV_LVL_LVL_0 \
16308 /* PBL pointer points to PTE table. */
16309 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_MRAV_LVL_LVL_1 \
16311 /* PBL pointer points to PDE table with each entry pointing to PTE tables. */
16312 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_MRAV_LVL_LVL_2 \
16314 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_MRAV_LVL_LAST \
16315 HWRM_FUNC_BACKING_STORE_CFG_INPUT_MRAV_LVL_LVL_2
16316 /* MR/AV page size. */
16317 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_MRAV_PG_SIZE_MASK \
16319 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_MRAV_PG_SIZE_SFT 4
16321 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_MRAV_PG_SIZE_PG_4K \
16322 (UINT32_C(0x0) << 4)
16324 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_MRAV_PG_SIZE_PG_8K \
16325 (UINT32_C(0x1) << 4)
16327 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_MRAV_PG_SIZE_PG_64K \
16328 (UINT32_C(0x2) << 4)
16330 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_MRAV_PG_SIZE_PG_2M \
16331 (UINT32_C(0x3) << 4)
16333 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_MRAV_PG_SIZE_PG_8M \
16334 (UINT32_C(0x4) << 4)
16336 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_MRAV_PG_SIZE_PG_1G \
16337 (UINT32_C(0x5) << 4)
16338 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_MRAV_PG_SIZE_LAST \
16339 HWRM_FUNC_BACKING_STORE_CFG_INPUT_MRAV_PG_SIZE_PG_1G
16340 /* Timer page size and level. */
16341 uint8_t tim_pg_size_tim_lvl;
16342 /* Timer PBL indirect levels. */
16343 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TIM_LVL_MASK \
16345 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TIM_LVL_SFT 0
16346 /* PBL pointer is physical start address. */
16347 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TIM_LVL_LVL_0 \
16349 /* PBL pointer points to PTE table. */
16350 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TIM_LVL_LVL_1 \
16352 /* PBL pointer points to PDE table with each entry pointing to PTE tables. */
16353 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TIM_LVL_LVL_2 \
16355 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TIM_LVL_LAST \
16356 HWRM_FUNC_BACKING_STORE_CFG_INPUT_TIM_LVL_LVL_2
16357 /* Timer page size. */
16358 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TIM_PG_SIZE_MASK \
16360 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TIM_PG_SIZE_SFT 4
16362 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TIM_PG_SIZE_PG_4K \
16363 (UINT32_C(0x0) << 4)
16365 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TIM_PG_SIZE_PG_8K \
16366 (UINT32_C(0x1) << 4)
16368 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TIM_PG_SIZE_PG_64K \
16369 (UINT32_C(0x2) << 4)
16371 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TIM_PG_SIZE_PG_2M \
16372 (UINT32_C(0x3) << 4)
16374 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TIM_PG_SIZE_PG_8M \
16375 (UINT32_C(0x4) << 4)
16377 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TIM_PG_SIZE_PG_1G \
16378 (UINT32_C(0x5) << 4)
16379 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TIM_PG_SIZE_LAST \
16380 HWRM_FUNC_BACKING_STORE_CFG_INPUT_TIM_PG_SIZE_PG_1G
16381 /* QP page directory. */
16382 uint64_t qpc_page_dir;
16383 /* SRQ page directory. */
16384 uint64_t srq_page_dir;
16385 /* CQ page directory. */
16386 uint64_t cq_page_dir;
16387 /* VNIC page directory. */
16388 uint64_t vnic_page_dir;
16389 /* Stat page directory. */
16390 uint64_t stat_page_dir;
16391 /* TQM slowpath page directory. */
16392 uint64_t tqm_sp_page_dir;
16393 /* TQM ring 0 page directory. */
16394 uint64_t tqm_ring0_page_dir;
16395 /* TQM ring 1 page directory. */
16396 uint64_t tqm_ring1_page_dir;
16397 /* TQM ring 2 page directory. */
16398 uint64_t tqm_ring2_page_dir;
16399 /* TQM ring 3 page directory. */
16400 uint64_t tqm_ring3_page_dir;
16401 /* TQM ring 4 page directory. */
16402 uint64_t tqm_ring4_page_dir;
16403 /* TQM ring 5 page directory. */
16404 uint64_t tqm_ring5_page_dir;
16405 /* TQM ring 6 page directory. */
16406 uint64_t tqm_ring6_page_dir;
16407 /* TQM ring 7 page directory. */
16408 uint64_t tqm_ring7_page_dir;
16409 /* MR/AV page directory. */
16410 uint64_t mrav_page_dir;
16411 /* Timer page directory. */
16412 uint64_t tim_page_dir;
16413 /* Number of QPs. */
16414 uint32_t qp_num_entries;
16415 /* Number of SRQs. */
16416 uint32_t srq_num_entries;
16417 /* Number of CQs. */
16418 uint32_t cq_num_entries;
16419 /* Number of Stats. */
16420 uint32_t stat_num_entries;
16422 * Number of TQM slowpath entries.
16424 * TQM slowpath rings should be sized as follows:
16426 * num_entries = num_vnics + num_l2_tx_rings + 2 * num_roce_qps + tqm_min_size
16429 * num_vnics is the number of VNICs allocated in the VNIC backing store
16430 * num_l2_tx_rings is the number of L2 rings in the QP backing store
16431 * num_roce_qps is the number of RoCE QPs in the QP backing store
16432 * tqm_min_size is tqm_min_entries_per_ring reported by
16433 * HWRM_FUNC_BACKING_STORE_QCAPS
16435 * Note that TQM ring sizes cannot be extended while the system is
16436 * operational. If a PF driver needs to extend a TQM ring, it needs
16437 * to reset the function (e.g. HWRM_FUNC_RESET) and then reallocate
16438 * the backing store.
16440 uint32_t tqm_sp_num_entries;
16442 * Number of TQM ring 0 entries.
16444 * TQM fastpath rings should be sized large enough to accommodate the
16445 * maximum number of QPs (either L2 or RoCE, or both if shared)
16446 * that can be enqueued to the TQM ring.
16448 * Note that TQM ring sizes cannot be extended while the system is
16449 * operational. If a PF driver needs to extend a TQM ring, it needs
16450 * to reset the function (e.g. HWRM_FUNC_RESET) and then reallocate
16451 * the backing store.
16453 uint32_t tqm_ring0_num_entries;
16455 * Number of TQM ring 1 entries.
16457 * TQM fastpath rings should be sized large enough to accommodate the
16458 * maximum number of QPs (either L2 or RoCE, or both if shared)
16459 * that can be enqueued to the TQM ring.
16461 * Note that TQM ring sizes cannot be extended while the system is
16462 * operational. If a PF driver needs to extend a TQM ring, it needs
16463 * to reset the function (e.g. HWRM_FUNC_RESET) and then reallocate
16464 * the backing store.
16466 uint32_t tqm_ring1_num_entries;
16468 * Number of TQM ring 2 entries.
16470 * TQM fastpath rings should be sized large enough to accommodate the
16471 * maximum number of QPs (either L2 or RoCE, or both if shared)
16472 * that can be enqueued to the TQM ring.
16474 * Note that TQM ring sizes cannot be extended while the system is
16475 * operational. If a PF driver needs to extend a TQM ring, it needs
16476 * to reset the function (e.g. HWRM_FUNC_RESET) and then reallocate
16477 * the backing store.
16479 uint32_t tqm_ring2_num_entries;
16481 * Number of TQM ring 3 entries.
16483 * TQM fastpath rings should be sized large enough to accommodate the
16484 * maximum number of QPs (either L2 or RoCE, or both if shared)
16485 * that can be enqueued to the TQM ring.
16487 * Note that TQM ring sizes cannot be extended while the system is
16488 * operational. If a PF driver needs to extend a TQM ring, it needs
16489 * to reset the function (e.g. HWRM_FUNC_RESET) and then reallocate
16490 * the backing store.
16492 uint32_t tqm_ring3_num_entries;
16494 * Number of TQM ring 4 entries.
16496 * TQM fastpath rings should be sized large enough to accommodate the
16497 * maximum number of QPs (either L2 or RoCE, or both if shared)
16498 * that can be enqueued to the TQM ring.
16500 * Note that TQM ring sizes cannot be extended while the system is
16501 * operational. If a PF driver needs to extend a TQM ring, it needs
16502 * to reset the function (e.g. HWRM_FUNC_RESET) and then reallocate
16503 * the backing store.
16505 uint32_t tqm_ring4_num_entries;
16507 * Number of TQM ring 5 entries.
16509 * TQM fastpath rings should be sized large enough to accommodate the
16510 * maximum number of QPs (either L2 or RoCE, or both if shared)
16511 * that can be enqueued to the TQM ring.
16513 * Note that TQM ring sizes cannot be extended while the system is
16514 * operational. If a PF driver needs to extend a TQM ring, it needs
16515 * to reset the function (e.g. HWRM_FUNC_RESET) and then reallocate
16516 * the backing store.
16518 uint32_t tqm_ring5_num_entries;
16520 * Number of TQM ring 6 entries.
16522 * TQM fastpath rings should be sized large enough to accommodate the
16523 * maximum number of QPs (either L2 or RoCE, or both if shared)
16524 * that can be enqueued to the TQM ring.
16526 * Note that TQM ring sizes cannot be extended while the system is
16527 * operational. If a PF driver needs to extend a TQM ring, it needs
16528 * to reset the function (e.g. HWRM_FUNC_RESET) and then reallocate
16529 * the backing store.
16531 uint32_t tqm_ring6_num_entries;
16533 * Number of TQM ring 7 entries.
16535 * TQM fastpath rings should be sized large enough to accommodate the
16536 * maximum number of QPs (either L2 or RoCE, or both if shared)
16537 * that can be enqueued to the TQM ring.
16539 * Note that TQM ring sizes cannot be extended while the system is
16540 * operational. If a PF driver needs to extend a TQM ring, it needs
16541 * to reset the function (e.g. HWRM_FUNC_RESET) and then reallocate
16542 * the backing store.
16544 uint32_t tqm_ring7_num_entries;
16546 * If the MR/AV split reservation flag is not set, then this field
16547 * represents the total number of MR plus AV entries. For versions
16548 * of firmware that support the split reservation, when it is not
16549 * specified half of the entries will be reserved for MRs and the
16550 * other half for AVs.
16552 * If the MR/AV split reservation flag is set, then this
16553 * field is logically divided into two 16b fields. Bits `[31:16]`
16554 * represents the `mr_num_entries` and bits `[15:0]` represents
16555 * `av_num_entries`. The granularity of these values is defined by
16556 * the `mrav_num_entries_unit` field returned by the
16557 * `backing_store_qcaps` command.
16559 uint32_t mrav_num_entries;
16560 /* Number of Timer entries. */
16561 uint32_t tim_num_entries;
16562 /* Number of entries to reserve for QP1 */
16563 uint16_t qp_num_qp1_entries;
16564 /* Number of entries to reserve for L2 */
16565 uint16_t qp_num_l2_entries;
16566 /* Number of bytes that have been allocated for each context entry. */
16567 uint16_t qp_entry_size;
16568 /* Number of entries to reserve for L2 */
16569 uint16_t srq_num_l2_entries;
16570 /* Number of bytes that have been allocated for each context entry. */
16571 uint16_t srq_entry_size;
16572 /* Number of entries to reserve for L2 */
16573 uint16_t cq_num_l2_entries;
16574 /* Number of bytes that have been allocated for each context entry. */
16575 uint16_t cq_entry_size;
16576 /* Number of entries to reserve for VNIC entries */
16577 uint16_t vnic_num_vnic_entries;
16578 /* Number of entries to reserve for Ring table entries */
16579 uint16_t vnic_num_ring_table_entries;
16580 /* Number of bytes that have been allocated for each context entry. */
16581 uint16_t vnic_entry_size;
16582 /* Number of bytes that have been allocated for each context entry. */
16583 uint16_t stat_entry_size;
16584 /* Number of bytes that have been allocated for each context entry. */
16585 uint16_t tqm_entry_size;
16586 /* Number of bytes that have been allocated for each context entry. */
16587 uint16_t mrav_entry_size;
16588 /* Number of bytes that have been allocated for each context entry. */
16589 uint16_t tim_entry_size;
16590 /* TQM ring page size and level. */
16591 uint8_t tqm_ring8_pg_size_tqm_ring_lvl;
16592 /* TQM ring PBL indirect levels. */
16593 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_RING8_TQM_RING_LVL_MASK \
16595 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_RING8_TQM_RING_LVL_SFT \
16597 /* PBL pointer is physical start address. */
16598 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_RING8_TQM_RING_LVL_LVL_0 \
16600 /* PBL pointer points to PTE table. */
16601 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_RING8_TQM_RING_LVL_LVL_1 \
16604 * PBL pointer points to PDE table with each entry pointing to
16607 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_RING8_TQM_RING_LVL_LVL_2 \
16609 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_RING8_TQM_RING_LVL_LAST \
16610 HWRM_FUNC_BACKING_STORE_CFG_INPUT_RING8_TQM_RING_LVL_LVL_2
16611 /* TQM ring page size. */
16612 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_RING8_TQM_RING_PG_SIZE_MASK \
16614 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_RING8_TQM_RING_PG_SIZE_SFT \
16617 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_RING8_TQM_RING_PG_SIZE_PG_4K \
16618 (UINT32_C(0x0) << 4)
16620 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_RING8_TQM_RING_PG_SIZE_PG_8K \
16621 (UINT32_C(0x1) << 4)
16623 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_RING8_TQM_RING_PG_SIZE_PG_64K \
16624 (UINT32_C(0x2) << 4)
16626 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_RING8_TQM_RING_PG_SIZE_PG_2M \
16627 (UINT32_C(0x3) << 4)
16629 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_RING8_TQM_RING_PG_SIZE_PG_8M \
16630 (UINT32_C(0x4) << 4)
16632 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_RING8_TQM_RING_PG_SIZE_PG_1G \
16633 (UINT32_C(0x5) << 4)
16634 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_RING8_TQM_RING_PG_SIZE_LAST \
16635 HWRM_FUNC_BACKING_STORE_CFG_INPUT_RING8_TQM_RING_PG_SIZE_PG_1G
16636 uint8_t ring8_unused[3];
16637 /* Number of TQM ring entries. */
16638 uint32_t tqm_ring8_num_entries;
16639 /* TQM ring page directory. */
16640 uint64_t tqm_ring8_page_dir;
16641 /* TQM ring page size and level. */
16642 uint8_t tqm_ring9_pg_size_tqm_ring_lvl;
16643 /* TQM ring PBL indirect levels. */
16644 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_RING9_TQM_RING_LVL_MASK \
16646 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_RING9_TQM_RING_LVL_SFT \
16648 /* PBL pointer is physical start address. */
16649 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_RING9_TQM_RING_LVL_LVL_0 \
16651 /* PBL pointer points to PTE table. */
16652 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_RING9_TQM_RING_LVL_LVL_1 \
16655 * PBL pointer points to PDE table with each entry pointing to
16658 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_RING9_TQM_RING_LVL_LVL_2 \
16660 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_RING9_TQM_RING_LVL_LAST \
16661 HWRM_FUNC_BACKING_STORE_CFG_INPUT_RING9_TQM_RING_LVL_LVL_2
16662 /* TQM ring page size. */
16663 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_RING9_TQM_RING_PG_SIZE_MASK \
16665 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_RING9_TQM_RING_PG_SIZE_SFT \
16668 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_RING9_TQM_RING_PG_SIZE_PG_4K \
16669 (UINT32_C(0x0) << 4)
16671 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_RING9_TQM_RING_PG_SIZE_PG_8K \
16672 (UINT32_C(0x1) << 4)
16674 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_RING9_TQM_RING_PG_SIZE_PG_64K \
16675 (UINT32_C(0x2) << 4)
16677 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_RING9_TQM_RING_PG_SIZE_PG_2M \
16678 (UINT32_C(0x3) << 4)
16680 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_RING9_TQM_RING_PG_SIZE_PG_8M \
16681 (UINT32_C(0x4) << 4)
16683 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_RING9_TQM_RING_PG_SIZE_PG_1G \
16684 (UINT32_C(0x5) << 4)
16685 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_RING9_TQM_RING_PG_SIZE_LAST \
16686 HWRM_FUNC_BACKING_STORE_CFG_INPUT_RING9_TQM_RING_PG_SIZE_PG_1G
16687 uint8_t ring9_unused[3];
16688 /* Number of TQM ring entries. */
16689 uint32_t tqm_ring9_num_entries;
16690 /* TQM ring page directory. */
16691 uint64_t tqm_ring9_page_dir;
16692 /* TQM ring page size and level. */
16693 uint8_t tqm_ring10_pg_size_tqm_ring_lvl;
16694 /* TQM ring PBL indirect levels. */
16695 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_RING10_TQM_RING_LVL_MASK \
16697 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_RING10_TQM_RING_LVL_SFT \
16699 /* PBL pointer is physical start address. */
16700 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_RING10_TQM_RING_LVL_LVL_0 \
16702 /* PBL pointer points to PTE table. */
16703 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_RING10_TQM_RING_LVL_LVL_1 \
16706 * PBL pointer points to PDE table with each entry pointing to
16709 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_RING10_TQM_RING_LVL_LVL_2 \
16711 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_RING10_TQM_RING_LVL_LAST \
16712 HWRM_FUNC_BACKING_STORE_CFG_INPUT_RING10_TQM_RING_LVL_LVL_2
16713 /* TQM ring page size. */
16714 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_RING10_TQM_RING_PG_SIZE_MASK \
16716 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_RING10_TQM_RING_PG_SIZE_SFT \
16719 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_RING10_TQM_RING_PG_SIZE_PG_4K \
16720 (UINT32_C(0x0) << 4)
16722 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_RING10_TQM_RING_PG_SIZE_PG_8K \
16723 (UINT32_C(0x1) << 4)
16725 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_RING10_TQM_RING_PG_SIZE_PG_64K \
16726 (UINT32_C(0x2) << 4)
16728 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_RING10_TQM_RING_PG_SIZE_PG_2M \
16729 (UINT32_C(0x3) << 4)
16731 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_RING10_TQM_RING_PG_SIZE_PG_8M \
16732 (UINT32_C(0x4) << 4)
16734 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_RING10_TQM_RING_PG_SIZE_PG_1G \
16735 (UINT32_C(0x5) << 4)
16736 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_RING10_TQM_RING_PG_SIZE_LAST \
16737 HWRM_FUNC_BACKING_STORE_CFG_INPUT_RING10_TQM_RING_PG_SIZE_PG_1G
16738 uint8_t ring10_unused[3];
16739 /* Number of TQM ring entries. */
16740 uint32_t tqm_ring10_num_entries;
16741 /* TQM ring page directory. */
16742 uint64_t tqm_ring10_page_dir;
16743 /* Number of Tx KTLS context entries allocated. */
16744 uint32_t tkc_num_entries;
16745 /* Number of Rx KTLS context entries allocated. */
16746 uint32_t rkc_num_entries;
16747 /* Tx KTLS context page directory. */
16748 uint64_t tkc_page_dir;
16749 /* Rx KTLS context page directory. */
16750 uint64_t rkc_page_dir;
16751 /* Number of bytes allocated for each Tx KTLS context entry. */
16752 uint16_t tkc_entry_size;
16753 /* Number of bytes allocated for each Rx KTLS context entry. */
16754 uint16_t rkc_entry_size;
16755 /* Tx KTLS context page size and level. */
16756 uint8_t tkc_pg_size_tkc_lvl;
16757 /* Tx KTLS context PBL indirect levels. */
16758 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TKC_LVL_MASK \
16760 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TKC_LVL_SFT 0
16761 /* PBL pointer is physical start address. */
16762 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TKC_LVL_LVL_0 \
16764 /* PBL pointer points to PTE table. */
16765 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TKC_LVL_LVL_1 \
16767 /* PBL pointer points to PDE table with each entry pointing to PTE tables. */
16768 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TKC_LVL_LVL_2 \
16770 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TKC_LVL_LAST \
16771 HWRM_FUNC_BACKING_STORE_CFG_INPUT_TKC_LVL_LVL_2
16772 /* Tx KTLS context page size. */
16773 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TKC_PG_SIZE_MASK \
16775 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TKC_PG_SIZE_SFT 4
16777 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TKC_PG_SIZE_PG_4K \
16778 (UINT32_C(0x0) << 4)
16780 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TKC_PG_SIZE_PG_8K \
16781 (UINT32_C(0x1) << 4)
16783 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TKC_PG_SIZE_PG_64K \
16784 (UINT32_C(0x2) << 4)
16786 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TKC_PG_SIZE_PG_2M \
16787 (UINT32_C(0x3) << 4)
16789 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TKC_PG_SIZE_PG_8M \
16790 (UINT32_C(0x4) << 4)
16792 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TKC_PG_SIZE_PG_1G \
16793 (UINT32_C(0x5) << 4)
16794 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TKC_PG_SIZE_LAST \
16795 HWRM_FUNC_BACKING_STORE_CFG_INPUT_TKC_PG_SIZE_PG_1G
16796 /* Rx KTLS context page size and level. */
16797 uint8_t rkc_pg_size_rkc_lvl;
16798 /* Rx KTLS context PBL indirect levels. */
16799 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_RKC_LVL_MASK \
16801 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_RKC_LVL_SFT 0
16802 /* PBL pointer is physical start address. */
16803 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_RKC_LVL_LVL_0 \
16805 /* PBL pointer points to PTE table. */
16806 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_RKC_LVL_LVL_1 \
16809 * PBL pointer points to PDE table with each entry pointing to
16812 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_RKC_LVL_LVL_2 \
16814 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_RKC_LVL_LAST \
16815 HWRM_FUNC_BACKING_STORE_CFG_INPUT_RKC_LVL_LVL_2
16816 /* Rx KTLS context page size. */
16817 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_RKC_PG_SIZE_MASK \
16819 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_RKC_PG_SIZE_SFT 4
16821 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_RKC_PG_SIZE_PG_4K \
16822 (UINT32_C(0x0) << 4)
16824 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_RKC_PG_SIZE_PG_8K \
16825 (UINT32_C(0x1) << 4)
16827 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_RKC_PG_SIZE_PG_64K \
16828 (UINT32_C(0x2) << 4)
16830 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_RKC_PG_SIZE_PG_2M \
16831 (UINT32_C(0x3) << 4)
16833 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_RKC_PG_SIZE_PG_8M \
16834 (UINT32_C(0x4) << 4)
16836 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_RKC_PG_SIZE_PG_1G \
16837 (UINT32_C(0x5) << 4)
16838 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_RKC_PG_SIZE_LAST \
16839 HWRM_FUNC_BACKING_STORE_CFG_INPUT_RKC_PG_SIZE_PG_1G
16840 /* Reserved for future. */
16844 /* hwrm_func_backing_store_cfg_output (size:128b/16B) */
16845 struct hwrm_func_backing_store_cfg_output {
16846 /* The specific error status for the command. */
16847 uint16_t error_code;
16848 /* The HWRM command request type. */
16850 /* The sequence ID from the original command. */
16852 /* The length of the response data in number of bytes. */
16854 uint8_t unused_0[7];
16856 * This field is used in Output records to indicate that the output
16857 * is completely written to RAM. This field should be read as '1'
16858 * to indicate that the output has been completely written.
16859 * When writing a command completion or response to an internal processor,
16860 * the order of writes has to be such that this field is written last.
16865 /********************************
16866 * hwrm_func_backing_store_qcfg *
16867 ********************************/
16870 /* hwrm_func_backing_store_qcfg_input (size:128b/16B) */
16871 struct hwrm_func_backing_store_qcfg_input {
16872 /* The HWRM command request type. */
16875 * The completion ring to send the completion event on. This should
16876 * be the NQ ID returned from the `nq_alloc` HWRM command.
16878 uint16_t cmpl_ring;
16880 * The sequence ID is used by the driver for tracking multiple
16881 * commands. This ID is treated as opaque data by the firmware and
16882 * the value is returned in the `hwrm_resp_hdr` upon completion.
16886 * The target ID of the command:
16887 * * 0x0-0xFFF8 - The function ID
16888 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
16889 * * 0xFFFD - Reserved for user-space HWRM interface
16892 uint16_t target_id;
16894 * A physical address pointer pointing to a host buffer that the
16895 * command's response data will be written. This can be either a host
16896 * physical address (HPA) or a guest physical address (GPA) and must
16897 * point to a physically contiguous block of memory.
16899 uint64_t resp_addr;
16902 /* hwrm_func_backing_store_qcfg_output (size:2496b/312B) */
16903 struct hwrm_func_backing_store_qcfg_output {
16904 /* The specific error status for the command. */
16905 uint16_t error_code;
16906 /* The HWRM command request type. */
16908 /* The sequence ID from the original command. */
16910 /* The length of the response data in number of bytes. */
16914 * When set, the firmware only uses on-chip resources and does not
16915 * expect any backing store to be provided by the host driver. This
16916 * mode provides minimal L2 functionality (e.g. limited L2 resources,
16919 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_FLAGS_PREBOOT_MODE \
16922 * When set, the 32b `mrav_num_entries` field is logically divided
16923 * into two 16b fields, `mr_num_entries` and `av_num_entries`.
16925 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_FLAGS_MRAV_RESERVATION_SPLIT \
16929 * This bit must be '1' for the qp fields to be
16932 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_ENABLES_QP \
16935 * This bit must be '1' for the srq fields to be
16938 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_ENABLES_SRQ \
16941 * This bit must be '1' for the cq fields to be
16944 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_ENABLES_CQ \
16947 * This bit must be '1' for the vnic fields to be
16950 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_ENABLES_VNIC \
16953 * This bit must be '1' for the stat fields to be
16956 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_ENABLES_STAT \
16959 * This bit must be '1' for the tqm_sp fields to be
16962 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_ENABLES_TQM_SP \
16965 * This bit must be '1' for the tqm_ring0 fields to be
16968 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_ENABLES_TQM_RING0 \
16971 * This bit must be '1' for the tqm_ring1 fields to be
16974 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_ENABLES_TQM_RING1 \
16977 * This bit must be '1' for the tqm_ring2 fields to be
16980 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_ENABLES_TQM_RING2 \
16983 * This bit must be '1' for the tqm_ring3 fields to be
16986 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_ENABLES_TQM_RING3 \
16989 * This bit must be '1' for the tqm_ring4 fields to be
16992 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_ENABLES_TQM_RING4 \
16995 * This bit must be '1' for the tqm_ring5 fields to be
16998 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_ENABLES_TQM_RING5 \
17001 * This bit must be '1' for the tqm_ring6 fields to be
17004 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_ENABLES_TQM_RING6 \
17007 * This bit must be '1' for the tqm_ring7 fields to be
17010 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_ENABLES_TQM_RING7 \
17013 * This bit must be '1' for the mrav fields to be
17016 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_ENABLES_MRAV \
17019 * This bit must be '1' for the tim fields to be
17022 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_ENABLES_TIM \
17025 * This bit must be '1' for the tqm_ring8 fields to be
17028 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_ENABLES_TQM_RING8 \
17031 * This bit must be '1' for the tqm_ring9 fields to be
17034 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_ENABLES_TQM_RING9 \
17037 * This bit must be '1' for the tqm_ring10 fields to be
17040 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_ENABLES_TQM_RING10 \
17043 * This bit must be '1' for the Tx KTLS context
17044 * fields to be configured.
17046 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_ENABLES_TKC \
17049 * This bit must be '1' for the Rx KTLS context
17050 * fields to be configured.
17052 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_ENABLES_RKC \
17054 /* QPC page size and level. */
17055 uint8_t qpc_pg_size_qpc_lvl;
17056 /* QPC PBL indirect levels. */
17057 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_QPC_LVL_MASK \
17059 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_QPC_LVL_SFT 0
17060 /* PBL pointer is physical start address. */
17061 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_QPC_LVL_LVL_0 \
17063 /* PBL pointer points to PTE table. */
17064 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_QPC_LVL_LVL_1 \
17066 /* PBL pointer points to PDE table with each entry pointing to PTE tables. */
17067 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_QPC_LVL_LVL_2 \
17069 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_QPC_LVL_LAST \
17070 HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_QPC_LVL_LVL_2
17071 /* QPC page size. */
17072 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_QPC_PG_SIZE_MASK \
17074 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_QPC_PG_SIZE_SFT 4
17076 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_QPC_PG_SIZE_PG_4K \
17077 (UINT32_C(0x0) << 4)
17079 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_QPC_PG_SIZE_PG_8K \
17080 (UINT32_C(0x1) << 4)
17082 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_QPC_PG_SIZE_PG_64K \
17083 (UINT32_C(0x2) << 4)
17085 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_QPC_PG_SIZE_PG_2M \
17086 (UINT32_C(0x3) << 4)
17088 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_QPC_PG_SIZE_PG_8M \
17089 (UINT32_C(0x4) << 4)
17091 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_QPC_PG_SIZE_PG_1G \
17092 (UINT32_C(0x5) << 4)
17093 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_QPC_PG_SIZE_LAST \
17094 HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_QPC_PG_SIZE_PG_1G
17095 /* SRQ page size and level. */
17096 uint8_t srq_pg_size_srq_lvl;
17097 /* SRQ PBL indirect levels. */
17098 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_SRQ_LVL_MASK \
17100 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_SRQ_LVL_SFT 0
17101 /* PBL pointer is physical start address. */
17102 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_SRQ_LVL_LVL_0 \
17104 /* PBL pointer points to PTE table. */
17105 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_SRQ_LVL_LVL_1 \
17107 /* PBL pointer points to PDE table with each entry pointing to PTE tables. */
17108 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_SRQ_LVL_LVL_2 \
17110 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_SRQ_LVL_LAST \
17111 HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_SRQ_LVL_LVL_2
17112 /* SRQ page size. */
17113 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_SRQ_PG_SIZE_MASK \
17115 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_SRQ_PG_SIZE_SFT 4
17117 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_SRQ_PG_SIZE_PG_4K \
17118 (UINT32_C(0x0) << 4)
17120 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_SRQ_PG_SIZE_PG_8K \
17121 (UINT32_C(0x1) << 4)
17123 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_SRQ_PG_SIZE_PG_64K \
17124 (UINT32_C(0x2) << 4)
17126 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_SRQ_PG_SIZE_PG_2M \
17127 (UINT32_C(0x3) << 4)
17129 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_SRQ_PG_SIZE_PG_8M \
17130 (UINT32_C(0x4) << 4)
17132 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_SRQ_PG_SIZE_PG_1G \
17133 (UINT32_C(0x5) << 4)
17134 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_SRQ_PG_SIZE_LAST \
17135 HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_SRQ_PG_SIZE_PG_1G
17136 /* CQ page size and level. */
17137 uint8_t cq_pg_size_cq_lvl;
17138 /* CQ PBL indirect levels. */
17139 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_CQ_LVL_MASK \
17141 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_CQ_LVL_SFT 0
17142 /* PBL pointer is physical start address. */
17143 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_CQ_LVL_LVL_0 \
17145 /* PBL pointer points to PTE table. */
17146 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_CQ_LVL_LVL_1 \
17148 /* PBL pointer points to PDE table with each entry pointing to PTE tables. */
17149 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_CQ_LVL_LVL_2 \
17151 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_CQ_LVL_LAST \
17152 HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_CQ_LVL_LVL_2
17153 /* CQ page size. */
17154 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_CQ_PG_SIZE_MASK \
17156 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_CQ_PG_SIZE_SFT 4
17158 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_CQ_PG_SIZE_PG_4K \
17159 (UINT32_C(0x0) << 4)
17161 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_CQ_PG_SIZE_PG_8K \
17162 (UINT32_C(0x1) << 4)
17164 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_CQ_PG_SIZE_PG_64K \
17165 (UINT32_C(0x2) << 4)
17167 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_CQ_PG_SIZE_PG_2M \
17168 (UINT32_C(0x3) << 4)
17170 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_CQ_PG_SIZE_PG_8M \
17171 (UINT32_C(0x4) << 4)
17173 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_CQ_PG_SIZE_PG_1G \
17174 (UINT32_C(0x5) << 4)
17175 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_CQ_PG_SIZE_LAST \
17176 HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_CQ_PG_SIZE_PG_1G
17177 /* VNIC page size and level. */
17178 uint8_t vnic_pg_size_vnic_lvl;
17179 /* VNIC PBL indirect levels. */
17180 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_VNIC_LVL_MASK \
17182 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_VNIC_LVL_SFT 0
17183 /* PBL pointer is physical start address. */
17184 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_VNIC_LVL_LVL_0 \
17186 /* PBL pointer points to PTE table. */
17187 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_VNIC_LVL_LVL_1 \
17189 /* PBL pointer points to PDE table with each entry pointing to PTE tables. */
17190 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_VNIC_LVL_LVL_2 \
17192 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_VNIC_LVL_LAST \
17193 HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_VNIC_LVL_LVL_2
17194 /* VNIC page size. */
17195 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_VNIC_PG_SIZE_MASK \
17197 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_VNIC_PG_SIZE_SFT 4
17199 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_VNIC_PG_SIZE_PG_4K \
17200 (UINT32_C(0x0) << 4)
17202 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_VNIC_PG_SIZE_PG_8K \
17203 (UINT32_C(0x1) << 4)
17205 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_VNIC_PG_SIZE_PG_64K \
17206 (UINT32_C(0x2) << 4)
17208 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_VNIC_PG_SIZE_PG_2M \
17209 (UINT32_C(0x3) << 4)
17211 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_VNIC_PG_SIZE_PG_8M \
17212 (UINT32_C(0x4) << 4)
17214 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_VNIC_PG_SIZE_PG_1G \
17215 (UINT32_C(0x5) << 4)
17216 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_VNIC_PG_SIZE_LAST \
17217 HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_VNIC_PG_SIZE_PG_1G
17218 /* Stat page size and level. */
17219 uint8_t stat_pg_size_stat_lvl;
17220 /* Stat PBL indirect levels. */
17221 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_STAT_LVL_MASK \
17223 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_STAT_LVL_SFT 0
17224 /* PBL pointer is physical start address. */
17225 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_STAT_LVL_LVL_0 \
17227 /* PBL pointer points to PTE table. */
17228 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_STAT_LVL_LVL_1 \
17230 /* PBL pointer points to PDE table with each entry pointing to PTE tables. */
17231 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_STAT_LVL_LVL_2 \
17233 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_STAT_LVL_LAST \
17234 HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_STAT_LVL_LVL_2
17235 /* Stat page size. */
17236 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_STAT_PG_SIZE_MASK \
17238 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_STAT_PG_SIZE_SFT 4
17240 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_STAT_PG_SIZE_PG_4K \
17241 (UINT32_C(0x0) << 4)
17243 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_STAT_PG_SIZE_PG_8K \
17244 (UINT32_C(0x1) << 4)
17246 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_STAT_PG_SIZE_PG_64K \
17247 (UINT32_C(0x2) << 4)
17249 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_STAT_PG_SIZE_PG_2M \
17250 (UINT32_C(0x3) << 4)
17252 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_STAT_PG_SIZE_PG_8M \
17253 (UINT32_C(0x4) << 4)
17255 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_STAT_PG_SIZE_PG_1G \
17256 (UINT32_C(0x5) << 4)
17257 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_STAT_PG_SIZE_LAST \
17258 HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_STAT_PG_SIZE_PG_1G
17259 /* TQM slow path page size and level. */
17260 uint8_t tqm_sp_pg_size_tqm_sp_lvl;
17261 /* TQM slow path PBL indirect levels. */
17262 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_SP_LVL_MASK \
17264 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_SP_LVL_SFT 0
17265 /* PBL pointer is physical start address. */
17266 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_SP_LVL_LVL_0 \
17268 /* PBL pointer points to PTE table. */
17269 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_SP_LVL_LVL_1 \
17271 /* PBL pointer points to PDE table with each entry pointing to PTE tables. */
17272 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_SP_LVL_LVL_2 \
17274 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_SP_LVL_LAST \
17275 HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_SP_LVL_LVL_2
17276 /* TQM slow path page size. */
17277 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_SP_PG_SIZE_MASK \
17279 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_SP_PG_SIZE_SFT 4
17281 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_SP_PG_SIZE_PG_4K \
17282 (UINT32_C(0x0) << 4)
17284 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_SP_PG_SIZE_PG_8K \
17285 (UINT32_C(0x1) << 4)
17287 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_SP_PG_SIZE_PG_64K \
17288 (UINT32_C(0x2) << 4)
17290 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_SP_PG_SIZE_PG_2M \
17291 (UINT32_C(0x3) << 4)
17293 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_SP_PG_SIZE_PG_8M \
17294 (UINT32_C(0x4) << 4)
17296 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_SP_PG_SIZE_PG_1G \
17297 (UINT32_C(0x5) << 4)
17298 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_SP_PG_SIZE_LAST \
17299 HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_SP_PG_SIZE_PG_1G
17300 /* TQM ring 0 page size and level. */
17301 uint8_t tqm_ring0_pg_size_tqm_ring0_lvl;
17302 /* TQM ring 0 PBL indirect levels. */
17303 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING0_LVL_MASK \
17305 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING0_LVL_SFT 0
17306 /* PBL pointer is physical start address. */
17307 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING0_LVL_LVL_0 \
17309 /* PBL pointer points to PTE table. */
17310 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING0_LVL_LVL_1 \
17312 /* PBL pointer points to PDE table with each entry pointing to PTE tables. */
17313 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING0_LVL_LVL_2 \
17315 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING0_LVL_LAST \
17316 HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING0_LVL_LVL_2
17317 /* TQM ring 0 page size. */
17318 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING0_PG_SIZE_MASK \
17320 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING0_PG_SIZE_SFT 4
17322 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING0_PG_SIZE_PG_4K \
17323 (UINT32_C(0x0) << 4)
17325 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING0_PG_SIZE_PG_8K \
17326 (UINT32_C(0x1) << 4)
17328 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING0_PG_SIZE_PG_64K \
17329 (UINT32_C(0x2) << 4)
17331 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING0_PG_SIZE_PG_2M \
17332 (UINT32_C(0x3) << 4)
17334 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING0_PG_SIZE_PG_8M \
17335 (UINT32_C(0x4) << 4)
17337 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING0_PG_SIZE_PG_1G \
17338 (UINT32_C(0x5) << 4)
17339 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING0_PG_SIZE_LAST \
17340 HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING0_PG_SIZE_PG_1G
17341 /* TQM ring 1 page size and level. */
17342 uint8_t tqm_ring1_pg_size_tqm_ring1_lvl;
17343 /* TQM ring 1 PBL indirect levels. */
17344 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING1_LVL_MASK \
17346 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING1_LVL_SFT 0
17347 /* PBL pointer is physical start address. */
17348 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING1_LVL_LVL_0 \
17350 /* PBL pointer points to PTE table. */
17351 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING1_LVL_LVL_1 \
17353 /* PBL pointer points to PDE table with each entry pointing to PTE tables. */
17354 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING1_LVL_LVL_2 \
17356 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING1_LVL_LAST \
17357 HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING1_LVL_LVL_2
17358 /* TQM ring 1 page size. */
17359 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING1_PG_SIZE_MASK \
17361 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING1_PG_SIZE_SFT 4
17363 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING1_PG_SIZE_PG_4K \
17364 (UINT32_C(0x0) << 4)
17366 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING1_PG_SIZE_PG_8K \
17367 (UINT32_C(0x1) << 4)
17369 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING1_PG_SIZE_PG_64K \
17370 (UINT32_C(0x2) << 4)
17372 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING1_PG_SIZE_PG_2M \
17373 (UINT32_C(0x3) << 4)
17375 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING1_PG_SIZE_PG_8M \
17376 (UINT32_C(0x4) << 4)
17378 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING1_PG_SIZE_PG_1G \
17379 (UINT32_C(0x5) << 4)
17380 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING1_PG_SIZE_LAST \
17381 HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING1_PG_SIZE_PG_1G
17382 /* TQM ring 2 page size and level. */
17383 uint8_t tqm_ring2_pg_size_tqm_ring2_lvl;
17384 /* TQM ring 2 PBL indirect levels. */
17385 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING2_LVL_MASK \
17387 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING2_LVL_SFT 0
17388 /* PBL pointer is physical start address. */
17389 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING2_LVL_LVL_0 \
17391 /* PBL pointer points to PTE table. */
17392 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING2_LVL_LVL_1 \
17394 /* PBL pointer points to PDE table with each entry pointing to PTE tables. */
17395 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING2_LVL_LVL_2 \
17397 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING2_LVL_LAST \
17398 HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING2_LVL_LVL_2
17399 /* TQM ring 2 page size. */
17400 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING2_PG_SIZE_MASK \
17402 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING2_PG_SIZE_SFT 4
17404 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING2_PG_SIZE_PG_4K \
17405 (UINT32_C(0x0) << 4)
17407 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING2_PG_SIZE_PG_8K \
17408 (UINT32_C(0x1) << 4)
17410 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING2_PG_SIZE_PG_64K \
17411 (UINT32_C(0x2) << 4)
17413 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING2_PG_SIZE_PG_2M \
17414 (UINT32_C(0x3) << 4)
17416 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING2_PG_SIZE_PG_8M \
17417 (UINT32_C(0x4) << 4)
17419 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING2_PG_SIZE_PG_1G \
17420 (UINT32_C(0x5) << 4)
17421 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING2_PG_SIZE_LAST \
17422 HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING2_PG_SIZE_PG_1G
17423 /* TQM ring 3 page size and level. */
17424 uint8_t tqm_ring3_pg_size_tqm_ring3_lvl;
17425 /* TQM ring 3 PBL indirect levels. */
17426 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING3_LVL_MASK \
17428 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING3_LVL_SFT 0
17429 /* PBL pointer is physical start address. */
17430 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING3_LVL_LVL_0 \
17432 /* PBL pointer points to PTE table. */
17433 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING3_LVL_LVL_1 \
17435 /* PBL pointer points to PDE table with each entry pointing to PTE tables. */
17436 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING3_LVL_LVL_2 \
17438 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING3_LVL_LAST \
17439 HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING3_LVL_LVL_2
17440 /* TQM ring 3 page size. */
17441 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING3_PG_SIZE_MASK \
17443 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING3_PG_SIZE_SFT 4
17445 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING3_PG_SIZE_PG_4K \
17446 (UINT32_C(0x0) << 4)
17448 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING3_PG_SIZE_PG_8K \
17449 (UINT32_C(0x1) << 4)
17451 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING3_PG_SIZE_PG_64K \
17452 (UINT32_C(0x2) << 4)
17454 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING3_PG_SIZE_PG_2M \
17455 (UINT32_C(0x3) << 4)
17457 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING3_PG_SIZE_PG_8M \
17458 (UINT32_C(0x4) << 4)
17460 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING3_PG_SIZE_PG_1G \
17461 (UINT32_C(0x5) << 4)
17462 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING3_PG_SIZE_LAST \
17463 HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING3_PG_SIZE_PG_1G
17464 /* TQM ring 4 page size and level. */
17465 uint8_t tqm_ring4_pg_size_tqm_ring4_lvl;
17466 /* TQM ring 4 PBL indirect levels. */
17467 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING4_LVL_MASK \
17469 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING4_LVL_SFT 0
17470 /* PBL pointer is physical start address. */
17471 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING4_LVL_LVL_0 \
17473 /* PBL pointer points to PTE table. */
17474 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING4_LVL_LVL_1 \
17476 /* PBL pointer points to PDE table with each entry pointing to PTE tables. */
17477 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING4_LVL_LVL_2 \
17479 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING4_LVL_LAST \
17480 HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING4_LVL_LVL_2
17481 /* TQM ring 4 page size. */
17482 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING4_PG_SIZE_MASK \
17484 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING4_PG_SIZE_SFT 4
17486 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING4_PG_SIZE_PG_4K \
17487 (UINT32_C(0x0) << 4)
17489 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING4_PG_SIZE_PG_8K \
17490 (UINT32_C(0x1) << 4)
17492 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING4_PG_SIZE_PG_64K \
17493 (UINT32_C(0x2) << 4)
17495 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING4_PG_SIZE_PG_2M \
17496 (UINT32_C(0x3) << 4)
17498 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING4_PG_SIZE_PG_8M \
17499 (UINT32_C(0x4) << 4)
17501 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING4_PG_SIZE_PG_1G \
17502 (UINT32_C(0x5) << 4)
17503 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING4_PG_SIZE_LAST \
17504 HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING4_PG_SIZE_PG_1G
17505 /* TQM ring 5 page size and level. */
17506 uint8_t tqm_ring5_pg_size_tqm_ring5_lvl;
17507 /* TQM ring 5 PBL indirect levels. */
17508 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING5_LVL_MASK \
17510 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING5_LVL_SFT 0
17511 /* PBL pointer is physical start address. */
17512 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING5_LVL_LVL_0 \
17514 /* PBL pointer points to PTE table. */
17515 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING5_LVL_LVL_1 \
17517 /* PBL pointer points to PDE table with each entry pointing to PTE tables. */
17518 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING5_LVL_LVL_2 \
17520 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING5_LVL_LAST \
17521 HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING5_LVL_LVL_2
17522 /* TQM ring 5 page size. */
17523 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING5_PG_SIZE_MASK \
17525 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING5_PG_SIZE_SFT 4
17527 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING5_PG_SIZE_PG_4K \
17528 (UINT32_C(0x0) << 4)
17530 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING5_PG_SIZE_PG_8K \
17531 (UINT32_C(0x1) << 4)
17533 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING5_PG_SIZE_PG_64K \
17534 (UINT32_C(0x2) << 4)
17536 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING5_PG_SIZE_PG_2M \
17537 (UINT32_C(0x3) << 4)
17539 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING5_PG_SIZE_PG_8M \
17540 (UINT32_C(0x4) << 4)
17542 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING5_PG_SIZE_PG_1G \
17543 (UINT32_C(0x5) << 4)
17544 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING5_PG_SIZE_LAST \
17545 HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING5_PG_SIZE_PG_1G
17546 /* TQM ring 6 page size and level. */
17547 uint8_t tqm_ring6_pg_size_tqm_ring6_lvl;
17548 /* TQM ring 6 PBL indirect levels. */
17549 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING6_LVL_MASK \
17551 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING6_LVL_SFT 0
17552 /* PBL pointer is physical start address. */
17553 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING6_LVL_LVL_0 \
17555 /* PBL pointer points to PTE table. */
17556 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING6_LVL_LVL_1 \
17558 /* PBL pointer points to PDE table with each entry pointing to PTE tables. */
17559 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING6_LVL_LVL_2 \
17561 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING6_LVL_LAST \
17562 HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING6_LVL_LVL_2
17563 /* TQM ring 6 page size. */
17564 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING6_PG_SIZE_MASK \
17566 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING6_PG_SIZE_SFT 4
17568 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING6_PG_SIZE_PG_4K \
17569 (UINT32_C(0x0) << 4)
17571 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING6_PG_SIZE_PG_8K \
17572 (UINT32_C(0x1) << 4)
17574 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING6_PG_SIZE_PG_64K \
17575 (UINT32_C(0x2) << 4)
17577 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING6_PG_SIZE_PG_2M \
17578 (UINT32_C(0x3) << 4)
17580 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING6_PG_SIZE_PG_8M \
17581 (UINT32_C(0x4) << 4)
17583 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING6_PG_SIZE_PG_1G \
17584 (UINT32_C(0x5) << 4)
17585 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING6_PG_SIZE_LAST \
17586 HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING6_PG_SIZE_PG_1G
17587 /* TQM ring 7 page size and level. */
17588 uint8_t tqm_ring7_pg_size_tqm_ring7_lvl;
17589 /* TQM ring 7 PBL indirect levels. */
17590 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING7_LVL_MASK \
17592 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING7_LVL_SFT 0
17593 /* PBL pointer is physical start address. */
17594 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING7_LVL_LVL_0 \
17596 /* PBL pointer points to PTE table. */
17597 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING7_LVL_LVL_1 \
17599 /* PBL pointer points to PDE table with each entry pointing to PTE tables. */
17600 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING7_LVL_LVL_2 \
17602 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING7_LVL_LAST \
17603 HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING7_LVL_LVL_2
17604 /* TQM ring 7 page size. */
17605 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING7_PG_SIZE_MASK \
17607 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING7_PG_SIZE_SFT 4
17609 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING7_PG_SIZE_PG_4K \
17610 (UINT32_C(0x0) << 4)
17612 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING7_PG_SIZE_PG_8K \
17613 (UINT32_C(0x1) << 4)
17615 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING7_PG_SIZE_PG_64K \
17616 (UINT32_C(0x2) << 4)
17618 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING7_PG_SIZE_PG_2M \
17619 (UINT32_C(0x3) << 4)
17621 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING7_PG_SIZE_PG_8M \
17622 (UINT32_C(0x4) << 4)
17624 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING7_PG_SIZE_PG_1G \
17625 (UINT32_C(0x5) << 4)
17626 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING7_PG_SIZE_LAST \
17627 HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING7_PG_SIZE_PG_1G
17628 /* MR/AV page size and level. */
17629 uint8_t mrav_pg_size_mrav_lvl;
17630 /* MR/AV PBL indirect levels. */
17631 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_MRAV_LVL_MASK \
17633 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_MRAV_LVL_SFT 0
17634 /* PBL pointer is physical start address. */
17635 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_MRAV_LVL_LVL_0 \
17637 /* PBL pointer points to PTE table. */
17638 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_MRAV_LVL_LVL_1 \
17640 /* PBL pointer points to PDE table with each entry pointing to PTE tables. */
17641 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_MRAV_LVL_LVL_2 \
17643 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_MRAV_LVL_LAST \
17644 HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_MRAV_LVL_LVL_2
17645 /* MR/AV page size. */
17646 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_MRAV_PG_SIZE_MASK \
17648 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_MRAV_PG_SIZE_SFT 4
17650 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_MRAV_PG_SIZE_PG_4K \
17651 (UINT32_C(0x0) << 4)
17653 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_MRAV_PG_SIZE_PG_8K \
17654 (UINT32_C(0x1) << 4)
17656 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_MRAV_PG_SIZE_PG_64K \
17657 (UINT32_C(0x2) << 4)
17659 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_MRAV_PG_SIZE_PG_2M \
17660 (UINT32_C(0x3) << 4)
17662 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_MRAV_PG_SIZE_PG_8M \
17663 (UINT32_C(0x4) << 4)
17665 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_MRAV_PG_SIZE_PG_1G \
17666 (UINT32_C(0x5) << 4)
17667 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_MRAV_PG_SIZE_LAST \
17668 HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_MRAV_PG_SIZE_PG_1G
17669 /* Timer page size and level. */
17670 uint8_t tim_pg_size_tim_lvl;
17671 /* Timer PBL indirect levels. */
17672 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TIM_LVL_MASK \
17674 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TIM_LVL_SFT 0
17675 /* PBL pointer is physical start address. */
17676 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TIM_LVL_LVL_0 \
17678 /* PBL pointer points to PTE table. */
17679 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TIM_LVL_LVL_1 \
17681 /* PBL pointer points to PDE table with each entry pointing to PTE tables. */
17682 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TIM_LVL_LVL_2 \
17684 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TIM_LVL_LAST \
17685 HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TIM_LVL_LVL_2
17686 /* Timer page size. */
17687 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TIM_PG_SIZE_MASK \
17689 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TIM_PG_SIZE_SFT 4
17691 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TIM_PG_SIZE_PG_4K \
17692 (UINT32_C(0x0) << 4)
17694 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TIM_PG_SIZE_PG_8K \
17695 (UINT32_C(0x1) << 4)
17697 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TIM_PG_SIZE_PG_64K \
17698 (UINT32_C(0x2) << 4)
17700 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TIM_PG_SIZE_PG_2M \
17701 (UINT32_C(0x3) << 4)
17703 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TIM_PG_SIZE_PG_8M \
17704 (UINT32_C(0x4) << 4)
17706 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TIM_PG_SIZE_PG_1G \
17707 (UINT32_C(0x5) << 4)
17708 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TIM_PG_SIZE_LAST \
17709 HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TIM_PG_SIZE_PG_1G
17710 /* QP page directory. */
17711 uint64_t qpc_page_dir;
17712 /* SRQ page directory. */
17713 uint64_t srq_page_dir;
17714 /* CQ page directory. */
17715 uint64_t cq_page_dir;
17716 /* VNIC page directory. */
17717 uint64_t vnic_page_dir;
17718 /* Stat page directory. */
17719 uint64_t stat_page_dir;
17720 /* TQM slowpath page directory. */
17721 uint64_t tqm_sp_page_dir;
17722 /* TQM ring 0 page directory. */
17723 uint64_t tqm_ring0_page_dir;
17724 /* TQM ring 1 page directory. */
17725 uint64_t tqm_ring1_page_dir;
17726 /* TQM ring 2 page directory. */
17727 uint64_t tqm_ring2_page_dir;
17728 /* TQM ring 3 page directory. */
17729 uint64_t tqm_ring3_page_dir;
17730 /* TQM ring 4 page directory. */
17731 uint64_t tqm_ring4_page_dir;
17732 /* TQM ring 5 page directory. */
17733 uint64_t tqm_ring5_page_dir;
17734 /* TQM ring 6 page directory. */
17735 uint64_t tqm_ring6_page_dir;
17736 /* TQM ring 7 page directory. */
17737 uint64_t tqm_ring7_page_dir;
17738 /* MR/AV page directory. */
17739 uint64_t mrav_page_dir;
17740 /* Timer page directory. */
17741 uint64_t tim_page_dir;
17742 /* Number of entries to reserve for QP1 */
17743 uint16_t qp_num_qp1_entries;
17744 /* Number of entries to reserve for L2 */
17745 uint16_t qp_num_l2_entries;
17746 /* Number of QPs. */
17747 uint32_t qp_num_entries;
17748 /* Number of SRQs. */
17749 uint32_t srq_num_entries;
17750 /* Number of entries to reserve for L2 */
17751 uint16_t srq_num_l2_entries;
17752 /* Number of entries to reserve for L2 */
17753 uint16_t cq_num_l2_entries;
17754 /* Number of CQs. */
17755 uint32_t cq_num_entries;
17756 /* Number of entries to reserve for VNIC entries */
17757 uint16_t vnic_num_vnic_entries;
17758 /* Number of entries to reserve for Ring table entries */
17759 uint16_t vnic_num_ring_table_entries;
17760 /* Number of Stats. */
17761 uint32_t stat_num_entries;
17762 /* Number of TQM slowpath entries. */
17763 uint32_t tqm_sp_num_entries;
17764 /* Number of TQM ring 0 entries. */
17765 uint32_t tqm_ring0_num_entries;
17766 /* Number of TQM ring 1 entries. */
17767 uint32_t tqm_ring1_num_entries;
17768 /* Number of TQM ring 2 entries. */
17769 uint32_t tqm_ring2_num_entries;
17770 /* Number of TQM ring 3 entries. */
17771 uint32_t tqm_ring3_num_entries;
17772 /* Number of TQM ring 4 entries. */
17773 uint32_t tqm_ring4_num_entries;
17774 /* Number of TQM ring 5 entries. */
17775 uint32_t tqm_ring5_num_entries;
17776 /* Number of TQM ring 6 entries. */
17777 uint32_t tqm_ring6_num_entries;
17778 /* Number of TQM ring 7 entries. */
17779 uint32_t tqm_ring7_num_entries;
17781 * If the MR/AV split reservation flag is not set, then this field
17782 * represents the total number of MR plus AV entries. For versions
17783 * of firmware that support the split reservation, when it is not
17784 * specified half of the entries will be reserved for MRs and the
17785 * other half for AVs.
17787 * If the MR/AV split reservation flag is set, then this
17788 * field is logically divided into two 16b fields. Bits `[31:16]`
17789 * represents the `mr_num_entries` and bits `[15:0]` represents
17790 * `av_num_entries`. The granularity of these values is defined by
17791 * the `mrav_num_entries_unit` field returned by the
17792 * `backing_store_qcaps` command.
17794 uint32_t mrav_num_entries;
17795 /* Number of Timer entries. */
17796 uint32_t tim_num_entries;
17797 /* TQM ring page size and level. */
17798 uint8_t tqm_ring8_pg_size_tqm_ring_lvl;
17799 /* TQM ring PBL indirect levels. */
17800 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_RING8_TQM_RING_LVL_MASK \
17802 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_RING8_TQM_RING_LVL_SFT \
17804 /* PBL pointer is physical start address. */
17805 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_RING8_TQM_RING_LVL_LVL_0 \
17807 /* PBL pointer points to PTE table. */
17808 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_RING8_TQM_RING_LVL_LVL_1 \
17811 * PBL pointer points to PDE table with each entry pointing to
17814 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_RING8_TQM_RING_LVL_LVL_2 \
17816 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_RING8_TQM_RING_LVL_LAST \
17817 HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_RING8_TQM_RING_LVL_LVL_2
17818 /* TQM ring page size. */
17819 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_RING8_TQM_RING_PG_SIZE_MASK \
17821 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_RING8_TQM_RING_PG_SIZE_SFT \
17824 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_RING8_TQM_RING_PG_SIZE_PG_4K \
17825 (UINT32_C(0x0) << 4)
17827 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_RING8_TQM_RING_PG_SIZE_PG_8K \
17828 (UINT32_C(0x1) << 4)
17830 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_RING8_TQM_RING_PG_SIZE_PG_64K \
17831 (UINT32_C(0x2) << 4)
17833 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_RING8_TQM_RING_PG_SIZE_PG_2M \
17834 (UINT32_C(0x3) << 4)
17836 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_RING8_TQM_RING_PG_SIZE_PG_8M \
17837 (UINT32_C(0x4) << 4)
17839 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_RING8_TQM_RING_PG_SIZE_PG_1G \
17840 (UINT32_C(0x5) << 4)
17841 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_RING8_TQM_RING_PG_SIZE_LAST \
17842 HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_RING8_TQM_RING_PG_SIZE_PG_1G
17843 uint8_t ring8_unused[3];
17844 /* Number of TQM ring entries. */
17845 uint32_t tqm_ring8_num_entries;
17846 /* TQM ring page directory. */
17847 uint64_t tqm_ring8_page_dir;
17848 /* TQM ring page size and level. */
17849 uint8_t tqm_ring9_pg_size_tqm_ring_lvl;
17850 /* TQM ring PBL indirect levels. */
17851 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_RING9_TQM_RING_LVL_MASK \
17853 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_RING9_TQM_RING_LVL_SFT \
17855 /* PBL pointer is physical start address. */
17856 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_RING9_TQM_RING_LVL_LVL_0 \
17858 /* PBL pointer points to PTE table. */
17859 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_RING9_TQM_RING_LVL_LVL_1 \
17862 * PBL pointer points to PDE table with each entry pointing to
17865 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_RING9_TQM_RING_LVL_LVL_2 \
17867 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_RING9_TQM_RING_LVL_LAST \
17868 HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_RING9_TQM_RING_LVL_LVL_2
17869 /* TQM ring page size. */
17870 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_RING9_TQM_RING_PG_SIZE_MASK \
17872 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_RING9_TQM_RING_PG_SIZE_SFT \
17875 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_RING9_TQM_RING_PG_SIZE_PG_4K \
17876 (UINT32_C(0x0) << 4)
17878 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_RING9_TQM_RING_PG_SIZE_PG_8K \
17879 (UINT32_C(0x1) << 4)
17881 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_RING9_TQM_RING_PG_SIZE_PG_64K \
17882 (UINT32_C(0x2) << 4)
17884 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_RING9_TQM_RING_PG_SIZE_PG_2M \
17885 (UINT32_C(0x3) << 4)
17887 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_RING9_TQM_RING_PG_SIZE_PG_8M \
17888 (UINT32_C(0x4) << 4)
17890 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_RING9_TQM_RING_PG_SIZE_PG_1G \
17891 (UINT32_C(0x5) << 4)
17892 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_RING9_TQM_RING_PG_SIZE_LAST \
17893 HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_RING9_TQM_RING_PG_SIZE_PG_1G
17894 uint8_t ring9_unused[3];
17895 /* Number of TQM ring entries. */
17896 uint32_t tqm_ring9_num_entries;
17897 /* TQM ring page directory. */
17898 uint64_t tqm_ring9_page_dir;
17899 /* TQM ring page size and level. */
17900 uint8_t tqm_ring10_pg_size_tqm_ring_lvl;
17901 /* TQM ring PBL indirect levels. */
17902 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_RING10_TQM_RING_LVL_MASK \
17904 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_RING10_TQM_RING_LVL_SFT \
17906 /* PBL pointer is physical start address. */
17907 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_RING10_TQM_RING_LVL_LVL_0 \
17909 /* PBL pointer points to PTE table. */
17910 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_RING10_TQM_RING_LVL_LVL_1 \
17913 * PBL pointer points to PDE table with each entry pointing to
17916 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_RING10_TQM_RING_LVL_LVL_2 \
17918 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_RING10_TQM_RING_LVL_LAST \
17919 HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_RING10_TQM_RING_LVL_LVL_2
17920 /* TQM ring page size. */
17921 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_RING10_TQM_RING_PG_SIZE_MASK \
17923 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_RING10_TQM_RING_PG_SIZE_SFT \
17926 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_RING10_TQM_RING_PG_SIZE_PG_4K \
17927 (UINT32_C(0x0) << 4)
17929 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_RING10_TQM_RING_PG_SIZE_PG_8K \
17930 (UINT32_C(0x1) << 4)
17932 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_RING10_TQM_RING_PG_SIZE_PG_64K \
17933 (UINT32_C(0x2) << 4)
17935 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_RING10_TQM_RING_PG_SIZE_PG_2M \
17936 (UINT32_C(0x3) << 4)
17938 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_RING10_TQM_RING_PG_SIZE_PG_8M \
17939 (UINT32_C(0x4) << 4)
17941 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_RING10_TQM_RING_PG_SIZE_PG_1G \
17942 (UINT32_C(0x5) << 4)
17943 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_RING10_TQM_RING_PG_SIZE_LAST \
17944 HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_RING10_TQM_RING_PG_SIZE_PG_1G
17945 uint8_t ring10_unused[3];
17946 /* Number of TQM ring entries. */
17947 uint32_t tqm_ring10_num_entries;
17948 /* TQM ring page directory. */
17949 uint64_t tqm_ring10_page_dir;
17950 /* Number of Tx KTLS context entries. */
17951 uint32_t tkc_num_entries;
17952 /* Number of Rx KTLS context entries. */
17953 uint32_t rkc_num_entries;
17954 /* Tx KTLS context page directory. */
17955 uint64_t tkc_page_dir;
17956 /* Rx KTLS context page directory. */
17957 uint64_t rkc_page_dir;
17958 /* Tx KTLS context page size and level. */
17959 uint8_t tkc_pg_size_tkc_lvl;
17960 /* Tx KTLS context PBL indirect levels. */
17961 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TKC_LVL_MASK \
17963 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TKC_LVL_SFT 0
17964 /* PBL pointer is physical start address. */
17965 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TKC_LVL_LVL_0 \
17967 /* PBL pointer points to PTE table. */
17968 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TKC_LVL_LVL_1 \
17971 * PBL pointer points to PDE table with each entry pointing to
17974 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TKC_LVL_LVL_2 \
17976 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TKC_LVL_LAST \
17977 HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TKC_LVL_LVL_2
17978 /* Tx KTLS context page size. */
17979 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TKC_PG_SIZE_MASK \
17981 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TKC_PG_SIZE_SFT 4
17983 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TKC_PG_SIZE_PG_4K \
17984 (UINT32_C(0x0) << 4)
17986 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TKC_PG_SIZE_PG_8K \
17987 (UINT32_C(0x1) << 4)
17989 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TKC_PG_SIZE_PG_64K \
17990 (UINT32_C(0x2) << 4)
17992 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TKC_PG_SIZE_PG_2M \
17993 (UINT32_C(0x3) << 4)
17995 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TKC_PG_SIZE_PG_8M \
17996 (UINT32_C(0x4) << 4)
17998 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TKC_PG_SIZE_PG_1G \
17999 (UINT32_C(0x5) << 4)
18000 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TKC_PG_SIZE_LAST \
18001 HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TKC_PG_SIZE_PG_1G
18002 /* Rx KTLS context page size and level. */
18003 uint8_t rkc_pg_size_rkc_lvl;
18004 /* Rx KTLS context PBL indirect levels. */
18005 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_RKC_LVL_MASK \
18007 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_RKC_LVL_SFT 0
18008 /* PBL pointer is physical start address. */
18009 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_RKC_LVL_LVL_0 \
18011 /* PBL pointer points to PTE table. */
18012 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_RKC_LVL_LVL_1 \
18015 * PBL pointer points to PDE table with each entry pointing to
18018 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_RKC_LVL_LVL_2 \
18020 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_RKC_LVL_LAST \
18021 HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_RKC_LVL_LVL_2
18022 /* Rx KTLS context page size. */
18023 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_RKC_PG_SIZE_MASK \
18025 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_RKC_PG_SIZE_SFT 4
18027 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_RKC_PG_SIZE_PG_4K \
18028 (UINT32_C(0x0) << 4)
18030 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_RKC_PG_SIZE_PG_8K \
18031 (UINT32_C(0x1) << 4)
18033 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_RKC_PG_SIZE_PG_64K \
18034 (UINT32_C(0x2) << 4)
18036 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_RKC_PG_SIZE_PG_2M \
18037 (UINT32_C(0x3) << 4)
18039 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_RKC_PG_SIZE_PG_8M \
18040 (UINT32_C(0x4) << 4)
18042 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_RKC_PG_SIZE_PG_1G \
18043 (UINT32_C(0x5) << 4)
18044 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_RKC_PG_SIZE_LAST \
18045 HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_RKC_PG_SIZE_PG_1G
18046 uint8_t unused_1[5];
18048 * This field is used in Output records to indicate that the output
18049 * is completely written to RAM. This field should be read as 1
18050 * to indicate that the output has been completely written.
18051 * When writing a command completion or response to an internal
18052 * processor, the order of writes has to be such that this field
18058 /****************************
18059 * hwrm_error_recovery_qcfg *
18060 ****************************/
18063 /* hwrm_error_recovery_qcfg_input (size:192b/24B) */
18064 struct hwrm_error_recovery_qcfg_input {
18065 /* The HWRM command request type. */
18068 * The completion ring to send the completion event on. This should
18069 * be the NQ ID returned from the `nq_alloc` HWRM command.
18071 uint16_t cmpl_ring;
18073 * The sequence ID is used by the driver for tracking multiple
18074 * commands. This ID is treated as opaque data by the firmware and
18075 * the value is returned in the `hwrm_resp_hdr` upon completion.
18079 * The target ID of the command:
18080 * * 0x0-0xFFF8 - The function ID
18081 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
18082 * * 0xFFFD - Reserved for user-space HWRM interface
18085 uint16_t target_id;
18087 * A physical address pointer pointing to a host buffer that the
18088 * command's response data will be written. This can be either a host
18089 * physical address (HPA) or a guest physical address (GPA) and must
18090 * point to a physically contiguous block of memory.
18092 uint64_t resp_addr;
18093 uint8_t unused_0[8];
18096 /* hwrm_error_recovery_qcfg_output (size:1664b/208B) */
18097 struct hwrm_error_recovery_qcfg_output {
18098 /* The specific error status for the command. */
18099 uint16_t error_code;
18100 /* The HWRM command request type. */
18102 /* The sequence ID from the original command. */
18104 /* The length of the response data in number of bytes. */
18108 * When this flag is set to 1, error recovery will be initiated
18109 * through master function driver.
18111 #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FLAGS_HOST UINT32_C(0x1)
18113 * When this flag is set to 1, error recovery will be performed
18114 * through Co processor.
18116 #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FLAGS_CO_CPU UINT32_C(0x2)
18118 * Driver Polling frequency. This value is in units of 100msec.
18119 * Typical value would be 10 to indicate 1sec.
18120 * Drivers can poll FW health status, Heartbeat, reset_counter with
18123 uint32_t driver_polling_freq;
18125 * This value is in units of 100msec.
18126 * Typical value would be 30 to indicate 3sec.
18127 * Master function wait period from detecting a fatal error to
18128 * initiating reset. In this time period Master PF expects every
18129 * active driver will detect fatal error.
18131 uint32_t master_func_wait_period;
18133 * This value is in units of 100msec.
18134 * Typical value would be 50 to indicate 5sec.
18135 * Normal function wait period from fatal error detection to
18136 * polling FW health status. In this time period, drivers should not
18137 * do any PCIe MMIO transaction and should not send any HWRM commands.
18139 uint32_t normal_func_wait_period;
18141 * This value is in units of 100msec.
18142 * Typical value would be 20 to indicate 2sec.
18143 * This field indicates that, master function wait period after chip
18144 * reset. After this time, master function should reinitialize with
18147 uint32_t master_func_wait_period_after_reset;
18149 * This value is in units of 100msec.
18150 * Typical value would be 60 to indicate 6sec.
18151 * This field is applicable to both master and normal functions.
18152 * Even after chip reset, if FW status not changed to ready,
18153 * then all the functions can poll for this much time and bailout.
18155 uint32_t max_bailout_time_after_reset;
18157 * FW health status register.
18158 * Lower 2 bits indicates address space location and upper 30 bits
18159 * indicates upper 30bits of the register address.
18160 * A value of 0xFFFF-FFFF indicates this register does not exist.
18162 uint32_t fw_health_status_reg;
18163 /* Lower 2 bits indicates address space location. */
18164 #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FW_HEALTH_STATUS_REG_ADDR_SPACE_MASK \
18166 #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FW_HEALTH_STATUS_REG_ADDR_SPACE_SFT \
18169 * If value is 0, this register is located in PCIe config space.
18170 * Drivers have to map appropriate window to access this
18173 #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FW_HEALTH_STATUS_REG_ADDR_SPACE_PCIE_CFG \
18176 * If value is 1, this register is located in GRC address space.
18177 * Drivers have to map appropriate window to access this
18180 #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FW_HEALTH_STATUS_REG_ADDR_SPACE_GRC \
18183 * If value is 2, this register is located in first BAR address
18184 * space. Drivers have to map appropriate window to access this
18187 #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FW_HEALTH_STATUS_REG_ADDR_SPACE_BAR0 \
18190 * If value is 3, this register is located in second BAR address
18191 * space. Drivers have to map appropriate window to access this
18192 * Drivers have to map appropriate window to access this
18195 #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FW_HEALTH_STATUS_REG_ADDR_SPACE_BAR1 \
18197 #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FW_HEALTH_STATUS_REG_ADDR_SPACE_LAST \
18198 HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FW_HEALTH_STATUS_REG_ADDR_SPACE_BAR1
18199 /* Upper 30bits of the register address. */
18200 #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FW_HEALTH_STATUS_REG_ADDR_MASK \
18201 UINT32_C(0xfffffffc)
18202 #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FW_HEALTH_STATUS_REG_ADDR_SFT \
18205 * FW HeartBeat register.
18206 * Lower 2 bits indicates address space location and upper 30 bits
18207 * indicates actual address.
18208 * A value of 0xFFFF-FFFF indicates this register does not exist.
18210 uint32_t fw_heartbeat_reg;
18211 /* Lower 2 bits indicates address space location. */
18212 #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FW_HEARTBEAT_REG_ADDR_SPACE_MASK \
18214 #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FW_HEARTBEAT_REG_ADDR_SPACE_SFT \
18217 * If value is 0, this register is located in PCIe config space.
18218 * Drivers have to map appropriate window to access this
18221 #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FW_HEARTBEAT_REG_ADDR_SPACE_PCIE_CFG \
18224 * If value is 1, this register is located in GRC address space.
18225 * Drivers have to map appropriate window to access this
18228 #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FW_HEARTBEAT_REG_ADDR_SPACE_GRC \
18231 * If value is 2, this register is located in first BAR address
18232 * space. Drivers have to map appropriate window to access this
18235 #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FW_HEARTBEAT_REG_ADDR_SPACE_BAR0 \
18238 * If value is 3, this register is located in second BAR address
18239 * space. Drivers have to map appropriate window to access this
18242 #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FW_HEARTBEAT_REG_ADDR_SPACE_BAR1 \
18244 #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FW_HEARTBEAT_REG_ADDR_SPACE_LAST \
18245 HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FW_HEARTBEAT_REG_ADDR_SPACE_BAR1
18246 /* Upper 30bits of the register address. */
18247 #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FW_HEARTBEAT_REG_ADDR_MASK \
18248 UINT32_C(0xfffffffc)
18249 #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FW_HEARTBEAT_REG_ADDR_SFT \
18252 * FW reset counter.
18253 * Lower 2 bits indicates address space location and upper 30 bits
18254 * indicates actual address.
18255 * A value of 0xFFFF-FFFF indicates this register does not exist.
18257 uint32_t fw_reset_cnt_reg;
18258 /* Lower 2 bits indicates address space location. */
18259 #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FW_RESET_CNT_REG_ADDR_SPACE_MASK \
18261 #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FW_RESET_CNT_REG_ADDR_SPACE_SFT \
18264 * If value is 0, this register is located in PCIe config space.
18265 * Drivers have to map appropriate window to access this
18268 #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FW_RESET_CNT_REG_ADDR_SPACE_PCIE_CFG \
18271 * If value is 1, this register is located in GRC address space.
18272 * Drivers have to map appropriate window to access this
18275 #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FW_RESET_CNT_REG_ADDR_SPACE_GRC \
18278 * If value is 2, this register is located in first BAR address
18279 * space. Drivers have to map appropriate window to access this
18282 #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FW_RESET_CNT_REG_ADDR_SPACE_BAR0 \
18285 * If value is 3, this register is located in second BAR address
18286 * space. Drivers have to map appropriate window to access this
18289 #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FW_RESET_CNT_REG_ADDR_SPACE_BAR1 \
18291 #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FW_RESET_CNT_REG_ADDR_SPACE_LAST \
18292 HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FW_RESET_CNT_REG_ADDR_SPACE_BAR1
18293 /* Upper 30bits of the register address. */
18294 #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FW_RESET_CNT_REG_ADDR_MASK \
18295 UINT32_C(0xfffffffc)
18296 #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FW_RESET_CNT_REG_ADDR_SFT \
18299 * Reset Inprogress Register address for PFs.
18300 * Lower 2 bits indicates address space location and upper 30 bits
18301 * indicates actual address.
18302 * A value of 0xFFFF-FFFF indicates this register does not exist.
18304 uint32_t reset_inprogress_reg;
18305 /* Lower 2 bits indicates address space location. */
18306 #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_RESET_INPROGRESS_REG_ADDR_SPACE_MASK \
18308 #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_RESET_INPROGRESS_REG_ADDR_SPACE_SFT \
18311 * If value is 0, this register is located in PCIe config space.
18312 * Drivers have to map appropriate window to access this
18315 #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_RESET_INPROGRESS_REG_ADDR_SPACE_PCIE_CFG \
18318 * If value is 1, this register is located in GRC address space.
18319 * Drivers have to map appropriate window to access this
18322 #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_RESET_INPROGRESS_REG_ADDR_SPACE_GRC \
18325 * If value is 2, this register is located in first BAR address
18326 * space. Drivers have to map appropriate window to access this
18329 #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_RESET_INPROGRESS_REG_ADDR_SPACE_BAR0 \
18332 * If value is 3, this register is located in second BAR address
18333 * space. Drivers have to map appropriate window to access this
18336 #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_RESET_INPROGRESS_REG_ADDR_SPACE_BAR1 \
18338 #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_RESET_INPROGRESS_REG_ADDR_SPACE_LAST \
18339 HWRM_ERROR_RECOVERY_QCFG_OUTPUT_RESET_INPROGRESS_REG_ADDR_SPACE_BAR1
18340 /* Upper 30bits of the register address. */
18341 #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_RESET_INPROGRESS_REG_ADDR_MASK \
18342 UINT32_C(0xfffffffc)
18343 #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_RESET_INPROGRESS_REG_ADDR_SFT \
18345 /* This field indicates the mask value for reset_inprogress_reg. */
18346 uint32_t reset_inprogress_reg_mask;
18347 uint8_t unused_0[3];
18349 * Array of registers and value count to reset the Chip
18350 * Each array count has reset_reg, reset_reg_val, delay_after_reset
18351 * in TLV format. Depending upon Chip type, number of reset registers
18352 * will vary. Drivers have to write reset_reg_val in the reset_reg
18353 * location in the same sequence in order to recover from a fatal
18356 uint8_t reg_array_cnt;
18359 * Lower 2 bits indicates address space location and upper 30 bits
18360 * indicates actual address.
18361 * A value of 0xFFFF-FFFF indicates this register does not exist.
18363 uint32_t reset_reg[16];
18364 /* Lower 2 bits indicates address space location. */
18365 #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_RESET_REG_ADDR_SPACE_MASK \
18367 #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_RESET_REG_ADDR_SPACE_SFT 0
18369 * If value is 0, this register is located in PCIe config space.
18370 * Drivers have to map appropriate window to access this
18373 #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_RESET_REG_ADDR_SPACE_PCIE_CFG \
18376 * If value is 1, this register is located in GRC address space.
18377 * Drivers have to map appropriate window to access this
18380 #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_RESET_REG_ADDR_SPACE_GRC \
18383 * If value is 2, this register is located in first BAR address
18384 * space. Drivers have to map appropriate window to access this
18387 #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_RESET_REG_ADDR_SPACE_BAR0 \
18390 * If value is 3, this register is located in second BAR address
18391 * space. Drivers have to map appropriate window to access this
18394 #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_RESET_REG_ADDR_SPACE_BAR1 \
18396 #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_RESET_REG_ADDR_SPACE_LAST \
18397 HWRM_ERROR_RECOVERY_QCFG_OUTPUT_RESET_REG_ADDR_SPACE_BAR1
18398 /* Upper 30bits of the register address. */
18399 #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_RESET_REG_ADDR_MASK \
18400 UINT32_C(0xfffffffc)
18401 #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_RESET_REG_ADDR_SFT 2
18402 /* Value to be written in reset_reg to reset the controller. */
18403 uint32_t reset_reg_val[16];
18405 * This value is in units of 1msec.
18406 * Typical value would be 10 to indicate 10msec.
18407 * Some of the operations like Core reset require delay before
18408 * accessing PCIE MMIO register space.
18409 * If this value is non-zero, drivers have to wait for
18410 * this much time after writing reset_reg_val in reset_reg.
18412 uint8_t delay_after_reset[16];
18414 * Error recovery counter.
18415 * Lower 2 bits indicates address space location and upper 30 bits
18416 * indicates actual address.
18417 * A value of 0xFFFF-FFFF indicates this register does not exist.
18419 uint32_t err_recovery_cnt_reg;
18420 /* Lower 2 bits indicates address space location. */
18421 #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_ERR_RECOVERY_CNT_REG_ADDR_SPACE_MASK \
18423 #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_ERR_RECOVERY_CNT_REG_ADDR_SPACE_SFT \
18426 * If value is 0, this register is located in PCIe config space.
18427 * Drivers have to map appropriate window to access this
18430 #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_ERR_RECOVERY_CNT_REG_ADDR_SPACE_PCIE_CFG \
18433 * If value is 1, this register is located in GRC address space.
18434 * Drivers have to map appropriate window to access this
18437 #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_ERR_RECOVERY_CNT_REG_ADDR_SPACE_GRC \
18440 * If value is 2, this register is located in first BAR address
18441 * space. Drivers have to map appropriate window to access this
18444 #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_ERR_RECOVERY_CNT_REG_ADDR_SPACE_BAR0 \
18447 * If value is 3, this register is located in second BAR address
18448 * space. Drivers have to map appropriate window to access this
18451 #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_ERR_RECOVERY_CNT_REG_ADDR_SPACE_BAR1 \
18453 #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_ERR_RECOVERY_CNT_REG_ADDR_SPACE_LAST \
18454 HWRM_ERROR_RECOVERY_QCFG_OUTPUT_ERR_RECOVERY_CNT_REG_ADDR_SPACE_BAR1
18455 /* Upper 30bits of the register address. */
18456 #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_ERR_RECOVERY_CNT_REG_ADDR_MASK \
18457 UINT32_C(0xfffffffc)
18458 #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_ERR_RECOVERY_CNT_REG_ADDR_SFT \
18460 uint8_t unused_1[3];
18462 * This field is used in Output records to indicate that the output
18463 * is completely written to RAM. This field should be read as '1'
18464 * to indicate that the output has been completely written.
18465 * When writing a command completion or response to an internal
18466 * processor, the order of writes has to be such that this field
18472 /***************************
18473 * hwrm_func_echo_response *
18474 ***************************/
18477 /* hwrm_func_echo_response_input (size:192b/24B) */
18478 struct hwrm_func_echo_response_input {
18479 /* The HWRM command request type. */
18482 * The completion ring to send the completion event on. This should
18483 * be the NQ ID returned from the `nq_alloc` HWRM command.
18485 uint16_t cmpl_ring;
18487 * The sequence ID is used by the driver for tracking multiple
18488 * commands. This ID is treated as opaque data by the firmware and
18489 * the value is returned in the `hwrm_resp_hdr` upon completion.
18493 * The target ID of the command:
18494 * * 0x0-0xFFF8 - The function ID
18495 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
18496 * * 0xFFFD - Reserved for user-space HWRM interface
18499 uint16_t target_id;
18501 * A physical address pointer pointing to a host buffer that the
18502 * command's response data will be written. This can be either a host
18503 * physical address (HPA) or a guest physical address (GPA) and must
18504 * point to a physically contiguous block of memory.
18506 uint64_t resp_addr;
18507 uint32_t event_data1;
18508 uint32_t event_data2;
18511 /* hwrm_func_echo_response_output (size:128b/16B) */
18512 struct hwrm_func_echo_response_output {
18513 /* The specific error status for the command. */
18514 uint16_t error_code;
18515 /* The HWRM command request type. */
18517 /* The sequence ID from the original command. */
18519 /* The length of the response data in number of bytes. */
18521 uint8_t unused_0[7];
18523 * This field is used in Output records to indicate that the output
18524 * is completely written to RAM. This field should be read as '1'
18525 * to indicate that the output has been completely written.
18526 * When writing a command completion or response to an internal processor,
18527 * the order of writes has to be such that this field is written last.
18532 /**************************
18533 * hwrm_func_ptp_pin_qcfg *
18534 **************************/
18537 /* hwrm_func_ptp_pin_qcfg_input (size:192b/24B) */
18538 struct hwrm_func_ptp_pin_qcfg_input {
18539 /* The HWRM command request type. */
18542 * The completion ring to send the completion event on. This should
18543 * be the NQ ID returned from the `nq_alloc` HWRM command.
18545 uint16_t cmpl_ring;
18547 * The sequence ID is used by the driver for tracking multiple
18548 * commands. This ID is treated as opaque data by the firmware and
18549 * the value is returned in the `hwrm_resp_hdr` upon completion.
18553 * The target ID of the command:
18554 * * 0x0-0xFFF8 - The function ID
18555 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
18556 * * 0xFFFD - Reserved for user-space HWRM interface
18559 uint16_t target_id;
18561 * A physical address pointer pointing to a host buffer that the
18562 * command's response data will be written. This can be either a host
18563 * physical address (HPA) or a guest physical address (GPA) and must
18564 * point to a physically contiguous block of memory.
18566 uint64_t resp_addr;
18567 uint8_t unused_0[8];
18570 /* hwrm_func_ptp_pin_qcfg_output (size:128b/16B) */
18571 struct hwrm_func_ptp_pin_qcfg_output {
18572 /* The specific error status for the command. */
18573 uint16_t error_code;
18574 /* The HWRM command request type. */
18576 /* The sequence ID from the original command. */
18578 /* The length of the response data in number of bytes. */
18581 * The number of TSIO pins that are configured on this board
18582 * Up to 4 pins can be returned in the response.
18588 * When this bit is '1', TSIO pin 0 is enabled.
18589 * When this bit is '0', TSIO pin 0 is disabled.
18591 #define HWRM_FUNC_PTP_PIN_QCFG_OUTPUT_STATE_PIN0_ENABLED \
18594 * When this bit is '1', TSIO pin 1 is enabled.
18595 * When this bit is '0', TSIO pin 1 is disabled.
18597 #define HWRM_FUNC_PTP_PIN_QCFG_OUTPUT_STATE_PIN1_ENABLED \
18600 * When this bit is '1', TSIO pin 2 is enabled.
18601 * When this bit is '0', TSIO pin 2 is disabled.
18603 #define HWRM_FUNC_PTP_PIN_QCFG_OUTPUT_STATE_PIN2_ENABLED \
18606 * When this bit is '1', TSIO pin 3 is enabled.
18607 * When this bit is '0', TSIO pin 3 is disabled.
18609 #define HWRM_FUNC_PTP_PIN_QCFG_OUTPUT_STATE_PIN3_ENABLED \
18611 /* Type of function for Pin #0. */
18612 uint8_t pin0_usage;
18613 /* No function is configured. */
18614 #define HWRM_FUNC_PTP_PIN_QCFG_OUTPUT_PIN0_USAGE_NONE UINT32_C(0x0)
18615 /* PPS IN is configured. */
18616 #define HWRM_FUNC_PTP_PIN_QCFG_OUTPUT_PIN0_USAGE_PPS_IN UINT32_C(0x1)
18617 /* PPS OUT is configured. */
18618 #define HWRM_FUNC_PTP_PIN_QCFG_OUTPUT_PIN0_USAGE_PPS_OUT UINT32_C(0x2)
18619 /* SYNC IN is configured. */
18620 #define HWRM_FUNC_PTP_PIN_QCFG_OUTPUT_PIN0_USAGE_SYNC_IN UINT32_C(0x3)
18621 /* SYNC OUT is configured. */
18622 #define HWRM_FUNC_PTP_PIN_QCFG_OUTPUT_PIN0_USAGE_SYNC_OUT UINT32_C(0x4)
18623 #define HWRM_FUNC_PTP_PIN_QCFG_OUTPUT_PIN0_USAGE_LAST \
18624 HWRM_FUNC_PTP_PIN_QCFG_OUTPUT_PIN0_USAGE_SYNC_OUT
18625 /* Type of function for Pin #1. */
18626 uint8_t pin1_usage;
18627 /* No function is configured. */
18628 #define HWRM_FUNC_PTP_PIN_QCFG_OUTPUT_PIN1_USAGE_NONE UINT32_C(0x0)
18629 /* PPS IN is configured. */
18630 #define HWRM_FUNC_PTP_PIN_QCFG_OUTPUT_PIN1_USAGE_PPS_IN UINT32_C(0x1)
18631 /* PPS OUT is configured. */
18632 #define HWRM_FUNC_PTP_PIN_QCFG_OUTPUT_PIN1_USAGE_PPS_OUT UINT32_C(0x2)
18633 /* SYNC IN is configured. */
18634 #define HWRM_FUNC_PTP_PIN_QCFG_OUTPUT_PIN1_USAGE_SYNC_IN UINT32_C(0x3)
18635 /* SYNC OUT is configured. */
18636 #define HWRM_FUNC_PTP_PIN_QCFG_OUTPUT_PIN1_USAGE_SYNC_OUT UINT32_C(0x4)
18637 #define HWRM_FUNC_PTP_PIN_QCFG_OUTPUT_PIN1_USAGE_LAST \
18638 HWRM_FUNC_PTP_PIN_QCFG_OUTPUT_PIN1_USAGE_SYNC_OUT
18639 /* Type of function for Pin #2. */
18640 uint8_t pin2_usage;
18641 /* No function is configured. */
18642 #define HWRM_FUNC_PTP_PIN_QCFG_OUTPUT_PIN2_USAGE_NONE UINT32_C(0x0)
18643 /* PPS IN is configured. */
18644 #define HWRM_FUNC_PTP_PIN_QCFG_OUTPUT_PIN2_USAGE_PPS_IN UINT32_C(0x1)
18645 /* PPS OUT is configured. */
18646 #define HWRM_FUNC_PTP_PIN_QCFG_OUTPUT_PIN2_USAGE_PPS_OUT UINT32_C(0x2)
18647 /* SYNC IN is configured. */
18648 #define HWRM_FUNC_PTP_PIN_QCFG_OUTPUT_PIN2_USAGE_SYNC_IN UINT32_C(0x3)
18649 /* SYNC OUT is configured. */
18650 #define HWRM_FUNC_PTP_PIN_QCFG_OUTPUT_PIN2_USAGE_SYNC_OUT UINT32_C(0x4)
18651 #define HWRM_FUNC_PTP_PIN_QCFG_OUTPUT_PIN2_USAGE_LAST \
18652 HWRM_FUNC_PTP_PIN_QCFG_OUTPUT_PIN2_USAGE_SYNC_OUT
18653 /* Type of function for Pin #3. */
18654 uint8_t pin3_usage;
18655 /* No function is configured. */
18656 #define HWRM_FUNC_PTP_PIN_QCFG_OUTPUT_PIN3_USAGE_NONE UINT32_C(0x0)
18657 /* PPS IN is configured. */
18658 #define HWRM_FUNC_PTP_PIN_QCFG_OUTPUT_PIN3_USAGE_PPS_IN UINT32_C(0x1)
18659 /* PPS OUT is configured. */
18660 #define HWRM_FUNC_PTP_PIN_QCFG_OUTPUT_PIN3_USAGE_PPS_OUT UINT32_C(0x2)
18661 /* SYNC IN is configured. */
18662 #define HWRM_FUNC_PTP_PIN_QCFG_OUTPUT_PIN3_USAGE_SYNC_IN UINT32_C(0x3)
18663 /* SYNC OUT is configured. */
18664 #define HWRM_FUNC_PTP_PIN_QCFG_OUTPUT_PIN3_USAGE_SYNC_OUT UINT32_C(0x4)
18665 #define HWRM_FUNC_PTP_PIN_QCFG_OUTPUT_PIN3_USAGE_LAST \
18666 HWRM_FUNC_PTP_PIN_QCFG_OUTPUT_PIN3_USAGE_SYNC_OUT
18669 * This field is used in Output records to indicate that the output
18670 * is completely written to RAM. This field should be read as '1'
18671 * to indicate that the output has been completely written.
18672 * When writing a command completion or response to an internal processor,
18673 * the order of writes has to be such that this field is written last.
18678 /*************************
18679 * hwrm_func_ptp_pin_cfg *
18680 *************************/
18683 /* hwrm_func_ptp_pin_cfg_input (size:256b/32B) */
18684 struct hwrm_func_ptp_pin_cfg_input {
18685 /* The HWRM command request type. */
18688 * The completion ring to send the completion event on. This should
18689 * be the NQ ID returned from the `nq_alloc` HWRM command.
18691 uint16_t cmpl_ring;
18693 * The sequence ID is used by the driver for tracking multiple
18694 * commands. This ID is treated as opaque data by the firmware and
18695 * the value is returned in the `hwrm_resp_hdr` upon completion.
18699 * The target ID of the command:
18700 * * 0x0-0xFFF8 - The function ID
18701 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
18702 * * 0xFFFD - Reserved for user-space HWRM interface
18705 uint16_t target_id;
18707 * A physical address pointer pointing to a host buffer that the
18708 * command's response data will be written. This can be either a host
18709 * physical address (HPA) or a guest physical address (GPA) and must
18710 * point to a physically contiguous block of memory.
18712 uint64_t resp_addr;
18715 * This bit must be '1' for the pin0_state field to be
18718 #define HWRM_FUNC_PTP_PIN_CFG_INPUT_ENABLES_PIN0_STATE \
18721 * This bit must be '1' for the pin0_usage field to be
18724 #define HWRM_FUNC_PTP_PIN_CFG_INPUT_ENABLES_PIN0_USAGE \
18727 * This bit must be '1' for the pin1_state field to be
18730 #define HWRM_FUNC_PTP_PIN_CFG_INPUT_ENABLES_PIN1_STATE \
18733 * This bit must be '1' for the pin1_usage field to be
18736 #define HWRM_FUNC_PTP_PIN_CFG_INPUT_ENABLES_PIN1_USAGE \
18739 * This bit must be '1' for the pin2_state field to be
18742 #define HWRM_FUNC_PTP_PIN_CFG_INPUT_ENABLES_PIN2_STATE \
18745 * This bit must be '1' for the pin2_usage field to be
18748 #define HWRM_FUNC_PTP_PIN_CFG_INPUT_ENABLES_PIN2_USAGE \
18751 * This bit must be '1' for the pin3_state field to be
18754 #define HWRM_FUNC_PTP_PIN_CFG_INPUT_ENABLES_PIN3_STATE \
18757 * This bit must be '1' for the pin3_usage field to be
18760 #define HWRM_FUNC_PTP_PIN_CFG_INPUT_ENABLES_PIN3_USAGE \
18762 /* Enable or disable functionality of Pin #0. */
18763 uint8_t pin0_state;
18765 #define HWRM_FUNC_PTP_PIN_CFG_INPUT_PIN0_STATE_DISABLED UINT32_C(0x0)
18767 #define HWRM_FUNC_PTP_PIN_CFG_INPUT_PIN0_STATE_ENABLED UINT32_C(0x1)
18768 #define HWRM_FUNC_PTP_PIN_CFG_INPUT_PIN0_STATE_LAST \
18769 HWRM_FUNC_PTP_PIN_CFG_INPUT_PIN0_STATE_ENABLED
18770 /* Configure function for TSIO pin#0. */
18771 uint8_t pin0_usage;
18772 /* No function is configured. */
18773 #define HWRM_FUNC_PTP_PIN_CFG_INPUT_PIN0_USAGE_NONE UINT32_C(0x0)
18774 /* PPS IN is configured. */
18775 #define HWRM_FUNC_PTP_PIN_CFG_INPUT_PIN0_USAGE_PPS_IN UINT32_C(0x1)
18776 /* PPS OUT is configured. */
18777 #define HWRM_FUNC_PTP_PIN_CFG_INPUT_PIN0_USAGE_PPS_OUT UINT32_C(0x2)
18778 /* SYNC IN is configured. */
18779 #define HWRM_FUNC_PTP_PIN_CFG_INPUT_PIN0_USAGE_SYNC_IN UINT32_C(0x3)
18780 /* SYNC OUT is configured. */
18781 #define HWRM_FUNC_PTP_PIN_CFG_INPUT_PIN0_USAGE_SYNC_OUT UINT32_C(0x4)
18782 #define HWRM_FUNC_PTP_PIN_CFG_INPUT_PIN0_USAGE_LAST \
18783 HWRM_FUNC_PTP_PIN_CFG_INPUT_PIN0_USAGE_SYNC_OUT
18784 /* Enable or disable functionality of Pin #1. */
18785 uint8_t pin1_state;
18787 #define HWRM_FUNC_PTP_PIN_CFG_INPUT_PIN1_STATE_DISABLED UINT32_C(0x0)
18789 #define HWRM_FUNC_PTP_PIN_CFG_INPUT_PIN1_STATE_ENABLED UINT32_C(0x1)
18790 #define HWRM_FUNC_PTP_PIN_CFG_INPUT_PIN1_STATE_LAST \
18791 HWRM_FUNC_PTP_PIN_CFG_INPUT_PIN1_STATE_ENABLED
18792 /* Configure function for TSIO pin#1. */
18793 uint8_t pin1_usage;
18794 /* No function is configured. */
18795 #define HWRM_FUNC_PTP_PIN_CFG_INPUT_PIN1_USAGE_NONE UINT32_C(0x0)
18796 /* PPS IN is configured. */
18797 #define HWRM_FUNC_PTP_PIN_CFG_INPUT_PIN1_USAGE_PPS_IN UINT32_C(0x1)
18798 /* PPS OUT is configured. */
18799 #define HWRM_FUNC_PTP_PIN_CFG_INPUT_PIN1_USAGE_PPS_OUT UINT32_C(0x2)
18800 /* SYNC IN is configured. */
18801 #define HWRM_FUNC_PTP_PIN_CFG_INPUT_PIN1_USAGE_SYNC_IN UINT32_C(0x3)
18802 /* SYNC OUT is configured. */
18803 #define HWRM_FUNC_PTP_PIN_CFG_INPUT_PIN1_USAGE_SYNC_OUT UINT32_C(0x4)
18804 #define HWRM_FUNC_PTP_PIN_CFG_INPUT_PIN1_USAGE_LAST \
18805 HWRM_FUNC_PTP_PIN_CFG_INPUT_PIN1_USAGE_SYNC_OUT
18806 /* Enable or disable functionality of Pin #2. */
18807 uint8_t pin2_state;
18809 #define HWRM_FUNC_PTP_PIN_CFG_INPUT_PIN2_STATE_DISABLED UINT32_C(0x0)
18811 #define HWRM_FUNC_PTP_PIN_CFG_INPUT_PIN2_STATE_ENABLED UINT32_C(0x1)
18812 #define HWRM_FUNC_PTP_PIN_CFG_INPUT_PIN2_STATE_LAST \
18813 HWRM_FUNC_PTP_PIN_CFG_INPUT_PIN2_STATE_ENABLED
18814 /* Configure function for TSIO pin#2. */
18815 uint8_t pin2_usage;
18816 /* No function is configured. */
18817 #define HWRM_FUNC_PTP_PIN_CFG_INPUT_PIN2_USAGE_NONE UINT32_C(0x0)
18818 /* PPS IN is configured. */
18819 #define HWRM_FUNC_PTP_PIN_CFG_INPUT_PIN2_USAGE_PPS_IN UINT32_C(0x1)
18820 /* PPS OUT is configured. */
18821 #define HWRM_FUNC_PTP_PIN_CFG_INPUT_PIN2_USAGE_PPS_OUT UINT32_C(0x2)
18822 /* SYNC IN is configured. */
18823 #define HWRM_FUNC_PTP_PIN_CFG_INPUT_PIN2_USAGE_SYNC_IN UINT32_C(0x3)
18824 /* SYNC OUT is configured. */
18825 #define HWRM_FUNC_PTP_PIN_CFG_INPUT_PIN2_USAGE_SYNC_OUT UINT32_C(0x4)
18826 #define HWRM_FUNC_PTP_PIN_CFG_INPUT_PIN2_USAGE_LAST \
18827 HWRM_FUNC_PTP_PIN_CFG_INPUT_PIN2_USAGE_SYNC_OUT
18828 /* Enable or disable functionality of Pin #3. */
18829 uint8_t pin3_state;
18831 #define HWRM_FUNC_PTP_PIN_CFG_INPUT_PIN3_STATE_DISABLED UINT32_C(0x0)
18833 #define HWRM_FUNC_PTP_PIN_CFG_INPUT_PIN3_STATE_ENABLED UINT32_C(0x1)
18834 #define HWRM_FUNC_PTP_PIN_CFG_INPUT_PIN3_STATE_LAST \
18835 HWRM_FUNC_PTP_PIN_CFG_INPUT_PIN3_STATE_ENABLED
18836 /* Configure function for TSIO pin#3. */
18837 uint8_t pin3_usage;
18838 /* No function is configured. */
18839 #define HWRM_FUNC_PTP_PIN_CFG_INPUT_PIN3_USAGE_NONE UINT32_C(0x0)
18840 /* PPS IN is configured. */
18841 #define HWRM_FUNC_PTP_PIN_CFG_INPUT_PIN3_USAGE_PPS_IN UINT32_C(0x1)
18842 /* PPS OUT is configured. */
18843 #define HWRM_FUNC_PTP_PIN_CFG_INPUT_PIN3_USAGE_PPS_OUT UINT32_C(0x2)
18844 /* SYNC IN is configured. */
18845 #define HWRM_FUNC_PTP_PIN_CFG_INPUT_PIN3_USAGE_SYNC_IN UINT32_C(0x3)
18846 /* SYNC OUT is configured. */
18847 #define HWRM_FUNC_PTP_PIN_CFG_INPUT_PIN3_USAGE_SYNC_OUT UINT32_C(0x4)
18848 #define HWRM_FUNC_PTP_PIN_CFG_INPUT_PIN3_USAGE_LAST \
18849 HWRM_FUNC_PTP_PIN_CFG_INPUT_PIN3_USAGE_SYNC_OUT
18850 uint8_t unused_0[4];
18853 /* hwrm_func_ptp_pin_cfg_output (size:128b/16B) */
18854 struct hwrm_func_ptp_pin_cfg_output {
18855 /* The specific error status for the command. */
18856 uint16_t error_code;
18857 /* The HWRM command request type. */
18859 /* The sequence ID from the original command. */
18861 /* The length of the response data in number of bytes. */
18863 uint8_t unused_0[7];
18865 * This field is used in Output records to indicate that the output
18866 * is completely written to RAM. This field should be read as '1'
18867 * to indicate that the output has been completely written.
18868 * When writing a command completion or response to an internal processor,
18869 * the order of writes has to be such that this field is written last.
18874 /*********************
18875 * hwrm_func_ptp_cfg *
18876 *********************/
18879 /* hwrm_func_ptp_cfg_input (size:320b/40B) */
18880 struct hwrm_func_ptp_cfg_input {
18881 /* The HWRM command request type. */
18884 * The completion ring to send the completion event on. This should
18885 * be the NQ ID returned from the `nq_alloc` HWRM command.
18887 uint16_t cmpl_ring;
18889 * The sequence ID is used by the driver for tracking multiple
18890 * commands. This ID is treated as opaque data by the firmware and
18891 * the value is returned in the `hwrm_resp_hdr` upon completion.
18895 * The target ID of the command:
18896 * * 0x0-0xFFF8 - The function ID
18897 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
18898 * * 0xFFFD - Reserved for user-space HWRM interface
18901 uint16_t target_id;
18903 * A physical address pointer pointing to a host buffer that the
18904 * command's response data will be written. This can be either a host
18905 * physical address (HPA) or a guest physical address (GPA) and must
18906 * point to a physically contiguous block of memory.
18908 uint64_t resp_addr;
18911 * This bit must be '1' for the ptp_pps_event field to be
18914 #define HWRM_FUNC_PTP_CFG_INPUT_ENABLES_PTP_PPS_EVENT \
18917 * This bit must be '1' for the ptp_freq_adj_dll_source field to be
18920 #define HWRM_FUNC_PTP_CFG_INPUT_ENABLES_PTP_FREQ_ADJ_DLL_SOURCE \
18923 * This bit must be '1' for the ptp_freq_adj_dll_phase field to be
18926 #define HWRM_FUNC_PTP_CFG_INPUT_ENABLES_PTP_FREQ_ADJ_DLL_PHASE \
18929 * This bit must be '1' for the ptp_freq_adj_ext_period field to be
18932 #define HWRM_FUNC_PTP_CFG_INPUT_ENABLES_PTP_FREQ_ADJ_EXT_PERIOD \
18935 * This bit must be '1' for the ptp_freq_adj_ext_up field to be
18938 #define HWRM_FUNC_PTP_CFG_INPUT_ENABLES_PTP_FREQ_ADJ_EXT_UP \
18941 * This bit must be '1' for the ptp_freq_adj_ext_phase field to be
18944 #define HWRM_FUNC_PTP_CFG_INPUT_ENABLES_PTP_FREQ_ADJ_EXT_PHASE \
18946 /* This field is used to enable interrupt for a specific PPS event. */
18947 uint8_t ptp_pps_event;
18949 * When this bit is set to '1', interrupt is enabled for internal
18950 * PPS event. Latches timestamp on PPS_OUT TSIO Pin. If user does
18951 * not configure PPS_OUT on a TSIO pin, then firmware will allocate
18952 * PPS_OUT to an unallocated pin.
18954 #define HWRM_FUNC_PTP_CFG_INPUT_PTP_PPS_EVENT_INTERNAL \
18957 * When this bit is set to '1', interrupt is enabled for external
18958 * PPS event. Latches timestamp on PPS_IN TSIO pin.
18960 #define HWRM_FUNC_PTP_CFG_INPUT_PTP_PPS_EVENT_EXTERNAL \
18963 * This field is used to set the source signal used to discipline
18964 * PHC (PTP Hardware Clock)
18966 uint8_t ptp_freq_adj_dll_source;
18967 /* No source is selected. Use servo to discipline PHC */
18968 #define HWRM_FUNC_PTP_CFG_INPUT_PTP_FREQ_ADJ_DLL_SOURCE_NONE \
18970 /* TSIO Pin #0 is selected as source signal. */
18971 #define HWRM_FUNC_PTP_CFG_INPUT_PTP_FREQ_ADJ_DLL_SOURCE_TSIO_0 \
18973 /* TSIO Pin #1 is selected as source signal. */
18974 #define HWRM_FUNC_PTP_CFG_INPUT_PTP_FREQ_ADJ_DLL_SOURCE_TSIO_1 \
18976 /* TSIO Pin #2 is selected as source signal. */
18977 #define HWRM_FUNC_PTP_CFG_INPUT_PTP_FREQ_ADJ_DLL_SOURCE_TSIO_2 \
18979 /* TSIO Pin #3 is selected as source signal. */
18980 #define HWRM_FUNC_PTP_CFG_INPUT_PTP_FREQ_ADJ_DLL_SOURCE_TSIO_3 \
18982 /* Port #0 is selected as source signal. */
18983 #define HWRM_FUNC_PTP_CFG_INPUT_PTP_FREQ_ADJ_DLL_SOURCE_PORT_0 \
18985 /* Port #1 is selected as source signal. */
18986 #define HWRM_FUNC_PTP_CFG_INPUT_PTP_FREQ_ADJ_DLL_SOURCE_PORT_1 \
18988 /* Port #2 is selected as source signal. */
18989 #define HWRM_FUNC_PTP_CFG_INPUT_PTP_FREQ_ADJ_DLL_SOURCE_PORT_2 \
18991 /* Port #3 is selected as source signal. */
18992 #define HWRM_FUNC_PTP_CFG_INPUT_PTP_FREQ_ADJ_DLL_SOURCE_PORT_3 \
18994 /* Invalid signal. */
18995 #define HWRM_FUNC_PTP_CFG_INPUT_PTP_FREQ_ADJ_DLL_SOURCE_INVALID \
18997 #define HWRM_FUNC_PTP_CFG_INPUT_PTP_FREQ_ADJ_DLL_SOURCE_LAST \
18998 HWRM_FUNC_PTP_CFG_INPUT_PTP_FREQ_ADJ_DLL_SOURCE_INVALID
19000 * This field is used to provide phase adjustment for DLL
19001 * used to discipline PHC (PTP Hardware clock)
19003 uint8_t ptp_freq_adj_dll_phase;
19004 /* No Phase adjustment. */
19005 #define HWRM_FUNC_PTP_CFG_INPUT_PTP_FREQ_ADJ_DLL_PHASE_NONE \
19007 /* 4Khz sync in frequency. */
19008 #define HWRM_FUNC_PTP_CFG_INPUT_PTP_FREQ_ADJ_DLL_PHASE_4K \
19010 /* 8Khz sync in frequency. */
19011 #define HWRM_FUNC_PTP_CFG_INPUT_PTP_FREQ_ADJ_DLL_PHASE_8K \
19013 /* 10Mhz sync in frequency. */
19014 #define HWRM_FUNC_PTP_CFG_INPUT_PTP_FREQ_ADJ_DLL_PHASE_10M \
19016 #define HWRM_FUNC_PTP_CFG_INPUT_PTP_FREQ_ADJ_DLL_PHASE_LAST \
19017 HWRM_FUNC_PTP_CFG_INPUT_PTP_FREQ_ADJ_DLL_PHASE_10M
19018 uint8_t unused_0[3];
19020 * Period in nanoseconds (ns) for external signal
19023 uint32_t ptp_freq_adj_ext_period;
19025 * Up time in nanoseconds (ns) of the duty cycle
19026 * of the external signal. This value should be
19027 * less than ptp_freq_adj_ext_period.
19029 uint32_t ptp_freq_adj_ext_up;
19031 * Phase value is provided. This field provides the
19032 * least significant 32 bits of the phase input. The
19033 * most significant 16 bits come from
19034 * ptp_freq_adj_ext_phase_upper field. Setting this
19035 * field requires setting ptp_freq_adj_ext_period
19036 * field as well to identify the external signal
19039 uint32_t ptp_freq_adj_ext_phase_lower;
19041 * Phase value is provided. The lower 16 bits of this field is used
19042 * with the 32 bit value from ptp_freq_adj_ext_phase_lower
19043 * to provide a 48 bit value input for Phase.
19045 uint32_t ptp_freq_adj_ext_phase_upper;
19048 /* hwrm_func_ptp_cfg_output (size:128b/16B) */
19049 struct hwrm_func_ptp_cfg_output {
19050 /* The specific error status for the command. */
19051 uint16_t error_code;
19052 /* The HWRM command request type. */
19054 /* The sequence ID from the original command. */
19056 /* The length of the response data in number of bytes. */
19058 uint8_t unused_0[7];
19060 * This field is used in Output records to indicate that the output
19061 * is completely written to RAM. This field should be read as '1'
19062 * to indicate that the output has been completely written.
19063 * When writing a command completion or response to an internal processor,
19064 * the order of writes has to be such that this field is written last.
19069 /**************************
19070 * hwrm_func_ptp_ts_query *
19071 **************************/
19074 /* hwrm_func_ptp_ts_query_input (size:192b/24B) */
19075 struct hwrm_func_ptp_ts_query_input {
19076 /* The HWRM command request type. */
19079 * The completion ring to send the completion event on. This should
19080 * be the NQ ID returned from the `nq_alloc` HWRM command.
19082 uint16_t cmpl_ring;
19084 * The sequence ID is used by the driver for tracking multiple
19085 * commands. This ID is treated as opaque data by the firmware and
19086 * the value is returned in the `hwrm_resp_hdr` upon completion.
19090 * The target ID of the command:
19091 * * 0x0-0xFFF8 - The function ID
19092 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
19093 * * 0xFFFD - Reserved for user-space HWRM interface
19096 uint16_t target_id;
19098 * A physical address pointer pointing to a host buffer that the
19099 * command's response data will be written. This can be either a host
19100 * physical address (HPA) or a guest physical address (GPA) and must
19101 * point to a physically contiguous block of memory.
19103 uint64_t resp_addr;
19105 /* If set, the response includes PPS event timestamps */
19106 #define HWRM_FUNC_PTP_TS_QUERY_INPUT_FLAGS_PPS_TIME UINT32_C(0x1)
19107 /* If set, the response includes PTM timestamps */
19108 #define HWRM_FUNC_PTP_TS_QUERY_INPUT_FLAGS_PTM_TIME UINT32_C(0x2)
19109 uint8_t unused_0[4];
19112 /* hwrm_func_ptp_ts_query_output (size:320b/40B) */
19113 struct hwrm_func_ptp_ts_query_output {
19114 /* The specific error status for the command. */
19115 uint16_t error_code;
19116 /* The HWRM command request type. */
19118 /* The sequence ID from the original command. */
19120 /* The length of the response data in number of bytes. */
19122 /* Timestamp value of last PPS event latched. */
19123 uint64_t pps_event_ts;
19124 /* PTM local timestamp value. */
19125 uint64_t ptm_res_local_ts;
19126 /* PTM Master timestamp value. */
19127 uint64_t ptm_pmstr_ts;
19128 /* PTM Master propagation delay */
19129 uint32_t ptm_mstr_prop_dly;
19130 uint8_t unused_0[3];
19132 * This field is used in Output records to indicate that the output
19133 * is completely written to RAM. This field should be read as '1'
19134 * to indicate that the output has been completely written.
19135 * When writing a command completion or response to an internal processor,
19136 * the order of writes has to be such that this field is written last.
19141 /*************************
19142 * hwrm_func_ptp_ext_cfg *
19143 *************************/
19146 /* hwrm_func_ptp_ext_cfg_input (size:256b/32B) */
19147 struct hwrm_func_ptp_ext_cfg_input {
19148 /* The HWRM command request type. */
19151 * The completion ring to send the completion event on. This should
19152 * be the NQ ID returned from the `nq_alloc` HWRM command.
19154 uint16_t cmpl_ring;
19156 * The sequence ID is used by the driver for tracking multiple
19157 * commands. This ID is treated as opaque data by the firmware and
19158 * the value is returned in the `hwrm_resp_hdr` upon completion.
19162 * The target ID of the command:
19163 * * 0x0-0xFFF8 - The function ID
19164 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
19165 * * 0xFFFD - Reserved for user-space HWRM interface
19168 uint16_t target_id;
19170 * A physical address pointer pointing to a host buffer that the
19171 * command's response data will be written. This can be either a host
19172 * physical address (HPA) or a guest physical address (GPA) and must
19173 * point to a physically contiguous block of memory.
19175 uint64_t resp_addr;
19178 * This bit must be '1' for the phc_master_fid field to be
19181 #define HWRM_FUNC_PTP_EXT_CFG_INPUT_ENABLES_PHC_MASTER_FID \
19184 * This bit must be '1' for the phc_sec_fid field to be
19187 #define HWRM_FUNC_PTP_EXT_CFG_INPUT_ENABLES_PHC_SEC_FID \
19190 * This bit must be '1' for the phc_sec_mode field to be
19193 #define HWRM_FUNC_PTP_EXT_CFG_INPUT_ENABLES_PHC_SEC_MODE \
19196 * This bit must be '1' for the failover_timer field to be
19199 #define HWRM_FUNC_PTP_EXT_CFG_INPUT_ENABLES_FAILOVER_TIMER \
19202 * This field is used to configure the Master function. Only this
19203 * function can modify or condition the PHC. Only driver calls from
19204 * this function are allowed to adjust frequency of PHC or configure
19205 * PPS functionality.
19206 * If driver does not specify this FID, then firmware will auto select
19207 * the first function that makes the call to modify PHC as the Master.
19209 uint16_t phc_master_fid;
19211 * This field is used to configure the secondary function. This
19212 * function becomes the Master function in case of failover from
19214 * If driver does not specify this FID, firmware will auto select
19215 * the last non-master function to make a call to condition PHC as
19218 uint16_t phc_sec_fid;
19220 * This field is used to configure conditions under which a function
19221 * can become a secondary function.
19223 uint8_t phc_sec_mode;
19225 * Immediately failover to the current secondary function. If there
19226 * is no secondary function available, failover does not happen.
19228 #define HWRM_FUNC_PTP_EXT_CFG_INPUT_PHC_SEC_MODE_SWITCH UINT32_C(0x0)
19230 * All functions (PF and VF) can be used during auto selection
19231 * of a secondary function. This is not used in case of admin
19232 * configured secondary function.
19234 #define HWRM_FUNC_PTP_EXT_CFG_INPUT_PHC_SEC_MODE_ALL UINT32_C(0x1)
19236 * Only PF's can be selected as a secondary function during auto
19237 * selection. This is not used in case of admin configured secondary
19240 #define HWRM_FUNC_PTP_EXT_CFG_INPUT_PHC_SEC_MODE_PF_ONLY UINT32_C(0x2)
19241 #define HWRM_FUNC_PTP_EXT_CFG_INPUT_PHC_SEC_MODE_LAST \
19242 HWRM_FUNC_PTP_EXT_CFG_INPUT_PHC_SEC_MODE_PF_ONLY
19245 * This field indicates the failover time is milliseconds. If the
19246 * timeout expires, firmware will failover PTP configurability from
19247 * current master to secondary fid.
19248 * 0 - Failover timer is automatically selected based on the last
19249 * adjFreq() call. If adjFreq() is not called for 3 * (last interval)
19250 * the failover kicks in. For example, if last interval between
19251 * adjFreq() calls was 2 seconds and the next adjFreq() is not made for
19252 * at least 6 seconds, then secondary takes over as master to condition
19253 * PHC. Firmware rounds up the failover timer to be a multiple of 250
19254 * ms. Firmware checks every 250 ms to see if timer expired.
19255 * 0xFFFFFFFF - If driver specifies this value, then failover never
19256 * happens. Admin or auto selected Master will always be used for
19257 * conditioning PHC.
19258 * X - If driver specifies any other value, this is admin indicated
19259 * failover timeout. If no adjFreq() call is made within this timeout
19260 * value, then failover happens. This value should be a multiple of
19261 * 250 ms. Firmware checks every 250 ms to see if timer expired.
19263 uint32_t failover_timer;
19264 uint8_t unused_1[4];
19267 /* hwrm_func_ptp_ext_cfg_output (size:128b/16B) */
19268 struct hwrm_func_ptp_ext_cfg_output {
19269 /* The specific error status for the command. */
19270 uint16_t error_code;
19271 /* The HWRM command request type. */
19273 /* The sequence ID from the original command. */
19275 /* The length of the response data in number of bytes. */
19277 uint8_t unused_0[7];
19279 * This field is used in Output records to indicate that the output
19280 * is completely written to RAM. This field should be read as '1'
19281 * to indicate that the output has been completely written.
19282 * When writing a command completion or response to an internal processor,
19283 * the order of writes has to be such that this field is written last.
19288 /**************************
19289 * hwrm_func_ptp_ext_qcfg *
19290 **************************/
19293 /* hwrm_func_ptp_ext_qcfg_input (size:192b/24B) */
19294 struct hwrm_func_ptp_ext_qcfg_input {
19295 /* The HWRM command request type. */
19298 * The completion ring to send the completion event on. This should
19299 * be the NQ ID returned from the `nq_alloc` HWRM command.
19301 uint16_t cmpl_ring;
19303 * The sequence ID is used by the driver for tracking multiple
19304 * commands. This ID is treated as opaque data by the firmware and
19305 * the value is returned in the `hwrm_resp_hdr` upon completion.
19309 * The target ID of the command:
19310 * * 0x0-0xFFF8 - The function ID
19311 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
19312 * * 0xFFFD - Reserved for user-space HWRM interface
19315 uint16_t target_id;
19317 * A physical address pointer pointing to a host buffer that the
19318 * command's response data will be written. This can be either a host
19319 * physical address (HPA) or a guest physical address (GPA) and must
19320 * point to a physically contiguous block of memory.
19322 uint64_t resp_addr;
19323 uint8_t unused_0[8];
19326 /* hwrm_func_ptp_ext_qcfg_output (size:256b/32B) */
19327 struct hwrm_func_ptp_ext_qcfg_output {
19328 /* The specific error status for the command. */
19329 uint16_t error_code;
19330 /* The HWRM command request type. */
19332 /* The sequence ID from the original command. */
19334 /* The length of the response data in number of bytes. */
19337 * Firmware returns the current PHC master function. This function
19338 * could either be admin selected or auto selected.
19340 uint16_t phc_master_fid;
19342 * Firmware returns the current PHC secondary function. This function
19343 * could either be admin selected or auto selected.
19345 uint16_t phc_sec_fid;
19347 * Firmware returns the last non-master/non-secondary function to
19348 * make a call to condition PHC.
19350 uint16_t phc_active_fid0;
19352 * Firmware returns the second last non-master/non-secondary function
19353 * to make a call to condition PHC.
19355 uint16_t phc_active_fid1;
19357 * Timestamp indicating the last time a failover happened. The master
19358 * and secondary functions in the failover event is indicated in the
19361 uint32_t last_failover_event;
19363 * Last failover happened from this function. This was the master
19364 * function at the time of failover.
19368 * Last failover happened to this function. This was the secondary
19369 * function at the time of failover.
19372 uint8_t unused_0[7];
19374 * This field is used in Output records to indicate that the output
19375 * is completely written to RAM. This field should be read as '1'
19376 * to indicate that the output has been completely written.
19377 * When writing a command completion or response to an internal processor,
19378 * the order of writes has to be such that this field is written last.
19383 /***************************
19384 * hwrm_func_key_ctx_alloc *
19385 ***************************/
19388 /* hwrm_func_key_ctx_alloc_input (size:320b/40B) */
19389 struct hwrm_func_key_ctx_alloc_input {
19390 /* The HWRM command request type. */
19393 * The completion ring to send the completion event on. This should
19394 * be the NQ ID returned from the `nq_alloc` HWRM command.
19396 uint16_t cmpl_ring;
19398 * The sequence ID is used by the driver for tracking multiple
19399 * commands. This ID is treated as opaque data by the firmware and
19400 * the value is returned in the `hwrm_resp_hdr` upon completion.
19404 * The target ID of the command:
19405 * * 0x0-0xFFF8 - The function ID
19406 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
19407 * * 0xFFFD - Reserved for user-space HWRM interface
19410 uint16_t target_id;
19412 * A physical address pointer pointing to a host buffer that the
19413 * command's response data will be written. This can be either a host
19414 * physical address (HPA) or a guest physical address (GPA) and must
19415 * point to a physically contiguous block of memory.
19417 uint64_t resp_addr;
19420 /* Number of Key Contexts to be allocated. */
19421 uint16_t num_key_ctxs;
19422 /* DMA buffer size in bytes. */
19423 uint32_t dma_bufr_size_bytes;
19424 /* Key Context type. */
19425 uint8_t key_ctx_type;
19426 /* Tx Key Context. */
19427 #define HWRM_FUNC_KEY_CTX_ALLOC_INPUT_KEY_CTX_TYPE_TX UINT32_C(0x0)
19428 /* Rx KTLS Context. */
19429 #define HWRM_FUNC_KEY_CTX_ALLOC_INPUT_KEY_CTX_TYPE_RX UINT32_C(0x1)
19430 #define HWRM_FUNC_KEY_CTX_ALLOC_INPUT_KEY_CTX_TYPE_LAST \
19431 HWRM_FUNC_KEY_CTX_ALLOC_INPUT_KEY_CTX_TYPE_RX
19432 uint8_t unused_0[7];
19433 /* Host DMA address to send back KTLS context IDs. */
19434 uint64_t host_dma_addr;
19437 /* hwrm_func_key_ctx_alloc_output (size:128b/16B) */
19438 struct hwrm_func_key_ctx_alloc_output {
19439 /* The specific error status for the command. */
19440 uint16_t error_code;
19441 /* The HWRM command request type. */
19443 /* The sequence ID from the original command. */
19445 /* The length of the response data in number of bytes. */
19447 /* Actual number of Key Contexts allocated. */
19448 uint16_t num_key_ctxs_allocated;
19449 uint8_t unused_0[5];
19451 * This field is used in Output records to indicate that the output
19452 * is completely written to RAM. This field should be read as '1'
19453 * to indicate that the output has been completely written.
19454 * When writing a command completion or response to an internal processor,
19455 * the order of writes has to be such that this field is written last.
19460 /**********************************
19461 * hwrm_func_backing_store_cfg_v2 *
19462 **********************************/
19465 /* hwrm_func_backing_store_cfg_v2_input (size:320b/40B) */
19466 struct hwrm_func_backing_store_cfg_v2_input {
19467 /* The HWRM command request type. */
19470 * The completion ring to send the completion event on. This should
19471 * be the NQ ID returned from the `nq_alloc` HWRM command.
19473 uint16_t cmpl_ring;
19475 * The sequence ID is used by the driver for tracking multiple
19476 * commands. This ID is treated as opaque data by the firmware and
19477 * the value is returned in the `hwrm_resp_hdr` upon completion.
19481 * The target ID of the command:
19482 * * 0x0-0xFFF8 - The function ID
19483 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
19484 * * 0xFFFD - Reserved for user-space HWRM interface
19487 uint16_t target_id;
19489 * A physical address pointer pointing to a host buffer that the
19490 * command's response data will be written. This can be either a host
19491 * physical address (HPA) or a guest physical address (GPA) and must
19492 * point to a physically contiguous block of memory.
19494 uint64_t resp_addr;
19495 /* Type of backing store to be configured. */
19498 #define HWRM_FUNC_BACKING_STORE_CFG_V2_INPUT_TYPE_QP \
19500 /* Shared receive queue. */
19501 #define HWRM_FUNC_BACKING_STORE_CFG_V2_INPUT_TYPE_SRQ \
19503 /* Completion queue. */
19504 #define HWRM_FUNC_BACKING_STORE_CFG_V2_INPUT_TYPE_CQ \
19507 #define HWRM_FUNC_BACKING_STORE_CFG_V2_INPUT_TYPE_VNIC \
19509 /* Statistic context. */
19510 #define HWRM_FUNC_BACKING_STORE_CFG_V2_INPUT_TYPE_STAT \
19512 /* Slow-path TQM ring. */
19513 #define HWRM_FUNC_BACKING_STORE_CFG_V2_INPUT_TYPE_SP_TQM_RING \
19515 /* Fast-path TQM ring. */
19516 #define HWRM_FUNC_BACKING_STORE_CFG_V2_INPUT_TYPE_FP_TQM_RING \
19519 #define HWRM_FUNC_BACKING_STORE_CFG_V2_INPUT_TYPE_MRAV \
19522 #define HWRM_FUNC_BACKING_STORE_CFG_V2_INPUT_TYPE_TIM \
19524 /* Tx key context. */
19525 #define HWRM_FUNC_BACKING_STORE_CFG_V2_INPUT_TYPE_TKC \
19527 /* Rx key context. */
19528 #define HWRM_FUNC_BACKING_STORE_CFG_V2_INPUT_TYPE_RKC \
19530 /* Mid-path TQM ring. */
19531 #define HWRM_FUNC_BACKING_STORE_CFG_V2_INPUT_TYPE_MP_TQM_RING \
19533 #define HWRM_FUNC_BACKING_STORE_CFG_V2_INPUT_TYPE_LAST \
19534 HWRM_FUNC_BACKING_STORE_CFG_V2_INPUT_TYPE_MP_TQM_RING
19536 * Instance of the backing store type. It is zero-based,
19537 * which means "0" indicates the first instance. For backing
19538 * stores with single instance only, leave this field to 0.
19541 /* Control flags. */
19544 * When set, the firmware only uses on-chip resources and
19545 * does not expect any backing store to be provided by the
19546 * host driver. This mode provides minimal L2 functionality
19547 * (e.g. limited L2 resources, no RoCE).
19549 #define HWRM_FUNC_BACKING_STORE_CFG_V2_INPUT_FLAGS_PREBOOT_MODE \
19551 /* Page directory. */
19553 /* Number of entries */
19554 uint32_t num_entries;
19555 /* Number of bytes allocated for each entry */
19556 uint16_t entry_size;
19557 /* Page size and pbl level. */
19558 uint8_t page_size_pbl_level;
19559 /* PBL indirect levels. */
19560 #define HWRM_FUNC_BACKING_STORE_CFG_V2_INPUT_PBL_LEVEL_MASK \
19562 #define HWRM_FUNC_BACKING_STORE_CFG_V2_INPUT_PBL_LEVEL_SFT 0
19563 /* PBL pointer is physical start address. */
19564 #define HWRM_FUNC_BACKING_STORE_CFG_V2_INPUT_PBL_LEVEL_LVL_0 \
19566 /* PBL pointer points to PTE table. */
19567 #define HWRM_FUNC_BACKING_STORE_CFG_V2_INPUT_PBL_LEVEL_LVL_1 \
19570 * PBL pointer points to PDE table with each entry pointing to
19573 #define HWRM_FUNC_BACKING_STORE_CFG_V2_INPUT_PBL_LEVEL_LVL_2 \
19575 #define HWRM_FUNC_BACKING_STORE_CFG_V2_INPUT_PBL_LEVEL_LAST \
19576 HWRM_FUNC_BACKING_STORE_CFG_V2_INPUT_PBL_LEVEL_LVL_2
19578 #define HWRM_FUNC_BACKING_STORE_CFG_V2_INPUT_PAGE_SIZE_MASK \
19580 #define HWRM_FUNC_BACKING_STORE_CFG_V2_INPUT_PAGE_SIZE_SFT 4
19582 #define HWRM_FUNC_BACKING_STORE_CFG_V2_INPUT_PAGE_SIZE_PG_4K \
19583 (UINT32_C(0x0) << 4)
19585 #define HWRM_FUNC_BACKING_STORE_CFG_V2_INPUT_PAGE_SIZE_PG_8K \
19586 (UINT32_C(0x1) << 4)
19588 #define HWRM_FUNC_BACKING_STORE_CFG_V2_INPUT_PAGE_SIZE_PG_64K \
19589 (UINT32_C(0x2) << 4)
19591 #define HWRM_FUNC_BACKING_STORE_CFG_V2_INPUT_PAGE_SIZE_PG_2M \
19592 (UINT32_C(0x3) << 4)
19594 #define HWRM_FUNC_BACKING_STORE_CFG_V2_INPUT_PAGE_SIZE_PG_8M \
19595 (UINT32_C(0x4) << 4)
19597 #define HWRM_FUNC_BACKING_STORE_CFG_V2_INPUT_PAGE_SIZE_PG_1G \
19598 (UINT32_C(0x5) << 4)
19599 #define HWRM_FUNC_BACKING_STORE_CFG_V2_INPUT_PAGE_SIZE_LAST \
19600 HWRM_FUNC_BACKING_STORE_CFG_V2_INPUT_PAGE_SIZE_PG_1G
19604 /* hwrm_func_backing_store_cfg_v2_output (size:128b/16B) */
19605 struct hwrm_func_backing_store_cfg_v2_output {
19606 /* The specific error status for the command. */
19607 uint16_t error_code;
19608 /* The HWRM command request type. */
19610 /* The sequence ID from the original command. */
19612 /* The length of the response data in number of bytes. */
19616 * This field is used in Output records to indicate that the
19617 * output is completely written to RAM. This field should be
19618 * read as '1' to indicate that the output has been completely
19619 * written. When writing a command completion or response to
19620 * an internal processor, the order of writes has to be such
19621 * that this field is written last.
19626 /***********************************
19627 * hwrm_func_backing_store_qcfg_v2 *
19628 ***********************************/
19631 /* hwrm_func_backing_store_qcfg_v2_input (size:192b/24B) */
19632 struct hwrm_func_backing_store_qcfg_v2_input {
19633 /* The HWRM command request type. */
19636 * The completion ring to send the completion event on. This should
19637 * be the NQ ID returned from the `nq_alloc` HWRM command.
19639 uint16_t cmpl_ring;
19641 * The sequence ID is used by the driver for tracking multiple
19642 * commands. This ID is treated as opaque data by the firmware and
19643 * the value is returned in the `hwrm_resp_hdr` upon completion.
19647 * The target ID of the command:
19648 * * 0x0-0xFFF8 - The function ID
19649 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
19650 * * 0xFFFD - Reserved for user-space HWRM interface
19653 uint16_t target_id;
19655 * A physical address pointer pointing to a host buffer that the
19656 * command's response data will be written. This can be either a host
19657 * physical address (HPA) or a guest physical address (GPA) and must
19658 * point to a physically contiguous block of memory.
19660 uint64_t resp_addr;
19661 /* Type of backing store to be configured. */
19664 #define HWRM_FUNC_BACKING_STORE_QCFG_V2_INPUT_TYPE_QP \
19666 /* Shared receive queue. */
19667 #define HWRM_FUNC_BACKING_STORE_QCFG_V2_INPUT_TYPE_SRQ \
19669 /* Completion queue. */
19670 #define HWRM_FUNC_BACKING_STORE_QCFG_V2_INPUT_TYPE_CQ \
19673 #define HWRM_FUNC_BACKING_STORE_QCFG_V2_INPUT_TYPE_VNIC \
19675 /* Statistic context. */
19676 #define HWRM_FUNC_BACKING_STORE_QCFG_V2_INPUT_TYPE_STAT \
19678 /* Slow-path TQM ring. */
19679 #define HWRM_FUNC_BACKING_STORE_QCFG_V2_INPUT_TYPE_SP_TQM_RING \
19681 /* Fast-path TQM ring. */
19682 #define HWRM_FUNC_BACKING_STORE_QCFG_V2_INPUT_TYPE_FP_TQM_RING \
19685 #define HWRM_FUNC_BACKING_STORE_QCFG_V2_INPUT_TYPE_MRAV \
19688 #define HWRM_FUNC_BACKING_STORE_QCFG_V2_INPUT_TYPE_TIM \
19690 /* Tx key context. */
19691 #define HWRM_FUNC_BACKING_STORE_QCFG_V2_INPUT_TYPE_TKC \
19693 /* Rx key context. */
19694 #define HWRM_FUNC_BACKING_STORE_QCFG_V2_INPUT_TYPE_RKC \
19696 /* Mid-path TQM ring. */
19697 #define HWRM_FUNC_BACKING_STORE_QCFG_V2_INPUT_TYPE_MP_TQM_RING \
19699 #define HWRM_FUNC_BACKING_STORE_QCFG_V2_INPUT_TYPE_LAST \
19700 HWRM_FUNC_BACKING_STORE_QCFG_V2_INPUT_TYPE_MP_TQM_RING
19702 * Instance of the backing store type. It is zero-based,
19703 * which means "0" indicates the first instance. For backing
19704 * stores with single instance only, leave this field to 0.
19710 /* hwrm_func_backing_store_qcfg_v2_output (size:256b/32B) */
19711 struct hwrm_func_backing_store_qcfg_v2_output {
19712 /* The specific error status for the command. */
19713 uint16_t error_code;
19714 /* The HWRM command request type. */
19716 /* The sequence ID from the original command. */
19718 /* The length of the response data in number of bytes. */
19720 /* Type of backing store to be configured. */
19723 #define HWRM_FUNC_BACKING_STORE_QCFG_V2_OUTPUT_TYPE_QP \
19725 /* Shared receive queue. */
19726 #define HWRM_FUNC_BACKING_STORE_QCFG_V2_OUTPUT_TYPE_SRQ \
19728 /* Completion queue. */
19729 #define HWRM_FUNC_BACKING_STORE_QCFG_V2_OUTPUT_TYPE_CQ \
19732 #define HWRM_FUNC_BACKING_STORE_QCFG_V2_OUTPUT_TYPE_VNIC \
19734 /* Statistic context. */
19735 #define HWRM_FUNC_BACKING_STORE_QCFG_V2_OUTPUT_TYPE_STAT \
19737 /* Slow-path TQM ring. */
19738 #define HWRM_FUNC_BACKING_STORE_QCFG_V2_OUTPUT_TYPE_SP_TQM_RING \
19740 /* Fast-path TQM ring. */
19741 #define HWRM_FUNC_BACKING_STORE_QCFG_V2_OUTPUT_TYPE_FP_TQM_RING \
19744 #define HWRM_FUNC_BACKING_STORE_QCFG_V2_OUTPUT_TYPE_MRAV \
19747 #define HWRM_FUNC_BACKING_STORE_QCFG_V2_OUTPUT_TYPE_TIM \
19749 /* Tx key context. */
19750 #define HWRM_FUNC_BACKING_STORE_QCFG_V2_OUTPUT_TYPE_TKC \
19752 /* Rx key context. */
19753 #define HWRM_FUNC_BACKING_STORE_QCFG_V2_OUTPUT_TYPE_RKC \
19755 /* Mid-path TQM ring. */
19756 #define HWRM_FUNC_BACKING_STORE_QCFG_V2_OUTPUT_TYPE_MP_TQM_RING \
19758 #define HWRM_FUNC_BACKING_STORE_QCFG_V2_OUTPUT_TYPE_LAST \
19759 HWRM_FUNC_BACKING_STORE_QCFG_V2_OUTPUT_TYPE_MP_TQM_RING
19761 * Instance of the backing store type. It is zero-based,
19762 * which means "0" indicates the first instance. For backing
19763 * stores with single instance only, leave this field to 0.
19766 /* Control flags. */
19768 /* Page directory. */
19770 /* Number of entries */
19771 uint32_t num_entries;
19772 /* Page size and pbl level. */
19773 uint8_t page_size_pbl_level;
19774 /* PBL indirect levels. */
19775 #define HWRM_FUNC_BACKING_STORE_QCFG_V2_OUTPUT_PBL_LEVEL_MASK \
19777 #define HWRM_FUNC_BACKING_STORE_QCFG_V2_OUTPUT_PBL_LEVEL_SFT 0
19778 /* PBL pointer is physical start address. */
19779 #define HWRM_FUNC_BACKING_STORE_QCFG_V2_OUTPUT_PBL_LEVEL_LVL_0 \
19781 /* PBL pointer points to PTE table. */
19782 #define HWRM_FUNC_BACKING_STORE_QCFG_V2_OUTPUT_PBL_LEVEL_LVL_1 \
19785 * PBL pointer points to PDE table with each entry pointing to
19788 #define HWRM_FUNC_BACKING_STORE_QCFG_V2_OUTPUT_PBL_LEVEL_LVL_2 \
19790 #define HWRM_FUNC_BACKING_STORE_QCFG_V2_OUTPUT_PBL_LEVEL_LAST \
19791 HWRM_FUNC_BACKING_STORE_QCFG_V2_OUTPUT_PBL_LEVEL_LVL_2
19793 #define HWRM_FUNC_BACKING_STORE_QCFG_V2_OUTPUT_PAGE_SIZE_MASK \
19795 #define HWRM_FUNC_BACKING_STORE_QCFG_V2_OUTPUT_PAGE_SIZE_SFT 4
19797 #define HWRM_FUNC_BACKING_STORE_QCFG_V2_OUTPUT_PAGE_SIZE_PG_4K \
19798 (UINT32_C(0x0) << 4)
19800 #define HWRM_FUNC_BACKING_STORE_QCFG_V2_OUTPUT_PAGE_SIZE_PG_8K \
19801 (UINT32_C(0x1) << 4)
19803 #define HWRM_FUNC_BACKING_STORE_QCFG_V2_OUTPUT_PAGE_SIZE_PG_64K \
19804 (UINT32_C(0x2) << 4)
19806 #define HWRM_FUNC_BACKING_STORE_QCFG_V2_OUTPUT_PAGE_SIZE_PG_2M \
19807 (UINT32_C(0x3) << 4)
19809 #define HWRM_FUNC_BACKING_STORE_QCFG_V2_OUTPUT_PAGE_SIZE_PG_8M \
19810 (UINT32_C(0x4) << 4)
19812 #define HWRM_FUNC_BACKING_STORE_QCFG_V2_OUTPUT_PAGE_SIZE_PG_1G \
19813 (UINT32_C(0x5) << 4)
19814 #define HWRM_FUNC_BACKING_STORE_QCFG_V2_OUTPUT_PAGE_SIZE_LAST \
19815 HWRM_FUNC_BACKING_STORE_QCFG_V2_OUTPUT_PAGE_SIZE_PG_1G
19818 * This field is used in Output records to indicate that the
19819 * output is completely written to RAM. This field should be
19820 * read as '1' to indicate that the output has been completely
19821 * written. When writing a command completion or response to
19822 * an internal processor, the order of writes has to be such
19823 * that this field is written last.
19828 /***********************
19829 * hwrm_func_vlan_qcfg *
19830 ***********************/
19833 /* hwrm_func_vlan_qcfg_input (size:192b/24B) */
19834 struct hwrm_func_vlan_qcfg_input {
19835 /* The HWRM command request type. */
19838 * The completion ring to send the completion event on. This should
19839 * be the NQ ID returned from the `nq_alloc` HWRM command.
19841 uint16_t cmpl_ring;
19843 * The sequence ID is used by the driver for tracking multiple
19844 * commands. This ID is treated as opaque data by the firmware and
19845 * the value is returned in the `hwrm_resp_hdr` upon completion.
19849 * The target ID of the command:
19850 * * 0x0-0xFFF8 - The function ID
19851 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
19852 * * 0xFFFD - Reserved for user-space HWRM interface
19855 uint16_t target_id;
19857 * A physical address pointer pointing to a host buffer that the
19858 * command's response data will be written. This can be either a host
19859 * physical address (HPA) or a guest physical address (GPA) and must
19860 * point to a physically contiguous block of memory.
19862 uint64_t resp_addr;
19864 * Function ID of the function that is being
19866 * If set to 0xFF... (All Fs), then the configuration is
19867 * for the requesting function.
19870 uint8_t unused_0[6];
19873 /* hwrm_func_vlan_qcfg_output (size:320b/40B) */
19874 struct hwrm_func_vlan_qcfg_output {
19875 /* The specific error status for the command. */
19876 uint16_t error_code;
19877 /* The HWRM command request type. */
19879 /* The sequence ID from the original command. */
19881 /* The length of the response data in number of bytes. */
19884 /* S-TAG VLAN identifier configured for the function. */
19886 /* S-TAG PCP value configured for the function. */
19890 * S-TAG TPID value configured for the function. This field is specified in
19891 * network byte order.
19893 uint16_t stag_tpid;
19894 /* C-TAG VLAN identifier configured for the function. */
19896 /* C-TAG PCP value configured for the function. */
19900 * C-TAG TPID value configured for the function. This field is specified in
19901 * network byte order.
19903 uint16_t ctag_tpid;
19908 uint8_t unused_3[3];
19910 * This field is used in Output records to indicate that the output
19911 * is completely written to RAM. This field should be read as '1'
19912 * to indicate that the output has been completely written.
19913 * When writing a command completion or response to an internal processor,
19914 * the order of writes has to be such that this field is written last.
19919 /**********************
19920 * hwrm_func_vlan_cfg *
19921 **********************/
19924 /* hwrm_func_vlan_cfg_input (size:384b/48B) */
19925 struct hwrm_func_vlan_cfg_input {
19926 /* The HWRM command request type. */
19929 * The completion ring to send the completion event on. This should
19930 * be the NQ ID returned from the `nq_alloc` HWRM command.
19932 uint16_t cmpl_ring;
19934 * The sequence ID is used by the driver for tracking multiple
19935 * commands. This ID is treated as opaque data by the firmware and
19936 * the value is returned in the `hwrm_resp_hdr` upon completion.
19940 * The target ID of the command:
19941 * * 0x0-0xFFF8 - The function ID
19942 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
19943 * * 0xFFFD - Reserved for user-space HWRM interface
19946 uint16_t target_id;
19948 * A physical address pointer pointing to a host buffer that the
19949 * command's response data will be written. This can be either a host
19950 * physical address (HPA) or a guest physical address (GPA) and must
19951 * point to a physically contiguous block of memory.
19953 uint64_t resp_addr;
19955 * Function ID of the function that is being
19957 * If set to 0xFF... (All Fs), then the configuration is
19958 * for the requesting function.
19961 uint8_t unused_0[2];
19964 * This bit must be '1' for the stag_vid field to be
19967 #define HWRM_FUNC_VLAN_CFG_INPUT_ENABLES_STAG_VID UINT32_C(0x1)
19969 * This bit must be '1' for the ctag_vid field to be
19972 #define HWRM_FUNC_VLAN_CFG_INPUT_ENABLES_CTAG_VID UINT32_C(0x2)
19974 * This bit must be '1' for the stag_pcp field to be
19977 #define HWRM_FUNC_VLAN_CFG_INPUT_ENABLES_STAG_PCP UINT32_C(0x4)
19979 * This bit must be '1' for the ctag_pcp field to be
19982 #define HWRM_FUNC_VLAN_CFG_INPUT_ENABLES_CTAG_PCP UINT32_C(0x8)
19984 * This bit must be '1' for the stag_tpid field to be
19987 #define HWRM_FUNC_VLAN_CFG_INPUT_ENABLES_STAG_TPID UINT32_C(0x10)
19989 * This bit must be '1' for the ctag_tpid field to be
19992 #define HWRM_FUNC_VLAN_CFG_INPUT_ENABLES_CTAG_TPID UINT32_C(0x20)
19993 /* S-TAG VLAN identifier configured for the function. */
19995 /* S-TAG PCP value configured for the function. */
19999 * S-TAG TPID value configured for the function. This field is specified in
20000 * network byte order.
20002 uint16_t stag_tpid;
20003 /* C-TAG VLAN identifier configured for the function. */
20005 /* C-TAG PCP value configured for the function. */
20009 * C-TAG TPID value configured for the function. This field is specified in
20010 * network byte order.
20012 uint16_t ctag_tpid;
20017 uint8_t unused_3[4];
20020 /* hwrm_func_vlan_cfg_output (size:128b/16B) */
20021 struct hwrm_func_vlan_cfg_output {
20022 /* The specific error status for the command. */
20023 uint16_t error_code;
20024 /* The HWRM command request type. */
20026 /* The sequence ID from the original command. */
20028 /* The length of the response data in number of bytes. */
20030 uint8_t unused_0[7];
20032 * This field is used in Output records to indicate that the output
20033 * is completely written to RAM. This field should be read as '1'
20034 * to indicate that the output has been completely written.
20035 * When writing a command completion or response to an internal processor,
20036 * the order of writes has to be such that this field is written last.
20041 /*******************************
20042 * hwrm_func_vf_vnic_ids_query *
20043 *******************************/
20046 /* hwrm_func_vf_vnic_ids_query_input (size:256b/32B) */
20047 struct hwrm_func_vf_vnic_ids_query_input {
20048 /* The HWRM command request type. */
20051 * The completion ring to send the completion event on. This should
20052 * be the NQ ID returned from the `nq_alloc` HWRM command.
20054 uint16_t cmpl_ring;
20056 * The sequence ID is used by the driver for tracking multiple
20057 * commands. This ID is treated as opaque data by the firmware and
20058 * the value is returned in the `hwrm_resp_hdr` upon completion.
20062 * The target ID of the command:
20063 * * 0x0-0xFFF8 - The function ID
20064 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
20065 * * 0xFFFD - Reserved for user-space HWRM interface
20068 uint16_t target_id;
20070 * A physical address pointer pointing to a host buffer that the
20071 * command's response data will be written. This can be either a host
20072 * physical address (HPA) or a guest physical address (GPA) and must
20073 * point to a physically contiguous block of memory.
20075 uint64_t resp_addr;
20077 * This value is used to identify a Virtual Function (VF).
20078 * The scope of VF ID is local within a PF.
20081 uint8_t unused_0[2];
20082 /* Max number of vnic ids in vnic id table */
20083 uint32_t max_vnic_id_cnt;
20084 /* This is the address for VF VNIC ID table */
20085 uint64_t vnic_id_tbl_addr;
20088 /* hwrm_func_vf_vnic_ids_query_output (size:128b/16B) */
20089 struct hwrm_func_vf_vnic_ids_query_output {
20090 /* The specific error status for the command. */
20091 uint16_t error_code;
20092 /* The HWRM command request type. */
20094 /* The sequence ID from the original command. */
20096 /* The length of the response data in number of bytes. */
20099 * Actual number of vnic ids
20101 * Each VNIC ID is written as a 32-bit number.
20103 uint32_t vnic_id_cnt;
20104 uint8_t unused_0[3];
20106 * This field is used in Output records to indicate that the output
20107 * is completely written to RAM. This field should be read as '1'
20108 * to indicate that the output has been completely written.
20109 * When writing a command completion or response to an internal processor,
20110 * the order of writes has to be such that this field is written last.
20115 /***********************
20116 * hwrm_func_vf_bw_cfg *
20117 ***********************/
20120 /* hwrm_func_vf_bw_cfg_input (size:960b/120B) */
20121 struct hwrm_func_vf_bw_cfg_input {
20122 /* The HWRM command request type. */
20125 * The completion ring to send the completion event on. This should
20126 * be the NQ ID returned from the `nq_alloc` HWRM command.
20128 uint16_t cmpl_ring;
20130 * The sequence ID is used by the driver for tracking multiple
20131 * commands. This ID is treated as opaque data by the firmware and
20132 * the value is returned in the `hwrm_resp_hdr` upon completion.
20136 * The target ID of the command:
20137 * * 0x0-0xFFF8 - The function ID
20138 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
20139 * * 0xFFFD - Reserved for user-space HWRM interface
20142 uint16_t target_id;
20144 * A physical address pointer pointing to a host buffer that the
20145 * command's response data will be written. This can be either a host
20146 * physical address (HPA) or a guest physical address (GPA) and must
20147 * point to a physically contiguous block of memory.
20149 uint64_t resp_addr;
20151 * The number of VF functions that are being configured.
20152 * The cmd space allows up to 50 VFs' BW to be configured with one cmd.
20155 uint16_t unused[3];
20156 /* These 16-bit fields contain the VF fid and the rate scale percentage. */
20158 /* The physical VF id the adjustment will be made to. */
20159 #define HWRM_FUNC_VF_BW_CFG_INPUT_VFN_VFID_MASK UINT32_C(0xfff)
20160 #define HWRM_FUNC_VF_BW_CFG_INPUT_VFN_VFID_SFT 0
20162 * This field configures the rate scale percentage of the VF as specified
20163 * by the physical VF id.
20165 #define HWRM_FUNC_VF_BW_CFG_INPUT_VFN_RATE_MASK UINT32_C(0xf000)
20166 #define HWRM_FUNC_VF_BW_CFG_INPUT_VFN_RATE_SFT 12
20167 /* 0% of the max tx rate */
20168 #define HWRM_FUNC_VF_BW_CFG_INPUT_VFN_RATE_PCT_0 \
20169 (UINT32_C(0x0) << 12)
20170 /* 6.66% of the max tx rate */
20171 #define HWRM_FUNC_VF_BW_CFG_INPUT_VFN_RATE_PCT_6_66 \
20172 (UINT32_C(0x1) << 12)
20173 /* 13.33% of the max tx rate */
20174 #define HWRM_FUNC_VF_BW_CFG_INPUT_VFN_RATE_PCT_13_33 \
20175 (UINT32_C(0x2) << 12)
20176 /* 20% of the max tx rate */
20177 #define HWRM_FUNC_VF_BW_CFG_INPUT_VFN_RATE_PCT_20 \
20178 (UINT32_C(0x3) << 12)
20179 /* 26.66% of the max tx rate */
20180 #define HWRM_FUNC_VF_BW_CFG_INPUT_VFN_RATE_PCT_26_66 \
20181 (UINT32_C(0x4) << 12)
20182 /* 33% of the max tx rate */
20183 #define HWRM_FUNC_VF_BW_CFG_INPUT_VFN_RATE_PCT_33_33 \
20184 (UINT32_C(0x5) << 12)
20185 /* 40% of the max tx rate */
20186 #define HWRM_FUNC_VF_BW_CFG_INPUT_VFN_RATE_PCT_40 \
20187 (UINT32_C(0x6) << 12)
20188 /* 46.66% of the max tx rate */
20189 #define HWRM_FUNC_VF_BW_CFG_INPUT_VFN_RATE_PCT_46_66 \
20190 (UINT32_C(0x7) << 12)
20191 /* 53.33% of the max tx rate */
20192 #define HWRM_FUNC_VF_BW_CFG_INPUT_VFN_RATE_PCT_53_33 \
20193 (UINT32_C(0x8) << 12)
20194 /* 60% of the max tx rate */
20195 #define HWRM_FUNC_VF_BW_CFG_INPUT_VFN_RATE_PCT_60 \
20196 (UINT32_C(0x9) << 12)
20197 /* 66.66% of the max tx rate */
20198 #define HWRM_FUNC_VF_BW_CFG_INPUT_VFN_RATE_PCT_66_66 \
20199 (UINT32_C(0xa) << 12)
20200 /* 53.33% of the max tx rate */
20201 #define HWRM_FUNC_VF_BW_CFG_INPUT_VFN_RATE_PCT_73_33 \
20202 (UINT32_C(0xb) << 12)
20203 /* 80% of the max tx rate */
20204 #define HWRM_FUNC_VF_BW_CFG_INPUT_VFN_RATE_PCT_80 \
20205 (UINT32_C(0xc) << 12)
20206 /* 86.66% of the max tx rate */
20207 #define HWRM_FUNC_VF_BW_CFG_INPUT_VFN_RATE_PCT_86_66 \
20208 (UINT32_C(0xd) << 12)
20209 /* 93.33% of the max tx rate */
20210 #define HWRM_FUNC_VF_BW_CFG_INPUT_VFN_RATE_PCT_93_33 \
20211 (UINT32_C(0xe) << 12)
20212 /* 100% of the max tx rate */
20213 #define HWRM_FUNC_VF_BW_CFG_INPUT_VFN_RATE_PCT_100 \
20214 (UINT32_C(0xf) << 12)
20215 #define HWRM_FUNC_VF_BW_CFG_INPUT_VFN_RATE_LAST \
20216 HWRM_FUNC_VF_BW_CFG_INPUT_VFN_RATE_PCT_100
20219 /* hwrm_func_vf_bw_cfg_output (size:128b/16B) */
20220 struct hwrm_func_vf_bw_cfg_output {
20221 /* The specific error status for the command. */
20222 uint16_t error_code;
20223 /* The HWRM command request type. */
20225 /* The sequence ID from the original command. */
20227 /* The length of the response data in number of bytes. */
20229 uint8_t unused_0[7];
20231 * This field is used in Output records to indicate that the output
20232 * is completely written to RAM. This field should be read as '1'
20233 * to indicate that the output has been completely written.
20234 * When writing a command completion or response to an internal processor,
20235 * the order of writes has to be such that this field is written last.
20240 /************************
20241 * hwrm_func_vf_bw_qcfg *
20242 ************************/
20245 /* hwrm_func_vf_bw_qcfg_input (size:960b/120B) */
20246 struct hwrm_func_vf_bw_qcfg_input {
20247 /* The HWRM command request type. */
20250 * The completion ring to send the completion event on. This should
20251 * be the NQ ID returned from the `nq_alloc` HWRM command.
20253 uint16_t cmpl_ring;
20255 * The sequence ID is used by the driver for tracking multiple
20256 * commands. This ID is treated as opaque data by the firmware and
20257 * the value is returned in the `hwrm_resp_hdr` upon completion.
20261 * The target ID of the command:
20262 * * 0x0-0xFFF8 - The function ID
20263 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
20264 * * 0xFFFD - Reserved for user-space HWRM interface
20267 uint16_t target_id;
20269 * A physical address pointer pointing to a host buffer that the
20270 * command's response data will be written. This can be either a host
20271 * physical address (HPA) or a guest physical address (GPA) and must
20272 * point to a physically contiguous block of memory.
20274 uint64_t resp_addr;
20276 * The number of VF functions that are being queried.
20277 * The inline response space allows the host to query up to 50 VFs'
20278 * rate scale percentage
20281 uint16_t unused[3];
20282 /* These 16-bit fields contain the VF fid */
20284 /* The physical VF id of interest */
20285 #define HWRM_FUNC_VF_BW_QCFG_INPUT_VFN_VFID_MASK UINT32_C(0xfff)
20286 #define HWRM_FUNC_VF_BW_QCFG_INPUT_VFN_VFID_SFT 0
20289 /* hwrm_func_vf_bw_qcfg_output (size:960b/120B) */
20290 struct hwrm_func_vf_bw_qcfg_output {
20291 /* The specific error status for the command. */
20292 uint16_t error_code;
20293 /* The HWRM command request type. */
20295 /* The sequence ID from the original command. */
20297 /* The length of the response data in number of bytes. */
20300 * The number of VF functions that are being queried.
20301 * The inline response space allows the host to query up to 50 VFs' rate
20305 uint16_t unused[3];
20306 /* These 16-bit fields contain the VF fid and the rate scale percentage. */
20308 /* The physical VF id the adjustment will be made to. */
20309 #define HWRM_FUNC_VF_BW_QCFG_OUTPUT_VFN_VFID_MASK UINT32_C(0xfff)
20310 #define HWRM_FUNC_VF_BW_QCFG_OUTPUT_VFN_VFID_SFT 0
20312 * This field configures the rate scale percentage of the VF as specified
20313 * by the physical VF id.
20315 #define HWRM_FUNC_VF_BW_QCFG_OUTPUT_VFN_RATE_MASK UINT32_C(0xf000)
20316 #define HWRM_FUNC_VF_BW_QCFG_OUTPUT_VFN_RATE_SFT 12
20317 /* 0% of the max tx rate */
20318 #define HWRM_FUNC_VF_BW_QCFG_OUTPUT_VFN_RATE_PCT_0 \
20319 (UINT32_C(0x0) << 12)
20320 /* 6.66% of the max tx rate */
20321 #define HWRM_FUNC_VF_BW_QCFG_OUTPUT_VFN_RATE_PCT_6_66 \
20322 (UINT32_C(0x1) << 12)
20323 /* 13.33% of the max tx rate */
20324 #define HWRM_FUNC_VF_BW_QCFG_OUTPUT_VFN_RATE_PCT_13_33 \
20325 (UINT32_C(0x2) << 12)
20326 /* 20% of the max tx rate */
20327 #define HWRM_FUNC_VF_BW_QCFG_OUTPUT_VFN_RATE_PCT_20 \
20328 (UINT32_C(0x3) << 12)
20329 /* 26.66% of the max tx rate */
20330 #define HWRM_FUNC_VF_BW_QCFG_OUTPUT_VFN_RATE_PCT_26_66 \
20331 (UINT32_C(0x4) << 12)
20332 /* 33% of the max tx rate */
20333 #define HWRM_FUNC_VF_BW_QCFG_OUTPUT_VFN_RATE_PCT_33_33 \
20334 (UINT32_C(0x5) << 12)
20335 /* 40% of the max tx rate */
20336 #define HWRM_FUNC_VF_BW_QCFG_OUTPUT_VFN_RATE_PCT_40 \
20337 (UINT32_C(0x6) << 12)
20338 /* 46.66% of the max tx rate */
20339 #define HWRM_FUNC_VF_BW_QCFG_OUTPUT_VFN_RATE_PCT_46_66 \
20340 (UINT32_C(0x7) << 12)
20341 /* 53.33% of the max tx rate */
20342 #define HWRM_FUNC_VF_BW_QCFG_OUTPUT_VFN_RATE_PCT_53_33 \
20343 (UINT32_C(0x8) << 12)
20344 /* 60% of the max tx rate */
20345 #define HWRM_FUNC_VF_BW_QCFG_OUTPUT_VFN_RATE_PCT_60 \
20346 (UINT32_C(0x9) << 12)
20347 /* 66.66% of the max tx rate */
20348 #define HWRM_FUNC_VF_BW_QCFG_OUTPUT_VFN_RATE_PCT_66_66 \
20349 (UINT32_C(0xa) << 12)
20350 /* 53.33% of the max tx rate */
20351 #define HWRM_FUNC_VF_BW_QCFG_OUTPUT_VFN_RATE_PCT_73_33 \
20352 (UINT32_C(0xb) << 12)
20353 /* 80% of the max tx rate */
20354 #define HWRM_FUNC_VF_BW_QCFG_OUTPUT_VFN_RATE_PCT_80 \
20355 (UINT32_C(0xc) << 12)
20356 /* 86.66% of the max tx rate */
20357 #define HWRM_FUNC_VF_BW_QCFG_OUTPUT_VFN_RATE_PCT_86_66 \
20358 (UINT32_C(0xd) << 12)
20359 /* 93.33% of the max tx rate */
20360 #define HWRM_FUNC_VF_BW_QCFG_OUTPUT_VFN_RATE_PCT_93_33 \
20361 (UINT32_C(0xe) << 12)
20362 /* 100% of the max tx rate */
20363 #define HWRM_FUNC_VF_BW_QCFG_OUTPUT_VFN_RATE_PCT_100 \
20364 (UINT32_C(0xf) << 12)
20365 #define HWRM_FUNC_VF_BW_QCFG_OUTPUT_VFN_RATE_LAST \
20366 HWRM_FUNC_VF_BW_QCFG_OUTPUT_VFN_RATE_PCT_100
20367 uint8_t unused_0[7];
20369 * This field is used in Output records to indicate that the output
20370 * is completely written to RAM. This field should be read as '1'
20371 * to indicate that the output has been completely written.
20372 * When writing a command completion or response to an internal processor,
20373 * the order of writes has to be such that this field is written last.
20378 /***************************
20379 * hwrm_func_drv_if_change *
20380 ***************************/
20383 /* hwrm_func_drv_if_change_input (size:192b/24B) */
20384 struct hwrm_func_drv_if_change_input {
20385 /* The HWRM command request type. */
20388 * The completion ring to send the completion event on. This should
20389 * be the NQ ID returned from the `nq_alloc` HWRM command.
20391 uint16_t cmpl_ring;
20393 * The sequence ID is used by the driver for tracking multiple
20394 * commands. This ID is treated as opaque data by the firmware and
20395 * the value is returned in the `hwrm_resp_hdr` upon completion.
20399 * The target ID of the command:
20400 * * 0x0-0xFFF8 - The function ID
20401 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
20402 * * 0xFFFD - Reserved for user-space HWRM interface
20405 uint16_t target_id;
20407 * A physical address pointer pointing to a host buffer that the
20408 * command's response data will be written. This can be either a host
20409 * physical address (HPA) or a guest physical address (GPA) and must
20410 * point to a physically contiguous block of memory.
20412 uint64_t resp_addr;
20415 * When this bit is '1', the function driver is indicating
20416 * that the IF state is changing to UP state. The call should
20417 * be made at the beginning of the driver's open call before
20418 * resources are allocated. After making the call, the driver
20419 * should check the response to see if any resources may have
20420 * changed (see the response below). If the driver fails
20421 * the open call, the driver should make this call again with
20422 * this bit cleared to indicate that the IF state is not UP.
20423 * During the driver's close call when the IF state is changing
20424 * to DOWN, the driver should make this call with the bit cleared
20425 * after all resources have been freed.
20427 #define HWRM_FUNC_DRV_IF_CHANGE_INPUT_FLAGS_UP UINT32_C(0x1)
20431 /* hwrm_func_drv_if_change_output (size:128b/16B) */
20432 struct hwrm_func_drv_if_change_output {
20433 /* The specific error status for the command. */
20434 uint16_t error_code;
20435 /* The HWRM command request type. */
20437 /* The sequence ID from the original command. */
20439 /* The length of the response data in number of bytes. */
20443 * When this bit is '1', it indicates that the resources reserved
20444 * for this function may have changed. The driver should check
20445 * resource capabilities and reserve resources again before
20446 * allocating resources.
20448 #define HWRM_FUNC_DRV_IF_CHANGE_OUTPUT_FLAGS_RESC_CHANGE \
20451 * When this bit is '1', it indicates that the firmware got changed / reset.
20452 * The driver should do complete re-initialization when that bit is set.
20454 #define HWRM_FUNC_DRV_IF_CHANGE_OUTPUT_FLAGS_HOT_FW_RESET_DONE \
20456 uint8_t unused_0[3];
20458 * This field is used in Output records to indicate that the output
20459 * is completely written to RAM. This field should be read as '1'
20460 * to indicate that the output has been completely written.
20461 * When writing a command completion or response to an internal processor,
20462 * the order of writes has to be such that this field is written last.
20467 /*******************************
20468 * hwrm_func_host_pf_ids_query *
20469 *******************************/
20472 /* hwrm_func_host_pf_ids_query_input (size:192b/24B) */
20473 struct hwrm_func_host_pf_ids_query_input {
20474 /* The HWRM command request type. */
20477 * The completion ring to send the completion event on. This should
20478 * be the NQ ID returned from the `nq_alloc` HWRM command.
20480 uint16_t cmpl_ring;
20482 * The sequence ID is used by the driver for tracking multiple
20483 * commands. This ID is treated as opaque data by the firmware and
20484 * the value is returned in the `hwrm_resp_hdr` upon completion.
20488 * The target ID of the command:
20489 * * 0x0-0xFFF8 - The function ID
20490 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
20491 * * 0xFFFD - Reserved for user-space HWRM interface
20494 uint16_t target_id;
20496 * A physical address pointer pointing to a host buffer that the
20497 * command's response data will be written. This can be either a host
20498 * physical address (HPA) or a guest physical address (GPA) and must
20499 * point to a physically contiguous block of memory.
20501 uint64_t resp_addr;
20504 * # If this bit is set to '1', the query will contain PF(s)
20505 * belongs to SOC host.
20507 #define HWRM_FUNC_HOST_PF_IDS_QUERY_INPUT_HOST_SOC UINT32_C(0x1)
20509 * # If this bit is set to '1', the query will contain PF(s)
20510 * belongs to EP0 host.
20512 #define HWRM_FUNC_HOST_PF_IDS_QUERY_INPUT_HOST_EP_0 UINT32_C(0x2)
20514 * # If this bit is set to '1', the query will contain PF(s)
20515 * belongs to EP1 host.
20517 #define HWRM_FUNC_HOST_PF_IDS_QUERY_INPUT_HOST_EP_1 UINT32_C(0x4)
20519 * # If this bit is set to '1', the query will contain PF(s)
20520 * belongs to EP2 host.
20522 #define HWRM_FUNC_HOST_PF_IDS_QUERY_INPUT_HOST_EP_2 UINT32_C(0x8)
20524 * # If this bit is set to '1', the query will contain PF(s)
20525 * belongs to EP3 host.
20527 #define HWRM_FUNC_HOST_PF_IDS_QUERY_INPUT_HOST_EP_3 UINT32_C(0x10)
20529 * This provides a filter of what PF(s) will be returned in the
20534 * all available PF(s) belong to the host(s) (defined in the
20535 * host field). This includes the hidden PFs.
20537 #define HWRM_FUNC_HOST_PF_IDS_QUERY_INPUT_FILTER_ALL UINT32_C(0x0)
20539 * all available PF(s) belong to the host(s) (defined in the
20540 * host field) that is available for L2 traffic.
20542 #define HWRM_FUNC_HOST_PF_IDS_QUERY_INPUT_FILTER_L2 UINT32_C(0x1)
20544 * all available PF(s) belong to the host(s) (defined in the
20545 * host field) that is available for ROCE traffic.
20547 #define HWRM_FUNC_HOST_PF_IDS_QUERY_INPUT_FILTER_ROCE UINT32_C(0x2)
20548 #define HWRM_FUNC_HOST_PF_IDS_QUERY_INPUT_FILTER_LAST \
20549 HWRM_FUNC_HOST_PF_IDS_QUERY_INPUT_FILTER_ROCE
20550 uint8_t unused_1[6];
20553 /* hwrm_func_host_pf_ids_query_output (size:128b/16B) */
20554 struct hwrm_func_host_pf_ids_query_output {
20555 /* The specific error status for the command. */
20556 uint16_t error_code;
20557 /* The HWRM command request type. */
20559 /* The sequence ID from the original command. */
20561 /* The length of the response data in number of bytes. */
20563 /* This provides the first PF ID of the device. */
20564 uint16_t first_pf_id;
20565 uint16_t pf_ordinal_mask;
20567 * When this bit is '1', it indicates first PF belongs to one of
20568 * the hosts defined in the input request.
20570 #define HWRM_FUNC_HOST_PF_IDS_QUERY_OUTPUT_PF_ORDINAL_MASK_FUNC_0 \
20573 * When this bit is '1', it indicates 2nd PF belongs to one of the
20574 * hosts defined in the input request.
20576 #define HWRM_FUNC_HOST_PF_IDS_QUERY_OUTPUT_PF_ORDINAL_MASK_FUNC_1 \
20579 * When this bit is '1', it indicates 3rd PF belongs to one of the
20580 * hosts defined in the input request.
20582 #define HWRM_FUNC_HOST_PF_IDS_QUERY_OUTPUT_PF_ORDINAL_MASK_FUNC_2 \
20585 * When this bit is '1', it indicates 4th PF belongs to one of the
20586 * hosts defined in the input request.
20588 #define HWRM_FUNC_HOST_PF_IDS_QUERY_OUTPUT_PF_ORDINAL_MASK_FUNC_3 \
20591 * When this bit is '1', it indicates 5th PF belongs to one of the
20592 * hosts defined in the input request.
20594 #define HWRM_FUNC_HOST_PF_IDS_QUERY_OUTPUT_PF_ORDINAL_MASK_FUNC_4 \
20597 * When this bit is '1', it indicates 6th PF belongs to one of the
20598 * hosts defined in the input request.
20600 #define HWRM_FUNC_HOST_PF_IDS_QUERY_OUTPUT_PF_ORDINAL_MASK_FUNC_5 \
20603 * When this bit is '1', it indicates 7th PF belongs to one of the
20604 * hosts defined in the input request.
20606 #define HWRM_FUNC_HOST_PF_IDS_QUERY_OUTPUT_PF_ORDINAL_MASK_FUNC_6 \
20609 * When this bit is '1', it indicates 8th PF belongs to one of the
20610 * hosts defined in the input request.
20612 #define HWRM_FUNC_HOST_PF_IDS_QUERY_OUTPUT_PF_ORDINAL_MASK_FUNC_7 \
20615 * When this bit is '1', it indicates 9th PF belongs to one of the
20616 * hosts defined in the input request.
20618 #define HWRM_FUNC_HOST_PF_IDS_QUERY_OUTPUT_PF_ORDINAL_MASK_FUNC_8 \
20621 * When this bit is '1', it indicates 10th PF belongs to one of the
20622 * hosts defined in the input request.
20624 #define HWRM_FUNC_HOST_PF_IDS_QUERY_OUTPUT_PF_ORDINAL_MASK_FUNC_9 \
20627 * When this bit is '1', it indicates 11th PF belongs to one of the
20628 * hosts defined in the input request.
20630 #define HWRM_FUNC_HOST_PF_IDS_QUERY_OUTPUT_PF_ORDINAL_MASK_FUNC_10 \
20633 * When this bit is '1', it indicates 12th PF belongs to one of the
20634 * hosts defined in the input request.
20636 #define HWRM_FUNC_HOST_PF_IDS_QUERY_OUTPUT_PF_ORDINAL_MASK_FUNC_11 \
20639 * When this bit is '1', it indicates 13th PF belongs to one of the
20640 * hosts defined in the input request.
20642 #define HWRM_FUNC_HOST_PF_IDS_QUERY_OUTPUT_PF_ORDINAL_MASK_FUNC_12 \
20645 * When this bit is '1', it indicates 14th PF belongs to one of the
20646 * hosts defined in the input request.
20648 #define HWRM_FUNC_HOST_PF_IDS_QUERY_OUTPUT_PF_ORDINAL_MASK_FUNC_13 \
20651 * When this bit is '1', it indicates 15th PF belongs to one of the
20652 * hosts defined in the input request.
20654 #define HWRM_FUNC_HOST_PF_IDS_QUERY_OUTPUT_PF_ORDINAL_MASK_FUNC_14 \
20657 * When this bit is '1', it indicates 16th PF belongs to one of the
20658 * hosts defined in the input request.
20660 #define HWRM_FUNC_HOST_PF_IDS_QUERY_OUTPUT_PF_ORDINAL_MASK_FUNC_15 \
20662 uint8_t unused_1[3];
20664 * This field is used in Output records to indicate that the output
20665 * is completely written to RAM. This field should be read as '1'
20666 * to indicate that the output has been completely written.
20667 * When writing a command completion or response to an internal processor,
20668 * the order of writes has to be such that this field is written last.
20673 /*********************
20674 * hwrm_func_spd_cfg *
20675 *********************/
20678 /* hwrm_func_spd_cfg_input (size:384b/48B) */
20679 struct hwrm_func_spd_cfg_input {
20680 /* The HWRM command request type. */
20683 * The completion ring to send the completion event on. This should
20684 * be the NQ ID returned from the `nq_alloc` HWRM command.
20686 uint16_t cmpl_ring;
20688 * The sequence ID is used by the driver for tracking multiple
20689 * commands. This ID is treated as opaque data by the firmware and
20690 * the value is returned in the `hwrm_resp_hdr` upon completion.
20694 * The target ID of the command:
20695 * * 0x0-0xFFF8 - The function ID
20696 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
20697 * * 0xFFFD - Reserved for user-space HWRM interface
20700 uint16_t target_id;
20702 * A physical address pointer pointing to a host buffer that the
20703 * command's response data will be written. This can be either a host
20704 * physical address (HPA) or a guest physical address (GPA) and must
20705 * point to a physically contiguous block of memory.
20707 uint64_t resp_addr;
20709 /* Set this bit is '1' to enable the SPD datapath forwarding. */
20710 #define HWRM_FUNC_SPD_CFG_INPUT_FLAGS_FWD_ENABLE UINT32_C(0x1)
20711 /* Set this bit is '1' to disable the SPD datapath forwarding. */
20712 #define HWRM_FUNC_SPD_CFG_INPUT_FLAGS_FWD_DISABLE UINT32_C(0x2)
20714 * Set this bit is '1' to enable the SPD datapath checksum
20717 #define HWRM_FUNC_SPD_CFG_INPUT_FLAGS_CSUM_ENABLE UINT32_C(0x4)
20719 * Set this bit is '1' to disable the SPD datapath checksum
20722 #define HWRM_FUNC_SPD_CFG_INPUT_FLAGS_CSUM_DISABLE UINT32_C(0x8)
20724 * Set this bit is '1' to enable the SPD datapath debug
20727 #define HWRM_FUNC_SPD_CFG_INPUT_FLAGS_DBG_ENABLE UINT32_C(0x10)
20729 * Set this bit is '1' to disable the SPD datapath debug
20732 #define HWRM_FUNC_SPD_CFG_INPUT_FLAGS_DBG_DISABLE UINT32_C(0x20)
20735 * This bit must be '1' for the ethertype field to be
20738 #define HWRM_FUNC_SPD_CFG_INPUT_ENABLES_ETHERTYPE \
20741 * This bit must be '1' for the hash_mode_flags field to be
20744 #define HWRM_FUNC_SPD_CFG_INPUT_ENABLES_HASH_MODE_FLAGS \
20747 * This bit must be '1' for the hash_type field to be
20750 #define HWRM_FUNC_SPD_CFG_INPUT_ENABLES_HASH_TYPE \
20753 * This bit must be '1' for the ring_tbl_addr field to be
20756 #define HWRM_FUNC_SPD_CFG_INPUT_ENABLES_RING_TBL_ADDR \
20759 * This bit must be '1' for the hash_key_tbl_addr field to be
20762 #define HWRM_FUNC_SPD_CFG_INPUT_ENABLES_HASH_KEY_TBL_ADDR \
20765 * Ethertype value used in the encapsulated SPD packet header.
20766 * The user must choose a value that is not conflicting with
20767 * publicly defined ethertype values. By default, the ethertype
20768 * value of 0xffff is used if there is no user specified value.
20770 uint16_t ethertype;
20771 /* Flags to specify different RSS hash modes. */
20772 uint8_t hash_mode_flags;
20774 * When this bit is '1', it indicates using current RSS
20775 * hash mode setting configured in the device.
20777 #define HWRM_FUNC_SPD_CFG_INPUT_HASH_MODE_FLAGS_DEFAULT \
20780 * When this bit is '1', it indicates requesting support of
20781 * RSS hashing over innermost 4 tuples {l3.src, l3.dest,
20782 * l4.src, l4.dest} for tunnel packets. For none-tunnel
20783 * packets, the RSS hash is computed over the normal
20784 * src/dest l3 and src/dest l4 headers.
20786 #define HWRM_FUNC_SPD_CFG_INPUT_HASH_MODE_FLAGS_INNERMOST_4 \
20789 * When this bit is '1', it indicates requesting support of
20790 * RSS hashing over innermost 2 tuples {l3.src, l3.dest} for
20791 * tunnel packets. For none-tunnel packets, the RSS hash is
20792 * computed over the normal src/dest l3 headers.
20794 #define HWRM_FUNC_SPD_CFG_INPUT_HASH_MODE_FLAGS_INNERMOST_2 \
20797 * When this bit is '1', it indicates requesting support of
20798 * RSS hashing over outermost 4 tuples {t_l3.src, t_l3.dest,
20799 * t_l4.src, t_l4.dest} for tunnel packets. For none-tunnel
20800 * packets, the RSS hash is computed over the normal
20801 * src/dest l3 and src/dest l4 headers.
20803 #define HWRM_FUNC_SPD_CFG_INPUT_HASH_MODE_FLAGS_OUTERMOST_4 \
20806 * When this bit is '1', it indicates requesting support of
20807 * RSS hashing over outermost 2 tuples {t_l3.src, t_l3.dest} for
20808 * tunnel packets. For none-tunnel packets, the RSS hash is
20809 * computed over the normal src/dest l3 headers.
20811 #define HWRM_FUNC_SPD_CFG_INPUT_HASH_MODE_FLAGS_OUTERMOST_2 \
20814 uint32_t hash_type;
20816 * When this bit is '1', the RSS hash shall be computed
20817 * over source and destination IPv4 addresses of IPv4
20820 #define HWRM_FUNC_SPD_CFG_INPUT_HASH_TYPE_IPV4 UINT32_C(0x1)
20822 * When this bit is '1', the RSS hash shall be computed
20823 * over source/destination IPv4 addresses and
20824 * source/destination ports of TCP/IPv4 packets.
20826 #define HWRM_FUNC_SPD_CFG_INPUT_HASH_TYPE_TCP_IPV4 UINT32_C(0x2)
20828 * When this bit is '1', the RSS hash shall be computed
20829 * over source/destination IPv4 addresses and
20830 * source/destination ports of UDP/IPv4 packets.
20832 #define HWRM_FUNC_SPD_CFG_INPUT_HASH_TYPE_UDP_IPV4 UINT32_C(0x4)
20834 * When this bit is '1', the RSS hash shall be computed
20835 * over source and destination IPv4 addresses of IPv6
20838 #define HWRM_FUNC_SPD_CFG_INPUT_HASH_TYPE_IPV6 UINT32_C(0x8)
20840 * When this bit is '1', the RSS hash shall be computed
20841 * over source/destination IPv6 addresses and
20842 * source/destination ports of TCP/IPv6 packets.
20844 #define HWRM_FUNC_SPD_CFG_INPUT_HASH_TYPE_TCP_IPV6 UINT32_C(0x10)
20846 * When this bit is '1', the RSS hash shall be computed
20847 * over source/destination IPv6 addresses and
20848 * source/destination ports of UDP/IPv6 packets.
20850 #define HWRM_FUNC_SPD_CFG_INPUT_HASH_TYPE_UDP_IPV6 UINT32_C(0x20)
20851 /* This is the address for rss ring group table */
20852 uint64_t ring_grp_tbl_addr;
20853 /* This is the address for rss hash key table */
20854 uint64_t hash_key_tbl_addr;
20857 /* hwrm_func_spd_cfg_output (size:128b/16B) */
20858 struct hwrm_func_spd_cfg_output {
20859 /* The specific error status for the command. */
20860 uint16_t error_code;
20861 /* The HWRM command request type. */
20863 /* The sequence ID from the original command. */
20865 /* The length of the response data in number of bytes. */
20867 uint8_t unused_0[7];
20869 * This field is used in Output records to indicate that the output
20870 * is completely written to RAM. This field should be read as '1'
20871 * to indicate that the output has been completely written.
20872 * When writing a command completion or response to an internal processor,
20873 * the order of writes has to be such that this field is written last.
20878 /**********************
20879 * hwrm_func_spd_qcfg *
20880 **********************/
20883 /* hwrm_func_spd_qcfg_input (size:128b/16B) */
20884 struct hwrm_func_spd_qcfg_input {
20885 /* The HWRM command request type. */
20888 * The completion ring to send the completion event on. This should
20889 * be the NQ ID returned from the `nq_alloc` HWRM command.
20891 uint16_t cmpl_ring;
20893 * The sequence ID is used by the driver for tracking multiple
20894 * commands. This ID is treated as opaque data by the firmware and
20895 * the value is returned in the `hwrm_resp_hdr` upon completion.
20899 * The target ID of the command:
20900 * * 0x0-0xFFF8 - The function ID
20901 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
20902 * * 0xFFFD - Reserved for user-space HWRM interface
20905 uint16_t target_id;
20907 * A physical address pointer pointing to a host buffer that the
20908 * command's response data will be written. This can be either a host
20909 * physical address (HPA) or a guest physical address (GPA) and must
20910 * point to a physically contiguous block of memory.
20912 uint64_t resp_addr;
20915 /* hwrm_func_spd_qcfg_output (size:512b/64B) */
20916 struct hwrm_func_spd_qcfg_output {
20917 /* The specific error status for the command. */
20918 uint16_t error_code;
20919 /* The HWRM command request type. */
20921 /* The sequence ID from the original command. */
20923 /* The length of the response data in number of bytes. */
20927 * The SPD datapath forwarding is currently enabled when this
20928 * flag is set to '1'.
20930 #define HWRM_FUNC_SPD_QCFG_OUTPUT_FLAGS_FWD_ENABLED UINT32_C(0x1)
20932 * The SPD datapath checksum feature is currently enabled when
20933 * this flag is set to '1'.
20935 #define HWRM_FUNC_SPD_QCFG_OUTPUT_FLAGS_CSUM_ENABLED UINT32_C(0x2)
20937 * The SPD datapath debug feature is currently enabled when
20938 * this flag is set to '1'.
20940 #define HWRM_FUNC_SPD_QCFG_OUTPUT_FLAGS_DBG_ENABLED UINT32_C(0x4)
20941 uint32_t hash_type;
20943 * When this bit is '1', the RSS hash shall be computed
20944 * over source and destination IPv4 addresses of IPv4
20947 #define HWRM_FUNC_SPD_QCFG_OUTPUT_HASH_TYPE_IPV4 UINT32_C(0x1)
20949 * When this bit is '1', the RSS hash shall be computed
20950 * over source/destination IPv4 addresses and
20951 * source/destination ports of TCP/IPv4 packets.
20953 #define HWRM_FUNC_SPD_QCFG_OUTPUT_HASH_TYPE_TCP_IPV4 UINT32_C(0x2)
20955 * When this bit is '1', the RSS hash shall be computed
20956 * over source/destination IPv4 addresses and
20957 * source/destination ports of UDP/IPv4 packets.
20959 #define HWRM_FUNC_SPD_QCFG_OUTPUT_HASH_TYPE_UDP_IPV4 UINT32_C(0x4)
20961 * When this bit is '1', the RSS hash shall be computed
20962 * over source and destination IPv4 addresses of IPv6
20965 #define HWRM_FUNC_SPD_QCFG_OUTPUT_HASH_TYPE_IPV6 UINT32_C(0x8)
20967 * When this bit is '1', the RSS hash shall be computed
20968 * over source/destination IPv6 addresses and
20969 * source/destination ports of TCP/IPv6 packets.
20971 #define HWRM_FUNC_SPD_QCFG_OUTPUT_HASH_TYPE_TCP_IPV6 UINT32_C(0x10)
20973 * When this bit is '1', the RSS hash shall be computed
20974 * over source/destination IPv6 addresses and
20975 * source/destination ports of UDP/IPv6 packets.
20977 #define HWRM_FUNC_SPD_QCFG_OUTPUT_HASH_TYPE_UDP_IPV6 UINT32_C(0x20)
20978 /* This is the value of rss hash key */
20979 uint32_t hash_key[10];
20980 /* Flags to specify different RSS hash modes. */
20981 uint8_t hash_mode_flags;
20983 * When this bit is '1', it indicates using current RSS
20984 * hash mode setting configured in the device.
20986 #define HWRM_FUNC_SPD_QCFG_OUTPUT_HASH_MODE_FLAGS_DEFAULT \
20989 * When this bit is '1', it indicates requesting support of
20990 * RSS hashing over innermost 4 tuples {l3.src, l3.dest,
20991 * l4.src, l4.dest} for tunnel packets. For none-tunnel
20992 * packets, the RSS hash is computed over the normal
20993 * src/dest l3 and src/dest l4 headers.
20995 #define HWRM_FUNC_SPD_QCFG_OUTPUT_HASH_MODE_FLAGS_INNERMOST_4 \
20998 * When this bit is '1', it indicates requesting support of
20999 * RSS hashing over innermost 2 tuples {l3.src, l3.dest} for
21000 * tunnel packets. For none-tunnel packets, the RSS hash is
21001 * computed over the normal src/dest l3 headers.
21003 #define HWRM_FUNC_SPD_QCFG_OUTPUT_HASH_MODE_FLAGS_INNERMOST_2 \
21006 * When this bit is '1', it indicates requesting support of
21007 * RSS hashing over outermost 4 tuples {t_l3.src, t_l3.dest,
21008 * t_l4.src, t_l4.dest} for tunnel packets. For none-tunnel
21009 * packets, the RSS hash is computed over the normal
21010 * src/dest l3 and src/dest l4 headers.
21012 #define HWRM_FUNC_SPD_QCFG_OUTPUT_HASH_MODE_FLAGS_OUTERMOST_4 \
21015 * When this bit is '1', it indicates requesting support of
21016 * RSS hashing over outermost 2 tuples {t_l3.src, t_l3.dest} for
21017 * tunnel packets. For none-tunnel packets, the RSS hash is
21018 * computed over the normal src/dest l3 headers.
21020 #define HWRM_FUNC_SPD_QCFG_OUTPUT_HASH_MODE_FLAGS_OUTERMOST_2 \
21024 * Ethertype value used in the encapsulated SPD packet header.
21025 * The user must choose a value that is not conflicting with
21026 * publicly defined ethertype values. By default, the ethertype
21027 * value of 0xffff is used if there is no user specified value.
21029 uint16_t ethertype;
21030 uint8_t unused_2[3];
21032 * This field is used in Output records to indicate that the output
21033 * is completely written to RAM. This field should be read as '1'
21034 * to indicate that the output has been completely written.
21035 * When writing a command completion or response to an internal processor,
21036 * the order of writes has to be such that this field is written last.
21041 /*********************
21042 * hwrm_port_phy_cfg *
21043 *********************/
21046 /* hwrm_port_phy_cfg_input (size:448b/56B) */
21047 struct hwrm_port_phy_cfg_input {
21048 /* The HWRM command request type. */
21051 * The completion ring to send the completion event on. This should
21052 * be the NQ ID returned from the `nq_alloc` HWRM command.
21054 uint16_t cmpl_ring;
21056 * The sequence ID is used by the driver for tracking multiple
21057 * commands. This ID is treated as opaque data by the firmware and
21058 * the value is returned in the `hwrm_resp_hdr` upon completion.
21062 * The target ID of the command:
21063 * * 0x0-0xFFF8 - The function ID
21064 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
21065 * * 0xFFFD - Reserved for user-space HWRM interface
21068 uint16_t target_id;
21070 * A physical address pointer pointing to a host buffer that the
21071 * command's response data will be written. This can be either a host
21072 * physical address (HPA) or a guest physical address (GPA) and must
21073 * point to a physically contiguous block of memory.
21075 uint64_t resp_addr;
21078 * When this bit is set to '1', the PHY for the port shall
21081 * # If this bit is set to 1, then the HWRM shall reset the
21082 * PHY after applying PHY configuration changes specified
21084 * # In order to guarantee that PHY configuration changes
21085 * specified in this command take effect, the HWRM
21086 * client should set this flag to 1.
21087 * # If this bit is not set to 1, then the HWRM may reset
21088 * the PHY depending on the current PHY configuration and
21089 * settings specified in this command.
21091 #define HWRM_PORT_PHY_CFG_INPUT_FLAGS_RESET_PHY \
21093 /* deprecated bit. Do not use!!! */
21094 #define HWRM_PORT_PHY_CFG_INPUT_FLAGS_DEPRECATED \
21097 * When this bit is set to '1', and the force_pam4_link_speed
21098 * bit in the 'enables' field is '0', the link shall be forced
21099 * to the force_link_speed value.
21101 * When this bit is set to '1', and the force_pam4_link_speed
21102 * bit in the 'enables' field is '1', the link shall be forced
21103 * to the force_pam4_link_speed value.
21105 * When this bit is set to '1', the HWRM client should
21106 * not enable any of the auto negotiation related
21107 * fields represented by auto_XXX fields in this command.
21108 * When this bit is set to '1' and the HWRM client has
21109 * enabled a auto_XXX field in this command, then the
21110 * HWRM shall ignore the enabled auto_XXX field.
21112 * When this bit is set to zero, the link
21113 * shall be allowed to autoneg.
21115 #define HWRM_PORT_PHY_CFG_INPUT_FLAGS_FORCE \
21118 * When this bit is set to '1', the auto-negotiation process
21119 * shall be restarted on the link.
21121 #define HWRM_PORT_PHY_CFG_INPUT_FLAGS_RESTART_AUTONEG \
21124 * When this bit is set to '1', Energy Efficient Ethernet
21125 * (EEE) is requested to be enabled on this link.
21126 * If EEE is not supported on this port, then this flag
21127 * shall be ignored by the HWRM.
21129 #define HWRM_PORT_PHY_CFG_INPUT_FLAGS_EEE_ENABLE \
21132 * When this bit is set to '1', Energy Efficient Ethernet
21133 * (EEE) is requested to be disabled on this link.
21134 * If EEE is not supported on this port, then this flag
21135 * shall be ignored by the HWRM.
21137 #define HWRM_PORT_PHY_CFG_INPUT_FLAGS_EEE_DISABLE \
21140 * When this bit is set to '1' and EEE is enabled on this
21141 * link, then TX LPI is requested to be enabled on the link.
21142 * If EEE is not supported on this port, then this flag
21143 * shall be ignored by the HWRM.
21144 * If EEE is disabled on this port, then this flag shall be
21145 * ignored by the HWRM.
21147 #define HWRM_PORT_PHY_CFG_INPUT_FLAGS_EEE_TX_LPI_ENABLE \
21150 * When this bit is set to '1' and EEE is enabled on this
21151 * link, then TX LPI is requested to be disabled on the link.
21152 * If EEE is not supported on this port, then this flag
21153 * shall be ignored by the HWRM.
21154 * If EEE is disabled on this port, then this flag shall be
21155 * ignored by the HWRM.
21157 #define HWRM_PORT_PHY_CFG_INPUT_FLAGS_EEE_TX_LPI_DISABLE \
21160 * When set to 1, then the HWRM shall enable FEC autonegotitation
21161 * on this port if supported. When enabled, at least one of the
21162 * FEC modes must be advertised by enabling the fec_clause_74_enable,
21163 * fec_clause_91_enable, fec_rs544_1xn_enable, fec_rs544_ieee_enable,
21164 * fec_rs272_1xn_enable, or fec_rs272_ieee_enable flag. If none
21165 * of the FEC mode is currently enabled, the HWRM shall choose
21166 * a default advertisement setting.
21167 * The default advertisement setting can be queried by calling
21168 * hwrm_port_phy_qcfg. Note that the link speed must be
21169 * in autonegotiation mode for FEC autonegotiation to take effect.
21170 * When set to 0, then this flag shall be ignored.
21171 * If FEC autonegotiation is not supported, then the HWRM shall ignore this
21174 #define HWRM_PORT_PHY_CFG_INPUT_FLAGS_FEC_AUTONEG_ENABLE \
21177 * When set to 1, then the HWRM shall disable FEC autonegotiation
21178 * on this port and use forced FEC mode. In forced FEC mode, one
21179 * or more FEC forced settings under the same clause can be set.
21180 * When set to 0, then this flag shall be ignored.
21181 * If FEC autonegotiation is not supported, then the HWRM shall ignore this
21184 #define HWRM_PORT_PHY_CFG_INPUT_FLAGS_FEC_AUTONEG_DISABLE \
21187 * When set to 1, then the HWRM shall enable FEC CLAUSE 74 (Fire Code)
21188 * on this port if supported, by advertising FEC CLAUSE 74 if
21189 * FEC autonegotiation is enabled or force enabled otherwise.
21190 * When set to 0, then this flag shall be ignored.
21191 * If FEC CLAUSE 74 is not supported, then the HWRM shall ignore this
21194 #define HWRM_PORT_PHY_CFG_INPUT_FLAGS_FEC_CLAUSE74_ENABLE \
21197 * When set to 1, then the HWRM shall disable FEC CLAUSE 74 (Fire Code)
21198 * on this port if supported, by not advertising FEC CLAUSE 74 if
21199 * FEC autonegotiation is enabled or force disabled otherwise.
21200 * When set to 0, then this flag shall be ignored.
21201 * If FEC CLAUSE 74 is not supported, then the HWRM shall ignore this
21204 #define HWRM_PORT_PHY_CFG_INPUT_FLAGS_FEC_CLAUSE74_DISABLE \
21207 * When set to 1, then the HWRM shall enable FEC CLAUSE 91
21208 * (Reed Solomon RS(528,514) for NRZ) on this port if supported,
21209 * by advertising FEC RS(528,514) if FEC autonegotiation is enabled
21210 * or force enabled otherwise. In forced FEC mode, this flag
21211 * will only take effect if the speed is NRZ. Additional
21212 * RS544 or RS272 flags (also under clause 91) may be set for PAM4
21213 * in forced FEC mode.
21214 * When set to 0, then this flag shall be ignored.
21215 * If FEC RS(528,514) is not supported, then the HWRM shall ignore
21218 #define HWRM_PORT_PHY_CFG_INPUT_FLAGS_FEC_CLAUSE91_ENABLE \
21221 * When set to 1, then the HWRM shall disable FEC CLAUSE 91
21222 * (Reed Solomon RS(528,514) for NRZ) on this port if supported, by
21223 * not advertising RS(528,514) if FEC autonegotiation is enabled or
21224 * force disabled otherwise. When set to 0, then this flag shall be
21225 * ignored. If FEC RS(528,514) is not supported, then the HWRM
21226 * shall ignore this flag.
21228 #define HWRM_PORT_PHY_CFG_INPUT_FLAGS_FEC_CLAUSE91_DISABLE \
21231 * When this bit is set to '1', the link shall be forced to
21234 * # When this bit is set to '1", all other
21235 * command input settings related to the link speed shall
21237 * Once the link state is forced down, it can be
21238 * explicitly cleared from that state by setting this flag
21240 * # If this flag is set to '0', then the link shall be
21241 * cleared from forced down state if the link is in forced
21243 * There may be conditions (e.g. out-of-band or sideband
21244 * configuration changes for the link) outside the scope
21245 * of the HWRM implementation that may clear forced down
21248 #define HWRM_PORT_PHY_CFG_INPUT_FLAGS_FORCE_LINK_DWN \
21251 * When set to 1, then the HWRM shall enable FEC RS544_1XN
21252 * on this port if supported, by advertising FEC RS544_1XN if
21253 * FEC autonegotiation is enabled or force enabled otherwise.
21254 * In forced mode, this flag will only take effect if the speed is
21255 * PAM4. If this flag and fec_rs544_ieee_enable are set, the
21256 * HWRM shall choose one of the RS544 modes.
21257 * When set to 0, then this flag shall be ignored.
21258 * If FEC RS544_1XN is not supported, then the HWRM shall ignore this
21261 #define HWRM_PORT_PHY_CFG_INPUT_FLAGS_FEC_RS544_1XN_ENABLE \
21264 * When set to 1, then the HWRM shall disable FEC RS544_1XN
21265 * on this port if supported, by not advertising FEC RS544_1XN if
21266 * FEC autonegotiation is enabled or force disabled otherwise.
21267 * When set to 0, then this flag shall be ignored.
21268 * If FEC RS544_1XN is not supported, then the HWRM shall ignore this
21271 #define HWRM_PORT_PHY_CFG_INPUT_FLAGS_FEC_RS544_1XN_DISABLE \
21274 * When set to 1, then the HWRM shall enable FEC RS(544,514)
21275 * on this port if supported, by advertising FEC RS(544,514) if
21276 * FEC autonegotiation is enabled or force enabled otherwise.
21277 * In forced mode, this flag will only take effect if the speed is
21278 * PAM4. If this flag and fec_rs544_1xn_enable are set, the
21279 * HWRM shall choose one of the RS544 modes.
21280 * When set to 0, then this flag shall be ignored.
21281 * If FEC RS(544,514) is not supported, then the HWRM shall ignore
21284 #define HWRM_PORT_PHY_CFG_INPUT_FLAGS_FEC_RS544_IEEE_ENABLE \
21287 * When set to 1, then the HWRM shall disable FEC RS(544,514)
21288 * on this port if supported, by not advertising FEC RS(544,514) if
21289 * FEC autonegotiation is enabled or force disabled otherwise.
21290 * When set to 0, then this flag shall be ignored.
21291 * If FEC RS(544,514) is not supported, then the HWRM shall ignore
21294 #define HWRM_PORT_PHY_CFG_INPUT_FLAGS_FEC_RS544_IEEE_DISABLE \
21297 * When set to 1, then the HWRM shall enable FEC RS272_1XN
21298 * on this port if supported, by advertising FEC RS272_1XN if
21299 * FEC autonegotiation is enabled or force enabled otherwise.
21300 * In forced mode, this flag will only take effect if the speed is
21301 * PAM4. If this flag and fec_rs272_ieee_enable are set, the
21302 * HWRM shall choose one of the RS272 modes. Note that RS272
21303 * and RS544 modes cannot be set at the same time in forced FEC mode.
21304 * When set to 0, then this flag shall be ignored.
21305 * If FEC RS272_1XN is not supported, then the HWRM shall ignore this
21308 #define HWRM_PORT_PHY_CFG_INPUT_FLAGS_FEC_RS272_1XN_ENABLE \
21311 * When set to 1, then the HWRM shall disable FEC RS272_1XN
21312 * on this port if supported, by not advertising FEC RS272_1XN if
21313 * FEC autonegotiation is enabled or force disabled otherwise.
21314 * When set to 0, then this flag shall be ignored.
21315 * If FEC RS272_1XN is not supported, then the HWRM shall ignore
21318 #define HWRM_PORT_PHY_CFG_INPUT_FLAGS_FEC_RS272_1XN_DISABLE \
21321 * When set to 1, then the HWRM shall enable FEC RS(272,257)
21322 * on this port if supported, by advertising FEC RS(272,257) if
21323 * FEC autonegotiation is enabled or force enabled otherwise.
21324 * In forced mode, this flag will only take effect if the speed is
21325 * PAM4. If this flag and fec_rs272_1xn_enable are set, the
21326 * HWRM shall choose one of the RS272 modes. Note that RS272
21327 * and RS544 modes cannot be set at the same time in forced FEC mode.
21328 * When set to 0, then this flag shall be ignored.
21329 * If FEC RS(272,257) is not supported, then the HWRM shall ignore
21332 #define HWRM_PORT_PHY_CFG_INPUT_FLAGS_FEC_RS272_IEEE_ENABLE \
21335 * When set to 1, then the HWRM shall disable FEC RS(272,257)
21336 * on this port if supported, by not advertising FEC RS(272,257) if
21337 * FEC autonegotiation is enabled or force disabled otherwise.
21338 * When set to 0, then this flag shall be ignored.
21339 * If FEC RS(272,257) is not supported, then the HWRM shall ignore
21342 #define HWRM_PORT_PHY_CFG_INPUT_FLAGS_FEC_RS272_IEEE_DISABLE \
21346 * This bit must be '1' for the auto_mode field to be
21349 #define HWRM_PORT_PHY_CFG_INPUT_ENABLES_AUTO_MODE \
21352 * This bit must be '1' for the auto_duplex field to be
21355 #define HWRM_PORT_PHY_CFG_INPUT_ENABLES_AUTO_DUPLEX \
21358 * This bit must be '1' for the auto_pause field to be
21361 #define HWRM_PORT_PHY_CFG_INPUT_ENABLES_AUTO_PAUSE \
21364 * This bit must be '1' for the auto_link_speed field to be
21367 #define HWRM_PORT_PHY_CFG_INPUT_ENABLES_AUTO_LINK_SPEED \
21370 * This bit must be '1' for the auto_link_speed_mask field to be
21373 #define HWRM_PORT_PHY_CFG_INPUT_ENABLES_AUTO_LINK_SPEED_MASK \
21376 * This bit must be '1' for the wirespeed field to be
21379 #define HWRM_PORT_PHY_CFG_INPUT_ENABLES_WIRESPEED \
21382 * This bit must be '1' for the lpbk field to be
21385 #define HWRM_PORT_PHY_CFG_INPUT_ENABLES_LPBK \
21388 * This bit must be '1' for the preemphasis field to be
21391 #define HWRM_PORT_PHY_CFG_INPUT_ENABLES_PREEMPHASIS \
21394 * This bit must be '1' for the force_pause field to be
21397 #define HWRM_PORT_PHY_CFG_INPUT_ENABLES_FORCE_PAUSE \
21400 * This bit must be '1' for the eee_link_speed_mask field to be
21403 #define HWRM_PORT_PHY_CFG_INPUT_ENABLES_EEE_LINK_SPEED_MASK \
21406 * This bit must be '1' for the tx_lpi_timer field to be
21409 #define HWRM_PORT_PHY_CFG_INPUT_ENABLES_TX_LPI_TIMER \
21412 * This bit must be '1' for the force_pam4_link_speed field to be
21415 #define HWRM_PORT_PHY_CFG_INPUT_ENABLES_FORCE_PAM4_LINK_SPEED \
21418 * This bit must be '1' for the auto_pam4_link_speed_mask field to
21421 #define HWRM_PORT_PHY_CFG_INPUT_ENABLES_AUTO_PAM4_LINK_SPEED_MASK \
21423 /* Port ID of port that is to be configured. */
21426 * This is the speed that will be used if the force
21427 * bit is '1'. If unsupported speed is selected, an error
21428 * will be generated.
21430 uint16_t force_link_speed;
21431 /* 100Mb link speed */
21432 #define HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_100MB UINT32_C(0x1)
21433 /* 1Gb link speed */
21434 #define HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_1GB UINT32_C(0xa)
21435 /* 2Gb link speed */
21436 #define HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_2GB UINT32_C(0x14)
21437 /* 25Gb link speed */
21438 #define HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_2_5GB UINT32_C(0x19)
21439 /* 10Gb link speed */
21440 #define HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_10GB UINT32_C(0x64)
21441 /* 20Mb link speed */
21442 #define HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_20GB UINT32_C(0xc8)
21443 /* 25Gb link speed */
21444 #define HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_25GB UINT32_C(0xfa)
21445 /* 40Gb link speed */
21446 #define HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_40GB UINT32_C(0x190)
21447 /* 50Gb link speed */
21448 #define HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_50GB UINT32_C(0x1f4)
21449 /* 100Gb link speed */
21450 #define HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_100GB UINT32_C(0x3e8)
21451 /* 10Mb link speed */
21452 #define HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_10MB UINT32_C(0xffff)
21453 #define HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_LAST \
21454 HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_10MB
21456 * This value is used to identify what autoneg mode is
21457 * used when the link speed is not being forced.
21460 /* Disable autoneg or autoneg disabled. No speeds are selected. */
21461 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_MODE_NONE UINT32_C(0x0)
21462 /* Select all possible speeds for autoneg mode. */
21463 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_MODE_ALL_SPEEDS UINT32_C(0x1)
21465 * Select only the auto_link_speed speed for autoneg mode. This mode has
21466 * been DEPRECATED. An HWRM client should not use this mode.
21468 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_MODE_ONE_SPEED UINT32_C(0x2)
21470 * Select the auto_link_speed or any speed below that speed for autoneg.
21471 * This mode has been DEPRECATED. An HWRM client should not use this mode.
21473 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_MODE_ONE_OR_BELOW UINT32_C(0x3)
21475 * Select the speeds based on the corresponding link speed mask values
21476 * that are provided. The included speeds are specified in the
21477 * auto_link_speed and auto_pam4_link_speed fields.
21479 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_MODE_SPEED_MASK UINT32_C(0x4)
21480 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_MODE_LAST \
21481 HWRM_PORT_PHY_CFG_INPUT_AUTO_MODE_SPEED_MASK
21483 * This is the duplex setting that will be used if the autoneg_mode
21484 * is "one_speed" or "one_or_below".
21486 uint8_t auto_duplex;
21487 /* Half Duplex will be requested. */
21488 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_HALF UINT32_C(0x0)
21489 /* Full duplex will be requested. */
21490 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_FULL UINT32_C(0x1)
21491 /* Both Half and Full duplex will be requested. */
21492 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_BOTH UINT32_C(0x2)
21493 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_LAST \
21494 HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_BOTH
21496 * This value is used to configure the pause that will be
21497 * used for autonegotiation.
21498 * Add text on the usage of auto_pause and force_pause.
21500 uint8_t auto_pause;
21502 * When this bit is '1', Generation of tx pause messages
21503 * has been requested. Disabled otherwise.
21505 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_TX \
21508 * When this bit is '1', Reception of rx pause messages
21509 * has been requested. Disabled otherwise.
21511 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_RX \
21514 * When set to 1, the advertisement of pause is enabled.
21516 * # When the auto_mode is not set to none and this flag is
21517 * set to 1, then the auto_pause bits on this port are being
21518 * advertised and autoneg pause results are being interpreted.
21519 * # When the auto_mode is not set to none and this
21520 * flag is set to 0, the pause is forced as indicated in
21521 * force_pause, and also advertised as auto_pause bits, but
21522 * the autoneg results are not interpreted since the pause
21523 * configuration is being forced.
21524 * # When the auto_mode is set to none and this flag is set to
21525 * 1, auto_pause bits should be ignored and should be set to 0.
21527 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_AUTONEG_PAUSE \
21531 * This is the speed that will be used if the autoneg_mode
21532 * is "one_speed" or "one_or_below". If an unsupported speed
21533 * is selected, an error will be generated.
21535 uint16_t auto_link_speed;
21536 /* 100Mb link speed */
21537 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_100MB UINT32_C(0x1)
21538 /* 1Gb link speed */
21539 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_1GB UINT32_C(0xa)
21540 /* 2Gb link speed */
21541 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_2GB UINT32_C(0x14)
21542 /* 25Gb link speed */
21543 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_2_5GB UINT32_C(0x19)
21544 /* 10Gb link speed */
21545 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_10GB UINT32_C(0x64)
21546 /* 20Mb link speed */
21547 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_20GB UINT32_C(0xc8)
21548 /* 25Gb link speed */
21549 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_25GB UINT32_C(0xfa)
21550 /* 40Gb link speed */
21551 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_40GB UINT32_C(0x190)
21552 /* 50Gb link speed */
21553 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_50GB UINT32_C(0x1f4)
21554 /* 100Gb link speed */
21555 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_100GB UINT32_C(0x3e8)
21556 /* 10Mb link speed */
21557 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_10MB UINT32_C(0xffff)
21558 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_LAST \
21559 HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_10MB
21561 * This is a mask of link speeds that will be used if
21562 * autoneg_mode is "mask". If unsupported speed is enabled
21563 * an error will be generated.
21565 uint16_t auto_link_speed_mask;
21566 /* 100Mb link speed (Half-duplex) */
21567 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_100MBHD \
21569 /* 100Mb link speed (Full-duplex) */
21570 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_100MB \
21572 /* 1Gb link speed (Half-duplex) */
21573 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_1GBHD \
21575 /* 1Gb link speed (Full-duplex) */
21576 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_1GB \
21578 /* 2Gb link speed */
21579 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_2GB \
21581 /* 25Gb link speed */
21582 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_2_5GB \
21584 /* 10Gb link speed */
21585 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_10GB \
21587 /* 20Gb link speed */
21588 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_20GB \
21590 /* 25Gb link speed */
21591 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_25GB \
21593 /* 40Gb link speed */
21594 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_40GB \
21596 /* 50Gb link speed */
21597 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_50GB \
21599 /* 100Gb link speed */
21600 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_100GB \
21602 /* 10Mb link speed (Half-duplex) */
21603 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_10MBHD \
21605 /* 10Mb link speed (Full-duplex) */
21606 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_10MB \
21608 /* This value controls the wirespeed feature. */
21610 /* Wirespeed feature is disabled. */
21611 #define HWRM_PORT_PHY_CFG_INPUT_WIRESPEED_OFF UINT32_C(0x0)
21612 /* Wirespeed feature is enabled. */
21613 #define HWRM_PORT_PHY_CFG_INPUT_WIRESPEED_ON UINT32_C(0x1)
21614 #define HWRM_PORT_PHY_CFG_INPUT_WIRESPEED_LAST \
21615 HWRM_PORT_PHY_CFG_INPUT_WIRESPEED_ON
21616 /* This value controls the loopback setting for the PHY. */
21618 /* No loopback is selected. Normal operation. */
21619 #define HWRM_PORT_PHY_CFG_INPUT_LPBK_NONE UINT32_C(0x0)
21621 * The HW will be configured with local loopback such that
21622 * host data is sent back to the host without modification.
21624 #define HWRM_PORT_PHY_CFG_INPUT_LPBK_LOCAL UINT32_C(0x1)
21626 * The HW will be configured with remote loopback such that
21627 * port logic will send packets back out the transmitter that
21630 #define HWRM_PORT_PHY_CFG_INPUT_LPBK_REMOTE UINT32_C(0x2)
21632 * The HW will be configured with external loopback such that
21633 * host data is sent on the transmitter and based on the external
21634 * loopback connection the data will be received without modification.
21636 #define HWRM_PORT_PHY_CFG_INPUT_LPBK_EXTERNAL UINT32_C(0x3)
21637 #define HWRM_PORT_PHY_CFG_INPUT_LPBK_LAST \
21638 HWRM_PORT_PHY_CFG_INPUT_LPBK_EXTERNAL
21640 * This value is used to configure the pause that will be
21641 * used for force mode.
21643 uint8_t force_pause;
21645 * When this bit is '1', Generation of tx pause messages
21646 * is supported. Disabled otherwise.
21648 #define HWRM_PORT_PHY_CFG_INPUT_FORCE_PAUSE_TX UINT32_C(0x1)
21650 * When this bit is '1', Reception of rx pause messages
21651 * is supported. Disabled otherwise.
21653 #define HWRM_PORT_PHY_CFG_INPUT_FORCE_PAUSE_RX UINT32_C(0x2)
21656 * This value controls the pre-emphasis to be used for the
21657 * link. Driver should not set this value (use
21658 * enable.preemphasis = 0) unless driver is sure of setting.
21659 * Normally HWRM FW will determine proper pre-emphasis.
21661 uint32_t preemphasis;
21663 * Setting for link speed mask that is used to
21664 * advertise speeds during autonegotiation when EEE is enabled.
21665 * This field is valid only when EEE is enabled.
21666 * The speeds specified in this field shall be a subset of
21667 * speeds specified in auto_link_speed_mask.
21668 * If EEE is enabled,then at least one speed shall be provided
21671 uint16_t eee_link_speed_mask;
21673 #define HWRM_PORT_PHY_CFG_INPUT_EEE_LINK_SPEED_MASK_RSVD1 \
21675 /* 100Mb link speed (Full-duplex) */
21676 #define HWRM_PORT_PHY_CFG_INPUT_EEE_LINK_SPEED_MASK_100MB \
21679 #define HWRM_PORT_PHY_CFG_INPUT_EEE_LINK_SPEED_MASK_RSVD2 \
21681 /* 1Gb link speed (Full-duplex) */
21682 #define HWRM_PORT_PHY_CFG_INPUT_EEE_LINK_SPEED_MASK_1GB \
21685 #define HWRM_PORT_PHY_CFG_INPUT_EEE_LINK_SPEED_MASK_RSVD3 \
21688 #define HWRM_PORT_PHY_CFG_INPUT_EEE_LINK_SPEED_MASK_RSVD4 \
21690 /* 10Gb link speed */
21691 #define HWRM_PORT_PHY_CFG_INPUT_EEE_LINK_SPEED_MASK_10GB \
21694 * This is the speed that will be used if the force and force_pam4
21695 * bits are '1'. If unsupported speed is selected, an error
21696 * will be generated.
21698 uint16_t force_pam4_link_speed;
21699 /* 50Gb link speed */
21700 #define HWRM_PORT_PHY_CFG_INPUT_FORCE_PAM4_LINK_SPEED_50GB \
21702 /* 100Gb link speed */
21703 #define HWRM_PORT_PHY_CFG_INPUT_FORCE_PAM4_LINK_SPEED_100GB \
21705 /* 200Gb link speed */
21706 #define HWRM_PORT_PHY_CFG_INPUT_FORCE_PAM4_LINK_SPEED_200GB \
21708 #define HWRM_PORT_PHY_CFG_INPUT_FORCE_PAM4_LINK_SPEED_LAST \
21709 HWRM_PORT_PHY_CFG_INPUT_FORCE_PAM4_LINK_SPEED_200GB
21711 * Requested setting of TX LPI timer in microseconds.
21712 * This field is valid only when EEE is enabled and TX LPI is
21715 uint32_t tx_lpi_timer;
21716 #define HWRM_PORT_PHY_CFG_INPUT_TX_LPI_TIMER_MASK UINT32_C(0xffffff)
21717 #define HWRM_PORT_PHY_CFG_INPUT_TX_LPI_TIMER_SFT 0
21718 /* This field specifies which PAM4 speeds are enabled for auto mode. */
21719 uint16_t auto_link_pam4_speed_mask;
21720 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_PAM4_SPEED_MASK_50G \
21722 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_PAM4_SPEED_MASK_100G \
21724 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_PAM4_SPEED_MASK_200G \
21726 uint8_t unused_2[2];
21729 /* hwrm_port_phy_cfg_output (size:128b/16B) */
21730 struct hwrm_port_phy_cfg_output {
21731 /* The specific error status for the command. */
21732 uint16_t error_code;
21733 /* The HWRM command request type. */
21735 /* The sequence ID from the original command. */
21737 /* The length of the response data in number of bytes. */
21739 uint8_t unused_0[7];
21741 * This field is used in Output records to indicate that the output
21742 * is completely written to RAM. This field should be read as '1'
21743 * to indicate that the output has been completely written.
21744 * When writing a command completion or response to an internal processor,
21745 * the order of writes has to be such that this field is written last.
21750 /* hwrm_port_phy_cfg_cmd_err (size:64b/8B) */
21751 struct hwrm_port_phy_cfg_cmd_err {
21753 * command specific error codes that goes to
21754 * the cmd_err field in Common HWRM Error Response.
21757 /* Unknown error */
21758 #define HWRM_PORT_PHY_CFG_CMD_ERR_CODE_UNKNOWN UINT32_C(0x0)
21759 /* Unable to complete operation due to invalid speed */
21760 #define HWRM_PORT_PHY_CFG_CMD_ERR_CODE_ILLEGAL_SPEED UINT32_C(0x1)
21762 * retry the command since the phy is not ready.
21763 * retry count is returned in opaque_0.
21764 * This is only valid for the first command and
21765 * this value will not change for successive calls.
21766 * but if a 0 is returned at any time then this should
21767 * be treated as an un recoverable failure,
21769 * retry interval in milli seconds is returned in opaque_1.
21770 * This specifies the time that user should wait before
21771 * issuing the next port_phy_cfg command.
21773 #define HWRM_PORT_PHY_CFG_CMD_ERR_CODE_RETRY UINT32_C(0x2)
21774 #define HWRM_PORT_PHY_CFG_CMD_ERR_CODE_LAST \
21775 HWRM_PORT_PHY_CFG_CMD_ERR_CODE_RETRY
21776 uint8_t unused_0[7];
21779 /**********************
21780 * hwrm_port_phy_qcfg *
21781 **********************/
21784 /* hwrm_port_phy_qcfg_input (size:192b/24B) */
21785 struct hwrm_port_phy_qcfg_input {
21786 /* The HWRM command request type. */
21789 * The completion ring to send the completion event on. This should
21790 * be the NQ ID returned from the `nq_alloc` HWRM command.
21792 uint16_t cmpl_ring;
21794 * The sequence ID is used by the driver for tracking multiple
21795 * commands. This ID is treated as opaque data by the firmware and
21796 * the value is returned in the `hwrm_resp_hdr` upon completion.
21800 * The target ID of the command:
21801 * * 0x0-0xFFF8 - The function ID
21802 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
21803 * * 0xFFFD - Reserved for user-space HWRM interface
21806 uint16_t target_id;
21808 * A physical address pointer pointing to a host buffer that the
21809 * command's response data will be written. This can be either a host
21810 * physical address (HPA) or a guest physical address (GPA) and must
21811 * point to a physically contiguous block of memory.
21813 uint64_t resp_addr;
21814 /* Port ID of port that is to be queried. */
21816 uint8_t unused_0[6];
21819 /* hwrm_port_phy_qcfg_output (size:768b/96B) */
21820 struct hwrm_port_phy_qcfg_output {
21821 /* The specific error status for the command. */
21822 uint16_t error_code;
21823 /* The HWRM command request type. */
21825 /* The sequence ID from the original command. */
21827 /* The length of the response data in number of bytes. */
21829 /* This value indicates the current link status. */
21831 /* There is no link or cable detected. */
21832 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_NO_LINK UINT32_C(0x0)
21833 /* There is no link, but a cable has been detected. */
21834 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SIGNAL UINT32_C(0x1)
21835 /* There is a link. */
21836 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_LINK UINT32_C(0x2)
21837 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_LAST \
21838 HWRM_PORT_PHY_QCFG_OUTPUT_LINK_LINK
21839 uint8_t active_fec_signal_mode;
21841 * This value indicates the current link signaling mode of the
21844 #define HWRM_PORT_PHY_QCFG_OUTPUT_SIGNAL_MODE_MASK \
21846 #define HWRM_PORT_PHY_QCFG_OUTPUT_SIGNAL_MODE_SFT 0
21847 /* NRZ signaling */
21848 #define HWRM_PORT_PHY_QCFG_OUTPUT_SIGNAL_MODE_NRZ \
21850 /* PAM4 signaling */
21851 #define HWRM_PORT_PHY_QCFG_OUTPUT_SIGNAL_MODE_PAM4 \
21853 #define HWRM_PORT_PHY_QCFG_OUTPUT_SIGNAL_MODE_LAST \
21854 HWRM_PORT_PHY_QCFG_OUTPUT_SIGNAL_MODE_PAM4
21855 /* This value indicates the current active FEC mode. */
21856 #define HWRM_PORT_PHY_QCFG_OUTPUT_ACTIVE_FEC_MASK \
21858 #define HWRM_PORT_PHY_QCFG_OUTPUT_ACTIVE_FEC_SFT 4
21859 /* No active FEC */
21860 #define HWRM_PORT_PHY_QCFG_OUTPUT_ACTIVE_FEC_FEC_NONE_ACTIVE \
21861 (UINT32_C(0x0) << 4)
21862 /* FEC CLAUSE 74 (Fire Code) active, autonegotiated or forced. */
21863 #define HWRM_PORT_PHY_QCFG_OUTPUT_ACTIVE_FEC_FEC_CLAUSE74_ACTIVE \
21864 (UINT32_C(0x1) << 4)
21865 /* FEC CLAUSE 91 RS(528,514) active, autonegoatiated or forced. */
21866 #define HWRM_PORT_PHY_QCFG_OUTPUT_ACTIVE_FEC_FEC_CLAUSE91_ACTIVE \
21867 (UINT32_C(0x2) << 4)
21868 /* FEC RS544_1XN active, autonegoatiated or forced. */
21869 #define HWRM_PORT_PHY_QCFG_OUTPUT_ACTIVE_FEC_FEC_RS544_1XN_ACTIVE \
21870 (UINT32_C(0x3) << 4)
21871 /* FEC RS(544,528) active, autonegoatiated or forced. */
21872 #define HWRM_PORT_PHY_QCFG_OUTPUT_ACTIVE_FEC_FEC_RS544_IEEE_ACTIVE \
21873 (UINT32_C(0x4) << 4)
21874 /* FEC RS272_1XN active, autonegotiated or forced. */
21875 #define HWRM_PORT_PHY_QCFG_OUTPUT_ACTIVE_FEC_FEC_RS272_1XN_ACTIVE \
21876 (UINT32_C(0x5) << 4)
21877 /* FEC RS(272,257) active, autonegoatiated or forced. */
21878 #define HWRM_PORT_PHY_QCFG_OUTPUT_ACTIVE_FEC_FEC_RS272_IEEE_ACTIVE \
21879 (UINT32_C(0x6) << 4)
21880 #define HWRM_PORT_PHY_QCFG_OUTPUT_ACTIVE_FEC_LAST \
21881 HWRM_PORT_PHY_QCFG_OUTPUT_ACTIVE_FEC_FEC_RS272_IEEE_ACTIVE
21883 * This value indicates the current link speed of the connection.
21884 * The signal_mode field indicates if the link is using
21885 * NRZ or PAM4 signaling.
21887 uint16_t link_speed;
21888 /* 100Mb link speed */
21889 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_100MB UINT32_C(0x1)
21890 /* 1Gb link speed */
21891 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_1GB UINT32_C(0xa)
21892 /* 2Gb link speed */
21893 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_2GB UINT32_C(0x14)
21894 /* 25Gb link speed */
21895 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_2_5GB UINT32_C(0x19)
21896 /* 10Gb link speed */
21897 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_10GB UINT32_C(0x64)
21898 /* 20Mb link speed */
21899 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_20GB UINT32_C(0xc8)
21900 /* 25Gb link speed */
21901 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_25GB UINT32_C(0xfa)
21902 /* 40Gb link speed */
21903 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_40GB UINT32_C(0x190)
21904 /* 50Gb link speed */
21905 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_50GB UINT32_C(0x1f4)
21906 /* 100Gb link speed */
21907 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_100GB UINT32_C(0x3e8)
21908 /* 200Gb link speed */
21909 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_200GB UINT32_C(0x7d0)
21910 /* 10Mb link speed */
21911 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_10MB UINT32_C(0xffff)
21912 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_LAST \
21913 HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_10MB
21915 * This value is indicates the duplex of the current
21918 uint8_t duplex_cfg;
21919 /* Half Duplex connection. */
21920 #define HWRM_PORT_PHY_QCFG_OUTPUT_DUPLEX_CFG_HALF UINT32_C(0x0)
21921 /* Full duplex connection. */
21922 #define HWRM_PORT_PHY_QCFG_OUTPUT_DUPLEX_CFG_FULL UINT32_C(0x1)
21923 #define HWRM_PORT_PHY_QCFG_OUTPUT_DUPLEX_CFG_LAST \
21924 HWRM_PORT_PHY_QCFG_OUTPUT_DUPLEX_CFG_FULL
21926 * This value is used to indicate the current
21927 * pause configuration. When autoneg is enabled, this value
21928 * represents the autoneg results of pause configuration.
21932 * When this bit is '1', Generation of tx pause messages
21933 * is supported. Disabled otherwise.
21935 #define HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_TX UINT32_C(0x1)
21937 * When this bit is '1', Reception of rx pause messages
21938 * is supported. Disabled otherwise.
21940 #define HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_RX UINT32_C(0x2)
21942 * The supported speeds for the port. This is a bit mask.
21943 * For each speed that is supported, the corresponding
21944 * bit will be set to '1'.
21946 uint16_t support_speeds;
21947 /* 100Mb link speed (Half-duplex) */
21948 #define HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_100MBHD \
21950 /* 100Mb link speed (Full-duplex) */
21951 #define HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_100MB \
21953 /* 1Gb link speed (Half-duplex) */
21954 #define HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_1GBHD \
21956 /* 1Gb link speed (Full-duplex) */
21957 #define HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_1GB \
21959 /* 2Gb link speed */
21960 #define HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_2GB \
21962 /* 25Gb link speed */
21963 #define HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_2_5GB \
21965 /* 10Gb link speed */
21966 #define HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_10GB \
21968 /* 20Gb link speed */
21969 #define HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_20GB \
21971 /* 25Gb link speed */
21972 #define HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_25GB \
21974 /* 40Gb link speed */
21975 #define HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_40GB \
21977 /* 50Gb link speed */
21978 #define HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_50GB \
21980 /* 100Gb link speed */
21981 #define HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_100GB \
21983 /* 10Mb link speed (Half-duplex) */
21984 #define HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_10MBHD \
21986 /* 10Mb link speed (Full-duplex) */
21987 #define HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_10MB \
21990 * Current setting of forced link speed.
21991 * When the link speed is not being forced, this
21992 * value shall be set to 0.
21994 uint16_t force_link_speed;
21995 /* 100Mb link speed */
21996 #define HWRM_PORT_PHY_QCFG_OUTPUT_FORCE_LINK_SPEED_100MB UINT32_C(0x1)
21997 /* 1Gb link speed */
21998 #define HWRM_PORT_PHY_QCFG_OUTPUT_FORCE_LINK_SPEED_1GB UINT32_C(0xa)
21999 /* 2Gb link speed */
22000 #define HWRM_PORT_PHY_QCFG_OUTPUT_FORCE_LINK_SPEED_2GB UINT32_C(0x14)
22001 /* 25Gb link speed */
22002 #define HWRM_PORT_PHY_QCFG_OUTPUT_FORCE_LINK_SPEED_2_5GB UINT32_C(0x19)
22003 /* 10Gb link speed */
22004 #define HWRM_PORT_PHY_QCFG_OUTPUT_FORCE_LINK_SPEED_10GB UINT32_C(0x64)
22005 /* 20Mb link speed */
22006 #define HWRM_PORT_PHY_QCFG_OUTPUT_FORCE_LINK_SPEED_20GB UINT32_C(0xc8)
22007 /* 25Gb link speed */
22008 #define HWRM_PORT_PHY_QCFG_OUTPUT_FORCE_LINK_SPEED_25GB UINT32_C(0xfa)
22009 /* 40Gb link speed */
22010 #define HWRM_PORT_PHY_QCFG_OUTPUT_FORCE_LINK_SPEED_40GB \
22012 /* 50Gb link speed */
22013 #define HWRM_PORT_PHY_QCFG_OUTPUT_FORCE_LINK_SPEED_50GB \
22015 /* 100Gb link speed */
22016 #define HWRM_PORT_PHY_QCFG_OUTPUT_FORCE_LINK_SPEED_100GB \
22018 /* 10Mb link speed */
22019 #define HWRM_PORT_PHY_QCFG_OUTPUT_FORCE_LINK_SPEED_10MB \
22021 #define HWRM_PORT_PHY_QCFG_OUTPUT_FORCE_LINK_SPEED_LAST \
22022 HWRM_PORT_PHY_QCFG_OUTPUT_FORCE_LINK_SPEED_10MB
22023 /* Current setting of auto negotiation mode. */
22025 /* Disable autoneg or autoneg disabled. No speeds are selected. */
22026 #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_MODE_NONE UINT32_C(0x0)
22027 /* Select all possible speeds for autoneg mode. */
22028 #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_MODE_ALL_SPEEDS UINT32_C(0x1)
22030 * Select only the auto_link_speed speed for autoneg mode. This mode has
22031 * been DEPRECATED. An HWRM client should not use this mode.
22033 #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_MODE_ONE_SPEED UINT32_C(0x2)
22035 * Select the auto_link_speed or any speed below that speed for autoneg.
22036 * This mode has been DEPRECATED. An HWRM client should not use this mode.
22038 #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_MODE_ONE_OR_BELOW UINT32_C(0x3)
22040 * Select the speeds based on the corresponding link speed mask value
22041 * that is provided.
22043 #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_MODE_SPEED_MASK UINT32_C(0x4)
22044 #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_MODE_LAST \
22045 HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_MODE_SPEED_MASK
22047 * Current setting of pause autonegotiation.
22048 * Move autoneg_pause flag here.
22050 uint8_t auto_pause;
22052 * When this bit is '1', Generation of tx pause messages
22053 * has been requested. Disabled otherwise.
22055 #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_PAUSE_TX \
22058 * When this bit is '1', Reception of rx pause messages
22059 * has been requested. Disabled otherwise.
22061 #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_PAUSE_RX \
22064 * When set to 1, the advertisement of pause is enabled.
22066 * # When the auto_mode is not set to none and this flag is
22067 * set to 1, then the auto_pause bits on this port are being
22068 * advertised and autoneg pause results are being interpreted.
22069 * # When the auto_mode is not set to none and this
22070 * flag is set to 0, the pause is forced as indicated in
22071 * force_pause, and also advertised as auto_pause bits, but
22072 * the autoneg results are not interpreted since the pause
22073 * configuration is being forced.
22074 * # When the auto_mode is set to none and this flag is set to
22075 * 1, auto_pause bits should be ignored and should be set to 0.
22077 #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_PAUSE_AUTONEG_PAUSE \
22080 * Current setting for auto_link_speed. This field is only
22081 * valid when auto_mode is set to "one_speed" or "one_or_below".
22083 uint16_t auto_link_speed;
22084 /* 100Mb link speed */
22085 #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_100MB UINT32_C(0x1)
22086 /* 1Gb link speed */
22087 #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_1GB UINT32_C(0xa)
22088 /* 2Gb link speed */
22089 #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_2GB UINT32_C(0x14)
22090 /* 25Gb link speed */
22091 #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_2_5GB UINT32_C(0x19)
22092 /* 10Gb link speed */
22093 #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_10GB UINT32_C(0x64)
22094 /* 20Mb link speed */
22095 #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_20GB UINT32_C(0xc8)
22096 /* 25Gb link speed */
22097 #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_25GB UINT32_C(0xfa)
22098 /* 40Gb link speed */
22099 #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_40GB UINT32_C(0x190)
22100 /* 50Gb link speed */
22101 #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_50GB UINT32_C(0x1f4)
22102 /* 100Gb link speed */
22103 #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_100GB UINT32_C(0x3e8)
22104 /* 10Mb link speed */
22105 #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_10MB \
22107 #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_LAST \
22108 HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_10MB
22110 * Current setting for auto_link_speed_mask that is used to
22111 * advertise speeds during autonegotiation.
22112 * This field is only valid when auto_mode is set to "mask".
22113 * The speeds specified in this field shall be a subset of
22114 * supported speeds on this port.
22116 uint16_t auto_link_speed_mask;
22117 /* 100Mb link speed (Half-duplex) */
22118 #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_MASK_100MBHD \
22120 /* 100Mb link speed (Full-duplex) */
22121 #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_MASK_100MB \
22123 /* 1Gb link speed (Half-duplex) */
22124 #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_MASK_1GBHD \
22126 /* 1Gb link speed (Full-duplex) */
22127 #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_MASK_1GB \
22129 /* 2Gb link speed */
22130 #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_MASK_2GB \
22132 /* 25Gb link speed */
22133 #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_MASK_2_5GB \
22135 /* 10Gb link speed */
22136 #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_MASK_10GB \
22138 /* 20Gb link speed */
22139 #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_MASK_20GB \
22141 /* 25Gb link speed */
22142 #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_MASK_25GB \
22144 /* 40Gb link speed */
22145 #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_MASK_40GB \
22147 /* 50Gb link speed */
22148 #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_MASK_50GB \
22150 /* 100Gb link speed */
22151 #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_MASK_100GB \
22153 /* 10Mb link speed (Half-duplex) */
22154 #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_MASK_10MBHD \
22156 /* 10Mb link speed (Full-duplex) */
22157 #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_MASK_10MB \
22159 /* Current setting for wirespeed. */
22161 /* Wirespeed feature is disabled. */
22162 #define HWRM_PORT_PHY_QCFG_OUTPUT_WIRESPEED_OFF UINT32_C(0x0)
22163 /* Wirespeed feature is enabled. */
22164 #define HWRM_PORT_PHY_QCFG_OUTPUT_WIRESPEED_ON UINT32_C(0x1)
22165 #define HWRM_PORT_PHY_QCFG_OUTPUT_WIRESPEED_LAST \
22166 HWRM_PORT_PHY_QCFG_OUTPUT_WIRESPEED_ON
22167 /* Current setting for loopback. */
22169 /* No loopback is selected. Normal operation. */
22170 #define HWRM_PORT_PHY_QCFG_OUTPUT_LPBK_NONE UINT32_C(0x0)
22172 * The HW will be configured with local loopback such that
22173 * host data is sent back to the host without modification.
22175 #define HWRM_PORT_PHY_QCFG_OUTPUT_LPBK_LOCAL UINT32_C(0x1)
22177 * The HW will be configured with remote loopback such that
22178 * port logic will send packets back out the transmitter that
22181 #define HWRM_PORT_PHY_QCFG_OUTPUT_LPBK_REMOTE UINT32_C(0x2)
22183 * The HW will be configured with external loopback such that
22184 * host data is sent on the transmitter and based on the external
22185 * loopback connection the data will be received without modification.
22187 #define HWRM_PORT_PHY_QCFG_OUTPUT_LPBK_EXTERNAL UINT32_C(0x3)
22188 #define HWRM_PORT_PHY_QCFG_OUTPUT_LPBK_LAST \
22189 HWRM_PORT_PHY_QCFG_OUTPUT_LPBK_EXTERNAL
22191 * Current setting of forced pause.
22192 * When the pause configuration is not being forced, then
22193 * this value shall be set to 0.
22195 uint8_t force_pause;
22197 * When this bit is '1', Generation of tx pause messages
22198 * is supported. Disabled otherwise.
22200 #define HWRM_PORT_PHY_QCFG_OUTPUT_FORCE_PAUSE_TX UINT32_C(0x1)
22202 * When this bit is '1', Reception of rx pause messages
22203 * is supported. Disabled otherwise.
22205 #define HWRM_PORT_PHY_QCFG_OUTPUT_FORCE_PAUSE_RX UINT32_C(0x2)
22207 * This value indicates the current status of the optics module on
22210 uint8_t module_status;
22211 /* Module is inserted and accepted */
22212 #define HWRM_PORT_PHY_QCFG_OUTPUT_MODULE_STATUS_NONE \
22214 /* Module is rejected and transmit side Laser is disabled. */
22215 #define HWRM_PORT_PHY_QCFG_OUTPUT_MODULE_STATUS_DISABLETX \
22217 /* Module mismatch warning. */
22218 #define HWRM_PORT_PHY_QCFG_OUTPUT_MODULE_STATUS_WARNINGMSG \
22220 /* Module is rejected and powered down. */
22221 #define HWRM_PORT_PHY_QCFG_OUTPUT_MODULE_STATUS_PWRDOWN \
22223 /* Module is not inserted. */
22224 #define HWRM_PORT_PHY_QCFG_OUTPUT_MODULE_STATUS_NOTINSERTED \
22226 /* Module is powered down because of over current fault. */
22227 #define HWRM_PORT_PHY_QCFG_OUTPUT_MODULE_STATUS_CURRENTFAULT \
22229 /* Module status is not applicable. */
22230 #define HWRM_PORT_PHY_QCFG_OUTPUT_MODULE_STATUS_NOTAPPLICABLE \
22232 #define HWRM_PORT_PHY_QCFG_OUTPUT_MODULE_STATUS_LAST \
22233 HWRM_PORT_PHY_QCFG_OUTPUT_MODULE_STATUS_NOTAPPLICABLE
22234 /* Current setting for preemphasis. */
22235 uint32_t preemphasis;
22236 /* This field represents the major version of the PHY. */
22238 /* This field represents the minor version of the PHY. */
22240 /* This field represents the build version of the PHY. */
22242 /* This value represents a PHY type. */
22245 #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_UNKNOWN \
22248 #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_BASECR \
22250 /* BASE-KR4 (Deprecated) */
22251 #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_BASEKR4 \
22254 #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_BASELR \
22257 #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_BASESR \
22259 /* BASE-KR2 (Deprecated) */
22260 #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_BASEKR2 \
22263 #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_BASEKX \
22266 #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_BASEKR \
22269 #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_BASET \
22271 /* EEE capable BASE-T */
22272 #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_BASETE \
22274 /* SGMII connected external PHY */
22275 #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_SGMIIEXTPHY \
22277 /* 25G_BASECR_CA_L */
22278 #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_25G_BASECR_CA_L \
22280 /* 25G_BASECR_CA_S */
22281 #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_25G_BASECR_CA_S \
22283 /* 25G_BASECR_CA_N */
22284 #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_25G_BASECR_CA_N \
22287 #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_25G_BASESR \
22290 #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_100G_BASECR4 \
22293 #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_100G_BASESR4 \
22296 #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_100G_BASELR4 \
22299 #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_100G_BASEER4 \
22301 /* 100G_BASESR10 */
22302 #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_100G_BASESR10 \
22305 #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_40G_BASECR4 \
22308 #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_40G_BASESR4 \
22311 #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_40G_BASELR4 \
22314 #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_40G_BASEER4 \
22316 /* 40G_ACTIVE_CABLE */
22317 #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_40G_ACTIVE_CABLE \
22320 #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_1G_BASET \
22323 #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_1G_BASESX \
22326 #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_1G_BASECX \
22329 #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_200G_BASECR4 \
22332 #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_200G_BASESR4 \
22335 #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_200G_BASELR4 \
22338 #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_200G_BASEER4 \
22341 #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_50G_BASECR \
22344 #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_50G_BASESR \
22347 #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_50G_BASELR \
22350 #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_50G_BASEER \
22353 #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_100G_BASECR2 \
22356 #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_100G_BASESR2 \
22359 #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_100G_BASELR2 \
22362 #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_100G_BASEER2 \
22364 #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_LAST \
22365 HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_100G_BASEER2
22366 /* This value represents a media type. */
22367 uint8_t media_type;
22369 #define HWRM_PORT_PHY_QCFG_OUTPUT_MEDIA_TYPE_UNKNOWN UINT32_C(0x0)
22371 #define HWRM_PORT_PHY_QCFG_OUTPUT_MEDIA_TYPE_TP UINT32_C(0x1)
22372 /* Direct Attached Copper */
22373 #define HWRM_PORT_PHY_QCFG_OUTPUT_MEDIA_TYPE_DAC UINT32_C(0x2)
22375 #define HWRM_PORT_PHY_QCFG_OUTPUT_MEDIA_TYPE_FIBRE UINT32_C(0x3)
22376 #define HWRM_PORT_PHY_QCFG_OUTPUT_MEDIA_TYPE_LAST \
22377 HWRM_PORT_PHY_QCFG_OUTPUT_MEDIA_TYPE_FIBRE
22378 /* This value represents a transceiver type. */
22379 uint8_t xcvr_pkg_type;
22380 /* PHY and MAC are in the same package */
22381 #define HWRM_PORT_PHY_QCFG_OUTPUT_XCVR_PKG_TYPE_XCVR_INTERNAL \
22383 /* PHY and MAC are in different packages */
22384 #define HWRM_PORT_PHY_QCFG_OUTPUT_XCVR_PKG_TYPE_XCVR_EXTERNAL \
22386 #define HWRM_PORT_PHY_QCFG_OUTPUT_XCVR_PKG_TYPE_LAST \
22387 HWRM_PORT_PHY_QCFG_OUTPUT_XCVR_PKG_TYPE_XCVR_EXTERNAL
22388 uint8_t eee_config_phy_addr;
22389 /* This field represents PHY address. */
22390 #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_ADDR_MASK \
22392 #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_ADDR_SFT 0
22394 * This field represents flags related to EEE configuration.
22395 * These EEE configuration flags are valid only when the
22396 * auto_mode is not set to none (in other words autonegotiation
22399 #define HWRM_PORT_PHY_QCFG_OUTPUT_EEE_CONFIG_MASK \
22401 #define HWRM_PORT_PHY_QCFG_OUTPUT_EEE_CONFIG_SFT 5
22403 * When set to 1, Energy Efficient Ethernet (EEE) mode is enabled.
22404 * Speeds for autoneg with EEE mode enabled
22405 * are based on eee_link_speed_mask.
22407 #define HWRM_PORT_PHY_QCFG_OUTPUT_EEE_CONFIG_EEE_ENABLED \
22410 * This flag is valid only when eee_enabled is set to 1.
22412 * # If eee_enabled is set to 0, then EEE mode is disabled
22413 * and this flag shall be ignored.
22414 * # If eee_enabled is set to 1 and this flag is set to 1,
22415 * then Energy Efficient Ethernet (EEE) mode is enabled
22417 * # If eee_enabled is set to 1 and this flag is set to 0,
22418 * then Energy Efficient Ethernet (EEE) mode is enabled
22419 * but is currently not in use.
22421 #define HWRM_PORT_PHY_QCFG_OUTPUT_EEE_CONFIG_EEE_ACTIVE \
22424 * This flag is valid only when eee_enabled is set to 1.
22426 * # If eee_enabled is set to 0, then EEE mode is disabled
22427 * and this flag shall be ignored.
22428 * # If eee_enabled is set to 1 and this flag is set to 1,
22429 * then Energy Efficient Ethernet (EEE) mode is enabled
22430 * and TX LPI is enabled.
22431 * # If eee_enabled is set to 1 and this flag is set to 0,
22432 * then Energy Efficient Ethernet (EEE) mode is enabled
22433 * but TX LPI is disabled.
22435 #define HWRM_PORT_PHY_QCFG_OUTPUT_EEE_CONFIG_EEE_TX_LPI \
22438 * When set to 1, the parallel detection is used to determine
22439 * the speed of the link partner.
22441 * Parallel detection is used when a autonegotiation capable
22442 * device is connected to a link partner that is not capable
22443 * of autonegotiation.
22445 uint8_t parallel_detect;
22447 * When set to 1, the parallel detection is used to determine
22448 * the speed of the link partner.
22450 * Parallel detection is used when a autonegotiation capable
22451 * device is connected to a link partner that is not capable
22452 * of autonegotiation.
22454 #define HWRM_PORT_PHY_QCFG_OUTPUT_PARALLEL_DETECT UINT32_C(0x1)
22456 * The advertised speeds for the port by the link partner.
22457 * Each advertised speed will be set to '1'.
22459 uint16_t link_partner_adv_speeds;
22460 /* 100Mb link speed (Half-duplex) */
22461 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_SPEEDS_100MBHD \
22463 /* 100Mb link speed (Full-duplex) */
22464 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_SPEEDS_100MB \
22466 /* 1Gb link speed (Half-duplex) */
22467 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_SPEEDS_1GBHD \
22469 /* 1Gb link speed (Full-duplex) */
22470 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_SPEEDS_1GB \
22472 /* 2Gb link speed */
22473 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_SPEEDS_2GB \
22475 /* 25Gb link speed */
22476 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_SPEEDS_2_5GB \
22478 /* 10Gb link speed */
22479 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_SPEEDS_10GB \
22481 /* 20Gb link speed */
22482 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_SPEEDS_20GB \
22484 /* 25Gb link speed */
22485 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_SPEEDS_25GB \
22487 /* 40Gb link speed */
22488 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_SPEEDS_40GB \
22490 /* 50Gb link speed */
22491 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_SPEEDS_50GB \
22493 /* 100Gb link speed */
22494 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_SPEEDS_100GB \
22496 /* 10Mb link speed (Half-duplex) */
22497 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_SPEEDS_10MBHD \
22499 /* 10Mb link speed (Full-duplex) */
22500 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_SPEEDS_10MB \
22503 * The advertised autoneg for the port by the link partner.
22504 * This field is deprecated and should be set to 0.
22506 uint8_t link_partner_adv_auto_mode;
22507 /* Disable autoneg or autoneg disabled. No speeds are selected. */
22508 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_AUTO_MODE_NONE \
22510 /* Select all possible speeds for autoneg mode. */
22511 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_AUTO_MODE_ALL_SPEEDS \
22514 * Select only the auto_link_speed speed for autoneg mode. This mode has
22515 * been DEPRECATED. An HWRM client should not use this mode.
22517 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_AUTO_MODE_ONE_SPEED \
22520 * Select the auto_link_speed or any speed below that speed for autoneg.
22521 * This mode has been DEPRECATED. An HWRM client should not use this mode.
22523 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_AUTO_MODE_ONE_OR_BELOW \
22526 * Select the speeds based on the corresponding link speed mask value
22527 * that is provided.
22529 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_AUTO_MODE_SPEED_MASK \
22531 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_AUTO_MODE_LAST \
22532 HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_AUTO_MODE_SPEED_MASK
22533 /* The advertised pause settings on the port by the link partner. */
22534 uint8_t link_partner_adv_pause;
22536 * When this bit is '1', Generation of tx pause messages
22537 * is supported. Disabled otherwise.
22539 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_PAUSE_TX \
22542 * When this bit is '1', Reception of rx pause messages
22543 * is supported. Disabled otherwise.
22545 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_PAUSE_RX \
22548 * Current setting for link speed mask that is used to
22549 * advertise speeds during autonegotiation when EEE is enabled.
22550 * This field is valid only when eee_enabled flags is set to 1.
22551 * The speeds specified in this field shall be a subset of
22552 * speeds specified in auto_link_speed_mask.
22554 uint16_t adv_eee_link_speed_mask;
22556 #define HWRM_PORT_PHY_QCFG_OUTPUT_ADV_EEE_LINK_SPEED_MASK_RSVD1 \
22558 /* 100Mb link speed (Full-duplex) */
22559 #define HWRM_PORT_PHY_QCFG_OUTPUT_ADV_EEE_LINK_SPEED_MASK_100MB \
22562 #define HWRM_PORT_PHY_QCFG_OUTPUT_ADV_EEE_LINK_SPEED_MASK_RSVD2 \
22564 /* 1Gb link speed (Full-duplex) */
22565 #define HWRM_PORT_PHY_QCFG_OUTPUT_ADV_EEE_LINK_SPEED_MASK_1GB \
22568 #define HWRM_PORT_PHY_QCFG_OUTPUT_ADV_EEE_LINK_SPEED_MASK_RSVD3 \
22571 #define HWRM_PORT_PHY_QCFG_OUTPUT_ADV_EEE_LINK_SPEED_MASK_RSVD4 \
22573 /* 10Gb link speed */
22574 #define HWRM_PORT_PHY_QCFG_OUTPUT_ADV_EEE_LINK_SPEED_MASK_10GB \
22577 * Current setting for link speed mask that is advertised by
22578 * the link partner when EEE is enabled.
22579 * This field is valid only when eee_enabled flags is set to 1.
22581 uint16_t link_partner_adv_eee_link_speed_mask;
22583 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_EEE_LINK_SPEED_MASK_RSVD1 \
22585 /* 100Mb link speed (Full-duplex) */
22586 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_EEE_LINK_SPEED_MASK_100MB \
22589 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_EEE_LINK_SPEED_MASK_RSVD2 \
22591 /* 1Gb link speed (Full-duplex) */
22592 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_EEE_LINK_SPEED_MASK_1GB \
22595 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_EEE_LINK_SPEED_MASK_RSVD3 \
22598 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_EEE_LINK_SPEED_MASK_RSVD4 \
22600 /* 10Gb link speed */
22601 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_EEE_LINK_SPEED_MASK_10GB \
22603 uint32_t xcvr_identifier_type_tx_lpi_timer;
22605 * Current setting of TX LPI timer in microseconds.
22606 * This field is valid only when_eee_enabled flag is set to 1
22607 * and tx_lpi_enabled is set to 1.
22609 #define HWRM_PORT_PHY_QCFG_OUTPUT_TX_LPI_TIMER_MASK \
22611 #define HWRM_PORT_PHY_QCFG_OUTPUT_TX_LPI_TIMER_SFT 0
22612 /* This value represents transceiver identifier type. */
22613 #define HWRM_PORT_PHY_QCFG_OUTPUT_XCVR_IDENTIFIER_TYPE_MASK \
22614 UINT32_C(0xff000000)
22615 #define HWRM_PORT_PHY_QCFG_OUTPUT_XCVR_IDENTIFIER_TYPE_SFT 24
22617 #define HWRM_PORT_PHY_QCFG_OUTPUT_XCVR_IDENTIFIER_TYPE_UNKNOWN \
22618 (UINT32_C(0x0) << 24)
22619 /* SFP/SFP+/SFP28 */
22620 #define HWRM_PORT_PHY_QCFG_OUTPUT_XCVR_IDENTIFIER_TYPE_SFP \
22621 (UINT32_C(0x3) << 24)
22623 #define HWRM_PORT_PHY_QCFG_OUTPUT_XCVR_IDENTIFIER_TYPE_QSFP \
22624 (UINT32_C(0xc) << 24)
22626 #define HWRM_PORT_PHY_QCFG_OUTPUT_XCVR_IDENTIFIER_TYPE_QSFPPLUS \
22627 (UINT32_C(0xd) << 24)
22629 #define HWRM_PORT_PHY_QCFG_OUTPUT_XCVR_IDENTIFIER_TYPE_QSFP28 \
22630 (UINT32_C(0x11) << 24)
22631 #define HWRM_PORT_PHY_QCFG_OUTPUT_XCVR_IDENTIFIER_TYPE_LAST \
22632 HWRM_PORT_PHY_QCFG_OUTPUT_XCVR_IDENTIFIER_TYPE_QSFP28
22634 * This value represents the current configuration of
22635 * Forward Error Correction (FEC) on the port.
22639 * When set to 1, then FEC is not supported on this port. If this flag
22640 * is set to 1, then all other FEC configuration flags shall be ignored.
22641 * When set to 0, then FEC is supported as indicated by other
22642 * configuration flags.
22644 #define HWRM_PORT_PHY_QCFG_OUTPUT_FEC_CFG_FEC_NONE_SUPPORTED \
22647 * When set to 1, then FEC autonegotiation is supported on this port.
22648 * When set to 0, then FEC autonegotiation is not supported on this port.
22650 #define HWRM_PORT_PHY_QCFG_OUTPUT_FEC_CFG_FEC_AUTONEG_SUPPORTED \
22653 * When set to 1, then FEC autonegotiation is enabled on this port.
22654 * When set to 0, then FEC autonegotiation is disabled if supported.
22655 * This flag should be ignored if FEC autonegotiation is not supported on this port.
22657 #define HWRM_PORT_PHY_QCFG_OUTPUT_FEC_CFG_FEC_AUTONEG_ENABLED \
22660 * When set to 1, then FEC CLAUSE 74 (Fire Code) is supported on this port.
22661 * When set to 0, then FEC CLAUSE 74 (Fire Code) is not supported on this port.
22663 #define HWRM_PORT_PHY_QCFG_OUTPUT_FEC_CFG_FEC_CLAUSE74_SUPPORTED \
22666 * When set to 1, then FEC CLAUSE 74 (Fire Code) is enabled on this
22667 * port. This means that FEC CLAUSE 74 is either advertised if
22668 * FEC autonegotiation is enabled or FEC CLAUSE 74 is force enabled.
22669 * When set to 0, then FEC CLAUSE 74 (Fire Code) is disabled if supported.
22670 * This flag should be ignored if FEC CLAUSE 74 is not supported on this port.
22672 #define HWRM_PORT_PHY_QCFG_OUTPUT_FEC_CFG_FEC_CLAUSE74_ENABLED \
22675 * When set to 1, then FEC CLAUSE 91 (Reed Solomon RS(528,514) for
22676 * NRZ) is supported on this port.
22677 * When set to 0, then FEC RS(528,418) is not supported on this port.
22679 #define HWRM_PORT_PHY_QCFG_OUTPUT_FEC_CFG_FEC_CLAUSE91_SUPPORTED \
22682 * When set to 1, then FEC CLAUSE 91 (Reed Solomon RS(528,514) for
22683 * NRZ) is enabled on this port. This means that FEC RS(528,514) is
22684 * either advertised if FEC autonegotiation is enabled or FEC
22685 * RS(528,514) is force enabled. When set to 0, then FEC RS(528,514)
22686 * is disabled if supported.
22687 * This flag should be ignored if FEC CLAUSE 91 is not supported on this port.
22689 #define HWRM_PORT_PHY_QCFG_OUTPUT_FEC_CFG_FEC_CLAUSE91_ENABLED \
22692 * When set to 1, then FEC RS544_1XN is supported on this port.
22693 * When set to 0, then FEC RS544_1XN is not supported on this port.
22695 #define HWRM_PORT_PHY_QCFG_OUTPUT_FEC_CFG_FEC_RS544_1XN_SUPPORTED \
22698 * When set to 1, then RS544_1XN is enabled on this
22699 * port. This means that FEC RS544_1XN is either advertised if
22700 * FEC autonegotiation is enabled or FEC RS544_1XN is force enabled.
22701 * When set to 0, then FEC RS544_1XN is disabled if supported.
22702 * This flag should be ignored if FEC RS544_1XN is not supported on this port.
22704 #define HWRM_PORT_PHY_QCFG_OUTPUT_FEC_CFG_FEC_RS544_1XN_ENABLED \
22707 * When set to 1, then FEC RS(544,514) is supported on this port.
22708 * When set to 0, then FEC RS(544,514) is not supported on this port.
22710 #define HWRM_PORT_PHY_QCFG_OUTPUT_FEC_CFG_FEC_RS544_IEEE_SUPPORTED \
22713 * When set to 1, then RS(544,514) is enabled on this
22714 * port. This means that FEC RS(544,514) is either advertised if
22715 * FEC autonegotiation is enabled or FEC RS(544,514) is force
22716 * enabled. When set to 0, then FEC RS(544,514) is disabled if supported.
22717 * This flag should be ignored if FEC RS(544,514) is not supported on this port.
22719 #define HWRM_PORT_PHY_QCFG_OUTPUT_FEC_CFG_FEC_RS544_IEEE_ENABLED \
22722 * When set to 1, then FEC RS272_1XN is supported on this port.
22723 * When set to 0, then FEC RS272_1XN is not supported on this port.
22725 #define HWRM_PORT_PHY_QCFG_OUTPUT_FEC_CFG_FEC_RS272_1XN_SUPPORTED \
22728 * When set to 1, then RS272_1XN is enabled on this
22729 * port. This means that FEC RS272_1XN is either advertised if
22730 * FEC autonegotiation is enabled or FEC RS272_1XN is force
22731 * enabled. When set to 0, then FEC RS272_1XN is disabled if supported.
22732 * This flag should be ignored if FEC RS272_1XN is not supported on this port.
22734 #define HWRM_PORT_PHY_QCFG_OUTPUT_FEC_CFG_FEC_RS272_1XN_ENABLED \
22737 * When set to 1, then FEC RS(272,514) is supported on this port.
22738 * When set to 0, then FEC RS(272,514) is not supported on this port.
22740 #define HWRM_PORT_PHY_QCFG_OUTPUT_FEC_CFG_FEC_RS272_IEEE_SUPPORTED \
22743 * When set to 1, then RS(272,257) is enabled on this
22744 * port. This means that FEC RS(272,257) is either advertised if
22745 * FEC autonegotiation is enabled or FEC RS(272,257) is force
22746 * enabled. When set to 0, then FEC RS(272,257) is disabled if supported.
22747 * This flag should be ignored if FEC RS(272,257) is not supported on this port.
22749 #define HWRM_PORT_PHY_QCFG_OUTPUT_FEC_CFG_FEC_RS272_IEEE_ENABLED \
22752 * This value is indicates the duplex of the current
22753 * connection state.
22755 uint8_t duplex_state;
22756 /* Half Duplex connection. */
22757 #define HWRM_PORT_PHY_QCFG_OUTPUT_DUPLEX_STATE_HALF UINT32_C(0x0)
22758 /* Full duplex connection. */
22759 #define HWRM_PORT_PHY_QCFG_OUTPUT_DUPLEX_STATE_FULL UINT32_C(0x1)
22760 #define HWRM_PORT_PHY_QCFG_OUTPUT_DUPLEX_STATE_LAST \
22761 HWRM_PORT_PHY_QCFG_OUTPUT_DUPLEX_STATE_FULL
22762 /* Option flags fields. */
22763 uint8_t option_flags;
22764 /* When this bit is '1', Media auto detect is enabled. */
22765 #define HWRM_PORT_PHY_QCFG_OUTPUT_OPTION_FLAGS_MEDIA_AUTO_DETECT \
22768 * When this bit is '1', active_fec_signal_mode can be
22771 #define HWRM_PORT_PHY_QCFG_OUTPUT_OPTION_FLAGS_SIGNAL_MODE_KNOWN \
22774 * Up to 16 bytes of null padded ASCII string representing
22776 * If the string is set to null, then the vendor name is not
22779 char phy_vendor_name[16];
22781 * Up to 16 bytes of null padded ASCII string that
22782 * identifies vendor specific part number of the PHY.
22783 * If the string is set to null, then the vendor specific
22784 * part number is not available.
22786 char phy_vendor_partnumber[16];
22788 * The supported PAM4 speeds for the port. This is a bit mask.
22789 * For each speed that is supported, the corresponding
22790 * bit will be set to '1'.
22792 uint16_t support_pam4_speeds;
22793 #define HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_PAM4_SPEEDS_50G \
22795 #define HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_PAM4_SPEEDS_100G \
22797 #define HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_PAM4_SPEEDS_200G \
22800 * Current setting of forced PAM4 link speed.
22801 * When the link speed is not being forced, this
22802 * value shall be set to 0.
22804 uint16_t force_pam4_link_speed;
22805 /* 50Gb link speed */
22806 #define HWRM_PORT_PHY_QCFG_OUTPUT_FORCE_PAM4_LINK_SPEED_50GB \
22808 /* 100Gb link speed */
22809 #define HWRM_PORT_PHY_QCFG_OUTPUT_FORCE_PAM4_LINK_SPEED_100GB \
22811 /* 200Gb link speed */
22812 #define HWRM_PORT_PHY_QCFG_OUTPUT_FORCE_PAM4_LINK_SPEED_200GB \
22814 #define HWRM_PORT_PHY_QCFG_OUTPUT_FORCE_PAM4_LINK_SPEED_LAST \
22815 HWRM_PORT_PHY_QCFG_OUTPUT_FORCE_PAM4_LINK_SPEED_200GB
22817 * Current setting for auto_pam4_link_speed_mask that is used to
22818 * advertise speeds during autonegotiation.
22819 * This field is only valid when auto_mode is set to "mask".
22820 * The speeds specified in this field shall be a subset of
22821 * supported speeds on this port.
22823 uint16_t auto_pam4_link_speed_mask;
22824 #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_PAM4_LINK_SPEED_MASK_50G \
22826 #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_PAM4_LINK_SPEED_MASK_100G \
22828 #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_PAM4_LINK_SPEED_MASK_200G \
22831 * The advertised PAM4 speeds for the port by the link partner.
22832 * Each advertised speed will be set to '1'.
22834 uint8_t link_partner_pam4_adv_speeds;
22835 /* 50Gb link speed */
22836 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_PAM4_ADV_SPEEDS_50GB \
22838 /* 100Gb link speed */
22839 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_PAM4_ADV_SPEEDS_100GB \
22841 /* 200Gb link speed */
22842 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_PAM4_ADV_SPEEDS_200GB \
22845 * This field is used in Output records to indicate that the output
22846 * is completely written to RAM. This field should be read as '1'
22847 * to indicate that the output has been completely written.
22848 * When writing a command completion or response to an internal processor,
22849 * the order of writes has to be such that this field is written last.
22854 /*********************
22855 * hwrm_port_mac_cfg *
22856 *********************/
22859 /* hwrm_port_mac_cfg_input (size:384b/48B) */
22860 struct hwrm_port_mac_cfg_input {
22861 /* The HWRM command request type. */
22864 * The completion ring to send the completion event on. This should
22865 * be the NQ ID returned from the `nq_alloc` HWRM command.
22867 uint16_t cmpl_ring;
22869 * The sequence ID is used by the driver for tracking multiple
22870 * commands. This ID is treated as opaque data by the firmware and
22871 * the value is returned in the `hwrm_resp_hdr` upon completion.
22875 * The target ID of the command:
22876 * * 0x0-0xFFF8 - The function ID
22877 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
22878 * * 0xFFFD - Reserved for user-space HWRM interface
22881 uint16_t target_id;
22883 * A physical address pointer pointing to a host buffer that the
22884 * command's response data will be written. This can be either a host
22885 * physical address (HPA) or a guest physical address (GPA) and must
22886 * point to a physically contiguous block of memory.
22888 uint64_t resp_addr;
22890 * In this field, there are a number of CoS mappings related flags
22891 * that are used to configure CoS mappings and their corresponding
22892 * priorities in the hardware.
22893 * For the priorities of CoS mappings, the HWRM uses the following
22894 * priority order (high to low) by default:
22897 * # tunnel_vlan_pri
22900 * A subset of CoS mappings can be enabled.
22901 * If a priority is not specified for an enabled CoS mapping, the
22902 * priority will be assigned in the above order for the enabled CoS
22903 * mappings. For example, if vlan_pri and ip_dscp CoS mappings are
22904 * enabled and their priorities are not specified, the following
22905 * priority order (high to low) will be used by the HWRM:
22910 * vlan_pri CoS mapping together with default CoS with lower priority
22911 * are enabled by default by the HWRM.
22915 * When this bit is '1', this command will configure
22916 * the MAC to match the current link state of the PHY.
22917 * If the link is not established on the PHY, then this
22918 * bit has no effect.
22920 #define HWRM_PORT_MAC_CFG_INPUT_FLAGS_MATCH_LINK \
22923 * When this bit is set to '1', the inner VLAN PRI to CoS mapping
22924 * is requested to be enabled.
22926 #define HWRM_PORT_MAC_CFG_INPUT_FLAGS_VLAN_PRI2COS_ENABLE \
22929 * When this bit is set to '1', tunnel VLAN PRI field to
22930 * CoS mapping is requested to be enabled.
22932 #define HWRM_PORT_MAC_CFG_INPUT_FLAGS_TUNNEL_PRI2COS_ENABLE \
22935 * When this bit is set to '1', the IP DSCP to CoS mapping is
22936 * requested to be enabled.
22938 #define HWRM_PORT_MAC_CFG_INPUT_FLAGS_IP_DSCP2COS_ENABLE \
22941 * When this bit is '1', the HWRM is requested to
22942 * enable timestamp capture capability on the receive side
22945 #define HWRM_PORT_MAC_CFG_INPUT_FLAGS_PTP_RX_TS_CAPTURE_ENABLE \
22948 * When this bit is '1', the HWRM is requested to
22949 * disable timestamp capture capability on the receive side
22952 #define HWRM_PORT_MAC_CFG_INPUT_FLAGS_PTP_RX_TS_CAPTURE_DISABLE \
22955 * When this bit is '1', the HWRM is requested to
22956 * enable timestamp capture capability on the transmit side
22959 #define HWRM_PORT_MAC_CFG_INPUT_FLAGS_PTP_TX_TS_CAPTURE_ENABLE \
22962 * When this bit is '1', the HWRM is requested to
22963 * disable timestamp capture capability on the transmit side
22966 #define HWRM_PORT_MAC_CFG_INPUT_FLAGS_PTP_TX_TS_CAPTURE_DISABLE \
22969 * When this bit is '1', the Out-Of-Box WoL is requested to
22970 * be enabled on this port.
22972 #define HWRM_PORT_MAC_CFG_INPUT_FLAGS_OOB_WOL_ENABLE \
22975 * When this bit is '1', the Out-Of-Box WoL is requested to
22976 * be disabled on this port.
22978 #define HWRM_PORT_MAC_CFG_INPUT_FLAGS_OOB_WOL_DISABLE \
22981 * When this bit is set to '1', the inner VLAN PRI to CoS mapping
22982 * is requested to be disabled.
22984 #define HWRM_PORT_MAC_CFG_INPUT_FLAGS_VLAN_PRI2COS_DISABLE \
22987 * When this bit is set to '1', tunnel VLAN PRI field to
22988 * CoS mapping is requested to be disabled.
22990 #define HWRM_PORT_MAC_CFG_INPUT_FLAGS_TUNNEL_PRI2COS_DISABLE \
22993 * When this bit is set to '1', the IP DSCP to CoS mapping is
22994 * requested to be disabled.
22996 #define HWRM_PORT_MAC_CFG_INPUT_FLAGS_IP_DSCP2COS_DISABLE \
22999 * When this bit is set to '1', and the ptp_tx_ts_capture_enable
23000 * bit is set, then the device uses one step Tx timestamping.
23001 * This bit is temporary and used for experimental purposes.
23003 #define HWRM_PORT_MAC_CFG_INPUT_FLAGS_PTP_ONE_STEP_TX_TS \
23007 * This bit must be '1' for the ipg field to be
23010 #define HWRM_PORT_MAC_CFG_INPUT_ENABLES_IPG \
23013 * This bit must be '1' for the lpbk field to be
23016 #define HWRM_PORT_MAC_CFG_INPUT_ENABLES_LPBK \
23019 * This bit must be '1' for the vlan_pri2cos_map_pri field to be
23022 #define HWRM_PORT_MAC_CFG_INPUT_ENABLES_VLAN_PRI2COS_MAP_PRI \
23025 * This bit must be '1' for the tunnel_pri2cos_map_pri field to be
23028 #define HWRM_PORT_MAC_CFG_INPUT_ENABLES_TUNNEL_PRI2COS_MAP_PRI \
23031 * This bit must be '1' for the dscp2cos_map_pri field to be
23034 #define HWRM_PORT_MAC_CFG_INPUT_ENABLES_DSCP2COS_MAP_PRI \
23037 * This bit must be '1' for the rx_ts_capture_ptp_msg_type field to be
23040 #define HWRM_PORT_MAC_CFG_INPUT_ENABLES_RX_TS_CAPTURE_PTP_MSG_TYPE \
23043 * This bit must be '1' for the tx_ts_capture_ptp_msg_type field to be
23046 #define HWRM_PORT_MAC_CFG_INPUT_ENABLES_TX_TS_CAPTURE_PTP_MSG_TYPE \
23049 * This bit must be '1' for the cos_field_cfg field to be
23052 #define HWRM_PORT_MAC_CFG_INPUT_ENABLES_COS_FIELD_CFG \
23055 * This bit must be '1' for the ptp_freq_adj_ppb field to be
23058 #define HWRM_PORT_MAC_CFG_INPUT_ENABLES_PTP_FREQ_ADJ_PPB \
23061 * This bit must be '1' for the ptp_adj_phase field to be
23064 #define HWRM_PORT_MAC_CFG_INPUT_ENABLES_PTP_ADJ_PHASE \
23066 /* Port ID of port that is to be configured. */
23069 * This value is used to configure the minimum IPG that will
23070 * be sent between packets by this port.
23073 /* This value controls the loopback setting for the MAC. */
23075 /* No loopback is selected. Normal operation. */
23076 #define HWRM_PORT_MAC_CFG_INPUT_LPBK_NONE UINT32_C(0x0)
23078 * The HW will be configured with local loopback such that
23079 * host data is sent back to the host without modification.
23081 #define HWRM_PORT_MAC_CFG_INPUT_LPBK_LOCAL UINT32_C(0x1)
23083 * The HW will be configured with remote loopback such that
23084 * port logic will send packets back out the transmitter that
23087 #define HWRM_PORT_MAC_CFG_INPUT_LPBK_REMOTE UINT32_C(0x2)
23088 #define HWRM_PORT_MAC_CFG_INPUT_LPBK_LAST \
23089 HWRM_PORT_MAC_CFG_INPUT_LPBK_REMOTE
23091 * This value controls the priority setting of VLAN PRI to CoS
23092 * mapping based on VLAN Tags of inner packet headers of
23093 * tunneled packets or packet headers of non-tunneled packets.
23095 * # Each XXX_pri variable shall have a unique priority value
23096 * when it is being specified.
23097 * # When comparing priorities of mappings, higher value
23098 * indicates higher priority.
23099 * For example, a value of 0-3 is returned where 0 is being
23100 * the lowest priority and 3 is being the highest priority.
23102 uint8_t vlan_pri2cos_map_pri;
23103 /* Reserved field. */
23106 * This value controls the priority setting of VLAN PRI to CoS
23107 * mapping based on VLAN Tags of tunneled header.
23108 * This mapping only applies when tunneled headers
23111 * # Each XXX_pri variable shall have a unique priority value
23112 * when it is being specified.
23113 * # When comparing priorities of mappings, higher value
23114 * indicates higher priority.
23115 * For example, a value of 0-3 is returned where 0 is being
23116 * the lowest priority and 3 is being the highest priority.
23118 uint8_t tunnel_pri2cos_map_pri;
23120 * This value controls the priority setting of IP DSCP to CoS
23121 * mapping based on inner IP header of tunneled packets or
23122 * IP header of non-tunneled packets.
23124 * # Each XXX_pri variable shall have a unique priority value
23125 * when it is being specified.
23126 * # When comparing priorities of mappings, higher value
23127 * indicates higher priority.
23128 * For example, a value of 0-3 is returned where 0 is being
23129 * the lowest priority and 3 is being the highest priority.
23131 uint8_t dscp2pri_map_pri;
23133 * This is a 16-bit bit mask that is used to request a
23134 * specific configuration of time stamp capture of PTP messages
23135 * on the receive side of this port.
23136 * This field shall be ignored if the ptp_rx_ts_capture_enable
23137 * flag is not set in this command.
23138 * Otherwise, if bit 'i' is set, then the HWRM is being
23139 * requested to configure the receive side of the port to
23140 * capture the time stamp of every received PTP message
23141 * with messageType field value set to i.
23143 uint16_t rx_ts_capture_ptp_msg_type;
23145 * This is a 16-bit bit mask that is used to request a
23146 * specific configuration of time stamp capture of PTP messages
23147 * on the transmit side of this port.
23148 * This field shall be ignored if the ptp_tx_ts_capture_enable
23149 * flag is not set in this command.
23150 * Otherwise, if bit 'i' is set, then the HWRM is being
23151 * requested to configure the transmit side of the port to
23152 * capture the time stamp of every transmitted PTP message
23153 * with messageType field value set to i.
23155 uint16_t tx_ts_capture_ptp_msg_type;
23156 /* Configuration of CoS fields. */
23157 uint8_t cos_field_cfg;
23159 #define HWRM_PORT_MAC_CFG_INPUT_COS_FIELD_CFG_RSVD1 \
23162 * This field is used to specify selection of VLAN PRI value
23163 * based on whether one or two VLAN Tags are present in
23164 * the inner packet headers of tunneled packets or
23165 * non-tunneled packets.
23166 * This field is valid only if inner VLAN PRI to CoS mapping
23168 * If VLAN PRI to CoS mapping is not enabled, then this
23169 * field shall be ignored.
23171 #define HWRM_PORT_MAC_CFG_INPUT_COS_FIELD_CFG_VLAN_PRI_SEL_MASK \
23173 #define HWRM_PORT_MAC_CFG_INPUT_COS_FIELD_CFG_VLAN_PRI_SEL_SFT \
23176 * Select inner VLAN PRI when 1 or 2 VLAN Tags are
23177 * present in the inner packet headers
23179 #define HWRM_PORT_MAC_CFG_INPUT_COS_FIELD_CFG_VLAN_PRI_SEL_INNERMOST \
23180 (UINT32_C(0x0) << 1)
23182 * Select outer VLAN Tag PRI when 2 VLAN Tags are
23183 * present in the inner packet headers.
23184 * No VLAN PRI shall be selected for this configuration
23185 * if only one VLAN Tag is present in the inner
23188 #define HWRM_PORT_MAC_CFG_INPUT_COS_FIELD_CFG_VLAN_PRI_SEL_OUTER \
23189 (UINT32_C(0x1) << 1)
23191 * Select outermost VLAN PRI when 1 or 2 VLAN Tags
23192 * are present in the inner packet headers
23194 #define HWRM_PORT_MAC_CFG_INPUT_COS_FIELD_CFG_VLAN_PRI_SEL_OUTERMOST \
23195 (UINT32_C(0x2) << 1)
23197 #define HWRM_PORT_MAC_CFG_INPUT_COS_FIELD_CFG_VLAN_PRI_SEL_UNSPECIFIED \
23198 (UINT32_C(0x3) << 1)
23199 #define HWRM_PORT_MAC_CFG_INPUT_COS_FIELD_CFG_VLAN_PRI_SEL_LAST \
23200 HWRM_PORT_MAC_CFG_INPUT_COS_FIELD_CFG_VLAN_PRI_SEL_UNSPECIFIED
23202 * This field is used to specify selection of tunnel VLAN
23203 * PRI value based on whether one or two VLAN Tags are
23204 * present in tunnel headers.
23205 * This field is valid only if tunnel VLAN PRI to CoS mapping
23207 * If tunnel VLAN PRI to CoS mapping is not enabled, then this
23208 * field shall be ignored.
23210 #define HWRM_PORT_MAC_CFG_INPUT_COS_FIELD_CFG_T_VLAN_PRI_SEL_MASK \
23212 #define HWRM_PORT_MAC_CFG_INPUT_COS_FIELD_CFG_T_VLAN_PRI_SEL_SFT \
23215 * Select inner VLAN PRI when 1 or 2 VLAN Tags are
23216 * present in the tunnel packet headers
23218 #define HWRM_PORT_MAC_CFG_INPUT_COS_FIELD_CFG_T_VLAN_PRI_SEL_INNERMOST \
23219 (UINT32_C(0x0) << 3)
23221 * Select outer VLAN Tag PRI when 2 VLAN Tags are
23222 * present in the tunnel packet headers.
23223 * No tunnel VLAN PRI shall be selected for this
23224 * configuration if only one VLAN Tag is present in
23225 * the tunnel packet headers.
23227 #define HWRM_PORT_MAC_CFG_INPUT_COS_FIELD_CFG_T_VLAN_PRI_SEL_OUTER \
23228 (UINT32_C(0x1) << 3)
23230 * Select outermost VLAN PRI when 1 or 2 VLAN Tags
23231 * are present in the tunnel packet headers
23233 #define HWRM_PORT_MAC_CFG_INPUT_COS_FIELD_CFG_T_VLAN_PRI_SEL_OUTERMOST \
23234 (UINT32_C(0x2) << 3)
23236 #define HWRM_PORT_MAC_CFG_INPUT_COS_FIELD_CFG_T_VLAN_PRI_SEL_UNSPECIFIED \
23237 (UINT32_C(0x3) << 3)
23238 #define HWRM_PORT_MAC_CFG_INPUT_COS_FIELD_CFG_T_VLAN_PRI_SEL_LAST \
23239 HWRM_PORT_MAC_CFG_INPUT_COS_FIELD_CFG_T_VLAN_PRI_SEL_UNSPECIFIED
23241 * This field shall be used to provide default CoS value
23242 * that has been configured on this port.
23243 * This field is valid only if default CoS mapping
23245 * If default CoS mapping is not enabled, then this
23246 * field shall be ignored.
23248 #define HWRM_PORT_MAC_CFG_INPUT_COS_FIELD_CFG_DEFAULT_COS_MASK \
23250 #define HWRM_PORT_MAC_CFG_INPUT_COS_FIELD_CFG_DEFAULT_COS_SFT \
23252 uint8_t unused_0[3];
23254 * This signed field specifies by how much to adjust the frequency
23255 * of sync timer updates (measured in parts per billion).
23257 int32_t ptp_freq_adj_ppb;
23259 * This unsigned field specifies the phase offset to be applied
23260 * to the PHC (PTP Hardware Clock). This field is specified in
23263 uint32_t ptp_adj_phase;
23266 /* hwrm_port_mac_cfg_output (size:128b/16B) */
23267 struct hwrm_port_mac_cfg_output {
23268 /* The specific error status for the command. */
23269 uint16_t error_code;
23270 /* The HWRM command request type. */
23272 /* The sequence ID from the original command. */
23274 /* The length of the response data in number of bytes. */
23277 * This is the configured maximum length of Ethernet packet
23278 * payload that is allowed to be received on the port.
23279 * This value does not include the number of bytes used by
23280 * Ethernet header and trailer (CRC).
23284 * This is the configured maximum length of Ethernet packet
23285 * payload that is allowed to be transmitted on the port.
23286 * This value does not include the number of bytes used by
23287 * Ethernet header and trailer (CRC).
23290 /* Current configuration of the IPG value. */
23292 /* Current value of the loopback value. */
23294 /* No loopback is selected. Normal operation. */
23295 #define HWRM_PORT_MAC_CFG_OUTPUT_LPBK_NONE UINT32_C(0x0)
23297 * The HW will be configured with local loopback such that
23298 * host data is sent back to the host without modification.
23300 #define HWRM_PORT_MAC_CFG_OUTPUT_LPBK_LOCAL UINT32_C(0x1)
23302 * The HW will be configured with remote loopback such that
23303 * port logic will send packets back out the transmitter that
23306 #define HWRM_PORT_MAC_CFG_OUTPUT_LPBK_REMOTE UINT32_C(0x2)
23307 #define HWRM_PORT_MAC_CFG_OUTPUT_LPBK_LAST \
23308 HWRM_PORT_MAC_CFG_OUTPUT_LPBK_REMOTE
23311 * This field is used in Output records to indicate that the output
23312 * is completely written to RAM. This field should be read as '1'
23313 * to indicate that the output has been completely written.
23314 * When writing a command completion or response to an internal processor,
23315 * the order of writes has to be such that this field is written last.
23320 /**********************
23321 * hwrm_port_mac_qcfg *
23322 **********************/
23325 /* hwrm_port_mac_qcfg_input (size:192b/24B) */
23326 struct hwrm_port_mac_qcfg_input {
23327 /* The HWRM command request type. */
23330 * The completion ring to send the completion event on. This should
23331 * be the NQ ID returned from the `nq_alloc` HWRM command.
23333 uint16_t cmpl_ring;
23335 * The sequence ID is used by the driver for tracking multiple
23336 * commands. This ID is treated as opaque data by the firmware and
23337 * the value is returned in the `hwrm_resp_hdr` upon completion.
23341 * The target ID of the command:
23342 * * 0x0-0xFFF8 - The function ID
23343 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
23344 * * 0xFFFD - Reserved for user-space HWRM interface
23347 uint16_t target_id;
23349 * A physical address pointer pointing to a host buffer that the
23350 * command's response data will be written. This can be either a host
23351 * physical address (HPA) or a guest physical address (GPA) and must
23352 * point to a physically contiguous block of memory.
23354 uint64_t resp_addr;
23355 /* Port ID of port that is to be configured. */
23357 uint8_t unused_0[6];
23360 /* hwrm_port_mac_qcfg_output (size:256b/32B) */
23361 struct hwrm_port_mac_qcfg_output {
23362 /* The specific error status for the command. */
23363 uint16_t error_code;
23364 /* The HWRM command request type. */
23366 /* The sequence ID from the original command. */
23368 /* The length of the response data in number of bytes. */
23371 * This is the configured maximum length of Ethernet packet
23372 * payload that is allowed to be received on the port.
23373 * This value does not include the number of bytes used by the
23374 * Ethernet header and trailer (CRC).
23378 * This is the configured maximum length of Ethernet packet
23379 * payload that is allowed to be transmitted on the port.
23380 * This value does not include the number of bytes used by the
23381 * Ethernet header and trailer (CRC).
23385 * The minimum IPG that will
23386 * be sent between packets by this port.
23389 /* The loopback setting for the MAC. */
23391 /* No loopback is selected. Normal operation. */
23392 #define HWRM_PORT_MAC_QCFG_OUTPUT_LPBK_NONE UINT32_C(0x0)
23394 * The HW will be configured with local loopback such that
23395 * host data is sent back to the host without modification.
23397 #define HWRM_PORT_MAC_QCFG_OUTPUT_LPBK_LOCAL UINT32_C(0x1)
23399 * The HW will be configured with remote loopback such that
23400 * port logic will send packets back out the transmitter that
23403 #define HWRM_PORT_MAC_QCFG_OUTPUT_LPBK_REMOTE UINT32_C(0x2)
23404 #define HWRM_PORT_MAC_QCFG_OUTPUT_LPBK_LAST \
23405 HWRM_PORT_MAC_QCFG_OUTPUT_LPBK_REMOTE
23407 * Priority setting for VLAN PRI to CoS mapping.
23408 * # Each XXX_pri variable shall have a unique priority value
23409 * when it is being used.
23410 * # When comparing priorities of mappings, higher value
23411 * indicates higher priority.
23412 * For example, a value of 0-3 is returned where 0 is being
23413 * the lowest priority and 3 is being the highest priority.
23414 * # If the corresponding CoS mapping is not enabled, then this
23415 * field should be ignored.
23416 * # This value indicates the normalized priority value retained
23419 uint8_t vlan_pri2cos_map_pri;
23421 * In this field, a number of CoS mappings related flags
23422 * are used to indicate configured CoS mappings.
23426 * When this bit is set to '1', the inner VLAN PRI to CoS mapping
23429 #define HWRM_PORT_MAC_QCFG_OUTPUT_FLAGS_VLAN_PRI2COS_ENABLE \
23432 * When this bit is set to '1', tunnel VLAN PRI field to
23433 * CoS mapping is enabled.
23435 #define HWRM_PORT_MAC_QCFG_OUTPUT_FLAGS_TUNNEL_PRI2COS_ENABLE \
23438 * When this bit is set to '1', the IP DSCP to CoS mapping is
23441 #define HWRM_PORT_MAC_QCFG_OUTPUT_FLAGS_IP_DSCP2COS_ENABLE \
23444 * When this bit is '1', the Out-Of-Box WoL is enabled on this
23447 #define HWRM_PORT_MAC_QCFG_OUTPUT_FLAGS_OOB_WOL_ENABLE \
23449 /* When this bit is '1', PTP is enabled for RX on this port. */
23450 #define HWRM_PORT_MAC_QCFG_OUTPUT_FLAGS_PTP_RX_TS_CAPTURE_ENABLE \
23452 /* When this bit is '1', PTP is enabled for TX on this port. */
23453 #define HWRM_PORT_MAC_QCFG_OUTPUT_FLAGS_PTP_TX_TS_CAPTURE_ENABLE \
23456 * Priority setting for tunnel VLAN PRI to CoS mapping.
23457 * # Each XXX_pri variable shall have a unique priority value
23458 * when it is being used.
23459 * # When comparing priorities of mappings, higher value
23460 * indicates higher priority.
23461 * For example, a value of 0-3 is returned where 0 is being
23462 * the lowest priority and 3 is being the highest priority.
23463 * # If the corresponding CoS mapping is not enabled, then this
23464 * field should be ignored.
23465 * # This value indicates the normalized priority value retained
23468 uint8_t tunnel_pri2cos_map_pri;
23470 * Priority setting for DSCP to PRI mapping.
23471 * # Each XXX_pri variable shall have a unique priority value
23472 * when it is being used.
23473 * # When comparing priorities of mappings, higher value
23474 * indicates higher priority.
23475 * For example, a value of 0-3 is returned where 0 is being
23476 * the lowest priority and 3 is being the highest priority.
23477 * # If the corresponding CoS mapping is not enabled, then this
23478 * field should be ignored.
23479 * # This value indicates the normalized priority value retained
23482 uint8_t dscp2pri_map_pri;
23484 * This is a 16-bit bit mask that represents the
23485 * current configuration of time stamp capture of PTP messages
23486 * on the receive side of this port.
23487 * If bit 'i' is set, then the receive side of the port
23488 * is configured to capture the time stamp of every
23489 * received PTP message with messageType field value set
23491 * If all bits are set to 0 (i.e. field value set 0),
23492 * then the receive side of the port is not configured
23493 * to capture timestamp for PTP messages.
23494 * If all bits are set to 1, then the receive side of the
23495 * port is configured to capture timestamp for all PTP
23498 uint16_t rx_ts_capture_ptp_msg_type;
23500 * This is a 16-bit bit mask that represents the
23501 * current configuration of time stamp capture of PTP messages
23502 * on the transmit side of this port.
23503 * If bit 'i' is set, then the transmit side of the port
23504 * is configured to capture the time stamp of every
23505 * received PTP message with messageType field value set
23507 * If all bits are set to 0 (i.e. field value set 0),
23508 * then the transmit side of the port is not configured
23509 * to capture timestamp for PTP messages.
23510 * If all bits are set to 1, then the transmit side of the
23511 * port is configured to capture timestamp for all PTP
23514 uint16_t tx_ts_capture_ptp_msg_type;
23515 /* Configuration of CoS fields. */
23516 uint8_t cos_field_cfg;
23518 #define HWRM_PORT_MAC_QCFG_OUTPUT_COS_FIELD_CFG_RSVD \
23521 * This field is used for selecting VLAN PRI value
23522 * based on whether one or two VLAN Tags are present in
23523 * the inner packet headers of tunneled packets or
23524 * non-tunneled packets.
23526 #define HWRM_PORT_MAC_QCFG_OUTPUT_COS_FIELD_CFG_VLAN_PRI_SEL_MASK \
23528 #define HWRM_PORT_MAC_QCFG_OUTPUT_COS_FIELD_CFG_VLAN_PRI_SEL_SFT \
23531 * Select inner VLAN PRI when 1 or 2 VLAN Tags are
23532 * present in the inner packet headers
23534 #define HWRM_PORT_MAC_QCFG_OUTPUT_COS_FIELD_CFG_VLAN_PRI_SEL_INNERMOST \
23535 (UINT32_C(0x0) << 1)
23537 * Select outer VLAN Tag PRI when 2 VLAN Tags are
23538 * present in the inner packet headers.
23539 * No VLAN PRI is selected for this configuration
23540 * if only one VLAN Tag is present in the inner
23543 #define HWRM_PORT_MAC_QCFG_OUTPUT_COS_FIELD_CFG_VLAN_PRI_SEL_OUTER \
23544 (UINT32_C(0x1) << 1)
23546 * Select outermost VLAN PRI when 1 or 2 VLAN Tags
23547 * are present in the inner packet headers
23549 #define HWRM_PORT_MAC_QCFG_OUTPUT_COS_FIELD_CFG_VLAN_PRI_SEL_OUTERMOST \
23550 (UINT32_C(0x2) << 1)
23552 #define HWRM_PORT_MAC_QCFG_OUTPUT_COS_FIELD_CFG_VLAN_PRI_SEL_UNSPECIFIED \
23553 (UINT32_C(0x3) << 1)
23554 #define HWRM_PORT_MAC_QCFG_OUTPUT_COS_FIELD_CFG_VLAN_PRI_SEL_LAST \
23555 HWRM_PORT_MAC_QCFG_OUTPUT_COS_FIELD_CFG_VLAN_PRI_SEL_UNSPECIFIED
23557 * This field is used for selecting tunnel VLAN PRI value
23558 * based on whether one or two VLAN Tags are present in
23559 * the tunnel headers of tunneled packets. This selection
23560 * does not apply to non-tunneled packets.
23562 #define HWRM_PORT_MAC_QCFG_OUTPUT_COS_FIELD_CFG_T_VLAN_PRI_SEL_MASK \
23564 #define HWRM_PORT_MAC_QCFG_OUTPUT_COS_FIELD_CFG_T_VLAN_PRI_SEL_SFT \
23567 * Select inner VLAN PRI when 1 or 2 VLAN Tags are
23568 * present in the tunnel packet headers
23570 #define HWRM_PORT_MAC_QCFG_OUTPUT_COS_FIELD_CFG_T_VLAN_PRI_SEL_INNERMOST \
23571 (UINT32_C(0x0) << 3)
23573 * Select outer VLAN Tag PRI when 2 VLAN Tags are
23574 * present in the tunnel packet headers.
23575 * No VLAN PRI is selected for this configuration
23576 * if only one VLAN Tag is present in the tunnel
23579 #define HWRM_PORT_MAC_QCFG_OUTPUT_COS_FIELD_CFG_T_VLAN_PRI_SEL_OUTER \
23580 (UINT32_C(0x1) << 3)
23582 * Select outermost VLAN PRI when 1 or 2 VLAN Tags
23583 * are present in the tunnel packet headers
23585 #define HWRM_PORT_MAC_QCFG_OUTPUT_COS_FIELD_CFG_T_VLAN_PRI_SEL_OUTERMOST \
23586 (UINT32_C(0x2) << 3)
23588 #define HWRM_PORT_MAC_QCFG_OUTPUT_COS_FIELD_CFG_T_VLAN_PRI_SEL_UNSPECIFIED \
23589 (UINT32_C(0x3) << 3)
23590 #define HWRM_PORT_MAC_QCFG_OUTPUT_COS_FIELD_CFG_T_VLAN_PRI_SEL_LAST \
23591 HWRM_PORT_MAC_QCFG_OUTPUT_COS_FIELD_CFG_T_VLAN_PRI_SEL_UNSPECIFIED
23593 * This field is used to provide default CoS value that
23594 * has been configured on this port.
23596 #define HWRM_PORT_MAC_QCFG_OUTPUT_COS_FIELD_CFG_DEFAULT_COS_MASK \
23598 #define HWRM_PORT_MAC_QCFG_OUTPUT_COS_FIELD_CFG_DEFAULT_COS_SFT \
23601 uint16_t port_svif_info;
23603 * This field specifies the source virtual interface of the port being
23604 * queried. Drivers can use this to program port svif field in the
23607 #define HWRM_PORT_MAC_QCFG_OUTPUT_PORT_SVIF_INFO_PORT_SVIF_MASK \
23609 #define HWRM_PORT_MAC_QCFG_OUTPUT_PORT_SVIF_INFO_PORT_SVIF_SFT 0
23610 /* This field specifies whether port_svif is valid or not */
23611 #define HWRM_PORT_MAC_QCFG_OUTPUT_PORT_SVIF_INFO_PORT_SVIF_VALID \
23613 uint8_t unused_2[5];
23615 * This field is used in Output records to indicate that the output
23616 * is completely written to RAM. This field should be read as '1'
23617 * to indicate that the output has been completely written.
23618 * When writing a command completion or response to an internal processor,
23619 * the order of writes has to be such that this field is written last.
23624 /**************************
23625 * hwrm_port_mac_ptp_qcfg *
23626 **************************/
23629 /* hwrm_port_mac_ptp_qcfg_input (size:192b/24B) */
23630 struct hwrm_port_mac_ptp_qcfg_input {
23631 /* The HWRM command request type. */
23634 * The completion ring to send the completion event on. This should
23635 * be the NQ ID returned from the `nq_alloc` HWRM command.
23637 uint16_t cmpl_ring;
23639 * The sequence ID is used by the driver for tracking multiple
23640 * commands. This ID is treated as opaque data by the firmware and
23641 * the value is returned in the `hwrm_resp_hdr` upon completion.
23645 * The target ID of the command:
23646 * * 0x0-0xFFF8 - The function ID
23647 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
23648 * * 0xFFFD - Reserved for user-space HWRM interface
23651 uint16_t target_id;
23653 * A physical address pointer pointing to a host buffer that the
23654 * command's response data will be written. This can be either a host
23655 * physical address (HPA) or a guest physical address (GPA) and must
23656 * point to a physically contiguous block of memory.
23658 uint64_t resp_addr;
23659 /* Port ID of port that is being queried. */
23661 uint8_t unused_0[6];
23664 /* hwrm_port_mac_ptp_qcfg_output (size:704b/88B) */
23665 struct hwrm_port_mac_ptp_qcfg_output {
23666 /* The specific error status for the command. */
23667 uint16_t error_code;
23668 /* The HWRM command request type. */
23670 /* The sequence ID from the original command. */
23672 /* The length of the response data in number of bytes. */
23675 * In this field, a number of PTP related flags
23676 * are used to indicate configured PTP capabilities.
23680 * When this bit is set to '1', the PTP related registers are
23681 * directly accessible by the host.
23683 #define HWRM_PORT_MAC_PTP_QCFG_OUTPUT_FLAGS_DIRECT_ACCESS \
23686 * When this bit is set to '1', the device supports one-step
23689 #define HWRM_PORT_MAC_PTP_QCFG_OUTPUT_FLAGS_ONE_STEP_TX_TS \
23692 * When this bit is set to '1', the PTP information is accessible
23693 * via HWRM commands.
23695 #define HWRM_PORT_MAC_PTP_QCFG_OUTPUT_FLAGS_HWRM_ACCESS \
23698 * When this bit is set to '1', two specific registers for current
23699 * time (ts_ref_clock_reg_lower and ts_ref_clock_reg_upper) are
23700 * directly accessible by the host.
23702 #define HWRM_PORT_MAC_PTP_QCFG_OUTPUT_FLAGS_PARTIAL_DIRECT_ACCESS_REF_CLOCK \
23704 uint8_t unused_0[3];
23706 * Offset of the PTP register for the lower 32 bits of timestamp
23709 uint32_t rx_ts_reg_off_lower;
23711 * Offset of the PTP register for the upper 32 bits of timestamp
23714 uint32_t rx_ts_reg_off_upper;
23715 /* Offset of the PTP register for the sequence ID for RX. */
23716 uint32_t rx_ts_reg_off_seq_id;
23717 /* Offset of the first PTP source ID for RX. */
23718 uint32_t rx_ts_reg_off_src_id_0;
23719 /* Offset of the second PTP source ID for RX. */
23720 uint32_t rx_ts_reg_off_src_id_1;
23721 /* Offset of the third PTP source ID for RX. */
23722 uint32_t rx_ts_reg_off_src_id_2;
23723 /* Offset of the domain ID for RX. */
23724 uint32_t rx_ts_reg_off_domain_id;
23725 /* Offset of the PTP FIFO register for RX. */
23726 uint32_t rx_ts_reg_off_fifo;
23727 /* Offset of the PTP advance FIFO register for RX. */
23728 uint32_t rx_ts_reg_off_fifo_adv;
23729 /* PTP timestamp granularity for RX. */
23730 uint32_t rx_ts_reg_off_granularity;
23732 * Offset of the PTP register for the lower 32 bits of timestamp
23735 uint32_t tx_ts_reg_off_lower;
23737 * Offset of the PTP register for the upper 32 bits of timestamp
23740 uint32_t tx_ts_reg_off_upper;
23741 /* Offset of the PTP register for the sequence ID for TX. */
23742 uint32_t tx_ts_reg_off_seq_id;
23743 /* Offset of the PTP FIFO register for TX. */
23744 uint32_t tx_ts_reg_off_fifo;
23745 /* PTP timestamp granularity for TX. */
23746 uint32_t tx_ts_reg_off_granularity;
23747 /* Offset of register to get lower 32 bits of current time. */
23748 uint32_t ts_ref_clock_reg_lower;
23749 /* Offset of register to get upper 32 bits of current time. */
23750 uint32_t ts_ref_clock_reg_upper;
23751 uint8_t unused_1[7];
23753 * This field is used in Output records to indicate that the output
23754 * is completely written to RAM. This field should be read as '1'
23755 * to indicate that the output has been completely written.
23756 * When writing a command completion or response to an internal processor,
23757 * the order of writes has to be such that this field is written last.
23762 /* Port Tx Statistics Format */
23763 /* tx_port_stats (size:3264b/408B) */
23764 struct tx_port_stats {
23765 /* Total Number of 64 Bytes frames transmitted */
23766 uint64_t tx_64b_frames;
23767 /* Total Number of 65-127 Bytes frames transmitted */
23768 uint64_t tx_65b_127b_frames;
23769 /* Total Number of 128-255 Bytes frames transmitted */
23770 uint64_t tx_128b_255b_frames;
23771 /* Total Number of 256-511 Bytes frames transmitted */
23772 uint64_t tx_256b_511b_frames;
23773 /* Total Number of 512-1023 Bytes frames transmitted */
23774 uint64_t tx_512b_1023b_frames;
23775 /* Total Number of 1024-1518 Bytes frames transmitted */
23776 uint64_t tx_1024b_1518b_frames;
23778 * Total Number of each good VLAN (excludes FCS errors)
23779 * frame transmitted which is 1519 to 1522 bytes in length
23780 * inclusive (excluding framing bits but including FCS bytes).
23782 uint64_t tx_good_vlan_frames;
23783 /* Total Number of 1519-2047 Bytes frames transmitted */
23784 uint64_t tx_1519b_2047b_frames;
23785 /* Total Number of 2048-4095 Bytes frames transmitted */
23786 uint64_t tx_2048b_4095b_frames;
23787 /* Total Number of 4096-9216 Bytes frames transmitted */
23788 uint64_t tx_4096b_9216b_frames;
23789 /* Total Number of 9217-16383 Bytes frames transmitted */
23790 uint64_t tx_9217b_16383b_frames;
23791 /* Total Number of good frames transmitted */
23792 uint64_t tx_good_frames;
23793 /* Total Number of frames transmitted */
23794 uint64_t tx_total_frames;
23795 /* Total number of unicast frames transmitted */
23796 uint64_t tx_ucast_frames;
23797 /* Total number of multicast frames transmitted */
23798 uint64_t tx_mcast_frames;
23799 /* Total number of broadcast frames transmitted */
23800 uint64_t tx_bcast_frames;
23801 /* Total number of PAUSE control frames transmitted */
23802 uint64_t tx_pause_frames;
23804 * Total number of PFC/per-priority PAUSE
23805 * control frames transmitted
23807 uint64_t tx_pfc_frames;
23808 /* Total number of jabber frames transmitted */
23809 uint64_t tx_jabber_frames;
23810 /* Total number of frames transmitted with FCS error */
23811 uint64_t tx_fcs_err_frames;
23812 /* Total number of control frames transmitted */
23813 uint64_t tx_control_frames;
23814 /* Total number of over-sized frames transmitted */
23815 uint64_t tx_oversz_frames;
23816 /* Total number of frames with single deferral */
23817 uint64_t tx_single_dfrl_frames;
23818 /* Total number of frames with multiple deferrals */
23819 uint64_t tx_multi_dfrl_frames;
23820 /* Total number of frames with single collision */
23821 uint64_t tx_single_coll_frames;
23822 /* Total number of frames with multiple collisions */
23823 uint64_t tx_multi_coll_frames;
23824 /* Total number of frames with late collisions */
23825 uint64_t tx_late_coll_frames;
23826 /* Total number of frames with excessive collisions */
23827 uint64_t tx_excessive_coll_frames;
23828 /* Total number of fragmented frames transmitted */
23829 uint64_t tx_frag_frames;
23830 /* Total number of transmit errors */
23832 /* Total number of single VLAN tagged frames transmitted */
23833 uint64_t tx_tagged_frames;
23834 /* Total number of double VLAN tagged frames transmitted */
23835 uint64_t tx_dbl_tagged_frames;
23836 /* Total number of runt frames transmitted */
23837 uint64_t tx_runt_frames;
23838 /* Total number of TX FIFO under runs */
23839 uint64_t tx_fifo_underruns;
23841 * Total number of PFC frames with PFC enabled bit for
23842 * Pri 0 transmitted
23844 uint64_t tx_pfc_ena_frames_pri0;
23846 * Total number of PFC frames with PFC enabled bit for
23847 * Pri 1 transmitted
23849 uint64_t tx_pfc_ena_frames_pri1;
23851 * Total number of PFC frames with PFC enabled bit for
23852 * Pri 2 transmitted
23854 uint64_t tx_pfc_ena_frames_pri2;
23856 * Total number of PFC frames with PFC enabled bit for
23857 * Pri 3 transmitted
23859 uint64_t tx_pfc_ena_frames_pri3;
23861 * Total number of PFC frames with PFC enabled bit for
23862 * Pri 4 transmitted
23864 uint64_t tx_pfc_ena_frames_pri4;
23866 * Total number of PFC frames with PFC enabled bit for
23867 * Pri 5 transmitted
23869 uint64_t tx_pfc_ena_frames_pri5;
23871 * Total number of PFC frames with PFC enabled bit for
23872 * Pri 6 transmitted
23874 uint64_t tx_pfc_ena_frames_pri6;
23876 * Total number of PFC frames with PFC enabled bit for
23877 * Pri 7 transmitted
23879 uint64_t tx_pfc_ena_frames_pri7;
23880 /* Total number of EEE LPI Events on TX */
23881 uint64_t tx_eee_lpi_events;
23882 /* EEE LPI Duration Counter on TX */
23883 uint64_t tx_eee_lpi_duration;
23885 * Total number of Link Level Flow Control (LLFC) messages
23888 uint64_t tx_llfc_logical_msgs;
23889 /* Total number of HCFC messages transmitted */
23890 uint64_t tx_hcfc_msgs;
23891 /* Total number of TX collisions */
23892 uint64_t tx_total_collisions;
23893 /* Total number of transmitted bytes */
23895 /* Total number of end-to-end HOL frames */
23896 uint64_t tx_xthol_frames;
23897 /* Total Tx Drops per Port reported by STATS block */
23898 uint64_t tx_stat_discard;
23899 /* Total Tx Error Drops per Port reported by STATS block */
23900 uint64_t tx_stat_error;
23903 /* Port Rx Statistics Format */
23904 /* rx_port_stats (size:4224b/528B) */
23905 struct rx_port_stats {
23906 /* Total Number of 64 Bytes frames received */
23907 uint64_t rx_64b_frames;
23908 /* Total Number of 65-127 Bytes frames received */
23909 uint64_t rx_65b_127b_frames;
23910 /* Total Number of 128-255 Bytes frames received */
23911 uint64_t rx_128b_255b_frames;
23912 /* Total Number of 256-511 Bytes frames received */
23913 uint64_t rx_256b_511b_frames;
23914 /* Total Number of 512-1023 Bytes frames received */
23915 uint64_t rx_512b_1023b_frames;
23916 /* Total Number of 1024-1518 Bytes frames received */
23917 uint64_t rx_1024b_1518b_frames;
23919 * Total Number of each good VLAN (excludes FCS errors)
23920 * frame received which is 1519 to 1522 bytes in length
23921 * inclusive (excluding framing bits but including FCS bytes).
23923 uint64_t rx_good_vlan_frames;
23924 /* Total Number of 1519-2047 Bytes frames received */
23925 uint64_t rx_1519b_2047b_frames;
23926 /* Total Number of 2048-4095 Bytes frames received */
23927 uint64_t rx_2048b_4095b_frames;
23928 /* Total Number of 4096-9216 Bytes frames received */
23929 uint64_t rx_4096b_9216b_frames;
23930 /* Total Number of 9217-16383 Bytes frames received */
23931 uint64_t rx_9217b_16383b_frames;
23932 /* Total number of frames received */
23933 uint64_t rx_total_frames;
23934 /* Total number of unicast frames received */
23935 uint64_t rx_ucast_frames;
23936 /* Total number of multicast frames received */
23937 uint64_t rx_mcast_frames;
23938 /* Total number of broadcast frames received */
23939 uint64_t rx_bcast_frames;
23940 /* Total number of received frames with FCS error */
23941 uint64_t rx_fcs_err_frames;
23942 /* Total number of control frames received */
23943 uint64_t rx_ctrl_frames;
23944 /* Total number of PAUSE frames received */
23945 uint64_t rx_pause_frames;
23946 /* Total number of PFC frames received */
23947 uint64_t rx_pfc_frames;
23949 * Total number of frames received with an unsupported
23952 uint64_t rx_unsupported_opcode_frames;
23954 * Total number of frames received with an unsupported
23955 * DA for pause and PFC
23957 uint64_t rx_unsupported_da_pausepfc_frames;
23958 /* Total number of frames received with an unsupported SA */
23959 uint64_t rx_wrong_sa_frames;
23960 /* Total number of received packets with alignment error */
23961 uint64_t rx_align_err_frames;
23962 /* Total number of received frames with out-of-range length */
23963 uint64_t rx_oor_len_frames;
23964 /* Total number of received frames with error termination */
23965 uint64_t rx_code_err_frames;
23967 * Total number of received frames with a false carrier is
23968 * detected during idle, as defined by RX_ER samples active
23969 * and RXD is 0xE. The event is reported along with the
23970 * statistics generated on the next received frame. Only
23971 * one false carrier condition can be detected and logged
23974 * Carrier event, valid for 10M/100M speed modes only.
23976 uint64_t rx_false_carrier_frames;
23977 /* Total number of over-sized frames received */
23978 uint64_t rx_ovrsz_frames;
23979 /* Total number of jabber packets received */
23980 uint64_t rx_jbr_frames;
23981 /* Total number of received frames with MTU error */
23982 uint64_t rx_mtu_err_frames;
23983 /* Total number of received frames with CRC match */
23984 uint64_t rx_match_crc_frames;
23985 /* Total number of frames received promiscuously */
23986 uint64_t rx_promiscuous_frames;
23988 * Total number of received frames with one or two VLAN
23991 uint64_t rx_tagged_frames;
23992 /* Total number of received frames with two VLAN tags */
23993 uint64_t rx_double_tagged_frames;
23994 /* Total number of truncated frames received */
23995 uint64_t rx_trunc_frames;
23996 /* Total number of good frames (without errors) received */
23997 uint64_t rx_good_frames;
23999 * Total number of received PFC frames with transition from
24000 * XON to XOFF on Pri 0
24002 uint64_t rx_pfc_xon2xoff_frames_pri0;
24004 * Total number of received PFC frames with transition from
24005 * XON to XOFF on Pri 1
24007 uint64_t rx_pfc_xon2xoff_frames_pri1;
24009 * Total number of received PFC frames with transition from
24010 * XON to XOFF on Pri 2
24012 uint64_t rx_pfc_xon2xoff_frames_pri2;
24014 * Total number of received PFC frames with transition from
24015 * XON to XOFF on Pri 3
24017 uint64_t rx_pfc_xon2xoff_frames_pri3;
24019 * Total number of received PFC frames with transition from
24020 * XON to XOFF on Pri 4
24022 uint64_t rx_pfc_xon2xoff_frames_pri4;
24024 * Total number of received PFC frames with transition from
24025 * XON to XOFF on Pri 5
24027 uint64_t rx_pfc_xon2xoff_frames_pri5;
24029 * Total number of received PFC frames with transition from
24030 * XON to XOFF on Pri 6
24032 uint64_t rx_pfc_xon2xoff_frames_pri6;
24034 * Total number of received PFC frames with transition from
24035 * XON to XOFF on Pri 7
24037 uint64_t rx_pfc_xon2xoff_frames_pri7;
24039 * Total number of received PFC frames with PFC enabled
24042 uint64_t rx_pfc_ena_frames_pri0;
24044 * Total number of received PFC frames with PFC enabled
24047 uint64_t rx_pfc_ena_frames_pri1;
24049 * Total number of received PFC frames with PFC enabled
24052 uint64_t rx_pfc_ena_frames_pri2;
24054 * Total number of received PFC frames with PFC enabled
24057 uint64_t rx_pfc_ena_frames_pri3;
24059 * Total number of received PFC frames with PFC enabled
24062 uint64_t rx_pfc_ena_frames_pri4;
24064 * Total number of received PFC frames with PFC enabled
24067 uint64_t rx_pfc_ena_frames_pri5;
24069 * Total number of received PFC frames with PFC enabled
24072 uint64_t rx_pfc_ena_frames_pri6;
24074 * Total number of received PFC frames with PFC enabled
24077 uint64_t rx_pfc_ena_frames_pri7;
24078 /* Total Number of frames received with SCH CRC error */
24079 uint64_t rx_sch_crc_err_frames;
24080 /* Total Number of under-sized frames received */
24081 uint64_t rx_undrsz_frames;
24082 /* Total Number of fragmented frames received */
24083 uint64_t rx_frag_frames;
24084 /* Total number of RX EEE LPI Events */
24085 uint64_t rx_eee_lpi_events;
24086 /* EEE LPI Duration Counter on RX */
24087 uint64_t rx_eee_lpi_duration;
24089 * Total number of physical type Link Level Flow Control
24090 * (LLFC) messages received
24092 uint64_t rx_llfc_physical_msgs;
24094 * Total number of logical type Link Level Flow Control
24095 * (LLFC) messages received
24097 uint64_t rx_llfc_logical_msgs;
24099 * Total number of logical type Link Level Flow Control
24100 * (LLFC) messages received with CRC error
24102 uint64_t rx_llfc_msgs_with_crc_err;
24103 /* Total number of HCFC messages received */
24104 uint64_t rx_hcfc_msgs;
24105 /* Total number of HCFC messages received with CRC error */
24106 uint64_t rx_hcfc_msgs_with_crc_err;
24107 /* Total number of received bytes */
24109 /* Total number of bytes received in runt frames */
24110 uint64_t rx_runt_bytes;
24111 /* Total number of runt frames received */
24112 uint64_t rx_runt_frames;
24113 /* Total Rx Discards per Port reported by STATS block */
24114 uint64_t rx_stat_discard;
24115 uint64_t rx_stat_err;
24118 /********************
24119 * hwrm_port_qstats *
24120 ********************/
24123 /* hwrm_port_qstats_input (size:320b/40B) */
24124 struct hwrm_port_qstats_input {
24125 /* The HWRM command request type. */
24128 * The completion ring to send the completion event on. This should
24129 * be the NQ ID returned from the `nq_alloc` HWRM command.
24131 uint16_t cmpl_ring;
24133 * The sequence ID is used by the driver for tracking multiple
24134 * commands. This ID is treated as opaque data by the firmware and
24135 * the value is returned in the `hwrm_resp_hdr` upon completion.
24139 * The target ID of the command:
24140 * * 0x0-0xFFF8 - The function ID
24141 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
24142 * * 0xFFFD - Reserved for user-space HWRM interface
24145 uint16_t target_id;
24147 * A physical address pointer pointing to a host buffer that the
24148 * command's response data will be written. This can be either a host
24149 * physical address (HPA) or a guest physical address (GPA) and must
24150 * point to a physically contiguous block of memory.
24152 uint64_t resp_addr;
24153 /* Port ID of port that is being queried. */
24156 /* This value is not used to avoid backward compatibility issues. */
24157 #define HWRM_PORT_QSTATS_INPUT_FLAGS_UNUSED UINT32_C(0x0)
24159 * This bit is set to 1 when request is for a counter mask,
24160 * representing the width of each of the stats counters, rather
24161 * than counters themselves.
24163 #define HWRM_PORT_QSTATS_INPUT_FLAGS_COUNTER_MASK UINT32_C(0x1)
24164 #define HWRM_PORT_QSTATS_INPUT_FLAGS_LAST \
24165 HWRM_PORT_QSTATS_INPUT_FLAGS_COUNTER_MASK
24166 uint8_t unused_0[5];
24168 * This is the host address where
24169 * Tx port statistics will be stored
24171 uint64_t tx_stat_host_addr;
24173 * This is the host address where
24174 * Rx port statistics will be stored
24176 uint64_t rx_stat_host_addr;
24179 /* hwrm_port_qstats_output (size:128b/16B) */
24180 struct hwrm_port_qstats_output {
24181 /* The specific error status for the command. */
24182 uint16_t error_code;
24183 /* The HWRM command request type. */
24185 /* The sequence ID from the original command. */
24187 /* The length of the response data in number of bytes. */
24189 /* The size of TX port statistics block in bytes. */
24190 uint16_t tx_stat_size;
24191 /* The size of RX port statistics block in bytes. */
24192 uint16_t rx_stat_size;
24193 uint8_t unused_0[3];
24195 * This field is used in Output records to indicate that the output
24196 * is completely written to RAM. This field should be read as '1'
24197 * to indicate that the output has been completely written.
24198 * When writing a command completion or response to an internal processor,
24199 * the order of writes has to be such that this field is written last.
24204 /* Port Tx Statistics extended Format */
24205 /* tx_port_stats_ext (size:2048b/256B) */
24206 struct tx_port_stats_ext {
24207 /* Total number of tx bytes count on cos queue 0 */
24208 uint64_t tx_bytes_cos0;
24209 /* Total number of tx bytes count on cos queue 1 */
24210 uint64_t tx_bytes_cos1;
24211 /* Total number of tx bytes count on cos queue 2 */
24212 uint64_t tx_bytes_cos2;
24213 /* Total number of tx bytes count on cos queue 3 */
24214 uint64_t tx_bytes_cos3;
24215 /* Total number of tx bytes count on cos queue 4 */
24216 uint64_t tx_bytes_cos4;
24217 /* Total number of tx bytes count on cos queue 5 */
24218 uint64_t tx_bytes_cos5;
24219 /* Total number of tx bytes count on cos queue 6 */
24220 uint64_t tx_bytes_cos6;
24221 /* Total number of tx bytes count on cos queue 7 */
24222 uint64_t tx_bytes_cos7;
24223 /* Total number of tx packets count on cos queue 0 */
24224 uint64_t tx_packets_cos0;
24225 /* Total number of tx packets count on cos queue 1 */
24226 uint64_t tx_packets_cos1;
24227 /* Total number of tx packets count on cos queue 2 */
24228 uint64_t tx_packets_cos2;
24229 /* Total number of tx packets count on cos queue 3 */
24230 uint64_t tx_packets_cos3;
24231 /* Total number of tx packets count on cos queue 4 */
24232 uint64_t tx_packets_cos4;
24233 /* Total number of tx packets count on cos queue 5 */
24234 uint64_t tx_packets_cos5;
24235 /* Total number of tx packets count on cos queue 6 */
24236 uint64_t tx_packets_cos6;
24237 /* Total number of tx packets count on cos queue 7 */
24238 uint64_t tx_packets_cos7;
24239 /* time duration between transmitting a XON -> XOFF and a subsequent XOFF -> XON for priority 0 */
24240 uint64_t pfc_pri0_tx_duration_us;
24241 /* Number of times, a XON -> XOFF and XOFF -> XON transitions occur for priority 0 */
24242 uint64_t pfc_pri0_tx_transitions;
24243 /* time duration between transmitting a XON -> XOFF and a subsequent XOFF -> XON for priority 1 */
24244 uint64_t pfc_pri1_tx_duration_us;
24245 /* Number of times, a XON -> XOFF and XOFF -> XON transitions occur for priority 1 */
24246 uint64_t pfc_pri1_tx_transitions;
24247 /* time duration between transmitting a XON -> XOFF and a subsequent XOFF -> XON for priority 2 */
24248 uint64_t pfc_pri2_tx_duration_us;
24249 /* Number of times, a XON -> XOFF and XOFF -> XON transitions occur for priority 2 */
24250 uint64_t pfc_pri2_tx_transitions;
24251 /* time duration between transmitting a XON -> XOFF and a subsequent XOFF -> XON for priority 3 */
24252 uint64_t pfc_pri3_tx_duration_us;
24253 /* Number of times, a XON -> XOFF and XOFF -> XON transitions occur for priority 3 */
24254 uint64_t pfc_pri3_tx_transitions;
24255 /* time duration between transmitting a XON -> XOFF and a subsequent XOFF -> XON for priority 4 */
24256 uint64_t pfc_pri4_tx_duration_us;
24257 /* Number of times, a XON -> XOFF and XOFF -> XON transitions occur for priority 4 */
24258 uint64_t pfc_pri4_tx_transitions;
24259 /* time duration between transmitting a XON -> XOFF and a subsequent XOFF -> XON for priority 5 */
24260 uint64_t pfc_pri5_tx_duration_us;
24261 /* Number of times, a XON -> XOFF and XOFF -> XON transitions occur for priority 5 */
24262 uint64_t pfc_pri5_tx_transitions;
24263 /* time duration between transmitting a XON -> XOFF and a subsequent XOFF -> XON for priority 6 */
24264 uint64_t pfc_pri6_tx_duration_us;
24265 /* Number of times, a XON -> XOFF and XOFF -> XON transitions occur for priority 6 */
24266 uint64_t pfc_pri6_tx_transitions;
24267 /* time duration between transmitting a XON -> XOFF and a subsequent XOFF -> XON for priority 7 */
24268 uint64_t pfc_pri7_tx_duration_us;
24269 /* Number of times, a XON -> XOFF and XOFF -> XON transitions occur for priority 7 */
24270 uint64_t pfc_pri7_tx_transitions;
24273 /* Port Rx Statistics extended Format */
24274 /* rx_port_stats_ext (size:3776b/472B) */
24275 struct rx_port_stats_ext {
24276 /* Number of times link state changed to down */
24277 uint64_t link_down_events;
24278 /* Number of times the idle rings with pause bit are found */
24279 uint64_t continuous_pause_events;
24280 /* Number of times the active rings pause bit resumed back */
24281 uint64_t resume_pause_events;
24282 /* Number of times, the ROCE cos queue PFC is disabled to avoid pause flood/burst */
24283 uint64_t continuous_roce_pause_events;
24284 /* Number of times, the ROCE cos queue PFC is enabled back */
24285 uint64_t resume_roce_pause_events;
24286 /* Total number of rx bytes count on cos queue 0 */
24287 uint64_t rx_bytes_cos0;
24288 /* Total number of rx bytes count on cos queue 1 */
24289 uint64_t rx_bytes_cos1;
24290 /* Total number of rx bytes count on cos queue 2 */
24291 uint64_t rx_bytes_cos2;
24292 /* Total number of rx bytes count on cos queue 3 */
24293 uint64_t rx_bytes_cos3;
24294 /* Total number of rx bytes count on cos queue 4 */
24295 uint64_t rx_bytes_cos4;
24296 /* Total number of rx bytes count on cos queue 5 */
24297 uint64_t rx_bytes_cos5;
24298 /* Total number of rx bytes count on cos queue 6 */
24299 uint64_t rx_bytes_cos6;
24300 /* Total number of rx bytes count on cos queue 7 */
24301 uint64_t rx_bytes_cos7;
24302 /* Total number of rx packets count on cos queue 0 */
24303 uint64_t rx_packets_cos0;
24304 /* Total number of rx packets count on cos queue 1 */
24305 uint64_t rx_packets_cos1;
24306 /* Total number of rx packets count on cos queue 2 */
24307 uint64_t rx_packets_cos2;
24308 /* Total number of rx packets count on cos queue 3 */
24309 uint64_t rx_packets_cos3;
24310 /* Total number of rx packets count on cos queue 4 */
24311 uint64_t rx_packets_cos4;
24312 /* Total number of rx packets count on cos queue 5 */
24313 uint64_t rx_packets_cos5;
24314 /* Total number of rx packets count on cos queue 6 */
24315 uint64_t rx_packets_cos6;
24316 /* Total number of rx packets count on cos queue 7 */
24317 uint64_t rx_packets_cos7;
24318 /* time duration receiving a XON -> XOFF and a subsequent XOFF -> XON for priority 0 */
24319 uint64_t pfc_pri0_rx_duration_us;
24320 /* Number of times, a XON -> XOFF and XOFF -> XON transitions occur for priority 0 */
24321 uint64_t pfc_pri0_rx_transitions;
24322 /* time duration receiving a XON -> XOFF and a subsequent XOFF -> XON for priority 1 */
24323 uint64_t pfc_pri1_rx_duration_us;
24324 /* Number of times, a XON -> XOFF and XOFF -> XON transitions occur for priority 1 */
24325 uint64_t pfc_pri1_rx_transitions;
24326 /* time duration receiving a XON -> XOFF and a subsequent XOFF -> XON for priority 2 */
24327 uint64_t pfc_pri2_rx_duration_us;
24328 /* Number of times, a XON -> XOFF and XOFF -> XON transitions occur for priority 2 */
24329 uint64_t pfc_pri2_rx_transitions;
24330 /* time duration receiving a XON -> XOFF and a subsequent XOFF -> XON for priority 3 */
24331 uint64_t pfc_pri3_rx_duration_us;
24332 /* Number of times, a XON -> XOFF and XOFF -> XON transitions occur for priority 3 */
24333 uint64_t pfc_pri3_rx_transitions;
24334 /* time duration receiving a XON -> XOFF and a subsequent XOFF -> XON for priority 4 */
24335 uint64_t pfc_pri4_rx_duration_us;
24336 /* Number of times, a XON -> XOFF and XOFF -> XON transitions occur for priority 4 */
24337 uint64_t pfc_pri4_rx_transitions;
24338 /* time duration receiving a XON -> XOFF and a subsequent XOFF -> XON for priority 5 */
24339 uint64_t pfc_pri5_rx_duration_us;
24340 /* Number of times, a XON -> XOFF and XOFF -> XON transitions occur for priority 5 */
24341 uint64_t pfc_pri5_rx_transitions;
24342 /* time duration receiving a XON -> XOFF and a subsequent XOFF -> XON for priority 6 */
24343 uint64_t pfc_pri6_rx_duration_us;
24344 /* Number of times, a XON -> XOFF and XOFF -> XON transitions occur for priority 6 */
24345 uint64_t pfc_pri6_rx_transitions;
24346 /* time duration receiving a XON -> XOFF and a subsequent XOFF -> XON for priority 7 */
24347 uint64_t pfc_pri7_rx_duration_us;
24348 /* Number of times, a XON -> XOFF and XOFF -> XON transitions occur for priority 7 */
24349 uint64_t pfc_pri7_rx_transitions;
24350 /* Total number of received bits */
24352 /* The number of events where the port receive buffer was over 85% full */
24353 uint64_t rx_buffer_passed_threshold;
24355 * The number of symbol errors that wasn't corrected by FEC correction
24358 uint64_t rx_pcs_symbol_err;
24359 /* The number of corrected bits on the port according to active FEC */
24360 uint64_t rx_corrected_bits;
24361 /* Total number of rx discard bytes count on cos queue 0 */
24362 uint64_t rx_discard_bytes_cos0;
24363 /* Total number of rx discard bytes count on cos queue 1 */
24364 uint64_t rx_discard_bytes_cos1;
24365 /* Total number of rx discard bytes count on cos queue 2 */
24366 uint64_t rx_discard_bytes_cos2;
24367 /* Total number of rx discard bytes count on cos queue 3 */
24368 uint64_t rx_discard_bytes_cos3;
24369 /* Total number of rx discard bytes count on cos queue 4 */
24370 uint64_t rx_discard_bytes_cos4;
24371 /* Total number of rx discard bytes count on cos queue 5 */
24372 uint64_t rx_discard_bytes_cos5;
24373 /* Total number of rx discard bytes count on cos queue 6 */
24374 uint64_t rx_discard_bytes_cos6;
24375 /* Total number of rx discard bytes count on cos queue 7 */
24376 uint64_t rx_discard_bytes_cos7;
24377 /* Total number of rx discard packets count on cos queue 0 */
24378 uint64_t rx_discard_packets_cos0;
24379 /* Total number of rx discard packets count on cos queue 1 */
24380 uint64_t rx_discard_packets_cos1;
24381 /* Total number of rx discard packets count on cos queue 2 */
24382 uint64_t rx_discard_packets_cos2;
24383 /* Total number of rx discard packets count on cos queue 3 */
24384 uint64_t rx_discard_packets_cos3;
24385 /* Total number of rx discard packets count on cos queue 4 */
24386 uint64_t rx_discard_packets_cos4;
24387 /* Total number of rx discard packets count on cos queue 5 */
24388 uint64_t rx_discard_packets_cos5;
24389 /* Total number of rx discard packets count on cos queue 6 */
24390 uint64_t rx_discard_packets_cos6;
24391 /* Total number of rx discard packets count on cos queue 7 */
24392 uint64_t rx_discard_packets_cos7;
24393 /* Total number of FEC blocks corrected by the FEC function in the PHY */
24394 uint64_t rx_fec_corrected_blocks;
24396 * Total number of FEC blocks determined to be uncorrectable by the
24397 * FEC function in the PHY
24399 uint64_t rx_fec_uncorrectable_blocks;
24403 * Port Rx Statistics extended PFC WatchDog Format.
24404 * StormDetect and StormRevert event determination is based
24405 * on an integration period and a percentage threshold.
24406 * StormDetect event - when percentage of XOFF frames received
24407 * within an integration period exceeds the configured threshold.
24408 * StormRevert event - when percentage of XON frames received
24409 * within an integration period exceeds the configured threshold.
24410 * Actual number of XOFF/XON frames for the events to be triggered
24411 * depends on both configured integration period and sampling rate.
24412 * The statistics in this structure represent counts of specified
24413 * events from the moment the feature (PFC WatchDog) is enabled via
24414 * hwrm_queue_pfc_enable_cfg call.
24416 /* rx_port_stats_ext_pfc_wd (size:5120b/640B) */
24417 struct rx_port_stats_ext_pfc_wd {
24419 * Total number of PFC WatchDog StormDetect events detected
24422 uint64_t rx_pfc_watchdog_storms_detected_pri0;
24424 * Total number of PFC WatchDog StormDetect events detected
24427 uint64_t rx_pfc_watchdog_storms_detected_pri1;
24429 * Total number of PFC WatchDog StormDetect events detected
24432 uint64_t rx_pfc_watchdog_storms_detected_pri2;
24434 * Total number of PFC WatchDog StormDetect events detected
24437 uint64_t rx_pfc_watchdog_storms_detected_pri3;
24439 * Total number of PFC WatchDog StormDetect events detected
24442 uint64_t rx_pfc_watchdog_storms_detected_pri4;
24444 * Total number of PFC WatchDog StormDetect events detected
24447 uint64_t rx_pfc_watchdog_storms_detected_pri5;
24449 * Total number of PFC WatchDog StormDetect events detected
24452 uint64_t rx_pfc_watchdog_storms_detected_pri6;
24454 * Total number of PFC WatchDog StormDetect events detected
24457 uint64_t rx_pfc_watchdog_storms_detected_pri7;
24459 * Total number of PFC WatchDog StormRevert events detected
24462 uint64_t rx_pfc_watchdog_storms_reverted_pri0;
24464 * Total number of PFC WatchDog StormRevert events detected
24467 uint64_t rx_pfc_watchdog_storms_reverted_pri1;
24469 * Total number of PFC WatchDog StormRevert events detected
24472 uint64_t rx_pfc_watchdog_storms_reverted_pri2;
24474 * Total number of PFC WatchDog StormRevert events detected
24477 uint64_t rx_pfc_watchdog_storms_reverted_pri3;
24479 * Total number of PFC WatchDog StormRevert events detected
24482 uint64_t rx_pfc_watchdog_storms_reverted_pri4;
24484 * Total number of PFC WatchDog StormRevert events detected
24487 uint64_t rx_pfc_watchdog_storms_reverted_pri5;
24489 * Total number of PFC WatchDog StormRevert events detected
24492 uint64_t rx_pfc_watchdog_storms_reverted_pri6;
24494 * Total number of PFC WatchDog StormRevert events detected
24497 uint64_t rx_pfc_watchdog_storms_reverted_pri7;
24499 * Total number of packets received during PFC watchdog storm
24502 uint64_t rx_pfc_watchdog_storms_rx_packets_pri0;
24504 * Total number of packets received during PFC watchdog storm
24507 uint64_t rx_pfc_watchdog_storms_rx_packets_pri1;
24509 * Total number of packets received during PFC watchdog storm
24512 uint64_t rx_pfc_watchdog_storms_rx_packets_pri2;
24514 * Total number of packets received during PFC watchdog storm
24517 uint64_t rx_pfc_watchdog_storms_rx_packets_pri3;
24519 * Total number of packets received during PFC watchdog storm
24522 uint64_t rx_pfc_watchdog_storms_rx_packets_pri4;
24524 * Total number of packets received during PFC watchdog storm
24527 uint64_t rx_pfc_watchdog_storms_rx_packets_pri5;
24529 * Total number of packets received during PFC watchdog storm
24532 uint64_t rx_pfc_watchdog_storms_rx_packets_pri6;
24534 * Total number of packets received during PFC watchdog storm
24537 uint64_t rx_pfc_watchdog_storms_rx_packets_pri7;
24539 * Total number of bytes received during PFC watchdog storm
24542 uint64_t rx_pfc_watchdog_storms_rx_bytes_pri0;
24544 * Total number of bytes received during PFC watchdog storm
24547 uint64_t rx_pfc_watchdog_storms_rx_bytes_pri1;
24549 * Total number of bytes received during PFC watchdog storm
24552 uint64_t rx_pfc_watchdog_storms_rx_bytes_pri2;
24554 * Total number of bytes received during PFC watchdog storm
24557 uint64_t rx_pfc_watchdog_storms_rx_bytes_pri3;
24559 * Total number of bytes received during PFC watchdog storm
24562 uint64_t rx_pfc_watchdog_storms_rx_bytes_pri4;
24564 * Total number of bytes received during PFC watchdog storm
24567 uint64_t rx_pfc_watchdog_storms_rx_bytes_pri5;
24569 * Total number of bytes received during PFC watchdog storm
24572 uint64_t rx_pfc_watchdog_storms_rx_bytes_pri6;
24574 * Total number of bytes received during PFC watchdog storm
24577 uint64_t rx_pfc_watchdog_storms_rx_bytes_pri7;
24579 * Total number of packets dropped on rx during PFC watchdog storm
24582 uint64_t rx_pfc_watchdog_storms_rx_packets_dropped_pri0;
24584 * Total number of packets dropped on rx during PFC watchdog storm
24587 uint64_t rx_pfc_watchdog_storms_rx_packets_dropped_pri1;
24589 * Total number of packets dropped on rx during PFC watchdog storm
24592 uint64_t rx_pfc_watchdog_storms_rx_packets_dropped_pri2;
24594 * Total number of packets dropped on rx during PFC watchdog storm
24597 uint64_t rx_pfc_watchdog_storms_rx_packets_dropped_pri3;
24599 * Total number of packets dropped on rx during PFC watchdog storm
24602 uint64_t rx_pfc_watchdog_storms_rx_packets_dropped_pri4;
24604 * Total number of packets dropped on rx during PFC watchdog storm
24607 uint64_t rx_pfc_watchdog_storms_rx_packets_dropped_pri5;
24609 * Total number of packets dropped on rx during PFC watchdog storm
24612 uint64_t rx_pfc_watchdog_storms_rx_packets_dropped_pri6;
24614 * Total number of packets dropped on rx during PFC watchdog storm
24617 uint64_t rx_pfc_watchdog_storms_rx_packets_dropped_pri7;
24619 * Total number of bytes dropped on rx during PFC watchdog storm
24622 uint64_t rx_pfc_watchdog_storms_rx_bytes_dropped_pri0;
24624 * Total number of bytes dropped on rx during PFC watchdog storm
24627 uint64_t rx_pfc_watchdog_storms_rx_bytes_dropped_pri1;
24629 * Total number of bytes dropped on rx during PFC watchdog storm
24632 uint64_t rx_pfc_watchdog_storms_rx_bytes_dropped_pri2;
24634 * Total number of bytes dropped on rx during PFC watchdog storm
24637 uint64_t rx_pfc_watchdog_storms_rx_bytes_dropped_pri3;
24639 * Total number of bytes dropped on rx during PFC watchdog storm
24642 uint64_t rx_pfc_watchdog_storms_rx_bytes_dropped_pri4;
24644 * Total number of bytes dropped on rx during PFC watchdog storm
24647 uint64_t rx_pfc_watchdog_storms_rx_bytes_dropped_pri5;
24649 * Total number of bytes dropped on rx during PFC watchdog storm
24652 uint64_t rx_pfc_watchdog_storms_rx_bytes_dropped_pri6;
24654 * Total number of bytes dropped on rx during PFC watchdog storm
24657 uint64_t rx_pfc_watchdog_storms_rx_bytes_dropped_pri7;
24659 * Number of packets received during last PFC watchdog storm
24662 uint64_t rx_pfc_watchdog_last_storm_rx_packets_pri0;
24664 * Number of packets received during last PFC watchdog storm
24667 uint64_t rx_pfc_watchdog_last_storm_rx_packets_pri1;
24669 * Number of packets received during last PFC watchdog storm
24672 uint64_t rx_pfc_watchdog_last_storm_rx_packets_pri2;
24674 * Number of packets received during last PFC watchdog storm
24677 uint64_t rx_pfc_watchdog_last_storm_rx_packets_pri3;
24679 * Number of packets received during last PFC watchdog storm
24682 uint64_t rx_pfc_watchdog_last_storm_rx_packets_pri4;
24684 * Number of packets received during last PFC watchdog storm
24687 uint64_t rx_pfc_watchdog_last_storm_rx_packets_pri5;
24689 * Number of packets received during last PFC watchdog storm
24692 uint64_t rx_pfc_watchdog_last_storm_rx_packets_pri6;
24694 * Number of packets received during last PFC watchdog storm
24697 uint64_t rx_pfc_watchdog_last_storm_rx_packets_pri7;
24699 * Number of bytes received during last PFC watchdog storm
24702 uint64_t rx_pfc_watchdog_last_storm_rx_bytes_pri0;
24704 * Number of bytes received during last PFC watchdog storm
24707 uint64_t rx_pfc_watchdog_last_storm_rx_bytes_pri1;
24709 * Number of bytes received during last PFC watchdog storm
24712 uint64_t rx_pfc_watchdog_last_storm_rx_bytes_pri2;
24714 * Number of bytes received during last PFC watchdog storm
24717 uint64_t rx_pfc_watchdog_last_storm_rx_bytes_pri3;
24719 * Number of bytes received during last PFC watchdog storm
24722 uint64_t rx_pfc_watchdog_last_storm_rx_bytes_pri4;
24724 * Number of bytes received during last PFC watchdog storm
24727 uint64_t rx_pfc_watchdog_last_storm_rx_bytes_pri5;
24729 * Number of bytes received during last PFC watchdog storm
24732 uint64_t rx_pfc_watchdog_last_storm_rx_bytes_pri6;
24734 * Number of bytes received during last PFC watchdog storm
24737 uint64_t rx_pfc_watchdog_last_storm_rx_bytes_pri7;
24739 * Number of packets dropped on rx during last PFC watchdog storm
24742 uint64_t rx_pfc_watchdog_last_storm_rx_packets_dropped_pri0;
24744 * Number of packets dropped on rx during last PFC watchdog storm
24747 uint64_t rx_pfc_watchdog_last_storm_rx_packets_dropped_pri1;
24749 * Number of packets dropped on rx during last PFC watchdog storm
24752 uint64_t rx_pfc_watchdog_last_storm_rx_packets_dropped_pri2;
24754 * Number of packets dropped on rx during last PFC watchdog storm
24757 uint64_t rx_pfc_watchdog_last_storm_rx_packets_dropped_pri3;
24759 * Number of packets dropped on rx during last PFC watchdog storm
24762 uint64_t rx_pfc_watchdog_last_storm_rx_packets_dropped_pri4;
24764 * Number of packets dropped on rx during last PFC watchdog storm
24767 uint64_t rx_pfc_watchdog_last_storm_rx_packets_dropped_pri5;
24769 * Number of packets dropped on rx during last PFC watchdog storm
24772 uint64_t rx_pfc_watchdog_last_storm_rx_packets_dropped_pri6;
24774 * Number of packets dropped on rx during last PFC watchdog storm
24777 uint64_t rx_pfc_watchdog_last_storm_rx_packets_dropped_pri7;
24779 * Total number of bytes dropped on rx during PFC watchdog storm
24782 uint64_t rx_pfc_watchdog_last_storm_rx_bytes_dropped_pri0;
24784 * Number of bytes dropped on rx during last PFC watchdog storm
24787 uint64_t rx_pfc_watchdog_last_storm_rx_bytes_dropped_pri1;
24789 * Number of bytes dropped on rx during last PFC watchdog storm
24792 uint64_t rx_pfc_watchdog_last_storm_rx_bytes_dropped_pri2;
24794 * Number of bytes dropped on rx during last PFC watchdog storm
24797 uint64_t rx_pfc_watchdog_last_storm_rx_bytes_dropped_pri3;
24799 * Number of bytes dropped on rx during last PFC watchdog storm
24802 uint64_t rx_pfc_watchdog_last_storm_rx_bytes_dropped_pri4;
24804 * Number of bytes dropped on rx during last PFC watchdog storm
24807 uint64_t rx_pfc_watchdog_last_storm_rx_bytes_dropped_pri5;
24809 * Number of bytes dropped on rx during last PFC watchdog storm
24812 uint64_t rx_pfc_watchdog_last_storm_rx_bytes_dropped_pri6;
24814 * Number of bytes dropped on rx during last PFC watchdog storm
24817 uint64_t rx_pfc_watchdog_last_storm_rx_bytes_dropped_pri7;
24820 /************************
24821 * hwrm_port_qstats_ext *
24822 ************************/
24825 /* hwrm_port_qstats_ext_input (size:320b/40B) */
24826 struct hwrm_port_qstats_ext_input {
24827 /* The HWRM command request type. */
24830 * The completion ring to send the completion event on. This should
24831 * be the NQ ID returned from the `nq_alloc` HWRM command.
24833 uint16_t cmpl_ring;
24835 * The sequence ID is used by the driver for tracking multiple
24836 * commands. This ID is treated as opaque data by the firmware and
24837 * the value is returned in the `hwrm_resp_hdr` upon completion.
24841 * The target ID of the command:
24842 * * 0x0-0xFFF8 - The function ID
24843 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
24844 * * 0xFFFD - Reserved for user-space HWRM interface
24847 uint16_t target_id;
24849 * A physical address pointer pointing to a host buffer that the
24850 * command's response data will be written. This can be either a host
24851 * physical address (HPA) or a guest physical address (GPA) and must
24852 * point to a physically contiguous block of memory.
24854 uint64_t resp_addr;
24855 /* Port ID of port that is being queried. */
24858 * The size of TX port extended
24859 * statistics block in bytes.
24861 uint16_t tx_stat_size;
24863 * The size of RX port extended
24864 * statistics block in bytes
24866 uint16_t rx_stat_size;
24868 /* This value is not used to avoid backward compatibility issues. */
24869 #define HWRM_PORT_QSTATS_EXT_INPUT_FLAGS_UNUSED UINT32_C(0x0)
24871 * This bit is set to 1 when request is for the counter mask,
24872 * representing width of each of the stats counters, rather than
24873 * counters themselves.
24875 #define HWRM_PORT_QSTATS_EXT_INPUT_FLAGS_COUNTER_MASK UINT32_C(0x1)
24876 #define HWRM_PORT_QSTATS_EXT_INPUT_FLAGS_LAST \
24877 HWRM_PORT_QSTATS_EXT_INPUT_FLAGS_COUNTER_MASK
24880 * This is the host address where
24881 * Tx port statistics will be stored
24883 uint64_t tx_stat_host_addr;
24885 * This is the host address where
24886 * Rx port statistics will be stored
24888 uint64_t rx_stat_host_addr;
24891 /* hwrm_port_qstats_ext_output (size:128b/16B) */
24892 struct hwrm_port_qstats_ext_output {
24893 /* The specific error status for the command. */
24894 uint16_t error_code;
24895 /* The HWRM command request type. */
24897 /* The sequence ID from the original command. */
24899 /* The length of the response data in number of bytes. */
24901 /* The size of TX port statistics block in bytes. */
24902 uint16_t tx_stat_size;
24903 /* The size of RX port statistics block in bytes. */
24904 uint16_t rx_stat_size;
24905 /* Total number of active cos queues available. */
24906 uint16_t total_active_cos_queues;
24909 * If set to 1, then this field indicates that clear
24910 * roce specific counters is supported.
24912 #define HWRM_PORT_QSTATS_EXT_OUTPUT_FLAGS_CLEAR_ROCE_COUNTERS_SUPPORTED \
24915 * This field is used in Output records to indicate that the output
24916 * is completely written to RAM. This field should be read as '1'
24917 * to indicate that the output has been completely written.
24918 * When writing a command completion or response to an internal processor,
24919 * the order of writes has to be such that this field is written last.
24924 /*******************************
24925 * hwrm_port_qstats_ext_pfc_wd *
24926 *******************************/
24929 /* hwrm_port_qstats_ext_pfc_wd_input (size:256b/32B) */
24930 struct hwrm_port_qstats_ext_pfc_wd_input {
24931 /* The HWRM command request type. */
24934 * The completion ring to send the completion event on. This should
24935 * be the NQ ID returned from the `nq_alloc` HWRM command.
24937 uint16_t cmpl_ring;
24939 * The sequence ID is used by the driver for tracking multiple
24940 * commands. This ID is treated as opaque data by the firmware and
24941 * the value is returned in the `hwrm_resp_hdr` upon completion.
24945 * The target ID of the command:
24946 * * 0x0-0xFFF8 - The function ID
24947 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
24948 * * 0xFFFD - Reserved for user-space HWRM interface
24951 uint16_t target_id;
24953 * A physical address pointer pointing to a host buffer that the
24954 * command's response data will be written. This can be either a host
24955 * physical address (HPA) or a guest physical address (GPA) and must
24956 * point to a physically contiguous block of memory.
24958 uint64_t resp_addr;
24959 /* Port ID of port that is being queried. */
24962 * The size of rx_port_stats_ext_pfc_wd
24965 uint16_t pfc_wd_stat_size;
24966 uint8_t unused_0[4];
24968 * This is the host address where
24969 * rx_port_stats_ext_pfc_wd will be stored
24971 uint64_t pfc_wd_stat_host_addr;
24974 /* hwrm_port_qstats_ext_pfc_wd_output (size:128b/16B) */
24975 struct hwrm_port_qstats_ext_pfc_wd_output {
24976 /* The specific error status for the command. */
24977 uint16_t error_code;
24978 /* The HWRM command request type. */
24980 /* The sequence ID from the original command. */
24982 /* The length of the response data in number of bytes. */
24985 * The size of rx_port_stats_ext_pfc_wd
24986 * statistics block in bytes.
24988 uint16_t pfc_wd_stat_size;
24991 * This field is used in Output records to indicate that the output
24992 * is completely written to RAM. This field should be read as '1'
24993 * to indicate that the output has been completely written.
24994 * When writing a command completion or response to an internal processor,
24995 * the order of writes has to be such that this field is written last.
24998 uint8_t unused_0[4];
25001 /*************************
25002 * hwrm_port_lpbk_qstats *
25003 *************************/
25006 /* hwrm_port_lpbk_qstats_input (size:128b/16B) */
25007 struct hwrm_port_lpbk_qstats_input {
25008 /* The HWRM command request type. */
25011 * The completion ring to send the completion event on. This should
25012 * be the NQ ID returned from the `nq_alloc` HWRM command.
25014 uint16_t cmpl_ring;
25016 * The sequence ID is used by the driver for tracking multiple
25017 * commands. This ID is treated as opaque data by the firmware and
25018 * the value is returned in the `hwrm_resp_hdr` upon completion.
25022 * The target ID of the command:
25023 * * 0x0-0xFFF8 - The function ID
25024 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
25025 * * 0xFFFD - Reserved for user-space HWRM interface
25028 uint16_t target_id;
25030 * A physical address pointer pointing to a host buffer that the
25031 * command's response data will be written. This can be either a host
25032 * physical address (HPA) or a guest physical address (GPA) and must
25033 * point to a physically contiguous block of memory.
25035 uint64_t resp_addr;
25038 /* hwrm_port_lpbk_qstats_output (size:768b/96B) */
25039 struct hwrm_port_lpbk_qstats_output {
25040 /* The specific error status for the command. */
25041 uint16_t error_code;
25042 /* The HWRM command request type. */
25044 /* The sequence ID from the original command. */
25046 /* The length of the response data in number of bytes. */
25048 /* Number of transmitted unicast frames */
25049 uint64_t lpbk_ucast_frames;
25050 /* Number of transmitted multicast frames */
25051 uint64_t lpbk_mcast_frames;
25052 /* Number of transmitted broadcast frames */
25053 uint64_t lpbk_bcast_frames;
25054 /* Number of transmitted bytes for unicast traffic */
25055 uint64_t lpbk_ucast_bytes;
25056 /* Number of transmitted bytes for multicast traffic */
25057 uint64_t lpbk_mcast_bytes;
25058 /* Number of transmitted bytes for broadcast traffic */
25059 uint64_t lpbk_bcast_bytes;
25060 /* Total Tx Drops for loopback traffic reported by STATS block */
25061 uint64_t tx_stat_discard;
25062 /* Total Tx Error Drops for loopback traffic reported by STATS block */
25063 uint64_t tx_stat_error;
25064 /* Total Rx Drops for loopback traffic reported by STATS block */
25065 uint64_t rx_stat_discard;
25066 /* Total Rx Error Drops for loopback traffic reported by STATS block */
25067 uint64_t rx_stat_error;
25068 uint8_t unused_0[7];
25070 * This field is used in Output records to indicate that the output
25071 * is completely written to RAM. This field should be read as '1'
25072 * to indicate that the output has been completely written.
25073 * When writing a command completion or response to an internal processor,
25074 * the order of writes has to be such that this field is written last.
25079 /************************
25080 * hwrm_port_ecn_qstats *
25081 ************************/
25084 /* hwrm_port_ecn_qstats_input (size:256b/32B) */
25085 struct hwrm_port_ecn_qstats_input {
25086 /* The HWRM command request type. */
25089 * The completion ring to send the completion event on. This should
25090 * be the NQ ID returned from the `nq_alloc` HWRM command.
25092 uint16_t cmpl_ring;
25094 * The sequence ID is used by the driver for tracking multiple
25095 * commands. This ID is treated as opaque data by the firmware and
25096 * the value is returned in the `hwrm_resp_hdr` upon completion.
25100 * The target ID of the command:
25101 * * 0x0-0xFFF8 - The function ID
25102 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
25103 * * 0xFFFD - Reserved for user-space HWRM interface
25106 uint16_t target_id;
25108 * A physical address pointer pointing to a host buffer that the
25109 * command's response data will be written. This can be either a host
25110 * physical address (HPA) or a guest physical address (GPA) and must
25111 * point to a physically contiguous block of memory.
25113 uint64_t resp_addr;
25115 * Port ID of port that is being queried. Unused if NIC is in
25120 * Size of the DMA buffer the caller has allocated for the firmware to
25123 uint16_t ecn_stat_buf_size;
25125 /* This value is not used to avoid backward compatibility issues. */
25126 #define HWRM_PORT_ECN_QSTATS_INPUT_FLAGS_UNUSED UINT32_C(0x0)
25128 * This bit is set to 1 when request is for a counter mask,
25129 * representing the width of each of the stats counters, rather
25130 * than counters themselves.
25132 #define HWRM_PORT_ECN_QSTATS_INPUT_FLAGS_COUNTER_MASK UINT32_C(0x1)
25133 #define HWRM_PORT_ECN_QSTATS_INPUT_FLAGS_LAST \
25134 HWRM_PORT_ECN_QSTATS_INPUT_FLAGS_COUNTER_MASK
25135 uint8_t unused_0[3];
25137 * This is the host address where
25138 * ECN port statistics will be stored
25140 uint64_t ecn_stat_host_addr;
25143 /* hwrm_port_ecn_qstats_output (size:128b/16B) */
25144 struct hwrm_port_ecn_qstats_output {
25145 /* The specific error status for the command. */
25146 uint16_t error_code;
25147 /* The HWRM command request type. */
25149 /* The sequence ID from the original command. */
25151 /* The length of the response data in number of bytes. */
25153 /* Number of bytes of stats the firmware wrote to the DMA buffer. */
25154 uint16_t ecn_stat_buf_size;
25156 * Bitmask that indicates which CoS queues have ECN marking enabled.
25157 * Bit i corresponds to CoS queue i.
25160 uint8_t unused_0[4];
25162 * This field is used in Output records to indicate that the output
25163 * is completely written to RAM. This field should be read as '1'
25164 * to indicate that the output has been completely written.
25165 * When writing a command completion or response to an internal processor,
25166 * the order of writes has to be such that this field is written last.
25171 /* ECN mark statistics format */
25172 /* port_stats_ecn (size:512b/64B) */
25173 struct port_stats_ecn {
25175 * Number of packets marked in CoS queue 0.
25176 * Or, if the driver requested counter masks, a mask to indicate the size
25179 uint64_t mark_cnt_cos0;
25181 * Number of packets marked in CoS queue 1.
25182 * Or, if the driver requested counter masks, a mask to indicate the size
25185 uint64_t mark_cnt_cos1;
25187 * Number of packets marked in CoS queue 2.
25188 * Or, if the driver requested counter masks, a mask to indicate the size
25191 uint64_t mark_cnt_cos2;
25193 * Number of packets marked in CoS queue 3.
25194 * Or, if the driver requested counter masks, a mask to indicate the size
25197 uint64_t mark_cnt_cos3;
25199 * Number of packets marked in CoS queue 4.
25200 * Or, if the driver requested counter masks, a mask to indicate the size
25203 uint64_t mark_cnt_cos4;
25205 * Number of packets marked in CoS queue 5.
25206 * Or, if the driver requested counter masks, a mask to indicate the size
25209 uint64_t mark_cnt_cos5;
25211 * Number of packets marked in CoS queue 6.
25212 * Or, if the driver requested counter masks, a mask to indicate the size
25215 uint64_t mark_cnt_cos6;
25217 * Number of packets marked in CoS queue 7.
25218 * Or, if the driver requested counter masks, a mask to indicate the size
25221 uint64_t mark_cnt_cos7;
25224 /***********************
25225 * hwrm_port_clr_stats *
25226 ***********************/
25229 /* hwrm_port_clr_stats_input (size:192b/24B) */
25230 struct hwrm_port_clr_stats_input {
25231 /* The HWRM command request type. */
25234 * The completion ring to send the completion event on. This should
25235 * be the NQ ID returned from the `nq_alloc` HWRM command.
25237 uint16_t cmpl_ring;
25239 * The sequence ID is used by the driver for tracking multiple
25240 * commands. This ID is treated as opaque data by the firmware and
25241 * the value is returned in the `hwrm_resp_hdr` upon completion.
25245 * The target ID of the command:
25246 * * 0x0-0xFFF8 - The function ID
25247 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
25248 * * 0xFFFD - Reserved for user-space HWRM interface
25251 uint16_t target_id;
25253 * A physical address pointer pointing to a host buffer that the
25254 * command's response data will be written. This can be either a host
25255 * physical address (HPA) or a guest physical address (GPA) and must
25256 * point to a physically contiguous block of memory.
25258 uint64_t resp_addr;
25259 /* Port ID of port that is being queried. */
25263 * If set to 1, then this field indicates clear the following RoCE
25264 * specific counters.
25265 * RoCE associated TX/RX cos counters
25266 * CNP associated TX/RX cos counters
25267 * RoCE/CNP specific TX/RX flow counters
25268 * Firmware will determine the RoCE/CNP cos queue based on qos profile.
25269 * This flag is honored only when RoCE is enabled on that port.
25271 #define HWRM_PORT_CLR_STATS_INPUT_FLAGS_ROCE_COUNTERS UINT32_C(0x1)
25272 uint8_t unused_0[5];
25275 /* hwrm_port_clr_stats_output (size:128b/16B) */
25276 struct hwrm_port_clr_stats_output {
25277 /* The specific error status for the command. */
25278 uint16_t error_code;
25279 /* The HWRM command request type. */
25281 /* The sequence ID from the original command. */
25283 /* The length of the response data in number of bytes. */
25285 uint8_t unused_0[7];
25287 * This field is used in Output records to indicate that the output
25288 * is completely written to RAM. This field should be read as '1'
25289 * to indicate that the output has been completely written.
25290 * When writing a command completion or response to an internal processor,
25291 * the order of writes has to be such that this field is written last.
25296 /***********************
25297 * hwrm_port_phy_qcaps *
25298 ***********************/
25301 /* hwrm_port_phy_qcaps_input (size:192b/24B) */
25302 struct hwrm_port_phy_qcaps_input {
25303 /* The HWRM command request type. */
25306 * The completion ring to send the completion event on. This should
25307 * be the NQ ID returned from the `nq_alloc` HWRM command.
25309 uint16_t cmpl_ring;
25311 * The sequence ID is used by the driver for tracking multiple
25312 * commands. This ID is treated as opaque data by the firmware and
25313 * the value is returned in the `hwrm_resp_hdr` upon completion.
25317 * The target ID of the command:
25318 * * 0x0-0xFFF8 - The function ID
25319 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
25320 * * 0xFFFD - Reserved for user-space HWRM interface
25323 uint16_t target_id;
25325 * A physical address pointer pointing to a host buffer that the
25326 * command's response data will be written. This can be either a host
25327 * physical address (HPA) or a guest physical address (GPA) and must
25328 * point to a physically contiguous block of memory.
25330 uint64_t resp_addr;
25331 /* Port ID of port that is being queried. */
25333 uint8_t unused_0[6];
25336 /* hwrm_port_phy_qcaps_output (size:256b/32B) */
25337 struct hwrm_port_phy_qcaps_output {
25338 /* The specific error status for the command. */
25339 uint16_t error_code;
25340 /* The HWRM command request type. */
25342 /* The sequence ID from the original command. */
25344 /* The length of the response data in number of bytes. */
25346 /* PHY capability flags */
25349 * If set to 1, then this field indicates that the
25350 * link is capable of supporting EEE.
25352 #define HWRM_PORT_PHY_QCAPS_OUTPUT_FLAGS_EEE_SUPPORTED \
25355 * If set to 1, then this field indicates that the
25356 * PHY is capable of supporting external loopback.
25358 #define HWRM_PORT_PHY_QCAPS_OUTPUT_FLAGS_EXTERNAL_LPBK_SUPPORTED \
25361 * If set to 1, then this field indicates that the
25362 * PHY is capable of supporting loopback in autoneg mode.
25364 #define HWRM_PORT_PHY_QCAPS_OUTPUT_FLAGS_AUTONEG_LPBK_SUPPORTED \
25367 * Indicates if the configuration of shared PHY settings is supported.
25368 * In cases where a physical port is shared by multiple functions
25369 * (e.g. NPAR, multihost, etc), the configuration of PHY
25370 * settings may not be allowed. Callers to HWRM_PORT_PHY_CFG will
25371 * get an HWRM_ERR_CODE_RESOURCE_ACCESS_DENIED error in this case.
25373 #define HWRM_PORT_PHY_QCAPS_OUTPUT_FLAGS_SHARED_PHY_CFG_SUPPORTED \
25376 * If set to 1, it indicates that the port counters and extended
25377 * port counters will not reset when the firmware shuts down or
25378 * resets the PHY. These counters will only be reset during power
25379 * cycle or by calling HWRM_PORT_CLR_STATS.
25380 * If set to 0, the state of the counters is unspecified when
25381 * firmware shuts down or resets the PHY.
25383 #define HWRM_PORT_PHY_QCAPS_OUTPUT_FLAGS_CUMULATIVE_COUNTERS_ON_RESET \
25386 * If set to 1, then this field indicates that the
25387 * local loopback is not supported on this controller.
25389 #define HWRM_PORT_PHY_QCAPS_OUTPUT_FLAGS_LOCAL_LPBK_NOT_SUPPORTED \
25392 * If set to 1, then this field indicates that the
25393 * PHY/Link down policy during PF shutdown is totally
25394 * controlled by the firmware. It can shutdown the link
25395 * even when there are active VFs associated with the PF.
25396 * Host PF driver can send HWRM_PHY_CFG command to bring
25397 * down the PHY even when the port is shared between VFs
25400 #define HWRM_PORT_PHY_QCAPS_OUTPUT_FLAGS_FW_MANAGED_LINK_DOWN \
25403 * If set to 1, this field indicates that the FCS may
25404 * be disabled for a given packet via the transmit
25405 * buffer descriptor.
25407 #define HWRM_PORT_PHY_QCAPS_OUTPUT_FLAGS_NO_FCS \
25409 /* Number of front panel ports for this device. */
25411 /* Not supported or unknown */
25412 #define HWRM_PORT_PHY_QCAPS_OUTPUT_PORT_CNT_UNKNOWN UINT32_C(0x0)
25413 /* single port device */
25414 #define HWRM_PORT_PHY_QCAPS_OUTPUT_PORT_CNT_1 UINT32_C(0x1)
25415 /* 2-port device */
25416 #define HWRM_PORT_PHY_QCAPS_OUTPUT_PORT_CNT_2 UINT32_C(0x2)
25417 /* 3-port device */
25418 #define HWRM_PORT_PHY_QCAPS_OUTPUT_PORT_CNT_3 UINT32_C(0x3)
25419 /* 4-port device */
25420 #define HWRM_PORT_PHY_QCAPS_OUTPUT_PORT_CNT_4 UINT32_C(0x4)
25421 /* 12-port device */
25422 #define HWRM_PORT_PHY_QCAPS_OUTPUT_PORT_CNT_12 UINT32_C(0xc)
25423 #define HWRM_PORT_PHY_QCAPS_OUTPUT_PORT_CNT_LAST \
25424 HWRM_PORT_PHY_QCAPS_OUTPUT_PORT_CNT_12
25426 * This is a bit mask to indicate what speeds are supported
25427 * as forced speeds on this link.
25428 * For each speed that can be forced on this link, the
25429 * corresponding mask bit shall be set to '1'.
25431 uint16_t supported_speeds_force_mode;
25432 /* 100Mb link speed (Half-duplex) */
25433 #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_FORCE_MODE_100MBHD \
25435 /* 100Mb link speed (Full-duplex) */
25436 #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_FORCE_MODE_100MB \
25438 /* 1Gb link speed (Half-duplex) */
25439 #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_FORCE_MODE_1GBHD \
25441 /* 1Gb link speed (Full-duplex) */
25442 #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_FORCE_MODE_1GB \
25444 /* 2Gb link speed */
25445 #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_FORCE_MODE_2GB \
25447 /* 25Gb link speed */
25448 #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_FORCE_MODE_2_5GB \
25450 /* 10Gb link speed */
25451 #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_FORCE_MODE_10GB \
25453 /* 20Gb link speed */
25454 #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_FORCE_MODE_20GB \
25456 /* 25Gb link speed */
25457 #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_FORCE_MODE_25GB \
25459 /* 40Gb link speed */
25460 #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_FORCE_MODE_40GB \
25462 /* 50Gb link speed */
25463 #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_FORCE_MODE_50GB \
25465 /* 100Gb link speed */
25466 #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_FORCE_MODE_100GB \
25468 /* 10Mb link speed (Half-duplex) */
25469 #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_FORCE_MODE_10MBHD \
25471 /* 10Mb link speed (Full-duplex) */
25472 #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_FORCE_MODE_10MB \
25475 * This is a bit mask to indicate what speeds are supported
25476 * for autonegotiation on this link.
25477 * For each speed that can be autonegotiated on this link, the
25478 * corresponding mask bit shall be set to '1'.
25480 uint16_t supported_speeds_auto_mode;
25481 /* 100Mb link speed (Half-duplex) */
25482 #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_AUTO_MODE_100MBHD \
25484 /* 100Mb link speed (Full-duplex) */
25485 #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_AUTO_MODE_100MB \
25487 /* 1Gb link speed (Half-duplex) */
25488 #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_AUTO_MODE_1GBHD \
25490 /* 1Gb link speed (Full-duplex) */
25491 #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_AUTO_MODE_1GB \
25493 /* 2Gb link speed */
25494 #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_AUTO_MODE_2GB \
25496 /* 25Gb link speed */
25497 #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_AUTO_MODE_2_5GB \
25499 /* 10Gb link speed */
25500 #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_AUTO_MODE_10GB \
25502 /* 20Gb link speed */
25503 #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_AUTO_MODE_20GB \
25505 /* 25Gb link speed */
25506 #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_AUTO_MODE_25GB \
25508 /* 40Gb link speed */
25509 #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_AUTO_MODE_40GB \
25511 /* 50Gb link speed */
25512 #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_AUTO_MODE_50GB \
25514 /* 100Gb link speed */
25515 #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_AUTO_MODE_100GB \
25517 /* 10Mb link speed (Half-duplex) */
25518 #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_AUTO_MODE_10MBHD \
25520 /* 10Mb link speed (Full-duplex) */
25521 #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_AUTO_MODE_10MB \
25524 * This is a bit mask to indicate what speeds are supported
25525 * for EEE on this link.
25526 * For each speed that can be autonegotiated when EEE is enabled
25527 * on this link, the corresponding mask bit shall be set to '1'.
25528 * This field is only valid when the eee_supported is set to '1'.
25530 uint16_t supported_speeds_eee_mode;
25532 #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_EEE_MODE_RSVD1 \
25534 /* 100Mb link speed (Full-duplex) */
25535 #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_EEE_MODE_100MB \
25538 #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_EEE_MODE_RSVD2 \
25540 /* 1Gb link speed (Full-duplex) */
25541 #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_EEE_MODE_1GB \
25544 #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_EEE_MODE_RSVD3 \
25547 #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_EEE_MODE_RSVD4 \
25549 /* 10Gb link speed */
25550 #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_EEE_MODE_10GB \
25552 uint32_t tx_lpi_timer_low;
25554 * The lowest value of TX LPI timer that can be set on this link
25555 * when EEE is enabled. This value is in microseconds.
25556 * This field is valid only when_eee_supported is set to '1'.
25558 #define HWRM_PORT_PHY_QCAPS_OUTPUT_TX_LPI_TIMER_LOW_MASK \
25560 #define HWRM_PORT_PHY_QCAPS_OUTPUT_TX_LPI_TIMER_LOW_SFT 0
25562 * Reserved field. The HWRM shall set this field to 0.
25563 * An HWRM client shall ignore this field.
25565 #define HWRM_PORT_PHY_QCAPS_OUTPUT_RSVD2_MASK \
25566 UINT32_C(0xff000000)
25567 #define HWRM_PORT_PHY_QCAPS_OUTPUT_RSVD2_SFT 24
25568 uint32_t valid_tx_lpi_timer_high;
25570 * The highest value of TX LPI timer that can be set on this link
25571 * when EEE is enabled. This value is in microseconds.
25572 * This field is valid only when_eee_supported is set to '1'.
25574 #define HWRM_PORT_PHY_QCAPS_OUTPUT_TX_LPI_TIMER_HIGH_MASK \
25576 #define HWRM_PORT_PHY_QCAPS_OUTPUT_TX_LPI_TIMER_HIGH_SFT 0
25578 * Reserved field. The HWRM shall set this field to 0.
25579 * An HWRM client shall ignore this field.
25581 #define HWRM_PORT_PHY_QCAPS_OUTPUT_RSVD_MASK \
25582 UINT32_C(0xff000000)
25583 #define HWRM_PORT_PHY_QCAPS_OUTPUT_RSVD_SFT 24
25585 * This field is used to advertise which PAM4 speeds are supported
25588 uint16_t supported_pam4_speeds_auto_mode;
25589 #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_PAM4_SPEEDS_AUTO_MODE_50G \
25591 #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_PAM4_SPEEDS_AUTO_MODE_100G \
25593 #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_PAM4_SPEEDS_AUTO_MODE_200G \
25596 * This field is used to advertise which PAM4 speeds are supported
25599 uint16_t supported_pam4_speeds_force_mode;
25600 #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_PAM4_SPEEDS_FORCE_MODE_50G \
25602 #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_PAM4_SPEEDS_FORCE_MODE_100G \
25604 #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_PAM4_SPEEDS_FORCE_MODE_200G \
25606 /* More PHY capability flags */
25609 * If set to 1, then this field indicates that
25610 * 802.3x flow control is not supported.
25612 #define HWRM_PORT_PHY_QCAPS_OUTPUT_FLAGS2_PAUSE_UNSUPPORTED \
25615 * If set to 1, then this field indicates that
25616 * priority-based flow control is not supported.
25618 #define HWRM_PORT_PHY_QCAPS_OUTPUT_FLAGS2_PFC_UNSUPPORTED \
25621 * Number of internal ports for this device. This field allows the FW
25622 * to advertise how many internal ports are present. Manufacturing
25623 * tools uses this to determine how many internal ports should have
25624 * the PRBS test run on them. This field always return 0 unless NVM
25625 * option "HPTN_MODE" is set to 1.
25627 uint8_t internal_port_cnt;
25629 * This field is used in Output records to indicate that the output
25630 * is completely written to RAM. This field should be read as '1'
25631 * to indicate that the output has been completely written.
25632 * When writing a command completion or response to an internal processor,
25633 * the order of writes has to be such that this field is written last.
25638 /****************************
25639 * hwrm_port_phy_mdio_write *
25640 ****************************/
25643 /* hwrm_port_phy_mdio_write_input (size:320b/40B) */
25644 struct hwrm_port_phy_mdio_write_input {
25645 /* The HWRM command request type. */
25648 * The completion ring to send the completion event on. This should
25649 * be the NQ ID returned from the `nq_alloc` HWRM command.
25651 uint16_t cmpl_ring;
25653 * The sequence ID is used by the driver for tracking multiple
25654 * commands. This ID is treated as opaque data by the firmware and
25655 * the value is returned in the `hwrm_resp_hdr` upon completion.
25659 * The target ID of the command:
25660 * * 0x0-0xFFF8 - The function ID
25661 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
25662 * * 0xFFFD - Reserved for user-space HWRM interface
25665 uint16_t target_id;
25667 * A physical address pointer pointing to a host buffer that the
25668 * command's response data will be written. This can be either a host
25669 * physical address (HPA) or a guest physical address (GPA) and must
25670 * point to a physically contiguous block of memory.
25672 uint64_t resp_addr;
25673 /* Reserved for future use. */
25674 uint32_t unused_0[2];
25675 /* Port ID of port. */
25677 /* If phy_address is 0xFF, port_id will be used to derive phy_addr. */
25679 /* 8-bit device address. */
25681 /* 16-bit register address. */
25683 /* 16-bit register data. */
25686 * When this bit is set to 1 a Clause 45 mdio access is done.
25687 * when this bit is set to 0 a Clause 22 mdio access is done.
25691 uint8_t unused_1[7];
25694 /* hwrm_port_phy_mdio_write_output (size:128b/16B) */
25695 struct hwrm_port_phy_mdio_write_output {
25696 /* The specific error status for the command. */
25697 uint16_t error_code;
25698 /* The HWRM command request type. */
25700 /* The sequence ID from the original command. */
25702 /* The length of the response data in number of bytes. */
25704 uint8_t unused_0[7];
25706 * This field is used in Output records to indicate that the output
25707 * is completely written to RAM. This field should be read as '1'
25708 * to indicate that the output has been completely written.
25709 * When writing a command completion or response to an internal processor,
25710 * the order of writes has to be such that this field is written last.
25715 /***************************
25716 * hwrm_port_phy_mdio_read *
25717 ***************************/
25720 /* hwrm_port_phy_mdio_read_input (size:256b/32B) */
25721 struct hwrm_port_phy_mdio_read_input {
25722 /* The HWRM command request type. */
25725 * The completion ring to send the completion event on. This should
25726 * be the NQ ID returned from the `nq_alloc` HWRM command.
25728 uint16_t cmpl_ring;
25730 * The sequence ID is used by the driver for tracking multiple
25731 * commands. This ID is treated as opaque data by the firmware and
25732 * the value is returned in the `hwrm_resp_hdr` upon completion.
25736 * The target ID of the command:
25737 * * 0x0-0xFFF8 - The function ID
25738 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
25739 * * 0xFFFD - Reserved for user-space HWRM interface
25742 uint16_t target_id;
25744 * A physical address pointer pointing to a host buffer that the
25745 * command's response data will be written. This can be either a host
25746 * physical address (HPA) or a guest physical address (GPA) and must
25747 * point to a physically contiguous block of memory.
25749 uint64_t resp_addr;
25750 /* Reserved for future use. */
25751 uint32_t unused_0[2];
25752 /* Port ID of port. */
25754 /* If phy_address is 0xFF, port_id will be used to derive phy_addr. */
25756 /* 8-bit device address. */
25758 /* 16-bit register address. */
25761 * When this bit is set to 1 a Clause 45 mdio access is done.
25762 * when this bit is set to 0 a Clause 22 mdio access is done.
25769 /* hwrm_port_phy_mdio_read_output (size:128b/16B) */
25770 struct hwrm_port_phy_mdio_read_output {
25771 /* The specific error status for the command. */
25772 uint16_t error_code;
25773 /* The HWRM command request type. */
25775 /* The sequence ID from the original command. */
25777 /* The length of the response data in number of bytes. */
25779 /* 16-bit register data. */
25781 uint8_t unused_0[5];
25783 * This field is used in Output records to indicate that the output
25784 * is completely written to RAM. This field should be read as '1'
25785 * to indicate that the output has been completely written.
25786 * When writing a command completion or response to an internal processor,
25787 * the order of writes has to be such that this field is written last.
25792 /*********************
25793 * hwrm_port_led_cfg *
25794 *********************/
25797 /* hwrm_port_led_cfg_input (size:512b/64B) */
25798 struct hwrm_port_led_cfg_input {
25799 /* The HWRM command request type. */
25802 * The completion ring to send the completion event on. This should
25803 * be the NQ ID returned from the `nq_alloc` HWRM command.
25805 uint16_t cmpl_ring;
25807 * The sequence ID is used by the driver for tracking multiple
25808 * commands. This ID is treated as opaque data by the firmware and
25809 * the value is returned in the `hwrm_resp_hdr` upon completion.
25813 * The target ID of the command:
25814 * * 0x0-0xFFF8 - The function ID
25815 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
25816 * * 0xFFFD - Reserved for user-space HWRM interface
25819 uint16_t target_id;
25821 * A physical address pointer pointing to a host buffer that the
25822 * command's response data will be written. This can be either a host
25823 * physical address (HPA) or a guest physical address (GPA) and must
25824 * point to a physically contiguous block of memory.
25826 uint64_t resp_addr;
25829 * This bit must be '1' for the led0_id field to be
25832 #define HWRM_PORT_LED_CFG_INPUT_ENABLES_LED0_ID \
25835 * This bit must be '1' for the led0_state field to be
25838 #define HWRM_PORT_LED_CFG_INPUT_ENABLES_LED0_STATE \
25841 * This bit must be '1' for the led0_color field to be
25844 #define HWRM_PORT_LED_CFG_INPUT_ENABLES_LED0_COLOR \
25847 * This bit must be '1' for the led0_blink_on field to be
25850 #define HWRM_PORT_LED_CFG_INPUT_ENABLES_LED0_BLINK_ON \
25853 * This bit must be '1' for the led0_blink_off field to be
25856 #define HWRM_PORT_LED_CFG_INPUT_ENABLES_LED0_BLINK_OFF \
25859 * This bit must be '1' for the led0_group_id field to be
25862 #define HWRM_PORT_LED_CFG_INPUT_ENABLES_LED0_GROUP_ID \
25865 * This bit must be '1' for the led1_id field to be
25868 #define HWRM_PORT_LED_CFG_INPUT_ENABLES_LED1_ID \
25871 * This bit must be '1' for the led1_state field to be
25874 #define HWRM_PORT_LED_CFG_INPUT_ENABLES_LED1_STATE \
25877 * This bit must be '1' for the led1_color field to be
25880 #define HWRM_PORT_LED_CFG_INPUT_ENABLES_LED1_COLOR \
25883 * This bit must be '1' for the led1_blink_on field to be
25886 #define HWRM_PORT_LED_CFG_INPUT_ENABLES_LED1_BLINK_ON \
25889 * This bit must be '1' for the led1_blink_off field to be
25892 #define HWRM_PORT_LED_CFG_INPUT_ENABLES_LED1_BLINK_OFF \
25895 * This bit must be '1' for the led1_group_id field to be
25898 #define HWRM_PORT_LED_CFG_INPUT_ENABLES_LED1_GROUP_ID \
25901 * This bit must be '1' for the led2_id field to be
25904 #define HWRM_PORT_LED_CFG_INPUT_ENABLES_LED2_ID \
25907 * This bit must be '1' for the led2_state field to be
25910 #define HWRM_PORT_LED_CFG_INPUT_ENABLES_LED2_STATE \
25913 * This bit must be '1' for the led2_color field to be
25916 #define HWRM_PORT_LED_CFG_INPUT_ENABLES_LED2_COLOR \
25919 * This bit must be '1' for the led2_blink_on field to be
25922 #define HWRM_PORT_LED_CFG_INPUT_ENABLES_LED2_BLINK_ON \
25925 * This bit must be '1' for the led2_blink_off field to be
25928 #define HWRM_PORT_LED_CFG_INPUT_ENABLES_LED2_BLINK_OFF \
25931 * This bit must be '1' for the led2_group_id field to be
25934 #define HWRM_PORT_LED_CFG_INPUT_ENABLES_LED2_GROUP_ID \
25937 * This bit must be '1' for the led3_id field to be
25940 #define HWRM_PORT_LED_CFG_INPUT_ENABLES_LED3_ID \
25943 * This bit must be '1' for the led3_state field to be
25946 #define HWRM_PORT_LED_CFG_INPUT_ENABLES_LED3_STATE \
25949 * This bit must be '1' for the led3_color field to be
25952 #define HWRM_PORT_LED_CFG_INPUT_ENABLES_LED3_COLOR \
25955 * This bit must be '1' for the led3_blink_on field to be
25958 #define HWRM_PORT_LED_CFG_INPUT_ENABLES_LED3_BLINK_ON \
25961 * This bit must be '1' for the led3_blink_off field to be
25964 #define HWRM_PORT_LED_CFG_INPUT_ENABLES_LED3_BLINK_OFF \
25967 * This bit must be '1' for the led3_group_id field to be
25970 #define HWRM_PORT_LED_CFG_INPUT_ENABLES_LED3_GROUP_ID \
25972 /* Port ID of port whose LEDs are configured. */
25975 * The number of LEDs that are being configured.
25976 * Up to 4 LEDs can be configured with this command.
25979 /* Reserved field. */
25981 /* An identifier for the LED #0. */
25983 /* The requested state of the LED #0. */
25984 uint8_t led0_state;
25985 /* Default state of the LED */
25986 #define HWRM_PORT_LED_CFG_INPUT_LED0_STATE_DEFAULT UINT32_C(0x0)
25988 #define HWRM_PORT_LED_CFG_INPUT_LED0_STATE_OFF UINT32_C(0x1)
25990 #define HWRM_PORT_LED_CFG_INPUT_LED0_STATE_ON UINT32_C(0x2)
25992 #define HWRM_PORT_LED_CFG_INPUT_LED0_STATE_BLINK UINT32_C(0x3)
25993 /* Blink Alternately */
25994 #define HWRM_PORT_LED_CFG_INPUT_LED0_STATE_BLINKALT UINT32_C(0x4)
25995 #define HWRM_PORT_LED_CFG_INPUT_LED0_STATE_LAST \
25996 HWRM_PORT_LED_CFG_INPUT_LED0_STATE_BLINKALT
25997 /* The requested color of LED #0. */
25998 uint8_t led0_color;
26000 #define HWRM_PORT_LED_CFG_INPUT_LED0_COLOR_DEFAULT UINT32_C(0x0)
26002 #define HWRM_PORT_LED_CFG_INPUT_LED0_COLOR_AMBER UINT32_C(0x1)
26004 #define HWRM_PORT_LED_CFG_INPUT_LED0_COLOR_GREEN UINT32_C(0x2)
26005 /* Green or Amber */
26006 #define HWRM_PORT_LED_CFG_INPUT_LED0_COLOR_GREENAMBER UINT32_C(0x3)
26007 #define HWRM_PORT_LED_CFG_INPUT_LED0_COLOR_LAST \
26008 HWRM_PORT_LED_CFG_INPUT_LED0_COLOR_GREENAMBER
26011 * If the LED #0 state is "blink" or "blinkalt", then
26012 * this field represents the requested time in milliseconds
26013 * to keep LED on between cycles.
26015 uint16_t led0_blink_on;
26017 * If the LED #0 state is "blink" or "blinkalt", then
26018 * this field represents the requested time in milliseconds
26019 * to keep LED off between cycles.
26021 uint16_t led0_blink_off;
26023 * An identifier for the group of LEDs that LED #0 belongs
26025 * If set to 0, then the LED #0 shall not be grouped and
26026 * shall be treated as an individual resource.
26027 * For all other non-zero values of this field, LED #0 shall
26028 * be grouped together with the LEDs with the same group ID
26031 uint8_t led0_group_id;
26032 /* Reserved field. */
26034 /* An identifier for the LED #1. */
26036 /* The requested state of the LED #1. */
26037 uint8_t led1_state;
26038 /* Default state of the LED */
26039 #define HWRM_PORT_LED_CFG_INPUT_LED1_STATE_DEFAULT UINT32_C(0x0)
26041 #define HWRM_PORT_LED_CFG_INPUT_LED1_STATE_OFF UINT32_C(0x1)
26043 #define HWRM_PORT_LED_CFG_INPUT_LED1_STATE_ON UINT32_C(0x2)
26045 #define HWRM_PORT_LED_CFG_INPUT_LED1_STATE_BLINK UINT32_C(0x3)
26046 /* Blink Alternately */
26047 #define HWRM_PORT_LED_CFG_INPUT_LED1_STATE_BLINKALT UINT32_C(0x4)
26048 #define HWRM_PORT_LED_CFG_INPUT_LED1_STATE_LAST \
26049 HWRM_PORT_LED_CFG_INPUT_LED1_STATE_BLINKALT
26050 /* The requested color of LED #1. */
26051 uint8_t led1_color;
26053 #define HWRM_PORT_LED_CFG_INPUT_LED1_COLOR_DEFAULT UINT32_C(0x0)
26055 #define HWRM_PORT_LED_CFG_INPUT_LED1_COLOR_AMBER UINT32_C(0x1)
26057 #define HWRM_PORT_LED_CFG_INPUT_LED1_COLOR_GREEN UINT32_C(0x2)
26058 /* Green or Amber */
26059 #define HWRM_PORT_LED_CFG_INPUT_LED1_COLOR_GREENAMBER UINT32_C(0x3)
26060 #define HWRM_PORT_LED_CFG_INPUT_LED1_COLOR_LAST \
26061 HWRM_PORT_LED_CFG_INPUT_LED1_COLOR_GREENAMBER
26064 * If the LED #1 state is "blink" or "blinkalt", then
26065 * this field represents the requested time in milliseconds
26066 * to keep LED on between cycles.
26068 uint16_t led1_blink_on;
26070 * If the LED #1 state is "blink" or "blinkalt", then
26071 * this field represents the requested time in milliseconds
26072 * to keep LED off between cycles.
26074 uint16_t led1_blink_off;
26076 * An identifier for the group of LEDs that LED #1 belongs
26078 * If set to 0, then the LED #1 shall not be grouped and
26079 * shall be treated as an individual resource.
26080 * For all other non-zero values of this field, LED #1 shall
26081 * be grouped together with the LEDs with the same group ID
26084 uint8_t led1_group_id;
26085 /* Reserved field. */
26087 /* An identifier for the LED #2. */
26089 /* The requested state of the LED #2. */
26090 uint8_t led2_state;
26091 /* Default state of the LED */
26092 #define HWRM_PORT_LED_CFG_INPUT_LED2_STATE_DEFAULT UINT32_C(0x0)
26094 #define HWRM_PORT_LED_CFG_INPUT_LED2_STATE_OFF UINT32_C(0x1)
26096 #define HWRM_PORT_LED_CFG_INPUT_LED2_STATE_ON UINT32_C(0x2)
26098 #define HWRM_PORT_LED_CFG_INPUT_LED2_STATE_BLINK UINT32_C(0x3)
26099 /* Blink Alternately */
26100 #define HWRM_PORT_LED_CFG_INPUT_LED2_STATE_BLINKALT UINT32_C(0x4)
26101 #define HWRM_PORT_LED_CFG_INPUT_LED2_STATE_LAST \
26102 HWRM_PORT_LED_CFG_INPUT_LED2_STATE_BLINKALT
26103 /* The requested color of LED #2. */
26104 uint8_t led2_color;
26106 #define HWRM_PORT_LED_CFG_INPUT_LED2_COLOR_DEFAULT UINT32_C(0x0)
26108 #define HWRM_PORT_LED_CFG_INPUT_LED2_COLOR_AMBER UINT32_C(0x1)
26110 #define HWRM_PORT_LED_CFG_INPUT_LED2_COLOR_GREEN UINT32_C(0x2)
26111 /* Green or Amber */
26112 #define HWRM_PORT_LED_CFG_INPUT_LED2_COLOR_GREENAMBER UINT32_C(0x3)
26113 #define HWRM_PORT_LED_CFG_INPUT_LED2_COLOR_LAST \
26114 HWRM_PORT_LED_CFG_INPUT_LED2_COLOR_GREENAMBER
26117 * If the LED #2 state is "blink" or "blinkalt", then
26118 * this field represents the requested time in milliseconds
26119 * to keep LED on between cycles.
26121 uint16_t led2_blink_on;
26123 * If the LED #2 state is "blink" or "blinkalt", then
26124 * this field represents the requested time in milliseconds
26125 * to keep LED off between cycles.
26127 uint16_t led2_blink_off;
26129 * An identifier for the group of LEDs that LED #2 belongs
26131 * If set to 0, then the LED #2 shall not be grouped and
26132 * shall be treated as an individual resource.
26133 * For all other non-zero values of this field, LED #2 shall
26134 * be grouped together with the LEDs with the same group ID
26137 uint8_t led2_group_id;
26138 /* Reserved field. */
26140 /* An identifier for the LED #3. */
26142 /* The requested state of the LED #3. */
26143 uint8_t led3_state;
26144 /* Default state of the LED */
26145 #define HWRM_PORT_LED_CFG_INPUT_LED3_STATE_DEFAULT UINT32_C(0x0)
26147 #define HWRM_PORT_LED_CFG_INPUT_LED3_STATE_OFF UINT32_C(0x1)
26149 #define HWRM_PORT_LED_CFG_INPUT_LED3_STATE_ON UINT32_C(0x2)
26151 #define HWRM_PORT_LED_CFG_INPUT_LED3_STATE_BLINK UINT32_C(0x3)
26152 /* Blink Alternately */
26153 #define HWRM_PORT_LED_CFG_INPUT_LED3_STATE_BLINKALT UINT32_C(0x4)
26154 #define HWRM_PORT_LED_CFG_INPUT_LED3_STATE_LAST \
26155 HWRM_PORT_LED_CFG_INPUT_LED3_STATE_BLINKALT
26156 /* The requested color of LED #3. */
26157 uint8_t led3_color;
26159 #define HWRM_PORT_LED_CFG_INPUT_LED3_COLOR_DEFAULT UINT32_C(0x0)
26161 #define HWRM_PORT_LED_CFG_INPUT_LED3_COLOR_AMBER UINT32_C(0x1)
26163 #define HWRM_PORT_LED_CFG_INPUT_LED3_COLOR_GREEN UINT32_C(0x2)
26164 /* Green or Amber */
26165 #define HWRM_PORT_LED_CFG_INPUT_LED3_COLOR_GREENAMBER UINT32_C(0x3)
26166 #define HWRM_PORT_LED_CFG_INPUT_LED3_COLOR_LAST \
26167 HWRM_PORT_LED_CFG_INPUT_LED3_COLOR_GREENAMBER
26170 * If the LED #3 state is "blink" or "blinkalt", then
26171 * this field represents the requested time in milliseconds
26172 * to keep LED on between cycles.
26174 uint16_t led3_blink_on;
26176 * If the LED #3 state is "blink" or "blinkalt", then
26177 * this field represents the requested time in milliseconds
26178 * to keep LED off between cycles.
26180 uint16_t led3_blink_off;
26182 * An identifier for the group of LEDs that LED #3 belongs
26184 * If set to 0, then the LED #3 shall not be grouped and
26185 * shall be treated as an individual resource.
26186 * For all other non-zero values of this field, LED #3 shall
26187 * be grouped together with the LEDs with the same group ID
26190 uint8_t led3_group_id;
26191 /* Reserved field. */
26195 /* hwrm_port_led_cfg_output (size:128b/16B) */
26196 struct hwrm_port_led_cfg_output {
26197 /* The specific error status for the command. */
26198 uint16_t error_code;
26199 /* The HWRM command request type. */
26201 /* The sequence ID from the original command. */
26203 /* The length of the response data in number of bytes. */
26205 uint8_t unused_0[7];
26207 * This field is used in Output records to indicate that the output
26208 * is completely written to RAM. This field should be read as '1'
26209 * to indicate that the output has been completely written.
26210 * When writing a command completion or response to an internal processor,
26211 * the order of writes has to be such that this field is written last.
26216 /**********************
26217 * hwrm_port_led_qcfg *
26218 **********************/
26221 /* hwrm_port_led_qcfg_input (size:192b/24B) */
26222 struct hwrm_port_led_qcfg_input {
26223 /* The HWRM command request type. */
26226 * The completion ring to send the completion event on. This should
26227 * be the NQ ID returned from the `nq_alloc` HWRM command.
26229 uint16_t cmpl_ring;
26231 * The sequence ID is used by the driver for tracking multiple
26232 * commands. This ID is treated as opaque data by the firmware and
26233 * the value is returned in the `hwrm_resp_hdr` upon completion.
26237 * The target ID of the command:
26238 * * 0x0-0xFFF8 - The function ID
26239 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
26240 * * 0xFFFD - Reserved for user-space HWRM interface
26243 uint16_t target_id;
26245 * A physical address pointer pointing to a host buffer that the
26246 * command's response data will be written. This can be either a host
26247 * physical address (HPA) or a guest physical address (GPA) and must
26248 * point to a physically contiguous block of memory.
26250 uint64_t resp_addr;
26251 /* Port ID of port whose LED configuration is being queried. */
26253 uint8_t unused_0[6];
26256 /* hwrm_port_led_qcfg_output (size:448b/56B) */
26257 struct hwrm_port_led_qcfg_output {
26258 /* The specific error status for the command. */
26259 uint16_t error_code;
26260 /* The HWRM command request type. */
26262 /* The sequence ID from the original command. */
26264 /* The length of the response data in number of bytes. */
26267 * The number of LEDs that are configured on this port.
26268 * Up to 4 LEDs can be returned in the response.
26271 /* An identifier for the LED #0. */
26273 /* The type of LED #0. */
26276 #define HWRM_PORT_LED_QCFG_OUTPUT_LED0_TYPE_SPEED UINT32_C(0x0)
26278 #define HWRM_PORT_LED_QCFG_OUTPUT_LED0_TYPE_ACTIVITY UINT32_C(0x1)
26280 #define HWRM_PORT_LED_QCFG_OUTPUT_LED0_TYPE_INVALID UINT32_C(0xff)
26281 #define HWRM_PORT_LED_QCFG_OUTPUT_LED0_TYPE_LAST \
26282 HWRM_PORT_LED_QCFG_OUTPUT_LED0_TYPE_INVALID
26283 /* The current state of the LED #0. */
26284 uint8_t led0_state;
26285 /* Default state of the LED */
26286 #define HWRM_PORT_LED_QCFG_OUTPUT_LED0_STATE_DEFAULT UINT32_C(0x0)
26288 #define HWRM_PORT_LED_QCFG_OUTPUT_LED0_STATE_OFF UINT32_C(0x1)
26290 #define HWRM_PORT_LED_QCFG_OUTPUT_LED0_STATE_ON UINT32_C(0x2)
26292 #define HWRM_PORT_LED_QCFG_OUTPUT_LED0_STATE_BLINK UINT32_C(0x3)
26293 /* Blink Alternately */
26294 #define HWRM_PORT_LED_QCFG_OUTPUT_LED0_STATE_BLINKALT UINT32_C(0x4)
26295 #define HWRM_PORT_LED_QCFG_OUTPUT_LED0_STATE_LAST \
26296 HWRM_PORT_LED_QCFG_OUTPUT_LED0_STATE_BLINKALT
26297 /* The color of LED #0. */
26298 uint8_t led0_color;
26300 #define HWRM_PORT_LED_QCFG_OUTPUT_LED0_COLOR_DEFAULT UINT32_C(0x0)
26302 #define HWRM_PORT_LED_QCFG_OUTPUT_LED0_COLOR_AMBER UINT32_C(0x1)
26304 #define HWRM_PORT_LED_QCFG_OUTPUT_LED0_COLOR_GREEN UINT32_C(0x2)
26305 /* Green or Amber */
26306 #define HWRM_PORT_LED_QCFG_OUTPUT_LED0_COLOR_GREENAMBER UINT32_C(0x3)
26307 #define HWRM_PORT_LED_QCFG_OUTPUT_LED0_COLOR_LAST \
26308 HWRM_PORT_LED_QCFG_OUTPUT_LED0_COLOR_GREENAMBER
26311 * If the LED #0 state is "blink" or "blinkalt", then
26312 * this field represents the requested time in milliseconds
26313 * to keep LED on between cycles.
26315 uint16_t led0_blink_on;
26317 * If the LED #0 state is "blink" or "blinkalt", then
26318 * this field represents the requested time in milliseconds
26319 * to keep LED off between cycles.
26321 uint16_t led0_blink_off;
26323 * An identifier for the group of LEDs that LED #0 belongs
26325 * If set to 0, then the LED #0 is not grouped.
26326 * For all other non-zero values of this field, LED #0 is
26327 * grouped together with the LEDs with the same group ID
26330 uint8_t led0_group_id;
26331 /* An identifier for the LED #1. */
26333 /* The type of LED #1. */
26336 #define HWRM_PORT_LED_QCFG_OUTPUT_LED1_TYPE_SPEED UINT32_C(0x0)
26338 #define HWRM_PORT_LED_QCFG_OUTPUT_LED1_TYPE_ACTIVITY UINT32_C(0x1)
26340 #define HWRM_PORT_LED_QCFG_OUTPUT_LED1_TYPE_INVALID UINT32_C(0xff)
26341 #define HWRM_PORT_LED_QCFG_OUTPUT_LED1_TYPE_LAST \
26342 HWRM_PORT_LED_QCFG_OUTPUT_LED1_TYPE_INVALID
26343 /* The current state of the LED #1. */
26344 uint8_t led1_state;
26345 /* Default state of the LED */
26346 #define HWRM_PORT_LED_QCFG_OUTPUT_LED1_STATE_DEFAULT UINT32_C(0x0)
26348 #define HWRM_PORT_LED_QCFG_OUTPUT_LED1_STATE_OFF UINT32_C(0x1)
26350 #define HWRM_PORT_LED_QCFG_OUTPUT_LED1_STATE_ON UINT32_C(0x2)
26352 #define HWRM_PORT_LED_QCFG_OUTPUT_LED1_STATE_BLINK UINT32_C(0x3)
26353 /* Blink Alternately */
26354 #define HWRM_PORT_LED_QCFG_OUTPUT_LED1_STATE_BLINKALT UINT32_C(0x4)
26355 #define HWRM_PORT_LED_QCFG_OUTPUT_LED1_STATE_LAST \
26356 HWRM_PORT_LED_QCFG_OUTPUT_LED1_STATE_BLINKALT
26357 /* The color of LED #1. */
26358 uint8_t led1_color;
26360 #define HWRM_PORT_LED_QCFG_OUTPUT_LED1_COLOR_DEFAULT UINT32_C(0x0)
26362 #define HWRM_PORT_LED_QCFG_OUTPUT_LED1_COLOR_AMBER UINT32_C(0x1)
26364 #define HWRM_PORT_LED_QCFG_OUTPUT_LED1_COLOR_GREEN UINT32_C(0x2)
26365 /* Green or Amber */
26366 #define HWRM_PORT_LED_QCFG_OUTPUT_LED1_COLOR_GREENAMBER UINT32_C(0x3)
26367 #define HWRM_PORT_LED_QCFG_OUTPUT_LED1_COLOR_LAST \
26368 HWRM_PORT_LED_QCFG_OUTPUT_LED1_COLOR_GREENAMBER
26371 * If the LED #1 state is "blink" or "blinkalt", then
26372 * this field represents the requested time in milliseconds
26373 * to keep LED on between cycles.
26375 uint16_t led1_blink_on;
26377 * If the LED #1 state is "blink" or "blinkalt", then
26378 * this field represents the requested time in milliseconds
26379 * to keep LED off between cycles.
26381 uint16_t led1_blink_off;
26383 * An identifier for the group of LEDs that LED #1 belongs
26385 * If set to 0, then the LED #1 is not grouped.
26386 * For all other non-zero values of this field, LED #1 is
26387 * grouped together with the LEDs with the same group ID
26390 uint8_t led1_group_id;
26391 /* An identifier for the LED #2. */
26393 /* The type of LED #2. */
26396 #define HWRM_PORT_LED_QCFG_OUTPUT_LED2_TYPE_SPEED UINT32_C(0x0)
26398 #define HWRM_PORT_LED_QCFG_OUTPUT_LED2_TYPE_ACTIVITY UINT32_C(0x1)
26400 #define HWRM_PORT_LED_QCFG_OUTPUT_LED2_TYPE_INVALID UINT32_C(0xff)
26401 #define HWRM_PORT_LED_QCFG_OUTPUT_LED2_TYPE_LAST \
26402 HWRM_PORT_LED_QCFG_OUTPUT_LED2_TYPE_INVALID
26403 /* The current state of the LED #2. */
26404 uint8_t led2_state;
26405 /* Default state of the LED */
26406 #define HWRM_PORT_LED_QCFG_OUTPUT_LED2_STATE_DEFAULT UINT32_C(0x0)
26408 #define HWRM_PORT_LED_QCFG_OUTPUT_LED2_STATE_OFF UINT32_C(0x1)
26410 #define HWRM_PORT_LED_QCFG_OUTPUT_LED2_STATE_ON UINT32_C(0x2)
26412 #define HWRM_PORT_LED_QCFG_OUTPUT_LED2_STATE_BLINK UINT32_C(0x3)
26413 /* Blink Alternately */
26414 #define HWRM_PORT_LED_QCFG_OUTPUT_LED2_STATE_BLINKALT UINT32_C(0x4)
26415 #define HWRM_PORT_LED_QCFG_OUTPUT_LED2_STATE_LAST \
26416 HWRM_PORT_LED_QCFG_OUTPUT_LED2_STATE_BLINKALT
26417 /* The color of LED #2. */
26418 uint8_t led2_color;
26420 #define HWRM_PORT_LED_QCFG_OUTPUT_LED2_COLOR_DEFAULT UINT32_C(0x0)
26422 #define HWRM_PORT_LED_QCFG_OUTPUT_LED2_COLOR_AMBER UINT32_C(0x1)
26424 #define HWRM_PORT_LED_QCFG_OUTPUT_LED2_COLOR_GREEN UINT32_C(0x2)
26425 /* Green or Amber */
26426 #define HWRM_PORT_LED_QCFG_OUTPUT_LED2_COLOR_GREENAMBER UINT32_C(0x3)
26427 #define HWRM_PORT_LED_QCFG_OUTPUT_LED2_COLOR_LAST \
26428 HWRM_PORT_LED_QCFG_OUTPUT_LED2_COLOR_GREENAMBER
26431 * If the LED #2 state is "blink" or "blinkalt", then
26432 * this field represents the requested time in milliseconds
26433 * to keep LED on between cycles.
26435 uint16_t led2_blink_on;
26437 * If the LED #2 state is "blink" or "blinkalt", then
26438 * this field represents the requested time in milliseconds
26439 * to keep LED off between cycles.
26441 uint16_t led2_blink_off;
26443 * An identifier for the group of LEDs that LED #2 belongs
26445 * If set to 0, then the LED #2 is not grouped.
26446 * For all other non-zero values of this field, LED #2 is
26447 * grouped together with the LEDs with the same group ID
26450 uint8_t led2_group_id;
26451 /* An identifier for the LED #3. */
26453 /* The type of LED #3. */
26456 #define HWRM_PORT_LED_QCFG_OUTPUT_LED3_TYPE_SPEED UINT32_C(0x0)
26458 #define HWRM_PORT_LED_QCFG_OUTPUT_LED3_TYPE_ACTIVITY UINT32_C(0x1)
26460 #define HWRM_PORT_LED_QCFG_OUTPUT_LED3_TYPE_INVALID UINT32_C(0xff)
26461 #define HWRM_PORT_LED_QCFG_OUTPUT_LED3_TYPE_LAST \
26462 HWRM_PORT_LED_QCFG_OUTPUT_LED3_TYPE_INVALID
26463 /* The current state of the LED #3. */
26464 uint8_t led3_state;
26465 /* Default state of the LED */
26466 #define HWRM_PORT_LED_QCFG_OUTPUT_LED3_STATE_DEFAULT UINT32_C(0x0)
26468 #define HWRM_PORT_LED_QCFG_OUTPUT_LED3_STATE_OFF UINT32_C(0x1)
26470 #define HWRM_PORT_LED_QCFG_OUTPUT_LED3_STATE_ON UINT32_C(0x2)
26472 #define HWRM_PORT_LED_QCFG_OUTPUT_LED3_STATE_BLINK UINT32_C(0x3)
26473 /* Blink Alternately */
26474 #define HWRM_PORT_LED_QCFG_OUTPUT_LED3_STATE_BLINKALT UINT32_C(0x4)
26475 #define HWRM_PORT_LED_QCFG_OUTPUT_LED3_STATE_LAST \
26476 HWRM_PORT_LED_QCFG_OUTPUT_LED3_STATE_BLINKALT
26477 /* The color of LED #3. */
26478 uint8_t led3_color;
26480 #define HWRM_PORT_LED_QCFG_OUTPUT_LED3_COLOR_DEFAULT UINT32_C(0x0)
26482 #define HWRM_PORT_LED_QCFG_OUTPUT_LED3_COLOR_AMBER UINT32_C(0x1)
26484 #define HWRM_PORT_LED_QCFG_OUTPUT_LED3_COLOR_GREEN UINT32_C(0x2)
26485 /* Green or Amber */
26486 #define HWRM_PORT_LED_QCFG_OUTPUT_LED3_COLOR_GREENAMBER UINT32_C(0x3)
26487 #define HWRM_PORT_LED_QCFG_OUTPUT_LED3_COLOR_LAST \
26488 HWRM_PORT_LED_QCFG_OUTPUT_LED3_COLOR_GREENAMBER
26491 * If the LED #3 state is "blink" or "blinkalt", then
26492 * this field represents the requested time in milliseconds
26493 * to keep LED on between cycles.
26495 uint16_t led3_blink_on;
26497 * If the LED #3 state is "blink" or "blinkalt", then
26498 * this field represents the requested time in milliseconds
26499 * to keep LED off between cycles.
26501 uint16_t led3_blink_off;
26503 * An identifier for the group of LEDs that LED #3 belongs
26505 * If set to 0, then the LED #3 is not grouped.
26506 * For all other non-zero values of this field, LED #3 is
26507 * grouped together with the LEDs with the same group ID
26510 uint8_t led3_group_id;
26511 uint8_t unused_4[6];
26513 * This field is used in Output records to indicate that the output
26514 * is completely written to RAM. This field should be read as '1'
26515 * to indicate that the output has been completely written.
26516 * When writing a command completion or response to an internal processor,
26517 * the order of writes has to be such that this field is written last.
26522 /***********************
26523 * hwrm_port_led_qcaps *
26524 ***********************/
26527 /* hwrm_port_led_qcaps_input (size:192b/24B) */
26528 struct hwrm_port_led_qcaps_input {
26529 /* The HWRM command request type. */
26532 * The completion ring to send the completion event on. This should
26533 * be the NQ ID returned from the `nq_alloc` HWRM command.
26535 uint16_t cmpl_ring;
26537 * The sequence ID is used by the driver for tracking multiple
26538 * commands. This ID is treated as opaque data by the firmware and
26539 * the value is returned in the `hwrm_resp_hdr` upon completion.
26543 * The target ID of the command:
26544 * * 0x0-0xFFF8 - The function ID
26545 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
26546 * * 0xFFFD - Reserved for user-space HWRM interface
26549 uint16_t target_id;
26551 * A physical address pointer pointing to a host buffer that the
26552 * command's response data will be written. This can be either a host
26553 * physical address (HPA) or a guest physical address (GPA) and must
26554 * point to a physically contiguous block of memory.
26556 uint64_t resp_addr;
26557 /* Port ID of port whose LED configuration is being queried. */
26559 uint8_t unused_0[6];
26562 /* hwrm_port_led_qcaps_output (size:384b/48B) */
26563 struct hwrm_port_led_qcaps_output {
26564 /* The specific error status for the command. */
26565 uint16_t error_code;
26566 /* The HWRM command request type. */
26568 /* The sequence ID from the original command. */
26570 /* The length of the response data in number of bytes. */
26573 * The number of LEDs that are configured on this port.
26574 * Up to 4 LEDs can be returned in the response.
26577 /* Reserved for future use. */
26579 /* An identifier for the LED #0. */
26581 /* The type of LED #0. */
26584 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED0_TYPE_SPEED UINT32_C(0x0)
26586 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED0_TYPE_ACTIVITY UINT32_C(0x1)
26588 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED0_TYPE_INVALID UINT32_C(0xff)
26589 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED0_TYPE_LAST \
26590 HWRM_PORT_LED_QCAPS_OUTPUT_LED0_TYPE_INVALID
26592 * An identifier for the group of LEDs that LED #0 belongs
26594 * If set to 0, then the LED #0 cannot be grouped.
26595 * For all other non-zero values of this field, LED #0 is
26596 * grouped together with the LEDs with the same group ID
26599 uint8_t led0_group_id;
26601 /* The states supported by LED #0. */
26602 uint16_t led0_state_caps;
26604 * If set to 1, this LED is enabled.
26605 * If set to 0, this LED is disabled.
26607 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED0_STATE_CAPS_ENABLED \
26610 * If set to 1, off state is supported on this LED.
26611 * If set to 0, off state is not supported on this LED.
26613 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED0_STATE_CAPS_OFF_SUPPORTED \
26616 * If set to 1, on state is supported on this LED.
26617 * If set to 0, on state is not supported on this LED.
26619 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED0_STATE_CAPS_ON_SUPPORTED \
26622 * If set to 1, blink state is supported on this LED.
26623 * If set to 0, blink state is not supported on this LED.
26625 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED0_STATE_CAPS_BLINK_SUPPORTED \
26628 * If set to 1, blink_alt state is supported on this LED.
26629 * If set to 0, blink_alt state is not supported on this LED.
26631 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED0_STATE_CAPS_BLINK_ALT_SUPPORTED \
26633 /* The colors supported by LED #0. */
26634 uint16_t led0_color_caps;
26636 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED0_COLOR_CAPS_RSVD \
26639 * If set to 1, Amber color is supported on this LED.
26640 * If set to 0, Amber color is not supported on this LED.
26642 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED0_COLOR_CAPS_AMBER_SUPPORTED \
26645 * If set to 1, Green color is supported on this LED.
26646 * If set to 0, Green color is not supported on this LED.
26648 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED0_COLOR_CAPS_GREEN_SUPPORTED \
26650 /* An identifier for the LED #1. */
26652 /* The type of LED #1. */
26655 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED1_TYPE_SPEED UINT32_C(0x0)
26657 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED1_TYPE_ACTIVITY UINT32_C(0x1)
26659 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED1_TYPE_INVALID UINT32_C(0xff)
26660 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED1_TYPE_LAST \
26661 HWRM_PORT_LED_QCAPS_OUTPUT_LED1_TYPE_INVALID
26663 * An identifier for the group of LEDs that LED #1 belongs
26665 * If set to 0, then the LED #0 cannot be grouped.
26666 * For all other non-zero values of this field, LED #0 is
26667 * grouped together with the LEDs with the same group ID
26670 uint8_t led1_group_id;
26672 /* The states supported by LED #1. */
26673 uint16_t led1_state_caps;
26675 * If set to 1, this LED is enabled.
26676 * If set to 0, this LED is disabled.
26678 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED1_STATE_CAPS_ENABLED \
26681 * If set to 1, off state is supported on this LED.
26682 * If set to 0, off state is not supported on this LED.
26684 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED1_STATE_CAPS_OFF_SUPPORTED \
26687 * If set to 1, on state is supported on this LED.
26688 * If set to 0, on state is not supported on this LED.
26690 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED1_STATE_CAPS_ON_SUPPORTED \
26693 * If set to 1, blink state is supported on this LED.
26694 * If set to 0, blink state is not supported on this LED.
26696 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED1_STATE_CAPS_BLINK_SUPPORTED \
26699 * If set to 1, blink_alt state is supported on this LED.
26700 * If set to 0, blink_alt state is not supported on this LED.
26702 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED1_STATE_CAPS_BLINK_ALT_SUPPORTED \
26704 /* The colors supported by LED #1. */
26705 uint16_t led1_color_caps;
26707 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED1_COLOR_CAPS_RSVD \
26710 * If set to 1, Amber color is supported on this LED.
26711 * If set to 0, Amber color is not supported on this LED.
26713 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED1_COLOR_CAPS_AMBER_SUPPORTED \
26716 * If set to 1, Green color is supported on this LED.
26717 * If set to 0, Green color is not supported on this LED.
26719 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED1_COLOR_CAPS_GREEN_SUPPORTED \
26721 /* An identifier for the LED #2. */
26723 /* The type of LED #2. */
26726 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED2_TYPE_SPEED UINT32_C(0x0)
26728 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED2_TYPE_ACTIVITY UINT32_C(0x1)
26730 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED2_TYPE_INVALID UINT32_C(0xff)
26731 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED2_TYPE_LAST \
26732 HWRM_PORT_LED_QCAPS_OUTPUT_LED2_TYPE_INVALID
26734 * An identifier for the group of LEDs that LED #0 belongs
26736 * If set to 0, then the LED #0 cannot be grouped.
26737 * For all other non-zero values of this field, LED #0 is
26738 * grouped together with the LEDs with the same group ID
26741 uint8_t led2_group_id;
26743 /* The states supported by LED #2. */
26744 uint16_t led2_state_caps;
26746 * If set to 1, this LED is enabled.
26747 * If set to 0, this LED is disabled.
26749 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED2_STATE_CAPS_ENABLED \
26752 * If set to 1, off state is supported on this LED.
26753 * If set to 0, off state is not supported on this LED.
26755 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED2_STATE_CAPS_OFF_SUPPORTED \
26758 * If set to 1, on state is supported on this LED.
26759 * If set to 0, on state is not supported on this LED.
26761 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED2_STATE_CAPS_ON_SUPPORTED \
26764 * If set to 1, blink state is supported on this LED.
26765 * If set to 0, blink state is not supported on this LED.
26767 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED2_STATE_CAPS_BLINK_SUPPORTED \
26770 * If set to 1, blink_alt state is supported on this LED.
26771 * If set to 0, blink_alt state is not supported on this LED.
26773 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED2_STATE_CAPS_BLINK_ALT_SUPPORTED \
26775 /* The colors supported by LED #2. */
26776 uint16_t led2_color_caps;
26778 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED2_COLOR_CAPS_RSVD \
26781 * If set to 1, Amber color is supported on this LED.
26782 * If set to 0, Amber color is not supported on this LED.
26784 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED2_COLOR_CAPS_AMBER_SUPPORTED \
26787 * If set to 1, Green color is supported on this LED.
26788 * If set to 0, Green color is not supported on this LED.
26790 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED2_COLOR_CAPS_GREEN_SUPPORTED \
26792 /* An identifier for the LED #3. */
26794 /* The type of LED #3. */
26797 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED3_TYPE_SPEED UINT32_C(0x0)
26799 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED3_TYPE_ACTIVITY UINT32_C(0x1)
26801 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED3_TYPE_INVALID UINT32_C(0xff)
26802 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED3_TYPE_LAST \
26803 HWRM_PORT_LED_QCAPS_OUTPUT_LED3_TYPE_INVALID
26805 * An identifier for the group of LEDs that LED #3 belongs
26807 * If set to 0, then the LED #0 cannot be grouped.
26808 * For all other non-zero values of this field, LED #0 is
26809 * grouped together with the LEDs with the same group ID
26812 uint8_t led3_group_id;
26814 /* The states supported by LED #3. */
26815 uint16_t led3_state_caps;
26817 * If set to 1, this LED is enabled.
26818 * If set to 0, this LED is disabled.
26820 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED3_STATE_CAPS_ENABLED \
26823 * If set to 1, off state is supported on this LED.
26824 * If set to 0, off state is not supported on this LED.
26826 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED3_STATE_CAPS_OFF_SUPPORTED \
26829 * If set to 1, on state is supported on this LED.
26830 * If set to 0, on state is not supported on this LED.
26832 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED3_STATE_CAPS_ON_SUPPORTED \
26835 * If set to 1, blink state is supported on this LED.
26836 * If set to 0, blink state is not supported on this LED.
26838 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED3_STATE_CAPS_BLINK_SUPPORTED \
26841 * If set to 1, blink_alt state is supported on this LED.
26842 * If set to 0, blink_alt state is not supported on this LED.
26844 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED3_STATE_CAPS_BLINK_ALT_SUPPORTED \
26846 /* The colors supported by LED #3. */
26847 uint16_t led3_color_caps;
26849 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED3_COLOR_CAPS_RSVD \
26852 * If set to 1, Amber color is supported on this LED.
26853 * If set to 0, Amber color is not supported on this LED.
26855 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED3_COLOR_CAPS_AMBER_SUPPORTED \
26858 * If set to 1, Green color is supported on this LED.
26859 * If set to 0, Green color is not supported on this LED.
26861 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED3_COLOR_CAPS_GREEN_SUPPORTED \
26863 uint8_t unused_4[3];
26865 * This field is used in Output records to indicate that the output
26866 * is completely written to RAM. This field should be read as '1'
26867 * to indicate that the output has been completely written.
26868 * When writing a command completion or response to an internal processor,
26869 * the order of writes has to be such that this field is written last.
26874 /***********************
26875 * hwrm_port_prbs_test *
26876 ***********************/
26879 /* hwrm_port_prbs_test_input (size:384b/48B) */
26880 struct hwrm_port_prbs_test_input {
26881 /* The HWRM command request type. */
26884 * The completion ring to send the completion event on. This should
26885 * be the NQ ID returned from the `nq_alloc` HWRM command.
26887 uint16_t cmpl_ring;
26889 * The sequence ID is used by the driver for tracking multiple
26890 * commands. This ID is treated as opaque data by the firmware and
26891 * the value is returned in the `hwrm_resp_hdr` upon completion.
26895 * The target ID of the command:
26896 * * 0x0-0xFFF8 - The function ID
26897 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
26898 * * 0xFFFD - Reserved for user-space HWRM interface
26901 uint16_t target_id;
26903 * A physical address pointer pointing to a host buffer that the
26904 * command's response data will be written. This can be either a host
26905 * physical address (HPA) or a guest physical address (GPA) and must
26906 * point to a physically contiguous block of memory.
26908 uint64_t resp_addr;
26909 /* Host address data is to DMA'd to. */
26910 uint64_t resp_data_addr;
26912 * Size of the buffer pointed to by resp_data_addr. The firmware may
26913 * use this entire buffer or less than the entire buffer, but never more.
26918 * If set, the port_id field should be interpreted as an internal
26919 * port. The internal port id range is returned in port_phy_qcaps
26920 * response internal_port_cnt field.
26922 #define HWRM_PORT_PRBS_TEST_INPUT_FLAGS_INTERNAL UINT32_C(0x1)
26924 /* Port ID of port where PRBS test to be run. */
26926 /* Polynomial selection for PRBS test. */
26929 #define HWRM_PORT_PRBS_TEST_INPUT_POLY_PRBS7 UINT32_C(0x0)
26931 #define HWRM_PORT_PRBS_TEST_INPUT_POLY_PRBS9 UINT32_C(0x1)
26933 #define HWRM_PORT_PRBS_TEST_INPUT_POLY_PRBS11 UINT32_C(0x2)
26935 #define HWRM_PORT_PRBS_TEST_INPUT_POLY_PRBS15 UINT32_C(0x3)
26937 #define HWRM_PORT_PRBS_TEST_INPUT_POLY_PRBS23 UINT32_C(0x4)
26939 #define HWRM_PORT_PRBS_TEST_INPUT_POLY_PRBS31 UINT32_C(0x5)
26941 #define HWRM_PORT_PRBS_TEST_INPUT_POLY_PRBS58 UINT32_C(0x6)
26943 #define HWRM_PORT_PRBS_TEST_INPUT_POLY_INVALID UINT32_C(0xff)
26944 #define HWRM_PORT_PRBS_TEST_INPUT_POLY_LAST \
26945 HWRM_PORT_PRBS_TEST_INPUT_POLY_INVALID
26947 * Configuration bits for PRBS test.
26948 * Use enable bit to start/stop test.
26949 * Use tx/rx lane map bits to run test on specific lanes,
26950 * if set to 0 test will be run on all lanes.
26952 uint16_t prbs_config;
26954 * Set 0 to stop test currently in progress
26955 * Set 1 to start test with configuration provided.
26957 #define HWRM_PORT_PRBS_TEST_INPUT_PRBS_CONFIG_START_STOP \
26960 * If set to 1, tx_lane_map bitmap should have lane bits set.
26961 * If set to 0, test will be run on all lanes for this port.
26963 #define HWRM_PORT_PRBS_TEST_INPUT_PRBS_CONFIG_TX_LANE_MAP_VALID \
26966 * If set to 1, rx_lane_map bitmap should have lane bits set.
26967 * If set to 0, test will be run on all lanes for this port.
26969 #define HWRM_PORT_PRBS_TEST_INPUT_PRBS_CONFIG_RX_LANE_MAP_VALID \
26971 /* Duration in seconds to run the PRBS test. */
26974 * If tx_lane_map_valid is set to 1, this field is a bitmap
26975 * of tx lanes to run PRBS test. bit0 = lane0,
26976 * bit1 = lane1 ..bit31 = lane31
26978 uint32_t tx_lane_map;
26980 * If rx_lane_map_valid is set to 1, this field is a bitmap
26981 * of rx lanes to run PRBS test. bit0 = lane0,
26982 * bit1 = lane1 ..bit31 = lane31
26984 uint32_t rx_lane_map;
26987 /* hwrm_port_prbs_test_output (size:128b/16B) */
26988 struct hwrm_port_prbs_test_output {
26989 /* The specific error status for the command. */
26990 uint16_t error_code;
26991 /* The HWRM command request type. */
26993 /* The sequence ID from the original command. */
26995 /* The length of the response data in number of bytes. */
26997 /* Total length of stored data. */
26998 uint16_t total_data_len;
27000 uint8_t unused_1[3];
27002 * This field is used in Output records to indicate that the output
27003 * is completely written to RAM. This field should be read as '1'
27004 * to indicate that the output has been completely written.
27005 * When writing a command completion or response to an internal processor,
27006 * the order of writes has to be such that this field is written last.
27011 /**********************
27012 * hwrm_port_dsc_dump *
27013 **********************/
27016 /* hwrm_port_dsc_dump_input (size:320b/40B) */
27017 struct hwrm_port_dsc_dump_input {
27018 /* The HWRM command request type. */
27021 * The completion ring to send the completion event on. This should
27022 * be the NQ ID returned from the `nq_alloc` HWRM command.
27024 uint16_t cmpl_ring;
27026 * The sequence ID is used by the driver for tracking multiple
27027 * commands. This ID is treated as opaque data by the firmware and
27028 * the value is returned in the `hwrm_resp_hdr` upon completion.
27032 * The target ID of the command:
27033 * * 0x0-0xFFF8 - The function ID
27034 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
27035 * * 0xFFFD - Reserved for user-space HWRM interface
27038 uint16_t target_id;
27040 * A physical address pointer pointing to a host buffer that the
27041 * command's response data will be written. This can be either a host
27042 * physical address (HPA) or a guest physical address (GPA) and must
27043 * point to a physically contiguous block of memory.
27045 uint64_t resp_addr;
27046 /* Host address where response diagnostic data is returned. */
27047 uint64_t resp_data_addr;
27049 * Size of the buffer pointed to by resp_data_addr. The firmware
27050 * may use this entire buffer or less than the entire buffer, but
27056 /* Port ID of port where dsc dump to be collected. */
27058 /* Diag level specified by the user */
27059 uint16_t diag_level;
27060 /* SRDS_DIAG_LANE */
27061 #define HWRM_PORT_DSC_DUMP_INPUT_DIAG_LEVEL_SRDS_DIAG_LANE \
27063 /* SRDS_DIAG_CORE */
27064 #define HWRM_PORT_DSC_DUMP_INPUT_DIAG_LEVEL_SRDS_DIAG_CORE \
27066 /* SRDS_DIAG_EVENT */
27067 #define HWRM_PORT_DSC_DUMP_INPUT_DIAG_LEVEL_SRDS_DIAG_EVENT \
27069 /* SRDS_DIAG_EYE */
27070 #define HWRM_PORT_DSC_DUMP_INPUT_DIAG_LEVEL_SRDS_DIAG_EYE \
27072 /* SRDS_DIAG_REG_CORE */
27073 #define HWRM_PORT_DSC_DUMP_INPUT_DIAG_LEVEL_SRDS_DIAG_REG_CORE \
27075 /* SRDS_DIAG_REG_LANE */
27076 #define HWRM_PORT_DSC_DUMP_INPUT_DIAG_LEVEL_SRDS_DIAG_REG_LANE \
27078 /* SRDS_DIAG_UC_CORE */
27079 #define HWRM_PORT_DSC_DUMP_INPUT_DIAG_LEVEL_SRDS_DIAG_UC_CORE \
27081 /* SRDS_DIAG_UC_LANE */
27082 #define HWRM_PORT_DSC_DUMP_INPUT_DIAG_LEVEL_SRDS_DIAG_UC_LANE \
27084 /* SRDS_DIAG_LANE_DEBUG */
27085 #define HWRM_PORT_DSC_DUMP_INPUT_DIAG_LEVEL_SRDS_DIAG_LANE_DEBUG \
27087 /* SRDS_DIAG_BER_VERT */
27088 #define HWRM_PORT_DSC_DUMP_INPUT_DIAG_LEVEL_SRDS_DIAG_BER_VERT \
27090 /* SRDS_DIAG_BER_HORZ */
27091 #define HWRM_PORT_DSC_DUMP_INPUT_DIAG_LEVEL_SRDS_DIAG_BER_HORZ \
27093 /* SRDS_DIAG_EVENT_SAFE */
27094 #define HWRM_PORT_DSC_DUMP_INPUT_DIAG_LEVEL_SRDS_DIAG_EVENT_SAFE \
27096 /* SRDS_DIAG_TIMESTAMP */
27097 #define HWRM_PORT_DSC_DUMP_INPUT_DIAG_LEVEL_SRDS_DIAG_TIMESTAMP \
27099 #define HWRM_PORT_DSC_DUMP_INPUT_DIAG_LEVEL_LAST \
27100 HWRM_PORT_DSC_DUMP_INPUT_DIAG_LEVEL_SRDS_DIAG_TIMESTAMP
27102 * This field is a lane number
27103 * on which to collect the dsc dump
27105 uint16_t lane_number;
27107 * Configuration bits.
27108 * Use enable bit to start dsc dump or retrieve dump
27110 uint16_t dsc_dump_config;
27112 * Set 0 to retrieve the dsc dump
27113 * Set 1 to start the dsc dump
27115 #define HWRM_PORT_DSC_DUMP_INPUT_DSC_DUMP_CONFIG_START_RETRIEVE \
27119 /* hwrm_port_dsc_dump_output (size:128b/16B) */
27120 struct hwrm_port_dsc_dump_output {
27121 /* The specific error status for the command. */
27122 uint16_t error_code;
27123 /* The HWRM command request type. */
27125 /* The sequence ID from the original command. */
27127 /* The length of the response data in number of bytes. */
27129 /* Total length of stored data. */
27130 uint16_t total_data_len;
27132 uint8_t unused_1[3];
27134 * This field is used in Output records to indicate that the output
27135 * is completely written to RAM. This field should be read as '1'
27136 * to indicate that the output has been completely written.
27137 * When writing a command completion or response to an internal processor,
27138 * the order of writes has to be such that this field is written last.
27143 /******************************
27144 * hwrm_port_sfp_sideband_cfg *
27145 ******************************/
27148 /* hwrm_port_sfp_sideband_cfg_input (size:256b/32B) */
27149 struct hwrm_port_sfp_sideband_cfg_input {
27150 /* The HWRM command request type. */
27153 * The completion ring to send the completion event on. This should
27154 * be the NQ ID returned from the `nq_alloc` HWRM command.
27156 uint16_t cmpl_ring;
27158 * The sequence ID is used by the driver for tracking multiple
27159 * commands. This ID is treated as opaque data by the firmware and
27160 * the value is returned in the `hwrm_resp_hdr` upon completion.
27164 * The target ID of the command:
27165 * * 0x0-0xFFF8 - The function ID
27166 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
27167 * * 0xFFFD - Reserved for user-space HWRM interface
27170 uint16_t target_id;
27172 * A physical address pointer pointing to a host buffer that the
27173 * command's response data will be written. This can be either a host
27174 * physical address (HPA) or a guest physical address (GPA) and must
27175 * point to a physically contiguous block of memory.
27177 uint64_t resp_addr;
27178 /* Port ID of port that is to be queried. */
27180 uint8_t unused_0[6];
27182 * This bitfield is used to specify which bits from the 'flags'
27183 * fields are being configured by the caller.
27186 /* This bit must be '1' for rs0 to be configured. */
27187 #define HWRM_PORT_SFP_SIDEBAND_CFG_INPUT_ENABLES_RS0 \
27189 /* This bit must be '1' for rs1 to be configured. */
27190 #define HWRM_PORT_SFP_SIDEBAND_CFG_INPUT_ENABLES_RS1 \
27192 /* This bit must be '1' for tx_disable to be configured. */
27193 #define HWRM_PORT_SFP_SIDEBAND_CFG_INPUT_ENABLES_TX_DIS \
27196 * This bit must be '1' for mod_sel to be configured.
27197 * Valid only on QSFP modules
27199 #define HWRM_PORT_SFP_SIDEBAND_CFG_INPUT_ENABLES_MOD_SEL \
27201 /* This bit must be '1' for reset_l to be configured. */
27202 #define HWRM_PORT_SFP_SIDEBAND_CFG_INPUT_ENABLES_RESET_L \
27204 /* This bit must be '1' for lp_mode to be configured. */
27205 #define HWRM_PORT_SFP_SIDEBAND_CFG_INPUT_ENABLES_LP_MODE \
27207 /* This bit must be '1' for pwr_disable to be configured. */
27208 #define HWRM_PORT_SFP_SIDEBAND_CFG_INPUT_ENABLES_PWR_DIS \
27211 * Only bits that have corresponding bits in the 'enables'
27212 * bitfield are processed by the firmware, all other bits
27213 * of 'flags' are ignored.
27217 * This bit along with rs1 configures the current speed of the dual
27218 * rate module. If these pins are GNDed then the speed can be changed
27219 * by directly writing to EEPROM.
27221 #define HWRM_PORT_SFP_SIDEBAND_CFG_INPUT_FLAGS_RS0 \
27224 * This bit along with rs0 configures the current speed of the dual
27225 * rate module. If these pins are GNDed then the speed can be changed
27226 * by directly writing to EEPROM.
27228 #define HWRM_PORT_SFP_SIDEBAND_CFG_INPUT_FLAGS_RS1 \
27231 * When this bit is set to '1', tx_disable is set.
27232 * On a 1G BASE-T module, if this bit is set,
27233 * module PHY registers will not be accessible.
27235 #define HWRM_PORT_SFP_SIDEBAND_CFG_INPUT_FLAGS_TX_DIS \
27238 * When this bit is set to '1', this module is selected.
27239 * Valid only on QSFP modules
27241 #define HWRM_PORT_SFP_SIDEBAND_CFG_INPUT_FLAGS_MOD_SEL \
27244 * If reset_l is set to 0, Module will be taken out of reset
27245 * and other signals will be set to their requested state once
27246 * the module is out of reset.
27247 * Valid only on QSFP modules
27249 #define HWRM_PORT_SFP_SIDEBAND_CFG_INPUT_FLAGS_RESET_L \
27252 * When this bit is set to '1', the module will be configured
27253 * in low power mode.
27254 * Valid only on QSFP modules
27256 #define HWRM_PORT_SFP_SIDEBAND_CFG_INPUT_FLAGS_LP_MODE \
27258 /* When this bit is set to '1', the module will be powered down. */
27259 #define HWRM_PORT_SFP_SIDEBAND_CFG_INPUT_FLAGS_PWR_DIS \
27263 /* hwrm_port_sfp_sideband_cfg_output (size:128b/16B) */
27264 struct hwrm_port_sfp_sideband_cfg_output {
27265 /* The specific error status for the command. */
27266 uint16_t error_code;
27267 /* The HWRM command request type. */
27269 /* The sequence ID from the original command. */
27271 /* The length of the response data in number of bytes. */
27275 * This field is used in Output records to indicate that the output
27276 * is completely written to RAM. This field should be read as '1'
27277 * to indicate that the output has been completely written. When
27278 * writing a command completion or response to an internal processor,
27279 * the order of writes has to be such that this field is written last.
27284 /*******************************
27285 * hwrm_port_sfp_sideband_qcfg *
27286 *******************************/
27289 /* hwrm_port_sfp_sideband_qcfg_input (size:192b/24B) */
27290 struct hwrm_port_sfp_sideband_qcfg_input {
27291 /* The HWRM command request type. */
27294 * The completion ring to send the completion event on. This should
27295 * be the NQ ID returned from the `nq_alloc` HWRM command.
27297 uint16_t cmpl_ring;
27299 * The sequence ID is used by the driver for tracking multiple
27300 * commands. This ID is treated as opaque data by the firmware and
27301 * the value is returned in the `hwrm_resp_hdr` upon completion.
27305 * The target ID of the command:
27306 * * 0x0-0xFFF8 - The function ID
27307 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
27308 * * 0xFFFD - Reserved for user-space HWRM interface
27311 uint16_t target_id;
27313 * A physical address pointer pointing to a host buffer that the
27314 * command's response data will be written. This can be either a host
27315 * physical address (HPA) or a guest physical address (GPA) and must
27316 * point to a physically contiguous block of memory.
27318 uint64_t resp_addr;
27319 /* Port ID of port that is to be queried. */
27321 uint8_t unused_0[6];
27324 /* hwrm_port_sfp_sideband_qcfg_output (size:192b/24B) */
27325 struct hwrm_port_sfp_sideband_qcfg_output {
27326 /* The specific error status for the command. */
27327 uint16_t error_code;
27328 /* The HWRM command request type. */
27330 /* The sequence ID from the original command. */
27332 /* The length of the response data in number of bytes. */
27335 * Bitmask indicating which sideband signals are valid.
27336 * This is based on the board and nvm cfg that is present on the board.
27338 uint32_t supported_mask;
27339 uint32_t sideband_signals;
27340 /* When this bit is set to '1', the Module is absent. */
27341 #define HWRM_PORT_SFP_SIDEBAND_QCFG_OUTPUT_SIDEBAND_SIGNALS_MOD_ABS \
27344 * When this bit is set to '1', there is no valid signal on RX.
27345 * This signal is a filtered version of Signal Detect.
27347 #define HWRM_PORT_SFP_SIDEBAND_QCFG_OUTPUT_SIDEBAND_SIGNALS_RX_LOS \
27350 * This bit along with rs1 indicates the current speed of the dual
27351 * rate module.If these pins are grounded then the speed can be
27352 * changed by directly writing to EEPROM.
27354 #define HWRM_PORT_SFP_SIDEBAND_QCFG_OUTPUT_SIDEBAND_SIGNALS_RS0 \
27357 * This bit along with rs0 indicates the current speed of the dual
27358 * rate module.If these pins are grounded then the speed can be
27359 * changed by directly writing to EEPROM.
27361 #define HWRM_PORT_SFP_SIDEBAND_QCFG_OUTPUT_SIDEBAND_SIGNALS_RS1 \
27364 * When this bit is set to '1', tx_disable is set.
27365 * On a 1G BASE-T module, if this bit is set, module PHY
27366 * registers will not be accessible.
27368 #define HWRM_PORT_SFP_SIDEBAND_QCFG_OUTPUT_SIDEBAND_SIGNALS_TX_DIS \
27370 /* When this bit is set to '1', tx_fault is set. */
27371 #define HWRM_PORT_SFP_SIDEBAND_QCFG_OUTPUT_SIDEBAND_SIGNALS_TX_FAULT \
27374 * When this bit is set to '1', module is selected.
27375 * Valid only on QSFP modules
27377 #define HWRM_PORT_SFP_SIDEBAND_QCFG_OUTPUT_SIDEBAND_SIGNALS_MOD_SEL \
27380 * When this bit is set to '0', the module is held in reset.
27381 * if reset_l is set to 1,first module is taken out of reset
27382 * and other signals will be set to their requested state.
27383 * Valid only on QSFP modules.
27385 #define HWRM_PORT_SFP_SIDEBAND_QCFG_OUTPUT_SIDEBAND_SIGNALS_RESET_L \
27388 * When this bit is set to '1', the module is in low power mode.
27389 * Valid only on QSFP modules
27391 #define HWRM_PORT_SFP_SIDEBAND_QCFG_OUTPUT_SIDEBAND_SIGNALS_LP_MODE \
27393 /* When this bit is set to '1', module is in power down state. */
27394 #define HWRM_PORT_SFP_SIDEBAND_QCFG_OUTPUT_SIDEBAND_SIGNALS_PWR_DIS \
27398 * This field is used in Output records to indicate that the output
27399 * is completely written to RAM. This field should be read as '1'
27400 * to indicate that the output has been completely written. When
27401 * writing a command completion or response to an internal processor,
27402 * the order of writes has to be such that this field is written last.
27407 /**********************************
27408 * hwrm_port_phy_mdio_bus_acquire *
27409 **********************************/
27412 /* hwrm_port_phy_mdio_bus_acquire_input (size:192b/24B) */
27413 struct hwrm_port_phy_mdio_bus_acquire_input {
27414 /* The HWRM command request type. */
27417 * The completion ring to send the completion event on. This should
27418 * be the NQ ID returned from the `nq_alloc` HWRM command.
27420 uint16_t cmpl_ring;
27422 * The sequence ID is used by the driver for tracking multiple
27423 * commands. This ID is treated as opaque data by the firmware and
27424 * the value is returned in the `hwrm_resp_hdr` upon completion.
27428 * The target ID of the command:
27429 * * 0x0-0xFFF8 - The function ID
27430 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
27431 * * 0xFFFD - Reserved for user-space HWRM interface
27434 uint16_t target_id;
27436 * A physical address pointer pointing to a host buffer that the
27437 * command's response data will be written. This can be either a host
27438 * physical address (HPA) or a guest physical address (GPA) and must
27439 * point to a physically contiguous block of memory.
27441 uint64_t resp_addr;
27442 /* Port ID of the port. */
27445 * client_id of the client requesting BUS access.
27446 * Any value from 0x10 to 0xFFFF can be used.
27447 * Client should make sure that the returned client_id
27448 * in response matches the client_id in request.
27449 * 0-0xF are reserved for internal use.
27451 uint16_t client_id;
27453 * Timeout in milli seconds, MDIO BUS will be released automatically
27454 * after this time, if another mdio acquire command is not received
27455 * within the timeout window from the same client.
27456 * A 0xFFFF will hold the bus until this bus is released.
27458 uint16_t mdio_bus_timeout;
27459 uint8_t unused_0[2];
27462 /* hwrm_port_phy_mdio_bus_acquire_output (size:128b/16B) */
27463 struct hwrm_port_phy_mdio_bus_acquire_output {
27464 /* The specific error status for the command. */
27465 uint16_t error_code;
27466 /* The HWRM command request type. */
27468 /* The sequence ID from the original command. */
27470 /* The length of the response data in number of bytes. */
27474 * client_id of the module holding the BUS.
27475 * 0-0xF are reserved for internal use.
27477 uint16_t client_id;
27478 uint8_t unused_1[3];
27480 * This field is used in Output records to indicate that the output
27481 * is completely written to RAM. This field should be read as '1'
27482 * to indicate that the output has been completely written.
27483 * When writing a command completion or response to an internal processor,
27484 * the order of writes has to be such that this field is written last.
27489 /**********************************
27490 * hwrm_port_phy_mdio_bus_release *
27491 **********************************/
27494 /* hwrm_port_phy_mdio_bus_release_input (size:192b/24B) */
27495 struct hwrm_port_phy_mdio_bus_release_input {
27496 /* The HWRM command request type. */
27499 * The completion ring to send the completion event on. This should
27500 * be the NQ ID returned from the `nq_alloc` HWRM command.
27502 uint16_t cmpl_ring;
27504 * The sequence ID is used by the driver for tracking multiple
27505 * commands. This ID is treated as opaque data by the firmware and
27506 * the value is returned in the `hwrm_resp_hdr` upon completion.
27510 * The target ID of the command:
27511 * * 0x0-0xFFF8 - The function ID
27512 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
27513 * * 0xFFFD - Reserved for user-space HWRM interface
27516 uint16_t target_id;
27518 * A physical address pointer pointing to a host buffer that the
27519 * command's response data will be written. This can be either a host
27520 * physical address (HPA) or a guest physical address (GPA) and must
27521 * point to a physically contiguous block of memory.
27523 uint64_t resp_addr;
27524 /* Port ID of the port. */
27527 * client_id of the client requesting BUS release.
27528 * A client should not release any other clients BUS.
27530 uint16_t client_id;
27531 uint8_t unused_0[4];
27534 /* hwrm_port_phy_mdio_bus_release_output (size:128b/16B) */
27535 struct hwrm_port_phy_mdio_bus_release_output {
27536 /* The specific error status for the command. */
27537 uint16_t error_code;
27538 /* The HWRM command request type. */
27540 /* The sequence ID from the original command. */
27542 /* The length of the response data in number of bytes. */
27545 /* The BUS is released if client_id matches the client_id in request. */
27546 uint16_t clients_id;
27547 uint8_t unused_1[3];
27549 * This field is used in Output records to indicate that the output
27550 * is completely written to RAM. This field should be read as '1'
27551 * to indicate that the output has been completely written.
27552 * When writing a command completion or response to an internal processor,
27553 * the order of writes has to be such that this field is written last.
27558 /************************
27559 * hwrm_port_tx_fir_cfg *
27560 ************************/
27563 /* hwrm_port_tx_fir_cfg_input (size:320b/40B) */
27564 struct hwrm_port_tx_fir_cfg_input {
27565 /* The HWRM command request type. */
27568 * The completion ring to send the completion event on. This should
27569 * be the NQ ID returned from the `nq_alloc` HWRM command.
27571 uint16_t cmpl_ring;
27573 * The sequence ID is used by the driver for tracking multiple
27574 * commands. This ID is treated as opaque data by the firmware and
27575 * the value is returned in the `hwrm_resp_hdr` upon completion.
27579 * The target ID of the command:
27580 * * 0x0-0xFFF8 - The function ID
27581 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
27582 * * 0xFFFD - Reserved for user-space HWRM interface
27585 uint16_t target_id;
27587 * A physical address pointer pointing to a host buffer that the
27588 * command's response data will be written. This can be either a host
27589 * physical address (HPA) or a guest physical address (GPA) and must
27590 * point to a physically contiguous block of memory.
27592 uint64_t resp_addr;
27593 /* Modulation types of TX FIR: NRZ, PAM4. */
27596 #define HWRM_PORT_TX_FIR_CFG_INPUT_MOD_TYPE_NRZ UINT32_C(0x0)
27598 #define HWRM_PORT_TX_FIR_CFG_INPUT_MOD_TYPE_PAM4 UINT32_C(0x1)
27599 #define HWRM_PORT_TX_FIR_CFG_INPUT_MOD_TYPE_LAST \
27600 HWRM_PORT_TX_FIR_CFG_INPUT_MOD_TYPE_PAM4
27601 /* The lane mask of the lane TX FIR will be configured. */
27603 uint8_t unused_0[2];
27604 /* Value1 of TX FIR, required for NRZ or PAM4. */
27605 uint32_t txfir_val_1;
27606 /* Value2 of TX FIR, required for NRZ or PAM4. */
27607 uint32_t txfir_val_2;
27608 /* Value3 of TX FIR, required for PAM4. */
27609 uint32_t txfir_val_3;
27610 /* Value4 of TX FIR, required for PAM4. */
27611 uint32_t txfir_val_4;
27612 uint8_t unused_1[4];
27615 /* hwrm_port_tx_fir_cfg_output (size:128b/16B) */
27616 struct hwrm_port_tx_fir_cfg_output {
27617 /* The specific error status for the command. */
27618 uint16_t error_code;
27619 /* The HWRM command request type. */
27621 /* The sequence ID from the original command. */
27623 /* The length of the response data in number of bytes. */
27627 * This field is used in Output records to indicate that the output
27628 * is completely written to RAM. This field should be read as '1'
27629 * to indicate that the output has been completely written.
27630 * When writing a command completion or response to an internal processor,
27631 * the order of writes has to be such that this field is written last.
27636 /*************************
27637 * hwrm_port_tx_fir_qcfg *
27638 *************************/
27641 /* hwrm_port_tx_fir_qcfg_input (size:192b/24B) */
27642 struct hwrm_port_tx_fir_qcfg_input {
27643 /* The HWRM command request type. */
27646 * The completion ring to send the completion event on. This should
27647 * be the NQ ID returned from the `nq_alloc` HWRM command.
27649 uint16_t cmpl_ring;
27651 * The sequence ID is used by the driver for tracking multiple
27652 * commands. This ID is treated as opaque data by the firmware and
27653 * the value is returned in the `hwrm_resp_hdr` upon completion.
27657 * The target ID of the command:
27658 * * 0x0-0xFFF8 - The function ID
27659 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
27660 * * 0xFFFD - Reserved for user-space HWRM interface
27663 uint16_t target_id;
27665 * A physical address pointer pointing to a host buffer that the
27666 * command's response data will be written. This can be either a host
27667 * physical address (HPA) or a guest physical address (GPA) and must
27668 * point to a physically contiguous block of memory.
27670 uint64_t resp_addr;
27671 /* Modulation types of TX FIR: NRZ, PAM4. */
27674 #define HWRM_PORT_TX_FIR_QCFG_INPUT_MOD_TYPE_NRZ UINT32_C(0x0)
27676 #define HWRM_PORT_TX_FIR_QCFG_INPUT_MOD_TYPE_PAM4 UINT32_C(0x1)
27677 #define HWRM_PORT_TX_FIR_QCFG_INPUT_MOD_TYPE_LAST \
27678 HWRM_PORT_TX_FIR_QCFG_INPUT_MOD_TYPE_PAM4
27679 /* The ID of the lane TX FIR will be queried. */
27684 /* hwrm_port_tx_fir_qcfg_output (size:256b/32B) */
27685 struct hwrm_port_tx_fir_qcfg_output {
27686 /* The specific error status for the command. */
27687 uint16_t error_code;
27688 /* The HWRM command request type. */
27690 /* The sequence ID from the original command. */
27692 /* The length of the response data in number of bytes. */
27694 /* Value1 of TX FIR, required for NRZ or PAM4. */
27695 uint32_t txfir_val_1;
27696 /* Value2 of TX FIR, required for NRZ or PAM4. */
27697 uint32_t txfir_val_2;
27698 /* Value3 of TX FIR, required for PAM4. */
27699 uint32_t txfir_val_3;
27700 /* Value4 of TX FIR, required for PAM4. */
27701 uint32_t txfir_val_4;
27704 * This field is used in Output records to indicate that the output
27705 * is completely written to RAM. This field should be read as '1'
27706 * to indicate that the output has been completely written.
27707 * When writing a command completion or response to an internal processor,
27708 * the order of writes has to be such that this field is written last.
27713 /***********************
27714 * hwrm_port_ep_tx_cfg *
27715 ***********************/
27718 /* hwrm_port_ep_tx_cfg_input (size:256b/32B) */
27719 struct hwrm_port_ep_tx_cfg_input {
27720 /* The HWRM command request type. */
27723 * The completion ring to send the completion event on. This should
27724 * be the NQ ID returned from the `nq_alloc` HWRM command.
27726 uint16_t cmpl_ring;
27728 * The sequence ID is used by the driver for tracking multiple
27729 * commands. This ID is treated as opaque data by the firmware and
27730 * the value is returned in the `hwrm_resp_hdr` upon completion.
27734 * The target ID of the command:
27735 * * 0x0-0xFFF8 - The function ID
27736 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
27737 * * 0xFFFD - Reserved for user-space HWRM interface
27740 uint16_t target_id;
27742 * A physical address pointer pointing to a host buffer that the
27743 * command's response data will be written. This can be either a host
27744 * physical address (HPA) or a guest physical address (GPA) and must
27745 * point to a physically contiguous block of memory.
27747 uint64_t resp_addr;
27749 /* When this bit is '1', the value in the ep0_min_bw field is valid. */
27750 #define HWRM_PORT_EP_TX_CFG_INPUT_ENABLES_EP0_MIN_BW UINT32_C(0x1)
27751 /* When this bit is '1', the value in the ep0_max_bw field is valid. */
27752 #define HWRM_PORT_EP_TX_CFG_INPUT_ENABLES_EP0_MAX_BW UINT32_C(0x2)
27753 /* When this bit is '1', the value in the ep1_min_bw field is valid. */
27754 #define HWRM_PORT_EP_TX_CFG_INPUT_ENABLES_EP1_MIN_BW UINT32_C(0x4)
27755 /* When this bit is '1', the value in the ep1_max_bw field is valid. */
27756 #define HWRM_PORT_EP_TX_CFG_INPUT_ENABLES_EP1_MAX_BW UINT32_C(0x8)
27757 /* When this bit is '1', the value in the ep2_min_bw field is valid. */
27758 #define HWRM_PORT_EP_TX_CFG_INPUT_ENABLES_EP2_MIN_BW UINT32_C(0x10)
27759 /* When this bit is '1', the value in the ep2_max_bw field is valid. */
27760 #define HWRM_PORT_EP_TX_CFG_INPUT_ENABLES_EP2_MAX_BW UINT32_C(0x20)
27761 /* When this bit is '1', the value in the ep3_min_bw field is valid. */
27762 #define HWRM_PORT_EP_TX_CFG_INPUT_ENABLES_EP3_MIN_BW UINT32_C(0x40)
27763 /* When this bit is '1', the value in the ep3_max_bw field is valid. */
27764 #define HWRM_PORT_EP_TX_CFG_INPUT_ENABLES_EP3_MAX_BW UINT32_C(0x80)
27765 /* A port index, from 0 to the number of front panel ports, minus 1. */
27769 * Specifies a minimum guaranteed bandwidth, as a percentage of the
27770 * port bandwidth, for the set of PFs and VFs on PCIe endpoint 0 for
27771 * the specified port. The range is 0 to 100. A value of 0 indicates no
27772 * minimum rate. The endpoint's min_bw must be less than or equal to
27773 * max_bw. The sum of all configured minimum bandwidths for a port must
27774 * be less than or equal to 100.
27776 uint8_t ep0_min_bw;
27778 * Specifies the maximum portion of the port's bandwidth that the set
27779 * of PFs and VFs on PCIe endpoint 0 may use. The value is a percentage
27780 * of the link bandwidth, from 0 to 100. A value of 0 indicates no
27783 uint8_t ep0_max_bw;
27785 * Specifies a minimum guaranteed bandwidth, as a percentage of the
27786 * port bandwidth, for the set of PFs and VFs on PCIe endpoint 1 for
27787 * the specified port. The range is 0 to 100. A value of 0 indicates no
27788 * minimum rate. The endpoint's min_bw must be less than or equal to
27789 * max_bw. The sum of all configured minimum bandwidths for a port must
27790 * be less than or equal to 100.
27792 uint8_t ep1_min_bw;
27794 * Specifies the maximum portion of the port's bandwidth that the set
27795 * of PFs and VFs on PCIe endpoint 1 may use. The value is a percentage
27796 * of the link bandwidth, from 0 to 100. A value of 0 indicates no
27799 uint8_t ep1_max_bw;
27801 * Specifies a minimum guaranteed bandwidth, as a percentage of the
27802 * port bandwidth, for the set of PFs and VFs on PCIe endpoint 2 for
27803 * the specified port. The range is 0 to 100. A value of 0 indicates no
27804 * minimum rate. The endpoint's min_bw must be less than or equal to
27805 * max_bw. The sum of all configured minimum bandwidths for a port must
27806 * be less than or equal to 100.
27808 uint8_t ep2_min_bw;
27810 * Specifies the maximum portion of the port's bandwidth that the set of
27811 * PFs and VFs on PCIe endpoint 2 may use. The value is a percentage of
27812 * the link bandwidth, from 0 to 100. A value of 0 indicates no
27815 uint8_t ep2_max_bw;
27817 * Specifies a minimum guaranteed bandwidth, as a percentage of the
27818 * port bandwidth, for the set of PFs and VFs on PCIe endpoint 3 for
27819 * the specified port. The range is 0 to 100. A value of 0 indicates no
27820 * minimum rate. The endpoint's min_bw must be less than or equal to
27821 * max_bw. The sum of all configured minimum bandwidths for a port must
27822 * be less than or equal to 100.
27824 uint8_t ep3_min_bw;
27826 * Specifies the maximum portion of the port's bandwidth that the set
27827 * of PFs and VFs on PCIe endpoint 3 may use. The value is a percentage
27828 * of the link bandwidth, from 0 to 100. A value of 0 indicates no
27831 uint8_t ep3_max_bw;
27832 uint8_t unused_1[4];
27835 /* hwrm_port_ep_tx_cfg_output (size:128b/16B) */
27836 struct hwrm_port_ep_tx_cfg_output {
27837 /* The specific error status for the command. */
27838 uint16_t error_code;
27839 /* The HWRM command request type. */
27841 /* The sequence ID from the original command. */
27843 /* The length of the response data in number of bytes. */
27845 uint8_t unused_0[7];
27847 * This field is used in output records to indicate that the output
27848 * is completely written to RAM. This field should be read as '1'
27849 * to indicate that the output has been completely written.
27850 * When writing a command completion or response to an internal
27851 * processor, the order of writes has to be such that this field
27857 /* hwrm_port_ep_tx_cfg_cmd_err (size:64b/8B) */
27858 struct hwrm_port_ep_tx_cfg_cmd_err {
27860 * command specific error codes for the cmd_err field in
27864 /* Unknown error. */
27865 #define HWRM_PORT_EP_TX_CFG_CMD_ERR_CODE_UNKNOWN \
27867 /* The port ID is invalid */
27868 #define HWRM_PORT_EP_TX_CFG_CMD_ERR_CODE_PORT_ID_INVALID \
27870 /* One of the PCIe endpoints configured is not active. */
27871 #define HWRM_PORT_EP_TX_CFG_CMD_ERR_CODE_EP_INACTIVE \
27873 /* A minimum bandwidth is out of range. */
27874 #define HWRM_PORT_EP_TX_CFG_CMD_ERR_CODE_MIN_BW_RANGE \
27877 * One endpoint's minimum bandwidth is more than its maximum
27880 #define HWRM_PORT_EP_TX_CFG_CMD_ERR_CODE_MIN_MORE_THAN_MAX \
27882 /* The sum of the minimum bandwidths on the port is more than 100%. */
27883 #define HWRM_PORT_EP_TX_CFG_CMD_ERR_CODE_MIN_BW_SUM \
27886 * The NIC does not support enforcement of a minimum guaranteed
27887 * bandwidth for an endpoint.
27889 #define HWRM_PORT_EP_TX_CFG_CMD_ERR_CODE_MIN_BW_UNSUPPORTED \
27891 #define HWRM_PORT_EP_TX_CFG_CMD_ERR_CODE_LAST \
27892 HWRM_PORT_EP_TX_CFG_CMD_ERR_CODE_MIN_BW_UNSUPPORTED
27893 uint8_t unused_0[7];
27896 /************************
27897 * hwrm_port_ep_tx_qcfg *
27898 ************************/
27901 /* hwrm_port_ep_tx_qcfg_input (size:192b/24B) */
27902 struct hwrm_port_ep_tx_qcfg_input {
27903 /* The HWRM command request type. */
27906 * The completion ring to send the completion event on. This should
27907 * be the NQ ID returned from the `nq_alloc` HWRM command.
27909 uint16_t cmpl_ring;
27911 * The sequence ID is used by the driver for tracking multiple
27912 * commands. This ID is treated as opaque data by the firmware and
27913 * the value is returned in the `hwrm_resp_hdr` upon completion.
27917 * The target ID of the command:
27918 * * 0x0-0xFFF8 - The function ID
27919 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
27920 * * 0xFFFD - Reserved for user-space HWRM interface
27923 uint16_t target_id;
27925 * A physical address pointer pointing to a host buffer that the
27926 * command's response data will be written. This can be either a host
27927 * physical address (HPA) or a guest physical address (GPA) and must
27928 * point to a physically contiguous block of memory.
27930 uint64_t resp_addr;
27931 /* The port whose endpoint rate limits are queried. */
27936 /* hwrm_port_ep_tx_qcfg_output (size:192b/24B) */
27937 struct hwrm_port_ep_tx_qcfg_output {
27938 /* The specific error status for the command. */
27939 uint16_t error_code;
27940 /* The HWRM command request type. */
27942 /* The sequence ID from the original command. */
27944 /* The length of the response data in number of bytes. */
27947 * Specifies a minimum guaranteed bandwidth, as a percentage of the
27948 * port bandwidth, for the set of PFs and VFs on PCIe endpoint 0 for
27949 * the specified port. The range is 0 to 100. A value of 0 indicates no
27950 * minimum rate. The endpoint's min_bw must be less than or equal to
27951 * max_bw. The sum of all configured minimum bandwidths for a port must
27952 * be less than or equal to 100.
27954 uint8_t ep0_min_bw;
27956 * Specifies the maximum portion of the port's bandwidth that the set
27957 * of PFs and VFs on PCIe endpoint 0 may use. The value is a percentage
27958 * of the link bandwidth, from 0 to 100. A value of 0 indicates no
27961 uint8_t ep0_max_bw;
27963 * Specifies a minimum guaranteed bandwidth, as a percentage of the
27964 * port bandwidth, for the set of PFs and VFs on PCIe endpoint 1 for
27965 * the specified port. The range is 0 to 100. A value of 0 indicates no
27966 * minimum rate. The endpoint's min_bw must be less than or equal to
27967 * max_bw. The sum of all configured minimum bandwidths for a port must
27968 * be less than or equal to 100.
27970 uint8_t ep1_min_bw;
27972 * Specifies the maximum portion of the port's bandwidth that the set
27973 * of PFs and VFs on PCIe endpoint 1 may use. The value is a percentage
27974 * of the link bandwidth, from 0 to 100. A value of 0 indicates no
27977 uint8_t ep1_max_bw;
27979 * Specifies a minimum guaranteed bandwidth, as a percentage of the
27980 * port bandwidth, for the set of PFs and VFs on PCIe endpoint 2 for
27981 * the specified port. The range is 0 to 100. A value of 0 indicates no
27982 * minimum rate. The endpoint's min_bw must be less than or equal to
27983 * max_bw. The sum of all configured minimum bandwidths for a port must
27984 * be less than or equal to 100.
27986 uint8_t ep2_min_bw;
27988 * Specifies the maximum portion of the port's bandwidth that the set
27989 * of PFs and VFs on PCIe endpoint 2 may use. The value is a percentage
27990 * of the link bandwidth, from 0 to 100. A value of 0 indicates no
27993 uint8_t ep2_max_bw;
27995 * Specifies a minimum guaranteed bandwidth, as a percentage of the
27996 * port bandwidth, for the set of PFs and VFs on PCIe endpoint 3 for
27997 * the specified port. The range is 0 to 100. A value of 0 indicates no
27998 * minimum rate. The endpoint's min_bw must be less than or equal to
27999 * max_bw. The sum of all configured minimum bandwidths for a port must
28000 * be less than or equal to 100.
28002 uint8_t ep3_min_bw;
28004 * Specifies the maximum portion of the port's bandwidth that the set
28005 * of PFs and VFs on PCIe endpoint 3 may use. The value is a percentage
28006 * of the link bandwidth, from 0 to 100. A value of 0 indicates no
28009 uint8_t ep3_max_bw;
28010 uint8_t unused_0[7];
28012 * This field is used in output records to indicate that the output
28013 * is completely written to RAM. This field should be read as '1'
28014 * to indicate that the output has been completely written.
28015 * When writing a command completion or response to an internal
28016 * processor, the order of writes has to be such that this field is
28022 /***********************
28023 * hwrm_queue_qportcfg *
28024 ***********************/
28027 /* hwrm_queue_qportcfg_input (size:192b/24B) */
28028 struct hwrm_queue_qportcfg_input {
28029 /* The HWRM command request type. */
28032 * The completion ring to send the completion event on. This should
28033 * be the NQ ID returned from the `nq_alloc` HWRM command.
28035 uint16_t cmpl_ring;
28037 * The sequence ID is used by the driver for tracking multiple
28038 * commands. This ID is treated as opaque data by the firmware and
28039 * the value is returned in the `hwrm_resp_hdr` upon completion.
28043 * The target ID of the command:
28044 * * 0x0-0xFFF8 - The function ID
28045 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
28046 * * 0xFFFD - Reserved for user-space HWRM interface
28049 uint16_t target_id;
28051 * A physical address pointer pointing to a host buffer that the
28052 * command's response data will be written. This can be either a host
28053 * physical address (HPA) or a guest physical address (GPA) and must
28054 * point to a physically contiguous block of memory.
28056 uint64_t resp_addr;
28059 * Enumeration denoting the RX, TX type of the resource.
28060 * This enumeration is used for resources that are similar for both
28061 * TX and RX paths of the chip.
28063 #define HWRM_QUEUE_QPORTCFG_INPUT_FLAGS_PATH UINT32_C(0x1)
28065 #define HWRM_QUEUE_QPORTCFG_INPUT_FLAGS_PATH_TX UINT32_C(0x0)
28067 #define HWRM_QUEUE_QPORTCFG_INPUT_FLAGS_PATH_RX UINT32_C(0x1)
28068 #define HWRM_QUEUE_QPORTCFG_INPUT_FLAGS_PATH_LAST \
28069 HWRM_QUEUE_QPORTCFG_INPUT_FLAGS_PATH_RX
28071 * Port ID of port for which the queue configuration is being
28072 * queried. This field is only required when sent by IPC.
28076 * Drivers will set this capability when it can use
28077 * queue_idx_service_profile to map the queues to application.
28079 uint8_t drv_qmap_cap;
28081 #define HWRM_QUEUE_QPORTCFG_INPUT_DRV_QMAP_CAP_DISABLED UINT32_C(0x0)
28083 #define HWRM_QUEUE_QPORTCFG_INPUT_DRV_QMAP_CAP_ENABLED UINT32_C(0x1)
28084 #define HWRM_QUEUE_QPORTCFG_INPUT_DRV_QMAP_CAP_LAST \
28085 HWRM_QUEUE_QPORTCFG_INPUT_DRV_QMAP_CAP_ENABLED
28089 /* hwrm_queue_qportcfg_output (size:1344b/168B) */
28090 struct hwrm_queue_qportcfg_output {
28091 /* The specific error status for the command. */
28092 uint16_t error_code;
28093 /* The HWRM command request type. */
28095 /* The sequence ID from the original command. */
28097 /* The length of the response data in number of bytes. */
28100 * The maximum number of queues that can be configured on this
28102 * Valid values range from 1 through 8.
28104 uint8_t max_configurable_queues;
28106 * The maximum number of lossless queues that can be configured
28108 * Valid values range from 0 through 8.
28110 uint8_t max_configurable_lossless_queues;
28112 * Bitmask indicating which queues can be configured by the
28113 * hwrm_queue_cfg command.
28115 * Each bit represents a specific queue where bit 0 represents
28116 * queue 0 and bit 7 represents queue 7.
28117 * # A value of 0 indicates that the queue is not configurable
28118 * by the hwrm_queue_cfg command.
28119 * # A value of 1 indicates that the queue is configurable.
28120 * # A hwrm_queue_cfg command shall return error when trying to
28121 * configure a queue not configurable.
28123 uint8_t queue_cfg_allowed;
28124 /* Information about queue configuration. */
28125 uint8_t queue_cfg_info;
28127 * If this flag is set to '1', then the queues are
28128 * configured asymmetrically on TX and RX sides.
28129 * If this flag is set to '0', then the queues are
28130 * configured symmetrically on TX and RX sides. For
28131 * symmetric configuration, the queue configuration
28132 * including queue ids and service profiles on the
28133 * TX side is the same as the corresponding queue
28134 * configuration on the RX side.
28136 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_CFG_INFO_ASYM_CFG \
28139 * If this flag is set to '1', then service_profile will carry
28140 * either lossy/lossless type and the new service_profile_type
28141 * field will be used to determine if the queue is for L2/ROCE/CNP.
28143 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_CFG_INFO_USE_PROFILE_TYPE \
28146 * Bitmask indicating which queues can be configured by the
28147 * hwrm_queue_pfcenable_cfg command.
28149 * Each bit represents a specific priority where bit 0 represents
28150 * priority 0 and bit 7 represents priority 7.
28151 * # A value of 0 indicates that the priority is not configurable by
28152 * the hwrm_queue_pfcenable_cfg command.
28153 * # A value of 1 indicates that the priority is configurable.
28154 * # A hwrm_queue_pfcenable_cfg command shall return error when
28155 * trying to configure a priority that is not configurable.
28157 uint8_t queue_pfcenable_cfg_allowed;
28159 * Bitmask indicating which queues can be configured by the
28160 * hwrm_queue_pri2cos_cfg command.
28162 * Each bit represents a specific queue where bit 0 represents
28163 * queue 0 and bit 7 represents queue 7.
28164 * # A value of 0 indicates that the queue is not configurable
28165 * by the hwrm_queue_pri2cos_cfg command.
28166 * # A value of 1 indicates that the queue is configurable.
28167 * # A hwrm_queue_pri2cos_cfg command shall return error when
28168 * trying to configure a queue that is not configurable.
28170 uint8_t queue_pri2cos_cfg_allowed;
28172 * Bitmask indicating which queues can be configured by the
28173 * hwrm_queue_pri2cos_cfg command.
28175 * Each bit represents a specific queue where bit 0 represents
28176 * queue 0 and bit 7 represents queue 7.
28177 * # A value of 0 indicates that the queue is not configurable
28178 * by the hwrm_queue_pri2cos_cfg command.
28179 * # A value of 1 indicates that the queue is configurable.
28180 * # A hwrm_queue_pri2cos_cfg command shall return error when
28181 * trying to configure a queue not configurable.
28183 uint8_t queue_cos2bw_cfg_allowed;
28185 * ID of CoS Queue 0.
28188 * # This ID can be used on any subsequent call to an hwrm command
28189 * that takes a queue id.
28190 * # IDs must always be queried by this command before any use
28191 * by the driver or software.
28192 * # The CoS queue index is obtained by applying modulo 10 to the
28193 * CoS queue ID. Valid CoS queue indexes are in the range of 0 to 7.
28194 * The CoS queue index is used to reference port statistics for the
28196 * # A value of 0xff indicates that the queue is not available.
28197 * # Available queues may not be in sequential order.
28200 /* This value specifies service profile kind for CoS queue */
28201 uint8_t queue_id0_service_profile;
28202 /* Lossy (best-effort) */
28203 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID0_SERVICE_PROFILE_LOSSY \
28206 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID0_SERVICE_PROFILE_LOSSLESS \
28208 /* Lossless RoCE (deprecated) */
28209 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID0_SERVICE_PROFILE_LOSSLESS_ROCE \
28211 /* Lossy RoCE CNP (deprecated) */
28212 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID0_SERVICE_PROFILE_LOSSY_ROCE_CNP \
28214 /* Lossless NIC (deprecated) */
28215 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID0_SERVICE_PROFILE_LOSSLESS_NIC \
28217 /* Set to 0xFF... (All Fs) if there is no service profile specified */
28218 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID0_SERVICE_PROFILE_UNKNOWN \
28220 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID0_SERVICE_PROFILE_LAST \
28221 HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID0_SERVICE_PROFILE_UNKNOWN
28223 * ID of CoS Queue 1.
28226 * # This ID can be used on any subsequent call to an hwrm command
28227 * that takes a queue id.
28228 * # IDs must always be queried by this command before any use
28229 * by the driver or software.
28230 * # The CoS queue index is obtained by applying modulo 10 to the
28231 * CoS queue ID. Valid CoS queue indexes are in the range of 0 to 7.
28232 * The CoS queue index is used to reference port statistics for the
28234 * # A value of 0xff indicates that the queue is not available.
28235 * # Available queues may not be in sequential order.
28238 /* This value specifies service profile kind for CoS queue */
28239 uint8_t queue_id1_service_profile;
28240 /* Lossy (best-effort) */
28241 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID1_SERVICE_PROFILE_LOSSY \
28244 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID1_SERVICE_PROFILE_LOSSLESS \
28246 /* Lossless RoCE (deprecated) */
28247 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID1_SERVICE_PROFILE_LOSSLESS_ROCE \
28249 /* Lossy RoCE CNP (deprecated) */
28250 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID1_SERVICE_PROFILE_LOSSY_ROCE_CNP \
28252 /* Lossless NIC (deprecated) */
28253 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID1_SERVICE_PROFILE_LOSSLESS_NIC \
28255 /* Set to 0xFF... (All Fs) if there is no service profile specified */
28256 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID1_SERVICE_PROFILE_UNKNOWN \
28258 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID1_SERVICE_PROFILE_LAST \
28259 HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID1_SERVICE_PROFILE_UNKNOWN
28261 * ID of CoS Queue 2.
28264 * # This ID can be used on any subsequent call to an hwrm command
28265 * that takes a queue id.
28266 * # IDs must always be queried by this command before any use
28267 * by the driver or software.
28268 * # The CoS queue index is obtained by applying modulo 10 to the
28269 * CoS queue ID. Valid CoS queue indexes are in the range of 0 to 7.
28270 * The CoS queue index is used to reference port statistics for the
28272 * # A value of 0xff indicates that the queue is not available.
28273 * # Available queues may not be in sequential order.
28276 /* This value specifies service profile kind for CoS queue */
28277 uint8_t queue_id2_service_profile;
28278 /* Lossy (best-effort) */
28279 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID2_SERVICE_PROFILE_LOSSY \
28282 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID2_SERVICE_PROFILE_LOSSLESS \
28284 /* Lossless RoCE (deprecated) */
28285 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID2_SERVICE_PROFILE_LOSSLESS_ROCE \
28287 /* Lossy RoCE CNP (deprecated) */
28288 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID2_SERVICE_PROFILE_LOSSY_ROCE_CNP \
28290 /* Lossless NIC (deprecated) */
28291 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID2_SERVICE_PROFILE_LOSSLESS_NIC \
28293 /* Set to 0xFF... (All Fs) if there is no service profile specified */
28294 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID2_SERVICE_PROFILE_UNKNOWN \
28296 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID2_SERVICE_PROFILE_LAST \
28297 HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID2_SERVICE_PROFILE_UNKNOWN
28299 * ID of CoS Queue 3.
28302 * # This ID can be used on any subsequent call to an hwrm command
28303 * that takes a queue id.
28304 * # IDs must always be queried by this command before any use
28305 * by the driver or software.
28306 * # The CoS queue index is obtained by applying modulo 10 to the
28307 * CoS queue ID. Valid CoS queue indexes are in the range of 0 to 7.
28308 * The CoS queue index is used to reference port statistics for the
28310 * # A value of 0xff indicates that the queue is not available.
28311 * # Available queues may not be in sequential order.
28314 /* This value specifies service profile kind for CoS queue */
28315 uint8_t queue_id3_service_profile;
28316 /* Lossy (best-effort) */
28317 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID3_SERVICE_PROFILE_LOSSY \
28320 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID3_SERVICE_PROFILE_LOSSLESS \
28322 /* Lossless RoCE (deprecated) */
28323 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID3_SERVICE_PROFILE_LOSSLESS_ROCE \
28325 /* Lossy RoCE CNP (deprecated) */
28326 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID3_SERVICE_PROFILE_LOSSY_ROCE_CNP \
28328 /* Lossless NIC (deprecated) */
28329 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID3_SERVICE_PROFILE_LOSSLESS_NIC \
28331 /* Set to 0xFF... (All Fs) if there is no service profile specified */
28332 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID3_SERVICE_PROFILE_UNKNOWN \
28334 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID3_SERVICE_PROFILE_LAST \
28335 HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID3_SERVICE_PROFILE_UNKNOWN
28337 * ID of CoS Queue 4.
28340 * # This ID can be used on any subsequent call to an hwrm command
28341 * that takes a queue id.
28342 * # IDs must always be queried by this command before any use
28343 * by the driver or software.
28344 * # The CoS queue index is obtained by applying modulo 10 to the
28345 * CoS queue ID. Valid CoS queue indexes are in the range of 0 to 7.
28346 * The CoS queue index is used to reference port statistics for the
28348 * # A value of 0xff indicates that the queue is not available.
28349 * # Available queues may not be in sequential order.
28352 /* This value specifies service profile kind for CoS queue */
28353 uint8_t queue_id4_service_profile;
28354 /* Lossy (best-effort) */
28355 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID4_SERVICE_PROFILE_LOSSY \
28358 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID4_SERVICE_PROFILE_LOSSLESS \
28360 /* Lossless RoCE (deprecated) */
28361 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID4_SERVICE_PROFILE_LOSSLESS_ROCE \
28363 /* Lossy RoCE CNP (deprecated) */
28364 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID4_SERVICE_PROFILE_LOSSY_ROCE_CNP \
28366 /* Lossless NIC (deprecated) */
28367 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID4_SERVICE_PROFILE_LOSSLESS_NIC \
28369 /* Set to 0xFF... (All Fs) if there is no service profile specified */
28370 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID4_SERVICE_PROFILE_UNKNOWN \
28372 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID4_SERVICE_PROFILE_LAST \
28373 HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID4_SERVICE_PROFILE_UNKNOWN
28375 * ID of CoS Queue 5.
28378 * # This ID can be used on any subsequent call to an hwrm command
28379 * that takes a queue id.
28380 * # IDs must always be queried by this command before any use
28381 * by the driver or software.
28382 * # The CoS queue index is obtained by applying modulo 10 to the
28383 * CoS queue ID. Valid CoS queue indexes are in the range of 0 to 7.
28384 * The CoS queue index is used to reference port statistics for the
28386 * # A value of 0xff indicates that the queue is not available.
28387 * # Available queues may not be in sequential order.
28390 /* This value specifies service profile kind for CoS queue */
28391 uint8_t queue_id5_service_profile;
28392 /* Lossy (best-effort) */
28393 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID5_SERVICE_PROFILE_LOSSY \
28396 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID5_SERVICE_PROFILE_LOSSLESS \
28398 /* Lossless RoCE (deprecated) */
28399 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID5_SERVICE_PROFILE_LOSSLESS_ROCE \
28401 /* Lossy RoCE CNP (deprecated) */
28402 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID5_SERVICE_PROFILE_LOSSY_ROCE_CNP \
28404 /* Lossless NIC (deprecated) */
28405 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID5_SERVICE_PROFILE_LOSSLESS_NIC \
28407 /* Set to 0xFF... (All Fs) if there is no service profile specified */
28408 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID5_SERVICE_PROFILE_UNKNOWN \
28410 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID5_SERVICE_PROFILE_LAST \
28411 HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID5_SERVICE_PROFILE_UNKNOWN
28413 * ID of CoS Queue 6.
28416 * # This ID can be used on any subsequent call to an hwrm command
28417 * that takes a queue id.
28418 * # IDs must always be queried by this command before any use
28419 * by the driver or software.
28420 * # The CoS queue index is obtained by applying modulo 10 to the
28421 * CoS queue ID. Valid CoS queue indexes are in the range of 0 to 7.
28422 * The CoS queue index is used to reference port statistics for the
28424 * # A value of 0xff indicates that the queue is not available.
28425 * # Available queues may not be in sequential order.
28428 /* This value specifies service profile kind for CoS queue */
28429 uint8_t queue_id6_service_profile;
28430 /* Lossy (best-effort) */
28431 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID6_SERVICE_PROFILE_LOSSY \
28434 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID6_SERVICE_PROFILE_LOSSLESS \
28436 /* Lossless RoCE (deprecated) */
28437 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID6_SERVICE_PROFILE_LOSSLESS_ROCE \
28439 /* Lossy RoCE CNP (deprecated) */
28440 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID6_SERVICE_PROFILE_LOSSY_ROCE_CNP \
28442 /* Lossless NIC (deprecated) */
28443 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID6_SERVICE_PROFILE_LOSSLESS_NIC \
28445 /* Set to 0xFF... (All Fs) if there is no service profile specified */
28446 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID6_SERVICE_PROFILE_UNKNOWN \
28448 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID6_SERVICE_PROFILE_LAST \
28449 HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID6_SERVICE_PROFILE_UNKNOWN
28451 * ID of CoS Queue 7.
28454 * # This ID can be used on any subsequent call to an hwrm command
28455 * that takes a queue id.
28456 * # IDs must always be queried by this command before any use
28457 * by the driver or software.
28458 * # The CoS queue index is obtained by applying modulo 10 to the
28459 * CoS queue ID. Valid CoS queue indexes are in the range of 0 to 7.
28460 * The CoS queue index is used to reference port statistics for the
28462 * # A value of 0xff indicates that the queue is not available.
28463 * # Available queues may not be in sequential order.
28466 /* This value specifies service profile kind for CoS queue */
28467 uint8_t queue_id7_service_profile;
28468 /* Lossy (best-effort) */
28469 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID7_SERVICE_PROFILE_LOSSY \
28472 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID7_SERVICE_PROFILE_LOSSLESS \
28474 /* Lossless RoCE (deprecated) */
28475 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID7_SERVICE_PROFILE_LOSSLESS_ROCE \
28477 /* Lossy RoCE CNP (deprecated) */
28478 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID7_SERVICE_PROFILE_LOSSY_ROCE_CNP \
28480 /* Lossless NIC (deprecated) */
28481 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID7_SERVICE_PROFILE_LOSSLESS_NIC \
28483 /* Set to 0xFF... (All Fs) if there is no service profile specified */
28484 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID7_SERVICE_PROFILE_UNKNOWN \
28486 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID7_SERVICE_PROFILE_LAST \
28487 HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID7_SERVICE_PROFILE_UNKNOWN
28489 * This value specifies traffic type for the service profile. We can
28490 * have a TC mapped to multiple traffic types. For example shared
28491 * CoS Q for CNP and NIC will have both cnp and nic bits set (0x6).
28492 * A value of zero is considered as invalid.
28494 uint8_t queue_id0_service_profile_type;
28495 /* Recommended to be used for RoCE traffic only. */
28496 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID0_SERVICE_PROFILE_TYPE_ROCE \
28498 /* Recommended to be used for NIC/L2 traffic only. */
28499 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID0_SERVICE_PROFILE_TYPE_NIC \
28501 /* Recommended to be used for CNP traffic only. */
28502 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID0_SERVICE_PROFILE_TYPE_CNP \
28505 * Up to 16 bytes of null padded ASCII string describing this queue.
28506 * The queue name includes a CoS queue index and, in some cases, text
28507 * that distinguishes the queue from other queues in the group.
28509 char qid0_name[16];
28510 /* Up to 16 bytes of null padded ASCII string describing this queue. */
28511 char qid1_name[16];
28512 /* Up to 16 bytes of null padded ASCII string describing this queue. */
28513 char qid2_name[16];
28514 /* Up to 16 bytes of null padded ASCII string describing this queue. */
28515 char qid3_name[16];
28516 /* Up to 16 bytes of null padded ASCII string describing this queue. */
28517 char qid4_name[16];
28518 /* Up to 16 bytes of null padded ASCII string describing this queue. */
28519 char qid5_name[16];
28520 /* Up to 16 bytes of null padded ASCII string describing this queue. */
28521 char qid6_name[16];
28522 /* Up to 16 bytes of null padded ASCII string describing this queue. */
28523 char qid7_name[16];
28525 * This value specifies traffic type for the service profile. We can
28526 * have a TC mapped to multiple traffic types. For example shared
28527 * CoS Q for CNP and NIC will have both cnp and nic bits set (0x6).
28528 * A value of zero is considered as invalid.
28530 uint8_t queue_id1_service_profile_type;
28531 /* Recommended to be used for RoCE traffic only. */
28532 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID1_SERVICE_PROFILE_TYPE_ROCE \
28534 /* Recommended to be used for NIC/L2 traffic only. */
28535 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID1_SERVICE_PROFILE_TYPE_NIC \
28537 /* Recommended to be used for CNP traffic only. */
28538 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID1_SERVICE_PROFILE_TYPE_CNP \
28541 * This value specifies traffic type for the service profile. We can
28542 * have a TC mapped to multiple traffic types. For example shared
28543 * CoS Q for CNP and NIC will have both cnp and nic bits set (0x6).
28544 * A value of zero is considered as invalid.
28546 uint8_t queue_id2_service_profile_type;
28547 /* Recommended to be used for RoCE traffic only. */
28548 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID2_SERVICE_PROFILE_TYPE_ROCE \
28550 /* Recommended to be used for NIC/L2 traffic only. */
28551 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID2_SERVICE_PROFILE_TYPE_NIC \
28553 /* Recommended to be used for CNP traffic only. */
28554 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID2_SERVICE_PROFILE_TYPE_CNP \
28557 * This value specifies traffic type for the service profile. We can
28558 * have a TC mapped to multiple traffic types. For example shared
28559 * CoS Q for CNP and NIC will have both cnp and nic bits set (0x6).
28560 * A value of zero is considered as invalid.
28562 uint8_t queue_id3_service_profile_type;
28563 /* Recommended to be used for RoCE traffic only. */
28564 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID3_SERVICE_PROFILE_TYPE_ROCE \
28566 /* Recommended to be used for NIC/L2 traffic only. */
28567 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID3_SERVICE_PROFILE_TYPE_NIC \
28569 /* Recommended to be used for CNP traffic only. */
28570 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID3_SERVICE_PROFILE_TYPE_CNP \
28573 * This value specifies traffic type for the service profile. We can
28574 * have a TC mapped to multiple traffic types. For example shared
28575 * CoS Q for CNP and NIC will have both cnp and nic bits set (0x6).
28576 * A value of zero is considered as invalid.
28578 uint8_t queue_id4_service_profile_type;
28579 /* Recommended to be used for RoCE traffic only. */
28580 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID4_SERVICE_PROFILE_TYPE_ROCE \
28582 /* Recommended to be used for NIC/L2 traffic only. */
28583 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID4_SERVICE_PROFILE_TYPE_NIC \
28585 /* Recommended to be used for CNP traffic only. */
28586 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID4_SERVICE_PROFILE_TYPE_CNP \
28589 * This value specifies traffic type for the service profile. We can
28590 * have a TC mapped to multiple traffic types. For example shared
28591 * CoS Q for CNP and NIC will have both cnp and nic bits set (0x6).
28592 * A value of zero is considered as invalid.
28594 uint8_t queue_id5_service_profile_type;
28595 /* Recommended to be used for RoCE traffic only. */
28596 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID5_SERVICE_PROFILE_TYPE_ROCE \
28598 /* Recommended to be used for NIC/L2 traffic only. */
28599 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID5_SERVICE_PROFILE_TYPE_NIC \
28601 /* Recommended to be used for CNP traffic only. */
28602 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID5_SERVICE_PROFILE_TYPE_CNP \
28605 * This value specifies traffic type for the service profile. We can
28606 * have a TC mapped to multiple traffic types. For example shared
28607 * CoS Q for CNP and NIC will have both cnp and nic bits set (0x6).
28608 * A value of zero is considered as invalid.
28610 uint8_t queue_id6_service_profile_type;
28611 /* Recommended to be used for RoCE traffic only. */
28612 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID6_SERVICE_PROFILE_TYPE_ROCE \
28614 /* Recommended to be used for NIC/L2 traffic only. */
28615 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID6_SERVICE_PROFILE_TYPE_NIC \
28617 /* Recommended to be used for CNP traffic only. */
28618 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID6_SERVICE_PROFILE_TYPE_CNP \
28621 * This value specifies traffic type for the service profile. We can
28622 * have a TC mapped to multiple traffic types. For example shared
28623 * CoS Q for CNP and NIC will have both cnp and nic bits set (0x6).
28624 * A value of zero is considered as invalid.
28626 uint8_t queue_id7_service_profile_type;
28627 /* Recommended to be used for RoCE traffic only. */
28628 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID7_SERVICE_PROFILE_TYPE_ROCE \
28630 /* Recommended to be used for NIC/L2 traffic only. */
28631 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID7_SERVICE_PROFILE_TYPE_NIC \
28633 /* Recommended to be used for CNP traffic only. */
28634 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID7_SERVICE_PROFILE_TYPE_CNP \
28637 * This field is used in Output records to indicate that the output
28638 * is completely written to RAM. This field should be read as '1'
28639 * to indicate that the output has been completely written.
28640 * When writing a command completion or response to an internal processor,
28641 * the order of writes has to be such that this field is written last.
28646 /*******************
28647 * hwrm_queue_qcfg *
28648 *******************/
28651 /* hwrm_queue_qcfg_input (size:192b/24B) */
28652 struct hwrm_queue_qcfg_input {
28653 /* The HWRM command request type. */
28656 * The completion ring to send the completion event on. This should
28657 * be the NQ ID returned from the `nq_alloc` HWRM command.
28659 uint16_t cmpl_ring;
28661 * The sequence ID is used by the driver for tracking multiple
28662 * commands. This ID is treated as opaque data by the firmware and
28663 * the value is returned in the `hwrm_resp_hdr` upon completion.
28667 * The target ID of the command:
28668 * * 0x0-0xFFF8 - The function ID
28669 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
28670 * * 0xFFFD - Reserved for user-space HWRM interface
28673 uint16_t target_id;
28675 * A physical address pointer pointing to a host buffer that the
28676 * command's response data will be written. This can be either a host
28677 * physical address (HPA) or a guest physical address (GPA) and must
28678 * point to a physically contiguous block of memory.
28680 uint64_t resp_addr;
28683 * Enumeration denoting the RX, TX type of the resource.
28684 * This enumeration is used for resources that are similar for both
28685 * TX and RX paths of the chip.
28687 #define HWRM_QUEUE_QCFG_INPUT_FLAGS_PATH UINT32_C(0x1)
28689 #define HWRM_QUEUE_QCFG_INPUT_FLAGS_PATH_TX UINT32_C(0x0)
28691 #define HWRM_QUEUE_QCFG_INPUT_FLAGS_PATH_RX UINT32_C(0x1)
28692 #define HWRM_QUEUE_QCFG_INPUT_FLAGS_PATH_LAST \
28693 HWRM_QUEUE_QCFG_INPUT_FLAGS_PATH_RX
28694 /* Queue ID of the queue. */
28698 /* hwrm_queue_qcfg_output (size:128b/16B) */
28699 struct hwrm_queue_qcfg_output {
28700 /* The specific error status for the command. */
28701 uint16_t error_code;
28702 /* The HWRM command request type. */
28704 /* The sequence ID from the original command. */
28706 /* The length of the response data in number of bytes. */
28709 * This value is the estimate packet length used in the
28712 uint32_t queue_len;
28713 /* This value is applicable to CoS queues only. */
28714 uint8_t service_profile;
28715 /* Lossy (best-effort) */
28716 #define HWRM_QUEUE_QCFG_OUTPUT_SERVICE_PROFILE_LOSSY UINT32_C(0x0)
28718 #define HWRM_QUEUE_QCFG_OUTPUT_SERVICE_PROFILE_LOSSLESS UINT32_C(0x1)
28719 /* Set to 0xFF... (All Fs) if there is no service profile specified */
28720 #define HWRM_QUEUE_QCFG_OUTPUT_SERVICE_PROFILE_UNKNOWN UINT32_C(0xff)
28721 #define HWRM_QUEUE_QCFG_OUTPUT_SERVICE_PROFILE_LAST \
28722 HWRM_QUEUE_QCFG_OUTPUT_SERVICE_PROFILE_UNKNOWN
28723 /* Information about queue configuration. */
28724 uint8_t queue_cfg_info;
28726 * If this flag is set to '1', then the queue is
28727 * configured asymmetrically on TX and RX sides.
28728 * If this flag is set to '0', then this queue is
28729 * configured symmetrically on TX and RX sides.
28731 #define HWRM_QUEUE_QCFG_OUTPUT_QUEUE_CFG_INFO_ASYM_CFG \
28735 * This field is used in Output records to indicate that the output
28736 * is completely written to RAM. This field should be read as '1'
28737 * to indicate that the output has been completely written.
28738 * When writing a command completion or response to an internal processor,
28739 * the order of writes has to be such that this field is written last.
28744 /******************
28746 ******************/
28749 /* hwrm_queue_cfg_input (size:320b/40B) */
28750 struct hwrm_queue_cfg_input {
28751 /* The HWRM command request type. */
28754 * The completion ring to send the completion event on. This should
28755 * be the NQ ID returned from the `nq_alloc` HWRM command.
28757 uint16_t cmpl_ring;
28759 * The sequence ID is used by the driver for tracking multiple
28760 * commands. This ID is treated as opaque data by the firmware and
28761 * the value is returned in the `hwrm_resp_hdr` upon completion.
28765 * The target ID of the command:
28766 * * 0x0-0xFFF8 - The function ID
28767 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
28768 * * 0xFFFD - Reserved for user-space HWRM interface
28771 uint16_t target_id;
28773 * A physical address pointer pointing to a host buffer that the
28774 * command's response data will be written. This can be either a host
28775 * physical address (HPA) or a guest physical address (GPA) and must
28776 * point to a physically contiguous block of memory.
28778 uint64_t resp_addr;
28781 * Enumeration denoting the RX, TX, or both directions applicable to the resource.
28782 * This enumeration is used for resources that are similar for both
28783 * TX and RX paths of the chip.
28785 #define HWRM_QUEUE_CFG_INPUT_FLAGS_PATH_MASK UINT32_C(0x3)
28786 #define HWRM_QUEUE_CFG_INPUT_FLAGS_PATH_SFT 0
28788 #define HWRM_QUEUE_CFG_INPUT_FLAGS_PATH_TX UINT32_C(0x0)
28790 #define HWRM_QUEUE_CFG_INPUT_FLAGS_PATH_RX UINT32_C(0x1)
28791 /* Bi-directional (Symmetrically applicable to TX and RX paths) */
28792 #define HWRM_QUEUE_CFG_INPUT_FLAGS_PATH_BIDIR UINT32_C(0x2)
28793 #define HWRM_QUEUE_CFG_INPUT_FLAGS_PATH_LAST \
28794 HWRM_QUEUE_CFG_INPUT_FLAGS_PATH_BIDIR
28797 * This bit must be '1' for the dflt_len field to be
28800 #define HWRM_QUEUE_CFG_INPUT_ENABLES_DFLT_LEN UINT32_C(0x1)
28802 * This bit must be '1' for the service_profile field to be
28805 #define HWRM_QUEUE_CFG_INPUT_ENABLES_SERVICE_PROFILE UINT32_C(0x2)
28806 /* Queue ID of queue that is to be configured by this function. */
28809 * This value is a the estimate packet length used in the
28811 * Set to 0xFF... (All Fs) to not adjust this value.
28814 /* This value is applicable to CoS queues only. */
28815 uint8_t service_profile;
28816 /* Lossy (best-effort) */
28817 #define HWRM_QUEUE_CFG_INPUT_SERVICE_PROFILE_LOSSY UINT32_C(0x0)
28819 #define HWRM_QUEUE_CFG_INPUT_SERVICE_PROFILE_LOSSLESS UINT32_C(0x1)
28820 /* Set to 0xFF... (All Fs) if there is no service profile specified */
28821 #define HWRM_QUEUE_CFG_INPUT_SERVICE_PROFILE_UNKNOWN UINT32_C(0xff)
28822 #define HWRM_QUEUE_CFG_INPUT_SERVICE_PROFILE_LAST \
28823 HWRM_QUEUE_CFG_INPUT_SERVICE_PROFILE_UNKNOWN
28824 uint8_t unused_0[7];
28827 /* hwrm_queue_cfg_output (size:128b/16B) */
28828 struct hwrm_queue_cfg_output {
28829 /* The specific error status for the command. */
28830 uint16_t error_code;
28831 /* The HWRM command request type. */
28833 /* The sequence ID from the original command. */
28835 /* The length of the response data in number of bytes. */
28837 uint8_t unused_0[7];
28839 * This field is used in Output records to indicate that the output
28840 * is completely written to RAM. This field should be read as '1'
28841 * to indicate that the output has been completely written.
28842 * When writing a command completion or response to an internal processor,
28843 * the order of writes has to be such that this field is written last.
28848 /*****************************
28849 * hwrm_queue_pfcenable_qcfg *
28850 *****************************/
28853 /* hwrm_queue_pfcenable_qcfg_input (size:192b/24B) */
28854 struct hwrm_queue_pfcenable_qcfg_input {
28855 /* The HWRM command request type. */
28858 * The completion ring to send the completion event on. This should
28859 * be the NQ ID returned from the `nq_alloc` HWRM command.
28861 uint16_t cmpl_ring;
28863 * The sequence ID is used by the driver for tracking multiple
28864 * commands. This ID is treated as opaque data by the firmware and
28865 * the value is returned in the `hwrm_resp_hdr` upon completion.
28869 * The target ID of the command:
28870 * * 0x0-0xFFF8 - The function ID
28871 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
28872 * * 0xFFFD - Reserved for user-space HWRM interface
28875 uint16_t target_id;
28877 * A physical address pointer pointing to a host buffer that the
28878 * command's response data will be written. This can be either a host
28879 * physical address (HPA) or a guest physical address (GPA) and must
28880 * point to a physically contiguous block of memory.
28882 uint64_t resp_addr;
28884 * Port ID of port for which the table is being configured.
28885 * The HWRM needs to check whether this function is allowed
28886 * to configure pri2cos mapping on this port.
28889 uint8_t unused_0[6];
28892 /* hwrm_queue_pfcenable_qcfg_output (size:128b/16B) */
28893 struct hwrm_queue_pfcenable_qcfg_output {
28894 /* The specific error status for the command. */
28895 uint16_t error_code;
28896 /* The HWRM command request type. */
28898 /* The sequence ID from the original command. */
28900 /* The length of the response data in number of bytes. */
28903 /* If set to 1, then PFC is enabled on PRI 0. */
28904 #define HWRM_QUEUE_PFCENABLE_QCFG_OUTPUT_FLAGS_PRI0_PFC_ENABLED \
28906 /* If set to 1, then PFC is enabled on PRI 1. */
28907 #define HWRM_QUEUE_PFCENABLE_QCFG_OUTPUT_FLAGS_PRI1_PFC_ENABLED \
28909 /* If set to 1, then PFC is enabled on PRI 2. */
28910 #define HWRM_QUEUE_PFCENABLE_QCFG_OUTPUT_FLAGS_PRI2_PFC_ENABLED \
28912 /* If set to 1, then PFC is enabled on PRI 3. */
28913 #define HWRM_QUEUE_PFCENABLE_QCFG_OUTPUT_FLAGS_PRI3_PFC_ENABLED \
28915 /* If set to 1, then PFC is enabled on PRI 4. */
28916 #define HWRM_QUEUE_PFCENABLE_QCFG_OUTPUT_FLAGS_PRI4_PFC_ENABLED \
28918 /* If set to 1, then PFC is enabled on PRI 5. */
28919 #define HWRM_QUEUE_PFCENABLE_QCFG_OUTPUT_FLAGS_PRI5_PFC_ENABLED \
28921 /* If set to 1, then PFC is enabled on PRI 6. */
28922 #define HWRM_QUEUE_PFCENABLE_QCFG_OUTPUT_FLAGS_PRI6_PFC_ENABLED \
28924 /* If set to 1, then PFC is enabled on PRI 7. */
28925 #define HWRM_QUEUE_PFCENABLE_QCFG_OUTPUT_FLAGS_PRI7_PFC_ENABLED \
28927 /* If set to 1, then PFC WatchDog is requested to be enabled on PRI0. */
28928 #define HWRM_QUEUE_PFCENABLE_QCFG_OUTPUT_FLAGS_PRI0_PFC_WATCHDOG_ENABLED \
28930 /* If set to 1, then PFC WatchDog is requested to be enabled on PRI1. */
28931 #define HWRM_QUEUE_PFCENABLE_QCFG_OUTPUT_FLAGS_PRI1_PFC_WATCHDOG_ENABLED \
28933 /* If set to 1, then PFC WatchDog is requested to be enabled on PRI2. */
28934 #define HWRM_QUEUE_PFCENABLE_QCFG_OUTPUT_FLAGS_PRI2_PFC_WATCHDOG_ENABLED \
28936 /* If set to 1, then PFC WatchDog is requested to be enabled on PRI3. */
28937 #define HWRM_QUEUE_PFCENABLE_QCFG_OUTPUT_FLAGS_PRI3_PFC_WATCHDOG_ENABLED \
28939 /* If set to 1, then PFC WatchDog is requested to be enabled on PRI4. */
28940 #define HWRM_QUEUE_PFCENABLE_QCFG_OUTPUT_FLAGS_PRI4_PFC_WATCHDOG_ENABLED \
28942 /* If set to 1, then PFC WatchDog is requested to be enabled on PRI5. */
28943 #define HWRM_QUEUE_PFCENABLE_QCFG_OUTPUT_FLAGS_PRI5_PFC_WATCHDOG_ENABLED \
28945 /* If set to 1, then PFC WatchDog is requested to be enabled on PRI6. */
28946 #define HWRM_QUEUE_PFCENABLE_QCFG_OUTPUT_FLAGS_PRI6_PFC_WATCHDOG_ENABLED \
28948 /* If set to 1, then PFC WatchDog is requested to be enabled on PRI7. */
28949 #define HWRM_QUEUE_PFCENABLE_QCFG_OUTPUT_FLAGS_PRI7_PFC_WATCHDOG_ENABLED \
28951 uint8_t unused_0[3];
28953 * This field is used in Output records to indicate that the output
28954 * is completely written to RAM. This field should be read as '1'
28955 * to indicate that the output has been completely written.
28956 * When writing a command completion or response to an internal processor,
28957 * the order of writes has to be such that this field is written last.
28962 /****************************
28963 * hwrm_queue_pfcenable_cfg *
28964 ****************************/
28967 /* hwrm_queue_pfcenable_cfg_input (size:192b/24B) */
28968 struct hwrm_queue_pfcenable_cfg_input {
28969 /* The HWRM command request type. */
28972 * The completion ring to send the completion event on. This should
28973 * be the NQ ID returned from the `nq_alloc` HWRM command.
28975 uint16_t cmpl_ring;
28977 * The sequence ID is used by the driver for tracking multiple
28978 * commands. This ID is treated as opaque data by the firmware and
28979 * the value is returned in the `hwrm_resp_hdr` upon completion.
28983 * The target ID of the command:
28984 * * 0x0-0xFFF8 - The function ID
28985 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
28986 * * 0xFFFD - Reserved for user-space HWRM interface
28989 uint16_t target_id;
28991 * A physical address pointer pointing to a host buffer that the
28992 * command's response data will be written. This can be either a host
28993 * physical address (HPA) or a guest physical address (GPA) and must
28994 * point to a physically contiguous block of memory.
28996 uint64_t resp_addr;
28998 /* If set to 1, then PFC is requested to be enabled on PRI 0. */
28999 #define HWRM_QUEUE_PFCENABLE_CFG_INPUT_FLAGS_PRI0_PFC_ENABLED \
29001 /* If set to 1, then PFC is requested to be enabled on PRI 1. */
29002 #define HWRM_QUEUE_PFCENABLE_CFG_INPUT_FLAGS_PRI1_PFC_ENABLED \
29004 /* If set to 1, then PFC is requested to be enabled on PRI 2. */
29005 #define HWRM_QUEUE_PFCENABLE_CFG_INPUT_FLAGS_PRI2_PFC_ENABLED \
29007 /* If set to 1, then PFC is requested to be enabled on PRI 3. */
29008 #define HWRM_QUEUE_PFCENABLE_CFG_INPUT_FLAGS_PRI3_PFC_ENABLED \
29010 /* If set to 1, then PFC is requested to be enabled on PRI 4. */
29011 #define HWRM_QUEUE_PFCENABLE_CFG_INPUT_FLAGS_PRI4_PFC_ENABLED \
29013 /* If set to 1, then PFC is requested to be enabled on PRI 5. */
29014 #define HWRM_QUEUE_PFCENABLE_CFG_INPUT_FLAGS_PRI5_PFC_ENABLED \
29016 /* If set to 1, then PFC is requested to be enabled on PRI 6. */
29017 #define HWRM_QUEUE_PFCENABLE_CFG_INPUT_FLAGS_PRI6_PFC_ENABLED \
29019 /* If set to 1, then PFC is requested to be enabled on PRI 7. */
29020 #define HWRM_QUEUE_PFCENABLE_CFG_INPUT_FLAGS_PRI7_PFC_ENABLED \
29022 /* If set to 1, then PFC WatchDog is requested to be enabled on PRI0. */
29023 #define HWRM_QUEUE_PFCENABLE_CFG_INPUT_FLAGS_PRI0_PFC_WATCHDOG_ENABLED \
29025 /* If set to 1, then PFC WatchDog is requested to be enabled on PRI1. */
29026 #define HWRM_QUEUE_PFCENABLE_CFG_INPUT_FLAGS_PRI1_PFC_WATCHDOG_ENABLED \
29028 /* If set to 1, then PFC WatchDog is requested to be enabled on PRI2. */
29029 #define HWRM_QUEUE_PFCENABLE_CFG_INPUT_FLAGS_PRI2_PFC_WATCHDOG_ENABLED \
29031 /* If set to 1, then PFC WatchDog is requested to be enabled on PRI3. */
29032 #define HWRM_QUEUE_PFCENABLE_CFG_INPUT_FLAGS_PRI3_PFC_WATCHDOG_ENABLED \
29034 /* If set to 1, then PFC WatchDog is requested to be enabled on PRI4. */
29035 #define HWRM_QUEUE_PFCENABLE_CFG_INPUT_FLAGS_PRI4_PFC_WATCHDOG_ENABLED \
29037 /* If set to 1, then PFC WatchDog is requested to be enabled on PRI5. */
29038 #define HWRM_QUEUE_PFCENABLE_CFG_INPUT_FLAGS_PRI5_PFC_WATCHDOG_ENABLED \
29040 /* If set to 1, then PFC WatchDog is requested to be enabled on PRI6. */
29041 #define HWRM_QUEUE_PFCENABLE_CFG_INPUT_FLAGS_PRI6_PFC_WATCHDOG_ENABLED \
29043 /* If set to 1, then PFC WatchDog is requested to be enabled on PRI7. */
29044 #define HWRM_QUEUE_PFCENABLE_CFG_INPUT_FLAGS_PRI7_PFC_WATCHDOG_ENABLED \
29047 * Port ID of port for which the table is being configured.
29048 * The HWRM needs to check whether this function is allowed
29049 * to configure pri2cos mapping on this port.
29052 uint8_t unused_0[2];
29055 /* hwrm_queue_pfcenable_cfg_output (size:128b/16B) */
29056 struct hwrm_queue_pfcenable_cfg_output {
29057 /* The specific error status for the command. */
29058 uint16_t error_code;
29059 /* The HWRM command request type. */
29061 /* The sequence ID from the original command. */
29063 /* The length of the response data in number of bytes. */
29065 uint8_t unused_0[7];
29067 * This field is used in Output records to indicate that the output
29068 * is completely written to RAM. This field should be read as '1'
29069 * to indicate that the output has been completely written.
29070 * When writing a command completion or response to an internal processor,
29071 * the order of writes has to be such that this field is written last.
29076 /***************************
29077 * hwrm_queue_pri2cos_qcfg *
29078 ***************************/
29081 /* hwrm_queue_pri2cos_qcfg_input (size:192b/24B) */
29082 struct hwrm_queue_pri2cos_qcfg_input {
29083 /* The HWRM command request type. */
29086 * The completion ring to send the completion event on. This should
29087 * be the NQ ID returned from the `nq_alloc` HWRM command.
29089 uint16_t cmpl_ring;
29091 * The sequence ID is used by the driver for tracking multiple
29092 * commands. This ID is treated as opaque data by the firmware and
29093 * the value is returned in the `hwrm_resp_hdr` upon completion.
29097 * The target ID of the command:
29098 * * 0x0-0xFFF8 - The function ID
29099 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
29100 * * 0xFFFD - Reserved for user-space HWRM interface
29103 uint16_t target_id;
29105 * A physical address pointer pointing to a host buffer that the
29106 * command's response data will be written. This can be either a host
29107 * physical address (HPA) or a guest physical address (GPA) and must
29108 * point to a physically contiguous block of memory.
29110 uint64_t resp_addr;
29113 * Enumeration denoting the RX, TX type of the resource.
29114 * This enumeration is used for resources that are similar for both
29115 * TX and RX paths of the chip.
29117 #define HWRM_QUEUE_PRI2COS_QCFG_INPUT_FLAGS_PATH UINT32_C(0x1)
29119 #define HWRM_QUEUE_PRI2COS_QCFG_INPUT_FLAGS_PATH_TX UINT32_C(0x0)
29121 #define HWRM_QUEUE_PRI2COS_QCFG_INPUT_FLAGS_PATH_RX UINT32_C(0x1)
29122 #define HWRM_QUEUE_PRI2COS_QCFG_INPUT_FLAGS_PATH_LAST \
29123 HWRM_QUEUE_PRI2COS_QCFG_INPUT_FLAGS_PATH_RX
29125 * When this bit is set to '0', the query is
29126 * for PRI from tunnel headers.
29127 * When this bit is set to '1', the query is
29128 * for PRI from inner packet headers.
29130 #define HWRM_QUEUE_PRI2COS_QCFG_INPUT_FLAGS_IVLAN UINT32_C(0x2)
29132 * Port ID of port for which the table is being configured.
29133 * The HWRM needs to check whether this function is allowed
29134 * to configure pri2cos mapping on this port.
29137 uint8_t unused_0[3];
29140 /* hwrm_queue_pri2cos_qcfg_output (size:192b/24B) */
29141 struct hwrm_queue_pri2cos_qcfg_output {
29142 /* The specific error status for the command. */
29143 uint16_t error_code;
29144 /* The HWRM command request type. */
29146 /* The sequence ID from the original command. */
29148 /* The length of the response data in number of bytes. */
29151 * CoS Queue assigned to priority 0. This value can only
29152 * be changed before traffic has started.
29153 * A value of 0xff indicates that no CoS queue is assigned to the
29154 * specified priority.
29156 uint8_t pri0_cos_queue_id;
29158 * CoS Queue assigned to priority 1. This value can only
29159 * be changed before traffic has started.
29160 * A value of 0xff indicates that no CoS queue is assigned to the
29161 * specified priority.
29163 uint8_t pri1_cos_queue_id;
29165 * CoS Queue assigned to priority 2. This value can only
29166 * be changed before traffic has started.
29167 * A value of 0xff indicates that no CoS queue is assigned to the
29168 * specified priority.
29170 uint8_t pri2_cos_queue_id;
29172 * CoS Queue assigned to priority 3. This value can only
29173 * be changed before traffic has started.
29174 * A value of 0xff indicates that no CoS queue is assigned to the
29175 * specified priority.
29177 uint8_t pri3_cos_queue_id;
29179 * CoS Queue assigned to priority 4. This value can only
29180 * be changed before traffic has started.
29181 * A value of 0xff indicates that no CoS queue is assigned to the
29182 * specified priority.
29184 uint8_t pri4_cos_queue_id;
29186 * CoS Queue assigned to priority 5. This value can only
29187 * be changed before traffic has started.
29188 * A value of 0xff indicates that no CoS queue is assigned to the
29189 * specified priority.
29191 uint8_t pri5_cos_queue_id;
29193 * CoS Queue assigned to priority 6. This value can only
29194 * be changed before traffic has started.
29195 * A value of 0xff indicates that no CoS queue is assigned to the
29196 * specified priority.
29198 uint8_t pri6_cos_queue_id;
29200 * CoS Queue assigned to priority 7. This value can only
29201 * be changed before traffic has started.
29202 * A value of 0xff indicates that no CoS queue is assigned to the
29203 * specified priority.
29205 uint8_t pri7_cos_queue_id;
29206 /* Information about queue configuration. */
29207 uint8_t queue_cfg_info;
29209 * If this flag is set to '1', then the PRI to CoS
29210 * configuration is asymmetric on TX and RX sides.
29211 * If this flag is set to '0', then PRI to CoS configuration
29212 * is symmetric on TX and RX sides.
29214 #define HWRM_QUEUE_PRI2COS_QCFG_OUTPUT_QUEUE_CFG_INFO_ASYM_CFG \
29216 uint8_t unused_0[6];
29218 * This field is used in Output records to indicate that the output
29219 * is completely written to RAM. This field should be read as '1'
29220 * to indicate that the output has been completely written.
29221 * When writing a command completion or response to an internal processor,
29222 * the order of writes has to be such that this field is written last.
29227 /**************************
29228 * hwrm_queue_pri2cos_cfg *
29229 **************************/
29232 /* hwrm_queue_pri2cos_cfg_input (size:320b/40B) */
29233 struct hwrm_queue_pri2cos_cfg_input {
29234 /* The HWRM command request type. */
29237 * The completion ring to send the completion event on. This should
29238 * be the NQ ID returned from the `nq_alloc` HWRM command.
29240 uint16_t cmpl_ring;
29242 * The sequence ID is used by the driver for tracking multiple
29243 * commands. This ID is treated as opaque data by the firmware and
29244 * the value is returned in the `hwrm_resp_hdr` upon completion.
29248 * The target ID of the command:
29249 * * 0x0-0xFFF8 - The function ID
29250 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
29251 * * 0xFFFD - Reserved for user-space HWRM interface
29254 uint16_t target_id;
29256 * A physical address pointer pointing to a host buffer that the
29257 * command's response data will be written. This can be either a host
29258 * physical address (HPA) or a guest physical address (GPA) and must
29259 * point to a physically contiguous block of memory.
29261 uint64_t resp_addr;
29264 * Enumeration denoting the RX, TX, or both directions applicable to the resource.
29265 * This enumeration is used for resources that are similar for both
29266 * TX and RX paths of the chip.
29268 #define HWRM_QUEUE_PRI2COS_CFG_INPUT_FLAGS_PATH_MASK UINT32_C(0x3)
29269 #define HWRM_QUEUE_PRI2COS_CFG_INPUT_FLAGS_PATH_SFT 0
29271 #define HWRM_QUEUE_PRI2COS_CFG_INPUT_FLAGS_PATH_TX UINT32_C(0x0)
29273 #define HWRM_QUEUE_PRI2COS_CFG_INPUT_FLAGS_PATH_RX UINT32_C(0x1)
29274 /* Bi-directional (Symmetrically applicable to TX and RX paths) */
29275 #define HWRM_QUEUE_PRI2COS_CFG_INPUT_FLAGS_PATH_BIDIR UINT32_C(0x2)
29276 #define HWRM_QUEUE_PRI2COS_CFG_INPUT_FLAGS_PATH_LAST \
29277 HWRM_QUEUE_PRI2COS_CFG_INPUT_FLAGS_PATH_BIDIR
29279 * When this bit is set to '0', the mapping is requested
29280 * for PRI from tunnel headers.
29281 * When this bit is set to '1', the mapping is requested
29282 * for PRI from inner packet headers.
29284 #define HWRM_QUEUE_PRI2COS_CFG_INPUT_FLAGS_IVLAN UINT32_C(0x4)
29287 * This bit must be '1' for the pri0_cos_queue_id field to be
29290 #define HWRM_QUEUE_PRI2COS_CFG_INPUT_ENABLES_PRI0_COS_QUEUE_ID \
29293 * This bit must be '1' for the pri1_cos_queue_id field to be
29296 #define HWRM_QUEUE_PRI2COS_CFG_INPUT_ENABLES_PRI1_COS_QUEUE_ID \
29299 * This bit must be '1' for the pri2_cos_queue_id field to be
29302 #define HWRM_QUEUE_PRI2COS_CFG_INPUT_ENABLES_PRI2_COS_QUEUE_ID \
29305 * This bit must be '1' for the pri3_cos_queue_id field to be
29308 #define HWRM_QUEUE_PRI2COS_CFG_INPUT_ENABLES_PRI3_COS_QUEUE_ID \
29311 * This bit must be '1' for the pri4_cos_queue_id field to be
29314 #define HWRM_QUEUE_PRI2COS_CFG_INPUT_ENABLES_PRI4_COS_QUEUE_ID \
29317 * This bit must be '1' for the pri5_cos_queue_id field to be
29320 #define HWRM_QUEUE_PRI2COS_CFG_INPUT_ENABLES_PRI5_COS_QUEUE_ID \
29323 * This bit must be '1' for the pri6_cos_queue_id field to be
29326 #define HWRM_QUEUE_PRI2COS_CFG_INPUT_ENABLES_PRI6_COS_QUEUE_ID \
29329 * This bit must be '1' for the pri7_cos_queue_id field to be
29332 #define HWRM_QUEUE_PRI2COS_CFG_INPUT_ENABLES_PRI7_COS_QUEUE_ID \
29335 * Port ID of port for which the table is being configured.
29336 * The HWRM needs to check whether this function is allowed
29337 * to configure pri2cos mapping on this port.
29341 * CoS Queue assigned to priority 0. This value can only
29342 * be changed before traffic has started.
29344 uint8_t pri0_cos_queue_id;
29346 * CoS Queue assigned to priority 1. This value can only
29347 * be changed before traffic has started.
29349 uint8_t pri1_cos_queue_id;
29351 * CoS Queue assigned to priority 2 This value can only
29352 * be changed before traffic has started.
29354 uint8_t pri2_cos_queue_id;
29356 * CoS Queue assigned to priority 3. This value can only
29357 * be changed before traffic has started.
29359 uint8_t pri3_cos_queue_id;
29361 * CoS Queue assigned to priority 4. This value can only
29362 * be changed before traffic has started.
29364 uint8_t pri4_cos_queue_id;
29366 * CoS Queue assigned to priority 5. This value can only
29367 * be changed before traffic has started.
29369 uint8_t pri5_cos_queue_id;
29371 * CoS Queue assigned to priority 6. This value can only
29372 * be changed before traffic has started.
29374 uint8_t pri6_cos_queue_id;
29376 * CoS Queue assigned to priority 7. This value can only
29377 * be changed before traffic has started.
29379 uint8_t pri7_cos_queue_id;
29380 uint8_t unused_0[7];
29383 /* hwrm_queue_pri2cos_cfg_output (size:128b/16B) */
29384 struct hwrm_queue_pri2cos_cfg_output {
29385 /* The specific error status for the command. */
29386 uint16_t error_code;
29387 /* The HWRM command request type. */
29389 /* The sequence ID from the original command. */
29391 /* The length of the response data in number of bytes. */
29393 uint8_t unused_0[7];
29395 * This field is used in Output records to indicate that the output
29396 * is completely written to RAM. This field should be read as '1'
29397 * to indicate that the output has been completely written.
29398 * When writing a command completion or response to an internal processor,
29399 * the order of writes has to be such that this field is written last.
29404 /**************************
29405 * hwrm_queue_cos2bw_qcfg *
29406 **************************/
29409 /* hwrm_queue_cos2bw_qcfg_input (size:192b/24B) */
29410 struct hwrm_queue_cos2bw_qcfg_input {
29411 /* The HWRM command request type. */
29414 * The completion ring to send the completion event on. This should
29415 * be the NQ ID returned from the `nq_alloc` HWRM command.
29417 uint16_t cmpl_ring;
29419 * The sequence ID is used by the driver for tracking multiple
29420 * commands. This ID is treated as opaque data by the firmware and
29421 * the value is returned in the `hwrm_resp_hdr` upon completion.
29425 * The target ID of the command:
29426 * * 0x0-0xFFF8 - The function ID
29427 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
29428 * * 0xFFFD - Reserved for user-space HWRM interface
29431 uint16_t target_id;
29433 * A physical address pointer pointing to a host buffer that the
29434 * command's response data will be written. This can be either a host
29435 * physical address (HPA) or a guest physical address (GPA) and must
29436 * point to a physically contiguous block of memory.
29438 uint64_t resp_addr;
29440 * Port ID of port for which the table is being configured.
29441 * The HWRM needs to check whether this function is allowed
29442 * to configure TC BW assignment on this port.
29445 uint8_t unused_0[6];
29448 /* hwrm_queue_cos2bw_qcfg_output (size:896b/112B) */
29449 struct hwrm_queue_cos2bw_qcfg_output {
29450 /* The specific error status for the command. */
29451 uint16_t error_code;
29452 /* The HWRM command request type. */
29454 /* The sequence ID from the original command. */
29456 /* The length of the response data in number of bytes. */
29458 /* ID of CoS Queue 0. */
29463 * Minimum BW allocated to CoS Queue.
29464 * The HWRM will translate this value into byte counter and
29465 * time interval used for this COS inside the device.
29467 uint32_t queue_id0_min_bw;
29468 /* The bandwidth value. */
29469 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MIN_BW_BW_VALUE_MASK \
29470 UINT32_C(0xfffffff)
29471 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MIN_BW_BW_VALUE_SFT \
29473 /* The granularity of the value (bits or bytes). */
29474 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MIN_BW_SCALE \
29475 UINT32_C(0x10000000)
29476 /* Value is in bits. */
29477 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MIN_BW_SCALE_BITS \
29478 (UINT32_C(0x0) << 28)
29479 /* Value is in bytes. */
29480 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MIN_BW_SCALE_BYTES \
29481 (UINT32_C(0x1) << 28)
29482 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MIN_BW_SCALE_LAST \
29483 HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MIN_BW_SCALE_BYTES
29484 /* bw_value_unit is 3 b */
29485 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_MASK \
29486 UINT32_C(0xe0000000)
29487 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_SFT \
29489 /* Value is in Mb or MB (base 10). */
29490 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_MEGA \
29491 (UINT32_C(0x0) << 29)
29492 /* Value is in Kb or KB (base 10). */
29493 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_KILO \
29494 (UINT32_C(0x2) << 29)
29495 /* Value is in bits or bytes. */
29496 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_BASE \
29497 (UINT32_C(0x4) << 29)
29498 /* Value is in Gb or GB (base 10). */
29499 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_GIGA \
29500 (UINT32_C(0x6) << 29)
29501 /* Value is in 1/100th of a percentage of total bandwidth. */
29502 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 \
29503 (UINT32_C(0x1) << 29)
29505 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_INVALID \
29506 (UINT32_C(0x7) << 29)
29507 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_LAST \
29508 HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_INVALID
29510 * Maximum BW allocated to CoS Queue.
29511 * The HWRM will translate this value into byte counter and
29512 * time interval used for this COS inside the device.
29514 uint32_t queue_id0_max_bw;
29515 /* The bandwidth value. */
29516 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MAX_BW_BW_VALUE_MASK \
29517 UINT32_C(0xfffffff)
29518 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MAX_BW_BW_VALUE_SFT \
29520 /* The granularity of the value (bits or bytes). */
29521 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MAX_BW_SCALE \
29522 UINT32_C(0x10000000)
29523 /* Value is in bits. */
29524 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MAX_BW_SCALE_BITS \
29525 (UINT32_C(0x0) << 28)
29526 /* Value is in bytes. */
29527 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MAX_BW_SCALE_BYTES \
29528 (UINT32_C(0x1) << 28)
29529 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MAX_BW_SCALE_LAST \
29530 HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MAX_BW_SCALE_BYTES
29531 /* bw_value_unit is 3 b */
29532 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_MASK \
29533 UINT32_C(0xe0000000)
29534 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_SFT \
29536 /* Value is in Mb or MB (base 10). */
29537 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_MEGA \
29538 (UINT32_C(0x0) << 29)
29539 /* Value is in Kb or KB (base 10). */
29540 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_KILO \
29541 (UINT32_C(0x2) << 29)
29542 /* Value is in bits or bytes. */
29543 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_BASE \
29544 (UINT32_C(0x4) << 29)
29545 /* Value is in Gb or GB (base 10). */
29546 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_GIGA \
29547 (UINT32_C(0x6) << 29)
29548 /* Value is in 1/100th of a percentage of total bandwidth. */
29549 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 \
29550 (UINT32_C(0x1) << 29)
29552 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_INVALID \
29553 (UINT32_C(0x7) << 29)
29554 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_LAST \
29555 HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_INVALID
29556 /* Transmission Selection Algorithm (TSA) for CoS Queue. */
29557 uint8_t queue_id0_tsa_assign;
29558 /* Strict Priority */
29559 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_TSA_ASSIGN_SP \
29561 /* Enhanced Transmission Selection */
29562 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_TSA_ASSIGN_ETS \
29565 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_TSA_ASSIGN_RESERVED_FIRST \
29568 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_TSA_ASSIGN_RESERVED_LAST \
29571 * Priority level for strict priority. Valid only when the
29572 * tsa_assign is 0 - Strict Priority (SP)
29573 * 0..7 - Valid values.
29574 * 8..255 - Reserved.
29576 uint8_t queue_id0_pri_lvl;
29578 * Weight used to allocate remaining BW for this COS after
29579 * servicing guaranteed bandwidths for all COS.
29581 uint8_t queue_id0_bw_weight;
29582 /* ID of CoS Queue 1. */
29585 * Minimum BW allocated to CoS Queue.
29586 * The HWRM will translate this value into byte counter and
29587 * time interval used for this COS inside the device.
29589 uint32_t queue_id1_min_bw;
29590 /* The bandwidth value. */
29591 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MIN_BW_BW_VALUE_MASK \
29592 UINT32_C(0xfffffff)
29593 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MIN_BW_BW_VALUE_SFT \
29595 /* The granularity of the value (bits or bytes). */
29596 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MIN_BW_SCALE \
29597 UINT32_C(0x10000000)
29598 /* Value is in bits. */
29599 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MIN_BW_SCALE_BITS \
29600 (UINT32_C(0x0) << 28)
29601 /* Value is in bytes. */
29602 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MIN_BW_SCALE_BYTES \
29603 (UINT32_C(0x1) << 28)
29604 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MIN_BW_SCALE_LAST \
29605 HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MIN_BW_SCALE_BYTES
29606 /* bw_value_unit is 3 b */
29607 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_MASK \
29608 UINT32_C(0xe0000000)
29609 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_SFT \
29611 /* Value is in Mb or MB (base 10). */
29612 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_MEGA \
29613 (UINT32_C(0x0) << 29)
29614 /* Value is in Kb or KB (base 10). */
29615 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_KILO \
29616 (UINT32_C(0x2) << 29)
29617 /* Value is in bits or bytes. */
29618 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_BASE \
29619 (UINT32_C(0x4) << 29)
29620 /* Value is in Gb or GB (base 10). */
29621 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_GIGA \
29622 (UINT32_C(0x6) << 29)
29623 /* Value is in 1/100th of a percentage of total bandwidth. */
29624 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 \
29625 (UINT32_C(0x1) << 29)
29627 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_INVALID \
29628 (UINT32_C(0x7) << 29)
29629 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_LAST \
29630 HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_INVALID
29632 * Maximum BW allocated to CoS queue.
29633 * The HWRM will translate this value into byte counter and
29634 * time interval used for this COS inside the device.
29636 uint32_t queue_id1_max_bw;
29637 /* The bandwidth value. */
29638 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MAX_BW_BW_VALUE_MASK \
29639 UINT32_C(0xfffffff)
29640 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MAX_BW_BW_VALUE_SFT \
29642 /* The granularity of the value (bits or bytes). */
29643 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MAX_BW_SCALE \
29644 UINT32_C(0x10000000)
29645 /* Value is in bits. */
29646 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MAX_BW_SCALE_BITS \
29647 (UINT32_C(0x0) << 28)
29648 /* Value is in bytes. */
29649 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MAX_BW_SCALE_BYTES \
29650 (UINT32_C(0x1) << 28)
29651 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MAX_BW_SCALE_LAST \
29652 HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MAX_BW_SCALE_BYTES
29653 /* bw_value_unit is 3 b */
29654 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_MASK \
29655 UINT32_C(0xe0000000)
29656 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_SFT \
29658 /* Value is in Mb or MB (base 10). */
29659 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_MEGA \
29660 (UINT32_C(0x0) << 29)
29661 /* Value is in Kb or KB (base 10). */
29662 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_KILO \
29663 (UINT32_C(0x2) << 29)
29664 /* Value is in bits or bytes. */
29665 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_BASE \
29666 (UINT32_C(0x4) << 29)
29667 /* Value is in Gb or GB (base 10). */
29668 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_GIGA \
29669 (UINT32_C(0x6) << 29)
29670 /* Value is in 1/100th of a percentage of total bandwidth. */
29671 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 \
29672 (UINT32_C(0x1) << 29)
29674 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_INVALID \
29675 (UINT32_C(0x7) << 29)
29676 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_LAST \
29677 HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_INVALID
29678 /* Transmission Selection Algorithm (TSA) for CoS Queue. */
29679 uint8_t queue_id1_tsa_assign;
29680 /* Strict Priority */
29681 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_TSA_ASSIGN_SP \
29683 /* Enhanced Transmission Selection */
29684 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_TSA_ASSIGN_ETS \
29687 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_TSA_ASSIGN_RESERVED_FIRST \
29690 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_TSA_ASSIGN_RESERVED_LAST \
29693 * Priority level for strict priority. Valid only when the
29694 * tsa_assign is 0 - Strict Priority (SP)
29695 * 0..7 - Valid values.
29696 * 8..255 - Reserved.
29698 uint8_t queue_id1_pri_lvl;
29700 * Weight used to allocate remaining BW for this COS after
29701 * servicing guaranteed bandwidths for all COS.
29703 uint8_t queue_id1_bw_weight;
29704 /* ID of CoS Queue 2. */
29707 * Minimum BW allocated to CoS Queue.
29708 * The HWRM will translate this value into byte counter and
29709 * time interval used for this COS inside the device.
29711 uint32_t queue_id2_min_bw;
29712 /* The bandwidth value. */
29713 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MIN_BW_BW_VALUE_MASK \
29714 UINT32_C(0xfffffff)
29715 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MIN_BW_BW_VALUE_SFT \
29717 /* The granularity of the value (bits or bytes). */
29718 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MIN_BW_SCALE \
29719 UINT32_C(0x10000000)
29720 /* Value is in bits. */
29721 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MIN_BW_SCALE_BITS \
29722 (UINT32_C(0x0) << 28)
29723 /* Value is in bytes. */
29724 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MIN_BW_SCALE_BYTES \
29725 (UINT32_C(0x1) << 28)
29726 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MIN_BW_SCALE_LAST \
29727 HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MIN_BW_SCALE_BYTES
29728 /* bw_value_unit is 3 b */
29729 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_MASK \
29730 UINT32_C(0xe0000000)
29731 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_SFT \
29733 /* Value is in Mb or MB (base 10). */
29734 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_MEGA \
29735 (UINT32_C(0x0) << 29)
29736 /* Value is in Kb or KB (base 10). */
29737 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_KILO \
29738 (UINT32_C(0x2) << 29)
29739 /* Value is in bits or bytes. */
29740 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_BASE \
29741 (UINT32_C(0x4) << 29)
29742 /* Value is in Gb or GB (base 10). */
29743 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_GIGA \
29744 (UINT32_C(0x6) << 29)
29745 /* Value is in 1/100th of a percentage of total bandwidth. */
29746 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 \
29747 (UINT32_C(0x1) << 29)
29749 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_INVALID \
29750 (UINT32_C(0x7) << 29)
29751 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_LAST \
29752 HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_INVALID
29754 * Maximum BW allocated to CoS queue.
29755 * The HWRM will translate this value into byte counter and
29756 * time interval used for this COS inside the device.
29758 uint32_t queue_id2_max_bw;
29759 /* The bandwidth value. */
29760 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MAX_BW_BW_VALUE_MASK \
29761 UINT32_C(0xfffffff)
29762 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MAX_BW_BW_VALUE_SFT \
29764 /* The granularity of the value (bits or bytes). */
29765 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MAX_BW_SCALE \
29766 UINT32_C(0x10000000)
29767 /* Value is in bits. */
29768 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MAX_BW_SCALE_BITS \
29769 (UINT32_C(0x0) << 28)
29770 /* Value is in bytes. */
29771 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MAX_BW_SCALE_BYTES \
29772 (UINT32_C(0x1) << 28)
29773 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MAX_BW_SCALE_LAST \
29774 HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MAX_BW_SCALE_BYTES
29775 /* bw_value_unit is 3 b */
29776 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_MASK \
29777 UINT32_C(0xe0000000)
29778 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_SFT \
29780 /* Value is in Mb or MB (base 10). */
29781 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_MEGA \
29782 (UINT32_C(0x0) << 29)
29783 /* Value is in Kb or KB (base 10). */
29784 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_KILO \
29785 (UINT32_C(0x2) << 29)
29786 /* Value is in bits or bytes. */
29787 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_BASE \
29788 (UINT32_C(0x4) << 29)
29789 /* Value is in Gb or GB (base 10). */
29790 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_GIGA \
29791 (UINT32_C(0x6) << 29)
29792 /* Value is in 1/100th of a percentage of total bandwidth. */
29793 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 \
29794 (UINT32_C(0x1) << 29)
29796 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_INVALID \
29797 (UINT32_C(0x7) << 29)
29798 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_LAST \
29799 HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_INVALID
29800 /* Transmission Selection Algorithm (TSA) for CoS Queue. */
29801 uint8_t queue_id2_tsa_assign;
29802 /* Strict Priority */
29803 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_TSA_ASSIGN_SP \
29805 /* Enhanced Transmission Selection */
29806 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_TSA_ASSIGN_ETS \
29809 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_TSA_ASSIGN_RESERVED_FIRST \
29812 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_TSA_ASSIGN_RESERVED_LAST \
29815 * Priority level for strict priority. Valid only when the
29816 * tsa_assign is 0 - Strict Priority (SP)
29817 * 0..7 - Valid values.
29818 * 8..255 - Reserved.
29820 uint8_t queue_id2_pri_lvl;
29822 * Weight used to allocate remaining BW for this COS after
29823 * servicing guaranteed bandwidths for all COS.
29825 uint8_t queue_id2_bw_weight;
29826 /* ID of CoS Queue 3. */
29829 * Minimum BW allocated to CoS Queue.
29830 * The HWRM will translate this value into byte counter and
29831 * time interval used for this COS inside the device.
29833 uint32_t queue_id3_min_bw;
29834 /* The bandwidth value. */
29835 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MIN_BW_BW_VALUE_MASK \
29836 UINT32_C(0xfffffff)
29837 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MIN_BW_BW_VALUE_SFT \
29839 /* The granularity of the value (bits or bytes). */
29840 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MIN_BW_SCALE \
29841 UINT32_C(0x10000000)
29842 /* Value is in bits. */
29843 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MIN_BW_SCALE_BITS \
29844 (UINT32_C(0x0) << 28)
29845 /* Value is in bytes. */
29846 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MIN_BW_SCALE_BYTES \
29847 (UINT32_C(0x1) << 28)
29848 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MIN_BW_SCALE_LAST \
29849 HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MIN_BW_SCALE_BYTES
29850 /* bw_value_unit is 3 b */
29851 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_MASK \
29852 UINT32_C(0xe0000000)
29853 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_SFT \
29855 /* Value is in Mb or MB (base 10). */
29856 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_MEGA \
29857 (UINT32_C(0x0) << 29)
29858 /* Value is in Kb or KB (base 10). */
29859 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_KILO \
29860 (UINT32_C(0x2) << 29)
29861 /* Value is in bits or bytes. */
29862 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_BASE \
29863 (UINT32_C(0x4) << 29)
29864 /* Value is in Gb or GB (base 10). */
29865 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_GIGA \
29866 (UINT32_C(0x6) << 29)
29867 /* Value is in 1/100th of a percentage of total bandwidth. */
29868 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 \
29869 (UINT32_C(0x1) << 29)
29871 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_INVALID \
29872 (UINT32_C(0x7) << 29)
29873 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_LAST \
29874 HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_INVALID
29876 * Maximum BW allocated to CoS queue.
29877 * The HWRM will translate this value into byte counter and
29878 * time interval used for this COS inside the device.
29880 uint32_t queue_id3_max_bw;
29881 /* The bandwidth value. */
29882 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MAX_BW_BW_VALUE_MASK \
29883 UINT32_C(0xfffffff)
29884 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MAX_BW_BW_VALUE_SFT \
29886 /* The granularity of the value (bits or bytes). */
29887 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MAX_BW_SCALE \
29888 UINT32_C(0x10000000)
29889 /* Value is in bits. */
29890 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MAX_BW_SCALE_BITS \
29891 (UINT32_C(0x0) << 28)
29892 /* Value is in bytes. */
29893 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MAX_BW_SCALE_BYTES \
29894 (UINT32_C(0x1) << 28)
29895 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MAX_BW_SCALE_LAST \
29896 HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MAX_BW_SCALE_BYTES
29897 /* bw_value_unit is 3 b */
29898 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_MASK \
29899 UINT32_C(0xe0000000)
29900 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_SFT \
29902 /* Value is in Mb or MB (base 10). */
29903 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_MEGA \
29904 (UINT32_C(0x0) << 29)
29905 /* Value is in Kb or KB (base 10). */
29906 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_KILO \
29907 (UINT32_C(0x2) << 29)
29908 /* Value is in bits or bytes. */
29909 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_BASE \
29910 (UINT32_C(0x4) << 29)
29911 /* Value is in Gb or GB (base 10). */
29912 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_GIGA \
29913 (UINT32_C(0x6) << 29)
29914 /* Value is in 1/100th of a percentage of total bandwidth. */
29915 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 \
29916 (UINT32_C(0x1) << 29)
29918 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_INVALID \
29919 (UINT32_C(0x7) << 29)
29920 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_LAST \
29921 HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_INVALID
29922 /* Transmission Selection Algorithm (TSA) for CoS Queue. */
29923 uint8_t queue_id3_tsa_assign;
29924 /* Strict Priority */
29925 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_TSA_ASSIGN_SP \
29927 /* Enhanced Transmission Selection */
29928 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_TSA_ASSIGN_ETS \
29931 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_TSA_ASSIGN_RESERVED_FIRST \
29934 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_TSA_ASSIGN_RESERVED_LAST \
29937 * Priority level for strict priority. Valid only when the
29938 * tsa_assign is 0 - Strict Priority (SP)
29939 * 0..7 - Valid values.
29940 * 8..255 - Reserved.
29942 uint8_t queue_id3_pri_lvl;
29944 * Weight used to allocate remaining BW for this COS after
29945 * servicing guaranteed bandwidths for all COS.
29947 uint8_t queue_id3_bw_weight;
29948 /* ID of CoS Queue 4. */
29951 * Minimum BW allocated to CoS Queue.
29952 * The HWRM will translate this value into byte counter and
29953 * time interval used for this COS inside the device.
29955 uint32_t queue_id4_min_bw;
29956 /* The bandwidth value. */
29957 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MIN_BW_BW_VALUE_MASK \
29958 UINT32_C(0xfffffff)
29959 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MIN_BW_BW_VALUE_SFT \
29961 /* The granularity of the value (bits or bytes). */
29962 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MIN_BW_SCALE \
29963 UINT32_C(0x10000000)
29964 /* Value is in bits. */
29965 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MIN_BW_SCALE_BITS \
29966 (UINT32_C(0x0) << 28)
29967 /* Value is in bytes. */
29968 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MIN_BW_SCALE_BYTES \
29969 (UINT32_C(0x1) << 28)
29970 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MIN_BW_SCALE_LAST \
29971 HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MIN_BW_SCALE_BYTES
29972 /* bw_value_unit is 3 b */
29973 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_MASK \
29974 UINT32_C(0xe0000000)
29975 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_SFT \
29977 /* Value is in Mb or MB (base 10). */
29978 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_MEGA \
29979 (UINT32_C(0x0) << 29)
29980 /* Value is in Kb or KB (base 10). */
29981 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_KILO \
29982 (UINT32_C(0x2) << 29)
29983 /* Value is in bits or bytes. */
29984 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_BASE \
29985 (UINT32_C(0x4) << 29)
29986 /* Value is in Gb or GB (base 10). */
29987 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_GIGA \
29988 (UINT32_C(0x6) << 29)
29989 /* Value is in 1/100th of a percentage of total bandwidth. */
29990 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 \
29991 (UINT32_C(0x1) << 29)
29993 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_INVALID \
29994 (UINT32_C(0x7) << 29)
29995 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_LAST \
29996 HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_INVALID
29998 * Maximum BW allocated to CoS queue.
29999 * The HWRM will translate this value into byte counter and
30000 * time interval used for this COS inside the device.
30002 uint32_t queue_id4_max_bw;
30003 /* The bandwidth value. */
30004 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MAX_BW_BW_VALUE_MASK \
30005 UINT32_C(0xfffffff)
30006 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MAX_BW_BW_VALUE_SFT \
30008 /* The granularity of the value (bits or bytes). */
30009 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MAX_BW_SCALE \
30010 UINT32_C(0x10000000)
30011 /* Value is in bits. */
30012 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MAX_BW_SCALE_BITS \
30013 (UINT32_C(0x0) << 28)
30014 /* Value is in bytes. */
30015 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MAX_BW_SCALE_BYTES \
30016 (UINT32_C(0x1) << 28)
30017 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MAX_BW_SCALE_LAST \
30018 HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MAX_BW_SCALE_BYTES
30019 /* bw_value_unit is 3 b */
30020 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_MASK \
30021 UINT32_C(0xe0000000)
30022 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_SFT \
30024 /* Value is in Mb or MB (base 10). */
30025 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_MEGA \
30026 (UINT32_C(0x0) << 29)
30027 /* Value is in Kb or KB (base 10). */
30028 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_KILO \
30029 (UINT32_C(0x2) << 29)
30030 /* Value is in bits or bytes. */
30031 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_BASE \
30032 (UINT32_C(0x4) << 29)
30033 /* Value is in Gb or GB (base 10). */
30034 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_GIGA \
30035 (UINT32_C(0x6) << 29)
30036 /* Value is in 1/100th of a percentage of total bandwidth. */
30037 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 \
30038 (UINT32_C(0x1) << 29)
30040 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_INVALID \
30041 (UINT32_C(0x7) << 29)
30042 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_LAST \
30043 HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_INVALID
30044 /* Transmission Selection Algorithm (TSA) for CoS Queue. */
30045 uint8_t queue_id4_tsa_assign;
30046 /* Strict Priority */
30047 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_TSA_ASSIGN_SP \
30049 /* Enhanced Transmission Selection */
30050 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_TSA_ASSIGN_ETS \
30053 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_TSA_ASSIGN_RESERVED_FIRST \
30056 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_TSA_ASSIGN_RESERVED_LAST \
30059 * Priority level for strict priority. Valid only when the
30060 * tsa_assign is 0 - Strict Priority (SP)
30061 * 0..7 - Valid values.
30062 * 8..255 - Reserved.
30064 uint8_t queue_id4_pri_lvl;
30066 * Weight used to allocate remaining BW for this COS after
30067 * servicing guaranteed bandwidths for all COS.
30069 uint8_t queue_id4_bw_weight;
30070 /* ID of CoS Queue 5. */
30073 * Minimum BW allocated to CoS Queue.
30074 * The HWRM will translate this value into byte counter and
30075 * time interval used for this COS inside the device.
30077 uint32_t queue_id5_min_bw;
30078 /* The bandwidth value. */
30079 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MIN_BW_BW_VALUE_MASK \
30080 UINT32_C(0xfffffff)
30081 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MIN_BW_BW_VALUE_SFT \
30083 /* The granularity of the value (bits or bytes). */
30084 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MIN_BW_SCALE \
30085 UINT32_C(0x10000000)
30086 /* Value is in bits. */
30087 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MIN_BW_SCALE_BITS \
30088 (UINT32_C(0x0) << 28)
30089 /* Value is in bytes. */
30090 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MIN_BW_SCALE_BYTES \
30091 (UINT32_C(0x1) << 28)
30092 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MIN_BW_SCALE_LAST \
30093 HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MIN_BW_SCALE_BYTES
30094 /* bw_value_unit is 3 b */
30095 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_MASK \
30096 UINT32_C(0xe0000000)
30097 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_SFT \
30099 /* Value is in Mb or MB (base 10). */
30100 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_MEGA \
30101 (UINT32_C(0x0) << 29)
30102 /* Value is in Kb or KB (base 10). */
30103 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_KILO \
30104 (UINT32_C(0x2) << 29)
30105 /* Value is in bits or bytes. */
30106 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_BASE \
30107 (UINT32_C(0x4) << 29)
30108 /* Value is in Gb or GB (base 10). */
30109 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_GIGA \
30110 (UINT32_C(0x6) << 29)
30111 /* Value is in 1/100th of a percentage of total bandwidth. */
30112 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 \
30113 (UINT32_C(0x1) << 29)
30115 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_INVALID \
30116 (UINT32_C(0x7) << 29)
30117 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_LAST \
30118 HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_INVALID
30120 * Maximum BW allocated to CoS queue.
30121 * The HWRM will translate this value into byte counter and
30122 * time interval used for this COS inside the device.
30124 uint32_t queue_id5_max_bw;
30125 /* The bandwidth value. */
30126 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MAX_BW_BW_VALUE_MASK \
30127 UINT32_C(0xfffffff)
30128 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MAX_BW_BW_VALUE_SFT \
30130 /* The granularity of the value (bits or bytes). */
30131 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MAX_BW_SCALE \
30132 UINT32_C(0x10000000)
30133 /* Value is in bits. */
30134 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MAX_BW_SCALE_BITS \
30135 (UINT32_C(0x0) << 28)
30136 /* Value is in bytes. */
30137 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MAX_BW_SCALE_BYTES \
30138 (UINT32_C(0x1) << 28)
30139 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MAX_BW_SCALE_LAST \
30140 HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MAX_BW_SCALE_BYTES
30141 /* bw_value_unit is 3 b */
30142 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_MASK \
30143 UINT32_C(0xe0000000)
30144 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_SFT \
30146 /* Value is in Mb or MB (base 10). */
30147 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_MEGA \
30148 (UINT32_C(0x0) << 29)
30149 /* Value is in Kb or KB (base 10). */
30150 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_KILO \
30151 (UINT32_C(0x2) << 29)
30152 /* Value is in bits or bytes. */
30153 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_BASE \
30154 (UINT32_C(0x4) << 29)
30155 /* Value is in Gb or GB (base 10). */
30156 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_GIGA \
30157 (UINT32_C(0x6) << 29)
30158 /* Value is in 1/100th of a percentage of total bandwidth. */
30159 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 \
30160 (UINT32_C(0x1) << 29)
30162 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_INVALID \
30163 (UINT32_C(0x7) << 29)
30164 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_LAST \
30165 HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_INVALID
30166 /* Transmission Selection Algorithm (TSA) for CoS Queue. */
30167 uint8_t queue_id5_tsa_assign;
30168 /* Strict Priority */
30169 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_TSA_ASSIGN_SP \
30171 /* Enhanced Transmission Selection */
30172 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_TSA_ASSIGN_ETS \
30175 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_TSA_ASSIGN_RESERVED_FIRST \
30178 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_TSA_ASSIGN_RESERVED_LAST \
30181 * Priority level for strict priority. Valid only when the
30182 * tsa_assign is 0 - Strict Priority (SP)
30183 * 0..7 - Valid values.
30184 * 8..255 - Reserved.
30186 uint8_t queue_id5_pri_lvl;
30188 * Weight used to allocate remaining BW for this COS after
30189 * servicing guaranteed bandwidths for all COS.
30191 uint8_t queue_id5_bw_weight;
30192 /* ID of CoS Queue 6. */
30195 * Minimum BW allocated to CoS Queue.
30196 * The HWRM will translate this value into byte counter and
30197 * time interval used for this COS inside the device.
30199 uint32_t queue_id6_min_bw;
30200 /* The bandwidth value. */
30201 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MIN_BW_BW_VALUE_MASK \
30202 UINT32_C(0xfffffff)
30203 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MIN_BW_BW_VALUE_SFT \
30205 /* The granularity of the value (bits or bytes). */
30206 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MIN_BW_SCALE \
30207 UINT32_C(0x10000000)
30208 /* Value is in bits. */
30209 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MIN_BW_SCALE_BITS \
30210 (UINT32_C(0x0) << 28)
30211 /* Value is in bytes. */
30212 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MIN_BW_SCALE_BYTES \
30213 (UINT32_C(0x1) << 28)
30214 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MIN_BW_SCALE_LAST \
30215 HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MIN_BW_SCALE_BYTES
30216 /* bw_value_unit is 3 b */
30217 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_MASK \
30218 UINT32_C(0xe0000000)
30219 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_SFT \
30221 /* Value is in Mb or MB (base 10). */
30222 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_MEGA \
30223 (UINT32_C(0x0) << 29)
30224 /* Value is in Kb or KB (base 10). */
30225 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_KILO \
30226 (UINT32_C(0x2) << 29)
30227 /* Value is in bits or bytes. */
30228 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_BASE \
30229 (UINT32_C(0x4) << 29)
30230 /* Value is in Gb or GB (base 10). */
30231 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_GIGA \
30232 (UINT32_C(0x6) << 29)
30233 /* Value is in 1/100th of a percentage of total bandwidth. */
30234 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 \
30235 (UINT32_C(0x1) << 29)
30237 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_INVALID \
30238 (UINT32_C(0x7) << 29)
30239 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_LAST \
30240 HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_INVALID
30242 * Maximum BW allocated to CoS queue.
30243 * The HWRM will translate this value into byte counter and
30244 * time interval used for this COS inside the device.
30246 uint32_t queue_id6_max_bw;
30247 /* The bandwidth value. */
30248 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MAX_BW_BW_VALUE_MASK \
30249 UINT32_C(0xfffffff)
30250 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MAX_BW_BW_VALUE_SFT \
30252 /* The granularity of the value (bits or bytes). */
30253 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MAX_BW_SCALE \
30254 UINT32_C(0x10000000)
30255 /* Value is in bits. */
30256 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MAX_BW_SCALE_BITS \
30257 (UINT32_C(0x0) << 28)
30258 /* Value is in bytes. */
30259 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MAX_BW_SCALE_BYTES \
30260 (UINT32_C(0x1) << 28)
30261 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MAX_BW_SCALE_LAST \
30262 HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MAX_BW_SCALE_BYTES
30263 /* bw_value_unit is 3 b */
30264 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_MASK \
30265 UINT32_C(0xe0000000)
30266 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_SFT \
30268 /* Value is in Mb or MB (base 10). */
30269 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_MEGA \
30270 (UINT32_C(0x0) << 29)
30271 /* Value is in Kb or KB (base 10). */
30272 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_KILO \
30273 (UINT32_C(0x2) << 29)
30274 /* Value is in bits or bytes. */
30275 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_BASE \
30276 (UINT32_C(0x4) << 29)
30277 /* Value is in Gb or GB (base 10). */
30278 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_GIGA \
30279 (UINT32_C(0x6) << 29)
30280 /* Value is in 1/100th of a percentage of total bandwidth. */
30281 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 \
30282 (UINT32_C(0x1) << 29)
30284 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_INVALID \
30285 (UINT32_C(0x7) << 29)
30286 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_LAST \
30287 HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_INVALID
30288 /* Transmission Selection Algorithm (TSA) for CoS Queue. */
30289 uint8_t queue_id6_tsa_assign;
30290 /* Strict Priority */
30291 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_TSA_ASSIGN_SP \
30293 /* Enhanced Transmission Selection */
30294 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_TSA_ASSIGN_ETS \
30297 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_TSA_ASSIGN_RESERVED_FIRST \
30300 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_TSA_ASSIGN_RESERVED_LAST \
30303 * Priority level for strict priority. Valid only when the
30304 * tsa_assign is 0 - Strict Priority (SP)
30305 * 0..7 - Valid values.
30306 * 8..255 - Reserved.
30308 uint8_t queue_id6_pri_lvl;
30310 * Weight used to allocate remaining BW for this COS after
30311 * servicing guaranteed bandwidths for all COS.
30313 uint8_t queue_id6_bw_weight;
30314 /* ID of CoS Queue 7. */
30317 * Minimum BW allocated to CoS Queue.
30318 * The HWRM will translate this value into byte counter and
30319 * time interval used for this COS inside the device.
30321 uint32_t queue_id7_min_bw;
30322 /* The bandwidth value. */
30323 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MIN_BW_BW_VALUE_MASK \
30324 UINT32_C(0xfffffff)
30325 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MIN_BW_BW_VALUE_SFT \
30327 /* The granularity of the value (bits or bytes). */
30328 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MIN_BW_SCALE \
30329 UINT32_C(0x10000000)
30330 /* Value is in bits. */
30331 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MIN_BW_SCALE_BITS \
30332 (UINT32_C(0x0) << 28)
30333 /* Value is in bytes. */
30334 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MIN_BW_SCALE_BYTES \
30335 (UINT32_C(0x1) << 28)
30336 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MIN_BW_SCALE_LAST \
30337 HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MIN_BW_SCALE_BYTES
30338 /* bw_value_unit is 3 b */
30339 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_MASK \
30340 UINT32_C(0xe0000000)
30341 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_SFT \
30343 /* Value is in Mb or MB (base 10). */
30344 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_MEGA \
30345 (UINT32_C(0x0) << 29)
30346 /* Value is in Kb or KB (base 10). */
30347 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_KILO \
30348 (UINT32_C(0x2) << 29)
30349 /* Value is in bits or bytes. */
30350 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_BASE \
30351 (UINT32_C(0x4) << 29)
30352 /* Value is in Gb or GB (base 10). */
30353 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_GIGA \
30354 (UINT32_C(0x6) << 29)
30355 /* Value is in 1/100th of a percentage of total bandwidth. */
30356 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 \
30357 (UINT32_C(0x1) << 29)
30359 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_INVALID \
30360 (UINT32_C(0x7) << 29)
30361 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_LAST \
30362 HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_INVALID
30364 * Maximum BW allocated to CoS queue.
30365 * The HWRM will translate this value into byte counter and
30366 * time interval used for this COS inside the device.
30368 uint32_t queue_id7_max_bw;
30369 /* The bandwidth value. */
30370 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MAX_BW_BW_VALUE_MASK \
30371 UINT32_C(0xfffffff)
30372 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MAX_BW_BW_VALUE_SFT \
30374 /* The granularity of the value (bits or bytes). */
30375 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MAX_BW_SCALE \
30376 UINT32_C(0x10000000)
30377 /* Value is in bits. */
30378 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MAX_BW_SCALE_BITS \
30379 (UINT32_C(0x0) << 28)
30380 /* Value is in bytes. */
30381 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MAX_BW_SCALE_BYTES \
30382 (UINT32_C(0x1) << 28)
30383 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MAX_BW_SCALE_LAST \
30384 HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MAX_BW_SCALE_BYTES
30385 /* bw_value_unit is 3 b */
30386 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_MASK \
30387 UINT32_C(0xe0000000)
30388 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_SFT \
30390 /* Value is in Mb or MB (base 10). */
30391 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_MEGA \
30392 (UINT32_C(0x0) << 29)
30393 /* Value is in Kb or KB (base 10). */
30394 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_KILO \
30395 (UINT32_C(0x2) << 29)
30396 /* Value is in bits or bytes. */
30397 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_BASE \
30398 (UINT32_C(0x4) << 29)
30399 /* Value is in Gb or GB (base 10). */
30400 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_GIGA \
30401 (UINT32_C(0x6) << 29)
30402 /* Value is in 1/100th of a percentage of total bandwidth. */
30403 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 \
30404 (UINT32_C(0x1) << 29)
30406 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_INVALID \
30407 (UINT32_C(0x7) << 29)
30408 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_LAST \
30409 HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_INVALID
30410 /* Transmission Selection Algorithm (TSA) for CoS Queue. */
30411 uint8_t queue_id7_tsa_assign;
30412 /* Strict Priority */
30413 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_TSA_ASSIGN_SP \
30415 /* Enhanced Transmission Selection */
30416 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_TSA_ASSIGN_ETS \
30419 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_TSA_ASSIGN_RESERVED_FIRST \
30422 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_TSA_ASSIGN_RESERVED_LAST \
30425 * Priority level for strict priority. Valid only when the
30426 * tsa_assign is 0 - Strict Priority (SP)
30427 * 0..7 - Valid values.
30428 * 8..255 - Reserved.
30430 uint8_t queue_id7_pri_lvl;
30432 * Weight used to allocate remaining BW for this COS after
30433 * servicing guaranteed bandwidths for all COS.
30435 uint8_t queue_id7_bw_weight;
30436 uint8_t unused_2[4];
30438 * This field is used in Output records to indicate that the output
30439 * is completely written to RAM. This field should be read as '1'
30440 * to indicate that the output has been completely written.
30441 * When writing a command completion or response to an internal processor,
30442 * the order of writes has to be such that this field is written last.
30447 /*************************
30448 * hwrm_queue_cos2bw_cfg *
30449 *************************/
30452 /* hwrm_queue_cos2bw_cfg_input (size:1024b/128B) */
30453 struct hwrm_queue_cos2bw_cfg_input {
30454 /* The HWRM command request type. */
30457 * The completion ring to send the completion event on. This should
30458 * be the NQ ID returned from the `nq_alloc` HWRM command.
30460 uint16_t cmpl_ring;
30462 * The sequence ID is used by the driver for tracking multiple
30463 * commands. This ID is treated as opaque data by the firmware and
30464 * the value is returned in the `hwrm_resp_hdr` upon completion.
30468 * The target ID of the command:
30469 * * 0x0-0xFFF8 - The function ID
30470 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
30471 * * 0xFFFD - Reserved for user-space HWRM interface
30474 uint16_t target_id;
30476 * A physical address pointer pointing to a host buffer that the
30477 * command's response data will be written. This can be either a host
30478 * physical address (HPA) or a guest physical address (GPA) and must
30479 * point to a physically contiguous block of memory.
30481 uint64_t resp_addr;
30485 * If this bit is set to 1, then all queue_id0 related
30486 * parameters in this command are valid.
30488 #define HWRM_QUEUE_COS2BW_CFG_INPUT_ENABLES_COS_QUEUE_ID0_VALID \
30491 * If this bit is set to 1, then all queue_id1 related
30492 * parameters in this command are valid.
30494 #define HWRM_QUEUE_COS2BW_CFG_INPUT_ENABLES_COS_QUEUE_ID1_VALID \
30497 * If this bit is set to 1, then all queue_id2 related
30498 * parameters in this command are valid.
30500 #define HWRM_QUEUE_COS2BW_CFG_INPUT_ENABLES_COS_QUEUE_ID2_VALID \
30503 * If this bit is set to 1, then all queue_id3 related
30504 * parameters in this command are valid.
30506 #define HWRM_QUEUE_COS2BW_CFG_INPUT_ENABLES_COS_QUEUE_ID3_VALID \
30509 * If this bit is set to 1, then all queue_id4 related
30510 * parameters in this command are valid.
30512 #define HWRM_QUEUE_COS2BW_CFG_INPUT_ENABLES_COS_QUEUE_ID4_VALID \
30515 * If this bit is set to 1, then all queue_id5 related
30516 * parameters in this command are valid.
30518 #define HWRM_QUEUE_COS2BW_CFG_INPUT_ENABLES_COS_QUEUE_ID5_VALID \
30521 * If this bit is set to 1, then all queue_id6 related
30522 * parameters in this command are valid.
30524 #define HWRM_QUEUE_COS2BW_CFG_INPUT_ENABLES_COS_QUEUE_ID6_VALID \
30527 * If this bit is set to 1, then all queue_id7 related
30528 * parameters in this command are valid.
30530 #define HWRM_QUEUE_COS2BW_CFG_INPUT_ENABLES_COS_QUEUE_ID7_VALID \
30533 * Port ID of port for which the table is being configured.
30534 * The HWRM needs to check whether this function is allowed
30535 * to configure TC BW assignment on this port.
30538 /* ID of CoS Queue 0. */
30542 * Minimum BW allocated to CoS Queue.
30543 * The HWRM will translate this value into byte counter and
30544 * time interval used for this COS inside the device.
30546 uint32_t queue_id0_min_bw;
30547 /* The bandwidth value. */
30548 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MIN_BW_BW_VALUE_MASK \
30549 UINT32_C(0xfffffff)
30550 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MIN_BW_BW_VALUE_SFT \
30552 /* The granularity of the value (bits or bytes). */
30553 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MIN_BW_SCALE \
30554 UINT32_C(0x10000000)
30555 /* Value is in bits. */
30556 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MIN_BW_SCALE_BITS \
30557 (UINT32_C(0x0) << 28)
30558 /* Value is in bytes. */
30559 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MIN_BW_SCALE_BYTES \
30560 (UINT32_C(0x1) << 28)
30561 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MIN_BW_SCALE_LAST \
30562 HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MIN_BW_SCALE_BYTES
30563 /* bw_value_unit is 3 b */
30564 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_MASK \
30565 UINT32_C(0xe0000000)
30566 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_SFT \
30568 /* Value is in Mb or MB (base 10). */
30569 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_MEGA \
30570 (UINT32_C(0x0) << 29)
30571 /* Value is in Kb or KB (base 10). */
30572 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_KILO \
30573 (UINT32_C(0x2) << 29)
30574 /* Value is in bits or bytes. */
30575 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_BASE \
30576 (UINT32_C(0x4) << 29)
30577 /* Value is in Gb or GB (base 10). */
30578 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_GIGA \
30579 (UINT32_C(0x6) << 29)
30580 /* Value is in 1/100th of a percentage of total bandwidth. */
30581 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 \
30582 (UINT32_C(0x1) << 29)
30584 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_INVALID \
30585 (UINT32_C(0x7) << 29)
30586 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_LAST \
30587 HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_INVALID
30589 * Maximum BW allocated to CoS Queue.
30590 * The HWRM will translate this value into byte counter and
30591 * time interval used for this COS inside the device.
30593 uint32_t queue_id0_max_bw;
30594 /* The bandwidth value. */
30595 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MAX_BW_BW_VALUE_MASK \
30596 UINT32_C(0xfffffff)
30597 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MAX_BW_BW_VALUE_SFT \
30599 /* The granularity of the value (bits or bytes). */
30600 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MAX_BW_SCALE \
30601 UINT32_C(0x10000000)
30602 /* Value is in bits. */
30603 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MAX_BW_SCALE_BITS \
30604 (UINT32_C(0x0) << 28)
30605 /* Value is in bytes. */
30606 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MAX_BW_SCALE_BYTES \
30607 (UINT32_C(0x1) << 28)
30608 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MAX_BW_SCALE_LAST \
30609 HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MAX_BW_SCALE_BYTES
30610 /* bw_value_unit is 3 b */
30611 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_MASK \
30612 UINT32_C(0xe0000000)
30613 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_SFT \
30615 /* Value is in Mb or MB (base 10). */
30616 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_MEGA \
30617 (UINT32_C(0x0) << 29)
30618 /* Value is in Kb or KB (base 10). */
30619 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_KILO \
30620 (UINT32_C(0x2) << 29)
30621 /* Value is in bits or bytes. */
30622 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_BASE \
30623 (UINT32_C(0x4) << 29)
30624 /* Value is in Gb or GB (base 10). */
30625 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_GIGA \
30626 (UINT32_C(0x6) << 29)
30627 /* Value is in 1/100th of a percentage of total bandwidth. */
30628 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 \
30629 (UINT32_C(0x1) << 29)
30631 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_INVALID \
30632 (UINT32_C(0x7) << 29)
30633 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_LAST \
30634 HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_INVALID
30635 /* Transmission Selection Algorithm (TSA) for CoS Queue. */
30636 uint8_t queue_id0_tsa_assign;
30637 /* Strict Priority */
30638 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_TSA_ASSIGN_SP \
30640 /* Enhanced Transmission Selection */
30641 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_TSA_ASSIGN_ETS \
30644 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_TSA_ASSIGN_RESERVED_FIRST \
30647 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_TSA_ASSIGN_RESERVED_LAST \
30650 * Priority level for strict priority. Valid only when the
30651 * tsa_assign is 0 - Strict Priority (SP)
30652 * 0..7 - Valid values.
30653 * 8..255 - Reserved.
30655 uint8_t queue_id0_pri_lvl;
30657 * Weight used to allocate remaining BW for this COS after
30658 * servicing guaranteed bandwidths for all COS.
30660 uint8_t queue_id0_bw_weight;
30661 /* ID of CoS Queue 1. */
30664 * Minimum BW allocated to CoS Queue.
30665 * The HWRM will translate this value into byte counter and
30666 * time interval used for this COS inside the device.
30668 uint32_t queue_id1_min_bw;
30669 /* The bandwidth value. */
30670 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MIN_BW_BW_VALUE_MASK \
30671 UINT32_C(0xfffffff)
30672 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MIN_BW_BW_VALUE_SFT \
30674 /* The granularity of the value (bits or bytes). */
30675 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MIN_BW_SCALE \
30676 UINT32_C(0x10000000)
30677 /* Value is in bits. */
30678 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MIN_BW_SCALE_BITS \
30679 (UINT32_C(0x0) << 28)
30680 /* Value is in bytes. */
30681 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MIN_BW_SCALE_BYTES \
30682 (UINT32_C(0x1) << 28)
30683 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MIN_BW_SCALE_LAST \
30684 HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MIN_BW_SCALE_BYTES
30685 /* bw_value_unit is 3 b */
30686 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_MASK \
30687 UINT32_C(0xe0000000)
30688 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_SFT \
30690 /* Value is in Mb or MB (base 10). */
30691 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_MEGA \
30692 (UINT32_C(0x0) << 29)
30693 /* Value is in Kb or KB (base 10). */
30694 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_KILO \
30695 (UINT32_C(0x2) << 29)
30696 /* Value is in bits or bytes. */
30697 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_BASE \
30698 (UINT32_C(0x4) << 29)
30699 /* Value is in Gb or GB (base 10). */
30700 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_GIGA \
30701 (UINT32_C(0x6) << 29)
30702 /* Value is in 1/100th of a percentage of total bandwidth. */
30703 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 \
30704 (UINT32_C(0x1) << 29)
30706 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_INVALID \
30707 (UINT32_C(0x7) << 29)
30708 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_LAST \
30709 HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_INVALID
30711 * Maximum BW allocated to CoS queue.
30712 * The HWRM will translate this value into byte counter and
30713 * time interval used for this COS inside the device.
30715 uint32_t queue_id1_max_bw;
30716 /* The bandwidth value. */
30717 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MAX_BW_BW_VALUE_MASK \
30718 UINT32_C(0xfffffff)
30719 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MAX_BW_BW_VALUE_SFT \
30721 /* The granularity of the value (bits or bytes). */
30722 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MAX_BW_SCALE \
30723 UINT32_C(0x10000000)
30724 /* Value is in bits. */
30725 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MAX_BW_SCALE_BITS \
30726 (UINT32_C(0x0) << 28)
30727 /* Value is in bytes. */
30728 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MAX_BW_SCALE_BYTES \
30729 (UINT32_C(0x1) << 28)
30730 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MAX_BW_SCALE_LAST \
30731 HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MAX_BW_SCALE_BYTES
30732 /* bw_value_unit is 3 b */
30733 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_MASK \
30734 UINT32_C(0xe0000000)
30735 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_SFT \
30737 /* Value is in Mb or MB (base 10). */
30738 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_MEGA \
30739 (UINT32_C(0x0) << 29)
30740 /* Value is in Kb or KB (base 10). */
30741 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_KILO \
30742 (UINT32_C(0x2) << 29)
30743 /* Value is in bits or bytes. */
30744 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_BASE \
30745 (UINT32_C(0x4) << 29)
30746 /* Value is in Gb or GB (base 10). */
30747 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_GIGA \
30748 (UINT32_C(0x6) << 29)
30749 /* Value is in 1/100th of a percentage of total bandwidth. */
30750 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 \
30751 (UINT32_C(0x1) << 29)
30753 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_INVALID \
30754 (UINT32_C(0x7) << 29)
30755 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_LAST \
30756 HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_INVALID
30757 /* Transmission Selection Algorithm (TSA) for CoS Queue. */
30758 uint8_t queue_id1_tsa_assign;
30759 /* Strict Priority */
30760 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_TSA_ASSIGN_SP \
30762 /* Enhanced Transmission Selection */
30763 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_TSA_ASSIGN_ETS \
30766 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_TSA_ASSIGN_RESERVED_FIRST \
30769 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_TSA_ASSIGN_RESERVED_LAST \
30772 * Priority level for strict priority. Valid only when the
30773 * tsa_assign is 0 - Strict Priority (SP)
30774 * 0..7 - Valid values.
30775 * 8..255 - Reserved.
30777 uint8_t queue_id1_pri_lvl;
30779 * Weight used to allocate remaining BW for this COS after
30780 * servicing guaranteed bandwidths for all COS.
30782 uint8_t queue_id1_bw_weight;
30783 /* ID of CoS Queue 2. */
30786 * Minimum BW allocated to CoS Queue.
30787 * The HWRM will translate this value into byte counter and
30788 * time interval used for this COS inside the device.
30790 uint32_t queue_id2_min_bw;
30791 /* The bandwidth value. */
30792 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MIN_BW_BW_VALUE_MASK \
30793 UINT32_C(0xfffffff)
30794 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MIN_BW_BW_VALUE_SFT \
30796 /* The granularity of the value (bits or bytes). */
30797 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MIN_BW_SCALE \
30798 UINT32_C(0x10000000)
30799 /* Value is in bits. */
30800 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MIN_BW_SCALE_BITS \
30801 (UINT32_C(0x0) << 28)
30802 /* Value is in bytes. */
30803 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MIN_BW_SCALE_BYTES \
30804 (UINT32_C(0x1) << 28)
30805 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MIN_BW_SCALE_LAST \
30806 HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MIN_BW_SCALE_BYTES
30807 /* bw_value_unit is 3 b */
30808 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_MASK \
30809 UINT32_C(0xe0000000)
30810 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_SFT \
30812 /* Value is in Mb or MB (base 10). */
30813 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_MEGA \
30814 (UINT32_C(0x0) << 29)
30815 /* Value is in Kb or KB (base 10). */
30816 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_KILO \
30817 (UINT32_C(0x2) << 29)
30818 /* Value is in bits or bytes. */
30819 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_BASE \
30820 (UINT32_C(0x4) << 29)
30821 /* Value is in Gb or GB (base 10). */
30822 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_GIGA \
30823 (UINT32_C(0x6) << 29)
30824 /* Value is in 1/100th of a percentage of total bandwidth. */
30825 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 \
30826 (UINT32_C(0x1) << 29)
30828 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_INVALID \
30829 (UINT32_C(0x7) << 29)
30830 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_LAST \
30831 HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_INVALID
30833 * Maximum BW allocated to CoS queue.
30834 * The HWRM will translate this value into byte counter and
30835 * time interval used for this COS inside the device.
30837 uint32_t queue_id2_max_bw;
30838 /* The bandwidth value. */
30839 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MAX_BW_BW_VALUE_MASK \
30840 UINT32_C(0xfffffff)
30841 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MAX_BW_BW_VALUE_SFT \
30843 /* The granularity of the value (bits or bytes). */
30844 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MAX_BW_SCALE \
30845 UINT32_C(0x10000000)
30846 /* Value is in bits. */
30847 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MAX_BW_SCALE_BITS \
30848 (UINT32_C(0x0) << 28)
30849 /* Value is in bytes. */
30850 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MAX_BW_SCALE_BYTES \
30851 (UINT32_C(0x1) << 28)
30852 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MAX_BW_SCALE_LAST \
30853 HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MAX_BW_SCALE_BYTES
30854 /* bw_value_unit is 3 b */
30855 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_MASK \
30856 UINT32_C(0xe0000000)
30857 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_SFT \
30859 /* Value is in Mb or MB (base 10). */
30860 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_MEGA \
30861 (UINT32_C(0x0) << 29)
30862 /* Value is in Kb or KB (base 10). */
30863 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_KILO \
30864 (UINT32_C(0x2) << 29)
30865 /* Value is in bits or bytes. */
30866 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_BASE \
30867 (UINT32_C(0x4) << 29)
30868 /* Value is in Gb or GB (base 10). */
30869 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_GIGA \
30870 (UINT32_C(0x6) << 29)
30871 /* Value is in 1/100th of a percentage of total bandwidth. */
30872 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 \
30873 (UINT32_C(0x1) << 29)
30875 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_INVALID \
30876 (UINT32_C(0x7) << 29)
30877 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_LAST \
30878 HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_INVALID
30879 /* Transmission Selection Algorithm (TSA) for CoS Queue. */
30880 uint8_t queue_id2_tsa_assign;
30881 /* Strict Priority */
30882 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_TSA_ASSIGN_SP \
30884 /* Enhanced Transmission Selection */
30885 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_TSA_ASSIGN_ETS \
30888 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_TSA_ASSIGN_RESERVED_FIRST \
30891 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_TSA_ASSIGN_RESERVED_LAST \
30894 * Priority level for strict priority. Valid only when the
30895 * tsa_assign is 0 - Strict Priority (SP)
30896 * 0..7 - Valid values.
30897 * 8..255 - Reserved.
30899 uint8_t queue_id2_pri_lvl;
30901 * Weight used to allocate remaining BW for this COS after
30902 * servicing guaranteed bandwidths for all COS.
30904 uint8_t queue_id2_bw_weight;
30905 /* ID of CoS Queue 3. */
30908 * Minimum BW allocated to CoS Queue.
30909 * The HWRM will translate this value into byte counter and
30910 * time interval used for this COS inside the device.
30912 uint32_t queue_id3_min_bw;
30913 /* The bandwidth value. */
30914 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MIN_BW_BW_VALUE_MASK \
30915 UINT32_C(0xfffffff)
30916 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MIN_BW_BW_VALUE_SFT \
30918 /* The granularity of the value (bits or bytes). */
30919 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MIN_BW_SCALE \
30920 UINT32_C(0x10000000)
30921 /* Value is in bits. */
30922 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MIN_BW_SCALE_BITS \
30923 (UINT32_C(0x0) << 28)
30924 /* Value is in bytes. */
30925 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MIN_BW_SCALE_BYTES \
30926 (UINT32_C(0x1) << 28)
30927 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MIN_BW_SCALE_LAST \
30928 HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MIN_BW_SCALE_BYTES
30929 /* bw_value_unit is 3 b */
30930 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_MASK \
30931 UINT32_C(0xe0000000)
30932 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_SFT \
30934 /* Value is in Mb or MB (base 10). */
30935 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_MEGA \
30936 (UINT32_C(0x0) << 29)
30937 /* Value is in Kb or KB (base 10). */
30938 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_KILO \
30939 (UINT32_C(0x2) << 29)
30940 /* Value is in bits or bytes. */
30941 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_BASE \
30942 (UINT32_C(0x4) << 29)
30943 /* Value is in Gb or GB (base 10). */
30944 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_GIGA \
30945 (UINT32_C(0x6) << 29)
30946 /* Value is in 1/100th of a percentage of total bandwidth. */
30947 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 \
30948 (UINT32_C(0x1) << 29)
30950 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_INVALID \
30951 (UINT32_C(0x7) << 29)
30952 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_LAST \
30953 HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_INVALID
30955 * Maximum BW allocated to CoS queue.
30956 * The HWRM will translate this value into byte counter and
30957 * time interval used for this COS inside the device.
30959 uint32_t queue_id3_max_bw;
30960 /* The bandwidth value. */
30961 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MAX_BW_BW_VALUE_MASK \
30962 UINT32_C(0xfffffff)
30963 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MAX_BW_BW_VALUE_SFT \
30965 /* The granularity of the value (bits or bytes). */
30966 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MAX_BW_SCALE \
30967 UINT32_C(0x10000000)
30968 /* Value is in bits. */
30969 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MAX_BW_SCALE_BITS \
30970 (UINT32_C(0x0) << 28)
30971 /* Value is in bytes. */
30972 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MAX_BW_SCALE_BYTES \
30973 (UINT32_C(0x1) << 28)
30974 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MAX_BW_SCALE_LAST \
30975 HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MAX_BW_SCALE_BYTES
30976 /* bw_value_unit is 3 b */
30977 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_MASK \
30978 UINT32_C(0xe0000000)
30979 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_SFT \
30981 /* Value is in Mb or MB (base 10). */
30982 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_MEGA \
30983 (UINT32_C(0x0) << 29)
30984 /* Value is in Kb or KB (base 10). */
30985 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_KILO \
30986 (UINT32_C(0x2) << 29)
30987 /* Value is in bits or bytes. */
30988 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_BASE \
30989 (UINT32_C(0x4) << 29)
30990 /* Value is in Gb or GB (base 10). */
30991 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_GIGA \
30992 (UINT32_C(0x6) << 29)
30993 /* Value is in 1/100th of a percentage of total bandwidth. */
30994 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 \
30995 (UINT32_C(0x1) << 29)
30997 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_INVALID \
30998 (UINT32_C(0x7) << 29)
30999 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_LAST \
31000 HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_INVALID
31001 /* Transmission Selection Algorithm (TSA) for CoS Queue. */
31002 uint8_t queue_id3_tsa_assign;
31003 /* Strict Priority */
31004 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_TSA_ASSIGN_SP \
31006 /* Enhanced Transmission Selection */
31007 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_TSA_ASSIGN_ETS \
31010 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_TSA_ASSIGN_RESERVED_FIRST \
31013 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_TSA_ASSIGN_RESERVED_LAST \
31016 * Priority level for strict priority. Valid only when the
31017 * tsa_assign is 0 - Strict Priority (SP)
31018 * 0..7 - Valid values.
31019 * 8..255 - Reserved.
31021 uint8_t queue_id3_pri_lvl;
31023 * Weight used to allocate remaining BW for this COS after
31024 * servicing guaranteed bandwidths for all COS.
31026 uint8_t queue_id3_bw_weight;
31027 /* ID of CoS Queue 4. */
31030 * Minimum BW allocated to CoS Queue.
31031 * The HWRM will translate this value into byte counter and
31032 * time interval used for this COS inside the device.
31034 uint32_t queue_id4_min_bw;
31035 /* The bandwidth value. */
31036 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MIN_BW_BW_VALUE_MASK \
31037 UINT32_C(0xfffffff)
31038 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MIN_BW_BW_VALUE_SFT \
31040 /* The granularity of the value (bits or bytes). */
31041 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MIN_BW_SCALE \
31042 UINT32_C(0x10000000)
31043 /* Value is in bits. */
31044 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MIN_BW_SCALE_BITS \
31045 (UINT32_C(0x0) << 28)
31046 /* Value is in bytes. */
31047 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MIN_BW_SCALE_BYTES \
31048 (UINT32_C(0x1) << 28)
31049 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MIN_BW_SCALE_LAST \
31050 HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MIN_BW_SCALE_BYTES
31051 /* bw_value_unit is 3 b */
31052 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_MASK \
31053 UINT32_C(0xe0000000)
31054 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_SFT \
31056 /* Value is in Mb or MB (base 10). */
31057 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_MEGA \
31058 (UINT32_C(0x0) << 29)
31059 /* Value is in Kb or KB (base 10). */
31060 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_KILO \
31061 (UINT32_C(0x2) << 29)
31062 /* Value is in bits or bytes. */
31063 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_BASE \
31064 (UINT32_C(0x4) << 29)
31065 /* Value is in Gb or GB (base 10). */
31066 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_GIGA \
31067 (UINT32_C(0x6) << 29)
31068 /* Value is in 1/100th of a percentage of total bandwidth. */
31069 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 \
31070 (UINT32_C(0x1) << 29)
31072 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_INVALID \
31073 (UINT32_C(0x7) << 29)
31074 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_LAST \
31075 HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_INVALID
31077 * Maximum BW allocated to CoS queue.
31078 * The HWRM will translate this value into byte counter and
31079 * time interval used for this COS inside the device.
31081 uint32_t queue_id4_max_bw;
31082 /* The bandwidth value. */
31083 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MAX_BW_BW_VALUE_MASK \
31084 UINT32_C(0xfffffff)
31085 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MAX_BW_BW_VALUE_SFT \
31087 /* The granularity of the value (bits or bytes). */
31088 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MAX_BW_SCALE \
31089 UINT32_C(0x10000000)
31090 /* Value is in bits. */
31091 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MAX_BW_SCALE_BITS \
31092 (UINT32_C(0x0) << 28)
31093 /* Value is in bytes. */
31094 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MAX_BW_SCALE_BYTES \
31095 (UINT32_C(0x1) << 28)
31096 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MAX_BW_SCALE_LAST \
31097 HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MAX_BW_SCALE_BYTES
31098 /* bw_value_unit is 3 b */
31099 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_MASK \
31100 UINT32_C(0xe0000000)
31101 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_SFT \
31103 /* Value is in Mb or MB (base 10). */
31104 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_MEGA \
31105 (UINT32_C(0x0) << 29)
31106 /* Value is in Kb or KB (base 10). */
31107 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_KILO \
31108 (UINT32_C(0x2) << 29)
31109 /* Value is in bits or bytes. */
31110 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_BASE \
31111 (UINT32_C(0x4) << 29)
31112 /* Value is in Gb or GB (base 10). */
31113 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_GIGA \
31114 (UINT32_C(0x6) << 29)
31115 /* Value is in 1/100th of a percentage of total bandwidth. */
31116 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 \
31117 (UINT32_C(0x1) << 29)
31119 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_INVALID \
31120 (UINT32_C(0x7) << 29)
31121 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_LAST \
31122 HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_INVALID
31123 /* Transmission Selection Algorithm (TSA) for CoS Queue. */
31124 uint8_t queue_id4_tsa_assign;
31125 /* Strict Priority */
31126 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_TSA_ASSIGN_SP \
31128 /* Enhanced Transmission Selection */
31129 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_TSA_ASSIGN_ETS \
31132 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_TSA_ASSIGN_RESERVED_FIRST \
31135 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_TSA_ASSIGN_RESERVED_LAST \
31138 * Priority level for strict priority. Valid only when the
31139 * tsa_assign is 0 - Strict Priority (SP)
31140 * 0..7 - Valid values.
31141 * 8..255 - Reserved.
31143 uint8_t queue_id4_pri_lvl;
31145 * Weight used to allocate remaining BW for this COS after
31146 * servicing guaranteed bandwidths for all COS.
31148 uint8_t queue_id4_bw_weight;
31149 /* ID of CoS Queue 5. */
31152 * Minimum BW allocated to CoS Queue.
31153 * The HWRM will translate this value into byte counter and
31154 * time interval used for this COS inside the device.
31156 uint32_t queue_id5_min_bw;
31157 /* The bandwidth value. */
31158 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MIN_BW_BW_VALUE_MASK \
31159 UINT32_C(0xfffffff)
31160 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MIN_BW_BW_VALUE_SFT \
31162 /* The granularity of the value (bits or bytes). */
31163 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MIN_BW_SCALE \
31164 UINT32_C(0x10000000)
31165 /* Value is in bits. */
31166 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MIN_BW_SCALE_BITS \
31167 (UINT32_C(0x0) << 28)
31168 /* Value is in bytes. */
31169 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MIN_BW_SCALE_BYTES \
31170 (UINT32_C(0x1) << 28)
31171 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MIN_BW_SCALE_LAST \
31172 HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MIN_BW_SCALE_BYTES
31173 /* bw_value_unit is 3 b */
31174 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_MASK \
31175 UINT32_C(0xe0000000)
31176 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_SFT \
31178 /* Value is in Mb or MB (base 10). */
31179 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_MEGA \
31180 (UINT32_C(0x0) << 29)
31181 /* Value is in Kb or KB (base 10). */
31182 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_KILO \
31183 (UINT32_C(0x2) << 29)
31184 /* Value is in bits or bytes. */
31185 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_BASE \
31186 (UINT32_C(0x4) << 29)
31187 /* Value is in Gb or GB (base 10). */
31188 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_GIGA \
31189 (UINT32_C(0x6) << 29)
31190 /* Value is in 1/100th of a percentage of total bandwidth. */
31191 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 \
31192 (UINT32_C(0x1) << 29)
31194 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_INVALID \
31195 (UINT32_C(0x7) << 29)
31196 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_LAST \
31197 HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_INVALID
31199 * Maximum BW allocated to CoS queue.
31200 * The HWRM will translate this value into byte counter and
31201 * time interval used for this COS inside the device.
31203 uint32_t queue_id5_max_bw;
31204 /* The bandwidth value. */
31205 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MAX_BW_BW_VALUE_MASK \
31206 UINT32_C(0xfffffff)
31207 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MAX_BW_BW_VALUE_SFT \
31209 /* The granularity of the value (bits or bytes). */
31210 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MAX_BW_SCALE \
31211 UINT32_C(0x10000000)
31212 /* Value is in bits. */
31213 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MAX_BW_SCALE_BITS \
31214 (UINT32_C(0x0) << 28)
31215 /* Value is in bytes. */
31216 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MAX_BW_SCALE_BYTES \
31217 (UINT32_C(0x1) << 28)
31218 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MAX_BW_SCALE_LAST \
31219 HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MAX_BW_SCALE_BYTES
31220 /* bw_value_unit is 3 b */
31221 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_MASK \
31222 UINT32_C(0xe0000000)
31223 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_SFT \
31225 /* Value is in Mb or MB (base 10). */
31226 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_MEGA \
31227 (UINT32_C(0x0) << 29)
31228 /* Value is in Kb or KB (base 10). */
31229 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_KILO \
31230 (UINT32_C(0x2) << 29)
31231 /* Value is in bits or bytes. */
31232 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_BASE \
31233 (UINT32_C(0x4) << 29)
31234 /* Value is in Gb or GB (base 10). */
31235 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_GIGA \
31236 (UINT32_C(0x6) << 29)
31237 /* Value is in 1/100th of a percentage of total bandwidth. */
31238 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 \
31239 (UINT32_C(0x1) << 29)
31241 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_INVALID \
31242 (UINT32_C(0x7) << 29)
31243 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_LAST \
31244 HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_INVALID
31245 /* Transmission Selection Algorithm (TSA) for CoS Queue. */
31246 uint8_t queue_id5_tsa_assign;
31247 /* Strict Priority */
31248 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_TSA_ASSIGN_SP \
31250 /* Enhanced Transmission Selection */
31251 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_TSA_ASSIGN_ETS \
31254 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_TSA_ASSIGN_RESERVED_FIRST \
31257 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_TSA_ASSIGN_RESERVED_LAST \
31260 * Priority level for strict priority. Valid only when the
31261 * tsa_assign is 0 - Strict Priority (SP)
31262 * 0..7 - Valid values.
31263 * 8..255 - Reserved.
31265 uint8_t queue_id5_pri_lvl;
31267 * Weight used to allocate remaining BW for this COS after
31268 * servicing guaranteed bandwidths for all COS.
31270 uint8_t queue_id5_bw_weight;
31271 /* ID of CoS Queue 6. */
31274 * Minimum BW allocated to CoS Queue.
31275 * The HWRM will translate this value into byte counter and
31276 * time interval used for this COS inside the device.
31278 uint32_t queue_id6_min_bw;
31279 /* The bandwidth value. */
31280 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MIN_BW_BW_VALUE_MASK \
31281 UINT32_C(0xfffffff)
31282 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MIN_BW_BW_VALUE_SFT \
31284 /* The granularity of the value (bits or bytes). */
31285 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MIN_BW_SCALE \
31286 UINT32_C(0x10000000)
31287 /* Value is in bits. */
31288 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MIN_BW_SCALE_BITS \
31289 (UINT32_C(0x0) << 28)
31290 /* Value is in bytes. */
31291 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MIN_BW_SCALE_BYTES \
31292 (UINT32_C(0x1) << 28)
31293 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MIN_BW_SCALE_LAST \
31294 HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MIN_BW_SCALE_BYTES
31295 /* bw_value_unit is 3 b */
31296 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_MASK \
31297 UINT32_C(0xe0000000)
31298 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_SFT \
31300 /* Value is in Mb or MB (base 10). */
31301 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_MEGA \
31302 (UINT32_C(0x0) << 29)
31303 /* Value is in Kb or KB (base 10). */
31304 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_KILO \
31305 (UINT32_C(0x2) << 29)
31306 /* Value is in bits or bytes. */
31307 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_BASE \
31308 (UINT32_C(0x4) << 29)
31309 /* Value is in Gb or GB (base 10). */
31310 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_GIGA \
31311 (UINT32_C(0x6) << 29)
31312 /* Value is in 1/100th of a percentage of total bandwidth. */
31313 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 \
31314 (UINT32_C(0x1) << 29)
31316 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_INVALID \
31317 (UINT32_C(0x7) << 29)
31318 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_LAST \
31319 HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_INVALID
31321 * Maximum BW allocated to CoS queue.
31322 * The HWRM will translate this value into byte counter and
31323 * time interval used for this COS inside the device.
31325 uint32_t queue_id6_max_bw;
31326 /* The bandwidth value. */
31327 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MAX_BW_BW_VALUE_MASK \
31328 UINT32_C(0xfffffff)
31329 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MAX_BW_BW_VALUE_SFT \
31331 /* The granularity of the value (bits or bytes). */
31332 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MAX_BW_SCALE \
31333 UINT32_C(0x10000000)
31334 /* Value is in bits. */
31335 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MAX_BW_SCALE_BITS \
31336 (UINT32_C(0x0) << 28)
31337 /* Value is in bytes. */
31338 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MAX_BW_SCALE_BYTES \
31339 (UINT32_C(0x1) << 28)
31340 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MAX_BW_SCALE_LAST \
31341 HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MAX_BW_SCALE_BYTES
31342 /* bw_value_unit is 3 b */
31343 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_MASK \
31344 UINT32_C(0xe0000000)
31345 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_SFT \
31347 /* Value is in Mb or MB (base 10). */
31348 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_MEGA \
31349 (UINT32_C(0x0) << 29)
31350 /* Value is in Kb or KB (base 10). */
31351 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_KILO \
31352 (UINT32_C(0x2) << 29)
31353 /* Value is in bits or bytes. */
31354 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_BASE \
31355 (UINT32_C(0x4) << 29)
31356 /* Value is in Gb or GB (base 10). */
31357 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_GIGA \
31358 (UINT32_C(0x6) << 29)
31359 /* Value is in 1/100th of a percentage of total bandwidth. */
31360 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 \
31361 (UINT32_C(0x1) << 29)
31363 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_INVALID \
31364 (UINT32_C(0x7) << 29)
31365 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_LAST \
31366 HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_INVALID
31367 /* Transmission Selection Algorithm (TSA) for CoS Queue. */
31368 uint8_t queue_id6_tsa_assign;
31369 /* Strict Priority */
31370 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_TSA_ASSIGN_SP \
31372 /* Enhanced Transmission Selection */
31373 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_TSA_ASSIGN_ETS \
31376 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_TSA_ASSIGN_RESERVED_FIRST \
31379 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_TSA_ASSIGN_RESERVED_LAST \
31382 * Priority level for strict priority. Valid only when the
31383 * tsa_assign is 0 - Strict Priority (SP)
31384 * 0..7 - Valid values.
31385 * 8..255 - Reserved.
31387 uint8_t queue_id6_pri_lvl;
31389 * Weight used to allocate remaining BW for this COS after
31390 * servicing guaranteed bandwidths for all COS.
31392 uint8_t queue_id6_bw_weight;
31393 /* ID of CoS Queue 7. */
31396 * Minimum BW allocated to CoS Queue.
31397 * The HWRM will translate this value into byte counter and
31398 * time interval used for this COS inside the device.
31400 uint32_t queue_id7_min_bw;
31401 /* The bandwidth value. */
31402 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MIN_BW_BW_VALUE_MASK \
31403 UINT32_C(0xfffffff)
31404 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MIN_BW_BW_VALUE_SFT \
31406 /* The granularity of the value (bits or bytes). */
31407 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MIN_BW_SCALE \
31408 UINT32_C(0x10000000)
31409 /* Value is in bits. */
31410 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MIN_BW_SCALE_BITS \
31411 (UINT32_C(0x0) << 28)
31412 /* Value is in bytes. */
31413 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MIN_BW_SCALE_BYTES \
31414 (UINT32_C(0x1) << 28)
31415 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MIN_BW_SCALE_LAST \
31416 HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MIN_BW_SCALE_BYTES
31417 /* bw_value_unit is 3 b */
31418 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_MASK \
31419 UINT32_C(0xe0000000)
31420 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_SFT \
31422 /* Value is in Mb or MB (base 10). */
31423 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_MEGA \
31424 (UINT32_C(0x0) << 29)
31425 /* Value is in Kb or KB (base 10). */
31426 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_KILO \
31427 (UINT32_C(0x2) << 29)
31428 /* Value is in bits or bytes. */
31429 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_BASE \
31430 (UINT32_C(0x4) << 29)
31431 /* Value is in Gb or GB (base 10). */
31432 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_GIGA \
31433 (UINT32_C(0x6) << 29)
31434 /* Value is in 1/100th of a percentage of total bandwidth. */
31435 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 \
31436 (UINT32_C(0x1) << 29)
31438 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_INVALID \
31439 (UINT32_C(0x7) << 29)
31440 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_LAST \
31441 HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_INVALID
31443 * Maximum BW allocated to CoS queue.
31444 * The HWRM will translate this value into byte counter and
31445 * time interval used for this COS inside the device.
31447 uint32_t queue_id7_max_bw;
31448 /* The bandwidth value. */
31449 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MAX_BW_BW_VALUE_MASK \
31450 UINT32_C(0xfffffff)
31451 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MAX_BW_BW_VALUE_SFT \
31453 /* The granularity of the value (bits or bytes). */
31454 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MAX_BW_SCALE \
31455 UINT32_C(0x10000000)
31456 /* Value is in bits. */
31457 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MAX_BW_SCALE_BITS \
31458 (UINT32_C(0x0) << 28)
31459 /* Value is in bytes. */
31460 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MAX_BW_SCALE_BYTES \
31461 (UINT32_C(0x1) << 28)
31462 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MAX_BW_SCALE_LAST \
31463 HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MAX_BW_SCALE_BYTES
31464 /* bw_value_unit is 3 b */
31465 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_MASK \
31466 UINT32_C(0xe0000000)
31467 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_SFT \
31469 /* Value is in Mb or MB (base 10). */
31470 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_MEGA \
31471 (UINT32_C(0x0) << 29)
31472 /* Value is in Kb or KB (base 10). */
31473 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_KILO \
31474 (UINT32_C(0x2) << 29)
31475 /* Value is in bits or bytes. */
31476 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_BASE \
31477 (UINT32_C(0x4) << 29)
31478 /* Value is in Gb or GB (base 10). */
31479 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_GIGA \
31480 (UINT32_C(0x6) << 29)
31481 /* Value is in 1/100th of a percentage of total bandwidth. */
31482 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 \
31483 (UINT32_C(0x1) << 29)
31485 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_INVALID \
31486 (UINT32_C(0x7) << 29)
31487 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_LAST \
31488 HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_INVALID
31489 /* Transmission Selection Algorithm (TSA) for CoS Queue. */
31490 uint8_t queue_id7_tsa_assign;
31491 /* Strict Priority */
31492 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_TSA_ASSIGN_SP \
31494 /* Enhanced Transmission Selection */
31495 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_TSA_ASSIGN_ETS \
31498 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_TSA_ASSIGN_RESERVED_FIRST \
31501 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_TSA_ASSIGN_RESERVED_LAST \
31504 * Priority level for strict priority. Valid only when the
31505 * tsa_assign is 0 - Strict Priority (SP)
31506 * 0..7 - Valid values.
31507 * 8..255 - Reserved.
31509 uint8_t queue_id7_pri_lvl;
31511 * Weight used to allocate remaining BW for this COS after
31512 * servicing guaranteed bandwidths for all COS.
31514 uint8_t queue_id7_bw_weight;
31515 uint8_t unused_1[5];
31518 /* hwrm_queue_cos2bw_cfg_output (size:128b/16B) */
31519 struct hwrm_queue_cos2bw_cfg_output {
31520 /* The specific error status for the command. */
31521 uint16_t error_code;
31522 /* The HWRM command request type. */
31524 /* The sequence ID from the original command. */
31526 /* The length of the response data in number of bytes. */
31528 uint8_t unused_0[7];
31530 * This field is used in Output records to indicate that the output
31531 * is completely written to RAM. This field should be read as '1'
31532 * to indicate that the output has been completely written.
31533 * When writing a command completion or response to an internal processor,
31534 * the order of writes has to be such that this field is written last.
31539 /*************************
31540 * hwrm_queue_dscp_qcaps *
31541 *************************/
31544 /* hwrm_queue_dscp_qcaps_input (size:192b/24B) */
31545 struct hwrm_queue_dscp_qcaps_input {
31546 /* The HWRM command request type. */
31549 * The completion ring to send the completion event on. This should
31550 * be the NQ ID returned from the `nq_alloc` HWRM command.
31552 uint16_t cmpl_ring;
31554 * The sequence ID is used by the driver for tracking multiple
31555 * commands. This ID is treated as opaque data by the firmware and
31556 * the value is returned in the `hwrm_resp_hdr` upon completion.
31560 * The target ID of the command:
31561 * * 0x0-0xFFF8 - The function ID
31562 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
31563 * * 0xFFFD - Reserved for user-space HWRM interface
31566 uint16_t target_id;
31568 * A physical address pointer pointing to a host buffer that the
31569 * command's response data will be written. This can be either a host
31570 * physical address (HPA) or a guest physical address (GPA) and must
31571 * point to a physically contiguous block of memory.
31573 uint64_t resp_addr;
31575 * Port ID of port for which the table is being configured.
31576 * The HWRM needs to check whether this function is allowed
31577 * to configure pri2cos mapping on this port.
31580 uint8_t unused_0[7];
31583 /* hwrm_queue_dscp_qcaps_output (size:128b/16B) */
31584 struct hwrm_queue_dscp_qcaps_output {
31585 /* The specific error status for the command. */
31586 uint16_t error_code;
31587 /* The HWRM command request type. */
31589 /* The sequence ID from the original command. */
31591 /* The length of the response data in number of bytes. */
31593 /* The number of bits provided by the hardware for the DSCP value. */
31594 uint8_t num_dscp_bits;
31596 /* Max number of DSCP-MASK-PRI entries supported. */
31597 uint16_t max_entries;
31598 uint8_t unused_1[3];
31600 * This field is used in Output records to indicate that the output
31601 * is completely written to RAM. This field should be read as '1'
31602 * to indicate that the output has been completely written.
31603 * When writing a command completion or response to an internal processor,
31604 * the order of writes has to be such that this field is written last.
31609 /****************************
31610 * hwrm_queue_dscp2pri_qcfg *
31611 ****************************/
31614 /* hwrm_queue_dscp2pri_qcfg_input (size:256b/32B) */
31615 struct hwrm_queue_dscp2pri_qcfg_input {
31616 /* The HWRM command request type. */
31619 * The completion ring to send the completion event on. This should
31620 * be the NQ ID returned from the `nq_alloc` HWRM command.
31622 uint16_t cmpl_ring;
31624 * The sequence ID is used by the driver for tracking multiple
31625 * commands. This ID is treated as opaque data by the firmware and
31626 * the value is returned in the `hwrm_resp_hdr` upon completion.
31630 * The target ID of the command:
31631 * * 0x0-0xFFF8 - The function ID
31632 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
31633 * * 0xFFFD - Reserved for user-space HWRM interface
31636 uint16_t target_id;
31638 * A physical address pointer pointing to a host buffer that the
31639 * command's response data will be written. This can be either a host
31640 * physical address (HPA) or a guest physical address (GPA) and must
31641 * point to a physically contiguous block of memory.
31643 uint64_t resp_addr;
31645 * This is the host address where the 24-bits DSCP-MASK-PRI
31646 * tuple(s) will be copied to.
31648 uint64_t dest_data_addr;
31650 * Port ID of port for which the table is being configured.
31651 * The HWRM needs to check whether this function is allowed
31652 * to configure pri2cos mapping on this port.
31656 /* Size of the buffer pointed to by dest_data_addr. */
31657 uint16_t dest_data_buffer_size;
31658 uint8_t unused_1[4];
31661 /* hwrm_queue_dscp2pri_qcfg_output (size:128b/16B) */
31662 struct hwrm_queue_dscp2pri_qcfg_output {
31663 /* The specific error status for the command. */
31664 uint16_t error_code;
31665 /* The HWRM command request type. */
31667 /* The sequence ID from the original command. */
31669 /* The length of the response data in number of bytes. */
31672 * A count of the number of DSCP-MASK-PRI tuple(s) pointed to
31673 * by the dest_data_addr.
31675 uint16_t entry_cnt;
31677 * This is the default PRI which un-initialized DSCP values are
31680 uint8_t default_pri;
31681 uint8_t unused_0[4];
31683 * This field is used in Output records to indicate that the output
31684 * is completely written to RAM. This field should be read as '1'
31685 * to indicate that the output has been completely written.
31686 * When writing a command completion or response to an internal processor,
31687 * the order of writes has to be such that this field is written last.
31692 /***************************
31693 * hwrm_queue_dscp2pri_cfg *
31694 ***************************/
31697 /* hwrm_queue_dscp2pri_cfg_input (size:320b/40B) */
31698 struct hwrm_queue_dscp2pri_cfg_input {
31699 /* The HWRM command request type. */
31702 * The completion ring to send the completion event on. This should
31703 * be the NQ ID returned from the `nq_alloc` HWRM command.
31705 uint16_t cmpl_ring;
31707 * The sequence ID is used by the driver for tracking multiple
31708 * commands. This ID is treated as opaque data by the firmware and
31709 * the value is returned in the `hwrm_resp_hdr` upon completion.
31713 * The target ID of the command:
31714 * * 0x0-0xFFF8 - The function ID
31715 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
31716 * * 0xFFFD - Reserved for user-space HWRM interface
31719 uint16_t target_id;
31721 * A physical address pointer pointing to a host buffer that the
31722 * command's response data will be written. This can be either a host
31723 * physical address (HPA) or a guest physical address (GPA) and must
31724 * point to a physically contiguous block of memory.
31726 uint64_t resp_addr;
31728 * This is the host address where the 24-bits DSCP-MASK-PRI tuple
31729 * will be copied from.
31731 uint64_t src_data_addr;
31733 /* use_hw_default_pri is 1 b */
31734 #define HWRM_QUEUE_DSCP2PRI_CFG_INPUT_FLAGS_USE_HW_DEFAULT_PRI \
31738 * This bit must be '1' for the default_pri field to be
31741 #define HWRM_QUEUE_DSCP2PRI_CFG_INPUT_ENABLES_DEFAULT_PRI \
31744 * Port ID of port for which the table is being configured.
31745 * The HWRM needs to check whether this function is allowed
31746 * to configure pri2cos mapping on this port.
31750 * This is the default PRI which un-initialized DSCP values will be
31753 uint8_t default_pri;
31755 * A count of the number of DSCP-MASK-PRI tuple(s) in the data pointed
31756 * to by src_data_addr.
31758 uint16_t entry_cnt;
31759 uint8_t unused_0[4];
31762 /* hwrm_queue_dscp2pri_cfg_output (size:128b/16B) */
31763 struct hwrm_queue_dscp2pri_cfg_output {
31764 /* The specific error status for the command. */
31765 uint16_t error_code;
31766 /* The HWRM command request type. */
31768 /* The sequence ID from the original command. */
31770 /* The length of the response data in number of bytes. */
31772 uint8_t unused_0[7];
31774 * This field is used in Output records to indicate that the output
31775 * is completely written to RAM. This field should be read as '1'
31776 * to indicate that the output has been completely written.
31777 * When writing a command completion or response to an internal processor,
31778 * the order of writes has to be such that this field is written last.
31783 /*************************
31784 * hwrm_queue_mpls_qcaps *
31785 *************************/
31788 /* hwrm_queue_mpls_qcaps_input (size:192b/24B) */
31789 struct hwrm_queue_mpls_qcaps_input {
31790 /* The HWRM command request type. */
31793 * The completion ring to send the completion event on. This should
31794 * be the NQ ID returned from the `nq_alloc` HWRM command.
31796 uint16_t cmpl_ring;
31798 * The sequence ID is used by the driver for tracking multiple
31799 * commands. This ID is treated as opaque data by the firmware and
31800 * the value is returned in the `hwrm_resp_hdr` upon completion.
31804 * The target ID of the command:
31805 * * 0x0-0xFFF8 - The function ID
31806 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
31807 * * 0xFFFD - Reserved for user-space HWRM interface
31810 uint16_t target_id;
31812 * A physical address pointer pointing to a host buffer that the
31813 * command's response data will be written. This can be either a host
31814 * physical address (HPA) or a guest physical address (GPA) and must
31815 * point to a physically contiguous block of memory.
31817 uint64_t resp_addr;
31819 * Port ID of port for which the table is being configured.
31820 * The HWRM needs to check whether this function is allowed
31821 * to configure MPLS TC(EXP) to pri mapping on this port.
31824 uint8_t unused_0[7];
31827 /* hwrm_queue_mpls_qcaps_output (size:128b/16B) */
31828 struct hwrm_queue_mpls_qcaps_output {
31829 /* The specific error status for the command. */
31830 uint16_t error_code;
31831 /* The HWRM command request type. */
31833 /* The sequence ID from the original command. */
31835 /* The length of the response data in number of bytes. */
31838 * Bitmask indicating which queues can be configured by the
31839 * hwrm_queue_mplstc2pri_cfg command.
31841 * Each bit represents a specific pri where bit 0 represents
31842 * pri 0 and bit 7 represents pri 7.
31843 * # A value of 0 indicates that the pri is not configurable
31844 * by the hwrm_queue_mplstc2pri_cfg command.
31845 * # A value of 1 indicates that the pri is configurable.
31846 * # A hwrm_queue_mplstc2pri_cfg command shall return error when
31847 * trying to configure a pri that is not configurable.
31849 uint8_t queue_mplstc2pri_cfg_allowed;
31851 * This is the default PRI which un-initialized MPLS values will be
31854 uint8_t hw_default_pri;
31855 uint8_t unused_0[5];
31857 * This field is used in Output records to indicate that the output
31858 * is completely written to RAM. This field should be read as '1'
31859 * to indicate that the output has been completely written.
31860 * When writing a command completion or response to an internal processor,
31861 * the order of writes has to be such that this field is written last.
31866 /******************************
31867 * hwrm_queue_mplstc2pri_qcfg *
31868 ******************************/
31871 /* hwrm_queue_mplstc2pri_qcfg_input (size:192b/24B) */
31872 struct hwrm_queue_mplstc2pri_qcfg_input {
31873 /* The HWRM command request type. */
31876 * The completion ring to send the completion event on. This should
31877 * be the NQ ID returned from the `nq_alloc` HWRM command.
31879 uint16_t cmpl_ring;
31881 * The sequence ID is used by the driver for tracking multiple
31882 * commands. This ID is treated as opaque data by the firmware and
31883 * the value is returned in the `hwrm_resp_hdr` upon completion.
31887 * The target ID of the command:
31888 * * 0x0-0xFFF8 - The function ID
31889 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
31890 * * 0xFFFD - Reserved for user-space HWRM interface
31893 uint16_t target_id;
31895 * A physical address pointer pointing to a host buffer that the
31896 * command's response data will be written. This can be either a host
31897 * physical address (HPA) or a guest physical address (GPA) and must
31898 * point to a physically contiguous block of memory.
31900 uint64_t resp_addr;
31902 * Port ID of port for which the table is being configured.
31903 * The HWRM needs to check whether this function is allowed
31904 * to configure MPLS TC(EXP) to pri mapping on this port.
31907 uint8_t unused_0[7];
31910 /* hwrm_queue_mplstc2pri_qcfg_output (size:192b/24B) */
31911 struct hwrm_queue_mplstc2pri_qcfg_output {
31912 /* The specific error status for the command. */
31913 uint16_t error_code;
31914 /* The HWRM command request type. */
31916 /* The sequence ID from the original command. */
31918 /* The length of the response data in number of bytes. */
31921 * pri assigned to MPLS TC(EXP) 0. This value can only be changed
31922 * before traffic has started.
31923 * A value of 0xff indicates that no pri is assigned to the
31926 uint8_t tc0_pri_queue_id;
31928 * pri assigned to MPLS TC(EXP) 1. This value can only be changed
31929 * before traffic has started.
31930 * A value of 0xff indicates that no pri is assigned to the
31933 uint8_t tc1_pri_queue_id;
31935 * pri assigned to MPLS TC(EXP) 2. This value can only be changed
31936 * before traffic has started.
31937 * A value of 0xff indicates that no pri is assigned to the
31940 uint8_t tc2_pri_queue_id;
31942 * pri assigned to MPLS TC(EXP) 3. This value can only be changed
31943 * before traffic has started.
31944 * A value of 0xff indicates that no pri is assigned to the
31947 uint8_t tc3_pri_queue_id;
31949 * pri assigned to MPLS TC(EXP) 4. This value can only be changed
31950 * before traffic has started.
31951 * A value of 0xff indicates that no pri is assigned to the
31954 uint8_t tc4_pri_queue_id;
31956 * pri assigned to MPLS TC(EXP) 5. This value can only be changed
31957 * before traffic has started.
31958 * A value of 0xff indicates that no pri is assigned to the
31961 uint8_t tc5_pri_queue_id;
31963 * pri assigned to MPLS TC(EXP) 6. This value can only
31964 * be changed before traffic has started.
31965 * A value of 0xff indicates that no pri is assigned to the
31968 uint8_t tc6_pri_queue_id;
31970 * pri assigned to MPLS TC(EXP) 7. This value can only
31971 * be changed before traffic has started.
31972 * A value of 0xff indicates that no pri is assigned to the
31975 uint8_t tc7_pri_queue_id;
31976 uint8_t unused_0[7];
31978 * This field is used in Output records to indicate that the output
31979 * is completely written to RAM. This field should be read as '1'
31980 * to indicate that the output has been completely written.
31981 * When writing a command completion or response to an internal processor,
31982 * the order of writes has to be such that this field is written last.
31987 /*****************************
31988 * hwrm_queue_mplstc2pri_cfg *
31989 *****************************/
31992 /* hwrm_queue_mplstc2pri_cfg_input (size:256b/32B) */
31993 struct hwrm_queue_mplstc2pri_cfg_input {
31994 /* The HWRM command request type. */
31997 * The completion ring to send the completion event on. This should
31998 * be the NQ ID returned from the `nq_alloc` HWRM command.
32000 uint16_t cmpl_ring;
32002 * The sequence ID is used by the driver for tracking multiple
32003 * commands. This ID is treated as opaque data by the firmware and
32004 * the value is returned in the `hwrm_resp_hdr` upon completion.
32008 * The target ID of the command:
32009 * * 0x0-0xFFF8 - The function ID
32010 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
32011 * * 0xFFFD - Reserved for user-space HWRM interface
32014 uint16_t target_id;
32016 * A physical address pointer pointing to a host buffer that the
32017 * command's response data will be written. This can be either a host
32018 * physical address (HPA) or a guest physical address (GPA) and must
32019 * point to a physically contiguous block of memory.
32021 uint64_t resp_addr;
32024 * This bit must be '1' for the mplstc0_pri_queue_id field to be
32027 #define HWRM_QUEUE_MPLSTC2PRI_CFG_INPUT_ENABLES_TC0_PRI_QUEUE_ID \
32030 * This bit must be '1' for the mplstc1_pri_queue_id field to be
32033 #define HWRM_QUEUE_MPLSTC2PRI_CFG_INPUT_ENABLES_TC1_PRI_QUEUE_ID \
32036 * This bit must be '1' for the mplstc2_pri_queue_id field to be
32039 #define HWRM_QUEUE_MPLSTC2PRI_CFG_INPUT_ENABLES_TC2_PRI_QUEUE_ID \
32042 * This bit must be '1' for the mplstc3_pri_queue_id field to be
32045 #define HWRM_QUEUE_MPLSTC2PRI_CFG_INPUT_ENABLES_TC3_PRI_QUEUE_ID \
32048 * This bit must be '1' for the mplstc4_pri_queue_id field to be
32051 #define HWRM_QUEUE_MPLSTC2PRI_CFG_INPUT_ENABLES_TC4_PRI_QUEUE_ID \
32054 * This bit must be '1' for the mplstc5_pri_queue_id field to be
32057 #define HWRM_QUEUE_MPLSTC2PRI_CFG_INPUT_ENABLES_TC5_PRI_QUEUE_ID \
32060 * This bit must be '1' for the mplstc6_pri_queue_id field to be
32063 #define HWRM_QUEUE_MPLSTC2PRI_CFG_INPUT_ENABLES_TC6_PRI_QUEUE_ID \
32066 * This bit must be '1' for the mplstc7_pri_queue_id field to be
32069 #define HWRM_QUEUE_MPLSTC2PRI_CFG_INPUT_ENABLES_TC7_PRI_QUEUE_ID \
32072 * Port ID of port for which the table is being configured.
32073 * The HWRM needs to check whether this function is allowed
32074 * to configure MPLS TC(EXP)to pri mapping on this port.
32077 uint8_t unused_0[3];
32079 * pri assigned to MPLS TC(EXP) 0. This value can only
32080 * be changed before traffic has started.
32082 uint8_t tc0_pri_queue_id;
32084 * pri assigned to MPLS TC(EXP) 1. This value can only
32085 * be changed before traffic has started.
32087 uint8_t tc1_pri_queue_id;
32089 * pri assigned to MPLS TC(EXP) 2 This value can only
32090 * be changed before traffic has started.
32092 uint8_t tc2_pri_queue_id;
32094 * pri assigned to MPLS TC(EXP) 3. This value can only
32095 * be changed before traffic has started.
32097 uint8_t tc3_pri_queue_id;
32099 * pri assigned to MPLS TC(EXP) 4. This value can only
32100 * be changed before traffic has started.
32102 uint8_t tc4_pri_queue_id;
32104 * pri assigned to MPLS TC(EXP) 5. This value can only
32105 * be changed before traffic has started.
32107 uint8_t tc5_pri_queue_id;
32109 * pri assigned to MPLS TC(EXP) 6. This value can only
32110 * be changed before traffic has started.
32112 uint8_t tc6_pri_queue_id;
32114 * pri assigned to MPLS TC(EXP) 7. This value can only
32115 * be changed before traffic has started.
32117 uint8_t tc7_pri_queue_id;
32120 /* hwrm_queue_mplstc2pri_cfg_output (size:128b/16B) */
32121 struct hwrm_queue_mplstc2pri_cfg_output {
32122 /* The specific error status for the command. */
32123 uint16_t error_code;
32124 /* The HWRM command request type. */
32126 /* The sequence ID from the original command. */
32128 /* The length of the response data in number of bytes. */
32130 uint8_t unused_0[7];
32132 * This field is used in Output records to indicate that the output
32133 * is completely written to RAM. This field should be read as '1'
32134 * to indicate that the output has been completely written.
32135 * When writing a command completion or response to an internal processor,
32136 * the order of writes has to be such that this field is written last.
32141 /****************************
32142 * hwrm_queue_vlanpri_qcaps *
32143 ****************************/
32146 /* hwrm_queue_vlanpri_qcaps_input (size:192b/24B) */
32147 struct hwrm_queue_vlanpri_qcaps_input {
32148 /* The HWRM command request type. */
32151 * The completion ring to send the completion event on. This should
32152 * be the NQ ID returned from the `nq_alloc` HWRM command.
32154 uint16_t cmpl_ring;
32156 * The sequence ID is used by the driver for tracking multiple
32157 * commands. This ID is treated as opaque data by the firmware and
32158 * the value is returned in the `hwrm_resp_hdr` upon completion.
32162 * The target ID of the command:
32163 * * 0x0-0xFFF8 - The function ID
32164 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
32165 * * 0xFFFD - Reserved for user-space HWRM interface
32168 uint16_t target_id;
32170 * A physical address pointer pointing to a host buffer that the
32171 * command's response data will be written. This can be either a host
32172 * physical address (HPA) or a guest physical address (GPA) and must
32173 * point to a physically contiguous block of memory.
32175 uint64_t resp_addr;
32177 * Port ID of port for which the table is being configured.
32178 * The HWRM needs to check whether this function is allowed
32179 * to configure VLAN priority to user priority mapping on this port.
32182 uint8_t unused_0[7];
32185 /* hwrm_queue_vlanpri_qcaps_output (size:128b/16B) */
32186 struct hwrm_queue_vlanpri_qcaps_output {
32187 /* The specific error status for the command. */
32188 uint16_t error_code;
32189 /* The HWRM command request type. */
32191 /* The sequence ID from the original command. */
32193 /* The length of the response data in number of bytes. */
32196 * This is the default user priority which all VLAN priority values
32197 * are mapped to if there is no VLAN priority to user priority mapping.
32199 uint8_t hw_default_pri;
32200 uint8_t unused_0[6];
32202 * This field is used in Output records to indicate that the output
32203 * is completely written to RAM. This field should be read as '1'
32204 * to indicate that the output has been completely written.
32205 * When writing a command completion or response to an internal processor,
32206 * the order of writes has to be such that this field is written last.
32211 /*******************************
32212 * hwrm_queue_vlanpri2pri_qcfg *
32213 *******************************/
32216 /* hwrm_queue_vlanpri2pri_qcfg_input (size:192b/24B) */
32217 struct hwrm_queue_vlanpri2pri_qcfg_input {
32218 /* The HWRM command request type. */
32221 * The completion ring to send the completion event on. This should
32222 * be the NQ ID returned from the `nq_alloc` HWRM command.
32224 uint16_t cmpl_ring;
32226 * The sequence ID is used by the driver for tracking multiple
32227 * commands. This ID is treated as opaque data by the firmware and
32228 * the value is returned in the `hwrm_resp_hdr` upon completion.
32232 * The target ID of the command:
32233 * * 0x0-0xFFF8 - The function ID
32234 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
32235 * * 0xFFFD - Reserved for user-space HWRM interface
32238 uint16_t target_id;
32240 * A physical address pointer pointing to a host buffer that the
32241 * command's response data will be written. This can be either a host
32242 * physical address (HPA) or a guest physical address (GPA) and must
32243 * point to a physically contiguous block of memory.
32245 uint64_t resp_addr;
32247 * Port ID of port for which the table is being configured.
32248 * The HWRM needs to check whether this function is allowed
32249 * to configure VLAN priority to user priority mapping on this port.
32252 uint8_t unused_0[7];
32255 /* hwrm_queue_vlanpri2pri_qcfg_output (size:192b/24B) */
32256 struct hwrm_queue_vlanpri2pri_qcfg_output {
32257 /* The specific error status for the command. */
32258 uint16_t error_code;
32259 /* The HWRM command request type. */
32261 /* The sequence ID from the original command. */
32263 /* The length of the response data in number of bytes. */
32266 * User priority assigned to VLAN priority 0. A value of 0xff
32267 * indicates that no user priority is assigned. The default user
32268 * priority will be used.
32270 uint8_t vlanpri0_user_pri_id;
32272 * User priority assigned to VLAN priority 1. A value of 0xff
32273 * indicates that no user priority is assigned. The default user
32274 * priority will be used.
32276 uint8_t vlanpri1_user_pri_id;
32278 * User priority assigned to VLAN priority 2. A value of 0xff
32279 * indicates that no user priority is assigned. The default user
32280 * priority will be used.
32282 uint8_t vlanpri2_user_pri_id;
32284 * User priority assigned to VLAN priority 3. A value of 0xff
32285 * indicates that no user priority is assigned. The default user
32286 * priority will be used.
32288 uint8_t vlanpri3_user_pri_id;
32290 * User priority assigned to VLAN priority 4. A value of 0xff
32291 * indicates that no user priority is assigned. The default user
32292 * priority will be used.
32294 uint8_t vlanpri4_user_pri_id;
32296 * User priority assigned to VLAN priority 5. A value of 0xff
32297 * indicates that no user priority is assigned. The default user
32298 * priority will be used.
32300 uint8_t vlanpri5_user_pri_id;
32302 * User priority assigned to VLAN priority 6. A value of 0xff
32303 * indicates that no user priority is assigned. The default user
32304 * priority will be used.
32306 uint8_t vlanpri6_user_pri_id;
32308 * User priority assigned to VLAN priority 7. A value of 0xff
32309 * indicates that no user priority is assigned. The default user
32310 * priority will be used.
32312 uint8_t vlanpri7_user_pri_id;
32313 uint8_t unused_0[7];
32315 * This field is used in Output records to indicate that the output
32316 * is completely written to RAM. This field should be read as '1'
32317 * to indicate that the output has been completely written.
32318 * When writing a command completion or response to an internal processor,
32319 * the order of writes has to be such that this field is written last.
32324 /******************************
32325 * hwrm_queue_vlanpri2pri_cfg *
32326 ******************************/
32329 /* hwrm_queue_vlanpri2pri_cfg_input (size:256b/32B) */
32330 struct hwrm_queue_vlanpri2pri_cfg_input {
32331 /* The HWRM command request type. */
32334 * The completion ring to send the completion event on. This should
32335 * be the NQ ID returned from the `nq_alloc` HWRM command.
32337 uint16_t cmpl_ring;
32339 * The sequence ID is used by the driver for tracking multiple
32340 * commands. This ID is treated as opaque data by the firmware and
32341 * the value is returned in the `hwrm_resp_hdr` upon completion.
32345 * The target ID of the command:
32346 * * 0x0-0xFFF8 - The function ID
32347 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
32348 * * 0xFFFD - Reserved for user-space HWRM interface
32351 uint16_t target_id;
32353 * A physical address pointer pointing to a host buffer that the
32354 * command's response data will be written. This can be either a host
32355 * physical address (HPA) or a guest physical address (GPA) and must
32356 * point to a physically contiguous block of memory.
32358 uint64_t resp_addr;
32361 * This bit must be '1' for the vlanpri0_user_pri_id field to be
32364 #define HWRM_QUEUE_VLANPRI2PRI_CFG_INPUT_ENABLES_VLANPRI0_USER_PRI_ID \
32367 * This bit must be '1' for the vlanpri1_user_pri_id field to be
32370 #define HWRM_QUEUE_VLANPRI2PRI_CFG_INPUT_ENABLES_VLANPRI1_USER_PRI_ID \
32373 * This bit must be '1' for the vlanpri2_user_pri_id field to be
32376 #define HWRM_QUEUE_VLANPRI2PRI_CFG_INPUT_ENABLES_VLANPRI2_USER_PRI_ID \
32379 * This bit must be '1' for the vlanpri3_user_pri_id field to be
32382 #define HWRM_QUEUE_VLANPRI2PRI_CFG_INPUT_ENABLES_VLANPRI3_USER_PRI_ID \
32385 * This bit must be '1' for the vlanpri4_user_pri_id field to be
32388 #define HWRM_QUEUE_VLANPRI2PRI_CFG_INPUT_ENABLES_VLANPRI4_USER_PRI_ID \
32391 * This bit must be '1' for the vlanpri5_user_pri_id field to be
32394 #define HWRM_QUEUE_VLANPRI2PRI_CFG_INPUT_ENABLES_VLANPRI5_USER_PRI_ID \
32397 * This bit must be '1' for the vlanpri6_user_pri_id field to be
32400 #define HWRM_QUEUE_VLANPRI2PRI_CFG_INPUT_ENABLES_VLANPRI6_USER_PRI_ID \
32403 * This bit must be '1' for the vlanpri7_user_pri_id field to be
32406 #define HWRM_QUEUE_VLANPRI2PRI_CFG_INPUT_ENABLES_VLANPRI7_USER_PRI_ID \
32409 * Port ID of port for which the table is being configured.
32410 * The HWRM needs to check whether this function is allowed
32411 * to configure VLAN priority to user priority mapping on this port.
32414 uint8_t unused_0[3];
32416 * User priority assigned to VLAN priority 0. This value can only
32417 * be changed before traffic has started.
32419 uint8_t vlanpri0_user_pri_id;
32421 * User priority assigned to VLAN priority 1. This value can only
32422 * be changed before traffic has started.
32424 uint8_t vlanpri1_user_pri_id;
32426 * User priority assigned to VLAN priority 2. This value can only
32427 * be changed before traffic has started.
32429 uint8_t vlanpri2_user_pri_id;
32431 * User priority assigned to VLAN priority 3. This value can only
32432 * be changed before traffic has started.
32434 uint8_t vlanpri3_user_pri_id;
32436 * User priority assigned to VLAN priority 4. This value can only
32437 * be changed before traffic has started.
32439 uint8_t vlanpri4_user_pri_id;
32441 * User priority assigned to VLAN priority 5. This value can only
32442 * be changed before traffic has started.
32444 uint8_t vlanpri5_user_pri_id;
32446 * User priority assigned to VLAN priority 6. This value can only
32447 * be changed before traffic has started.
32449 uint8_t vlanpri6_user_pri_id;
32451 * User priority assigned to VLAN priority 7. This value can only
32452 * be changed before traffic has started.
32454 uint8_t vlanpri7_user_pri_id;
32457 /* hwrm_queue_vlanpri2pri_cfg_output (size:128b/16B) */
32458 struct hwrm_queue_vlanpri2pri_cfg_output {
32459 /* The specific error status for the command. */
32460 uint16_t error_code;
32461 /* The HWRM command request type. */
32463 /* The sequence ID from the original command. */
32465 /* The length of the response data in number of bytes. */
32467 uint8_t unused_0[7];
32469 * This field is used in Output records to indicate that the output
32470 * is completely written to RAM. This field should be read as '1'
32471 * to indicate that the output has been completely written.
32472 * When writing a command completion or response to an internal processor,
32473 * the order of writes has to be such that this field is written last.
32478 /*************************
32479 * hwrm_queue_global_cfg *
32480 *************************/
32483 /* hwrm_queue_global_cfg_input (size:192b/24B) */
32484 struct hwrm_queue_global_cfg_input {
32485 /* The HWRM command request type. */
32488 * The completion ring to send the completion event on. This should
32489 * be the NQ ID returned from the `nq_alloc` HWRM command.
32491 uint16_t cmpl_ring;
32493 * The sequence ID is used by the driver for tracking multiple
32494 * commands. This ID is treated as opaque data by the firmware and
32495 * the value is returned in the `hwrm_resp_hdr` upon completion.
32499 * The target ID of the command:
32500 * * 0x0-0xFFF8 - The function ID
32501 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
32502 * * 0xFFFD - Reserved for user-space HWRM interface
32505 uint16_t target_id;
32507 * A physical address pointer pointing to a host buffer that the
32508 * command's response data will be written. This can be either a host
32509 * physical address (HPA) or a guest physical address (GPA) and must
32510 * point to a physically contiguous block of memory.
32512 uint64_t resp_addr;
32514 * Configuration mode for rx cos queues, configuring whether they
32515 * use one shared buffer pool (across ports or PCIe endpoints) or
32516 * independent per port or per endpoint buffer pools.
32519 /* One shared buffer pool to be used by all RX CoS queues */
32520 #define HWRM_QUEUE_GLOBAL_CFG_INPUT_MODE_SHARED UINT32_C(0x0)
32522 * Each port or PCIe endpoint to use an independent buffer pool
32523 * for its RX CoS queues
32525 #define HWRM_QUEUE_GLOBAL_CFG_INPUT_MODE_INDEPENDENT UINT32_C(0x1)
32526 #define HWRM_QUEUE_GLOBAL_CFG_INPUT_MODE_LAST \
32527 HWRM_QUEUE_GLOBAL_CFG_INPUT_MODE_INDEPENDENT
32530 /* This bit must be '1' when the mode field is configured. */
32531 #define HWRM_QUEUE_GLOBAL_CFG_INPUT_ENABLES_MODE UINT32_C(0x1)
32533 * This bit must be '1' when the maximum bandwidth for queue group 0
32534 * (g0_max_bw) is configured.
32536 #define HWRM_QUEUE_GLOBAL_CFG_INPUT_ENABLES_G0_MAX_BW UINT32_C(0x2)
32538 * This bit must be '1' when the maximum bandwidth for queue group 1
32539 * (g1_max_bw) is configured.
32541 #define HWRM_QUEUE_GLOBAL_CFG_INPUT_ENABLES_G1_MAX_BW UINT32_C(0x4)
32543 * This bit must be '1' when the maximum bandwidth for queue group 2
32544 * (g2_max_bw) is configured.
32546 #define HWRM_QUEUE_GLOBAL_CFG_INPUT_ENABLES_G2_MAX_BW UINT32_C(0x8)
32548 * This bit must be '1' when the maximum bandwidth for queue group 3
32549 * (g3_max_bw) is configured.
32551 #define HWRM_QUEUE_GLOBAL_CFG_INPUT_ENABLES_G3_MAX_BW \
32554 * Specifies the maximum receive rate, as a percentage of total link
32555 * bandwidth, of the receive traffic through queue group 0. A value
32556 * of 0 indicates no rate limit.
32558 * A queue group is a set of queues, one per traffic class. In
32559 * single-host mode, each panel port has its own queue group, and thus,
32560 * this rate limit shapes the traffic received on a port, in this case,
32561 * through port 0. In multi-root or multi-host mode, each PCIe endpoint
32562 * on the NIC has its own queue group. In these cases, the rate limit
32563 * shapes the traffic sent to the host through one of the PCIe
32564 * endpoints, in this case endpoint 0.
32568 * Specifies the maximum rate of the traffic through receive CoS queue
32569 * group 1 (for port 1 or PCIe endpoint 1). The rate is a percentage of
32570 * total link bandwidth (the sum of the bandwidths of all links). A
32571 * value of 0 indicates no rate limit.
32575 * Specifies the maximum rate of the traffic through receive CoS queue
32576 * group 2 (for port 2 or PCIe endpoint 2). The rate is a percentage of
32577 * total link bandwidth (the sum of the bandwidths of all links). A
32578 * value of 0 indicates no rate limit.
32582 * Specifies the maximum receive rate, in Mbps, of the receive traffic
32583 * through queue group 3 (for port 3 or PCIe endpoint 3). A value of 0
32584 * indicates no rate limit.
32589 /* hwrm_queue_global_cfg_output (size:128b/16B) */
32590 struct hwrm_queue_global_cfg_output {
32591 /* The specific error status for the command. */
32592 uint16_t error_code;
32593 /* The HWRM command request type. */
32595 /* The sequence ID from the original command. */
32597 /* The length of the response data in number of bytes. */
32599 uint8_t unused_0[7];
32601 * This field is used in Output records to indicate that the output
32602 * is completely written to RAM. This field should be read as '1'
32603 * to indicate that the output has been completely written.
32604 * When writing a command completion or response to an internal processor,
32605 * the order of writes has to be such that this field is written last.
32610 /**************************
32611 * hwrm_queue_global_qcfg *
32612 **************************/
32615 /* hwrm_queue_global_qcfg_input (size:128b/16B) */
32616 struct hwrm_queue_global_qcfg_input {
32617 /* The HWRM command request type. */
32620 * The completion ring to send the completion event on. This should
32621 * be the NQ ID returned from the `nq_alloc` HWRM command.
32623 uint16_t cmpl_ring;
32625 * The sequence ID is used by the driver for tracking multiple
32626 * commands. This ID is treated as opaque data by the firmware and
32627 * the value is returned in the `hwrm_resp_hdr` upon completion.
32631 * The target ID of the command:
32632 * * 0x0-0xFFF8 - The function ID
32633 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
32634 * * 0xFFFD - Reserved for user-space HWRM interface
32637 uint16_t target_id;
32639 * A physical address pointer pointing to a host buffer that the
32640 * command's response data will be written. This can be either a host
32641 * physical address (HPA) or a guest physical address (GPA) and must
32642 * point to a physically contiguous block of memory.
32644 uint64_t resp_addr;
32647 /* hwrm_queue_global_qcfg_output (size:320b/40B) */
32648 struct hwrm_queue_global_qcfg_output {
32649 /* The specific error status for the command. */
32650 uint16_t error_code;
32651 /* The HWRM command request type. */
32653 /* The sequence ID from the original command. */
32655 /* The length of the response data in number of bytes. */
32657 /* Port or PCIe endpoint id to be mapped for buffer pool 0. */
32658 uint8_t buffer_pool_id0_map;
32659 /* Port or PCIe endpoint id to be mapped for buffer pool 1. */
32660 uint8_t buffer_pool_id1_map;
32661 /* Port or PCIe endpoint id to be mapped for buffer pool 2. */
32662 uint8_t buffer_pool_id2_map;
32663 /* Port or PCIe endpoint id to be mapped for buffer pool 3. */
32664 uint8_t buffer_pool_id3_map;
32665 /* Size of buffer pool 0 (KBytes). */
32666 uint32_t buffer_pool_id0_size;
32667 /* Size of buffer pool 1 (KBytes). */
32668 uint32_t buffer_pool_id1_size;
32669 /* Size of buffer pool 2 (KBytes). */
32670 uint32_t buffer_pool_id2_size;
32671 /* Size of buffer pool 3 (KBytes). */
32672 uint32_t buffer_pool_id3_size;
32675 * Enumeration denoting whether the rx buffer pool mapping is
32676 * per port or per PCIe endpoint
32678 #define HWRM_QUEUE_GLOBAL_QCFG_OUTPUT_FLAGS_MAPPING \
32681 * The buffer_pool_id[0-3]_map field represents mapping of rx
32682 * buffer pools to a port.
32684 #define HWRM_QUEUE_GLOBAL_QCFG_OUTPUT_FLAGS_MAPPING_MAPPING_PER_PORT \
32687 * The buffer_pool_id[0-3]_map field represents mapping of rx
32688 * buffer pools to a PCIe endpoint.
32690 #define HWRM_QUEUE_GLOBAL_QCFG_OUTPUT_FLAGS_MAPPING_MAPPING_PER_ENDPOINT \
32692 #define HWRM_QUEUE_GLOBAL_QCFG_OUTPUT_FLAGS_MAPPING_LAST \
32693 HWRM_QUEUE_GLOBAL_QCFG_OUTPUT_FLAGS_MAPPING_MAPPING_PER_ENDPOINT
32695 * Configuration mode for rx cos queues, configuring whether they
32696 * use one shared buffer pool (across ports or PCIe endpoints) or
32697 * independent per port or per endpoint buffer pools.
32700 /* One shared buffer pool to be used by all RX CoS queues */
32701 #define HWRM_QUEUE_GLOBAL_QCFG_OUTPUT_MODE_SHARED UINT32_C(0x0)
32703 * Each port or PCIe endpoint to use an independent buffer pool
32704 * for its RX CoS queues
32706 #define HWRM_QUEUE_GLOBAL_QCFG_OUTPUT_MODE_INDEPENDENT UINT32_C(0x1)
32707 #define HWRM_QUEUE_GLOBAL_QCFG_OUTPUT_MODE_LAST \
32708 HWRM_QUEUE_GLOBAL_QCFG_OUTPUT_MODE_INDEPENDENT
32711 * Reports the rate limit applied to traffic through receive CoS queue
32712 * group 0. The rate limit is a percentage of total link bandwidth. A
32713 * value of 0 indicates no rate limit.
32715 * A queue group is a set of queues, one per traffic class. In
32716 * single-host mode, each panel port has its own queue group, and thus,
32717 * this rate limit shapes the traffic received on a port, in this case,
32718 * through port 0. In multi-root or multi-host mode, each PCIe endpoint
32719 * on the NIC has its own queue group. In these cases, the rate limit
32720 * shapes the traffic sent to the host through one of the PCIe
32721 * endpoints, in this case endpoint 0.
32725 * Reports the rate limit applied to traffic through receive CoS queue
32726 * group 1 (for port 1 or PCIe endpoint 1). The rate limit is a
32727 * percentage of total link bandwidth. A value of 0 indicates no rate
32732 * Reports the rate limit applied to traffic through receive CoS queue
32733 * group 2 (for port 2 or PCIe endpoint 2). The rate limit is a
32734 * percentage of total link bandwidth. A value of 0 indicates no rate
32739 * Reports the rate limit applied to traffic through receive CoS queue
32740 * group 3 (for port 3 or PCIe endpoint 3). The rate limit is a
32741 * percentage of total link bandwidth. A value of 0 indicates no rate
32745 uint8_t unused_1[3];
32747 * This field is used in Output records to indicate that the output
32748 * is completely written to RAM. This field should be read as '1'
32749 * to indicate that the output has been completely written.
32750 * When writing a command completion or response to an internal processor,
32751 * the order of writes has to be such that this field is written last.
32756 /*******************
32757 * hwrm_vnic_alloc *
32758 *******************/
32761 /* hwrm_vnic_alloc_input (size:192b/24B) */
32762 struct hwrm_vnic_alloc_input {
32763 /* The HWRM command request type. */
32766 * The completion ring to send the completion event on. This should
32767 * be the NQ ID returned from the `nq_alloc` HWRM command.
32769 uint16_t cmpl_ring;
32771 * The sequence ID is used by the driver for tracking multiple
32772 * commands. This ID is treated as opaque data by the firmware and
32773 * the value is returned in the `hwrm_resp_hdr` upon completion.
32777 * The target ID of the command:
32778 * * 0x0-0xFFF8 - The function ID
32779 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
32780 * * 0xFFFD - Reserved for user-space HWRM interface
32783 uint16_t target_id;
32785 * A physical address pointer pointing to a host buffer that the
32786 * command's response data will be written. This can be either a host
32787 * physical address (HPA) or a guest physical address (GPA) and must
32788 * point to a physically contiguous block of memory.
32790 uint64_t resp_addr;
32793 * When this bit is '1', this VNIC is requested to
32794 * be the default VNIC for this function.
32796 #define HWRM_VNIC_ALLOC_INPUT_FLAGS_DEFAULT \
32799 * When this bit is '1', proxy VEE PF is requesting
32800 * allocation of a default VNIC on behalf of virtio-net
32801 * function given in virtio_net_fid field.
32803 #define HWRM_VNIC_ALLOC_INPUT_FLAGS_VIRTIO_NET_FID_VALID \
32806 * Virtio-net function's FID.
32807 * This virtio-net function is requesting allocation of default
32808 * VNIC through proxy VEE PF.
32810 uint16_t virtio_net_fid;
32811 uint8_t unused_0[2];
32814 /* hwrm_vnic_alloc_output (size:128b/16B) */
32815 struct hwrm_vnic_alloc_output {
32816 /* The specific error status for the command. */
32817 uint16_t error_code;
32818 /* The HWRM command request type. */
32820 /* The sequence ID from the original command. */
32822 /* The length of the response data in number of bytes. */
32824 /* Logical vnic ID */
32826 uint8_t unused_0[3];
32828 * This field is used in Output records to indicate that the output
32829 * is completely written to RAM. This field should be read as '1'
32830 * to indicate that the output has been completely written.
32831 * When writing a command completion or response to an internal processor,
32832 * the order of writes has to be such that this field is written last.
32837 /********************
32838 * hwrm_vnic_update *
32839 ********************/
32842 /* hwrm_vnic_update_input (size:256b/32B) */
32843 struct hwrm_vnic_update_input {
32844 /* The HWRM command request type. */
32847 * The completion ring to send the completion event on. This should
32848 * be the NQ ID returned from the `nq_alloc` HWRM command.
32850 uint16_t cmpl_ring;
32852 * The sequence ID is used by the driver for tracking multiple
32853 * commands. This ID is treated as opaque data by the firmware and
32854 * the value is returned in the `hwrm_resp_hdr` upon completion.
32858 * The target ID of the command:
32859 * * 0x0-0xFFF8 - The function ID
32860 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
32861 * * 0xFFFD - Reserved for user-space HWRM interface
32864 uint16_t target_id;
32866 * A physical address pointer pointing to a host buffer that the
32867 * command's response data will be written. This can be either a host
32868 * physical address (HPA) or a guest physical address (GPA) and must
32869 * point to a physically contiguous block of memory.
32871 uint64_t resp_addr;
32872 /* Logical vnic ID */
32876 * This bit must be '1' for the vnic_state field to be
32879 #define HWRM_VNIC_UPDATE_INPUT_ENABLES_VNIC_STATE_VALID \
32882 * This bit must be '1' for the mru field to be
32885 #define HWRM_VNIC_UPDATE_INPUT_ENABLES_MRU_VALID \
32888 * This bit must be '1' for the metadata_format_type field to be
32891 #define HWRM_VNIC_UPDATE_INPUT_ENABLES_METADATA_FORMAT_TYPE_VALID \
32894 * This bit must be '1' for the rss_hash_function field to be
32897 #define HWRM_VNIC_UPDATE_INPUT_ENABLES_RSS_HASH_FUNCTION_VALID \
32900 * This will update the context variable with the same name if
32901 * the corresponding enable is set.
32903 uint8_t vnic_state;
32904 /* Normal operation state for the VNIC. */
32905 #define HWRM_VNIC_UPDATE_INPUT_VNIC_STATE_NORMAL UINT32_C(0x0)
32906 /* All packets are dropped in this state. */
32907 #define HWRM_VNIC_UPDATE_INPUT_VNIC_STATE_DROP UINT32_C(0x1)
32908 #define HWRM_VNIC_UPDATE_INPUT_VNIC_STATE_LAST \
32909 HWRM_VNIC_UPDATE_INPUT_VNIC_STATE_DROP
32911 * The metadata format type used in all the RX packet completions
32912 * going through this VNIC.
32914 uint8_t metadata_format_type;
32915 /* No metadata information. */
32916 #define HWRM_VNIC_UPDATE_INPUT_METADATA_FORMAT_TYPE_NONE \
32919 * Action record pointer (table_scope[4:0], act_rec_ptr[25:0],
32922 #define HWRM_VNIC_UPDATE_INPUT_METADATA_FORMAT_TYPE_ACT_RECORD_PTR \
32924 /* Tunnel ID (tunnel_id[31:0], vtag[19:0]) */
32925 #define HWRM_VNIC_UPDATE_INPUT_METADATA_FORMAT_TYPE_TUNNEL_ID \
32927 /* Custom header data (updated_chdr_data[31:0], vtag[19:0]) */
32928 #define HWRM_VNIC_UPDATE_INPUT_METADATA_FORMAT_TYPE_CUSTOM_HDR_DATA \
32930 /* Header offsets (hdr_offsets[31:0], vtag[19:0]) */
32931 #define HWRM_VNIC_UPDATE_INPUT_METADATA_FORMAT_TYPE_HDR_OFFSETS \
32933 #define HWRM_VNIC_UPDATE_INPUT_METADATA_FORMAT_TYPE_LAST \
32934 HWRM_VNIC_UPDATE_INPUT_METADATA_FORMAT_TYPE_HDR_OFFSETS
32936 * The maximum receive unit of the vnic.
32937 * Each vnic is associated with a function.
32938 * The vnic mru value overwrites the mru setting of the
32939 * associated function.
32940 * The HWRM shall make sure that vnic mru does not exceed
32941 * the mru of the port the function is associated with.
32945 * Used to choose the RSS hash algorithm based on which HW
32946 * can select the destination ring
32948 uint8_t rss_hash_function;
32950 * NIC calculates the RSS hash using the Toeplitz algorithm on L3/L4
32951 * headers and uses the hash to select the ring.
32953 #define HWRM_VNIC_UPDATE_INPUT_RSS_HASH_FUNCTION_TOEPLITZ UINT32_C(0x0)
32955 * NIC calculates the RSS hash using the XOR algorithm on L3/L4
32956 * headers and uses the hash to select the ring.
32958 #define HWRM_VNIC_UPDATE_INPUT_RSS_HASH_FUNCTION_XOR UINT32_C(0x1)
32960 * In this mode, RSS hash is calculated with Toeplitz and reported
32961 * in the RX completion. However, the ring selection algorithm is
32962 * based on the checksum. In this mode, only the innermost L3/L4
32963 * packet checksums are used. So this hash function mode will not
32964 * be exposed/valid when the outer RSS mode is enabled.
32966 #define HWRM_VNIC_UPDATE_INPUT_RSS_HASH_FUNCTION_CHECKSUM UINT32_C(0x2)
32967 #define HWRM_VNIC_UPDATE_INPUT_RSS_HASH_FUNCTION_LAST \
32968 HWRM_VNIC_UPDATE_INPUT_RSS_HASH_FUNCTION_CHECKSUM
32969 uint8_t unused_1[3];
32972 /* hwrm_vnic_update_output (size:128b/16B) */
32973 struct hwrm_vnic_update_output {
32974 /* The specific error status for the command. */
32975 uint16_t error_code;
32976 /* The HWRM command request type. */
32978 /* The sequence ID from the original command. */
32980 /* The length of the response data in number of bytes. */
32982 uint8_t unused_0[7];
32984 * This field is used in Output records to indicate that the output
32985 * is completely written to RAM. This field should be read as '1'
32986 * to indicate that the output has been completely written.
32987 * When writing a command completion or response to an internal
32988 * processor, the order of writes has to be such that this field is
32994 /******************
32996 ******************/
32999 /* hwrm_vnic_free_input (size:192b/24B) */
33000 struct hwrm_vnic_free_input {
33001 /* The HWRM command request type. */
33004 * The completion ring to send the completion event on. This should
33005 * be the NQ ID returned from the `nq_alloc` HWRM command.
33007 uint16_t cmpl_ring;
33009 * The sequence ID is used by the driver for tracking multiple
33010 * commands. This ID is treated as opaque data by the firmware and
33011 * the value is returned in the `hwrm_resp_hdr` upon completion.
33015 * The target ID of the command:
33016 * * 0x0-0xFFF8 - The function ID
33017 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
33018 * * 0xFFFD - Reserved for user-space HWRM interface
33021 uint16_t target_id;
33023 * A physical address pointer pointing to a host buffer that the
33024 * command's response data will be written. This can be either a host
33025 * physical address (HPA) or a guest physical address (GPA) and must
33026 * point to a physically contiguous block of memory.
33028 uint64_t resp_addr;
33029 /* Logical vnic ID */
33031 uint8_t unused_0[4];
33034 /* hwrm_vnic_free_output (size:128b/16B) */
33035 struct hwrm_vnic_free_output {
33036 /* The specific error status for the command. */
33037 uint16_t error_code;
33038 /* The HWRM command request type. */
33040 /* The sequence ID from the original command. */
33042 /* The length of the response data in number of bytes. */
33044 uint8_t unused_0[7];
33046 * This field is used in Output records to indicate that the output
33047 * is completely written to RAM. This field should be read as '1'
33048 * to indicate that the output has been completely written.
33049 * When writing a command completion or response to an internal processor,
33050 * the order of writes has to be such that this field is written last.
33060 /* hwrm_vnic_cfg_input (size:384b/48B) */
33061 struct hwrm_vnic_cfg_input {
33062 /* The HWRM command request type. */
33065 * The completion ring to send the completion event on. This should
33066 * be the NQ ID returned from the `nq_alloc` HWRM command.
33068 uint16_t cmpl_ring;
33070 * The sequence ID is used by the driver for tracking multiple
33071 * commands. This ID is treated as opaque data by the firmware and
33072 * the value is returned in the `hwrm_resp_hdr` upon completion.
33076 * The target ID of the command:
33077 * * 0x0-0xFFF8 - The function ID
33078 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
33079 * * 0xFFFD - Reserved for user-space HWRM interface
33082 uint16_t target_id;
33084 * A physical address pointer pointing to a host buffer that the
33085 * command's response data will be written. This can be either a host
33086 * physical address (HPA) or a guest physical address (GPA) and must
33087 * point to a physically contiguous block of memory.
33089 uint64_t resp_addr;
33092 * When this bit is '1', the VNIC is requested to
33093 * be the default VNIC for the function.
33095 #define HWRM_VNIC_CFG_INPUT_FLAGS_DEFAULT \
33098 * When this bit is '1', the VNIC is being configured to
33099 * strip VLAN in the RX path.
33100 * If set to '0', then VLAN stripping is disabled on
33103 #define HWRM_VNIC_CFG_INPUT_FLAGS_VLAN_STRIP_MODE \
33106 * When this bit is '1', the VNIC is being configured to
33107 * buffer receive packets in the hardware until the host
33108 * posts new receive buffers.
33109 * If set to '0', then bd_stall is being configured to be
33110 * disabled on this VNIC.
33112 #define HWRM_VNIC_CFG_INPUT_FLAGS_BD_STALL_MODE \
33115 * When this bit is '1', the VNIC is being configured to
33116 * receive both RoCE and non-RoCE traffic.
33117 * If set to '0', then this VNIC is not configured to be
33118 * operating in dual VNIC mode.
33120 #define HWRM_VNIC_CFG_INPUT_FLAGS_ROCE_DUAL_VNIC_MODE \
33123 * When this flag is set to '1', the VNIC is requested to
33124 * be configured to receive only RoCE traffic.
33125 * If this flag is set to '0', then this flag shall be
33126 * ignored by the HWRM.
33127 * If roce_dual_vnic_mode flag is set to '1'
33128 * or roce_mirroring_capable_vnic_mode flag to 1,
33129 * then the HWRM client shall not set this flag to '1'.
33131 #define HWRM_VNIC_CFG_INPUT_FLAGS_ROCE_ONLY_VNIC_MODE \
33134 * When a VNIC uses one destination ring group for certain
33135 * application (e.g. Receive Flow Steering) where
33136 * exact match is used to direct packets to a VNIC with one
33137 * destination ring group only, there is no need to configure
33138 * RSS indirection table for that VNIC as only one destination
33139 * ring group is used.
33141 * This flag is used to enable a mode where
33142 * RSS is enabled in the VNIC using a RSS context
33143 * for computing RSS hash but the RSS indirection table is
33144 * not configured using hwrm_vnic_rss_cfg.
33146 * If this mode is enabled, then the driver should not program
33147 * RSS indirection table for the RSS context that is used for
33148 * computing RSS hash only.
33150 #define HWRM_VNIC_CFG_INPUT_FLAGS_RSS_DFLT_CR_MODE \
33153 * When this bit is '1', the VNIC is being configured to
33154 * receive both RoCE and non-RoCE traffic, but forward only the
33155 * RoCE traffic further. Also, RoCE traffic can be mirrored to
33158 #define HWRM_VNIC_CFG_INPUT_FLAGS_ROCE_MIRRORING_CAPABLE_VNIC_MODE \
33162 * This bit must be '1' for the dflt_ring_grp field to be
33165 #define HWRM_VNIC_CFG_INPUT_ENABLES_DFLT_RING_GRP \
33168 * This bit must be '1' for the rss_rule field to be
33171 #define HWRM_VNIC_CFG_INPUT_ENABLES_RSS_RULE \
33174 * This bit must be '1' for the cos_rule field to be
33177 #define HWRM_VNIC_CFG_INPUT_ENABLES_COS_RULE \
33180 * This bit must be '1' for the lb_rule field to be
33183 #define HWRM_VNIC_CFG_INPUT_ENABLES_LB_RULE \
33186 * This bit must be '1' for the mru field to be
33189 #define HWRM_VNIC_CFG_INPUT_ENABLES_MRU \
33192 * This bit must be '1' for the default_rx_ring_id field to be
33195 #define HWRM_VNIC_CFG_INPUT_ENABLES_DEFAULT_RX_RING_ID \
33198 * This bit must be '1' for the default_cmpl_ring_id field to be
33201 #define HWRM_VNIC_CFG_INPUT_ENABLES_DEFAULT_CMPL_RING_ID \
33203 /* This bit must be '1' for the queue_id field to be configured. */
33204 #define HWRM_VNIC_CFG_INPUT_ENABLES_QUEUE_ID \
33206 /* This bit must be '1' for the rx_csum_v2_mode field to be configured. */
33207 #define HWRM_VNIC_CFG_INPUT_ENABLES_RX_CSUM_V2_MODE \
33209 /* Logical vnic ID */
33212 * Default Completion ring for the VNIC. This ring will
33213 * be chosen if packet does not match any RSS rules and if
33214 * there is no COS rule.
33216 uint16_t dflt_ring_grp;
33218 * RSS ID for RSS rule/table structure. 0xFF... (All Fs) if
33219 * there is no RSS rule.
33223 * RSS ID for COS rule/table structure. 0xFF... (All Fs) if
33224 * there is no COS rule.
33228 * RSS ID for load balancing rule/table structure.
33229 * 0xFF... (All Fs) if there is no LB rule.
33233 * The maximum receive unit of the vnic.
33234 * Each vnic is associated with a function.
33235 * The vnic mru value overwrites the mru setting of the
33236 * associated function.
33237 * The HWRM shall make sure that vnic mru does not exceed
33238 * the mru of the port the function is associated with.
33242 * Default Rx ring for the VNIC. This ring will
33243 * be chosen if packet does not match any RSS rules.
33244 * The aggregation ring associated with the Rx ring is
33245 * implied based on the Rx ring specified when the
33246 * aggregation ring was allocated.
33248 uint16_t default_rx_ring_id;
33250 * Default completion ring for the VNIC. This ring will
33251 * be chosen if packet does not match any RSS rules.
33253 uint16_t default_cmpl_ring_id;
33255 * When specified, only incoming packets classified to the specified CoS
33256 * queue ID will be arriving on this VNIC. Packet priority to CoS mapping
33257 * rules can be specified using HWRM_QUEUE_PRI2COS_CFG. In this mode,
33258 * ntuple filters with VNIC destination specified are invalid since they
33259 * conflict with the CoS to VNIC steering rules in this mode.
33261 * If this field is not specified, packet to VNIC steering will be
33262 * subject to the standard L2 filter rules and any additional ntuple
33263 * filter rules with destination VNIC specified.
33267 * If the device supports the RX V2 and RX TPA start V2 completion
33268 * records as indicated by the HWRM_VNIC_QCAPS command, this field is
33269 * used to specify the two RX checksum modes supported by these
33270 * completion records.
33272 uint8_t rx_csum_v2_mode;
33274 * When configured with this checksum mode, the number of header
33275 * groups in the delivered packet with a valid IP checksum and
33276 * the number of header groups in the delivered packet with a valid
33277 * L4 checksum are reported. Valid checksums are counted from the
33278 * outermost header group to the innermost header group, stopping at
33279 * the first error. This is the default checksum mode supported if
33280 * the driver doesn't explicitly configure the RX checksum mode.
33282 #define HWRM_VNIC_CFG_INPUT_RX_CSUM_V2_MODE_DEFAULT UINT32_C(0x0)
33284 * When configured with this checksum mode, the checksum status is
33285 * reported using 'all ok' mode. In the RX completion record, one
33286 * bit indicates if the IP checksum is valid for all the parsed
33287 * header groups with an IP checksum. Another bit indicates if the
33288 * L4 checksum is valid for all the parsed header groups with an L4
33289 * checksum. The number of header groups that were parsed by the
33290 * chip and passed in the delivered packet is also reported.
33292 #define HWRM_VNIC_CFG_INPUT_RX_CSUM_V2_MODE_ALL_OK UINT32_C(0x1)
33294 * Any rx_csum_v2_mode value larger than or equal to this is not
33297 #define HWRM_VNIC_CFG_INPUT_RX_CSUM_V2_MODE_MAX UINT32_C(0x2)
33298 #define HWRM_VNIC_CFG_INPUT_RX_CSUM_V2_MODE_LAST \
33299 HWRM_VNIC_CFG_INPUT_RX_CSUM_V2_MODE_MAX
33300 uint8_t unused0[5];
33303 /* hwrm_vnic_cfg_output (size:128b/16B) */
33304 struct hwrm_vnic_cfg_output {
33305 /* The specific error status for the command. */
33306 uint16_t error_code;
33307 /* The HWRM command request type. */
33309 /* The sequence ID from the original command. */
33311 /* The length of the response data in number of bytes. */
33313 uint8_t unused_0[7];
33315 * This field is used in Output records to indicate that the output
33316 * is completely written to RAM. This field should be read as '1'
33317 * to indicate that the output has been completely written.
33318 * When writing a command completion or response to an internal processor,
33319 * the order of writes has to be such that this field is written last.
33324 /******************
33326 ******************/
33329 /* hwrm_vnic_qcfg_input (size:256b/32B) */
33330 struct hwrm_vnic_qcfg_input {
33331 /* The HWRM command request type. */
33334 * The completion ring to send the completion event on. This should
33335 * be the NQ ID returned from the `nq_alloc` HWRM command.
33337 uint16_t cmpl_ring;
33339 * The sequence ID is used by the driver for tracking multiple
33340 * commands. This ID is treated as opaque data by the firmware and
33341 * the value is returned in the `hwrm_resp_hdr` upon completion.
33345 * The target ID of the command:
33346 * * 0x0-0xFFF8 - The function ID
33347 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
33348 * * 0xFFFD - Reserved for user-space HWRM interface
33351 uint16_t target_id;
33353 * A physical address pointer pointing to a host buffer that the
33354 * command's response data will be written. This can be either a host
33355 * physical address (HPA) or a guest physical address (GPA) and must
33356 * point to a physically contiguous block of memory.
33358 uint64_t resp_addr;
33361 * This bit must be '1' for the vf_id_valid field to be
33364 #define HWRM_VNIC_QCFG_INPUT_ENABLES_VF_ID_VALID UINT32_C(0x1)
33365 /* Logical vnic ID */
33367 /* ID of Virtual Function whose VNIC resource is being queried. */
33369 uint8_t unused_0[6];
33372 /* hwrm_vnic_qcfg_output (size:256b/32B) */
33373 struct hwrm_vnic_qcfg_output {
33374 /* The specific error status for the command. */
33375 uint16_t error_code;
33376 /* The HWRM command request type. */
33378 /* The sequence ID from the original command. */
33380 /* The length of the response data in number of bytes. */
33382 /* Default Completion ring for the VNIC. */
33383 uint16_t dflt_ring_grp;
33385 * RSS ID for RSS rule/table structure. 0xFF... (All Fs) if
33386 * there is no RSS rule.
33390 * RSS ID for COS rule/table structure. 0xFF... (All Fs) if
33391 * there is no COS rule.
33395 * RSS ID for load balancing rule/table structure.
33396 * 0xFF... (All Fs) if there is no LB rule.
33399 /* The maximum receive unit of the vnic. */
33401 uint8_t unused_0[2];
33404 * When this bit is '1', the VNIC is the default VNIC for
33407 #define HWRM_VNIC_QCFG_OUTPUT_FLAGS_DEFAULT \
33410 * When this bit is '1', the VNIC is configured to
33411 * strip VLAN in the RX path.
33412 * If set to '0', then VLAN stripping is disabled on
33415 #define HWRM_VNIC_QCFG_OUTPUT_FLAGS_VLAN_STRIP_MODE \
33418 * When this bit is '1', the VNIC is configured to
33419 * buffer receive packets in the hardware until the host
33420 * posts new receive buffers.
33421 * If set to '0', then bd_stall is disabled on
33424 #define HWRM_VNIC_QCFG_OUTPUT_FLAGS_BD_STALL_MODE \
33427 * When this bit is '1', the VNIC is configured to
33428 * receive both RoCE and non-RoCE traffic.
33429 * If set to '0', then this VNIC is not configured to
33430 * operate in dual VNIC mode.
33432 #define HWRM_VNIC_QCFG_OUTPUT_FLAGS_ROCE_DUAL_VNIC_MODE \
33435 * When this flag is set to '1', the VNIC is configured to
33436 * receive only RoCE traffic.
33437 * When this flag is set to '0', the VNIC is not configured
33438 * to receive only RoCE traffic.
33439 * If roce_dual_vnic_mode flag and this flag both are set
33440 * to '1', then it is an invalid configuration of the
33441 * VNIC. The HWRM should not allow that type of
33442 * mis-configuration by HWRM clients.
33444 #define HWRM_VNIC_QCFG_OUTPUT_FLAGS_ROCE_ONLY_VNIC_MODE \
33447 * When a VNIC uses one destination ring group for certain
33448 * application (e.g. Receive Flow Steering) where
33449 * exact match is used to direct packets to a VNIC with one
33450 * destination ring group only, there is no need to configure
33451 * RSS indirection table for that VNIC as only one destination
33452 * ring group is used.
33454 * When this bit is set to '1', then the VNIC is enabled in a
33455 * mode where RSS is enabled in the VNIC using a RSS context
33456 * for computing RSS hash but the RSS indirection table is
33459 #define HWRM_VNIC_QCFG_OUTPUT_FLAGS_RSS_DFLT_CR_MODE \
33462 * When this bit is '1', the VNIC is configured to
33463 * receive both RoCE and non-RoCE traffic, but forward only
33464 * RoCE traffic further. Also RoCE traffic can be mirrored to
33467 #define HWRM_VNIC_QCFG_OUTPUT_FLAGS_ROCE_MIRRORING_CAPABLE_VNIC_MODE \
33470 * When this bit is '0', VNIC is in normal operation state.
33471 * When this bit is '1', VNIC drops all the received packets.
33473 #define HWRM_VNIC_QCFG_OUTPUT_FLAGS_OPERATION_STATE \
33476 * When returned with a valid CoS Queue id, the CoS Queue/VNIC association
33477 * is valid. Otherwise it will return 0xFFFF to indicate no VNIC/CoS
33478 * queue association.
33482 * If the device supports the RX V2 and RX TPA start V2 completion
33483 * records as indicated by the HWRM_VNIC_QCAPS command, this field is
33484 * used to specify the current RX checksum mode configured for all the
33485 * RX rings of a VNIC.
33487 uint8_t rx_csum_v2_mode;
33489 * This value indicates that the VNIC is configured to use the
33490 * default RX checksum mode for all the rings associated with this
33493 #define HWRM_VNIC_QCFG_OUTPUT_RX_CSUM_V2_MODE_DEFAULT UINT32_C(0x0)
33495 * This value indicates that the VNIC is configured to use the RX
33496 * checksum ‘all_ok’ mode for all the rings associated with this
33499 #define HWRM_VNIC_QCFG_OUTPUT_RX_CSUM_V2_MODE_ALL_OK UINT32_C(0x1)
33501 * Any rx_csum_v2_mode value larger than or equal to this is not
33504 #define HWRM_VNIC_QCFG_OUTPUT_RX_CSUM_V2_MODE_MAX UINT32_C(0x2)
33505 #define HWRM_VNIC_QCFG_OUTPUT_RX_CSUM_V2_MODE_LAST \
33506 HWRM_VNIC_QCFG_OUTPUT_RX_CSUM_V2_MODE_MAX
33507 uint8_t unused_1[4];
33509 * This field is used in Output records to indicate that the output
33510 * is completely written to RAM. This field should be read as '1'
33511 * to indicate that the output has been completely written.
33512 * When writing a command completion or response to an internal processor,
33513 * the order of writes has to be such that this field is written last.
33518 /*******************
33519 * hwrm_vnic_qcaps *
33520 *******************/
33523 /* hwrm_vnic_qcaps_input (size:192b/24B) */
33524 struct hwrm_vnic_qcaps_input {
33525 /* The HWRM command request type. */
33528 * The completion ring to send the completion event on. This should
33529 * be the NQ ID returned from the `nq_alloc` HWRM command.
33531 uint16_t cmpl_ring;
33533 * The sequence ID is used by the driver for tracking multiple
33534 * commands. This ID is treated as opaque data by the firmware and
33535 * the value is returned in the `hwrm_resp_hdr` upon completion.
33539 * The target ID of the command:
33540 * * 0x0-0xFFF8 - The function ID
33541 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
33542 * * 0xFFFD - Reserved for user-space HWRM interface
33545 uint16_t target_id;
33547 * A physical address pointer pointing to a host buffer that the
33548 * command's response data will be written. This can be either a host
33549 * physical address (HPA) or a guest physical address (GPA) and must
33550 * point to a physically contiguous block of memory.
33552 uint64_t resp_addr;
33554 uint8_t unused_0[4];
33557 /* hwrm_vnic_qcaps_output (size:192b/24B) */
33558 struct hwrm_vnic_qcaps_output {
33559 /* The specific error status for the command. */
33560 uint16_t error_code;
33561 /* The HWRM command request type. */
33563 /* The sequence ID from the original command. */
33565 /* The length of the response data in number of bytes. */
33567 /* The maximum receive unit that is settable on a vnic. */
33569 uint8_t unused_0[2];
33572 #define HWRM_VNIC_QCAPS_OUTPUT_FLAGS_UNUSED \
33575 * When this bit is '1', the capability of stripping VLAN in
33576 * the RX path is supported on VNIC(s).
33577 * If set to '0', then VLAN stripping capability is
33578 * not supported on VNIC(s).
33580 #define HWRM_VNIC_QCAPS_OUTPUT_FLAGS_VLAN_STRIP_CAP \
33583 * When this bit is '1', the capability to buffer receive
33584 * packets in the hardware until the host posts new receive buffers
33585 * is supported on VNIC(s).
33586 * If set to '0', then bd_stall capability is not supported
33589 #define HWRM_VNIC_QCAPS_OUTPUT_FLAGS_BD_STALL_CAP \
33592 * When this bit is '1', the capability to
33593 * receive both RoCE and non-RoCE traffic on VNIC(s) is
33595 * If set to '0', then the capability to receive
33596 * both RoCE and non-RoCE traffic on VNIC(s) is
33599 #define HWRM_VNIC_QCAPS_OUTPUT_FLAGS_ROCE_DUAL_VNIC_CAP \
33602 * When this bit is set to '1', the capability to configure
33603 * a VNIC to receive only RoCE traffic is supported.
33604 * When this flag is set to '0', the VNIC capability to
33605 * configure to receive only RoCE traffic is not supported.
33607 #define HWRM_VNIC_QCAPS_OUTPUT_FLAGS_ROCE_ONLY_VNIC_CAP \
33610 * When this bit is set to '1', then the capability to enable
33611 * a VNIC in a mode where RSS context without configuring
33612 * RSS indirection table is supported (for RSS hash computation).
33613 * When this bit is set to '0', then a VNIC can not be configured
33614 * with a mode to enable RSS context without configuring RSS
33615 * indirection table.
33617 #define HWRM_VNIC_QCAPS_OUTPUT_FLAGS_RSS_DFLT_CR_CAP \
33620 * When this bit is '1', the capability to
33621 * mirror the RoCE traffic is supported.
33622 * If set to '0', then the capability to mirror the
33623 * RoCE traffic is not supported.
33625 #define HWRM_VNIC_QCAPS_OUTPUT_FLAGS_ROCE_MIRRORING_CAPABLE_VNIC_CAP \
33628 * When this bit is '1', the outermost RSS hashing capability
33629 * is supported. If set to '0', then the outermost RSS hashing
33630 * capability is not supported.
33632 #define HWRM_VNIC_QCAPS_OUTPUT_FLAGS_OUTERMOST_RSS_CAP \
33635 * When this bit is '1', it indicates that firmware supports the
33636 * ability to steer incoming packets from one CoS queue to one
33637 * VNIC. This optional feature can then be enabled
33638 * using HWRM_VNIC_CFG on any VNIC. This feature is only
33639 * available when NVM option “enable_cos_classification” is set
33640 * to 1. If set to '0', firmware does not support this feature.
33642 #define HWRM_VNIC_QCAPS_OUTPUT_FLAGS_COS_ASSIGNMENT_CAP \
33645 * When this bit is '1', it indicates that HW and firmware supports
33646 * the use of RX V2 and RX TPA start V2 completion records for all
33647 * the RX rings of a VNIC. Once set, this feature is mandatory to
33648 * be used for the RX rings of the VNIC. Additionally, two new RX
33649 * checksum features supported by these completion records can be
33650 * configured using the HWRM_VNIC_CFG on a VNIC. If set to '0', the
33651 * HW and the firmware does not support this feature.
33653 #define HWRM_VNIC_QCAPS_OUTPUT_FLAGS_RX_CMPL_V2_CAP \
33656 * When this bit is '1', it indicates that HW and firmware support
33657 * vnic state change. Host drivers can change the vnic state using
33658 * HWRM_VNIC_UPDATE. If set to '0', the HW and firmware do not
33659 * support this feature.
33661 #define HWRM_VNIC_QCAPS_OUTPUT_FLAGS_VNIC_STATE_CAP \
33664 * When this bit is '1', it indicates that firmware supports
33665 * virtio-net functions default VNIC allocation using
33667 * This capability is available only on Proxy VEE PF. If set to '0',
33668 * firmware does not support this feature.
33670 #define HWRM_VNIC_QCAPS_OUTPUT_FLAGS_VIRTIO_NET_VNIC_ALLOC_CAP \
33673 * When this bit is set '1', then the capability to configure the
33674 * metadata format in the RX completion is supported for the VNIC.
33675 * When this bit is set to '0', then the capability to configure
33676 * the metadata format in the RX completion is not supported for
33679 #define HWRM_VNIC_QCAPS_OUTPUT_FLAGS_METADATA_FORMAT_CAP \
33682 * When this bit is set '1', it indicates that firmware returns
33683 * INVALID_PARAM error, if host drivers choose invalid hash type
33684 * bit combinations in vnic_rss_cfg.
33686 #define HWRM_VNIC_QCAPS_OUTPUT_FLAGS_RSS_STRICT_HASH_TYPE_CAP \
33689 * When this bit is set '1', it indicates that firmware supports
33690 * the hash_type include and exclude flags in hwrm_vnic_rss_cfg.
33692 #define HWRM_VNIC_QCAPS_OUTPUT_FLAGS_RSS_HASH_TYPE_DELTA_CAP \
33695 * When this bit is '1', it indicates that HW is capable
33696 * of calculating the RSS hash using Toeplitz algorithm.
33698 #define HWRM_VNIC_QCAPS_OUTPUT_FLAGS_RSS_HASH_FUNCTION_TOEPLITZ_CAP \
33701 * When this bit is '1', it indicates that HW is capable
33702 * of calculating the RSS hash using XOR algorithm.
33704 #define HWRM_VNIC_QCAPS_OUTPUT_FLAGS_RSS_HASH_FUNCTION_XOR_CAP \
33707 * When this bit is '1', it indicates that HW is capable
33708 * of using checksum algorithm.
33709 * In this mode, RSS hash is calculated with Toeplitz and reported
33710 * in the RX completion. However, the ring selection algorithm is
33711 * based on the checksum. In this mode, only the innermost L3/L4
33712 * packet checksums are used. So this hash function mode will not
33713 * be exposed/valid when the outer RSS mode is enabled.
33715 #define HWRM_VNIC_QCAPS_OUTPUT_FLAGS_RSS_HASH_FUNCTION_CHKSM_CAP \
33718 * When this bit is '1' HW supports hash calculation
33719 * based on IPV6 flow labels.
33721 #define HWRM_VNIC_QCAPS_OUTPUT_FLAGS_RSS_IPV6_FLOW_LABEL_CAP \
33724 * This field advertises the maximum concurrent TPA aggregations
33725 * supported by the VNIC on new devices that support TPA v2.
33726 * '0' means that TPA v2 is not supported.
33728 uint16_t max_aggs_supported;
33729 uint8_t unused_1[5];
33731 * This field is used in Output records to indicate that the output
33732 * is completely written to RAM. This field should be read as '1'
33733 * to indicate that the output has been completely written.
33734 * When writing a command completion or response to an internal processor,
33735 * the order of writes has to be such that this field is written last.
33740 /*********************
33741 * hwrm_vnic_tpa_cfg *
33742 *********************/
33745 /* hwrm_vnic_tpa_cfg_input (size:320b/40B) */
33746 struct hwrm_vnic_tpa_cfg_input {
33747 /* The HWRM command request type. */
33750 * The completion ring to send the completion event on. This should
33751 * be the NQ ID returned from the `nq_alloc` HWRM command.
33753 uint16_t cmpl_ring;
33755 * The sequence ID is used by the driver for tracking multiple
33756 * commands. This ID is treated as opaque data by the firmware and
33757 * the value is returned in the `hwrm_resp_hdr` upon completion.
33761 * The target ID of the command:
33762 * * 0x0-0xFFF8 - The function ID
33763 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
33764 * * 0xFFFD - Reserved for user-space HWRM interface
33767 uint16_t target_id;
33769 * A physical address pointer pointing to a host buffer that the
33770 * command's response data will be written. This can be either a host
33771 * physical address (HPA) or a guest physical address (GPA) and must
33772 * point to a physically contiguous block of memory.
33774 uint64_t resp_addr;
33777 * When this bit is '1', the VNIC shall be configured to
33778 * perform transparent packet aggregation (TPA) of
33779 * non-tunneled TCP packets.
33781 #define HWRM_VNIC_TPA_CFG_INPUT_FLAGS_TPA \
33784 * When this bit is '1', the VNIC shall be configured to
33785 * perform transparent packet aggregation (TPA) of
33786 * tunneled TCP packets.
33788 #define HWRM_VNIC_TPA_CFG_INPUT_FLAGS_ENCAP_TPA \
33791 * When this bit is '1', the VNIC shall be configured to
33792 * perform transparent packet aggregation (TPA) according
33793 * to Windows Receive Segment Coalescing (RSC) rules.
33795 #define HWRM_VNIC_TPA_CFG_INPUT_FLAGS_RSC_WND_UPDATE \
33798 * When this bit is '1', the VNIC shall be configured to
33799 * perform transparent packet aggregation (TPA) according
33800 * to Linux Generic Receive Offload (GRO) rules.
33802 #define HWRM_VNIC_TPA_CFG_INPUT_FLAGS_GRO \
33805 * When this bit is '1', the VNIC shall be configured to
33806 * perform transparent packet aggregation (TPA) for TCP
33807 * packets with IP ECN set to non-zero.
33809 #define HWRM_VNIC_TPA_CFG_INPUT_FLAGS_AGG_WITH_ECN \
33812 * When this bit is '1', the VNIC shall be configured to
33813 * perform transparent packet aggregation (TPA) for
33814 * GRE tunneled TCP packets only if all packets have the
33815 * same GRE sequence.
33817 #define HWRM_VNIC_TPA_CFG_INPUT_FLAGS_AGG_WITH_SAME_GRE_SEQ \
33820 * When this bit is '1' and the GRO mode is enabled,
33821 * the VNIC shall be configured to
33822 * perform transparent packet aggregation (TPA) for
33823 * TCP/IPv4 packets with consecutively increasing IPIDs.
33824 * In other words, the last packet that is being
33825 * aggregated to an already existing aggregation context
33826 * shall have IPID 1 more than the IPID of the last packet
33827 * that was aggregated in that aggregation context.
33829 #define HWRM_VNIC_TPA_CFG_INPUT_FLAGS_GRO_IPID_CHECK \
33832 * When this bit is '1' and the GRO mode is enabled,
33833 * the VNIC shall be configured to
33834 * perform transparent packet aggregation (TPA) for
33835 * TCP packets with the same TTL (IPv4) or Hop limit (IPv6)
33838 #define HWRM_VNIC_TPA_CFG_INPUT_FLAGS_GRO_TTL_CHECK \
33841 * When this bit is '1' and the GRO mode is enabled,
33842 * the VNIC shall DMA payload data using GRO rules.
33843 * When this bit is '0', the VNIC shall DMA payload data
33844 * using the more efficient LRO rules of filling all
33845 * aggregation buffers.
33847 #define HWRM_VNIC_TPA_CFG_INPUT_FLAGS_AGG_PACK_AS_GRO \
33851 * This bit must be '1' for the max_agg_segs field to be
33854 #define HWRM_VNIC_TPA_CFG_INPUT_ENABLES_MAX_AGG_SEGS UINT32_C(0x1)
33856 * This bit must be '1' for the max_aggs field to be
33859 #define HWRM_VNIC_TPA_CFG_INPUT_ENABLES_MAX_AGGS UINT32_C(0x2)
33861 * This bit must be '1' for the max_agg_timer field to be
33864 #define HWRM_VNIC_TPA_CFG_INPUT_ENABLES_MAX_AGG_TIMER UINT32_C(0x4)
33865 /* deprecated bit. Do not use!!! */
33866 #define HWRM_VNIC_TPA_CFG_INPUT_ENABLES_MIN_AGG_LEN UINT32_C(0x8)
33867 /* Logical vnic ID */
33870 * This is the maximum number of TCP segments that can
33871 * be aggregated (unit is Log2). Max value is 31. On new
33872 * devices supporting TPA v2, the unit is multiples of 4 and
33873 * valid values are > 0 and <= 63.
33875 uint16_t max_agg_segs;
33877 #define HWRM_VNIC_TPA_CFG_INPUT_MAX_AGG_SEGS_1 UINT32_C(0x0)
33879 #define HWRM_VNIC_TPA_CFG_INPUT_MAX_AGG_SEGS_2 UINT32_C(0x1)
33881 #define HWRM_VNIC_TPA_CFG_INPUT_MAX_AGG_SEGS_4 UINT32_C(0x2)
33883 #define HWRM_VNIC_TPA_CFG_INPUT_MAX_AGG_SEGS_8 UINT32_C(0x3)
33884 /* Any segment size larger than this is not valid */
33885 #define HWRM_VNIC_TPA_CFG_INPUT_MAX_AGG_SEGS_MAX UINT32_C(0x1f)
33886 #define HWRM_VNIC_TPA_CFG_INPUT_MAX_AGG_SEGS_LAST \
33887 HWRM_VNIC_TPA_CFG_INPUT_MAX_AGG_SEGS_MAX
33889 * This is the maximum number of aggregations this VNIC is
33890 * allowed (unit is Log2). Max value is 7. On new devices
33891 * supporting TPA v2, this is in unit of 1 and must be > 0
33892 * and <= max_aggs_supported in the hwrm_vnic_qcaps response
33893 * to enable TPA v2.
33896 /* 1 aggregation */
33897 #define HWRM_VNIC_TPA_CFG_INPUT_MAX_AGGS_1 UINT32_C(0x0)
33898 /* 2 aggregations */
33899 #define HWRM_VNIC_TPA_CFG_INPUT_MAX_AGGS_2 UINT32_C(0x1)
33900 /* 4 aggregations */
33901 #define HWRM_VNIC_TPA_CFG_INPUT_MAX_AGGS_4 UINT32_C(0x2)
33902 /* 8 aggregations */
33903 #define HWRM_VNIC_TPA_CFG_INPUT_MAX_AGGS_8 UINT32_C(0x3)
33904 /* 16 aggregations */
33905 #define HWRM_VNIC_TPA_CFG_INPUT_MAX_AGGS_16 UINT32_C(0x4)
33906 /* Any aggregation size larger than this is not valid */
33907 #define HWRM_VNIC_TPA_CFG_INPUT_MAX_AGGS_MAX UINT32_C(0x7)
33908 #define HWRM_VNIC_TPA_CFG_INPUT_MAX_AGGS_LAST \
33909 HWRM_VNIC_TPA_CFG_INPUT_MAX_AGGS_MAX
33910 uint8_t unused_0[2];
33912 * This is the maximum amount of time allowed for
33913 * an aggregation context to complete after it was initiated.
33915 uint32_t max_agg_timer;
33917 * This is the minimum amount of payload length required to
33918 * start an aggregation context. This field is deprecated and
33919 * should be set to 0. The minimum length is set by firmware
33920 * and can be queried using hwrm_vnic_tpa_qcfg.
33922 uint32_t min_agg_len;
33925 /* hwrm_vnic_tpa_cfg_output (size:128b/16B) */
33926 struct hwrm_vnic_tpa_cfg_output {
33927 /* The specific error status for the command. */
33928 uint16_t error_code;
33929 /* The HWRM command request type. */
33931 /* The sequence ID from the original command. */
33933 /* The length of the response data in number of bytes. */
33935 uint8_t unused_0[7];
33937 * This field is used in Output records to indicate that the output
33938 * is completely written to RAM. This field should be read as '1'
33939 * to indicate that the output has been completely written.
33940 * When writing a command completion or response to an internal processor,
33941 * the order of writes has to be such that this field is written last.
33946 /*********************
33947 * hwrm_vnic_rss_cfg *
33948 *********************/
33951 /* hwrm_vnic_rss_cfg_input (size:384b/48B) */
33952 struct hwrm_vnic_rss_cfg_input {
33953 /* The HWRM command request type. */
33956 * The completion ring to send the completion event on. This should
33957 * be the NQ ID returned from the `nq_alloc` HWRM command.
33959 uint16_t cmpl_ring;
33961 * The sequence ID is used by the driver for tracking multiple
33962 * commands. This ID is treated as opaque data by the firmware and
33963 * the value is returned in the `hwrm_resp_hdr` upon completion.
33967 * The target ID of the command:
33968 * * 0x0-0xFFF8 - The function ID
33969 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
33970 * * 0xFFFD - Reserved for user-space HWRM interface
33973 uint16_t target_id;
33975 * A physical address pointer pointing to a host buffer that the
33976 * command's response data will be written. This can be either a host
33977 * physical address (HPA) or a guest physical address (GPA) and must
33978 * point to a physically contiguous block of memory.
33980 uint64_t resp_addr;
33981 uint32_t hash_type;
33983 * When this bit is '1', the RSS hash shall be computed
33984 * over source and destination IPv4 addresses of IPv4
33987 #define HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV4 UINT32_C(0x1)
33989 * When this bit is '1', the RSS hash shall be computed
33990 * over source/destination IPv4 addresses and
33991 * source/destination ports of TCP/IPv4 packets.
33993 #define HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV4 UINT32_C(0x2)
33995 * When this bit is '1', the RSS hash shall be computed
33996 * over source/destination IPv4 addresses and
33997 * source/destination ports of UDP/IPv4 packets.
33999 #define HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV4 UINT32_C(0x4)
34001 * When this bit is '1', the RSS hash shall be computed
34002 * over source and destination IPv6 addresses of IPv6
34005 #define HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV6 UINT32_C(0x8)
34007 * When this bit is '1', the RSS hash shall be computed
34008 * over source/destination IPv6 addresses and
34009 * source/destination ports of TCP/IPv6 packets.
34011 #define HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV6 UINT32_C(0x10)
34013 * When this bit is '1', the RSS hash shall be computed
34014 * over source/destination IPv6 addresses and
34015 * source/destination ports of UDP/IPv6 packets.
34017 #define HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV6 UINT32_C(0x20)
34018 /* VNIC ID of VNIC associated with RSS table being configured. */
34021 * Specifies which VNIC ring table pair to configure.
34022 * Valid values range from 0 to 7.
34024 uint8_t ring_table_pair_index;
34025 /* Flags to specify different RSS hash modes. */
34026 uint8_t hash_mode_flags;
34028 * When this bit is '1', it indicates using current RSS
34029 * hash mode setting configured in the device.
34031 #define HWRM_VNIC_RSS_CFG_INPUT_HASH_MODE_FLAGS_DEFAULT \
34034 * When this bit is '1', it indicates requesting support of
34035 * RSS hashing over innermost 4 tuples {l3.src, l3.dest,
34036 * l4.src, l4.dest} for tunnel packets. For none-tunnel
34037 * packets, the RSS hash is computed over the normal
34038 * src/dest l3 and src/dest l4 headers.
34040 #define HWRM_VNIC_RSS_CFG_INPUT_HASH_MODE_FLAGS_INNERMOST_4 \
34043 * When this bit is '1', it indicates requesting support of
34044 * RSS hashing over innermost 2 tuples {l3.src, l3.dest} for
34045 * tunnel packets. For none-tunnel packets, the RSS hash is
34046 * computed over the normal src/dest l3 headers.
34048 #define HWRM_VNIC_RSS_CFG_INPUT_HASH_MODE_FLAGS_INNERMOST_2 \
34051 * When this bit is '1', it indicates requesting support of
34052 * RSS hashing over outermost 4 tuples {t_l3.src, t_l3.dest,
34053 * t_l4.src, t_l4.dest} for tunnel packets. For none-tunnel
34054 * packets, the RSS hash is computed over the normal
34055 * src/dest l3 and src/dest l4 headers.
34057 #define HWRM_VNIC_RSS_CFG_INPUT_HASH_MODE_FLAGS_OUTERMOST_4 \
34060 * When this bit is '1', it indicates requesting support of
34061 * RSS hashing over outermost 2 tuples {t_l3.src, t_l3.dest} for
34062 * tunnel packets. For none-tunnel packets, the RSS hash is
34063 * computed over the normal src/dest l3 headers.
34065 #define HWRM_VNIC_RSS_CFG_INPUT_HASH_MODE_FLAGS_OUTERMOST_2 \
34067 /* This is the address for rss ring group table */
34068 uint64_t ring_grp_tbl_addr;
34069 /* This is the address for rss hash key table */
34070 uint64_t hash_key_tbl_addr;
34071 /* Index to the rss indirection table. */
34072 uint16_t rss_ctx_idx;
34075 * When this bit is '1', it indicates that the hash_type field is
34076 * interpreted as a change relative the current configuration. Each
34077 * '1' bit in hash_type represents a header to add to the current
34078 * hash. Zeroes designate the hash_type state bits that should remain
34079 * unchanged, if possible. If this constraint on the existing state
34080 * cannot be satisfied, then the implementation should preference
34081 * adding other headers so as to honor the request to add the
34082 * specified headers. It is an error to set this flag concurrently
34083 * with hash_type_exclude.
34085 #define HWRM_VNIC_RSS_CFG_INPUT_FLAGS_HASH_TYPE_INCLUDE \
34088 * When this bit is '1', it indicates that the hash_type field is
34089 * interpreted as a change relative the current configuration. Each
34090 * '1' bit in hash_type represents a header to remove from the
34091 * current hash. Zeroes designate the hash_type state bits that
34092 * should remain unchanged, if possible. If this constraint on the
34093 * existing state cannot be satisfied, then the implementation should
34094 * preference removing other headers so as to honor the request to
34095 * remove the specified headers. It is an error to set this flag
34096 * concurrently with hash_type_include.
34098 #define HWRM_VNIC_RSS_CFG_INPUT_FLAGS_HASH_TYPE_EXCLUDE \
34101 * Used to choose the RSS hash algorithm based on which HW
34102 * can select the destination ring
34104 uint8_t rss_hash_function;
34106 * NIC calculates the RSS hash using the Toeplitz algorithm on L3/L4
34107 * headers and uses the hash to select the ring.
34109 #define HWRM_VNIC_RSS_CFG_INPUT_RSS_HASH_FUNCTION_TOEPLITZ \
34112 * NIC calculates the RSS hash using the XOR algorithm on L3/L4
34113 * headers and uses the hash to select the ring.
34115 #define HWRM_VNIC_RSS_CFG_INPUT_RSS_HASH_FUNCTION_XOR \
34118 * In this mode, RSS hash is calculated with Toeplitz and reported
34119 * in the RX completion. However, the ring selection algorithm is
34120 * based on the checksum. In this mode, only the innermost L3/L4
34121 * packet checksums are used. So this hash function mode will not
34122 * be exposed/valid when the outer RSS mode is enabled.
34124 #define HWRM_VNIC_RSS_CFG_INPUT_RSS_HASH_FUNCTION_CHECKSUM \
34126 #define HWRM_VNIC_RSS_CFG_INPUT_RSS_HASH_FUNCTION_LAST \
34127 HWRM_VNIC_RSS_CFG_INPUT_RSS_HASH_FUNCTION_CHECKSUM
34128 uint8_t unused_1[4];
34131 /* hwrm_vnic_rss_cfg_output (size:128b/16B) */
34132 struct hwrm_vnic_rss_cfg_output {
34133 /* The specific error status for the command. */
34134 uint16_t error_code;
34135 /* The HWRM command request type. */
34137 /* The sequence ID from the original command. */
34139 /* The length of the response data in number of bytes. */
34141 uint8_t unused_0[7];
34143 * This field is used in Output records to indicate that the output
34144 * is completely written to RAM. This field should be read as '1'
34145 * to indicate that the output has been completely written.
34146 * When writing a command completion or response to an internal processor,
34147 * the order of writes has to be such that this field is written last.
34152 /* hwrm_vnic_rss_cfg_cmd_err (size:64b/8B) */
34153 struct hwrm_vnic_rss_cfg_cmd_err {
34155 * command specific error codes that goes to
34156 * the cmd_err field in Common HWRM Error Response.
34159 /* Unknown error */
34160 #define HWRM_VNIC_RSS_CFG_CMD_ERR_CODE_UNKNOWN \
34163 * Unable to change global RSS mode to outer due to all active
34164 * interfaces are not ready to support outer RSS hashing.
34166 #define HWRM_VNIC_RSS_CFG_CMD_ERR_CODE_INTERFACE_NOT_READY \
34168 #define HWRM_VNIC_RSS_CFG_CMD_ERR_CODE_LAST \
34169 HWRM_VNIC_RSS_CFG_CMD_ERR_CODE_INTERFACE_NOT_READY
34170 uint8_t unused_0[7];
34173 /**********************
34174 * hwrm_vnic_rss_qcfg *
34175 **********************/
34178 /* hwrm_vnic_rss_qcfg_input (size:192b/24B) */
34179 struct hwrm_vnic_rss_qcfg_input {
34180 /* The HWRM command request type. */
34183 * The completion ring to send the completion event on. This should
34184 * be the NQ ID returned from the `nq_alloc` HWRM command.
34186 uint16_t cmpl_ring;
34188 * The sequence ID is used by the driver for tracking multiple
34189 * commands. This ID is treated as opaque data by the firmware and
34190 * the value is returned in the `hwrm_resp_hdr` upon completion.
34194 * The target ID of the command:
34195 * * 0x0-0xFFF8 - The function ID
34196 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
34197 * * 0xFFFD - Reserved for user-space HWRM interface
34200 uint16_t target_id;
34202 * A physical address pointer pointing to a host buffer that the
34203 * command's response data will be written. This can be either a host
34204 * physical address (HPA) or a guest physical address (GPA) and must
34205 * point to a physically contiguous block of memory.
34207 uint64_t resp_addr;
34208 /* Index to the rss indirection table. */
34209 uint16_t rss_ctx_idx;
34210 uint8_t unused_0[6];
34213 /* hwrm_vnic_rss_qcfg_output (size:512b/64B) */
34214 struct hwrm_vnic_rss_qcfg_output {
34215 /* The specific error status for the command. */
34216 uint16_t error_code;
34217 /* The HWRM command request type. */
34219 /* The sequence ID from the original command. */
34221 /* The length of the response data in number of bytes. */
34223 uint32_t hash_type;
34225 * When this bit is '1', the RSS hash shall be computed
34226 * over source and destination IPv4 addresses of IPv4
34229 #define HWRM_VNIC_RSS_QCFG_OUTPUT_HASH_TYPE_IPV4 UINT32_C(0x1)
34231 * When this bit is '1', the RSS hash shall be computed
34232 * over source/destination IPv4 addresses and
34233 * source/destination ports of TCP/IPv4 packets.
34235 #define HWRM_VNIC_RSS_QCFG_OUTPUT_HASH_TYPE_TCP_IPV4 UINT32_C(0x2)
34237 * When this bit is '1', the RSS hash shall be computed
34238 * over source/destination IPv4 addresses and
34239 * source/destination ports of UDP/IPv4 packets.
34241 #define HWRM_VNIC_RSS_QCFG_OUTPUT_HASH_TYPE_UDP_IPV4 UINT32_C(0x4)
34243 * When this bit is '1', the RSS hash shall be computed
34244 * over source and destination IPv6 addresses of IPv6
34247 #define HWRM_VNIC_RSS_QCFG_OUTPUT_HASH_TYPE_IPV6 UINT32_C(0x8)
34249 * When this bit is '1', the RSS hash shall be computed
34250 * over source/destination IPv6 addresses and
34251 * source/destination ports of TCP/IPv6 packets.
34253 #define HWRM_VNIC_RSS_QCFG_OUTPUT_HASH_TYPE_TCP_IPV6 UINT32_C(0x10)
34255 * When this bit is '1', the RSS hash shall be computed
34256 * over source/destination IPv6 addresses and
34257 * source/destination ports of UDP/IPv6 packets.
34259 #define HWRM_VNIC_RSS_QCFG_OUTPUT_HASH_TYPE_UDP_IPV6 UINT32_C(0x20)
34260 uint8_t unused_0[4];
34261 /* This is the value of rss hash key */
34262 uint32_t hash_key[10];
34263 /* Flags to specify different RSS hash modes. */
34264 uint8_t hash_mode_flags;
34266 * When this bit is '1', it indicates using current RSS
34267 * hash mode setting configured in the device.
34269 #define HWRM_VNIC_RSS_QCFG_OUTPUT_HASH_MODE_FLAGS_DEFAULT \
34272 * When this bit is '1', it indicates requesting support of
34273 * RSS hashing over innermost 4 tuples {l3.src, l3.dest,
34274 * l4.src, l4.dest} for tunnel packets. For none-tunnel
34275 * packets, the RSS hash is computed over the normal
34276 * src/dest l3 and src/dest l4 headers.
34278 #define HWRM_VNIC_RSS_QCFG_OUTPUT_HASH_MODE_FLAGS_INNERMOST_4 \
34281 * When this bit is '1', it indicates requesting support of
34282 * RSS hashing over innermost 2 tuples {l3.src, l3.dest} for
34283 * tunnel packets. For none-tunnel packets, the RSS hash is
34284 * computed over the normal src/dest l3 headers.
34286 #define HWRM_VNIC_RSS_QCFG_OUTPUT_HASH_MODE_FLAGS_INNERMOST_2 \
34289 * When this bit is '1', it indicates requesting support of
34290 * RSS hashing over outermost 4 tuples {t_l3.src, t_l3.dest,
34291 * t_l4.src, t_l4.dest} for tunnel packets. For none-tunnel
34292 * packets, the RSS hash is computed over the normal
34293 * src/dest l3 and src/dest l4 headers.
34295 #define HWRM_VNIC_RSS_QCFG_OUTPUT_HASH_MODE_FLAGS_OUTERMOST_4 \
34298 * When this bit is '1', it indicates requesting support of
34299 * RSS hashing over outermost 2 tuples {t_l3.src, t_l3.dest} for
34300 * tunnel packets. For none-tunnel packets, the RSS hash is
34301 * computed over the normal src/dest l3 headers.
34303 #define HWRM_VNIC_RSS_QCFG_OUTPUT_HASH_MODE_FLAGS_OUTERMOST_2 \
34306 * Used to choose the RSS hash algorithm based on which HW
34307 * can select the destination ring
34309 uint8_t rss_hash_function;
34311 * NIC calculates the RSS hash using the Toeplitz algorithm on L3/L4
34312 * headers and uses the hash to select the ring.
34314 #define HWRM_VNIC_RSS_QCFG_OUTPUT_RSS_HASH_FUNCTION_TOEPLITZ \
34317 * NIC calculates the RSS hash using the XOR algorithm on L3/L4
34318 * headers and uses the hash to select the ring.
34320 #define HWRM_VNIC_RSS_QCFG_OUTPUT_RSS_HASH_FUNCTION_XOR \
34323 * In this mode, RSS hash is calculated with Toeplitz and reported
34324 * in the RX completion. However, the ring selection algorithm is
34325 * based on the checksum. In this mode, only the innermost L3/L4
34326 * packet checksums are used. So this hash function mode will not
34327 * be exposed/valid when the outer RSS mode is enabled.
34329 #define HWRM_VNIC_RSS_QCFG_OUTPUT_RSS_HASH_FUNCTION_CHECKSUM \
34331 #define HWRM_VNIC_RSS_QCFG_OUTPUT_RSS_HASH_FUNCTION_LAST \
34332 HWRM_VNIC_RSS_QCFG_OUTPUT_RSS_HASH_FUNCTION_CHECKSUM
34333 uint8_t unused_1[5];
34335 * This field is used in Output records to indicate that the output
34336 * is completely written to RAM. This field should be read as '1'
34337 * to indicate that the output has been completely written.
34338 * When writing a command completion or response to an internal processor,
34339 * the order of writes has to be such that this field is written last.
34344 /**************************
34345 * hwrm_vnic_plcmodes_cfg *
34346 **************************/
34349 /* hwrm_vnic_plcmodes_cfg_input (size:320b/40B) */
34350 struct hwrm_vnic_plcmodes_cfg_input {
34351 /* The HWRM command request type. */
34354 * The completion ring to send the completion event on. This should
34355 * be the NQ ID returned from the `nq_alloc` HWRM command.
34357 uint16_t cmpl_ring;
34359 * The sequence ID is used by the driver for tracking multiple
34360 * commands. This ID is treated as opaque data by the firmware and
34361 * the value is returned in the `hwrm_resp_hdr` upon completion.
34365 * The target ID of the command:
34366 * * 0x0-0xFFF8 - The function ID
34367 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
34368 * * 0xFFFD - Reserved for user-space HWRM interface
34371 uint16_t target_id;
34373 * A physical address pointer pointing to a host buffer that the
34374 * command's response data will be written. This can be either a host
34375 * physical address (HPA) or a guest physical address (GPA) and must
34376 * point to a physically contiguous block of memory.
34378 uint64_t resp_addr;
34381 * When this bit is '1', the VNIC shall be configured to
34382 * use regular placement algorithm.
34383 * By default, the regular placement algorithm shall be
34384 * enabled on the VNIC.
34386 #define HWRM_VNIC_PLCMODES_CFG_INPUT_FLAGS_REGULAR_PLACEMENT \
34389 * When this bit is '1', the VNIC shall be configured
34390 * use the jumbo placement algorithm.
34392 #define HWRM_VNIC_PLCMODES_CFG_INPUT_FLAGS_JUMBO_PLACEMENT \
34395 * When this bit is '1', the VNIC shall be configured
34396 * to enable Header-Data split for IPv4 packets according
34397 * to the following rules:
34398 * # If the packet is identified as TCP/IPv4, then the
34399 * packet is split at the beginning of the TCP payload.
34400 * # If the packet is identified as UDP/IPv4, then the
34401 * packet is split at the beginning of UDP payload.
34402 * # If the packet is identified as non-TCP and non-UDP
34403 * IPv4 packet, then the packet is split at the beginning
34404 * of the upper layer protocol header carried in the IPv4
34407 #define HWRM_VNIC_PLCMODES_CFG_INPUT_FLAGS_HDS_IPV4 \
34410 * When this bit is '1', the VNIC shall be configured
34411 * to enable Header-Data split for IPv6 packets according
34412 * to the following rules:
34413 * # If the packet is identified as TCP/IPv6, then the
34414 * packet is split at the beginning of the TCP payload.
34415 * # If the packet is identified as UDP/IPv6, then the
34416 * packet is split at the beginning of UDP payload.
34417 * # If the packet is identified as non-TCP and non-UDP
34418 * IPv6 packet, then the packet is split at the beginning
34419 * of the upper layer protocol header carried in the IPv6
34422 #define HWRM_VNIC_PLCMODES_CFG_INPUT_FLAGS_HDS_IPV6 \
34425 * When this bit is '1', the VNIC shall be configured
34426 * to enable Header-Data split for FCoE packets at the
34427 * beginning of FC payload.
34429 #define HWRM_VNIC_PLCMODES_CFG_INPUT_FLAGS_HDS_FCOE \
34432 * When this bit is '1', the VNIC shall be configured
34433 * to enable Header-Data split for RoCE packets at the
34434 * beginning of RoCE payload (after BTH/GRH headers).
34436 #define HWRM_VNIC_PLCMODES_CFG_INPUT_FLAGS_HDS_ROCE \
34439 * When this bit is '1', the VNIC shall be configured use the virtio
34440 * placement algorithm. This feature can only be configured when
34441 * proxy mode is supported on the function.
34443 #define HWRM_VNIC_PLCMODES_CFG_INPUT_FLAGS_VIRTIO_PLACEMENT \
34447 * This bit must be '1' for the jumbo_thresh_valid field to be
34450 #define HWRM_VNIC_PLCMODES_CFG_INPUT_ENABLES_JUMBO_THRESH_VALID \
34453 * This bit must be '1' for the hds_offset_valid field to be
34456 #define HWRM_VNIC_PLCMODES_CFG_INPUT_ENABLES_HDS_OFFSET_VALID \
34459 * This bit must be '1' for the hds_threshold_valid field to be
34462 #define HWRM_VNIC_PLCMODES_CFG_INPUT_ENABLES_HDS_THRESHOLD_VALID \
34465 * This bit must be '1' for the max_bds_valid field to be
34468 #define HWRM_VNIC_PLCMODES_CFG_INPUT_ENABLES_MAX_BDS_VALID \
34470 /* Logical vnic ID */
34473 * When jumbo placement algorithm is enabled, this value
34474 * is used to determine the threshold for jumbo placement.
34475 * Packets with length larger than this value will be
34476 * placed according to the jumbo placement algorithm.
34478 uint16_t jumbo_thresh;
34480 * This value is used to determine the offset into
34481 * packet buffer where the split data (payload) will be
34482 * placed according to one of HDS placement algorithm.
34484 * The lengths of packet buffers provided for split data
34485 * shall be larger than this value.
34487 uint16_t hds_offset;
34489 * When one of the HDS placement algorithm is enabled, this
34490 * value is used to determine the threshold for HDS
34492 * Packets with length larger than this value will be
34493 * placed according to the HDS placement algorithm.
34494 * This value shall be in multiple of 4 bytes.
34496 uint16_t hds_threshold;
34498 * When virtio placement algorithm is enabled, this
34499 * value is used to determine the maximum number of BDs
34500 * that can be used to place an Rx Packet.
34501 * If an incoming packet does not fit in the buffers described
34502 * by the max BDs, the packet will be dropped and an error
34503 * will be reported in the completion. Valid values for this
34504 * field are between 1 and 8. If the VNIC uses header-data-
34505 * separation and/or TPA with buffer spanning enabled, valid
34506 * values for this field are between 2 and 8.
34507 * This feature can only be configured when proxy mode is
34508 * supported on the function.
34511 uint8_t unused_0[4];
34514 /* hwrm_vnic_plcmodes_cfg_output (size:128b/16B) */
34515 struct hwrm_vnic_plcmodes_cfg_output {
34516 /* The specific error status for the command. */
34517 uint16_t error_code;
34518 /* The HWRM command request type. */
34520 /* The sequence ID from the original command. */
34522 /* The length of the response data in number of bytes. */
34524 uint8_t unused_0[7];
34526 * This field is used in Output records to indicate that the output
34527 * is completely written to RAM. This field should be read as '1'
34528 * to indicate that the output has been completely written.
34529 * When writing a command completion or response to an internal
34530 * processor, the order of writes has to be such that this field is
34536 /***************************
34537 * hwrm_vnic_plcmodes_qcfg *
34538 ***************************/
34541 /* hwrm_vnic_plcmodes_qcfg_input (size:192b/24B) */
34542 struct hwrm_vnic_plcmodes_qcfg_input {
34543 /* The HWRM command request type. */
34546 * The completion ring to send the completion event on. This should
34547 * be the NQ ID returned from the `nq_alloc` HWRM command.
34549 uint16_t cmpl_ring;
34551 * The sequence ID is used by the driver for tracking multiple
34552 * commands. This ID is treated as opaque data by the firmware and
34553 * the value is returned in the `hwrm_resp_hdr` upon completion.
34557 * The target ID of the command:
34558 * * 0x0-0xFFF8 - The function ID
34559 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
34560 * * 0xFFFD - Reserved for user-space HWRM interface
34563 uint16_t target_id;
34565 * A physical address pointer pointing to a host buffer that the
34566 * command's response data will be written. This can be either a host
34567 * physical address (HPA) or a guest physical address (GPA) and must
34568 * point to a physically contiguous block of memory.
34570 uint64_t resp_addr;
34571 /* Logical vnic ID */
34573 uint8_t unused_0[4];
34576 /* hwrm_vnic_plcmodes_qcfg_output (size:192b/24B) */
34577 struct hwrm_vnic_plcmodes_qcfg_output {
34578 /* The specific error status for the command. */
34579 uint16_t error_code;
34580 /* The HWRM command request type. */
34582 /* The sequence ID from the original command. */
34584 /* The length of the response data in number of bytes. */
34588 * When this bit is '1', the VNIC is configured to
34589 * use regular placement algorithm.
34591 #define HWRM_VNIC_PLCMODES_QCFG_OUTPUT_FLAGS_REGULAR_PLACEMENT \
34594 * When this bit is '1', the VNIC is configured to
34595 * use the jumbo placement algorithm.
34597 #define HWRM_VNIC_PLCMODES_QCFG_OUTPUT_FLAGS_JUMBO_PLACEMENT \
34600 * When this bit is '1', the VNIC is configured
34601 * to enable Header-Data split for IPv4 packets.
34603 #define HWRM_VNIC_PLCMODES_QCFG_OUTPUT_FLAGS_HDS_IPV4 \
34606 * When this bit is '1', the VNIC is configured
34607 * to enable Header-Data split for IPv6 packets.
34609 #define HWRM_VNIC_PLCMODES_QCFG_OUTPUT_FLAGS_HDS_IPV6 \
34612 * When this bit is '1', the VNIC is configured
34613 * to enable Header-Data split for FCoE packets.
34615 #define HWRM_VNIC_PLCMODES_QCFG_OUTPUT_FLAGS_HDS_FCOE \
34618 * When this bit is '1', the VNIC is configured
34619 * to enable Header-Data split for RoCE packets.
34621 #define HWRM_VNIC_PLCMODES_QCFG_OUTPUT_FLAGS_HDS_ROCE \
34624 * When this bit is '1', the VNIC is configured
34625 * to be the default VNIC of the requesting function.
34627 #define HWRM_VNIC_PLCMODES_QCFG_OUTPUT_FLAGS_DFLT_VNIC \
34630 * When this bit is '1', the VNIC is configured to use the virtio
34631 * placement algorithm. This feature can only be configured when
34632 * proxy mode is supported on the function.
34634 #define HWRM_VNIC_PLCMODES_QCFG_OUTPUT_FLAGS_VIRTIO_PLACEMENT \
34637 * When jumbo placement algorithm is enabled, this value
34638 * is used to determine the threshold for jumbo placement.
34639 * Packets with length larger than this value will be
34640 * placed according to the jumbo placement algorithm.
34642 uint16_t jumbo_thresh;
34644 * This value is used to determine the offset into
34645 * packet buffer where the split data (payload) will be
34646 * placed according to one of HDS placement algorithm.
34648 * The lengths of packet buffers provided for split data
34649 * shall be larger than this value.
34651 uint16_t hds_offset;
34653 * When one of the HDS placement algorithm is enabled, this
34654 * value is used to determine the threshold for HDS
34656 * Packets with length larger than this value will be
34657 * placed according to the HDS placement algorithm.
34658 * This value shall be in multiple of 4 bytes.
34660 uint16_t hds_threshold;
34662 * When virtio placement algorithm is enabled, this
34663 * value is used to determine the maximum number of BDs
34664 * that can be used to place an Rx Packet.
34665 * If an incoming packet does not fit in the buffers described
34666 * by the max BDs, the packet will be dropped and an error
34667 * will be reported in the completion. Valid values for this
34668 * field are between 1 and 8. If the VNIC uses header-data-
34669 * separation and/or TPA with buffer spanning enabled, valid
34670 * values for this field are between 2 and 8.
34671 * This feature can only be configured when proxy mode is supported
34675 uint8_t unused_0[3];
34677 * This field is used in Output records to indicate that the output
34678 * is completely written to RAM. This field should be read as '1'
34679 * to indicate that the output has been completely written.
34680 * When writing a command completion or response to an internal
34681 * processor, the order of writes has to be such that this field is
34687 /**********************************
34688 * hwrm_vnic_rss_cos_lb_ctx_alloc *
34689 **********************************/
34692 /* hwrm_vnic_rss_cos_lb_ctx_alloc_input (size:128b/16B) */
34693 struct hwrm_vnic_rss_cos_lb_ctx_alloc_input {
34694 /* The HWRM command request type. */
34697 * The completion ring to send the completion event on. This should
34698 * be the NQ ID returned from the `nq_alloc` HWRM command.
34700 uint16_t cmpl_ring;
34702 * The sequence ID is used by the driver for tracking multiple
34703 * commands. This ID is treated as opaque data by the firmware and
34704 * the value is returned in the `hwrm_resp_hdr` upon completion.
34708 * The target ID of the command:
34709 * * 0x0-0xFFF8 - The function ID
34710 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
34711 * * 0xFFFD - Reserved for user-space HWRM interface
34714 uint16_t target_id;
34716 * A physical address pointer pointing to a host buffer that the
34717 * command's response data will be written. This can be either a host
34718 * physical address (HPA) or a guest physical address (GPA) and must
34719 * point to a physically contiguous block of memory.
34721 uint64_t resp_addr;
34724 /* hwrm_vnic_rss_cos_lb_ctx_alloc_output (size:128b/16B) */
34725 struct hwrm_vnic_rss_cos_lb_ctx_alloc_output {
34726 /* The specific error status for the command. */
34727 uint16_t error_code;
34728 /* The HWRM command request type. */
34730 /* The sequence ID from the original command. */
34732 /* The length of the response data in number of bytes. */
34734 /* rss_cos_lb_ctx_id is 16 b */
34735 uint16_t rss_cos_lb_ctx_id;
34736 uint8_t unused_0[5];
34738 * This field is used in Output records to indicate that the output
34739 * is completely written to RAM. This field should be read as '1'
34740 * to indicate that the output has been completely written.
34741 * When writing a command completion or response to an internal processor,
34742 * the order of writes has to be such that this field is written last.
34747 /*********************************
34748 * hwrm_vnic_rss_cos_lb_ctx_free *
34749 *********************************/
34752 /* hwrm_vnic_rss_cos_lb_ctx_free_input (size:192b/24B) */
34753 struct hwrm_vnic_rss_cos_lb_ctx_free_input {
34754 /* The HWRM command request type. */
34757 * The completion ring to send the completion event on. This should
34758 * be the NQ ID returned from the `nq_alloc` HWRM command.
34760 uint16_t cmpl_ring;
34762 * The sequence ID is used by the driver for tracking multiple
34763 * commands. This ID is treated as opaque data by the firmware and
34764 * the value is returned in the `hwrm_resp_hdr` upon completion.
34768 * The target ID of the command:
34769 * * 0x0-0xFFF8 - The function ID
34770 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
34771 * * 0xFFFD - Reserved for user-space HWRM interface
34774 uint16_t target_id;
34776 * A physical address pointer pointing to a host buffer that the
34777 * command's response data will be written. This can be either a host
34778 * physical address (HPA) or a guest physical address (GPA) and must
34779 * point to a physically contiguous block of memory.
34781 uint64_t resp_addr;
34782 /* rss_cos_lb_ctx_id is 16 b */
34783 uint16_t rss_cos_lb_ctx_id;
34784 uint8_t unused_0[6];
34787 /* hwrm_vnic_rss_cos_lb_ctx_free_output (size:128b/16B) */
34788 struct hwrm_vnic_rss_cos_lb_ctx_free_output {
34789 /* The specific error status for the command. */
34790 uint16_t error_code;
34791 /* The HWRM command request type. */
34793 /* The sequence ID from the original command. */
34795 /* The length of the response data in number of bytes. */
34797 uint8_t unused_0[7];
34799 * This field is used in Output records to indicate that the output
34800 * is completely written to RAM. This field should be read as '1'
34801 * to indicate that the output has been completely written.
34802 * When writing a command completion or response to an internal processor,
34803 * the order of writes has to be such that this field is written last.
34808 /*******************
34809 * hwrm_ring_alloc *
34810 *******************/
34813 /* hwrm_ring_alloc_input (size:704b/88B) */
34814 struct hwrm_ring_alloc_input {
34815 /* The HWRM command request type. */
34818 * The completion ring to send the completion event on. This should
34819 * be the NQ ID returned from the `nq_alloc` HWRM command.
34821 uint16_t cmpl_ring;
34823 * The sequence ID is used by the driver for tracking multiple
34824 * commands. This ID is treated as opaque data by the firmware and
34825 * the value is returned in the `hwrm_resp_hdr` upon completion.
34829 * The target ID of the command:
34830 * * 0x0-0xFFF8 - The function ID
34831 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
34832 * * 0xFFFD - Reserved for user-space HWRM interface
34835 uint16_t target_id;
34837 * A physical address pointer pointing to a host buffer that the
34838 * command's response data will be written. This can be either a host
34839 * physical address (HPA) or a guest physical address (GPA) and must
34840 * point to a physically contiguous block of memory.
34842 uint64_t resp_addr;
34845 * This bit must be '1' for the ring_arb_cfg field to be
34848 #define HWRM_RING_ALLOC_INPUT_ENABLES_RING_ARB_CFG \
34851 * This bit must be '1' for the stat_ctx_id_valid field to be
34854 #define HWRM_RING_ALLOC_INPUT_ENABLES_STAT_CTX_ID_VALID \
34857 * This bit must be '1' for the max_bw_valid field to be
34860 #define HWRM_RING_ALLOC_INPUT_ENABLES_MAX_BW_VALID \
34863 * This bit must be '1' for the rx_ring_id field to be
34866 #define HWRM_RING_ALLOC_INPUT_ENABLES_RX_RING_ID_VALID \
34869 * This bit must be '1' for the nq_ring_id field to be
34872 #define HWRM_RING_ALLOC_INPUT_ENABLES_NQ_RING_ID_VALID \
34875 * This bit must be '1' for the rx_buf_size field to be
34878 #define HWRM_RING_ALLOC_INPUT_ENABLES_RX_BUF_SIZE_VALID \
34881 * This bit must be '1' for the schq_id field to be
34884 #define HWRM_RING_ALLOC_INPUT_ENABLES_SCHQ_ID \
34887 * This bit must be '1' for the mpc_chnls_type field to be
34890 #define HWRM_RING_ALLOC_INPUT_ENABLES_MPC_CHNLS_TYPE \
34894 /* L2 Completion Ring (CR) */
34895 #define HWRM_RING_ALLOC_INPUT_RING_TYPE_L2_CMPL UINT32_C(0x0)
34897 #define HWRM_RING_ALLOC_INPUT_RING_TYPE_TX UINT32_C(0x1)
34899 #define HWRM_RING_ALLOC_INPUT_RING_TYPE_RX UINT32_C(0x2)
34900 /* RoCE Notification Completion Ring (ROCE_CR) */
34901 #define HWRM_RING_ALLOC_INPUT_RING_TYPE_ROCE_CMPL UINT32_C(0x3)
34902 /* RX Aggregation Ring */
34903 #define HWRM_RING_ALLOC_INPUT_RING_TYPE_RX_AGG UINT32_C(0x4)
34904 /* Notification Queue */
34905 #define HWRM_RING_ALLOC_INPUT_RING_TYPE_NQ UINT32_C(0x5)
34906 #define HWRM_RING_ALLOC_INPUT_RING_TYPE_LAST \
34907 HWRM_RING_ALLOC_INPUT_RING_TYPE_NQ
34909 * This field controls the number of packets transmitted before a TX
34910 * completion is generated. Non-zero values for the field are only
34911 * valid if HWRM_FUNC_QCAPS indicates that the TX coalesced completion
34912 * records capability is supported.
34914 uint8_t cmpl_coal_cnt;
34915 /* Generates a legacy TX completion on every packet. */
34916 #define HWRM_RING_ALLOC_INPUT_CMPL_COAL_CNT_COAL_OFF UINT32_C(0x0)
34917 /* Generates a TX coalesced completion for up to 4 TX packets. */
34918 #define HWRM_RING_ALLOC_INPUT_CMPL_COAL_CNT_COAL_4 UINT32_C(0x1)
34919 /* Generates a TX coalesced completion for up to 8 TX packets. */
34920 #define HWRM_RING_ALLOC_INPUT_CMPL_COAL_CNT_COAL_8 UINT32_C(0x2)
34921 /* Generates a TX coalesced completion for up to 12 TX packets. */
34922 #define HWRM_RING_ALLOC_INPUT_CMPL_COAL_CNT_COAL_12 UINT32_C(0x3)
34923 /* Generates a TX coalesced completion for up to 16 TX packets. */
34924 #define HWRM_RING_ALLOC_INPUT_CMPL_COAL_CNT_COAL_16 UINT32_C(0x4)
34925 /* Generates a TX coalesced completion for up to 24 TX packets. */
34926 #define HWRM_RING_ALLOC_INPUT_CMPL_COAL_CNT_COAL_24 UINT32_C(0x5)
34927 /* Generates a TX coalesced completion for up to 32 TX packets. */
34928 #define HWRM_RING_ALLOC_INPUT_CMPL_COAL_CNT_COAL_32 UINT32_C(0x6)
34929 /* Generates a TX coalesced completion for up to 48 TX packets. */
34930 #define HWRM_RING_ALLOC_INPUT_CMPL_COAL_CNT_COAL_48 UINT32_C(0x7)
34931 /* Generates a TX coalesced completion for up to 64 TX packets. */
34932 #define HWRM_RING_ALLOC_INPUT_CMPL_COAL_CNT_COAL_64 UINT32_C(0x8)
34933 /* Generates a TX coalesced completion for up to 96 TX packets. */
34934 #define HWRM_RING_ALLOC_INPUT_CMPL_COAL_CNT_COAL_96 UINT32_C(0x9)
34935 /* Generates a TX coalesced completion for up to 128 TX packets. */
34936 #define HWRM_RING_ALLOC_INPUT_CMPL_COAL_CNT_COAL_128 UINT32_C(0xa)
34937 /* Generates a TX coalesced completion for up to 192 TX packets. */
34938 #define HWRM_RING_ALLOC_INPUT_CMPL_COAL_CNT_COAL_192 UINT32_C(0xb)
34939 /* Generates a TX coalesced completion for up to 256 TX packets. */
34940 #define HWRM_RING_ALLOC_INPUT_CMPL_COAL_CNT_COAL_256 UINT32_C(0xc)
34941 /* Generates a TX coalesced completion for up to 320 TX packets. */
34942 #define HWRM_RING_ALLOC_INPUT_CMPL_COAL_CNT_COAL_320 UINT32_C(0xd)
34943 /* Generates a TX coalesced completion for up to 384 TX packets. */
34944 #define HWRM_RING_ALLOC_INPUT_CMPL_COAL_CNT_COAL_384 UINT32_C(0xe)
34945 /* Generates a TX coalesced completion up to the last packet. (Maximum coalescing). */
34946 #define HWRM_RING_ALLOC_INPUT_CMPL_COAL_CNT_COAL_MAX UINT32_C(0xf)
34947 #define HWRM_RING_ALLOC_INPUT_CMPL_COAL_CNT_LAST \
34948 HWRM_RING_ALLOC_INPUT_CMPL_COAL_CNT_COAL_MAX
34949 /* Ring allocation flags. */
34952 * For Rx rings, the incoming packet data can be placed at either
34953 * a 0B or 2B offset from the start of the Rx packet buffer. When
34954 * '1', the received packet will be padded with 2B of zeros at the
34955 * front of the packet. Note that this flag is only used for
34956 * Rx rings and is ignored for all other rings included Rx
34957 * Aggregation rings.
34959 #define HWRM_RING_ALLOC_INPUT_FLAGS_RX_SOP_PAD UINT32_C(0x1)
34961 * This value is a pointer to the page table for the
34964 uint64_t page_tbl_addr;
34965 /* First Byte Offset of the first entry in the first page. */
34968 * Actual page size in 2^page_size. The supported range is increments
34969 * in powers of 2 from 16 bytes to 1GB.
34971 * Page size is 16 B.
34973 * Page size is 4 KB.
34975 * Page size is 8 KB.
34977 * Page size is 64 KB.
34979 * Page size is 2 MB.
34981 * Page size is 4 MB.
34983 * Page size is 1 GB.
34987 * This value indicates the depth of page table.
34988 * For this version of the specification, value other than 0 or
34989 * 1 shall be considered as an invalid value.
34990 * When the page_tbl_depth = 0, then it is treated as a
34991 * special case with the following.
34992 * 1. FBO and page size fields are not valid.
34993 * 2. page_tbl_addr is the physical address of the first
34994 * element of the ring.
34996 uint8_t page_tbl_depth;
34997 /* Used by a PF driver to associate a SCHQ with one of its TX rings. */
35000 * Number of 16B units in the ring. Minimum size for
35001 * a ring is 16 16B entries.
35005 * Logical ring number for the ring to be allocated.
35006 * This value determines the position in the doorbell
35007 * area where the update to the ring will be made.
35009 * For completion rings, this value is also the MSI-X
35010 * vector number for the function the completion ring is
35013 uint16_t logical_id;
35015 * This field is used only when ring_type is a TX ring.
35016 * This value indicates what completion ring the TX ring
35017 * is associated with.
35019 uint16_t cmpl_ring_id;
35021 * This field is used only when ring_type is a TX ring.
35022 * This value indicates what CoS queue the TX ring
35023 * is associated with.
35027 * When allocating a Rx ring or Rx aggregation ring, this field
35028 * specifies the size of the buffer descriptors posted to the ring.
35030 uint16_t rx_buf_size;
35032 * When allocating an Rx aggregation ring, this field
35033 * specifies the associated Rx ring ID.
35035 uint16_t rx_ring_id;
35037 * When allocating a completion ring, this field
35038 * specifies the associated NQ ring ID.
35040 uint16_t nq_ring_id;
35042 * This field is used only when ring_type is a TX ring.
35043 * This field is used to configure arbitration related
35044 * parameters for a TX ring.
35046 uint16_t ring_arb_cfg;
35047 /* Arbitration policy used for the ring. */
35048 #define HWRM_RING_ALLOC_INPUT_RING_ARB_CFG_ARB_POLICY_MASK \
35050 #define HWRM_RING_ALLOC_INPUT_RING_ARB_CFG_ARB_POLICY_SFT 0
35052 * Use strict priority for the TX ring.
35053 * Priority value is specified in arb_policy_param
35055 #define HWRM_RING_ALLOC_INPUT_RING_ARB_CFG_ARB_POLICY_SP \
35058 * Use weighted fair queue arbitration for the TX ring.
35059 * Weight is specified in arb_policy_param
35061 #define HWRM_RING_ALLOC_INPUT_RING_ARB_CFG_ARB_POLICY_WFQ \
35063 #define HWRM_RING_ALLOC_INPUT_RING_ARB_CFG_ARB_POLICY_LAST \
35064 HWRM_RING_ALLOC_INPUT_RING_ARB_CFG_ARB_POLICY_WFQ
35065 /* Reserved field. */
35066 #define HWRM_RING_ALLOC_INPUT_RING_ARB_CFG_RSVD_MASK \
35068 #define HWRM_RING_ALLOC_INPUT_RING_ARB_CFG_RSVD_SFT 4
35070 * Arbitration policy specific parameter.
35071 * # For strict priority arbitration policy, this field
35072 * represents a priority value. If set to 0, then the priority
35073 * is not specified and the HWRM is allowed to select
35074 * any priority for this TX ring.
35075 * # For weighted fair queue arbitration policy, this field
35076 * represents a weight value. If set to 0, then the weight
35077 * is not specified and the HWRM is allowed to select
35078 * any weight for this TX ring.
35080 #define HWRM_RING_ALLOC_INPUT_RING_ARB_CFG_ARB_POLICY_PARAM_MASK \
35082 #define HWRM_RING_ALLOC_INPUT_RING_ARB_CFG_ARB_POLICY_PARAM_SFT 8
35085 * This field is reserved for the future use.
35086 * It shall be set to 0.
35088 uint32_t reserved3;
35090 * This field is used only when ring_type is a TX ring.
35091 * This input indicates what statistics context this ring
35092 * should be associated with.
35094 uint32_t stat_ctx_id;
35096 * This field is reserved for the future use.
35097 * It shall be set to 0.
35099 uint32_t reserved4;
35101 * This field is used only when ring_type is a TX ring
35102 * to specify maximum BW allocated to the TX ring.
35103 * The HWRM will translate this value into byte counter and
35104 * time interval used for this ring inside the device.
35107 /* The bandwidth value. */
35108 #define HWRM_RING_ALLOC_INPUT_MAX_BW_BW_VALUE_MASK \
35109 UINT32_C(0xfffffff)
35110 #define HWRM_RING_ALLOC_INPUT_MAX_BW_BW_VALUE_SFT 0
35111 /* The granularity of the value (bits or bytes). */
35112 #define HWRM_RING_ALLOC_INPUT_MAX_BW_SCALE \
35113 UINT32_C(0x10000000)
35114 /* Value is in bits. */
35115 #define HWRM_RING_ALLOC_INPUT_MAX_BW_SCALE_BITS \
35116 (UINT32_C(0x0) << 28)
35117 /* Value is in bytes. */
35118 #define HWRM_RING_ALLOC_INPUT_MAX_BW_SCALE_BYTES \
35119 (UINT32_C(0x1) << 28)
35120 #define HWRM_RING_ALLOC_INPUT_MAX_BW_SCALE_LAST \
35121 HWRM_RING_ALLOC_INPUT_MAX_BW_SCALE_BYTES
35122 /* bw_value_unit is 3 b */
35123 #define HWRM_RING_ALLOC_INPUT_MAX_BW_BW_VALUE_UNIT_MASK \
35124 UINT32_C(0xe0000000)
35125 #define HWRM_RING_ALLOC_INPUT_MAX_BW_BW_VALUE_UNIT_SFT 29
35126 /* Value is in Mb or MB (base 10). */
35127 #define HWRM_RING_ALLOC_INPUT_MAX_BW_BW_VALUE_UNIT_MEGA \
35128 (UINT32_C(0x0) << 29)
35129 /* Value is in Kb or KB (base 10). */
35130 #define HWRM_RING_ALLOC_INPUT_MAX_BW_BW_VALUE_UNIT_KILO \
35131 (UINT32_C(0x2) << 29)
35132 /* Value is in bits or bytes. */
35133 #define HWRM_RING_ALLOC_INPUT_MAX_BW_BW_VALUE_UNIT_BASE \
35134 (UINT32_C(0x4) << 29)
35135 /* Value is in Gb or GB (base 10). */
35136 #define HWRM_RING_ALLOC_INPUT_MAX_BW_BW_VALUE_UNIT_GIGA \
35137 (UINT32_C(0x6) << 29)
35138 /* Value is in 1/100th of a percentage of total bandwidth. */
35139 #define HWRM_RING_ALLOC_INPUT_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 \
35140 (UINT32_C(0x1) << 29)
35142 #define HWRM_RING_ALLOC_INPUT_MAX_BW_BW_VALUE_UNIT_INVALID \
35143 (UINT32_C(0x7) << 29)
35144 #define HWRM_RING_ALLOC_INPUT_MAX_BW_BW_VALUE_UNIT_LAST \
35145 HWRM_RING_ALLOC_INPUT_MAX_BW_BW_VALUE_UNIT_INVALID
35147 * This field is used only when ring_type is a Completion ring.
35148 * This value indicates what interrupt mode should be used
35149 * on this completion ring.
35150 * Note: In the legacy interrupt mode, no more than 16
35151 * completion rings are allowed.
35155 #define HWRM_RING_ALLOC_INPUT_INT_MODE_LEGACY UINT32_C(0x0)
35157 #define HWRM_RING_ALLOC_INPUT_INT_MODE_RSVD UINT32_C(0x1)
35159 #define HWRM_RING_ALLOC_INPUT_INT_MODE_MSIX UINT32_C(0x2)
35160 /* No Interrupt - Polled mode */
35161 #define HWRM_RING_ALLOC_INPUT_INT_MODE_POLL UINT32_C(0x3)
35162 #define HWRM_RING_ALLOC_INPUT_INT_MODE_LAST \
35163 HWRM_RING_ALLOC_INPUT_INT_MODE_POLL
35164 /* Midpath channel type */
35165 uint8_t mpc_chnls_type;
35167 * Indicate the TX ring alloc MPC channel type is a MPC channel
35168 * with destination to the TX crypto engine block.
35170 #define HWRM_RING_ALLOC_INPUT_MPC_CHNLS_TYPE_TCE UINT32_C(0x0)
35172 * Indicate the RX ring alloc MPC channel type is a MPC channel
35173 * with destination to the RX crypto engine block.
35175 #define HWRM_RING_ALLOC_INPUT_MPC_CHNLS_TYPE_RCE UINT32_C(0x1)
35177 * Indicate the RX ring alloc MPC channel type is a MPC channel
35178 * with destination to the TX configurable flow processing block.
35180 #define HWRM_RING_ALLOC_INPUT_MPC_CHNLS_TYPE_TE_CFA UINT32_C(0x2)
35182 * Indicate the RX ring alloc MPC channel type is a MPC channel
35183 * with destination to the RX configurable flow processing block.
35185 #define HWRM_RING_ALLOC_INPUT_MPC_CHNLS_TYPE_RE_CFA UINT32_C(0x3)
35187 * Indicate the RX ring alloc MPC channel type is a MPC channel
35188 * with destination to the primate processor block.
35190 #define HWRM_RING_ALLOC_INPUT_MPC_CHNLS_TYPE_PRIMATE UINT32_C(0x4)
35191 #define HWRM_RING_ALLOC_INPUT_MPC_CHNLS_TYPE_LAST \
35192 HWRM_RING_ALLOC_INPUT_MPC_CHNLS_TYPE_PRIMATE
35193 uint8_t unused_4[2];
35195 * The cq_handle is specified when allocating a completion ring. For
35196 * devices that support NQs, this cq_handle will be included in the
35197 * NQE to specify which CQ should be read to retrieve the completion
35200 uint64_t cq_handle;
35203 /* hwrm_ring_alloc_output (size:128b/16B) */
35204 struct hwrm_ring_alloc_output {
35205 /* The specific error status for the command. */
35206 uint16_t error_code;
35207 /* The HWRM command request type. */
35209 /* The sequence ID from the original command. */
35211 /* The length of the response data in number of bytes. */
35214 * Physical number of ring allocated.
35215 * This value shall be unique for a ring type.
35218 /* Logical number of ring allocated. */
35219 uint16_t logical_ring_id;
35221 * This field will tell whether to use ping or pong buffer
35222 * for first push operation.
35224 uint8_t push_buffer_index;
35225 /* Start push from ping buffer index */
35226 #define HWRM_RING_ALLOC_OUTPUT_PUSH_BUFFER_INDEX_PING_BUFFER \
35228 /* Start push from pong buffer index */
35229 #define HWRM_RING_ALLOC_OUTPUT_PUSH_BUFFER_INDEX_PONG_BUFFER \
35231 #define HWRM_RING_ALLOC_OUTPUT_PUSH_BUFFER_INDEX_LAST \
35232 HWRM_RING_ALLOC_OUTPUT_PUSH_BUFFER_INDEX_PONG_BUFFER
35233 uint8_t unused_0[2];
35235 * This field is used in Output records to indicate that the output
35236 * is completely written to RAM. This field should be read as '1'
35237 * to indicate that the output has been completely written.
35238 * When writing a command completion or response to an internal processor,
35239 * the order of writes has to be such that this field is written last.
35244 /******************
35246 ******************/
35249 /* hwrm_ring_free_input (size:256b/32B) */
35250 struct hwrm_ring_free_input {
35251 /* The HWRM command request type. */
35254 * The completion ring to send the completion event on. This should
35255 * be the NQ ID returned from the `nq_alloc` HWRM command.
35257 uint16_t cmpl_ring;
35259 * The sequence ID is used by the driver for tracking multiple
35260 * commands. This ID is treated as opaque data by the firmware and
35261 * the value is returned in the `hwrm_resp_hdr` upon completion.
35265 * The target ID of the command:
35266 * * 0x0-0xFFF8 - The function ID
35267 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
35268 * * 0xFFFD - Reserved for user-space HWRM interface
35271 uint16_t target_id;
35273 * A physical address pointer pointing to a host buffer that the
35274 * command's response data will be written. This can be either a host
35275 * physical address (HPA) or a guest physical address (GPA) and must
35276 * point to a physically contiguous block of memory.
35278 uint64_t resp_addr;
35281 /* L2 Completion Ring (CR) */
35282 #define HWRM_RING_FREE_INPUT_RING_TYPE_L2_CMPL UINT32_C(0x0)
35284 #define HWRM_RING_FREE_INPUT_RING_TYPE_TX UINT32_C(0x1)
35286 #define HWRM_RING_FREE_INPUT_RING_TYPE_RX UINT32_C(0x2)
35287 /* RoCE Notification Completion Ring (ROCE_CR) */
35288 #define HWRM_RING_FREE_INPUT_RING_TYPE_ROCE_CMPL UINT32_C(0x3)
35289 /* RX Aggregation Ring */
35290 #define HWRM_RING_FREE_INPUT_RING_TYPE_RX_AGG UINT32_C(0x4)
35291 /* Notification Queue */
35292 #define HWRM_RING_FREE_INPUT_RING_TYPE_NQ UINT32_C(0x5)
35293 #define HWRM_RING_FREE_INPUT_RING_TYPE_LAST \
35294 HWRM_RING_FREE_INPUT_RING_TYPE_NQ
35297 * If this bit is set to '1', ring_id in this command belongs to
35298 * virtio function. prod_idx in this command corresponds to doorbell
35299 * producer index. opaque field in this command needs to be inserted
35300 * by firmware in VEE_FLUSH completion record.
35301 * Firmware will poll the corresponding ring context to reach the
35302 * given producer index before sending successful response. It will
35303 * finish the completion using VEE_FLUSH completion record.
35305 * If this bit is '0', firmware will not treat ring_id as virtio
35306 * ring and ignore prod_idx, opaque fields.
35308 * This feature is not applicable for L2 or RoCE.
35310 #define HWRM_RING_FREE_INPUT_FLAGS_VIRTIO_RING_VALID UINT32_C(0x1)
35311 #define HWRM_RING_FREE_INPUT_FLAGS_LAST \
35312 HWRM_RING_FREE_INPUT_FLAGS_VIRTIO_RING_VALID
35313 /* Physical number of ring allocated. */
35316 * Ring BD producer index posted by the virtio block.
35317 * This field is valid if virtio_ring_valid flag is set.
35321 * User defined opaque field to be inserted into VEE_FLUSH completion
35322 * record. This field is valid if virtio_ring_valid flag is set.
35328 /* hwrm_ring_free_output (size:128b/16B) */
35329 struct hwrm_ring_free_output {
35330 /* The specific error status for the command. */
35331 uint16_t error_code;
35332 /* The HWRM command request type. */
35334 /* The sequence ID from the original command. */
35336 /* The length of the response data in number of bytes. */
35338 uint8_t unused_0[7];
35340 * This field is used in Output records to indicate that the output
35341 * is completely written to RAM. This field should be read as '1'
35342 * to indicate that the output has been completely written.
35343 * When writing a command completion or response to an internal processor,
35344 * the order of writes has to be such that this field is written last.
35349 /*******************
35350 * hwrm_ring_reset *
35351 *******************/
35354 /* hwrm_ring_reset_input (size:192b/24B) */
35355 struct hwrm_ring_reset_input {
35356 /* The HWRM command request type. */
35359 * The completion ring to send the completion event on. This should
35360 * be the NQ ID returned from the `nq_alloc` HWRM command.
35362 uint16_t cmpl_ring;
35364 * The sequence ID is used by the driver for tracking multiple
35365 * commands. This ID is treated as opaque data by the firmware and
35366 * the value is returned in the `hwrm_resp_hdr` upon completion.
35370 * The target ID of the command:
35371 * * 0x0-0xFFF8 - The function ID
35372 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
35373 * * 0xFFFD - Reserved for user-space HWRM interface
35376 uint16_t target_id;
35378 * A physical address pointer pointing to a host buffer that the
35379 * command's response data will be written. This can be either a host
35380 * physical address (HPA) or a guest physical address (GPA) and must
35381 * point to a physically contiguous block of memory.
35383 uint64_t resp_addr;
35386 /* L2 Completion Ring (CR) */
35387 #define HWRM_RING_RESET_INPUT_RING_TYPE_L2_CMPL UINT32_C(0x0)
35389 #define HWRM_RING_RESET_INPUT_RING_TYPE_TX UINT32_C(0x1)
35391 #define HWRM_RING_RESET_INPUT_RING_TYPE_RX UINT32_C(0x2)
35392 /* RoCE Notification Completion Ring (ROCE_CR) */
35393 #define HWRM_RING_RESET_INPUT_RING_TYPE_ROCE_CMPL UINT32_C(0x3)
35395 * Rx Ring Group. This is to reset rx and aggregation in an atomic
35396 * operation. Completion ring associated with this ring group is
35399 #define HWRM_RING_RESET_INPUT_RING_TYPE_RX_RING_GRP UINT32_C(0x6)
35400 #define HWRM_RING_RESET_INPUT_RING_TYPE_LAST \
35401 HWRM_RING_RESET_INPUT_RING_TYPE_RX_RING_GRP
35404 * Physical number of the ring. When ring type is rx_ring_grp, ring id
35405 * actually refers to ring group id.
35408 uint8_t unused_1[4];
35411 /* hwrm_ring_reset_output (size:128b/16B) */
35412 struct hwrm_ring_reset_output {
35413 /* The specific error status for the command. */
35414 uint16_t error_code;
35415 /* The HWRM command request type. */
35417 /* The sequence ID from the original command. */
35419 /* The length of the response data in number of bytes. */
35422 * This field will tell whether to use ping or pong buffer
35423 * for first push operation.
35425 uint8_t push_buffer_index;
35426 /* Start push from ping buffer index */
35427 #define HWRM_RING_RESET_OUTPUT_PUSH_BUFFER_INDEX_PING_BUFFER \
35429 /* Start push from pong buffer index */
35430 #define HWRM_RING_RESET_OUTPUT_PUSH_BUFFER_INDEX_PONG_BUFFER \
35432 #define HWRM_RING_RESET_OUTPUT_PUSH_BUFFER_INDEX_LAST \
35433 HWRM_RING_RESET_OUTPUT_PUSH_BUFFER_INDEX_PONG_BUFFER
35434 uint8_t unused_0[3];
35435 /* Position of consumer index after ring reset completes. */
35436 uint8_t consumer_idx[3];
35438 * This field is used in Output records to indicate that the output
35439 * is completely written to RAM. This field should be read as '1'
35440 * to indicate that the output has been completely written.
35441 * When writing a command completion or response to an internal processor,
35442 * the order of writes has to be such that this field is written last.
35452 /* hwrm_ring_cfg_input (size:320b/40B) */
35453 struct hwrm_ring_cfg_input {
35454 /* The HWRM command request type. */
35457 * The completion ring to send the completion event on. This should
35458 * be the NQ ID returned from the `nq_alloc` HWRM command.
35460 uint16_t cmpl_ring;
35462 * The sequence ID is used by the driver for tracking multiple
35463 * commands. This ID is treated as opaque data by the firmware and
35464 * the value is returned in the `hwrm_resp_hdr` upon completion.
35468 * The target ID of the command:
35469 * * 0x0-0xFFF8 - The function ID
35470 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
35471 * * 0xFFFD - Reserved for user-space HWRM interface
35474 uint16_t target_id;
35476 * A physical address pointer pointing to a host buffer that the
35477 * command's response data will be written. This can be either a host
35478 * physical address (HPA) or a guest physical address (GPA) and must
35479 * point to a physically contiguous block of memory.
35481 uint64_t resp_addr;
35485 #define HWRM_RING_CFG_INPUT_RING_TYPE_TX UINT32_C(0x1)
35487 #define HWRM_RING_CFG_INPUT_RING_TYPE_RX UINT32_C(0x2)
35488 #define HWRM_RING_CFG_INPUT_RING_TYPE_LAST \
35489 HWRM_RING_CFG_INPUT_RING_TYPE_RX
35491 /* Physical number of the ring. */
35493 /* Ring config enable bits. */
35496 * For Rx rings, the incoming packet data can be placed at either
35497 * a 0B, 2B, 10B or 12B offset from the start of the Rx packet
35499 * When '1', the received packet will be padded with 2B, 10B or 12B
35500 * of zeros at the front of the packet. The exact offset is specified
35501 * by rx_sop_pad_bytes parameter.
35502 * When '0', the received packet will not be padded.
35503 * Note that this flag is only used for Rx rings and is ignored
35504 * for all other rings included Rx Aggregation rings.
35506 #define HWRM_RING_CFG_INPUT_ENABLES_RX_SOP_PAD_ENABLE \
35509 * Proxy mode enable, for Tx, Rx and Rx aggregation rings only.
35510 * When rings are allocated, the PCI function on which driver issues
35511 * HWRM_RING_CFG command is assumed to own the rings. Hardware takes
35512 * the buffer descriptors (BDs) from those rings is assumed to issue
35513 * packet payload DMA using same PCI function. When proxy mode is
35514 * enabled, hardware can perform payload DMA using another PCI
35515 * function on same or different host.
35516 * When set to '0', the PCI function on which driver issues
35517 * HWRM_RING_CFG command is used for host payload DMA operation.
35518 * When set to '1', the host PCI function specified by proxy_fid is
35519 * used for host payload DMA operation.
35521 #define HWRM_RING_CFG_INPUT_ENABLES_PROXY_MODE_ENABLE \
35524 * Tx ring packet source interface override, for Tx rings only.
35525 * When TX rings are allocated, the PCI function on which driver
35526 * issues HWRM_RING_CFG is assumed to be source interface of
35527 * packets sent from TX ring.
35528 * When set to '1', the host PCI function specified by proxy_fid
35529 * is used as source interface of the transmitted packets.
35531 #define HWRM_RING_CFG_INPUT_ENABLES_TX_PROXY_SRC_INTF_OVERRIDE \
35533 /* The schq_id field is valid */
35534 #define HWRM_RING_CFG_INPUT_ENABLES_SCHQ_ID \
35536 /* Update completion ring ID associated with Tx or Rx ring. */
35537 #define HWRM_RING_CFG_INPUT_ENABLES_CMPL_RING_ID_UPDATE \
35540 * When set to '1', metadata value provided by tx_metadata
35541 * field in this command is inserted in the lb_header_metadata
35542 * QP context field. When set to '0', no change done to metadata.
35543 * Firmware rejects the tx ring metadata programming with
35544 * HWRM_ERR_CODE_UNSUPPORTED error if the per function CFA BD
35545 * metadata feature is not disabled.
35547 #define HWRM_RING_CFG_INPUT_ENABLES_TX_METADATA \
35550 * Proxy function FID value.
35551 * This value is only used when either proxy_mode_enable flag or
35552 * tx_proxy_svif_override is set to '1'.
35553 * When proxy_mode_enable is set to '1', it identifies a host PCI
35554 * function used for host payload DMA operations.
35555 * When tx_proxy_src_intf is set to '1', it identifies a host PCI
35556 * function as source interface for all transmitted packets from
35559 uint16_t proxy_fid;
35561 * Identifies the new scheduler queue (SCHQ) to associate with the
35562 * ring. Only valid for Tx rings.
35563 * A value of zero indicates that the Tx ring should be associated
35564 * with the default scheduler queue (SCHQ).
35568 * This field is valid for TX or Rx rings. This value identifies the
35569 * new completion ring ID to associate with the TX or Rx ring.
35571 uint16_t cmpl_ring_id;
35573 * Rx SOP padding amount in bytes.
35574 * This value is only used when rx_sop_pad_enable flag is set to '1'.
35576 uint8_t rx_sop_pad_bytes;
35577 uint8_t unused_1[3];
35579 * When tx_metadata enable bit is set, value specified in this field
35580 * is copied to lb_header_metadata in the QP context.
35582 uint32_t tx_metadata;
35583 uint8_t unused_2[4];
35586 /* hwrm_ring_cfg_output (size:128b/16B) */
35587 struct hwrm_ring_cfg_output {
35588 /* The specific error status for the command. */
35589 uint16_t error_code;
35590 /* The HWRM command request type. */
35592 /* The sequence ID from the original command. */
35594 /* The length of the response data in number of bytes. */
35596 uint8_t unused_0[7];
35598 * This field is used in Output records to indicate that the output
35599 * is completely written to RAM. This field should be read as '1'
35600 * to indicate that the output has been completely written.
35601 * When writing a command completion or response to an internal
35602 * processor, the order of writes has to be such that this field is
35608 /******************
35610 ******************/
35613 /* hwrm_ring_qcfg_input (size:192b/24B) */
35614 struct hwrm_ring_qcfg_input {
35615 /* The HWRM command request type. */
35618 * The completion ring to send the completion event on. This should
35619 * be the NQ ID returned from the `nq_alloc` HWRM command.
35621 uint16_t cmpl_ring;
35623 * The sequence ID is used by the driver for tracking multiple
35624 * commands. This ID is treated as opaque data by the firmware and
35625 * the value is returned in the `hwrm_resp_hdr` upon completion.
35629 * The target ID of the command:
35630 * * 0x0-0xFFF8 - The function ID
35631 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
35632 * * 0xFFFD - Reserved for user-space HWRM interface
35635 uint16_t target_id;
35637 * A physical address pointer pointing to a host buffer that the
35638 * command's response data will be written. This can be either a host
35639 * physical address (HPA) or a guest physical address (GPA) and must
35640 * point to a physically contiguous block of memory.
35642 uint64_t resp_addr;
35646 #define HWRM_RING_QCFG_INPUT_RING_TYPE_TX UINT32_C(0x1)
35648 #define HWRM_RING_QCFG_INPUT_RING_TYPE_RX UINT32_C(0x2)
35649 #define HWRM_RING_QCFG_INPUT_RING_TYPE_LAST \
35650 HWRM_RING_QCFG_INPUT_RING_TYPE_RX
35651 uint8_t unused_0[5];
35652 /* Physical number of the ring. */
35656 /* hwrm_ring_qcfg_output (size:256b/32B) */
35657 struct hwrm_ring_qcfg_output {
35658 /* The specific error status for the command. */
35659 uint16_t error_code;
35660 /* The HWRM command request type. */
35662 /* The sequence ID from the original command. */
35664 /* The length of the response data in number of bytes. */
35666 /* Ring config enable bits. */
35669 * For Rx rings, the incoming packet data can be placed at either
35670 * a 0B, 2B, 10B or 12B offset from the start of the Rx packet
35672 * When '1', the received packet will be padded with 2B, 10B or 12B
35673 * of zeros at the front of the packet. The exact offset is specified
35674 * by rx_sop_pad_bytes parameter.
35675 * When '0', the received packet will not be padded.
35676 * Note that this flag is only used for Rx rings and is ignored
35677 * for all other rings included Rx Aggregation rings.
35679 #define HWRM_RING_QCFG_OUTPUT_ENABLES_RX_SOP_PAD_ENABLE \
35682 * Proxy mode enable, for Tx, Rx and Rx aggregation rings only.
35683 * When rings are allocated, the PCI function on which driver issues
35684 * HWRM_RING_CFG command is assumed to own the rings. Hardware takes
35685 * the buffer descriptors (BDs) from those rings is assumed to issue
35686 * packet payload DMA using same PCI function. When proxy mode is
35687 * enabled, hardware can perform payload DMA using another PCI
35688 * function on same or different host.
35689 * When set to '0', the PCI function on which driver issues
35690 * HWRM_RING_CFG command is used for host payload DMA operation.
35691 * When set to '1', the host PCI function specified by proxy_fid is
35692 * used for host payload DMA operation.
35694 #define HWRM_RING_QCFG_OUTPUT_ENABLES_PROXY_MODE_ENABLE \
35697 * Tx ring packet source interface override, for Tx rings only.
35698 * When TX rings are allocated, the PCI function on which driver
35699 * issues HWRM_RING_CFG is assumed to be source interface of
35700 * packets sent from TX ring.
35701 * When set to '1', the host PCI function specified by proxy_fid is
35702 * used as source interface of the transmitted packets.
35704 #define HWRM_RING_QCFG_OUTPUT_ENABLES_TX_PROXY_SRC_INTF_OVERRIDE \
35707 * Proxy function FID value.
35708 * This value is only used when either proxy_mode_enable flag or
35709 * tx_proxy_svif_override is set to '1'.
35710 * When proxy_mode_enable is set to '1', it identifies a host PCI
35711 * function used for host payload DMA operations.
35712 * When tx_proxy_src_intf is set to '1', it identifies a host PCI
35713 * function as source interface for all transmitted packets from the TX
35716 uint16_t proxy_fid;
35718 * Identifies the new scheduler queue (SCHQ) to associate with the
35719 * ring. Only valid for Tx rings.
35720 * A value of zero indicates that the Tx ring should be associated with
35721 * the default scheduler queue (SCHQ).
35725 * This field is used when ring_type is a TX or Rx ring.
35726 * This value indicates what completion ring the TX or Rx ring
35727 * is associated with.
35729 uint16_t cmpl_ring_id;
35731 * Rx SOP padding amount in bytes.
35732 * This value is only used when rx_sop_pad_enable flag is set to '1'.
35734 uint8_t rx_sop_pad_bytes;
35735 uint8_t unused_0[3];
35736 /* lb_header_metadata in the QP context is copied to this field. */
35737 uint32_t tx_metadata;
35738 uint8_t unused_1[7];
35740 * This field is used in Output records to indicate that the output
35741 * is completely written to RAM. This field should be read as '1'
35742 * to indicate that the output has been completely written.
35743 * When writing a command completion or response to an internal
35744 * processor, the order of writes has to be such that this field is
35750 /**************************
35751 * hwrm_ring_aggint_qcaps *
35752 **************************/
35755 /* hwrm_ring_aggint_qcaps_input (size:128b/16B) */
35756 struct hwrm_ring_aggint_qcaps_input {
35757 /* The HWRM command request type. */
35760 * The completion ring to send the completion event on. This should
35761 * be the NQ ID returned from the `nq_alloc` HWRM command.
35763 uint16_t cmpl_ring;
35765 * The sequence ID is used by the driver for tracking multiple
35766 * commands. This ID is treated as opaque data by the firmware and
35767 * the value is returned in the `hwrm_resp_hdr` upon completion.
35771 * The target ID of the command:
35772 * * 0x0-0xFFF8 - The function ID
35773 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
35774 * * 0xFFFD - Reserved for user-space HWRM interface
35777 uint16_t target_id;
35779 * A physical address pointer pointing to a host buffer that the
35780 * command's response data will be written. This can be either a host
35781 * physical address (HPA) or a guest physical address (GPA) and must
35782 * point to a physically contiguous block of memory.
35784 uint64_t resp_addr;
35787 /* hwrm_ring_aggint_qcaps_output (size:384b/48B) */
35788 struct hwrm_ring_aggint_qcaps_output {
35789 /* The specific error status for the command. */
35790 uint16_t error_code;
35791 /* The HWRM command request type. */
35793 /* The sequence ID from the original command. */
35795 /* The length of the response data in number of bytes. */
35797 uint32_t cmpl_params;
35799 * When this bit is set to '1', int_lat_tmr_min can be configured
35800 * on completion rings.
35802 #define HWRM_RING_AGGINT_QCAPS_OUTPUT_CMPL_PARAMS_INT_LAT_TMR_MIN \
35805 * When this bit is set to '1', int_lat_tmr_max can be configured
35806 * on completion rings.
35808 #define HWRM_RING_AGGINT_QCAPS_OUTPUT_CMPL_PARAMS_INT_LAT_TMR_MAX \
35811 * When this bit is set to '1', timer_reset can be enabled
35812 * on completion rings.
35814 #define HWRM_RING_AGGINT_QCAPS_OUTPUT_CMPL_PARAMS_TIMER_RESET \
35817 * When this bit is set to '1', ring_idle can be enabled
35818 * on completion rings.
35820 #define HWRM_RING_AGGINT_QCAPS_OUTPUT_CMPL_PARAMS_RING_IDLE \
35823 * When this bit is set to '1', num_cmpl_dma_aggr can be configured
35824 * on completion rings.
35826 #define HWRM_RING_AGGINT_QCAPS_OUTPUT_CMPL_PARAMS_NUM_CMPL_DMA_AGGR \
35829 * When this bit is set to '1', num_cmpl_dma_aggr_during_int can be configured
35830 * on completion rings.
35832 #define HWRM_RING_AGGINT_QCAPS_OUTPUT_CMPL_PARAMS_NUM_CMPL_DMA_AGGR_DURING_INT \
35835 * When this bit is set to '1', cmpl_aggr_dma_tmr can be configured
35836 * on completion rings.
35838 #define HWRM_RING_AGGINT_QCAPS_OUTPUT_CMPL_PARAMS_CMPL_AGGR_DMA_TMR \
35841 * When this bit is set to '1', cmpl_aggr_dma_tmr_during_int can be configured
35842 * on completion rings.
35844 #define HWRM_RING_AGGINT_QCAPS_OUTPUT_CMPL_PARAMS_CMPL_AGGR_DMA_TMR_DURING_INT \
35847 * When this bit is set to '1', num_cmpl_aggr_int can be configured
35848 * on completion rings.
35850 #define HWRM_RING_AGGINT_QCAPS_OUTPUT_CMPL_PARAMS_NUM_CMPL_AGGR_INT \
35852 uint32_t nq_params;
35854 * When this bit is set to '1', int_lat_tmr_min can be configured
35855 * on notification queues.
35857 #define HWRM_RING_AGGINT_QCAPS_OUTPUT_NQ_PARAMS_INT_LAT_TMR_MIN \
35859 /* Minimum value for num_cmpl_dma_aggr */
35860 uint16_t num_cmpl_dma_aggr_min;
35861 /* Maximum value for num_cmpl_dma_aggr */
35862 uint16_t num_cmpl_dma_aggr_max;
35863 /* Minimum value for num_cmpl_dma_aggr_during_int */
35864 uint16_t num_cmpl_dma_aggr_during_int_min;
35865 /* Maximum value for num_cmpl_dma_aggr_during_int */
35866 uint16_t num_cmpl_dma_aggr_during_int_max;
35867 /* Minimum value for cmpl_aggr_dma_tmr */
35868 uint16_t cmpl_aggr_dma_tmr_min;
35869 /* Maximum value for cmpl_aggr_dma_tmr */
35870 uint16_t cmpl_aggr_dma_tmr_max;
35871 /* Minimum value for cmpl_aggr_dma_tmr_during_int */
35872 uint16_t cmpl_aggr_dma_tmr_during_int_min;
35873 /* Maximum value for cmpl_aggr_dma_tmr_during_int */
35874 uint16_t cmpl_aggr_dma_tmr_during_int_max;
35875 /* Minimum value for int_lat_tmr_min */
35876 uint16_t int_lat_tmr_min_min;
35877 /* Maximum value for int_lat_tmr_min */
35878 uint16_t int_lat_tmr_min_max;
35879 /* Minimum value for int_lat_tmr_max */
35880 uint16_t int_lat_tmr_max_min;
35881 /* Maximum value for int_lat_tmr_max */
35882 uint16_t int_lat_tmr_max_max;
35883 /* Minimum value for num_cmpl_aggr_int */
35884 uint16_t num_cmpl_aggr_int_min;
35885 /* Maximum value for num_cmpl_aggr_int */
35886 uint16_t num_cmpl_aggr_int_max;
35887 /* The units for timer parameters, in nanoseconds. */
35888 uint16_t timer_units;
35889 uint8_t unused_0[1];
35891 * This field is used in Output records to indicate that the output
35892 * is completely written to RAM. This field should be read as '1'
35893 * to indicate that the output has been completely written.
35894 * When writing a command completion or response to an internal processor,
35895 * the order of writes has to be such that this field is written last.
35900 /**************************************
35901 * hwrm_ring_cmpl_ring_qaggint_params *
35902 **************************************/
35905 /* hwrm_ring_cmpl_ring_qaggint_params_input (size:192b/24B) */
35906 struct hwrm_ring_cmpl_ring_qaggint_params_input {
35907 /* The HWRM command request type. */
35910 * The completion ring to send the completion event on. This should
35911 * be the NQ ID returned from the `nq_alloc` HWRM command.
35913 uint16_t cmpl_ring;
35915 * The sequence ID is used by the driver for tracking multiple
35916 * commands. This ID is treated as opaque data by the firmware and
35917 * the value is returned in the `hwrm_resp_hdr` upon completion.
35921 * The target ID of the command:
35922 * * 0x0-0xFFF8 - The function ID
35923 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
35924 * * 0xFFFD - Reserved for user-space HWRM interface
35927 uint16_t target_id;
35929 * A physical address pointer pointing to a host buffer that the
35930 * command's response data will be written. This can be either a host
35931 * physical address (HPA) or a guest physical address (GPA) and must
35932 * point to a physically contiguous block of memory.
35934 uint64_t resp_addr;
35935 /* Physical number of completion ring. */
35938 #define HWRM_RING_CMPL_RING_QAGGINT_PARAMS_INPUT_FLAGS_UNUSED_0_MASK \
35940 #define HWRM_RING_CMPL_RING_QAGGINT_PARAMS_INPUT_FLAGS_UNUSED_0_SFT 0
35942 * Set this flag to 1 when querying parameters on a notification
35943 * queue. Set this flag to 0 when querying parameters on a
35944 * completion queue or completion ring.
35946 #define HWRM_RING_CMPL_RING_QAGGINT_PARAMS_INPUT_FLAGS_IS_NQ \
35948 uint8_t unused_0[4];
35951 /* hwrm_ring_cmpl_ring_qaggint_params_output (size:256b/32B) */
35952 struct hwrm_ring_cmpl_ring_qaggint_params_output {
35953 /* The specific error status for the command. */
35954 uint16_t error_code;
35955 /* The HWRM command request type. */
35957 /* The sequence ID from the original command. */
35959 /* The length of the response data in number of bytes. */
35963 * When this bit is set to '1', interrupt max
35964 * timer is reset whenever a completion is received.
35966 #define HWRM_RING_CMPL_RING_QAGGINT_PARAMS_OUTPUT_FLAGS_TIMER_RESET \
35969 * When this bit is set to '1', ring idle mode
35970 * aggregation will be enabled.
35972 #define HWRM_RING_CMPL_RING_QAGGINT_PARAMS_OUTPUT_FLAGS_RING_IDLE \
35975 * Number of completions to aggregate before DMA
35976 * during the normal mode.
35978 uint16_t num_cmpl_dma_aggr;
35980 * Number of completions to aggregate before DMA
35981 * during the interrupt mode.
35983 uint16_t num_cmpl_dma_aggr_during_int;
35985 * Timer used to aggregate completions before
35986 * DMA during the normal mode (not in interrupt mode).
35988 uint16_t cmpl_aggr_dma_tmr;
35990 * Timer used to aggregate completions before
35991 * DMA when in interrupt mode.
35993 uint16_t cmpl_aggr_dma_tmr_during_int;
35994 /* Minimum time between two interrupts. */
35995 uint16_t int_lat_tmr_min;
35997 * Maximum wait time spent aggregating
35998 * completions before signaling the interrupt after the
35999 * interrupt is enabled.
36001 uint16_t int_lat_tmr_max;
36003 * Minimum number of completions aggregated before signaling
36006 uint16_t num_cmpl_aggr_int;
36007 uint8_t unused_0[7];
36009 * This field is used in Output records to indicate that the output
36010 * is completely written to RAM. This field should be read as '1'
36011 * to indicate that the output has been completely written.
36012 * When writing a command completion or response to an internal processor,
36013 * the order of writes has to be such that this field is written last.
36018 /*****************************************
36019 * hwrm_ring_cmpl_ring_cfg_aggint_params *
36020 *****************************************/
36023 /* hwrm_ring_cmpl_ring_cfg_aggint_params_input (size:320b/40B) */
36024 struct hwrm_ring_cmpl_ring_cfg_aggint_params_input {
36025 /* The HWRM command request type. */
36028 * The completion ring to send the completion event on. This should
36029 * be the NQ ID returned from the `nq_alloc` HWRM command.
36031 uint16_t cmpl_ring;
36033 * The sequence ID is used by the driver for tracking multiple
36034 * commands. This ID is treated as opaque data by the firmware and
36035 * the value is returned in the `hwrm_resp_hdr` upon completion.
36039 * The target ID of the command:
36040 * * 0x0-0xFFF8 - The function ID
36041 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
36042 * * 0xFFFD - Reserved for user-space HWRM interface
36045 uint16_t target_id;
36047 * A physical address pointer pointing to a host buffer that the
36048 * command's response data will be written. This can be either a host
36049 * physical address (HPA) or a guest physical address (GPA) and must
36050 * point to a physically contiguous block of memory.
36052 uint64_t resp_addr;
36053 /* Physical number of completion ring. */
36057 * When this bit is set to '1', interrupt latency max
36058 * timer is reset whenever a completion is received.
36060 #define HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_FLAGS_TIMER_RESET \
36063 * When this bit is set to '1', ring idle mode
36064 * aggregation will be enabled.
36066 #define HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_FLAGS_RING_IDLE \
36069 * Set this flag to 1 when configuring parameters on a
36070 * notification queue. Set this flag to 0 when configuring
36071 * parameters on a completion queue or completion ring.
36073 #define HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_FLAGS_IS_NQ \
36076 * Number of completions to aggregate before DMA
36077 * during the normal mode.
36079 uint16_t num_cmpl_dma_aggr;
36081 * Number of completions to aggregate before DMA
36082 * during the interrupt mode.
36084 uint16_t num_cmpl_dma_aggr_during_int;
36086 * Timer used to aggregate completions before
36087 * DMA during the normal mode (not in interrupt mode).
36089 uint16_t cmpl_aggr_dma_tmr;
36091 * Timer used to aggregate completions before
36092 * DMA while in interrupt mode.
36094 uint16_t cmpl_aggr_dma_tmr_during_int;
36095 /* Minimum time between two interrupts. */
36096 uint16_t int_lat_tmr_min;
36098 * Maximum wait time spent aggregating
36099 * completions before signaling the interrupt after the
36100 * interrupt is enabled.
36102 uint16_t int_lat_tmr_max;
36104 * Minimum number of completions aggregated before signaling
36107 uint16_t num_cmpl_aggr_int;
36109 * Bitfield that indicates which parameters are to be applied. Only
36110 * required when configuring devices with notification queues, and
36111 * used in that case to set certain parameters on completion queues
36112 * and others on notification queues.
36116 * This bit must be '1' for the num_cmpl_dma_aggr field to be
36119 #define HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_ENABLES_NUM_CMPL_DMA_AGGR \
36122 * This bit must be '1' for the num_cmpl_dma_aggr_during_int field to be
36125 #define HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_ENABLES_NUM_CMPL_DMA_AGGR_DURING_INT \
36128 * This bit must be '1' for the cmpl_aggr_dma_tmr field to be
36131 #define HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_ENABLES_CMPL_AGGR_DMA_TMR \
36134 * This bit must be '1' for the int_lat_tmr_min field to be
36137 #define HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_ENABLES_INT_LAT_TMR_MIN \
36140 * This bit must be '1' for the int_lat_tmr_max field to be
36143 #define HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_ENABLES_INT_LAT_TMR_MAX \
36146 * This bit must be '1' for the num_cmpl_aggr_int field to be
36149 #define HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_ENABLES_NUM_CMPL_AGGR_INT \
36151 uint8_t unused_0[4];
36154 /* hwrm_ring_cmpl_ring_cfg_aggint_params_output (size:128b/16B) */
36155 struct hwrm_ring_cmpl_ring_cfg_aggint_params_output {
36156 /* The specific error status for the command. */
36157 uint16_t error_code;
36158 /* The HWRM command request type. */
36160 /* The sequence ID from the original command. */
36162 /* The length of the response data in number of bytes. */
36164 uint8_t unused_0[7];
36166 * This field is used in Output records to indicate that the output
36167 * is completely written to RAM. This field should be read as '1'
36168 * to indicate that the output has been completely written.
36169 * When writing a command completion or response to an internal processor,
36170 * the order of writes has to be such that this field is written last.
36175 /***********************
36176 * hwrm_ring_grp_alloc *
36177 ***********************/
36180 /* hwrm_ring_grp_alloc_input (size:192b/24B) */
36181 struct hwrm_ring_grp_alloc_input {
36182 /* The HWRM command request type. */
36185 * The completion ring to send the completion event on. This should
36186 * be the NQ ID returned from the `nq_alloc` HWRM command.
36188 uint16_t cmpl_ring;
36190 * The sequence ID is used by the driver for tracking multiple
36191 * commands. This ID is treated as opaque data by the firmware and
36192 * the value is returned in the `hwrm_resp_hdr` upon completion.
36196 * The target ID of the command:
36197 * * 0x0-0xFFF8 - The function ID
36198 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
36199 * * 0xFFFD - Reserved for user-space HWRM interface
36202 uint16_t target_id;
36204 * A physical address pointer pointing to a host buffer that the
36205 * command's response data will be written. This can be either a host
36206 * physical address (HPA) or a guest physical address (GPA) and must
36207 * point to a physically contiguous block of memory.
36209 uint64_t resp_addr;
36211 * This value identifies the CR associated with the ring
36216 * This value identifies the main RR associated with the ring
36221 * This value identifies the aggregation RR associated with
36222 * the ring group. If this value is 0xFF... (All Fs), then no
36223 * Aggregation ring will be set.
36227 * This value identifies the statistics context associated
36228 * with the ring group.
36233 /* hwrm_ring_grp_alloc_output (size:128b/16B) */
36234 struct hwrm_ring_grp_alloc_output {
36235 /* The specific error status for the command. */
36236 uint16_t error_code;
36237 /* The HWRM command request type. */
36239 /* The sequence ID from the original command. */
36241 /* The length of the response data in number of bytes. */
36244 * This is the ring group ID value. Use this value to program
36245 * the default ring group for the VNIC or as table entries
36246 * in an RSS/COS context.
36248 uint32_t ring_group_id;
36249 uint8_t unused_0[3];
36251 * This field is used in Output records to indicate that the output
36252 * is completely written to RAM. This field should be read as '1'
36253 * to indicate that the output has been completely written.
36254 * When writing a command completion or response to an internal processor,
36255 * the order of writes has to be such that this field is written last.
36260 /**********************
36261 * hwrm_ring_grp_free *
36262 **********************/
36265 /* hwrm_ring_grp_free_input (size:192b/24B) */
36266 struct hwrm_ring_grp_free_input {
36267 /* The HWRM command request type. */
36270 * The completion ring to send the completion event on. This should
36271 * be the NQ ID returned from the `nq_alloc` HWRM command.
36273 uint16_t cmpl_ring;
36275 * The sequence ID is used by the driver for tracking multiple
36276 * commands. This ID is treated as opaque data by the firmware and
36277 * the value is returned in the `hwrm_resp_hdr` upon completion.
36281 * The target ID of the command:
36282 * * 0x0-0xFFF8 - The function ID
36283 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
36284 * * 0xFFFD - Reserved for user-space HWRM interface
36287 uint16_t target_id;
36289 * A physical address pointer pointing to a host buffer that the
36290 * command's response data will be written. This can be either a host
36291 * physical address (HPA) or a guest physical address (GPA) and must
36292 * point to a physically contiguous block of memory.
36294 uint64_t resp_addr;
36295 /* This is the ring group ID value. */
36296 uint32_t ring_group_id;
36297 uint8_t unused_0[4];
36300 /* hwrm_ring_grp_free_output (size:128b/16B) */
36301 struct hwrm_ring_grp_free_output {
36302 /* The specific error status for the command. */
36303 uint16_t error_code;
36304 /* The HWRM command request type. */
36306 /* The sequence ID from the original command. */
36308 /* The length of the response data in number of bytes. */
36310 uint8_t unused_0[7];
36312 * This field is used in Output records to indicate that the output
36313 * is completely written to RAM. This field should be read as '1'
36314 * to indicate that the output has been completely written.
36315 * When writing a command completion or response to an internal processor,
36316 * the order of writes has to be such that this field is written last.
36321 /************************
36322 * hwrm_ring_schq_alloc *
36323 ************************/
36326 /* hwrm_ring_schq_alloc_input (size:1088b/136B) */
36327 struct hwrm_ring_schq_alloc_input {
36328 /* The HWRM command request type. */
36331 * The completion ring to send the completion event on. This should
36332 * be the NQ ID returned from the `nq_alloc` HWRM command.
36334 uint16_t cmpl_ring;
36336 * The sequence ID is used by the driver for tracking multiple
36337 * commands. This ID is treated as opaque data by the firmware and
36338 * the value is returned in the `hwrm_resp_hdr` upon completion.
36342 * The target ID of the command:
36343 * * 0x0-0xFFF8 - The function ID
36344 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
36345 * * 0xFFFD - Reserved for user-space HWRM interface
36348 uint16_t target_id;
36350 * A physical address pointer pointing to a host buffer that the
36351 * command's response data will be written. This can be either a host
36352 * physical address (HPA) or a guest physical address (GPA) and must
36353 * point to a physically contiguous block of memory.
36355 uint64_t resp_addr;
36358 * This bit must be '1' for the tqm_ring0 fields to be
36361 #define HWRM_RING_SCHQ_ALLOC_INPUT_ENABLES_TQM_RING0 UINT32_C(0x1)
36363 * This bit must be '1' for the tqm_ring1 fields to be
36366 #define HWRM_RING_SCHQ_ALLOC_INPUT_ENABLES_TQM_RING1 UINT32_C(0x2)
36368 * This bit must be '1' for the tqm_ring2 fields to be
36371 #define HWRM_RING_SCHQ_ALLOC_INPUT_ENABLES_TQM_RING2 UINT32_C(0x4)
36373 * This bit must be '1' for the tqm_ring3 fields to be
36376 #define HWRM_RING_SCHQ_ALLOC_INPUT_ENABLES_TQM_RING3 UINT32_C(0x8)
36378 * This bit must be '1' for the tqm_ring4 fields to be
36381 #define HWRM_RING_SCHQ_ALLOC_INPUT_ENABLES_TQM_RING4 UINT32_C(0x10)
36383 * This bit must be '1' for the tqm_ring5 fields to be
36386 #define HWRM_RING_SCHQ_ALLOC_INPUT_ENABLES_TQM_RING5 UINT32_C(0x20)
36388 * This bit must be '1' for the tqm_ring6 fields to be
36391 #define HWRM_RING_SCHQ_ALLOC_INPUT_ENABLES_TQM_RING6 UINT32_C(0x40)
36393 * This bit must be '1' for the tqm_ring7 fields to be
36396 #define HWRM_RING_SCHQ_ALLOC_INPUT_ENABLES_TQM_RING7 UINT32_C(0x80)
36397 /* Reserved for future use. */
36399 /* TQM ring 0 page size and level. */
36400 uint8_t tqm_ring0_pg_size_tqm_ring0_lvl;
36401 /* TQM ring 0 PBL indirect levels. */
36402 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING0_LVL_MASK \
36404 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING0_LVL_SFT 0
36405 /* PBL pointer is physical start address. */
36406 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING0_LVL_LVL_0 \
36408 /* PBL pointer points to PTE table. */
36409 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING0_LVL_LVL_1 \
36412 * PBL pointer points to PDE table with each entry pointing to PTE
36415 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING0_LVL_LVL_2 \
36417 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING0_LVL_LAST \
36418 HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING0_LVL_LVL_2
36419 /* TQM ring 0 page size. */
36420 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING0_PG_SIZE_MASK \
36422 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING0_PG_SIZE_SFT 4
36424 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING0_PG_SIZE_PG_4K \
36425 (UINT32_C(0x0) << 4)
36427 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING0_PG_SIZE_PG_8K \
36428 (UINT32_C(0x1) << 4)
36430 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING0_PG_SIZE_PG_64K \
36431 (UINT32_C(0x2) << 4)
36433 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING0_PG_SIZE_PG_2M \
36434 (UINT32_C(0x3) << 4)
36436 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING0_PG_SIZE_PG_8M \
36437 (UINT32_C(0x4) << 4)
36439 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING0_PG_SIZE_PG_1G \
36440 (UINT32_C(0x5) << 4)
36441 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING0_PG_SIZE_LAST \
36442 HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING0_PG_SIZE_PG_1G
36443 /* TQM ring 1 page size and level. */
36444 uint8_t tqm_ring1_pg_size_tqm_ring1_lvl;
36445 /* TQM ring 1 PBL indirect levels. */
36446 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING1_LVL_MASK \
36448 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING1_LVL_SFT 0
36449 /* PBL pointer is physical start address. */
36450 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING1_LVL_LVL_0 \
36452 /* PBL pointer points to PTE table. */
36453 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING1_LVL_LVL_1 \
36456 * PBL pointer points to PDE table with each entry pointing to PTE
36459 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING1_LVL_LVL_2 \
36461 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING1_LVL_LAST \
36462 HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING1_LVL_LVL_2
36463 /* TQM ring 1 page size. */
36464 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING1_PG_SIZE_MASK \
36466 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING1_PG_SIZE_SFT 4
36468 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING1_PG_SIZE_PG_4K \
36469 (UINT32_C(0x0) << 4)
36471 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING1_PG_SIZE_PG_8K \
36472 (UINT32_C(0x1) << 4)
36474 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING1_PG_SIZE_PG_64K \
36475 (UINT32_C(0x2) << 4)
36477 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING1_PG_SIZE_PG_2M \
36478 (UINT32_C(0x3) << 4)
36480 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING1_PG_SIZE_PG_8M \
36481 (UINT32_C(0x4) << 4)
36483 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING1_PG_SIZE_PG_1G \
36484 (UINT32_C(0x5) << 4)
36485 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING1_PG_SIZE_LAST \
36486 HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING1_PG_SIZE_PG_1G
36487 /* TQM ring 2 page size and level. */
36488 uint8_t tqm_ring2_pg_size_tqm_ring2_lvl;
36489 /* TQM ring 2 PBL indirect levels. */
36490 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING2_LVL_MASK \
36492 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING2_LVL_SFT 0
36493 /* PBL pointer is physical start address. */
36494 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING2_LVL_LVL_0 \
36496 /* PBL pointer points to PTE table. */
36497 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING2_LVL_LVL_1 \
36500 * PBL pointer points to PDE table with each entry pointing to PTE
36503 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING2_LVL_LVL_2 \
36505 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING2_LVL_LAST \
36506 HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING2_LVL_LVL_2
36507 /* TQM ring 2 page size. */
36508 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING2_PG_SIZE_MASK \
36510 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING2_PG_SIZE_SFT 4
36512 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING2_PG_SIZE_PG_4K \
36513 (UINT32_C(0x0) << 4)
36515 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING2_PG_SIZE_PG_8K \
36516 (UINT32_C(0x1) << 4)
36518 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING2_PG_SIZE_PG_64K \
36519 (UINT32_C(0x2) << 4)
36521 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING2_PG_SIZE_PG_2M \
36522 (UINT32_C(0x3) << 4)
36524 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING2_PG_SIZE_PG_8M \
36525 (UINT32_C(0x4) << 4)
36527 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING2_PG_SIZE_PG_1G \
36528 (UINT32_C(0x5) << 4)
36529 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING2_PG_SIZE_LAST \
36530 HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING2_PG_SIZE_PG_1G
36531 /* TQM ring 3 page size and level. */
36532 uint8_t tqm_ring3_pg_size_tqm_ring3_lvl;
36533 /* TQM ring 3 PBL indirect levels. */
36534 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING3_LVL_MASK \
36536 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING3_LVL_SFT 0
36537 /* PBL pointer is physical start address. */
36538 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING3_LVL_LVL_0 \
36540 /* PBL pointer points to PTE table. */
36541 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING3_LVL_LVL_1 \
36544 * PBL pointer points to PDE table with each entry pointing to PTE
36547 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING3_LVL_LVL_2 \
36549 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING3_LVL_LAST \
36550 HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING3_LVL_LVL_2
36551 /* TQM ring 3 page size. */
36552 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING3_PG_SIZE_MASK \
36554 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING3_PG_SIZE_SFT 4
36556 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING3_PG_SIZE_PG_4K \
36557 (UINT32_C(0x0) << 4)
36559 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING3_PG_SIZE_PG_8K \
36560 (UINT32_C(0x1) << 4)
36562 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING3_PG_SIZE_PG_64K \
36563 (UINT32_C(0x2) << 4)
36565 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING3_PG_SIZE_PG_2M \
36566 (UINT32_C(0x3) << 4)
36568 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING3_PG_SIZE_PG_8M \
36569 (UINT32_C(0x4) << 4)
36571 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING3_PG_SIZE_PG_1G \
36572 (UINT32_C(0x5) << 4)
36573 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING3_PG_SIZE_LAST \
36574 HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING3_PG_SIZE_PG_1G
36575 /* TQM ring 4 page size and level. */
36576 uint8_t tqm_ring4_pg_size_tqm_ring4_lvl;
36577 /* TQM ring 4 PBL indirect levels. */
36578 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING4_LVL_MASK \
36580 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING4_LVL_SFT 0
36581 /* PBL pointer is physical start address. */
36582 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING4_LVL_LVL_0 \
36584 /* PBL pointer points to PTE table. */
36585 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING4_LVL_LVL_1 \
36588 * PBL pointer points to PDE table with each entry pointing to PTE
36591 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING4_LVL_LVL_2 \
36593 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING4_LVL_LAST \
36594 HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING4_LVL_LVL_2
36595 /* TQM ring 4 page size. */
36596 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING4_PG_SIZE_MASK \
36598 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING4_PG_SIZE_SFT 4
36600 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING4_PG_SIZE_PG_4K \
36601 (UINT32_C(0x0) << 4)
36603 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING4_PG_SIZE_PG_8K \
36604 (UINT32_C(0x1) << 4)
36606 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING4_PG_SIZE_PG_64K \
36607 (UINT32_C(0x2) << 4)
36609 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING4_PG_SIZE_PG_2M \
36610 (UINT32_C(0x3) << 4)
36612 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING4_PG_SIZE_PG_8M \
36613 (UINT32_C(0x4) << 4)
36615 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING4_PG_SIZE_PG_1G \
36616 (UINT32_C(0x5) << 4)
36617 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING4_PG_SIZE_LAST \
36618 HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING4_PG_SIZE_PG_1G
36619 /* TQM ring 5 page size and level. */
36620 uint8_t tqm_ring5_pg_size_tqm_ring5_lvl;
36621 /* TQM ring 5 PBL indirect levels. */
36622 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING5_LVL_MASK \
36624 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING5_LVL_SFT 0
36625 /* PBL pointer is physical start address. */
36626 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING5_LVL_LVL_0 \
36628 /* PBL pointer points to PTE table. */
36629 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING5_LVL_LVL_1 \
36632 * PBL pointer points to PDE table with each entry pointing to PTE
36635 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING5_LVL_LVL_2 \
36637 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING5_LVL_LAST \
36638 HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING5_LVL_LVL_2
36639 /* TQM ring 5 page size. */
36640 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING5_PG_SIZE_MASK \
36642 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING5_PG_SIZE_SFT 4
36644 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING5_PG_SIZE_PG_4K \
36645 (UINT32_C(0x0) << 4)
36647 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING5_PG_SIZE_PG_8K \
36648 (UINT32_C(0x1) << 4)
36650 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING5_PG_SIZE_PG_64K \
36651 (UINT32_C(0x2) << 4)
36653 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING5_PG_SIZE_PG_2M \
36654 (UINT32_C(0x3) << 4)
36656 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING5_PG_SIZE_PG_8M \
36657 (UINT32_C(0x4) << 4)
36659 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING5_PG_SIZE_PG_1G \
36660 (UINT32_C(0x5) << 4)
36661 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING5_PG_SIZE_LAST \
36662 HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING5_PG_SIZE_PG_1G
36663 /* TQM ring 6 page size and level. */
36664 uint8_t tqm_ring6_pg_size_tqm_ring6_lvl;
36665 /* TQM ring 6 PBL indirect levels. */
36666 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING6_LVL_MASK \
36668 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING6_LVL_SFT 0
36669 /* PBL pointer is physical start address. */
36670 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING6_LVL_LVL_0 \
36672 /* PBL pointer points to PTE table. */
36673 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING6_LVL_LVL_1 \
36676 * PBL pointer points to PDE table with each entry pointing to PTE
36679 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING6_LVL_LVL_2 \
36681 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING6_LVL_LAST \
36682 HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING6_LVL_LVL_2
36683 /* TQM ring 6 page size. */
36684 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING6_PG_SIZE_MASK \
36686 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING6_PG_SIZE_SFT 4
36688 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING6_PG_SIZE_PG_4K \
36689 (UINT32_C(0x0) << 4)
36691 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING6_PG_SIZE_PG_8K \
36692 (UINT32_C(0x1) << 4)
36694 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING6_PG_SIZE_PG_64K \
36695 (UINT32_C(0x2) << 4)
36697 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING6_PG_SIZE_PG_2M \
36698 (UINT32_C(0x3) << 4)
36700 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING6_PG_SIZE_PG_8M \
36701 (UINT32_C(0x4) << 4)
36703 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING6_PG_SIZE_PG_1G \
36704 (UINT32_C(0x5) << 4)
36705 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING6_PG_SIZE_LAST \
36706 HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING6_PG_SIZE_PG_1G
36707 /* TQM ring 7 page size and level. */
36708 uint8_t tqm_ring7_pg_size_tqm_ring7_lvl;
36709 /* TQM ring 7 PBL indirect levels. */
36710 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING7_LVL_MASK \
36712 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING7_LVL_SFT 0
36713 /* PBL pointer is physical start address. */
36714 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING7_LVL_LVL_0 \
36716 /* PBL pointer points to PTE table. */
36717 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING7_LVL_LVL_1 \
36720 * PBL pointer points to PDE table with each entry pointing to PTE
36723 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING7_LVL_LVL_2 \
36725 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING7_LVL_LAST \
36726 HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING7_LVL_LVL_2
36727 /* TQM ring 7 page size. */
36728 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING7_PG_SIZE_MASK \
36730 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING7_PG_SIZE_SFT 4
36732 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING7_PG_SIZE_PG_4K \
36733 (UINT32_C(0x0) << 4)
36735 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING7_PG_SIZE_PG_8K \
36736 (UINT32_C(0x1) << 4)
36738 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING7_PG_SIZE_PG_64K \
36739 (UINT32_C(0x2) << 4)
36741 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING7_PG_SIZE_PG_2M \
36742 (UINT32_C(0x3) << 4)
36744 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING7_PG_SIZE_PG_8M \
36745 (UINT32_C(0x4) << 4)
36747 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING7_PG_SIZE_PG_1G \
36748 (UINT32_C(0x5) << 4)
36749 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING7_PG_SIZE_LAST \
36750 HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING7_PG_SIZE_PG_1G
36751 /* TQM ring 0 page directory. */
36752 uint64_t tqm_ring0_page_dir;
36753 /* TQM ring 1 page directory. */
36754 uint64_t tqm_ring1_page_dir;
36755 /* TQM ring 2 page directory. */
36756 uint64_t tqm_ring2_page_dir;
36757 /* TQM ring 3 page directory. */
36758 uint64_t tqm_ring3_page_dir;
36759 /* TQM ring 4 page directory. */
36760 uint64_t tqm_ring4_page_dir;
36761 /* TQM ring 5 page directory. */
36762 uint64_t tqm_ring5_page_dir;
36763 /* TQM ring 6 page directory. */
36764 uint64_t tqm_ring6_page_dir;
36765 /* TQM ring 7 page directory. */
36766 uint64_t tqm_ring7_page_dir;
36768 * Number of TQM ring 0 entries.
36770 * TQM fastpath rings should be sized large enough to accommodate the
36771 * maximum number of QPs (either L2 or RoCE, or both if shared)
36772 * that can be enqueued to the TQM ring.
36774 * Note that TQM ring sizes cannot be extended while the system is
36775 * operational. If a PF driver needs to extend a TQM ring, it needs
36776 * to delete the SCHQ and then reallocate it.
36778 uint32_t tqm_ring0_num_entries;
36780 * Number of TQM ring 1 entries.
36782 * TQM fastpath rings should be sized large enough to accommodate the
36783 * maximum number of QPs (either L2 or RoCE, or both if shared)
36784 * that can be enqueued to the TQM ring.
36786 * Note that TQM ring sizes cannot be extended while the system is
36787 * operational. If a PF driver needs to extend a TQM ring, it needs
36788 * to delete the SCHQ and then reallocate it.
36790 uint32_t tqm_ring1_num_entries;
36792 * Number of TQM ring 2 entries.
36794 * TQM fastpath rings should be sized large enough to accommodate the
36795 * maximum number of QPs (either L2 or RoCE, or both if shared)
36796 * that can be enqueued to the TQM ring.
36798 * Note that TQM ring sizes cannot be extended while the system is
36799 * operational. If a PF driver needs to extend a TQM ring, it needs
36800 * to delete the SCHQ and then reallocate it.
36802 uint32_t tqm_ring2_num_entries;
36804 * Number of TQM ring 3 entries.
36806 * TQM fastpath rings should be sized large enough to accommodate the
36807 * maximum number of QPs (either L2 or RoCE, or both if shared)
36808 * that can be enqueued to the TQM ring.
36810 * Note that TQM ring sizes cannot be extended while the system is
36811 * operational. If a PF driver needs to extend a TQM ring, it needs
36812 * to delete the SCHQ and then reallocate it.
36814 uint32_t tqm_ring3_num_entries;
36816 * Number of TQM ring 4 entries.
36818 * TQM fastpath rings should be sized large enough to accommodate the
36819 * maximum number of QPs (either L2 or RoCE, or both if shared)
36820 * that can be enqueued to the TQM ring.
36822 * Note that TQM ring sizes cannot be extended while the system is
36823 * operational. If a PF driver needs to extend a TQM ring, it needs
36824 * to delete the SCHQ and then reallocate it.
36826 uint32_t tqm_ring4_num_entries;
36828 * Number of TQM ring 5 entries.
36830 * TQM fastpath rings should be sized large enough to accommodate the
36831 * maximum number of QPs (either L2 or RoCE, or both if shared)
36832 * that can be enqueued to the TQM ring.
36834 * Note that TQM ring sizes cannot be extended while the system is
36835 * operational. If a PF driver needs to extend a TQM ring, it needs
36836 * to delete the SCHQ and then reallocate it.
36838 uint32_t tqm_ring5_num_entries;
36840 * Number of TQM ring 6 entries.
36842 * TQM fastpath rings should be sized large enough to accommodate the
36843 * maximum number of QPs (either L2 or RoCE, or both if shared)
36844 * that can be enqueued to the TQM ring.
36846 * Note that TQM ring sizes cannot be extended while the system is
36847 * operational. If a PF driver needs to extend a TQM ring, it needs
36848 * to delete the SCHQ and then reallocate it.
36850 uint32_t tqm_ring6_num_entries;
36852 * Number of TQM ring 7 entries.
36854 * TQM fastpath rings should be sized large enough to accommodate the
36855 * maximum number of QPs (either L2 or RoCE, or both if shared)
36856 * that can be enqueued to the TQM ring.
36858 * Note that TQM ring sizes cannot be extended while the system is
36859 * operational. If a PF driver needs to extend a TQM ring, it needs
36860 * to delete the SCHQ and then reallocate it.
36862 uint32_t tqm_ring7_num_entries;
36863 /* Number of bytes that have been allocated for each context entry. */
36864 uint16_t tqm_entry_size;
36865 uint8_t unused_0[6];
36868 /* hwrm_ring_schq_alloc_output (size:128b/16B) */
36869 struct hwrm_ring_schq_alloc_output {
36870 /* The specific error status for the command. */
36871 uint16_t error_code;
36872 /* The HWRM command request type. */
36874 /* The sequence ID from the original command. */
36876 /* The length of the response data in number of bytes. */
36879 * This is an identifier for the SCHQ to be used in other HWRM commands
36880 * that need to reference this SCHQ. This value is greater than zero
36881 * (i.e. a schq_id of zero references the default SCHQ).
36884 uint8_t unused_0[5];
36886 * This field is used in Output records to indicate that the output
36887 * is completely written to RAM. This field should be read as '1'
36888 * to indicate that the output has been completely written.
36889 * When writing a command completion or response to an internal processor,
36890 * the order of writes has to be such that this field is written last.
36895 /**********************
36896 * hwrm_ring_schq_cfg *
36897 **********************/
36900 /* hwrm_ring_schq_cfg_input (size:768b/96B) */
36901 struct hwrm_ring_schq_cfg_input {
36902 /* The HWRM command request type. */
36905 * The completion ring to send the completion event on. This should
36906 * be the NQ ID returned from the `nq_alloc` HWRM command.
36908 uint16_t cmpl_ring;
36910 * The sequence ID is used by the driver for tracking multiple
36911 * commands. This ID is treated as opaque data by the firmware and
36912 * the value is returned in the `hwrm_resp_hdr` upon completion.
36916 * The target ID of the command:
36917 * * 0x0-0xFFF8 - The function ID
36918 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
36919 * * 0xFFFD - Reserved for user-space HWRM interface
36922 uint16_t target_id;
36924 * A physical address pointer pointing to a host buffer that the
36925 * command's response data will be written. This can be either a host
36926 * physical address (HPA) or a guest physical address (GPA) and must
36927 * point to a physically contiguous block of memory.
36929 uint64_t resp_addr;
36931 * Identifies the SCHQ being configured. A schq_id of zero refers to
36932 * the default SCHQ.
36936 * This field is an 8 bit bitmap that indicates which TCs are enabled
36937 * in this SCHQ. Bit 0 represents traffic class 0 and bit 7 represents
36940 uint8_t tc_enabled;
36943 /* The tc_max_bw array and the max_bw parameters are valid */
36944 #define HWRM_RING_SCHQ_CFG_INPUT_FLAGS_TC_MAX_BW_ENABLED \
36946 /* The tc_min_bw array is valid */
36947 #define HWRM_RING_SCHQ_CFG_INPUT_FLAGS_TC_MIN_BW_ENABLED \
36949 /* Maximum bandwidth of the traffic class, specified in Mbps. */
36950 uint32_t max_bw_tc0;
36951 /* Maximum bandwidth of the traffic class, specified in Mbps. */
36952 uint32_t max_bw_tc1;
36953 /* Maximum bandwidth of the traffic class, specified in Mbps. */
36954 uint32_t max_bw_tc2;
36955 /* Maximum bandwidth of the traffic class, specified in Mbps. */
36956 uint32_t max_bw_tc3;
36957 /* Maximum bandwidth of the traffic class, specified in Mbps. */
36958 uint32_t max_bw_tc4;
36959 /* Maximum bandwidth of the traffic class, specified in Mbps. */
36960 uint32_t max_bw_tc5;
36961 /* Maximum bandwidth of the traffic class, specified in Mbps. */
36962 uint32_t max_bw_tc6;
36963 /* Maximum bandwidth of the traffic class, specified in Mbps. */
36964 uint32_t max_bw_tc7;
36966 * Bandwidth reservation for the traffic class, specified in Mbps.
36967 * A value of zero signifies that traffic belonging to this class
36968 * shares the bandwidth reservation for the same traffic class of
36969 * the default SCHQ.
36971 uint32_t min_bw_tc0;
36973 * Bandwidth reservation for the traffic class, specified in Mbps.
36974 * A value of zero signifies that traffic belonging to this class
36975 * shares the bandwidth reservation for the same traffic class of
36976 * the default SCHQ.
36978 uint32_t min_bw_tc1;
36980 * Bandwidth reservation for the traffic class, specified in Mbps.
36981 * A value of zero signifies that traffic belonging to this class
36982 * shares the bandwidth reservation for the same traffic class of
36983 * the default SCHQ.
36985 uint32_t min_bw_tc2;
36987 * Bandwidth reservation for the traffic class, specified in Mbps.
36988 * A value of zero signifies that traffic belonging to this class
36989 * shares the bandwidth reservation for the same traffic class of
36990 * the default SCHQ.
36992 uint32_t min_bw_tc3;
36994 * Bandwidth reservation for the traffic class, specified in Mbps.
36995 * A value of zero signifies that traffic belonging to this class
36996 * shares the bandwidth reservation for the same traffic class of
36997 * the default SCHQ.
36999 uint32_t min_bw_tc4;
37001 * Bandwidth reservation for the traffic class, specified in Mbps.
37002 * A value of zero signifies that traffic belonging to this class
37003 * shares the bandwidth reservation for the same traffic class of
37004 * the default SCHQ.
37006 uint32_t min_bw_tc5;
37008 * Bandwidth reservation for the traffic class, specified in Mbps.
37009 * A value of zero signifies that traffic belonging to this class
37010 * shares the bandwidth reservation for the same traffic class of
37011 * the default SCHQ.
37013 uint32_t min_bw_tc6;
37015 * Bandwidth reservation for the traffic class, specified in Mbps.
37016 * A value of zero signifies that traffic belonging to this class
37017 * shares the bandwidth reservation for the same traffic class of
37018 * the default SCHQ.
37020 uint32_t min_bw_tc7;
37022 * Indicates the max bandwidth for all enabled traffic classes in
37023 * this SCHQ, specified in Mbps.
37026 uint8_t unused_1[4];
37029 /* hwrm_ring_schq_cfg_output (size:128b/16B) */
37030 struct hwrm_ring_schq_cfg_output {
37031 /* The specific error status for the command. */
37032 uint16_t error_code;
37033 /* The HWRM command request type. */
37035 /* The sequence ID from the original command. */
37037 /* The length of the response data in number of bytes. */
37039 uint8_t unused_0[7];
37041 * This field is used in Output records to indicate that the output
37042 * is completely written to RAM. This field should be read as '1'
37043 * to indicate that the output has been completely written.
37044 * When writing a command completion or response to an internal processor,
37045 * the order of writes has to be such that this field is written last.
37050 /***********************
37051 * hwrm_ring_schq_free *
37052 ***********************/
37055 /* hwrm_ring_schq_free_input (size:192b/24B) */
37056 struct hwrm_ring_schq_free_input {
37057 /* The HWRM command request type. */
37060 * The completion ring to send the completion event on. This should
37061 * be the NQ ID returned from the `nq_alloc` HWRM command.
37063 uint16_t cmpl_ring;
37065 * The sequence ID is used by the driver for tracking multiple
37066 * commands. This ID is treated as opaque data by the firmware and
37067 * the value is returned in the `hwrm_resp_hdr` upon completion.
37071 * The target ID of the command:
37072 * * 0x0-0xFFF8 - The function ID
37073 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
37074 * * 0xFFFD - Reserved for user-space HWRM interface
37077 uint16_t target_id;
37079 * A physical address pointer pointing to a host buffer that the
37080 * command's response data will be written. This can be either a host
37081 * physical address (HPA) or a guest physical address (GPA) and must
37082 * point to a physically contiguous block of memory.
37084 uint64_t resp_addr;
37085 /* Identifies the SCHQ being freed. */
37087 uint8_t unused_0[6];
37090 /* hwrm_ring_schq_free_output (size:128b/16B) */
37091 struct hwrm_ring_schq_free_output {
37092 /* The specific error status for the command. */
37093 uint16_t error_code;
37094 /* The HWRM command request type. */
37096 /* The sequence ID from the original command. */
37098 /* The length of the response data in number of bytes. */
37100 uint8_t unused_0[7];
37102 * This field is used in Output records to indicate that the output
37103 * is completely written to RAM. This field should be read as '1'
37104 * to indicate that the output has been completely written.
37105 * When writing a command completion or response to an internal processor,
37106 * the order of writes has to be such that this field is written last.
37111 * special reserved flow ID to identify per function default
37112 * flows for vSwitch offload
37114 #define DEFAULT_FLOW_ID 0xFFFFFFFFUL
37116 * special reserved flow ID to identify per function RoCEv1
37119 #define ROCEV1_FLOW_ID 0xFFFFFFFEUL
37121 * special reserved flow ID to identify per function RoCEv2
37124 #define ROCEV2_FLOW_ID 0xFFFFFFFDUL
37126 * special reserved flow ID to identify per function RoCEv2
37129 #define ROCEV2_CNP_FLOW_ID 0xFFFFFFFCUL
37131 /****************************
37132 * hwrm_cfa_l2_filter_alloc *
37133 ****************************/
37136 /* hwrm_cfa_l2_filter_alloc_input (size:768b/96B) */
37137 struct hwrm_cfa_l2_filter_alloc_input {
37138 /* The HWRM command request type. */
37141 * The completion ring to send the completion event on. This should
37142 * be the NQ ID returned from the `nq_alloc` HWRM command.
37144 uint16_t cmpl_ring;
37146 * The sequence ID is used by the driver for tracking multiple
37147 * commands. This ID is treated as opaque data by the firmware and
37148 * the value is returned in the `hwrm_resp_hdr` upon completion.
37152 * The target ID of the command:
37153 * * 0x0-0xFFF8 - The function ID
37154 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
37155 * * 0xFFFD - Reserved for user-space HWRM interface
37158 uint16_t target_id;
37160 * A physical address pointer pointing to a host buffer that the
37161 * command's response data will be written. This can be either a host
37162 * physical address (HPA) or a guest physical address (GPA) and must
37163 * point to a physically contiguous block of memory.
37165 uint64_t resp_addr;
37168 * Enumeration denoting the RX, TX type of the resource.
37169 * This enumeration is used for resources that are similar for both
37170 * TX and RX paths of the chip.
37172 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_PATH \
37175 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_PATH_TX \
37178 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_PATH_RX \
37180 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_PATH_LAST \
37181 HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_PATH_RX
37183 * Setting of this flag indicates the applicability to the loopback
37186 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_LOOPBACK \
37189 * Setting of this flag indicates drop action. If this flag is not
37190 * set, then it should be considered accept action.
37192 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_DROP \
37195 * If this flag is set, all t_l2_* fields are invalid
37196 * and they should not be specified.
37197 * If this flag is set, then l2_* fields refer to
37198 * fields of outermost L2 header.
37200 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_OUTERMOST \
37203 * Enumeration denoting NO_ROCE_L2 to support old drivers.
37204 * New driver L2 for only L2 traffic, ROCE for roce and l2 traffic
37206 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_TRAFFIC_MASK \
37208 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_TRAFFIC_SFT 4
37209 /* To support old drivers */
37210 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_TRAFFIC_NO_ROCE_L2 \
37211 (UINT32_C(0x0) << 4)
37212 /* Only L2 traffic */
37213 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_TRAFFIC_L2 \
37214 (UINT32_C(0x1) << 4)
37215 /* Roce & L2 traffic */
37216 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_TRAFFIC_ROCE \
37217 (UINT32_C(0x2) << 4)
37218 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_TRAFFIC_LAST \
37219 HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_TRAFFIC_ROCE
37221 * Setting of this flag indicates that no XDP filter is created with
37223 * 0 - legacy behavior, XDP filter is created with L2 filter
37224 * 1 - XDP filter won't be created with L2 filter
37226 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_XDP_DISABLE \
37229 * Setting this flag to 1 indicate the L2 fields in this command
37230 * pertain to source fields. Setting this flag to 0 indicate the
37231 * L2 fields in this command pertain to the destination fields
37232 * and this is the default/legacy behavior.
37234 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_SOURCE_VALID \
37238 * This bit must be '1' for the l2_addr field to be
37241 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_ADDR \
37244 * This bit must be '1' for the l2_addr_mask field to be
37247 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_ADDR_MASK \
37250 * This bit must be '1' for the l2_ovlan field to be
37253 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_OVLAN \
37256 * This bit must be '1' for the l2_ovlan_mask field to be
37259 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_OVLAN_MASK \
37262 * This bit must be '1' for the l2_ivlan field to be
37265 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN \
37268 * This bit must be '1' for the l2_ivlan_mask field to be
37271 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN_MASK \
37274 * This bit must be '1' for the t_l2_addr field to be
37277 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_T_L2_ADDR \
37280 * This bit must be '1' for the t_l2_addr_mask field to be
37283 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_T_L2_ADDR_MASK \
37286 * This bit must be '1' for the t_l2_ovlan field to be
37289 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_T_L2_OVLAN \
37292 * This bit must be '1' for the t_l2_ovlan_mask field to be
37295 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_T_L2_OVLAN_MASK \
37298 * This bit must be '1' for the t_l2_ivlan field to be
37301 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_T_L2_IVLAN \
37304 * This bit must be '1' for the t_l2_ivlan_mask field to be
37307 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_T_L2_IVLAN_MASK \
37310 * This bit must be '1' for the src_type field to be
37313 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_SRC_TYPE \
37316 * This bit must be '1' for the src_id field to be
37319 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_SRC_ID \
37322 * This bit must be '1' for the tunnel_type field to be
37325 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_TUNNEL_TYPE \
37328 * This bit must be '1' for the dst_id field to be
37331 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_DST_ID \
37334 * This bit must be '1' for the mirror_vnic_id field to be
37337 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_MIRROR_VNIC_ID \
37340 * This bit must be '1' for the num_vlans field to be
37343 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_NUM_VLANS \
37346 * This bit must be '1' for the t_num_vlans field to be
37349 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_T_NUM_VLANS \
37352 * This value sets the match value for the L2 MAC address.
37353 * Destination MAC address for RX path.
37354 * Source MAC address for TX path.
37356 uint8_t l2_addr[6];
37357 /* This value sets the match value for the number of VLANs. */
37360 * This value sets the match value for the number of VLANs
37361 * in the tunnel headers.
37363 uint8_t t_num_vlans;
37365 * This value sets the mask value for the L2 address.
37366 * A value of 0 will mask the corresponding bit from
37369 uint8_t l2_addr_mask[6];
37370 /* This value sets VLAN ID value for outer VLAN. */
37373 * This value sets the mask value for the ovlan id.
37374 * A value of 0 will mask the corresponding bit from
37377 uint16_t l2_ovlan_mask;
37378 /* This value sets VLAN ID value for inner VLAN. */
37381 * This value sets the mask value for the ivlan id.
37382 * A value of 0 will mask the corresponding bit from
37385 uint16_t l2_ivlan_mask;
37386 uint8_t unused_1[2];
37388 * This value sets the match value for the tunnel
37390 * Destination MAC address for RX path.
37391 * Source MAC address for TX path.
37393 uint8_t t_l2_addr[6];
37394 uint8_t unused_2[2];
37396 * This value sets the mask value for the tunnel L2
37398 * A value of 0 will mask the corresponding bit from
37401 uint8_t t_l2_addr_mask[6];
37402 /* This value sets VLAN ID value for tunnel outer VLAN. */
37403 uint16_t t_l2_ovlan;
37405 * This value sets the mask value for the tunnel ovlan id.
37406 * A value of 0 will mask the corresponding bit from
37409 uint16_t t_l2_ovlan_mask;
37410 /* This value sets VLAN ID value for tunnel inner VLAN. */
37411 uint16_t t_l2_ivlan;
37413 * This value sets the mask value for the tunnel ivlan id.
37414 * A value of 0 will mask the corresponding bit from
37417 uint16_t t_l2_ivlan_mask;
37418 /* This value identifies the type of source of the packet. */
37421 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_SRC_TYPE_NPORT UINT32_C(0x0)
37422 /* Physical function */
37423 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_SRC_TYPE_PF UINT32_C(0x1)
37424 /* Virtual function */
37425 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_SRC_TYPE_VF UINT32_C(0x2)
37426 /* Virtual NIC of a function */
37427 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_SRC_TYPE_VNIC UINT32_C(0x3)
37428 /* Embedded processor for CFA management */
37429 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_SRC_TYPE_KONG UINT32_C(0x4)
37430 /* Embedded processor for OOB management */
37431 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_SRC_TYPE_APE UINT32_C(0x5)
37432 /* Embedded processor for RoCE */
37433 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_SRC_TYPE_BONO UINT32_C(0x6)
37434 /* Embedded processor for network proxy functions */
37435 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_SRC_TYPE_TANG UINT32_C(0x7)
37436 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_SRC_TYPE_LAST \
37437 HWRM_CFA_L2_FILTER_ALLOC_INPUT_SRC_TYPE_TANG
37440 * This value is the id of the source.
37441 * For a network port, it represents port_id.
37442 * For a physical function, it represents fid.
37443 * For a virtual function, it represents vf_id.
37444 * For a vnic, it represents vnic_id.
37445 * For embedded processors, this id is not valid.
37448 * 1. The function ID is implied if it src_id is
37449 * not provided for a src_type that is either
37453 uint8_t tunnel_type;
37455 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_TUNNEL_TYPE_NONTUNNEL \
37457 /* Virtual eXtensible Local Area Network (VXLAN) */
37458 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_TUNNEL_TYPE_VXLAN \
37460 /* Network Virtualization Generic Routing Encapsulation (NVGRE) */
37461 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_TUNNEL_TYPE_NVGRE \
37463 /* Generic Routing Encapsulation (GRE) inside Ethernet payload */
37464 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_TUNNEL_TYPE_L2GRE \
37467 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_TUNNEL_TYPE_IPIP \
37469 /* Generic Network Virtualization Encapsulation (Geneve) */
37470 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_TUNNEL_TYPE_GENEVE \
37472 /* Multi-Protocol Label Switching (MPLS) */
37473 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_TUNNEL_TYPE_MPLS \
37475 /* Stateless Transport Tunnel (STT) */
37476 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_TUNNEL_TYPE_STT \
37478 /* Generic Routing Encapsulation (GRE) inside IP datagram payload */
37479 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_TUNNEL_TYPE_IPGRE \
37481 /* IPV4 over virtual eXtensible Local Area Network (IPV4oVXLAN) */
37482 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_TUNNEL_TYPE_VXLAN_V4 \
37485 * Enhance Generic Routing Encapsulation (GRE version 1) inside IP
37488 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_TUNNEL_TYPE_IPGRE_V1 \
37490 /* Use fixed layer 2 ether type of 0xFFFF */
37491 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_TUNNEL_TYPE_L2_ETYPE \
37494 * IPV6 over virtual eXtensible Local Area Network with GPE header
37497 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_TUNNEL_TYPE_VXLAN_GPE_V6 \
37499 /* Any tunneled traffic */
37500 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_TUNNEL_TYPE_ANYTUNNEL \
37502 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_TUNNEL_TYPE_LAST \
37503 HWRM_CFA_L2_FILTER_ALLOC_INPUT_TUNNEL_TYPE_ANYTUNNEL
37506 * If set, this value shall represent the
37507 * Logical VNIC ID of the destination VNIC for the RX
37508 * path and network port id of the destination port for
37513 * Logical VNIC ID of the VNIC where traffic is
37516 uint16_t mirror_vnic_id;
37518 * This hint is provided to help in placing
37519 * the filter in the filter table.
37522 /* No preference */
37523 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_PRI_HINT_NO_PREFER \
37525 /* Above the given filter */
37526 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_PRI_HINT_ABOVE_FILTER \
37528 /* Below the given filter */
37529 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_PRI_HINT_BELOW_FILTER \
37531 /* As high as possible */
37532 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_PRI_HINT_MAX \
37534 /* As low as possible */
37535 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_PRI_HINT_MIN \
37537 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_PRI_HINT_LAST \
37538 HWRM_CFA_L2_FILTER_ALLOC_INPUT_PRI_HINT_MIN
37542 * This is the ID of the filter that goes along with
37545 * This field is valid only for the following values.
37546 * 1 - Above the given filter
37547 * 2 - Below the given filter
37549 uint64_t l2_filter_id_hint;
37552 /* hwrm_cfa_l2_filter_alloc_output (size:192b/24B) */
37553 struct hwrm_cfa_l2_filter_alloc_output {
37554 /* The specific error status for the command. */
37555 uint16_t error_code;
37556 /* The HWRM command request type. */
37558 /* The sequence ID from the original command. */
37560 /* The length of the response data in number of bytes. */
37563 * This value identifies a set of CFA data structures used for an L2
37566 uint64_t l2_filter_id;
37568 * The flow id value in bit 0-29 is the actual ID of the flow
37569 * associated with this filter and it shall be used to match
37570 * and associate the flow identifier returned in completion
37571 * records. A value of 0xFFFFFFFF in the 32-bit flow_id field
37572 * shall indicate no valid flow id.
37575 /* Indicate the flow id value. */
37576 #define HWRM_CFA_L2_FILTER_ALLOC_OUTPUT_FLOW_ID_VALUE_MASK \
37577 UINT32_C(0x3fffffff)
37578 #define HWRM_CFA_L2_FILTER_ALLOC_OUTPUT_FLOW_ID_VALUE_SFT 0
37579 /* Indicate type of the flow. */
37580 #define HWRM_CFA_L2_FILTER_ALLOC_OUTPUT_FLOW_ID_TYPE \
37581 UINT32_C(0x40000000)
37583 * If this bit set to 0, then it indicates that the flow is
37586 #define HWRM_CFA_L2_FILTER_ALLOC_OUTPUT_FLOW_ID_TYPE_INT \
37587 (UINT32_C(0x0) << 30)
37589 * If this bit is set to 1, then it indicates that the flow is
37592 #define HWRM_CFA_L2_FILTER_ALLOC_OUTPUT_FLOW_ID_TYPE_EXT \
37593 (UINT32_C(0x1) << 30)
37594 #define HWRM_CFA_L2_FILTER_ALLOC_OUTPUT_FLOW_ID_TYPE_LAST \
37595 HWRM_CFA_L2_FILTER_ALLOC_OUTPUT_FLOW_ID_TYPE_EXT
37596 /* Indicate the flow direction. */
37597 #define HWRM_CFA_L2_FILTER_ALLOC_OUTPUT_FLOW_ID_DIR \
37598 UINT32_C(0x80000000)
37599 /* If this bit set to 0, then it indicates rx flow. */
37600 #define HWRM_CFA_L2_FILTER_ALLOC_OUTPUT_FLOW_ID_DIR_RX \
37601 (UINT32_C(0x0) << 31)
37602 /* If this bit is set to 1, then it indicates that tx flow. */
37603 #define HWRM_CFA_L2_FILTER_ALLOC_OUTPUT_FLOW_ID_DIR_TX \
37604 (UINT32_C(0x1) << 31)
37605 #define HWRM_CFA_L2_FILTER_ALLOC_OUTPUT_FLOW_ID_DIR_LAST \
37606 HWRM_CFA_L2_FILTER_ALLOC_OUTPUT_FLOW_ID_DIR_TX
37607 uint8_t unused_0[3];
37609 * This field is used in Output records to indicate that the output
37610 * is completely written to RAM. This field should be read as '1'
37611 * to indicate that the output has been completely written.
37612 * When writing a command completion or response to an internal
37613 * processor, the order of writes has to be such that this field is
37619 /***************************
37620 * hwrm_cfa_l2_filter_free *
37621 ***************************/
37624 /* hwrm_cfa_l2_filter_free_input (size:192b/24B) */
37625 struct hwrm_cfa_l2_filter_free_input {
37626 /* The HWRM command request type. */
37629 * The completion ring to send the completion event on. This should
37630 * be the NQ ID returned from the `nq_alloc` HWRM command.
37632 uint16_t cmpl_ring;
37634 * The sequence ID is used by the driver for tracking multiple
37635 * commands. This ID is treated as opaque data by the firmware and
37636 * the value is returned in the `hwrm_resp_hdr` upon completion.
37640 * The target ID of the command:
37641 * * 0x0-0xFFF8 - The function ID
37642 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
37643 * * 0xFFFD - Reserved for user-space HWRM interface
37646 uint16_t target_id;
37648 * A physical address pointer pointing to a host buffer that the
37649 * command's response data will be written. This can be either a host
37650 * physical address (HPA) or a guest physical address (GPA) and must
37651 * point to a physically contiguous block of memory.
37653 uint64_t resp_addr;
37655 * This value identifies a set of CFA data structures used for an L2
37658 uint64_t l2_filter_id;
37661 /* hwrm_cfa_l2_filter_free_output (size:128b/16B) */
37662 struct hwrm_cfa_l2_filter_free_output {
37663 /* The specific error status for the command. */
37664 uint16_t error_code;
37665 /* The HWRM command request type. */
37667 /* The sequence ID from the original command. */
37669 /* The length of the response data in number of bytes. */
37671 uint8_t unused_0[7];
37673 * This field is used in Output records to indicate that the output
37674 * is completely written to RAM. This field should be read as '1'
37675 * to indicate that the output has been completely written.
37676 * When writing a command completion or response to an internal
37677 * processor, the order of writes has to be such that this field is
37683 /**************************
37684 * hwrm_cfa_l2_filter_cfg *
37685 **************************/
37688 /* hwrm_cfa_l2_filter_cfg_input (size:320b/40B) */
37689 struct hwrm_cfa_l2_filter_cfg_input {
37690 /* The HWRM command request type. */
37693 * The completion ring to send the completion event on. This should
37694 * be the NQ ID returned from the `nq_alloc` HWRM command.
37696 uint16_t cmpl_ring;
37698 * The sequence ID is used by the driver for tracking multiple
37699 * commands. This ID is treated as opaque data by the firmware and
37700 * the value is returned in the `hwrm_resp_hdr` upon completion.
37704 * The target ID of the command:
37705 * * 0x0-0xFFF8 - The function ID
37706 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
37707 * * 0xFFFD - Reserved for user-space HWRM interface
37710 uint16_t target_id;
37712 * A physical address pointer pointing to a host buffer that the
37713 * command's response data will be written. This can be either a host
37714 * physical address (HPA) or a guest physical address (GPA) and must
37715 * point to a physically contiguous block of memory.
37717 uint64_t resp_addr;
37720 * Enumeration denoting the RX, TX type of the resource.
37721 * This enumeration is used for resources that are similar for both
37722 * TX and RX paths of the chip.
37724 #define HWRM_CFA_L2_FILTER_CFG_INPUT_FLAGS_PATH \
37727 #define HWRM_CFA_L2_FILTER_CFG_INPUT_FLAGS_PATH_TX \
37730 #define HWRM_CFA_L2_FILTER_CFG_INPUT_FLAGS_PATH_RX \
37732 #define HWRM_CFA_L2_FILTER_CFG_INPUT_FLAGS_PATH_LAST \
37733 HWRM_CFA_L2_FILTER_CFG_INPUT_FLAGS_PATH_RX
37735 * Setting of this flag indicates drop action. If this flag is not
37736 * set, then it should be considered accept action.
37738 #define HWRM_CFA_L2_FILTER_CFG_INPUT_FLAGS_DROP \
37741 * Enumeration denoting NO_ROCE_L2 to support old drivers.
37742 * New driver L2 for only L2 traffic, ROCE for roce and l2 traffic
37744 #define HWRM_CFA_L2_FILTER_CFG_INPUT_FLAGS_TRAFFIC_MASK \
37746 #define HWRM_CFA_L2_FILTER_CFG_INPUT_FLAGS_TRAFFIC_SFT 2
37747 /* To support old drivers */
37748 #define HWRM_CFA_L2_FILTER_CFG_INPUT_FLAGS_TRAFFIC_NO_ROCE_L2 \
37749 (UINT32_C(0x0) << 2)
37750 /* Only L2 traffic */
37751 #define HWRM_CFA_L2_FILTER_CFG_INPUT_FLAGS_TRAFFIC_L2 \
37752 (UINT32_C(0x1) << 2)
37753 /* Roce & L2 traffic */
37754 #define HWRM_CFA_L2_FILTER_CFG_INPUT_FLAGS_TRAFFIC_ROCE \
37755 (UINT32_C(0x2) << 2)
37756 #define HWRM_CFA_L2_FILTER_CFG_INPUT_FLAGS_TRAFFIC_LAST \
37757 HWRM_CFA_L2_FILTER_CFG_INPUT_FLAGS_TRAFFIC_ROCE
37760 * This bit must be '1' for the dst_id field to be
37763 #define HWRM_CFA_L2_FILTER_CFG_INPUT_ENABLES_DST_ID \
37766 * This bit must be '1' for the new_mirror_vnic_id field to be
37769 #define HWRM_CFA_L2_FILTER_CFG_INPUT_ENABLES_NEW_MIRROR_VNIC_ID \
37772 * This value identifies a set of CFA data structures used for an L2
37775 uint64_t l2_filter_id;
37777 * If set, this value shall represent the
37778 * Logical VNIC ID of the destination VNIC for the RX
37779 * path and network port id of the destination port for
37784 * New Logical VNIC ID of the VNIC where traffic is
37787 uint32_t new_mirror_vnic_id;
37790 /* hwrm_cfa_l2_filter_cfg_output (size:128b/16B) */
37791 struct hwrm_cfa_l2_filter_cfg_output {
37792 /* The specific error status for the command. */
37793 uint16_t error_code;
37794 /* The HWRM command request type. */
37796 /* The sequence ID from the original command. */
37798 /* The length of the response data in number of bytes. */
37800 uint8_t unused_0[7];
37802 * This field is used in Output records to indicate that the output
37803 * is completely written to RAM. This field should be read as '1'
37804 * to indicate that the output has been completely written.
37805 * When writing a command completion or response to an internal
37806 * processor, the order of writes has to be such that this field is
37812 /***************************
37813 * hwrm_cfa_l2_set_rx_mask *
37814 ***************************/
37817 /* hwrm_cfa_l2_set_rx_mask_input (size:448b/56B) */
37818 struct hwrm_cfa_l2_set_rx_mask_input {
37819 /* The HWRM command request type. */
37822 * The completion ring to send the completion event on. This should
37823 * be the NQ ID returned from the `nq_alloc` HWRM command.
37825 uint16_t cmpl_ring;
37827 * The sequence ID is used by the driver for tracking multiple
37828 * commands. This ID is treated as opaque data by the firmware and
37829 * the value is returned in the `hwrm_resp_hdr` upon completion.
37833 * The target ID of the command:
37834 * * 0x0-0xFFF8 - The function ID
37835 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
37836 * * 0xFFFD - Reserved for user-space HWRM interface
37839 uint16_t target_id;
37841 * A physical address pointer pointing to a host buffer that the
37842 * command's response data will be written. This can be either a host
37843 * physical address (HPA) or a guest physical address (GPA) and must
37844 * point to a physically contiguous block of memory.
37846 uint64_t resp_addr;
37851 * When this bit is '1', the function is requested to accept
37852 * multi-cast packets specified by the multicast addr table.
37854 #define HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_MCAST \
37857 * When this bit is '1', the function is requested to accept
37858 * all multi-cast packets.
37860 #define HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_ALL_MCAST \
37863 * When this bit is '1', the function is requested to accept
37864 * broadcast packets.
37866 #define HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_BCAST \
37869 * When this bit is '1', the function is requested to be
37870 * put in the promiscuous mode.
37872 * The HWRM should accept any function to set up
37873 * promiscuous mode.
37875 * The HWRM shall follow the semantics below for the
37876 * promiscuous mode support.
37877 * # When partitioning is not enabled on a port
37878 * (i.e. single PF on the port), then the PF shall
37879 * be allowed to be in the promiscuous mode. When the
37880 * PF is in the promiscuous mode, then it shall
37881 * receive all host bound traffic on that port.
37882 * # When partitioning is enabled on a port
37883 * (i.e. multiple PFs per port) and a PF on that
37884 * port is in the promiscuous mode, then the PF
37885 * receives all traffic within that partition as
37886 * identified by a unique identifier for the
37887 * PF (e.g. S-Tag). If a unique outer VLAN
37888 * for the PF is specified, then the setting of
37889 * promiscuous mode on that PF shall result in the
37890 * PF receiving all host bound traffic with matching
37892 * # A VF shall can be set in the promiscuous mode.
37893 * In the promiscuous mode, the VF does not receive any
37894 * traffic unless a unique outer VLAN for the
37895 * VF is specified. If a unique outer VLAN
37896 * for the VF is specified, then the setting of
37897 * promiscuous mode on that VF shall result in the
37898 * VF receiving all host bound traffic with the
37899 * matching outer VLAN.
37900 * # The HWRM shall allow the setting of promiscuous
37901 * mode on a function independently from the
37902 * promiscuous mode settings on other functions.
37904 #define HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_PROMISCUOUS \
37907 * If this flag is set, the corresponding RX
37908 * filters shall be set up to cover multicast/broadcast
37909 * filters for the outermost Layer 2 destination MAC
37912 #define HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_OUTERMOST \
37915 * If this flag is set, the corresponding RX
37916 * filters shall be set up to cover multicast/broadcast
37917 * filters for the VLAN-tagged packets that match the
37918 * TPID and VID fields of VLAN tags in the VLAN tag
37919 * table specified in this command.
37921 #define HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_VLANONLY \
37924 * If this flag is set, the corresponding RX
37925 * filters shall be set up to cover multicast/broadcast
37926 * filters for non-VLAN tagged packets and VLAN-tagged
37927 * packets that match the TPID and VID fields of VLAN
37928 * tags in the VLAN tag table specified in this command.
37930 #define HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_VLAN_NONVLAN \
37933 * If this flag is set, the corresponding RX
37934 * filters shall be set up to cover multicast/broadcast
37935 * filters for non-VLAN tagged packets and VLAN-tagged
37936 * packets matching any VLAN tag.
37938 * If this flag is set, then the HWRM shall ignore
37939 * VLAN tags specified in vlan_tag_tbl.
37941 * If none of vlanonly, vlan_nonvlan, and anyvlan_nonvlan
37942 * flags is set, then the HWRM shall ignore
37943 * VLAN tags specified in vlan_tag_tbl.
37945 * The HWRM client shall set at most one flag out of
37946 * vlanonly, vlan_nonvlan, and anyvlan_nonvlan.
37948 #define HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_ANYVLAN_NONVLAN \
37950 /* This is the address for mcast address tbl. */
37951 uint64_t mc_tbl_addr;
37953 * This value indicates how many entries in mc_tbl are valid.
37954 * Each entry is 6 bytes.
37956 uint32_t num_mc_entries;
37957 uint8_t unused_0[4];
37959 * This is the address for VLAN tag table.
37960 * Each VLAN entry in the table is 4 bytes of a VLAN tag
37961 * including TPID, PCP, DEI, and VID fields in network byte
37964 uint64_t vlan_tag_tbl_addr;
37966 * This value indicates how many entries in vlan_tag_tbl are
37967 * valid. Each entry is 4 bytes.
37969 uint32_t num_vlan_tags;
37970 uint8_t unused_1[4];
37973 /* hwrm_cfa_l2_set_rx_mask_output (size:128b/16B) */
37974 struct hwrm_cfa_l2_set_rx_mask_output {
37975 /* The specific error status for the command. */
37976 uint16_t error_code;
37977 /* The HWRM command request type. */
37979 /* The sequence ID from the original command. */
37981 /* The length of the response data in number of bytes. */
37983 uint8_t unused_0[7];
37985 * This field is used in Output records to indicate that the output
37986 * is completely written to RAM. This field should be read as '1'
37987 * to indicate that the output has been completely written.
37988 * When writing a command completion or response to an internal
37989 * processor, the order of writes has to be such that this field is
37995 /* hwrm_cfa_l2_set_rx_mask_cmd_err (size:64b/8B) */
37996 struct hwrm_cfa_l2_set_rx_mask_cmd_err {
37998 * command specific error codes that goes to
37999 * the cmd_err field in Common HWRM Error Response.
38002 /* Unknown error */
38003 #define HWRM_CFA_L2_SET_RX_MASK_CMD_ERR_CODE_UNKNOWN \
38005 /* Unable to complete operation due to conflict with Ntuple Filter */
38006 #define HWRM_CFA_L2_SET_RX_MASK_CMD_ERR_CODE_NTUPLE_FILTER_CONFLICT_ERR \
38008 #define HWRM_CFA_L2_SET_RX_MASK_CMD_ERR_CODE_LAST \
38009 HWRM_CFA_L2_SET_RX_MASK_CMD_ERR_CODE_NTUPLE_FILTER_CONFLICT_ERR
38010 uint8_t unused_0[7];
38013 /*******************************
38014 * hwrm_cfa_vlan_antispoof_cfg *
38015 *******************************/
38018 /* hwrm_cfa_vlan_antispoof_cfg_input (size:256b/32B) */
38019 struct hwrm_cfa_vlan_antispoof_cfg_input {
38020 /* The HWRM command request type. */
38023 * The completion ring to send the completion event on. This should
38024 * be the NQ ID returned from the `nq_alloc` HWRM command.
38026 uint16_t cmpl_ring;
38028 * The sequence ID is used by the driver for tracking multiple
38029 * commands. This ID is treated as opaque data by the firmware and
38030 * the value is returned in the `hwrm_resp_hdr` upon completion.
38034 * The target ID of the command:
38035 * * 0x0-0xFFF8 - The function ID
38036 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
38037 * * 0xFFFD - Reserved for user-space HWRM interface
38040 uint16_t target_id;
38042 * A physical address pointer pointing to a host buffer that the
38043 * command's response data will be written. This can be either a host
38044 * physical address (HPA) or a guest physical address (GPA) and must
38045 * point to a physically contiguous block of memory.
38047 uint64_t resp_addr;
38049 * Function ID of the function that is being configured.
38050 * Only valid for a VF FID configured by the PF.
38053 uint8_t unused_0[2];
38054 /* Number of VLAN entries in the vlan_tag_mask_tbl. */
38055 uint32_t num_vlan_entries;
38057 * The vlan_tag_mask_tbl_addr is the DMA address of the VLAN
38058 * antispoof table. Each table entry contains the 16-bit TPID
38059 * (0x8100 or 0x88a8 only), 16-bit VLAN ID, and a 16-bit mask,
38060 * all in network order to match hwrm_cfa_l2_set_rx_mask.
38061 * For an individual VLAN entry, the mask value should be 0xfff
38062 * for the 12-bit VLAN ID.
38064 uint64_t vlan_tag_mask_tbl_addr;
38067 /* hwrm_cfa_vlan_antispoof_cfg_output (size:128b/16B) */
38068 struct hwrm_cfa_vlan_antispoof_cfg_output {
38069 /* The specific error status for the command. */
38070 uint16_t error_code;
38071 /* The HWRM command request type. */
38073 /* The sequence ID from the original command. */
38075 /* The length of the response data in number of bytes. */
38077 uint8_t unused_0[7];
38079 * This field is used in Output records to indicate that the output
38080 * is completely written to RAM. This field should be read as '1'
38081 * to indicate that the output has been completely written.
38082 * When writing a command completion or response to an internal
38083 * processor, the order of writes has to be such that this field is
38089 /********************************
38090 * hwrm_cfa_vlan_antispoof_qcfg *
38091 ********************************/
38094 /* hwrm_cfa_vlan_antispoof_qcfg_input (size:256b/32B) */
38095 struct hwrm_cfa_vlan_antispoof_qcfg_input {
38096 /* The HWRM command request type. */
38099 * The completion ring to send the completion event on. This should
38100 * be the NQ ID returned from the `nq_alloc` HWRM command.
38102 uint16_t cmpl_ring;
38104 * The sequence ID is used by the driver for tracking multiple
38105 * commands. This ID is treated as opaque data by the firmware and
38106 * the value is returned in the `hwrm_resp_hdr` upon completion.
38110 * The target ID of the command:
38111 * * 0x0-0xFFF8 - The function ID
38112 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
38113 * * 0xFFFD - Reserved for user-space HWRM interface
38116 uint16_t target_id;
38118 * A physical address pointer pointing to a host buffer that the
38119 * command's response data will be written. This can be either a host
38120 * physical address (HPA) or a guest physical address (GPA) and must
38121 * point to a physically contiguous block of memory.
38123 uint64_t resp_addr;
38125 * Function ID of the function that is being queried.
38126 * Only valid for a VF FID queried by the PF.
38129 uint8_t unused_0[2];
38131 * Maximum number of VLAN entries the firmware is allowed to DMA
38132 * to vlan_tag_mask_tbl.
38134 uint32_t max_vlan_entries;
38136 * The vlan_tag_mask_tbl_addr is the DMA address of the VLAN
38137 * antispoof table to which firmware will DMA to. Each table
38138 * entry will contain the 16-bit TPID (0x8100 or 0x88a8 only),
38139 * 16-bit VLAN ID, and a 16-bit mask, all in network order to
38140 * match hwrm_cfa_l2_set_rx_mask. For an individual VLAN entry,
38141 * the mask value should be 0xfff for the 12-bit VLAN ID.
38143 uint64_t vlan_tag_mask_tbl_addr;
38146 /* hwrm_cfa_vlan_antispoof_qcfg_output (size:128b/16B) */
38147 struct hwrm_cfa_vlan_antispoof_qcfg_output {
38148 /* The specific error status for the command. */
38149 uint16_t error_code;
38150 /* The HWRM command request type. */
38152 /* The sequence ID from the original command. */
38154 /* The length of the response data in number of bytes. */
38156 /* Number of valid entries DMAd by firmware to vlan_tag_mask_tbl. */
38157 uint32_t num_vlan_entries;
38158 uint8_t unused_0[3];
38160 * This field is used in Output records to indicate that the output
38161 * is completely written to RAM. This field should be read as '1'
38162 * to indicate that the output has been completely written.
38163 * When writing a command completion or response to an internal
38164 * processor, the order of writes has to be such that this field is
38170 /********************************
38171 * hwrm_cfa_tunnel_filter_alloc *
38172 ********************************/
38175 /* hwrm_cfa_tunnel_filter_alloc_input (size:704b/88B) */
38176 struct hwrm_cfa_tunnel_filter_alloc_input {
38177 /* The HWRM command request type. */
38180 * The completion ring to send the completion event on. This should
38181 * be the NQ ID returned from the `nq_alloc` HWRM command.
38183 uint16_t cmpl_ring;
38185 * The sequence ID is used by the driver for tracking multiple
38186 * commands. This ID is treated as opaque data by the firmware and
38187 * the value is returned in the `hwrm_resp_hdr` upon completion.
38191 * The target ID of the command:
38192 * * 0x0-0xFFF8 - The function ID
38193 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
38194 * * 0xFFFD - Reserved for user-space HWRM interface
38197 uint16_t target_id;
38199 * A physical address pointer pointing to a host buffer that the
38200 * command's response data will be written. This can be either a host
38201 * physical address (HPA) or a guest physical address (GPA) and must
38202 * point to a physically contiguous block of memory.
38204 uint64_t resp_addr;
38207 * Setting of this flag indicates the applicability to the loopback
38210 #define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_FLAGS_LOOPBACK \
38214 * This bit must be '1' for the l2_filter_id field to be
38217 #define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_ENABLES_L2_FILTER_ID \
38220 * This bit must be '1' for the l2_addr field to be
38223 #define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_ENABLES_L2_ADDR \
38226 * This bit must be '1' for the l2_ivlan field to be
38229 #define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN \
38232 * This bit must be '1' for the l3_addr field to be
38235 #define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_ENABLES_L3_ADDR \
38238 * This bit must be '1' for the l3_addr_type field to be
38241 #define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_ENABLES_L3_ADDR_TYPE \
38244 * This bit must be '1' for the t_l3_addr_type field to be
38247 #define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_ENABLES_T_L3_ADDR_TYPE \
38250 * This bit must be '1' for the t_l3_addr field to be
38253 #define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_ENABLES_T_L3_ADDR \
38256 * This bit must be '1' for the tunnel_type field to be
38259 #define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_ENABLES_TUNNEL_TYPE \
38262 * This bit must be '1' for the vni field to be
38265 #define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_ENABLES_VNI \
38268 * This bit must be '1' for the dst_vnic_id field to be
38271 #define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_ENABLES_DST_VNIC_ID \
38274 * This bit must be '1' for the mirror_vnic_id field to be
38277 #define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_ENABLES_MIRROR_VNIC_ID \
38280 * This value identifies a set of CFA data structures used for an L2
38283 uint64_t l2_filter_id;
38285 * This value sets the match value for the inner L2
38287 * Destination MAC address for RX path.
38288 * Source MAC address for TX path.
38290 uint8_t l2_addr[6];
38292 * This value sets VLAN ID value for inner VLAN.
38293 * Only 12-bits of VLAN ID are used in setting the filter.
38297 * The value of inner destination IP address to be used in filtering.
38298 * For IPv4, first four bytes represent the IP address.
38300 uint32_t l3_addr[4];
38302 * The value of tunnel destination IP address to be used in filtering.
38303 * For IPv4, first four bytes represent the IP address.
38305 uint32_t t_l3_addr[4];
38307 * This value indicates the type of inner IP address.
38310 * All others are invalid.
38312 uint8_t l3_addr_type;
38314 * This value indicates the type of tunnel IP address.
38317 * All others are invalid.
38319 uint8_t t_l3_addr_type;
38321 uint8_t tunnel_type;
38323 #define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_TUNNEL_TYPE_NONTUNNEL \
38325 /* Virtual eXtensible Local Area Network (VXLAN) */
38326 #define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_TUNNEL_TYPE_VXLAN \
38328 /* Network Virtualization Generic Routing Encapsulation (NVGRE) */
38329 #define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_TUNNEL_TYPE_NVGRE \
38331 /* Generic Routing Encapsulation (GRE) inside Ethernet payload */
38332 #define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_TUNNEL_TYPE_L2GRE \
38335 #define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_TUNNEL_TYPE_IPIP \
38337 /* Generic Network Virtualization Encapsulation (Geneve) */
38338 #define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_TUNNEL_TYPE_GENEVE \
38340 /* Multi-Protocol Label Switching (MPLS) */
38341 #define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_TUNNEL_TYPE_MPLS \
38343 /* Stateless Transport Tunnel (STT) */
38344 #define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_TUNNEL_TYPE_STT \
38346 /* Generic Routing Encapsulation (GRE) inside IP datagram payload */
38347 #define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_TUNNEL_TYPE_IPGRE \
38349 /* IPV4 over virtual eXtensible Local Area Network (IPV4oVXLAN) */
38350 #define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_TUNNEL_TYPE_VXLAN_V4 \
38353 * Enhance Generic Routing Encapsulation (GRE version 1) inside IP
38356 #define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_TUNNEL_TYPE_IPGRE_V1 \
38358 /* Use fixed layer 2 ether type of 0xFFFF */
38359 #define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_TUNNEL_TYPE_L2_ETYPE \
38362 * IPV6 over virtual eXtensible Local Area Network with GPE header
38365 #define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_TUNNEL_TYPE_VXLAN_GPE_V6 \
38367 /* Any tunneled traffic */
38368 #define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_TUNNEL_TYPE_ANYTUNNEL \
38370 #define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_TUNNEL_TYPE_LAST \
38371 HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_TUNNEL_TYPE_ANYTUNNEL
38373 * tunnel_flags allows the user to indicate the tunnel tag detection
38374 * for the tunnel type specified in tunnel_type.
38376 uint8_t tunnel_flags;
38378 * If the tunnel_type is geneve, then this bit indicates if we
38379 * need to match the geneve OAM packet.
38380 * If the tunnel_type is nvgre or gre, then this bit indicates if
38381 * we need to detect checksum present bit in geneve header.
38382 * If the tunnel_type is mpls, then this bit indicates if we need
38383 * to match mpls packet with explicit IPV4/IPV6 null header.
38385 #define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_TUNNEL_FLAGS_TUN_FLAGS_OAM_CHECKSUM_EXPLHDR \
38388 * If the tunnel_type is geneve, then this bit indicates if we
38389 * need to detect the critical option bit set in the oam packet.
38390 * If the tunnel_type is nvgre or gre, then this bit indicates
38391 * if we need to match nvgre packets with key present bit set in
38393 * If the tunnel_type is mpls, then this bit indicates if we
38394 * need to match mpls packet with S bit from inner/second label.
38396 #define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_TUNNEL_FLAGS_TUN_FLAGS_CRITICAL_OPT_S1 \
38399 * If the tunnel_type is geneve, then this bit indicates if we
38400 * need to match geneve packet with extended header bit set in
38402 * If the tunnel_type is nvgre or gre, then this bit indicates
38403 * if we need to match nvgre packets with sequence number
38404 * present bit set in gre header.
38405 * If the tunnel_type is mpls, then this bit indicates if we
38406 * need to match mpls packet with S bit from out/first label.
38408 #define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_TUNNEL_FLAGS_TUN_FLAGS_EXTHDR_SEQNUM_S0 \
38411 * Virtual Network Identifier (VNI). Only valid with
38412 * tunnel_types VXLAN, NVGRE, and Geneve.
38413 * Only lower 24-bits of VNI field are used
38414 * in setting up the filter.
38417 /* Logical VNIC ID of the destination VNIC. */
38418 uint32_t dst_vnic_id;
38420 * Logical VNIC ID of the VNIC where traffic is
38423 uint32_t mirror_vnic_id;
38426 /* hwrm_cfa_tunnel_filter_alloc_output (size:192b/24B) */
38427 struct hwrm_cfa_tunnel_filter_alloc_output {
38428 /* The specific error status for the command. */
38429 uint16_t error_code;
38430 /* The HWRM command request type. */
38432 /* The sequence ID from the original command. */
38434 /* The length of the response data in number of bytes. */
38436 /* This value is an opaque id into CFA data structures. */
38437 uint64_t tunnel_filter_id;
38439 * The flow id value in bit 0-29 is the actual ID of the flow
38440 * associated with this filter and it shall be used to match
38441 * and associate the flow identifier returned in completion
38442 * records. A value of 0xFFFFFFFF in the 32-bit flow_id field
38443 * shall indicate no valid flow id.
38446 /* Indicate the flow id value. */
38447 #define HWRM_CFA_TUNNEL_FILTER_ALLOC_OUTPUT_FLOW_ID_VALUE_MASK \
38448 UINT32_C(0x3fffffff)
38449 #define HWRM_CFA_TUNNEL_FILTER_ALLOC_OUTPUT_FLOW_ID_VALUE_SFT 0
38450 /* Indicate type of the flow. */
38451 #define HWRM_CFA_TUNNEL_FILTER_ALLOC_OUTPUT_FLOW_ID_TYPE \
38452 UINT32_C(0x40000000)
38454 * If this bit set to 0, then it indicates that the flow is
38457 #define HWRM_CFA_TUNNEL_FILTER_ALLOC_OUTPUT_FLOW_ID_TYPE_INT \
38458 (UINT32_C(0x0) << 30)
38460 * If this bit is set to 1, then it indicates that the flow is
38463 #define HWRM_CFA_TUNNEL_FILTER_ALLOC_OUTPUT_FLOW_ID_TYPE_EXT \
38464 (UINT32_C(0x1) << 30)
38465 #define HWRM_CFA_TUNNEL_FILTER_ALLOC_OUTPUT_FLOW_ID_TYPE_LAST \
38466 HWRM_CFA_TUNNEL_FILTER_ALLOC_OUTPUT_FLOW_ID_TYPE_EXT
38467 /* Indicate the flow direction. */
38468 #define HWRM_CFA_TUNNEL_FILTER_ALLOC_OUTPUT_FLOW_ID_DIR \
38469 UINT32_C(0x80000000)
38470 /* If this bit set to 0, then it indicates rx flow. */
38471 #define HWRM_CFA_TUNNEL_FILTER_ALLOC_OUTPUT_FLOW_ID_DIR_RX \
38472 (UINT32_C(0x0) << 31)
38473 /* If this bit is set to 1, then it indicates that tx flow. */
38474 #define HWRM_CFA_TUNNEL_FILTER_ALLOC_OUTPUT_FLOW_ID_DIR_TX \
38475 (UINT32_C(0x1) << 31)
38476 #define HWRM_CFA_TUNNEL_FILTER_ALLOC_OUTPUT_FLOW_ID_DIR_LAST \
38477 HWRM_CFA_TUNNEL_FILTER_ALLOC_OUTPUT_FLOW_ID_DIR_TX
38478 uint8_t unused_0[3];
38480 * This field is used in Output records to indicate that the output
38481 * is completely written to RAM. This field should be read as '1'
38482 * to indicate that the output has been completely written.
38483 * When writing a command completion or response to an internal
38484 * processor, the order of writes has to be such that this field is
38490 /*******************************
38491 * hwrm_cfa_tunnel_filter_free *
38492 *******************************/
38495 /* hwrm_cfa_tunnel_filter_free_input (size:192b/24B) */
38496 struct hwrm_cfa_tunnel_filter_free_input {
38497 /* The HWRM command request type. */
38500 * The completion ring to send the completion event on. This should
38501 * be the NQ ID returned from the `nq_alloc` HWRM command.
38503 uint16_t cmpl_ring;
38505 * The sequence ID is used by the driver for tracking multiple
38506 * commands. This ID is treated as opaque data by the firmware and
38507 * the value is returned in the `hwrm_resp_hdr` upon completion.
38511 * The target ID of the command:
38512 * * 0x0-0xFFF8 - The function ID
38513 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
38514 * * 0xFFFD - Reserved for user-space HWRM interface
38517 uint16_t target_id;
38519 * A physical address pointer pointing to a host buffer that the
38520 * command's response data will be written. This can be either a host
38521 * physical address (HPA) or a guest physical address (GPA) and must
38522 * point to a physically contiguous block of memory.
38524 uint64_t resp_addr;
38525 /* This value is an opaque id into CFA data structures. */
38526 uint64_t tunnel_filter_id;
38529 /* hwrm_cfa_tunnel_filter_free_output (size:128b/16B) */
38530 struct hwrm_cfa_tunnel_filter_free_output {
38531 /* The specific error status for the command. */
38532 uint16_t error_code;
38533 /* The HWRM command request type. */
38535 /* The sequence ID from the original command. */
38537 /* The length of the response data in number of bytes. */
38539 uint8_t unused_0[7];
38541 * This field is used in Output records to indicate that the output
38542 * is completely written to RAM. This field should be read as '1'
38543 * to indicate that the output has been completely written.
38544 * When writing a command completion or response to an internal
38545 * processor, the order of writes has to be such that this field is
38551 /***************************************
38552 * hwrm_cfa_redirect_tunnel_type_alloc *
38553 ***************************************/
38556 /* hwrm_cfa_redirect_tunnel_type_alloc_input (size:192b/24B) */
38557 struct hwrm_cfa_redirect_tunnel_type_alloc_input {
38558 /* The HWRM command request type. */
38561 * The completion ring to send the completion event on. This should
38562 * be the NQ ID returned from the `nq_alloc` HWRM command.
38564 uint16_t cmpl_ring;
38566 * The sequence ID is used by the driver for tracking multiple
38567 * commands. This ID is treated as opaque data by the firmware and
38568 * the value is returned in the `hwrm_resp_hdr` upon completion.
38572 * The target ID of the command:
38573 * * 0x0-0xFFF8 - The function ID
38574 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
38575 * * 0xFFFD - Reserved for user-space HWRM interface
38578 uint16_t target_id;
38580 * A physical address pointer pointing to a host buffer that the
38581 * command's response data will be written. This can be either a host
38582 * physical address (HPA) or a guest physical address (GPA) and must
38583 * point to a physically contiguous block of memory.
38585 uint64_t resp_addr;
38586 /* The destination function id, to whom the traffic is redirected. */
38589 uint8_t tunnel_type;
38591 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_ALLOC_INPUT_TUNNEL_TYPE_NONTUNNEL \
38593 /* Virtual eXtensible Local Area Network (VXLAN) */
38594 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_ALLOC_INPUT_TUNNEL_TYPE_VXLAN \
38596 /* Network Virtualization Generic Routing Encapsulation (NVGRE) */
38597 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_ALLOC_INPUT_TUNNEL_TYPE_NVGRE \
38599 /* Generic Routing Encapsulation (GRE) inside Ethernet payload */
38600 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_ALLOC_INPUT_TUNNEL_TYPE_L2GRE \
38603 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_ALLOC_INPUT_TUNNEL_TYPE_IPIP \
38605 /* Generic Network Virtualization Encapsulation (Geneve) */
38606 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_ALLOC_INPUT_TUNNEL_TYPE_GENEVE \
38608 /* Multi-Protocol Label Switching (MPLS) */
38609 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_ALLOC_INPUT_TUNNEL_TYPE_MPLS \
38611 /* Stateless Transport Tunnel (STT) */
38612 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_ALLOC_INPUT_TUNNEL_TYPE_STT \
38614 /* Generic Routing Encapsulation (GRE) inside IP datagram payload */
38615 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_ALLOC_INPUT_TUNNEL_TYPE_IPGRE \
38617 /* IPV4 over virtual eXtensible Local Area Network (IPV4oVXLAN) */
38618 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_ALLOC_INPUT_TUNNEL_TYPE_VXLAN_V4 \
38621 * Enhance Generic Routing Encapsulation (GRE version 1) inside IP
38624 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_ALLOC_INPUT_TUNNEL_TYPE_IPGRE_V1 \
38626 /* Use fixed layer 2 ether type of 0xFFFF */
38627 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_ALLOC_INPUT_TUNNEL_TYPE_L2_ETYPE \
38630 * IPV6 over virtual eXtensible Local Area Network with GPE header
38633 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_ALLOC_INPUT_TUNNEL_TYPE_VXLAN_GPE_V6 \
38635 /* Any tunneled traffic */
38636 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_ALLOC_INPUT_TUNNEL_TYPE_ANYTUNNEL \
38638 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_ALLOC_INPUT_TUNNEL_TYPE_LAST \
38639 HWRM_CFA_REDIRECT_TUNNEL_TYPE_ALLOC_INPUT_TUNNEL_TYPE_ANYTUNNEL
38640 /* Tunnel alloc flags. */
38643 * Setting of this flag indicates modify existing redirect tunnel
38644 * to new destination function ID.
38646 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_ALLOC_INPUT_FLAGS_MODIFY_DST \
38648 uint8_t unused_0[4];
38651 /* hwrm_cfa_redirect_tunnel_type_alloc_output (size:128b/16B) */
38652 struct hwrm_cfa_redirect_tunnel_type_alloc_output {
38653 /* The specific error status for the command. */
38654 uint16_t error_code;
38655 /* The HWRM command request type. */
38657 /* The sequence ID from the original command. */
38659 /* The length of the response data in number of bytes. */
38661 uint8_t unused_0[7];
38663 * This field is used in Output records to indicate that the output
38664 * is completely written to RAM. This field should be read as '1'
38665 * to indicate that the output has been completely written.
38666 * When writing a command completion or response to an internal
38667 * processor, the order of writes has to be such that this field is
38673 /**************************************
38674 * hwrm_cfa_redirect_tunnel_type_free *
38675 **************************************/
38678 /* hwrm_cfa_redirect_tunnel_type_free_input (size:192b/24B) */
38679 struct hwrm_cfa_redirect_tunnel_type_free_input {
38680 /* The HWRM command request type. */
38683 * The completion ring to send the completion event on. This should
38684 * be the NQ ID returned from the `nq_alloc` HWRM command.
38686 uint16_t cmpl_ring;
38688 * The sequence ID is used by the driver for tracking multiple
38689 * commands. This ID is treated as opaque data by the firmware and
38690 * the value is returned in the `hwrm_resp_hdr` upon completion.
38694 * The target ID of the command:
38695 * * 0x0-0xFFF8 - The function ID
38696 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
38697 * * 0xFFFD - Reserved for user-space HWRM interface
38700 uint16_t target_id;
38702 * A physical address pointer pointing to a host buffer that the
38703 * command's response data will be written. This can be either a host
38704 * physical address (HPA) or a guest physical address (GPA) and must
38705 * point to a physically contiguous block of memory.
38707 uint64_t resp_addr;
38708 /* The destination function id, to whom the traffic is redirected. */
38711 uint8_t tunnel_type;
38713 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_FREE_INPUT_TUNNEL_TYPE_NONTUNNEL \
38715 /* Virtual eXtensible Local Area Network (VXLAN) */
38716 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_FREE_INPUT_TUNNEL_TYPE_VXLAN \
38718 /* Network Virtualization Generic Routing Encapsulation (NVGRE) */
38719 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_FREE_INPUT_TUNNEL_TYPE_NVGRE \
38721 /* Generic Routing Encapsulation (GRE) inside Ethernet payload */
38722 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_FREE_INPUT_TUNNEL_TYPE_L2GRE \
38725 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_FREE_INPUT_TUNNEL_TYPE_IPIP \
38727 /* Generic Network Virtualization Encapsulation (Geneve) */
38728 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_FREE_INPUT_TUNNEL_TYPE_GENEVE \
38730 /* Multi-Protocol Label Switching (MPLS) */
38731 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_FREE_INPUT_TUNNEL_TYPE_MPLS \
38733 /* Stateless Transport Tunnel (STT) */
38734 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_FREE_INPUT_TUNNEL_TYPE_STT \
38736 /* Generic Routing Encapsulation (GRE) inside IP datagram payload */
38737 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_FREE_INPUT_TUNNEL_TYPE_IPGRE \
38739 /* IPV4 over virtual eXtensible Local Area Network (IPV4oVXLAN) */
38740 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_FREE_INPUT_TUNNEL_TYPE_VXLAN_V4 \
38743 * Enhance Generic Routing Encapsulation (GRE version 1) inside IP
38746 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_FREE_INPUT_TUNNEL_TYPE_IPGRE_V1 \
38748 /* Use fixed layer 2 ether type of 0xFFFF */
38749 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_FREE_INPUT_TUNNEL_TYPE_L2_ETYPE \
38752 * IPV6 over virtual eXtensible Local Area Network with GPE header
38755 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_FREE_INPUT_TUNNEL_TYPE_VXLAN_GPE_V6 \
38757 /* Any tunneled traffic */
38758 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_FREE_INPUT_TUNNEL_TYPE_ANYTUNNEL \
38760 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_FREE_INPUT_TUNNEL_TYPE_LAST \
38761 HWRM_CFA_REDIRECT_TUNNEL_TYPE_FREE_INPUT_TUNNEL_TYPE_ANYTUNNEL
38762 uint8_t unused_0[5];
38765 /* hwrm_cfa_redirect_tunnel_type_free_output (size:128b/16B) */
38766 struct hwrm_cfa_redirect_tunnel_type_free_output {
38767 /* The specific error status for the command. */
38768 uint16_t error_code;
38769 /* The HWRM command request type. */
38771 /* The sequence ID from the original command. */
38773 /* The length of the response data in number of bytes. */
38775 uint8_t unused_0[7];
38777 * This field is used in Output records to indicate that the output
38778 * is completely written to RAM. This field should be read as '1'
38779 * to indicate that the output has been completely written.
38780 * When writing a command completion or response to an internal
38781 * processor, the order of writes has to be such that this field is
38787 /**************************************
38788 * hwrm_cfa_redirect_tunnel_type_info *
38789 **************************************/
38792 /* hwrm_cfa_redirect_tunnel_type_info_input (size:192b/24B) */
38793 struct hwrm_cfa_redirect_tunnel_type_info_input {
38794 /* The HWRM command request type. */
38797 * The completion ring to send the completion event on. This should
38798 * be the NQ ID returned from the `nq_alloc` HWRM command.
38800 uint16_t cmpl_ring;
38802 * The sequence ID is used by the driver for tracking multiple
38803 * commands. This ID is treated as opaque data by the firmware and
38804 * the value is returned in the `hwrm_resp_hdr` upon completion.
38808 * The target ID of the command:
38809 * * 0x0-0xFFF8 - The function ID
38810 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
38811 * * 0xFFFD - Reserved for user-space HWRM interface
38814 uint16_t target_id;
38816 * A physical address pointer pointing to a host buffer that the
38817 * command's response data will be written. This can be either a host
38818 * physical address (HPA) or a guest physical address (GPA) and must
38819 * point to a physically contiguous block of memory.
38821 uint64_t resp_addr;
38822 /* The source function id. */
38825 uint8_t tunnel_type;
38827 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_INFO_INPUT_TUNNEL_TYPE_NONTUNNEL \
38829 /* Virtual eXtensible Local Area Network (VXLAN) */
38830 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_INFO_INPUT_TUNNEL_TYPE_VXLAN \
38832 /* Network Virtualization Generic Routing Encapsulation (NVGRE) */
38833 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_INFO_INPUT_TUNNEL_TYPE_NVGRE \
38835 /* Generic Routing Encapsulation (GRE) inside Ethernet payload */
38836 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_INFO_INPUT_TUNNEL_TYPE_L2GRE \
38839 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_INFO_INPUT_TUNNEL_TYPE_IPIP \
38841 /* Generic Network Virtualization Encapsulation (Geneve) */
38842 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_INFO_INPUT_TUNNEL_TYPE_GENEVE \
38844 /* Multi-Protocol Label Switching (MPLS) */
38845 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_INFO_INPUT_TUNNEL_TYPE_MPLS \
38847 /* Stateless Transport Tunnel (STT) */
38848 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_INFO_INPUT_TUNNEL_TYPE_STT \
38850 /* Generic Routing Encapsulation (GRE) inside IP datagram payload */
38851 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_INFO_INPUT_TUNNEL_TYPE_IPGRE \
38853 /* IPV4 over virtual eXtensible Local Area Network (IPV4oVXLAN) */
38854 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_INFO_INPUT_TUNNEL_TYPE_VXLAN_V4 \
38857 * Enhance Generic Routing Encapsulation (GRE version 1) inside IP
38860 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_INFO_INPUT_TUNNEL_TYPE_IPGRE_V1 \
38862 /* Use fixed layer 2 ether type of 0xFFFF */
38863 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_INFO_INPUT_TUNNEL_TYPE_L2_ETYPE \
38866 * IPV6 over virtual eXtensible Local Area Network with GPE header
38869 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_INFO_INPUT_TUNNEL_TYPE_VXLAN_GPE_V6 \
38871 /* Any tunneled traffic */
38872 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_INFO_INPUT_TUNNEL_TYPE_ANYTUNNEL \
38874 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_INFO_INPUT_TUNNEL_TYPE_LAST \
38875 HWRM_CFA_REDIRECT_TUNNEL_TYPE_INFO_INPUT_TUNNEL_TYPE_ANYTUNNEL
38876 uint8_t unused_0[5];
38879 /* hwrm_cfa_redirect_tunnel_type_info_output (size:128b/16B) */
38880 struct hwrm_cfa_redirect_tunnel_type_info_output {
38881 /* The specific error status for the command. */
38882 uint16_t error_code;
38883 /* The HWRM command request type. */
38885 /* The sequence ID from the original command. */
38887 /* The length of the response data in number of bytes. */
38889 /* The destination function id, to whom the traffic is redirected. */
38891 uint8_t unused_0[5];
38893 * This field is used in Output records to indicate that the output
38894 * is completely written to RAM. This field should be read as '1'
38895 * to indicate that the output has been completely written.
38896 * When writing a command completion or response to an internal
38897 * processor, the order of writes has to be such that this field is
38903 /* hwrm_vxlan_ipv4_hdr (size:128b/16B) */
38904 struct hwrm_vxlan_ipv4_hdr {
38905 /* IPv4 version and header length. */
38907 /* IPv4 header length */
38908 #define HWRM_VXLAN_IPV4_HDR_VER_HLEN_HEADER_LENGTH_MASK UINT32_C(0xf)
38909 #define HWRM_VXLAN_IPV4_HDR_VER_HLEN_HEADER_LENGTH_SFT 0
38911 #define HWRM_VXLAN_IPV4_HDR_VER_HLEN_VERSION_MASK UINT32_C(0xf0)
38912 #define HWRM_VXLAN_IPV4_HDR_VER_HLEN_VERSION_SFT 4
38913 /* IPv4 type of service. */
38915 /* IPv4 identification. */
38917 /* IPv4 flags and offset. */
38918 uint16_t flags_frag_offset;
38921 /* IPv4 protocol. */
38923 /* IPv4 source address. */
38924 uint32_t src_ip_addr;
38925 /* IPv4 destination address. */
38926 uint32_t dest_ip_addr;
38929 /* hwrm_vxlan_ipv6_hdr (size:320b/40B) */
38930 struct hwrm_vxlan_ipv6_hdr {
38931 /* IPv6 version, traffic class and flow label. */
38932 uint32_t ver_tc_flow_label;
38933 /* IPv6 version shift */
38934 #define HWRM_VXLAN_IPV6_HDR_VER_TC_FLOW_LABEL_VER_SFT \
38936 /* IPv6 version mask */
38937 #define HWRM_VXLAN_IPV6_HDR_VER_TC_FLOW_LABEL_VER_MASK \
38938 UINT32_C(0xf0000000)
38939 /* IPv6 TC shift */
38940 #define HWRM_VXLAN_IPV6_HDR_VER_TC_FLOW_LABEL_TC_SFT \
38943 #define HWRM_VXLAN_IPV6_HDR_VER_TC_FLOW_LABEL_TC_MASK \
38944 UINT32_C(0xff00000)
38945 /* IPv6 flow label shift */
38946 #define HWRM_VXLAN_IPV6_HDR_VER_TC_FLOW_LABEL_FLOW_LABEL_SFT \
38948 /* IPv6 flow label mask */
38949 #define HWRM_VXLAN_IPV6_HDR_VER_TC_FLOW_LABEL_FLOW_LABEL_MASK \
38951 #define HWRM_VXLAN_IPV6_HDR_VER_TC_FLOW_LABEL_LAST \
38952 HWRM_VXLAN_IPV6_HDR_VER_TC_FLOW_LABEL_FLOW_LABEL_MASK
38953 /* IPv6 payload length. */
38954 uint16_t payload_len;
38955 /* IPv6 next header. */
38959 /* IPv6 source address. */
38960 uint32_t src_ip_addr[4];
38961 /* IPv6 destination address. */
38962 uint32_t dest_ip_addr[4];
38965 /* hwrm_cfa_encap_data_vxlan (size:640b/80B) */
38966 struct hwrm_cfa_encap_data_vxlan {
38967 /* Source MAC address. */
38968 uint8_t src_mac_addr[6];
38971 /* Destination MAC address. */
38972 uint8_t dst_mac_addr[6];
38973 /* Number of VLAN tags. */
38974 uint8_t num_vlan_tags;
38977 /* Outer VLAN TPID. */
38978 uint16_t ovlan_tpid;
38979 /* Outer VLAN TCI. */
38980 uint16_t ovlan_tci;
38981 /* Inner VLAN TPID. */
38982 uint16_t ivlan_tpid;
38983 /* Inner VLAN TCI. */
38984 uint16_t ivlan_tci;
38985 /* L3 header fields. */
38987 /* IP version mask. */
38988 #define HWRM_CFA_ENCAP_DATA_VXLAN_L3_VER_MASK UINT32_C(0xf)
38989 /* IP version 4. */
38990 #define HWRM_CFA_ENCAP_DATA_VXLAN_L3_VER_IPV4 UINT32_C(0x4)
38991 /* IP version 6. */
38992 #define HWRM_CFA_ENCAP_DATA_VXLAN_L3_VER_IPV6 UINT32_C(0x6)
38993 #define HWRM_CFA_ENCAP_DATA_VXLAN_L3_LAST \
38994 HWRM_CFA_ENCAP_DATA_VXLAN_L3_VER_IPV6
38995 /* UDP source port. */
38997 /* UDP destination port. */
38999 /* VXLAN Network Identifier. */
39002 * 3 bytes VXLAN header reserve fields from 1st dword of the VXLAN
39005 uint8_t hdr_rsvd0[3];
39006 /* 1 byte VXLAN header reserve field from 2nd dword of the VXLAN header. */
39008 /* VXLAN header flags field. */
39013 /*******************************
39014 * hwrm_cfa_encap_record_alloc *
39015 *******************************/
39018 /* hwrm_cfa_encap_record_alloc_input (size:832b/104B) */
39019 struct hwrm_cfa_encap_record_alloc_input {
39020 /* The HWRM command request type. */
39023 * The completion ring to send the completion event on. This should
39024 * be the NQ ID returned from the `nq_alloc` HWRM command.
39026 uint16_t cmpl_ring;
39028 * The sequence ID is used by the driver for tracking multiple
39029 * commands. This ID is treated as opaque data by the firmware and
39030 * the value is returned in the `hwrm_resp_hdr` upon completion.
39034 * The target ID of the command:
39035 * * 0x0-0xFFF8 - The function ID
39036 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
39037 * * 0xFFFD - Reserved for user-space HWRM interface
39040 uint16_t target_id;
39042 * A physical address pointer pointing to a host buffer that the
39043 * command's response data will be written. This can be either a host
39044 * physical address (HPA) or a guest physical address (GPA) and must
39045 * point to a physically contiguous block of memory.
39047 uint64_t resp_addr;
39050 * Setting of this flag indicates the applicability to the loopback
39053 #define HWRM_CFA_ENCAP_RECORD_ALLOC_INPUT_FLAGS_LOOPBACK \
39056 * Setting of this flag indicates this encap record is external
39057 * encap record. Resetting of this flag indicates this flag is
39058 * internal encap record and this is the default setting.
39060 #define HWRM_CFA_ENCAP_RECORD_ALLOC_INPUT_FLAGS_EXTERNAL \
39062 /* Encapsulation Type. */
39063 uint8_t encap_type;
39064 /* Virtual eXtensible Local Area Network (VXLAN) */
39065 #define HWRM_CFA_ENCAP_RECORD_ALLOC_INPUT_ENCAP_TYPE_VXLAN \
39067 /* Network Virtualization Generic Routing Encapsulation (NVGRE) */
39068 #define HWRM_CFA_ENCAP_RECORD_ALLOC_INPUT_ENCAP_TYPE_NVGRE \
39070 /* Generic Routing Encapsulation (GRE) after inside Ethernet payload */
39071 #define HWRM_CFA_ENCAP_RECORD_ALLOC_INPUT_ENCAP_TYPE_L2GRE \
39074 #define HWRM_CFA_ENCAP_RECORD_ALLOC_INPUT_ENCAP_TYPE_IPIP \
39076 /* Generic Network Virtualization Encapsulation (Geneve) */
39077 #define HWRM_CFA_ENCAP_RECORD_ALLOC_INPUT_ENCAP_TYPE_GENEVE \
39079 /* Multi-Protocol Label Switching (MPLS) */
39080 #define HWRM_CFA_ENCAP_RECORD_ALLOC_INPUT_ENCAP_TYPE_MPLS \
39083 #define HWRM_CFA_ENCAP_RECORD_ALLOC_INPUT_ENCAP_TYPE_VLAN \
39085 /* Generic Routing Encapsulation (GRE) inside IP datagram payload */
39086 #define HWRM_CFA_ENCAP_RECORD_ALLOC_INPUT_ENCAP_TYPE_IPGRE \
39088 /* IPV4 over virtual eXtensible Local Area Network (IPV4oVXLAN) */
39089 #define HWRM_CFA_ENCAP_RECORD_ALLOC_INPUT_ENCAP_TYPE_VXLAN_V4 \
39092 * Enhance Generic Routing Encapsulation (GRE version 1) inside IP
39095 #define HWRM_CFA_ENCAP_RECORD_ALLOC_INPUT_ENCAP_TYPE_IPGRE_V1 \
39097 /* Use fixed layer 2 ether type of 0xFFFF */
39098 #define HWRM_CFA_ENCAP_RECORD_ALLOC_INPUT_ENCAP_TYPE_L2_ETYPE \
39101 * IPV6 over virtual eXtensible Local Area Network with GPE header
39104 #define HWRM_CFA_ENCAP_RECORD_ALLOC_INPUT_ENCAP_TYPE_VXLAN_GPE_V6 \
39106 #define HWRM_CFA_ENCAP_RECORD_ALLOC_INPUT_ENCAP_TYPE_LAST \
39107 HWRM_CFA_ENCAP_RECORD_ALLOC_INPUT_ENCAP_TYPE_VXLAN_GPE_V6
39108 uint8_t unused_0[3];
39109 /* This value is encap data used for the given encap type. */
39110 uint32_t encap_data[20];
39113 /* hwrm_cfa_encap_record_alloc_output (size:128b/16B) */
39114 struct hwrm_cfa_encap_record_alloc_output {
39115 /* The specific error status for the command. */
39116 uint16_t error_code;
39117 /* The HWRM command request type. */
39119 /* The sequence ID from the original command. */
39121 /* The length of the response data in number of bytes. */
39123 /* This value is an opaque id into CFA data structures. */
39124 uint32_t encap_record_id;
39125 uint8_t unused_0[3];
39127 * This field is used in Output records to indicate that the output
39128 * is completely written to RAM. This field should be read as '1'
39129 * to indicate that the output has been completely written.
39130 * When writing a command completion or response to an internal
39131 * processor, the order of writes has to be such that this field is
39137 /******************************
39138 * hwrm_cfa_encap_record_free *
39139 ******************************/
39142 /* hwrm_cfa_encap_record_free_input (size:192b/24B) */
39143 struct hwrm_cfa_encap_record_free_input {
39144 /* The HWRM command request type. */
39147 * The completion ring to send the completion event on. This should
39148 * be the NQ ID returned from the `nq_alloc` HWRM command.
39150 uint16_t cmpl_ring;
39152 * The sequence ID is used by the driver for tracking multiple
39153 * commands. This ID is treated as opaque data by the firmware and
39154 * the value is returned in the `hwrm_resp_hdr` upon completion.
39158 * The target ID of the command:
39159 * * 0x0-0xFFF8 - The function ID
39160 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
39161 * * 0xFFFD - Reserved for user-space HWRM interface
39164 uint16_t target_id;
39166 * A physical address pointer pointing to a host buffer that the
39167 * command's response data will be written. This can be either a host
39168 * physical address (HPA) or a guest physical address (GPA) and must
39169 * point to a physically contiguous block of memory.
39171 uint64_t resp_addr;
39172 /* This value is an opaque id into CFA data structures. */
39173 uint32_t encap_record_id;
39174 uint8_t unused_0[4];
39177 /* hwrm_cfa_encap_record_free_output (size:128b/16B) */
39178 struct hwrm_cfa_encap_record_free_output {
39179 /* The specific error status for the command. */
39180 uint16_t error_code;
39181 /* The HWRM command request type. */
39183 /* The sequence ID from the original command. */
39185 /* The length of the response data in number of bytes. */
39187 uint8_t unused_0[7];
39189 * This field is used in Output records to indicate that the output
39190 * is completely written to RAM. This field should be read as '1'
39191 * to indicate that the output has been completely written.
39192 * When writing a command completion or response to an internal
39193 * processor, the order of writes has to be such that this field is
39199 /********************************
39200 * hwrm_cfa_ntuple_filter_alloc *
39201 ********************************/
39204 /* hwrm_cfa_ntuple_filter_alloc_input (size:1024b/128B) */
39205 struct hwrm_cfa_ntuple_filter_alloc_input {
39206 /* The HWRM command request type. */
39209 * The completion ring to send the completion event on. This should
39210 * be the NQ ID returned from the `nq_alloc` HWRM command.
39212 uint16_t cmpl_ring;
39214 * The sequence ID is used by the driver for tracking multiple
39215 * commands. This ID is treated as opaque data by the firmware and
39216 * the value is returned in the `hwrm_resp_hdr` upon completion.
39220 * The target ID of the command:
39221 * * 0x0-0xFFF8 - The function ID
39222 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
39223 * * 0xFFFD - Reserved for user-space HWRM interface
39226 uint16_t target_id;
39228 * A physical address pointer pointing to a host buffer that the
39229 * command's response data will be written. This can be either a host
39230 * physical address (HPA) or a guest physical address (GPA) and must
39231 * point to a physically contiguous block of memory.
39233 uint64_t resp_addr;
39236 * Setting of this flag indicates the applicability to the loopback
39239 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_FLAGS_LOOPBACK \
39242 * Setting of this flag indicates drop action. If this flag is not
39243 * set, then it should be considered accept action.
39245 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_FLAGS_DROP \
39248 * Setting of this flag indicates that a meter is expected to be
39249 * attached to this flow. This hint can be used when choosing the
39250 * action record format required for the flow.
39252 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_FLAGS_METER \
39255 * Setting of this flag indicates that the dst_id field contains
39256 * function ID. If this is not set it indicates dest_id is VNIC
39259 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_FLAGS_DEST_FID \
39262 * Setting of this flag indicates match on arp reply when ethertype
39263 * is 0x0806. If this is not set it indicates no specific arp opcode
39266 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_FLAGS_ARP_REPLY \
39269 * Setting of this flag indicates that the dst_id field contains RFS
39270 * ring table index. If this is not set it indicates dst_id is VNIC
39271 * or VPORT or function ID. Note dest_fid and dest_rfs_ring_idx
39272 * can’t be set at the same time.
39274 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_FLAGS_DEST_RFS_RING_IDX \
39277 * Setting of this flag indicates that when the ntuple filter is
39278 * created, the L2 context should not be used in the filter. This
39279 * allows packet from different L2 contexts to match and be directed
39280 * to the same destination.
39282 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_FLAGS_NO_L2_CONTEXT \
39286 * This bit must be '1' for the l2_filter_id field to be
39289 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_L2_FILTER_ID \
39292 * This bit must be '1' for the ethertype field to be
39295 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_ETHERTYPE \
39298 * This bit must be '1' for the tunnel_type field to be
39301 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_TUNNEL_TYPE \
39304 * This bit must be '1' for the src_macaddr field to be
39307 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_SRC_MACADDR \
39310 * This bit must be '1' for the ipaddr_type field to be
39313 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_IPADDR_TYPE \
39316 * This bit must be '1' for the src_ipaddr field to be
39319 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_SRC_IPADDR \
39322 * This bit must be '1' for the src_ipaddr_mask field to be
39325 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_SRC_IPADDR_MASK \
39328 * This bit must be '1' for the dst_ipaddr field to be
39331 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_IPADDR \
39334 * This bit must be '1' for the dst_ipaddr_mask field to be
39337 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_IPADDR_MASK \
39340 * This bit must be '1' for the ip_protocol field to be
39343 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_IP_PROTOCOL \
39346 * This bit must be '1' for the src_port field to be
39349 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_SRC_PORT \
39352 * This bit must be '1' for the src_port_mask field to be
39355 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_SRC_PORT_MASK \
39358 * This bit must be '1' for the dst_port field to be
39361 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_PORT \
39364 * This bit must be '1' for the dst_port_mask field to be
39367 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_PORT_MASK \
39370 * This bit must be '1' for the pri_hint field to be
39373 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_PRI_HINT \
39376 * This bit must be '1' for the ntuple_filter_id field to be
39379 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_NTUPLE_FILTER_ID \
39382 * This bit must be '1' for the dst_id field to be
39385 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_ID \
39388 * This bit must be '1' for the mirror_vnic_id field to be
39391 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_MIRROR_VNIC_ID \
39394 * This bit must be '1' for the dst_macaddr field to be
39397 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_MACADDR \
39399 /* This flag is deprecated. */
39400 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_RFS_RING_TBL_IDX \
39403 * This value identifies a set of CFA data structures used for an L2
39406 uint64_t l2_filter_id;
39408 * This value indicates the source MAC address in
39409 * the Ethernet header.
39411 uint8_t src_macaddr[6];
39412 /* This value indicates the ethertype in the Ethernet header. */
39413 uint16_t ethertype;
39415 * This value indicates the type of IP address.
39418 * All others are invalid.
39420 uint8_t ip_addr_type;
39422 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_IP_ADDR_TYPE_UNKNOWN \
39425 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_IP_ADDR_TYPE_IPV4 \
39428 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_IP_ADDR_TYPE_IPV6 \
39430 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_IP_ADDR_TYPE_LAST \
39431 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_IP_ADDR_TYPE_IPV6
39433 * The value of protocol filed in IP header.
39434 * Applies to UDP and TCP traffic.
39438 uint8_t ip_protocol;
39440 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_IP_PROTOCOL_UNKNOWN \
39443 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_IP_PROTOCOL_TCP \
39446 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_IP_PROTOCOL_UDP \
39448 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_IP_PROTOCOL_LAST \
39449 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_IP_PROTOCOL_UDP
39451 * If set, this value shall represent the
39452 * Logical VNIC ID of the destination VNIC for the RX
39453 * path and network port id of the destination port for
39458 * Logical VNIC ID of the VNIC where traffic is
39461 uint16_t mirror_vnic_id;
39463 * This value indicates the tunnel type for this filter.
39464 * If this field is not specified, then the filter shall
39465 * apply to both non-tunneled and tunneled packets.
39466 * If this field conflicts with the tunnel_type specified
39467 * in the l2_filter_id, then the HWRM shall return an
39468 * error for this command.
39470 uint8_t tunnel_type;
39472 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_TUNNEL_TYPE_NONTUNNEL \
39474 /* Virtual eXtensible Local Area Network (VXLAN) */
39475 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_TUNNEL_TYPE_VXLAN \
39477 /* Network Virtualization Generic Routing Encapsulation (NVGRE) */
39478 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_TUNNEL_TYPE_NVGRE \
39480 /* Generic Routing Encapsulation (GRE) inside Ethernet payload */
39481 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_TUNNEL_TYPE_L2GRE \
39484 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_TUNNEL_TYPE_IPIP \
39486 /* Generic Network Virtualization Encapsulation (Geneve) */
39487 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_TUNNEL_TYPE_GENEVE \
39489 /* Multi-Protocol Label Switching (MPLS) */
39490 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_TUNNEL_TYPE_MPLS \
39492 /* Stateless Transport Tunnel (STT) */
39493 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_TUNNEL_TYPE_STT \
39495 /* Generic Routing Encapsulation (GRE) inside IP datagram payload */
39496 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_TUNNEL_TYPE_IPGRE \
39498 /* IPV4 over virtual eXtensible Local Area Network (IPV4oVXLAN) */
39499 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_TUNNEL_TYPE_VXLAN_V4 \
39502 * Enhance Generic Routing Encapsulation (GRE version 1) inside IP
39505 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_TUNNEL_TYPE_IPGRE_V1 \
39507 /* Use fixed layer 2 ether type of 0xFFFF */
39508 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_TUNNEL_TYPE_L2_ETYPE \
39511 * IPV6 over virtual eXtensible Local Area Network with GPE header
39514 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_TUNNEL_TYPE_VXLAN_GPE_V6 \
39516 /* Any tunneled traffic */
39517 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_TUNNEL_TYPE_ANYTUNNEL \
39519 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_TUNNEL_TYPE_LAST \
39520 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_TUNNEL_TYPE_ANYTUNNEL
39522 * This hint is provided to help in placing
39523 * the filter in the filter table.
39526 /* No preference */
39527 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_PRI_HINT_NO_PREFER \
39529 /* Above the given filter */
39530 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_PRI_HINT_ABOVE \
39532 /* Below the given filter */
39533 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_PRI_HINT_BELOW \
39535 /* As high as possible */
39536 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_PRI_HINT_HIGHEST \
39538 /* As low as possible */
39539 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_PRI_HINT_LOWEST \
39541 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_PRI_HINT_LAST \
39542 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_PRI_HINT_LOWEST
39544 * The value of source IP address to be used in filtering.
39545 * For IPv4, first four bytes represent the IP address.
39547 uint32_t src_ipaddr[4];
39549 * The value of source IP address mask to be used in
39551 * For IPv4, first four bytes represent the IP address mask.
39553 uint32_t src_ipaddr_mask[4];
39555 * The value of destination IP address to be used in filtering.
39556 * For IPv4, first four bytes represent the IP address.
39558 uint32_t dst_ipaddr[4];
39560 * The value of destination IP address mask to be used in
39562 * For IPv4, first four bytes represent the IP address mask.
39564 uint32_t dst_ipaddr_mask[4];
39566 * The value of source port to be used in filtering.
39567 * Applies to UDP and TCP traffic.
39571 * The value of source port mask to be used in filtering.
39572 * Applies to UDP and TCP traffic.
39574 uint16_t src_port_mask;
39576 * The value of destination port to be used in filtering.
39577 * Applies to UDP and TCP traffic.
39581 * The value of destination port mask to be used in
39583 * Applies to UDP and TCP traffic.
39585 uint16_t dst_port_mask;
39587 * This is the ID of the filter that goes along with
39590 uint64_t ntuple_filter_id_hint;
39593 /* hwrm_cfa_ntuple_filter_alloc_output (size:192b/24B) */
39594 struct hwrm_cfa_ntuple_filter_alloc_output {
39595 /* The specific error status for the command. */
39596 uint16_t error_code;
39597 /* The HWRM command request type. */
39599 /* The sequence ID from the original command. */
39601 /* The length of the response data in number of bytes. */
39603 /* This value is an opaque id into CFA data structures. */
39604 uint64_t ntuple_filter_id;
39606 * The flow id value in bit 0-29 is the actual ID of the flow
39607 * associated with this filter and it shall be used to match
39608 * and associate the flow identifier returned in completion
39609 * records. A value of 0xFFFFFFFF in the 32-bit flow_id field
39610 * shall indicate no valid flow id.
39613 /* Indicate the flow id value. */
39614 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_OUTPUT_FLOW_ID_VALUE_MASK \
39615 UINT32_C(0x3fffffff)
39616 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_OUTPUT_FLOW_ID_VALUE_SFT 0
39617 /* Indicate type of the flow. */
39618 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_OUTPUT_FLOW_ID_TYPE \
39619 UINT32_C(0x40000000)
39621 * If this bit set to 0, then it indicates that the flow is
39624 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_OUTPUT_FLOW_ID_TYPE_INT \
39625 (UINT32_C(0x0) << 30)
39627 * If this bit is set to 1, then it indicates that the flow is
39630 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_OUTPUT_FLOW_ID_TYPE_EXT \
39631 (UINT32_C(0x1) << 30)
39632 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_OUTPUT_FLOW_ID_TYPE_LAST \
39633 HWRM_CFA_NTUPLE_FILTER_ALLOC_OUTPUT_FLOW_ID_TYPE_EXT
39634 /* Indicate the flow direction. */
39635 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_OUTPUT_FLOW_ID_DIR \
39636 UINT32_C(0x80000000)
39637 /* If this bit set to 0, then it indicates rx flow. */
39638 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_OUTPUT_FLOW_ID_DIR_RX \
39639 (UINT32_C(0x0) << 31)
39640 /* If this bit is set to 1, then it indicates that tx flow. */
39641 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_OUTPUT_FLOW_ID_DIR_TX \
39642 (UINT32_C(0x1) << 31)
39643 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_OUTPUT_FLOW_ID_DIR_LAST \
39644 HWRM_CFA_NTUPLE_FILTER_ALLOC_OUTPUT_FLOW_ID_DIR_TX
39645 uint8_t unused_0[3];
39647 * This field is used in Output records to indicate that the output
39648 * is completely written to RAM. This field should be read as '1'
39649 * to indicate that the output has been completely written.
39650 * When writing a command completion or response to an internal
39651 * processor, the order of writes has to be such that this field is
39657 /* hwrm_cfa_ntuple_filter_alloc_cmd_err (size:64b/8B) */
39658 struct hwrm_cfa_ntuple_filter_alloc_cmd_err {
39660 * command specific error codes that goes to
39661 * the cmd_err field in Common HWRM Error Response.
39664 /* Unknown error */
39665 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_CMD_ERR_CODE_UNKNOWN \
39667 /* Unable to complete operation due to conflict with Rx Mask VLAN */
39668 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_CMD_ERR_CODE_RX_MASK_VLAN_CONFLICT_ERR \
39670 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_CMD_ERR_CODE_LAST \
39671 HWRM_CFA_NTUPLE_FILTER_ALLOC_CMD_ERR_CODE_RX_MASK_VLAN_CONFLICT_ERR
39672 uint8_t unused_0[7];
39675 /*******************************
39676 * hwrm_cfa_ntuple_filter_free *
39677 *******************************/
39680 /* hwrm_cfa_ntuple_filter_free_input (size:192b/24B) */
39681 struct hwrm_cfa_ntuple_filter_free_input {
39682 /* The HWRM command request type. */
39685 * The completion ring to send the completion event on. This should
39686 * be the NQ ID returned from the `nq_alloc` HWRM command.
39688 uint16_t cmpl_ring;
39690 * The sequence ID is used by the driver for tracking multiple
39691 * commands. This ID is treated as opaque data by the firmware and
39692 * the value is returned in the `hwrm_resp_hdr` upon completion.
39696 * The target ID of the command:
39697 * * 0x0-0xFFF8 - The function ID
39698 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
39699 * * 0xFFFD - Reserved for user-space HWRM interface
39702 uint16_t target_id;
39704 * A physical address pointer pointing to a host buffer that the
39705 * command's response data will be written. This can be either a host
39706 * physical address (HPA) or a guest physical address (GPA) and must
39707 * point to a physically contiguous block of memory.
39709 uint64_t resp_addr;
39710 /* This value is an opaque id into CFA data structures. */
39711 uint64_t ntuple_filter_id;
39714 /* hwrm_cfa_ntuple_filter_free_output (size:128b/16B) */
39715 struct hwrm_cfa_ntuple_filter_free_output {
39716 /* The specific error status for the command. */
39717 uint16_t error_code;
39718 /* The HWRM command request type. */
39720 /* The sequence ID from the original command. */
39722 /* The length of the response data in number of bytes. */
39724 uint8_t unused_0[7];
39726 * This field is used in Output records to indicate that the output
39727 * is completely written to RAM. This field should be read as '1'
39728 * to indicate that the output has been completely written.
39729 * When writing a command completion or response to an internal
39730 * processor, the order of writes has to be such that this field is
39736 /******************************
39737 * hwrm_cfa_ntuple_filter_cfg *
39738 ******************************/
39741 /* hwrm_cfa_ntuple_filter_cfg_input (size:384b/48B) */
39742 struct hwrm_cfa_ntuple_filter_cfg_input {
39743 /* The HWRM command request type. */
39746 * The completion ring to send the completion event on. This should
39747 * be the NQ ID returned from the `nq_alloc` HWRM command.
39749 uint16_t cmpl_ring;
39751 * The sequence ID is used by the driver for tracking multiple
39752 * commands. This ID is treated as opaque data by the firmware and
39753 * the value is returned in the `hwrm_resp_hdr` upon completion.
39757 * The target ID of the command:
39758 * * 0x0-0xFFF8 - The function ID
39759 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
39760 * * 0xFFFD - Reserved for user-space HWRM interface
39763 uint16_t target_id;
39765 * A physical address pointer pointing to a host buffer that the
39766 * command's response data will be written. This can be either a host
39767 * physical address (HPA) or a guest physical address (GPA) and must
39768 * point to a physically contiguous block of memory.
39770 uint64_t resp_addr;
39773 * This bit must be '1' for the new_dst_id field to be
39776 #define HWRM_CFA_NTUPLE_FILTER_CFG_INPUT_ENABLES_NEW_DST_ID \
39779 * This bit must be '1' for the new_mirror_vnic_id field to be
39782 #define HWRM_CFA_NTUPLE_FILTER_CFG_INPUT_ENABLES_NEW_MIRROR_VNIC_ID \
39785 * This bit must be '1' for the new_meter_instance_id field to be
39788 #define HWRM_CFA_NTUPLE_FILTER_CFG_INPUT_ENABLES_NEW_METER_INSTANCE_ID \
39792 * Setting this bit to 1 indicates that dest_id field contains FID.
39793 * Setting this to 0 indicates that dest_id field contains VNIC or
39796 #define HWRM_CFA_NTUPLE_FILTER_CFG_INPUT_FLAGS_DEST_FID \
39799 * Setting of this flag indicates that the new_dst_id field contains
39800 * RFS ring table index. If this is not set it indicates new_dst_id
39801 * is VNIC or VPORT or function ID. Note dest_fid and
39802 * dest_rfs_ring_idx can’t be set at the same time.
39804 #define HWRM_CFA_NTUPLE_FILTER_CFG_INPUT_FLAGS_DEST_RFS_RING_IDX \
39807 * Setting of this flag indicates that when the ntuple filter is
39808 * created, the L2 context should not be used in the filter. This
39809 * allows packet from different L2 contexts to match and be directed
39810 * to the same destination.
39812 #define HWRM_CFA_NTUPLE_FILTER_CFG_INPUT_FLAGS_NO_L2_CONTEXT \
39814 /* This value is an opaque id into CFA data structures. */
39815 uint64_t ntuple_filter_id;
39817 * If set, this value shall represent the new
39818 * Logical VNIC ID of the destination VNIC for the RX
39819 * path and new network port id of the destination port for
39822 uint32_t new_dst_id;
39824 * New Logical VNIC ID of the VNIC where traffic is
39827 uint32_t new_mirror_vnic_id;
39829 * New meter to attach to the flow. Specifying the
39830 * invalid instance ID is used to remove any existing
39831 * meter from the flow.
39833 uint16_t new_meter_instance_id;
39835 * A value of 0xfff is considered invalid and implies the
39836 * instance is not configured.
39838 #define HWRM_CFA_NTUPLE_FILTER_CFG_INPUT_NEW_METER_INSTANCE_ID_INVALID \
39840 #define HWRM_CFA_NTUPLE_FILTER_CFG_INPUT_NEW_METER_INSTANCE_ID_LAST \
39841 HWRM_CFA_NTUPLE_FILTER_CFG_INPUT_NEW_METER_INSTANCE_ID_INVALID
39842 uint8_t unused_1[6];
39845 /* hwrm_cfa_ntuple_filter_cfg_output (size:128b/16B) */
39846 struct hwrm_cfa_ntuple_filter_cfg_output {
39847 /* The specific error status for the command. */
39848 uint16_t error_code;
39849 /* The HWRM command request type. */
39851 /* The sequence ID from the original command. */
39853 /* The length of the response data in number of bytes. */
39855 uint8_t unused_0[7];
39857 * This field is used in Output records to indicate that the output
39858 * is completely written to RAM. This field should be read as '1'
39859 * to indicate that the output has been completely written.
39860 * When writing a command completion or response to an internal
39861 * processor, the order of writes has to be such that this field is
39867 /**************************
39868 * hwrm_cfa_em_flow_alloc *
39869 **************************/
39872 /* hwrm_cfa_em_flow_alloc_input (size:896b/112B) */
39873 struct hwrm_cfa_em_flow_alloc_input {
39874 /* The HWRM command request type. */
39877 * The completion ring to send the completion event on. This should
39878 * be the NQ ID returned from the `nq_alloc` HWRM command.
39880 uint16_t cmpl_ring;
39882 * The sequence ID is used by the driver for tracking multiple
39883 * commands. This ID is treated as opaque data by the firmware and
39884 * the value is returned in the `hwrm_resp_hdr` upon completion.
39888 * The target ID of the command:
39889 * * 0x0-0xFFF8 - The function ID
39890 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
39891 * * 0xFFFD - Reserved for user-space HWRM interface
39894 uint16_t target_id;
39896 * A physical address pointer pointing to a host buffer that the
39897 * command's response data will be written. This can be either a host
39898 * physical address (HPA) or a guest physical address (GPA) and must
39899 * point to a physically contiguous block of memory.
39901 uint64_t resp_addr;
39904 * Enumeration denoting the RX, TX type of the resource.
39905 * This enumeration is used for resources that are similar for both
39906 * TX and RX paths of the chip.
39908 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_FLAGS_PATH UINT32_C(0x1)
39910 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_FLAGS_PATH_TX UINT32_C(0x0)
39912 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_FLAGS_PATH_RX UINT32_C(0x1)
39913 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_FLAGS_PATH_LAST \
39914 HWRM_CFA_EM_FLOW_ALLOC_INPUT_FLAGS_PATH_RX
39916 * Setting of this flag indicates enabling of a byte counter for a
39919 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_FLAGS_BYTE_CTR UINT32_C(0x2)
39921 * Setting of this flag indicates enabling of a packet counter for a
39924 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_FLAGS_PKT_CTR UINT32_C(0x4)
39926 * Setting of this flag indicates de-capsulation action for the
39929 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_FLAGS_DECAP UINT32_C(0x8)
39931 * Setting of this flag indicates encapsulation action for the
39934 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_FLAGS_ENCAP UINT32_C(0x10)
39936 * Setting of this flag indicates drop action. If this flag is not
39937 * set, then it should be considered accept action.
39939 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_FLAGS_DROP UINT32_C(0x20)
39941 * Setting of this flag indicates that a meter is expected to be
39942 * attached to this flow. This hint can be used when choosing the
39943 * action record format required for the flow.
39945 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_FLAGS_METER UINT32_C(0x40)
39948 * This bit must be '1' for the l2_filter_id field to be
39951 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_L2_FILTER_ID \
39954 * This bit must be '1' for the tunnel_type field to be
39957 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_TUNNEL_TYPE \
39960 * This bit must be '1' for the tunnel_id field to be
39963 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_TUNNEL_ID \
39966 * This bit must be '1' for the src_macaddr field to be
39969 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_SRC_MACADDR \
39972 * This bit must be '1' for the dst_macaddr field to be
39975 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_DST_MACADDR \
39978 * This bit must be '1' for the ovlan_vid field to be
39981 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_OVLAN_VID \
39984 * This bit must be '1' for the ivlan_vid field to be
39987 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_IVLAN_VID \
39990 * This bit must be '1' for the ethertype field to be
39993 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_ETHERTYPE \
39996 * This bit must be '1' for the src_ipaddr field to be
39999 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_SRC_IPADDR \
40002 * This bit must be '1' for the dst_ipaddr field to be
40005 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_DST_IPADDR \
40008 * This bit must be '1' for the ipaddr_type field to be
40011 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_IPADDR_TYPE \
40014 * This bit must be '1' for the ip_protocol field to be
40017 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_IP_PROTOCOL \
40020 * This bit must be '1' for the src_port field to be
40023 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_SRC_PORT \
40026 * This bit must be '1' for the dst_port field to be
40029 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_DST_PORT \
40032 * This bit must be '1' for the dst_id field to be
40035 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_DST_ID \
40038 * This bit must be '1' for the mirror_vnic_id field to be
40041 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_MIRROR_VNIC_ID \
40044 * This bit must be '1' for the encap_record_id field to be
40047 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_ENCAP_RECORD_ID \
40050 * This bit must be '1' for the meter_instance_id field to be
40053 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_METER_INSTANCE_ID \
40056 * This value identifies a set of CFA data structures used for an L2
40059 uint64_t l2_filter_id;
40061 uint8_t tunnel_type;
40063 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_TUNNEL_TYPE_NONTUNNEL \
40065 /* Virtual eXtensible Local Area Network (VXLAN) */
40066 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_TUNNEL_TYPE_VXLAN \
40068 /* Network Virtualization Generic Routing Encapsulation (NVGRE) */
40069 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_TUNNEL_TYPE_NVGRE \
40071 /* Generic Routing Encapsulation (GRE) inside Ethernet payload */
40072 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_TUNNEL_TYPE_L2GRE \
40075 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_TUNNEL_TYPE_IPIP \
40077 /* Generic Network Virtualization Encapsulation (Geneve) */
40078 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_TUNNEL_TYPE_GENEVE \
40080 /* Multi-Protocol Label Switching (MPLS) */
40081 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_TUNNEL_TYPE_MPLS \
40083 /* Stateless Transport Tunnel (STT) */
40084 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_TUNNEL_TYPE_STT \
40086 /* Generic Routing Encapsulation (GRE) inside IP datagram payload */
40087 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_TUNNEL_TYPE_IPGRE \
40089 /* IPV4 over virtual eXtensible Local Area Network (IPV4oVXLAN) */
40090 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_TUNNEL_TYPE_VXLAN_V4 \
40093 * Enhance Generic Routing Encapsulation (GRE version 1) inside IP
40096 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_TUNNEL_TYPE_IPGRE_V1 \
40098 /* Use fixed layer 2 ether type of 0xFFFF */
40099 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_TUNNEL_TYPE_L2_ETYPE \
40102 * IPV6 over virtual eXtensible Local Area Network with GPE header
40105 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_TUNNEL_TYPE_VXLAN_GPE_V6 \
40107 /* Any tunneled traffic */
40108 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_TUNNEL_TYPE_ANYTUNNEL \
40110 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_TUNNEL_TYPE_LAST \
40111 HWRM_CFA_EM_FLOW_ALLOC_INPUT_TUNNEL_TYPE_ANYTUNNEL
40112 uint8_t unused_0[3];
40114 * Tunnel identifier.
40115 * Virtual Network Identifier (VNI). Only valid with
40116 * tunnel_types VXLAN, NVGRE, and Geneve.
40117 * Only lower 24-bits of VNI field are used
40118 * in setting up the filter.
40120 uint32_t tunnel_id;
40122 * This value indicates the source MAC address in
40123 * the Ethernet header.
40125 uint8_t src_macaddr[6];
40126 /* The meter instance to attach to the flow. */
40127 uint16_t meter_instance_id;
40129 * A value of 0xfff is considered invalid and implies the
40130 * instance is not configured.
40132 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_METER_INSTANCE_ID_INVALID \
40134 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_METER_INSTANCE_ID_LAST \
40135 HWRM_CFA_EM_FLOW_ALLOC_INPUT_METER_INSTANCE_ID_INVALID
40137 * This value indicates the destination MAC address in
40138 * the Ethernet header.
40140 uint8_t dst_macaddr[6];
40142 * This value indicates the VLAN ID of the outer VLAN tag
40143 * in the Ethernet header.
40145 uint16_t ovlan_vid;
40147 * This value indicates the VLAN ID of the inner VLAN tag
40148 * in the Ethernet header.
40150 uint16_t ivlan_vid;
40151 /* This value indicates the ethertype in the Ethernet header. */
40152 uint16_t ethertype;
40154 * This value indicates the type of IP address.
40157 * All others are invalid.
40159 uint8_t ip_addr_type;
40161 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_IP_ADDR_TYPE_UNKNOWN UINT32_C(0x0)
40163 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_IP_ADDR_TYPE_IPV4 UINT32_C(0x4)
40165 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_IP_ADDR_TYPE_IPV6 UINT32_C(0x6)
40166 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_IP_ADDR_TYPE_LAST \
40167 HWRM_CFA_EM_FLOW_ALLOC_INPUT_IP_ADDR_TYPE_IPV6
40169 * The value of protocol filed in IP header.
40170 * Applies to UDP and TCP traffic.
40174 uint8_t ip_protocol;
40176 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_IP_PROTOCOL_UNKNOWN UINT32_C(0x0)
40178 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_IP_PROTOCOL_TCP UINT32_C(0x6)
40180 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_IP_PROTOCOL_UDP UINT32_C(0x11)
40181 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_IP_PROTOCOL_LAST \
40182 HWRM_CFA_EM_FLOW_ALLOC_INPUT_IP_PROTOCOL_UDP
40183 uint8_t unused_1[2];
40185 * The value of source IP address to be used in filtering.
40186 * For IPv4, first four bytes represent the IP address.
40188 uint32_t src_ipaddr[4];
40190 * big_endian = True
40191 * The value of destination IP address to be used in filtering.
40192 * For IPv4, first four bytes represent the IP address.
40194 uint32_t dst_ipaddr[4];
40196 * The value of source port to be used in filtering.
40197 * Applies to UDP and TCP traffic.
40201 * The value of destination port to be used in filtering.
40202 * Applies to UDP and TCP traffic.
40206 * If set, this value shall represent the
40207 * Logical VNIC ID of the destination VNIC for the RX
40208 * path and network port id of the destination port for
40213 * Logical VNIC ID of the VNIC where traffic is
40216 uint16_t mirror_vnic_id;
40217 /* Logical ID of the encapsulation record. */
40218 uint32_t encap_record_id;
40219 uint8_t unused_2[4];
40222 /* hwrm_cfa_em_flow_alloc_output (size:192b/24B) */
40223 struct hwrm_cfa_em_flow_alloc_output {
40224 /* The specific error status for the command. */
40225 uint16_t error_code;
40226 /* The HWRM command request type. */
40228 /* The sequence ID from the original command. */
40230 /* The length of the response data in number of bytes. */
40232 /* This value is an opaque id into CFA data structures. */
40233 uint64_t em_filter_id;
40235 * The flow id value in bit 0-29 is the actual ID of the flow
40236 * associated with this filter and it shall be used to match
40237 * and associate the flow identifier returned in completion
40238 * records. A value of 0xFFFFFFFF in the 32-bit flow_id field
40239 * shall indicate no valid flow id.
40242 /* Indicate the flow id value. */
40243 #define HWRM_CFA_EM_FLOW_ALLOC_OUTPUT_FLOW_ID_VALUE_MASK \
40244 UINT32_C(0x3fffffff)
40245 #define HWRM_CFA_EM_FLOW_ALLOC_OUTPUT_FLOW_ID_VALUE_SFT 0
40246 /* Indicate type of the flow. */
40247 #define HWRM_CFA_EM_FLOW_ALLOC_OUTPUT_FLOW_ID_TYPE \
40248 UINT32_C(0x40000000)
40250 * If this bit set to 0, then it indicates that the flow is
40253 #define HWRM_CFA_EM_FLOW_ALLOC_OUTPUT_FLOW_ID_TYPE_INT \
40254 (UINT32_C(0x0) << 30)
40256 * If this bit is set to 1, then it indicates that the flow is
40259 #define HWRM_CFA_EM_FLOW_ALLOC_OUTPUT_FLOW_ID_TYPE_EXT \
40260 (UINT32_C(0x1) << 30)
40261 #define HWRM_CFA_EM_FLOW_ALLOC_OUTPUT_FLOW_ID_TYPE_LAST \
40262 HWRM_CFA_EM_FLOW_ALLOC_OUTPUT_FLOW_ID_TYPE_EXT
40263 /* Indicate the flow direction. */
40264 #define HWRM_CFA_EM_FLOW_ALLOC_OUTPUT_FLOW_ID_DIR \
40265 UINT32_C(0x80000000)
40266 /* If this bit set to 0, then it indicates rx flow. */
40267 #define HWRM_CFA_EM_FLOW_ALLOC_OUTPUT_FLOW_ID_DIR_RX \
40268 (UINT32_C(0x0) << 31)
40269 /* If this bit is set to 1, then it indicates that tx flow. */
40270 #define HWRM_CFA_EM_FLOW_ALLOC_OUTPUT_FLOW_ID_DIR_TX \
40271 (UINT32_C(0x1) << 31)
40272 #define HWRM_CFA_EM_FLOW_ALLOC_OUTPUT_FLOW_ID_DIR_LAST \
40273 HWRM_CFA_EM_FLOW_ALLOC_OUTPUT_FLOW_ID_DIR_TX
40274 uint8_t unused_0[3];
40276 * This field is used in Output records to indicate that the output
40277 * is completely written to RAM. This field should be read as '1'
40278 * to indicate that the output has been completely written.
40279 * When writing a command completion or response to an internal
40280 * processor, the order of writes has to be such that this field is
40286 /*************************
40287 * hwrm_cfa_em_flow_free *
40288 *************************/
40291 /* hwrm_cfa_em_flow_free_input (size:192b/24B) */
40292 struct hwrm_cfa_em_flow_free_input {
40293 /* The HWRM command request type. */
40296 * The completion ring to send the completion event on. This should
40297 * be the NQ ID returned from the `nq_alloc` HWRM command.
40299 uint16_t cmpl_ring;
40301 * The sequence ID is used by the driver for tracking multiple
40302 * commands. This ID is treated as opaque data by the firmware and
40303 * the value is returned in the `hwrm_resp_hdr` upon completion.
40307 * The target ID of the command:
40308 * * 0x0-0xFFF8 - The function ID
40309 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
40310 * * 0xFFFD - Reserved for user-space HWRM interface
40313 uint16_t target_id;
40315 * A physical address pointer pointing to a host buffer that the
40316 * command's response data will be written. This can be either a host
40317 * physical address (HPA) or a guest physical address (GPA) and must
40318 * point to a physically contiguous block of memory.
40320 uint64_t resp_addr;
40321 /* This value is an opaque id into CFA data structures. */
40322 uint64_t em_filter_id;
40325 /* hwrm_cfa_em_flow_free_output (size:128b/16B) */
40326 struct hwrm_cfa_em_flow_free_output {
40327 /* The specific error status for the command. */
40328 uint16_t error_code;
40329 /* The HWRM command request type. */
40331 /* The sequence ID from the original command. */
40333 /* The length of the response data in number of bytes. */
40335 uint8_t unused_0[7];
40337 * This field is used in Output records to indicate that the output
40338 * is completely written to RAM. This field should be read as '1'
40339 * to indicate that the output has been completely written.
40340 * When writing a command completion or response to an internal
40341 * processor, the order of writes has to be such that this field is
40347 /************************
40348 * hwrm_cfa_meter_qcaps *
40349 ************************/
40352 /* hwrm_cfa_meter_qcaps_input (size:128b/16B) */
40353 struct hwrm_cfa_meter_qcaps_input {
40354 /* The HWRM command request type. */
40357 * The completion ring to send the completion event on. This should
40358 * be the NQ ID returned from the `nq_alloc` HWRM command.
40360 uint16_t cmpl_ring;
40362 * The sequence ID is used by the driver for tracking multiple
40363 * commands. This ID is treated as opaque data by the firmware and
40364 * the value is returned in the `hwrm_resp_hdr` upon completion.
40368 * The target ID of the command:
40369 * * 0x0-0xFFF8 - The function ID
40370 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
40371 * * 0xFFFD - Reserved for user-space HWRM interface
40374 uint16_t target_id;
40376 * A physical address pointer pointing to a host buffer that the
40377 * command's response data will be written. This can be either a host
40378 * physical address (HPA) or a guest physical address (GPA) and must
40379 * point to a physically contiguous block of memory.
40381 uint64_t resp_addr;
40384 /* hwrm_cfa_meter_qcaps_output (size:320b/40B) */
40385 struct hwrm_cfa_meter_qcaps_output {
40386 /* The specific error status for the command. */
40387 uint16_t error_code;
40388 /* The HWRM command request type. */
40390 /* The sequence ID from the original command. */
40392 /* The length of the response data in number of bytes. */
40396 * Enumeration denoting the clock at which the Meter is running
40397 * with. This enumeration is used for resources that are similar
40398 * for both TX and RX paths of the chip.
40400 #define HWRM_CFA_METER_QCAPS_OUTPUT_FLAGS_CLOCK_MASK UINT32_C(0xf)
40401 #define HWRM_CFA_METER_QCAPS_OUTPUT_FLAGS_CLOCK_SFT 0
40403 #define HWRM_CFA_METER_QCAPS_OUTPUT_FLAGS_CLOCK_375MHZ UINT32_C(0x0)
40405 #define HWRM_CFA_METER_QCAPS_OUTPUT_FLAGS_CLOCK_625MHZ UINT32_C(0x1)
40406 #define HWRM_CFA_METER_QCAPS_OUTPUT_FLAGS_CLOCK_LAST \
40407 HWRM_CFA_METER_QCAPS_OUTPUT_FLAGS_CLOCK_625MHZ
40408 uint8_t unused_0[4];
40410 * The minimum guaranteed number of tx meter profiles supported
40411 * for this function.
40413 uint16_t min_tx_profile;
40415 * The maximum non-guaranteed number of tx meter profiles supported
40416 * for this function.
40418 uint16_t max_tx_profile;
40420 * The minimum guaranteed number of rx meter profiles supported
40421 * for this function.
40423 uint16_t min_rx_profile;
40425 * The maximum non-guaranteed number of rx meter profiles supported
40426 * for this function.
40428 uint16_t max_rx_profile;
40430 * The minimum guaranteed number of tx meter instances supported
40431 * for this function.
40433 uint16_t min_tx_instance;
40435 * The maximum non-guaranteed number of tx meter instances supported
40436 * for this function.
40438 uint16_t max_tx_instance;
40440 * The minimum guaranteed number of rx meter instances supported
40441 * for this function.
40443 uint16_t min_rx_instance;
40445 * The maximum non-guaranteed number of rx meter instances supported
40446 * for this function.
40448 uint16_t max_rx_instance;
40449 uint8_t unused_1[7];
40451 * This field is used in Output records to indicate that the output
40452 * is completely written to RAM. This field should be read as '1'
40453 * to indicate that the output has been completely written.
40454 * When writing a command completion or response to an internal
40455 * processor, the order of writes has to be such that this field is
40461 /********************************
40462 * hwrm_cfa_meter_profile_alloc *
40463 ********************************/
40466 /* hwrm_cfa_meter_profile_alloc_input (size:320b/40B) */
40467 struct hwrm_cfa_meter_profile_alloc_input {
40468 /* The HWRM command request type. */
40471 * The completion ring to send the completion event on. This should
40472 * be the NQ ID returned from the `nq_alloc` HWRM command.
40474 uint16_t cmpl_ring;
40476 * The sequence ID is used by the driver for tracking multiple
40477 * commands. This ID is treated as opaque data by the firmware and
40478 * the value is returned in the `hwrm_resp_hdr` upon completion.
40482 * The target ID of the command:
40483 * * 0x0-0xFFF8 - The function ID
40484 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
40485 * * 0xFFFD - Reserved for user-space HWRM interface
40488 uint16_t target_id;
40490 * A physical address pointer pointing to a host buffer that the
40491 * command's response data will be written. This can be either a host
40492 * physical address (HPA) or a guest physical address (GPA) and must
40493 * point to a physically contiguous block of memory.
40495 uint64_t resp_addr;
40498 * Enumeration denoting the RX, TX type of the resource.
40499 * This enumeration is used for resources that are similar for both
40500 * TX and RX paths of the chip.
40502 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_FLAGS_PATH UINT32_C(0x1)
40504 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_FLAGS_PATH_TX \
40507 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_FLAGS_PATH_RX \
40509 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_FLAGS_PATH_LAST \
40510 HWRM_CFA_METER_PROFILE_ALLOC_INPUT_FLAGS_PATH_RX
40511 /* The meter algorithm type. */
40512 uint8_t meter_type;
40513 /* RFC 2697 (srTCM) */
40514 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_METER_TYPE_RFC2697 \
40516 /* RFC 2698 (trTCM) */
40517 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_METER_TYPE_RFC2698 \
40519 /* RFC 4115 (trTCM) */
40520 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_METER_TYPE_RFC4115 \
40522 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_METER_TYPE_LAST \
40523 HWRM_CFA_METER_PROFILE_ALLOC_INPUT_METER_TYPE_RFC4115
40525 * This field is reserved for the future use.
40526 * It shall be set to 0.
40528 uint16_t reserved1;
40530 * This field is reserved for the future use.
40531 * It shall be set to 0.
40533 uint32_t reserved2;
40534 /* A meter rate specified in bytes-per-second. */
40535 uint32_t commit_rate;
40536 /* The bandwidth value. */
40537 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_RATE_BW_VALUE_MASK \
40538 UINT32_C(0xfffffff)
40539 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_RATE_BW_VALUE_SFT \
40541 /* The granularity of the value (bits or bytes). */
40542 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_RATE_SCALE \
40543 UINT32_C(0x10000000)
40544 /* Value is in bits. */
40545 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_RATE_SCALE_BITS \
40546 (UINT32_C(0x0) << 28)
40547 /* Value is in bytes. */
40548 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_RATE_SCALE_BYTES \
40549 (UINT32_C(0x1) << 28)
40550 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_RATE_SCALE_LAST \
40551 HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_RATE_SCALE_BYTES
40552 /* bw_value_unit is 3 b */
40553 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_RATE_BW_VALUE_UNIT_MASK \
40554 UINT32_C(0xe0000000)
40555 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_RATE_BW_VALUE_UNIT_SFT \
40557 /* Value is in Mb or MB (base 10). */
40558 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_RATE_BW_VALUE_UNIT_MEGA \
40559 (UINT32_C(0x0) << 29)
40560 /* Value is in Kb or KB (base 10). */
40561 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_RATE_BW_VALUE_UNIT_KILO \
40562 (UINT32_C(0x2) << 29)
40563 /* Value is in bits or bytes. */
40564 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_RATE_BW_VALUE_UNIT_BASE \
40565 (UINT32_C(0x4) << 29)
40566 /* Value is in Gb or GB (base 10). */
40567 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_RATE_BW_VALUE_UNIT_GIGA \
40568 (UINT32_C(0x6) << 29)
40569 /* Value is in 1/100th of a percentage of total bandwidth. */
40570 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_RATE_BW_VALUE_UNIT_PERCENT1_100 \
40571 (UINT32_C(0x1) << 29)
40573 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_RATE_BW_VALUE_UNIT_RAW \
40574 (UINT32_C(0x7) << 29)
40575 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_RATE_BW_VALUE_UNIT_LAST \
40576 HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_RATE_BW_VALUE_UNIT_RAW
40577 /* A meter burst size specified in bytes. */
40578 uint32_t commit_burst;
40579 /* The bandwidth value. */
40580 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_BURST_BW_VALUE_MASK \
40581 UINT32_C(0xfffffff)
40582 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_BURST_BW_VALUE_SFT \
40584 /* The granularity of the value (bits or bytes). */
40585 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_BURST_SCALE \
40586 UINT32_C(0x10000000)
40587 /* Value is in bits. */
40588 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_BURST_SCALE_BITS \
40589 (UINT32_C(0x0) << 28)
40590 /* Value is in bytes. */
40591 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_BURST_SCALE_BYTES \
40592 (UINT32_C(0x1) << 28)
40593 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_BURST_SCALE_LAST \
40594 HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_BURST_SCALE_BYTES
40595 /* bw_value_unit is 3 b */
40596 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_BURST_BW_VALUE_UNIT_MASK \
40597 UINT32_C(0xe0000000)
40598 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_BURST_BW_VALUE_UNIT_SFT \
40600 /* Value is in Mb or MB (base 10). */
40601 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_BURST_BW_VALUE_UNIT_MEGA \
40602 (UINT32_C(0x0) << 29)
40603 /* Value is in Kb or KB (base 10). */
40604 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_BURST_BW_VALUE_UNIT_KILO \
40605 (UINT32_C(0x2) << 29)
40606 /* Value is in bits or bytes. */
40607 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_BURST_BW_VALUE_UNIT_BASE \
40608 (UINT32_C(0x4) << 29)
40609 /* Value is in Gb or GB (base 10). */
40610 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_BURST_BW_VALUE_UNIT_GIGA \
40611 (UINT32_C(0x6) << 29)
40612 /* Value is in 1/100th of a percentage of total bandwidth. */
40613 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_BURST_BW_VALUE_UNIT_PERCENT1_100 \
40614 (UINT32_C(0x1) << 29)
40615 /* Invalid value */
40616 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_BURST_BW_VALUE_UNIT_INVALID \
40617 (UINT32_C(0x7) << 29)
40618 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_BURST_BW_VALUE_UNIT_LAST \
40619 HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_BURST_BW_VALUE_UNIT_INVALID
40620 /* A meter rate specified in bytes-per-second. */
40621 uint32_t excess_peak_rate;
40622 /* The bandwidth value. */
40623 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_RATE_BW_VALUE_MASK \
40624 UINT32_C(0xfffffff)
40625 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_RATE_BW_VALUE_SFT \
40627 /* The granularity of the value (bits or bytes). */
40628 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_RATE_SCALE \
40629 UINT32_C(0x10000000)
40630 /* Value is in bits. */
40631 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_RATE_SCALE_BITS \
40632 (UINT32_C(0x0) << 28)
40633 /* Value is in bytes. */
40634 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_RATE_SCALE_BYTES \
40635 (UINT32_C(0x1) << 28)
40636 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_RATE_SCALE_LAST \
40637 HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_RATE_SCALE_BYTES
40638 /* bw_value_unit is 3 b */
40639 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_RATE_BW_VALUE_UNIT_MASK \
40640 UINT32_C(0xe0000000)
40641 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_RATE_BW_VALUE_UNIT_SFT \
40643 /* Value is in Mb or MB (base 10). */
40644 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_RATE_BW_VALUE_UNIT_MEGA \
40645 (UINT32_C(0x0) << 29)
40646 /* Value is in Kb or KB (base 10). */
40647 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_RATE_BW_VALUE_UNIT_KILO \
40648 (UINT32_C(0x2) << 29)
40649 /* Value is in bits or bytes. */
40650 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_RATE_BW_VALUE_UNIT_BASE \
40651 (UINT32_C(0x4) << 29)
40652 /* Value is in Gb or GB (base 10). */
40653 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_RATE_BW_VALUE_UNIT_GIGA \
40654 (UINT32_C(0x6) << 29)
40655 /* Value is in 1/100th of a percentage of total bandwidth. */
40656 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_RATE_BW_VALUE_UNIT_PERCENT1_100 \
40657 (UINT32_C(0x1) << 29)
40659 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_RATE_BW_VALUE_UNIT_RAW \
40660 (UINT32_C(0x7) << 29)
40661 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_RATE_BW_VALUE_UNIT_LAST \
40662 HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_RATE_BW_VALUE_UNIT_RAW
40663 /* A meter burst size specified in bytes. */
40664 uint32_t excess_peak_burst;
40665 /* The bandwidth value. */
40666 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_BURST_BW_VALUE_MASK \
40667 UINT32_C(0xfffffff)
40668 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_BURST_BW_VALUE_SFT \
40670 /* The granularity of the value (bits or bytes). */
40671 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_BURST_SCALE \
40672 UINT32_C(0x10000000)
40673 /* Value is in bits. */
40674 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_BURST_SCALE_BITS \
40675 (UINT32_C(0x0) << 28)
40676 /* Value is in bytes. */
40677 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_BURST_SCALE_BYTES \
40678 (UINT32_C(0x1) << 28)
40679 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_BURST_SCALE_LAST \
40680 HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_BURST_SCALE_BYTES
40681 /* bw_value_unit is 3 b */
40682 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_BURST_BW_VALUE_UNIT_MASK \
40683 UINT32_C(0xe0000000)
40684 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_BURST_BW_VALUE_UNIT_SFT \
40686 /* Value is in Mb or MB (base 10). */
40687 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_BURST_BW_VALUE_UNIT_MEGA \
40688 (UINT32_C(0x0) << 29)
40689 /* Value is in Kb or KB (base 10). */
40690 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_BURST_BW_VALUE_UNIT_KILO \
40691 (UINT32_C(0x2) << 29)
40692 /* Value is in bits or bytes. */
40693 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_BURST_BW_VALUE_UNIT_BASE \
40694 (UINT32_C(0x4) << 29)
40695 /* Value is in Gb or GB (base 10). */
40696 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_BURST_BW_VALUE_UNIT_GIGA \
40697 (UINT32_C(0x6) << 29)
40698 /* Value is in 1/100th of a percentage of total bandwidth. */
40699 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_BURST_BW_VALUE_UNIT_PERCENT1_100 \
40700 (UINT32_C(0x1) << 29)
40702 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_BURST_BW_VALUE_UNIT_INVALID \
40703 (UINT32_C(0x7) << 29)
40704 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_BURST_BW_VALUE_UNIT_LAST \
40705 HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_BURST_BW_VALUE_UNIT_INVALID
40708 /* hwrm_cfa_meter_profile_alloc_output (size:128b/16B) */
40709 struct hwrm_cfa_meter_profile_alloc_output {
40710 /* The specific error status for the command. */
40711 uint16_t error_code;
40712 /* The HWRM command request type. */
40714 /* The sequence ID from the original command. */
40716 /* The length of the response data in number of bytes. */
40718 /* This value identifies a meter profile in CFA. */
40719 uint16_t meter_profile_id;
40721 * A value of 0xfff is considered invalid and implies the
40722 * profile is not configured.
40724 #define HWRM_CFA_METER_PROFILE_ALLOC_OUTPUT_METER_PROFILE_ID_INVALID \
40726 #define HWRM_CFA_METER_PROFILE_ALLOC_OUTPUT_METER_PROFILE_ID_LAST \
40727 HWRM_CFA_METER_PROFILE_ALLOC_OUTPUT_METER_PROFILE_ID_INVALID
40728 uint8_t unused_0[5];
40730 * This field is used in Output records to indicate that the output
40731 * is completely written to RAM. This field should be read as '1'
40732 * to indicate that the output has been completely written.
40733 * When writing a command completion or response to an internal
40734 * processor, the order of writes has to be such that this field is
40740 /*******************************
40741 * hwrm_cfa_meter_profile_free *
40742 *******************************/
40745 /* hwrm_cfa_meter_profile_free_input (size:192b/24B) */
40746 struct hwrm_cfa_meter_profile_free_input {
40747 /* The HWRM command request type. */
40750 * The completion ring to send the completion event on. This should
40751 * be the NQ ID returned from the `nq_alloc` HWRM command.
40753 uint16_t cmpl_ring;
40755 * The sequence ID is used by the driver for tracking multiple
40756 * commands. This ID is treated as opaque data by the firmware and
40757 * the value is returned in the `hwrm_resp_hdr` upon completion.
40761 * The target ID of the command:
40762 * * 0x0-0xFFF8 - The function ID
40763 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
40764 * * 0xFFFD - Reserved for user-space HWRM interface
40767 uint16_t target_id;
40769 * A physical address pointer pointing to a host buffer that the
40770 * command's response data will be written. This can be either a host
40771 * physical address (HPA) or a guest physical address (GPA) and must
40772 * point to a physically contiguous block of memory.
40774 uint64_t resp_addr;
40777 * Enumeration denoting the RX, TX type of the resource.
40778 * This enumeration is used for resources that are similar for both
40779 * TX and RX paths of the chip.
40781 #define HWRM_CFA_METER_PROFILE_FREE_INPUT_FLAGS_PATH UINT32_C(0x1)
40783 #define HWRM_CFA_METER_PROFILE_FREE_INPUT_FLAGS_PATH_TX \
40786 #define HWRM_CFA_METER_PROFILE_FREE_INPUT_FLAGS_PATH_RX \
40788 #define HWRM_CFA_METER_PROFILE_FREE_INPUT_FLAGS_PATH_LAST \
40789 HWRM_CFA_METER_PROFILE_FREE_INPUT_FLAGS_PATH_RX
40791 /* This value identifies a meter profile in CFA. */
40792 uint16_t meter_profile_id;
40794 * A value of 0xfff is considered invalid and implies the
40795 * profile is not configured.
40797 #define HWRM_CFA_METER_PROFILE_FREE_INPUT_METER_PROFILE_ID_INVALID \
40799 #define HWRM_CFA_METER_PROFILE_FREE_INPUT_METER_PROFILE_ID_LAST \
40800 HWRM_CFA_METER_PROFILE_FREE_INPUT_METER_PROFILE_ID_INVALID
40801 uint8_t unused_1[4];
40804 /* hwrm_cfa_meter_profile_free_output (size:128b/16B) */
40805 struct hwrm_cfa_meter_profile_free_output {
40806 /* The specific error status for the command. */
40807 uint16_t error_code;
40808 /* The HWRM command request type. */
40810 /* The sequence ID from the original command. */
40812 /* The length of the response data in number of bytes. */
40814 uint8_t unused_0[7];
40816 * This field is used in Output records to indicate that the output
40817 * is completely written to RAM. This field should be read as '1'
40818 * to indicate that the output has been completely written.
40819 * When writing a command completion or response to an internal
40820 * processor, the order of writes has to be such that this field is
40826 /******************************
40827 * hwrm_cfa_meter_profile_cfg *
40828 ******************************/
40831 /* hwrm_cfa_meter_profile_cfg_input (size:320b/40B) */
40832 struct hwrm_cfa_meter_profile_cfg_input {
40833 /* The HWRM command request type. */
40836 * The completion ring to send the completion event on. This should
40837 * be the NQ ID returned from the `nq_alloc` HWRM command.
40839 uint16_t cmpl_ring;
40841 * The sequence ID is used by the driver for tracking multiple
40842 * commands. This ID is treated as opaque data by the firmware and
40843 * the value is returned in the `hwrm_resp_hdr` upon completion.
40847 * The target ID of the command:
40848 * * 0x0-0xFFF8 - The function ID
40849 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
40850 * * 0xFFFD - Reserved for user-space HWRM interface
40853 uint16_t target_id;
40855 * A physical address pointer pointing to a host buffer that the
40856 * command's response data will be written. This can be either a host
40857 * physical address (HPA) or a guest physical address (GPA) and must
40858 * point to a physically contiguous block of memory.
40860 uint64_t resp_addr;
40863 * Enumeration denoting the RX, TX type of the resource.
40864 * This enumeration is used for resources that are similar for both
40865 * TX and RX paths of the chip.
40867 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_FLAGS_PATH UINT32_C(0x1)
40869 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_FLAGS_PATH_TX UINT32_C(0x0)
40871 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_FLAGS_PATH_RX UINT32_C(0x1)
40872 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_FLAGS_PATH_LAST \
40873 HWRM_CFA_METER_PROFILE_CFG_INPUT_FLAGS_PATH_RX
40874 /* The meter algorithm type. */
40875 uint8_t meter_type;
40876 /* RFC 2697 (srTCM) */
40877 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_METER_TYPE_RFC2697 \
40879 /* RFC 2698 (trTCM) */
40880 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_METER_TYPE_RFC2698 \
40882 /* RFC 4115 (trTCM) */
40883 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_METER_TYPE_RFC4115 \
40885 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_METER_TYPE_LAST \
40886 HWRM_CFA_METER_PROFILE_CFG_INPUT_METER_TYPE_RFC4115
40887 /* This value identifies a meter profile in CFA. */
40888 uint16_t meter_profile_id;
40890 * A value of 0xfff is considered invalid and implies the
40891 * profile is not configured.
40893 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_METER_PROFILE_ID_INVALID \
40895 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_METER_PROFILE_ID_LAST \
40896 HWRM_CFA_METER_PROFILE_CFG_INPUT_METER_PROFILE_ID_INVALID
40898 * This field is reserved for the future use.
40899 * It shall be set to 0.
40902 /* A meter rate specified in bytes-per-second. */
40903 uint32_t commit_rate;
40904 /* The bandwidth value. */
40905 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_RATE_BW_VALUE_MASK \
40906 UINT32_C(0xfffffff)
40907 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_RATE_BW_VALUE_SFT \
40909 /* The granularity of the value (bits or bytes). */
40910 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_RATE_SCALE \
40911 UINT32_C(0x10000000)
40912 /* Value is in bits. */
40913 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_RATE_SCALE_BITS \
40914 (UINT32_C(0x0) << 28)
40915 /* Value is in bytes. */
40916 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_RATE_SCALE_BYTES \
40917 (UINT32_C(0x1) << 28)
40918 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_RATE_SCALE_LAST \
40919 HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_RATE_SCALE_BYTES
40920 /* bw_value_unit is 3 b */
40921 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_RATE_BW_VALUE_UNIT_MASK \
40922 UINT32_C(0xe0000000)
40923 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_RATE_BW_VALUE_UNIT_SFT \
40925 /* Value is in Mb or MB (base 10). */
40926 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_RATE_BW_VALUE_UNIT_MEGA \
40927 (UINT32_C(0x0) << 29)
40928 /* Value is in Kb or KB (base 10). */
40929 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_RATE_BW_VALUE_UNIT_KILO \
40930 (UINT32_C(0x2) << 29)
40931 /* Value is in bits or bytes. */
40932 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_RATE_BW_VALUE_UNIT_BASE \
40933 (UINT32_C(0x4) << 29)
40934 /* Value is in Gb or GB (base 10). */
40935 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_RATE_BW_VALUE_UNIT_GIGA \
40936 (UINT32_C(0x6) << 29)
40937 /* Value is in 1/100th of a percentage of total bandwidth. */
40938 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_RATE_BW_VALUE_UNIT_PERCENT1_100 \
40939 (UINT32_C(0x1) << 29)
40941 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_RATE_BW_VALUE_UNIT_RAW \
40942 (UINT32_C(0x7) << 29)
40943 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_RATE_BW_VALUE_UNIT_LAST \
40944 HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_RATE_BW_VALUE_UNIT_RAW
40945 /* A meter burst size specified in bytes. */
40946 uint32_t commit_burst;
40947 /* The bandwidth value. */
40948 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_BURST_BW_VALUE_MASK \
40949 UINT32_C(0xfffffff)
40950 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_BURST_BW_VALUE_SFT \
40952 /* The granularity of the value (bits or bytes). */
40953 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_BURST_SCALE \
40954 UINT32_C(0x10000000)
40955 /* Value is in bits. */
40956 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_BURST_SCALE_BITS \
40957 (UINT32_C(0x0) << 28)
40958 /* Value is in bytes. */
40959 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_BURST_SCALE_BYTES \
40960 (UINT32_C(0x1) << 28)
40961 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_BURST_SCALE_LAST \
40962 HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_BURST_SCALE_BYTES
40963 /* bw_value_unit is 3 b */
40964 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_BURST_BW_VALUE_UNIT_MASK \
40965 UINT32_C(0xe0000000)
40966 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_BURST_BW_VALUE_UNIT_SFT \
40968 /* Value is in Mb or MB (base 10). */
40969 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_BURST_BW_VALUE_UNIT_MEGA \
40970 (UINT32_C(0x0) << 29)
40971 /* Value is in Kb or KB (base 10). */
40972 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_BURST_BW_VALUE_UNIT_KILO \
40973 (UINT32_C(0x2) << 29)
40974 /* Value is in bits or bytes. */
40975 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_BURST_BW_VALUE_UNIT_BASE \
40976 (UINT32_C(0x4) << 29)
40977 /* Value is in Gb or GB (base 10). */
40978 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_BURST_BW_VALUE_UNIT_GIGA \
40979 (UINT32_C(0x6) << 29)
40980 /* Value is in 1/100th of a percentage of total bandwidth. */
40981 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_BURST_BW_VALUE_UNIT_PERCENT1_100 \
40982 (UINT32_C(0x1) << 29)
40983 /* Invalid value */
40984 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_BURST_BW_VALUE_UNIT_INVALID \
40985 (UINT32_C(0x7) << 29)
40986 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_BURST_BW_VALUE_UNIT_LAST \
40987 HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_BURST_BW_VALUE_UNIT_INVALID
40988 /* A meter rate specified in bytes-per-second. */
40989 uint32_t excess_peak_rate;
40990 /* The bandwidth value. */
40991 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_RATE_BW_VALUE_MASK \
40992 UINT32_C(0xfffffff)
40993 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_RATE_BW_VALUE_SFT \
40995 /* The granularity of the value (bits or bytes). */
40996 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_RATE_SCALE \
40997 UINT32_C(0x10000000)
40998 /* Value is in bits. */
40999 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_RATE_SCALE_BITS \
41000 (UINT32_C(0x0) << 28)
41001 /* Value is in bytes. */
41002 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_RATE_SCALE_BYTES \
41003 (UINT32_C(0x1) << 28)
41004 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_RATE_SCALE_LAST \
41005 HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_RATE_SCALE_BYTES
41006 /* bw_value_unit is 3 b */
41007 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_RATE_BW_VALUE_UNIT_MASK \
41008 UINT32_C(0xe0000000)
41009 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_RATE_BW_VALUE_UNIT_SFT \
41011 /* Value is in Mb or MB (base 10). */
41012 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_RATE_BW_VALUE_UNIT_MEGA \
41013 (UINT32_C(0x0) << 29)
41014 /* Value is in Kb or KB (base 10). */
41015 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_RATE_BW_VALUE_UNIT_KILO \
41016 (UINT32_C(0x2) << 29)
41017 /* Value is in bits or bytes. */
41018 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_RATE_BW_VALUE_UNIT_BASE \
41019 (UINT32_C(0x4) << 29)
41020 /* Value is in Gb or GB (base 10). */
41021 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_RATE_BW_VALUE_UNIT_GIGA \
41022 (UINT32_C(0x6) << 29)
41023 /* Value is in 1/100th of a percentage of total bandwidth. */
41024 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_RATE_BW_VALUE_UNIT_PERCENT1_100 \
41025 (UINT32_C(0x1) << 29)
41027 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_RATE_BW_VALUE_UNIT_RAW \
41028 (UINT32_C(0x7) << 29)
41029 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_RATE_BW_VALUE_UNIT_LAST \
41030 HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_RATE_BW_VALUE_UNIT_RAW
41031 /* A meter burst size specified in bytes. */
41032 uint32_t excess_peak_burst;
41033 /* The bandwidth value. */
41034 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_BURST_BW_VALUE_MASK \
41035 UINT32_C(0xfffffff)
41036 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_BURST_BW_VALUE_SFT \
41038 /* The granularity of the value (bits or bytes). */
41039 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_BURST_SCALE \
41040 UINT32_C(0x10000000)
41041 /* Value is in bits. */
41042 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_BURST_SCALE_BITS \
41043 (UINT32_C(0x0) << 28)
41044 /* Value is in bytes. */
41045 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_BURST_SCALE_BYTES \
41046 (UINT32_C(0x1) << 28)
41047 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_BURST_SCALE_LAST \
41048 HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_BURST_SCALE_BYTES
41049 /* bw_value_unit is 3 b */
41050 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_BURST_BW_VALUE_UNIT_MASK \
41051 UINT32_C(0xe0000000)
41052 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_BURST_BW_VALUE_UNIT_SFT \
41054 /* Value is in Mb or MB (base 10). */
41055 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_BURST_BW_VALUE_UNIT_MEGA \
41056 (UINT32_C(0x0) << 29)
41057 /* Value is in Kb or KB (base 10). */
41058 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_BURST_BW_VALUE_UNIT_KILO \
41059 (UINT32_C(0x2) << 29)
41060 /* Value is in bits or bytes. */
41061 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_BURST_BW_VALUE_UNIT_BASE \
41062 (UINT32_C(0x4) << 29)
41063 /* Value is in Gb or GB (base 10). */
41064 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_BURST_BW_VALUE_UNIT_GIGA \
41065 (UINT32_C(0x6) << 29)
41066 /* Value is in 1/100th of a percentage of total bandwidth. */
41067 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_BURST_BW_VALUE_UNIT_PERCENT1_100 \
41068 (UINT32_C(0x1) << 29)
41070 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_BURST_BW_VALUE_UNIT_INVALID \
41071 (UINT32_C(0x7) << 29)
41072 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_BURST_BW_VALUE_UNIT_LAST \
41073 HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_BURST_BW_VALUE_UNIT_INVALID
41076 /* hwrm_cfa_meter_profile_cfg_output (size:128b/16B) */
41077 struct hwrm_cfa_meter_profile_cfg_output {
41078 /* The specific error status for the command. */
41079 uint16_t error_code;
41080 /* The HWRM command request type. */
41082 /* The sequence ID from the original command. */
41084 /* The length of the response data in number of bytes. */
41086 uint8_t unused_0[7];
41088 * This field is used in Output records to indicate that the output
41089 * is completely written to RAM. This field should be read as '1'
41090 * to indicate that the output has been completely written.
41091 * When writing a command completion or response to an internal
41092 * processor, the order of writes has to be such that this field is
41098 /*********************************
41099 * hwrm_cfa_meter_instance_alloc *
41100 *********************************/
41103 /* hwrm_cfa_meter_instance_alloc_input (size:192b/24B) */
41104 struct hwrm_cfa_meter_instance_alloc_input {
41105 /* The HWRM command request type. */
41108 * The completion ring to send the completion event on. This should
41109 * be the NQ ID returned from the `nq_alloc` HWRM command.
41111 uint16_t cmpl_ring;
41113 * The sequence ID is used by the driver for tracking multiple
41114 * commands. This ID is treated as opaque data by the firmware and
41115 * the value is returned in the `hwrm_resp_hdr` upon completion.
41119 * The target ID of the command:
41120 * * 0x0-0xFFF8 - The function ID
41121 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
41122 * * 0xFFFD - Reserved for user-space HWRM interface
41125 uint16_t target_id;
41127 * A physical address pointer pointing to a host buffer that the
41128 * command's response data will be written. This can be either a host
41129 * physical address (HPA) or a guest physical address (GPA) and must
41130 * point to a physically contiguous block of memory.
41132 uint64_t resp_addr;
41135 * Enumeration denoting the RX, TX type of the resource.
41136 * This enumeration is used for resources that are similar for both
41137 * TX and RX paths of the chip.
41139 #define HWRM_CFA_METER_INSTANCE_ALLOC_INPUT_FLAGS_PATH \
41142 #define HWRM_CFA_METER_INSTANCE_ALLOC_INPUT_FLAGS_PATH_TX \
41145 #define HWRM_CFA_METER_INSTANCE_ALLOC_INPUT_FLAGS_PATH_RX \
41147 #define HWRM_CFA_METER_INSTANCE_ALLOC_INPUT_FLAGS_PATH_LAST \
41148 HWRM_CFA_METER_INSTANCE_ALLOC_INPUT_FLAGS_PATH_RX
41150 /* This value identifies a meter profile in CFA. */
41151 uint16_t meter_profile_id;
41153 * A value of 0xffff is considered invalid and implies the
41154 * profile is not configured.
41156 #define HWRM_CFA_METER_INSTANCE_ALLOC_INPUT_METER_PROFILE_ID_INVALID \
41158 #define HWRM_CFA_METER_INSTANCE_ALLOC_INPUT_METER_PROFILE_ID_LAST \
41159 HWRM_CFA_METER_INSTANCE_ALLOC_INPUT_METER_PROFILE_ID_INVALID
41160 uint8_t unused_1[4];
41163 /* hwrm_cfa_meter_instance_alloc_output (size:128b/16B) */
41164 struct hwrm_cfa_meter_instance_alloc_output {
41165 /* The specific error status for the command. */
41166 uint16_t error_code;
41167 /* The HWRM command request type. */
41169 /* The sequence ID from the original command. */
41171 /* The length of the response data in number of bytes. */
41173 /* This value identifies a meter instance in CFA. */
41174 uint16_t meter_instance_id;
41176 * A value of 0xffff is considered invalid and implies the
41177 * instance is not configured.
41179 #define HWRM_CFA_METER_INSTANCE_ALLOC_OUTPUT_METER_INSTANCE_ID_INVALID \
41181 #define HWRM_CFA_METER_INSTANCE_ALLOC_OUTPUT_METER_INSTANCE_ID_LAST \
41182 HWRM_CFA_METER_INSTANCE_ALLOC_OUTPUT_METER_INSTANCE_ID_INVALID
41183 uint8_t unused_0[5];
41185 * This field is used in Output records to indicate that the output
41186 * is completely written to RAM. This field should be read as '1'
41187 * to indicate that the output has been completely written.
41188 * When writing a command completion or response to an internal
41189 * processor, the order of writes has to be such that this field is
41195 /*******************************
41196 * hwrm_cfa_meter_instance_cfg *
41197 *******************************/
41200 /* hwrm_cfa_meter_instance_cfg_input (size:192b/24B) */
41201 struct hwrm_cfa_meter_instance_cfg_input {
41202 /* The HWRM command request type. */
41205 * The completion ring to send the completion event on. This should
41206 * be the NQ ID returned from the `nq_alloc` HWRM command.
41208 uint16_t cmpl_ring;
41210 * The sequence ID is used by the driver for tracking multiple
41211 * commands. This ID is treated as opaque data by the firmware and
41212 * the value is returned in the `hwrm_resp_hdr` upon completion.
41216 * The target ID of the command:
41217 * * 0x0-0xFFF8 - The function ID
41218 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
41219 * * 0xFFFD - Reserved for user-space HWRM interface
41222 uint16_t target_id;
41224 * A physical address pointer pointing to a host buffer that the
41225 * command's response data will be written. This can be either a host
41226 * physical address (HPA) or a guest physical address (GPA) and must
41227 * point to a physically contiguous block of memory.
41229 uint64_t resp_addr;
41232 * Enumeration denoting the RX, TX type of the resource.
41233 * This enumeration is used for resources that are similar for both
41234 * TX and RX paths of the chip.
41236 #define HWRM_CFA_METER_INSTANCE_CFG_INPUT_FLAGS_PATH UINT32_C(0x1)
41238 #define HWRM_CFA_METER_INSTANCE_CFG_INPUT_FLAGS_PATH_TX \
41241 #define HWRM_CFA_METER_INSTANCE_CFG_INPUT_FLAGS_PATH_RX \
41243 #define HWRM_CFA_METER_INSTANCE_CFG_INPUT_FLAGS_PATH_LAST \
41244 HWRM_CFA_METER_INSTANCE_CFG_INPUT_FLAGS_PATH_RX
41247 * This value identifies a new meter profile to be associated with
41248 * the meter instance specified in this command.
41250 uint16_t meter_profile_id;
41252 * A value of 0xffff is considered invalid and implies the
41253 * profile is not configured.
41255 #define HWRM_CFA_METER_INSTANCE_CFG_INPUT_METER_PROFILE_ID_INVALID \
41257 #define HWRM_CFA_METER_INSTANCE_CFG_INPUT_METER_PROFILE_ID_LAST \
41258 HWRM_CFA_METER_INSTANCE_CFG_INPUT_METER_PROFILE_ID_INVALID
41260 * This value identifies the ID of a meter instance that needs to be
41261 * updated with a new meter profile specified in this command.
41263 uint16_t meter_instance_id;
41264 uint8_t unused_1[2];
41267 /* hwrm_cfa_meter_instance_cfg_output (size:128b/16B) */
41268 struct hwrm_cfa_meter_instance_cfg_output {
41269 /* The specific error status for the command. */
41270 uint16_t error_code;
41271 /* The HWRM command request type. */
41273 /* The sequence ID from the original command. */
41275 /* The length of the response data in number of bytes. */
41277 uint8_t unused_0[7];
41279 * This field is used in Output records to indicate that the output
41280 * is completely written to RAM. This field should be read as '1'
41281 * to indicate that the output has been completely written.
41282 * When writing a command completion or response to an internal
41283 * processor, the order of writes has to be such that this field is
41289 /********************************
41290 * hwrm_cfa_meter_instance_free *
41291 ********************************/
41294 /* hwrm_cfa_meter_instance_free_input (size:192b/24B) */
41295 struct hwrm_cfa_meter_instance_free_input {
41296 /* The HWRM command request type. */
41299 * The completion ring to send the completion event on. This should
41300 * be the NQ ID returned from the `nq_alloc` HWRM command.
41302 uint16_t cmpl_ring;
41304 * The sequence ID is used by the driver for tracking multiple
41305 * commands. This ID is treated as opaque data by the firmware and
41306 * the value is returned in the `hwrm_resp_hdr` upon completion.
41310 * The target ID of the command:
41311 * * 0x0-0xFFF8 - The function ID
41312 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
41313 * * 0xFFFD - Reserved for user-space HWRM interface
41316 uint16_t target_id;
41318 * A physical address pointer pointing to a host buffer that the
41319 * command's response data will be written. This can be either a host
41320 * physical address (HPA) or a guest physical address (GPA) and must
41321 * point to a physically contiguous block of memory.
41323 uint64_t resp_addr;
41326 * Enumeration denoting the RX, TX type of the resource.
41327 * This enumeration is used for resources that are similar for both
41328 * TX and RX paths of the chip.
41330 #define HWRM_CFA_METER_INSTANCE_FREE_INPUT_FLAGS_PATH UINT32_C(0x1)
41332 #define HWRM_CFA_METER_INSTANCE_FREE_INPUT_FLAGS_PATH_TX \
41335 #define HWRM_CFA_METER_INSTANCE_FREE_INPUT_FLAGS_PATH_RX \
41337 #define HWRM_CFA_METER_INSTANCE_FREE_INPUT_FLAGS_PATH_LAST \
41338 HWRM_CFA_METER_INSTANCE_FREE_INPUT_FLAGS_PATH_RX
41340 /* This value identifies a meter instance in CFA. */
41341 uint16_t meter_instance_id;
41343 * A value of 0xfff is considered invalid and implies the
41344 * instance is not configured.
41346 #define HWRM_CFA_METER_INSTANCE_FREE_INPUT_METER_INSTANCE_ID_INVALID \
41348 #define HWRM_CFA_METER_INSTANCE_FREE_INPUT_METER_INSTANCE_ID_LAST \
41349 HWRM_CFA_METER_INSTANCE_FREE_INPUT_METER_INSTANCE_ID_INVALID
41350 uint8_t unused_1[4];
41353 /* hwrm_cfa_meter_instance_free_output (size:128b/16B) */
41354 struct hwrm_cfa_meter_instance_free_output {
41355 /* The specific error status for the command. */
41356 uint16_t error_code;
41357 /* The HWRM command request type. */
41359 /* The sequence ID from the original command. */
41361 /* The length of the response data in number of bytes. */
41363 uint8_t unused_0[7];
41365 * This field is used in Output records to indicate that the output
41366 * is completely written to RAM. This field should be read as '1'
41367 * to indicate that the output has been completely written.
41368 * When writing a command completion or response to an internal
41369 * processor, the order of writes has to be such that this field is
41375 /*******************************
41376 * hwrm_cfa_decap_filter_alloc *
41377 *******************************/
41380 /* hwrm_cfa_decap_filter_alloc_input (size:832b/104B) */
41381 struct hwrm_cfa_decap_filter_alloc_input {
41382 /* The HWRM command request type. */
41385 * The completion ring to send the completion event on. This should
41386 * be the NQ ID returned from the `nq_alloc` HWRM command.
41388 uint16_t cmpl_ring;
41390 * The sequence ID is used by the driver for tracking multiple
41391 * commands. This ID is treated as opaque data by the firmware and
41392 * the value is returned in the `hwrm_resp_hdr` upon completion.
41396 * The target ID of the command:
41397 * * 0x0-0xFFF8 - The function ID
41398 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
41399 * * 0xFFFD - Reserved for user-space HWRM interface
41402 uint16_t target_id;
41404 * A physical address pointer pointing to a host buffer that the
41405 * command's response data will be written. This can be either a host
41406 * physical address (HPA) or a guest physical address (GPA) and must
41407 * point to a physically contiguous block of memory.
41409 uint64_t resp_addr;
41411 /* ovs_tunnel is 1 b */
41412 #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_FLAGS_OVS_TUNNEL \
41416 * This bit must be '1' for the tunnel_type field to be
41419 #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_ENABLES_TUNNEL_TYPE \
41422 * This bit must be '1' for the tunnel_id field to be
41425 #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_ENABLES_TUNNEL_ID \
41428 * This bit must be '1' for the src_macaddr field to be
41431 #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_ENABLES_SRC_MACADDR \
41434 * This bit must be '1' for the dst_macaddr field to be
41437 #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_ENABLES_DST_MACADDR \
41440 * This bit must be '1' for the ovlan_vid field to be
41443 #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_ENABLES_OVLAN_VID \
41446 * This bit must be '1' for the ivlan_vid field to be
41449 #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_ENABLES_IVLAN_VID \
41452 * This bit must be '1' for the t_ovlan_vid field to be
41455 #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_ENABLES_T_OVLAN_VID \
41458 * This bit must be '1' for the t_ivlan_vid field to be
41461 #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_ENABLES_T_IVLAN_VID \
41464 * This bit must be '1' for the ethertype field to be
41467 #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_ENABLES_ETHERTYPE \
41470 * This bit must be '1' for the src_ipaddr field to be
41473 #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_ENABLES_SRC_IPADDR \
41476 * This bit must be '1' for the dst_ipaddr field to be
41479 #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_ENABLES_DST_IPADDR \
41482 * This bit must be '1' for the ipaddr_type field to be
41485 #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_ENABLES_IPADDR_TYPE \
41488 * This bit must be '1' for the ip_protocol field to be
41491 #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_ENABLES_IP_PROTOCOL \
41494 * This bit must be '1' for the src_port field to be
41497 #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_ENABLES_SRC_PORT \
41500 * This bit must be '1' for the dst_port field to be
41503 #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_ENABLES_DST_PORT \
41506 * This bit must be '1' for the dst_id field to be
41509 #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_ENABLES_DST_ID \
41512 * This bit must be '1' for the mirror_vnic_id field to be
41515 #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_ENABLES_MIRROR_VNIC_ID \
41518 * Tunnel identifier.
41519 * Virtual Network Identifier (VNI). Only valid with
41520 * tunnel_types VXLAN, NVGRE, and Geneve.
41521 * Only lower 24-bits of VNI field are used
41522 * in setting up the filter.
41524 uint32_t tunnel_id;
41526 uint8_t tunnel_type;
41528 #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_TUNNEL_TYPE_NONTUNNEL \
41530 /* Virtual eXtensible Local Area Network (VXLAN) */
41531 #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_TUNNEL_TYPE_VXLAN \
41533 /* Network Virtualization Generic Routing Encapsulation (NVGRE) */
41534 #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_TUNNEL_TYPE_NVGRE \
41536 /* Generic Routing Encapsulation (GRE) inside Ethernet payload */
41537 #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_TUNNEL_TYPE_L2GRE \
41540 #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_TUNNEL_TYPE_IPIP \
41542 /* Generic Network Virtualization Encapsulation (Geneve) */
41543 #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_TUNNEL_TYPE_GENEVE \
41545 /* Multi-Protocol Label Switching (MPLS) */
41546 #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_TUNNEL_TYPE_MPLS \
41548 /* Stateless Transport Tunnel (STT) */
41549 #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_TUNNEL_TYPE_STT \
41551 /* Generic Routing Encapsulation (GRE) inside IP datagram payload */
41552 #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_TUNNEL_TYPE_IPGRE \
41554 /* IPV4 over virtual eXtensible Local Area Network (IPV4oVXLAN) */
41555 #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_TUNNEL_TYPE_VXLAN_V4 \
41558 * Enhance Generic Routing Encapsulation (GRE version 1) inside IP
41561 #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_TUNNEL_TYPE_IPGRE_V1 \
41563 /* Use fixed layer 2 ether type of 0xFFFF */
41564 #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_TUNNEL_TYPE_L2_ETYPE \
41567 * IPV6 over virtual eXtensible Local Area Network with GPE header
41570 #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_TUNNEL_TYPE_VXLAN_GPE_V6 \
41572 /* Any tunneled traffic */
41573 #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_TUNNEL_TYPE_ANYTUNNEL \
41575 #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_TUNNEL_TYPE_LAST \
41576 HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_TUNNEL_TYPE_ANYTUNNEL
41580 * This value indicates the source MAC address in
41581 * the Ethernet header.
41583 uint8_t src_macaddr[6];
41584 uint8_t unused_2[2];
41586 * This value indicates the destination MAC address in
41587 * the Ethernet header.
41589 uint8_t dst_macaddr[6];
41591 * This value indicates the VLAN ID of the outer VLAN tag
41592 * in the Ethernet header.
41594 uint16_t ovlan_vid;
41596 * This value indicates the VLAN ID of the inner VLAN tag
41597 * in the Ethernet header.
41599 uint16_t ivlan_vid;
41601 * This value indicates the VLAN ID of the outer VLAN tag
41602 * in the tunnel Ethernet header.
41604 uint16_t t_ovlan_vid;
41606 * This value indicates the VLAN ID of the inner VLAN tag
41607 * in the tunnel Ethernet header.
41609 uint16_t t_ivlan_vid;
41610 /* This value indicates the ethertype in the Ethernet header. */
41611 uint16_t ethertype;
41613 * This value indicates the type of IP address.
41616 * All others are invalid.
41618 uint8_t ip_addr_type;
41620 #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_IP_ADDR_TYPE_UNKNOWN \
41623 #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_IP_ADDR_TYPE_IPV4 \
41626 #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_IP_ADDR_TYPE_IPV6 \
41628 #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_IP_ADDR_TYPE_LAST \
41629 HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_IP_ADDR_TYPE_IPV6
41631 * The value of protocol filed in IP header.
41632 * Applies to UDP and TCP traffic.
41636 uint8_t ip_protocol;
41638 #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_IP_PROTOCOL_UNKNOWN \
41641 #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_IP_PROTOCOL_TCP \
41644 #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_IP_PROTOCOL_UDP \
41646 #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_IP_PROTOCOL_LAST \
41647 HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_IP_PROTOCOL_UDP
41651 * The value of source IP address to be used in filtering.
41652 * For IPv4, first four bytes represent the IP address.
41654 uint32_t src_ipaddr[4];
41656 * The value of destination IP address to be used in filtering.
41657 * For IPv4, first four bytes represent the IP address.
41659 uint32_t dst_ipaddr[4];
41661 * The value of source port to be used in filtering.
41662 * Applies to UDP and TCP traffic.
41666 * The value of destination port to be used in filtering.
41667 * Applies to UDP and TCP traffic.
41671 * If set, this value shall represent the
41672 * Logical VNIC ID of the destination VNIC for the RX
41677 * If set, this value shall represent the L2 context that matches the
41678 * L2 information of the decap filter.
41680 uint16_t l2_ctxt_ref_id;
41683 /* hwrm_cfa_decap_filter_alloc_output (size:128b/16B) */
41684 struct hwrm_cfa_decap_filter_alloc_output {
41685 /* The specific error status for the command. */
41686 uint16_t error_code;
41687 /* The HWRM command request type. */
41689 /* The sequence ID from the original command. */
41691 /* The length of the response data in number of bytes. */
41693 /* This value is an opaque id into CFA data structures. */
41694 uint32_t decap_filter_id;
41695 uint8_t unused_0[3];
41697 * This field is used in Output records to indicate that the output
41698 * is completely written to RAM. This field should be read as '1'
41699 * to indicate that the output has been completely written.
41700 * When writing a command completion or response to an internal
41701 * processor, the order of writes has to be such that this field is
41707 /******************************
41708 * hwrm_cfa_decap_filter_free *
41709 ******************************/
41712 /* hwrm_cfa_decap_filter_free_input (size:192b/24B) */
41713 struct hwrm_cfa_decap_filter_free_input {
41714 /* The HWRM command request type. */
41717 * The completion ring to send the completion event on. This should
41718 * be the NQ ID returned from the `nq_alloc` HWRM command.
41720 uint16_t cmpl_ring;
41722 * The sequence ID is used by the driver for tracking multiple
41723 * commands. This ID is treated as opaque data by the firmware and
41724 * the value is returned in the `hwrm_resp_hdr` upon completion.
41728 * The target ID of the command:
41729 * * 0x0-0xFFF8 - The function ID
41730 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
41731 * * 0xFFFD - Reserved for user-space HWRM interface
41734 uint16_t target_id;
41736 * A physical address pointer pointing to a host buffer that the
41737 * command's response data will be written. This can be either a host
41738 * physical address (HPA) or a guest physical address (GPA) and must
41739 * point to a physically contiguous block of memory.
41741 uint64_t resp_addr;
41742 /* This value is an opaque id into CFA data structures. */
41743 uint32_t decap_filter_id;
41744 uint8_t unused_0[4];
41747 /* hwrm_cfa_decap_filter_free_output (size:128b/16B) */
41748 struct hwrm_cfa_decap_filter_free_output {
41749 /* The specific error status for the command. */
41750 uint16_t error_code;
41751 /* The HWRM command request type. */
41753 /* The sequence ID from the original command. */
41755 /* The length of the response data in number of bytes. */
41757 uint8_t unused_0[7];
41759 * This field is used in Output records to indicate that the output
41760 * is completely written to RAM. This field should be read as '1'
41761 * to indicate that the output has been completely written.
41762 * When writing a command completion or response to an internal
41763 * processor, the order of writes has to be such that this field is
41769 /***********************
41770 * hwrm_cfa_flow_alloc *
41771 ***********************/
41774 /* hwrm_cfa_flow_alloc_input (size:1024b/128B) */
41775 struct hwrm_cfa_flow_alloc_input {
41776 /* The HWRM command request type. */
41779 * The completion ring to send the completion event on. This should
41780 * be the NQ ID returned from the `nq_alloc` HWRM command.
41782 uint16_t cmpl_ring;
41784 * The sequence ID is used by the driver for tracking multiple
41785 * commands. This ID is treated as opaque data by the firmware and
41786 * the value is returned in the `hwrm_resp_hdr` upon completion.
41790 * The target ID of the command:
41791 * * 0x0-0xFFF8 - The function ID
41792 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
41793 * * 0xFFFD - Reserved for user-space HWRM interface
41796 uint16_t target_id;
41798 * A physical address pointer pointing to a host buffer that the
41799 * command's response data will be written. This can be either a host
41800 * physical address (HPA) or a guest physical address (GPA) and must
41801 * point to a physically contiguous block of memory.
41803 uint64_t resp_addr;
41805 /* tunnel is 1 b */
41806 #define HWRM_CFA_FLOW_ALLOC_INPUT_FLAGS_TUNNEL \
41808 /* num_vlan is 2 b */
41809 #define HWRM_CFA_FLOW_ALLOC_INPUT_FLAGS_NUM_VLAN_MASK \
41811 #define HWRM_CFA_FLOW_ALLOC_INPUT_FLAGS_NUM_VLAN_SFT 1
41813 #define HWRM_CFA_FLOW_ALLOC_INPUT_FLAGS_NUM_VLAN_NONE \
41814 (UINT32_C(0x0) << 1)
41816 #define HWRM_CFA_FLOW_ALLOC_INPUT_FLAGS_NUM_VLAN_ONE \
41817 (UINT32_C(0x1) << 1)
41819 #define HWRM_CFA_FLOW_ALLOC_INPUT_FLAGS_NUM_VLAN_TWO \
41820 (UINT32_C(0x2) << 1)
41821 #define HWRM_CFA_FLOW_ALLOC_INPUT_FLAGS_NUM_VLAN_LAST \
41822 HWRM_CFA_FLOW_ALLOC_INPUT_FLAGS_NUM_VLAN_TWO
41823 /* Enumeration denoting the Flow Type. */
41824 #define HWRM_CFA_FLOW_ALLOC_INPUT_FLAGS_FLOWTYPE_MASK \
41826 #define HWRM_CFA_FLOW_ALLOC_INPUT_FLAGS_FLOWTYPE_SFT 3
41828 #define HWRM_CFA_FLOW_ALLOC_INPUT_FLAGS_FLOWTYPE_L2 \
41829 (UINT32_C(0x0) << 3)
41831 #define HWRM_CFA_FLOW_ALLOC_INPUT_FLAGS_FLOWTYPE_IPV4 \
41832 (UINT32_C(0x1) << 3)
41834 #define HWRM_CFA_FLOW_ALLOC_INPUT_FLAGS_FLOWTYPE_IPV6 \
41835 (UINT32_C(0x2) << 3)
41836 #define HWRM_CFA_FLOW_ALLOC_INPUT_FLAGS_FLOWTYPE_LAST \
41837 HWRM_CFA_FLOW_ALLOC_INPUT_FLAGS_FLOWTYPE_IPV6
41839 * when set to 1, indicates TX flow offload for function specified
41840 * in src_fid and the dst_fid should be set to invalid value. To
41841 * indicate a VM to VM flow, both of the path_tx and path_rx flags
41842 * need to be set. For virtio vSwitch offload case, the src_fid and
41843 * dst_fid is set to the same fid value. For the SRIOV vSwitch
41844 * offload case, the src_fid and dst_fid must be set to the same VF
41845 * FID belong to the children VFs of the same PF to indicate VM to
41848 #define HWRM_CFA_FLOW_ALLOC_INPUT_FLAGS_PATH_TX \
41851 * when set to 1, indicates RX flow offload for function specified
41852 * in dst_fid and the src_fid should be set to invalid value.
41854 #define HWRM_CFA_FLOW_ALLOC_INPUT_FLAGS_PATH_RX \
41857 * Set to 1 to indicate matching of VXLAN VNI from the custom vxlan
41858 * header is required and the VXLAN VNI value is stored in the first
41859 * 24 bits of the dmac field. This flag is only valid when the flow
41862 #define HWRM_CFA_FLOW_ALLOC_INPUT_FLAGS_MATCH_VXLAN_IP_VNI \
41865 * Set to 1 to indicate vhost_id is specified in the outer_vlan_tci
41868 #define HWRM_CFA_FLOW_ALLOC_INPUT_FLAGS_VHOST_ID_USE_VLAN \
41875 /* Tunnel handle valid when tunnel flag is set. */
41876 uint32_t tunnel_handle;
41877 uint16_t action_flags;
41879 * Setting of this flag indicates drop action. If this flag is not
41880 * set, then it should be considered accept action.
41882 #define HWRM_CFA_FLOW_ALLOC_INPUT_ACTION_FLAGS_FWD \
41884 /* recycle is 1 b */
41885 #define HWRM_CFA_FLOW_ALLOC_INPUT_ACTION_FLAGS_RECYCLE \
41888 * Setting of this flag indicates drop action. If this flag is not
41889 * set, then it should be considered accept action.
41891 #define HWRM_CFA_FLOW_ALLOC_INPUT_ACTION_FLAGS_DROP \
41894 #define HWRM_CFA_FLOW_ALLOC_INPUT_ACTION_FLAGS_METER \
41896 /* tunnel is 1 b */
41897 #define HWRM_CFA_FLOW_ALLOC_INPUT_ACTION_FLAGS_TUNNEL \
41899 /* nat_src is 1 b */
41900 #define HWRM_CFA_FLOW_ALLOC_INPUT_ACTION_FLAGS_NAT_SRC \
41902 /* nat_dest is 1 b */
41903 #define HWRM_CFA_FLOW_ALLOC_INPUT_ACTION_FLAGS_NAT_DEST \
41905 /* nat_ipv4_address is 1 b */
41906 #define HWRM_CFA_FLOW_ALLOC_INPUT_ACTION_FLAGS_NAT_IPV4_ADDRESS \
41908 /* l2_header_rewrite is 1 b */
41909 #define HWRM_CFA_FLOW_ALLOC_INPUT_ACTION_FLAGS_L2_HEADER_REWRITE \
41911 /* ttl_decrement is 1 b */
41912 #define HWRM_CFA_FLOW_ALLOC_INPUT_ACTION_FLAGS_TTL_DECREMENT \
41915 * If set to 1 and flow direction is TX, it indicates decap of L2
41916 * header and encap of tunnel header. If set to 1 and flow direction
41917 * is RX, it indicates decap of tunnel header and encap L2 header.
41918 * The type of tunnel is specified in the tunnel_type field.
41920 #define HWRM_CFA_FLOW_ALLOC_INPUT_ACTION_FLAGS_TUNNEL_IP \
41922 /* If set to 1, flow aging is enabled for this flow. */
41923 #define HWRM_CFA_FLOW_ALLOC_INPUT_ACTION_FLAGS_FLOW_AGING_ENABLED \
41926 * If set to 1 an attempt will be made to try to offload this flow
41927 * to the most optimal flow table resource. If set to 0, the flow
41928 * will be placed to the default flow table resource.
41930 #define HWRM_CFA_FLOW_ALLOC_INPUT_ACTION_FLAGS_PRI_HINT \
41933 * If set to 1 there will be no attempt to allocate an on-chip try
41934 * to offload this flow. If set to 0, which will keep compatibility
41935 * with the older drivers, will cause the FW to attempt to allocate
41936 * an on-chip flow counter for the newly created flow. This will
41937 * keep the existing behavior with EM flows which always had an
41938 * associated flow counter.
41940 #define HWRM_CFA_FLOW_ALLOC_INPUT_ACTION_FLAGS_NO_FLOW_COUNTER_ALLOC \
41943 * Tx Flow: pf or vf fid.
41947 /* VLAN tpid, valid when push_vlan flag is set. */
41948 uint16_t l2_rewrite_vlan_tpid;
41949 /* VLAN tci, valid when push_vlan flag is set. */
41950 uint16_t l2_rewrite_vlan_tci;
41951 /* Meter id, valid when meter flag is set. */
41952 uint16_t act_meter_id;
41953 /* Flow with the same l2 context tcam key. */
41954 uint16_t ref_flow_handle;
41955 /* This value sets the match value for the ethertype. */
41956 uint16_t ethertype;
41957 /* valid when num tags is 1 or 2. */
41958 uint16_t outer_vlan_tci;
41959 /* This value sets the match value for the Destination MAC address. */
41961 /* valid when num tags is 2. */
41962 uint16_t inner_vlan_tci;
41963 /* This value sets the match value for the Source MAC address. */
41965 /* The bit length of destination IP address mask. */
41966 uint8_t ip_dst_mask_len;
41967 /* The bit length of source IP address mask. */
41968 uint8_t ip_src_mask_len;
41969 /* The value of destination IPv4/IPv6 address. */
41970 uint32_t ip_dst[4];
41971 /* The source IPv4/IPv6 address. */
41972 uint32_t ip_src[4];
41974 * The value of source port.
41975 * Applies to UDP and TCP traffic.
41977 uint16_t l4_src_port;
41979 * The value of source port mask.
41980 * Applies to UDP and TCP traffic.
41982 uint16_t l4_src_port_mask;
41984 * The value of destination port.
41985 * Applies to UDP and TCP traffic.
41987 uint16_t l4_dst_port;
41989 * The value of destination port mask.
41990 * Applies to UDP and TCP traffic.
41992 uint16_t l4_dst_port_mask;
41994 * NAT IPv4/6 address based on address type flag.
41995 * 0 values are ignored.
41997 uint32_t nat_ip_address[4];
41998 /* L2 header re-write Destination MAC address. */
41999 uint16_t l2_rewrite_dmac[3];
42001 * The NAT source/destination port based on direction flag.
42002 * Applies to UDP and TCP traffic.
42003 * 0 values are ignored.
42006 /* L2 header re-write Source MAC address. */
42007 uint16_t l2_rewrite_smac[3];
42008 /* The value of ip protocol. */
42011 uint8_t tunnel_type;
42013 #define HWRM_CFA_FLOW_ALLOC_INPUT_TUNNEL_TYPE_NONTUNNEL \
42015 /* Virtual eXtensible Local Area Network (VXLAN) */
42016 #define HWRM_CFA_FLOW_ALLOC_INPUT_TUNNEL_TYPE_VXLAN \
42018 /* Network Virtualization Generic Routing Encapsulation (NVGRE) */
42019 #define HWRM_CFA_FLOW_ALLOC_INPUT_TUNNEL_TYPE_NVGRE \
42021 /* Generic Routing Encapsulation (GRE) inside Ethernet payload */
42022 #define HWRM_CFA_FLOW_ALLOC_INPUT_TUNNEL_TYPE_L2GRE \
42025 #define HWRM_CFA_FLOW_ALLOC_INPUT_TUNNEL_TYPE_IPIP \
42027 /* Generic Network Virtualization Encapsulation (Geneve) */
42028 #define HWRM_CFA_FLOW_ALLOC_INPUT_TUNNEL_TYPE_GENEVE \
42030 /* Multi-Protocol Label Switching (MPLS) */
42031 #define HWRM_CFA_FLOW_ALLOC_INPUT_TUNNEL_TYPE_MPLS \
42033 /* Stateless Transport Tunnel (STT) */
42034 #define HWRM_CFA_FLOW_ALLOC_INPUT_TUNNEL_TYPE_STT \
42036 /* Generic Routing Encapsulation (GRE) inside IP datagram payload */
42037 #define HWRM_CFA_FLOW_ALLOC_INPUT_TUNNEL_TYPE_IPGRE \
42039 /* IPV4 over virtual eXtensible Local Area Network (IPV4oVXLAN) */
42040 #define HWRM_CFA_FLOW_ALLOC_INPUT_TUNNEL_TYPE_VXLAN_V4 \
42043 * Enhance Generic Routing Encapsulation (GRE version 1) inside IP
42046 #define HWRM_CFA_FLOW_ALLOC_INPUT_TUNNEL_TYPE_IPGRE_V1 \
42048 /* Use fixed layer 2 ether type of 0xFFFF */
42049 #define HWRM_CFA_FLOW_ALLOC_INPUT_TUNNEL_TYPE_L2_ETYPE \
42052 * IPV6 over virtual eXtensible Local Area Network with GPE header
42055 #define HWRM_CFA_FLOW_ALLOC_INPUT_TUNNEL_TYPE_VXLAN_GPE_V6 \
42057 /* Any tunneled traffic */
42058 #define HWRM_CFA_FLOW_ALLOC_INPUT_TUNNEL_TYPE_ANYTUNNEL \
42060 #define HWRM_CFA_FLOW_ALLOC_INPUT_TUNNEL_TYPE_LAST \
42061 HWRM_CFA_FLOW_ALLOC_INPUT_TUNNEL_TYPE_ANYTUNNEL
42064 /* hwrm_cfa_flow_alloc_output (size:256b/32B) */
42065 struct hwrm_cfa_flow_alloc_output {
42066 /* The specific error status for the command. */
42067 uint16_t error_code;
42068 /* The HWRM command request type. */
42070 /* The sequence ID from the original command. */
42072 /* The length of the response data in number of bytes. */
42074 /* Flow record index. */
42075 uint16_t flow_handle;
42076 uint8_t unused_0[2];
42078 * The flow id value in bit 0-29 is the actual ID of the flow
42079 * associated with this filter and it shall be used to match
42080 * and associate the flow identifier returned in completion
42081 * records. A value of 0xFFFFFFFF in the 32-bit flow_id field
42082 * shall indicate no valid flow id.
42085 /* Indicate the flow id value. */
42086 #define HWRM_CFA_FLOW_ALLOC_OUTPUT_FLOW_ID_VALUE_MASK \
42087 UINT32_C(0x3fffffff)
42088 #define HWRM_CFA_FLOW_ALLOC_OUTPUT_FLOW_ID_VALUE_SFT 0
42089 /* Indicate type of the flow. */
42090 #define HWRM_CFA_FLOW_ALLOC_OUTPUT_FLOW_ID_TYPE \
42091 UINT32_C(0x40000000)
42093 * If this bit set to 0, then it indicates that the flow is
42096 #define HWRM_CFA_FLOW_ALLOC_OUTPUT_FLOW_ID_TYPE_INT \
42097 (UINT32_C(0x0) << 30)
42099 * If this bit is set to 1, then it indicates that the flow is
42102 #define HWRM_CFA_FLOW_ALLOC_OUTPUT_FLOW_ID_TYPE_EXT \
42103 (UINT32_C(0x1) << 30)
42104 #define HWRM_CFA_FLOW_ALLOC_OUTPUT_FLOW_ID_TYPE_LAST \
42105 HWRM_CFA_FLOW_ALLOC_OUTPUT_FLOW_ID_TYPE_EXT
42106 /* Indicate the flow direction. */
42107 #define HWRM_CFA_FLOW_ALLOC_OUTPUT_FLOW_ID_DIR \
42108 UINT32_C(0x80000000)
42109 /* If this bit set to 0, then it indicates rx flow. */
42110 #define HWRM_CFA_FLOW_ALLOC_OUTPUT_FLOW_ID_DIR_RX \
42111 (UINT32_C(0x0) << 31)
42112 /* If this bit is set to 1, then it indicates that tx flow. */
42113 #define HWRM_CFA_FLOW_ALLOC_OUTPUT_FLOW_ID_DIR_TX \
42114 (UINT32_C(0x1) << 31)
42115 #define HWRM_CFA_FLOW_ALLOC_OUTPUT_FLOW_ID_DIR_LAST \
42116 HWRM_CFA_FLOW_ALLOC_OUTPUT_FLOW_ID_DIR_TX
42117 /* This value identifies a set of CFA data structures used for a flow. */
42118 uint64_t ext_flow_handle;
42119 uint32_t flow_counter_id;
42120 uint8_t unused_1[3];
42122 * This field is used in Output records to indicate that the output
42123 * is completely written to RAM. This field should be read as '1'
42124 * to indicate that the output has been completely written.
42125 * When writing a command completion or response to an internal
42126 * processor, the order of writes has to be such that this field is
42132 /* hwrm_cfa_flow_alloc_cmd_err (size:64b/8B) */
42133 struct hwrm_cfa_flow_alloc_cmd_err {
42135 * command specific error codes that goes to
42136 * the cmd_err field in Common HWRM Error Response.
42139 /* Unknown error */
42140 #define HWRM_CFA_FLOW_ALLOC_CMD_ERR_CODE_UNKNOWN UINT32_C(0x0)
42141 /* No more L2 Context TCAM */
42142 #define HWRM_CFA_FLOW_ALLOC_CMD_ERR_CODE_L2_CONTEXT_TCAM UINT32_C(0x1)
42143 /* No more action records */
42144 #define HWRM_CFA_FLOW_ALLOC_CMD_ERR_CODE_ACTION_RECORD UINT32_C(0x2)
42145 /* No more flow counters */
42146 #define HWRM_CFA_FLOW_ALLOC_CMD_ERR_CODE_FLOW_COUNTER UINT32_C(0x3)
42147 /* No more wild-card TCAM */
42148 #define HWRM_CFA_FLOW_ALLOC_CMD_ERR_CODE_WILD_CARD_TCAM UINT32_C(0x4)
42149 /* Hash collision in exact match tables */
42150 #define HWRM_CFA_FLOW_ALLOC_CMD_ERR_CODE_HASH_COLLISION UINT32_C(0x5)
42151 /* Key is already installed */
42152 #define HWRM_CFA_FLOW_ALLOC_CMD_ERR_CODE_KEY_EXISTS UINT32_C(0x6)
42153 /* Flow Context DB is out of resource */
42154 #define HWRM_CFA_FLOW_ALLOC_CMD_ERR_CODE_FLOW_CTXT_DB UINT32_C(0x7)
42155 #define HWRM_CFA_FLOW_ALLOC_CMD_ERR_CODE_LAST \
42156 HWRM_CFA_FLOW_ALLOC_CMD_ERR_CODE_FLOW_CTXT_DB
42157 uint8_t unused_0[7];
42160 /**********************
42161 * hwrm_cfa_flow_free *
42162 **********************/
42165 /* hwrm_cfa_flow_free_input (size:256b/32B) */
42166 struct hwrm_cfa_flow_free_input {
42167 /* The HWRM command request type. */
42170 * The completion ring to send the completion event on. This should
42171 * be the NQ ID returned from the `nq_alloc` HWRM command.
42173 uint16_t cmpl_ring;
42175 * The sequence ID is used by the driver for tracking multiple
42176 * commands. This ID is treated as opaque data by the firmware and
42177 * the value is returned in the `hwrm_resp_hdr` upon completion.
42181 * The target ID of the command:
42182 * * 0x0-0xFFF8 - The function ID
42183 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
42184 * * 0xFFFD - Reserved for user-space HWRM interface
42187 uint16_t target_id;
42189 * A physical address pointer pointing to a host buffer that the
42190 * command's response data will be written. This can be either a host
42191 * physical address (HPA) or a guest physical address (GPA) and must
42192 * point to a physically contiguous block of memory.
42194 uint64_t resp_addr;
42195 /* Flow record index. */
42196 uint16_t flow_handle;
42198 /* Flow counter id to be freed. */
42199 uint32_t flow_counter_id;
42200 /* This value identifies a set of CFA data structures used for a flow. */
42201 uint64_t ext_flow_handle;
42204 /* hwrm_cfa_flow_free_output (size:256b/32B) */
42205 struct hwrm_cfa_flow_free_output {
42206 /* The specific error status for the command. */
42207 uint16_t error_code;
42208 /* The HWRM command request type. */
42210 /* The sequence ID from the original command. */
42212 /* The length of the response data in number of bytes. */
42214 /* packet is 64 b */
42218 uint8_t unused_0[7];
42220 * This field is used in Output records to indicate that the output
42221 * is completely written to RAM. This field should be read as '1'
42222 * to indicate that the output has been completely written.
42223 * When writing a command completion or response to an internal
42224 * processor, the order of writes has to be such that this field is
42230 /* hwrm_cfa_flow_action_data (size:960b/120B) */
42231 struct hwrm_cfa_flow_action_data {
42232 uint16_t action_flags;
42233 /* Setting of this flag indicates accept action. */
42234 #define HWRM_CFA_FLOW_ACTION_DATA_ACTION_FLAGS_FWD \
42236 /* Setting of this flag indicates recycle action. */
42237 #define HWRM_CFA_FLOW_ACTION_DATA_ACTION_FLAGS_RECYCLE \
42239 /* Setting of this flag indicates drop action. */
42240 #define HWRM_CFA_FLOW_ACTION_DATA_ACTION_FLAGS_DROP \
42242 /* Setting of this flag indicates meter action. */
42243 #define HWRM_CFA_FLOW_ACTION_DATA_ACTION_FLAGS_METER \
42245 /* Setting of this flag indicates tunnel action. */
42246 #define HWRM_CFA_FLOW_ACTION_DATA_ACTION_FLAGS_TUNNEL \
42249 * If set to 1 and flow direction is TX, it indicates decap of L2
42250 * header and encap of tunnel header. If set to 1 and flow direction
42251 * is RX, it indicates decap of tunnel header and encap L2 header.
42253 #define HWRM_CFA_FLOW_ACTION_DATA_ACTION_FLAGS_TUNNEL_IP \
42255 /* Setting of this flag indicates ttl decrement action. */
42256 #define HWRM_CFA_FLOW_ACTION_DATA_ACTION_FLAGS_TTL_DECREMENT \
42258 /* If set to 1, flow aging is enabled for this flow. */
42259 #define HWRM_CFA_FLOW_ACTION_DATA_ACTION_FLAGS_FLOW_AGING_ENABLED \
42261 /* Setting of this flag indicates encap action. */
42262 #define HWRM_CFA_FLOW_ACTION_DATA_ACTION_FLAGS_ENCAP \
42264 /* Setting of this flag indicates decap action. */
42265 #define HWRM_CFA_FLOW_ACTION_DATA_ACTION_FLAGS_DECAP \
42268 uint16_t act_meter_id;
42271 /* vport number. */
42273 /* The NAT source/destination. */
42275 uint16_t unused_0[3];
42276 /* NAT IPv4/IPv6 address. */
42277 uint32_t nat_ip_address[4];
42278 /* Encapsulation Type. */
42279 uint8_t encap_type;
42280 /* Virtual eXtensible Local Area Network (VXLAN) */
42281 #define HWRM_CFA_FLOW_ACTION_DATA_ENCAP_TYPE_VXLAN UINT32_C(0x1)
42282 /* Network Virtualization Generic Routing Encapsulation (NVGRE) */
42283 #define HWRM_CFA_FLOW_ACTION_DATA_ENCAP_TYPE_NVGRE UINT32_C(0x2)
42284 /* Generic Routing Encapsulation (GRE) after inside Ethernet payload */
42285 #define HWRM_CFA_FLOW_ACTION_DATA_ENCAP_TYPE_L2GRE UINT32_C(0x3)
42287 #define HWRM_CFA_FLOW_ACTION_DATA_ENCAP_TYPE_IPIP UINT32_C(0x4)
42288 /* Generic Network Virtualization Encapsulation (Geneve) */
42289 #define HWRM_CFA_FLOW_ACTION_DATA_ENCAP_TYPE_GENEVE UINT32_C(0x5)
42290 /* Multi-Protocol Label Switching (MPLS) */
42291 #define HWRM_CFA_FLOW_ACTION_DATA_ENCAP_TYPE_MPLS UINT32_C(0x6)
42293 #define HWRM_CFA_FLOW_ACTION_DATA_ENCAP_TYPE_VLAN UINT32_C(0x7)
42294 /* Generic Routing Encapsulation (GRE) inside IP datagram payload */
42295 #define HWRM_CFA_FLOW_ACTION_DATA_ENCAP_TYPE_IPGRE UINT32_C(0x8)
42296 /* IPV4 over virtual eXtensible Local Area Network (IPV4oVXLAN) */
42297 #define HWRM_CFA_FLOW_ACTION_DATA_ENCAP_TYPE_VXLAN_V4 UINT32_C(0x9)
42299 * Enhance Generic Routing Encapsulation (GRE version 1) inside IP
42302 #define HWRM_CFA_FLOW_ACTION_DATA_ENCAP_TYPE_IPGRE_V1 UINT32_C(0xa)
42303 /* Use fixed layer 2 ether type of 0xFFFF */
42304 #define HWRM_CFA_FLOW_ACTION_DATA_ENCAP_TYPE_L2_ETYPE UINT32_C(0xb)
42306 * IPV6 over virtual eXtensible Local Area Network with GPE header
42309 #define HWRM_CFA_FLOW_ACTION_DATA_ENCAP_TYPE_VXLAN_GPE_V6 UINT32_C(0xc)
42310 #define HWRM_CFA_FLOW_ACTION_DATA_ENCAP_TYPE_LAST \
42311 HWRM_CFA_FLOW_ACTION_DATA_ENCAP_TYPE_VXLAN_GPE_V6
42313 /* This value is encap data for the associated encap type. */
42314 uint32_t encap_data[20];
42317 /* hwrm_cfa_flow_tunnel_hdr_data (size:64b/8B) */
42318 struct hwrm_cfa_flow_tunnel_hdr_data {
42320 uint8_t tunnel_type;
42322 #define HWRM_CFA_FLOW_TUNNEL_HDR_DATA_TUNNEL_TYPE_NONTUNNEL \
42324 /* Virtual eXtensible Local Area Network (VXLAN) */
42325 #define HWRM_CFA_FLOW_TUNNEL_HDR_DATA_TUNNEL_TYPE_VXLAN \
42327 /* Network Virtualization Generic Routing Encapsulation (NVGRE) */
42328 #define HWRM_CFA_FLOW_TUNNEL_HDR_DATA_TUNNEL_TYPE_NVGRE \
42330 /* Generic Routing Encapsulation (GRE) inside Ethernet payload */
42331 #define HWRM_CFA_FLOW_TUNNEL_HDR_DATA_TUNNEL_TYPE_L2GRE \
42334 #define HWRM_CFA_FLOW_TUNNEL_HDR_DATA_TUNNEL_TYPE_IPIP \
42336 /* Generic Network Virtualization Encapsulation (Geneve) */
42337 #define HWRM_CFA_FLOW_TUNNEL_HDR_DATA_TUNNEL_TYPE_GENEVE \
42339 /* Multi-Protocol Label Switching (MPLS) */
42340 #define HWRM_CFA_FLOW_TUNNEL_HDR_DATA_TUNNEL_TYPE_MPLS \
42342 /* Stateless Transport Tunnel (STT) */
42343 #define HWRM_CFA_FLOW_TUNNEL_HDR_DATA_TUNNEL_TYPE_STT \
42345 /* Generic Routing Encapsulation (GRE) inside IP datagram payload */
42346 #define HWRM_CFA_FLOW_TUNNEL_HDR_DATA_TUNNEL_TYPE_IPGRE \
42348 /* IPV4 over virtual eXtensible Local Area Network (IPV4oVXLAN) */
42349 #define HWRM_CFA_FLOW_TUNNEL_HDR_DATA_TUNNEL_TYPE_VXLAN_V4 \
42352 * Enhance Generic Routing Encapsulation (GRE version 1) inside IP
42355 #define HWRM_CFA_FLOW_TUNNEL_HDR_DATA_TUNNEL_TYPE_IPGRE_V1 \
42357 /* Use fixed layer 2 ether type of 0xFFFF */
42358 #define HWRM_CFA_FLOW_TUNNEL_HDR_DATA_TUNNEL_TYPE_L2_ETYPE \
42361 * IPV6 over virtual eXtensible Local Area Network with GPE header
42364 #define HWRM_CFA_FLOW_TUNNEL_HDR_DATA_TUNNEL_TYPE_VXLAN_GPE_V6 \
42366 /* Any tunneled traffic */
42367 #define HWRM_CFA_FLOW_TUNNEL_HDR_DATA_TUNNEL_TYPE_ANYTUNNEL \
42369 #define HWRM_CFA_FLOW_TUNNEL_HDR_DATA_TUNNEL_TYPE_LAST \
42370 HWRM_CFA_FLOW_TUNNEL_HDR_DATA_TUNNEL_TYPE_ANYTUNNEL
42373 * Tunnel identifier.
42374 * Virtual Network Identifier (VNI).
42376 uint32_t tunnel_id;
42379 /* hwrm_cfa_flow_l4_key_data (size:64b/8B) */
42380 struct hwrm_cfa_flow_l4_key_data {
42381 /* The value of source port. */
42382 uint16_t l4_src_port;
42383 /* The value of destination port. */
42384 uint16_t l4_dst_port;
42388 /* hwrm_cfa_flow_l3_key_data (size:512b/64B) */
42389 struct hwrm_cfa_flow_l3_key_data {
42390 /* The value of ip protocol. */
42391 uint8_t ip_protocol;
42392 uint8_t unused_0[7];
42393 /* The value of destination IPv4/IPv6 address. */
42394 uint32_t ip_dst[4];
42395 /* The source IPv4/IPv6 address. */
42396 uint32_t ip_src[4];
42397 /* NAT IPv4/IPv6 address. */
42398 uint32_t nat_ip_address[4];
42399 uint32_t unused[2];
42402 /* hwrm_cfa_flow_l2_key_data (size:448b/56B) */
42403 struct hwrm_cfa_flow_l2_key_data {
42404 /* Destination MAC address. */
42407 /* Source MAC address. */
42410 /* L2 header re-write Destination MAC address. */
42411 uint16_t l2_rewrite_dmac[3];
42413 /* L2 header re-write Source MAC address. */
42414 uint16_t l2_rewrite_smac[3];
42416 uint16_t ethertype;
42417 /* Number of VLAN tags. */
42418 uint16_t num_vlan_tags;
42420 uint16_t l2_rewrite_vlan_tpid;
42422 uint16_t l2_rewrite_vlan_tci;
42423 uint8_t unused_3[2];
42424 /* Outer VLAN TPID. */
42425 uint16_t ovlan_tpid;
42426 /* Outer VLAN TCI. */
42427 uint16_t ovlan_tci;
42428 /* Inner VLAN TPID. */
42429 uint16_t ivlan_tpid;
42430 /* Inner VLAN TCI. */
42431 uint16_t ivlan_tci;
42435 /* hwrm_cfa_flow_key_data (size:4160b/520B) */
42436 struct hwrm_cfa_flow_key_data {
42437 /* Flow associated tunnel L2 header key info. */
42438 uint32_t t_l2_key_data[14];
42439 /* Flow associated tunnel L2 header mask info. */
42440 uint32_t t_l2_key_mask[14];
42441 /* Flow associated tunnel L3 header key info. */
42442 uint32_t t_l3_key_data[16];
42443 /* Flow associated tunnel L3 header mask info. */
42444 uint32_t t_l3_key_mask[16];
42445 /* Flow associated tunnel L4 header key info. */
42446 uint32_t t_l4_key_data[2];
42447 /* Flow associated tunnel L4 header mask info. */
42448 uint32_t t_l4_key_mask[2];
42449 /* Flow associated tunnel header info. */
42450 uint32_t tunnel_hdr[2];
42451 /* Flow associated L2 header key info. */
42452 uint32_t l2_key_data[14];
42453 /* Flow associated L2 header mask info. */
42454 uint32_t l2_key_mask[14];
42455 /* Flow associated L3 header key info. */
42456 uint32_t l3_key_data[16];
42457 /* Flow associated L3 header mask info. */
42458 uint32_t l3_key_mask[16];
42459 /* Flow associated L4 header key info. */
42460 uint32_t l4_key_data[2];
42461 /* Flow associated L4 header mask info. */
42462 uint32_t l4_key_mask[2];
42465 /**********************
42466 * hwrm_cfa_flow_info *
42467 **********************/
42470 /* hwrm_cfa_flow_info_input (size:256b/32B) */
42471 struct hwrm_cfa_flow_info_input {
42472 /* The HWRM command request type. */
42475 * The completion ring to send the completion event on. This should
42476 * be the NQ ID returned from the `nq_alloc` HWRM command.
42478 uint16_t cmpl_ring;
42480 * The sequence ID is used by the driver for tracking multiple
42481 * commands. This ID is treated as opaque data by the firmware and
42482 * the value is returned in the `hwrm_resp_hdr` upon completion.
42486 * The target ID of the command:
42487 * * 0x0-0xFFF8 - The function ID
42488 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
42489 * * 0xFFFD - Reserved for user-space HWRM interface
42492 uint16_t target_id;
42494 * A physical address pointer pointing to a host buffer that the
42495 * command's response data will be written. This can be either a host
42496 * physical address (HPA) or a guest physical address (GPA) and must
42497 * point to a physically contiguous block of memory.
42499 uint64_t resp_addr;
42500 /* Flow record index. */
42501 uint16_t flow_handle;
42502 /* Max flow handle */
42503 #define HWRM_CFA_FLOW_INFO_INPUT_FLOW_HANDLE_MAX_MASK \
42505 #define HWRM_CFA_FLOW_INFO_INPUT_FLOW_HANDLE_MAX_SFT 0
42506 /* CNP flow handle */
42507 #define HWRM_CFA_FLOW_INFO_INPUT_FLOW_HANDLE_CNP_CNT \
42509 /* RoCEv1 flow handle */
42510 #define HWRM_CFA_FLOW_INFO_INPUT_FLOW_HANDLE_ROCEV1_CNT \
42512 /* RoCEv2 flow handle */
42513 #define HWRM_CFA_FLOW_INFO_INPUT_FLOW_HANDLE_ROCEV2_CNT \
42515 /* Direction rx = 1 */
42516 #define HWRM_CFA_FLOW_INFO_INPUT_FLOW_HANDLE_DIR_RX \
42518 uint8_t unused_0[6];
42519 /* This value identifies a set of CFA data structures used for a flow. */
42520 uint64_t ext_flow_handle;
42523 /* hwrm_cfa_flow_info_output (size:5632b/704B) */
42524 struct hwrm_cfa_flow_info_output {
42525 /* The specific error status for the command. */
42526 uint16_t error_code;
42527 /* The HWRM command request type. */
42529 /* The sequence ID from the original command. */
42531 /* The length of the response data in number of bytes. */
42534 /* When set to 1, indicates the configuration is the TX flow. */
42535 #define HWRM_CFA_FLOW_INFO_OUTPUT_FLAGS_PATH_TX UINT32_C(0x1)
42536 /* When set to 1, indicates the configuration is the RX flow. */
42537 #define HWRM_CFA_FLOW_INFO_OUTPUT_FLAGS_PATH_RX UINT32_C(0x2)
42538 /* profile is 8 b */
42540 /* src_fid is 16 b */
42542 /* dst_fid is 16 b */
42544 /* l2_ctxt_id is 16 b */
42545 uint16_t l2_ctxt_id;
42546 /* em_info is 64 b */
42548 /* tcam_info is 64 b */
42549 uint64_t tcam_info;
42550 /* vfp_tcam_info is 64 b */
42551 uint64_t vfp_tcam_info;
42552 /* ar_id is 16 b */
42554 /* flow_handle is 16 b */
42555 uint16_t flow_handle;
42556 /* tunnel_handle is 32 b */
42557 uint32_t tunnel_handle;
42558 /* The flow aging timer for the flow, the unit is 100 milliseconds */
42559 uint16_t flow_timer;
42560 uint8_t unused_0[6];
42561 /* Flow associated L2, L3 and L4 headers info. */
42562 uint32_t flow_key_data[130];
42563 /* Flow associated action record info. */
42564 uint32_t flow_action_info[30];
42565 uint8_t unused_1[7];
42567 * This field is used in Output records to indicate that the output
42568 * is completely written to RAM. This field should be read as '1'
42569 * to indicate that the output has been completely written.
42570 * When writing a command completion or response to an internal
42571 * processor, the order of writes has to be such that this field is
42577 /***********************
42578 * hwrm_cfa_flow_flush *
42579 ***********************/
42582 /* hwrm_cfa_flow_flush_input (size:256b/32B) */
42583 struct hwrm_cfa_flow_flush_input {
42584 /* The HWRM command request type. */
42587 * The completion ring to send the completion event on. This should
42588 * be the NQ ID returned from the `nq_alloc` HWRM command.
42590 uint16_t cmpl_ring;
42592 * The sequence ID is used by the driver for tracking multiple
42593 * commands. This ID is treated as opaque data by the firmware and
42594 * the value is returned in the `hwrm_resp_hdr` upon completion.
42598 * The target ID of the command:
42599 * * 0x0-0xFFF8 - The function ID
42600 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
42601 * * 0xFFFD - Reserved for user-space HWRM interface
42604 uint16_t target_id;
42606 * A physical address pointer pointing to a host buffer that the
42607 * command's response data will be written. This can be either a host
42608 * physical address (HPA) or a guest physical address (GPA) and must
42609 * point to a physically contiguous block of memory.
42611 uint64_t resp_addr;
42612 /* flags is 32 b */
42615 * Set to 1 to indicate the page size, page layers, and
42616 * flow_handle_table_dma_addr fields are valid. The flow flush
42617 * operation should only flush the flows from the flow table
42618 * specified. This flag is set to 0 by older driver. For older
42619 * firmware, setting this flag has no effect.
42621 #define HWRM_CFA_FLOW_FLUSH_INPUT_FLAGS_FLOW_TABLE_VALID \
42624 * Set to 1 to indicate flow flush operation to cleanup all the
42625 * flows, meters, CFA context memory tables etc. This flag is set to
42626 * 0 by older driver. For older firmware, setting this flag has no
42629 #define HWRM_CFA_FLOW_FLUSH_INPUT_FLAGS_FLOW_RESET_ALL \
42632 * Set to 1 to indicate flow flush operation to cleanup all the
42633 * flows by the caller. This flag is set to 0 by older driver. For
42634 * older firmware, setting this flag has no effect.
42636 #define HWRM_CFA_FLOW_FLUSH_INPUT_FLAGS_FLOW_RESET_PORT \
42639 * Set to 1 to indicate the flow counter IDs are included in the
42642 #define HWRM_CFA_FLOW_FLUSH_INPUT_FLAGS_FLOW_HANDLE_INCL_FC \
42643 UINT32_C(0x8000000)
42645 * This specifies the size of flow handle entries provided by the
42646 * driver in the flow table specified below. Only two flow handle
42647 * size enums are defined.
42649 #define HWRM_CFA_FLOW_FLUSH_INPUT_FLAGS_FLOW_HANDLE_ENTRY_SIZE_MASK \
42650 UINT32_C(0xc0000000)
42651 #define HWRM_CFA_FLOW_FLUSH_INPUT_FLAGS_FLOW_HANDLE_ENTRY_SIZE_SFT \
42653 /* The flow handle is 16bit */
42654 #define HWRM_CFA_FLOW_FLUSH_INPUT_FLAGS_FLOW_HANDLE_ENTRY_SIZE_FLOW_HND_16BIT \
42655 (UINT32_C(0x0) << 30)
42656 /* The flow handle is 64bit */
42657 #define HWRM_CFA_FLOW_FLUSH_INPUT_FLAGS_FLOW_HANDLE_ENTRY_SIZE_FLOW_HND_64BIT \
42658 (UINT32_C(0x1) << 30)
42659 #define HWRM_CFA_FLOW_FLUSH_INPUT_FLAGS_FLOW_HANDLE_ENTRY_SIZE_LAST \
42660 HWRM_CFA_FLOW_FLUSH_INPUT_FLAGS_FLOW_HANDLE_ENTRY_SIZE_FLOW_HND_64BIT
42661 /* Specify page size of the flow table memory. */
42663 /* The page size is 4K */
42664 #define HWRM_CFA_FLOW_FLUSH_INPUT_PAGE_SIZE_4K UINT32_C(0x0)
42665 /* The page size is 8K */
42666 #define HWRM_CFA_FLOW_FLUSH_INPUT_PAGE_SIZE_8K UINT32_C(0x1)
42667 /* The page size is 64K */
42668 #define HWRM_CFA_FLOW_FLUSH_INPUT_PAGE_SIZE_64K UINT32_C(0x4)
42669 /* The page size is 256K */
42670 #define HWRM_CFA_FLOW_FLUSH_INPUT_PAGE_SIZE_256K UINT32_C(0x6)
42671 /* The page size is 1M */
42672 #define HWRM_CFA_FLOW_FLUSH_INPUT_PAGE_SIZE_1M UINT32_C(0x8)
42673 /* The page size is 2M */
42674 #define HWRM_CFA_FLOW_FLUSH_INPUT_PAGE_SIZE_2M UINT32_C(0x9)
42675 /* The page size is 4M */
42676 #define HWRM_CFA_FLOW_FLUSH_INPUT_PAGE_SIZE_4M UINT32_C(0xa)
42677 /* The page size is 1G */
42678 #define HWRM_CFA_FLOW_FLUSH_INPUT_PAGE_SIZE_1G UINT32_C(0x12)
42679 #define HWRM_CFA_FLOW_FLUSH_INPUT_PAGE_SIZE_LAST \
42680 HWRM_CFA_FLOW_FLUSH_INPUT_PAGE_SIZE_1G
42681 /* FLow table memory indirect levels. */
42682 uint8_t page_level;
42683 /* PBL pointer is physical start address. */
42684 #define HWRM_CFA_FLOW_FLUSH_INPUT_PAGE_LEVEL_LVL_0 UINT32_C(0x0)
42685 /* PBL pointer points to PTE table. */
42686 #define HWRM_CFA_FLOW_FLUSH_INPUT_PAGE_LEVEL_LVL_1 UINT32_C(0x1)
42688 * PBL pointer points to PDE table with each entry pointing to PTE
42691 #define HWRM_CFA_FLOW_FLUSH_INPUT_PAGE_LEVEL_LVL_2 UINT32_C(0x2)
42692 #define HWRM_CFA_FLOW_FLUSH_INPUT_PAGE_LEVEL_LAST \
42693 HWRM_CFA_FLOW_FLUSH_INPUT_PAGE_LEVEL_LVL_2
42694 /* number of flows in the flow table */
42695 uint16_t num_flows;
42696 /* Pointer to the PBL, or PDL depending on number of levels */
42700 /* hwrm_cfa_flow_flush_output (size:128b/16B) */
42701 struct hwrm_cfa_flow_flush_output {
42702 /* The specific error status for the command. */
42703 uint16_t error_code;
42704 /* The HWRM command request type. */
42706 /* The sequence ID from the original command. */
42708 /* The length of the response data in number of bytes. */
42710 uint8_t unused_0[7];
42712 * This field is used in Output records to indicate that the output
42713 * is completely written to RAM. This field should be read as '1'
42714 * to indicate that the output has been completely written.
42715 * When writing a command completion or response to an internal
42716 * processor, the order of writes has to be such that this field is
42722 /***********************
42723 * hwrm_cfa_flow_stats *
42724 ***********************/
42727 /* hwrm_cfa_flow_stats_input (size:640b/80B) */
42728 struct hwrm_cfa_flow_stats_input {
42729 /* The HWRM command request type. */
42732 * The completion ring to send the completion event on. This should
42733 * be the NQ ID returned from the `nq_alloc` HWRM command.
42735 uint16_t cmpl_ring;
42737 * The sequence ID is used by the driver for tracking multiple
42738 * commands. This ID is treated as opaque data by the firmware and
42739 * the value is returned in the `hwrm_resp_hdr` upon completion.
42743 * The target ID of the command:
42744 * * 0x0-0xFFF8 - The function ID
42745 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
42746 * * 0xFFFD - Reserved for user-space HWRM interface
42749 uint16_t target_id;
42751 * A physical address pointer pointing to a host buffer that the
42752 * command's response data will be written. This can be either a host
42753 * physical address (HPA) or a guest physical address (GPA) and must
42754 * point to a physically contiguous block of memory.
42756 uint64_t resp_addr;
42758 uint16_t num_flows;
42760 uint16_t flow_handle_0;
42762 uint16_t flow_handle_1;
42764 uint16_t flow_handle_2;
42766 uint16_t flow_handle_3;
42768 uint16_t flow_handle_4;
42770 uint16_t flow_handle_5;
42772 uint16_t flow_handle_6;
42774 uint16_t flow_handle_7;
42776 uint16_t flow_handle_8;
42778 uint16_t flow_handle_9;
42779 uint8_t unused_0[2];
42780 /* Flow ID of a flow. */
42781 uint32_t flow_id_0;
42782 /* Flow ID of a flow. */
42783 uint32_t flow_id_1;
42784 /* Flow ID of a flow. */
42785 uint32_t flow_id_2;
42786 /* Flow ID of a flow. */
42787 uint32_t flow_id_3;
42788 /* Flow ID of a flow. */
42789 uint32_t flow_id_4;
42790 /* Flow ID of a flow. */
42791 uint32_t flow_id_5;
42792 /* Flow ID of a flow. */
42793 uint32_t flow_id_6;
42794 /* Flow ID of a flow. */
42795 uint32_t flow_id_7;
42796 /* Flow ID of a flow. */
42797 uint32_t flow_id_8;
42798 /* Flow ID of a flow. */
42799 uint32_t flow_id_9;
42802 /* hwrm_cfa_flow_stats_output (size:1408b/176B) */
42803 struct hwrm_cfa_flow_stats_output {
42804 /* The specific error status for the command. */
42805 uint16_t error_code;
42806 /* The HWRM command request type. */
42808 /* The sequence ID from the original command. */
42810 /* The length of the response data in number of bytes. */
42812 /* packet_0 is 64 b */
42814 /* packet_1 is 64 b */
42816 /* packet_2 is 64 b */
42818 /* packet_3 is 64 b */
42820 /* packet_4 is 64 b */
42822 /* packet_5 is 64 b */
42824 /* packet_6 is 64 b */
42826 /* packet_7 is 64 b */
42828 /* packet_8 is 64 b */
42830 /* packet_9 is 64 b */
42832 /* byte_0 is 64 b */
42834 /* byte_1 is 64 b */
42836 /* byte_2 is 64 b */
42838 /* byte_3 is 64 b */
42840 /* byte_4 is 64 b */
42842 /* byte_5 is 64 b */
42844 /* byte_6 is 64 b */
42846 /* byte_7 is 64 b */
42848 /* byte_8 is 64 b */
42850 /* byte_9 is 64 b */
42852 uint8_t unused_0[7];
42854 * This field is used in Output records to indicate that the output
42855 * is completely written to RAM. This field should be read as '1'
42856 * to indicate that the output has been completely written.
42857 * When writing a command completion or response to an internal
42858 * processor, the order of writes has to be such that this field is
42864 /***********************************
42865 * hwrm_cfa_flow_aging_timer_reset *
42866 ***********************************/
42869 /* hwrm_cfa_flow_aging_timer_reset_input (size:256b/32B) */
42870 struct hwrm_cfa_flow_aging_timer_reset_input {
42871 /* The HWRM command request type. */
42874 * The completion ring to send the completion event on. This should
42875 * be the NQ ID returned from the `nq_alloc` HWRM command.
42877 uint16_t cmpl_ring;
42879 * The sequence ID is used by the driver for tracking multiple
42880 * commands. This ID is treated as opaque data by the firmware and
42881 * the value is returned in the `hwrm_resp_hdr` upon completion.
42885 * The target ID of the command:
42886 * * 0x0-0xFFF8 - The function ID
42887 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
42888 * * 0xFFFD - Reserved for user-space HWRM interface
42891 uint16_t target_id;
42893 * A physical address pointer pointing to a host buffer that the
42894 * command's response data will be written. This can be either a host
42895 * physical address (HPA) or a guest physical address (GPA) and must
42896 * point to a physically contiguous block of memory.
42898 uint64_t resp_addr;
42899 /* Flow record index. */
42900 uint16_t flow_handle;
42901 uint8_t unused_0[2];
42903 * New flow timer value for the flow specified in the ext_flow_handle.
42904 * The flow timer unit is 100ms.
42906 uint32_t flow_timer;
42907 /* This value identifies a set of CFA data structures used for a flow. */
42908 uint64_t ext_flow_handle;
42911 /* hwrm_cfa_flow_aging_timer_reset_output (size:128b/16B) */
42912 struct hwrm_cfa_flow_aging_timer_reset_output {
42913 /* The specific error status for the command. */
42914 uint16_t error_code;
42915 /* The HWRM command request type. */
42917 /* The sequence ID from the original command. */
42919 /* The length of the response data in number of bytes. */
42921 uint8_t unused_0[7];
42923 * This field is used in Output records to indicate that the output
42924 * is completely written to RAM. This field should be read as '1'
42925 * to indicate that the output has been completely written.
42926 * When writing a command completion or response to an internal
42927 * processor, the order of writes has to be such that this field is
42933 /***************************
42934 * hwrm_cfa_flow_aging_cfg *
42935 ***************************/
42938 /* hwrm_cfa_flow_aging_cfg_input (size:384b/48B) */
42939 struct hwrm_cfa_flow_aging_cfg_input {
42940 /* The HWRM command request type. */
42943 * The completion ring to send the completion event on. This should
42944 * be the NQ ID returned from the `nq_alloc` HWRM command.
42946 uint16_t cmpl_ring;
42948 * The sequence ID is used by the driver for tracking multiple
42949 * commands. This ID is treated as opaque data by the firmware and
42950 * the value is returned in the `hwrm_resp_hdr` upon completion.
42954 * The target ID of the command:
42955 * * 0x0-0xFFF8 - The function ID
42956 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
42957 * * 0xFFFD - Reserved for user-space HWRM interface
42960 uint16_t target_id;
42962 * A physical address pointer pointing to a host buffer that the
42963 * command's response data will be written. This can be either a host
42964 * physical address (HPA) or a guest physical address (GPA) and must
42965 * point to a physically contiguous block of memory.
42967 uint64_t resp_addr;
42968 /* The bit field to enable per flow aging configuration. */
42971 * This bit must be '1' for the tcp flow timer field to be
42974 #define HWRM_CFA_FLOW_AGING_CFG_INPUT_ENABLES_TCP_FLOW_TIMER \
42977 * This bit must be '1' for the tcp finish timer field to be
42980 #define HWRM_CFA_FLOW_AGING_CFG_INPUT_ENABLES_TCP_FIN_TIMER \
42983 * This bit must be '1' for the udp flow timer field to be
42986 #define HWRM_CFA_FLOW_AGING_CFG_INPUT_ENABLES_UDP_FLOW_TIMER \
42989 * This bit must be '1' for the eem dma interval field to be
42992 #define HWRM_CFA_FLOW_AGING_CFG_INPUT_ENABLES_EEM_DMA_INTERVAL \
42995 * This bit must be '1' for the eem notice interval field to be
42998 #define HWRM_CFA_FLOW_AGING_CFG_INPUT_ENABLES_EEM_NOTICE_INTERVAL \
43001 * This bit must be '1' for the eem context memory maximum entries
43002 * field to be configured
43004 #define HWRM_CFA_FLOW_AGING_CFG_INPUT_ENABLES_EEM_CTX_MAX_ENTRIES \
43007 * This bit must be '1' for the eem context memory ID field to be
43010 #define HWRM_CFA_FLOW_AGING_CFG_INPUT_ENABLES_EEM_CTX_ID \
43013 * This bit must be '1' for the eem context memory type field to be
43016 #define HWRM_CFA_FLOW_AGING_CFG_INPUT_ENABLES_EEM_CTX_MEM_TYPE \
43019 /* Enumeration denoting the RX, TX type of the resource. */
43020 #define HWRM_CFA_FLOW_AGING_CFG_INPUT_FLAGS_PATH UINT32_C(0x1)
43022 #define HWRM_CFA_FLOW_AGING_CFG_INPUT_FLAGS_PATH_TX UINT32_C(0x0)
43024 #define HWRM_CFA_FLOW_AGING_CFG_INPUT_FLAGS_PATH_RX UINT32_C(0x1)
43025 #define HWRM_CFA_FLOW_AGING_CFG_INPUT_FLAGS_PATH_LAST \
43026 HWRM_CFA_FLOW_AGING_CFG_INPUT_FLAGS_PATH_RX
43028 * Enumeration denoting the enable, disable eem flow aging
43031 #define HWRM_CFA_FLOW_AGING_CFG_INPUT_FLAGS_EEM UINT32_C(0x2)
43033 #define HWRM_CFA_FLOW_AGING_CFG_INPUT_FLAGS_EEM_DISABLE \
43034 (UINT32_C(0x0) << 1)
43036 #define HWRM_CFA_FLOW_AGING_CFG_INPUT_FLAGS_EEM_ENABLE \
43037 (UINT32_C(0x1) << 1)
43038 #define HWRM_CFA_FLOW_AGING_CFG_INPUT_FLAGS_EEM_LAST \
43039 HWRM_CFA_FLOW_AGING_CFG_INPUT_FLAGS_EEM_ENABLE
43042 * The flow aging timer for all TCP flows, the unit is 100
43045 uint32_t tcp_flow_timer;
43047 * The TCP finished timer for all TCP flows, the unit is 100
43050 uint32_t tcp_fin_timer;
43052 * The flow aging timer for all UDP flows, the unit is 100
43055 uint32_t udp_flow_timer;
43057 * The interval to dma eem ejection data to host memory, the unit is
43060 uint16_t eem_dma_interval;
43062 * The interval to notify driver to read the eem ejection data, the
43063 * unit is milliseconds.
43065 uint16_t eem_notice_interval;
43066 /* The maximum entries number in the eem context memory. */
43067 uint32_t eem_ctx_max_entries;
43068 /* The context memory ID for eem flow aging. */
43069 uint16_t eem_ctx_id;
43070 uint16_t eem_ctx_mem_type;
43072 * The content of context memory is eem ejection data, the size of
43073 * each entry is 4 bytes.
43075 #define HWRM_CFA_FLOW_AGING_CFG_INPUT_EEM_CTX_MEM_TYPE_EJECTION_DATA \
43077 #define HWRM_CFA_FLOW_AGING_CFG_INPUT_EEM_CTX_MEM_TYPE_LAST \
43078 HWRM_CFA_FLOW_AGING_CFG_INPUT_EEM_CTX_MEM_TYPE_EJECTION_DATA
43079 uint8_t unused_1[4];
43082 /* hwrm_cfa_flow_aging_cfg_output (size:128b/16B) */
43083 struct hwrm_cfa_flow_aging_cfg_output {
43084 /* The specific error status for the command. */
43085 uint16_t error_code;
43086 /* The HWRM command request type. */
43088 /* The sequence ID from the original command. */
43090 /* The length of the response data in number of bytes. */
43092 uint8_t unused_0[7];
43094 * This field is used in Output records to indicate that the output
43095 * is completely written to RAM. This field should be read as '1'
43096 * to indicate that the output has been completely written.
43097 * When writing a command completion or response to an internal
43098 * processor, the order of writes has to be such that this field is
43104 /****************************
43105 * hwrm_cfa_flow_aging_qcfg *
43106 ****************************/
43109 /* hwrm_cfa_flow_aging_qcfg_input (size:192b/24B) */
43110 struct hwrm_cfa_flow_aging_qcfg_input {
43111 /* The HWRM command request type. */
43114 * The completion ring to send the completion event on. This should
43115 * be the NQ ID returned from the `nq_alloc` HWRM command.
43117 uint16_t cmpl_ring;
43119 * The sequence ID is used by the driver for tracking multiple
43120 * commands. This ID is treated as opaque data by the firmware and
43121 * the value is returned in the `hwrm_resp_hdr` upon completion.
43125 * The target ID of the command:
43126 * * 0x0-0xFFF8 - The function ID
43127 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
43128 * * 0xFFFD - Reserved for user-space HWRM interface
43131 uint16_t target_id;
43133 * A physical address pointer pointing to a host buffer that the
43134 * command's response data will be written. This can be either a host
43135 * physical address (HPA) or a guest physical address (GPA) and must
43136 * point to a physically contiguous block of memory.
43138 uint64_t resp_addr;
43140 * The direction for the flow aging configuration, 1 is rx path, 2 is
43144 /* Enumeration denoting the RX, TX type of the resource. */
43145 #define HWRM_CFA_FLOW_AGING_QCFG_INPUT_FLAGS_PATH UINT32_C(0x1)
43147 #define HWRM_CFA_FLOW_AGING_QCFG_INPUT_FLAGS_PATH_TX UINT32_C(0x0)
43149 #define HWRM_CFA_FLOW_AGING_QCFG_INPUT_FLAGS_PATH_RX UINT32_C(0x1)
43150 #define HWRM_CFA_FLOW_AGING_QCFG_INPUT_FLAGS_PATH_LAST \
43151 HWRM_CFA_FLOW_AGING_QCFG_INPUT_FLAGS_PATH_RX
43152 uint8_t unused_0[7];
43155 /* hwrm_cfa_flow_aging_qcfg_output (size:320b/40B) */
43156 struct hwrm_cfa_flow_aging_qcfg_output {
43157 /* The specific error status for the command. */
43158 uint16_t error_code;
43159 /* The HWRM command request type. */
43161 /* The sequence ID from the original command. */
43163 /* The length of the response data in number of bytes. */
43166 * The current flow aging timer for all TCP flows, the unit is 100
43169 uint32_t tcp_flow_timer;
43171 * The current TCP finished timer for all TCP flows, the unit is 100
43174 uint32_t tcp_fin_timer;
43176 * The current flow aging timer for all UDP flows, the unit is 100
43179 uint32_t udp_flow_timer;
43181 * The interval to dma eem ejection data to host memory, the unit is
43184 uint16_t eem_dma_interval;
43186 * The interval to notify driver to read the eem ejection data, the
43187 * unit is milliseconds.
43189 uint16_t eem_notice_interval;
43190 /* The maximum entries number in the eem context memory. */
43191 uint32_t eem_ctx_max_entries;
43192 /* The context memory ID for eem flow aging. */
43193 uint16_t eem_ctx_id;
43194 /* The context memory type for eem flow aging. */
43195 uint16_t eem_ctx_mem_type;
43196 uint8_t unused_0[7];
43198 * This field is used in Output records to indicate that the output
43199 * is completely written to RAM. This field should be read as '1'
43200 * to indicate that the output has been completely written.
43201 * When writing a command completion or response to an internal
43202 * processor, the order of writes has to be such that this field is
43208 /*****************************
43209 * hwrm_cfa_flow_aging_qcaps *
43210 *****************************/
43213 /* hwrm_cfa_flow_aging_qcaps_input (size:192b/24B) */
43214 struct hwrm_cfa_flow_aging_qcaps_input {
43215 /* The HWRM command request type. */
43218 * The completion ring to send the completion event on. This should
43219 * be the NQ ID returned from the `nq_alloc` HWRM command.
43221 uint16_t cmpl_ring;
43223 * The sequence ID is used by the driver for tracking multiple
43224 * commands. This ID is treated as opaque data by the firmware and
43225 * the value is returned in the `hwrm_resp_hdr` upon completion.
43229 * The target ID of the command:
43230 * * 0x0-0xFFF8 - The function ID
43231 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
43232 * * 0xFFFD - Reserved for user-space HWRM interface
43235 uint16_t target_id;
43237 * A physical address pointer pointing to a host buffer that the
43238 * command's response data will be written. This can be either a host
43239 * physical address (HPA) or a guest physical address (GPA) and must
43240 * point to a physically contiguous block of memory.
43242 uint64_t resp_addr;
43244 * The direction for the flow aging configuration, 1 is rx path, 2 is
43248 /* Enumeration denoting the RX, TX type of the resource. */
43249 #define HWRM_CFA_FLOW_AGING_QCAPS_INPUT_FLAGS_PATH UINT32_C(0x1)
43251 #define HWRM_CFA_FLOW_AGING_QCAPS_INPUT_FLAGS_PATH_TX UINT32_C(0x0)
43253 #define HWRM_CFA_FLOW_AGING_QCAPS_INPUT_FLAGS_PATH_RX UINT32_C(0x1)
43254 #define HWRM_CFA_FLOW_AGING_QCAPS_INPUT_FLAGS_PATH_LAST \
43255 HWRM_CFA_FLOW_AGING_QCAPS_INPUT_FLAGS_PATH_RX
43256 uint8_t unused_0[7];
43259 /* hwrm_cfa_flow_aging_qcaps_output (size:256b/32B) */
43260 struct hwrm_cfa_flow_aging_qcaps_output {
43261 /* The specific error status for the command. */
43262 uint16_t error_code;
43263 /* The HWRM command request type. */
43265 /* The sequence ID from the original command. */
43267 /* The length of the response data in number of bytes. */
43270 * The maximum flow aging timer for all TCP flows, the unit is 100
43273 uint32_t max_tcp_flow_timer;
43275 * The maximum TCP finished timer for all TCP flows, the unit is 100
43278 uint32_t max_tcp_fin_timer;
43280 * The maximum flow aging timer for all UDP flows, the unit is 100
43283 uint32_t max_udp_flow_timer;
43284 /* The maximum aging flows that HW can support. */
43285 uint32_t max_aging_flows;
43286 uint8_t unused_0[7];
43288 * This field is used in Output records to indicate that the output
43289 * is completely written to RAM. This field should be read as '1'
43290 * to indicate that the output has been completely written.
43291 * When writing a command completion or response to an internal
43292 * processor, the order of writes has to be such that this field is
43298 /**********************************
43299 * hwrm_cfa_tcp_flag_process_qcfg *
43300 **********************************/
43303 /* hwrm_cfa_tcp_flag_process_qcfg_input (size:128b/16B) */
43304 struct hwrm_cfa_tcp_flag_process_qcfg_input {
43305 /* The HWRM command request type. */
43308 * The completion ring to send the completion event on. This should
43309 * be the NQ ID returned from the `nq_alloc` HWRM command.
43311 uint16_t cmpl_ring;
43313 * The sequence ID is used by the driver for tracking multiple
43314 * commands. This ID is treated as opaque data by the firmware and
43315 * the value is returned in the `hwrm_resp_hdr` upon completion.
43319 * The target ID of the command:
43320 * * 0x0-0xFFF8 - The function ID
43321 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
43322 * * 0xFFFD - Reserved for user-space HWRM interface
43325 uint16_t target_id;
43327 * A physical address pointer pointing to a host buffer that the
43328 * command's response data will be written. This can be either a host
43329 * physical address (HPA) or a guest physical address (GPA) and must
43330 * point to a physically contiguous block of memory.
43332 uint64_t resp_addr;
43335 /* hwrm_cfa_tcp_flag_process_qcfg_output (size:192b/24B) */
43336 struct hwrm_cfa_tcp_flag_process_qcfg_output {
43337 /* The specific error status for the command. */
43338 uint16_t error_code;
43339 /* The HWRM command request type. */
43341 /* The sequence ID from the original command. */
43343 /* The length of the response data in number of bytes. */
43345 /* The port 0 RX mirror action record ID. */
43346 uint16_t rx_ar_id_port0;
43347 /* The port 1 RX mirror action record ID. */
43348 uint16_t rx_ar_id_port1;
43350 * The port 0 RX action record ID for TX TCP flag packets from
43353 uint16_t tx_ar_id_port0;
43355 * The port 1 RX action record ID for TX TCP flag packets from
43358 uint16_t tx_ar_id_port1;
43359 uint8_t unused_0[7];
43361 * This field is used in Output records to indicate that the output
43362 * is completely written to RAM. This field should be read as '1'
43363 * to indicate that the output has been completely written.
43364 * When writing a command completion or response to an internal
43365 * processor, the order of writes has to be such that this field is
43371 /**************************
43372 * hwrm_cfa_vf_pair_alloc *
43373 **************************/
43376 /* hwrm_cfa_vf_pair_alloc_input (size:448b/56B) */
43377 struct hwrm_cfa_vf_pair_alloc_input {
43378 /* The HWRM command request type. */
43381 * The completion ring to send the completion event on. This should
43382 * be the NQ ID returned from the `nq_alloc` HWRM command.
43384 uint16_t cmpl_ring;
43386 * The sequence ID is used by the driver for tracking multiple
43387 * commands. This ID is treated as opaque data by the firmware and
43388 * the value is returned in the `hwrm_resp_hdr` upon completion.
43392 * The target ID of the command:
43393 * * 0x0-0xFFF8 - The function ID
43394 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
43395 * * 0xFFFD - Reserved for user-space HWRM interface
43398 uint16_t target_id;
43400 * A physical address pointer pointing to a host buffer that the
43401 * command's response data will be written. This can be either a host
43402 * physical address (HPA) or a guest physical address (GPA) and must
43403 * point to a physically contiguous block of memory.
43405 uint64_t resp_addr;
43406 /* Logical VF number (range: 0 -> MAX_VFS -1). */
43408 /* Logical VF number (range: 0 -> MAX_VFS -1). */
43410 uint8_t unused_0[4];
43411 /* VF Pair name (32 byte string). */
43412 char pair_name[32];
43415 /* hwrm_cfa_vf_pair_alloc_output (size:128b/16B) */
43416 struct hwrm_cfa_vf_pair_alloc_output {
43417 /* The specific error status for the command. */
43418 uint16_t error_code;
43419 /* The HWRM command request type. */
43421 /* The sequence ID from the original command. */
43423 /* The length of the response data in number of bytes. */
43425 uint8_t unused_0[7];
43427 * This field is used in Output records to indicate that the output
43428 * is completely written to RAM. This field should be read as '1'
43429 * to indicate that the output has been completely written.
43430 * When writing a command completion or response to an internal
43431 * processor, the order of writes has to be such that this field is
43437 /*************************
43438 * hwrm_cfa_vf_pair_free *
43439 *************************/
43442 /* hwrm_cfa_vf_pair_free_input (size:384b/48B) */
43443 struct hwrm_cfa_vf_pair_free_input {
43444 /* The HWRM command request type. */
43447 * The completion ring to send the completion event on. This should
43448 * be the NQ ID returned from the `nq_alloc` HWRM command.
43450 uint16_t cmpl_ring;
43452 * The sequence ID is used by the driver for tracking multiple
43453 * commands. This ID is treated as opaque data by the firmware and
43454 * the value is returned in the `hwrm_resp_hdr` upon completion.
43458 * The target ID of the command:
43459 * * 0x0-0xFFF8 - The function ID
43460 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
43461 * * 0xFFFD - Reserved for user-space HWRM interface
43464 uint16_t target_id;
43466 * A physical address pointer pointing to a host buffer that the
43467 * command's response data will be written. This can be either a host
43468 * physical address (HPA) or a guest physical address (GPA) and must
43469 * point to a physically contiguous block of memory.
43471 uint64_t resp_addr;
43472 /* VF Pair name (32 byte string). */
43473 char pair_name[32];
43476 /* hwrm_cfa_vf_pair_free_output (size:128b/16B) */
43477 struct hwrm_cfa_vf_pair_free_output {
43478 /* The specific error status for the command. */
43479 uint16_t error_code;
43480 /* The HWRM command request type. */
43482 /* The sequence ID from the original command. */
43484 /* The length of the response data in number of bytes. */
43486 uint8_t unused_0[7];
43488 * This field is used in Output records to indicate that the output
43489 * is completely written to RAM. This field should be read as '1'
43490 * to indicate that the output has been completely written.
43491 * When writing a command completion or response to an internal
43492 * processor, the order of writes has to be such that this field is
43498 /*************************
43499 * hwrm_cfa_vf_pair_info *
43500 *************************/
43503 /* hwrm_cfa_vf_pair_info_input (size:448b/56B) */
43504 struct hwrm_cfa_vf_pair_info_input {
43505 /* The HWRM command request type. */
43508 * The completion ring to send the completion event on. This should
43509 * be the NQ ID returned from the `nq_alloc` HWRM command.
43511 uint16_t cmpl_ring;
43513 * The sequence ID is used by the driver for tracking multiple
43514 * commands. This ID is treated as opaque data by the firmware and
43515 * the value is returned in the `hwrm_resp_hdr` upon completion.
43519 * The target ID of the command:
43520 * * 0x0-0xFFF8 - The function ID
43521 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
43522 * * 0xFFFD - Reserved for user-space HWRM interface
43525 uint16_t target_id;
43527 * A physical address pointer pointing to a host buffer that the
43528 * command's response data will be written. This can be either a host
43529 * physical address (HPA) or a guest physical address (GPA) and must
43530 * point to a physically contiguous block of memory.
43532 uint64_t resp_addr;
43534 /* If this flag is set, lookup by name else lookup by index. */
43535 #define HWRM_CFA_VF_PAIR_INFO_INPUT_FLAGS_LOOKUP_TYPE UINT32_C(0x1)
43536 /* vf pair table index. */
43537 uint16_t vf_pair_index;
43538 uint8_t unused_0[2];
43539 /* VF Pair name (32 byte string). */
43540 char vf_pair_name[32];
43543 /* hwrm_cfa_vf_pair_info_output (size:512b/64B) */
43544 struct hwrm_cfa_vf_pair_info_output {
43545 /* The specific error status for the command. */
43546 uint16_t error_code;
43547 /* The HWRM command request type. */
43549 /* The sequence ID from the original command. */
43551 /* The length of the response data in number of bytes. */
43553 /* vf pair table index. */
43554 uint16_t next_vf_pair_index;
43555 /* vf pair member a's vf_fid. */
43557 /* vf pair member a's Linux logical VF number. */
43558 uint16_t vf_a_index;
43559 /* vf pair member b's vf_fid. */
43561 /* vf pair member a's Linux logical VF number. */
43562 uint16_t vf_b_index;
43563 /* vf pair state. */
43564 uint8_t pair_state;
43565 /* Pair has been allocated */
43566 #define HWRM_CFA_VF_PAIR_INFO_OUTPUT_PAIR_STATE_ALLOCATED UINT32_C(0x1)
43567 /* Both pair members are active */
43568 #define HWRM_CFA_VF_PAIR_INFO_OUTPUT_PAIR_STATE_ACTIVE UINT32_C(0x2)
43569 #define HWRM_CFA_VF_PAIR_INFO_OUTPUT_PAIR_STATE_LAST \
43570 HWRM_CFA_VF_PAIR_INFO_OUTPUT_PAIR_STATE_ACTIVE
43571 uint8_t unused_0[5];
43572 /* VF Pair name (32 byte string). */
43573 char pair_name[32];
43574 uint8_t unused_1[7];
43576 * This field is used in Output records to indicate that the output
43577 * is completely written to RAM. This field should be read as '1'
43578 * to indicate that the output has been completely written.
43579 * When writing a command completion or response to an internal
43580 * processor, the order of writes has to be such that this field is
43586 /***********************
43587 * hwrm_cfa_pair_alloc *
43588 ***********************/
43591 /* hwrm_cfa_pair_alloc_input (size:576b/72B) */
43592 struct hwrm_cfa_pair_alloc_input {
43593 /* The HWRM command request type. */
43596 * The completion ring to send the completion event on. This should
43597 * be the NQ ID returned from the `nq_alloc` HWRM command.
43599 uint16_t cmpl_ring;
43601 * The sequence ID is used by the driver for tracking multiple
43602 * commands. This ID is treated as opaque data by the firmware and
43603 * the value is returned in the `hwrm_resp_hdr` upon completion.
43607 * The target ID of the command:
43608 * * 0x0-0xFFF8 - The function ID
43609 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
43610 * * 0xFFFD - Reserved for user-space HWRM interface
43613 uint16_t target_id;
43615 * A physical address pointer pointing to a host buffer that the
43616 * command's response data will be written. This can be either a host
43617 * physical address (HPA) or a guest physical address (GPA) and must
43618 * point to a physically contiguous block of memory.
43620 uint64_t resp_addr;
43622 * Pair mode (0-vf2fn, 1-rep2fn, 2-rep2rep, 3-proxy, 4-pfpair,
43623 * 5-rep2fn_mod, 6-rep2fn_modall, 7-rep2fn_truflow).
43625 uint16_t pair_mode;
43626 /* Pair between VF on local host with PF or VF on specified host. */
43627 #define HWRM_CFA_PAIR_ALLOC_INPUT_PAIR_MODE_VF2FN \
43629 /* Pair between REP on local host with PF or VF on specified host. */
43630 #define HWRM_CFA_PAIR_ALLOC_INPUT_PAIR_MODE_REP2FN \
43632 /* Pair between REP on local host with REP on specified host. */
43633 #define HWRM_CFA_PAIR_ALLOC_INPUT_PAIR_MODE_REP2REP \
43635 /* Pair for the proxy interface. */
43636 #define HWRM_CFA_PAIR_ALLOC_INPUT_PAIR_MODE_PROXY \
43638 /* Pair for the PF interface. */
43639 #define HWRM_CFA_PAIR_ALLOC_INPUT_PAIR_MODE_PFPAIR \
43641 /* Modify existing rep2fn pair and move pair to new PF. */
43642 #define HWRM_CFA_PAIR_ALLOC_INPUT_PAIR_MODE_REP2FN_MOD \
43645 * Modify existing rep2fn pairs paired with same PF and move pairs
43648 #define HWRM_CFA_PAIR_ALLOC_INPUT_PAIR_MODE_REP2FN_MODALL \
43651 * Truflow pair between REP on local host with PF or VF on specified
43654 #define HWRM_CFA_PAIR_ALLOC_INPUT_PAIR_MODE_REP2FN_TRUFLOW \
43656 #define HWRM_CFA_PAIR_ALLOC_INPUT_PAIR_MODE_LAST \
43657 HWRM_CFA_PAIR_ALLOC_INPUT_PAIR_MODE_REP2FN_TRUFLOW
43658 /* Logical VF number (range: 0 -> MAX_VFS -1). */
43660 /* Logical Host (0xff-local host). */
43662 /* Logical PF (0xff-PF for command channel). */
43664 /* Logical VF number (range: 0 -> MAX_VFS -1). */
43666 /* Loopback port (0xff-internal loopback), valid for mode-3. */
43668 /* Priority used for encap of loopback packets valid for mode-3. */
43670 /* New PF for rep2fn modify, valid for mode 5. */
43671 uint16_t new_pf_fid;
43674 * This bit must be '1' for the q_ab field to be
43677 #define HWRM_CFA_PAIR_ALLOC_INPUT_ENABLES_Q_AB_VALID UINT32_C(0x1)
43679 * This bit must be '1' for the q_ba field to be
43682 #define HWRM_CFA_PAIR_ALLOC_INPUT_ENABLES_Q_BA_VALID UINT32_C(0x2)
43684 * This bit must be '1' for the fc_ab field to be
43687 #define HWRM_CFA_PAIR_ALLOC_INPUT_ENABLES_FC_AB_VALID UINT32_C(0x4)
43689 * This bit must be '1' for the fc_ba field to be
43692 #define HWRM_CFA_PAIR_ALLOC_INPUT_ENABLES_FC_BA_VALID UINT32_C(0x8)
43693 /* VF Pair name (32 byte string). */
43694 char pair_name[32];
43696 * The q_ab value specifies the logical index of the TX/RX CoS
43697 * queue to be assigned for traffic in the A to B direction of
43698 * the interface pair. The default value is 0.
43702 * The q_ba value specifies the logical index of the TX/RX CoS
43703 * queue to be assigned for traffic in the B to A direction of
43704 * the interface pair. The default value is 1.
43708 * Specifies whether RX ring flow control is disabled (0) or enabled
43709 * (1) in the A to B direction. The default value is 0, meaning that
43710 * packets will be dropped when the B-side RX rings are full.
43714 * Specifies whether RX ring flow control is disabled (0) or enabled
43715 * (1) in the B to A direction. The default value is 1, meaning that
43716 * the RX CoS queue will be flow controlled when the A-side RX rings
43720 uint8_t unused_1[4];
43723 /* hwrm_cfa_pair_alloc_output (size:192b/24B) */
43724 struct hwrm_cfa_pair_alloc_output {
43725 /* The specific error status for the command. */
43726 uint16_t error_code;
43727 /* The HWRM command request type. */
43729 /* The sequence ID from the original command. */
43731 /* The length of the response data in number of bytes. */
43733 /* Only valid for modes 1 and 2. */
43734 uint16_t rx_cfa_code_a;
43735 /* Only valid for modes 1 and 2. */
43736 uint16_t tx_cfa_action_a;
43737 /* Only valid for mode 2. */
43738 uint16_t rx_cfa_code_b;
43739 /* Only valid for mode 2. */
43740 uint16_t tx_cfa_action_b;
43741 uint8_t unused_0[7];
43743 * This field is used in Output records to indicate that the output
43744 * is completely written to RAM. This field should be read as '1'
43745 * to indicate that the output has been completely written.
43746 * When writing a command completion or response to an internal
43747 * processor, the order of writes has to be such that this field is
43753 /**********************
43754 * hwrm_cfa_pair_free *
43755 **********************/
43758 /* hwrm_cfa_pair_free_input (size:448b/56B) */
43759 struct hwrm_cfa_pair_free_input {
43760 /* The HWRM command request type. */
43763 * The completion ring to send the completion event on. This should
43764 * be the NQ ID returned from the `nq_alloc` HWRM command.
43766 uint16_t cmpl_ring;
43768 * The sequence ID is used by the driver for tracking multiple
43769 * commands. This ID is treated as opaque data by the firmware and
43770 * the value is returned in the `hwrm_resp_hdr` upon completion.
43774 * The target ID of the command:
43775 * * 0x0-0xFFF8 - The function ID
43776 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
43777 * * 0xFFFD - Reserved for user-space HWRM interface
43780 uint16_t target_id;
43782 * A physical address pointer pointing to a host buffer that the
43783 * command's response data will be written. This can be either a host
43784 * physical address (HPA) or a guest physical address (GPA) and must
43785 * point to a physically contiguous block of memory.
43787 uint64_t resp_addr;
43788 /* VF Pair name (32 byte string). */
43789 char pair_name[32];
43790 /* Logical PF (0xff-PF for command channel). */
43792 uint8_t unused_0[3];
43793 /* Logical VF number (range: 0 -> MAX_VFS -1). */
43796 * Pair mode (0-vf2fn, 1-rep2fn, 2-rep2rep, 3-proxy, 4-pfpair,
43797 * 5-rep2fn_mod, 6-rep2fn_modall, 7-rep2fn_truflow).
43799 uint16_t pair_mode;
43800 /* Pair between VF on local host with PF or VF on specified host. */
43801 #define HWRM_CFA_PAIR_FREE_INPUT_PAIR_MODE_VF2FN UINT32_C(0x0)
43802 /* Pair between REP on local host with PF or VF on specified host. */
43803 #define HWRM_CFA_PAIR_FREE_INPUT_PAIR_MODE_REP2FN UINT32_C(0x1)
43804 /* Pair between REP on local host with REP on specified host. */
43805 #define HWRM_CFA_PAIR_FREE_INPUT_PAIR_MODE_REP2REP UINT32_C(0x2)
43806 /* Pair for the proxy interface. */
43807 #define HWRM_CFA_PAIR_FREE_INPUT_PAIR_MODE_PROXY UINT32_C(0x3)
43808 /* Pair for the PF interface. */
43809 #define HWRM_CFA_PAIR_FREE_INPUT_PAIR_MODE_PFPAIR UINT32_C(0x4)
43810 /* Modify existing rep2fn pair and move pair to new PF. */
43811 #define HWRM_CFA_PAIR_FREE_INPUT_PAIR_MODE_REP2FN_MOD UINT32_C(0x5)
43813 * Modify existing rep2fn pairs paired with same PF and move pairs
43816 #define HWRM_CFA_PAIR_FREE_INPUT_PAIR_MODE_REP2FN_MODALL UINT32_C(0x6)
43818 * Truflow pair between REP on local host with PF or VF on
43821 #define HWRM_CFA_PAIR_FREE_INPUT_PAIR_MODE_REP2FN_TRUFLOW UINT32_C(0x7)
43822 #define HWRM_CFA_PAIR_FREE_INPUT_PAIR_MODE_LAST \
43823 HWRM_CFA_PAIR_FREE_INPUT_PAIR_MODE_REP2FN_TRUFLOW
43826 /* hwrm_cfa_pair_free_output (size:128b/16B) */
43827 struct hwrm_cfa_pair_free_output {
43828 /* The specific error status for the command. */
43829 uint16_t error_code;
43830 /* The HWRM command request type. */
43832 /* The sequence ID from the original command. */
43834 /* The length of the response data in number of bytes. */
43836 uint8_t unused_0[7];
43838 * This field is used in Output records to indicate that the output
43839 * is completely written to RAM. This field should be read as '1'
43840 * to indicate that the output has been completely written.
43841 * When writing a command completion or response to an internal
43842 * processor, the order of writes has to be such that this field is
43848 /**********************
43849 * hwrm_cfa_pair_info *
43850 **********************/
43853 /* hwrm_cfa_pair_info_input (size:448b/56B) */
43854 struct hwrm_cfa_pair_info_input {
43855 /* The HWRM command request type. */
43858 * The completion ring to send the completion event on. This should
43859 * be the NQ ID returned from the `nq_alloc` HWRM command.
43861 uint16_t cmpl_ring;
43863 * The sequence ID is used by the driver for tracking multiple
43864 * commands. This ID is treated as opaque data by the firmware and
43865 * the value is returned in the `hwrm_resp_hdr` upon completion.
43869 * The target ID of the command:
43870 * * 0x0-0xFFF8 - The function ID
43871 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
43872 * * 0xFFFD - Reserved for user-space HWRM interface
43875 uint16_t target_id;
43877 * A physical address pointer pointing to a host buffer that the
43878 * command's response data will be written. This can be either a host
43879 * physical address (HPA) or a guest physical address (GPA) and must
43880 * point to a physically contiguous block of memory.
43882 uint64_t resp_addr;
43884 /* If this flag is set, lookup by name else lookup by index. */
43885 #define HWRM_CFA_PAIR_INFO_INPUT_FLAGS_LOOKUP_TYPE UINT32_C(0x1)
43886 /* If this flag is set, lookup by PF id and VF id. */
43887 #define HWRM_CFA_PAIR_INFO_INPUT_FLAGS_LOOKUP_REPRE UINT32_C(0x2)
43888 /* Pair table index. */
43889 uint16_t pair_index;
43890 /* Pair pf index. */
43892 /* Pair vf index. */
43894 /* Pair name (32 byte string). */
43895 char pair_name[32];
43898 /* hwrm_cfa_pair_info_output (size:576b/72B) */
43899 struct hwrm_cfa_pair_info_output {
43900 /* The specific error status for the command. */
43901 uint16_t error_code;
43902 /* The HWRM command request type. */
43904 /* The sequence ID from the original command. */
43906 /* The length of the response data in number of bytes. */
43908 /* Pair table index. */
43909 uint16_t next_pair_index;
43910 /* Pair member a's fid. */
43912 /* Logical host number. */
43913 uint8_t host_a_index;
43914 /* Logical PF number. */
43915 uint8_t pf_a_index;
43916 /* Pair member a's Linux logical VF number. */
43917 uint16_t vf_a_index;
43919 uint16_t rx_cfa_code_a;
43920 /* Tx CFA action. */
43921 uint16_t tx_cfa_action_a;
43922 /* Pair member b's fid. */
43924 /* Logical host number. */
43925 uint8_t host_b_index;
43926 /* Logical PF number. */
43927 uint8_t pf_b_index;
43928 /* Pair member a's Linux logical VF number. */
43929 uint16_t vf_b_index;
43931 uint16_t rx_cfa_code_b;
43932 /* Tx CFA action. */
43933 uint16_t tx_cfa_action_b;
43934 /* Pair mode (0-vf2fn, 1-rep2fn, 2-rep2rep, 3-proxy, 4-pfpair). */
43936 /* Pair between VF on local host with PF or VF on specified host. */
43937 #define HWRM_CFA_PAIR_INFO_OUTPUT_PAIR_MODE_VF2FN UINT32_C(0x0)
43938 /* Pair between REP on local host with PF or VF on specified host. */
43939 #define HWRM_CFA_PAIR_INFO_OUTPUT_PAIR_MODE_REP2FN UINT32_C(0x1)
43940 /* Pair between REP on local host with REP on specified host. */
43941 #define HWRM_CFA_PAIR_INFO_OUTPUT_PAIR_MODE_REP2REP UINT32_C(0x2)
43942 /* Pair for the proxy interface. */
43943 #define HWRM_CFA_PAIR_INFO_OUTPUT_PAIR_MODE_PROXY UINT32_C(0x3)
43944 /* Pair for the PF interface. */
43945 #define HWRM_CFA_PAIR_INFO_OUTPUT_PAIR_MODE_PFPAIR UINT32_C(0x4)
43946 #define HWRM_CFA_PAIR_INFO_OUTPUT_PAIR_MODE_LAST \
43947 HWRM_CFA_PAIR_INFO_OUTPUT_PAIR_MODE_PFPAIR
43949 uint8_t pair_state;
43950 /* Pair has been allocated */
43951 #define HWRM_CFA_PAIR_INFO_OUTPUT_PAIR_STATE_ALLOCATED UINT32_C(0x1)
43952 /* Both pair members are active */
43953 #define HWRM_CFA_PAIR_INFO_OUTPUT_PAIR_STATE_ACTIVE UINT32_C(0x2)
43954 #define HWRM_CFA_PAIR_INFO_OUTPUT_PAIR_STATE_LAST \
43955 HWRM_CFA_PAIR_INFO_OUTPUT_PAIR_STATE_ACTIVE
43956 /* Pair name (32 byte string). */
43957 char pair_name[32];
43958 uint8_t unused_0[7];
43960 * This field is used in Output records to indicate that the output
43961 * is completely written to RAM. This field should be read as '1'
43962 * to indicate that the output has been completely written.
43963 * When writing a command completion or response to an internal
43964 * processor, the order of writes has to be such that this field is
43970 /**********************
43971 * hwrm_cfa_vfr_alloc *
43972 **********************/
43975 /* hwrm_cfa_vfr_alloc_input (size:448b/56B) */
43976 struct hwrm_cfa_vfr_alloc_input {
43977 /* The HWRM command request type. */
43980 * The completion ring to send the completion event on. This should
43981 * be the NQ ID returned from the `nq_alloc` HWRM command.
43983 uint16_t cmpl_ring;
43985 * The sequence ID is used by the driver for tracking multiple
43986 * commands. This ID is treated as opaque data by the firmware and
43987 * the value is returned in the `hwrm_resp_hdr` upon completion.
43991 * The target ID of the command:
43992 * * 0x0-0xFFF8 - The function ID
43993 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
43994 * * 0xFFFD - Reserved for user-space HWRM interface
43997 uint16_t target_id;
43999 * A physical address pointer pointing to a host buffer that the
44000 * command's response data will be written. This can be either a host
44001 * physical address (HPA) or a guest physical address (GPA) and must
44002 * point to a physically contiguous block of memory.
44004 uint64_t resp_addr;
44005 /* Logical VF number (range: 0 -> MAX_VFS -1). */
44008 * This field is reserved for the future use.
44009 * It shall be set to 0.
44012 uint8_t unused_0[4];
44013 /* VF Representor name (32 byte string). */
44017 /* hwrm_cfa_vfr_alloc_output (size:128b/16B) */
44018 struct hwrm_cfa_vfr_alloc_output {
44019 /* The specific error status for the command. */
44020 uint16_t error_code;
44021 /* The HWRM command request type. */
44023 /* The sequence ID from the original command. */
44025 /* The length of the response data in number of bytes. */
44028 uint16_t rx_cfa_code;
44029 /* Tx CFA action. */
44030 uint16_t tx_cfa_action;
44031 uint8_t unused_0[3];
44033 * This field is used in Output records to indicate that the output
44034 * is completely written to RAM. This field should be read as '1'
44035 * to indicate that the output has been completely written.
44036 * When writing a command completion or response to an internal
44037 * processor, the order of writes has to be such that this field is
44043 /*********************
44044 * hwrm_cfa_vfr_free *
44045 *********************/
44048 /* hwrm_cfa_vfr_free_input (size:448b/56B) */
44049 struct hwrm_cfa_vfr_free_input {
44050 /* The HWRM command request type. */
44053 * The completion ring to send the completion event on. This should
44054 * be the NQ ID returned from the `nq_alloc` HWRM command.
44056 uint16_t cmpl_ring;
44058 * The sequence ID is used by the driver for tracking multiple
44059 * commands. This ID is treated as opaque data by the firmware and
44060 * the value is returned in the `hwrm_resp_hdr` upon completion.
44064 * The target ID of the command:
44065 * * 0x0-0xFFF8 - The function ID
44066 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
44067 * * 0xFFFD - Reserved for user-space HWRM interface
44070 uint16_t target_id;
44072 * A physical address pointer pointing to a host buffer that the
44073 * command's response data will be written. This can be either a host
44074 * physical address (HPA) or a guest physical address (GPA) and must
44075 * point to a physically contiguous block of memory.
44077 uint64_t resp_addr;
44078 /* VF Representor name (32 byte string). */
44080 /* Logical VF number (range: 0 -> MAX_VFS -1). */
44083 * This field is reserved for the future use.
44084 * It shall be set to 0.
44087 uint8_t unused_0[4];
44090 /* hwrm_cfa_vfr_free_output (size:128b/16B) */
44091 struct hwrm_cfa_vfr_free_output {
44092 /* The specific error status for the command. */
44093 uint16_t error_code;
44094 /* The HWRM command request type. */
44096 /* The sequence ID from the original command. */
44098 /* The length of the response data in number of bytes. */
44100 uint8_t unused_0[7];
44102 * This field is used in Output records to indicate that the output
44103 * is completely written to RAM. This field should be read as '1'
44104 * to indicate that the output has been completely written.
44105 * When writing a command completion or response to an internal
44106 * processor, the order of writes has to be such that this field is
44112 /***************************************
44113 * hwrm_cfa_redirect_query_tunnel_type *
44114 ***************************************/
44117 /* hwrm_cfa_redirect_query_tunnel_type_input (size:192b/24B) */
44118 struct hwrm_cfa_redirect_query_tunnel_type_input {
44119 /* The HWRM command request type. */
44122 * The completion ring to send the completion event on. This should
44123 * be the NQ ID returned from the `nq_alloc` HWRM command.
44125 uint16_t cmpl_ring;
44127 * The sequence ID is used by the driver for tracking multiple
44128 * commands. This ID is treated as opaque data by the firmware and
44129 * the value is returned in the `hwrm_resp_hdr` upon completion.
44133 * The target ID of the command:
44134 * * 0x0-0xFFF8 - The function ID
44135 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
44136 * * 0xFFFD - Reserved for user-space HWRM interface
44139 uint16_t target_id;
44141 * A physical address pointer pointing to a host buffer that the
44142 * command's response data will be written. This can be either a host
44143 * physical address (HPA) or a guest physical address (GPA) and must
44144 * point to a physically contiguous block of memory.
44146 uint64_t resp_addr;
44147 /* The source function id. */
44149 uint8_t unused_0[6];
44152 /* hwrm_cfa_redirect_query_tunnel_type_output (size:128b/16B) */
44153 struct hwrm_cfa_redirect_query_tunnel_type_output {
44154 /* The specific error status for the command. */
44155 uint16_t error_code;
44156 /* The HWRM command request type. */
44158 /* The sequence ID from the original command. */
44160 /* The length of the response data in number of bytes. */
44163 uint32_t tunnel_mask;
44165 #define HWRM_CFA_REDIRECT_QUERY_TUNNEL_TYPE_OUTPUT_TUNNEL_MASK_NONTUNNEL \
44167 /* Virtual eXtensible Local Area Network (VXLAN) */
44168 #define HWRM_CFA_REDIRECT_QUERY_TUNNEL_TYPE_OUTPUT_TUNNEL_MASK_VXLAN \
44170 /* Network Virtualization Generic Routing Encapsulation (NVGRE) */
44171 #define HWRM_CFA_REDIRECT_QUERY_TUNNEL_TYPE_OUTPUT_TUNNEL_MASK_NVGRE \
44173 /* Generic Routing Encapsulation (GRE) inside Ethernet payload */
44174 #define HWRM_CFA_REDIRECT_QUERY_TUNNEL_TYPE_OUTPUT_TUNNEL_MASK_L2GRE \
44177 #define HWRM_CFA_REDIRECT_QUERY_TUNNEL_TYPE_OUTPUT_TUNNEL_MASK_IPIP \
44179 /* Generic Network Virtualization Encapsulation (Geneve) */
44180 #define HWRM_CFA_REDIRECT_QUERY_TUNNEL_TYPE_OUTPUT_TUNNEL_MASK_GENEVE \
44182 /* Multi-Protocol Label Switching (MPLS) */
44183 #define HWRM_CFA_REDIRECT_QUERY_TUNNEL_TYPE_OUTPUT_TUNNEL_MASK_MPLS \
44185 /* Stateless Transport Tunnel (STT) */
44186 #define HWRM_CFA_REDIRECT_QUERY_TUNNEL_TYPE_OUTPUT_TUNNEL_MASK_STT \
44188 /* Generic Routing Encapsulation (GRE) inside IP datagram payload */
44189 #define HWRM_CFA_REDIRECT_QUERY_TUNNEL_TYPE_OUTPUT_TUNNEL_MASK_IPGRE \
44191 /* IPV4 over virtual eXtensible Local Area Network (IPV4oVXLAN) */
44192 #define HWRM_CFA_REDIRECT_QUERY_TUNNEL_TYPE_OUTPUT_TUNNEL_MASK_VXLAN_V4 \
44195 * Enhance Generic Routing Encapsulation (GRE version 1) inside IP
44198 #define HWRM_CFA_REDIRECT_QUERY_TUNNEL_TYPE_OUTPUT_TUNNEL_MASK_IPGRE_V1 \
44200 /* Any tunneled traffic */
44201 #define HWRM_CFA_REDIRECT_QUERY_TUNNEL_TYPE_OUTPUT_TUNNEL_MASK_ANYTUNNEL \
44203 /* Use fixed layer 2 ether type of 0xFFFF */
44204 #define HWRM_CFA_REDIRECT_QUERY_TUNNEL_TYPE_OUTPUT_TUNNEL_MASK_L2_ETYPE \
44207 * IPV6 over virtual eXtensible Local Area Network with GPE header
44210 #define HWRM_CFA_REDIRECT_QUERY_TUNNEL_TYPE_OUTPUT_TUNNEL_MASK_VXLAN_GPE_V6 \
44212 uint8_t unused_0[3];
44214 * This field is used in Output records to indicate that the output
44215 * is completely written to RAM. This field should be read as '1'
44216 * to indicate that the output has been completely written.
44217 * When writing a command completion or response to an internal
44218 * processor, the order of writes has to be such that this field is
44224 /*************************
44225 * hwrm_cfa_ctx_mem_rgtr *
44226 *************************/
44229 /* hwrm_cfa_ctx_mem_rgtr_input (size:256b/32B) */
44230 struct hwrm_cfa_ctx_mem_rgtr_input {
44231 /* The HWRM command request type. */
44234 * The completion ring to send the completion event on. This should
44235 * be the NQ ID returned from the `nq_alloc` HWRM command.
44237 uint16_t cmpl_ring;
44239 * The sequence ID is used by the driver for tracking multiple
44240 * commands. This ID is treated as opaque data by the firmware and
44241 * the value is returned in the `hwrm_resp_hdr` upon completion.
44245 * The target ID of the command:
44246 * * 0x0-0xFFF8 - The function ID
44247 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
44248 * * 0xFFFD - Reserved for user-space HWRM interface
44251 uint16_t target_id;
44253 * A physical address pointer pointing to a host buffer that the
44254 * command's response data will be written. This can be either a host
44255 * physical address (HPA) or a guest physical address (GPA) and must
44256 * point to a physically contiguous block of memory.
44258 uint64_t resp_addr;
44260 /* Counter PBL indirect levels. */
44261 uint8_t page_level;
44262 /* PBL pointer is physical start address. */
44263 #define HWRM_CFA_CTX_MEM_RGTR_INPUT_PAGE_LEVEL_LVL_0 UINT32_C(0x0)
44264 /* PBL pointer points to PTE table. */
44265 #define HWRM_CFA_CTX_MEM_RGTR_INPUT_PAGE_LEVEL_LVL_1 UINT32_C(0x1)
44267 * PBL pointer points to PDE table with each entry pointing to PTE
44270 #define HWRM_CFA_CTX_MEM_RGTR_INPUT_PAGE_LEVEL_LVL_2 UINT32_C(0x2)
44271 #define HWRM_CFA_CTX_MEM_RGTR_INPUT_PAGE_LEVEL_LAST \
44272 HWRM_CFA_CTX_MEM_RGTR_INPUT_PAGE_LEVEL_LVL_2
44275 /* 4KB page size. */
44276 #define HWRM_CFA_CTX_MEM_RGTR_INPUT_PAGE_SIZE_4K UINT32_C(0x0)
44277 /* 8KB page size. */
44278 #define HWRM_CFA_CTX_MEM_RGTR_INPUT_PAGE_SIZE_8K UINT32_C(0x1)
44279 /* 64KB page size. */
44280 #define HWRM_CFA_CTX_MEM_RGTR_INPUT_PAGE_SIZE_64K UINT32_C(0x4)
44281 /* 256KB page size. */
44282 #define HWRM_CFA_CTX_MEM_RGTR_INPUT_PAGE_SIZE_256K UINT32_C(0x6)
44283 /* 1MB page size. */
44284 #define HWRM_CFA_CTX_MEM_RGTR_INPUT_PAGE_SIZE_1M UINT32_C(0x8)
44285 /* 2MB page size. */
44286 #define HWRM_CFA_CTX_MEM_RGTR_INPUT_PAGE_SIZE_2M UINT32_C(0x9)
44287 /* 4MB page size. */
44288 #define HWRM_CFA_CTX_MEM_RGTR_INPUT_PAGE_SIZE_4M UINT32_C(0xa)
44289 /* 1GB page size. */
44290 #define HWRM_CFA_CTX_MEM_RGTR_INPUT_PAGE_SIZE_1G UINT32_C(0x12)
44291 #define HWRM_CFA_CTX_MEM_RGTR_INPUT_PAGE_SIZE_LAST \
44292 HWRM_CFA_CTX_MEM_RGTR_INPUT_PAGE_SIZE_1G
44294 /* Pointer to the PBL, or PDL depending on number of levels */
44298 /* hwrm_cfa_ctx_mem_rgtr_output (size:128b/16B) */
44299 struct hwrm_cfa_ctx_mem_rgtr_output {
44300 /* The specific error status for the command. */
44301 uint16_t error_code;
44302 /* The HWRM command request type. */
44304 /* The sequence ID from the original command. */
44306 /* The length of the response data in number of bytes. */
44309 * Id/Handle to the recently register context memory. This handle is
44310 * passed to the CFA feature.
44313 uint8_t unused_0[5];
44315 * This field is used in Output records to indicate that the output
44316 * is completely written to RAM. This field should be read as '1'
44317 * to indicate that the output has been completely written.
44318 * When writing a command completion or response to an internal
44319 * processor, the order of writes has to be such that this field is
44325 /***************************
44326 * hwrm_cfa_ctx_mem_unrgtr *
44327 ***************************/
44330 /* hwrm_cfa_ctx_mem_unrgtr_input (size:192b/24B) */
44331 struct hwrm_cfa_ctx_mem_unrgtr_input {
44332 /* The HWRM command request type. */
44335 * The completion ring to send the completion event on. This should
44336 * be the NQ ID returned from the `nq_alloc` HWRM command.
44338 uint16_t cmpl_ring;
44340 * The sequence ID is used by the driver for tracking multiple
44341 * commands. This ID is treated as opaque data by the firmware and
44342 * the value is returned in the `hwrm_resp_hdr` upon completion.
44346 * The target ID of the command:
44347 * * 0x0-0xFFF8 - The function ID
44348 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
44349 * * 0xFFFD - Reserved for user-space HWRM interface
44352 uint16_t target_id;
44354 * A physical address pointer pointing to a host buffer that the
44355 * command's response data will be written. This can be either a host
44356 * physical address (HPA) or a guest physical address (GPA) and must
44357 * point to a physically contiguous block of memory.
44359 uint64_t resp_addr;
44361 * Id/Handle to the recently register context memory. This handle is
44362 * passed to the CFA feature.
44365 uint8_t unused_0[6];
44368 /* hwrm_cfa_ctx_mem_unrgtr_output (size:128b/16B) */
44369 struct hwrm_cfa_ctx_mem_unrgtr_output {
44370 /* The specific error status for the command. */
44371 uint16_t error_code;
44372 /* The HWRM command request type. */
44374 /* The sequence ID from the original command. */
44376 /* The length of the response data in number of bytes. */
44378 uint8_t unused_0[7];
44380 * This field is used in Output records to indicate that the output
44381 * is completely written to RAM. This field should be read as '1'
44382 * to indicate that the output has been completely written.
44383 * When writing a command completion or response to an internal
44384 * processor, the order of writes has to be such that this field is
44390 /*************************
44391 * hwrm_cfa_ctx_mem_qctx *
44392 *************************/
44395 /* hwrm_cfa_ctx_mem_qctx_input (size:192b/24B) */
44396 struct hwrm_cfa_ctx_mem_qctx_input {
44397 /* The HWRM command request type. */
44400 * The completion ring to send the completion event on. This should
44401 * be the NQ ID returned from the `nq_alloc` HWRM command.
44403 uint16_t cmpl_ring;
44405 * The sequence ID is used by the driver for tracking multiple
44406 * commands. This ID is treated as opaque data by the firmware and
44407 * the value is returned in the `hwrm_resp_hdr` upon completion.
44411 * The target ID of the command:
44412 * * 0x0-0xFFF8 - The function ID
44413 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
44414 * * 0xFFFD - Reserved for user-space HWRM interface
44417 uint16_t target_id;
44419 * A physical address pointer pointing to a host buffer that the
44420 * command's response data will be written. This can be either a host
44421 * physical address (HPA) or a guest physical address (GPA) and must
44422 * point to a physically contiguous block of memory.
44424 uint64_t resp_addr;
44426 * Id/Handle to the recently register context memory. This handle is
44427 * passed to the CFA feature.
44430 uint8_t unused_0[6];
44433 /* hwrm_cfa_ctx_mem_qctx_output (size:256b/32B) */
44434 struct hwrm_cfa_ctx_mem_qctx_output {
44435 /* The specific error status for the command. */
44436 uint16_t error_code;
44437 /* The HWRM command request type. */
44439 /* The sequence ID from the original command. */
44441 /* The length of the response data in number of bytes. */
44444 /* Counter PBL indirect levels. */
44445 uint8_t page_level;
44446 /* PBL pointer is physical start address. */
44447 #define HWRM_CFA_CTX_MEM_QCTX_OUTPUT_PAGE_LEVEL_LVL_0 UINT32_C(0x0)
44448 /* PBL pointer points to PTE table. */
44449 #define HWRM_CFA_CTX_MEM_QCTX_OUTPUT_PAGE_LEVEL_LVL_1 UINT32_C(0x1)
44451 * PBL pointer points to PDE table with each entry pointing to PTE
44454 #define HWRM_CFA_CTX_MEM_QCTX_OUTPUT_PAGE_LEVEL_LVL_2 UINT32_C(0x2)
44455 #define HWRM_CFA_CTX_MEM_QCTX_OUTPUT_PAGE_LEVEL_LAST \
44456 HWRM_CFA_CTX_MEM_QCTX_OUTPUT_PAGE_LEVEL_LVL_2
44459 /* 4KB page size. */
44460 #define HWRM_CFA_CTX_MEM_QCTX_OUTPUT_PAGE_SIZE_4K UINT32_C(0x0)
44461 /* 8KB page size. */
44462 #define HWRM_CFA_CTX_MEM_QCTX_OUTPUT_PAGE_SIZE_8K UINT32_C(0x1)
44463 /* 64KB page size. */
44464 #define HWRM_CFA_CTX_MEM_QCTX_OUTPUT_PAGE_SIZE_64K UINT32_C(0x4)
44465 /* 256KB page size. */
44466 #define HWRM_CFA_CTX_MEM_QCTX_OUTPUT_PAGE_SIZE_256K UINT32_C(0x6)
44467 /* 1MB page size. */
44468 #define HWRM_CFA_CTX_MEM_QCTX_OUTPUT_PAGE_SIZE_1M UINT32_C(0x8)
44469 /* 2MB page size. */
44470 #define HWRM_CFA_CTX_MEM_QCTX_OUTPUT_PAGE_SIZE_2M UINT32_C(0x9)
44471 /* 4MB page size. */
44472 #define HWRM_CFA_CTX_MEM_QCTX_OUTPUT_PAGE_SIZE_4M UINT32_C(0xa)
44473 /* 1GB page size. */
44474 #define HWRM_CFA_CTX_MEM_QCTX_OUTPUT_PAGE_SIZE_1G UINT32_C(0x12)
44475 #define HWRM_CFA_CTX_MEM_QCTX_OUTPUT_PAGE_SIZE_LAST \
44476 HWRM_CFA_CTX_MEM_QCTX_OUTPUT_PAGE_SIZE_1G
44477 uint8_t unused_0[4];
44478 /* Pointer to the PBL, or PDL depending on number of levels */
44480 uint8_t unused_1[7];
44482 * This field is used in Output records to indicate that the output
44483 * is completely written to RAM. This field should be read as '1'
44484 * to indicate that the output has been completely written.
44485 * When writing a command completion or response to an internal
44486 * processor, the order of writes has to be such that this field is
44492 /**************************
44493 * hwrm_cfa_ctx_mem_qcaps *
44494 **************************/
44497 /* hwrm_cfa_ctx_mem_qcaps_input (size:128b/16B) */
44498 struct hwrm_cfa_ctx_mem_qcaps_input {
44499 /* The HWRM command request type. */
44502 * The completion ring to send the completion event on. This should
44503 * be the NQ ID returned from the `nq_alloc` HWRM command.
44505 uint16_t cmpl_ring;
44507 * The sequence ID is used by the driver for tracking multiple
44508 * commands. This ID is treated as opaque data by the firmware and
44509 * the value is returned in the `hwrm_resp_hdr` upon completion.
44513 * The target ID of the command:
44514 * * 0x0-0xFFF8 - The function ID
44515 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
44516 * * 0xFFFD - Reserved for user-space HWRM interface
44519 uint16_t target_id;
44521 * A physical address pointer pointing to a host buffer that the
44522 * command's response data will be written. This can be either a host
44523 * physical address (HPA) or a guest physical address (GPA) and must
44524 * point to a physically contiguous block of memory.
44526 uint64_t resp_addr;
44529 /* hwrm_cfa_ctx_mem_qcaps_output (size:128b/16B) */
44530 struct hwrm_cfa_ctx_mem_qcaps_output {
44531 /* The specific error status for the command. */
44532 uint16_t error_code;
44533 /* The HWRM command request type. */
44535 /* The sequence ID from the original command. */
44537 /* The length of the response data in number of bytes. */
44540 * Indicates the maximum number of context memory which can be
44543 uint16_t max_entries;
44544 uint8_t unused_0[5];
44546 * This field is used in Output records to indicate that the output
44547 * is completely written to RAM. This field should be read as '1'
44548 * to indicate that the output has been completely written.
44549 * When writing a command completion or response to an internal
44550 * processor, the order of writes has to be such that this field is
44556 /**************************
44557 * hwrm_cfa_counter_qcaps *
44558 **************************/
44561 /* hwrm_cfa_counter_qcaps_input (size:128b/16B) */
44562 struct hwrm_cfa_counter_qcaps_input {
44563 /* The HWRM command request type. */
44566 * The completion ring to send the completion event on. This should
44567 * be the NQ ID returned from the `nq_alloc` HWRM command.
44569 uint16_t cmpl_ring;
44571 * The sequence ID is used by the driver for tracking multiple
44572 * commands. This ID is treated as opaque data by the firmware and
44573 * the value is returned in the `hwrm_resp_hdr` upon completion.
44577 * The target ID of the command:
44578 * * 0x0-0xFFF8 - The function ID
44579 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
44580 * * 0xFFFD - Reserved for user-space HWRM interface
44583 uint16_t target_id;
44585 * A physical address pointer pointing to a host buffer that the
44586 * command's response data will be written. This can be either a host
44587 * physical address (HPA) or a guest physical address (GPA) and must
44588 * point to a physically contiguous block of memory.
44590 uint64_t resp_addr;
44593 /* hwrm_cfa_counter_qcaps_output (size:576b/72B) */
44594 struct hwrm_cfa_counter_qcaps_output {
44595 /* The specific error status for the command. */
44596 uint16_t error_code;
44597 /* The HWRM command request type. */
44599 /* The sequence ID from the original command. */
44601 /* The length of the response data in number of bytes. */
44604 /* Enumeration denoting the supported CFA counter format. */
44605 #define HWRM_CFA_COUNTER_QCAPS_OUTPUT_FLAGS_COUNTER_FORMAT \
44607 /* CFA counter types are not supported. */
44608 #define HWRM_CFA_COUNTER_QCAPS_OUTPUT_FLAGS_COUNTER_FORMAT_NONE \
44610 /* 64-bit packet counters followed by 64-bit byte counters format. */
44611 #define HWRM_CFA_COUNTER_QCAPS_OUTPUT_FLAGS_COUNTER_FORMAT_64_BIT \
44613 #define HWRM_CFA_COUNTER_QCAPS_OUTPUT_FLAGS_COUNTER_FORMAT_LAST \
44614 HWRM_CFA_COUNTER_QCAPS_OUTPUT_FLAGS_COUNTER_FORMAT_64_BIT
44617 * Minimum guaranteed number of flow counters supported for this
44618 * function, in RX direction.
44620 uint32_t min_rx_fc;
44622 * Maximum non-guaranteed number of flow counters supported for this
44623 * function, in RX direction.
44625 uint32_t max_rx_fc;
44627 * Minimum guaranteed number of flow counters supported for this
44628 * function, in TX direction.
44630 uint32_t min_tx_fc;
44632 * Maximum non-guaranteed number of flow counters supported for this
44633 * function, in TX direction.
44635 uint32_t max_tx_fc;
44637 * Minimum guaranteed number of extension flow counters supported for
44638 * this function, in RX direction.
44640 uint32_t min_rx_efc;
44642 * Maximum non-guaranteed number of extension flow counters supported
44643 * for this function, in RX direction.
44645 uint32_t max_rx_efc;
44647 * Minimum guaranteed number of extension flow counters supported for
44648 * this function, in TX direction.
44650 uint32_t min_tx_efc;
44652 * Maximum non-guaranteed number of extension flow counters supported
44653 * for this function, in TX direction.
44655 uint32_t max_tx_efc;
44657 * Minimum guaranteed number of meter drop counters supported for
44658 * this function, in RX direction.
44660 uint32_t min_rx_mdc;
44662 * Maximum non-guaranteed number of meter drop counters supported for
44663 * this function, in RX direction.
44665 uint32_t max_rx_mdc;
44667 * Minimum guaranteed number of meter drop counters supported for this
44668 * function, in TX direction.
44670 uint32_t min_tx_mdc;
44672 * Maximum non-guaranteed number of meter drop counters supported for
44673 * this function, in TX direction.
44675 uint32_t max_tx_mdc;
44677 * Maximum guaranteed number of flow counters which can be used during
44680 uint32_t max_flow_alloc_fc;
44681 uint8_t unused_1[3];
44683 * This field is used in Output records to indicate that the output
44684 * is completely written to RAM. This field should be read as '1'
44685 * to indicate that the output has been completely written.
44686 * When writing a command completion or response to an internal
44687 * processor, the order of writes has to be such that this field is
44693 /************************
44694 * hwrm_cfa_counter_cfg *
44695 ************************/
44698 /* hwrm_cfa_counter_cfg_input (size:256b/32B) */
44699 struct hwrm_cfa_counter_cfg_input {
44700 /* The HWRM command request type. */
44703 * The completion ring to send the completion event on. This should
44704 * be the NQ ID returned from the `nq_alloc` HWRM command.
44706 uint16_t cmpl_ring;
44708 * The sequence ID is used by the driver for tracking multiple
44709 * commands. This ID is treated as opaque data by the firmware and
44710 * the value is returned in the `hwrm_resp_hdr` upon completion.
44714 * The target ID of the command:
44715 * * 0x0-0xFFF8 - The function ID
44716 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
44717 * * 0xFFFD - Reserved for user-space HWRM interface
44720 uint16_t target_id;
44722 * A physical address pointer pointing to a host buffer that the
44723 * command's response data will be written. This can be either a host
44724 * physical address (HPA) or a guest physical address (GPA) and must
44725 * point to a physically contiguous block of memory.
44727 uint64_t resp_addr;
44729 /* Enumeration denoting the configuration mode. */
44730 #define HWRM_CFA_COUNTER_CFG_INPUT_FLAGS_CFG_MODE \
44732 /* Disable the configuration mode. */
44733 #define HWRM_CFA_COUNTER_CFG_INPUT_FLAGS_CFG_MODE_DISABLE \
44735 /* Enable the configuration mode. */
44736 #define HWRM_CFA_COUNTER_CFG_INPUT_FLAGS_CFG_MODE_ENABLE \
44738 #define HWRM_CFA_COUNTER_CFG_INPUT_FLAGS_CFG_MODE_LAST \
44739 HWRM_CFA_COUNTER_CFG_INPUT_FLAGS_CFG_MODE_ENABLE
44740 /* Enumeration denoting the RX, TX type of the resource. */
44741 #define HWRM_CFA_COUNTER_CFG_INPUT_FLAGS_PATH \
44744 #define HWRM_CFA_COUNTER_CFG_INPUT_FLAGS_PATH_TX \
44745 (UINT32_C(0x0) << 1)
44747 #define HWRM_CFA_COUNTER_CFG_INPUT_FLAGS_PATH_RX \
44748 (UINT32_C(0x1) << 1)
44749 #define HWRM_CFA_COUNTER_CFG_INPUT_FLAGS_PATH_LAST \
44750 HWRM_CFA_COUNTER_CFG_INPUT_FLAGS_PATH_RX
44751 /* Enumeration denoting the data transfer mode. */
44752 #define HWRM_CFA_COUNTER_CFG_INPUT_FLAGS_DATA_TRANSFER_MODE_MASK \
44754 #define HWRM_CFA_COUNTER_CFG_INPUT_FLAGS_DATA_TRANSFER_MODE_SFT 2
44756 #define HWRM_CFA_COUNTER_CFG_INPUT_FLAGS_DATA_TRANSFER_MODE_PUSH \
44757 (UINT32_C(0x0) << 2)
44759 #define HWRM_CFA_COUNTER_CFG_INPUT_FLAGS_DATA_TRANSFER_MODE_PULL \
44760 (UINT32_C(0x1) << 2)
44761 /* Pull on async update. */
44762 #define HWRM_CFA_COUNTER_CFG_INPUT_FLAGS_DATA_TRANSFER_MODE_PULL_ASYNC \
44763 (UINT32_C(0x2) << 2)
44764 #define HWRM_CFA_COUNTER_CFG_INPUT_FLAGS_DATA_TRANSFER_MODE_LAST \
44765 HWRM_CFA_COUNTER_CFG_INPUT_FLAGS_DATA_TRANSFER_MODE_PULL_ASYNC
44766 uint16_t counter_type;
44767 /* Flow counters. */
44768 #define HWRM_CFA_COUNTER_CFG_INPUT_COUNTER_TYPE_FC UINT32_C(0x0)
44769 /* Extended flow counters. */
44770 #define HWRM_CFA_COUNTER_CFG_INPUT_COUNTER_TYPE_EFC UINT32_C(0x1)
44771 /* Meter drop counters. */
44772 #define HWRM_CFA_COUNTER_CFG_INPUT_COUNTER_TYPE_MDC UINT32_C(0x2)
44773 #define HWRM_CFA_COUNTER_CFG_INPUT_COUNTER_TYPE_LAST \
44774 HWRM_CFA_COUNTER_CFG_INPUT_COUNTER_TYPE_MDC
44775 /* Ctx memory handle to be used for the counter. */
44777 /* Counter update cadence hint (only in Push mode). */
44778 uint16_t update_tmr_ms;
44779 /* Total number of entries. */
44780 uint32_t num_entries;
44784 /* hwrm_cfa_counter_cfg_output (size:128b/16B) */
44785 struct hwrm_cfa_counter_cfg_output {
44786 /* The specific error status for the command. */
44787 uint16_t error_code;
44788 /* The HWRM command request type. */
44790 /* The sequence ID from the original command. */
44792 /* The length of the response data in number of bytes. */
44794 uint8_t unused_0[7];
44796 * This field is used in Output records to indicate that the output
44797 * is completely written to RAM. This field should be read as '1'
44798 * to indicate that the output has been completely written.
44799 * When writing a command completion or response to an internal
44800 * processor, the order of writes has to be such that this field is
44806 /***************************
44807 * hwrm_cfa_counter_qstats *
44808 ***************************/
44811 /* hwrm_cfa_counter_qstats_input (size:320b/40B) */
44812 struct hwrm_cfa_counter_qstats_input {
44813 /* The HWRM command request type. */
44816 * The completion ring to send the completion event on. This should
44817 * be the NQ ID returned from the `nq_alloc` HWRM command.
44819 uint16_t cmpl_ring;
44821 * The sequence ID is used by the driver for tracking multiple
44822 * commands. This ID is treated as opaque data by the firmware and
44823 * the value is returned in the `hwrm_resp_hdr` upon completion.
44827 * The target ID of the command:
44828 * * 0x0-0xFFF8 - The function ID
44829 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
44830 * * 0xFFFD - Reserved for user-space HWRM interface
44833 uint16_t target_id;
44835 * A physical address pointer pointing to a host buffer that the
44836 * command's response data will be written. This can be either a host
44837 * physical address (HPA) or a guest physical address (GPA) and must
44838 * point to a physically contiguous block of memory.
44840 uint64_t resp_addr;
44842 /* Enumeration denoting the RX, TX type of the resource. */
44843 #define HWRM_CFA_COUNTER_QSTATS_INPUT_FLAGS_PATH UINT32_C(0x1)
44845 #define HWRM_CFA_COUNTER_QSTATS_INPUT_FLAGS_PATH_TX UINT32_C(0x0)
44847 #define HWRM_CFA_COUNTER_QSTATS_INPUT_FLAGS_PATH_RX UINT32_C(0x1)
44848 #define HWRM_CFA_COUNTER_QSTATS_INPUT_FLAGS_PATH_LAST \
44849 HWRM_CFA_COUNTER_QSTATS_INPUT_FLAGS_PATH_RX
44850 uint16_t counter_type;
44851 uint16_t input_flow_ctx_id;
44852 uint16_t num_entries;
44853 uint16_t delta_time_ms;
44854 uint16_t meter_instance_id;
44855 uint16_t mdc_ctx_id;
44856 uint8_t unused_0[2];
44857 uint64_t expected_count;
44860 /* hwrm_cfa_counter_qstats_output (size:128b/16B) */
44861 struct hwrm_cfa_counter_qstats_output {
44862 /* The specific error status for the command. */
44863 uint16_t error_code;
44864 /* The HWRM command request type. */
44866 /* The sequence ID from the original command. */
44868 /* The length of the response data in number of bytes. */
44870 uint8_t unused_0[7];
44872 * This field is used in Output records to indicate that the output
44873 * is completely written to RAM. This field should be read as '1'
44874 * to indicate that the output has been completely written.
44875 * When writing a command completion or response to an internal
44876 * processor, the order of writes has to be such that this field is
44882 /**********************
44883 * hwrm_cfa_eem_qcaps *
44884 **********************/
44887 /* hwrm_cfa_eem_qcaps_input (size:192b/24B) */
44888 struct hwrm_cfa_eem_qcaps_input {
44889 /* The HWRM command request type. */
44892 * The completion ring to send the completion event on. This should
44893 * be the NQ ID returned from the `nq_alloc` HWRM command.
44895 uint16_t cmpl_ring;
44897 * The sequence ID is used by the driver for tracking multiple
44898 * commands. This ID is treated as opaque data by the firmware and
44899 * the value is returned in the `hwrm_resp_hdr` upon completion.
44903 * The target ID of the command:
44904 * * 0x0-0xFFF8 - The function ID
44905 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
44906 * * 0xFFFD - Reserved for user-space HWRM interface
44909 uint16_t target_id;
44911 * A physical address pointer pointing to a host buffer that the
44912 * command's response data will be written. This can be either a host
44913 * physical address (HPA) or a guest physical address (GPA) and must
44914 * point to a physically contiguous block of memory.
44916 uint64_t resp_addr;
44919 * When set to 1, indicates the configuration will apply to TX flows
44920 * which are to be offloaded.
44921 * Note if this bit is set then the path_rx bit can't be set.
44923 #define HWRM_CFA_EEM_QCAPS_INPUT_FLAGS_PATH_TX \
44926 * When set to 1, indicates the configuration will apply to RX flows
44927 * which are to be offloaded.
44928 * Note if this bit is set then the path_tx bit can't be set.
44930 #define HWRM_CFA_EEM_QCAPS_INPUT_FLAGS_PATH_RX \
44932 /* When set to 1, all offloaded flows will be sent to EEM. */
44933 #define HWRM_CFA_EEM_QCAPS_INPUT_FLAGS_PREFERRED_OFFLOAD \
44938 /* hwrm_cfa_eem_qcaps_output (size:320b/40B) */
44939 struct hwrm_cfa_eem_qcaps_output {
44940 /* The specific error status for the command. */
44941 uint16_t error_code;
44942 /* The HWRM command request type. */
44944 /* The sequence ID from the original command. */
44946 /* The length of the response data in number of bytes. */
44950 * When set to 1, indicates the configuration will apply to TX flows
44951 * which are to be offloaded.
44952 * Note if this bit is set then the path_rx bit can't be set.
44954 #define HWRM_CFA_EEM_QCAPS_OUTPUT_FLAGS_PATH_TX \
44957 * When set to 1, indicates the configuration will apply to RX flows
44958 * which are to be offloaded.
44959 * Note if this bit is set then the path_tx bit can't be set.
44961 #define HWRM_CFA_EEM_QCAPS_OUTPUT_FLAGS_PATH_RX \
44964 * When set to 1, indicates the FW supports the Centralized
44965 * Memory Model. The concept designates one entity for the
44966 * memory allocation while all others ‘subscribe’ to it.
44968 #define HWRM_CFA_EEM_QCAPS_OUTPUT_FLAGS_CENTRALIZED_MEMORY_MODEL_SUPPORTED \
44971 * When set to 1, indicates the FW supports the Detached
44972 * Centralized Memory Model. The memory is allocated and managed
44973 * as a separate entity. All PFs and VFs will be granted direct
44974 * or semi-direct access to the allocated memory while none of
44975 * which can interfere with the management of the memory.
44977 #define HWRM_CFA_EEM_QCAPS_OUTPUT_FLAGS_DETACHED_CENTRALIZED_MEMORY_MODEL_SUPPORTED \
44980 uint32_t supported;
44982 * If set to 1, then EEM KEY0 table is supported using crc32 hash.
44983 * If set to 0, EEM KEY0 table is not supported.
44985 #define HWRM_CFA_EEM_QCAPS_OUTPUT_SUPPORTED_KEY0_TABLE \
44988 * If set to 1, then EEM KEY1 table is supported using lookup3 hash.
44989 * If set to 0, EEM KEY1 table is not supported.
44991 #define HWRM_CFA_EEM_QCAPS_OUTPUT_SUPPORTED_KEY1_TABLE \
44994 * If set to 1, then EEM External Record table is supported.
44995 * If set to 0, EEM External Record table is not supported.
44996 * (This table includes action record, EFC pointers, encap pointers)
44998 #define HWRM_CFA_EEM_QCAPS_OUTPUT_SUPPORTED_EXTERNAL_RECORD_TABLE \
45001 * If set to 1, then EEM External Flow Counters table is supported.
45002 * If set to 0, EEM External Flow Counters table is not supported.
45004 #define HWRM_CFA_EEM_QCAPS_OUTPUT_SUPPORTED_EXTERNAL_FLOW_COUNTERS_TABLE \
45007 * If set to 1, then FID table used for implicit flow flush is
45009 * If set to 0, then FID table used for implicit flow flush is
45012 #define HWRM_CFA_EEM_QCAPS_OUTPUT_SUPPORTED_FID_TABLE \
45015 * The maximum number of entries supported by EEM. When configuring
45016 * the host memory, the number of numbers of entries that can
45018 * 32k, 64k 128k, 256k, 512k, 1M, 2M, 4M, 8M, 32M, 64M, 128M
45020 * Any value that are not these values, the FW will round down to the
45021 * closest support number of entries.
45023 uint32_t max_entries_supported;
45024 /* The entry size in bytes of each entry in the EEM KEY0/KEY1 tables. */
45025 uint16_t key_entry_size;
45026 /* The entry size in bytes of each entry in the EEM RECORD tables. */
45027 uint16_t record_entry_size;
45028 /* The entry size in bytes of each entry in the EEM EFC tables. */
45029 uint16_t efc_entry_size;
45030 /* The FID size in bytes of each entry in the EEM FID tables. */
45031 uint16_t fid_entry_size;
45032 uint8_t unused_1[7];
45034 * This field is used in Output records to indicate that the output
45035 * is completely written to RAM. This field should be read as '1'
45036 * to indicate that the output has been completely written.
45037 * When writing a command completion or response to an internal
45038 * processor, the order of writes has to be such that this field is
45044 /********************
45045 * hwrm_cfa_eem_cfg *
45046 ********************/
45049 /* hwrm_cfa_eem_cfg_input (size:384b/48B) */
45050 struct hwrm_cfa_eem_cfg_input {
45051 /* The HWRM command request type. */
45054 * The completion ring to send the completion event on. This should
45055 * be the NQ ID returned from the `nq_alloc` HWRM command.
45057 uint16_t cmpl_ring;
45059 * The sequence ID is used by the driver for tracking multiple
45060 * commands. This ID is treated as opaque data by the firmware and
45061 * the value is returned in the `hwrm_resp_hdr` upon completion.
45065 * The target ID of the command:
45066 * * 0x0-0xFFF8 - The function ID
45067 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
45068 * * 0xFFFD - Reserved for user-space HWRM interface
45071 uint16_t target_id;
45073 * A physical address pointer pointing to a host buffer that the
45074 * command's response data will be written. This can be either a host
45075 * physical address (HPA) or a guest physical address (GPA) and must
45076 * point to a physically contiguous block of memory.
45078 uint64_t resp_addr;
45081 * When set to 1, indicates the configuration will apply to TX flows
45082 * which are to be offloaded.
45083 * Note if this bit is set then the path_rx bit can't be set.
45085 #define HWRM_CFA_EEM_CFG_INPUT_FLAGS_PATH_TX \
45088 * When set to 1, indicates the configuration will apply to RX flows
45089 * which are to be offloaded.
45090 * Note if this bit is set then the path_tx bit can't be set.
45092 #define HWRM_CFA_EEM_CFG_INPUT_FLAGS_PATH_RX \
45094 /* When set to 1, all offloaded flows will be sent to EEM. */
45095 #define HWRM_CFA_EEM_CFG_INPUT_FLAGS_PREFERRED_OFFLOAD \
45097 /* When set to 1, secondary, 0 means primary. */
45098 #define HWRM_CFA_EEM_CFG_INPUT_FLAGS_SECONDARY_PF \
45101 * Group_id which used by Firmware to identify memory pools belonging
45102 * to certain group.
45107 * Configured EEM with the given number of entries. All the EEM tables
45108 * KEY0, KEY1, RECORD, EFC all have the same number of entries and all
45109 * tables will be configured using this value. Current minimum value
45110 * is 32k. Current maximum value is 128M.
45112 uint32_t num_entries;
45114 /* Configured EEM with the given context if for KEY0 table. */
45115 uint16_t key0_ctx_id;
45116 /* Configured EEM with the given context if for KEY1 table. */
45117 uint16_t key1_ctx_id;
45118 /* Configured EEM with the given context if for RECORD table. */
45119 uint16_t record_ctx_id;
45120 /* Configured EEM with the given context if for EFC table. */
45121 uint16_t efc_ctx_id;
45122 /* Configured EEM with the given context if for EFC table. */
45123 uint16_t fid_ctx_id;
45128 /* hwrm_cfa_eem_cfg_output (size:128b/16B) */
45129 struct hwrm_cfa_eem_cfg_output {
45130 /* The specific error status for the command. */
45131 uint16_t error_code;
45132 /* The HWRM command request type. */
45134 /* The sequence ID from the original command. */
45136 /* The length of the response data in number of bytes. */
45138 uint8_t unused_0[7];
45140 * This field is used in Output records to indicate that the output
45141 * is completely written to RAM. This field should be read as '1'
45142 * to indicate that the output has been completely written.
45143 * When writing a command completion or response to an internal
45144 * processor, the order of writes has to be such that this field is
45150 /*********************
45151 * hwrm_cfa_eem_qcfg *
45152 *********************/
45155 /* hwrm_cfa_eem_qcfg_input (size:192b/24B) */
45156 struct hwrm_cfa_eem_qcfg_input {
45157 /* The HWRM command request type. */
45160 * The completion ring to send the completion event on. This should
45161 * be the NQ ID returned from the `nq_alloc` HWRM command.
45163 uint16_t cmpl_ring;
45165 * The sequence ID is used by the driver for tracking multiple
45166 * commands. This ID is treated as opaque data by the firmware and
45167 * the value is returned in the `hwrm_resp_hdr` upon completion.
45171 * The target ID of the command:
45172 * * 0x0-0xFFF8 - The function ID
45173 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
45174 * * 0xFFFD - Reserved for user-space HWRM interface
45177 uint16_t target_id;
45179 * A physical address pointer pointing to a host buffer that the
45180 * command's response data will be written. This can be either a host
45181 * physical address (HPA) or a guest physical address (GPA) and must
45182 * point to a physically contiguous block of memory.
45184 uint64_t resp_addr;
45186 /* When set to 1, indicates the configuration is the TX flow. */
45187 #define HWRM_CFA_EEM_QCFG_INPUT_FLAGS_PATH_TX UINT32_C(0x1)
45188 /* When set to 1, indicates the configuration is the RX flow. */
45189 #define HWRM_CFA_EEM_QCFG_INPUT_FLAGS_PATH_RX UINT32_C(0x2)
45193 /* hwrm_cfa_eem_qcfg_output (size:256b/32B) */
45194 struct hwrm_cfa_eem_qcfg_output {
45195 /* The specific error status for the command. */
45196 uint16_t error_code;
45197 /* The HWRM command request type. */
45199 /* The sequence ID from the original command. */
45201 /* The length of the response data in number of bytes. */
45204 /* When set to 1, indicates the configuration is the TX flow. */
45205 #define HWRM_CFA_EEM_QCFG_OUTPUT_FLAGS_PATH_TX \
45207 /* When set to 1, indicates the configuration is the RX flow. */
45208 #define HWRM_CFA_EEM_QCFG_OUTPUT_FLAGS_PATH_RX \
45210 /* When set to 1, all offloaded flows will be sent to EEM. */
45211 #define HWRM_CFA_EEM_QCFG_OUTPUT_FLAGS_PREFERRED_OFFLOAD \
45213 /* The number of entries the FW has configured for EEM. */
45214 uint32_t num_entries;
45215 /* Configured EEM with the given context if for KEY0 table. */
45216 uint16_t key0_ctx_id;
45217 /* Configured EEM with the given context if for KEY1 table. */
45218 uint16_t key1_ctx_id;
45219 /* Configured EEM with the given context if for RECORD table. */
45220 uint16_t record_ctx_id;
45221 /* Configured EEM with the given context if for EFC table. */
45222 uint16_t efc_ctx_id;
45223 /* Configured EEM with the given context if for EFC table. */
45224 uint16_t fid_ctx_id;
45225 uint8_t unused_2[5];
45227 * This field is used in Output records to indicate that the output
45228 * is completely written to RAM. This field should be read as '1'
45229 * to indicate that the output has been completely written.
45230 * When writing a command completion or response to an internal
45231 * processor, the order of writes has to be such that this field is
45237 /*******************
45238 * hwrm_cfa_eem_op *
45239 *******************/
45242 /* hwrm_cfa_eem_op_input (size:192b/24B) */
45243 struct hwrm_cfa_eem_op_input {
45244 /* The HWRM command request type. */
45247 * The completion ring to send the completion event on. This should
45248 * be the NQ ID returned from the `nq_alloc` HWRM command.
45250 uint16_t cmpl_ring;
45252 * The sequence ID is used by the driver for tracking multiple
45253 * commands. This ID is treated as opaque data by the firmware and
45254 * the value is returned in the `hwrm_resp_hdr` upon completion.
45258 * The target ID of the command:
45259 * * 0x0-0xFFF8 - The function ID
45260 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
45261 * * 0xFFFD - Reserved for user-space HWRM interface
45264 uint16_t target_id;
45266 * A physical address pointer pointing to a host buffer that the
45267 * command's response data will be written. This can be either a host
45268 * physical address (HPA) or a guest physical address (GPA) and must
45269 * point to a physically contiguous block of memory.
45271 uint64_t resp_addr;
45274 * When set to 1, indicates the host memory which is passed will be
45275 * used for the TX flow offload function specified in fid.
45276 * Note if this bit is set then the path_rx bit can't be set.
45278 #define HWRM_CFA_EEM_OP_INPUT_FLAGS_PATH_TX UINT32_C(0x1)
45280 * When set to 1, indicates the host memory which is passed will be
45281 * used for the RX flow offload function specified in fid.
45282 * Note if this bit is set then the path_tx bit can't be set.
45284 #define HWRM_CFA_EEM_OP_INPUT_FLAGS_PATH_RX UINT32_C(0x2)
45286 /* The number of EEM key table entries to be configured. */
45288 /* This value is reserved and should not be used. */
45289 #define HWRM_CFA_EEM_OP_INPUT_OP_RESERVED UINT32_C(0x0)
45291 * To properly stop EEM and ensure there are no DMA's, the caller
45292 * must disable EEM for the given PF, using this call. This will
45293 * safely disable EEM and ensure that all DMA'ed to the
45294 * keys/records/efc have been completed.
45296 #define HWRM_CFA_EEM_OP_INPUT_OP_EEM_DISABLE UINT32_C(0x1)
45298 * Once the EEM host memory has been configured, EEM options have
45299 * been configured. Then the caller should enable EEM for the given
45300 * PF. Note once this call has been made, then the EEM mechanism
45301 * will be active and DMA's will occur as packets are processed.
45303 #define HWRM_CFA_EEM_OP_INPUT_OP_EEM_ENABLE UINT32_C(0x2)
45305 * Clear EEM settings for the given PF so that the register values
45306 * are reset back to there initial state.
45308 #define HWRM_CFA_EEM_OP_INPUT_OP_EEM_CLEANUP UINT32_C(0x3)
45309 #define HWRM_CFA_EEM_OP_INPUT_OP_LAST \
45310 HWRM_CFA_EEM_OP_INPUT_OP_EEM_CLEANUP
45313 /* hwrm_cfa_eem_op_output (size:128b/16B) */
45314 struct hwrm_cfa_eem_op_output {
45315 /* The specific error status for the command. */
45316 uint16_t error_code;
45317 /* The HWRM command request type. */
45319 /* The sequence ID from the original command. */
45321 /* The length of the response data in number of bytes. */
45323 uint8_t unused_0[7];
45325 * This field is used in Output records to indicate that the output
45326 * is completely written to RAM. This field should be read as '1'
45327 * to indicate that the output has been completely written.
45328 * When writing a command completion or response to an internal
45329 * processor, the order of writes has to be such that this field is
45335 /********************************
45336 * hwrm_cfa_adv_flow_mgnt_qcaps *
45337 ********************************/
45340 /* hwrm_cfa_adv_flow_mgnt_qcaps_input (size:256b/32B) */
45341 struct hwrm_cfa_adv_flow_mgnt_qcaps_input {
45342 /* The HWRM command request type. */
45345 * The completion ring to send the completion event on. This should
45346 * be the NQ ID returned from the `nq_alloc` HWRM command.
45348 uint16_t cmpl_ring;
45350 * The sequence ID is used by the driver for tracking multiple
45351 * commands. This ID is treated as opaque data by the firmware and
45352 * the value is returned in the `hwrm_resp_hdr` upon completion.
45356 * The target ID of the command:
45357 * * 0x0-0xFFF8 - The function ID
45358 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
45359 * * 0xFFFD - Reserved for user-space HWRM interface
45362 uint16_t target_id;
45364 * A physical address pointer pointing to a host buffer that the
45365 * command's response data will be written. This can be either a host
45366 * physical address (HPA) or a guest physical address (GPA) and must
45367 * point to a physically contiguous block of memory.
45369 uint64_t resp_addr;
45370 uint32_t unused_0[4];
45373 /* hwrm_cfa_adv_flow_mgnt_qcaps_output (size:128b/16B) */
45374 struct hwrm_cfa_adv_flow_mgnt_qcaps_output {
45375 /* The specific error status for the command. */
45376 uint16_t error_code;
45377 /* The HWRM command request type. */
45379 /* The sequence ID from the original command. */
45381 /* The length of the response data in number of bytes. */
45385 * Value of 1 to indicate firmware support 16-bit flow handle.
45386 * Value of 0 to indicate firmware not support 16-bit flow handle.
45388 #define HWRM_CFA_ADV_FLOW_MGNT_QCAPS_OUTPUT_FLAGS_FLOW_HND_16BIT_SUPPORTED \
45391 * Value of 1 to indicate firmware support 64-bit flow handle.
45392 * Value of 0 to indicate firmware not support 64-bit flow handle.
45394 #define HWRM_CFA_ADV_FLOW_MGNT_QCAPS_OUTPUT_FLAGS_FLOW_HND_64BIT_SUPPORTED \
45397 * Value of 1 to indicate firmware support flow batch delete
45398 * operation through HWRM_CFA_FLOW_FLUSH command.
45399 * Value of 0 to indicate that the firmware does not support flow
45400 * batch delete operation.
45402 #define HWRM_CFA_ADV_FLOW_MGNT_QCAPS_OUTPUT_FLAGS_FLOW_BATCH_DELETE_SUPPORTED \
45405 * Value of 1 to indicate that the firmware support flow reset all
45406 * operation through HWRM_CFA_FLOW_FLUSH command.
45407 * Value of 0 indicates firmware does not support flow reset all
45410 #define HWRM_CFA_ADV_FLOW_MGNT_QCAPS_OUTPUT_FLAGS_FLOW_RESET_ALL_SUPPORTED \
45413 * Value of 1 to indicate that firmware supports use of FID as
45414 * dest_id in HWRM_CFA_NTUPLE_ALLOC/CFG commands.
45415 * Value of 0 indicates firmware does not support use of FID as
45418 #define HWRM_CFA_ADV_FLOW_MGNT_QCAPS_OUTPUT_FLAGS_NTUPLE_FLOW_DEST_FUNC_SUPPORTED \
45421 * Value of 1 to indicate that firmware supports TX EEM flows.
45422 * Value of 0 indicates firmware does not support TX EEM flows.
45424 #define HWRM_CFA_ADV_FLOW_MGNT_QCAPS_OUTPUT_FLAGS_TX_EEM_FLOW_SUPPORTED \
45427 * Value of 1 to indicate that firmware supports RX EEM flows.
45428 * Value of 0 indicates firmware does not support RX EEM flows.
45430 #define HWRM_CFA_ADV_FLOW_MGNT_QCAPS_OUTPUT_FLAGS_RX_EEM_FLOW_SUPPORTED \
45433 * Value of 1 to indicate that firmware supports the dynamic
45434 * allocation of an on-chip flow counter which can be used for EEM
45435 * flows. Value of 0 indicates firmware does not support the dynamic
45436 * allocation of an on-chip flow counter.
45438 #define HWRM_CFA_ADV_FLOW_MGNT_QCAPS_OUTPUT_FLAGS_FLOW_COUNTER_ALLOC_SUPPORTED \
45441 * Value of 1 to indicate that firmware supports setting of
45442 * rfs_ring_tbl_idx in HWRM_CFA_NTUPLE_ALLOC command.
45443 * Value of 0 indicates firmware does not support rfs_ring_tbl_idx.
45445 #define HWRM_CFA_ADV_FLOW_MGNT_QCAPS_OUTPUT_FLAGS_RFS_RING_TBL_IDX_SUPPORTED \
45448 * Value of 1 to indicate that firmware supports untagged matching
45449 * criteria on HWRM_CFA_L2_FILTER_ALLOC command. Value of 0
45450 * indicates firmware does not support untagged matching.
45452 #define HWRM_CFA_ADV_FLOW_MGNT_QCAPS_OUTPUT_FLAGS_UNTAGGED_VLAN_SUPPORTED \
45455 * Value of 1 to indicate that firmware supports XDP filter. Value
45456 * of 0 indicates firmware does not support XDP filter.
45458 #define HWRM_CFA_ADV_FLOW_MGNT_QCAPS_OUTPUT_FLAGS_XDP_SUPPORTED \
45461 * Value of 1 to indicate that the firmware support L2 header source
45462 * fields matching criteria on HWRM_CFA_L2_FILTER_ALLOC command.
45463 * Value of 0 indicates firmware does not support L2 header source
45466 #define HWRM_CFA_ADV_FLOW_MGNT_QCAPS_OUTPUT_FLAGS_L2_HEADER_SOURCE_FIELDS_SUPPORTED \
45469 * If set to 1, firmware is capable of supporting ARP ethertype as
45470 * matching criteria for HWRM_CFA_NTUPLE_FILTER_ALLOC command on the
45471 * RX direction. By default, this flag should be 0 for older version
45474 #define HWRM_CFA_ADV_FLOW_MGNT_QCAPS_OUTPUT_FLAGS_NTUPLE_FLOW_RX_ARP_SUPPORTED \
45477 * Value of 1 to indicate that firmware supports setting of
45478 * rfs_ring_tbl_idx in dst_id field of the HWRM_CFA_NTUPLE_ALLOC
45479 * command. Value of 0 indicates firmware does not support
45480 * rfs_ring_tbl_idx in dst_id field.
45482 #define HWRM_CFA_ADV_FLOW_MGNT_QCAPS_OUTPUT_FLAGS_RFS_RING_TBL_IDX_V2_SUPPORTED \
45485 * If set to 1, firmware is capable of supporting IPv4/IPv6 as
45486 * ethertype in HWRM_CFA_NTUPLE_FILTER_ALLOC command on the RX
45487 * direction. By default, this flag should be 0 for older version
45490 #define HWRM_CFA_ADV_FLOW_MGNT_QCAPS_OUTPUT_FLAGS_NTUPLE_FLOW_RX_ETHERTYPE_IP_SUPPORTED \
45493 * When this bit is '1', it indicates that core firmware is
45494 * capable of TruFlow. Driver can restrict sending HWRM CFA_FLOW_XXX
45495 * and CFA_ENCAP_XXX, CFA_DECAP_XXX commands.
45497 #define HWRM_CFA_ADV_FLOW_MGNT_QCAPS_OUTPUT_FLAGS_TRUFLOW_CAPABLE \
45500 * If set to 1, firmware is capable of supporting L2/ROCE as
45501 * traffic type in flags field of HWRM_CFA_L2_FILTER_ALLOC command.
45502 * By default, this flag should be 0 for older version of firmware.
45504 #define HWRM_CFA_ADV_FLOW_MGNT_QCAPS_OUTPUT_FLAGS_L2_FILTER_TRAFFIC_TYPE_L2_ROCE_SUPPORTED \
45507 * If set to 1, firmware is capable of HW LAG. This bit is only
45508 * advertised if the calling function is a PAXC function.
45510 #define HWRM_CFA_ADV_FLOW_MGNT_QCAPS_OUTPUT_FLAGS_LAG_SUPPORTED \
45513 * If set to 1, firmware is capable installing ntuple rules without
45514 * additional classification on the L2 Context.
45516 #define HWRM_CFA_ADV_FLOW_MGNT_QCAPS_OUTPUT_FLAGS_NTUPLE_FLOW_NO_L2CTX_SUPPORTED \
45518 uint8_t unused_0[3];
45520 * This field is used in Output records to indicate that the output
45521 * is completely written to RAM. This field should be read as '1'
45522 * to indicate that the output has been completely written.
45523 * When writing a command completion or response to an internal
45524 * processor, the order of writes has to be such that this field is
45530 /******************
45532 ******************/
45535 /* hwrm_cfa_tflib_input (size:1024b/128B) */
45536 struct hwrm_cfa_tflib_input {
45537 /* The HWRM command request type. */
45540 * The completion ring to send the completion event on. This should
45541 * be the NQ ID returned from the `nq_alloc` HWRM command.
45543 uint16_t cmpl_ring;
45545 * The sequence ID is used by the driver for tracking multiple
45546 * commands. This ID is treated as opaque data by the firmware and
45547 * the value is returned in the `hwrm_resp_hdr` upon completion.
45551 * The target ID of the command:
45552 * * 0x0-0xFFF8 - The function ID
45553 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
45554 * * 0xFFFD - Reserved for user-space HWRM interface
45557 uint16_t target_id;
45559 * A physical address pointer pointing to a host buffer that the
45560 * command's response data will be written. This can be either a host
45561 * physical address (HPA) or a guest physical address (GPA) and must
45562 * point to a physically contiguous block of memory.
45564 uint64_t resp_addr;
45565 /* TFLIB message type. */
45567 /* TFLIB message subtype. */
45568 uint16_t tf_subtype;
45570 uint8_t unused0[4];
45571 /* TFLIB request data. */
45572 uint32_t tf_req[26];
45575 /* hwrm_cfa_tflib_output (size:5632b/704B) */
45576 struct hwrm_cfa_tflib_output {
45577 /* The specific error status for the command. */
45578 uint16_t error_code;
45579 /* The HWRM command request type. */
45581 /* The sequence ID from the original command. */
45583 /* The length of the response data in number of bytes. */
45585 /* TFLIB message type. */
45587 /* TFLIB message subtype. */
45588 uint16_t tf_subtype;
45589 /* TFLIB response code */
45590 uint32_t tf_resp_code;
45591 /* TFLIB response data. */
45592 uint32_t tf_resp[170];
45594 uint8_t unused1[7];
45596 * This field is used in Output records to indicate that the output
45597 * is completely written to RAM. This field should be read as '1'
45598 * to indicate that the output has been completely written.
45599 * When writing a command completion or response to an internal
45600 * processor, the order of writes has to be such that this field is
45606 /**********************************
45607 * hwrm_cfa_lag_group_member_rgtr *
45608 **********************************/
45611 /* hwrm_cfa_lag_group_member_rgtr_input (size:192b/24B) */
45612 struct hwrm_cfa_lag_group_member_rgtr_input {
45613 /* The HWRM command request type. */
45616 * The completion ring to send the completion event on. This should
45617 * be the NQ ID returned from the `nq_alloc` HWRM command.
45619 uint16_t cmpl_ring;
45621 * The sequence ID is used by the driver for tracking multiple
45622 * commands. This ID is treated as opaque data by the firmware and
45623 * the value is returned in the `hwrm_resp_hdr` upon completion.
45627 * The target ID of the command:
45628 * * 0x0-0xFFF8 - The function ID
45629 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
45630 * * 0xFFFD - Reserved for user-space HWRM interface
45633 uint16_t target_id;
45635 * A physical address pointer pointing to a host buffer that the
45636 * command's response data will be written. This can be either a host
45637 * physical address (HPA) or a guest physical address (GPA) and must
45638 * point to a physically contiguous block of memory.
45640 uint64_t resp_addr;
45643 * Transmit only on the active port. Automatically failover
45646 #define HWRM_CFA_LAG_GROUP_MEMBER_RGTR_INPUT_MODE_ACTIVE_BACKUP \
45649 * Transmit based on packet header ntuple hash. Packet with only
45650 * layer 2 headers will hash using the destination MAC, source MAC
45651 * and Ethertype fields. Packets with layer 3 (IP) headers will
45652 * hash using the destination MAC, source MAC, IP protocol/next
45653 * header, source IP address and destination IP address. Packets
45654 * with layer 4 (TCP/UDP) headers will hash using the destination
45655 * MAC, source MAC, IP protocol/next header, source IP address,
45656 * destination IP address, source port and destination port fields.
45658 #define HWRM_CFA_LAG_GROUP_MEMBER_RGTR_INPUT_MODE_BALANCE_XOR \
45660 /* Transmit packets on all specified ports. */
45661 #define HWRM_CFA_LAG_GROUP_MEMBER_RGTR_INPUT_MODE_BROADCAST \
45663 #define HWRM_CFA_LAG_GROUP_MEMBER_RGTR_INPUT_MODE_LAST \
45664 HWRM_CFA_LAG_GROUP_MEMBER_RGTR_INPUT_MODE_BROADCAST
45666 * Supports up to 5 ports. bit0 = port 0, bit1 = port 1,
45667 * bit2 = port 2, bit3 = port 4, bit4 = loopback port
45669 uint8_t port_bitmap;
45670 /* Specify the active port when active-backup mode is specified */
45671 uint8_t active_port;
45672 uint8_t unused_0[5];
45675 /* hwrm_cfa_lag_group_member_rgtr_output (size:128b/16B) */
45676 struct hwrm_cfa_lag_group_member_rgtr_output {
45677 /* The specific error status for the command. */
45678 uint16_t error_code;
45679 /* The HWRM command request type. */
45681 /* The sequence ID from the original command. */
45683 /* The length of the response data in number of bytes. */
45685 /* lag group ID configured for the function */
45687 uint8_t unused_0[5];
45689 * This field is used in Output records to indicate that the output
45690 * is completely written to RAM. This field should be read as '1'
45691 * to indicate that the output has been completely written.
45692 * When writing a command completion or response to an internal
45693 * processor, the order of writes has to be such that this field is
45699 /************************************
45700 * hwrm_cfa_lag_group_member_unrgtr *
45701 ************************************/
45704 /* hwrm_cfa_lag_group_member_unrgtr_input (size:192b/24B) */
45705 struct hwrm_cfa_lag_group_member_unrgtr_input {
45706 /* The HWRM command request type. */
45709 * The completion ring to send the completion event on. This should
45710 * be the NQ ID returned from the `nq_alloc` HWRM command.
45712 uint16_t cmpl_ring;
45714 * The sequence ID is used by the driver for tracking multiple
45715 * commands. This ID is treated as opaque data by the firmware and
45716 * the value is returned in the `hwrm_resp_hdr` upon completion.
45720 * The target ID of the command:
45721 * * 0x0-0xFFF8 - The function ID
45722 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
45723 * * 0xFFFD - Reserved for user-space HWRM interface
45726 uint16_t target_id;
45728 * A physical address pointer pointing to a host buffer that the
45729 * command's response data will be written. This can be either a host
45730 * physical address (HPA) or a guest physical address (GPA) and must
45731 * point to a physically contiguous block of memory.
45733 uint64_t resp_addr;
45734 /* lag group ID configured for the function */
45736 uint8_t unused_0[6];
45739 /* hwrm_cfa_lag_group_member_unrgtr_output (size:128b/16B) */
45740 struct hwrm_cfa_lag_group_member_unrgtr_output {
45741 /* The specific error status for the command. */
45742 uint16_t error_code;
45743 /* The HWRM command request type. */
45745 /* The sequence ID from the original command. */
45747 /* The length of the response data in number of bytes. */
45749 uint8_t unused_0[7];
45751 * This field is used in Output records to indicate that the output
45752 * is completely written to RAM. This field should be read as '1'
45753 * to indicate that the output has been completely written.
45754 * When writing a command completion or response to an internal
45755 * processor, the order of writes has to be such that this field is
45766 /* hwrm_tf_input (size:1024b/128B) */
45767 struct hwrm_tf_input {
45768 /* The HWRM command request type. */
45771 * The completion ring to send the completion event on. This should
45772 * be the NQ ID returned from the `nq_alloc` HWRM command.
45774 uint16_t cmpl_ring;
45776 * The sequence ID is used by the driver for tracking multiple
45777 * commands. This ID is treated as opaque data by the firmware and
45778 * the value is returned in the `hwrm_resp_hdr` upon completion.
45782 * The target ID of the command:
45783 * * 0x0-0xFFF8 - The function ID
45784 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
45785 * * 0xFFFD - Reserved for user-space HWRM interface
45788 uint16_t target_id;
45790 * A physical address pointer pointing to a host buffer that the
45791 * command's response data will be written. This can be either a host
45792 * physical address (HPA) or a guest physical address (GPA) and must
45793 * point to a physically contiguous block of memory.
45795 uint64_t resp_addr;
45796 /* TF message type. */
45798 /* TF message subtype. */
45801 uint8_t unused0[4];
45802 /* TF request data. */
45806 /* hwrm_tf_output (size:5632b/704B) */
45807 struct hwrm_tf_output {
45808 /* The specific error status for the command. */
45809 uint16_t error_code;
45810 /* The HWRM command request type. */
45812 /* The sequence ID from the original command. */
45814 /* The length of the response data in number of bytes. */
45816 /* TF message type. */
45818 /* TF message subtype. */
45820 /* TF response code */
45821 uint32_t resp_code;
45822 /* TF response data. */
45823 uint32_t resp[170];
45825 uint8_t unused1[7];
45827 * This field is used in Output records to indicate that the
45828 * output is completely written to RAM. This field should be
45829 * read as '1' to indicate that the output has been
45830 * completely written. When writing a command completion or
45831 * response to an internal processor, the order of writes has
45832 * to be such that this field is written last.
45837 /***********************
45838 * hwrm_tf_version_get *
45839 ***********************/
45842 /* hwrm_tf_version_get_input (size:128b/16B) */
45843 struct hwrm_tf_version_get_input {
45844 /* The HWRM command request type. */
45847 * The completion ring to send the completion event on. This should
45848 * be the NQ ID returned from the `nq_alloc` HWRM command.
45850 uint16_t cmpl_ring;
45852 * The sequence ID is used by the driver for tracking multiple
45853 * commands. This ID is treated as opaque data by the firmware and
45854 * the value is returned in the `hwrm_resp_hdr` upon completion.
45858 * The target ID of the command:
45859 * * 0x0-0xFFF8 - The function ID
45860 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
45861 * * 0xFFFD - Reserved for user-space HWRM interface
45864 uint16_t target_id;
45866 * A physical address pointer pointing to a host buffer that the
45867 * command's response data will be written. This can be either a host
45868 * physical address (HPA) or a guest physical address (GPA) and must
45869 * point to a physically contiguous block of memory.
45871 uint64_t resp_addr;
45874 /* hwrm_tf_version_get_output (size:256b/32B) */
45875 struct hwrm_tf_version_get_output {
45876 /* The specific error status for the command. */
45877 uint16_t error_code;
45878 /* The HWRM command request type. */
45880 /* The sequence ID from the original command. */
45882 /* The length of the response data in number of bytes. */
45884 /* Version Major number. */
45886 /* Version Minor number. */
45888 /* Version Update number. */
45891 uint8_t unused0[5];
45893 * This field is used to indicate device's capabilities and
45896 uint64_t dev_caps_cfg;
45898 uint8_t unused1[7];
45900 * This field is used in Output records to indicate that the output
45901 * is completely written to RAM. This field should be read as '1'
45902 * to indicate that the output has been completely written.
45903 * When writing a command completion or response to an internal
45904 * processor, the order of writes has to be such that this field is
45910 /************************
45911 * hwrm_tf_session_open *
45912 ************************/
45915 /* hwrm_tf_session_open_input (size:640b/80B) */
45916 struct hwrm_tf_session_open_input {
45917 /* The HWRM command request type. */
45920 * The completion ring to send the completion event on. This should
45921 * be the NQ ID returned from the `nq_alloc` HWRM command.
45923 uint16_t cmpl_ring;
45925 * The sequence ID is used by the driver for tracking multiple
45926 * commands. This ID is treated as opaque data by the firmware and
45927 * the value is returned in the `hwrm_resp_hdr` upon completion.
45931 * The target ID of the command:
45932 * * 0x0-0xFFF8 - The function ID
45933 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
45934 * * 0xFFFD - Reserved for user-space HWRM interface
45937 uint16_t target_id;
45939 * A physical address pointer pointing to a host buffer that the
45940 * command's response data will be written. This can be either a host
45941 * physical address (HPA) or a guest physical address (GPA) and must
45942 * point to a physically contiguous block of memory.
45944 uint64_t resp_addr;
45945 /* Name of the session. */
45946 uint8_t session_name[64];
45949 /* hwrm_tf_session_open_output (size:192b/24B) */
45950 struct hwrm_tf_session_open_output {
45951 /* The specific error status for the command. */
45952 uint16_t error_code;
45953 /* The HWRM command request type. */
45955 /* The sequence ID from the original command. */
45957 /* The length of the response data in number of bytes. */
45960 * Unique session identifier for the session created by the
45963 uint32_t fw_session_id;
45965 * Unique session client identifier for the first client on
45966 * the newly created session.
45968 uint32_t fw_session_client_id;
45969 /* This field is used to return the status of fw session to host. */
45972 * Indicates if the shared session has been created. Shared session
45973 * should be the first session created ever. Its fw_rm_client_id
45974 * should be 1. The AFM session's fw_rm_client_id is 0.
45976 #define HWRM_TF_SESSION_OPEN_OUTPUT_FLAGS_SHARED_SESSION \
45979 * If this bit set to 0, then it indicates the shared session
45980 * has been created by another session.
45982 #define HWRM_TF_SESSION_OPEN_OUTPUT_FLAGS_SHARED_SESSION_NOT_CREATOR \
45985 * If this bit is set to 1, then it indicates the shared session
45986 * is created by this session.
45988 #define HWRM_TF_SESSION_OPEN_OUTPUT_FLAGS_SHARED_SESSION_CREATOR \
45990 #define HWRM_TF_SESSION_OPEN_OUTPUT_FLAGS_SHARED_SESSION_LAST \
45991 HWRM_TF_SESSION_OPEN_OUTPUT_FLAGS_SHARED_SESSION_CREATOR
45993 uint8_t unused1[3];
45995 * This field is used in Output records to indicate that the output
45996 * is completely written to RAM. This field should be read as '1'
45997 * to indicate that the output has been completely written.
45998 * When writing a command completion or response to an internal
45999 * processor, the order of writes has to be such that this field is
46005 /**************************
46006 * hwrm_tf_session_attach *
46007 **************************/
46010 /* hwrm_tf_session_attach_input (size:704b/88B) */
46011 struct hwrm_tf_session_attach_input {
46012 /* The HWRM command request type. */
46015 * The completion ring to send the completion event on. This should
46016 * be the NQ ID returned from the `nq_alloc` HWRM command.
46018 uint16_t cmpl_ring;
46020 * The sequence ID is used by the driver for tracking multiple
46021 * commands. This ID is treated as opaque data by the firmware and
46022 * the value is returned in the `hwrm_resp_hdr` upon completion.
46026 * The target ID of the command:
46027 * * 0x0-0xFFF8 - The function ID
46028 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
46029 * * 0xFFFD - Reserved for user-space HWRM interface
46032 uint16_t target_id;
46034 * A physical address pointer pointing to a host buffer that the
46035 * command's response data will be written. This can be either a host
46036 * physical address (HPA) or a guest physical address (GPA) and must
46037 * point to a physically contiguous block of memory.
46039 uint64_t resp_addr;
46041 * Unique session identifier for the session that the attach
46042 * request want to attach to. This value originates from the
46043 * shared session memory that the attach request opened by
46044 * way of the 'attach name' that was passed in to the core
46046 * The fw_session_id of the attach session includes PCIe bus
46047 * info to distinguish the PF and session info to identify
46048 * the associated TruFlow session.
46050 uint32_t attach_fw_session_id;
46053 /* Name of the session it self. */
46054 uint8_t session_name[64];
46057 /* hwrm_tf_session_attach_output (size:128b/16B) */
46058 struct hwrm_tf_session_attach_output {
46059 /* The specific error status for the command. */
46060 uint16_t error_code;
46061 /* The HWRM command request type. */
46063 /* The sequence ID from the original command. */
46065 /* The length of the response data in number of bytes. */
46068 * Unique session identifier for the session created by the
46069 * firmware. It includes PCIe bus info to distinguish the PF
46070 * and session info to identify the associated TruFlow
46071 * session. This fw_session_id is unique to the attach
46074 uint32_t fw_session_id;
46076 uint8_t unused0[3];
46078 * This field is used in Output records to indicate that the output
46079 * is completely written to RAM. This field should be read as '1'
46080 * to indicate that the output has been completely written.
46081 * When writing a command completion or response to an internal
46082 * processor, the order of writes has to be such that this field is
46088 /****************************
46089 * hwrm_tf_session_register *
46090 ****************************/
46093 /* hwrm_tf_session_register_input (size:704b/88B) */
46094 struct hwrm_tf_session_register_input {
46095 /* The HWRM command request type. */
46098 * The completion ring to send the completion event on. This should
46099 * be the NQ ID returned from the `nq_alloc` HWRM command.
46101 uint16_t cmpl_ring;
46103 * The sequence ID is used by the driver for tracking multiple
46104 * commands. This ID is treated as opaque data by the firmware and
46105 * the value is returned in the `hwrm_resp_hdr` upon completion.
46109 * The target ID of the command:
46110 * * 0x0-0xFFF8 - The function ID
46111 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
46112 * * 0xFFFD - Reserved for user-space HWRM interface
46115 uint16_t target_id;
46117 * A physical address pointer pointing to a host buffer that the
46118 * command's response data will be written. This can be either a host
46119 * physical address (HPA) or a guest physical address (GPA) and must
46120 * point to a physically contiguous block of memory.
46122 uint64_t resp_addr;
46124 * Unique session identifier for the session that the
46125 * register request want to create a new client on. This
46126 * value originates from the first open request.
46127 * The fw_session_id of the attach session includes PCIe bus
46128 * info to distinguish the PF and session info to identify
46129 * the associated TruFlow session.
46131 uint32_t fw_session_id;
46134 /* Name of the session client. */
46135 uint8_t session_client_name[64];
46138 /* hwrm_tf_session_register_output (size:128b/16B) */
46139 struct hwrm_tf_session_register_output {
46140 /* The specific error status for the command. */
46141 uint16_t error_code;
46142 /* The HWRM command request type. */
46144 /* The sequence ID from the original command. */
46146 /* The length of the response data in number of bytes. */
46149 * Unique session client identifier for the session created
46150 * by the firmware. It includes the session the client it
46151 * attached to and session client info.
46153 uint32_t fw_session_client_id;
46155 uint8_t unused0[3];
46157 * This field is used in Output records to indicate that the output
46158 * is completely written to RAM. This field should be read as '1'
46159 * to indicate that the output has been completely written.
46160 * When writing a command completion or response to an internal
46161 * processor, the order of writes has to be such that this field is
46167 /******************************
46168 * hwrm_tf_session_unregister *
46169 ******************************/
46172 /* hwrm_tf_session_unregister_input (size:192b/24B) */
46173 struct hwrm_tf_session_unregister_input {
46174 /* The HWRM command request type. */
46177 * The completion ring to send the completion event on. This should
46178 * be the NQ ID returned from the `nq_alloc` HWRM command.
46180 uint16_t cmpl_ring;
46182 * The sequence ID is used by the driver for tracking multiple
46183 * commands. This ID is treated as opaque data by the firmware and
46184 * the value is returned in the `hwrm_resp_hdr` upon completion.
46188 * The target ID of the command:
46189 * * 0x0-0xFFF8 - The function ID
46190 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
46191 * * 0xFFFD - Reserved for user-space HWRM interface
46194 uint16_t target_id;
46196 * A physical address pointer pointing to a host buffer that the
46197 * command's response data will be written. This can be either a host
46198 * physical address (HPA) or a guest physical address (GPA) and must
46199 * point to a physically contiguous block of memory.
46201 uint64_t resp_addr;
46203 * Unique session identifier for the session that the
46204 * unregister request want to close a session client on.
46206 uint32_t fw_session_id;
46208 * Unique session client identifier for the session that the
46209 * unregister request want to close.
46211 uint32_t fw_session_client_id;
46214 /* hwrm_tf_session_unregister_output (size:128b/16B) */
46215 struct hwrm_tf_session_unregister_output {
46216 /* The specific error status for the command. */
46217 uint16_t error_code;
46218 /* The HWRM command request type. */
46220 /* The sequence ID from the original command. */
46222 /* The length of the response data in number of bytes. */
46225 uint8_t unused0[7];
46227 * This field is used in Output records to indicate that the output
46228 * is completely written to RAM. This field should be read as '1'
46229 * to indicate that the output has been completely written.
46230 * When writing a command completion or response to an internal
46231 * processor, the order of writes has to be such that this field is
46237 /*************************
46238 * hwrm_tf_session_close *
46239 *************************/
46242 /* hwrm_tf_session_close_input (size:192b/24B) */
46243 struct hwrm_tf_session_close_input {
46244 /* The HWRM command request type. */
46247 * The completion ring to send the completion event on. This should
46248 * be the NQ ID returned from the `nq_alloc` HWRM command.
46250 uint16_t cmpl_ring;
46252 * The sequence ID is used by the driver for tracking multiple
46253 * commands. This ID is treated as opaque data by the firmware and
46254 * the value is returned in the `hwrm_resp_hdr` upon completion.
46258 * The target ID of the command:
46259 * * 0x0-0xFFF8 - The function ID
46260 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
46261 * * 0xFFFD - Reserved for user-space HWRM interface
46264 uint16_t target_id;
46266 * A physical address pointer pointing to a host buffer that the
46267 * command's response data will be written. This can be either a host
46268 * physical address (HPA) or a guest physical address (GPA) and must
46269 * point to a physically contiguous block of memory.
46271 uint64_t resp_addr;
46272 /* Firmware session id returned when HWRM_TF_SESSION_OPEN is sent. */
46273 uint32_t fw_session_id;
46275 uint8_t unused0[4];
46278 /* hwrm_tf_session_close_output (size:128b/16B) */
46279 struct hwrm_tf_session_close_output {
46280 /* The specific error status for the command. */
46281 uint16_t error_code;
46282 /* The HWRM command request type. */
46284 /* The sequence ID from the original command. */
46286 /* The length of the response data in number of bytes. */
46289 uint8_t unused0[7];
46291 * This field is used in Output records to indicate that the output
46292 * is completely written to RAM. This field should be read as '1'
46293 * to indicate that the output has been completely written.
46294 * When writing a command completion or response to an internal
46295 * processor, the order of writes has to be such that this field
46301 /************************
46302 * hwrm_tf_session_qcfg *
46303 ************************/
46306 /* hwrm_tf_session_qcfg_input (size:192b/24B) */
46307 struct hwrm_tf_session_qcfg_input {
46308 /* The HWRM command request type. */
46311 * The completion ring to send the completion event on. This should
46312 * be the NQ ID returned from the `nq_alloc` HWRM command.
46314 uint16_t cmpl_ring;
46316 * The sequence ID is used by the driver for tracking multiple
46317 * commands. This ID is treated as opaque data by the firmware and
46318 * the value is returned in the `hwrm_resp_hdr` upon completion.
46322 * The target ID of the command:
46323 * * 0x0-0xFFF8 - The function ID
46324 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
46325 * * 0xFFFD - Reserved for user-space HWRM interface
46328 uint16_t target_id;
46330 * A physical address pointer pointing to a host buffer that the
46331 * command's response data will be written. This can be either a host
46332 * physical address (HPA) or a guest physical address (GPA) and must
46333 * point to a physically contiguous block of memory.
46335 uint64_t resp_addr;
46336 /* Firmware session id returned when HWRM_TF_SESSION_OPEN is sent. */
46337 uint32_t fw_session_id;
46339 uint8_t unused0[4];
46342 /* hwrm_tf_session_qcfg_output (size:128b/16B) */
46343 struct hwrm_tf_session_qcfg_output {
46344 /* The specific error status for the command. */
46345 uint16_t error_code;
46346 /* The HWRM command request type. */
46348 /* The sequence ID from the original command. */
46350 /* The length of the response data in number of bytes. */
46352 /* RX action control settings flags. */
46353 uint8_t rx_act_flags;
46355 * A value of 1 in this field indicates that Global Flow ID
46356 * reporting into cfa_code and cfa_metadata is enabled.
46358 #define HWRM_TF_SESSION_QCFG_OUTPUT_RX_ACT_FLAGS_ABCR_GFID_EN \
46361 * A value of 1 in this field indicates that both inner and outer
46362 * are stripped and inner tag is passed.
46365 #define HWRM_TF_SESSION_QCFG_OUTPUT_RX_ACT_FLAGS_ABCR_VTAG_DLT_BOTH \
46368 * A value of 1 in this field indicates that the re-use of
46369 * existing tunnel L2 header SMAC is enabled for
46370 * Non-tunnel L2, L2-L3 and IP-IP tunnel.
46372 #define HWRM_TF_SESSION_QCFG_OUTPUT_RX_ACT_FLAGS_TECT_SMAC_OVR_RUTNSL2 \
46374 /* TX Action control settings flags. */
46375 uint8_t tx_act_flags;
46377 #define HWRM_TF_SESSION_QCFG_OUTPUT_TX_ACT_FLAGS_ABCR_VEB_EN \
46380 * When set to 1 any GRE tunnels will include the
46381 * optional Key field.
46383 #define HWRM_TF_SESSION_QCFG_OUTPUT_TX_ACT_FLAGS_TECT_GRE_SET_K \
46386 * When set to 1, for GRE tunnels, the IPV6 Traffic Class (TC)
46387 * field of the outer header is inherited from the inner header
46388 * (if present) or the fixed value as taken from the encap
46391 #define HWRM_TF_SESSION_QCFG_OUTPUT_TX_ACT_FLAGS_TECT_IPV6_TC_IH \
46394 * When set to 1, for GRE tunnels, the IPV4 Type Of Service (TOS)
46395 * field of the outer header is inherited from the inner header
46396 * (if present) or the fixed value as taken from the encap record.
46398 #define HWRM_TF_SESSION_QCFG_OUTPUT_TX_ACT_FLAGS_TECT_IPV4_TOS_IH \
46401 uint8_t unused0[5];
46403 * This field is used in Output records to indicate that the output
46404 * is completely written to RAM. This field should be read as '1'
46405 * to indicate that the output has been completely written.
46406 * When writing a command completion or response to an internal
46407 * processor, the order of writes has to be such that this field
46413 /******************************
46414 * hwrm_tf_session_resc_qcaps *
46415 ******************************/
46418 /* hwrm_tf_session_resc_qcaps_input (size:256b/32B) */
46419 struct hwrm_tf_session_resc_qcaps_input {
46420 /* The HWRM command request type. */
46423 * The completion ring to send the completion event on. This should
46424 * be the NQ ID returned from the `nq_alloc` HWRM command.
46426 uint16_t cmpl_ring;
46428 * The sequence ID is used by the driver for tracking multiple
46429 * commands. This ID is treated as opaque data by the firmware and
46430 * the value is returned in the `hwrm_resp_hdr` upon completion.
46434 * The target ID of the command:
46435 * * 0x0-0xFFF8 - The function ID
46436 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
46437 * * 0xFFFD - Reserved for user-space HWRM interface
46440 uint16_t target_id;
46442 * A physical address pointer pointing to a host buffer that the
46443 * command's response data will be written. This can be either a host
46444 * physical address (HPA) or a guest physical address (GPA) and must
46445 * point to a physically contiguous block of memory.
46447 uint64_t resp_addr;
46448 /* Firmware session id returned when HWRM_TF_SESSION_OPEN is sent. */
46449 uint32_t fw_session_id;
46450 /* Control flags. */
46452 /* Indicates the flow direction. */
46453 #define HWRM_TF_SESSION_RESC_QCAPS_INPUT_FLAGS_DIR UINT32_C(0x1)
46454 /* If this bit set to 0, then it indicates rx flow. */
46455 #define HWRM_TF_SESSION_RESC_QCAPS_INPUT_FLAGS_DIR_RX UINT32_C(0x0)
46456 /* If this bit is set to 1, then it indicates tx flow. */
46457 #define HWRM_TF_SESSION_RESC_QCAPS_INPUT_FLAGS_DIR_TX UINT32_C(0x1)
46458 #define HWRM_TF_SESSION_RESC_QCAPS_INPUT_FLAGS_DIR_LAST \
46459 HWRM_TF_SESSION_RESC_QCAPS_INPUT_FLAGS_DIR_TX
46461 * Defines the size of the provided qcaps_addr array
46462 * buffer. The size should be set to the Resource Manager
46463 * provided max number of qcaps entries which is device
46464 * specific. Resource Manager gets the max size from HCAPI
46467 uint16_t qcaps_size;
46469 * This is the DMA address for the qcaps output data array
46470 * buffer. Array is of tf_rm_resc_req_entry type and is
46473 uint64_t qcaps_addr;
46476 /* hwrm_tf_session_resc_qcaps_output (size:192b/24B) */
46477 struct hwrm_tf_session_resc_qcaps_output {
46478 /* The specific error status for the command. */
46479 uint16_t error_code;
46480 /* The HWRM command request type. */
46482 /* The sequence ID from the original command. */
46484 /* The length of the response data in number of bytes. */
46486 /* Control flags. */
46488 /* Session reservation strategy. */
46489 #define HWRM_TF_SESSION_RESC_QCAPS_OUTPUT_FLAGS_SESS_RESV_STRATEGY_MASK \
46491 #define HWRM_TF_SESSION_RESC_QCAPS_OUTPUT_FLAGS_SESS_RESV_STRATEGY_SFT \
46493 /* Static partitioning. */
46494 #define HWRM_TF_SESSION_RESC_QCAPS_OUTPUT_FLAGS_SESS_RESV_STRATEGY_STATIC \
46497 #define HWRM_TF_SESSION_RESC_QCAPS_OUTPUT_FLAGS_SESS_RESV_STRATEGY_1 \
46500 #define HWRM_TF_SESSION_RESC_QCAPS_OUTPUT_FLAGS_SESS_RESV_STRATEGY_2 \
46503 #define HWRM_TF_SESSION_RESC_QCAPS_OUTPUT_FLAGS_SESS_RESV_STRATEGY_3 \
46505 #define HWRM_TF_SESSION_RESC_QCAPS_OUTPUT_FLAGS_SESS_RESV_STRATEGY_LAST \
46506 HWRM_TF_SESSION_RESC_QCAPS_OUTPUT_FLAGS_SESS_RESV_STRATEGY_3
46508 * Size of the returned qcaps_addr data array buffer. The
46509 * value cannot exceed the size defined by the input msg,
46514 * SRAM profile number that sets the partition of SRAM memory
46515 * between TF and AFM within the 4 internal memory banks (Thor).
46517 uint8_t sram_profile;
46521 uint8_t unused1[7];
46523 * This field is used in Output records to indicate that the output
46524 * is completely written to RAM. This field should be read as '1'
46525 * to indicate that the output has been completely written.
46526 * When writing a command completion or response to an internal
46527 * processor, the order of writes has to be such that this field is
46533 /******************************
46534 * hwrm_tf_session_resc_alloc *
46535 ******************************/
46538 /* hwrm_tf_session_resc_alloc_input (size:320b/40B) */
46539 struct hwrm_tf_session_resc_alloc_input {
46540 /* The HWRM command request type. */
46543 * The completion ring to send the completion event on. This should
46544 * be the NQ ID returned from the `nq_alloc` HWRM command.
46546 uint16_t cmpl_ring;
46548 * The sequence ID is used by the driver for tracking multiple
46549 * commands. This ID is treated as opaque data by the firmware and
46550 * the value is returned in the `hwrm_resp_hdr` upon completion.
46554 * The target ID of the command:
46555 * * 0x0-0xFFF8 - The function ID
46556 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
46557 * * 0xFFFD - Reserved for user-space HWRM interface
46560 uint16_t target_id;
46562 * A physical address pointer pointing to a host buffer that the
46563 * command's response data will be written. This can be either a host
46564 * physical address (HPA) or a guest physical address (GPA) and must
46565 * point to a physically contiguous block of memory.
46567 uint64_t resp_addr;
46568 /* Firmware session id returned when HWRM_TF_SESSION_OPEN is sent. */
46569 uint32_t fw_session_id;
46570 /* Control flags. */
46572 /* Indicates the flow direction. */
46573 #define HWRM_TF_SESSION_RESC_ALLOC_INPUT_FLAGS_DIR UINT32_C(0x1)
46574 /* If this bit set to 0, then it indicates rx flow. */
46575 #define HWRM_TF_SESSION_RESC_ALLOC_INPUT_FLAGS_DIR_RX UINT32_C(0x0)
46576 /* If this bit is set to 1, then it indicates tx flow. */
46577 #define HWRM_TF_SESSION_RESC_ALLOC_INPUT_FLAGS_DIR_TX UINT32_C(0x1)
46578 #define HWRM_TF_SESSION_RESC_ALLOC_INPUT_FLAGS_DIR_LAST \
46579 HWRM_TF_SESSION_RESC_ALLOC_INPUT_FLAGS_DIR_TX
46581 * Defines the array size of the provided req_addr and
46582 * resv_addr array buffers. Should be set to the number of
46587 * This is the DMA address for the request input data array
46588 * buffer. Array is of tf_rm_resc_req_entry type. Size of the
46589 * array buffer is provided by the 'req_size' field in this
46594 * This is the DMA address for the resc output data array
46595 * buffer. Array is of tf_rm_resc_entry type. Size of the array
46596 * buffer is provided by the 'req_size' field in this
46599 uint64_t resc_addr;
46602 /* hwrm_tf_session_resc_alloc_output (size:128b/16B) */
46603 struct hwrm_tf_session_resc_alloc_output {
46604 /* The specific error status for the command. */
46605 uint16_t error_code;
46606 /* The HWRM command request type. */
46608 /* The sequence ID from the original command. */
46610 /* The length of the response data in number of bytes. */
46613 * Size of the returned tf_rm_resc_entry data array. The value
46614 * cannot exceed the req_size defined by the input msg. The data
46615 * array is returned using the resv_addr specified DMA
46616 * address also provided by the input msg.
46620 uint8_t unused0[5];
46622 * This field is used in Output records to indicate that the output
46623 * is completely written to RAM. This field should be read as '1'
46624 * to indicate that the output has been completely written.
46625 * When writing a command completion or response to an internal
46626 * processor, the order of writes has to be such that this field is
46632 /*****************************
46633 * hwrm_tf_session_resc_free *
46634 *****************************/
46637 /* hwrm_tf_session_resc_free_input (size:256b/32B) */
46638 struct hwrm_tf_session_resc_free_input {
46639 /* The HWRM command request type. */
46642 * The completion ring to send the completion event on. This should
46643 * be the NQ ID returned from the `nq_alloc` HWRM command.
46645 uint16_t cmpl_ring;
46647 * The sequence ID is used by the driver for tracking multiple
46648 * commands. This ID is treated as opaque data by the firmware and
46649 * the value is returned in the `hwrm_resp_hdr` upon completion.
46653 * The target ID of the command:
46654 * * 0x0-0xFFF8 - The function ID
46655 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
46656 * * 0xFFFD - Reserved for user-space HWRM interface
46659 uint16_t target_id;
46661 * A physical address pointer pointing to a host buffer that the
46662 * command's response data will be written. This can be either a host
46663 * physical address (HPA) or a guest physical address (GPA) and must
46664 * point to a physically contiguous block of memory.
46666 uint64_t resp_addr;
46667 /* Firmware session id returned when HWRM_TF_SESSION_OPEN is sent. */
46668 uint32_t fw_session_id;
46669 /* Control flags. */
46671 /* Indicates the flow direction. */
46672 #define HWRM_TF_SESSION_RESC_FREE_INPUT_FLAGS_DIR UINT32_C(0x1)
46673 /* If this bit set to 0, then it indicates rx flow. */
46674 #define HWRM_TF_SESSION_RESC_FREE_INPUT_FLAGS_DIR_RX UINT32_C(0x0)
46675 /* If this bit is set to 1, then it indicates tx flow. */
46676 #define HWRM_TF_SESSION_RESC_FREE_INPUT_FLAGS_DIR_TX UINT32_C(0x1)
46677 #define HWRM_TF_SESSION_RESC_FREE_INPUT_FLAGS_DIR_LAST \
46678 HWRM_TF_SESSION_RESC_FREE_INPUT_FLAGS_DIR_TX
46680 * Defines the size, in bytes, of the provided free_addr
46683 uint16_t free_size;
46685 * This is the DMA address for the free input data array
46686 * buffer. Array is of tf_rm_resc_entry type. Size of the
46687 * buffer is provided by the 'free_size' field of this
46690 uint64_t free_addr;
46693 /* hwrm_tf_session_resc_free_output (size:128b/16B) */
46694 struct hwrm_tf_session_resc_free_output {
46695 /* The specific error status for the command. */
46696 uint16_t error_code;
46697 /* The HWRM command request type. */
46699 /* The sequence ID from the original command. */
46701 /* The length of the response data in number of bytes. */
46704 uint8_t unused0[7];
46706 * This field is used in Output records to indicate that the output
46707 * is completely written to RAM. This field should be read as '1'
46708 * to indicate that the output has been completely written.
46709 * When writing a command completion or response to an internal
46710 * processor, the order of writes has to be such that this field is
46716 /******************************
46717 * hwrm_tf_session_resc_flush *
46718 ******************************/
46721 /* hwrm_tf_session_resc_flush_input (size:256b/32B) */
46722 struct hwrm_tf_session_resc_flush_input {
46723 /* The HWRM command request type. */
46726 * The completion ring to send the completion event on. This should
46727 * be the NQ ID returned from the `nq_alloc` HWRM command.
46729 uint16_t cmpl_ring;
46731 * The sequence ID is used by the driver for tracking multiple
46732 * commands. This ID is treated as opaque data by the firmware and
46733 * the value is returned in the `hwrm_resp_hdr` upon completion.
46737 * The target ID of the command:
46738 * * 0x0-0xFFF8 - The function ID
46739 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
46740 * * 0xFFFD - Reserved for user-space HWRM interface
46743 uint16_t target_id;
46745 * A physical address pointer pointing to a host buffer that the
46746 * command's response data will be written. This can be either a host
46747 * physical address (HPA) or a guest physical address (GPA) and must
46748 * point to a physically contiguous block of memory.
46750 uint64_t resp_addr;
46751 /* Firmware session id returned when HWRM_TF_SESSION_OPEN is sent. */
46752 uint32_t fw_session_id;
46753 /* Control flags. */
46755 /* Indicates the flow direction. */
46756 #define HWRM_TF_SESSION_RESC_FLUSH_INPUT_FLAGS_DIR UINT32_C(0x1)
46757 /* If this bit set to 0, then it indicates rx flow. */
46758 #define HWRM_TF_SESSION_RESC_FLUSH_INPUT_FLAGS_DIR_RX UINT32_C(0x0)
46759 /* If this bit is set to 1, then it indicates tx flow. */
46760 #define HWRM_TF_SESSION_RESC_FLUSH_INPUT_FLAGS_DIR_TX UINT32_C(0x1)
46761 #define HWRM_TF_SESSION_RESC_FLUSH_INPUT_FLAGS_DIR_LAST \
46762 HWRM_TF_SESSION_RESC_FLUSH_INPUT_FLAGS_DIR_TX
46764 * Defines the size, in bytes, of the provided flush_addr
46767 uint16_t flush_size;
46769 * This is the DMA address for the flush input data array
46770 * buffer. Array of tf_rm_resc_entry type. Size of the
46771 * buffer is provided by the 'flush_size' field in this
46774 uint64_t flush_addr;
46777 /* hwrm_tf_session_resc_flush_output (size:128b/16B) */
46778 struct hwrm_tf_session_resc_flush_output {
46779 /* The specific error status for the command. */
46780 uint16_t error_code;
46781 /* The HWRM command request type. */
46783 /* The sequence ID from the original command. */
46785 /* The length of the response data in number of bytes. */
46788 uint8_t unused0[7];
46790 * This field is used in Output records to indicate that the output
46791 * is completely written to RAM. This field should be read as '1'
46792 * to indicate that the output has been completely written.
46793 * When writing a command completion or response to an internal
46794 * processor, the order of writes has to be such that this field is
46800 /*****************************
46801 * hwrm_tf_session_resc_info *
46802 *****************************/
46805 /* hwrm_tf_session_resc_info_input (size:320b/40B) */
46806 struct hwrm_tf_session_resc_info_input {
46807 /* The HWRM command request type. */
46810 * The completion ring to send the completion event on. This should
46811 * be the NQ ID returned from the `nq_alloc` HWRM command.
46813 uint16_t cmpl_ring;
46815 * The sequence ID is used by the driver for tracking multiple
46816 * commands. This ID is treated as opaque data by the firmware and
46817 * the value is returned in the `hwrm_resp_hdr` upon completion.
46821 * The target ID of the command:
46822 * * 0x0-0xFFF8 - The function ID
46823 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
46824 * * 0xFFFD - Reserved for user-space HWRM interface
46827 uint16_t target_id;
46829 * A physical address pointer pointing to a host buffer that the
46830 * command's response data will be written. This can be either a host
46831 * physical address (HPA) or a guest physical address (GPA) and must
46832 * point to a physically contiguous block of memory.
46834 uint64_t resp_addr;
46835 /* Firmware session id returned when HWRM_TF_SESSION_OPEN is sent. */
46836 uint32_t fw_session_id;
46837 /* Control flags. */
46839 /* Indicates the flow direction. */
46840 #define HWRM_TF_SESSION_RESC_INFO_INPUT_FLAGS_DIR UINT32_C(0x1)
46841 /* If this bit set to 0, then it indicates rx flow. */
46842 #define HWRM_TF_SESSION_RESC_INFO_INPUT_FLAGS_DIR_RX UINT32_C(0x0)
46843 /* If this bit is set to 1, then it indicates tx flow. */
46844 #define HWRM_TF_SESSION_RESC_INFO_INPUT_FLAGS_DIR_TX UINT32_C(0x1)
46845 #define HWRM_TF_SESSION_RESC_INFO_INPUT_FLAGS_DIR_LAST \
46846 HWRM_TF_SESSION_RESC_INFO_INPUT_FLAGS_DIR_TX
46848 * Defines the array size of the provided req_addr and
46849 * resv_addr array buffers. Should be set to the number of
46854 * This is the DMA address for the request input data array
46855 * buffer. Array is of tf_rm_resc_req_entry type. Size of the
46856 * array buffer is provided by the 'req_size' field in this
46861 * This is the DMA address for the resc output data array
46862 * buffer. Array is of tf_rm_resc_entry type. Size of the array
46863 * buffer is provided by the 'req_size' field in this
46866 uint64_t resc_addr;
46869 /* hwrm_tf_session_resc_info_output (size:128b/16B) */
46870 struct hwrm_tf_session_resc_info_output {
46871 /* The specific error status for the command. */
46872 uint16_t error_code;
46873 /* The HWRM command request type. */
46875 /* The sequence ID from the original command. */
46877 /* The length of the response data in number of bytes. */
46880 * Size of the returned tf_rm_resc_entry data array. The value
46881 * cannot exceed the req_size defined by the input msg. The data
46882 * array is returned using the resv_addr specified DMA
46883 * address also provided by the input msg.
46887 uint8_t unused0[5];
46889 * This field is used in Output records to indicate that the output
46890 * is completely written to RAM. This field should be read as '1'
46891 * to indicate that the output has been completely written.
46892 * When writing a command completion or response to an internal
46893 * processor, the order of writes has to be such that this field is
46899 /* TruFlow RM capability of a resource. */
46900 /* tf_rm_resc_req_entry (size:64b/8B) */
46901 struct tf_rm_resc_req_entry {
46902 /* Type of the resource, defined globally in HCAPI RM. */
46904 /* Minimum value. */
46906 /* Maximum value. */
46910 /* TruFlow RM reservation information. */
46911 /* tf_rm_resc_entry (size:64b/8B) */
46912 struct tf_rm_resc_entry {
46913 /* Type of the resource, defined globally in HCAPI RM. */
46915 /* Start offset. */
46917 /* Number of resources. */
46921 /************************
46922 * hwrm_tf_tbl_type_get *
46923 ************************/
46926 /* hwrm_tf_tbl_type_get_input (size:256b/32B) */
46927 struct hwrm_tf_tbl_type_get_input {
46928 /* The HWRM command request type. */
46931 * The completion ring to send the completion event on. This should
46932 * be the NQ ID returned from the `nq_alloc` HWRM command.
46934 uint16_t cmpl_ring;
46936 * The sequence ID is used by the driver for tracking multiple
46937 * commands. This ID is treated as opaque data by the firmware and
46938 * the value is returned in the `hwrm_resp_hdr` upon completion.
46942 * The target ID of the command:
46943 * * 0x0-0xFFF8 - The function ID
46944 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
46945 * * 0xFFFD - Reserved for user-space HWRM interface
46948 uint16_t target_id;
46950 * A physical address pointer pointing to a host buffer that the
46951 * command's response data will be written. This can be either a host
46952 * physical address (HPA) or a guest physical address (GPA) and must
46953 * point to a physically contiguous block of memory.
46955 uint64_t resp_addr;
46956 /* Firmware session id returned when HWRM_TF_SESSION_OPEN is sent. */
46957 uint32_t fw_session_id;
46958 /* Control flags. */
46960 /* Indicates the flow direction. */
46961 #define HWRM_TF_TBL_TYPE_GET_INPUT_FLAGS_DIR \
46963 /* If this bit set to 0, then it indicates rx flow. */
46964 #define HWRM_TF_TBL_TYPE_GET_INPUT_FLAGS_DIR_RX \
46966 /* If this bit is set to 1, then it indicates tx flow. */
46967 #define HWRM_TF_TBL_TYPE_GET_INPUT_FLAGS_DIR_TX \
46969 #define HWRM_TF_TBL_TYPE_GET_INPUT_FLAGS_DIR_LAST \
46970 HWRM_TF_TBL_TYPE_GET_INPUT_FLAGS_DIR_TX
46972 * When set use the special access register access to clear
46973 * the table entry on read.
46975 #define HWRM_TF_TBL_TYPE_GET_INPUT_FLAGS_CLEAR_ON_READ \
46978 uint8_t unused0[2];
46980 * Type of the resource, defined globally in the
46981 * hwrm_tf_resc_type enum.
46984 /* Index of the type to retrieve. */
46988 /* hwrm_tf_tbl_type_get_output (size:1216b/152B) */
46989 struct hwrm_tf_tbl_type_get_output {
46990 /* The specific error status for the command. */
46991 uint16_t error_code;
46992 /* The HWRM command request type. */
46994 /* The sequence ID from the original command. */
46996 /* The length of the response data in number of bytes. */
46998 /* Response code. */
46999 uint32_t resp_code;
47000 /* Response size. */
47004 /* Response data. */
47007 uint8_t unused1[7];
47009 * This field is used in Output records to indicate that the output
47010 * is completely written to RAM. This field should be read as '1'
47011 * to indicate that the output has been completely written.
47012 * When writing a command completion or response to an internal
47013 * processor, the order of writes has to be such that this field
47019 /************************
47020 * hwrm_tf_tbl_type_set *
47021 ************************/
47024 /* hwrm_tf_tbl_type_set_input (size:1024b/128B) */
47025 struct hwrm_tf_tbl_type_set_input {
47026 /* The HWRM command request type. */
47029 * The completion ring to send the completion event on. This should
47030 * be the NQ ID returned from the `nq_alloc` HWRM command.
47032 uint16_t cmpl_ring;
47034 * The sequence ID is used by the driver for tracking multiple
47035 * commands. This ID is treated as opaque data by the firmware and
47036 * the value is returned in the `hwrm_resp_hdr` upon completion.
47040 * The target ID of the command:
47041 * * 0x0-0xFFF8 - The function ID
47042 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
47043 * * 0xFFFD - Reserved for user-space HWRM interface
47046 uint16_t target_id;
47048 * A physical address pointer pointing to a host buffer that the
47049 * command's response data will be written. This can be either a host
47050 * physical address (HPA) or a guest physical address (GPA) and must
47051 * point to a physically contiguous block of memory.
47053 uint64_t resp_addr;
47054 /* Firmware session id returned when HWRM_TF_SESSION_OPEN is sent. */
47055 uint32_t fw_session_id;
47056 /* Control flags. */
47058 /* Indicates the flow direction. */
47059 #define HWRM_TF_TBL_TYPE_SET_INPUT_FLAGS_DIR UINT32_C(0x1)
47060 /* If this bit set to 0, then it indicates rx flow. */
47061 #define HWRM_TF_TBL_TYPE_SET_INPUT_FLAGS_DIR_RX UINT32_C(0x0)
47062 /* If this bit is set to 1, then it indicates tx flow. */
47063 #define HWRM_TF_TBL_TYPE_SET_INPUT_FLAGS_DIR_TX UINT32_C(0x1)
47064 #define HWRM_TF_TBL_TYPE_SET_INPUT_FLAGS_DIR_LAST \
47065 HWRM_TF_TBL_TYPE_SET_INPUT_FLAGS_DIR_TX
47067 uint8_t unused0[2];
47069 * Type of the resource, defined globally in the
47070 * hwrm_tf_resc_type enum.
47073 /* Index of the type to retrieve. */
47075 /* Size of the data to set. */
47078 uint8_t unused1[6];
47079 /* Data to be set. */
47083 /* hwrm_tf_tbl_type_set_output (size:128b/16B) */
47084 struct hwrm_tf_tbl_type_set_output {
47085 /* The specific error status for the command. */
47086 uint16_t error_code;
47087 /* The HWRM command request type. */
47089 /* The sequence ID from the original command. */
47091 /* The length of the response data in number of bytes. */
47094 uint8_t unused0[7];
47096 * This field is used in Output records to indicate that the output
47097 * is completely written to RAM. This field should be read as '1'
47098 * to indicate that the output has been completely written.
47099 * When writing a command completion or response to an internal
47100 * processor, the order of writes has to be such that this field
47106 /**************************
47107 * hwrm_tf_ctxt_mem_alloc *
47108 **************************/
47111 /* hwrm_tf_ctxt_mem_alloc_input (size:192b/24B) */
47112 struct hwrm_tf_ctxt_mem_alloc_input {
47113 /* The HWRM command request type. */
47116 * The completion ring to send the completion event on. This should
47117 * be the NQ ID returned from the `nq_alloc` HWRM command.
47119 uint16_t cmpl_ring;
47121 * The sequence ID is used by the driver for tracking multiple
47122 * commands. This ID is treated as opaque data by the firmware and
47123 * the value is returned in the `hwrm_resp_hdr` upon completion.
47127 * The target ID of the command:
47128 * * 0x0-0xFFF8 - The function ID
47129 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
47130 * * 0xFFFD - Reserved for user-space HWRM interface
47133 uint16_t target_id;
47135 * A physical address pointer pointing to a host buffer that the
47136 * command's response data will be written. This can be either a host
47137 * physical address (HPA) or a guest physical address (GPA) and must
47138 * point to a physically contiguous block of memory.
47140 uint64_t resp_addr;
47141 /* Size in KB of memory to be allocated. */
47143 /* Firmware session id returned when HWRM_TF_SESSION_OPEN is sent. */
47144 uint32_t fw_session_id;
47147 /* hwrm_tf_ctxt_mem_alloc_output (size:192b/24B) */
47148 struct hwrm_tf_ctxt_mem_alloc_output {
47149 /* The specific error status for the command. */
47150 uint16_t error_code;
47151 /* The HWRM command request type. */
47153 /* The sequence ID from the original command. */
47155 /* The length of the response data in number of bytes. */
47157 /* Pointer to the PBL, or PDL depending on number of levels */
47159 /* Size of memory allocated. */
47161 /* Counter PBL indirect levels. */
47162 uint8_t page_level;
47163 /* PBL pointer is physical start address. */
47164 #define HWRM_TF_CTXT_MEM_ALLOC_OUTPUT_PAGE_LEVEL_LVL_0 UINT32_C(0x0)
47165 /* PBL pointer points to PTE table. */
47166 #define HWRM_TF_CTXT_MEM_ALLOC_OUTPUT_PAGE_LEVEL_LVL_1 UINT32_C(0x1)
47168 * PBL pointer points to PDE table with each entry pointing
47171 #define HWRM_TF_CTXT_MEM_ALLOC_OUTPUT_PAGE_LEVEL_LVL_2 UINT32_C(0x2)
47172 #define HWRM_TF_CTXT_MEM_ALLOC_OUTPUT_PAGE_LEVEL_LAST \
47173 HWRM_TF_CTXT_MEM_ALLOC_OUTPUT_PAGE_LEVEL_LVL_2
47176 /* 4KB page size. */
47177 #define HWRM_TF_CTXT_MEM_ALLOC_OUTPUT_PAGE_SIZE_4K UINT32_C(0x0)
47178 /* 8KB page size. */
47179 #define HWRM_TF_CTXT_MEM_ALLOC_OUTPUT_PAGE_SIZE_8K UINT32_C(0x1)
47180 /* 64KB page size. */
47181 #define HWRM_TF_CTXT_MEM_ALLOC_OUTPUT_PAGE_SIZE_64K UINT32_C(0x4)
47182 /* 128KB page size. */
47183 #define HWRM_TF_CTXT_MEM_ALLOC_OUTPUT_PAGE_SIZE_128K UINT32_C(0x5)
47184 /* 256KB page size. */
47185 #define HWRM_TF_CTXT_MEM_ALLOC_OUTPUT_PAGE_SIZE_256K UINT32_C(0x6)
47186 /* 512KB page size. */
47187 #define HWRM_TF_CTXT_MEM_ALLOC_OUTPUT_PAGE_SIZE_512K UINT32_C(0x7)
47188 /* 1MB page size. */
47189 #define HWRM_TF_CTXT_MEM_ALLOC_OUTPUT_PAGE_SIZE_1M UINT32_C(0x8)
47190 /* 2MB page size. */
47191 #define HWRM_TF_CTXT_MEM_ALLOC_OUTPUT_PAGE_SIZE_2M UINT32_C(0x9)
47192 /* 4MB page size. */
47193 #define HWRM_TF_CTXT_MEM_ALLOC_OUTPUT_PAGE_SIZE_4M UINT32_C(0xa)
47194 /* 8MB page size. */
47195 #define HWRM_TF_CTXT_MEM_ALLOC_OUTPUT_PAGE_SIZE_8M UINT32_C(0xb)
47196 /* 1GB page size. */
47197 #define HWRM_TF_CTXT_MEM_ALLOC_OUTPUT_PAGE_SIZE_1G UINT32_C(0x12)
47198 #define HWRM_TF_CTXT_MEM_ALLOC_OUTPUT_PAGE_SIZE_LAST \
47199 HWRM_TF_CTXT_MEM_ALLOC_OUTPUT_PAGE_SIZE_1G
47203 * This field is used in Output records to indicate that the
47204 * output is completely written to RAM. This field should be
47205 * read as '1' to indicate that the output has been
47206 * completely written. When writing a command completion or
47207 * response to an internal processor, the order of writes has
47208 * to be such that this field is written last.
47213 /*************************
47214 * hwrm_tf_ctxt_mem_free *
47215 *************************/
47218 /* hwrm_tf_ctxt_mem_free_input (size:320b/40B) */
47219 struct hwrm_tf_ctxt_mem_free_input {
47220 /* The HWRM command request type. */
47223 * The completion ring to send the completion event on. This should
47224 * be the NQ ID returned from the `nq_alloc` HWRM command.
47226 uint16_t cmpl_ring;
47228 * The sequence ID is used by the driver for tracking multiple
47229 * commands. This ID is treated as opaque data by the firmware and
47230 * the value is returned in the `hwrm_resp_hdr` upon completion.
47234 * The target ID of the command:
47235 * * 0x0-0xFFF8 - The function ID
47236 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
47237 * * 0xFFFD - Reserved for user-space HWRM interface
47240 uint16_t target_id;
47242 * A physical address pointer pointing to a host buffer that the
47243 * command's response data will be written. This can be either a host
47244 * physical address (HPA) or a guest physical address (GPA) and must
47245 * point to a physically contiguous block of memory.
47247 uint64_t resp_addr;
47248 /* Firmware session id returned when HWRM_TF_SESSION_OPEN is sent. */
47249 uint32_t fw_session_id;
47250 /* Counter PBL indirect levels. */
47251 uint8_t page_level;
47252 /* PBL pointer is physical start address. */
47253 #define HWRM_TF_CTXT_MEM_FREE_INPUT_PAGE_LEVEL_LVL_0 UINT32_C(0x0)
47254 /* PBL pointer points to PTE table. */
47255 #define HWRM_TF_CTXT_MEM_FREE_INPUT_PAGE_LEVEL_LVL_1 UINT32_C(0x1)
47257 * PBL pointer points to PDE table with each entry pointing
47260 #define HWRM_TF_CTXT_MEM_FREE_INPUT_PAGE_LEVEL_LVL_2 UINT32_C(0x2)
47261 #define HWRM_TF_CTXT_MEM_FREE_INPUT_PAGE_LEVEL_LAST \
47262 HWRM_TF_CTXT_MEM_FREE_INPUT_PAGE_LEVEL_LVL_2
47265 /* 4KB page size. */
47266 #define HWRM_TF_CTXT_MEM_FREE_INPUT_PAGE_SIZE_4K UINT32_C(0x0)
47267 /* 8KB page size. */
47268 #define HWRM_TF_CTXT_MEM_FREE_INPUT_PAGE_SIZE_8K UINT32_C(0x1)
47269 /* 64KB page size. */
47270 #define HWRM_TF_CTXT_MEM_FREE_INPUT_PAGE_SIZE_64K UINT32_C(0x4)
47271 /* 128KB page size. */
47272 #define HWRM_TF_CTXT_MEM_FREE_INPUT_PAGE_SIZE_128K UINT32_C(0x5)
47273 /* 256KB page size. */
47274 #define HWRM_TF_CTXT_MEM_FREE_INPUT_PAGE_SIZE_256K UINT32_C(0x6)
47275 /* 512KB page size. */
47276 #define HWRM_TF_CTXT_MEM_FREE_INPUT_PAGE_SIZE_512K UINT32_C(0x7)
47277 /* 1MB page size. */
47278 #define HWRM_TF_CTXT_MEM_FREE_INPUT_PAGE_SIZE_1M UINT32_C(0x8)
47279 /* 2MB page size. */
47280 #define HWRM_TF_CTXT_MEM_FREE_INPUT_PAGE_SIZE_2M UINT32_C(0x9)
47281 /* 4MB page size. */
47282 #define HWRM_TF_CTXT_MEM_FREE_INPUT_PAGE_SIZE_4M UINT32_C(0xa)
47283 /* 8MB page size. */
47284 #define HWRM_TF_CTXT_MEM_FREE_INPUT_PAGE_SIZE_8M UINT32_C(0xb)
47285 /* 1GB page size. */
47286 #define HWRM_TF_CTXT_MEM_FREE_INPUT_PAGE_SIZE_1G UINT32_C(0x12)
47287 #define HWRM_TF_CTXT_MEM_FREE_INPUT_PAGE_SIZE_LAST \
47288 HWRM_TF_CTXT_MEM_FREE_INPUT_PAGE_SIZE_1G
47290 uint8_t unused0[2];
47291 /* Pointer to the PBL, or PDL depending on number of levels */
47293 /* Size of memory allocated. */
47296 uint8_t unused1[4];
47299 /* hwrm_tf_ctxt_mem_free_output (size:128b/16B) */
47300 struct hwrm_tf_ctxt_mem_free_output {
47301 /* The specific error status for the command. */
47302 uint16_t error_code;
47303 /* The HWRM command request type. */
47305 /* The sequence ID from the original command. */
47307 /* The length of the response data in number of bytes. */
47310 uint8_t unused0[7];
47312 * This field is used in Output records to indicate that the
47313 * output is completely written to RAM. This field should be
47314 * read as '1' to indicate that the output has been
47315 * completely written. When writing a command completion or
47316 * response to an internal processor, the order of writes has
47317 * to be such that this field is written last.
47322 /*************************
47323 * hwrm_tf_ctxt_mem_rgtr *
47324 *************************/
47327 /* hwrm_tf_ctxt_mem_rgtr_input (size:256b/32B) */
47328 struct hwrm_tf_ctxt_mem_rgtr_input {
47329 /* The HWRM command request type. */
47332 * The completion ring to send the completion event on. This should
47333 * be the NQ ID returned from the `nq_alloc` HWRM command.
47335 uint16_t cmpl_ring;
47337 * The sequence ID is used by the driver for tracking multiple
47338 * commands. This ID is treated as opaque data by the firmware and
47339 * the value is returned in the `hwrm_resp_hdr` upon completion.
47343 * The target ID of the command:
47344 * * 0x0-0xFFF8 - The function ID
47345 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
47346 * * 0xFFFD - Reserved for user-space HWRM interface
47349 uint16_t target_id;
47351 * A physical address pointer pointing to a host buffer that the
47352 * command's response data will be written. This can be either a host
47353 * physical address (HPA) or a guest physical address (GPA) and must
47354 * point to a physically contiguous block of memory.
47356 uint64_t resp_addr;
47357 /* Control flags. */
47359 /* Counter PBL indirect levels. */
47360 uint8_t page_level;
47361 /* PBL pointer is physical start address. */
47362 #define HWRM_TF_CTXT_MEM_RGTR_INPUT_PAGE_LEVEL_LVL_0 UINT32_C(0x0)
47363 /* PBL pointer points to PTE table. */
47364 #define HWRM_TF_CTXT_MEM_RGTR_INPUT_PAGE_LEVEL_LVL_1 UINT32_C(0x1)
47366 * PBL pointer points to PDE table with each entry pointing
47369 #define HWRM_TF_CTXT_MEM_RGTR_INPUT_PAGE_LEVEL_LVL_2 UINT32_C(0x2)
47370 #define HWRM_TF_CTXT_MEM_RGTR_INPUT_PAGE_LEVEL_LAST \
47371 HWRM_TF_CTXT_MEM_RGTR_INPUT_PAGE_LEVEL_LVL_2
47374 /* 4KB page size. */
47375 #define HWRM_TF_CTXT_MEM_RGTR_INPUT_PAGE_SIZE_4K UINT32_C(0x0)
47376 /* 8KB page size. */
47377 #define HWRM_TF_CTXT_MEM_RGTR_INPUT_PAGE_SIZE_8K UINT32_C(0x1)
47378 /* 64KB page size. */
47379 #define HWRM_TF_CTXT_MEM_RGTR_INPUT_PAGE_SIZE_64K UINT32_C(0x4)
47380 /* 128KB page size. */
47381 #define HWRM_TF_CTXT_MEM_RGTR_INPUT_PAGE_SIZE_128K UINT32_C(0x5)
47382 /* 256KB page size. */
47383 #define HWRM_TF_CTXT_MEM_RGTR_INPUT_PAGE_SIZE_256K UINT32_C(0x6)
47384 /* 512KB page size. */
47385 #define HWRM_TF_CTXT_MEM_RGTR_INPUT_PAGE_SIZE_512K UINT32_C(0x7)
47386 /* 1MB page size. */
47387 #define HWRM_TF_CTXT_MEM_RGTR_INPUT_PAGE_SIZE_1M UINT32_C(0x8)
47388 /* 2MB page size. */
47389 #define HWRM_TF_CTXT_MEM_RGTR_INPUT_PAGE_SIZE_2M UINT32_C(0x9)
47390 /* 4MB page size. */
47391 #define HWRM_TF_CTXT_MEM_RGTR_INPUT_PAGE_SIZE_4M UINT32_C(0xa)
47392 /* 8MB page size. */
47393 #define HWRM_TF_CTXT_MEM_RGTR_INPUT_PAGE_SIZE_8M UINT32_C(0xb)
47394 /* 1GB page size. */
47395 #define HWRM_TF_CTXT_MEM_RGTR_INPUT_PAGE_SIZE_1G UINT32_C(0x12)
47396 #define HWRM_TF_CTXT_MEM_RGTR_INPUT_PAGE_SIZE_LAST \
47397 HWRM_TF_CTXT_MEM_RGTR_INPUT_PAGE_SIZE_1G
47398 /* Firmware session id returned when HWRM_TF_SESSION_OPEN is sent. */
47399 uint32_t fw_session_id;
47400 /* Pointer to the PBL, or PDL depending on number of levels */
47404 /* hwrm_tf_ctxt_mem_rgtr_output (size:128b/16B) */
47405 struct hwrm_tf_ctxt_mem_rgtr_output {
47406 /* The specific error status for the command. */
47407 uint16_t error_code;
47408 /* The HWRM command request type. */
47410 /* The sequence ID from the original command. */
47412 /* The length of the response data in number of bytes. */
47415 * Id/Handle to the recently register context memory. This
47416 * handle is passed to the TF session.
47420 uint8_t unused0[5];
47422 * This field is used in Output records to indicate that the
47423 * output is completely written to RAM. This field should be
47424 * read as '1' to indicate that the output has been
47425 * completely written. When writing a command completion or
47426 * response to an internal processor, the order of writes has
47427 * to be such that this field is written last.
47432 /***************************
47433 * hwrm_tf_ctxt_mem_unrgtr *
47434 ***************************/
47437 /* hwrm_tf_ctxt_mem_unrgtr_input (size:192b/24B) */
47438 struct hwrm_tf_ctxt_mem_unrgtr_input {
47439 /* The HWRM command request type. */
47442 * The completion ring to send the completion event on. This should
47443 * be the NQ ID returned from the `nq_alloc` HWRM command.
47445 uint16_t cmpl_ring;
47447 * The sequence ID is used by the driver for tracking multiple
47448 * commands. This ID is treated as opaque data by the firmware and
47449 * the value is returned in the `hwrm_resp_hdr` upon completion.
47453 * The target ID of the command:
47454 * * 0x0-0xFFF8 - The function ID
47455 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
47456 * * 0xFFFD - Reserved for user-space HWRM interface
47459 uint16_t target_id;
47461 * A physical address pointer pointing to a host buffer that the
47462 * command's response data will be written. This can be either a host
47463 * physical address (HPA) or a guest physical address (GPA) and must
47464 * point to a physically contiguous block of memory.
47466 uint64_t resp_addr;
47468 * Id/Handle to the recently register context memory. This
47469 * handle is passed to the TF session.
47473 uint8_t unused0[2];
47474 /* Firmware session id returned when HWRM_TF_SESSION_OPEN is sent. */
47475 uint32_t fw_session_id;
47478 /* hwrm_tf_ctxt_mem_unrgtr_output (size:128b/16B) */
47479 struct hwrm_tf_ctxt_mem_unrgtr_output {
47480 /* The specific error status for the command. */
47481 uint16_t error_code;
47482 /* The HWRM command request type. */
47484 /* The sequence ID from the original command. */
47486 /* The length of the response data in number of bytes. */
47489 uint8_t unused0[7];
47491 * This field is used in Output records to indicate that the
47492 * output is completely written to RAM. This field should be
47493 * read as '1' to indicate that the output has been
47494 * completely written. When writing a command completion or
47495 * response to an internal processor, the order of writes has
47496 * to be such that this field is written last.
47501 /************************
47502 * hwrm_tf_ext_em_qcaps *
47503 ************************/
47506 /* hwrm_tf_ext_em_qcaps_input (size:192b/24B) */
47507 struct hwrm_tf_ext_em_qcaps_input {
47508 /* The HWRM command request type. */
47511 * The completion ring to send the completion event on. This should
47512 * be the NQ ID returned from the `nq_alloc` HWRM command.
47514 uint16_t cmpl_ring;
47516 * The sequence ID is used by the driver for tracking multiple
47517 * commands. This ID is treated as opaque data by the firmware and
47518 * the value is returned in the `hwrm_resp_hdr` upon completion.
47522 * The target ID of the command:
47523 * * 0x0-0xFFF8 - The function ID
47524 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
47525 * * 0xFFFD - Reserved for user-space HWRM interface
47528 uint16_t target_id;
47530 * A physical address pointer pointing to a host buffer that the
47531 * command's response data will be written. This can be either a host
47532 * physical address (HPA) or a guest physical address (GPA) and must
47533 * point to a physically contiguous block of memory.
47535 uint64_t resp_addr;
47536 /* Control flags. */
47538 /* Indicates the flow direction. */
47539 #define HWRM_TF_EXT_EM_QCAPS_INPUT_FLAGS_DIR \
47541 /* If this bit set to 0, then it indicates rx flow. */
47542 #define HWRM_TF_EXT_EM_QCAPS_INPUT_FLAGS_DIR_RX \
47544 /* If this bit is set to 1, then it indicates tx flow. */
47545 #define HWRM_TF_EXT_EM_QCAPS_INPUT_FLAGS_DIR_TX \
47547 #define HWRM_TF_EXT_EM_QCAPS_INPUT_FLAGS_DIR_LAST \
47548 HWRM_TF_EXT_EM_QCAPS_INPUT_FLAGS_DIR_TX
47549 /* When set to 1, all offloaded flows will be sent to EXT EM. */
47550 #define HWRM_TF_EXT_EM_QCAPS_INPUT_FLAGS_PREFERRED_OFFLOAD \
47552 /* Firmware session id returned when HWRM_TF_SESSION_OPEN is sent. */
47553 uint32_t fw_session_id;
47556 /* hwrm_tf_ext_em_qcaps_output (size:384b/48B) */
47557 struct hwrm_tf_ext_em_qcaps_output {
47558 /* The specific error status for the command. */
47559 uint16_t error_code;
47560 /* The HWRM command request type. */
47562 /* The sequence ID from the original command. */
47564 /* The length of the response data in number of bytes. */
47568 * When set to 1, indicates the FW supports the Centralized
47569 * Memory Model. The concept designates one entity for the
47570 * memory allocation while all others ‘subscribe’ to it.
47572 #define HWRM_TF_EXT_EM_QCAPS_OUTPUT_FLAGS_CENTRALIZED_MEMORY_MODEL_SUPPORTED \
47575 * When set to 1, indicates the FW supports the Detached
47576 * Centralized Memory Model. The memory is allocated and managed
47577 * as a separate entity. All PFs and VFs will be granted direct
47578 * or semi-direct access to the allocated memory while none of
47579 * which can interfere with the management of the memory.
47581 #define HWRM_TF_EXT_EM_QCAPS_OUTPUT_FLAGS_DETACHED_CENTRALIZED_MEMORY_MODEL_SUPPORTED \
47583 /* When set to 1, indicates FW support for host based EEM memory. */
47584 #define HWRM_TF_EXT_EM_QCAPS_OUTPUT_FLAGS_HOST_MEMORY_SUPPORTED \
47586 /* When set to 1, indicates FW support for on-chip based EEM memory. */
47587 #define HWRM_TF_EXT_EM_QCAPS_OUTPUT_FLAGS_FW_MEMORY_SUPPORTED \
47591 /* Support flags. */
47592 uint32_t supported;
47594 * If set to 1, then EXT EM KEY0 table is supported using
47596 * If set to 0, EXT EM KEY0 table is not supported.
47598 #define HWRM_TF_EXT_EM_QCAPS_OUTPUT_SUPPORTED_KEY0_TABLE \
47601 * If set to 1, then EXT EM KEY1 table is supported using
47603 * If set to 0, EXT EM KEY1 table is not supported.
47605 #define HWRM_TF_EXT_EM_QCAPS_OUTPUT_SUPPORTED_KEY1_TABLE \
47608 * If set to 1, then EXT EM External Record table is supported.
47609 * If set to 0, EXT EM External Record table is not
47610 * supported. (This table includes action record, EFC
47611 * pointers, encap pointers)
47613 #define HWRM_TF_EXT_EM_QCAPS_OUTPUT_SUPPORTED_EXTERNAL_RECORD_TABLE \
47616 * If set to 1, then EXT EM External Flow Counters table is
47618 * If set to 0, EXT EM External Flow Counters table is not
47621 #define HWRM_TF_EXT_EM_QCAPS_OUTPUT_SUPPORTED_EXTERNAL_FLOW_COUNTERS_TABLE \
47624 * If set to 1, then FID table used for implicit flow flush
47626 * If set to 0, then FID table used for implicit flow flush
47627 * is not supported.
47629 #define HWRM_TF_EXT_EM_QCAPS_OUTPUT_SUPPORTED_FID_TABLE \
47632 * If set to 1, then table scopes are supported.
47633 * If set to 0, then table scopes are not supported.
47635 #define HWRM_TF_EXT_EM_QCAPS_OUTPUT_SUPPORTED_TBL_SCOPES \
47638 * The maximum number of entries supported by EXT EM. When
47639 * configuring the host memory the number of numbers of
47640 * entries that can supported are -
47641 * 32k, 64k 128k, 256k, 512k, 1M, 2M, 4M, 8M, 32M, 64M,
47643 * Any value that are not these values, the FW will round
47644 * down to the closest support number of entries.
47646 uint32_t max_entries_supported;
47648 * The entry size in bytes of each entry in the EXT EM
47649 * KEY0/KEY1 tables.
47651 uint16_t key_entry_size;
47653 * The entry size in bytes of each entry in the EXT EM RECORD
47656 uint16_t record_entry_size;
47657 /* The entry size in bytes of each entry in the EXT EM EFC tables. */
47658 uint16_t efc_entry_size;
47659 /* The FID size in bytes of each entry in the EXT EM FID tables. */
47660 uint16_t fid_entry_size;
47661 /* Maximum number of ctxt mem allocations allowed. */
47662 uint32_t max_ctxt_mem_allocs;
47664 * Maximum number of static buckets that can be assigned to lookup
47667 uint32_t max_static_buckets;
47669 uint8_t unused1[7];
47671 * This field is used in Output records to indicate that the
47672 * output is completely written to RAM. This field should be
47673 * read as '1' to indicate that the output has been
47674 * completely written. When writing a command completion or
47675 * response to an internal processor, the order of writes has
47676 * to be such that this field is written last.
47681 /*********************
47682 * hwrm_tf_ext_em_op *
47683 *********************/
47686 /* hwrm_tf_ext_em_op_input (size:256b/32B) */
47687 struct hwrm_tf_ext_em_op_input {
47688 /* The HWRM command request type. */
47691 * The completion ring to send the completion event on. This should
47692 * be the NQ ID returned from the `nq_alloc` HWRM command.
47694 uint16_t cmpl_ring;
47696 * The sequence ID is used by the driver for tracking multiple
47697 * commands. This ID is treated as opaque data by the firmware and
47698 * the value is returned in the `hwrm_resp_hdr` upon completion.
47702 * The target ID of the command:
47703 * * 0x0-0xFFF8 - The function ID
47704 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
47705 * * 0xFFFD - Reserved for user-space HWRM interface
47708 uint16_t target_id;
47710 * A physical address pointer pointing to a host buffer that the
47711 * command's response data will be written. This can be either a host
47712 * physical address (HPA) or a guest physical address (GPA) and must
47713 * point to a physically contiguous block of memory.
47715 uint64_t resp_addr;
47716 /* Control flags. */
47718 /* Indicates the flow direction. */
47719 #define HWRM_TF_EXT_EM_OP_INPUT_FLAGS_DIR UINT32_C(0x1)
47720 /* If this bit set to 0, then it indicates rx flow. */
47721 #define HWRM_TF_EXT_EM_OP_INPUT_FLAGS_DIR_RX UINT32_C(0x0)
47722 /* If this bit is set to 1, then it indicates tx flow. */
47723 #define HWRM_TF_EXT_EM_OP_INPUT_FLAGS_DIR_TX UINT32_C(0x1)
47724 #define HWRM_TF_EXT_EM_OP_INPUT_FLAGS_DIR_LAST \
47725 HWRM_TF_EXT_EM_OP_INPUT_FLAGS_DIR_TX
47728 /* The number of EXT EM key table entries to be configured. */
47730 /* This value is reserved and should not be used. */
47731 #define HWRM_TF_EXT_EM_OP_INPUT_OP_RESERVED UINT32_C(0x0)
47733 * To properly stop EXT EM and ensure there are no DMA's,
47734 * the caller must disable EXT EM for the given PF, using
47735 * this call. This will safely disable EXT EM and ensure
47736 * that all DMA'ed to the keys/records/efc have been
47739 #define HWRM_TF_EXT_EM_OP_INPUT_OP_EXT_EM_DISABLE UINT32_C(0x1)
47741 * Once the EXT EM host memory has been configured, EXT EM
47742 * options have been configured. Then the caller should
47743 * enable EXT EM for the given PF. Note once this call has
47744 * been made, then the EXT EM mechanism will be active and
47745 * DMA's will occur as packets are processed.
47747 #define HWRM_TF_EXT_EM_OP_INPUT_OP_EXT_EM_ENABLE UINT32_C(0x2)
47749 * Clear EXT EM settings for the given PF so that the
47750 * register values are reset back to their initial state.
47752 #define HWRM_TF_EXT_EM_OP_INPUT_OP_EXT_EM_CLEANUP UINT32_C(0x3)
47753 #define HWRM_TF_EXT_EM_OP_INPUT_OP_LAST \
47754 HWRM_TF_EXT_EM_OP_INPUT_OP_EXT_EM_CLEANUP
47757 /* Firmware session id returned when HWRM_TF_SESSION_OPEN is sent. */
47758 uint32_t fw_session_id;
47763 /* hwrm_tf_ext_em_op_output (size:128b/16B) */
47764 struct hwrm_tf_ext_em_op_output {
47765 /* The specific error status for the command. */
47766 uint16_t error_code;
47767 /* The HWRM command request type. */
47769 /* The sequence ID from the original command. */
47771 /* The length of the response data in number of bytes. */
47774 uint8_t unused0[7];
47776 * This field is used in Output records to indicate that the
47777 * output is completely written to RAM. This field should be
47778 * read as '1' to indicate that the output has been
47779 * completely written. When writing a command completion or
47780 * response to an internal processor, the order of writes has
47781 * to be such that this field is written last.
47786 /**********************
47787 * hwrm_tf_ext_em_cfg *
47788 **********************/
47791 /* hwrm_tf_ext_em_cfg_input (size:512b/64B) */
47792 struct hwrm_tf_ext_em_cfg_input {
47793 /* The HWRM command request type. */
47796 * The completion ring to send the completion event on. This should
47797 * be the NQ ID returned from the `nq_alloc` HWRM command.
47799 uint16_t cmpl_ring;
47801 * The sequence ID is used by the driver for tracking multiple
47802 * commands. This ID is treated as opaque data by the firmware and
47803 * the value is returned in the `hwrm_resp_hdr` upon completion.
47807 * The target ID of the command:
47808 * * 0x0-0xFFF8 - The function ID
47809 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
47810 * * 0xFFFD - Reserved for user-space HWRM interface
47813 uint16_t target_id;
47815 * A physical address pointer pointing to a host buffer that the
47816 * command's response data will be written. This can be either a host
47817 * physical address (HPA) or a guest physical address (GPA) and must
47818 * point to a physically contiguous block of memory.
47820 uint64_t resp_addr;
47821 /* Control flags. */
47823 /* Indicates the flow direction. */
47824 #define HWRM_TF_EXT_EM_CFG_INPUT_FLAGS_DIR \
47826 /* If this bit set to 0, then it indicates rx flow. */
47827 #define HWRM_TF_EXT_EM_CFG_INPUT_FLAGS_DIR_RX \
47829 /* If this bit is set to 1, then it indicates tx flow. */
47830 #define HWRM_TF_EXT_EM_CFG_INPUT_FLAGS_DIR_TX \
47832 #define HWRM_TF_EXT_EM_CFG_INPUT_FLAGS_DIR_LAST \
47833 HWRM_TF_EXT_EM_CFG_INPUT_FLAGS_DIR_TX
47834 /* When set to 1, all offloaded flows will be sent to EXT EM. */
47835 #define HWRM_TF_EXT_EM_CFG_INPUT_FLAGS_PREFERRED_OFFLOAD \
47837 /* When set to 1, secondary, 0 means primary. */
47838 #define HWRM_TF_EXT_EM_CFG_INPUT_FLAGS_SECONDARY_PF \
47841 * Group_id which used by Firmware to identify memory pools belonging
47842 * to certain group.
47846 * Dynamically reconfigure EEM pending cache every 1/10th of second.
47847 * If set to 0 it will disable the EEM HW flush of the pending cache.
47849 uint8_t flush_interval;
47853 * Configured EXT EM with the given number of entries. All
47854 * the EXT EM tables KEY0, KEY1, RECORD, EFC all have the
47855 * same number of entries and all tables will be configured
47856 * using this value. Current minimum value is 32k. Current
47857 * maximum value is 128M.
47859 uint32_t num_entries;
47862 * This bit must be '1' for the group_id field to be
47865 #define HWRM_TF_EXT_EM_CFG_INPUT_ENABLES_GROUP_ID \
47868 * This bit must be '1' for the flush_interval field to be
47871 #define HWRM_TF_EXT_EM_CFG_INPUT_ENABLES_FLUSH_INTERVAL \
47874 * This bit must be '1' for the num_entries field to be
47877 #define HWRM_TF_EXT_EM_CFG_INPUT_ENABLES_NUM_ENTRIES \
47880 * This bit must be '1' for the key0_ctx_id field to be
47883 #define HWRM_TF_EXT_EM_CFG_INPUT_ENABLES_KEY0_CTX_ID \
47886 * This bit must be '1' for the key1_ctx_id field to be
47889 #define HWRM_TF_EXT_EM_CFG_INPUT_ENABLES_KEY1_CTX_ID \
47892 * This bit must be '1' for the record_ctx_id field to be
47895 #define HWRM_TF_EXT_EM_CFG_INPUT_ENABLES_RECORD_CTX_ID \
47898 * This bit must be '1' for the efc_ctx_id field to be
47901 #define HWRM_TF_EXT_EM_CFG_INPUT_ENABLES_EFC_CTX_ID \
47904 * This bit must be '1' for the fid_ctx_id field to be
47907 #define HWRM_TF_EXT_EM_CFG_INPUT_ENABLES_FID_CTX_ID \
47910 * This bit must be '1' for the action_ctx_id field to be
47913 #define HWRM_TF_EXT_EM_CFG_INPUT_ENABLES_ACTION_CTX_ID \
47916 * This bit must be '1' for the action_tbl_scope field to be
47919 #define HWRM_TF_EXT_EM_CFG_INPUT_ENABLES_ACTION_TBL_SCOPE \
47922 * This bit must be '1' for the lkup_ctx_id field to be
47925 #define HWRM_TF_EXT_EM_CFG_INPUT_ENABLES_LKUP_CTX_ID \
47928 * This bit must be '1' for the lkup_tbl_scope field to be
47931 #define HWRM_TF_EXT_EM_CFG_INPUT_ENABLES_LKUP_TBL_SCOPE \
47934 * This bit must be '1' for the lkup_static_buckets field to be
47937 #define HWRM_TF_EXT_EM_CFG_INPUT_ENABLES_LKUP_STATIC_BUCKETS \
47939 /* Configured EXT EM with the given context if for KEY0 table. */
47940 uint16_t key0_ctx_id;
47941 /* Configured EXT EM with the given context if for KEY1 table. */
47942 uint16_t key1_ctx_id;
47943 /* Configured EXT EM with the given context if for RECORD table. */
47944 uint16_t record_ctx_id;
47945 /* Configured EXT EM with the given context if for EFC table. */
47946 uint16_t efc_ctx_id;
47947 /* Configured EXT EM with the given context if for EFC table. */
47948 uint16_t fid_ctx_id;
47949 /* Context id of action table scope. */
47950 uint16_t action_ctx_id;
47951 /* Table scope id used for action record entries. */
47952 uint16_t action_tbl_scope;
47953 /* Context id of lookup table scope. */
47954 uint16_t lkup_ctx_id;
47955 /* Table scope id used for EM lookup entries. */
47956 uint16_t lkup_tbl_scope;
47960 * Number of 32B static buckets to be allocated at the beginning
47963 uint32_t lkup_static_buckets;
47964 /* Firmware session id returned when HWRM_TF_SESSION_OPEN is sent. */
47965 uint32_t fw_session_id;
47970 /* hwrm_tf_ext_em_cfg_output (size:128b/16B) */
47971 struct hwrm_tf_ext_em_cfg_output {
47972 /* The specific error status for the command. */
47973 uint16_t error_code;
47974 /* The HWRM command request type. */
47976 /* The sequence ID from the original command. */
47978 /* The length of the response data in number of bytes. */
47981 uint8_t unused0[7];
47983 * This field is used in Output records to indicate that the
47984 * output is completely written to RAM. This field should be
47985 * read as '1' to indicate that the output has been
47986 * completely written. When writing a command completion or
47987 * response to an internal processor, the order of writes has
47988 * to be such that this field is written last.
47993 /***********************
47994 * hwrm_tf_ext_em_qcfg *
47995 ***********************/
47998 /* hwrm_tf_ext_em_qcfg_input (size:192b/24B) */
47999 struct hwrm_tf_ext_em_qcfg_input {
48000 /* The HWRM command request type. */
48003 * The completion ring to send the completion event on. This should
48004 * be the NQ ID returned from the `nq_alloc` HWRM command.
48006 uint16_t cmpl_ring;
48008 * The sequence ID is used by the driver for tracking multiple
48009 * commands. This ID is treated as opaque data by the firmware and
48010 * the value is returned in the `hwrm_resp_hdr` upon completion.
48014 * The target ID of the command:
48015 * * 0x0-0xFFF8 - The function ID
48016 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
48017 * * 0xFFFD - Reserved for user-space HWRM interface
48020 uint16_t target_id;
48022 * A physical address pointer pointing to a host buffer that the
48023 * command's response data will be written. This can be either a host
48024 * physical address (HPA) or a guest physical address (GPA) and must
48025 * point to a physically contiguous block of memory.
48027 uint64_t resp_addr;
48028 /* Control flags. */
48030 /* Indicates the flow direction. */
48031 #define HWRM_TF_EXT_EM_QCFG_INPUT_FLAGS_DIR UINT32_C(0x1)
48032 /* If this bit set to 0, then it indicates rx flow. */
48033 #define HWRM_TF_EXT_EM_QCFG_INPUT_FLAGS_DIR_RX UINT32_C(0x0)
48034 /* If this bit is set to 1, then it indicates tx flow. */
48035 #define HWRM_TF_EXT_EM_QCFG_INPUT_FLAGS_DIR_TX UINT32_C(0x1)
48036 #define HWRM_TF_EXT_EM_QCFG_INPUT_FLAGS_DIR_LAST \
48037 HWRM_TF_EXT_EM_QCFG_INPUT_FLAGS_DIR_TX
48038 /* Firmware session id returned when HWRM_TF_SESSION_OPEN is sent. */
48039 uint32_t fw_session_id;
48042 /* hwrm_tf_ext_em_qcfg_output (size:448b/56B) */
48043 struct hwrm_tf_ext_em_qcfg_output {
48044 /* The specific error status for the command. */
48045 uint16_t error_code;
48046 /* The HWRM command request type. */
48048 /* The sequence ID from the original command. */
48050 /* The length of the response data in number of bytes. */
48052 /* Control flags. */
48054 /* Indicates the flow direction. */
48055 #define HWRM_TF_EXT_EM_QCFG_OUTPUT_FLAGS_DIR \
48057 /* If this bit set to 0, then it indicates rx flow. */
48058 #define HWRM_TF_EXT_EM_QCFG_OUTPUT_FLAGS_DIR_RX \
48060 /* If this bit is set to 1, then it indicates tx flow. */
48061 #define HWRM_TF_EXT_EM_QCFG_OUTPUT_FLAGS_DIR_TX \
48063 #define HWRM_TF_EXT_EM_QCFG_OUTPUT_FLAGS_DIR_LAST \
48064 HWRM_TF_EXT_EM_QCFG_OUTPUT_FLAGS_DIR_TX
48065 /* When set to 1, all offloaded flows will be sent to EXT EM. */
48066 #define HWRM_TF_EXT_EM_QCFG_OUTPUT_FLAGS_PREFERRED_OFFLOAD \
48068 /* The number of entries the FW has configured for EXT EM. */
48069 uint32_t num_entries;
48070 /* Configured EXT EM with the given context if for KEY0 table. */
48071 uint16_t key0_ctx_id;
48072 /* Configured EXT EM with the given context if for KEY1 table. */
48073 uint16_t key1_ctx_id;
48074 /* Configured EXT EM with the given context if for RECORD table. */
48075 uint16_t record_ctx_id;
48076 /* Configured EXT EM with the given context if for EFC table. */
48077 uint16_t efc_ctx_id;
48078 /* Configured EXT EM with the given context if for EFC table. */
48079 uint16_t fid_ctx_id;
48082 uint32_t supported;
48083 /* This bit must be '1' for the group_id field is set. */
48084 #define HWRM_TF_EXT_EM_QCFG_OUTPUT_SUPPORTED_GROUP_ID \
48086 /* This bit must be '1' for the flush_interval field is set. */
48087 #define HWRM_TF_EXT_EM_QCFG_OUTPUT_SUPPORTED_FLUSH_INTERVAL \
48089 /* This bit must be '1' for the num_entries field is set. */
48090 #define HWRM_TF_EXT_EM_QCFG_OUTPUT_SUPPORTED_NUM_ENTRIES \
48092 /* This bit must be '1' for the key0_ctx_id field is set. */
48093 #define HWRM_TF_EXT_EM_QCFG_OUTPUT_SUPPORTED_KEY0_CTX_ID \
48095 /* This bit must be '1' for the key1_ctx_id field is set. */
48096 #define HWRM_TF_EXT_EM_QCFG_OUTPUT_SUPPORTED_KEY1_CTX_ID \
48098 /* This bit must be '1' for the record_ctx_id field is set. */
48099 #define HWRM_TF_EXT_EM_QCFG_OUTPUT_SUPPORTED_RECORD_CTX_ID \
48101 /* This bit must be '1' for the efc_ctx_id field is set. */
48102 #define HWRM_TF_EXT_EM_QCFG_OUTPUT_SUPPORTED_EFC_CTX_ID \
48104 /* This bit must be '1' for the fid_ctx_id field is set. */
48105 #define HWRM_TF_EXT_EM_QCFG_OUTPUT_SUPPORTED_FID_CTX_ID \
48107 /* This bit must be '1' for the action_ctx_id field is set. */
48108 #define HWRM_TF_EXT_EM_QCFG_OUTPUT_SUPPORTED_ACTION_CTX_ID \
48110 /* This bit must be '1' for the action_tbl_scope field is set. */
48111 #define HWRM_TF_EXT_EM_QCFG_OUTPUT_SUPPORTED_ACTION_TBL_SCOPE \
48113 /* This bit must be '1' for the lkup_ctx_id field is set. */
48114 #define HWRM_TF_EXT_EM_QCFG_OUTPUT_SUPPORTED_LKUP_CTX_ID \
48116 /* This bit must be '1' for the lkup_tbl_scope field is set. */
48117 #define HWRM_TF_EXT_EM_QCFG_OUTPUT_SUPPORTED_LKUP_TBL_SCOPE \
48119 /* This bit must be '1' for the lkup_static_buckets field is set. */
48120 #define HWRM_TF_EXT_EM_QCFG_OUTPUT_SUPPORTED_LKUP_STATIC_BUCKETS \
48123 * Group id is used by firmware to identify memory pools belonging
48124 * to certain group.
48127 /* EEM pending cache flush interval in 1/10th of second. */
48128 uint8_t flush_interval;
48131 /* Context id of action table scope. */
48132 uint16_t action_ctx_id;
48133 /* Table scope id used for action record entries. */
48134 uint16_t action_tbl_scope;
48135 /* Context id of lookup table scope. */
48136 uint16_t lkup_ctx_id;
48137 /* Table scope id used for EM lookup entries. */
48138 uint16_t lkup_tbl_scope;
48140 * Number of 32B static buckets to be allocated at the beginning
48143 uint32_t lkup_static_buckets;
48145 uint8_t unused2[7];
48147 * This field is used in Output records to indicate that the
48148 * output is completely written to RAM. This field should be
48149 * read as '1' to indicate that the output has been
48150 * completely written. When writing a command completion or
48151 * response to an internal processor, the order of writes has
48152 * to be such that this field is written last.
48157 /*********************
48158 * hwrm_tf_em_insert *
48159 *********************/
48162 /* hwrm_tf_em_insert_input (size:832b/104B) */
48163 struct hwrm_tf_em_insert_input {
48164 /* The HWRM command request type. */
48167 * The completion ring to send the completion event on. This should
48168 * be the NQ ID returned from the `nq_alloc` HWRM command.
48170 uint16_t cmpl_ring;
48172 * The sequence ID is used by the driver for tracking multiple
48173 * commands. This ID is treated as opaque data by the firmware and
48174 * the value is returned in the `hwrm_resp_hdr` upon completion.
48178 * The target ID of the command:
48179 * * 0x0-0xFFF8 - The function ID
48180 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
48181 * * 0xFFFD - Reserved for user-space HWRM interface
48184 uint16_t target_id;
48186 * A physical address pointer pointing to a host buffer that the
48187 * command's response data will be written. This can be either a host
48188 * physical address (HPA) or a guest physical address (GPA) and must
48189 * point to a physically contiguous block of memory.
48191 uint64_t resp_addr;
48192 /* Firmware Session Id. */
48193 uint32_t fw_session_id;
48194 /* Control Flags. */
48196 /* Indicates the flow direction. */
48197 #define HWRM_TF_EM_INSERT_INPUT_FLAGS_DIR UINT32_C(0x1)
48198 /* If this bit set to 0, then it indicates rx flow. */
48199 #define HWRM_TF_EM_INSERT_INPUT_FLAGS_DIR_RX UINT32_C(0x0)
48200 /* If this bit is set to 1, then it indicates tx flow. */
48201 #define HWRM_TF_EM_INSERT_INPUT_FLAGS_DIR_TX UINT32_C(0x1)
48202 #define HWRM_TF_EM_INSERT_INPUT_FLAGS_DIR_LAST \
48203 HWRM_TF_EM_INSERT_INPUT_FLAGS_DIR_TX
48204 /* Reported match strength. */
48206 /* Index to action. */
48207 uint32_t action_ptr;
48208 /* Index of EM record. */
48209 uint32_t em_record_idx;
48210 /* EM Key value. */
48211 uint64_t em_key[8];
48212 /* Number of bits in em_key. */
48213 uint16_t em_key_bitlen;
48215 uint16_t unused0[3];
48218 /* hwrm_tf_em_insert_output (size:128b/16B) */
48219 struct hwrm_tf_em_insert_output {
48220 /* The specific error status for the command. */
48221 uint16_t error_code;
48222 /* The HWRM command request type. */
48224 /* The sequence ID from the original command. */
48226 /* The length of the response data in number of bytes. */
48228 /* EM record pointer index. */
48229 uint16_t rptr_index;
48230 /* EM record offset 0~3. */
48231 uint8_t rptr_entry;
48232 /* Number of word entries consumed by the key. */
48233 uint8_t num_of_entries;
48238 /**************************
48239 * hwrm_tf_em_hash_insert *
48240 **************************/
48243 /* hwrm_tf_em_hash_insert_input (size:1024b/128B) */
48244 struct hwrm_tf_em_hash_insert_input {
48245 /* The HWRM command request type. */
48248 * The completion ring to send the completion event on. This should
48249 * be the NQ ID returned from the `nq_alloc` HWRM command.
48251 uint16_t cmpl_ring;
48253 * The sequence ID is used by the driver for tracking multiple
48254 * commands. This ID is treated as opaque data by the firmware and
48255 * the value is returned in the `hwrm_resp_hdr` upon completion.
48259 * The target ID of the command:
48260 * * 0x0-0xFFF8 - The function ID
48261 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
48262 * * 0xFFFD - Reserved for user-space HWRM interface
48265 uint16_t target_id;
48267 * A physical address pointer pointing to a host buffer that the
48268 * command's response data will be written. This can be either a host
48269 * physical address (HPA) or a guest physical address (GPA) and must
48270 * point to a physically contiguous block of memory.
48272 uint64_t resp_addr;
48273 /* Firmware Session Id. */
48274 uint32_t fw_session_id;
48275 /* Control Flags. */
48277 /* Indicates the flow direction. */
48278 #define HWRM_TF_EM_HASH_INSERT_INPUT_FLAGS_DIR UINT32_C(0x1)
48279 /* If this bit set to 0, then it indicates rx flow. */
48280 #define HWRM_TF_EM_HASH_INSERT_INPUT_FLAGS_DIR_RX UINT32_C(0x0)
48281 /* If this bit is set to 1, then it indicates tx flow. */
48282 #define HWRM_TF_EM_HASH_INSERT_INPUT_FLAGS_DIR_TX UINT32_C(0x1)
48283 #define HWRM_TF_EM_HASH_INSERT_INPUT_FLAGS_DIR_LAST \
48284 HWRM_TF_EM_HASH_INSERT_INPUT_FLAGS_DIR_TX
48285 /* Number of bits in the EM record. */
48286 uint16_t em_record_size_bits;
48287 /* CRC32 hash of key. */
48288 uint32_t key0_hash;
48289 /* Lookup3 hash of key. */
48290 uint32_t key1_hash;
48291 /* Index of EM record. */
48292 uint32_t em_record_idx;
48296 uint64_t em_record[11];
48299 /* hwrm_tf_em_hash_insert_output (size:128b/16B) */
48300 struct hwrm_tf_em_hash_insert_output {
48301 /* The specific error status for the command. */
48302 uint16_t error_code;
48303 /* The HWRM command request type. */
48305 /* The sequence ID from the original command. */
48307 /* The length of the response data in number of bytes. */
48309 /* EM record pointer index. */
48310 uint16_t rptr_index;
48311 /* EM record offset 0~3. */
48312 uint8_t rptr_entry;
48313 /* Number of word entries consumed by the key. */
48314 uint8_t num_of_entries;
48319 /*********************
48320 * hwrm_tf_em_delete *
48321 *********************/
48324 /* hwrm_tf_em_delete_input (size:832b/104B) */
48325 struct hwrm_tf_em_delete_input {
48326 /* The HWRM command request type. */
48329 * The completion ring to send the completion event on. This should
48330 * be the NQ ID returned from the `nq_alloc` HWRM command.
48332 uint16_t cmpl_ring;
48334 * The sequence ID is used by the driver for tracking multiple
48335 * commands. This ID is treated as opaque data by the firmware and
48336 * the value is returned in the `hwrm_resp_hdr` upon completion.
48340 * The target ID of the command:
48341 * * 0x0-0xFFF8 - The function ID
48342 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
48343 * * 0xFFFD - Reserved for user-space HWRM interface
48346 uint16_t target_id;
48348 * A physical address pointer pointing to a host buffer that the
48349 * command's response data will be written. This can be either a host
48350 * physical address (HPA) or a guest physical address (GPA) and must
48351 * point to a physically contiguous block of memory.
48353 uint64_t resp_addr;
48355 uint32_t fw_session_id;
48356 /* Control flags. */
48358 /* Indicates the flow direction. */
48359 #define HWRM_TF_EM_DELETE_INPUT_FLAGS_DIR UINT32_C(0x1)
48360 /* If this bit set to 0, then it indicates rx flow. */
48361 #define HWRM_TF_EM_DELETE_INPUT_FLAGS_DIR_RX UINT32_C(0x0)
48362 /* If this bit is set to 1, then it indicates tx flow. */
48363 #define HWRM_TF_EM_DELETE_INPUT_FLAGS_DIR_TX UINT32_C(0x1)
48364 #define HWRM_TF_EM_DELETE_INPUT_FLAGS_DIR_LAST \
48365 HWRM_TF_EM_DELETE_INPUT_FLAGS_DIR_TX
48368 /* EM internal flow handle. */
48369 uint64_t flow_handle;
48371 uint64_t em_key[8];
48372 /* Number of bits in em_key. */
48373 uint16_t em_key_bitlen;
48375 uint16_t unused1[3];
48378 /* hwrm_tf_em_delete_output (size:128b/16B) */
48379 struct hwrm_tf_em_delete_output {
48380 /* The specific error status for the command. */
48381 uint16_t error_code;
48382 /* The HWRM command request type. */
48384 /* The sequence ID from the original command. */
48386 /* The length of the response data in number of bytes. */
48388 /* Original stack allocation index. */
48391 uint16_t unused0[3];
48394 /*******************
48395 * hwrm_tf_em_move *
48396 *******************/
48399 /* hwrm_tf_em_move_input (size:320b/40B) */
48400 struct hwrm_tf_em_move_input {
48401 /* The HWRM command request type. */
48404 * The completion ring to send the completion event on. This should
48405 * be the NQ ID returned from the `nq_alloc` HWRM command.
48407 uint16_t cmpl_ring;
48409 * The sequence ID is used by the driver for tracking multiple
48410 * commands. This ID is treated as opaque data by the firmware and
48411 * the value is returned in the `hwrm_resp_hdr` upon completion.
48415 * The target ID of the command:
48416 * * 0x0-0xFFF8 - The function ID
48417 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
48418 * * 0xFFFD - Reserved for user-space HWRM interface
48421 uint16_t target_id;
48423 * A physical address pointer pointing to a host buffer that the
48424 * command's response data will be written. This can be either a host
48425 * physical address (HPA) or a guest physical address (GPA) and must
48426 * point to a physically contiguous block of memory.
48428 uint64_t resp_addr;
48430 uint32_t fw_session_id;
48431 /* Control flags. */
48433 /* Indicates the flow direction. */
48434 #define HWRM_TF_EM_MOVE_INPUT_FLAGS_DIR UINT32_C(0x1)
48435 /* If this bit set to 0, then it indicates rx flow. */
48436 #define HWRM_TF_EM_MOVE_INPUT_FLAGS_DIR_RX UINT32_C(0x0)
48437 /* If this bit is set to 1, then it indicates tx flow. */
48438 #define HWRM_TF_EM_MOVE_INPUT_FLAGS_DIR_TX UINT32_C(0x1)
48439 #define HWRM_TF_EM_MOVE_INPUT_FLAGS_DIR_LAST \
48440 HWRM_TF_EM_MOVE_INPUT_FLAGS_DIR_TX
48441 /* Number of EM entry blocks */
48442 uint16_t num_blocks;
48443 /* New index for entry */
48444 uint32_t new_index;
48447 /* EM internal flow handle. */
48448 uint64_t flow_handle;
48451 /* hwrm_tf_em_move_output (size:128b/16B) */
48452 struct hwrm_tf_em_move_output {
48453 /* The specific error status for the command. */
48454 uint16_t error_code;
48455 /* The HWRM command request type. */
48457 /* The sequence ID from the original command. */
48459 /* The length of the response data in number of bytes. */
48461 /* Index of old entry. */
48464 uint16_t unused0[3];
48467 /********************
48468 * hwrm_tf_tcam_set *
48469 ********************/
48472 /* hwrm_tf_tcam_set_input (size:1024b/128B) */
48473 struct hwrm_tf_tcam_set_input {
48474 /* The HWRM command request type. */
48477 * The completion ring to send the completion event on. This should
48478 * be the NQ ID returned from the `nq_alloc` HWRM command.
48480 uint16_t cmpl_ring;
48482 * The sequence ID is used by the driver for tracking multiple
48483 * commands. This ID is treated as opaque data by the firmware and
48484 * the value is returned in the `hwrm_resp_hdr` upon completion.
48488 * The target ID of the command:
48489 * * 0x0-0xFFF8 - The function ID
48490 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
48491 * * 0xFFFD - Reserved for user-space HWRM interface
48494 uint16_t target_id;
48496 * A physical address pointer pointing to a host buffer that the
48497 * command's response data will be written. This can be either a host
48498 * physical address (HPA) or a guest physical address (GPA) and must
48499 * point to a physically contiguous block of memory.
48501 uint64_t resp_addr;
48502 /* Firmware session id returned when HWRM_TF_SESSION_OPEN is sent. */
48503 uint32_t fw_session_id;
48504 /* Control flags. */
48506 /* Indicates the flow direction. */
48507 #define HWRM_TF_TCAM_SET_INPUT_FLAGS_DIR UINT32_C(0x1)
48508 /* If this bit set to 0, then it indicates rx flow. */
48509 #define HWRM_TF_TCAM_SET_INPUT_FLAGS_DIR_RX UINT32_C(0x0)
48510 /* If this bit is set to 1, then it indicates tx flow. */
48511 #define HWRM_TF_TCAM_SET_INPUT_FLAGS_DIR_TX UINT32_C(0x1)
48512 #define HWRM_TF_TCAM_SET_INPUT_FLAGS_DIR_LAST \
48513 HWRM_TF_TCAM_SET_INPUT_FLAGS_DIR_TX
48515 * Indicate device data is being sent via DMA, the device
48516 * data is packing does not change.
48518 #define HWRM_TF_TCAM_SET_INPUT_FLAGS_DMA UINT32_C(0x2)
48520 * TCAM type of the resource, defined globally in the
48521 * hwrm_tf_resc_type enum.
48524 /* Index of TCAM entry. */
48526 /* Number of bytes in the TCAM key. */
48528 /* Number of bytes in the TCAM result. */
48529 uint8_t result_size;
48531 * Offset from which the mask bytes start in the device data
48532 * array, key offset is always 0.
48534 uint8_t mask_offset;
48535 /* Offset from which the result bytes start in the device data array. */
48536 uint8_t result_offset;
48538 uint8_t unused0[6];
48540 * TCAM key located at offset 0, mask located at mask_offset
48541 * and result at result_offset for the device.
48543 uint8_t dev_data[88];
48546 /* hwrm_tf_tcam_set_output (size:128b/16B) */
48547 struct hwrm_tf_tcam_set_output {
48548 /* The specific error status for the command. */
48549 uint16_t error_code;
48550 /* The HWRM command request type. */
48552 /* The sequence ID from the original command. */
48554 /* The length of the response data in number of bytes. */
48557 uint8_t unused0[7];
48559 * This field is used in Output records to indicate that the
48560 * output is completely written to RAM. This field should be
48561 * read as '1' to indicate that the output has been
48562 * completely written. When writing a command completion or
48563 * response to an internal processor, the order of writes has
48564 * to be such that this field is written last.
48569 /********************
48570 * hwrm_tf_tcam_get *
48571 ********************/
48574 /* hwrm_tf_tcam_get_input (size:256b/32B) */
48575 struct hwrm_tf_tcam_get_input {
48576 /* The HWRM command request type. */
48579 * The completion ring to send the completion event on. This should
48580 * be the NQ ID returned from the `nq_alloc` HWRM command.
48582 uint16_t cmpl_ring;
48584 * The sequence ID is used by the driver for tracking multiple
48585 * commands. This ID is treated as opaque data by the firmware and
48586 * the value is returned in the `hwrm_resp_hdr` upon completion.
48590 * The target ID of the command:
48591 * * 0x0-0xFFF8 - The function ID
48592 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
48593 * * 0xFFFD - Reserved for user-space HWRM interface
48596 uint16_t target_id;
48598 * A physical address pointer pointing to a host buffer that the
48599 * command's response data will be written. This can be either a host
48600 * physical address (HPA) or a guest physical address (GPA) and must
48601 * point to a physically contiguous block of memory.
48603 uint64_t resp_addr;
48604 /* Firmware session id returned when HWRM_TF_SESSION_OPEN is sent. */
48605 uint32_t fw_session_id;
48606 /* Control flags. */
48608 /* Indicates the flow direction. */
48609 #define HWRM_TF_TCAM_GET_INPUT_FLAGS_DIR UINT32_C(0x1)
48610 /* If this bit set to 0, then it indicates rx flow. */
48611 #define HWRM_TF_TCAM_GET_INPUT_FLAGS_DIR_RX UINT32_C(0x0)
48612 /* If this bit is set to 1, then it indicates tx flow. */
48613 #define HWRM_TF_TCAM_GET_INPUT_FLAGS_DIR_TX UINT32_C(0x1)
48614 #define HWRM_TF_TCAM_GET_INPUT_FLAGS_DIR_LAST \
48615 HWRM_TF_TCAM_GET_INPUT_FLAGS_DIR_TX
48617 * TCAM type of the resource, defined globally in the
48618 * hwrm_tf_resc_type enum.
48621 /* Index of a TCAM entry. */
48627 /* hwrm_tf_tcam_get_output (size:2368b/296B) */
48628 struct hwrm_tf_tcam_get_output {
48629 /* The specific error status for the command. */
48630 uint16_t error_code;
48631 /* The HWRM command request type. */
48633 /* The sequence ID from the original command. */
48635 /* The length of the response data in number of bytes. */
48637 /* Number of bytes in the TCAM key. */
48639 /* Number of bytes in the TCAM entry. */
48640 uint8_t result_size;
48641 /* Offset from which the mask bytes start in the device data array. */
48642 uint8_t mask_offset;
48643 /* Offset from which the result bytes start in the device data array. */
48644 uint8_t result_offset;
48646 uint8_t unused0[4];
48648 * TCAM key located at offset 0, mask located at mask_offset
48649 * and result at result_offset for the device.
48651 uint8_t dev_data[272];
48653 uint8_t unused1[7];
48655 * This field is used in Output records to indicate that the
48656 * output is completely written to RAM. This field should be
48657 * read as '1' to indicate that the output has been
48658 * completely written. When writing a command completion or
48659 * response to an internal processor, the order of writes has
48660 * to be such that this field is written last.
48665 /*********************
48666 * hwrm_tf_tcam_move *
48667 *********************/
48670 /* hwrm_tf_tcam_move_input (size:1024b/128B) */
48671 struct hwrm_tf_tcam_move_input {
48672 /* The HWRM command request type. */
48675 * The completion ring to send the completion event on. This should
48676 * be the NQ ID returned from the `nq_alloc` HWRM command.
48678 uint16_t cmpl_ring;
48680 * The sequence ID is used by the driver for tracking multiple
48681 * commands. This ID is treated as opaque data by the firmware and
48682 * the value is returned in the `hwrm_resp_hdr` upon completion.
48686 * The target ID of the command:
48687 * * 0x0-0xFFF8 - The function ID
48688 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
48689 * * 0xFFFD - Reserved for user-space HWRM interface
48692 uint16_t target_id;
48694 * A physical address pointer pointing to a host buffer that the
48695 * command's response data will be written. This can be either a host
48696 * physical address (HPA) or a guest physical address (GPA) and must
48697 * point to a physically contiguous block of memory.
48699 uint64_t resp_addr;
48700 /* Firmware session id returned when HWRM_TF_SESSION_OPEN is sent. */
48701 uint32_t fw_session_id;
48702 /* Control flags. */
48704 /* Indicates the flow direction. */
48705 #define HWRM_TF_TCAM_MOVE_INPUT_FLAGS_DIR UINT32_C(0x1)
48706 /* If this bit set to 0, then it indicates rx flow. */
48707 #define HWRM_TF_TCAM_MOVE_INPUT_FLAGS_DIR_RX UINT32_C(0x0)
48708 /* If this bit is set to 1, then it indicates tx flow. */
48709 #define HWRM_TF_TCAM_MOVE_INPUT_FLAGS_DIR_TX UINT32_C(0x1)
48710 #define HWRM_TF_TCAM_MOVE_INPUT_FLAGS_DIR_LAST \
48711 HWRM_TF_TCAM_MOVE_INPUT_FLAGS_DIR_TX
48713 * TCAM type of the resource, defined globally in the
48714 * hwrm_tf_resc_type enum.
48717 /* Number of TCAM index pairs to be swapped for the device. */
48721 /* TCAM index pairs to be swapped for the device. */
48722 uint16_t idx_pairs[48];
48725 /* hwrm_tf_tcam_move_output (size:128b/16B) */
48726 struct hwrm_tf_tcam_move_output {
48727 /* The specific error status for the command. */
48728 uint16_t error_code;
48729 /* The HWRM command request type. */
48731 /* The sequence ID from the original command. */
48733 /* The length of the response data in number of bytes. */
48736 uint8_t unused0[7];
48738 * This field is used in Output records to indicate that the
48739 * output is completely written to RAM. This field should be
48740 * read as '1' to indicate that the output has been
48741 * completely written. When writing a command completion or
48742 * response to an internal processor, the order of writes has
48743 * to be such that this field is written last.
48748 /*********************
48749 * hwrm_tf_tcam_free *
48750 *********************/
48753 /* hwrm_tf_tcam_free_input (size:1024b/128B) */
48754 struct hwrm_tf_tcam_free_input {
48755 /* The HWRM command request type. */
48758 * The completion ring to send the completion event on. This should
48759 * be the NQ ID returned from the `nq_alloc` HWRM command.
48761 uint16_t cmpl_ring;
48763 * The sequence ID is used by the driver for tracking multiple
48764 * commands. This ID is treated as opaque data by the firmware and
48765 * the value is returned in the `hwrm_resp_hdr` upon completion.
48769 * The target ID of the command:
48770 * * 0x0-0xFFF8 - The function ID
48771 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
48772 * * 0xFFFD - Reserved for user-space HWRM interface
48775 uint16_t target_id;
48777 * A physical address pointer pointing to a host buffer that the
48778 * command's response data will be written. This can be either a host
48779 * physical address (HPA) or a guest physical address (GPA) and must
48780 * point to a physically contiguous block of memory.
48782 uint64_t resp_addr;
48783 /* Firmware session id returned when HWRM_TF_SESSION_OPEN is sent. */
48784 uint32_t fw_session_id;
48785 /* Control flags. */
48787 /* Indicates the flow direction. */
48788 #define HWRM_TF_TCAM_FREE_INPUT_FLAGS_DIR UINT32_C(0x1)
48789 /* If this bit set to 0, then it indicates rx flow. */
48790 #define HWRM_TF_TCAM_FREE_INPUT_FLAGS_DIR_RX UINT32_C(0x0)
48791 /* If this bit is set to 1, then it indicates tx flow. */
48792 #define HWRM_TF_TCAM_FREE_INPUT_FLAGS_DIR_TX UINT32_C(0x1)
48793 #define HWRM_TF_TCAM_FREE_INPUT_FLAGS_DIR_LAST \
48794 HWRM_TF_TCAM_FREE_INPUT_FLAGS_DIR_TX
48796 * TCAM type of the resource, defined globally in the
48797 * hwrm_tf_resc_type enum.
48800 /* Number of TCAM index to be deleted for the device. */
48804 /* TCAM index list to be deleted for the device. */
48805 uint16_t idx_list[48];
48808 /* hwrm_tf_tcam_free_output (size:128b/16B) */
48809 struct hwrm_tf_tcam_free_output {
48810 /* The specific error status for the command. */
48811 uint16_t error_code;
48812 /* The HWRM command request type. */
48814 /* The sequence ID from the original command. */
48816 /* The length of the response data in number of bytes. */
48819 uint8_t unused0[7];
48821 * This field is used in Output records to indicate that the
48822 * output is completely written to RAM. This field should be
48823 * read as '1' to indicate that the output has been
48824 * completely written. When writing a command completion or
48825 * response to an internal processor, the order of writes has
48826 * to be such that this field is written last.
48831 /**************************
48832 * hwrm_tf_global_cfg_set *
48833 **************************/
48836 /* hwrm_tf_global_cfg_set_input (size:448b/56B) */
48837 struct hwrm_tf_global_cfg_set_input {
48838 /* The HWRM command request type. */
48841 * The completion ring to send the completion event on. This should
48842 * be the NQ ID returned from the `nq_alloc` HWRM command.
48844 uint16_t cmpl_ring;
48846 * The sequence ID is used by the driver for tracking multiple
48847 * commands. This ID is treated as opaque data by the firmware and
48848 * the value is returned in the `hwrm_resp_hdr` upon completion.
48852 * The target ID of the command:
48853 * * 0x0-0xFFF8 - The function ID
48854 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
48855 * * 0xFFFD - Reserved for user-space HWRM interface
48858 uint16_t target_id;
48860 * A physical address pointer pointing to a host buffer that the
48861 * command's response data will be written. This can be either a host
48862 * physical address (HPA) or a guest physical address (GPA) and must
48863 * point to a physically contiguous block of memory.
48865 uint64_t resp_addr;
48866 /* Firmware session id returned when HWRM_TF_SESSION_OPEN is sent. */
48867 uint32_t fw_session_id;
48868 /* Control flags. */
48870 /* Indicates the flow direction. */
48871 #define HWRM_TF_GLOBAL_CFG_SET_INPUT_FLAGS_DIR UINT32_C(0x1)
48872 /* If this bit set to 0, then it indicates rx flow. */
48873 #define HWRM_TF_GLOBAL_CFG_SET_INPUT_FLAGS_DIR_RX UINT32_C(0x0)
48874 /* If this bit is set to 1, then it indicates tx flow. */
48875 #define HWRM_TF_GLOBAL_CFG_SET_INPUT_FLAGS_DIR_TX UINT32_C(0x1)
48876 #define HWRM_TF_GLOBAL_CFG_SET_INPUT_FLAGS_DIR_LAST \
48877 HWRM_TF_GLOBAL_CFG_SET_INPUT_FLAGS_DIR_TX
48878 /* Global Cfg type */
48880 /* Offset of the type */
48882 /* Size of the data to set in bytes */
48885 uint8_t unused0[6];
48888 /* Mask of data to set, 0 indicates no mask */
48892 /* hwrm_tf_global_cfg_set_output (size:128b/16B) */
48893 struct hwrm_tf_global_cfg_set_output {
48894 /* The specific error status for the command. */
48895 uint16_t error_code;
48896 /* The HWRM command request type. */
48898 /* The sequence ID from the original command. */
48900 /* The length of the response data in number of bytes. */
48903 uint8_t unused0[7];
48905 * This field is used in Output records to indicate that the
48906 * output is completely written to RAM. This field should be
48907 * read as '1' to indicate that the output has been
48908 * completely written. When writing a command completion or
48909 * response to an internal processor, the order of writes has
48910 * to be such that this field is written last.
48915 /**************************
48916 * hwrm_tf_global_cfg_get *
48917 **************************/
48920 /* hwrm_tf_global_cfg_get_input (size:320b/40B) */
48921 struct hwrm_tf_global_cfg_get_input {
48922 /* The HWRM command request type. */
48925 * The completion ring to send the completion event on. This should
48926 * be the NQ ID returned from the `nq_alloc` HWRM command.
48928 uint16_t cmpl_ring;
48930 * The sequence ID is used by the driver for tracking multiple
48931 * commands. This ID is treated as opaque data by the firmware and
48932 * the value is returned in the `hwrm_resp_hdr` upon completion.
48936 * The target ID of the command:
48937 * * 0x0-0xFFF8 - The function ID
48938 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
48939 * * 0xFFFD - Reserved for user-space HWRM interface
48942 uint16_t target_id;
48944 * A physical address pointer pointing to a host buffer that the
48945 * command's response data will be written. This can be either a host
48946 * physical address (HPA) or a guest physical address (GPA) and must
48947 * point to a physically contiguous block of memory.
48949 uint64_t resp_addr;
48950 /* Firmware session id returned when HWRM_TF_SESSION_OPEN is sent. */
48951 uint32_t fw_session_id;
48952 /* Control flags. */
48954 /* Indicates the flow direction. */
48955 #define HWRM_TF_GLOBAL_CFG_GET_INPUT_FLAGS_DIR UINT32_C(0x1)
48956 /* If this bit set to 0, then it indicates rx flow. */
48957 #define HWRM_TF_GLOBAL_CFG_GET_INPUT_FLAGS_DIR_RX UINT32_C(0x0)
48958 /* If this bit is set to 1, then it indicates tx flow. */
48959 #define HWRM_TF_GLOBAL_CFG_GET_INPUT_FLAGS_DIR_TX UINT32_C(0x1)
48960 #define HWRM_TF_GLOBAL_CFG_GET_INPUT_FLAGS_DIR_LAST \
48961 HWRM_TF_GLOBAL_CFG_GET_INPUT_FLAGS_DIR_TX
48962 /* Global Cfg type */
48964 /* Offset of the type */
48966 /* Size of the data to set in bytes */
48969 uint8_t unused0[6];
48972 /* hwrm_tf_global_cfg_get_output (size:256b/32B) */
48973 struct hwrm_tf_global_cfg_get_output {
48974 /* The specific error status for the command. */
48975 uint16_t error_code;
48976 /* The HWRM command request type. */
48978 /* The sequence ID from the original command. */
48980 /* The length of the response data in number of bytes. */
48982 /* Size of the data read in bytes */
48985 uint8_t unused0[6];
48990 /**********************
48991 * hwrm_tf_if_tbl_get *
48992 **********************/
48995 /* hwrm_tf_if_tbl_get_input (size:256b/32B) */
48996 struct hwrm_tf_if_tbl_get_input {
48997 /* The HWRM command request type. */
49000 * The completion ring to send the completion event on. This should
49001 * be the NQ ID returned from the `nq_alloc` HWRM command.
49003 uint16_t cmpl_ring;
49005 * The sequence ID is used by the driver for tracking multiple
49006 * commands. This ID is treated as opaque data by the firmware and
49007 * the value is returned in the `hwrm_resp_hdr` upon completion.
49011 * The target ID of the command:
49012 * * 0x0-0xFFF8 - The function ID
49013 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
49014 * * 0xFFFD - Reserved for user-space HWRM interface
49017 uint16_t target_id;
49019 * A physical address pointer pointing to a host buffer that the
49020 * command's response data will be written. This can be either a host
49021 * physical address (HPA) or a guest physical address (GPA) and must
49022 * point to a physically contiguous block of memory.
49024 uint64_t resp_addr;
49025 /* Firmware session id returned when HWRM_TF_SESSION_OPEN is sent. */
49026 uint32_t fw_session_id;
49027 /* Control flags. */
49029 /* Indicates the flow direction. */
49030 #define HWRM_TF_IF_TBL_GET_INPUT_FLAGS_DIR UINT32_C(0x1)
49031 /* If this bit set to 0, then it indicates rx flow. */
49032 #define HWRM_TF_IF_TBL_GET_INPUT_FLAGS_DIR_RX UINT32_C(0x0)
49033 /* If this bit is set to 1, then it indicates tx flow. */
49034 #define HWRM_TF_IF_TBL_GET_INPUT_FLAGS_DIR_TX UINT32_C(0x1)
49035 #define HWRM_TF_IF_TBL_GET_INPUT_FLAGS_DIR_LAST \
49036 HWRM_TF_IF_TBL_GET_INPUT_FLAGS_DIR_TX
49037 /* Size of the data to set. */
49040 * Type of the resource, defined globally in the
49041 * hwrm_tf_resc_type enum.
49044 /* Index of the type to retrieve. */
49048 /* hwrm_tf_if_tbl_get_output (size:256b/32B) */
49049 struct hwrm_tf_if_tbl_get_output {
49050 /* The specific error status for the command. */
49051 uint16_t error_code;
49052 /* The HWRM command request type. */
49054 /* The sequence ID from the original command. */
49056 /* The length of the response data in number of bytes. */
49058 /* Response code. */
49059 uint32_t resp_code;
49060 /* Response size. */
49064 /* Response data. */
49067 uint8_t unused1[7];
49069 * This field is used in Output records to indicate that the output
49070 * is completely written to RAM. This field should be read as '1'
49071 * to indicate that the output has been completely written.
49072 * When writing a command completion or response to an internal
49073 * processor, the order of writes has to be such that this field
49079 /***************************
49080 * hwrm_tf_if_tbl_type_set *
49081 ***************************/
49084 /* hwrm_tf_if_tbl_set_input (size:384b/48B) */
49085 struct hwrm_tf_if_tbl_set_input {
49086 /* The HWRM command request type. */
49089 * The completion ring to send the completion event on. This should
49090 * be the NQ ID returned from the `nq_alloc` HWRM command.
49092 uint16_t cmpl_ring;
49094 * The sequence ID is used by the driver for tracking multiple
49095 * commands. This ID is treated as opaque data by the firmware and
49096 * the value is returned in the `hwrm_resp_hdr` upon completion.
49100 * The target ID of the command:
49101 * * 0x0-0xFFF8 - The function ID
49102 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
49103 * * 0xFFFD - Reserved for user-space HWRM interface
49106 uint16_t target_id;
49108 * A physical address pointer pointing to a host buffer that the
49109 * command's response data will be written. This can be either a host
49110 * physical address (HPA) or a guest physical address (GPA) and must
49111 * point to a physically contiguous block of memory.
49113 uint64_t resp_addr;
49114 /* Firmware session id returned when HWRM_TF_SESSION_OPEN is sent. */
49115 uint32_t fw_session_id;
49116 /* Control flags. */
49118 /* Indicates the flow direction. */
49119 #define HWRM_TF_IF_TBL_SET_INPUT_FLAGS_DIR UINT32_C(0x1)
49120 /* If this bit set to 0, then it indicates rx flow. */
49121 #define HWRM_TF_IF_TBL_SET_INPUT_FLAGS_DIR_RX UINT32_C(0x0)
49122 /* If this bit is set to 1, then it indicates tx flow. */
49123 #define HWRM_TF_IF_TBL_SET_INPUT_FLAGS_DIR_TX UINT32_C(0x1)
49124 #define HWRM_TF_IF_TBL_SET_INPUT_FLAGS_DIR_LAST \
49125 HWRM_TF_IF_TBL_SET_INPUT_FLAGS_DIR_TX
49127 uint8_t unused0[2];
49129 * Type of the resource, defined globally in the
49130 * hwrm_tf_resc_type enum.
49133 /* Index of the type to set. */
49135 /* Size of the data to set. */
49138 uint8_t unused1[6];
49139 /* Data to be set. */
49143 /* hwrm_tf_if_tbl_set_output (size:128b/16B) */
49144 struct hwrm_tf_if_tbl_set_output {
49145 /* The specific error status for the command. */
49146 uint16_t error_code;
49147 /* The HWRM command request type. */
49149 /* The sequence ID from the original command. */
49151 /* The length of the response data in number of bytes. */
49154 uint8_t unused0[7];
49156 * This field is used in Output records to indicate that the output
49157 * is completely written to RAM. This field should be read as '1'
49158 * to indicate that the output has been completely written.
49159 * When writing a command completion or response to an internal
49160 * processor, the order of writes has to be such that this field
49166 /*****************************
49167 * hwrm_tf_tbl_type_bulk_get *
49168 *****************************/
49171 /* hwrm_tf_tbl_type_bulk_get_input (size:384b/48B) */
49172 struct hwrm_tf_tbl_type_bulk_get_input {
49173 /* The HWRM command request type. */
49176 * The completion ring to send the completion event on. This should
49177 * be the NQ ID returned from the `nq_alloc` HWRM command.
49179 uint16_t cmpl_ring;
49181 * The sequence ID is used by the driver for tracking multiple
49182 * commands. This ID is treated as opaque data by the firmware and
49183 * the value is returned in the `hwrm_resp_hdr` upon completion.
49187 * The target ID of the command:
49188 * * 0x0-0xFFF8 - The function ID
49189 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
49190 * * 0xFFFD - Reserved for user-space HWRM interface
49193 uint16_t target_id;
49195 * A physical address pointer pointing to a host buffer that the
49196 * command's response data will be written. This can be either a host
49197 * physical address (HPA) or a guest physical address (GPA) and must
49198 * point to a physically contiguous block of memory.
49200 uint64_t resp_addr;
49201 /* Firmware session id returned when HWRM_TF_SESSION_OPEN is sent. */
49202 uint32_t fw_session_id;
49203 /* Control flags. */
49205 /* Indicates the flow direction. */
49206 #define HWRM_TF_TBL_TYPE_BULK_GET_INPUT_FLAGS_DIR \
49208 /* If this bit set to 0, then it indicates rx flow. */
49209 #define HWRM_TF_TBL_TYPE_BULK_GET_INPUT_FLAGS_DIR_RX \
49211 /* If this bit is set to 1, then it indicates tx flow. */
49212 #define HWRM_TF_TBL_TYPE_BULK_GET_INPUT_FLAGS_DIR_TX \
49214 #define HWRM_TF_TBL_TYPE_BULK_GET_INPUT_FLAGS_DIR_LAST \
49215 HWRM_TF_TBL_TYPE_BULK_GET_INPUT_FLAGS_DIR_TX
49217 * When set use the special access register access to clear
49218 * the table entries on read.
49220 #define HWRM_TF_TBL_TYPE_BULK_GET_INPUT_FLAGS_CLEAR_ON_READ \
49223 uint8_t unused0[2];
49225 * Type of the resource, defined globally in the
49226 * hwrm_tf_resc_type enum.
49229 /* Starting index of the type to retrieve. */
49230 uint32_t start_index;
49231 /* Number of entries to retrieve. */
49232 uint32_t num_entries;
49233 /* Number of entries to retrieve. */
49235 /* Host memory where data will be stored. */
49236 uint64_t host_addr;
49239 /* hwrm_tf_tbl_type_bulk_get_output (size:128b/16B) */
49240 struct hwrm_tf_tbl_type_bulk_get_output {
49241 /* The specific error status for the command. */
49242 uint16_t error_code;
49243 /* The HWRM command request type. */
49245 /* The sequence ID from the original command. */
49247 /* The length of the response data in number of bytes. */
49249 /* Response code. */
49250 uint32_t resp_code;
49251 /* Response size. */
49256 * This field is used in Output records to indicate that the output
49257 * is completely written to RAM. This field should be read as '1'
49258 * to indicate that the output has been completely written.
49259 * When writing a command completion or response to an internal
49260 * processor, the order of writes has to be such that this field
49266 /******************************
49267 * hwrm_tunnel_dst_port_query *
49268 ******************************/
49271 /* hwrm_tunnel_dst_port_query_input (size:192b/24B) */
49272 struct hwrm_tunnel_dst_port_query_input {
49273 /* The HWRM command request type. */
49276 * The completion ring to send the completion event on. This should
49277 * be the NQ ID returned from the `nq_alloc` HWRM command.
49279 uint16_t cmpl_ring;
49281 * The sequence ID is used by the driver for tracking multiple
49282 * commands. This ID is treated as opaque data by the firmware and
49283 * the value is returned in the `hwrm_resp_hdr` upon completion.
49287 * The target ID of the command:
49288 * * 0x0-0xFFF8 - The function ID
49289 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
49290 * * 0xFFFD - Reserved for user-space HWRM interface
49293 uint16_t target_id;
49295 * A physical address pointer pointing to a host buffer that the
49296 * command's response data will be written. This can be either a host
49297 * physical address (HPA) or a guest physical address (GPA) and must
49298 * point to a physically contiguous block of memory.
49300 uint64_t resp_addr;
49302 uint8_t tunnel_type;
49303 /* Virtual eXtensible Local Area Network (VXLAN) */
49304 #define HWRM_TUNNEL_DST_PORT_QUERY_INPUT_TUNNEL_TYPE_VXLAN \
49306 /* Generic Network Virtualization Encapsulation (Geneve) */
49307 #define HWRM_TUNNEL_DST_PORT_QUERY_INPUT_TUNNEL_TYPE_GENEVE \
49309 /* IPV4 over virtual eXtensible Local Area Network (IPV4oVXLAN) */
49310 #define HWRM_TUNNEL_DST_PORT_QUERY_INPUT_TUNNEL_TYPE_VXLAN_V4 \
49312 /* Enhance Generic Routing Encapsulation (GRE version 1) inside IP datagram payload */
49313 #define HWRM_TUNNEL_DST_PORT_QUERY_INPUT_TUNNEL_TYPE_IPGRE_V1 \
49315 /* Use fixed layer 2 ether type of 0xFFFF */
49316 #define HWRM_TUNNEL_DST_PORT_QUERY_INPUT_TUNNEL_TYPE_L2_ETYPE \
49318 /* IPV6 over virtual eXtensible Local Area Network with GPE header (IPV6oVXLANGPE) */
49319 #define HWRM_TUNNEL_DST_PORT_QUERY_INPUT_TUNNEL_TYPE_VXLAN_GPE_V6 \
49321 #define HWRM_TUNNEL_DST_PORT_QUERY_INPUT_TUNNEL_TYPE_LAST \
49322 HWRM_TUNNEL_DST_PORT_QUERY_INPUT_TUNNEL_TYPE_VXLAN_GPE_V6
49323 uint8_t unused_0[7];
49326 /* hwrm_tunnel_dst_port_query_output (size:128b/16B) */
49327 struct hwrm_tunnel_dst_port_query_output {
49328 /* The specific error status for the command. */
49329 uint16_t error_code;
49330 /* The HWRM command request type. */
49332 /* The sequence ID from the original command. */
49334 /* The length of the response data in number of bytes. */
49337 * This field represents the identifier of L4 destination port
49338 * used for the given tunnel type. This field is valid for
49339 * specific tunnel types that use layer 4 (e.g. UDP)
49340 * transports for tunneling.
49342 uint16_t tunnel_dst_port_id;
49344 * This field represents the value of L4 destination port
49345 * identified by tunnel_dst_port_id. This field is valid for
49346 * specific tunnel types that use layer 4 (e.g. UDP)
49347 * transports for tunneling.
49348 * This field is in network byte order.
49350 * A value of 0 means that the destination port is not
49353 uint16_t tunnel_dst_port_val;
49354 uint8_t unused_0[3];
49356 * This field is used in Output records to indicate that the output
49357 * is completely written to RAM. This field should be read as '1'
49358 * to indicate that the output has been completely written.
49359 * When writing a command completion or response to an internal processor,
49360 * the order of writes has to be such that this field is written last.
49365 /******************************
49366 * hwrm_tunnel_dst_port_alloc *
49367 ******************************/
49370 /* hwrm_tunnel_dst_port_alloc_input (size:192b/24B) */
49371 struct hwrm_tunnel_dst_port_alloc_input {
49372 /* The HWRM command request type. */
49375 * The completion ring to send the completion event on. This should
49376 * be the NQ ID returned from the `nq_alloc` HWRM command.
49378 uint16_t cmpl_ring;
49380 * The sequence ID is used by the driver for tracking multiple
49381 * commands. This ID is treated as opaque data by the firmware and
49382 * the value is returned in the `hwrm_resp_hdr` upon completion.
49386 * The target ID of the command:
49387 * * 0x0-0xFFF8 - The function ID
49388 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
49389 * * 0xFFFD - Reserved for user-space HWRM interface
49392 uint16_t target_id;
49394 * A physical address pointer pointing to a host buffer that the
49395 * command's response data will be written. This can be either a host
49396 * physical address (HPA) or a guest physical address (GPA) and must
49397 * point to a physically contiguous block of memory.
49399 uint64_t resp_addr;
49401 uint8_t tunnel_type;
49402 /* Virtual eXtensible Local Area Network (VXLAN) */
49403 #define HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_VXLAN \
49405 /* Generic Network Virtualization Encapsulation (Geneve) */
49406 #define HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_GENEVE \
49408 /* IPV4 over virtual eXtensible Local Area Network (IPV4oVXLAN) */
49409 #define HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_VXLAN_V4 \
49411 /* Enhance Generic Routing Encapsulation (GRE version 1) inside IP datagram payload */
49412 #define HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_IPGRE_V1 \
49414 /* Use fixed layer 2 ether type of 0xFFFF */
49415 #define HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_L2_ETYPE \
49417 /* IPV6 over virtual eXtensible Local Area Network with GPE header (IPV6oVXLANGPE) */
49418 #define HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_VXLAN_GPE_V6 \
49420 #define HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_LAST \
49421 HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_VXLAN_GPE_V6
49424 * This field represents the value of L4 destination port used
49425 * for the given tunnel type. This field is valid for
49426 * specific tunnel types that use layer 4 (e.g. UDP)
49427 * transports for tunneling.
49429 * This field is in network byte order.
49431 * A value of 0 shall fail the command.
49433 uint16_t tunnel_dst_port_val;
49434 uint8_t unused_1[4];
49437 /* hwrm_tunnel_dst_port_alloc_output (size:128b/16B) */
49438 struct hwrm_tunnel_dst_port_alloc_output {
49439 /* The specific error status for the command. */
49440 uint16_t error_code;
49441 /* The HWRM command request type. */
49443 /* The sequence ID from the original command. */
49445 /* The length of the response data in number of bytes. */
49448 * Identifier of a tunnel L4 destination port value. Only applies to tunnel
49449 * types that has l4 destination port parameters.
49451 uint16_t tunnel_dst_port_id;
49452 uint8_t unused_0[5];
49454 * This field is used in Output records to indicate that the output
49455 * is completely written to RAM. This field should be read as '1'
49456 * to indicate that the output has been completely written.
49457 * When writing a command completion or response to an internal processor,
49458 * the order of writes has to be such that this field is written last.
49463 /*****************************
49464 * hwrm_tunnel_dst_port_free *
49465 *****************************/
49468 /* hwrm_tunnel_dst_port_free_input (size:192b/24B) */
49469 struct hwrm_tunnel_dst_port_free_input {
49470 /* The HWRM command request type. */
49473 * The completion ring to send the completion event on. This should
49474 * be the NQ ID returned from the `nq_alloc` HWRM command.
49476 uint16_t cmpl_ring;
49478 * The sequence ID is used by the driver for tracking multiple
49479 * commands. This ID is treated as opaque data by the firmware and
49480 * the value is returned in the `hwrm_resp_hdr` upon completion.
49484 * The target ID of the command:
49485 * * 0x0-0xFFF8 - The function ID
49486 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
49487 * * 0xFFFD - Reserved for user-space HWRM interface
49490 uint16_t target_id;
49492 * A physical address pointer pointing to a host buffer that the
49493 * command's response data will be written. This can be either a host
49494 * physical address (HPA) or a guest physical address (GPA) and must
49495 * point to a physically contiguous block of memory.
49497 uint64_t resp_addr;
49499 uint8_t tunnel_type;
49500 /* Virtual eXtensible Local Area Network (VXLAN) */
49501 #define HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_VXLAN \
49503 /* Generic Network Virtualization Encapsulation (Geneve) */
49504 #define HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_GENEVE \
49506 /* IPV4 over virtual eXtensible Local Area Network (IPV4oVXLAN) */
49507 #define HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_VXLAN_V4 \
49509 /* Enhance Generic Routing Encapsulation (GRE version 1) inside IP datagram payload */
49510 #define HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_IPGRE_V1 \
49512 /* Use fixed layer 2 ether type of 0xFFFF */
49513 #define HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_L2_ETYPE \
49515 /* IPV6 over virtual eXtensible Local Area Network with GPE header (IPV6oVXLANGPE) */
49516 #define HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_VXLAN_GPE_V6 \
49518 #define HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_LAST \
49519 HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_VXLAN_GPE_V6
49522 * Identifier of a tunnel L4 destination port value. Only applies to tunnel
49523 * types that has l4 destination port parameters.
49525 uint16_t tunnel_dst_port_id;
49526 uint8_t unused_1[4];
49529 /* hwrm_tunnel_dst_port_free_output (size:128b/16B) */
49530 struct hwrm_tunnel_dst_port_free_output {
49531 /* The specific error status for the command. */
49532 uint16_t error_code;
49533 /* The HWRM command request type. */
49535 /* The sequence ID from the original command. */
49537 /* The length of the response data in number of bytes. */
49539 uint8_t unused_1[7];
49541 * This field is used in Output records to indicate that the output
49542 * is completely written to RAM. This field should be read as '1'
49543 * to indicate that the output has been completely written.
49544 * When writing a command completion or response to an internal processor,
49545 * the order of writes has to be such that this field is written last.
49550 /* Periodic statistics context DMA to host. */
49551 /* ctx_hw_stats (size:1280b/160B) */
49552 struct ctx_hw_stats {
49553 /* Number of received unicast packets */
49554 uint64_t rx_ucast_pkts;
49555 /* Number of received multicast packets */
49556 uint64_t rx_mcast_pkts;
49557 /* Number of received broadcast packets */
49558 uint64_t rx_bcast_pkts;
49559 /* Number of discarded packets on receive path */
49560 uint64_t rx_discard_pkts;
49561 /* Number of packets on receive path with error */
49562 uint64_t rx_error_pkts;
49563 /* Number of received bytes for unicast traffic */
49564 uint64_t rx_ucast_bytes;
49565 /* Number of received bytes for multicast traffic */
49566 uint64_t rx_mcast_bytes;
49567 /* Number of received bytes for broadcast traffic */
49568 uint64_t rx_bcast_bytes;
49569 /* Number of transmitted unicast packets */
49570 uint64_t tx_ucast_pkts;
49571 /* Number of transmitted multicast packets */
49572 uint64_t tx_mcast_pkts;
49573 /* Number of transmitted broadcast packets */
49574 uint64_t tx_bcast_pkts;
49575 /* Number of packets on transmit path with error */
49576 uint64_t tx_error_pkts;
49577 /* Number of discarded packets on transmit path */
49578 uint64_t tx_discard_pkts;
49579 /* Number of transmitted bytes for unicast traffic */
49580 uint64_t tx_ucast_bytes;
49581 /* Number of transmitted bytes for multicast traffic */
49582 uint64_t tx_mcast_bytes;
49583 /* Number of transmitted bytes for broadcast traffic */
49584 uint64_t tx_bcast_bytes;
49585 /* Number of TPA packets */
49587 /* Number of TPA bytes */
49588 uint64_t tpa_bytes;
49589 /* Number of TPA events */
49590 uint64_t tpa_events;
49591 /* Number of TPA aborts */
49592 uint64_t tpa_aborts;
49596 * Extended periodic statistics context DMA to host. On cards that
49597 * support TPA v2, additional TPA related stats exist and can be retrieved
49598 * by DMA of ctx_hw_stats_ext, rather than legacy ctx_hw_stats structure.
49600 /* ctx_hw_stats_ext (size:1408b/176B) */
49601 struct ctx_hw_stats_ext {
49602 /* Number of received unicast packets */
49603 uint64_t rx_ucast_pkts;
49604 /* Number of received multicast packets */
49605 uint64_t rx_mcast_pkts;
49606 /* Number of received broadcast packets */
49607 uint64_t rx_bcast_pkts;
49608 /* Number of discarded packets on receive path */
49609 uint64_t rx_discard_pkts;
49610 /* Number of packets on receive path with error */
49611 uint64_t rx_error_pkts;
49612 /* Number of received bytes for unicast traffic */
49613 uint64_t rx_ucast_bytes;
49614 /* Number of received bytes for multicast traffic */
49615 uint64_t rx_mcast_bytes;
49616 /* Number of received bytes for broadcast traffic */
49617 uint64_t rx_bcast_bytes;
49618 /* Number of transmitted unicast packets */
49619 uint64_t tx_ucast_pkts;
49620 /* Number of transmitted multicast packets */
49621 uint64_t tx_mcast_pkts;
49622 /* Number of transmitted broadcast packets */
49623 uint64_t tx_bcast_pkts;
49624 /* Number of packets on transmit path with error */
49625 uint64_t tx_error_pkts;
49626 /* Number of discarded packets on transmit path */
49627 uint64_t tx_discard_pkts;
49628 /* Number of transmitted bytes for unicast traffic */
49629 uint64_t tx_ucast_bytes;
49630 /* Number of transmitted bytes for multicast traffic */
49631 uint64_t tx_mcast_bytes;
49632 /* Number of transmitted bytes for broadcast traffic */
49633 uint64_t tx_bcast_bytes;
49634 /* Number of TPA eligible packets */
49635 uint64_t rx_tpa_eligible_pkt;
49636 /* Number of TPA eligible bytes */
49637 uint64_t rx_tpa_eligible_bytes;
49638 /* Number of TPA packets */
49639 uint64_t rx_tpa_pkt;
49640 /* Number of TPA bytes */
49641 uint64_t rx_tpa_bytes;
49642 /* Number of TPA errors */
49643 uint64_t rx_tpa_errors;
49644 /* Number of TPA events */
49645 uint64_t rx_tpa_events;
49648 /* Periodic Engine statistics context DMA to host. */
49649 /* ctx_eng_stats (size:512b/64B) */
49650 struct ctx_eng_stats {
49652 * Count of data bytes into the Engine.
49653 * This includes any user supplied prefix,
49654 * but does not include any predefined
49657 uint64_t eng_bytes_in;
49658 /* Count of data bytes out of the Engine. */
49659 uint64_t eng_bytes_out;
49661 * Count, in 4-byte (dword) units, of bytes
49662 * that are input as auxiliary data.
49663 * This includes the aux_cmd data.
49665 uint64_t aux_bytes_in;
49667 * Count, in 4-byte (dword) units, of bytes
49668 * that are output as auxiliary data.
49669 * This count is the buffer space for aux_data
49670 * output provided in the RQE, not the actual
49673 uint64_t aux_bytes_out;
49674 /* Count of number of commands executed. */
49677 * Count of number of error commands.
49678 * These are the commands with a
49679 * non-zero status value.
49681 uint64_t error_commands;
49683 * Compression/Encryption Engine usage,
49684 * the unit is count of clock cycles
49686 uint64_t cce_engine_usage;
49688 * De-Compression/De-cryption Engine usage,
49689 * the unit is count of clock cycles
49691 uint64_t cdd_engine_usage;
49694 /***********************
49695 * hwrm_stat_ctx_alloc *
49696 ***********************/
49699 /* hwrm_stat_ctx_alloc_input (size:256b/32B) */
49700 struct hwrm_stat_ctx_alloc_input {
49701 /* The HWRM command request type. */
49704 * The completion ring to send the completion event on. This should
49705 * be the NQ ID returned from the `nq_alloc` HWRM command.
49707 uint16_t cmpl_ring;
49709 * The sequence ID is used by the driver for tracking multiple
49710 * commands. This ID is treated as opaque data by the firmware and
49711 * the value is returned in the `hwrm_resp_hdr` upon completion.
49715 * The target ID of the command:
49716 * * 0x0-0xFFF8 - The function ID
49717 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
49718 * * 0xFFFD - Reserved for user-space HWRM interface
49721 uint16_t target_id;
49723 * A physical address pointer pointing to a host buffer that the
49724 * command's response data will be written. This can be either a host
49725 * physical address (HPA) or a guest physical address (GPA) and must
49726 * point to a physically contiguous block of memory.
49728 uint64_t resp_addr;
49730 * This is the address for statistic block.
49731 * > For new versions of the chip, this address should be 128B
49734 uint64_t stats_dma_addr;
49736 * The statistic block update period in ms.
49737 * e.g. 250ms, 500ms, 750ms, 1000ms.
49738 * If update_period_ms is 0, then the stats update
49739 * shall be never done and the DMA address shall not be used.
49740 * In this case, the stat block can only be read by
49741 * hwrm_stat_ctx_query command.
49742 * On Ethernet/L2 based devices:
49743 * if tpa v2 supported (hwrm_vnic_qcaps[max_aggs_supported]>0),
49744 * ctx_hw_stats_ext is used for DMA,
49746 * ctx_hw_stats is used for DMA.
49748 uint32_t update_period_ms;
49750 * This field is used to specify statistics context specific
49751 * configuration flags.
49753 uint8_t stat_ctx_flags;
49755 * When this bit is set to '1', the statistics context shall be
49756 * allocated for RoCE traffic only. In this case, traffic other
49757 * than offloaded RoCE traffic shall not be included in this
49758 * statistic context.
49759 * When this bit is set to '0', the statistics context shall be
49760 * used for network traffic or engine traffic.
49762 #define HWRM_STAT_CTX_ALLOC_INPUT_STAT_CTX_FLAGS_ROCE UINT32_C(0x1)
49765 * This is the size of the structure (ctx_hw_stats or
49766 * ctx_hw_stats_ext) that the driver has allocated to be used
49767 * for the periodic DMA updates.
49769 uint16_t stats_dma_length;
49772 /* hwrm_stat_ctx_alloc_output (size:128b/16B) */
49773 struct hwrm_stat_ctx_alloc_output {
49774 /* The specific error status for the command. */
49775 uint16_t error_code;
49776 /* The HWRM command request type. */
49778 /* The sequence ID from the original command. */
49780 /* The length of the response data in number of bytes. */
49782 /* This is the statistics context ID value. */
49783 uint32_t stat_ctx_id;
49784 uint8_t unused_0[3];
49786 * This field is used in Output records to indicate that the output
49787 * is completely written to RAM. This field should be read as '1'
49788 * to indicate that the output has been completely written.
49789 * When writing a command completion or response to an internal processor,
49790 * the order of writes has to be such that this field is written last.
49795 /**********************
49796 * hwrm_stat_ctx_free *
49797 **********************/
49800 /* hwrm_stat_ctx_free_input (size:192b/24B) */
49801 struct hwrm_stat_ctx_free_input {
49802 /* The HWRM command request type. */
49805 * The completion ring to send the completion event on. This should
49806 * be the NQ ID returned from the `nq_alloc` HWRM command.
49808 uint16_t cmpl_ring;
49810 * The sequence ID is used by the driver for tracking multiple
49811 * commands. This ID is treated as opaque data by the firmware and
49812 * the value is returned in the `hwrm_resp_hdr` upon completion.
49816 * The target ID of the command:
49817 * * 0x0-0xFFF8 - The function ID
49818 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
49819 * * 0xFFFD - Reserved for user-space HWRM interface
49822 uint16_t target_id;
49824 * A physical address pointer pointing to a host buffer that the
49825 * command's response data will be written. This can be either a host
49826 * physical address (HPA) or a guest physical address (GPA) and must
49827 * point to a physically contiguous block of memory.
49829 uint64_t resp_addr;
49830 /* ID of the statistics context that is being queried. */
49831 uint32_t stat_ctx_id;
49832 uint8_t unused_0[4];
49835 /* hwrm_stat_ctx_free_output (size:128b/16B) */
49836 struct hwrm_stat_ctx_free_output {
49837 /* The specific error status for the command. */
49838 uint16_t error_code;
49839 /* The HWRM command request type. */
49841 /* The sequence ID from the original command. */
49843 /* The length of the response data in number of bytes. */
49845 /* This is the statistics context ID value. */
49846 uint32_t stat_ctx_id;
49847 uint8_t unused_0[3];
49849 * This field is used in Output records to indicate that the output
49850 * is completely written to RAM. This field should be read as '1'
49851 * to indicate that the output has been completely written.
49852 * When writing a command completion or response to an internal processor,
49853 * the order of writes has to be such that this field is written last.
49858 /***********************
49859 * hwrm_stat_ctx_query *
49860 ***********************/
49863 /* hwrm_stat_ctx_query_input (size:192b/24B) */
49864 struct hwrm_stat_ctx_query_input {
49865 /* The HWRM command request type. */
49868 * The completion ring to send the completion event on. This should
49869 * be the NQ ID returned from the `nq_alloc` HWRM command.
49871 uint16_t cmpl_ring;
49873 * The sequence ID is used by the driver for tracking multiple
49874 * commands. This ID is treated as opaque data by the firmware and
49875 * the value is returned in the `hwrm_resp_hdr` upon completion.
49879 * The target ID of the command:
49880 * * 0x0-0xFFF8 - The function ID
49881 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
49882 * * 0xFFFD - Reserved for user-space HWRM interface
49885 uint16_t target_id;
49887 * A physical address pointer pointing to a host buffer that the
49888 * command's response data will be written. This can be either a host
49889 * physical address (HPA) or a guest physical address (GPA) and must
49890 * point to a physically contiguous block of memory.
49892 uint64_t resp_addr;
49893 /* ID of the statistics context that is being queried. */
49894 uint32_t stat_ctx_id;
49897 * This bit is set to 1 when request is for a counter mask,
49898 * representing the width of each of the stats counters, rather
49899 * than counters themselves.
49901 #define HWRM_STAT_CTX_QUERY_INPUT_FLAGS_COUNTER_MASK UINT32_C(0x1)
49902 uint8_t unused_0[3];
49905 /* hwrm_stat_ctx_query_output (size:1408b/176B) */
49906 struct hwrm_stat_ctx_query_output {
49907 /* The specific error status for the command. */
49908 uint16_t error_code;
49909 /* The HWRM command request type. */
49911 /* The sequence ID from the original command. */
49913 /* The length of the response data in number of bytes. */
49915 /* Number of transmitted unicast packets */
49916 uint64_t tx_ucast_pkts;
49917 /* Number of transmitted multicast packets */
49918 uint64_t tx_mcast_pkts;
49919 /* Number of transmitted broadcast packets */
49920 uint64_t tx_bcast_pkts;
49921 /* Number of packets discarded in transmit path */
49922 uint64_t tx_discard_pkts;
49923 /* Number of packets in transmit path with error */
49924 uint64_t tx_error_pkts;
49925 /* Number of transmitted bytes for unicast traffic */
49926 uint64_t tx_ucast_bytes;
49927 /* Number of transmitted bytes for multicast traffic */
49928 uint64_t tx_mcast_bytes;
49929 /* Number of transmitted bytes for broadcast traffic */
49930 uint64_t tx_bcast_bytes;
49931 /* Number of received unicast packets */
49932 uint64_t rx_ucast_pkts;
49933 /* Number of received multicast packets */
49934 uint64_t rx_mcast_pkts;
49935 /* Number of received broadcast packets */
49936 uint64_t rx_bcast_pkts;
49937 /* Number of packets discarded in receive path */
49938 uint64_t rx_discard_pkts;
49939 /* Number of packets in receive path with errors */
49940 uint64_t rx_error_pkts;
49941 /* Number of received bytes for unicast traffic */
49942 uint64_t rx_ucast_bytes;
49943 /* Number of received bytes for multicast traffic */
49944 uint64_t rx_mcast_bytes;
49945 /* Number of received bytes for broadcast traffic */
49946 uint64_t rx_bcast_bytes;
49947 /* Number of aggregated unicast packets */
49948 uint64_t rx_agg_pkts;
49949 /* Number of aggregated unicast bytes */
49950 uint64_t rx_agg_bytes;
49951 /* Number of aggregation events */
49952 uint64_t rx_agg_events;
49953 /* Number of aborted aggregations */
49954 uint64_t rx_agg_aborts;
49955 uint8_t unused_0[7];
49957 * This field is used in Output records to indicate that the output
49958 * is completely written to RAM. This field should be read as '1'
49959 * to indicate that the output has been completely written.
49960 * When writing a command completion or response to an internal processor,
49961 * the order of writes has to be such that this field is written last.
49966 /***************************
49967 * hwrm_stat_ext_ctx_query *
49968 ***************************/
49971 /* hwrm_stat_ext_ctx_query_input (size:192b/24B) */
49972 struct hwrm_stat_ext_ctx_query_input {
49973 /* The HWRM command request type. */
49976 * The completion ring to send the completion event on. This should
49977 * be the NQ ID returned from the `nq_alloc` HWRM command.
49979 uint16_t cmpl_ring;
49981 * The sequence ID is used by the driver for tracking multiple
49982 * commands. This ID is treated as opaque data by the firmware and
49983 * the value is returned in the `hwrm_resp_hdr` upon completion.
49987 * The target ID of the command:
49988 * * 0x0-0xFFF8 - The function ID
49989 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
49990 * * 0xFFFD - Reserved for user-space HWRM interface
49993 uint16_t target_id;
49995 * A physical address pointer pointing to a host buffer that the
49996 * command's response data will be written. This can be either a host
49997 * physical address (HPA) or a guest physical address (GPA) and must
49998 * point to a physically contiguous block of memory.
50000 uint64_t resp_addr;
50001 /* ID of the extended statistics context that is being queried. */
50002 uint32_t stat_ctx_id;
50005 * This bit is set to 1 when request is for a counter mask,
50006 * representing the width of each of the stats counters, rather
50007 * than counters themselves.
50009 #define HWRM_STAT_EXT_CTX_QUERY_INPUT_FLAGS_COUNTER_MASK \
50011 uint8_t unused_0[3];
50014 /* hwrm_stat_ext_ctx_query_output (size:1536b/192B) */
50015 struct hwrm_stat_ext_ctx_query_output {
50016 /* The specific error status for the command. */
50017 uint16_t error_code;
50018 /* The HWRM command request type. */
50020 /* The sequence ID from the original command. */
50022 /* The length of the response data in number of bytes. */
50024 /* Number of received unicast packets */
50025 uint64_t rx_ucast_pkts;
50026 /* Number of received multicast packets */
50027 uint64_t rx_mcast_pkts;
50028 /* Number of received broadcast packets */
50029 uint64_t rx_bcast_pkts;
50030 /* Number of discarded packets on receive path */
50031 uint64_t rx_discard_pkts;
50032 /* Number of packets on receive path with error */
50033 uint64_t rx_error_pkts;
50034 /* Number of received bytes for unicast traffic */
50035 uint64_t rx_ucast_bytes;
50036 /* Number of received bytes for multicast traffic */
50037 uint64_t rx_mcast_bytes;
50038 /* Number of received bytes for broadcast traffic */
50039 uint64_t rx_bcast_bytes;
50040 /* Number of transmitted unicast packets */
50041 uint64_t tx_ucast_pkts;
50042 /* Number of transmitted multicast packets */
50043 uint64_t tx_mcast_pkts;
50044 /* Number of transmitted broadcast packets */
50045 uint64_t tx_bcast_pkts;
50046 /* Number of packets on transmit path with error */
50047 uint64_t tx_error_pkts;
50048 /* Number of discarded packets on transmit path */
50049 uint64_t tx_discard_pkts;
50050 /* Number of transmitted bytes for unicast traffic */
50051 uint64_t tx_ucast_bytes;
50052 /* Number of transmitted bytes for multicast traffic */
50053 uint64_t tx_mcast_bytes;
50054 /* Number of transmitted bytes for broadcast traffic */
50055 uint64_t tx_bcast_bytes;
50056 /* Number of TPA eligible packets */
50057 uint64_t rx_tpa_eligible_pkt;
50058 /* Number of TPA eligible bytes */
50059 uint64_t rx_tpa_eligible_bytes;
50060 /* Number of TPA packets */
50061 uint64_t rx_tpa_pkt;
50062 /* Number of TPA bytes */
50063 uint64_t rx_tpa_bytes;
50064 /* Number of TPA errors */
50065 uint64_t rx_tpa_errors;
50066 /* Number of TPA events */
50067 uint64_t rx_tpa_events;
50068 uint8_t unused_0[7];
50070 * This field is used in Output records to indicate that the output
50071 * is completely written to RAM. This field should be read as '1'
50072 * to indicate that the output has been completely written.
50073 * When writing a command completion or response to an internal processor,
50074 * the order of writes has to be such that this field is written last.
50079 /***************************
50080 * hwrm_stat_ctx_eng_query *
50081 ***************************/
50084 /* hwrm_stat_ctx_eng_query_input (size:192b/24B) */
50085 struct hwrm_stat_ctx_eng_query_input {
50086 /* The HWRM command request type. */
50089 * The completion ring to send the completion event on. This should
50090 * be the NQ ID returned from the `nq_alloc` HWRM command.
50092 uint16_t cmpl_ring;
50094 * The sequence ID is used by the driver for tracking multiple
50095 * commands. This ID is treated as opaque data by the firmware and
50096 * the value is returned in the `hwrm_resp_hdr` upon completion.
50100 * The target ID of the command:
50101 * * 0x0-0xFFF8 - The function ID
50102 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
50103 * * 0xFFFD - Reserved for user-space HWRM interface
50106 uint16_t target_id;
50108 * A physical address pointer pointing to a host buffer that the
50109 * command's response data will be written. This can be either a host
50110 * physical address (HPA) or a guest physical address (GPA) and must
50111 * point to a physically contiguous block of memory.
50113 uint64_t resp_addr;
50114 /* ID of the statistics context that is being queried. */
50115 uint32_t stat_ctx_id;
50116 uint8_t unused_0[4];
50119 /* hwrm_stat_ctx_eng_query_output (size:640b/80B) */
50120 struct hwrm_stat_ctx_eng_query_output {
50121 /* The specific error status for the command. */
50122 uint16_t error_code;
50123 /* The HWRM command request type. */
50125 /* The sequence ID from the original command. */
50127 /* The length of the response data in number of bytes. */
50130 * Count of data bytes into the Engine.
50131 * This includes any user supplied prefix,
50132 * but does not include any predefined
50135 uint64_t eng_bytes_in;
50136 /* Count of data bytes out of the Engine. */
50137 uint64_t eng_bytes_out;
50139 * Count, in 4-byte (dword) units, of bytes
50140 * that are input as auxiliary data.
50141 * This includes the aux_cmd data.
50143 uint64_t aux_bytes_in;
50145 * Count, in 4-byte (dword) units, of bytes
50146 * that are output as auxiliary data.
50147 * This count is the buffer space for aux_data
50148 * output provided in the RQE, not the actual
50151 uint64_t aux_bytes_out;
50152 /* Count of number of commands executed. */
50155 * Count of number of error commands.
50156 * These are the commands with a
50157 * non-zero status value.
50159 uint64_t error_commands;
50161 * Compression/Encryption Engine usage,
50162 * the unit is count of clock cycles
50164 uint64_t cce_engine_usage;
50166 * De-Compression/De-cryption Engine usage,
50167 * the unit is count of clock cycles
50169 uint64_t cdd_engine_usage;
50170 uint8_t unused_0[7];
50172 * This field is used in Output records to indicate that the output
50173 * is completely written to RAM. This field should be read as '1'
50174 * to indicate that the output has been completely written.
50175 * When writing a command completion or response to an internal processor,
50176 * the order of writes has to be such that this field is written last.
50181 /***************************
50182 * hwrm_stat_ctx_clr_stats *
50183 ***************************/
50186 /* hwrm_stat_ctx_clr_stats_input (size:192b/24B) */
50187 struct hwrm_stat_ctx_clr_stats_input {
50188 /* The HWRM command request type. */
50191 * The completion ring to send the completion event on. This should
50192 * be the NQ ID returned from the `nq_alloc` HWRM command.
50194 uint16_t cmpl_ring;
50196 * The sequence ID is used by the driver for tracking multiple
50197 * commands. This ID is treated as opaque data by the firmware and
50198 * the value is returned in the `hwrm_resp_hdr` upon completion.
50202 * The target ID of the command:
50203 * * 0x0-0xFFF8 - The function ID
50204 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
50205 * * 0xFFFD - Reserved for user-space HWRM interface
50208 uint16_t target_id;
50210 * A physical address pointer pointing to a host buffer that the
50211 * command's response data will be written. This can be either a host
50212 * physical address (HPA) or a guest physical address (GPA) and must
50213 * point to a physically contiguous block of memory.
50215 uint64_t resp_addr;
50216 /* ID of the statistics context that is being queried. */
50217 uint32_t stat_ctx_id;
50218 uint8_t unused_0[4];
50221 /* hwrm_stat_ctx_clr_stats_output (size:128b/16B) */
50222 struct hwrm_stat_ctx_clr_stats_output {
50223 /* The specific error status for the command. */
50224 uint16_t error_code;
50225 /* The HWRM command request type. */
50227 /* The sequence ID from the original command. */
50229 /* The length of the response data in number of bytes. */
50231 uint8_t unused_0[7];
50233 * This field is used in Output records to indicate that the output
50234 * is completely written to RAM. This field should be read as '1'
50235 * to indicate that the output has been completely written.
50236 * When writing a command completion or response to an internal processor,
50237 * the order of writes has to be such that this field is written last.
50242 /********************
50243 * hwrm_pcie_qstats *
50244 ********************/
50247 /* hwrm_pcie_qstats_input (size:256b/32B) */
50248 struct hwrm_pcie_qstats_input {
50249 /* The HWRM command request type. */
50252 * The completion ring to send the completion event on. This should
50253 * be the NQ ID returned from the `nq_alloc` HWRM command.
50255 uint16_t cmpl_ring;
50257 * The sequence ID is used by the driver for tracking multiple
50258 * commands. This ID is treated as opaque data by the firmware and
50259 * the value is returned in the `hwrm_resp_hdr` upon completion.
50263 * The target ID of the command:
50264 * * 0x0-0xFFF8 - The function ID
50265 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
50266 * * 0xFFFD - Reserved for user-space HWRM interface
50269 uint16_t target_id;
50271 * A physical address pointer pointing to a host buffer that the
50272 * command's response data will be written. This can be either a host
50273 * physical address (HPA) or a guest physical address (GPA) and must
50274 * point to a physically contiguous block of memory.
50276 uint64_t resp_addr;
50278 * The size of PCIe statistics block in bytes.
50279 * Firmware will DMA the PCIe statistics to
50280 * the host with this field size in the response.
50282 uint16_t pcie_stat_size;
50283 uint8_t unused_0[6];
50285 * This is the host address where
50286 * PCIe statistics will be stored
50288 uint64_t pcie_stat_host_addr;
50291 /* hwrm_pcie_qstats_output (size:128b/16B) */
50292 struct hwrm_pcie_qstats_output {
50293 /* The specific error status for the command. */
50294 uint16_t error_code;
50295 /* The HWRM command request type. */
50297 /* The sequence ID from the original command. */
50299 /* The length of the response data in number of bytes. */
50301 /* The size of PCIe statistics block in bytes. */
50302 uint16_t pcie_stat_size;
50303 uint8_t unused_0[5];
50305 * This field is used in Output records to indicate that the output
50306 * is completely written to RAM. This field should be read as '1'
50307 * to indicate that the output has been completely written.
50308 * When writing a command completion or response to an internal processor,
50309 * the order of writes has to be such that this field is written last.
50314 /* PCIe Statistics Formats */
50315 /* pcie_ctx_hw_stats (size:768b/96B) */
50316 struct pcie_ctx_hw_stats {
50317 /* Number of physical layer receiver errors */
50318 uint64_t pcie_pl_signal_integrity;
50319 /* Number of DLLP CRC errors detected by Data Link Layer */
50320 uint64_t pcie_dl_signal_integrity;
50322 * Number of TLP LCRC and sequence number errors detected
50323 * by Data Link Layer
50325 uint64_t pcie_tl_signal_integrity;
50326 /* Number of times LTSSM entered Recovery state */
50327 uint64_t pcie_link_integrity;
50328 /* Report number of TLP bits that have been transmitted in Mbps */
50329 uint64_t pcie_tx_traffic_rate;
50330 /* Report number of TLP bits that have been received in Mbps */
50331 uint64_t pcie_rx_traffic_rate;
50332 /* Number of DLLP bytes that have been transmitted */
50333 uint64_t pcie_tx_dllp_statistics;
50334 /* Number of DLLP bytes that have been received */
50335 uint64_t pcie_rx_dllp_statistics;
50337 * Number of times spent in each phase of gen3
50340 uint64_t pcie_equalization_time;
50341 /* Records the last 16 transitions of the LTSSM */
50342 uint32_t pcie_ltssm_histogram[4];
50344 * Record the last 8 reasons on why LTSSM transitioned
50347 uint64_t pcie_recovery_histogram;
50350 /**********************
50351 * hwrm_exec_fwd_resp *
50352 **********************/
50355 /* hwrm_exec_fwd_resp_input (size:1024b/128B) */
50356 struct hwrm_exec_fwd_resp_input {
50357 /* The HWRM command request type. */
50360 * The completion ring to send the completion event on. This should
50361 * be the NQ ID returned from the `nq_alloc` HWRM command.
50363 uint16_t cmpl_ring;
50365 * The sequence ID is used by the driver for tracking multiple
50366 * commands. This ID is treated as opaque data by the firmware and
50367 * the value is returned in the `hwrm_resp_hdr` upon completion.
50371 * The target ID of the command:
50372 * * 0x0-0xFFF8 - The function ID
50373 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
50374 * * 0xFFFD - Reserved for user-space HWRM interface
50377 uint16_t target_id;
50379 * A physical address pointer pointing to a host buffer that the
50380 * command's response data will be written. This can be either a host
50381 * physical address (HPA) or a guest physical address (GPA) and must
50382 * point to a physically contiguous block of memory.
50384 uint64_t resp_addr;
50386 * This is an encapsulated request. This request should
50387 * be executed by the HWRM and the response should be
50388 * provided in the response buffer inside the encapsulated
50391 uint32_t encap_request[26];
50393 * This value indicates the target id of the response to
50394 * the encapsulated request.
50395 * 0x0 - 0xFFF8 - Used for function ids
50396 * 0xFFF8 - 0xFFFE - Reserved for internal processors
50399 uint16_t encap_resp_target_id;
50400 uint8_t unused_0[6];
50403 /* hwrm_exec_fwd_resp_output (size:128b/16B) */
50404 struct hwrm_exec_fwd_resp_output {
50405 /* The specific error status for the command. */
50406 uint16_t error_code;
50407 /* The HWRM command request type. */
50409 /* The sequence ID from the original command. */
50411 /* The length of the response data in number of bytes. */
50413 uint8_t unused_0[7];
50415 * This field is used in Output records to indicate that the output
50416 * is completely written to RAM. This field should be read as '1'
50417 * to indicate that the output has been completely written.
50418 * When writing a command completion or response to an internal processor,
50419 * the order of writes has to be such that this field is written last.
50424 /************************
50425 * hwrm_reject_fwd_resp *
50426 ************************/
50429 /* hwrm_reject_fwd_resp_input (size:1024b/128B) */
50430 struct hwrm_reject_fwd_resp_input {
50431 /* The HWRM command request type. */
50434 * The completion ring to send the completion event on. This should
50435 * be the NQ ID returned from the `nq_alloc` HWRM command.
50437 uint16_t cmpl_ring;
50439 * The sequence ID is used by the driver for tracking multiple
50440 * commands. This ID is treated as opaque data by the firmware and
50441 * the value is returned in the `hwrm_resp_hdr` upon completion.
50445 * The target ID of the command:
50446 * * 0x0-0xFFF8 - The function ID
50447 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
50448 * * 0xFFFD - Reserved for user-space HWRM interface
50451 uint16_t target_id;
50453 * A physical address pointer pointing to a host buffer that the
50454 * command's response data will be written. This can be either a host
50455 * physical address (HPA) or a guest physical address (GPA) and must
50456 * point to a physically contiguous block of memory.
50458 uint64_t resp_addr;
50460 * This is an encapsulated request. This request should
50461 * be rejected by the HWRM and the error response should be
50462 * provided in the response buffer inside the encapsulated
50465 uint32_t encap_request[26];
50467 * This value indicates the target id of the response to
50468 * the encapsulated request.
50469 * 0x0 - 0xFFF8 - Used for function ids
50470 * 0xFFF8 - 0xFFFE - Reserved for internal processors
50473 uint16_t encap_resp_target_id;
50474 uint8_t unused_0[6];
50477 /* hwrm_reject_fwd_resp_output (size:128b/16B) */
50478 struct hwrm_reject_fwd_resp_output {
50479 /* The specific error status for the command. */
50480 uint16_t error_code;
50481 /* The HWRM command request type. */
50483 /* The sequence ID from the original command. */
50485 /* The length of the response data in number of bytes. */
50487 uint8_t unused_0[7];
50489 * This field is used in Output records to indicate that the output
50490 * is completely written to RAM. This field should be read as '1'
50491 * to indicate that the output has been completely written.
50492 * When writing a command completion or response to an internal processor,
50493 * the order of writes has to be such that this field is written last.
50503 /* hwrm_fwd_resp_input (size:1024b/128B) */
50504 struct hwrm_fwd_resp_input {
50505 /* The HWRM command request type. */
50508 * The completion ring to send the completion event on. This should
50509 * be the NQ ID returned from the `nq_alloc` HWRM command.
50511 uint16_t cmpl_ring;
50513 * The sequence ID is used by the driver for tracking multiple
50514 * commands. This ID is treated as opaque data by the firmware and
50515 * the value is returned in the `hwrm_resp_hdr` upon completion.
50519 * The target ID of the command:
50520 * * 0x0-0xFFF8 - The function ID
50521 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
50522 * * 0xFFFD - Reserved for user-space HWRM interface
50525 uint16_t target_id;
50527 * A physical address pointer pointing to a host buffer that the
50528 * command's response data will be written. This can be either a host
50529 * physical address (HPA) or a guest physical address (GPA) and must
50530 * point to a physically contiguous block of memory.
50532 uint64_t resp_addr;
50534 * This value indicates the target id of the encapsulated
50536 * 0x0 - 0xFFF8 - Used for function ids
50537 * 0xFFF8 - 0xFFFE - Reserved for internal processors
50540 uint16_t encap_resp_target_id;
50542 * This value indicates the completion ring the encapsulated
50543 * response will be optionally completed on. If the value is
50544 * -1, then no CR completion shall be generated for the
50545 * encapsulated response. Any other value must be a
50546 * valid CR ring_id value. If a valid encap_resp_cmpl_ring
50547 * is provided, then a CR completion shall be generated for
50548 * the encapsulated response.
50550 uint16_t encap_resp_cmpl_ring;
50551 /* This field indicates the length of encapsulated response. */
50552 uint16_t encap_resp_len;
50556 * This is the host address where the encapsulated response
50558 * This area must be 16B aligned and must be cleared to zero
50559 * before the original request is made.
50561 uint64_t encap_resp_addr;
50562 /* This is an encapsulated response. */
50563 uint32_t encap_resp[24];
50566 /* hwrm_fwd_resp_output (size:128b/16B) */
50567 struct hwrm_fwd_resp_output {
50568 /* The specific error status for the command. */
50569 uint16_t error_code;
50570 /* The HWRM command request type. */
50572 /* The sequence ID from the original command. */
50574 /* The length of the response data in number of bytes. */
50576 uint8_t unused_0[7];
50578 * This field is used in Output records to indicate that the output
50579 * is completely written to RAM. This field should be read as '1'
50580 * to indicate that the output has been completely written.
50581 * When writing a command completion or response to an internal processor,
50582 * the order of writes has to be such that this field is written last.
50587 /*****************************
50588 * hwrm_fwd_async_event_cmpl *
50589 *****************************/
50592 /* hwrm_fwd_async_event_cmpl_input (size:320b/40B) */
50593 struct hwrm_fwd_async_event_cmpl_input {
50594 /* The HWRM command request type. */
50597 * The completion ring to send the completion event on. This should
50598 * be the NQ ID returned from the `nq_alloc` HWRM command.
50600 uint16_t cmpl_ring;
50602 * The sequence ID is used by the driver for tracking multiple
50603 * commands. This ID is treated as opaque data by the firmware and
50604 * the value is returned in the `hwrm_resp_hdr` upon completion.
50608 * The target ID of the command:
50609 * * 0x0-0xFFF8 - The function ID
50610 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
50611 * * 0xFFFD - Reserved for user-space HWRM interface
50614 uint16_t target_id;
50616 * A physical address pointer pointing to a host buffer that the
50617 * command's response data will be written. This can be either a host
50618 * physical address (HPA) or a guest physical address (GPA) and must
50619 * point to a physically contiguous block of memory.
50621 uint64_t resp_addr;
50623 * This value indicates the target id of the encapsulated
50624 * asynchronous event.
50625 * 0x0 - 0xFFF8 - Used for function ids
50626 * 0xFFF8 - 0xFFFE - Reserved for internal processors
50627 * 0xFFFF - Broadcast to all children VFs (only applicable when
50628 * a PF is the requester)
50630 uint16_t encap_async_event_target_id;
50631 uint8_t unused_0[6];
50632 /* This is an encapsulated asynchronous event completion. */
50633 uint32_t encap_async_event_cmpl[4];
50636 /* hwrm_fwd_async_event_cmpl_output (size:128b/16B) */
50637 struct hwrm_fwd_async_event_cmpl_output {
50638 /* The specific error status for the command. */
50639 uint16_t error_code;
50640 /* The HWRM command request type. */
50642 /* The sequence ID from the original command. */
50644 /* The length of the response data in number of bytes. */
50646 uint8_t unused_0[7];
50648 * This field is used in Output records to indicate that the output
50649 * is completely written to RAM. This field should be read as '1'
50650 * to indicate that the output has been completely written.
50651 * When writing a command completion or response to an internal processor,
50652 * the order of writes has to be such that this field is written last.
50657 /**************************
50658 * hwrm_nvm_raw_write_blk *
50659 **************************/
50662 /* hwrm_nvm_raw_write_blk_input (size:256b/32B) */
50663 struct hwrm_nvm_raw_write_blk_input {
50664 /* The HWRM command request type. */
50667 * The completion ring to send the completion event on. This should
50668 * be the NQ ID returned from the `nq_alloc` HWRM command.
50670 uint16_t cmpl_ring;
50672 * The sequence ID is used by the driver for tracking multiple
50673 * commands. This ID is treated as opaque data by the firmware and
50674 * the value is returned in the `hwrm_resp_hdr` upon completion.
50678 * The target ID of the command:
50679 * * 0x0-0xFFF8 - The function ID
50680 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
50681 * * 0xFFFD - Reserved for user-space HWRM interface
50684 uint16_t target_id;
50686 * A physical address pointer pointing to a host buffer that the
50687 * command's response data will be written. This can be either a host
50688 * physical address (HPA) or a guest physical address (GPA) and must
50689 * point to a physically contiguous block of memory.
50691 uint64_t resp_addr;
50693 * 64-bit Host Source Address.
50694 * This is the location of the source data to be written.
50696 uint64_t host_src_addr;
50698 * 32-bit Destination Address.
50699 * This is the NVRAM byte-offset where the source data will be written to.
50701 uint32_t dest_addr;
50702 /* Length of data to be written, in bytes. */
50706 /* hwrm_nvm_raw_write_blk_output (size:128b/16B) */
50707 struct hwrm_nvm_raw_write_blk_output {
50708 /* The specific error status for the command. */
50709 uint16_t error_code;
50710 /* The HWRM command request type. */
50712 /* The sequence ID from the original command. */
50714 /* The length of the response data in number of bytes. */
50716 uint8_t unused_0[7];
50718 * This field is used in Output records to indicate that the output
50719 * is completely written to RAM. This field should be read as '1'
50720 * to indicate that the output has been completely written.
50721 * When writing a command completion or response to an internal processor,
50722 * the order of writes has to be such that this field is written last.
50732 /* hwrm_nvm_read_input (size:320b/40B) */
50733 struct hwrm_nvm_read_input {
50734 /* The HWRM command request type. */
50737 * The completion ring to send the completion event on. This should
50738 * be the NQ ID returned from the `nq_alloc` HWRM command.
50740 uint16_t cmpl_ring;
50742 * The sequence ID is used by the driver for tracking multiple
50743 * commands. This ID is treated as opaque data by the firmware and
50744 * the value is returned in the `hwrm_resp_hdr` upon completion.
50748 * The target ID of the command:
50749 * * 0x0-0xFFF8 - The function ID
50750 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
50751 * * 0xFFFD - Reserved for user-space HWRM interface
50754 uint16_t target_id;
50756 * A physical address pointer pointing to a host buffer that the
50757 * command's response data will be written. This can be either a host
50758 * physical address (HPA) or a guest physical address (GPA) and must
50759 * point to a physically contiguous block of memory.
50761 uint64_t resp_addr;
50763 * 64-bit Host Destination Address.
50764 * This is the host address where the data will be written to.
50766 uint64_t host_dest_addr;
50767 /* The 0-based index of the directory entry. */
50769 uint8_t unused_0[2];
50770 /* The NVRAM byte-offset to read from. */
50772 /* The length of the data to be read, in bytes. */
50774 uint8_t unused_1[4];
50777 /* hwrm_nvm_read_output (size:128b/16B) */
50778 struct hwrm_nvm_read_output {
50779 /* The specific error status for the command. */
50780 uint16_t error_code;
50781 /* The HWRM command request type. */
50783 /* The sequence ID from the original command. */
50785 /* The length of the response data in number of bytes. */
50787 uint8_t unused_0[7];
50789 * This field is used in Output records to indicate that the output
50790 * is completely written to RAM. This field should be read as '1'
50791 * to indicate that the output has been completely written.
50792 * When writing a command completion or response to an internal processor,
50793 * the order of writes has to be such that this field is written last.
50798 /*********************
50799 * hwrm_nvm_raw_dump *
50800 *********************/
50803 /* hwrm_nvm_raw_dump_input (size:256b/32B) */
50804 struct hwrm_nvm_raw_dump_input {
50805 /* The HWRM command request type. */
50808 * The completion ring to send the completion event on. This should
50809 * be the NQ ID returned from the `nq_alloc` HWRM command.
50811 uint16_t cmpl_ring;
50813 * The sequence ID is used by the driver for tracking multiple
50814 * commands. This ID is treated as opaque data by the firmware and
50815 * the value is returned in the `hwrm_resp_hdr` upon completion.
50819 * The target ID of the command:
50820 * * 0x0-0xFFF8 - The function ID
50821 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
50822 * * 0xFFFD - Reserved for user-space HWRM interface
50825 uint16_t target_id;
50827 * A physical address pointer pointing to a host buffer that the
50828 * command's response data will be written. This can be either a host
50829 * physical address (HPA) or a guest physical address (GPA) and must
50830 * point to a physically contiguous block of memory.
50832 uint64_t resp_addr;
50834 * 64-bit Host Destination Address.
50835 * This is the host address where the data will be written to.
50837 uint64_t host_dest_addr;
50838 /* 32-bit NVRAM byte-offset to read from. */
50840 /* Total length of NVRAM contents to be read, in bytes. */
50844 /* hwrm_nvm_raw_dump_output (size:128b/16B) */
50845 struct hwrm_nvm_raw_dump_output {
50846 /* The specific error status for the command. */
50847 uint16_t error_code;
50848 /* The HWRM command request type. */
50850 /* The sequence ID from the original command. */
50852 /* The length of the response data in number of bytes. */
50854 uint8_t unused_0[7];
50856 * This field is used in Output records to indicate that the output
50857 * is completely written to RAM. This field should be read as '1'
50858 * to indicate that the output has been completely written.
50859 * When writing a command completion or response to an internal processor,
50860 * the order of writes has to be such that this field is written last.
50865 /****************************
50866 * hwrm_nvm_get_dir_entries *
50867 ****************************/
50870 /* hwrm_nvm_get_dir_entries_input (size:192b/24B) */
50871 struct hwrm_nvm_get_dir_entries_input {
50872 /* The HWRM command request type. */
50875 * The completion ring to send the completion event on. This should
50876 * be the NQ ID returned from the `nq_alloc` HWRM command.
50878 uint16_t cmpl_ring;
50880 * The sequence ID is used by the driver for tracking multiple
50881 * commands. This ID is treated as opaque data by the firmware and
50882 * the value is returned in the `hwrm_resp_hdr` upon completion.
50886 * The target ID of the command:
50887 * * 0x0-0xFFF8 - The function ID
50888 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
50889 * * 0xFFFD - Reserved for user-space HWRM interface
50892 uint16_t target_id;
50894 * A physical address pointer pointing to a host buffer that the
50895 * command's response data will be written. This can be either a host
50896 * physical address (HPA) or a guest physical address (GPA) and must
50897 * point to a physically contiguous block of memory.
50899 uint64_t resp_addr;
50901 * 64-bit Host Destination Address.
50902 * This is the host address where the directory will be written.
50904 uint64_t host_dest_addr;
50907 /* hwrm_nvm_get_dir_entries_output (size:128b/16B) */
50908 struct hwrm_nvm_get_dir_entries_output {
50909 /* The specific error status for the command. */
50910 uint16_t error_code;
50911 /* The HWRM command request type. */
50913 /* The sequence ID from the original command. */
50915 /* The length of the response data in number of bytes. */
50917 uint8_t unused_0[7];
50919 * This field is used in Output records to indicate that the output
50920 * is completely written to RAM. This field should be read as '1'
50921 * to indicate that the output has been completely written.
50922 * When writing a command completion or response to an internal processor,
50923 * the order of writes has to be such that this field is written last.
50928 /*************************
50929 * hwrm_nvm_get_dir_info *
50930 *************************/
50933 /* hwrm_nvm_get_dir_info_input (size:128b/16B) */
50934 struct hwrm_nvm_get_dir_info_input {
50935 /* The HWRM command request type. */
50938 * The completion ring to send the completion event on. This should
50939 * be the NQ ID returned from the `nq_alloc` HWRM command.
50941 uint16_t cmpl_ring;
50943 * The sequence ID is used by the driver for tracking multiple
50944 * commands. This ID is treated as opaque data by the firmware and
50945 * the value is returned in the `hwrm_resp_hdr` upon completion.
50949 * The target ID of the command:
50950 * * 0x0-0xFFF8 - The function ID
50951 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
50952 * * 0xFFFD - Reserved for user-space HWRM interface
50955 uint16_t target_id;
50957 * A physical address pointer pointing to a host buffer that the
50958 * command's response data will be written. This can be either a host
50959 * physical address (HPA) or a guest physical address (GPA) and must
50960 * point to a physically contiguous block of memory.
50962 uint64_t resp_addr;
50965 /* hwrm_nvm_get_dir_info_output (size:192b/24B) */
50966 struct hwrm_nvm_get_dir_info_output {
50967 /* The specific error status for the command. */
50968 uint16_t error_code;
50969 /* The HWRM command request type. */
50971 /* The sequence ID from the original command. */
50973 /* The length of the response data in number of bytes. */
50975 /* Number of directory entries in the directory. */
50977 /* Size of each directory entry, in bytes. */
50978 uint32_t entry_length;
50979 uint8_t unused_0[7];
50981 * This field is used in Output records to indicate that the output
50982 * is completely written to RAM. This field should be read as '1'
50983 * to indicate that the output has been completely written.
50984 * When writing a command completion or response to an internal processor,
50985 * the order of writes has to be such that this field is written last.
50990 /******************
50992 ******************/
50995 /* hwrm_nvm_write_input (size:448b/56B) */
50996 struct hwrm_nvm_write_input {
50997 /* The HWRM command request type. */
51000 * The completion ring to send the completion event on. This should
51001 * be the NQ ID returned from the `nq_alloc` HWRM command.
51003 uint16_t cmpl_ring;
51005 * The sequence ID is used by the driver for tracking multiple
51006 * commands. This ID is treated as opaque data by the firmware and
51007 * the value is returned in the `hwrm_resp_hdr` upon completion.
51011 * The target ID of the command:
51012 * * 0x0-0xFFF8 - The function ID
51013 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
51014 * * 0xFFFD - Reserved for user-space HWRM interface
51017 uint16_t target_id;
51019 * A physical address pointer pointing to a host buffer that the
51020 * command's response data will be written. This can be either a host
51021 * physical address (HPA) or a guest physical address (GPA) and must
51022 * point to a physically contiguous block of memory.
51024 uint64_t resp_addr;
51026 * 64-bit Host Source Address.
51027 * This is where the source data is.
51029 uint64_t host_src_addr;
51031 * The Directory Entry Type (valid values are defined in the
51032 * bnxnvm_directory_type enum defined in the file bnxnvm_defs.h).
51036 * Directory ordinal.
51037 * The 0-based instance of the combined Directory Entry Type and Extension.
51039 uint16_t dir_ordinal;
51041 * The Directory Entry Extension flags (see BNX_DIR_EXT_* in the file
51046 * Directory Entry Attribute flags (see BNX_DIR_ATTR_* in the file
51051 * Length of data to write, in bytes. May be less than or equal to the
51052 * allocated size for the directory entry.
51053 * The data length stored in the directory entry will be updated to
51054 * reflect this value once the write is complete.
51056 uint32_t dir_data_length;
51061 * When this bit is '1', the original active image
51062 * will not be removed. TBD: what purpose is this?
51064 #define HWRM_NVM_WRITE_INPUT_FLAGS_KEEP_ORIG_ACTIVE_IMG \
51067 * This flag indicates the sender wants to modify a continuous
51068 * NVRAM area using a batch of this HWRM requests. The
51069 * offset of a request must be continuous to the end of previous
51070 * request's. Firmware does not update the directory entry until
51071 * receiving the last request, which is indicated by the batch_last
51072 * flag. This flag is set usually when a sender does not have a
51073 * block of memory that is big enough to hold the entire NVRAM
51074 * data for send at one time.
51076 #define HWRM_NVM_WRITE_INPUT_FLAGS_BATCH_MODE \
51079 * This flag can be used only when the batch_mode flag is set. It
51080 * indicates this request is the last of batch requests.
51082 #define HWRM_NVM_WRITE_INPUT_FLAGS_BATCH_LAST \
51085 * The requested length of the allocated NVM for the item, in bytes.
51086 * This value may be greater than or equal to the specified data
51087 * length (dir_data_length).
51088 * If this value is less than the specified data length, it will be ignored.
51089 * The response will contain the actual allocated item length,
51090 * which may be greater than the requested item length.
51091 * The purpose for allocating more than the required number of bytes
51092 * for an item's data is to pre-allocate extra storage (padding) to
51093 * accommodate the potential future growth of an item (e.g. upgraded
51094 * firmware with a size increase, log growth, expanded configuration data).
51096 uint32_t dir_item_length;
51098 * 32-bit offset of data blob from where data is being written.
51099 * Only valid for batch mode. For non-batch writes 'dont care'.
51103 * Length of data to be written.Should be non-zero.
51104 * Only valid for batch mode. For non-batch writes 'dont care'.
51110 /* hwrm_nvm_write_output (size:128b/16B) */
51111 struct hwrm_nvm_write_output {
51112 /* The specific error status for the command. */
51113 uint16_t error_code;
51114 /* The HWRM command request type. */
51116 /* The sequence ID from the original command. */
51118 /* The length of the response data in number of bytes. */
51121 * Length of the allocated NVM for the item, in bytes. The value may be
51122 * greater than or equal to the specified data length or the requested
51124 * The actual item length used when creating a new directory entry will
51125 * be a multiple of an NVM block size.
51127 uint32_t dir_item_length;
51128 /* The directory index of the created or modified item. */
51132 * This field is used in Output records to indicate that the output
51133 * is completely written to RAM. This field should be read as '1'
51134 * to indicate that the output has been completely written.
51135 * When writing a command completion or response to an internal processor,
51136 * the order of writes has to be such that this field is written last.
51141 /* hwrm_nvm_write_cmd_err (size:64b/8B) */
51142 struct hwrm_nvm_write_cmd_err {
51144 * command specific error codes that goes to
51145 * the cmd_err field in Common HWRM Error Response.
51148 /* Unknown error */
51149 #define HWRM_NVM_WRITE_CMD_ERR_CODE_UNKNOWN UINT32_C(0x0)
51150 /* Unable to complete operation due to fragmentation */
51151 #define HWRM_NVM_WRITE_CMD_ERR_CODE_FRAG_ERR UINT32_C(0x1)
51152 /* nvm is completely full. */
51153 #define HWRM_NVM_WRITE_CMD_ERR_CODE_NO_SPACE UINT32_C(0x2)
51154 #define HWRM_NVM_WRITE_CMD_ERR_CODE_LAST \
51155 HWRM_NVM_WRITE_CMD_ERR_CODE_NO_SPACE
51156 uint8_t unused_0[7];
51159 /*******************
51160 * hwrm_nvm_modify *
51161 *******************/
51164 /* hwrm_nvm_modify_input (size:320b/40B) */
51165 struct hwrm_nvm_modify_input {
51166 /* The HWRM command request type. */
51169 * The completion ring to send the completion event on. This should
51170 * be the NQ ID returned from the `nq_alloc` HWRM command.
51172 uint16_t cmpl_ring;
51174 * The sequence ID is used by the driver for tracking multiple
51175 * commands. This ID is treated as opaque data by the firmware and
51176 * the value is returned in the `hwrm_resp_hdr` upon completion.
51180 * The target ID of the command:
51181 * * 0x0-0xFFF8 - The function ID
51182 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
51183 * * 0xFFFD - Reserved for user-space HWRM interface
51186 uint16_t target_id;
51188 * A physical address pointer pointing to a host buffer that the
51189 * command's response data will be written. This can be either a host
51190 * physical address (HPA) or a guest physical address (GPA) and must
51191 * point to a physically contiguous block of memory.
51193 uint64_t resp_addr;
51195 * 64-bit Host Source Address.
51196 * This is where the modified data is.
51198 uint64_t host_src_addr;
51199 /* 16-bit directory entry index. */
51203 * This flag indicates the sender wants to modify a continuous NVRAM
51204 * area using a batch of this HWRM requests. The offset of a request
51205 * must be continuous to the end of previous request's. Firmware does
51206 * not update the directory entry until receiving the last request,
51207 * which is indicated by the batch_last flag.
51208 * This flag is set usually when a sender does not have a block of
51209 * memory that is big enough to hold the entire NVRAM data for send
51212 #define HWRM_NVM_MODIFY_INPUT_FLAGS_BATCH_MODE UINT32_C(0x1)
51214 * This flag can be used only when the batch_mode flag is set.
51215 * It indicates this request is the last of batch requests.
51217 #define HWRM_NVM_MODIFY_INPUT_FLAGS_BATCH_LAST UINT32_C(0x2)
51218 /* 32-bit NVRAM byte-offset to modify content from. */
51221 * Length of data to be modified, in bytes. The length shall
51225 uint8_t unused_1[4];
51228 /* hwrm_nvm_modify_output (size:128b/16B) */
51229 struct hwrm_nvm_modify_output {
51230 /* The specific error status for the command. */
51231 uint16_t error_code;
51232 /* The HWRM command request type. */
51234 /* The sequence ID from the original command. */
51236 /* The length of the response data in number of bytes. */
51238 uint8_t unused_0[7];
51240 * This field is used in Output records to indicate that the output
51241 * is completely written to RAM. This field should be read as '1'
51242 * to indicate that the output has been completely written.
51243 * When writing a command completion or response to an internal processor,
51244 * the order of writes has to be such that this field is written last.
51249 /***************************
51250 * hwrm_nvm_find_dir_entry *
51251 ***************************/
51254 /* hwrm_nvm_find_dir_entry_input (size:256b/32B) */
51255 struct hwrm_nvm_find_dir_entry_input {
51256 /* The HWRM command request type. */
51259 * The completion ring to send the completion event on. This should
51260 * be the NQ ID returned from the `nq_alloc` HWRM command.
51262 uint16_t cmpl_ring;
51264 * The sequence ID is used by the driver for tracking multiple
51265 * commands. This ID is treated as opaque data by the firmware and
51266 * the value is returned in the `hwrm_resp_hdr` upon completion.
51270 * The target ID of the command:
51271 * * 0x0-0xFFF8 - The function ID
51272 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
51273 * * 0xFFFD - Reserved for user-space HWRM interface
51276 uint16_t target_id;
51278 * A physical address pointer pointing to a host buffer that the
51279 * command's response data will be written. This can be either a host
51280 * physical address (HPA) or a guest physical address (GPA) and must
51281 * point to a physically contiguous block of memory.
51283 uint64_t resp_addr;
51286 * This bit must be '1' for the dir_idx_valid field to be
51289 #define HWRM_NVM_FIND_DIR_ENTRY_INPUT_ENABLES_DIR_IDX_VALID \
51291 /* Directory Entry Index */
51293 /* Directory Entry (Image) Type */
51296 * Directory ordinal.
51297 * The instance of this Directory Type
51299 uint16_t dir_ordinal;
51300 /* The Directory Entry Extension flags. */
51302 /* This value indicates the search option using dir_ordinal. */
51303 uint8_t opt_ordinal;
51304 /* This value indicates the search option using dir_ordinal. */
51305 #define HWRM_NVM_FIND_DIR_ENTRY_INPUT_OPT_ORDINAL_MASK UINT32_C(0x3)
51306 #define HWRM_NVM_FIND_DIR_ENTRY_INPUT_OPT_ORDINAL_SFT 0
51307 /* Equal to specified ordinal value. */
51308 #define HWRM_NVM_FIND_DIR_ENTRY_INPUT_OPT_ORDINAL_EQ UINT32_C(0x0)
51309 /* Greater than or equal to specified ordinal value */
51310 #define HWRM_NVM_FIND_DIR_ENTRY_INPUT_OPT_ORDINAL_GE UINT32_C(0x1)
51311 /* Greater than specified ordinal value */
51312 #define HWRM_NVM_FIND_DIR_ENTRY_INPUT_OPT_ORDINAL_GT UINT32_C(0x2)
51313 #define HWRM_NVM_FIND_DIR_ENTRY_INPUT_OPT_ORDINAL_LAST \
51314 HWRM_NVM_FIND_DIR_ENTRY_INPUT_OPT_ORDINAL_GT
51315 uint8_t unused_0[3];
51318 /* hwrm_nvm_find_dir_entry_output (size:256b/32B) */
51319 struct hwrm_nvm_find_dir_entry_output {
51320 /* The specific error status for the command. */
51321 uint16_t error_code;
51322 /* The HWRM command request type. */
51324 /* The sequence ID from the original command. */
51326 /* The length of the response data in number of bytes. */
51328 /* Allocated NVRAM for this directory entry, in bytes. */
51329 uint32_t dir_item_length;
51330 /* Size of the stored data for this directory entry, in bytes. */
51331 uint32_t dir_data_length;
51333 * Firmware version.
51334 * Only valid if the directory entry is for embedded firmware stored
51335 * in APE_BIN Format.
51338 /* Directory ordinal. */
51339 uint16_t dir_ordinal;
51340 /* Directory Entry Index */
51342 uint8_t unused_0[7];
51344 * This field is used in Output records to indicate that the output
51345 * is completely written to RAM. This field should be read as '1'
51346 * to indicate that the output has been completely written.
51347 * When writing a command completion or response to an internal processor,
51348 * the order of writes has to be such that this field is written last.
51353 /****************************
51354 * hwrm_nvm_erase_dir_entry *
51355 ****************************/
51358 /* hwrm_nvm_erase_dir_entry_input (size:192b/24B) */
51359 struct hwrm_nvm_erase_dir_entry_input {
51360 /* The HWRM command request type. */
51363 * The completion ring to send the completion event on. This should
51364 * be the NQ ID returned from the `nq_alloc` HWRM command.
51366 uint16_t cmpl_ring;
51368 * The sequence ID is used by the driver for tracking multiple
51369 * commands. This ID is treated as opaque data by the firmware and
51370 * the value is returned in the `hwrm_resp_hdr` upon completion.
51374 * The target ID of the command:
51375 * * 0x0-0xFFF8 - The function ID
51376 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
51377 * * 0xFFFD - Reserved for user-space HWRM interface
51380 uint16_t target_id;
51382 * A physical address pointer pointing to a host buffer that the
51383 * command's response data will be written. This can be either a host
51384 * physical address (HPA) or a guest physical address (GPA) and must
51385 * point to a physically contiguous block of memory.
51387 uint64_t resp_addr;
51388 /* Directory Entry Index */
51390 uint8_t unused_0[6];
51393 /* hwrm_nvm_erase_dir_entry_output (size:128b/16B) */
51394 struct hwrm_nvm_erase_dir_entry_output {
51395 /* The specific error status for the command. */
51396 uint16_t error_code;
51397 /* The HWRM command request type. */
51399 /* The sequence ID from the original command. */
51401 /* The length of the response data in number of bytes. */
51403 uint8_t unused_0[7];
51405 * This field is used in Output records to indicate that the output
51406 * is completely written to RAM. This field should be read as '1'
51407 * to indicate that the output has been completely written.
51408 * When writing a command completion or response to an internal processor,
51409 * the order of writes has to be such that this field is written last.
51414 /*************************
51415 * hwrm_nvm_get_dev_info *
51416 *************************/
51419 /* hwrm_nvm_get_dev_info_input (size:128b/16B) */
51420 struct hwrm_nvm_get_dev_info_input {
51421 /* The HWRM command request type. */
51424 * The completion ring to send the completion event on. This should
51425 * be the NQ ID returned from the `nq_alloc` HWRM command.
51427 uint16_t cmpl_ring;
51429 * The sequence ID is used by the driver for tracking multiple
51430 * commands. This ID is treated as opaque data by the firmware and
51431 * the value is returned in the `hwrm_resp_hdr` upon completion.
51435 * The target ID of the command:
51436 * * 0x0-0xFFF8 - The function ID
51437 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
51438 * * 0xFFFD - Reserved for user-space HWRM interface
51441 uint16_t target_id;
51443 * A physical address pointer pointing to a host buffer that the
51444 * command's response data will be written. This can be either a host
51445 * physical address (HPA) or a guest physical address (GPA) and must
51446 * point to a physically contiguous block of memory.
51448 uint64_t resp_addr;
51451 /* hwrm_nvm_get_dev_info_output (size:640b/80B) */
51452 struct hwrm_nvm_get_dev_info_output {
51453 /* The specific error status for the command. */
51454 uint16_t error_code;
51455 /* The HWRM command request type. */
51457 /* The sequence ID from the original command. */
51459 /* The length of the response data in number of bytes. */
51461 /* Manufacturer ID. */
51462 uint16_t manufacturer_id;
51464 uint16_t device_id;
51465 /* Sector size of the NVRAM device. */
51466 uint32_t sector_size;
51467 /* Total size, in bytes of the NVRAM device. */
51468 uint32_t nvram_size;
51469 uint32_t reserved_size;
51471 * Available size that can be used, in bytes. Available size is the
51472 * NVRAM size take away the used size and reserved size.
51474 uint32_t available_size;
51475 /* This field represents the major version of NVM cfg */
51476 uint8_t nvm_cfg_ver_maj;
51477 /* This field represents the minor version of NVM cfg */
51478 uint8_t nvm_cfg_ver_min;
51479 /* This field represents the update version of NVM cfg */
51480 uint8_t nvm_cfg_ver_upd;
51483 * If set to 1, firmware will provide various firmware version
51484 * information stored in the flash.
51486 #define HWRM_NVM_GET_DEV_INFO_OUTPUT_FLAGS_FW_VER_VALID \
51489 * This field represents the board package name stored in the flash.
51490 * (ASCII chars with NULL at the end).
51494 * This field represents the major version of HWRM firmware, stored in
51497 uint16_t hwrm_fw_major;
51499 * This field represents the minor version of HWRM firmware, stored in
51502 uint16_t hwrm_fw_minor;
51504 * This field represents the build version of HWRM firmware, stored in
51507 uint16_t hwrm_fw_build;
51509 * This field can be used to represent firmware branches or customer
51510 * specific releases tied to a specific (major, minor, build) version
51511 * of the HWRM firmware.
51513 uint16_t hwrm_fw_patch;
51515 * This field represents the major version of mgmt firmware, stored in
51518 uint16_t mgmt_fw_major;
51520 * This field represents the minor version of mgmt firmware, stored in
51523 uint16_t mgmt_fw_minor;
51525 * This field represents the build version of mgmt firmware, stored in
51528 uint16_t mgmt_fw_build;
51530 * This field can be used to represent firmware branches or customer
51531 * specific releases tied to a specific (major, minor, build) version
51532 * of the mgmt firmware.
51534 uint16_t mgmt_fw_patch;
51536 * This field represents the major version of roce firmware, stored in
51539 uint16_t roce_fw_major;
51541 * This field represents the minor version of roce firmware, stored in
51544 uint16_t roce_fw_minor;
51546 * This field represents the build version of roce firmware, stored in
51549 uint16_t roce_fw_build;
51551 * This field can be used to represent firmware branches or customer
51552 * specific releases tied to a specific (major, minor, build) version
51553 * of the roce firmware.
51555 uint16_t roce_fw_patch;
51556 uint8_t unused_0[7];
51558 * This field is used in Output records to indicate that the output
51559 * is completely written to RAM. This field should be read as '1'
51560 * to indicate that the output has been completely written.
51561 * When writing a command completion or response to an internal processor,
51562 * the order of writes has to be such that this field is written last.
51567 /**************************
51568 * hwrm_nvm_mod_dir_entry *
51569 **************************/
51572 /* hwrm_nvm_mod_dir_entry_input (size:256b/32B) */
51573 struct hwrm_nvm_mod_dir_entry_input {
51574 /* The HWRM command request type. */
51577 * The completion ring to send the completion event on. This should
51578 * be the NQ ID returned from the `nq_alloc` HWRM command.
51580 uint16_t cmpl_ring;
51582 * The sequence ID is used by the driver for tracking multiple
51583 * commands. This ID is treated as opaque data by the firmware and
51584 * the value is returned in the `hwrm_resp_hdr` upon completion.
51588 * The target ID of the command:
51589 * * 0x0-0xFFF8 - The function ID
51590 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
51591 * * 0xFFFD - Reserved for user-space HWRM interface
51594 uint16_t target_id;
51596 * A physical address pointer pointing to a host buffer that the
51597 * command's response data will be written. This can be either a host
51598 * physical address (HPA) or a guest physical address (GPA) and must
51599 * point to a physically contiguous block of memory.
51601 uint64_t resp_addr;
51604 * This bit must be '1' for the checksum field to be
51607 #define HWRM_NVM_MOD_DIR_ENTRY_INPUT_ENABLES_CHECKSUM UINT32_C(0x1)
51608 /* Directory Entry Index */
51611 * Directory ordinal.
51612 * The (0-based) instance of this Directory Type.
51614 uint16_t dir_ordinal;
51616 * The Directory Entry Extension flags (see BNX_DIR_EXT_* for
51617 * extension flag definitions).
51621 * Directory Entry Attribute flags (see BNX_DIR_ATTR_* for attribute
51622 * flag definitions).
51626 * If valid, then this field updates the checksum
51627 * value of the content in the directory entry.
51632 /* hwrm_nvm_mod_dir_entry_output (size:128b/16B) */
51633 struct hwrm_nvm_mod_dir_entry_output {
51634 /* The specific error status for the command. */
51635 uint16_t error_code;
51636 /* The HWRM command request type. */
51638 /* The sequence ID from the original command. */
51640 /* The length of the response data in number of bytes. */
51642 uint8_t unused_0[7];
51644 * This field is used in Output records to indicate that the output
51645 * is completely written to RAM. This field should be read as '1'
51646 * to indicate that the output has been completely written.
51647 * When writing a command completion or response to an internal processor,
51648 * the order of writes has to be such that this field is written last.
51653 /**************************
51654 * hwrm_nvm_verify_update *
51655 **************************/
51658 /* hwrm_nvm_verify_update_input (size:192b/24B) */
51659 struct hwrm_nvm_verify_update_input {
51660 /* The HWRM command request type. */
51663 * The completion ring to send the completion event on. This should
51664 * be the NQ ID returned from the `nq_alloc` HWRM command.
51666 uint16_t cmpl_ring;
51668 * The sequence ID is used by the driver for tracking multiple
51669 * commands. This ID is treated as opaque data by the firmware and
51670 * the value is returned in the `hwrm_resp_hdr` upon completion.
51674 * The target ID of the command:
51675 * * 0x0-0xFFF8 - The function ID
51676 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
51677 * * 0xFFFD - Reserved for user-space HWRM interface
51680 uint16_t target_id;
51682 * A physical address pointer pointing to a host buffer that the
51683 * command's response data will be written. This can be either a host
51684 * physical address (HPA) or a guest physical address (GPA) and must
51685 * point to a physically contiguous block of memory.
51687 uint64_t resp_addr;
51688 /* Directory Entry Type, to be verified. */
51691 * Directory ordinal.
51692 * The instance of the Directory Type to be verified.
51694 uint16_t dir_ordinal;
51696 * The Directory Entry Extension flags.
51697 * The "UPDATE" extension flag must be set in this value.
51698 * A corresponding directory entry with the same type and ordinal
51699 * values but *without*
51700 * the "UPDATE" extension flag must also exist. The other flags of
51701 * the extension must
51702 * be identical between the active and update entries.
51705 uint8_t unused_0[2];
51708 /* hwrm_nvm_verify_update_output (size:128b/16B) */
51709 struct hwrm_nvm_verify_update_output {
51710 /* The specific error status for the command. */
51711 uint16_t error_code;
51712 /* The HWRM command request type. */
51714 /* The sequence ID from the original command. */
51716 /* The length of the response data in number of bytes. */
51718 uint8_t unused_0[7];
51720 * This field is used in Output records to indicate that the output
51721 * is completely written to RAM. This field should be read as '1'
51722 * to indicate that the output has been completely written.
51723 * When writing a command completion or response to an internal processor,
51724 * the order of writes has to be such that this field is written last.
51729 /***************************
51730 * hwrm_nvm_install_update *
51731 ***************************/
51734 /* hwrm_nvm_install_update_input (size:192b/24B) */
51735 struct hwrm_nvm_install_update_input {
51736 /* The HWRM command request type. */
51739 * The completion ring to send the completion event on. This should
51740 * be the NQ ID returned from the `nq_alloc` HWRM command.
51742 uint16_t cmpl_ring;
51744 * The sequence ID is used by the driver for tracking multiple
51745 * commands. This ID is treated as opaque data by the firmware and
51746 * the value is returned in the `hwrm_resp_hdr` upon completion.
51750 * The target ID of the command:
51751 * * 0x0-0xFFF8 - The function ID
51752 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
51753 * * 0xFFFD - Reserved for user-space HWRM interface
51756 uint16_t target_id;
51758 * A physical address pointer pointing to a host buffer that the
51759 * command's response data will be written. This can be either a host
51760 * physical address (HPA) or a guest physical address (GPA) and must
51761 * point to a physically contiguous block of memory.
51763 uint64_t resp_addr;
51765 * Installation type. If the value 3 through 0xffff is used,
51766 * only packaged items with that type value will be installed and
51767 * conditional installation directives for those packaged items
51768 * will be over-ridden (i.e. 'create' or 'replace' will be treated
51771 uint32_t install_type;
51773 * Perform a normal package installation. Conditional installation
51774 * directives (e.g. 'create' and 'replace') of packaged items
51775 * will be followed.
51777 #define HWRM_NVM_INSTALL_UPDATE_INPUT_INSTALL_TYPE_NORMAL UINT32_C(0x0)
51779 * Install all packaged items regardless of installation directive
51780 * (i.e. treat all packaged items as though they have an installation
51781 * directive of 'install').
51783 #define HWRM_NVM_INSTALL_UPDATE_INPUT_INSTALL_TYPE_ALL \
51784 UINT32_C(0xffffffff)
51785 #define HWRM_NVM_INSTALL_UPDATE_INPUT_INSTALL_TYPE_LAST \
51786 HWRM_NVM_INSTALL_UPDATE_INPUT_INSTALL_TYPE_ALL
51789 * If set to 1, then securely erase all unused locations in
51790 * persistent storage.
51792 #define HWRM_NVM_INSTALL_UPDATE_INPUT_FLAGS_ERASE_UNUSED_SPACE \
51795 * If set to 1, then unspecified images, images not in the package
51796 * file, will be safely deleted.
51797 * When combined with erase_unused_space then unspecified images will
51798 * be securely erased.
51800 #define HWRM_NVM_INSTALL_UPDATE_INPUT_FLAGS_REMOVE_UNUSED_PKG \
51803 * If set to 1, FW will defragment the NVM if defragmentation is
51804 * required for the update.
51805 * Allow additional time for this command to complete if this bit is
51808 #define HWRM_NVM_INSTALL_UPDATE_INPUT_FLAGS_ALLOWED_TO_DEFRAG \
51811 * If set to 1, FW will verify the package in the "UPDATE" NVM item
51812 * without installing it. This flag is for FW internal use only.
51813 * Users should not set this flag. The request will otherwise fail.
51815 #define HWRM_NVM_INSTALL_UPDATE_INPUT_FLAGS_VERIFY_ONLY \
51817 uint8_t unused_0[2];
51820 /* hwrm_nvm_install_update_output (size:192b/24B) */
51821 struct hwrm_nvm_install_update_output {
51822 /* The specific error status for the command. */
51823 uint16_t error_code;
51824 /* The HWRM command request type. */
51826 /* The sequence ID from the original command. */
51828 /* The length of the response data in number of bytes. */
51831 * Bit-mask of successfully installed items.
51832 * Bit-0 corresponding to the first packaged item, Bit-1 for the second item, etc.
51833 * A value of 0 indicates that no items were successfully installed.
51835 uint64_t installed_items;
51836 /* result is 8 b corresponding to BCMRETVAL error codes */
51838 /* There was no problem with the package installation. */
51839 #define HWRM_NVM_INSTALL_UPDATE_OUTPUT_RESULT_SUCCESS \
51841 /* Generic failure */
51842 #define HWRM_NVM_INSTALL_UPDATE_OUTPUT_RESULT_FAILURE \
51844 /* Allocation error malloc failure */
51845 #define HWRM_NVM_INSTALL_UPDATE_OUTPUT_RESULT_MALLOC_FAILURE \
51847 /* NVM install error due to invalid index */
51848 #define HWRM_NVM_INSTALL_UPDATE_OUTPUT_RESULT_INVALID_INDEX_PARAMETER \
51850 /* NVM install error due to invalid type */
51851 #define HWRM_NVM_INSTALL_UPDATE_OUTPUT_RESULT_INVALID_TYPE_PARAMETER \
51853 /* Invalid package due to invalid prerequisite */
51854 #define HWRM_NVM_INSTALL_UPDATE_OUTPUT_RESULT_INVALID_PREREQUISITE \
51856 /* Invalid package due to invalid file header */
51857 #define HWRM_NVM_INSTALL_UPDATE_OUTPUT_RESULT_INVALID_FILE_HEADER \
51859 /* Invalid package due to invalid format */
51860 #define HWRM_NVM_INSTALL_UPDATE_OUTPUT_RESULT_INVALID_SIGNATURE \
51862 /* Invalid package due to invalid property stream */
51863 #define HWRM_NVM_INSTALL_UPDATE_OUTPUT_RESULT_INVALID_PROP_STREAM \
51865 /* Invalid package due to invalid property length */
51866 #define HWRM_NVM_INSTALL_UPDATE_OUTPUT_RESULT_INVALID_PROP_LENGTH \
51868 /* Invalid package due to invalid manifest */
51869 #define HWRM_NVM_INSTALL_UPDATE_OUTPUT_RESULT_INVALID_MANIFEST \
51871 /* Invalid package due to invalid trailer */
51872 #define HWRM_NVM_INSTALL_UPDATE_OUTPUT_RESULT_INVALID_TRAILER \
51874 /* Invalid package due to invalid checksum */
51875 #define HWRM_NVM_INSTALL_UPDATE_OUTPUT_RESULT_INVALID_CHECKSUM \
51877 /* Invalid package due to invalid item checksum */
51878 #define HWRM_NVM_INSTALL_UPDATE_OUTPUT_RESULT_INVALID_ITEM_CHECKSUM \
51880 /* Invalid package due to invalid length */
51881 #define HWRM_NVM_INSTALL_UPDATE_OUTPUT_RESULT_INVALID_DATA_LENGTH \
51883 /* Invalid package due to invalid directive */
51884 #define HWRM_NVM_INSTALL_UPDATE_OUTPUT_RESULT_INVALID_DIRECTIVE \
51886 /* Invalid device due to unsupported chip revision */
51887 #define HWRM_NVM_INSTALL_UPDATE_OUTPUT_RESULT_UNSUPPORTED_CHIP_REV \
51889 /* Invalid device due to unsupported device ID */
51890 #define HWRM_NVM_INSTALL_UPDATE_OUTPUT_RESULT_UNSUPPORTED_DEVICE_ID \
51892 /* Invalid device due to unsupported subsystem vendor */
51893 #define HWRM_NVM_INSTALL_UPDATE_OUTPUT_RESULT_UNSUPPORTED_SUBSYS_VENDOR \
51895 /* Invalid device due to unsupported subsystem ID */
51896 #define HWRM_NVM_INSTALL_UPDATE_OUTPUT_RESULT_UNSUPPORTED_SUBSYS_ID \
51898 /* Invalid device due to unsupported product ID or customer ID */
51899 #define HWRM_NVM_INSTALL_UPDATE_OUTPUT_RESULT_UNSUPPORTED_PLATFORM \
51901 /* Invalid package due to duplicate item */
51902 #define HWRM_NVM_INSTALL_UPDATE_OUTPUT_RESULT_DUPLICATE_ITEM \
51904 /* Invalid package due to zero length item */
51905 #define HWRM_NVM_INSTALL_UPDATE_OUTPUT_RESULT_ZERO_LENGTH_ITEM \
51907 /* NVM integrity error checksum */
51908 #define HWRM_NVM_INSTALL_UPDATE_OUTPUT_RESULT_INSTALL_CHECKSUM_ERROR \
51910 /* NVM integrity error */
51911 #define HWRM_NVM_INSTALL_UPDATE_OUTPUT_RESULT_INSTALL_DATA_ERROR \
51913 /* Authentication error */
51914 #define HWRM_NVM_INSTALL_UPDATE_OUTPUT_RESULT_INSTALL_AUTHENTICATION_ERROR \
51916 /* NVM install error item not found */
51917 #define HWRM_NVM_INSTALL_UPDATE_OUTPUT_RESULT_ITEM_NOT_FOUND \
51919 /* NVM install error item locked */
51920 #define HWRM_NVM_INSTALL_UPDATE_OUTPUT_RESULT_ITEM_LOCKED \
51922 #define HWRM_NVM_INSTALL_UPDATE_OUTPUT_RESULT_LAST \
51923 HWRM_NVM_INSTALL_UPDATE_OUTPUT_RESULT_ITEM_LOCKED
51924 /* problem_item is 8 b */
51925 uint8_t problem_item;
51926 /* There was no problem with any packaged items. */
51927 #define HWRM_NVM_INSTALL_UPDATE_OUTPUT_PROBLEM_ITEM_NONE \
51929 /* There was a problem with the NVM package itself. */
51930 #define HWRM_NVM_INSTALL_UPDATE_OUTPUT_PROBLEM_ITEM_PACKAGE \
51932 #define HWRM_NVM_INSTALL_UPDATE_OUTPUT_PROBLEM_ITEM_LAST \
51933 HWRM_NVM_INSTALL_UPDATE_OUTPUT_PROBLEM_ITEM_PACKAGE
51934 /* reset_required is 8 b */
51935 uint8_t reset_required;
51937 * No reset is required for installed/updated firmware or
51938 * microcode to take effect.
51940 #define HWRM_NVM_INSTALL_UPDATE_OUTPUT_RESET_REQUIRED_NONE \
51943 * A PCIe reset (e.g. system reboot) is
51944 * required for newly installed/updated firmware or
51945 * microcode to take effect.
51947 #define HWRM_NVM_INSTALL_UPDATE_OUTPUT_RESET_REQUIRED_PCI \
51950 * A controller power reset (e.g. system power-cycle) is
51951 * required for newly installed/updated firmware or
51952 * microcode to take effect. Some newly installed/updated
51953 * firmware or microcode may still take effect upon the
51956 #define HWRM_NVM_INSTALL_UPDATE_OUTPUT_RESET_REQUIRED_POWER \
51958 #define HWRM_NVM_INSTALL_UPDATE_OUTPUT_RESET_REQUIRED_LAST \
51959 HWRM_NVM_INSTALL_UPDATE_OUTPUT_RESET_REQUIRED_POWER
51960 uint8_t unused_0[4];
51962 * This field is used in Output records to indicate that the output
51963 * is completely written to RAM. This field should be read as '1'
51964 * to indicate that the output has been completely written.
51965 * When writing a command completion or response to an internal processor,
51966 * the order of writes has to be such that this field is written last.
51971 /* hwrm_nvm_install_update_cmd_err (size:64b/8B) */
51972 struct hwrm_nvm_install_update_cmd_err {
51974 * command specific error codes that goes to
51975 * the cmd_err field in Common HWRM Error Response.
51978 /* Unknown error */
51979 #define HWRM_NVM_INSTALL_UPDATE_CMD_ERR_CODE_UNKNOWN \
51981 /* Unable to complete operation due to fragmentation */
51982 #define HWRM_NVM_INSTALL_UPDATE_CMD_ERR_CODE_FRAG_ERR \
51984 /* nvm is completely full. */
51985 #define HWRM_NVM_INSTALL_UPDATE_CMD_ERR_CODE_NO_SPACE \
51987 /* Firmware update failed due to Anti-rollback. */
51988 #define HWRM_NVM_INSTALL_UPDATE_CMD_ERR_CODE_ANTI_ROLLBACK \
51990 #define HWRM_NVM_INSTALL_UPDATE_CMD_ERR_CODE_LAST \
51991 HWRM_NVM_INSTALL_UPDATE_CMD_ERR_CODE_ANTI_ROLLBACK
51992 uint8_t unused_0[7];
51995 /******************
51997 ******************/
52000 /* hwrm_nvm_flush_input (size:128b/16B) */
52001 struct hwrm_nvm_flush_input {
52002 /* The HWRM command request type. */
52005 * The completion ring to send the completion event on. This should
52006 * be the NQ ID returned from the `nq_alloc` HWRM command.
52008 uint16_t cmpl_ring;
52010 * The sequence ID is used by the driver for tracking multiple
52011 * commands. This ID is treated as opaque data by the firmware and
52012 * the value is returned in the `hwrm_resp_hdr` upon completion.
52016 * The target ID of the command:
52017 * * 0x0-0xFFF8 - The function ID
52018 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
52019 * * 0xFFFD - Reserved for user-space HWRM interface
52022 uint16_t target_id;
52024 * A physical address pointer pointing to a host buffer that the
52025 * command's response data will be written. This can be either a host
52026 * physical address (HPA) or a guest physical address (GPA) and must
52027 * point to a physically contiguous block of memory.
52029 uint64_t resp_addr;
52032 /* hwrm_nvm_flush_output (size:128b/16B) */
52033 struct hwrm_nvm_flush_output {
52034 /* The specific error status for the command. */
52035 uint16_t error_code;
52036 /* The HWRM command request type. */
52038 /* The sequence ID from the original command. */
52040 /* The length of the response data in number of bytes. */
52042 uint8_t unused_0[7];
52044 * This field is used in Output records to indicate that the output
52045 * is completely written to RAM. This field should be read as '1'
52046 * to indicate that the output has been completely written.
52047 * When writing a command completion or response to an internal processor,
52048 * the order of writes has to be such that this field is written last.
52053 /* hwrm_nvm_flush_cmd_err (size:64b/8B) */
52054 struct hwrm_nvm_flush_cmd_err {
52056 * command specific error codes that goes to
52057 * the cmd_err field in Common HWRM Error Response.
52060 /* Unknown error */
52061 #define HWRM_NVM_FLUSH_CMD_ERR_CODE_UNKNOWN UINT32_C(0x0)
52062 /* flush could not be performed */
52063 #define HWRM_NVM_FLUSH_CMD_ERR_CODE_FAIL UINT32_C(0x1)
52064 #define HWRM_NVM_FLUSH_CMD_ERR_CODE_LAST \
52065 HWRM_NVM_FLUSH_CMD_ERR_CODE_FAIL
52066 uint8_t unused_0[7];
52069 /*************************
52070 * hwrm_nvm_get_variable *
52071 *************************/
52074 /* hwrm_nvm_get_variable_input (size:320b/40B) */
52075 struct hwrm_nvm_get_variable_input {
52076 /* The HWRM command request type. */
52079 * The completion ring to send the completion event on. This should
52080 * be the NQ ID returned from the `nq_alloc` HWRM command.
52082 uint16_t cmpl_ring;
52084 * The sequence ID is used by the driver for tracking multiple
52085 * commands. This ID is treated as opaque data by the firmware and
52086 * the value is returned in the `hwrm_resp_hdr` upon completion.
52090 * The target ID of the command:
52091 * * 0x0-0xFFF8 - The function ID
52092 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
52093 * * 0xFFFD - Reserved for user-space HWRM interface
52096 uint16_t target_id;
52098 * A physical address pointer pointing to a host buffer that the
52099 * command's response data will be written. This can be either a host
52100 * physical address (HPA) or a guest physical address (GPA) and must
52101 * point to a physically contiguous block of memory.
52103 uint64_t resp_addr;
52105 * This is the host address where
52106 * nvm variable will be stored
52108 uint64_t dest_data_addr;
52109 /* size of data in bits */
52111 /* nvm cfg option number */
52112 uint16_t option_num;
52114 #define HWRM_NVM_GET_VARIABLE_INPUT_OPTION_NUM_RSVD_0 UINT32_C(0x0)
52116 #define HWRM_NVM_GET_VARIABLE_INPUT_OPTION_NUM_RSVD_FFFF \
52118 #define HWRM_NVM_GET_VARIABLE_INPUT_OPTION_NUM_LAST \
52119 HWRM_NVM_GET_VARIABLE_INPUT_OPTION_NUM_RSVD_FFFF
52121 * Number of dimensions for this nvm configuration variable.
52122 * This value indicates how many of the indexN values to use.
52123 * A value of 0 means that none of the indexN values are valid.
52124 * A value of 1 requires at index0 is valued, a value of 2
52125 * requires that index0 and index1 are valid, and so forth
52127 uint16_t dimensions;
52128 /* index for the 1st dimensions */
52130 /* index for the 2nd dimensions */
52132 /* index for the 3rd dimensions */
52134 /* index for the 4th dimensions */
52138 * When this bit is set to 1, the factory default value will be returned,
52139 * 0 returns the operational value.
52141 #define HWRM_NVM_GET_VARIABLE_INPUT_FLAGS_FACTORY_DFLT \
52146 /* hwrm_nvm_get_variable_output (size:128b/16B) */
52147 struct hwrm_nvm_get_variable_output {
52148 /* The specific error status for the command. */
52149 uint16_t error_code;
52150 /* The HWRM command request type. */
52152 /* The sequence ID from the original command. */
52154 /* The length of the response data in number of bytes. */
52156 /* size of data of the actual variable retrieved in bits */
52159 * option_num is the option number for the data retrieved. It is
52160 * possible in the future that the option number returned would be
52161 * different than requested. This condition could occur if an option is
52162 * deprecated and a new option id is defined with similar
52163 * characteristics, but has a slightly different definition. This
52164 * also makes it convenient for the caller to identify the variable
52165 * result with the option id from the response.
52167 uint16_t option_num;
52169 #define HWRM_NVM_GET_VARIABLE_OUTPUT_OPTION_NUM_RSVD_0 UINT32_C(0x0)
52171 #define HWRM_NVM_GET_VARIABLE_OUTPUT_OPTION_NUM_RSVD_FFFF \
52173 #define HWRM_NVM_GET_VARIABLE_OUTPUT_OPTION_NUM_LAST \
52174 HWRM_NVM_GET_VARIABLE_OUTPUT_OPTION_NUM_RSVD_FFFF
52175 uint8_t unused_0[3];
52177 * This field is used in Output records to indicate that the output
52178 * is completely written to RAM. This field should be read as '1'
52179 * to indicate that the output has been completely written.
52180 * When writing a command completion or response to an internal processor,
52181 * the order of writes has to be such that this field is written last.
52186 /* hwrm_nvm_get_variable_cmd_err (size:64b/8B) */
52187 struct hwrm_nvm_get_variable_cmd_err {
52189 * command specific error codes that goes to
52190 * the cmd_err field in Common HWRM Error Response.
52193 /* Unknown error */
52194 #define HWRM_NVM_GET_VARIABLE_CMD_ERR_CODE_UNKNOWN UINT32_C(0x0)
52195 /* variable does not exist */
52196 #define HWRM_NVM_GET_VARIABLE_CMD_ERR_CODE_VAR_NOT_EXIST UINT32_C(0x1)
52197 /* configuration is corrupted and the variable cannot be saved */
52198 #define HWRM_NVM_GET_VARIABLE_CMD_ERR_CODE_CORRUPT_VAR UINT32_C(0x2)
52199 /* length specified is too small */
52200 #define HWRM_NVM_GET_VARIABLE_CMD_ERR_CODE_LEN_TOO_SHORT UINT32_C(0x3)
52201 #define HWRM_NVM_GET_VARIABLE_CMD_ERR_CODE_LAST \
52202 HWRM_NVM_GET_VARIABLE_CMD_ERR_CODE_LEN_TOO_SHORT
52203 uint8_t unused_0[7];
52206 /*************************
52207 * hwrm_nvm_set_variable *
52208 *************************/
52211 /* hwrm_nvm_set_variable_input (size:320b/40B) */
52212 struct hwrm_nvm_set_variable_input {
52213 /* The HWRM command request type. */
52216 * The completion ring to send the completion event on. This should
52217 * be the NQ ID returned from the `nq_alloc` HWRM command.
52219 uint16_t cmpl_ring;
52221 * The sequence ID is used by the driver for tracking multiple
52222 * commands. This ID is treated as opaque data by the firmware and
52223 * the value is returned in the `hwrm_resp_hdr` upon completion.
52227 * The target ID of the command:
52228 * * 0x0-0xFFF8 - The function ID
52229 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
52230 * * 0xFFFD - Reserved for user-space HWRM interface
52233 uint16_t target_id;
52235 * A physical address pointer pointing to a host buffer that the
52236 * command's response data will be written. This can be either a host
52237 * physical address (HPA) or a guest physical address (GPA) and must
52238 * point to a physically contiguous block of memory.
52240 uint64_t resp_addr;
52242 * This is the host address where
52243 * nvm variable will be copied from
52245 uint64_t src_data_addr;
52246 /* size of data in bits */
52248 /* nvm cfg option number */
52249 uint16_t option_num;
52251 #define HWRM_NVM_SET_VARIABLE_INPUT_OPTION_NUM_RSVD_0 UINT32_C(0x0)
52253 #define HWRM_NVM_SET_VARIABLE_INPUT_OPTION_NUM_RSVD_FFFF \
52255 #define HWRM_NVM_SET_VARIABLE_INPUT_OPTION_NUM_LAST \
52256 HWRM_NVM_SET_VARIABLE_INPUT_OPTION_NUM_RSVD_FFFF
52258 * Number of dimensions for this nvm configuration variable.
52259 * This value indicates how many of the indexN values to use.
52260 * A value of 0 means that none of the indexN values are valid.
52261 * A value of 1 requires at index0 is valued, a value of 2
52262 * requires that index0 and index1 are valid, and so forth
52264 uint16_t dimensions;
52265 /* index for the 1st dimensions */
52267 /* index for the 2nd dimensions */
52269 /* index for the 3rd dimensions */
52271 /* index for the 4th dimensions */
52275 * When this bit is 1, flush internal cache after this write
52276 * operation (see hwrm_nvm_flush command.)
52278 #define HWRM_NVM_SET_VARIABLE_INPUT_FLAGS_FORCE_FLUSH \
52280 /* encryption method */
52281 #define HWRM_NVM_SET_VARIABLE_INPUT_FLAGS_ENCRYPT_MODE_MASK \
52283 #define HWRM_NVM_SET_VARIABLE_INPUT_FLAGS_ENCRYPT_MODE_SFT 1
52284 /* No encryption. */
52285 #define HWRM_NVM_SET_VARIABLE_INPUT_FLAGS_ENCRYPT_MODE_NONE \
52286 (UINT32_C(0x0) << 1)
52287 /* one-way encryption. */
52288 #define HWRM_NVM_SET_VARIABLE_INPUT_FLAGS_ENCRYPT_MODE_HMAC_SHA1 \
52289 (UINT32_C(0x1) << 1)
52290 /* symmetric AES256 encryption. */
52291 #define HWRM_NVM_SET_VARIABLE_INPUT_FLAGS_ENCRYPT_MODE_AES256 \
52292 (UINT32_C(0x2) << 1)
52293 /* SHA1 digest appended to plaintext contents, for authentication */
52294 #define HWRM_NVM_SET_VARIABLE_INPUT_FLAGS_ENCRYPT_MODE_HMAC_SHA1_AUTH \
52295 (UINT32_C(0x3) << 1)
52296 #define HWRM_NVM_SET_VARIABLE_INPUT_FLAGS_ENCRYPT_MODE_LAST \
52297 HWRM_NVM_SET_VARIABLE_INPUT_FLAGS_ENCRYPT_MODE_HMAC_SHA1_AUTH
52298 #define HWRM_NVM_SET_VARIABLE_INPUT_FLAGS_FLAGS_UNUSED_0_MASK \
52300 #define HWRM_NVM_SET_VARIABLE_INPUT_FLAGS_FLAGS_UNUSED_0_SFT 4
52301 /* When this bit is 1, update the factory default region */
52302 #define HWRM_NVM_SET_VARIABLE_INPUT_FLAGS_FACTORY_DEFAULT \
52307 /* hwrm_nvm_set_variable_output (size:128b/16B) */
52308 struct hwrm_nvm_set_variable_output {
52309 /* The specific error status for the command. */
52310 uint16_t error_code;
52311 /* The HWRM command request type. */
52313 /* The sequence ID from the original command. */
52315 /* The length of the response data in number of bytes. */
52317 uint8_t unused_0[7];
52319 * This field is used in Output records to indicate that the output
52320 * is completely written to RAM. This field should be read as '1'
52321 * to indicate that the output has been completely written.
52322 * When writing a command completion or response to an internal processor,
52323 * the order of writes has to be such that this field is written last.
52328 /* hwrm_nvm_set_variable_cmd_err (size:64b/8B) */
52329 struct hwrm_nvm_set_variable_cmd_err {
52331 * command specific error codes that goes to
52332 * the cmd_err field in Common HWRM Error Response.
52335 /* Unknown error */
52336 #define HWRM_NVM_SET_VARIABLE_CMD_ERR_CODE_UNKNOWN UINT32_C(0x0)
52337 /* variable does not exist */
52338 #define HWRM_NVM_SET_VARIABLE_CMD_ERR_CODE_VAR_NOT_EXIST UINT32_C(0x1)
52339 /* configuration is corrupted and the variable cannot be saved */
52340 #define HWRM_NVM_SET_VARIABLE_CMD_ERR_CODE_CORRUPT_VAR UINT32_C(0x2)
52341 #define HWRM_NVM_SET_VARIABLE_CMD_ERR_CODE_LAST \
52342 HWRM_NVM_SET_VARIABLE_CMD_ERR_CODE_CORRUPT_VAR
52343 uint8_t unused_0[7];
52346 /****************************
52347 * hwrm_nvm_validate_option *
52348 ****************************/
52351 /* hwrm_nvm_validate_option_input (size:320b/40B) */
52352 struct hwrm_nvm_validate_option_input {
52353 /* The HWRM command request type. */
52356 * The completion ring to send the completion event on. This should
52357 * be the NQ ID returned from the `nq_alloc` HWRM command.
52359 uint16_t cmpl_ring;
52361 * The sequence ID is used by the driver for tracking multiple
52362 * commands. This ID is treated as opaque data by the firmware and
52363 * the value is returned in the `hwrm_resp_hdr` upon completion.
52367 * The target ID of the command:
52368 * * 0x0-0xFFF8 - The function ID
52369 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
52370 * * 0xFFFD - Reserved for user-space HWRM interface
52373 uint16_t target_id;
52375 * A physical address pointer pointing to a host buffer that the
52376 * command's response data will be written. This can be either a host
52377 * physical address (HPA) or a guest physical address (GPA) and must
52378 * point to a physically contiguous block of memory.
52380 uint64_t resp_addr;
52382 * This is the host address where
52383 * nvm variable will be copied from
52385 uint64_t src_data_addr;
52386 /* size of data in bits */
52388 /* nvm cfg option number */
52389 uint16_t option_num;
52391 #define HWRM_NVM_VALIDATE_OPTION_INPUT_OPTION_NUM_RSVD_0 \
52394 #define HWRM_NVM_VALIDATE_OPTION_INPUT_OPTION_NUM_RSVD_FFFF \
52396 #define HWRM_NVM_VALIDATE_OPTION_INPUT_OPTION_NUM_LAST \
52397 HWRM_NVM_VALIDATE_OPTION_INPUT_OPTION_NUM_RSVD_FFFF
52399 * Number of dimensions for this nvm configuration variable.
52400 * This value indicates how many of the indexN values to use.
52401 * A value of 0 means that none of the indexN values are valid.
52402 * A value of 1 requires at index0 is valued, a value of 2
52403 * requires that index0 and index1 are valid, and so forth
52405 uint16_t dimensions;
52406 /* index for the 1st dimensions */
52408 /* index for the 2nd dimensions */
52410 /* index for the 3rd dimensions */
52412 /* index for the 4th dimensions */
52414 uint8_t unused_0[2];
52417 /* hwrm_nvm_validate_option_output (size:128b/16B) */
52418 struct hwrm_nvm_validate_option_output {
52419 /* The specific error status for the command. */
52420 uint16_t error_code;
52421 /* The HWRM command request type. */
52423 /* The sequence ID from the original command. */
52425 /* The length of the response data in number of bytes. */
52429 * indicates that the value provided for the option is not matching
52430 * with the saved data.
52432 #define HWRM_NVM_VALIDATE_OPTION_OUTPUT_RESULT_NOT_MATCH UINT32_C(0x0)
52434 * indicates that the value provided for the option is matching the
52437 #define HWRM_NVM_VALIDATE_OPTION_OUTPUT_RESULT_MATCH UINT32_C(0x1)
52438 #define HWRM_NVM_VALIDATE_OPTION_OUTPUT_RESULT_LAST \
52439 HWRM_NVM_VALIDATE_OPTION_OUTPUT_RESULT_MATCH
52440 uint8_t unused_0[6];
52442 * This field is used in Output records to indicate that the output
52443 * is completely written to RAM. This field should be read as '1'
52444 * to indicate that the output has been completely written.
52445 * When writing a command completion or response to an internal processor,
52446 * the order of writes has to be such that this field is written last.
52451 /* hwrm_nvm_validate_option_cmd_err (size:64b/8B) */
52452 struct hwrm_nvm_validate_option_cmd_err {
52454 * command specific error codes that goes to
52455 * the cmd_err field in Common HWRM Error Response.
52458 /* Unknown error */
52459 #define HWRM_NVM_VALIDATE_OPTION_CMD_ERR_CODE_UNKNOWN UINT32_C(0x0)
52460 #define HWRM_NVM_VALIDATE_OPTION_CMD_ERR_CODE_LAST \
52461 HWRM_NVM_VALIDATE_OPTION_CMD_ERR_CODE_UNKNOWN
52462 uint8_t unused_0[7];
52465 /*******************
52466 * hwrm_nvm_defrag *
52467 *******************/
52470 /* hwrm_nvm_defrag_input (size:192b/24B) */
52471 struct hwrm_nvm_defrag_input {
52472 /* The HWRM command request type. */
52475 * The completion ring to send the completion event on. This should
52476 * be the NQ ID returned from the `nq_alloc` HWRM command.
52478 uint16_t cmpl_ring;
52480 * The sequence ID is used by the driver for tracking multiple
52481 * commands. This ID is treated as opaque data by the firmware and
52482 * the value is returned in the `hwrm_resp_hdr` upon completion.
52486 * The target ID of the command:
52487 * * 0x0-0xFFF8 - The function ID
52488 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
52489 * * 0xFFFD - Reserved for user-space HWRM interface
52492 uint16_t target_id;
52494 * A physical address pointer pointing to a host buffer that the
52495 * command's response data will be written. This can be either a host
52496 * physical address (HPA) or a guest physical address (GPA) and must
52497 * point to a physically contiguous block of memory.
52499 uint64_t resp_addr;
52501 /* This bit must be '1' to perform NVM defragmentation. */
52502 #define HWRM_NVM_DEFRAG_INPUT_FLAGS_DEFRAG UINT32_C(0x1)
52503 uint8_t unused_0[4];
52506 /* hwrm_nvm_defrag_output (size:128b/16B) */
52507 struct hwrm_nvm_defrag_output {
52508 /* The specific error status for the command. */
52509 uint16_t error_code;
52510 /* The HWRM command request type. */
52512 /* The sequence ID from the original command. */
52514 /* The length of the response data in number of bytes. */
52516 uint8_t unused_0[7];
52518 * This field is used in Output records to indicate that the output
52519 * is completely written to RAM. This field should be read as '1'
52520 * to indicate that the output has been completely written.
52521 * When writing a command completion or response to an internal processor,
52522 * the order of writes has to be such that this field is written last.
52527 /* hwrm_nvm_defrag_cmd_err (size:64b/8B) */
52528 struct hwrm_nvm_defrag_cmd_err {
52530 * command specific error codes that goes to
52531 * the cmd_err field in Common HWRM Error Response.
52534 /* Unknown error */
52535 #define HWRM_NVM_DEFRAG_CMD_ERR_CODE_UNKNOWN UINT32_C(0x0)
52536 /* NVM defragmentation could not be performed */
52537 #define HWRM_NVM_DEFRAG_CMD_ERR_CODE_FAIL UINT32_C(0x1)
52538 #define HWRM_NVM_DEFRAG_CMD_ERR_CODE_LAST \
52539 HWRM_NVM_DEFRAG_CMD_ERR_CODE_FAIL
52540 uint8_t unused_0[7];
52548 /* hwrm_oem_cmd_input (size:1024b/128B) */
52549 struct hwrm_oem_cmd_input {
52550 /* The HWRM command request type. */
52553 * The completion ring to send the completion event on. This should
52554 * be the NQ ID returned from the `nq_alloc` HWRM command.
52556 uint16_t cmpl_ring;
52558 * The sequence ID is used by the driver for tracking multiple
52559 * commands. This ID is treated as opaque data by the firmware and
52560 * the value is returned in the `hwrm_resp_hdr` upon completion.
52564 * The target ID of the command:
52565 * * 0x0-0xFFF8 - The function ID
52566 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
52567 * * 0xFFFD - Reserved for user-space HWRM interface
52570 uint16_t target_id;
52572 * A physical address pointer pointing to a host buffer that the
52573 * command's response data will be written. This can be either a host
52574 * physical address (HPA) or a guest physical address (GPA) and must
52575 * point to a physically contiguous block of memory.
52577 uint64_t resp_addr;
52580 /* This field contains the vendor specific command data. */
52581 uint32_t oem_data[26];
52584 /* hwrm_oem_cmd_output (size:768b/96B) */
52585 struct hwrm_oem_cmd_output {
52586 /* The specific error status for the command. */
52587 uint16_t error_code;
52588 /* The HWRM command request type. */
52590 /* The sequence ID from the original command. */
52592 /* The length of the response data in number of bytes. */
52596 /* This field contains the vendor specific response data. */
52597 uint32_t oem_data[18];
52598 uint8_t unused_1[7];
52600 * This field is used in Output records to indicate that the output
52601 * is completely written to RAM. This field should be read as '1'
52602 * to indicate that the output has been completely written.
52603 * When writing a command completion or response to an internal processor,
52604 * the order of writes has to be such that this field is written last.
52611 ******************/
52614 /* hwrm_fw_reset_input (size:192b/24B) */
52615 struct hwrm_fw_reset_input {
52616 /* The HWRM command request type. */
52619 * The completion ring to send the completion event on. This should
52620 * be the NQ ID returned from the `nq_alloc` HWRM command.
52622 uint16_t cmpl_ring;
52624 * The sequence ID is used by the driver for tracking multiple
52625 * commands. This ID is treated as opaque data by the firmware and
52626 * the value is returned in the `hwrm_resp_hdr` upon completion.
52630 * The target ID of the command:
52631 * * 0x0-0xFFF8 - The function ID
52632 * * 0xFFF8-0xFFFE - Reserved for internal processors
52635 uint16_t target_id;
52637 * A physical address pointer pointing to a host buffer that the
52638 * command's response data will be written. This can be either a host
52639 * physical address (HPA) or a guest physical address (GPA) and must
52640 * point to a physically contiguous block of memory.
52642 uint64_t resp_addr;
52643 /* Type of embedded processor. */
52644 uint8_t embedded_proc_type;
52645 /* Boot Processor */
52646 #define HWRM_FW_RESET_INPUT_EMBEDDED_PROC_TYPE_BOOT \
52648 /* Management Processor */
52649 #define HWRM_FW_RESET_INPUT_EMBEDDED_PROC_TYPE_MGMT \
52651 /* Network control processor */
52652 #define HWRM_FW_RESET_INPUT_EMBEDDED_PROC_TYPE_NETCTRL \
52654 /* RoCE control processor */
52655 #define HWRM_FW_RESET_INPUT_EMBEDDED_PROC_TYPE_ROCE \
52658 * Host (in multi-host environment): This is only valid if requester is IPC.
52659 * Reinit host hardware resources and PCIe.
52661 #define HWRM_FW_RESET_INPUT_EMBEDDED_PROC_TYPE_HOST \
52664 * AP processor complex (in multi-host environment).
52665 * Use host_idx to control which core is reset
52667 #define HWRM_FW_RESET_INPUT_EMBEDDED_PROC_TYPE_AP \
52669 /* Reset all blocks of the chip (including all processors) */
52670 #define HWRM_FW_RESET_INPUT_EMBEDDED_PROC_TYPE_CHIP \
52673 * Host (in multi-host environment): This is only valid if requester is IPC.
52674 * Reinit host hardware resources.
52676 #define HWRM_FW_RESET_INPUT_EMBEDDED_PROC_TYPE_HOST_RESOURCE_REINIT \
52678 #define HWRM_FW_RESET_INPUT_EMBEDDED_PROC_TYPE_LAST \
52679 HWRM_FW_RESET_INPUT_EMBEDDED_PROC_TYPE_HOST_RESOURCE_REINIT
52680 /* Type of self reset. */
52681 uint8_t selfrst_status;
52682 /* No Self Reset */
52683 #define HWRM_FW_RESET_INPUT_SELFRST_STATUS_SELFRSTNONE \
52685 /* Self Reset as soon as possible to do so safely */
52686 #define HWRM_FW_RESET_INPUT_SELFRST_STATUS_SELFRSTASAP \
52688 /* Self Reset on PCIe Reset */
52689 #define HWRM_FW_RESET_INPUT_SELFRST_STATUS_SELFRSTPCIERST \
52691 /* Self Reset immediately after notification to all clients. */
52692 #define HWRM_FW_RESET_INPUT_SELFRST_STATUS_SELFRSTIMMEDIATE \
52694 #define HWRM_FW_RESET_INPUT_SELFRST_STATUS_LAST \
52695 HWRM_FW_RESET_INPUT_SELFRST_STATUS_SELFRSTIMMEDIATE
52697 * Indicate which host is being reset. 0 means first host.
52698 * Only valid when embedded_proc_type is host in multihost
52704 * When this bit is '1', then the core firmware initiates
52705 * the reset only after graceful shut down of all registered instances.
52706 * If not, the device will continue with the existing firmware.
52708 #define HWRM_FW_RESET_INPUT_FLAGS_RESET_GRACEFUL UINT32_C(0x1)
52709 uint8_t unused_0[4];
52712 /* hwrm_fw_reset_output (size:128b/16B) */
52713 struct hwrm_fw_reset_output {
52714 /* The specific error status for the command. */
52715 uint16_t error_code;
52716 /* The HWRM command request type. */
52718 /* The sequence ID from the original command. */
52720 /* The length of the response data in number of bytes. */
52722 /* Type of self reset. */
52723 uint8_t selfrst_status;
52724 /* No Self Reset */
52725 #define HWRM_FW_RESET_OUTPUT_SELFRST_STATUS_SELFRSTNONE \
52727 /* Self Reset as soon as possible to do so safely */
52728 #define HWRM_FW_RESET_OUTPUT_SELFRST_STATUS_SELFRSTASAP \
52730 /* Self Reset on PCIe Reset */
52731 #define HWRM_FW_RESET_OUTPUT_SELFRST_STATUS_SELFRSTPCIERST \
52733 /* Self Reset immediately after notification to all clients. */
52734 #define HWRM_FW_RESET_OUTPUT_SELFRST_STATUS_SELFRSTIMMEDIATE \
52736 #define HWRM_FW_RESET_OUTPUT_SELFRST_STATUS_LAST \
52737 HWRM_FW_RESET_OUTPUT_SELFRST_STATUS_SELFRSTIMMEDIATE
52738 uint8_t unused_0[6];
52740 * This field is used in Output records to indicate that the output
52741 * is completely written to RAM. This field should be read as '1'
52742 * to indicate that the output has been completely written.
52743 * When writing a command completion or response to an internal processor,
52744 * the order of writes has to be such that this field is written last.
52749 /**********************
52750 * hwrm_port_ts_query *
52751 ***********************/
52754 /* hwrm_port_ts_query_input (size:192b/24B) */
52755 struct hwrm_port_ts_query_input {
52756 /* The HWRM command request type. */
52759 * The completion ring to send the completion event on. This should
52760 * be the NQ ID returned from the `nq_alloc` HWRM command.
52762 uint16_t cmpl_ring;
52764 * The sequence ID is used by the driver for tracking multiple
52765 * commands. This ID is treated as opaque data by the firmware and
52766 * the value is returned in the `hwrm_resp_hdr` upon completion.
52770 * The target ID of the command:
52771 * * 0x0-0xFFF8 - The function ID
52772 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
52773 * * 0xFFFD - Reserved for user-space HWRM interface
52776 uint16_t target_id;
52778 * A physical address pointer pointing to a host buffer that the
52779 * command's response data will be written. This can be either a host
52780 * physical address (HPA) or a guest physical address (GPA) and must
52781 * point to a physically contiguous block of memory.
52783 uint64_t resp_addr;
52786 * Enumeration denoting the RX, TX type of the resource.
52787 * This enumeration is used for resources that are similar for both
52788 * TX and RX paths of the chip.
52790 #define HWRM_PORT_TS_QUERY_INPUT_FLAGS_PATH 0x1UL
52792 #define HWRM_PORT_TS_QUERY_INPUT_FLAGS_PATH_TX 0x0UL
52794 #define HWRM_PORT_TS_QUERY_INPUT_FLAGS_PATH_RX 0x1UL
52795 #define HWRM_PORT_TS_QUERY_INPUT_FLAGS_PATH_LAST \
52796 HWRM_PORT_TS_QUERY_INPUT_FLAGS_PATH_RX
52798 * If set, the response includes the current value of the free
52801 #define HWRM_PORT_TS_QUERY_INPUT_FLAGS_CURRENT_TIME 0x2UL
52802 /* Port ID of port that is being queried. */
52804 uint8_t unused_0[2];
52807 /* hwrm_port_ts_query_output (size:192b/24B) */
52808 struct hwrm_port_ts_query_output {
52809 /* The specific error status for the command. */
52810 uint16_t error_code;
52811 /* The HWRM command request type. */
52813 /* The sequence ID from the original command. */
52815 /* The length of the response data in number of bytes. */
52818 * Timestamp value of PTP message captured, or current value of
52819 * free running timer.
52821 uint32_t ptp_msg_ts[2];
52822 /* Sequence ID of the PTP message captured. */
52823 uint16_t ptp_msg_seqid;
52824 uint8_t unused_0[5];
52826 * This field is used in Output records to indicate that the output
52827 * is completely written to RAM. This field should be read as '1'
52828 * to indicate that the output has been completely written.
52829 * When writing a command completion or response to an internal processor,
52830 * the order of writes has to be such that this field is written last.
52836 * This structure is fixed at the beginning of the ChiMP SRAM (GRC
52837 * offset: 0x31001F0). Host software is expected to read from this
52838 * location for a defined signature. If it exists, the software can
52839 * assume the presence of this structure and the validity of the
52840 * FW_STATUS location in the next field.
52842 /* hcomm_status (size:64b/8B) */
52843 struct hcomm_status {
52846 * This field defines the version of the structure. The latest
52847 * version value is 1.
52849 #define HCOMM_STATUS_VER_MASK UINT32_C(0xff)
52850 #define HCOMM_STATUS_VER_SFT 0
52851 #define HCOMM_STATUS_VER_LATEST UINT32_C(0x1)
52852 #define HCOMM_STATUS_VER_LAST HCOMM_STATUS_VER_LATEST
52854 * This field is to store the signature value to indicate the
52855 * presence of the structure.
52857 #define HCOMM_STATUS_SIGNATURE_MASK UINT32_C(0xffffff00)
52858 #define HCOMM_STATUS_SIGNATURE_SFT 8
52859 #define HCOMM_STATUS_SIGNATURE_VAL (UINT32_C(0x484353) << 8)
52860 #define HCOMM_STATUS_SIGNATURE_LAST HCOMM_STATUS_SIGNATURE_VAL
52861 uint32_t fw_status_loc;
52862 #define HCOMM_STATUS_TRUE_ADDR_SPACE_MASK UINT32_C(0x3)
52863 #define HCOMM_STATUS_TRUE_ADDR_SPACE_SFT 0
52864 /* PCIE configuration space */
52865 #define HCOMM_STATUS_FW_STATUS_LOC_ADDR_SPACE_PCIE_CFG UINT32_C(0x0)
52867 #define HCOMM_STATUS_FW_STATUS_LOC_ADDR_SPACE_GRC UINT32_C(0x1)
52869 #define HCOMM_STATUS_FW_STATUS_LOC_ADDR_SPACE_BAR0 UINT32_C(0x2)
52871 #define HCOMM_STATUS_FW_STATUS_LOC_ADDR_SPACE_BAR1 UINT32_C(0x3)
52872 #define HCOMM_STATUS_FW_STATUS_LOC_ADDR_SPACE_LAST \
52873 HCOMM_STATUS_FW_STATUS_LOC_ADDR_SPACE_BAR1
52875 * This offset where the fw_status register is located. The value
52876 * is generally 4-byte aligned.
52878 #define HCOMM_STATUS_TRUE_OFFSET_MASK UINT32_C(0xfffffffc)
52879 #define HCOMM_STATUS_TRUE_OFFSET_SFT 2
52881 /* This is the GRC offset where the hcomm_status struct resides. */
52882 #define HCOMM_STATUS_STRUCT_LOC 0x31001F0UL
52884 /**************************
52885 * hwrm_port_phy_i2c_read *
52886 **************************/
52889 /* hwrm_port_phy_i2c_read_input (size:320b/40B) */
52890 struct hwrm_port_phy_i2c_read_input {
52891 /* The HWRM command request type. */
52894 * The completion ring to send the completion event on. This should
52895 * be the NQ ID returned from the `nq_alloc` HWRM command.
52897 uint16_t cmpl_ring;
52899 * The sequence ID is used by the driver for tracking multiple
52900 * commands. This ID is treated as opaque data by the firmware and
52901 * the value is returned in the `hwrm_resp_hdr` upon completion.
52905 * The target ID of the command:
52906 * * 0x0-0xFFF8 - The function ID
52907 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
52908 * * 0xFFFD - Reserved for user-space HWRM interface
52911 uint16_t target_id;
52913 * A physical address pointer pointing to a host buffer that the
52914 * command's response data will be written. This can be either a host
52915 * physical address (HPA) or a guest physical address (GPA) and must
52916 * point to a physically contiguous block of memory.
52918 uint64_t resp_addr;
52922 * This bit must be '1' for the page_offset field to be
52925 #define HWRM_PORT_PHY_I2C_READ_INPUT_ENABLES_PAGE_OFFSET 0x1UL
52926 /* Port ID of port. */
52928 /* 8-bit I2C slave address. */
52929 uint8_t i2c_slave_addr;
52931 /* The page number that is being accessed over I2C. */
52932 uint16_t page_number;
52933 /* Offset within the page that is being accessed over I2C. */
52934 uint16_t page_offset;
52936 * Length of data to read, in bytes starting at the offset
52937 * specified above. If the offset is not specified, then
52938 * the data shall be read from the beginning of the page.
52940 uint8_t data_length;
52941 uint8_t unused_1[7];
52944 /* hwrm_port_phy_i2c_read_output (size:640b/80B) */
52945 struct hwrm_port_phy_i2c_read_output {
52946 /* The specific error status for the command. */
52947 uint16_t error_code;
52948 /* The HWRM command request type. */
52950 /* The sequence ID from the original command. */
52952 /* The length of the response data in number of bytes. */
52954 /* Up to 64B of data. */
52956 uint8_t unused_0[7];
52958 * This field is used in Output records to indicate that the output
52959 * is completely written to RAM. This field should be read as '1'
52960 * to indicate that the output has been completely written.
52961 * When writing a command completion or response to an internal processor,
52962 * the order of writes has to be such that this field is written last.
52966 #endif /* _HSI_STRUCT_DEF_DPDK_H_ */