1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright (c) 2014-2020 Broadcom Inc.
5 * DO NOT MODIFY!!! This file is automatically generated.
8 #ifndef _HSI_STRUCT_DEF_DPDK_H_
9 #define _HSI_STRUCT_DEF_DPDK_H_
11 /* This is the HWRM command header. */
12 /* hwrm_cmd_hdr (size:128b/16B) */
14 /* The HWRM command request type. */
17 * The completion ring to send the completion event on. This should
18 * be the NQ ID returned from the `nq_alloc` HWRM command.
22 * The sequence ID is used by the driver for tracking multiple
23 * commands. This ID is treated as opaque data by the firmware and
24 * the value is returned in the `hwrm_resp_hdr` upon completion.
28 * The target ID of the command:
29 * * 0x0-0xFFF8 - The function ID
30 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
31 * * 0xFFFD - Reserved for user-space HWRM interface
36 * A physical address pointer pointing to a host buffer that the
37 * command's response data will be written. This can be either a host
38 * physical address (HPA) or a guest physical address (GPA) and must
39 * point to a physically contiguous block of memory.
44 /* This is the HWRM response header. */
45 /* hwrm_resp_hdr (size:64b/8B) */
46 struct hwrm_resp_hdr {
47 /* The specific error status for the command. */
49 /* The HWRM command request type. */
51 /* The sequence ID from the original command. */
53 /* The length of the response data in number of bytes. */
58 * TLV encapsulated message. Use the TLV type field of the
59 * TLV to determine the type of message encapsulated.
61 #define CMD_DISCR_TLV_ENCAP UINT32_C(0x8000)
62 #define CMD_DISCR_LAST CMD_DISCR_TLV_ENCAP
65 /* HWRM request message */
66 #define TLV_TYPE_HWRM_REQUEST UINT32_C(0x1)
67 /* HWRM response message */
68 #define TLV_TYPE_HWRM_RESPONSE UINT32_C(0x2)
69 /* RoCE slow path command */
70 #define TLV_TYPE_ROCE_SP_COMMAND UINT32_C(0x3)
71 /* RoCE slow path command to query CC Gen1 support. */
72 #define TLV_TYPE_QUERY_ROCE_CC_GEN1 UINT32_C(0x4)
73 /* RoCE slow path command to modify CC Gen1 support. */
74 #define TLV_TYPE_MODIFY_ROCE_CC_GEN1 UINT32_C(0x5)
75 /* Engine CKV - The Alias key EC curve and ECC public key information. */
76 #define TLV_TYPE_ENGINE_CKV_ALIAS_ECC_PUBLIC_KEY UINT32_C(0x8001)
77 /* Engine CKV - Initialization vector. */
78 #define TLV_TYPE_ENGINE_CKV_IV UINT32_C(0x8003)
79 /* Engine CKV - Authentication tag. */
80 #define TLV_TYPE_ENGINE_CKV_AUTH_TAG UINT32_C(0x8004)
81 /* Engine CKV - The encrypted data. */
82 #define TLV_TYPE_ENGINE_CKV_CIPHERTEXT UINT32_C(0x8005)
83 /* Engine CKV - Supported host_algorithms. */
84 #define TLV_TYPE_ENGINE_CKV_HOST_ALGORITHMS UINT32_C(0x8006)
85 /* Engine CKV - The Host EC curve name and ECC public key information. */
86 #define TLV_TYPE_ENGINE_CKV_HOST_ECC_PUBLIC_KEY UINT32_C(0x8007)
87 /* Engine CKV - The ECDSA signature. */
88 #define TLV_TYPE_ENGINE_CKV_ECDSA_SIGNATURE UINT32_C(0x8008)
89 /* Engine CKV - The firmware EC curve name and ECC public key information. */
90 #define TLV_TYPE_ENGINE_CKV_FW_ECC_PUBLIC_KEY UINT32_C(0x8009)
91 /* Engine CKV - Supported firmware algorithms. */
92 #define TLV_TYPE_ENGINE_CKV_FW_ALGORITHMS UINT32_C(0x800a)
93 #define TLV_TYPE_LAST \
94 TLV_TYPE_ENGINE_CKV_FW_ALGORITHMS
97 /* tlv (size:64b/8B) */
100 * The command discriminator is used to differentiate between various
101 * types of HWRM messages. This includes legacy HWRM and RoCE slowpath
102 * command messages as well as newer TLV encapsulated HWRM commands.
104 * For TLV encapsulated messages this field must be 0x8000.
110 * Indicates the presence of additional TLV encapsulated data
113 #define TLV_FLAGS_MORE UINT32_C(0x1)
114 /* Last TLV in a sequence of TLVs. */
115 #define TLV_FLAGS_MORE_LAST UINT32_C(0x0)
116 /* More TLVs follow this TLV. */
117 #define TLV_FLAGS_MORE_NOT_LAST UINT32_C(0x1)
119 * When an HWRM receiver detects a TLV type that it does not
120 * support with the TLV required flag set, the receiver must
121 * reject the HWRM message with an error code indicating an
122 * unsupported TLV type.
124 #define TLV_FLAGS_REQUIRED UINT32_C(0x2)
126 #define TLV_FLAGS_REQUIRED_NO (UINT32_C(0x0) << 1)
128 #define TLV_FLAGS_REQUIRED_YES (UINT32_C(0x1) << 1)
129 #define TLV_FLAGS_REQUIRED_LAST TLV_FLAGS_REQUIRED_YES
131 * This field defines the TLV type value which is divided into
132 * two ranges to differentiate between global and local TLV types.
133 * Global TLV types must be unique across all defined TLV types.
134 * Local TLV types are valid only for extensions to a given
135 * HWRM message and may be repeated across different HWRM message
136 * types. There is a direct correlation of each HWRM message type
137 * to a single global TLV type value.
139 * Global TLV range: `0 - (63k-1)`
141 * Local TLV range: `63k - (64k-1)`
145 * Length of the message data encapsulated by this TLV in bytes.
146 * This length does not include the size of the TLV header itself
147 * and it must be an integer multiple of 8B.
153 /* input (size:128b/16B) */
156 * This value indicates what type of request this is. The format
157 * for the rest of the command is determined by this field.
161 * This value indicates the what completion ring the request will
162 * be optionally completed on. If the value is -1, then no
163 * CR completion will be generated. Any other value must be a
164 * valid CR ring_id value for this function.
167 /* This value indicates the command sequence number. */
170 * Target ID of this command.
172 * 0x0 - 0xFFF8 - Used for function ids
173 * 0xFFF8 - 0xFFFE - Reserved for internal processors
178 * This is the host address where the response will be written
179 * when the request is complete. This area must be 16B aligned
180 * and must be cleared to zero before the request is made.
186 /* output (size:64b/8B) */
189 * Pass/Fail or error type
191 * Note: receiver to verify the in parameters, and fail the call
192 * with an error when appropriate
195 /* This field returns the type of original request. */
197 /* This field provides original sequence number of the command. */
200 * This field is the length of the response in bytes. The
201 * last byte of the response is a valid flag that will read
202 * as '1' when the command has been completely written to
208 /* Short Command Structure */
209 /* hwrm_short_input (size:128b/16B) */
210 struct hwrm_short_input {
212 * This field indicates the type of request in the request buffer.
213 * The format for the rest of the command (request) is determined
218 * This field indicates a signature that is used to identify short
219 * form of the command listed here. This field shall be set to
223 /* Signature indicating this is a short form of HWRM command */
224 #define HWRM_SHORT_INPUT_SIGNATURE_SHORT_CMD UINT32_C(0x4321)
225 #define HWRM_SHORT_INPUT_SIGNATURE_LAST \
226 HWRM_SHORT_INPUT_SIGNATURE_SHORT_CMD
227 /* The target ID of the command */
229 /* Default target_id (0x0) to maintain compatibility with old driver */
230 #define HWRM_SHORT_INPUT_TARGET_ID_DEFAULT UINT32_C(0x0)
231 /* Reserved for user-space HWRM interface */
232 #define HWRM_SHORT_INPUT_TARGET_ID_TOOLS UINT32_C(0xfffd)
233 #define HWRM_SHORT_INPUT_TARGET_ID_LAST \
234 HWRM_SHORT_INPUT_TARGET_ID_TOOLS
235 /* This value indicates the length of the request. */
238 * This is the host address where the request was written.
239 * This area must be 16B aligned.
246 * # NOTE - definitions already in hwrm_req_type, in hwrm_types.yaml
247 * # So only structure definition is provided here.
249 /* cmd_nums (size:64b/8B) */
252 * This version of the specification defines the commands listed in
253 * the table below. The following are general implementation
254 * requirements for these commands:
256 * # All commands listed below that are marked neither
257 * reserved nor experimental shall be implemented by the HWRM.
258 * # A HWRM client compliant to this specification should not use
259 * commands outside of the list below.
260 * # A HWRM client compliant to this specification should not use
261 * command numbers marked reserved below.
262 * # A command marked experimental below may not be implemented
264 * # A command marked experimental may change in the
265 * future version of the HWRM specification.
266 * # A command not listed below may be implemented by the HWRM.
267 * The behavior of commands that are not listed below is outside
268 * the scope of this specification.
271 #define HWRM_VER_GET UINT32_C(0x0)
272 #define HWRM_ERROR_RECOVERY_QCFG UINT32_C(0xc)
273 #define HWRM_FUNC_DRV_IF_CHANGE UINT32_C(0xd)
274 #define HWRM_FUNC_BUF_UNRGTR UINT32_C(0xe)
275 #define HWRM_FUNC_VF_CFG UINT32_C(0xf)
276 /* Reserved for future use. */
277 #define HWRM_RESERVED1 UINT32_C(0x10)
278 #define HWRM_FUNC_RESET UINT32_C(0x11)
279 #define HWRM_FUNC_GETFID UINT32_C(0x12)
280 #define HWRM_FUNC_VF_ALLOC UINT32_C(0x13)
281 #define HWRM_FUNC_VF_FREE UINT32_C(0x14)
282 #define HWRM_FUNC_QCAPS UINT32_C(0x15)
283 #define HWRM_FUNC_QCFG UINT32_C(0x16)
284 #define HWRM_FUNC_CFG UINT32_C(0x17)
285 #define HWRM_FUNC_QSTATS UINT32_C(0x18)
286 #define HWRM_FUNC_CLR_STATS UINT32_C(0x19)
287 #define HWRM_FUNC_DRV_UNRGTR UINT32_C(0x1a)
288 #define HWRM_FUNC_VF_RESC_FREE UINT32_C(0x1b)
289 #define HWRM_FUNC_VF_VNIC_IDS_QUERY UINT32_C(0x1c)
290 #define HWRM_FUNC_DRV_RGTR UINT32_C(0x1d)
291 #define HWRM_FUNC_DRV_QVER UINT32_C(0x1e)
292 #define HWRM_FUNC_BUF_RGTR UINT32_C(0x1f)
293 #define HWRM_PORT_PHY_CFG UINT32_C(0x20)
294 #define HWRM_PORT_MAC_CFG UINT32_C(0x21)
296 #define HWRM_PORT_TS_QUERY UINT32_C(0x22)
297 #define HWRM_PORT_QSTATS UINT32_C(0x23)
298 #define HWRM_PORT_LPBK_QSTATS UINT32_C(0x24)
300 #define HWRM_PORT_CLR_STATS UINT32_C(0x25)
302 #define HWRM_PORT_LPBK_CLR_STATS UINT32_C(0x26)
303 #define HWRM_PORT_PHY_QCFG UINT32_C(0x27)
304 #define HWRM_PORT_MAC_QCFG UINT32_C(0x28)
306 #define HWRM_PORT_MAC_PTP_QCFG UINT32_C(0x29)
307 #define HWRM_PORT_PHY_QCAPS UINT32_C(0x2a)
308 #define HWRM_PORT_PHY_I2C_WRITE UINT32_C(0x2b)
309 #define HWRM_PORT_PHY_I2C_READ UINT32_C(0x2c)
310 #define HWRM_PORT_LED_CFG UINT32_C(0x2d)
311 #define HWRM_PORT_LED_QCFG UINT32_C(0x2e)
312 #define HWRM_PORT_LED_QCAPS UINT32_C(0x2f)
313 #define HWRM_QUEUE_QPORTCFG UINT32_C(0x30)
314 #define HWRM_QUEUE_QCFG UINT32_C(0x31)
315 #define HWRM_QUEUE_CFG UINT32_C(0x32)
316 #define HWRM_FUNC_VLAN_CFG UINT32_C(0x33)
317 #define HWRM_FUNC_VLAN_QCFG UINT32_C(0x34)
318 #define HWRM_QUEUE_PFCENABLE_QCFG UINT32_C(0x35)
319 #define HWRM_QUEUE_PFCENABLE_CFG UINT32_C(0x36)
320 #define HWRM_QUEUE_PRI2COS_QCFG UINT32_C(0x37)
321 #define HWRM_QUEUE_PRI2COS_CFG UINT32_C(0x38)
322 #define HWRM_QUEUE_COS2BW_QCFG UINT32_C(0x39)
323 #define HWRM_QUEUE_COS2BW_CFG UINT32_C(0x3a)
324 #define HWRM_QUEUE_DSCP_QCAPS UINT32_C(0x3b)
325 #define HWRM_QUEUE_DSCP2PRI_QCFG UINT32_C(0x3c)
326 #define HWRM_QUEUE_DSCP2PRI_CFG UINT32_C(0x3d)
327 #define HWRM_VNIC_ALLOC UINT32_C(0x40)
328 #define HWRM_VNIC_FREE UINT32_C(0x41)
329 #define HWRM_VNIC_CFG UINT32_C(0x42)
330 #define HWRM_VNIC_QCFG UINT32_C(0x43)
331 #define HWRM_VNIC_TPA_CFG UINT32_C(0x44)
333 #define HWRM_VNIC_TPA_QCFG UINT32_C(0x45)
334 #define HWRM_VNIC_RSS_CFG UINT32_C(0x46)
335 #define HWRM_VNIC_RSS_QCFG UINT32_C(0x47)
336 #define HWRM_VNIC_PLCMODES_CFG UINT32_C(0x48)
337 #define HWRM_VNIC_PLCMODES_QCFG UINT32_C(0x49)
338 #define HWRM_VNIC_QCAPS UINT32_C(0x4a)
339 #define HWRM_RING_ALLOC UINT32_C(0x50)
340 #define HWRM_RING_FREE UINT32_C(0x51)
341 #define HWRM_RING_CMPL_RING_QAGGINT_PARAMS UINT32_C(0x52)
342 #define HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS UINT32_C(0x53)
343 #define HWRM_RING_AGGINT_QCAPS UINT32_C(0x54)
344 #define HWRM_RING_SCHQ_ALLOC UINT32_C(0x55)
345 #define HWRM_RING_SCHQ_CFG UINT32_C(0x56)
346 #define HWRM_RING_SCHQ_FREE UINT32_C(0x57)
347 #define HWRM_RING_RESET UINT32_C(0x5e)
348 #define HWRM_RING_GRP_ALLOC UINT32_C(0x60)
349 #define HWRM_RING_GRP_FREE UINT32_C(0x61)
350 #define HWRM_RING_CFG UINT32_C(0x62)
351 #define HWRM_RING_QCFG UINT32_C(0x63)
352 /* Reserved for future use. */
353 #define HWRM_RESERVED5 UINT32_C(0x64)
354 /* Reserved for future use. */
355 #define HWRM_RESERVED6 UINT32_C(0x65)
356 #define HWRM_VNIC_RSS_COS_LB_CTX_ALLOC UINT32_C(0x70)
357 #define HWRM_VNIC_RSS_COS_LB_CTX_FREE UINT32_C(0x71)
358 #define HWRM_QUEUE_MPLS_QCAPS UINT32_C(0x80)
359 #define HWRM_QUEUE_MPLSTC2PRI_QCFG UINT32_C(0x81)
360 #define HWRM_QUEUE_MPLSTC2PRI_CFG UINT32_C(0x82)
361 #define HWRM_CFA_L2_FILTER_ALLOC UINT32_C(0x90)
362 #define HWRM_CFA_L2_FILTER_FREE UINT32_C(0x91)
363 #define HWRM_CFA_L2_FILTER_CFG UINT32_C(0x92)
364 #define HWRM_CFA_L2_SET_RX_MASK UINT32_C(0x93)
365 #define HWRM_CFA_VLAN_ANTISPOOF_CFG UINT32_C(0x94)
366 #define HWRM_CFA_TUNNEL_FILTER_ALLOC UINT32_C(0x95)
367 #define HWRM_CFA_TUNNEL_FILTER_FREE UINT32_C(0x96)
369 #define HWRM_CFA_ENCAP_RECORD_ALLOC UINT32_C(0x97)
371 #define HWRM_CFA_ENCAP_RECORD_FREE UINT32_C(0x98)
372 #define HWRM_CFA_NTUPLE_FILTER_ALLOC UINT32_C(0x99)
373 #define HWRM_CFA_NTUPLE_FILTER_FREE UINT32_C(0x9a)
374 #define HWRM_CFA_NTUPLE_FILTER_CFG UINT32_C(0x9b)
376 #define HWRM_CFA_EM_FLOW_ALLOC UINT32_C(0x9c)
378 #define HWRM_CFA_EM_FLOW_FREE UINT32_C(0x9d)
380 #define HWRM_CFA_EM_FLOW_CFG UINT32_C(0x9e)
381 #define HWRM_TUNNEL_DST_PORT_QUERY UINT32_C(0xa0)
382 #define HWRM_TUNNEL_DST_PORT_ALLOC UINT32_C(0xa1)
383 #define HWRM_TUNNEL_DST_PORT_FREE UINT32_C(0xa2)
384 #define HWRM_STAT_CTX_ENG_QUERY UINT32_C(0xaf)
385 #define HWRM_STAT_CTX_ALLOC UINT32_C(0xb0)
386 #define HWRM_STAT_CTX_FREE UINT32_C(0xb1)
387 #define HWRM_STAT_CTX_QUERY UINT32_C(0xb2)
388 #define HWRM_STAT_CTX_CLR_STATS UINT32_C(0xb3)
389 #define HWRM_PORT_QSTATS_EXT UINT32_C(0xb4)
390 #define HWRM_PORT_PHY_MDIO_WRITE UINT32_C(0xb5)
391 #define HWRM_PORT_PHY_MDIO_READ UINT32_C(0xb6)
392 #define HWRM_PORT_PHY_MDIO_BUS_ACQUIRE UINT32_C(0xb7)
393 #define HWRM_PORT_PHY_MDIO_BUS_RELEASE UINT32_C(0xb8)
394 #define HWRM_PORT_QSTATS_EXT_PFC_WD UINT32_C(0xb9)
395 #define HWRM_PORT_ECN_QSTATS UINT32_C(0xba)
396 #define HWRM_FW_RESET UINT32_C(0xc0)
397 #define HWRM_FW_QSTATUS UINT32_C(0xc1)
398 #define HWRM_FW_HEALTH_CHECK UINT32_C(0xc2)
399 #define HWRM_FW_SYNC UINT32_C(0xc3)
400 #define HWRM_FW_STATE_QCAPS UINT32_C(0xc4)
401 #define HWRM_FW_STATE_QUIESCE UINT32_C(0xc5)
402 #define HWRM_FW_STATE_BACKUP UINT32_C(0xc6)
403 #define HWRM_FW_STATE_RESTORE UINT32_C(0xc7)
405 #define HWRM_FW_SET_TIME UINT32_C(0xc8)
407 #define HWRM_FW_GET_TIME UINT32_C(0xc9)
409 #define HWRM_FW_SET_STRUCTURED_DATA UINT32_C(0xca)
411 #define HWRM_FW_GET_STRUCTURED_DATA UINT32_C(0xcb)
413 #define HWRM_FW_IPC_MAILBOX UINT32_C(0xcc)
414 #define HWRM_FW_ECN_CFG UINT32_C(0xcd)
415 #define HWRM_FW_ECN_QCFG UINT32_C(0xce)
416 #define HWRM_FW_SECURE_CFG UINT32_C(0xcf)
417 #define HWRM_EXEC_FWD_RESP UINT32_C(0xd0)
418 #define HWRM_REJECT_FWD_RESP UINT32_C(0xd1)
419 #define HWRM_FWD_RESP UINT32_C(0xd2)
420 #define HWRM_FWD_ASYNC_EVENT_CMPL UINT32_C(0xd3)
421 #define HWRM_OEM_CMD UINT32_C(0xd4)
422 /* Tells the fw to run PRBS test on a given port and lane. */
423 #define HWRM_PORT_PRBS_TEST UINT32_C(0xd5)
424 #define HWRM_PORT_SFP_SIDEBAND_CFG UINT32_C(0xd6)
425 #define HWRM_PORT_SFP_SIDEBAND_QCFG UINT32_C(0xd7)
426 #define HWRM_FW_STATE_UNQUIESCE UINT32_C(0xd8)
427 /* Tells the fw to collect dsc dump on a given port and lane. */
428 #define HWRM_PORT_DSC_DUMP UINT32_C(0xd9)
429 #define HWRM_TEMP_MONITOR_QUERY UINT32_C(0xe0)
430 #define HWRM_REG_POWER_QUERY UINT32_C(0xe1)
431 #define HWRM_CORE_FREQUENCY_QUERY UINT32_C(0xe2)
432 #define HWRM_REG_POWER_HISTOGRAM UINT32_C(0xe3)
433 #define HWRM_WOL_FILTER_ALLOC UINT32_C(0xf0)
434 #define HWRM_WOL_FILTER_FREE UINT32_C(0xf1)
435 #define HWRM_WOL_FILTER_QCFG UINT32_C(0xf2)
436 #define HWRM_WOL_REASON_QCFG UINT32_C(0xf3)
438 #define HWRM_CFA_METER_QCAPS UINT32_C(0xf4)
440 #define HWRM_CFA_METER_PROFILE_ALLOC UINT32_C(0xf5)
442 #define HWRM_CFA_METER_PROFILE_FREE UINT32_C(0xf6)
444 #define HWRM_CFA_METER_PROFILE_CFG UINT32_C(0xf7)
446 #define HWRM_CFA_METER_INSTANCE_ALLOC UINT32_C(0xf8)
448 #define HWRM_CFA_METER_INSTANCE_FREE UINT32_C(0xf9)
450 #define HWRM_CFA_METER_INSTANCE_CFG UINT32_C(0xfa)
452 #define HWRM_CFA_VFR_ALLOC UINT32_C(0xfd)
454 #define HWRM_CFA_VFR_FREE UINT32_C(0xfe)
456 #define HWRM_CFA_VF_PAIR_ALLOC UINT32_C(0x100)
458 #define HWRM_CFA_VF_PAIR_FREE UINT32_C(0x101)
460 #define HWRM_CFA_VF_PAIR_INFO UINT32_C(0x102)
462 #define HWRM_CFA_FLOW_ALLOC UINT32_C(0x103)
464 #define HWRM_CFA_FLOW_FREE UINT32_C(0x104)
466 #define HWRM_CFA_FLOW_FLUSH UINT32_C(0x105)
468 #define HWRM_CFA_FLOW_STATS UINT32_C(0x106)
470 #define HWRM_CFA_FLOW_INFO UINT32_C(0x107)
472 #define HWRM_CFA_DECAP_FILTER_ALLOC UINT32_C(0x108)
474 #define HWRM_CFA_DECAP_FILTER_FREE UINT32_C(0x109)
475 #define HWRM_CFA_VLAN_ANTISPOOF_QCFG UINT32_C(0x10a)
476 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_ALLOC UINT32_C(0x10b)
477 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_FREE UINT32_C(0x10c)
479 #define HWRM_CFA_PAIR_ALLOC UINT32_C(0x10d)
481 #define HWRM_CFA_PAIR_FREE UINT32_C(0x10e)
483 #define HWRM_CFA_PAIR_INFO UINT32_C(0x10f)
485 #define HWRM_FW_IPC_MSG UINT32_C(0x110)
486 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_INFO UINT32_C(0x111)
487 #define HWRM_CFA_REDIRECT_QUERY_TUNNEL_TYPE UINT32_C(0x112)
489 #define HWRM_CFA_FLOW_AGING_TIMER_RESET UINT32_C(0x113)
491 #define HWRM_CFA_FLOW_AGING_CFG UINT32_C(0x114)
493 #define HWRM_CFA_FLOW_AGING_QCFG UINT32_C(0x115)
495 #define HWRM_CFA_FLOW_AGING_QCAPS UINT32_C(0x116)
497 #define HWRM_CFA_CTX_MEM_RGTR UINT32_C(0x117)
499 #define HWRM_CFA_CTX_MEM_UNRGTR UINT32_C(0x118)
501 #define HWRM_CFA_CTX_MEM_QCTX UINT32_C(0x119)
503 #define HWRM_CFA_CTX_MEM_QCAPS UINT32_C(0x11a)
505 #define HWRM_CFA_COUNTER_QCAPS UINT32_C(0x11b)
507 #define HWRM_CFA_COUNTER_CFG UINT32_C(0x11c)
509 #define HWRM_CFA_COUNTER_QCFG UINT32_C(0x11d)
511 #define HWRM_CFA_COUNTER_QSTATS UINT32_C(0x11e)
513 #define HWRM_CFA_TCP_FLAG_PROCESS_QCFG UINT32_C(0x11f)
515 #define HWRM_CFA_EEM_QCAPS UINT32_C(0x120)
517 #define HWRM_CFA_EEM_CFG UINT32_C(0x121)
519 #define HWRM_CFA_EEM_QCFG UINT32_C(0x122)
521 #define HWRM_CFA_EEM_OP UINT32_C(0x123)
523 #define HWRM_CFA_ADV_FLOW_MGNT_QCAPS UINT32_C(0x124)
524 /* Experimental - DEPRECATED */
525 #define HWRM_CFA_TFLIB UINT32_C(0x125)
526 /* Engine CKV - Get the current allocation status of keys provisioned in the key vault. */
527 #define HWRM_ENGINE_CKV_STATUS UINT32_C(0x12e)
528 /* Engine CKV - Add a new CKEK used to encrypt keys. */
529 #define HWRM_ENGINE_CKV_CKEK_ADD UINT32_C(0x12f)
530 /* Engine CKV - Delete a previously added CKEK. */
531 #define HWRM_ENGINE_CKV_CKEK_DELETE UINT32_C(0x130)
532 /* Engine CKV - Add a new key to the key vault. */
533 #define HWRM_ENGINE_CKV_KEY_ADD UINT32_C(0x131)
534 /* Engine CKV - Delete a key from the key vault. */
535 #define HWRM_ENGINE_CKV_KEY_DELETE UINT32_C(0x132)
536 /* Engine CKV - Delete all keys from the key vault. */
537 #define HWRM_ENGINE_CKV_FLUSH UINT32_C(0x133)
538 /* Engine CKV - Get random data. */
539 #define HWRM_ENGINE_CKV_RNG_GET UINT32_C(0x134)
540 /* Engine CKV - Generate and encrypt a new AES key. */
541 #define HWRM_ENGINE_CKV_KEY_GEN UINT32_C(0x135)
542 /* Engine CKV - Configure a label index with a label value. */
543 #define HWRM_ENGINE_CKV_KEY_LABEL_CFG UINT32_C(0x136)
544 /* Engine CKV - Query a label */
545 #define HWRM_ENGINE_CKV_KEY_LABEL_QCFG UINT32_C(0x137)
546 /* Engine - Query the available queue groups configuration. */
547 #define HWRM_ENGINE_QG_CONFIG_QUERY UINT32_C(0x13c)
548 /* Engine - Query the queue groups assigned to a function. */
549 #define HWRM_ENGINE_QG_QUERY UINT32_C(0x13d)
550 /* Engine - Query the available queue group meter profile configuration. */
551 #define HWRM_ENGINE_QG_METER_PROFILE_CONFIG_QUERY UINT32_C(0x13e)
552 /* Engine - Query the configuration of a queue group meter profile. */
553 #define HWRM_ENGINE_QG_METER_PROFILE_QUERY UINT32_C(0x13f)
554 /* Engine - Allocate a queue group meter profile. */
555 #define HWRM_ENGINE_QG_METER_PROFILE_ALLOC UINT32_C(0x140)
556 /* Engine - Free a queue group meter profile. */
557 #define HWRM_ENGINE_QG_METER_PROFILE_FREE UINT32_C(0x141)
558 /* Engine - Query the meters assigned to a queue group. */
559 #define HWRM_ENGINE_QG_METER_QUERY UINT32_C(0x142)
560 /* Engine - Bind a queue group meter profile to a queue group. */
561 #define HWRM_ENGINE_QG_METER_BIND UINT32_C(0x143)
562 /* Engine - Unbind a queue group meter profile from a queue group. */
563 #define HWRM_ENGINE_QG_METER_UNBIND UINT32_C(0x144)
564 /* Engine - Bind a queue group to a function. */
565 #define HWRM_ENGINE_QG_FUNC_BIND UINT32_C(0x145)
566 /* Engine - Query the scheduling group configuration. */
567 #define HWRM_ENGINE_SG_CONFIG_QUERY UINT32_C(0x146)
568 /* Engine - Query the queue groups assigned to a scheduling group. */
569 #define HWRM_ENGINE_SG_QUERY UINT32_C(0x147)
570 /* Engine - Query the configuration of a scheduling group's meter profiles. */
571 #define HWRM_ENGINE_SG_METER_QUERY UINT32_C(0x148)
572 /* Engine - Configure a scheduling group's meter profiles. */
573 #define HWRM_ENGINE_SG_METER_CONFIG UINT32_C(0x149)
574 /* Engine - Bind a queue group to a scheduling group. */
575 #define HWRM_ENGINE_SG_QG_BIND UINT32_C(0x14a)
576 /* Engine - Unbind a queue group from its scheduling group. */
577 #define HWRM_ENGINE_QG_SG_UNBIND UINT32_C(0x14b)
578 /* Engine - Query the Engine configuration. */
579 #define HWRM_ENGINE_CONFIG_QUERY UINT32_C(0x154)
580 /* Engine - Configure the statistics accumulator for an Engine. */
581 #define HWRM_ENGINE_STATS_CONFIG UINT32_C(0x155)
582 /* Engine - Clear the statistics accumulator for an Engine. */
583 #define HWRM_ENGINE_STATS_CLEAR UINT32_C(0x156)
584 /* Engine - Query the statistics accumulator for an Engine. */
585 #define HWRM_ENGINE_STATS_QUERY UINT32_C(0x157)
586 /* Engine - Query statistics counters for continuous errors from all CDDIP Engines. */
587 #define HWRM_ENGINE_STATS_QUERY_CONTINUOUS_ERROR UINT32_C(0x158)
588 /* Engine - Allocate an Engine RQ. */
589 #define HWRM_ENGINE_RQ_ALLOC UINT32_C(0x15e)
590 /* Engine - Free an Engine RQ. */
591 #define HWRM_ENGINE_RQ_FREE UINT32_C(0x15f)
592 /* Engine - Allocate an Engine CQ. */
593 #define HWRM_ENGINE_CQ_ALLOC UINT32_C(0x160)
594 /* Engine - Free an Engine CQ. */
595 #define HWRM_ENGINE_CQ_FREE UINT32_C(0x161)
596 /* Engine - Allocate an NQ. */
597 #define HWRM_ENGINE_NQ_ALLOC UINT32_C(0x162)
598 /* Engine - Free an NQ. */
599 #define HWRM_ENGINE_NQ_FREE UINT32_C(0x163)
600 /* Engine - Set the on-die RQE credit update location. */
601 #define HWRM_ENGINE_ON_DIE_RQE_CREDITS UINT32_C(0x164)
602 /* Engine - Query the engine function configuration. */
603 #define HWRM_ENGINE_FUNC_QCFG UINT32_C(0x165)
605 #define HWRM_FUNC_RESOURCE_QCAPS UINT32_C(0x190)
607 #define HWRM_FUNC_VF_RESOURCE_CFG UINT32_C(0x191)
609 #define HWRM_FUNC_BACKING_STORE_QCAPS UINT32_C(0x192)
611 #define HWRM_FUNC_BACKING_STORE_CFG UINT32_C(0x193)
613 #define HWRM_FUNC_BACKING_STORE_QCFG UINT32_C(0x194)
614 /* Configures the BW of any VF */
615 #define HWRM_FUNC_VF_BW_CFG UINT32_C(0x195)
616 /* Queries the BW of any VF */
617 #define HWRM_FUNC_VF_BW_QCFG UINT32_C(0x196)
618 /* Queries pf ids belong to specified host(s) */
619 #define HWRM_FUNC_HOST_PF_IDS_QUERY UINT32_C(0x197)
620 /* Queries extended stats per function */
621 #define HWRM_FUNC_QSTATS_EXT UINT32_C(0x198)
622 /* Queries extended statistics context */
623 #define HWRM_STAT_EXT_CTX_QUERY UINT32_C(0x199)
625 #define HWRM_SELFTEST_QLIST UINT32_C(0x200)
627 #define HWRM_SELFTEST_EXEC UINT32_C(0x201)
629 #define HWRM_SELFTEST_IRQ UINT32_C(0x202)
631 #define HWRM_SELFTEST_RETRIEVE_SERDES_DATA UINT32_C(0x203)
633 #define HWRM_PCIE_QSTATS UINT32_C(0x204)
635 #define HWRM_MFG_FRU_WRITE_CONTROL UINT32_C(0x205)
636 /* Returns the current value of a free running counter from the device. */
637 #define HWRM_MFG_TIMERS_QUERY UINT32_C(0x206)
639 #define HWRM_MFG_OTP_CFG UINT32_C(0x207)
641 #define HWRM_MFG_OTP_QCFG UINT32_C(0x208)
643 * Tells the fw to run the DMA read from the host and DMA write
646 #define HWRM_MFG_HDMA_TEST UINT32_C(0x209)
647 /* Tells the fw to program the fru memory */
648 #define HWRM_MFG_FRU_EEPROM_WRITE UINT32_C(0x20a)
649 /* Tells the fw to read the fru memory */
650 #define HWRM_MFG_FRU_EEPROM_READ UINT32_C(0x20b)
652 #define HWRM_TF UINT32_C(0x2bc)
654 #define HWRM_TF_VERSION_GET UINT32_C(0x2bd)
656 #define HWRM_TF_SESSION_OPEN UINT32_C(0x2c6)
658 #define HWRM_TF_SESSION_ATTACH UINT32_C(0x2c7)
660 #define HWRM_TF_SESSION_REGISTER UINT32_C(0x2c8)
662 #define HWRM_TF_SESSION_UNREGISTER UINT32_C(0x2c9)
664 #define HWRM_TF_SESSION_CLOSE UINT32_C(0x2ca)
666 #define HWRM_TF_SESSION_QCFG UINT32_C(0x2cb)
668 #define HWRM_TF_SESSION_RESC_QCAPS UINT32_C(0x2cc)
670 #define HWRM_TF_SESSION_RESC_ALLOC UINT32_C(0x2cd)
672 #define HWRM_TF_SESSION_RESC_FREE UINT32_C(0x2ce)
674 #define HWRM_TF_SESSION_RESC_FLUSH UINT32_C(0x2cf)
676 #define HWRM_TF_TBL_TYPE_GET UINT32_C(0x2da)
678 #define HWRM_TF_TBL_TYPE_SET UINT32_C(0x2db)
680 #define HWRM_TF_CTXT_MEM_RGTR UINT32_C(0x2e4)
682 #define HWRM_TF_CTXT_MEM_UNRGTR UINT32_C(0x2e5)
684 #define HWRM_TF_EXT_EM_QCAPS UINT32_C(0x2e6)
686 #define HWRM_TF_EXT_EM_OP UINT32_C(0x2e7)
688 #define HWRM_TF_EXT_EM_CFG UINT32_C(0x2e8)
690 #define HWRM_TF_EXT_EM_QCFG UINT32_C(0x2e9)
692 #define HWRM_TF_EM_INSERT UINT32_C(0x2ea)
694 #define HWRM_TF_EM_DELETE UINT32_C(0x2eb)
696 #define HWRM_TF_TCAM_SET UINT32_C(0x2f8)
698 #define HWRM_TF_TCAM_GET UINT32_C(0x2f9)
700 #define HWRM_TF_TCAM_MOVE UINT32_C(0x2fa)
702 #define HWRM_TF_TCAM_FREE UINT32_C(0x2fb)
704 #define HWRM_TF_GLOBAL_CFG_SET UINT32_C(0x2fc)
706 #define HWRM_TF_GLOBAL_CFG_GET UINT32_C(0x2fd)
708 #define HWRM_TF_IF_TBL_SET UINT32_C(0x2fe)
710 #define HWRM_TF_IF_TBL_GET UINT32_C(0x2ff)
712 #define HWRM_SV UINT32_C(0x400)
714 #define HWRM_DBG_READ_DIRECT UINT32_C(0xff10)
716 #define HWRM_DBG_READ_INDIRECT UINT32_C(0xff11)
718 #define HWRM_DBG_WRITE_DIRECT UINT32_C(0xff12)
720 #define HWRM_DBG_WRITE_INDIRECT UINT32_C(0xff13)
721 #define HWRM_DBG_DUMP UINT32_C(0xff14)
723 #define HWRM_DBG_ERASE_NVM UINT32_C(0xff15)
725 #define HWRM_DBG_CFG UINT32_C(0xff16)
727 #define HWRM_DBG_COREDUMP_LIST UINT32_C(0xff17)
729 #define HWRM_DBG_COREDUMP_INITIATE UINT32_C(0xff18)
731 #define HWRM_DBG_COREDUMP_RETRIEVE UINT32_C(0xff19)
733 #define HWRM_DBG_FW_CLI UINT32_C(0xff1a)
735 #define HWRM_DBG_I2C_CMD UINT32_C(0xff1b)
737 #define HWRM_DBG_RING_INFO_GET UINT32_C(0xff1c)
739 #define HWRM_DBG_CRASHDUMP_HEADER UINT32_C(0xff1d)
741 #define HWRM_DBG_CRASHDUMP_ERASE UINT32_C(0xff1e)
742 /* Send driver debug information to firmware */
743 #define HWRM_DBG_DRV_TRACE UINT32_C(0xff1f)
744 /* Query debug capabilities of firmware */
745 #define HWRM_DBG_QCAPS UINT32_C(0xff20)
746 /* Retrieve debug settings of firmware */
747 #define HWRM_DBG_QCFG UINT32_C(0xff21)
748 /* Set destination parameters for crashdump medium */
749 #define HWRM_DBG_CRASHDUMP_MEDIUM_CFG UINT32_C(0xff22)
750 #define HWRM_NVM_REQ_ARBITRATION UINT32_C(0xffed)
752 #define HWRM_NVM_FACTORY_DEFAULTS UINT32_C(0xffee)
753 #define HWRM_NVM_VALIDATE_OPTION UINT32_C(0xffef)
754 #define HWRM_NVM_FLUSH UINT32_C(0xfff0)
755 #define HWRM_NVM_GET_VARIABLE UINT32_C(0xfff1)
756 #define HWRM_NVM_SET_VARIABLE UINT32_C(0xfff2)
757 #define HWRM_NVM_INSTALL_UPDATE UINT32_C(0xfff3)
758 #define HWRM_NVM_MODIFY UINT32_C(0xfff4)
759 #define HWRM_NVM_VERIFY_UPDATE UINT32_C(0xfff5)
760 #define HWRM_NVM_GET_DEV_INFO UINT32_C(0xfff6)
761 #define HWRM_NVM_ERASE_DIR_ENTRY UINT32_C(0xfff7)
762 #define HWRM_NVM_MOD_DIR_ENTRY UINT32_C(0xfff8)
763 #define HWRM_NVM_FIND_DIR_ENTRY UINT32_C(0xfff9)
764 #define HWRM_NVM_GET_DIR_ENTRIES UINT32_C(0xfffa)
765 #define HWRM_NVM_GET_DIR_INFO UINT32_C(0xfffb)
766 #define HWRM_NVM_RAW_DUMP UINT32_C(0xfffc)
767 #define HWRM_NVM_READ UINT32_C(0xfffd)
768 #define HWRM_NVM_WRITE UINT32_C(0xfffe)
769 #define HWRM_NVM_RAW_WRITE_BLK UINT32_C(0xffff)
770 #define HWRM_LAST HWRM_NVM_RAW_WRITE_BLK
771 uint16_t unused_0[3];
775 /* ret_codes (size:64b/8B) */
778 /* Request was successfully executed by the HWRM. */
779 #define HWRM_ERR_CODE_SUCCESS UINT32_C(0x0)
780 /* The HWRM failed to execute the request. */
781 #define HWRM_ERR_CODE_FAIL UINT32_C(0x1)
783 * The request contains invalid argument(s) or input
786 #define HWRM_ERR_CODE_INVALID_PARAMS UINT32_C(0x2)
788 * The requester is not allowed to access the requested
789 * resource. This error code shall be provided in a
790 * response to a request to query or modify an existing
791 * resource that is not accessible by the requester.
793 #define HWRM_ERR_CODE_RESOURCE_ACCESS_DENIED UINT32_C(0x3)
795 * The HWRM is unable to allocate the requested resource.
796 * This code only applies to requests for HWRM resource
799 #define HWRM_ERR_CODE_RESOURCE_ALLOC_ERROR UINT32_C(0x4)
801 * Invalid combination of flags is specified in the
804 #define HWRM_ERR_CODE_INVALID_FLAGS UINT32_C(0x5)
806 * Invalid combination of enables fields is specified in
809 #define HWRM_ERR_CODE_INVALID_ENABLES UINT32_C(0x6)
811 * Request contains a required TLV that is not supported by
812 * the installed version of firmware.
814 #define HWRM_ERR_CODE_UNSUPPORTED_TLV UINT32_C(0x7)
816 * No firmware buffer available to accept the request. Driver
817 * should retry the request.
819 #define HWRM_ERR_CODE_NO_BUFFER UINT32_C(0x8)
821 * This error code is only reported by firmware when some
822 * sub-option of a supported HWRM command is unsupported.
824 #define HWRM_ERR_CODE_UNSUPPORTED_OPTION_ERR UINT32_C(0x9)
826 * This error code is only reported by firmware when the specific
827 * request is not able to process when the HOT reset in progress.
829 #define HWRM_ERR_CODE_HOT_RESET_PROGRESS UINT32_C(0xa)
831 * This error code is only reported by firmware when the registered
832 * driver instances are not capable of hot reset.
834 #define HWRM_ERR_CODE_HOT_RESET_FAIL UINT32_C(0xb)
836 * This error code is only reported by the firmware when during
837 * flow allocation when a request for a flow counter fails because
838 * the number of flow counters are exhausted.
840 #define HWRM_ERR_CODE_NO_FLOW_COUNTER_DURING_ALLOC UINT32_C(0xc)
842 * This error code is only reported by firmware when the registered
843 * driver instances requested to offloaded a flow but was unable to because
844 * the requested key's hash collides with the installed keys.
846 #define HWRM_ERR_CODE_KEY_HASH_COLLISION UINT32_C(0xd)
848 * This error code is only reported by firmware when the registered
849 * driver instances requested to offloaded a flow but was unable to because
850 * the same key has already been installed.
852 #define HWRM_ERR_CODE_KEY_ALREADY_EXISTS UINT32_C(0xe)
854 * Generic HWRM execution error that represents an
857 #define HWRM_ERR_CODE_HWRM_ERROR UINT32_C(0xf)
859 * Firmware is unable to service the request at the present time. Caller
860 * may try again later.
862 #define HWRM_ERR_CODE_BUSY UINT32_C(0x10)
864 * This value indicates that the HWRM response is in TLV format and
865 * should be interpreted as one or more TLVs starting with the
866 * hwrm_resp_hdr TLV. This value is not an indication of any error
867 * by itself, just an indication that the response should be parsed
868 * as TLV and the actual error code will be in the hwrm_resp_hdr TLV.
870 #define HWRM_ERR_CODE_TLV_ENCAPSULATED_RESPONSE UINT32_C(0x8000)
872 #define HWRM_ERR_CODE_UNKNOWN_ERR UINT32_C(0xfffe)
873 /* Unsupported or invalid command */
874 #define HWRM_ERR_CODE_CMD_NOT_SUPPORTED UINT32_C(0xffff)
875 #define HWRM_ERR_CODE_LAST \
876 HWRM_ERR_CODE_CMD_NOT_SUPPORTED
877 uint16_t unused_0[3];
881 /* hwrm_err_output (size:128b/16B) */
882 struct hwrm_err_output {
884 * Pass/Fail or error type
886 * Note: receiver to verify the in parameters, and fail the call
887 * with an error when appropriate
890 /* This field returns the type of original request. */
892 /* This field provides original sequence number of the command. */
895 * This field is the length of the response in bytes. The
896 * last byte of the response is a valid flag that will read
897 * as '1' when the command has been completely written to
901 /* debug info for this error response. */
903 /* debug info for this error response. */
906 * In the case of an error response, command specific error
907 * code is returned in this field.
911 * This field is used in Output records to indicate that the output
912 * is completely written to RAM. This field should be read as '1'
913 * to indicate that the output has been completely written.
914 * When writing a command completion or response to an internal processor,
915 * the order of writes has to be such that this field is written last.
920 * Following is the signature for HWRM message field that indicates not
921 * applicable (All F's). Need to cast it the size of the field if needed.
923 #define HWRM_NA_SIGNATURE ((uint32_t)(-1))
924 /* hwrm_func_buf_rgtr */
925 #define HWRM_MAX_REQ_LEN 128
926 /* hwrm_cfa_flow_info */
927 #define HWRM_MAX_RESP_LEN 704
928 /* 7 bit indirection table index. */
929 #define HW_HASH_INDEX_SIZE 0x80
930 #define HW_HASH_KEY_SIZE 40
931 /* valid key for HWRM response */
932 #define HWRM_RESP_VALID_KEY 1
933 /* Reserved for BONO processor */
934 #define HWRM_TARGET_ID_BONO 0xFFF8
935 /* Reserved for KONG processor */
936 #define HWRM_TARGET_ID_KONG 0xFFF9
937 /* Reserved for APE processor */
938 #define HWRM_TARGET_ID_APE 0xFFFA
940 * This value will be used by tools for User-space HWRM Interface.
941 * When tool execute any HWRM command with this target_id, firmware
942 * will copy the response and/or data payload via register space instead
945 #define HWRM_TARGET_ID_TOOLS 0xFFFD
946 #define HWRM_VERSION_MAJOR 1
947 #define HWRM_VERSION_MINOR 10
948 #define HWRM_VERSION_UPDATE 1
949 /* non-zero means beta version */
950 #define HWRM_VERSION_RSVD 56
951 #define HWRM_VERSION_STR "1.10.1.56"
958 /* hwrm_ver_get_input (size:192b/24B) */
959 struct hwrm_ver_get_input {
960 /* The HWRM command request type. */
963 * The completion ring to send the completion event on. This should
964 * be the NQ ID returned from the `nq_alloc` HWRM command.
968 * The sequence ID is used by the driver for tracking multiple
969 * commands. This ID is treated as opaque data by the firmware and
970 * the value is returned in the `hwrm_resp_hdr` upon completion.
974 * The target ID of the command:
975 * * 0x0-0xFFF8 - The function ID
976 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
977 * * 0xFFFD - Reserved for user-space HWRM interface
982 * A physical address pointer pointing to a host buffer that the
983 * command's response data will be written. This can be either a host
984 * physical address (HPA) or a guest physical address (GPA) and must
985 * point to a physically contiguous block of memory.
989 * This field represents the major version of HWRM interface
990 * specification supported by the driver HWRM implementation.
991 * The interface major version is intended to change only when
992 * non backward compatible changes are made to the HWRM
993 * interface specification.
995 uint8_t hwrm_intf_maj;
997 * This field represents the minor version of HWRM interface
998 * specification supported by the driver HWRM implementation.
999 * A change in interface minor version is used to reflect
1000 * significant backward compatible modification to HWRM
1001 * interface specification.
1002 * This can be due to addition or removal of functionality.
1003 * HWRM interface specifications with the same major version
1004 * but different minor versions are compatible.
1006 uint8_t hwrm_intf_min;
1008 * This field represents the update version of HWRM interface
1009 * specification supported by the driver HWRM implementation.
1010 * The interface update version is used to reflect minor
1011 * changes or bug fixes to a released HWRM interface
1014 uint8_t hwrm_intf_upd;
1015 uint8_t unused_0[5];
1018 /* hwrm_ver_get_output (size:1408b/176B) */
1019 struct hwrm_ver_get_output {
1020 /* The specific error status for the command. */
1021 uint16_t error_code;
1022 /* The HWRM command request type. */
1024 /* The sequence ID from the original command. */
1026 /* The length of the response data in number of bytes. */
1029 * This field represents the major version of HWRM interface
1030 * specification supported by the HWRM implementation.
1031 * The interface major version is intended to change only when
1032 * non backward compatible changes are made to the HWRM
1033 * interface specification.
1034 * A HWRM implementation that is compliant with this
1035 * specification shall provide value of 1 in this field.
1037 uint8_t hwrm_intf_maj_8b;
1039 * This field represents the minor version of HWRM interface
1040 * specification supported by the HWRM implementation.
1041 * A change in interface minor version is used to reflect
1042 * significant backward compatible modification to HWRM
1043 * interface specification.
1044 * This can be due to addition or removal of functionality.
1045 * HWRM interface specifications with the same major version
1046 * but different minor versions are compatible.
1047 * A HWRM implementation that is compliant with this
1048 * specification shall provide value of 2 in this field.
1050 uint8_t hwrm_intf_min_8b;
1052 * This field represents the update version of HWRM interface
1053 * specification supported by the HWRM implementation.
1054 * The interface update version is used to reflect minor
1055 * changes or bug fixes to a released HWRM interface
1057 * A HWRM implementation that is compliant with this
1058 * specification shall provide value of 2 in this field.
1060 uint8_t hwrm_intf_upd_8b;
1061 uint8_t hwrm_intf_rsvd_8b;
1063 * This field represents the major version of HWRM firmware.
1064 * A change in firmware major version represents a major
1067 uint8_t hwrm_fw_maj_8b;
1069 * This field represents the minor version of HWRM firmware.
1070 * A change in firmware minor version represents significant
1071 * firmware functionality changes.
1073 uint8_t hwrm_fw_min_8b;
1075 * This field represents the build version of HWRM firmware.
1076 * A change in firmware build version represents bug fixes
1077 * to a released firmware.
1079 uint8_t hwrm_fw_bld_8b;
1081 * This field is a reserved field. This field can be used to
1082 * represent firmware branches or customer specific releases
1083 * tied to a specific (major,minor,update) version of the
1086 uint8_t hwrm_fw_rsvd_8b;
1088 * This field represents the major version of mgmt firmware.
1089 * A change in major version represents a major release.
1091 uint8_t mgmt_fw_maj_8b;
1093 * This field represents the minor version of mgmt firmware.
1094 * A change in minor version represents significant
1095 * functionality changes.
1097 uint8_t mgmt_fw_min_8b;
1099 * This field represents the build version of mgmt firmware.
1100 * A change in update version represents bug fixes.
1102 uint8_t mgmt_fw_bld_8b;
1104 * This field is a reserved field. This field can be used to
1105 * represent firmware branches or customer specific releases
1106 * tied to a specific (major,minor,update) version
1108 uint8_t mgmt_fw_rsvd_8b;
1110 * This field represents the major version of network
1112 * A change in major version represents a major release.
1114 uint8_t netctrl_fw_maj_8b;
1116 * This field represents the minor version of network
1118 * A change in minor version represents significant
1119 * functionality changes.
1121 uint8_t netctrl_fw_min_8b;
1123 * This field represents the build version of network
1125 * A change in update version represents bug fixes.
1127 uint8_t netctrl_fw_bld_8b;
1129 * This field is a reserved field. This field can be used to
1130 * represent firmware branches or customer specific releases
1131 * tied to a specific (major,minor,update) version
1133 uint8_t netctrl_fw_rsvd_8b;
1135 * This field is used to indicate device's capabilities and
1138 uint32_t dev_caps_cfg;
1140 * If set to 1, then secure firmware update behavior
1142 * If set to 0, then secure firmware update behavior is
1145 #define HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_SECURE_FW_UPD_SUPPORTED \
1148 * If set to 1, then firmware based DCBX agent is supported.
1149 * If set to 0, then firmware based DCBX agent capability
1150 * is not supported on this device.
1152 #define HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_FW_DCBX_AGENT_SUPPORTED \
1155 * If set to 1, then HWRM short command format is supported.
1156 * If set to 0, then HWRM short command format is not supported.
1158 #define HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_SHORT_CMD_SUPPORTED \
1161 * If set to 1, then HWRM short command format is required.
1162 * If set to 0, then HWRM short command format is not required.
1164 #define HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_SHORT_CMD_REQUIRED \
1167 * If set to 1, then the KONG host mailbox channel is supported.
1168 * If set to 0, then the KONG host mailbox channel is not supported.
1169 * By default, this flag should be 0 for older version of core firmware.
1171 #define HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_KONG_MB_CHNL_SUPPORTED \
1174 * If set to 1, then the 64bit flow handle is supported in addition to the
1175 * legacy 16bit flow handle. If set to 0, then the 64bit flow handle is not
1176 * supported. By default, this flag should be 0 for older version of core firmware.
1178 #define HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_FLOW_HANDLE_64BIT_SUPPORTED \
1181 * If set to 1, then filter type can be provided in filter_alloc or filter_cfg
1182 * filter types like L2 for l2 traffic and ROCE for roce & l2 traffic.
1183 * If set to 0, then filter types not supported.
1184 * By default, this flag should be 0 for older version of core firmware.
1186 #define HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_L2_FILTER_TYPES_ROCE_OR_L2_SUPPORTED \
1189 * If set to 1, firmware is capable to support virtio vSwitch offload model.
1190 * If set to 0, firmware can't supported virtio vSwitch offload model.
1191 * By default, this flag should be 0 for older version of core firmware.
1193 #define HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_VIRTIO_VSWITCH_OFFLOAD_SUPPORTED \
1196 * If set to 1, firmware is capable to support trusted VF.
1197 * If set to 0, firmware is not capable to support trusted VF.
1198 * By default, this flag should be 0 for older version of core firmware.
1200 #define HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_TRUSTED_VF_SUPPORTED \
1203 * If set to 1, firmware is capable to support flow aging.
1204 * If set to 0, firmware is not capable to support flow aging.
1205 * By default, this flag should be 0 for older version of core firmware.
1207 #define HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_FLOW_AGING_SUPPORTED \
1210 * If set to 1, firmware is capable to support advanced flow counters like,
1211 * Meter drop counters and EEM counters.
1212 * If set to 0, firmware is not capable to support advanced flow counters.
1213 * By default, this flag should be 0 for older version of core firmware.
1215 #define HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_ADV_FLOW_COUNTERS_SUPPORTED \
1218 * If set to 1, the firmware is able to support the use of the CFA
1219 * Extended Exact Match(EEM) feature.
1220 * If set to 0, firmware is not capable to support the use of the
1222 * By default, this flag should be 0 for older version of core firmware.
1224 #define HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_CFA_EEM_SUPPORTED \
1227 * If set to 1, the firmware is able to support advance CFA flow management
1228 * features reported in the HWRM_CFA_FLOW_MGNT_QCAPS.
1229 * If set to 0, then the firmware doesn’t support the advance CFA flow management
1231 * By default, this flag should be 0 for older version of core firmware.
1233 #define HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_CFA_ADV_FLOW_MGNT_SUPPORTED \
1236 * Deprecated and replaced with cfa_truflow_supported.
1237 * If set to 1, the firmware is able to support TFLIB features.
1238 * If set to 0, then the firmware doesn’t support TFLIB features.
1239 * By default, this flag should be 0 for older version of core firmware.
1241 #define HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_CFA_TFLIB_SUPPORTED \
1244 * If set to 1, the firmware is able to support TruFlow features.
1245 * If set to 0, then the firmware doesn’t support TruFlow features.
1246 * By default, this flag should be 0 for older version of
1249 #define HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_CFA_TRUFLOW_SUPPORTED \
1252 * This field represents the major version of RoCE firmware.
1253 * A change in major version represents a major release.
1255 uint8_t roce_fw_maj_8b;
1257 * This field represents the minor version of RoCE firmware.
1258 * A change in minor version represents significant
1259 * functionality changes.
1261 uint8_t roce_fw_min_8b;
1263 * This field represents the build version of RoCE firmware.
1264 * A change in update version represents bug fixes.
1266 uint8_t roce_fw_bld_8b;
1268 * This field is a reserved field. This field can be used to
1269 * represent firmware branches or customer specific releases
1270 * tied to a specific (major,minor,update) version
1272 uint8_t roce_fw_rsvd_8b;
1274 * This field represents the name of HWRM FW (ASCII chars
1275 * with NULL at the end).
1277 char hwrm_fw_name[16];
1279 * This field represents the name of mgmt FW (ASCII chars
1280 * with NULL at the end).
1282 char mgmt_fw_name[16];
1284 * This field represents the name of network control
1285 * firmware (ASCII chars with NULL at the end).
1287 char netctrl_fw_name[16];
1288 /* This field represents the active board package name. */
1289 char active_pkg_name[16];
1291 * This field represents the name of RoCE FW (ASCII chars
1292 * with NULL at the end).
1294 char roce_fw_name[16];
1295 /* This field returns the chip number. */
1297 /* This field returns the revision of chip. */
1299 /* This field returns the chip metal number. */
1301 /* This field returns the bond id of the chip. */
1302 uint8_t chip_bond_id;
1303 /* This value indicates the type of platform used for chip implementation. */
1304 uint8_t chip_platform_type;
1306 #define HWRM_VER_GET_OUTPUT_CHIP_PLATFORM_TYPE_ASIC UINT32_C(0x0)
1307 /* FPGA platform of the chip. */
1308 #define HWRM_VER_GET_OUTPUT_CHIP_PLATFORM_TYPE_FPGA UINT32_C(0x1)
1309 /* Palladium platform of the chip. */
1310 #define HWRM_VER_GET_OUTPUT_CHIP_PLATFORM_TYPE_PALLADIUM UINT32_C(0x2)
1311 #define HWRM_VER_GET_OUTPUT_CHIP_PLATFORM_TYPE_LAST \
1312 HWRM_VER_GET_OUTPUT_CHIP_PLATFORM_TYPE_PALLADIUM
1314 * This field returns the maximum value of request window that
1315 * is supported by the HWRM. The request window is mapped
1316 * into device address space using MMIO.
1318 uint16_t max_req_win_len;
1320 * This field returns the maximum value of response buffer in
1323 uint16_t max_resp_len;
1325 * This field returns the default request timeout value in
1328 uint16_t def_req_timeout;
1330 * This field will indicate if any subsystems is not fully
1335 * If set to 1, it will indicate to host drivers that firmware is
1336 * not ready to start full blown HWRM commands. Host drivers should
1337 * re-try HWRM_VER_GET with some timeout period. The timeout period
1338 * can be selected up to 5 seconds.
1339 * For Example, PCIe hot-plug:
1340 * Hot plug timing is system dependent. It generally takes up to
1341 * 600 miliseconds for firmware to clear DEV_NOT_RDY flag.
1342 * If set to 0, device is ready to accept all HWRM commands.
1344 #define HWRM_VER_GET_OUTPUT_FLAGS_DEV_NOT_RDY UINT32_C(0x1)
1346 * If set to 1, external version present.
1347 * If set to 0, external version not present.
1349 #define HWRM_VER_GET_OUTPUT_FLAGS_EXT_VER_AVAIL UINT32_C(0x2)
1350 uint8_t unused_0[2];
1352 * For backward compatibility this field must be set to 1.
1353 * Older drivers might look for this field to be 1 before
1354 * processing the message.
1358 * This field represents the major version of HWRM interface
1359 * specification supported by the HWRM implementation.
1360 * The interface major version is intended to change only when
1361 * non backward compatible changes are made to the HWRM
1362 * interface specification. A HWRM implementation that is
1363 * compliant with this specification shall provide value of 1
1366 uint16_t hwrm_intf_major;
1368 * This field represents the minor version of HWRM interface
1369 * specification supported by the HWRM implementation.
1370 * A change in interface minor version is used to reflect
1371 * significant backward compatible modification to HWRM
1372 * interface specification. This can be due to addition or
1373 * removal of functionality. HWRM interface specifications
1374 * with the same major version but different minor versions are
1375 * compatible. A HWRM implementation that is compliant with
1376 * this specification shall provide value of 2 in this field.
1378 uint16_t hwrm_intf_minor;
1380 * This field represents the update version of HWRM interface
1381 * specification supported by the HWRM implementation. The
1382 * interface update version is used to reflect minor changes or
1383 * bug fixes to a released HWRM interface specification.
1384 * A HWRM implementation that is compliant with this
1385 * specification shall provide value of 2 in this field.
1387 uint16_t hwrm_intf_build;
1389 * This field represents the patch version of HWRM interface
1390 * specification supported by the HWRM implementation.
1392 uint16_t hwrm_intf_patch;
1394 * This field represents the major version of HWRM firmware.
1395 * A change in firmware major version represents a major
1398 uint16_t hwrm_fw_major;
1400 * This field represents the minor version of HWRM firmware.
1401 * A change in firmware minor version represents significant
1402 * firmware functionality changes.
1404 uint16_t hwrm_fw_minor;
1406 * This field represents the build version of HWRM firmware.
1407 * A change in firmware build version represents bug fixes to
1408 * a released firmware.
1410 uint16_t hwrm_fw_build;
1412 * This field is a reserved field.
1413 * This field can be used to represent firmware branches or customer
1414 * specific releases tied to a specific (major,minor,update) version
1415 * of the HWRM firmware.
1417 uint16_t hwrm_fw_patch;
1419 * This field represents the major version of mgmt firmware.
1420 * A change in major version represents a major release.
1422 uint16_t mgmt_fw_major;
1424 * This field represents the minor version of HWRM firmware.
1425 * A change in firmware minor version represents significant
1426 * firmware functionality changes.
1428 uint16_t mgmt_fw_minor;
1430 * This field represents the build version of mgmt firmware.
1431 * A change in update version represents bug fixes.
1433 uint16_t mgmt_fw_build;
1435 * This field is a reserved field. This field can be used to
1436 * represent firmware branches or customer specific releases
1437 * tied to a specific (major,minor,update) version.
1439 uint16_t mgmt_fw_patch;
1441 * This field represents the major version of network control
1442 * firmware. A change in major version represents
1445 uint16_t netctrl_fw_major;
1447 * This field represents the minor version of network control
1448 * firmware. A change in minor version represents significant
1449 * functionality changes.
1451 uint16_t netctrl_fw_minor;
1453 * This field represents the build version of network control
1454 * firmware. A change in update version represents bug fixes.
1456 uint16_t netctrl_fw_build;
1458 * This field is a reserved field. This field can be used to
1459 * represent firmware branches or customer specific releases
1460 * tied to a specific (major,minor,update) version
1462 uint16_t netctrl_fw_patch;
1464 * This field represents the major version of RoCE firmware.
1465 * A change in major version represents a major release.
1467 uint16_t roce_fw_major;
1469 * This field represents the minor version of RoCE firmware.
1470 * A change in minor version represents significant
1471 * functionality changes.
1473 uint16_t roce_fw_minor;
1475 * This field represents the build version of RoCE firmware.
1476 * A change in update version represents bug fixes.
1478 uint16_t roce_fw_build;
1480 * This field is a reserved field. This field can be used to
1481 * represent firmware branches or customer specific releases
1482 * tied to a specific (major,minor,update) version
1484 uint16_t roce_fw_patch;
1486 * This field returns the maximum extended request length acceptable
1487 * by the device which allows requests greater than mailbox size when
1488 * used with the short cmd request format.
1490 uint16_t max_ext_req_len;
1491 uint8_t unused_1[5];
1493 * This field is used in Output records to indicate that the output
1494 * is completely written to RAM. This field should be read as '1'
1495 * to indicate that the output has been completely written.
1496 * When writing a command completion or response to an internal processor,
1497 * the order of writes has to be such that this field is written last.
1502 /* bd_base (size:64b/8B) */
1505 /* This value identifies the type of buffer descriptor. */
1506 #define BD_BASE_TYPE_MASK UINT32_C(0x3f)
1507 #define BD_BASE_TYPE_SFT 0
1509 * Indicates that this BD is 16B long and is used for
1510 * normal L2 packet transmission.
1512 #define BD_BASE_TYPE_TX_BD_SHORT UINT32_C(0x0)
1514 * Indicates that this BD is 1BB long and is an empty
1515 * TX BD. Not valid for use by the driver.
1517 #define BD_BASE_TYPE_TX_BD_EMPTY UINT32_C(0x1)
1519 * Indicates that this BD is 16B long and is an RX Producer
1520 * (i.e. empty) buffer descriptor.
1522 #define BD_BASE_TYPE_RX_PROD_PKT UINT32_C(0x4)
1524 * Indicates that this BD is 16B long and is an RX
1525 * Producer Buffer BD.
1527 #define BD_BASE_TYPE_RX_PROD_BFR UINT32_C(0x5)
1529 * Indicates that this BD is 16B long and is an
1530 * RX Producer Assembly Buffer Descriptor.
1532 #define BD_BASE_TYPE_RX_PROD_AGG UINT32_C(0x6)
1534 * Indicates that this BD is 32B long and is used for
1535 * normal L2 packet transmission.
1537 #define BD_BASE_TYPE_TX_BD_LONG UINT32_C(0x10)
1539 * Indicates that this BD is 32B long and is used for
1540 * L2 packet transmission for small packets that require
1543 #define BD_BASE_TYPE_TX_BD_LONG_INLINE UINT32_C(0x11)
1544 #define BD_BASE_TYPE_LAST BD_BASE_TYPE_TX_BD_LONG_INLINE
1545 uint8_t unused_1[7];
1548 /* tx_bd_short (size:128b/16B) */
1549 struct tx_bd_short {
1551 * All bits in this field must be valid on the first BD of a packet.
1552 * Only the packet_end bit must be valid for the remaining BDs
1555 uint16_t flags_type;
1556 /* This value identifies the type of buffer descriptor. */
1557 #define TX_BD_SHORT_TYPE_MASK UINT32_C(0x3f)
1558 #define TX_BD_SHORT_TYPE_SFT 0
1560 * Indicates that this BD is 16B long and is used for
1561 * normal L2 packet transmission.
1563 #define TX_BD_SHORT_TYPE_TX_BD_SHORT UINT32_C(0x0)
1564 #define TX_BD_SHORT_TYPE_LAST TX_BD_SHORT_TYPE_TX_BD_SHORT
1566 * All bits in this field must be valid on the first BD of a packet.
1567 * Only the packet_end bit must be valid for the remaining BDs
1570 #define TX_BD_SHORT_FLAGS_MASK UINT32_C(0xffc0)
1571 #define TX_BD_SHORT_FLAGS_SFT 6
1573 * If set to 1, the packet ends with the data in the buffer
1574 * pointed to by this descriptor. This flag must be
1575 * valid on every BD.
1577 #define TX_BD_SHORT_FLAGS_PACKET_END UINT32_C(0x40)
1579 * If set to 1, the device will not generate a completion for
1580 * this transmit packet unless there is an error in it's
1583 * is set to 0, then the packet will be completed normally.
1585 * This bit must be valid only on the first BD of a packet.
1587 #define TX_BD_SHORT_FLAGS_NO_CMPL UINT32_C(0x80)
1589 * This value indicates how many 16B BD locations are consumed
1590 * in the ring by this packet.
1591 * A value of 1 indicates that this BD is the only BD (and that
1592 * it is a short BD). A value
1593 * of 3 indicates either 3 short BDs or 1 long BD and one short
1594 * BD in the packet. A value of 0 indicates
1595 * that there are 32 BD locations in the packet (the maximum).
1597 * This field is valid only on the first BD of a packet.
1599 #define TX_BD_SHORT_FLAGS_BD_CNT_MASK UINT32_C(0x1f00)
1600 #define TX_BD_SHORT_FLAGS_BD_CNT_SFT 8
1602 * This value is a hint for the length of the entire packet.
1603 * It is used by the chip to optimize internal processing.
1605 * The packet will be dropped if the hint is too short.
1607 * This field is valid only on the first BD of a packet.
1609 #define TX_BD_SHORT_FLAGS_LHINT_MASK UINT32_C(0x6000)
1610 #define TX_BD_SHORT_FLAGS_LHINT_SFT 13
1611 /* indicates packet length < 512B */
1612 #define TX_BD_SHORT_FLAGS_LHINT_LT512 (UINT32_C(0x0) << 13)
1613 /* indicates 512 <= packet length < 1KB */
1614 #define TX_BD_SHORT_FLAGS_LHINT_LT1K (UINT32_C(0x1) << 13)
1615 /* indicates 1KB <= packet length < 2KB */
1616 #define TX_BD_SHORT_FLAGS_LHINT_LT2K (UINT32_C(0x2) << 13)
1617 /* indicates packet length >= 2KB */
1618 #define TX_BD_SHORT_FLAGS_LHINT_GTE2K (UINT32_C(0x3) << 13)
1619 #define TX_BD_SHORT_FLAGS_LHINT_LAST \
1620 TX_BD_SHORT_FLAGS_LHINT_GTE2K
1622 * If set to 1, the device immediately updates the Send Consumer
1623 * Index after the buffer associated with this descriptor has
1624 * been transferred via DMA to NIC memory from host memory. An
1625 * interrupt may or may not be generated according to the state
1626 * of the interrupt avoidance mechanisms. If this bit
1627 * is set to 0, then the Consumer Index is only updated as soon
1628 * as one of the host interrupt coalescing conditions has been met.
1630 * This bit must be valid on the first BD of a packet.
1632 #define TX_BD_SHORT_FLAGS_COAL_NOW UINT32_C(0x8000)
1634 * This is the length of the host physical buffer this BD describes
1637 * This field must be valid on all BDs of a packet.
1641 * The opaque data field is pass through to the completion and can be
1642 * used for any data that the driver wants to associate with the
1645 * This field must be valid on the first BD of a packet.
1649 * This is the host physical address for the portion of the packet
1650 * described by this TX BD.
1652 * This value must be valid on all BDs of a packet.
1657 /* tx_bd_long (size:128b/16B) */
1659 /* This value identifies the type of buffer descriptor. */
1660 uint16_t flags_type;
1662 * This value indicates the type of buffer descriptor.
1665 #define TX_BD_LONG_TYPE_MASK UINT32_C(0x3f)
1666 #define TX_BD_LONG_TYPE_SFT 0
1668 * Indicates that this BD is 32B long and is used for
1669 * normal L2 packet transmission.
1671 #define TX_BD_LONG_TYPE_TX_BD_LONG UINT32_C(0x10)
1672 #define TX_BD_LONG_TYPE_LAST TX_BD_LONG_TYPE_TX_BD_LONG
1674 * All bits in this field must be valid on the first BD of a packet.
1675 * Only the packet_end bit must be valid for the remaining BDs
1678 #define TX_BD_LONG_FLAGS_MASK UINT32_C(0xffc0)
1679 #define TX_BD_LONG_FLAGS_SFT 6
1681 * If set to 1, the packet ends with the data in the buffer
1682 * pointed to by this descriptor. This flag must be
1683 * valid on every BD.
1685 #define TX_BD_LONG_FLAGS_PACKET_END UINT32_C(0x40)
1687 * If set to 1, the device will not generate a completion for
1688 * this transmit packet unless there is an error in it's
1691 * is set to 0, then the packet will be completed normally.
1693 * This bit must be valid only on the first BD of a packet.
1695 #define TX_BD_LONG_FLAGS_NO_CMPL UINT32_C(0x80)
1697 * This value indicates how many 16B BD locations are consumed
1698 * in the ring by this packet.
1699 * A value of 1 indicates that this BD is the only BD (and that
1700 * it is a short BD). A value
1701 * of 3 indicates either 3 short BDs or 1 long BD and one short
1702 * BD in the packet. A value of 0 indicates
1703 * that there are 32 BD locations in the packet (the maximum).
1705 * This field is valid only on the first BD of a packet.
1707 #define TX_BD_LONG_FLAGS_BD_CNT_MASK UINT32_C(0x1f00)
1708 #define TX_BD_LONG_FLAGS_BD_CNT_SFT 8
1710 * This value is a hint for the length of the entire packet.
1711 * It is used by the chip to optimize internal processing.
1713 * The packet will be dropped if the hint is too short.
1715 * This field is valid only on the first BD of a packet.
1717 #define TX_BD_LONG_FLAGS_LHINT_MASK UINT32_C(0x6000)
1718 #define TX_BD_LONG_FLAGS_LHINT_SFT 13
1719 /* indicates packet length < 512B */
1720 #define TX_BD_LONG_FLAGS_LHINT_LT512 (UINT32_C(0x0) << 13)
1721 /* indicates 512 <= packet length < 1KB */
1722 #define TX_BD_LONG_FLAGS_LHINT_LT1K (UINT32_C(0x1) << 13)
1723 /* indicates 1KB <= packet length < 2KB */
1724 #define TX_BD_LONG_FLAGS_LHINT_LT2K (UINT32_C(0x2) << 13)
1725 /* indicates packet length >= 2KB */
1726 #define TX_BD_LONG_FLAGS_LHINT_GTE2K (UINT32_C(0x3) << 13)
1727 #define TX_BD_LONG_FLAGS_LHINT_LAST TX_BD_LONG_FLAGS_LHINT_GTE2K
1729 * If set to 1, the device immediately updates the Send Consumer
1730 * Index after the buffer associated with this descriptor has
1731 * been transferred via DMA to NIC memory from host memory. An
1732 * interrupt may or may not be generated according to the state
1733 * of the interrupt avoidance mechanisms. If this bit
1734 * is set to 0, then the Consumer Index is only updated as soon
1735 * as one of the host interrupt coalescing conditions has been met.
1737 * This bit must be valid on the first BD of a packet.
1739 #define TX_BD_LONG_FLAGS_COAL_NOW UINT32_C(0x8000)
1741 * This is the length of the host physical buffer this BD describes
1744 * This field must be valid on all BDs of a packet.
1748 * The opaque data field is pass through to the completion and can be
1749 * used for any data that the driver wants to associate with the
1752 * This field must be valid on the first BD of a packet.
1756 * This is the host physical address for the portion of the packet
1757 * described by this TX BD.
1759 * This value must be valid on all BDs of a packet.
1764 /* Last 16 bytes of tx_bd_long. */
1765 /* tx_bd_long_hi (size:128b/16B) */
1766 struct tx_bd_long_hi {
1768 * All bits in this field must be valid on the first BD of a packet.
1769 * Their value on other BDs of the packet will be ignored.
1773 * If set to 1, the controller replaces the TCP/UPD checksum
1774 * fields of normal TCP/UPD checksum, or the inner TCP/UDP
1775 * checksum field of the encapsulated TCP/UDP packets with the
1776 * hardware calculated TCP/UDP checksum for the packet associated
1777 * with this descriptor. The flag is ignored if the LSO flag is set.
1779 * This bit must be valid on the first BD of a packet.
1781 #define TX_BD_LONG_LFLAGS_TCP_UDP_CHKSUM UINT32_C(0x1)
1783 * If set to 1, the controller replaces the IP checksum of the
1784 * normal packets, or the inner IP checksum of the encapsulated
1785 * packets with the hardware calculated IP checksum for the
1786 * packet associated with this descriptor.
1788 * This bit must be valid on the first BD of a packet.
1790 #define TX_BD_LONG_LFLAGS_IP_CHKSUM UINT32_C(0x2)
1792 * If set to 1, the controller will not append an Ethernet CRC
1793 * to the end of the frame.
1795 * This bit must be valid on the first BD of a packet.
1797 * Packet must be 64B or longer when this flag is set. It is not
1798 * useful to use this bit with any form of TX offload such as
1799 * CSO or LSO. The intent is that the packet from the host already
1800 * has a valid Ethernet CRC on the packet.
1802 #define TX_BD_LONG_LFLAGS_NOCRC UINT32_C(0x4)
1804 * If set to 1, the device will record the time at which the packet
1805 * was actually transmitted at the TX MAC.
1807 * This bit must be valid on the first BD of a packet.
1809 #define TX_BD_LONG_LFLAGS_STAMP UINT32_C(0x8)
1811 * If set to 1, The controller replaces the tunnel IP checksum
1812 * field with hardware calculated IP checksum for the IP header
1813 * of the packet associated with this descriptor.
1815 * For outer UDP checksum, global outer UDP checksum TE_NIC register
1816 * needs to be enabled. If the global outer UDP checksum TE_NIC register
1817 * bit is set, outer UDP checksum will be calculated for the following
1819 * 1. Packets with tcp_udp_chksum flag set to offload checksum for inner
1820 * packet AND the inner packet is TCP/UDP. If the inner packet is ICMP for
1821 * example (non-TCP/UDP), even if the tcp_udp_chksum is set, the outer UDP
1822 * checksum will not be calculated.
1823 * 2. Packets with lso flag set which implies inner TCP checksum calculation
1824 * as part of LSO operation.
1826 #define TX_BD_LONG_LFLAGS_T_IP_CHKSUM UINT32_C(0x10)
1828 * If set to 1, the device will treat this packet with LSO(Large
1829 * Send Offload) processing for both normal or encapsulated
1830 * packets, which is a form of TCP segmentation. When this bit
1831 * is 1, the hdr_size and mss fields must be valid. The driver
1832 * doesn't need to set t_ip_chksum, ip_chksum, and tcp_udp_chksum
1833 * flags since the controller will replace the appropriate
1834 * checksum fields for segmented packets.
1836 * When this bit is 1, the hdr_size and mss fields must be valid.
1838 #define TX_BD_LONG_LFLAGS_LSO UINT32_C(0x20)
1840 * If set to zero when LSO is '1', then the IPID will be treated
1841 * as a 16b number and will be wrapped if it exceeds a value of
1844 * If set to one when LSO is '1', then the IPID will be treated
1845 * as a 15b number and will be wrapped if it exceeds a value 0f
1848 #define TX_BD_LONG_LFLAGS_IPID_FMT UINT32_C(0x40)
1850 * If set to zero when LSO is '1', then the IPID of the tunnel
1851 * IP header will not be modified during LSO operations.
1853 * If set to one when LSO is '1', then the IPID of the tunnel
1854 * IP header will be incremented for each subsequent segment of an
1857 * The flag is ignored if the LSO packet is a normal (non-tunneled)
1860 #define TX_BD_LONG_LFLAGS_T_IPID UINT32_C(0x80)
1862 * If set to '1', then the RoCE ICRC will be appended to the
1863 * packet. Packet must be a valid RoCE format packet.
1865 #define TX_BD_LONG_LFLAGS_ROCE_CRC UINT32_C(0x100)
1867 * If set to '1', then the FCoE CRC will be appended to the
1868 * packet. Packet must be a valid FCoE format packet.
1870 #define TX_BD_LONG_LFLAGS_FCOE_CRC UINT32_C(0x200)
1873 * When LSO is '1', this field must contain the offset of the
1874 * TCP payload from the beginning of the packet in as
1875 * 16b words. In case of encapsulated/tunneling packet, this field
1876 * contains the offset of the inner TCP payload from beginning of the
1877 * packet as 16-bit words.
1879 * This value must be valid on the first BD of a packet.
1881 #define TX_BD_LONG_HDR_SIZE_MASK UINT32_C(0x1ff)
1882 #define TX_BD_LONG_HDR_SIZE_SFT 0
1885 * This is the MSS value that will be used to do the LSO processing.
1886 * The value is the length in bytes of the TCP payload for each
1887 * segment generated by the LSO operation.
1889 * This value must be valid on the first BD of a packet.
1891 #define TX_BD_LONG_MSS_MASK UINT32_C(0x7fff)
1892 #define TX_BD_LONG_MSS_SFT 0
1895 * This value selects a CFA action to perform on the packet.
1896 * Set this value to zero if no CFA action is desired.
1898 * This value must be valid on the first BD of a packet.
1900 uint16_t cfa_action;
1902 * This value is action meta-data that defines CFA edit operations
1903 * that are done in addition to any action editing.
1906 /* When key=1, This is the VLAN tag VID value. */
1907 #define TX_BD_LONG_CFA_META_VLAN_VID_MASK UINT32_C(0xfff)
1908 #define TX_BD_LONG_CFA_META_VLAN_VID_SFT 0
1909 /* When key=1, This is the VLAN tag DE value. */
1910 #define TX_BD_LONG_CFA_META_VLAN_DE UINT32_C(0x1000)
1911 /* When key=1, This is the VLAN tag PRI value. */
1912 #define TX_BD_LONG_CFA_META_VLAN_PRI_MASK UINT32_C(0xe000)
1913 #define TX_BD_LONG_CFA_META_VLAN_PRI_SFT 13
1914 /* When key=1, This is the VLAN tag TPID select value. */
1915 #define TX_BD_LONG_CFA_META_VLAN_TPID_MASK UINT32_C(0x70000)
1916 #define TX_BD_LONG_CFA_META_VLAN_TPID_SFT 16
1918 #define TX_BD_LONG_CFA_META_VLAN_TPID_TPID88A8 (UINT32_C(0x0) << 16)
1920 #define TX_BD_LONG_CFA_META_VLAN_TPID_TPID8100 (UINT32_C(0x1) << 16)
1922 #define TX_BD_LONG_CFA_META_VLAN_TPID_TPID9100 (UINT32_C(0x2) << 16)
1924 #define TX_BD_LONG_CFA_META_VLAN_TPID_TPID9200 (UINT32_C(0x3) << 16)
1926 #define TX_BD_LONG_CFA_META_VLAN_TPID_TPID9300 (UINT32_C(0x4) << 16)
1927 /* Value programmed in CFA VLANTPID register. */
1928 #define TX_BD_LONG_CFA_META_VLAN_TPID_TPIDCFG (UINT32_C(0x5) << 16)
1929 #define TX_BD_LONG_CFA_META_VLAN_TPID_LAST \
1930 TX_BD_LONG_CFA_META_VLAN_TPID_TPIDCFG
1931 /* When key=1, This is the VLAN tag TPID select value. */
1932 #define TX_BD_LONG_CFA_META_VLAN_RESERVED_MASK UINT32_C(0xff80000)
1933 #define TX_BD_LONG_CFA_META_VLAN_RESERVED_SFT 19
1935 * This field identifies the type of edit to be performed
1938 * This value must be valid on the first BD of a packet.
1940 #define TX_BD_LONG_CFA_META_KEY_MASK UINT32_C(0xf0000000)
1941 #define TX_BD_LONG_CFA_META_KEY_SFT 28
1943 #define TX_BD_LONG_CFA_META_KEY_NONE (UINT32_C(0x0) << 28)
1945 * - meta[17:16] - TPID select value (0 = 0x8100).
1946 * - meta[15:12] - PRI/DE value.
1947 * - meta[11:0] - VID value.
1949 #define TX_BD_LONG_CFA_META_KEY_VLAN_TAG (UINT32_C(0x1) << 28)
1950 #define TX_BD_LONG_CFA_META_KEY_LAST \
1951 TX_BD_LONG_CFA_META_KEY_VLAN_TAG
1955 * This structure is used to inform the NIC of packet data that needs to be
1956 * transmitted with additional processing that requires extra data such as
1957 * VLAN insertion plus attached inline data. This BD type may be used to
1958 * improve latency for small packets needing the additional extended features
1959 * supported by long BDs.
1961 /* tx_bd_long_inline (size:256b/32B) */
1962 struct tx_bd_long_inline {
1963 uint16_t flags_type;
1964 /* This value identifies the type of buffer descriptor. */
1965 #define TX_BD_LONG_INLINE_TYPE_MASK UINT32_C(0x3f)
1966 #define TX_BD_LONG_INLINE_TYPE_SFT 0
1968 * This type of BD is 32B long and is used for inline L2 packet
1971 #define TX_BD_LONG_INLINE_TYPE_TX_BD_LONG_INLINE UINT32_C(0x11)
1972 #define TX_BD_LONG_INLINE_TYPE_LAST \
1973 TX_BD_LONG_INLINE_TYPE_TX_BD_LONG_INLINE
1975 * All bits in this field may be set on the first BD of a packet.
1976 * Only the packet_end bit may be set in non-first BDs.
1978 #define TX_BD_LONG_INLINE_FLAGS_MASK UINT32_C(0xffc0)
1979 #define TX_BD_LONG_INLINE_FLAGS_SFT 6
1981 * If set to 1, the packet ends with the data in the buffer
1982 * pointed to by this descriptor. This flag must be
1983 * valid on every BD.
1985 #define TX_BD_LONG_INLINE_FLAGS_PACKET_END UINT32_C(0x40)
1987 * If set to 1, the device will not generate a completion for
1988 * this transmit packet unless there is an error in its processing.
1989 * If this bit is set to 0, then the packet will be completed
1992 * This bit may be set only on the first BD of a packet.
1994 #define TX_BD_LONG_INLINE_FLAGS_NO_CMPL UINT32_C(0x80)
1996 * This value indicates how many 16B BD locations are consumed
1997 * in the ring by this packet, including the BD and inline
2000 #define TX_BD_LONG_INLINE_FLAGS_BD_CNT_MASK UINT32_C(0x1f00)
2001 #define TX_BD_LONG_INLINE_FLAGS_BD_CNT_SFT 8
2002 /* This field is deprecated. */
2003 #define TX_BD_LONG_INLINE_FLAGS_LHINT_MASK UINT32_C(0x6000)
2004 #define TX_BD_LONG_INLINE_FLAGS_LHINT_SFT 13
2006 * If set to 1, the device immediately updates the Send Consumer
2007 * Index after the buffer associated with this descriptor has
2008 * been transferred via DMA to NIC memory from host memory. An
2009 * interrupt may or may not be generated according to the state
2010 * of the interrupt avoidance mechanisms. If this bit
2011 * is set to 0, then the Consumer Index is only updated as soon
2012 * as one of the host interrupt coalescing conditions has been met.
2014 * This bit must be valid on the first BD of a packet.
2016 #define TX_BD_LONG_INLINE_FLAGS_COAL_NOW UINT32_C(0x8000)
2018 * This is the length of the inline data, not including BD length, in
2020 * The maximum value is 480.
2022 * This field must be valid on all BDs of a packet.
2026 * The opaque data field is passed through to the completion and can be
2027 * used for any data that the driver wants to associate with the transmit
2030 * This field must be valid on the first BD of a packet.
2035 * All bits in this field must be valid on the first BD of a packet.
2036 * Their value on other BDs of the packet is ignored.
2040 * If set to 1, the controller replaces the TCP/UPD checksum
2041 * fields of normal TCP/UPD checksum, or the inner TCP/UDP
2042 * checksum field of the encapsulated TCP/UDP packets with the
2043 * hardware calculated TCP/UDP checksum for the packet associated
2044 * with this descriptor. The flag is ignored if the LSO flag is set.
2046 #define TX_BD_LONG_INLINE_LFLAGS_TCP_UDP_CHKSUM UINT32_C(0x1)
2048 * If set to 1, the controller replaces the IP checksum of the
2049 * normal packets, or the inner IP checksum of the encapsulated
2050 * packets with the hardware calculated IP checksum for the
2051 * packet associated with this descriptor.
2053 #define TX_BD_LONG_INLINE_LFLAGS_IP_CHKSUM UINT32_C(0x2)
2055 * If set to 1, the controller will not append an Ethernet CRC
2056 * to the end of the frame.
2058 * Packet must be 64B or longer when this flag is set. It is not
2059 * useful to use this bit with any form of TX offload such as
2060 * CSO or LSO. The intent is that the packet from the host already
2061 * has a valid Ethernet CRC on the packet.
2063 #define TX_BD_LONG_INLINE_LFLAGS_NOCRC UINT32_C(0x4)
2065 * If set to 1, the device will record the time at which the packet
2066 * was actually transmitted at the TX MAC.
2068 #define TX_BD_LONG_INLINE_LFLAGS_STAMP UINT32_C(0x8)
2070 * If set to 1, the controller replaces the tunnel IP checksum
2071 * field with hardware calculated IP checksum for the IP header
2072 * of the packet associated with this descriptor. The hardware
2073 * updates an outer UDP checksum if it is non-zero.
2075 #define TX_BD_LONG_INLINE_LFLAGS_T_IP_CHKSUM UINT32_C(0x10)
2077 * This bit must be 0 for BDs of this type. LSO is not supported with
2080 #define TX_BD_LONG_INLINE_LFLAGS_LSO UINT32_C(0x20)
2081 /* Since LSO is not supported with inline BDs, this bit is not used. */
2082 #define TX_BD_LONG_INLINE_LFLAGS_IPID_FMT UINT32_C(0x40)
2083 /* Since LSO is not supported with inline BDs, this bit is not used. */
2084 #define TX_BD_LONG_INLINE_LFLAGS_T_IPID UINT32_C(0x80)
2086 * If set to '1', then the RoCE ICRC will be appended to the
2087 * packet. Packet must be a valid RoCE format packet.
2089 #define TX_BD_LONG_INLINE_LFLAGS_ROCE_CRC UINT32_C(0x100)
2091 * If set to '1', then the FCoE CRC will be appended to the
2092 * packet. Packet must be a valid FCoE format packet.
2094 #define TX_BD_LONG_INLINE_LFLAGS_FCOE_CRC UINT32_C(0x200)
2099 * This value selects a CFA action to perform on the packet.
2100 * Set this value to zero if no CFA action is desired.
2102 * This value must be valid on the first BD of a packet.
2104 uint16_t cfa_action;
2106 * This value is action meta-data that defines CFA edit operations
2107 * that are done in addition to any action editing.
2110 /* When key = 1, this is the VLAN tag VID value. */
2111 #define TX_BD_LONG_INLINE_CFA_META_VLAN_VID_MASK UINT32_C(0xfff)
2112 #define TX_BD_LONG_INLINE_CFA_META_VLAN_VID_SFT 0
2113 /* When key = 1, this is the VLAN tag DE value. */
2114 #define TX_BD_LONG_INLINE_CFA_META_VLAN_DE UINT32_C(0x1000)
2115 /* When key = 1, this is the VLAN tag PRI value. */
2116 #define TX_BD_LONG_INLINE_CFA_META_VLAN_PRI_MASK UINT32_C(0xe000)
2117 #define TX_BD_LONG_INLINE_CFA_META_VLAN_PRI_SFT 13
2118 /* When key = 1, this is the VLAN tag TPID select value. */
2119 #define TX_BD_LONG_INLINE_CFA_META_VLAN_TPID_MASK UINT32_C(0x70000)
2120 #define TX_BD_LONG_INLINE_CFA_META_VLAN_TPID_SFT 16
2122 #define TX_BD_LONG_INLINE_CFA_META_VLAN_TPID_TPID88A8 \
2123 (UINT32_C(0x0) << 16)
2125 #define TX_BD_LONG_INLINE_CFA_META_VLAN_TPID_TPID8100 \
2126 (UINT32_C(0x1) << 16)
2128 #define TX_BD_LONG_INLINE_CFA_META_VLAN_TPID_TPID9100 \
2129 (UINT32_C(0x2) << 16)
2131 #define TX_BD_LONG_INLINE_CFA_META_VLAN_TPID_TPID9200 \
2132 (UINT32_C(0x3) << 16)
2134 #define TX_BD_LONG_INLINE_CFA_META_VLAN_TPID_TPID9300 \
2135 (UINT32_C(0x4) << 16)
2136 /* Value programmed in CFA VLANTPID register. */
2137 #define TX_BD_LONG_INLINE_CFA_META_VLAN_TPID_TPIDCFG \
2138 (UINT32_C(0x5) << 16)
2139 #define TX_BD_LONG_INLINE_CFA_META_VLAN_TPID_LAST \
2140 TX_BD_LONG_INLINE_CFA_META_VLAN_TPID_TPIDCFG
2141 #define TX_BD_LONG_INLINE_CFA_META_VLAN_RESERVED_MASK \
2143 #define TX_BD_LONG_INLINE_CFA_META_VLAN_RESERVED_SFT 19
2145 * This field identifies the type of edit to be performed
2148 * This value must be valid on the first BD of a packet.
2150 #define TX_BD_LONG_INLINE_CFA_META_KEY_MASK \
2151 UINT32_C(0xf0000000)
2152 #define TX_BD_LONG_INLINE_CFA_META_KEY_SFT 28
2154 #define TX_BD_LONG_INLINE_CFA_META_KEY_NONE \
2155 (UINT32_C(0x0) << 28)
2157 * - meta[17:16] - TPID select value (0 = 0x8100).
2158 * - meta[15:12] - PRI/DE value.
2159 * - meta[11:0] - VID value.
2161 #define TX_BD_LONG_INLINE_CFA_META_KEY_VLAN_TAG \
2162 (UINT32_C(0x1) << 28)
2163 #define TX_BD_LONG_INLINE_CFA_META_KEY_LAST \
2164 TX_BD_LONG_INLINE_CFA_META_KEY_VLAN_TAG
2167 /* tx_bd_empty (size:128b/16B) */
2168 struct tx_bd_empty {
2169 /* This value identifies the type of buffer descriptor. */
2171 #define TX_BD_EMPTY_TYPE_MASK UINT32_C(0x3f)
2172 #define TX_BD_EMPTY_TYPE_SFT 0
2174 * Indicates that this BD is 1BB long and is an empty
2175 * TX BD. Not valid for use by the driver.
2177 #define TX_BD_EMPTY_TYPE_TX_BD_EMPTY UINT32_C(0x1)
2178 #define TX_BD_EMPTY_TYPE_LAST TX_BD_EMPTY_TYPE_TX_BD_EMPTY
2179 uint8_t unused_1[3];
2181 uint8_t unused_3[3];
2182 uint8_t unused_4[8];
2185 /* rx_prod_pkt_bd (size:128b/16B) */
2186 struct rx_prod_pkt_bd {
2187 /* This value identifies the type of buffer descriptor. */
2188 uint16_t flags_type;
2189 /* This value identifies the type of buffer descriptor. */
2190 #define RX_PROD_PKT_BD_TYPE_MASK UINT32_C(0x3f)
2191 #define RX_PROD_PKT_BD_TYPE_SFT 0
2193 * Indicates that this BD is 16B long and is an RX Producer
2194 * (i.e. empty) buffer descriptor.
2196 #define RX_PROD_PKT_BD_TYPE_RX_PROD_PKT UINT32_C(0x4)
2197 #define RX_PROD_PKT_BD_TYPE_LAST \
2198 RX_PROD_PKT_BD_TYPE_RX_PROD_PKT
2199 #define RX_PROD_PKT_BD_FLAGS_MASK UINT32_C(0xffc0)
2200 #define RX_PROD_PKT_BD_FLAGS_SFT 6
2202 * If set to 1, the packet will be placed at the address plus
2203 * 2B. The 2 Bytes of padding will be written as zero.
2205 #define RX_PROD_PKT_BD_FLAGS_SOP_PAD UINT32_C(0x40)
2207 * If set to 1, the packet write will be padded out to the
2208 * nearest cache-line with zero value padding.
2210 #define RX_PROD_PKT_BD_FLAGS_EOP_PAD UINT32_C(0x80)
2212 * This field has been deprecated. There can be no additional
2213 * BDs for this packet from this ring.
2216 * This value is the number of additional buffers in the ring that
2217 * describe the buffer space to be consumed for this packet.
2218 * If the value is zero, then the packet must fit within the
2219 * space described by this BD. If this value is 1 or more, it
2220 * indicates how many additional "buffer" BDs are in the ring
2221 * immediately following this BD to be used for the same
2222 * network packet. Even if the packet to be placed does not need
2223 * all the additional buffers, they will be consumed anyway.
2225 #define RX_PROD_PKT_BD_FLAGS_BUFFERS_MASK UINT32_C(0x300)
2226 #define RX_PROD_PKT_BD_FLAGS_BUFFERS_SFT 8
2228 * This is the length in Bytes of the host physical buffer where
2229 * data for the packet may be placed in host memory.
2233 * The opaque data field is pass through to the completion and can be
2234 * used for any data that the driver wants to associate with this
2235 * receive buffer set.
2239 * This is the host physical address where data for the packet may
2240 * be placed in host memory.
2245 /* rx_prod_bfr_bd (size:128b/16B) */
2246 struct rx_prod_bfr_bd {
2247 /* This value identifies the type of buffer descriptor. */
2248 uint16_t flags_type;
2249 /* This value identifies the type of buffer descriptor. */
2250 #define RX_PROD_BFR_BD_TYPE_MASK UINT32_C(0x3f)
2251 #define RX_PROD_BFR_BD_TYPE_SFT 0
2253 * Indicates that this BD is 16B long and is an RX
2254 * Producer Buffer BD.
2256 #define RX_PROD_BFR_BD_TYPE_RX_PROD_BFR UINT32_C(0x5)
2257 #define RX_PROD_BFR_BD_TYPE_LAST RX_PROD_BFR_BD_TYPE_RX_PROD_BFR
2258 #define RX_PROD_BFR_BD_FLAGS_MASK UINT32_C(0xffc0)
2259 #define RX_PROD_BFR_BD_FLAGS_SFT 6
2261 * This is the length in Bytes of the host physical buffer where
2262 * data for the packet may be placed in host memory.
2265 /* This field is not used. */
2268 * This is the host physical address where data for the packet may
2269 * be placed in host memory.
2274 /* rx_prod_agg_bd (size:128b/16B) */
2275 struct rx_prod_agg_bd {
2276 /* This value identifies the type of buffer descriptor. */
2277 uint16_t flags_type;
2278 /* This value identifies the type of buffer descriptor. */
2279 #define RX_PROD_AGG_BD_TYPE_MASK UINT32_C(0x3f)
2280 #define RX_PROD_AGG_BD_TYPE_SFT 0
2282 * Indicates that this BD is 16B long and is an
2283 * RX Producer Assembly Buffer Descriptor.
2285 #define RX_PROD_AGG_BD_TYPE_RX_PROD_AGG UINT32_C(0x6)
2286 #define RX_PROD_AGG_BD_TYPE_LAST \
2287 RX_PROD_AGG_BD_TYPE_RX_PROD_AGG
2288 #define RX_PROD_AGG_BD_FLAGS_MASK UINT32_C(0xffc0)
2289 #define RX_PROD_AGG_BD_FLAGS_SFT 6
2291 * If set to 1, the packet write will be padded out to the
2292 * nearest cache-line with zero value padding.
2294 #define RX_PROD_AGG_BD_FLAGS_EOP_PAD UINT32_C(0x40)
2296 * This is the length in Bytes of the host physical buffer where
2297 * data for the packet may be placed in host memory.
2301 * The opaque data field is pass through to the completion and can be
2302 * used for any data that the driver wants to associate with this
2303 * receive assembly buffer.
2307 * This is the host physical address where data for the packet may
2308 * be placed in host memory.
2313 /* cmpl_base (size:128b/16B) */
2317 * This field indicates the exact type of the completion.
2318 * By convention, the LSB identifies the length of the
2319 * record in 16B units. Even values indicate 16B
2320 * records. Odd values indicate 32B
2323 #define CMPL_BASE_TYPE_MASK UINT32_C(0x3f)
2324 #define CMPL_BASE_TYPE_SFT 0
2327 * Completion of TX packet. Length = 16B
2329 #define CMPL_BASE_TYPE_TX_L2 UINT32_C(0x0)
2332 * Completion of NO-OP. Length = 16B
2334 #define CMPL_BASE_TYPE_NO_OP UINT32_C(0x1)
2336 * TX L2 coalesced completion:
2337 * Completion of coalesced TX packet. Length = 16B
2339 #define CMPL_BASE_TYPE_TX_L2_COAL UINT32_C(0x2)
2341 * TX L2 PTP completion:
2342 * Completion of PTP TX packet. Length = 32B
2344 #define CMPL_BASE_TYPE_TX_L2_PTP UINT32_C(0x3)
2346 * RX L2 TPA Start V2 Completion:
2347 * Completion of and L2 RX packet. Length = 32B
2348 * This is the new version of the RX_TPA_START completion used
2349 * in SR2 and later chips.
2351 #define CMPL_BASE_TYPE_RX_TPA_START_V2 UINT32_C(0xd)
2353 * RX L2 V2 completion:
2354 * Completion of and L2 RX packet. Length = 32B
2355 * This is the new version of the RX_L2 completion used in SR2
2358 #define CMPL_BASE_TYPE_RX_L2_V2 UINT32_C(0xf)
2361 * Completion of and L2 RX packet. Length = 32B
2363 #define CMPL_BASE_TYPE_RX_L2 UINT32_C(0x11)
2365 * RX Aggregation Buffer completion :
2366 * Completion of an L2 aggregation buffer in support of
2367 * TPA, HDS, or Jumbo packet completion. Length = 16B
2369 #define CMPL_BASE_TYPE_RX_AGG UINT32_C(0x12)
2371 * RX L2 TPA Start Completion:
2372 * Completion at the beginning of a TPA operation.
2375 #define CMPL_BASE_TYPE_RX_TPA_START UINT32_C(0x13)
2377 * RX L2 TPA End Completion:
2378 * Completion at the end of a TPA operation.
2381 #define CMPL_BASE_TYPE_RX_TPA_END UINT32_C(0x15)
2383 * Statistics Ejection Completion:
2384 * Completion of statistics data ejection buffer.
2387 #define CMPL_BASE_TYPE_STAT_EJECT UINT32_C(0x1a)
2389 * VEE Flush Completion:
2390 * This completion is inserted manually by
2391 * the Primate and processed by the VEE hardware to ensure that
2392 * all completions on a VEE function have been processed by the
2393 * VEE hardware before FLR process is completed.
2395 #define CMPL_BASE_TYPE_VEE_FLUSH UINT32_C(0x1c)
2397 * Mid Path Short Completion :
2398 * Completion of a Mid Path Command. Length = 16B
2400 #define CMPL_BASE_TYPE_MID_PATH_SHORT UINT32_C(0x1e)
2402 * Mid Path Long Completion :
2403 * Completion of a Mid Path Command. Length = 32B
2405 #define CMPL_BASE_TYPE_MID_PATH_LONG UINT32_C(0x1f)
2407 * HWRM Command Completion:
2408 * Completion of an HWRM command.
2410 #define CMPL_BASE_TYPE_HWRM_DONE UINT32_C(0x20)
2411 /* Forwarded HWRM Request */
2412 #define CMPL_BASE_TYPE_HWRM_FWD_REQ UINT32_C(0x22)
2413 /* Forwarded HWRM Response */
2414 #define CMPL_BASE_TYPE_HWRM_FWD_RESP UINT32_C(0x24)
2415 /* HWRM Asynchronous Event Information */
2416 #define CMPL_BASE_TYPE_HWRM_ASYNC_EVENT UINT32_C(0x2e)
2417 /* CQ Notification */
2418 #define CMPL_BASE_TYPE_CQ_NOTIFICATION UINT32_C(0x30)
2419 /* SRQ Threshold Event */
2420 #define CMPL_BASE_TYPE_SRQ_EVENT UINT32_C(0x32)
2421 /* DBQ Threshold Event */
2422 #define CMPL_BASE_TYPE_DBQ_EVENT UINT32_C(0x34)
2423 /* QP Async Notification */
2424 #define CMPL_BASE_TYPE_QP_EVENT UINT32_C(0x38)
2425 /* Function Async Notification */
2426 #define CMPL_BASE_TYPE_FUNC_EVENT UINT32_C(0x3a)
2427 #define CMPL_BASE_TYPE_LAST CMPL_BASE_TYPE_FUNC_EVENT
2433 * This value is written by the NIC such that it will be different
2434 * for each pass through the completion queue. The even passes
2435 * will write 1. The odd passes will write 0.
2438 #define CMPL_BASE_V UINT32_C(0x1)
2439 #define CMPL_BASE_INFO3_MASK UINT32_C(0xfffffffe)
2440 #define CMPL_BASE_INFO3_SFT 1
2445 /* tx_cmpl (size:128b/16B) */
2447 uint16_t flags_type;
2449 * This field indicates the exact type of the completion.
2450 * By convention, the LSB identifies the length of the
2451 * record in 16B units. Even values indicate 16B
2452 * records. Odd values indicate 32B
2455 #define TX_CMPL_TYPE_MASK UINT32_C(0x3f)
2456 #define TX_CMPL_TYPE_SFT 0
2459 * Completion of TX packet. Length = 16B
2461 #define TX_CMPL_TYPE_TX_L2 UINT32_C(0x0)
2462 #define TX_CMPL_TYPE_LAST TX_CMPL_TYPE_TX_L2
2463 #define TX_CMPL_FLAGS_MASK UINT32_C(0xffc0)
2464 #define TX_CMPL_FLAGS_SFT 6
2466 * When this bit is '1', it indicates a packet that has an
2467 * error of some type. Type of error is indicated in
2470 #define TX_CMPL_FLAGS_ERROR UINT32_C(0x40)
2472 * When this bit is '1', it indicates that the packet completed
2473 * was transmitted using the push acceleration data provided
2474 * by the driver. When this bit is '0', it indicates that the
2475 * packet had not push acceleration data written or was executed
2476 * as a normal packet even though push data was provided.
2478 #define TX_CMPL_FLAGS_PUSH UINT32_C(0x80)
2479 /* unused1 is 16 b */
2482 * This is a copy of the opaque field from the first TX BD of this
2483 * transmitted packet. Note that, if the packet was described by a short
2484 * CSO or short CSO inline BD, then the 16-bit opaque field from the
2485 * short CSO BD will appear in the bottom 16 bits of this field.
2490 * This value is written by the NIC such that it will be different
2491 * for each pass through the completion queue. The even passes
2492 * will write 1. The odd passes will write 0.
2494 #define TX_CMPL_V UINT32_C(0x1)
2495 #define TX_CMPL_ERRORS_MASK UINT32_C(0xfffe)
2496 #define TX_CMPL_ERRORS_SFT 1
2498 * This error indicates that there was some sort of problem
2499 * with the BDs for the packet.
2501 #define TX_CMPL_ERRORS_BUFFER_ERROR_MASK UINT32_C(0xe)
2502 #define TX_CMPL_ERRORS_BUFFER_ERROR_SFT 1
2504 #define TX_CMPL_ERRORS_BUFFER_ERROR_NO_ERROR \
2505 (UINT32_C(0x0) << 1)
2508 * BDs were not formatted correctly.
2510 #define TX_CMPL_ERRORS_BUFFER_ERROR_BAD_FMT \
2511 (UINT32_C(0x2) << 1)
2512 #define TX_CMPL_ERRORS_BUFFER_ERROR_LAST \
2513 TX_CMPL_ERRORS_BUFFER_ERROR_BAD_FMT
2515 * When this bit is '1', it indicates that the length of
2516 * the packet was zero. No packet was transmitted.
2518 #define TX_CMPL_ERRORS_ZERO_LENGTH_PKT UINT32_C(0x10)
2520 * When this bit is '1', it indicates that the packet
2521 * was longer than the programmed limit in TDI. No
2522 * packet was transmitted.
2524 #define TX_CMPL_ERRORS_EXCESSIVE_BD_LENGTH UINT32_C(0x20)
2526 * When this bit is '1', it indicates that one or more of the
2527 * BDs associated with this packet generated a PCI error.
2528 * This probably means the address was not valid.
2530 #define TX_CMPL_ERRORS_DMA_ERROR UINT32_C(0x40)
2532 * When this bit is '1', it indicates that the packet was longer
2533 * than indicated by the hint. No packet was transmitted.
2535 #define TX_CMPL_ERRORS_HINT_TOO_SHORT UINT32_C(0x80)
2537 * When this bit is '1', it indicates that the packet was
2538 * dropped due to Poison TLP error on one or more of the
2539 * TLPs in the PXP completion.
2541 #define TX_CMPL_ERRORS_POISON_TLP_ERROR UINT32_C(0x100)
2543 * When this bit is '1', it indicates that the packet was dropped
2544 * due to a transient internal error in TDC. The packet or LSO can
2545 * be retried and may transmit successfully on a subsequent attempt.
2547 #define TX_CMPL_ERRORS_INTERNAL_ERROR UINT32_C(0x200)
2549 * When this bit is '1', it was not possible to collect a a timestamp
2550 * for a PTP completion, in which case the timestamp_hi and
2551 * timestamp_lo fields are invalid. When this bit is '0' for a PTP
2552 * completion, the timestamp_hi and timestamp_lo fields are valid.
2553 * RJRN will copy the value of this bit into the field of the same
2554 * name in all TX completions, regardless of whether such completions
2555 * are PTP completions or other TX completions.
2557 #define TX_CMPL_ERRORS_TIMESTAMP_INVALID_ERROR UINT32_C(0x400)
2558 /* unused2 is 16 b */
2560 /* unused3 is 32 b */
2564 /* tx_cmpl_coal (size:128b/16B) */
2565 struct tx_cmpl_coal {
2566 uint16_t flags_type;
2568 * This field indicates the exact type of the completion.
2569 * By convention, the LSB identifies the length of the
2570 * record in 16B units. Even values indicate 16B
2571 * records. Odd values indicate 32B
2574 #define TX_CMPL_COAL_TYPE_MASK UINT32_C(0x3f)
2575 #define TX_CMPL_COAL_TYPE_SFT 0
2577 * TX L2 coalesced completion:
2578 * Completion of TX packet. Length = 16B
2580 #define TX_CMPL_COAL_TYPE_TX_L2_COAL UINT32_C(0x2)
2581 #define TX_CMPL_COAL_TYPE_LAST TX_CMPL_COAL_TYPE_TX_L2_COAL
2582 #define TX_CMPL_COAL_FLAGS_MASK UINT32_C(0xffc0)
2583 #define TX_CMPL_COAL_FLAGS_SFT 6
2585 * When this bit is '1', it indicates a packet that has an
2586 * error of some type. Type of error is indicated in
2589 #define TX_CMPL_COAL_FLAGS_ERROR UINT32_C(0x40)
2591 * When this bit is '1', it indicates that the packet completed
2592 * was transmitted using the push acceleration data provided
2593 * by the driver. When this bit is '0', it indicates that the
2594 * packet had not push acceleration data written or was executed
2595 * as a normal packet even though push data was provided.
2597 #define TX_CMPL_COAL_FLAGS_PUSH UINT32_C(0x80)
2598 /* unused1 is 16 b */
2601 * This is a copy of the opaque field from the first TX BD of the packet
2602 * which corresponds with the reported sq_cons_idx. Note that, with
2603 * coalesced completions, completions are generated for only some of the
2604 * packets. The driver will see the opaque field for only those packets.
2605 * Note that, if the packet was described by a short CSO or short CSO
2606 * inline BD, then the 16-bit opaque field from the short CSO BD will
2607 * appear in the bottom 16 bits of this field. For TX rings with
2608 * completion coalescing enabled (which would use the coalesced
2609 * completion record), it is suggested that the driver populate the
2610 * opaque field to indicate the specific TX ring with which the
2611 * completion is associated, then utilize the opaque and sq_cons_idx
2612 * fields in the coalesced completion record to determine the specific
2613 * packets that are to be completed on that ring.
2618 * This value is written by the NIC such that it will be different
2619 * for each pass through the completion queue. The even passes
2620 * will write 1. The odd passes will write 0.
2622 #define TX_CMPL_COAL_V UINT32_C(0x1)
2623 #define TX_CMPL_COAL_ERRORS_MASK \
2625 #define TX_CMPL_COAL_ERRORS_SFT 1
2627 * This error indicates that there was some sort of problem
2628 * with the BDs for the packet.
2630 #define TX_CMPL_COAL_ERRORS_BUFFER_ERROR_MASK UINT32_C(0xe)
2631 #define TX_CMPL_COAL_ERRORS_BUFFER_ERROR_SFT 1
2633 #define TX_CMPL_COAL_ERRORS_BUFFER_ERROR_NO_ERROR \
2634 (UINT32_C(0x0) << 1)
2637 * BDs were not formatted correctly.
2639 #define TX_CMPL_COAL_ERRORS_BUFFER_ERROR_BAD_FMT \
2640 (UINT32_C(0x2) << 1)
2641 #define TX_CMPL_COAL_ERRORS_BUFFER_ERROR_LAST \
2642 TX_CMPL_COAL_ERRORS_BUFFER_ERROR_BAD_FMT
2644 * When this bit is '1', it indicates that the length of
2645 * the packet was zero. No packet was transmitted.
2647 #define TX_CMPL_COAL_ERRORS_ZERO_LENGTH_PKT UINT32_C(0x10)
2649 * When this bit is '1', it indicates that the packet
2650 * was longer than the programmed limit in TDI. No
2651 * packet was transmitted.
2653 #define TX_CMPL_COAL_ERRORS_EXCESSIVE_BD_LENGTH UINT32_C(0x20)
2655 * When this bit is '1', it indicates that one or more of the
2656 * BDs associated with this packet generated a PCI error.
2657 * This probably means the address was not valid.
2659 #define TX_CMPL_COAL_ERRORS_DMA_ERROR UINT32_C(0x40)
2661 * When this bit is '1', it indicates that the packet was longer
2662 * than indicated by the hint. No packet was transmitted.
2664 #define TX_CMPL_COAL_ERRORS_HINT_TOO_SHORT UINT32_C(0x80)
2666 * When this bit is '1', it indicates that the packet was
2667 * dropped due to Poison TLP error on one or more of the
2668 * TLPs in the PXP completion.
2670 #define TX_CMPL_COAL_ERRORS_POISON_TLP_ERROR \
2673 * When this bit is '1', it indicates that the packet was dropped
2674 * due to a transient internal error in TDC. The packet or LSO can
2675 * be retried and may transmit successfully on a subsequent attempt.
2677 #define TX_CMPL_COAL_ERRORS_INTERNAL_ERROR \
2680 * When this bit is '1', it was not possible to collect a a timestamp
2681 * for a PTP completion, in which case the timestamp_hi and
2682 * timestamp_lo fields are invalid. When this bit is '0' for a PTP
2683 * completion, the timestamp_hi and timestamp_lo fields are valid.
2684 * RJRN will copy the value of this bit into the field of the same
2685 * name in all TX completions, regardless of whether such
2686 * completions are PTP completions or other TX completions.
2688 #define TX_CMPL_COAL_ERRORS_TIMESTAMP_INVALID_ERROR \
2690 /* unused2 is 16 b */
2692 uint32_t sq_cons_idx;
2694 * This value is SQ index for the start of the packet following the
2695 * last completed packet.
2697 #define TX_CMPL_COAL_SQ_CONS_IDX_MASK UINT32_C(0xffffff)
2698 #define TX_CMPL_COAL_SQ_CONS_IDX_SFT 0
2701 /* tx_cmpl_ptp (size:128b/16B) */
2702 struct tx_cmpl_ptp {
2703 uint16_t flags_type;
2705 * This field indicates the exact type of the completion.
2706 * By convention, the LSB identifies the length of the
2707 * record in 16B units. Even values indicate 16B
2708 * records. Odd values indicate 32B
2711 #define TX_CMPL_PTP_TYPE_MASK UINT32_C(0x3f)
2712 #define TX_CMPL_PTP_TYPE_SFT 0
2714 * TX L2 PTP completion:
2715 * Completion of TX packet. Length = 32B
2717 #define TX_CMPL_PTP_TYPE_TX_L2_PTP UINT32_C(0x2)
2718 #define TX_CMPL_PTP_TYPE_LAST TX_CMPL_PTP_TYPE_TX_L2_PTP
2719 #define TX_CMPL_PTP_FLAGS_MASK UINT32_C(0xffc0)
2720 #define TX_CMPL_PTP_FLAGS_SFT 6
2722 * When this bit is '1', it indicates a packet that has an
2723 * error of some type. Type of error is indicated in
2726 #define TX_CMPL_PTP_FLAGS_ERROR UINT32_C(0x40)
2728 * When this bit is '1', it indicates that the packet completed
2729 * was transmitted using the push acceleration data provided
2730 * by the driver. When this bit is '0', it indicates that the
2731 * packet had not push acceleration data written or was executed
2732 * as a normal packet even though push data was provided.
2734 #define TX_CMPL_PTP_FLAGS_PUSH UINT32_C(0x80)
2735 /* unused1 is 16 b */
2738 * This is a copy of the opaque field from the first TX BD of this
2739 * transmitted packet. Note that, if the packet was described by a short
2740 * CSO or short CSO inline BD, then the 16-bit opaque field from the
2741 * short CSO BD will appear in the bottom 16 bits of this field.
2746 * This value is written by the NIC such that it will be different
2747 * for each pass through the completion queue. The even passes
2748 * will write 1. The odd passes will write 0.
2750 #define TX_CMPL_PTP_V UINT32_C(0x1)
2751 #define TX_CMPL_PTP_ERRORS_MASK UINT32_C(0xfffe)
2752 #define TX_CMPL_PTP_ERRORS_SFT 1
2754 * This error indicates that there was some sort of problem
2755 * with the BDs for the packet.
2757 #define TX_CMPL_PTP_ERRORS_BUFFER_ERROR_MASK UINT32_C(0xe)
2758 #define TX_CMPL_PTP_ERRORS_BUFFER_ERROR_SFT 1
2760 #define TX_CMPL_PTP_ERRORS_BUFFER_ERROR_NO_ERROR \
2761 (UINT32_C(0x0) << 1)
2764 * BDs were not formatted correctly.
2766 #define TX_CMPL_PTP_ERRORS_BUFFER_ERROR_BAD_FMT \
2767 (UINT32_C(0x2) << 1)
2768 #define TX_CMPL_PTP_ERRORS_BUFFER_ERROR_LAST \
2769 TX_CMPL_PTP_ERRORS_BUFFER_ERROR_BAD_FMT
2771 * When this bit is '1', it indicates that the length of
2772 * the packet was zero. No packet was transmitted.
2774 #define TX_CMPL_PTP_ERRORS_ZERO_LENGTH_PKT UINT32_C(0x10)
2776 * When this bit is '1', it indicates that the packet
2777 * was longer than the programmed limit in TDI. No
2778 * packet was transmitted.
2780 #define TX_CMPL_PTP_ERRORS_EXCESSIVE_BD_LENGTH UINT32_C(0x20)
2782 * When this bit is '1', it indicates that one or more of the
2783 * BDs associated with this packet generated a PCI error.
2784 * This probably means the address was not valid.
2786 #define TX_CMPL_PTP_ERRORS_DMA_ERROR UINT32_C(0x40)
2788 * When this bit is '1', it indicates that the packet was longer
2789 * than indicated by the hint. No packet was transmitted.
2791 #define TX_CMPL_PTP_ERRORS_HINT_TOO_SHORT UINT32_C(0x80)
2793 * When this bit is '1', it indicates that the packet was
2794 * dropped due to Poison TLP error on one or more of the
2795 * TLPs in the PXP completion.
2797 #define TX_CMPL_PTP_ERRORS_POISON_TLP_ERROR UINT32_C(0x100)
2799 * When this bit is '1', it indicates that the packet was dropped due
2800 * to a transient internal error in TDC. The packet or LSO can be
2801 * retried and may transmit successfully on a subsequent attempt.
2803 #define TX_CMPL_PTP_ERRORS_INTERNAL_ERROR UINT32_C(0x200)
2805 * When this bit is '1', it was not possible to collect a a timestamp
2806 * for a PTP completion, in which case the timestamp_hi and
2807 * timestamp_lo fields are invalid. When this bit is '0' for a PTP
2808 * completion, the timestamp_hi and timestamp_lo fields are valid.
2809 * RJRN will copy the value of this bit into the field of the same
2810 * name in all TX completions, regardless of whether such
2811 * completions are PTP completions or other TX completions.
2813 #define TX_CMPL_PTP_ERRORS_TIMESTAMP_INVALID_ERROR UINT32_C(0x400)
2814 /* unused2 is 16 b */
2817 * This is timestamp value (lower 32bits) read from PM for the PTP
2818 * timestamp enabled packet.
2820 uint32_t timestamp_lo;
2823 /* tx_cmpl_ptp_hi (size:128b/16B) */
2824 struct tx_cmpl_ptp_hi {
2826 * This is timestamp value (lower 32bits) read from PM for the PTP
2827 * timestamp enabled packet.
2829 uint16_t timestamp_hi[3];
2830 uint16_t reserved16;
2833 * This value is written by the NIC such that it will be different for
2834 * each pass through the completion queue.The even passes will write 1.
2835 * The odd passes will write 0
2837 #define TX_CMPL_PTP_HI_V2 UINT32_C(0x1)
2840 /* rx_pkt_cmpl (size:128b/16B) */
2841 struct rx_pkt_cmpl {
2842 uint16_t flags_type;
2844 * This field indicates the exact type of the completion.
2845 * By convention, the LSB identifies the length of the
2846 * record in 16B units. Even values indicate 16B
2847 * records. Odd values indicate 32B
2850 #define RX_PKT_CMPL_TYPE_MASK UINT32_C(0x3f)
2851 #define RX_PKT_CMPL_TYPE_SFT 0
2854 * Completion of and L2 RX packet. Length = 32B
2856 #define RX_PKT_CMPL_TYPE_RX_L2 UINT32_C(0x11)
2857 #define RX_PKT_CMPL_TYPE_LAST RX_PKT_CMPL_TYPE_RX_L2
2858 #define RX_PKT_CMPL_FLAGS_MASK UINT32_C(0xffc0)
2859 #define RX_PKT_CMPL_FLAGS_SFT 6
2861 * When this bit is '1', it indicates a packet that has an
2862 * error of some type. Type of error is indicated in
2865 #define RX_PKT_CMPL_FLAGS_ERROR UINT32_C(0x40)
2866 /* This field indicates how the packet was placed in the buffer. */
2867 #define RX_PKT_CMPL_FLAGS_PLACEMENT_MASK UINT32_C(0x380)
2868 #define RX_PKT_CMPL_FLAGS_PLACEMENT_SFT 7
2871 * Packet was placed using normal algorithm.
2873 #define RX_PKT_CMPL_FLAGS_PLACEMENT_NORMAL (UINT32_C(0x0) << 7)
2876 * Packet was placed using jumbo algorithm.
2878 #define RX_PKT_CMPL_FLAGS_PLACEMENT_JUMBO (UINT32_C(0x1) << 7)
2880 * Header/Data Separation:
2881 * Packet was placed using Header/Data separation algorithm.
2882 * The separation location is indicated by the itype field.
2884 #define RX_PKT_CMPL_FLAGS_PLACEMENT_HDS (UINT32_C(0x2) << 7)
2885 #define RX_PKT_CMPL_FLAGS_PLACEMENT_LAST \
2886 RX_PKT_CMPL_FLAGS_PLACEMENT_HDS
2887 /* This bit is '1' if the RSS field in this completion is valid. */
2888 #define RX_PKT_CMPL_FLAGS_RSS_VALID UINT32_C(0x400)
2890 #define RX_PKT_CMPL_FLAGS_UNUSED UINT32_C(0x800)
2892 * This value indicates what the inner packet determined for the
2895 #define RX_PKT_CMPL_FLAGS_ITYPE_MASK UINT32_C(0xf000)
2896 #define RX_PKT_CMPL_FLAGS_ITYPE_SFT 12
2899 * Indicates that the packet type was not known.
2901 #define RX_PKT_CMPL_FLAGS_ITYPE_NOT_KNOWN \
2902 (UINT32_C(0x0) << 12)
2905 * Indicates that the packet was an IP packet, but further
2906 * classification was not possible.
2908 #define RX_PKT_CMPL_FLAGS_ITYPE_IP \
2909 (UINT32_C(0x1) << 12)
2912 * Indicates that the packet was IP and TCP.
2913 * This indicates that the payload_offset field is valid.
2915 #define RX_PKT_CMPL_FLAGS_ITYPE_TCP \
2916 (UINT32_C(0x2) << 12)
2919 * Indicates that the packet was IP and UDP.
2920 * This indicates that the payload_offset field is valid.
2922 #define RX_PKT_CMPL_FLAGS_ITYPE_UDP \
2923 (UINT32_C(0x3) << 12)
2926 * Indicates that the packet was recognized as a FCoE.
2927 * This also indicates that the payload_offset field is valid.
2929 #define RX_PKT_CMPL_FLAGS_ITYPE_FCOE \
2930 (UINT32_C(0x4) << 12)
2933 * Indicates that the packet was recognized as a RoCE.
2934 * This also indicates that the payload_offset field is valid.
2936 #define RX_PKT_CMPL_FLAGS_ITYPE_ROCE \
2937 (UINT32_C(0x5) << 12)
2940 * Indicates that the packet was recognized as ICMP.
2941 * This indicates that the payload_offset field is valid.
2943 #define RX_PKT_CMPL_FLAGS_ITYPE_ICMP \
2944 (UINT32_C(0x7) << 12)
2946 * PtP packet wo/timestamp:
2947 * Indicates that the packet was recognized as a PtP
2950 #define RX_PKT_CMPL_FLAGS_ITYPE_PTP_WO_TIMESTAMP \
2951 (UINT32_C(0x8) << 12)
2953 * PtP packet w/timestamp:
2954 * Indicates that the packet was recognized as a PtP
2955 * packet and that a timestamp was taken for the packet.
2957 #define RX_PKT_CMPL_FLAGS_ITYPE_PTP_W_TIMESTAMP \
2958 (UINT32_C(0x9) << 12)
2959 #define RX_PKT_CMPL_FLAGS_ITYPE_LAST \
2960 RX_PKT_CMPL_FLAGS_ITYPE_PTP_W_TIMESTAMP
2962 * This is the length of the data for the packet stored in the
2963 * buffer(s) identified by the opaque value. This includes
2964 * the packet BD and any associated buffer BDs. This does not include
2965 * the length of any data places in aggregation BDs.
2969 * This is a copy of the opaque field from the RX BD this completion
2973 uint8_t agg_bufs_v1;
2975 * This value is written by the NIC such that it will be different
2976 * for each pass through the completion queue. The even passes
2977 * will write 1. The odd passes will write 0.
2979 #define RX_PKT_CMPL_V1 UINT32_C(0x1)
2981 * This value is the number of aggregation buffers that follow this
2982 * entry in the completion ring that are a part of this packet.
2983 * If the value is zero, then the packet is completely contained
2984 * in the buffer space provided for the packet in the RX ring.
2986 #define RX_PKT_CMPL_AGG_BUFS_MASK UINT32_C(0x3e)
2987 #define RX_PKT_CMPL_AGG_BUFS_SFT 1
2988 /* unused1 is 2 b */
2989 #define RX_PKT_CMPL_UNUSED1_MASK UINT32_C(0xc0)
2990 #define RX_PKT_CMPL_UNUSED1_SFT 6
2992 * This is the RSS hash type for the packet. The value is packed
2993 * {tuple_extrac_op[1:0],rss_profile_id[4:0],tuple_extrac_op[2]}.
2995 * The value of tuple_extrac_op provides the information about
2996 * what fields the hash was computed on.
2997 * * 0: The RSS hash was computed over source IP address,
2998 * destination IP address, source port, and destination port of inner
2999 * IP and TCP or UDP headers. Note: For non-tunneled packets,
3000 * the packet headers are considered inner packet headers for the RSS
3001 * hash computation purpose.
3002 * * 1: The RSS hash was computed over source IP address and destination
3003 * IP address of inner IP header. Note: For non-tunneled packets,
3004 * the packet headers are considered inner packet headers for the RSS
3005 * hash computation purpose.
3006 * * 2: The RSS hash was computed over source IP address,
3007 * destination IP address, source port, and destination port of
3008 * IP and TCP or UDP headers of outer tunnel headers.
3009 * Note: For non-tunneled packets, this value is not applicable.
3010 * * 3: The RSS hash was computed over source IP address and
3011 * destination IP address of IP header of outer tunnel headers.
3012 * Note: For non-tunneled packets, this value is not applicable.
3014 * Note that 4-tuples values listed above are applicable
3015 * for layer 4 protocols supported and enabled for RSS in the hardware,
3016 * HWRM firmware, and drivers. For example, if RSS hash is supported and
3017 * enabled for TCP traffic only, then the values of tuple_extract_op
3018 * corresponding to 4-tuples are only valid for TCP traffic.
3020 uint8_t rss_hash_type;
3022 * This value indicates the offset in bytes from the beginning of the packet
3023 * where the inner payload starts. This value is valid for TCP, UDP,
3024 * FCoE, and RoCE packets.
3026 * A value of zero indicates that header is 256B into the packet.
3028 uint8_t payload_offset;
3029 /* unused2 is 8 b */
3032 * This value is the RSS hash value calculated for the packet
3033 * based on the mode bits and key value in the VNIC.
3038 /* Last 16 bytes of rx_pkt_cmpl. */
3039 /* rx_pkt_cmpl_hi (size:128b/16B) */
3040 struct rx_pkt_cmpl_hi {
3043 * This indicates that the ip checksum was calculated for the
3044 * inner packet and that the ip_cs_error field indicates if there
3047 #define RX_PKT_CMPL_FLAGS2_IP_CS_CALC UINT32_C(0x1)
3049 * This indicates that the TCP, UDP or ICMP checksum was
3050 * calculated for the inner packet and that the l4_cs_error field
3051 * indicates if there was an error.
3053 #define RX_PKT_CMPL_FLAGS2_L4_CS_CALC UINT32_C(0x2)
3055 * This indicates that the ip checksum was calculated for the
3056 * tunnel header and that the t_ip_cs_error field indicates if there
3059 #define RX_PKT_CMPL_FLAGS2_T_IP_CS_CALC UINT32_C(0x4)
3061 * This indicates that the UDP checksum was
3062 * calculated for the tunnel packet and that the t_l4_cs_error field
3063 * indicates if there was an error.
3065 #define RX_PKT_CMPL_FLAGS2_T_L4_CS_CALC UINT32_C(0x8)
3066 /* This value indicates what format the metadata field is. */
3067 #define RX_PKT_CMPL_FLAGS2_META_FORMAT_MASK UINT32_C(0xf0)
3068 #define RX_PKT_CMPL_FLAGS2_META_FORMAT_SFT 4
3069 /* No metadata information. Value is zero. */
3070 #define RX_PKT_CMPL_FLAGS2_META_FORMAT_NONE \
3071 (UINT32_C(0x0) << 4)
3073 * The metadata field contains the VLAN tag and TPID value.
3074 * - metadata[11:0] contains the vlan VID value.
3075 * - metadata[12] contains the vlan DE value.
3076 * - metadata[15:13] contains the vlan PRI value.
3077 * - metadata[31:16] contains the vlan TPID value.
3079 #define RX_PKT_CMPL_FLAGS2_META_FORMAT_VLAN \
3080 (UINT32_C(0x1) << 4)
3082 * If ext_meta_format is equal to 1, the metadata field
3083 * contains the lower 16b of the tunnel ID value, justified
3085 * - VXLAN = VNI[23:0] -> VXLAN Network ID
3086 * - Geneve (NGE) = VNI[23:0] a-> Virtual Network Identifier.
3087 * - NVGRE = TNI[23:0] -> Tenant Network ID
3088 * - GRE = KEY[31:0] -> key field with bit mask. zero if K = 0
3089 * - IPV4 = 0 (not populated)
3090 * - IPV6 = Flow Label[19:0]
3091 * - PPPoE = sessionID[15:0]
3092 * - MPLs = Outer label[19:0]
3093 * - UPAR = Selected[31:0] with bit mask
3095 #define RX_PKT_CMPL_FLAGS2_META_FORMAT_TUNNEL_ID \
3096 (UINT32_C(0x2) << 4)
3098 * if ext_meta_format is equal to 1, metadata field contains
3099 * 16b metadata from the prepended header (chdr_data).
3101 #define RX_PKT_CMPL_FLAGS2_META_FORMAT_CHDR_DATA \
3102 (UINT32_C(0x3) << 4)
3104 * If ext_meta_format is equal to 1, the metadata field contains
3105 * the outer_l3_offset, inner_l2_offset, inner_l3_offset and
3107 * - metadata[8:0] contains the outer_l3_offset.
3108 * - metadata[17:9] contains the inner_l2_offset.
3109 * - metadata[26:18] contains the inner_l3_offset.
3110 * - metadata[31:27] contains the inner_l4_size.
3112 #define RX_PKT_CMPL_FLAGS2_META_FORMAT_HDR_OFFSET \
3113 (UINT32_C(0x4) << 4)
3114 #define RX_PKT_CMPL_FLAGS2_META_FORMAT_LAST \
3115 RX_PKT_CMPL_FLAGS2_META_FORMAT_HDR_OFFSET
3117 * This field indicates the IP type for the inner-most IP header.
3118 * A value of '0' indicates IPv4. A value of '1' indicates IPv6.
3119 * This value is only valid if itype indicates a packet
3120 * with an IP header.
3122 #define RX_PKT_CMPL_FLAGS2_IP_TYPE UINT32_C(0x100)
3124 * This indicates that the complete 1's complement checksum was
3125 * calculated for the packet.
3127 #define RX_PKT_CMPL_FLAGS2_COMPLETE_CHECKSUM_CALC UINT32_C(0x200)
3129 * The combination of this value and meta_format indicated what
3130 * format the metadata field is.
3132 #define RX_PKT_CMPL_FLAGS2_EXT_META_FORMAT_MASK UINT32_C(0xc00)
3133 #define RX_PKT_CMPL_FLAGS2_EXT_META_FORMAT_SFT 10
3135 * This value is the complete 1's complement checksum calculated from
3136 * the start of the outer L3 header to the end of the packet (not
3137 * including the ethernet crc). It is valid when the
3138 * 'complete_checksum_calc' flag is set.
3140 #define RX_PKT_CMPL_FLAGS2_COMPLETE_CHECKSUM_MASK \
3141 UINT32_C(0xffff0000)
3142 #define RX_PKT_CMPL_FLAGS2_COMPLETE_CHECKSUM_SFT 16
3144 * This is data from the CFA block as indicated by the meta_format
3148 /* When meta_format=1, this value is the VLAN VID. */
3149 #define RX_PKT_CMPL_METADATA_VID_MASK UINT32_C(0xfff)
3150 #define RX_PKT_CMPL_METADATA_VID_SFT 0
3151 /* When meta_format=1, this value is the VLAN DE. */
3152 #define RX_PKT_CMPL_METADATA_DE UINT32_C(0x1000)
3153 /* When meta_format=1, this value is the VLAN PRI. */
3154 #define RX_PKT_CMPL_METADATA_PRI_MASK UINT32_C(0xe000)
3155 #define RX_PKT_CMPL_METADATA_PRI_SFT 13
3156 /* When meta_format=1, this value is the VLAN TPID. */
3157 #define RX_PKT_CMPL_METADATA_TPID_MASK UINT32_C(0xffff0000)
3158 #define RX_PKT_CMPL_METADATA_TPID_SFT 16
3161 * This value is written by the NIC such that it will be different
3162 * for each pass through the completion queue. The even passes
3163 * will write 1. The odd passes will write 0.
3165 #define RX_PKT_CMPL_V2 \
3167 #define RX_PKT_CMPL_ERRORS_MASK \
3169 #define RX_PKT_CMPL_ERRORS_SFT 1
3171 * This error indicates that there was some sort of problem with
3172 * the BDs for the packet that was found after part of the
3173 * packet was already placed. The packet should be treated as
3176 #define RX_PKT_CMPL_ERRORS_BUFFER_ERROR_MASK \
3178 #define RX_PKT_CMPL_ERRORS_BUFFER_ERROR_SFT 1
3179 /* No buffer error */
3180 #define RX_PKT_CMPL_ERRORS_BUFFER_ERROR_NO_BUFFER \
3181 (UINT32_C(0x0) << 1)
3184 * Packet did not fit into packet buffer provided.
3185 * For regular placement, this means the packet did not fit
3186 * in the buffer provided. For HDS and jumbo placement, this
3187 * means that the packet could not be placed into 7 physical
3190 #define RX_PKT_CMPL_ERRORS_BUFFER_ERROR_DID_NOT_FIT \
3191 (UINT32_C(0x1) << 1)
3194 * All BDs needed for the packet were not on-chip when
3195 * the packet arrived.
3197 #define RX_PKT_CMPL_ERRORS_BUFFER_ERROR_NOT_ON_CHIP \
3198 (UINT32_C(0x2) << 1)
3201 * BDs were not formatted correctly.
3203 #define RX_PKT_CMPL_ERRORS_BUFFER_ERROR_BAD_FORMAT \
3204 (UINT32_C(0x3) << 1)
3207 * There was a bad_format error on the previous operation
3209 #define RX_PKT_CMPL_ERRORS_BUFFER_ERROR_FLUSH \
3210 (UINT32_C(0x5) << 1)
3211 #define RX_PKT_CMPL_ERRORS_BUFFER_ERROR_LAST \
3212 RX_PKT_CMPL_ERRORS_BUFFER_ERROR_FLUSH
3214 * This indicates that there was an error in the IP header
3217 #define RX_PKT_CMPL_ERRORS_IP_CS_ERROR \
3220 * This indicates that there was an error in the TCP, UDP
3223 #define RX_PKT_CMPL_ERRORS_L4_CS_ERROR \
3226 * This indicates that there was an error in the tunnel
3227 * IP header checksum.
3229 #define RX_PKT_CMPL_ERRORS_T_IP_CS_ERROR \
3232 * This indicates that there was an error in the tunnel
3235 #define RX_PKT_CMPL_ERRORS_T_L4_CS_ERROR \
3238 * This indicates that there was a CRC error on either an FCoE
3239 * or RoCE packet. The itype indicates the packet type.
3241 #define RX_PKT_CMPL_ERRORS_CRC_ERROR \
3244 * This indicates that there was an error in the tunnel
3245 * portion of the packet when this
3246 * field is non-zero.
3248 #define RX_PKT_CMPL_ERRORS_T_PKT_ERROR_MASK \
3250 #define RX_PKT_CMPL_ERRORS_T_PKT_ERROR_SFT 9
3252 * No additional error occurred on the tunnel portion
3253 * or the packet of the packet does not have a tunnel.
3255 #define RX_PKT_CMPL_ERRORS_T_PKT_ERROR_NO_ERROR \
3256 (UINT32_C(0x0) << 9)
3258 * Indicates that IP header version does not match
3259 * expectation from L2 Ethertype for IPv4 and IPv6
3260 * in the tunnel header.
3262 #define RX_PKT_CMPL_ERRORS_T_PKT_ERROR_T_L3_BAD_VERSION \
3263 (UINT32_C(0x1) << 9)
3265 * Indicates that header length is out of range in the
3266 * tunnel header. Valid for
3269 #define RX_PKT_CMPL_ERRORS_T_PKT_ERROR_T_L3_BAD_HDR_LEN \
3270 (UINT32_C(0x2) << 9)
3272 * Indicates that the physical packet is shorter than that
3273 * claimed by the PPPoE header length for a tunnel PPPoE
3276 #define RX_PKT_CMPL_ERRORS_T_PKT_ERROR_TUNNEL_TOTAL_ERROR \
3277 (UINT32_C(0x3) << 9)
3279 * Indicates that physical packet is shorter than that claimed
3280 * by the tunnel l3 header length. Valid for IPv4, or IPv6
3281 * tunnel packet packets.
3283 #define RX_PKT_CMPL_ERRORS_T_PKT_ERROR_T_IP_TOTAL_ERROR \
3284 (UINT32_C(0x4) << 9)
3286 * Indicates that the physical packet is shorter than that
3287 * claimed by the tunnel UDP header length for a tunnel
3288 * UDP packet that is not fragmented.
3290 #define RX_PKT_CMPL_ERRORS_T_PKT_ERROR_T_UDP_TOTAL_ERROR \
3291 (UINT32_C(0x5) << 9)
3293 * indicates that the IPv4 TTL or IPv6 hop limit check
3294 * have failed (e.g. TTL = 0) in the tunnel header. Valid
3295 * for IPv4, and IPv6.
3297 #define RX_PKT_CMPL_ERRORS_T_PKT_ERROR_T_L3_BAD_TTL \
3298 (UINT32_C(0x6) << 9)
3299 #define RX_PKT_CMPL_ERRORS_T_PKT_ERROR_LAST \
3300 RX_PKT_CMPL_ERRORS_T_PKT_ERROR_T_L3_BAD_TTL
3302 * This indicates that there was an error in the inner
3303 * portion of the packet when this
3304 * field is non-zero.
3306 #define RX_PKT_CMPL_ERRORS_PKT_ERROR_MASK \
3308 #define RX_PKT_CMPL_ERRORS_PKT_ERROR_SFT 12
3310 * No additional error occurred on the tunnel portion
3311 * or the packet of the packet does not have a tunnel.
3313 #define RX_PKT_CMPL_ERRORS_PKT_ERROR_NO_ERROR \
3314 (UINT32_C(0x0) << 12)
3316 * Indicates that IP header version does not match
3317 * expectation from L2 Ethertype for IPv4 and IPv6 or that
3318 * option other than VFT was parsed on
3321 #define RX_PKT_CMPL_ERRORS_PKT_ERROR_L3_BAD_VERSION \
3322 (UINT32_C(0x1) << 12)
3324 * indicates that header length is out of range. Valid for
3327 #define RX_PKT_CMPL_ERRORS_PKT_ERROR_L3_BAD_HDR_LEN \
3328 (UINT32_C(0x2) << 12)
3330 * indicates that the IPv4 TTL or IPv6 hop limit check
3331 * have failed (e.g. TTL = 0). Valid for IPv4, and IPv6
3333 #define RX_PKT_CMPL_ERRORS_PKT_ERROR_L3_BAD_TTL \
3334 (UINT32_C(0x3) << 12)
3336 * Indicates that physical packet is shorter than that
3337 * claimed by the l3 header length. Valid for IPv4,
3338 * IPv6 packet or RoCE packets.
3340 #define RX_PKT_CMPL_ERRORS_PKT_ERROR_IP_TOTAL_ERROR \
3341 (UINT32_C(0x4) << 12)
3343 * Indicates that the physical packet is shorter than that
3344 * claimed by the UDP header length for a UDP packet that is
3347 #define RX_PKT_CMPL_ERRORS_PKT_ERROR_UDP_TOTAL_ERROR \
3348 (UINT32_C(0x5) << 12)
3350 * Indicates that TCP header length > IP payload. Valid for
3353 #define RX_PKT_CMPL_ERRORS_PKT_ERROR_L4_BAD_HDR_LEN \
3354 (UINT32_C(0x6) << 12)
3355 /* Indicates that TCP header length < 5. Valid for TCP. */
3356 #define RX_PKT_CMPL_ERRORS_PKT_ERROR_L4_BAD_HDR_LEN_TOO_SMALL \
3357 (UINT32_C(0x7) << 12)
3359 * Indicates that TCP option headers result in a TCP header
3360 * size that does not match data offset in TCP header. Valid
3363 #define RX_PKT_CMPL_ERRORS_PKT_ERROR_L4_BAD_OPT_LEN \
3364 (UINT32_C(0x8) << 12)
3365 #define RX_PKT_CMPL_ERRORS_PKT_ERROR_LAST \
3366 RX_PKT_CMPL_ERRORS_PKT_ERROR_L4_BAD_OPT_LEN
3368 * This field identifies the CFA action rule that was used for this
3374 * This value holds the reordering sequence number for the packet.
3375 * If the reordering sequence is not valid, then this value is zero.
3376 * The reordering domain for the packet is in the bottom 8 to 10b of
3377 * the rss_hash value. The bottom 20b of this value contain the
3378 * ordering domain value for the packet.
3380 #define RX_PKT_CMPL_REORDER_MASK UINT32_C(0xffffff)
3381 #define RX_PKT_CMPL_REORDER_SFT 0
3384 /* rx_pkt_v2_cmpl (size:128b/16B) */
3385 struct rx_pkt_v2_cmpl {
3386 uint16_t flags_type;
3388 * This field indicates the exact type of the completion.
3389 * By convention, the LSB identifies the length of the
3390 * record in 16B units. Even values indicate 16B
3391 * records. Odd values indicate 32B
3394 #define RX_PKT_V2_CMPL_TYPE_MASK UINT32_C(0x3f)
3395 #define RX_PKT_V2_CMPL_TYPE_SFT 0
3397 * RX L2 V2 completion:
3398 * Completion of and L2 RX packet. Length = 32B
3399 * This is the new version of the RX_L2 completion used in SR2
3402 #define RX_PKT_V2_CMPL_TYPE_RX_L2_V2 UINT32_C(0xf)
3403 #define RX_PKT_V2_CMPL_TYPE_LAST \
3404 RX_PKT_V2_CMPL_TYPE_RX_L2_V2
3405 #define RX_PKT_V2_CMPL_FLAGS_MASK UINT32_C(0xffc0)
3406 #define RX_PKT_V2_CMPL_FLAGS_SFT 6
3408 * When this bit is '1', it indicates a packet that has an
3409 * error of some type. Type of error is indicated in
3412 #define RX_PKT_V2_CMPL_FLAGS_ERROR UINT32_C(0x40)
3413 /* This field indicates how the packet was placed in the buffer. */
3414 #define RX_PKT_V2_CMPL_FLAGS_PLACEMENT_MASK UINT32_C(0x380)
3415 #define RX_PKT_V2_CMPL_FLAGS_PLACEMENT_SFT 7
3418 * Packet was placed using normal algorithm.
3420 #define RX_PKT_V2_CMPL_FLAGS_PLACEMENT_NORMAL \
3421 (UINT32_C(0x0) << 7)
3424 * Packet was placed using jumbo algorithm.
3426 #define RX_PKT_V2_CMPL_FLAGS_PLACEMENT_JUMBO \
3427 (UINT32_C(0x1) << 7)
3429 * Header/Data Separation:
3430 * Packet was placed using Header/Data separation algorithm.
3431 * The separation location is indicated by the itype field.
3433 #define RX_PKT_V2_CMPL_FLAGS_PLACEMENT_HDS \
3434 (UINT32_C(0x2) << 7)
3437 * Packet was placed using truncation algorithm. The
3438 * placed (truncated) length is indicated in the payload_offset
3439 * field. The original length is indicated in the len field.
3441 #define RX_PKT_V2_CMPL_FLAGS_PLACEMENT_TRUNCATION \
3442 (UINT32_C(0x3) << 7)
3443 #define RX_PKT_V2_CMPL_FLAGS_PLACEMENT_LAST \
3444 RX_PKT_V2_CMPL_FLAGS_PLACEMENT_TRUNCATION
3445 /* This bit is '1' if the RSS field in this completion is valid. */
3446 #define RX_PKT_V2_CMPL_FLAGS_RSS_VALID UINT32_C(0x400)
3448 * This bit is '1' if metadata has been added to the end of the
3449 * packet in host memory. Metadata starts at the first 32B boundary
3450 * after the end of the packet for regular and jumbo placement.
3451 * It starts at the first 32B boundary after the end of the header
3452 * for HDS placement. The length of the metadata is indicated in the
3455 #define RX_PKT_V2_CMPL_FLAGS_PKT_METADATA_PRESENT UINT32_C(0x800)
3457 * This value indicates what the inner packet determined for the
3460 #define RX_PKT_V2_CMPL_FLAGS_ITYPE_MASK UINT32_C(0xf000)
3461 #define RX_PKT_V2_CMPL_FLAGS_ITYPE_SFT 12
3464 * Indicates that the packet type was not known.
3466 #define RX_PKT_V2_CMPL_FLAGS_ITYPE_NOT_KNOWN \
3467 (UINT32_C(0x0) << 12)
3470 * Indicates that the packet was an IP packet, but further
3471 * classification was not possible.
3473 #define RX_PKT_V2_CMPL_FLAGS_ITYPE_IP \
3474 (UINT32_C(0x1) << 12)
3477 * Indicates that the packet was IP and TCP.
3478 * This indicates that the payload_offset field is valid.
3480 #define RX_PKT_V2_CMPL_FLAGS_ITYPE_TCP \
3481 (UINT32_C(0x2) << 12)
3484 * Indicates that the packet was IP and UDP.
3485 * This indicates that the payload_offset field is valid.
3487 #define RX_PKT_V2_CMPL_FLAGS_ITYPE_UDP \
3488 (UINT32_C(0x3) << 12)
3491 * Indicates that the packet was recognized as a FCoE.
3492 * This also indicates that the payload_offset field is valid.
3494 #define RX_PKT_V2_CMPL_FLAGS_ITYPE_FCOE \
3495 (UINT32_C(0x4) << 12)
3498 * Indicates that the packet was recognized as a RoCE.
3499 * This also indicates that the payload_offset field is valid.
3501 #define RX_PKT_V2_CMPL_FLAGS_ITYPE_ROCE \
3502 (UINT32_C(0x5) << 12)
3505 * Indicates that the packet was recognized as ICMP.
3506 * This indicates that the payload_offset field is valid.
3508 #define RX_PKT_V2_CMPL_FLAGS_ITYPE_ICMP \
3509 (UINT32_C(0x7) << 12)
3511 * PtP packet wo/timestamp:
3512 * Indicates that the packet was recognized as a PtP
3515 #define RX_PKT_V2_CMPL_FLAGS_ITYPE_PTP_WO_TIMESTAMP \
3516 (UINT32_C(0x8) << 12)
3518 * PtP packet w/timestamp:
3519 * Indicates that the packet was recognized as a PtP
3520 * packet and that a timestamp was taken for the packet.
3522 #define RX_PKT_V2_CMPL_FLAGS_ITYPE_PTP_W_TIMESTAMP \
3523 (UINT32_C(0x9) << 12)
3524 #define RX_PKT_V2_CMPL_FLAGS_ITYPE_LAST \
3525 RX_PKT_V2_CMPL_FLAGS_ITYPE_PTP_W_TIMESTAMP
3527 * This is the length of the data for the packet stored in the
3528 * buffer(s) identified by the opaque value. This includes
3529 * the packet BD and any associated buffer BDs. This does not include
3530 * the length of any data places in aggregation BDs.
3534 * This is a copy of the opaque field from the RX BD this completion
3538 uint8_t agg_bufs_v1;
3540 * This value is written by the NIC such that it will be different
3541 * for each pass through the completion queue. The even passes
3542 * will write 1. The odd passes will write 0.
3544 #define RX_PKT_V2_CMPL_V1 UINT32_C(0x1)
3546 * This value is the number of aggregation buffers that follow this
3547 * entry in the completion ring that are a part of this packet.
3548 * If the value is zero, then the packet is completely contained
3549 * in the buffer space provided for the packet in the RX ring.
3551 #define RX_PKT_V2_CMPL_AGG_BUFS_MASK UINT32_C(0x3e)
3552 #define RX_PKT_V2_CMPL_AGG_BUFS_SFT 1
3553 /* unused1 is 2 b */
3554 #define RX_PKT_V2_CMPL_UNUSED1_MASK UINT32_C(0xc0)
3555 #define RX_PKT_V2_CMPL_UNUSED1_SFT 6
3557 * This is the RSS hash type for the packet. The value is packed
3558 * {tuple_extrac_op[1:0],rss_profile_id[4:0],tuple_extrac_op[2]}.
3560 * The value of tuple_extrac_op provides the information about
3561 * what fields the hash was computed on.
3562 * * 0: The RSS hash was computed over source IP address,
3563 * destination IP address, source port, and destination port of inner
3564 * IP and TCP or UDP headers. Note: For non-tunneled packets,
3565 * the packet headers are considered inner packet headers for the RSS
3566 * hash computation purpose.
3567 * * 1: The RSS hash was computed over source IP address and destination
3568 * IP address of inner IP header. Note: For non-tunneled packets,
3569 * the packet headers are considered inner packet headers for the RSS
3570 * hash computation purpose.
3571 * * 2: The RSS hash was computed over source IP address,
3572 * destination IP address, source port, and destination port of
3573 * IP and TCP or UDP headers of outer tunnel headers.
3574 * Note: For non-tunneled packets, this value is not applicable.
3575 * * 3: The RSS hash was computed over source IP address and
3576 * destination IP address of IP header of outer tunnel headers.
3577 * Note: For non-tunneled packets, this value is not applicable.
3579 * Note that 4-tuples values listed above are applicable
3580 * for layer 4 protocols supported and enabled for RSS in the hardware,
3581 * HWRM firmware, and drivers. For example, if RSS hash is supported and
3582 * enabled for TCP traffic only, then the values of tuple_extract_op
3583 * corresponding to 4-tuples are only valid for TCP traffic.
3585 uint8_t rss_hash_type;
3586 uint16_t metadata1_payload_offset;
3588 * This is data from the CFA as indicated by the meta_format field.
3589 * If truncation placement is not used, this value indicates the offset
3590 * in bytes from the beginning of the packet where the inner payload
3591 * starts. This value is valid for TCP, UDP, FCoE, and RoCE packets. If
3592 * truncation placement is used, this value represents the placed
3593 * (truncated) length of the packet.
3595 #define RX_PKT_V2_CMPL_PAYLOAD_OFFSET_MASK UINT32_C(0x1ff)
3596 #define RX_PKT_V2_CMPL_PAYLOAD_OFFSET_SFT 0
3597 /* This is data from the CFA as indicated by the meta_format field. */
3598 #define RX_PKT_V2_CMPL_METADATA1_MASK UINT32_C(0xf000)
3599 #define RX_PKT_V2_CMPL_METADATA1_SFT 12
3600 /* When meta_format != 0, this value is the VLAN TPID_SEL. */
3601 #define RX_PKT_V2_CMPL_METADATA1_TPID_SEL_MASK UINT32_C(0x7000)
3602 #define RX_PKT_V2_CMPL_METADATA1_TPID_SEL_SFT 12
3604 #define RX_PKT_V2_CMPL_METADATA1_TPID_SEL_TPID88A8 \
3605 (UINT32_C(0x0) << 12)
3607 #define RX_PKT_V2_CMPL_METADATA1_TPID_SEL_TPID8100 \
3608 (UINT32_C(0x1) << 12)
3610 #define RX_PKT_V2_CMPL_METADATA1_TPID_SEL_TPID9100 \
3611 (UINT32_C(0x2) << 12)
3613 #define RX_PKT_V2_CMPL_METADATA1_TPID_SEL_TPID9200 \
3614 (UINT32_C(0x3) << 12)
3616 #define RX_PKT_V2_CMPL_METADATA1_TPID_SEL_TPID9300 \
3617 (UINT32_C(0x4) << 12)
3618 /* Value programmed in CFA VLANTPID register. */
3619 #define RX_PKT_V2_CMPL_METADATA1_TPID_SEL_TPIDCFG \
3620 (UINT32_C(0x5) << 12)
3621 #define RX_PKT_V2_CMPL_METADATA1_TPID_SEL_LAST \
3622 RX_PKT_V2_CMPL_METADATA1_TPID_SEL_TPIDCFG
3623 /* When meta_format != 0, this value is the VLAN valid. */
3624 #define RX_PKT_V2_CMPL_METADATA1_VALID UINT32_C(0x8000)
3626 * This value is the RSS hash value calculated for the packet
3627 * based on the mode bits and key value in the VNIC. When vee_cmpl_mode
3628 * is set in VNIC context, this is the lower 32b of the host address
3629 * from the first BD used to place the packet.
3634 /* Last 16 bytes of RX Packet V2 Completion Record */
3635 /* rx_pkt_v2_cmpl_hi (size:128b/16B) */
3636 struct rx_pkt_v2_cmpl_hi {
3639 * When this bit is '0', the cs_ok field has the following definition:-
3640 * ip_cs_ok[2:0] = The number of header groups with a valid IP checksum
3641 * in the delivered packet, counted from the outer-most header group to
3642 * the inner-most header group, stopping at the first error. -
3643 * l4_cs_ok[5:3] = The number of header groups with a valid L4 checksum
3644 * in the delivered packet, counted from the outer-most header group to
3645 * the inner-most header group, stopping at the first error. When this
3646 * bit is '1', the cs_ok field has the following definition: -
3647 * hdr_cnt[2:0] = The number of header groups that were parsed by the
3648 * chip and passed in the delivered packet. - ip_cs_all_ok[3] =This bit
3649 * will be '1' if all the parsed header groups with an IP checksum are
3650 * valid. - l4_cs_all_ok[4] = This bit will be '1' if all the parsed
3651 * header groups with an L4 checksum are valid.
3653 #define RX_PKT_V2_CMPL_HI_FLAGS2_CS_ALL_OK_MODE \
3655 /* This value indicates what format the metadata field is. */
3656 #define RX_PKT_V2_CMPL_HI_FLAGS2_META_FORMAT_MASK \
3658 #define RX_PKT_V2_CMPL_HI_FLAGS2_META_FORMAT_SFT 4
3659 /* There is no metadata information. Values are zero. */
3660 #define RX_PKT_V2_CMPL_HI_FLAGS2_META_FORMAT_NONE \
3661 (UINT32_C(0x0) << 4)
3663 * The {metadata1, metadata0} fields contain the vtag
3664 * information: - vtag[19:0] = {valid, tpid_sel[2:0], pri[2:0],
3665 * de, vid[11:0]} The metadata2 field contains the table scope
3666 * and action record pointer. - metadata2[25:0] contains the
3667 * action record pointer. - metadata2[31:26] contains the table
3670 #define RX_PKT_V2_CMPL_HI_FLAGS2_META_FORMAT_ACT_REC_PTR \
3671 (UINT32_C(0x1) << 4)
3673 * The {metadata1, metadata0} fields contain the vtag
3675 * - vtag[19:0] = {valid, tpid_sel[2:0], pri[2:0], de, vid[11:0]}
3676 * The metadata2 field contains the Tunnel ID
3677 * value, justified to LSB. i
3678 * - VXLAN = VNI[23:0] -> VXLAN Network ID
3679 * - Geneve (NGE) = VNI[23:0] a-> Virtual Network Identifier
3680 * - NVGRE = TNI[23:0] -> Tenant Network ID
3681 * - GRE = KEY[31:0] -> key field with bit mask. zero if K=0
3682 * - IPv4 = 0 (not populated)
3683 * - IPv6 = Flow Label[19:0]
3684 * - PPPoE = sessionID[15:0]
3685 * - MPLs = Outer label[19:0]
3686 * - UPAR = Selected[31:0] with bit mask
3688 #define RX_PKT_V2_CMPL_HI_FLAGS2_META_FORMAT_TUNNEL_ID \
3689 (UINT32_C(0x2) << 4)
3691 * The {metadata1, metadata0} fields contain the vtag
3693 * - vtag[19:0] = {valid, tpid_sel[2:0], pri[2:0],de, vid[11:0]}
3694 * The metadata2 field contains the 32b metadata from the prepended
3695 * header (chdr_data).
3697 #define RX_PKT_V2_CMPL_HI_FLAGS2_META_FORMAT_CHDR_DATA \
3698 (UINT32_C(0x3) << 4)
3700 * The {metadata1, metadata0} fields contain the vtag
3702 * - vtag[19:0] = {valid, tpid_sel[2:0], pri[2:0], de, vid[11:0]}
3703 * The metadata2 field contains the outer_l3_offset,
3704 * inner_l2_offset, inner_l3_offset, and inner_l4_size.
3705 * - metadata2[8:0] contains the outer_l3_offset.
3706 * - metadata2[17:9] contains the inner_l2_offset.
3707 * - metadata2[26:18] contains the inner_l3_offset.
3708 * - metadata2[31:27] contains the inner_l4_size.
3710 #define RX_PKT_V2_CMPL_HI_FLAGS2_META_FORMAT_HDR_OFFSET \
3711 (UINT32_C(0x4) << 4)
3712 #define RX_PKT_V2_CMPL_HI_FLAGS2_META_FORMAT_LAST \
3713 RX_PKT_V2_CMPL_HI_FLAGS2_META_FORMAT_HDR_OFFSET
3715 * This field indicates the IP type for the inner-most IP header.
3716 * A value of '0' indicates IPv4. A value of '1' indicates IPv6.
3717 * This value is only valid if itype indicates a packet
3718 * with an IP header.
3720 #define RX_PKT_V2_CMPL_HI_FLAGS2_IP_TYPE \
3723 * This indicates that the complete 1's complement checksum was
3724 * calculated for the packet.
3726 #define RX_PKT_V2_CMPL_HI_FLAGS2_COMPLETE_CHECKSUM_CALC \
3729 * This field indicates the status of IP and L4 CS calculations done
3730 * by the chip. The format of this field is indicated by the
3731 * cs_all_ok_mode bit.
3733 #define RX_PKT_V2_CMPL_HI_FLAGS2_CS_OK_MASK \
3735 #define RX_PKT_V2_CMPL_HI_FLAGS2_CS_OK_SFT 10
3737 * This value is the complete 1's complement checksum calculated from
3738 * the start of the outer L3 header to the end of the packet (not
3739 * including the ethernet crc). It is valid when the
3740 * 'complete_checksum_calc' flag is set.
3742 #define RX_PKT_V2_CMPL_HI_FLAGS2_COMPLETE_CHECKSUM_MASK \
3743 UINT32_C(0xffff0000)
3744 #define RX_PKT_V2_CMPL_HI_FLAGS2_COMPLETE_CHECKSUM_SFT 16
3746 * This is data from the CFA block as indicated by the meta_format
3748 * - meta_format 0 - none - metadata2 = 0 - not valid/not stripped
3749 * - meta_format 1 - act_rec_ptr - metadata2 = {table_scope[5:0],
3750 * act_rec_ptr[25:0]}
3751 * - meta_format 2 - tunnel_id - metadata2 = tunnel_id[31:0]
3752 * - meta_format 3 - chdr_data - metadata2 = updated_chdr_data[31:0]
3753 * - meta_format 4 - hdr_offsets - metadata2 = hdr_offsets[31:0]
3754 * When vee_cmpl_mode is set in VNIC context, this is the upper 32b
3755 * of the host address from the first BD used to place the packet.
3760 * This value is written by the NIC such that it will be different
3761 * for each pass through the completion queue. The even passes
3762 * will write 1. The odd passes will write 0.
3764 #define RX_PKT_V2_CMPL_HI_V2 \
3766 #define RX_PKT_V2_CMPL_HI_ERRORS_MASK \
3768 #define RX_PKT_V2_CMPL_HI_ERRORS_SFT 1
3770 * This error indicates that there was some sort of problem with
3771 * the BDs for the packet that was found after part of the
3772 * packet was already placed. The packet should be treated as
3775 #define RX_PKT_V2_CMPL_HI_ERRORS_BUFFER_ERROR_MASK \
3777 #define RX_PKT_V2_CMPL_HI_ERRORS_BUFFER_ERROR_SFT 1
3778 /* No buffer error */
3779 #define RX_PKT_V2_CMPL_HI_ERRORS_BUFFER_ERROR_NO_BUFFER \
3780 (UINT32_C(0x0) << 1)
3782 * Did Not Fit: Packet did not fit into packet buffer provided.
3783 * For regular placement, this means the packet did not fit in
3784 * the buffer provided. For HDS and jumbo placement, this means
3785 * that the packet could not be placed into 8 physical buffers
3786 * (if fixed-size buffers are used), or that the packet could
3787 * not be placed in the number of physical buffers configured
3788 * for the VNIC (if variable-size buffers are used)
3790 #define RX_PKT_V2_CMPL_HI_ERRORS_BUFFER_ERROR_DID_NOT_FIT \
3791 (UINT32_C(0x1) << 1)
3793 * Not On Chip: All BDs needed for the packet were not on-chip
3794 * when the packet arrived. For regular placement, this error is
3795 * not valid. For HDS and jumbo placement, this means that not
3796 * enough agg BDs were posted to place the packet.
3798 #define RX_PKT_V2_CMPL_HI_ERRORS_BUFFER_ERROR_NOT_ON_CHIP \
3799 (UINT32_C(0x2) << 1)
3802 * BDs were not formatted correctly.
3804 #define RX_PKT_V2_CMPL_HI_ERRORS_BUFFER_ERROR_BAD_FORMAT \
3805 (UINT32_C(0x3) << 1)
3808 * There was a bad_format error on the previous operation
3810 #define RX_PKT_V2_CMPL_HI_ERRORS_BUFFER_ERROR_FLUSH \
3811 (UINT32_C(0x5) << 1)
3812 #define RX_PKT_V2_CMPL_HI_ERRORS_BUFFER_ERROR_LAST \
3813 RX_PKT_V2_CMPL_HI_ERRORS_BUFFER_ERROR_FLUSH
3815 * This indicates that there was an error in the outer tunnel
3816 * portion of the packet when this field is non-zero.
3818 #define RX_PKT_V2_CMPL_HI_ERRORS_OT_PKT_ERROR_MASK \
3820 #define RX_PKT_V2_CMPL_HI_ERRORS_OT_PKT_ERROR_SFT 4
3822 * No additional error occurred on the outer tunnel portion
3823 * of the packet or the packet does not have a outer tunnel.
3825 #define RX_PKT_V2_CMPL_HI_ERRORS_OT_PKT_ERROR_NO_ERROR \
3826 (UINT32_C(0x0) << 4)
3828 * Indicates that IP header version does not match expectation
3829 * from L2 Ethertype for IPv4 and IPv6 in the outer tunnel header.
3831 #define RX_PKT_V2_CMPL_HI_ERRORS_OT_PKT_ERROR_OT_L3_BAD_VERSION \
3832 (UINT32_C(0x1) << 4)
3834 * Indicates that header length is out of range in the outer
3835 * tunnel header. Valid for IPv4.
3837 #define RX_PKT_V2_CMPL_HI_ERRORS_OT_PKT_ERROR_OT_L3_BAD_HDR_LEN \
3838 (UINT32_C(0x2) << 4)
3840 * Indicates that physical packet is shorter than that claimed
3841 * by the outer tunnel l3 header length. Valid for IPv4, or
3842 * IPv6 outer tunnel packets.
3844 #define RX_PKT_V2_CMPL_HI_ERRORS_OT_PKT_ERROR_OT_IP_TOTAL_ERROR \
3845 (UINT32_C(0x3) << 4)
3847 * Indicates that the physical packet is shorter than that
3848 * claimed by the outer tunnel UDP header length for a outer
3849 * tunnel UDP packet that is not fragmented.
3851 #define RX_PKT_V2_CMPL_HI_ERRORS_OT_PKT_ERROR_OT_UDP_TOTAL_ERROR \
3852 (UINT32_C(0x4) << 4)
3854 * Indicates that the IPv4 TTL or IPv6 hop limit check have
3855 * failed (e.g. TTL = 0) in the outer tunnel header. Valid for
3858 #define RX_PKT_V2_CMPL_HI_ERRORS_OT_PKT_ERROR_OT_L3_BAD_TTL \
3859 (UINT32_C(0x5) << 4)
3861 * Indicates that the IP checksum failed its check in the outer
3864 #define RX_PKT_V2_CMPL_HI_ERRORS_OT_PKT_ERROR_OT_IP_CS_ERROR \
3865 (UINT32_C(0x6) << 4)
3867 * Indicates that the L4 checksum failed its check in the outer
3870 #define RX_PKT_V2_CMPL_HI_ERRORS_OT_PKT_ERROR_OT_L4_CS_ERROR \
3871 (UINT32_C(0x7) << 4)
3872 #define RX_PKT_V2_CMPL_HI_ERRORS_OT_PKT_ERROR_LAST \
3873 RX_PKT_V2_CMPL_HI_ERRORS_OT_PKT_ERROR_OT_L4_CS_ERROR
3875 * This indicates that there was a CRC error on either an FCoE
3876 * or RoCE packet. The itype indicates the packet type.
3878 #define RX_PKT_V2_CMPL_HI_ERRORS_CRC_ERROR \
3881 * This indicates that there was an error in the tunnel portion
3882 * of the packet when this field is non-zero.
3884 #define RX_PKT_V2_CMPL_HI_ERRORS_T_PKT_ERROR_MASK \
3886 #define RX_PKT_V2_CMPL_HI_ERRORS_T_PKT_ERROR_SFT 9
3888 * No additional error occurred on the tunnel portion
3889 * of the packet or the packet does not have a tunnel.
3891 #define RX_PKT_V2_CMPL_HI_ERRORS_T_PKT_ERROR_NO_ERROR \
3892 (UINT32_C(0x0) << 9)
3894 * Indicates that IP header version does not match expectation
3895 * from L2 Ethertype for IPv4 and IPv6 in the tunnel header.
3897 #define RX_PKT_V2_CMPL_HI_ERRORS_T_PKT_ERROR_T_L3_BAD_VERSION \
3898 (UINT32_C(0x1) << 9)
3900 * Indicates that header length is out of range in the tunnel
3901 * header. Valid for IPv4.
3903 #define RX_PKT_V2_CMPL_HI_ERRORS_T_PKT_ERROR_T_L3_BAD_HDR_LEN \
3904 (UINT32_C(0x2) << 9)
3906 * Indicates that physical packet is shorter than that claimed
3907 * by the tunnel l3 header length. Valid for IPv4, or IPv6 tunnel
3910 #define RX_PKT_V2_CMPL_HI_ERRORS_T_PKT_ERROR_T_IP_TOTAL_ERROR \
3911 (UINT32_C(0x3) << 9)
3913 * Indicates that the physical packet is shorter than that claimed
3914 * by the tunnel UDP header length for a tunnel UDP packet that is
3917 #define RX_PKT_V2_CMPL_HI_ERRORS_T_PKT_ERROR_T_UDP_TOTAL_ERROR \
3918 (UINT32_C(0x4) << 9)
3920 * Indicates that the IPv4 TTL or IPv6 hop limit check have failed
3921 * (e.g. TTL = 0) in the tunnel header. Valid for IPv4, and IPv6.
3923 #define RX_PKT_V2_CMPL_HI_ERRORS_T_PKT_ERROR_T_L3_BAD_TTL \
3924 (UINT32_C(0x5) << 9)
3926 * Indicates that the IP checksum failed its check in the tunnel
3929 #define RX_PKT_V2_CMPL_HI_ERRORS_T_PKT_ERROR_T_IP_CS_ERROR \
3930 (UINT32_C(0x6) << 9)
3932 * Indicates that the L4 checksum failed its check in the tunnel
3935 #define RX_PKT_V2_CMPL_HI_ERRORS_T_PKT_ERROR_T_L4_CS_ERROR \
3936 (UINT32_C(0x7) << 9)
3937 #define RX_PKT_V2_CMPL_HI_ERRORS_T_PKT_ERROR_LAST \
3938 RX_PKT_V2_CMPL_HI_ERRORS_T_PKT_ERROR_T_L4_CS_ERROR
3940 * This indicates that there was an error in the inner
3941 * portion of the packet when this
3942 * field is non-zero.
3944 #define RX_PKT_V2_CMPL_HI_ERRORS_PKT_ERROR_MASK \
3946 #define RX_PKT_V2_CMPL_HI_ERRORS_PKT_ERROR_SFT 12
3948 * No additional error occurred on the tunnel portion
3949 * or the packet of the packet does not have a tunnel.
3951 #define RX_PKT_V2_CMPL_HI_ERRORS_PKT_ERROR_NO_ERROR \
3952 (UINT32_C(0x0) << 12)
3954 * Indicates that IP header version does not match
3955 * expectation from L2 Ethertype for IPv4 and IPv6 or that
3956 * option other than VFT was parsed on
3959 #define RX_PKT_V2_CMPL_HI_ERRORS_PKT_ERROR_L3_BAD_VERSION \
3960 (UINT32_C(0x1) << 12)
3962 * indicates that header length is out of range. Valid for
3965 #define RX_PKT_V2_CMPL_HI_ERRORS_PKT_ERROR_L3_BAD_HDR_LEN \
3966 (UINT32_C(0x2) << 12)
3968 * indicates that the IPv4 TTL or IPv6 hop limit check
3969 * have failed (e.g. TTL = 0). Valid for IPv4, and IPv6
3971 #define RX_PKT_V2_CMPL_HI_ERRORS_PKT_ERROR_L3_BAD_TTL \
3972 (UINT32_C(0x3) << 12)
3974 * Indicates that physical packet is shorter than that
3975 * claimed by the l3 header length. Valid for IPv4,
3976 * IPv6 packet or RoCE packets.
3978 #define RX_PKT_V2_CMPL_HI_ERRORS_PKT_ERROR_IP_TOTAL_ERROR \
3979 (UINT32_C(0x4) << 12)
3981 * Indicates that the physical packet is shorter than that
3982 * claimed by the UDP header length for a UDP packet that is
3985 #define RX_PKT_V2_CMPL_HI_ERRORS_PKT_ERROR_UDP_TOTAL_ERROR \
3986 (UINT32_C(0x5) << 12)
3988 * Indicates that TCP header length > IP payload. Valid for
3991 #define RX_PKT_V2_CMPL_HI_ERRORS_PKT_ERROR_L4_BAD_HDR_LEN \
3992 (UINT32_C(0x6) << 12)
3993 /* Indicates that TCP header length < 5. Valid for TCP. */
3994 #define RX_PKT_V2_CMPL_HI_ERRORS_PKT_ERROR_L4_BAD_HDR_LEN_TOO_SMALL \
3995 (UINT32_C(0x7) << 12)
3997 * Indicates that TCP option headers result in a TCP header
3998 * size that does not match data offset in TCP header. Valid
4001 #define RX_PKT_V2_CMPL_HI_ERRORS_PKT_ERROR_L4_BAD_OPT_LEN \
4002 (UINT32_C(0x8) << 12)
4004 * Indicates that the IP checksum failed its check in the
4007 #define RX_PKT_V2_CMPL_HI_ERRORS_PKT_ERROR_IP_CS_ERROR \
4008 (UINT32_C(0x9) << 12)
4010 * Indicates that the L4 checksum failed its check in the
4013 #define RX_PKT_V2_CMPL_HI_ERRORS_PKT_ERROR_L4_CS_ERROR \
4014 (UINT32_C(0xa) << 12)
4015 #define RX_PKT_V2_CMPL_HI_ERRORS_PKT_ERROR_LAST \
4016 RX_PKT_V2_CMPL_HI_ERRORS_PKT_ERROR_L4_CS_ERROR
4018 * This is data from the CFA block as indicated by the meta_format
4022 /* When meta_format=1, this value is the VLAN VID. */
4023 #define RX_PKT_V2_CMPL_HI_METADATA0_VID_MASK UINT32_C(0xfff)
4024 #define RX_PKT_V2_CMPL_HI_METADATA0_VID_SFT 0
4025 /* When meta_format=1, this value is the VLAN DE. */
4026 #define RX_PKT_V2_CMPL_HI_METADATA0_DE UINT32_C(0x1000)
4027 /* When meta_format=1, this value is the VLAN PRI. */
4028 #define RX_PKT_V2_CMPL_HI_METADATA0_PRI_MASK UINT32_C(0xe000)
4029 #define RX_PKT_V2_CMPL_HI_METADATA0_PRI_SFT 13
4031 * The timestamp field contains the 32b timestamp for the packet from
4038 * This TPA completion structure is used on devices where the
4039 * `hwrm_vnic_qcaps.max_aggs_supported` value is 0.
4041 /* rx_tpa_start_cmpl (size:128b/16B) */
4042 struct rx_tpa_start_cmpl {
4043 uint16_t flags_type;
4045 * This field indicates the exact type of the completion.
4046 * By convention, the LSB identifies the length of the
4047 * record in 16B units. Even values indicate 16B
4048 * records. Odd values indicate 32B
4051 #define RX_TPA_START_CMPL_TYPE_MASK UINT32_C(0x3f)
4052 #define RX_TPA_START_CMPL_TYPE_SFT 0
4054 * RX L2 TPA Start Completion:
4055 * Completion at the beginning of a TPA operation.
4058 #define RX_TPA_START_CMPL_TYPE_RX_TPA_START UINT32_C(0x13)
4059 #define RX_TPA_START_CMPL_TYPE_LAST \
4060 RX_TPA_START_CMPL_TYPE_RX_TPA_START
4061 #define RX_TPA_START_CMPL_FLAGS_MASK UINT32_C(0xffc0)
4062 #define RX_TPA_START_CMPL_FLAGS_SFT 6
4063 /* This bit will always be '0' for TPA start completions. */
4064 #define RX_TPA_START_CMPL_FLAGS_ERROR UINT32_C(0x40)
4065 /* This field indicates how the packet was placed in the buffer. */
4066 #define RX_TPA_START_CMPL_FLAGS_PLACEMENT_MASK UINT32_C(0x380)
4067 #define RX_TPA_START_CMPL_FLAGS_PLACEMENT_SFT 7
4070 * TPA Packet was placed using jumbo algorithm. This means
4071 * that the first buffer will be filled with data before
4072 * moving to aggregation buffers. Each aggregation buffer
4073 * will be filled before moving to the next aggregation
4076 #define RX_TPA_START_CMPL_FLAGS_PLACEMENT_JUMBO \
4077 (UINT32_C(0x1) << 7)
4079 * Header/Data Separation:
4080 * Packet was placed using Header/Data separation algorithm.
4081 * The separation location is indicated by the itype field.
4083 #define RX_TPA_START_CMPL_FLAGS_PLACEMENT_HDS \
4084 (UINT32_C(0x2) << 7)
4087 * Packet will be placed using GRO/Jumbo where the first
4088 * packet is filled with data. Subsequent packets will be
4089 * placed such that any one packet does not span two
4090 * aggregation buffers unless it starts at the beginning of
4091 * an aggregation buffer.
4093 #define RX_TPA_START_CMPL_FLAGS_PLACEMENT_GRO_JUMBO \
4094 (UINT32_C(0x5) << 7)
4096 * GRO/Header-Data Separation:
4097 * Packet will be placed using GRO/HDS where the header
4098 * is in the first packet.
4099 * Payload of each packet will be
4100 * placed such that any one packet does not span two
4101 * aggregation buffers unless it starts at the beginning of
4102 * an aggregation buffer.
4104 #define RX_TPA_START_CMPL_FLAGS_PLACEMENT_GRO_HDS \
4105 (UINT32_C(0x6) << 7)
4106 #define RX_TPA_START_CMPL_FLAGS_PLACEMENT_LAST \
4107 RX_TPA_START_CMPL_FLAGS_PLACEMENT_GRO_HDS
4108 /* This bit is '1' if the RSS field in this completion is valid. */
4109 #define RX_TPA_START_CMPL_FLAGS_RSS_VALID UINT32_C(0x400)
4111 #define RX_TPA_START_CMPL_FLAGS_UNUSED UINT32_C(0x800)
4113 * This value indicates what the inner packet determined for the
4116 #define RX_TPA_START_CMPL_FLAGS_ITYPE_MASK UINT32_C(0xf000)
4117 #define RX_TPA_START_CMPL_FLAGS_ITYPE_SFT 12
4120 * Indicates that the packet was IP and TCP.
4122 #define RX_TPA_START_CMPL_FLAGS_ITYPE_TCP \
4123 (UINT32_C(0x2) << 12)
4124 #define RX_TPA_START_CMPL_FLAGS_ITYPE_LAST \
4125 RX_TPA_START_CMPL_FLAGS_ITYPE_TCP
4127 * This value indicates the amount of packet data written to the
4128 * buffer the opaque field in this completion corresponds to.
4132 * This is a copy of the opaque field from the RX BD this completion
4137 * This value is written by the NIC such that it will be different
4138 * for each pass through the completion queue. The even passes
4139 * will write 1. The odd passes will write 0.
4143 * This value is written by the NIC such that it will be different
4144 * for each pass through the completion queue. The even passes
4145 * will write 1. The odd passes will write 0.
4147 #define RX_TPA_START_CMPL_V1 UINT32_C(0x1)
4148 #define RX_TPA_START_CMPL_LAST RX_TPA_START_CMPL_V1
4150 * This is the RSS hash type for the packet. The value is packed
4151 * {tuple_extrac_op[1:0],rss_profile_id[4:0],tuple_extrac_op[2]}.
4153 * The value of tuple_extrac_op provides the information about
4154 * what fields the hash was computed on.
4155 * * 0: The RSS hash was computed over source IP address,
4156 * destination IP address, source port, and destination port of inner
4157 * IP and TCP or UDP headers. Note: For non-tunneled packets,
4158 * the packet headers are considered inner packet headers for the RSS
4159 * hash computation purpose.
4160 * * 1: The RSS hash was computed over source IP address and destination
4161 * IP address of inner IP header. Note: For non-tunneled packets,
4162 * the packet headers are considered inner packet headers for the RSS
4163 * hash computation purpose.
4164 * * 2: The RSS hash was computed over source IP address,
4165 * destination IP address, source port, and destination port of
4166 * IP and TCP or UDP headers of outer tunnel headers.
4167 * Note: For non-tunneled packets, this value is not applicable.
4168 * * 3: The RSS hash was computed over source IP address and
4169 * destination IP address of IP header of outer tunnel headers.
4170 * Note: For non-tunneled packets, this value is not applicable.
4172 * Note that 4-tuples values listed above are applicable
4173 * for layer 4 protocols supported and enabled for RSS in the hardware,
4174 * HWRM firmware, and drivers. For example, if RSS hash is supported and
4175 * enabled for TCP traffic only, then the values of tuple_extract_op
4176 * corresponding to 4-tuples are only valid for TCP traffic.
4178 uint8_t rss_hash_type;
4180 * This is the aggregation ID that the completion is associated
4181 * with. Use this number to correlate the TPA start completion
4182 * with the TPA end completion.
4185 /* unused2 is 9 b */
4186 #define RX_TPA_START_CMPL_UNUSED2_MASK UINT32_C(0x1ff)
4187 #define RX_TPA_START_CMPL_UNUSED2_SFT 0
4189 * This is the aggregation ID that the completion is associated
4190 * with. Use this number to correlate the TPA start completion
4191 * with the TPA end completion.
4193 #define RX_TPA_START_CMPL_AGG_ID_MASK UINT32_C(0xfe00)
4194 #define RX_TPA_START_CMPL_AGG_ID_SFT 9
4196 * This value is the RSS hash value calculated for the packet
4197 * based on the mode bits and key value in the VNIC.
4203 * Last 16 bytes of rx_tpa_start_cmpl.
4205 * This TPA completion structure is used on devices where the
4206 * `hwrm_vnic_qcaps.max_aggs_supported` value is 0.
4208 /* rx_tpa_start_cmpl_hi (size:128b/16B) */
4209 struct rx_tpa_start_cmpl_hi {
4212 * This indicates that the ip checksum was calculated for the
4213 * inner packet and that the sum passed for all segments
4214 * included in the aggregation.
4216 #define RX_TPA_START_CMPL_FLAGS2_IP_CS_CALC UINT32_C(0x1)
4218 * This indicates that the TCP, UDP or ICMP checksum was
4219 * calculated for the inner packet and that the sum passed
4220 * for all segments included in the aggregation.
4222 #define RX_TPA_START_CMPL_FLAGS2_L4_CS_CALC UINT32_C(0x2)
4224 * This indicates that the ip checksum was calculated for the
4225 * tunnel header and that the sum passed for all segments
4226 * included in the aggregation.
4228 #define RX_TPA_START_CMPL_FLAGS2_T_IP_CS_CALC UINT32_C(0x4)
4230 * This indicates that the UDP checksum was
4231 * calculated for the tunnel packet and that the sum passed for
4232 * all segments included in the aggregation.
4234 #define RX_TPA_START_CMPL_FLAGS2_T_L4_CS_CALC UINT32_C(0x8)
4235 /* This value indicates what format the metadata field is. */
4236 #define RX_TPA_START_CMPL_FLAGS2_META_FORMAT_MASK UINT32_C(0xf0)
4237 #define RX_TPA_START_CMPL_FLAGS2_META_FORMAT_SFT 4
4238 /* No metadata information. Value is zero. */
4239 #define RX_TPA_START_CMPL_FLAGS2_META_FORMAT_NONE \
4240 (UINT32_C(0x0) << 4)
4242 * The metadata field contains the VLAN tag and TPID value.
4243 * - metadata[11:0] contains the vlan VID value.
4244 * - metadata[12] contains the vlan DE value.
4245 * - metadata[15:13] contains the vlan PRI value.
4246 * - metadata[31:16] contains the vlan TPID value.
4248 #define RX_TPA_START_CMPL_FLAGS2_META_FORMAT_VLAN \
4249 (UINT32_C(0x1) << 4)
4250 #define RX_TPA_START_CMPL_FLAGS2_META_FORMAT_LAST \
4251 RX_TPA_START_CMPL_FLAGS2_META_FORMAT_VLAN
4253 * This field indicates the IP type for the inner-most IP header.
4254 * A value of '0' indicates IPv4. A value of '1' indicates IPv6.
4256 #define RX_TPA_START_CMPL_FLAGS2_IP_TYPE UINT32_C(0x100)
4258 * This is data from the CFA block as indicated by the meta_format
4262 /* When meta_format=1, this value is the VLAN VID. */
4263 #define RX_TPA_START_CMPL_METADATA_VID_MASK UINT32_C(0xfff)
4264 #define RX_TPA_START_CMPL_METADATA_VID_SFT 0
4265 /* When meta_format=1, this value is the VLAN DE. */
4266 #define RX_TPA_START_CMPL_METADATA_DE UINT32_C(0x1000)
4267 /* When meta_format=1, this value is the VLAN PRI. */
4268 #define RX_TPA_START_CMPL_METADATA_PRI_MASK UINT32_C(0xe000)
4269 #define RX_TPA_START_CMPL_METADATA_PRI_SFT 13
4270 /* When meta_format=1, this value is the VLAN TPID. */
4271 #define RX_TPA_START_CMPL_METADATA_TPID_MASK UINT32_C(0xffff0000)
4272 #define RX_TPA_START_CMPL_METADATA_TPID_SFT 16
4275 * This value is written by the NIC such that it will be different
4276 * for each pass through the completion queue. The even passes
4277 * will write 1. The odd passes will write 0.
4279 #define RX_TPA_START_CMPL_V2 UINT32_C(0x1)
4281 * This field identifies the CFA action rule that was used for this
4286 * This is the size in bytes of the inner most L4 header.
4287 * This can be subtracted from the payload_offset to determine
4288 * the start of the inner most L4 header.
4290 uint32_t inner_l4_size_inner_l3_offset_inner_l2_offset_outer_l3_offset;
4292 * This is the offset from the beginning of the packet in bytes for
4293 * the outer L3 header. If there is no outer L3 header, then this
4296 #define RX_TPA_START_CMPL_OUTER_L3_OFFSET_MASK UINT32_C(0x1ff)
4297 #define RX_TPA_START_CMPL_OUTER_L3_OFFSET_SFT 0
4299 * This is the offset from the beginning of the packet in bytes for
4300 * the inner most L2 header.
4302 #define RX_TPA_START_CMPL_INNER_L2_OFFSET_MASK UINT32_C(0x3fe00)
4303 #define RX_TPA_START_CMPL_INNER_L2_OFFSET_SFT 9
4305 * This is the offset from the beginning of the packet in bytes for
4306 * the inner most L3 header.
4308 #define RX_TPA_START_CMPL_INNER_L3_OFFSET_MASK UINT32_C(0x7fc0000)
4309 #define RX_TPA_START_CMPL_INNER_L3_OFFSET_SFT 18
4311 * This is the size in bytes of the inner most L4 header.
4312 * This can be subtracted from the payload_offset to determine
4313 * the start of the inner most L4 header.
4315 #define RX_TPA_START_CMPL_INNER_L4_SIZE_MASK UINT32_C(0xf8000000)
4316 #define RX_TPA_START_CMPL_INNER_L4_SIZE_SFT 27
4320 * This TPA completion structure is used on devices where the
4321 * `hwrm_vnic_qcaps.max_aggs_supported` value is 0.
4322 * RX L2 TPA Start V2 Completion Record (32 bytes split to 2 16-byte
4325 /* rx_tpa_start_v2_cmpl (size:128b/16B) */
4326 struct rx_tpa_start_v2_cmpl {
4327 uint16_t flags_type;
4329 * This field indicates the exact type of the completion.
4330 * By convention, the LSB identifies the length of the
4331 * record in 16B units. Even values indicate 16B
4332 * records. Odd values indicate 32B
4335 #define RX_TPA_START_V2_CMPL_TYPE_MASK \
4337 #define RX_TPA_START_V2_CMPL_TYPE_SFT 0
4339 * RX L2 TPA Start V2 Completion:
4340 * Completion at the beginning of a TPA operation.
4342 * This is the new version of the RX_TPA_START completion used
4343 * in SR2 and later chips.
4345 #define RX_TPA_START_V2_CMPL_TYPE_RX_TPA_START_V2 \
4347 #define RX_TPA_START_V2_CMPL_TYPE_LAST \
4348 RX_TPA_START_V2_CMPL_TYPE_RX_TPA_START_V2
4349 #define RX_TPA_START_V2_CMPL_FLAGS_MASK \
4351 #define RX_TPA_START_V2_CMPL_FLAGS_SFT 6
4353 * When this bit is '1', it indicates a packet that has an error
4354 * of some type. Type of error is indicated in error_flags.
4356 #define RX_TPA_START_V2_CMPL_FLAGS_ERROR \
4358 /* This field indicates how the packet was placed in the buffer. */
4359 #define RX_TPA_START_V2_CMPL_FLAGS_PLACEMENT_MASK \
4361 #define RX_TPA_START_V2_CMPL_FLAGS_PLACEMENT_SFT 7
4364 * TPA Packet was placed using jumbo algorithm. This means
4365 * that the first buffer will be filled with data before
4366 * moving to aggregation buffers. Each aggregation buffer
4367 * will be filled before moving to the next aggregation
4370 #define RX_TPA_START_V2_CMPL_FLAGS_PLACEMENT_JUMBO \
4371 (UINT32_C(0x1) << 7)
4373 * Header/Data Separation:
4374 * Packet was placed using Header/Data separation algorithm.
4375 * The separation location is indicated by the itype field.
4377 #define RX_TPA_START_V2_CMPL_FLAGS_PLACEMENT_HDS \
4378 (UINT32_C(0x2) << 7)
4381 * Packet will be placed using In-Order Completion/Jumbo where
4382 * the first packet of the aggregation is placed using Jumbo
4383 * Placement. Subsequent packets will be placed such that each
4384 * packet starts at the beginning of an aggregation buffer.
4386 #define RX_TPA_START_V2_CMPL_FLAGS_PLACEMENT_IOC_JUMBO \
4387 (UINT32_C(0x4) << 7)
4390 * Packet will be placed using GRO/Jumbo where the first
4391 * packet is filled with data. Subsequent packets will be
4392 * placed such that any one packet does not span two
4393 * aggregation buffers unless it starts at the beginning of
4394 * an aggregation buffer.
4396 #define RX_TPA_START_V2_CMPL_FLAGS_PLACEMENT_GRO_JUMBO \
4397 (UINT32_C(0x5) << 7)
4399 * GRO/Header-Data Separation:
4400 * Packet will be placed using GRO/HDS where the header
4401 * is in the first packet.
4402 * Payload of each packet will be
4403 * placed such that any one packet does not span two
4404 * aggregation buffers unless it starts at the beginning of
4405 * an aggregation buffer.
4407 #define RX_TPA_START_V2_CMPL_FLAGS_PLACEMENT_GRO_HDS \
4408 (UINT32_C(0x6) << 7)
4410 * IOC/Header-Data Separation:
4411 * Packet will be placed using In-Order Completion/HDS where
4412 * the header is in the first packet buffer. Payload of each
4413 * packet will be placed such that each packet starts at the
4414 * beginning of an aggregation buffer.
4416 #define RX_TPA_START_V2_CMPL_FLAGS_PLACEMENT_IOC_HDS \
4417 (UINT32_C(0x7) << 7)
4418 #define RX_TPA_START_V2_CMPL_FLAGS_PLACEMENT_LAST \
4419 RX_TPA_START_V2_CMPL_FLAGS_PLACEMENT_IOC_HDS
4420 /* This bit is '1' if the RSS field in this completion is valid. */
4421 #define RX_TPA_START_V2_CMPL_FLAGS_RSS_VALID \
4424 * This bit is '1' if metadata has been added to the end of the
4425 * packet in host memory. Metadata starts at the first 32B boundary
4426 * after the end of the packet for regular and jumbo placement. It
4427 * starts at the first 32B boundary after the end of the header for
4428 * HDS placement. The length of the metadata is indicated in the
4431 #define RX_TPA_START_V2_CMPL_FLAGS_PKT_METADATA_PRESENT \
4434 * This value indicates what the inner packet determined for the
4437 #define RX_TPA_START_V2_CMPL_FLAGS_ITYPE_MASK \
4439 #define RX_TPA_START_V2_CMPL_FLAGS_ITYPE_SFT 12
4442 * Indicates that the packet was IP and TCP.
4444 #define RX_TPA_START_V2_CMPL_FLAGS_ITYPE_TCP \
4445 (UINT32_C(0x2) << 12)
4446 #define RX_TPA_START_V2_CMPL_FLAGS_ITYPE_LAST \
4447 RX_TPA_START_V2_CMPL_FLAGS_ITYPE_TCP
4449 * This value indicates the amount of packet data written to the
4450 * buffer the opaque field in this completion corresponds to.
4454 * This is a copy of the opaque field from the RX BD this completion
4455 * corresponds to. If the VNIC is configured to not use an Rx BD for
4456 * the TPA Start completion, then this is a copy of the opaque field
4457 * from the first BD used to place the TPA Start packet.
4461 * This value is written by the NIC such that it will be different
4462 * for each pass through the completion queue. The even passes
4463 * will write 1. The odd passes will write 0.
4467 * This value is written by the NIC such that it will be different
4468 * for each pass through the completion queue. The even passes
4469 * will write 1. The odd passes will write 0.
4471 #define RX_TPA_START_V2_CMPL_V1 UINT32_C(0x1)
4472 #define RX_TPA_START_V2_CMPL_LAST RX_TPA_START_V2_CMPL_V1
4474 * This is the RSS hash type for the packet. The value is packed
4475 * {tuple_extrac_op[1:0],rss_profile_id[4:0],tuple_extrac_op[2]}.
4477 * The value of tuple_extrac_op provides the information about
4478 * what fields the hash was computed on.
4479 * * 0: The RSS hash was computed over source IP address,
4480 * destination IP address, source port, and destination port of inner
4481 * IP and TCP or UDP headers. Note: For non-tunneled packets,
4482 * the packet headers are considered inner packet headers for the RSS
4483 * hash computation purpose.
4484 * * 1: The RSS hash was computed over source IP address and destination
4485 * IP address of inner IP header. Note: For non-tunneled packets,
4486 * the packet headers are considered inner packet headers for the RSS
4487 * hash computation purpose.
4488 * * 2: The RSS hash was computed over source IP address,
4489 * destination IP address, source port, and destination port of
4490 * IP and TCP or UDP headers of outer tunnel headers.
4491 * Note: For non-tunneled packets, this value is not applicable.
4492 * * 3: The RSS hash was computed over source IP address and
4493 * destination IP address of IP header of outer tunnel headers.
4494 * Note: For non-tunneled packets, this value is not applicable.
4496 * Note that 4-tuples values listed above are applicable
4497 * for layer 4 protocols supported and enabled for RSS in the hardware,
4498 * HWRM firmware, and drivers. For example, if RSS hash is supported and
4499 * enabled for TCP traffic only, then the values of tuple_extract_op
4500 * corresponding to 4-tuples are only valid for TCP traffic.
4502 uint8_t rss_hash_type;
4504 * This is the aggregation ID that the completion is associated
4505 * with. Use this number to correlate the TPA start completion
4506 * with the TPA end completion.
4510 * This is the aggregation ID that the completion is associated
4511 * with. Use this number to correlate the TPA start completion
4512 * with the TPA end completion.
4514 #define RX_TPA_START_V2_CMPL_AGG_ID_MASK UINT32_C(0xfff)
4515 #define RX_TPA_START_V2_CMPL_AGG_ID_SFT 0
4516 #define RX_TPA_START_V2_CMPL_METADATA1_MASK \
4518 #define RX_TPA_START_V2_CMPL_METADATA1_SFT 12
4519 /* When meta_format != 0, this value is the VLAN TPID_SEL. */
4520 #define RX_TPA_START_V2_CMPL_METADATA1_TPID_SEL_MASK \
4522 #define RX_TPA_START_V2_CMPL_METADATA1_TPID_SEL_SFT 12
4524 #define RX_TPA_START_V2_CMPL_METADATA1_TPID_SEL_TPID88A8 \
4525 (UINT32_C(0x0) << 12)
4527 #define RX_TPA_START_V2_CMPL_METADATA1_TPID_SEL_TPID8100 \
4528 (UINT32_C(0x1) << 12)
4530 #define RX_TPA_START_V2_CMPL_METADATA1_TPID_SEL_TPID9100 \
4531 (UINT32_C(0x2) << 12)
4533 #define RX_TPA_START_V2_CMPL_METADATA1_TPID_SEL_TPID9200 \
4534 (UINT32_C(0x3) << 12)
4536 #define RX_TPA_START_V2_CMPL_METADATA1_TPID_SEL_TPID9300 \
4537 (UINT32_C(0x4) << 12)
4538 /* Value programmed in CFA VLANTPID register. */
4539 #define RX_TPA_START_V2_CMPL_METADATA1_TPID_SEL_TPIDCFG \
4540 (UINT32_C(0x5) << 12)
4541 #define RX_TPA_START_V2_CMPL_METADATA1_TPID_SEL_LAST \
4542 RX_TPA_START_V2_CMPL_METADATA1_TPID_SEL_TPIDCFG
4543 /* When meta_format != 0, this value is the VLAN valid. */
4544 #define RX_TPA_START_V2_CMPL_METADATA1_VALID \
4547 * This value is the RSS hash value calculated for the packet
4548 * based on the mode bits and key value in the VNIC.
4549 * When vee_cmpl_mode is set in VNIC context, this is the lower
4550 * 32b of the host address from the first BD used to place the packet.
4556 * Last 16 bytes of RX L2 TPA Start V2 Completion Record
4558 * This TPA completion structure is used on devices where the
4559 * `hwrm_vnic_qcaps.max_aggs_supported` value is 0.
4561 /* rx_tpa_start_v2_cmpl_hi (size:128b/16B) */
4562 struct rx_tpa_start_v2_cmpl_hi {
4564 /* This indicates that the aggregation was done using GRO rules. */
4565 #define RX_TPA_START_V2_CMPL_FLAGS2_AGG_GRO \
4568 * When this bit is '0', the cs_ok field has the following definition:-
4569 * ip_cs_ok[2:0] = The number of header groups with a valid IP checksum
4570 * in the delivered packet, counted from the outer-most header group to
4571 * the inner-most header group, stopping at the first error. -
4572 * l4_cs_ok[5:3] = The number of header groups with a valid L4 checksum
4573 * in the delivered packet, counted from the outer-most header group to
4574 * the inner-most header group, stopping at the first error. When this
4575 * bit is '1', the cs_ok field has the following definition: -
4576 * hdr_cnt[2:0] = The number of header groups that were parsed by the
4577 * chip and passed in the delivered packet. - ip_cs_all_ok[3] =This bit
4578 * will be '1' if all the parsed header groups with an IP checksum are
4579 * valid. - l4_cs_all_ok[4] = This bit will be '1' if all the parsed
4580 * header groups with an L4 checksum are valid.
4582 #define RX_TPA_START_V2_CMPL_FLAGS2_CS_ALL_OK_MODE \
4584 /* This value indicates what format the metadata field is. */
4585 #define RX_TPA_START_V2_CMPL_FLAGS2_META_FORMAT_MASK \
4587 #define RX_TPA_START_V2_CMPL_FLAGS2_META_FORMAT_SFT 4
4588 /* There is no metadata information. Values are zero. */
4589 #define RX_TPA_START_V2_CMPL_FLAGS2_META_FORMAT_NONE \
4590 (UINT32_C(0x0) << 4)
4592 * The {metadata1, metadata0} fields contain the vtag
4593 * information: - vtag[19:0] = {valid, tpid_sel[2:0], pri[2:0],
4594 * de, vid[11:0]} The metadata2 field contains the table scope
4595 * and action record pointer. - metadata2[25:0] contains the
4596 * action record pointer. - metadata2[31:26] contains the table
4599 #define RX_TPA_START_V2_CMPL_FLAGS2_META_FORMAT_ACT_REC_PTR \
4600 (UINT32_C(0x1) << 4)
4602 * The {metadata1, metadata0} fields contain the vtag
4604 * - vtag[19:0] = {valid, tpid_sel[2:0], pri[2:0], de, vid[11:0]}
4605 * The metadata2 field contains the Tunnel ID
4606 * value, justified to LSB. i
4607 * - VXLAN = VNI[23:0] -> VXLAN Network ID
4608 * - Geneve (NGE) = VNI[23:0] a-> Virtual Network Identifier
4609 * - NVGRE = TNI[23:0] -> Tenant Network ID
4610 * - GRE = KEY[31:0] -> key field with bit mask. zero if K=0
4611 * - IPv4 = 0 (not populated)
4612 * - IPv6 = Flow Label[19:0]
4613 * - PPPoE = sessionID[15:0]
4614 * - MPLs = Outer label[19:0]
4615 * - UPAR = Selected[31:0] with bit mask
4617 #define RX_TPA_START_V2_CMPL_FLAGS2_META_FORMAT_TUNNEL_ID \
4618 (UINT32_C(0x2) << 4)
4620 * The {metadata1, metadata0} fields contain the vtag
4622 * - vtag[19:0] = {valid, tpid_sel[2:0], pri[2:0],de, vid[11:0]}
4623 * The metadata2 field contains the 32b metadata from the prepended
4624 * header (chdr_data).
4626 #define RX_TPA_START_V2_CMPL_FLAGS2_META_FORMAT_CHDR_DATA \
4627 (UINT32_C(0x3) << 4)
4629 * The {metadata1, metadata0} fields contain the vtag
4631 * - vtag[19:0] = {valid, tpid_sel[2:0], pri[2:0], de, vid[11:0]}
4632 * The metadata2 field contains the outer_l3_offset,
4633 * inner_l2_offset, inner_l3_offset, and inner_l4_size.
4634 * - metadata2[8:0] contains the outer_l3_offset.
4635 * - metadata2[17:9] contains the inner_l2_offset.
4636 * - metadata2[26:18] contains the inner_l3_offset.
4637 * - metadata2[31:27] contains the inner_l4_size.
4639 #define RX_TPA_START_V2_CMPL_FLAGS2_META_FORMAT_HDR_OFFSET \
4640 (UINT32_C(0x4) << 4)
4641 #define RX_TPA_START_V2_CMPL_FLAGS2_META_FORMAT_LAST \
4642 RX_TPA_START_V2_CMPL_FLAGS2_META_FORMAT_HDR_OFFSET
4644 * This field indicates the IP type for the inner-most IP header.
4645 * A value of '0' indicates IPv4. A value of '1' indicates IPv6.
4646 * This value is only valid if itype indicates a packet
4647 * with an IP header.
4649 #define RX_TPA_START_V2_CMPL_FLAGS2_IP_TYPE \
4652 * This indicates that the complete 1's complement checksum was
4653 * calculated for the packet in the affregation.
4655 #define RX_TPA_START_V2_CMPL_FLAGS2_COMPLETE_CHECKSUM_CALC \
4658 * This field indicates the status of IP and L4 CS calculations done
4659 * by the chip. The format of this field is indicated by the
4660 * cs_all_ok_mode bit.
4661 * CS status for TPA packets is always valid. This means that "all_ok"
4662 * status will always be set. The ok count status will be set
4663 * appropriately for the packet header, such that all existing CS
4666 #define RX_TPA_START_V2_CMPL_FLAGS2_CS_OK_MASK \
4668 #define RX_TPA_START_V2_CMPL_FLAGS2_CS_OK_SFT 10
4670 * This value is the complete 1's complement checksum calculated from
4671 * the start of the outer L3 header to the end of the packet (not
4672 * including the ethernet crc). It is valid when the
4673 * 'complete_checksum_calc' flag is set. For TPA Start completions,
4674 * the complete checksum is calculated for the first packet in the
4677 #define RX_TPA_START_V2_CMPL_FLAGS2_COMPLETE_CHECKSUM_MASK \
4678 UINT32_C(0xffff0000)
4679 #define RX_TPA_START_V2_CMPL_FLAGS2_COMPLETE_CHECKSUM_SFT 16
4681 * This is data from the CFA block as indicated by the meta_format
4683 * - meta_format 0 - none - metadata2 = 0 - not valid/not stripped
4684 * - meta_format 1 - act_rec_ptr - metadata2 = {table_scope[5:0],
4685 * act_rec_ptr[25:0]}
4686 * - meta_format 2 - tunnel_id - metadata2 = tunnel_id[31:0]
4687 * - meta_format 3 - chdr_data - metadata2 = updated_chdr_data[31:0]
4688 * - meta_format 4 - hdr_offsets - metadata2 = hdr_offsets[31:0]
4689 * When vee_cmpl_mode is set in VNIC context, this is the upper 32b
4690 * of the host address from the first BD used to place the packet.
4695 * This value is written by the NIC such that it will be different
4696 * for each pass through the completion queue. The even passes
4697 * will write 1. The odd passes will write 0.
4699 #define RX_TPA_START_V2_CMPL_V2 \
4701 #define RX_TPA_START_V2_CMPL_ERRORS_MASK \
4703 #define RX_TPA_START_V2_CMPL_ERRORS_SFT 1
4705 * This error indicates that there was some sort of problem with
4706 * the BDs for the packetThe packet should be treated as
4709 #define RX_TPA_START_V2_CMPL_ERRORS_BUFFER_ERROR_MASK \
4711 #define RX_TPA_START_V2_CMPL_ERRORS_BUFFER_ERROR_SFT 1
4712 /* No buffer error */
4713 #define RX_TPA_START_V2_CMPL_ERRORS_BUFFER_ERROR_NO_BUFFER \
4714 (UINT32_C(0x0) << 1)
4717 * Packet did not fit into packet buffer provided. This means
4718 * that the TPA Start packet was too big to be placed into the
4719 * per-packet maximum number of physical buffers configured for
4720 * the VNIC, or that it was too big to be placed into the
4721 * per-aggregation maximum number of physical buffers configured
4722 * for the VNIC. This error only occurs when the VNIC is
4723 * configured for variable size receive buffers.
4725 #define RX_TPA_START_V2_CMPL_ERRORS_BUFFER_ERROR_DID_NOT_FIT \
4726 (UINT32_C(0x1) << 1)
4729 * BDs were not formatted correctly.
4731 #define RX_TPA_START_V2_CMPL_ERRORS_BUFFER_ERROR_BAD_FORMAT \
4732 (UINT32_C(0x3) << 1)
4735 * There was a bad_format error on the previous operation
4737 #define RX_TPA_START_V2_CMPL_ERRORS_BUFFER_ERROR_FLUSH \
4738 (UINT32_C(0x5) << 1)
4739 #define RX_TPA_START_V2_CMPL_ERRORS_BUFFER_ERROR_LAST \
4740 RX_TPA_START_V2_CMPL_ERRORS_BUFFER_ERROR_FLUSH
4742 * This is data from the CFA block as indicated by the meta_format
4746 /* When meta_format != 0, this value is the VLAN VID. */
4747 #define RX_TPA_START_V2_CMPL_METADATA0_VID_MASK UINT32_C(0xfff)
4748 #define RX_TPA_START_V2_CMPL_METADATA0_VID_SFT 0
4749 /* When meta_format != 0, this value is the VLAN DE. */
4750 #define RX_TPA_START_V2_CMPL_METADATA0_DE UINT32_C(0x1000)
4751 /* When meta_format != 0, this value is the VLAN PRI. */
4752 #define RX_TPA_START_V2_CMPL_METADATA0_PRI_MASK UINT32_C(0xe000)
4753 #define RX_TPA_START_V2_CMPL_METADATA0_PRI_SFT 13
4755 * This field contains the outer_l3_offset, inner_l2_offset,
4756 * inner_l3_offset, and inner_l4_size.
4758 * hdr_offsets[8:0] contains the outer_l3_offset.
4759 * hdr_offsets[17:9] contains the inner_l2_offset.
4760 * hdr_offsets[26:18] contains the inner_l3_offset.
4761 * hdr_offsets[31:27] contains the inner_l4_size.
4763 uint32_t hdr_offsets;
4767 * This TPA completion structure is used on devices where the
4768 * `hwrm_vnic_qcaps.max_aggs_supported` value is 0.
4770 /* rx_tpa_end_cmpl (size:128b/16B) */
4771 struct rx_tpa_end_cmpl {
4772 uint16_t flags_type;
4774 * This field indicates the exact type of the completion.
4775 * By convention, the LSB identifies the length of the
4776 * record in 16B units. Even values indicate 16B
4777 * records. Odd values indicate 32B
4780 #define RX_TPA_END_CMPL_TYPE_MASK UINT32_C(0x3f)
4781 #define RX_TPA_END_CMPL_TYPE_SFT 0
4783 * RX L2 TPA End Completion:
4784 * Completion at the end of a TPA operation.
4787 #define RX_TPA_END_CMPL_TYPE_RX_TPA_END UINT32_C(0x15)
4788 #define RX_TPA_END_CMPL_TYPE_LAST \
4789 RX_TPA_END_CMPL_TYPE_RX_TPA_END
4790 #define RX_TPA_END_CMPL_FLAGS_MASK UINT32_C(0xffc0)
4791 #define RX_TPA_END_CMPL_FLAGS_SFT 6
4793 * When this bit is '1', it indicates a packet that has an
4794 * error of some type. Type of error is indicated in
4797 #define RX_TPA_END_CMPL_FLAGS_ERROR UINT32_C(0x40)
4798 /* This field indicates how the packet was placed in the buffer. */
4799 #define RX_TPA_END_CMPL_FLAGS_PLACEMENT_MASK UINT32_C(0x380)
4800 #define RX_TPA_END_CMPL_FLAGS_PLACEMENT_SFT 7
4803 * TPA Packet was placed using jumbo algorithm. This means
4804 * that the first buffer will be filled with data before
4805 * moving to aggregation buffers. Each aggregation buffer
4806 * will be filled before moving to the next aggregation
4809 #define RX_TPA_END_CMPL_FLAGS_PLACEMENT_JUMBO \
4810 (UINT32_C(0x1) << 7)
4812 * Header/Data Separation:
4813 * Packet was placed using Header/Data separation algorithm.
4814 * The separation location is indicated by the itype field.
4816 #define RX_TPA_END_CMPL_FLAGS_PLACEMENT_HDS \
4817 (UINT32_C(0x2) << 7)
4820 * Packet will be placed using In-Order Completion/Jumbo where
4821 * the first packet of the aggregation is placed using Jumbo
4822 * Placement. Subsequent packets will be placed such that each
4823 * packet starts at the beginning of an aggregation buffer.
4825 #define RX_TPA_END_CMPL_FLAGS_PLACEMENT_IOC_JUMBO \
4826 (UINT32_C(0x4) << 7)
4829 * Packet will be placed using GRO/Jumbo where the first
4830 * packet is filled with data. Subsequent packets will be
4831 * placed such that any one packet does not span two
4832 * aggregation buffers unless it starts at the beginning of
4833 * an aggregation buffer.
4835 #define RX_TPA_END_CMPL_FLAGS_PLACEMENT_GRO_JUMBO \
4836 (UINT32_C(0x5) << 7)
4838 * GRO/Header-Data Separation:
4839 * Packet will be placed using GRO/HDS where the header
4840 * is in the first packet.
4841 * Payload of each packet will be
4842 * placed such that any one packet does not span two
4843 * aggregation buffers unless it starts at the beginning of
4844 * an aggregation buffer.
4846 #define RX_TPA_END_CMPL_FLAGS_PLACEMENT_GRO_HDS \
4847 (UINT32_C(0x6) << 7)
4849 * IOC/Header-Data Separation:
4850 * Packet will be placed using In-Order Completion/HDS where
4851 * the header is in the first packet buffer. Payload of each
4852 * packet will be placed such that each packet starts at the
4853 * beginning of an aggregation buffer.
4855 #define RX_TPA_END_CMPL_FLAGS_PLACEMENT_IOC_HDS \
4856 (UINT32_C(0x7) << 7)
4857 #define RX_TPA_END_CMPL_FLAGS_PLACEMENT_LAST \
4858 RX_TPA_END_CMPL_FLAGS_PLACEMENT_IOC_HDS
4860 #define RX_TPA_END_CMPL_FLAGS_UNUSED UINT32_C(0x400)
4862 * This bit is '1' if metadata has been added to the end of the
4863 * packet in host memory. Metadata starts at the first 32B boundary
4864 * after the end of the packet for regular and jumbo placement.
4865 * It starts at the first 32B boundary after the end of the header
4866 * for HDS placement. The length of the metadata is indicated in the
4869 #define RX_TPA_END_CMPL_FLAGS_PKT_METADATA_PRESENT UINT32_C(0x800)
4871 * This value indicates what the inner packet determined for the
4874 * Indicates that the packet was IP and TCP. This indicates
4875 * that the ip_cs field is valid and that the tcp_udp_cs
4876 * field is valid and contains the TCP checksum.
4877 * This also indicates that the payload_offset field is valid.
4879 #define RX_TPA_END_CMPL_FLAGS_ITYPE_MASK \
4881 #define RX_TPA_END_CMPL_FLAGS_ITYPE_SFT 12
4883 * This value is zero for TPA End completions.
4884 * There is no data in the buffer that corresponds to the opaque
4885 * value in this completion.
4889 * This is a copy of the opaque field from the RX BD this completion
4894 * This value is written by the NIC such that it will be different
4895 * for each pass through the completion queue. The even passes
4896 * will write 1. The odd passes will write 0.
4898 uint8_t agg_bufs_v1;
4900 * This value is written by the NIC such that it will be different
4901 * for each pass through the completion queue. The even passes
4902 * will write 1. The odd passes will write 0.
4904 #define RX_TPA_END_CMPL_V1 UINT32_C(0x1)
4906 * This value is the number of aggregation buffers that follow this
4907 * entry in the completion ring that are a part of this aggregation
4909 * If the value is zero, then the packet is completely contained
4910 * in the buffer space provided in the aggregation start completion.
4912 #define RX_TPA_END_CMPL_AGG_BUFS_MASK UINT32_C(0x7e)
4913 #define RX_TPA_END_CMPL_AGG_BUFS_SFT 1
4914 /* This value is the number of segments in the TPA operation. */
4917 * This value indicates the offset in bytes from the beginning of the packet
4918 * where the inner payload starts. This value is valid for TCP, UDP,
4919 * FCoE, and RoCE packets.
4921 * A value of zero indicates an offset of 256 bytes.
4923 uint8_t payload_offset;
4925 /* unused2 is 1 b */
4926 #define RX_TPA_END_CMPL_UNUSED2 UINT32_C(0x1)
4928 * This is the aggregation ID that the completion is associated
4929 * with. Use this number to correlate the TPA start completion
4930 * with the TPA end completion.
4932 #define RX_TPA_END_CMPL_AGG_ID_MASK UINT32_C(0xfe)
4933 #define RX_TPA_END_CMPL_AGG_ID_SFT 1
4935 * For non-GRO packets, this value is the
4936 * timestamp delta between earliest and latest timestamp values for
4937 * TPA packet. If packets were not time stamped, then delta will be
4940 * For GRO packets, this field is zero except for the following
4943 * Timestamp present indication. When '0', no Timestamp
4944 * option is in the packet. When '1', then a Timestamp
4945 * option is present in the packet.
4951 * Last 16 bytes of rx_tpa_end_cmpl.
4953 * This TPA completion structure is used on devices where the
4954 * `hwrm_vnic_qcaps.max_aggs_supported` value is 0.
4956 /* rx_tpa_end_cmpl_hi (size:128b/16B) */
4957 struct rx_tpa_end_cmpl_hi {
4958 uint32_t tpa_dup_acks;
4960 * This value is the number of duplicate ACKs that have been
4961 * received as part of the TPA operation.
4963 #define RX_TPA_END_CMPL_TPA_DUP_ACKS_MASK UINT32_C(0xf)
4964 #define RX_TPA_END_CMPL_TPA_DUP_ACKS_SFT 0
4966 * This value is the valid when TPA completion is active. It
4967 * indicates the length of the longest segment of the TPA operation
4968 * for LRO mode and the length of the first segment in GRO mode.
4970 * This value may be used by GRO software to re-construct the original
4971 * packet stream from the TPA packet. This is the length of all
4972 * but the last segment for GRO. In LRO mode this value may be used
4973 * to indicate MSS size to the stack.
4975 uint16_t tpa_seg_len;
4976 /* unused4 is 16 b */
4980 * This value is written by the NIC such that it will be different
4981 * for each pass through the completion queue. The even passes
4982 * will write 1. The odd passes will write 0.
4984 #define RX_TPA_END_CMPL_V2 UINT32_C(0x1)
4985 #define RX_TPA_END_CMPL_ERRORS_MASK UINT32_C(0xfffe)
4986 #define RX_TPA_END_CMPL_ERRORS_SFT 1
4988 * This error indicates that there was some sort of problem with
4989 * the BDs for the packet that was found after part of the
4990 * packet was already placed. The packet should be treated as
4993 #define RX_TPA_END_CMPL_ERRORS_BUFFER_ERROR_MASK UINT32_C(0xe)
4994 #define RX_TPA_END_CMPL_ERRORS_BUFFER_ERROR_SFT 1
4996 * This error occurs when there is a fatal HW problem in
4997 * the chip only. It indicates that there were not
4998 * BDs on chip but that there was adequate reservation.
4999 * provided by the TPA block.
5001 #define RX_TPA_END_CMPL_ERRORS_BUFFER_ERROR_NOT_ON_CHIP \
5002 (UINT32_C(0x2) << 1)
5004 * This error occurs when TPA block was not configured to
5005 * reserve adequate BDs for TPA operations on this RX
5006 * ring. All data for the TPA operation was not placed.
5008 * This error can also be generated when the number of
5009 * segments is not programmed correctly in TPA and the
5010 * 33 total aggregation buffers allowed for the TPA
5011 * operation has been exceeded.
5013 #define RX_TPA_END_CMPL_ERRORS_BUFFER_ERROR_RSV_ERROR \
5014 (UINT32_C(0x4) << 1)
5015 #define RX_TPA_END_CMPL_ERRORS_BUFFER_ERROR_LAST \
5016 RX_TPA_END_CMPL_ERRORS_BUFFER_ERROR_RSV_ERROR
5017 /* unused5 is 16 b */
5020 * This is the opaque value that was completed for the TPA start
5021 * completion that corresponds to this TPA end completion.
5023 uint32_t start_opaque;
5027 * This TPA completion structure is used on devices where the
5028 * `hwrm_vnic_qcaps.max_aggs_supported` value is greater than 0.
5030 /* rx_tpa_v2_start_cmpl (size:128b/16B) */
5031 struct rx_tpa_v2_start_cmpl {
5032 uint16_t flags_type;
5034 * This field indicates the exact type of the completion.
5035 * By convention, the LSB identifies the length of the
5036 * record in 16B units. Even values indicate 16B
5037 * records. Odd values indicate 32B
5040 #define RX_TPA_V2_START_CMPL_TYPE_MASK \
5042 #define RX_TPA_V2_START_CMPL_TYPE_SFT 0
5044 * RX L2 TPA Start Completion:
5045 * Completion at the beginning of a TPA operation.
5048 #define RX_TPA_V2_START_CMPL_TYPE_RX_TPA_START \
5050 #define RX_TPA_V2_START_CMPL_TYPE_LAST \
5051 RX_TPA_V2_START_CMPL_TYPE_RX_TPA_START
5052 #define RX_TPA_V2_START_CMPL_FLAGS_MASK \
5054 #define RX_TPA_V2_START_CMPL_FLAGS_SFT 6
5055 /* This bit will always be '0' for TPA start completions. */
5056 #define RX_TPA_V2_START_CMPL_FLAGS_ERROR \
5058 /* This field indicates how the packet was placed in the buffer. */
5059 #define RX_TPA_V2_START_CMPL_FLAGS_PLACEMENT_MASK \
5061 #define RX_TPA_V2_START_CMPL_FLAGS_PLACEMENT_SFT 7
5064 * TPA Packet was placed using jumbo algorithm. This means
5065 * that the first buffer will be filled with data before
5066 * moving to aggregation buffers. Each aggregation buffer
5067 * will be filled before moving to the next aggregation
5070 #define RX_TPA_V2_START_CMPL_FLAGS_PLACEMENT_JUMBO \
5071 (UINT32_C(0x1) << 7)
5073 * Header/Data Separation:
5074 * Packet was placed using Header/Data separation algorithm.
5075 * The separation location is indicated by the itype field.
5077 #define RX_TPA_V2_START_CMPL_FLAGS_PLACEMENT_HDS \
5078 (UINT32_C(0x2) << 7)
5081 * Packet will be placed using GRO/Jumbo where the first
5082 * packet is filled with data. Subsequent packets will be
5083 * placed such that any one packet does not span two
5084 * aggregation buffers unless it starts at the beginning of
5085 * an aggregation buffer.
5087 #define RX_TPA_V2_START_CMPL_FLAGS_PLACEMENT_GRO_JUMBO \
5088 (UINT32_C(0x5) << 7)
5090 * GRO/Header-Data Separation:
5091 * Packet will be placed using GRO/HDS where the header
5092 * is in the first packet.
5093 * Payload of each packet will be
5094 * placed such that any one packet does not span two
5095 * aggregation buffers unless it starts at the beginning of
5096 * an aggregation buffer.
5098 #define RX_TPA_V2_START_CMPL_FLAGS_PLACEMENT_GRO_HDS \
5099 (UINT32_C(0x6) << 7)
5100 #define RX_TPA_V2_START_CMPL_FLAGS_PLACEMENT_LAST \
5101 RX_TPA_V2_START_CMPL_FLAGS_PLACEMENT_GRO_HDS
5102 /* This bit is '1' if the RSS field in this completion is valid. */
5103 #define RX_TPA_V2_START_CMPL_FLAGS_RSS_VALID \
5106 * For devices that support timestamps, when this bit is cleared the
5107 * `inner_l4_size_inner_l3_offset_inner_l2_offset_outer_l3_offset`
5108 * field contains the 32b timestamp for
5109 * the packet from the MAC. When this bit is set, the
5110 * `inner_l4_size_inner_l3_offset_inner_l2_offset_outer_l3_offset`
5111 * field contains the outer_l3_offset, inner_l2_offset,
5112 * inner_l3_offset, and inner_l4_size.
5114 #define RX_TPA_V2_START_CMPL_FLAGS_TIMESTAMP_FLD_FORMAT \
5117 * This value indicates what the inner packet determined for the
5120 #define RX_TPA_V2_START_CMPL_FLAGS_ITYPE_MASK \
5122 #define RX_TPA_V2_START_CMPL_FLAGS_ITYPE_SFT 12
5125 * Indicates that the packet was IP and TCP.
5127 #define RX_TPA_V2_START_CMPL_FLAGS_ITYPE_TCP \
5128 (UINT32_C(0x2) << 12)
5129 #define RX_TPA_V2_START_CMPL_FLAGS_ITYPE_LAST \
5130 RX_TPA_V2_START_CMPL_FLAGS_ITYPE_TCP
5132 * This value indicates the amount of packet data written to the
5133 * buffer the opaque field in this completion corresponds to.
5137 * This is a copy of the opaque field from the RX BD this completion
5142 * This value is written by the NIC such that it will be different
5143 * for each pass through the completion queue. The even passes
5144 * will write 1. The odd passes will write 0.
5148 * This value is written by the NIC such that it will be different
5149 * for each pass through the completion queue. The even passes
5150 * will write 1. The odd passes will write 0.
5152 #define RX_TPA_V2_START_CMPL_V1 UINT32_C(0x1)
5153 #define RX_TPA_V2_START_CMPL_LAST RX_TPA_V2_START_CMPL_V1
5155 * This is the RSS hash type for the packet. The value is packed
5156 * {tuple_extrac_op[1:0],rss_profile_id[4:0],tuple_extrac_op[2]}.
5158 * The value of tuple_extrac_op provides the information about
5159 * what fields the hash was computed on.
5160 * * 0: The RSS hash was computed over source IP address,
5161 * destination IP address, source port, and destination port of inner
5162 * IP and TCP or UDP headers. Note: For non-tunneled packets,
5163 * the packet headers are considered inner packet headers for the RSS
5164 * hash computation purpose.
5165 * * 1: The RSS hash was computed over source IP address and destination
5166 * IP address of inner IP header. Note: For non-tunneled packets,
5167 * the packet headers are considered inner packet headers for the RSS
5168 * hash computation purpose.
5169 * * 2: The RSS hash was computed over source IP address,
5170 * destination IP address, source port, and destination port of
5171 * IP and TCP or UDP headers of outer tunnel headers.
5172 * Note: For non-tunneled packets, this value is not applicable.
5173 * * 3: The RSS hash was computed over source IP address and
5174 * destination IP address of IP header of outer tunnel headers.
5175 * Note: For non-tunneled packets, this value is not applicable.
5177 * Note that 4-tuples values listed above are applicable
5178 * for layer 4 protocols supported and enabled for RSS in the hardware,
5179 * HWRM firmware, and drivers. For example, if RSS hash is supported and
5180 * enabled for TCP traffic only, then the values of tuple_extract_op
5181 * corresponding to 4-tuples are only valid for TCP traffic.
5183 uint8_t rss_hash_type;
5185 * This is the aggregation ID that the completion is associated
5186 * with. Use this number to correlate the TPA start completion
5187 * with the TPA end completion.
5191 * This value is the RSS hash value calculated for the packet
5192 * based on the mode bits and key value in the VNIC.
5198 * Last 16 bytes of rx_tpa_v2_start_cmpl.
5200 * This TPA completion structure is used on devices where the
5201 * `hwrm_vnic_qcaps.max_aggs_supported` value is greater than 0.
5203 /* rx_tpa_v2_start_cmpl_hi (size:128b/16B) */
5204 struct rx_tpa_v2_start_cmpl_hi {
5207 * This indicates that the ip checksum was calculated for the
5208 * inner packet and that the sum passed for all segments
5209 * included in the aggregation.
5211 #define RX_TPA_V2_START_CMPL_FLAGS2_IP_CS_CALC \
5214 * This indicates that the TCP, UDP or ICMP checksum was
5215 * calculated for the inner packet and that the sum passed
5216 * for all segments included in the aggregation.
5218 #define RX_TPA_V2_START_CMPL_FLAGS2_L4_CS_CALC \
5221 * This indicates that the ip checksum was calculated for the
5222 * tunnel header and that the sum passed for all segments
5223 * included in the aggregation.
5225 #define RX_TPA_V2_START_CMPL_FLAGS2_T_IP_CS_CALC \
5228 * This indicates that the UDP checksum was
5229 * calculated for the tunnel packet and that the sum passed for
5230 * all segments included in the aggregation.
5232 #define RX_TPA_V2_START_CMPL_FLAGS2_T_L4_CS_CALC \
5234 /* This value indicates what format the metadata field is. */
5235 #define RX_TPA_V2_START_CMPL_FLAGS2_META_FORMAT_MASK \
5237 #define RX_TPA_V2_START_CMPL_FLAGS2_META_FORMAT_SFT 4
5238 /* No metadata informtaion. Value is zero. */
5239 #define RX_TPA_V2_START_CMPL_FLAGS2_META_FORMAT_NONE \
5240 (UINT32_C(0x0) << 4)
5242 * The metadata field contains the VLAN tag and TPID value.
5243 * - metadata[11:0] contains the vlan VID value.
5244 * - metadata[12] contains the vlan DE value.
5245 * - metadata[15:13] contains the vlan PRI value.
5246 * - metadata[31:16] contains the vlan TPID value.
5248 #define RX_TPA_V2_START_CMPL_FLAGS2_META_FORMAT_VLAN \
5249 (UINT32_C(0x1) << 4)
5251 * If ext_meta_format is equal to 1, the metadata field
5252 * contains the lower 16b of the tunnel ID value, justified
5254 * - VXLAN = VNI[23:0] -> VXLAN Network ID
5255 * - Geneve (NGE) = VNI[23:0] a-> Virtual Network Identifier.
5256 * - NVGRE = TNI[23:0] -> Tenant Network ID
5257 * - GRE = KEY[31:0 -> key fieled with bit mask. zero if K = 0
5258 * - IPV4 = 0 (not populated)
5259 * - IPV6 = Flow Label[19:0]
5260 * - PPPoE = sessionID[15:0]
5261 * - MPLs = Outer label[19:0]
5262 * - UPAR = Selected[31:0] with bit mask
5264 #define RX_TPA_V2_START_CMPL_FLAGS2_META_FORMAT_TUNNEL_ID \
5265 (UINT32_C(0x2) << 4)
5267 * if ext_meta_format is equal to 1, metadata field contains
5268 * 16b metadata from the prepended header (chdr_data).
5270 #define RX_TPA_V2_START_CMPL_FLAGS2_META_FORMAT_CHDR_DATA \
5271 (UINT32_C(0x3) << 4)
5273 * If ext_meta_format is equal to 1, the metadata field contains
5274 * the outer_l3_offset, inner_l2_offset, inner_l3_offset and
5276 * - metadata[8:0] contains the outer_l3_offset.
5277 * - metadata[17:9] contains the inner_l2_offset.
5278 * - metadata[26:18] contains the inner_l3_offset.
5279 * - metadata[31:27] contains the inner_l4_size.
5281 #define RX_TPA_V2_START_CMPL_FLAGS2_META_FORMAT_HDR_OFFSET \
5282 (UINT32_C(0x4) << 4)
5283 #define RX_TPA_V2_START_CMPL_FLAGS2_META_FORMAT_LAST \
5284 RX_TPA_V2_START_CMPL_FLAGS2_META_FORMAT_HDR_OFFSET
5286 * This field indicates the IP type for the inner-most IP header.
5287 * A value of '0' indicates IPv4. A value of '1' indicates IPv6.
5289 #define RX_TPA_V2_START_CMPL_FLAGS2_IP_TYPE \
5292 * This indicates that the complete 1's complement checksum was
5293 * calculated for the packet.
5295 #define RX_TPA_V2_START_CMPL_FLAGS2_COMPLETE_CHECKSUM_CALC \
5298 * The combination of this value and meta_format indicated what
5299 * format the metadata field is.
5301 #define RX_TPA_V2_START_CMPL_FLAGS2_EXT_META_FORMAT_MASK \
5303 #define RX_TPA_V2_START_CMPL_FLAGS2_EXT_META_FORMAT_SFT 10
5305 * This value is the complete 1's complement checksum calculated from
5306 * the start of the outer L3 header to the end of the packet (not
5307 * including the ethernet crc). It is valid when the
5308 * 'complete_checksum_calc' flag is set. For TPA Start completions,
5309 * the complete checksum is calculated for the first packet in the
5312 #define RX_TPA_V2_START_CMPL_FLAGS2_COMPLETE_CHECKSUM_MASK \
5313 UINT32_C(0xffff0000)
5314 #define RX_TPA_V2_START_CMPL_FLAGS2_COMPLETE_CHECKSUM_SFT 16
5316 * This is data from the CFA block as indicated by the meta_format
5320 /* When {ext_meta_format,meta_format}=1, this value is the VLAN VID. */
5321 #define RX_TPA_V2_START_CMPL_METADATA_VID_MASK UINT32_C(0xfff)
5322 #define RX_TPA_V2_START_CMPL_METADATA_VID_SFT 0
5323 /* When {ext_meta_format,meta_format}=1, this value is the VLAN DE. */
5324 #define RX_TPA_V2_START_CMPL_METADATA_DE UINT32_C(0x1000)
5325 /* When {ext_meta_format,meta_format}=1, this value is the VLAN PRI. */
5326 #define RX_TPA_V2_START_CMPL_METADATA_PRI_MASK UINT32_C(0xe000)
5327 #define RX_TPA_V2_START_CMPL_METADATA_PRI_SFT 13
5328 /* When {ext_meta_format,meta_format}=1, this value is the VLAN TPID. */
5329 #define RX_TPA_V2_START_CMPL_METADATA_TPID_MASK UINT32_C(0xffff0000)
5330 #define RX_TPA_V2_START_CMPL_METADATA_TPID_SFT 16
5333 * This value is written by the NIC such that it will be different
5334 * for each pass through the completion queue. The even passes
5335 * will write 1. The odd passes will write 0.
5337 #define RX_TPA_V2_START_CMPL_V2 \
5339 #define RX_TPA_V2_START_CMPL_ERRORS_MASK \
5341 #define RX_TPA_V2_START_CMPL_ERRORS_SFT 1
5343 * This error indicates that there was some sort of problem with
5344 * the BDs for the packet that was found after part of the
5345 * packet was already placed. The packet should be treated as
5348 #define RX_TPA_V2_START_CMPL_ERRORS_BUFFER_ERROR_MASK \
5350 #define RX_TPA_V2_START_CMPL_ERRORS_BUFFER_ERROR_SFT 1
5351 /* No buffer error */
5352 #define RX_TPA_V2_START_CMPL_ERRORS_BUFFER_ERROR_NO_BUFFER \
5353 (UINT32_C(0x0) << 1)
5356 * BDs were not formatted correctly.
5358 #define RX_TPA_V2_START_CMPL_ERRORS_BUFFER_ERROR_BAD_FORMAT \
5359 (UINT32_C(0x3) << 1)
5362 * There was a bad_format error on the previous operation
5364 #define RX_TPA_V2_START_CMPL_ERRORS_BUFFER_ERROR_FLUSH \
5365 (UINT32_C(0x5) << 1)
5366 #define RX_TPA_V2_START_CMPL_ERRORS_BUFFER_ERROR_LAST \
5367 RX_TPA_V2_START_CMPL_ERRORS_BUFFER_ERROR_FLUSH
5369 * This field identifies the CFA action rule that was used for this
5374 * For devices that support timestamps this field is overridden
5375 * with the timestamp value. When `flags.timestamp_fld_format` is
5376 * cleared, this field contains the 32b timestamp for the packet from the
5379 * When `flags.timestamp_fld_format` is set, this field contains the
5380 * outer_l3_offset, inner_l2_offset, inner_l3_offset, and inner_l4_size
5383 uint32_t inner_l4_size_inner_l3_offset_inner_l2_offset_outer_l3_offset;
5385 * This is the offset from the beginning of the packet in bytes for
5386 * the outer L3 header. If there is no outer L3 header, then this
5389 #define RX_TPA_V2_START_CMPL_OUTER_L3_OFFSET_MASK UINT32_C(0x1ff)
5390 #define RX_TPA_V2_START_CMPL_OUTER_L3_OFFSET_SFT 0
5392 * This is the offset from the beginning of the packet in bytes for
5393 * the inner most L2 header.
5395 #define RX_TPA_V2_START_CMPL_INNER_L2_OFFSET_MASK UINT32_C(0x3fe00)
5396 #define RX_TPA_V2_START_CMPL_INNER_L2_OFFSET_SFT 9
5398 * This is the offset from the beginning of the packet in bytes for
5399 * the inner most L3 header.
5401 #define RX_TPA_V2_START_CMPL_INNER_L3_OFFSET_MASK UINT32_C(0x7fc0000)
5402 #define RX_TPA_V2_START_CMPL_INNER_L3_OFFSET_SFT 18
5404 * This is the size in bytes of the inner most L4 header.
5405 * This can be subtracted from the payload_offset to determine
5406 * the start of the inner most L4 header.
5408 #define RX_TPA_V2_START_CMPL_INNER_L4_SIZE_MASK UINT32_C(0xf8000000)
5409 #define RX_TPA_V2_START_CMPL_INNER_L4_SIZE_SFT 27
5413 * This TPA completion structure is used on devices where the
5414 * `hwrm_vnic_qcaps.max_aggs_supported` value is greater than 0.
5416 /* rx_tpa_v2_end_cmpl (size:128b/16B) */
5417 struct rx_tpa_v2_end_cmpl {
5418 uint16_t flags_type;
5420 * This field indicates the exact type of the completion.
5421 * By convention, the LSB identifies the length of the
5422 * record in 16B units. Even values indicate 16B
5423 * records. Odd values indicate 32B
5426 #define RX_TPA_V2_END_CMPL_TYPE_MASK UINT32_C(0x3f)
5427 #define RX_TPA_V2_END_CMPL_TYPE_SFT 0
5429 * RX L2 TPA End Completion:
5430 * Completion at the end of a TPA operation.
5433 #define RX_TPA_V2_END_CMPL_TYPE_RX_TPA_END UINT32_C(0x15)
5434 #define RX_TPA_V2_END_CMPL_TYPE_LAST \
5435 RX_TPA_V2_END_CMPL_TYPE_RX_TPA_END
5436 #define RX_TPA_V2_END_CMPL_FLAGS_MASK UINT32_C(0xffc0)
5437 #define RX_TPA_V2_END_CMPL_FLAGS_SFT 6
5439 * When this bit is '1', it indicates a packet that has an
5440 * error of some type. Type of error is indicated in
5443 #define RX_TPA_V2_END_CMPL_FLAGS_ERROR UINT32_C(0x40)
5444 /* This field indicates how the packet was placed in the buffer. */
5445 #define RX_TPA_V2_END_CMPL_FLAGS_PLACEMENT_MASK UINT32_C(0x380)
5446 #define RX_TPA_V2_END_CMPL_FLAGS_PLACEMENT_SFT 7
5449 * TPA Packet was placed using jumbo algorithm. This means
5450 * that the first buffer will be filled with data before
5451 * moving to aggregation buffers. Each aggregation buffer
5452 * will be filled before moving to the next aggregation
5455 #define RX_TPA_V2_END_CMPL_FLAGS_PLACEMENT_JUMBO \
5456 (UINT32_C(0x1) << 7)
5458 * Header/Data Separation:
5459 * Packet was placed using Header/Data separation algorithm.
5460 * The separation location is indicated by the itype field.
5462 #define RX_TPA_V2_END_CMPL_FLAGS_PLACEMENT_HDS \
5463 (UINT32_C(0x2) << 7)
5466 * Packet will be placed using GRO/Jumbo where the first
5467 * packet is filled with data. Subsequent packets will be
5468 * placed such that any one packet does not span two
5469 * aggregation buffers unless it starts at the beginning of
5470 * an aggregation buffer.
5472 #define RX_TPA_V2_END_CMPL_FLAGS_PLACEMENT_GRO_JUMBO \
5473 (UINT32_C(0x5) << 7)
5475 * GRO/Header-Data Separation:
5476 * Packet will be placed using GRO/HDS where the header
5477 * is in the first packet.
5478 * Payload of each packet will be
5479 * placed such that any one packet does not span two
5480 * aggregation buffers unless it starts at the beginning of
5481 * an aggregation buffer.
5483 #define RX_TPA_V2_END_CMPL_FLAGS_PLACEMENT_GRO_HDS \
5484 (UINT32_C(0x6) << 7)
5485 #define RX_TPA_V2_END_CMPL_FLAGS_PLACEMENT_LAST \
5486 RX_TPA_V2_END_CMPL_FLAGS_PLACEMENT_GRO_HDS
5488 #define RX_TPA_V2_END_CMPL_FLAGS_UNUSED_MASK UINT32_C(0xc00)
5489 #define RX_TPA_V2_END_CMPL_FLAGS_UNUSED_SFT 10
5491 * This value indicates what the inner packet determined for the
5494 * Indicates that the packet was IP and TCP. This indicates
5495 * that the ip_cs field is valid and that the tcp_udp_cs
5496 * field is valid and contains the TCP checksum.
5497 * This also indicates that the payload_offset field is valid.
5499 #define RX_TPA_V2_END_CMPL_FLAGS_ITYPE_MASK UINT32_C(0xf000)
5500 #define RX_TPA_V2_END_CMPL_FLAGS_ITYPE_SFT 12
5502 * This value is zero for TPA End completions.
5503 * There is no data in the buffer that corresponds to the opaque
5504 * value in this completion.
5508 * This is a copy of the opaque field from the RX BD this completion
5514 * This value is written by the NIC such that it will be different
5515 * for each pass through the completion queue. The even passes
5516 * will write 1. The odd passes will write 0.
5518 #define RX_TPA_V2_END_CMPL_V1 UINT32_C(0x1)
5519 /* This value is the number of segments in the TPA operation. */
5522 * This is the aggregation ID that the completion is associated
5523 * with. Use this number to correlate the TPA start completion
5524 * with the TPA end completion.
5528 * For non-GRO packets, this value is the
5529 * timestamp delta between earliest and latest timestamp values for
5530 * TPA packet. If packets were not time stamped, then delta will be
5533 * For GRO packets, this field is zero except for the following
5536 * Timestamp present indication. When '0', no Timestamp
5537 * option is in the packet. When '1', then a Timestamp
5538 * option is present in the packet.
5544 * Last 16 bytes of rx_tpa_v2_end_cmpl.
5546 * This TPA completion structure is used on devices where the
5547 * `hwrm_vnic_qcaps.max_aggs_supported` value is greater than 0.
5549 /* rx_tpa_v2_end_cmpl_hi (size:128b/16B) */
5550 struct rx_tpa_v2_end_cmpl_hi {
5552 * This value is the number of duplicate ACKs that have been
5553 * received as part of the TPA operation.
5555 uint16_t tpa_dup_acks;
5557 * This value is the number of duplicate ACKs that have been
5558 * received as part of the TPA operation.
5560 #define RX_TPA_V2_END_CMPL_TPA_DUP_ACKS_MASK UINT32_C(0xf)
5561 #define RX_TPA_V2_END_CMPL_TPA_DUP_ACKS_SFT 0
5563 * This value indicated the offset in bytes from the beginning of
5564 * the packet where the inner payload starts. This value is valid
5565 * for TCP, UDP, FCoE and RoCE packets
5567 uint8_t payload_offset;
5569 * The value is the total number of aggregation buffers that were
5570 * used in the TPA operation. All TPA aggregation buffer completions
5571 * precede the TPA End completion. If the value is zero, then the
5572 * aggregation is completely contained in the buffer space provided
5573 * in the aggregation start completion.
5574 * Note that the field is simply provided as a cross check.
5576 uint8_t tpa_agg_bufs;
5578 * This value is the valid when TPA completion is active. It
5579 * indicates the length of the longest segment of the TPA operation
5580 * for LRO mode and the length of the first segment in GRO mode.
5582 * This value may be used by GRO software to re-construct the original
5583 * packet stream from the TPA packet. This is the length of all
5584 * but the last segment for GRO. In LRO mode this value may be used
5585 * to indicate MSS size to the stack.
5587 uint16_t tpa_seg_len;
5591 * This value is written by the NIC such that it will be different
5592 * for each pass through the completion queue. The even passes
5593 * will write 1. The odd passes will write 0.
5595 #define RX_TPA_V2_END_CMPL_V2 UINT32_C(0x1)
5596 #define RX_TPA_V2_END_CMPL_ERRORS_MASK \
5598 #define RX_TPA_V2_END_CMPL_ERRORS_SFT 1
5600 * This error indicates that there was some sort of problem with
5601 * the BDs for the packet that was found after part of the
5602 * packet was already placed. The packet should be treated as
5605 #define RX_TPA_V2_END_CMPL_ERRORS_BUFFER_ERROR_MASK \
5607 #define RX_TPA_V2_END_CMPL_ERRORS_BUFFER_ERROR_SFT 1
5608 /* No buffer error */
5609 #define RX_TPA_V2_END_CMPL_ERRORS_BUFFER_ERROR_NO_BUFFER \
5610 (UINT32_C(0x0) << 1)
5612 * This error occurs when there is a fatal HW problem in
5613 * the chip only. It indicates that there were not
5614 * BDs on chip but that there was adequate reservation.
5615 * provided by the TPA block.
5617 #define RX_TPA_V2_END_CMPL_ERRORS_BUFFER_ERROR_NOT_ON_CHIP \
5618 (UINT32_C(0x2) << 1)
5621 * BDs were not formatted correctly.
5623 #define RX_TPA_V2_END_CMPL_ERRORS_BUFFER_ERROR_BAD_FORMAT \
5624 (UINT32_C(0x3) << 1)
5626 * This error occurs when TPA block was not configured to
5627 * reserve adequate BDs for TPA operations on this RX
5628 * ring. All data for the TPA operation was not placed.
5630 * This error can also be generated when the number of
5631 * segments is not programmed correctly in TPA and the
5632 * 33 total aggregation buffers allowed for the TPA
5633 * operation has been exceeded.
5635 #define RX_TPA_V2_END_CMPL_ERRORS_BUFFER_ERROR_RSV_ERROR \
5636 (UINT32_C(0x4) << 1)
5639 * There was a bad_format error on the previous operation
5641 #define RX_TPA_V2_END_CMPL_ERRORS_BUFFER_ERROR_FLUSH \
5642 (UINT32_C(0x5) << 1)
5643 #define RX_TPA_V2_END_CMPL_ERRORS_BUFFER_ERROR_LAST \
5644 RX_TPA_V2_END_CMPL_ERRORS_BUFFER_ERROR_FLUSH
5647 * This is the opaque value that was completed for the TPA start
5648 * completion that corresponds to this TPA end completion.
5650 uint32_t start_opaque;
5654 * This TPA completion structure is used on devices where the
5655 * `hwrm_vnic_qcaps.max_aggs_supported` value is greater than 0.
5657 /* rx_tpa_v2_abuf_cmpl (size:128b/16B) */
5658 struct rx_tpa_v2_abuf_cmpl {
5661 * This field indicates the exact type of the completion.
5662 * By convention, the LSB identifies the length of the
5663 * record in 16B units. Even values indicate 16B
5664 * records. Odd values indicate 32B
5667 #define RX_TPA_V2_ABUF_CMPL_TYPE_MASK UINT32_C(0x3f)
5668 #define RX_TPA_V2_ABUF_CMPL_TYPE_SFT 0
5670 * RX TPA Aggregation Buffer completion :
5671 * Completion of an L2 aggregation buffer in support of
5672 * TPA packet completion. Length = 16B
5674 #define RX_TPA_V2_ABUF_CMPL_TYPE_RX_TPA_AGG UINT32_C(0x16)
5675 #define RX_TPA_V2_ABUF_CMPL_TYPE_LAST \
5676 RX_TPA_V2_ABUF_CMPL_TYPE_RX_TPA_AGG
5678 * This is the length of the data for the packet stored in this
5679 * aggregation buffer identified by the opaque value. This does not
5680 * include the length of any
5681 * data placed in other aggregation BDs or in the packet or buffer
5682 * BDs. This length does not include any space added due to
5683 * hdr_offset register during HDS placement mode.
5687 * This is a copy of the opaque field from the RX BD this aggregation
5688 * buffer corresponds to.
5693 * This value is written by the NIC such that it will be different
5694 * for each pass through the completion queue. The even passes
5695 * will write 1. The odd passes will write 0.
5697 #define RX_TPA_V2_ABUF_CMPL_V UINT32_C(0x1)
5699 * This is the aggregation ID that the completion is associated with. Use
5700 * this number to correlate the TPA agg completion with the TPA start
5701 * completion and the TPA end completion.
5707 /* rx_abuf_cmpl (size:128b/16B) */
5708 struct rx_abuf_cmpl {
5711 * This field indicates the exact type of the completion.
5712 * By convention, the LSB identifies the length of the
5713 * record in 16B units. Even values indicate 16B
5714 * records. Odd values indicate 32B
5717 #define RX_ABUF_CMPL_TYPE_MASK UINT32_C(0x3f)
5718 #define RX_ABUF_CMPL_TYPE_SFT 0
5720 * RX Aggregation Buffer completion :
5721 * Completion of an L2 aggregation buffer in support of
5722 * TPA, HDS, or Jumbo packet completion. Length = 16B
5724 #define RX_ABUF_CMPL_TYPE_RX_AGG UINT32_C(0x12)
5725 #define RX_ABUF_CMPL_TYPE_LAST RX_ABUF_CMPL_TYPE_RX_AGG
5727 * This is the length of the data for the packet stored in this
5728 * aggregation buffer identified by the opaque value. This does not
5729 * include the length of any
5730 * data placed in other aggregation BDs or in the packet or buffer
5731 * BDs. This length does not include any space added due to
5732 * hdr_offset register during HDS placement mode.
5736 * This is a copy of the opaque field from the RX BD this aggregation
5737 * buffer corresponds to.
5742 * This value is written by the NIC such that it will be different
5743 * for each pass through the completion queue. The even passes
5744 * will write 1. The odd passes will write 0.
5746 #define RX_ABUF_CMPL_V UINT32_C(0x1)
5747 /* unused3 is 32 b */
5751 /* VEE FLUSH Completion Record (16 bytes) */
5752 /* vee_flush (size:128b/16B) */
5754 uint32_t downstream_path_type;
5756 * This field indicates the exact type of the completion.
5757 * By convention, the LSB identifies the length of the
5758 * record in 16B units. Even values indicate 16B
5759 * records. Odd values indicate 32B
5762 #define VEE_FLUSH_TYPE_MASK UINT32_C(0x3f)
5763 #define VEE_FLUSH_TYPE_SFT 0
5765 * VEE Flush Completion:
5766 * This completion is inserted manually by the Primate and processed
5767 * by the VEE hardware to ensure that all completions on a VEE
5768 * function have been processed by the VEE hardware before FLR
5769 * process is completed.
5771 #define VEE_FLUSH_TYPE_VEE_FLUSH UINT32_C(0x1c)
5772 #define VEE_FLUSH_TYPE_LAST VEE_FLUSH_TYPE_VEE_FLUSH
5773 /* downstream_path is 1 b */
5774 #define VEE_FLUSH_DOWNSTREAM_PATH UINT32_C(0x40)
5775 /* This completion is associated with VEE Transmit */
5776 #define VEE_FLUSH_DOWNSTREAM_PATH_TX (UINT32_C(0x0) << 6)
5777 /* This completion is associated with VEE Receive */
5778 #define VEE_FLUSH_DOWNSTREAM_PATH_RX (UINT32_C(0x1) << 6)
5779 #define VEE_FLUSH_DOWNSTREAM_PATH_LAST VEE_FLUSH_DOWNSTREAM_PATH_RX
5781 * This is an opaque value that is passed through the completion
5782 * to the VEE handler SW and is used to indicate what VEE VQ or
5783 * function has completed FLR processing.
5788 * This value is written by the NIC such that it will be different
5789 * for each pass through the completion queue. The even passes will
5790 * write 1. The odd passes will write 0.
5792 #define VEE_FLUSH_V UINT32_C(0x1)
5793 /* unused3 is 32 b */
5797 /* eject_cmpl (size:128b/16B) */
5801 * This field indicates the exact type of the completion.
5802 * By convention, the LSB identifies the length of the
5803 * record in 16B units. Even values indicate 16B
5804 * records. Odd values indicate 32B
5807 #define EJECT_CMPL_TYPE_MASK UINT32_C(0x3f)
5808 #define EJECT_CMPL_TYPE_SFT 0
5810 * Statistics Ejection Completion:
5811 * Completion of statistics data ejection buffer.
5814 #define EJECT_CMPL_TYPE_STAT_EJECT UINT32_C(0x1a)
5815 #define EJECT_CMPL_TYPE_LAST EJECT_CMPL_TYPE_STAT_EJECT
5816 #define EJECT_CMPL_FLAGS_MASK UINT32_C(0xffc0)
5817 #define EJECT_CMPL_FLAGS_SFT 6
5819 * When this bit is '1', it indicates a packet that has an
5820 * error of some type. Type of error is indicated in
5823 #define EJECT_CMPL_FLAGS_ERROR UINT32_C(0x40)
5825 * This is the length of the statistics data stored in this
5830 * This is a copy of the opaque field from the RX BD this ejection
5831 * buffer corresponds to.
5836 * This value is written by the NIC such that it will be different
5837 * for each pass through the completion queue. The even passes
5838 * will write 1. The odd passes will write 0.
5840 #define EJECT_CMPL_V UINT32_C(0x1)
5841 #define EJECT_CMPL_ERRORS_MASK UINT32_C(0xfffe)
5842 #define EJECT_CMPL_ERRORS_SFT 1
5844 * This error indicates that there was some sort of problem with
5845 * the BDs for statistics ejection. The statistics ejection should
5846 * be treated as invalid
5848 #define EJECT_CMPL_ERRORS_BUFFER_ERROR_MASK UINT32_C(0xe)
5849 #define EJECT_CMPL_ERRORS_BUFFER_ERROR_SFT 1
5850 /* No buffer error */
5851 #define EJECT_CMPL_ERRORS_BUFFER_ERROR_NO_BUFFER \
5852 (UINT32_C(0x0) << 1)
5855 * Statistics did not fit into aggregation buffer provided.
5857 #define EJECT_CMPL_ERRORS_BUFFER_ERROR_DID_NOT_FIT \
5858 (UINT32_C(0x1) << 1)
5861 * BDs were not formatted correctly.
5863 #define EJECT_CMPL_ERRORS_BUFFER_ERROR_BAD_FORMAT \
5864 (UINT32_C(0x3) << 1)
5867 * There was a bad_format error on the previous operation
5869 #define EJECT_CMPL_ERRORS_BUFFER_ERROR_FLUSH \
5870 (UINT32_C(0x5) << 1)
5871 #define EJECT_CMPL_ERRORS_BUFFER_ERROR_LAST \
5872 EJECT_CMPL_ERRORS_BUFFER_ERROR_FLUSH
5873 /* reserved16 is 16 b */
5874 uint16_t reserved16;
5875 /* unused3 is 32 b */
5879 /* hwrm_cmpl (size:128b/16B) */
5883 * This field indicates the exact type of the completion.
5884 * By convention, the LSB identifies the length of the
5885 * record in 16B units. Even values indicate 16B
5886 * records. Odd values indicate 32B
5889 #define HWRM_CMPL_TYPE_MASK UINT32_C(0x3f)
5890 #define HWRM_CMPL_TYPE_SFT 0
5892 * HWRM Command Completion:
5893 * Completion of an HWRM command.
5895 #define HWRM_CMPL_TYPE_HWRM_DONE UINT32_C(0x20)
5896 #define HWRM_CMPL_TYPE_LAST HWRM_CMPL_TYPE_HWRM_DONE
5897 /* This is the sequence_id of the HWRM command that has completed. */
5898 uint16_t sequence_id;
5899 /* unused2 is 32 b */
5903 * This value is written by the NIC such that it will be different
5904 * for each pass through the completion queue. The even passes
5905 * will write 1. The odd passes will write 0.
5907 #define HWRM_CMPL_V UINT32_C(0x1)
5908 /* unused4 is 32 b */
5912 /* hwrm_fwd_req_cmpl (size:128b/16B) */
5913 struct hwrm_fwd_req_cmpl {
5915 * This field indicates the exact type of the completion.
5916 * By convention, the LSB identifies the length of the
5917 * record in 16B units. Even values indicate 16B
5918 * records. Odd values indicate 32B
5921 uint16_t req_len_type;
5923 * This field indicates the exact type of the completion.
5924 * By convention, the LSB identifies the length of the
5925 * record in 16B units. Even values indicate 16B
5926 * records. Odd values indicate 32B
5929 #define HWRM_FWD_REQ_CMPL_TYPE_MASK UINT32_C(0x3f)
5930 #define HWRM_FWD_REQ_CMPL_TYPE_SFT 0
5931 /* Forwarded HWRM Request */
5932 #define HWRM_FWD_REQ_CMPL_TYPE_HWRM_FWD_REQ UINT32_C(0x22)
5933 #define HWRM_FWD_REQ_CMPL_TYPE_LAST \
5934 HWRM_FWD_REQ_CMPL_TYPE_HWRM_FWD_REQ
5935 /* Length of forwarded request in bytes. */
5936 #define HWRM_FWD_REQ_CMPL_REQ_LEN_MASK UINT32_C(0xffc0)
5937 #define HWRM_FWD_REQ_CMPL_REQ_LEN_SFT 6
5939 * Source ID of this request.
5940 * Typically used in forwarding requests and responses.
5941 * 0x0 - 0xFFF8 - Used for function ids
5942 * 0xFFF8 - 0xFFFE - Reserved for internal processors
5946 /* unused1 is 32 b */
5948 /* Address of forwarded request. */
5949 uint32_t req_buf_addr_v[2];
5951 * This value is written by the NIC such that it will be different
5952 * for each pass through the completion queue. The even passes
5953 * will write 1. The odd passes will write 0.
5955 #define HWRM_FWD_REQ_CMPL_V UINT32_C(0x1)
5956 /* Address of forwarded request. */
5957 #define HWRM_FWD_REQ_CMPL_REQ_BUF_ADDR_MASK UINT32_C(0xfffffffe)
5958 #define HWRM_FWD_REQ_CMPL_REQ_BUF_ADDR_SFT 1
5961 /* hwrm_fwd_resp_cmpl (size:128b/16B) */
5962 struct hwrm_fwd_resp_cmpl {
5965 * This field indicates the exact type of the completion.
5966 * By convention, the LSB identifies the length of the
5967 * record in 16B units. Even values indicate 16B
5968 * records. Odd values indicate 32B
5971 #define HWRM_FWD_RESP_CMPL_TYPE_MASK UINT32_C(0x3f)
5972 #define HWRM_FWD_RESP_CMPL_TYPE_SFT 0
5973 /* Forwarded HWRM Response */
5974 #define HWRM_FWD_RESP_CMPL_TYPE_HWRM_FWD_RESP UINT32_C(0x24)
5975 #define HWRM_FWD_RESP_CMPL_TYPE_LAST \
5976 HWRM_FWD_RESP_CMPL_TYPE_HWRM_FWD_RESP
5978 * Source ID of this response.
5979 * Typically used in forwarding requests and responses.
5980 * 0x0 - 0xFFF8 - Used for function ids
5981 * 0xFFF8 - 0xFFFE - Reserved for internal processors
5985 /* Length of forwarded response in bytes. */
5987 /* unused2 is 16 b */
5989 /* Address of forwarded request. */
5990 uint32_t resp_buf_addr_v[2];
5992 * This value is written by the NIC such that it will be different
5993 * for each pass through the completion queue. The even passes
5994 * will write 1. The odd passes will write 0.
5996 #define HWRM_FWD_RESP_CMPL_V UINT32_C(0x1)
5997 /* Address of forwarded request. */
5998 #define HWRM_FWD_RESP_CMPL_RESP_BUF_ADDR_MASK UINT32_C(0xfffffffe)
5999 #define HWRM_FWD_RESP_CMPL_RESP_BUF_ADDR_SFT 1
6002 /* hwrm_async_event_cmpl (size:128b/16B) */
6003 struct hwrm_async_event_cmpl {
6006 * This field indicates the exact type of the completion.
6007 * By convention, the LSB identifies the length of the
6008 * record in 16B units. Even values indicate 16B
6009 * records. Odd values indicate 32B
6012 #define HWRM_ASYNC_EVENT_CMPL_TYPE_MASK UINT32_C(0x3f)
6013 #define HWRM_ASYNC_EVENT_CMPL_TYPE_SFT 0
6014 /* HWRM Asynchronous Event Information */
6015 #define HWRM_ASYNC_EVENT_CMPL_TYPE_HWRM_ASYNC_EVENT UINT32_C(0x2e)
6016 #define HWRM_ASYNC_EVENT_CMPL_TYPE_LAST \
6017 HWRM_ASYNC_EVENT_CMPL_TYPE_HWRM_ASYNC_EVENT
6018 /* Identifiers of events. */
6020 /* Link status changed */
6021 #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_LINK_STATUS_CHANGE \
6023 /* Link MTU changed */
6024 #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_LINK_MTU_CHANGE \
6026 /* Link speed changed */
6027 #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_LINK_SPEED_CHANGE \
6029 /* DCB Configuration changed */
6030 #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_DCB_CONFIG_CHANGE \
6032 /* Port connection not allowed */
6033 #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_PORT_CONN_NOT_ALLOWED \
6035 /* Link speed configuration was not allowed */
6036 #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_LINK_SPEED_CFG_NOT_ALLOWED \
6038 /* Link speed configuration change */
6039 #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_LINK_SPEED_CFG_CHANGE \
6041 /* Port PHY configuration change */
6042 #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_PORT_PHY_CFG_CHANGE \
6044 /* Reset notification to clients */
6045 #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_RESET_NOTIFY \
6047 /* Master function selection event */
6048 #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_ERROR_RECOVERY \
6050 /* Function driver unloaded */
6051 #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_FUNC_DRVR_UNLOAD \
6053 /* Function driver loaded */
6054 #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_FUNC_DRVR_LOAD \
6056 /* Function FLR related processing has completed */
6057 #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_FUNC_FLR_PROC_CMPLT \
6059 /* PF driver unloaded */
6060 #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_PF_DRVR_UNLOAD \
6062 /* PF driver loaded */
6063 #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_PF_DRVR_LOAD \
6065 /* VF Function Level Reset (FLR) */
6066 #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_VF_FLR \
6068 /* VF MAC Address Change */
6069 #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_VF_MAC_ADDR_CHANGE \
6071 /* PF-VF communication channel status change. */
6072 #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_PF_VF_COMM_STATUS_CHANGE \
6074 /* VF Configuration Change */
6075 #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_VF_CFG_CHANGE \
6077 /* LLFC/PFC Configuration Change */
6078 #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_LLFC_PFC_CHANGE \
6080 /* Default VNIC Configuration Change */
6081 #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_DEFAULT_VNIC_CHANGE \
6084 #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_HW_FLOW_AGED \
6087 * A debug notification being posted to the driver. These
6088 * notifications are purely for diagnostic purpose and should not be
6089 * used for functional purpose. The driver is not supposed to act
6090 * on these messages except to log/record it.
6092 #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_DEBUG_NOTIFICATION \
6095 * An EEM flow cached memory flush for all flows request event being
6096 * posted to the PF driver.
6098 #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_EEM_CACHE_FLUSH_REQ \
6101 * An EEM flow cache memory flush completion event being posted to the
6102 * firmware by the PF driver. This is indication that host EEM flush
6103 * has completed by the PF.
6105 #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_EEM_CACHE_FLUSH_DONE \
6108 * A tcp flag action change event being posted to the PF or trusted VF
6109 * driver by the firmware. The PF or trusted VF driver should query
6110 * the firmware for the new TCP flag action update after receiving
6113 #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_TCP_FLAG_ACTION_CHANGE \
6116 * An EEM flow active event being posted to the PF or trusted VF driver
6117 * by the firmware. The PF or trusted VF driver should update the
6118 * flow's aging timer after receiving this async event.
6120 #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_EEM_FLOW_ACTIVE \
6123 * A eem cfg change event being posted to the trusted VF driver by the
6124 * firmware if the parent PF EEM configuration changed.
6126 #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_EEM_CFG_CHANGE \
6130 * TFLIB unique default VNIC Configuration Change
6132 #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_TFLIB_DEFAULT_VNIC_CHANGE \
6136 * TFLIB unique link status changed
6138 #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_TFLIB_LINK_STATUS_CHANGE \
6141 * An event signifying completion for HWRM_FW_STATE_QUIESCE
6142 * (completion, timeout, or error)
6144 #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_QUIESCE_DONE \
6147 * An event signifying a HWRM command is in progress and its
6148 * response will be deferred. This event is used on crypto controllers
6151 #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_DEFERRED_RESPONSE \
6154 * An event signifying that a PFC WatchDog configuration
6155 * has changed on any port / cos.
6157 #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_PFC_WATCHDOG_CFG_CHANGE \
6160 * A trace log message. This contains firmware trace logs string
6161 * embedded in the asynchronous message. This is an experimental
6162 * event, not meant for production use at this time.
6164 #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_FW_TRACE_MSG \
6167 #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_HWRM_ERROR \
6169 #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_LAST \
6170 HWRM_ASYNC_EVENT_CMPL_EVENT_ID_HWRM_ERROR
6171 /* Event specific data */
6172 uint32_t event_data2;
6175 * This value is written by the NIC such that it will be different
6176 * for each pass through the completion queue. The even passes
6177 * will write 1. The odd passes will write 0.
6179 #define HWRM_ASYNC_EVENT_CMPL_V UINT32_C(0x1)
6181 #define HWRM_ASYNC_EVENT_CMPL_OPAQUE_MASK UINT32_C(0xfe)
6182 #define HWRM_ASYNC_EVENT_CMPL_OPAQUE_SFT 1
6183 /* 8-lsb timestamp from POR (100-msec resolution) */
6184 uint8_t timestamp_lo;
6185 /* 16-lsb timestamp from POR (100-msec resolution) */
6186 uint16_t timestamp_hi;
6187 /* Event specific data */
6188 uint32_t event_data1;
6191 /* hwrm_async_event_cmpl_link_status_change (size:128b/16B) */
6192 struct hwrm_async_event_cmpl_link_status_change {
6195 * This field indicates the exact type of the completion.
6196 * By convention, the LSB identifies the length of the
6197 * record in 16B units. Even values indicate 16B
6198 * records. Odd values indicate 32B
6201 #define HWRM_ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_TYPE_MASK \
6203 #define HWRM_ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_TYPE_SFT 0
6204 /* HWRM Asynchronous Event Information */
6205 #define HWRM_ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_TYPE_HWRM_ASYNC_EVENT \
6207 #define HWRM_ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_TYPE_LAST \
6208 HWRM_ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_TYPE_HWRM_ASYNC_EVENT
6209 /* Identifiers of events. */
6211 /* Link status changed */
6212 #define HWRM_ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_ID_LINK_STATUS_CHANGE \
6214 #define HWRM_ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_ID_LAST \
6215 HWRM_ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_ID_LINK_STATUS_CHANGE
6216 /* Event specific data */
6217 uint32_t event_data2;
6220 * This value is written by the NIC such that it will be different
6221 * for each pass through the completion queue. The even passes
6222 * will write 1. The odd passes will write 0.
6224 #define HWRM_ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_V \
6227 #define HWRM_ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_OPAQUE_MASK \
6229 #define HWRM_ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_OPAQUE_SFT 1
6230 /* 8-lsb timestamp from POR (100-msec resolution) */
6231 uint8_t timestamp_lo;
6232 /* 16-lsb timestamp from POR (100-msec resolution) */
6233 uint16_t timestamp_hi;
6234 /* Event specific data */
6235 uint32_t event_data1;
6236 /* Indicates link status change */
6237 #define HWRM_ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_DATA1_LINK_CHANGE \
6240 * If this bit set to 0, then it indicates that the link
6241 * was up and it went down.
6243 #define HWRM_ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_DATA1_LINK_CHANGE_DOWN \
6246 * If this bit is set to 1, then it indicates that the link
6247 * was down and it went up.
6249 #define HWRM_ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_DATA1_LINK_CHANGE_UP \
6251 #define HWRM_ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_DATA1_LINK_CHANGE_LAST \
6252 HWRM_ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_DATA1_LINK_CHANGE_UP
6253 /* Indicates the physical port this link status change occur */
6254 #define HWRM_ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_DATA1_PORT_MASK \
6256 #define HWRM_ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_DATA1_PORT_SFT \
6259 #define HWRM_ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_DATA1_PORT_ID_MASK \
6261 #define HWRM_ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_DATA1_PORT_ID_SFT \
6263 /* Indicates the physical function this event occurred on. */
6264 #define HWRM_ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_DATA1_PF_ID_MASK \
6266 #define HWRM_ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_DATA1_PF_ID_SFT \
6270 /* hwrm_async_event_cmpl_link_mtu_change (size:128b/16B) */
6271 struct hwrm_async_event_cmpl_link_mtu_change {
6274 * This field indicates the exact type of the completion.
6275 * By convention, the LSB identifies the length of the
6276 * record in 16B units. Even values indicate 16B
6277 * records. Odd values indicate 32B
6280 #define HWRM_ASYNC_EVENT_CMPL_LINK_MTU_CHANGE_TYPE_MASK \
6282 #define HWRM_ASYNC_EVENT_CMPL_LINK_MTU_CHANGE_TYPE_SFT 0
6283 /* HWRM Asynchronous Event Information */
6284 #define HWRM_ASYNC_EVENT_CMPL_LINK_MTU_CHANGE_TYPE_HWRM_ASYNC_EVENT \
6286 #define HWRM_ASYNC_EVENT_CMPL_LINK_MTU_CHANGE_TYPE_LAST \
6287 HWRM_ASYNC_EVENT_CMPL_LINK_MTU_CHANGE_TYPE_HWRM_ASYNC_EVENT
6288 /* Identifiers of events. */
6290 /* Link MTU changed */
6291 #define HWRM_ASYNC_EVENT_CMPL_LINK_MTU_CHANGE_EVENT_ID_LINK_MTU_CHANGE \
6293 #define HWRM_ASYNC_EVENT_CMPL_LINK_MTU_CHANGE_EVENT_ID_LAST \
6294 HWRM_ASYNC_EVENT_CMPL_LINK_MTU_CHANGE_EVENT_ID_LINK_MTU_CHANGE
6295 /* Event specific data */
6296 uint32_t event_data2;
6299 * This value is written by the NIC such that it will be different
6300 * for each pass through the completion queue. The even passes
6301 * will write 1. The odd passes will write 0.
6303 #define HWRM_ASYNC_EVENT_CMPL_LINK_MTU_CHANGE_V UINT32_C(0x1)
6305 #define HWRM_ASYNC_EVENT_CMPL_LINK_MTU_CHANGE_OPAQUE_MASK \
6307 #define HWRM_ASYNC_EVENT_CMPL_LINK_MTU_CHANGE_OPAQUE_SFT 1
6308 /* 8-lsb timestamp from POR (100-msec resolution) */
6309 uint8_t timestamp_lo;
6310 /* 16-lsb timestamp from POR (100-msec resolution) */
6311 uint16_t timestamp_hi;
6312 /* Event specific data */
6313 uint32_t event_data1;
6314 /* The new MTU of the link in bytes. */
6315 #define HWRM_ASYNC_EVENT_CMPL_LINK_MTU_CHANGE_EVENT_DATA1_NEW_MTU_MASK \
6317 #define HWRM_ASYNC_EVENT_CMPL_LINK_MTU_CHANGE_EVENT_DATA1_NEW_MTU_SFT 0
6320 /* hwrm_async_event_cmpl_link_speed_change (size:128b/16B) */
6321 struct hwrm_async_event_cmpl_link_speed_change {
6324 * This field indicates the exact type of the completion.
6325 * By convention, the LSB identifies the length of the
6326 * record in 16B units. Even values indicate 16B
6327 * records. Odd values indicate 32B
6330 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_TYPE_MASK \
6332 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_TYPE_SFT 0
6333 /* HWRM Asynchronous Event Information */
6334 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_TYPE_HWRM_ASYNC_EVENT \
6336 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_TYPE_LAST \
6337 HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_TYPE_HWRM_ASYNC_EVENT
6338 /* Identifiers of events. */
6340 /* Link speed changed */
6341 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_EVENT_ID_LINK_SPEED_CHANGE \
6343 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_EVENT_ID_LAST \
6344 HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_EVENT_ID_LINK_SPEED_CHANGE
6345 /* Event specific data */
6346 uint32_t event_data2;
6349 * This value is written by the NIC such that it will be different
6350 * for each pass through the completion queue. The even passes
6351 * will write 1. The odd passes will write 0.
6353 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_V \
6356 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_OPAQUE_MASK \
6358 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_OPAQUE_SFT 1
6359 /* 8-lsb timestamp from POR (100-msec resolution) */
6360 uint8_t timestamp_lo;
6361 /* 16-lsb timestamp from POR (100-msec resolution) */
6362 uint16_t timestamp_hi;
6363 /* Event specific data */
6364 uint32_t event_data1;
6366 * When this bit is '1', the link was forced to the
6367 * force_link_speed value.
6369 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_EVENT_DATA1_FORCE \
6371 /* The new link speed in 100 Mbps units. */
6372 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_EVENT_DATA1_NEW_LINK_SPEED_100MBPS_MASK \
6374 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_EVENT_DATA1_NEW_LINK_SPEED_100MBPS_SFT \
6376 /* 100Mb link speed */
6377 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_EVENT_DATA1_NEW_LINK_SPEED_100MBPS_100MB \
6378 (UINT32_C(0x1) << 1)
6379 /* 1Gb link speed */
6380 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_EVENT_DATA1_NEW_LINK_SPEED_100MBPS_1GB \
6381 (UINT32_C(0xa) << 1)
6382 /* 2Gb link speed */
6383 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_EVENT_DATA1_NEW_LINK_SPEED_100MBPS_2GB \
6384 (UINT32_C(0x14) << 1)
6385 /* 25Gb link speed */
6386 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_EVENT_DATA1_NEW_LINK_SPEED_100MBPS_2_5GB \
6387 (UINT32_C(0x19) << 1)
6388 /* 10Gb link speed */
6389 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_EVENT_DATA1_NEW_LINK_SPEED_100MBPS_10GB \
6390 (UINT32_C(0x64) << 1)
6391 /* 20Mb link speed */
6392 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_EVENT_DATA1_NEW_LINK_SPEED_100MBPS_20GB \
6393 (UINT32_C(0xc8) << 1)
6394 /* 25Gb link speed */
6395 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_EVENT_DATA1_NEW_LINK_SPEED_100MBPS_25GB \
6396 (UINT32_C(0xfa) << 1)
6397 /* 40Gb link speed */
6398 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_EVENT_DATA1_NEW_LINK_SPEED_100MBPS_40GB \
6399 (UINT32_C(0x190) << 1)
6400 /* 50Gb link speed */
6401 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_EVENT_DATA1_NEW_LINK_SPEED_100MBPS_50GB \
6402 (UINT32_C(0x1f4) << 1)
6403 /* 100Gb link speed */
6404 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_EVENT_DATA1_NEW_LINK_SPEED_100MBPS_100GB \
6405 (UINT32_C(0x3e8) << 1)
6406 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_EVENT_DATA1_NEW_LINK_SPEED_100MBPS_LAST \
6407 HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_EVENT_DATA1_NEW_LINK_SPEED_100MBPS_100GB
6409 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_EVENT_DATA1_PORT_ID_MASK \
6410 UINT32_C(0xffff0000)
6411 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_EVENT_DATA1_PORT_ID_SFT \
6415 /* hwrm_async_event_cmpl_dcb_config_change (size:128b/16B) */
6416 struct hwrm_async_event_cmpl_dcb_config_change {
6419 * This field indicates the exact type of the completion.
6420 * By convention, the LSB identifies the length of the
6421 * record in 16B units. Even values indicate 16B
6422 * records. Odd values indicate 32B
6425 #define HWRM_ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_TYPE_MASK \
6427 #define HWRM_ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_TYPE_SFT 0
6428 /* HWRM Asynchronous Event Information */
6429 #define HWRM_ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_TYPE_HWRM_ASYNC_EVENT \
6431 #define HWRM_ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_TYPE_LAST \
6432 HWRM_ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_TYPE_HWRM_ASYNC_EVENT
6433 /* Identifiers of events. */
6435 /* DCB Configuration changed */
6436 #define HWRM_ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_EVENT_ID_DCB_CONFIG_CHANGE \
6438 #define HWRM_ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_EVENT_ID_LAST \
6439 HWRM_ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_EVENT_ID_DCB_CONFIG_CHANGE
6440 /* Event specific data */
6441 uint32_t event_data2;
6442 /* ETS configuration change */
6443 #define HWRM_ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_EVENT_DATA2_ETS \
6445 /* PFC configuration change */
6446 #define HWRM_ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_EVENT_DATA2_PFC \
6448 /* APP configuration change */
6449 #define HWRM_ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_EVENT_DATA2_APP \
6453 * This value is written by the NIC such that it will be different
6454 * for each pass through the completion queue. The even passes
6455 * will write 1. The odd passes will write 0.
6457 #define HWRM_ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_V \
6460 #define HWRM_ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_OPAQUE_MASK \
6462 #define HWRM_ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_OPAQUE_SFT 1
6463 /* 8-lsb timestamp from POR (100-msec resolution) */
6464 uint8_t timestamp_lo;
6465 /* 16-lsb timestamp from POR (100-msec resolution) */
6466 uint16_t timestamp_hi;
6467 /* Event specific data */
6468 uint32_t event_data1;
6470 #define HWRM_ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_EVENT_DATA1_PORT_ID_MASK \
6472 #define HWRM_ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_EVENT_DATA1_PORT_ID_SFT \
6474 /* Priority recommended for RoCE traffic */
6475 #define HWRM_ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_EVENT_DATA1_RECOMMEND_ROCE_PRIORITY_MASK \
6477 #define HWRM_ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_EVENT_DATA1_RECOMMEND_ROCE_PRIORITY_SFT \
6480 #define HWRM_ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_EVENT_DATA1_RECOMMEND_ROCE_PRIORITY_NONE \
6481 (UINT32_C(0xff) << 16)
6482 #define HWRM_ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_EVENT_DATA1_RECOMMEND_ROCE_PRIORITY_LAST \
6483 HWRM_ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_EVENT_DATA1_RECOMMEND_ROCE_PRIORITY_NONE
6484 /* Priority recommended for L2 traffic */
6485 #define HWRM_ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_EVENT_DATA1_RECOMMEND_L2_PRIORITY_MASK \
6486 UINT32_C(0xff000000)
6487 #define HWRM_ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_EVENT_DATA1_RECOMMEND_L2_PRIORITY_SFT \
6490 #define HWRM_ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_EVENT_DATA1_RECOMMEND_L2_PRIORITY_NONE \
6491 (UINT32_C(0xff) << 24)
6492 #define HWRM_ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_EVENT_DATA1_RECOMMEND_L2_PRIORITY_LAST \
6493 HWRM_ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_EVENT_DATA1_RECOMMEND_L2_PRIORITY_NONE
6496 /* hwrm_async_event_cmpl_port_conn_not_allowed (size:128b/16B) */
6497 struct hwrm_async_event_cmpl_port_conn_not_allowed {
6500 * This field indicates the exact type of the completion.
6501 * By convention, the LSB identifies the length of the
6502 * record in 16B units. Even values indicate 16B
6503 * records. Odd values indicate 32B
6506 #define HWRM_ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_TYPE_MASK \
6508 #define HWRM_ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_TYPE_SFT \
6510 /* HWRM Asynchronous Event Information */
6511 #define HWRM_ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_TYPE_HWRM_ASYNC_EVENT \
6513 #define HWRM_ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_TYPE_LAST \
6514 HWRM_ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_TYPE_HWRM_ASYNC_EVENT
6515 /* Identifiers of events. */
6517 /* Port connection not allowed */
6518 #define HWRM_ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_ID_PORT_CONN_NOT_ALLOWED \
6520 #define HWRM_ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_ID_LAST \
6521 HWRM_ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_ID_PORT_CONN_NOT_ALLOWED
6522 /* Event specific data */
6523 uint32_t event_data2;
6526 * This value is written by the NIC such that it will be different
6527 * for each pass through the completion queue. The even passes
6528 * will write 1. The odd passes will write 0.
6530 #define HWRM_ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_V \
6533 #define HWRM_ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_OPAQUE_MASK \
6535 #define HWRM_ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_OPAQUE_SFT 1
6536 /* 8-lsb timestamp from POR (100-msec resolution) */
6537 uint8_t timestamp_lo;
6538 /* 16-lsb timestamp from POR (100-msec resolution) */
6539 uint16_t timestamp_hi;
6540 /* Event specific data */
6541 uint32_t event_data1;
6543 #define HWRM_ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_PORT_ID_MASK \
6545 #define HWRM_ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_PORT_ID_SFT \
6548 * This value indicates the current port level enforcement policy
6549 * for the optics module when there is an optical module mismatch
6550 * and port is not connected.
6552 #define HWRM_ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_ENFORCEMENT_POLICY_MASK \
6554 #define HWRM_ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_ENFORCEMENT_POLICY_SFT \
6556 /* No enforcement */
6557 #define HWRM_ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_ENFORCEMENT_POLICY_NONE \
6558 (UINT32_C(0x0) << 16)
6559 /* Disable Transmit side Laser. */
6560 #define HWRM_ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_ENFORCEMENT_POLICY_DISABLETX \
6561 (UINT32_C(0x1) << 16)
6562 /* Raise a warning message. */
6563 #define HWRM_ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_ENFORCEMENT_POLICY_WARNINGMSG \
6564 (UINT32_C(0x2) << 16)
6565 /* Power down the module. */
6566 #define HWRM_ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_ENFORCEMENT_POLICY_PWRDOWN \
6567 (UINT32_C(0x3) << 16)
6568 #define HWRM_ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_ENFORCEMENT_POLICY_LAST \
6569 HWRM_ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_ENFORCEMENT_POLICY_PWRDOWN
6572 /* hwrm_async_event_cmpl_link_speed_cfg_not_allowed (size:128b/16B) */
6573 struct hwrm_async_event_cmpl_link_speed_cfg_not_allowed {
6576 * This field indicates the exact type of the completion.
6577 * By convention, the LSB identifies the length of the
6578 * record in 16B units. Even values indicate 16B
6579 * records. Odd values indicate 32B
6582 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_NOT_ALLOWED_TYPE_MASK \
6584 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_NOT_ALLOWED_TYPE_SFT \
6586 /* HWRM Asynchronous Event Information */
6587 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_NOT_ALLOWED_TYPE_HWRM_ASYNC_EVENT \
6589 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_NOT_ALLOWED_TYPE_LAST \
6590 HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_NOT_ALLOWED_TYPE_HWRM_ASYNC_EVENT
6591 /* Identifiers of events. */
6593 /* Link speed configuration was not allowed */
6594 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_NOT_ALLOWED_EVENT_ID_LINK_SPEED_CFG_NOT_ALLOWED \
6596 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_NOT_ALLOWED_EVENT_ID_LAST \
6597 HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_NOT_ALLOWED_EVENT_ID_LINK_SPEED_CFG_NOT_ALLOWED
6598 /* Event specific data */
6599 uint32_t event_data2;
6602 * This value is written by the NIC such that it will be different
6603 * for each pass through the completion queue. The even passes
6604 * will write 1. The odd passes will write 0.
6606 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_NOT_ALLOWED_V \
6609 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_NOT_ALLOWED_OPAQUE_MASK \
6611 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_NOT_ALLOWED_OPAQUE_SFT 1
6612 /* 8-lsb timestamp from POR (100-msec resolution) */
6613 uint8_t timestamp_lo;
6614 /* 16-lsb timestamp from POR (100-msec resolution) */
6615 uint16_t timestamp_hi;
6616 /* Event specific data */
6617 uint32_t event_data1;
6619 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_NOT_ALLOWED_EVENT_DATA1_PORT_ID_MASK \
6621 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_NOT_ALLOWED_EVENT_DATA1_PORT_ID_SFT \
6625 /* hwrm_async_event_cmpl_link_speed_cfg_change (size:128b/16B) */
6626 struct hwrm_async_event_cmpl_link_speed_cfg_change {
6629 * This field indicates the exact type of the completion.
6630 * By convention, the LSB identifies the length of the
6631 * record in 16B units. Even values indicate 16B
6632 * records. Odd values indicate 32B
6635 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_TYPE_MASK \
6637 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_TYPE_SFT \
6639 /* HWRM Asynchronous Event Information */
6640 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_TYPE_HWRM_ASYNC_EVENT \
6642 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_TYPE_LAST \
6643 HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_TYPE_HWRM_ASYNC_EVENT
6644 /* Identifiers of events. */
6646 /* Link speed configuration change */
6647 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_EVENT_ID_LINK_SPEED_CFG_CHANGE \
6649 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_EVENT_ID_LAST \
6650 HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_EVENT_ID_LINK_SPEED_CFG_CHANGE
6651 /* Event specific data */
6652 uint32_t event_data2;
6655 * This value is written by the NIC such that it will be different
6656 * for each pass through the completion queue. The even passes
6657 * will write 1. The odd passes will write 0.
6659 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_V \
6662 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_OPAQUE_MASK \
6664 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_OPAQUE_SFT 1
6665 /* 8-lsb timestamp from POR (100-msec resolution) */
6666 uint8_t timestamp_lo;
6667 /* 16-lsb timestamp from POR (100-msec resolution) */
6668 uint16_t timestamp_hi;
6669 /* Event specific data */
6670 uint32_t event_data1;
6672 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_EVENT_DATA1_PORT_ID_MASK \
6674 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_EVENT_DATA1_PORT_ID_SFT \
6677 * If set to 1, it indicates that the supported link speeds
6678 * configuration on the port has changed.
6679 * If set to 0, then there is no change in supported link speeds
6682 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_EVENT_DATA1_SUPPORTED_LINK_SPEEDS_CHANGE \
6685 * If set to 1, it indicates that the link speed configuration
6686 * on the port has become illegal or invalid.
6687 * If set to 0, then the link speed configuration on the port is
6690 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_EVENT_DATA1_ILLEGAL_LINK_SPEED_CFG \
6694 /* hwrm_async_event_cmpl_port_phy_cfg_change (size:128b/16B) */
6695 struct hwrm_async_event_cmpl_port_phy_cfg_change {
6698 * This field indicates the exact type of the completion.
6699 * By convention, the LSB identifies the length of the
6700 * record in 16B units. Even values indicate 16B
6701 * records. Odd values indicate 32B
6704 #define HWRM_ASYNC_EVENT_CMPL_PORT_PHY_CFG_CHANGE_TYPE_MASK \
6706 #define HWRM_ASYNC_EVENT_CMPL_PORT_PHY_CFG_CHANGE_TYPE_SFT \
6708 /* HWRM Asynchronous Event Information */
6709 #define HWRM_ASYNC_EVENT_CMPL_PORT_PHY_CFG_CHANGE_TYPE_HWRM_ASYNC_EVENT \
6711 #define HWRM_ASYNC_EVENT_CMPL_PORT_PHY_CFG_CHANGE_TYPE_LAST \
6712 HWRM_ASYNC_EVENT_CMPL_PORT_PHY_CFG_CHANGE_TYPE_HWRM_ASYNC_EVENT
6713 /* Identifiers of events. */
6715 /* Port PHY configuration change */
6716 #define HWRM_ASYNC_EVENT_CMPL_PORT_PHY_CFG_CHANGE_EVENT_ID_PORT_PHY_CFG_CHANGE \
6718 #define HWRM_ASYNC_EVENT_CMPL_PORT_PHY_CFG_CHANGE_EVENT_ID_LAST \
6719 HWRM_ASYNC_EVENT_CMPL_PORT_PHY_CFG_CHANGE_EVENT_ID_PORT_PHY_CFG_CHANGE
6720 /* Event specific data */
6721 uint32_t event_data2;
6724 * This value is written by the NIC such that it will be different
6725 * for each pass through the completion queue. The even passes
6726 * will write 1. The odd passes will write 0.
6728 #define HWRM_ASYNC_EVENT_CMPL_PORT_PHY_CFG_CHANGE_V \
6731 #define HWRM_ASYNC_EVENT_CMPL_PORT_PHY_CFG_CHANGE_OPAQUE_MASK \
6733 #define HWRM_ASYNC_EVENT_CMPL_PORT_PHY_CFG_CHANGE_OPAQUE_SFT 1
6734 /* 8-lsb timestamp from POR (100-msec resolution) */
6735 uint8_t timestamp_lo;
6736 /* 16-lsb timestamp from POR (100-msec resolution) */
6737 uint16_t timestamp_hi;
6738 /* Event specific data */
6739 uint32_t event_data1;
6741 #define HWRM_ASYNC_EVENT_CMPL_PORT_PHY_CFG_CHANGE_EVENT_DATA1_PORT_ID_MASK \
6743 #define HWRM_ASYNC_EVENT_CMPL_PORT_PHY_CFG_CHANGE_EVENT_DATA1_PORT_ID_SFT \
6746 * If set to 1, it indicates that the FEC
6747 * configuration on the port has changed.
6748 * If set to 0, then there is no change in FEC configuration.
6750 #define HWRM_ASYNC_EVENT_CMPL_PORT_PHY_CFG_CHANGE_EVENT_DATA1_FEC_CFG_CHANGE \
6753 * If set to 1, it indicates that the EEE configuration
6754 * on the port has changed.
6755 * If set to 0, then there is no change in EEE configuration
6758 #define HWRM_ASYNC_EVENT_CMPL_PORT_PHY_CFG_CHANGE_EVENT_DATA1_EEE_CFG_CHANGE \
6761 * If set to 1, it indicates that the pause configuration
6762 * on the PHY has changed.
6763 * If set to 0, then there is no change in the pause
6764 * configuration on the PHY.
6766 #define HWRM_ASYNC_EVENT_CMPL_PORT_PHY_CFG_CHANGE_EVENT_DATA1_PAUSE_CFG_CHANGE \
6770 /* hwrm_async_event_cmpl_reset_notify (size:128b/16B) */
6771 struct hwrm_async_event_cmpl_reset_notify {
6774 * This field indicates the exact type of the completion.
6775 * By convention, the LSB identifies the length of the
6776 * record in 16B units. Even values indicate 16B
6777 * records. Odd values indicate 32B
6780 #define HWRM_ASYNC_EVENT_CMPL_RESET_NOTIFY_TYPE_MASK \
6782 #define HWRM_ASYNC_EVENT_CMPL_RESET_NOTIFY_TYPE_SFT 0
6783 /* HWRM Asynchronous Event Information */
6784 #define HWRM_ASYNC_EVENT_CMPL_RESET_NOTIFY_TYPE_HWRM_ASYNC_EVENT \
6786 #define HWRM_ASYNC_EVENT_CMPL_RESET_NOTIFY_TYPE_LAST \
6787 HWRM_ASYNC_EVENT_CMPL_RESET_NOTIFY_TYPE_HWRM_ASYNC_EVENT
6788 /* Identifiers of events. */
6790 /* Notify clients of imminent reset. */
6791 #define HWRM_ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_ID_RESET_NOTIFY \
6793 #define HWRM_ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_ID_LAST \
6794 HWRM_ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_ID_RESET_NOTIFY
6795 /* Event specific data */
6796 uint32_t event_data2;
6799 * This value is written by the NIC such that it will be different
6800 * for each pass through the completion queue. The even passes
6801 * will write 1. The odd passes will write 0.
6803 #define HWRM_ASYNC_EVENT_CMPL_RESET_NOTIFY_V UINT32_C(0x1)
6805 #define HWRM_ASYNC_EVENT_CMPL_RESET_NOTIFY_OPAQUE_MASK UINT32_C(0xfe)
6806 #define HWRM_ASYNC_EVENT_CMPL_RESET_NOTIFY_OPAQUE_SFT 1
6808 * 8-lsb timestamp (100-msec resolution)
6809 * The Minimum time required for the Firmware readiness after sending this
6810 * notification to the driver instances.
6812 uint8_t timestamp_lo;
6814 * 16-lsb timestamp (100-msec resolution)
6815 * The Maximum Firmware Reset bail out value in the order of 100
6816 * milli seconds. The driver instances will use this value to re-initiate the
6817 * registration process again if the core firmware didn’t set the ready
6820 uint16_t timestamp_hi;
6821 /* Event specific data */
6822 uint32_t event_data1;
6823 /* Indicates driver action requested */
6824 #define HWRM_ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_DRIVER_ACTION_MASK \
6826 #define HWRM_ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_DRIVER_ACTION_SFT \
6829 * If set to 1, it indicates that the l2 client should
6830 * stop sending in band traffic to Nitro.
6831 * if set to 0, there is no change in L2 client behavior.
6833 #define HWRM_ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_DRIVER_ACTION_DRIVER_STOP_TX_QUEUE \
6836 * If set to 1, it indicates that the L2 client should
6837 * bring down the interface.
6838 * If set to 0, then there is no change in L2 client behavior.
6840 #define HWRM_ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_DRIVER_ACTION_DRIVER_IFDOWN \
6842 #define HWRM_ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_DRIVER_ACTION_LAST \
6843 HWRM_ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_DRIVER_ACTION_DRIVER_IFDOWN
6844 /* Indicates reason for reset. */
6845 #define HWRM_ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_REASON_CODE_MASK \
6847 #define HWRM_ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_REASON_CODE_SFT \
6849 /* A management client has requested reset. */
6850 #define HWRM_ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_REASON_CODE_MANAGEMENT_RESET_REQUEST \
6851 (UINT32_C(0x1) << 8)
6852 /* A fatal firmware exception has occurred. */
6853 #define HWRM_ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_REASON_CODE_FW_EXCEPTION_FATAL \
6854 (UINT32_C(0x2) << 8)
6855 /* A non-fatal firmware exception has occurred. */
6856 #define HWRM_ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_REASON_CODE_FW_EXCEPTION_NON_FATAL \
6857 (UINT32_C(0x3) << 8)
6858 #define HWRM_ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_REASON_CODE_LAST \
6859 HWRM_ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_REASON_CODE_FW_EXCEPTION_NON_FATAL
6861 * Minimum time before driver should attempt access - units 100ms ticks.
6864 #define HWRM_ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_DELAY_IN_100MS_TICKS_MASK \
6865 UINT32_C(0xffff0000)
6866 #define HWRM_ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_DELAY_IN_100MS_TICKS_SFT \
6870 /* hwrm_async_event_cmpl_error_recovery (size:128b/16B) */
6871 struct hwrm_async_event_cmpl_error_recovery {
6874 * This field indicates the exact type of the completion.
6875 * By convention, the LSB identifies the length of the
6876 * record in 16B units. Even values indicate 16B
6877 * records. Odd values indicate 32B
6880 #define HWRM_ASYNC_EVENT_CMPL_ERROR_RECOVERY_TYPE_MASK \
6882 #define HWRM_ASYNC_EVENT_CMPL_ERROR_RECOVERY_TYPE_SFT 0
6883 /* HWRM Asynchronous Event Information */
6884 #define HWRM_ASYNC_EVENT_CMPL_ERROR_RECOVERY_TYPE_HWRM_ASYNC_EVENT \
6886 #define HWRM_ASYNC_EVENT_CMPL_ERROR_RECOVERY_TYPE_LAST \
6887 HWRM_ASYNC_EVENT_CMPL_ERROR_RECOVERY_TYPE_HWRM_ASYNC_EVENT
6888 /* Identifiers of events. */
6891 * This async notification message can be used for selecting or
6892 * deselecting master function for error recovery,
6893 * and to communicate to all the functions whether error recovery
6894 * was enabled/disabled.
6896 #define HWRM_ASYNC_EVENT_CMPL_ERROR_RECOVERY_EVENT_ID_ERROR_RECOVERY \
6898 #define HWRM_ASYNC_EVENT_CMPL_ERROR_RECOVERY_EVENT_ID_LAST \
6899 HWRM_ASYNC_EVENT_CMPL_ERROR_RECOVERY_EVENT_ID_ERROR_RECOVERY
6900 /* Event specific data */
6901 uint32_t event_data2;
6904 * This value is written by the NIC such that it will be different
6905 * for each pass through the completion queue. The even passes
6906 * will write 1. The odd passes will write 0.
6908 #define HWRM_ASYNC_EVENT_CMPL_ERROR_RECOVERY_V UINT32_C(0x1)
6910 #define HWRM_ASYNC_EVENT_CMPL_ERROR_RECOVERY_OPAQUE_MASK UINT32_C(0xfe)
6911 #define HWRM_ASYNC_EVENT_CMPL_ERROR_RECOVERY_OPAQUE_SFT 1
6912 /* 8-lsb timestamp (100-msec resolution) */
6913 uint8_t timestamp_lo;
6914 /* 16-lsb timestamp (100-msec resolution) */
6915 uint16_t timestamp_hi;
6916 /* Event specific data */
6917 uint32_t event_data1;
6918 /* Indicates driver action requested */
6919 #define HWRM_ASYNC_EVENT_CMPL_ERROR_RECOVERY_EVENT_DATA1_FLAGS_MASK \
6921 #define HWRM_ASYNC_EVENT_CMPL_ERROR_RECOVERY_EVENT_DATA1_FLAGS_SFT \
6924 * If set to 1, this function is selected as Master function.
6925 * This function has responsibility to do 'chip reset' when it
6926 * detects a fatal error. If set to 0, master function functionality
6927 * is disabled on this function.
6929 #define HWRM_ASYNC_EVENT_CMPL_ERROR_RECOVERY_EVENT_DATA1_FLAGS_MASTER_FUNC \
6932 * If set to 1, error recovery is enabled.
6933 * If set to 0, error recovery is disabled.
6935 #define HWRM_ASYNC_EVENT_CMPL_ERROR_RECOVERY_EVENT_DATA1_FLAGS_RECOVERY_ENABLED \
6939 /* hwrm_async_event_cmpl_func_drvr_unload (size:128b/16B) */
6940 struct hwrm_async_event_cmpl_func_drvr_unload {
6943 * This field indicates the exact type of the completion.
6944 * By convention, the LSB identifies the length of the
6945 * record in 16B units. Even values indicate 16B
6946 * records. Odd values indicate 32B
6949 #define HWRM_ASYNC_EVENT_CMPL_FUNC_DRVR_UNLOAD_TYPE_MASK \
6951 #define HWRM_ASYNC_EVENT_CMPL_FUNC_DRVR_UNLOAD_TYPE_SFT 0
6952 /* HWRM Asynchronous Event Information */
6953 #define HWRM_ASYNC_EVENT_CMPL_FUNC_DRVR_UNLOAD_TYPE_HWRM_ASYNC_EVENT \
6955 #define HWRM_ASYNC_EVENT_CMPL_FUNC_DRVR_UNLOAD_TYPE_LAST \
6956 HWRM_ASYNC_EVENT_CMPL_FUNC_DRVR_UNLOAD_TYPE_HWRM_ASYNC_EVENT
6957 /* Identifiers of events. */
6959 /* Function driver unloaded */
6960 #define HWRM_ASYNC_EVENT_CMPL_FUNC_DRVR_UNLOAD_EVENT_ID_FUNC_DRVR_UNLOAD \
6962 #define HWRM_ASYNC_EVENT_CMPL_FUNC_DRVR_UNLOAD_EVENT_ID_LAST \
6963 HWRM_ASYNC_EVENT_CMPL_FUNC_DRVR_UNLOAD_EVENT_ID_FUNC_DRVR_UNLOAD
6964 /* Event specific data */
6965 uint32_t event_data2;
6968 * This value is written by the NIC such that it will be different
6969 * for each pass through the completion queue. The even passes
6970 * will write 1. The odd passes will write 0.
6972 #define HWRM_ASYNC_EVENT_CMPL_FUNC_DRVR_UNLOAD_V UINT32_C(0x1)
6974 #define HWRM_ASYNC_EVENT_CMPL_FUNC_DRVR_UNLOAD_OPAQUE_MASK \
6976 #define HWRM_ASYNC_EVENT_CMPL_FUNC_DRVR_UNLOAD_OPAQUE_SFT 1
6977 /* 8-lsb timestamp from POR (100-msec resolution) */
6978 uint8_t timestamp_lo;
6979 /* 16-lsb timestamp from POR (100-msec resolution) */
6980 uint16_t timestamp_hi;
6981 /* Event specific data */
6982 uint32_t event_data1;
6984 #define HWRM_ASYNC_EVENT_CMPL_FUNC_DRVR_UNLOAD_EVENT_DATA1_FUNC_ID_MASK \
6986 #define HWRM_ASYNC_EVENT_CMPL_FUNC_DRVR_UNLOAD_EVENT_DATA1_FUNC_ID_SFT \
6990 /* hwrm_async_event_cmpl_func_drvr_load (size:128b/16B) */
6991 struct hwrm_async_event_cmpl_func_drvr_load {
6994 * This field indicates the exact type of the completion.
6995 * By convention, the LSB identifies the length of the
6996 * record in 16B units. Even values indicate 16B
6997 * records. Odd values indicate 32B
7000 #define HWRM_ASYNC_EVENT_CMPL_FUNC_DRVR_LOAD_TYPE_MASK \
7002 #define HWRM_ASYNC_EVENT_CMPL_FUNC_DRVR_LOAD_TYPE_SFT 0
7003 /* HWRM Asynchronous Event Information */
7004 #define HWRM_ASYNC_EVENT_CMPL_FUNC_DRVR_LOAD_TYPE_HWRM_ASYNC_EVENT \
7006 #define HWRM_ASYNC_EVENT_CMPL_FUNC_DRVR_LOAD_TYPE_LAST \
7007 HWRM_ASYNC_EVENT_CMPL_FUNC_DRVR_LOAD_TYPE_HWRM_ASYNC_EVENT
7008 /* Identifiers of events. */
7010 /* Function driver loaded */
7011 #define HWRM_ASYNC_EVENT_CMPL_FUNC_DRVR_LOAD_EVENT_ID_FUNC_DRVR_LOAD \
7013 #define HWRM_ASYNC_EVENT_CMPL_FUNC_DRVR_LOAD_EVENT_ID_LAST \
7014 HWRM_ASYNC_EVENT_CMPL_FUNC_DRVR_LOAD_EVENT_ID_FUNC_DRVR_LOAD
7015 /* Event specific data */
7016 uint32_t event_data2;
7019 * This value is written by the NIC such that it will be different
7020 * for each pass through the completion queue. The even passes
7021 * will write 1. The odd passes will write 0.
7023 #define HWRM_ASYNC_EVENT_CMPL_FUNC_DRVR_LOAD_V UINT32_C(0x1)
7025 #define HWRM_ASYNC_EVENT_CMPL_FUNC_DRVR_LOAD_OPAQUE_MASK UINT32_C(0xfe)
7026 #define HWRM_ASYNC_EVENT_CMPL_FUNC_DRVR_LOAD_OPAQUE_SFT 1
7027 /* 8-lsb timestamp from POR (100-msec resolution) */
7028 uint8_t timestamp_lo;
7029 /* 16-lsb timestamp from POR (100-msec resolution) */
7030 uint16_t timestamp_hi;
7031 /* Event specific data */
7032 uint32_t event_data1;
7034 #define HWRM_ASYNC_EVENT_CMPL_FUNC_DRVR_LOAD_EVENT_DATA1_FUNC_ID_MASK \
7036 #define HWRM_ASYNC_EVENT_CMPL_FUNC_DRVR_LOAD_EVENT_DATA1_FUNC_ID_SFT 0
7039 /* hwrm_async_event_cmpl_func_flr_proc_cmplt (size:128b/16B) */
7040 struct hwrm_async_event_cmpl_func_flr_proc_cmplt {
7043 * This field indicates the exact type of the completion.
7044 * By convention, the LSB identifies the length of the
7045 * record in 16B units. Even values indicate 16B
7046 * records. Odd values indicate 32B
7049 #define HWRM_ASYNC_EVENT_CMPL_FUNC_FLR_PROC_CMPLT_TYPE_MASK \
7051 #define HWRM_ASYNC_EVENT_CMPL_FUNC_FLR_PROC_CMPLT_TYPE_SFT \
7053 /* HWRM Asynchronous Event Information */
7054 #define HWRM_ASYNC_EVENT_CMPL_FUNC_FLR_PROC_CMPLT_TYPE_HWRM_ASYNC_EVENT \
7056 #define HWRM_ASYNC_EVENT_CMPL_FUNC_FLR_PROC_CMPLT_TYPE_LAST \
7057 HWRM_ASYNC_EVENT_CMPL_FUNC_FLR_PROC_CMPLT_TYPE_HWRM_ASYNC_EVENT
7058 /* Identifiers of events. */
7060 /* Function FLR related processing has completed */
7061 #define HWRM_ASYNC_EVENT_CMPL_FUNC_FLR_PROC_CMPLT_EVENT_ID_FUNC_FLR_PROC_CMPLT \
7063 #define HWRM_ASYNC_EVENT_CMPL_FUNC_FLR_PROC_CMPLT_EVENT_ID_LAST \
7064 HWRM_ASYNC_EVENT_CMPL_FUNC_FLR_PROC_CMPLT_EVENT_ID_FUNC_FLR_PROC_CMPLT
7065 /* Event specific data */
7066 uint32_t event_data2;
7069 * This value is written by the NIC such that it will be different
7070 * for each pass through the completion queue. The even passes
7071 * will write 1. The odd passes will write 0.
7073 #define HWRM_ASYNC_EVENT_CMPL_FUNC_FLR_PROC_CMPLT_V \
7076 #define HWRM_ASYNC_EVENT_CMPL_FUNC_FLR_PROC_CMPLT_OPAQUE_MASK \
7078 #define HWRM_ASYNC_EVENT_CMPL_FUNC_FLR_PROC_CMPLT_OPAQUE_SFT 1
7079 /* 8-lsb timestamp from POR (100-msec resolution) */
7080 uint8_t timestamp_lo;
7081 /* 16-lsb timestamp from POR (100-msec resolution) */
7082 uint16_t timestamp_hi;
7083 /* Event specific data */
7084 uint32_t event_data1;
7086 #define HWRM_ASYNC_EVENT_CMPL_FUNC_FLR_PROC_CMPLT_EVENT_DATA1_FUNC_ID_MASK \
7088 #define HWRM_ASYNC_EVENT_CMPL_FUNC_FLR_PROC_CMPLT_EVENT_DATA1_FUNC_ID_SFT \
7092 /* hwrm_async_event_cmpl_pf_drvr_unload (size:128b/16B) */
7093 struct hwrm_async_event_cmpl_pf_drvr_unload {
7096 * This field indicates the exact type of the completion.
7097 * By convention, the LSB identifies the length of the
7098 * record in 16B units. Even values indicate 16B
7099 * records. Odd values indicate 32B
7102 #define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_UNLOAD_TYPE_MASK \
7104 #define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_UNLOAD_TYPE_SFT 0
7105 /* HWRM Asynchronous Event Information */
7106 #define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_UNLOAD_TYPE_HWRM_ASYNC_EVENT \
7108 #define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_UNLOAD_TYPE_LAST \
7109 HWRM_ASYNC_EVENT_CMPL_PF_DRVR_UNLOAD_TYPE_HWRM_ASYNC_EVENT
7110 /* Identifiers of events. */
7112 /* PF driver unloaded */
7113 #define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_UNLOAD_EVENT_ID_PF_DRVR_UNLOAD \
7115 #define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_UNLOAD_EVENT_ID_LAST \
7116 HWRM_ASYNC_EVENT_CMPL_PF_DRVR_UNLOAD_EVENT_ID_PF_DRVR_UNLOAD
7117 /* Event specific data */
7118 uint32_t event_data2;
7121 * This value is written by the NIC such that it will be different
7122 * for each pass through the completion queue. The even passes
7123 * will write 1. The odd passes will write 0.
7125 #define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_UNLOAD_V UINT32_C(0x1)
7127 #define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_UNLOAD_OPAQUE_MASK UINT32_C(0xfe)
7128 #define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_UNLOAD_OPAQUE_SFT 1
7129 /* 8-lsb timestamp from POR (100-msec resolution) */
7130 uint8_t timestamp_lo;
7131 /* 16-lsb timestamp from POR (100-msec resolution) */
7132 uint16_t timestamp_hi;
7133 /* Event specific data */
7134 uint32_t event_data1;
7136 #define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_UNLOAD_EVENT_DATA1_FUNC_ID_MASK \
7138 #define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_UNLOAD_EVENT_DATA1_FUNC_ID_SFT 0
7139 /* Indicates the physical port this pf belongs to */
7140 #define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_UNLOAD_EVENT_DATA1_PORT_MASK \
7142 #define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_UNLOAD_EVENT_DATA1_PORT_SFT 16
7145 /* hwrm_async_event_cmpl_pf_drvr_load (size:128b/16B) */
7146 struct hwrm_async_event_cmpl_pf_drvr_load {
7149 * This field indicates the exact type of the completion.
7150 * By convention, the LSB identifies the length of the
7151 * record in 16B units. Even values indicate 16B
7152 * records. Odd values indicate 32B
7155 #define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_LOAD_TYPE_MASK \
7157 #define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_LOAD_TYPE_SFT 0
7158 /* HWRM Asynchronous Event Information */
7159 #define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_LOAD_TYPE_HWRM_ASYNC_EVENT \
7161 #define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_LOAD_TYPE_LAST \
7162 HWRM_ASYNC_EVENT_CMPL_PF_DRVR_LOAD_TYPE_HWRM_ASYNC_EVENT
7163 /* Identifiers of events. */
7165 /* PF driver loaded */
7166 #define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_LOAD_EVENT_ID_PF_DRVR_LOAD \
7168 #define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_LOAD_EVENT_ID_LAST \
7169 HWRM_ASYNC_EVENT_CMPL_PF_DRVR_LOAD_EVENT_ID_PF_DRVR_LOAD
7170 /* Event specific data */
7171 uint32_t event_data2;
7174 * This value is written by the NIC such that it will be different
7175 * for each pass through the completion queue. The even passes
7176 * will write 1. The odd passes will write 0.
7178 #define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_LOAD_V UINT32_C(0x1)
7180 #define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_LOAD_OPAQUE_MASK UINT32_C(0xfe)
7181 #define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_LOAD_OPAQUE_SFT 1
7182 /* 8-lsb timestamp from POR (100-msec resolution) */
7183 uint8_t timestamp_lo;
7184 /* 16-lsb timestamp from POR (100-msec resolution) */
7185 uint16_t timestamp_hi;
7186 /* Event specific data */
7187 uint32_t event_data1;
7189 #define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_LOAD_EVENT_DATA1_FUNC_ID_MASK \
7191 #define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_LOAD_EVENT_DATA1_FUNC_ID_SFT 0
7192 /* Indicates the physical port this pf belongs to */
7193 #define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_LOAD_EVENT_DATA1_PORT_MASK \
7195 #define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_LOAD_EVENT_DATA1_PORT_SFT 16
7198 /* hwrm_async_event_cmpl_vf_flr (size:128b/16B) */
7199 struct hwrm_async_event_cmpl_vf_flr {
7202 * This field indicates the exact type of the completion.
7203 * By convention, the LSB identifies the length of the
7204 * record in 16B units. Even values indicate 16B
7205 * records. Odd values indicate 32B
7208 #define HWRM_ASYNC_EVENT_CMPL_VF_FLR_TYPE_MASK \
7210 #define HWRM_ASYNC_EVENT_CMPL_VF_FLR_TYPE_SFT 0
7211 /* HWRM Asynchronous Event Information */
7212 #define HWRM_ASYNC_EVENT_CMPL_VF_FLR_TYPE_HWRM_ASYNC_EVENT \
7214 #define HWRM_ASYNC_EVENT_CMPL_VF_FLR_TYPE_LAST \
7215 HWRM_ASYNC_EVENT_CMPL_VF_FLR_TYPE_HWRM_ASYNC_EVENT
7216 /* Identifiers of events. */
7218 /* VF Function Level Reset (FLR) */
7219 #define HWRM_ASYNC_EVENT_CMPL_VF_FLR_EVENT_ID_VF_FLR UINT32_C(0x30)
7220 #define HWRM_ASYNC_EVENT_CMPL_VF_FLR_EVENT_ID_LAST \
7221 HWRM_ASYNC_EVENT_CMPL_VF_FLR_EVENT_ID_VF_FLR
7222 /* Event specific data */
7223 uint32_t event_data2;
7226 * This value is written by the NIC such that it will be different
7227 * for each pass through the completion queue. The even passes
7228 * will write 1. The odd passes will write 0.
7230 #define HWRM_ASYNC_EVENT_CMPL_VF_FLR_V UINT32_C(0x1)
7232 #define HWRM_ASYNC_EVENT_CMPL_VF_FLR_OPAQUE_MASK UINT32_C(0xfe)
7233 #define HWRM_ASYNC_EVENT_CMPL_VF_FLR_OPAQUE_SFT 1
7234 /* 8-lsb timestamp from POR (100-msec resolution) */
7235 uint8_t timestamp_lo;
7236 /* 16-lsb timestamp from POR (100-msec resolution) */
7237 uint16_t timestamp_hi;
7238 /* Event specific data */
7239 uint32_t event_data1;
7241 #define HWRM_ASYNC_EVENT_CMPL_VF_FLR_EVENT_DATA1_VF_ID_MASK \
7243 #define HWRM_ASYNC_EVENT_CMPL_VF_FLR_EVENT_DATA1_VF_ID_SFT 0
7244 /* Indicates the physical function this event occurred on. */
7245 #define HWRM_ASYNC_EVENT_CMPL_VF_FLR_EVENT_DATA1_PF_ID_MASK \
7247 #define HWRM_ASYNC_EVENT_CMPL_VF_FLR_EVENT_DATA1_PF_ID_SFT 16
7250 /* hwrm_async_event_cmpl_vf_mac_addr_change (size:128b/16B) */
7251 struct hwrm_async_event_cmpl_vf_mac_addr_change {
7254 * This field indicates the exact type of the completion.
7255 * By convention, the LSB identifies the length of the
7256 * record in 16B units. Even values indicate 16B
7257 * records. Odd values indicate 32B
7260 #define HWRM_ASYNC_EVENT_CMPL_VF_MAC_ADDR_CHANGE_TYPE_MASK \
7262 #define HWRM_ASYNC_EVENT_CMPL_VF_MAC_ADDR_CHANGE_TYPE_SFT 0
7263 /* HWRM Asynchronous Event Information */
7264 #define HWRM_ASYNC_EVENT_CMPL_VF_MAC_ADDR_CHANGE_TYPE_HWRM_ASYNC_EVENT \
7266 #define HWRM_ASYNC_EVENT_CMPL_VF_MAC_ADDR_CHANGE_TYPE_LAST \
7267 HWRM_ASYNC_EVENT_CMPL_VF_MAC_ADDR_CHANGE_TYPE_HWRM_ASYNC_EVENT
7268 /* Identifiers of events. */
7270 /* VF MAC Address Change */
7271 #define HWRM_ASYNC_EVENT_CMPL_VF_MAC_ADDR_CHANGE_EVENT_ID_VF_MAC_ADDR_CHANGE \
7273 #define HWRM_ASYNC_EVENT_CMPL_VF_MAC_ADDR_CHANGE_EVENT_ID_LAST \
7274 HWRM_ASYNC_EVENT_CMPL_VF_MAC_ADDR_CHANGE_EVENT_ID_VF_MAC_ADDR_CHANGE
7275 /* Event specific data */
7276 uint32_t event_data2;
7279 * This value is written by the NIC such that it will be different
7280 * for each pass through the completion queue. The even passes
7281 * will write 1. The odd passes will write 0.
7283 #define HWRM_ASYNC_EVENT_CMPL_VF_MAC_ADDR_CHANGE_V \
7286 #define HWRM_ASYNC_EVENT_CMPL_VF_MAC_ADDR_CHANGE_OPAQUE_MASK \
7288 #define HWRM_ASYNC_EVENT_CMPL_VF_MAC_ADDR_CHANGE_OPAQUE_SFT 1
7289 /* 8-lsb timestamp from POR (100-msec resolution) */
7290 uint8_t timestamp_lo;
7291 /* 16-lsb timestamp from POR (100-msec resolution) */
7292 uint16_t timestamp_hi;
7293 /* Event specific data */
7294 uint32_t event_data1;
7296 #define HWRM_ASYNC_EVENT_CMPL_VF_MAC_ADDR_CHANGE_EVENT_DATA1_VF_ID_MASK \
7298 #define HWRM_ASYNC_EVENT_CMPL_VF_MAC_ADDR_CHANGE_EVENT_DATA1_VF_ID_SFT \
7302 /* hwrm_async_event_cmpl_pf_vf_comm_status_change (size:128b/16B) */
7303 struct hwrm_async_event_cmpl_pf_vf_comm_status_change {
7306 * This field indicates the exact type of the completion.
7307 * By convention, the LSB identifies the length of the
7308 * record in 16B units. Even values indicate 16B
7309 * records. Odd values indicate 32B
7312 #define HWRM_ASYNC_EVENT_CMPL_PF_VF_COMM_STATUS_CHANGE_TYPE_MASK \
7314 #define HWRM_ASYNC_EVENT_CMPL_PF_VF_COMM_STATUS_CHANGE_TYPE_SFT \
7316 /* HWRM Asynchronous Event Information */
7317 #define HWRM_ASYNC_EVENT_CMPL_PF_VF_COMM_STATUS_CHANGE_TYPE_HWRM_ASYNC_EVENT \
7319 #define HWRM_ASYNC_EVENT_CMPL_PF_VF_COMM_STATUS_CHANGE_TYPE_LAST \
7320 HWRM_ASYNC_EVENT_CMPL_PF_VF_COMM_STATUS_CHANGE_TYPE_HWRM_ASYNC_EVENT
7321 /* Identifiers of events. */
7323 /* PF-VF communication channel status change. */
7324 #define HWRM_ASYNC_EVENT_CMPL_PF_VF_COMM_STATUS_CHANGE_EVENT_ID_PF_VF_COMM_STATUS_CHANGE \
7326 #define HWRM_ASYNC_EVENT_CMPL_PF_VF_COMM_STATUS_CHANGE_EVENT_ID_LAST \
7327 HWRM_ASYNC_EVENT_CMPL_PF_VF_COMM_STATUS_CHANGE_EVENT_ID_PF_VF_COMM_STATUS_CHANGE
7328 /* Event specific data */
7329 uint32_t event_data2;
7332 * This value is written by the NIC such that it will be different
7333 * for each pass through the completion queue. The even passes
7334 * will write 1. The odd passes will write 0.
7336 #define HWRM_ASYNC_EVENT_CMPL_PF_VF_COMM_STATUS_CHANGE_V \
7339 #define HWRM_ASYNC_EVENT_CMPL_PF_VF_COMM_STATUS_CHANGE_OPAQUE_MASK \
7341 #define HWRM_ASYNC_EVENT_CMPL_PF_VF_COMM_STATUS_CHANGE_OPAQUE_SFT 1
7342 /* 8-lsb timestamp from POR (100-msec resolution) */
7343 uint8_t timestamp_lo;
7344 /* 16-lsb timestamp from POR (100-msec resolution) */
7345 uint16_t timestamp_hi;
7346 /* Event specific data */
7347 uint32_t event_data1;
7349 * If this bit is set to 1, then it indicates that the PF-VF
7350 * communication was lost and it is established.
7351 * If this bit set to 0, then it indicates that the PF-VF
7352 * communication was established and it is lost.
7354 #define HWRM_ASYNC_EVENT_CMPL_PF_VF_COMM_STATUS_CHANGE_EVENT_DATA1_COMM_ESTABLISHED \
7358 /* hwrm_async_event_cmpl_vf_cfg_change (size:128b/16B) */
7359 struct hwrm_async_event_cmpl_vf_cfg_change {
7362 * This field indicates the exact type of the completion.
7363 * By convention, the LSB identifies the length of the
7364 * record in 16B units. Even values indicate 16B
7365 * records. Odd values indicate 32B
7368 #define HWRM_ASYNC_EVENT_CMPL_VF_CFG_CHANGE_TYPE_MASK \
7370 #define HWRM_ASYNC_EVENT_CMPL_VF_CFG_CHANGE_TYPE_SFT 0
7371 /* HWRM Asynchronous Event Information */
7372 #define HWRM_ASYNC_EVENT_CMPL_VF_CFG_CHANGE_TYPE_HWRM_ASYNC_EVENT \
7374 #define HWRM_ASYNC_EVENT_CMPL_VF_CFG_CHANGE_TYPE_LAST \
7375 HWRM_ASYNC_EVENT_CMPL_VF_CFG_CHANGE_TYPE_HWRM_ASYNC_EVENT
7376 /* Identifiers of events. */
7378 /* VF Configuration Change */
7379 #define HWRM_ASYNC_EVENT_CMPL_VF_CFG_CHANGE_EVENT_ID_VF_CFG_CHANGE \
7381 #define HWRM_ASYNC_EVENT_CMPL_VF_CFG_CHANGE_EVENT_ID_LAST \
7382 HWRM_ASYNC_EVENT_CMPL_VF_CFG_CHANGE_EVENT_ID_VF_CFG_CHANGE
7383 /* Event specific data */
7384 uint32_t event_data2;
7387 * This value is written by the NIC such that it will be different
7388 * for each pass through the completion queue. The even passes
7389 * will write 1. The odd passes will write 0.
7391 #define HWRM_ASYNC_EVENT_CMPL_VF_CFG_CHANGE_V UINT32_C(0x1)
7393 #define HWRM_ASYNC_EVENT_CMPL_VF_CFG_CHANGE_OPAQUE_MASK UINT32_C(0xfe)
7394 #define HWRM_ASYNC_EVENT_CMPL_VF_CFG_CHANGE_OPAQUE_SFT 1
7395 /* 8-lsb timestamp from POR (100-msec resolution) */
7396 uint8_t timestamp_lo;
7397 /* 16-lsb timestamp from POR (100-msec resolution) */
7398 uint16_t timestamp_hi;
7400 * Each flag provided in this field indicates a specific VF
7401 * configuration change. At least one of these flags shall be set to 1
7402 * when an asynchronous event completion of this type is provided
7405 uint32_t event_data1;
7407 * If this bit is set to 1, then the value of MTU
7408 * was changed on this VF.
7409 * If set to 0, then this bit should be ignored.
7411 #define HWRM_ASYNC_EVENT_CMPL_VF_CFG_CHANGE_EVENT_DATA1_MTU_CHANGE \
7414 * If this bit is set to 1, then the value of MRU
7415 * was changed on this VF.
7416 * If set to 0, then this bit should be ignored.
7418 #define HWRM_ASYNC_EVENT_CMPL_VF_CFG_CHANGE_EVENT_DATA1_MRU_CHANGE \
7421 * If this bit is set to 1, then the value of default MAC
7422 * address was changed on this VF.
7423 * If set to 0, then this bit should be ignored.
7425 #define HWRM_ASYNC_EVENT_CMPL_VF_CFG_CHANGE_EVENT_DATA1_DFLT_MAC_ADDR_CHANGE \
7428 * If this bit is set to 1, then the value of default VLAN
7429 * was changed on this VF.
7430 * If set to 0, then this bit should be ignored.
7432 #define HWRM_ASYNC_EVENT_CMPL_VF_CFG_CHANGE_EVENT_DATA1_DFLT_VLAN_CHANGE \
7435 * If this bit is set to 1, then the value of trusted VF enable
7436 * was changed on this VF.
7437 * If set to 0, then this bit should be ignored.
7439 #define HWRM_ASYNC_EVENT_CMPL_VF_CFG_CHANGE_EVENT_DATA1_TRUSTED_VF_CFG_CHANGE \
7443 /* hwrm_async_event_cmpl_llfc_pfc_change (size:128b/16B) */
7444 struct hwrm_async_event_cmpl_llfc_pfc_change {
7447 * This field indicates the exact type of the completion.
7448 * By convention, the LSB identifies the length of the
7449 * record in 16B units. Even values indicate 16B
7450 * records. Odd values indicate 32B
7453 #define HWRM_ASYNC_EVENT_CMPL_LLFC_PFC_CHANGE_TYPE_MASK \
7455 #define HWRM_ASYNC_EVENT_CMPL_LLFC_PFC_CHANGE_TYPE_SFT 0
7456 /* HWRM Asynchronous Event Information */
7457 #define HWRM_ASYNC_EVENT_CMPL_LLFC_PFC_CHANGE_TYPE_HWRM_ASYNC_EVENT \
7459 #define HWRM_ASYNC_EVENT_CMPL_LLFC_PFC_CHANGE_TYPE_LAST \
7460 HWRM_ASYNC_EVENT_CMPL_LLFC_PFC_CHANGE_TYPE_HWRM_ASYNC_EVENT
7461 /* unused1 is 10 b */
7462 #define HWRM_ASYNC_EVENT_CMPL_LLFC_PFC_CHANGE_UNUSED1_MASK \
7464 #define HWRM_ASYNC_EVENT_CMPL_LLFC_PFC_CHANGE_UNUSED1_SFT 6
7465 /* Identifiers of events. */
7467 /* LLFC/PFC Configuration Change */
7468 #define HWRM_ASYNC_EVENT_CMPL_LLFC_PFC_CHANGE_EVENT_ID_LLFC_PFC_CHANGE \
7470 #define HWRM_ASYNC_EVENT_CMPL_LLFC_PFC_CHANGE_EVENT_ID_LAST \
7471 HWRM_ASYNC_EVENT_CMPL_LLFC_PFC_CHANGE_EVENT_ID_LLFC_PFC_CHANGE
7472 /* Event specific data */
7473 uint32_t event_data2;
7476 * This value is written by the NIC such that it will be different
7477 * for each pass through the completion queue. The even passes
7478 * will write 1. The odd passes will write 0.
7480 #define HWRM_ASYNC_EVENT_CMPL_LLFC_PFC_CHANGE_V UINT32_C(0x1)
7482 #define HWRM_ASYNC_EVENT_CMPL_LLFC_PFC_CHANGE_OPAQUE_MASK \
7484 #define HWRM_ASYNC_EVENT_CMPL_LLFC_PFC_CHANGE_OPAQUE_SFT 1
7485 /* 8-lsb timestamp from POR (100-msec resolution) */
7486 uint8_t timestamp_lo;
7487 /* 16-lsb timestamp from POR (100-msec resolution) */
7488 uint16_t timestamp_hi;
7489 /* Event specific data */
7490 uint32_t event_data1;
7491 /* Indicates llfc pfc status change */
7492 #define HWRM_ASYNC_EVENT_CMPL_LLFC_PFC_CHANGE_EVENT_DATA1_LLFC_PFC_MASK \
7494 #define HWRM_ASYNC_EVENT_CMPL_LLFC_PFC_CHANGE_EVENT_DATA1_LLFC_PFC_SFT \
7497 * If this field set to 1, then it indicates that llfc is
7500 #define HWRM_ASYNC_EVENT_CMPL_LLFC_PFC_CHANGE_EVENT_DATA1_LLFC_PFC_LLFC \
7503 * If this field is set to 2, then it indicates that pfc
7506 #define HWRM_ASYNC_EVENT_CMPL_LLFC_PFC_CHANGE_EVENT_DATA1_LLFC_PFC_PFC \
7508 #define HWRM_ASYNC_EVENT_CMPL_LLFC_PFC_CHANGE_EVENT_DATA1_LLFC_PFC_LAST \
7509 HWRM_ASYNC_EVENT_CMPL_LLFC_PFC_CHANGE_EVENT_DATA1_LLFC_PFC_PFC
7510 /* Indicates the physical port this llfc pfc change occur */
7511 #define HWRM_ASYNC_EVENT_CMPL_LLFC_PFC_CHANGE_EVENT_DATA1_PORT_MASK \
7513 #define HWRM_ASYNC_EVENT_CMPL_LLFC_PFC_CHANGE_EVENT_DATA1_PORT_SFT \
7516 #define HWRM_ASYNC_EVENT_CMPL_LLFC_PFC_CHANGE_EVENT_DATA1_PORT_ID_MASK \
7518 #define HWRM_ASYNC_EVENT_CMPL_LLFC_PFC_CHANGE_EVENT_DATA1_PORT_ID_SFT \
7522 /* hwrm_async_event_cmpl_default_vnic_change (size:128b/16B) */
7523 struct hwrm_async_event_cmpl_default_vnic_change {
7526 * This field indicates the exact type of the completion.
7527 * By convention, the LSB identifies the length of the
7528 * record in 16B units. Even values indicate 16B
7529 * records. Odd values indicate 32B
7532 #define HWRM_ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_TYPE_MASK \
7534 #define HWRM_ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_TYPE_SFT \
7536 /* HWRM Asynchronous Event Information */
7537 #define HWRM_ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_TYPE_HWRM_ASYNC_EVENT \
7539 #define HWRM_ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_TYPE_LAST \
7540 HWRM_ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_TYPE_HWRM_ASYNC_EVENT
7541 /* unused1 is 10 b */
7542 #define HWRM_ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_UNUSED1_MASK \
7544 #define HWRM_ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_UNUSED1_SFT \
7546 /* Identifiers of events. */
7548 /* Notification of a default vnic allocation or free */
7549 #define HWRM_ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_EVENT_ID_ALLOC_FREE_NOTIFICATION \
7551 #define HWRM_ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_EVENT_ID_LAST \
7552 HWRM_ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_EVENT_ID_ALLOC_FREE_NOTIFICATION
7553 /* Event specific data */
7554 uint32_t event_data2;
7557 * This value is written by the NIC such that it will be different
7558 * for each pass through the completion queue. The even passes
7559 * will write 1. The odd passes will write 0.
7561 #define HWRM_ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_V \
7564 #define HWRM_ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_OPAQUE_MASK \
7566 #define HWRM_ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_OPAQUE_SFT 1
7567 /* 8-lsb timestamp from POR (100-msec resolution) */
7568 uint8_t timestamp_lo;
7569 /* 16-lsb timestamp from POR (100-msec resolution) */
7570 uint16_t timestamp_hi;
7571 /* Event specific data */
7572 uint32_t event_data1;
7573 /* Indicates default vnic configuration change */
7574 #define HWRM_ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_EVENT_DATA1_DEF_VNIC_STATE_MASK \
7576 #define HWRM_ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_EVENT_DATA1_DEF_VNIC_STATE_SFT \
7579 * If this field is set to 1, then it indicates that
7580 * a default VNIC has been allocate.
7582 #define HWRM_ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_EVENT_DATA1_DEF_VNIC_STATE_DEF_VNIC_ALLOC \
7585 * If this field is set to 2, then it indicates that
7586 * a default VNIC has been freed.
7588 #define HWRM_ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_EVENT_DATA1_DEF_VNIC_STATE_DEF_VNIC_FREE \
7590 #define HWRM_ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_EVENT_DATA1_DEF_VNIC_STATE_LAST \
7591 HWRM_ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_EVENT_DATA1_DEF_VNIC_STATE_DEF_VNIC_FREE
7592 /* Indicates the physical function this event occurred on. */
7593 #define HWRM_ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_EVENT_DATA1_PF_ID_MASK \
7595 #define HWRM_ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_EVENT_DATA1_PF_ID_SFT \
7597 /* Indicates the virtual function this event occurred on */
7598 #define HWRM_ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_EVENT_DATA1_VF_ID_MASK \
7600 #define HWRM_ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_EVENT_DATA1_VF_ID_SFT \
7604 /* hwrm_async_event_cmpl_hw_flow_aged (size:128b/16B) */
7605 struct hwrm_async_event_cmpl_hw_flow_aged {
7608 * This field indicates the exact type of the completion.
7609 * By convention, the LSB identifies the length of the
7610 * record in 16B units. Even values indicate 16B
7611 * records. Odd values indicate 32B
7614 #define HWRM_ASYNC_EVENT_CMPL_HW_FLOW_AGED_TYPE_MASK \
7616 #define HWRM_ASYNC_EVENT_CMPL_HW_FLOW_AGED_TYPE_SFT 0
7617 /* HWRM Asynchronous Event Information */
7618 #define HWRM_ASYNC_EVENT_CMPL_HW_FLOW_AGED_TYPE_HWRM_ASYNC_EVENT \
7620 #define HWRM_ASYNC_EVENT_CMPL_HW_FLOW_AGED_TYPE_LAST \
7621 HWRM_ASYNC_EVENT_CMPL_HW_FLOW_AGED_TYPE_HWRM_ASYNC_EVENT
7622 /* Identifiers of events. */
7624 /* Notification of a hw flow aged */
7625 #define HWRM_ASYNC_EVENT_CMPL_HW_FLOW_AGED_EVENT_ID_HW_FLOW_AGED \
7627 #define HWRM_ASYNC_EVENT_CMPL_HW_FLOW_AGED_EVENT_ID_LAST \
7628 HWRM_ASYNC_EVENT_CMPL_HW_FLOW_AGED_EVENT_ID_HW_FLOW_AGED
7629 /* Event specific data */
7630 uint32_t event_data2;
7633 * This value is written by the NIC such that it will be different
7634 * for each pass through the completion queue. The even passes
7635 * will write 1. The odd passes will write 0.
7637 #define HWRM_ASYNC_EVENT_CMPL_HW_FLOW_AGED_V UINT32_C(0x1)
7639 #define HWRM_ASYNC_EVENT_CMPL_HW_FLOW_AGED_OPAQUE_MASK UINT32_C(0xfe)
7640 #define HWRM_ASYNC_EVENT_CMPL_HW_FLOW_AGED_OPAQUE_SFT 1
7641 /* 8-lsb timestamp from POR (100-msec resolution) */
7642 uint8_t timestamp_lo;
7643 /* 16-lsb timestamp from POR (100-msec resolution) */
7644 uint16_t timestamp_hi;
7645 /* Event specific data */
7646 uint32_t event_data1;
7647 /* Indicates flow ID this event occurred on. */
7648 #define HWRM_ASYNC_EVENT_CMPL_HW_FLOW_AGED_EVENT_DATA1_FLOW_ID_MASK \
7649 UINT32_C(0x7fffffff)
7650 #define HWRM_ASYNC_EVENT_CMPL_HW_FLOW_AGED_EVENT_DATA1_FLOW_ID_SFT \
7652 /* Indicates flow direction this event occurred on. */
7653 #define HWRM_ASYNC_EVENT_CMPL_HW_FLOW_AGED_EVENT_DATA1_FLOW_DIRECTION \
7654 UINT32_C(0x80000000)
7656 * If this bit set to 0, then it indicates that the aged
7657 * event was rx flow.
7659 #define HWRM_ASYNC_EVENT_CMPL_HW_FLOW_AGED_EVENT_DATA1_FLOW_DIRECTION_RX \
7660 (UINT32_C(0x0) << 31)
7662 * If this bit is set to 1, then it indicates that the aged
7663 * event was tx flow.
7665 #define HWRM_ASYNC_EVENT_CMPL_HW_FLOW_AGED_EVENT_DATA1_FLOW_DIRECTION_TX \
7666 (UINT32_C(0x1) << 31)
7667 #define HWRM_ASYNC_EVENT_CMPL_HW_FLOW_AGED_EVENT_DATA1_FLOW_DIRECTION_LAST \
7668 HWRM_ASYNC_EVENT_CMPL_HW_FLOW_AGED_EVENT_DATA1_FLOW_DIRECTION_TX
7671 /* hwrm_async_event_cmpl_eem_cache_flush_req (size:128b/16B) */
7672 struct hwrm_async_event_cmpl_eem_cache_flush_req {
7675 * This field indicates the exact type of the completion.
7676 * By convention, the LSB identifies the length of the
7677 * record in 16B units. Even values indicate 16B
7678 * records. Odd values indicate 32B
7681 #define HWRM_ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_REQ_TYPE_MASK \
7683 #define HWRM_ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_REQ_TYPE_SFT \
7685 /* HWRM Asynchronous Event Information */
7686 #define HWRM_ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_REQ_TYPE_HWRM_ASYNC_EVENT \
7688 #define HWRM_ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_REQ_TYPE_LAST \
7689 HWRM_ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_REQ_TYPE_HWRM_ASYNC_EVENT
7690 /* Identifiers of events. */
7692 /* Notification of a eem_cache_flush request */
7693 #define HWRM_ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_REQ_EVENT_ID_EEM_CACHE_FLUSH_REQ \
7695 #define HWRM_ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_REQ_EVENT_ID_LAST \
7696 HWRM_ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_REQ_EVENT_ID_EEM_CACHE_FLUSH_REQ
7697 /* Event specific data */
7698 uint32_t event_data2;
7701 * This value is written by the NIC such that it will be different
7702 * for each pass through the completion queue. The even passes
7703 * will write 1. The odd passes will write 0.
7705 #define HWRM_ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_REQ_V \
7708 #define HWRM_ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_REQ_OPAQUE_MASK \
7710 #define HWRM_ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_REQ_OPAQUE_SFT 1
7711 /* 8-lsb timestamp from POR (100-msec resolution) */
7712 uint8_t timestamp_lo;
7713 /* 16-lsb timestamp from POR (100-msec resolution) */
7714 uint16_t timestamp_hi;
7715 /* Event specific data */
7716 uint32_t event_data1;
7719 /* hwrm_async_event_cmpl_eem_cache_flush_done (size:128b/16B) */
7720 struct hwrm_async_event_cmpl_eem_cache_flush_done {
7723 * This field indicates the exact type of the completion.
7724 * By convention, the LSB identifies the length of the
7725 * record in 16B units. Even values indicate 16B
7726 * records. Odd values indicate 32B
7729 #define HWRM_ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_DONE_TYPE_MASK \
7731 #define HWRM_ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_DONE_TYPE_SFT \
7733 /* HWRM Asynchronous Event Information */
7734 #define HWRM_ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_DONE_TYPE_HWRM_ASYNC_EVENT \
7736 #define HWRM_ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_DONE_TYPE_LAST \
7737 HWRM_ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_DONE_TYPE_HWRM_ASYNC_EVENT
7738 /* Identifiers of events. */
7741 * Notification of a host eem_cache_flush has completed. This event
7742 * is generated by the host driver.
7744 #define HWRM_ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_DONE_EVENT_ID_EEM_CACHE_FLUSH_DONE \
7746 #define HWRM_ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_DONE_EVENT_ID_LAST \
7747 HWRM_ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_DONE_EVENT_ID_EEM_CACHE_FLUSH_DONE
7748 /* Event specific data */
7749 uint32_t event_data2;
7752 * This value is written by the NIC such that it will be different
7753 * for each pass through the completion queue. The even passes
7754 * will write 1. The odd passes will write 0.
7756 #define HWRM_ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_DONE_V \
7759 #define HWRM_ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_DONE_OPAQUE_MASK \
7761 #define HWRM_ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_DONE_OPAQUE_SFT 1
7762 /* 8-lsb timestamp from POR (100-msec resolution) */
7763 uint8_t timestamp_lo;
7764 /* 16-lsb timestamp from POR (100-msec resolution) */
7765 uint16_t timestamp_hi;
7766 /* Event specific data */
7767 uint32_t event_data1;
7768 /* Indicates function ID that this event occurred on. */
7769 #define HWRM_ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_DONE_EVENT_DATA1_FID_MASK \
7771 #define HWRM_ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_DONE_EVENT_DATA1_FID_SFT \
7775 /* hwrm_async_event_cmpl_tcp_flag_action_change (size:128b/16B) */
7776 struct hwrm_async_event_cmpl_tcp_flag_action_change {
7779 * This field indicates the exact type of the completion.
7780 * By convention, the LSB identifies the length of the
7781 * record in 16B units. Even values indicate 16B
7782 * records. Odd values indicate 32B
7785 #define HWRM_ASYNC_EVENT_CMPL_TCP_FLAG_ACTION_CHANGE_TYPE_MASK \
7787 #define HWRM_ASYNC_EVENT_CMPL_TCP_FLAG_ACTION_CHANGE_TYPE_SFT \
7789 /* HWRM Asynchronous Event Information */
7790 #define HWRM_ASYNC_EVENT_CMPL_TCP_FLAG_ACTION_CHANGE_TYPE_HWRM_ASYNC_EVENT \
7792 #define HWRM_ASYNC_EVENT_CMPL_TCP_FLAG_ACTION_CHANGE_TYPE_LAST \
7793 HWRM_ASYNC_EVENT_CMPL_TCP_FLAG_ACTION_CHANGE_TYPE_HWRM_ASYNC_EVENT
7794 /* Identifiers of events. */
7796 /* Notification of tcp flag action change */
7797 #define HWRM_ASYNC_EVENT_CMPL_TCP_FLAG_ACTION_CHANGE_EVENT_ID_TCP_FLAG_ACTION_CHANGE \
7799 #define HWRM_ASYNC_EVENT_CMPL_TCP_FLAG_ACTION_CHANGE_EVENT_ID_LAST \
7800 HWRM_ASYNC_EVENT_CMPL_TCP_FLAG_ACTION_CHANGE_EVENT_ID_TCP_FLAG_ACTION_CHANGE
7801 /* Event specific data */
7802 uint32_t event_data2;
7805 * This value is written by the NIC such that it will be different
7806 * for each pass through the completion queue. The even passes
7807 * will write 1. The odd passes will write 0.
7809 #define HWRM_ASYNC_EVENT_CMPL_TCP_FLAG_ACTION_CHANGE_V \
7812 #define HWRM_ASYNC_EVENT_CMPL_TCP_FLAG_ACTION_CHANGE_OPAQUE_MASK \
7814 #define HWRM_ASYNC_EVENT_CMPL_TCP_FLAG_ACTION_CHANGE_OPAQUE_SFT 1
7815 /* 8-lsb timestamp from POR (100-msec resolution) */
7816 uint8_t timestamp_lo;
7817 /* 16-lsb timestamp from POR (100-msec resolution) */
7818 uint16_t timestamp_hi;
7819 /* Event specific data */
7820 uint32_t event_data1;
7823 /* hwrm_async_event_cmpl_eem_flow_active (size:128b/16B) */
7824 struct hwrm_async_event_cmpl_eem_flow_active {
7827 * This field indicates the exact type of the completion.
7828 * By convention, the LSB identifies the length of the
7829 * record in 16B units. Even values indicate 16B
7830 * records. Odd values indicate 32B
7833 #define HWRM_ASYNC_EVENT_CMPL_EEM_FLOW_ACTIVE_TYPE_MASK \
7835 #define HWRM_ASYNC_EVENT_CMPL_EEM_FLOW_ACTIVE_TYPE_SFT 0
7836 /* HWRM Asynchronous Event Information */
7837 #define HWRM_ASYNC_EVENT_CMPL_EEM_FLOW_ACTIVE_TYPE_HWRM_ASYNC_EVENT \
7839 #define HWRM_ASYNC_EVENT_CMPL_EEM_FLOW_ACTIVE_TYPE_LAST \
7840 HWRM_ASYNC_EVENT_CMPL_EEM_FLOW_ACTIVE_TYPE_HWRM_ASYNC_EVENT
7841 /* Identifiers of events. */
7843 /* Notification of an active eem flow */
7844 #define HWRM_ASYNC_EVENT_CMPL_EEM_FLOW_ACTIVE_EVENT_ID_EEM_FLOW_ACTIVE \
7846 #define HWRM_ASYNC_EVENT_CMPL_EEM_FLOW_ACTIVE_EVENT_ID_LAST \
7847 HWRM_ASYNC_EVENT_CMPL_EEM_FLOW_ACTIVE_EVENT_ID_EEM_FLOW_ACTIVE
7848 /* Event specific data */
7849 uint32_t event_data2;
7850 /* Indicates the 2nd global id this event occurred on. */
7851 #define HWRM_ASYNC_EVENT_CMPL_EEM_FLOW_ACTIVE_EVENT_DATA2_GLOBAL_ID_2_MASK \
7852 UINT32_C(0x3fffffff)
7853 #define HWRM_ASYNC_EVENT_CMPL_EEM_FLOW_ACTIVE_EVENT_DATA2_GLOBAL_ID_2_SFT \
7856 * Indicates flow direction of the flow identified by
7859 #define HWRM_ASYNC_EVENT_CMPL_EEM_FLOW_ACTIVE_EVENT_DATA2_FLOW_DIRECTION \
7860 UINT32_C(0x40000000)
7861 /* If this bit is set to 0, then it indicates that this rx flow. */
7862 #define HWRM_ASYNC_EVENT_CMPL_EEM_FLOW_ACTIVE_EVENT_DATA2_FLOW_DIRECTION_RX \
7863 (UINT32_C(0x0) << 30)
7864 /* If this bit is set to 1, then it indicates that this tx flow. */
7865 #define HWRM_ASYNC_EVENT_CMPL_EEM_FLOW_ACTIVE_EVENT_DATA2_FLOW_DIRECTION_TX \
7866 (UINT32_C(0x1) << 30)
7867 #define HWRM_ASYNC_EVENT_CMPL_EEM_FLOW_ACTIVE_EVENT_DATA2_FLOW_DIRECTION_LAST \
7868 HWRM_ASYNC_EVENT_CMPL_EEM_FLOW_ACTIVE_EVENT_DATA2_FLOW_DIRECTION_TX
7871 * This value is written by the NIC such that it will be different
7872 * for each pass through the completion queue. The even passes
7873 * will write 1. The odd passes will write 0.
7875 #define HWRM_ASYNC_EVENT_CMPL_EEM_FLOW_ACTIVE_V UINT32_C(0x1)
7877 #define HWRM_ASYNC_EVENT_CMPL_EEM_FLOW_ACTIVE_OPAQUE_MASK \
7879 #define HWRM_ASYNC_EVENT_CMPL_EEM_FLOW_ACTIVE_OPAQUE_SFT 1
7880 /* 8-lsb timestamp from POR (100-msec resolution) */
7881 uint8_t timestamp_lo;
7882 /* 16-lsb timestamp from POR (100-msec resolution) */
7883 uint16_t timestamp_hi;
7884 /* Event specific data */
7885 uint32_t event_data1;
7886 /* Indicates the 1st global id this event occurred on. */
7887 #define HWRM_ASYNC_EVENT_CMPL_EEM_FLOW_ACTIVE_EVENT_DATA1_GLOBAL_ID_1_MASK \
7888 UINT32_C(0x3fffffff)
7889 #define HWRM_ASYNC_EVENT_CMPL_EEM_FLOW_ACTIVE_EVENT_DATA1_GLOBAL_ID_1_SFT \
7892 * Indicates flow direction of the flow identified by the
7895 #define HWRM_ASYNC_EVENT_CMPL_EEM_FLOW_ACTIVE_EVENT_DATA1_FLOW_DIRECTION \
7896 UINT32_C(0x40000000)
7897 /* If this bit is set to 0, then it indicates that this is rx flow. */
7898 #define HWRM_ASYNC_EVENT_CMPL_EEM_FLOW_ACTIVE_EVENT_DATA1_FLOW_DIRECTION_RX \
7899 (UINT32_C(0x0) << 30)
7900 /* If this bit is set to 1, then it indicates that this is tx flow. */
7901 #define HWRM_ASYNC_EVENT_CMPL_EEM_FLOW_ACTIVE_EVENT_DATA1_FLOW_DIRECTION_TX \
7902 (UINT32_C(0x1) << 30)
7903 #define HWRM_ASYNC_EVENT_CMPL_EEM_FLOW_ACTIVE_EVENT_DATA1_FLOW_DIRECTION_LAST \
7904 HWRM_ASYNC_EVENT_CMPL_EEM_FLOW_ACTIVE_EVENT_DATA1_FLOW_DIRECTION_TX
7906 * Indicates EEM flow aging mode this event occurred on. If
7907 * this bit is set to 0, the event_data1 is the EEM global
7908 * ID. If this bit is set to 1, the event_data1 is the number
7909 * of global ID in the context memory.
7911 #define HWRM_ASYNC_EVENT_CMPL_EEM_FLOW_ACTIVE_EVENT_DATA1_MODE \
7912 UINT32_C(0x80000000)
7913 /* EEM flow aging mode 0. */
7914 #define HWRM_ASYNC_EVENT_CMPL_EEM_FLOW_ACTIVE_EVENT_DATA1_MODE_0 \
7915 (UINT32_C(0x0) << 31)
7916 /* EEM flow aging mode 1. */
7917 #define HWRM_ASYNC_EVENT_CMPL_EEM_FLOW_ACTIVE_EVENT_DATA1_MODE_1 \
7918 (UINT32_C(0x1) << 31)
7919 #define HWRM_ASYNC_EVENT_CMPL_EEM_FLOW_ACTIVE_EVENT_DATA1_MODE_LAST \
7920 HWRM_ASYNC_EVENT_CMPL_EEM_FLOW_ACTIVE_EVENT_DATA1_MODE_1
7923 /* hwrm_async_event_cmpl_eem_cfg_change (size:128b/16B) */
7924 struct hwrm_async_event_cmpl_eem_cfg_change {
7927 * This field indicates the exact type of the completion.
7928 * By convention, the LSB identifies the length of the
7929 * record in 16B units. Even values indicate 16B
7930 * records. Odd values indicate 32B
7933 #define HWRM_ASYNC_EVENT_CMPL_EEM_CFG_CHANGE_TYPE_MASK \
7935 #define HWRM_ASYNC_EVENT_CMPL_EEM_CFG_CHANGE_TYPE_SFT 0
7936 /* HWRM Asynchronous Event Information */
7937 #define HWRM_ASYNC_EVENT_CMPL_EEM_CFG_CHANGE_TYPE_HWRM_ASYNC_EVENT \
7939 #define HWRM_ASYNC_EVENT_CMPL_EEM_CFG_CHANGE_TYPE_LAST \
7940 HWRM_ASYNC_EVENT_CMPL_EEM_CFG_CHANGE_TYPE_HWRM_ASYNC_EVENT
7941 /* Identifiers of events. */
7943 /* Notification of EEM configuration change */
7944 #define HWRM_ASYNC_EVENT_CMPL_EEM_CFG_CHANGE_EVENT_ID_EEM_CFG_CHANGE \
7946 #define HWRM_ASYNC_EVENT_CMPL_EEM_CFG_CHANGE_EVENT_ID_LAST \
7947 HWRM_ASYNC_EVENT_CMPL_EEM_CFG_CHANGE_EVENT_ID_EEM_CFG_CHANGE
7948 /* Event specific data */
7949 uint32_t event_data2;
7952 * This value is written by the NIC such that it will be different
7953 * for each pass through the completion queue. The even passes
7954 * will write 1. The odd passes will write 0.
7956 #define HWRM_ASYNC_EVENT_CMPL_EEM_CFG_CHANGE_V UINT32_C(0x1)
7958 #define HWRM_ASYNC_EVENT_CMPL_EEM_CFG_CHANGE_OPAQUE_MASK UINT32_C(0xfe)
7959 #define HWRM_ASYNC_EVENT_CMPL_EEM_CFG_CHANGE_OPAQUE_SFT 1
7960 /* 8-lsb timestamp from POR (100-msec resolution) */
7961 uint8_t timestamp_lo;
7962 /* 16-lsb timestamp from POR (100-msec resolution) */
7963 uint16_t timestamp_hi;
7964 /* Event specific data */
7965 uint32_t event_data1;
7967 * Value of 1 to indicate EEM TX configuration is enabled. Value of
7968 * 0 to indicate the EEM TX configuration is disabled.
7970 #define HWRM_ASYNC_EVENT_CMPL_EEM_CFG_CHANGE_EVENT_DATA1_EEM_TX_ENABLE \
7973 * Value of 1 to indicate EEM RX configuration is enabled. Value of 0
7974 * to indicate the EEM RX configuration is disabled.
7976 #define HWRM_ASYNC_EVENT_CMPL_EEM_CFG_CHANGE_EVENT_DATA1_EEM_RX_ENABLE \
7980 /* hwrm_async_event_cmpl_quiesce_done (size:128b/16B) */
7981 struct hwrm_async_event_cmpl_quiesce_done {
7984 * This field indicates the exact type of the completion.
7985 * By convention, the LSB identifies the length of the
7986 * record in 16B units. Even values indicate 16B
7987 * records. Odd values indicate 32B
7990 #define HWRM_ASYNC_EVENT_CMPL_QUIESCE_DONE_TYPE_MASK \
7992 #define HWRM_ASYNC_EVENT_CMPL_QUIESCE_DONE_TYPE_SFT 0
7993 /* HWRM Asynchronous Event Information */
7994 #define HWRM_ASYNC_EVENT_CMPL_QUIESCE_DONE_TYPE_HWRM_ASYNC_EVENT \
7996 #define HWRM_ASYNC_EVENT_CMPL_QUIESCE_DONE_TYPE_LAST \
7997 HWRM_ASYNC_EVENT_CMPL_QUIESCE_DONE_TYPE_HWRM_ASYNC_EVENT
7998 /* Identifiers of events. */
8000 /* An event signifying completion of HWRM_FW_STATE_QUIESCE */
8001 #define HWRM_ASYNC_EVENT_CMPL_QUIESCE_DONE_EVENT_ID_QUIESCE_DONE \
8003 #define HWRM_ASYNC_EVENT_CMPL_QUIESCE_DONE_EVENT_ID_LAST \
8004 HWRM_ASYNC_EVENT_CMPL_QUIESCE_DONE_EVENT_ID_QUIESCE_DONE
8005 /* Event specific data */
8006 uint32_t event_data2;
8007 /* Status of HWRM_FW_STATE_QUIESCE completion */
8008 #define HWRM_ASYNC_EVENT_CMPL_QUIESCE_DONE_EVENT_DATA2_QUIESCE_STATUS_MASK \
8010 #define HWRM_ASYNC_EVENT_CMPL_QUIESCE_DONE_EVENT_DATA2_QUIESCE_STATUS_SFT \
8013 * The quiesce operation started by HWRM_FW_STATE_QUIESCE
8014 * completed successfully.
8016 #define HWRM_ASYNC_EVENT_CMPL_QUIESCE_DONE_EVENT_DATA2_QUIESCE_STATUS_SUCCESS \
8019 * The quiesce operation started by HWRM_FW_STATE_QUIESCE timed
8022 #define HWRM_ASYNC_EVENT_CMPL_QUIESCE_DONE_EVENT_DATA2_QUIESCE_STATUS_TIMEOUT \
8025 * The quiesce operation started by HWRM_FW_STATE_QUIESCE
8026 * encountered an error.
8028 #define HWRM_ASYNC_EVENT_CMPL_QUIESCE_DONE_EVENT_DATA2_QUIESCE_STATUS_ERROR \
8030 #define HWRM_ASYNC_EVENT_CMPL_QUIESCE_DONE_EVENT_DATA2_QUIESCE_STATUS_LAST \
8031 HWRM_ASYNC_EVENT_CMPL_QUIESCE_DONE_EVENT_DATA2_QUIESCE_STATUS_ERROR
8033 #define HWRM_ASYNC_EVENT_CMPL_QUIESCE_DONE_EVENT_DATA2_OPAQUE_MASK \
8035 #define HWRM_ASYNC_EVENT_CMPL_QUIESCE_DONE_EVENT_DATA2_OPAQUE_SFT \
8038 * Additional information about internal hardware state related to
8039 * idle/quiesce state. QUIESCE may succeed per quiesce_status
8040 * regardless of idle_state_flags. If QUIESCE fails, the host may
8041 * inspect idle_state_flags to determine whether a retry is warranted.
8043 #define HWRM_ASYNC_EVENT_CMPL_QUIESCE_DONE_EVENT_DATA2_IDLE_STATE_FLAGS_MASK \
8045 #define HWRM_ASYNC_EVENT_CMPL_QUIESCE_DONE_EVENT_DATA2_IDLE_STATE_FLAGS_SFT \
8048 * Failure to quiesce is caused by host not updating the NQ consumer
8051 #define HWRM_ASYNC_EVENT_CMPL_QUIESCE_DONE_EVENT_DATA2_IDLE_STATE_FLAGS_INCOMPLETE_NQ \
8053 /* Flag 1 indicating partial non-idle state. */
8054 #define HWRM_ASYNC_EVENT_CMPL_QUIESCE_DONE_EVENT_DATA2_IDLE_STATE_FLAGS_IDLE_STATUS_1 \
8056 /* Flag 2 indicating partial non-idle state. */
8057 #define HWRM_ASYNC_EVENT_CMPL_QUIESCE_DONE_EVENT_DATA2_IDLE_STATE_FLAGS_IDLE_STATUS_2 \
8059 /* Flag 3 indicating partial non-idle state. */
8060 #define HWRM_ASYNC_EVENT_CMPL_QUIESCE_DONE_EVENT_DATA2_IDLE_STATE_FLAGS_IDLE_STATUS_3 \
8064 * This value is written by the NIC such that it will be different
8065 * for each pass through the completion queue. The even passes
8066 * will write 1. The odd passes will write 0.
8068 #define HWRM_ASYNC_EVENT_CMPL_QUIESCE_DONE_V UINT32_C(0x1)
8070 #define HWRM_ASYNC_EVENT_CMPL_QUIESCE_DONE_OPAQUE_MASK UINT32_C(0xfe)
8071 #define HWRM_ASYNC_EVENT_CMPL_QUIESCE_DONE_OPAQUE_SFT 1
8072 /* 8-lsb timestamp from POR (100-msec resolution) */
8073 uint8_t timestamp_lo;
8074 /* 16-lsb timestamp from POR (100-msec resolution) */
8075 uint16_t timestamp_hi;
8076 /* Event specific data */
8077 uint32_t event_data1;
8078 /* Time stamp for error event */
8079 #define HWRM_ASYNC_EVENT_CMPL_QUIESCE_DONE_EVENT_DATA1_TIMESTAMP \
8083 /* hwrm_async_event_cmpl_deferred_response (size:128b/16B) */
8084 struct hwrm_async_event_cmpl_deferred_response {
8087 * This field indicates the exact type of the completion.
8088 * By convention, the LSB identifies the length of the
8089 * record in 16B units. Even values indicate 16B
8090 * records. Odd values indicate 32B
8093 #define HWRM_ASYNC_EVENT_CMPL_DEFERRED_RESPONSE_TYPE_MASK \
8095 #define HWRM_ASYNC_EVENT_CMPL_DEFERRED_RESPONSE_TYPE_SFT 0
8096 /* HWRM Asynchronous Event Information */
8097 #define HWRM_ASYNC_EVENT_CMPL_DEFERRED_RESPONSE_TYPE_HWRM_ASYNC_EVENT \
8099 #define HWRM_ASYNC_EVENT_CMPL_DEFERRED_RESPONSE_TYPE_LAST \
8100 HWRM_ASYNC_EVENT_CMPL_DEFERRED_RESPONSE_TYPE_HWRM_ASYNC_EVENT
8101 /* Identifiers of events. */
8104 * An event signifying a HWRM command is in progress and its
8105 * response will be deferred
8107 #define HWRM_ASYNC_EVENT_CMPL_DEFERRED_RESPONSE_EVENT_ID_DEFERRED_RESPONSE \
8109 #define HWRM_ASYNC_EVENT_CMPL_DEFERRED_RESPONSE_EVENT_ID_LAST \
8110 HWRM_ASYNC_EVENT_CMPL_DEFERRED_RESPONSE_EVENT_ID_DEFERRED_RESPONSE
8111 /* Event specific data */
8112 uint32_t event_data2;
8114 * The PF's mailbox is clear to issue another command.
8115 * A command with this seq_id is still in progress
8116 * and will return a regular HWRM completion when done.
8117 * 'event_data1' field, if non-zero, contains the estimated
8118 * execution time for the command.
8120 #define HWRM_ASYNC_EVENT_CMPL_DEFERRED_RESPONSE_EVENT_DATA2_SEQ_ID_MASK \
8122 #define HWRM_ASYNC_EVENT_CMPL_DEFERRED_RESPONSE_EVENT_DATA2_SEQ_ID_SFT \
8126 * This value is written by the NIC such that it will be different
8127 * for each pass through the completion queue. The even passes
8128 * will write 1. The odd passes will write 0.
8130 #define HWRM_ASYNC_EVENT_CMPL_DEFERRED_RESPONSE_V \
8133 #define HWRM_ASYNC_EVENT_CMPL_DEFERRED_RESPONSE_OPAQUE_MASK \
8135 #define HWRM_ASYNC_EVENT_CMPL_DEFERRED_RESPONSE_OPAQUE_SFT 1
8136 /* 8-lsb timestamp from POR (100-msec resolution) */
8137 uint8_t timestamp_lo;
8138 /* 16-lsb timestamp from POR (100-msec resolution) */
8139 uint16_t timestamp_hi;
8140 /* Estimated remaining time of command execution in ms (if not zero) */
8141 uint32_t event_data1;
8144 /* hwrm_async_event_cmpl_pfc_watchdog_cfg_change (size:128b/16B) */
8145 struct hwrm_async_event_cmpl_pfc_watchdog_cfg_change {
8148 * This field indicates the exact type of the completion.
8149 * By convention, the LSB identifies the length of the
8150 * record in 16B units. Even values indicate 16B
8151 * records. Odd values indicate 32B
8154 #define HWRM_ASYNC_EVENT_CMPL_PFC_WATCHDOG_CFG_CHANGE_TYPE_MASK \
8156 #define HWRM_ASYNC_EVENT_CMPL_PFC_WATCHDOG_CFG_CHANGE_TYPE_SFT \
8158 /* HWRM Asynchronous Event Information */
8159 #define HWRM_ASYNC_EVENT_CMPL_PFC_WATCHDOG_CFG_CHANGE_TYPE_HWRM_ASYNC_EVENT \
8161 #define HWRM_ASYNC_EVENT_CMPL_PFC_WATCHDOG_CFG_CHANGE_TYPE_LAST \
8162 HWRM_ASYNC_EVENT_CMPL_PFC_WATCHDOG_CFG_CHANGE_TYPE_HWRM_ASYNC_EVENT
8163 /* Identifiers of events. */
8165 /* PFC watchdog configuration change for given port/cos */
8166 #define HWRM_ASYNC_EVENT_CMPL_PFC_WATCHDOG_CFG_CHANGE_EVENT_ID_PFC_WATCHDOG_CFG_CHANGE \
8168 #define HWRM_ASYNC_EVENT_CMPL_PFC_WATCHDOG_CFG_CHANGE_EVENT_ID_LAST \
8169 HWRM_ASYNC_EVENT_CMPL_PFC_WATCHDOG_CFG_CHANGE_EVENT_ID_PFC_WATCHDOG_CFG_CHANGE
8170 /* Event specific data */
8171 uint32_t event_data2;
8174 * This value is written by the NIC such that it will be different
8175 * for each pass through the completion queue. The even passes
8176 * will write 1. The odd passes will write 0.
8178 #define HWRM_ASYNC_EVENT_CMPL_PFC_WATCHDOG_CFG_CHANGE_V \
8181 #define HWRM_ASYNC_EVENT_CMPL_PFC_WATCHDOG_CFG_CHANGE_OPAQUE_MASK \
8183 #define HWRM_ASYNC_EVENT_CMPL_PFC_WATCHDOG_CFG_CHANGE_OPAQUE_SFT 1
8184 /* 8-lsb timestamp from POR (100-msec resolution) */
8185 uint8_t timestamp_lo;
8186 /* 16-lsb timestamp from POR (100-msec resolution) */
8187 uint16_t timestamp_hi;
8188 /* Event specific data */
8189 uint32_t event_data1;
8191 * 1 in bit position X indicates PFC watchdog should
8194 #define HWRM_ASYNC_EVENT_CMPL_PFC_WATCHDOG_CFG_CHANGE_EVENT_DATA1_PFC_WD_COS_MASK \
8196 #define HWRM_ASYNC_EVENT_CMPL_PFC_WATCHDOG_CFG_CHANGE_EVENT_DATA1_PFC_WD_COS_SFT \
8198 /* 1 means PFC WD for COS0 is on, 0 - off. */
8199 #define HWRM_ASYNC_EVENT_CMPL_PFC_WATCHDOG_CFG_CHANGE_EVENT_DATA1_PFC_WD_COS_PFC_WD_COS0 \
8201 /* 1 means PFC WD for COS1 is on, 0 - off. */
8202 #define HWRM_ASYNC_EVENT_CMPL_PFC_WATCHDOG_CFG_CHANGE_EVENT_DATA1_PFC_WD_COS_PFC_WD_COS1 \
8204 /* 1 means PFC WD for COS2 is on, 0 - off. */
8205 #define HWRM_ASYNC_EVENT_CMPL_PFC_WATCHDOG_CFG_CHANGE_EVENT_DATA1_PFC_WD_COS_PFC_WD_COS2 \
8207 /* 1 means PFC WD for COS3 is on, 0 - off. */
8208 #define HWRM_ASYNC_EVENT_CMPL_PFC_WATCHDOG_CFG_CHANGE_EVENT_DATA1_PFC_WD_COS_PFC_WD_COS3 \
8210 /* 1 means PFC WD for COS4 is on, 0 - off. */
8211 #define HWRM_ASYNC_EVENT_CMPL_PFC_WATCHDOG_CFG_CHANGE_EVENT_DATA1_PFC_WD_COS_PFC_WD_COS4 \
8213 /* 1 means PFC WD for COS5 is on, 0 - off. */
8214 #define HWRM_ASYNC_EVENT_CMPL_PFC_WATCHDOG_CFG_CHANGE_EVENT_DATA1_PFC_WD_COS_PFC_WD_COS5 \
8216 /* 1 means PFC WD for COS6 is on, 0 - off. */
8217 #define HWRM_ASYNC_EVENT_CMPL_PFC_WATCHDOG_CFG_CHANGE_EVENT_DATA1_PFC_WD_COS_PFC_WD_COS6 \
8219 /* 1 means PFC WD for COS7 is on, 0 - off. */
8220 #define HWRM_ASYNC_EVENT_CMPL_PFC_WATCHDOG_CFG_CHANGE_EVENT_DATA1_PFC_WD_COS_PFC_WD_COS7 \
8223 #define HWRM_ASYNC_EVENT_CMPL_PFC_WATCHDOG_CFG_CHANGE_EVENT_DATA1_PORT_ID_MASK \
8225 #define HWRM_ASYNC_EVENT_CMPL_PFC_WATCHDOG_CFG_CHANGE_EVENT_DATA1_PORT_ID_SFT \
8229 /* hwrm_async_event_cmpl_fw_trace_msg (size:128b/16B) */
8230 struct hwrm_async_event_cmpl_fw_trace_msg {
8233 * This field indicates the exact type of the completion.
8234 * By convention, the LSB identifies the length of the
8235 * record in 16B units. Even values indicate 16B
8236 * records. Odd values indicate 32B
8239 #define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_TYPE_MASK \
8241 #define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_TYPE_SFT 0
8242 /* HWRM Asynchronous Event Information */
8243 #define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_TYPE_HWRM_ASYNC_EVENT \
8245 #define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_TYPE_LAST \
8246 HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_TYPE_HWRM_ASYNC_EVENT
8247 /* Identifiers of events. */
8249 /* Firmware trace log message */
8250 #define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_EVENT_ID_FW_TRACE_MSG \
8252 #define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_EVENT_ID_LAST \
8253 HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_EVENT_ID_FW_TRACE_MSG
8254 /* Trace byte 0 to 3 */
8255 uint32_t event_data2;
8257 #define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_EVENT_DATA2_BYTE0_MASK \
8259 #define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_EVENT_DATA2_BYTE0_SFT 0
8261 #define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_EVENT_DATA2_BYTE1_MASK \
8263 #define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_EVENT_DATA2_BYTE1_SFT 8
8265 #define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_EVENT_DATA2_BYTE2_MASK \
8267 #define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_EVENT_DATA2_BYTE2_SFT 16
8269 #define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_EVENT_DATA2_BYTE3_MASK \
8270 UINT32_C(0xff000000)
8271 #define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_EVENT_DATA2_BYTE3_SFT 24
8274 * This value is written by the NIC such that it will be different
8275 * for each pass through the completion queue. The even passes
8276 * will write 1. The odd passes will write 0.
8278 #define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_V UINT32_C(0x1)
8280 #define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_OPAQUE_MASK UINT32_C(0xfe)
8281 #define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_OPAQUE_SFT 1
8283 uint8_t timestamp_lo;
8284 /* Indicates if the string is partial or complete. */
8285 #define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_TIMESTAMP_LO_STRING \
8287 /* Complete string */
8288 #define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_TIMESTAMP_LO_STRING_COMPLETE \
8290 /* Partial string */
8291 #define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_TIMESTAMP_LO_STRING_PARTIAL \
8293 #define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_TIMESTAMP_LO_STRING_LAST \
8294 HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_TIMESTAMP_LO_STRING_PARTIAL
8295 /* Indicates the firmware that sent the trace message. */
8296 #define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_TIMESTAMP_LO_FIRMWARE \
8298 /* Primary firmware */
8299 #define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_TIMESTAMP_LO_FIRMWARE_PRIMARY \
8300 (UINT32_C(0x0) << 1)
8301 /* Secondary firmware */
8302 #define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_TIMESTAMP_LO_FIRMWARE_SECONDARY \
8303 (UINT32_C(0x1) << 1)
8304 #define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_TIMESTAMP_LO_FIRMWARE_LAST \
8305 HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_TIMESTAMP_LO_FIRMWARE_SECONDARY
8306 /* Trace byte 4 to 5 */
8307 uint16_t timestamp_hi;
8309 #define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_TIMESTAMP_HI_BYTE4_MASK \
8311 #define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_TIMESTAMP_HI_BYTE4_SFT 0
8313 #define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_TIMESTAMP_HI_BYTE5_MASK \
8315 #define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_TIMESTAMP_HI_BYTE5_SFT 8
8316 /* Trace byte 6 to 9 */
8317 uint32_t event_data1;
8319 #define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_EVENT_DATA1_BYTE6_MASK \
8321 #define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_EVENT_DATA1_BYTE6_SFT 0
8323 #define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_EVENT_DATA1_BYTE7_MASK \
8325 #define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_EVENT_DATA1_BYTE7_SFT 8
8327 #define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_EVENT_DATA1_BYTE8_MASK \
8329 #define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_EVENT_DATA1_BYTE8_SFT 16
8331 #define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_EVENT_DATA1_BYTE9_MASK \
8332 UINT32_C(0xff000000)
8333 #define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_EVENT_DATA1_BYTE9_SFT 24
8336 /* hwrm_async_event_cmpl_hwrm_error (size:128b/16B) */
8337 struct hwrm_async_event_cmpl_hwrm_error {
8340 * This field indicates the exact type of the completion.
8341 * By convention, the LSB identifies the length of the
8342 * record in 16B units. Even values indicate 16B
8343 * records. Odd values indicate 32B
8346 #define HWRM_ASYNC_EVENT_CMPL_HWRM_ERROR_TYPE_MASK \
8348 #define HWRM_ASYNC_EVENT_CMPL_HWRM_ERROR_TYPE_SFT 0
8349 /* HWRM Asynchronous Event Information */
8350 #define HWRM_ASYNC_EVENT_CMPL_HWRM_ERROR_TYPE_HWRM_ASYNC_EVENT \
8352 #define HWRM_ASYNC_EVENT_CMPL_HWRM_ERROR_TYPE_LAST \
8353 HWRM_ASYNC_EVENT_CMPL_HWRM_ERROR_TYPE_HWRM_ASYNC_EVENT
8354 /* Identifiers of events. */
8357 #define HWRM_ASYNC_EVENT_CMPL_HWRM_ERROR_EVENT_ID_HWRM_ERROR \
8359 #define HWRM_ASYNC_EVENT_CMPL_HWRM_ERROR_EVENT_ID_LAST \
8360 HWRM_ASYNC_EVENT_CMPL_HWRM_ERROR_EVENT_ID_HWRM_ERROR
8361 /* Event specific data */
8362 uint32_t event_data2;
8363 /* Severity of HWRM Error */
8364 #define HWRM_ASYNC_EVENT_CMPL_HWRM_ERROR_EVENT_DATA2_SEVERITY_MASK \
8366 #define HWRM_ASYNC_EVENT_CMPL_HWRM_ERROR_EVENT_DATA2_SEVERITY_SFT 0
8368 #define HWRM_ASYNC_EVENT_CMPL_HWRM_ERROR_EVENT_DATA2_SEVERITY_WARNING \
8370 /* Non-fatal Error */
8371 #define HWRM_ASYNC_EVENT_CMPL_HWRM_ERROR_EVENT_DATA2_SEVERITY_NONFATAL \
8374 #define HWRM_ASYNC_EVENT_CMPL_HWRM_ERROR_EVENT_DATA2_SEVERITY_FATAL \
8376 #define HWRM_ASYNC_EVENT_CMPL_HWRM_ERROR_EVENT_DATA2_SEVERITY_LAST \
8377 HWRM_ASYNC_EVENT_CMPL_HWRM_ERROR_EVENT_DATA2_SEVERITY_FATAL
8380 * This value is written by the NIC such that it will be different
8381 * for each pass through the completion queue. The even passes
8382 * will write 1. The odd passes will write 0.
8384 #define HWRM_ASYNC_EVENT_CMPL_HWRM_ERROR_V UINT32_C(0x1)
8386 #define HWRM_ASYNC_EVENT_CMPL_HWRM_ERROR_OPAQUE_MASK UINT32_C(0xfe)
8387 #define HWRM_ASYNC_EVENT_CMPL_HWRM_ERROR_OPAQUE_SFT 1
8388 /* 8-lsb timestamp from POR (100-msec resolution) */
8389 uint8_t timestamp_lo;
8390 /* 16-lsb timestamp from POR (100-msec resolution) */
8391 uint16_t timestamp_hi;
8392 /* Event specific data */
8393 uint32_t event_data1;
8394 /* Time stamp for error event */
8395 #define HWRM_ASYNC_EVENT_CMPL_HWRM_ERROR_EVENT_DATA1_TIMESTAMP \
8399 /*******************
8401 *******************/
8404 /* hwrm_func_reset_input (size:192b/24B) */
8405 struct hwrm_func_reset_input {
8406 /* The HWRM command request type. */
8409 * The completion ring to send the completion event on. This should
8410 * be the NQ ID returned from the `nq_alloc` HWRM command.
8414 * The sequence ID is used by the driver for tracking multiple
8415 * commands. This ID is treated as opaque data by the firmware and
8416 * the value is returned in the `hwrm_resp_hdr` upon completion.
8420 * The target ID of the command:
8421 * * 0x0-0xFFF8 - The function ID
8422 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
8423 * * 0xFFFD - Reserved for user-space HWRM interface
8428 * A physical address pointer pointing to a host buffer that the
8429 * command's response data will be written. This can be either a host
8430 * physical address (HPA) or a guest physical address (GPA) and must
8431 * point to a physically contiguous block of memory.
8436 * This bit must be '1' for the vf_id_valid field to be
8439 #define HWRM_FUNC_RESET_INPUT_ENABLES_VF_ID_VALID UINT32_C(0x1)
8441 * The ID of the VF that this PF is trying to reset.
8442 * Only the parent PF shall be allowed to reset a child VF.
8444 * A parent PF driver shall use this field only when a specific child VF
8445 * is requested to be reset.
8448 /* This value indicates the level of a function reset. */
8449 uint8_t func_reset_level;
8451 * Reset the caller function and its children VFs (if any). If no
8452 * children functions exist, then reset the caller function only.
8454 #define HWRM_FUNC_RESET_INPUT_FUNC_RESET_LEVEL_RESETALL \
8456 /* Reset the caller function only */
8457 #define HWRM_FUNC_RESET_INPUT_FUNC_RESET_LEVEL_RESETME \
8460 * Reset all children VFs of the caller function driver if the
8461 * caller is a PF driver.
8462 * It is an error to specify this level by a VF driver.
8463 * It is an error to specify this level by a PF driver with
8466 #define HWRM_FUNC_RESET_INPUT_FUNC_RESET_LEVEL_RESETCHILDREN \
8469 * Reset a specific VF of the caller function driver if the caller
8470 * is the parent PF driver.
8471 * It is an error to specify this level by a VF driver.
8472 * It is an error to specify this level by a PF driver that is not
8473 * the parent of the VF that is being requested to reset.
8475 #define HWRM_FUNC_RESET_INPUT_FUNC_RESET_LEVEL_RESETVF \
8477 #define HWRM_FUNC_RESET_INPUT_FUNC_RESET_LEVEL_LAST \
8478 HWRM_FUNC_RESET_INPUT_FUNC_RESET_LEVEL_RESETVF
8482 /* hwrm_func_reset_output (size:128b/16B) */
8483 struct hwrm_func_reset_output {
8484 /* The specific error status for the command. */
8485 uint16_t error_code;
8486 /* The HWRM command request type. */
8488 /* The sequence ID from the original command. */
8490 /* The length of the response data in number of bytes. */
8492 uint8_t unused_0[7];
8494 * This field is used in Output records to indicate that the output
8495 * is completely written to RAM. This field should be read as '1'
8496 * to indicate that the output has been completely written.
8497 * When writing a command completion or response to an internal processor,
8498 * the order of writes has to be such that this field is written last.
8503 /********************
8504 * hwrm_func_getfid *
8505 ********************/
8508 /* hwrm_func_getfid_input (size:192b/24B) */
8509 struct hwrm_func_getfid_input {
8510 /* The HWRM command request type. */
8513 * The completion ring to send the completion event on. This should
8514 * be the NQ ID returned from the `nq_alloc` HWRM command.
8518 * The sequence ID is used by the driver for tracking multiple
8519 * commands. This ID is treated as opaque data by the firmware and
8520 * the value is returned in the `hwrm_resp_hdr` upon completion.
8524 * The target ID of the command:
8525 * * 0x0-0xFFF8 - The function ID
8526 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
8527 * * 0xFFFD - Reserved for user-space HWRM interface
8532 * A physical address pointer pointing to a host buffer that the
8533 * command's response data will be written. This can be either a host
8534 * physical address (HPA) or a guest physical address (GPA) and must
8535 * point to a physically contiguous block of memory.
8540 * This bit must be '1' for the pci_id field to be
8543 #define HWRM_FUNC_GETFID_INPUT_ENABLES_PCI_ID UINT32_C(0x1)
8545 * This value is the PCI ID of the queried function.
8546 * If ARI is enabled, then it is
8547 * Bus Number (8b):Function Number(8b). Otherwise, it is
8548 * Bus Number (8b):Device Number (5b):Function Number(3b).
8551 uint8_t unused_0[2];
8554 /* hwrm_func_getfid_output (size:128b/16B) */
8555 struct hwrm_func_getfid_output {
8556 /* The specific error status for the command. */
8557 uint16_t error_code;
8558 /* The HWRM command request type. */
8560 /* The sequence ID from the original command. */
8562 /* The length of the response data in number of bytes. */
8565 * FID value. This value is used to identify operations on the PCI
8566 * bus as belonging to a particular PCI function.
8569 uint8_t unused_0[5];
8571 * This field is used in Output records to indicate that the output
8572 * is completely written to RAM. This field should be read as '1'
8573 * to indicate that the output has been completely written.
8574 * When writing a command completion or response to an internal processor,
8575 * the order of writes has to be such that this field is written last.
8580 /**********************
8581 * hwrm_func_vf_alloc *
8582 **********************/
8585 /* hwrm_func_vf_alloc_input (size:192b/24B) */
8586 struct hwrm_func_vf_alloc_input {
8587 /* The HWRM command request type. */
8590 * The completion ring to send the completion event on. This should
8591 * be the NQ ID returned from the `nq_alloc` HWRM command.
8595 * The sequence ID is used by the driver for tracking multiple
8596 * commands. This ID is treated as opaque data by the firmware and
8597 * the value is returned in the `hwrm_resp_hdr` upon completion.
8601 * The target ID of the command:
8602 * * 0x0-0xFFF8 - The function ID
8603 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
8604 * * 0xFFFD - Reserved for user-space HWRM interface
8609 * A physical address pointer pointing to a host buffer that the
8610 * command's response data will be written. This can be either a host
8611 * physical address (HPA) or a guest physical address (GPA) and must
8612 * point to a physically contiguous block of memory.
8617 * This bit must be '1' for the first_vf_id field to be
8620 #define HWRM_FUNC_VF_ALLOC_INPUT_ENABLES_FIRST_VF_ID UINT32_C(0x1)
8622 * This value is used to identify a Virtual Function (VF).
8623 * The scope of VF ID is local within a PF.
8625 uint16_t first_vf_id;
8626 /* The number of virtual functions requested. */
8630 /* hwrm_func_vf_alloc_output (size:128b/16B) */
8631 struct hwrm_func_vf_alloc_output {
8632 /* The specific error status for the command. */
8633 uint16_t error_code;
8634 /* The HWRM command request type. */
8636 /* The sequence ID from the original command. */
8638 /* The length of the response data in number of bytes. */
8640 /* The ID of the first VF allocated. */
8641 uint16_t first_vf_id;
8642 uint8_t unused_0[5];
8644 * This field is used in Output records to indicate that the output
8645 * is completely written to RAM. This field should be read as '1'
8646 * to indicate that the output has been completely written.
8647 * When writing a command completion or response to an internal processor,
8648 * the order of writes has to be such that this field is written last.
8653 /*********************
8654 * hwrm_func_vf_free *
8655 *********************/
8658 /* hwrm_func_vf_free_input (size:192b/24B) */
8659 struct hwrm_func_vf_free_input {
8660 /* The HWRM command request type. */
8663 * The completion ring to send the completion event on. This should
8664 * be the NQ ID returned from the `nq_alloc` HWRM command.
8668 * The sequence ID is used by the driver for tracking multiple
8669 * commands. This ID is treated as opaque data by the firmware and
8670 * the value is returned in the `hwrm_resp_hdr` upon completion.
8674 * The target ID of the command:
8675 * * 0x0-0xFFF8 - The function ID
8676 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
8677 * * 0xFFFD - Reserved for user-space HWRM interface
8682 * A physical address pointer pointing to a host buffer that the
8683 * command's response data will be written. This can be either a host
8684 * physical address (HPA) or a guest physical address (GPA) and must
8685 * point to a physically contiguous block of memory.
8690 * This bit must be '1' for the first_vf_id field to be
8693 #define HWRM_FUNC_VF_FREE_INPUT_ENABLES_FIRST_VF_ID UINT32_C(0x1)
8695 * This value is used to identify a Virtual Function (VF).
8696 * The scope of VF ID is local within a PF.
8698 uint16_t first_vf_id;
8700 * The number of virtual functions requested.
8701 * 0xFFFF - Cleanup all children of this PF.
8706 /* hwrm_func_vf_free_output (size:128b/16B) */
8707 struct hwrm_func_vf_free_output {
8708 /* The specific error status for the command. */
8709 uint16_t error_code;
8710 /* The HWRM command request type. */
8712 /* The sequence ID from the original command. */
8714 /* The length of the response data in number of bytes. */
8716 uint8_t unused_0[7];
8718 * This field is used in Output records to indicate that the output
8719 * is completely written to RAM. This field should be read as '1'
8720 * to indicate that the output has been completely written.
8721 * When writing a command completion or response to an internal processor,
8722 * the order of writes has to be such that this field is written last.
8727 /********************
8728 * hwrm_func_vf_cfg *
8729 ********************/
8732 /* hwrm_func_vf_cfg_input (size:448b/56B) */
8733 struct hwrm_func_vf_cfg_input {
8734 /* The HWRM command request type. */
8737 * The completion ring to send the completion event on. This should
8738 * be the NQ ID returned from the `nq_alloc` HWRM command.
8742 * The sequence ID is used by the driver for tracking multiple
8743 * commands. This ID is treated as opaque data by the firmware and
8744 * the value is returned in the `hwrm_resp_hdr` upon completion.
8748 * The target ID of the command:
8749 * * 0x0-0xFFF8 - The function ID
8750 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
8751 * * 0xFFFD - Reserved for user-space HWRM interface
8756 * A physical address pointer pointing to a host buffer that the
8757 * command's response data will be written. This can be either a host
8758 * physical address (HPA) or a guest physical address (GPA) and must
8759 * point to a physically contiguous block of memory.
8764 * This bit must be '1' for the mtu field to be
8767 #define HWRM_FUNC_VF_CFG_INPUT_ENABLES_MTU \
8770 * This bit must be '1' for the guest_vlan field to be
8773 #define HWRM_FUNC_VF_CFG_INPUT_ENABLES_GUEST_VLAN \
8776 * This bit must be '1' for the async_event_cr field to be
8779 #define HWRM_FUNC_VF_CFG_INPUT_ENABLES_ASYNC_EVENT_CR \
8782 * This bit must be '1' for the dflt_mac_addr field to be
8785 #define HWRM_FUNC_VF_CFG_INPUT_ENABLES_DFLT_MAC_ADDR \
8788 * This bit must be '1' for the num_rsscos_ctxs field to be
8791 #define HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_RSSCOS_CTXS \
8794 * This bit must be '1' for the num_cmpl_rings field to be
8797 #define HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_CMPL_RINGS \
8800 * This bit must be '1' for the num_tx_rings field to be
8803 #define HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_TX_RINGS \
8806 * This bit must be '1' for the num_rx_rings field to be
8809 #define HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_RX_RINGS \
8812 * This bit must be '1' for the num_l2_ctxs field to be
8815 #define HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_L2_CTXS \
8818 * This bit must be '1' for the num_vnics field to be
8821 #define HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_VNICS \
8824 * This bit must be '1' for the num_stat_ctxs field to be
8827 #define HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_STAT_CTXS \
8830 * This bit must be '1' for the num_hw_ring_grps field to be
8833 #define HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_HW_RING_GRPS \
8836 * The maximum transmission unit requested on the function.
8837 * The HWRM should make sure that the mtu of
8838 * the function does not exceed the mtu of the physical
8839 * port that this function is associated with.
8841 * In addition to requesting mtu per function, it is
8842 * possible to configure mtu per transmit ring.
8843 * By default, the mtu of each transmit ring associated
8844 * with a function is equal to the mtu of the function.
8845 * The HWRM should make sure that the mtu of each transmit
8846 * ring that is assigned to a function has a valid mtu.
8850 * The guest VLAN for the function being configured.
8851 * This field's format is same as 802.1Q Tag's
8852 * Tag Control Information (TCI) format that includes both
8853 * Priority Code Point (PCP) and VLAN Identifier (VID).
8855 uint16_t guest_vlan;
8857 * ID of the target completion ring for receiving asynchronous
8858 * event completions. If this field is not valid, then the
8859 * HWRM shall use the default completion ring of the function
8860 * that is being configured as the target completion ring for
8861 * providing any asynchronous event completions for that
8863 * If this field is valid, then the HWRM shall use the
8864 * completion ring identified by this ID as the target
8865 * completion ring for providing any asynchronous event
8866 * completions for the function that is being configured.
8868 uint16_t async_event_cr;
8870 * This value is the current MAC address requested by the VF
8871 * driver to be configured on this VF. A value of
8872 * 00-00-00-00-00-00 indicates no MAC address configuration
8873 * is requested by the VF driver.
8874 * The parent PF driver may reject or overwrite this
8877 uint8_t dflt_mac_addr[6];
8880 * This bit requests that the firmware test to see if all the assets
8881 * requested in this command (i.e. number of TX rings) are available.
8882 * The firmware will return an error if the requested assets are
8883 * not available. The firwmare will NOT reserve the assets if they
8886 #define HWRM_FUNC_VF_CFG_INPUT_FLAGS_TX_ASSETS_TEST \
8889 * This bit requests that the firmware test to see if all the assets
8890 * requested in this command (i.e. number of RX rings) are available.
8891 * The firmware will return an error if the requested assets are
8892 * not available. The firwmare will NOT reserve the assets if they
8895 #define HWRM_FUNC_VF_CFG_INPUT_FLAGS_RX_ASSETS_TEST \
8898 * This bit requests that the firmware test to see if all the assets
8899 * requested in this command (i.e. number of CMPL rings) are available.
8900 * The firmware will return an error if the requested assets are
8901 * not available. The firwmare will NOT reserve the assets if they
8904 #define HWRM_FUNC_VF_CFG_INPUT_FLAGS_CMPL_ASSETS_TEST \
8907 * This bit requests that the firmware test to see if all the assets
8908 * requested in this command (i.e. number of RSS ctx) are available.
8909 * The firmware will return an error if the requested assets are
8910 * not available. The firwmare will NOT reserve the assets if they
8913 #define HWRM_FUNC_VF_CFG_INPUT_FLAGS_RSSCOS_CTX_ASSETS_TEST \
8916 * This bit requests that the firmware test to see if all the assets
8917 * requested in this command (i.e. number of ring groups) are available.
8918 * The firmware will return an error if the requested assets are
8919 * not available. The firwmare will NOT reserve the assets if they
8922 #define HWRM_FUNC_VF_CFG_INPUT_FLAGS_RING_GRP_ASSETS_TEST \
8925 * This bit requests that the firmware test to see if all the assets
8926 * requested in this command (i.e. number of stat ctx) are available.
8927 * The firmware will return an error if the requested assets are
8928 * not available. The firwmare will NOT reserve the assets if they
8931 #define HWRM_FUNC_VF_CFG_INPUT_FLAGS_STAT_CTX_ASSETS_TEST \
8934 * This bit requests that the firmware test to see if all the assets
8935 * requested in this command (i.e. number of VNICs) are available.
8936 * The firmware will return an error if the requested assets are
8937 * not available. The firwmare will NOT reserve the assets if they
8940 #define HWRM_FUNC_VF_CFG_INPUT_FLAGS_VNIC_ASSETS_TEST \
8943 * This bit requests that the firmware test to see if all the assets
8944 * requested in this command (i.e. number of L2 ctx) are available.
8945 * The firmware will return an error if the requested assets are
8946 * not available. The firwmare will NOT reserve the assets if they
8949 #define HWRM_FUNC_VF_CFG_INPUT_FLAGS_L2_CTX_ASSETS_TEST \
8952 * If this bit is set to 1, the VF driver is requesting FW to enable
8953 * PPP TX PUSH feature on all the TX rings specified in the
8954 * num_tx_rings field. By default, the PPP TX push feature is
8955 * disabled for all the TX rings of the VF. This flag is ignored if
8956 * the num_tx_rings field is not specified or the VF doesn't support
8957 * PPP tx push feature.
8959 #define HWRM_FUNC_VF_CFG_INPUT_FLAGS_PPP_PUSH_MODE_ENABLE \
8962 * If this bit is set to 1, the VF driver is requesting FW to disable
8963 * PPP TX PUSH feature on all the TX rings of the VF. This flag is
8964 * ignored if the VF doesn't support PPP tx push feature.
8966 #define HWRM_FUNC_VF_CFG_INPUT_FLAGS_PPP_PUSH_MODE_DISABLE \
8968 /* The number of RSS/COS contexts requested for the VF. */
8969 uint16_t num_rsscos_ctxs;
8970 /* The number of completion rings requested for the VF. */
8971 uint16_t num_cmpl_rings;
8972 /* The number of transmit rings requested for the VF. */
8973 uint16_t num_tx_rings;
8974 /* The number of receive rings requested for the VF. */
8975 uint16_t num_rx_rings;
8976 /* The number of L2 contexts requested for the VF. */
8977 uint16_t num_l2_ctxs;
8978 /* The number of vnics requested for the VF. */
8980 /* The number of statistic contexts requested for the VF. */
8981 uint16_t num_stat_ctxs;
8982 /* The number of HW ring groups requested for the VF. */
8983 uint16_t num_hw_ring_grps;
8984 uint8_t unused_0[4];
8987 /* hwrm_func_vf_cfg_output (size:128b/16B) */
8988 struct hwrm_func_vf_cfg_output {
8989 /* The specific error status for the command. */
8990 uint16_t error_code;
8991 /* The HWRM command request type. */
8993 /* The sequence ID from the original command. */
8995 /* The length of the response data in number of bytes. */
8997 uint8_t unused_0[7];
8999 * This field is used in Output records to indicate that the output
9000 * is completely written to RAM. This field should be read as '1'
9001 * to indicate that the output has been completely written.
9002 * When writing a command completion or response to an internal processor,
9003 * the order of writes has to be such that this field is written last.
9008 /*******************
9010 *******************/
9013 /* hwrm_func_qcaps_input (size:192b/24B) */
9014 struct hwrm_func_qcaps_input {
9015 /* The HWRM command request type. */
9018 * The completion ring to send the completion event on. This should
9019 * be the NQ ID returned from the `nq_alloc` HWRM command.
9023 * The sequence ID is used by the driver for tracking multiple
9024 * commands. This ID is treated as opaque data by the firmware and
9025 * the value is returned in the `hwrm_resp_hdr` upon completion.
9029 * The target ID of the command:
9030 * * 0x0-0xFFF8 - The function ID
9031 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
9032 * * 0xFFFD - Reserved for user-space HWRM interface
9037 * A physical address pointer pointing to a host buffer that the
9038 * command's response data will be written. This can be either a host
9039 * physical address (HPA) or a guest physical address (GPA) and must
9040 * point to a physically contiguous block of memory.
9044 * Function ID of the function that is being queried.
9045 * 0xFF... (All Fs) if the query is for the requesting
9047 * 0xFFFE (REQUESTING_PARENT_FID) This is a special FID
9048 * to be used by a trusted VF to query its parent PF.
9051 uint8_t unused_0[6];
9054 /* hwrm_func_qcaps_output (size:704b/88B) */
9055 struct hwrm_func_qcaps_output {
9056 /* The specific error status for the command. */
9057 uint16_t error_code;
9058 /* The HWRM command request type. */
9060 /* The sequence ID from the original command. */
9062 /* The length of the response data in number of bytes. */
9065 * FID value. This value is used to identify operations on the PCI
9066 * bus as belonging to a particular PCI function.
9070 * Port ID of port that this function is associated with.
9071 * Valid only for the PF.
9072 * 0xFF... (All Fs) if this function is not associated with
9074 * 0xFF... (All Fs) if this function is called from a VF.
9078 /* If 1, then Push mode is supported on this function. */
9079 #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_PUSH_MODE_SUPPORTED \
9082 * If 1, then the global MSI-X auto-masking is enabled for the
9085 #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_GLOBAL_MSIX_AUTOMASKING \
9088 * If 1, then the Precision Time Protocol (PTP) processing
9089 * is supported on this function.
9090 * The HWRM should enable PTP on only a single Physical
9091 * Function (PF) per port.
9093 #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_PTP_SUPPORTED \
9096 * If 1, then RDMA over Converged Ethernet (RoCE) v1
9097 * is supported on this function.
9099 #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_ROCE_V1_SUPPORTED \
9102 * If 1, then RDMA over Converged Ethernet (RoCE) v2
9103 * is supported on this function.
9105 #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_ROCE_V2_SUPPORTED \
9108 * If 1, then control and configuration of WoL magic packet
9109 * are supported on this function.
9111 #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_WOL_MAGICPKT_SUPPORTED \
9114 * If 1, then control and configuration of bitmap pattern
9115 * packet are supported on this function.
9117 #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_WOL_BMP_SUPPORTED \
9120 * If set to 1, then the control and configuration of rate limit
9121 * of an allocated TX ring on the queried function is supported.
9123 #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_TX_RING_RL_SUPPORTED \
9126 * If 1, then control and configuration of minimum and
9127 * maximum bandwidths are supported on the queried function.
9129 #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_TX_BW_CFG_SUPPORTED \
9132 * If the query is for a VF, then this flag shall be ignored.
9133 * If this query is for a PF and this flag is set to 1,
9134 * then the PF has the capability to set the rate limits
9135 * on the TX rings of its children VFs.
9136 * If this query is for a PF and this flag is set to 0, then
9137 * the PF does not have the capability to set the rate limits
9138 * on the TX rings of its children VFs.
9140 #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_VF_TX_RING_RL_SUPPORTED \
9143 * If the query is for a VF, then this flag shall be ignored.
9144 * If this query is for a PF and this flag is set to 1,
9145 * then the PF has the capability to set the minimum and/or
9146 * maximum bandwidths for its children VFs.
9147 * If this query is for a PF and this flag is set to 0, then
9148 * the PF does not have the capability to set the minimum or
9149 * maximum bandwidths for its children VFs.
9151 #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_VF_BW_CFG_SUPPORTED \
9154 * Standard TX Ring mode is used for the allocation of TX ring
9155 * and underlying scheduling resources that allow bandwidth
9156 * reservation and limit settings on the queried function.
9157 * If set to 1, then standard TX ring mode is supported
9158 * on the queried function.
9159 * If set to 0, then standard TX ring mode is not available
9160 * on the queried function.
9162 #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_STD_TX_RING_MODE_SUPPORTED \
9165 * If the query is for a VF, then this flag shall be ignored,
9166 * If this query is for a PF and this flag is set to 1,
9167 * then the PF has the capability to detect GENEVE tunnel
9170 #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_GENEVE_TUN_FLAGS_SUPPORTED \
9173 * If the query is for a VF, then this flag shall be ignored,
9174 * If this query is for a PF and this flag is set to 1,
9175 * then the PF has the capability to detect NVGRE tunnel
9178 #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_NVGRE_TUN_FLAGS_SUPPORTED \
9181 * If the query is for a VF, then this flag shall be ignored,
9182 * If this query is for a PF and this flag is set to 1,
9183 * then the PF has the capability to detect GRE tunnel
9186 #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_GRE_TUN_FLAGS_SUPPORTED \
9189 * If the query is for a VF, then this flag shall be ignored,
9190 * If this query is for a PF and this flag is set to 1,
9191 * then the PF has the capability to detect MPLS tunnel
9194 #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_MPLS_TUN_FLAGS_SUPPORTED \
9197 * If the query is for a VF, then this flag shall be ignored,
9198 * If this query is for a PF and this flag is set to 1,
9199 * then the PF has the capability to support pcie stats.
9201 #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_PCIE_STATS_SUPPORTED \
9204 * If the query is for a VF, then this flag shall be ignored,
9205 * If this query is for a PF and this flag is set to 1,
9206 * then the PF has the capability to adopt the VF's belonging
9209 #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_ADOPTED_PF_SUPPORTED \
9212 * If the query is for a VF, then this flag shall be ignored,
9213 * If this query is for a PF and this flag is set to 1,
9214 * then the PF has the administrative privilege to configure another PF
9216 #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_ADMIN_PF_SUPPORTED \
9219 * If the query is for a VF, then this flag shall be ignored.
9220 * If this query is for a PF and this flag is set to 1, then
9221 * the PF will know that the firmware has the capability to track
9222 * the virtual link status.
9224 #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_LINK_ADMIN_STATUS_SUPPORTED \
9227 * If 1, then this function supports the push mode that uses
9228 * write combine buffers and the long inline tx buffer descriptor.
9230 #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_WCB_PUSH_MODE \
9233 * If 1, then FW has capability to allocate TX rings dynamically
9234 * in ring alloc even if PF reserved pool is zero.
9235 * This bit will be used only for PFs.
9237 #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_DYNAMIC_TX_RING_ALLOC \
9240 * When this bit is '1', it indicates that core firmware is
9241 * capable of Hot Reset.
9243 #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_HOT_RESET_CAPABLE \
9246 * This flag will be set to 1 by the FW if FW supports adapter error
9249 #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_ERROR_RECOVERY_CAPABLE \
9252 * If the query is for a VF, then this flag shall be ignored.
9253 * If this query is for a PF and this flag is set to 1, then
9254 * the PF has the capability to support extended stats.
9256 #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_EXT_STATS_SUPPORTED \
9259 * If the query is for a VF, then this flag shall be ignored.
9260 * If this query is for a PF and this flag is set to 1, then host
9261 * must initiate reset or reload (or fastboot) the firmware image
9262 * upon detection of device shutdown state.
9264 #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_ERR_RECOVER_RELOAD \
9267 * If the query is for a VF, then this flag (always set to 0) shall
9268 * be ignored. If this query is for a PF and this flag is set to 1,
9269 * host, when registered for the default vnic change async event,
9270 * receives async notification whenever a default vnic state is
9271 * changed for any of child or adopted VFs.
9273 #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_NOTIFY_VF_DEF_VNIC_CHNG_SUPPORTED \
9275 /* If set to 1, then the vlan acceleration for TX is disabled. */
9276 #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_VLAN_ACCELERATION_TX_DISABLED \
9279 * When this bit is '1', it indicates that core firmware supports
9280 * DBG_COREDUMP_XXX commands.
9282 #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_COREDUMP_CMD_SUPPORTED \
9283 UINT32_C(0x10000000)
9285 * When this bit is '1', it indicates that core firmware supports
9286 * DBG_CRASHDUMP_XXX commands.
9288 #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_CRASHDUMP_CMD_SUPPORTED \
9289 UINT32_C(0x20000000)
9291 * If the query is for a VF, then this flag should be ignored.
9292 * If the query is for a PF and this flag is set to 1, then
9293 * the PF has the capability to support retrieval of
9294 * rx_port_stats_ext_pfc_wd statistics (supported by the PFC
9295 * WatchDog feature) via the hwrm_port_qstats_ext_pfc_wd command.
9296 * If this flag is set to 1, only that (supported) command should
9297 * be used for retrieval of PFC related statistics (rather than
9298 * hwrm_port_qstats_ext command, which could previously be used).
9300 #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_PFC_WD_STATS_SUPPORTED \
9301 UINT32_C(0x40000000)
9303 * When this bit is '1', it indicates that core firmware supports
9306 #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_DBG_QCAPS_CMD_SUPPORTED \
9307 UINT32_C(0x80000000)
9309 * This value is current MAC address configured for this
9310 * function. A value of 00-00-00-00-00-00 indicates no
9311 * MAC address is currently configured.
9313 uint8_t mac_address[6];
9315 * The maximum number of RSS/COS contexts that can be
9316 * allocated to the function.
9318 uint16_t max_rsscos_ctx;
9320 * The maximum number of completion rings that can be
9321 * allocated to the function.
9323 uint16_t max_cmpl_rings;
9325 * The maximum number of transmit rings that can be
9326 * allocated to the function.
9328 uint16_t max_tx_rings;
9330 * The maximum number of receive rings that can be
9331 * allocated to the function.
9333 uint16_t max_rx_rings;
9335 * The maximum number of L2 contexts that can be
9336 * allocated to the function.
9338 uint16_t max_l2_ctxs;
9340 * The maximum number of VNICs that can be
9341 * allocated to the function.
9345 * The identifier for the first VF enabled on a PF. This
9346 * is valid only on the PF with SR-IOV enabled.
9347 * 0xFF... (All Fs) if this command is called on a PF with
9348 * SR-IOV disabled or on a VF.
9350 uint16_t first_vf_id;
9352 * The maximum number of VFs that can be
9353 * allocated to the function. This is valid only on the
9354 * PF with SR-IOV enabled. 0xFF... (All Fs) if this
9355 * command is called on a PF with SR-IOV disabled or
9360 * The maximum number of statistic contexts that can be
9361 * allocated to the function.
9363 uint16_t max_stat_ctx;
9365 * The maximum number of Encapsulation records that can be
9366 * offloaded by this function.
9368 uint32_t max_encap_records;
9370 * The maximum number of decapsulation records that can
9371 * be offloaded by this function.
9373 uint32_t max_decap_records;
9375 * The maximum number of Exact Match (EM) flows that can be
9376 * offloaded by this function on the TX side.
9378 uint32_t max_tx_em_flows;
9380 * The maximum number of Wildcard Match (WM) flows that can
9381 * be offloaded by this function on the TX side.
9383 uint32_t max_tx_wm_flows;
9385 * The maximum number of Exact Match (EM) flows that can be
9386 * offloaded by this function on the RX side.
9388 uint32_t max_rx_em_flows;
9390 * The maximum number of Wildcard Match (WM) flows that can
9391 * be offloaded by this function on the RX side.
9393 uint32_t max_rx_wm_flows;
9395 * The maximum number of multicast filters that can
9396 * be supported by this function on the RX side.
9398 uint32_t max_mcast_filters;
9400 * The maximum value of flow_id that can be supported
9401 * in completion records.
9403 uint32_t max_flow_id;
9405 * The maximum number of HW ring groups that can be
9406 * supported on this function.
9408 uint32_t max_hw_ring_grps;
9410 * The maximum number of strict priority transmit rings
9411 * that can be allocated to the function.
9412 * This number indicates the maximum number of TX rings
9413 * that can be assigned strict priorities out of the
9414 * maximum number of TX rings that can be allocated
9415 * (max_tx_rings) to the function.
9417 uint16_t max_sp_tx_rings;
9418 uint8_t unused_0[2];
9421 * If 1, the device can be configured to set the ECN bits in the
9422 * IP header of received packets if the receive queue length
9423 * exceeds a given threshold.
9425 #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_EXT_ECN_MARK_SUPPORTED \
9428 * If 1, the device can report the number of received packets
9429 * that it marked as having experienced congestion.
9431 #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_EXT_ECN_STATS_SUPPORTED \
9434 * If 1, the device can report extended hw statistics (including
9435 * additional tpa statistics).
9437 #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_EXT_EXT_HW_STATS_SUPPORTED \
9440 * If set to 1, then the core firmware has support to enable/
9441 * disable hot reset support for interface dynamically through
9444 #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_EXT_HOT_RESET_IF_SUPPORT \
9446 /* If 1, the proxy mode is supported on this function */
9447 #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_EXT_PROXY_MODE_SUPPORT \
9450 * If 1, the tx rings source interface override feature is supported
9453 #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_EXT_TX_PROXY_SRC_INTF_OVERRIDE_SUPPORT \
9456 * If 1, the device supports scheduler queues. SCHQs can be managed
9457 * using RING_SCHQ_ALLOC/CFG/FREE commands.
9459 #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_EXT_SCHQ_SUPPORTED \
9462 * If set to 1, then this function supports the TX push mode that
9463 * uses ping-pong buffers from the push pages.
9465 #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_EXT_PPP_PUSH_MODE_SUPPORTED \
9467 /* The maximum number of SCHQs supported by this device. */
9469 uint8_t unused_1[2];
9471 * This field is used in Output records to indicate that the output
9472 * is completely written to RAM. This field should be read as '1'
9473 * to indicate that the output has been completely written.
9474 * When writing a command completion or response to an internal processor,
9475 * the order of writes has to be such that this field is written last.
9485 /* hwrm_func_qcfg_input (size:192b/24B) */
9486 struct hwrm_func_qcfg_input {
9487 /* The HWRM command request type. */
9490 * The completion ring to send the completion event on. This should
9491 * be the NQ ID returned from the `nq_alloc` HWRM command.
9495 * The sequence ID is used by the driver for tracking multiple
9496 * commands. This ID is treated as opaque data by the firmware and
9497 * the value is returned in the `hwrm_resp_hdr` upon completion.
9501 * The target ID of the command:
9502 * * 0x0-0xFFF8 - The function ID
9503 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
9504 * * 0xFFFD - Reserved for user-space HWRM interface
9509 * A physical address pointer pointing to a host buffer that the
9510 * command's response data will be written. This can be either a host
9511 * physical address (HPA) or a guest physical address (GPA) and must
9512 * point to a physically contiguous block of memory.
9516 * Function ID of the function that is being queried.
9517 * 0xFF... (All Fs) if the query is for the requesting
9519 * 0xFFFE (REQUESTING_PARENT_FID) This is a special FID
9520 * to be used by a trusted VF to query its parent PF.
9523 uint8_t unused_0[6];
9526 /* hwrm_func_qcfg_output (size:768b/96B) */
9527 struct hwrm_func_qcfg_output {
9528 /* The specific error status for the command. */
9529 uint16_t error_code;
9530 /* The HWRM command request type. */
9532 /* The sequence ID from the original command. */
9534 /* The length of the response data in number of bytes. */
9537 * FID value. This value is used to identify operations on the PCI
9538 * bus as belonging to a particular PCI function.
9542 * Port ID of port that this function is associated with.
9543 * 0xFF... (All Fs) if this function is not associated with
9548 * This value is the current VLAN setting for this
9549 * function. The value of 0 for this field indicates
9550 * no priority tagging or VLAN is used.
9551 * This field's format is same as 802.1Q Tag's
9552 * Tag Control Information (TCI) format that includes both
9553 * Priority Code Point (PCP) and VLAN Identifier (VID).
9558 * If 1, then magic packet based Out-Of-Box WoL is enabled on
9559 * the port associated with this function.
9561 #define HWRM_FUNC_QCFG_OUTPUT_FLAGS_OOB_WOL_MAGICPKT_ENABLED \
9564 * If 1, then bitmap pattern based Out-Of-Box WoL packet is enabled
9565 * on the port associated with this function.
9567 #define HWRM_FUNC_QCFG_OUTPUT_FLAGS_OOB_WOL_BMP_ENABLED \
9570 * If set to 1, then FW based DCBX agent is enabled and running on
9571 * the port associated with this function.
9572 * If set to 0, then DCBX agent is not running in the firmware.
9574 #define HWRM_FUNC_QCFG_OUTPUT_FLAGS_FW_DCBX_AGENT_ENABLED \
9577 * Standard TX Ring mode is used for the allocation of TX ring
9578 * and underlying scheduling resources that allow bandwidth
9579 * reservation and limit settings on the queried function.
9580 * If set to 1, then standard TX ring mode is enabled
9581 * on the queried function.
9582 * If set to 0, then the standard TX ring mode is disabled
9583 * on the queried function. In this extended TX ring resource
9584 * mode, the minimum and maximum bandwidth settings are not
9585 * supported to allow the allocation of TX rings to span multiple
9588 #define HWRM_FUNC_QCFG_OUTPUT_FLAGS_STD_TX_RING_MODE_ENABLED \
9591 * If set to 1 then FW based LLDP agent is enabled and running on
9592 * the port associated with this function.
9593 * If set to 0 then the LLDP agent is not running in the firmware.
9595 #define HWRM_FUNC_QCFG_OUTPUT_FLAGS_FW_LLDP_AGENT_ENABLED \
9598 * If set to 1, then multi-host mode is active for this function.
9599 * If set to 0, then multi-host mode is inactive for this function
9600 * or not applicable for this device.
9602 #define HWRM_FUNC_QCFG_OUTPUT_FLAGS_MULTI_HOST \
9605 * If the function that is being queried is a PF, then the HWRM shall
9606 * set this field to 0 and the HWRM client shall ignore this field.
9607 * If the function that is being queried is a VF, then the HWRM shall
9608 * set this field to 1 if the queried VF is trusted, otherwise the HWRM
9609 * shall set this field to 0.
9611 #define HWRM_FUNC_QCFG_OUTPUT_FLAGS_TRUSTED_VF \
9614 * If set to 1, then secure mode is enabled for this function or device.
9615 * If set to 0, then secure mode is disabled (or normal mode) for this
9616 * function or device.
9618 #define HWRM_FUNC_QCFG_OUTPUT_FLAGS_SECURE_MODE_ENABLED \
9621 * If set to 1, then this PF is enabled with a preboot driver that
9622 * requires access to the legacy L2 ring model and legacy 32b
9623 * doorbells. If set to 0, then this PF is not allowed to use
9624 * the legacy L2 rings. This feature is not allowed on VFs and
9625 * is only relevant for devices that require a context backing
9628 #define HWRM_FUNC_QCFG_OUTPUT_FLAGS_PREBOOT_LEGACY_L2_RINGS \
9631 * If set to 1, then the firmware and all currently registered driver
9632 * instances support hot reset. The hot reset support will be updated
9633 * dynamically based on the driver interface advertisement.
9634 * If set to 0, then the adapter is not currently able to initiate
9637 #define HWRM_FUNC_QCFG_OUTPUT_FLAGS_HOT_RESET_ALLOWED \
9640 * If set to 1, then the PPP tx push mode is enabled for all the
9641 * reserved TX rings of this function. If set to 0, then PPP tx push
9642 * mode is disabled for all the reserved TX rings of this function.
9644 #define HWRM_FUNC_QCFG_OUTPUT_FLAGS_PPP_PUSH_MODE_ENABLED \
9647 * This value is current MAC address configured for this
9648 * function. A value of 00-00-00-00-00-00 indicates no
9649 * MAC address is currently configured.
9651 uint8_t mac_address[6];
9653 * This value is current PCI ID of this
9654 * function. If ARI is enabled, then it is
9655 * Bus Number (8b):Function Number(8b). Otherwise, it is
9656 * Bus Number (8b):Device Number (4b):Function Number(4b).
9657 * If multi-host mode is active, the 4 lsb will indicate
9658 * the PF index for this function.
9662 * The number of RSS/COS contexts currently
9663 * allocated to the function.
9665 uint16_t alloc_rsscos_ctx;
9667 * The number of completion rings currently allocated to
9668 * the function. This does not include the rings allocated
9669 * to any children functions if any.
9671 uint16_t alloc_cmpl_rings;
9673 * The number of transmit rings currently allocated to
9674 * the function. This does not include the rings allocated
9675 * to any children functions if any.
9677 uint16_t alloc_tx_rings;
9679 * The number of receive rings currently allocated to
9680 * the function. This does not include the rings allocated
9681 * to any children functions if any.
9683 uint16_t alloc_rx_rings;
9684 /* The allocated number of L2 contexts to the function. */
9685 uint16_t alloc_l2_ctx;
9686 /* The allocated number of vnics to the function. */
9687 uint16_t alloc_vnics;
9689 * The maximum transmission unit of the function.
9690 * If the reported mtu value is non-zero then it will used for the
9691 * rings allocated on this function. otherwise the default
9692 * value is used if ring MTU is not specified.
9696 * The maximum receive unit of the function.
9697 * For vnics allocated on this function, this default
9698 * value is used if vnic MRU is not specified.
9701 /* The statistics context assigned to a function. */
9702 uint16_t stat_ctx_id;
9704 * The HWRM shall return Unknown value for this field
9705 * when this command is used to query VF's configuration.
9707 uint8_t port_partition_type;
9708 /* Single physical function */
9709 #define HWRM_FUNC_QCFG_OUTPUT_PORT_PARTITION_TYPE_SPF UINT32_C(0x0)
9710 /* Multiple physical functions */
9711 #define HWRM_FUNC_QCFG_OUTPUT_PORT_PARTITION_TYPE_MPFS UINT32_C(0x1)
9712 /* Network Partitioning 1.0 */
9713 #define HWRM_FUNC_QCFG_OUTPUT_PORT_PARTITION_TYPE_NPAR1_0 UINT32_C(0x2)
9714 /* Network Partitioning 1.5 */
9715 #define HWRM_FUNC_QCFG_OUTPUT_PORT_PARTITION_TYPE_NPAR1_5 UINT32_C(0x3)
9716 /* Network Partitioning 2.0 */
9717 #define HWRM_FUNC_QCFG_OUTPUT_PORT_PARTITION_TYPE_NPAR2_0 UINT32_C(0x4)
9719 #define HWRM_FUNC_QCFG_OUTPUT_PORT_PARTITION_TYPE_UNKNOWN \
9721 #define HWRM_FUNC_QCFG_OUTPUT_PORT_PARTITION_TYPE_LAST \
9722 HWRM_FUNC_QCFG_OUTPUT_PORT_PARTITION_TYPE_UNKNOWN
9724 * This field will indicate number of physical functions on this port_partition.
9725 * HWRM shall return unavail (i.e. value of 0) for this field
9726 * when this command is used to query VF's configuration or
9727 * from older firmware that doesn't support this field.
9729 uint8_t port_pf_cnt;
9730 /* number of PFs is not available */
9731 #define HWRM_FUNC_QCFG_OUTPUT_PORT_PF_CNT_UNAVAIL UINT32_C(0x0)
9732 #define HWRM_FUNC_QCFG_OUTPUT_PORT_PF_CNT_LAST \
9733 HWRM_FUNC_QCFG_OUTPUT_PORT_PF_CNT_UNAVAIL
9735 * The default VNIC ID assigned to a function that is
9738 uint16_t dflt_vnic_id;
9739 uint16_t max_mtu_configured;
9741 * Minimum BW allocated for this function.
9742 * The HWRM will translate this value into byte counter and
9743 * time interval used for the scheduler inside the device.
9744 * A value of 0 indicates the minimum bandwidth is not
9748 /* The bandwidth value. */
9749 #define HWRM_FUNC_QCFG_OUTPUT_MIN_BW_BW_VALUE_MASK \
9751 #define HWRM_FUNC_QCFG_OUTPUT_MIN_BW_BW_VALUE_SFT 0
9752 /* The granularity of the value (bits or bytes). */
9753 #define HWRM_FUNC_QCFG_OUTPUT_MIN_BW_SCALE \
9754 UINT32_C(0x10000000)
9755 /* Value is in bits. */
9756 #define HWRM_FUNC_QCFG_OUTPUT_MIN_BW_SCALE_BITS \
9757 (UINT32_C(0x0) << 28)
9758 /* Value is in bytes. */
9759 #define HWRM_FUNC_QCFG_OUTPUT_MIN_BW_SCALE_BYTES \
9760 (UINT32_C(0x1) << 28)
9761 #define HWRM_FUNC_QCFG_OUTPUT_MIN_BW_SCALE_LAST \
9762 HWRM_FUNC_QCFG_OUTPUT_MIN_BW_SCALE_BYTES
9763 /* bw_value_unit is 3 b */
9764 #define HWRM_FUNC_QCFG_OUTPUT_MIN_BW_BW_VALUE_UNIT_MASK \
9765 UINT32_C(0xe0000000)
9766 #define HWRM_FUNC_QCFG_OUTPUT_MIN_BW_BW_VALUE_UNIT_SFT 29
9767 /* Value is in Mb or MB (base 10). */
9768 #define HWRM_FUNC_QCFG_OUTPUT_MIN_BW_BW_VALUE_UNIT_MEGA \
9769 (UINT32_C(0x0) << 29)
9770 /* Value is in Kb or KB (base 10). */
9771 #define HWRM_FUNC_QCFG_OUTPUT_MIN_BW_BW_VALUE_UNIT_KILO \
9772 (UINT32_C(0x2) << 29)
9773 /* Value is in bits or bytes. */
9774 #define HWRM_FUNC_QCFG_OUTPUT_MIN_BW_BW_VALUE_UNIT_BASE \
9775 (UINT32_C(0x4) << 29)
9776 /* Value is in Gb or GB (base 10). */
9777 #define HWRM_FUNC_QCFG_OUTPUT_MIN_BW_BW_VALUE_UNIT_GIGA \
9778 (UINT32_C(0x6) << 29)
9779 /* Value is in 1/100th of a percentage of total bandwidth. */
9780 #define HWRM_FUNC_QCFG_OUTPUT_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 \
9781 (UINT32_C(0x1) << 29)
9783 #define HWRM_FUNC_QCFG_OUTPUT_MIN_BW_BW_VALUE_UNIT_INVALID \
9784 (UINT32_C(0x7) << 29)
9785 #define HWRM_FUNC_QCFG_OUTPUT_MIN_BW_BW_VALUE_UNIT_LAST \
9786 HWRM_FUNC_QCFG_OUTPUT_MIN_BW_BW_VALUE_UNIT_INVALID
9788 * Maximum BW allocated for this function.
9789 * The HWRM will translate this value into byte counter and
9790 * time interval used for the scheduler inside the device.
9791 * A value of 0 indicates that the maximum bandwidth is not
9795 /* The bandwidth value. */
9796 #define HWRM_FUNC_QCFG_OUTPUT_MAX_BW_BW_VALUE_MASK \
9798 #define HWRM_FUNC_QCFG_OUTPUT_MAX_BW_BW_VALUE_SFT 0
9799 /* The granularity of the value (bits or bytes). */
9800 #define HWRM_FUNC_QCFG_OUTPUT_MAX_BW_SCALE \
9801 UINT32_C(0x10000000)
9802 /* Value is in bits. */
9803 #define HWRM_FUNC_QCFG_OUTPUT_MAX_BW_SCALE_BITS \
9804 (UINT32_C(0x0) << 28)
9805 /* Value is in bytes. */
9806 #define HWRM_FUNC_QCFG_OUTPUT_MAX_BW_SCALE_BYTES \
9807 (UINT32_C(0x1) << 28)
9808 #define HWRM_FUNC_QCFG_OUTPUT_MAX_BW_SCALE_LAST \
9809 HWRM_FUNC_QCFG_OUTPUT_MAX_BW_SCALE_BYTES
9810 /* bw_value_unit is 3 b */
9811 #define HWRM_FUNC_QCFG_OUTPUT_MAX_BW_BW_VALUE_UNIT_MASK \
9812 UINT32_C(0xe0000000)
9813 #define HWRM_FUNC_QCFG_OUTPUT_MAX_BW_BW_VALUE_UNIT_SFT 29
9814 /* Value is in Mb or MB (base 10). */
9815 #define HWRM_FUNC_QCFG_OUTPUT_MAX_BW_BW_VALUE_UNIT_MEGA \
9816 (UINT32_C(0x0) << 29)
9817 /* Value is in Kb or KB (base 10). */
9818 #define HWRM_FUNC_QCFG_OUTPUT_MAX_BW_BW_VALUE_UNIT_KILO \
9819 (UINT32_C(0x2) << 29)
9820 /* Value is in bits or bytes. */
9821 #define HWRM_FUNC_QCFG_OUTPUT_MAX_BW_BW_VALUE_UNIT_BASE \
9822 (UINT32_C(0x4) << 29)
9823 /* Value is in Gb or GB (base 10). */
9824 #define HWRM_FUNC_QCFG_OUTPUT_MAX_BW_BW_VALUE_UNIT_GIGA \
9825 (UINT32_C(0x6) << 29)
9826 /* Value is in 1/100th of a percentage of total bandwidth. */
9827 #define HWRM_FUNC_QCFG_OUTPUT_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 \
9828 (UINT32_C(0x1) << 29)
9830 #define HWRM_FUNC_QCFG_OUTPUT_MAX_BW_BW_VALUE_UNIT_INVALID \
9831 (UINT32_C(0x7) << 29)
9832 #define HWRM_FUNC_QCFG_OUTPUT_MAX_BW_BW_VALUE_UNIT_LAST \
9833 HWRM_FUNC_QCFG_OUTPUT_MAX_BW_BW_VALUE_UNIT_INVALID
9835 * This value indicates the Edge virtual bridge mode for the
9836 * domain that this function belongs to.
9839 /* No Edge Virtual Bridging (EVB) */
9840 #define HWRM_FUNC_QCFG_OUTPUT_EVB_MODE_NO_EVB UINT32_C(0x0)
9841 /* Virtual Ethernet Bridge (VEB) */
9842 #define HWRM_FUNC_QCFG_OUTPUT_EVB_MODE_VEB UINT32_C(0x1)
9843 /* Virtual Ethernet Port Aggregator (VEPA) */
9844 #define HWRM_FUNC_QCFG_OUTPUT_EVB_MODE_VEPA UINT32_C(0x2)
9845 #define HWRM_FUNC_QCFG_OUTPUT_EVB_MODE_LAST \
9846 HWRM_FUNC_QCFG_OUTPUT_EVB_MODE_VEPA
9849 * This value indicates the PCIE device cache line size.
9850 * The cache line size allows the DMA writes to terminate and
9851 * start at the cache boundary.
9853 #define HWRM_FUNC_QCFG_OUTPUT_OPTIONS_CACHE_LINESIZE_MASK \
9855 #define HWRM_FUNC_QCFG_OUTPUT_OPTIONS_CACHE_LINESIZE_SFT 0
9856 /* Cache Line Size 64 bytes */
9857 #define HWRM_FUNC_QCFG_OUTPUT_OPTIONS_CACHE_LINESIZE_SIZE_64 \
9859 /* Cache Line Size 128 bytes */
9860 #define HWRM_FUNC_QCFG_OUTPUT_OPTIONS_CACHE_LINESIZE_SIZE_128 \
9862 #define HWRM_FUNC_QCFG_OUTPUT_OPTIONS_CACHE_LINESIZE_LAST \
9863 HWRM_FUNC_QCFG_OUTPUT_OPTIONS_CACHE_LINESIZE_SIZE_128
9864 /* This value is the virtual link admin state setting. */
9865 #define HWRM_FUNC_QCFG_OUTPUT_OPTIONS_LINK_ADMIN_STATE_MASK \
9867 #define HWRM_FUNC_QCFG_OUTPUT_OPTIONS_LINK_ADMIN_STATE_SFT 2
9868 /* Admin link state is in forced down mode. */
9869 #define HWRM_FUNC_QCFG_OUTPUT_OPTIONS_LINK_ADMIN_STATE_FORCED_DOWN \
9870 (UINT32_C(0x0) << 2)
9871 /* Admin link state is in forced up mode. */
9872 #define HWRM_FUNC_QCFG_OUTPUT_OPTIONS_LINK_ADMIN_STATE_FORCED_UP \
9873 (UINT32_C(0x1) << 2)
9874 /* Admin link state is in auto mode - follows the physical link state. */
9875 #define HWRM_FUNC_QCFG_OUTPUT_OPTIONS_LINK_ADMIN_STATE_AUTO \
9876 (UINT32_C(0x2) << 2)
9877 #define HWRM_FUNC_QCFG_OUTPUT_OPTIONS_LINK_ADMIN_STATE_LAST \
9878 HWRM_FUNC_QCFG_OUTPUT_OPTIONS_LINK_ADMIN_STATE_AUTO
9879 /* Reserved for future. */
9880 #define HWRM_FUNC_QCFG_OUTPUT_OPTIONS_RSVD_MASK \
9882 #define HWRM_FUNC_QCFG_OUTPUT_OPTIONS_RSVD_SFT 4
9884 * The number of VFs that are allocated to the function.
9885 * This is valid only on the PF with SR-IOV enabled.
9886 * 0xFF... (All Fs) if this command is called on a PF with
9887 * SR-IOV disabled or on a VF.
9891 * The number of allocated multicast filters for this
9892 * function on the RX side.
9894 uint32_t alloc_mcast_filters;
9896 * The number of allocated HW ring groups for this
9899 uint32_t alloc_hw_ring_grps;
9901 * The number of strict priority transmit rings out of
9902 * currently allocated TX rings to the function
9905 uint16_t alloc_sp_tx_rings;
9907 * The number of statistics contexts
9908 * currently reserved for the function.
9910 uint16_t alloc_stat_ctx;
9912 * This field specifies how many NQs are reserved for the PF.
9913 * Remaining NQs that belong to the PF are available for VFs.
9914 * Once a PF has created VFs, it cannot change how many NQs are
9915 * reserved for itself (since the NQs must be contiguous in HW).
9917 uint16_t alloc_msix;
9919 * The number of registered VF’s associated with the PF. This field
9920 * should be ignored when the request received on the VF interface.
9921 * This field will be updated on the PF interface to initiate
9922 * the unregister request on PF in the HOT Reset Process.
9924 uint16_t registered_vfs;
9926 * The size of the doorbell BAR in KBytes reserved for L2 including
9927 * any area that is shared between L2 and RoCE. The L2 driver
9928 * should only map the L2 portion of the doorbell BAR. Any rounding
9929 * of the BAR size to the native CPU page size should be performed
9930 * by the driver. If the value is zero, no special partitioning
9931 * of the doorbell BAR between L2 and RoCE is required.
9933 uint16_t l2_doorbell_bar_size_kb;
9936 * For backward compatibility this field must be set to 1.
9937 * Older drivers might look for this field to be 1 before
9938 * processing the message.
9942 * This GRC address location is used by the Host driver interfaces to poll
9943 * the adapter ready state to re-initiate the registration process again
9944 * after receiving the RESET Notify event.
9946 uint32_t reset_addr_poll;
9948 * This field specifies legacy L2 doorbell size in KBytes. Drivers should use
9949 * this value to find out the doorbell page offset from the BAR.
9951 uint16_t legacy_l2_db_size_kb;
9954 * This field specifies the source virtual interface of the function being
9955 * queried. Drivers can use this to program svif field in the L2 context
9958 #define HWRM_FUNC_QCFG_OUTPUT_SVIF_INFO_SVIF_MASK UINT32_C(0x7fff)
9959 #define HWRM_FUNC_QCFG_OUTPUT_SVIF_INFO_SVIF_SFT 0
9960 /* This field specifies whether svif is valid or not */
9961 #define HWRM_FUNC_QCFG_OUTPUT_SVIF_INFO_SVIF_VALID UINT32_C(0x8000)
9962 uint8_t unused_2[7];
9964 * This field is used in Output records to indicate that the output
9965 * is completely written to RAM. This field should be read as '1'
9966 * to indicate that the output has been completely written.
9967 * When writing a command completion or response to an internal processor,
9968 * the order of writes has to be such that this field is written last.
9978 /* hwrm_func_cfg_input (size:768b/96B) */
9979 struct hwrm_func_cfg_input {
9980 /* The HWRM command request type. */
9983 * The completion ring to send the completion event on. This should
9984 * be the NQ ID returned from the `nq_alloc` HWRM command.
9988 * The sequence ID is used by the driver for tracking multiple
9989 * commands. This ID is treated as opaque data by the firmware and
9990 * the value is returned in the `hwrm_resp_hdr` upon completion.
9994 * The target ID of the command:
9995 * * 0x0-0xFFF8 - The function ID
9996 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
9997 * * 0xFFFD - Reserved for user-space HWRM interface
10000 uint16_t target_id;
10002 * A physical address pointer pointing to a host buffer that the
10003 * command's response data will be written. This can be either a host
10004 * physical address (HPA) or a guest physical address (GPA) and must
10005 * point to a physically contiguous block of memory.
10007 uint64_t resp_addr;
10009 * Function ID of the function that is being
10011 * If set to 0xFF... (All Fs), then the the configuration is
10012 * for the requesting function.
10016 * This field specifies how many NQs will be reserved for the PF.
10017 * Remaining NQs that belong to the PF become available for VFs.
10018 * Once a PF has created VFs, it cannot change how many NQs are
10019 * reserved for itself (since the NQs must be contiguous in HW).
10024 * When this bit is '1', the function is disabled with
10025 * source MAC address check.
10026 * This is an anti-spoofing check. If this flag is set,
10027 * then the function shall be configured to disallow
10028 * transmission of frames with the source MAC address that
10029 * is configured for this function.
10031 #define HWRM_FUNC_CFG_INPUT_FLAGS_SRC_MAC_ADDR_CHECK_DISABLE \
10034 * When this bit is '1', the function is enabled with
10035 * source MAC address check.
10036 * This is an anti-spoofing check. If this flag is set,
10037 * then the function shall be configured to allow
10038 * transmission of frames with the source MAC address that
10039 * is configured for this function.
10041 #define HWRM_FUNC_CFG_INPUT_FLAGS_SRC_MAC_ADDR_CHECK_ENABLE \
10044 #define HWRM_FUNC_CFG_INPUT_FLAGS_RSVD_MASK \
10046 #define HWRM_FUNC_CFG_INPUT_FLAGS_RSVD_SFT 2
10048 * Standard TX Ring mode is used for the allocation of TX ring
10049 * and underlying scheduling resources that allow bandwidth
10050 * reservation and limit settings on the queried function.
10051 * If set to 1, then standard TX ring mode is requested to be
10052 * enabled on the function being configured.
10054 #define HWRM_FUNC_CFG_INPUT_FLAGS_STD_TX_RING_MODE_ENABLE \
10057 * Standard TX Ring mode is used for the allocation of TX ring
10058 * and underlying scheduling resources that allow bandwidth
10059 * reservation and limit settings on the queried function.
10060 * If set to 1, then the standard TX ring mode is requested to
10061 * be disabled on the function being configured. In this extended
10062 * TX ring resource mode, the minimum and maximum bandwidth settings
10063 * are not supported to allow the allocation of TX rings to
10064 * span multiple scheduler nodes.
10066 #define HWRM_FUNC_CFG_INPUT_FLAGS_STD_TX_RING_MODE_DISABLE \
10069 * If this bit is set, virtual mac address configured
10070 * in this command will be persistent over warm boot.
10072 #define HWRM_FUNC_CFG_INPUT_FLAGS_VIRT_MAC_PERSIST \
10075 * This bit only applies to the VF. If this bit is set, the statistic
10076 * context counters will not be cleared when the statistic context is freed
10077 * or a function reset is called on VF. This bit will be cleared when the PF
10078 * is unloaded or a function reset is called on the PF.
10080 #define HWRM_FUNC_CFG_INPUT_FLAGS_NO_AUTOCLEAR_STATISTIC \
10083 * This bit requests that the firmware test to see if all the assets
10084 * requested in this command (i.e. number of TX rings) are available.
10085 * The firmware will return an error if the requested assets are
10086 * not available. The firwmare will NOT reserve the assets if they
10089 #define HWRM_FUNC_CFG_INPUT_FLAGS_TX_ASSETS_TEST \
10092 * This bit requests that the firmware test to see if all the assets
10093 * requested in this command (i.e. number of RX rings) are available.
10094 * The firmware will return an error if the requested assets are
10095 * not available. The firwmare will NOT reserve the assets if they
10098 #define HWRM_FUNC_CFG_INPUT_FLAGS_RX_ASSETS_TEST \
10101 * This bit requests that the firmware test to see if all the assets
10102 * requested in this command (i.e. number of CMPL rings) are available.
10103 * The firmware will return an error if the requested assets are
10104 * not available. The firwmare will NOT reserve the assets if they
10107 #define HWRM_FUNC_CFG_INPUT_FLAGS_CMPL_ASSETS_TEST \
10110 * This bit requests that the firmware test to see if all the assets
10111 * requested in this command (i.e. number of RSS ctx) are available.
10112 * The firmware will return an error if the requested assets are
10113 * not available. The firwmare will NOT reserve the assets if they
10116 #define HWRM_FUNC_CFG_INPUT_FLAGS_RSSCOS_CTX_ASSETS_TEST \
10119 * This bit requests that the firmware test to see if all the assets
10120 * requested in this command (i.e. number of ring groups) are available.
10121 * The firmware will return an error if the requested assets are
10122 * not available. The firwmare will NOT reserve the assets if they
10125 #define HWRM_FUNC_CFG_INPUT_FLAGS_RING_GRP_ASSETS_TEST \
10128 * This bit requests that the firmware test to see if all the assets
10129 * requested in this command (i.e. number of stat ctx) are available.
10130 * The firmware will return an error if the requested assets are
10131 * not available. The firwmare will NOT reserve the assets if they
10134 #define HWRM_FUNC_CFG_INPUT_FLAGS_STAT_CTX_ASSETS_TEST \
10137 * This bit requests that the firmware test to see if all the assets
10138 * requested in this command (i.e. number of VNICs) are available.
10139 * The firmware will return an error if the requested assets are
10140 * not available. The firwmare will NOT reserve the assets if they
10143 #define HWRM_FUNC_CFG_INPUT_FLAGS_VNIC_ASSETS_TEST \
10146 * This bit requests that the firmware test to see if all the assets
10147 * requested in this command (i.e. number of L2 ctx) are available.
10148 * The firmware will return an error if the requested assets are
10149 * not available. The firwmare will NOT reserve the assets if they
10152 #define HWRM_FUNC_CFG_INPUT_FLAGS_L2_CTX_ASSETS_TEST \
10155 * This configuration change can be initiated by a PF driver. This
10156 * configuration request shall be targeted to a VF. From local host
10157 * resident HWRM clients, only the parent PF driver shall be allowed
10158 * to initiate this change on one of its children VFs. If this bit is
10159 * set to 1, then the VF that is being configured is requested to be
10162 #define HWRM_FUNC_CFG_INPUT_FLAGS_TRUSTED_VF_ENABLE \
10165 * When this bit it set, even if PF reserved pool size is zero,
10166 * FW will allow driver to create TX rings in ring alloc,
10167 * by reserving TX ring, S3 node dynamically.
10169 #define HWRM_FUNC_CFG_INPUT_FLAGS_DYNAMIC_TX_RING_ALLOC \
10172 * This bit requests that the firmware test to see if all the assets
10173 * requested in this command (i.e. number of NQ rings) are available.
10174 * The firmware will return an error if the requested assets are
10175 * not available. The firwmare will NOT reserve the assets if they
10178 #define HWRM_FUNC_CFG_INPUT_FLAGS_NQ_ASSETS_TEST \
10181 * This configuration change can be initiated by a PF driver. This
10182 * configuration request shall be targeted to a VF. From local host
10183 * resident HWRM clients, only the parent PF driver shall be allowed
10184 * to initiate this change on one of its children VFs. If this bit is
10185 * set to 1, then the VF that is being configured is requested to be
10188 #define HWRM_FUNC_CFG_INPUT_FLAGS_TRUSTED_VF_DISABLE \
10189 UINT32_C(0x1000000)
10191 * This bit is used by preboot drivers on a PF that require access
10192 * to the legacy L2 ring model and legacy 32b doorbells. This
10193 * feature is not allowed on VFs and is only relevant for devices
10194 * that require a context backing store.
10196 #define HWRM_FUNC_CFG_INPUT_FLAGS_PREBOOT_LEGACY_L2_RINGS \
10197 UINT32_C(0x2000000)
10199 * If this bit is set to 0, then the interface does not support hot
10200 * reset capability which it advertised with the hot_reset_support
10201 * flag in HWRM_FUNC_DRV_RGTR. If any of the function has set this
10202 * flag to 0, adapter cannot do the hot reset. In this state, if the
10203 * firmware receives a hot reset request, firmware must fail the
10204 * request. If this bit is set to 1, then interface is renabling the
10205 * hot reset capability.
10207 #define HWRM_FUNC_CFG_INPUT_FLAGS_HOT_RESET_IF_EN_DIS \
10208 UINT32_C(0x4000000)
10210 * If this bit is set to 1, the PF driver is requesting FW
10211 * to enable PPP TX PUSH feature on all the TX rings specified in
10212 * the num_tx_rings field. By default, the PPP TX push feature is
10213 * disabled for all the TX rings of the function. This flag is
10214 * ignored if num_tx_rings field is not specified or the function
10215 * doesn't support PPP tx push feature.
10217 #define HWRM_FUNC_CFG_INPUT_FLAGS_PPP_PUSH_MODE_ENABLE \
10218 UINT32_C(0x8000000)
10220 * If this bit is set to 1, the PF driver is requesting FW
10221 * to disable PPP TX PUSH feature on all the TX rings specified in
10222 * the num_tx_rings field. This flag is ignored if num_tx_rings
10223 * field is not specified or the function doesn't support PPP tx
10226 #define HWRM_FUNC_CFG_INPUT_FLAGS_PPP_PUSH_MODE_DISABLE \
10227 UINT32_C(0x10000000)
10230 * This bit must be '1' for the mtu field to be
10233 #define HWRM_FUNC_CFG_INPUT_ENABLES_MTU \
10236 * This bit must be '1' for the mru field to be
10239 #define HWRM_FUNC_CFG_INPUT_ENABLES_MRU \
10242 * This bit must be '1' for the num_rsscos_ctxs field to be
10245 #define HWRM_FUNC_CFG_INPUT_ENABLES_NUM_RSSCOS_CTXS \
10248 * This bit must be '1' for the num_cmpl_rings field to be
10251 #define HWRM_FUNC_CFG_INPUT_ENABLES_NUM_CMPL_RINGS \
10254 * This bit must be '1' for the num_tx_rings field to be
10257 #define HWRM_FUNC_CFG_INPUT_ENABLES_NUM_TX_RINGS \
10260 * This bit must be '1' for the num_rx_rings field to be
10263 #define HWRM_FUNC_CFG_INPUT_ENABLES_NUM_RX_RINGS \
10266 * This bit must be '1' for the num_l2_ctxs field to be
10269 #define HWRM_FUNC_CFG_INPUT_ENABLES_NUM_L2_CTXS \
10272 * This bit must be '1' for the num_vnics field to be
10275 #define HWRM_FUNC_CFG_INPUT_ENABLES_NUM_VNICS \
10278 * This bit must be '1' for the num_stat_ctxs field to be
10281 #define HWRM_FUNC_CFG_INPUT_ENABLES_NUM_STAT_CTXS \
10284 * This bit must be '1' for the dflt_mac_addr field to be
10287 #define HWRM_FUNC_CFG_INPUT_ENABLES_DFLT_MAC_ADDR \
10290 * This bit must be '1' for the dflt_vlan field to be
10293 #define HWRM_FUNC_CFG_INPUT_ENABLES_DFLT_VLAN \
10296 * This bit must be '1' for the dflt_ip_addr field to be
10299 #define HWRM_FUNC_CFG_INPUT_ENABLES_DFLT_IP_ADDR \
10302 * This bit must be '1' for the min_bw field to be
10305 #define HWRM_FUNC_CFG_INPUT_ENABLES_MIN_BW \
10308 * This bit must be '1' for the max_bw field to be
10311 #define HWRM_FUNC_CFG_INPUT_ENABLES_MAX_BW \
10314 * This bit must be '1' for the async_event_cr field to be
10317 #define HWRM_FUNC_CFG_INPUT_ENABLES_ASYNC_EVENT_CR \
10320 * This bit must be '1' for the vlan_antispoof_mode field to be
10323 #define HWRM_FUNC_CFG_INPUT_ENABLES_VLAN_ANTISPOOF_MODE \
10326 * This bit must be '1' for the allowed_vlan_pris field to be
10329 #define HWRM_FUNC_CFG_INPUT_ENABLES_ALLOWED_VLAN_PRIS \
10332 * This bit must be '1' for the evb_mode field to be
10335 #define HWRM_FUNC_CFG_INPUT_ENABLES_EVB_MODE \
10338 * This bit must be '1' for the num_mcast_filters field to be
10341 #define HWRM_FUNC_CFG_INPUT_ENABLES_NUM_MCAST_FILTERS \
10344 * This bit must be '1' for the num_hw_ring_grps field to be
10347 #define HWRM_FUNC_CFG_INPUT_ENABLES_NUM_HW_RING_GRPS \
10350 * This bit must be '1' for the cache_linesize field to be
10353 #define HWRM_FUNC_CFG_INPUT_ENABLES_CACHE_LINESIZE \
10356 * This bit must be '1' for the num_msix field to be
10359 #define HWRM_FUNC_CFG_INPUT_ENABLES_NUM_MSIX \
10362 * This bit must be '1' for the link admin state field to be
10365 #define HWRM_FUNC_CFG_INPUT_ENABLES_ADMIN_LINK_STATE \
10368 * This bit must be '1' for the hot_reset_if_en_dis field to be
10371 #define HWRM_FUNC_CFG_INPUT_ENABLES_HOT_RESET_IF_SUPPORT \
10374 * This bit must be '1' for the schq_id field to be
10377 #define HWRM_FUNC_CFG_INPUT_ENABLES_SCHQ_ID \
10378 UINT32_C(0x1000000)
10380 * The maximum transmission unit of the function.
10381 * The HWRM should make sure that the mtu of
10382 * the function does not exceed the mtu of the physical
10383 * port that this function is associated with.
10385 * In addition to configuring mtu per function, it is
10386 * possible to configure mtu per transmit ring.
10387 * By default, the mtu of each transmit ring associated
10388 * with a function is equal to the mtu of the function.
10389 * The HWRM should make sure that the mtu of each transmit
10390 * ring that is assigned to a function has a valid mtu.
10394 * The maximum receive unit of the function.
10395 * The HWRM should make sure that the mru of
10396 * the function does not exceed the mru of the physical
10397 * port that this function is associated with.
10399 * In addition to configuring mru per function, it is
10400 * possible to configure mru per vnic.
10401 * By default, the mru of each vnic associated
10402 * with a function is equal to the mru of the function.
10403 * The HWRM should make sure that the mru of each vnic
10404 * that is assigned to a function has a valid mru.
10408 * The number of RSS/COS contexts requested for the
10411 uint16_t num_rsscos_ctxs;
10413 * The number of completion rings requested for the
10414 * function. This does not include the rings allocated
10415 * to any children functions if any.
10417 uint16_t num_cmpl_rings;
10419 * The number of transmit rings requested for the function.
10420 * This does not include the rings allocated to any
10421 * children functions if any.
10423 uint16_t num_tx_rings;
10425 * The number of receive rings requested for the function.
10426 * This does not include the rings allocated
10427 * to any children functions if any.
10429 uint16_t num_rx_rings;
10430 /* The requested number of L2 contexts for the function. */
10431 uint16_t num_l2_ctxs;
10432 /* The requested number of vnics for the function. */
10433 uint16_t num_vnics;
10434 /* The requested number of statistic contexts for the function. */
10435 uint16_t num_stat_ctxs;
10437 * The number of HW ring groups that should
10438 * be reserved for this function.
10440 uint16_t num_hw_ring_grps;
10441 /* The default MAC address for the function being configured. */
10442 uint8_t dflt_mac_addr[6];
10444 * The default VLAN for the function being configured.
10445 * This field's format is same as 802.1Q Tag's
10446 * Tag Control Information (TCI) format that includes both
10447 * Priority Code Point (PCP) and VLAN Identifier (VID).
10449 uint16_t dflt_vlan;
10451 * The default IP address for the function being configured.
10452 * This address is only used in enabling source property check.
10454 uint32_t dflt_ip_addr[4];
10456 * Minimum BW allocated for this function.
10457 * The HWRM will translate this value into byte counter and
10458 * time interval used for the scheduler inside the device.
10461 /* The bandwidth value. */
10462 #define HWRM_FUNC_CFG_INPUT_MIN_BW_BW_VALUE_MASK \
10463 UINT32_C(0xfffffff)
10464 #define HWRM_FUNC_CFG_INPUT_MIN_BW_BW_VALUE_SFT 0
10465 /* The granularity of the value (bits or bytes). */
10466 #define HWRM_FUNC_CFG_INPUT_MIN_BW_SCALE \
10467 UINT32_C(0x10000000)
10468 /* Value is in bits. */
10469 #define HWRM_FUNC_CFG_INPUT_MIN_BW_SCALE_BITS \
10470 (UINT32_C(0x0) << 28)
10471 /* Value is in bytes. */
10472 #define HWRM_FUNC_CFG_INPUT_MIN_BW_SCALE_BYTES \
10473 (UINT32_C(0x1) << 28)
10474 #define HWRM_FUNC_CFG_INPUT_MIN_BW_SCALE_LAST \
10475 HWRM_FUNC_CFG_INPUT_MIN_BW_SCALE_BYTES
10476 /* bw_value_unit is 3 b */
10477 #define HWRM_FUNC_CFG_INPUT_MIN_BW_BW_VALUE_UNIT_MASK \
10478 UINT32_C(0xe0000000)
10479 #define HWRM_FUNC_CFG_INPUT_MIN_BW_BW_VALUE_UNIT_SFT 29
10480 /* Value is in Mb or MB (base 10). */
10481 #define HWRM_FUNC_CFG_INPUT_MIN_BW_BW_VALUE_UNIT_MEGA \
10482 (UINT32_C(0x0) << 29)
10483 /* Value is in Kb or KB (base 10). */
10484 #define HWRM_FUNC_CFG_INPUT_MIN_BW_BW_VALUE_UNIT_KILO \
10485 (UINT32_C(0x2) << 29)
10486 /* Value is in bits or bytes. */
10487 #define HWRM_FUNC_CFG_INPUT_MIN_BW_BW_VALUE_UNIT_BASE \
10488 (UINT32_C(0x4) << 29)
10489 /* Value is in Gb or GB (base 10). */
10490 #define HWRM_FUNC_CFG_INPUT_MIN_BW_BW_VALUE_UNIT_GIGA \
10491 (UINT32_C(0x6) << 29)
10492 /* Value is in 1/100th of a percentage of total bandwidth. */
10493 #define HWRM_FUNC_CFG_INPUT_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 \
10494 (UINT32_C(0x1) << 29)
10496 #define HWRM_FUNC_CFG_INPUT_MIN_BW_BW_VALUE_UNIT_INVALID \
10497 (UINT32_C(0x7) << 29)
10498 #define HWRM_FUNC_CFG_INPUT_MIN_BW_BW_VALUE_UNIT_LAST \
10499 HWRM_FUNC_CFG_INPUT_MIN_BW_BW_VALUE_UNIT_INVALID
10501 * Maximum BW allocated for this function.
10502 * The HWRM will translate this value into byte counter and
10503 * time interval used for the scheduler inside the device.
10506 /* The bandwidth value. */
10507 #define HWRM_FUNC_CFG_INPUT_MAX_BW_BW_VALUE_MASK \
10508 UINT32_C(0xfffffff)
10509 #define HWRM_FUNC_CFG_INPUT_MAX_BW_BW_VALUE_SFT 0
10510 /* The granularity of the value (bits or bytes). */
10511 #define HWRM_FUNC_CFG_INPUT_MAX_BW_SCALE \
10512 UINT32_C(0x10000000)
10513 /* Value is in bits. */
10514 #define HWRM_FUNC_CFG_INPUT_MAX_BW_SCALE_BITS \
10515 (UINT32_C(0x0) << 28)
10516 /* Value is in bytes. */
10517 #define HWRM_FUNC_CFG_INPUT_MAX_BW_SCALE_BYTES \
10518 (UINT32_C(0x1) << 28)
10519 #define HWRM_FUNC_CFG_INPUT_MAX_BW_SCALE_LAST \
10520 HWRM_FUNC_CFG_INPUT_MAX_BW_SCALE_BYTES
10521 /* bw_value_unit is 3 b */
10522 #define HWRM_FUNC_CFG_INPUT_MAX_BW_BW_VALUE_UNIT_MASK \
10523 UINT32_C(0xe0000000)
10524 #define HWRM_FUNC_CFG_INPUT_MAX_BW_BW_VALUE_UNIT_SFT 29
10525 /* Value is in Mb or MB (base 10). */
10526 #define HWRM_FUNC_CFG_INPUT_MAX_BW_BW_VALUE_UNIT_MEGA \
10527 (UINT32_C(0x0) << 29)
10528 /* Value is in Kb or KB (base 10). */
10529 #define HWRM_FUNC_CFG_INPUT_MAX_BW_BW_VALUE_UNIT_KILO \
10530 (UINT32_C(0x2) << 29)
10531 /* Value is in bits or bytes. */
10532 #define HWRM_FUNC_CFG_INPUT_MAX_BW_BW_VALUE_UNIT_BASE \
10533 (UINT32_C(0x4) << 29)
10534 /* Value is in Gb or GB (base 10). */
10535 #define HWRM_FUNC_CFG_INPUT_MAX_BW_BW_VALUE_UNIT_GIGA \
10536 (UINT32_C(0x6) << 29)
10537 /* Value is in 1/100th of a percentage of total bandwidth. */
10538 #define HWRM_FUNC_CFG_INPUT_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 \
10539 (UINT32_C(0x1) << 29)
10541 #define HWRM_FUNC_CFG_INPUT_MAX_BW_BW_VALUE_UNIT_INVALID \
10542 (UINT32_C(0x7) << 29)
10543 #define HWRM_FUNC_CFG_INPUT_MAX_BW_BW_VALUE_UNIT_LAST \
10544 HWRM_FUNC_CFG_INPUT_MAX_BW_BW_VALUE_UNIT_INVALID
10546 * ID of the target completion ring for receiving asynchronous
10547 * event completions. If this field is not valid, then the
10548 * HWRM shall use the default completion ring of the function
10549 * that is being configured as the target completion ring for
10550 * providing any asynchronous event completions for that
10552 * If this field is valid, then the HWRM shall use the
10553 * completion ring identified by this ID as the target
10554 * completion ring for providing any asynchronous event
10555 * completions for the function that is being configured.
10557 uint16_t async_event_cr;
10558 /* VLAN Anti-spoofing mode. */
10559 uint8_t vlan_antispoof_mode;
10560 /* No VLAN anti-spoofing checks are enabled */
10561 #define HWRM_FUNC_CFG_INPUT_VLAN_ANTISPOOF_MODE_NOCHECK \
10563 /* Validate VLAN against the configured VLAN(s) */
10564 #define HWRM_FUNC_CFG_INPUT_VLAN_ANTISPOOF_MODE_VALIDATE_VLAN \
10566 /* Insert VLAN if it does not exist, otherwise discard */
10567 #define HWRM_FUNC_CFG_INPUT_VLAN_ANTISPOOF_MODE_INSERT_IF_VLANDNE \
10569 /* Insert VLAN if it does not exist, override VLAN if it exists */
10570 #define HWRM_FUNC_CFG_INPUT_VLAN_ANTISPOOF_MODE_INSERT_OR_OVERRIDE_VLAN \
10572 #define HWRM_FUNC_CFG_INPUT_VLAN_ANTISPOOF_MODE_LAST \
10573 HWRM_FUNC_CFG_INPUT_VLAN_ANTISPOOF_MODE_INSERT_OR_OVERRIDE_VLAN
10575 * This bit field defines VLAN PRIs that are allowed on
10577 * If nth bit is set, then VLAN PRI n is allowed on this
10580 uint8_t allowed_vlan_pris;
10582 * The HWRM shall allow a PF driver to change EVB mode for the
10583 * partition it belongs to.
10584 * The HWRM shall not allow a VF driver to change the EVB mode.
10585 * The HWRM shall take into account the switching of EVB mode
10586 * from one to another and reconfigure hardware resources as
10588 * The switching from VEB to VEPA mode requires
10589 * the disabling of the loopback traffic. Additionally,
10590 * source knock outs are handled differently in VEB and VEPA
10594 /* No Edge Virtual Bridging (EVB) */
10595 #define HWRM_FUNC_CFG_INPUT_EVB_MODE_NO_EVB UINT32_C(0x0)
10596 /* Virtual Ethernet Bridge (VEB) */
10597 #define HWRM_FUNC_CFG_INPUT_EVB_MODE_VEB UINT32_C(0x1)
10598 /* Virtual Ethernet Port Aggregator (VEPA) */
10599 #define HWRM_FUNC_CFG_INPUT_EVB_MODE_VEPA UINT32_C(0x2)
10600 #define HWRM_FUNC_CFG_INPUT_EVB_MODE_LAST \
10601 HWRM_FUNC_CFG_INPUT_EVB_MODE_VEPA
10604 * This value indicates the PCIE device cache line size.
10605 * The cache line size allows the DMA writes to terminate and
10606 * start at the cache boundary.
10608 #define HWRM_FUNC_CFG_INPUT_OPTIONS_CACHE_LINESIZE_MASK \
10610 #define HWRM_FUNC_CFG_INPUT_OPTIONS_CACHE_LINESIZE_SFT 0
10611 /* Cache Line Size 64 bytes */
10612 #define HWRM_FUNC_CFG_INPUT_OPTIONS_CACHE_LINESIZE_SIZE_64 \
10614 /* Cache Line Size 128 bytes */
10615 #define HWRM_FUNC_CFG_INPUT_OPTIONS_CACHE_LINESIZE_SIZE_128 \
10617 #define HWRM_FUNC_CFG_INPUT_OPTIONS_CACHE_LINESIZE_LAST \
10618 HWRM_FUNC_CFG_INPUT_OPTIONS_CACHE_LINESIZE_SIZE_128
10619 /* This value is the virtual link admin state setting. */
10620 #define HWRM_FUNC_CFG_INPUT_OPTIONS_LINK_ADMIN_STATE_MASK \
10622 #define HWRM_FUNC_CFG_INPUT_OPTIONS_LINK_ADMIN_STATE_SFT 2
10623 /* Admin state is forced down. */
10624 #define HWRM_FUNC_CFG_INPUT_OPTIONS_LINK_ADMIN_STATE_FORCED_DOWN \
10625 (UINT32_C(0x0) << 2)
10626 /* Admin state is forced up. */
10627 #define HWRM_FUNC_CFG_INPUT_OPTIONS_LINK_ADMIN_STATE_FORCED_UP \
10628 (UINT32_C(0x1) << 2)
10629 /* Admin state is in auto mode - is to follow the physical link state. */
10630 #define HWRM_FUNC_CFG_INPUT_OPTIONS_LINK_ADMIN_STATE_AUTO \
10631 (UINT32_C(0x2) << 2)
10632 #define HWRM_FUNC_CFG_INPUT_OPTIONS_LINK_ADMIN_STATE_LAST \
10633 HWRM_FUNC_CFG_INPUT_OPTIONS_LINK_ADMIN_STATE_AUTO
10634 /* Reserved for future. */
10635 #define HWRM_FUNC_CFG_INPUT_OPTIONS_RSVD_MASK \
10637 #define HWRM_FUNC_CFG_INPUT_OPTIONS_RSVD_SFT 4
10639 * The number of multicast filters that should
10640 * be reserved for this function on the RX side.
10642 uint16_t num_mcast_filters;
10643 /* Used by a PF driver to associate a SCHQ with a VF. */
10645 uint8_t unused_0[6];
10648 /* hwrm_func_cfg_output (size:128b/16B) */
10649 struct hwrm_func_cfg_output {
10650 /* The specific error status for the command. */
10651 uint16_t error_code;
10652 /* The HWRM command request type. */
10654 /* The sequence ID from the original command. */
10656 /* The length of the response data in number of bytes. */
10658 uint8_t unused_0[7];
10660 * This field is used in Output records to indicate that the output
10661 * is completely written to RAM. This field should be read as '1'
10662 * to indicate that the output has been completely written.
10663 * When writing a command completion or response to an internal processor,
10664 * the order of writes has to be such that this field is written last.
10669 /********************
10670 * hwrm_func_qstats *
10671 ********************/
10674 /* hwrm_func_qstats_input (size:192b/24B) */
10675 struct hwrm_func_qstats_input {
10676 /* The HWRM command request type. */
10679 * The completion ring to send the completion event on. This should
10680 * be the NQ ID returned from the `nq_alloc` HWRM command.
10682 uint16_t cmpl_ring;
10684 * The sequence ID is used by the driver for tracking multiple
10685 * commands. This ID is treated as opaque data by the firmware and
10686 * the value is returned in the `hwrm_resp_hdr` upon completion.
10690 * The target ID of the command:
10691 * * 0x0-0xFFF8 - The function ID
10692 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
10693 * * 0xFFFD - Reserved for user-space HWRM interface
10696 uint16_t target_id;
10698 * A physical address pointer pointing to a host buffer that the
10699 * command's response data will be written. This can be either a host
10700 * physical address (HPA) or a guest physical address (GPA) and must
10701 * point to a physically contiguous block of memory.
10703 uint64_t resp_addr;
10705 * Function ID of the function that is being queried.
10706 * 0xFF... (All Fs) if the query is for the requesting
10708 * A privileged PF can query for other function's statistics.
10711 /* This flags indicates the type of statistics request. */
10713 /* This value is not used to avoid backward compatibility issues. */
10714 #define HWRM_FUNC_QSTATS_INPUT_FLAGS_UNUSED UINT32_C(0x0)
10716 * flags should be set to 1 when request is for only RoCE statistics.
10717 * This will be honored only if the caller_fid is a privileged PF.
10718 * In all other cases FID and caller_fid should be the same.
10720 #define HWRM_FUNC_QSTATS_INPUT_FLAGS_ROCE_ONLY UINT32_C(0x1)
10722 * flags should be set to 2 when request is for the counter mask,
10723 * representing the width of each of the stats counters, rather
10724 * than counters themselves.
10726 #define HWRM_FUNC_QSTATS_INPUT_FLAGS_COUNTER_MASK UINT32_C(0x2)
10727 #define HWRM_FUNC_QSTATS_INPUT_FLAGS_LAST \
10728 HWRM_FUNC_QSTATS_INPUT_FLAGS_COUNTER_MASK
10729 uint8_t unused_0[5];
10732 /* hwrm_func_qstats_output (size:1408b/176B) */
10733 struct hwrm_func_qstats_output {
10734 /* The specific error status for the command. */
10735 uint16_t error_code;
10736 /* The HWRM command request type. */
10738 /* The sequence ID from the original command. */
10740 /* The length of the response data in number of bytes. */
10742 /* Number of transmitted unicast packets on the function. */
10743 uint64_t tx_ucast_pkts;
10744 /* Number of transmitted multicast packets on the function. */
10745 uint64_t tx_mcast_pkts;
10746 /* Number of transmitted broadcast packets on the function. */
10747 uint64_t tx_bcast_pkts;
10749 * Number of transmitted packets that were discarded due to
10750 * internal NIC resource problems. For transmit, this
10751 * can only happen if TMP is configured to allow dropping
10752 * in HOL blocking conditions, which is not a normal
10755 uint64_t tx_discard_pkts;
10757 * Number of dropped packets on transmit path on the function.
10758 * These are packets that have been marked for drop by
10759 * the TE CFA block or are packets that exceeded the
10760 * transmit MTU limit for the function.
10762 uint64_t tx_drop_pkts;
10763 /* Number of transmitted bytes for unicast traffic on the function. */
10764 uint64_t tx_ucast_bytes;
10765 /* Number of transmitted bytes for multicast traffic on the function. */
10766 uint64_t tx_mcast_bytes;
10767 /* Number of transmitted bytes for broadcast traffic on the function. */
10768 uint64_t tx_bcast_bytes;
10769 /* Number of received unicast packets on the function. */
10770 uint64_t rx_ucast_pkts;
10771 /* Number of received multicast packets on the function. */
10772 uint64_t rx_mcast_pkts;
10773 /* Number of received broadcast packets on the function. */
10774 uint64_t rx_bcast_pkts;
10776 * Number of received packets that were discarded on the function
10777 * due to resource limitations. This can happen for 3 reasons.
10778 * # The BD used for the packet has a bad format.
10779 * # There were no BDs available in the ring for the packet.
10780 * # There were no BDs available on-chip for the packet.
10782 uint64_t rx_discard_pkts;
10784 * Number of dropped packets on received path on the function.
10785 * These are packets that have been marked for drop by the
10788 uint64_t rx_drop_pkts;
10789 /* Number of received bytes for unicast traffic on the function. */
10790 uint64_t rx_ucast_bytes;
10791 /* Number of received bytes for multicast traffic on the function. */
10792 uint64_t rx_mcast_bytes;
10793 /* Number of received bytes for broadcast traffic on the function. */
10794 uint64_t rx_bcast_bytes;
10795 /* Number of aggregated unicast packets on the function. */
10796 uint64_t rx_agg_pkts;
10797 /* Number of aggregated unicast bytes on the function. */
10798 uint64_t rx_agg_bytes;
10799 /* Number of aggregation events on the function. */
10800 uint64_t rx_agg_events;
10801 /* Number of aborted aggregations on the function. */
10802 uint64_t rx_agg_aborts;
10803 uint8_t unused_0[7];
10805 * This field is used in Output records to indicate that the output
10806 * is completely written to RAM. This field should be read as '1'
10807 * to indicate that the output has been completely written.
10808 * When writing a command completion or response to an internal processor,
10809 * the order of writes has to be such that this field is written last.
10814 /************************
10815 * hwrm_func_qstats_ext *
10816 ************************/
10819 /* hwrm_func_qstats_ext_input (size:256b/32B) */
10820 struct hwrm_func_qstats_ext_input {
10821 /* The HWRM command request type. */
10824 * The completion ring to send the completion event on. This should
10825 * be the NQ ID returned from the `nq_alloc` HWRM command.
10827 uint16_t cmpl_ring;
10829 * The sequence ID is used by the driver for tracking multiple
10830 * commands. This ID is treated as opaque data by the firmware and
10831 * the value is returned in the `hwrm_resp_hdr` upon completion.
10835 * The target ID of the command:
10836 * * 0x0-0xFFF8 - The function ID
10837 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
10838 * * 0xFFFD - Reserved for user-space HWRM interface
10841 uint16_t target_id;
10843 * A physical address pointer pointing to a host buffer that the
10844 * command's response data will be written. This can be either a host
10845 * physical address (HPA) or a guest physical address (GPA) and must
10846 * point to a physically contiguous block of memory.
10848 uint64_t resp_addr;
10850 * Function ID of the function that is being queried.
10851 * 0xFF... (All Fs) if the query is for the requesting
10853 * A privileged PF can query for other function's statistics.
10856 /* This flags indicates the type of statistics request. */
10858 /* This value is not used to avoid backward compatibility issues. */
10859 #define HWRM_FUNC_QSTATS_EXT_INPUT_FLAGS_UNUSED UINT32_C(0x0)
10861 * flags should be set to 1 when request is for only RoCE statistics.
10862 * This will be honored only if the caller_fid is a privileged PF.
10863 * In all other cases FID and caller_fid should be the same.
10865 #define HWRM_FUNC_QSTATS_EXT_INPUT_FLAGS_ROCE_ONLY UINT32_C(0x1)
10867 * flags should be set to 2 when request is for the counter mask
10868 * representing the width of each of the stats counters, rather
10869 * than counters themselves.
10871 #define HWRM_FUNC_QSTATS_EXT_INPUT_FLAGS_COUNTER_MASK UINT32_C(0x2)
10872 #define HWRM_FUNC_QSTATS_EXT_INPUT_FLAGS_LAST \
10873 HWRM_FUNC_QSTATS_EXT_INPUT_FLAGS_COUNTER_MASK
10874 uint8_t unused_0[1];
10877 * This bit must be '1' for the schq_id and traffic_class fields to
10880 #define HWRM_FUNC_QSTATS_EXT_INPUT_ENABLES_SCHQ_ID UINT32_C(0x1)
10881 /* Specifies the SCHQ for which to gather statistics */
10884 * Specifies the traffic class for which to gather statistics. Valid
10885 * values are 0 through (max_configurable_queues - 1), where
10886 * max_configurable_queues is in the response of HWRM_QUEUE_QPORTCFG
10888 uint16_t traffic_class;
10889 uint8_t unused_1[4];
10892 /* hwrm_func_qstats_ext_output (size:1472b/184B) */
10893 struct hwrm_func_qstats_ext_output {
10894 /* The specific error status for the command. */
10895 uint16_t error_code;
10896 /* The HWRM command request type. */
10898 /* The sequence ID from the original command. */
10900 /* The length of the response data in number of bytes. */
10902 /* Number of received unicast packets */
10903 uint64_t rx_ucast_pkts;
10904 /* Number of received multicast packets */
10905 uint64_t rx_mcast_pkts;
10906 /* Number of received broadcast packets */
10907 uint64_t rx_bcast_pkts;
10908 /* Number of discarded packets on received path */
10909 uint64_t rx_discard_pkts;
10910 /* Number of packets on receive path with error */
10911 uint64_t rx_error_pkts;
10912 /* Number of received bytes for unicast traffic */
10913 uint64_t rx_ucast_bytes;
10914 /* Number of received bytes for multicast traffic */
10915 uint64_t rx_mcast_bytes;
10916 /* Number of received bytes for broadcast traffic */
10917 uint64_t rx_bcast_bytes;
10918 /* Number of transmitted unicast packets */
10919 uint64_t tx_ucast_pkts;
10920 /* Number of transmitted multicast packets */
10921 uint64_t tx_mcast_pkts;
10922 /* Number of transmitted broadcast packets */
10923 uint64_t tx_bcast_pkts;
10924 /* Number of packets on transmit path with error */
10925 uint64_t tx_error_pkts;
10926 /* Number of discarded packets on transmit path */
10927 uint64_t tx_discard_pkts;
10928 /* Number of transmitted bytes for unicast traffic */
10929 uint64_t tx_ucast_bytes;
10930 /* Number of transmitted bytes for multicast traffic */
10931 uint64_t tx_mcast_bytes;
10932 /* Number of transmitted bytes for broadcast traffic */
10933 uint64_t tx_bcast_bytes;
10934 /* Number of TPA eligible packets */
10935 uint64_t rx_tpa_eligible_pkt;
10936 /* Number of TPA eligible bytes */
10937 uint64_t rx_tpa_eligible_bytes;
10938 /* Number of TPA packets */
10939 uint64_t rx_tpa_pkt;
10940 /* Number of TPA bytes */
10941 uint64_t rx_tpa_bytes;
10942 /* Number of TPA errors */
10943 uint64_t rx_tpa_errors;
10944 uint8_t unused_0[7];
10946 * This field is used in Output records to indicate that the output
10947 * is completely written to RAM. This field should be read as '1'
10948 * to indicate that the output has been completely written.
10949 * When writing a command completion or response to an internal processor,
10950 * the order of writes has to be such that this field is written last.
10955 /***********************
10956 * hwrm_func_clr_stats *
10957 ***********************/
10960 /* hwrm_func_clr_stats_input (size:192b/24B) */
10961 struct hwrm_func_clr_stats_input {
10962 /* The HWRM command request type. */
10965 * The completion ring to send the completion event on. This should
10966 * be the NQ ID returned from the `nq_alloc` HWRM command.
10968 uint16_t cmpl_ring;
10970 * The sequence ID is used by the driver for tracking multiple
10971 * commands. This ID is treated as opaque data by the firmware and
10972 * the value is returned in the `hwrm_resp_hdr` upon completion.
10976 * The target ID of the command:
10977 * * 0x0-0xFFF8 - The function ID
10978 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
10979 * * 0xFFFD - Reserved for user-space HWRM interface
10982 uint16_t target_id;
10984 * A physical address pointer pointing to a host buffer that the
10985 * command's response data will be written. This can be either a host
10986 * physical address (HPA) or a guest physical address (GPA) and must
10987 * point to a physically contiguous block of memory.
10989 uint64_t resp_addr;
10991 * Function ID of the function.
10992 * 0xFF... (All Fs) if the query is for the requesting
10996 uint8_t unused_0[6];
10999 /* hwrm_func_clr_stats_output (size:128b/16B) */
11000 struct hwrm_func_clr_stats_output {
11001 /* The specific error status for the command. */
11002 uint16_t error_code;
11003 /* The HWRM command request type. */
11005 /* The sequence ID from the original command. */
11007 /* The length of the response data in number of bytes. */
11009 uint8_t unused_0[7];
11011 * This field is used in Output records to indicate that the output
11012 * is completely written to RAM. This field should be read as '1'
11013 * to indicate that the output has been completely written.
11014 * When writing a command completion or response to an internal processor,
11015 * the order of writes has to be such that this field is written last.
11020 /**************************
11021 * hwrm_func_vf_resc_free *
11022 **************************/
11025 /* hwrm_func_vf_resc_free_input (size:192b/24B) */
11026 struct hwrm_func_vf_resc_free_input {
11027 /* The HWRM command request type. */
11030 * The completion ring to send the completion event on. This should
11031 * be the NQ ID returned from the `nq_alloc` HWRM command.
11033 uint16_t cmpl_ring;
11035 * The sequence ID is used by the driver for tracking multiple
11036 * commands. This ID is treated as opaque data by the firmware and
11037 * the value is returned in the `hwrm_resp_hdr` upon completion.
11041 * The target ID of the command:
11042 * * 0x0-0xFFF8 - The function ID
11043 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
11044 * * 0xFFFD - Reserved for user-space HWRM interface
11047 uint16_t target_id;
11049 * A physical address pointer pointing to a host buffer that the
11050 * command's response data will be written. This can be either a host
11051 * physical address (HPA) or a guest physical address (GPA) and must
11052 * point to a physically contiguous block of memory.
11054 uint64_t resp_addr;
11056 * This value is used to identify a Virtual Function (VF).
11057 * The scope of VF ID is local within a PF.
11060 uint8_t unused_0[6];
11063 /* hwrm_func_vf_resc_free_output (size:128b/16B) */
11064 struct hwrm_func_vf_resc_free_output {
11065 /* The specific error status for the command. */
11066 uint16_t error_code;
11067 /* The HWRM command request type. */
11069 /* The sequence ID from the original command. */
11071 /* The length of the response data in number of bytes. */
11073 uint8_t unused_0[7];
11075 * This field is used in Output records to indicate that the output
11076 * is completely written to RAM. This field should be read as '1'
11077 * to indicate that the output has been completely written.
11078 * When writing a command completion or response to an internal processor,
11079 * the order of writes has to be such that this field is written last.
11084 /**********************
11085 * hwrm_func_drv_rgtr *
11086 **********************/
11089 /* hwrm_func_drv_rgtr_input (size:896b/112B) */
11090 struct hwrm_func_drv_rgtr_input {
11091 /* The HWRM command request type. */
11094 * The completion ring to send the completion event on. This should
11095 * be the NQ ID returned from the `nq_alloc` HWRM command.
11097 uint16_t cmpl_ring;
11099 * The sequence ID is used by the driver for tracking multiple
11100 * commands. This ID is treated as opaque data by the firmware and
11101 * the value is returned in the `hwrm_resp_hdr` upon completion.
11105 * The target ID of the command:
11106 * * 0x0-0xFFF8 - The function ID
11107 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
11108 * * 0xFFFD - Reserved for user-space HWRM interface
11111 uint16_t target_id;
11113 * A physical address pointer pointing to a host buffer that the
11114 * command's response data will be written. This can be either a host
11115 * physical address (HPA) or a guest physical address (GPA) and must
11116 * point to a physically contiguous block of memory.
11118 uint64_t resp_addr;
11121 * When this bit is '1', the function driver is requesting
11122 * all requests from its children VF drivers to be
11123 * forwarded to itself.
11124 * This flag can only be set by the PF driver.
11125 * If a VF driver sets this flag, it should be ignored
11128 #define HWRM_FUNC_DRV_RGTR_INPUT_FLAGS_FWD_ALL_MODE \
11131 * When this bit is '1', the function is requesting none of
11132 * the requests from its children VF drivers to be
11133 * forwarded to itself.
11134 * This flag can only be set by the PF driver.
11135 * If a VF driver sets this flag, it should be ignored
11138 #define HWRM_FUNC_DRV_RGTR_INPUT_FLAGS_FWD_NONE_MODE \
11141 * When this bit is '1', then ver_maj_8b, ver_min_8b, ver_upd_8b
11142 * fields shall be ignored and ver_maj, ver_min, ver_upd
11143 * and ver_patch shall be used for the driver version information.
11144 * When this bit is '0', then ver_maj_8b, ver_min_8b, ver_upd_8b
11145 * fields shall be used for the driver version information and
11146 * ver_maj, ver_min, ver_upd and ver_patch shall be ignored.
11148 #define HWRM_FUNC_DRV_RGTR_INPUT_FLAGS_16BIT_VER_MODE \
11151 * When this bit is '1', the function is indicating support of
11152 * 64bit flow handle. The firmware that only supports 64bit flow
11153 * handle should check this bit before allowing processing of
11154 * HWRM_CFA_FLOW_XXX commands from the requesting function as firmware
11155 * with 64bit flow handle support can only be compatible with drivers
11156 * that support 64bit flow handle. The legacy drivers that don't support
11157 * 64bit flow handle won't be able to use HWRM_CFA_FLOW_XXX commands when
11158 * running with new firmware that only supports 64bit flow handle. The new
11159 * firmware support 64bit flow handle returns HWRM_ERR_CODE_CMD_NOT_SUPPORTED
11160 * status to the legacy driver when encounters these commands.
11162 #define HWRM_FUNC_DRV_RGTR_INPUT_FLAGS_FLOW_HANDLE_64BIT_MODE \
11165 * When this bit is '1', the function is indicating support of
11166 * Hot Reset. The driver interface will destroy the resources,
11167 * unregister the function and register again up on receiving
11168 * the RESET_NOTIFY Async notification from the core firmware.
11169 * The core firmware will this use flag and trigger the Hot Reset
11170 * process only if all the registered driver instances are capable
11173 #define HWRM_FUNC_DRV_RGTR_INPUT_FLAGS_HOT_RESET_SUPPORT \
11176 * When this bit is 1, the function is indicating the support of the
11177 * error recovery capability. Error recovery support will be used by
11178 * firmware only if all the driver instances support error recovery
11179 * process. By setting this bit, driver is indicating support for
11180 * corresponding async event completion message. These will be
11181 * delivered to the driver even if they did not register for it.
11182 * If supported, after receiving reset notify async event with fatal
11183 * flag set in event data1, then all the drivers have to tear down
11184 * their resources without sending any HWRM commands to FW.
11186 #define HWRM_FUNC_DRV_RGTR_INPUT_FLAGS_ERROR_RECOVERY_SUPPORT \
11189 * When this bit is 1, the function is indicating the support of the
11190 * Master capability. The Firmware will use this capability to select the
11191 * Master function. The master function will be used to initiate
11192 * designated functionality like error recovery etc… If none of the
11193 * registered PF’s or trusted VF’s indicate this support, then
11194 * firmware will select the 1st registered PF as Master capable instance.
11196 #define HWRM_FUNC_DRV_RGTR_INPUT_FLAGS_MASTER_SUPPORT \
11200 * This bit must be '1' for the os_type field to be
11203 #define HWRM_FUNC_DRV_RGTR_INPUT_ENABLES_OS_TYPE \
11206 * This bit must be '1' for the ver field to be
11209 #define HWRM_FUNC_DRV_RGTR_INPUT_ENABLES_VER \
11212 * This bit must be '1' for the timestamp field to be
11215 #define HWRM_FUNC_DRV_RGTR_INPUT_ENABLES_TIMESTAMP \
11218 * This bit must be '1' for the vf_req_fwd field to be
11221 #define HWRM_FUNC_DRV_RGTR_INPUT_ENABLES_VF_REQ_FWD \
11224 * This bit must be '1' for the async_event_fwd field to be
11227 #define HWRM_FUNC_DRV_RGTR_INPUT_ENABLES_ASYNC_EVENT_FWD \
11229 /* This value indicates the type of OS. The values are based on CIM_OperatingSystem.mof file as published by the DMTF. */
11232 #define HWRM_FUNC_DRV_RGTR_INPUT_OS_TYPE_UNKNOWN UINT32_C(0x0)
11233 /* Other OS not listed below. */
11234 #define HWRM_FUNC_DRV_RGTR_INPUT_OS_TYPE_OTHER UINT32_C(0x1)
11236 #define HWRM_FUNC_DRV_RGTR_INPUT_OS_TYPE_MSDOS UINT32_C(0xe)
11238 #define HWRM_FUNC_DRV_RGTR_INPUT_OS_TYPE_WINDOWS UINT32_C(0x12)
11240 #define HWRM_FUNC_DRV_RGTR_INPUT_OS_TYPE_SOLARIS UINT32_C(0x1d)
11242 #define HWRM_FUNC_DRV_RGTR_INPUT_OS_TYPE_LINUX UINT32_C(0x24)
11244 #define HWRM_FUNC_DRV_RGTR_INPUT_OS_TYPE_FREEBSD UINT32_C(0x2a)
11245 /* VMware ESXi OS. */
11246 #define HWRM_FUNC_DRV_RGTR_INPUT_OS_TYPE_ESXI UINT32_C(0x68)
11247 /* Microsoft Windows 8 64-bit OS. */
11248 #define HWRM_FUNC_DRV_RGTR_INPUT_OS_TYPE_WIN864 UINT32_C(0x73)
11249 /* Microsoft Windows Server 2012 R2 OS. */
11250 #define HWRM_FUNC_DRV_RGTR_INPUT_OS_TYPE_WIN2012R2 UINT32_C(0x74)
11252 #define HWRM_FUNC_DRV_RGTR_INPUT_OS_TYPE_UEFI UINT32_C(0x8000)
11253 #define HWRM_FUNC_DRV_RGTR_INPUT_OS_TYPE_LAST \
11254 HWRM_FUNC_DRV_RGTR_INPUT_OS_TYPE_UEFI
11255 /* This is the 8bit major version of the driver. */
11256 uint8_t ver_maj_8b;
11257 /* This is the 8bit minor version of the driver. */
11258 uint8_t ver_min_8b;
11259 /* This is the 8bit update version of the driver. */
11260 uint8_t ver_upd_8b;
11261 uint8_t unused_0[3];
11263 * This is a 32-bit timestamp provided by the driver for
11265 * The timestamp is in multiples of 1ms.
11267 uint32_t timestamp;
11268 uint8_t unused_1[4];
11270 * This is a 256-bit bit mask provided by the PF driver for
11271 * letting the HWRM know what commands issued by the VF driver
11272 * to the HWRM should be forwarded to the PF driver.
11273 * Nth bit refers to the Nth req_type.
11275 * Setting Nth bit to 1 indicates that requests from the
11276 * VF driver with req_type equal to N shall be forwarded to
11277 * the parent PF driver.
11279 * This field is not valid for the VF driver.
11281 uint32_t vf_req_fwd[8];
11283 * This is a 256-bit bit mask provided by the function driver
11284 * (PF or VF driver) to indicate the list of asynchronous event
11285 * completions to be forwarded.
11287 * Nth bit refers to the Nth event_id.
11289 * Setting Nth bit to 1 by the function driver shall result in
11290 * the HWRM forwarding asynchronous event completion with
11291 * event_id equal to N.
11293 * If all bits are set to 0 (value of 0), then the HWRM shall
11294 * not forward any asynchronous event completion to this
11297 uint32_t async_event_fwd[8];
11298 /* This is the 16bit major version of the driver. */
11300 /* This is the 16bit minor version of the driver. */
11302 /* This is the 16bit update version of the driver. */
11304 /* This is the 16bit patch version of the driver. */
11305 uint16_t ver_patch;
11308 /* hwrm_func_drv_rgtr_output (size:128b/16B) */
11309 struct hwrm_func_drv_rgtr_output {
11310 /* The specific error status for the command. */
11311 uint16_t error_code;
11312 /* The HWRM command request type. */
11314 /* The sequence ID from the original command. */
11316 /* The length of the response data in number of bytes. */
11320 * When this bit is '1', it indicates that the
11321 * HWRM_FUNC_DRV_IF_CHANGE call is supported.
11323 #define HWRM_FUNC_DRV_RGTR_OUTPUT_FLAGS_IF_CHANGE_SUPPORTED \
11325 uint8_t unused_0[3];
11327 * This field is used in Output records to indicate that the output
11328 * is completely written to RAM. This field should be read as '1'
11329 * to indicate that the output has been completely written.
11330 * When writing a command completion or response to an internal processor,
11331 * the order of writes has to be such that this field is written last.
11336 /************************
11337 * hwrm_func_drv_unrgtr *
11338 ************************/
11341 /* hwrm_func_drv_unrgtr_input (size:192b/24B) */
11342 struct hwrm_func_drv_unrgtr_input {
11343 /* The HWRM command request type. */
11346 * The completion ring to send the completion event on. This should
11347 * be the NQ ID returned from the `nq_alloc` HWRM command.
11349 uint16_t cmpl_ring;
11351 * The sequence ID is used by the driver for tracking multiple
11352 * commands. This ID is treated as opaque data by the firmware and
11353 * the value is returned in the `hwrm_resp_hdr` upon completion.
11357 * The target ID of the command:
11358 * * 0x0-0xFFF8 - The function ID
11359 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
11360 * * 0xFFFD - Reserved for user-space HWRM interface
11363 uint16_t target_id;
11365 * A physical address pointer pointing to a host buffer that the
11366 * command's response data will be written. This can be either a host
11367 * physical address (HPA) or a guest physical address (GPA) and must
11368 * point to a physically contiguous block of memory.
11370 uint64_t resp_addr;
11373 * When this bit is '1', the function driver is notifying
11374 * the HWRM to prepare for the shutdown.
11376 #define HWRM_FUNC_DRV_UNRGTR_INPUT_FLAGS_PREPARE_FOR_SHUTDOWN \
11378 uint8_t unused_0[4];
11381 /* hwrm_func_drv_unrgtr_output (size:128b/16B) */
11382 struct hwrm_func_drv_unrgtr_output {
11383 /* The specific error status for the command. */
11384 uint16_t error_code;
11385 /* The HWRM command request type. */
11387 /* The sequence ID from the original command. */
11389 /* The length of the response data in number of bytes. */
11391 uint8_t unused_0[7];
11393 * This field is used in Output records to indicate that the output
11394 * is completely written to RAM. This field should be read as '1'
11395 * to indicate that the output has been completely written.
11396 * When writing a command completion or response to an internal processor,
11397 * the order of writes has to be such that this field is written last.
11402 /**********************
11403 * hwrm_func_buf_rgtr *
11404 **********************/
11407 /* hwrm_func_buf_rgtr_input (size:1024b/128B) */
11408 struct hwrm_func_buf_rgtr_input {
11409 /* The HWRM command request type. */
11412 * The completion ring to send the completion event on. This should
11413 * be the NQ ID returned from the `nq_alloc` HWRM command.
11415 uint16_t cmpl_ring;
11417 * The sequence ID is used by the driver for tracking multiple
11418 * commands. This ID is treated as opaque data by the firmware and
11419 * the value is returned in the `hwrm_resp_hdr` upon completion.
11423 * The target ID of the command:
11424 * * 0x0-0xFFF8 - The function ID
11425 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
11426 * * 0xFFFD - Reserved for user-space HWRM interface
11429 uint16_t target_id;
11431 * A physical address pointer pointing to a host buffer that the
11432 * command's response data will be written. This can be either a host
11433 * physical address (HPA) or a guest physical address (GPA) and must
11434 * point to a physically contiguous block of memory.
11436 uint64_t resp_addr;
11439 * This bit must be '1' for the vf_id field to be
11442 #define HWRM_FUNC_BUF_RGTR_INPUT_ENABLES_VF_ID UINT32_C(0x1)
11444 * This bit must be '1' for the err_buf_addr field to be
11447 #define HWRM_FUNC_BUF_RGTR_INPUT_ENABLES_ERR_BUF_ADDR UINT32_C(0x2)
11449 * This value is used to identify a Virtual Function (VF).
11450 * The scope of VF ID is local within a PF.
11454 * This field represents the number of pages used for request
11457 uint16_t req_buf_num_pages;
11459 * This field represents the page size used for request
11462 uint16_t req_buf_page_size;
11464 #define HWRM_FUNC_BUF_RGTR_INPUT_REQ_BUF_PAGE_SIZE_16B UINT32_C(0x4)
11466 #define HWRM_FUNC_BUF_RGTR_INPUT_REQ_BUF_PAGE_SIZE_4K UINT32_C(0xc)
11468 #define HWRM_FUNC_BUF_RGTR_INPUT_REQ_BUF_PAGE_SIZE_8K UINT32_C(0xd)
11470 #define HWRM_FUNC_BUF_RGTR_INPUT_REQ_BUF_PAGE_SIZE_64K UINT32_C(0x10)
11472 #define HWRM_FUNC_BUF_RGTR_INPUT_REQ_BUF_PAGE_SIZE_2M UINT32_C(0x15)
11474 #define HWRM_FUNC_BUF_RGTR_INPUT_REQ_BUF_PAGE_SIZE_4M UINT32_C(0x16)
11476 #define HWRM_FUNC_BUF_RGTR_INPUT_REQ_BUF_PAGE_SIZE_1G UINT32_C(0x1e)
11477 #define HWRM_FUNC_BUF_RGTR_INPUT_REQ_BUF_PAGE_SIZE_LAST \
11478 HWRM_FUNC_BUF_RGTR_INPUT_REQ_BUF_PAGE_SIZE_1G
11479 /* The length of the request buffer per VF in bytes. */
11480 uint16_t req_buf_len;
11481 /* The length of the response buffer in bytes. */
11482 uint16_t resp_buf_len;
11483 uint8_t unused_0[2];
11484 /* This field represents the page address of page #0. */
11485 uint64_t req_buf_page_addr0;
11486 /* This field represents the page address of page #1. */
11487 uint64_t req_buf_page_addr1;
11488 /* This field represents the page address of page #2. */
11489 uint64_t req_buf_page_addr2;
11490 /* This field represents the page address of page #3. */
11491 uint64_t req_buf_page_addr3;
11492 /* This field represents the page address of page #4. */
11493 uint64_t req_buf_page_addr4;
11494 /* This field represents the page address of page #5. */
11495 uint64_t req_buf_page_addr5;
11496 /* This field represents the page address of page #6. */
11497 uint64_t req_buf_page_addr6;
11498 /* This field represents the page address of page #7. */
11499 uint64_t req_buf_page_addr7;
11500 /* This field represents the page address of page #8. */
11501 uint64_t req_buf_page_addr8;
11502 /* This field represents the page address of page #9. */
11503 uint64_t req_buf_page_addr9;
11505 * This field is used to receive the error reporting from
11506 * the chipset. Only applicable for PFs.
11508 uint64_t error_buf_addr;
11510 * This field is used to receive the response forwarded by the
11513 uint64_t resp_buf_addr;
11516 /* hwrm_func_buf_rgtr_output (size:128b/16B) */
11517 struct hwrm_func_buf_rgtr_output {
11518 /* The specific error status for the command. */
11519 uint16_t error_code;
11520 /* The HWRM command request type. */
11522 /* The sequence ID from the original command. */
11524 /* The length of the response data in number of bytes. */
11526 uint8_t unused_0[7];
11528 * This field is used in Output records to indicate that the output
11529 * is completely written to RAM. This field should be read as '1'
11530 * to indicate that the output has been completely written.
11531 * When writing a command completion or response to an internal processor,
11532 * the order of writes has to be such that this field is written last.
11537 /************************
11538 * hwrm_func_buf_unrgtr *
11539 ************************/
11542 /* hwrm_func_buf_unrgtr_input (size:192b/24B) */
11543 struct hwrm_func_buf_unrgtr_input {
11544 /* The HWRM command request type. */
11547 * The completion ring to send the completion event on. This should
11548 * be the NQ ID returned from the `nq_alloc` HWRM command.
11550 uint16_t cmpl_ring;
11552 * The sequence ID is used by the driver for tracking multiple
11553 * commands. This ID is treated as opaque data by the firmware and
11554 * the value is returned in the `hwrm_resp_hdr` upon completion.
11558 * The target ID of the command:
11559 * * 0x0-0xFFF8 - The function ID
11560 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
11561 * * 0xFFFD - Reserved for user-space HWRM interface
11564 uint16_t target_id;
11566 * A physical address pointer pointing to a host buffer that the
11567 * command's response data will be written. This can be either a host
11568 * physical address (HPA) or a guest physical address (GPA) and must
11569 * point to a physically contiguous block of memory.
11571 uint64_t resp_addr;
11574 * This bit must be '1' for the vf_id field to be
11577 #define HWRM_FUNC_BUF_UNRGTR_INPUT_ENABLES_VF_ID UINT32_C(0x1)
11579 * This value is used to identify a Virtual Function (VF).
11580 * The scope of VF ID is local within a PF.
11583 uint8_t unused_0[2];
11586 /* hwrm_func_buf_unrgtr_output (size:128b/16B) */
11587 struct hwrm_func_buf_unrgtr_output {
11588 /* The specific error status for the command. */
11589 uint16_t error_code;
11590 /* The HWRM command request type. */
11592 /* The sequence ID from the original command. */
11594 /* The length of the response data in number of bytes. */
11596 uint8_t unused_0[7];
11598 * This field is used in Output records to indicate that the output
11599 * is completely written to RAM. This field should be read as '1'
11600 * to indicate that the output has been completely written.
11601 * When writing a command completion or response to an internal processor,
11602 * the order of writes has to be such that this field is written last.
11607 /**********************
11608 * hwrm_func_drv_qver *
11609 **********************/
11612 /* hwrm_func_drv_qver_input (size:192b/24B) */
11613 struct hwrm_func_drv_qver_input {
11614 /* The HWRM command request type. */
11617 * The completion ring to send the completion event on. This should
11618 * be the NQ ID returned from the `nq_alloc` HWRM command.
11620 uint16_t cmpl_ring;
11622 * The sequence ID is used by the driver for tracking multiple
11623 * commands. This ID is treated as opaque data by the firmware and
11624 * the value is returned in the `hwrm_resp_hdr` upon completion.
11628 * The target ID of the command:
11629 * * 0x0-0xFFF8 - The function ID
11630 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
11631 * * 0xFFFD - Reserved for user-space HWRM interface
11634 uint16_t target_id;
11636 * A physical address pointer pointing to a host buffer that the
11637 * command's response data will be written. This can be either a host
11638 * physical address (HPA) or a guest physical address (GPA) and must
11639 * point to a physically contiguous block of memory.
11641 uint64_t resp_addr;
11642 /* Reserved for future use. */
11645 * Function ID of the function that is being queried.
11646 * 0xFF... (All Fs) if the query is for the requesting
11650 uint8_t unused_0[2];
11653 /* hwrm_func_drv_qver_output (size:256b/32B) */
11654 struct hwrm_func_drv_qver_output {
11655 /* The specific error status for the command. */
11656 uint16_t error_code;
11657 /* The HWRM command request type. */
11659 /* The sequence ID from the original command. */
11661 /* The length of the response data in number of bytes. */
11663 /* This value indicates the type of OS. The values are based on CIM_OperatingSystem.mof file as published by the DMTF. */
11666 #define HWRM_FUNC_DRV_QVER_OUTPUT_OS_TYPE_UNKNOWN UINT32_C(0x0)
11667 /* Other OS not listed below. */
11668 #define HWRM_FUNC_DRV_QVER_OUTPUT_OS_TYPE_OTHER UINT32_C(0x1)
11670 #define HWRM_FUNC_DRV_QVER_OUTPUT_OS_TYPE_MSDOS UINT32_C(0xe)
11672 #define HWRM_FUNC_DRV_QVER_OUTPUT_OS_TYPE_WINDOWS UINT32_C(0x12)
11674 #define HWRM_FUNC_DRV_QVER_OUTPUT_OS_TYPE_SOLARIS UINT32_C(0x1d)
11676 #define HWRM_FUNC_DRV_QVER_OUTPUT_OS_TYPE_LINUX UINT32_C(0x24)
11678 #define HWRM_FUNC_DRV_QVER_OUTPUT_OS_TYPE_FREEBSD UINT32_C(0x2a)
11679 /* VMware ESXi OS. */
11680 #define HWRM_FUNC_DRV_QVER_OUTPUT_OS_TYPE_ESXI UINT32_C(0x68)
11681 /* Microsoft Windows 8 64-bit OS. */
11682 #define HWRM_FUNC_DRV_QVER_OUTPUT_OS_TYPE_WIN864 UINT32_C(0x73)
11683 /* Microsoft Windows Server 2012 R2 OS. */
11684 #define HWRM_FUNC_DRV_QVER_OUTPUT_OS_TYPE_WIN2012R2 UINT32_C(0x74)
11686 #define HWRM_FUNC_DRV_QVER_OUTPUT_OS_TYPE_UEFI UINT32_C(0x8000)
11687 #define HWRM_FUNC_DRV_QVER_OUTPUT_OS_TYPE_LAST \
11688 HWRM_FUNC_DRV_QVER_OUTPUT_OS_TYPE_UEFI
11689 /* This is the 8bit major version of the driver. */
11690 uint8_t ver_maj_8b;
11691 /* This is the 8bit minor version of the driver. */
11692 uint8_t ver_min_8b;
11693 /* This is the 8bit update version of the driver. */
11694 uint8_t ver_upd_8b;
11695 uint8_t unused_0[3];
11696 /* This is the 16bit major version of the driver. */
11698 /* This is the 16bit minor version of the driver. */
11700 /* This is the 16bit update version of the driver. */
11702 /* This is the 16bit patch version of the driver. */
11703 uint16_t ver_patch;
11704 uint8_t unused_1[7];
11706 * This field is used in Output records to indicate that the output
11707 * is completely written to RAM. This field should be read as '1'
11708 * to indicate that the output has been completely written.
11709 * When writing a command completion or response to an internal processor,
11710 * the order of writes has to be such that this field is written last.
11715 /****************************
11716 * hwrm_func_resource_qcaps *
11717 ****************************/
11720 /* hwrm_func_resource_qcaps_input (size:192b/24B) */
11721 struct hwrm_func_resource_qcaps_input {
11722 /* The HWRM command request type. */
11725 * The completion ring to send the completion event on. This should
11726 * be the NQ ID returned from the `nq_alloc` HWRM command.
11728 uint16_t cmpl_ring;
11730 * The sequence ID is used by the driver for tracking multiple
11731 * commands. This ID is treated as opaque data by the firmware and
11732 * the value is returned in the `hwrm_resp_hdr` upon completion.
11736 * The target ID of the command:
11737 * * 0x0-0xFFF8 - The function ID
11738 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
11739 * * 0xFFFD - Reserved for user-space HWRM interface
11742 uint16_t target_id;
11744 * A physical address pointer pointing to a host buffer that the
11745 * command's response data will be written. This can be either a host
11746 * physical address (HPA) or a guest physical address (GPA) and must
11747 * point to a physically contiguous block of memory.
11749 uint64_t resp_addr;
11751 * Function ID of the function that is being queried.
11752 * 0xFF... (All Fs) if the query is for the requesting
11756 uint8_t unused_0[6];
11759 /* hwrm_func_resource_qcaps_output (size:448b/56B) */
11760 struct hwrm_func_resource_qcaps_output {
11761 /* The specific error status for the command. */
11762 uint16_t error_code;
11763 /* The HWRM command request type. */
11765 /* The sequence ID from the original command. */
11767 /* The length of the response data in number of bytes. */
11769 /* Maximum guaranteed number of VFs supported by PF. Not applicable for VFs. */
11771 /* Maximum guaranteed number of MSI-X vectors supported by function */
11773 /* Hint of strategy to be used by PF driver to reserve resources for its VF */
11774 uint16_t vf_reservation_strategy;
11775 /* The PF driver should evenly divide its remaining resources among all VFs. */
11776 #define HWRM_FUNC_RESOURCE_QCAPS_OUTPUT_VF_RESERVATION_STRATEGY_MAXIMAL \
11778 /* The PF driver should only reserve minimal resources for each VF. */
11779 #define HWRM_FUNC_RESOURCE_QCAPS_OUTPUT_VF_RESERVATION_STRATEGY_MINIMAL \
11782 * The PF driver should not reserve any resources for each VF until the
11783 * the VF interface is brought up.
11785 #define HWRM_FUNC_RESOURCE_QCAPS_OUTPUT_VF_RESERVATION_STRATEGY_MINIMAL_STATIC \
11787 #define HWRM_FUNC_RESOURCE_QCAPS_OUTPUT_VF_RESERVATION_STRATEGY_LAST \
11788 HWRM_FUNC_RESOURCE_QCAPS_OUTPUT_VF_RESERVATION_STRATEGY_MINIMAL_STATIC
11789 /* Minimum guaranteed number of RSS/COS contexts */
11790 uint16_t min_rsscos_ctx;
11791 /* Maximum non-guaranteed number of RSS/COS contexts */
11792 uint16_t max_rsscos_ctx;
11793 /* Minimum guaranteed number of completion rings */
11794 uint16_t min_cmpl_rings;
11795 /* Maximum non-guaranteed number of completion rings */
11796 uint16_t max_cmpl_rings;
11797 /* Minimum guaranteed number of transmit rings */
11798 uint16_t min_tx_rings;
11799 /* Maximum non-guaranteed number of transmit rings */
11800 uint16_t max_tx_rings;
11801 /* Minimum guaranteed number of receive rings */
11802 uint16_t min_rx_rings;
11803 /* Maximum non-guaranteed number of receive rings */
11804 uint16_t max_rx_rings;
11805 /* Minimum guaranteed number of L2 contexts */
11806 uint16_t min_l2_ctxs;
11807 /* Maximum non-guaranteed number of L2 contexts */
11808 uint16_t max_l2_ctxs;
11809 /* Minimum guaranteed number of VNICs */
11810 uint16_t min_vnics;
11811 /* Maximum non-guaranteed number of VNICs */
11812 uint16_t max_vnics;
11813 /* Minimum guaranteed number of statistic contexts */
11814 uint16_t min_stat_ctx;
11815 /* Maximum non-guaranteed number of statistic contexts */
11816 uint16_t max_stat_ctx;
11817 /* Minimum guaranteed number of ring groups */
11818 uint16_t min_hw_ring_grps;
11819 /* Maximum non-guaranteed number of ring groups */
11820 uint16_t max_hw_ring_grps;
11822 * Maximum number of inputs into the transmit scheduler for this function.
11823 * The number of TX rings assigned to the function cannot exceed this value.
11825 uint16_t max_tx_scheduler_inputs;
11828 * When this bit is '1', it indicates that VF_RESOURCE_CFG supports
11829 * feature to reserve all minimum resources when minimum >= 1, otherwise
11830 * returns an error.
11832 #define HWRM_FUNC_RESOURCE_QCAPS_OUTPUT_FLAGS_MIN_GUARANTEED \
11834 uint8_t unused_0[5];
11836 * This field is used in Output records to indicate that the output
11837 * is completely written to RAM. This field should be read as '1'
11838 * to indicate that the output has been completely written.
11839 * When writing a command completion or response to an internal processor,
11840 * the order of writes has to be such that this field is written last.
11845 /*********************************
11846 * hwrm_func_backing_store_qcaps *
11847 *********************************/
11850 /* hwrm_func_backing_store_qcaps_input (size:128b/16B) */
11851 struct hwrm_func_backing_store_qcaps_input {
11852 /* The HWRM command request type. */
11855 * The completion ring to send the completion event on. This should
11856 * be the NQ ID returned from the `nq_alloc` HWRM command.
11858 uint16_t cmpl_ring;
11860 * The sequence ID is used by the driver for tracking multiple
11861 * commands. This ID is treated as opaque data by the firmware and
11862 * the value is returned in the `hwrm_resp_hdr` upon completion.
11866 * The target ID of the command:
11867 * * 0x0-0xFFF8 - The function ID
11868 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
11869 * * 0xFFFD - Reserved for user-space HWRM interface
11872 uint16_t target_id;
11874 * A physical address pointer pointing to a host buffer that the
11875 * command's response data will be written. This can be either a host
11876 * physical address (HPA) or a guest physical address (GPA) and must
11877 * point to a physically contiguous block of memory.
11879 uint64_t resp_addr;
11882 /* hwrm_func_backing_store_qcaps_output (size:640b/80B) */
11883 struct hwrm_func_backing_store_qcaps_output {
11884 /* The specific error status for the command. */
11885 uint16_t error_code;
11886 /* The HWRM command request type. */
11888 /* The sequence ID from the original command. */
11890 /* The length of the response data in number of bytes. */
11892 /* Maximum number of QP context entries supported for this function. */
11893 uint32_t qp_max_entries;
11895 * Minimum number of QP context entries that are needed to be reserved
11896 * for QP1 for the PF and its VFs. PF drivers must allocate at least
11897 * this many QP context entries, even if RoCE will not be used.
11899 uint16_t qp_min_qp1_entries;
11900 /* Maximum number of QP context entries that can be used for L2. */
11901 uint16_t qp_max_l2_entries;
11902 /* Number of bytes that must be allocated for each context entry. */
11903 uint16_t qp_entry_size;
11904 /* Maximum number of SRQ context entries that can be used for L2. */
11905 uint16_t srq_max_l2_entries;
11906 /* Maximum number of SRQ context entries supported for this function. */
11907 uint32_t srq_max_entries;
11908 /* Number of bytes that must be allocated for each context entry. */
11909 uint16_t srq_entry_size;
11910 /* Maximum number of CQ context entries that can be used for L2. */
11911 uint16_t cq_max_l2_entries;
11912 /* Maximum number of CQ context entries supported for this function. */
11913 uint32_t cq_max_entries;
11914 /* Number of bytes that must be allocated for each context entry. */
11915 uint16_t cq_entry_size;
11916 /* Maximum number of VNIC context entries supported for this function. */
11917 uint16_t vnic_max_vnic_entries;
11918 /* Maximum number of Ring table context entries supported for this function. */
11919 uint16_t vnic_max_ring_table_entries;
11920 /* Number of bytes that must be allocated for each context entry. */
11921 uint16_t vnic_entry_size;
11922 /* Maximum number of statistic context entries supported for this function. */
11923 uint32_t stat_max_entries;
11924 /* Number of bytes that must be allocated for each context entry. */
11925 uint16_t stat_entry_size;
11926 /* Number of bytes that must be allocated for each context entry. */
11927 uint16_t tqm_entry_size;
11928 /* Minimum number of TQM context entries required per ring. */
11929 uint32_t tqm_min_entries_per_ring;
11931 * Maximum number of TQM context entries supported per ring. This is
11932 * actually a recommended TQM queue size based on worst case usage of
11935 * TQM fastpath rings should be sized large enough to accommodate the
11936 * maximum number of QPs (either L2 or RoCE, or both if shared)
11937 * that can be enqueued to the TQM ring.
11939 * TQM slowpath rings should be sized as follows:
11941 * num_entries = num_vnics + num_l2_tx_rings + 2 * num_roce_qps + tqm_min_size
11944 * num_vnics is the number of VNICs allocated in the VNIC backing store
11945 * num_l2_tx_rings is the number of L2 rings in the QP backing store
11946 * num_roce_qps is the number of RoCE QPs in the QP backing store
11947 * tqm_min_size is tqm_min_entries_per_ring reported by
11948 * HWRM_FUNC_BACKING_STORE_QCAPS
11950 * Note that TQM ring sizes cannot be extended while the system is
11951 * operational. If a PF driver needs to extend a TQM ring, it needs
11952 * to reset the function (e.g. HWRM_FUNC_RESET) and then reallocate
11953 * the backing store.
11955 uint32_t tqm_max_entries_per_ring;
11957 * Maximum number of MR plus AV context entries supported for this
11960 uint32_t mrav_max_entries;
11961 /* Number of bytes that must be allocated for each context entry. */
11962 uint16_t mrav_entry_size;
11963 /* Number of bytes that must be allocated for each context entry. */
11964 uint16_t tim_entry_size;
11965 /* Maximum number of Timer context entries supported for this function. */
11966 uint32_t tim_max_entries;
11968 * When this field is zero, the 32b `mrav_num_entries` field in the
11969 * `backing_store_cfg` and `backing_store_qcfg` commands represents
11970 * the total number of MR plus AV entries allowed in the MR/AV backing
11973 * When this field is non-zero, the 32b `mrav_num_entries` field in
11974 * the `backing_store_cfg` and `backing_store_qcfg` commands is
11975 * logically divided into two 16b fields. Bits `[31:16]` represents
11976 * the `mr_num_entries` and bits `[15:0]` represents `av_num_entries`.
11977 * Both of these values are represented in a unit granularity
11978 * specified by this field. For example, if this field is 16 and
11979 * `mrav_num_entries` is `0x02000100`, then the number of MR entries
11980 * is 8192 and the number of AV entries is 4096.
11982 uint16_t mrav_num_entries_units;
11984 * The number of entries specified for any TQM ring must be a
11985 * multiple of this value to prevent any resource allocation
11988 uint8_t tqm_entries_multiple;
11990 * Initializer to be used by drivers
11991 * to initialize context memory to ensure
11992 * context subsystem flags an error for an attack
11993 * before the first time context load.
11995 uint8_t ctx_kind_initializer;
11996 /* Reserved for future. */
11998 /* Reserved for future. */
12001 * Count of TQM fastpath rings to be used for allocating backing store.
12002 * Backing store configuration must be specified for each TQM ring from
12003 * this count in `backing_store_cfg`.
12005 uint8_t tqm_fp_rings_count;
12007 * This field is used in Output records to indicate that the output
12008 * is completely written to RAM. This field should be read as '1'
12009 * to indicate that the output has been completely written.
12010 * When writing a command completion or response to an internal processor,
12011 * the order of writes has to be such that this field is written last.
12016 /*******************************
12017 * hwrm_func_backing_store_cfg *
12018 *******************************/
12021 /* hwrm_func_backing_store_cfg_input (size:2048b/256B) */
12022 struct hwrm_func_backing_store_cfg_input {
12023 /* The HWRM command request type. */
12026 * The completion ring to send the completion event on. This should
12027 * be the NQ ID returned from the `nq_alloc` HWRM command.
12029 uint16_t cmpl_ring;
12031 * The sequence ID is used by the driver for tracking multiple
12032 * commands. This ID is treated as opaque data by the firmware and
12033 * the value is returned in the `hwrm_resp_hdr` upon completion.
12037 * The target ID of the command:
12038 * * 0x0-0xFFF8 - The function ID
12039 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
12040 * * 0xFFFD - Reserved for user-space HWRM interface
12043 uint16_t target_id;
12045 * A physical address pointer pointing to a host buffer that the
12046 * command's response data will be written. This can be either a host
12047 * physical address (HPA) or a guest physical address (GPA) and must
12048 * point to a physically contiguous block of memory.
12050 uint64_t resp_addr;
12053 * When set, the firmware only uses on-chip resources and does not
12054 * expect any backing store to be provided by the host driver. This
12055 * mode provides minimal L2 functionality (e.g. limited L2 resources,
12058 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_FLAGS_PREBOOT_MODE \
12061 * When set, the 32b `mrav_num_entries` field is logically divided
12062 * into two 16b fields, `mr_num_entries` and `av_num_entries`.
12064 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_FLAGS_MRAV_RESERVATION_SPLIT \
12068 * This bit must be '1' for the qp fields to be
12071 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_QP \
12074 * This bit must be '1' for the srq fields to be
12077 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_SRQ \
12080 * This bit must be '1' for the cq fields to be
12083 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_CQ \
12086 * This bit must be '1' for the vnic fields to be
12089 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_VNIC \
12092 * This bit must be '1' for the stat fields to be
12095 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_STAT \
12098 * This bit must be '1' for the tqm_sp fields to be
12101 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_TQM_SP \
12104 * This bit must be '1' for the tqm_ring0 fields to be
12107 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_TQM_RING0 \
12110 * This bit must be '1' for the tqm_ring1 fields to be
12113 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_TQM_RING1 \
12116 * This bit must be '1' for the tqm_ring2 fields to be
12119 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_TQM_RING2 \
12122 * This bit must be '1' for the tqm_ring3 fields to be
12125 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_TQM_RING3 \
12128 * This bit must be '1' for the tqm_ring4 fields to be
12131 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_TQM_RING4 \
12134 * This bit must be '1' for the tqm_ring5 fields to be
12137 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_TQM_RING5 \
12140 * This bit must be '1' for the tqm_ring6 fields to be
12143 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_TQM_RING6 \
12146 * This bit must be '1' for the tqm_ring7 fields to be
12149 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_TQM_RING7 \
12152 * This bit must be '1' for the mrav fields to be
12155 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_MRAV \
12158 * This bit must be '1' for the tim fields to be
12161 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_TIM \
12163 /* QPC page size and level. */
12164 uint8_t qpc_pg_size_qpc_lvl;
12165 /* QPC PBL indirect levels. */
12166 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_QPC_LVL_MASK \
12168 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_QPC_LVL_SFT 0
12169 /* PBL pointer is physical start address. */
12170 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_QPC_LVL_LVL_0 \
12172 /* PBL pointer points to PTE table. */
12173 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_QPC_LVL_LVL_1 \
12175 /* PBL pointer points to PDE table with each entry pointing to PTE tables. */
12176 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_QPC_LVL_LVL_2 \
12178 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_QPC_LVL_LAST \
12179 HWRM_FUNC_BACKING_STORE_CFG_INPUT_QPC_LVL_LVL_2
12180 /* QPC page size. */
12181 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_QPC_PG_SIZE_MASK \
12183 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_QPC_PG_SIZE_SFT 4
12185 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_QPC_PG_SIZE_PG_4K \
12186 (UINT32_C(0x0) << 4)
12188 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_QPC_PG_SIZE_PG_8K \
12189 (UINT32_C(0x1) << 4)
12191 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_QPC_PG_SIZE_PG_64K \
12192 (UINT32_C(0x2) << 4)
12194 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_QPC_PG_SIZE_PG_2M \
12195 (UINT32_C(0x3) << 4)
12197 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_QPC_PG_SIZE_PG_8M \
12198 (UINT32_C(0x4) << 4)
12200 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_QPC_PG_SIZE_PG_1G \
12201 (UINT32_C(0x5) << 4)
12202 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_QPC_PG_SIZE_LAST \
12203 HWRM_FUNC_BACKING_STORE_CFG_INPUT_QPC_PG_SIZE_PG_1G
12204 /* SRQ page size and level. */
12205 uint8_t srq_pg_size_srq_lvl;
12206 /* SRQ PBL indirect levels. */
12207 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_SRQ_LVL_MASK \
12209 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_SRQ_LVL_SFT 0
12210 /* PBL pointer is physical start address. */
12211 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_SRQ_LVL_LVL_0 \
12213 /* PBL pointer points to PTE table. */
12214 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_SRQ_LVL_LVL_1 \
12216 /* PBL pointer points to PDE table with each entry pointing to PTE tables. */
12217 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_SRQ_LVL_LVL_2 \
12219 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_SRQ_LVL_LAST \
12220 HWRM_FUNC_BACKING_STORE_CFG_INPUT_SRQ_LVL_LVL_2
12221 /* SRQ page size. */
12222 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_SRQ_PG_SIZE_MASK \
12224 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_SRQ_PG_SIZE_SFT 4
12226 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_SRQ_PG_SIZE_PG_4K \
12227 (UINT32_C(0x0) << 4)
12229 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_SRQ_PG_SIZE_PG_8K \
12230 (UINT32_C(0x1) << 4)
12232 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_SRQ_PG_SIZE_PG_64K \
12233 (UINT32_C(0x2) << 4)
12235 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_SRQ_PG_SIZE_PG_2M \
12236 (UINT32_C(0x3) << 4)
12238 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_SRQ_PG_SIZE_PG_8M \
12239 (UINT32_C(0x4) << 4)
12241 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_SRQ_PG_SIZE_PG_1G \
12242 (UINT32_C(0x5) << 4)
12243 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_SRQ_PG_SIZE_LAST \
12244 HWRM_FUNC_BACKING_STORE_CFG_INPUT_SRQ_PG_SIZE_PG_1G
12245 /* CQ page size and level. */
12246 uint8_t cq_pg_size_cq_lvl;
12247 /* CQ PBL indirect levels. */
12248 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_CQ_LVL_MASK \
12250 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_CQ_LVL_SFT 0
12251 /* PBL pointer is physical start address. */
12252 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_CQ_LVL_LVL_0 \
12254 /* PBL pointer points to PTE table. */
12255 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_CQ_LVL_LVL_1 \
12257 /* PBL pointer points to PDE table with each entry pointing to PTE tables. */
12258 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_CQ_LVL_LVL_2 \
12260 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_CQ_LVL_LAST \
12261 HWRM_FUNC_BACKING_STORE_CFG_INPUT_CQ_LVL_LVL_2
12262 /* CQ page size. */
12263 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_CQ_PG_SIZE_MASK \
12265 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_CQ_PG_SIZE_SFT 4
12267 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_CQ_PG_SIZE_PG_4K \
12268 (UINT32_C(0x0) << 4)
12270 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_CQ_PG_SIZE_PG_8K \
12271 (UINT32_C(0x1) << 4)
12273 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_CQ_PG_SIZE_PG_64K \
12274 (UINT32_C(0x2) << 4)
12276 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_CQ_PG_SIZE_PG_2M \
12277 (UINT32_C(0x3) << 4)
12279 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_CQ_PG_SIZE_PG_8M \
12280 (UINT32_C(0x4) << 4)
12282 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_CQ_PG_SIZE_PG_1G \
12283 (UINT32_C(0x5) << 4)
12284 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_CQ_PG_SIZE_LAST \
12285 HWRM_FUNC_BACKING_STORE_CFG_INPUT_CQ_PG_SIZE_PG_1G
12286 /* VNIC page size and level. */
12287 uint8_t vnic_pg_size_vnic_lvl;
12288 /* VNIC PBL indirect levels. */
12289 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_VNIC_LVL_MASK \
12291 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_VNIC_LVL_SFT 0
12292 /* PBL pointer is physical start address. */
12293 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_VNIC_LVL_LVL_0 \
12295 /* PBL pointer points to PTE table. */
12296 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_VNIC_LVL_LVL_1 \
12298 /* PBL pointer points to PDE table with each entry pointing to PTE tables. */
12299 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_VNIC_LVL_LVL_2 \
12301 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_VNIC_LVL_LAST \
12302 HWRM_FUNC_BACKING_STORE_CFG_INPUT_VNIC_LVL_LVL_2
12303 /* VNIC page size. */
12304 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_VNIC_PG_SIZE_MASK \
12306 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_VNIC_PG_SIZE_SFT 4
12308 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_VNIC_PG_SIZE_PG_4K \
12309 (UINT32_C(0x0) << 4)
12311 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_VNIC_PG_SIZE_PG_8K \
12312 (UINT32_C(0x1) << 4)
12314 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_VNIC_PG_SIZE_PG_64K \
12315 (UINT32_C(0x2) << 4)
12317 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_VNIC_PG_SIZE_PG_2M \
12318 (UINT32_C(0x3) << 4)
12320 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_VNIC_PG_SIZE_PG_8M \
12321 (UINT32_C(0x4) << 4)
12323 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_VNIC_PG_SIZE_PG_1G \
12324 (UINT32_C(0x5) << 4)
12325 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_VNIC_PG_SIZE_LAST \
12326 HWRM_FUNC_BACKING_STORE_CFG_INPUT_VNIC_PG_SIZE_PG_1G
12327 /* Stat page size and level. */
12328 uint8_t stat_pg_size_stat_lvl;
12329 /* Stat PBL indirect levels. */
12330 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_STAT_LVL_MASK \
12332 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_STAT_LVL_SFT 0
12333 /* PBL pointer is physical start address. */
12334 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_STAT_LVL_LVL_0 \
12336 /* PBL pointer points to PTE table. */
12337 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_STAT_LVL_LVL_1 \
12339 /* PBL pointer points to PDE table with each entry pointing to PTE tables. */
12340 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_STAT_LVL_LVL_2 \
12342 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_STAT_LVL_LAST \
12343 HWRM_FUNC_BACKING_STORE_CFG_INPUT_STAT_LVL_LVL_2
12344 /* Stat page size. */
12345 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_STAT_PG_SIZE_MASK \
12347 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_STAT_PG_SIZE_SFT 4
12349 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_STAT_PG_SIZE_PG_4K \
12350 (UINT32_C(0x0) << 4)
12352 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_STAT_PG_SIZE_PG_8K \
12353 (UINT32_C(0x1) << 4)
12355 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_STAT_PG_SIZE_PG_64K \
12356 (UINT32_C(0x2) << 4)
12358 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_STAT_PG_SIZE_PG_2M \
12359 (UINT32_C(0x3) << 4)
12361 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_STAT_PG_SIZE_PG_8M \
12362 (UINT32_C(0x4) << 4)
12364 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_STAT_PG_SIZE_PG_1G \
12365 (UINT32_C(0x5) << 4)
12366 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_STAT_PG_SIZE_LAST \
12367 HWRM_FUNC_BACKING_STORE_CFG_INPUT_STAT_PG_SIZE_PG_1G
12368 /* TQM slow path page size and level. */
12369 uint8_t tqm_sp_pg_size_tqm_sp_lvl;
12370 /* TQM slow path PBL indirect levels. */
12371 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_SP_LVL_MASK \
12373 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_SP_LVL_SFT 0
12374 /* PBL pointer is physical start address. */
12375 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_SP_LVL_LVL_0 \
12377 /* PBL pointer points to PTE table. */
12378 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_SP_LVL_LVL_1 \
12380 /* PBL pointer points to PDE table with each entry pointing to PTE tables. */
12381 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_SP_LVL_LVL_2 \
12383 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_SP_LVL_LAST \
12384 HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_SP_LVL_LVL_2
12385 /* TQM slow path page size. */
12386 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_SP_PG_SIZE_MASK \
12388 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_SP_PG_SIZE_SFT 4
12390 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_SP_PG_SIZE_PG_4K \
12391 (UINT32_C(0x0) << 4)
12393 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_SP_PG_SIZE_PG_8K \
12394 (UINT32_C(0x1) << 4)
12396 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_SP_PG_SIZE_PG_64K \
12397 (UINT32_C(0x2) << 4)
12399 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_SP_PG_SIZE_PG_2M \
12400 (UINT32_C(0x3) << 4)
12402 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_SP_PG_SIZE_PG_8M \
12403 (UINT32_C(0x4) << 4)
12405 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_SP_PG_SIZE_PG_1G \
12406 (UINT32_C(0x5) << 4)
12407 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_SP_PG_SIZE_LAST \
12408 HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_SP_PG_SIZE_PG_1G
12409 /* TQM ring 0 page size and level. */
12410 uint8_t tqm_ring0_pg_size_tqm_ring0_lvl;
12411 /* TQM ring 0 PBL indirect levels. */
12412 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING0_LVL_MASK \
12414 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING0_LVL_SFT 0
12415 /* PBL pointer is physical start address. */
12416 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING0_LVL_LVL_0 \
12418 /* PBL pointer points to PTE table. */
12419 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING0_LVL_LVL_1 \
12421 /* PBL pointer points to PDE table with each entry pointing to PTE tables. */
12422 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING0_LVL_LVL_2 \
12424 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING0_LVL_LAST \
12425 HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING0_LVL_LVL_2
12426 /* TQM ring 0 page size. */
12427 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING0_PG_SIZE_MASK \
12429 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING0_PG_SIZE_SFT 4
12431 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING0_PG_SIZE_PG_4K \
12432 (UINT32_C(0x0) << 4)
12434 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING0_PG_SIZE_PG_8K \
12435 (UINT32_C(0x1) << 4)
12437 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING0_PG_SIZE_PG_64K \
12438 (UINT32_C(0x2) << 4)
12440 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING0_PG_SIZE_PG_2M \
12441 (UINT32_C(0x3) << 4)
12443 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING0_PG_SIZE_PG_8M \
12444 (UINT32_C(0x4) << 4)
12446 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING0_PG_SIZE_PG_1G \
12447 (UINT32_C(0x5) << 4)
12448 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING0_PG_SIZE_LAST \
12449 HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING0_PG_SIZE_PG_1G
12450 /* TQM ring 1 page size and level. */
12451 uint8_t tqm_ring1_pg_size_tqm_ring1_lvl;
12452 /* TQM ring 1 PBL indirect levels. */
12453 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING1_LVL_MASK \
12455 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING1_LVL_SFT 0
12456 /* PBL pointer is physical start address. */
12457 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING1_LVL_LVL_0 \
12459 /* PBL pointer points to PTE table. */
12460 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING1_LVL_LVL_1 \
12462 /* PBL pointer points to PDE table with each entry pointing to PTE tables. */
12463 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING1_LVL_LVL_2 \
12465 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING1_LVL_LAST \
12466 HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING1_LVL_LVL_2
12467 /* TQM ring 1 page size. */
12468 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING1_PG_SIZE_MASK \
12470 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING1_PG_SIZE_SFT 4
12472 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING1_PG_SIZE_PG_4K \
12473 (UINT32_C(0x0) << 4)
12475 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING1_PG_SIZE_PG_8K \
12476 (UINT32_C(0x1) << 4)
12478 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING1_PG_SIZE_PG_64K \
12479 (UINT32_C(0x2) << 4)
12481 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING1_PG_SIZE_PG_2M \
12482 (UINT32_C(0x3) << 4)
12484 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING1_PG_SIZE_PG_8M \
12485 (UINT32_C(0x4) << 4)
12487 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING1_PG_SIZE_PG_1G \
12488 (UINT32_C(0x5) << 4)
12489 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING1_PG_SIZE_LAST \
12490 HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING1_PG_SIZE_PG_1G
12491 /* TQM ring 2 page size and level. */
12492 uint8_t tqm_ring2_pg_size_tqm_ring2_lvl;
12493 /* TQM ring 2 PBL indirect levels. */
12494 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING2_LVL_MASK \
12496 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING2_LVL_SFT 0
12497 /* PBL pointer is physical start address. */
12498 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING2_LVL_LVL_0 \
12500 /* PBL pointer points to PTE table. */
12501 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING2_LVL_LVL_1 \
12503 /* PBL pointer points to PDE table with each entry pointing to PTE tables. */
12504 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING2_LVL_LVL_2 \
12506 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING2_LVL_LAST \
12507 HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING2_LVL_LVL_2
12508 /* TQM ring 2 page size. */
12509 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING2_PG_SIZE_MASK \
12511 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING2_PG_SIZE_SFT 4
12513 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING2_PG_SIZE_PG_4K \
12514 (UINT32_C(0x0) << 4)
12516 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING2_PG_SIZE_PG_8K \
12517 (UINT32_C(0x1) << 4)
12519 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING2_PG_SIZE_PG_64K \
12520 (UINT32_C(0x2) << 4)
12522 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING2_PG_SIZE_PG_2M \
12523 (UINT32_C(0x3) << 4)
12525 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING2_PG_SIZE_PG_8M \
12526 (UINT32_C(0x4) << 4)
12528 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING2_PG_SIZE_PG_1G \
12529 (UINT32_C(0x5) << 4)
12530 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING2_PG_SIZE_LAST \
12531 HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING2_PG_SIZE_PG_1G
12532 /* TQM ring 3 page size and level. */
12533 uint8_t tqm_ring3_pg_size_tqm_ring3_lvl;
12534 /* TQM ring 3 PBL indirect levels. */
12535 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING3_LVL_MASK \
12537 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING3_LVL_SFT 0
12538 /* PBL pointer is physical start address. */
12539 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING3_LVL_LVL_0 \
12541 /* PBL pointer points to PTE table. */
12542 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING3_LVL_LVL_1 \
12544 /* PBL pointer points to PDE table with each entry pointing to PTE tables. */
12545 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING3_LVL_LVL_2 \
12547 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING3_LVL_LAST \
12548 HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING3_LVL_LVL_2
12549 /* TQM ring 3 page size. */
12550 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING3_PG_SIZE_MASK \
12552 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING3_PG_SIZE_SFT 4
12554 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING3_PG_SIZE_PG_4K \
12555 (UINT32_C(0x0) << 4)
12557 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING3_PG_SIZE_PG_8K \
12558 (UINT32_C(0x1) << 4)
12560 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING3_PG_SIZE_PG_64K \
12561 (UINT32_C(0x2) << 4)
12563 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING3_PG_SIZE_PG_2M \
12564 (UINT32_C(0x3) << 4)
12566 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING3_PG_SIZE_PG_8M \
12567 (UINT32_C(0x4) << 4)
12569 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING3_PG_SIZE_PG_1G \
12570 (UINT32_C(0x5) << 4)
12571 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING3_PG_SIZE_LAST \
12572 HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING3_PG_SIZE_PG_1G
12573 /* TQM ring 4 page size and level. */
12574 uint8_t tqm_ring4_pg_size_tqm_ring4_lvl;
12575 /* TQM ring 4 PBL indirect levels. */
12576 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING4_LVL_MASK \
12578 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING4_LVL_SFT 0
12579 /* PBL pointer is physical start address. */
12580 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING4_LVL_LVL_0 \
12582 /* PBL pointer points to PTE table. */
12583 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING4_LVL_LVL_1 \
12585 /* PBL pointer points to PDE table with each entry pointing to PTE tables. */
12586 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING4_LVL_LVL_2 \
12588 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING4_LVL_LAST \
12589 HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING4_LVL_LVL_2
12590 /* TQM ring 4 page size. */
12591 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING4_PG_SIZE_MASK \
12593 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING4_PG_SIZE_SFT 4
12595 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING4_PG_SIZE_PG_4K \
12596 (UINT32_C(0x0) << 4)
12598 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING4_PG_SIZE_PG_8K \
12599 (UINT32_C(0x1) << 4)
12601 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING4_PG_SIZE_PG_64K \
12602 (UINT32_C(0x2) << 4)
12604 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING4_PG_SIZE_PG_2M \
12605 (UINT32_C(0x3) << 4)
12607 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING4_PG_SIZE_PG_8M \
12608 (UINT32_C(0x4) << 4)
12610 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING4_PG_SIZE_PG_1G \
12611 (UINT32_C(0x5) << 4)
12612 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING4_PG_SIZE_LAST \
12613 HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING4_PG_SIZE_PG_1G
12614 /* TQM ring 5 page size and level. */
12615 uint8_t tqm_ring5_pg_size_tqm_ring5_lvl;
12616 /* TQM ring 5 PBL indirect levels. */
12617 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING5_LVL_MASK \
12619 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING5_LVL_SFT 0
12620 /* PBL pointer is physical start address. */
12621 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING5_LVL_LVL_0 \
12623 /* PBL pointer points to PTE table. */
12624 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING5_LVL_LVL_1 \
12626 /* PBL pointer points to PDE table with each entry pointing to PTE tables. */
12627 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING5_LVL_LVL_2 \
12629 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING5_LVL_LAST \
12630 HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING5_LVL_LVL_2
12631 /* TQM ring 5 page size. */
12632 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING5_PG_SIZE_MASK \
12634 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING5_PG_SIZE_SFT 4
12636 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING5_PG_SIZE_PG_4K \
12637 (UINT32_C(0x0) << 4)
12639 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING5_PG_SIZE_PG_8K \
12640 (UINT32_C(0x1) << 4)
12642 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING5_PG_SIZE_PG_64K \
12643 (UINT32_C(0x2) << 4)
12645 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING5_PG_SIZE_PG_2M \
12646 (UINT32_C(0x3) << 4)
12648 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING5_PG_SIZE_PG_8M \
12649 (UINT32_C(0x4) << 4)
12651 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING5_PG_SIZE_PG_1G \
12652 (UINT32_C(0x5) << 4)
12653 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING5_PG_SIZE_LAST \
12654 HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING5_PG_SIZE_PG_1G
12655 /* TQM ring 6 page size and level. */
12656 uint8_t tqm_ring6_pg_size_tqm_ring6_lvl;
12657 /* TQM ring 6 PBL indirect levels. */
12658 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING6_LVL_MASK \
12660 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING6_LVL_SFT 0
12661 /* PBL pointer is physical start address. */
12662 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING6_LVL_LVL_0 \
12664 /* PBL pointer points to PTE table. */
12665 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING6_LVL_LVL_1 \
12667 /* PBL pointer points to PDE table with each entry pointing to PTE tables. */
12668 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING6_LVL_LVL_2 \
12670 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING6_LVL_LAST \
12671 HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING6_LVL_LVL_2
12672 /* TQM ring 6 page size. */
12673 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING6_PG_SIZE_MASK \
12675 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING6_PG_SIZE_SFT 4
12677 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING6_PG_SIZE_PG_4K \
12678 (UINT32_C(0x0) << 4)
12680 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING6_PG_SIZE_PG_8K \
12681 (UINT32_C(0x1) << 4)
12683 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING6_PG_SIZE_PG_64K \
12684 (UINT32_C(0x2) << 4)
12686 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING6_PG_SIZE_PG_2M \
12687 (UINT32_C(0x3) << 4)
12689 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING6_PG_SIZE_PG_8M \
12690 (UINT32_C(0x4) << 4)
12692 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING6_PG_SIZE_PG_1G \
12693 (UINT32_C(0x5) << 4)
12694 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING6_PG_SIZE_LAST \
12695 HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING6_PG_SIZE_PG_1G
12696 /* TQM ring 7 page size and level. */
12697 uint8_t tqm_ring7_pg_size_tqm_ring7_lvl;
12698 /* TQM ring 7 PBL indirect levels. */
12699 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING7_LVL_MASK \
12701 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING7_LVL_SFT 0
12702 /* PBL pointer is physical start address. */
12703 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING7_LVL_LVL_0 \
12705 /* PBL pointer points to PTE table. */
12706 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING7_LVL_LVL_1 \
12708 /* PBL pointer points to PDE table with each entry pointing to PTE tables. */
12709 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING7_LVL_LVL_2 \
12711 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING7_LVL_LAST \
12712 HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING7_LVL_LVL_2
12713 /* TQM ring 7 page size. */
12714 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING7_PG_SIZE_MASK \
12716 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING7_PG_SIZE_SFT 4
12718 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING7_PG_SIZE_PG_4K \
12719 (UINT32_C(0x0) << 4)
12721 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING7_PG_SIZE_PG_8K \
12722 (UINT32_C(0x1) << 4)
12724 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING7_PG_SIZE_PG_64K \
12725 (UINT32_C(0x2) << 4)
12727 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING7_PG_SIZE_PG_2M \
12728 (UINT32_C(0x3) << 4)
12730 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING7_PG_SIZE_PG_8M \
12731 (UINT32_C(0x4) << 4)
12733 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING7_PG_SIZE_PG_1G \
12734 (UINT32_C(0x5) << 4)
12735 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING7_PG_SIZE_LAST \
12736 HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING7_PG_SIZE_PG_1G
12737 /* MR/AV page size and level. */
12738 uint8_t mrav_pg_size_mrav_lvl;
12739 /* MR/AV PBL indirect levels. */
12740 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_MRAV_LVL_MASK \
12742 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_MRAV_LVL_SFT 0
12743 /* PBL pointer is physical start address. */
12744 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_MRAV_LVL_LVL_0 \
12746 /* PBL pointer points to PTE table. */
12747 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_MRAV_LVL_LVL_1 \
12749 /* PBL pointer points to PDE table with each entry pointing to PTE tables. */
12750 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_MRAV_LVL_LVL_2 \
12752 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_MRAV_LVL_LAST \
12753 HWRM_FUNC_BACKING_STORE_CFG_INPUT_MRAV_LVL_LVL_2
12754 /* MR/AV page size. */
12755 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_MRAV_PG_SIZE_MASK \
12757 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_MRAV_PG_SIZE_SFT 4
12759 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_MRAV_PG_SIZE_PG_4K \
12760 (UINT32_C(0x0) << 4)
12762 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_MRAV_PG_SIZE_PG_8K \
12763 (UINT32_C(0x1) << 4)
12765 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_MRAV_PG_SIZE_PG_64K \
12766 (UINT32_C(0x2) << 4)
12768 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_MRAV_PG_SIZE_PG_2M \
12769 (UINT32_C(0x3) << 4)
12771 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_MRAV_PG_SIZE_PG_8M \
12772 (UINT32_C(0x4) << 4)
12774 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_MRAV_PG_SIZE_PG_1G \
12775 (UINT32_C(0x5) << 4)
12776 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_MRAV_PG_SIZE_LAST \
12777 HWRM_FUNC_BACKING_STORE_CFG_INPUT_MRAV_PG_SIZE_PG_1G
12778 /* Timer page size and level. */
12779 uint8_t tim_pg_size_tim_lvl;
12780 /* Timer PBL indirect levels. */
12781 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TIM_LVL_MASK \
12783 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TIM_LVL_SFT 0
12784 /* PBL pointer is physical start address. */
12785 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TIM_LVL_LVL_0 \
12787 /* PBL pointer points to PTE table. */
12788 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TIM_LVL_LVL_1 \
12790 /* PBL pointer points to PDE table with each entry pointing to PTE tables. */
12791 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TIM_LVL_LVL_2 \
12793 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TIM_LVL_LAST \
12794 HWRM_FUNC_BACKING_STORE_CFG_INPUT_TIM_LVL_LVL_2
12795 /* Timer page size. */
12796 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TIM_PG_SIZE_MASK \
12798 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TIM_PG_SIZE_SFT 4
12800 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TIM_PG_SIZE_PG_4K \
12801 (UINT32_C(0x0) << 4)
12803 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TIM_PG_SIZE_PG_8K \
12804 (UINT32_C(0x1) << 4)
12806 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TIM_PG_SIZE_PG_64K \
12807 (UINT32_C(0x2) << 4)
12809 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TIM_PG_SIZE_PG_2M \
12810 (UINT32_C(0x3) << 4)
12812 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TIM_PG_SIZE_PG_8M \
12813 (UINT32_C(0x4) << 4)
12815 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TIM_PG_SIZE_PG_1G \
12816 (UINT32_C(0x5) << 4)
12817 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TIM_PG_SIZE_LAST \
12818 HWRM_FUNC_BACKING_STORE_CFG_INPUT_TIM_PG_SIZE_PG_1G
12819 /* QP page directory. */
12820 uint64_t qpc_page_dir;
12821 /* SRQ page directory. */
12822 uint64_t srq_page_dir;
12823 /* CQ page directory. */
12824 uint64_t cq_page_dir;
12825 /* VNIC page directory. */
12826 uint64_t vnic_page_dir;
12827 /* Stat page directory. */
12828 uint64_t stat_page_dir;
12829 /* TQM slowpath page directory. */
12830 uint64_t tqm_sp_page_dir;
12831 /* TQM ring 0 page directory. */
12832 uint64_t tqm_ring0_page_dir;
12833 /* TQM ring 1 page directory. */
12834 uint64_t tqm_ring1_page_dir;
12835 /* TQM ring 2 page directory. */
12836 uint64_t tqm_ring2_page_dir;
12837 /* TQM ring 3 page directory. */
12838 uint64_t tqm_ring3_page_dir;
12839 /* TQM ring 4 page directory. */
12840 uint64_t tqm_ring4_page_dir;
12841 /* TQM ring 5 page directory. */
12842 uint64_t tqm_ring5_page_dir;
12843 /* TQM ring 6 page directory. */
12844 uint64_t tqm_ring6_page_dir;
12845 /* TQM ring 7 page directory. */
12846 uint64_t tqm_ring7_page_dir;
12847 /* MR/AV page directory. */
12848 uint64_t mrav_page_dir;
12849 /* Timer page directory. */
12850 uint64_t tim_page_dir;
12851 /* Number of QPs. */
12852 uint32_t qp_num_entries;
12853 /* Number of SRQs. */
12854 uint32_t srq_num_entries;
12855 /* Number of CQs. */
12856 uint32_t cq_num_entries;
12857 /* Number of Stats. */
12858 uint32_t stat_num_entries;
12860 * Number of TQM slowpath entries.
12862 * TQM slowpath rings should be sized as follows:
12864 * num_entries = num_vnics + num_l2_tx_rings + 2 * num_roce_qps + tqm_min_size
12867 * num_vnics is the number of VNICs allocated in the VNIC backing store
12868 * num_l2_tx_rings is the number of L2 rings in the QP backing store
12869 * num_roce_qps is the number of RoCE QPs in the QP backing store
12870 * tqm_min_size is tqm_min_entries_per_ring reported by
12871 * HWRM_FUNC_BACKING_STORE_QCAPS
12873 * Note that TQM ring sizes cannot be extended while the system is
12874 * operational. If a PF driver needs to extend a TQM ring, it needs
12875 * to reset the function (e.g. HWRM_FUNC_RESET) and then reallocate
12876 * the backing store.
12878 uint32_t tqm_sp_num_entries;
12880 * Number of TQM ring 0 entries.
12882 * TQM fastpath rings should be sized large enough to accommodate the
12883 * maximum number of QPs (either L2 or RoCE, or both if shared)
12884 * that can be enqueued to the TQM ring.
12886 * Note that TQM ring sizes cannot be extended while the system is
12887 * operational. If a PF driver needs to extend a TQM ring, it needs
12888 * to reset the function (e.g. HWRM_FUNC_RESET) and then reallocate
12889 * the backing store.
12891 uint32_t tqm_ring0_num_entries;
12893 * Number of TQM ring 1 entries.
12895 * TQM fastpath rings should be sized large enough to accommodate the
12896 * maximum number of QPs (either L2 or RoCE, or both if shared)
12897 * that can be enqueued to the TQM ring.
12899 * Note that TQM ring sizes cannot be extended while the system is
12900 * operational. If a PF driver needs to extend a TQM ring, it needs
12901 * to reset the function (e.g. HWRM_FUNC_RESET) and then reallocate
12902 * the backing store.
12904 uint32_t tqm_ring1_num_entries;
12906 * Number of TQM ring 2 entries.
12908 * TQM fastpath rings should be sized large enough to accommodate the
12909 * maximum number of QPs (either L2 or RoCE, or both if shared)
12910 * that can be enqueued to the TQM ring.
12912 * Note that TQM ring sizes cannot be extended while the system is
12913 * operational. If a PF driver needs to extend a TQM ring, it needs
12914 * to reset the function (e.g. HWRM_FUNC_RESET) and then reallocate
12915 * the backing store.
12917 uint32_t tqm_ring2_num_entries;
12919 * Number of TQM ring 3 entries.
12921 * TQM fastpath rings should be sized large enough to accommodate the
12922 * maximum number of QPs (either L2 or RoCE, or both if shared)
12923 * that can be enqueued to the TQM ring.
12925 * Note that TQM ring sizes cannot be extended while the system is
12926 * operational. If a PF driver needs to extend a TQM ring, it needs
12927 * to reset the function (e.g. HWRM_FUNC_RESET) and then reallocate
12928 * the backing store.
12930 uint32_t tqm_ring3_num_entries;
12932 * Number of TQM ring 4 entries.
12934 * TQM fastpath rings should be sized large enough to accommodate the
12935 * maximum number of QPs (either L2 or RoCE, or both if shared)
12936 * that can be enqueued to the TQM ring.
12938 * Note that TQM ring sizes cannot be extended while the system is
12939 * operational. If a PF driver needs to extend a TQM ring, it needs
12940 * to reset the function (e.g. HWRM_FUNC_RESET) and then reallocate
12941 * the backing store.
12943 uint32_t tqm_ring4_num_entries;
12945 * Number of TQM ring 5 entries.
12947 * TQM fastpath rings should be sized large enough to accommodate the
12948 * maximum number of QPs (either L2 or RoCE, or both if shared)
12949 * that can be enqueued to the TQM ring.
12951 * Note that TQM ring sizes cannot be extended while the system is
12952 * operational. If a PF driver needs to extend a TQM ring, it needs
12953 * to reset the function (e.g. HWRM_FUNC_RESET) and then reallocate
12954 * the backing store.
12956 uint32_t tqm_ring5_num_entries;
12958 * Number of TQM ring 6 entries.
12960 * TQM fastpath rings should be sized large enough to accommodate the
12961 * maximum number of QPs (either L2 or RoCE, or both if shared)
12962 * that can be enqueued to the TQM ring.
12964 * Note that TQM ring sizes cannot be extended while the system is
12965 * operational. If a PF driver needs to extend a TQM ring, it needs
12966 * to reset the function (e.g. HWRM_FUNC_RESET) and then reallocate
12967 * the backing store.
12969 uint32_t tqm_ring6_num_entries;
12971 * Number of TQM ring 7 entries.
12973 * TQM fastpath rings should be sized large enough to accommodate the
12974 * maximum number of QPs (either L2 or RoCE, or both if shared)
12975 * that can be enqueued to the TQM ring.
12977 * Note that TQM ring sizes cannot be extended while the system is
12978 * operational. If a PF driver needs to extend a TQM ring, it needs
12979 * to reset the function (e.g. HWRM_FUNC_RESET) and then reallocate
12980 * the backing store.
12982 uint32_t tqm_ring7_num_entries;
12984 * If the MR/AV split reservation flag is not set, then this field
12985 * represents the total number of MR plus AV entries. For versions
12986 * of firmware that support the split reservation, when it is not
12987 * specified half of the entries will be reserved for MRs and the
12988 * other half for AVs.
12990 * If the MR/AV split reservation flag is set, then this
12991 * field is logically divided into two 16b fields. Bits `[31:16]`
12992 * represents the `mr_num_entries` and bits `[15:0]` represents
12993 * `av_num_entries`. The granularity of these values is defined by
12994 * the `mrav_num_entries_unit` field returned by the
12995 * `backing_store_qcaps` command.
12997 uint32_t mrav_num_entries;
12998 /* Number of Timer entries. */
12999 uint32_t tim_num_entries;
13000 /* Number of entries to reserve for QP1 */
13001 uint16_t qp_num_qp1_entries;
13002 /* Number of entries to reserve for L2 */
13003 uint16_t qp_num_l2_entries;
13004 /* Number of bytes that have been allocated for each context entry. */
13005 uint16_t qp_entry_size;
13006 /* Number of entries to reserve for L2 */
13007 uint16_t srq_num_l2_entries;
13008 /* Number of bytes that have been allocated for each context entry. */
13009 uint16_t srq_entry_size;
13010 /* Number of entries to reserve for L2 */
13011 uint16_t cq_num_l2_entries;
13012 /* Number of bytes that have been allocated for each context entry. */
13013 uint16_t cq_entry_size;
13014 /* Number of entries to reserve for VNIC entries */
13015 uint16_t vnic_num_vnic_entries;
13016 /* Number of entries to reserve for Ring table entries */
13017 uint16_t vnic_num_ring_table_entries;
13018 /* Number of bytes that have been allocated for each context entry. */
13019 uint16_t vnic_entry_size;
13020 /* Number of bytes that have been allocated for each context entry. */
13021 uint16_t stat_entry_size;
13022 /* Number of bytes that have been allocated for each context entry. */
13023 uint16_t tqm_entry_size;
13024 /* Number of bytes that have been allocated for each context entry. */
13025 uint16_t mrav_entry_size;
13026 /* Number of bytes that have been allocated for each context entry. */
13027 uint16_t tim_entry_size;
13030 /* hwrm_func_backing_store_cfg_output (size:128b/16B) */
13031 struct hwrm_func_backing_store_cfg_output {
13032 /* The specific error status for the command. */
13033 uint16_t error_code;
13034 /* The HWRM command request type. */
13036 /* The sequence ID from the original command. */
13038 /* The length of the response data in number of bytes. */
13040 uint8_t unused_0[7];
13042 * This field is used in Output records to indicate that the output
13043 * is completely written to RAM. This field should be read as '1'
13044 * to indicate that the output has been completely written.
13045 * When writing a command completion or response to an internal processor,
13046 * the order of writes has to be such that this field is written last.
13051 /********************************
13052 * hwrm_func_backing_store_qcfg *
13053 ********************************/
13056 /* hwrm_func_backing_store_qcfg_input (size:128b/16B) */
13057 struct hwrm_func_backing_store_qcfg_input {
13058 /* The HWRM command request type. */
13061 * The completion ring to send the completion event on. This should
13062 * be the NQ ID returned from the `nq_alloc` HWRM command.
13064 uint16_t cmpl_ring;
13066 * The sequence ID is used by the driver for tracking multiple
13067 * commands. This ID is treated as opaque data by the firmware and
13068 * the value is returned in the `hwrm_resp_hdr` upon completion.
13072 * The target ID of the command:
13073 * * 0x0-0xFFF8 - The function ID
13074 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
13075 * * 0xFFFD - Reserved for user-space HWRM interface
13078 uint16_t target_id;
13080 * A physical address pointer pointing to a host buffer that the
13081 * command's response data will be written. This can be either a host
13082 * physical address (HPA) or a guest physical address (GPA) and must
13083 * point to a physically contiguous block of memory.
13085 uint64_t resp_addr;
13088 /* hwrm_func_backing_store_qcfg_output (size:1920b/240B) */
13089 struct hwrm_func_backing_store_qcfg_output {
13090 /* The specific error status for the command. */
13091 uint16_t error_code;
13092 /* The HWRM command request type. */
13094 /* The sequence ID from the original command. */
13096 /* The length of the response data in number of bytes. */
13100 * When set, the firmware only uses on-chip resources and does not
13101 * expect any backing store to be provided by the host driver. This
13102 * mode provides minimal L2 functionality (e.g. limited L2 resources,
13105 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_FLAGS_PREBOOT_MODE \
13108 * When set, the 32b `mrav_num_entries` field is logically divided
13109 * into two 16b fields, `mr_num_entries` and `av_num_entries`.
13111 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_FLAGS_MRAV_RESERVATION_SPLIT \
13113 uint8_t unused_0[4];
13115 * This bit must be '1' for the qp fields to be
13118 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_UNUSED_0_QP \
13121 * This bit must be '1' for the srq fields to be
13124 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_UNUSED_0_SRQ \
13127 * This bit must be '1' for the cq fields to be
13130 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_UNUSED_0_CQ \
13133 * This bit must be '1' for the vnic fields to be
13136 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_UNUSED_0_VNIC \
13139 * This bit must be '1' for the stat fields to be
13142 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_UNUSED_0_STAT \
13145 * This bit must be '1' for the tqm_sp fields to be
13148 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_UNUSED_0_TQM_SP \
13151 * This bit must be '1' for the tqm_ring0 fields to be
13154 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_UNUSED_0_TQM_RING0 \
13157 * This bit must be '1' for the tqm_ring1 fields to be
13160 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_UNUSED_0_TQM_RING1 \
13163 * This bit must be '1' for the tqm_ring2 fields to be
13166 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_UNUSED_0_TQM_RING2 \
13169 * This bit must be '1' for the tqm_ring3 fields to be
13172 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_UNUSED_0_TQM_RING3 \
13175 * This bit must be '1' for the tqm_ring4 fields to be
13178 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_UNUSED_0_TQM_RING4 \
13181 * This bit must be '1' for the tqm_ring5 fields to be
13184 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_UNUSED_0_TQM_RING5 \
13187 * This bit must be '1' for the tqm_ring6 fields to be
13190 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_UNUSED_0_TQM_RING6 \
13193 * This bit must be '1' for the tqm_ring7 fields to be
13196 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_UNUSED_0_TQM_RING7 \
13199 * This bit must be '1' for the mrav fields to be
13202 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_UNUSED_0_MRAV \
13205 * This bit must be '1' for the tim fields to be
13208 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_UNUSED_0_TIM \
13210 /* QPC page size and level. */
13211 uint8_t qpc_pg_size_qpc_lvl;
13212 /* QPC PBL indirect levels. */
13213 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_QPC_LVL_MASK \
13215 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_QPC_LVL_SFT 0
13216 /* PBL pointer is physical start address. */
13217 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_QPC_LVL_LVL_0 \
13219 /* PBL pointer points to PTE table. */
13220 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_QPC_LVL_LVL_1 \
13222 /* PBL pointer points to PDE table with each entry pointing to PTE tables. */
13223 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_QPC_LVL_LVL_2 \
13225 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_QPC_LVL_LAST \
13226 HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_QPC_LVL_LVL_2
13227 /* QPC page size. */
13228 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_QPC_PG_SIZE_MASK \
13230 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_QPC_PG_SIZE_SFT 4
13232 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_QPC_PG_SIZE_PG_4K \
13233 (UINT32_C(0x0) << 4)
13235 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_QPC_PG_SIZE_PG_8K \
13236 (UINT32_C(0x1) << 4)
13238 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_QPC_PG_SIZE_PG_64K \
13239 (UINT32_C(0x2) << 4)
13241 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_QPC_PG_SIZE_PG_2M \
13242 (UINT32_C(0x3) << 4)
13244 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_QPC_PG_SIZE_PG_8M \
13245 (UINT32_C(0x4) << 4)
13247 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_QPC_PG_SIZE_PG_1G \
13248 (UINT32_C(0x5) << 4)
13249 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_QPC_PG_SIZE_LAST \
13250 HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_QPC_PG_SIZE_PG_1G
13251 /* SRQ page size and level. */
13252 uint8_t srq_pg_size_srq_lvl;
13253 /* SRQ PBL indirect levels. */
13254 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_SRQ_LVL_MASK \
13256 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_SRQ_LVL_SFT 0
13257 /* PBL pointer is physical start address. */
13258 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_SRQ_LVL_LVL_0 \
13260 /* PBL pointer points to PTE table. */
13261 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_SRQ_LVL_LVL_1 \
13263 /* PBL pointer points to PDE table with each entry pointing to PTE tables. */
13264 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_SRQ_LVL_LVL_2 \
13266 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_SRQ_LVL_LAST \
13267 HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_SRQ_LVL_LVL_2
13268 /* SRQ page size. */
13269 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_SRQ_PG_SIZE_MASK \
13271 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_SRQ_PG_SIZE_SFT 4
13273 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_SRQ_PG_SIZE_PG_4K \
13274 (UINT32_C(0x0) << 4)
13276 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_SRQ_PG_SIZE_PG_8K \
13277 (UINT32_C(0x1) << 4)
13279 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_SRQ_PG_SIZE_PG_64K \
13280 (UINT32_C(0x2) << 4)
13282 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_SRQ_PG_SIZE_PG_2M \
13283 (UINT32_C(0x3) << 4)
13285 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_SRQ_PG_SIZE_PG_8M \
13286 (UINT32_C(0x4) << 4)
13288 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_SRQ_PG_SIZE_PG_1G \
13289 (UINT32_C(0x5) << 4)
13290 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_SRQ_PG_SIZE_LAST \
13291 HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_SRQ_PG_SIZE_PG_1G
13292 /* CQ page size and level. */
13293 uint8_t cq_pg_size_cq_lvl;
13294 /* CQ PBL indirect levels. */
13295 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_CQ_LVL_MASK \
13297 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_CQ_LVL_SFT 0
13298 /* PBL pointer is physical start address. */
13299 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_CQ_LVL_LVL_0 \
13301 /* PBL pointer points to PTE table. */
13302 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_CQ_LVL_LVL_1 \
13304 /* PBL pointer points to PDE table with each entry pointing to PTE tables. */
13305 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_CQ_LVL_LVL_2 \
13307 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_CQ_LVL_LAST \
13308 HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_CQ_LVL_LVL_2
13309 /* CQ page size. */
13310 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_CQ_PG_SIZE_MASK \
13312 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_CQ_PG_SIZE_SFT 4
13314 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_CQ_PG_SIZE_PG_4K \
13315 (UINT32_C(0x0) << 4)
13317 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_CQ_PG_SIZE_PG_8K \
13318 (UINT32_C(0x1) << 4)
13320 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_CQ_PG_SIZE_PG_64K \
13321 (UINT32_C(0x2) << 4)
13323 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_CQ_PG_SIZE_PG_2M \
13324 (UINT32_C(0x3) << 4)
13326 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_CQ_PG_SIZE_PG_8M \
13327 (UINT32_C(0x4) << 4)
13329 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_CQ_PG_SIZE_PG_1G \
13330 (UINT32_C(0x5) << 4)
13331 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_CQ_PG_SIZE_LAST \
13332 HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_CQ_PG_SIZE_PG_1G
13333 /* VNIC page size and level. */
13334 uint8_t vnic_pg_size_vnic_lvl;
13335 /* VNIC PBL indirect levels. */
13336 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_VNIC_LVL_MASK \
13338 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_VNIC_LVL_SFT 0
13339 /* PBL pointer is physical start address. */
13340 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_VNIC_LVL_LVL_0 \
13342 /* PBL pointer points to PTE table. */
13343 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_VNIC_LVL_LVL_1 \
13345 /* PBL pointer points to PDE table with each entry pointing to PTE tables. */
13346 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_VNIC_LVL_LVL_2 \
13348 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_VNIC_LVL_LAST \
13349 HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_VNIC_LVL_LVL_2
13350 /* VNIC page size. */
13351 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_VNIC_PG_SIZE_MASK \
13353 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_VNIC_PG_SIZE_SFT 4
13355 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_VNIC_PG_SIZE_PG_4K \
13356 (UINT32_C(0x0) << 4)
13358 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_VNIC_PG_SIZE_PG_8K \
13359 (UINT32_C(0x1) << 4)
13361 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_VNIC_PG_SIZE_PG_64K \
13362 (UINT32_C(0x2) << 4)
13364 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_VNIC_PG_SIZE_PG_2M \
13365 (UINT32_C(0x3) << 4)
13367 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_VNIC_PG_SIZE_PG_8M \
13368 (UINT32_C(0x4) << 4)
13370 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_VNIC_PG_SIZE_PG_1G \
13371 (UINT32_C(0x5) << 4)
13372 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_VNIC_PG_SIZE_LAST \
13373 HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_VNIC_PG_SIZE_PG_1G
13374 /* Stat page size and level. */
13375 uint8_t stat_pg_size_stat_lvl;
13376 /* Stat PBL indirect levels. */
13377 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_STAT_LVL_MASK \
13379 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_STAT_LVL_SFT 0
13380 /* PBL pointer is physical start address. */
13381 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_STAT_LVL_LVL_0 \
13383 /* PBL pointer points to PTE table. */
13384 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_STAT_LVL_LVL_1 \
13386 /* PBL pointer points to PDE table with each entry pointing to PTE tables. */
13387 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_STAT_LVL_LVL_2 \
13389 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_STAT_LVL_LAST \
13390 HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_STAT_LVL_LVL_2
13391 /* Stat page size. */
13392 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_STAT_PG_SIZE_MASK \
13394 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_STAT_PG_SIZE_SFT 4
13396 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_STAT_PG_SIZE_PG_4K \
13397 (UINT32_C(0x0) << 4)
13399 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_STAT_PG_SIZE_PG_8K \
13400 (UINT32_C(0x1) << 4)
13402 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_STAT_PG_SIZE_PG_64K \
13403 (UINT32_C(0x2) << 4)
13405 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_STAT_PG_SIZE_PG_2M \
13406 (UINT32_C(0x3) << 4)
13408 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_STAT_PG_SIZE_PG_8M \
13409 (UINT32_C(0x4) << 4)
13411 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_STAT_PG_SIZE_PG_1G \
13412 (UINT32_C(0x5) << 4)
13413 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_STAT_PG_SIZE_LAST \
13414 HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_STAT_PG_SIZE_PG_1G
13415 /* TQM slow path page size and level. */
13416 uint8_t tqm_sp_pg_size_tqm_sp_lvl;
13417 /* TQM slow path PBL indirect levels. */
13418 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_SP_LVL_MASK \
13420 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_SP_LVL_SFT 0
13421 /* PBL pointer is physical start address. */
13422 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_SP_LVL_LVL_0 \
13424 /* PBL pointer points to PTE table. */
13425 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_SP_LVL_LVL_1 \
13427 /* PBL pointer points to PDE table with each entry pointing to PTE tables. */
13428 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_SP_LVL_LVL_2 \
13430 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_SP_LVL_LAST \
13431 HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_SP_LVL_LVL_2
13432 /* TQM slow path page size. */
13433 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_SP_PG_SIZE_MASK \
13435 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_SP_PG_SIZE_SFT 4
13437 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_SP_PG_SIZE_PG_4K \
13438 (UINT32_C(0x0) << 4)
13440 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_SP_PG_SIZE_PG_8K \
13441 (UINT32_C(0x1) << 4)
13443 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_SP_PG_SIZE_PG_64K \
13444 (UINT32_C(0x2) << 4)
13446 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_SP_PG_SIZE_PG_2M \
13447 (UINT32_C(0x3) << 4)
13449 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_SP_PG_SIZE_PG_8M \
13450 (UINT32_C(0x4) << 4)
13452 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_SP_PG_SIZE_PG_1G \
13453 (UINT32_C(0x5) << 4)
13454 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_SP_PG_SIZE_LAST \
13455 HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_SP_PG_SIZE_PG_1G
13456 /* TQM ring 0 page size and level. */
13457 uint8_t tqm_ring0_pg_size_tqm_ring0_lvl;
13458 /* TQM ring 0 PBL indirect levels. */
13459 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING0_LVL_MASK \
13461 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING0_LVL_SFT 0
13462 /* PBL pointer is physical start address. */
13463 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING0_LVL_LVL_0 \
13465 /* PBL pointer points to PTE table. */
13466 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING0_LVL_LVL_1 \
13468 /* PBL pointer points to PDE table with each entry pointing to PTE tables. */
13469 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING0_LVL_LVL_2 \
13471 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING0_LVL_LAST \
13472 HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING0_LVL_LVL_2
13473 /* TQM ring 0 page size. */
13474 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING0_PG_SIZE_MASK \
13476 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING0_PG_SIZE_SFT 4
13478 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING0_PG_SIZE_PG_4K \
13479 (UINT32_C(0x0) << 4)
13481 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING0_PG_SIZE_PG_8K \
13482 (UINT32_C(0x1) << 4)
13484 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING0_PG_SIZE_PG_64K \
13485 (UINT32_C(0x2) << 4)
13487 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING0_PG_SIZE_PG_2M \
13488 (UINT32_C(0x3) << 4)
13490 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING0_PG_SIZE_PG_8M \
13491 (UINT32_C(0x4) << 4)
13493 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING0_PG_SIZE_PG_1G \
13494 (UINT32_C(0x5) << 4)
13495 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING0_PG_SIZE_LAST \
13496 HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING0_PG_SIZE_PG_1G
13497 /* TQM ring 1 page size and level. */
13498 uint8_t tqm_ring1_pg_size_tqm_ring1_lvl;
13499 /* TQM ring 1 PBL indirect levels. */
13500 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING1_LVL_MASK \
13502 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING1_LVL_SFT 0
13503 /* PBL pointer is physical start address. */
13504 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING1_LVL_LVL_0 \
13506 /* PBL pointer points to PTE table. */
13507 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING1_LVL_LVL_1 \
13509 /* PBL pointer points to PDE table with each entry pointing to PTE tables. */
13510 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING1_LVL_LVL_2 \
13512 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING1_LVL_LAST \
13513 HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING1_LVL_LVL_2
13514 /* TQM ring 1 page size. */
13515 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING1_PG_SIZE_MASK \
13517 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING1_PG_SIZE_SFT 4
13519 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING1_PG_SIZE_PG_4K \
13520 (UINT32_C(0x0) << 4)
13522 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING1_PG_SIZE_PG_8K \
13523 (UINT32_C(0x1) << 4)
13525 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING1_PG_SIZE_PG_64K \
13526 (UINT32_C(0x2) << 4)
13528 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING1_PG_SIZE_PG_2M \
13529 (UINT32_C(0x3) << 4)
13531 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING1_PG_SIZE_PG_8M \
13532 (UINT32_C(0x4) << 4)
13534 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING1_PG_SIZE_PG_1G \
13535 (UINT32_C(0x5) << 4)
13536 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING1_PG_SIZE_LAST \
13537 HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING1_PG_SIZE_PG_1G
13538 /* TQM ring 2 page size and level. */
13539 uint8_t tqm_ring2_pg_size_tqm_ring2_lvl;
13540 /* TQM ring 2 PBL indirect levels. */
13541 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING2_LVL_MASK \
13543 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING2_LVL_SFT 0
13544 /* PBL pointer is physical start address. */
13545 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING2_LVL_LVL_0 \
13547 /* PBL pointer points to PTE table. */
13548 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING2_LVL_LVL_1 \
13550 /* PBL pointer points to PDE table with each entry pointing to PTE tables. */
13551 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING2_LVL_LVL_2 \
13553 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING2_LVL_LAST \
13554 HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING2_LVL_LVL_2
13555 /* TQM ring 2 page size. */
13556 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING2_PG_SIZE_MASK \
13558 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING2_PG_SIZE_SFT 4
13560 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING2_PG_SIZE_PG_4K \
13561 (UINT32_C(0x0) << 4)
13563 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING2_PG_SIZE_PG_8K \
13564 (UINT32_C(0x1) << 4)
13566 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING2_PG_SIZE_PG_64K \
13567 (UINT32_C(0x2) << 4)
13569 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING2_PG_SIZE_PG_2M \
13570 (UINT32_C(0x3) << 4)
13572 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING2_PG_SIZE_PG_8M \
13573 (UINT32_C(0x4) << 4)
13575 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING2_PG_SIZE_PG_1G \
13576 (UINT32_C(0x5) << 4)
13577 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING2_PG_SIZE_LAST \
13578 HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING2_PG_SIZE_PG_1G
13579 /* TQM ring 3 page size and level. */
13580 uint8_t tqm_ring3_pg_size_tqm_ring3_lvl;
13581 /* TQM ring 3 PBL indirect levels. */
13582 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING3_LVL_MASK \
13584 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING3_LVL_SFT 0
13585 /* PBL pointer is physical start address. */
13586 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING3_LVL_LVL_0 \
13588 /* PBL pointer points to PTE table. */
13589 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING3_LVL_LVL_1 \
13591 /* PBL pointer points to PDE table with each entry pointing to PTE tables. */
13592 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING3_LVL_LVL_2 \
13594 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING3_LVL_LAST \
13595 HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING3_LVL_LVL_2
13596 /* TQM ring 3 page size. */
13597 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING3_PG_SIZE_MASK \
13599 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING3_PG_SIZE_SFT 4
13601 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING3_PG_SIZE_PG_4K \
13602 (UINT32_C(0x0) << 4)
13604 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING3_PG_SIZE_PG_8K \
13605 (UINT32_C(0x1) << 4)
13607 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING3_PG_SIZE_PG_64K \
13608 (UINT32_C(0x2) << 4)
13610 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING3_PG_SIZE_PG_2M \
13611 (UINT32_C(0x3) << 4)
13613 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING3_PG_SIZE_PG_8M \
13614 (UINT32_C(0x4) << 4)
13616 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING3_PG_SIZE_PG_1G \
13617 (UINT32_C(0x5) << 4)
13618 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING3_PG_SIZE_LAST \
13619 HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING3_PG_SIZE_PG_1G
13620 /* TQM ring 4 page size and level. */
13621 uint8_t tqm_ring4_pg_size_tqm_ring4_lvl;
13622 /* TQM ring 4 PBL indirect levels. */
13623 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING4_LVL_MASK \
13625 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING4_LVL_SFT 0
13626 /* PBL pointer is physical start address. */
13627 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING4_LVL_LVL_0 \
13629 /* PBL pointer points to PTE table. */
13630 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING4_LVL_LVL_1 \
13632 /* PBL pointer points to PDE table with each entry pointing to PTE tables. */
13633 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING4_LVL_LVL_2 \
13635 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING4_LVL_LAST \
13636 HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING4_LVL_LVL_2
13637 /* TQM ring 4 page size. */
13638 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING4_PG_SIZE_MASK \
13640 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING4_PG_SIZE_SFT 4
13642 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING4_PG_SIZE_PG_4K \
13643 (UINT32_C(0x0) << 4)
13645 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING4_PG_SIZE_PG_8K \
13646 (UINT32_C(0x1) << 4)
13648 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING4_PG_SIZE_PG_64K \
13649 (UINT32_C(0x2) << 4)
13651 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING4_PG_SIZE_PG_2M \
13652 (UINT32_C(0x3) << 4)
13654 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING4_PG_SIZE_PG_8M \
13655 (UINT32_C(0x4) << 4)
13657 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING4_PG_SIZE_PG_1G \
13658 (UINT32_C(0x5) << 4)
13659 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING4_PG_SIZE_LAST \
13660 HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING4_PG_SIZE_PG_1G
13661 /* TQM ring 5 page size and level. */
13662 uint8_t tqm_ring5_pg_size_tqm_ring5_lvl;
13663 /* TQM ring 5 PBL indirect levels. */
13664 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING5_LVL_MASK \
13666 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING5_LVL_SFT 0
13667 /* PBL pointer is physical start address. */
13668 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING5_LVL_LVL_0 \
13670 /* PBL pointer points to PTE table. */
13671 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING5_LVL_LVL_1 \
13673 /* PBL pointer points to PDE table with each entry pointing to PTE tables. */
13674 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING5_LVL_LVL_2 \
13676 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING5_LVL_LAST \
13677 HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING5_LVL_LVL_2
13678 /* TQM ring 5 page size. */
13679 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING5_PG_SIZE_MASK \
13681 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING5_PG_SIZE_SFT 4
13683 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING5_PG_SIZE_PG_4K \
13684 (UINT32_C(0x0) << 4)
13686 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING5_PG_SIZE_PG_8K \
13687 (UINT32_C(0x1) << 4)
13689 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING5_PG_SIZE_PG_64K \
13690 (UINT32_C(0x2) << 4)
13692 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING5_PG_SIZE_PG_2M \
13693 (UINT32_C(0x3) << 4)
13695 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING5_PG_SIZE_PG_8M \
13696 (UINT32_C(0x4) << 4)
13698 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING5_PG_SIZE_PG_1G \
13699 (UINT32_C(0x5) << 4)
13700 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING5_PG_SIZE_LAST \
13701 HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING5_PG_SIZE_PG_1G
13702 /* TQM ring 6 page size and level. */
13703 uint8_t tqm_ring6_pg_size_tqm_ring6_lvl;
13704 /* TQM ring 6 PBL indirect levels. */
13705 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING6_LVL_MASK \
13707 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING6_LVL_SFT 0
13708 /* PBL pointer is physical start address. */
13709 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING6_LVL_LVL_0 \
13711 /* PBL pointer points to PTE table. */
13712 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING6_LVL_LVL_1 \
13714 /* PBL pointer points to PDE table with each entry pointing to PTE tables. */
13715 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING6_LVL_LVL_2 \
13717 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING6_LVL_LAST \
13718 HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING6_LVL_LVL_2
13719 /* TQM ring 6 page size. */
13720 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING6_PG_SIZE_MASK \
13722 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING6_PG_SIZE_SFT 4
13724 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING6_PG_SIZE_PG_4K \
13725 (UINT32_C(0x0) << 4)
13727 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING6_PG_SIZE_PG_8K \
13728 (UINT32_C(0x1) << 4)
13730 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING6_PG_SIZE_PG_64K \
13731 (UINT32_C(0x2) << 4)
13733 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING6_PG_SIZE_PG_2M \
13734 (UINT32_C(0x3) << 4)
13736 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING6_PG_SIZE_PG_8M \
13737 (UINT32_C(0x4) << 4)
13739 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING6_PG_SIZE_PG_1G \
13740 (UINT32_C(0x5) << 4)
13741 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING6_PG_SIZE_LAST \
13742 HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING6_PG_SIZE_PG_1G
13743 /* TQM ring 7 page size and level. */
13744 uint8_t tqm_ring7_pg_size_tqm_ring7_lvl;
13745 /* TQM ring 7 PBL indirect levels. */
13746 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING7_LVL_MASK \
13748 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING7_LVL_SFT 0
13749 /* PBL pointer is physical start address. */
13750 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING7_LVL_LVL_0 \
13752 /* PBL pointer points to PTE table. */
13753 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING7_LVL_LVL_1 \
13755 /* PBL pointer points to PDE table with each entry pointing to PTE tables. */
13756 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING7_LVL_LVL_2 \
13758 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING7_LVL_LAST \
13759 HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING7_LVL_LVL_2
13760 /* TQM ring 7 page size. */
13761 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING7_PG_SIZE_MASK \
13763 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING7_PG_SIZE_SFT 4
13765 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING7_PG_SIZE_PG_4K \
13766 (UINT32_C(0x0) << 4)
13768 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING7_PG_SIZE_PG_8K \
13769 (UINT32_C(0x1) << 4)
13771 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING7_PG_SIZE_PG_64K \
13772 (UINT32_C(0x2) << 4)
13774 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING7_PG_SIZE_PG_2M \
13775 (UINT32_C(0x3) << 4)
13777 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING7_PG_SIZE_PG_8M \
13778 (UINT32_C(0x4) << 4)
13780 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING7_PG_SIZE_PG_1G \
13781 (UINT32_C(0x5) << 4)
13782 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING7_PG_SIZE_LAST \
13783 HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING7_PG_SIZE_PG_1G
13784 /* MR/AV page size and level. */
13785 uint8_t mrav_pg_size_mrav_lvl;
13786 /* MR/AV PBL indirect levels. */
13787 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_MRAV_LVL_MASK \
13789 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_MRAV_LVL_SFT 0
13790 /* PBL pointer is physical start address. */
13791 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_MRAV_LVL_LVL_0 \
13793 /* PBL pointer points to PTE table. */
13794 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_MRAV_LVL_LVL_1 \
13796 /* PBL pointer points to PDE table with each entry pointing to PTE tables. */
13797 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_MRAV_LVL_LVL_2 \
13799 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_MRAV_LVL_LAST \
13800 HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_MRAV_LVL_LVL_2
13801 /* MR/AV page size. */
13802 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_MRAV_PG_SIZE_MASK \
13804 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_MRAV_PG_SIZE_SFT 4
13806 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_MRAV_PG_SIZE_PG_4K \
13807 (UINT32_C(0x0) << 4)
13809 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_MRAV_PG_SIZE_PG_8K \
13810 (UINT32_C(0x1) << 4)
13812 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_MRAV_PG_SIZE_PG_64K \
13813 (UINT32_C(0x2) << 4)
13815 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_MRAV_PG_SIZE_PG_2M \
13816 (UINT32_C(0x3) << 4)
13818 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_MRAV_PG_SIZE_PG_8M \
13819 (UINT32_C(0x4) << 4)
13821 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_MRAV_PG_SIZE_PG_1G \
13822 (UINT32_C(0x5) << 4)
13823 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_MRAV_PG_SIZE_LAST \
13824 HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_MRAV_PG_SIZE_PG_1G
13825 /* Timer page size and level. */
13826 uint8_t tim_pg_size_tim_lvl;
13827 /* Timer PBL indirect levels. */
13828 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TIM_LVL_MASK \
13830 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TIM_LVL_SFT 0
13831 /* PBL pointer is physical start address. */
13832 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TIM_LVL_LVL_0 \
13834 /* PBL pointer points to PTE table. */
13835 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TIM_LVL_LVL_1 \
13837 /* PBL pointer points to PDE table with each entry pointing to PTE tables. */
13838 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TIM_LVL_LVL_2 \
13840 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TIM_LVL_LAST \
13841 HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TIM_LVL_LVL_2
13842 /* Timer page size. */
13843 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TIM_PG_SIZE_MASK \
13845 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TIM_PG_SIZE_SFT 4
13847 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TIM_PG_SIZE_PG_4K \
13848 (UINT32_C(0x0) << 4)
13850 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TIM_PG_SIZE_PG_8K \
13851 (UINT32_C(0x1) << 4)
13853 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TIM_PG_SIZE_PG_64K \
13854 (UINT32_C(0x2) << 4)
13856 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TIM_PG_SIZE_PG_2M \
13857 (UINT32_C(0x3) << 4)
13859 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TIM_PG_SIZE_PG_8M \
13860 (UINT32_C(0x4) << 4)
13862 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TIM_PG_SIZE_PG_1G \
13863 (UINT32_C(0x5) << 4)
13864 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TIM_PG_SIZE_LAST \
13865 HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TIM_PG_SIZE_PG_1G
13866 /* QP page directory. */
13867 uint64_t qpc_page_dir;
13868 /* SRQ page directory. */
13869 uint64_t srq_page_dir;
13870 /* CQ page directory. */
13871 uint64_t cq_page_dir;
13872 /* VNIC page directory. */
13873 uint64_t vnic_page_dir;
13874 /* Stat page directory. */
13875 uint64_t stat_page_dir;
13876 /* TQM slowpath page directory. */
13877 uint64_t tqm_sp_page_dir;
13878 /* TQM ring 0 page directory. */
13879 uint64_t tqm_ring0_page_dir;
13880 /* TQM ring 1 page directory. */
13881 uint64_t tqm_ring1_page_dir;
13882 /* TQM ring 2 page directory. */
13883 uint64_t tqm_ring2_page_dir;
13884 /* TQM ring 3 page directory. */
13885 uint64_t tqm_ring3_page_dir;
13886 /* TQM ring 4 page directory. */
13887 uint64_t tqm_ring4_page_dir;
13888 /* TQM ring 5 page directory. */
13889 uint64_t tqm_ring5_page_dir;
13890 /* TQM ring 6 page directory. */
13891 uint64_t tqm_ring6_page_dir;
13892 /* TQM ring 7 page directory. */
13893 uint64_t tqm_ring7_page_dir;
13894 /* MR/AV page directory. */
13895 uint64_t mrav_page_dir;
13896 /* Timer page directory. */
13897 uint64_t tim_page_dir;
13898 /* Number of entries to reserve for QP1 */
13899 uint16_t qp_num_qp1_entries;
13900 /* Number of entries to reserve for L2 */
13901 uint16_t qp_num_l2_entries;
13902 /* Number of QPs. */
13903 uint32_t qp_num_entries;
13904 /* Number of SRQs. */
13905 uint32_t srq_num_entries;
13906 /* Number of entries to reserve for L2 */
13907 uint16_t srq_num_l2_entries;
13908 /* Number of entries to reserve for L2 */
13909 uint16_t cq_num_l2_entries;
13910 /* Number of CQs. */
13911 uint32_t cq_num_entries;
13912 /* Number of entries to reserve for VNIC entries */
13913 uint16_t vnic_num_vnic_entries;
13914 /* Number of entries to reserve for Ring table entries */
13915 uint16_t vnic_num_ring_table_entries;
13916 /* Number of Stats. */
13917 uint32_t stat_num_entries;
13918 /* Number of TQM slowpath entries. */
13919 uint32_t tqm_sp_num_entries;
13920 /* Number of TQM ring 0 entries. */
13921 uint32_t tqm_ring0_num_entries;
13922 /* Number of TQM ring 1 entries. */
13923 uint32_t tqm_ring1_num_entries;
13924 /* Number of TQM ring 2 entries. */
13925 uint32_t tqm_ring2_num_entries;
13926 /* Number of TQM ring 3 entries. */
13927 uint32_t tqm_ring3_num_entries;
13928 /* Number of TQM ring 4 entries. */
13929 uint32_t tqm_ring4_num_entries;
13930 /* Number of TQM ring 5 entries. */
13931 uint32_t tqm_ring5_num_entries;
13932 /* Number of TQM ring 6 entries. */
13933 uint32_t tqm_ring6_num_entries;
13934 /* Number of TQM ring 7 entries. */
13935 uint32_t tqm_ring7_num_entries;
13937 * If the MR/AV split reservation flag is not set, then this field
13938 * represents the total number of MR plus AV entries. For versions
13939 * of firmware that support the split reservation, when it is not
13940 * specified half of the entries will be reserved for MRs and the
13941 * other half for AVs.
13943 * If the MR/AV split reservation flag is set, then this
13944 * field is logically divided into two 16b fields. Bits `[31:16]`
13945 * represents the `mr_num_entries` and bits `[15:0]` represents
13946 * `av_num_entries`. The granularity of these values is defined by
13947 * the `mrav_num_entries_unit` field returned by the
13948 * `backing_store_qcaps` command.
13950 uint32_t mrav_num_entries;
13951 /* Number of Timer entries. */
13952 uint32_t tim_num_entries;
13953 uint8_t unused_1[7];
13955 * This field is used in Output records to indicate that the output
13956 * is completely written to RAM. This field should be read as 1
13957 * to indicate that the output has been completely written.
13958 * When writing a command completion or response to an internal
13959 * processor, the order of writes has to be such that this field
13965 /****************************
13966 * hwrm_error_recovery_qcfg *
13967 ****************************/
13970 /* hwrm_error_recovery_qcfg_input (size:192b/24B) */
13971 struct hwrm_error_recovery_qcfg_input {
13972 /* The HWRM command request type. */
13975 * The completion ring to send the completion event on. This should
13976 * be the NQ ID returned from the `nq_alloc` HWRM command.
13978 uint16_t cmpl_ring;
13980 * The sequence ID is used by the driver for tracking multiple
13981 * commands. This ID is treated as opaque data by the firmware and
13982 * the value is returned in the `hwrm_resp_hdr` upon completion.
13986 * The target ID of the command:
13987 * * 0x0-0xFFF8 - The function ID
13988 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
13989 * * 0xFFFD - Reserved for user-space HWRM interface
13992 uint16_t target_id;
13994 * A physical address pointer pointing to a host buffer that the
13995 * command's response data will be written. This can be either a host
13996 * physical address (HPA) or a guest physical address (GPA) and must
13997 * point to a physically contiguous block of memory.
13999 uint64_t resp_addr;
14000 uint8_t unused_0[8];
14003 /* hwrm_error_recovery_qcfg_output (size:1664b/208B) */
14004 struct hwrm_error_recovery_qcfg_output {
14005 /* The specific error status for the command. */
14006 uint16_t error_code;
14007 /* The HWRM command request type. */
14009 /* The sequence ID from the original command. */
14011 /* The length of the response data in number of bytes. */
14015 * When this flag is set to 1, error recovery will be initiated
14016 * through master function driver.
14018 #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FLAGS_HOST UINT32_C(0x1)
14020 * When this flag is set to 1, error recovery will be performed
14021 * through Co processor.
14023 #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FLAGS_CO_CPU UINT32_C(0x2)
14025 * Driver Polling frequency. This value is in units of 100msec.
14026 * Typical value would be 10 to indicate 1sec.
14027 * Drivers can poll FW health status, Heartbeat, reset_counter with
14030 uint32_t driver_polling_freq;
14032 * This value is in units of 100msec.
14033 * Typical value would be 30 to indicate 3sec.
14034 * Master function wait period from detecting a fatal error to
14035 * initiating reset. In this time period Master PF expects every
14036 * active driver will detect fatal error.
14038 uint32_t master_func_wait_period;
14040 * This value is in units of 100msec.
14041 * Typical value would be 50 to indicate 5sec.
14042 * Normal function wait period from fatal error detection to
14043 * polling FW health status. In this time period, drivers should not
14044 * do any PCIe MMIO transaction and should not send any HWRM commands.
14046 uint32_t normal_func_wait_period;
14048 * This value is in units of 100msec.
14049 * Typical value would be 20 to indicate 2sec.
14050 * This field indicates that, master function wait period after chip
14051 * reset. After this time, master function should reinitialize with
14054 uint32_t master_func_wait_period_after_reset;
14056 * This value is in units of 100msec.
14057 * Typical value would be 60 to indicate 6sec.
14058 * This field is applicable to both master and normal functions.
14059 * Even after chip reset, if FW status not changed to ready,
14060 * then all the functions can poll for this much time and bailout.
14062 uint32_t max_bailout_time_after_reset;
14064 * FW health status register.
14065 * Lower 2 bits indicates address space location and upper 30 bits
14066 * indicates upper 30bits of the register address.
14067 * A value of 0xFFFF-FFFF indicates this register does not exist.
14069 uint32_t fw_health_status_reg;
14070 /* Lower 2 bits indicates address space location. */
14071 #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FW_HEALTH_STATUS_REG_ADDR_SPACE_MASK \
14073 #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FW_HEALTH_STATUS_REG_ADDR_SPACE_SFT \
14076 * If value is 0, this register is located in PCIe config space.
14077 * Drivers have to map appropriate window to access this
14080 #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FW_HEALTH_STATUS_REG_ADDR_SPACE_PCIE_CFG \
14083 * If value is 1, this register is located in GRC address space.
14084 * Drivers have to map appropriate window to access this
14087 #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FW_HEALTH_STATUS_REG_ADDR_SPACE_GRC \
14090 * If value is 2, this register is located in first BAR address
14091 * space. Drivers have to map appropriate window to access this
14094 #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FW_HEALTH_STATUS_REG_ADDR_SPACE_BAR0 \
14097 * If value is 3, this register is located in second BAR address
14098 * space. Drivers have to map appropriate window to access this
14099 * Drivers have to map appropriate window to access this
14102 #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FW_HEALTH_STATUS_REG_ADDR_SPACE_BAR1 \
14104 #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FW_HEALTH_STATUS_REG_ADDR_SPACE_LAST \
14105 HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FW_HEALTH_STATUS_REG_ADDR_SPACE_BAR1
14106 /* Upper 30bits of the register address. */
14107 #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FW_HEALTH_STATUS_REG_ADDR_MASK \
14108 UINT32_C(0xfffffffc)
14109 #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FW_HEALTH_STATUS_REG_ADDR_SFT \
14112 * FW HeartBeat register.
14113 * Lower 2 bits indicates address space location and upper 30 bits
14114 * indicates actual address.
14115 * A value of 0xFFFF-FFFF indicates this register does not exist.
14117 uint32_t fw_heartbeat_reg;
14118 /* Lower 2 bits indicates address space location. */
14119 #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FW_HEARTBEAT_REG_ADDR_SPACE_MASK \
14121 #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FW_HEARTBEAT_REG_ADDR_SPACE_SFT \
14124 * If value is 0, this register is located in PCIe config space.
14125 * Drivers have to map appropriate window to access this
14128 #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FW_HEARTBEAT_REG_ADDR_SPACE_PCIE_CFG \
14131 * If value is 1, this register is located in GRC address space.
14132 * Drivers have to map appropriate window to access this
14135 #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FW_HEARTBEAT_REG_ADDR_SPACE_GRC \
14138 * If value is 2, this register is located in first BAR address
14139 * space. Drivers have to map appropriate window to access this
14142 #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FW_HEARTBEAT_REG_ADDR_SPACE_BAR0 \
14145 * If value is 3, this register is located in second BAR address
14146 * space. Drivers have to map appropriate window to access this
14149 #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FW_HEARTBEAT_REG_ADDR_SPACE_BAR1 \
14151 #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FW_HEARTBEAT_REG_ADDR_SPACE_LAST \
14152 HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FW_HEARTBEAT_REG_ADDR_SPACE_BAR1
14153 /* Upper 30bits of the register address. */
14154 #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FW_HEARTBEAT_REG_ADDR_MASK \
14155 UINT32_C(0xfffffffc)
14156 #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FW_HEARTBEAT_REG_ADDR_SFT \
14159 * FW reset counter.
14160 * Lower 2 bits indicates address space location and upper 30 bits
14161 * indicates actual address.
14162 * A value of 0xFFFF-FFFF indicates this register does not exist.
14164 uint32_t fw_reset_cnt_reg;
14165 /* Lower 2 bits indicates address space location. */
14166 #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FW_RESET_CNT_REG_ADDR_SPACE_MASK \
14168 #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FW_RESET_CNT_REG_ADDR_SPACE_SFT \
14171 * If value is 0, this register is located in PCIe config space.
14172 * Drivers have to map appropriate window to access this
14175 #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FW_RESET_CNT_REG_ADDR_SPACE_PCIE_CFG \
14178 * If value is 1, this register is located in GRC address space.
14179 * Drivers have to map appropriate window to access this
14182 #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FW_RESET_CNT_REG_ADDR_SPACE_GRC \
14185 * If value is 2, this register is located in first BAR address
14186 * space. Drivers have to map appropriate window to access this
14189 #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FW_RESET_CNT_REG_ADDR_SPACE_BAR0 \
14192 * If value is 3, this register is located in second BAR address
14193 * space. Drivers have to map appropriate window to access this
14196 #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FW_RESET_CNT_REG_ADDR_SPACE_BAR1 \
14198 #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FW_RESET_CNT_REG_ADDR_SPACE_LAST \
14199 HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FW_RESET_CNT_REG_ADDR_SPACE_BAR1
14200 /* Upper 30bits of the register address. */
14201 #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FW_RESET_CNT_REG_ADDR_MASK \
14202 UINT32_C(0xfffffffc)
14203 #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FW_RESET_CNT_REG_ADDR_SFT \
14206 * Reset Inprogress Register address for PFs.
14207 * Lower 2 bits indicates address space location and upper 30 bits
14208 * indicates actual address.
14209 * A value of 0xFFFF-FFFF indicates this register does not exist.
14211 uint32_t reset_inprogress_reg;
14212 /* Lower 2 bits indicates address space location. */
14213 #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_RESET_INPROGRESS_REG_ADDR_SPACE_MASK \
14215 #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_RESET_INPROGRESS_REG_ADDR_SPACE_SFT \
14218 * If value is 0, this register is located in PCIe config space.
14219 * Drivers have to map appropriate window to access this
14222 #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_RESET_INPROGRESS_REG_ADDR_SPACE_PCIE_CFG \
14225 * If value is 1, this register is located in GRC address space.
14226 * Drivers have to map appropriate window to access this
14229 #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_RESET_INPROGRESS_REG_ADDR_SPACE_GRC \
14232 * If value is 2, this register is located in first BAR address
14233 * space. Drivers have to map appropriate window to access this
14236 #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_RESET_INPROGRESS_REG_ADDR_SPACE_BAR0 \
14239 * If value is 3, this register is located in second BAR address
14240 * space. Drivers have to map appropriate window to access this
14243 #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_RESET_INPROGRESS_REG_ADDR_SPACE_BAR1 \
14245 #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_RESET_INPROGRESS_REG_ADDR_SPACE_LAST \
14246 HWRM_ERROR_RECOVERY_QCFG_OUTPUT_RESET_INPROGRESS_REG_ADDR_SPACE_BAR1
14247 /* Upper 30bits of the register address. */
14248 #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_RESET_INPROGRESS_REG_ADDR_MASK \
14249 UINT32_C(0xfffffffc)
14250 #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_RESET_INPROGRESS_REG_ADDR_SFT \
14252 /* This field indicates the mask value for reset_inprogress_reg. */
14253 uint32_t reset_inprogress_reg_mask;
14254 uint8_t unused_0[3];
14256 * Array of registers and value count to reset the Chip
14257 * Each array count has reset_reg, reset_reg_val, delay_after_reset
14258 * in TLV format. Depending upon Chip type, number of reset registers
14259 * will vary. Drivers have to write reset_reg_val in the reset_reg
14260 * location in the same sequence in order to recover from a fatal
14263 uint8_t reg_array_cnt;
14266 * Lower 2 bits indicates address space location and upper 30 bits
14267 * indicates actual address.
14268 * A value of 0xFFFF-FFFF indicates this register does not exist.
14270 uint32_t reset_reg[16];
14271 /* Lower 2 bits indicates address space location. */
14272 #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_RESET_REG_ADDR_SPACE_MASK \
14274 #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_RESET_REG_ADDR_SPACE_SFT 0
14276 * If value is 0, this register is located in PCIe config space.
14277 * Drivers have to map appropriate window to access this
14280 #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_RESET_REG_ADDR_SPACE_PCIE_CFG \
14283 * If value is 1, this register is located in GRC address space.
14284 * Drivers have to map appropriate window to access this
14287 #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_RESET_REG_ADDR_SPACE_GRC \
14290 * If value is 2, this register is located in first BAR address
14291 * space. Drivers have to map appropriate window to access this
14294 #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_RESET_REG_ADDR_SPACE_BAR0 \
14297 * If value is 3, this register is located in second BAR address
14298 * space. Drivers have to map appropriate window to access this
14301 #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_RESET_REG_ADDR_SPACE_BAR1 \
14303 #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_RESET_REG_ADDR_SPACE_LAST \
14304 HWRM_ERROR_RECOVERY_QCFG_OUTPUT_RESET_REG_ADDR_SPACE_BAR1
14305 /* Upper 30bits of the register address. */
14306 #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_RESET_REG_ADDR_MASK \
14307 UINT32_C(0xfffffffc)
14308 #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_RESET_REG_ADDR_SFT 2
14309 /* Value to be written in reset_reg to reset the controller. */
14310 uint32_t reset_reg_val[16];
14312 * This value is in units of 1msec.
14313 * Typical value would be 10 to indicate 10msec.
14314 * Some of the operations like Core reset require delay before
14315 * accessing PCIE MMIO register space.
14316 * If this value is non-zero, drivers have to wait for
14317 * this much time after writing reset_reg_val in reset_reg.
14319 uint8_t delay_after_reset[16];
14321 * Error recovery counter.
14322 * Lower 2 bits indicates address space location and upper 30 bits
14323 * indicates actual address.
14324 * A value of 0xFFFF-FFFF indicates this register does not exist.
14326 uint32_t err_recovery_cnt_reg;
14327 /* Lower 2 bits indicates address space location. */
14328 #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_ERR_RECOVERY_CNT_REG_ADDR_SPACE_MASK \
14330 #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_ERR_RECOVERY_CNT_REG_ADDR_SPACE_SFT \
14333 * If value is 0, this register is located in PCIe config space.
14334 * Drivers have to map appropriate window to access this
14337 #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_ERR_RECOVERY_CNT_REG_ADDR_SPACE_PCIE_CFG \
14340 * If value is 1, this register is located in GRC address space.
14341 * Drivers have to map appropriate window to access this
14344 #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_ERR_RECOVERY_CNT_REG_ADDR_SPACE_GRC \
14347 * If value is 2, this register is located in first BAR address
14348 * space. Drivers have to map appropriate window to access this
14351 #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_ERR_RECOVERY_CNT_REG_ADDR_SPACE_BAR0 \
14354 * If value is 3, this register is located in second BAR address
14355 * space. Drivers have to map appropriate window to access this
14358 #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_ERR_RECOVERY_CNT_REG_ADDR_SPACE_BAR1 \
14360 #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_ERR_RECOVERY_CNT_REG_ADDR_SPACE_LAST \
14361 HWRM_ERROR_RECOVERY_QCFG_OUTPUT_ERR_RECOVERY_CNT_REG_ADDR_SPACE_BAR1
14362 /* Upper 30bits of the register address. */
14363 #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_ERR_RECOVERY_CNT_REG_ADDR_MASK \
14364 UINT32_C(0xfffffffc)
14365 #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_ERR_RECOVERY_CNT_REG_ADDR_SFT \
14367 uint8_t unused_1[3];
14369 * This field is used in Output records to indicate that the output
14370 * is completely written to RAM. This field should be read as '1'
14371 * to indicate that the output has been completely written.
14372 * When writing a command completion or response to an internal
14373 * processor, the order of writes has to be such that this field
14379 /***********************
14380 * hwrm_func_vlan_qcfg *
14381 ***********************/
14384 /* hwrm_func_vlan_qcfg_input (size:192b/24B) */
14385 struct hwrm_func_vlan_qcfg_input {
14386 /* The HWRM command request type. */
14389 * The completion ring to send the completion event on. This should
14390 * be the NQ ID returned from the `nq_alloc` HWRM command.
14392 uint16_t cmpl_ring;
14394 * The sequence ID is used by the driver for tracking multiple
14395 * commands. This ID is treated as opaque data by the firmware and
14396 * the value is returned in the `hwrm_resp_hdr` upon completion.
14400 * The target ID of the command:
14401 * * 0x0-0xFFF8 - The function ID
14402 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
14403 * * 0xFFFD - Reserved for user-space HWRM interface
14406 uint16_t target_id;
14408 * A physical address pointer pointing to a host buffer that the
14409 * command's response data will be written. This can be either a host
14410 * physical address (HPA) or a guest physical address (GPA) and must
14411 * point to a physically contiguous block of memory.
14413 uint64_t resp_addr;
14415 * Function ID of the function that is being
14417 * If set to 0xFF... (All Fs), then the configuration is
14418 * for the requesting function.
14421 uint8_t unused_0[6];
14424 /* hwrm_func_vlan_qcfg_output (size:320b/40B) */
14425 struct hwrm_func_vlan_qcfg_output {
14426 /* The specific error status for the command. */
14427 uint16_t error_code;
14428 /* The HWRM command request type. */
14430 /* The sequence ID from the original command. */
14432 /* The length of the response data in number of bytes. */
14435 /* S-TAG VLAN identifier configured for the function. */
14437 /* S-TAG PCP value configured for the function. */
14441 * S-TAG TPID value configured for the function. This field is specified in
14442 * network byte order.
14444 uint16_t stag_tpid;
14445 /* C-TAG VLAN identifier configured for the function. */
14447 /* C-TAG PCP value configured for the function. */
14451 * C-TAG TPID value configured for the function. This field is specified in
14452 * network byte order.
14454 uint16_t ctag_tpid;
14459 uint8_t unused_3[3];
14461 * This field is used in Output records to indicate that the output
14462 * is completely written to RAM. This field should be read as '1'
14463 * to indicate that the output has been completely written.
14464 * When writing a command completion or response to an internal processor,
14465 * the order of writes has to be such that this field is written last.
14470 /**********************
14471 * hwrm_func_vlan_cfg *
14472 **********************/
14475 /* hwrm_func_vlan_cfg_input (size:384b/48B) */
14476 struct hwrm_func_vlan_cfg_input {
14477 /* The HWRM command request type. */
14480 * The completion ring to send the completion event on. This should
14481 * be the NQ ID returned from the `nq_alloc` HWRM command.
14483 uint16_t cmpl_ring;
14485 * The sequence ID is used by the driver for tracking multiple
14486 * commands. This ID is treated as opaque data by the firmware and
14487 * the value is returned in the `hwrm_resp_hdr` upon completion.
14491 * The target ID of the command:
14492 * * 0x0-0xFFF8 - The function ID
14493 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
14494 * * 0xFFFD - Reserved for user-space HWRM interface
14497 uint16_t target_id;
14499 * A physical address pointer pointing to a host buffer that the
14500 * command's response data will be written. This can be either a host
14501 * physical address (HPA) or a guest physical address (GPA) and must
14502 * point to a physically contiguous block of memory.
14504 uint64_t resp_addr;
14506 * Function ID of the function that is being
14508 * If set to 0xFF... (All Fs), then the configuration is
14509 * for the requesting function.
14512 uint8_t unused_0[2];
14515 * This bit must be '1' for the stag_vid field to be
14518 #define HWRM_FUNC_VLAN_CFG_INPUT_ENABLES_STAG_VID UINT32_C(0x1)
14520 * This bit must be '1' for the ctag_vid field to be
14523 #define HWRM_FUNC_VLAN_CFG_INPUT_ENABLES_CTAG_VID UINT32_C(0x2)
14525 * This bit must be '1' for the stag_pcp field to be
14528 #define HWRM_FUNC_VLAN_CFG_INPUT_ENABLES_STAG_PCP UINT32_C(0x4)
14530 * This bit must be '1' for the ctag_pcp field to be
14533 #define HWRM_FUNC_VLAN_CFG_INPUT_ENABLES_CTAG_PCP UINT32_C(0x8)
14535 * This bit must be '1' for the stag_tpid field to be
14538 #define HWRM_FUNC_VLAN_CFG_INPUT_ENABLES_STAG_TPID UINT32_C(0x10)
14540 * This bit must be '1' for the ctag_tpid field to be
14543 #define HWRM_FUNC_VLAN_CFG_INPUT_ENABLES_CTAG_TPID UINT32_C(0x20)
14544 /* S-TAG VLAN identifier configured for the function. */
14546 /* S-TAG PCP value configured for the function. */
14550 * S-TAG TPID value configured for the function. This field is specified in
14551 * network byte order.
14553 uint16_t stag_tpid;
14554 /* C-TAG VLAN identifier configured for the function. */
14556 /* C-TAG PCP value configured for the function. */
14560 * C-TAG TPID value configured for the function. This field is specified in
14561 * network byte order.
14563 uint16_t ctag_tpid;
14568 uint8_t unused_3[4];
14571 /* hwrm_func_vlan_cfg_output (size:128b/16B) */
14572 struct hwrm_func_vlan_cfg_output {
14573 /* The specific error status for the command. */
14574 uint16_t error_code;
14575 /* The HWRM command request type. */
14577 /* The sequence ID from the original command. */
14579 /* The length of the response data in number of bytes. */
14581 uint8_t unused_0[7];
14583 * This field is used in Output records to indicate that the output
14584 * is completely written to RAM. This field should be read as '1'
14585 * to indicate that the output has been completely written.
14586 * When writing a command completion or response to an internal processor,
14587 * the order of writes has to be such that this field is written last.
14592 /*******************************
14593 * hwrm_func_vf_vnic_ids_query *
14594 *******************************/
14597 /* hwrm_func_vf_vnic_ids_query_input (size:256b/32B) */
14598 struct hwrm_func_vf_vnic_ids_query_input {
14599 /* The HWRM command request type. */
14602 * The completion ring to send the completion event on. This should
14603 * be the NQ ID returned from the `nq_alloc` HWRM command.
14605 uint16_t cmpl_ring;
14607 * The sequence ID is used by the driver for tracking multiple
14608 * commands. This ID is treated as opaque data by the firmware and
14609 * the value is returned in the `hwrm_resp_hdr` upon completion.
14613 * The target ID of the command:
14614 * * 0x0-0xFFF8 - The function ID
14615 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
14616 * * 0xFFFD - Reserved for user-space HWRM interface
14619 uint16_t target_id;
14621 * A physical address pointer pointing to a host buffer that the
14622 * command's response data will be written. This can be either a host
14623 * physical address (HPA) or a guest physical address (GPA) and must
14624 * point to a physically contiguous block of memory.
14626 uint64_t resp_addr;
14628 * This value is used to identify a Virtual Function (VF).
14629 * The scope of VF ID is local within a PF.
14632 uint8_t unused_0[2];
14633 /* Max number of vnic ids in vnic id table */
14634 uint32_t max_vnic_id_cnt;
14635 /* This is the address for VF VNIC ID table */
14636 uint64_t vnic_id_tbl_addr;
14639 /* hwrm_func_vf_vnic_ids_query_output (size:128b/16B) */
14640 struct hwrm_func_vf_vnic_ids_query_output {
14641 /* The specific error status for the command. */
14642 uint16_t error_code;
14643 /* The HWRM command request type. */
14645 /* The sequence ID from the original command. */
14647 /* The length of the response data in number of bytes. */
14650 * Actual number of vnic ids
14652 * Each VNIC ID is written as a 32-bit number.
14654 uint32_t vnic_id_cnt;
14655 uint8_t unused_0[3];
14657 * This field is used in Output records to indicate that the output
14658 * is completely written to RAM. This field should be read as '1'
14659 * to indicate that the output has been completely written.
14660 * When writing a command completion or response to an internal processor,
14661 * the order of writes has to be such that this field is written last.
14666 /***********************
14667 * hwrm_func_vf_bw_cfg *
14668 ***********************/
14671 /* hwrm_func_vf_bw_cfg_input (size:960b/120B) */
14672 struct hwrm_func_vf_bw_cfg_input {
14673 /* The HWRM command request type. */
14676 * The completion ring to send the completion event on. This should
14677 * be the NQ ID returned from the `nq_alloc` HWRM command.
14679 uint16_t cmpl_ring;
14681 * The sequence ID is used by the driver for tracking multiple
14682 * commands. This ID is treated as opaque data by the firmware and
14683 * the value is returned in the `hwrm_resp_hdr` upon completion.
14687 * The target ID of the command:
14688 * * 0x0-0xFFF8 - The function ID
14689 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
14690 * * 0xFFFD - Reserved for user-space HWRM interface
14693 uint16_t target_id;
14695 * A physical address pointer pointing to a host buffer that the
14696 * command's response data will be written. This can be either a host
14697 * physical address (HPA) or a guest physical address (GPA) and must
14698 * point to a physically contiguous block of memory.
14700 uint64_t resp_addr;
14702 * The number of VF functions that are being configured.
14703 * The cmd space allows up to 50 VFs' BW to be configured with one cmd.
14706 uint16_t unused[3];
14707 /* These 16-bit fields contain the VF fid and the rate scale percentage. */
14709 /* The physical VF id the adjustment will be made to. */
14710 #define HWRM_FUNC_VF_BW_CFG_INPUT_VFN_VFID_MASK UINT32_C(0xfff)
14711 #define HWRM_FUNC_VF_BW_CFG_INPUT_VFN_VFID_SFT 0
14713 * This field configures the rate scale percentage of the VF as specified
14714 * by the physical VF id.
14716 #define HWRM_FUNC_VF_BW_CFG_INPUT_VFN_RATE_MASK UINT32_C(0xf000)
14717 #define HWRM_FUNC_VF_BW_CFG_INPUT_VFN_RATE_SFT 12
14718 /* 0% of the max tx rate */
14719 #define HWRM_FUNC_VF_BW_CFG_INPUT_VFN_RATE_PCT_0 \
14720 (UINT32_C(0x0) << 12)
14721 /* 6.66% of the max tx rate */
14722 #define HWRM_FUNC_VF_BW_CFG_INPUT_VFN_RATE_PCT_6_66 \
14723 (UINT32_C(0x1) << 12)
14724 /* 13.33% of the max tx rate */
14725 #define HWRM_FUNC_VF_BW_CFG_INPUT_VFN_RATE_PCT_13_33 \
14726 (UINT32_C(0x2) << 12)
14727 /* 20% of the max tx rate */
14728 #define HWRM_FUNC_VF_BW_CFG_INPUT_VFN_RATE_PCT_20 \
14729 (UINT32_C(0x3) << 12)
14730 /* 26.66% of the max tx rate */
14731 #define HWRM_FUNC_VF_BW_CFG_INPUT_VFN_RATE_PCT_26_66 \
14732 (UINT32_C(0x4) << 12)
14733 /* 33% of the max tx rate */
14734 #define HWRM_FUNC_VF_BW_CFG_INPUT_VFN_RATE_PCT_33_33 \
14735 (UINT32_C(0x5) << 12)
14736 /* 40% of the max tx rate */
14737 #define HWRM_FUNC_VF_BW_CFG_INPUT_VFN_RATE_PCT_40 \
14738 (UINT32_C(0x6) << 12)
14739 /* 46.66% of the max tx rate */
14740 #define HWRM_FUNC_VF_BW_CFG_INPUT_VFN_RATE_PCT_46_66 \
14741 (UINT32_C(0x7) << 12)
14742 /* 53.33% of the max tx rate */
14743 #define HWRM_FUNC_VF_BW_CFG_INPUT_VFN_RATE_PCT_53_33 \
14744 (UINT32_C(0x8) << 12)
14745 /* 60% of the max tx rate */
14746 #define HWRM_FUNC_VF_BW_CFG_INPUT_VFN_RATE_PCT_60 \
14747 (UINT32_C(0x9) << 12)
14748 /* 66.66% of the max tx rate */
14749 #define HWRM_FUNC_VF_BW_CFG_INPUT_VFN_RATE_PCT_66_66 \
14750 (UINT32_C(0xa) << 12)
14751 /* 53.33% of the max tx rate */
14752 #define HWRM_FUNC_VF_BW_CFG_INPUT_VFN_RATE_PCT_73_33 \
14753 (UINT32_C(0xb) << 12)
14754 /* 80% of the max tx rate */
14755 #define HWRM_FUNC_VF_BW_CFG_INPUT_VFN_RATE_PCT_80 \
14756 (UINT32_C(0xc) << 12)
14757 /* 86.66% of the max tx rate */
14758 #define HWRM_FUNC_VF_BW_CFG_INPUT_VFN_RATE_PCT_86_66 \
14759 (UINT32_C(0xd) << 12)
14760 /* 93.33% of the max tx rate */
14761 #define HWRM_FUNC_VF_BW_CFG_INPUT_VFN_RATE_PCT_93_33 \
14762 (UINT32_C(0xe) << 12)
14763 /* 100% of the max tx rate */
14764 #define HWRM_FUNC_VF_BW_CFG_INPUT_VFN_RATE_PCT_100 \
14765 (UINT32_C(0xf) << 12)
14766 #define HWRM_FUNC_VF_BW_CFG_INPUT_VFN_RATE_LAST \
14767 HWRM_FUNC_VF_BW_CFG_INPUT_VFN_RATE_PCT_100
14770 /* hwrm_func_vf_bw_cfg_output (size:128b/16B) */
14771 struct hwrm_func_vf_bw_cfg_output {
14772 /* The specific error status for the command. */
14773 uint16_t error_code;
14774 /* The HWRM command request type. */
14776 /* The sequence ID from the original command. */
14778 /* The length of the response data in number of bytes. */
14780 uint8_t unused_0[7];
14782 * This field is used in Output records to indicate that the output
14783 * is completely written to RAM. This field should be read as '1'
14784 * to indicate that the output has been completely written.
14785 * When writing a command completion or response to an internal processor,
14786 * the order of writes has to be such that this field is written last.
14791 /************************
14792 * hwrm_func_vf_bw_qcfg *
14793 ************************/
14796 /* hwrm_func_vf_bw_qcfg_input (size:960b/120B) */
14797 struct hwrm_func_vf_bw_qcfg_input {
14798 /* The HWRM command request type. */
14801 * The completion ring to send the completion event on. This should
14802 * be the NQ ID returned from the `nq_alloc` HWRM command.
14804 uint16_t cmpl_ring;
14806 * The sequence ID is used by the driver for tracking multiple
14807 * commands. This ID is treated as opaque data by the firmware and
14808 * the value is returned in the `hwrm_resp_hdr` upon completion.
14812 * The target ID of the command:
14813 * * 0x0-0xFFF8 - The function ID
14814 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
14815 * * 0xFFFD - Reserved for user-space HWRM interface
14818 uint16_t target_id;
14820 * A physical address pointer pointing to a host buffer that the
14821 * command's response data will be written. This can be either a host
14822 * physical address (HPA) or a guest physical address (GPA) and must
14823 * point to a physically contiguous block of memory.
14825 uint64_t resp_addr;
14827 * The number of VF functions that are being queried.
14828 * The inline response space allows the host to query up to 50 VFs'
14829 * rate scale percentage
14832 uint16_t unused[3];
14833 /* These 16-bit fields contain the VF fid */
14835 /* The physical VF id of interest */
14836 #define HWRM_FUNC_VF_BW_QCFG_INPUT_VFN_VFID_MASK UINT32_C(0xfff)
14837 #define HWRM_FUNC_VF_BW_QCFG_INPUT_VFN_VFID_SFT 0
14840 /* hwrm_func_vf_bw_qcfg_output (size:960b/120B) */
14841 struct hwrm_func_vf_bw_qcfg_output {
14842 /* The specific error status for the command. */
14843 uint16_t error_code;
14844 /* The HWRM command request type. */
14846 /* The sequence ID from the original command. */
14848 /* The length of the response data in number of bytes. */
14851 * The number of VF functions that are being queried.
14852 * The inline response space allows the host to query up to 50 VFs' rate
14856 uint16_t unused[3];
14857 /* These 16-bit fields contain the VF fid and the rate scale percentage. */
14859 /* The physical VF id the adjustment will be made to. */
14860 #define HWRM_FUNC_VF_BW_QCFG_OUTPUT_VFN_VFID_MASK UINT32_C(0xfff)
14861 #define HWRM_FUNC_VF_BW_QCFG_OUTPUT_VFN_VFID_SFT 0
14863 * This field configures the rate scale percentage of the VF as specified
14864 * by the physical VF id.
14866 #define HWRM_FUNC_VF_BW_QCFG_OUTPUT_VFN_RATE_MASK UINT32_C(0xf000)
14867 #define HWRM_FUNC_VF_BW_QCFG_OUTPUT_VFN_RATE_SFT 12
14868 /* 0% of the max tx rate */
14869 #define HWRM_FUNC_VF_BW_QCFG_OUTPUT_VFN_RATE_PCT_0 \
14870 (UINT32_C(0x0) << 12)
14871 /* 6.66% of the max tx rate */
14872 #define HWRM_FUNC_VF_BW_QCFG_OUTPUT_VFN_RATE_PCT_6_66 \
14873 (UINT32_C(0x1) << 12)
14874 /* 13.33% of the max tx rate */
14875 #define HWRM_FUNC_VF_BW_QCFG_OUTPUT_VFN_RATE_PCT_13_33 \
14876 (UINT32_C(0x2) << 12)
14877 /* 20% of the max tx rate */
14878 #define HWRM_FUNC_VF_BW_QCFG_OUTPUT_VFN_RATE_PCT_20 \
14879 (UINT32_C(0x3) << 12)
14880 /* 26.66% of the max tx rate */
14881 #define HWRM_FUNC_VF_BW_QCFG_OUTPUT_VFN_RATE_PCT_26_66 \
14882 (UINT32_C(0x4) << 12)
14883 /* 33% of the max tx rate */
14884 #define HWRM_FUNC_VF_BW_QCFG_OUTPUT_VFN_RATE_PCT_33_33 \
14885 (UINT32_C(0x5) << 12)
14886 /* 40% of the max tx rate */
14887 #define HWRM_FUNC_VF_BW_QCFG_OUTPUT_VFN_RATE_PCT_40 \
14888 (UINT32_C(0x6) << 12)
14889 /* 46.66% of the max tx rate */
14890 #define HWRM_FUNC_VF_BW_QCFG_OUTPUT_VFN_RATE_PCT_46_66 \
14891 (UINT32_C(0x7) << 12)
14892 /* 53.33% of the max tx rate */
14893 #define HWRM_FUNC_VF_BW_QCFG_OUTPUT_VFN_RATE_PCT_53_33 \
14894 (UINT32_C(0x8) << 12)
14895 /* 60% of the max tx rate */
14896 #define HWRM_FUNC_VF_BW_QCFG_OUTPUT_VFN_RATE_PCT_60 \
14897 (UINT32_C(0x9) << 12)
14898 /* 66.66% of the max tx rate */
14899 #define HWRM_FUNC_VF_BW_QCFG_OUTPUT_VFN_RATE_PCT_66_66 \
14900 (UINT32_C(0xa) << 12)
14901 /* 53.33% of the max tx rate */
14902 #define HWRM_FUNC_VF_BW_QCFG_OUTPUT_VFN_RATE_PCT_73_33 \
14903 (UINT32_C(0xb) << 12)
14904 /* 80% of the max tx rate */
14905 #define HWRM_FUNC_VF_BW_QCFG_OUTPUT_VFN_RATE_PCT_80 \
14906 (UINT32_C(0xc) << 12)
14907 /* 86.66% of the max tx rate */
14908 #define HWRM_FUNC_VF_BW_QCFG_OUTPUT_VFN_RATE_PCT_86_66 \
14909 (UINT32_C(0xd) << 12)
14910 /* 93.33% of the max tx rate */
14911 #define HWRM_FUNC_VF_BW_QCFG_OUTPUT_VFN_RATE_PCT_93_33 \
14912 (UINT32_C(0xe) << 12)
14913 /* 100% of the max tx rate */
14914 #define HWRM_FUNC_VF_BW_QCFG_OUTPUT_VFN_RATE_PCT_100 \
14915 (UINT32_C(0xf) << 12)
14916 #define HWRM_FUNC_VF_BW_QCFG_OUTPUT_VFN_RATE_LAST \
14917 HWRM_FUNC_VF_BW_QCFG_OUTPUT_VFN_RATE_PCT_100
14918 uint8_t unused_0[7];
14920 * This field is used in Output records to indicate that the output
14921 * is completely written to RAM. This field should be read as '1'
14922 * to indicate that the output has been completely written.
14923 * When writing a command completion or response to an internal processor,
14924 * the order of writes has to be such that this field is written last.
14929 /***************************
14930 * hwrm_func_drv_if_change *
14931 ***************************/
14934 /* hwrm_func_drv_if_change_input (size:192b/24B) */
14935 struct hwrm_func_drv_if_change_input {
14936 /* The HWRM command request type. */
14939 * The completion ring to send the completion event on. This should
14940 * be the NQ ID returned from the `nq_alloc` HWRM command.
14942 uint16_t cmpl_ring;
14944 * The sequence ID is used by the driver for tracking multiple
14945 * commands. This ID is treated as opaque data by the firmware and
14946 * the value is returned in the `hwrm_resp_hdr` upon completion.
14950 * The target ID of the command:
14951 * * 0x0-0xFFF8 - The function ID
14952 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
14953 * * 0xFFFD - Reserved for user-space HWRM interface
14956 uint16_t target_id;
14958 * A physical address pointer pointing to a host buffer that the
14959 * command's response data will be written. This can be either a host
14960 * physical address (HPA) or a guest physical address (GPA) and must
14961 * point to a physically contiguous block of memory.
14963 uint64_t resp_addr;
14966 * When this bit is '1', the function driver is indicating
14967 * that the IF state is changing to UP state. The call should
14968 * be made at the beginning of the driver's open call before
14969 * resources are allocated. After making the call, the driver
14970 * should check the response to see if any resources may have
14971 * changed (see the response below). If the driver fails
14972 * the open call, the driver should make this call again with
14973 * this bit cleared to indicate that the IF state is not UP.
14974 * During the driver's close call when the IF state is changing
14975 * to DOWN, the driver should make this call with the bit cleared
14976 * after all resources have been freed.
14978 #define HWRM_FUNC_DRV_IF_CHANGE_INPUT_FLAGS_UP UINT32_C(0x1)
14982 /* hwrm_func_drv_if_change_output (size:128b/16B) */
14983 struct hwrm_func_drv_if_change_output {
14984 /* The specific error status for the command. */
14985 uint16_t error_code;
14986 /* The HWRM command request type. */
14988 /* The sequence ID from the original command. */
14990 /* The length of the response data in number of bytes. */
14994 * When this bit is '1', it indicates that the resources reserved
14995 * for this function may have changed. The driver should check
14996 * resource capabilities and reserve resources again before
14997 * allocating resources.
14999 #define HWRM_FUNC_DRV_IF_CHANGE_OUTPUT_FLAGS_RESC_CHANGE \
15002 * When this bit is '1', it indicates that the firmware got changed / reset.
15003 * The driver should do complete re-initialization when that bit is set.
15005 #define HWRM_FUNC_DRV_IF_CHANGE_OUTPUT_FLAGS_HOT_FW_RESET_DONE \
15007 uint8_t unused_0[3];
15009 * This field is used in Output records to indicate that the output
15010 * is completely written to RAM. This field should be read as '1'
15011 * to indicate that the output has been completely written.
15012 * When writing a command completion or response to an internal processor,
15013 * the order of writes has to be such that this field is written last.
15018 /*******************************
15019 * hwrm_func_host_pf_ids_query *
15020 *******************************/
15023 /* hwrm_func_host_pf_ids_query_input (size:192b/24B) */
15024 struct hwrm_func_host_pf_ids_query_input {
15025 /* The HWRM command request type. */
15028 * The completion ring to send the completion event on. This should
15029 * be the NQ ID returned from the `nq_alloc` HWRM command.
15031 uint16_t cmpl_ring;
15033 * The sequence ID is used by the driver for tracking multiple
15034 * commands. This ID is treated as opaque data by the firmware and
15035 * the value is returned in the `hwrm_resp_hdr` upon completion.
15039 * The target ID of the command:
15040 * * 0x0-0xFFF8 - The function ID
15041 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
15042 * * 0xFFFD - Reserved for user-space HWRM interface
15045 uint16_t target_id;
15047 * A physical address pointer pointing to a host buffer that the
15048 * command's response data will be written. This can be either a host
15049 * physical address (HPA) or a guest physical address (GPA) and must
15050 * point to a physically contiguous block of memory.
15052 uint64_t resp_addr;
15055 * # If this bit is set to '1', the query will contain PF(s)
15056 * belongs to SOC host.
15058 #define HWRM_FUNC_HOST_PF_IDS_QUERY_INPUT_HOST_SOC UINT32_C(0x1)
15060 * # If this bit is set to '1', the query will contain PF(s)
15061 * belongs to EP0 host.
15063 #define HWRM_FUNC_HOST_PF_IDS_QUERY_INPUT_HOST_EP_0 UINT32_C(0x2)
15065 * # If this bit is set to '1', the query will contain PF(s)
15066 * belongs to EP1 host.
15068 #define HWRM_FUNC_HOST_PF_IDS_QUERY_INPUT_HOST_EP_1 UINT32_C(0x4)
15070 * # If this bit is set to '1', the query will contain PF(s)
15071 * belongs to EP2 host.
15073 #define HWRM_FUNC_HOST_PF_IDS_QUERY_INPUT_HOST_EP_2 UINT32_C(0x8)
15075 * # If this bit is set to '1', the query will contain PF(s)
15076 * belongs to EP3 host.
15078 #define HWRM_FUNC_HOST_PF_IDS_QUERY_INPUT_HOST_EP_3 UINT32_C(0x10)
15080 * This provides a filter of what PF(s) will be returned in the
15085 * all available PF(s) belong to the host(s) (defined in the
15086 * host field). This includes the hidden PFs.
15088 #define HWRM_FUNC_HOST_PF_IDS_QUERY_INPUT_FILTER_ALL UINT32_C(0x0)
15090 * all available PF(s) belong to the host(s) (defined in the
15091 * host field) that is available for L2 traffic.
15093 #define HWRM_FUNC_HOST_PF_IDS_QUERY_INPUT_FILTER_L2 UINT32_C(0x1)
15095 * all available PF(s) belong to the host(s) (defined in the
15096 * host field) that is available for ROCE traffic.
15098 #define HWRM_FUNC_HOST_PF_IDS_QUERY_INPUT_FILTER_ROCE UINT32_C(0x2)
15099 #define HWRM_FUNC_HOST_PF_IDS_QUERY_INPUT_FILTER_LAST \
15100 HWRM_FUNC_HOST_PF_IDS_QUERY_INPUT_FILTER_ROCE
15101 uint8_t unused_1[6];
15104 /* hwrm_func_host_pf_ids_query_output (size:128b/16B) */
15105 struct hwrm_func_host_pf_ids_query_output {
15106 /* The specific error status for the command. */
15107 uint16_t error_code;
15108 /* The HWRM command request type. */
15110 /* The sequence ID from the original command. */
15112 /* The length of the response data in number of bytes. */
15114 /* This provides the first PF ID of the device. */
15115 uint16_t first_pf_id;
15116 uint16_t pf_ordinal_mask;
15118 * When this bit is '1', it indicates first PF belongs to one of
15119 * the hosts defined in the input request.
15121 #define HWRM_FUNC_HOST_PF_IDS_QUERY_OUTPUT_PF_ORDINAL_MASK_FUNC_0 \
15124 * When this bit is '1', it indicates 2nd PF belongs to one of the
15125 * hosts defined in the input request.
15127 #define HWRM_FUNC_HOST_PF_IDS_QUERY_OUTPUT_PF_ORDINAL_MASK_FUNC_1 \
15130 * When this bit is '1', it indicates 3rd PF belongs to one of the
15131 * hosts defined in the input request.
15133 #define HWRM_FUNC_HOST_PF_IDS_QUERY_OUTPUT_PF_ORDINAL_MASK_FUNC_2 \
15136 * When this bit is '1', it indicates 4th PF belongs to one of the
15137 * hosts defined in the input request.
15139 #define HWRM_FUNC_HOST_PF_IDS_QUERY_OUTPUT_PF_ORDINAL_MASK_FUNC_3 \
15142 * When this bit is '1', it indicates 5th PF belongs to one of the
15143 * hosts defined in the input request.
15145 #define HWRM_FUNC_HOST_PF_IDS_QUERY_OUTPUT_PF_ORDINAL_MASK_FUNC_4 \
15148 * When this bit is '1', it indicates 6th PF belongs to one of the
15149 * hosts defined in the input request.
15151 #define HWRM_FUNC_HOST_PF_IDS_QUERY_OUTPUT_PF_ORDINAL_MASK_FUNC_5 \
15154 * When this bit is '1', it indicates 7th PF belongs to one of the
15155 * hosts defined in the input request.
15157 #define HWRM_FUNC_HOST_PF_IDS_QUERY_OUTPUT_PF_ORDINAL_MASK_FUNC_6 \
15160 * When this bit is '1', it indicates 8th PF belongs to one of the
15161 * hosts defined in the input request.
15163 #define HWRM_FUNC_HOST_PF_IDS_QUERY_OUTPUT_PF_ORDINAL_MASK_FUNC_7 \
15166 * When this bit is '1', it indicates 9th PF belongs to one of the
15167 * hosts defined in the input request.
15169 #define HWRM_FUNC_HOST_PF_IDS_QUERY_OUTPUT_PF_ORDINAL_MASK_FUNC_8 \
15172 * When this bit is '1', it indicates 10th PF belongs to one of the
15173 * hosts defined in the input request.
15175 #define HWRM_FUNC_HOST_PF_IDS_QUERY_OUTPUT_PF_ORDINAL_MASK_FUNC_9 \
15178 * When this bit is '1', it indicates 11th PF belongs to one of the
15179 * hosts defined in the input request.
15181 #define HWRM_FUNC_HOST_PF_IDS_QUERY_OUTPUT_PF_ORDINAL_MASK_FUNC_10 \
15184 * When this bit is '1', it indicates 12th PF belongs to one of the
15185 * hosts defined in the input request.
15187 #define HWRM_FUNC_HOST_PF_IDS_QUERY_OUTPUT_PF_ORDINAL_MASK_FUNC_11 \
15190 * When this bit is '1', it indicates 13th PF belongs to one of the
15191 * hosts defined in the input request.
15193 #define HWRM_FUNC_HOST_PF_IDS_QUERY_OUTPUT_PF_ORDINAL_MASK_FUNC_12 \
15196 * When this bit is '1', it indicates 14th PF belongs to one of the
15197 * hosts defined in the input request.
15199 #define HWRM_FUNC_HOST_PF_IDS_QUERY_OUTPUT_PF_ORDINAL_MASK_FUNC_13 \
15202 * When this bit is '1', it indicates 15th PF belongs to one of the
15203 * hosts defined in the input request.
15205 #define HWRM_FUNC_HOST_PF_IDS_QUERY_OUTPUT_PF_ORDINAL_MASK_FUNC_14 \
15208 * When this bit is '1', it indicates 16th PF belongs to one of the
15209 * hosts defined in the input request.
15211 #define HWRM_FUNC_HOST_PF_IDS_QUERY_OUTPUT_PF_ORDINAL_MASK_FUNC_15 \
15213 uint8_t unused_1[3];
15215 * This field is used in Output records to indicate that the output
15216 * is completely written to RAM. This field should be read as '1'
15217 * to indicate that the output has been completely written.
15218 * When writing a command completion or response to an internal processor,
15219 * the order of writes has to be such that this field is written last.
15224 /*********************
15225 * hwrm_port_phy_cfg *
15226 *********************/
15229 /* hwrm_port_phy_cfg_input (size:448b/56B) */
15230 struct hwrm_port_phy_cfg_input {
15231 /* The HWRM command request type. */
15234 * The completion ring to send the completion event on. This should
15235 * be the NQ ID returned from the `nq_alloc` HWRM command.
15237 uint16_t cmpl_ring;
15239 * The sequence ID is used by the driver for tracking multiple
15240 * commands. This ID is treated as opaque data by the firmware and
15241 * the value is returned in the `hwrm_resp_hdr` upon completion.
15245 * The target ID of the command:
15246 * * 0x0-0xFFF8 - The function ID
15247 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
15248 * * 0xFFFD - Reserved for user-space HWRM interface
15251 uint16_t target_id;
15253 * A physical address pointer pointing to a host buffer that the
15254 * command's response data will be written. This can be either a host
15255 * physical address (HPA) or a guest physical address (GPA) and must
15256 * point to a physically contiguous block of memory.
15258 uint64_t resp_addr;
15261 * When this bit is set to '1', the PHY for the port shall
15264 * # If this bit is set to 1, then the HWRM shall reset the
15265 * PHY after applying PHY configuration changes specified
15267 * # In order to guarantee that PHY configuration changes
15268 * specified in this command take effect, the HWRM
15269 * client should set this flag to 1.
15270 * # If this bit is not set to 1, then the HWRM may reset
15271 * the PHY depending on the current PHY configuration and
15272 * settings specified in this command.
15274 #define HWRM_PORT_PHY_CFG_INPUT_FLAGS_RESET_PHY \
15276 /* deprecated bit. Do not use!!! */
15277 #define HWRM_PORT_PHY_CFG_INPUT_FLAGS_DEPRECATED \
15280 * When this bit is set to '1', and the force_pam4_link_speed
15281 * bit in the 'enables' field is '0', the link shall be forced
15282 * to the force_link_speed value.
15284 * When this bit is set to '1', and the force_pam4_link_speed
15285 * bit in the 'enables' field is '1', the link shall be forced
15286 * to the force_pam4_link_speed value.
15288 * When this bit is set to '1', the HWRM client should
15289 * not enable any of the auto negotiation related
15290 * fields represented by auto_XXX fields in this command.
15291 * When this bit is set to '1' and the HWRM client has
15292 * enabled a auto_XXX field in this command, then the
15293 * HWRM shall ignore the enabled auto_XXX field.
15295 * When this bit is set to zero, the link
15296 * shall be allowed to autoneg.
15298 #define HWRM_PORT_PHY_CFG_INPUT_FLAGS_FORCE \
15301 * When this bit is set to '1', the auto-negotiation process
15302 * shall be restarted on the link.
15304 #define HWRM_PORT_PHY_CFG_INPUT_FLAGS_RESTART_AUTONEG \
15307 * When this bit is set to '1', Energy Efficient Ethernet
15308 * (EEE) is requested to be enabled on this link.
15309 * If EEE is not supported on this port, then this flag
15310 * shall be ignored by the HWRM.
15312 #define HWRM_PORT_PHY_CFG_INPUT_FLAGS_EEE_ENABLE \
15315 * When this bit is set to '1', Energy Efficient Ethernet
15316 * (EEE) is requested to be disabled on this link.
15317 * If EEE is not supported on this port, then this flag
15318 * shall be ignored by the HWRM.
15320 #define HWRM_PORT_PHY_CFG_INPUT_FLAGS_EEE_DISABLE \
15323 * When this bit is set to '1' and EEE is enabled on this
15324 * link, then TX LPI is requested to be enabled on the link.
15325 * If EEE is not supported on this port, then this flag
15326 * shall be ignored by the HWRM.
15327 * If EEE is disabled on this port, then this flag shall be
15328 * ignored by the HWRM.
15330 #define HWRM_PORT_PHY_CFG_INPUT_FLAGS_EEE_TX_LPI_ENABLE \
15333 * When this bit is set to '1' and EEE is enabled on this
15334 * link, then TX LPI is requested to be disabled on the link.
15335 * If EEE is not supported on this port, then this flag
15336 * shall be ignored by the HWRM.
15337 * If EEE is disabled on this port, then this flag shall be
15338 * ignored by the HWRM.
15340 #define HWRM_PORT_PHY_CFG_INPUT_FLAGS_EEE_TX_LPI_DISABLE \
15343 * When set to 1, then the HWRM shall enable FEC autonegotitation
15344 * on this port if supported. When enabled, at least one of the
15345 * FEC modes must be advertised by enabling the fec_clause_74_enable,
15346 * fec_clause_91_enable, fec_rs544_1xn_enable, or fec_rs544_2xn_enable
15347 * flag. If none of the FEC mode is currently enabled, the HWRM
15348 * shall choose a default advertisement setting.
15349 * The default advertisement setting can be queried by calling
15350 * hwrm_port_phy_qcfg. Note that the link speed must be
15351 * in autonegotiation mode for FEC autonegotiation to take effect.
15352 * When set to 0, then this flag shall be ignored.
15353 * If FEC autonegotiation is not supported, then the HWRM shall ignore this
15356 #define HWRM_PORT_PHY_CFG_INPUT_FLAGS_FEC_AUTONEG_ENABLE \
15359 * When set to 1, then the HWRM shall disable FEC autonegotiation
15360 * on this port if supported.
15361 * When set to 0, then this flag shall be ignored.
15362 * If FEC autonegotiation is not supported, then the HWRM shall ignore this
15365 #define HWRM_PORT_PHY_CFG_INPUT_FLAGS_FEC_AUTONEG_DISABLE \
15368 * When set to 1, then the HWRM shall enable FEC CLAUSE 74 (Fire Code)
15369 * on this port if supported, by advertising FEC CLAUSE 74 if
15370 * FEC autonegotiation is enabled or force enabled otherwise.
15371 * When set to 0, then this flag shall be ignored.
15372 * If FEC CLAUSE 74 is not supported, then the HWRM shall ignore this
15375 #define HWRM_PORT_PHY_CFG_INPUT_FLAGS_FEC_CLAUSE74_ENABLE \
15378 * When set to 1, then the HWRM shall disable FEC CLAUSE 74 (Fire Code)
15379 * on this port if supported, by not advertising FEC CLAUSE 74 if
15380 * FEC autonegotiation is enabled or force disabled otherwise.
15381 * When set to 0, then this flag shall be ignored.
15382 * If FEC CLAUSE 74 is not supported, then the HWRM shall ignore this
15385 #define HWRM_PORT_PHY_CFG_INPUT_FLAGS_FEC_CLAUSE74_DISABLE \
15388 * When set to 1, then the HWRM shall enable FEC CLAUSE 91 (Reed Solomon)
15389 * on this port if supported, by advertising FEC CLAUSE 91 if
15390 * FEC autonegotiation is enabled or force enabled otherwise.
15391 * When set to 0, then this flag shall be ignored.
15392 * If FEC CLAUSE 91 is not supported, then the HWRM shall ignore this
15395 #define HWRM_PORT_PHY_CFG_INPUT_FLAGS_FEC_CLAUSE91_ENABLE \
15398 * When set to 1, then the HWRM shall disable FEC CLAUSE 91 (Reed Solomon)
15399 * on this port if supported, by not advertising FEC CLAUSE 91 if
15400 * FEC autonegotiation is enabled or force disabled otherwise.
15401 * When set to 0, then this flag shall be ignored.
15402 * If FEC CLAUSE 91 is not supported, then the HWRM shall ignore this
15405 #define HWRM_PORT_PHY_CFG_INPUT_FLAGS_FEC_CLAUSE91_DISABLE \
15408 * When this bit is set to '1', the link shall be forced to
15411 * # When this bit is set to '1", all other
15412 * command input settings related to the link speed shall
15414 * Once the link state is forced down, it can be
15415 * explicitly cleared from that state by setting this flag
15417 * # If this flag is set to '0', then the link shall be
15418 * cleared from forced down state if the link is in forced
15420 * There may be conditions (e.g. out-of-band or sideband
15421 * configuration changes for the link) outside the scope
15422 * of the HWRM implementation that may clear forced down
15425 #define HWRM_PORT_PHY_CFG_INPUT_FLAGS_FORCE_LINK_DWN \
15428 * When set to 1, then the HWRM shall enable FEC RS544_1XN
15429 * on this port if supported, by advertising FEC RS544_1XN if
15430 * FEC autonegotiation is enabled or force enabled otherwise.
15431 * When set to 0, then this flag shall be ignored.
15432 * If FEC RS544_1XN is not supported, then the HWRM shall ignore this
15435 #define HWRM_PORT_PHY_CFG_INPUT_FLAGS_FEC_RS544_1XN_ENABLE \
15438 * When set to 1, then the HWRM shall disable FEC RS544_1XN
15439 * on this port if supported, by not advertising FEC RS544_1XN if
15440 * FEC autonegotiation is enabled or force disabled otherwise.
15441 * When set to 0, then this flag shall be ignored.
15442 * If FEC RS544_1XN is not supported, then the HWRM shall ignore this
15445 #define HWRM_PORT_PHY_CFG_INPUT_FLAGS_FEC_RS544_1XN_DISABLE \
15448 * When set to 1, then the HWRM shall enable FEC RS544_2XN
15449 * on this port if supported, by advertising FEC RS544_2XN if
15450 * FEC autonegotiation is enabled or force enabled otherwise.
15451 * When set to 0, then this flag shall be ignored.
15452 * If FEC RS544_2XN is not supported, then the HWRM shall ignore this
15455 #define HWRM_PORT_PHY_CFG_INPUT_FLAGS_FEC_RS544_2XN_ENABLE \
15458 * When set to 1, then the HWRM shall disable FEC RS544_2XN
15459 * on this port if supported, by not advertising FEC RS544_2XN if
15460 * FEC autonegotiation is enabled or force disabled otherwise.
15461 * When set to 0, then this flag shall be ignored.
15462 * If FEC RS544_2XN is not supported, then the HWRM shall ignore this
15465 #define HWRM_PORT_PHY_CFG_INPUT_FLAGS_FEC_RS544_2XN_DISABLE \
15469 * This bit must be '1' for the auto_mode field to be
15472 #define HWRM_PORT_PHY_CFG_INPUT_ENABLES_AUTO_MODE \
15475 * This bit must be '1' for the auto_duplex field to be
15478 #define HWRM_PORT_PHY_CFG_INPUT_ENABLES_AUTO_DUPLEX \
15481 * This bit must be '1' for the auto_pause field to be
15484 #define HWRM_PORT_PHY_CFG_INPUT_ENABLES_AUTO_PAUSE \
15487 * This bit must be '1' for the auto_link_speed field to be
15490 #define HWRM_PORT_PHY_CFG_INPUT_ENABLES_AUTO_LINK_SPEED \
15493 * This bit must be '1' for the auto_link_speed_mask field to be
15496 #define HWRM_PORT_PHY_CFG_INPUT_ENABLES_AUTO_LINK_SPEED_MASK \
15499 * This bit must be '1' for the wirespeed field to be
15502 #define HWRM_PORT_PHY_CFG_INPUT_ENABLES_WIRESPEED \
15505 * This bit must be '1' for the lpbk field to be
15508 #define HWRM_PORT_PHY_CFG_INPUT_ENABLES_LPBK \
15511 * This bit must be '1' for the preemphasis field to be
15514 #define HWRM_PORT_PHY_CFG_INPUT_ENABLES_PREEMPHASIS \
15517 * This bit must be '1' for the force_pause field to be
15520 #define HWRM_PORT_PHY_CFG_INPUT_ENABLES_FORCE_PAUSE \
15523 * This bit must be '1' for the eee_link_speed_mask field to be
15526 #define HWRM_PORT_PHY_CFG_INPUT_ENABLES_EEE_LINK_SPEED_MASK \
15529 * This bit must be '1' for the tx_lpi_timer field to be
15532 #define HWRM_PORT_PHY_CFG_INPUT_ENABLES_TX_LPI_TIMER \
15535 * This bit must be '1' for the force_pam4_link_speed field to be
15538 #define HWRM_PORT_PHY_CFG_INPUT_ENABLES_FORCE_PAM4_LINK_SPEED \
15541 * This bit must be '1' for the auto_pam4_link_speed_mask field to
15544 #define HWRM_PORT_PHY_CFG_INPUT_ENABLES_AUTO_PAM4_LINK_SPEED_MASK \
15546 /* Port ID of port that is to be configured. */
15549 * This is the speed that will be used if the force
15550 * bit is '1'. If unsupported speed is selected, an error
15551 * will be generated.
15553 uint16_t force_link_speed;
15554 /* 100Mb link speed */
15555 #define HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_100MB UINT32_C(0x1)
15556 /* 1Gb link speed */
15557 #define HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_1GB UINT32_C(0xa)
15558 /* 2Gb link speed */
15559 #define HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_2GB UINT32_C(0x14)
15560 /* 25Gb link speed */
15561 #define HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_2_5GB UINT32_C(0x19)
15562 /* 10Gb link speed */
15563 #define HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_10GB UINT32_C(0x64)
15564 /* 20Mb link speed */
15565 #define HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_20GB UINT32_C(0xc8)
15566 /* 25Gb link speed */
15567 #define HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_25GB UINT32_C(0xfa)
15568 /* 40Gb link speed */
15569 #define HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_40GB UINT32_C(0x190)
15570 /* 50Gb link speed */
15571 #define HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_50GB UINT32_C(0x1f4)
15572 /* 100Gb link speed */
15573 #define HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_100GB UINT32_C(0x3e8)
15574 /* 10Mb link speed */
15575 #define HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_10MB UINT32_C(0xffff)
15576 #define HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_LAST \
15577 HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_10MB
15579 * This value is used to identify what autoneg mode is
15580 * used when the link speed is not being forced.
15583 /* Disable autoneg or autoneg disabled. No speeds are selected. */
15584 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_MODE_NONE UINT32_C(0x0)
15585 /* Select all possible speeds for autoneg mode. */
15586 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_MODE_ALL_SPEEDS UINT32_C(0x1)
15588 * Select only the auto_link_speed speed for autoneg mode. This mode has
15589 * been DEPRECATED. An HWRM client should not use this mode.
15591 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_MODE_ONE_SPEED UINT32_C(0x2)
15593 * Select the auto_link_speed or any speed below that speed for autoneg.
15594 * This mode has been DEPRECATED. An HWRM client should not use this mode.
15596 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_MODE_ONE_OR_BELOW UINT32_C(0x3)
15598 * Select the speeds based on the corresponding link speed mask values
15599 * that are provided. The included speeds are specified in the
15600 * auto_link_speed and auto_pam4_link_speed fields.
15602 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_MODE_SPEED_MASK UINT32_C(0x4)
15603 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_MODE_LAST \
15604 HWRM_PORT_PHY_CFG_INPUT_AUTO_MODE_SPEED_MASK
15606 * This is the duplex setting that will be used if the autoneg_mode
15607 * is "one_speed" or "one_or_below".
15609 uint8_t auto_duplex;
15610 /* Half Duplex will be requested. */
15611 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_HALF UINT32_C(0x0)
15612 /* Full duplex will be requested. */
15613 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_FULL UINT32_C(0x1)
15614 /* Both Half and Full dupex will be requested. */
15615 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_BOTH UINT32_C(0x2)
15616 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_LAST \
15617 HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_BOTH
15619 * This value is used to configure the pause that will be
15620 * used for autonegotiation.
15621 * Add text on the usage of auto_pause and force_pause.
15623 uint8_t auto_pause;
15625 * When this bit is '1', Generation of tx pause messages
15626 * has been requested. Disabled otherwise.
15628 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_TX \
15631 * When this bit is '1', Reception of rx pause messages
15632 * has been requested. Disabled otherwise.
15634 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_RX \
15637 * When set to 1, the advertisement of pause is enabled.
15639 * # When the auto_mode is not set to none and this flag is
15640 * set to 1, then the auto_pause bits on this port are being
15641 * advertised and autoneg pause results are being interpreted.
15642 * # When the auto_mode is not set to none and this
15643 * flag is set to 0, the pause is forced as indicated in
15644 * force_pause, and also advertised as auto_pause bits, but
15645 * the autoneg results are not interpreted since the pause
15646 * configuration is being forced.
15647 * # When the auto_mode is set to none and this flag is set to
15648 * 1, auto_pause bits should be ignored and should be set to 0.
15650 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_AUTONEG_PAUSE \
15654 * This is the speed that will be used if the autoneg_mode
15655 * is "one_speed" or "one_or_below". If an unsupported speed
15656 * is selected, an error will be generated.
15658 uint16_t auto_link_speed;
15659 /* 100Mb link speed */
15660 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_100MB UINT32_C(0x1)
15661 /* 1Gb link speed */
15662 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_1GB UINT32_C(0xa)
15663 /* 2Gb link speed */
15664 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_2GB UINT32_C(0x14)
15665 /* 25Gb link speed */
15666 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_2_5GB UINT32_C(0x19)
15667 /* 10Gb link speed */
15668 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_10GB UINT32_C(0x64)
15669 /* 20Mb link speed */
15670 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_20GB UINT32_C(0xc8)
15671 /* 25Gb link speed */
15672 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_25GB UINT32_C(0xfa)
15673 /* 40Gb link speed */
15674 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_40GB UINT32_C(0x190)
15675 /* 50Gb link speed */
15676 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_50GB UINT32_C(0x1f4)
15677 /* 100Gb link speed */
15678 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_100GB UINT32_C(0x3e8)
15679 /* 10Mb link speed */
15680 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_10MB UINT32_C(0xffff)
15681 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_LAST \
15682 HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_10MB
15684 * This is a mask of link speeds that will be used if
15685 * autoneg_mode is "mask". If unsupported speed is enabled
15686 * an error will be generated.
15688 uint16_t auto_link_speed_mask;
15689 /* 100Mb link speed (Half-duplex) */
15690 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_100MBHD \
15692 /* 100Mb link speed (Full-duplex) */
15693 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_100MB \
15695 /* 1Gb link speed (Half-duplex) */
15696 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_1GBHD \
15698 /* 1Gb link speed (Full-duplex) */
15699 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_1GB \
15701 /* 2Gb link speed */
15702 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_2GB \
15704 /* 25Gb link speed */
15705 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_2_5GB \
15707 /* 10Gb link speed */
15708 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_10GB \
15710 /* 20Gb link speed */
15711 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_20GB \
15713 /* 25Gb link speed */
15714 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_25GB \
15716 /* 40Gb link speed */
15717 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_40GB \
15719 /* 50Gb link speed */
15720 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_50GB \
15722 /* 100Gb link speed */
15723 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_100GB \
15725 /* 10Mb link speed (Half-duplex) */
15726 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_10MBHD \
15728 /* 10Mb link speed (Full-duplex) */
15729 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_10MB \
15731 /* This value controls the wirespeed feature. */
15733 /* Wirespeed feature is disabled. */
15734 #define HWRM_PORT_PHY_CFG_INPUT_WIRESPEED_OFF UINT32_C(0x0)
15735 /* Wirespeed feature is enabled. */
15736 #define HWRM_PORT_PHY_CFG_INPUT_WIRESPEED_ON UINT32_C(0x1)
15737 #define HWRM_PORT_PHY_CFG_INPUT_WIRESPEED_LAST \
15738 HWRM_PORT_PHY_CFG_INPUT_WIRESPEED_ON
15739 /* This value controls the loopback setting for the PHY. */
15741 /* No loopback is selected. Normal operation. */
15742 #define HWRM_PORT_PHY_CFG_INPUT_LPBK_NONE UINT32_C(0x0)
15744 * The HW will be configured with local loopback such that
15745 * host data is sent back to the host without modification.
15747 #define HWRM_PORT_PHY_CFG_INPUT_LPBK_LOCAL UINT32_C(0x1)
15749 * The HW will be configured with remote loopback such that
15750 * port logic will send packets back out the transmitter that
15753 #define HWRM_PORT_PHY_CFG_INPUT_LPBK_REMOTE UINT32_C(0x2)
15755 * The HW will be configured with external loopback such that
15756 * host data is sent on the transmitter and based on the external
15757 * loopback connection the data will be received without modification.
15759 #define HWRM_PORT_PHY_CFG_INPUT_LPBK_EXTERNAL UINT32_C(0x3)
15760 #define HWRM_PORT_PHY_CFG_INPUT_LPBK_LAST \
15761 HWRM_PORT_PHY_CFG_INPUT_LPBK_EXTERNAL
15763 * This value is used to configure the pause that will be
15764 * used for force mode.
15766 uint8_t force_pause;
15768 * When this bit is '1', Generation of tx pause messages
15769 * is supported. Disabled otherwise.
15771 #define HWRM_PORT_PHY_CFG_INPUT_FORCE_PAUSE_TX UINT32_C(0x1)
15773 * When this bit is '1', Reception of rx pause messages
15774 * is supported. Disabled otherwise.
15776 #define HWRM_PORT_PHY_CFG_INPUT_FORCE_PAUSE_RX UINT32_C(0x2)
15779 * This value controls the pre-emphasis to be used for the
15780 * link. Driver should not set this value (use
15781 * enable.preemphasis = 0) unless driver is sure of setting.
15782 * Normally HWRM FW will determine proper pre-emphasis.
15784 uint32_t preemphasis;
15786 * Setting for link speed mask that is used to
15787 * advertise speeds during autonegotiation when EEE is enabled.
15788 * This field is valid only when EEE is enabled.
15789 * The speeds specified in this field shall be a subset of
15790 * speeds specified in auto_link_speed_mask.
15791 * If EEE is enabled,then at least one speed shall be provided
15794 uint16_t eee_link_speed_mask;
15796 #define HWRM_PORT_PHY_CFG_INPUT_EEE_LINK_SPEED_MASK_RSVD1 \
15798 /* 100Mb link speed (Full-duplex) */
15799 #define HWRM_PORT_PHY_CFG_INPUT_EEE_LINK_SPEED_MASK_100MB \
15802 #define HWRM_PORT_PHY_CFG_INPUT_EEE_LINK_SPEED_MASK_RSVD2 \
15804 /* 1Gb link speed (Full-duplex) */
15805 #define HWRM_PORT_PHY_CFG_INPUT_EEE_LINK_SPEED_MASK_1GB \
15808 #define HWRM_PORT_PHY_CFG_INPUT_EEE_LINK_SPEED_MASK_RSVD3 \
15811 #define HWRM_PORT_PHY_CFG_INPUT_EEE_LINK_SPEED_MASK_RSVD4 \
15813 /* 10Gb link speed */
15814 #define HWRM_PORT_PHY_CFG_INPUT_EEE_LINK_SPEED_MASK_10GB \
15817 * This is the speed that will be used if the force and force_pam4
15818 * bits are '1'. If unsupported speed is selected, an error
15819 * will be generated.
15821 uint16_t force_pam4_link_speed;
15822 /* 50Gb link speed */
15823 #define HWRM_PORT_PHY_CFG_INPUT_FORCE_PAM4_LINK_SPEED_50GB \
15825 /* 100Gb link speed */
15826 #define HWRM_PORT_PHY_CFG_INPUT_FORCE_PAM4_LINK_SPEED_100GB \
15828 /* 200Gb link speed */
15829 #define HWRM_PORT_PHY_CFG_INPUT_FORCE_PAM4_LINK_SPEED_200GB \
15831 #define HWRM_PORT_PHY_CFG_INPUT_FORCE_PAM4_LINK_SPEED_LAST \
15832 HWRM_PORT_PHY_CFG_INPUT_FORCE_PAM4_LINK_SPEED_200GB
15834 * Requested setting of TX LPI timer in microseconds.
15835 * This field is valid only when EEE is enabled and TX LPI is
15838 uint32_t tx_lpi_timer;
15839 #define HWRM_PORT_PHY_CFG_INPUT_TX_LPI_TIMER_MASK UINT32_C(0xffffff)
15840 #define HWRM_PORT_PHY_CFG_INPUT_TX_LPI_TIMER_SFT 0
15841 /* This field specifies which PAM4 speeds are enabled for auto mode. */
15842 uint16_t auto_link_pam4_speed_mask;
15843 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_PAM4_SPEED_MASK_50G \
15845 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_PAM4_SPEED_MASK_100G \
15847 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_PAM4_SPEED_MASK_200G \
15849 uint8_t unused_2[2];
15852 /* hwrm_port_phy_cfg_output (size:128b/16B) */
15853 struct hwrm_port_phy_cfg_output {
15854 /* The specific error status for the command. */
15855 uint16_t error_code;
15856 /* The HWRM command request type. */
15858 /* The sequence ID from the original command. */
15860 /* The length of the response data in number of bytes. */
15862 uint8_t unused_0[7];
15864 * This field is used in Output records to indicate that the output
15865 * is completely written to RAM. This field should be read as '1'
15866 * to indicate that the output has been completely written.
15867 * When writing a command completion or response to an internal processor,
15868 * the order of writes has to be such that this field is written last.
15873 /* hwrm_port_phy_cfg_cmd_err (size:64b/8B) */
15874 struct hwrm_port_phy_cfg_cmd_err {
15876 * command specific error codes that goes to
15877 * the cmd_err field in Common HWRM Error Response.
15880 /* Unknown error */
15881 #define HWRM_PORT_PHY_CFG_CMD_ERR_CODE_UNKNOWN UINT32_C(0x0)
15882 /* Unable to complete operation due to invalid speed */
15883 #define HWRM_PORT_PHY_CFG_CMD_ERR_CODE_ILLEGAL_SPEED UINT32_C(0x1)
15885 * retry the command since the phy is not ready.
15886 * retry count is returned in opaque_0.
15887 * This is only valid for the first command and
15888 * this value will not change for successive calls.
15889 * but if a 0 is returned at any time then this should
15890 * be treated as an un recoverable failure,
15892 * retry interval in milli seconds is returned in opaque_1.
15893 * This specifies the time that user should wait before
15894 * issuing the next port_phy_cfg command.
15896 #define HWRM_PORT_PHY_CFG_CMD_ERR_CODE_RETRY UINT32_C(0x2)
15897 #define HWRM_PORT_PHY_CFG_CMD_ERR_CODE_LAST \
15898 HWRM_PORT_PHY_CFG_CMD_ERR_CODE_RETRY
15899 uint8_t unused_0[7];
15902 /**********************
15903 * hwrm_port_phy_qcfg *
15904 **********************/
15907 /* hwrm_port_phy_qcfg_input (size:192b/24B) */
15908 struct hwrm_port_phy_qcfg_input {
15909 /* The HWRM command request type. */
15912 * The completion ring to send the completion event on. This should
15913 * be the NQ ID returned from the `nq_alloc` HWRM command.
15915 uint16_t cmpl_ring;
15917 * The sequence ID is used by the driver for tracking multiple
15918 * commands. This ID is treated as opaque data by the firmware and
15919 * the value is returned in the `hwrm_resp_hdr` upon completion.
15923 * The target ID of the command:
15924 * * 0x0-0xFFF8 - The function ID
15925 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
15926 * * 0xFFFD - Reserved for user-space HWRM interface
15929 uint16_t target_id;
15931 * A physical address pointer pointing to a host buffer that the
15932 * command's response data will be written. This can be either a host
15933 * physical address (HPA) or a guest physical address (GPA) and must
15934 * point to a physically contiguous block of memory.
15936 uint64_t resp_addr;
15937 /* Port ID of port that is to be queried. */
15939 uint8_t unused_0[6];
15942 /* hwrm_port_phy_qcfg_output (size:832b/104B) */
15943 struct hwrm_port_phy_qcfg_output {
15944 /* The specific error status for the command. */
15945 uint16_t error_code;
15946 /* The HWRM command request type. */
15948 /* The sequence ID from the original command. */
15950 /* The length of the response data in number of bytes. */
15952 /* This value indicates the current link status. */
15954 /* There is no link or cable detected. */
15955 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_NO_LINK UINT32_C(0x0)
15956 /* There is no link, but a cable has been detected. */
15957 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SIGNAL UINT32_C(0x1)
15958 /* There is a link. */
15959 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_LINK UINT32_C(0x2)
15960 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_LAST \
15961 HWRM_PORT_PHY_QCFG_OUTPUT_LINK_LINK
15963 * This value indicates the current link signaling mode of the
15966 uint8_t link_signal_mode;
15967 /* NRZ signaling */
15968 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SIGNAL_MODE_NRZ UINT32_C(0x0)
15969 /* PAM4 signaling */
15970 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SIGNAL_MODE_PAM4 UINT32_C(0x1)
15971 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SIGNAL_MODE_LAST \
15972 HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SIGNAL_MODE_PAM4
15974 * This value indicates the current link speed of the connection.
15975 * The link_signal_mode field indicates if the link is using
15976 * NRZ or PAM4 signaling.
15978 uint16_t link_speed;
15979 /* 100Mb link speed */
15980 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_100MB UINT32_C(0x1)
15981 /* 1Gb link speed */
15982 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_1GB UINT32_C(0xa)
15983 /* 2Gb link speed */
15984 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_2GB UINT32_C(0x14)
15985 /* 25Gb link speed */
15986 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_2_5GB UINT32_C(0x19)
15987 /* 10Gb link speed */
15988 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_10GB UINT32_C(0x64)
15989 /* 20Mb link speed */
15990 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_20GB UINT32_C(0xc8)
15991 /* 25Gb link speed */
15992 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_25GB UINT32_C(0xfa)
15993 /* 40Gb link speed */
15994 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_40GB UINT32_C(0x190)
15995 /* 50Gb link speed */
15996 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_50GB UINT32_C(0x1f4)
15997 /* 100Gb link speed */
15998 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_100GB UINT32_C(0x3e8)
15999 /* 200Gb link speed */
16000 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_200GB UINT32_C(0x7d0)
16001 /* 10Mb link speed */
16002 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_10MB UINT32_C(0xffff)
16003 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_LAST \
16004 HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_10MB
16006 * This value is indicates the duplex of the current
16009 uint8_t duplex_cfg;
16010 /* Half Duplex connection. */
16011 #define HWRM_PORT_PHY_QCFG_OUTPUT_DUPLEX_CFG_HALF UINT32_C(0x0)
16012 /* Full duplex connection. */
16013 #define HWRM_PORT_PHY_QCFG_OUTPUT_DUPLEX_CFG_FULL UINT32_C(0x1)
16014 #define HWRM_PORT_PHY_QCFG_OUTPUT_DUPLEX_CFG_LAST \
16015 HWRM_PORT_PHY_QCFG_OUTPUT_DUPLEX_CFG_FULL
16017 * This value is used to indicate the current
16018 * pause configuration. When autoneg is enabled, this value
16019 * represents the autoneg results of pause configuration.
16023 * When this bit is '1', Generation of tx pause messages
16024 * is supported. Disabled otherwise.
16026 #define HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_TX UINT32_C(0x1)
16028 * When this bit is '1', Reception of rx pause messages
16029 * is supported. Disabled otherwise.
16031 #define HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_RX UINT32_C(0x2)
16033 * The supported speeds for the port. This is a bit mask.
16034 * For each speed that is supported, the corresponding
16035 * bit will be set to '1'.
16037 uint16_t support_speeds;
16038 /* 100Mb link speed (Half-duplex) */
16039 #define HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_100MBHD \
16041 /* 100Mb link speed (Full-duplex) */
16042 #define HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_100MB \
16044 /* 1Gb link speed (Half-duplex) */
16045 #define HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_1GBHD \
16047 /* 1Gb link speed (Full-duplex) */
16048 #define HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_1GB \
16050 /* 2Gb link speed */
16051 #define HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_2GB \
16053 /* 25Gb link speed */
16054 #define HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_2_5GB \
16056 /* 10Gb link speed */
16057 #define HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_10GB \
16059 /* 20Gb link speed */
16060 #define HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_20GB \
16062 /* 25Gb link speed */
16063 #define HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_25GB \
16065 /* 40Gb link speed */
16066 #define HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_40GB \
16068 /* 50Gb link speed */
16069 #define HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_50GB \
16071 /* 100Gb link speed */
16072 #define HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_100GB \
16074 /* 10Mb link speed (Half-duplex) */
16075 #define HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_10MBHD \
16077 /* 10Mb link speed (Full-duplex) */
16078 #define HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_10MB \
16081 * Current setting of forced link speed.
16082 * When the link speed is not being forced, this
16083 * value shall be set to 0.
16085 uint16_t force_link_speed;
16086 /* 100Mb link speed */
16087 #define HWRM_PORT_PHY_QCFG_OUTPUT_FORCE_LINK_SPEED_100MB UINT32_C(0x1)
16088 /* 1Gb link speed */
16089 #define HWRM_PORT_PHY_QCFG_OUTPUT_FORCE_LINK_SPEED_1GB UINT32_C(0xa)
16090 /* 2Gb link speed */
16091 #define HWRM_PORT_PHY_QCFG_OUTPUT_FORCE_LINK_SPEED_2GB UINT32_C(0x14)
16092 /* 25Gb link speed */
16093 #define HWRM_PORT_PHY_QCFG_OUTPUT_FORCE_LINK_SPEED_2_5GB UINT32_C(0x19)
16094 /* 10Gb link speed */
16095 #define HWRM_PORT_PHY_QCFG_OUTPUT_FORCE_LINK_SPEED_10GB UINT32_C(0x64)
16096 /* 20Mb link speed */
16097 #define HWRM_PORT_PHY_QCFG_OUTPUT_FORCE_LINK_SPEED_20GB UINT32_C(0xc8)
16098 /* 25Gb link speed */
16099 #define HWRM_PORT_PHY_QCFG_OUTPUT_FORCE_LINK_SPEED_25GB UINT32_C(0xfa)
16100 /* 40Gb link speed */
16101 #define HWRM_PORT_PHY_QCFG_OUTPUT_FORCE_LINK_SPEED_40GB \
16103 /* 50Gb link speed */
16104 #define HWRM_PORT_PHY_QCFG_OUTPUT_FORCE_LINK_SPEED_50GB \
16106 /* 100Gb link speed */
16107 #define HWRM_PORT_PHY_QCFG_OUTPUT_FORCE_LINK_SPEED_100GB \
16109 /* 10Mb link speed */
16110 #define HWRM_PORT_PHY_QCFG_OUTPUT_FORCE_LINK_SPEED_10MB \
16112 #define HWRM_PORT_PHY_QCFG_OUTPUT_FORCE_LINK_SPEED_LAST \
16113 HWRM_PORT_PHY_QCFG_OUTPUT_FORCE_LINK_SPEED_10MB
16114 /* Current setting of auto negotiation mode. */
16116 /* Disable autoneg or autoneg disabled. No speeds are selected. */
16117 #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_MODE_NONE UINT32_C(0x0)
16118 /* Select all possible speeds for autoneg mode. */
16119 #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_MODE_ALL_SPEEDS UINT32_C(0x1)
16121 * Select only the auto_link_speed speed for autoneg mode. This mode has
16122 * been DEPRECATED. An HWRM client should not use this mode.
16124 #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_MODE_ONE_SPEED UINT32_C(0x2)
16126 * Select the auto_link_speed or any speed below that speed for autoneg.
16127 * This mode has been DEPRECATED. An HWRM client should not use this mode.
16129 #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_MODE_ONE_OR_BELOW UINT32_C(0x3)
16131 * Select the speeds based on the corresponding link speed mask value
16132 * that is provided.
16134 #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_MODE_SPEED_MASK UINT32_C(0x4)
16135 #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_MODE_LAST \
16136 HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_MODE_SPEED_MASK
16138 * Current setting of pause autonegotiation.
16139 * Move autoneg_pause flag here.
16141 uint8_t auto_pause;
16143 * When this bit is '1', Generation of tx pause messages
16144 * has been requested. Disabled otherwise.
16146 #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_PAUSE_TX \
16149 * When this bit is '1', Reception of rx pause messages
16150 * has been requested. Disabled otherwise.
16152 #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_PAUSE_RX \
16155 * When set to 1, the advertisement of pause is enabled.
16157 * # When the auto_mode is not set to none and this flag is
16158 * set to 1, then the auto_pause bits on this port are being
16159 * advertised and autoneg pause results are being interpreted.
16160 * # When the auto_mode is not set to none and this
16161 * flag is set to 0, the pause is forced as indicated in
16162 * force_pause, and also advertised as auto_pause bits, but
16163 * the autoneg results are not interpreted since the pause
16164 * configuration is being forced.
16165 * # When the auto_mode is set to none and this flag is set to
16166 * 1, auto_pause bits should be ignored and should be set to 0.
16168 #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_PAUSE_AUTONEG_PAUSE \
16171 * Current setting for auto_link_speed. This field is only
16172 * valid when auto_mode is set to "one_speed" or "one_or_below".
16174 uint16_t auto_link_speed;
16175 /* 100Mb link speed */
16176 #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_100MB UINT32_C(0x1)
16177 /* 1Gb link speed */
16178 #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_1GB UINT32_C(0xa)
16179 /* 2Gb link speed */
16180 #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_2GB UINT32_C(0x14)
16181 /* 25Gb link speed */
16182 #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_2_5GB UINT32_C(0x19)
16183 /* 10Gb link speed */
16184 #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_10GB UINT32_C(0x64)
16185 /* 20Mb link speed */
16186 #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_20GB UINT32_C(0xc8)
16187 /* 25Gb link speed */
16188 #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_25GB UINT32_C(0xfa)
16189 /* 40Gb link speed */
16190 #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_40GB UINT32_C(0x190)
16191 /* 50Gb link speed */
16192 #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_50GB UINT32_C(0x1f4)
16193 /* 100Gb link speed */
16194 #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_100GB UINT32_C(0x3e8)
16195 /* 10Mb link speed */
16196 #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_10MB \
16198 #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_LAST \
16199 HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_10MB
16201 * Current setting for auto_link_speed_mask that is used to
16202 * advertise speeds during autonegotiation.
16203 * This field is only valid when auto_mode is set to "mask".
16204 * The speeds specified in this field shall be a subset of
16205 * supported speeds on this port.
16207 uint16_t auto_link_speed_mask;
16208 /* 100Mb link speed (Half-duplex) */
16209 #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_MASK_100MBHD \
16211 /* 100Mb link speed (Full-duplex) */
16212 #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_MASK_100MB \
16214 /* 1Gb link speed (Half-duplex) */
16215 #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_MASK_1GBHD \
16217 /* 1Gb link speed (Full-duplex) */
16218 #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_MASK_1GB \
16220 /* 2Gb link speed */
16221 #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_MASK_2GB \
16223 /* 25Gb link speed */
16224 #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_MASK_2_5GB \
16226 /* 10Gb link speed */
16227 #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_MASK_10GB \
16229 /* 20Gb link speed */
16230 #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_MASK_20GB \
16232 /* 25Gb link speed */
16233 #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_MASK_25GB \
16235 /* 40Gb link speed */
16236 #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_MASK_40GB \
16238 /* 50Gb link speed */
16239 #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_MASK_50GB \
16241 /* 100Gb link speed */
16242 #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_MASK_100GB \
16244 /* 10Mb link speed (Half-duplex) */
16245 #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_MASK_10MBHD \
16247 /* 10Mb link speed (Full-duplex) */
16248 #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_MASK_10MB \
16250 /* Current setting for wirespeed. */
16252 /* Wirespeed feature is disabled. */
16253 #define HWRM_PORT_PHY_QCFG_OUTPUT_WIRESPEED_OFF UINT32_C(0x0)
16254 /* Wirespeed feature is enabled. */
16255 #define HWRM_PORT_PHY_QCFG_OUTPUT_WIRESPEED_ON UINT32_C(0x1)
16256 #define HWRM_PORT_PHY_QCFG_OUTPUT_WIRESPEED_LAST \
16257 HWRM_PORT_PHY_QCFG_OUTPUT_WIRESPEED_ON
16258 /* Current setting for loopback. */
16260 /* No loopback is selected. Normal operation. */
16261 #define HWRM_PORT_PHY_QCFG_OUTPUT_LPBK_NONE UINT32_C(0x0)
16263 * The HW will be configured with local loopback such that
16264 * host data is sent back to the host without modification.
16266 #define HWRM_PORT_PHY_QCFG_OUTPUT_LPBK_LOCAL UINT32_C(0x1)
16268 * The HW will be configured with remote loopback such that
16269 * port logic will send packets back out the transmitter that
16272 #define HWRM_PORT_PHY_QCFG_OUTPUT_LPBK_REMOTE UINT32_C(0x2)
16274 * The HW will be configured with external loopback such that
16275 * host data is sent on the transmitter and based on the external
16276 * loopback connection the data will be received without modification.
16278 #define HWRM_PORT_PHY_QCFG_OUTPUT_LPBK_EXTERNAL UINT32_C(0x3)
16279 #define HWRM_PORT_PHY_QCFG_OUTPUT_LPBK_LAST \
16280 HWRM_PORT_PHY_QCFG_OUTPUT_LPBK_EXTERNAL
16282 * Current setting of forced pause.
16283 * When the pause configuration is not being forced, then
16284 * this value shall be set to 0.
16286 uint8_t force_pause;
16288 * When this bit is '1', Generation of tx pause messages
16289 * is supported. Disabled otherwise.
16291 #define HWRM_PORT_PHY_QCFG_OUTPUT_FORCE_PAUSE_TX UINT32_C(0x1)
16293 * When this bit is '1', Reception of rx pause messages
16294 * is supported. Disabled otherwise.
16296 #define HWRM_PORT_PHY_QCFG_OUTPUT_FORCE_PAUSE_RX UINT32_C(0x2)
16298 * This value indicates the current status of the optics module on
16301 uint8_t module_status;
16302 /* Module is inserted and accepted */
16303 #define HWRM_PORT_PHY_QCFG_OUTPUT_MODULE_STATUS_NONE \
16305 /* Module is rejected and transmit side Laser is disabled. */
16306 #define HWRM_PORT_PHY_QCFG_OUTPUT_MODULE_STATUS_DISABLETX \
16308 /* Module mismatch warning. */
16309 #define HWRM_PORT_PHY_QCFG_OUTPUT_MODULE_STATUS_WARNINGMSG \
16311 /* Module is rejected and powered down. */
16312 #define HWRM_PORT_PHY_QCFG_OUTPUT_MODULE_STATUS_PWRDOWN \
16314 /* Module is not inserted. */
16315 #define HWRM_PORT_PHY_QCFG_OUTPUT_MODULE_STATUS_NOTINSERTED \
16317 /* Module is powered down because of over current fault. */
16318 #define HWRM_PORT_PHY_QCFG_OUTPUT_MODULE_STATUS_CURRENTFAULT \
16320 /* Module status is not applicable. */
16321 #define HWRM_PORT_PHY_QCFG_OUTPUT_MODULE_STATUS_NOTAPPLICABLE \
16323 #define HWRM_PORT_PHY_QCFG_OUTPUT_MODULE_STATUS_LAST \
16324 HWRM_PORT_PHY_QCFG_OUTPUT_MODULE_STATUS_NOTAPPLICABLE
16325 /* Current setting for preemphasis. */
16326 uint32_t preemphasis;
16327 /* This field represents the major version of the PHY. */
16329 /* This field represents the minor version of the PHY. */
16331 /* This field represents the build version of the PHY. */
16333 /* This value represents a PHY type. */
16336 #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_UNKNOWN \
16339 #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_BASECR \
16341 /* BASE-KR4 (Deprecated) */
16342 #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_BASEKR4 \
16345 #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_BASELR \
16348 #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_BASESR \
16350 /* BASE-KR2 (Deprecated) */
16351 #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_BASEKR2 \
16354 #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_BASEKX \
16357 #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_BASEKR \
16360 #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_BASET \
16362 /* EEE capable BASE-T */
16363 #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_BASETE \
16365 /* SGMII connected external PHY */
16366 #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_SGMIIEXTPHY \
16368 /* 25G_BASECR_CA_L */
16369 #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_25G_BASECR_CA_L \
16371 /* 25G_BASECR_CA_S */
16372 #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_25G_BASECR_CA_S \
16374 /* 25G_BASECR_CA_N */
16375 #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_25G_BASECR_CA_N \
16378 #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_25G_BASESR \
16381 #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_100G_BASECR4 \
16384 #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_100G_BASESR4 \
16387 #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_100G_BASELR4 \
16390 #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_100G_BASEER4 \
16392 /* 100G_BASESR10 */
16393 #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_100G_BASESR10 \
16396 #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_40G_BASECR4 \
16399 #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_40G_BASESR4 \
16402 #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_40G_BASELR4 \
16405 #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_40G_BASEER4 \
16407 /* 40G_ACTIVE_CABLE */
16408 #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_40G_ACTIVE_CABLE \
16411 #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_1G_BASET \
16414 #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_1G_BASESX \
16417 #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_1G_BASECX \
16420 #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_200G_BASECR4 \
16423 #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_200G_BASESR4 \
16426 #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_200G_BASELR4 \
16429 #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_200G_BASEER4 \
16431 #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_LAST \
16432 HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_200G_BASEER4
16433 /* This value represents a media type. */
16434 uint8_t media_type;
16436 #define HWRM_PORT_PHY_QCFG_OUTPUT_MEDIA_TYPE_UNKNOWN UINT32_C(0x0)
16438 #define HWRM_PORT_PHY_QCFG_OUTPUT_MEDIA_TYPE_TP UINT32_C(0x1)
16439 /* Direct Attached Copper */
16440 #define HWRM_PORT_PHY_QCFG_OUTPUT_MEDIA_TYPE_DAC UINT32_C(0x2)
16442 #define HWRM_PORT_PHY_QCFG_OUTPUT_MEDIA_TYPE_FIBRE UINT32_C(0x3)
16443 #define HWRM_PORT_PHY_QCFG_OUTPUT_MEDIA_TYPE_LAST \
16444 HWRM_PORT_PHY_QCFG_OUTPUT_MEDIA_TYPE_FIBRE
16445 /* This value represents a transceiver type. */
16446 uint8_t xcvr_pkg_type;
16447 /* PHY and MAC are in the same package */
16448 #define HWRM_PORT_PHY_QCFG_OUTPUT_XCVR_PKG_TYPE_XCVR_INTERNAL \
16450 /* PHY and MAC are in different packages */
16451 #define HWRM_PORT_PHY_QCFG_OUTPUT_XCVR_PKG_TYPE_XCVR_EXTERNAL \
16453 #define HWRM_PORT_PHY_QCFG_OUTPUT_XCVR_PKG_TYPE_LAST \
16454 HWRM_PORT_PHY_QCFG_OUTPUT_XCVR_PKG_TYPE_XCVR_EXTERNAL
16455 uint8_t eee_config_phy_addr;
16456 /* This field represents PHY address. */
16457 #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_ADDR_MASK \
16459 #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_ADDR_SFT 0
16461 * This field represents flags related to EEE configuration.
16462 * These EEE configuration flags are valid only when the
16463 * auto_mode is not set to none (in other words autonegotiation
16466 #define HWRM_PORT_PHY_QCFG_OUTPUT_EEE_CONFIG_MASK \
16468 #define HWRM_PORT_PHY_QCFG_OUTPUT_EEE_CONFIG_SFT 5
16470 * When set to 1, Energy Efficient Ethernet (EEE) mode is enabled.
16471 * Speeds for autoneg with EEE mode enabled
16472 * are based on eee_link_speed_mask.
16474 #define HWRM_PORT_PHY_QCFG_OUTPUT_EEE_CONFIG_EEE_ENABLED \
16477 * This flag is valid only when eee_enabled is set to 1.
16479 * # If eee_enabled is set to 0, then EEE mode is disabled
16480 * and this flag shall be ignored.
16481 * # If eee_enabled is set to 1 and this flag is set to 1,
16482 * then Energy Efficient Ethernet (EEE) mode is enabled
16484 * # If eee_enabled is set to 1 and this flag is set to 0,
16485 * then Energy Efficient Ethernet (EEE) mode is enabled
16486 * but is currently not in use.
16488 #define HWRM_PORT_PHY_QCFG_OUTPUT_EEE_CONFIG_EEE_ACTIVE \
16491 * This flag is valid only when eee_enabled is set to 1.
16493 * # If eee_enabled is set to 0, then EEE mode is disabled
16494 * and this flag shall be ignored.
16495 * # If eee_enabled is set to 1 and this flag is set to 1,
16496 * then Energy Efficient Ethernet (EEE) mode is enabled
16497 * and TX LPI is enabled.
16498 * # If eee_enabled is set to 1 and this flag is set to 0,
16499 * then Energy Efficient Ethernet (EEE) mode is enabled
16500 * but TX LPI is disabled.
16502 #define HWRM_PORT_PHY_QCFG_OUTPUT_EEE_CONFIG_EEE_TX_LPI \
16505 * When set to 1, the parallel detection is used to determine
16506 * the speed of the link partner.
16508 * Parallel detection is used when a autonegotiation capable
16509 * device is connected to a link parter that is not capable
16510 * of autonegotiation.
16512 uint8_t parallel_detect;
16514 * When set to 1, the parallel detection is used to determine
16515 * the speed of the link partner.
16517 * Parallel detection is used when a autonegotiation capable
16518 * device is connected to a link parter that is not capable
16519 * of autonegotiation.
16521 #define HWRM_PORT_PHY_QCFG_OUTPUT_PARALLEL_DETECT UINT32_C(0x1)
16523 * The advertised speeds for the port by the link partner.
16524 * Each advertised speed will be set to '1'.
16526 uint16_t link_partner_adv_speeds;
16527 /* 100Mb link speed (Half-duplex) */
16528 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_SPEEDS_100MBHD \
16530 /* 100Mb link speed (Full-duplex) */
16531 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_SPEEDS_100MB \
16533 /* 1Gb link speed (Half-duplex) */
16534 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_SPEEDS_1GBHD \
16536 /* 1Gb link speed (Full-duplex) */
16537 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_SPEEDS_1GB \
16539 /* 2Gb link speed */
16540 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_SPEEDS_2GB \
16542 /* 25Gb link speed */
16543 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_SPEEDS_2_5GB \
16545 /* 10Gb link speed */
16546 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_SPEEDS_10GB \
16548 /* 20Gb link speed */
16549 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_SPEEDS_20GB \
16551 /* 25Gb link speed */
16552 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_SPEEDS_25GB \
16554 /* 40Gb link speed */
16555 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_SPEEDS_40GB \
16557 /* 50Gb link speed */
16558 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_SPEEDS_50GB \
16560 /* 100Gb link speed */
16561 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_SPEEDS_100GB \
16563 /* 10Mb link speed (Half-duplex) */
16564 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_SPEEDS_10MBHD \
16566 /* 10Mb link speed (Full-duplex) */
16567 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_SPEEDS_10MB \
16570 * The advertised autoneg for the port by the link partner.
16571 * This field is deprecated and should be set to 0.
16573 uint8_t link_partner_adv_auto_mode;
16574 /* Disable autoneg or autoneg disabled. No speeds are selected. */
16575 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_AUTO_MODE_NONE \
16577 /* Select all possible speeds for autoneg mode. */
16578 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_AUTO_MODE_ALL_SPEEDS \
16581 * Select only the auto_link_speed speed for autoneg mode. This mode has
16582 * been DEPRECATED. An HWRM client should not use this mode.
16584 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_AUTO_MODE_ONE_SPEED \
16587 * Select the auto_link_speed or any speed below that speed for autoneg.
16588 * This mode has been DEPRECATED. An HWRM client should not use this mode.
16590 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_AUTO_MODE_ONE_OR_BELOW \
16593 * Select the speeds based on the corresponding link speed mask value
16594 * that is provided.
16596 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_AUTO_MODE_SPEED_MASK \
16598 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_AUTO_MODE_LAST \
16599 HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_AUTO_MODE_SPEED_MASK
16600 /* The advertised pause settings on the port by the link partner. */
16601 uint8_t link_partner_adv_pause;
16603 * When this bit is '1', Generation of tx pause messages
16604 * is supported. Disabled otherwise.
16606 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_PAUSE_TX \
16609 * When this bit is '1', Reception of rx pause messages
16610 * is supported. Disabled otherwise.
16612 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_PAUSE_RX \
16615 * Current setting for link speed mask that is used to
16616 * advertise speeds during autonegotiation when EEE is enabled.
16617 * This field is valid only when eee_enabled flags is set to 1.
16618 * The speeds specified in this field shall be a subset of
16619 * speeds specified in auto_link_speed_mask.
16621 uint16_t adv_eee_link_speed_mask;
16623 #define HWRM_PORT_PHY_QCFG_OUTPUT_ADV_EEE_LINK_SPEED_MASK_RSVD1 \
16625 /* 100Mb link speed (Full-duplex) */
16626 #define HWRM_PORT_PHY_QCFG_OUTPUT_ADV_EEE_LINK_SPEED_MASK_100MB \
16629 #define HWRM_PORT_PHY_QCFG_OUTPUT_ADV_EEE_LINK_SPEED_MASK_RSVD2 \
16631 /* 1Gb link speed (Full-duplex) */
16632 #define HWRM_PORT_PHY_QCFG_OUTPUT_ADV_EEE_LINK_SPEED_MASK_1GB \
16635 #define HWRM_PORT_PHY_QCFG_OUTPUT_ADV_EEE_LINK_SPEED_MASK_RSVD3 \
16638 #define HWRM_PORT_PHY_QCFG_OUTPUT_ADV_EEE_LINK_SPEED_MASK_RSVD4 \
16640 /* 10Gb link speed */
16641 #define HWRM_PORT_PHY_QCFG_OUTPUT_ADV_EEE_LINK_SPEED_MASK_10GB \
16644 * Current setting for link speed mask that is advertised by
16645 * the link partner when EEE is enabled.
16646 * This field is valid only when eee_enabled flags is set to 1.
16648 uint16_t link_partner_adv_eee_link_speed_mask;
16650 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_EEE_LINK_SPEED_MASK_RSVD1 \
16652 /* 100Mb link speed (Full-duplex) */
16653 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_EEE_LINK_SPEED_MASK_100MB \
16656 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_EEE_LINK_SPEED_MASK_RSVD2 \
16658 /* 1Gb link speed (Full-duplex) */
16659 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_EEE_LINK_SPEED_MASK_1GB \
16662 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_EEE_LINK_SPEED_MASK_RSVD3 \
16665 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_EEE_LINK_SPEED_MASK_RSVD4 \
16667 /* 10Gb link speed */
16668 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_EEE_LINK_SPEED_MASK_10GB \
16670 uint32_t xcvr_identifier_type_tx_lpi_timer;
16672 * Current setting of TX LPI timer in microseconds.
16673 * This field is valid only when_eee_enabled flag is set to 1
16674 * and tx_lpi_enabled is set to 1.
16676 #define HWRM_PORT_PHY_QCFG_OUTPUT_TX_LPI_TIMER_MASK \
16678 #define HWRM_PORT_PHY_QCFG_OUTPUT_TX_LPI_TIMER_SFT 0
16679 /* This value represents transceiver identifier type. */
16680 #define HWRM_PORT_PHY_QCFG_OUTPUT_XCVR_IDENTIFIER_TYPE_MASK \
16681 UINT32_C(0xff000000)
16682 #define HWRM_PORT_PHY_QCFG_OUTPUT_XCVR_IDENTIFIER_TYPE_SFT 24
16684 #define HWRM_PORT_PHY_QCFG_OUTPUT_XCVR_IDENTIFIER_TYPE_UNKNOWN \
16685 (UINT32_C(0x0) << 24)
16686 /* SFP/SFP+/SFP28 */
16687 #define HWRM_PORT_PHY_QCFG_OUTPUT_XCVR_IDENTIFIER_TYPE_SFP \
16688 (UINT32_C(0x3) << 24)
16690 #define HWRM_PORT_PHY_QCFG_OUTPUT_XCVR_IDENTIFIER_TYPE_QSFP \
16691 (UINT32_C(0xc) << 24)
16693 #define HWRM_PORT_PHY_QCFG_OUTPUT_XCVR_IDENTIFIER_TYPE_QSFPPLUS \
16694 (UINT32_C(0xd) << 24)
16696 #define HWRM_PORT_PHY_QCFG_OUTPUT_XCVR_IDENTIFIER_TYPE_QSFP28 \
16697 (UINT32_C(0x11) << 24)
16698 #define HWRM_PORT_PHY_QCFG_OUTPUT_XCVR_IDENTIFIER_TYPE_LAST \
16699 HWRM_PORT_PHY_QCFG_OUTPUT_XCVR_IDENTIFIER_TYPE_QSFP28
16701 * This value represents the current configuration of
16702 * Forward Error Correction (FEC) on the port.
16706 * When set to 1, then FEC is not supported on this port. If this flag
16707 * is set to 1, then all other FEC configuration flags shall be ignored.
16708 * When set to 0, then FEC is supported as indicated by other
16709 * configuration flags.
16711 #define HWRM_PORT_PHY_QCFG_OUTPUT_FEC_CFG_FEC_NONE_SUPPORTED \
16714 * When set to 1, then FEC autonegotiation is supported on this port.
16715 * When set to 0, then FEC autonegotiation is not supported on this port.
16717 #define HWRM_PORT_PHY_QCFG_OUTPUT_FEC_CFG_FEC_AUTONEG_SUPPORTED \
16720 * When set to 1, then FEC autonegotiation is enabled on this port.
16721 * When set to 0, then FEC autonegotiation is disabled if supported.
16722 * This flag should be ignored if FEC autonegotiation is not supported on this port.
16724 #define HWRM_PORT_PHY_QCFG_OUTPUT_FEC_CFG_FEC_AUTONEG_ENABLED \
16727 * When set to 1, then FEC CLAUSE 74 (Fire Code) is supported on this port.
16728 * When set to 0, then FEC CLAUSE 74 (Fire Code) is not supported on this port.
16730 #define HWRM_PORT_PHY_QCFG_OUTPUT_FEC_CFG_FEC_CLAUSE74_SUPPORTED \
16733 * When set to 1, then FEC CLAUSE 74 (Fire Code) is enabled on this
16734 * port. This means that FEC CLAUSE 74 is either advertised if
16735 * FEC autonegotiation is enabled or FEC CLAUSE 74 is force enabled.
16736 * When set to 0, then FEC CLAUSE 74 (Fire Code) is disabled if supported.
16737 * This flag should be ignored if FEC CLAUSE 74 is not supported on this port.
16739 #define HWRM_PORT_PHY_QCFG_OUTPUT_FEC_CFG_FEC_CLAUSE74_ENABLED \
16742 * When set to 1, then FEC CLAUSE 91 (Reed Solomon) is supported on this port.
16743 * When set to 0, then FEC CLAUSE 91 (Reed Solomon) is not supported on this port.
16745 #define HWRM_PORT_PHY_QCFG_OUTPUT_FEC_CFG_FEC_CLAUSE91_SUPPORTED \
16748 * When set to 1, then FEC CLAUSE 91 (Reed Solomon) is enabled on this
16749 * port. This means that FEC CLAUSE 91 is either advertised if
16750 * FEC autonegotiation is enabled or FEC CLAUSE 91 is force enabled.
16751 * When set to 0, then FEC CLAUSE 91 (Reed Solomon) is disabled if supported.
16752 * This flag should be ignored if FEC CLAUSE 91 is not supported on this port.
16754 #define HWRM_PORT_PHY_QCFG_OUTPUT_FEC_CFG_FEC_CLAUSE91_ENABLED \
16757 * When set to 1, then FEC RS544_1XN is supported on this port.
16758 * When set to 0, then FEC RS544_1XN is not supported on this port.
16760 #define HWRM_PORT_PHY_QCFG_OUTPUT_FEC_CFG_FEC_RS544_1XN_SUPPORTED \
16763 * When set to 1, then RS544_1XN is enabled on this
16764 * port. This means that FEC RS544_1XN is either advertised if
16765 * FEC autonegotiation is enabled or FEC RS544_1XN is force enabled.
16766 * When set to 0, then FEC RS544_1XN is disabled if supported.
16767 * This flag should be ignored if FEC RS544_1XN is not supported on this port.
16769 #define HWRM_PORT_PHY_QCFG_OUTPUT_FEC_CFG_FEC_RS544_1XN_ENABLED \
16772 * When set to 1, then FEC RS544_2XN is supported on this port.
16773 * When set to 0, then FEC RS544_2XN is not supported on this port.
16775 #define HWRM_PORT_PHY_QCFG_OUTPUT_FEC_CFG_FEC_RS544_2XN_SUPPORTED \
16778 * When set to 1, then RS544_2XN is enabled on this
16779 * port. This means that FEC RS544_2XN is either advertised if
16780 * FEC autonegotiation is enabled or FEC RS544_2XN is force enabled.
16781 * When set to 0, then FEC RS544_2XN is disabled if supported.
16782 * This flag should be ignored if FEC RS544_2XN is not supported on this port.
16784 #define HWRM_PORT_PHY_QCFG_OUTPUT_FEC_CFG_FEC_RS544_2XN_ENABLED \
16787 * When set to 1, then FEC CLAUSE 74 (Fire Code) is active on this
16788 * port, either successfully autonegoatiated or forced.
16789 * When set to 0, then FEC CLAUSE 74 (Fire Code) is not active.
16790 * This flag is only valid when link is up on this port.
16791 * At most only one active FEC flags (fec_clause74_active,
16792 * fec_clause91_active, fec_rs544_1xn, fec_rs544_2xn) can be set.
16794 #define HWRM_PORT_PHY_QCFG_OUTPUT_FEC_CFG_FEC_CLAUSE74_ACTIVE \
16797 * When set to 1, then FEC CLAUSE 91 (Reed Solomon) is active on this
16798 * port, either successfully autonegoatiated or forced.
16799 * When set to 0, then FEC CLAUSE 91 (Reed Solomon) is not active.
16800 * This flag is only valid when link is up on this port.
16801 * At most only one active FEC flags (fec_clause74_active,
16802 * fec_clause91_active, fec_rs544_1xn, fec_rs544_2xn) can be set.
16804 #define HWRM_PORT_PHY_QCFG_OUTPUT_FEC_CFG_FEC_CLAUSE91_ACTIVE \
16807 * When set to 1, then FEC RS544_1XN is active on this
16808 * port, either successfully autonegoatiated or forced.
16809 * When set to 0, then FEC RS544_1XN is not active.
16810 * This flag is only valid when link is up on this port.
16811 * At most only one active FEC flags (fec_clause74_active,
16812 * fec_clause91_active, fec_rs544_1xn, fec_rs544_2xn) can be set.
16814 #define HWRM_PORT_PHY_QCFG_OUTPUT_FEC_CFG_FEC_RS544_1XN_ACTIVE \
16817 * When set to 1, then FEC RS544_2XN is active on this
16818 * port, either successfully autonegoatiated or forced.
16819 * When set to 0, then FEC RS544_2XN is not active.
16820 * This flag is only valid when link is up on this port.
16821 * At most only one active FEC flags (fec_clause74_active,
16822 * fec_clause91_active, fec_rs544_1xn, fec_rs544_2xn) can be set.
16824 #define HWRM_PORT_PHY_QCFG_OUTPUT_FEC_CFG_FEC_RS544_2XN_ACTIVE \
16827 * This value is indicates the duplex of the current
16828 * connection state.
16830 uint8_t duplex_state;
16831 /* Half Duplex connection. */
16832 #define HWRM_PORT_PHY_QCFG_OUTPUT_DUPLEX_STATE_HALF UINT32_C(0x0)
16833 /* Full duplex connection. */
16834 #define HWRM_PORT_PHY_QCFG_OUTPUT_DUPLEX_STATE_FULL UINT32_C(0x1)
16835 #define HWRM_PORT_PHY_QCFG_OUTPUT_DUPLEX_STATE_LAST \
16836 HWRM_PORT_PHY_QCFG_OUTPUT_DUPLEX_STATE_FULL
16837 /* Option flags fields. */
16838 uint8_t option_flags;
16839 /* When this bit is '1', Media auto detect is enabled. */
16840 #define HWRM_PORT_PHY_QCFG_OUTPUT_OPTION_FLAGS_MEDIA_AUTO_DETECT \
16843 * Up to 16 bytes of null padded ASCII string representing
16845 * If the string is set to null, then the vendor name is not
16848 char phy_vendor_name[16];
16850 * Up to 16 bytes of null padded ASCII string that
16851 * identifies vendor specific part number of the PHY.
16852 * If the string is set to null, then the vendor specific
16853 * part number is not available.
16855 char phy_vendor_partnumber[16];
16857 * The supported PAM4 speeds for the port. This is a bit mask.
16858 * For each speed that is supported, the corresponding
16859 * bit will be set to '1'.
16861 uint16_t support_pam4_speeds;
16862 #define HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_PAM4_SPEEDS_50G \
16864 #define HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_PAM4_SPEEDS_100G \
16866 #define HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_PAM4_SPEEDS_200G \
16869 * Current setting of forced PAM4 link speed.
16870 * When the link speed is not being forced, this
16871 * value shall be set to 0.
16873 uint16_t force_pam4_link_speed;
16874 /* 50Gb link speed */
16875 #define HWRM_PORT_PHY_QCFG_OUTPUT_FORCE_PAM4_LINK_SPEED_50GB \
16877 /* 100Gb link speed */
16878 #define HWRM_PORT_PHY_QCFG_OUTPUT_FORCE_PAM4_LINK_SPEED_100GB \
16880 /* 200Gb link speed */
16881 #define HWRM_PORT_PHY_QCFG_OUTPUT_FORCE_PAM4_LINK_SPEED_200GB \
16883 #define HWRM_PORT_PHY_QCFG_OUTPUT_FORCE_PAM4_LINK_SPEED_LAST \
16884 HWRM_PORT_PHY_QCFG_OUTPUT_FORCE_PAM4_LINK_SPEED_200GB
16886 * Current setting for auto_pam4_link_speed_mask that is used to
16887 * advertise speeds during autonegotiation.
16888 * This field is only valid when auto_mode is set to "mask".
16889 * The speeds specified in this field shall be a subset of
16890 * supported speeds on this port.
16892 uint16_t auto_pam4_link_speed_mask;
16893 #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_PAM4_LINK_SPEED_MASK_50G \
16895 #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_PAM4_LINK_SPEED_MASK_100G \
16897 #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_PAM4_LINK_SPEED_MASK_200G \
16900 * The advertised PAM4 speeds for the port by the link partner.
16901 * Each advertised speed will be set to '1'.
16903 uint16_t link_partner_pam4_adv_speeds;
16904 /* 50Gb link speed */
16905 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_PAM4_ADV_SPEEDS_50GB \
16907 /* 100Gb link speed */
16908 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_PAM4_ADV_SPEEDS_100GB \
16910 /* 200Gb link speed */
16911 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_PAM4_ADV_SPEEDS_200GB \
16913 uint8_t unused_0[7];
16915 * This field is used in Output records to indicate that the output
16916 * is completely written to RAM. This field should be read as '1'
16917 * to indicate that the output has been completely written.
16918 * When writing a command completion or response to an internal processor,
16919 * the order of writes has to be such that this field is written last.
16924 /*********************
16925 * hwrm_port_mac_cfg *
16926 *********************/
16929 /* hwrm_port_mac_cfg_input (size:384b/48B) */
16930 struct hwrm_port_mac_cfg_input {
16931 /* The HWRM command request type. */
16934 * The completion ring to send the completion event on. This should
16935 * be the NQ ID returned from the `nq_alloc` HWRM command.
16937 uint16_t cmpl_ring;
16939 * The sequence ID is used by the driver for tracking multiple
16940 * commands. This ID is treated as opaque data by the firmware and
16941 * the value is returned in the `hwrm_resp_hdr` upon completion.
16945 * The target ID of the command:
16946 * * 0x0-0xFFF8 - The function ID
16947 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
16948 * * 0xFFFD - Reserved for user-space HWRM interface
16951 uint16_t target_id;
16953 * A physical address pointer pointing to a host buffer that the
16954 * command's response data will be written. This can be either a host
16955 * physical address (HPA) or a guest physical address (GPA) and must
16956 * point to a physically contiguous block of memory.
16958 uint64_t resp_addr;
16960 * In this field, there are a number of CoS mappings related flags
16961 * that are used to configure CoS mappings and their corresponding
16962 * priorities in the hardware.
16963 * For the priorities of CoS mappings, the HWRM uses the following
16964 * priority order (high to low) by default:
16967 * # tunnel_vlan_pri
16970 * A subset of CoS mappings can be enabled.
16971 * If a priority is not specified for an enabled CoS mapping, the
16972 * priority will be assigned in the above order for the enabled CoS
16973 * mappings. For example, if vlan_pri and ip_dscp CoS mappings are
16974 * enabled and their priorities are not specified, the following
16975 * priority order (high to low) will be used by the HWRM:
16980 * vlan_pri CoS mapping together with default CoS with lower priority
16981 * are enabled by default by the HWRM.
16985 * When this bit is '1', this command will configure
16986 * the MAC to match the current link state of the PHY.
16987 * If the link is not established on the PHY, then this
16988 * bit has no effect.
16990 #define HWRM_PORT_MAC_CFG_INPUT_FLAGS_MATCH_LINK \
16993 * When this bit is set to '1', the inner VLAN PRI to CoS mapping
16994 * is requested to be enabled.
16996 #define HWRM_PORT_MAC_CFG_INPUT_FLAGS_VLAN_PRI2COS_ENABLE \
16999 * When this bit is set to '1', tunnel VLAN PRI field to
17000 * CoS mapping is requested to be enabled.
17002 #define HWRM_PORT_MAC_CFG_INPUT_FLAGS_TUNNEL_PRI2COS_ENABLE \
17005 * When this bit is set to '1', the IP DSCP to CoS mapping is
17006 * requested to be enabled.
17008 #define HWRM_PORT_MAC_CFG_INPUT_FLAGS_IP_DSCP2COS_ENABLE \
17011 * When this bit is '1', the HWRM is requested to
17012 * enable timestamp capture capability on the receive side
17015 #define HWRM_PORT_MAC_CFG_INPUT_FLAGS_PTP_RX_TS_CAPTURE_ENABLE \
17018 * When this bit is '1', the HWRM is requested to
17019 * disable timestamp capture capability on the receive side
17022 #define HWRM_PORT_MAC_CFG_INPUT_FLAGS_PTP_RX_TS_CAPTURE_DISABLE \
17025 * When this bit is '1', the HWRM is requested to
17026 * enable timestamp capture capability on the transmit side
17029 #define HWRM_PORT_MAC_CFG_INPUT_FLAGS_PTP_TX_TS_CAPTURE_ENABLE \
17032 * When this bit is '1', the HWRM is requested to
17033 * disable timestamp capture capability on the transmit side
17036 #define HWRM_PORT_MAC_CFG_INPUT_FLAGS_PTP_TX_TS_CAPTURE_DISABLE \
17039 * When this bit is '1', the Out-Of-Box WoL is requested to
17040 * be enabled on this port.
17042 #define HWRM_PORT_MAC_CFG_INPUT_FLAGS_OOB_WOL_ENABLE \
17045 * When this bit is '1', the Out-Of-Box WoL is requested to
17046 * be disabled on this port.
17048 #define HWRM_PORT_MAC_CFG_INPUT_FLAGS_OOB_WOL_DISABLE \
17051 * When this bit is set to '1', the inner VLAN PRI to CoS mapping
17052 * is requested to be disabled.
17054 #define HWRM_PORT_MAC_CFG_INPUT_FLAGS_VLAN_PRI2COS_DISABLE \
17057 * When this bit is set to '1', tunnel VLAN PRI field to
17058 * CoS mapping is requested to be disabled.
17060 #define HWRM_PORT_MAC_CFG_INPUT_FLAGS_TUNNEL_PRI2COS_DISABLE \
17063 * When this bit is set to '1', the IP DSCP to CoS mapping is
17064 * requested to be disabled.
17066 #define HWRM_PORT_MAC_CFG_INPUT_FLAGS_IP_DSCP2COS_DISABLE \
17069 * When this bit is set to '1', and the ptp_tx_ts_capture_enable
17070 * bit is set, then the device uses one step Tx timestamping.
17071 * This bit is temporary and used for experimental purposes.
17073 #define HWRM_PORT_MAC_CFG_INPUT_FLAGS_PTP_ONE_STEP_TX_TS \
17077 * This bit must be '1' for the ipg field to be
17080 #define HWRM_PORT_MAC_CFG_INPUT_ENABLES_IPG \
17083 * This bit must be '1' for the lpbk field to be
17086 #define HWRM_PORT_MAC_CFG_INPUT_ENABLES_LPBK \
17089 * This bit must be '1' for the vlan_pri2cos_map_pri field to be
17092 #define HWRM_PORT_MAC_CFG_INPUT_ENABLES_VLAN_PRI2COS_MAP_PRI \
17095 * This bit must be '1' for the tunnel_pri2cos_map_pri field to be
17098 #define HWRM_PORT_MAC_CFG_INPUT_ENABLES_TUNNEL_PRI2COS_MAP_PRI \
17101 * This bit must be '1' for the dscp2cos_map_pri field to be
17104 #define HWRM_PORT_MAC_CFG_INPUT_ENABLES_DSCP2COS_MAP_PRI \
17107 * This bit must be '1' for the rx_ts_capture_ptp_msg_type field to be
17110 #define HWRM_PORT_MAC_CFG_INPUT_ENABLES_RX_TS_CAPTURE_PTP_MSG_TYPE \
17113 * This bit must be '1' for the tx_ts_capture_ptp_msg_type field to be
17116 #define HWRM_PORT_MAC_CFG_INPUT_ENABLES_TX_TS_CAPTURE_PTP_MSG_TYPE \
17119 * This bit must be '1' for the cos_field_cfg field to be
17122 #define HWRM_PORT_MAC_CFG_INPUT_ENABLES_COS_FIELD_CFG \
17125 * This bit must be '1' for the ptp_freq_adj_ppb field to be
17128 #define HWRM_PORT_MAC_CFG_INPUT_ENABLES_PTP_FREQ_ADJ_PPB \
17130 /* Port ID of port that is to be configured. */
17133 * This value is used to configure the minimum IPG that will
17134 * be sent between packets by this port.
17137 /* This value controls the loopback setting for the MAC. */
17139 /* No loopback is selected. Normal operation. */
17140 #define HWRM_PORT_MAC_CFG_INPUT_LPBK_NONE UINT32_C(0x0)
17142 * The HW will be configured with local loopback such that
17143 * host data is sent back to the host without modification.
17145 #define HWRM_PORT_MAC_CFG_INPUT_LPBK_LOCAL UINT32_C(0x1)
17147 * The HW will be configured with remote loopback such that
17148 * port logic will send packets back out the transmitter that
17151 #define HWRM_PORT_MAC_CFG_INPUT_LPBK_REMOTE UINT32_C(0x2)
17152 #define HWRM_PORT_MAC_CFG_INPUT_LPBK_LAST \
17153 HWRM_PORT_MAC_CFG_INPUT_LPBK_REMOTE
17155 * This value controls the priority setting of VLAN PRI to CoS
17156 * mapping based on VLAN Tags of inner packet headers of
17157 * tunneled packets or packet headers of non-tunneled packets.
17159 * # Each XXX_pri variable shall have a unique priority value
17160 * when it is being specified.
17161 * # When comparing priorities of mappings, higher value
17162 * indicates higher priority.
17163 * For example, a value of 0-3 is returned where 0 is being
17164 * the lowest priority and 3 is being the highest priority.
17166 uint8_t vlan_pri2cos_map_pri;
17167 /* Reserved field. */
17170 * This value controls the priority setting of VLAN PRI to CoS
17171 * mapping based on VLAN Tags of tunneled header.
17172 * This mapping only applies when tunneled headers
17175 * # Each XXX_pri variable shall have a unique priority value
17176 * when it is being specified.
17177 * # When comparing priorities of mappings, higher value
17178 * indicates higher priority.
17179 * For example, a value of 0-3 is returned where 0 is being
17180 * the lowest priority and 3 is being the highest priority.
17182 uint8_t tunnel_pri2cos_map_pri;
17184 * This value controls the priority setting of IP DSCP to CoS
17185 * mapping based on inner IP header of tunneled packets or
17186 * IP header of non-tunneled packets.
17188 * # Each XXX_pri variable shall have a unique priority value
17189 * when it is being specified.
17190 * # When comparing priorities of mappings, higher value
17191 * indicates higher priority.
17192 * For example, a value of 0-3 is returned where 0 is being
17193 * the lowest priority and 3 is being the highest priority.
17195 uint8_t dscp2pri_map_pri;
17197 * This is a 16-bit bit mask that is used to request a
17198 * specific configuration of time stamp capture of PTP messages
17199 * on the receive side of this port.
17200 * This field shall be ignored if the ptp_rx_ts_capture_enable
17201 * flag is not set in this command.
17202 * Otherwise, if bit 'i' is set, then the HWRM is being
17203 * requested to configure the receive side of the port to
17204 * capture the time stamp of every received PTP message
17205 * with messageType field value set to i.
17207 uint16_t rx_ts_capture_ptp_msg_type;
17209 * This is a 16-bit bit mask that is used to request a
17210 * specific configuration of time stamp capture of PTP messages
17211 * on the transmit side of this port.
17212 * This field shall be ignored if the ptp_tx_ts_capture_enable
17213 * flag is not set in this command.
17214 * Otherwise, if bit 'i' is set, then the HWRM is being
17215 * requested to configure the transmit side of the port to
17216 * capture the time stamp of every transmitted PTP message
17217 * with messageType field value set to i.
17219 uint16_t tx_ts_capture_ptp_msg_type;
17220 /* Configuration of CoS fields. */
17221 uint8_t cos_field_cfg;
17223 #define HWRM_PORT_MAC_CFG_INPUT_COS_FIELD_CFG_RSVD1 \
17226 * This field is used to specify selection of VLAN PRI value
17227 * based on whether one or two VLAN Tags are present in
17228 * the inner packet headers of tunneled packets or
17229 * non-tunneled packets.
17230 * This field is valid only if inner VLAN PRI to CoS mapping
17232 * If VLAN PRI to CoS mapping is not enabled, then this
17233 * field shall be ignored.
17235 #define HWRM_PORT_MAC_CFG_INPUT_COS_FIELD_CFG_VLAN_PRI_SEL_MASK \
17237 #define HWRM_PORT_MAC_CFG_INPUT_COS_FIELD_CFG_VLAN_PRI_SEL_SFT \
17240 * Select inner VLAN PRI when 1 or 2 VLAN Tags are
17241 * present in the inner packet headers
17243 #define HWRM_PORT_MAC_CFG_INPUT_COS_FIELD_CFG_VLAN_PRI_SEL_INNERMOST \
17244 (UINT32_C(0x0) << 1)
17246 * Select outer VLAN Tag PRI when 2 VLAN Tags are
17247 * present in the inner packet headers.
17248 * No VLAN PRI shall be selected for this configuration
17249 * if only one VLAN Tag is present in the inner
17252 #define HWRM_PORT_MAC_CFG_INPUT_COS_FIELD_CFG_VLAN_PRI_SEL_OUTER \
17253 (UINT32_C(0x1) << 1)
17255 * Select outermost VLAN PRI when 1 or 2 VLAN Tags
17256 * are present in the inner packet headers
17258 #define HWRM_PORT_MAC_CFG_INPUT_COS_FIELD_CFG_VLAN_PRI_SEL_OUTERMOST \
17259 (UINT32_C(0x2) << 1)
17261 #define HWRM_PORT_MAC_CFG_INPUT_COS_FIELD_CFG_VLAN_PRI_SEL_UNSPECIFIED \
17262 (UINT32_C(0x3) << 1)
17263 #define HWRM_PORT_MAC_CFG_INPUT_COS_FIELD_CFG_VLAN_PRI_SEL_LAST \
17264 HWRM_PORT_MAC_CFG_INPUT_COS_FIELD_CFG_VLAN_PRI_SEL_UNSPECIFIED
17266 * This field is used to specify selection of tunnel VLAN
17267 * PRI value based on whether one or two VLAN Tags are
17268 * present in tunnel headers.
17269 * This field is valid only if tunnel VLAN PRI to CoS mapping
17271 * If tunnel VLAN PRI to CoS mapping is not enabled, then this
17272 * field shall be ignored.
17274 #define HWRM_PORT_MAC_CFG_INPUT_COS_FIELD_CFG_T_VLAN_PRI_SEL_MASK \
17276 #define HWRM_PORT_MAC_CFG_INPUT_COS_FIELD_CFG_T_VLAN_PRI_SEL_SFT \
17279 * Select inner VLAN PRI when 1 or 2 VLAN Tags are
17280 * present in the tunnel packet headers
17282 #define HWRM_PORT_MAC_CFG_INPUT_COS_FIELD_CFG_T_VLAN_PRI_SEL_INNERMOST \
17283 (UINT32_C(0x0) << 3)
17285 * Select outer VLAN Tag PRI when 2 VLAN Tags are
17286 * present in the tunnel packet headers.
17287 * No tunnel VLAN PRI shall be selected for this
17288 * configuration if only one VLAN Tag is present in
17289 * the tunnel packet headers.
17291 #define HWRM_PORT_MAC_CFG_INPUT_COS_FIELD_CFG_T_VLAN_PRI_SEL_OUTER \
17292 (UINT32_C(0x1) << 3)
17294 * Select outermost VLAN PRI when 1 or 2 VLAN Tags
17295 * are present in the tunnel packet headers
17297 #define HWRM_PORT_MAC_CFG_INPUT_COS_FIELD_CFG_T_VLAN_PRI_SEL_OUTERMOST \
17298 (UINT32_C(0x2) << 3)
17300 #define HWRM_PORT_MAC_CFG_INPUT_COS_FIELD_CFG_T_VLAN_PRI_SEL_UNSPECIFIED \
17301 (UINT32_C(0x3) << 3)
17302 #define HWRM_PORT_MAC_CFG_INPUT_COS_FIELD_CFG_T_VLAN_PRI_SEL_LAST \
17303 HWRM_PORT_MAC_CFG_INPUT_COS_FIELD_CFG_T_VLAN_PRI_SEL_UNSPECIFIED
17305 * This field shall be used to provide default CoS value
17306 * that has been configured on this port.
17307 * This field is valid only if default CoS mapping
17309 * If default CoS mapping is not enabled, then this
17310 * field shall be ignored.
17312 #define HWRM_PORT_MAC_CFG_INPUT_COS_FIELD_CFG_DEFAULT_COS_MASK \
17314 #define HWRM_PORT_MAC_CFG_INPUT_COS_FIELD_CFG_DEFAULT_COS_SFT \
17316 uint8_t unused_0[3];
17318 * This signed field specifies by how much to adjust the frequency
17319 * of sync timer updates (measured in parts per billion).
17321 int32_t ptp_freq_adj_ppb;
17322 uint8_t unused_1[4];
17325 /* hwrm_port_mac_cfg_output (size:128b/16B) */
17326 struct hwrm_port_mac_cfg_output {
17327 /* The specific error status for the command. */
17328 uint16_t error_code;
17329 /* The HWRM command request type. */
17331 /* The sequence ID from the original command. */
17333 /* The length of the response data in number of bytes. */
17336 * This is the configured maximum length of Ethernet packet
17337 * payload that is allowed to be received on the port.
17338 * This value does not include the number of bytes used by
17339 * Ethernet header and trailer (CRC).
17343 * This is the configured maximum length of Ethernet packet
17344 * payload that is allowed to be transmitted on the port.
17345 * This value does not include the number of bytes used by
17346 * Ethernet header and trailer (CRC).
17349 /* Current configuration of the IPG value. */
17351 /* Current value of the loopback value. */
17353 /* No loopback is selected. Normal operation. */
17354 #define HWRM_PORT_MAC_CFG_OUTPUT_LPBK_NONE UINT32_C(0x0)
17356 * The HW will be configured with local loopback such that
17357 * host data is sent back to the host without modification.
17359 #define HWRM_PORT_MAC_CFG_OUTPUT_LPBK_LOCAL UINT32_C(0x1)
17361 * The HW will be configured with remote loopback such that
17362 * port logic will send packets back out the transmitter that
17365 #define HWRM_PORT_MAC_CFG_OUTPUT_LPBK_REMOTE UINT32_C(0x2)
17366 #define HWRM_PORT_MAC_CFG_OUTPUT_LPBK_LAST \
17367 HWRM_PORT_MAC_CFG_OUTPUT_LPBK_REMOTE
17370 * This field is used in Output records to indicate that the output
17371 * is completely written to RAM. This field should be read as '1'
17372 * to indicate that the output has been completely written.
17373 * When writing a command completion or response to an internal processor,
17374 * the order of writes has to be such that this field is written last.
17379 /**********************
17380 * hwrm_port_mac_qcfg *
17381 **********************/
17384 /* hwrm_port_mac_qcfg_input (size:192b/24B) */
17385 struct hwrm_port_mac_qcfg_input {
17386 /* The HWRM command request type. */
17389 * The completion ring to send the completion event on. This should
17390 * be the NQ ID returned from the `nq_alloc` HWRM command.
17392 uint16_t cmpl_ring;
17394 * The sequence ID is used by the driver for tracking multiple
17395 * commands. This ID is treated as opaque data by the firmware and
17396 * the value is returned in the `hwrm_resp_hdr` upon completion.
17400 * The target ID of the command:
17401 * * 0x0-0xFFF8 - The function ID
17402 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
17403 * * 0xFFFD - Reserved for user-space HWRM interface
17406 uint16_t target_id;
17408 * A physical address pointer pointing to a host buffer that the
17409 * command's response data will be written. This can be either a host
17410 * physical address (HPA) or a guest physical address (GPA) and must
17411 * point to a physically contiguous block of memory.
17413 uint64_t resp_addr;
17414 /* Port ID of port that is to be configured. */
17416 uint8_t unused_0[6];
17419 /* hwrm_port_mac_qcfg_output (size:256b/32B) */
17420 struct hwrm_port_mac_qcfg_output {
17421 /* The specific error status for the command. */
17422 uint16_t error_code;
17423 /* The HWRM command request type. */
17425 /* The sequence ID from the original command. */
17427 /* The length of the response data in number of bytes. */
17430 * This is the configured maximum length of Ethernet packet
17431 * payload that is allowed to be received on the port.
17432 * This value does not include the number of bytes used by the
17433 * Ethernet header and trailer (CRC).
17437 * This is the configured maximum length of Ethernet packet
17438 * payload that is allowed to be transmitted on the port.
17439 * This value does not include the number of bytes used by the
17440 * Ethernet header and trailer (CRC).
17444 * The minimum IPG that will
17445 * be sent between packets by this port.
17448 /* The loopback setting for the MAC. */
17450 /* No loopback is selected. Normal operation. */
17451 #define HWRM_PORT_MAC_QCFG_OUTPUT_LPBK_NONE UINT32_C(0x0)
17453 * The HW will be configured with local loopback such that
17454 * host data is sent back to the host without modification.
17456 #define HWRM_PORT_MAC_QCFG_OUTPUT_LPBK_LOCAL UINT32_C(0x1)
17458 * The HW will be configured with remote loopback such that
17459 * port logic will send packets back out the transmitter that
17462 #define HWRM_PORT_MAC_QCFG_OUTPUT_LPBK_REMOTE UINT32_C(0x2)
17463 #define HWRM_PORT_MAC_QCFG_OUTPUT_LPBK_LAST \
17464 HWRM_PORT_MAC_QCFG_OUTPUT_LPBK_REMOTE
17466 * Priority setting for VLAN PRI to CoS mapping.
17467 * # Each XXX_pri variable shall have a unique priority value
17468 * when it is being used.
17469 * # When comparing priorities of mappings, higher value
17470 * indicates higher priority.
17471 * For example, a value of 0-3 is returned where 0 is being
17472 * the lowest priority and 3 is being the highest priority.
17473 * # If the correspoding CoS mapping is not enabled, then this
17474 * field should be ignored.
17475 * # This value indicates the normalized priority value retained
17478 uint8_t vlan_pri2cos_map_pri;
17480 * In this field, a number of CoS mappings related flags
17481 * are used to indicate configured CoS mappings.
17485 * When this bit is set to '1', the inner VLAN PRI to CoS mapping
17488 #define HWRM_PORT_MAC_QCFG_OUTPUT_FLAGS_VLAN_PRI2COS_ENABLE \
17491 * When this bit is set to '1', tunnel VLAN PRI field to
17492 * CoS mapping is enabled.
17494 #define HWRM_PORT_MAC_QCFG_OUTPUT_FLAGS_TUNNEL_PRI2COS_ENABLE \
17497 * When this bit is set to '1', the IP DSCP to CoS mapping is
17500 #define HWRM_PORT_MAC_QCFG_OUTPUT_FLAGS_IP_DSCP2COS_ENABLE \
17503 * When this bit is '1', the Out-Of-Box WoL is enabled on this
17506 #define HWRM_PORT_MAC_QCFG_OUTPUT_FLAGS_OOB_WOL_ENABLE \
17508 /* When this bit is '1', PTP is enabled for RX on this port. */
17509 #define HWRM_PORT_MAC_QCFG_OUTPUT_FLAGS_PTP_RX_TS_CAPTURE_ENABLE \
17511 /* When this bit is '1', PTP is enabled for TX on this port. */
17512 #define HWRM_PORT_MAC_QCFG_OUTPUT_FLAGS_PTP_TX_TS_CAPTURE_ENABLE \
17515 * Priority setting for tunnel VLAN PRI to CoS mapping.
17516 * # Each XXX_pri variable shall have a unique priority value
17517 * when it is being used.
17518 * # When comparing priorities of mappings, higher value
17519 * indicates higher priority.
17520 * For example, a value of 0-3 is returned where 0 is being
17521 * the lowest priority and 3 is being the highest priority.
17522 * # If the correspoding CoS mapping is not enabled, then this
17523 * field should be ignored.
17524 * # This value indicates the normalized priority value retained
17527 uint8_t tunnel_pri2cos_map_pri;
17529 * Priority setting for DSCP to PRI mapping.
17530 * # Each XXX_pri variable shall have a unique priority value
17531 * when it is being used.
17532 * # When comparing priorities of mappings, higher value
17533 * indicates higher priority.
17534 * For example, a value of 0-3 is returned where 0 is being
17535 * the lowest priority and 3 is being the highest priority.
17536 * # If the correspoding CoS mapping is not enabled, then this
17537 * field should be ignored.
17538 * # This value indicates the normalized priority value retained
17541 uint8_t dscp2pri_map_pri;
17543 * This is a 16-bit bit mask that represents the
17544 * current configuration of time stamp capture of PTP messages
17545 * on the receive side of this port.
17546 * If bit 'i' is set, then the receive side of the port
17547 * is configured to capture the time stamp of every
17548 * received PTP message with messageType field value set
17550 * If all bits are set to 0 (i.e. field value set 0),
17551 * then the receive side of the port is not configured
17552 * to capture timestamp for PTP messages.
17553 * If all bits are set to 1, then the receive side of the
17554 * port is configured to capture timestamp for all PTP
17557 uint16_t rx_ts_capture_ptp_msg_type;
17559 * This is a 16-bit bit mask that represents the
17560 * current configuration of time stamp capture of PTP messages
17561 * on the transmit side of this port.
17562 * If bit 'i' is set, then the transmit side of the port
17563 * is configured to capture the time stamp of every
17564 * received PTP message with messageType field value set
17566 * If all bits are set to 0 (i.e. field value set 0),
17567 * then the transmit side of the port is not configured
17568 * to capture timestamp for PTP messages.
17569 * If all bits are set to 1, then the transmit side of the
17570 * port is configured to capture timestamp for all PTP
17573 uint16_t tx_ts_capture_ptp_msg_type;
17574 /* Configuration of CoS fields. */
17575 uint8_t cos_field_cfg;
17577 #define HWRM_PORT_MAC_QCFG_OUTPUT_COS_FIELD_CFG_RSVD \
17580 * This field is used for selecting VLAN PRI value
17581 * based on whether one or two VLAN Tags are present in
17582 * the inner packet headers of tunneled packets or
17583 * non-tunneled packets.
17585 #define HWRM_PORT_MAC_QCFG_OUTPUT_COS_FIELD_CFG_VLAN_PRI_SEL_MASK \
17587 #define HWRM_PORT_MAC_QCFG_OUTPUT_COS_FIELD_CFG_VLAN_PRI_SEL_SFT \
17590 * Select inner VLAN PRI when 1 or 2 VLAN Tags are
17591 * present in the inner packet headers
17593 #define HWRM_PORT_MAC_QCFG_OUTPUT_COS_FIELD_CFG_VLAN_PRI_SEL_INNERMOST \
17594 (UINT32_C(0x0) << 1)
17596 * Select outer VLAN Tag PRI when 2 VLAN Tags are
17597 * present in the inner packet headers.
17598 * No VLAN PRI is selected for this configuration
17599 * if only one VLAN Tag is present in the inner
17602 #define HWRM_PORT_MAC_QCFG_OUTPUT_COS_FIELD_CFG_VLAN_PRI_SEL_OUTER \
17603 (UINT32_C(0x1) << 1)
17605 * Select outermost VLAN PRI when 1 or 2 VLAN Tags
17606 * are present in the inner packet headers
17608 #define HWRM_PORT_MAC_QCFG_OUTPUT_COS_FIELD_CFG_VLAN_PRI_SEL_OUTERMOST \
17609 (UINT32_C(0x2) << 1)
17611 #define HWRM_PORT_MAC_QCFG_OUTPUT_COS_FIELD_CFG_VLAN_PRI_SEL_UNSPECIFIED \
17612 (UINT32_C(0x3) << 1)
17613 #define HWRM_PORT_MAC_QCFG_OUTPUT_COS_FIELD_CFG_VLAN_PRI_SEL_LAST \
17614 HWRM_PORT_MAC_QCFG_OUTPUT_COS_FIELD_CFG_VLAN_PRI_SEL_UNSPECIFIED
17616 * This field is used for selecting tunnel VLAN PRI value
17617 * based on whether one or two VLAN Tags are present in
17618 * the tunnel headers of tunneled packets. This selection
17619 * does not apply to non-tunneled packets.
17621 #define HWRM_PORT_MAC_QCFG_OUTPUT_COS_FIELD_CFG_T_VLAN_PRI_SEL_MASK \
17623 #define HWRM_PORT_MAC_QCFG_OUTPUT_COS_FIELD_CFG_T_VLAN_PRI_SEL_SFT \
17626 * Select inner VLAN PRI when 1 or 2 VLAN Tags are
17627 * present in the tunnel packet headers
17629 #define HWRM_PORT_MAC_QCFG_OUTPUT_COS_FIELD_CFG_T_VLAN_PRI_SEL_INNERMOST \
17630 (UINT32_C(0x0) << 3)
17632 * Select outer VLAN Tag PRI when 2 VLAN Tags are
17633 * present in the tunnel packet headers.
17634 * No VLAN PRI is selected for this configuration
17635 * if only one VLAN Tag is present in the tunnel
17638 #define HWRM_PORT_MAC_QCFG_OUTPUT_COS_FIELD_CFG_T_VLAN_PRI_SEL_OUTER \
17639 (UINT32_C(0x1) << 3)
17641 * Select outermost VLAN PRI when 1 or 2 VLAN Tags
17642 * are present in the tunnel packet headers
17644 #define HWRM_PORT_MAC_QCFG_OUTPUT_COS_FIELD_CFG_T_VLAN_PRI_SEL_OUTERMOST \
17645 (UINT32_C(0x2) << 3)
17647 #define HWRM_PORT_MAC_QCFG_OUTPUT_COS_FIELD_CFG_T_VLAN_PRI_SEL_UNSPECIFIED \
17648 (UINT32_C(0x3) << 3)
17649 #define HWRM_PORT_MAC_QCFG_OUTPUT_COS_FIELD_CFG_T_VLAN_PRI_SEL_LAST \
17650 HWRM_PORT_MAC_QCFG_OUTPUT_COS_FIELD_CFG_T_VLAN_PRI_SEL_UNSPECIFIED
17652 * This field is used to provide default CoS value that
17653 * has been configured on this port.
17655 #define HWRM_PORT_MAC_QCFG_OUTPUT_COS_FIELD_CFG_DEFAULT_COS_MASK \
17657 #define HWRM_PORT_MAC_QCFG_OUTPUT_COS_FIELD_CFG_DEFAULT_COS_SFT \
17660 uint16_t port_svif_info;
17662 * This field specifies the source virtual interface of the port being
17663 * queried. Drivers can use this to program port svif field in the
17666 #define HWRM_PORT_MAC_QCFG_OUTPUT_PORT_SVIF_INFO_PORT_SVIF_MASK \
17668 #define HWRM_PORT_MAC_QCFG_OUTPUT_PORT_SVIF_INFO_PORT_SVIF_SFT 0
17669 /* This field specifies whether port_svif is valid or not */
17670 #define HWRM_PORT_MAC_QCFG_OUTPUT_PORT_SVIF_INFO_PORT_SVIF_VALID \
17672 uint8_t unused_2[5];
17674 * This field is used in Output records to indicate that the output
17675 * is completely written to RAM. This field should be read as '1'
17676 * to indicate that the output has been completely written.
17677 * When writing a command completion or response to an internal processor,
17678 * the order of writes has to be such that this field is written last.
17683 /**************************
17684 * hwrm_port_mac_ptp_qcfg *
17685 **************************/
17688 /* hwrm_port_mac_ptp_qcfg_input (size:192b/24B) */
17689 struct hwrm_port_mac_ptp_qcfg_input {
17690 /* The HWRM command request type. */
17693 * The completion ring to send the completion event on. This should
17694 * be the NQ ID returned from the `nq_alloc` HWRM command.
17696 uint16_t cmpl_ring;
17698 * The sequence ID is used by the driver for tracking multiple
17699 * commands. This ID is treated as opaque data by the firmware and
17700 * the value is returned in the `hwrm_resp_hdr` upon completion.
17704 * The target ID of the command:
17705 * * 0x0-0xFFF8 - The function ID
17706 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
17707 * * 0xFFFD - Reserved for user-space HWRM interface
17710 uint16_t target_id;
17712 * A physical address pointer pointing to a host buffer that the
17713 * command's response data will be written. This can be either a host
17714 * physical address (HPA) or a guest physical address (GPA) and must
17715 * point to a physically contiguous block of memory.
17717 uint64_t resp_addr;
17718 /* Port ID of port that is being queried. */
17720 uint8_t unused_0[6];
17723 /* hwrm_port_mac_ptp_qcfg_output (size:640b/80B) */
17724 struct hwrm_port_mac_ptp_qcfg_output {
17725 /* The specific error status for the command. */
17726 uint16_t error_code;
17727 /* The HWRM command request type. */
17729 /* The sequence ID from the original command. */
17731 /* The length of the response data in number of bytes. */
17734 * In this field, a number of PTP related flags
17735 * are used to indicate configured PTP capabilities.
17739 * When this bit is set to '1', the PTP related registers are
17740 * directly accessible by the host.
17742 #define HWRM_PORT_MAC_PTP_QCFG_OUTPUT_FLAGS_DIRECT_ACCESS \
17745 * When this bit is set to '1', the device supports one-step
17748 #define HWRM_PORT_MAC_PTP_QCFG_OUTPUT_FLAGS_ONE_STEP_TX_TS \
17751 * When this bit is set to '1', the PTP information is accessible
17752 * via HWRM commands.
17754 #define HWRM_PORT_MAC_PTP_QCFG_OUTPUT_FLAGS_HWRM_ACCESS \
17756 uint8_t unused_0[3];
17757 /* Offset of the PTP register for the lower 32 bits of timestamp for RX. */
17758 uint32_t rx_ts_reg_off_lower;
17759 /* Offset of the PTP register for the upper 32 bits of timestamp for RX. */
17760 uint32_t rx_ts_reg_off_upper;
17761 /* Offset of the PTP register for the sequence ID for RX. */
17762 uint32_t rx_ts_reg_off_seq_id;
17763 /* Offset of the first PTP source ID for RX. */
17764 uint32_t rx_ts_reg_off_src_id_0;
17765 /* Offset of the second PTP source ID for RX. */
17766 uint32_t rx_ts_reg_off_src_id_1;
17767 /* Offset of the third PTP source ID for RX. */
17768 uint32_t rx_ts_reg_off_src_id_2;
17769 /* Offset of the domain ID for RX. */
17770 uint32_t rx_ts_reg_off_domain_id;
17771 /* Offset of the PTP FIFO register for RX. */
17772 uint32_t rx_ts_reg_off_fifo;
17773 /* Offset of the PTP advance FIFO register for RX. */
17774 uint32_t rx_ts_reg_off_fifo_adv;
17775 /* PTP timestamp granularity for RX. */
17776 uint32_t rx_ts_reg_off_granularity;
17777 /* Offset of the PTP register for the lower 32 bits of timestamp for TX. */
17778 uint32_t tx_ts_reg_off_lower;
17779 /* Offset of the PTP register for the upper 32 bits of timestamp for TX. */
17780 uint32_t tx_ts_reg_off_upper;
17781 /* Offset of the PTP register for the sequence ID for TX. */
17782 uint32_t tx_ts_reg_off_seq_id;
17783 /* Offset of the PTP FIFO register for TX. */
17784 uint32_t tx_ts_reg_off_fifo;
17785 /* PTP timestamp granularity for TX. */
17786 uint32_t tx_ts_reg_off_granularity;
17787 uint8_t unused_1[7];
17789 * This field is used in Output records to indicate that the output
17790 * is completely written to RAM. This field should be read as '1'
17791 * to indicate that the output has been completely written.
17792 * When writing a command completion or response to an internal processor,
17793 * the order of writes has to be such that this field is written last.
17798 /* Port Tx Statistics Format */
17799 /* tx_port_stats (size:3264b/408B) */
17800 struct tx_port_stats {
17801 /* Total Number of 64 Bytes frames transmitted */
17802 uint64_t tx_64b_frames;
17803 /* Total Number of 65-127 Bytes frames transmitted */
17804 uint64_t tx_65b_127b_frames;
17805 /* Total Number of 128-255 Bytes frames transmitted */
17806 uint64_t tx_128b_255b_frames;
17807 /* Total Number of 256-511 Bytes frames transmitted */
17808 uint64_t tx_256b_511b_frames;
17809 /* Total Number of 512-1023 Bytes frames transmitted */
17810 uint64_t tx_512b_1023b_frames;
17811 /* Total Number of 1024-1518 Bytes frames transmitted */
17812 uint64_t tx_1024b_1518b_frames;
17814 * Total Number of each good VLAN (exludes FCS errors)
17815 * frame transmitted which is 1519 to 1522 bytes in length
17816 * inclusive (excluding framing bits but including FCS bytes).
17818 uint64_t tx_good_vlan_frames;
17819 /* Total Number of 1519-2047 Bytes frames transmitted */
17820 uint64_t tx_1519b_2047b_frames;
17821 /* Total Number of 2048-4095 Bytes frames transmitted */
17822 uint64_t tx_2048b_4095b_frames;
17823 /* Total Number of 4096-9216 Bytes frames transmitted */
17824 uint64_t tx_4096b_9216b_frames;
17825 /* Total Number of 9217-16383 Bytes frames transmitted */
17826 uint64_t tx_9217b_16383b_frames;
17827 /* Total Number of good frames transmitted */
17828 uint64_t tx_good_frames;
17829 /* Total Number of frames transmitted */
17830 uint64_t tx_total_frames;
17831 /* Total number of unicast frames transmitted */
17832 uint64_t tx_ucast_frames;
17833 /* Total number of multicast frames transmitted */
17834 uint64_t tx_mcast_frames;
17835 /* Total number of broadcast frames transmitted */
17836 uint64_t tx_bcast_frames;
17837 /* Total number of PAUSE control frames transmitted */
17838 uint64_t tx_pause_frames;
17840 * Total number of PFC/per-priority PAUSE
17841 * control frames transmitted
17843 uint64_t tx_pfc_frames;
17844 /* Total number of jabber frames transmitted */
17845 uint64_t tx_jabber_frames;
17846 /* Total number of frames transmitted with FCS error */
17847 uint64_t tx_fcs_err_frames;
17848 /* Total number of control frames transmitted */
17849 uint64_t tx_control_frames;
17850 /* Total number of over-sized frames transmitted */
17851 uint64_t tx_oversz_frames;
17852 /* Total number of frames with single deferral */
17853 uint64_t tx_single_dfrl_frames;
17854 /* Total number of frames with multiple deferrals */
17855 uint64_t tx_multi_dfrl_frames;
17856 /* Total number of frames with single collision */
17857 uint64_t tx_single_coll_frames;
17858 /* Total number of frames with multiple collisions */
17859 uint64_t tx_multi_coll_frames;
17860 /* Total number of frames with late collisions */
17861 uint64_t tx_late_coll_frames;
17862 /* Total number of frames with excessive collisions */
17863 uint64_t tx_excessive_coll_frames;
17864 /* Total number of fragmented frames transmitted */
17865 uint64_t tx_frag_frames;
17866 /* Total number of transmit errors */
17868 /* Total number of single VLAN tagged frames transmitted */
17869 uint64_t tx_tagged_frames;
17870 /* Total number of double VLAN tagged frames transmitted */
17871 uint64_t tx_dbl_tagged_frames;
17872 /* Total number of runt frames transmitted */
17873 uint64_t tx_runt_frames;
17874 /* Total number of TX FIFO under runs */
17875 uint64_t tx_fifo_underruns;
17877 * Total number of PFC frames with PFC enabled bit for
17878 * Pri 0 transmitted
17880 uint64_t tx_pfc_ena_frames_pri0;
17882 * Total number of PFC frames with PFC enabled bit for
17883 * Pri 1 transmitted
17885 uint64_t tx_pfc_ena_frames_pri1;
17887 * Total number of PFC frames with PFC enabled bit for
17888 * Pri 2 transmitted
17890 uint64_t tx_pfc_ena_frames_pri2;
17892 * Total number of PFC frames with PFC enabled bit for
17893 * Pri 3 transmitted
17895 uint64_t tx_pfc_ena_frames_pri3;
17897 * Total number of PFC frames with PFC enabled bit for
17898 * Pri 4 transmitted
17900 uint64_t tx_pfc_ena_frames_pri4;
17902 * Total number of PFC frames with PFC enabled bit for
17903 * Pri 5 transmitted
17905 uint64_t tx_pfc_ena_frames_pri5;
17907 * Total number of PFC frames with PFC enabled bit for
17908 * Pri 6 transmitted
17910 uint64_t tx_pfc_ena_frames_pri6;
17912 * Total number of PFC frames with PFC enabled bit for
17913 * Pri 7 transmitted
17915 uint64_t tx_pfc_ena_frames_pri7;
17916 /* Total number of EEE LPI Events on TX */
17917 uint64_t tx_eee_lpi_events;
17918 /* EEE LPI Duration Counter on TX */
17919 uint64_t tx_eee_lpi_duration;
17921 * Total number of Link Level Flow Control (LLFC) messages
17924 uint64_t tx_llfc_logical_msgs;
17925 /* Total number of HCFC messages transmitted */
17926 uint64_t tx_hcfc_msgs;
17927 /* Total number of TX collisions */
17928 uint64_t tx_total_collisions;
17929 /* Total number of transmitted bytes */
17931 /* Total number of end-to-end HOL frames */
17932 uint64_t tx_xthol_frames;
17933 /* Total Tx Drops per Port reported by STATS block */
17934 uint64_t tx_stat_discard;
17935 /* Total Tx Error Drops per Port reported by STATS block */
17936 uint64_t tx_stat_error;
17939 /* Port Rx Statistics Format */
17940 /* rx_port_stats (size:4224b/528B) */
17941 struct rx_port_stats {
17942 /* Total Number of 64 Bytes frames received */
17943 uint64_t rx_64b_frames;
17944 /* Total Number of 65-127 Bytes frames received */
17945 uint64_t rx_65b_127b_frames;
17946 /* Total Number of 128-255 Bytes frames received */
17947 uint64_t rx_128b_255b_frames;
17948 /* Total Number of 256-511 Bytes frames received */
17949 uint64_t rx_256b_511b_frames;
17950 /* Total Number of 512-1023 Bytes frames received */
17951 uint64_t rx_512b_1023b_frames;
17952 /* Total Number of 1024-1518 Bytes frames received */
17953 uint64_t rx_1024b_1518b_frames;
17955 * Total Number of each good VLAN (exludes FCS errors)
17956 * frame received which is 1519 to 1522 bytes in length
17957 * inclusive (excluding framing bits but including FCS bytes).
17959 uint64_t rx_good_vlan_frames;
17960 /* Total Number of 1519-2047 Bytes frames received */
17961 uint64_t rx_1519b_2047b_frames;
17962 /* Total Number of 2048-4095 Bytes frames received */
17963 uint64_t rx_2048b_4095b_frames;
17964 /* Total Number of 4096-9216 Bytes frames received */
17965 uint64_t rx_4096b_9216b_frames;
17966 /* Total Number of 9217-16383 Bytes frames received */
17967 uint64_t rx_9217b_16383b_frames;
17968 /* Total number of frames received */
17969 uint64_t rx_total_frames;
17970 /* Total number of unicast frames received */
17971 uint64_t rx_ucast_frames;
17972 /* Total number of multicast frames received */
17973 uint64_t rx_mcast_frames;
17974 /* Total number of broadcast frames received */
17975 uint64_t rx_bcast_frames;
17976 /* Total number of received frames with FCS error */
17977 uint64_t rx_fcs_err_frames;
17978 /* Total number of control frames received */
17979 uint64_t rx_ctrl_frames;
17980 /* Total number of PAUSE frames received */
17981 uint64_t rx_pause_frames;
17982 /* Total number of PFC frames received */
17983 uint64_t rx_pfc_frames;
17985 * Total number of frames received with an unsupported
17988 uint64_t rx_unsupported_opcode_frames;
17990 * Total number of frames received with an unsupported
17991 * DA for pause and PFC
17993 uint64_t rx_unsupported_da_pausepfc_frames;
17994 /* Total number of frames received with an unsupported SA */
17995 uint64_t rx_wrong_sa_frames;
17996 /* Total number of received packets with alignment error */
17997 uint64_t rx_align_err_frames;
17998 /* Total number of received frames with out-of-range length */
17999 uint64_t rx_oor_len_frames;
18000 /* Total number of received frames with error termination */
18001 uint64_t rx_code_err_frames;
18003 * Total number of received frames with a false carrier is
18004 * detected during idle, as defined by RX_ER samples active
18005 * and RXD is 0xE. The event is reported along with the
18006 * statistics generated on the next received frame. Only
18007 * one false carrier condition can be detected and logged
18010 * Carrier event, valid for 10M/100M speed modes only.
18012 uint64_t rx_false_carrier_frames;
18013 /* Total number of over-sized frames received */
18014 uint64_t rx_ovrsz_frames;
18015 /* Total number of jabber packets received */
18016 uint64_t rx_jbr_frames;
18017 /* Total number of received frames with MTU error */
18018 uint64_t rx_mtu_err_frames;
18019 /* Total number of received frames with CRC match */
18020 uint64_t rx_match_crc_frames;
18021 /* Total number of frames received promiscuously */
18022 uint64_t rx_promiscuous_frames;
18024 * Total number of received frames with one or two VLAN
18027 uint64_t rx_tagged_frames;
18028 /* Total number of received frames with two VLAN tags */
18029 uint64_t rx_double_tagged_frames;
18030 /* Total number of truncated frames received */
18031 uint64_t rx_trunc_frames;
18032 /* Total number of good frames (without errors) received */
18033 uint64_t rx_good_frames;
18035 * Total number of received PFC frames with transition from
18036 * XON to XOFF on Pri 0
18038 uint64_t rx_pfc_xon2xoff_frames_pri0;
18040 * Total number of received PFC frames with transition from
18041 * XON to XOFF on Pri 1
18043 uint64_t rx_pfc_xon2xoff_frames_pri1;
18045 * Total number of received PFC frames with transition from
18046 * XON to XOFF on Pri 2
18048 uint64_t rx_pfc_xon2xoff_frames_pri2;
18050 * Total number of received PFC frames with transition from
18051 * XON to XOFF on Pri 3
18053 uint64_t rx_pfc_xon2xoff_frames_pri3;
18055 * Total number of received PFC frames with transition from
18056 * XON to XOFF on Pri 4
18058 uint64_t rx_pfc_xon2xoff_frames_pri4;
18060 * Total number of received PFC frames with transition from
18061 * XON to XOFF on Pri 5
18063 uint64_t rx_pfc_xon2xoff_frames_pri5;
18065 * Total number of received PFC frames with transition from
18066 * XON to XOFF on Pri 6
18068 uint64_t rx_pfc_xon2xoff_frames_pri6;
18070 * Total number of received PFC frames with transition from
18071 * XON to XOFF on Pri 7
18073 uint64_t rx_pfc_xon2xoff_frames_pri7;
18075 * Total number of received PFC frames with PFC enabled
18078 uint64_t rx_pfc_ena_frames_pri0;
18080 * Total number of received PFC frames with PFC enabled
18083 uint64_t rx_pfc_ena_frames_pri1;
18085 * Total number of received PFC frames with PFC enabled
18088 uint64_t rx_pfc_ena_frames_pri2;
18090 * Total number of received PFC frames with PFC enabled
18093 uint64_t rx_pfc_ena_frames_pri3;
18095 * Total number of received PFC frames with PFC enabled
18098 uint64_t rx_pfc_ena_frames_pri4;
18100 * Total number of received PFC frames with PFC enabled
18103 uint64_t rx_pfc_ena_frames_pri5;
18105 * Total number of received PFC frames with PFC enabled
18108 uint64_t rx_pfc_ena_frames_pri6;
18110 * Total number of received PFC frames with PFC enabled
18113 uint64_t rx_pfc_ena_frames_pri7;
18114 /* Total Number of frames received with SCH CRC error */
18115 uint64_t rx_sch_crc_err_frames;
18116 /* Total Number of under-sized frames received */
18117 uint64_t rx_undrsz_frames;
18118 /* Total Number of fragmented frames received */
18119 uint64_t rx_frag_frames;
18120 /* Total number of RX EEE LPI Events */
18121 uint64_t rx_eee_lpi_events;
18122 /* EEE LPI Duration Counter on RX */
18123 uint64_t rx_eee_lpi_duration;
18125 * Total number of physical type Link Level Flow Control
18126 * (LLFC) messages received
18128 uint64_t rx_llfc_physical_msgs;
18130 * Total number of logical type Link Level Flow Control
18131 * (LLFC) messages received
18133 uint64_t rx_llfc_logical_msgs;
18135 * Total number of logical type Link Level Flow Control
18136 * (LLFC) messages received with CRC error
18138 uint64_t rx_llfc_msgs_with_crc_err;
18139 /* Total number of HCFC messages received */
18140 uint64_t rx_hcfc_msgs;
18141 /* Total number of HCFC messages received with CRC error */
18142 uint64_t rx_hcfc_msgs_with_crc_err;
18143 /* Total number of received bytes */
18145 /* Total number of bytes received in runt frames */
18146 uint64_t rx_runt_bytes;
18147 /* Total number of runt frames received */
18148 uint64_t rx_runt_frames;
18149 /* Total Rx Discards per Port reported by STATS block */
18150 uint64_t rx_stat_discard;
18151 uint64_t rx_stat_err;
18154 /********************
18155 * hwrm_port_qstats *
18156 ********************/
18159 /* hwrm_port_qstats_input (size:320b/40B) */
18160 struct hwrm_port_qstats_input {
18161 /* The HWRM command request type. */
18164 * The completion ring to send the completion event on. This should
18165 * be the NQ ID returned from the `nq_alloc` HWRM command.
18167 uint16_t cmpl_ring;
18169 * The sequence ID is used by the driver for tracking multiple
18170 * commands. This ID is treated as opaque data by the firmware and
18171 * the value is returned in the `hwrm_resp_hdr` upon completion.
18175 * The target ID of the command:
18176 * * 0x0-0xFFF8 - The function ID
18177 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
18178 * * 0xFFFD - Reserved for user-space HWRM interface
18181 uint16_t target_id;
18183 * A physical address pointer pointing to a host buffer that the
18184 * command's response data will be written. This can be either a host
18185 * physical address (HPA) or a guest physical address (GPA) and must
18186 * point to a physically contiguous block of memory.
18188 uint64_t resp_addr;
18189 /* Port ID of port that is being queried. */
18192 /* This value is not used to avoid backward compatibility issues. */
18193 #define HWRM_PORT_QSTATS_INPUT_FLAGS_UNUSED UINT32_C(0x0)
18195 * This bit is set to 1 when request is for a counter mask,
18196 * representing the width of each of the stats counters, rather
18197 * than counters themselves.
18199 #define HWRM_PORT_QSTATS_INPUT_FLAGS_COUNTER_MASK UINT32_C(0x1)
18200 #define HWRM_PORT_QSTATS_INPUT_FLAGS_LAST \
18201 HWRM_PORT_QSTATS_INPUT_FLAGS_COUNTER_MASK
18202 uint8_t unused_0[5];
18204 * This is the host address where
18205 * Tx port statistics will be stored
18207 uint64_t tx_stat_host_addr;
18209 * This is the host address where
18210 * Rx port statistics will be stored
18212 uint64_t rx_stat_host_addr;
18215 /* hwrm_port_qstats_output (size:128b/16B) */
18216 struct hwrm_port_qstats_output {
18217 /* The specific error status for the command. */
18218 uint16_t error_code;
18219 /* The HWRM command request type. */
18221 /* The sequence ID from the original command. */
18223 /* The length of the response data in number of bytes. */
18225 /* The size of TX port statistics block in bytes. */
18226 uint16_t tx_stat_size;
18227 /* The size of RX port statistics block in bytes. */
18228 uint16_t rx_stat_size;
18229 uint8_t unused_0[3];
18231 * This field is used in Output records to indicate that the output
18232 * is completely written to RAM. This field should be read as '1'
18233 * to indicate that the output has been completely written.
18234 * When writing a command completion or response to an internal processor,
18235 * the order of writes has to be such that this field is written last.
18240 /* Port Tx Statistics extended Format */
18241 /* tx_port_stats_ext (size:2048b/256B) */
18242 struct tx_port_stats_ext {
18243 /* Total number of tx bytes count on cos queue 0 */
18244 uint64_t tx_bytes_cos0;
18245 /* Total number of tx bytes count on cos queue 1 */
18246 uint64_t tx_bytes_cos1;
18247 /* Total number of tx bytes count on cos queue 2 */
18248 uint64_t tx_bytes_cos2;
18249 /* Total number of tx bytes count on cos queue 3 */
18250 uint64_t tx_bytes_cos3;
18251 /* Total number of tx bytes count on cos queue 4 */
18252 uint64_t tx_bytes_cos4;
18253 /* Total number of tx bytes count on cos queue 5 */
18254 uint64_t tx_bytes_cos5;
18255 /* Total number of tx bytes count on cos queue 6 */
18256 uint64_t tx_bytes_cos6;
18257 /* Total number of tx bytes count on cos queue 7 */
18258 uint64_t tx_bytes_cos7;
18259 /* Total number of tx packets count on cos queue 0 */
18260 uint64_t tx_packets_cos0;
18261 /* Total number of tx packets count on cos queue 1 */
18262 uint64_t tx_packets_cos1;
18263 /* Total number of tx packets count on cos queue 2 */
18264 uint64_t tx_packets_cos2;
18265 /* Total number of tx packets count on cos queue 3 */
18266 uint64_t tx_packets_cos3;
18267 /* Total number of tx packets count on cos queue 4 */
18268 uint64_t tx_packets_cos4;
18269 /* Total number of tx packets count on cos queue 5 */
18270 uint64_t tx_packets_cos5;
18271 /* Total number of tx packets count on cos queue 6 */
18272 uint64_t tx_packets_cos6;
18273 /* Total number of tx packets count on cos queue 7 */
18274 uint64_t tx_packets_cos7;
18275 /* time duration between transmitting a XON -> XOFF and a subsequent XOFF -> XON for priority 0 */
18276 uint64_t pfc_pri0_tx_duration_us;
18277 /* Number of times, a XON -> XOFF and XOFF -> XON transitions occur for priority 0 */
18278 uint64_t pfc_pri0_tx_transitions;
18279 /* time duration between transmitting a XON -> XOFF and a subsequent XOFF -> XON for priority 1 */
18280 uint64_t pfc_pri1_tx_duration_us;
18281 /* Number of times, a XON -> XOFF and XOFF -> XON transitions occur for priority 1 */
18282 uint64_t pfc_pri1_tx_transitions;
18283 /* time duration between transmitting a XON -> XOFF and a subsequent XOFF -> XON for priority 2 */
18284 uint64_t pfc_pri2_tx_duration_us;
18285 /* Number of times, a XON -> XOFF and XOFF -> XON transitions occur for priority 2 */
18286 uint64_t pfc_pri2_tx_transitions;
18287 /* time duration between transmitting a XON -> XOFF and a subsequent XOFF -> XON for priority 3 */
18288 uint64_t pfc_pri3_tx_duration_us;
18289 /* Number of times, a XON -> XOFF and XOFF -> XON transitions occur for priority 3 */
18290 uint64_t pfc_pri3_tx_transitions;
18291 /* time duration between transmitting a XON -> XOFF and a subsequent XOFF -> XON for priority 4 */
18292 uint64_t pfc_pri4_tx_duration_us;
18293 /* Number of times, a XON -> XOFF and XOFF -> XON transitions occur for priority 4 */
18294 uint64_t pfc_pri4_tx_transitions;
18295 /* time duration between transmitting a XON -> XOFF and a subsequent XOFF -> XON for priority 5 */
18296 uint64_t pfc_pri5_tx_duration_us;
18297 /* Number of times, a XON -> XOFF and XOFF -> XON transitions occur for priority 5 */
18298 uint64_t pfc_pri5_tx_transitions;
18299 /* time duration between transmitting a XON -> XOFF and a subsequent XOFF -> XON for priority 6 */
18300 uint64_t pfc_pri6_tx_duration_us;
18301 /* Number of times, a XON -> XOFF and XOFF -> XON transitions occur for priority 6 */
18302 uint64_t pfc_pri6_tx_transitions;
18303 /* time duration between transmitting a XON -> XOFF and a subsequent XOFF -> XON for priority 7 */
18304 uint64_t pfc_pri7_tx_duration_us;
18305 /* Number of times, a XON -> XOFF and XOFF -> XON transitions occur for priority 7 */
18306 uint64_t pfc_pri7_tx_transitions;
18309 /* Port Rx Statistics extended Format */
18310 /* rx_port_stats_ext (size:3648b/456B) */
18311 struct rx_port_stats_ext {
18312 /* Number of times link state changed to down */
18313 uint64_t link_down_events;
18314 /* Number of times the idle rings with pause bit are found */
18315 uint64_t continuous_pause_events;
18316 /* Number of times the active rings pause bit resumed back */
18317 uint64_t resume_pause_events;
18318 /* Number of times, the ROCE cos queue PFC is disabled to avoid pause flood/burst */
18319 uint64_t continuous_roce_pause_events;
18320 /* Number of times, the ROCE cos queue PFC is enabled back */
18321 uint64_t resume_roce_pause_events;
18322 /* Total number of rx bytes count on cos queue 0 */
18323 uint64_t rx_bytes_cos0;
18324 /* Total number of rx bytes count on cos queue 1 */
18325 uint64_t rx_bytes_cos1;
18326 /* Total number of rx bytes count on cos queue 2 */
18327 uint64_t rx_bytes_cos2;
18328 /* Total number of rx bytes count on cos queue 3 */
18329 uint64_t rx_bytes_cos3;
18330 /* Total number of rx bytes count on cos queue 4 */
18331 uint64_t rx_bytes_cos4;
18332 /* Total number of rx bytes count on cos queue 5 */
18333 uint64_t rx_bytes_cos5;
18334 /* Total number of rx bytes count on cos queue 6 */
18335 uint64_t rx_bytes_cos6;
18336 /* Total number of rx bytes count on cos queue 7 */
18337 uint64_t rx_bytes_cos7;
18338 /* Total number of rx packets count on cos queue 0 */
18339 uint64_t rx_packets_cos0;
18340 /* Total number of rx packets count on cos queue 1 */
18341 uint64_t rx_packets_cos1;
18342 /* Total number of rx packets count on cos queue 2 */
18343 uint64_t rx_packets_cos2;
18344 /* Total number of rx packets count on cos queue 3 */
18345 uint64_t rx_packets_cos3;
18346 /* Total number of rx packets count on cos queue 4 */
18347 uint64_t rx_packets_cos4;
18348 /* Total number of rx packets count on cos queue 5 */
18349 uint64_t rx_packets_cos5;
18350 /* Total number of rx packets count on cos queue 6 */
18351 uint64_t rx_packets_cos6;
18352 /* Total number of rx packets count on cos queue 7 */
18353 uint64_t rx_packets_cos7;
18354 /* time duration receiving a XON -> XOFF and a subsequent XOFF -> XON for priority 0 */
18355 uint64_t pfc_pri0_rx_duration_us;
18356 /* Number of times, a XON -> XOFF and XOFF -> XON transitions occur for priority 0 */
18357 uint64_t pfc_pri0_rx_transitions;
18358 /* time duration receiving a XON -> XOFF and a subsequent XOFF -> XON for priority 1 */
18359 uint64_t pfc_pri1_rx_duration_us;
18360 /* Number of times, a XON -> XOFF and XOFF -> XON transitions occur for priority 1 */
18361 uint64_t pfc_pri1_rx_transitions;
18362 /* time duration receiving a XON -> XOFF and a subsequent XOFF -> XON for priority 2 */
18363 uint64_t pfc_pri2_rx_duration_us;
18364 /* Number of times, a XON -> XOFF and XOFF -> XON transitions occur for priority 2 */
18365 uint64_t pfc_pri2_rx_transitions;
18366 /* time duration receiving a XON -> XOFF and a subsequent XOFF -> XON for priority 3 */
18367 uint64_t pfc_pri3_rx_duration_us;
18368 /* Number of times, a XON -> XOFF and XOFF -> XON transitions occur for priority 3 */
18369 uint64_t pfc_pri3_rx_transitions;
18370 /* time duration receiving a XON -> XOFF and a subsequent XOFF -> XON for priority 4 */
18371 uint64_t pfc_pri4_rx_duration_us;
18372 /* Number of times, a XON -> XOFF and XOFF -> XON transitions occur for priority 4 */
18373 uint64_t pfc_pri4_rx_transitions;
18374 /* time duration receiving a XON -> XOFF and a subsequent XOFF -> XON for priority 5 */
18375 uint64_t pfc_pri5_rx_duration_us;
18376 /* Number of times, a XON -> XOFF and XOFF -> XON transitions occur for priority 5 */
18377 uint64_t pfc_pri5_rx_transitions;
18378 /* time duration receiving a XON -> XOFF and a subsequent XOFF -> XON for priority 6 */
18379 uint64_t pfc_pri6_rx_duration_us;
18380 /* Number of times, a XON -> XOFF and XOFF -> XON transitions occur for priority 6 */
18381 uint64_t pfc_pri6_rx_transitions;
18382 /* time duration receiving a XON -> XOFF and a subsequent XOFF -> XON for priority 7 */
18383 uint64_t pfc_pri7_rx_duration_us;
18384 /* Number of times, a XON -> XOFF and XOFF -> XON transitions occur for priority 7 */
18385 uint64_t pfc_pri7_rx_transitions;
18386 /* Total number of received bits */
18388 /* The number of events where the port receive buffer was over 85% full */
18389 uint64_t rx_buffer_passed_threshold;
18391 * The number of symbol errors that wasn't corrected by FEC correction
18394 uint64_t rx_pcs_symbol_err;
18395 /* The number of corrected bits on the port according to active FEC */
18396 uint64_t rx_corrected_bits;
18397 /* Total number of rx discard bytes count on cos queue 0 */
18398 uint64_t rx_discard_bytes_cos0;
18399 /* Total number of rx discard bytes count on cos queue 1 */
18400 uint64_t rx_discard_bytes_cos1;
18401 /* Total number of rx discard bytes count on cos queue 2 */
18402 uint64_t rx_discard_bytes_cos2;
18403 /* Total number of rx discard bytes count on cos queue 3 */
18404 uint64_t rx_discard_bytes_cos3;
18405 /* Total number of rx discard bytes count on cos queue 4 */
18406 uint64_t rx_discard_bytes_cos4;
18407 /* Total number of rx discard bytes count on cos queue 5 */
18408 uint64_t rx_discard_bytes_cos5;
18409 /* Total number of rx discard bytes count on cos queue 6 */
18410 uint64_t rx_discard_bytes_cos6;
18411 /* Total number of rx discard bytes count on cos queue 7 */
18412 uint64_t rx_discard_bytes_cos7;
18413 /* Total number of rx discard packets count on cos queue 0 */
18414 uint64_t rx_discard_packets_cos0;
18415 /* Total number of rx discard packets count on cos queue 1 */
18416 uint64_t rx_discard_packets_cos1;
18417 /* Total number of rx discard packets count on cos queue 2 */
18418 uint64_t rx_discard_packets_cos2;
18419 /* Total number of rx discard packets count on cos queue 3 */
18420 uint64_t rx_discard_packets_cos3;
18421 /* Total number of rx discard packets count on cos queue 4 */
18422 uint64_t rx_discard_packets_cos4;
18423 /* Total number of rx discard packets count on cos queue 5 */
18424 uint64_t rx_discard_packets_cos5;
18425 /* Total number of rx discard packets count on cos queue 6 */
18426 uint64_t rx_discard_packets_cos6;
18427 /* Total number of rx discard packets count on cos queue 7 */
18428 uint64_t rx_discard_packets_cos7;
18432 * Port Rx Statistics extended PFC WatchDog Format.
18433 * StormDetect and StormRevert event determination is based
18434 * on an integration period and a percentage threshold.
18435 * StormDetect event - when percentage of XOFF frames received
18436 * within an integration period exceeds the configured threshold.
18437 * StormRevert event - when percentage of XON frames received
18438 * within an integration period exceeds the configured threshold.
18439 * Actual number of XOFF/XON frames for the events to be triggered
18440 * depends on both configured integration period and sampling rate.
18441 * The statistics in this structure represent counts of specified
18442 * events from the moment the feature (PFC WatchDog) is enabled via
18443 * hwrm_queue_pfc_enable_cfg call.
18445 /* rx_port_stats_ext_pfc_wd (size:5120b/640B) */
18446 struct rx_port_stats_ext_pfc_wd {
18448 * Total number of PFC WatchDog StormDetect events detected
18451 uint64_t rx_pfc_watchdog_storms_detected_pri0;
18453 * Total number of PFC WatchDog StormDetect events detected
18456 uint64_t rx_pfc_watchdog_storms_detected_pri1;
18458 * Total number of PFC WatchDog StormDetect events detected
18461 uint64_t rx_pfc_watchdog_storms_detected_pri2;
18463 * Total number of PFC WatchDog StormDetect events detected
18466 uint64_t rx_pfc_watchdog_storms_detected_pri3;
18468 * Total number of PFC WatchDog StormDetect events detected
18471 uint64_t rx_pfc_watchdog_storms_detected_pri4;
18473 * Total number of PFC WatchDog StormDetect events detected
18476 uint64_t rx_pfc_watchdog_storms_detected_pri5;
18478 * Total number of PFC WatchDog StormDetect events detected
18481 uint64_t rx_pfc_watchdog_storms_detected_pri6;
18483 * Total number of PFC WatchDog StormDetect events detected
18486 uint64_t rx_pfc_watchdog_storms_detected_pri7;
18488 * Total number of PFC WatchDog StormRevert events detected
18491 uint64_t rx_pfc_watchdog_storms_reverted_pri0;
18493 * Total number of PFC WatchDog StormRevert events detected
18496 uint64_t rx_pfc_watchdog_storms_reverted_pri1;
18498 * Total number of PFC WatchDog StormRevert events detected
18501 uint64_t rx_pfc_watchdog_storms_reverted_pri2;
18503 * Total number of PFC WatchDog StormRevert events detected
18506 uint64_t rx_pfc_watchdog_storms_reverted_pri3;
18508 * Total number of PFC WatchDog StormRevert events detected
18511 uint64_t rx_pfc_watchdog_storms_reverted_pri4;
18513 * Total number of PFC WatchDog StormRevert events detected
18516 uint64_t rx_pfc_watchdog_storms_reverted_pri5;
18518 * Total number of PFC WatchDog StormRevert events detected
18521 uint64_t rx_pfc_watchdog_storms_reverted_pri6;
18523 * Total number of PFC WatchDog StormRevert events detected
18526 uint64_t rx_pfc_watchdog_storms_reverted_pri7;
18528 * Total number of packets received during PFC watchdog storm
18531 uint64_t rx_pfc_watchdog_storms_rx_packets_pri0;
18533 * Total number of packets received during PFC watchdog storm
18536 uint64_t rx_pfc_watchdog_storms_rx_packets_pri1;
18538 * Total number of packets received during PFC watchdog storm
18541 uint64_t rx_pfc_watchdog_storms_rx_packets_pri2;
18543 * Total number of packets received during PFC watchdog storm
18546 uint64_t rx_pfc_watchdog_storms_rx_packets_pri3;
18548 * Total number of packets received during PFC watchdog storm
18551 uint64_t rx_pfc_watchdog_storms_rx_packets_pri4;
18553 * Total number of packets received during PFC watchdog storm
18556 uint64_t rx_pfc_watchdog_storms_rx_packets_pri5;
18558 * Total number of packets received during PFC watchdog storm
18561 uint64_t rx_pfc_watchdog_storms_rx_packets_pri6;
18563 * Total number of packets received during PFC watchdog storm
18566 uint64_t rx_pfc_watchdog_storms_rx_packets_pri7;
18568 * Total number of bytes received during PFC watchdog storm
18571 uint64_t rx_pfc_watchdog_storms_rx_bytes_pri0;
18573 * Total number of bytes received during PFC watchdog storm
18576 uint64_t rx_pfc_watchdog_storms_rx_bytes_pri1;
18578 * Total number of bytes received during PFC watchdog storm
18581 uint64_t rx_pfc_watchdog_storms_rx_bytes_pri2;
18583 * Total number of bytes received during PFC watchdog storm
18586 uint64_t rx_pfc_watchdog_storms_rx_bytes_pri3;
18588 * Total number of bytes received during PFC watchdog storm
18591 uint64_t rx_pfc_watchdog_storms_rx_bytes_pri4;
18593 * Total number of bytes received during PFC watchdog storm
18596 uint64_t rx_pfc_watchdog_storms_rx_bytes_pri5;
18598 * Total number of bytes received during PFC watchdog storm
18601 uint64_t rx_pfc_watchdog_storms_rx_bytes_pri6;
18603 * Total number of bytes received during PFC watchdog storm
18606 uint64_t rx_pfc_watchdog_storms_rx_bytes_pri7;
18608 * Total number of packets dropped on rx during PFC watchdog storm
18611 uint64_t rx_pfc_watchdog_storms_rx_packets_dropped_pri0;
18613 * Total number of packets dropped on rx during PFC watchdog storm
18616 uint64_t rx_pfc_watchdog_storms_rx_packets_dropped_pri1;
18618 * Total number of packets dropped on rx during PFC watchdog storm
18621 uint64_t rx_pfc_watchdog_storms_rx_packets_dropped_pri2;
18623 * Total number of packets dropped on rx during PFC watchdog storm
18626 uint64_t rx_pfc_watchdog_storms_rx_packets_dropped_pri3;
18628 * Total number of packets dropped on rx during PFC watchdog storm
18631 uint64_t rx_pfc_watchdog_storms_rx_packets_dropped_pri4;
18633 * Total number of packets dropped on rx during PFC watchdog storm
18636 uint64_t rx_pfc_watchdog_storms_rx_packets_dropped_pri5;
18638 * Total number of packets dropped on rx during PFC watchdog storm
18641 uint64_t rx_pfc_watchdog_storms_rx_packets_dropped_pri6;
18643 * Total number of packets dropped on rx during PFC watchdog storm
18646 uint64_t rx_pfc_watchdog_storms_rx_packets_dropped_pri7;
18648 * Total number of bytes dropped on rx during PFC watchdog storm
18651 uint64_t rx_pfc_watchdog_storms_rx_bytes_dropped_pri0;
18653 * Total number of bytes dropped on rx during PFC watchdog storm
18656 uint64_t rx_pfc_watchdog_storms_rx_bytes_dropped_pri1;
18658 * Total number of bytes dropped on rx during PFC watchdog storm
18661 uint64_t rx_pfc_watchdog_storms_rx_bytes_dropped_pri2;
18663 * Total number of bytes dropped on rx during PFC watchdog storm
18666 uint64_t rx_pfc_watchdog_storms_rx_bytes_dropped_pri3;
18668 * Total number of bytes dropped on rx during PFC watchdog storm
18671 uint64_t rx_pfc_watchdog_storms_rx_bytes_dropped_pri4;
18673 * Total number of bytes dropped on rx during PFC watchdog storm
18676 uint64_t rx_pfc_watchdog_storms_rx_bytes_dropped_pri5;
18678 * Total number of bytes dropped on rx during PFC watchdog storm
18681 uint64_t rx_pfc_watchdog_storms_rx_bytes_dropped_pri6;
18683 * Total number of bytes dropped on rx during PFC watchdog storm
18686 uint64_t rx_pfc_watchdog_storms_rx_bytes_dropped_pri7;
18688 * Number of packets received during last PFC watchdog storm
18691 uint64_t rx_pfc_watchdog_last_storm_rx_packets_pri0;
18693 * Number of packets received during last PFC watchdog storm
18696 uint64_t rx_pfc_watchdog_last_storm_rx_packets_pri1;
18698 * Number of packets received during last PFC watchdog storm
18701 uint64_t rx_pfc_watchdog_last_storm_rx_packets_pri2;
18703 * Number of packets received during last PFC watchdog storm
18706 uint64_t rx_pfc_watchdog_last_storm_rx_packets_pri3;
18708 * Number of packets received during last PFC watchdog storm
18711 uint64_t rx_pfc_watchdog_last_storm_rx_packets_pri4;
18713 * Number of packets received during last PFC watchdog storm
18716 uint64_t rx_pfc_watchdog_last_storm_rx_packets_pri5;
18718 * Number of packets received during last PFC watchdog storm
18721 uint64_t rx_pfc_watchdog_last_storm_rx_packets_pri6;
18723 * Number of packets received during last PFC watchdog storm
18726 uint64_t rx_pfc_watchdog_last_storm_rx_packets_pri7;
18728 * Number of bytes received during last PFC watchdog storm
18731 uint64_t rx_pfc_watchdog_last_storm_rx_bytes_pri0;
18733 * Number of bytes received during last PFC watchdog storm
18736 uint64_t rx_pfc_watchdog_last_storm_rx_bytes_pri1;
18738 * Number of bytes received during last PFC watchdog storm
18741 uint64_t rx_pfc_watchdog_last_storm_rx_bytes_pri2;
18743 * Number of bytes received during last PFC watchdog storm
18746 uint64_t rx_pfc_watchdog_last_storm_rx_bytes_pri3;
18748 * Number of bytes received during last PFC watchdog storm
18751 uint64_t rx_pfc_watchdog_last_storm_rx_bytes_pri4;
18753 * Number of bytes received during last PFC watchdog storm
18756 uint64_t rx_pfc_watchdog_last_storm_rx_bytes_pri5;
18758 * Number of bytes received during last PFC watchdog storm
18761 uint64_t rx_pfc_watchdog_last_storm_rx_bytes_pri6;
18763 * Number of bytes received during last PFC watchdog storm
18766 uint64_t rx_pfc_watchdog_last_storm_rx_bytes_pri7;
18768 * Number of packets dropped on rx during last PFC watchdog storm
18771 uint64_t rx_pfc_watchdog_last_storm_rx_packets_dropped_pri0;
18773 * Number of packets dropped on rx during last PFC watchdog storm
18776 uint64_t rx_pfc_watchdog_last_storm_rx_packets_dropped_pri1;
18778 * Number of packets dropped on rx during last PFC watchdog storm
18781 uint64_t rx_pfc_watchdog_last_storm_rx_packets_dropped_pri2;
18783 * Number of packets dropped on rx during last PFC watchdog storm
18786 uint64_t rx_pfc_watchdog_last_storm_rx_packets_dropped_pri3;
18788 * Number of packets dropped on rx during last PFC watchdog storm
18791 uint64_t rx_pfc_watchdog_last_storm_rx_packets_dropped_pri4;
18793 * Number of packets dropped on rx during last PFC watchdog storm
18796 uint64_t rx_pfc_watchdog_last_storm_rx_packets_dropped_pri5;
18798 * Number of packets dropped on rx during last PFC watchdog storm
18801 uint64_t rx_pfc_watchdog_last_storm_rx_packets_dropped_pri6;
18803 * Number of packets dropped on rx during last PFC watchdog storm
18806 uint64_t rx_pfc_watchdog_last_storm_rx_packets_dropped_pri7;
18808 * Total number of bytes dropped on rx during PFC watchdog storm
18811 uint64_t rx_pfc_watchdog_last_storm_rx_bytes_dropped_pri0;
18813 * Number of bytes dropped on rx during last PFC watchdog storm
18816 uint64_t rx_pfc_watchdog_last_storm_rx_bytes_dropped_pri1;
18818 * Number of bytes dropped on rx during last PFC watchdog storm
18821 uint64_t rx_pfc_watchdog_last_storm_rx_bytes_dropped_pri2;
18823 * Number of bytes dropped on rx during last PFC watchdog storm
18826 uint64_t rx_pfc_watchdog_last_storm_rx_bytes_dropped_pri3;
18828 * Number of bytes dropped on rx during last PFC watchdog storm
18831 uint64_t rx_pfc_watchdog_last_storm_rx_bytes_dropped_pri4;
18833 * Number of bytes dropped on rx during last PFC watchdog storm
18836 uint64_t rx_pfc_watchdog_last_storm_rx_bytes_dropped_pri5;
18838 * Number of bytes dropped on rx during last PFC watchdog storm
18841 uint64_t rx_pfc_watchdog_last_storm_rx_bytes_dropped_pri6;
18843 * Number of bytes dropped on rx during last PFC watchdog storm
18846 uint64_t rx_pfc_watchdog_last_storm_rx_bytes_dropped_pri7;
18849 /************************
18850 * hwrm_port_qstats_ext *
18851 ************************/
18854 /* hwrm_port_qstats_ext_input (size:320b/40B) */
18855 struct hwrm_port_qstats_ext_input {
18856 /* The HWRM command request type. */
18859 * The completion ring to send the completion event on. This should
18860 * be the NQ ID returned from the `nq_alloc` HWRM command.
18862 uint16_t cmpl_ring;
18864 * The sequence ID is used by the driver for tracking multiple
18865 * commands. This ID is treated as opaque data by the firmware and
18866 * the value is returned in the `hwrm_resp_hdr` upon completion.
18870 * The target ID of the command:
18871 * * 0x0-0xFFF8 - The function ID
18872 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
18873 * * 0xFFFD - Reserved for user-space HWRM interface
18876 uint16_t target_id;
18878 * A physical address pointer pointing to a host buffer that the
18879 * command's response data will be written. This can be either a host
18880 * physical address (HPA) or a guest physical address (GPA) and must
18881 * point to a physically contiguous block of memory.
18883 uint64_t resp_addr;
18884 /* Port ID of port that is being queried. */
18887 * The size of TX port extended
18888 * statistics block in bytes.
18890 uint16_t tx_stat_size;
18892 * The size of RX port extended
18893 * statistics block in bytes
18895 uint16_t rx_stat_size;
18897 /* This value is not used to avoid backward compatibility issues. */
18898 #define HWRM_PORT_QSTATS_EXT_INPUT_FLAGS_UNUSED UINT32_C(0x0)
18900 * This bit is set to 1 when request is for the counter mask,
18901 * representing width of each of the stats counters, rather than
18902 * counters themselves.
18904 #define HWRM_PORT_QSTATS_EXT_INPUT_FLAGS_COUNTER_MASK UINT32_C(0x1)
18905 #define HWRM_PORT_QSTATS_EXT_INPUT_FLAGS_LAST \
18906 HWRM_PORT_QSTATS_EXT_INPUT_FLAGS_COUNTER_MASK
18909 * This is the host address where
18910 * Tx port statistics will be stored
18912 uint64_t tx_stat_host_addr;
18914 * This is the host address where
18915 * Rx port statistics will be stored
18917 uint64_t rx_stat_host_addr;
18920 /* hwrm_port_qstats_ext_output (size:128b/16B) */
18921 struct hwrm_port_qstats_ext_output {
18922 /* The specific error status for the command. */
18923 uint16_t error_code;
18924 /* The HWRM command request type. */
18926 /* The sequence ID from the original command. */
18928 /* The length of the response data in number of bytes. */
18930 /* The size of TX port statistics block in bytes. */
18931 uint16_t tx_stat_size;
18932 /* The size of RX port statistics block in bytes. */
18933 uint16_t rx_stat_size;
18934 /* Total number of active cos queues available. */
18935 uint16_t total_active_cos_queues;
18938 * If set to 1, then this field indicates that clear
18939 * roce specific counters is supported.
18941 #define HWRM_PORT_QSTATS_EXT_OUTPUT_FLAGS_CLEAR_ROCE_COUNTERS_SUPPORTED \
18944 * This field is used in Output records to indicate that the output
18945 * is completely written to RAM. This field should be read as '1'
18946 * to indicate that the output has been completely written.
18947 * When writing a command completion or response to an internal processor,
18948 * the order of writes has to be such that this field is written last.
18953 /*******************************
18954 * hwrm_port_qstats_ext_pfc_wd *
18955 *******************************/
18958 /* hwrm_port_qstats_ext_pfc_wd_input (size:256b/32B) */
18959 struct hwrm_port_qstats_ext_pfc_wd_input {
18960 /* The HWRM command request type. */
18963 * The completion ring to send the completion event on. This should
18964 * be the NQ ID returned from the `nq_alloc` HWRM command.
18966 uint16_t cmpl_ring;
18968 * The sequence ID is used by the driver for tracking multiple
18969 * commands. This ID is treated as opaque data by the firmware and
18970 * the value is returned in the `hwrm_resp_hdr` upon completion.
18974 * The target ID of the command:
18975 * * 0x0-0xFFF8 - The function ID
18976 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
18977 * * 0xFFFD - Reserved for user-space HWRM interface
18980 uint16_t target_id;
18982 * A physical address pointer pointing to a host buffer that the
18983 * command's response data will be written. This can be either a host
18984 * physical address (HPA) or a guest physical address (GPA) and must
18985 * point to a physically contiguous block of memory.
18987 uint64_t resp_addr;
18988 /* Port ID of port that is being queried. */
18991 * The size of rx_port_stats_ext_pfc_wd
18994 uint16_t pfc_wd_stat_size;
18995 uint8_t unused_0[4];
18997 * This is the host address where
18998 * rx_port_stats_ext_pfc_wd will be stored
19000 uint64_t pfc_wd_stat_host_addr;
19003 /* hwrm_port_qstats_ext_pfc_wd_output (size:128b/16B) */
19004 struct hwrm_port_qstats_ext_pfc_wd_output {
19005 /* The specific error status for the command. */
19006 uint16_t error_code;
19007 /* The HWRM command request type. */
19009 /* The sequence ID from the original command. */
19011 /* The length of the response data in number of bytes. */
19014 * The size of rx_port_stats_ext_pfc_wd
19015 * statistics block in bytes.
19017 uint16_t pfc_wd_stat_size;
19020 * This field is used in Output records to indicate that the output
19021 * is completely written to RAM. This field should be read as '1'
19022 * to indicate that the output has been completely written.
19023 * When writing a command completion or response to an internal processor,
19024 * the order of writes has to be such that this field is written last.
19027 uint8_t unused_0[4];
19030 /*************************
19031 * hwrm_port_lpbk_qstats *
19032 *************************/
19035 /* hwrm_port_lpbk_qstats_input (size:128b/16B) */
19036 struct hwrm_port_lpbk_qstats_input {
19037 /* The HWRM command request type. */
19040 * The completion ring to send the completion event on. This should
19041 * be the NQ ID returned from the `nq_alloc` HWRM command.
19043 uint16_t cmpl_ring;
19045 * The sequence ID is used by the driver for tracking multiple
19046 * commands. This ID is treated as opaque data by the firmware and
19047 * the value is returned in the `hwrm_resp_hdr` upon completion.
19051 * The target ID of the command:
19052 * * 0x0-0xFFF8 - The function ID
19053 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
19054 * * 0xFFFD - Reserved for user-space HWRM interface
19057 uint16_t target_id;
19059 * A physical address pointer pointing to a host buffer that the
19060 * command's response data will be written. This can be either a host
19061 * physical address (HPA) or a guest physical address (GPA) and must
19062 * point to a physically contiguous block of memory.
19064 uint64_t resp_addr;
19067 /* hwrm_port_lpbk_qstats_output (size:768b/96B) */
19068 struct hwrm_port_lpbk_qstats_output {
19069 /* The specific error status for the command. */
19070 uint16_t error_code;
19071 /* The HWRM command request type. */
19073 /* The sequence ID from the original command. */
19075 /* The length of the response data in number of bytes. */
19077 /* Number of transmitted unicast frames */
19078 uint64_t lpbk_ucast_frames;
19079 /* Number of transmitted multicast frames */
19080 uint64_t lpbk_mcast_frames;
19081 /* Number of transmitted broadcast frames */
19082 uint64_t lpbk_bcast_frames;
19083 /* Number of transmitted bytes for unicast traffic */
19084 uint64_t lpbk_ucast_bytes;
19085 /* Number of transmitted bytes for multicast traffic */
19086 uint64_t lpbk_mcast_bytes;
19087 /* Number of transmitted bytes for broadcast traffic */
19088 uint64_t lpbk_bcast_bytes;
19089 /* Total Tx Drops for loopback traffic reported by STATS block */
19090 uint64_t tx_stat_discard;
19091 /* Total Tx Error Drops for loopback traffic reported by STATS block */
19092 uint64_t tx_stat_error;
19093 /* Total Rx Drops for loopback traffic reported by STATS block */
19094 uint64_t rx_stat_discard;
19095 /* Total Rx Error Drops for loopback traffic reported by STATS block */
19096 uint64_t rx_stat_error;
19097 uint8_t unused_0[7];
19099 * This field is used in Output records to indicate that the output
19100 * is completely written to RAM. This field should be read as '1'
19101 * to indicate that the output has been completely written.
19102 * When writing a command completion or response to an internal processor,
19103 * the order of writes has to be such that this field is written last.
19108 /************************
19109 * hwrm_port_ecn_qstats *
19110 ************************/
19113 /* hwrm_port_ecn_qstats_input (size:192b/24B) */
19114 struct hwrm_port_ecn_qstats_input {
19115 /* The HWRM command request type. */
19118 * The completion ring to send the completion event on. This should
19119 * be the NQ ID returned from the `nq_alloc` HWRM command.
19121 uint16_t cmpl_ring;
19123 * The sequence ID is used by the driver for tracking multiple
19124 * commands. This ID is treated as opaque data by the firmware and
19125 * the value is returned in the `hwrm_resp_hdr` upon completion.
19129 * The target ID of the command:
19130 * * 0x0-0xFFF8 - The function ID
19131 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
19132 * * 0xFFFD - Reserved for user-space HWRM interface
19135 uint16_t target_id;
19137 * A physical address pointer pointing to a host buffer that the
19138 * command's response data will be written. This can be either a host
19139 * physical address (HPA) or a guest physical address (GPA) and must
19140 * point to a physically contiguous block of memory.
19142 uint64_t resp_addr;
19144 * Port ID of port that is being queried. Unused if NIC is in
19148 uint8_t unused_0[6];
19151 /* hwrm_port_ecn_qstats_output (size:384b/48B) */
19152 struct hwrm_port_ecn_qstats_output {
19153 /* The specific error status for the command. */
19154 uint16_t error_code;
19155 /* The HWRM command request type. */
19157 /* The sequence ID from the original command. */
19159 /* The length of the response data in number of bytes. */
19161 /* Number of packets marked in CoS queue 0. */
19162 uint32_t mark_cnt_cos0;
19163 /* Number of packets marked in CoS queue 1. */
19164 uint32_t mark_cnt_cos1;
19165 /* Number of packets marked in CoS queue 2. */
19166 uint32_t mark_cnt_cos2;
19167 /* Number of packets marked in CoS queue 3. */
19168 uint32_t mark_cnt_cos3;
19169 /* Number of packets marked in CoS queue 4. */
19170 uint32_t mark_cnt_cos4;
19171 /* Number of packets marked in CoS queue 5. */
19172 uint32_t mark_cnt_cos5;
19173 /* Number of packets marked in CoS queue 6. */
19174 uint32_t mark_cnt_cos6;
19175 /* Number of packets marked in CoS queue 7. */
19176 uint32_t mark_cnt_cos7;
19178 * Bitmask that indicates which CoS queues have ECN marking enabled.
19179 * Bit i corresponds to CoS queue i.
19182 uint8_t unused_0[6];
19184 * This field is used in Output records to indicate that the output
19185 * is completely written to RAM. This field should be read as '1'
19186 * to indicate that the output has been completely written.
19187 * When writing a command completion or response to an internal processor,
19188 * the order of writes has to be such that this field is written last.
19193 /***********************
19194 * hwrm_port_clr_stats *
19195 ***********************/
19198 /* hwrm_port_clr_stats_input (size:192b/24B) */
19199 struct hwrm_port_clr_stats_input {
19200 /* The HWRM command request type. */
19203 * The completion ring to send the completion event on. This should
19204 * be the NQ ID returned from the `nq_alloc` HWRM command.
19206 uint16_t cmpl_ring;
19208 * The sequence ID is used by the driver for tracking multiple
19209 * commands. This ID is treated as opaque data by the firmware and
19210 * the value is returned in the `hwrm_resp_hdr` upon completion.
19214 * The target ID of the command:
19215 * * 0x0-0xFFF8 - The function ID
19216 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
19217 * * 0xFFFD - Reserved for user-space HWRM interface
19220 uint16_t target_id;
19222 * A physical address pointer pointing to a host buffer that the
19223 * command's response data will be written. This can be either a host
19224 * physical address (HPA) or a guest physical address (GPA) and must
19225 * point to a physically contiguous block of memory.
19227 uint64_t resp_addr;
19228 /* Port ID of port that is being queried. */
19232 * If set to 1, then this field indicates clear the following RoCE
19233 * specific counters.
19234 * RoCE associated TX/RX cos counters
19235 * CNP associated TX/RX cos counters
19236 * RoCE/CNP specific TX/RX flow counters
19237 * Firmware will determine the RoCE/CNP cos queue based on qos profile.
19238 * This flag is honored only when RoCE is enabled on that port.
19240 #define HWRM_PORT_CLR_STATS_INPUT_FLAGS_ROCE_COUNTERS UINT32_C(0x1)
19241 uint8_t unused_0[5];
19244 /* hwrm_port_clr_stats_output (size:128b/16B) */
19245 struct hwrm_port_clr_stats_output {
19246 /* The specific error status for the command. */
19247 uint16_t error_code;
19248 /* The HWRM command request type. */
19250 /* The sequence ID from the original command. */
19252 /* The length of the response data in number of bytes. */
19254 uint8_t unused_0[7];
19256 * This field is used in Output records to indicate that the output
19257 * is completely written to RAM. This field should be read as '1'
19258 * to indicate that the output has been completely written.
19259 * When writing a command completion or response to an internal processor,
19260 * the order of writes has to be such that this field is written last.
19265 /***********************
19266 * hwrm_port_phy_qcaps *
19267 ***********************/
19270 /* hwrm_port_phy_qcaps_input (size:192b/24B) */
19271 struct hwrm_port_phy_qcaps_input {
19272 /* The HWRM command request type. */
19275 * The completion ring to send the completion event on. This should
19276 * be the NQ ID returned from the `nq_alloc` HWRM command.
19278 uint16_t cmpl_ring;
19280 * The sequence ID is used by the driver for tracking multiple
19281 * commands. This ID is treated as opaque data by the firmware and
19282 * the value is returned in the `hwrm_resp_hdr` upon completion.
19286 * The target ID of the command:
19287 * * 0x0-0xFFF8 - The function ID
19288 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
19289 * * 0xFFFD - Reserved for user-space HWRM interface
19292 uint16_t target_id;
19294 * A physical address pointer pointing to a host buffer that the
19295 * command's response data will be written. This can be either a host
19296 * physical address (HPA) or a guest physical address (GPA) and must
19297 * point to a physically contiguous block of memory.
19299 uint64_t resp_addr;
19300 /* Port ID of port that is being queried. */
19302 uint8_t unused_0[6];
19305 /* hwrm_port_phy_qcaps_output (size:256b/32B) */
19306 struct hwrm_port_phy_qcaps_output {
19307 /* The specific error status for the command. */
19308 uint16_t error_code;
19309 /* The HWRM command request type. */
19311 /* The sequence ID from the original command. */
19313 /* The length of the response data in number of bytes. */
19315 /* PHY capability flags */
19318 * If set to 1, then this field indicates that the
19319 * link is capable of supporting EEE.
19321 #define HWRM_PORT_PHY_QCAPS_OUTPUT_FLAGS_EEE_SUPPORTED \
19324 * If set to 1, then this field indicates that the
19325 * PHY is capable of supporting external loopback.
19327 #define HWRM_PORT_PHY_QCAPS_OUTPUT_FLAGS_EXTERNAL_LPBK_SUPPORTED \
19330 * If set to 1, then this field indicates that the
19331 * PHY is capable of supporting loopback in autoneg mode.
19333 #define HWRM_PORT_PHY_QCAPS_OUTPUT_FLAGS_AUTONEG_LPBK_SUPPORTED \
19336 * Indicates if the configuration of shared PHY settings is supported.
19337 * In cases where a physical port is shared by multiple functions
19338 * (e.g. NPAR, multihost, etc), the configuration of PHY
19339 * settings may not be allowed. Callers to HWRM_PORT_PHY_CFG will
19340 * get an HWRM_ERR_CODE_RESOURCE_ACCESS_DENIED error in this case.
19342 #define HWRM_PORT_PHY_QCAPS_OUTPUT_FLAGS_SHARED_PHY_CFG_SUPPORTED \
19345 * If set to 1, it indicates that the port counters and extended
19346 * port counters will not reset when the firmware shuts down or
19347 * resets the PHY. These counters will only be reset during power
19348 * cycle or by calling HWRM_PORT_CLR_STATS.
19349 * If set to 0, the state of the counters is unspecified when
19350 * firmware shuts down or resets the PHY.
19352 #define HWRM_PORT_PHY_QCAPS_OUTPUT_FLAGS_CUMULATIVE_COUNTERS_ON_RESET \
19355 * Reserved field. The HWRM shall set this field to 0.
19356 * An HWRM client shall ignore this field.
19358 #define HWRM_PORT_PHY_QCAPS_OUTPUT_FLAGS_RSVD1_MASK \
19360 #define HWRM_PORT_PHY_QCAPS_OUTPUT_FLAGS_RSVD1_SFT \
19362 /* Number of front panel ports for this device. */
19364 /* Not supported or unknown */
19365 #define HWRM_PORT_PHY_QCAPS_OUTPUT_PORT_CNT_UNKNOWN UINT32_C(0x0)
19366 /* single port device */
19367 #define HWRM_PORT_PHY_QCAPS_OUTPUT_PORT_CNT_1 UINT32_C(0x1)
19368 /* 2-port device */
19369 #define HWRM_PORT_PHY_QCAPS_OUTPUT_PORT_CNT_2 UINT32_C(0x2)
19370 /* 3-port device */
19371 #define HWRM_PORT_PHY_QCAPS_OUTPUT_PORT_CNT_3 UINT32_C(0x3)
19372 /* 4-port device */
19373 #define HWRM_PORT_PHY_QCAPS_OUTPUT_PORT_CNT_4 UINT32_C(0x4)
19374 #define HWRM_PORT_PHY_QCAPS_OUTPUT_PORT_CNT_LAST \
19375 HWRM_PORT_PHY_QCAPS_OUTPUT_PORT_CNT_4
19377 * This is a bit mask to indicate what speeds are supported
19378 * as forced speeds on this link.
19379 * For each speed that can be forced on this link, the
19380 * corresponding mask bit shall be set to '1'.
19382 uint16_t supported_speeds_force_mode;
19383 /* 100Mb link speed (Half-duplex) */
19384 #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_FORCE_MODE_100MBHD \
19386 /* 100Mb link speed (Full-duplex) */
19387 #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_FORCE_MODE_100MB \
19389 /* 1Gb link speed (Half-duplex) */
19390 #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_FORCE_MODE_1GBHD \
19392 /* 1Gb link speed (Full-duplex) */
19393 #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_FORCE_MODE_1GB \
19395 /* 2Gb link speed */
19396 #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_FORCE_MODE_2GB \
19398 /* 25Gb link speed */
19399 #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_FORCE_MODE_2_5GB \
19401 /* 10Gb link speed */
19402 #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_FORCE_MODE_10GB \
19404 /* 20Gb link speed */
19405 #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_FORCE_MODE_20GB \
19407 /* 25Gb link speed */
19408 #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_FORCE_MODE_25GB \
19410 /* 40Gb link speed */
19411 #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_FORCE_MODE_40GB \
19413 /* 50Gb link speed */
19414 #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_FORCE_MODE_50GB \
19416 /* 100Gb link speed */
19417 #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_FORCE_MODE_100GB \
19419 /* 10Mb link speed (Half-duplex) */
19420 #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_FORCE_MODE_10MBHD \
19422 /* 10Mb link speed (Full-duplex) */
19423 #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_FORCE_MODE_10MB \
19426 * This is a bit mask to indicate what speeds are supported
19427 * for autonegotiation on this link.
19428 * For each speed that can be autonegotiated on this link, the
19429 * corresponding mask bit shall be set to '1'.
19431 uint16_t supported_speeds_auto_mode;
19432 /* 100Mb link speed (Half-duplex) */
19433 #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_AUTO_MODE_100MBHD \
19435 /* 100Mb link speed (Full-duplex) */
19436 #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_AUTO_MODE_100MB \
19438 /* 1Gb link speed (Half-duplex) */
19439 #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_AUTO_MODE_1GBHD \
19441 /* 1Gb link speed (Full-duplex) */
19442 #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_AUTO_MODE_1GB \
19444 /* 2Gb link speed */
19445 #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_AUTO_MODE_2GB \
19447 /* 25Gb link speed */
19448 #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_AUTO_MODE_2_5GB \
19450 /* 10Gb link speed */
19451 #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_AUTO_MODE_10GB \
19453 /* 20Gb link speed */
19454 #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_AUTO_MODE_20GB \
19456 /* 25Gb link speed */
19457 #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_AUTO_MODE_25GB \
19459 /* 40Gb link speed */
19460 #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_AUTO_MODE_40GB \
19462 /* 50Gb link speed */
19463 #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_AUTO_MODE_50GB \
19465 /* 100Gb link speed */
19466 #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_AUTO_MODE_100GB \
19468 /* 10Mb link speed (Half-duplex) */
19469 #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_AUTO_MODE_10MBHD \
19471 /* 10Mb link speed (Full-duplex) */
19472 #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_AUTO_MODE_10MB \
19475 * This is a bit mask to indicate what speeds are supported
19476 * for EEE on this link.
19477 * For each speed that can be autonegotiated when EEE is enabled
19478 * on this link, the corresponding mask bit shall be set to '1'.
19479 * This field is only valid when the eee_suppotred is set to '1'.
19481 uint16_t supported_speeds_eee_mode;
19483 #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_EEE_MODE_RSVD1 \
19485 /* 100Mb link speed (Full-duplex) */
19486 #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_EEE_MODE_100MB \
19489 #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_EEE_MODE_RSVD2 \
19491 /* 1Gb link speed (Full-duplex) */
19492 #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_EEE_MODE_1GB \
19495 #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_EEE_MODE_RSVD3 \
19498 #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_EEE_MODE_RSVD4 \
19500 /* 10Gb link speed */
19501 #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_EEE_MODE_10GB \
19503 uint32_t tx_lpi_timer_low;
19505 * The lowest value of TX LPI timer that can be set on this link
19506 * when EEE is enabled. This value is in microseconds.
19507 * This field is valid only when_eee_supported is set to '1'.
19509 #define HWRM_PORT_PHY_QCAPS_OUTPUT_TX_LPI_TIMER_LOW_MASK \
19511 #define HWRM_PORT_PHY_QCAPS_OUTPUT_TX_LPI_TIMER_LOW_SFT 0
19513 * Reserved field. The HWRM shall set this field to 0.
19514 * An HWRM client shall ignore this field.
19516 #define HWRM_PORT_PHY_QCAPS_OUTPUT_RSVD2_MASK \
19517 UINT32_C(0xff000000)
19518 #define HWRM_PORT_PHY_QCAPS_OUTPUT_RSVD2_SFT 24
19519 uint32_t valid_tx_lpi_timer_high;
19521 * The highest value of TX LPI timer that can be set on this link
19522 * when EEE is enabled. This value is in microseconds.
19523 * This field is valid only when_eee_supported is set to '1'.
19525 #define HWRM_PORT_PHY_QCAPS_OUTPUT_TX_LPI_TIMER_HIGH_MASK \
19527 #define HWRM_PORT_PHY_QCAPS_OUTPUT_TX_LPI_TIMER_HIGH_SFT 0
19529 * Reserved field. The HWRM shall set this field to 0.
19530 * An HWRM client shall ignore this field.
19532 #define HWRM_PORT_PHY_QCAPS_OUTPUT_RSVD_MASK \
19533 UINT32_C(0xff000000)
19534 #define HWRM_PORT_PHY_QCAPS_OUTPUT_RSVD_SFT 24
19536 * This field is used to advertise which PAM4 speeds are supported
19539 uint16_t supported_pam4_speeds_auto_mode;
19540 #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_PAM4_SPEEDS_AUTO_MODE_50G \
19542 #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_PAM4_SPEEDS_AUTO_MODE_100G \
19544 #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_PAM4_SPEEDS_AUTO_MODE_200G \
19547 * This field is used to advertise which PAM4 speeds are supported
19550 uint16_t supported_pam4_speeds_force_mode;
19551 #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_PAM4_SPEEDS_FORCE_MODE_50G \
19553 #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_PAM4_SPEEDS_FORCE_MODE_100G \
19555 #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_PAM4_SPEEDS_FORCE_MODE_200G \
19557 uint8_t unused_0[3];
19559 * This field is used in Output records to indicate that the output
19560 * is completely written to RAM. This field should be read as '1'
19561 * to indicate that the output has been completely written.
19562 * When writing a command completion or response to an internal processor,
19563 * the order of writes has to be such that this field is written last.
19568 /****************************
19569 * hwrm_port_phy_mdio_write *
19570 ****************************/
19573 /* hwrm_port_phy_mdio_write_input (size:320b/40B) */
19574 struct hwrm_port_phy_mdio_write_input {
19575 /* The HWRM command request type. */
19578 * The completion ring to send the completion event on. This should
19579 * be the NQ ID returned from the `nq_alloc` HWRM command.
19581 uint16_t cmpl_ring;
19583 * The sequence ID is used by the driver for tracking multiple
19584 * commands. This ID is treated as opaque data by the firmware and
19585 * the value is returned in the `hwrm_resp_hdr` upon completion.
19589 * The target ID of the command:
19590 * * 0x0-0xFFF8 - The function ID
19591 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
19592 * * 0xFFFD - Reserved for user-space HWRM interface
19595 uint16_t target_id;
19597 * A physical address pointer pointing to a host buffer that the
19598 * command's response data will be written. This can be either a host
19599 * physical address (HPA) or a guest physical address (GPA) and must
19600 * point to a physically contiguous block of memory.
19602 uint64_t resp_addr;
19603 /* Reserved for future use. */
19604 uint32_t unused_0[2];
19605 /* Port ID of port. */
19607 /* If phy_address is 0xFF, port_id will be used to derive phy_addr. */
19609 /* 8-bit device address. */
19611 /* 16-bit register address. */
19613 /* 16-bit register data. */
19616 * When this bit is set to 1 a Clause 45 mdio access is done.
19617 * when this bit is set to 0 a Clause 22 mdio access is done.
19621 uint8_t unused_1[7];
19624 /* hwrm_port_phy_mdio_write_output (size:128b/16B) */
19625 struct hwrm_port_phy_mdio_write_output {
19626 /* The specific error status for the command. */
19627 uint16_t error_code;
19628 /* The HWRM command request type. */
19630 /* The sequence ID from the original command. */
19632 /* The length of the response data in number of bytes. */
19634 uint8_t unused_0[7];
19636 * This field is used in Output records to indicate that the output
19637 * is completely written to RAM. This field should be read as '1'
19638 * to indicate that the output has been completely written.
19639 * When writing a command completion or response to an internal processor,
19640 * the order of writes has to be such that this field is written last.
19645 /***************************
19646 * hwrm_port_phy_mdio_read *
19647 ***************************/
19650 /* hwrm_port_phy_mdio_read_input (size:256b/32B) */
19651 struct hwrm_port_phy_mdio_read_input {
19652 /* The HWRM command request type. */
19655 * The completion ring to send the completion event on. This should
19656 * be the NQ ID returned from the `nq_alloc` HWRM command.
19658 uint16_t cmpl_ring;
19660 * The sequence ID is used by the driver for tracking multiple
19661 * commands. This ID is treated as opaque data by the firmware and
19662 * the value is returned in the `hwrm_resp_hdr` upon completion.
19666 * The target ID of the command:
19667 * * 0x0-0xFFF8 - The function ID
19668 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
19669 * * 0xFFFD - Reserved for user-space HWRM interface
19672 uint16_t target_id;
19674 * A physical address pointer pointing to a host buffer that the
19675 * command's response data will be written. This can be either a host
19676 * physical address (HPA) or a guest physical address (GPA) and must
19677 * point to a physically contiguous block of memory.
19679 uint64_t resp_addr;
19680 /* Reserved for future use. */
19681 uint32_t unused_0[2];
19682 /* Port ID of port. */
19684 /* If phy_address is 0xFF, port_id will be used to derive phy_addr. */
19686 /* 8-bit device address. */
19688 /* 16-bit register address. */
19691 * When this bit is set to 1 a Clause 45 mdio access is done.
19692 * when this bit is set to 0 a Clause 22 mdio access is done.
19699 /* hwrm_port_phy_mdio_read_output (size:128b/16B) */
19700 struct hwrm_port_phy_mdio_read_output {
19701 /* The specific error status for the command. */
19702 uint16_t error_code;
19703 /* The HWRM command request type. */
19705 /* The sequence ID from the original command. */
19707 /* The length of the response data in number of bytes. */
19709 /* 16-bit register data. */
19711 uint8_t unused_0[5];
19713 * This field is used in Output records to indicate that the output
19714 * is completely written to RAM. This field should be read as '1'
19715 * to indicate that the output has been completely written.
19716 * When writing a command completion or response to an internal processor,
19717 * the order of writes has to be such that this field is written last.
19722 /*********************
19723 * hwrm_port_led_cfg *
19724 *********************/
19727 /* hwrm_port_led_cfg_input (size:512b/64B) */
19728 struct hwrm_port_led_cfg_input {
19729 /* The HWRM command request type. */
19732 * The completion ring to send the completion event on. This should
19733 * be the NQ ID returned from the `nq_alloc` HWRM command.
19735 uint16_t cmpl_ring;
19737 * The sequence ID is used by the driver for tracking multiple
19738 * commands. This ID is treated as opaque data by the firmware and
19739 * the value is returned in the `hwrm_resp_hdr` upon completion.
19743 * The target ID of the command:
19744 * * 0x0-0xFFF8 - The function ID
19745 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
19746 * * 0xFFFD - Reserved for user-space HWRM interface
19749 uint16_t target_id;
19751 * A physical address pointer pointing to a host buffer that the
19752 * command's response data will be written. This can be either a host
19753 * physical address (HPA) or a guest physical address (GPA) and must
19754 * point to a physically contiguous block of memory.
19756 uint64_t resp_addr;
19759 * This bit must be '1' for the led0_id field to be
19762 #define HWRM_PORT_LED_CFG_INPUT_ENABLES_LED0_ID \
19765 * This bit must be '1' for the led0_state field to be
19768 #define HWRM_PORT_LED_CFG_INPUT_ENABLES_LED0_STATE \
19771 * This bit must be '1' for the led0_color field to be
19774 #define HWRM_PORT_LED_CFG_INPUT_ENABLES_LED0_COLOR \
19777 * This bit must be '1' for the led0_blink_on field to be
19780 #define HWRM_PORT_LED_CFG_INPUT_ENABLES_LED0_BLINK_ON \
19783 * This bit must be '1' for the led0_blink_off field to be
19786 #define HWRM_PORT_LED_CFG_INPUT_ENABLES_LED0_BLINK_OFF \
19789 * This bit must be '1' for the led0_group_id field to be
19792 #define HWRM_PORT_LED_CFG_INPUT_ENABLES_LED0_GROUP_ID \
19795 * This bit must be '1' for the led1_id field to be
19798 #define HWRM_PORT_LED_CFG_INPUT_ENABLES_LED1_ID \
19801 * This bit must be '1' for the led1_state field to be
19804 #define HWRM_PORT_LED_CFG_INPUT_ENABLES_LED1_STATE \
19807 * This bit must be '1' for the led1_color field to be
19810 #define HWRM_PORT_LED_CFG_INPUT_ENABLES_LED1_COLOR \
19813 * This bit must be '1' for the led1_blink_on field to be
19816 #define HWRM_PORT_LED_CFG_INPUT_ENABLES_LED1_BLINK_ON \
19819 * This bit must be '1' for the led1_blink_off field to be
19822 #define HWRM_PORT_LED_CFG_INPUT_ENABLES_LED1_BLINK_OFF \
19825 * This bit must be '1' for the led1_group_id field to be
19828 #define HWRM_PORT_LED_CFG_INPUT_ENABLES_LED1_GROUP_ID \
19831 * This bit must be '1' for the led2_id field to be
19834 #define HWRM_PORT_LED_CFG_INPUT_ENABLES_LED2_ID \
19837 * This bit must be '1' for the led2_state field to be
19840 #define HWRM_PORT_LED_CFG_INPUT_ENABLES_LED2_STATE \
19843 * This bit must be '1' for the led2_color field to be
19846 #define HWRM_PORT_LED_CFG_INPUT_ENABLES_LED2_COLOR \
19849 * This bit must be '1' for the led2_blink_on field to be
19852 #define HWRM_PORT_LED_CFG_INPUT_ENABLES_LED2_BLINK_ON \
19855 * This bit must be '1' for the led2_blink_off field to be
19858 #define HWRM_PORT_LED_CFG_INPUT_ENABLES_LED2_BLINK_OFF \
19861 * This bit must be '1' for the led2_group_id field to be
19864 #define HWRM_PORT_LED_CFG_INPUT_ENABLES_LED2_GROUP_ID \
19867 * This bit must be '1' for the led3_id field to be
19870 #define HWRM_PORT_LED_CFG_INPUT_ENABLES_LED3_ID \
19873 * This bit must be '1' for the led3_state field to be
19876 #define HWRM_PORT_LED_CFG_INPUT_ENABLES_LED3_STATE \
19879 * This bit must be '1' for the led3_color field to be
19882 #define HWRM_PORT_LED_CFG_INPUT_ENABLES_LED3_COLOR \
19885 * This bit must be '1' for the led3_blink_on field to be
19888 #define HWRM_PORT_LED_CFG_INPUT_ENABLES_LED3_BLINK_ON \
19891 * This bit must be '1' for the led3_blink_off field to be
19894 #define HWRM_PORT_LED_CFG_INPUT_ENABLES_LED3_BLINK_OFF \
19897 * This bit must be '1' for the led3_group_id field to be
19900 #define HWRM_PORT_LED_CFG_INPUT_ENABLES_LED3_GROUP_ID \
19902 /* Port ID of port whose LEDs are configured. */
19905 * The number of LEDs that are being configured.
19906 * Up to 4 LEDs can be configured with this command.
19909 /* Reserved field. */
19911 /* An identifier for the LED #0. */
19913 /* The requested state of the LED #0. */
19914 uint8_t led0_state;
19915 /* Default state of the LED */
19916 #define HWRM_PORT_LED_CFG_INPUT_LED0_STATE_DEFAULT UINT32_C(0x0)
19918 #define HWRM_PORT_LED_CFG_INPUT_LED0_STATE_OFF UINT32_C(0x1)
19920 #define HWRM_PORT_LED_CFG_INPUT_LED0_STATE_ON UINT32_C(0x2)
19922 #define HWRM_PORT_LED_CFG_INPUT_LED0_STATE_BLINK UINT32_C(0x3)
19923 /* Blink Alternately */
19924 #define HWRM_PORT_LED_CFG_INPUT_LED0_STATE_BLINKALT UINT32_C(0x4)
19925 #define HWRM_PORT_LED_CFG_INPUT_LED0_STATE_LAST \
19926 HWRM_PORT_LED_CFG_INPUT_LED0_STATE_BLINKALT
19927 /* The requested color of LED #0. */
19928 uint8_t led0_color;
19930 #define HWRM_PORT_LED_CFG_INPUT_LED0_COLOR_DEFAULT UINT32_C(0x0)
19932 #define HWRM_PORT_LED_CFG_INPUT_LED0_COLOR_AMBER UINT32_C(0x1)
19934 #define HWRM_PORT_LED_CFG_INPUT_LED0_COLOR_GREEN UINT32_C(0x2)
19935 /* Green or Amber */
19936 #define HWRM_PORT_LED_CFG_INPUT_LED0_COLOR_GREENAMBER UINT32_C(0x3)
19937 #define HWRM_PORT_LED_CFG_INPUT_LED0_COLOR_LAST \
19938 HWRM_PORT_LED_CFG_INPUT_LED0_COLOR_GREENAMBER
19941 * If the LED #0 state is "blink" or "blinkalt", then
19942 * this field represents the requested time in milliseconds
19943 * to keep LED on between cycles.
19945 uint16_t led0_blink_on;
19947 * If the LED #0 state is "blink" or "blinkalt", then
19948 * this field represents the requested time in milliseconds
19949 * to keep LED off between cycles.
19951 uint16_t led0_blink_off;
19953 * An identifier for the group of LEDs that LED #0 belongs
19955 * If set to 0, then the LED #0 shall not be grouped and
19956 * shall be treated as an individual resource.
19957 * For all other non-zero values of this field, LED #0 shall
19958 * be grouped together with the LEDs with the same group ID
19961 uint8_t led0_group_id;
19962 /* Reserved field. */
19964 /* An identifier for the LED #1. */
19966 /* The requested state of the LED #1. */
19967 uint8_t led1_state;
19968 /* Default state of the LED */
19969 #define HWRM_PORT_LED_CFG_INPUT_LED1_STATE_DEFAULT UINT32_C(0x0)
19971 #define HWRM_PORT_LED_CFG_INPUT_LED1_STATE_OFF UINT32_C(0x1)
19973 #define HWRM_PORT_LED_CFG_INPUT_LED1_STATE_ON UINT32_C(0x2)
19975 #define HWRM_PORT_LED_CFG_INPUT_LED1_STATE_BLINK UINT32_C(0x3)
19976 /* Blink Alternately */
19977 #define HWRM_PORT_LED_CFG_INPUT_LED1_STATE_BLINKALT UINT32_C(0x4)
19978 #define HWRM_PORT_LED_CFG_INPUT_LED1_STATE_LAST \
19979 HWRM_PORT_LED_CFG_INPUT_LED1_STATE_BLINKALT
19980 /* The requested color of LED #1. */
19981 uint8_t led1_color;
19983 #define HWRM_PORT_LED_CFG_INPUT_LED1_COLOR_DEFAULT UINT32_C(0x0)
19985 #define HWRM_PORT_LED_CFG_INPUT_LED1_COLOR_AMBER UINT32_C(0x1)
19987 #define HWRM_PORT_LED_CFG_INPUT_LED1_COLOR_GREEN UINT32_C(0x2)
19988 /* Green or Amber */
19989 #define HWRM_PORT_LED_CFG_INPUT_LED1_COLOR_GREENAMBER UINT32_C(0x3)
19990 #define HWRM_PORT_LED_CFG_INPUT_LED1_COLOR_LAST \
19991 HWRM_PORT_LED_CFG_INPUT_LED1_COLOR_GREENAMBER
19994 * If the LED #1 state is "blink" or "blinkalt", then
19995 * this field represents the requested time in milliseconds
19996 * to keep LED on between cycles.
19998 uint16_t led1_blink_on;
20000 * If the LED #1 state is "blink" or "blinkalt", then
20001 * this field represents the requested time in milliseconds
20002 * to keep LED off between cycles.
20004 uint16_t led1_blink_off;
20006 * An identifier for the group of LEDs that LED #1 belongs
20008 * If set to 0, then the LED #1 shall not be grouped and
20009 * shall be treated as an individual resource.
20010 * For all other non-zero values of this field, LED #1 shall
20011 * be grouped together with the LEDs with the same group ID
20014 uint8_t led1_group_id;
20015 /* Reserved field. */
20017 /* An identifier for the LED #2. */
20019 /* The requested state of the LED #2. */
20020 uint8_t led2_state;
20021 /* Default state of the LED */
20022 #define HWRM_PORT_LED_CFG_INPUT_LED2_STATE_DEFAULT UINT32_C(0x0)
20024 #define HWRM_PORT_LED_CFG_INPUT_LED2_STATE_OFF UINT32_C(0x1)
20026 #define HWRM_PORT_LED_CFG_INPUT_LED2_STATE_ON UINT32_C(0x2)
20028 #define HWRM_PORT_LED_CFG_INPUT_LED2_STATE_BLINK UINT32_C(0x3)
20029 /* Blink Alternately */
20030 #define HWRM_PORT_LED_CFG_INPUT_LED2_STATE_BLINKALT UINT32_C(0x4)
20031 #define HWRM_PORT_LED_CFG_INPUT_LED2_STATE_LAST \
20032 HWRM_PORT_LED_CFG_INPUT_LED2_STATE_BLINKALT
20033 /* The requested color of LED #2. */
20034 uint8_t led2_color;
20036 #define HWRM_PORT_LED_CFG_INPUT_LED2_COLOR_DEFAULT UINT32_C(0x0)
20038 #define HWRM_PORT_LED_CFG_INPUT_LED2_COLOR_AMBER UINT32_C(0x1)
20040 #define HWRM_PORT_LED_CFG_INPUT_LED2_COLOR_GREEN UINT32_C(0x2)
20041 /* Green or Amber */
20042 #define HWRM_PORT_LED_CFG_INPUT_LED2_COLOR_GREENAMBER UINT32_C(0x3)
20043 #define HWRM_PORT_LED_CFG_INPUT_LED2_COLOR_LAST \
20044 HWRM_PORT_LED_CFG_INPUT_LED2_COLOR_GREENAMBER
20047 * If the LED #2 state is "blink" or "blinkalt", then
20048 * this field represents the requested time in milliseconds
20049 * to keep LED on between cycles.
20051 uint16_t led2_blink_on;
20053 * If the LED #2 state is "blink" or "blinkalt", then
20054 * this field represents the requested time in milliseconds
20055 * to keep LED off between cycles.
20057 uint16_t led2_blink_off;
20059 * An identifier for the group of LEDs that LED #2 belongs
20061 * If set to 0, then the LED #2 shall not be grouped and
20062 * shall be treated as an individual resource.
20063 * For all other non-zero values of this field, LED #2 shall
20064 * be grouped together with the LEDs with the same group ID
20067 uint8_t led2_group_id;
20068 /* Reserved field. */
20070 /* An identifier for the LED #3. */
20072 /* The requested state of the LED #3. */
20073 uint8_t led3_state;
20074 /* Default state of the LED */
20075 #define HWRM_PORT_LED_CFG_INPUT_LED3_STATE_DEFAULT UINT32_C(0x0)
20077 #define HWRM_PORT_LED_CFG_INPUT_LED3_STATE_OFF UINT32_C(0x1)
20079 #define HWRM_PORT_LED_CFG_INPUT_LED3_STATE_ON UINT32_C(0x2)
20081 #define HWRM_PORT_LED_CFG_INPUT_LED3_STATE_BLINK UINT32_C(0x3)
20082 /* Blink Alternately */
20083 #define HWRM_PORT_LED_CFG_INPUT_LED3_STATE_BLINKALT UINT32_C(0x4)
20084 #define HWRM_PORT_LED_CFG_INPUT_LED3_STATE_LAST \
20085 HWRM_PORT_LED_CFG_INPUT_LED3_STATE_BLINKALT
20086 /* The requested color of LED #3. */
20087 uint8_t led3_color;
20089 #define HWRM_PORT_LED_CFG_INPUT_LED3_COLOR_DEFAULT UINT32_C(0x0)
20091 #define HWRM_PORT_LED_CFG_INPUT_LED3_COLOR_AMBER UINT32_C(0x1)
20093 #define HWRM_PORT_LED_CFG_INPUT_LED3_COLOR_GREEN UINT32_C(0x2)
20094 /* Green or Amber */
20095 #define HWRM_PORT_LED_CFG_INPUT_LED3_COLOR_GREENAMBER UINT32_C(0x3)
20096 #define HWRM_PORT_LED_CFG_INPUT_LED3_COLOR_LAST \
20097 HWRM_PORT_LED_CFG_INPUT_LED3_COLOR_GREENAMBER
20100 * If the LED #3 state is "blink" or "blinkalt", then
20101 * this field represents the requested time in milliseconds
20102 * to keep LED on between cycles.
20104 uint16_t led3_blink_on;
20106 * If the LED #3 state is "blink" or "blinkalt", then
20107 * this field represents the requested time in milliseconds
20108 * to keep LED off between cycles.
20110 uint16_t led3_blink_off;
20112 * An identifier for the group of LEDs that LED #3 belongs
20114 * If set to 0, then the LED #3 shall not be grouped and
20115 * shall be treated as an individual resource.
20116 * For all other non-zero values of this field, LED #3 shall
20117 * be grouped together with the LEDs with the same group ID
20120 uint8_t led3_group_id;
20121 /* Reserved field. */
20125 /* hwrm_port_led_cfg_output (size:128b/16B) */
20126 struct hwrm_port_led_cfg_output {
20127 /* The specific error status for the command. */
20128 uint16_t error_code;
20129 /* The HWRM command request type. */
20131 /* The sequence ID from the original command. */
20133 /* The length of the response data in number of bytes. */
20135 uint8_t unused_0[7];
20137 * This field is used in Output records to indicate that the output
20138 * is completely written to RAM. This field should be read as '1'
20139 * to indicate that the output has been completely written.
20140 * When writing a command completion or response to an internal processor,
20141 * the order of writes has to be such that this field is written last.
20146 /**********************
20147 * hwrm_port_led_qcfg *
20148 **********************/
20151 /* hwrm_port_led_qcfg_input (size:192b/24B) */
20152 struct hwrm_port_led_qcfg_input {
20153 /* The HWRM command request type. */
20156 * The completion ring to send the completion event on. This should
20157 * be the NQ ID returned from the `nq_alloc` HWRM command.
20159 uint16_t cmpl_ring;
20161 * The sequence ID is used by the driver for tracking multiple
20162 * commands. This ID is treated as opaque data by the firmware and
20163 * the value is returned in the `hwrm_resp_hdr` upon completion.
20167 * The target ID of the command:
20168 * * 0x0-0xFFF8 - The function ID
20169 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
20170 * * 0xFFFD - Reserved for user-space HWRM interface
20173 uint16_t target_id;
20175 * A physical address pointer pointing to a host buffer that the
20176 * command's response data will be written. This can be either a host
20177 * physical address (HPA) or a guest physical address (GPA) and must
20178 * point to a physically contiguous block of memory.
20180 uint64_t resp_addr;
20181 /* Port ID of port whose LED configuration is being queried. */
20183 uint8_t unused_0[6];
20186 /* hwrm_port_led_qcfg_output (size:448b/56B) */
20187 struct hwrm_port_led_qcfg_output {
20188 /* The specific error status for the command. */
20189 uint16_t error_code;
20190 /* The HWRM command request type. */
20192 /* The sequence ID from the original command. */
20194 /* The length of the response data in number of bytes. */
20197 * The number of LEDs that are configured on this port.
20198 * Up to 4 LEDs can be returned in the response.
20201 /* An identifier for the LED #0. */
20203 /* The type of LED #0. */
20206 #define HWRM_PORT_LED_QCFG_OUTPUT_LED0_TYPE_SPEED UINT32_C(0x0)
20208 #define HWRM_PORT_LED_QCFG_OUTPUT_LED0_TYPE_ACTIVITY UINT32_C(0x1)
20210 #define HWRM_PORT_LED_QCFG_OUTPUT_LED0_TYPE_INVALID UINT32_C(0xff)
20211 #define HWRM_PORT_LED_QCFG_OUTPUT_LED0_TYPE_LAST \
20212 HWRM_PORT_LED_QCFG_OUTPUT_LED0_TYPE_INVALID
20213 /* The current state of the LED #0. */
20214 uint8_t led0_state;
20215 /* Default state of the LED */
20216 #define HWRM_PORT_LED_QCFG_OUTPUT_LED0_STATE_DEFAULT UINT32_C(0x0)
20218 #define HWRM_PORT_LED_QCFG_OUTPUT_LED0_STATE_OFF UINT32_C(0x1)
20220 #define HWRM_PORT_LED_QCFG_OUTPUT_LED0_STATE_ON UINT32_C(0x2)
20222 #define HWRM_PORT_LED_QCFG_OUTPUT_LED0_STATE_BLINK UINT32_C(0x3)
20223 /* Blink Alternately */
20224 #define HWRM_PORT_LED_QCFG_OUTPUT_LED0_STATE_BLINKALT UINT32_C(0x4)
20225 #define HWRM_PORT_LED_QCFG_OUTPUT_LED0_STATE_LAST \
20226 HWRM_PORT_LED_QCFG_OUTPUT_LED0_STATE_BLINKALT
20227 /* The color of LED #0. */
20228 uint8_t led0_color;
20230 #define HWRM_PORT_LED_QCFG_OUTPUT_LED0_COLOR_DEFAULT UINT32_C(0x0)
20232 #define HWRM_PORT_LED_QCFG_OUTPUT_LED0_COLOR_AMBER UINT32_C(0x1)
20234 #define HWRM_PORT_LED_QCFG_OUTPUT_LED0_COLOR_GREEN UINT32_C(0x2)
20235 /* Green or Amber */
20236 #define HWRM_PORT_LED_QCFG_OUTPUT_LED0_COLOR_GREENAMBER UINT32_C(0x3)
20237 #define HWRM_PORT_LED_QCFG_OUTPUT_LED0_COLOR_LAST \
20238 HWRM_PORT_LED_QCFG_OUTPUT_LED0_COLOR_GREENAMBER
20241 * If the LED #0 state is "blink" or "blinkalt", then
20242 * this field represents the requested time in milliseconds
20243 * to keep LED on between cycles.
20245 uint16_t led0_blink_on;
20247 * If the LED #0 state is "blink" or "blinkalt", then
20248 * this field represents the requested time in milliseconds
20249 * to keep LED off between cycles.
20251 uint16_t led0_blink_off;
20253 * An identifier for the group of LEDs that LED #0 belongs
20255 * If set to 0, then the LED #0 is not grouped.
20256 * For all other non-zero values of this field, LED #0 is
20257 * grouped together with the LEDs with the same group ID
20260 uint8_t led0_group_id;
20261 /* An identifier for the LED #1. */
20263 /* The type of LED #1. */
20266 #define HWRM_PORT_LED_QCFG_OUTPUT_LED1_TYPE_SPEED UINT32_C(0x0)
20268 #define HWRM_PORT_LED_QCFG_OUTPUT_LED1_TYPE_ACTIVITY UINT32_C(0x1)
20270 #define HWRM_PORT_LED_QCFG_OUTPUT_LED1_TYPE_INVALID UINT32_C(0xff)
20271 #define HWRM_PORT_LED_QCFG_OUTPUT_LED1_TYPE_LAST \
20272 HWRM_PORT_LED_QCFG_OUTPUT_LED1_TYPE_INVALID
20273 /* The current state of the LED #1. */
20274 uint8_t led1_state;
20275 /* Default state of the LED */
20276 #define HWRM_PORT_LED_QCFG_OUTPUT_LED1_STATE_DEFAULT UINT32_C(0x0)
20278 #define HWRM_PORT_LED_QCFG_OUTPUT_LED1_STATE_OFF UINT32_C(0x1)
20280 #define HWRM_PORT_LED_QCFG_OUTPUT_LED1_STATE_ON UINT32_C(0x2)
20282 #define HWRM_PORT_LED_QCFG_OUTPUT_LED1_STATE_BLINK UINT32_C(0x3)
20283 /* Blink Alternately */
20284 #define HWRM_PORT_LED_QCFG_OUTPUT_LED1_STATE_BLINKALT UINT32_C(0x4)
20285 #define HWRM_PORT_LED_QCFG_OUTPUT_LED1_STATE_LAST \
20286 HWRM_PORT_LED_QCFG_OUTPUT_LED1_STATE_BLINKALT
20287 /* The color of LED #1. */
20288 uint8_t led1_color;
20290 #define HWRM_PORT_LED_QCFG_OUTPUT_LED1_COLOR_DEFAULT UINT32_C(0x0)
20292 #define HWRM_PORT_LED_QCFG_OUTPUT_LED1_COLOR_AMBER UINT32_C(0x1)
20294 #define HWRM_PORT_LED_QCFG_OUTPUT_LED1_COLOR_GREEN UINT32_C(0x2)
20295 /* Green or Amber */
20296 #define HWRM_PORT_LED_QCFG_OUTPUT_LED1_COLOR_GREENAMBER UINT32_C(0x3)
20297 #define HWRM_PORT_LED_QCFG_OUTPUT_LED1_COLOR_LAST \
20298 HWRM_PORT_LED_QCFG_OUTPUT_LED1_COLOR_GREENAMBER
20301 * If the LED #1 state is "blink" or "blinkalt", then
20302 * this field represents the requested time in milliseconds
20303 * to keep LED on between cycles.
20305 uint16_t led1_blink_on;
20307 * If the LED #1 state is "blink" or "blinkalt", then
20308 * this field represents the requested time in milliseconds
20309 * to keep LED off between cycles.
20311 uint16_t led1_blink_off;
20313 * An identifier for the group of LEDs that LED #1 belongs
20315 * If set to 0, then the LED #1 is not grouped.
20316 * For all other non-zero values of this field, LED #1 is
20317 * grouped together with the LEDs with the same group ID
20320 uint8_t led1_group_id;
20321 /* An identifier for the LED #2. */
20323 /* The type of LED #2. */
20326 #define HWRM_PORT_LED_QCFG_OUTPUT_LED2_TYPE_SPEED UINT32_C(0x0)
20328 #define HWRM_PORT_LED_QCFG_OUTPUT_LED2_TYPE_ACTIVITY UINT32_C(0x1)
20330 #define HWRM_PORT_LED_QCFG_OUTPUT_LED2_TYPE_INVALID UINT32_C(0xff)
20331 #define HWRM_PORT_LED_QCFG_OUTPUT_LED2_TYPE_LAST \
20332 HWRM_PORT_LED_QCFG_OUTPUT_LED2_TYPE_INVALID
20333 /* The current state of the LED #2. */
20334 uint8_t led2_state;
20335 /* Default state of the LED */
20336 #define HWRM_PORT_LED_QCFG_OUTPUT_LED2_STATE_DEFAULT UINT32_C(0x0)
20338 #define HWRM_PORT_LED_QCFG_OUTPUT_LED2_STATE_OFF UINT32_C(0x1)
20340 #define HWRM_PORT_LED_QCFG_OUTPUT_LED2_STATE_ON UINT32_C(0x2)
20342 #define HWRM_PORT_LED_QCFG_OUTPUT_LED2_STATE_BLINK UINT32_C(0x3)
20343 /* Blink Alternately */
20344 #define HWRM_PORT_LED_QCFG_OUTPUT_LED2_STATE_BLINKALT UINT32_C(0x4)
20345 #define HWRM_PORT_LED_QCFG_OUTPUT_LED2_STATE_LAST \
20346 HWRM_PORT_LED_QCFG_OUTPUT_LED2_STATE_BLINKALT
20347 /* The color of LED #2. */
20348 uint8_t led2_color;
20350 #define HWRM_PORT_LED_QCFG_OUTPUT_LED2_COLOR_DEFAULT UINT32_C(0x0)
20352 #define HWRM_PORT_LED_QCFG_OUTPUT_LED2_COLOR_AMBER UINT32_C(0x1)
20354 #define HWRM_PORT_LED_QCFG_OUTPUT_LED2_COLOR_GREEN UINT32_C(0x2)
20355 /* Green or Amber */
20356 #define HWRM_PORT_LED_QCFG_OUTPUT_LED2_COLOR_GREENAMBER UINT32_C(0x3)
20357 #define HWRM_PORT_LED_QCFG_OUTPUT_LED2_COLOR_LAST \
20358 HWRM_PORT_LED_QCFG_OUTPUT_LED2_COLOR_GREENAMBER
20361 * If the LED #2 state is "blink" or "blinkalt", then
20362 * this field represents the requested time in milliseconds
20363 * to keep LED on between cycles.
20365 uint16_t led2_blink_on;
20367 * If the LED #2 state is "blink" or "blinkalt", then
20368 * this field represents the requested time in milliseconds
20369 * to keep LED off between cycles.
20371 uint16_t led2_blink_off;
20373 * An identifier for the group of LEDs that LED #2 belongs
20375 * If set to 0, then the LED #2 is not grouped.
20376 * For all other non-zero values of this field, LED #2 is
20377 * grouped together with the LEDs with the same group ID
20380 uint8_t led2_group_id;
20381 /* An identifier for the LED #3. */
20383 /* The type of LED #3. */
20386 #define HWRM_PORT_LED_QCFG_OUTPUT_LED3_TYPE_SPEED UINT32_C(0x0)
20388 #define HWRM_PORT_LED_QCFG_OUTPUT_LED3_TYPE_ACTIVITY UINT32_C(0x1)
20390 #define HWRM_PORT_LED_QCFG_OUTPUT_LED3_TYPE_INVALID UINT32_C(0xff)
20391 #define HWRM_PORT_LED_QCFG_OUTPUT_LED3_TYPE_LAST \
20392 HWRM_PORT_LED_QCFG_OUTPUT_LED3_TYPE_INVALID
20393 /* The current state of the LED #3. */
20394 uint8_t led3_state;
20395 /* Default state of the LED */
20396 #define HWRM_PORT_LED_QCFG_OUTPUT_LED3_STATE_DEFAULT UINT32_C(0x0)
20398 #define HWRM_PORT_LED_QCFG_OUTPUT_LED3_STATE_OFF UINT32_C(0x1)
20400 #define HWRM_PORT_LED_QCFG_OUTPUT_LED3_STATE_ON UINT32_C(0x2)
20402 #define HWRM_PORT_LED_QCFG_OUTPUT_LED3_STATE_BLINK UINT32_C(0x3)
20403 /* Blink Alternately */
20404 #define HWRM_PORT_LED_QCFG_OUTPUT_LED3_STATE_BLINKALT UINT32_C(0x4)
20405 #define HWRM_PORT_LED_QCFG_OUTPUT_LED3_STATE_LAST \
20406 HWRM_PORT_LED_QCFG_OUTPUT_LED3_STATE_BLINKALT
20407 /* The color of LED #3. */
20408 uint8_t led3_color;
20410 #define HWRM_PORT_LED_QCFG_OUTPUT_LED3_COLOR_DEFAULT UINT32_C(0x0)
20412 #define HWRM_PORT_LED_QCFG_OUTPUT_LED3_COLOR_AMBER UINT32_C(0x1)
20414 #define HWRM_PORT_LED_QCFG_OUTPUT_LED3_COLOR_GREEN UINT32_C(0x2)
20415 /* Green or Amber */
20416 #define HWRM_PORT_LED_QCFG_OUTPUT_LED3_COLOR_GREENAMBER UINT32_C(0x3)
20417 #define HWRM_PORT_LED_QCFG_OUTPUT_LED3_COLOR_LAST \
20418 HWRM_PORT_LED_QCFG_OUTPUT_LED3_COLOR_GREENAMBER
20421 * If the LED #3 state is "blink" or "blinkalt", then
20422 * this field represents the requested time in milliseconds
20423 * to keep LED on between cycles.
20425 uint16_t led3_blink_on;
20427 * If the LED #3 state is "blink" or "blinkalt", then
20428 * this field represents the requested time in milliseconds
20429 * to keep LED off between cycles.
20431 uint16_t led3_blink_off;
20433 * An identifier for the group of LEDs that LED #3 belongs
20435 * If set to 0, then the LED #3 is not grouped.
20436 * For all other non-zero values of this field, LED #3 is
20437 * grouped together with the LEDs with the same group ID
20440 uint8_t led3_group_id;
20441 uint8_t unused_4[6];
20443 * This field is used in Output records to indicate that the output
20444 * is completely written to RAM. This field should be read as '1'
20445 * to indicate that the output has been completely written.
20446 * When writing a command completion or response to an internal processor,
20447 * the order of writes has to be such that this field is written last.
20452 /***********************
20453 * hwrm_port_led_qcaps *
20454 ***********************/
20457 /* hwrm_port_led_qcaps_input (size:192b/24B) */
20458 struct hwrm_port_led_qcaps_input {
20459 /* The HWRM command request type. */
20462 * The completion ring to send the completion event on. This should
20463 * be the NQ ID returned from the `nq_alloc` HWRM command.
20465 uint16_t cmpl_ring;
20467 * The sequence ID is used by the driver for tracking multiple
20468 * commands. This ID is treated as opaque data by the firmware and
20469 * the value is returned in the `hwrm_resp_hdr` upon completion.
20473 * The target ID of the command:
20474 * * 0x0-0xFFF8 - The function ID
20475 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
20476 * * 0xFFFD - Reserved for user-space HWRM interface
20479 uint16_t target_id;
20481 * A physical address pointer pointing to a host buffer that the
20482 * command's response data will be written. This can be either a host
20483 * physical address (HPA) or a guest physical address (GPA) and must
20484 * point to a physically contiguous block of memory.
20486 uint64_t resp_addr;
20487 /* Port ID of port whose LED configuration is being queried. */
20489 uint8_t unused_0[6];
20492 /* hwrm_port_led_qcaps_output (size:384b/48B) */
20493 struct hwrm_port_led_qcaps_output {
20494 /* The specific error status for the command. */
20495 uint16_t error_code;
20496 /* The HWRM command request type. */
20498 /* The sequence ID from the original command. */
20500 /* The length of the response data in number of bytes. */
20503 * The number of LEDs that are configured on this port.
20504 * Up to 4 LEDs can be returned in the response.
20507 /* Reserved for future use. */
20509 /* An identifier for the LED #0. */
20511 /* The type of LED #0. */
20514 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED0_TYPE_SPEED UINT32_C(0x0)
20516 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED0_TYPE_ACTIVITY UINT32_C(0x1)
20518 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED0_TYPE_INVALID UINT32_C(0xff)
20519 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED0_TYPE_LAST \
20520 HWRM_PORT_LED_QCAPS_OUTPUT_LED0_TYPE_INVALID
20522 * An identifier for the group of LEDs that LED #0 belongs
20524 * If set to 0, then the LED #0 cannot be grouped.
20525 * For all other non-zero values of this field, LED #0 is
20526 * grouped together with the LEDs with the same group ID
20529 uint8_t led0_group_id;
20531 /* The states supported by LED #0. */
20532 uint16_t led0_state_caps;
20534 * If set to 1, this LED is enabled.
20535 * If set to 0, this LED is disabled.
20537 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED0_STATE_CAPS_ENABLED \
20540 * If set to 1, off state is supported on this LED.
20541 * If set to 0, off state is not supported on this LED.
20543 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED0_STATE_CAPS_OFF_SUPPORTED \
20546 * If set to 1, on state is supported on this LED.
20547 * If set to 0, on state is not supported on this LED.
20549 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED0_STATE_CAPS_ON_SUPPORTED \
20552 * If set to 1, blink state is supported on this LED.
20553 * If set to 0, blink state is not supported on this LED.
20555 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED0_STATE_CAPS_BLINK_SUPPORTED \
20558 * If set to 1, blink_alt state is supported on this LED.
20559 * If set to 0, blink_alt state is not supported on this LED.
20561 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED0_STATE_CAPS_BLINK_ALT_SUPPORTED \
20563 /* The colors supported by LED #0. */
20564 uint16_t led0_color_caps;
20566 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED0_COLOR_CAPS_RSVD \
20569 * If set to 1, Amber color is supported on this LED.
20570 * If set to 0, Amber color is not supported on this LED.
20572 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED0_COLOR_CAPS_AMBER_SUPPORTED \
20575 * If set to 1, Green color is supported on this LED.
20576 * If set to 0, Green color is not supported on this LED.
20578 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED0_COLOR_CAPS_GREEN_SUPPORTED \
20580 /* An identifier for the LED #1. */
20582 /* The type of LED #1. */
20585 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED1_TYPE_SPEED UINT32_C(0x0)
20587 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED1_TYPE_ACTIVITY UINT32_C(0x1)
20589 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED1_TYPE_INVALID UINT32_C(0xff)
20590 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED1_TYPE_LAST \
20591 HWRM_PORT_LED_QCAPS_OUTPUT_LED1_TYPE_INVALID
20593 * An identifier for the group of LEDs that LED #1 belongs
20595 * If set to 0, then the LED #0 cannot be grouped.
20596 * For all other non-zero values of this field, LED #0 is
20597 * grouped together with the LEDs with the same group ID
20600 uint8_t led1_group_id;
20602 /* The states supported by LED #1. */
20603 uint16_t led1_state_caps;
20605 * If set to 1, this LED is enabled.
20606 * If set to 0, this LED is disabled.
20608 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED1_STATE_CAPS_ENABLED \
20611 * If set to 1, off state is supported on this LED.
20612 * If set to 0, off state is not supported on this LED.
20614 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED1_STATE_CAPS_OFF_SUPPORTED \
20617 * If set to 1, on state is supported on this LED.
20618 * If set to 0, on state is not supported on this LED.
20620 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED1_STATE_CAPS_ON_SUPPORTED \
20623 * If set to 1, blink state is supported on this LED.
20624 * If set to 0, blink state is not supported on this LED.
20626 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED1_STATE_CAPS_BLINK_SUPPORTED \
20629 * If set to 1, blink_alt state is supported on this LED.
20630 * If set to 0, blink_alt state is not supported on this LED.
20632 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED1_STATE_CAPS_BLINK_ALT_SUPPORTED \
20634 /* The colors supported by LED #1. */
20635 uint16_t led1_color_caps;
20637 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED1_COLOR_CAPS_RSVD \
20640 * If set to 1, Amber color is supported on this LED.
20641 * If set to 0, Amber color is not supported on this LED.
20643 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED1_COLOR_CAPS_AMBER_SUPPORTED \
20646 * If set to 1, Green color is supported on this LED.
20647 * If set to 0, Green color is not supported on this LED.
20649 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED1_COLOR_CAPS_GREEN_SUPPORTED \
20651 /* An identifier for the LED #2. */
20653 /* The type of LED #2. */
20656 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED2_TYPE_SPEED UINT32_C(0x0)
20658 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED2_TYPE_ACTIVITY UINT32_C(0x1)
20660 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED2_TYPE_INVALID UINT32_C(0xff)
20661 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED2_TYPE_LAST \
20662 HWRM_PORT_LED_QCAPS_OUTPUT_LED2_TYPE_INVALID
20664 * An identifier for the group of LEDs that LED #0 belongs
20666 * If set to 0, then the LED #0 cannot be grouped.
20667 * For all other non-zero values of this field, LED #0 is
20668 * grouped together with the LEDs with the same group ID
20671 uint8_t led2_group_id;
20673 /* The states supported by LED #2. */
20674 uint16_t led2_state_caps;
20676 * If set to 1, this LED is enabled.
20677 * If set to 0, this LED is disabled.
20679 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED2_STATE_CAPS_ENABLED \
20682 * If set to 1, off state is supported on this LED.
20683 * If set to 0, off state is not supported on this LED.
20685 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED2_STATE_CAPS_OFF_SUPPORTED \
20688 * If set to 1, on state is supported on this LED.
20689 * If set to 0, on state is not supported on this LED.
20691 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED2_STATE_CAPS_ON_SUPPORTED \
20694 * If set to 1, blink state is supported on this LED.
20695 * If set to 0, blink state is not supported on this LED.
20697 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED2_STATE_CAPS_BLINK_SUPPORTED \
20700 * If set to 1, blink_alt state is supported on this LED.
20701 * If set to 0, blink_alt state is not supported on this LED.
20703 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED2_STATE_CAPS_BLINK_ALT_SUPPORTED \
20705 /* The colors supported by LED #2. */
20706 uint16_t led2_color_caps;
20708 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED2_COLOR_CAPS_RSVD \
20711 * If set to 1, Amber color is supported on this LED.
20712 * If set to 0, Amber color is not supported on this LED.
20714 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED2_COLOR_CAPS_AMBER_SUPPORTED \
20717 * If set to 1, Green color is supported on this LED.
20718 * If set to 0, Green color is not supported on this LED.
20720 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED2_COLOR_CAPS_GREEN_SUPPORTED \
20722 /* An identifier for the LED #3. */
20724 /* The type of LED #3. */
20727 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED3_TYPE_SPEED UINT32_C(0x0)
20729 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED3_TYPE_ACTIVITY UINT32_C(0x1)
20731 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED3_TYPE_INVALID UINT32_C(0xff)
20732 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED3_TYPE_LAST \
20733 HWRM_PORT_LED_QCAPS_OUTPUT_LED3_TYPE_INVALID
20735 * An identifier for the group of LEDs that LED #3 belongs
20737 * If set to 0, then the LED #0 cannot be grouped.
20738 * For all other non-zero values of this field, LED #0 is
20739 * grouped together with the LEDs with the same group ID
20742 uint8_t led3_group_id;
20744 /* The states supported by LED #3. */
20745 uint16_t led3_state_caps;
20747 * If set to 1, this LED is enabled.
20748 * If set to 0, this LED is disabled.
20750 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED3_STATE_CAPS_ENABLED \
20753 * If set to 1, off state is supported on this LED.
20754 * If set to 0, off state is not supported on this LED.
20756 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED3_STATE_CAPS_OFF_SUPPORTED \
20759 * If set to 1, on state is supported on this LED.
20760 * If set to 0, on state is not supported on this LED.
20762 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED3_STATE_CAPS_ON_SUPPORTED \
20765 * If set to 1, blink state is supported on this LED.
20766 * If set to 0, blink state is not supported on this LED.
20768 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED3_STATE_CAPS_BLINK_SUPPORTED \
20771 * If set to 1, blink_alt state is supported on this LED.
20772 * If set to 0, blink_alt state is not supported on this LED.
20774 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED3_STATE_CAPS_BLINK_ALT_SUPPORTED \
20776 /* The colors supported by LED #3. */
20777 uint16_t led3_color_caps;
20779 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED3_COLOR_CAPS_RSVD \
20782 * If set to 1, Amber color is supported on this LED.
20783 * If set to 0, Amber color is not supported on this LED.
20785 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED3_COLOR_CAPS_AMBER_SUPPORTED \
20788 * If set to 1, Green color is supported on this LED.
20789 * If set to 0, Green color is not supported on this LED.
20791 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED3_COLOR_CAPS_GREEN_SUPPORTED \
20793 uint8_t unused_4[3];
20795 * This field is used in Output records to indicate that the output
20796 * is completely written to RAM. This field should be read as '1'
20797 * to indicate that the output has been completely written.
20798 * When writing a command completion or response to an internal processor,
20799 * the order of writes has to be such that this field is written last.
20804 /***********************
20805 * hwrm_port_prbs_test *
20806 ***********************/
20809 /* hwrm_port_prbs_test_input (size:384b/48B) */
20810 struct hwrm_port_prbs_test_input {
20811 /* The HWRM command request type. */
20814 * The completion ring to send the completion event on. This should
20815 * be the NQ ID returned from the `nq_alloc` HWRM command.
20817 uint16_t cmpl_ring;
20819 * The sequence ID is used by the driver for tracking multiple
20820 * commands. This ID is treated as opaque data by the firmware and
20821 * the value is returned in the `hwrm_resp_hdr` upon completion.
20825 * The target ID of the command:
20826 * * 0x0-0xFFF8 - The function ID
20827 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
20828 * * 0xFFFD - Reserved for user-space HWRM interface
20831 uint16_t target_id;
20833 * A physical address pointer pointing to a host buffer that the
20834 * command's response data will be written. This can be either a host
20835 * physical address (HPA) or a guest physical address (GPA) and must
20836 * point to a physically contiguous block of memory.
20838 uint64_t resp_addr;
20839 /* Host address data is to DMA'd to. */
20840 uint64_t resp_data_addr;
20842 * Size of the buffer pointed to by resp_data_addr. The firmware may
20843 * use this entire buffer or less than the entire buffer, but never more.
20848 /* Port ID of port where PRBS test to be run. */
20850 /* Polynomial selection for PRBS test. */
20853 #define HWRM_PORT_PRBS_TEST_INPUT_POLY_PRBS7 UINT32_C(0x0)
20855 #define HWRM_PORT_PRBS_TEST_INPUT_POLY_PRBS9 UINT32_C(0x1)
20857 #define HWRM_PORT_PRBS_TEST_INPUT_POLY_PRBS11 UINT32_C(0x2)
20859 #define HWRM_PORT_PRBS_TEST_INPUT_POLY_PRBS15 UINT32_C(0x3)
20861 #define HWRM_PORT_PRBS_TEST_INPUT_POLY_PRBS23 UINT32_C(0x4)
20863 #define HWRM_PORT_PRBS_TEST_INPUT_POLY_PRBS31 UINT32_C(0x5)
20865 #define HWRM_PORT_PRBS_TEST_INPUT_POLY_PRBS58 UINT32_C(0x6)
20867 #define HWRM_PORT_PRBS_TEST_INPUT_POLY_INVALID UINT32_C(0xff)
20868 #define HWRM_PORT_PRBS_TEST_INPUT_POLY_LAST \
20869 HWRM_PORT_PRBS_TEST_INPUT_POLY_INVALID
20871 * Configuration bits for PRBS test.
20872 * Use enable bit to start/stop test.
20873 * Use tx/rx lane map bits to run test on specific lanes,
20874 * if set to 0 test will be run on all lanes.
20876 uint16_t prbs_config;
20878 * Set 0 to stop test currently in progress
20879 * Set 1 to start test with configuration provided.
20881 #define HWRM_PORT_PRBS_TEST_INPUT_PRBS_CONFIG_START_STOP \
20884 * If set to 1, tx_lane_map bitmap should have lane bits set.
20885 * If set to 0, test will be run on all lanes for this port.
20887 #define HWRM_PORT_PRBS_TEST_INPUT_PRBS_CONFIG_TX_LANE_MAP_VALID \
20890 * If set to 1, rx_lane_map bitmap should have lane bits set.
20891 * If set to 0, test will be run on all lanes for this port.
20893 #define HWRM_PORT_PRBS_TEST_INPUT_PRBS_CONFIG_RX_LANE_MAP_VALID \
20895 /* Duration in seconds to run the PRBS test. */
20898 * If tx_lane_map_valid is set to 1, this field is a bitmap
20899 * of tx lanes to run PRBS test. bit0 = lane0,
20900 * bit1 = lane1 ..bit31 = lane31
20902 uint32_t tx_lane_map;
20904 * If rx_lane_map_valid is set to 1, this field is a bitmap
20905 * of rx lanes to run PRBS test. bit0 = lane0,
20906 * bit1 = lane1 ..bit31 = lane31
20908 uint32_t rx_lane_map;
20911 /* hwrm_port_prbs_test_output (size:128b/16B) */
20912 struct hwrm_port_prbs_test_output {
20913 /* The specific error status for the command. */
20914 uint16_t error_code;
20915 /* The HWRM command request type. */
20917 /* The sequence ID from the original command. */
20919 /* The length of the response data in number of bytes. */
20921 /* Total length of stored data. */
20922 uint16_t total_data_len;
20924 uint8_t unused_1[3];
20926 * This field is used in Output records to indicate that the output
20927 * is completely written to RAM. This field should be read as '1'
20928 * to indicate that the output has been completely written.
20929 * When writing a command completion or response to an internal processor,
20930 * the order of writes has to be such that this field is written last.
20935 /**********************
20936 * hwrm_port_dsc_dump *
20937 **********************/
20940 /* hwrm_port_dsc_dump_input (size:320b/40B) */
20941 struct hwrm_port_dsc_dump_input {
20942 /* The HWRM command request type. */
20945 * The completion ring to send the completion event on. This should
20946 * be the NQ ID returned from the `nq_alloc` HWRM command.
20948 uint16_t cmpl_ring;
20950 * The sequence ID is used by the driver for tracking multiple
20951 * commands. This ID is treated as opaque data by the firmware and
20952 * the value is returned in the `hwrm_resp_hdr` upon completion.
20956 * The target ID of the command:
20957 * * 0x0-0xFFF8 - The function ID
20958 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
20959 * * 0xFFFD - Reserved for user-space HWRM interface
20962 uint16_t target_id;
20964 * A physical address pointer pointing to a host buffer that the
20965 * command's response data will be written. This can be either a host
20966 * physical address (HPA) or a guest physical address (GPA) and must
20967 * point to a physically contiguous block of memory.
20969 uint64_t resp_addr;
20970 /* Host address where response diagnostic data is returned. */
20971 uint64_t resp_data_addr;
20973 * Size of the buffer pointed to by resp_data_addr. The firmware
20974 * may use this entire buffer or less than the entire buffer, but
20980 /* Port ID of port where dsc dump to be collected. */
20982 /* Diag level specified by the user */
20983 uint16_t diag_level;
20984 /* SRDS_DIAG_LANE */
20985 #define HWRM_PORT_DSC_DUMP_INPUT_DIAG_LEVEL_SRDS_DIAG_LANE \
20987 /* SRDS_DIAG_CORE */
20988 #define HWRM_PORT_DSC_DUMP_INPUT_DIAG_LEVEL_SRDS_DIAG_CORE \
20990 /* SRDS_DIAG_EVENT */
20991 #define HWRM_PORT_DSC_DUMP_INPUT_DIAG_LEVEL_SRDS_DIAG_EVENT \
20993 /* SRDS_DIAG_EYE */
20994 #define HWRM_PORT_DSC_DUMP_INPUT_DIAG_LEVEL_SRDS_DIAG_EYE \
20996 /* SRDS_DIAG_REG_CORE */
20997 #define HWRM_PORT_DSC_DUMP_INPUT_DIAG_LEVEL_SRDS_DIAG_REG_CORE \
20999 /* SRDS_DIAG_REG_LANE */
21000 #define HWRM_PORT_DSC_DUMP_INPUT_DIAG_LEVEL_SRDS_DIAG_REG_LANE \
21002 /* SRDS_DIAG_UC_CORE */
21003 #define HWRM_PORT_DSC_DUMP_INPUT_DIAG_LEVEL_SRDS_DIAG_UC_CORE \
21005 /* SRDS_DIAG_UC_LANE */
21006 #define HWRM_PORT_DSC_DUMP_INPUT_DIAG_LEVEL_SRDS_DIAG_UC_LANE \
21008 /* SRDS_DIAG_LANE_DEBUG */
21009 #define HWRM_PORT_DSC_DUMP_INPUT_DIAG_LEVEL_SRDS_DIAG_LANE_DEBUG \
21011 /* SRDS_DIAG_BER_VERT */
21012 #define HWRM_PORT_DSC_DUMP_INPUT_DIAG_LEVEL_SRDS_DIAG_BER_VERT \
21014 /* SRDS_DIAG_BER_HORZ */
21015 #define HWRM_PORT_DSC_DUMP_INPUT_DIAG_LEVEL_SRDS_DIAG_BER_HORZ \
21017 /* SRDS_DIAG_EVENT_SAFE */
21018 #define HWRM_PORT_DSC_DUMP_INPUT_DIAG_LEVEL_SRDS_DIAG_EVENT_SAFE \
21020 /* SRDS_DIAG_TIMESTAMP */
21021 #define HWRM_PORT_DSC_DUMP_INPUT_DIAG_LEVEL_SRDS_DIAG_TIMESTAMP \
21023 #define HWRM_PORT_DSC_DUMP_INPUT_DIAG_LEVEL_LAST \
21024 HWRM_PORT_DSC_DUMP_INPUT_DIAG_LEVEL_SRDS_DIAG_TIMESTAMP
21026 * This field is a lane number
21027 * on which to collect the dsc dump
21029 uint16_t lane_number;
21031 * Configuration bits.
21032 * Use enable bit to start dsc dump or retrieve dump
21034 uint16_t dsc_dump_config;
21036 * Set 0 to retrieve the dsc dump
21037 * Set 1 to start the dsc dump
21039 #define HWRM_PORT_DSC_DUMP_INPUT_DSC_DUMP_CONFIG_START_RETRIEVE \
21043 /* hwrm_port_dsc_dump_output (size:128b/16B) */
21044 struct hwrm_port_dsc_dump_output {
21045 /* The specific error status for the command. */
21046 uint16_t error_code;
21047 /* The HWRM command request type. */
21049 /* The sequence ID from the original command. */
21051 /* The length of the response data in number of bytes. */
21053 /* Total length of stored data. */
21054 uint16_t total_data_len;
21056 uint8_t unused_1[3];
21058 * This field is used in Output records to indicate that the output
21059 * is completely written to RAM. This field should be read as '1'
21060 * to indicate that the output has been completely written.
21061 * When writing a command completion or response to an internal processor,
21062 * the order of writes has to be such that this field is written last.
21067 /******************************
21068 * hwrm_port_sfp_sideband_cfg *
21069 ******************************/
21072 /* hwrm_port_sfp_sideband_cfg_input (size:256b/32B) */
21073 struct hwrm_port_sfp_sideband_cfg_input {
21074 /* The HWRM command request type. */
21077 * The completion ring to send the completion event on. This should
21078 * be the NQ ID returned from the `nq_alloc` HWRM command.
21080 uint16_t cmpl_ring;
21082 * The sequence ID is used by the driver for tracking multiple
21083 * commands. This ID is treated as opaque data by the firmware and
21084 * the value is returned in the `hwrm_resp_hdr` upon completion.
21088 * The target ID of the command:
21089 * * 0x0-0xFFF8 - The function ID
21090 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
21091 * * 0xFFFD - Reserved for user-space HWRM interface
21094 uint16_t target_id;
21096 * A physical address pointer pointing to a host buffer that the
21097 * command's response data will be written. This can be either a host
21098 * physical address (HPA) or a guest physical address (GPA) and must
21099 * point to a physically contiguous block of memory.
21101 uint64_t resp_addr;
21102 /* Port ID of port that is to be queried. */
21104 uint8_t unused_0[6];
21106 * This bitfield is used to specify which bits from the 'flags'
21107 * fields are being configured by the caller.
21110 /* This bit must be '1' for rs0 to be configured. */
21111 #define HWRM_PORT_SFP_SIDEBAND_CFG_INPUT_ENABLES_RS0 \
21113 /* This bit must be '1' for rs1 to be configured. */
21114 #define HWRM_PORT_SFP_SIDEBAND_CFG_INPUT_ENABLES_RS1 \
21116 /* This bit must be '1' for tx_disable to be configured. */
21117 #define HWRM_PORT_SFP_SIDEBAND_CFG_INPUT_ENABLES_TX_DIS \
21120 * This bit must be '1' for mod_sel to be configured.
21121 * Valid only on QSFP modules
21123 #define HWRM_PORT_SFP_SIDEBAND_CFG_INPUT_ENABLES_MOD_SEL \
21125 /* This bit must be '1' for reset_l to be configured. */
21126 #define HWRM_PORT_SFP_SIDEBAND_CFG_INPUT_ENABLES_RESET_L \
21128 /* This bit must be '1' for lp_mode to be configured. */
21129 #define HWRM_PORT_SFP_SIDEBAND_CFG_INPUT_ENABLES_LP_MODE \
21131 /* This bit must be '1' for pwr_disable to be configured. */
21132 #define HWRM_PORT_SFP_SIDEBAND_CFG_INPUT_ENABLES_PWR_DIS \
21135 * Only bits that have corresponding bits in the 'enables'
21136 * bitfield are processed by the firmware, all other bits
21137 * of 'flags' are ignored.
21141 * This bit along with rs1 configures the current speed of the dual
21142 * rate module. If these pins are GNDed then the speed can be changed
21143 * by driectly writing to EEPROM.
21145 #define HWRM_PORT_SFP_SIDEBAND_CFG_INPUT_FLAGS_RS0 \
21148 * This bit along with rs0 configures the current speed of the dual
21149 * rate module. If these pins are GNDed then the speed can be changed
21150 * by driectly writing to EEPROM.
21152 #define HWRM_PORT_SFP_SIDEBAND_CFG_INPUT_FLAGS_RS1 \
21155 * When this bit is set to '1', tx_disable is set.
21156 * On a 1G BASE-T module, if this bit is set,
21157 * module PHY registers will not be accessible.
21159 #define HWRM_PORT_SFP_SIDEBAND_CFG_INPUT_FLAGS_TX_DIS \
21162 * When this bit is set to '1', this module is selected.
21163 * Valid only on QSFP modules
21165 #define HWRM_PORT_SFP_SIDEBAND_CFG_INPUT_FLAGS_MOD_SEL \
21168 * If reset_l is set to 0, Module will be taken out of reset
21169 * and other signals will be set to their requested state once
21170 * the module is out of reset.
21171 * Valid only on QSFP modules
21173 #define HWRM_PORT_SFP_SIDEBAND_CFG_INPUT_FLAGS_RESET_L \
21176 * When this bit is set to '1', the module will be configured
21177 * in low power mode.
21178 * Valid only on QSFP modules
21180 #define HWRM_PORT_SFP_SIDEBAND_CFG_INPUT_FLAGS_LP_MODE \
21182 /* When this bit is set to '1', the module will be powered down. */
21183 #define HWRM_PORT_SFP_SIDEBAND_CFG_INPUT_FLAGS_PWR_DIS \
21187 /* hwrm_port_sfp_sideband_cfg_output (size:128b/16B) */
21188 struct hwrm_port_sfp_sideband_cfg_output {
21189 /* The specific error status for the command. */
21190 uint16_t error_code;
21191 /* The HWRM command request type. */
21193 /* The sequence ID from the original command. */
21195 /* The length of the response data in number of bytes. */
21199 * This field is used in Output records to indicate that the output
21200 * is completely written to RAM. This field should be read as '1'
21201 * to indicate that the output has been completely written. When
21202 * writing a command completion or response to an internal processor,
21203 * the order of writes has to be such that this field is written last.
21208 /*******************************
21209 * hwrm_port_sfp_sideband_qcfg *
21210 *******************************/
21213 /* hwrm_port_sfp_sideband_qcfg_input (size:192b/24B) */
21214 struct hwrm_port_sfp_sideband_qcfg_input {
21215 /* The HWRM command request type. */
21218 * The completion ring to send the completion event on. This should
21219 * be the NQ ID returned from the `nq_alloc` HWRM command.
21221 uint16_t cmpl_ring;
21223 * The sequence ID is used by the driver for tracking multiple
21224 * commands. This ID is treated as opaque data by the firmware and
21225 * the value is returned in the `hwrm_resp_hdr` upon completion.
21229 * The target ID of the command:
21230 * * 0x0-0xFFF8 - The function ID
21231 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
21232 * * 0xFFFD - Reserved for user-space HWRM interface
21235 uint16_t target_id;
21237 * A physical address pointer pointing to a host buffer that the
21238 * command's response data will be written. This can be either a host
21239 * physical address (HPA) or a guest physical address (GPA) and must
21240 * point to a physically contiguous block of memory.
21242 uint64_t resp_addr;
21243 /* Port ID of port that is to be queried. */
21245 uint8_t unused_0[6];
21248 /* hwrm_port_sfp_sideband_qcfg_output (size:192b/24B) */
21249 struct hwrm_port_sfp_sideband_qcfg_output {
21250 /* The specific error status for the command. */
21251 uint16_t error_code;
21252 /* The HWRM command request type. */
21254 /* The sequence ID from the original command. */
21256 /* The length of the response data in number of bytes. */
21259 * Bitmask indicating which sideband signals are valid.
21260 * This is based on the board and nvm cfg that is present on the board.
21262 uint32_t supported_mask;
21263 uint32_t sideband_signals;
21264 /* When this bit is set to '1', the Module is absent. */
21265 #define HWRM_PORT_SFP_SIDEBAND_QCFG_OUTPUT_SIDEBAND_SIGNALS_MOD_ABS \
21268 * When this bit is set to '1', there is no valid signal on RX.
21269 * This signal is a filtered version of Signal Detect.
21271 #define HWRM_PORT_SFP_SIDEBAND_QCFG_OUTPUT_SIDEBAND_SIGNALS_RX_LOS \
21274 * This bit along with rs1 indiactes the current speed of the dual
21275 * rate module.If these pins are grounded then the speed can be
21276 * changed by driectky writing to EEPROM.
21278 #define HWRM_PORT_SFP_SIDEBAND_QCFG_OUTPUT_SIDEBAND_SIGNALS_RS0 \
21281 * This bit along with rs0 indiactes the current speed of the dual
21282 * rate module.If these pins are grounded then the speed can be
21283 * changed by driectky writing to EEPROM.
21285 #define HWRM_PORT_SFP_SIDEBAND_QCFG_OUTPUT_SIDEBAND_SIGNALS_RS1 \
21288 * When this bit is set to '1', tx_disable is set.
21289 * On a 1G BASE-T module, if this bit is set, module PHY
21290 * registers will not be accessible.
21292 #define HWRM_PORT_SFP_SIDEBAND_QCFG_OUTPUT_SIDEBAND_SIGNALS_TX_DIS \
21294 /* When this bit is set to '1', tx_fault is set. */
21295 #define HWRM_PORT_SFP_SIDEBAND_QCFG_OUTPUT_SIDEBAND_SIGNALS_TX_FAULT \
21298 * When this bit is set to '1', module is selected.
21299 * Valid only on QSFP modules
21301 #define HWRM_PORT_SFP_SIDEBAND_QCFG_OUTPUT_SIDEBAND_SIGNALS_MOD_SEL \
21304 * When this bit is set to '0', the module is held in reset.
21305 * if reset_l is set to 1,first module is taken out of reset
21306 * and other signals will be set to their requested state.
21307 * Valid only on QSFP modules.
21309 #define HWRM_PORT_SFP_SIDEBAND_QCFG_OUTPUT_SIDEBAND_SIGNALS_RESET_L \
21312 * When this bit is set to '1', the module is in low power mode.
21313 * Valid only on QSFP modules
21315 #define HWRM_PORT_SFP_SIDEBAND_QCFG_OUTPUT_SIDEBAND_SIGNALS_LP_MODE \
21317 /* When this bit is set to '1', module is in power down state. */
21318 #define HWRM_PORT_SFP_SIDEBAND_QCFG_OUTPUT_SIDEBAND_SIGNALS_PWR_DIS \
21322 * This field is used in Output records to indicate that the output
21323 * is completely written to RAM. This field should be read as '1'
21324 * to indicate that the output has been completely written. When
21325 * writing a command completion or response to an internal processor,
21326 * the order of writes has to be such that this field is written last.
21331 /**********************************
21332 * hwrm_port_phy_mdio_bus_acquire *
21333 **********************************/
21336 /* hwrm_port_phy_mdio_bus_acquire_input (size:192b/24B) */
21337 struct hwrm_port_phy_mdio_bus_acquire_input {
21338 /* The HWRM command request type. */
21341 * The completion ring to send the completion event on. This should
21342 * be the NQ ID returned from the `nq_alloc` HWRM command.
21344 uint16_t cmpl_ring;
21346 * The sequence ID is used by the driver for tracking multiple
21347 * commands. This ID is treated as opaque data by the firmware and
21348 * the value is returned in the `hwrm_resp_hdr` upon completion.
21352 * The target ID of the command:
21353 * * 0x0-0xFFF8 - The function ID
21354 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
21355 * * 0xFFFD - Reserved for user-space HWRM interface
21358 uint16_t target_id;
21360 * A physical address pointer pointing to a host buffer that the
21361 * command's response data will be written. This can be either a host
21362 * physical address (HPA) or a guest physical address (GPA) and must
21363 * point to a physically contiguous block of memory.
21365 uint64_t resp_addr;
21366 /* Port ID of the port. */
21369 * client_id of the client requesting BUS access.
21370 * Any value from 0x10 to 0xFFFF can be used.
21371 * Client should make sure that the returned client_id
21372 * in response matches the client_id in request.
21373 * 0-0xF are reserved for internal use.
21375 uint16_t client_id;
21377 * Timeout in milli seconds, MDIO BUS will be released automatically
21378 * after this time, if another mdio acquire command is not received
21379 * within the timeout window from the same client.
21380 * A 0xFFFF will hold the bus until this bus is released.
21382 uint16_t mdio_bus_timeout;
21383 uint8_t unused_0[2];
21386 /* hwrm_port_phy_mdio_bus_acquire_output (size:128b/16B) */
21387 struct hwrm_port_phy_mdio_bus_acquire_output {
21388 /* The specific error status for the command. */
21389 uint16_t error_code;
21390 /* The HWRM command request type. */
21392 /* The sequence ID from the original command. */
21394 /* The length of the response data in number of bytes. */
21398 * client_id of the module holding the BUS.
21399 * 0-0xF are reserved for internal use.
21401 uint16_t client_id;
21402 uint8_t unused_1[3];
21404 * This field is used in Output records to indicate that the output
21405 * is completely written to RAM. This field should be read as '1'
21406 * to indicate that the output has been completely written.
21407 * When writing a command completion or response to an internal processor,
21408 * the order of writes has to be such that this field is written last.
21413 /**********************************
21414 * hwrm_port_phy_mdio_bus_release *
21415 **********************************/
21418 /* hwrm_port_phy_mdio_bus_release_input (size:192b/24B) */
21419 struct hwrm_port_phy_mdio_bus_release_input {
21420 /* The HWRM command request type. */
21423 * The completion ring to send the completion event on. This should
21424 * be the NQ ID returned from the `nq_alloc` HWRM command.
21426 uint16_t cmpl_ring;
21428 * The sequence ID is used by the driver for tracking multiple
21429 * commands. This ID is treated as opaque data by the firmware and
21430 * the value is returned in the `hwrm_resp_hdr` upon completion.
21434 * The target ID of the command:
21435 * * 0x0-0xFFF8 - The function ID
21436 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
21437 * * 0xFFFD - Reserved for user-space HWRM interface
21440 uint16_t target_id;
21442 * A physical address pointer pointing to a host buffer that the
21443 * command's response data will be written. This can be either a host
21444 * physical address (HPA) or a guest physical address (GPA) and must
21445 * point to a physically contiguous block of memory.
21447 uint64_t resp_addr;
21448 /* Port ID of the port. */
21451 * client_id of the client requesting BUS release.
21452 * A client should not release any other clients BUS.
21454 uint16_t client_id;
21455 uint8_t unused_0[4];
21458 /* hwrm_port_phy_mdio_bus_release_output (size:128b/16B) */
21459 struct hwrm_port_phy_mdio_bus_release_output {
21460 /* The specific error status for the command. */
21461 uint16_t error_code;
21462 /* The HWRM command request type. */
21464 /* The sequence ID from the original command. */
21466 /* The length of the response data in number of bytes. */
21469 /* The BUS is released if client_id matches the client_id in request. */
21470 uint16_t clients_id;
21471 uint8_t unused_1[3];
21473 * This field is used in Output records to indicate that the output
21474 * is completely written to RAM. This field should be read as '1'
21475 * to indicate that the output has been completely written.
21476 * When writing a command completion or response to an internal processor,
21477 * the order of writes has to be such that this field is written last.
21482 /***********************
21483 * hwrm_queue_qportcfg *
21484 ***********************/
21487 /* hwrm_queue_qportcfg_input (size:192b/24B) */
21488 struct hwrm_queue_qportcfg_input {
21489 /* The HWRM command request type. */
21492 * The completion ring to send the completion event on. This should
21493 * be the NQ ID returned from the `nq_alloc` HWRM command.
21495 uint16_t cmpl_ring;
21497 * The sequence ID is used by the driver for tracking multiple
21498 * commands. This ID is treated as opaque data by the firmware and
21499 * the value is returned in the `hwrm_resp_hdr` upon completion.
21503 * The target ID of the command:
21504 * * 0x0-0xFFF8 - The function ID
21505 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
21506 * * 0xFFFD - Reserved for user-space HWRM interface
21509 uint16_t target_id;
21511 * A physical address pointer pointing to a host buffer that the
21512 * command's response data will be written. This can be either a host
21513 * physical address (HPA) or a guest physical address (GPA) and must
21514 * point to a physically contiguous block of memory.
21516 uint64_t resp_addr;
21519 * Enumeration denoting the RX, TX type of the resource.
21520 * This enumeration is used for resources that are similar for both
21521 * TX and RX paths of the chip.
21523 #define HWRM_QUEUE_QPORTCFG_INPUT_FLAGS_PATH UINT32_C(0x1)
21525 #define HWRM_QUEUE_QPORTCFG_INPUT_FLAGS_PATH_TX UINT32_C(0x0)
21527 #define HWRM_QUEUE_QPORTCFG_INPUT_FLAGS_PATH_RX UINT32_C(0x1)
21528 #define HWRM_QUEUE_QPORTCFG_INPUT_FLAGS_PATH_LAST \
21529 HWRM_QUEUE_QPORTCFG_INPUT_FLAGS_PATH_RX
21531 * Port ID of port for which the queue configuration is being
21532 * queried. This field is only required when sent by IPC.
21536 * Drivers will set this capability when it can use
21537 * queue_idx_service_profile to map the queues to application.
21539 uint8_t drv_qmap_cap;
21541 #define HWRM_QUEUE_QPORTCFG_INPUT_DRV_QMAP_CAP_DISABLED UINT32_C(0x0)
21543 #define HWRM_QUEUE_QPORTCFG_INPUT_DRV_QMAP_CAP_ENABLED UINT32_C(0x1)
21544 #define HWRM_QUEUE_QPORTCFG_INPUT_DRV_QMAP_CAP_LAST \
21545 HWRM_QUEUE_QPORTCFG_INPUT_DRV_QMAP_CAP_ENABLED
21549 /* hwrm_queue_qportcfg_output (size:1344b/168B) */
21550 struct hwrm_queue_qportcfg_output {
21551 /* The specific error status for the command. */
21552 uint16_t error_code;
21553 /* The HWRM command request type. */
21555 /* The sequence ID from the original command. */
21557 /* The length of the response data in number of bytes. */
21560 * The maximum number of queues that can be configured on this
21562 * Valid values range from 1 through 8.
21564 uint8_t max_configurable_queues;
21566 * The maximum number of lossless queues that can be configured
21568 * Valid values range from 0 through 8.
21570 uint8_t max_configurable_lossless_queues;
21572 * Bitmask indicating which queues can be configured by the
21573 * hwrm_queue_cfg command.
21575 * Each bit represents a specific queue where bit 0 represents
21576 * queue 0 and bit 7 represents queue 7.
21577 * # A value of 0 indicates that the queue is not configurable
21578 * by the hwrm_queue_cfg command.
21579 * # A value of 1 indicates that the queue is configurable.
21580 * # A hwrm_queue_cfg command shall return error when trying to
21581 * configure a queue not configurable.
21583 uint8_t queue_cfg_allowed;
21584 /* Information about queue configuration. */
21585 uint8_t queue_cfg_info;
21587 * If this flag is set to '1', then the queues are
21588 * configured asymmetrically on TX and RX sides.
21589 * If this flag is set to '0', then the queues are
21590 * configured symmetrically on TX and RX sides. For
21591 * symmetric configuration, the queue configuration
21592 * including queue ids and service profiles on the
21593 * TX side is the same as the corresponding queue
21594 * configuration on the RX side.
21596 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_CFG_INFO_ASYM_CFG \
21599 * Bitmask indicating which queues can be configured by the
21600 * hwrm_queue_pfcenable_cfg command.
21602 * Each bit represents a specific priority where bit 0 represents
21603 * priority 0 and bit 7 represents priority 7.
21604 * # A value of 0 indicates that the priority is not configurable by
21605 * the hwrm_queue_pfcenable_cfg command.
21606 * # A value of 1 indicates that the priority is configurable.
21607 * # A hwrm_queue_pfcenable_cfg command shall return error when
21608 * trying to configure a priority that is not configurable.
21610 uint8_t queue_pfcenable_cfg_allowed;
21612 * Bitmask indicating which queues can be configured by the
21613 * hwrm_queue_pri2cos_cfg command.
21615 * Each bit represents a specific queue where bit 0 represents
21616 * queue 0 and bit 7 represents queue 7.
21617 * # A value of 0 indicates that the queue is not configurable
21618 * by the hwrm_queue_pri2cos_cfg command.
21619 * # A value of 1 indicates that the queue is configurable.
21620 * # A hwrm_queue_pri2cos_cfg command shall return error when
21621 * trying to configure a queue that is not configurable.
21623 uint8_t queue_pri2cos_cfg_allowed;
21625 * Bitmask indicating which queues can be configured by the
21626 * hwrm_queue_pri2cos_cfg command.
21628 * Each bit represents a specific queue where bit 0 represents
21629 * queue 0 and bit 7 represents queue 7.
21630 * # A value of 0 indicates that the queue is not configurable
21631 * by the hwrm_queue_pri2cos_cfg command.
21632 * # A value of 1 indicates that the queue is configurable.
21633 * # A hwrm_queue_pri2cos_cfg command shall return error when
21634 * trying to configure a queue not configurable.
21636 uint8_t queue_cos2bw_cfg_allowed;
21638 * ID of CoS Queue 0.
21641 * # This ID can be used on any subsequent call to an hwrm command
21642 * that takes a queue id.
21643 * # IDs must always be queried by this command before any use
21644 * by the driver or software.
21645 * # Any driver or software should not make any assumptions about
21647 * # A value of 0xff indicates that the queue is not available.
21648 * # Available queues may not be in sequential order.
21651 /* This value is applicable to CoS queues only. */
21652 uint8_t queue_id0_service_profile;
21653 /* Lossy (best-effort) */
21654 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID0_SERVICE_PROFILE_LOSSY \
21656 /* Lossless (legacy) */
21657 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID0_SERVICE_PROFILE_LOSSLESS \
21659 /* Lossless RoCE */
21660 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID0_SERVICE_PROFILE_LOSSLESS_ROCE \
21662 /* Lossy RoCE CNP */
21663 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID0_SERVICE_PROFILE_LOSSY_ROCE_CNP \
21666 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID0_SERVICE_PROFILE_LOSSLESS_NIC \
21668 /* Set to 0xFF... (All Fs) if there is no service profile specified */
21669 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID0_SERVICE_PROFILE_UNKNOWN \
21671 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID0_SERVICE_PROFILE_LAST \
21672 HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID0_SERVICE_PROFILE_UNKNOWN
21674 * ID of CoS Queue 1.
21677 * # This ID can be used on any subsequent call to an hwrm command
21678 * that takes a queue id.
21679 * # IDs must always be queried by this command before any use
21680 * by the driver or software.
21681 * # Any driver or software should not make any assumptions about
21683 * # A value of 0xff indicates that the queue is not available.
21684 * # Available queues may not be in sequential order.
21687 /* This value is applicable to CoS queues only. */
21688 uint8_t queue_id1_service_profile;
21689 /* Lossy (best-effort) */
21690 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID1_SERVICE_PROFILE_LOSSY \
21692 /* Lossless (legacy) */
21693 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID1_SERVICE_PROFILE_LOSSLESS \
21695 /* Lossless RoCE */
21696 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID1_SERVICE_PROFILE_LOSSLESS_ROCE \
21698 /* Lossy RoCE CNP */
21699 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID1_SERVICE_PROFILE_LOSSY_ROCE_CNP \
21702 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID1_SERVICE_PROFILE_LOSSLESS_NIC \
21704 /* Set to 0xFF... (All Fs) if there is no service profile specified */
21705 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID1_SERVICE_PROFILE_UNKNOWN \
21707 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID1_SERVICE_PROFILE_LAST \
21708 HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID1_SERVICE_PROFILE_UNKNOWN
21710 * ID of CoS Queue 2.
21713 * # This ID can be used on any subsequent call to an hwrm command
21714 * that takes a queue id.
21715 * # IDs must always be queried by this command before any use
21716 * by the driver or software.
21717 * # Any driver or software should not make any assumptions about
21719 * # A value of 0xff indicates that the queue is not available.
21720 * # Available queues may not be in sequential order.
21723 /* This value is applicable to CoS queues only. */
21724 uint8_t queue_id2_service_profile;
21725 /* Lossy (best-effort) */
21726 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID2_SERVICE_PROFILE_LOSSY \
21728 /* Lossless (legacy) */
21729 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID2_SERVICE_PROFILE_LOSSLESS \
21731 /* Lossless RoCE */
21732 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID2_SERVICE_PROFILE_LOSSLESS_ROCE \
21734 /* Lossy RoCE CNP */
21735 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID2_SERVICE_PROFILE_LOSSY_ROCE_CNP \
21738 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID2_SERVICE_PROFILE_LOSSLESS_NIC \
21740 /* Set to 0xFF... (All Fs) if there is no service profile specified */
21741 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID2_SERVICE_PROFILE_UNKNOWN \
21743 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID2_SERVICE_PROFILE_LAST \
21744 HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID2_SERVICE_PROFILE_UNKNOWN
21746 * ID of CoS Queue 3.
21749 * # This ID can be used on any subsequent call to an hwrm command
21750 * that takes a queue id.
21751 * # IDs must always be queried by this command before any use
21752 * by the driver or software.
21753 * # Any driver or software should not make any assumptions about
21755 * # A value of 0xff indicates that the queue is not available.
21756 * # Available queues may not be in sequential order.
21759 /* This value is applicable to CoS queues only. */
21760 uint8_t queue_id3_service_profile;
21761 /* Lossy (best-effort) */
21762 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID3_SERVICE_PROFILE_LOSSY \
21764 /* Lossless (legacy) */
21765 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID3_SERVICE_PROFILE_LOSSLESS \
21767 /* Lossless RoCE */
21768 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID3_SERVICE_PROFILE_LOSSLESS_ROCE \
21770 /* Lossy RoCE CNP */
21771 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID3_SERVICE_PROFILE_LOSSY_ROCE_CNP \
21774 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID3_SERVICE_PROFILE_LOSSLESS_NIC \
21776 /* Set to 0xFF... (All Fs) if there is no service profile specified */
21777 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID3_SERVICE_PROFILE_UNKNOWN \
21779 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID3_SERVICE_PROFILE_LAST \
21780 HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID3_SERVICE_PROFILE_UNKNOWN
21782 * ID of CoS Queue 4.
21785 * # This ID can be used on any subsequent call to an hwrm command
21786 * that takes a queue id.
21787 * # IDs must always be queried by this command before any use
21788 * by the driver or software.
21789 * # Any driver or software should not make any assumptions about
21791 * # A value of 0xff indicates that the queue is not available.
21792 * # Available queues may not be in sequential order.
21795 /* This value is applicable to CoS queues only. */
21796 uint8_t queue_id4_service_profile;
21797 /* Lossy (best-effort) */
21798 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID4_SERVICE_PROFILE_LOSSY \
21800 /* Lossless (legacy) */
21801 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID4_SERVICE_PROFILE_LOSSLESS \
21803 /* Lossless RoCE */
21804 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID4_SERVICE_PROFILE_LOSSLESS_ROCE \
21806 /* Lossy RoCE CNP */
21807 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID4_SERVICE_PROFILE_LOSSY_ROCE_CNP \
21810 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID4_SERVICE_PROFILE_LOSSLESS_NIC \
21812 /* Set to 0xFF... (All Fs) if there is no service profile specified */
21813 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID4_SERVICE_PROFILE_UNKNOWN \
21815 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID4_SERVICE_PROFILE_LAST \
21816 HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID4_SERVICE_PROFILE_UNKNOWN
21818 * ID of CoS Queue 5.
21821 * # This ID can be used on any subsequent call to an hwrm command
21822 * that takes a queue id.
21823 * # IDs must always be queried by this command before any use
21824 * by the driver or software.
21825 * # Any driver or software should not make any assumptions about
21827 * # A value of 0xff indicates that the queue is not available.
21828 * # Available queues may not be in sequential order.
21831 /* This value is applicable to CoS queues only. */
21832 uint8_t queue_id5_service_profile;
21833 /* Lossy (best-effort) */
21834 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID5_SERVICE_PROFILE_LOSSY \
21836 /* Lossless (legacy) */
21837 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID5_SERVICE_PROFILE_LOSSLESS \
21839 /* Lossless RoCE */
21840 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID5_SERVICE_PROFILE_LOSSLESS_ROCE \
21842 /* Lossy RoCE CNP */
21843 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID5_SERVICE_PROFILE_LOSSY_ROCE_CNP \
21846 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID5_SERVICE_PROFILE_LOSSLESS_NIC \
21848 /* Set to 0xFF... (All Fs) if there is no service profile specified */
21849 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID5_SERVICE_PROFILE_UNKNOWN \
21851 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID5_SERVICE_PROFILE_LAST \
21852 HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID5_SERVICE_PROFILE_UNKNOWN
21854 * ID of CoS Queue 6.
21857 * # This ID can be used on any subsequent call to an hwrm command
21858 * that takes a queue id.
21859 * # IDs must always be queried by this command before any use
21860 * by the driver or software.
21861 * # Any driver or software should not make any assumptions about
21863 * # A value of 0xff indicates that the queue is not available.
21864 * # Available queues may not be in sequential order.
21867 /* This value is applicable to CoS queues only. */
21868 uint8_t queue_id6_service_profile;
21869 /* Lossy (best-effort) */
21870 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID6_SERVICE_PROFILE_LOSSY \
21872 /* Lossless (legacy) */
21873 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID6_SERVICE_PROFILE_LOSSLESS \
21875 /* Lossless RoCE */
21876 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID6_SERVICE_PROFILE_LOSSLESS_ROCE \
21878 /* Lossy RoCE CNP */
21879 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID6_SERVICE_PROFILE_LOSSY_ROCE_CNP \
21882 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID6_SERVICE_PROFILE_LOSSLESS_NIC \
21884 /* Set to 0xFF... (All Fs) if there is no service profile specified */
21885 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID6_SERVICE_PROFILE_UNKNOWN \
21887 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID6_SERVICE_PROFILE_LAST \
21888 HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID6_SERVICE_PROFILE_UNKNOWN
21890 * ID of CoS Queue 7.
21893 * # This ID can be used on any subsequent call to an hwrm command
21894 * that takes a queue id.
21895 * # IDs must always be queried by this command before any use
21896 * by the driver or software.
21897 * # Any driver or software should not make any assumptions about
21899 * # A value of 0xff indicates that the queue is not available.
21900 * # Available queues may not be in sequential order.
21903 /* This value is applicable to CoS queues only. */
21904 uint8_t queue_id7_service_profile;
21905 /* Lossy (best-effort) */
21906 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID7_SERVICE_PROFILE_LOSSY \
21908 /* Lossless (legacy) */
21909 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID7_SERVICE_PROFILE_LOSSLESS \
21911 /* Lossless RoCE */
21912 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID7_SERVICE_PROFILE_LOSSLESS_ROCE \
21914 /* Lossy RoCE CNP */
21915 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID7_SERVICE_PROFILE_LOSSY_ROCE_CNP \
21918 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID7_SERVICE_PROFILE_LOSSLESS_NIC \
21920 /* Set to 0xFF... (All Fs) if there is no service profile specified */
21921 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID7_SERVICE_PROFILE_UNKNOWN \
21923 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID7_SERVICE_PROFILE_LAST \
21924 HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID7_SERVICE_PROFILE_UNKNOWN
21927 * Up to 16 bytes of null padded ASCII string describing this queue.
21928 * The queue name includes a CoS queue index and, in some cases, text
21929 * that distinguishes the queue from other queues in the group.
21931 char qid0_name[16];
21932 /* Up to 16 bytes of null padded ASCII string describing this queue. */
21933 char qid1_name[16];
21934 /* Up to 16 bytes of null padded ASCII string describing this queue. */
21935 char qid2_name[16];
21936 /* Up to 16 bytes of null padded ASCII string describing this queue. */
21937 char qid3_name[16];
21938 /* Up to 16 bytes of null padded ASCII string describing this queue. */
21939 char qid4_name[16];
21940 /* Up to 16 bytes of null padded ASCII string describing this queue. */
21941 char qid5_name[16];
21942 /* Up to 16 bytes of null padded ASCII string describing this queue. */
21943 char qid6_name[16];
21944 /* Up to 16 bytes of null padded ASCII string describing this queue. */
21945 char qid7_name[16];
21946 uint8_t unused_1[7];
21948 * This field is used in Output records to indicate that the output
21949 * is completely written to RAM. This field should be read as '1'
21950 * to indicate that the output has been completely written.
21951 * When writing a command completion or response to an internal processor,
21952 * the order of writes has to be such that this field is written last.
21957 /*******************
21958 * hwrm_queue_qcfg *
21959 *******************/
21962 /* hwrm_queue_qcfg_input (size:192b/24B) */
21963 struct hwrm_queue_qcfg_input {
21964 /* The HWRM command request type. */
21967 * The completion ring to send the completion event on. This should
21968 * be the NQ ID returned from the `nq_alloc` HWRM command.
21970 uint16_t cmpl_ring;
21972 * The sequence ID is used by the driver for tracking multiple
21973 * commands. This ID is treated as opaque data by the firmware and
21974 * the value is returned in the `hwrm_resp_hdr` upon completion.
21978 * The target ID of the command:
21979 * * 0x0-0xFFF8 - The function ID
21980 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
21981 * * 0xFFFD - Reserved for user-space HWRM interface
21984 uint16_t target_id;
21986 * A physical address pointer pointing to a host buffer that the
21987 * command's response data will be written. This can be either a host
21988 * physical address (HPA) or a guest physical address (GPA) and must
21989 * point to a physically contiguous block of memory.
21991 uint64_t resp_addr;
21994 * Enumeration denoting the RX, TX type of the resource.
21995 * This enumeration is used for resources that are similar for both
21996 * TX and RX paths of the chip.
21998 #define HWRM_QUEUE_QCFG_INPUT_FLAGS_PATH UINT32_C(0x1)
22000 #define HWRM_QUEUE_QCFG_INPUT_FLAGS_PATH_TX UINT32_C(0x0)
22002 #define HWRM_QUEUE_QCFG_INPUT_FLAGS_PATH_RX UINT32_C(0x1)
22003 #define HWRM_QUEUE_QCFG_INPUT_FLAGS_PATH_LAST \
22004 HWRM_QUEUE_QCFG_INPUT_FLAGS_PATH_RX
22005 /* Queue ID of the queue. */
22009 /* hwrm_queue_qcfg_output (size:128b/16B) */
22010 struct hwrm_queue_qcfg_output {
22011 /* The specific error status for the command. */
22012 uint16_t error_code;
22013 /* The HWRM command request type. */
22015 /* The sequence ID from the original command. */
22017 /* The length of the response data in number of bytes. */
22020 * This value is the estimate packet length used in the
22023 uint32_t queue_len;
22024 /* This value is applicable to CoS queues only. */
22025 uint8_t service_profile;
22026 /* Lossy (best-effort) */
22027 #define HWRM_QUEUE_QCFG_OUTPUT_SERVICE_PROFILE_LOSSY UINT32_C(0x0)
22029 #define HWRM_QUEUE_QCFG_OUTPUT_SERVICE_PROFILE_LOSSLESS UINT32_C(0x1)
22030 /* Set to 0xFF... (All Fs) if there is no service profile specified */
22031 #define HWRM_QUEUE_QCFG_OUTPUT_SERVICE_PROFILE_UNKNOWN UINT32_C(0xff)
22032 #define HWRM_QUEUE_QCFG_OUTPUT_SERVICE_PROFILE_LAST \
22033 HWRM_QUEUE_QCFG_OUTPUT_SERVICE_PROFILE_UNKNOWN
22034 /* Information about queue configuration. */
22035 uint8_t queue_cfg_info;
22037 * If this flag is set to '1', then the queue is
22038 * configured asymmetrically on TX and RX sides.
22039 * If this flag is set to '0', then this queue is
22040 * configured symmetrically on TX and RX sides.
22042 #define HWRM_QUEUE_QCFG_OUTPUT_QUEUE_CFG_INFO_ASYM_CFG \
22046 * This field is used in Output records to indicate that the output
22047 * is completely written to RAM. This field should be read as '1'
22048 * to indicate that the output has been completely written.
22049 * When writing a command completion or response to an internal processor,
22050 * the order of writes has to be such that this field is written last.
22055 /******************
22057 ******************/
22060 /* hwrm_queue_cfg_input (size:320b/40B) */
22061 struct hwrm_queue_cfg_input {
22062 /* The HWRM command request type. */
22065 * The completion ring to send the completion event on. This should
22066 * be the NQ ID returned from the `nq_alloc` HWRM command.
22068 uint16_t cmpl_ring;
22070 * The sequence ID is used by the driver for tracking multiple
22071 * commands. This ID is treated as opaque data by the firmware and
22072 * the value is returned in the `hwrm_resp_hdr` upon completion.
22076 * The target ID of the command:
22077 * * 0x0-0xFFF8 - The function ID
22078 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
22079 * * 0xFFFD - Reserved for user-space HWRM interface
22082 uint16_t target_id;
22084 * A physical address pointer pointing to a host buffer that the
22085 * command's response data will be written. This can be either a host
22086 * physical address (HPA) or a guest physical address (GPA) and must
22087 * point to a physically contiguous block of memory.
22089 uint64_t resp_addr;
22092 * Enumeration denoting the RX, TX, or both directions applicable to the resource.
22093 * This enumeration is used for resources that are similar for both
22094 * TX and RX paths of the chip.
22096 #define HWRM_QUEUE_CFG_INPUT_FLAGS_PATH_MASK UINT32_C(0x3)
22097 #define HWRM_QUEUE_CFG_INPUT_FLAGS_PATH_SFT 0
22099 #define HWRM_QUEUE_CFG_INPUT_FLAGS_PATH_TX UINT32_C(0x0)
22101 #define HWRM_QUEUE_CFG_INPUT_FLAGS_PATH_RX UINT32_C(0x1)
22102 /* Bi-directional (Symmetrically applicable to TX and RX paths) */
22103 #define HWRM_QUEUE_CFG_INPUT_FLAGS_PATH_BIDIR UINT32_C(0x2)
22104 #define HWRM_QUEUE_CFG_INPUT_FLAGS_PATH_LAST \
22105 HWRM_QUEUE_CFG_INPUT_FLAGS_PATH_BIDIR
22108 * This bit must be '1' for the dflt_len field to be
22111 #define HWRM_QUEUE_CFG_INPUT_ENABLES_DFLT_LEN UINT32_C(0x1)
22113 * This bit must be '1' for the service_profile field to be
22116 #define HWRM_QUEUE_CFG_INPUT_ENABLES_SERVICE_PROFILE UINT32_C(0x2)
22117 /* Queue ID of queue that is to be configured by this function. */
22120 * This value is a the estimate packet length used in the
22122 * Set to 0xFF... (All Fs) to not adjust this value.
22125 /* This value is applicable to CoS queues only. */
22126 uint8_t service_profile;
22127 /* Lossy (best-effort) */
22128 #define HWRM_QUEUE_CFG_INPUT_SERVICE_PROFILE_LOSSY UINT32_C(0x0)
22130 #define HWRM_QUEUE_CFG_INPUT_SERVICE_PROFILE_LOSSLESS UINT32_C(0x1)
22131 /* Set to 0xFF... (All Fs) if there is no service profile specified */
22132 #define HWRM_QUEUE_CFG_INPUT_SERVICE_PROFILE_UNKNOWN UINT32_C(0xff)
22133 #define HWRM_QUEUE_CFG_INPUT_SERVICE_PROFILE_LAST \
22134 HWRM_QUEUE_CFG_INPUT_SERVICE_PROFILE_UNKNOWN
22135 uint8_t unused_0[7];
22138 /* hwrm_queue_cfg_output (size:128b/16B) */
22139 struct hwrm_queue_cfg_output {
22140 /* The specific error status for the command. */
22141 uint16_t error_code;
22142 /* The HWRM command request type. */
22144 /* The sequence ID from the original command. */
22146 /* The length of the response data in number of bytes. */
22148 uint8_t unused_0[7];
22150 * This field is used in Output records to indicate that the output
22151 * is completely written to RAM. This field should be read as '1'
22152 * to indicate that the output has been completely written.
22153 * When writing a command completion or response to an internal processor,
22154 * the order of writes has to be such that this field is written last.
22159 /*****************************
22160 * hwrm_queue_pfcenable_qcfg *
22161 *****************************/
22164 /* hwrm_queue_pfcenable_qcfg_input (size:192b/24B) */
22165 struct hwrm_queue_pfcenable_qcfg_input {
22166 /* The HWRM command request type. */
22169 * The completion ring to send the completion event on. This should
22170 * be the NQ ID returned from the `nq_alloc` HWRM command.
22172 uint16_t cmpl_ring;
22174 * The sequence ID is used by the driver for tracking multiple
22175 * commands. This ID is treated as opaque data by the firmware and
22176 * the value is returned in the `hwrm_resp_hdr` upon completion.
22180 * The target ID of the command:
22181 * * 0x0-0xFFF8 - The function ID
22182 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
22183 * * 0xFFFD - Reserved for user-space HWRM interface
22186 uint16_t target_id;
22188 * A physical address pointer pointing to a host buffer that the
22189 * command's response data will be written. This can be either a host
22190 * physical address (HPA) or a guest physical address (GPA) and must
22191 * point to a physically contiguous block of memory.
22193 uint64_t resp_addr;
22195 * Port ID of port for which the table is being configured.
22196 * The HWRM needs to check whether this function is allowed
22197 * to configure pri2cos mapping on this port.
22200 uint8_t unused_0[6];
22203 /* hwrm_queue_pfcenable_qcfg_output (size:128b/16B) */
22204 struct hwrm_queue_pfcenable_qcfg_output {
22205 /* The specific error status for the command. */
22206 uint16_t error_code;
22207 /* The HWRM command request type. */
22209 /* The sequence ID from the original command. */
22211 /* The length of the response data in number of bytes. */
22214 /* If set to 1, then PFC is enabled on PRI 0. */
22215 #define HWRM_QUEUE_PFCENABLE_QCFG_OUTPUT_FLAGS_PRI0_PFC_ENABLED \
22217 /* If set to 1, then PFC is enabled on PRI 1. */
22218 #define HWRM_QUEUE_PFCENABLE_QCFG_OUTPUT_FLAGS_PRI1_PFC_ENABLED \
22220 /* If set to 1, then PFC is enabled on PRI 2. */
22221 #define HWRM_QUEUE_PFCENABLE_QCFG_OUTPUT_FLAGS_PRI2_PFC_ENABLED \
22223 /* If set to 1, then PFC is enabled on PRI 3. */
22224 #define HWRM_QUEUE_PFCENABLE_QCFG_OUTPUT_FLAGS_PRI3_PFC_ENABLED \
22226 /* If set to 1, then PFC is enabled on PRI 4. */
22227 #define HWRM_QUEUE_PFCENABLE_QCFG_OUTPUT_FLAGS_PRI4_PFC_ENABLED \
22229 /* If set to 1, then PFC is enabled on PRI 5. */
22230 #define HWRM_QUEUE_PFCENABLE_QCFG_OUTPUT_FLAGS_PRI5_PFC_ENABLED \
22232 /* If set to 1, then PFC is enabled on PRI 6. */
22233 #define HWRM_QUEUE_PFCENABLE_QCFG_OUTPUT_FLAGS_PRI6_PFC_ENABLED \
22235 /* If set to 1, then PFC is enabled on PRI 7. */
22236 #define HWRM_QUEUE_PFCENABLE_QCFG_OUTPUT_FLAGS_PRI7_PFC_ENABLED \
22238 /* If set to 1, then PFC WatchDog is requested to be enabled on PRI0. */
22239 #define HWRM_QUEUE_PFCENABLE_QCFG_OUTPUT_FLAGS_PRI0_PFC_WATCHDOG_ENABLED \
22241 /* If set to 1, then PFC WatchDog is requested to be enabled on PRI1. */
22242 #define HWRM_QUEUE_PFCENABLE_QCFG_OUTPUT_FLAGS_PRI1_PFC_WATCHDOG_ENABLED \
22244 /* If set to 1, then PFC WatchDog is requested to be enabled on PRI2. */
22245 #define HWRM_QUEUE_PFCENABLE_QCFG_OUTPUT_FLAGS_PRI2_PFC_WATCHDOG_ENABLED \
22247 /* If set to 1, then PFC WatchDog is requested to be enabled on PRI3. */
22248 #define HWRM_QUEUE_PFCENABLE_QCFG_OUTPUT_FLAGS_PRI3_PFC_WATCHDOG_ENABLED \
22250 /* If set to 1, then PFC WatchDog is requested to be enabled on PRI4. */
22251 #define HWRM_QUEUE_PFCENABLE_QCFG_OUTPUT_FLAGS_PRI4_PFC_WATCHDOG_ENABLED \
22253 /* If set to 1, then PFC WatchDog is requested to be enabled on PRI5. */
22254 #define HWRM_QUEUE_PFCENABLE_QCFG_OUTPUT_FLAGS_PRI5_PFC_WATCHDOG_ENABLED \
22256 /* If set to 1, then PFC WatchDog is requested to be enabled on PRI6. */
22257 #define HWRM_QUEUE_PFCENABLE_QCFG_OUTPUT_FLAGS_PRI6_PFC_WATCHDOG_ENABLED \
22259 /* If set to 1, then PFC WatchDog is requested to be enabled on PRI7. */
22260 #define HWRM_QUEUE_PFCENABLE_QCFG_OUTPUT_FLAGS_PRI7_PFC_WATCHDOG_ENABLED \
22262 uint8_t unused_0[3];
22264 * This field is used in Output records to indicate that the output
22265 * is completely written to RAM. This field should be read as '1'
22266 * to indicate that the output has been completely written.
22267 * When writing a command completion or response to an internal processor,
22268 * the order of writes has to be such that this field is written last.
22273 /****************************
22274 * hwrm_queue_pfcenable_cfg *
22275 ****************************/
22278 /* hwrm_queue_pfcenable_cfg_input (size:192b/24B) */
22279 struct hwrm_queue_pfcenable_cfg_input {
22280 /* The HWRM command request type. */
22283 * The completion ring to send the completion event on. This should
22284 * be the NQ ID returned from the `nq_alloc` HWRM command.
22286 uint16_t cmpl_ring;
22288 * The sequence ID is used by the driver for tracking multiple
22289 * commands. This ID is treated as opaque data by the firmware and
22290 * the value is returned in the `hwrm_resp_hdr` upon completion.
22294 * The target ID of the command:
22295 * * 0x0-0xFFF8 - The function ID
22296 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
22297 * * 0xFFFD - Reserved for user-space HWRM interface
22300 uint16_t target_id;
22302 * A physical address pointer pointing to a host buffer that the
22303 * command's response data will be written. This can be either a host
22304 * physical address (HPA) or a guest physical address (GPA) and must
22305 * point to a physically contiguous block of memory.
22307 uint64_t resp_addr;
22309 /* If set to 1, then PFC is requested to be enabled on PRI 0. */
22310 #define HWRM_QUEUE_PFCENABLE_CFG_INPUT_FLAGS_PRI0_PFC_ENABLED \
22312 /* If set to 1, then PFC is requested to be enabled on PRI 1. */
22313 #define HWRM_QUEUE_PFCENABLE_CFG_INPUT_FLAGS_PRI1_PFC_ENABLED \
22315 /* If set to 1, then PFC is requested to be enabled on PRI 2. */
22316 #define HWRM_QUEUE_PFCENABLE_CFG_INPUT_FLAGS_PRI2_PFC_ENABLED \
22318 /* If set to 1, then PFC is requested to be enabled on PRI 3. */
22319 #define HWRM_QUEUE_PFCENABLE_CFG_INPUT_FLAGS_PRI3_PFC_ENABLED \
22321 /* If set to 1, then PFC is requested to be enabled on PRI 4. */
22322 #define HWRM_QUEUE_PFCENABLE_CFG_INPUT_FLAGS_PRI4_PFC_ENABLED \
22324 /* If set to 1, then PFC is requested to be enabled on PRI 5. */
22325 #define HWRM_QUEUE_PFCENABLE_CFG_INPUT_FLAGS_PRI5_PFC_ENABLED \
22327 /* If set to 1, then PFC is requested to be enabled on PRI 6. */
22328 #define HWRM_QUEUE_PFCENABLE_CFG_INPUT_FLAGS_PRI6_PFC_ENABLED \
22330 /* If set to 1, then PFC is requested to be enabled on PRI 7. */
22331 #define HWRM_QUEUE_PFCENABLE_CFG_INPUT_FLAGS_PRI7_PFC_ENABLED \
22333 /* If set to 1, then PFC WatchDog is requested to be enabled on PRI0. */
22334 #define HWRM_QUEUE_PFCENABLE_CFG_INPUT_FLAGS_PRI0_PFC_WATCHDOG_ENABLED \
22336 /* If set to 1, then PFC WatchDog is requested to be enabled on PRI1. */
22337 #define HWRM_QUEUE_PFCENABLE_CFG_INPUT_FLAGS_PRI1_PFC_WATCHDOG_ENABLED \
22339 /* If set to 1, then PFC WatchDog is requested to be enabled on PRI2. */
22340 #define HWRM_QUEUE_PFCENABLE_CFG_INPUT_FLAGS_PRI2_PFC_WATCHDOG_ENABLED \
22342 /* If set to 1, then PFC WatchDog is requested to be enabled on PRI3. */
22343 #define HWRM_QUEUE_PFCENABLE_CFG_INPUT_FLAGS_PRI3_PFC_WATCHDOG_ENABLED \
22345 /* If set to 1, then PFC WatchDog is requested to be enabled on PRI4. */
22346 #define HWRM_QUEUE_PFCENABLE_CFG_INPUT_FLAGS_PRI4_PFC_WATCHDOG_ENABLED \
22348 /* If set to 1, then PFC WatchDog is requested to be enabled on PRI5. */
22349 #define HWRM_QUEUE_PFCENABLE_CFG_INPUT_FLAGS_PRI5_PFC_WATCHDOG_ENABLED \
22351 /* If set to 1, then PFC WatchDog is requested to be enabled on PRI6. */
22352 #define HWRM_QUEUE_PFCENABLE_CFG_INPUT_FLAGS_PRI6_PFC_WATCHDOG_ENABLED \
22354 /* If set to 1, then PFC WatchDog is requested to be enabled on PRI7. */
22355 #define HWRM_QUEUE_PFCENABLE_CFG_INPUT_FLAGS_PRI7_PFC_WATCHDOG_ENABLED \
22358 * Port ID of port for which the table is being configured.
22359 * The HWRM needs to check whether this function is allowed
22360 * to configure pri2cos mapping on this port.
22363 uint8_t unused_0[2];
22366 /* hwrm_queue_pfcenable_cfg_output (size:128b/16B) */
22367 struct hwrm_queue_pfcenable_cfg_output {
22368 /* The specific error status for the command. */
22369 uint16_t error_code;
22370 /* The HWRM command request type. */
22372 /* The sequence ID from the original command. */
22374 /* The length of the response data in number of bytes. */
22376 uint8_t unused_0[7];
22378 * This field is used in Output records to indicate that the output
22379 * is completely written to RAM. This field should be read as '1'
22380 * to indicate that the output has been completely written.
22381 * When writing a command completion or response to an internal processor,
22382 * the order of writes has to be such that this field is written last.
22387 /***************************
22388 * hwrm_queue_pri2cos_qcfg *
22389 ***************************/
22392 /* hwrm_queue_pri2cos_qcfg_input (size:192b/24B) */
22393 struct hwrm_queue_pri2cos_qcfg_input {
22394 /* The HWRM command request type. */
22397 * The completion ring to send the completion event on. This should
22398 * be the NQ ID returned from the `nq_alloc` HWRM command.
22400 uint16_t cmpl_ring;
22402 * The sequence ID is used by the driver for tracking multiple
22403 * commands. This ID is treated as opaque data by the firmware and
22404 * the value is returned in the `hwrm_resp_hdr` upon completion.
22408 * The target ID of the command:
22409 * * 0x0-0xFFF8 - The function ID
22410 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
22411 * * 0xFFFD - Reserved for user-space HWRM interface
22414 uint16_t target_id;
22416 * A physical address pointer pointing to a host buffer that the
22417 * command's response data will be written. This can be either a host
22418 * physical address (HPA) or a guest physical address (GPA) and must
22419 * point to a physically contiguous block of memory.
22421 uint64_t resp_addr;
22424 * Enumeration denoting the RX, TX type of the resource.
22425 * This enumeration is used for resources that are similar for both
22426 * TX and RX paths of the chip.
22428 #define HWRM_QUEUE_PRI2COS_QCFG_INPUT_FLAGS_PATH UINT32_C(0x1)
22430 #define HWRM_QUEUE_PRI2COS_QCFG_INPUT_FLAGS_PATH_TX UINT32_C(0x0)
22432 #define HWRM_QUEUE_PRI2COS_QCFG_INPUT_FLAGS_PATH_RX UINT32_C(0x1)
22433 #define HWRM_QUEUE_PRI2COS_QCFG_INPUT_FLAGS_PATH_LAST \
22434 HWRM_QUEUE_PRI2COS_QCFG_INPUT_FLAGS_PATH_RX
22436 * When this bit is set to '0', the query is
22437 * for PRI from tunnel headers.
22438 * When this bit is set to '1', the query is
22439 * for PRI from inner packet headers.
22441 #define HWRM_QUEUE_PRI2COS_QCFG_INPUT_FLAGS_IVLAN UINT32_C(0x2)
22443 * Port ID of port for which the table is being configured.
22444 * The HWRM needs to check whether this function is allowed
22445 * to configure pri2cos mapping on this port.
22448 uint8_t unused_0[3];
22451 /* hwrm_queue_pri2cos_qcfg_output (size:192b/24B) */
22452 struct hwrm_queue_pri2cos_qcfg_output {
22453 /* The specific error status for the command. */
22454 uint16_t error_code;
22455 /* The HWRM command request type. */
22457 /* The sequence ID from the original command. */
22459 /* The length of the response data in number of bytes. */
22462 * CoS Queue assigned to priority 0. This value can only
22463 * be changed before traffic has started.
22464 * A value of 0xff indicates that no CoS queue is assigned to the
22465 * specified priority.
22467 uint8_t pri0_cos_queue_id;
22469 * CoS Queue assigned to priority 1. This value can only
22470 * be changed before traffic has started.
22471 * A value of 0xff indicates that no CoS queue is assigned to the
22472 * specified priority.
22474 uint8_t pri1_cos_queue_id;
22476 * CoS Queue assigned to priority 2. This value can only
22477 * be changed before traffic has started.
22478 * A value of 0xff indicates that no CoS queue is assigned to the
22479 * specified priority.
22481 uint8_t pri2_cos_queue_id;
22483 * CoS Queue assigned to priority 3. This value can only
22484 * be changed before traffic has started.
22485 * A value of 0xff indicates that no CoS queue is assigned to the
22486 * specified priority.
22488 uint8_t pri3_cos_queue_id;
22490 * CoS Queue assigned to priority 4. This value can only
22491 * be changed before traffic has started.
22492 * A value of 0xff indicates that no CoS queue is assigned to the
22493 * specified priority.
22495 uint8_t pri4_cos_queue_id;
22497 * CoS Queue assigned to priority 5. This value can only
22498 * be changed before traffic has started.
22499 * A value of 0xff indicates that no CoS queue is assigned to the
22500 * specified priority.
22502 uint8_t pri5_cos_queue_id;
22504 * CoS Queue assigned to priority 6. This value can only
22505 * be changed before traffic has started.
22506 * A value of 0xff indicates that no CoS queue is assigned to the
22507 * specified priority.
22509 uint8_t pri6_cos_queue_id;
22511 * CoS Queue assigned to priority 7. This value can only
22512 * be changed before traffic has started.
22513 * A value of 0xff indicates that no CoS queue is assigned to the
22514 * specified priority.
22516 uint8_t pri7_cos_queue_id;
22517 /* Information about queue configuration. */
22518 uint8_t queue_cfg_info;
22520 * If this flag is set to '1', then the PRI to CoS
22521 * configuration is asymmetric on TX and RX sides.
22522 * If this flag is set to '0', then PRI to CoS configuration
22523 * is symmetric on TX and RX sides.
22525 #define HWRM_QUEUE_PRI2COS_QCFG_OUTPUT_QUEUE_CFG_INFO_ASYM_CFG \
22527 uint8_t unused_0[6];
22529 * This field is used in Output records to indicate that the output
22530 * is completely written to RAM. This field should be read as '1'
22531 * to indicate that the output has been completely written.
22532 * When writing a command completion or response to an internal processor,
22533 * the order of writes has to be such that this field is written last.
22538 /**************************
22539 * hwrm_queue_pri2cos_cfg *
22540 **************************/
22543 /* hwrm_queue_pri2cos_cfg_input (size:320b/40B) */
22544 struct hwrm_queue_pri2cos_cfg_input {
22545 /* The HWRM command request type. */
22548 * The completion ring to send the completion event on. This should
22549 * be the NQ ID returned from the `nq_alloc` HWRM command.
22551 uint16_t cmpl_ring;
22553 * The sequence ID is used by the driver for tracking multiple
22554 * commands. This ID is treated as opaque data by the firmware and
22555 * the value is returned in the `hwrm_resp_hdr` upon completion.
22559 * The target ID of the command:
22560 * * 0x0-0xFFF8 - The function ID
22561 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
22562 * * 0xFFFD - Reserved for user-space HWRM interface
22565 uint16_t target_id;
22567 * A physical address pointer pointing to a host buffer that the
22568 * command's response data will be written. This can be either a host
22569 * physical address (HPA) or a guest physical address (GPA) and must
22570 * point to a physically contiguous block of memory.
22572 uint64_t resp_addr;
22575 * Enumeration denoting the RX, TX, or both directions applicable to the resource.
22576 * This enumeration is used for resources that are similar for both
22577 * TX and RX paths of the chip.
22579 #define HWRM_QUEUE_PRI2COS_CFG_INPUT_FLAGS_PATH_MASK UINT32_C(0x3)
22580 #define HWRM_QUEUE_PRI2COS_CFG_INPUT_FLAGS_PATH_SFT 0
22582 #define HWRM_QUEUE_PRI2COS_CFG_INPUT_FLAGS_PATH_TX UINT32_C(0x0)
22584 #define HWRM_QUEUE_PRI2COS_CFG_INPUT_FLAGS_PATH_RX UINT32_C(0x1)
22585 /* Bi-directional (Symmetrically applicable to TX and RX paths) */
22586 #define HWRM_QUEUE_PRI2COS_CFG_INPUT_FLAGS_PATH_BIDIR UINT32_C(0x2)
22587 #define HWRM_QUEUE_PRI2COS_CFG_INPUT_FLAGS_PATH_LAST \
22588 HWRM_QUEUE_PRI2COS_CFG_INPUT_FLAGS_PATH_BIDIR
22590 * When this bit is set to '0', the mapping is requested
22591 * for PRI from tunnel headers.
22592 * When this bit is set to '1', the mapping is requested
22593 * for PRI from inner packet headers.
22595 #define HWRM_QUEUE_PRI2COS_CFG_INPUT_FLAGS_IVLAN UINT32_C(0x4)
22598 * This bit must be '1' for the pri0_cos_queue_id field to be
22601 #define HWRM_QUEUE_PRI2COS_CFG_INPUT_ENABLES_PRI0_COS_QUEUE_ID \
22604 * This bit must be '1' for the pri1_cos_queue_id field to be
22607 #define HWRM_QUEUE_PRI2COS_CFG_INPUT_ENABLES_PRI1_COS_QUEUE_ID \
22610 * This bit must be '1' for the pri2_cos_queue_id field to be
22613 #define HWRM_QUEUE_PRI2COS_CFG_INPUT_ENABLES_PRI2_COS_QUEUE_ID \
22616 * This bit must be '1' for the pri3_cos_queue_id field to be
22619 #define HWRM_QUEUE_PRI2COS_CFG_INPUT_ENABLES_PRI3_COS_QUEUE_ID \
22622 * This bit must be '1' for the pri4_cos_queue_id field to be
22625 #define HWRM_QUEUE_PRI2COS_CFG_INPUT_ENABLES_PRI4_COS_QUEUE_ID \
22628 * This bit must be '1' for the pri5_cos_queue_id field to be
22631 #define HWRM_QUEUE_PRI2COS_CFG_INPUT_ENABLES_PRI5_COS_QUEUE_ID \
22634 * This bit must be '1' for the pri6_cos_queue_id field to be
22637 #define HWRM_QUEUE_PRI2COS_CFG_INPUT_ENABLES_PRI6_COS_QUEUE_ID \
22640 * This bit must be '1' for the pri7_cos_queue_id field to be
22643 #define HWRM_QUEUE_PRI2COS_CFG_INPUT_ENABLES_PRI7_COS_QUEUE_ID \
22646 * Port ID of port for which the table is being configured.
22647 * The HWRM needs to check whether this function is allowed
22648 * to configure pri2cos mapping on this port.
22652 * CoS Queue assigned to priority 0. This value can only
22653 * be changed before traffic has started.
22655 uint8_t pri0_cos_queue_id;
22657 * CoS Queue assigned to priority 1. This value can only
22658 * be changed before traffic has started.
22660 uint8_t pri1_cos_queue_id;
22662 * CoS Queue assigned to priority 2 This value can only
22663 * be changed before traffic has started.
22665 uint8_t pri2_cos_queue_id;
22667 * CoS Queue assigned to priority 3. This value can only
22668 * be changed before traffic has started.
22670 uint8_t pri3_cos_queue_id;
22672 * CoS Queue assigned to priority 4. This value can only
22673 * be changed before traffic has started.
22675 uint8_t pri4_cos_queue_id;
22677 * CoS Queue assigned to priority 5. This value can only
22678 * be changed before traffic has started.
22680 uint8_t pri5_cos_queue_id;
22682 * CoS Queue assigned to priority 6. This value can only
22683 * be changed before traffic has started.
22685 uint8_t pri6_cos_queue_id;
22687 * CoS Queue assigned to priority 7. This value can only
22688 * be changed before traffic has started.
22690 uint8_t pri7_cos_queue_id;
22691 uint8_t unused_0[7];
22694 /* hwrm_queue_pri2cos_cfg_output (size:128b/16B) */
22695 struct hwrm_queue_pri2cos_cfg_output {
22696 /* The specific error status for the command. */
22697 uint16_t error_code;
22698 /* The HWRM command request type. */
22700 /* The sequence ID from the original command. */
22702 /* The length of the response data in number of bytes. */
22704 uint8_t unused_0[7];
22706 * This field is used in Output records to indicate that the output
22707 * is completely written to RAM. This field should be read as '1'
22708 * to indicate that the output has been completely written.
22709 * When writing a command completion or response to an internal processor,
22710 * the order of writes has to be such that this field is written last.
22715 /**************************
22716 * hwrm_queue_cos2bw_qcfg *
22717 **************************/
22720 /* hwrm_queue_cos2bw_qcfg_input (size:192b/24B) */
22721 struct hwrm_queue_cos2bw_qcfg_input {
22722 /* The HWRM command request type. */
22725 * The completion ring to send the completion event on. This should
22726 * be the NQ ID returned from the `nq_alloc` HWRM command.
22728 uint16_t cmpl_ring;
22730 * The sequence ID is used by the driver for tracking multiple
22731 * commands. This ID is treated as opaque data by the firmware and
22732 * the value is returned in the `hwrm_resp_hdr` upon completion.
22736 * The target ID of the command:
22737 * * 0x0-0xFFF8 - The function ID
22738 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
22739 * * 0xFFFD - Reserved for user-space HWRM interface
22742 uint16_t target_id;
22744 * A physical address pointer pointing to a host buffer that the
22745 * command's response data will be written. This can be either a host
22746 * physical address (HPA) or a guest physical address (GPA) and must
22747 * point to a physically contiguous block of memory.
22749 uint64_t resp_addr;
22751 * Port ID of port for which the table is being configured.
22752 * The HWRM needs to check whether this function is allowed
22753 * to configure TC BW assignment on this port.
22756 uint8_t unused_0[6];
22759 /* hwrm_queue_cos2bw_qcfg_output (size:896b/112B) */
22760 struct hwrm_queue_cos2bw_qcfg_output {
22761 /* The specific error status for the command. */
22762 uint16_t error_code;
22763 /* The HWRM command request type. */
22765 /* The sequence ID from the original command. */
22767 /* The length of the response data in number of bytes. */
22769 /* ID of CoS Queue 0. */
22774 * Minimum BW allocated to CoS Queue.
22775 * The HWRM will translate this value into byte counter and
22776 * time interval used for this COS inside the device.
22778 uint32_t queue_id0_min_bw;
22779 /* The bandwidth value. */
22780 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MIN_BW_BW_VALUE_MASK \
22781 UINT32_C(0xfffffff)
22782 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MIN_BW_BW_VALUE_SFT \
22784 /* The granularity of the value (bits or bytes). */
22785 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MIN_BW_SCALE \
22786 UINT32_C(0x10000000)
22787 /* Value is in bits. */
22788 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MIN_BW_SCALE_BITS \
22789 (UINT32_C(0x0) << 28)
22790 /* Value is in bytes. */
22791 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MIN_BW_SCALE_BYTES \
22792 (UINT32_C(0x1) << 28)
22793 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MIN_BW_SCALE_LAST \
22794 HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MIN_BW_SCALE_BYTES
22795 /* bw_value_unit is 3 b */
22796 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_MASK \
22797 UINT32_C(0xe0000000)
22798 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_SFT \
22800 /* Value is in Mb or MB (base 10). */
22801 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_MEGA \
22802 (UINT32_C(0x0) << 29)
22803 /* Value is in Kb or KB (base 10). */
22804 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_KILO \
22805 (UINT32_C(0x2) << 29)
22806 /* Value is in bits or bytes. */
22807 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_BASE \
22808 (UINT32_C(0x4) << 29)
22809 /* Value is in Gb or GB (base 10). */
22810 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_GIGA \
22811 (UINT32_C(0x6) << 29)
22812 /* Value is in 1/100th of a percentage of total bandwidth. */
22813 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 \
22814 (UINT32_C(0x1) << 29)
22816 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_INVALID \
22817 (UINT32_C(0x7) << 29)
22818 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_LAST \
22819 HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_INVALID
22821 * Maximum BW allocated to CoS Queue.
22822 * The HWRM will translate this value into byte counter and
22823 * time interval used for this COS inside the device.
22825 uint32_t queue_id0_max_bw;
22826 /* The bandwidth value. */
22827 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MAX_BW_BW_VALUE_MASK \
22828 UINT32_C(0xfffffff)
22829 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MAX_BW_BW_VALUE_SFT \
22831 /* The granularity of the value (bits or bytes). */
22832 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MAX_BW_SCALE \
22833 UINT32_C(0x10000000)
22834 /* Value is in bits. */
22835 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MAX_BW_SCALE_BITS \
22836 (UINT32_C(0x0) << 28)
22837 /* Value is in bytes. */
22838 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MAX_BW_SCALE_BYTES \
22839 (UINT32_C(0x1) << 28)
22840 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MAX_BW_SCALE_LAST \
22841 HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MAX_BW_SCALE_BYTES
22842 /* bw_value_unit is 3 b */
22843 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_MASK \
22844 UINT32_C(0xe0000000)
22845 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_SFT \
22847 /* Value is in Mb or MB (base 10). */
22848 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_MEGA \
22849 (UINT32_C(0x0) << 29)
22850 /* Value is in Kb or KB (base 10). */
22851 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_KILO \
22852 (UINT32_C(0x2) << 29)
22853 /* Value is in bits or bytes. */
22854 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_BASE \
22855 (UINT32_C(0x4) << 29)
22856 /* Value is in Gb or GB (base 10). */
22857 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_GIGA \
22858 (UINT32_C(0x6) << 29)
22859 /* Value is in 1/100th of a percentage of total bandwidth. */
22860 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 \
22861 (UINT32_C(0x1) << 29)
22863 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_INVALID \
22864 (UINT32_C(0x7) << 29)
22865 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_LAST \
22866 HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_INVALID
22867 /* Transmission Selection Algorithm (TSA) for CoS Queue. */
22868 uint8_t queue_id0_tsa_assign;
22869 /* Strict Priority */
22870 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_TSA_ASSIGN_SP \
22872 /* Enhanced Transmission Selection */
22873 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_TSA_ASSIGN_ETS \
22876 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_TSA_ASSIGN_RESERVED_FIRST \
22879 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_TSA_ASSIGN_RESERVED_LAST \
22882 * Priority level for strict priority. Valid only when the
22883 * tsa_assign is 0 - Strict Priority (SP)
22884 * 0..7 - Valid values.
22885 * 8..255 - Reserved.
22887 uint8_t queue_id0_pri_lvl;
22889 * Weight used to allocate remaining BW for this COS after
22890 * servicing guaranteed bandwidths for all COS.
22892 uint8_t queue_id0_bw_weight;
22893 /* ID of CoS Queue 1. */
22896 * Minimum BW allocated to CoS Queue.
22897 * The HWRM will translate this value into byte counter and
22898 * time interval used for this COS inside the device.
22900 uint32_t queue_id1_min_bw;
22901 /* The bandwidth value. */
22902 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MIN_BW_BW_VALUE_MASK \
22903 UINT32_C(0xfffffff)
22904 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MIN_BW_BW_VALUE_SFT \
22906 /* The granularity of the value (bits or bytes). */
22907 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MIN_BW_SCALE \
22908 UINT32_C(0x10000000)
22909 /* Value is in bits. */
22910 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MIN_BW_SCALE_BITS \
22911 (UINT32_C(0x0) << 28)
22912 /* Value is in bytes. */
22913 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MIN_BW_SCALE_BYTES \
22914 (UINT32_C(0x1) << 28)
22915 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MIN_BW_SCALE_LAST \
22916 HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MIN_BW_SCALE_BYTES
22917 /* bw_value_unit is 3 b */
22918 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_MASK \
22919 UINT32_C(0xe0000000)
22920 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_SFT \
22922 /* Value is in Mb or MB (base 10). */
22923 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_MEGA \
22924 (UINT32_C(0x0) << 29)
22925 /* Value is in Kb or KB (base 10). */
22926 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_KILO \
22927 (UINT32_C(0x2) << 29)
22928 /* Value is in bits or bytes. */
22929 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_BASE \
22930 (UINT32_C(0x4) << 29)
22931 /* Value is in Gb or GB (base 10). */
22932 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_GIGA \
22933 (UINT32_C(0x6) << 29)
22934 /* Value is in 1/100th of a percentage of total bandwidth. */
22935 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 \
22936 (UINT32_C(0x1) << 29)
22938 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_INVALID \
22939 (UINT32_C(0x7) << 29)
22940 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_LAST \
22941 HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_INVALID
22943 * Maximum BW allocated to CoS queue.
22944 * The HWRM will translate this value into byte counter and
22945 * time interval used for this COS inside the device.
22947 uint32_t queue_id1_max_bw;
22948 /* The bandwidth value. */
22949 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MAX_BW_BW_VALUE_MASK \
22950 UINT32_C(0xfffffff)
22951 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MAX_BW_BW_VALUE_SFT \
22953 /* The granularity of the value (bits or bytes). */
22954 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MAX_BW_SCALE \
22955 UINT32_C(0x10000000)
22956 /* Value is in bits. */
22957 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MAX_BW_SCALE_BITS \
22958 (UINT32_C(0x0) << 28)
22959 /* Value is in bytes. */
22960 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MAX_BW_SCALE_BYTES \
22961 (UINT32_C(0x1) << 28)
22962 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MAX_BW_SCALE_LAST \
22963 HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MAX_BW_SCALE_BYTES
22964 /* bw_value_unit is 3 b */
22965 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_MASK \
22966 UINT32_C(0xe0000000)
22967 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_SFT \
22969 /* Value is in Mb or MB (base 10). */
22970 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_MEGA \
22971 (UINT32_C(0x0) << 29)
22972 /* Value is in Kb or KB (base 10). */
22973 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_KILO \
22974 (UINT32_C(0x2) << 29)
22975 /* Value is in bits or bytes. */
22976 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_BASE \
22977 (UINT32_C(0x4) << 29)
22978 /* Value is in Gb or GB (base 10). */
22979 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_GIGA \
22980 (UINT32_C(0x6) << 29)
22981 /* Value is in 1/100th of a percentage of total bandwidth. */
22982 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 \
22983 (UINT32_C(0x1) << 29)
22985 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_INVALID \
22986 (UINT32_C(0x7) << 29)
22987 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_LAST \
22988 HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_INVALID
22989 /* Transmission Selection Algorithm (TSA) for CoS Queue. */
22990 uint8_t queue_id1_tsa_assign;
22991 /* Strict Priority */
22992 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_TSA_ASSIGN_SP \
22994 /* Enhanced Transmission Selection */
22995 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_TSA_ASSIGN_ETS \
22998 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_TSA_ASSIGN_RESERVED_FIRST \
23001 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_TSA_ASSIGN_RESERVED_LAST \
23004 * Priority level for strict priority. Valid only when the
23005 * tsa_assign is 0 - Strict Priority (SP)
23006 * 0..7 - Valid values.
23007 * 8..255 - Reserved.
23009 uint8_t queue_id1_pri_lvl;
23011 * Weight used to allocate remaining BW for this COS after
23012 * servicing guaranteed bandwidths for all COS.
23014 uint8_t queue_id1_bw_weight;
23015 /* ID of CoS Queue 2. */
23018 * Minimum BW allocated to CoS Queue.
23019 * The HWRM will translate this value into byte counter and
23020 * time interval used for this COS inside the device.
23022 uint32_t queue_id2_min_bw;
23023 /* The bandwidth value. */
23024 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MIN_BW_BW_VALUE_MASK \
23025 UINT32_C(0xfffffff)
23026 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MIN_BW_BW_VALUE_SFT \
23028 /* The granularity of the value (bits or bytes). */
23029 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MIN_BW_SCALE \
23030 UINT32_C(0x10000000)
23031 /* Value is in bits. */
23032 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MIN_BW_SCALE_BITS \
23033 (UINT32_C(0x0) << 28)
23034 /* Value is in bytes. */
23035 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MIN_BW_SCALE_BYTES \
23036 (UINT32_C(0x1) << 28)
23037 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MIN_BW_SCALE_LAST \
23038 HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MIN_BW_SCALE_BYTES
23039 /* bw_value_unit is 3 b */
23040 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_MASK \
23041 UINT32_C(0xe0000000)
23042 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_SFT \
23044 /* Value is in Mb or MB (base 10). */
23045 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_MEGA \
23046 (UINT32_C(0x0) << 29)
23047 /* Value is in Kb or KB (base 10). */
23048 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_KILO \
23049 (UINT32_C(0x2) << 29)
23050 /* Value is in bits or bytes. */
23051 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_BASE \
23052 (UINT32_C(0x4) << 29)
23053 /* Value is in Gb or GB (base 10). */
23054 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_GIGA \
23055 (UINT32_C(0x6) << 29)
23056 /* Value is in 1/100th of a percentage of total bandwidth. */
23057 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 \
23058 (UINT32_C(0x1) << 29)
23060 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_INVALID \
23061 (UINT32_C(0x7) << 29)
23062 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_LAST \
23063 HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_INVALID
23065 * Maximum BW allocated to CoS queue.
23066 * The HWRM will translate this value into byte counter and
23067 * time interval used for this COS inside the device.
23069 uint32_t queue_id2_max_bw;
23070 /* The bandwidth value. */
23071 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MAX_BW_BW_VALUE_MASK \
23072 UINT32_C(0xfffffff)
23073 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MAX_BW_BW_VALUE_SFT \
23075 /* The granularity of the value (bits or bytes). */
23076 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MAX_BW_SCALE \
23077 UINT32_C(0x10000000)
23078 /* Value is in bits. */
23079 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MAX_BW_SCALE_BITS \
23080 (UINT32_C(0x0) << 28)
23081 /* Value is in bytes. */
23082 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MAX_BW_SCALE_BYTES \
23083 (UINT32_C(0x1) << 28)
23084 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MAX_BW_SCALE_LAST \
23085 HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MAX_BW_SCALE_BYTES
23086 /* bw_value_unit is 3 b */
23087 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_MASK \
23088 UINT32_C(0xe0000000)
23089 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_SFT \
23091 /* Value is in Mb or MB (base 10). */
23092 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_MEGA \
23093 (UINT32_C(0x0) << 29)
23094 /* Value is in Kb or KB (base 10). */
23095 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_KILO \
23096 (UINT32_C(0x2) << 29)
23097 /* Value is in bits or bytes. */
23098 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_BASE \
23099 (UINT32_C(0x4) << 29)
23100 /* Value is in Gb or GB (base 10). */
23101 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_GIGA \
23102 (UINT32_C(0x6) << 29)
23103 /* Value is in 1/100th of a percentage of total bandwidth. */
23104 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 \
23105 (UINT32_C(0x1) << 29)
23107 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_INVALID \
23108 (UINT32_C(0x7) << 29)
23109 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_LAST \
23110 HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_INVALID
23111 /* Transmission Selection Algorithm (TSA) for CoS Queue. */
23112 uint8_t queue_id2_tsa_assign;
23113 /* Strict Priority */
23114 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_TSA_ASSIGN_SP \
23116 /* Enhanced Transmission Selection */
23117 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_TSA_ASSIGN_ETS \
23120 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_TSA_ASSIGN_RESERVED_FIRST \
23123 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_TSA_ASSIGN_RESERVED_LAST \
23126 * Priority level for strict priority. Valid only when the
23127 * tsa_assign is 0 - Strict Priority (SP)
23128 * 0..7 - Valid values.
23129 * 8..255 - Reserved.
23131 uint8_t queue_id2_pri_lvl;
23133 * Weight used to allocate remaining BW for this COS after
23134 * servicing guaranteed bandwidths for all COS.
23136 uint8_t queue_id2_bw_weight;
23137 /* ID of CoS Queue 3. */
23140 * Minimum BW allocated to CoS Queue.
23141 * The HWRM will translate this value into byte counter and
23142 * time interval used for this COS inside the device.
23144 uint32_t queue_id3_min_bw;
23145 /* The bandwidth value. */
23146 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MIN_BW_BW_VALUE_MASK \
23147 UINT32_C(0xfffffff)
23148 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MIN_BW_BW_VALUE_SFT \
23150 /* The granularity of the value (bits or bytes). */
23151 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MIN_BW_SCALE \
23152 UINT32_C(0x10000000)
23153 /* Value is in bits. */
23154 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MIN_BW_SCALE_BITS \
23155 (UINT32_C(0x0) << 28)
23156 /* Value is in bytes. */
23157 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MIN_BW_SCALE_BYTES \
23158 (UINT32_C(0x1) << 28)
23159 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MIN_BW_SCALE_LAST \
23160 HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MIN_BW_SCALE_BYTES
23161 /* bw_value_unit is 3 b */
23162 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_MASK \
23163 UINT32_C(0xe0000000)
23164 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_SFT \
23166 /* Value is in Mb or MB (base 10). */
23167 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_MEGA \
23168 (UINT32_C(0x0) << 29)
23169 /* Value is in Kb or KB (base 10). */
23170 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_KILO \
23171 (UINT32_C(0x2) << 29)
23172 /* Value is in bits or bytes. */
23173 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_BASE \
23174 (UINT32_C(0x4) << 29)
23175 /* Value is in Gb or GB (base 10). */
23176 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_GIGA \
23177 (UINT32_C(0x6) << 29)
23178 /* Value is in 1/100th of a percentage of total bandwidth. */
23179 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 \
23180 (UINT32_C(0x1) << 29)
23182 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_INVALID \
23183 (UINT32_C(0x7) << 29)
23184 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_LAST \
23185 HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_INVALID
23187 * Maximum BW allocated to CoS queue.
23188 * The HWRM will translate this value into byte counter and
23189 * time interval used for this COS inside the device.
23191 uint32_t queue_id3_max_bw;
23192 /* The bandwidth value. */
23193 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MAX_BW_BW_VALUE_MASK \
23194 UINT32_C(0xfffffff)
23195 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MAX_BW_BW_VALUE_SFT \
23197 /* The granularity of the value (bits or bytes). */
23198 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MAX_BW_SCALE \
23199 UINT32_C(0x10000000)
23200 /* Value is in bits. */
23201 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MAX_BW_SCALE_BITS \
23202 (UINT32_C(0x0) << 28)
23203 /* Value is in bytes. */
23204 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MAX_BW_SCALE_BYTES \
23205 (UINT32_C(0x1) << 28)
23206 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MAX_BW_SCALE_LAST \
23207 HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MAX_BW_SCALE_BYTES
23208 /* bw_value_unit is 3 b */
23209 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_MASK \
23210 UINT32_C(0xe0000000)
23211 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_SFT \
23213 /* Value is in Mb or MB (base 10). */
23214 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_MEGA \
23215 (UINT32_C(0x0) << 29)
23216 /* Value is in Kb or KB (base 10). */
23217 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_KILO \
23218 (UINT32_C(0x2) << 29)
23219 /* Value is in bits or bytes. */
23220 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_BASE \
23221 (UINT32_C(0x4) << 29)
23222 /* Value is in Gb or GB (base 10). */
23223 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_GIGA \
23224 (UINT32_C(0x6) << 29)
23225 /* Value is in 1/100th of a percentage of total bandwidth. */
23226 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 \
23227 (UINT32_C(0x1) << 29)
23229 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_INVALID \
23230 (UINT32_C(0x7) << 29)
23231 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_LAST \
23232 HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_INVALID
23233 /* Transmission Selection Algorithm (TSA) for CoS Queue. */
23234 uint8_t queue_id3_tsa_assign;
23235 /* Strict Priority */
23236 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_TSA_ASSIGN_SP \
23238 /* Enhanced Transmission Selection */
23239 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_TSA_ASSIGN_ETS \
23242 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_TSA_ASSIGN_RESERVED_FIRST \
23245 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_TSA_ASSIGN_RESERVED_LAST \
23248 * Priority level for strict priority. Valid only when the
23249 * tsa_assign is 0 - Strict Priority (SP)
23250 * 0..7 - Valid values.
23251 * 8..255 - Reserved.
23253 uint8_t queue_id3_pri_lvl;
23255 * Weight used to allocate remaining BW for this COS after
23256 * servicing guaranteed bandwidths for all COS.
23258 uint8_t queue_id3_bw_weight;
23259 /* ID of CoS Queue 4. */
23262 * Minimum BW allocated to CoS Queue.
23263 * The HWRM will translate this value into byte counter and
23264 * time interval used for this COS inside the device.
23266 uint32_t queue_id4_min_bw;
23267 /* The bandwidth value. */
23268 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MIN_BW_BW_VALUE_MASK \
23269 UINT32_C(0xfffffff)
23270 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MIN_BW_BW_VALUE_SFT \
23272 /* The granularity of the value (bits or bytes). */
23273 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MIN_BW_SCALE \
23274 UINT32_C(0x10000000)
23275 /* Value is in bits. */
23276 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MIN_BW_SCALE_BITS \
23277 (UINT32_C(0x0) << 28)
23278 /* Value is in bytes. */
23279 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MIN_BW_SCALE_BYTES \
23280 (UINT32_C(0x1) << 28)
23281 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MIN_BW_SCALE_LAST \
23282 HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MIN_BW_SCALE_BYTES
23283 /* bw_value_unit is 3 b */
23284 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_MASK \
23285 UINT32_C(0xe0000000)
23286 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_SFT \
23288 /* Value is in Mb or MB (base 10). */
23289 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_MEGA \
23290 (UINT32_C(0x0) << 29)
23291 /* Value is in Kb or KB (base 10). */
23292 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_KILO \
23293 (UINT32_C(0x2) << 29)
23294 /* Value is in bits or bytes. */
23295 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_BASE \
23296 (UINT32_C(0x4) << 29)
23297 /* Value is in Gb or GB (base 10). */
23298 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_GIGA \
23299 (UINT32_C(0x6) << 29)
23300 /* Value is in 1/100th of a percentage of total bandwidth. */
23301 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 \
23302 (UINT32_C(0x1) << 29)
23304 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_INVALID \
23305 (UINT32_C(0x7) << 29)
23306 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_LAST \
23307 HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_INVALID
23309 * Maximum BW allocated to CoS queue.
23310 * The HWRM will translate this value into byte counter and
23311 * time interval used for this COS inside the device.
23313 uint32_t queue_id4_max_bw;
23314 /* The bandwidth value. */
23315 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MAX_BW_BW_VALUE_MASK \
23316 UINT32_C(0xfffffff)
23317 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MAX_BW_BW_VALUE_SFT \
23319 /* The granularity of the value (bits or bytes). */
23320 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MAX_BW_SCALE \
23321 UINT32_C(0x10000000)
23322 /* Value is in bits. */
23323 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MAX_BW_SCALE_BITS \
23324 (UINT32_C(0x0) << 28)
23325 /* Value is in bytes. */
23326 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MAX_BW_SCALE_BYTES \
23327 (UINT32_C(0x1) << 28)
23328 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MAX_BW_SCALE_LAST \
23329 HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MAX_BW_SCALE_BYTES
23330 /* bw_value_unit is 3 b */
23331 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_MASK \
23332 UINT32_C(0xe0000000)
23333 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_SFT \
23335 /* Value is in Mb or MB (base 10). */
23336 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_MEGA \
23337 (UINT32_C(0x0) << 29)
23338 /* Value is in Kb or KB (base 10). */
23339 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_KILO \
23340 (UINT32_C(0x2) << 29)
23341 /* Value is in bits or bytes. */
23342 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_BASE \
23343 (UINT32_C(0x4) << 29)
23344 /* Value is in Gb or GB (base 10). */
23345 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_GIGA \
23346 (UINT32_C(0x6) << 29)
23347 /* Value is in 1/100th of a percentage of total bandwidth. */
23348 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 \
23349 (UINT32_C(0x1) << 29)
23351 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_INVALID \
23352 (UINT32_C(0x7) << 29)
23353 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_LAST \
23354 HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_INVALID
23355 /* Transmission Selection Algorithm (TSA) for CoS Queue. */
23356 uint8_t queue_id4_tsa_assign;
23357 /* Strict Priority */
23358 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_TSA_ASSIGN_SP \
23360 /* Enhanced Transmission Selection */
23361 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_TSA_ASSIGN_ETS \
23364 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_TSA_ASSIGN_RESERVED_FIRST \
23367 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_TSA_ASSIGN_RESERVED_LAST \
23370 * Priority level for strict priority. Valid only when the
23371 * tsa_assign is 0 - Strict Priority (SP)
23372 * 0..7 - Valid values.
23373 * 8..255 - Reserved.
23375 uint8_t queue_id4_pri_lvl;
23377 * Weight used to allocate remaining BW for this COS after
23378 * servicing guaranteed bandwidths for all COS.
23380 uint8_t queue_id4_bw_weight;
23381 /* ID of CoS Queue 5. */
23384 * Minimum BW allocated to CoS Queue.
23385 * The HWRM will translate this value into byte counter and
23386 * time interval used for this COS inside the device.
23388 uint32_t queue_id5_min_bw;
23389 /* The bandwidth value. */
23390 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MIN_BW_BW_VALUE_MASK \
23391 UINT32_C(0xfffffff)
23392 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MIN_BW_BW_VALUE_SFT \
23394 /* The granularity of the value (bits or bytes). */
23395 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MIN_BW_SCALE \
23396 UINT32_C(0x10000000)
23397 /* Value is in bits. */
23398 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MIN_BW_SCALE_BITS \
23399 (UINT32_C(0x0) << 28)
23400 /* Value is in bytes. */
23401 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MIN_BW_SCALE_BYTES \
23402 (UINT32_C(0x1) << 28)
23403 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MIN_BW_SCALE_LAST \
23404 HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MIN_BW_SCALE_BYTES
23405 /* bw_value_unit is 3 b */
23406 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_MASK \
23407 UINT32_C(0xe0000000)
23408 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_SFT \
23410 /* Value is in Mb or MB (base 10). */
23411 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_MEGA \
23412 (UINT32_C(0x0) << 29)
23413 /* Value is in Kb or KB (base 10). */
23414 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_KILO \
23415 (UINT32_C(0x2) << 29)
23416 /* Value is in bits or bytes. */
23417 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_BASE \
23418 (UINT32_C(0x4) << 29)
23419 /* Value is in Gb or GB (base 10). */
23420 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_GIGA \
23421 (UINT32_C(0x6) << 29)
23422 /* Value is in 1/100th of a percentage of total bandwidth. */
23423 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 \
23424 (UINT32_C(0x1) << 29)
23426 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_INVALID \
23427 (UINT32_C(0x7) << 29)
23428 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_LAST \
23429 HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_INVALID
23431 * Maximum BW allocated to CoS queue.
23432 * The HWRM will translate this value into byte counter and
23433 * time interval used for this COS inside the device.
23435 uint32_t queue_id5_max_bw;
23436 /* The bandwidth value. */
23437 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MAX_BW_BW_VALUE_MASK \
23438 UINT32_C(0xfffffff)
23439 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MAX_BW_BW_VALUE_SFT \
23441 /* The granularity of the value (bits or bytes). */
23442 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MAX_BW_SCALE \
23443 UINT32_C(0x10000000)
23444 /* Value is in bits. */
23445 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MAX_BW_SCALE_BITS \
23446 (UINT32_C(0x0) << 28)
23447 /* Value is in bytes. */
23448 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MAX_BW_SCALE_BYTES \
23449 (UINT32_C(0x1) << 28)
23450 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MAX_BW_SCALE_LAST \
23451 HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MAX_BW_SCALE_BYTES
23452 /* bw_value_unit is 3 b */
23453 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_MASK \
23454 UINT32_C(0xe0000000)
23455 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_SFT \
23457 /* Value is in Mb or MB (base 10). */
23458 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_MEGA \
23459 (UINT32_C(0x0) << 29)
23460 /* Value is in Kb or KB (base 10). */
23461 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_KILO \
23462 (UINT32_C(0x2) << 29)
23463 /* Value is in bits or bytes. */
23464 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_BASE \
23465 (UINT32_C(0x4) << 29)
23466 /* Value is in Gb or GB (base 10). */
23467 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_GIGA \
23468 (UINT32_C(0x6) << 29)
23469 /* Value is in 1/100th of a percentage of total bandwidth. */
23470 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 \
23471 (UINT32_C(0x1) << 29)
23473 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_INVALID \
23474 (UINT32_C(0x7) << 29)
23475 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_LAST \
23476 HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_INVALID
23477 /* Transmission Selection Algorithm (TSA) for CoS Queue. */
23478 uint8_t queue_id5_tsa_assign;
23479 /* Strict Priority */
23480 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_TSA_ASSIGN_SP \
23482 /* Enhanced Transmission Selection */
23483 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_TSA_ASSIGN_ETS \
23486 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_TSA_ASSIGN_RESERVED_FIRST \
23489 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_TSA_ASSIGN_RESERVED_LAST \
23492 * Priority level for strict priority. Valid only when the
23493 * tsa_assign is 0 - Strict Priority (SP)
23494 * 0..7 - Valid values.
23495 * 8..255 - Reserved.
23497 uint8_t queue_id5_pri_lvl;
23499 * Weight used to allocate remaining BW for this COS after
23500 * servicing guaranteed bandwidths for all COS.
23502 uint8_t queue_id5_bw_weight;
23503 /* ID of CoS Queue 6. */
23506 * Minimum BW allocated to CoS Queue.
23507 * The HWRM will translate this value into byte counter and
23508 * time interval used for this COS inside the device.
23510 uint32_t queue_id6_min_bw;
23511 /* The bandwidth value. */
23512 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MIN_BW_BW_VALUE_MASK \
23513 UINT32_C(0xfffffff)
23514 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MIN_BW_BW_VALUE_SFT \
23516 /* The granularity of the value (bits or bytes). */
23517 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MIN_BW_SCALE \
23518 UINT32_C(0x10000000)
23519 /* Value is in bits. */
23520 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MIN_BW_SCALE_BITS \
23521 (UINT32_C(0x0) << 28)
23522 /* Value is in bytes. */
23523 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MIN_BW_SCALE_BYTES \
23524 (UINT32_C(0x1) << 28)
23525 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MIN_BW_SCALE_LAST \
23526 HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MIN_BW_SCALE_BYTES
23527 /* bw_value_unit is 3 b */
23528 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_MASK \
23529 UINT32_C(0xe0000000)
23530 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_SFT \
23532 /* Value is in Mb or MB (base 10). */
23533 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_MEGA \
23534 (UINT32_C(0x0) << 29)
23535 /* Value is in Kb or KB (base 10). */
23536 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_KILO \
23537 (UINT32_C(0x2) << 29)
23538 /* Value is in bits or bytes. */
23539 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_BASE \
23540 (UINT32_C(0x4) << 29)
23541 /* Value is in Gb or GB (base 10). */
23542 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_GIGA \
23543 (UINT32_C(0x6) << 29)
23544 /* Value is in 1/100th of a percentage of total bandwidth. */
23545 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 \
23546 (UINT32_C(0x1) << 29)
23548 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_INVALID \
23549 (UINT32_C(0x7) << 29)
23550 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_LAST \
23551 HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_INVALID
23553 * Maximum BW allocated to CoS queue.
23554 * The HWRM will translate this value into byte counter and
23555 * time interval used for this COS inside the device.
23557 uint32_t queue_id6_max_bw;
23558 /* The bandwidth value. */
23559 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MAX_BW_BW_VALUE_MASK \
23560 UINT32_C(0xfffffff)
23561 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MAX_BW_BW_VALUE_SFT \
23563 /* The granularity of the value (bits or bytes). */
23564 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MAX_BW_SCALE \
23565 UINT32_C(0x10000000)
23566 /* Value is in bits. */
23567 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MAX_BW_SCALE_BITS \
23568 (UINT32_C(0x0) << 28)
23569 /* Value is in bytes. */
23570 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MAX_BW_SCALE_BYTES \
23571 (UINT32_C(0x1) << 28)
23572 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MAX_BW_SCALE_LAST \
23573 HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MAX_BW_SCALE_BYTES
23574 /* bw_value_unit is 3 b */
23575 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_MASK \
23576 UINT32_C(0xe0000000)
23577 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_SFT \
23579 /* Value is in Mb or MB (base 10). */
23580 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_MEGA \
23581 (UINT32_C(0x0) << 29)
23582 /* Value is in Kb or KB (base 10). */
23583 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_KILO \
23584 (UINT32_C(0x2) << 29)
23585 /* Value is in bits or bytes. */
23586 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_BASE \
23587 (UINT32_C(0x4) << 29)
23588 /* Value is in Gb or GB (base 10). */
23589 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_GIGA \
23590 (UINT32_C(0x6) << 29)
23591 /* Value is in 1/100th of a percentage of total bandwidth. */
23592 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 \
23593 (UINT32_C(0x1) << 29)
23595 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_INVALID \
23596 (UINT32_C(0x7) << 29)
23597 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_LAST \
23598 HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_INVALID
23599 /* Transmission Selection Algorithm (TSA) for CoS Queue. */
23600 uint8_t queue_id6_tsa_assign;
23601 /* Strict Priority */
23602 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_TSA_ASSIGN_SP \
23604 /* Enhanced Transmission Selection */
23605 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_TSA_ASSIGN_ETS \
23608 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_TSA_ASSIGN_RESERVED_FIRST \
23611 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_TSA_ASSIGN_RESERVED_LAST \
23614 * Priority level for strict priority. Valid only when the
23615 * tsa_assign is 0 - Strict Priority (SP)
23616 * 0..7 - Valid values.
23617 * 8..255 - Reserved.
23619 uint8_t queue_id6_pri_lvl;
23621 * Weight used to allocate remaining BW for this COS after
23622 * servicing guaranteed bandwidths for all COS.
23624 uint8_t queue_id6_bw_weight;
23625 /* ID of CoS Queue 7. */
23628 * Minimum BW allocated to CoS Queue.
23629 * The HWRM will translate this value into byte counter and
23630 * time interval used for this COS inside the device.
23632 uint32_t queue_id7_min_bw;
23633 /* The bandwidth value. */
23634 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MIN_BW_BW_VALUE_MASK \
23635 UINT32_C(0xfffffff)
23636 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MIN_BW_BW_VALUE_SFT \
23638 /* The granularity of the value (bits or bytes). */
23639 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MIN_BW_SCALE \
23640 UINT32_C(0x10000000)
23641 /* Value is in bits. */
23642 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MIN_BW_SCALE_BITS \
23643 (UINT32_C(0x0) << 28)
23644 /* Value is in bytes. */
23645 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MIN_BW_SCALE_BYTES \
23646 (UINT32_C(0x1) << 28)
23647 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MIN_BW_SCALE_LAST \
23648 HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MIN_BW_SCALE_BYTES
23649 /* bw_value_unit is 3 b */
23650 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_MASK \
23651 UINT32_C(0xe0000000)
23652 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_SFT \
23654 /* Value is in Mb or MB (base 10). */
23655 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_MEGA \
23656 (UINT32_C(0x0) << 29)
23657 /* Value is in Kb or KB (base 10). */
23658 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_KILO \
23659 (UINT32_C(0x2) << 29)
23660 /* Value is in bits or bytes. */
23661 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_BASE \
23662 (UINT32_C(0x4) << 29)
23663 /* Value is in Gb or GB (base 10). */
23664 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_GIGA \
23665 (UINT32_C(0x6) << 29)
23666 /* Value is in 1/100th of a percentage of total bandwidth. */
23667 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 \
23668 (UINT32_C(0x1) << 29)
23670 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_INVALID \
23671 (UINT32_C(0x7) << 29)
23672 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_LAST \
23673 HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_INVALID
23675 * Maximum BW allocated to CoS queue.
23676 * The HWRM will translate this value into byte counter and
23677 * time interval used for this COS inside the device.
23679 uint32_t queue_id7_max_bw;
23680 /* The bandwidth value. */
23681 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MAX_BW_BW_VALUE_MASK \
23682 UINT32_C(0xfffffff)
23683 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MAX_BW_BW_VALUE_SFT \
23685 /* The granularity of the value (bits or bytes). */
23686 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MAX_BW_SCALE \
23687 UINT32_C(0x10000000)
23688 /* Value is in bits. */
23689 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MAX_BW_SCALE_BITS \
23690 (UINT32_C(0x0) << 28)
23691 /* Value is in bytes. */
23692 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MAX_BW_SCALE_BYTES \
23693 (UINT32_C(0x1) << 28)
23694 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MAX_BW_SCALE_LAST \
23695 HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MAX_BW_SCALE_BYTES
23696 /* bw_value_unit is 3 b */
23697 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_MASK \
23698 UINT32_C(0xe0000000)
23699 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_SFT \
23701 /* Value is in Mb or MB (base 10). */
23702 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_MEGA \
23703 (UINT32_C(0x0) << 29)
23704 /* Value is in Kb or KB (base 10). */
23705 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_KILO \
23706 (UINT32_C(0x2) << 29)
23707 /* Value is in bits or bytes. */
23708 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_BASE \
23709 (UINT32_C(0x4) << 29)
23710 /* Value is in Gb or GB (base 10). */
23711 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_GIGA \
23712 (UINT32_C(0x6) << 29)
23713 /* Value is in 1/100th of a percentage of total bandwidth. */
23714 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 \
23715 (UINT32_C(0x1) << 29)
23717 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_INVALID \
23718 (UINT32_C(0x7) << 29)
23719 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_LAST \
23720 HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_INVALID
23721 /* Transmission Selection Algorithm (TSA) for CoS Queue. */
23722 uint8_t queue_id7_tsa_assign;
23723 /* Strict Priority */
23724 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_TSA_ASSIGN_SP \
23726 /* Enhanced Transmission Selection */
23727 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_TSA_ASSIGN_ETS \
23730 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_TSA_ASSIGN_RESERVED_FIRST \
23733 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_TSA_ASSIGN_RESERVED_LAST \
23736 * Priority level for strict priority. Valid only when the
23737 * tsa_assign is 0 - Strict Priority (SP)
23738 * 0..7 - Valid values.
23739 * 8..255 - Reserved.
23741 uint8_t queue_id7_pri_lvl;
23743 * Weight used to allocate remaining BW for this COS after
23744 * servicing guaranteed bandwidths for all COS.
23746 uint8_t queue_id7_bw_weight;
23747 uint8_t unused_2[4];
23749 * This field is used in Output records to indicate that the output
23750 * is completely written to RAM. This field should be read as '1'
23751 * to indicate that the output has been completely written.
23752 * When writing a command completion or response to an internal processor,
23753 * the order of writes has to be such that this field is written last.
23758 /*************************
23759 * hwrm_queue_cos2bw_cfg *
23760 *************************/
23763 /* hwrm_queue_cos2bw_cfg_input (size:1024b/128B) */
23764 struct hwrm_queue_cos2bw_cfg_input {
23765 /* The HWRM command request type. */
23768 * The completion ring to send the completion event on. This should
23769 * be the NQ ID returned from the `nq_alloc` HWRM command.
23771 uint16_t cmpl_ring;
23773 * The sequence ID is used by the driver for tracking multiple
23774 * commands. This ID is treated as opaque data by the firmware and
23775 * the value is returned in the `hwrm_resp_hdr` upon completion.
23779 * The target ID of the command:
23780 * * 0x0-0xFFF8 - The function ID
23781 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
23782 * * 0xFFFD - Reserved for user-space HWRM interface
23785 uint16_t target_id;
23787 * A physical address pointer pointing to a host buffer that the
23788 * command's response data will be written. This can be either a host
23789 * physical address (HPA) or a guest physical address (GPA) and must
23790 * point to a physically contiguous block of memory.
23792 uint64_t resp_addr;
23796 * If this bit is set to 1, then all queue_id0 related
23797 * parameters in this command are valid.
23799 #define HWRM_QUEUE_COS2BW_CFG_INPUT_ENABLES_COS_QUEUE_ID0_VALID \
23802 * If this bit is set to 1, then all queue_id1 related
23803 * parameters in this command are valid.
23805 #define HWRM_QUEUE_COS2BW_CFG_INPUT_ENABLES_COS_QUEUE_ID1_VALID \
23808 * If this bit is set to 1, then all queue_id2 related
23809 * parameters in this command are valid.
23811 #define HWRM_QUEUE_COS2BW_CFG_INPUT_ENABLES_COS_QUEUE_ID2_VALID \
23814 * If this bit is set to 1, then all queue_id3 related
23815 * parameters in this command are valid.
23817 #define HWRM_QUEUE_COS2BW_CFG_INPUT_ENABLES_COS_QUEUE_ID3_VALID \
23820 * If this bit is set to 1, then all queue_id4 related
23821 * parameters in this command are valid.
23823 #define HWRM_QUEUE_COS2BW_CFG_INPUT_ENABLES_COS_QUEUE_ID4_VALID \
23826 * If this bit is set to 1, then all queue_id5 related
23827 * parameters in this command are valid.
23829 #define HWRM_QUEUE_COS2BW_CFG_INPUT_ENABLES_COS_QUEUE_ID5_VALID \
23832 * If this bit is set to 1, then all queue_id6 related
23833 * parameters in this command are valid.
23835 #define HWRM_QUEUE_COS2BW_CFG_INPUT_ENABLES_COS_QUEUE_ID6_VALID \
23838 * If this bit is set to 1, then all queue_id7 related
23839 * parameters in this command are valid.
23841 #define HWRM_QUEUE_COS2BW_CFG_INPUT_ENABLES_COS_QUEUE_ID7_VALID \
23844 * Port ID of port for which the table is being configured.
23845 * The HWRM needs to check whether this function is allowed
23846 * to configure TC BW assignment on this port.
23849 /* ID of CoS Queue 0. */
23853 * Minimum BW allocated to CoS Queue.
23854 * The HWRM will translate this value into byte counter and
23855 * time interval used for this COS inside the device.
23857 uint32_t queue_id0_min_bw;
23858 /* The bandwidth value. */
23859 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MIN_BW_BW_VALUE_MASK \
23860 UINT32_C(0xfffffff)
23861 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MIN_BW_BW_VALUE_SFT \
23863 /* The granularity of the value (bits or bytes). */
23864 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MIN_BW_SCALE \
23865 UINT32_C(0x10000000)
23866 /* Value is in bits. */
23867 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MIN_BW_SCALE_BITS \
23868 (UINT32_C(0x0) << 28)
23869 /* Value is in bytes. */
23870 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MIN_BW_SCALE_BYTES \
23871 (UINT32_C(0x1) << 28)
23872 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MIN_BW_SCALE_LAST \
23873 HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MIN_BW_SCALE_BYTES
23874 /* bw_value_unit is 3 b */
23875 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_MASK \
23876 UINT32_C(0xe0000000)
23877 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_SFT \
23879 /* Value is in Mb or MB (base 10). */
23880 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_MEGA \
23881 (UINT32_C(0x0) << 29)
23882 /* Value is in Kb or KB (base 10). */
23883 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_KILO \
23884 (UINT32_C(0x2) << 29)
23885 /* Value is in bits or bytes. */
23886 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_BASE \
23887 (UINT32_C(0x4) << 29)
23888 /* Value is in Gb or GB (base 10). */
23889 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_GIGA \
23890 (UINT32_C(0x6) << 29)
23891 /* Value is in 1/100th of a percentage of total bandwidth. */
23892 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 \
23893 (UINT32_C(0x1) << 29)
23895 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_INVALID \
23896 (UINT32_C(0x7) << 29)
23897 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_LAST \
23898 HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_INVALID
23900 * Maximum BW allocated to CoS Queue.
23901 * The HWRM will translate this value into byte counter and
23902 * time interval used for this COS inside the device.
23904 uint32_t queue_id0_max_bw;
23905 /* The bandwidth value. */
23906 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MAX_BW_BW_VALUE_MASK \
23907 UINT32_C(0xfffffff)
23908 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MAX_BW_BW_VALUE_SFT \
23910 /* The granularity of the value (bits or bytes). */
23911 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MAX_BW_SCALE \
23912 UINT32_C(0x10000000)
23913 /* Value is in bits. */
23914 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MAX_BW_SCALE_BITS \
23915 (UINT32_C(0x0) << 28)
23916 /* Value is in bytes. */
23917 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MAX_BW_SCALE_BYTES \
23918 (UINT32_C(0x1) << 28)
23919 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MAX_BW_SCALE_LAST \
23920 HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MAX_BW_SCALE_BYTES
23921 /* bw_value_unit is 3 b */
23922 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_MASK \
23923 UINT32_C(0xe0000000)
23924 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_SFT \
23926 /* Value is in Mb or MB (base 10). */
23927 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_MEGA \
23928 (UINT32_C(0x0) << 29)
23929 /* Value is in Kb or KB (base 10). */
23930 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_KILO \
23931 (UINT32_C(0x2) << 29)
23932 /* Value is in bits or bytes. */
23933 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_BASE \
23934 (UINT32_C(0x4) << 29)
23935 /* Value is in Gb or GB (base 10). */
23936 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_GIGA \
23937 (UINT32_C(0x6) << 29)
23938 /* Value is in 1/100th of a percentage of total bandwidth. */
23939 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 \
23940 (UINT32_C(0x1) << 29)
23942 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_INVALID \
23943 (UINT32_C(0x7) << 29)
23944 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_LAST \
23945 HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_INVALID
23946 /* Transmission Selection Algorithm (TSA) for CoS Queue. */
23947 uint8_t queue_id0_tsa_assign;
23948 /* Strict Priority */
23949 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_TSA_ASSIGN_SP \
23951 /* Enhanced Transmission Selection */
23952 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_TSA_ASSIGN_ETS \
23955 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_TSA_ASSIGN_RESERVED_FIRST \
23958 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_TSA_ASSIGN_RESERVED_LAST \
23961 * Priority level for strict priority. Valid only when the
23962 * tsa_assign is 0 - Strict Priority (SP)
23963 * 0..7 - Valid values.
23964 * 8..255 - Reserved.
23966 uint8_t queue_id0_pri_lvl;
23968 * Weight used to allocate remaining BW for this COS after
23969 * servicing guaranteed bandwidths for all COS.
23971 uint8_t queue_id0_bw_weight;
23972 /* ID of CoS Queue 1. */
23975 * Minimum BW allocated to CoS Queue.
23976 * The HWRM will translate this value into byte counter and
23977 * time interval used for this COS inside the device.
23979 uint32_t queue_id1_min_bw;
23980 /* The bandwidth value. */
23981 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MIN_BW_BW_VALUE_MASK \
23982 UINT32_C(0xfffffff)
23983 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MIN_BW_BW_VALUE_SFT \
23985 /* The granularity of the value (bits or bytes). */
23986 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MIN_BW_SCALE \
23987 UINT32_C(0x10000000)
23988 /* Value is in bits. */
23989 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MIN_BW_SCALE_BITS \
23990 (UINT32_C(0x0) << 28)
23991 /* Value is in bytes. */
23992 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MIN_BW_SCALE_BYTES \
23993 (UINT32_C(0x1) << 28)
23994 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MIN_BW_SCALE_LAST \
23995 HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MIN_BW_SCALE_BYTES
23996 /* bw_value_unit is 3 b */
23997 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_MASK \
23998 UINT32_C(0xe0000000)
23999 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_SFT \
24001 /* Value is in Mb or MB (base 10). */
24002 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_MEGA \
24003 (UINT32_C(0x0) << 29)
24004 /* Value is in Kb or KB (base 10). */
24005 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_KILO \
24006 (UINT32_C(0x2) << 29)
24007 /* Value is in bits or bytes. */
24008 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_BASE \
24009 (UINT32_C(0x4) << 29)
24010 /* Value is in Gb or GB (base 10). */
24011 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_GIGA \
24012 (UINT32_C(0x6) << 29)
24013 /* Value is in 1/100th of a percentage of total bandwidth. */
24014 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 \
24015 (UINT32_C(0x1) << 29)
24017 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_INVALID \
24018 (UINT32_C(0x7) << 29)
24019 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_LAST \
24020 HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_INVALID
24022 * Maximum BW allocated to CoS queue.
24023 * The HWRM will translate this value into byte counter and
24024 * time interval used for this COS inside the device.
24026 uint32_t queue_id1_max_bw;
24027 /* The bandwidth value. */
24028 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MAX_BW_BW_VALUE_MASK \
24029 UINT32_C(0xfffffff)
24030 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MAX_BW_BW_VALUE_SFT \
24032 /* The granularity of the value (bits or bytes). */
24033 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MAX_BW_SCALE \
24034 UINT32_C(0x10000000)
24035 /* Value is in bits. */
24036 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MAX_BW_SCALE_BITS \
24037 (UINT32_C(0x0) << 28)
24038 /* Value is in bytes. */
24039 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MAX_BW_SCALE_BYTES \
24040 (UINT32_C(0x1) << 28)
24041 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MAX_BW_SCALE_LAST \
24042 HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MAX_BW_SCALE_BYTES
24043 /* bw_value_unit is 3 b */
24044 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_MASK \
24045 UINT32_C(0xe0000000)
24046 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_SFT \
24048 /* Value is in Mb or MB (base 10). */
24049 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_MEGA \
24050 (UINT32_C(0x0) << 29)
24051 /* Value is in Kb or KB (base 10). */
24052 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_KILO \
24053 (UINT32_C(0x2) << 29)
24054 /* Value is in bits or bytes. */
24055 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_BASE \
24056 (UINT32_C(0x4) << 29)
24057 /* Value is in Gb or GB (base 10). */
24058 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_GIGA \
24059 (UINT32_C(0x6) << 29)
24060 /* Value is in 1/100th of a percentage of total bandwidth. */
24061 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 \
24062 (UINT32_C(0x1) << 29)
24064 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_INVALID \
24065 (UINT32_C(0x7) << 29)
24066 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_LAST \
24067 HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_INVALID
24068 /* Transmission Selection Algorithm (TSA) for CoS Queue. */
24069 uint8_t queue_id1_tsa_assign;
24070 /* Strict Priority */
24071 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_TSA_ASSIGN_SP \
24073 /* Enhanced Transmission Selection */
24074 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_TSA_ASSIGN_ETS \
24077 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_TSA_ASSIGN_RESERVED_FIRST \
24080 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_TSA_ASSIGN_RESERVED_LAST \
24083 * Priority level for strict priority. Valid only when the
24084 * tsa_assign is 0 - Strict Priority (SP)
24085 * 0..7 - Valid values.
24086 * 8..255 - Reserved.
24088 uint8_t queue_id1_pri_lvl;
24090 * Weight used to allocate remaining BW for this COS after
24091 * servicing guaranteed bandwidths for all COS.
24093 uint8_t queue_id1_bw_weight;
24094 /* ID of CoS Queue 2. */
24097 * Minimum BW allocated to CoS Queue.
24098 * The HWRM will translate this value into byte counter and
24099 * time interval used for this COS inside the device.
24101 uint32_t queue_id2_min_bw;
24102 /* The bandwidth value. */
24103 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MIN_BW_BW_VALUE_MASK \
24104 UINT32_C(0xfffffff)
24105 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MIN_BW_BW_VALUE_SFT \
24107 /* The granularity of the value (bits or bytes). */
24108 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MIN_BW_SCALE \
24109 UINT32_C(0x10000000)
24110 /* Value is in bits. */
24111 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MIN_BW_SCALE_BITS \
24112 (UINT32_C(0x0) << 28)
24113 /* Value is in bytes. */
24114 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MIN_BW_SCALE_BYTES \
24115 (UINT32_C(0x1) << 28)
24116 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MIN_BW_SCALE_LAST \
24117 HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MIN_BW_SCALE_BYTES
24118 /* bw_value_unit is 3 b */
24119 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_MASK \
24120 UINT32_C(0xe0000000)
24121 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_SFT \
24123 /* Value is in Mb or MB (base 10). */
24124 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_MEGA \
24125 (UINT32_C(0x0) << 29)
24126 /* Value is in Kb or KB (base 10). */
24127 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_KILO \
24128 (UINT32_C(0x2) << 29)
24129 /* Value is in bits or bytes. */
24130 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_BASE \
24131 (UINT32_C(0x4) << 29)
24132 /* Value is in Gb or GB (base 10). */
24133 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_GIGA \
24134 (UINT32_C(0x6) << 29)
24135 /* Value is in 1/100th of a percentage of total bandwidth. */
24136 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 \
24137 (UINT32_C(0x1) << 29)
24139 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_INVALID \
24140 (UINT32_C(0x7) << 29)
24141 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_LAST \
24142 HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_INVALID
24144 * Maximum BW allocated to CoS queue.
24145 * The HWRM will translate this value into byte counter and
24146 * time interval used for this COS inside the device.
24148 uint32_t queue_id2_max_bw;
24149 /* The bandwidth value. */
24150 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MAX_BW_BW_VALUE_MASK \
24151 UINT32_C(0xfffffff)
24152 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MAX_BW_BW_VALUE_SFT \
24154 /* The granularity of the value (bits or bytes). */
24155 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MAX_BW_SCALE \
24156 UINT32_C(0x10000000)
24157 /* Value is in bits. */
24158 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MAX_BW_SCALE_BITS \
24159 (UINT32_C(0x0) << 28)
24160 /* Value is in bytes. */
24161 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MAX_BW_SCALE_BYTES \
24162 (UINT32_C(0x1) << 28)
24163 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MAX_BW_SCALE_LAST \
24164 HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MAX_BW_SCALE_BYTES
24165 /* bw_value_unit is 3 b */
24166 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_MASK \
24167 UINT32_C(0xe0000000)
24168 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_SFT \
24170 /* Value is in Mb or MB (base 10). */
24171 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_MEGA \
24172 (UINT32_C(0x0) << 29)
24173 /* Value is in Kb or KB (base 10). */
24174 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_KILO \
24175 (UINT32_C(0x2) << 29)
24176 /* Value is in bits or bytes. */
24177 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_BASE \
24178 (UINT32_C(0x4) << 29)
24179 /* Value is in Gb or GB (base 10). */
24180 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_GIGA \
24181 (UINT32_C(0x6) << 29)
24182 /* Value is in 1/100th of a percentage of total bandwidth. */
24183 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 \
24184 (UINT32_C(0x1) << 29)
24186 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_INVALID \
24187 (UINT32_C(0x7) << 29)
24188 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_LAST \
24189 HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_INVALID
24190 /* Transmission Selection Algorithm (TSA) for CoS Queue. */
24191 uint8_t queue_id2_tsa_assign;
24192 /* Strict Priority */
24193 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_TSA_ASSIGN_SP \
24195 /* Enhanced Transmission Selection */
24196 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_TSA_ASSIGN_ETS \
24199 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_TSA_ASSIGN_RESERVED_FIRST \
24202 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_TSA_ASSIGN_RESERVED_LAST \
24205 * Priority level for strict priority. Valid only when the
24206 * tsa_assign is 0 - Strict Priority (SP)
24207 * 0..7 - Valid values.
24208 * 8..255 - Reserved.
24210 uint8_t queue_id2_pri_lvl;
24212 * Weight used to allocate remaining BW for this COS after
24213 * servicing guaranteed bandwidths for all COS.
24215 uint8_t queue_id2_bw_weight;
24216 /* ID of CoS Queue 3. */
24219 * Minimum BW allocated to CoS Queue.
24220 * The HWRM will translate this value into byte counter and
24221 * time interval used for this COS inside the device.
24223 uint32_t queue_id3_min_bw;
24224 /* The bandwidth value. */
24225 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MIN_BW_BW_VALUE_MASK \
24226 UINT32_C(0xfffffff)
24227 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MIN_BW_BW_VALUE_SFT \
24229 /* The granularity of the value (bits or bytes). */
24230 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MIN_BW_SCALE \
24231 UINT32_C(0x10000000)
24232 /* Value is in bits. */
24233 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MIN_BW_SCALE_BITS \
24234 (UINT32_C(0x0) << 28)
24235 /* Value is in bytes. */
24236 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MIN_BW_SCALE_BYTES \
24237 (UINT32_C(0x1) << 28)
24238 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MIN_BW_SCALE_LAST \
24239 HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MIN_BW_SCALE_BYTES
24240 /* bw_value_unit is 3 b */
24241 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_MASK \
24242 UINT32_C(0xe0000000)
24243 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_SFT \
24245 /* Value is in Mb or MB (base 10). */
24246 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_MEGA \
24247 (UINT32_C(0x0) << 29)
24248 /* Value is in Kb or KB (base 10). */
24249 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_KILO \
24250 (UINT32_C(0x2) << 29)
24251 /* Value is in bits or bytes. */
24252 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_BASE \
24253 (UINT32_C(0x4) << 29)
24254 /* Value is in Gb or GB (base 10). */
24255 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_GIGA \
24256 (UINT32_C(0x6) << 29)
24257 /* Value is in 1/100th of a percentage of total bandwidth. */
24258 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 \
24259 (UINT32_C(0x1) << 29)
24261 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_INVALID \
24262 (UINT32_C(0x7) << 29)
24263 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_LAST \
24264 HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_INVALID
24266 * Maximum BW allocated to CoS queue.
24267 * The HWRM will translate this value into byte counter and
24268 * time interval used for this COS inside the device.
24270 uint32_t queue_id3_max_bw;
24271 /* The bandwidth value. */
24272 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MAX_BW_BW_VALUE_MASK \
24273 UINT32_C(0xfffffff)
24274 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MAX_BW_BW_VALUE_SFT \
24276 /* The granularity of the value (bits or bytes). */
24277 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MAX_BW_SCALE \
24278 UINT32_C(0x10000000)
24279 /* Value is in bits. */
24280 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MAX_BW_SCALE_BITS \
24281 (UINT32_C(0x0) << 28)
24282 /* Value is in bytes. */
24283 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MAX_BW_SCALE_BYTES \
24284 (UINT32_C(0x1) << 28)
24285 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MAX_BW_SCALE_LAST \
24286 HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MAX_BW_SCALE_BYTES
24287 /* bw_value_unit is 3 b */
24288 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_MASK \
24289 UINT32_C(0xe0000000)
24290 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_SFT \
24292 /* Value is in Mb or MB (base 10). */
24293 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_MEGA \
24294 (UINT32_C(0x0) << 29)
24295 /* Value is in Kb or KB (base 10). */
24296 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_KILO \
24297 (UINT32_C(0x2) << 29)
24298 /* Value is in bits or bytes. */
24299 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_BASE \
24300 (UINT32_C(0x4) << 29)
24301 /* Value is in Gb or GB (base 10). */
24302 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_GIGA \
24303 (UINT32_C(0x6) << 29)
24304 /* Value is in 1/100th of a percentage of total bandwidth. */
24305 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 \
24306 (UINT32_C(0x1) << 29)
24308 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_INVALID \
24309 (UINT32_C(0x7) << 29)
24310 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_LAST \
24311 HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_INVALID
24312 /* Transmission Selection Algorithm (TSA) for CoS Queue. */
24313 uint8_t queue_id3_tsa_assign;
24314 /* Strict Priority */
24315 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_TSA_ASSIGN_SP \
24317 /* Enhanced Transmission Selection */
24318 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_TSA_ASSIGN_ETS \
24321 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_TSA_ASSIGN_RESERVED_FIRST \
24324 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_TSA_ASSIGN_RESERVED_LAST \
24327 * Priority level for strict priority. Valid only when the
24328 * tsa_assign is 0 - Strict Priority (SP)
24329 * 0..7 - Valid values.
24330 * 8..255 - Reserved.
24332 uint8_t queue_id3_pri_lvl;
24334 * Weight used to allocate remaining BW for this COS after
24335 * servicing guaranteed bandwidths for all COS.
24337 uint8_t queue_id3_bw_weight;
24338 /* ID of CoS Queue 4. */
24341 * Minimum BW allocated to CoS Queue.
24342 * The HWRM will translate this value into byte counter and
24343 * time interval used for this COS inside the device.
24345 uint32_t queue_id4_min_bw;
24346 /* The bandwidth value. */
24347 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MIN_BW_BW_VALUE_MASK \
24348 UINT32_C(0xfffffff)
24349 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MIN_BW_BW_VALUE_SFT \
24351 /* The granularity of the value (bits or bytes). */
24352 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MIN_BW_SCALE \
24353 UINT32_C(0x10000000)
24354 /* Value is in bits. */
24355 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MIN_BW_SCALE_BITS \
24356 (UINT32_C(0x0) << 28)
24357 /* Value is in bytes. */
24358 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MIN_BW_SCALE_BYTES \
24359 (UINT32_C(0x1) << 28)
24360 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MIN_BW_SCALE_LAST \
24361 HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MIN_BW_SCALE_BYTES
24362 /* bw_value_unit is 3 b */
24363 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_MASK \
24364 UINT32_C(0xe0000000)
24365 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_SFT \
24367 /* Value is in Mb or MB (base 10). */
24368 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_MEGA \
24369 (UINT32_C(0x0) << 29)
24370 /* Value is in Kb or KB (base 10). */
24371 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_KILO \
24372 (UINT32_C(0x2) << 29)
24373 /* Value is in bits or bytes. */
24374 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_BASE \
24375 (UINT32_C(0x4) << 29)
24376 /* Value is in Gb or GB (base 10). */
24377 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_GIGA \
24378 (UINT32_C(0x6) << 29)
24379 /* Value is in 1/100th of a percentage of total bandwidth. */
24380 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 \
24381 (UINT32_C(0x1) << 29)
24383 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_INVALID \
24384 (UINT32_C(0x7) << 29)
24385 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_LAST \
24386 HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_INVALID
24388 * Maximum BW allocated to CoS queue.
24389 * The HWRM will translate this value into byte counter and
24390 * time interval used for this COS inside the device.
24392 uint32_t queue_id4_max_bw;
24393 /* The bandwidth value. */
24394 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MAX_BW_BW_VALUE_MASK \
24395 UINT32_C(0xfffffff)
24396 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MAX_BW_BW_VALUE_SFT \
24398 /* The granularity of the value (bits or bytes). */
24399 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MAX_BW_SCALE \
24400 UINT32_C(0x10000000)
24401 /* Value is in bits. */
24402 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MAX_BW_SCALE_BITS \
24403 (UINT32_C(0x0) << 28)
24404 /* Value is in bytes. */
24405 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MAX_BW_SCALE_BYTES \
24406 (UINT32_C(0x1) << 28)
24407 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MAX_BW_SCALE_LAST \
24408 HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MAX_BW_SCALE_BYTES
24409 /* bw_value_unit is 3 b */
24410 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_MASK \
24411 UINT32_C(0xe0000000)
24412 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_SFT \
24414 /* Value is in Mb or MB (base 10). */
24415 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_MEGA \
24416 (UINT32_C(0x0) << 29)
24417 /* Value is in Kb or KB (base 10). */
24418 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_KILO \
24419 (UINT32_C(0x2) << 29)
24420 /* Value is in bits or bytes. */
24421 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_BASE \
24422 (UINT32_C(0x4) << 29)
24423 /* Value is in Gb or GB (base 10). */
24424 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_GIGA \
24425 (UINT32_C(0x6) << 29)
24426 /* Value is in 1/100th of a percentage of total bandwidth. */
24427 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 \
24428 (UINT32_C(0x1) << 29)
24430 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_INVALID \
24431 (UINT32_C(0x7) << 29)
24432 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_LAST \
24433 HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_INVALID
24434 /* Transmission Selection Algorithm (TSA) for CoS Queue. */
24435 uint8_t queue_id4_tsa_assign;
24436 /* Strict Priority */
24437 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_TSA_ASSIGN_SP \
24439 /* Enhanced Transmission Selection */
24440 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_TSA_ASSIGN_ETS \
24443 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_TSA_ASSIGN_RESERVED_FIRST \
24446 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_TSA_ASSIGN_RESERVED_LAST \
24449 * Priority level for strict priority. Valid only when the
24450 * tsa_assign is 0 - Strict Priority (SP)
24451 * 0..7 - Valid values.
24452 * 8..255 - Reserved.
24454 uint8_t queue_id4_pri_lvl;
24456 * Weight used to allocate remaining BW for this COS after
24457 * servicing guaranteed bandwidths for all COS.
24459 uint8_t queue_id4_bw_weight;
24460 /* ID of CoS Queue 5. */
24463 * Minimum BW allocated to CoS Queue.
24464 * The HWRM will translate this value into byte counter and
24465 * time interval used for this COS inside the device.
24467 uint32_t queue_id5_min_bw;
24468 /* The bandwidth value. */
24469 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MIN_BW_BW_VALUE_MASK \
24470 UINT32_C(0xfffffff)
24471 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MIN_BW_BW_VALUE_SFT \
24473 /* The granularity of the value (bits or bytes). */
24474 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MIN_BW_SCALE \
24475 UINT32_C(0x10000000)
24476 /* Value is in bits. */
24477 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MIN_BW_SCALE_BITS \
24478 (UINT32_C(0x0) << 28)
24479 /* Value is in bytes. */
24480 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MIN_BW_SCALE_BYTES \
24481 (UINT32_C(0x1) << 28)
24482 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MIN_BW_SCALE_LAST \
24483 HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MIN_BW_SCALE_BYTES
24484 /* bw_value_unit is 3 b */
24485 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_MASK \
24486 UINT32_C(0xe0000000)
24487 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_SFT \
24489 /* Value is in Mb or MB (base 10). */
24490 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_MEGA \
24491 (UINT32_C(0x0) << 29)
24492 /* Value is in Kb or KB (base 10). */
24493 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_KILO \
24494 (UINT32_C(0x2) << 29)
24495 /* Value is in bits or bytes. */
24496 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_BASE \
24497 (UINT32_C(0x4) << 29)
24498 /* Value is in Gb or GB (base 10). */
24499 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_GIGA \
24500 (UINT32_C(0x6) << 29)
24501 /* Value is in 1/100th of a percentage of total bandwidth. */
24502 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 \
24503 (UINT32_C(0x1) << 29)
24505 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_INVALID \
24506 (UINT32_C(0x7) << 29)
24507 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_LAST \
24508 HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_INVALID
24510 * Maximum BW allocated to CoS queue.
24511 * The HWRM will translate this value into byte counter and
24512 * time interval used for this COS inside the device.
24514 uint32_t queue_id5_max_bw;
24515 /* The bandwidth value. */
24516 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MAX_BW_BW_VALUE_MASK \
24517 UINT32_C(0xfffffff)
24518 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MAX_BW_BW_VALUE_SFT \
24520 /* The granularity of the value (bits or bytes). */
24521 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MAX_BW_SCALE \
24522 UINT32_C(0x10000000)
24523 /* Value is in bits. */
24524 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MAX_BW_SCALE_BITS \
24525 (UINT32_C(0x0) << 28)
24526 /* Value is in bytes. */
24527 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MAX_BW_SCALE_BYTES \
24528 (UINT32_C(0x1) << 28)
24529 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MAX_BW_SCALE_LAST \
24530 HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MAX_BW_SCALE_BYTES
24531 /* bw_value_unit is 3 b */
24532 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_MASK \
24533 UINT32_C(0xe0000000)
24534 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_SFT \
24536 /* Value is in Mb or MB (base 10). */
24537 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_MEGA \
24538 (UINT32_C(0x0) << 29)
24539 /* Value is in Kb or KB (base 10). */
24540 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_KILO \
24541 (UINT32_C(0x2) << 29)
24542 /* Value is in bits or bytes. */
24543 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_BASE \
24544 (UINT32_C(0x4) << 29)
24545 /* Value is in Gb or GB (base 10). */
24546 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_GIGA \
24547 (UINT32_C(0x6) << 29)
24548 /* Value is in 1/100th of a percentage of total bandwidth. */
24549 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 \
24550 (UINT32_C(0x1) << 29)
24552 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_INVALID \
24553 (UINT32_C(0x7) << 29)
24554 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_LAST \
24555 HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_INVALID
24556 /* Transmission Selection Algorithm (TSA) for CoS Queue. */
24557 uint8_t queue_id5_tsa_assign;
24558 /* Strict Priority */
24559 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_TSA_ASSIGN_SP \
24561 /* Enhanced Transmission Selection */
24562 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_TSA_ASSIGN_ETS \
24565 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_TSA_ASSIGN_RESERVED_FIRST \
24568 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_TSA_ASSIGN_RESERVED_LAST \
24571 * Priority level for strict priority. Valid only when the
24572 * tsa_assign is 0 - Strict Priority (SP)
24573 * 0..7 - Valid values.
24574 * 8..255 - Reserved.
24576 uint8_t queue_id5_pri_lvl;
24578 * Weight used to allocate remaining BW for this COS after
24579 * servicing guaranteed bandwidths for all COS.
24581 uint8_t queue_id5_bw_weight;
24582 /* ID of CoS Queue 6. */
24585 * Minimum BW allocated to CoS Queue.
24586 * The HWRM will translate this value into byte counter and
24587 * time interval used for this COS inside the device.
24589 uint32_t queue_id6_min_bw;
24590 /* The bandwidth value. */
24591 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MIN_BW_BW_VALUE_MASK \
24592 UINT32_C(0xfffffff)
24593 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MIN_BW_BW_VALUE_SFT \
24595 /* The granularity of the value (bits or bytes). */
24596 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MIN_BW_SCALE \
24597 UINT32_C(0x10000000)
24598 /* Value is in bits. */
24599 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MIN_BW_SCALE_BITS \
24600 (UINT32_C(0x0) << 28)
24601 /* Value is in bytes. */
24602 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MIN_BW_SCALE_BYTES \
24603 (UINT32_C(0x1) << 28)
24604 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MIN_BW_SCALE_LAST \
24605 HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MIN_BW_SCALE_BYTES
24606 /* bw_value_unit is 3 b */
24607 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_MASK \
24608 UINT32_C(0xe0000000)
24609 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_SFT \
24611 /* Value is in Mb or MB (base 10). */
24612 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_MEGA \
24613 (UINT32_C(0x0) << 29)
24614 /* Value is in Kb or KB (base 10). */
24615 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_KILO \
24616 (UINT32_C(0x2) << 29)
24617 /* Value is in bits or bytes. */
24618 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_BASE \
24619 (UINT32_C(0x4) << 29)
24620 /* Value is in Gb or GB (base 10). */
24621 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_GIGA \
24622 (UINT32_C(0x6) << 29)
24623 /* Value is in 1/100th of a percentage of total bandwidth. */
24624 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 \
24625 (UINT32_C(0x1) << 29)
24627 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_INVALID \
24628 (UINT32_C(0x7) << 29)
24629 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_LAST \
24630 HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_INVALID
24632 * Maximum BW allocated to CoS queue.
24633 * The HWRM will translate this value into byte counter and
24634 * time interval used for this COS inside the device.
24636 uint32_t queue_id6_max_bw;
24637 /* The bandwidth value. */
24638 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MAX_BW_BW_VALUE_MASK \
24639 UINT32_C(0xfffffff)
24640 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MAX_BW_BW_VALUE_SFT \
24642 /* The granularity of the value (bits or bytes). */
24643 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MAX_BW_SCALE \
24644 UINT32_C(0x10000000)
24645 /* Value is in bits. */
24646 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MAX_BW_SCALE_BITS \
24647 (UINT32_C(0x0) << 28)
24648 /* Value is in bytes. */
24649 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MAX_BW_SCALE_BYTES \
24650 (UINT32_C(0x1) << 28)
24651 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MAX_BW_SCALE_LAST \
24652 HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MAX_BW_SCALE_BYTES
24653 /* bw_value_unit is 3 b */
24654 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_MASK \
24655 UINT32_C(0xe0000000)
24656 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_SFT \
24658 /* Value is in Mb or MB (base 10). */
24659 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_MEGA \
24660 (UINT32_C(0x0) << 29)
24661 /* Value is in Kb or KB (base 10). */
24662 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_KILO \
24663 (UINT32_C(0x2) << 29)
24664 /* Value is in bits or bytes. */
24665 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_BASE \
24666 (UINT32_C(0x4) << 29)
24667 /* Value is in Gb or GB (base 10). */
24668 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_GIGA \
24669 (UINT32_C(0x6) << 29)
24670 /* Value is in 1/100th of a percentage of total bandwidth. */
24671 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 \
24672 (UINT32_C(0x1) << 29)
24674 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_INVALID \
24675 (UINT32_C(0x7) << 29)
24676 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_LAST \
24677 HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_INVALID
24678 /* Transmission Selection Algorithm (TSA) for CoS Queue. */
24679 uint8_t queue_id6_tsa_assign;
24680 /* Strict Priority */
24681 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_TSA_ASSIGN_SP \
24683 /* Enhanced Transmission Selection */
24684 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_TSA_ASSIGN_ETS \
24687 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_TSA_ASSIGN_RESERVED_FIRST \
24690 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_TSA_ASSIGN_RESERVED_LAST \
24693 * Priority level for strict priority. Valid only when the
24694 * tsa_assign is 0 - Strict Priority (SP)
24695 * 0..7 - Valid values.
24696 * 8..255 - Reserved.
24698 uint8_t queue_id6_pri_lvl;
24700 * Weight used to allocate remaining BW for this COS after
24701 * servicing guaranteed bandwidths for all COS.
24703 uint8_t queue_id6_bw_weight;
24704 /* ID of CoS Queue 7. */
24707 * Minimum BW allocated to CoS Queue.
24708 * The HWRM will translate this value into byte counter and
24709 * time interval used for this COS inside the device.
24711 uint32_t queue_id7_min_bw;
24712 /* The bandwidth value. */
24713 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MIN_BW_BW_VALUE_MASK \
24714 UINT32_C(0xfffffff)
24715 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MIN_BW_BW_VALUE_SFT \
24717 /* The granularity of the value (bits or bytes). */
24718 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MIN_BW_SCALE \
24719 UINT32_C(0x10000000)
24720 /* Value is in bits. */
24721 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MIN_BW_SCALE_BITS \
24722 (UINT32_C(0x0) << 28)
24723 /* Value is in bytes. */
24724 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MIN_BW_SCALE_BYTES \
24725 (UINT32_C(0x1) << 28)
24726 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MIN_BW_SCALE_LAST \
24727 HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MIN_BW_SCALE_BYTES
24728 /* bw_value_unit is 3 b */
24729 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_MASK \
24730 UINT32_C(0xe0000000)
24731 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_SFT \
24733 /* Value is in Mb or MB (base 10). */
24734 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_MEGA \
24735 (UINT32_C(0x0) << 29)
24736 /* Value is in Kb or KB (base 10). */
24737 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_KILO \
24738 (UINT32_C(0x2) << 29)
24739 /* Value is in bits or bytes. */
24740 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_BASE \
24741 (UINT32_C(0x4) << 29)
24742 /* Value is in Gb or GB (base 10). */
24743 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_GIGA \
24744 (UINT32_C(0x6) << 29)
24745 /* Value is in 1/100th of a percentage of total bandwidth. */
24746 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 \
24747 (UINT32_C(0x1) << 29)
24749 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_INVALID \
24750 (UINT32_C(0x7) << 29)
24751 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_LAST \
24752 HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_INVALID
24754 * Maximum BW allocated to CoS queue.
24755 * The HWRM will translate this value into byte counter and
24756 * time interval used for this COS inside the device.
24758 uint32_t queue_id7_max_bw;
24759 /* The bandwidth value. */
24760 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MAX_BW_BW_VALUE_MASK \
24761 UINT32_C(0xfffffff)
24762 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MAX_BW_BW_VALUE_SFT \
24764 /* The granularity of the value (bits or bytes). */
24765 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MAX_BW_SCALE \
24766 UINT32_C(0x10000000)
24767 /* Value is in bits. */
24768 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MAX_BW_SCALE_BITS \
24769 (UINT32_C(0x0) << 28)
24770 /* Value is in bytes. */
24771 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MAX_BW_SCALE_BYTES \
24772 (UINT32_C(0x1) << 28)
24773 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MAX_BW_SCALE_LAST \
24774 HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MAX_BW_SCALE_BYTES
24775 /* bw_value_unit is 3 b */
24776 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_MASK \
24777 UINT32_C(0xe0000000)
24778 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_SFT \
24780 /* Value is in Mb or MB (base 10). */
24781 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_MEGA \
24782 (UINT32_C(0x0) << 29)
24783 /* Value is in Kb or KB (base 10). */
24784 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_KILO \
24785 (UINT32_C(0x2) << 29)
24786 /* Value is in bits or bytes. */
24787 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_BASE \
24788 (UINT32_C(0x4) << 29)
24789 /* Value is in Gb or GB (base 10). */
24790 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_GIGA \
24791 (UINT32_C(0x6) << 29)
24792 /* Value is in 1/100th of a percentage of total bandwidth. */
24793 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 \
24794 (UINT32_C(0x1) << 29)
24796 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_INVALID \
24797 (UINT32_C(0x7) << 29)
24798 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_LAST \
24799 HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_INVALID
24800 /* Transmission Selection Algorithm (TSA) for CoS Queue. */
24801 uint8_t queue_id7_tsa_assign;
24802 /* Strict Priority */
24803 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_TSA_ASSIGN_SP \
24805 /* Enhanced Transmission Selection */
24806 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_TSA_ASSIGN_ETS \
24809 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_TSA_ASSIGN_RESERVED_FIRST \
24812 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_TSA_ASSIGN_RESERVED_LAST \
24815 * Priority level for strict priority. Valid only when the
24816 * tsa_assign is 0 - Strict Priority (SP)
24817 * 0..7 - Valid values.
24818 * 8..255 - Reserved.
24820 uint8_t queue_id7_pri_lvl;
24822 * Weight used to allocate remaining BW for this COS after
24823 * servicing guaranteed bandwidths for all COS.
24825 uint8_t queue_id7_bw_weight;
24826 uint8_t unused_1[5];
24829 /* hwrm_queue_cos2bw_cfg_output (size:128b/16B) */
24830 struct hwrm_queue_cos2bw_cfg_output {
24831 /* The specific error status for the command. */
24832 uint16_t error_code;
24833 /* The HWRM command request type. */
24835 /* The sequence ID from the original command. */
24837 /* The length of the response data in number of bytes. */
24839 uint8_t unused_0[7];
24841 * This field is used in Output records to indicate that the output
24842 * is completely written to RAM. This field should be read as '1'
24843 * to indicate that the output has been completely written.
24844 * When writing a command completion or response to an internal processor,
24845 * the order of writes has to be such that this field is written last.
24850 /*************************
24851 * hwrm_queue_dscp_qcaps *
24852 *************************/
24855 /* hwrm_queue_dscp_qcaps_input (size:192b/24B) */
24856 struct hwrm_queue_dscp_qcaps_input {
24857 /* The HWRM command request type. */
24860 * The completion ring to send the completion event on. This should
24861 * be the NQ ID returned from the `nq_alloc` HWRM command.
24863 uint16_t cmpl_ring;
24865 * The sequence ID is used by the driver for tracking multiple
24866 * commands. This ID is treated as opaque data by the firmware and
24867 * the value is returned in the `hwrm_resp_hdr` upon completion.
24871 * The target ID of the command:
24872 * * 0x0-0xFFF8 - The function ID
24873 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
24874 * * 0xFFFD - Reserved for user-space HWRM interface
24877 uint16_t target_id;
24879 * A physical address pointer pointing to a host buffer that the
24880 * command's response data will be written. This can be either a host
24881 * physical address (HPA) or a guest physical address (GPA) and must
24882 * point to a physically contiguous block of memory.
24884 uint64_t resp_addr;
24886 * Port ID of port for which the table is being configured.
24887 * The HWRM needs to check whether this function is allowed
24888 * to configure pri2cos mapping on this port.
24891 uint8_t unused_0[7];
24894 /* hwrm_queue_dscp_qcaps_output (size:128b/16B) */
24895 struct hwrm_queue_dscp_qcaps_output {
24896 /* The specific error status for the command. */
24897 uint16_t error_code;
24898 /* The HWRM command request type. */
24900 /* The sequence ID from the original command. */
24902 /* The length of the response data in number of bytes. */
24904 /* The number of bits provided by the hardware for the DSCP value. */
24905 uint8_t num_dscp_bits;
24907 /* Max number of DSCP-MASK-PRI entries supported. */
24908 uint16_t max_entries;
24909 uint8_t unused_1[3];
24911 * This field is used in Output records to indicate that the output
24912 * is completely written to RAM. This field should be read as '1'
24913 * to indicate that the output has been completely written.
24914 * When writing a command completion or response to an internal processor,
24915 * the order of writes has to be such that this field is written last.
24920 /****************************
24921 * hwrm_queue_dscp2pri_qcfg *
24922 ****************************/
24925 /* hwrm_queue_dscp2pri_qcfg_input (size:256b/32B) */
24926 struct hwrm_queue_dscp2pri_qcfg_input {
24927 /* The HWRM command request type. */
24930 * The completion ring to send the completion event on. This should
24931 * be the NQ ID returned from the `nq_alloc` HWRM command.
24933 uint16_t cmpl_ring;
24935 * The sequence ID is used by the driver for tracking multiple
24936 * commands. This ID is treated as opaque data by the firmware and
24937 * the value is returned in the `hwrm_resp_hdr` upon completion.
24941 * The target ID of the command:
24942 * * 0x0-0xFFF8 - The function ID
24943 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
24944 * * 0xFFFD - Reserved for user-space HWRM interface
24947 uint16_t target_id;
24949 * A physical address pointer pointing to a host buffer that the
24950 * command's response data will be written. This can be either a host
24951 * physical address (HPA) or a guest physical address (GPA) and must
24952 * point to a physically contiguous block of memory.
24954 uint64_t resp_addr;
24956 * This is the host address where the 24-bits DSCP-MASK-PRI
24957 * tuple(s) will be copied to.
24959 uint64_t dest_data_addr;
24961 * Port ID of port for which the table is being configured.
24962 * The HWRM needs to check whether this function is allowed
24963 * to configure pri2cos mapping on this port.
24967 /* Size of the buffer pointed to by dest_data_addr. */
24968 uint16_t dest_data_buffer_size;
24969 uint8_t unused_1[4];
24972 /* hwrm_queue_dscp2pri_qcfg_output (size:128b/16B) */
24973 struct hwrm_queue_dscp2pri_qcfg_output {
24974 /* The specific error status for the command. */
24975 uint16_t error_code;
24976 /* The HWRM command request type. */
24978 /* The sequence ID from the original command. */
24980 /* The length of the response data in number of bytes. */
24983 * A count of the number of DSCP-MASK-PRI tuple(s) pointed to
24984 * by the dest_data_addr.
24986 uint16_t entry_cnt;
24988 * This is the default PRI which un-initialized DSCP values are
24991 uint8_t default_pri;
24992 uint8_t unused_0[4];
24994 * This field is used in Output records to indicate that the output
24995 * is completely written to RAM. This field should be read as '1'
24996 * to indicate that the output has been completely written.
24997 * When writing a command completion or response to an internal processor,
24998 * the order of writes has to be such that this field is written last.
25003 /***************************
25004 * hwrm_queue_dscp2pri_cfg *
25005 ***************************/
25008 /* hwrm_queue_dscp2pri_cfg_input (size:320b/40B) */
25009 struct hwrm_queue_dscp2pri_cfg_input {
25010 /* The HWRM command request type. */
25013 * The completion ring to send the completion event on. This should
25014 * be the NQ ID returned from the `nq_alloc` HWRM command.
25016 uint16_t cmpl_ring;
25018 * The sequence ID is used by the driver for tracking multiple
25019 * commands. This ID is treated as opaque data by the firmware and
25020 * the value is returned in the `hwrm_resp_hdr` upon completion.
25024 * The target ID of the command:
25025 * * 0x0-0xFFF8 - The function ID
25026 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
25027 * * 0xFFFD - Reserved for user-space HWRM interface
25030 uint16_t target_id;
25032 * A physical address pointer pointing to a host buffer that the
25033 * command's response data will be written. This can be either a host
25034 * physical address (HPA) or a guest physical address (GPA) and must
25035 * point to a physically contiguous block of memory.
25037 uint64_t resp_addr;
25039 * This is the host address where the 24-bits DSCP-MASK-PRI tuple
25040 * will be copied from.
25042 uint64_t src_data_addr;
25044 /* use_hw_default_pri is 1 b */
25045 #define HWRM_QUEUE_DSCP2PRI_CFG_INPUT_FLAGS_USE_HW_DEFAULT_PRI \
25049 * This bit must be '1' for the default_pri field to be
25052 #define HWRM_QUEUE_DSCP2PRI_CFG_INPUT_ENABLES_DEFAULT_PRI \
25055 * Port ID of port for which the table is being configured.
25056 * The HWRM needs to check whether this function is allowed
25057 * to configure pri2cos mapping on this port.
25061 * This is the default PRI which un-initialized DSCP values will be
25064 uint8_t default_pri;
25066 * A count of the number of DSCP-MASK-PRI tuple(s) in the data pointed
25067 * to by src_data_addr.
25069 uint16_t entry_cnt;
25070 uint8_t unused_0[4];
25073 /* hwrm_queue_dscp2pri_cfg_output (size:128b/16B) */
25074 struct hwrm_queue_dscp2pri_cfg_output {
25075 /* The specific error status for the command. */
25076 uint16_t error_code;
25077 /* The HWRM command request type. */
25079 /* The sequence ID from the original command. */
25081 /* The length of the response data in number of bytes. */
25083 uint8_t unused_0[7];
25085 * This field is used in Output records to indicate that the output
25086 * is completely written to RAM. This field should be read as '1'
25087 * to indicate that the output has been completely written.
25088 * When writing a command completion or response to an internal processor,
25089 * the order of writes has to be such that this field is written last.
25094 /*************************
25095 * hwrm_queue_mpls_qcaps *
25096 *************************/
25099 /* hwrm_queue_mpls_qcaps_input (size:192b/24B) */
25100 struct hwrm_queue_mpls_qcaps_input {
25101 /* The HWRM command request type. */
25104 * The completion ring to send the completion event on. This should
25105 * be the NQ ID returned from the `nq_alloc` HWRM command.
25107 uint16_t cmpl_ring;
25109 * The sequence ID is used by the driver for tracking multiple
25110 * commands. This ID is treated as opaque data by the firmware and
25111 * the value is returned in the `hwrm_resp_hdr` upon completion.
25115 * The target ID of the command:
25116 * * 0x0-0xFFF8 - The function ID
25117 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
25118 * * 0xFFFD - Reserved for user-space HWRM interface
25121 uint16_t target_id;
25123 * A physical address pointer pointing to a host buffer that the
25124 * command's response data will be written. This can be either a host
25125 * physical address (HPA) or a guest physical address (GPA) and must
25126 * point to a physically contiguous block of memory.
25128 uint64_t resp_addr;
25130 * Port ID of port for which the table is being configured.
25131 * The HWRM needs to check whether this function is allowed
25132 * to configure MPLS TC(EXP) to pri mapping on this port.
25135 uint8_t unused_0[7];
25138 /* hwrm_queue_mpls_qcaps_output (size:128b/16B) */
25139 struct hwrm_queue_mpls_qcaps_output {
25140 /* The specific error status for the command. */
25141 uint16_t error_code;
25142 /* The HWRM command request type. */
25144 /* The sequence ID from the original command. */
25146 /* The length of the response data in number of bytes. */
25149 * Bitmask indicating which queues can be configured by the
25150 * hwrm_queue_mplstc2pri_cfg command.
25152 * Each bit represents a specific pri where bit 0 represents
25153 * pri 0 and bit 7 represents pri 7.
25154 * # A value of 0 indicates that the pri is not configurable
25155 * by the hwrm_queue_mplstc2pri_cfg command.
25156 * # A value of 1 indicates that the pri is configurable.
25157 * # A hwrm_queue_mplstc2pri_cfg command shall return error when
25158 * trying to configure a pri that is not configurable.
25160 uint8_t queue_mplstc2pri_cfg_allowed;
25162 * This is the default PRI which un-initialized MPLS values will be
25165 uint8_t hw_default_pri;
25166 uint8_t unused_0[5];
25168 * This field is used in Output records to indicate that the output
25169 * is completely written to RAM. This field should be read as '1'
25170 * to indicate that the output has been completely written.
25171 * When writing a command completion or response to an internal processor,
25172 * the order of writes has to be such that this field is written last.
25177 /******************************
25178 * hwrm_queue_mplstc2pri_qcfg *
25179 ******************************/
25182 /* hwrm_queue_mplstc2pri_qcfg_input (size:192b/24B) */
25183 struct hwrm_queue_mplstc2pri_qcfg_input {
25184 /* The HWRM command request type. */
25187 * The completion ring to send the completion event on. This should
25188 * be the NQ ID returned from the `nq_alloc` HWRM command.
25190 uint16_t cmpl_ring;
25192 * The sequence ID is used by the driver for tracking multiple
25193 * commands. This ID is treated as opaque data by the firmware and
25194 * the value is returned in the `hwrm_resp_hdr` upon completion.
25198 * The target ID of the command:
25199 * * 0x0-0xFFF8 - The function ID
25200 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
25201 * * 0xFFFD - Reserved for user-space HWRM interface
25204 uint16_t target_id;
25206 * A physical address pointer pointing to a host buffer that the
25207 * command's response data will be written. This can be either a host
25208 * physical address (HPA) or a guest physical address (GPA) and must
25209 * point to a physically contiguous block of memory.
25211 uint64_t resp_addr;
25213 * Port ID of port for which the table is being configured.
25214 * The HWRM needs to check whether this function is allowed
25215 * to configure MPLS TC(EXP) to pri mapping on this port.
25218 uint8_t unused_0[7];
25221 /* hwrm_queue_mplstc2pri_qcfg_output (size:192b/24B) */
25222 struct hwrm_queue_mplstc2pri_qcfg_output {
25223 /* The specific error status for the command. */
25224 uint16_t error_code;
25225 /* The HWRM command request type. */
25227 /* The sequence ID from the original command. */
25229 /* The length of the response data in number of bytes. */
25232 * pri assigned to MPLS TC(EXP) 0. This value can only be changed
25233 * before traffic has started.
25234 * A value of 0xff indicates that no pri is assigned to the
25237 uint8_t tc0_pri_queue_id;
25239 * pri assigned to MPLS TC(EXP) 1. This value can only be changed
25240 * before traffic has started.
25241 * A value of 0xff indicates that no pri is assigned to the
25244 uint8_t tc1_pri_queue_id;
25246 * pri assigned to MPLS TC(EXP) 2. This value can only be changed
25247 * before traffic has started.
25248 * A value of 0xff indicates that no pri is assigned to the
25251 uint8_t tc2_pri_queue_id;
25253 * pri assigned to MPLS TC(EXP) 3. This value can only be changed
25254 * before traffic has started.
25255 * A value of 0xff indicates that no pri is assigned to the
25258 uint8_t tc3_pri_queue_id;
25260 * pri assigned to MPLS TC(EXP) 4. This value can only be changed
25261 * before traffic has started.
25262 * A value of 0xff indicates that no pri is assigned to the
25265 uint8_t tc4_pri_queue_id;
25267 * pri assigned to MPLS TC(EXP) 5. This value can only be changed
25268 * before traffic has started.
25269 * A value of 0xff indicates that no pri is assigned to the
25272 uint8_t tc5_pri_queue_id;
25274 * pri assigned to MPLS TC(EXP) 6. This value can only
25275 * be changed before traffic has started.
25276 * A value of 0xff indicates that no pri is assigned to the
25279 uint8_t tc6_pri_queue_id;
25281 * pri assigned to MPLS TC(EXP) 7. This value can only
25282 * be changed before traffic has started.
25283 * A value of 0xff indicates that no pri is assigned to the
25286 uint8_t tc7_pri_queue_id;
25287 uint8_t unused_0[7];
25289 * This field is used in Output records to indicate that the output
25290 * is completely written to RAM. This field should be read as '1'
25291 * to indicate that the output has been completely written.
25292 * When writing a command completion or response to an internal processor,
25293 * the order of writes has to be such that this field is written last.
25298 /*****************************
25299 * hwrm_queue_mplstc2pri_cfg *
25300 *****************************/
25303 /* hwrm_queue_mplstc2pri_cfg_input (size:256b/32B) */
25304 struct hwrm_queue_mplstc2pri_cfg_input {
25305 /* The HWRM command request type. */
25308 * The completion ring to send the completion event on. This should
25309 * be the NQ ID returned from the `nq_alloc` HWRM command.
25311 uint16_t cmpl_ring;
25313 * The sequence ID is used by the driver for tracking multiple
25314 * commands. This ID is treated as opaque data by the firmware and
25315 * the value is returned in the `hwrm_resp_hdr` upon completion.
25319 * The target ID of the command:
25320 * * 0x0-0xFFF8 - The function ID
25321 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
25322 * * 0xFFFD - Reserved for user-space HWRM interface
25325 uint16_t target_id;
25327 * A physical address pointer pointing to a host buffer that the
25328 * command's response data will be written. This can be either a host
25329 * physical address (HPA) or a guest physical address (GPA) and must
25330 * point to a physically contiguous block of memory.
25332 uint64_t resp_addr;
25335 * This bit must be '1' for the mplstc0_pri_queue_id field to be
25338 #define HWRM_QUEUE_MPLSTC2PRI_CFG_INPUT_ENABLES_TC0_PRI_QUEUE_ID \
25341 * This bit must be '1' for the mplstc1_pri_queue_id field to be
25344 #define HWRM_QUEUE_MPLSTC2PRI_CFG_INPUT_ENABLES_TC1_PRI_QUEUE_ID \
25347 * This bit must be '1' for the mplstc2_pri_queue_id field to be
25350 #define HWRM_QUEUE_MPLSTC2PRI_CFG_INPUT_ENABLES_TC2_PRI_QUEUE_ID \
25353 * This bit must be '1' for the mplstc3_pri_queue_id field to be
25356 #define HWRM_QUEUE_MPLSTC2PRI_CFG_INPUT_ENABLES_TC3_PRI_QUEUE_ID \
25359 * This bit must be '1' for the mplstc4_pri_queue_id field to be
25362 #define HWRM_QUEUE_MPLSTC2PRI_CFG_INPUT_ENABLES_TC4_PRI_QUEUE_ID \
25365 * This bit must be '1' for the mplstc5_pri_queue_id field to be
25368 #define HWRM_QUEUE_MPLSTC2PRI_CFG_INPUT_ENABLES_TC5_PRI_QUEUE_ID \
25371 * This bit must be '1' for the mplstc6_pri_queue_id field to be
25374 #define HWRM_QUEUE_MPLSTC2PRI_CFG_INPUT_ENABLES_TC6_PRI_QUEUE_ID \
25377 * This bit must be '1' for the mplstc7_pri_queue_id field to be
25380 #define HWRM_QUEUE_MPLSTC2PRI_CFG_INPUT_ENABLES_TC7_PRI_QUEUE_ID \
25383 * Port ID of port for which the table is being configured.
25384 * The HWRM needs to check whether this function is allowed
25385 * to configure MPLS TC(EXP)to pri mapping on this port.
25388 uint8_t unused_0[3];
25390 * pri assigned to MPLS TC(EXP) 0. This value can only
25391 * be changed before traffic has started.
25393 uint8_t tc0_pri_queue_id;
25395 * pri assigned to MPLS TC(EXP) 1. This value can only
25396 * be changed before traffic has started.
25398 uint8_t tc1_pri_queue_id;
25400 * pri assigned to MPLS TC(EXP) 2 This value can only
25401 * be changed before traffic has started.
25403 uint8_t tc2_pri_queue_id;
25405 * pri assigned to MPLS TC(EXP) 3. This value can only
25406 * be changed before traffic has started.
25408 uint8_t tc3_pri_queue_id;
25410 * pri assigned to MPLS TC(EXP) 4. This value can only
25411 * be changed before traffic has started.
25413 uint8_t tc4_pri_queue_id;
25415 * pri assigned to MPLS TC(EXP) 5. This value can only
25416 * be changed before traffic has started.
25418 uint8_t tc5_pri_queue_id;
25420 * pri assigned to MPLS TC(EXP) 6. This value can only
25421 * be changed before traffic has started.
25423 uint8_t tc6_pri_queue_id;
25425 * pri assigned to MPLS TC(EXP) 7. This value can only
25426 * be changed before traffic has started.
25428 uint8_t tc7_pri_queue_id;
25431 /* hwrm_queue_mplstc2pri_cfg_output (size:128b/16B) */
25432 struct hwrm_queue_mplstc2pri_cfg_output {
25433 /* The specific error status for the command. */
25434 uint16_t error_code;
25435 /* The HWRM command request type. */
25437 /* The sequence ID from the original command. */
25439 /* The length of the response data in number of bytes. */
25441 uint8_t unused_0[7];
25443 * This field is used in Output records to indicate that the output
25444 * is completely written to RAM. This field should be read as '1'
25445 * to indicate that the output has been completely written.
25446 * When writing a command completion or response to an internal processor,
25447 * the order of writes has to be such that this field is written last.
25452 /*******************
25453 * hwrm_vnic_alloc *
25454 *******************/
25457 /* hwrm_vnic_alloc_input (size:192b/24B) */
25458 struct hwrm_vnic_alloc_input {
25459 /* The HWRM command request type. */
25462 * The completion ring to send the completion event on. This should
25463 * be the NQ ID returned from the `nq_alloc` HWRM command.
25465 uint16_t cmpl_ring;
25467 * The sequence ID is used by the driver for tracking multiple
25468 * commands. This ID is treated as opaque data by the firmware and
25469 * the value is returned in the `hwrm_resp_hdr` upon completion.
25473 * The target ID of the command:
25474 * * 0x0-0xFFF8 - The function ID
25475 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
25476 * * 0xFFFD - Reserved for user-space HWRM interface
25479 uint16_t target_id;
25481 * A physical address pointer pointing to a host buffer that the
25482 * command's response data will be written. This can be either a host
25483 * physical address (HPA) or a guest physical address (GPA) and must
25484 * point to a physically contiguous block of memory.
25486 uint64_t resp_addr;
25489 * When this bit is '1', this VNIC is requested to
25490 * be the default VNIC for this function.
25492 #define HWRM_VNIC_ALLOC_INPUT_FLAGS_DEFAULT UINT32_C(0x1)
25493 uint8_t unused_0[4];
25496 /* hwrm_vnic_alloc_output (size:128b/16B) */
25497 struct hwrm_vnic_alloc_output {
25498 /* The specific error status for the command. */
25499 uint16_t error_code;
25500 /* The HWRM command request type. */
25502 /* The sequence ID from the original command. */
25504 /* The length of the response data in number of bytes. */
25506 /* Logical vnic ID */
25508 uint8_t unused_0[3];
25510 * This field is used in Output records to indicate that the output
25511 * is completely written to RAM. This field should be read as '1'
25512 * to indicate that the output has been completely written.
25513 * When writing a command completion or response to an internal processor,
25514 * the order of writes has to be such that this field is written last.
25519 /******************
25521 ******************/
25524 /* hwrm_vnic_free_input (size:192b/24B) */
25525 struct hwrm_vnic_free_input {
25526 /* The HWRM command request type. */
25529 * The completion ring to send the completion event on. This should
25530 * be the NQ ID returned from the `nq_alloc` HWRM command.
25532 uint16_t cmpl_ring;
25534 * The sequence ID is used by the driver for tracking multiple
25535 * commands. This ID is treated as opaque data by the firmware and
25536 * the value is returned in the `hwrm_resp_hdr` upon completion.
25540 * The target ID of the command:
25541 * * 0x0-0xFFF8 - The function ID
25542 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
25543 * * 0xFFFD - Reserved for user-space HWRM interface
25546 uint16_t target_id;
25548 * A physical address pointer pointing to a host buffer that the
25549 * command's response data will be written. This can be either a host
25550 * physical address (HPA) or a guest physical address (GPA) and must
25551 * point to a physically contiguous block of memory.
25553 uint64_t resp_addr;
25554 /* Logical vnic ID */
25556 uint8_t unused_0[4];
25559 /* hwrm_vnic_free_output (size:128b/16B) */
25560 struct hwrm_vnic_free_output {
25561 /* The specific error status for the command. */
25562 uint16_t error_code;
25563 /* The HWRM command request type. */
25565 /* The sequence ID from the original command. */
25567 /* The length of the response data in number of bytes. */
25569 uint8_t unused_0[7];
25571 * This field is used in Output records to indicate that the output
25572 * is completely written to RAM. This field should be read as '1'
25573 * to indicate that the output has been completely written.
25574 * When writing a command completion or response to an internal processor,
25575 * the order of writes has to be such that this field is written last.
25585 /* hwrm_vnic_cfg_input (size:384b/48B) */
25586 struct hwrm_vnic_cfg_input {
25587 /* The HWRM command request type. */
25590 * The completion ring to send the completion event on. This should
25591 * be the NQ ID returned from the `nq_alloc` HWRM command.
25593 uint16_t cmpl_ring;
25595 * The sequence ID is used by the driver for tracking multiple
25596 * commands. This ID is treated as opaque data by the firmware and
25597 * the value is returned in the `hwrm_resp_hdr` upon completion.
25601 * The target ID of the command:
25602 * * 0x0-0xFFF8 - The function ID
25603 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
25604 * * 0xFFFD - Reserved for user-space HWRM interface
25607 uint16_t target_id;
25609 * A physical address pointer pointing to a host buffer that the
25610 * command's response data will be written. This can be either a host
25611 * physical address (HPA) or a guest physical address (GPA) and must
25612 * point to a physically contiguous block of memory.
25614 uint64_t resp_addr;
25617 * When this bit is '1', the VNIC is requested to
25618 * be the default VNIC for the function.
25620 #define HWRM_VNIC_CFG_INPUT_FLAGS_DEFAULT \
25623 * When this bit is '1', the VNIC is being configured to
25624 * strip VLAN in the RX path.
25625 * If set to '0', then VLAN stripping is disabled on
25628 #define HWRM_VNIC_CFG_INPUT_FLAGS_VLAN_STRIP_MODE \
25631 * When this bit is '1', the VNIC is being configured to
25632 * buffer receive packets in the hardware until the host
25633 * posts new receive buffers.
25634 * If set to '0', then bd_stall is being configured to be
25635 * disabled on this VNIC.
25637 #define HWRM_VNIC_CFG_INPUT_FLAGS_BD_STALL_MODE \
25640 * When this bit is '1', the VNIC is being configured to
25641 * receive both RoCE and non-RoCE traffic.
25642 * If set to '0', then this VNIC is not configured to be
25643 * operating in dual VNIC mode.
25645 #define HWRM_VNIC_CFG_INPUT_FLAGS_ROCE_DUAL_VNIC_MODE \
25648 * When this flag is set to '1', the VNIC is requested to
25649 * be configured to receive only RoCE traffic.
25650 * If this flag is set to '0', then this flag shall be
25651 * ignored by the HWRM.
25652 * If roce_dual_vnic_mode flag is set to '1'
25653 * or roce_mirroring_capable_vnic_mode flag to 1,
25654 * then the HWRM client shall not set this flag to '1'.
25656 #define HWRM_VNIC_CFG_INPUT_FLAGS_ROCE_ONLY_VNIC_MODE \
25659 * When a VNIC uses one destination ring group for certain
25660 * application (e.g. Receive Flow Steering) where
25661 * exact match is used to direct packets to a VNIC with one
25662 * destination ring group only, there is no need to configure
25663 * RSS indirection table for that VNIC as only one destination
25664 * ring group is used.
25666 * This flag is used to enable a mode where
25667 * RSS is enabled in the VNIC using a RSS context
25668 * for computing RSS hash but the RSS indirection table is
25669 * not configured using hwrm_vnic_rss_cfg.
25671 * If this mode is enabled, then the driver should not program
25672 * RSS indirection table for the RSS context that is used for
25673 * computing RSS hash only.
25675 #define HWRM_VNIC_CFG_INPUT_FLAGS_RSS_DFLT_CR_MODE \
25678 * When this bit is '1', the VNIC is being configured to
25679 * receive both RoCE and non-RoCE traffic, but forward only the
25680 * RoCE traffic further. Also, RoCE traffic can be mirrored to
25683 #define HWRM_VNIC_CFG_INPUT_FLAGS_ROCE_MIRRORING_CAPABLE_VNIC_MODE \
25687 * This bit must be '1' for the dflt_ring_grp field to be
25690 #define HWRM_VNIC_CFG_INPUT_ENABLES_DFLT_RING_GRP \
25693 * This bit must be '1' for the rss_rule field to be
25696 #define HWRM_VNIC_CFG_INPUT_ENABLES_RSS_RULE \
25699 * This bit must be '1' for the cos_rule field to be
25702 #define HWRM_VNIC_CFG_INPUT_ENABLES_COS_RULE \
25705 * This bit must be '1' for the lb_rule field to be
25708 #define HWRM_VNIC_CFG_INPUT_ENABLES_LB_RULE \
25711 * This bit must be '1' for the mru field to be
25714 #define HWRM_VNIC_CFG_INPUT_ENABLES_MRU \
25717 * This bit must be '1' for the default_rx_ring_id field to be
25720 #define HWRM_VNIC_CFG_INPUT_ENABLES_DEFAULT_RX_RING_ID \
25723 * This bit must be '1' for the default_cmpl_ring_id field to be
25726 #define HWRM_VNIC_CFG_INPUT_ENABLES_DEFAULT_CMPL_RING_ID \
25728 /* This bit must be '1' for the queue_id field to be configured. */
25729 #define HWRM_VNIC_CFG_INPUT_ENABLES_QUEUE_ID \
25731 /* This bit must be '1' for the rx_csum_v2_mode field to be configured. */
25732 #define HWRM_VNIC_CFG_INPUT_ENABLES_RX_CSUM_V2_MODE \
25734 /* Logical vnic ID */
25737 * Default Completion ring for the VNIC. This ring will
25738 * be chosen if packet does not match any RSS rules and if
25739 * there is no COS rule.
25741 uint16_t dflt_ring_grp;
25743 * RSS ID for RSS rule/table structure. 0xFF... (All Fs) if
25744 * there is no RSS rule.
25748 * RSS ID for COS rule/table structure. 0xFF... (All Fs) if
25749 * there is no COS rule.
25753 * RSS ID for load balancing rule/table structure.
25754 * 0xFF... (All Fs) if there is no LB rule.
25758 * The maximum receive unit of the vnic.
25759 * Each vnic is associated with a function.
25760 * The vnic mru value overwrites the mru setting of the
25761 * associated function.
25762 * The HWRM shall make sure that vnic mru does not exceed
25763 * the mru of the port the function is associated with.
25767 * Default Rx ring for the VNIC. This ring will
25768 * be chosen if packet does not match any RSS rules.
25769 * The aggregation ring associated with the Rx ring is
25770 * implied based on the Rx ring specified when the
25771 * aggregation ring was allocated.
25773 uint16_t default_rx_ring_id;
25775 * Default completion ring for the VNIC. This ring will
25776 * be chosen if packet does not match any RSS rules.
25778 uint16_t default_cmpl_ring_id;
25780 * When specified, only incoming packets classified to the specified CoS
25781 * queue ID will be arriving on this VNIC. Packet priority to CoS mapping
25782 * rules can be specified using HWRM_QUEUE_PRI2COS_CFG. In this mode,
25783 * ntuple filters with VNIC destination specified are invalid since they
25784 * conflict with the the CoS to VNIC steering rules in this mode.
25786 * If this field is not specified, packet to VNIC steering will be
25787 * subject to the standard L2 filter rules and any additional ntuple
25788 * filter rules with destination VNIC specified.
25792 * If the device supports the RX V2 and RX TPA start V2 completion
25793 * records as indicated by the HWRM_VNIC_QCAPS command, this field is
25794 * used to specify the two RX checksum modes supported by these
25795 * completion records.
25797 uint8_t rx_csum_v2_mode;
25799 * When configured with this checksum mode, the number of header
25800 * groups in the delivered packet with a valid IP checksum and
25801 * the number of header groups in the delivered packet with a valid
25802 * L4 checksum are reported. Valid checksums are counted from the
25803 * outermost header group to the innermost header group, stopping at
25804 * the first error. This is the default checksum mode supported if
25805 * the driver doesn't explicitly configure the RX checksum mode.
25807 #define HWRM_VNIC_CFG_INPUT_RX_CSUM_V2_MODE_DEFAULT UINT32_C(0x0)
25809 * When configured with this checksum mode, the checksum status is
25810 * reported using 'all ok' mode. In the RX completion record, one
25811 * bit indicates if the IP checksum is valid for all the parsed
25812 * header groups with an IP checksum. Another bit indicates if the
25813 * L4 checksum is valid for all the parsed header groups with an L4
25814 * checksum. The number of header groups that were parsed by the
25815 * chip and passed in the delivered packet is also reported.
25817 #define HWRM_VNIC_CFG_INPUT_RX_CSUM_V2_MODE_ALL_OK UINT32_C(0x1)
25819 * Any rx_csum_v2_mode value larger than or equal to this is not
25822 #define HWRM_VNIC_CFG_INPUT_RX_CSUM_V2_MODE_MAX UINT32_C(0x2)
25823 #define HWRM_VNIC_CFG_INPUT_RX_CSUM_V2_MODE_LAST \
25824 HWRM_VNIC_CFG_INPUT_RX_CSUM_V2_MODE_MAX
25825 uint8_t unused0[5];
25828 /* hwrm_vnic_cfg_output (size:128b/16B) */
25829 struct hwrm_vnic_cfg_output {
25830 /* The specific error status for the command. */
25831 uint16_t error_code;
25832 /* The HWRM command request type. */
25834 /* The sequence ID from the original command. */
25836 /* The length of the response data in number of bytes. */
25838 uint8_t unused_0[7];
25840 * This field is used in Output records to indicate that the output
25841 * is completely written to RAM. This field should be read as '1'
25842 * to indicate that the output has been completely written.
25843 * When writing a command completion or response to an internal processor,
25844 * the order of writes has to be such that this field is written last.
25849 /******************
25851 ******************/
25854 /* hwrm_vnic_qcfg_input (size:256b/32B) */
25855 struct hwrm_vnic_qcfg_input {
25856 /* The HWRM command request type. */
25859 * The completion ring to send the completion event on. This should
25860 * be the NQ ID returned from the `nq_alloc` HWRM command.
25862 uint16_t cmpl_ring;
25864 * The sequence ID is used by the driver for tracking multiple
25865 * commands. This ID is treated as opaque data by the firmware and
25866 * the value is returned in the `hwrm_resp_hdr` upon completion.
25870 * The target ID of the command:
25871 * * 0x0-0xFFF8 - The function ID
25872 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
25873 * * 0xFFFD - Reserved for user-space HWRM interface
25876 uint16_t target_id;
25878 * A physical address pointer pointing to a host buffer that the
25879 * command's response data will be written. This can be either a host
25880 * physical address (HPA) or a guest physical address (GPA) and must
25881 * point to a physically contiguous block of memory.
25883 uint64_t resp_addr;
25886 * This bit must be '1' for the vf_id_valid field to be
25889 #define HWRM_VNIC_QCFG_INPUT_ENABLES_VF_ID_VALID UINT32_C(0x1)
25890 /* Logical vnic ID */
25892 /* ID of Virtual Function whose VNIC resource is being queried. */
25894 uint8_t unused_0[6];
25897 /* hwrm_vnic_qcfg_output (size:256b/32B) */
25898 struct hwrm_vnic_qcfg_output {
25899 /* The specific error status for the command. */
25900 uint16_t error_code;
25901 /* The HWRM command request type. */
25903 /* The sequence ID from the original command. */
25905 /* The length of the response data in number of bytes. */
25907 /* Default Completion ring for the VNIC. */
25908 uint16_t dflt_ring_grp;
25910 * RSS ID for RSS rule/table structure. 0xFF... (All Fs) if
25911 * there is no RSS rule.
25915 * RSS ID for COS rule/table structure. 0xFF... (All Fs) if
25916 * there is no COS rule.
25920 * RSS ID for load balancing rule/table structure.
25921 * 0xFF... (All Fs) if there is no LB rule.
25924 /* The maximum receive unit of the vnic. */
25926 uint8_t unused_0[2];
25929 * When this bit is '1', the VNIC is the default VNIC for
25932 #define HWRM_VNIC_QCFG_OUTPUT_FLAGS_DEFAULT \
25935 * When this bit is '1', the VNIC is configured to
25936 * strip VLAN in the RX path.
25937 * If set to '0', then VLAN stripping is disabled on
25940 #define HWRM_VNIC_QCFG_OUTPUT_FLAGS_VLAN_STRIP_MODE \
25943 * When this bit is '1', the VNIC is configured to
25944 * buffer receive packets in the hardware until the host
25945 * posts new receive buffers.
25946 * If set to '0', then bd_stall is disabled on
25949 #define HWRM_VNIC_QCFG_OUTPUT_FLAGS_BD_STALL_MODE \
25952 * When this bit is '1', the VNIC is configured to
25953 * receive both RoCE and non-RoCE traffic.
25954 * If set to '0', then this VNIC is not configured to
25955 * operate in dual VNIC mode.
25957 #define HWRM_VNIC_QCFG_OUTPUT_FLAGS_ROCE_DUAL_VNIC_MODE \
25960 * When this flag is set to '1', the VNIC is configured to
25961 * receive only RoCE traffic.
25962 * When this flag is set to '0', the VNIC is not configured
25963 * to receive only RoCE traffic.
25964 * If roce_dual_vnic_mode flag and this flag both are set
25965 * to '1', then it is an invalid configuration of the
25966 * VNIC. The HWRM should not allow that type of
25967 * mis-configuration by HWRM clients.
25969 #define HWRM_VNIC_QCFG_OUTPUT_FLAGS_ROCE_ONLY_VNIC_MODE \
25972 * When a VNIC uses one destination ring group for certain
25973 * application (e.g. Receive Flow Steering) where
25974 * exact match is used to direct packets to a VNIC with one
25975 * destination ring group only, there is no need to configure
25976 * RSS indirection table for that VNIC as only one destination
25977 * ring group is used.
25979 * When this bit is set to '1', then the VNIC is enabled in a
25980 * mode where RSS is enabled in the VNIC using a RSS context
25981 * for computing RSS hash but the RSS indirection table is
25984 #define HWRM_VNIC_QCFG_OUTPUT_FLAGS_RSS_DFLT_CR_MODE \
25987 * When this bit is '1', the VNIC is configured to
25988 * receive both RoCE and non-RoCE traffic, but forward only
25989 * RoCE traffic further. Also RoCE traffic can be mirrored to
25992 #define HWRM_VNIC_QCFG_OUTPUT_FLAGS_ROCE_MIRRORING_CAPABLE_VNIC_MODE \
25995 * When returned with a valid CoS Queue id, the CoS Queue/VNIC association
25996 * is valid. Otherwise it will return 0xFFFF to indicate no VNIC/CoS
25997 * queue association.
26001 * If the device supports the RX V2 and RX TPA start V2 completion
26002 * records as indicated by the HWRM_VNIC_QCAPS command, this field is
26003 * used to specify the current RX checksum mode configured for all the
26004 * RX rings of a VNIC.
26006 uint8_t rx_csum_v2_mode;
26008 * This value indicates that the VNIC is configured to use the
26009 * default RX checksum mode for all the rings associated with this
26012 #define HWRM_VNIC_QCFG_OUTPUT_RX_CSUM_V2_MODE_DEFAULT UINT32_C(0x0)
26014 * This value indicates that the VNIC is configured to use the RX
26015 * checksum ‘all_ok’ mode for all the rings associated with this
26018 #define HWRM_VNIC_QCFG_OUTPUT_RX_CSUM_V2_MODE_ALL_OK UINT32_C(0x1)
26020 * Any rx_csum_v2_mode value larger than or equal to this is not
26023 #define HWRM_VNIC_QCFG_OUTPUT_RX_CSUM_V2_MODE_MAX UINT32_C(0x2)
26024 #define HWRM_VNIC_QCFG_OUTPUT_RX_CSUM_V2_MODE_LAST \
26025 HWRM_VNIC_QCFG_OUTPUT_RX_CSUM_V2_MODE_MAX
26026 uint8_t unused_1[4];
26028 * This field is used in Output records to indicate that the output
26029 * is completely written to RAM. This field should be read as '1'
26030 * to indicate that the output has been completely written.
26031 * When writing a command completion or response to an internal processor,
26032 * the order of writes has to be such that this field is written last.
26037 /*******************
26038 * hwrm_vnic_qcaps *
26039 *******************/
26042 /* hwrm_vnic_qcaps_input (size:192b/24B) */
26043 struct hwrm_vnic_qcaps_input {
26044 /* The HWRM command request type. */
26047 * The completion ring to send the completion event on. This should
26048 * be the NQ ID returned from the `nq_alloc` HWRM command.
26050 uint16_t cmpl_ring;
26052 * The sequence ID is used by the driver for tracking multiple
26053 * commands. This ID is treated as opaque data by the firmware and
26054 * the value is returned in the `hwrm_resp_hdr` upon completion.
26058 * The target ID of the command:
26059 * * 0x0-0xFFF8 - The function ID
26060 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
26061 * * 0xFFFD - Reserved for user-space HWRM interface
26064 uint16_t target_id;
26066 * A physical address pointer pointing to a host buffer that the
26067 * command's response data will be written. This can be either a host
26068 * physical address (HPA) or a guest physical address (GPA) and must
26069 * point to a physically contiguous block of memory.
26071 uint64_t resp_addr;
26073 uint8_t unused_0[4];
26076 /* hwrm_vnic_qcaps_output (size:192b/24B) */
26077 struct hwrm_vnic_qcaps_output {
26078 /* The specific error status for the command. */
26079 uint16_t error_code;
26080 /* The HWRM command request type. */
26082 /* The sequence ID from the original command. */
26084 /* The length of the response data in number of bytes. */
26086 /* The maximum receive unit that is settable on a vnic. */
26088 uint8_t unused_0[2];
26091 #define HWRM_VNIC_QCAPS_OUTPUT_FLAGS_UNUSED \
26094 * When this bit is '1', the capability of stripping VLAN in
26095 * the RX path is supported on VNIC(s).
26096 * If set to '0', then VLAN stripping capability is
26097 * not supported on VNIC(s).
26099 #define HWRM_VNIC_QCAPS_OUTPUT_FLAGS_VLAN_STRIP_CAP \
26102 * When this bit is '1', the capability to buffer receive
26103 * packets in the hardware until the host posts new receive buffers
26104 * is supported on VNIC(s).
26105 * If set to '0', then bd_stall capability is not supported
26108 #define HWRM_VNIC_QCAPS_OUTPUT_FLAGS_BD_STALL_CAP \
26111 * When this bit is '1', the capability to
26112 * receive both RoCE and non-RoCE traffic on VNIC(s) is
26114 * If set to '0', then the capability to receive
26115 * both RoCE and non-RoCE traffic on VNIC(s) is
26118 #define HWRM_VNIC_QCAPS_OUTPUT_FLAGS_ROCE_DUAL_VNIC_CAP \
26121 * When this bit is set to '1', the capability to configure
26122 * a VNIC to receive only RoCE traffic is supported.
26123 * When this flag is set to '0', the VNIC capability to
26124 * configure to receive only RoCE traffic is not supported.
26126 #define HWRM_VNIC_QCAPS_OUTPUT_FLAGS_ROCE_ONLY_VNIC_CAP \
26129 * When this bit is set to '1', then the capability to enable
26130 * a VNIC in a mode where RSS context without configuring
26131 * RSS indirection table is supported (for RSS hash computation).
26132 * When this bit is set to '0', then a VNIC can not be configured
26133 * with a mode to enable RSS context without configuring RSS
26134 * indirection table.
26136 #define HWRM_VNIC_QCAPS_OUTPUT_FLAGS_RSS_DFLT_CR_CAP \
26139 * When this bit is '1', the capability to
26140 * mirror the the RoCE traffic is supported.
26141 * If set to '0', then the capability to mirror the
26142 * RoCE traffic is not supported.
26144 #define HWRM_VNIC_QCAPS_OUTPUT_FLAGS_ROCE_MIRRORING_CAPABLE_VNIC_CAP \
26147 * When this bit is '1', the outermost RSS hashing capability
26148 * is supported. If set to '0', then the outermost RSS hashing
26149 * capability is not supported.
26151 #define HWRM_VNIC_QCAPS_OUTPUT_FLAGS_OUTERMOST_RSS_CAP \
26154 * When this bit is '1', it indicates that firmware supports the
26155 * ability to steer incoming packets from one CoS queue to one
26156 * VNIC. This optional feature can then be enabled
26157 * using HWRM_VNIC_CFG on any VNIC. This feature is only
26158 * available when NVM option “enable_cos_classfication” is set
26159 * to 1. If set to '0', firmware does not support this feature.
26161 #define HWRM_VNIC_QCAPS_OUTPUT_FLAGS_COS_ASSIGNMENT_CAP \
26164 * When this bit is '1', it indicates that HW and firmware supports
26165 * the use of RX V2 and RX TPA start V2 completion records for all
26166 * the RX rings of a VNIC. Once set, this feature is mandatory to
26167 * be used for the RX rings of the VNIC. Additionally, two new RX
26168 * checksum features supported by these ompletion records can be
26169 * configured using the HWRM_VNIC_CFG on a VNIC. If set to '0', the
26170 * HW and the firmware does not support this feature.
26172 #define HWRM_VNIC_QCAPS_OUTPUT_FLAGS_RX_CMPL_V2_CAP \
26175 * This field advertises the maximum concurrent TPA aggregations
26176 * supported by the VNIC on new devices that support TPA v2.
26177 * '0' means that TPA v2 is not supported.
26179 uint16_t max_aggs_supported;
26180 uint8_t unused_1[5];
26182 * This field is used in Output records to indicate that the output
26183 * is completely written to RAM. This field should be read as '1'
26184 * to indicate that the output has been completely written.
26185 * When writing a command completion or response to an internal processor,
26186 * the order of writes has to be such that this field is written last.
26191 /*********************
26192 * hwrm_vnic_tpa_cfg *
26193 *********************/
26196 /* hwrm_vnic_tpa_cfg_input (size:320b/40B) */
26197 struct hwrm_vnic_tpa_cfg_input {
26198 /* The HWRM command request type. */
26201 * The completion ring to send the completion event on. This should
26202 * be the NQ ID returned from the `nq_alloc` HWRM command.
26204 uint16_t cmpl_ring;
26206 * The sequence ID is used by the driver for tracking multiple
26207 * commands. This ID is treated as opaque data by the firmware and
26208 * the value is returned in the `hwrm_resp_hdr` upon completion.
26212 * The target ID of the command:
26213 * * 0x0-0xFFF8 - The function ID
26214 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
26215 * * 0xFFFD - Reserved for user-space HWRM interface
26218 uint16_t target_id;
26220 * A physical address pointer pointing to a host buffer that the
26221 * command's response data will be written. This can be either a host
26222 * physical address (HPA) or a guest physical address (GPA) and must
26223 * point to a physically contiguous block of memory.
26225 uint64_t resp_addr;
26228 * When this bit is '1', the VNIC shall be configured to
26229 * perform transparent packet aggregation (TPA) of
26230 * non-tunneled TCP packets.
26232 #define HWRM_VNIC_TPA_CFG_INPUT_FLAGS_TPA \
26235 * When this bit is '1', the VNIC shall be configured to
26236 * perform transparent packet aggregation (TPA) of
26237 * tunneled TCP packets.
26239 #define HWRM_VNIC_TPA_CFG_INPUT_FLAGS_ENCAP_TPA \
26242 * When this bit is '1', the VNIC shall be configured to
26243 * perform transparent packet aggregation (TPA) according
26244 * to Windows Receive Segment Coalescing (RSC) rules.
26246 #define HWRM_VNIC_TPA_CFG_INPUT_FLAGS_RSC_WND_UPDATE \
26249 * When this bit is '1', the VNIC shall be configured to
26250 * perform transparent packet aggregation (TPA) according
26251 * to Linux Generic Receive Offload (GRO) rules.
26253 #define HWRM_VNIC_TPA_CFG_INPUT_FLAGS_GRO \
26256 * When this bit is '1', the VNIC shall be configured to
26257 * perform transparent packet aggregation (TPA) for TCP
26258 * packets with IP ECN set to non-zero.
26260 #define HWRM_VNIC_TPA_CFG_INPUT_FLAGS_AGG_WITH_ECN \
26263 * When this bit is '1', the VNIC shall be configured to
26264 * perform transparent packet aggregation (TPA) for
26265 * GRE tunneled TCP packets only if all packets have the
26266 * same GRE sequence.
26268 #define HWRM_VNIC_TPA_CFG_INPUT_FLAGS_AGG_WITH_SAME_GRE_SEQ \
26271 * When this bit is '1' and the GRO mode is enabled,
26272 * the VNIC shall be configured to
26273 * perform transparent packet aggregation (TPA) for
26274 * TCP/IPv4 packets with consecutively increasing IPIDs.
26275 * In other words, the last packet that is being
26276 * aggregated to an already existing aggregation context
26277 * shall have IPID 1 more than the IPID of the last packet
26278 * that was aggregated in that aggregation context.
26280 #define HWRM_VNIC_TPA_CFG_INPUT_FLAGS_GRO_IPID_CHECK \
26283 * When this bit is '1' and the GRO mode is enabled,
26284 * the VNIC shall be configured to
26285 * perform transparent packet aggregation (TPA) for
26286 * TCP packets with the same TTL (IPv4) or Hop limit (IPv6)
26289 #define HWRM_VNIC_TPA_CFG_INPUT_FLAGS_GRO_TTL_CHECK \
26292 * When this bit is '1' and the GRO mode is enabled,
26293 * the VNIC shall DMA payload data using GRO rules.
26294 * When this bit is '0', the VNIC shall DMA payload data
26295 * using the more efficient LRO rules of filling all
26296 * aggregation buffers.
26298 #define HWRM_VNIC_TPA_CFG_INPUT_FLAGS_AGG_PACK_AS_GRO \
26302 * This bit must be '1' for the max_agg_segs field to be
26305 #define HWRM_VNIC_TPA_CFG_INPUT_ENABLES_MAX_AGG_SEGS UINT32_C(0x1)
26307 * This bit must be '1' for the max_aggs field to be
26310 #define HWRM_VNIC_TPA_CFG_INPUT_ENABLES_MAX_AGGS UINT32_C(0x2)
26312 * This bit must be '1' for the max_agg_timer field to be
26315 #define HWRM_VNIC_TPA_CFG_INPUT_ENABLES_MAX_AGG_TIMER UINT32_C(0x4)
26316 /* deprecated bit. Do not use!!! */
26317 #define HWRM_VNIC_TPA_CFG_INPUT_ENABLES_MIN_AGG_LEN UINT32_C(0x8)
26318 /* Logical vnic ID */
26321 * This is the maximum number of TCP segments that can
26322 * be aggregated (unit is Log2). Max value is 31. On new
26323 * devices supporting TPA v2, the unit is multiples of 4 and
26324 * valid values are > 0 and <= 63.
26326 uint16_t max_agg_segs;
26328 #define HWRM_VNIC_TPA_CFG_INPUT_MAX_AGG_SEGS_1 UINT32_C(0x0)
26330 #define HWRM_VNIC_TPA_CFG_INPUT_MAX_AGG_SEGS_2 UINT32_C(0x1)
26332 #define HWRM_VNIC_TPA_CFG_INPUT_MAX_AGG_SEGS_4 UINT32_C(0x2)
26334 #define HWRM_VNIC_TPA_CFG_INPUT_MAX_AGG_SEGS_8 UINT32_C(0x3)
26335 /* Any segment size larger than this is not valid */
26336 #define HWRM_VNIC_TPA_CFG_INPUT_MAX_AGG_SEGS_MAX UINT32_C(0x1f)
26337 #define HWRM_VNIC_TPA_CFG_INPUT_MAX_AGG_SEGS_LAST \
26338 HWRM_VNIC_TPA_CFG_INPUT_MAX_AGG_SEGS_MAX
26340 * This is the maximum number of aggregations this VNIC is
26341 * allowed (unit is Log2). Max value is 7. On new devices
26342 * supporting TPA v2, this is in unit of 1 and must be > 0
26343 * and <= max_aggs_supported in the hwrm_vnic_qcaps response
26344 * to enable TPA v2.
26347 /* 1 aggregation */
26348 #define HWRM_VNIC_TPA_CFG_INPUT_MAX_AGGS_1 UINT32_C(0x0)
26349 /* 2 aggregations */
26350 #define HWRM_VNIC_TPA_CFG_INPUT_MAX_AGGS_2 UINT32_C(0x1)
26351 /* 4 aggregations */
26352 #define HWRM_VNIC_TPA_CFG_INPUT_MAX_AGGS_4 UINT32_C(0x2)
26353 /* 8 aggregations */
26354 #define HWRM_VNIC_TPA_CFG_INPUT_MAX_AGGS_8 UINT32_C(0x3)
26355 /* 16 aggregations */
26356 #define HWRM_VNIC_TPA_CFG_INPUT_MAX_AGGS_16 UINT32_C(0x4)
26357 /* Any aggregation size larger than this is not valid */
26358 #define HWRM_VNIC_TPA_CFG_INPUT_MAX_AGGS_MAX UINT32_C(0x7)
26359 #define HWRM_VNIC_TPA_CFG_INPUT_MAX_AGGS_LAST \
26360 HWRM_VNIC_TPA_CFG_INPUT_MAX_AGGS_MAX
26361 uint8_t unused_0[2];
26363 * This is the maximum amount of time allowed for
26364 * an aggregation context to complete after it was initiated.
26366 uint32_t max_agg_timer;
26368 * This is the minimum amount of payload length required to
26369 * start an aggregation context. This field is deprecated and
26370 * should be set to 0. The minimum length is set by firmware
26371 * and can be queried using hwrm_vnic_tpa_qcfg.
26373 uint32_t min_agg_len;
26376 /* hwrm_vnic_tpa_cfg_output (size:128b/16B) */
26377 struct hwrm_vnic_tpa_cfg_output {
26378 /* The specific error status for the command. */
26379 uint16_t error_code;
26380 /* The HWRM command request type. */
26382 /* The sequence ID from the original command. */
26384 /* The length of the response data in number of bytes. */
26386 uint8_t unused_0[7];
26388 * This field is used in Output records to indicate that the output
26389 * is completely written to RAM. This field should be read as '1'
26390 * to indicate that the output has been completely written.
26391 * When writing a command completion or response to an internal processor,
26392 * the order of writes has to be such that this field is written last.
26397 /*********************
26398 * hwrm_vnic_rss_cfg *
26399 *********************/
26402 /* hwrm_vnic_rss_cfg_input (size:384b/48B) */
26403 struct hwrm_vnic_rss_cfg_input {
26404 /* The HWRM command request type. */
26407 * The completion ring to send the completion event on. This should
26408 * be the NQ ID returned from the `nq_alloc` HWRM command.
26410 uint16_t cmpl_ring;
26412 * The sequence ID is used by the driver for tracking multiple
26413 * commands. This ID is treated as opaque data by the firmware and
26414 * the value is returned in the `hwrm_resp_hdr` upon completion.
26418 * The target ID of the command:
26419 * * 0x0-0xFFF8 - The function ID
26420 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
26421 * * 0xFFFD - Reserved for user-space HWRM interface
26424 uint16_t target_id;
26426 * A physical address pointer pointing to a host buffer that the
26427 * command's response data will be written. This can be either a host
26428 * physical address (HPA) or a guest physical address (GPA) and must
26429 * point to a physically contiguous block of memory.
26431 uint64_t resp_addr;
26432 uint32_t hash_type;
26434 * When this bit is '1', the RSS hash shall be computed
26435 * over source and destination IPv4 addresses of IPv4
26438 #define HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV4 UINT32_C(0x1)
26440 * When this bit is '1', the RSS hash shall be computed
26441 * over source/destination IPv4 addresses and
26442 * source/destination ports of TCP/IPv4 packets.
26444 #define HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV4 UINT32_C(0x2)
26446 * When this bit is '1', the RSS hash shall be computed
26447 * over source/destination IPv4 addresses and
26448 * source/destination ports of UDP/IPv4 packets.
26450 #define HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV4 UINT32_C(0x4)
26452 * When this bit is '1', the RSS hash shall be computed
26453 * over source and destination IPv4 addresses of IPv6
26456 #define HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV6 UINT32_C(0x8)
26458 * When this bit is '1', the RSS hash shall be computed
26459 * over source/destination IPv6 addresses and
26460 * source/destination ports of TCP/IPv6 packets.
26462 #define HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV6 UINT32_C(0x10)
26464 * When this bit is '1', the RSS hash shall be computed
26465 * over source/destination IPv6 addresses and
26466 * source/destination ports of UDP/IPv6 packets.
26468 #define HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV6 UINT32_C(0x20)
26469 /* VNIC ID of VNIC associated with RSS table being configured. */
26472 * Specifies which VNIC ring table pair to configure.
26473 * Valid values range from 0 to 7.
26475 uint8_t ring_table_pair_index;
26476 /* Flags to specify different RSS hash modes. */
26477 uint8_t hash_mode_flags;
26479 * When this bit is '1', it indicates using current RSS
26480 * hash mode setting configured in the device.
26482 #define HWRM_VNIC_RSS_CFG_INPUT_HASH_MODE_FLAGS_DEFAULT \
26485 * When this bit is '1', it indicates requesting support of
26486 * RSS hashing over innermost 4 tuples {l3.src, l3.dest,
26487 * l4.src, l4.dest} for tunnel packets. For none-tunnel
26488 * packets, the RSS hash is computed over the normal
26489 * src/dest l3 and src/dest l4 headers.
26491 #define HWRM_VNIC_RSS_CFG_INPUT_HASH_MODE_FLAGS_INNERMOST_4 \
26494 * When this bit is '1', it indicates requesting support of
26495 * RSS hashing over innermost 2 tuples {l3.src, l3.dest} for
26496 * tunnel packets. For none-tunnel packets, the RSS hash is
26497 * computed over the normal src/dest l3 headers.
26499 #define HWRM_VNIC_RSS_CFG_INPUT_HASH_MODE_FLAGS_INNERMOST_2 \
26502 * When this bit is '1', it indicates requesting support of
26503 * RSS hashing over outermost 4 tuples {t_l3.src, t_l3.dest,
26504 * t_l4.src, t_l4.dest} for tunnel packets. For none-tunnel
26505 * packets, the RSS hash is computed over the normal
26506 * src/dest l3 and src/dest l4 headers.
26508 #define HWRM_VNIC_RSS_CFG_INPUT_HASH_MODE_FLAGS_OUTERMOST_4 \
26511 * When this bit is '1', it indicates requesting support of
26512 * RSS hashing over outermost 2 tuples {t_l3.src, t_l3.dest} for
26513 * tunnel packets. For none-tunnel packets, the RSS hash is
26514 * computed over the normal src/dest l3 headers.
26516 #define HWRM_VNIC_RSS_CFG_INPUT_HASH_MODE_FLAGS_OUTERMOST_2 \
26518 /* This is the address for rss ring group table */
26519 uint64_t ring_grp_tbl_addr;
26520 /* This is the address for rss hash key table */
26521 uint64_t hash_key_tbl_addr;
26522 /* Index to the rss indirection table. */
26523 uint16_t rss_ctx_idx;
26524 uint8_t unused_1[6];
26527 /* hwrm_vnic_rss_cfg_output (size:128b/16B) */
26528 struct hwrm_vnic_rss_cfg_output {
26529 /* The specific error status for the command. */
26530 uint16_t error_code;
26531 /* The HWRM command request type. */
26533 /* The sequence ID from the original command. */
26535 /* The length of the response data in number of bytes. */
26537 uint8_t unused_0[7];
26539 * This field is used in Output records to indicate that the output
26540 * is completely written to RAM. This field should be read as '1'
26541 * to indicate that the output has been completely written.
26542 * When writing a command completion or response to an internal processor,
26543 * the order of writes has to be such that this field is written last.
26548 /* hwrm_vnic_rss_cfg_cmd_err (size:64b/8B) */
26549 struct hwrm_vnic_rss_cfg_cmd_err {
26551 * command specific error codes that goes to
26552 * the cmd_err field in Common HWRM Error Response.
26555 /* Unknown error */
26556 #define HWRM_VNIC_RSS_CFG_CMD_ERR_CODE_UNKNOWN \
26559 * Unable to change global RSS mode to outer due to all active
26560 * interfaces are not ready to support outer RSS hashing.
26562 #define HWRM_VNIC_RSS_CFG_CMD_ERR_CODE_INTERFACE_NOT_READY \
26564 #define HWRM_VNIC_RSS_CFG_CMD_ERR_CODE_LAST \
26565 HWRM_VNIC_RSS_CFG_CMD_ERR_CODE_INTERFACE_NOT_READY
26566 uint8_t unused_0[7];
26569 /**********************
26570 * hwrm_vnic_rss_qcfg *
26571 **********************/
26574 /* hwrm_vnic_rss_qcfg_input (size:192b/24B) */
26575 struct hwrm_vnic_rss_qcfg_input {
26576 /* The HWRM command request type. */
26579 * The completion ring to send the completion event on. This should
26580 * be the NQ ID returned from the `nq_alloc` HWRM command.
26582 uint16_t cmpl_ring;
26584 * The sequence ID is used by the driver for tracking multiple
26585 * commands. This ID is treated as opaque data by the firmware and
26586 * the value is returned in the `hwrm_resp_hdr` upon completion.
26590 * The target ID of the command:
26591 * * 0x0-0xFFF8 - The function ID
26592 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
26593 * * 0xFFFD - Reserved for user-space HWRM interface
26596 uint16_t target_id;
26598 * A physical address pointer pointing to a host buffer that the
26599 * command's response data will be written. This can be either a host
26600 * physical address (HPA) or a guest physical address (GPA) and must
26601 * point to a physically contiguous block of memory.
26603 uint64_t resp_addr;
26604 /* Index to the rss indirection table. */
26605 uint16_t rss_ctx_idx;
26606 uint8_t unused_0[6];
26609 /* hwrm_vnic_rss_qcfg_output (size:512b/64B) */
26610 struct hwrm_vnic_rss_qcfg_output {
26611 /* The specific error status for the command. */
26612 uint16_t error_code;
26613 /* The HWRM command request type. */
26615 /* The sequence ID from the original command. */
26617 /* The length of the response data in number of bytes. */
26619 uint32_t hash_type;
26621 * When this bit is '1', the RSS hash shall be computed
26622 * over source and destination IPv4 addresses of IPv4
26625 #define HWRM_VNIC_RSS_QCFG_OUTPUT_HASH_TYPE_IPV4 UINT32_C(0x1)
26627 * When this bit is '1', the RSS hash shall be computed
26628 * over source/destination IPv4 addresses and
26629 * source/destination ports of TCP/IPv4 packets.
26631 #define HWRM_VNIC_RSS_QCFG_OUTPUT_HASH_TYPE_TCP_IPV4 UINT32_C(0x2)
26633 * When this bit is '1', the RSS hash shall be computed
26634 * over source/destination IPv4 addresses and
26635 * source/destination ports of UDP/IPv4 packets.
26637 #define HWRM_VNIC_RSS_QCFG_OUTPUT_HASH_TYPE_UDP_IPV4 UINT32_C(0x4)
26639 * When this bit is '1', the RSS hash shall be computed
26640 * over source and destination IPv4 addresses of IPv6
26643 #define HWRM_VNIC_RSS_QCFG_OUTPUT_HASH_TYPE_IPV6 UINT32_C(0x8)
26645 * When this bit is '1', the RSS hash shall be computed
26646 * over source/destination IPv6 addresses and
26647 * source/destination ports of TCP/IPv6 packets.
26649 #define HWRM_VNIC_RSS_QCFG_OUTPUT_HASH_TYPE_TCP_IPV6 UINT32_C(0x10)
26651 * When this bit is '1', the RSS hash shall be computed
26652 * over source/destination IPv6 addresses and
26653 * source/destination ports of UDP/IPv6 packets.
26655 #define HWRM_VNIC_RSS_QCFG_OUTPUT_HASH_TYPE_UDP_IPV6 UINT32_C(0x20)
26656 uint8_t unused_0[4];
26657 /* This is the value of rss hash key */
26658 uint32_t hash_key[10];
26659 /* Flags to specify different RSS hash modes. */
26660 uint8_t hash_mode_flags;
26662 * When this bit is '1', it indicates using current RSS
26663 * hash mode setting configured in the device.
26665 #define HWRM_VNIC_RSS_QCFG_OUTPUT_HASH_MODE_FLAGS_DEFAULT \
26668 * When this bit is '1', it indicates requesting support of
26669 * RSS hashing over innermost 4 tuples {l3.src, l3.dest,
26670 * l4.src, l4.dest} for tunnel packets. For none-tunnel
26671 * packets, the RSS hash is computed over the normal
26672 * src/dest l3 and src/dest l4 headers.
26674 #define HWRM_VNIC_RSS_QCFG_OUTPUT_HASH_MODE_FLAGS_INNERMOST_4 \
26677 * When this bit is '1', it indicates requesting support of
26678 * RSS hashing over innermost 2 tuples {l3.src, l3.dest} for
26679 * tunnel packets. For none-tunnel packets, the RSS hash is
26680 * computed over the normal src/dest l3 headers.
26682 #define HWRM_VNIC_RSS_QCFG_OUTPUT_HASH_MODE_FLAGS_INNERMOST_2 \
26685 * When this bit is '1', it indicates requesting support of
26686 * RSS hashing over outermost 4 tuples {t_l3.src, t_l3.dest,
26687 * t_l4.src, t_l4.dest} for tunnel packets. For none-tunnel
26688 * packets, the RSS hash is computed over the normal
26689 * src/dest l3 and src/dest l4 headers.
26691 #define HWRM_VNIC_RSS_QCFG_OUTPUT_HASH_MODE_FLAGS_OUTERMOST_4 \
26694 * When this bit is '1', it indicates requesting support of
26695 * RSS hashing over outermost 2 tuples {t_l3.src, t_l3.dest} for
26696 * tunnel packets. For none-tunnel packets, the RSS hash is
26697 * computed over the normal src/dest l3 headers.
26699 #define HWRM_VNIC_RSS_QCFG_OUTPUT_HASH_MODE_FLAGS_OUTERMOST_2 \
26701 uint8_t unused_1[6];
26703 * This field is used in Output records to indicate that the output
26704 * is completely written to RAM. This field should be read as '1'
26705 * to indicate that the output has been completely written.
26706 * When writing a command completion or response to an internal processor,
26707 * the order of writes has to be such that this field is written last.
26712 /**************************
26713 * hwrm_vnic_plcmodes_cfg *
26714 **************************/
26717 /* hwrm_vnic_plcmodes_cfg_input (size:320b/40B) */
26718 struct hwrm_vnic_plcmodes_cfg_input {
26719 /* The HWRM command request type. */
26722 * The completion ring to send the completion event on. This should
26723 * be the NQ ID returned from the `nq_alloc` HWRM command.
26725 uint16_t cmpl_ring;
26727 * The sequence ID is used by the driver for tracking multiple
26728 * commands. This ID is treated as opaque data by the firmware and
26729 * the value is returned in the `hwrm_resp_hdr` upon completion.
26733 * The target ID of the command:
26734 * * 0x0-0xFFF8 - The function ID
26735 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
26736 * * 0xFFFD - Reserved for user-space HWRM interface
26739 uint16_t target_id;
26741 * A physical address pointer pointing to a host buffer that the
26742 * command's response data will be written. This can be either a host
26743 * physical address (HPA) or a guest physical address (GPA) and must
26744 * point to a physically contiguous block of memory.
26746 uint64_t resp_addr;
26749 * When this bit is '1', the VNIC shall be configured to
26750 * use regular placement algorithm.
26751 * By default, the regular placement algorithm shall be
26752 * enabled on the VNIC.
26754 #define HWRM_VNIC_PLCMODES_CFG_INPUT_FLAGS_REGULAR_PLACEMENT \
26757 * When this bit is '1', the VNIC shall be configured
26758 * use the jumbo placement algorithm.
26760 #define HWRM_VNIC_PLCMODES_CFG_INPUT_FLAGS_JUMBO_PLACEMENT \
26763 * When this bit is '1', the VNIC shall be configured
26764 * to enable Header-Data split for IPv4 packets according
26765 * to the following rules:
26766 * # If the packet is identified as TCP/IPv4, then the
26767 * packet is split at the beginning of the TCP payload.
26768 * # If the packet is identified as UDP/IPv4, then the
26769 * packet is split at the beginning of UDP payload.
26770 * # If the packet is identified as non-TCP and non-UDP
26771 * IPv4 packet, then the packet is split at the beginning
26772 * of the upper layer protocol header carried in the IPv4
26775 #define HWRM_VNIC_PLCMODES_CFG_INPUT_FLAGS_HDS_IPV4 \
26778 * When this bit is '1', the VNIC shall be configured
26779 * to enable Header-Data split for IPv6 packets according
26780 * to the following rules:
26781 * # If the packet is identified as TCP/IPv6, then the
26782 * packet is split at the beginning of the TCP payload.
26783 * # If the packet is identified as UDP/IPv6, then the
26784 * packet is split at the beginning of UDP payload.
26785 * # If the packet is identified as non-TCP and non-UDP
26786 * IPv6 packet, then the packet is split at the beginning
26787 * of the upper layer protocol header carried in the IPv6
26790 #define HWRM_VNIC_PLCMODES_CFG_INPUT_FLAGS_HDS_IPV6 \
26793 * When this bit is '1', the VNIC shall be configured
26794 * to enable Header-Data split for FCoE packets at the
26795 * beginning of FC payload.
26797 #define HWRM_VNIC_PLCMODES_CFG_INPUT_FLAGS_HDS_FCOE \
26800 * When this bit is '1', the VNIC shall be configured
26801 * to enable Header-Data split for RoCE packets at the
26802 * beginning of RoCE payload (after BTH/GRH headers).
26804 #define HWRM_VNIC_PLCMODES_CFG_INPUT_FLAGS_HDS_ROCE \
26807 * When this bit is '1', the VNIC shall be configured use the virtio
26808 * placement algorithm. This feature can only be configured when
26809 * proxy mode is supported on the function.
26811 #define HWRM_VNIC_PLCMODES_CFG_INPUT_FLAGS_VIRTIO_PLACEMENT \
26815 * This bit must be '1' for the jumbo_thresh_valid field to be
26818 #define HWRM_VNIC_PLCMODES_CFG_INPUT_ENABLES_JUMBO_THRESH_VALID \
26821 * This bit must be '1' for the hds_offset_valid field to be
26824 #define HWRM_VNIC_PLCMODES_CFG_INPUT_ENABLES_HDS_OFFSET_VALID \
26827 * This bit must be '1' for the hds_threshold_valid field to be
26830 #define HWRM_VNIC_PLCMODES_CFG_INPUT_ENABLES_HDS_THRESHOLD_VALID \
26833 * This bit must be '1' for the max_bds_valid field to be
26836 #define HWRM_VNIC_PLCMODES_CFG_INPUT_ENABLES_MAX_BDS_VALID \
26838 /* Logical vnic ID */
26841 * When jumbo placement algorithm is enabled, this value
26842 * is used to determine the threshold for jumbo placement.
26843 * Packets with length larger than this value will be
26844 * placed according to the jumbo placement algorithm.
26846 uint16_t jumbo_thresh;
26848 * This value is used to determine the offset into
26849 * packet buffer where the split data (payload) will be
26850 * placed according to one of HDS placement algorithm.
26852 * The lengths of packet buffers provided for split data
26853 * shall be larger than this value.
26855 uint16_t hds_offset;
26857 * When one of the HDS placement algorithm is enabled, this
26858 * value is used to determine the threshold for HDS
26860 * Packets with length larger than this value will be
26861 * placed according to the HDS placement algorithm.
26862 * This value shall be in multiple of 4 bytes.
26864 uint16_t hds_threshold;
26866 * When virtio placement algorithm is enabled, this
26867 * value is used to determine the the maximum number of BDs
26868 * that can be used to place an Rx Packet.
26869 * If an incoming packet does not fit in the buffers described
26870 * by the max BDs, the packet will be dropped and an error
26871 * will be reported in the completion. Valid values for this
26872 * field are between 1 and 8. If the VNIC uses header-data-
26873 * separation and/or TPA with buffer spanning enabled, valid
26874 * values for this field are between 2 and 8.
26875 * This feature can only be configured when proxy mode is
26876 * supported on the function.
26879 uint8_t unused_0[4];
26882 /* hwrm_vnic_plcmodes_cfg_output (size:128b/16B) */
26883 struct hwrm_vnic_plcmodes_cfg_output {
26884 /* The specific error status for the command. */
26885 uint16_t error_code;
26886 /* The HWRM command request type. */
26888 /* The sequence ID from the original command. */
26890 /* The length of the response data in number of bytes. */
26892 uint8_t unused_0[7];
26894 * This field is used in Output records to indicate that the output
26895 * is completely written to RAM. This field should be read as '1'
26896 * to indicate that the output has been completely written.
26897 * When writing a command completion or response to an internal
26898 * processor, the order of writes has to be such that this field is
26904 /***************************
26905 * hwrm_vnic_plcmodes_qcfg *
26906 ***************************/
26909 /* hwrm_vnic_plcmodes_qcfg_input (size:192b/24B) */
26910 struct hwrm_vnic_plcmodes_qcfg_input {
26911 /* The HWRM command request type. */
26914 * The completion ring to send the completion event on. This should
26915 * be the NQ ID returned from the `nq_alloc` HWRM command.
26917 uint16_t cmpl_ring;
26919 * The sequence ID is used by the driver for tracking multiple
26920 * commands. This ID is treated as opaque data by the firmware and
26921 * the value is returned in the `hwrm_resp_hdr` upon completion.
26925 * The target ID of the command:
26926 * * 0x0-0xFFF8 - The function ID
26927 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
26928 * * 0xFFFD - Reserved for user-space HWRM interface
26931 uint16_t target_id;
26933 * A physical address pointer pointing to a host buffer that the
26934 * command's response data will be written. This can be either a host
26935 * physical address (HPA) or a guest physical address (GPA) and must
26936 * point to a physically contiguous block of memory.
26938 uint64_t resp_addr;
26939 /* Logical vnic ID */
26941 uint8_t unused_0[4];
26944 /* hwrm_vnic_plcmodes_qcfg_output (size:192b/24B) */
26945 struct hwrm_vnic_plcmodes_qcfg_output {
26946 /* The specific error status for the command. */
26947 uint16_t error_code;
26948 /* The HWRM command request type. */
26950 /* The sequence ID from the original command. */
26952 /* The length of the response data in number of bytes. */
26956 * When this bit is '1', the VNIC is configured to
26957 * use regular placement algorithm.
26959 #define HWRM_VNIC_PLCMODES_QCFG_OUTPUT_FLAGS_REGULAR_PLACEMENT \
26962 * When this bit is '1', the VNIC is configured to
26963 * use the jumbo placement algorithm.
26965 #define HWRM_VNIC_PLCMODES_QCFG_OUTPUT_FLAGS_JUMBO_PLACEMENT \
26968 * When this bit is '1', the VNIC is configured
26969 * to enable Header-Data split for IPv4 packets.
26971 #define HWRM_VNIC_PLCMODES_QCFG_OUTPUT_FLAGS_HDS_IPV4 \
26974 * When this bit is '1', the VNIC is configured
26975 * to enable Header-Data split for IPv6 packets.
26977 #define HWRM_VNIC_PLCMODES_QCFG_OUTPUT_FLAGS_HDS_IPV6 \
26980 * When this bit is '1', the VNIC is configured
26981 * to enable Header-Data split for FCoE packets.
26983 #define HWRM_VNIC_PLCMODES_QCFG_OUTPUT_FLAGS_HDS_FCOE \
26986 * When this bit is '1', the VNIC is configured
26987 * to enable Header-Data split for RoCE packets.
26989 #define HWRM_VNIC_PLCMODES_QCFG_OUTPUT_FLAGS_HDS_ROCE \
26992 * When this bit is '1', the VNIC is configured
26993 * to be the default VNIC of the requesting function.
26995 #define HWRM_VNIC_PLCMODES_QCFG_OUTPUT_FLAGS_DFLT_VNIC \
26998 * When this bit is '1', the VNIC is configured to use the virtio
26999 * placement algorithm. This feature can only be configured when
27000 * proxy mode is supported on the function.
27002 #define HWRM_VNIC_PLCMODES_QCFG_OUTPUT_FLAGS_VIRTIO_PLACEMENT \
27005 * When jumbo placement algorithm is enabled, this value
27006 * is used to determine the threshold for jumbo placement.
27007 * Packets with length larger than this value will be
27008 * placed according to the jumbo placement algorithm.
27010 uint16_t jumbo_thresh;
27012 * This value is used to determine the offset into
27013 * packet buffer where the split data (payload) will be
27014 * placed according to one of HDS placement algorithm.
27016 * The lengths of packet buffers provided for split data
27017 * shall be larger than this value.
27019 uint16_t hds_offset;
27021 * When one of the HDS placement algorithm is enabled, this
27022 * value is used to determine the threshold for HDS
27024 * Packets with length larger than this value will be
27025 * placed according to the HDS placement algorithm.
27026 * This value shall be in multiple of 4 bytes.
27028 uint16_t hds_threshold;
27030 * When virtio placement algorithm is enabled, this
27031 * value is used to determine the the maximum number of BDs
27032 * that can be used to place an Rx Packet.
27033 * If an incoming packet does not fit in the buffers described
27034 * by the max BDs, the packet will be dropped and an error
27035 * will be reported in the completion. Valid values for this
27036 * field are between 1 and 8. If the VNIC uses header-data-
27037 * separation and/or TPA with buffer spanning enabled, valid
27038 * values for this field are between 2 and 8.
27039 * This feature can only be configured when proxy mode is supported
27043 uint8_t unused_0[3];
27045 * This field is used in Output records to indicate that the output
27046 * is completely written to RAM. This field should be read as '1'
27047 * to indicate that the output has been completely written.
27048 * When writing a command completion or response to an internal
27049 * processor, the order of writes has to be such that this field is
27055 /**********************************
27056 * hwrm_vnic_rss_cos_lb_ctx_alloc *
27057 **********************************/
27060 /* hwrm_vnic_rss_cos_lb_ctx_alloc_input (size:128b/16B) */
27061 struct hwrm_vnic_rss_cos_lb_ctx_alloc_input {
27062 /* The HWRM command request type. */
27065 * The completion ring to send the completion event on. This should
27066 * be the NQ ID returned from the `nq_alloc` HWRM command.
27068 uint16_t cmpl_ring;
27070 * The sequence ID is used by the driver for tracking multiple
27071 * commands. This ID is treated as opaque data by the firmware and
27072 * the value is returned in the `hwrm_resp_hdr` upon completion.
27076 * The target ID of the command:
27077 * * 0x0-0xFFF8 - The function ID
27078 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
27079 * * 0xFFFD - Reserved for user-space HWRM interface
27082 uint16_t target_id;
27084 * A physical address pointer pointing to a host buffer that the
27085 * command's response data will be written. This can be either a host
27086 * physical address (HPA) or a guest physical address (GPA) and must
27087 * point to a physically contiguous block of memory.
27089 uint64_t resp_addr;
27092 /* hwrm_vnic_rss_cos_lb_ctx_alloc_output (size:128b/16B) */
27093 struct hwrm_vnic_rss_cos_lb_ctx_alloc_output {
27094 /* The specific error status for the command. */
27095 uint16_t error_code;
27096 /* The HWRM command request type. */
27098 /* The sequence ID from the original command. */
27100 /* The length of the response data in number of bytes. */
27102 /* rss_cos_lb_ctx_id is 16 b */
27103 uint16_t rss_cos_lb_ctx_id;
27104 uint8_t unused_0[5];
27106 * This field is used in Output records to indicate that the output
27107 * is completely written to RAM. This field should be read as '1'
27108 * to indicate that the output has been completely written.
27109 * When writing a command completion or response to an internal processor,
27110 * the order of writes has to be such that this field is written last.
27115 /*********************************
27116 * hwrm_vnic_rss_cos_lb_ctx_free *
27117 *********************************/
27120 /* hwrm_vnic_rss_cos_lb_ctx_free_input (size:192b/24B) */
27121 struct hwrm_vnic_rss_cos_lb_ctx_free_input {
27122 /* The HWRM command request type. */
27125 * The completion ring to send the completion event on. This should
27126 * be the NQ ID returned from the `nq_alloc` HWRM command.
27128 uint16_t cmpl_ring;
27130 * The sequence ID is used by the driver for tracking multiple
27131 * commands. This ID is treated as opaque data by the firmware and
27132 * the value is returned in the `hwrm_resp_hdr` upon completion.
27136 * The target ID of the command:
27137 * * 0x0-0xFFF8 - The function ID
27138 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
27139 * * 0xFFFD - Reserved for user-space HWRM interface
27142 uint16_t target_id;
27144 * A physical address pointer pointing to a host buffer that the
27145 * command's response data will be written. This can be either a host
27146 * physical address (HPA) or a guest physical address (GPA) and must
27147 * point to a physically contiguous block of memory.
27149 uint64_t resp_addr;
27150 /* rss_cos_lb_ctx_id is 16 b */
27151 uint16_t rss_cos_lb_ctx_id;
27152 uint8_t unused_0[6];
27155 /* hwrm_vnic_rss_cos_lb_ctx_free_output (size:128b/16B) */
27156 struct hwrm_vnic_rss_cos_lb_ctx_free_output {
27157 /* The specific error status for the command. */
27158 uint16_t error_code;
27159 /* The HWRM command request type. */
27161 /* The sequence ID from the original command. */
27163 /* The length of the response data in number of bytes. */
27165 uint8_t unused_0[7];
27167 * This field is used in Output records to indicate that the output
27168 * is completely written to RAM. This field should be read as '1'
27169 * to indicate that the output has been completely written.
27170 * When writing a command completion or response to an internal processor,
27171 * the order of writes has to be such that this field is written last.
27176 /*******************
27177 * hwrm_ring_alloc *
27178 *******************/
27181 /* hwrm_ring_alloc_input (size:704b/88B) */
27182 struct hwrm_ring_alloc_input {
27183 /* The HWRM command request type. */
27186 * The completion ring to send the completion event on. This should
27187 * be the NQ ID returned from the `nq_alloc` HWRM command.
27189 uint16_t cmpl_ring;
27191 * The sequence ID is used by the driver for tracking multiple
27192 * commands. This ID is treated as opaque data by the firmware and
27193 * the value is returned in the `hwrm_resp_hdr` upon completion.
27197 * The target ID of the command:
27198 * * 0x0-0xFFF8 - The function ID
27199 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
27200 * * 0xFFFD - Reserved for user-space HWRM interface
27203 uint16_t target_id;
27205 * A physical address pointer pointing to a host buffer that the
27206 * command's response data will be written. This can be either a host
27207 * physical address (HPA) or a guest physical address (GPA) and must
27208 * point to a physically contiguous block of memory.
27210 uint64_t resp_addr;
27213 * This bit must be '1' for the ring_arb_cfg field to be
27216 #define HWRM_RING_ALLOC_INPUT_ENABLES_RING_ARB_CFG \
27219 * This bit must be '1' for the stat_ctx_id_valid field to be
27222 #define HWRM_RING_ALLOC_INPUT_ENABLES_STAT_CTX_ID_VALID \
27225 * This bit must be '1' for the max_bw_valid field to be
27228 #define HWRM_RING_ALLOC_INPUT_ENABLES_MAX_BW_VALID \
27231 * This bit must be '1' for the rx_ring_id field to be
27234 #define HWRM_RING_ALLOC_INPUT_ENABLES_RX_RING_ID_VALID \
27237 * This bit must be '1' for the nq_ring_id field to be
27240 #define HWRM_RING_ALLOC_INPUT_ENABLES_NQ_RING_ID_VALID \
27243 * This bit must be '1' for the rx_buf_size field to be
27246 #define HWRM_RING_ALLOC_INPUT_ENABLES_RX_BUF_SIZE_VALID \
27249 * This bit must be '1' for the schq_id field to be
27252 #define HWRM_RING_ALLOC_INPUT_ENABLES_SCHQ_ID \
27256 /* L2 Completion Ring (CR) */
27257 #define HWRM_RING_ALLOC_INPUT_RING_TYPE_L2_CMPL UINT32_C(0x0)
27259 #define HWRM_RING_ALLOC_INPUT_RING_TYPE_TX UINT32_C(0x1)
27261 #define HWRM_RING_ALLOC_INPUT_RING_TYPE_RX UINT32_C(0x2)
27262 /* RoCE Notification Completion Ring (ROCE_CR) */
27263 #define HWRM_RING_ALLOC_INPUT_RING_TYPE_ROCE_CMPL UINT32_C(0x3)
27264 /* RX Aggregation Ring */
27265 #define HWRM_RING_ALLOC_INPUT_RING_TYPE_RX_AGG UINT32_C(0x4)
27266 /* Notification Queue */
27267 #define HWRM_RING_ALLOC_INPUT_RING_TYPE_NQ UINT32_C(0x5)
27268 #define HWRM_RING_ALLOC_INPUT_RING_TYPE_LAST \
27269 HWRM_RING_ALLOC_INPUT_RING_TYPE_NQ
27271 /* Ring allocation flags. */
27274 * For Rx rings, the incoming packet data can be placed at either
27275 * a 0B or 2B offset from the start of the Rx packet buffer. When
27276 * '1', the received packet will be padded with 2B of zeros at the
27277 * front of the packet. Note that this flag is only used for
27278 * Rx rings and is ignored for all other rings included Rx
27279 * Aggregation rings.
27281 #define HWRM_RING_ALLOC_INPUT_FLAGS_RX_SOP_PAD UINT32_C(0x1)
27283 * This value is a pointer to the page table for the
27286 uint64_t page_tbl_addr;
27287 /* First Byte Offset of the first entry in the first page. */
27290 * Actual page size in 2^page_size. The supported range is increments
27291 * in powers of 2 from 16 bytes to 1GB.
27293 * Page size is 16 B.
27295 * Page size is 4 KB.
27297 * Page size is 8 KB.
27299 * Page size is 64 KB.
27301 * Page size is 2 MB.
27303 * Page size is 4 MB.
27305 * Page size is 1 GB.
27309 * This value indicates the depth of page table.
27310 * For this version of the specification, value other than 0 or
27311 * 1 shall be considered as an invalid value.
27312 * When the page_tbl_depth = 0, then it is treated as a
27313 * special case with the following.
27314 * 1. FBO and page size fields are not valid.
27315 * 2. page_tbl_addr is the physical address of the first
27316 * element of the ring.
27318 uint8_t page_tbl_depth;
27319 /* Used by a PF driver to associate a SCHQ with one of its TX rings. */
27322 * Number of 16B units in the ring. Minimum size for
27323 * a ring is 16 16B entries.
27327 * Logical ring number for the ring to be allocated.
27328 * This value determines the position in the doorbell
27329 * area where the update to the ring will be made.
27331 * For completion rings, this value is also the MSI-X
27332 * vector number for the function the completion ring is
27335 uint16_t logical_id;
27337 * This field is used only when ring_type is a TX ring.
27338 * This value indicates what completion ring the TX ring
27339 * is associated with.
27341 uint16_t cmpl_ring_id;
27343 * This field is used only when ring_type is a TX ring.
27344 * This value indicates what CoS queue the TX ring
27345 * is associated with.
27349 * When allocating a Rx ring or Rx aggregation ring, this field
27350 * specifies the size of the buffer descriptors posted to the ring.
27352 uint16_t rx_buf_size;
27354 * When allocating an Rx aggregation ring, this field
27355 * specifies the associated Rx ring ID.
27357 uint16_t rx_ring_id;
27359 * When allocating a completion ring, this field
27360 * specifies the associated NQ ring ID.
27362 uint16_t nq_ring_id;
27364 * This field is used only when ring_type is a TX ring.
27365 * This field is used to configure arbitration related
27366 * parameters for a TX ring.
27368 uint16_t ring_arb_cfg;
27369 /* Arbitration policy used for the ring. */
27370 #define HWRM_RING_ALLOC_INPUT_RING_ARB_CFG_ARB_POLICY_MASK \
27372 #define HWRM_RING_ALLOC_INPUT_RING_ARB_CFG_ARB_POLICY_SFT 0
27374 * Use strict priority for the TX ring.
27375 * Priority value is specified in arb_policy_param
27377 #define HWRM_RING_ALLOC_INPUT_RING_ARB_CFG_ARB_POLICY_SP \
27380 * Use weighted fair queue arbitration for the TX ring.
27381 * Weight is specified in arb_policy_param
27383 #define HWRM_RING_ALLOC_INPUT_RING_ARB_CFG_ARB_POLICY_WFQ \
27385 #define HWRM_RING_ALLOC_INPUT_RING_ARB_CFG_ARB_POLICY_LAST \
27386 HWRM_RING_ALLOC_INPUT_RING_ARB_CFG_ARB_POLICY_WFQ
27387 /* Reserved field. */
27388 #define HWRM_RING_ALLOC_INPUT_RING_ARB_CFG_RSVD_MASK \
27390 #define HWRM_RING_ALLOC_INPUT_RING_ARB_CFG_RSVD_SFT 4
27392 * Arbitration policy specific parameter.
27393 * # For strict priority arbitration policy, this field
27394 * represents a priority value. If set to 0, then the priority
27395 * is not specified and the HWRM is allowed to select
27396 * any priority for this TX ring.
27397 * # For weighted fair queue arbitration policy, this field
27398 * represents a weight value. If set to 0, then the weight
27399 * is not specified and the HWRM is allowed to select
27400 * any weight for this TX ring.
27402 #define HWRM_RING_ALLOC_INPUT_RING_ARB_CFG_ARB_POLICY_PARAM_MASK \
27404 #define HWRM_RING_ALLOC_INPUT_RING_ARB_CFG_ARB_POLICY_PARAM_SFT 8
27407 * This field is reserved for the future use.
27408 * It shall be set to 0.
27410 uint32_t reserved3;
27412 * This field is used only when ring_type is a TX ring.
27413 * This input indicates what statistics context this ring
27414 * should be associated with.
27416 uint32_t stat_ctx_id;
27418 * This field is reserved for the future use.
27419 * It shall be set to 0.
27421 uint32_t reserved4;
27423 * This field is used only when ring_type is a TX ring
27424 * to specify maximum BW allocated to the TX ring.
27425 * The HWRM will translate this value into byte counter and
27426 * time interval used for this ring inside the device.
27429 /* The bandwidth value. */
27430 #define HWRM_RING_ALLOC_INPUT_MAX_BW_BW_VALUE_MASK \
27431 UINT32_C(0xfffffff)
27432 #define HWRM_RING_ALLOC_INPUT_MAX_BW_BW_VALUE_SFT 0
27433 /* The granularity of the value (bits or bytes). */
27434 #define HWRM_RING_ALLOC_INPUT_MAX_BW_SCALE \
27435 UINT32_C(0x10000000)
27436 /* Value is in bits. */
27437 #define HWRM_RING_ALLOC_INPUT_MAX_BW_SCALE_BITS \
27438 (UINT32_C(0x0) << 28)
27439 /* Value is in bytes. */
27440 #define HWRM_RING_ALLOC_INPUT_MAX_BW_SCALE_BYTES \
27441 (UINT32_C(0x1) << 28)
27442 #define HWRM_RING_ALLOC_INPUT_MAX_BW_SCALE_LAST \
27443 HWRM_RING_ALLOC_INPUT_MAX_BW_SCALE_BYTES
27444 /* bw_value_unit is 3 b */
27445 #define HWRM_RING_ALLOC_INPUT_MAX_BW_BW_VALUE_UNIT_MASK \
27446 UINT32_C(0xe0000000)
27447 #define HWRM_RING_ALLOC_INPUT_MAX_BW_BW_VALUE_UNIT_SFT 29
27448 /* Value is in Mb or MB (base 10). */
27449 #define HWRM_RING_ALLOC_INPUT_MAX_BW_BW_VALUE_UNIT_MEGA \
27450 (UINT32_C(0x0) << 29)
27451 /* Value is in Kb or KB (base 10). */
27452 #define HWRM_RING_ALLOC_INPUT_MAX_BW_BW_VALUE_UNIT_KILO \
27453 (UINT32_C(0x2) << 29)
27454 /* Value is in bits or bytes. */
27455 #define HWRM_RING_ALLOC_INPUT_MAX_BW_BW_VALUE_UNIT_BASE \
27456 (UINT32_C(0x4) << 29)
27457 /* Value is in Gb or GB (base 10). */
27458 #define HWRM_RING_ALLOC_INPUT_MAX_BW_BW_VALUE_UNIT_GIGA \
27459 (UINT32_C(0x6) << 29)
27460 /* Value is in 1/100th of a percentage of total bandwidth. */
27461 #define HWRM_RING_ALLOC_INPUT_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 \
27462 (UINT32_C(0x1) << 29)
27464 #define HWRM_RING_ALLOC_INPUT_MAX_BW_BW_VALUE_UNIT_INVALID \
27465 (UINT32_C(0x7) << 29)
27466 #define HWRM_RING_ALLOC_INPUT_MAX_BW_BW_VALUE_UNIT_LAST \
27467 HWRM_RING_ALLOC_INPUT_MAX_BW_BW_VALUE_UNIT_INVALID
27469 * This field is used only when ring_type is a Completion ring.
27470 * This value indicates what interrupt mode should be used
27471 * on this completion ring.
27472 * Note: In the legacy interrupt mode, no more than 16
27473 * completion rings are allowed.
27477 #define HWRM_RING_ALLOC_INPUT_INT_MODE_LEGACY UINT32_C(0x0)
27479 #define HWRM_RING_ALLOC_INPUT_INT_MODE_RSVD UINT32_C(0x1)
27481 #define HWRM_RING_ALLOC_INPUT_INT_MODE_MSIX UINT32_C(0x2)
27482 /* No Interrupt - Polled mode */
27483 #define HWRM_RING_ALLOC_INPUT_INT_MODE_POLL UINT32_C(0x3)
27484 #define HWRM_RING_ALLOC_INPUT_INT_MODE_LAST \
27485 HWRM_RING_ALLOC_INPUT_INT_MODE_POLL
27486 uint8_t unused_4[3];
27488 * The cq_handle is specified when allocating a completion ring. For
27489 * devices that support NQs, this cq_handle will be included in the
27490 * NQE to specify which CQ should be read to retrieve the completion
27493 uint64_t cq_handle;
27496 /* hwrm_ring_alloc_output (size:128b/16B) */
27497 struct hwrm_ring_alloc_output {
27498 /* The specific error status for the command. */
27499 uint16_t error_code;
27500 /* The HWRM command request type. */
27502 /* The sequence ID from the original command. */
27504 /* The length of the response data in number of bytes. */
27507 * Physical number of ring allocated.
27508 * This value shall be unique for a ring type.
27511 /* Logical number of ring allocated. */
27512 uint16_t logical_ring_id;
27513 uint8_t unused_0[3];
27515 * This field is used in Output records to indicate that the output
27516 * is completely written to RAM. This field should be read as '1'
27517 * to indicate that the output has been completely written.
27518 * When writing a command completion or response to an internal processor,
27519 * the order of writes has to be such that this field is written last.
27524 /******************
27526 ******************/
27529 /* hwrm_ring_free_input (size:192b/24B) */
27530 struct hwrm_ring_free_input {
27531 /* The HWRM command request type. */
27534 * The completion ring to send the completion event on. This should
27535 * be the NQ ID returned from the `nq_alloc` HWRM command.
27537 uint16_t cmpl_ring;
27539 * The sequence ID is used by the driver for tracking multiple
27540 * commands. This ID is treated as opaque data by the firmware and
27541 * the value is returned in the `hwrm_resp_hdr` upon completion.
27545 * The target ID of the command:
27546 * * 0x0-0xFFF8 - The function ID
27547 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
27548 * * 0xFFFD - Reserved for user-space HWRM interface
27551 uint16_t target_id;
27553 * A physical address pointer pointing to a host buffer that the
27554 * command's response data will be written. This can be either a host
27555 * physical address (HPA) or a guest physical address (GPA) and must
27556 * point to a physically contiguous block of memory.
27558 uint64_t resp_addr;
27561 /* L2 Completion Ring (CR) */
27562 #define HWRM_RING_FREE_INPUT_RING_TYPE_L2_CMPL UINT32_C(0x0)
27564 #define HWRM_RING_FREE_INPUT_RING_TYPE_TX UINT32_C(0x1)
27566 #define HWRM_RING_FREE_INPUT_RING_TYPE_RX UINT32_C(0x2)
27567 /* RoCE Notification Completion Ring (ROCE_CR) */
27568 #define HWRM_RING_FREE_INPUT_RING_TYPE_ROCE_CMPL UINT32_C(0x3)
27569 /* RX Aggregation Ring */
27570 #define HWRM_RING_FREE_INPUT_RING_TYPE_RX_AGG UINT32_C(0x4)
27571 /* Notification Queue */
27572 #define HWRM_RING_FREE_INPUT_RING_TYPE_NQ UINT32_C(0x5)
27573 #define HWRM_RING_FREE_INPUT_RING_TYPE_LAST \
27574 HWRM_RING_FREE_INPUT_RING_TYPE_NQ
27576 /* Physical number of ring allocated. */
27578 uint8_t unused_1[4];
27581 /* hwrm_ring_free_output (size:128b/16B) */
27582 struct hwrm_ring_free_output {
27583 /* The specific error status for the command. */
27584 uint16_t error_code;
27585 /* The HWRM command request type. */
27587 /* The sequence ID from the original command. */
27589 /* The length of the response data in number of bytes. */
27591 uint8_t unused_0[7];
27593 * This field is used in Output records to indicate that the output
27594 * is completely written to RAM. This field should be read as '1'
27595 * to indicate that the output has been completely written.
27596 * When writing a command completion or response to an internal processor,
27597 * the order of writes has to be such that this field is written last.
27602 /*******************
27603 * hwrm_ring_reset *
27604 *******************/
27607 /* hwrm_ring_reset_input (size:192b/24B) */
27608 struct hwrm_ring_reset_input {
27609 /* The HWRM command request type. */
27612 * The completion ring to send the completion event on. This should
27613 * be the NQ ID returned from the `nq_alloc` HWRM command.
27615 uint16_t cmpl_ring;
27617 * The sequence ID is used by the driver for tracking multiple
27618 * commands. This ID is treated as opaque data by the firmware and
27619 * the value is returned in the `hwrm_resp_hdr` upon completion.
27623 * The target ID of the command:
27624 * * 0x0-0xFFF8 - The function ID
27625 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
27626 * * 0xFFFD - Reserved for user-space HWRM interface
27629 uint16_t target_id;
27631 * A physical address pointer pointing to a host buffer that the
27632 * command's response data will be written. This can be either a host
27633 * physical address (HPA) or a guest physical address (GPA) and must
27634 * point to a physically contiguous block of memory.
27636 uint64_t resp_addr;
27639 /* L2 Completion Ring (CR) */
27640 #define HWRM_RING_RESET_INPUT_RING_TYPE_L2_CMPL UINT32_C(0x0)
27642 #define HWRM_RING_RESET_INPUT_RING_TYPE_TX UINT32_C(0x1)
27644 #define HWRM_RING_RESET_INPUT_RING_TYPE_RX UINT32_C(0x2)
27645 /* RoCE Notification Completion Ring (ROCE_CR) */
27646 #define HWRM_RING_RESET_INPUT_RING_TYPE_ROCE_CMPL UINT32_C(0x3)
27648 * Rx Ring Group. This is to reset rx and aggregation in an atomic
27649 * operation. Completion ring associated with this ring group is
27652 #define HWRM_RING_RESET_INPUT_RING_TYPE_RX_RING_GRP UINT32_C(0x6)
27653 #define HWRM_RING_RESET_INPUT_RING_TYPE_LAST \
27654 HWRM_RING_RESET_INPUT_RING_TYPE_RX_RING_GRP
27657 * Physical number of the ring. When ring type is rx_ring_grp, ring id
27658 * actually refers to ring group id.
27661 uint8_t unused_1[4];
27664 /* hwrm_ring_reset_output (size:128b/16B) */
27665 struct hwrm_ring_reset_output {
27666 /* The specific error status for the command. */
27667 uint16_t error_code;
27668 /* The HWRM command request type. */
27670 /* The sequence ID from the original command. */
27672 /* The length of the response data in number of bytes. */
27674 uint8_t unused_0[4];
27675 /* Position of consumer index after ring reset completes. */
27676 uint8_t consumer_idx[3];
27678 * This field is used in Output records to indicate that the output
27679 * is completely written to RAM. This field should be read as '1'
27680 * to indicate that the output has been completely written.
27681 * When writing a command completion or response to an internal processor,
27682 * the order of writes has to be such that this field is written last.
27692 /* hwrm_ring_cfg_input (size:256b/32B) */
27693 struct hwrm_ring_cfg_input {
27694 /* The HWRM command request type. */
27697 * The completion ring to send the completion event on. This should
27698 * be the NQ ID returned from the `nq_alloc` HWRM command.
27700 uint16_t cmpl_ring;
27702 * The sequence ID is used by the driver for tracking multiple
27703 * commands. This ID is treated as opaque data by the firmware and
27704 * the value is returned in the `hwrm_resp_hdr` upon completion.
27708 * The target ID of the command:
27709 * * 0x0-0xFFF8 - The function ID
27710 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
27711 * * 0xFFFD - Reserved for user-space HWRM interface
27714 uint16_t target_id;
27716 * A physical address pointer pointing to a host buffer that the
27717 * command's response data will be written. This can be either a host
27718 * physical address (HPA) or a guest physical address (GPA) and must
27719 * point to a physically contiguous block of memory.
27721 uint64_t resp_addr;
27725 #define HWRM_RING_CFG_INPUT_RING_TYPE_TX UINT32_C(0x1)
27727 #define HWRM_RING_CFG_INPUT_RING_TYPE_RX UINT32_C(0x2)
27728 #define HWRM_RING_CFG_INPUT_RING_TYPE_LAST \
27729 HWRM_RING_CFG_INPUT_RING_TYPE_RX
27731 /* Physical number of the ring. */
27733 /* Ring config enable bits. */
27736 * For Rx rings, the incoming packet data can be placed at either
27737 * a 0B, 2B, 10B or 12B offset from the start of the Rx packet
27739 * When '1', the received packet will be padded with 2B, 10B or 12B
27740 * of zeros at the front of the packet. The exact offset is specified
27741 * by rx_sop_pad_bytes parameter.
27742 * When '0', the received packet will not be padded.
27743 * Note that this flag is only used for Rx rings and is ignored
27744 * for all other rings included Rx Aggregation rings.
27746 #define HWRM_RING_CFG_INPUT_ENABLES_RX_SOP_PAD_ENABLE \
27749 * Proxy mode enable, for Tx, Rx and Rx aggregation rings only.
27750 * When rings are allocated, the PCI function on which driver issues
27751 * HWRM_RING_CFG command is assumed to own the rings. Hardware takes
27752 * the buffer descriptors (BDs) from those rings is assumed to issue
27753 * packet payload DMA using same PCI function. When proxy mode is
27754 * enabled, hardware can perform payload DMA using another PCI
27755 * function on same or different host.
27756 * When set to '0', the PCI function on which driver issues
27757 * HWRM_RING_CFG command is used for host payload DMA operation.
27758 * When set to '1', the host PCI function specified by proxy_fid is
27759 * used for host payload DMA operation.
27761 #define HWRM_RING_CFG_INPUT_ENABLES_PROXY_MODE_ENABLE \
27764 * Tx ring packet source interface override, for Tx rings only.
27765 * When TX rings are allocated, the PCI function on which driver
27766 * issues HWRM_RING_CFG is assumed to be source interface of
27767 * packets sent from TX ring.
27768 * When set to '1', the host PCI function specified by proxy_fid
27769 * is used as source interface of the transmitted packets.
27771 #define HWRM_RING_CFG_INPUT_ENABLES_TX_PROXY_SRC_INTF_OVERRIDE \
27773 /* The schq_id field is valid */
27774 #define HWRM_RING_CFG_INPUT_ENABLES_SCHQ_ID \
27776 /* Update completion ring ID associated with Tx or Rx ring. */
27777 #define HWRM_RING_CFG_INPUT_ENABLES_CMPL_RING_ID_UPDATE \
27780 * Proxy function FID value.
27781 * This value is only used when either proxy_mode_enable flag or
27782 * tx_proxy_svif_override is set to '1'.
27783 * When proxy_mode_enable is set to '1', it identifies a host PCI
27784 * function used for host payload DMA operations.
27785 * When tx_proxy_src_intf is set to '1', it identifies a host PCI
27786 * function as source interface for all transmitted packets from
27789 uint16_t proxy_fid;
27791 * Identifies the new scheduler queue (SCHQ) to associate with the
27792 * ring. Only valid for Tx rings.
27793 * A value of zero indicates that the Tx ring should be associated
27794 * with the default scheduler queue (SCHQ).
27798 * This field is valid for TX or Rx rings. This value identifies the
27799 * new completion ring ID to associate with the TX or Rx ring.
27801 uint16_t cmpl_ring_id;
27803 * Rx SOP padding amount in bytes.
27804 * This value is only used when rx_sop_pad_enable flag is set to '1'.
27806 uint8_t rx_sop_pad_bytes;
27807 uint8_t unused_1[3];
27810 /* hwrm_ring_cfg_output (size:128b/16B) */
27811 struct hwrm_ring_cfg_output {
27812 /* The specific error status for the command. */
27813 uint16_t error_code;
27814 /* The HWRM command request type. */
27816 /* The sequence ID from the original command. */
27818 /* The length of the response data in number of bytes. */
27820 uint8_t unused_0[7];
27822 * This field is used in Output records to indicate that the output
27823 * is completely written to RAM. This field should be read as '1'
27824 * to indicate that the output has been completely written.
27825 * When writing a command completion or response to an internal
27826 * processor, the order of writes has to be such that this field is
27832 /******************
27834 ******************/
27837 /* hwrm_ring_qcfg_input (size:192b/24B) */
27838 struct hwrm_ring_qcfg_input {
27839 /* The HWRM command request type. */
27842 * The completion ring to send the completion event on. This should
27843 * be the NQ ID returned from the `nq_alloc` HWRM command.
27845 uint16_t cmpl_ring;
27847 * The sequence ID is used by the driver for tracking multiple
27848 * commands. This ID is treated as opaque data by the firmware and
27849 * the value is returned in the `hwrm_resp_hdr` upon completion.
27853 * The target ID of the command:
27854 * * 0x0-0xFFF8 - The function ID
27855 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
27856 * * 0xFFFD - Reserved for user-space HWRM interface
27859 uint16_t target_id;
27861 * A physical address pointer pointing to a host buffer that the
27862 * command's response data will be written. This can be either a host
27863 * physical address (HPA) or a guest physical address (GPA) and must
27864 * point to a physically contiguous block of memory.
27866 uint64_t resp_addr;
27870 #define HWRM_RING_QCFG_INPUT_RING_TYPE_TX UINT32_C(0x1)
27872 #define HWRM_RING_QCFG_INPUT_RING_TYPE_RX UINT32_C(0x2)
27873 #define HWRM_RING_QCFG_INPUT_RING_TYPE_LAST \
27874 HWRM_RING_QCFG_INPUT_RING_TYPE_RX
27875 uint8_t unused_0[5];
27876 /* Physical number of the ring. */
27880 /* hwrm_ring_qcfg_output (size:192b/24B) */
27881 struct hwrm_ring_qcfg_output {
27882 /* The specific error status for the command. */
27883 uint16_t error_code;
27884 /* The HWRM command request type. */
27886 /* The sequence ID from the original command. */
27888 /* The length of the response data in number of bytes. */
27890 /* Ring config enable bits. */
27893 * For Rx rings, the incoming packet data can be placed at either
27894 * a 0B, 2B, 10B or 12B offset from the start of the Rx packet
27896 * When '1', the received packet will be padded with 2B, 10B or 12B
27897 * of zeros at the front of the packet. The exact offset is specified
27898 * by rx_sop_pad_bytes parameter.
27899 * When '0', the received packet will not be padded.
27900 * Note that this flag is only used for Rx rings and is ignored
27901 * for all other rings included Rx Aggregation rings.
27903 #define HWRM_RING_QCFG_OUTPUT_ENABLES_RX_SOP_PAD_ENABLE \
27906 * Proxy mode enable, for Tx, Rx and Rx aggregation rings only.
27907 * When rings are allocated, the PCI function on which driver issues
27908 * HWRM_RING_CFG command is assumed to own the rings. Hardware takes
27909 * the buffer descriptors (BDs) from those rings is assumed to issue
27910 * packet payload DMA using same PCI function. When proxy mode is
27911 * enabled, hardware can perform payload DMA using another PCI
27912 * function on same or different host.
27913 * When set to '0', the PCI function on which driver issues
27914 * HWRM_RING_CFG command is used for host payload DMA operation.
27915 * When set to '1', the host PCI function specified by proxy_fid is
27916 * used for host payload DMA operation.
27918 #define HWRM_RING_QCFG_OUTPUT_ENABLES_PROXY_MODE_ENABLE \
27921 * Tx ring packet source interface override, for Tx rings only.
27922 * When TX rings are allocated, the PCI function on which driver
27923 * issues HWRM_RING_CFG is assumed to be source interface of
27924 * packets sent from TX ring.
27925 * When set to '1', the host PCI function specified by proxy_fid is
27926 * used as source interface of the transmitted packets.
27928 #define HWRM_RING_QCFG_OUTPUT_ENABLES_TX_PROXY_SRC_INTF_OVERRIDE \
27931 * Proxy function FID value.
27932 * This value is only used when either proxy_mode_enable flag or
27933 * tx_proxy_svif_override is set to '1'.
27934 * When proxy_mode_enable is set to '1', it identifies a host PCI
27935 * function used for host payload DMA operations.
27936 * When tx_proxy_src_intf is set to '1', it identifies a host PCI
27937 * function as source interface for all transmitted packets from the TX
27940 uint16_t proxy_fid;
27942 * Identifies the new scheduler queue (SCHQ) to associate with the
27943 * ring. Only valid for Tx rings.
27944 * A value of zero indicates that the Tx ring should be associated with
27945 * the default scheduler queue (SCHQ).
27949 * This field is used when ring_type is a TX or Rx ring.
27950 * This value indicates what completion ring the TX or Rx ring
27951 * is associated with.
27953 uint16_t cmpl_ring_id;
27955 * Rx SOP padding amount in bytes.
27956 * This value is only used when rx_sop_pad_enable flag is set to '1'.
27958 uint8_t rx_sop_pad_bytes;
27959 uint8_t unused_0[6];
27961 * This field is used in Output records to indicate that the output
27962 * is completely written to RAM. This field should be read as '1'
27963 * to indicate that the output has been completely written.
27964 * When writing a command completion or response to an internal
27965 * processor, the order of writes has to be such that this field is
27971 /**************************
27972 * hwrm_ring_aggint_qcaps *
27973 **************************/
27976 /* hwrm_ring_aggint_qcaps_input (size:128b/16B) */
27977 struct hwrm_ring_aggint_qcaps_input {
27978 /* The HWRM command request type. */
27981 * The completion ring to send the completion event on. This should
27982 * be the NQ ID returned from the `nq_alloc` HWRM command.
27984 uint16_t cmpl_ring;
27986 * The sequence ID is used by the driver for tracking multiple
27987 * commands. This ID is treated as opaque data by the firmware and
27988 * the value is returned in the `hwrm_resp_hdr` upon completion.
27992 * The target ID of the command:
27993 * * 0x0-0xFFF8 - The function ID
27994 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
27995 * * 0xFFFD - Reserved for user-space HWRM interface
27998 uint16_t target_id;
28000 * A physical address pointer pointing to a host buffer that the
28001 * command's response data will be written. This can be either a host
28002 * physical address (HPA) or a guest physical address (GPA) and must
28003 * point to a physically contiguous block of memory.
28005 uint64_t resp_addr;
28008 /* hwrm_ring_aggint_qcaps_output (size:384b/48B) */
28009 struct hwrm_ring_aggint_qcaps_output {
28010 /* The specific error status for the command. */
28011 uint16_t error_code;
28012 /* The HWRM command request type. */
28014 /* The sequence ID from the original command. */
28016 /* The length of the response data in number of bytes. */
28018 uint32_t cmpl_params;
28020 * When this bit is set to '1', int_lat_tmr_min can be configured
28021 * on completion rings.
28023 #define HWRM_RING_AGGINT_QCAPS_OUTPUT_CMPL_PARAMS_INT_LAT_TMR_MIN \
28026 * When this bit is set to '1', int_lat_tmr_max can be configured
28027 * on completion rings.
28029 #define HWRM_RING_AGGINT_QCAPS_OUTPUT_CMPL_PARAMS_INT_LAT_TMR_MAX \
28032 * When this bit is set to '1', timer_reset can be enabled
28033 * on completion rings.
28035 #define HWRM_RING_AGGINT_QCAPS_OUTPUT_CMPL_PARAMS_TIMER_RESET \
28038 * When this bit is set to '1', ring_idle can be enabled
28039 * on completion rings.
28041 #define HWRM_RING_AGGINT_QCAPS_OUTPUT_CMPL_PARAMS_RING_IDLE \
28044 * When this bit is set to '1', num_cmpl_dma_aggr can be configured
28045 * on completion rings.
28047 #define HWRM_RING_AGGINT_QCAPS_OUTPUT_CMPL_PARAMS_NUM_CMPL_DMA_AGGR \
28050 * When this bit is set to '1', num_cmpl_dma_aggr_during_int can be configured
28051 * on completion rings.
28053 #define HWRM_RING_AGGINT_QCAPS_OUTPUT_CMPL_PARAMS_NUM_CMPL_DMA_AGGR_DURING_INT \
28056 * When this bit is set to '1', cmpl_aggr_dma_tmr can be configured
28057 * on completion rings.
28059 #define HWRM_RING_AGGINT_QCAPS_OUTPUT_CMPL_PARAMS_CMPL_AGGR_DMA_TMR \
28062 * When this bit is set to '1', cmpl_aggr_dma_tmr_during_int can be configured
28063 * on completion rings.
28065 #define HWRM_RING_AGGINT_QCAPS_OUTPUT_CMPL_PARAMS_CMPL_AGGR_DMA_TMR_DURING_INT \
28068 * When this bit is set to '1', num_cmpl_aggr_int can be configured
28069 * on completion rings.
28071 #define HWRM_RING_AGGINT_QCAPS_OUTPUT_CMPL_PARAMS_NUM_CMPL_AGGR_INT \
28073 uint32_t nq_params;
28075 * When this bit is set to '1', int_lat_tmr_min can be configured
28076 * on notification queues.
28078 #define HWRM_RING_AGGINT_QCAPS_OUTPUT_NQ_PARAMS_INT_LAT_TMR_MIN \
28080 /* Minimum value for num_cmpl_dma_aggr */
28081 uint16_t num_cmpl_dma_aggr_min;
28082 /* Maximum value for num_cmpl_dma_aggr */
28083 uint16_t num_cmpl_dma_aggr_max;
28084 /* Minimum value for num_cmpl_dma_aggr_during_int */
28085 uint16_t num_cmpl_dma_aggr_during_int_min;
28086 /* Maximum value for num_cmpl_dma_aggr_during_int */
28087 uint16_t num_cmpl_dma_aggr_during_int_max;
28088 /* Minimum value for cmpl_aggr_dma_tmr */
28089 uint16_t cmpl_aggr_dma_tmr_min;
28090 /* Maximum value for cmpl_aggr_dma_tmr */
28091 uint16_t cmpl_aggr_dma_tmr_max;
28092 /* Minimum value for cmpl_aggr_dma_tmr_during_int */
28093 uint16_t cmpl_aggr_dma_tmr_during_int_min;
28094 /* Maximum value for cmpl_aggr_dma_tmr_during_int */
28095 uint16_t cmpl_aggr_dma_tmr_during_int_max;
28096 /* Minimum value for int_lat_tmr_min */
28097 uint16_t int_lat_tmr_min_min;
28098 /* Maximum value for int_lat_tmr_min */
28099 uint16_t int_lat_tmr_min_max;
28100 /* Minimum value for int_lat_tmr_max */
28101 uint16_t int_lat_tmr_max_min;
28102 /* Maximum value for int_lat_tmr_max */
28103 uint16_t int_lat_tmr_max_max;
28104 /* Minimum value for num_cmpl_aggr_int */
28105 uint16_t num_cmpl_aggr_int_min;
28106 /* Maximum value for num_cmpl_aggr_int */
28107 uint16_t num_cmpl_aggr_int_max;
28108 /* The units for timer parameters, in nanoseconds. */
28109 uint16_t timer_units;
28110 uint8_t unused_0[1];
28112 * This field is used in Output records to indicate that the output
28113 * is completely written to RAM. This field should be read as '1'
28114 * to indicate that the output has been completely written.
28115 * When writing a command completion or response to an internal processor,
28116 * the order of writes has to be such that this field is written last.
28121 /**************************************
28122 * hwrm_ring_cmpl_ring_qaggint_params *
28123 **************************************/
28126 /* hwrm_ring_cmpl_ring_qaggint_params_input (size:192b/24B) */
28127 struct hwrm_ring_cmpl_ring_qaggint_params_input {
28128 /* The HWRM command request type. */
28131 * The completion ring to send the completion event on. This should
28132 * be the NQ ID returned from the `nq_alloc` HWRM command.
28134 uint16_t cmpl_ring;
28136 * The sequence ID is used by the driver for tracking multiple
28137 * commands. This ID is treated as opaque data by the firmware and
28138 * the value is returned in the `hwrm_resp_hdr` upon completion.
28142 * The target ID of the command:
28143 * * 0x0-0xFFF8 - The function ID
28144 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
28145 * * 0xFFFD - Reserved for user-space HWRM interface
28148 uint16_t target_id;
28150 * A physical address pointer pointing to a host buffer that the
28151 * command's response data will be written. This can be either a host
28152 * physical address (HPA) or a guest physical address (GPA) and must
28153 * point to a physically contiguous block of memory.
28155 uint64_t resp_addr;
28156 /* Physical number of completion ring. */
28159 #define HWRM_RING_CMPL_RING_QAGGINT_PARAMS_INPUT_FLAGS_UNUSED_0_MASK \
28161 #define HWRM_RING_CMPL_RING_QAGGINT_PARAMS_INPUT_FLAGS_UNUSED_0_SFT 0
28163 * Set this flag to 1 when querying parameters on a notification
28164 * queue. Set this flag to 0 when querying parameters on a
28165 * completion queue or completion ring.
28167 #define HWRM_RING_CMPL_RING_QAGGINT_PARAMS_INPUT_FLAGS_IS_NQ \
28169 uint8_t unused_0[4];
28172 /* hwrm_ring_cmpl_ring_qaggint_params_output (size:256b/32B) */
28173 struct hwrm_ring_cmpl_ring_qaggint_params_output {
28174 /* The specific error status for the command. */
28175 uint16_t error_code;
28176 /* The HWRM command request type. */
28178 /* The sequence ID from the original command. */
28180 /* The length of the response data in number of bytes. */
28184 * When this bit is set to '1', interrupt max
28185 * timer is reset whenever a completion is received.
28187 #define HWRM_RING_CMPL_RING_QAGGINT_PARAMS_OUTPUT_FLAGS_TIMER_RESET \
28190 * When this bit is set to '1', ring idle mode
28191 * aggregation will be enabled.
28193 #define HWRM_RING_CMPL_RING_QAGGINT_PARAMS_OUTPUT_FLAGS_RING_IDLE \
28196 * Number of completions to aggregate before DMA
28197 * during the normal mode.
28199 uint16_t num_cmpl_dma_aggr;
28201 * Number of completions to aggregate before DMA
28202 * during the interrupt mode.
28204 uint16_t num_cmpl_dma_aggr_during_int;
28206 * Timer used to aggregate completions before
28207 * DMA during the normal mode (not in interrupt mode).
28209 uint16_t cmpl_aggr_dma_tmr;
28211 * Timer used to aggregate completions before
28212 * DMA when in interrupt mode.
28214 uint16_t cmpl_aggr_dma_tmr_during_int;
28215 /* Minimum time between two interrupts. */
28216 uint16_t int_lat_tmr_min;
28218 * Maximum wait time spent aggregating
28219 * completions before signaling the interrupt after the
28220 * interrupt is enabled.
28222 uint16_t int_lat_tmr_max;
28224 * Minimum number of completions aggregated before signaling
28227 uint16_t num_cmpl_aggr_int;
28228 uint8_t unused_0[7];
28230 * This field is used in Output records to indicate that the output
28231 * is completely written to RAM. This field should be read as '1'
28232 * to indicate that the output has been completely written.
28233 * When writing a command completion or response to an internal processor,
28234 * the order of writes has to be such that this field is written last.
28239 /*****************************************
28240 * hwrm_ring_cmpl_ring_cfg_aggint_params *
28241 *****************************************/
28244 /* hwrm_ring_cmpl_ring_cfg_aggint_params_input (size:320b/40B) */
28245 struct hwrm_ring_cmpl_ring_cfg_aggint_params_input {
28246 /* The HWRM command request type. */
28249 * The completion ring to send the completion event on. This should
28250 * be the NQ ID returned from the `nq_alloc` HWRM command.
28252 uint16_t cmpl_ring;
28254 * The sequence ID is used by the driver for tracking multiple
28255 * commands. This ID is treated as opaque data by the firmware and
28256 * the value is returned in the `hwrm_resp_hdr` upon completion.
28260 * The target ID of the command:
28261 * * 0x0-0xFFF8 - The function ID
28262 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
28263 * * 0xFFFD - Reserved for user-space HWRM interface
28266 uint16_t target_id;
28268 * A physical address pointer pointing to a host buffer that the
28269 * command's response data will be written. This can be either a host
28270 * physical address (HPA) or a guest physical address (GPA) and must
28271 * point to a physically contiguous block of memory.
28273 uint64_t resp_addr;
28274 /* Physical number of completion ring. */
28278 * When this bit is set to '1', interrupt latency max
28279 * timer is reset whenever a completion is received.
28281 #define HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_FLAGS_TIMER_RESET \
28284 * When this bit is set to '1', ring idle mode
28285 * aggregation will be enabled.
28287 #define HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_FLAGS_RING_IDLE \
28290 * Set this flag to 1 when configuring parameters on a
28291 * notification queue. Set this flag to 0 when configuring
28292 * parameters on a completion queue or completion ring.
28294 #define HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_FLAGS_IS_NQ \
28297 * Number of completions to aggregate before DMA
28298 * during the normal mode.
28300 uint16_t num_cmpl_dma_aggr;
28302 * Number of completions to aggregate before DMA
28303 * during the interrupt mode.
28305 uint16_t num_cmpl_dma_aggr_during_int;
28307 * Timer used to aggregate completions before
28308 * DMA during the normal mode (not in interrupt mode).
28310 uint16_t cmpl_aggr_dma_tmr;
28312 * Timer used to aggregate completions before
28313 * DMA while in interrupt mode.
28315 uint16_t cmpl_aggr_dma_tmr_during_int;
28316 /* Minimum time between two interrupts. */
28317 uint16_t int_lat_tmr_min;
28319 * Maximum wait time spent aggregating
28320 * completions before signaling the interrupt after the
28321 * interrupt is enabled.
28323 uint16_t int_lat_tmr_max;
28325 * Minimum number of completions aggregated before signaling
28328 uint16_t num_cmpl_aggr_int;
28330 * Bitfield that indicates which parameters are to be applied. Only
28331 * required when configuring devices with notification queues, and
28332 * used in that case to set certain parameters on completion queues
28333 * and others on notification queues.
28337 * This bit must be '1' for the num_cmpl_dma_aggr field to be
28340 #define HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_ENABLES_NUM_CMPL_DMA_AGGR \
28343 * This bit must be '1' for the num_cmpl_dma_aggr_during_int field to be
28346 #define HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_ENABLES_NUM_CMPL_DMA_AGGR_DURING_INT \
28349 * This bit must be '1' for the cmpl_aggr_dma_tmr field to be
28352 #define HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_ENABLES_CMPL_AGGR_DMA_TMR \
28355 * This bit must be '1' for the int_lat_tmr_min field to be
28358 #define HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_ENABLES_INT_LAT_TMR_MIN \
28361 * This bit must be '1' for the int_lat_tmr_max field to be
28364 #define HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_ENABLES_INT_LAT_TMR_MAX \
28367 * This bit must be '1' for the num_cmpl_aggr_int field to be
28370 #define HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_ENABLES_NUM_CMPL_AGGR_INT \
28372 uint8_t unused_0[4];
28375 /* hwrm_ring_cmpl_ring_cfg_aggint_params_output (size:128b/16B) */
28376 struct hwrm_ring_cmpl_ring_cfg_aggint_params_output {
28377 /* The specific error status for the command. */
28378 uint16_t error_code;
28379 /* The HWRM command request type. */
28381 /* The sequence ID from the original command. */
28383 /* The length of the response data in number of bytes. */
28385 uint8_t unused_0[7];
28387 * This field is used in Output records to indicate that the output
28388 * is completely written to RAM. This field should be read as '1'
28389 * to indicate that the output has been completely written.
28390 * When writing a command completion or response to an internal processor,
28391 * the order of writes has to be such that this field is written last.
28396 /***********************
28397 * hwrm_ring_grp_alloc *
28398 ***********************/
28401 /* hwrm_ring_grp_alloc_input (size:192b/24B) */
28402 struct hwrm_ring_grp_alloc_input {
28403 /* The HWRM command request type. */
28406 * The completion ring to send the completion event on. This should
28407 * be the NQ ID returned from the `nq_alloc` HWRM command.
28409 uint16_t cmpl_ring;
28411 * The sequence ID is used by the driver for tracking multiple
28412 * commands. This ID is treated as opaque data by the firmware and
28413 * the value is returned in the `hwrm_resp_hdr` upon completion.
28417 * The target ID of the command:
28418 * * 0x0-0xFFF8 - The function ID
28419 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
28420 * * 0xFFFD - Reserved for user-space HWRM interface
28423 uint16_t target_id;
28425 * A physical address pointer pointing to a host buffer that the
28426 * command's response data will be written. This can be either a host
28427 * physical address (HPA) or a guest physical address (GPA) and must
28428 * point to a physically contiguous block of memory.
28430 uint64_t resp_addr;
28432 * This value identifies the CR associated with the ring
28437 * This value identifies the main RR associated with the ring
28442 * This value identifies the aggregation RR associated with
28443 * the ring group. If this value is 0xFF... (All Fs), then no
28444 * Aggregation ring will be set.
28448 * This value identifies the statistics context associated
28449 * with the ring group.
28454 /* hwrm_ring_grp_alloc_output (size:128b/16B) */
28455 struct hwrm_ring_grp_alloc_output {
28456 /* The specific error status for the command. */
28457 uint16_t error_code;
28458 /* The HWRM command request type. */
28460 /* The sequence ID from the original command. */
28462 /* The length of the response data in number of bytes. */
28465 * This is the ring group ID value. Use this value to program
28466 * the default ring group for the VNIC or as table entries
28467 * in an RSS/COS context.
28469 uint32_t ring_group_id;
28470 uint8_t unused_0[3];
28472 * This field is used in Output records to indicate that the output
28473 * is completely written to RAM. This field should be read as '1'
28474 * to indicate that the output has been completely written.
28475 * When writing a command completion or response to an internal processor,
28476 * the order of writes has to be such that this field is written last.
28481 /**********************
28482 * hwrm_ring_grp_free *
28483 **********************/
28486 /* hwrm_ring_grp_free_input (size:192b/24B) */
28487 struct hwrm_ring_grp_free_input {
28488 /* The HWRM command request type. */
28491 * The completion ring to send the completion event on. This should
28492 * be the NQ ID returned from the `nq_alloc` HWRM command.
28494 uint16_t cmpl_ring;
28496 * The sequence ID is used by the driver for tracking multiple
28497 * commands. This ID is treated as opaque data by the firmware and
28498 * the value is returned in the `hwrm_resp_hdr` upon completion.
28502 * The target ID of the command:
28503 * * 0x0-0xFFF8 - The function ID
28504 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
28505 * * 0xFFFD - Reserved for user-space HWRM interface
28508 uint16_t target_id;
28510 * A physical address pointer pointing to a host buffer that the
28511 * command's response data will be written. This can be either a host
28512 * physical address (HPA) or a guest physical address (GPA) and must
28513 * point to a physically contiguous block of memory.
28515 uint64_t resp_addr;
28516 /* This is the ring group ID value. */
28517 uint32_t ring_group_id;
28518 uint8_t unused_0[4];
28521 /* hwrm_ring_grp_free_output (size:128b/16B) */
28522 struct hwrm_ring_grp_free_output {
28523 /* The specific error status for the command. */
28524 uint16_t error_code;
28525 /* The HWRM command request type. */
28527 /* The sequence ID from the original command. */
28529 /* The length of the response data in number of bytes. */
28531 uint8_t unused_0[7];
28533 * This field is used in Output records to indicate that the output
28534 * is completely written to RAM. This field should be read as '1'
28535 * to indicate that the output has been completely written.
28536 * When writing a command completion or response to an internal processor,
28537 * the order of writes has to be such that this field is written last.
28542 /************************
28543 * hwrm_ring_schq_alloc *
28544 ************************/
28547 /* hwrm_ring_schq_alloc_input (size:1088b/136B) */
28548 struct hwrm_ring_schq_alloc_input {
28549 /* The HWRM command request type. */
28552 * The completion ring to send the completion event on. This should
28553 * be the NQ ID returned from the `nq_alloc` HWRM command.
28555 uint16_t cmpl_ring;
28557 * The sequence ID is used by the driver for tracking multiple
28558 * commands. This ID is treated as opaque data by the firmware and
28559 * the value is returned in the `hwrm_resp_hdr` upon completion.
28563 * The target ID of the command:
28564 * * 0x0-0xFFF8 - The function ID
28565 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
28566 * * 0xFFFD - Reserved for user-space HWRM interface
28569 uint16_t target_id;
28571 * A physical address pointer pointing to a host buffer that the
28572 * command's response data will be written. This can be either a host
28573 * physical address (HPA) or a guest physical address (GPA) and must
28574 * point to a physically contiguous block of memory.
28576 uint64_t resp_addr;
28579 * This bit must be '1' for the tqm_ring0 fields to be
28582 #define HWRM_RING_SCHQ_ALLOC_INPUT_ENABLES_TQM_RING0 UINT32_C(0x1)
28584 * This bit must be '1' for the tqm_ring1 fields to be
28587 #define HWRM_RING_SCHQ_ALLOC_INPUT_ENABLES_TQM_RING1 UINT32_C(0x2)
28589 * This bit must be '1' for the tqm_ring2 fields to be
28592 #define HWRM_RING_SCHQ_ALLOC_INPUT_ENABLES_TQM_RING2 UINT32_C(0x4)
28594 * This bit must be '1' for the tqm_ring3 fields to be
28597 #define HWRM_RING_SCHQ_ALLOC_INPUT_ENABLES_TQM_RING3 UINT32_C(0x8)
28599 * This bit must be '1' for the tqm_ring4 fields to be
28602 #define HWRM_RING_SCHQ_ALLOC_INPUT_ENABLES_TQM_RING4 UINT32_C(0x10)
28604 * This bit must be '1' for the tqm_ring5 fields to be
28607 #define HWRM_RING_SCHQ_ALLOC_INPUT_ENABLES_TQM_RING5 UINT32_C(0x20)
28609 * This bit must be '1' for the tqm_ring6 fields to be
28612 #define HWRM_RING_SCHQ_ALLOC_INPUT_ENABLES_TQM_RING6 UINT32_C(0x40)
28614 * This bit must be '1' for the tqm_ring7 fields to be
28617 #define HWRM_RING_SCHQ_ALLOC_INPUT_ENABLES_TQM_RING7 UINT32_C(0x80)
28618 /* Reserved for future use. */
28620 /* TQM ring 0 page size and level. */
28621 uint8_t tqm_ring0_pg_size_tqm_ring0_lvl;
28622 /* TQM ring 0 PBL indirect levels. */
28623 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING0_LVL_MASK \
28625 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING0_LVL_SFT 0
28626 /* PBL pointer is physical start address. */
28627 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING0_LVL_LVL_0 \
28629 /* PBL pointer points to PTE table. */
28630 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING0_LVL_LVL_1 \
28633 * PBL pointer points to PDE table with each entry pointing to PTE
28636 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING0_LVL_LVL_2 \
28638 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING0_LVL_LAST \
28639 HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING0_LVL_LVL_2
28640 /* TQM ring 0 page size. */
28641 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING0_PG_SIZE_MASK \
28643 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING0_PG_SIZE_SFT 4
28645 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING0_PG_SIZE_PG_4K \
28646 (UINT32_C(0x0) << 4)
28648 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING0_PG_SIZE_PG_8K \
28649 (UINT32_C(0x1) << 4)
28651 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING0_PG_SIZE_PG_64K \
28652 (UINT32_C(0x2) << 4)
28654 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING0_PG_SIZE_PG_2M \
28655 (UINT32_C(0x3) << 4)
28657 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING0_PG_SIZE_PG_8M \
28658 (UINT32_C(0x4) << 4)
28660 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING0_PG_SIZE_PG_1G \
28661 (UINT32_C(0x5) << 4)
28662 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING0_PG_SIZE_LAST \
28663 HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING0_PG_SIZE_PG_1G
28664 /* TQM ring 1 page size and level. */
28665 uint8_t tqm_ring1_pg_size_tqm_ring1_lvl;
28666 /* TQM ring 1 PBL indirect levels. */
28667 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING1_LVL_MASK \
28669 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING1_LVL_SFT 0
28670 /* PBL pointer is physical start address. */
28671 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING1_LVL_LVL_0 \
28673 /* PBL pointer points to PTE table. */
28674 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING1_LVL_LVL_1 \
28677 * PBL pointer points to PDE table with each entry pointing to PTE
28680 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING1_LVL_LVL_2 \
28682 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING1_LVL_LAST \
28683 HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING1_LVL_LVL_2
28684 /* TQM ring 1 page size. */
28685 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING1_PG_SIZE_MASK \
28687 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING1_PG_SIZE_SFT 4
28689 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING1_PG_SIZE_PG_4K \
28690 (UINT32_C(0x0) << 4)
28692 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING1_PG_SIZE_PG_8K \
28693 (UINT32_C(0x1) << 4)
28695 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING1_PG_SIZE_PG_64K \
28696 (UINT32_C(0x2) << 4)
28698 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING1_PG_SIZE_PG_2M \
28699 (UINT32_C(0x3) << 4)
28701 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING1_PG_SIZE_PG_8M \
28702 (UINT32_C(0x4) << 4)
28704 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING1_PG_SIZE_PG_1G \
28705 (UINT32_C(0x5) << 4)
28706 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING1_PG_SIZE_LAST \
28707 HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING1_PG_SIZE_PG_1G
28708 /* TQM ring 2 page size and level. */
28709 uint8_t tqm_ring2_pg_size_tqm_ring2_lvl;
28710 /* TQM ring 2 PBL indirect levels. */
28711 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING2_LVL_MASK \
28713 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING2_LVL_SFT 0
28714 /* PBL pointer is physical start address. */
28715 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING2_LVL_LVL_0 \
28717 /* PBL pointer points to PTE table. */
28718 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING2_LVL_LVL_1 \
28721 * PBL pointer points to PDE table with each entry pointing to PTE
28724 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING2_LVL_LVL_2 \
28726 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING2_LVL_LAST \
28727 HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING2_LVL_LVL_2
28728 /* TQM ring 2 page size. */
28729 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING2_PG_SIZE_MASK \
28731 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING2_PG_SIZE_SFT 4
28733 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING2_PG_SIZE_PG_4K \
28734 (UINT32_C(0x0) << 4)
28736 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING2_PG_SIZE_PG_8K \
28737 (UINT32_C(0x1) << 4)
28739 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING2_PG_SIZE_PG_64K \
28740 (UINT32_C(0x2) << 4)
28742 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING2_PG_SIZE_PG_2M \
28743 (UINT32_C(0x3) << 4)
28745 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING2_PG_SIZE_PG_8M \
28746 (UINT32_C(0x4) << 4)
28748 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING2_PG_SIZE_PG_1G \
28749 (UINT32_C(0x5) << 4)
28750 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING2_PG_SIZE_LAST \
28751 HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING2_PG_SIZE_PG_1G
28752 /* TQM ring 3 page size and level. */
28753 uint8_t tqm_ring3_pg_size_tqm_ring3_lvl;
28754 /* TQM ring 3 PBL indirect levels. */
28755 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING3_LVL_MASK \
28757 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING3_LVL_SFT 0
28758 /* PBL pointer is physical start address. */
28759 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING3_LVL_LVL_0 \
28761 /* PBL pointer points to PTE table. */
28762 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING3_LVL_LVL_1 \
28765 * PBL pointer points to PDE table with each entry pointing to PTE
28768 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING3_LVL_LVL_2 \
28770 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING3_LVL_LAST \
28771 HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING3_LVL_LVL_2
28772 /* TQM ring 3 page size. */
28773 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING3_PG_SIZE_MASK \
28775 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING3_PG_SIZE_SFT 4
28777 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING3_PG_SIZE_PG_4K \
28778 (UINT32_C(0x0) << 4)
28780 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING3_PG_SIZE_PG_8K \
28781 (UINT32_C(0x1) << 4)
28783 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING3_PG_SIZE_PG_64K \
28784 (UINT32_C(0x2) << 4)
28786 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING3_PG_SIZE_PG_2M \
28787 (UINT32_C(0x3) << 4)
28789 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING3_PG_SIZE_PG_8M \
28790 (UINT32_C(0x4) << 4)
28792 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING3_PG_SIZE_PG_1G \
28793 (UINT32_C(0x5) << 4)
28794 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING3_PG_SIZE_LAST \
28795 HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING3_PG_SIZE_PG_1G
28796 /* TQM ring 4 page size and level. */
28797 uint8_t tqm_ring4_pg_size_tqm_ring4_lvl;
28798 /* TQM ring 4 PBL indirect levels. */
28799 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING4_LVL_MASK \
28801 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING4_LVL_SFT 0
28802 /* PBL pointer is physical start address. */
28803 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING4_LVL_LVL_0 \
28805 /* PBL pointer points to PTE table. */
28806 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING4_LVL_LVL_1 \
28809 * PBL pointer points to PDE table with each entry pointing to PTE
28812 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING4_LVL_LVL_2 \
28814 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING4_LVL_LAST \
28815 HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING4_LVL_LVL_2
28816 /* TQM ring 4 page size. */
28817 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING4_PG_SIZE_MASK \
28819 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING4_PG_SIZE_SFT 4
28821 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING4_PG_SIZE_PG_4K \
28822 (UINT32_C(0x0) << 4)
28824 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING4_PG_SIZE_PG_8K \
28825 (UINT32_C(0x1) << 4)
28827 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING4_PG_SIZE_PG_64K \
28828 (UINT32_C(0x2) << 4)
28830 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING4_PG_SIZE_PG_2M \
28831 (UINT32_C(0x3) << 4)
28833 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING4_PG_SIZE_PG_8M \
28834 (UINT32_C(0x4) << 4)
28836 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING4_PG_SIZE_PG_1G \
28837 (UINT32_C(0x5) << 4)
28838 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING4_PG_SIZE_LAST \
28839 HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING4_PG_SIZE_PG_1G
28840 /* TQM ring 5 page size and level. */
28841 uint8_t tqm_ring5_pg_size_tqm_ring5_lvl;
28842 /* TQM ring 5 PBL indirect levels. */
28843 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING5_LVL_MASK \
28845 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING5_LVL_SFT 0
28846 /* PBL pointer is physical start address. */
28847 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING5_LVL_LVL_0 \
28849 /* PBL pointer points to PTE table. */
28850 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING5_LVL_LVL_1 \
28853 * PBL pointer points to PDE table with each entry pointing to PTE
28856 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING5_LVL_LVL_2 \
28858 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING5_LVL_LAST \
28859 HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING5_LVL_LVL_2
28860 /* TQM ring 5 page size. */
28861 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING5_PG_SIZE_MASK \
28863 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING5_PG_SIZE_SFT 4
28865 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING5_PG_SIZE_PG_4K \
28866 (UINT32_C(0x0) << 4)
28868 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING5_PG_SIZE_PG_8K \
28869 (UINT32_C(0x1) << 4)
28871 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING5_PG_SIZE_PG_64K \
28872 (UINT32_C(0x2) << 4)
28874 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING5_PG_SIZE_PG_2M \
28875 (UINT32_C(0x3) << 4)
28877 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING5_PG_SIZE_PG_8M \
28878 (UINT32_C(0x4) << 4)
28880 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING5_PG_SIZE_PG_1G \
28881 (UINT32_C(0x5) << 4)
28882 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING5_PG_SIZE_LAST \
28883 HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING5_PG_SIZE_PG_1G
28884 /* TQM ring 6 page size and level. */
28885 uint8_t tqm_ring6_pg_size_tqm_ring6_lvl;
28886 /* TQM ring 6 PBL indirect levels. */
28887 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING6_LVL_MASK \
28889 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING6_LVL_SFT 0
28890 /* PBL pointer is physical start address. */
28891 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING6_LVL_LVL_0 \
28893 /* PBL pointer points to PTE table. */
28894 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING6_LVL_LVL_1 \
28897 * PBL pointer points to PDE table with each entry pointing to PTE
28900 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING6_LVL_LVL_2 \
28902 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING6_LVL_LAST \
28903 HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING6_LVL_LVL_2
28904 /* TQM ring 6 page size. */
28905 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING6_PG_SIZE_MASK \
28907 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING6_PG_SIZE_SFT 4
28909 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING6_PG_SIZE_PG_4K \
28910 (UINT32_C(0x0) << 4)
28912 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING6_PG_SIZE_PG_8K \
28913 (UINT32_C(0x1) << 4)
28915 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING6_PG_SIZE_PG_64K \
28916 (UINT32_C(0x2) << 4)
28918 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING6_PG_SIZE_PG_2M \
28919 (UINT32_C(0x3) << 4)
28921 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING6_PG_SIZE_PG_8M \
28922 (UINT32_C(0x4) << 4)
28924 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING6_PG_SIZE_PG_1G \
28925 (UINT32_C(0x5) << 4)
28926 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING6_PG_SIZE_LAST \
28927 HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING6_PG_SIZE_PG_1G
28928 /* TQM ring 7 page size and level. */
28929 uint8_t tqm_ring7_pg_size_tqm_ring7_lvl;
28930 /* TQM ring 7 PBL indirect levels. */
28931 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING7_LVL_MASK \
28933 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING7_LVL_SFT 0
28934 /* PBL pointer is physical start address. */
28935 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING7_LVL_LVL_0 \
28937 /* PBL pointer points to PTE table. */
28938 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING7_LVL_LVL_1 \
28941 * PBL pointer points to PDE table with each entry pointing to PTE
28944 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING7_LVL_LVL_2 \
28946 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING7_LVL_LAST \
28947 HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING7_LVL_LVL_2
28948 /* TQM ring 7 page size. */
28949 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING7_PG_SIZE_MASK \
28951 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING7_PG_SIZE_SFT 4
28953 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING7_PG_SIZE_PG_4K \
28954 (UINT32_C(0x0) << 4)
28956 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING7_PG_SIZE_PG_8K \
28957 (UINT32_C(0x1) << 4)
28959 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING7_PG_SIZE_PG_64K \
28960 (UINT32_C(0x2) << 4)
28962 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING7_PG_SIZE_PG_2M \
28963 (UINT32_C(0x3) << 4)
28965 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING7_PG_SIZE_PG_8M \
28966 (UINT32_C(0x4) << 4)
28968 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING7_PG_SIZE_PG_1G \
28969 (UINT32_C(0x5) << 4)
28970 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING7_PG_SIZE_LAST \
28971 HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING7_PG_SIZE_PG_1G
28972 /* TQM ring 0 page directory. */
28973 uint64_t tqm_ring0_page_dir;
28974 /* TQM ring 1 page directory. */
28975 uint64_t tqm_ring1_page_dir;
28976 /* TQM ring 2 page directory. */
28977 uint64_t tqm_ring2_page_dir;
28978 /* TQM ring 3 page directory. */
28979 uint64_t tqm_ring3_page_dir;
28980 /* TQM ring 4 page directory. */
28981 uint64_t tqm_ring4_page_dir;
28982 /* TQM ring 5 page directory. */
28983 uint64_t tqm_ring5_page_dir;
28984 /* TQM ring 6 page directory. */
28985 uint64_t tqm_ring6_page_dir;
28986 /* TQM ring 7 page directory. */
28987 uint64_t tqm_ring7_page_dir;
28989 * Number of TQM ring 0 entries.
28991 * TQM fastpath rings should be sized large enough to accommodate the
28992 * maximum number of QPs (either L2 or RoCE, or both if shared)
28993 * that can be enqueued to the TQM ring.
28995 * Note that TQM ring sizes cannot be extended while the system is
28996 * operational. If a PF driver needs to extend a TQM ring, it needs
28997 * to delete the SCHQ and then reallocate it.
28999 uint32_t tqm_ring0_num_entries;
29001 * Number of TQM ring 1 entries.
29003 * TQM fastpath rings should be sized large enough to accommodate the
29004 * maximum number of QPs (either L2 or RoCE, or both if shared)
29005 * that can be enqueued to the TQM ring.
29007 * Note that TQM ring sizes cannot be extended while the system is
29008 * operational. If a PF driver needs to extend a TQM ring, it needs
29009 * to delete the SCHQ and then reallocate it.
29011 uint32_t tqm_ring1_num_entries;
29013 * Number of TQM ring 2 entries.
29015 * TQM fastpath rings should be sized large enough to accommodate the
29016 * maximum number of QPs (either L2 or RoCE, or both if shared)
29017 * that can be enqueued to the TQM ring.
29019 * Note that TQM ring sizes cannot be extended while the system is
29020 * operational. If a PF driver needs to extend a TQM ring, it needs
29021 * to delete the SCHQ and then reallocate it.
29023 uint32_t tqm_ring2_num_entries;
29025 * Number of TQM ring 3 entries.
29027 * TQM fastpath rings should be sized large enough to accommodate the
29028 * maximum number of QPs (either L2 or RoCE, or both if shared)
29029 * that can be enqueued to the TQM ring.
29031 * Note that TQM ring sizes cannot be extended while the system is
29032 * operational. If a PF driver needs to extend a TQM ring, it needs
29033 * to delete the SCHQ and then reallocate it.
29035 uint32_t tqm_ring3_num_entries;
29037 * Number of TQM ring 4 entries.
29039 * TQM fastpath rings should be sized large enough to accommodate the
29040 * maximum number of QPs (either L2 or RoCE, or both if shared)
29041 * that can be enqueued to the TQM ring.
29043 * Note that TQM ring sizes cannot be extended while the system is
29044 * operational. If a PF driver needs to extend a TQM ring, it needs
29045 * to delete the SCHQ and then reallocate it.
29047 uint32_t tqm_ring4_num_entries;
29049 * Number of TQM ring 5 entries.
29051 * TQM fastpath rings should be sized large enough to accommodate the
29052 * maximum number of QPs (either L2 or RoCE, or both if shared)
29053 * that can be enqueued to the TQM ring.
29055 * Note that TQM ring sizes cannot be extended while the system is
29056 * operational. If a PF driver needs to extend a TQM ring, it needs
29057 * to delete the SCHQ and then reallocate it.
29059 uint32_t tqm_ring5_num_entries;
29061 * Number of TQM ring 6 entries.
29063 * TQM fastpath rings should be sized large enough to accommodate the
29064 * maximum number of QPs (either L2 or RoCE, or both if shared)
29065 * that can be enqueued to the TQM ring.
29067 * Note that TQM ring sizes cannot be extended while the system is
29068 * operational. If a PF driver needs to extend a TQM ring, it needs
29069 * to delete the SCHQ and then reallocate it.
29071 uint32_t tqm_ring6_num_entries;
29073 * Number of TQM ring 7 entries.
29075 * TQM fastpath rings should be sized large enough to accommodate the
29076 * maximum number of QPs (either L2 or RoCE, or both if shared)
29077 * that can be enqueued to the TQM ring.
29079 * Note that TQM ring sizes cannot be extended while the system is
29080 * operational. If a PF driver needs to extend a TQM ring, it needs
29081 * to delete the SCHQ and then reallocate it.
29083 uint32_t tqm_ring7_num_entries;
29084 /* Number of bytes that have been allocated for each context entry. */
29085 uint16_t tqm_entry_size;
29086 uint8_t unused_0[6];
29089 /* hwrm_ring_schq_alloc_output (size:128b/16B) */
29090 struct hwrm_ring_schq_alloc_output {
29091 /* The specific error status for the command. */
29092 uint16_t error_code;
29093 /* The HWRM command request type. */
29095 /* The sequence ID from the original command. */
29097 /* The length of the response data in number of bytes. */
29100 * This is an identifier for the SCHQ to be used in other HWRM commands
29101 * that need to reference this SCHQ. This value is greater than zero
29102 * (i.e. a schq_id of zero references the default SCHQ).
29105 uint8_t unused_0[5];
29107 * This field is used in Output records to indicate that the output
29108 * is completely written to RAM. This field should be read as '1'
29109 * to indicate that the output has been completely written.
29110 * When writing a command completion or response to an internal processor,
29111 * the order of writes has to be such that this field is written last.
29116 /**********************
29117 * hwrm_ring_schq_cfg *
29118 **********************/
29121 /* hwrm_ring_schq_cfg_input (size:768b/96B) */
29122 struct hwrm_ring_schq_cfg_input {
29123 /* The HWRM command request type. */
29126 * The completion ring to send the completion event on. This should
29127 * be the NQ ID returned from the `nq_alloc` HWRM command.
29129 uint16_t cmpl_ring;
29131 * The sequence ID is used by the driver for tracking multiple
29132 * commands. This ID is treated as opaque data by the firmware and
29133 * the value is returned in the `hwrm_resp_hdr` upon completion.
29137 * The target ID of the command:
29138 * * 0x0-0xFFF8 - The function ID
29139 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
29140 * * 0xFFFD - Reserved for user-space HWRM interface
29143 uint16_t target_id;
29145 * A physical address pointer pointing to a host buffer that the
29146 * command's response data will be written. This can be either a host
29147 * physical address (HPA) or a guest physical address (GPA) and must
29148 * point to a physically contiguous block of memory.
29150 uint64_t resp_addr;
29152 * Identifies the SCHQ being configured. A schq_id of zero refers to
29153 * the default SCHQ.
29157 * This field is an 8 bit bitmap that indicates which TCs are enabled
29158 * in this SCHQ. Bit 0 represents traffic class 0 and bit 7 represents
29161 uint8_t tc_enabled;
29164 /* The tc_max_bw array and the max_bw parameters are valid */
29165 #define HWRM_RING_SCHQ_CFG_INPUT_FLAGS_TC_MAX_BW_ENABLED \
29167 /* The tc_min_bw array is valid */
29168 #define HWRM_RING_SCHQ_CFG_INPUT_FLAGS_TC_MIN_BW_ENABLED \
29170 /* Maximum bandwidth of the traffic class, specified in Mbps. */
29171 uint32_t max_bw_tc0;
29172 /* Maximum bandwidth of the traffic class, specified in Mbps. */
29173 uint32_t max_bw_tc1;
29174 /* Maximum bandwidth of the traffic class, specified in Mbps. */
29175 uint32_t max_bw_tc2;
29176 /* Maximum bandwidth of the traffic class, specified in Mbps. */
29177 uint32_t max_bw_tc3;
29178 /* Maximum bandwidth of the traffic class, specified in Mbps. */
29179 uint32_t max_bw_tc4;
29180 /* Maximum bandwidth of the traffic class, specified in Mbps. */
29181 uint32_t max_bw_tc5;
29182 /* Maximum bandwidth of the traffic class, specified in Mbps. */
29183 uint32_t max_bw_tc6;
29184 /* Maximum bandwidth of the traffic class, specified in Mbps. */
29185 uint32_t max_bw_tc7;
29187 * Bandwidth reservation for the traffic class, specified in Mbps.
29188 * A value of zero signifies that traffic belonging to this class
29189 * shares the bandwidth reservation for the same traffic class of
29190 * the default SCHQ.
29192 uint32_t min_bw_tc0;
29194 * Bandwidth reservation for the traffic class, specified in Mbps.
29195 * A value of zero signifies that traffic belonging to this class
29196 * shares the bandwidth reservation for the same traffic class of
29197 * the default SCHQ.
29199 uint32_t min_bw_tc1;
29201 * Bandwidth reservation for the traffic class, specified in Mbps.
29202 * A value of zero signifies that traffic belonging to this class
29203 * shares the bandwidth reservation for the same traffic class of
29204 * the default SCHQ.
29206 uint32_t min_bw_tc2;
29208 * Bandwidth reservation for the traffic class, specified in Mbps.
29209 * A value of zero signifies that traffic belonging to this class
29210 * shares the bandwidth reservation for the same traffic class of
29211 * the default SCHQ.
29213 uint32_t min_bw_tc3;
29215 * Bandwidth reservation for the traffic class, specified in Mbps.
29216 * A value of zero signifies that traffic belonging to this class
29217 * shares the bandwidth reservation for the same traffic class of
29218 * the default SCHQ.
29220 uint32_t min_bw_tc4;
29222 * Bandwidth reservation for the traffic class, specified in Mbps.
29223 * A value of zero signifies that traffic belonging to this class
29224 * shares the bandwidth reservation for the same traffic class of
29225 * the default SCHQ.
29227 uint32_t min_bw_tc5;
29229 * Bandwidth reservation for the traffic class, specified in Mbps.
29230 * A value of zero signifies that traffic belonging to this class
29231 * shares the bandwidth reservation for the same traffic class of
29232 * the default SCHQ.
29234 uint32_t min_bw_tc6;
29236 * Bandwidth reservation for the traffic class, specified in Mbps.
29237 * A value of zero signifies that traffic belonging to this class
29238 * shares the bandwidth reservation for the same traffic class of
29239 * the default SCHQ.
29241 uint32_t min_bw_tc7;
29243 * Indicates the max bandwidth for all enabled traffic classes in
29244 * this SCHQ, specified in Mbps.
29247 uint8_t unused_1[4];
29250 /* hwrm_ring_schq_cfg_output (size:128b/16B) */
29251 struct hwrm_ring_schq_cfg_output {
29252 /* The specific error status for the command. */
29253 uint16_t error_code;
29254 /* The HWRM command request type. */
29256 /* The sequence ID from the original command. */
29258 /* The length of the response data in number of bytes. */
29260 uint8_t unused_0[7];
29262 * This field is used in Output records to indicate that the output
29263 * is completely written to RAM. This field should be read as '1'
29264 * to indicate that the output has been completely written.
29265 * When writing a command completion or response to an internal processor,
29266 * the order of writes has to be such that this field is written last.
29271 /***********************
29272 * hwrm_ring_schq_free *
29273 ***********************/
29276 /* hwrm_ring_schq_free_input (size:192b/24B) */
29277 struct hwrm_ring_schq_free_input {
29278 /* The HWRM command request type. */
29281 * The completion ring to send the completion event on. This should
29282 * be the NQ ID returned from the `nq_alloc` HWRM command.
29284 uint16_t cmpl_ring;
29286 * The sequence ID is used by the driver for tracking multiple
29287 * commands. This ID is treated as opaque data by the firmware and
29288 * the value is returned in the `hwrm_resp_hdr` upon completion.
29292 * The target ID of the command:
29293 * * 0x0-0xFFF8 - The function ID
29294 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
29295 * * 0xFFFD - Reserved for user-space HWRM interface
29298 uint16_t target_id;
29300 * A physical address pointer pointing to a host buffer that the
29301 * command's response data will be written. This can be either a host
29302 * physical address (HPA) or a guest physical address (GPA) and must
29303 * point to a physically contiguous block of memory.
29305 uint64_t resp_addr;
29306 /* Identifies the SCHQ being freed. */
29308 uint8_t unused_0[6];
29311 /* hwrm_ring_schq_free_output (size:128b/16B) */
29312 struct hwrm_ring_schq_free_output {
29313 /* The specific error status for the command. */
29314 uint16_t error_code;
29315 /* The HWRM command request type. */
29317 /* The sequence ID from the original command. */
29319 /* The length of the response data in number of bytes. */
29321 uint8_t unused_0[7];
29323 * This field is used in Output records to indicate that the output
29324 * is completely written to RAM. This field should be read as '1'
29325 * to indicate that the output has been completely written.
29326 * When writing a command completion or response to an internal processor,
29327 * the order of writes has to be such that this field is written last.
29332 * special reserved flow ID to identify per function default
29333 * flows for vSwitch offload
29335 #define DEFAULT_FLOW_ID 0xFFFFFFFFUL
29337 * special reserved flow ID to identify per function RoCEv1
29340 #define ROCEV1_FLOW_ID 0xFFFFFFFEUL
29342 * special reserved flow ID to identify per function RoCEv2
29345 #define ROCEV2_FLOW_ID 0xFFFFFFFDUL
29347 * special reserved flow ID to identify per function RoCEv2
29350 #define ROCEV2_CNP_FLOW_ID 0xFFFFFFFCUL
29352 /****************************
29353 * hwrm_cfa_l2_filter_alloc *
29354 ****************************/
29357 /* hwrm_cfa_l2_filter_alloc_input (size:768b/96B) */
29358 struct hwrm_cfa_l2_filter_alloc_input {
29359 /* The HWRM command request type. */
29362 * The completion ring to send the completion event on. This should
29363 * be the NQ ID returned from the `nq_alloc` HWRM command.
29365 uint16_t cmpl_ring;
29367 * The sequence ID is used by the driver for tracking multiple
29368 * commands. This ID is treated as opaque data by the firmware and
29369 * the value is returned in the `hwrm_resp_hdr` upon completion.
29373 * The target ID of the command:
29374 * * 0x0-0xFFF8 - The function ID
29375 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
29376 * * 0xFFFD - Reserved for user-space HWRM interface
29379 uint16_t target_id;
29381 * A physical address pointer pointing to a host buffer that the
29382 * command's response data will be written. This can be either a host
29383 * physical address (HPA) or a guest physical address (GPA) and must
29384 * point to a physically contiguous block of memory.
29386 uint64_t resp_addr;
29389 * Enumeration denoting the RX, TX type of the resource.
29390 * This enumeration is used for resources that are similar for both
29391 * TX and RX paths of the chip.
29393 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_PATH \
29396 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_PATH_TX \
29399 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_PATH_RX \
29401 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_PATH_LAST \
29402 HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_PATH_RX
29403 /* Setting of this flag indicates the applicability to the loopback path. */
29404 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_LOOPBACK \
29407 * Setting of this flag indicates drop action. If this flag is not set,
29408 * then it should be considered accept action.
29410 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_DROP \
29413 * If this flag is set, all t_l2_* fields are invalid
29414 * and they should not be specified.
29415 * If this flag is set, then l2_* fields refer to
29416 * fields of outermost L2 header.
29418 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_OUTERMOST \
29421 * Enumeration denoting NO_ROCE_L2 to support old drivers.
29422 * New driver L2 for only L2 traffic, ROCE for roce and l2 traffic
29424 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_TRAFFIC_MASK \
29426 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_TRAFFIC_SFT 4
29427 /* To support old drivers */
29428 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_TRAFFIC_NO_ROCE_L2 \
29429 (UINT32_C(0x0) << 4)
29430 /* Only L2 traffic */
29431 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_TRAFFIC_L2 \
29432 (UINT32_C(0x1) << 4)
29433 /* Roce & L2 traffic */
29434 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_TRAFFIC_ROCE \
29435 (UINT32_C(0x2) << 4)
29436 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_TRAFFIC_LAST \
29437 HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_TRAFFIC_ROCE
29439 * Setting of this flag indicates that no XDP filter is created with
29441 * 0 - legacy behavior, XDP filter is created with L2 filter
29442 * 1 - XDP filter won't be created with L2 filter
29444 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_XDP_DISABLE \
29447 * Setting this flag to 1 indicate the L2 fields in this command
29448 * pertain to source fields. Setting this flag to 0 indicate the
29449 * L2 fields in this command pertain to the destination fields
29450 * and this is the default/legacy behavior.
29452 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_SOURCE_VALID \
29456 * This bit must be '1' for the l2_addr field to be
29459 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_ADDR \
29462 * This bit must be '1' for the l2_addr_mask field to be
29465 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_ADDR_MASK \
29468 * This bit must be '1' for the l2_ovlan field to be
29471 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_OVLAN \
29474 * This bit must be '1' for the l2_ovlan_mask field to be
29477 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_OVLAN_MASK \
29480 * This bit must be '1' for the l2_ivlan field to be
29483 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN \
29486 * This bit must be '1' for the l2_ivlan_mask field to be
29489 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN_MASK \
29492 * This bit must be '1' for the t_l2_addr field to be
29495 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_T_L2_ADDR \
29498 * This bit must be '1' for the t_l2_addr_mask field to be
29501 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_T_L2_ADDR_MASK \
29504 * This bit must be '1' for the t_l2_ovlan field to be
29507 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_T_L2_OVLAN \
29510 * This bit must be '1' for the t_l2_ovlan_mask field to be
29513 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_T_L2_OVLAN_MASK \
29516 * This bit must be '1' for the t_l2_ivlan field to be
29519 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_T_L2_IVLAN \
29522 * This bit must be '1' for the t_l2_ivlan_mask field to be
29525 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_T_L2_IVLAN_MASK \
29528 * This bit must be '1' for the src_type field to be
29531 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_SRC_TYPE \
29534 * This bit must be '1' for the src_id field to be
29537 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_SRC_ID \
29540 * This bit must be '1' for the tunnel_type field to be
29543 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_TUNNEL_TYPE \
29546 * This bit must be '1' for the dst_id field to be
29549 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_DST_ID \
29552 * This bit must be '1' for the mirror_vnic_id field to be
29555 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_MIRROR_VNIC_ID \
29558 * This bit must be '1' for the num_vlans field to be
29561 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_NUM_VLANS \
29564 * This bit must be '1' for the t_num_vlans field to be
29567 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_T_NUM_VLANS \
29570 * This value sets the match value for the L2 MAC address.
29571 * Destination MAC address for RX path.
29572 * Source MAC address for TX path.
29574 uint8_t l2_addr[6];
29575 /* This value sets the match value for the number of VLANs. */
29578 * This value sets the match value for the number of VLANs
29579 * in the tunnel headers.
29581 uint8_t t_num_vlans;
29583 * This value sets the mask value for the L2 address.
29584 * A value of 0 will mask the corresponding bit from
29587 uint8_t l2_addr_mask[6];
29588 /* This value sets VLAN ID value for outer VLAN. */
29591 * This value sets the mask value for the ovlan id.
29592 * A value of 0 will mask the corresponding bit from
29595 uint16_t l2_ovlan_mask;
29596 /* This value sets VLAN ID value for inner VLAN. */
29599 * This value sets the mask value for the ivlan id.
29600 * A value of 0 will mask the corresponding bit from
29603 uint16_t l2_ivlan_mask;
29604 uint8_t unused_1[2];
29606 * This value sets the match value for the tunnel
29608 * Destination MAC address for RX path.
29609 * Source MAC address for TX path.
29611 uint8_t t_l2_addr[6];
29612 uint8_t unused_2[2];
29614 * This value sets the mask value for the tunnel L2
29616 * A value of 0 will mask the corresponding bit from
29619 uint8_t t_l2_addr_mask[6];
29620 /* This value sets VLAN ID value for tunnel outer VLAN. */
29621 uint16_t t_l2_ovlan;
29623 * This value sets the mask value for the tunnel ovlan id.
29624 * A value of 0 will mask the corresponding bit from
29627 uint16_t t_l2_ovlan_mask;
29628 /* This value sets VLAN ID value for tunnel inner VLAN. */
29629 uint16_t t_l2_ivlan;
29631 * This value sets the mask value for the tunnel ivlan id.
29632 * A value of 0 will mask the corresponding bit from
29635 uint16_t t_l2_ivlan_mask;
29636 /* This value identifies the type of source of the packet. */
29639 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_SRC_TYPE_NPORT UINT32_C(0x0)
29640 /* Physical function */
29641 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_SRC_TYPE_PF UINT32_C(0x1)
29642 /* Virtual function */
29643 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_SRC_TYPE_VF UINT32_C(0x2)
29644 /* Virtual NIC of a function */
29645 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_SRC_TYPE_VNIC UINT32_C(0x3)
29646 /* Embedded processor for CFA management */
29647 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_SRC_TYPE_KONG UINT32_C(0x4)
29648 /* Embedded processor for OOB management */
29649 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_SRC_TYPE_APE UINT32_C(0x5)
29650 /* Embedded processor for RoCE */
29651 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_SRC_TYPE_BONO UINT32_C(0x6)
29652 /* Embedded processor for network proxy functions */
29653 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_SRC_TYPE_TANG UINT32_C(0x7)
29654 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_SRC_TYPE_LAST \
29655 HWRM_CFA_L2_FILTER_ALLOC_INPUT_SRC_TYPE_TANG
29658 * This value is the id of the source.
29659 * For a network port, it represents port_id.
29660 * For a physical function, it represents fid.
29661 * For a virtual function, it represents vf_id.
29662 * For a vnic, it represents vnic_id.
29663 * For embedded processors, this id is not valid.
29666 * 1. The function ID is implied if it src_id is
29667 * not provided for a src_type that is either
29671 uint8_t tunnel_type;
29673 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_TUNNEL_TYPE_NONTUNNEL \
29675 /* Virtual eXtensible Local Area Network (VXLAN) */
29676 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_TUNNEL_TYPE_VXLAN \
29678 /* Network Virtualization Generic Routing Encapsulation (NVGRE) */
29679 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_TUNNEL_TYPE_NVGRE \
29681 /* Generic Routing Encapsulation (GRE) inside Ethernet payload */
29682 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_TUNNEL_TYPE_L2GRE \
29685 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_TUNNEL_TYPE_IPIP \
29687 /* Generic Network Virtualization Encapsulation (Geneve) */
29688 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_TUNNEL_TYPE_GENEVE \
29690 /* Multi-Protocol Label Switching (MPLS) */
29691 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_TUNNEL_TYPE_MPLS \
29693 /* Stateless Transport Tunnel (STT) */
29694 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_TUNNEL_TYPE_STT \
29696 /* Generic Routing Encapsulation (GRE) inside IP datagram payload */
29697 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_TUNNEL_TYPE_IPGRE \
29699 /* IPV4 over virtual eXtensible Local Area Network (IPV4oVXLAN) */
29700 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_TUNNEL_TYPE_VXLAN_V4 \
29702 /* Enhance Generic Routing Encapsulation (GRE version 1) inside IP datagram payload */
29703 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_TUNNEL_TYPE_IPGRE_V1 \
29705 /* Use fixed layer 2 ether type of 0xFFFF */
29706 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_TUNNEL_TYPE_L2_ETYPE \
29708 /* IPV6 over virtual eXtensible Local Area Network with GPE header (IPV6oVXLANGPE) */
29709 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_TUNNEL_TYPE_VXLAN_GPE_V6 \
29711 /* Any tunneled traffic */
29712 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_TUNNEL_TYPE_ANYTUNNEL \
29714 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_TUNNEL_TYPE_LAST \
29715 HWRM_CFA_L2_FILTER_ALLOC_INPUT_TUNNEL_TYPE_ANYTUNNEL
29718 * If set, this value shall represent the
29719 * Logical VNIC ID of the destination VNIC for the RX
29720 * path and network port id of the destination port for
29725 * Logical VNIC ID of the VNIC where traffic is
29728 uint16_t mirror_vnic_id;
29730 * This hint is provided to help in placing
29731 * the filter in the filter table.
29734 /* No preference */
29735 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_PRI_HINT_NO_PREFER \
29737 /* Above the given filter */
29738 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_PRI_HINT_ABOVE_FILTER \
29740 /* Below the given filter */
29741 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_PRI_HINT_BELOW_FILTER \
29743 /* As high as possible */
29744 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_PRI_HINT_MAX \
29746 /* As low as possible */
29747 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_PRI_HINT_MIN \
29749 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_PRI_HINT_LAST \
29750 HWRM_CFA_L2_FILTER_ALLOC_INPUT_PRI_HINT_MIN
29754 * This is the ID of the filter that goes along with
29757 * This field is valid only for the following values.
29758 * 1 - Above the given filter
29759 * 2 - Below the given filter
29761 uint64_t l2_filter_id_hint;
29764 /* hwrm_cfa_l2_filter_alloc_output (size:192b/24B) */
29765 struct hwrm_cfa_l2_filter_alloc_output {
29766 /* The specific error status for the command. */
29767 uint16_t error_code;
29768 /* The HWRM command request type. */
29770 /* The sequence ID from the original command. */
29772 /* The length of the response data in number of bytes. */
29775 * This value identifies a set of CFA data structures used for an L2
29778 uint64_t l2_filter_id;
29780 * The flow id value in bit 0-29 is the actual ID of the flow
29781 * associated with this filter and it shall be used to match
29782 * and associate the flow identifier returned in completion
29783 * records. A value of 0xFFFFFFFF in the 32-bit flow_id field
29784 * shall indicate no valid flow id.
29787 /* Indicate the flow id value. */
29788 #define HWRM_CFA_L2_FILTER_ALLOC_OUTPUT_FLOW_ID_VALUE_MASK \
29789 UINT32_C(0x3fffffff)
29790 #define HWRM_CFA_L2_FILTER_ALLOC_OUTPUT_FLOW_ID_VALUE_SFT 0
29791 /* Indicate type of the flow. */
29792 #define HWRM_CFA_L2_FILTER_ALLOC_OUTPUT_FLOW_ID_TYPE \
29793 UINT32_C(0x40000000)
29795 * If this bit set to 0, then it indicates that the flow is
29798 #define HWRM_CFA_L2_FILTER_ALLOC_OUTPUT_FLOW_ID_TYPE_INT \
29799 (UINT32_C(0x0) << 30)
29801 * If this bit is set to 1, then it indicates that the flow is
29804 #define HWRM_CFA_L2_FILTER_ALLOC_OUTPUT_FLOW_ID_TYPE_EXT \
29805 (UINT32_C(0x1) << 30)
29806 #define HWRM_CFA_L2_FILTER_ALLOC_OUTPUT_FLOW_ID_TYPE_LAST \
29807 HWRM_CFA_L2_FILTER_ALLOC_OUTPUT_FLOW_ID_TYPE_EXT
29808 /* Indicate the flow direction. */
29809 #define HWRM_CFA_L2_FILTER_ALLOC_OUTPUT_FLOW_ID_DIR \
29810 UINT32_C(0x80000000)
29811 /* If this bit set to 0, then it indicates rx flow. */
29812 #define HWRM_CFA_L2_FILTER_ALLOC_OUTPUT_FLOW_ID_DIR_RX \
29813 (UINT32_C(0x0) << 31)
29814 /* If this bit is set to 1, then it indicates that tx flow. */
29815 #define HWRM_CFA_L2_FILTER_ALLOC_OUTPUT_FLOW_ID_DIR_TX \
29816 (UINT32_C(0x1) << 31)
29817 #define HWRM_CFA_L2_FILTER_ALLOC_OUTPUT_FLOW_ID_DIR_LAST \
29818 HWRM_CFA_L2_FILTER_ALLOC_OUTPUT_FLOW_ID_DIR_TX
29819 uint8_t unused_0[3];
29821 * This field is used in Output records to indicate that the output
29822 * is completely written to RAM. This field should be read as '1'
29823 * to indicate that the output has been completely written.
29824 * When writing a command completion or response to an internal processor,
29825 * the order of writes has to be such that this field is written last.
29830 /***************************
29831 * hwrm_cfa_l2_filter_free *
29832 ***************************/
29835 /* hwrm_cfa_l2_filter_free_input (size:192b/24B) */
29836 struct hwrm_cfa_l2_filter_free_input {
29837 /* The HWRM command request type. */
29840 * The completion ring to send the completion event on. This should
29841 * be the NQ ID returned from the `nq_alloc` HWRM command.
29843 uint16_t cmpl_ring;
29845 * The sequence ID is used by the driver for tracking multiple
29846 * commands. This ID is treated as opaque data by the firmware and
29847 * the value is returned in the `hwrm_resp_hdr` upon completion.
29851 * The target ID of the command:
29852 * * 0x0-0xFFF8 - The function ID
29853 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
29854 * * 0xFFFD - Reserved for user-space HWRM interface
29857 uint16_t target_id;
29859 * A physical address pointer pointing to a host buffer that the
29860 * command's response data will be written. This can be either a host
29861 * physical address (HPA) or a guest physical address (GPA) and must
29862 * point to a physically contiguous block of memory.
29864 uint64_t resp_addr;
29866 * This value identifies a set of CFA data structures used for an L2
29869 uint64_t l2_filter_id;
29872 /* hwrm_cfa_l2_filter_free_output (size:128b/16B) */
29873 struct hwrm_cfa_l2_filter_free_output {
29874 /* The specific error status for the command. */
29875 uint16_t error_code;
29876 /* The HWRM command request type. */
29878 /* The sequence ID from the original command. */
29880 /* The length of the response data in number of bytes. */
29882 uint8_t unused_0[7];
29884 * This field is used in Output records to indicate that the output
29885 * is completely written to RAM. This field should be read as '1'
29886 * to indicate that the output has been completely written.
29887 * When writing a command completion or response to an internal processor,
29888 * the order of writes has to be such that this field is written last.
29893 /**************************
29894 * hwrm_cfa_l2_filter_cfg *
29895 **************************/
29898 /* hwrm_cfa_l2_filter_cfg_input (size:320b/40B) */
29899 struct hwrm_cfa_l2_filter_cfg_input {
29900 /* The HWRM command request type. */
29903 * The completion ring to send the completion event on. This should
29904 * be the NQ ID returned from the `nq_alloc` HWRM command.
29906 uint16_t cmpl_ring;
29908 * The sequence ID is used by the driver for tracking multiple
29909 * commands. This ID is treated as opaque data by the firmware and
29910 * the value is returned in the `hwrm_resp_hdr` upon completion.
29914 * The target ID of the command:
29915 * * 0x0-0xFFF8 - The function ID
29916 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
29917 * * 0xFFFD - Reserved for user-space HWRM interface
29920 uint16_t target_id;
29922 * A physical address pointer pointing to a host buffer that the
29923 * command's response data will be written. This can be either a host
29924 * physical address (HPA) or a guest physical address (GPA) and must
29925 * point to a physically contiguous block of memory.
29927 uint64_t resp_addr;
29930 * Enumeration denoting the RX, TX type of the resource.
29931 * This enumeration is used for resources that are similar for both
29932 * TX and RX paths of the chip.
29934 #define HWRM_CFA_L2_FILTER_CFG_INPUT_FLAGS_PATH \
29937 #define HWRM_CFA_L2_FILTER_CFG_INPUT_FLAGS_PATH_TX \
29940 #define HWRM_CFA_L2_FILTER_CFG_INPUT_FLAGS_PATH_RX \
29942 #define HWRM_CFA_L2_FILTER_CFG_INPUT_FLAGS_PATH_LAST \
29943 HWRM_CFA_L2_FILTER_CFG_INPUT_FLAGS_PATH_RX
29945 * Setting of this flag indicates drop action. If this flag is not set,
29946 * then it should be considered accept action.
29948 #define HWRM_CFA_L2_FILTER_CFG_INPUT_FLAGS_DROP \
29951 * Enumeration denoting NO_ROCE_L2 to support old drivers.
29952 * New driver L2 for only L2 traffic, ROCE for roce and l2 traffic
29954 #define HWRM_CFA_L2_FILTER_CFG_INPUT_FLAGS_TRAFFIC_MASK \
29956 #define HWRM_CFA_L2_FILTER_CFG_INPUT_FLAGS_TRAFFIC_SFT 2
29957 /* To support old drivers */
29958 #define HWRM_CFA_L2_FILTER_CFG_INPUT_FLAGS_TRAFFIC_NO_ROCE_L2 \
29959 (UINT32_C(0x0) << 2)
29960 /* Only L2 traffic */
29961 #define HWRM_CFA_L2_FILTER_CFG_INPUT_FLAGS_TRAFFIC_L2 \
29962 (UINT32_C(0x1) << 2)
29963 /* Roce & L2 traffic */
29964 #define HWRM_CFA_L2_FILTER_CFG_INPUT_FLAGS_TRAFFIC_ROCE \
29965 (UINT32_C(0x2) << 2)
29966 #define HWRM_CFA_L2_FILTER_CFG_INPUT_FLAGS_TRAFFIC_LAST \
29967 HWRM_CFA_L2_FILTER_CFG_INPUT_FLAGS_TRAFFIC_ROCE
29970 * This bit must be '1' for the dst_id field to be
29973 #define HWRM_CFA_L2_FILTER_CFG_INPUT_ENABLES_DST_ID \
29976 * This bit must be '1' for the new_mirror_vnic_id field to be
29979 #define HWRM_CFA_L2_FILTER_CFG_INPUT_ENABLES_NEW_MIRROR_VNIC_ID \
29982 * This value identifies a set of CFA data structures used for an L2
29985 uint64_t l2_filter_id;
29987 * If set, this value shall represent the
29988 * Logical VNIC ID of the destination VNIC for the RX
29989 * path and network port id of the destination port for
29994 * New Logical VNIC ID of the VNIC where traffic is
29997 uint32_t new_mirror_vnic_id;
30000 /* hwrm_cfa_l2_filter_cfg_output (size:128b/16B) */
30001 struct hwrm_cfa_l2_filter_cfg_output {
30002 /* The specific error status for the command. */
30003 uint16_t error_code;
30004 /* The HWRM command request type. */
30006 /* The sequence ID from the original command. */
30008 /* The length of the response data in number of bytes. */
30010 uint8_t unused_0[7];
30012 * This field is used in Output records to indicate that the output
30013 * is completely written to RAM. This field should be read as '1'
30014 * to indicate that the output has been completely written.
30015 * When writing a command completion or response to an internal processor,
30016 * the order of writes has to be such that this field is written last.
30021 /***************************
30022 * hwrm_cfa_l2_set_rx_mask *
30023 ***************************/
30026 /* hwrm_cfa_l2_set_rx_mask_input (size:448b/56B) */
30027 struct hwrm_cfa_l2_set_rx_mask_input {
30028 /* The HWRM command request type. */
30031 * The completion ring to send the completion event on. This should
30032 * be the NQ ID returned from the `nq_alloc` HWRM command.
30034 uint16_t cmpl_ring;
30036 * The sequence ID is used by the driver for tracking multiple
30037 * commands. This ID is treated as opaque data by the firmware and
30038 * the value is returned in the `hwrm_resp_hdr` upon completion.
30042 * The target ID of the command:
30043 * * 0x0-0xFFF8 - The function ID
30044 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
30045 * * 0xFFFD - Reserved for user-space HWRM interface
30048 uint16_t target_id;
30050 * A physical address pointer pointing to a host buffer that the
30051 * command's response data will be written. This can be either a host
30052 * physical address (HPA) or a guest physical address (GPA) and must
30053 * point to a physically contiguous block of memory.
30055 uint64_t resp_addr;
30060 * When this bit is '1', the function is requested to accept
30061 * multi-cast packets specified by the multicast addr table.
30063 #define HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_MCAST \
30066 * When this bit is '1', the function is requested to accept
30067 * all multi-cast packets.
30069 #define HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_ALL_MCAST \
30072 * When this bit is '1', the function is requested to accept
30073 * broadcast packets.
30075 #define HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_BCAST \
30078 * When this bit is '1', the function is requested to be
30079 * put in the promiscuous mode.
30081 * The HWRM should accept any function to set up
30082 * promiscuous mode.
30084 * The HWRM shall follow the semantics below for the
30085 * promiscuous mode support.
30086 * # When partitioning is not enabled on a port
30087 * (i.e. single PF on the port), then the PF shall
30088 * be allowed to be in the promiscuous mode. When the
30089 * PF is in the promiscuous mode, then it shall
30090 * receive all host bound traffic on that port.
30091 * # When partitioning is enabled on a port
30092 * (i.e. multiple PFs per port) and a PF on that
30093 * port is in the promiscuous mode, then the PF
30094 * receives all traffic within that partition as
30095 * identified by a unique identifier for the
30096 * PF (e.g. S-Tag). If a unique outer VLAN
30097 * for the PF is specified, then the setting of
30098 * promiscuous mode on that PF shall result in the
30099 * PF receiving all host bound traffic with matching
30101 * # A VF shall can be set in the promiscuous mode.
30102 * In the promiscuous mode, the VF does not receive any
30103 * traffic unless a unique outer VLAN for the
30104 * VF is specified. If a unique outer VLAN
30105 * for the VF is specified, then the setting of
30106 * promiscuous mode on that VF shall result in the
30107 * VF receiving all host bound traffic with the
30108 * matching outer VLAN.
30109 * # The HWRM shall allow the setting of promiscuous
30110 * mode on a function independently from the
30111 * promiscuous mode settings on other functions.
30113 #define HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_PROMISCUOUS \
30116 * If this flag is set, the corresponding RX
30117 * filters shall be set up to cover multicast/broadcast
30118 * filters for the outermost Layer 2 destination MAC
30121 #define HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_OUTERMOST \
30124 * If this flag is set, the corresponding RX
30125 * filters shall be set up to cover multicast/broadcast
30126 * filters for the VLAN-tagged packets that match the
30127 * TPID and VID fields of VLAN tags in the VLAN tag
30128 * table specified in this command.
30130 #define HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_VLANONLY \
30133 * If this flag is set, the corresponding RX
30134 * filters shall be set up to cover multicast/broadcast
30135 * filters for non-VLAN tagged packets and VLAN-tagged
30136 * packets that match the TPID and VID fields of VLAN
30137 * tags in the VLAN tag table specified in this command.
30139 #define HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_VLAN_NONVLAN \
30142 * If this flag is set, the corresponding RX
30143 * filters shall be set up to cover multicast/broadcast
30144 * filters for non-VLAN tagged packets and VLAN-tagged
30145 * packets matching any VLAN tag.
30147 * If this flag is set, then the HWRM shall ignore
30148 * VLAN tags specified in vlan_tag_tbl.
30150 * If none of vlanonly, vlan_nonvlan, and anyvlan_nonvlan
30151 * flags is set, then the HWRM shall ignore
30152 * VLAN tags specified in vlan_tag_tbl.
30154 * The HWRM client shall set at most one flag out of
30155 * vlanonly, vlan_nonvlan, and anyvlan_nonvlan.
30157 #define HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_ANYVLAN_NONVLAN \
30159 /* This is the address for mcast address tbl. */
30160 uint64_t mc_tbl_addr;
30162 * This value indicates how many entries in mc_tbl are valid.
30163 * Each entry is 6 bytes.
30165 uint32_t num_mc_entries;
30166 uint8_t unused_0[4];
30168 * This is the address for VLAN tag table.
30169 * Each VLAN entry in the table is 4 bytes of a VLAN tag
30170 * including TPID, PCP, DEI, and VID fields in network byte
30173 uint64_t vlan_tag_tbl_addr;
30175 * This value indicates how many entries in vlan_tag_tbl are
30176 * valid. Each entry is 4 bytes.
30178 uint32_t num_vlan_tags;
30179 uint8_t unused_1[4];
30182 /* hwrm_cfa_l2_set_rx_mask_output (size:128b/16B) */
30183 struct hwrm_cfa_l2_set_rx_mask_output {
30184 /* The specific error status for the command. */
30185 uint16_t error_code;
30186 /* The HWRM command request type. */
30188 /* The sequence ID from the original command. */
30190 /* The length of the response data in number of bytes. */
30192 uint8_t unused_0[7];
30194 * This field is used in Output records to indicate that the output
30195 * is completely written to RAM. This field should be read as '1'
30196 * to indicate that the output has been completely written.
30197 * When writing a command completion or response to an internal processor,
30198 * the order of writes has to be such that this field is written last.
30203 /* hwrm_cfa_l2_set_rx_mask_cmd_err (size:64b/8B) */
30204 struct hwrm_cfa_l2_set_rx_mask_cmd_err {
30206 * command specific error codes that goes to
30207 * the cmd_err field in Common HWRM Error Response.
30210 /* Unknown error */
30211 #define HWRM_CFA_L2_SET_RX_MASK_CMD_ERR_CODE_UNKNOWN \
30213 /* Unable to complete operation due to conflict with Ntuple Filter */
30214 #define HWRM_CFA_L2_SET_RX_MASK_CMD_ERR_CODE_NTUPLE_FILTER_CONFLICT_ERR \
30216 #define HWRM_CFA_L2_SET_RX_MASK_CMD_ERR_CODE_LAST \
30217 HWRM_CFA_L2_SET_RX_MASK_CMD_ERR_CODE_NTUPLE_FILTER_CONFLICT_ERR
30218 uint8_t unused_0[7];
30221 /*******************************
30222 * hwrm_cfa_vlan_antispoof_cfg *
30223 *******************************/
30226 /* hwrm_cfa_vlan_antispoof_cfg_input (size:256b/32B) */
30227 struct hwrm_cfa_vlan_antispoof_cfg_input {
30228 /* The HWRM command request type. */
30231 * The completion ring to send the completion event on. This should
30232 * be the NQ ID returned from the `nq_alloc` HWRM command.
30234 uint16_t cmpl_ring;
30236 * The sequence ID is used by the driver for tracking multiple
30237 * commands. This ID is treated as opaque data by the firmware and
30238 * the value is returned in the `hwrm_resp_hdr` upon completion.
30242 * The target ID of the command:
30243 * * 0x0-0xFFF8 - The function ID
30244 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
30245 * * 0xFFFD - Reserved for user-space HWRM interface
30248 uint16_t target_id;
30250 * A physical address pointer pointing to a host buffer that the
30251 * command's response data will be written. This can be either a host
30252 * physical address (HPA) or a guest physical address (GPA) and must
30253 * point to a physically contiguous block of memory.
30255 uint64_t resp_addr;
30257 * Function ID of the function that is being configured.
30258 * Only valid for a VF FID configured by the PF.
30261 uint8_t unused_0[2];
30262 /* Number of VLAN entries in the vlan_tag_mask_tbl. */
30263 uint32_t num_vlan_entries;
30265 * The vlan_tag_mask_tbl_addr is the DMA address of the VLAN
30266 * antispoof table. Each table entry contains the 16-bit TPID
30267 * (0x8100 or 0x88a8 only), 16-bit VLAN ID, and a 16-bit mask,
30268 * all in network order to match hwrm_cfa_l2_set_rx_mask.
30269 * For an individual VLAN entry, the mask value should be 0xfff
30270 * for the 12-bit VLAN ID.
30272 uint64_t vlan_tag_mask_tbl_addr;
30275 /* hwrm_cfa_vlan_antispoof_cfg_output (size:128b/16B) */
30276 struct hwrm_cfa_vlan_antispoof_cfg_output {
30277 /* The specific error status for the command. */
30278 uint16_t error_code;
30279 /* The HWRM command request type. */
30281 /* The sequence ID from the original command. */
30283 /* The length of the response data in number of bytes. */
30285 uint8_t unused_0[7];
30287 * This field is used in Output records to indicate that the output
30288 * is completely written to RAM. This field should be read as '1'
30289 * to indicate that the output has been completely written.
30290 * When writing a command completion or response to an internal processor,
30291 * the order of writes has to be such that this field is written last.
30296 /********************************
30297 * hwrm_cfa_vlan_antispoof_qcfg *
30298 ********************************/
30301 /* hwrm_cfa_vlan_antispoof_qcfg_input (size:256b/32B) */
30302 struct hwrm_cfa_vlan_antispoof_qcfg_input {
30303 /* The HWRM command request type. */
30306 * The completion ring to send the completion event on. This should
30307 * be the NQ ID returned from the `nq_alloc` HWRM command.
30309 uint16_t cmpl_ring;
30311 * The sequence ID is used by the driver for tracking multiple
30312 * commands. This ID is treated as opaque data by the firmware and
30313 * the value is returned in the `hwrm_resp_hdr` upon completion.
30317 * The target ID of the command:
30318 * * 0x0-0xFFF8 - The function ID
30319 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
30320 * * 0xFFFD - Reserved for user-space HWRM interface
30323 uint16_t target_id;
30325 * A physical address pointer pointing to a host buffer that the
30326 * command's response data will be written. This can be either a host
30327 * physical address (HPA) or a guest physical address (GPA) and must
30328 * point to a physically contiguous block of memory.
30330 uint64_t resp_addr;
30332 * Function ID of the function that is being queried.
30333 * Only valid for a VF FID queried by the PF.
30336 uint8_t unused_0[2];
30338 * Maximum number of VLAN entries the firmware is allowed to DMA
30339 * to vlan_tag_mask_tbl.
30341 uint32_t max_vlan_entries;
30343 * The vlan_tag_mask_tbl_addr is the DMA address of the VLAN
30344 * antispoof table to which firmware will DMA to. Each table
30345 * entry will contain the 16-bit TPID (0x8100 or 0x88a8 only),
30346 * 16-bit VLAN ID, and a 16-bit mask, all in network order to
30347 * match hwrm_cfa_l2_set_rx_mask. For an individual VLAN entry,
30348 * the mask value should be 0xfff for the 12-bit VLAN ID.
30350 uint64_t vlan_tag_mask_tbl_addr;
30353 /* hwrm_cfa_vlan_antispoof_qcfg_output (size:128b/16B) */
30354 struct hwrm_cfa_vlan_antispoof_qcfg_output {
30355 /* The specific error status for the command. */
30356 uint16_t error_code;
30357 /* The HWRM command request type. */
30359 /* The sequence ID from the original command. */
30361 /* The length of the response data in number of bytes. */
30363 /* Number of valid entries DMAd by firmware to vlan_tag_mask_tbl. */
30364 uint32_t num_vlan_entries;
30365 uint8_t unused_0[3];
30367 * This field is used in Output records to indicate that the output
30368 * is completely written to RAM. This field should be read as '1'
30369 * to indicate that the output has been completely written.
30370 * When writing a command completion or response to an internal processor,
30371 * the order of writes has to be such that this field is written last.
30376 /********************************
30377 * hwrm_cfa_tunnel_filter_alloc *
30378 ********************************/
30381 /* hwrm_cfa_tunnel_filter_alloc_input (size:704b/88B) */
30382 struct hwrm_cfa_tunnel_filter_alloc_input {
30383 /* The HWRM command request type. */
30386 * The completion ring to send the completion event on. This should
30387 * be the NQ ID returned from the `nq_alloc` HWRM command.
30389 uint16_t cmpl_ring;
30391 * The sequence ID is used by the driver for tracking multiple
30392 * commands. This ID is treated as opaque data by the firmware and
30393 * the value is returned in the `hwrm_resp_hdr` upon completion.
30397 * The target ID of the command:
30398 * * 0x0-0xFFF8 - The function ID
30399 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
30400 * * 0xFFFD - Reserved for user-space HWRM interface
30403 uint16_t target_id;
30405 * A physical address pointer pointing to a host buffer that the
30406 * command's response data will be written. This can be either a host
30407 * physical address (HPA) or a guest physical address (GPA) and must
30408 * point to a physically contiguous block of memory.
30410 uint64_t resp_addr;
30412 /* Setting of this flag indicates the applicability to the loopback path. */
30413 #define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_FLAGS_LOOPBACK \
30417 * This bit must be '1' for the l2_filter_id field to be
30420 #define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_ENABLES_L2_FILTER_ID \
30423 * This bit must be '1' for the l2_addr field to be
30426 #define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_ENABLES_L2_ADDR \
30429 * This bit must be '1' for the l2_ivlan field to be
30432 #define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN \
30435 * This bit must be '1' for the l3_addr field to be
30438 #define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_ENABLES_L3_ADDR \
30441 * This bit must be '1' for the l3_addr_type field to be
30444 #define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_ENABLES_L3_ADDR_TYPE \
30447 * This bit must be '1' for the t_l3_addr_type field to be
30450 #define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_ENABLES_T_L3_ADDR_TYPE \
30453 * This bit must be '1' for the t_l3_addr field to be
30456 #define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_ENABLES_T_L3_ADDR \
30459 * This bit must be '1' for the tunnel_type field to be
30462 #define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_ENABLES_TUNNEL_TYPE \
30465 * This bit must be '1' for the vni field to be
30468 #define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_ENABLES_VNI \
30471 * This bit must be '1' for the dst_vnic_id field to be
30474 #define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_ENABLES_DST_VNIC_ID \
30477 * This bit must be '1' for the mirror_vnic_id field to be
30480 #define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_ENABLES_MIRROR_VNIC_ID \
30483 * This value identifies a set of CFA data structures used for an L2
30486 uint64_t l2_filter_id;
30488 * This value sets the match value for the inner L2
30490 * Destination MAC address for RX path.
30491 * Source MAC address for TX path.
30493 uint8_t l2_addr[6];
30495 * This value sets VLAN ID value for inner VLAN.
30496 * Only 12-bits of VLAN ID are used in setting the filter.
30500 * The value of inner destination IP address to be used in filtering.
30501 * For IPv4, first four bytes represent the IP address.
30503 uint32_t l3_addr[4];
30505 * The value of tunnel destination IP address to be used in filtering.
30506 * For IPv4, first four bytes represent the IP address.
30508 uint32_t t_l3_addr[4];
30510 * This value indicates the type of inner IP address.
30513 * All others are invalid.
30515 uint8_t l3_addr_type;
30517 * This value indicates the type of tunnel IP address.
30520 * All others are invalid.
30522 uint8_t t_l3_addr_type;
30524 uint8_t tunnel_type;
30526 #define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_TUNNEL_TYPE_NONTUNNEL \
30528 /* Virtual eXtensible Local Area Network (VXLAN) */
30529 #define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_TUNNEL_TYPE_VXLAN \
30531 /* Network Virtualization Generic Routing Encapsulation (NVGRE) */
30532 #define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_TUNNEL_TYPE_NVGRE \
30534 /* Generic Routing Encapsulation (GRE) inside Ethernet payload */
30535 #define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_TUNNEL_TYPE_L2GRE \
30538 #define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_TUNNEL_TYPE_IPIP \
30540 /* Generic Network Virtualization Encapsulation (Geneve) */
30541 #define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_TUNNEL_TYPE_GENEVE \
30543 /* Multi-Protocol Label Switching (MPLS) */
30544 #define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_TUNNEL_TYPE_MPLS \
30546 /* Stateless Transport Tunnel (STT) */
30547 #define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_TUNNEL_TYPE_STT \
30549 /* Generic Routing Encapsulation (GRE) inside IP datagram payload */
30550 #define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_TUNNEL_TYPE_IPGRE \
30552 /* IPV4 over virtual eXtensible Local Area Network (IPV4oVXLAN) */
30553 #define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_TUNNEL_TYPE_VXLAN_V4 \
30555 /* Enhance Generic Routing Encapsulation (GRE version 1) inside IP datagram payload */
30556 #define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_TUNNEL_TYPE_IPGRE_V1 \
30558 /* Use fixed layer 2 ether type of 0xFFFF */
30559 #define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_TUNNEL_TYPE_L2_ETYPE \
30561 /* IPV6 over virtual eXtensible Local Area Network with GPE header (IPV6oVXLANGPE) */
30562 #define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_TUNNEL_TYPE_VXLAN_GPE_V6 \
30564 /* Any tunneled traffic */
30565 #define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_TUNNEL_TYPE_ANYTUNNEL \
30567 #define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_TUNNEL_TYPE_LAST \
30568 HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_TUNNEL_TYPE_ANYTUNNEL
30570 * tunnel_flags allows the user to indicate the tunnel tag detection
30571 * for the tunnel type specified in tunnel_type.
30573 uint8_t tunnel_flags;
30575 * If the tunnel_type is geneve, then this bit indicates if we
30576 * need to match the geneve OAM packet.
30577 * If the tunnel_type is nvgre or gre, then this bit indicates if
30578 * we need to detect checksum present bit in geneve header.
30579 * If the tunnel_type is mpls, then this bit indicates if we need
30580 * to match mpls packet with explicit IPV4/IPV6 null header.
30582 #define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_TUNNEL_FLAGS_TUN_FLAGS_OAM_CHECKSUM_EXPLHDR \
30585 * If the tunnel_type is geneve, then this bit indicates if we
30586 * need to detect the critical option bit set in the oam packet.
30587 * If the tunnel_type is nvgre or gre, then this bit indicates
30588 * if we need to match nvgre packets with key present bit set in
30590 * If the tunnel_type is mpls, then this bit indicates if we
30591 * need to match mpls packet with S bit from inner/second label.
30593 #define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_TUNNEL_FLAGS_TUN_FLAGS_CRITICAL_OPT_S1 \
30596 * If the tunnel_type is geneve, then this bit indicates if we
30597 * need to match geneve packet with extended header bit set in
30599 * If the tunnel_type is nvgre or gre, then this bit indicates
30600 * if we need to match nvgre packets with sequence number
30601 * present bit set in gre header.
30602 * If the tunnel_type is mpls, then this bit indicates if we
30603 * need to match mpls packet with S bit from out/first label.
30605 #define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_TUNNEL_FLAGS_TUN_FLAGS_EXTHDR_SEQNUM_S0 \
30608 * Virtual Network Identifier (VNI). Only valid with
30609 * tunnel_types VXLAN, NVGRE, and Geneve.
30610 * Only lower 24-bits of VNI field are used
30611 * in setting up the filter.
30614 /* Logical VNIC ID of the destination VNIC. */
30615 uint32_t dst_vnic_id;
30617 * Logical VNIC ID of the VNIC where traffic is
30620 uint32_t mirror_vnic_id;
30623 /* hwrm_cfa_tunnel_filter_alloc_output (size:192b/24B) */
30624 struct hwrm_cfa_tunnel_filter_alloc_output {
30625 /* The specific error status for the command. */
30626 uint16_t error_code;
30627 /* The HWRM command request type. */
30629 /* The sequence ID from the original command. */
30631 /* The length of the response data in number of bytes. */
30633 /* This value is an opaque id into CFA data structures. */
30634 uint64_t tunnel_filter_id;
30636 * The flow id value in bit 0-29 is the actual ID of the flow
30637 * associated with this filter and it shall be used to match
30638 * and associate the flow identifier returned in completion
30639 * records. A value of 0xFFFFFFFF in the 32-bit flow_id field
30640 * shall indicate no valid flow id.
30643 /* Indicate the flow id value. */
30644 #define HWRM_CFA_TUNNEL_FILTER_ALLOC_OUTPUT_FLOW_ID_VALUE_MASK \
30645 UINT32_C(0x3fffffff)
30646 #define HWRM_CFA_TUNNEL_FILTER_ALLOC_OUTPUT_FLOW_ID_VALUE_SFT 0
30647 /* Indicate type of the flow. */
30648 #define HWRM_CFA_TUNNEL_FILTER_ALLOC_OUTPUT_FLOW_ID_TYPE \
30649 UINT32_C(0x40000000)
30651 * If this bit set to 0, then it indicates that the flow is
30654 #define HWRM_CFA_TUNNEL_FILTER_ALLOC_OUTPUT_FLOW_ID_TYPE_INT \
30655 (UINT32_C(0x0) << 30)
30657 * If this bit is set to 1, then it indicates that the flow is
30660 #define HWRM_CFA_TUNNEL_FILTER_ALLOC_OUTPUT_FLOW_ID_TYPE_EXT \
30661 (UINT32_C(0x1) << 30)
30662 #define HWRM_CFA_TUNNEL_FILTER_ALLOC_OUTPUT_FLOW_ID_TYPE_LAST \
30663 HWRM_CFA_TUNNEL_FILTER_ALLOC_OUTPUT_FLOW_ID_TYPE_EXT
30664 /* Indicate the flow direction. */
30665 #define HWRM_CFA_TUNNEL_FILTER_ALLOC_OUTPUT_FLOW_ID_DIR \
30666 UINT32_C(0x80000000)
30667 /* If this bit set to 0, then it indicates rx flow. */
30668 #define HWRM_CFA_TUNNEL_FILTER_ALLOC_OUTPUT_FLOW_ID_DIR_RX \
30669 (UINT32_C(0x0) << 31)
30670 /* If this bit is set to 1, then it indicates that tx flow. */
30671 #define HWRM_CFA_TUNNEL_FILTER_ALLOC_OUTPUT_FLOW_ID_DIR_TX \
30672 (UINT32_C(0x1) << 31)
30673 #define HWRM_CFA_TUNNEL_FILTER_ALLOC_OUTPUT_FLOW_ID_DIR_LAST \
30674 HWRM_CFA_TUNNEL_FILTER_ALLOC_OUTPUT_FLOW_ID_DIR_TX
30675 uint8_t unused_0[3];
30677 * This field is used in Output records to indicate that the output
30678 * is completely written to RAM. This field should be read as '1'
30679 * to indicate that the output has been completely written.
30680 * When writing a command completion or response to an internal processor,
30681 * the order of writes has to be such that this field is written last.
30686 /*******************************
30687 * hwrm_cfa_tunnel_filter_free *
30688 *******************************/
30691 /* hwrm_cfa_tunnel_filter_free_input (size:192b/24B) */
30692 struct hwrm_cfa_tunnel_filter_free_input {
30693 /* The HWRM command request type. */
30696 * The completion ring to send the completion event on. This should
30697 * be the NQ ID returned from the `nq_alloc` HWRM command.
30699 uint16_t cmpl_ring;
30701 * The sequence ID is used by the driver for tracking multiple
30702 * commands. This ID is treated as opaque data by the firmware and
30703 * the value is returned in the `hwrm_resp_hdr` upon completion.
30707 * The target ID of the command:
30708 * * 0x0-0xFFF8 - The function ID
30709 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
30710 * * 0xFFFD - Reserved for user-space HWRM interface
30713 uint16_t target_id;
30715 * A physical address pointer pointing to a host buffer that the
30716 * command's response data will be written. This can be either a host
30717 * physical address (HPA) or a guest physical address (GPA) and must
30718 * point to a physically contiguous block of memory.
30720 uint64_t resp_addr;
30721 /* This value is an opaque id into CFA data structures. */
30722 uint64_t tunnel_filter_id;
30725 /* hwrm_cfa_tunnel_filter_free_output (size:128b/16B) */
30726 struct hwrm_cfa_tunnel_filter_free_output {
30727 /* The specific error status for the command. */
30728 uint16_t error_code;
30729 /* The HWRM command request type. */
30731 /* The sequence ID from the original command. */
30733 /* The length of the response data in number of bytes. */
30735 uint8_t unused_0[7];
30737 * This field is used in Output records to indicate that the output
30738 * is completely written to RAM. This field should be read as '1'
30739 * to indicate that the output has been completely written.
30740 * When writing a command completion or response to an internal processor,
30741 * the order of writes has to be such that this field is written last.
30746 /***************************************
30747 * hwrm_cfa_redirect_tunnel_type_alloc *
30748 ***************************************/
30751 /* hwrm_cfa_redirect_tunnel_type_alloc_input (size:192b/24B) */
30752 struct hwrm_cfa_redirect_tunnel_type_alloc_input {
30753 /* The HWRM command request type. */
30756 * The completion ring to send the completion event on. This should
30757 * be the NQ ID returned from the `nq_alloc` HWRM command.
30759 uint16_t cmpl_ring;
30761 * The sequence ID is used by the driver for tracking multiple
30762 * commands. This ID is treated as opaque data by the firmware and
30763 * the value is returned in the `hwrm_resp_hdr` upon completion.
30767 * The target ID of the command:
30768 * * 0x0-0xFFF8 - The function ID
30769 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
30770 * * 0xFFFD - Reserved for user-space HWRM interface
30773 uint16_t target_id;
30775 * A physical address pointer pointing to a host buffer that the
30776 * command's response data will be written. This can be either a host
30777 * physical address (HPA) or a guest physical address (GPA) and must
30778 * point to a physically contiguous block of memory.
30780 uint64_t resp_addr;
30781 /* The destination function id, to whom the traffic is redirected. */
30784 uint8_t tunnel_type;
30786 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_ALLOC_INPUT_TUNNEL_TYPE_NONTUNNEL \
30788 /* Virtual eXtensible Local Area Network (VXLAN) */
30789 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_ALLOC_INPUT_TUNNEL_TYPE_VXLAN \
30791 /* Network Virtualization Generic Routing Encapsulation (NVGRE) */
30792 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_ALLOC_INPUT_TUNNEL_TYPE_NVGRE \
30794 /* Generic Routing Encapsulation (GRE) inside Ethernet payload */
30795 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_ALLOC_INPUT_TUNNEL_TYPE_L2GRE \
30798 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_ALLOC_INPUT_TUNNEL_TYPE_IPIP \
30800 /* Generic Network Virtualization Encapsulation (Geneve) */
30801 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_ALLOC_INPUT_TUNNEL_TYPE_GENEVE \
30803 /* Multi-Protocol Label Switching (MPLS) */
30804 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_ALLOC_INPUT_TUNNEL_TYPE_MPLS \
30806 /* Stateless Transport Tunnel (STT) */
30807 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_ALLOC_INPUT_TUNNEL_TYPE_STT \
30809 /* Generic Routing Encapsulation (GRE) inside IP datagram payload */
30810 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_ALLOC_INPUT_TUNNEL_TYPE_IPGRE \
30812 /* IPV4 over virtual eXtensible Local Area Network (IPV4oVXLAN) */
30813 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_ALLOC_INPUT_TUNNEL_TYPE_VXLAN_V4 \
30815 /* Enhance Generic Routing Encapsulation (GRE version 1) inside IP datagram payload */
30816 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_ALLOC_INPUT_TUNNEL_TYPE_IPGRE_V1 \
30818 /* Use fixed layer 2 ether type of 0xFFFF */
30819 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_ALLOC_INPUT_TUNNEL_TYPE_L2_ETYPE \
30821 /* IPV6 over virtual eXtensible Local Area Network with GPE header (IPV6oVXLANGPE) */
30822 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_ALLOC_INPUT_TUNNEL_TYPE_VXLAN_GPE_V6 \
30824 /* Any tunneled traffic */
30825 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_ALLOC_INPUT_TUNNEL_TYPE_ANYTUNNEL \
30827 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_ALLOC_INPUT_TUNNEL_TYPE_LAST \
30828 HWRM_CFA_REDIRECT_TUNNEL_TYPE_ALLOC_INPUT_TUNNEL_TYPE_ANYTUNNEL
30829 /* Tunnel alloc flags. */
30831 /* Setting of this flag indicates modify existing redirect tunnel to new destination function ID. */
30832 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_ALLOC_INPUT_FLAGS_MODIFY_DST \
30834 uint8_t unused_0[4];
30837 /* hwrm_cfa_redirect_tunnel_type_alloc_output (size:128b/16B) */
30838 struct hwrm_cfa_redirect_tunnel_type_alloc_output {
30839 /* The specific error status for the command. */
30840 uint16_t error_code;
30841 /* The HWRM command request type. */
30843 /* The sequence ID from the original command. */
30845 /* The length of the response data in number of bytes. */
30847 uint8_t unused_0[7];
30849 * This field is used in Output records to indicate that the output
30850 * is completely written to RAM. This field should be read as '1'
30851 * to indicate that the output has been completely written.
30852 * When writing a command completion or response to an internal processor,
30853 * the order of writes has to be such that this field is written last.
30858 /**************************************
30859 * hwrm_cfa_redirect_tunnel_type_free *
30860 **************************************/
30863 /* hwrm_cfa_redirect_tunnel_type_free_input (size:192b/24B) */
30864 struct hwrm_cfa_redirect_tunnel_type_free_input {
30865 /* The HWRM command request type. */
30868 * The completion ring to send the completion event on. This should
30869 * be the NQ ID returned from the `nq_alloc` HWRM command.
30871 uint16_t cmpl_ring;
30873 * The sequence ID is used by the driver for tracking multiple
30874 * commands. This ID is treated as opaque data by the firmware and
30875 * the value is returned in the `hwrm_resp_hdr` upon completion.
30879 * The target ID of the command:
30880 * * 0x0-0xFFF8 - The function ID
30881 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
30882 * * 0xFFFD - Reserved for user-space HWRM interface
30885 uint16_t target_id;
30887 * A physical address pointer pointing to a host buffer that the
30888 * command's response data will be written. This can be either a host
30889 * physical address (HPA) or a guest physical address (GPA) and must
30890 * point to a physically contiguous block of memory.
30892 uint64_t resp_addr;
30893 /* The destination function id, to whom the traffic is redirected. */
30896 uint8_t tunnel_type;
30898 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_FREE_INPUT_TUNNEL_TYPE_NONTUNNEL \
30900 /* Virtual eXtensible Local Area Network (VXLAN) */
30901 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_FREE_INPUT_TUNNEL_TYPE_VXLAN \
30903 /* Network Virtualization Generic Routing Encapsulation (NVGRE) */
30904 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_FREE_INPUT_TUNNEL_TYPE_NVGRE \
30906 /* Generic Routing Encapsulation (GRE) inside Ethernet payload */
30907 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_FREE_INPUT_TUNNEL_TYPE_L2GRE \
30910 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_FREE_INPUT_TUNNEL_TYPE_IPIP \
30912 /* Generic Network Virtualization Encapsulation (Geneve) */
30913 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_FREE_INPUT_TUNNEL_TYPE_GENEVE \
30915 /* Multi-Protocol Label Switching (MPLS) */
30916 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_FREE_INPUT_TUNNEL_TYPE_MPLS \
30918 /* Stateless Transport Tunnel (STT) */
30919 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_FREE_INPUT_TUNNEL_TYPE_STT \
30921 /* Generic Routing Encapsulation (GRE) inside IP datagram payload */
30922 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_FREE_INPUT_TUNNEL_TYPE_IPGRE \
30924 /* IPV4 over virtual eXtensible Local Area Network (IPV4oVXLAN) */
30925 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_FREE_INPUT_TUNNEL_TYPE_VXLAN_V4 \
30927 /* Enhance Generic Routing Encapsulation (GRE version 1) inside IP datagram payload */
30928 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_FREE_INPUT_TUNNEL_TYPE_IPGRE_V1 \
30930 /* Use fixed layer 2 ether type of 0xFFFF */
30931 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_FREE_INPUT_TUNNEL_TYPE_L2_ETYPE \
30933 /* IPV6 over virtual eXtensible Local Area Network with GPE header (IPV6oVXLANGPE) */
30934 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_FREE_INPUT_TUNNEL_TYPE_VXLAN_GPE_V6 \
30936 /* Any tunneled traffic */
30937 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_FREE_INPUT_TUNNEL_TYPE_ANYTUNNEL \
30939 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_FREE_INPUT_TUNNEL_TYPE_LAST \
30940 HWRM_CFA_REDIRECT_TUNNEL_TYPE_FREE_INPUT_TUNNEL_TYPE_ANYTUNNEL
30941 uint8_t unused_0[5];
30944 /* hwrm_cfa_redirect_tunnel_type_free_output (size:128b/16B) */
30945 struct hwrm_cfa_redirect_tunnel_type_free_output {
30946 /* The specific error status for the command. */
30947 uint16_t error_code;
30948 /* The HWRM command request type. */
30950 /* The sequence ID from the original command. */
30952 /* The length of the response data in number of bytes. */
30954 uint8_t unused_0[7];
30956 * This field is used in Output records to indicate that the output
30957 * is completely written to RAM. This field should be read as '1'
30958 * to indicate that the output has been completely written.
30959 * When writing a command completion or response to an internal processor,
30960 * the order of writes has to be such that this field is written last.
30965 /**************************************
30966 * hwrm_cfa_redirect_tunnel_type_info *
30967 **************************************/
30970 /* hwrm_cfa_redirect_tunnel_type_info_input (size:192b/24B) */
30971 struct hwrm_cfa_redirect_tunnel_type_info_input {
30972 /* The HWRM command request type. */
30975 * The completion ring to send the completion event on. This should
30976 * be the NQ ID returned from the `nq_alloc` HWRM command.
30978 uint16_t cmpl_ring;
30980 * The sequence ID is used by the driver for tracking multiple
30981 * commands. This ID is treated as opaque data by the firmware and
30982 * the value is returned in the `hwrm_resp_hdr` upon completion.
30986 * The target ID of the command:
30987 * * 0x0-0xFFF8 - The function ID
30988 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
30989 * * 0xFFFD - Reserved for user-space HWRM interface
30992 uint16_t target_id;
30994 * A physical address pointer pointing to a host buffer that the
30995 * command's response data will be written. This can be either a host
30996 * physical address (HPA) or a guest physical address (GPA) and must
30997 * point to a physically contiguous block of memory.
30999 uint64_t resp_addr;
31000 /* The source function id. */
31003 uint8_t tunnel_type;
31005 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_INFO_INPUT_TUNNEL_TYPE_NONTUNNEL \
31007 /* Virtual eXtensible Local Area Network (VXLAN) */
31008 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_INFO_INPUT_TUNNEL_TYPE_VXLAN \
31010 /* Network Virtualization Generic Routing Encapsulation (NVGRE) */
31011 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_INFO_INPUT_TUNNEL_TYPE_NVGRE \
31013 /* Generic Routing Encapsulation (GRE) inside Ethernet payload */
31014 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_INFO_INPUT_TUNNEL_TYPE_L2GRE \
31017 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_INFO_INPUT_TUNNEL_TYPE_IPIP \
31019 /* Generic Network Virtualization Encapsulation (Geneve) */
31020 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_INFO_INPUT_TUNNEL_TYPE_GENEVE \
31022 /* Multi-Protocol Label Switching (MPLS) */
31023 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_INFO_INPUT_TUNNEL_TYPE_MPLS \
31025 /* Stateless Transport Tunnel (STT) */
31026 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_INFO_INPUT_TUNNEL_TYPE_STT \
31028 /* Generic Routing Encapsulation (GRE) inside IP datagram payload */
31029 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_INFO_INPUT_TUNNEL_TYPE_IPGRE \
31031 /* IPV4 over virtual eXtensible Local Area Network (IPV4oVXLAN) */
31032 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_INFO_INPUT_TUNNEL_TYPE_VXLAN_V4 \
31034 /* Enhance Generic Routing Encapsulation (GRE version 1) inside IP datagram payload */
31035 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_INFO_INPUT_TUNNEL_TYPE_IPGRE_V1 \
31037 /* Use fixed layer 2 ether type of 0xFFFF */
31038 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_INFO_INPUT_TUNNEL_TYPE_L2_ETYPE \
31040 /* IPV6 over virtual eXtensible Local Area Network with GPE header (IPV6oVXLANGPE) */
31041 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_INFO_INPUT_TUNNEL_TYPE_VXLAN_GPE_V6 \
31043 /* Any tunneled traffic */
31044 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_INFO_INPUT_TUNNEL_TYPE_ANYTUNNEL \
31046 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_INFO_INPUT_TUNNEL_TYPE_LAST \
31047 HWRM_CFA_REDIRECT_TUNNEL_TYPE_INFO_INPUT_TUNNEL_TYPE_ANYTUNNEL
31048 uint8_t unused_0[5];
31051 /* hwrm_cfa_redirect_tunnel_type_info_output (size:128b/16B) */
31052 struct hwrm_cfa_redirect_tunnel_type_info_output {
31053 /* The specific error status for the command. */
31054 uint16_t error_code;
31055 /* The HWRM command request type. */
31057 /* The sequence ID from the original command. */
31059 /* The length of the response data in number of bytes. */
31061 /* The destination function id, to whom the traffic is redirected. */
31063 uint8_t unused_0[5];
31065 * This field is used in Output records to indicate that the output
31066 * is completely written to RAM. This field should be read as '1'
31067 * to indicate that the output has been completely written.
31068 * When writing a command completion or response to an internal processor,
31069 * the order of writes has to be such that this field is written last.
31074 /* hwrm_vxlan_ipv4_hdr (size:128b/16B) */
31075 struct hwrm_vxlan_ipv4_hdr {
31076 /* IPv4 version and header length. */
31078 /* IPv4 header length */
31079 #define HWRM_VXLAN_IPV4_HDR_VER_HLEN_HEADER_LENGTH_MASK UINT32_C(0xf)
31080 #define HWRM_VXLAN_IPV4_HDR_VER_HLEN_HEADER_LENGTH_SFT 0
31082 #define HWRM_VXLAN_IPV4_HDR_VER_HLEN_VERSION_MASK UINT32_C(0xf0)
31083 #define HWRM_VXLAN_IPV4_HDR_VER_HLEN_VERSION_SFT 4
31084 /* IPv4 type of service. */
31086 /* IPv4 identification. */
31088 /* IPv4 flags and offset. */
31089 uint16_t flags_frag_offset;
31092 /* IPv4 protocol. */
31094 /* IPv4 source address. */
31095 uint32_t src_ip_addr;
31096 /* IPv4 destination address. */
31097 uint32_t dest_ip_addr;
31100 /* hwrm_vxlan_ipv6_hdr (size:320b/40B) */
31101 struct hwrm_vxlan_ipv6_hdr {
31102 /* IPv6 version, traffic class and flow label. */
31103 uint32_t ver_tc_flow_label;
31104 /* IPv6 version shift */
31105 #define HWRM_VXLAN_IPV6_HDR_VER_TC_FLOW_LABEL_VER_SFT \
31107 /* IPv6 version mask */
31108 #define HWRM_VXLAN_IPV6_HDR_VER_TC_FLOW_LABEL_VER_MASK \
31109 UINT32_C(0xf0000000)
31110 /* IPv6 TC shift */
31111 #define HWRM_VXLAN_IPV6_HDR_VER_TC_FLOW_LABEL_TC_SFT \
31114 #define HWRM_VXLAN_IPV6_HDR_VER_TC_FLOW_LABEL_TC_MASK \
31115 UINT32_C(0xff00000)
31116 /* IPv6 flow label shift */
31117 #define HWRM_VXLAN_IPV6_HDR_VER_TC_FLOW_LABEL_FLOW_LABEL_SFT \
31119 /* IPv6 flow label mask */
31120 #define HWRM_VXLAN_IPV6_HDR_VER_TC_FLOW_LABEL_FLOW_LABEL_MASK \
31122 #define HWRM_VXLAN_IPV6_HDR_VER_TC_FLOW_LABEL_LAST \
31123 HWRM_VXLAN_IPV6_HDR_VER_TC_FLOW_LABEL_FLOW_LABEL_MASK
31124 /* IPv6 payload length. */
31125 uint16_t payload_len;
31126 /* IPv6 next header. */
31130 /* IPv6 source address. */
31131 uint32_t src_ip_addr[4];
31132 /* IPv6 destination address. */
31133 uint32_t dest_ip_addr[4];
31136 /* hwrm_cfa_encap_data_vxlan (size:640b/80B) */
31137 struct hwrm_cfa_encap_data_vxlan {
31138 /* Source MAC address. */
31139 uint8_t src_mac_addr[6];
31142 /* Destination MAC address. */
31143 uint8_t dst_mac_addr[6];
31144 /* Number of VLAN tags. */
31145 uint8_t num_vlan_tags;
31148 /* Outer VLAN TPID. */
31149 uint16_t ovlan_tpid;
31150 /* Outer VLAN TCI. */
31151 uint16_t ovlan_tci;
31152 /* Inner VLAN TPID. */
31153 uint16_t ivlan_tpid;
31154 /* Inner VLAN TCI. */
31155 uint16_t ivlan_tci;
31156 /* L3 header fields. */
31158 /* IP version mask. */
31159 #define HWRM_CFA_ENCAP_DATA_VXLAN_L3_VER_MASK UINT32_C(0xf)
31160 /* IP version 4. */
31161 #define HWRM_CFA_ENCAP_DATA_VXLAN_L3_VER_IPV4 UINT32_C(0x4)
31162 /* IP version 6. */
31163 #define HWRM_CFA_ENCAP_DATA_VXLAN_L3_VER_IPV6 UINT32_C(0x6)
31164 #define HWRM_CFA_ENCAP_DATA_VXLAN_L3_LAST \
31165 HWRM_CFA_ENCAP_DATA_VXLAN_L3_VER_IPV6
31166 /* UDP source port. */
31168 /* UDP destination port. */
31170 /* VXLAN Network Identifier. */
31172 /* 3 bytes VXLAN header reserve fields from 1st dword of the VXLAN header. */
31173 uint8_t hdr_rsvd0[3];
31174 /* 1 byte VXLAN header reserve field from 2nd dword of the VXLAN header. */
31176 /* VXLAN header flags field. */
31181 /*******************************
31182 * hwrm_cfa_encap_record_alloc *
31183 *******************************/
31186 /* hwrm_cfa_encap_record_alloc_input (size:832b/104B) */
31187 struct hwrm_cfa_encap_record_alloc_input {
31188 /* The HWRM command request type. */
31191 * The completion ring to send the completion event on. This should
31192 * be the NQ ID returned from the `nq_alloc` HWRM command.
31194 uint16_t cmpl_ring;
31196 * The sequence ID is used by the driver for tracking multiple
31197 * commands. This ID is treated as opaque data by the firmware and
31198 * the value is returned in the `hwrm_resp_hdr` upon completion.
31202 * The target ID of the command:
31203 * * 0x0-0xFFF8 - The function ID
31204 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
31205 * * 0xFFFD - Reserved for user-space HWRM interface
31208 uint16_t target_id;
31210 * A physical address pointer pointing to a host buffer that the
31211 * command's response data will be written. This can be either a host
31212 * physical address (HPA) or a guest physical address (GPA) and must
31213 * point to a physically contiguous block of memory.
31215 uint64_t resp_addr;
31217 /* Setting of this flag indicates the applicability to the loopback path. */
31218 #define HWRM_CFA_ENCAP_RECORD_ALLOC_INPUT_FLAGS_LOOPBACK \
31221 * Setting of this flag indicates this encap record is external encap record.
31222 * Resetting of this flag indicates this flag is internal encap record and
31223 * this is the default setting.
31225 #define HWRM_CFA_ENCAP_RECORD_ALLOC_INPUT_FLAGS_EXTERNAL \
31227 /* Encapsulation Type. */
31228 uint8_t encap_type;
31229 /* Virtual eXtensible Local Area Network (VXLAN) */
31230 #define HWRM_CFA_ENCAP_RECORD_ALLOC_INPUT_ENCAP_TYPE_VXLAN \
31232 /* Network Virtualization Generic Routing Encapsulation (NVGRE) */
31233 #define HWRM_CFA_ENCAP_RECORD_ALLOC_INPUT_ENCAP_TYPE_NVGRE \
31235 /* Generic Routing Encapsulation (GRE) after inside Ethernet payload */
31236 #define HWRM_CFA_ENCAP_RECORD_ALLOC_INPUT_ENCAP_TYPE_L2GRE \
31239 #define HWRM_CFA_ENCAP_RECORD_ALLOC_INPUT_ENCAP_TYPE_IPIP \
31241 /* Generic Network Virtualization Encapsulation (Geneve) */
31242 #define HWRM_CFA_ENCAP_RECORD_ALLOC_INPUT_ENCAP_TYPE_GENEVE \
31244 /* Multi-Protocol Label Switching (MPLS) */
31245 #define HWRM_CFA_ENCAP_RECORD_ALLOC_INPUT_ENCAP_TYPE_MPLS \
31248 #define HWRM_CFA_ENCAP_RECORD_ALLOC_INPUT_ENCAP_TYPE_VLAN \
31250 /* Generic Routing Encapsulation (GRE) inside IP datagram payload */
31251 #define HWRM_CFA_ENCAP_RECORD_ALLOC_INPUT_ENCAP_TYPE_IPGRE \
31253 /* IPV4 over virtual eXtensible Local Area Network (IPV4oVXLAN) */
31254 #define HWRM_CFA_ENCAP_RECORD_ALLOC_INPUT_ENCAP_TYPE_VXLAN_V4 \
31256 /* Enhance Generic Routing Encapsulation (GRE version 1) inside IP datagram payload */
31257 #define HWRM_CFA_ENCAP_RECORD_ALLOC_INPUT_ENCAP_TYPE_IPGRE_V1 \
31259 /* Use fixed layer 2 ether type of 0xFFFF */
31260 #define HWRM_CFA_ENCAP_RECORD_ALLOC_INPUT_ENCAP_TYPE_L2_ETYPE \
31262 /* IPV6 over virtual eXtensible Local Area Network with GPE header (IPV6oVXLANGPE) */
31263 #define HWRM_CFA_ENCAP_RECORD_ALLOC_INPUT_ENCAP_TYPE_VXLAN_GPE_V6 \
31265 #define HWRM_CFA_ENCAP_RECORD_ALLOC_INPUT_ENCAP_TYPE_LAST \
31266 HWRM_CFA_ENCAP_RECORD_ALLOC_INPUT_ENCAP_TYPE_VXLAN_GPE_V6
31267 uint8_t unused_0[3];
31268 /* This value is encap data used for the given encap type. */
31269 uint32_t encap_data[20];
31272 /* hwrm_cfa_encap_record_alloc_output (size:128b/16B) */
31273 struct hwrm_cfa_encap_record_alloc_output {
31274 /* The specific error status for the command. */
31275 uint16_t error_code;
31276 /* The HWRM command request type. */
31278 /* The sequence ID from the original command. */
31280 /* The length of the response data in number of bytes. */
31282 /* This value is an opaque id into CFA data structures. */
31283 uint32_t encap_record_id;
31284 uint8_t unused_0[3];
31286 * This field is used in Output records to indicate that the output
31287 * is completely written to RAM. This field should be read as '1'
31288 * to indicate that the output has been completely written.
31289 * When writing a command completion or response to an internal processor,
31290 * the order of writes has to be such that this field is written last.
31295 /******************************
31296 * hwrm_cfa_encap_record_free *
31297 ******************************/
31300 /* hwrm_cfa_encap_record_free_input (size:192b/24B) */
31301 struct hwrm_cfa_encap_record_free_input {
31302 /* The HWRM command request type. */
31305 * The completion ring to send the completion event on. This should
31306 * be the NQ ID returned from the `nq_alloc` HWRM command.
31308 uint16_t cmpl_ring;
31310 * The sequence ID is used by the driver for tracking multiple
31311 * commands. This ID is treated as opaque data by the firmware and
31312 * the value is returned in the `hwrm_resp_hdr` upon completion.
31316 * The target ID of the command:
31317 * * 0x0-0xFFF8 - The function ID
31318 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
31319 * * 0xFFFD - Reserved for user-space HWRM interface
31322 uint16_t target_id;
31324 * A physical address pointer pointing to a host buffer that the
31325 * command's response data will be written. This can be either a host
31326 * physical address (HPA) or a guest physical address (GPA) and must
31327 * point to a physically contiguous block of memory.
31329 uint64_t resp_addr;
31330 /* This value is an opaque id into CFA data structures. */
31331 uint32_t encap_record_id;
31332 uint8_t unused_0[4];
31335 /* hwrm_cfa_encap_record_free_output (size:128b/16B) */
31336 struct hwrm_cfa_encap_record_free_output {
31337 /* The specific error status for the command. */
31338 uint16_t error_code;
31339 /* The HWRM command request type. */
31341 /* The sequence ID from the original command. */
31343 /* The length of the response data in number of bytes. */
31345 uint8_t unused_0[7];
31347 * This field is used in Output records to indicate that the output
31348 * is completely written to RAM. This field should be read as '1'
31349 * to indicate that the output has been completely written.
31350 * When writing a command completion or response to an internal processor,
31351 * the order of writes has to be such that this field is written last.
31356 /********************************
31357 * hwrm_cfa_ntuple_filter_alloc *
31358 ********************************/
31361 /* hwrm_cfa_ntuple_filter_alloc_input (size:1024b/128B) */
31362 struct hwrm_cfa_ntuple_filter_alloc_input {
31363 /* The HWRM command request type. */
31366 * The completion ring to send the completion event on. This should
31367 * be the NQ ID returned from the `nq_alloc` HWRM command.
31369 uint16_t cmpl_ring;
31371 * The sequence ID is used by the driver for tracking multiple
31372 * commands. This ID is treated as opaque data by the firmware and
31373 * the value is returned in the `hwrm_resp_hdr` upon completion.
31377 * The target ID of the command:
31378 * * 0x0-0xFFF8 - The function ID
31379 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
31380 * * 0xFFFD - Reserved for user-space HWRM interface
31383 uint16_t target_id;
31385 * A physical address pointer pointing to a host buffer that the
31386 * command's response data will be written. This can be either a host
31387 * physical address (HPA) or a guest physical address (GPA) and must
31388 * point to a physically contiguous block of memory.
31390 uint64_t resp_addr;
31392 /* Setting of this flag indicates the applicability to the loopback path. */
31393 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_FLAGS_LOOPBACK \
31396 * Setting of this flag indicates drop action. If this flag is not set,
31397 * then it should be considered accept action.
31399 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_FLAGS_DROP \
31402 * Setting of this flag indicates that a meter is expected to be attached
31403 * to this flow. This hint can be used when choosing the action record
31404 * format required for the flow.
31406 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_FLAGS_METER \
31409 * Setting of this flag indicates that the dst_id field contains function ID.
31410 * If this is not set it indicates dest_id is VNIC or VPORT.
31412 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_FLAGS_DEST_FID \
31415 * Setting of this flag indicates match on arp reply when ethertype is 0x0806.
31416 * If this is not set it indicates no specific arp opcode matching.
31418 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_FLAGS_ARP_REPLY \
31421 * Setting of this flag indicates that the dst_id field contains RFS ring
31422 * table index. If this is not set it indicates dst_id is VNIC or VPORT
31423 * or function ID. Note dest_fid and dest_rfs_ring_idx can’t be set at
31426 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_FLAGS_DEST_RFS_RING_IDX \
31430 * This bit must be '1' for the l2_filter_id field to be
31433 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_L2_FILTER_ID \
31436 * This bit must be '1' for the ethertype field to be
31439 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_ETHERTYPE \
31442 * This bit must be '1' for the tunnel_type field to be
31445 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_TUNNEL_TYPE \
31448 * This bit must be '1' for the src_macaddr field to be
31451 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_SRC_MACADDR \
31454 * This bit must be '1' for the ipaddr_type field to be
31457 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_IPADDR_TYPE \
31460 * This bit must be '1' for the src_ipaddr field to be
31463 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_SRC_IPADDR \
31466 * This bit must be '1' for the src_ipaddr_mask field to be
31469 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_SRC_IPADDR_MASK \
31472 * This bit must be '1' for the dst_ipaddr field to be
31475 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_IPADDR \
31478 * This bit must be '1' for the dst_ipaddr_mask field to be
31481 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_IPADDR_MASK \
31484 * This bit must be '1' for the ip_protocol field to be
31487 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_IP_PROTOCOL \
31490 * This bit must be '1' for the src_port field to be
31493 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_SRC_PORT \
31496 * This bit must be '1' for the src_port_mask field to be
31499 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_SRC_PORT_MASK \
31502 * This bit must be '1' for the dst_port field to be
31505 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_PORT \
31508 * This bit must be '1' for the dst_port_mask field to be
31511 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_PORT_MASK \
31514 * This bit must be '1' for the pri_hint field to be
31517 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_PRI_HINT \
31520 * This bit must be '1' for the ntuple_filter_id field to be
31523 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_NTUPLE_FILTER_ID \
31526 * This bit must be '1' for the dst_id field to be
31529 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_ID \
31532 * This bit must be '1' for the mirror_vnic_id field to be
31535 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_MIRROR_VNIC_ID \
31538 * This bit must be '1' for the dst_macaddr field to be
31541 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_MACADDR \
31543 /* This flag is deprecated. */
31544 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_RFS_RING_TBL_IDX \
31547 * This value identifies a set of CFA data structures used for an L2
31550 uint64_t l2_filter_id;
31552 * This value indicates the source MAC address in
31553 * the Ethernet header.
31555 uint8_t src_macaddr[6];
31556 /* This value indicates the ethertype in the Ethernet header. */
31557 uint16_t ethertype;
31559 * This value indicates the type of IP address.
31562 * All others are invalid.
31564 uint8_t ip_addr_type;
31566 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_IP_ADDR_TYPE_UNKNOWN \
31569 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_IP_ADDR_TYPE_IPV4 \
31572 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_IP_ADDR_TYPE_IPV6 \
31574 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_IP_ADDR_TYPE_LAST \
31575 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_IP_ADDR_TYPE_IPV6
31577 * The value of protocol filed in IP header.
31578 * Applies to UDP and TCP traffic.
31582 uint8_t ip_protocol;
31584 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_IP_PROTOCOL_UNKNOWN \
31587 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_IP_PROTOCOL_TCP \
31590 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_IP_PROTOCOL_UDP \
31592 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_IP_PROTOCOL_LAST \
31593 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_IP_PROTOCOL_UDP
31595 * If set, this value shall represent the
31596 * Logical VNIC ID of the destination VNIC for the RX
31597 * path and network port id of the destination port for
31602 * Logical VNIC ID of the VNIC where traffic is
31605 uint16_t mirror_vnic_id;
31607 * This value indicates the tunnel type for this filter.
31608 * If this field is not specified, then the filter shall
31609 * apply to both non-tunneled and tunneled packets.
31610 * If this field conflicts with the tunnel_type specified
31611 * in the l2_filter_id, then the HWRM shall return an
31612 * error for this command.
31614 uint8_t tunnel_type;
31616 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_TUNNEL_TYPE_NONTUNNEL \
31618 /* Virtual eXtensible Local Area Network (VXLAN) */
31619 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_TUNNEL_TYPE_VXLAN \
31621 /* Network Virtualization Generic Routing Encapsulation (NVGRE) */
31622 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_TUNNEL_TYPE_NVGRE \
31624 /* Generic Routing Encapsulation (GRE) inside Ethernet payload */
31625 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_TUNNEL_TYPE_L2GRE \
31628 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_TUNNEL_TYPE_IPIP \
31630 /* Generic Network Virtualization Encapsulation (Geneve) */
31631 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_TUNNEL_TYPE_GENEVE \
31633 /* Multi-Protocol Label Switching (MPLS) */
31634 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_TUNNEL_TYPE_MPLS \
31636 /* Stateless Transport Tunnel (STT) */
31637 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_TUNNEL_TYPE_STT \
31639 /* Generic Routing Encapsulation (GRE) inside IP datagram payload */
31640 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_TUNNEL_TYPE_IPGRE \
31642 /* IPV4 over virtual eXtensible Local Area Network (IPV4oVXLAN) */
31643 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_TUNNEL_TYPE_VXLAN_V4 \
31645 /* Enhance Generic Routing Encapsulation (GRE version 1) inside IP datagram payload */
31646 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_TUNNEL_TYPE_IPGRE_V1 \
31648 /* Use fixed layer 2 ether type of 0xFFFF */
31649 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_TUNNEL_TYPE_L2_ETYPE \
31651 /* IPV6 over virtual eXtensible Local Area Network with GPE header (IPV6oVXLANGPE) */
31652 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_TUNNEL_TYPE_VXLAN_GPE_V6 \
31654 /* Any tunneled traffic */
31655 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_TUNNEL_TYPE_ANYTUNNEL \
31657 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_TUNNEL_TYPE_LAST \
31658 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_TUNNEL_TYPE_ANYTUNNEL
31660 * This hint is provided to help in placing
31661 * the filter in the filter table.
31664 /* No preference */
31665 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_PRI_HINT_NO_PREFER \
31667 /* Above the given filter */
31668 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_PRI_HINT_ABOVE \
31670 /* Below the given filter */
31671 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_PRI_HINT_BELOW \
31673 /* As high as possible */
31674 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_PRI_HINT_HIGHEST \
31676 /* As low as possible */
31677 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_PRI_HINT_LOWEST \
31679 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_PRI_HINT_LAST \
31680 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_PRI_HINT_LOWEST
31682 * The value of source IP address to be used in filtering.
31683 * For IPv4, first four bytes represent the IP address.
31685 uint32_t src_ipaddr[4];
31687 * The value of source IP address mask to be used in
31689 * For IPv4, first four bytes represent the IP address mask.
31691 uint32_t src_ipaddr_mask[4];
31693 * The value of destination IP address to be used in filtering.
31694 * For IPv4, first four bytes represent the IP address.
31696 uint32_t dst_ipaddr[4];
31698 * The value of destination IP address mask to be used in
31700 * For IPv4, first four bytes represent the IP address mask.
31702 uint32_t dst_ipaddr_mask[4];
31704 * The value of source port to be used in filtering.
31705 * Applies to UDP and TCP traffic.
31709 * The value of source port mask to be used in filtering.
31710 * Applies to UDP and TCP traffic.
31712 uint16_t src_port_mask;
31714 * The value of destination port to be used in filtering.
31715 * Applies to UDP and TCP traffic.
31719 * The value of destination port mask to be used in
31721 * Applies to UDP and TCP traffic.
31723 uint16_t dst_port_mask;
31725 * This is the ID of the filter that goes along with
31728 uint64_t ntuple_filter_id_hint;
31731 /* hwrm_cfa_ntuple_filter_alloc_output (size:192b/24B) */
31732 struct hwrm_cfa_ntuple_filter_alloc_output {
31733 /* The specific error status for the command. */
31734 uint16_t error_code;
31735 /* The HWRM command request type. */
31737 /* The sequence ID from the original command. */
31739 /* The length of the response data in number of bytes. */
31741 /* This value is an opaque id into CFA data structures. */
31742 uint64_t ntuple_filter_id;
31744 * The flow id value in bit 0-29 is the actual ID of the flow
31745 * associated with this filter and it shall be used to match
31746 * and associate the flow identifier returned in completion
31747 * records. A value of 0xFFFFFFFF in the 32-bit flow_id field
31748 * shall indicate no valid flow id.
31751 /* Indicate the flow id value. */
31752 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_OUTPUT_FLOW_ID_VALUE_MASK \
31753 UINT32_C(0x3fffffff)
31754 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_OUTPUT_FLOW_ID_VALUE_SFT 0
31755 /* Indicate type of the flow. */
31756 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_OUTPUT_FLOW_ID_TYPE \
31757 UINT32_C(0x40000000)
31759 * If this bit set to 0, then it indicates that the flow is
31762 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_OUTPUT_FLOW_ID_TYPE_INT \
31763 (UINT32_C(0x0) << 30)
31765 * If this bit is set to 1, then it indicates that the flow is
31768 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_OUTPUT_FLOW_ID_TYPE_EXT \
31769 (UINT32_C(0x1) << 30)
31770 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_OUTPUT_FLOW_ID_TYPE_LAST \
31771 HWRM_CFA_NTUPLE_FILTER_ALLOC_OUTPUT_FLOW_ID_TYPE_EXT
31772 /* Indicate the flow direction. */
31773 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_OUTPUT_FLOW_ID_DIR \
31774 UINT32_C(0x80000000)
31775 /* If this bit set to 0, then it indicates rx flow. */
31776 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_OUTPUT_FLOW_ID_DIR_RX \
31777 (UINT32_C(0x0) << 31)
31778 /* If this bit is set to 1, then it indicates that tx flow. */
31779 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_OUTPUT_FLOW_ID_DIR_TX \
31780 (UINT32_C(0x1) << 31)
31781 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_OUTPUT_FLOW_ID_DIR_LAST \
31782 HWRM_CFA_NTUPLE_FILTER_ALLOC_OUTPUT_FLOW_ID_DIR_TX
31783 uint8_t unused_0[3];
31785 * This field is used in Output records to indicate that the output
31786 * is completely written to RAM. This field should be read as '1'
31787 * to indicate that the output has been completely written.
31788 * When writing a command completion or response to an internal processor,
31789 * the order of writes has to be such that this field is written last.
31794 /* hwrm_cfa_ntuple_filter_alloc_cmd_err (size:64b/8B) */
31795 struct hwrm_cfa_ntuple_filter_alloc_cmd_err {
31797 * command specific error codes that goes to
31798 * the cmd_err field in Common HWRM Error Response.
31801 /* Unknown error */
31802 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_CMD_ERR_CODE_UNKNOWN \
31804 /* Unable to complete operation due to conflict with Rx Mask VLAN */
31805 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_CMD_ERR_CODE_RX_MASK_VLAN_CONFLICT_ERR \
31807 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_CMD_ERR_CODE_LAST \
31808 HWRM_CFA_NTUPLE_FILTER_ALLOC_CMD_ERR_CODE_RX_MASK_VLAN_CONFLICT_ERR
31809 uint8_t unused_0[7];
31812 /*******************************
31813 * hwrm_cfa_ntuple_filter_free *
31814 *******************************/
31817 /* hwrm_cfa_ntuple_filter_free_input (size:192b/24B) */
31818 struct hwrm_cfa_ntuple_filter_free_input {
31819 /* The HWRM command request type. */
31822 * The completion ring to send the completion event on. This should
31823 * be the NQ ID returned from the `nq_alloc` HWRM command.
31825 uint16_t cmpl_ring;
31827 * The sequence ID is used by the driver for tracking multiple
31828 * commands. This ID is treated as opaque data by the firmware and
31829 * the value is returned in the `hwrm_resp_hdr` upon completion.
31833 * The target ID of the command:
31834 * * 0x0-0xFFF8 - The function ID
31835 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
31836 * * 0xFFFD - Reserved for user-space HWRM interface
31839 uint16_t target_id;
31841 * A physical address pointer pointing to a host buffer that the
31842 * command's response data will be written. This can be either a host
31843 * physical address (HPA) or a guest physical address (GPA) and must
31844 * point to a physically contiguous block of memory.
31846 uint64_t resp_addr;
31847 /* This value is an opaque id into CFA data structures. */
31848 uint64_t ntuple_filter_id;
31851 /* hwrm_cfa_ntuple_filter_free_output (size:128b/16B) */
31852 struct hwrm_cfa_ntuple_filter_free_output {
31853 /* The specific error status for the command. */
31854 uint16_t error_code;
31855 /* The HWRM command request type. */
31857 /* The sequence ID from the original command. */
31859 /* The length of the response data in number of bytes. */
31861 uint8_t unused_0[7];
31863 * This field is used in Output records to indicate that the output
31864 * is completely written to RAM. This field should be read as '1'
31865 * to indicate that the output has been completely written.
31866 * When writing a command completion or response to an internal processor,
31867 * the order of writes has to be such that this field is written last.
31872 /******************************
31873 * hwrm_cfa_ntuple_filter_cfg *
31874 ******************************/
31877 /* hwrm_cfa_ntuple_filter_cfg_input (size:384b/48B) */
31878 struct hwrm_cfa_ntuple_filter_cfg_input {
31879 /* The HWRM command request type. */
31882 * The completion ring to send the completion event on. This should
31883 * be the NQ ID returned from the `nq_alloc` HWRM command.
31885 uint16_t cmpl_ring;
31887 * The sequence ID is used by the driver for tracking multiple
31888 * commands. This ID is treated as opaque data by the firmware and
31889 * the value is returned in the `hwrm_resp_hdr` upon completion.
31893 * The target ID of the command:
31894 * * 0x0-0xFFF8 - The function ID
31895 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
31896 * * 0xFFFD - Reserved for user-space HWRM interface
31899 uint16_t target_id;
31901 * A physical address pointer pointing to a host buffer that the
31902 * command's response data will be written. This can be either a host
31903 * physical address (HPA) or a guest physical address (GPA) and must
31904 * point to a physically contiguous block of memory.
31906 uint64_t resp_addr;
31909 * This bit must be '1' for the new_dst_id field to be
31912 #define HWRM_CFA_NTUPLE_FILTER_CFG_INPUT_ENABLES_NEW_DST_ID \
31915 * This bit must be '1' for the new_mirror_vnic_id field to be
31918 #define HWRM_CFA_NTUPLE_FILTER_CFG_INPUT_ENABLES_NEW_MIRROR_VNIC_ID \
31921 * This bit must be '1' for the new_meter_instance_id field to be
31924 #define HWRM_CFA_NTUPLE_FILTER_CFG_INPUT_ENABLES_NEW_METER_INSTANCE_ID \
31928 * Setting this bit to 1 indicates that dest_id field contains FID.
31929 * Setting this to 0 indicates that dest_id field contains VNIC or VPORT.
31931 #define HWRM_CFA_NTUPLE_FILTER_CFG_INPUT_FLAGS_DEST_FID \
31934 * Setting of this flag indicates that the new_dst_id field contains
31935 * RFS ring table index. If this is not set it indicates new_dst_id is
31936 * VNIC or VPORT or function ID. Note dest_fid and dest_rfs_ring_idx
31937 * can’t be set at the same time.
31939 #define HWRM_CFA_NTUPLE_FILTER_CFG_INPUT_FLAGS_DEST_RFS_RING_IDX \
31941 /* This value is an opaque id into CFA data structures. */
31942 uint64_t ntuple_filter_id;
31944 * If set, this value shall represent the new
31945 * Logical VNIC ID of the destination VNIC for the RX
31946 * path and new network port id of the destination port for
31949 uint32_t new_dst_id;
31951 * New Logical VNIC ID of the VNIC where traffic is
31954 uint32_t new_mirror_vnic_id;
31956 * New meter to attach to the flow. Specifying the
31957 * invalid instance ID is used to remove any existing
31958 * meter from the flow.
31960 uint16_t new_meter_instance_id;
31962 * A value of 0xfff is considered invalid and implies the
31963 * instance is not configured.
31965 #define HWRM_CFA_NTUPLE_FILTER_CFG_INPUT_NEW_METER_INSTANCE_ID_INVALID \
31967 #define HWRM_CFA_NTUPLE_FILTER_CFG_INPUT_NEW_METER_INSTANCE_ID_LAST \
31968 HWRM_CFA_NTUPLE_FILTER_CFG_INPUT_NEW_METER_INSTANCE_ID_INVALID
31969 uint8_t unused_1[6];
31972 /* hwrm_cfa_ntuple_filter_cfg_output (size:128b/16B) */
31973 struct hwrm_cfa_ntuple_filter_cfg_output {
31974 /* The specific error status for the command. */
31975 uint16_t error_code;
31976 /* The HWRM command request type. */
31978 /* The sequence ID from the original command. */
31980 /* The length of the response data in number of bytes. */
31982 uint8_t unused_0[7];
31984 * This field is used in Output records to indicate that the output
31985 * is completely written to RAM. This field should be read as '1'
31986 * to indicate that the output has been completely written.
31987 * When writing a command completion or response to an internal processor,
31988 * the order of writes has to be such that this field is written last.
31993 /**************************
31994 * hwrm_cfa_em_flow_alloc *
31995 **************************/
31998 /* hwrm_cfa_em_flow_alloc_input (size:896b/112B) */
31999 struct hwrm_cfa_em_flow_alloc_input {
32000 /* The HWRM command request type. */
32003 * The completion ring to send the completion event on. This should
32004 * be the NQ ID returned from the `nq_alloc` HWRM command.
32006 uint16_t cmpl_ring;
32008 * The sequence ID is used by the driver for tracking multiple
32009 * commands. This ID is treated as opaque data by the firmware and
32010 * the value is returned in the `hwrm_resp_hdr` upon completion.
32014 * The target ID of the command:
32015 * * 0x0-0xFFF8 - The function ID
32016 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
32017 * * 0xFFFD - Reserved for user-space HWRM interface
32020 uint16_t target_id;
32022 * A physical address pointer pointing to a host buffer that the
32023 * command's response data will be written. This can be either a host
32024 * physical address (HPA) or a guest physical address (GPA) and must
32025 * point to a physically contiguous block of memory.
32027 uint64_t resp_addr;
32030 * Enumeration denoting the RX, TX type of the resource.
32031 * This enumeration is used for resources that are similar for both
32032 * TX and RX paths of the chip.
32034 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_FLAGS_PATH UINT32_C(0x1)
32036 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_FLAGS_PATH_TX UINT32_C(0x0)
32038 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_FLAGS_PATH_RX UINT32_C(0x1)
32039 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_FLAGS_PATH_LAST \
32040 HWRM_CFA_EM_FLOW_ALLOC_INPUT_FLAGS_PATH_RX
32042 * Setting of this flag indicates enabling of a byte counter for a given
32045 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_FLAGS_BYTE_CTR UINT32_C(0x2)
32047 * Setting of this flag indicates enabling of a packet counter for a given
32050 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_FLAGS_PKT_CTR UINT32_C(0x4)
32051 /* Setting of this flag indicates de-capsulation action for the given flow. */
32052 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_FLAGS_DECAP UINT32_C(0x8)
32053 /* Setting of this flag indicates encapsulation action for the given flow. */
32054 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_FLAGS_ENCAP UINT32_C(0x10)
32056 * Setting of this flag indicates drop action. If this flag is not set,
32057 * then it should be considered accept action.
32059 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_FLAGS_DROP UINT32_C(0x20)
32061 * Setting of this flag indicates that a meter is expected to be attached
32062 * to this flow. This hint can be used when choosing the action record
32063 * format required for the flow.
32065 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_FLAGS_METER UINT32_C(0x40)
32068 * This bit must be '1' for the l2_filter_id field to be
32071 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_L2_FILTER_ID \
32074 * This bit must be '1' for the tunnel_type field to be
32077 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_TUNNEL_TYPE \
32080 * This bit must be '1' for the tunnel_id field to be
32083 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_TUNNEL_ID \
32086 * This bit must be '1' for the src_macaddr field to be
32089 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_SRC_MACADDR \
32092 * This bit must be '1' for the dst_macaddr field to be
32095 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_DST_MACADDR \
32098 * This bit must be '1' for the ovlan_vid field to be
32101 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_OVLAN_VID \
32104 * This bit must be '1' for the ivlan_vid field to be
32107 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_IVLAN_VID \
32110 * This bit must be '1' for the ethertype field to be
32113 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_ETHERTYPE \
32116 * This bit must be '1' for the src_ipaddr field to be
32119 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_SRC_IPADDR \
32122 * This bit must be '1' for the dst_ipaddr field to be
32125 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_DST_IPADDR \
32128 * This bit must be '1' for the ipaddr_type field to be
32131 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_IPADDR_TYPE \
32134 * This bit must be '1' for the ip_protocol field to be
32137 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_IP_PROTOCOL \
32140 * This bit must be '1' for the src_port field to be
32143 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_SRC_PORT \
32146 * This bit must be '1' for the dst_port field to be
32149 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_DST_PORT \
32152 * This bit must be '1' for the dst_id field to be
32155 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_DST_ID \
32158 * This bit must be '1' for the mirror_vnic_id field to be
32161 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_MIRROR_VNIC_ID \
32164 * This bit must be '1' for the encap_record_id field to be
32167 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_ENCAP_RECORD_ID \
32170 * This bit must be '1' for the meter_instance_id field to be
32173 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_METER_INSTANCE_ID \
32176 * This value identifies a set of CFA data structures used for an L2
32179 uint64_t l2_filter_id;
32181 uint8_t tunnel_type;
32183 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_TUNNEL_TYPE_NONTUNNEL \
32185 /* Virtual eXtensible Local Area Network (VXLAN) */
32186 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_TUNNEL_TYPE_VXLAN \
32188 /* Network Virtualization Generic Routing Encapsulation (NVGRE) */
32189 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_TUNNEL_TYPE_NVGRE \
32191 /* Generic Routing Encapsulation (GRE) inside Ethernet payload */
32192 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_TUNNEL_TYPE_L2GRE \
32195 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_TUNNEL_TYPE_IPIP \
32197 /* Generic Network Virtualization Encapsulation (Geneve) */
32198 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_TUNNEL_TYPE_GENEVE \
32200 /* Multi-Protocol Label Switching (MPLS) */
32201 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_TUNNEL_TYPE_MPLS \
32203 /* Stateless Transport Tunnel (STT) */
32204 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_TUNNEL_TYPE_STT \
32206 /* Generic Routing Encapsulation (GRE) inside IP datagram payload */
32207 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_TUNNEL_TYPE_IPGRE \
32209 /* IPV4 over virtual eXtensible Local Area Network (IPV4oVXLAN) */
32210 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_TUNNEL_TYPE_VXLAN_V4 \
32212 /* Enhance Generic Routing Encapsulation (GRE version 1) inside IP datagram payload */
32213 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_TUNNEL_TYPE_IPGRE_V1 \
32215 /* Use fixed layer 2 ether type of 0xFFFF */
32216 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_TUNNEL_TYPE_L2_ETYPE \
32218 /* IPV6 over virtual eXtensible Local Area Network with GPE header (IPV6oVXLANGPE) */
32219 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_TUNNEL_TYPE_VXLAN_GPE_V6 \
32221 /* Any tunneled traffic */
32222 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_TUNNEL_TYPE_ANYTUNNEL \
32224 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_TUNNEL_TYPE_LAST \
32225 HWRM_CFA_EM_FLOW_ALLOC_INPUT_TUNNEL_TYPE_ANYTUNNEL
32226 uint8_t unused_0[3];
32228 * Tunnel identifier.
32229 * Virtual Network Identifier (VNI). Only valid with
32230 * tunnel_types VXLAN, NVGRE, and Geneve.
32231 * Only lower 24-bits of VNI field are used
32232 * in setting up the filter.
32234 uint32_t tunnel_id;
32236 * This value indicates the source MAC address in
32237 * the Ethernet header.
32239 uint8_t src_macaddr[6];
32240 /* The meter instance to attach to the flow. */
32241 uint16_t meter_instance_id;
32243 * A value of 0xfff is considered invalid and implies the
32244 * instance is not configured.
32246 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_METER_INSTANCE_ID_INVALID \
32248 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_METER_INSTANCE_ID_LAST \
32249 HWRM_CFA_EM_FLOW_ALLOC_INPUT_METER_INSTANCE_ID_INVALID
32251 * This value indicates the destination MAC address in
32252 * the Ethernet header.
32254 uint8_t dst_macaddr[6];
32256 * This value indicates the VLAN ID of the outer VLAN tag
32257 * in the Ethernet header.
32259 uint16_t ovlan_vid;
32261 * This value indicates the VLAN ID of the inner VLAN tag
32262 * in the Ethernet header.
32264 uint16_t ivlan_vid;
32265 /* This value indicates the ethertype in the Ethernet header. */
32266 uint16_t ethertype;
32268 * This value indicates the type of IP address.
32271 * All others are invalid.
32273 uint8_t ip_addr_type;
32275 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_IP_ADDR_TYPE_UNKNOWN UINT32_C(0x0)
32277 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_IP_ADDR_TYPE_IPV4 UINT32_C(0x4)
32279 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_IP_ADDR_TYPE_IPV6 UINT32_C(0x6)
32280 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_IP_ADDR_TYPE_LAST \
32281 HWRM_CFA_EM_FLOW_ALLOC_INPUT_IP_ADDR_TYPE_IPV6
32283 * The value of protocol filed in IP header.
32284 * Applies to UDP and TCP traffic.
32288 uint8_t ip_protocol;
32290 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_IP_PROTOCOL_UNKNOWN UINT32_C(0x0)
32292 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_IP_PROTOCOL_TCP UINT32_C(0x6)
32294 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_IP_PROTOCOL_UDP UINT32_C(0x11)
32295 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_IP_PROTOCOL_LAST \
32296 HWRM_CFA_EM_FLOW_ALLOC_INPUT_IP_PROTOCOL_UDP
32297 uint8_t unused_1[2];
32299 * The value of source IP address to be used in filtering.
32300 * For IPv4, first four bytes represent the IP address.
32302 uint32_t src_ipaddr[4];
32304 * big_endian = True
32305 * The value of destination IP address to be used in filtering.
32306 * For IPv4, first four bytes represent the IP address.
32308 uint32_t dst_ipaddr[4];
32310 * The value of source port to be used in filtering.
32311 * Applies to UDP and TCP traffic.
32315 * The value of destination port to be used in filtering.
32316 * Applies to UDP and TCP traffic.
32320 * If set, this value shall represent the
32321 * Logical VNIC ID of the destination VNIC for the RX
32322 * path and network port id of the destination port for
32327 * Logical VNIC ID of the VNIC where traffic is
32330 uint16_t mirror_vnic_id;
32331 /* Logical ID of the encapsulation record. */
32332 uint32_t encap_record_id;
32333 uint8_t unused_2[4];
32336 /* hwrm_cfa_em_flow_alloc_output (size:192b/24B) */
32337 struct hwrm_cfa_em_flow_alloc_output {
32338 /* The specific error status for the command. */
32339 uint16_t error_code;
32340 /* The HWRM command request type. */
32342 /* The sequence ID from the original command. */
32344 /* The length of the response data in number of bytes. */
32346 /* This value is an opaque id into CFA data structures. */
32347 uint64_t em_filter_id;
32349 * The flow id value in bit 0-29 is the actual ID of the flow
32350 * associated with this filter and it shall be used to match
32351 * and associate the flow identifier returned in completion
32352 * records. A value of 0xFFFFFFFF in the 32-bit flow_id field
32353 * shall indicate no valid flow id.
32356 /* Indicate the flow id value. */
32357 #define HWRM_CFA_EM_FLOW_ALLOC_OUTPUT_FLOW_ID_VALUE_MASK \
32358 UINT32_C(0x3fffffff)
32359 #define HWRM_CFA_EM_FLOW_ALLOC_OUTPUT_FLOW_ID_VALUE_SFT 0
32360 /* Indicate type of the flow. */
32361 #define HWRM_CFA_EM_FLOW_ALLOC_OUTPUT_FLOW_ID_TYPE \
32362 UINT32_C(0x40000000)
32364 * If this bit set to 0, then it indicates that the flow is
32367 #define HWRM_CFA_EM_FLOW_ALLOC_OUTPUT_FLOW_ID_TYPE_INT \
32368 (UINT32_C(0x0) << 30)
32370 * If this bit is set to 1, then it indicates that the flow is
32373 #define HWRM_CFA_EM_FLOW_ALLOC_OUTPUT_FLOW_ID_TYPE_EXT \
32374 (UINT32_C(0x1) << 30)
32375 #define HWRM_CFA_EM_FLOW_ALLOC_OUTPUT_FLOW_ID_TYPE_LAST \
32376 HWRM_CFA_EM_FLOW_ALLOC_OUTPUT_FLOW_ID_TYPE_EXT
32377 /* Indicate the flow direction. */
32378 #define HWRM_CFA_EM_FLOW_ALLOC_OUTPUT_FLOW_ID_DIR \
32379 UINT32_C(0x80000000)
32380 /* If this bit set to 0, then it indicates rx flow. */
32381 #define HWRM_CFA_EM_FLOW_ALLOC_OUTPUT_FLOW_ID_DIR_RX \
32382 (UINT32_C(0x0) << 31)
32383 /* If this bit is set to 1, then it indicates that tx flow. */
32384 #define HWRM_CFA_EM_FLOW_ALLOC_OUTPUT_FLOW_ID_DIR_TX \
32385 (UINT32_C(0x1) << 31)
32386 #define HWRM_CFA_EM_FLOW_ALLOC_OUTPUT_FLOW_ID_DIR_LAST \
32387 HWRM_CFA_EM_FLOW_ALLOC_OUTPUT_FLOW_ID_DIR_TX
32388 uint8_t unused_0[3];
32390 * This field is used in Output records to indicate that the output
32391 * is completely written to RAM. This field should be read as '1'
32392 * to indicate that the output has been completely written.
32393 * When writing a command completion or response to an internal processor,
32394 * the order of writes has to be such that this field is written last.
32399 /*************************
32400 * hwrm_cfa_em_flow_free *
32401 *************************/
32404 /* hwrm_cfa_em_flow_free_input (size:192b/24B) */
32405 struct hwrm_cfa_em_flow_free_input {
32406 /* The HWRM command request type. */
32409 * The completion ring to send the completion event on. This should
32410 * be the NQ ID returned from the `nq_alloc` HWRM command.
32412 uint16_t cmpl_ring;
32414 * The sequence ID is used by the driver for tracking multiple
32415 * commands. This ID is treated as opaque data by the firmware and
32416 * the value is returned in the `hwrm_resp_hdr` upon completion.
32420 * The target ID of the command:
32421 * * 0x0-0xFFF8 - The function ID
32422 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
32423 * * 0xFFFD - Reserved for user-space HWRM interface
32426 uint16_t target_id;
32428 * A physical address pointer pointing to a host buffer that the
32429 * command's response data will be written. This can be either a host
32430 * physical address (HPA) or a guest physical address (GPA) and must
32431 * point to a physically contiguous block of memory.
32433 uint64_t resp_addr;
32434 /* This value is an opaque id into CFA data structures. */
32435 uint64_t em_filter_id;
32438 /* hwrm_cfa_em_flow_free_output (size:128b/16B) */
32439 struct hwrm_cfa_em_flow_free_output {
32440 /* The specific error status for the command. */
32441 uint16_t error_code;
32442 /* The HWRM command request type. */
32444 /* The sequence ID from the original command. */
32446 /* The length of the response data in number of bytes. */
32448 uint8_t unused_0[7];
32450 * This field is used in Output records to indicate that the output
32451 * is completely written to RAM. This field should be read as '1'
32452 * to indicate that the output has been completely written.
32453 * When writing a command completion or response to an internal processor,
32454 * the order of writes has to be such that this field is written last.
32459 /************************
32460 * hwrm_cfa_meter_qcaps *
32461 ************************/
32464 /* hwrm_cfa_meter_qcaps_input (size:128b/16B) */
32465 struct hwrm_cfa_meter_qcaps_input {
32466 /* The HWRM command request type. */
32469 * The completion ring to send the completion event on. This should
32470 * be the NQ ID returned from the `nq_alloc` HWRM command.
32472 uint16_t cmpl_ring;
32474 * The sequence ID is used by the driver for tracking multiple
32475 * commands. This ID is treated as opaque data by the firmware and
32476 * the value is returned in the `hwrm_resp_hdr` upon completion.
32480 * The target ID of the command:
32481 * * 0x0-0xFFF8 - The function ID
32482 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
32483 * * 0xFFFD - Reserved for user-space HWRM interface
32486 uint16_t target_id;
32488 * A physical address pointer pointing to a host buffer that the
32489 * command's response data will be written. This can be either a host
32490 * physical address (HPA) or a guest physical address (GPA) and must
32491 * point to a physically contiguous block of memory.
32493 uint64_t resp_addr;
32496 /* hwrm_cfa_meter_qcaps_output (size:320b/40B) */
32497 struct hwrm_cfa_meter_qcaps_output {
32498 /* The specific error status for the command. */
32499 uint16_t error_code;
32500 /* The HWRM command request type. */
32502 /* The sequence ID from the original command. */
32504 /* The length of the response data in number of bytes. */
32508 * Enumeration denoting the clock at which the Meter is running with.
32509 * This enumeration is used for resources that are similar for both
32510 * TX and RX paths of the chip.
32512 #define HWRM_CFA_METER_QCAPS_OUTPUT_FLAGS_CLOCK_MASK UINT32_C(0xf)
32513 #define HWRM_CFA_METER_QCAPS_OUTPUT_FLAGS_CLOCK_SFT 0
32515 #define HWRM_CFA_METER_QCAPS_OUTPUT_FLAGS_CLOCK_375MHZ UINT32_C(0x0)
32517 #define HWRM_CFA_METER_QCAPS_OUTPUT_FLAGS_CLOCK_625MHZ UINT32_C(0x1)
32518 #define HWRM_CFA_METER_QCAPS_OUTPUT_FLAGS_CLOCK_LAST \
32519 HWRM_CFA_METER_QCAPS_OUTPUT_FLAGS_CLOCK_625MHZ
32520 uint8_t unused_0[4];
32522 * The minimum guaranteed number of tx meter profiles supported
32523 * for this function.
32525 uint16_t min_tx_profile;
32527 * The maximum non-guaranteed number of tx meter profiles supported
32528 * for this function.
32530 uint16_t max_tx_profile;
32532 * The minimum guaranteed number of rx meter profiles supported
32533 * for this function.
32535 uint16_t min_rx_profile;
32537 * The maximum non-guaranteed number of rx meter profiles supported
32538 * for this function.
32540 uint16_t max_rx_profile;
32542 * The minimum guaranteed number of tx meter instances supported
32543 * for this function.
32545 uint16_t min_tx_instance;
32547 * The maximum non-guaranteed number of tx meter instances supported
32548 * for this function.
32550 uint16_t max_tx_instance;
32552 * The minimum guaranteed number of rx meter instances supported
32553 * for this function.
32555 uint16_t min_rx_instance;
32557 * The maximum non-guaranteed number of rx meter instances supported
32558 * for this function.
32560 uint16_t max_rx_instance;
32561 uint8_t unused_1[7];
32563 * This field is used in Output records to indicate that the output
32564 * is completely written to RAM. This field should be read as '1'
32565 * to indicate that the output has been completely written.
32566 * When writing a command completion or response to an internal processor,
32567 * the order of writes has to be such that this field is written last.
32572 /********************************
32573 * hwrm_cfa_meter_profile_alloc *
32574 ********************************/
32577 /* hwrm_cfa_meter_profile_alloc_input (size:320b/40B) */
32578 struct hwrm_cfa_meter_profile_alloc_input {
32579 /* The HWRM command request type. */
32582 * The completion ring to send the completion event on. This should
32583 * be the NQ ID returned from the `nq_alloc` HWRM command.
32585 uint16_t cmpl_ring;
32587 * The sequence ID is used by the driver for tracking multiple
32588 * commands. This ID is treated as opaque data by the firmware and
32589 * the value is returned in the `hwrm_resp_hdr` upon completion.
32593 * The target ID of the command:
32594 * * 0x0-0xFFF8 - The function ID
32595 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
32596 * * 0xFFFD - Reserved for user-space HWRM interface
32599 uint16_t target_id;
32601 * A physical address pointer pointing to a host buffer that the
32602 * command's response data will be written. This can be either a host
32603 * physical address (HPA) or a guest physical address (GPA) and must
32604 * point to a physically contiguous block of memory.
32606 uint64_t resp_addr;
32609 * Enumeration denoting the RX, TX type of the resource.
32610 * This enumeration is used for resources that are similar for both
32611 * TX and RX paths of the chip.
32613 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_FLAGS_PATH UINT32_C(0x1)
32615 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_FLAGS_PATH_TX \
32618 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_FLAGS_PATH_RX \
32620 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_FLAGS_PATH_LAST \
32621 HWRM_CFA_METER_PROFILE_ALLOC_INPUT_FLAGS_PATH_RX
32622 /* The meter algorithm type. */
32623 uint8_t meter_type;
32624 /* RFC 2697 (srTCM) */
32625 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_METER_TYPE_RFC2697 \
32627 /* RFC 2698 (trTCM) */
32628 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_METER_TYPE_RFC2698 \
32630 /* RFC 4115 (trTCM) */
32631 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_METER_TYPE_RFC4115 \
32633 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_METER_TYPE_LAST \
32634 HWRM_CFA_METER_PROFILE_ALLOC_INPUT_METER_TYPE_RFC4115
32636 * This field is reserved for the future use.
32637 * It shall be set to 0.
32639 uint16_t reserved1;
32641 * This field is reserved for the future use.
32642 * It shall be set to 0.
32644 uint32_t reserved2;
32645 /* A meter rate specified in bytes-per-second. */
32646 uint32_t commit_rate;
32647 /* The bandwidth value. */
32648 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_RATE_BW_VALUE_MASK \
32649 UINT32_C(0xfffffff)
32650 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_RATE_BW_VALUE_SFT \
32652 /* The granularity of the value (bits or bytes). */
32653 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_RATE_SCALE \
32654 UINT32_C(0x10000000)
32655 /* Value is in bits. */
32656 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_RATE_SCALE_BITS \
32657 (UINT32_C(0x0) << 28)
32658 /* Value is in bytes. */
32659 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_RATE_SCALE_BYTES \
32660 (UINT32_C(0x1) << 28)
32661 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_RATE_SCALE_LAST \
32662 HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_RATE_SCALE_BYTES
32663 /* bw_value_unit is 3 b */
32664 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_RATE_BW_VALUE_UNIT_MASK \
32665 UINT32_C(0xe0000000)
32666 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_RATE_BW_VALUE_UNIT_SFT \
32668 /* Value is in Mb or MB (base 10). */
32669 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_RATE_BW_VALUE_UNIT_MEGA \
32670 (UINT32_C(0x0) << 29)
32671 /* Value is in Kb or KB (base 10). */
32672 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_RATE_BW_VALUE_UNIT_KILO \
32673 (UINT32_C(0x2) << 29)
32674 /* Value is in bits or bytes. */
32675 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_RATE_BW_VALUE_UNIT_BASE \
32676 (UINT32_C(0x4) << 29)
32677 /* Value is in Gb or GB (base 10). */
32678 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_RATE_BW_VALUE_UNIT_GIGA \
32679 (UINT32_C(0x6) << 29)
32680 /* Value is in 1/100th of a percentage of total bandwidth. */
32681 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_RATE_BW_VALUE_UNIT_PERCENT1_100 \
32682 (UINT32_C(0x1) << 29)
32684 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_RATE_BW_VALUE_UNIT_RAW \
32685 (UINT32_C(0x7) << 29)
32686 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_RATE_BW_VALUE_UNIT_LAST \
32687 HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_RATE_BW_VALUE_UNIT_RAW
32688 /* A meter burst size specified in bytes. */
32689 uint32_t commit_burst;
32690 /* The bandwidth value. */
32691 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_BURST_BW_VALUE_MASK \
32692 UINT32_C(0xfffffff)
32693 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_BURST_BW_VALUE_SFT \
32695 /* The granularity of the value (bits or bytes). */
32696 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_BURST_SCALE \
32697 UINT32_C(0x10000000)
32698 /* Value is in bits. */
32699 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_BURST_SCALE_BITS \
32700 (UINT32_C(0x0) << 28)
32701 /* Value is in bytes. */
32702 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_BURST_SCALE_BYTES \
32703 (UINT32_C(0x1) << 28)
32704 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_BURST_SCALE_LAST \
32705 HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_BURST_SCALE_BYTES
32706 /* bw_value_unit is 3 b */
32707 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_BURST_BW_VALUE_UNIT_MASK \
32708 UINT32_C(0xe0000000)
32709 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_BURST_BW_VALUE_UNIT_SFT \
32711 /* Value is in Mb or MB (base 10). */
32712 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_BURST_BW_VALUE_UNIT_MEGA \
32713 (UINT32_C(0x0) << 29)
32714 /* Value is in Kb or KB (base 10). */
32715 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_BURST_BW_VALUE_UNIT_KILO \
32716 (UINT32_C(0x2) << 29)
32717 /* Value is in bits or bytes. */
32718 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_BURST_BW_VALUE_UNIT_BASE \
32719 (UINT32_C(0x4) << 29)
32720 /* Value is in Gb or GB (base 10). */
32721 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_BURST_BW_VALUE_UNIT_GIGA \
32722 (UINT32_C(0x6) << 29)
32723 /* Value is in 1/100th of a percentage of total bandwidth. */
32724 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_BURST_BW_VALUE_UNIT_PERCENT1_100 \
32725 (UINT32_C(0x1) << 29)
32726 /* Invalid value */
32727 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_BURST_BW_VALUE_UNIT_INVALID \
32728 (UINT32_C(0x7) << 29)
32729 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_BURST_BW_VALUE_UNIT_LAST \
32730 HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_BURST_BW_VALUE_UNIT_INVALID
32731 /* A meter rate specified in bytes-per-second. */
32732 uint32_t excess_peak_rate;
32733 /* The bandwidth value. */
32734 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_RATE_BW_VALUE_MASK \
32735 UINT32_C(0xfffffff)
32736 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_RATE_BW_VALUE_SFT \
32738 /* The granularity of the value (bits or bytes). */
32739 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_RATE_SCALE \
32740 UINT32_C(0x10000000)
32741 /* Value is in bits. */
32742 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_RATE_SCALE_BITS \
32743 (UINT32_C(0x0) << 28)
32744 /* Value is in bytes. */
32745 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_RATE_SCALE_BYTES \
32746 (UINT32_C(0x1) << 28)
32747 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_RATE_SCALE_LAST \
32748 HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_RATE_SCALE_BYTES
32749 /* bw_value_unit is 3 b */
32750 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_RATE_BW_VALUE_UNIT_MASK \
32751 UINT32_C(0xe0000000)
32752 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_RATE_BW_VALUE_UNIT_SFT \
32754 /* Value is in Mb or MB (base 10). */
32755 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_RATE_BW_VALUE_UNIT_MEGA \
32756 (UINT32_C(0x0) << 29)
32757 /* Value is in Kb or KB (base 10). */
32758 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_RATE_BW_VALUE_UNIT_KILO \
32759 (UINT32_C(0x2) << 29)
32760 /* Value is in bits or bytes. */
32761 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_RATE_BW_VALUE_UNIT_BASE \
32762 (UINT32_C(0x4) << 29)
32763 /* Value is in Gb or GB (base 10). */
32764 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_RATE_BW_VALUE_UNIT_GIGA \
32765 (UINT32_C(0x6) << 29)
32766 /* Value is in 1/100th of a percentage of total bandwidth. */
32767 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_RATE_BW_VALUE_UNIT_PERCENT1_100 \
32768 (UINT32_C(0x1) << 29)
32770 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_RATE_BW_VALUE_UNIT_RAW \
32771 (UINT32_C(0x7) << 29)
32772 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_RATE_BW_VALUE_UNIT_LAST \
32773 HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_RATE_BW_VALUE_UNIT_RAW
32774 /* A meter burst size specified in bytes. */
32775 uint32_t excess_peak_burst;
32776 /* The bandwidth value. */
32777 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_BURST_BW_VALUE_MASK \
32778 UINT32_C(0xfffffff)
32779 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_BURST_BW_VALUE_SFT \
32781 /* The granularity of the value (bits or bytes). */
32782 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_BURST_SCALE \
32783 UINT32_C(0x10000000)
32784 /* Value is in bits. */
32785 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_BURST_SCALE_BITS \
32786 (UINT32_C(0x0) << 28)
32787 /* Value is in bytes. */
32788 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_BURST_SCALE_BYTES \
32789 (UINT32_C(0x1) << 28)
32790 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_BURST_SCALE_LAST \
32791 HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_BURST_SCALE_BYTES
32792 /* bw_value_unit is 3 b */
32793 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_BURST_BW_VALUE_UNIT_MASK \
32794 UINT32_C(0xe0000000)
32795 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_BURST_BW_VALUE_UNIT_SFT \
32797 /* Value is in Mb or MB (base 10). */
32798 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_BURST_BW_VALUE_UNIT_MEGA \
32799 (UINT32_C(0x0) << 29)
32800 /* Value is in Kb or KB (base 10). */
32801 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_BURST_BW_VALUE_UNIT_KILO \
32802 (UINT32_C(0x2) << 29)
32803 /* Value is in bits or bytes. */
32804 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_BURST_BW_VALUE_UNIT_BASE \
32805 (UINT32_C(0x4) << 29)
32806 /* Value is in Gb or GB (base 10). */
32807 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_BURST_BW_VALUE_UNIT_GIGA \
32808 (UINT32_C(0x6) << 29)
32809 /* Value is in 1/100th of a percentage of total bandwidth. */
32810 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_BURST_BW_VALUE_UNIT_PERCENT1_100 \
32811 (UINT32_C(0x1) << 29)
32813 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_BURST_BW_VALUE_UNIT_INVALID \
32814 (UINT32_C(0x7) << 29)
32815 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_BURST_BW_VALUE_UNIT_LAST \
32816 HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_BURST_BW_VALUE_UNIT_INVALID
32819 /* hwrm_cfa_meter_profile_alloc_output (size:128b/16B) */
32820 struct hwrm_cfa_meter_profile_alloc_output {
32821 /* The specific error status for the command. */
32822 uint16_t error_code;
32823 /* The HWRM command request type. */
32825 /* The sequence ID from the original command. */
32827 /* The length of the response data in number of bytes. */
32829 /* This value identifies a meter profile in CFA. */
32830 uint16_t meter_profile_id;
32832 * A value of 0xfff is considered invalid and implies the
32833 * profile is not configured.
32835 #define HWRM_CFA_METER_PROFILE_ALLOC_OUTPUT_METER_PROFILE_ID_INVALID \
32837 #define HWRM_CFA_METER_PROFILE_ALLOC_OUTPUT_METER_PROFILE_ID_LAST \
32838 HWRM_CFA_METER_PROFILE_ALLOC_OUTPUT_METER_PROFILE_ID_INVALID
32839 uint8_t unused_0[5];
32841 * This field is used in Output records to indicate that the output
32842 * is completely written to RAM. This field should be read as '1'
32843 * to indicate that the output has been completely written.
32844 * When writing a command completion or response to an internal processor,
32845 * the order of writes has to be such that this field is written last.
32850 /*******************************
32851 * hwrm_cfa_meter_profile_free *
32852 *******************************/
32855 /* hwrm_cfa_meter_profile_free_input (size:192b/24B) */
32856 struct hwrm_cfa_meter_profile_free_input {
32857 /* The HWRM command request type. */
32860 * The completion ring to send the completion event on. This should
32861 * be the NQ ID returned from the `nq_alloc` HWRM command.
32863 uint16_t cmpl_ring;
32865 * The sequence ID is used by the driver for tracking multiple
32866 * commands. This ID is treated as opaque data by the firmware and
32867 * the value is returned in the `hwrm_resp_hdr` upon completion.
32871 * The target ID of the command:
32872 * * 0x0-0xFFF8 - The function ID
32873 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
32874 * * 0xFFFD - Reserved for user-space HWRM interface
32877 uint16_t target_id;
32879 * A physical address pointer pointing to a host buffer that the
32880 * command's response data will be written. This can be either a host
32881 * physical address (HPA) or a guest physical address (GPA) and must
32882 * point to a physically contiguous block of memory.
32884 uint64_t resp_addr;
32887 * Enumeration denoting the RX, TX type of the resource.
32888 * This enumeration is used for resources that are similar for both
32889 * TX and RX paths of the chip.
32891 #define HWRM_CFA_METER_PROFILE_FREE_INPUT_FLAGS_PATH UINT32_C(0x1)
32893 #define HWRM_CFA_METER_PROFILE_FREE_INPUT_FLAGS_PATH_TX \
32896 #define HWRM_CFA_METER_PROFILE_FREE_INPUT_FLAGS_PATH_RX \
32898 #define HWRM_CFA_METER_PROFILE_FREE_INPUT_FLAGS_PATH_LAST \
32899 HWRM_CFA_METER_PROFILE_FREE_INPUT_FLAGS_PATH_RX
32901 /* This value identifies a meter profile in CFA. */
32902 uint16_t meter_profile_id;
32904 * A value of 0xfff is considered invalid and implies the
32905 * profile is not configured.
32907 #define HWRM_CFA_METER_PROFILE_FREE_INPUT_METER_PROFILE_ID_INVALID \
32909 #define HWRM_CFA_METER_PROFILE_FREE_INPUT_METER_PROFILE_ID_LAST \
32910 HWRM_CFA_METER_PROFILE_FREE_INPUT_METER_PROFILE_ID_INVALID
32911 uint8_t unused_1[4];
32914 /* hwrm_cfa_meter_profile_free_output (size:128b/16B) */
32915 struct hwrm_cfa_meter_profile_free_output {
32916 /* The specific error status for the command. */
32917 uint16_t error_code;
32918 /* The HWRM command request type. */
32920 /* The sequence ID from the original command. */
32922 /* The length of the response data in number of bytes. */
32924 uint8_t unused_0[7];
32926 * This field is used in Output records to indicate that the output
32927 * is completely written to RAM. This field should be read as '1'
32928 * to indicate that the output has been completely written.
32929 * When writing a command completion or response to an internal processor,
32930 * the order of writes has to be such that this field is written last.
32935 /******************************
32936 * hwrm_cfa_meter_profile_cfg *
32937 ******************************/
32940 /* hwrm_cfa_meter_profile_cfg_input (size:320b/40B) */
32941 struct hwrm_cfa_meter_profile_cfg_input {
32942 /* The HWRM command request type. */
32945 * The completion ring to send the completion event on. This should
32946 * be the NQ ID returned from the `nq_alloc` HWRM command.
32948 uint16_t cmpl_ring;
32950 * The sequence ID is used by the driver for tracking multiple
32951 * commands. This ID is treated as opaque data by the firmware and
32952 * the value is returned in the `hwrm_resp_hdr` upon completion.
32956 * The target ID of the command:
32957 * * 0x0-0xFFF8 - The function ID
32958 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
32959 * * 0xFFFD - Reserved for user-space HWRM interface
32962 uint16_t target_id;
32964 * A physical address pointer pointing to a host buffer that the
32965 * command's response data will be written. This can be either a host
32966 * physical address (HPA) or a guest physical address (GPA) and must
32967 * point to a physically contiguous block of memory.
32969 uint64_t resp_addr;
32972 * Enumeration denoting the RX, TX type of the resource.
32973 * This enumeration is used for resources that are similar for both
32974 * TX and RX paths of the chip.
32976 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_FLAGS_PATH UINT32_C(0x1)
32978 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_FLAGS_PATH_TX UINT32_C(0x0)
32980 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_FLAGS_PATH_RX UINT32_C(0x1)
32981 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_FLAGS_PATH_LAST \
32982 HWRM_CFA_METER_PROFILE_CFG_INPUT_FLAGS_PATH_RX
32983 /* The meter algorithm type. */
32984 uint8_t meter_type;
32985 /* RFC 2697 (srTCM) */
32986 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_METER_TYPE_RFC2697 \
32988 /* RFC 2698 (trTCM) */
32989 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_METER_TYPE_RFC2698 \
32991 /* RFC 4115 (trTCM) */
32992 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_METER_TYPE_RFC4115 \
32994 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_METER_TYPE_LAST \
32995 HWRM_CFA_METER_PROFILE_CFG_INPUT_METER_TYPE_RFC4115
32996 /* This value identifies a meter profile in CFA. */
32997 uint16_t meter_profile_id;
32999 * A value of 0xfff is considered invalid and implies the
33000 * profile is not configured.
33002 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_METER_PROFILE_ID_INVALID \
33004 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_METER_PROFILE_ID_LAST \
33005 HWRM_CFA_METER_PROFILE_CFG_INPUT_METER_PROFILE_ID_INVALID
33007 * This field is reserved for the future use.
33008 * It shall be set to 0.
33011 /* A meter rate specified in bytes-per-second. */
33012 uint32_t commit_rate;
33013 /* The bandwidth value. */
33014 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_RATE_BW_VALUE_MASK \
33015 UINT32_C(0xfffffff)
33016 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_RATE_BW_VALUE_SFT \
33018 /* The granularity of the value (bits or bytes). */
33019 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_RATE_SCALE \
33020 UINT32_C(0x10000000)
33021 /* Value is in bits. */
33022 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_RATE_SCALE_BITS \
33023 (UINT32_C(0x0) << 28)
33024 /* Value is in bytes. */
33025 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_RATE_SCALE_BYTES \
33026 (UINT32_C(0x1) << 28)
33027 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_RATE_SCALE_LAST \
33028 HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_RATE_SCALE_BYTES
33029 /* bw_value_unit is 3 b */
33030 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_RATE_BW_VALUE_UNIT_MASK \
33031 UINT32_C(0xe0000000)
33032 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_RATE_BW_VALUE_UNIT_SFT \
33034 /* Value is in Mb or MB (base 10). */
33035 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_RATE_BW_VALUE_UNIT_MEGA \
33036 (UINT32_C(0x0) << 29)
33037 /* Value is in Kb or KB (base 10). */
33038 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_RATE_BW_VALUE_UNIT_KILO \
33039 (UINT32_C(0x2) << 29)
33040 /* Value is in bits or bytes. */
33041 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_RATE_BW_VALUE_UNIT_BASE \
33042 (UINT32_C(0x4) << 29)
33043 /* Value is in Gb or GB (base 10). */
33044 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_RATE_BW_VALUE_UNIT_GIGA \
33045 (UINT32_C(0x6) << 29)
33046 /* Value is in 1/100th of a percentage of total bandwidth. */
33047 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_RATE_BW_VALUE_UNIT_PERCENT1_100 \
33048 (UINT32_C(0x1) << 29)
33050 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_RATE_BW_VALUE_UNIT_RAW \
33051 (UINT32_C(0x7) << 29)
33052 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_RATE_BW_VALUE_UNIT_LAST \
33053 HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_RATE_BW_VALUE_UNIT_RAW
33054 /* A meter burst size specified in bytes. */
33055 uint32_t commit_burst;
33056 /* The bandwidth value. */
33057 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_BURST_BW_VALUE_MASK \
33058 UINT32_C(0xfffffff)
33059 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_BURST_BW_VALUE_SFT \
33061 /* The granularity of the value (bits or bytes). */
33062 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_BURST_SCALE \
33063 UINT32_C(0x10000000)
33064 /* Value is in bits. */
33065 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_BURST_SCALE_BITS \
33066 (UINT32_C(0x0) << 28)
33067 /* Value is in bytes. */
33068 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_BURST_SCALE_BYTES \
33069 (UINT32_C(0x1) << 28)
33070 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_BURST_SCALE_LAST \
33071 HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_BURST_SCALE_BYTES
33072 /* bw_value_unit is 3 b */
33073 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_BURST_BW_VALUE_UNIT_MASK \
33074 UINT32_C(0xe0000000)
33075 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_BURST_BW_VALUE_UNIT_SFT \
33077 /* Value is in Mb or MB (base 10). */
33078 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_BURST_BW_VALUE_UNIT_MEGA \
33079 (UINT32_C(0x0) << 29)
33080 /* Value is in Kb or KB (base 10). */
33081 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_BURST_BW_VALUE_UNIT_KILO \
33082 (UINT32_C(0x2) << 29)
33083 /* Value is in bits or bytes. */
33084 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_BURST_BW_VALUE_UNIT_BASE \
33085 (UINT32_C(0x4) << 29)
33086 /* Value is in Gb or GB (base 10). */
33087 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_BURST_BW_VALUE_UNIT_GIGA \
33088 (UINT32_C(0x6) << 29)
33089 /* Value is in 1/100th of a percentage of total bandwidth. */
33090 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_BURST_BW_VALUE_UNIT_PERCENT1_100 \
33091 (UINT32_C(0x1) << 29)
33092 /* Invalid value */
33093 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_BURST_BW_VALUE_UNIT_INVALID \
33094 (UINT32_C(0x7) << 29)
33095 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_BURST_BW_VALUE_UNIT_LAST \
33096 HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_BURST_BW_VALUE_UNIT_INVALID
33097 /* A meter rate specified in bytes-per-second. */
33098 uint32_t excess_peak_rate;
33099 /* The bandwidth value. */
33100 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_RATE_BW_VALUE_MASK \
33101 UINT32_C(0xfffffff)
33102 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_RATE_BW_VALUE_SFT \
33104 /* The granularity of the value (bits or bytes). */
33105 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_RATE_SCALE \
33106 UINT32_C(0x10000000)
33107 /* Value is in bits. */
33108 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_RATE_SCALE_BITS \
33109 (UINT32_C(0x0) << 28)
33110 /* Value is in bytes. */
33111 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_RATE_SCALE_BYTES \
33112 (UINT32_C(0x1) << 28)
33113 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_RATE_SCALE_LAST \
33114 HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_RATE_SCALE_BYTES
33115 /* bw_value_unit is 3 b */
33116 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_RATE_BW_VALUE_UNIT_MASK \
33117 UINT32_C(0xe0000000)
33118 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_RATE_BW_VALUE_UNIT_SFT \
33120 /* Value is in Mb or MB (base 10). */
33121 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_RATE_BW_VALUE_UNIT_MEGA \
33122 (UINT32_C(0x0) << 29)
33123 /* Value is in Kb or KB (base 10). */
33124 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_RATE_BW_VALUE_UNIT_KILO \
33125 (UINT32_C(0x2) << 29)
33126 /* Value is in bits or bytes. */
33127 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_RATE_BW_VALUE_UNIT_BASE \
33128 (UINT32_C(0x4) << 29)
33129 /* Value is in Gb or GB (base 10). */
33130 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_RATE_BW_VALUE_UNIT_GIGA \
33131 (UINT32_C(0x6) << 29)
33132 /* Value is in 1/100th of a percentage of total bandwidth. */
33133 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_RATE_BW_VALUE_UNIT_PERCENT1_100 \
33134 (UINT32_C(0x1) << 29)
33136 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_RATE_BW_VALUE_UNIT_RAW \
33137 (UINT32_C(0x7) << 29)
33138 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_RATE_BW_VALUE_UNIT_LAST \
33139 HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_RATE_BW_VALUE_UNIT_RAW
33140 /* A meter burst size specified in bytes. */
33141 uint32_t excess_peak_burst;
33142 /* The bandwidth value. */
33143 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_BURST_BW_VALUE_MASK \
33144 UINT32_C(0xfffffff)
33145 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_BURST_BW_VALUE_SFT \
33147 /* The granularity of the value (bits or bytes). */
33148 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_BURST_SCALE \
33149 UINT32_C(0x10000000)
33150 /* Value is in bits. */
33151 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_BURST_SCALE_BITS \
33152 (UINT32_C(0x0) << 28)
33153 /* Value is in bytes. */
33154 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_BURST_SCALE_BYTES \
33155 (UINT32_C(0x1) << 28)
33156 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_BURST_SCALE_LAST \
33157 HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_BURST_SCALE_BYTES
33158 /* bw_value_unit is 3 b */
33159 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_BURST_BW_VALUE_UNIT_MASK \
33160 UINT32_C(0xe0000000)
33161 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_BURST_BW_VALUE_UNIT_SFT \
33163 /* Value is in Mb or MB (base 10). */
33164 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_BURST_BW_VALUE_UNIT_MEGA \
33165 (UINT32_C(0x0) << 29)
33166 /* Value is in Kb or KB (base 10). */
33167 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_BURST_BW_VALUE_UNIT_KILO \
33168 (UINT32_C(0x2) << 29)
33169 /* Value is in bits or bytes. */
33170 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_BURST_BW_VALUE_UNIT_BASE \
33171 (UINT32_C(0x4) << 29)
33172 /* Value is in Gb or GB (base 10). */
33173 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_BURST_BW_VALUE_UNIT_GIGA \
33174 (UINT32_C(0x6) << 29)
33175 /* Value is in 1/100th of a percentage of total bandwidth. */
33176 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_BURST_BW_VALUE_UNIT_PERCENT1_100 \
33177 (UINT32_C(0x1) << 29)
33179 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_BURST_BW_VALUE_UNIT_INVALID \
33180 (UINT32_C(0x7) << 29)
33181 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_BURST_BW_VALUE_UNIT_LAST \
33182 HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_BURST_BW_VALUE_UNIT_INVALID
33185 /* hwrm_cfa_meter_profile_cfg_output (size:128b/16B) */
33186 struct hwrm_cfa_meter_profile_cfg_output {
33187 /* The specific error status for the command. */
33188 uint16_t error_code;
33189 /* The HWRM command request type. */
33191 /* The sequence ID from the original command. */
33193 /* The length of the response data in number of bytes. */
33195 uint8_t unused_0[7];
33197 * This field is used in Output records to indicate that the output
33198 * is completely written to RAM. This field should be read as '1'
33199 * to indicate that the output has been completely written.
33200 * When writing a command completion or response to an internal processor,
33201 * the order of writes has to be such that this field is written last.
33206 /*********************************
33207 * hwrm_cfa_meter_instance_alloc *
33208 *********************************/
33211 /* hwrm_cfa_meter_instance_alloc_input (size:192b/24B) */
33212 struct hwrm_cfa_meter_instance_alloc_input {
33213 /* The HWRM command request type. */
33216 * The completion ring to send the completion event on. This should
33217 * be the NQ ID returned from the `nq_alloc` HWRM command.
33219 uint16_t cmpl_ring;
33221 * The sequence ID is used by the driver for tracking multiple
33222 * commands. This ID is treated as opaque data by the firmware and
33223 * the value is returned in the `hwrm_resp_hdr` upon completion.
33227 * The target ID of the command:
33228 * * 0x0-0xFFF8 - The function ID
33229 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
33230 * * 0xFFFD - Reserved for user-space HWRM interface
33233 uint16_t target_id;
33235 * A physical address pointer pointing to a host buffer that the
33236 * command's response data will be written. This can be either a host
33237 * physical address (HPA) or a guest physical address (GPA) and must
33238 * point to a physically contiguous block of memory.
33240 uint64_t resp_addr;
33243 * Enumeration denoting the RX, TX type of the resource.
33244 * This enumeration is used for resources that are similar for both
33245 * TX and RX paths of the chip.
33247 #define HWRM_CFA_METER_INSTANCE_ALLOC_INPUT_FLAGS_PATH \
33250 #define HWRM_CFA_METER_INSTANCE_ALLOC_INPUT_FLAGS_PATH_TX \
33253 #define HWRM_CFA_METER_INSTANCE_ALLOC_INPUT_FLAGS_PATH_RX \
33255 #define HWRM_CFA_METER_INSTANCE_ALLOC_INPUT_FLAGS_PATH_LAST \
33256 HWRM_CFA_METER_INSTANCE_ALLOC_INPUT_FLAGS_PATH_RX
33258 /* This value identifies a meter profile in CFA. */
33259 uint16_t meter_profile_id;
33261 * A value of 0xffff is considered invalid and implies the
33262 * profile is not configured.
33264 #define HWRM_CFA_METER_INSTANCE_ALLOC_INPUT_METER_PROFILE_ID_INVALID \
33266 #define HWRM_CFA_METER_INSTANCE_ALLOC_INPUT_METER_PROFILE_ID_LAST \
33267 HWRM_CFA_METER_INSTANCE_ALLOC_INPUT_METER_PROFILE_ID_INVALID
33268 uint8_t unused_1[4];
33271 /* hwrm_cfa_meter_instance_alloc_output (size:128b/16B) */
33272 struct hwrm_cfa_meter_instance_alloc_output {
33273 /* The specific error status for the command. */
33274 uint16_t error_code;
33275 /* The HWRM command request type. */
33277 /* The sequence ID from the original command. */
33279 /* The length of the response data in number of bytes. */
33281 /* This value identifies a meter instance in CFA. */
33282 uint16_t meter_instance_id;
33284 * A value of 0xffff is considered invalid and implies the
33285 * instance is not configured.
33287 #define HWRM_CFA_METER_INSTANCE_ALLOC_OUTPUT_METER_INSTANCE_ID_INVALID \
33289 #define HWRM_CFA_METER_INSTANCE_ALLOC_OUTPUT_METER_INSTANCE_ID_LAST \
33290 HWRM_CFA_METER_INSTANCE_ALLOC_OUTPUT_METER_INSTANCE_ID_INVALID
33291 uint8_t unused_0[5];
33293 * This field is used in Output records to indicate that the output
33294 * is completely written to RAM. This field should be read as '1'
33295 * to indicate that the output has been completely written.
33296 * When writing a command completion or response to an internal processor,
33297 * the order of writes has to be such that this field is written last.
33302 /*******************************
33303 * hwrm_cfa_meter_instance_cfg *
33304 *******************************/
33307 /* hwrm_cfa_meter_instance_cfg_input (size:192b/24B) */
33308 struct hwrm_cfa_meter_instance_cfg_input {
33309 /* The HWRM command request type. */
33312 * The completion ring to send the completion event on. This should
33313 * be the NQ ID returned from the `nq_alloc` HWRM command.
33315 uint16_t cmpl_ring;
33317 * The sequence ID is used by the driver for tracking multiple
33318 * commands. This ID is treated as opaque data by the firmware and
33319 * the value is returned in the `hwrm_resp_hdr` upon completion.
33323 * The target ID of the command:
33324 * * 0x0-0xFFF8 - The function ID
33325 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
33326 * * 0xFFFD - Reserved for user-space HWRM interface
33329 uint16_t target_id;
33331 * A physical address pointer pointing to a host buffer that the
33332 * command's response data will be written. This can be either a host
33333 * physical address (HPA) or a guest physical address (GPA) and must
33334 * point to a physically contiguous block of memory.
33336 uint64_t resp_addr;
33339 * Enumeration denoting the RX, TX type of the resource.
33340 * This enumeration is used for resources that are similar for both
33341 * TX and RX paths of the chip.
33343 #define HWRM_CFA_METER_INSTANCE_CFG_INPUT_FLAGS_PATH UINT32_C(0x1)
33345 #define HWRM_CFA_METER_INSTANCE_CFG_INPUT_FLAGS_PATH_TX \
33348 #define HWRM_CFA_METER_INSTANCE_CFG_INPUT_FLAGS_PATH_RX \
33350 #define HWRM_CFA_METER_INSTANCE_CFG_INPUT_FLAGS_PATH_LAST \
33351 HWRM_CFA_METER_INSTANCE_CFG_INPUT_FLAGS_PATH_RX
33354 * This value identifies a new meter profile to be associated with
33355 * the meter instance specified in this command.
33357 uint16_t meter_profile_id;
33359 * A value of 0xffff is considered invalid and implies the
33360 * profile is not configured.
33362 #define HWRM_CFA_METER_INSTANCE_CFG_INPUT_METER_PROFILE_ID_INVALID \
33364 #define HWRM_CFA_METER_INSTANCE_CFG_INPUT_METER_PROFILE_ID_LAST \
33365 HWRM_CFA_METER_INSTANCE_CFG_INPUT_METER_PROFILE_ID_INVALID
33367 * This value identifies the ID of a meter instance that needs to be updated with
33368 * a new meter profile specified in this command.
33370 uint16_t meter_instance_id;
33371 uint8_t unused_1[2];
33374 /* hwrm_cfa_meter_instance_cfg_output (size:128b/16B) */
33375 struct hwrm_cfa_meter_instance_cfg_output {
33376 /* The specific error status for the command. */
33377 uint16_t error_code;
33378 /* The HWRM command request type. */
33380 /* The sequence ID from the original command. */
33382 /* The length of the response data in number of bytes. */
33384 uint8_t unused_0[7];
33386 * This field is used in Output records to indicate that the output
33387 * is completely written to RAM. This field should be read as '1'
33388 * to indicate that the output has been completely written.
33389 * When writing a command completion or response to an internal processor,
33390 * the order of writes has to be such that this field is written last.
33395 /********************************
33396 * hwrm_cfa_meter_instance_free *
33397 ********************************/
33400 /* hwrm_cfa_meter_instance_free_input (size:192b/24B) */
33401 struct hwrm_cfa_meter_instance_free_input {
33402 /* The HWRM command request type. */
33405 * The completion ring to send the completion event on. This should
33406 * be the NQ ID returned from the `nq_alloc` HWRM command.
33408 uint16_t cmpl_ring;
33410 * The sequence ID is used by the driver for tracking multiple
33411 * commands. This ID is treated as opaque data by the firmware and
33412 * the value is returned in the `hwrm_resp_hdr` upon completion.
33416 * The target ID of the command:
33417 * * 0x0-0xFFF8 - The function ID
33418 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
33419 * * 0xFFFD - Reserved for user-space HWRM interface
33422 uint16_t target_id;
33424 * A physical address pointer pointing to a host buffer that the
33425 * command's response data will be written. This can be either a host
33426 * physical address (HPA) or a guest physical address (GPA) and must
33427 * point to a physically contiguous block of memory.
33429 uint64_t resp_addr;
33432 * Enumeration denoting the RX, TX type of the resource.
33433 * This enumeration is used for resources that are similar for both
33434 * TX and RX paths of the chip.
33436 #define HWRM_CFA_METER_INSTANCE_FREE_INPUT_FLAGS_PATH UINT32_C(0x1)
33438 #define HWRM_CFA_METER_INSTANCE_FREE_INPUT_FLAGS_PATH_TX \
33441 #define HWRM_CFA_METER_INSTANCE_FREE_INPUT_FLAGS_PATH_RX \
33443 #define HWRM_CFA_METER_INSTANCE_FREE_INPUT_FLAGS_PATH_LAST \
33444 HWRM_CFA_METER_INSTANCE_FREE_INPUT_FLAGS_PATH_RX
33446 /* This value identifies a meter instance in CFA. */
33447 uint16_t meter_instance_id;
33449 * A value of 0xfff is considered invalid and implies the
33450 * instance is not configured.
33452 #define HWRM_CFA_METER_INSTANCE_FREE_INPUT_METER_INSTANCE_ID_INVALID \
33454 #define HWRM_CFA_METER_INSTANCE_FREE_INPUT_METER_INSTANCE_ID_LAST \
33455 HWRM_CFA_METER_INSTANCE_FREE_INPUT_METER_INSTANCE_ID_INVALID
33456 uint8_t unused_1[4];
33459 /* hwrm_cfa_meter_instance_free_output (size:128b/16B) */
33460 struct hwrm_cfa_meter_instance_free_output {
33461 /* The specific error status for the command. */
33462 uint16_t error_code;
33463 /* The HWRM command request type. */
33465 /* The sequence ID from the original command. */
33467 /* The length of the response data in number of bytes. */
33469 uint8_t unused_0[7];
33471 * This field is used in Output records to indicate that the output
33472 * is completely written to RAM. This field should be read as '1'
33473 * to indicate that the output has been completely written.
33474 * When writing a command completion or response to an internal processor,
33475 * the order of writes has to be such that this field is written last.
33480 /*******************************
33481 * hwrm_cfa_decap_filter_alloc *
33482 *******************************/
33485 /* hwrm_cfa_decap_filter_alloc_input (size:832b/104B) */
33486 struct hwrm_cfa_decap_filter_alloc_input {
33487 /* The HWRM command request type. */
33490 * The completion ring to send the completion event on. This should
33491 * be the NQ ID returned from the `nq_alloc` HWRM command.
33493 uint16_t cmpl_ring;
33495 * The sequence ID is used by the driver for tracking multiple
33496 * commands. This ID is treated as opaque data by the firmware and
33497 * the value is returned in the `hwrm_resp_hdr` upon completion.
33501 * The target ID of the command:
33502 * * 0x0-0xFFF8 - The function ID
33503 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
33504 * * 0xFFFD - Reserved for user-space HWRM interface
33507 uint16_t target_id;
33509 * A physical address pointer pointing to a host buffer that the
33510 * command's response data will be written. This can be either a host
33511 * physical address (HPA) or a guest physical address (GPA) and must
33512 * point to a physically contiguous block of memory.
33514 uint64_t resp_addr;
33516 /* ovs_tunnel is 1 b */
33517 #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_FLAGS_OVS_TUNNEL \
33521 * This bit must be '1' for the tunnel_type field to be
33524 #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_ENABLES_TUNNEL_TYPE \
33527 * This bit must be '1' for the tunnel_id field to be
33530 #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_ENABLES_TUNNEL_ID \
33533 * This bit must be '1' for the src_macaddr field to be
33536 #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_ENABLES_SRC_MACADDR \
33539 * This bit must be '1' for the dst_macaddr field to be
33542 #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_ENABLES_DST_MACADDR \
33545 * This bit must be '1' for the ovlan_vid field to be
33548 #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_ENABLES_OVLAN_VID \
33551 * This bit must be '1' for the ivlan_vid field to be
33554 #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_ENABLES_IVLAN_VID \
33557 * This bit must be '1' for the t_ovlan_vid field to be
33560 #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_ENABLES_T_OVLAN_VID \
33563 * This bit must be '1' for the t_ivlan_vid field to be
33566 #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_ENABLES_T_IVLAN_VID \
33569 * This bit must be '1' for the ethertype field to be
33572 #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_ENABLES_ETHERTYPE \
33575 * This bit must be '1' for the src_ipaddr field to be
33578 #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_ENABLES_SRC_IPADDR \
33581 * This bit must be '1' for the dst_ipaddr field to be
33584 #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_ENABLES_DST_IPADDR \
33587 * This bit must be '1' for the ipaddr_type field to be
33590 #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_ENABLES_IPADDR_TYPE \
33593 * This bit must be '1' for the ip_protocol field to be
33596 #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_ENABLES_IP_PROTOCOL \
33599 * This bit must be '1' for the src_port field to be
33602 #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_ENABLES_SRC_PORT \
33605 * This bit must be '1' for the dst_port field to be
33608 #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_ENABLES_DST_PORT \
33611 * This bit must be '1' for the dst_id field to be
33614 #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_ENABLES_DST_ID \
33617 * This bit must be '1' for the mirror_vnic_id field to be
33620 #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_ENABLES_MIRROR_VNIC_ID \
33623 * Tunnel identifier.
33624 * Virtual Network Identifier (VNI). Only valid with
33625 * tunnel_types VXLAN, NVGRE, and Geneve.
33626 * Only lower 24-bits of VNI field are used
33627 * in setting up the filter.
33629 uint32_t tunnel_id;
33631 uint8_t tunnel_type;
33633 #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_TUNNEL_TYPE_NONTUNNEL \
33635 /* Virtual eXtensible Local Area Network (VXLAN) */
33636 #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_TUNNEL_TYPE_VXLAN \
33638 /* Network Virtualization Generic Routing Encapsulation (NVGRE) */
33639 #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_TUNNEL_TYPE_NVGRE \
33641 /* Generic Routing Encapsulation (GRE) inside Ethernet payload */
33642 #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_TUNNEL_TYPE_L2GRE \
33645 #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_TUNNEL_TYPE_IPIP \
33647 /* Generic Network Virtualization Encapsulation (Geneve) */
33648 #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_TUNNEL_TYPE_GENEVE \
33650 /* Multi-Protocol Label Switching (MPLS) */
33651 #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_TUNNEL_TYPE_MPLS \
33653 /* Stateless Transport Tunnel (STT) */
33654 #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_TUNNEL_TYPE_STT \
33656 /* Generic Routing Encapsulation (GRE) inside IP datagram payload */
33657 #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_TUNNEL_TYPE_IPGRE \
33659 /* IPV4 over virtual eXtensible Local Area Network (IPV4oVXLAN) */
33660 #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_TUNNEL_TYPE_VXLAN_V4 \
33662 /* Enhance Generic Routing Encapsulation (GRE version 1) inside IP datagram payload */
33663 #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_TUNNEL_TYPE_IPGRE_V1 \
33665 /* Use fixed layer 2 ether type of 0xFFFF */
33666 #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_TUNNEL_TYPE_L2_ETYPE \
33668 /* IPV6 over virtual eXtensible Local Area Network with GPE header (IPV6oVXLANGPE) */
33669 #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_TUNNEL_TYPE_VXLAN_GPE_V6 \
33671 /* Any tunneled traffic */
33672 #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_TUNNEL_TYPE_ANYTUNNEL \
33674 #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_TUNNEL_TYPE_LAST \
33675 HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_TUNNEL_TYPE_ANYTUNNEL
33679 * This value indicates the source MAC address in
33680 * the Ethernet header.
33682 uint8_t src_macaddr[6];
33683 uint8_t unused_2[2];
33685 * This value indicates the destination MAC address in
33686 * the Ethernet header.
33688 uint8_t dst_macaddr[6];
33690 * This value indicates the VLAN ID of the outer VLAN tag
33691 * in the Ethernet header.
33693 uint16_t ovlan_vid;
33695 * This value indicates the VLAN ID of the inner VLAN tag
33696 * in the Ethernet header.
33698 uint16_t ivlan_vid;
33700 * This value indicates the VLAN ID of the outer VLAN tag
33701 * in the tunnel Ethernet header.
33703 uint16_t t_ovlan_vid;
33705 * This value indicates the VLAN ID of the inner VLAN tag
33706 * in the tunnel Ethernet header.
33708 uint16_t t_ivlan_vid;
33709 /* This value indicates the ethertype in the Ethernet header. */
33710 uint16_t ethertype;
33712 * This value indicates the type of IP address.
33715 * All others are invalid.
33717 uint8_t ip_addr_type;
33719 #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_IP_ADDR_TYPE_UNKNOWN \
33722 #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_IP_ADDR_TYPE_IPV4 \
33725 #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_IP_ADDR_TYPE_IPV6 \
33727 #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_IP_ADDR_TYPE_LAST \
33728 HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_IP_ADDR_TYPE_IPV6
33730 * The value of protocol filed in IP header.
33731 * Applies to UDP and TCP traffic.
33735 uint8_t ip_protocol;
33737 #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_IP_PROTOCOL_UNKNOWN \
33740 #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_IP_PROTOCOL_TCP \
33743 #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_IP_PROTOCOL_UDP \
33745 #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_IP_PROTOCOL_LAST \
33746 HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_IP_PROTOCOL_UDP
33750 * The value of source IP address to be used in filtering.
33751 * For IPv4, first four bytes represent the IP address.
33753 uint32_t src_ipaddr[4];
33755 * The value of destination IP address to be used in filtering.
33756 * For IPv4, first four bytes represent the IP address.
33758 uint32_t dst_ipaddr[4];
33760 * The value of source port to be used in filtering.
33761 * Applies to UDP and TCP traffic.
33765 * The value of destination port to be used in filtering.
33766 * Applies to UDP and TCP traffic.
33770 * If set, this value shall represent the
33771 * Logical VNIC ID of the destination VNIC for the RX
33776 * If set, this value shall represent the L2 context that matches the L2
33777 * information of the decap filter.
33779 uint16_t l2_ctxt_ref_id;
33782 /* hwrm_cfa_decap_filter_alloc_output (size:128b/16B) */
33783 struct hwrm_cfa_decap_filter_alloc_output {
33784 /* The specific error status for the command. */
33785 uint16_t error_code;
33786 /* The HWRM command request type. */
33788 /* The sequence ID from the original command. */
33790 /* The length of the response data in number of bytes. */
33792 /* This value is an opaque id into CFA data structures. */
33793 uint32_t decap_filter_id;
33794 uint8_t unused_0[3];
33796 * This field is used in Output records to indicate that the output
33797 * is completely written to RAM. This field should be read as '1'
33798 * to indicate that the output has been completely written.
33799 * When writing a command completion or response to an internal processor,
33800 * the order of writes has to be such that this field is written last.
33805 /******************************
33806 * hwrm_cfa_decap_filter_free *
33807 ******************************/
33810 /* hwrm_cfa_decap_filter_free_input (size:192b/24B) */
33811 struct hwrm_cfa_decap_filter_free_input {
33812 /* The HWRM command request type. */
33815 * The completion ring to send the completion event on. This should
33816 * be the NQ ID returned from the `nq_alloc` HWRM command.
33818 uint16_t cmpl_ring;
33820 * The sequence ID is used by the driver for tracking multiple
33821 * commands. This ID is treated as opaque data by the firmware and
33822 * the value is returned in the `hwrm_resp_hdr` upon completion.
33826 * The target ID of the command:
33827 * * 0x0-0xFFF8 - The function ID
33828 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
33829 * * 0xFFFD - Reserved for user-space HWRM interface
33832 uint16_t target_id;
33834 * A physical address pointer pointing to a host buffer that the
33835 * command's response data will be written. This can be either a host
33836 * physical address (HPA) or a guest physical address (GPA) and must
33837 * point to a physically contiguous block of memory.
33839 uint64_t resp_addr;
33840 /* This value is an opaque id into CFA data structures. */
33841 uint32_t decap_filter_id;
33842 uint8_t unused_0[4];
33845 /* hwrm_cfa_decap_filter_free_output (size:128b/16B) */
33846 struct hwrm_cfa_decap_filter_free_output {
33847 /* The specific error status for the command. */
33848 uint16_t error_code;
33849 /* The HWRM command request type. */
33851 /* The sequence ID from the original command. */
33853 /* The length of the response data in number of bytes. */
33855 uint8_t unused_0[7];
33857 * This field is used in Output records to indicate that the output
33858 * is completely written to RAM. This field should be read as '1'
33859 * to indicate that the output has been completely written.
33860 * When writing a command completion or response to an internal processor,
33861 * the order of writes has to be such that this field is written last.
33866 /***********************
33867 * hwrm_cfa_flow_alloc *
33868 ***********************/
33871 /* hwrm_cfa_flow_alloc_input (size:1024b/128B) */
33872 struct hwrm_cfa_flow_alloc_input {
33873 /* The HWRM command request type. */
33876 * The completion ring to send the completion event on. This should
33877 * be the NQ ID returned from the `nq_alloc` HWRM command.
33879 uint16_t cmpl_ring;
33881 * The sequence ID is used by the driver for tracking multiple
33882 * commands. This ID is treated as opaque data by the firmware and
33883 * the value is returned in the `hwrm_resp_hdr` upon completion.
33887 * The target ID of the command:
33888 * * 0x0-0xFFF8 - The function ID
33889 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
33890 * * 0xFFFD - Reserved for user-space HWRM interface
33893 uint16_t target_id;
33895 * A physical address pointer pointing to a host buffer that the
33896 * command's response data will be written. This can be either a host
33897 * physical address (HPA) or a guest physical address (GPA) and must
33898 * point to a physically contiguous block of memory.
33900 uint64_t resp_addr;
33902 /* tunnel is 1 b */
33903 #define HWRM_CFA_FLOW_ALLOC_INPUT_FLAGS_TUNNEL \
33905 /* num_vlan is 2 b */
33906 #define HWRM_CFA_FLOW_ALLOC_INPUT_FLAGS_NUM_VLAN_MASK \
33908 #define HWRM_CFA_FLOW_ALLOC_INPUT_FLAGS_NUM_VLAN_SFT 1
33910 #define HWRM_CFA_FLOW_ALLOC_INPUT_FLAGS_NUM_VLAN_NONE \
33911 (UINT32_C(0x0) << 1)
33913 #define HWRM_CFA_FLOW_ALLOC_INPUT_FLAGS_NUM_VLAN_ONE \
33914 (UINT32_C(0x1) << 1)
33916 #define HWRM_CFA_FLOW_ALLOC_INPUT_FLAGS_NUM_VLAN_TWO \
33917 (UINT32_C(0x2) << 1)
33918 #define HWRM_CFA_FLOW_ALLOC_INPUT_FLAGS_NUM_VLAN_LAST \
33919 HWRM_CFA_FLOW_ALLOC_INPUT_FLAGS_NUM_VLAN_TWO
33920 /* Enumeration denoting the Flow Type. */
33921 #define HWRM_CFA_FLOW_ALLOC_INPUT_FLAGS_FLOWTYPE_MASK \
33923 #define HWRM_CFA_FLOW_ALLOC_INPUT_FLAGS_FLOWTYPE_SFT 3
33925 #define HWRM_CFA_FLOW_ALLOC_INPUT_FLAGS_FLOWTYPE_L2 \
33926 (UINT32_C(0x0) << 3)
33928 #define HWRM_CFA_FLOW_ALLOC_INPUT_FLAGS_FLOWTYPE_IPV4 \
33929 (UINT32_C(0x1) << 3)
33931 #define HWRM_CFA_FLOW_ALLOC_INPUT_FLAGS_FLOWTYPE_IPV6 \
33932 (UINT32_C(0x2) << 3)
33933 #define HWRM_CFA_FLOW_ALLOC_INPUT_FLAGS_FLOWTYPE_LAST \
33934 HWRM_CFA_FLOW_ALLOC_INPUT_FLAGS_FLOWTYPE_IPV6
33936 * when set to 1, indicates TX flow offload for function specified in src_fid and
33937 * the dst_fid should be set to invalid value. To indicate a VM to VM flow, both
33938 * of the path_tx and path_rx flags need to be set. For virtio vSwitch offload
33939 * case, the src_fid and dst_fid is set to the same fid value. For the SRIOV
33940 * vSwitch offload case, the src_fid and dst_fid must be set to the same VF FID
33941 * belong to the children VFs of the same PF to indicate VM to VM flow.
33943 #define HWRM_CFA_FLOW_ALLOC_INPUT_FLAGS_PATH_TX \
33946 * when set to 1, indicates RX flow offload for function specified in dst_fid and
33947 * the src_fid should be set to invalid value.
33949 #define HWRM_CFA_FLOW_ALLOC_INPUT_FLAGS_PATH_RX \
33952 * Set to 1 to indicate matching of VXLAN VNI from the custom vxlan header is
33953 * required and the VXLAN VNI value is stored in the first 24 bits of the dmac field.
33954 * This flag is only valid when the flow direction is RX.
33956 #define HWRM_CFA_FLOW_ALLOC_INPUT_FLAGS_MATCH_VXLAN_IP_VNI \
33958 /* Set to 1 to indicate vhost_id is specified in the outer_vlan_tci field. */
33959 #define HWRM_CFA_FLOW_ALLOC_INPUT_FLAGS_VHOST_ID_USE_VLAN \
33966 /* Tunnel handle valid when tunnel flag is set. */
33967 uint32_t tunnel_handle;
33968 uint16_t action_flags;
33970 * Setting of this flag indicates drop action. If this flag is not set,
33971 * then it should be considered accept action.
33973 #define HWRM_CFA_FLOW_ALLOC_INPUT_ACTION_FLAGS_FWD \
33975 /* recycle is 1 b */
33976 #define HWRM_CFA_FLOW_ALLOC_INPUT_ACTION_FLAGS_RECYCLE \
33979 * Setting of this flag indicates drop action. If this flag is not set,
33980 * then it should be considered accept action.
33982 #define HWRM_CFA_FLOW_ALLOC_INPUT_ACTION_FLAGS_DROP \
33985 #define HWRM_CFA_FLOW_ALLOC_INPUT_ACTION_FLAGS_METER \
33987 /* tunnel is 1 b */
33988 #define HWRM_CFA_FLOW_ALLOC_INPUT_ACTION_FLAGS_TUNNEL \
33990 /* nat_src is 1 b */
33991 #define HWRM_CFA_FLOW_ALLOC_INPUT_ACTION_FLAGS_NAT_SRC \
33993 /* nat_dest is 1 b */
33994 #define HWRM_CFA_FLOW_ALLOC_INPUT_ACTION_FLAGS_NAT_DEST \
33996 /* nat_ipv4_address is 1 b */
33997 #define HWRM_CFA_FLOW_ALLOC_INPUT_ACTION_FLAGS_NAT_IPV4_ADDRESS \
33999 /* l2_header_rewrite is 1 b */
34000 #define HWRM_CFA_FLOW_ALLOC_INPUT_ACTION_FLAGS_L2_HEADER_REWRITE \
34002 /* ttl_decrement is 1 b */
34003 #define HWRM_CFA_FLOW_ALLOC_INPUT_ACTION_FLAGS_TTL_DECREMENT \
34006 * If set to 1 and flow direction is TX, it indicates decap of L2 header
34007 * and encap of tunnel header. If set to 1 and flow direction is RX, it
34008 * indicates decap of tunnel header and encap L2 header. The type of tunnel
34009 * is specified in the tunnel_type field.
34011 #define HWRM_CFA_FLOW_ALLOC_INPUT_ACTION_FLAGS_TUNNEL_IP \
34013 /* If set to 1, flow aging is enabled for this flow. */
34014 #define HWRM_CFA_FLOW_ALLOC_INPUT_ACTION_FLAGS_FLOW_AGING_ENABLED \
34017 * If set to 1 an attempt will be made to try to offload this flow to the
34018 * most optimal flow table resource. If set to 0, the flow will be
34019 * placed to the default flow table resource.
34021 #define HWRM_CFA_FLOW_ALLOC_INPUT_ACTION_FLAGS_PRI_HINT \
34024 * If set to 1 there will be no attempt to allocate an on-chip try to
34025 * offload this flow. If set to 0, which will keep compatibility with the
34026 * older drivers, will cause the FW to attempt to allocate an on-chip flow
34027 * counter for the newly created flow. This will keep the existing behavior
34028 * with EM flows which always had an associated flow counter.
34030 #define HWRM_CFA_FLOW_ALLOC_INPUT_ACTION_FLAGS_NO_FLOW_COUNTER_ALLOC \
34033 * Tx Flow: pf or vf fid.
34037 /* VLAN tpid, valid when push_vlan flag is set. */
34038 uint16_t l2_rewrite_vlan_tpid;
34039 /* VLAN tci, valid when push_vlan flag is set. */
34040 uint16_t l2_rewrite_vlan_tci;
34041 /* Meter id, valid when meter flag is set. */
34042 uint16_t act_meter_id;
34043 /* Flow with the same l2 context tcam key. */
34044 uint16_t ref_flow_handle;
34045 /* This value sets the match value for the ethertype. */
34046 uint16_t ethertype;
34047 /* valid when num tags is 1 or 2. */
34048 uint16_t outer_vlan_tci;
34049 /* This value sets the match value for the Destination MAC address. */
34051 /* valid when num tags is 2. */
34052 uint16_t inner_vlan_tci;
34053 /* This value sets the match value for the Source MAC address. */
34055 /* The bit length of destination IP address mask. */
34056 uint8_t ip_dst_mask_len;
34057 /* The bit length of source IP address mask. */
34058 uint8_t ip_src_mask_len;
34059 /* The value of destination IPv4/IPv6 address. */
34060 uint32_t ip_dst[4];
34061 /* The source IPv4/IPv6 address. */
34062 uint32_t ip_src[4];
34064 * The value of source port.
34065 * Applies to UDP and TCP traffic.
34067 uint16_t l4_src_port;
34069 * The value of source port mask.
34070 * Applies to UDP and TCP traffic.
34072 uint16_t l4_src_port_mask;
34074 * The value of destination port.
34075 * Applies to UDP and TCP traffic.
34077 uint16_t l4_dst_port;
34079 * The value of destination port mask.
34080 * Applies to UDP and TCP traffic.
34082 uint16_t l4_dst_port_mask;
34084 * NAT IPv4/6 address based on address type flag.
34085 * 0 values are ignored.
34087 uint32_t nat_ip_address[4];
34088 /* L2 header re-write Destination MAC address. */
34089 uint16_t l2_rewrite_dmac[3];
34091 * The NAT source/destination port based on direction flag.
34092 * Applies to UDP and TCP traffic.
34093 * 0 values are ignored.
34096 /* L2 header re-write Source MAC address. */
34097 uint16_t l2_rewrite_smac[3];
34098 /* The value of ip protocol. */
34101 uint8_t tunnel_type;
34103 #define HWRM_CFA_FLOW_ALLOC_INPUT_TUNNEL_TYPE_NONTUNNEL \
34105 /* Virtual eXtensible Local Area Network (VXLAN) */
34106 #define HWRM_CFA_FLOW_ALLOC_INPUT_TUNNEL_TYPE_VXLAN \
34108 /* Network Virtualization Generic Routing Encapsulation (NVGRE) */
34109 #define HWRM_CFA_FLOW_ALLOC_INPUT_TUNNEL_TYPE_NVGRE \
34111 /* Generic Routing Encapsulation (GRE) inside Ethernet payload */
34112 #define HWRM_CFA_FLOW_ALLOC_INPUT_TUNNEL_TYPE_L2GRE \
34115 #define HWRM_CFA_FLOW_ALLOC_INPUT_TUNNEL_TYPE_IPIP \
34117 /* Generic Network Virtualization Encapsulation (Geneve) */
34118 #define HWRM_CFA_FLOW_ALLOC_INPUT_TUNNEL_TYPE_GENEVE \
34120 /* Multi-Protocol Label Switching (MPLS) */
34121 #define HWRM_CFA_FLOW_ALLOC_INPUT_TUNNEL_TYPE_MPLS \
34123 /* Stateless Transport Tunnel (STT) */
34124 #define HWRM_CFA_FLOW_ALLOC_INPUT_TUNNEL_TYPE_STT \
34126 /* Generic Routing Encapsulation (GRE) inside IP datagram payload */
34127 #define HWRM_CFA_FLOW_ALLOC_INPUT_TUNNEL_TYPE_IPGRE \
34129 /* IPV4 over virtual eXtensible Local Area Network (IPV4oVXLAN) */
34130 #define HWRM_CFA_FLOW_ALLOC_INPUT_TUNNEL_TYPE_VXLAN_V4 \
34132 /* Enhance Generic Routing Encapsulation (GRE version 1) inside IP datagram payload */
34133 #define HWRM_CFA_FLOW_ALLOC_INPUT_TUNNEL_TYPE_IPGRE_V1 \
34135 /* Use fixed layer 2 ether type of 0xFFFF */
34136 #define HWRM_CFA_FLOW_ALLOC_INPUT_TUNNEL_TYPE_L2_ETYPE \
34138 /* IPV6 over virtual eXtensible Local Area Network with GPE header (IPV6oVXLANGPE) */
34139 #define HWRM_CFA_FLOW_ALLOC_INPUT_TUNNEL_TYPE_VXLAN_GPE_V6 \
34141 /* Any tunneled traffic */
34142 #define HWRM_CFA_FLOW_ALLOC_INPUT_TUNNEL_TYPE_ANYTUNNEL \
34144 #define HWRM_CFA_FLOW_ALLOC_INPUT_TUNNEL_TYPE_LAST \
34145 HWRM_CFA_FLOW_ALLOC_INPUT_TUNNEL_TYPE_ANYTUNNEL
34148 /* hwrm_cfa_flow_alloc_output (size:256b/32B) */
34149 struct hwrm_cfa_flow_alloc_output {
34150 /* The specific error status for the command. */
34151 uint16_t error_code;
34152 /* The HWRM command request type. */
34154 /* The sequence ID from the original command. */
34156 /* The length of the response data in number of bytes. */
34158 /* Flow record index. */
34159 uint16_t flow_handle;
34160 uint8_t unused_0[2];
34162 * The flow id value in bit 0-29 is the actual ID of the flow
34163 * associated with this filter and it shall be used to match
34164 * and associate the flow identifier returned in completion
34165 * records. A value of 0xFFFFFFFF in the 32-bit flow_id field
34166 * shall indicate no valid flow id.
34169 /* Indicate the flow id value. */
34170 #define HWRM_CFA_FLOW_ALLOC_OUTPUT_FLOW_ID_VALUE_MASK \
34171 UINT32_C(0x3fffffff)
34172 #define HWRM_CFA_FLOW_ALLOC_OUTPUT_FLOW_ID_VALUE_SFT 0
34173 /* Indicate type of the flow. */
34174 #define HWRM_CFA_FLOW_ALLOC_OUTPUT_FLOW_ID_TYPE \
34175 UINT32_C(0x40000000)
34177 * If this bit set to 0, then it indicates that the flow is
34180 #define HWRM_CFA_FLOW_ALLOC_OUTPUT_FLOW_ID_TYPE_INT \
34181 (UINT32_C(0x0) << 30)
34183 * If this bit is set to 1, then it indicates that the flow is
34186 #define HWRM_CFA_FLOW_ALLOC_OUTPUT_FLOW_ID_TYPE_EXT \
34187 (UINT32_C(0x1) << 30)
34188 #define HWRM_CFA_FLOW_ALLOC_OUTPUT_FLOW_ID_TYPE_LAST \
34189 HWRM_CFA_FLOW_ALLOC_OUTPUT_FLOW_ID_TYPE_EXT
34190 /* Indicate the flow direction. */
34191 #define HWRM_CFA_FLOW_ALLOC_OUTPUT_FLOW_ID_DIR \
34192 UINT32_C(0x80000000)
34193 /* If this bit set to 0, then it indicates rx flow. */
34194 #define HWRM_CFA_FLOW_ALLOC_OUTPUT_FLOW_ID_DIR_RX \
34195 (UINT32_C(0x0) << 31)
34196 /* If this bit is set to 1, then it indicates that tx flow. */
34197 #define HWRM_CFA_FLOW_ALLOC_OUTPUT_FLOW_ID_DIR_TX \
34198 (UINT32_C(0x1) << 31)
34199 #define HWRM_CFA_FLOW_ALLOC_OUTPUT_FLOW_ID_DIR_LAST \
34200 HWRM_CFA_FLOW_ALLOC_OUTPUT_FLOW_ID_DIR_TX
34201 /* This value identifies a set of CFA data structures used for a flow. */
34202 uint64_t ext_flow_handle;
34203 uint32_t flow_counter_id;
34204 uint8_t unused_1[3];
34206 * This field is used in Output records to indicate that the output
34207 * is completely written to RAM. This field should be read as '1'
34208 * to indicate that the output has been completely written.
34209 * When writing a command completion or response to an internal processor,
34210 * the order of writes has to be such that this field is written last.
34215 /* hwrm_cfa_flow_alloc_cmd_err (size:64b/8B) */
34216 struct hwrm_cfa_flow_alloc_cmd_err {
34218 * command specific error codes that goes to
34219 * the cmd_err field in Common HWRM Error Response.
34222 /* Unknown error */
34223 #define HWRM_CFA_FLOW_ALLOC_CMD_ERR_CODE_UNKNOWN UINT32_C(0x0)
34224 /* No more L2 Context TCAM */
34225 #define HWRM_CFA_FLOW_ALLOC_CMD_ERR_CODE_L2_CONTEXT_TCAM UINT32_C(0x1)
34226 /* No more action records */
34227 #define HWRM_CFA_FLOW_ALLOC_CMD_ERR_CODE_ACTION_RECORD UINT32_C(0x2)
34228 /* No more flow counters */
34229 #define HWRM_CFA_FLOW_ALLOC_CMD_ERR_CODE_FLOW_COUNTER UINT32_C(0x3)
34230 /* No more wild-card TCAM */
34231 #define HWRM_CFA_FLOW_ALLOC_CMD_ERR_CODE_WILD_CARD_TCAM UINT32_C(0x4)
34232 /* Hash collsion in exact match tables */
34233 #define HWRM_CFA_FLOW_ALLOC_CMD_ERR_CODE_HASH_COLLISION UINT32_C(0x5)
34234 /* Key is already installed */
34235 #define HWRM_CFA_FLOW_ALLOC_CMD_ERR_CODE_KEY_EXISTS UINT32_C(0x6)
34236 /* Flow Context DB is out of resource */
34237 #define HWRM_CFA_FLOW_ALLOC_CMD_ERR_CODE_FLOW_CTXT_DB UINT32_C(0x7)
34238 #define HWRM_CFA_FLOW_ALLOC_CMD_ERR_CODE_LAST \
34239 HWRM_CFA_FLOW_ALLOC_CMD_ERR_CODE_FLOW_CTXT_DB
34240 uint8_t unused_0[7];
34243 /**********************
34244 * hwrm_cfa_flow_free *
34245 **********************/
34248 /* hwrm_cfa_flow_free_input (size:256b/32B) */
34249 struct hwrm_cfa_flow_free_input {
34250 /* The HWRM command request type. */
34253 * The completion ring to send the completion event on. This should
34254 * be the NQ ID returned from the `nq_alloc` HWRM command.
34256 uint16_t cmpl_ring;
34258 * The sequence ID is used by the driver for tracking multiple
34259 * commands. This ID is treated as opaque data by the firmware and
34260 * the value is returned in the `hwrm_resp_hdr` upon completion.
34264 * The target ID of the command:
34265 * * 0x0-0xFFF8 - The function ID
34266 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
34267 * * 0xFFFD - Reserved for user-space HWRM interface
34270 uint16_t target_id;
34272 * A physical address pointer pointing to a host buffer that the
34273 * command's response data will be written. This can be either a host
34274 * physical address (HPA) or a guest physical address (GPA) and must
34275 * point to a physically contiguous block of memory.
34277 uint64_t resp_addr;
34278 /* Flow record index. */
34279 uint16_t flow_handle;
34281 /* Flow counter id to be freed. */
34282 uint32_t flow_counter_id;
34283 /* This value identifies a set of CFA data structures used for a flow. */
34284 uint64_t ext_flow_handle;
34287 /* hwrm_cfa_flow_free_output (size:256b/32B) */
34288 struct hwrm_cfa_flow_free_output {
34289 /* The specific error status for the command. */
34290 uint16_t error_code;
34291 /* The HWRM command request type. */
34293 /* The sequence ID from the original command. */
34295 /* The length of the response data in number of bytes. */
34297 /* packet is 64 b */
34301 uint8_t unused_0[7];
34303 * This field is used in Output records to indicate that the output
34304 * is completely written to RAM. This field should be read as '1'
34305 * to indicate that the output has been completely written.
34306 * When writing a command completion or response to an internal processor,
34307 * the order of writes has to be such that this field is written last.
34312 /* hwrm_cfa_flow_action_data (size:960b/120B) */
34313 struct hwrm_cfa_flow_action_data {
34314 uint16_t action_flags;
34315 /* Setting of this flag indicates accept action. */
34316 #define HWRM_CFA_FLOW_ACTION_DATA_ACTION_FLAGS_FWD \
34318 /* Setting of this flag indicates recycle action. */
34319 #define HWRM_CFA_FLOW_ACTION_DATA_ACTION_FLAGS_RECYCLE \
34321 /* Setting of this flag indicates drop action. */
34322 #define HWRM_CFA_FLOW_ACTION_DATA_ACTION_FLAGS_DROP \
34324 /* Setting of this flag indicates meter action. */
34325 #define HWRM_CFA_FLOW_ACTION_DATA_ACTION_FLAGS_METER \
34327 /* Setting of this flag indicates tunnel action. */
34328 #define HWRM_CFA_FLOW_ACTION_DATA_ACTION_FLAGS_TUNNEL \
34331 * If set to 1 and flow direction is TX, it indicates decap of L2 header
34332 * and encap of tunnel header. If set to 1 and flow direction is RX, it
34333 * indicates decap of tunnel header and encap L2 header.
34335 #define HWRM_CFA_FLOW_ACTION_DATA_ACTION_FLAGS_TUNNEL_IP \
34337 /* Setting of this flag indicates ttl decrement action. */
34338 #define HWRM_CFA_FLOW_ACTION_DATA_ACTION_FLAGS_TTL_DECREMENT \
34340 /* If set to 1, flow aging is enabled for this flow. */
34341 #define HWRM_CFA_FLOW_ACTION_DATA_ACTION_FLAGS_FLOW_AGING_ENABLED \
34343 /* Setting of this flag indicates encap action. */
34344 #define HWRM_CFA_FLOW_ACTION_DATA_ACTION_FLAGS_ENCAP \
34346 /* Setting of this flag indicates decap action. */
34347 #define HWRM_CFA_FLOW_ACTION_DATA_ACTION_FLAGS_DECAP \
34350 uint16_t act_meter_id;
34353 /* vport number. */
34355 /* The NAT source/destination. */
34357 uint16_t unused_0[3];
34358 /* NAT IPv4/IPv6 address. */
34359 uint32_t nat_ip_address[4];
34360 /* Encapsulation Type. */
34361 uint8_t encap_type;
34362 /* Virtual eXtensible Local Area Network (VXLAN) */
34363 #define HWRM_CFA_FLOW_ACTION_DATA_ENCAP_TYPE_VXLAN UINT32_C(0x1)
34364 /* Network Virtualization Generic Routing Encapsulation (NVGRE) */
34365 #define HWRM_CFA_FLOW_ACTION_DATA_ENCAP_TYPE_NVGRE UINT32_C(0x2)
34366 /* Generic Routing Encapsulation (GRE) after inside Ethernet payload */
34367 #define HWRM_CFA_FLOW_ACTION_DATA_ENCAP_TYPE_L2GRE UINT32_C(0x3)
34369 #define HWRM_CFA_FLOW_ACTION_DATA_ENCAP_TYPE_IPIP UINT32_C(0x4)
34370 /* Generic Network Virtualization Encapsulation (Geneve) */
34371 #define HWRM_CFA_FLOW_ACTION_DATA_ENCAP_TYPE_GENEVE UINT32_C(0x5)
34372 /* Multi-Protocol Label Switching (MPLS) */
34373 #define HWRM_CFA_FLOW_ACTION_DATA_ENCAP_TYPE_MPLS UINT32_C(0x6)
34375 #define HWRM_CFA_FLOW_ACTION_DATA_ENCAP_TYPE_VLAN UINT32_C(0x7)
34376 /* Generic Routing Encapsulation (GRE) inside IP datagram payload */
34377 #define HWRM_CFA_FLOW_ACTION_DATA_ENCAP_TYPE_IPGRE UINT32_C(0x8)
34378 /* IPV4 over virtual eXtensible Local Area Network (IPV4oVXLAN) */
34379 #define HWRM_CFA_FLOW_ACTION_DATA_ENCAP_TYPE_VXLAN_V4 UINT32_C(0x9)
34380 /* Enhance Generic Routing Encapsulation (GRE version 1) inside IP datagram payload */
34381 #define HWRM_CFA_FLOW_ACTION_DATA_ENCAP_TYPE_IPGRE_V1 UINT32_C(0xa)
34382 /* Use fixed layer 2 ether type of 0xFFFF */
34383 #define HWRM_CFA_FLOW_ACTION_DATA_ENCAP_TYPE_L2_ETYPE UINT32_C(0xb)
34384 /* IPV6 over virtual eXtensible Local Area Network with GPE header (IPV6oVXLANGPE) */
34385 #define HWRM_CFA_FLOW_ACTION_DATA_ENCAP_TYPE_VXLAN_GPE_V6 UINT32_C(0xc)
34386 #define HWRM_CFA_FLOW_ACTION_DATA_ENCAP_TYPE_LAST \
34387 HWRM_CFA_FLOW_ACTION_DATA_ENCAP_TYPE_VXLAN_GPE_V6
34389 /* This value is encap data for the associated encap type. */
34390 uint32_t encap_data[20];
34393 /* hwrm_cfa_flow_tunnel_hdr_data (size:64b/8B) */
34394 struct hwrm_cfa_flow_tunnel_hdr_data {
34396 uint8_t tunnel_type;
34398 #define HWRM_CFA_FLOW_TUNNEL_HDR_DATA_TUNNEL_TYPE_NONTUNNEL \
34400 /* Virtual eXtensible Local Area Network (VXLAN) */
34401 #define HWRM_CFA_FLOW_TUNNEL_HDR_DATA_TUNNEL_TYPE_VXLAN \
34403 /* Network Virtualization Generic Routing Encapsulation (NVGRE) */
34404 #define HWRM_CFA_FLOW_TUNNEL_HDR_DATA_TUNNEL_TYPE_NVGRE \
34406 /* Generic Routing Encapsulation (GRE) inside Ethernet payload */
34407 #define HWRM_CFA_FLOW_TUNNEL_HDR_DATA_TUNNEL_TYPE_L2GRE \
34410 #define HWRM_CFA_FLOW_TUNNEL_HDR_DATA_TUNNEL_TYPE_IPIP \
34412 /* Generic Network Virtualization Encapsulation (Geneve) */
34413 #define HWRM_CFA_FLOW_TUNNEL_HDR_DATA_TUNNEL_TYPE_GENEVE \
34415 /* Multi-Protocol Label Switching (MPLS) */
34416 #define HWRM_CFA_FLOW_TUNNEL_HDR_DATA_TUNNEL_TYPE_MPLS \
34418 /* Stateless Transport Tunnel (STT) */
34419 #define HWRM_CFA_FLOW_TUNNEL_HDR_DATA_TUNNEL_TYPE_STT \
34421 /* Generic Routing Encapsulation (GRE) inside IP datagram payload */
34422 #define HWRM_CFA_FLOW_TUNNEL_HDR_DATA_TUNNEL_TYPE_IPGRE \
34424 /* IPV4 over virtual eXtensible Local Area Network (IPV4oVXLAN) */
34425 #define HWRM_CFA_FLOW_TUNNEL_HDR_DATA_TUNNEL_TYPE_VXLAN_V4 \
34427 /* Enhance Generic Routing Encapsulation (GRE version 1) inside IP datagram payload */
34428 #define HWRM_CFA_FLOW_TUNNEL_HDR_DATA_TUNNEL_TYPE_IPGRE_V1 \
34430 /* Use fixed layer 2 ether type of 0xFFFF */
34431 #define HWRM_CFA_FLOW_TUNNEL_HDR_DATA_TUNNEL_TYPE_L2_ETYPE \
34433 /* IPV6 over virtual eXtensible Local Area Network with GPE header (IPV6oVXLANGPE) */
34434 #define HWRM_CFA_FLOW_TUNNEL_HDR_DATA_TUNNEL_TYPE_VXLAN_GPE_V6 \
34436 /* Any tunneled traffic */
34437 #define HWRM_CFA_FLOW_TUNNEL_HDR_DATA_TUNNEL_TYPE_ANYTUNNEL \
34439 #define HWRM_CFA_FLOW_TUNNEL_HDR_DATA_TUNNEL_TYPE_LAST \
34440 HWRM_CFA_FLOW_TUNNEL_HDR_DATA_TUNNEL_TYPE_ANYTUNNEL
34443 * Tunnel identifier.
34444 * Virtual Network Identifier (VNI).
34446 uint32_t tunnel_id;
34449 /* hwrm_cfa_flow_l4_key_data (size:64b/8B) */
34450 struct hwrm_cfa_flow_l4_key_data {
34451 /* The value of source port. */
34452 uint16_t l4_src_port;
34453 /* The value of destination port. */
34454 uint16_t l4_dst_port;
34458 /* hwrm_cfa_flow_l3_key_data (size:512b/64B) */
34459 struct hwrm_cfa_flow_l3_key_data {
34460 /* The value of ip protocol. */
34461 uint8_t ip_protocol;
34462 uint8_t unused_0[7];
34463 /* The value of destination IPv4/IPv6 address. */
34464 uint32_t ip_dst[4];
34465 /* The source IPv4/IPv6 address. */
34466 uint32_t ip_src[4];
34467 /* NAT IPv4/IPv6 address. */
34468 uint32_t nat_ip_address[4];
34469 uint32_t unused[2];
34472 /* hwrm_cfa_flow_l2_key_data (size:448b/56B) */
34473 struct hwrm_cfa_flow_l2_key_data {
34474 /* Destination MAC address. */
34477 /* Source MAC address. */
34480 /* L2 header re-write Destination MAC address. */
34481 uint16_t l2_rewrite_dmac[3];
34483 /* L2 header re-write Source MAC address. */
34484 uint16_t l2_rewrite_smac[3];
34486 uint16_t ethertype;
34487 /* Number of VLAN tags. */
34488 uint16_t num_vlan_tags;
34490 uint16_t l2_rewrite_vlan_tpid;
34492 uint16_t l2_rewrite_vlan_tci;
34493 uint8_t unused_3[2];
34494 /* Outer VLAN TPID. */
34495 uint16_t ovlan_tpid;
34496 /* Outer VLAN TCI. */
34497 uint16_t ovlan_tci;
34498 /* Inner VLAN TPID. */
34499 uint16_t ivlan_tpid;
34500 /* Inner VLAN TCI. */
34501 uint16_t ivlan_tci;
34505 /* hwrm_cfa_flow_key_data (size:4160b/520B) */
34506 struct hwrm_cfa_flow_key_data {
34507 /* Flow associated tunnel L2 header key info. */
34508 uint32_t t_l2_key_data[14];
34509 /* Flow associated tunnel L2 header mask info. */
34510 uint32_t t_l2_key_mask[14];
34511 /* Flow associated tunnel L3 header key info. */
34512 uint32_t t_l3_key_data[16];
34513 /* Flow associated tunnel L3 header mask info. */
34514 uint32_t t_l3_key_mask[16];
34515 /* Flow associated tunnel L4 header key info. */
34516 uint32_t t_l4_key_data[2];
34517 /* Flow associated tunnel L4 header mask info. */
34518 uint32_t t_l4_key_mask[2];
34519 /* Flow associated tunnel header info. */
34520 uint32_t tunnel_hdr[2];
34521 /* Flow associated L2 header key info. */
34522 uint32_t l2_key_data[14];
34523 /* Flow associated L2 header mask info. */
34524 uint32_t l2_key_mask[14];
34525 /* Flow associated L3 header key info. */
34526 uint32_t l3_key_data[16];
34527 /* Flow associated L3 header mask info. */
34528 uint32_t l3_key_mask[16];
34529 /* Flow associated L4 header key info. */
34530 uint32_t l4_key_data[2];
34531 /* Flow associated L4 header mask info. */
34532 uint32_t l4_key_mask[2];
34535 /**********************
34536 * hwrm_cfa_flow_info *
34537 **********************/
34540 /* hwrm_cfa_flow_info_input (size:256b/32B) */
34541 struct hwrm_cfa_flow_info_input {
34542 /* The HWRM command request type. */
34545 * The completion ring to send the completion event on. This should
34546 * be the NQ ID returned from the `nq_alloc` HWRM command.
34548 uint16_t cmpl_ring;
34550 * The sequence ID is used by the driver for tracking multiple
34551 * commands. This ID is treated as opaque data by the firmware and
34552 * the value is returned in the `hwrm_resp_hdr` upon completion.
34556 * The target ID of the command:
34557 * * 0x0-0xFFF8 - The function ID
34558 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
34559 * * 0xFFFD - Reserved for user-space HWRM interface
34562 uint16_t target_id;
34564 * A physical address pointer pointing to a host buffer that the
34565 * command's response data will be written. This can be either a host
34566 * physical address (HPA) or a guest physical address (GPA) and must
34567 * point to a physically contiguous block of memory.
34569 uint64_t resp_addr;
34570 /* Flow record index. */
34571 uint16_t flow_handle;
34572 /* Max flow handle */
34573 #define HWRM_CFA_FLOW_INFO_INPUT_FLOW_HANDLE_MAX_MASK \
34575 #define HWRM_CFA_FLOW_INFO_INPUT_FLOW_HANDLE_MAX_SFT 0
34576 /* CNP flow handle */
34577 #define HWRM_CFA_FLOW_INFO_INPUT_FLOW_HANDLE_CNP_CNT \
34579 /* RoCEv1 flow handle */
34580 #define HWRM_CFA_FLOW_INFO_INPUT_FLOW_HANDLE_ROCEV1_CNT \
34582 /* RoCEv2 flow handle */
34583 #define HWRM_CFA_FLOW_INFO_INPUT_FLOW_HANDLE_ROCEV2_CNT \
34585 /* Direction rx = 1 */
34586 #define HWRM_CFA_FLOW_INFO_INPUT_FLOW_HANDLE_DIR_RX \
34588 uint8_t unused_0[6];
34589 /* This value identifies a set of CFA data structures used for a flow. */
34590 uint64_t ext_flow_handle;
34593 /* hwrm_cfa_flow_info_output (size:5632b/704B) */
34594 struct hwrm_cfa_flow_info_output {
34595 /* The specific error status for the command. */
34596 uint16_t error_code;
34597 /* The HWRM command request type. */
34599 /* The sequence ID from the original command. */
34601 /* The length of the response data in number of bytes. */
34604 /* When set to 1, indicates the configuration is the TX flow. */
34605 #define HWRM_CFA_FLOW_INFO_OUTPUT_FLAGS_PATH_TX UINT32_C(0x1)
34606 /* When set to 1, indicates the configuration is the RX flow. */
34607 #define HWRM_CFA_FLOW_INFO_OUTPUT_FLAGS_PATH_RX UINT32_C(0x2)
34608 /* profile is 8 b */
34610 /* src_fid is 16 b */
34612 /* dst_fid is 16 b */
34614 /* l2_ctxt_id is 16 b */
34615 uint16_t l2_ctxt_id;
34616 /* em_info is 64 b */
34618 /* tcam_info is 64 b */
34619 uint64_t tcam_info;
34620 /* vfp_tcam_info is 64 b */
34621 uint64_t vfp_tcam_info;
34622 /* ar_id is 16 b */
34624 /* flow_handle is 16 b */
34625 uint16_t flow_handle;
34626 /* tunnel_handle is 32 b */
34627 uint32_t tunnel_handle;
34628 /* The flow aging timer for the flow, the unit is 100 milliseconds */
34629 uint16_t flow_timer;
34630 uint8_t unused_0[6];
34631 /* Flow associated L2, L3 and L4 headers info. */
34632 uint32_t flow_key_data[130];
34633 /* Flow associated action record info. */
34634 uint32_t flow_action_info[30];
34635 uint8_t unused_1[7];
34637 * This field is used in Output records to indicate that the output
34638 * is completely written to RAM. This field should be read as '1'
34639 * to indicate that the output has been completely written.
34640 * When writing a command completion or response to an internal processor,
34641 * the order of writes has to be such that this field is written last.
34646 /***********************
34647 * hwrm_cfa_flow_flush *
34648 ***********************/
34651 /* hwrm_cfa_flow_flush_input (size:256b/32B) */
34652 struct hwrm_cfa_flow_flush_input {
34653 /* The HWRM command request type. */
34656 * The completion ring to send the completion event on. This should
34657 * be the NQ ID returned from the `nq_alloc` HWRM command.
34659 uint16_t cmpl_ring;
34661 * The sequence ID is used by the driver for tracking multiple
34662 * commands. This ID is treated as opaque data by the firmware and
34663 * the value is returned in the `hwrm_resp_hdr` upon completion.
34667 * The target ID of the command:
34668 * * 0x0-0xFFF8 - The function ID
34669 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
34670 * * 0xFFFD - Reserved for user-space HWRM interface
34673 uint16_t target_id;
34675 * A physical address pointer pointing to a host buffer that the
34676 * command's response data will be written. This can be either a host
34677 * physical address (HPA) or a guest physical address (GPA) and must
34678 * point to a physically contiguous block of memory.
34680 uint64_t resp_addr;
34681 /* flags is 32 b */
34684 * Set to 1 to indicate the page size, page layers, and flow_handle_table_dma_addr
34685 * fields are valid. The flow flush operation should only flush the flows from the
34686 * flow table specified. This flag is set to 0 by older driver. For older firmware,
34687 * setting this flag has no effect.
34689 #define HWRM_CFA_FLOW_FLUSH_INPUT_FLAGS_FLOW_TABLE_VALID \
34692 * Set to 1 to indicate flow flush operation to cleanup all the flows, meters, CFA
34693 * context memory tables etc. This flag is set to 0 by older driver. For older firmware,
34694 * setting this flag has no effect.
34696 #define HWRM_CFA_FLOW_FLUSH_INPUT_FLAGS_FLOW_RESET_ALL \
34699 * Set to 1 to indicate flow flush operation to cleanup all the flows by the caller.
34700 * This flag is set to 0 by older driver. For older firmware, setting this flag has no effect.
34702 #define HWRM_CFA_FLOW_FLUSH_INPUT_FLAGS_FLOW_RESET_PORT \
34704 /* Set to 1 to indicate the flow counter IDs are included in the flow table. */
34705 #define HWRM_CFA_FLOW_FLUSH_INPUT_FLAGS_FLOW_HANDLE_INCL_FC \
34706 UINT32_C(0x8000000)
34708 * This specifies the size of flow handle entries provided by the driver
34709 * in the flow table specified below. Only two flow handle size enums are defined.
34711 #define HWRM_CFA_FLOW_FLUSH_INPUT_FLAGS_FLOW_HANDLE_ENTRY_SIZE_MASK \
34712 UINT32_C(0xc0000000)
34713 #define HWRM_CFA_FLOW_FLUSH_INPUT_FLAGS_FLOW_HANDLE_ENTRY_SIZE_SFT \
34715 /* The flow handle is 16bit */
34716 #define HWRM_CFA_FLOW_FLUSH_INPUT_FLAGS_FLOW_HANDLE_ENTRY_SIZE_FLOW_HND_16BIT \
34717 (UINT32_C(0x0) << 30)
34718 /* The flow handle is 64bit */
34719 #define HWRM_CFA_FLOW_FLUSH_INPUT_FLAGS_FLOW_HANDLE_ENTRY_SIZE_FLOW_HND_64BIT \
34720 (UINT32_C(0x1) << 30)
34721 #define HWRM_CFA_FLOW_FLUSH_INPUT_FLAGS_FLOW_HANDLE_ENTRY_SIZE_LAST \
34722 HWRM_CFA_FLOW_FLUSH_INPUT_FLAGS_FLOW_HANDLE_ENTRY_SIZE_FLOW_HND_64BIT
34723 /* Specify page size of the flow table memory. */
34725 /* The page size is 4K */
34726 #define HWRM_CFA_FLOW_FLUSH_INPUT_PAGE_SIZE_4K UINT32_C(0x0)
34727 /* The page size is 8K */
34728 #define HWRM_CFA_FLOW_FLUSH_INPUT_PAGE_SIZE_8K UINT32_C(0x1)
34729 /* The page size is 64K */
34730 #define HWRM_CFA_FLOW_FLUSH_INPUT_PAGE_SIZE_64K UINT32_C(0x4)
34731 /* The page size is 256K */
34732 #define HWRM_CFA_FLOW_FLUSH_INPUT_PAGE_SIZE_256K UINT32_C(0x6)
34733 /* The page size is 1M */
34734 #define HWRM_CFA_FLOW_FLUSH_INPUT_PAGE_SIZE_1M UINT32_C(0x8)
34735 /* The page size is 2M */
34736 #define HWRM_CFA_FLOW_FLUSH_INPUT_PAGE_SIZE_2M UINT32_C(0x9)
34737 /* The page size is 4M */
34738 #define HWRM_CFA_FLOW_FLUSH_INPUT_PAGE_SIZE_4M UINT32_C(0xa)
34739 /* The page size is 1G */
34740 #define HWRM_CFA_FLOW_FLUSH_INPUT_PAGE_SIZE_1G UINT32_C(0x12)
34741 #define HWRM_CFA_FLOW_FLUSH_INPUT_PAGE_SIZE_LAST \
34742 HWRM_CFA_FLOW_FLUSH_INPUT_PAGE_SIZE_1G
34743 /* FLow table memory indirect levels. */
34744 uint8_t page_level;
34745 /* PBL pointer is physical start address. */
34746 #define HWRM_CFA_FLOW_FLUSH_INPUT_PAGE_LEVEL_LVL_0 UINT32_C(0x0)
34747 /* PBL pointer points to PTE table. */
34748 #define HWRM_CFA_FLOW_FLUSH_INPUT_PAGE_LEVEL_LVL_1 UINT32_C(0x1)
34749 /* PBL pointer points to PDE table with each entry pointing to PTE tables. */
34750 #define HWRM_CFA_FLOW_FLUSH_INPUT_PAGE_LEVEL_LVL_2 UINT32_C(0x2)
34751 #define HWRM_CFA_FLOW_FLUSH_INPUT_PAGE_LEVEL_LAST \
34752 HWRM_CFA_FLOW_FLUSH_INPUT_PAGE_LEVEL_LVL_2
34753 /* number of flows in the flow table */
34754 uint16_t num_flows;
34755 /* Pointer to the PBL, or PDL depending on number of levels */
34759 /* hwrm_cfa_flow_flush_output (size:128b/16B) */
34760 struct hwrm_cfa_flow_flush_output {
34761 /* The specific error status for the command. */
34762 uint16_t error_code;
34763 /* The HWRM command request type. */
34765 /* The sequence ID from the original command. */
34767 /* The length of the response data in number of bytes. */
34769 uint8_t unused_0[7];
34771 * This field is used in Output records to indicate that the output
34772 * is completely written to RAM. This field should be read as '1'
34773 * to indicate that the output has been completely written.
34774 * When writing a command completion or response to an internal processor,
34775 * the order of writes has to be such that this field is written last.
34780 /***********************
34781 * hwrm_cfa_flow_stats *
34782 ***********************/
34785 /* hwrm_cfa_flow_stats_input (size:640b/80B) */
34786 struct hwrm_cfa_flow_stats_input {
34787 /* The HWRM command request type. */
34790 * The completion ring to send the completion event on. This should
34791 * be the NQ ID returned from the `nq_alloc` HWRM command.
34793 uint16_t cmpl_ring;
34795 * The sequence ID is used by the driver for tracking multiple
34796 * commands. This ID is treated as opaque data by the firmware and
34797 * the value is returned in the `hwrm_resp_hdr` upon completion.
34801 * The target ID of the command:
34802 * * 0x0-0xFFF8 - The function ID
34803 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
34804 * * 0xFFFD - Reserved for user-space HWRM interface
34807 uint16_t target_id;
34809 * A physical address pointer pointing to a host buffer that the
34810 * command's response data will be written. This can be either a host
34811 * physical address (HPA) or a guest physical address (GPA) and must
34812 * point to a physically contiguous block of memory.
34814 uint64_t resp_addr;
34816 uint16_t num_flows;
34818 uint16_t flow_handle_0;
34820 uint16_t flow_handle_1;
34822 uint16_t flow_handle_2;
34824 uint16_t flow_handle_3;
34826 uint16_t flow_handle_4;
34828 uint16_t flow_handle_5;
34830 uint16_t flow_handle_6;
34832 uint16_t flow_handle_7;
34834 uint16_t flow_handle_8;
34836 uint16_t flow_handle_9;
34837 uint8_t unused_0[2];
34838 /* Flow ID of a flow. */
34839 uint32_t flow_id_0;
34840 /* Flow ID of a flow. */
34841 uint32_t flow_id_1;
34842 /* Flow ID of a flow. */
34843 uint32_t flow_id_2;
34844 /* Flow ID of a flow. */
34845 uint32_t flow_id_3;
34846 /* Flow ID of a flow. */
34847 uint32_t flow_id_4;
34848 /* Flow ID of a flow. */
34849 uint32_t flow_id_5;
34850 /* Flow ID of a flow. */
34851 uint32_t flow_id_6;
34852 /* Flow ID of a flow. */
34853 uint32_t flow_id_7;
34854 /* Flow ID of a flow. */
34855 uint32_t flow_id_8;
34856 /* Flow ID of a flow. */
34857 uint32_t flow_id_9;
34860 /* hwrm_cfa_flow_stats_output (size:1408b/176B) */
34861 struct hwrm_cfa_flow_stats_output {
34862 /* The specific error status for the command. */
34863 uint16_t error_code;
34864 /* The HWRM command request type. */
34866 /* The sequence ID from the original command. */
34868 /* The length of the response data in number of bytes. */
34870 /* packet_0 is 64 b */
34872 /* packet_1 is 64 b */
34874 /* packet_2 is 64 b */
34876 /* packet_3 is 64 b */
34878 /* packet_4 is 64 b */
34880 /* packet_5 is 64 b */
34882 /* packet_6 is 64 b */
34884 /* packet_7 is 64 b */
34886 /* packet_8 is 64 b */
34888 /* packet_9 is 64 b */
34890 /* byte_0 is 64 b */
34892 /* byte_1 is 64 b */
34894 /* byte_2 is 64 b */
34896 /* byte_3 is 64 b */
34898 /* byte_4 is 64 b */
34900 /* byte_5 is 64 b */
34902 /* byte_6 is 64 b */
34904 /* byte_7 is 64 b */
34906 /* byte_8 is 64 b */
34908 /* byte_9 is 64 b */
34910 uint8_t unused_0[7];
34912 * This field is used in Output records to indicate that the output
34913 * is completely written to RAM. This field should be read as '1'
34914 * to indicate that the output has been completely written.
34915 * When writing a command completion or response to an internal processor,
34916 * the order of writes has to be such that this field is written last.
34921 /***********************************
34922 * hwrm_cfa_flow_aging_timer_reset *
34923 ***********************************/
34926 /* hwrm_cfa_flow_aging_timer_reset_input (size:256b/32B) */
34927 struct hwrm_cfa_flow_aging_timer_reset_input {
34928 /* The HWRM command request type. */
34931 * The completion ring to send the completion event on. This should
34932 * be the NQ ID returned from the `nq_alloc` HWRM command.
34934 uint16_t cmpl_ring;
34936 * The sequence ID is used by the driver for tracking multiple
34937 * commands. This ID is treated as opaque data by the firmware and
34938 * the value is returned in the `hwrm_resp_hdr` upon completion.
34942 * The target ID of the command:
34943 * * 0x0-0xFFF8 - The function ID
34944 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
34945 * * 0xFFFD - Reserved for user-space HWRM interface
34948 uint16_t target_id;
34950 * A physical address pointer pointing to a host buffer that the
34951 * command's response data will be written. This can be either a host
34952 * physical address (HPA) or a guest physical address (GPA) and must
34953 * point to a physically contiguous block of memory.
34955 uint64_t resp_addr;
34956 /* Flow record index. */
34957 uint16_t flow_handle;
34958 uint8_t unused_0[2];
34960 * New flow timer value for the flow specified in the ext_flow_handle.
34961 * The flow timer unit is 100ms.
34963 uint32_t flow_timer;
34964 /* This value identifies a set of CFA data structures used for a flow. */
34965 uint64_t ext_flow_handle;
34968 /* hwrm_cfa_flow_aging_timer_reset_output (size:128b/16B) */
34969 struct hwrm_cfa_flow_aging_timer_reset_output {
34970 /* The specific error status for the command. */
34971 uint16_t error_code;
34972 /* The HWRM command request type. */
34974 /* The sequence ID from the original command. */
34976 /* The length of the response data in number of bytes. */
34978 uint8_t unused_0[7];
34980 * This field is used in Output records to indicate that the output
34981 * is completely written to RAM. This field should be read as '1'
34982 * to indicate that the output has been completely written.
34983 * When writing a command completion or response to an internal processor,
34984 * the order of writes has to be such that this field is written last.
34989 /***************************
34990 * hwrm_cfa_flow_aging_cfg *
34991 ***************************/
34994 /* hwrm_cfa_flow_aging_cfg_input (size:384b/48B) */
34995 struct hwrm_cfa_flow_aging_cfg_input {
34996 /* The HWRM command request type. */
34999 * The completion ring to send the completion event on. This should
35000 * be the NQ ID returned from the `nq_alloc` HWRM command.
35002 uint16_t cmpl_ring;
35004 * The sequence ID is used by the driver for tracking multiple
35005 * commands. This ID is treated as opaque data by the firmware and
35006 * the value is returned in the `hwrm_resp_hdr` upon completion.
35010 * The target ID of the command:
35011 * * 0x0-0xFFF8 - The function ID
35012 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
35013 * * 0xFFFD - Reserved for user-space HWRM interface
35016 uint16_t target_id;
35018 * A physical address pointer pointing to a host buffer that the
35019 * command's response data will be written. This can be either a host
35020 * physical address (HPA) or a guest physical address (GPA) and must
35021 * point to a physically contiguous block of memory.
35023 uint64_t resp_addr;
35024 /* The bit field to enable per flow aging configuration. */
35026 /* This bit must be '1' for the tcp flow timer field to be configured */
35027 #define HWRM_CFA_FLOW_AGING_CFG_INPUT_ENABLES_TCP_FLOW_TIMER \
35029 /* This bit must be '1' for the tcp finish timer field to be configured */
35030 #define HWRM_CFA_FLOW_AGING_CFG_INPUT_ENABLES_TCP_FIN_TIMER \
35032 /* This bit must be '1' for the udp flow timer field to be configured */
35033 #define HWRM_CFA_FLOW_AGING_CFG_INPUT_ENABLES_UDP_FLOW_TIMER \
35035 /* This bit must be '1' for the eem dma interval field to be configured */
35036 #define HWRM_CFA_FLOW_AGING_CFG_INPUT_ENABLES_EEM_DMA_INTERVAL \
35038 /* This bit must be '1' for the eem notice interval field to be configured */
35039 #define HWRM_CFA_FLOW_AGING_CFG_INPUT_ENABLES_EEM_NOTICE_INTERVAL \
35041 /* This bit must be '1' for the eem context memory maximum entries field to be configured */
35042 #define HWRM_CFA_FLOW_AGING_CFG_INPUT_ENABLES_EEM_CTX_MAX_ENTRIES \
35044 /* This bit must be '1' for the eem context memory ID field to be configured */
35045 #define HWRM_CFA_FLOW_AGING_CFG_INPUT_ENABLES_EEM_CTX_ID \
35047 /* This bit must be '1' for the eem context memory type field to be configured */
35048 #define HWRM_CFA_FLOW_AGING_CFG_INPUT_ENABLES_EEM_CTX_MEM_TYPE \
35051 /* Enumeration denoting the RX, TX type of the resource. */
35052 #define HWRM_CFA_FLOW_AGING_CFG_INPUT_FLAGS_PATH UINT32_C(0x1)
35054 #define HWRM_CFA_FLOW_AGING_CFG_INPUT_FLAGS_PATH_TX UINT32_C(0x0)
35056 #define HWRM_CFA_FLOW_AGING_CFG_INPUT_FLAGS_PATH_RX UINT32_C(0x1)
35057 #define HWRM_CFA_FLOW_AGING_CFG_INPUT_FLAGS_PATH_LAST \
35058 HWRM_CFA_FLOW_AGING_CFG_INPUT_FLAGS_PATH_RX
35059 /* Enumeration denoting the enable, disable eem flow aging configuration. */
35060 #define HWRM_CFA_FLOW_AGING_CFG_INPUT_FLAGS_EEM UINT32_C(0x2)
35062 #define HWRM_CFA_FLOW_AGING_CFG_INPUT_FLAGS_EEM_DISABLE \
35063 (UINT32_C(0x0) << 1)
35065 #define HWRM_CFA_FLOW_AGING_CFG_INPUT_FLAGS_EEM_ENABLE \
35066 (UINT32_C(0x1) << 1)
35067 #define HWRM_CFA_FLOW_AGING_CFG_INPUT_FLAGS_EEM_LAST \
35068 HWRM_CFA_FLOW_AGING_CFG_INPUT_FLAGS_EEM_ENABLE
35070 /* The flow aging timer for all TCP flows, the unit is 100 milliseconds. */
35071 uint32_t tcp_flow_timer;
35072 /* The TCP finished timer for all TCP flows, the unit is 100 milliseconds. */
35073 uint32_t tcp_fin_timer;
35074 /* The flow aging timer for all UDP flows, the unit is 100 milliseconds. */
35075 uint32_t udp_flow_timer;
35076 /* The interval to dma eem ejection data to host memory, the unit is milliseconds. */
35077 uint16_t eem_dma_interval;
35078 /* The interval to notify driver to read the eem ejection data, the unit is milliseconds. */
35079 uint16_t eem_notice_interval;
35080 /* The maximum entries number in the eem context memory. */
35081 uint32_t eem_ctx_max_entries;
35082 /* The context memory ID for eem flow aging. */
35083 uint16_t eem_ctx_id;
35084 uint16_t eem_ctx_mem_type;
35085 /* The content of context memory is eem ejection data, the size of each entry is 4 bytes. */
35086 #define HWRM_CFA_FLOW_AGING_CFG_INPUT_EEM_CTX_MEM_TYPE_EJECTION_DATA \
35088 #define HWRM_CFA_FLOW_AGING_CFG_INPUT_EEM_CTX_MEM_TYPE_LAST \
35089 HWRM_CFA_FLOW_AGING_CFG_INPUT_EEM_CTX_MEM_TYPE_EJECTION_DATA
35090 uint8_t unused_1[4];
35093 /* hwrm_cfa_flow_aging_cfg_output (size:128b/16B) */
35094 struct hwrm_cfa_flow_aging_cfg_output {
35095 /* The specific error status for the command. */
35096 uint16_t error_code;
35097 /* The HWRM command request type. */
35099 /* The sequence ID from the original command. */
35101 /* The length of the response data in number of bytes. */
35103 uint8_t unused_0[7];
35105 * This field is used in Output records to indicate that the output
35106 * is completely written to RAM. This field should be read as '1'
35107 * to indicate that the output has been completely written.
35108 * When writing a command completion or response to an internal processor,
35109 * the order of writes has to be such that this field is written last.
35114 /****************************
35115 * hwrm_cfa_flow_aging_qcfg *
35116 ****************************/
35119 /* hwrm_cfa_flow_aging_qcfg_input (size:192b/24B) */
35120 struct hwrm_cfa_flow_aging_qcfg_input {
35121 /* The HWRM command request type. */
35124 * The completion ring to send the completion event on. This should
35125 * be the NQ ID returned from the `nq_alloc` HWRM command.
35127 uint16_t cmpl_ring;
35129 * The sequence ID is used by the driver for tracking multiple
35130 * commands. This ID is treated as opaque data by the firmware and
35131 * the value is returned in the `hwrm_resp_hdr` upon completion.
35135 * The target ID of the command:
35136 * * 0x0-0xFFF8 - The function ID
35137 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
35138 * * 0xFFFD - Reserved for user-space HWRM interface
35141 uint16_t target_id;
35143 * A physical address pointer pointing to a host buffer that the
35144 * command's response data will be written. This can be either a host
35145 * physical address (HPA) or a guest physical address (GPA) and must
35146 * point to a physically contiguous block of memory.
35148 uint64_t resp_addr;
35149 /* The direction for the flow aging configuration, 1 is rx path, 2 is tx path. */
35151 /* Enumeration denoting the RX, TX type of the resource. */
35152 #define HWRM_CFA_FLOW_AGING_QCFG_INPUT_FLAGS_PATH UINT32_C(0x1)
35154 #define HWRM_CFA_FLOW_AGING_QCFG_INPUT_FLAGS_PATH_TX UINT32_C(0x0)
35156 #define HWRM_CFA_FLOW_AGING_QCFG_INPUT_FLAGS_PATH_RX UINT32_C(0x1)
35157 #define HWRM_CFA_FLOW_AGING_QCFG_INPUT_FLAGS_PATH_LAST \
35158 HWRM_CFA_FLOW_AGING_QCFG_INPUT_FLAGS_PATH_RX
35159 uint8_t unused_0[7];
35162 /* hwrm_cfa_flow_aging_qcfg_output (size:320b/40B) */
35163 struct hwrm_cfa_flow_aging_qcfg_output {
35164 /* The specific error status for the command. */
35165 uint16_t error_code;
35166 /* The HWRM command request type. */
35168 /* The sequence ID from the original command. */
35170 /* The length of the response data in number of bytes. */
35172 /* The current flow aging timer for all TCP flows, the unit is 100 millisecond. */
35173 uint32_t tcp_flow_timer;
35174 /* The current TCP finished timer for all TCP flows, the unit is 100 millisecond. */
35175 uint32_t tcp_fin_timer;
35176 /* The current flow aging timer for all UDP flows, the unit is 100 millisecond. */
35177 uint32_t udp_flow_timer;
35178 /* The interval to dma eem ejection data to host memory, the unit is milliseconds. */
35179 uint16_t eem_dma_interval;
35180 /* The interval to notify driver to read the eem ejection data, the unit is milliseconds. */
35181 uint16_t eem_notice_interval;
35182 /* The maximum entries number in the eem context memory. */
35183 uint32_t eem_ctx_max_entries;
35184 /* The context memory ID for eem flow aging. */
35185 uint16_t eem_ctx_id;
35186 /* The context memory type for eem flow aging. */
35187 uint16_t eem_ctx_mem_type;
35188 uint8_t unused_0[7];
35190 * This field is used in Output records to indicate that the output
35191 * is completely written to RAM. This field should be read as '1'
35192 * to indicate that the output has been completely written.
35193 * When writing a command completion or response to an internal processor,
35194 * the order of writes has to be such that this field is written last.
35199 /*****************************
35200 * hwrm_cfa_flow_aging_qcaps *
35201 *****************************/
35204 /* hwrm_cfa_flow_aging_qcaps_input (size:192b/24B) */
35205 struct hwrm_cfa_flow_aging_qcaps_input {
35206 /* The HWRM command request type. */
35209 * The completion ring to send the completion event on. This should
35210 * be the NQ ID returned from the `nq_alloc` HWRM command.
35212 uint16_t cmpl_ring;
35214 * The sequence ID is used by the driver for tracking multiple
35215 * commands. This ID is treated as opaque data by the firmware and
35216 * the value is returned in the `hwrm_resp_hdr` upon completion.
35220 * The target ID of the command:
35221 * * 0x0-0xFFF8 - The function ID
35222 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
35223 * * 0xFFFD - Reserved for user-space HWRM interface
35226 uint16_t target_id;
35228 * A physical address pointer pointing to a host buffer that the
35229 * command's response data will be written. This can be either a host
35230 * physical address (HPA) or a guest physical address (GPA) and must
35231 * point to a physically contiguous block of memory.
35233 uint64_t resp_addr;
35234 /* The direction for the flow aging configuration, 1 is rx path, 2 is tx path. */
35236 /* Enumeration denoting the RX, TX type of the resource. */
35237 #define HWRM_CFA_FLOW_AGING_QCAPS_INPUT_FLAGS_PATH UINT32_C(0x1)
35239 #define HWRM_CFA_FLOW_AGING_QCAPS_INPUT_FLAGS_PATH_TX UINT32_C(0x0)
35241 #define HWRM_CFA_FLOW_AGING_QCAPS_INPUT_FLAGS_PATH_RX UINT32_C(0x1)
35242 #define HWRM_CFA_FLOW_AGING_QCAPS_INPUT_FLAGS_PATH_LAST \
35243 HWRM_CFA_FLOW_AGING_QCAPS_INPUT_FLAGS_PATH_RX
35244 uint8_t unused_0[7];
35247 /* hwrm_cfa_flow_aging_qcaps_output (size:256b/32B) */
35248 struct hwrm_cfa_flow_aging_qcaps_output {
35249 /* The specific error status for the command. */
35250 uint16_t error_code;
35251 /* The HWRM command request type. */
35253 /* The sequence ID from the original command. */
35255 /* The length of the response data in number of bytes. */
35257 /* The maximum flow aging timer for all TCP flows, the unit is 100 millisecond. */
35258 uint32_t max_tcp_flow_timer;
35259 /* The maximum TCP finished timer for all TCP flows, the unit is 100 millisecond. */
35260 uint32_t max_tcp_fin_timer;
35261 /* The maximum flow aging timer for all UDP flows, the unit is 100 millisecond. */
35262 uint32_t max_udp_flow_timer;
35263 /* The maximum aging flows that HW can support. */
35264 uint32_t max_aging_flows;
35265 uint8_t unused_0[7];
35267 * This field is used in Output records to indicate that the output
35268 * is completely written to RAM. This field should be read as '1'
35269 * to indicate that the output has been completely written.
35270 * When writing a command completion or response to an internal processor,
35271 * the order of writes has to be such that this field is written last.
35276 /**********************************
35277 * hwrm_cfa_tcp_flag_process_qcfg *
35278 **********************************/
35281 /* hwrm_cfa_tcp_flag_process_qcfg_input (size:128b/16B) */
35282 struct hwrm_cfa_tcp_flag_process_qcfg_input {
35283 /* The HWRM command request type. */
35286 * The completion ring to send the completion event on. This should
35287 * be the NQ ID returned from the `nq_alloc` HWRM command.
35289 uint16_t cmpl_ring;
35291 * The sequence ID is used by the driver for tracking multiple
35292 * commands. This ID is treated as opaque data by the firmware and
35293 * the value is returned in the `hwrm_resp_hdr` upon completion.
35297 * The target ID of the command:
35298 * * 0x0-0xFFF8 - The function ID
35299 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
35300 * * 0xFFFD - Reserved for user-space HWRM interface
35303 uint16_t target_id;
35305 * A physical address pointer pointing to a host buffer that the
35306 * command's response data will be written. This can be either a host
35307 * physical address (HPA) or a guest physical address (GPA) and must
35308 * point to a physically contiguous block of memory.
35310 uint64_t resp_addr;
35313 /* hwrm_cfa_tcp_flag_process_qcfg_output (size:192b/24B) */
35314 struct hwrm_cfa_tcp_flag_process_qcfg_output {
35315 /* The specific error status for the command. */
35316 uint16_t error_code;
35317 /* The HWRM command request type. */
35319 /* The sequence ID from the original command. */
35321 /* The length of the response data in number of bytes. */
35323 /* The port 0 RX mirror action record ID. */
35324 uint16_t rx_ar_id_port0;
35325 /* The port 1 RX mirror action record ID. */
35326 uint16_t rx_ar_id_port1;
35327 /* The port 0 RX action record ID for TX TCP flag packets from loopback path. */
35328 uint16_t tx_ar_id_port0;
35329 /* The port 1 RX action record ID for TX TCP flag packets from loopback path. */
35330 uint16_t tx_ar_id_port1;
35331 uint8_t unused_0[7];
35333 * This field is used in Output records to indicate that the output
35334 * is completely written to RAM. This field should be read as '1'
35335 * to indicate that the output has been completely written.
35336 * When writing a command completion or response to an internal processor,
35337 * the order of writes has to be such that this field is written last.
35342 /**********************
35343 * hwrm_cfa_pair_info *
35344 **********************/
35347 /* hwrm_cfa_pair_info_input (size:448b/56B) */
35348 struct hwrm_cfa_pair_info_input {
35349 /* The HWRM command request type. */
35352 * The completion ring to send the completion event on. This should
35353 * be the NQ ID returned from the `nq_alloc` HWRM command.
35355 uint16_t cmpl_ring;
35357 * The sequence ID is used by the driver for tracking multiple
35358 * commands. This ID is treated as opaque data by the firmware and
35359 * the value is returned in the `hwrm_resp_hdr` upon completion.
35363 * The target ID of the command:
35364 * * 0x0-0xFFF8 - The function ID
35365 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
35366 * * 0xFFFD - Reserved for user-space HWRM interface
35369 uint16_t target_id;
35371 * A physical address pointer pointing to a host buffer that the
35372 * command's response data will be written. This can be either a host
35373 * physical address (HPA) or a guest physical address (GPA) and must
35374 * point to a physically contiguous block of memory.
35376 uint64_t resp_addr;
35378 /* If this flag is set, lookup by name else lookup by index. */
35379 #define HWRM_CFA_PAIR_INFO_INPUT_FLAGS_LOOKUP_TYPE UINT32_C(0x1)
35380 /* If this flag is set, lookup by PF id and VF id. */
35381 #define HWRM_CFA_PAIR_INFO_INPUT_FLAGS_LOOKUP_REPRE UINT32_C(0x2)
35382 /* Pair table index. */
35383 uint16_t pair_index;
35384 /* Pair pf index. */
35386 /* Pair vf index. */
35388 /* Pair name (32 byte string). */
35389 char pair_name[32];
35392 /* hwrm_cfa_pair_info_output (size:576b/72B) */
35393 struct hwrm_cfa_pair_info_output {
35394 /* The specific error status for the command. */
35395 uint16_t error_code;
35396 /* The HWRM command request type. */
35398 /* The sequence ID from the original command. */
35400 /* The length of the response data in number of bytes. */
35402 /* Pair table index. */
35403 uint16_t next_pair_index;
35404 /* Pair member a's fid. */
35406 /* Logical host number. */
35407 uint8_t host_a_index;
35408 /* Logical PF number. */
35409 uint8_t pf_a_index;
35410 /* Pair member a's Linux logical VF number. */
35411 uint16_t vf_a_index;
35413 uint16_t rx_cfa_code_a;
35414 /* Tx CFA action. */
35415 uint16_t tx_cfa_action_a;
35416 /* Pair member b's fid. */
35418 /* Logical host number. */
35419 uint8_t host_b_index;
35420 /* Logical PF number. */
35421 uint8_t pf_b_index;
35422 /* Pair member a's Linux logical VF number. */
35423 uint16_t vf_b_index;
35425 uint16_t rx_cfa_code_b;
35426 /* Tx CFA action. */
35427 uint16_t tx_cfa_action_b;
35428 /* Pair mode (0-vf2fn, 1-rep2fn, 2-rep2rep, 3-proxy, 4-pfpair). */
35430 /* Pair between VF on local host with PF or VF on specified host. */
35431 #define HWRM_CFA_PAIR_INFO_OUTPUT_PAIR_MODE_VF2FN UINT32_C(0x0)
35432 /* Pair between REP on local host with PF or VF on specified host. */
35433 #define HWRM_CFA_PAIR_INFO_OUTPUT_PAIR_MODE_REP2FN UINT32_C(0x1)
35434 /* Pair between REP on local host with REP on specified host. */
35435 #define HWRM_CFA_PAIR_INFO_OUTPUT_PAIR_MODE_REP2REP UINT32_C(0x2)
35436 /* Pair for the proxy interface. */
35437 #define HWRM_CFA_PAIR_INFO_OUTPUT_PAIR_MODE_PROXY UINT32_C(0x3)
35438 /* Pair for the PF interface. */
35439 #define HWRM_CFA_PAIR_INFO_OUTPUT_PAIR_MODE_PFPAIR UINT32_C(0x4)
35440 #define HWRM_CFA_PAIR_INFO_OUTPUT_PAIR_MODE_LAST \
35441 HWRM_CFA_PAIR_INFO_OUTPUT_PAIR_MODE_PFPAIR
35443 uint8_t pair_state;
35444 /* Pair has been allocated */
35445 #define HWRM_CFA_PAIR_INFO_OUTPUT_PAIR_STATE_ALLOCATED UINT32_C(0x1)
35446 /* Both pair members are active */
35447 #define HWRM_CFA_PAIR_INFO_OUTPUT_PAIR_STATE_ACTIVE UINT32_C(0x2)
35448 #define HWRM_CFA_PAIR_INFO_OUTPUT_PAIR_STATE_LAST \
35449 HWRM_CFA_PAIR_INFO_OUTPUT_PAIR_STATE_ACTIVE
35450 /* Pair name (32 byte string). */
35451 char pair_name[32];
35452 uint8_t unused_0[7];
35454 * This field is used in Output records to indicate that the output
35455 * is completely written to RAM. This field should be read as '1'
35456 * to indicate that the output has been completely written.
35457 * When writing a command completion or response to an internal processor,
35458 * the order of writes has to be such that this field is written last.
35463 /**********************
35464 * hwrm_cfa_vfr_alloc *
35465 **********************/
35468 /* hwrm_cfa_vfr_alloc_input (size:448b/56B) */
35469 struct hwrm_cfa_vfr_alloc_input {
35470 /* The HWRM command request type. */
35473 * The completion ring to send the completion event on. This should
35474 * be the NQ ID returned from the `nq_alloc` HWRM command.
35476 uint16_t cmpl_ring;
35478 * The sequence ID is used by the driver for tracking multiple
35479 * commands. This ID is treated as opaque data by the firmware and
35480 * the value is returned in the `hwrm_resp_hdr` upon completion.
35484 * The target ID of the command:
35485 * * 0x0-0xFFF8 - The function ID
35486 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
35487 * * 0xFFFD - Reserved for user-space HWRM interface
35490 uint16_t target_id;
35492 * A physical address pointer pointing to a host buffer that the
35493 * command's response data will be written. This can be either a host
35494 * physical address (HPA) or a guest physical address (GPA) and must
35495 * point to a physically contiguous block of memory.
35497 uint64_t resp_addr;
35498 /* Logical VF number (range: 0 -> MAX_VFS -1). */
35501 * This field is reserved for the future use.
35502 * It shall be set to 0.
35505 uint8_t unused_0[4];
35506 /* VF Representor name (32 byte string). */
35510 /* hwrm_cfa_vfr_alloc_output (size:128b/16B) */
35511 struct hwrm_cfa_vfr_alloc_output {
35512 /* The specific error status for the command. */
35513 uint16_t error_code;
35514 /* The HWRM command request type. */
35516 /* The sequence ID from the original command. */
35518 /* The length of the response data in number of bytes. */
35521 uint16_t rx_cfa_code;
35522 /* Tx CFA action. */
35523 uint16_t tx_cfa_action;
35524 uint8_t unused_0[3];
35526 * This field is used in Output records to indicate that the output
35527 * is completely written to RAM. This field should be read as '1'
35528 * to indicate that the output has been completely written.
35529 * When writing a command completion or response to an internal processor,
35530 * the order of writes has to be such that this field is written last.
35535 /*********************
35536 * hwrm_cfa_vfr_free *
35537 *********************/
35540 /* hwrm_cfa_vfr_free_input (size:448b/56B) */
35541 struct hwrm_cfa_vfr_free_input {
35542 /* The HWRM command request type. */
35545 * The completion ring to send the completion event on. This should
35546 * be the NQ ID returned from the `nq_alloc` HWRM command.
35548 uint16_t cmpl_ring;
35550 * The sequence ID is used by the driver for tracking multiple
35551 * commands. This ID is treated as opaque data by the firmware and
35552 * the value is returned in the `hwrm_resp_hdr` upon completion.
35556 * The target ID of the command:
35557 * * 0x0-0xFFF8 - The function ID
35558 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
35559 * * 0xFFFD - Reserved for user-space HWRM interface
35562 uint16_t target_id;
35564 * A physical address pointer pointing to a host buffer that the
35565 * command's response data will be written. This can be either a host
35566 * physical address (HPA) or a guest physical address (GPA) and must
35567 * point to a physically contiguous block of memory.
35569 uint64_t resp_addr;
35570 /* VF Representor name (32 byte string). */
35572 /* Logical VF number (range: 0 -> MAX_VFS -1). */
35575 uint8_t unused_0[4];
35578 /* hwrm_cfa_vfr_free_output (size:128b/16B) */
35579 struct hwrm_cfa_vfr_free_output {
35580 /* The specific error status for the command. */
35581 uint16_t error_code;
35582 /* The HWRM command request type. */
35584 /* The sequence ID from the original command. */
35586 /* The length of the response data in number of bytes. */
35588 uint8_t unused_0[7];
35590 * This field is used in Output records to indicate that the output
35591 * is completely written to RAM. This field should be read as '1'
35592 * to indicate that the output has been completely written.
35593 * When writing a command completion or response to an internal processor,
35594 * the order of writes has to be such that this field is written last.
35601 /***************************************
35602 * hwrm_cfa_redirect_query_tunnel_type *
35603 ***************************************/
35606 /* hwrm_cfa_redirect_query_tunnel_type_input (size:192b/24B) */
35607 struct hwrm_cfa_redirect_query_tunnel_type_input {
35608 /* The HWRM command request type. */
35611 * The completion ring to send the completion event on. This should
35612 * be the NQ ID returned from the `nq_alloc` HWRM command.
35614 uint16_t cmpl_ring;
35616 * The sequence ID is used by the driver for tracking multiple
35617 * commands. This ID is treated as opaque data by the firmware and
35618 * the value is returned in the `hwrm_resp_hdr` upon completion.
35622 * The target ID of the command:
35623 * * 0x0-0xFFF8 - The function ID
35624 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
35625 * * 0xFFFD - Reserved for user-space HWRM interface
35628 uint16_t target_id;
35630 * A physical address pointer pointing to a host buffer that the
35631 * command's response data will be written. This can be either a host
35632 * physical address (HPA) or a guest physical address (GPA) and must
35633 * point to a physically contiguous block of memory.
35635 uint64_t resp_addr;
35636 /* The source function id. */
35638 uint8_t unused_0[6];
35641 /* hwrm_cfa_redirect_query_tunnel_type_output (size:128b/16B) */
35642 struct hwrm_cfa_redirect_query_tunnel_type_output {
35643 /* The specific error status for the command. */
35644 uint16_t error_code;
35645 /* The HWRM command request type. */
35647 /* The sequence ID from the original command. */
35649 /* The length of the response data in number of bytes. */
35652 uint32_t tunnel_mask;
35654 #define HWRM_CFA_REDIRECT_QUERY_TUNNEL_TYPE_OUTPUT_TUNNEL_MASK_NONTUNNEL \
35656 /* Virtual eXtensible Local Area Network (VXLAN) */
35657 #define HWRM_CFA_REDIRECT_QUERY_TUNNEL_TYPE_OUTPUT_TUNNEL_MASK_VXLAN \
35659 /* Network Virtualization Generic Routing Encapsulation (NVGRE) */
35660 #define HWRM_CFA_REDIRECT_QUERY_TUNNEL_TYPE_OUTPUT_TUNNEL_MASK_NVGRE \
35662 /* Generic Routing Encapsulation (GRE) inside Ethernet payload */
35663 #define HWRM_CFA_REDIRECT_QUERY_TUNNEL_TYPE_OUTPUT_TUNNEL_MASK_L2GRE \
35666 #define HWRM_CFA_REDIRECT_QUERY_TUNNEL_TYPE_OUTPUT_TUNNEL_MASK_IPIP \
35668 /* Generic Network Virtualization Encapsulation (Geneve) */
35669 #define HWRM_CFA_REDIRECT_QUERY_TUNNEL_TYPE_OUTPUT_TUNNEL_MASK_GENEVE \
35671 /* Multi-Protocol Label Switching (MPLS) */
35672 #define HWRM_CFA_REDIRECT_QUERY_TUNNEL_TYPE_OUTPUT_TUNNEL_MASK_MPLS \
35674 /* Stateless Transport Tunnel (STT) */
35675 #define HWRM_CFA_REDIRECT_QUERY_TUNNEL_TYPE_OUTPUT_TUNNEL_MASK_STT \
35677 /* Generic Routing Encapsulation (GRE) inside IP datagram payload */
35678 #define HWRM_CFA_REDIRECT_QUERY_TUNNEL_TYPE_OUTPUT_TUNNEL_MASK_IPGRE \
35680 /* IPV4 over virtual eXtensible Local Area Network (IPV4oVXLAN) */
35681 #define HWRM_CFA_REDIRECT_QUERY_TUNNEL_TYPE_OUTPUT_TUNNEL_MASK_VXLAN_V4 \
35683 /* Enhance Generic Routing Encapsulation (GRE version 1) inside IP datagram payload */
35684 #define HWRM_CFA_REDIRECT_QUERY_TUNNEL_TYPE_OUTPUT_TUNNEL_MASK_IPGRE_V1 \
35686 /* Any tunneled traffic */
35687 #define HWRM_CFA_REDIRECT_QUERY_TUNNEL_TYPE_OUTPUT_TUNNEL_MASK_ANYTUNNEL \
35689 /* Use fixed layer 2 ether type of 0xFFFF */
35690 #define HWRM_CFA_REDIRECT_QUERY_TUNNEL_TYPE_OUTPUT_TUNNEL_MASK_L2_ETYPE \
35692 /* IPV6 over virtual eXtensible Local Area Network with GPE header (IPV6oVXLANGPE) */
35693 #define HWRM_CFA_REDIRECT_QUERY_TUNNEL_TYPE_OUTPUT_TUNNEL_MASK_VXLAN_GPE_V6 \
35695 uint8_t unused_0[3];
35697 * This field is used in Output records to indicate that the output
35698 * is completely written to RAM. This field should be read as '1'
35699 * to indicate that the output has been completely written.
35700 * When writing a command completion or response to an internal processor,
35701 * the order of writes has to be such that this field is written last.
35706 /*************************
35707 * hwrm_cfa_ctx_mem_rgtr *
35708 *************************/
35711 /* hwrm_cfa_ctx_mem_rgtr_input (size:256b/32B) */
35712 struct hwrm_cfa_ctx_mem_rgtr_input {
35713 /* The HWRM command request type. */
35716 * The completion ring to send the completion event on. This should
35717 * be the NQ ID returned from the `nq_alloc` HWRM command.
35719 uint16_t cmpl_ring;
35721 * The sequence ID is used by the driver for tracking multiple
35722 * commands. This ID is treated as opaque data by the firmware and
35723 * the value is returned in the `hwrm_resp_hdr` upon completion.
35727 * The target ID of the command:
35728 * * 0x0-0xFFF8 - The function ID
35729 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
35730 * * 0xFFFD - Reserved for user-space HWRM interface
35733 uint16_t target_id;
35735 * A physical address pointer pointing to a host buffer that the
35736 * command's response data will be written. This can be either a host
35737 * physical address (HPA) or a guest physical address (GPA) and must
35738 * point to a physically contiguous block of memory.
35740 uint64_t resp_addr;
35742 /* Counter PBL indirect levels. */
35743 uint8_t page_level;
35744 /* PBL pointer is physical start address. */
35745 #define HWRM_CFA_CTX_MEM_RGTR_INPUT_PAGE_LEVEL_LVL_0 UINT32_C(0x0)
35746 /* PBL pointer points to PTE table. */
35747 #define HWRM_CFA_CTX_MEM_RGTR_INPUT_PAGE_LEVEL_LVL_1 UINT32_C(0x1)
35748 /* PBL pointer points to PDE table with each entry pointing to PTE tables. */
35749 #define HWRM_CFA_CTX_MEM_RGTR_INPUT_PAGE_LEVEL_LVL_2 UINT32_C(0x2)
35750 #define HWRM_CFA_CTX_MEM_RGTR_INPUT_PAGE_LEVEL_LAST \
35751 HWRM_CFA_CTX_MEM_RGTR_INPUT_PAGE_LEVEL_LVL_2
35754 /* 4KB page size. */
35755 #define HWRM_CFA_CTX_MEM_RGTR_INPUT_PAGE_SIZE_4K UINT32_C(0x0)
35756 /* 8KB page size. */
35757 #define HWRM_CFA_CTX_MEM_RGTR_INPUT_PAGE_SIZE_8K UINT32_C(0x1)
35758 /* 64KB page size. */
35759 #define HWRM_CFA_CTX_MEM_RGTR_INPUT_PAGE_SIZE_64K UINT32_C(0x4)
35760 /* 256KB page size. */
35761 #define HWRM_CFA_CTX_MEM_RGTR_INPUT_PAGE_SIZE_256K UINT32_C(0x6)
35762 /* 1MB page size. */
35763 #define HWRM_CFA_CTX_MEM_RGTR_INPUT_PAGE_SIZE_1M UINT32_C(0x8)
35764 /* 2MB page size. */
35765 #define HWRM_CFA_CTX_MEM_RGTR_INPUT_PAGE_SIZE_2M UINT32_C(0x9)
35766 /* 4MB page size. */
35767 #define HWRM_CFA_CTX_MEM_RGTR_INPUT_PAGE_SIZE_4M UINT32_C(0xa)
35768 /* 1GB page size. */
35769 #define HWRM_CFA_CTX_MEM_RGTR_INPUT_PAGE_SIZE_1G UINT32_C(0x12)
35770 #define HWRM_CFA_CTX_MEM_RGTR_INPUT_PAGE_SIZE_LAST \
35771 HWRM_CFA_CTX_MEM_RGTR_INPUT_PAGE_SIZE_1G
35773 /* Pointer to the PBL, or PDL depending on number of levels */
35777 /* hwrm_cfa_ctx_mem_rgtr_output (size:128b/16B) */
35778 struct hwrm_cfa_ctx_mem_rgtr_output {
35779 /* The specific error status for the command. */
35780 uint16_t error_code;
35781 /* The HWRM command request type. */
35783 /* The sequence ID from the original command. */
35785 /* The length of the response data in number of bytes. */
35788 * Id/Handle to the recently register context memory. This handle is passed
35789 * to the CFA feature.
35792 uint8_t unused_0[5];
35794 * This field is used in Output records to indicate that the output
35795 * is completely written to RAM. This field should be read as '1'
35796 * to indicate that the output has been completely written.
35797 * When writing a command completion or response to an internal processor,
35798 * the order of writes has to be such that this field is written last.
35803 /***************************
35804 * hwrm_cfa_ctx_mem_unrgtr *
35805 ***************************/
35808 /* hwrm_cfa_ctx_mem_unrgtr_input (size:192b/24B) */
35809 struct hwrm_cfa_ctx_mem_unrgtr_input {
35810 /* The HWRM command request type. */
35813 * The completion ring to send the completion event on. This should
35814 * be the NQ ID returned from the `nq_alloc` HWRM command.
35816 uint16_t cmpl_ring;
35818 * The sequence ID is used by the driver for tracking multiple
35819 * commands. This ID is treated as opaque data by the firmware and
35820 * the value is returned in the `hwrm_resp_hdr` upon completion.
35824 * The target ID of the command:
35825 * * 0x0-0xFFF8 - The function ID
35826 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
35827 * * 0xFFFD - Reserved for user-space HWRM interface
35830 uint16_t target_id;
35832 * A physical address pointer pointing to a host buffer that the
35833 * command's response data will be written. This can be either a host
35834 * physical address (HPA) or a guest physical address (GPA) and must
35835 * point to a physically contiguous block of memory.
35837 uint64_t resp_addr;
35839 * Id/Handle to the recently register context memory. This handle is passed
35840 * to the CFA feature.
35843 uint8_t unused_0[6];
35846 /* hwrm_cfa_ctx_mem_unrgtr_output (size:128b/16B) */
35847 struct hwrm_cfa_ctx_mem_unrgtr_output {
35848 /* The specific error status for the command. */
35849 uint16_t error_code;
35850 /* The HWRM command request type. */
35852 /* The sequence ID from the original command. */
35854 /* The length of the response data in number of bytes. */
35856 uint8_t unused_0[7];
35858 * This field is used in Output records to indicate that the output
35859 * is completely written to RAM. This field should be read as '1'
35860 * to indicate that the output has been completely written.
35861 * When writing a command completion or response to an internal processor,
35862 * the order of writes has to be such that this field is written last.
35867 /*************************
35868 * hwrm_cfa_ctx_mem_qctx *
35869 *************************/
35872 /* hwrm_cfa_ctx_mem_qctx_input (size:192b/24B) */
35873 struct hwrm_cfa_ctx_mem_qctx_input {
35874 /* The HWRM command request type. */
35877 * The completion ring to send the completion event on. This should
35878 * be the NQ ID returned from the `nq_alloc` HWRM command.
35880 uint16_t cmpl_ring;
35882 * The sequence ID is used by the driver for tracking multiple
35883 * commands. This ID is treated as opaque data by the firmware and
35884 * the value is returned in the `hwrm_resp_hdr` upon completion.
35888 * The target ID of the command:
35889 * * 0x0-0xFFF8 - The function ID
35890 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
35891 * * 0xFFFD - Reserved for user-space HWRM interface
35894 uint16_t target_id;
35896 * A physical address pointer pointing to a host buffer that the
35897 * command's response data will be written. This can be either a host
35898 * physical address (HPA) or a guest physical address (GPA) and must
35899 * point to a physically contiguous block of memory.
35901 uint64_t resp_addr;
35903 * Id/Handle to the recently register context memory. This handle is passed
35904 * to the CFA feature.
35907 uint8_t unused_0[6];
35910 /* hwrm_cfa_ctx_mem_qctx_output (size:256b/32B) */
35911 struct hwrm_cfa_ctx_mem_qctx_output {
35912 /* The specific error status for the command. */
35913 uint16_t error_code;
35914 /* The HWRM command request type. */
35916 /* The sequence ID from the original command. */
35918 /* The length of the response data in number of bytes. */
35921 /* Counter PBL indirect levels. */
35922 uint8_t page_level;
35923 /* PBL pointer is physical start address. */
35924 #define HWRM_CFA_CTX_MEM_QCTX_OUTPUT_PAGE_LEVEL_LVL_0 UINT32_C(0x0)
35925 /* PBL pointer points to PTE table. */
35926 #define HWRM_CFA_CTX_MEM_QCTX_OUTPUT_PAGE_LEVEL_LVL_1 UINT32_C(0x1)
35927 /* PBL pointer points to PDE table with each entry pointing to PTE tables. */
35928 #define HWRM_CFA_CTX_MEM_QCTX_OUTPUT_PAGE_LEVEL_LVL_2 UINT32_C(0x2)
35929 #define HWRM_CFA_CTX_MEM_QCTX_OUTPUT_PAGE_LEVEL_LAST \
35930 HWRM_CFA_CTX_MEM_QCTX_OUTPUT_PAGE_LEVEL_LVL_2
35933 /* 4KB page size. */
35934 #define HWRM_CFA_CTX_MEM_QCTX_OUTPUT_PAGE_SIZE_4K UINT32_C(0x0)
35935 /* 8KB page size. */
35936 #define HWRM_CFA_CTX_MEM_QCTX_OUTPUT_PAGE_SIZE_8K UINT32_C(0x1)
35937 /* 64KB page size. */
35938 #define HWRM_CFA_CTX_MEM_QCTX_OUTPUT_PAGE_SIZE_64K UINT32_C(0x4)
35939 /* 256KB page size. */
35940 #define HWRM_CFA_CTX_MEM_QCTX_OUTPUT_PAGE_SIZE_256K UINT32_C(0x6)
35941 /* 1MB page size. */
35942 #define HWRM_CFA_CTX_MEM_QCTX_OUTPUT_PAGE_SIZE_1M UINT32_C(0x8)
35943 /* 2MB page size. */
35944 #define HWRM_CFA_CTX_MEM_QCTX_OUTPUT_PAGE_SIZE_2M UINT32_C(0x9)
35945 /* 4MB page size. */
35946 #define HWRM_CFA_CTX_MEM_QCTX_OUTPUT_PAGE_SIZE_4M UINT32_C(0xa)
35947 /* 1GB page size. */
35948 #define HWRM_CFA_CTX_MEM_QCTX_OUTPUT_PAGE_SIZE_1G UINT32_C(0x12)
35949 #define HWRM_CFA_CTX_MEM_QCTX_OUTPUT_PAGE_SIZE_LAST \
35950 HWRM_CFA_CTX_MEM_QCTX_OUTPUT_PAGE_SIZE_1G
35951 uint8_t unused_0[4];
35952 /* Pointer to the PBL, or PDL depending on number of levels */
35954 uint8_t unused_1[7];
35956 * This field is used in Output records to indicate that the output
35957 * is completely written to RAM. This field should be read as '1'
35958 * to indicate that the output has been completely written.
35959 * When writing a command completion or response to an internal processor,
35960 * the order of writes has to be such that this field is written last.
35965 /**************************
35966 * hwrm_cfa_ctx_mem_qcaps *
35967 **************************/
35970 /* hwrm_cfa_ctx_mem_qcaps_input (size:128b/16B) */
35971 struct hwrm_cfa_ctx_mem_qcaps_input {
35972 /* The HWRM command request type. */
35975 * The completion ring to send the completion event on. This should
35976 * be the NQ ID returned from the `nq_alloc` HWRM command.
35978 uint16_t cmpl_ring;
35980 * The sequence ID is used by the driver for tracking multiple
35981 * commands. This ID is treated as opaque data by the firmware and
35982 * the value is returned in the `hwrm_resp_hdr` upon completion.
35986 * The target ID of the command:
35987 * * 0x0-0xFFF8 - The function ID
35988 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
35989 * * 0xFFFD - Reserved for user-space HWRM interface
35992 uint16_t target_id;
35994 * A physical address pointer pointing to a host buffer that the
35995 * command's response data will be written. This can be either a host
35996 * physical address (HPA) or a guest physical address (GPA) and must
35997 * point to a physically contiguous block of memory.
35999 uint64_t resp_addr;
36002 /* hwrm_cfa_ctx_mem_qcaps_output (size:128b/16B) */
36003 struct hwrm_cfa_ctx_mem_qcaps_output {
36004 /* The specific error status for the command. */
36005 uint16_t error_code;
36006 /* The HWRM command request type. */
36008 /* The sequence ID from the original command. */
36010 /* The length of the response data in number of bytes. */
36012 /* Indicates the maximum number of context memory which can be registered. */
36013 uint16_t max_entries;
36014 uint8_t unused_0[5];
36016 * This field is used in Output records to indicate that the output
36017 * is completely written to RAM. This field should be read as '1'
36018 * to indicate that the output has been completely written.
36019 * When writing a command completion or response to an internal processor,
36020 * the order of writes has to be such that this field is written last.
36025 /**********************
36026 * hwrm_cfa_eem_qcaps *
36027 **********************/
36030 /* hwrm_cfa_eem_qcaps_input (size:192b/24B) */
36031 struct hwrm_cfa_eem_qcaps_input {
36032 /* The HWRM command request type. */
36035 * The completion ring to send the completion event on. This should
36036 * be the NQ ID returned from the `nq_alloc` HWRM command.
36038 uint16_t cmpl_ring;
36040 * The sequence ID is used by the driver for tracking multiple
36041 * commands. This ID is treated as opaque data by the firmware and
36042 * the value is returned in the `hwrm_resp_hdr` upon completion.
36046 * The target ID of the command:
36047 * * 0x0-0xFFF8 - The function ID
36048 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
36049 * * 0xFFFD - Reserved for user-space HWRM interface
36052 uint16_t target_id;
36054 * A physical address pointer pointing to a host buffer that the
36055 * command's response data will be written. This can be either a host
36056 * physical address (HPA) or a guest physical address (GPA) and must
36057 * point to a physically contiguous block of memory.
36059 uint64_t resp_addr;
36062 * When set to 1, indicates the configuration will apply to TX flows
36063 * which are to be offloaded.
36064 * Note if this bit is set then the path_rx bit can't be set.
36066 #define HWRM_CFA_EEM_QCAPS_INPUT_FLAGS_PATH_TX \
36069 * When set to 1, indicates the configuration will apply to RX flows
36070 * which are to be offloaded.
36071 * Note if this bit is set then the path_tx bit can't be set.
36073 #define HWRM_CFA_EEM_QCAPS_INPUT_FLAGS_PATH_RX \
36075 /* When set to 1, all offloaded flows will be sent to EEM. */
36076 #define HWRM_CFA_EEM_QCAPS_INPUT_FLAGS_PREFERRED_OFFLOAD \
36081 /* hwrm_cfa_eem_qcaps_output (size:320b/40B) */
36082 struct hwrm_cfa_eem_qcaps_output {
36083 /* The specific error status for the command. */
36084 uint16_t error_code;
36085 /* The HWRM command request type. */
36087 /* The sequence ID from the original command. */
36089 /* The length of the response data in number of bytes. */
36093 * When set to 1, indicates the configuration will apply to TX flows
36094 * which are to be offloaded.
36095 * Note if this bit is set then the path_rx bit can't be set.
36097 #define HWRM_CFA_EEM_QCAPS_OUTPUT_FLAGS_PATH_TX \
36100 * When set to 1, indicates the configuration will apply to RX flows
36101 * which are to be offloaded.
36102 * Note if this bit is set then the path_tx bit can't be set.
36104 #define HWRM_CFA_EEM_QCAPS_OUTPUT_FLAGS_PATH_RX \
36107 * When set to 1, indicates the the FW supports the Centralized
36108 * Memory Model. The concept designates one entity for the
36109 * memory allocation while all others ‘subscribe’ to it.
36111 #define HWRM_CFA_EEM_QCAPS_OUTPUT_FLAGS_CENTRALIZED_MEMORY_MODEL_SUPPORTED \
36114 * When set to 1, indicates the the FW supports the Detached
36115 * Centralized Memory Model. The memory is allocated and managed
36116 * as a separate entity. All PFs and VFs will be granted direct
36117 * or semi-direct access to the allocated memory while none of
36118 * which can interfere with the management of the memory.
36120 #define HWRM_CFA_EEM_QCAPS_OUTPUT_FLAGS_DETACHED_CENTRALIZED_MEMORY_MODEL_SUPPORTED \
36123 uint32_t supported;
36125 * If set to 1, then EEM KEY0 table is supported using crc32 hash.
36126 * If set to 0, EEM KEY0 table is not supported.
36128 #define HWRM_CFA_EEM_QCAPS_OUTPUT_SUPPORTED_KEY0_TABLE \
36131 * If set to 1, then EEM KEY1 table is supported using lookup3 hash.
36132 * If set to 0, EEM KEY1 table is not supported.
36134 #define HWRM_CFA_EEM_QCAPS_OUTPUT_SUPPORTED_KEY1_TABLE \
36137 * If set to 1, then EEM External Record table is supported.
36138 * If set to 0, EEM External Record table is not supported.
36139 * (This table includes action record, EFC pointers, encap pointers)
36141 #define HWRM_CFA_EEM_QCAPS_OUTPUT_SUPPORTED_EXTERNAL_RECORD_TABLE \
36144 * If set to 1, then EEM External Flow Counters table is supported.
36145 * If set to 0, EEM External Flow Counters table is not supported.
36147 #define HWRM_CFA_EEM_QCAPS_OUTPUT_SUPPORTED_EXTERNAL_FLOW_COUNTERS_TABLE \
36150 * If set to 1, then FID table used for implicit flow flush is supported.
36151 * If set to 0, then FID table used for implicit flow flush is not supported.
36153 #define HWRM_CFA_EEM_QCAPS_OUTPUT_SUPPORTED_FID_TABLE \
36156 * The maximum number of entries supported by EEM. When configuring the host memory
36157 * the number of numbers of entries that can supported are -
36158 * 32k, 64k 128k, 256k, 512k, 1M, 2M, 4M, 8M, 32M, 64M, 128M entries.
36159 * Any value that are not these values, the FW will round down to the closest support
36160 * number of entries.
36162 uint32_t max_entries_supported;
36163 /* The entry size in bytes of each entry in the EEM KEY0/KEY1 tables. */
36164 uint16_t key_entry_size;
36165 /* The entry size in bytes of each entry in the EEM RECORD tables. */
36166 uint16_t record_entry_size;
36167 /* The entry size in bytes of each entry in the EEM EFC tables. */
36168 uint16_t efc_entry_size;
36169 /* The FID size in bytes of each entry in the EEM FID tables. */
36170 uint16_t fid_entry_size;
36171 uint8_t unused_1[7];
36173 * This field is used in Output records to indicate that the output
36174 * is completely written to RAM. This field should be read as '1'
36175 * to indicate that the output has been completely written.
36176 * When writing a command completion or response to an internal processor,
36177 * the order of writes has to be such that this field is written last.
36182 /********************
36183 * hwrm_cfa_eem_cfg *
36184 ********************/
36187 /* hwrm_cfa_eem_cfg_input (size:384b/48B) */
36188 struct hwrm_cfa_eem_cfg_input {
36189 /* The HWRM command request type. */
36192 * The completion ring to send the completion event on. This should
36193 * be the NQ ID returned from the `nq_alloc` HWRM command.
36195 uint16_t cmpl_ring;
36197 * The sequence ID is used by the driver for tracking multiple
36198 * commands. This ID is treated as opaque data by the firmware and
36199 * the value is returned in the `hwrm_resp_hdr` upon completion.
36203 * The target ID of the command:
36204 * * 0x0-0xFFF8 - The function ID
36205 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
36206 * * 0xFFFD - Reserved for user-space HWRM interface
36209 uint16_t target_id;
36211 * A physical address pointer pointing to a host buffer that the
36212 * command's response data will be written. This can be either a host
36213 * physical address (HPA) or a guest physical address (GPA) and must
36214 * point to a physically contiguous block of memory.
36216 uint64_t resp_addr;
36219 * When set to 1, indicates the configuration will apply to TX flows
36220 * which are to be offloaded.
36221 * Note if this bit is set then the path_rx bit can't be set.
36223 #define HWRM_CFA_EEM_CFG_INPUT_FLAGS_PATH_TX \
36226 * When set to 1, indicates the configuration will apply to RX flows
36227 * which are to be offloaded.
36228 * Note if this bit is set then the path_tx bit can't be set.
36230 #define HWRM_CFA_EEM_CFG_INPUT_FLAGS_PATH_RX \
36232 /* When set to 1, all offloaded flows will be sent to EEM. */
36233 #define HWRM_CFA_EEM_CFG_INPUT_FLAGS_PREFERRED_OFFLOAD \
36235 /* When set to 1, secondary, 0 means primary. */
36236 #define HWRM_CFA_EEM_CFG_INPUT_FLAGS_SECONDARY_PF \
36239 * Group_id which used by Firmware to identify memory pools belonging
36240 * to certain group.
36245 * Configured EEM with the given number of entries. All the EEM tables KEY0, KEY1,
36246 * RECORD, EFC all have the same number of entries and all tables will be configured
36247 * using this value. Current minimum value is 32k. Current maximum value is 128M.
36249 uint32_t num_entries;
36251 /* Configured EEM with the given context if for KEY0 table. */
36252 uint16_t key0_ctx_id;
36253 /* Configured EEM with the given context if for KEY1 table. */
36254 uint16_t key1_ctx_id;
36255 /* Configured EEM with the given context if for RECORD table. */
36256 uint16_t record_ctx_id;
36257 /* Configured EEM with the given context if for EFC table. */
36258 uint16_t efc_ctx_id;
36259 /* Configured EEM with the given context if for EFC table. */
36260 uint16_t fid_ctx_id;
36265 /* hwrm_cfa_eem_cfg_output (size:128b/16B) */
36266 struct hwrm_cfa_eem_cfg_output {
36267 /* The specific error status for the command. */
36268 uint16_t error_code;
36269 /* The HWRM command request type. */
36271 /* The sequence ID from the original command. */
36273 /* The length of the response data in number of bytes. */
36275 uint8_t unused_0[7];
36277 * This field is used in Output records to indicate that the output
36278 * is completely written to RAM. This field should be read as '1'
36279 * to indicate that the output has been completely written.
36280 * When writing a command completion or response to an internal processor,
36281 * the order of writes has to be such that this field is written last.
36286 /*********************
36287 * hwrm_cfa_eem_qcfg *
36288 *********************/
36291 /* hwrm_cfa_eem_qcfg_input (size:192b/24B) */
36292 struct hwrm_cfa_eem_qcfg_input {
36293 /* The HWRM command request type. */
36296 * The completion ring to send the completion event on. This should
36297 * be the NQ ID returned from the `nq_alloc` HWRM command.
36299 uint16_t cmpl_ring;
36301 * The sequence ID is used by the driver for tracking multiple
36302 * commands. This ID is treated as opaque data by the firmware and
36303 * the value is returned in the `hwrm_resp_hdr` upon completion.
36307 * The target ID of the command:
36308 * * 0x0-0xFFF8 - The function ID
36309 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
36310 * * 0xFFFD - Reserved for user-space HWRM interface
36313 uint16_t target_id;
36315 * A physical address pointer pointing to a host buffer that the
36316 * command's response data will be written. This can be either a host
36317 * physical address (HPA) or a guest physical address (GPA) and must
36318 * point to a physically contiguous block of memory.
36320 uint64_t resp_addr;
36322 /* When set to 1, indicates the configuration is the TX flow. */
36323 #define HWRM_CFA_EEM_QCFG_INPUT_FLAGS_PATH_TX UINT32_C(0x1)
36324 /* When set to 1, indicates the configuration is the RX flow. */
36325 #define HWRM_CFA_EEM_QCFG_INPUT_FLAGS_PATH_RX UINT32_C(0x2)
36329 /* hwrm_cfa_eem_qcfg_output (size:256b/32B) */
36330 struct hwrm_cfa_eem_qcfg_output {
36331 /* The specific error status for the command. */
36332 uint16_t error_code;
36333 /* The HWRM command request type. */
36335 /* The sequence ID from the original command. */
36337 /* The length of the response data in number of bytes. */
36340 /* When set to 1, indicates the configuration is the TX flow. */
36341 #define HWRM_CFA_EEM_QCFG_OUTPUT_FLAGS_PATH_TX \
36343 /* When set to 1, indicates the configuration is the RX flow. */
36344 #define HWRM_CFA_EEM_QCFG_OUTPUT_FLAGS_PATH_RX \
36346 /* When set to 1, all offloaded flows will be sent to EEM. */
36347 #define HWRM_CFA_EEM_QCFG_OUTPUT_FLAGS_PREFERRED_OFFLOAD \
36349 /* The number of entries the FW has configured for EEM. */
36350 uint32_t num_entries;
36351 /* Configured EEM with the given context if for KEY0 table. */
36352 uint16_t key0_ctx_id;
36353 /* Configured EEM with the given context if for KEY1 table. */
36354 uint16_t key1_ctx_id;
36355 /* Configured EEM with the given context if for RECORD table. */
36356 uint16_t record_ctx_id;
36357 /* Configured EEM with the given context if for EFC table. */
36358 uint16_t efc_ctx_id;
36359 /* Configured EEM with the given context if for EFC table. */
36360 uint16_t fid_ctx_id;
36361 uint8_t unused_2[5];
36363 * This field is used in Output records to indicate that the output
36364 * is completely written to RAM. This field should be read as '1'
36365 * to indicate that the output has been completely written.
36366 * When writing a command completion or response to an internal processor,
36367 * the order of writes has to be such that this field is written last.
36372 /*******************
36373 * hwrm_cfa_eem_op *
36374 *******************/
36377 /* hwrm_cfa_eem_op_input (size:192b/24B) */
36378 struct hwrm_cfa_eem_op_input {
36379 /* The HWRM command request type. */
36382 * The completion ring to send the completion event on. This should
36383 * be the NQ ID returned from the `nq_alloc` HWRM command.
36385 uint16_t cmpl_ring;
36387 * The sequence ID is used by the driver for tracking multiple
36388 * commands. This ID is treated as opaque data by the firmware and
36389 * the value is returned in the `hwrm_resp_hdr` upon completion.
36393 * The target ID of the command:
36394 * * 0x0-0xFFF8 - The function ID
36395 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
36396 * * 0xFFFD - Reserved for user-space HWRM interface
36399 uint16_t target_id;
36401 * A physical address pointer pointing to a host buffer that the
36402 * command's response data will be written. This can be either a host
36403 * physical address (HPA) or a guest physical address (GPA) and must
36404 * point to a physically contiguous block of memory.
36406 uint64_t resp_addr;
36409 * When set to 1, indicates the host memory which is passed will be
36410 * used for the TX flow offload function specified in fid.
36411 * Note if this bit is set then the path_rx bit can't be set.
36413 #define HWRM_CFA_EEM_OP_INPUT_FLAGS_PATH_TX UINT32_C(0x1)
36415 * When set to 1, indicates the host memory which is passed will be
36416 * used for the RX flow offload function specified in fid.
36417 * Note if this bit is set then the path_tx bit can't be set.
36419 #define HWRM_CFA_EEM_OP_INPUT_FLAGS_PATH_RX UINT32_C(0x2)
36421 /* The number of EEM key table entries to be configured. */
36423 /* This value is reserved and should not be used. */
36424 #define HWRM_CFA_EEM_OP_INPUT_OP_RESERVED UINT32_C(0x0)
36426 * To properly stop EEM and ensure there are no DMA's, the caller
36427 * must disable EEM for the given PF, using this call. This will
36428 * safely disable EEM and ensure that all DMA'ed to the
36429 * keys/records/efc have been completed.
36431 #define HWRM_CFA_EEM_OP_INPUT_OP_EEM_DISABLE UINT32_C(0x1)
36433 * Once the EEM host memory has been configured, EEM options have
36434 * been configured. Then the caller should enable EEM for the given
36435 * PF. Note once this call has been made, then the EEM mechanism
36436 * will be active and DMA's will occur as packets are processed.
36438 #define HWRM_CFA_EEM_OP_INPUT_OP_EEM_ENABLE UINT32_C(0x2)
36440 * Clear EEM settings for the given PF so that the register values
36441 * are reset back to there initial state.
36443 #define HWRM_CFA_EEM_OP_INPUT_OP_EEM_CLEANUP UINT32_C(0x3)
36444 #define HWRM_CFA_EEM_OP_INPUT_OP_LAST \
36445 HWRM_CFA_EEM_OP_INPUT_OP_EEM_CLEANUP
36448 /* hwrm_cfa_eem_op_output (size:128b/16B) */
36449 struct hwrm_cfa_eem_op_output {
36450 /* The specific error status for the command. */
36451 uint16_t error_code;
36452 /* The HWRM command request type. */
36454 /* The sequence ID from the original command. */
36456 /* The length of the response data in number of bytes. */
36458 uint8_t unused_0[7];
36460 * This field is used in Output records to indicate that the output
36461 * is completely written to RAM. This field should be read as '1'
36462 * to indicate that the output has been completely written.
36463 * When writing a command completion or response to an internal processor,
36464 * the order of writes has to be such that this field is written last.
36469 /********************************
36470 * hwrm_cfa_adv_flow_mgnt_qcaps *
36471 ********************************/
36474 /* hwrm_cfa_adv_flow_mgnt_qcaps_input (size:256b/32B) */
36475 struct hwrm_cfa_adv_flow_mgnt_qcaps_input {
36476 /* The HWRM command request type. */
36479 * The completion ring to send the completion event on. This should
36480 * be the NQ ID returned from the `nq_alloc` HWRM command.
36482 uint16_t cmpl_ring;
36484 * The sequence ID is used by the driver for tracking multiple
36485 * commands. This ID is treated as opaque data by the firmware and
36486 * the value is returned in the `hwrm_resp_hdr` upon completion.
36490 * The target ID of the command:
36491 * * 0x0-0xFFF8 - The function ID
36492 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
36493 * * 0xFFFD - Reserved for user-space HWRM interface
36496 uint16_t target_id;
36498 * A physical address pointer pointing to a host buffer that the
36499 * command's response data will be written. This can be either a host
36500 * physical address (HPA) or a guest physical address (GPA) and must
36501 * point to a physically contiguous block of memory.
36503 uint64_t resp_addr;
36504 uint32_t unused_0[4];
36507 /* hwrm_cfa_adv_flow_mgnt_qcaps_output (size:128b/16B) */
36508 struct hwrm_cfa_adv_flow_mgnt_qcaps_output {
36509 /* The specific error status for the command. */
36510 uint16_t error_code;
36511 /* The HWRM command request type. */
36513 /* The sequence ID from the original command. */
36515 /* The length of the response data in number of bytes. */
36519 * Value of 1 to indicate firmware support 16-bit flow handle.
36520 * Value of 0 to indicate firmware not support 16-bit flow handle.
36522 #define HWRM_CFA_ADV_FLOW_MGNT_QCAPS_OUTPUT_FLAGS_FLOW_HND_16BIT_SUPPORTED \
36525 * Value of 1 to indicate firmware support 64-bit flow handle.
36526 * Value of 0 to indicate firmware not support 64-bit flow handle.
36528 #define HWRM_CFA_ADV_FLOW_MGNT_QCAPS_OUTPUT_FLAGS_FLOW_HND_64BIT_SUPPORTED \
36531 * Value of 1 to indicate firmware support flow batch delete operation through
36532 * HWRM_CFA_FLOW_FLUSH command.
36533 * Value of 0 to indicate that the firmware does not support flow batch delete
36536 #define HWRM_CFA_ADV_FLOW_MGNT_QCAPS_OUTPUT_FLAGS_FLOW_BATCH_DELETE_SUPPORTED \
36539 * Value of 1 to indicate that the firmware support flow reset all operation through
36540 * HWRM_CFA_FLOW_FLUSH command.
36541 * Value of 0 indicates firmware does not support flow reset all operation.
36543 #define HWRM_CFA_ADV_FLOW_MGNT_QCAPS_OUTPUT_FLAGS_FLOW_RESET_ALL_SUPPORTED \
36546 * Value of 1 to indicate that firmware supports use of FID as dest_id in
36547 * HWRM_CFA_NTUPLE_ALLOC/CFG commands.
36548 * Value of 0 indicates firmware does not support use of FID as dest_id.
36550 #define HWRM_CFA_ADV_FLOW_MGNT_QCAPS_OUTPUT_FLAGS_NTUPLE_FLOW_DEST_FUNC_SUPPORTED \
36553 * Value of 1 to indicate that firmware supports TX EEM flows.
36554 * Value of 0 indicates firmware does not support TX EEM flows.
36556 #define HWRM_CFA_ADV_FLOW_MGNT_QCAPS_OUTPUT_FLAGS_TX_EEM_FLOW_SUPPORTED \
36559 * Value of 1 to indicate that firmware supports RX EEM flows.
36560 * Value of 0 indicates firmware does not support RX EEM flows.
36562 #define HWRM_CFA_ADV_FLOW_MGNT_QCAPS_OUTPUT_FLAGS_RX_EEM_FLOW_SUPPORTED \
36565 * Value of 1 to indicate that firmware supports the dynamic allocation of an
36566 * on-chip flow counter which can be used for EEM flows.
36567 * Value of 0 indicates firmware does not support the dynamic allocation of an
36568 * on-chip flow counter.
36570 #define HWRM_CFA_ADV_FLOW_MGNT_QCAPS_OUTPUT_FLAGS_FLOW_COUNTER_ALLOC_SUPPORTED \
36573 * Value of 1 to indicate that firmware supports setting of
36574 * rfs_ring_tbl_idx in HWRM_CFA_NTUPLE_ALLOC command.
36575 * Value of 0 indicates firmware does not support rfs_ring_tbl_idx.
36577 #define HWRM_CFA_ADV_FLOW_MGNT_QCAPS_OUTPUT_FLAGS_RFS_RING_TBL_IDX_SUPPORTED \
36580 * Value of 1 to indicate that firmware supports untagged matching
36581 * criteria on HWRM_CFA_L2_FILTER_ALLOC command. Value of 0
36582 * indicates firmware does not support untagged matching.
36584 #define HWRM_CFA_ADV_FLOW_MGNT_QCAPS_OUTPUT_FLAGS_UNTAGGED_VLAN_SUPPORTED \
36587 * Value of 1 to indicate that firmware supports XDP filter. Value
36588 * of 0 indicates firmware does not support XDP filter.
36590 #define HWRM_CFA_ADV_FLOW_MGNT_QCAPS_OUTPUT_FLAGS_XDP_SUPPORTED \
36593 * Value of 1 to indicate that the firmware support L2 header source
36594 * fields matching criteria on HWRM_CFA_L2_FILTER_ALLOC command.
36595 * Value of 0 indicates firmware does not support L2 header source
36598 #define HWRM_CFA_ADV_FLOW_MGNT_QCAPS_OUTPUT_FLAGS_L2_HEADER_SOURCE_FIELDS_SUPPORTED \
36601 * If set to 1, firmware is capable of supporting ARP ethertype as
36602 * matching criteria for HWRM_CFA_NTUPLE_FILTER_ALLOC command on the
36603 * RX direction. By default, this flag should be 0 for older version
36606 #define HWRM_CFA_ADV_FLOW_MGNT_QCAPS_OUTPUT_FLAGS_NTUPLE_FLOW_RX_ARP_SUPPORTED \
36609 * Value of 1 to indicate that firmware supports setting of
36610 * rfs_ring_tbl_idx in dst_id field of the HWRM_CFA_NTUPLE_ALLOC
36611 * command. Value of 0 indicates firmware does not support
36612 * rfs_ring_tbl_idx in dst_id field.
36614 #define HWRM_CFA_ADV_FLOW_MGNT_QCAPS_OUTPUT_FLAGS_RFS_RING_TBL_IDX_V2_SUPPORTED \
36617 * If set to 1, firmware is capable of supporting IPv4/IPv6 as
36618 * ethertype in HWRM_CFA_NTUPLE_FILTER_ALLOC command on the RX
36619 * direction. By default, this flag should be 0 for older version
36622 #define HWRM_CFA_ADV_FLOW_MGNT_QCAPS_OUTPUT_FLAGS_NTUPLE_FLOW_RX_ETHERTYPE_IP_SUPPORTED \
36624 uint8_t unused_0[3];
36626 * This field is used in Output records to indicate that the output
36627 * is completely written to RAM. This field should be read as '1'
36628 * to indicate that the output has been completely written.
36629 * When writing a command completion or response to an internal processor,
36630 * the order of writes has to be such that this field is written last.
36635 /******************
36637 ******************/
36640 /* hwrm_cfa_tflib_input (size:1024b/128B) */
36641 struct hwrm_cfa_tflib_input {
36642 /* The HWRM command request type. */
36645 * The completion ring to send the completion event on. This should
36646 * be the NQ ID returned from the `nq_alloc` HWRM command.
36648 uint16_t cmpl_ring;
36650 * The sequence ID is used by the driver for tracking multiple
36651 * commands. This ID is treated as opaque data by the firmware and
36652 * the value is returned in the `hwrm_resp_hdr` upon completion.
36656 * The target ID of the command:
36657 * * 0x0-0xFFF8 - The function ID
36658 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
36659 * * 0xFFFD - Reserved for user-space HWRM interface
36662 uint16_t target_id;
36664 * A physical address pointer pointing to a host buffer that the
36665 * command's response data will be written. This can be either a host
36666 * physical address (HPA) or a guest physical address (GPA) and must
36667 * point to a physically contiguous block of memory.
36669 uint64_t resp_addr;
36670 /* TFLIB message type. */
36672 /* TFLIB message subtype. */
36673 uint16_t tf_subtype;
36675 uint8_t unused0[4];
36676 /* TFLIB request data. */
36677 uint32_t tf_req[26];
36680 /* hwrm_cfa_tflib_output (size:5632b/704B) */
36681 struct hwrm_cfa_tflib_output {
36682 /* The specific error status for the command. */
36683 uint16_t error_code;
36684 /* The HWRM command request type. */
36686 /* The sequence ID from the original command. */
36688 /* The length of the response data in number of bytes. */
36690 /* TFLIB message type. */
36692 /* TFLIB message subtype. */
36693 uint16_t tf_subtype;
36694 /* TFLIB response code */
36695 uint32_t tf_resp_code;
36696 /* TFLIB response data. */
36697 uint32_t tf_resp[170];
36699 uint8_t unused1[7];
36701 * This field is used in Output records to indicate that the output
36702 * is completely written to RAM. This field should be read as '1'
36703 * to indicate that the output has been completely written.
36704 * When writing a command completion or response to an internal processor,
36705 * the order of writes has to be such that this field is written last.
36715 /* hwrm_tf_input (size:1024b/128B) */
36716 struct hwrm_tf_input {
36717 /* The HWRM command request type. */
36720 * The completion ring to send the completion event on. This should
36721 * be the NQ ID returned from the `nq_alloc` HWRM command.
36723 uint16_t cmpl_ring;
36725 * The sequence ID is used by the driver for tracking multiple
36726 * commands. This ID is treated as opaque data by the firmware and
36727 * the value is returned in the `hwrm_resp_hdr` upon completion.
36731 * The target ID of the command:
36732 * * 0x0-0xFFF8 - The function ID
36733 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
36734 * * 0xFFFD - Reserved for user-space HWRM interface
36737 uint16_t target_id;
36739 * A physical address pointer pointing to a host buffer that the
36740 * command's response data will be written. This can be either a host
36741 * physical address (HPA) or a guest physical address (GPA) and must
36742 * point to a physically contiguous block of memory.
36744 uint64_t resp_addr;
36745 /* TF message type. */
36747 /* TF message subtype. */
36750 uint8_t unused0[4];
36751 /* TF request data. */
36755 /* hwrm_tf_output (size:5632b/704B) */
36756 struct hwrm_tf_output {
36757 /* The specific error status for the command. */
36758 uint16_t error_code;
36759 /* The HWRM command request type. */
36761 /* The sequence ID from the original command. */
36763 /* The length of the response data in number of bytes. */
36765 /* TF message type. */
36767 /* TF message subtype. */
36769 /* TF response code */
36770 uint32_t resp_code;
36771 /* TF response data. */
36772 uint32_t resp[170];
36774 uint8_t unused1[7];
36776 * This field is used in Output records to indicate that the
36777 * output is completely written to RAM. This field should be
36778 * read as '1' to indicate that the output has been
36779 * completely written. When writing a command completion or
36780 * response to an internal processor, the order of writes has
36781 * to be such that this field is written last.
36786 /***********************
36787 * hwrm_tf_version_get *
36788 ***********************/
36791 /* hwrm_tf_version_get_input (size:128b/16B) */
36792 struct hwrm_tf_version_get_input {
36793 /* The HWRM command request type. */
36796 * The completion ring to send the completion event on. This should
36797 * be the NQ ID returned from the `nq_alloc` HWRM command.
36799 uint16_t cmpl_ring;
36801 * The sequence ID is used by the driver for tracking multiple
36802 * commands. This ID is treated as opaque data by the firmware and
36803 * the value is returned in the `hwrm_resp_hdr` upon completion.
36807 * The target ID of the command:
36808 * * 0x0-0xFFF8 - The function ID
36809 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
36810 * * 0xFFFD - Reserved for user-space HWRM interface
36813 uint16_t target_id;
36815 * A physical address pointer pointing to a host buffer that the
36816 * command's response data will be written. This can be either a host
36817 * physical address (HPA) or a guest physical address (GPA) and must
36818 * point to a physically contiguous block of memory.
36820 uint64_t resp_addr;
36823 /* hwrm_tf_version_get_output (size:128b/16B) */
36824 struct hwrm_tf_version_get_output {
36825 /* The specific error status for the command. */
36826 uint16_t error_code;
36827 /* The HWRM command request type. */
36829 /* The sequence ID from the original command. */
36831 /* The length of the response data in number of bytes. */
36833 /* Version Major number. */
36835 /* Version Minor number. */
36837 /* Version Update number. */
36840 uint8_t unused0[4];
36842 * This field is used in Output records to indicate that the output
36843 * is completely written to RAM. This field should be read as '1'
36844 * to indicate that the output has been completely written.
36845 * When writing a command completion or response to an internal
36846 * processor, the order of writes has to be such that this field is
36852 /************************
36853 * hwrm_tf_session_open *
36854 ************************/
36857 /* hwrm_tf_session_open_input (size:640b/80B) */
36858 struct hwrm_tf_session_open_input {
36859 /* The HWRM command request type. */
36862 * The completion ring to send the completion event on. This should
36863 * be the NQ ID returned from the `nq_alloc` HWRM command.
36865 uint16_t cmpl_ring;
36867 * The sequence ID is used by the driver for tracking multiple
36868 * commands. This ID is treated as opaque data by the firmware and
36869 * the value is returned in the `hwrm_resp_hdr` upon completion.
36873 * The target ID of the command:
36874 * * 0x0-0xFFF8 - The function ID
36875 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
36876 * * 0xFFFD - Reserved for user-space HWRM interface
36879 uint16_t target_id;
36881 * A physical address pointer pointing to a host buffer that the
36882 * command's response data will be written. This can be either a host
36883 * physical address (HPA) or a guest physical address (GPA) and must
36884 * point to a physically contiguous block of memory.
36886 uint64_t resp_addr;
36887 /* Name of the session. */
36888 uint8_t session_name[64];
36891 /* hwrm_tf_session_open_output (size:192b/24B) */
36892 struct hwrm_tf_session_open_output {
36893 /* The specific error status for the command. */
36894 uint16_t error_code;
36895 /* The HWRM command request type. */
36897 /* The sequence ID from the original command. */
36899 /* The length of the response data in number of bytes. */
36902 * Unique session identifier for the session created by the
36905 uint32_t fw_session_id;
36907 * Unique session client identifier for the first client on
36908 * the newly created session.
36910 uint32_t fw_session_client_id;
36914 uint8_t unused1[3];
36916 * This field is used in Output records to indicate that the output
36917 * is completely written to RAM. This field should be read as '1'
36918 * to indicate that the output has been completely written.
36919 * When writing a command completion or response to an internal
36920 * processor, the order of writes has to be such that this field is
36926 /**************************
36927 * hwrm_tf_session_attach *
36928 **************************/
36931 /* hwrm_tf_session_attach_input (size:704b/88B) */
36932 struct hwrm_tf_session_attach_input {
36933 /* The HWRM command request type. */
36936 * The completion ring to send the completion event on. This should
36937 * be the NQ ID returned from the `nq_alloc` HWRM command.
36939 uint16_t cmpl_ring;
36941 * The sequence ID is used by the driver for tracking multiple
36942 * commands. This ID is treated as opaque data by the firmware and
36943 * the value is returned in the `hwrm_resp_hdr` upon completion.
36947 * The target ID of the command:
36948 * * 0x0-0xFFF8 - The function ID
36949 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
36950 * * 0xFFFD - Reserved for user-space HWRM interface
36953 uint16_t target_id;
36955 * A physical address pointer pointing to a host buffer that the
36956 * command's response data will be written. This can be either a host
36957 * physical address (HPA) or a guest physical address (GPA) and must
36958 * point to a physically contiguous block of memory.
36960 uint64_t resp_addr;
36962 * Unique session identifier for the session that the attach
36963 * request want to attach to. This value originates from the
36964 * shared session memory that the attach request opened by
36965 * way of the 'attach name' that was passed in to the core
36967 * The fw_session_id of the attach session includes PCIe bus
36968 * info to distinguish the PF and session info to identify
36969 * the associated TruFlow session.
36971 uint32_t attach_fw_session_id;
36974 /* Name of the session it self. */
36975 uint8_t session_name[64];
36978 /* hwrm_tf_session_attach_output (size:128b/16B) */
36979 struct hwrm_tf_session_attach_output {
36980 /* The specific error status for the command. */
36981 uint16_t error_code;
36982 /* The HWRM command request type. */
36984 /* The sequence ID from the original command. */
36986 /* The length of the response data in number of bytes. */
36989 * Unique session identifier for the session created by the
36990 * firmware. It includes PCIe bus info to distinguish the PF
36991 * and session info to identify the associated TruFlow
36992 * session. This fw_session_id is unique to the attach
36995 uint32_t fw_session_id;
36997 uint8_t unused0[3];
36999 * This field is used in Output records to indicate that the output
37000 * is completely written to RAM. This field should be read as '1'
37001 * to indicate that the output has been completely written.
37002 * When writing a command completion or response to an internal
37003 * processor, the order of writes has to be such that this field is
37009 /****************************
37010 * hwrm_tf_session_register *
37011 ****************************/
37014 /* hwrm_tf_session_register_input (size:704b/88B) */
37015 struct hwrm_tf_session_register_input {
37016 /* The HWRM command request type. */
37019 * The completion ring to send the completion event on. This should
37020 * be the NQ ID returned from the `nq_alloc` HWRM command.
37022 uint16_t cmpl_ring;
37024 * The sequence ID is used by the driver for tracking multiple
37025 * commands. This ID is treated as opaque data by the firmware and
37026 * the value is returned in the `hwrm_resp_hdr` upon completion.
37030 * The target ID of the command:
37031 * * 0x0-0xFFF8 - The function ID
37032 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
37033 * * 0xFFFD - Reserved for user-space HWRM interface
37036 uint16_t target_id;
37038 * A physical address pointer pointing to a host buffer that the
37039 * command's response data will be written. This can be either a host
37040 * physical address (HPA) or a guest physical address (GPA) and must
37041 * point to a physically contiguous block of memory.
37043 uint64_t resp_addr;
37045 * Unique session identifier for the session that the
37046 * register request want to create a new client on. This
37047 * value originates from the first open request.
37048 * The fw_session_id of the attach session includes PCIe bus
37049 * info to distinguish the PF and session info to identify
37050 * the associated TruFlow session.
37052 uint32_t fw_session_id;
37055 /* Name of the session client. */
37056 uint8_t session_client_name[64];
37059 /* hwrm_tf_session_register_output (size:128b/16B) */
37060 struct hwrm_tf_session_register_output {
37061 /* The specific error status for the command. */
37062 uint16_t error_code;
37063 /* The HWRM command request type. */
37065 /* The sequence ID from the original command. */
37067 /* The length of the response data in number of bytes. */
37070 * Unique session client identifier for the session created
37071 * by the firmware. It includes the session the client it
37072 * attached to and session client info.
37074 uint32_t fw_session_client_id;
37076 uint8_t unused0[3];
37078 * This field is used in Output records to indicate that the output
37079 * is completely written to RAM. This field should be read as '1'
37080 * to indicate that the output has been completely written.
37081 * When writing a command completion or response to an internal
37082 * processor, the order of writes has to be such that this field is
37088 /******************************
37089 * hwrm_tf_session_unregister *
37090 ******************************/
37093 /* hwrm_tf_session_unregister_input (size:192b/24B) */
37094 struct hwrm_tf_session_unregister_input {
37095 /* The HWRM command request type. */
37098 * The completion ring to send the completion event on. This should
37099 * be the NQ ID returned from the `nq_alloc` HWRM command.
37101 uint16_t cmpl_ring;
37103 * The sequence ID is used by the driver for tracking multiple
37104 * commands. This ID is treated as opaque data by the firmware and
37105 * the value is returned in the `hwrm_resp_hdr` upon completion.
37109 * The target ID of the command:
37110 * * 0x0-0xFFF8 - The function ID
37111 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
37112 * * 0xFFFD - Reserved for user-space HWRM interface
37115 uint16_t target_id;
37117 * A physical address pointer pointing to a host buffer that the
37118 * command's response data will be written. This can be either a host
37119 * physical address (HPA) or a guest physical address (GPA) and must
37120 * point to a physically contiguous block of memory.
37122 uint64_t resp_addr;
37124 * Unique session identifier for the session that the
37125 * unregister request want to close a session client on.
37127 uint32_t fw_session_id;
37129 * Unique session client identifier for the session that the
37130 * unregister request want to close.
37132 uint32_t fw_session_client_id;
37135 /* hwrm_tf_session_unregister_output (size:128b/16B) */
37136 struct hwrm_tf_session_unregister_output {
37137 /* The specific error status for the command. */
37138 uint16_t error_code;
37139 /* The HWRM command request type. */
37141 /* The sequence ID from the original command. */
37143 /* The length of the response data in number of bytes. */
37146 uint8_t unused0[7];
37148 * This field is used in Output records to indicate that the output
37149 * is completely written to RAM. This field should be read as '1'
37150 * to indicate that the output has been completely written.
37151 * When writing a command completion or response to an internal
37152 * processor, the order of writes has to be such that this field is
37158 /*************************
37159 * hwrm_tf_session_close *
37160 *************************/
37163 /* hwrm_tf_session_close_input (size:192b/24B) */
37164 struct hwrm_tf_session_close_input {
37165 /* The HWRM command request type. */
37168 * The completion ring to send the completion event on. This should
37169 * be the NQ ID returned from the `nq_alloc` HWRM command.
37171 uint16_t cmpl_ring;
37173 * The sequence ID is used by the driver for tracking multiple
37174 * commands. This ID is treated as opaque data by the firmware and
37175 * the value is returned in the `hwrm_resp_hdr` upon completion.
37179 * The target ID of the command:
37180 * * 0x0-0xFFF8 - The function ID
37181 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
37182 * * 0xFFFD - Reserved for user-space HWRM interface
37185 uint16_t target_id;
37187 * A physical address pointer pointing to a host buffer that the
37188 * command's response data will be written. This can be either a host
37189 * physical address (HPA) or a guest physical address (GPA) and must
37190 * point to a physically contiguous block of memory.
37192 uint64_t resp_addr;
37193 /* Firmware session id returned when HWRM_TF_SESSION_OPEN is sent. */
37194 uint32_t fw_session_id;
37196 uint8_t unused0[4];
37199 /* hwrm_tf_session_close_output (size:128b/16B) */
37200 struct hwrm_tf_session_close_output {
37201 /* The specific error status for the command. */
37202 uint16_t error_code;
37203 /* The HWRM command request type. */
37205 /* The sequence ID from the original command. */
37207 /* The length of the response data in number of bytes. */
37210 uint8_t unused0[7];
37212 * This field is used in Output records to indicate that the output
37213 * is completely written to RAM. This field should be read as '1'
37214 * to indicate that the output has been completely written.
37215 * When writing a command completion or response to an internal
37216 * processor, the order of writes has to be such that this field
37222 /************************
37223 * hwrm_tf_session_qcfg *
37224 ************************/
37227 /* hwrm_tf_session_qcfg_input (size:192b/24B) */
37228 struct hwrm_tf_session_qcfg_input {
37229 /* The HWRM command request type. */
37232 * The completion ring to send the completion event on. This should
37233 * be the NQ ID returned from the `nq_alloc` HWRM command.
37235 uint16_t cmpl_ring;
37237 * The sequence ID is used by the driver for tracking multiple
37238 * commands. This ID is treated as opaque data by the firmware and
37239 * the value is returned in the `hwrm_resp_hdr` upon completion.
37243 * The target ID of the command:
37244 * * 0x0-0xFFF8 - The function ID
37245 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
37246 * * 0xFFFD - Reserved for user-space HWRM interface
37249 uint16_t target_id;
37251 * A physical address pointer pointing to a host buffer that the
37252 * command's response data will be written. This can be either a host
37253 * physical address (HPA) or a guest physical address (GPA) and must
37254 * point to a physically contiguous block of memory.
37256 uint64_t resp_addr;
37257 /* Firmware session id returned when HWRM_TF_SESSION_OPEN is sent. */
37258 uint32_t fw_session_id;
37260 uint8_t unused0[4];
37263 /* hwrm_tf_session_qcfg_output (size:128b/16B) */
37264 struct hwrm_tf_session_qcfg_output {
37265 /* The specific error status for the command. */
37266 uint16_t error_code;
37267 /* The HWRM command request type. */
37269 /* The sequence ID from the original command. */
37271 /* The length of the response data in number of bytes. */
37273 /* RX action control settings flags. */
37274 uint8_t rx_act_flags;
37276 * A value of 1 in this field indicates that Global Flow ID
37277 * reporting into cfa_code and cfa_metadata is enabled.
37279 #define HWRM_TF_SESSION_QCFG_OUTPUT_RX_ACT_FLAGS_ABCR_GFID_EN \
37282 * A value of 1 in this field indicates that both inner and outer
37283 * are stripped and inner tag is passed.
37286 #define HWRM_TF_SESSION_QCFG_OUTPUT_RX_ACT_FLAGS_ABCR_VTAG_DLT_BOTH \
37289 * A value of 1 in this field indicates that the re-use of
37290 * existing tunnel L2 header SMAC is enabled for
37291 * Non-tunnel L2, L2-L3 and IP-IP tunnel.
37293 #define HWRM_TF_SESSION_QCFG_OUTPUT_RX_ACT_FLAGS_TECT_SMAC_OVR_RUTNSL2 \
37295 /* TX Action control settings flags. */
37296 uint8_t tx_act_flags;
37298 #define HWRM_TF_SESSION_QCFG_OUTPUT_TX_ACT_FLAGS_ABCR_VEB_EN \
37301 * When set to 1 any GRE tunnels will include the
37302 * optional Key field.
37304 #define HWRM_TF_SESSION_QCFG_OUTPUT_TX_ACT_FLAGS_TECT_GRE_SET_K \
37307 * When set to 1, for GRE tunnels, the IPV6 Traffic Class (TC)
37308 * field of the outer header is inherited from the inner header
37309 * (if present) or the fixed value as taken from the encap
37312 #define HWRM_TF_SESSION_QCFG_OUTPUT_TX_ACT_FLAGS_TECT_IPV6_TC_IH \
37315 * When set to 1, for GRE tunnels, the IPV4 Type Of Service (TOS)
37316 * field of the outer header is inherited from the inner header
37317 * (if present) or the fixed value as taken from the encap record.
37319 #define HWRM_TF_SESSION_QCFG_OUTPUT_TX_ACT_FLAGS_TECT_IPV4_TOS_IH \
37322 uint8_t unused0[5];
37324 * This field is used in Output records to indicate that the output
37325 * is completely written to RAM. This field should be read as '1'
37326 * to indicate that the output has been completely written.
37327 * When writing a command completion or response to an internal
37328 * processor, the order of writes has to be such that this field
37334 /******************************
37335 * hwrm_tf_session_resc_qcaps *
37336 ******************************/
37339 /* hwrm_tf_session_resc_qcaps_input (size:256b/32B) */
37340 struct hwrm_tf_session_resc_qcaps_input {
37341 /* The HWRM command request type. */
37344 * The completion ring to send the completion event on. This should
37345 * be the NQ ID returned from the `nq_alloc` HWRM command.
37347 uint16_t cmpl_ring;
37349 * The sequence ID is used by the driver for tracking multiple
37350 * commands. This ID is treated as opaque data by the firmware and
37351 * the value is returned in the `hwrm_resp_hdr` upon completion.
37355 * The target ID of the command:
37356 * * 0x0-0xFFF8 - The function ID
37357 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
37358 * * 0xFFFD - Reserved for user-space HWRM interface
37361 uint16_t target_id;
37363 * A physical address pointer pointing to a host buffer that the
37364 * command's response data will be written. This can be either a host
37365 * physical address (HPA) or a guest physical address (GPA) and must
37366 * point to a physically contiguous block of memory.
37368 uint64_t resp_addr;
37369 /* Firmware session id returned when HWRM_TF_SESSION_OPEN is sent. */
37370 uint32_t fw_session_id;
37371 /* Control flags. */
37373 /* Indicates the flow direction. */
37374 #define HWRM_TF_SESSION_RESC_QCAPS_INPUT_FLAGS_DIR UINT32_C(0x1)
37375 /* If this bit set to 0, then it indicates rx flow. */
37376 #define HWRM_TF_SESSION_RESC_QCAPS_INPUT_FLAGS_DIR_RX UINT32_C(0x0)
37377 /* If this bit is set to 1, then it indicates that tx flow. */
37378 #define HWRM_TF_SESSION_RESC_QCAPS_INPUT_FLAGS_DIR_TX UINT32_C(0x1)
37379 #define HWRM_TF_SESSION_RESC_QCAPS_INPUT_FLAGS_DIR_LAST \
37380 HWRM_TF_SESSION_RESC_QCAPS_INPUT_FLAGS_DIR_TX
37382 * Defines the size of the provided qcaps_addr array
37383 * buffer. The size should be set to the Resource Manager
37384 * provided max number of qcaps entries which is device
37385 * specific. Resource Manager gets the max size from HCAPI
37388 uint16_t qcaps_size;
37390 * This is the DMA address for the qcaps output data array
37391 * buffer. Array is of tf_rm_resc_req_entry type and is
37394 uint64_t qcaps_addr;
37397 /* hwrm_tf_session_resc_qcaps_output (size:192b/24B) */
37398 struct hwrm_tf_session_resc_qcaps_output {
37399 /* The specific error status for the command. */
37400 uint16_t error_code;
37401 /* The HWRM command request type. */
37403 /* The sequence ID from the original command. */
37405 /* The length of the response data in number of bytes. */
37407 /* Control flags. */
37409 /* Session reservation strategy. */
37410 #define HWRM_TF_SESSION_RESC_QCAPS_OUTPUT_FLAGS_SESS_RESV_STRATEGY_MASK \
37412 #define HWRM_TF_SESSION_RESC_QCAPS_OUTPUT_FLAGS_SESS_RESV_STRATEGY_SFT \
37414 /* Static partitioning. */
37415 #define HWRM_TF_SESSION_RESC_QCAPS_OUTPUT_FLAGS_SESS_RESV_STRATEGY_STATIC \
37418 #define HWRM_TF_SESSION_RESC_QCAPS_OUTPUT_FLAGS_SESS_RESV_STRATEGY_1 \
37421 #define HWRM_TF_SESSION_RESC_QCAPS_OUTPUT_FLAGS_SESS_RESV_STRATEGY_2 \
37424 #define HWRM_TF_SESSION_RESC_QCAPS_OUTPUT_FLAGS_SESS_RESV_STRATEGY_3 \
37426 #define HWRM_TF_SESSION_RESC_QCAPS_OUTPUT_FLAGS_SESS_RESV_STRATEGY_LAST \
37427 HWRM_TF_SESSION_RESC_QCAPS_OUTPUT_FLAGS_SESS_RESV_STRATEGY_3
37429 * Size of the returned qcaps_addr data array buffer. The
37430 * value cannot exceed the size defined by the input msg,
37437 uint8_t unused1[7];
37439 * This field is used in Output records to indicate that the output
37440 * is completely written to RAM. This field should be read as '1'
37441 * to indicate that the output has been completely written.
37442 * When writing a command completion or response to an internal
37443 * processor, the order of writes has to be such that this field is
37449 /******************************
37450 * hwrm_tf_session_resc_alloc *
37451 ******************************/
37454 /* hwrm_tf_session_resc_alloc_input (size:320b/40B) */
37455 struct hwrm_tf_session_resc_alloc_input {
37456 /* The HWRM command request type. */
37459 * The completion ring to send the completion event on. This should
37460 * be the NQ ID returned from the `nq_alloc` HWRM command.
37462 uint16_t cmpl_ring;
37464 * The sequence ID is used by the driver for tracking multiple
37465 * commands. This ID is treated as opaque data by the firmware and
37466 * the value is returned in the `hwrm_resp_hdr` upon completion.
37470 * The target ID of the command:
37471 * * 0x0-0xFFF8 - The function ID
37472 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
37473 * * 0xFFFD - Reserved for user-space HWRM interface
37476 uint16_t target_id;
37478 * A physical address pointer pointing to a host buffer that the
37479 * command's response data will be written. This can be either a host
37480 * physical address (HPA) or a guest physical address (GPA) and must
37481 * point to a physically contiguous block of memory.
37483 uint64_t resp_addr;
37484 /* Firmware session id returned when HWRM_TF_SESSION_OPEN is sent. */
37485 uint32_t fw_session_id;
37486 /* Control flags. */
37488 /* Indicates the flow direction. */
37489 #define HWRM_TF_SESSION_RESC_ALLOC_INPUT_FLAGS_DIR UINT32_C(0x1)
37490 /* If this bit set to 0, then it indicates rx flow. */
37491 #define HWRM_TF_SESSION_RESC_ALLOC_INPUT_FLAGS_DIR_RX UINT32_C(0x0)
37492 /* If this bit is set to 1, then it indicates that tx flow. */
37493 #define HWRM_TF_SESSION_RESC_ALLOC_INPUT_FLAGS_DIR_TX UINT32_C(0x1)
37494 #define HWRM_TF_SESSION_RESC_ALLOC_INPUT_FLAGS_DIR_LAST \
37495 HWRM_TF_SESSION_RESC_ALLOC_INPUT_FLAGS_DIR_TX
37497 * Defines the array size of the provided req_addr and
37498 * resv_addr array buffers. Should be set to the number of
37503 * This is the DMA address for the request input data array
37504 * buffer. Array is of tf_rm_resc_req_entry type. Size of the
37505 * array buffer is provided by the 'req_size' field in this
37510 * This is the DMA address for the resc output data array
37511 * buffer. Array is of tf_rm_resc_entry type. Size of the array
37512 * buffer is provided by the 'req_size' field in this
37515 uint64_t resc_addr;
37518 /* hwrm_tf_session_resc_alloc_output (size:128b/16B) */
37519 struct hwrm_tf_session_resc_alloc_output {
37520 /* The specific error status for the command. */
37521 uint16_t error_code;
37522 /* The HWRM command request type. */
37524 /* The sequence ID from the original command. */
37526 /* The length of the response data in number of bytes. */
37529 * Size of the returned tf_rm_resc_entry data array. The value
37530 * cannot exceed the req_size defined by the input msg. The data
37531 * array is returned using the resv_addr specified DMA
37532 * address also provided by the input msg.
37536 uint8_t unused0[5];
37538 * This field is used in Output records to indicate that the output
37539 * is completely written to RAM. This field should be read as '1'
37540 * to indicate that the output has been completely written.
37541 * When writing a command completion or response to an internal
37542 * processor, the order of writes has to be such that this field is
37548 /*****************************
37549 * hwrm_tf_session_resc_free *
37550 *****************************/
37553 /* hwrm_tf_session_resc_free_input (size:256b/32B) */
37554 struct hwrm_tf_session_resc_free_input {
37555 /* The HWRM command request type. */
37558 * The completion ring to send the completion event on. This should
37559 * be the NQ ID returned from the `nq_alloc` HWRM command.
37561 uint16_t cmpl_ring;
37563 * The sequence ID is used by the driver for tracking multiple
37564 * commands. This ID is treated as opaque data by the firmware and
37565 * the value is returned in the `hwrm_resp_hdr` upon completion.
37569 * The target ID of the command:
37570 * * 0x0-0xFFF8 - The function ID
37571 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
37572 * * 0xFFFD - Reserved for user-space HWRM interface
37575 uint16_t target_id;
37577 * A physical address pointer pointing to a host buffer that the
37578 * command's response data will be written. This can be either a host
37579 * physical address (HPA) or a guest physical address (GPA) and must
37580 * point to a physically contiguous block of memory.
37582 uint64_t resp_addr;
37583 /* Firmware session id returned when HWRM_TF_SESSION_OPEN is sent. */
37584 uint32_t fw_session_id;
37585 /* Control flags. */
37587 /* Indicates the flow direction. */
37588 #define HWRM_TF_SESSION_RESC_FREE_INPUT_FLAGS_DIR UINT32_C(0x1)
37589 /* If this bit set to 0, then it indicates rx flow. */
37590 #define HWRM_TF_SESSION_RESC_FREE_INPUT_FLAGS_DIR_RX UINT32_C(0x0)
37591 /* If this bit is set to 1, then it indicates that tx flow. */
37592 #define HWRM_TF_SESSION_RESC_FREE_INPUT_FLAGS_DIR_TX UINT32_C(0x1)
37593 #define HWRM_TF_SESSION_RESC_FREE_INPUT_FLAGS_DIR_LAST \
37594 HWRM_TF_SESSION_RESC_FREE_INPUT_FLAGS_DIR_TX
37596 * Defines the size, in bytes, of the provided free_addr
37599 uint16_t free_size;
37601 * This is the DMA address for the free input data array
37602 * buffer. Array is of tf_rm_resc_entry type. Size of the
37603 * buffer is provided by the 'free_size' field of this
37606 uint64_t free_addr;
37609 /* hwrm_tf_session_resc_free_output (size:128b/16B) */
37610 struct hwrm_tf_session_resc_free_output {
37611 /* The specific error status for the command. */
37612 uint16_t error_code;
37613 /* The HWRM command request type. */
37615 /* The sequence ID from the original command. */
37617 /* The length of the response data in number of bytes. */
37620 uint8_t unused0[7];
37622 * This field is used in Output records to indicate that the output
37623 * is completely written to RAM. This field should be read as '1'
37624 * to indicate that the output has been completely written.
37625 * When writing a command completion or response to an internal
37626 * processor, the order of writes has to be such that this field is
37632 /******************************
37633 * hwrm_tf_session_resc_flush *
37634 ******************************/
37637 /* hwrm_tf_session_resc_flush_input (size:256b/32B) */
37638 struct hwrm_tf_session_resc_flush_input {
37639 /* The HWRM command request type. */
37642 * The completion ring to send the completion event on. This should
37643 * be the NQ ID returned from the `nq_alloc` HWRM command.
37645 uint16_t cmpl_ring;
37647 * The sequence ID is used by the driver for tracking multiple
37648 * commands. This ID is treated as opaque data by the firmware and
37649 * the value is returned in the `hwrm_resp_hdr` upon completion.
37653 * The target ID of the command:
37654 * * 0x0-0xFFF8 - The function ID
37655 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
37656 * * 0xFFFD - Reserved for user-space HWRM interface
37659 uint16_t target_id;
37661 * A physical address pointer pointing to a host buffer that the
37662 * command's response data will be written. This can be either a host
37663 * physical address (HPA) or a guest physical address (GPA) and must
37664 * point to a physically contiguous block of memory.
37666 uint64_t resp_addr;
37667 /* Firmware session id returned when HWRM_TF_SESSION_OPEN is sent. */
37668 uint32_t fw_session_id;
37669 /* Control flags. */
37671 /* Indicates the flow direction. */
37672 #define HWRM_TF_SESSION_RESC_FLUSH_INPUT_FLAGS_DIR UINT32_C(0x1)
37673 /* If this bit set to 0, then it indicates rx flow. */
37674 #define HWRM_TF_SESSION_RESC_FLUSH_INPUT_FLAGS_DIR_RX UINT32_C(0x0)
37675 /* If this bit is set to 1, then it indicates that tx flow. */
37676 #define HWRM_TF_SESSION_RESC_FLUSH_INPUT_FLAGS_DIR_TX UINT32_C(0x1)
37677 #define HWRM_TF_SESSION_RESC_FLUSH_INPUT_FLAGS_DIR_LAST \
37678 HWRM_TF_SESSION_RESC_FLUSH_INPUT_FLAGS_DIR_TX
37680 * Defines the size, in bytes, of the provided flush_addr
37683 uint16_t flush_size;
37685 * This is the DMA address for the flush input data array
37686 * buffer. Array of tf_rm_resc_entry type. Size of the
37687 * buffer is provided by the 'flush_size' field in this
37690 uint64_t flush_addr;
37693 /* hwrm_tf_session_resc_flush_output (size:128b/16B) */
37694 struct hwrm_tf_session_resc_flush_output {
37695 /* The specific error status for the command. */
37696 uint16_t error_code;
37697 /* The HWRM command request type. */
37699 /* The sequence ID from the original command. */
37701 /* The length of the response data in number of bytes. */
37704 uint8_t unused0[7];
37706 * This field is used in Output records to indicate that the output
37707 * is completely written to RAM. This field should be read as '1'
37708 * to indicate that the output has been completely written.
37709 * When writing a command completion or response to an internal
37710 * processor, the order of writes has to be such that this field is
37716 /* TruFlow RM capability of a resource. */
37717 /* tf_rm_resc_req_entry (size:64b/8B) */
37718 struct tf_rm_resc_req_entry {
37719 /* Type of the resource, defined globally in HCAPI RM. */
37721 /* Minimum value. */
37723 /* Maximum value. */
37727 /* TruFlow RM reservation information. */
37728 /* tf_rm_resc_entry (size:64b/8B) */
37729 struct tf_rm_resc_entry {
37730 /* Type of the resource, defined globally in HCAPI RM. */
37732 /* Start offset. */
37734 /* Number of resources. */
37738 /************************
37739 * hwrm_tf_tbl_type_get *
37740 ************************/
37743 /* hwrm_tf_tbl_type_get_input (size:256b/32B) */
37744 struct hwrm_tf_tbl_type_get_input {
37745 /* The HWRM command request type. */
37748 * The completion ring to send the completion event on. This should
37749 * be the NQ ID returned from the `nq_alloc` HWRM command.
37751 uint16_t cmpl_ring;
37753 * The sequence ID is used by the driver for tracking multiple
37754 * commands. This ID is treated as opaque data by the firmware and
37755 * the value is returned in the `hwrm_resp_hdr` upon completion.
37759 * The target ID of the command:
37760 * * 0x0-0xFFF8 - The function ID
37761 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
37762 * * 0xFFFD - Reserved for user-space HWRM interface
37765 uint16_t target_id;
37767 * A physical address pointer pointing to a host buffer that the
37768 * command's response data will be written. This can be either a host
37769 * physical address (HPA) or a guest physical address (GPA) and must
37770 * point to a physically contiguous block of memory.
37772 uint64_t resp_addr;
37773 /* Firmware session id returned when HWRM_TF_SESSION_OPEN is sent. */
37774 uint32_t fw_session_id;
37775 /* Control flags. */
37777 /* Indicates the flow direction. */
37778 #define HWRM_TF_TBL_TYPE_GET_INPUT_FLAGS_DIR UINT32_C(0x1)
37779 /* If this bit set to 0, then it indicates rx flow. */
37780 #define HWRM_TF_TBL_TYPE_GET_INPUT_FLAGS_DIR_RX UINT32_C(0x0)
37781 /* If this bit is set to 1, then it indicates that tx flow. */
37782 #define HWRM_TF_TBL_TYPE_GET_INPUT_FLAGS_DIR_TX UINT32_C(0x1)
37783 #define HWRM_TF_TBL_TYPE_GET_INPUT_FLAGS_DIR_LAST \
37784 HWRM_TF_TBL_TYPE_GET_INPUT_FLAGS_DIR_TX
37786 uint8_t unused0[2];
37788 * Type of the resource, defined globally in the
37789 * hwrm_tf_resc_type enum.
37792 /* Index of the type to retrieve. */
37796 /* hwrm_tf_tbl_type_get_output (size:1216b/152B) */
37797 struct hwrm_tf_tbl_type_get_output {
37798 /* The specific error status for the command. */
37799 uint16_t error_code;
37800 /* The HWRM command request type. */
37802 /* The sequence ID from the original command. */
37804 /* The length of the response data in number of bytes. */
37806 /* Response code. */
37807 uint32_t resp_code;
37808 /* Response size. */
37812 /* Response data. */
37815 uint8_t unused1[7];
37817 * This field is used in Output records to indicate that the output
37818 * is completely written to RAM. This field should be read as '1'
37819 * to indicate that the output has been completely written.
37820 * When writing a command completion or response to an internal
37821 * processor, the order of writes has to be such that this field
37827 /************************
37828 * hwrm_tf_tbl_type_set *
37829 ************************/
37832 /* hwrm_tf_tbl_type_set_input (size:1024b/128B) */
37833 struct hwrm_tf_tbl_type_set_input {
37834 /* The HWRM command request type. */
37837 * The completion ring to send the completion event on. This should
37838 * be the NQ ID returned from the `nq_alloc` HWRM command.
37840 uint16_t cmpl_ring;
37842 * The sequence ID is used by the driver for tracking multiple
37843 * commands. This ID is treated as opaque data by the firmware and
37844 * the value is returned in the `hwrm_resp_hdr` upon completion.
37848 * The target ID of the command:
37849 * * 0x0-0xFFF8 - The function ID
37850 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
37851 * * 0xFFFD - Reserved for user-space HWRM interface
37854 uint16_t target_id;
37856 * A physical address pointer pointing to a host buffer that the
37857 * command's response data will be written. This can be either a host
37858 * physical address (HPA) or a guest physical address (GPA) and must
37859 * point to a physically contiguous block of memory.
37861 uint64_t resp_addr;
37862 /* Firmware session id returned when HWRM_TF_SESSION_OPEN is sent. */
37863 uint32_t fw_session_id;
37864 /* Control flags. */
37866 /* Indicates the flow direction. */
37867 #define HWRM_TF_TBL_TYPE_SET_INPUT_FLAGS_DIR UINT32_C(0x1)
37868 /* If this bit set to 0, then it indicates rx flow. */
37869 #define HWRM_TF_TBL_TYPE_SET_INPUT_FLAGS_DIR_RX UINT32_C(0x0)
37870 /* If this bit is set to 1, then it indicates that tx flow. */
37871 #define HWRM_TF_TBL_TYPE_SET_INPUT_FLAGS_DIR_TX UINT32_C(0x1)
37872 #define HWRM_TF_TBL_TYPE_SET_INPUT_FLAGS_DIR_LAST \
37873 HWRM_TF_TBL_TYPE_SET_INPUT_FLAGS_DIR_TX
37875 uint8_t unused0[2];
37877 * Type of the resource, defined globally in the
37878 * hwrm_tf_resc_type enum.
37881 /* Index of the type to retrieve. */
37883 /* Size of the data to set. */
37886 uint8_t unused1[6];
37887 /* Data to be set. */
37891 /* hwrm_tf_tbl_type_set_output (size:128b/16B) */
37892 struct hwrm_tf_tbl_type_set_output {
37893 /* The specific error status for the command. */
37894 uint16_t error_code;
37895 /* The HWRM command request type. */
37897 /* The sequence ID from the original command. */
37899 /* The length of the response data in number of bytes. */
37902 uint8_t unused0[7];
37904 * This field is used in Output records to indicate that the output
37905 * is completely written to RAM. This field should be read as '1'
37906 * to indicate that the output has been completely written.
37907 * When writing a command completion or response to an internal
37908 * processor, the order of writes has to be such that this field
37914 /*************************
37915 * hwrm_tf_ctxt_mem_rgtr *
37916 *************************/
37919 /* hwrm_tf_ctxt_mem_rgtr_input (size:256b/32B) */
37920 struct hwrm_tf_ctxt_mem_rgtr_input {
37921 /* The HWRM command request type. */
37924 * The completion ring to send the completion event on. This should
37925 * be the NQ ID returned from the `nq_alloc` HWRM command.
37927 uint16_t cmpl_ring;
37929 * The sequence ID is used by the driver for tracking multiple
37930 * commands. This ID is treated as opaque data by the firmware and
37931 * the value is returned in the `hwrm_resp_hdr` upon completion.
37935 * The target ID of the command:
37936 * * 0x0-0xFFF8 - The function ID
37937 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
37938 * * 0xFFFD - Reserved for user-space HWRM interface
37941 uint16_t target_id;
37943 * A physical address pointer pointing to a host buffer that the
37944 * command's response data will be written. This can be either a host
37945 * physical address (HPA) or a guest physical address (GPA) and must
37946 * point to a physically contiguous block of memory.
37948 uint64_t resp_addr;
37949 /* Control flags. */
37951 /* Counter PBL indirect levels. */
37952 uint8_t page_level;
37953 /* PBL pointer is physical start address. */
37954 #define HWRM_TF_CTXT_MEM_RGTR_INPUT_PAGE_LEVEL_LVL_0 UINT32_C(0x0)
37955 /* PBL pointer points to PTE table. */
37956 #define HWRM_TF_CTXT_MEM_RGTR_INPUT_PAGE_LEVEL_LVL_1 UINT32_C(0x1)
37958 * PBL pointer points to PDE table with each entry pointing
37961 #define HWRM_TF_CTXT_MEM_RGTR_INPUT_PAGE_LEVEL_LVL_2 UINT32_C(0x2)
37962 #define HWRM_TF_CTXT_MEM_RGTR_INPUT_PAGE_LEVEL_LAST \
37963 HWRM_TF_CTXT_MEM_RGTR_INPUT_PAGE_LEVEL_LVL_2
37966 /* 4KB page size. */
37967 #define HWRM_TF_CTXT_MEM_RGTR_INPUT_PAGE_SIZE_4K UINT32_C(0x0)
37968 /* 8KB page size. */
37969 #define HWRM_TF_CTXT_MEM_RGTR_INPUT_PAGE_SIZE_8K UINT32_C(0x1)
37970 /* 64KB page size. */
37971 #define HWRM_TF_CTXT_MEM_RGTR_INPUT_PAGE_SIZE_64K UINT32_C(0x4)
37972 /* 256KB page size. */
37973 #define HWRM_TF_CTXT_MEM_RGTR_INPUT_PAGE_SIZE_256K UINT32_C(0x6)
37974 /* 1MB page size. */
37975 #define HWRM_TF_CTXT_MEM_RGTR_INPUT_PAGE_SIZE_1M UINT32_C(0x8)
37976 /* 2MB page size. */
37977 #define HWRM_TF_CTXT_MEM_RGTR_INPUT_PAGE_SIZE_2M UINT32_C(0x9)
37978 /* 4MB page size. */
37979 #define HWRM_TF_CTXT_MEM_RGTR_INPUT_PAGE_SIZE_4M UINT32_C(0xa)
37980 /* 1GB page size. */
37981 #define HWRM_TF_CTXT_MEM_RGTR_INPUT_PAGE_SIZE_1G UINT32_C(0x12)
37982 #define HWRM_TF_CTXT_MEM_RGTR_INPUT_PAGE_SIZE_LAST \
37983 HWRM_TF_CTXT_MEM_RGTR_INPUT_PAGE_SIZE_1G
37986 /* Pointer to the PBL, or PDL depending on number of levels */
37990 /* hwrm_tf_ctxt_mem_rgtr_output (size:128b/16B) */
37991 struct hwrm_tf_ctxt_mem_rgtr_output {
37992 /* The specific error status for the command. */
37993 uint16_t error_code;
37994 /* The HWRM command request type. */
37996 /* The sequence ID from the original command. */
37998 /* The length of the response data in number of bytes. */
38001 * Id/Handle to the recently register context memory. This
38002 * handle is passed to the TF session.
38006 uint8_t unused0[5];
38008 * This field is used in Output records to indicate that the
38009 * output is completely written to RAM. This field should be
38010 * read as '1' to indicate that the output has been
38011 * completely written. When writing a command completion or
38012 * response to an internal processor, the order of writes has
38013 * to be such that this field is written last.
38018 /***************************
38019 * hwrm_tf_ctxt_mem_unrgtr *
38020 ***************************/
38023 /* hwrm_tf_ctxt_mem_unrgtr_input (size:192b/24B) */
38024 struct hwrm_tf_ctxt_mem_unrgtr_input {
38025 /* The HWRM command request type. */
38028 * The completion ring to send the completion event on. This should
38029 * be the NQ ID returned from the `nq_alloc` HWRM command.
38031 uint16_t cmpl_ring;
38033 * The sequence ID is used by the driver for tracking multiple
38034 * commands. This ID is treated as opaque data by the firmware and
38035 * the value is returned in the `hwrm_resp_hdr` upon completion.
38039 * The target ID of the command:
38040 * * 0x0-0xFFF8 - The function ID
38041 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
38042 * * 0xFFFD - Reserved for user-space HWRM interface
38045 uint16_t target_id;
38047 * A physical address pointer pointing to a host buffer that the
38048 * command's response data will be written. This can be either a host
38049 * physical address (HPA) or a guest physical address (GPA) and must
38050 * point to a physically contiguous block of memory.
38052 uint64_t resp_addr;
38054 * Id/Handle to the recently register context memory. This
38055 * handle is passed to the TF session.
38059 uint8_t unused0[6];
38062 /* hwrm_tf_ctxt_mem_unrgtr_output (size:128b/16B) */
38063 struct hwrm_tf_ctxt_mem_unrgtr_output {
38064 /* The specific error status for the command. */
38065 uint16_t error_code;
38066 /* The HWRM command request type. */
38068 /* The sequence ID from the original command. */
38070 /* The length of the response data in number of bytes. */
38073 uint8_t unused0[7];
38075 * This field is used in Output records to indicate that the
38076 * output is completely written to RAM. This field should be
38077 * read as '1' to indicate that the output has been
38078 * completely written. When writing a command completion or
38079 * response to an internal processor, the order of writes has
38080 * to be such that this field is written last.
38085 /************************
38086 * hwrm_tf_ext_em_qcaps *
38087 ************************/
38090 /* hwrm_tf_ext_em_qcaps_input (size:192b/24B) */
38091 struct hwrm_tf_ext_em_qcaps_input {
38092 /* The HWRM command request type. */
38095 * The completion ring to send the completion event on. This should
38096 * be the NQ ID returned from the `nq_alloc` HWRM command.
38098 uint16_t cmpl_ring;
38100 * The sequence ID is used by the driver for tracking multiple
38101 * commands. This ID is treated as opaque data by the firmware and
38102 * the value is returned in the `hwrm_resp_hdr` upon completion.
38106 * The target ID of the command:
38107 * * 0x0-0xFFF8 - The function ID
38108 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
38109 * * 0xFFFD - Reserved for user-space HWRM interface
38112 uint16_t target_id;
38114 * A physical address pointer pointing to a host buffer that the
38115 * command's response data will be written. This can be either a host
38116 * physical address (HPA) or a guest physical address (GPA) and must
38117 * point to a physically contiguous block of memory.
38119 uint64_t resp_addr;
38120 /* Control flags. */
38122 /* Indicates the flow direction. */
38123 #define HWRM_TF_EXT_EM_QCAPS_INPUT_FLAGS_DIR \
38125 /* If this bit set to 0, then it indicates rx flow. */
38126 #define HWRM_TF_EXT_EM_QCAPS_INPUT_FLAGS_DIR_RX \
38128 /* If this bit is set to 1, then it indicates that tx flow. */
38129 #define HWRM_TF_EXT_EM_QCAPS_INPUT_FLAGS_DIR_TX \
38131 #define HWRM_TF_EXT_EM_QCAPS_INPUT_FLAGS_DIR_LAST \
38132 HWRM_TF_EXT_EM_QCAPS_INPUT_FLAGS_DIR_TX
38133 /* When set to 1, all offloaded flows will be sent to EXT EM. */
38134 #define HWRM_TF_EXT_EM_QCAPS_INPUT_FLAGS_PREFERRED_OFFLOAD \
38140 /* hwrm_tf_ext_em_qcaps_output (size:320b/40B) */
38141 struct hwrm_tf_ext_em_qcaps_output {
38142 /* The specific error status for the command. */
38143 uint16_t error_code;
38144 /* The HWRM command request type. */
38146 /* The sequence ID from the original command. */
38148 /* The length of the response data in number of bytes. */
38152 * When set to 1, indicates the the FW supports the Centralized
38153 * Memory Model. The concept designates one entity for the
38154 * memory allocation while all others ‘subscribe’ to it.
38156 #define HWRM_TF_EXT_EM_QCAPS_OUTPUT_FLAGS_CENTRALIZED_MEMORY_MODEL_SUPPORTED \
38159 * When set to 1, indicates the the FW supports the Detached
38160 * Centralized Memory Model. The memory is allocated and managed
38161 * as a separate entity. All PFs and VFs will be granted direct
38162 * or semi-direct access to the allocated memory while none of
38163 * which can interfere with the management of the memory.
38165 #define HWRM_TF_EXT_EM_QCAPS_OUTPUT_FLAGS_DETACHED_CENTRALIZED_MEMORY_MODEL_SUPPORTED \
38169 /* Support flags. */
38170 uint32_t supported;
38172 * If set to 1, then EXT EM KEY0 table is supported using
38174 * If set to 0, EXT EM KEY0 table is not supported.
38176 #define HWRM_TF_EXT_EM_QCAPS_OUTPUT_SUPPORTED_KEY0_TABLE \
38179 * If set to 1, then EXT EM KEY1 table is supported using
38181 * If set to 0, EXT EM KEY1 table is not supported.
38183 #define HWRM_TF_EXT_EM_QCAPS_OUTPUT_SUPPORTED_KEY1_TABLE \
38186 * If set to 1, then EXT EM External Record table is supported.
38187 * If set to 0, EXT EM External Record table is not
38188 * supported. (This table includes action record, EFC
38189 * pointers, encap pointers)
38191 #define HWRM_TF_EXT_EM_QCAPS_OUTPUT_SUPPORTED_EXTERNAL_RECORD_TABLE \
38194 * If set to 1, then EXT EM External Flow Counters table is
38196 * If set to 0, EXT EM External Flow Counters table is not
38199 #define HWRM_TF_EXT_EM_QCAPS_OUTPUT_SUPPORTED_EXTERNAL_FLOW_COUNTERS_TABLE \
38202 * If set to 1, then FID table used for implicit flow flush
38204 * If set to 0, then FID table used for implicit flow flush
38205 * is not supported.
38207 #define HWRM_TF_EXT_EM_QCAPS_OUTPUT_SUPPORTED_FID_TABLE \
38210 * The maximum number of entries supported by EXT EM. When
38211 * configuring the host memory the number of numbers of
38212 * entries that can supported are -
38213 * 32k, 64k 128k, 256k, 512k, 1M, 2M, 4M, 8M, 32M, 64M,
38215 * Any value that are not these values, the FW will round
38216 * down to the closest support number of entries.
38218 uint32_t max_entries_supported;
38220 * The entry size in bytes of each entry in the EXT EM
38221 * KEY0/KEY1 tables.
38223 uint16_t key_entry_size;
38225 * The entry size in bytes of each entry in the EXT EM RECORD
38228 uint16_t record_entry_size;
38229 /* The entry size in bytes of each entry in the EXT EM EFC tables. */
38230 uint16_t efc_entry_size;
38231 /* The FID size in bytes of each entry in the EXT EM FID tables. */
38232 uint16_t fid_entry_size;
38234 uint8_t unused1[7];
38236 * This field is used in Output records to indicate that the
38237 * output is completely written to RAM. This field should be
38238 * read as '1' to indicate that the output has been
38239 * completely written. When writing a command completion or
38240 * response to an internal processor, the order of writes has
38241 * to be such that this field is written last.
38246 /*********************
38247 * hwrm_tf_ext_em_op *
38248 *********************/
38251 /* hwrm_tf_ext_em_op_input (size:192b/24B) */
38252 struct hwrm_tf_ext_em_op_input {
38253 /* The HWRM command request type. */
38256 * The completion ring to send the completion event on. This should
38257 * be the NQ ID returned from the `nq_alloc` HWRM command.
38259 uint16_t cmpl_ring;
38261 * The sequence ID is used by the driver for tracking multiple
38262 * commands. This ID is treated as opaque data by the firmware and
38263 * the value is returned in the `hwrm_resp_hdr` upon completion.
38267 * The target ID of the command:
38268 * * 0x0-0xFFF8 - The function ID
38269 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
38270 * * 0xFFFD - Reserved for user-space HWRM interface
38273 uint16_t target_id;
38275 * A physical address pointer pointing to a host buffer that the
38276 * command's response data will be written. This can be either a host
38277 * physical address (HPA) or a guest physical address (GPA) and must
38278 * point to a physically contiguous block of memory.
38280 uint64_t resp_addr;
38281 /* Control flags. */
38283 /* Indicates the flow direction. */
38284 #define HWRM_TF_EXT_EM_OP_INPUT_FLAGS_DIR UINT32_C(0x1)
38285 /* If this bit set to 0, then it indicates rx flow. */
38286 #define HWRM_TF_EXT_EM_OP_INPUT_FLAGS_DIR_RX UINT32_C(0x0)
38287 /* If this bit is set to 1, then it indicates that tx flow. */
38288 #define HWRM_TF_EXT_EM_OP_INPUT_FLAGS_DIR_TX UINT32_C(0x1)
38289 #define HWRM_TF_EXT_EM_OP_INPUT_FLAGS_DIR_LAST \
38290 HWRM_TF_EXT_EM_OP_INPUT_FLAGS_DIR_TX
38293 /* The number of EXT EM key table entries to be configured. */
38295 /* This value is reserved and should not be used. */
38296 #define HWRM_TF_EXT_EM_OP_INPUT_OP_RESERVED UINT32_C(0x0)
38298 * To properly stop EXT EM and ensure there are no DMA's,
38299 * the caller must disable EXT EM for the given PF, using
38300 * this call. This will safely disable EXT EM and ensure
38301 * that all DMA'ed to the keys/records/efc have been
38304 #define HWRM_TF_EXT_EM_OP_INPUT_OP_EXT_EM_DISABLE UINT32_C(0x1)
38306 * Once the EXT EM host memory has been configured, EXT EM
38307 * options have been configured. Then the caller should
38308 * enable EXT EM for the given PF. Note once this call has
38309 * been made, then the EXT EM mechanism will be active and
38310 * DMA's will occur as packets are processed.
38312 #define HWRM_TF_EXT_EM_OP_INPUT_OP_EXT_EM_ENABLE UINT32_C(0x2)
38314 * Clear EXT EM settings for the given PF so that the
38315 * register values are reset back to their initial state.
38317 #define HWRM_TF_EXT_EM_OP_INPUT_OP_EXT_EM_CLEANUP UINT32_C(0x3)
38318 #define HWRM_TF_EXT_EM_OP_INPUT_OP_LAST \
38319 HWRM_TF_EXT_EM_OP_INPUT_OP_EXT_EM_CLEANUP
38324 /* hwrm_tf_ext_em_op_output (size:128b/16B) */
38325 struct hwrm_tf_ext_em_op_output {
38326 /* The specific error status for the command. */
38327 uint16_t error_code;
38328 /* The HWRM command request type. */
38330 /* The sequence ID from the original command. */
38332 /* The length of the response data in number of bytes. */
38335 uint8_t unused0[7];
38337 * This field is used in Output records to indicate that the
38338 * output is completely written to RAM. This field should be
38339 * read as '1' to indicate that the output has been
38340 * completely written. When writing a command completion or
38341 * response to an internal processor, the order of writes has
38342 * to be such that this field is written last.
38347 /**********************
38348 * hwrm_tf_ext_em_cfg *
38349 **********************/
38352 /* hwrm_tf_ext_em_cfg_input (size:384b/48B) */
38353 struct hwrm_tf_ext_em_cfg_input {
38354 /* The HWRM command request type. */
38357 * The completion ring to send the completion event on. This should
38358 * be the NQ ID returned from the `nq_alloc` HWRM command.
38360 uint16_t cmpl_ring;
38362 * The sequence ID is used by the driver for tracking multiple
38363 * commands. This ID is treated as opaque data by the firmware and
38364 * the value is returned in the `hwrm_resp_hdr` upon completion.
38368 * The target ID of the command:
38369 * * 0x0-0xFFF8 - The function ID
38370 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
38371 * * 0xFFFD - Reserved for user-space HWRM interface
38374 uint16_t target_id;
38376 * A physical address pointer pointing to a host buffer that the
38377 * command's response data will be written. This can be either a host
38378 * physical address (HPA) or a guest physical address (GPA) and must
38379 * point to a physically contiguous block of memory.
38381 uint64_t resp_addr;
38382 /* Control flags. */
38384 /* Indicates the flow direction. */
38385 #define HWRM_TF_EXT_EM_CFG_INPUT_FLAGS_DIR \
38387 /* If this bit set to 0, then it indicates rx flow. */
38388 #define HWRM_TF_EXT_EM_CFG_INPUT_FLAGS_DIR_RX \
38390 /* If this bit is set to 1, then it indicates that tx flow. */
38391 #define HWRM_TF_EXT_EM_CFG_INPUT_FLAGS_DIR_TX \
38393 #define HWRM_TF_EXT_EM_CFG_INPUT_FLAGS_DIR_LAST \
38394 HWRM_TF_EXT_EM_CFG_INPUT_FLAGS_DIR_TX
38395 /* When set to 1, all offloaded flows will be sent to EXT EM. */
38396 #define HWRM_TF_EXT_EM_CFG_INPUT_FLAGS_PREFERRED_OFFLOAD \
38398 /* When set to 1, secondary, 0 means primary. */
38399 #define HWRM_TF_EXT_EM_CFG_INPUT_FLAGS_SECONDARY_PF \
38402 * Group_id which used by Firmware to identify memory pools belonging
38403 * to certain group.
38407 * Dynamically reconfigure EEM pending cache every 1/10th of second.
38408 * If set to 0 it will disable the EEM HW flush of the pending cache.
38410 uint8_t flush_interval;
38414 * Configured EXT EM with the given number of entries. All
38415 * the EXT EM tables KEY0, KEY1, RECORD, EFC all have the
38416 * same number of entries and all tables will be configured
38417 * using this value. Current minimum value is 32k. Current
38418 * maximum value is 128M.
38420 uint32_t num_entries;
38423 /* Configured EXT EM with the given context if for KEY0 table. */
38424 uint16_t key0_ctx_id;
38425 /* Configured EXT EM with the given context if for KEY1 table. */
38426 uint16_t key1_ctx_id;
38427 /* Configured EXT EM with the given context if for RECORD table. */
38428 uint16_t record_ctx_id;
38429 /* Configured EXT EM with the given context if for EFC table. */
38430 uint16_t efc_ctx_id;
38431 /* Configured EXT EM with the given context if for EFC table. */
38432 uint16_t fid_ctx_id;
38439 /* hwrm_tf_ext_em_cfg_output (size:128b/16B) */
38440 struct hwrm_tf_ext_em_cfg_output {
38441 /* The specific error status for the command. */
38442 uint16_t error_code;
38443 /* The HWRM command request type. */
38445 /* The sequence ID from the original command. */
38447 /* The length of the response data in number of bytes. */
38450 uint8_t unused0[7];
38452 * This field is used in Output records to indicate that the
38453 * output is completely written to RAM. This field should be
38454 * read as '1' to indicate that the output has been
38455 * completely written. When writing a command completion or
38456 * response to an internal processor, the order of writes has
38457 * to be such that this field is written last.
38462 /***********************
38463 * hwrm_tf_ext_em_qcfg *
38464 ***********************/
38467 /* hwrm_tf_ext_em_qcfg_input (size:192b/24B) */
38468 struct hwrm_tf_ext_em_qcfg_input {
38469 /* The HWRM command request type. */
38472 * The completion ring to send the completion event on. This should
38473 * be the NQ ID returned from the `nq_alloc` HWRM command.
38475 uint16_t cmpl_ring;
38477 * The sequence ID is used by the driver for tracking multiple
38478 * commands. This ID is treated as opaque data by the firmware and
38479 * the value is returned in the `hwrm_resp_hdr` upon completion.
38483 * The target ID of the command:
38484 * * 0x0-0xFFF8 - The function ID
38485 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
38486 * * 0xFFFD - Reserved for user-space HWRM interface
38489 uint16_t target_id;
38491 * A physical address pointer pointing to a host buffer that the
38492 * command's response data will be written. This can be either a host
38493 * physical address (HPA) or a guest physical address (GPA) and must
38494 * point to a physically contiguous block of memory.
38496 uint64_t resp_addr;
38497 /* Control flags. */
38499 /* Indicates the flow direction. */
38500 #define HWRM_TF_EXT_EM_QCFG_INPUT_FLAGS_DIR UINT32_C(0x1)
38501 /* If this bit set to 0, then it indicates rx flow. */
38502 #define HWRM_TF_EXT_EM_QCFG_INPUT_FLAGS_DIR_RX UINT32_C(0x0)
38503 /* If this bit is set to 1, then it indicates that tx flow. */
38504 #define HWRM_TF_EXT_EM_QCFG_INPUT_FLAGS_DIR_TX UINT32_C(0x1)
38505 #define HWRM_TF_EXT_EM_QCFG_INPUT_FLAGS_DIR_LAST \
38506 HWRM_TF_EXT_EM_QCFG_INPUT_FLAGS_DIR_TX
38511 /* hwrm_tf_ext_em_qcfg_output (size:256b/32B) */
38512 struct hwrm_tf_ext_em_qcfg_output {
38513 /* The specific error status for the command. */
38514 uint16_t error_code;
38515 /* The HWRM command request type. */
38517 /* The sequence ID from the original command. */
38519 /* The length of the response data in number of bytes. */
38521 /* Control flags. */
38523 /* Indicates the flow direction. */
38524 #define HWRM_TF_EXT_EM_QCFG_OUTPUT_FLAGS_DIR \
38526 /* If this bit set to 0, then it indicates rx flow. */
38527 #define HWRM_TF_EXT_EM_QCFG_OUTPUT_FLAGS_DIR_RX \
38529 /* If this bit is set to 1, then it indicates that tx flow. */
38530 #define HWRM_TF_EXT_EM_QCFG_OUTPUT_FLAGS_DIR_TX \
38532 #define HWRM_TF_EXT_EM_QCFG_OUTPUT_FLAGS_DIR_LAST \
38533 HWRM_TF_EXT_EM_QCFG_OUTPUT_FLAGS_DIR_TX
38534 /* When set to 1, all offloaded flows will be sent to EXT EM. */
38535 #define HWRM_TF_EXT_EM_QCFG_OUTPUT_FLAGS_PREFERRED_OFFLOAD \
38537 /* The number of entries the FW has configured for EXT EM. */
38538 uint32_t num_entries;
38539 /* Configured EXT EM with the given context if for KEY0 table. */
38540 uint16_t key0_ctx_id;
38541 /* Configured EXT EM with the given context if for KEY1 table. */
38542 uint16_t key1_ctx_id;
38543 /* Configured EXT EM with the given context if for RECORD table. */
38544 uint16_t record_ctx_id;
38545 /* Configured EXT EM with the given context if for EFC table. */
38546 uint16_t efc_ctx_id;
38547 /* Configured EXT EM with the given context if for EFC table. */
38548 uint16_t fid_ctx_id;
38550 uint8_t unused0[5];
38552 * This field is used in Output records to indicate that the
38553 * output is completely written to RAM. This field should be
38554 * read as '1' to indicate that the output has been
38555 * completely written. When writing a command completion or
38556 * response to an internal processor, the order of writes has
38557 * to be such that this field is written last.
38562 /*********************
38563 * hwrm_tf_em_insert *
38564 *********************/
38567 /* hwrm_tf_em_insert_input (size:832b/104B) */
38568 struct hwrm_tf_em_insert_input {
38569 /* The HWRM command request type. */
38572 * The completion ring to send the completion event on. This should
38573 * be the NQ ID returned from the `nq_alloc` HWRM command.
38575 uint16_t cmpl_ring;
38577 * The sequence ID is used by the driver for tracking multiple
38578 * commands. This ID is treated as opaque data by the firmware and
38579 * the value is returned in the `hwrm_resp_hdr` upon completion.
38583 * The target ID of the command:
38584 * * 0x0-0xFFF8 - The function ID
38585 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
38586 * * 0xFFFD - Reserved for user-space HWRM interface
38589 uint16_t target_id;
38591 * A physical address pointer pointing to a host buffer that the
38592 * command's response data will be written. This can be either a host
38593 * physical address (HPA) or a guest physical address (GPA) and must
38594 * point to a physically contiguous block of memory.
38596 uint64_t resp_addr;
38597 /* Firmware Session Id. */
38598 uint32_t fw_session_id;
38599 /* Control Flags. */
38601 /* Indicates the flow direction. */
38602 #define HWRM_TF_EM_INSERT_INPUT_FLAGS_DIR UINT32_C(0x1)
38603 /* If this bit set to 0, then it indicates rx flow. */
38604 #define HWRM_TF_EM_INSERT_INPUT_FLAGS_DIR_RX UINT32_C(0x0)
38605 /* If this bit is set to 1, then it indicates that tx flow. */
38606 #define HWRM_TF_EM_INSERT_INPUT_FLAGS_DIR_TX UINT32_C(0x1)
38607 #define HWRM_TF_EM_INSERT_INPUT_FLAGS_DIR_LAST \
38608 HWRM_TF_EM_INSERT_INPUT_FLAGS_DIR_TX
38609 /* Reported match strength. */
38611 /* Index to action. */
38612 uint32_t action_ptr;
38613 /* Index of EM record. */
38614 uint32_t em_record_idx;
38615 /* EM Key value. */
38616 uint64_t em_key[8];
38617 /* Number of bits in em_key. */
38618 uint16_t em_key_bitlen;
38620 uint16_t unused0[3];
38623 /* hwrm_tf_em_insert_output (size:128b/16B) */
38624 struct hwrm_tf_em_insert_output {
38625 /* The specific error status for the command. */
38626 uint16_t error_code;
38627 /* The HWRM command request type. */
38629 /* The sequence ID from the original command. */
38631 /* The length of the response data in number of bytes. */
38633 /* EM record pointer index. */
38634 uint16_t rptr_index;
38635 /* EM record offset 0~3. */
38636 uint8_t rptr_entry;
38637 /* Number of word entries consumed by the key. */
38638 uint8_t num_of_entries;
38643 /*********************
38644 * hwrm_tf_em_delete *
38645 *********************/
38648 /* hwrm_tf_em_delete_input (size:832b/104B) */
38649 struct hwrm_tf_em_delete_input {
38650 /* The HWRM command request type. */
38653 * The completion ring to send the completion event on. This should
38654 * be the NQ ID returned from the `nq_alloc` HWRM command.
38656 uint16_t cmpl_ring;
38658 * The sequence ID is used by the driver for tracking multiple
38659 * commands. This ID is treated as opaque data by the firmware and
38660 * the value is returned in the `hwrm_resp_hdr` upon completion.
38664 * The target ID of the command:
38665 * * 0x0-0xFFF8 - The function ID
38666 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
38667 * * 0xFFFD - Reserved for user-space HWRM interface
38670 uint16_t target_id;
38672 * A physical address pointer pointing to a host buffer that the
38673 * command's response data will be written. This can be either a host
38674 * physical address (HPA) or a guest physical address (GPA) and must
38675 * point to a physically contiguous block of memory.
38677 uint64_t resp_addr;
38679 uint32_t fw_session_id;
38680 /* Control flags. */
38682 /* Indicates the flow direction. */
38683 #define HWRM_TF_EM_DELETE_INPUT_FLAGS_DIR UINT32_C(0x1)
38684 /* If this bit set to 0, then it indicates rx flow. */
38685 #define HWRM_TF_EM_DELETE_INPUT_FLAGS_DIR_RX UINT32_C(0x0)
38686 /* If this bit is set to 1, then it indicates that tx flow. */
38687 #define HWRM_TF_EM_DELETE_INPUT_FLAGS_DIR_TX UINT32_C(0x1)
38688 #define HWRM_TF_EM_DELETE_INPUT_FLAGS_DIR_LAST \
38689 HWRM_TF_EM_DELETE_INPUT_FLAGS_DIR_TX
38692 /* EM internal flow hanndle. */
38693 uint64_t flow_handle;
38695 uint64_t em_key[8];
38696 /* Number of bits in em_key. */
38697 uint16_t em_key_bitlen;
38699 uint16_t unused1[3];
38702 /* hwrm_tf_em_delete_output (size:128b/16B) */
38703 struct hwrm_tf_em_delete_output {
38704 /* The specific error status for the command. */
38705 uint16_t error_code;
38706 /* The HWRM command request type. */
38708 /* The sequence ID from the original command. */
38710 /* The length of the response data in number of bytes. */
38712 /* Original stack allocation index. */
38715 uint16_t unused0[3];
38718 /********************
38719 * hwrm_tf_tcam_set *
38720 ********************/
38723 /* hwrm_tf_tcam_set_input (size:1024b/128B) */
38724 struct hwrm_tf_tcam_set_input {
38725 /* The HWRM command request type. */
38728 * The completion ring to send the completion event on. This should
38729 * be the NQ ID returned from the `nq_alloc` HWRM command.
38731 uint16_t cmpl_ring;
38733 * The sequence ID is used by the driver for tracking multiple
38734 * commands. This ID is treated as opaque data by the firmware and
38735 * the value is returned in the `hwrm_resp_hdr` upon completion.
38739 * The target ID of the command:
38740 * * 0x0-0xFFF8 - The function ID
38741 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
38742 * * 0xFFFD - Reserved for user-space HWRM interface
38745 uint16_t target_id;
38747 * A physical address pointer pointing to a host buffer that the
38748 * command's response data will be written. This can be either a host
38749 * physical address (HPA) or a guest physical address (GPA) and must
38750 * point to a physically contiguous block of memory.
38752 uint64_t resp_addr;
38753 /* Firmware session id returned when HWRM_TF_SESSION_OPEN is sent. */
38754 uint32_t fw_session_id;
38755 /* Control flags. */
38757 /* Indicates the flow direction. */
38758 #define HWRM_TF_TCAM_SET_INPUT_FLAGS_DIR UINT32_C(0x1)
38759 /* If this bit set to 0, then it indicates rx flow. */
38760 #define HWRM_TF_TCAM_SET_INPUT_FLAGS_DIR_RX UINT32_C(0x0)
38761 /* If this bit is set to 1, then it indicates that tx flow. */
38762 #define HWRM_TF_TCAM_SET_INPUT_FLAGS_DIR_TX UINT32_C(0x1)
38763 #define HWRM_TF_TCAM_SET_INPUT_FLAGS_DIR_LAST \
38764 HWRM_TF_TCAM_SET_INPUT_FLAGS_DIR_TX
38766 * Indicate device data is being sent via DMA, the device
38767 * data is packing does not change.
38769 #define HWRM_TF_TCAM_SET_INPUT_FLAGS_DMA UINT32_C(0x2)
38771 * TCAM type of the resource, defined globally in the
38772 * hwrm_tf_resc_type enum.
38775 /* Index of TCAM entry. */
38777 /* Number of bytes in the TCAM key. */
38779 /* Number of bytes in the TCAM result. */
38780 uint8_t result_size;
38782 * Offset from which the mask bytes start in the device data
38783 * array, key offset is always 0.
38785 uint8_t mask_offset;
38786 /* Offset from which the result bytes start in the device data array. */
38787 uint8_t result_offset;
38789 uint8_t unused0[6];
38791 * TCAM key located at offset 0, mask located at mask_offsec
38792 * and result at result_offsec for the device.
38794 uint8_t dev_data[88];
38797 /* hwrm_tf_tcam_set_output (size:128b/16B) */
38798 struct hwrm_tf_tcam_set_output {
38799 /* The specific error status for the command. */
38800 uint16_t error_code;
38801 /* The HWRM command request type. */
38803 /* The sequence ID from the original command. */
38805 /* The length of the response data in number of bytes. */
38808 uint8_t unused0[7];
38810 * This field is used in Output records to indicate that the
38811 * output is completely written to RAM. This field should be
38812 * read as '1' to indicate that the output has been
38813 * completely written. When writing a command completion or
38814 * response to an internal processor, the order of writes has
38815 * to be such that this field is written last.
38820 /********************
38821 * hwrm_tf_tcam_get *
38822 ********************/
38825 /* hwrm_tf_tcam_get_input (size:256b/32B) */
38826 struct hwrm_tf_tcam_get_input {
38827 /* The HWRM command request type. */
38830 * The completion ring to send the completion event on. This should
38831 * be the NQ ID returned from the `nq_alloc` HWRM command.
38833 uint16_t cmpl_ring;
38835 * The sequence ID is used by the driver for tracking multiple
38836 * commands. This ID is treated as opaque data by the firmware and
38837 * the value is returned in the `hwrm_resp_hdr` upon completion.
38841 * The target ID of the command:
38842 * * 0x0-0xFFF8 - The function ID
38843 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
38844 * * 0xFFFD - Reserved for user-space HWRM interface
38847 uint16_t target_id;
38849 * A physical address pointer pointing to a host buffer that the
38850 * command's response data will be written. This can be either a host
38851 * physical address (HPA) or a guest physical address (GPA) and must
38852 * point to a physically contiguous block of memory.
38854 uint64_t resp_addr;
38855 /* Firmware session id returned when HWRM_TF_SESSION_OPEN is sent. */
38856 uint32_t fw_session_id;
38857 /* Control flags. */
38859 /* Indicates the flow direction. */
38860 #define HWRM_TF_TCAM_GET_INPUT_FLAGS_DIR UINT32_C(0x1)
38861 /* If this bit set to 0, then it indicates rx flow. */
38862 #define HWRM_TF_TCAM_GET_INPUT_FLAGS_DIR_RX UINT32_C(0x0)
38863 /* If this bit is set to 1, then it indicates that tx flow. */
38864 #define HWRM_TF_TCAM_GET_INPUT_FLAGS_DIR_TX UINT32_C(0x1)
38865 #define HWRM_TF_TCAM_GET_INPUT_FLAGS_DIR_LAST \
38866 HWRM_TF_TCAM_GET_INPUT_FLAGS_DIR_TX
38868 * TCAM type of the resource, defined globally in the
38869 * hwrm_tf_resc_type enum.
38872 /* Index of a TCAM entry. */
38878 /* hwrm_tf_tcam_get_output (size:2368b/296B) */
38879 struct hwrm_tf_tcam_get_output {
38880 /* The specific error status for the command. */
38881 uint16_t error_code;
38882 /* The HWRM command request type. */
38884 /* The sequence ID from the original command. */
38886 /* The length of the response data in number of bytes. */
38888 /* Number of bytes in the TCAM key. */
38890 /* Number of bytes in the TCAM entry. */
38891 uint8_t result_size;
38892 /* Offset from which the mask bytes start in the device data array. */
38893 uint8_t mask_offset;
38894 /* Offset from which the result bytes start in the device data array. */
38895 uint8_t result_offset;
38897 uint8_t unused0[4];
38899 * TCAM key located at offset 0, mask located at mask_offsec
38900 * and result at result_offsec for the device.
38902 uint8_t dev_data[272];
38904 uint8_t unused1[7];
38906 * This field is used in Output records to indicate that the
38907 * output is completely written to RAM. This field should be
38908 * read as '1' to indicate that the output has been
38909 * completely written. When writing a command completion or
38910 * response to an internal processor, the order of writes has
38911 * to be such that this field is written last.
38916 /*********************
38917 * hwrm_tf_tcam_move *
38918 *********************/
38921 /* hwrm_tf_tcam_move_input (size:1024b/128B) */
38922 struct hwrm_tf_tcam_move_input {
38923 /* The HWRM command request type. */
38926 * The completion ring to send the completion event on. This should
38927 * be the NQ ID returned from the `nq_alloc` HWRM command.
38929 uint16_t cmpl_ring;
38931 * The sequence ID is used by the driver for tracking multiple
38932 * commands. This ID is treated as opaque data by the firmware and
38933 * the value is returned in the `hwrm_resp_hdr` upon completion.
38937 * The target ID of the command:
38938 * * 0x0-0xFFF8 - The function ID
38939 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
38940 * * 0xFFFD - Reserved for user-space HWRM interface
38943 uint16_t target_id;
38945 * A physical address pointer pointing to a host buffer that the
38946 * command's response data will be written. This can be either a host
38947 * physical address (HPA) or a guest physical address (GPA) and must
38948 * point to a physically contiguous block of memory.
38950 uint64_t resp_addr;
38951 /* Firmware session id returned when HWRM_TF_SESSION_OPEN is sent. */
38952 uint32_t fw_session_id;
38953 /* Control flags. */
38955 /* Indicates the flow direction. */
38956 #define HWRM_TF_TCAM_MOVE_INPUT_FLAGS_DIR UINT32_C(0x1)
38957 /* If this bit set to 0, then it indicates rx flow. */
38958 #define HWRM_TF_TCAM_MOVE_INPUT_FLAGS_DIR_RX UINT32_C(0x0)
38959 /* If this bit is set to 1, then it indicates that tx flow. */
38960 #define HWRM_TF_TCAM_MOVE_INPUT_FLAGS_DIR_TX UINT32_C(0x1)
38961 #define HWRM_TF_TCAM_MOVE_INPUT_FLAGS_DIR_LAST \
38962 HWRM_TF_TCAM_MOVE_INPUT_FLAGS_DIR_TX
38964 * TCAM type of the resource, defined globally in the
38965 * hwrm_tf_resc_type enum.
38968 /* Number of TCAM index pairs to be swapped for the device. */
38972 /* TCAM index pairs to be swapped for the device. */
38973 uint16_t idx_pairs[48];
38976 /* hwrm_tf_tcam_move_output (size:128b/16B) */
38977 struct hwrm_tf_tcam_move_output {
38978 /* The specific error status for the command. */
38979 uint16_t error_code;
38980 /* The HWRM command request type. */
38982 /* The sequence ID from the original command. */
38984 /* The length of the response data in number of bytes. */
38987 uint8_t unused0[7];
38989 * This field is used in Output records to indicate that the
38990 * output is completely written to RAM. This field should be
38991 * read as '1' to indicate that the output has been
38992 * completely written. When writing a command completion or
38993 * response to an internal processor, the order of writes has
38994 * to be such that this field is written last.
38999 /*********************
39000 * hwrm_tf_tcam_free *
39001 *********************/
39004 /* hwrm_tf_tcam_free_input (size:1024b/128B) */
39005 struct hwrm_tf_tcam_free_input {
39006 /* The HWRM command request type. */
39009 * The completion ring to send the completion event on. This should
39010 * be the NQ ID returned from the `nq_alloc` HWRM command.
39012 uint16_t cmpl_ring;
39014 * The sequence ID is used by the driver for tracking multiple
39015 * commands. This ID is treated as opaque data by the firmware and
39016 * the value is returned in the `hwrm_resp_hdr` upon completion.
39020 * The target ID of the command:
39021 * * 0x0-0xFFF8 - The function ID
39022 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
39023 * * 0xFFFD - Reserved for user-space HWRM interface
39026 uint16_t target_id;
39028 * A physical address pointer pointing to a host buffer that the
39029 * command's response data will be written. This can be either a host
39030 * physical address (HPA) or a guest physical address (GPA) and must
39031 * point to a physically contiguous block of memory.
39033 uint64_t resp_addr;
39034 /* Firmware session id returned when HWRM_TF_SESSION_OPEN is sent. */
39035 uint32_t fw_session_id;
39036 /* Control flags. */
39038 /* Indicates the flow direction. */
39039 #define HWRM_TF_TCAM_FREE_INPUT_FLAGS_DIR UINT32_C(0x1)
39040 /* If this bit set to 0, then it indicates rx flow. */
39041 #define HWRM_TF_TCAM_FREE_INPUT_FLAGS_DIR_RX UINT32_C(0x0)
39042 /* If this bit is set to 1, then it indicates that tx flow. */
39043 #define HWRM_TF_TCAM_FREE_INPUT_FLAGS_DIR_TX UINT32_C(0x1)
39044 #define HWRM_TF_TCAM_FREE_INPUT_FLAGS_DIR_LAST \
39045 HWRM_TF_TCAM_FREE_INPUT_FLAGS_DIR_TX
39047 * TCAM type of the resource, defined globally in the
39048 * hwrm_tf_resc_type enum.
39051 /* Number of TCAM index to be deleted for the device. */
39055 /* TCAM index list to be deleted for the device. */
39056 uint16_t idx_list[48];
39059 /* hwrm_tf_tcam_free_output (size:128b/16B) */
39060 struct hwrm_tf_tcam_free_output {
39061 /* The specific error status for the command. */
39062 uint16_t error_code;
39063 /* The HWRM command request type. */
39065 /* The sequence ID from the original command. */
39067 /* The length of the response data in number of bytes. */
39070 uint8_t unused0[7];
39072 * This field is used in Output records to indicate that the
39073 * output is completely written to RAM. This field should be
39074 * read as '1' to indicate that the output has been
39075 * completely written. When writing a command completion or
39076 * response to an internal processor, the order of writes has
39077 * to be such that this field is written last.
39082 /**************************
39083 * hwrm_tf_global_cfg_set *
39084 **************************/
39087 /* hwrm_tf_global_cfg_set_input (size:448b/56B) */
39088 struct hwrm_tf_global_cfg_set_input {
39089 /* The HWRM command request type. */
39092 * The completion ring to send the completion event on. This should
39093 * be the NQ ID returned from the `nq_alloc` HWRM command.
39095 uint16_t cmpl_ring;
39097 * The sequence ID is used by the driver for tracking multiple
39098 * commands. This ID is treated as opaque data by the firmware and
39099 * the value is returned in the `hwrm_resp_hdr` upon completion.
39103 * The target ID of the command:
39104 * * 0x0-0xFFF8 - The function ID
39105 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
39106 * * 0xFFFD - Reserved for user-space HWRM interface
39109 uint16_t target_id;
39111 * A physical address pointer pointing to a host buffer that the
39112 * command's response data will be written. This can be either a host
39113 * physical address (HPA) or a guest physical address (GPA) and must
39114 * point to a physically contiguous block of memory.
39116 uint64_t resp_addr;
39117 /* Firmware session id returned when HWRM_TF_SESSION_OPEN is sent. */
39118 uint32_t fw_session_id;
39119 /* Control flags. */
39121 /* Indicates the flow direction. */
39122 #define HWRM_TF_GLOBAL_CFG_SET_INPUT_FLAGS_DIR UINT32_C(0x1)
39123 /* If this bit set to 0, then it indicates rx flow. */
39124 #define HWRM_TF_GLOBAL_CFG_SET_INPUT_FLAGS_DIR_RX UINT32_C(0x0)
39125 /* If this bit is set to 1, then it indicates that tx flow. */
39126 #define HWRM_TF_GLOBAL_CFG_SET_INPUT_FLAGS_DIR_TX UINT32_C(0x1)
39127 #define HWRM_TF_GLOBAL_CFG_SET_INPUT_FLAGS_DIR_LAST \
39128 HWRM_TF_GLOBAL_CFG_SET_INPUT_FLAGS_DIR_TX
39129 /* Global Cfg type */
39131 /* Offset of the type */
39133 /* Size of the data to set in bytes */
39136 uint8_t unused0[6];
39139 /* Mask of data to set, 0 indicates no mask */
39143 /* hwrm_tf_global_cfg_set_output (size:128b/16B) */
39144 struct hwrm_tf_global_cfg_set_output {
39145 /* The specific error status for the command. */
39146 uint16_t error_code;
39147 /* The HWRM command request type. */
39149 /* The sequence ID from the original command. */
39151 /* The length of the response data in number of bytes. */
39154 uint8_t unused0[7];
39156 * This field is used in Output records to indicate that the
39157 * output is completely written to RAM. This field should be
39158 * read as '1' to indicate that the output has been
39159 * completely written. When writing a command completion or
39160 * response to an internal processor, the order of writes has
39161 * to be such that this field is written last.
39166 /**************************
39167 * hwrm_tf_global_cfg_get *
39168 **************************/
39171 /* hwrm_tf_global_cfg_get_input (size:320b/40B) */
39172 struct hwrm_tf_global_cfg_get_input {
39173 /* The HWRM command request type. */
39176 * The completion ring to send the completion event on. This should
39177 * be the NQ ID returned from the `nq_alloc` HWRM command.
39179 uint16_t cmpl_ring;
39181 * The sequence ID is used by the driver for tracking multiple
39182 * commands. This ID is treated as opaque data by the firmware and
39183 * the value is returned in the `hwrm_resp_hdr` upon completion.
39187 * The target ID of the command:
39188 * * 0x0-0xFFF8 - The function ID
39189 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
39190 * * 0xFFFD - Reserved for user-space HWRM interface
39193 uint16_t target_id;
39195 * A physical address pointer pointing to a host buffer that the
39196 * command's response data will be written. This can be either a host
39197 * physical address (HPA) or a guest physical address (GPA) and must
39198 * point to a physically contiguous block of memory.
39200 uint64_t resp_addr;
39201 /* Firmware session id returned when HWRM_TF_SESSION_OPEN is sent. */
39202 uint32_t fw_session_id;
39203 /* Control flags. */
39205 /* Indicates the flow direction. */
39206 #define HWRM_TF_GLOBAL_CFG_GET_INPUT_FLAGS_DIR UINT32_C(0x1)
39207 /* If this bit set to 0, then it indicates rx flow. */
39208 #define HWRM_TF_GLOBAL_CFG_GET_INPUT_FLAGS_DIR_RX UINT32_C(0x0)
39209 /* If this bit is set to 1, then it indicates that tx flow. */
39210 #define HWRM_TF_GLOBAL_CFG_GET_INPUT_FLAGS_DIR_TX UINT32_C(0x1)
39211 #define HWRM_TF_GLOBAL_CFG_GET_INPUT_FLAGS_DIR_LAST \
39212 HWRM_TF_GLOBAL_CFG_GET_INPUT_FLAGS_DIR_TX
39213 /* Global Cfg type */
39215 /* Offset of the type */
39217 /* Size of the data to set in bytes */
39220 uint8_t unused0[6];
39223 /* hwrm_tf_global_cfg_get_output (size:256b/32B) */
39224 struct hwrm_tf_global_cfg_get_output {
39225 /* The specific error status for the command. */
39226 uint16_t error_code;
39227 /* The HWRM command request type. */
39229 /* The sequence ID from the original command. */
39231 /* The length of the response data in number of bytes. */
39233 /* Size of the data read in bytes */
39236 uint8_t unused0[6];
39241 /**********************
39242 * hwrm_tf_if_tbl_get *
39243 **********************/
39246 /* hwrm_tf_if_tbl_get_input (size:256b/32B) */
39247 struct hwrm_tf_if_tbl_get_input {
39248 /* The HWRM command request type. */
39251 * The completion ring to send the completion event on. This should
39252 * be the NQ ID returned from the `nq_alloc` HWRM command.
39254 uint16_t cmpl_ring;
39256 * The sequence ID is used by the driver for tracking multiple
39257 * commands. This ID is treated as opaque data by the firmware and
39258 * the value is returned in the `hwrm_resp_hdr` upon completion.
39262 * The target ID of the command:
39263 * * 0x0-0xFFF8 - The function ID
39264 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
39265 * * 0xFFFD - Reserved for user-space HWRM interface
39268 uint16_t target_id;
39270 * A physical address pointer pointing to a host buffer that the
39271 * command's response data will be written. This can be either a host
39272 * physical address (HPA) or a guest physical address (GPA) and must
39273 * point to a physically contiguous block of memory.
39275 uint64_t resp_addr;
39276 /* Firmware session id returned when HWRM_TF_SESSION_OPEN is sent. */
39277 uint32_t fw_session_id;
39278 /* Control flags. */
39280 /* Indicates the flow direction. */
39281 #define HWRM_TF_IF_TBL_GET_INPUT_FLAGS_DIR UINT32_C(0x1)
39282 /* If this bit set to 0, then it indicates rx flow. */
39283 #define HWRM_TF_IF_TBL_GET_INPUT_FLAGS_DIR_RX UINT32_C(0x0)
39284 /* If this bit is set to 1, then it indicates that tx flow. */
39285 #define HWRM_TF_IF_TBL_GET_INPUT_FLAGS_DIR_TX UINT32_C(0x1)
39286 #define HWRM_TF_IF_TBL_GET_INPUT_FLAGS_DIR_LAST \
39287 HWRM_TF_IF_TBL_GET_INPUT_FLAGS_DIR_TX
39288 /* Size of the data to set. */
39291 * Type of the resource, defined globally in the
39292 * hwrm_tf_resc_type enum.
39295 /* Index of the type to retrieve. */
39299 /* hwrm_tf_if_tbl_get_output (size:256b/32B) */
39300 struct hwrm_tf_if_tbl_get_output {
39301 /* The specific error status for the command. */
39302 uint16_t error_code;
39303 /* The HWRM command request type. */
39305 /* The sequence ID from the original command. */
39307 /* The length of the response data in number of bytes. */
39309 /* Response code. */
39310 uint32_t resp_code;
39311 /* Response size. */
39315 /* Response data. */
39318 uint8_t unused1[7];
39320 * This field is used in Output records to indicate that the output
39321 * is completely written to RAM. This field should be read as '1'
39322 * to indicate that the output has been completely written.
39323 * When writing a command completion or response to an internal
39324 * processor, the order of writes has to be such that this field
39330 /***************************
39331 * hwrm_tf_if_tbl_type_set *
39332 ***************************/
39335 /* hwrm_tf_if_tbl_set_input (size:384b/48B) */
39336 struct hwrm_tf_if_tbl_set_input {
39337 /* The HWRM command request type. */
39340 * The completion ring to send the completion event on. This should
39341 * be the NQ ID returned from the `nq_alloc` HWRM command.
39343 uint16_t cmpl_ring;
39345 * The sequence ID is used by the driver for tracking multiple
39346 * commands. This ID is treated as opaque data by the firmware and
39347 * the value is returned in the `hwrm_resp_hdr` upon completion.
39351 * The target ID of the command:
39352 * * 0x0-0xFFF8 - The function ID
39353 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
39354 * * 0xFFFD - Reserved for user-space HWRM interface
39357 uint16_t target_id;
39359 * A physical address pointer pointing to a host buffer that the
39360 * command's response data will be written. This can be either a host
39361 * physical address (HPA) or a guest physical address (GPA) and must
39362 * point to a physically contiguous block of memory.
39364 uint64_t resp_addr;
39365 /* Firmware session id returned when HWRM_TF_SESSION_OPEN is sent. */
39366 uint32_t fw_session_id;
39367 /* Control flags. */
39369 /* Indicates the flow direction. */
39370 #define HWRM_TF_IF_TBL_SET_INPUT_FLAGS_DIR UINT32_C(0x1)
39371 /* If this bit set to 0, then it indicates rx flow. */
39372 #define HWRM_TF_IF_TBL_SET_INPUT_FLAGS_DIR_RX UINT32_C(0x0)
39373 /* If this bit is set to 1, then it indicates that tx flow. */
39374 #define HWRM_TF_IF_TBL_SET_INPUT_FLAGS_DIR_TX UINT32_C(0x1)
39375 #define HWRM_TF_IF_TBL_SET_INPUT_FLAGS_DIR_LAST \
39376 HWRM_TF_IF_TBL_SET_INPUT_FLAGS_DIR_TX
39378 uint8_t unused0[2];
39380 * Type of the resource, defined globally in the
39381 * hwrm_tf_resc_type enum.
39384 /* Index of the type to set. */
39386 /* Size of the data to set. */
39389 uint8_t unused1[6];
39390 /* Data to be set. */
39394 /* hwrm_tf_if_tbl_set_output (size:128b/16B) */
39395 struct hwrm_tf_if_tbl_set_output {
39396 /* The specific error status for the command. */
39397 uint16_t error_code;
39398 /* The HWRM command request type. */
39400 /* The sequence ID from the original command. */
39402 /* The length of the response data in number of bytes. */
39405 uint8_t unused0[7];
39407 * This field is used in Output records to indicate that the output
39408 * is completely written to RAM. This field should be read as '1'
39409 * to indicate that the output has been completely written.
39410 * When writing a command completion or response to an internal
39411 * processor, the order of writes has to be such that this field
39417 /******************************
39418 * hwrm_tunnel_dst_port_query *
39419 ******************************/
39422 /* hwrm_tunnel_dst_port_query_input (size:192b/24B) */
39423 struct hwrm_tunnel_dst_port_query_input {
39424 /* The HWRM command request type. */
39427 * The completion ring to send the completion event on. This should
39428 * be the NQ ID returned from the `nq_alloc` HWRM command.
39430 uint16_t cmpl_ring;
39432 * The sequence ID is used by the driver for tracking multiple
39433 * commands. This ID is treated as opaque data by the firmware and
39434 * the value is returned in the `hwrm_resp_hdr` upon completion.
39438 * The target ID of the command:
39439 * * 0x0-0xFFF8 - The function ID
39440 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
39441 * * 0xFFFD - Reserved for user-space HWRM interface
39444 uint16_t target_id;
39446 * A physical address pointer pointing to a host buffer that the
39447 * command's response data will be written. This can be either a host
39448 * physical address (HPA) or a guest physical address (GPA) and must
39449 * point to a physically contiguous block of memory.
39451 uint64_t resp_addr;
39453 uint8_t tunnel_type;
39454 /* Virtual eXtensible Local Area Network (VXLAN) */
39455 #define HWRM_TUNNEL_DST_PORT_QUERY_INPUT_TUNNEL_TYPE_VXLAN \
39457 /* Generic Network Virtualization Encapsulation (Geneve) */
39458 #define HWRM_TUNNEL_DST_PORT_QUERY_INPUT_TUNNEL_TYPE_GENEVE \
39460 /* IPV4 over virtual eXtensible Local Area Network (IPV4oVXLAN) */
39461 #define HWRM_TUNNEL_DST_PORT_QUERY_INPUT_TUNNEL_TYPE_VXLAN_V4 \
39463 /* Enhance Generic Routing Encapsulation (GRE version 1) inside IP datagram payload */
39464 #define HWRM_TUNNEL_DST_PORT_QUERY_INPUT_TUNNEL_TYPE_IPGRE_V1 \
39466 /* Use fixed layer 2 ether type of 0xFFFF */
39467 #define HWRM_TUNNEL_DST_PORT_QUERY_INPUT_TUNNEL_TYPE_L2_ETYPE \
39469 /* IPV6 over virtual eXtensible Local Area Network with GPE header (IPV6oVXLANGPE) */
39470 #define HWRM_TUNNEL_DST_PORT_QUERY_INPUT_TUNNEL_TYPE_VXLAN_GPE_V6 \
39472 #define HWRM_TUNNEL_DST_PORT_QUERY_INPUT_TUNNEL_TYPE_LAST \
39473 HWRM_TUNNEL_DST_PORT_QUERY_INPUT_TUNNEL_TYPE_VXLAN_GPE_V6
39474 uint8_t unused_0[7];
39477 /* hwrm_tunnel_dst_port_query_output (size:128b/16B) */
39478 struct hwrm_tunnel_dst_port_query_output {
39479 /* The specific error status for the command. */
39480 uint16_t error_code;
39481 /* The HWRM command request type. */
39483 /* The sequence ID from the original command. */
39485 /* The length of the response data in number of bytes. */
39488 * This field represents the identifier of L4 destination port
39489 * used for the given tunnel type. This field is valid for
39490 * specific tunnel types that use layer 4 (e.g. UDP)
39491 * transports for tunneling.
39493 uint16_t tunnel_dst_port_id;
39495 * This field represents the value of L4 destination port
39496 * identified by tunnel_dst_port_id. This field is valid for
39497 * specific tunnel types that use layer 4 (e.g. UDP)
39498 * transports for tunneling.
39499 * This field is in network byte order.
39501 * A value of 0 means that the destination port is not
39504 uint16_t tunnel_dst_port_val;
39505 uint8_t unused_0[3];
39507 * This field is used in Output records to indicate that the output
39508 * is completely written to RAM. This field should be read as '1'
39509 * to indicate that the output has been completely written.
39510 * When writing a command completion or response to an internal processor,
39511 * the order of writes has to be such that this field is written last.
39516 /******************************
39517 * hwrm_tunnel_dst_port_alloc *
39518 ******************************/
39521 /* hwrm_tunnel_dst_port_alloc_input (size:192b/24B) */
39522 struct hwrm_tunnel_dst_port_alloc_input {
39523 /* The HWRM command request type. */
39526 * The completion ring to send the completion event on. This should
39527 * be the NQ ID returned from the `nq_alloc` HWRM command.
39529 uint16_t cmpl_ring;
39531 * The sequence ID is used by the driver for tracking multiple
39532 * commands. This ID is treated as opaque data by the firmware and
39533 * the value is returned in the `hwrm_resp_hdr` upon completion.
39537 * The target ID of the command:
39538 * * 0x0-0xFFF8 - The function ID
39539 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
39540 * * 0xFFFD - Reserved for user-space HWRM interface
39543 uint16_t target_id;
39545 * A physical address pointer pointing to a host buffer that the
39546 * command's response data will be written. This can be either a host
39547 * physical address (HPA) or a guest physical address (GPA) and must
39548 * point to a physically contiguous block of memory.
39550 uint64_t resp_addr;
39552 uint8_t tunnel_type;
39553 /* Virtual eXtensible Local Area Network (VXLAN) */
39554 #define HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_VXLAN \
39556 /* Generic Network Virtualization Encapsulation (Geneve) */
39557 #define HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_GENEVE \
39559 /* IPV4 over virtual eXtensible Local Area Network (IPV4oVXLAN) */
39560 #define HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_VXLAN_V4 \
39562 /* Enhance Generic Routing Encapsulation (GRE version 1) inside IP datagram payload */
39563 #define HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_IPGRE_V1 \
39565 /* Use fixed layer 2 ether type of 0xFFFF */
39566 #define HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_L2_ETYPE \
39568 /* IPV6 over virtual eXtensible Local Area Network with GPE header (IPV6oVXLANGPE) */
39569 #define HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_VXLAN_GPE_V6 \
39571 #define HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_LAST \
39572 HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_VXLAN_GPE_V6
39575 * This field represents the value of L4 destination port used
39576 * for the given tunnel type. This field is valid for
39577 * specific tunnel types that use layer 4 (e.g. UDP)
39578 * transports for tunneling.
39580 * This field is in network byte order.
39582 * A value of 0 shall fail the command.
39584 uint16_t tunnel_dst_port_val;
39585 uint8_t unused_1[4];
39588 /* hwrm_tunnel_dst_port_alloc_output (size:128b/16B) */
39589 struct hwrm_tunnel_dst_port_alloc_output {
39590 /* The specific error status for the command. */
39591 uint16_t error_code;
39592 /* The HWRM command request type. */
39594 /* The sequence ID from the original command. */
39596 /* The length of the response data in number of bytes. */
39599 * Identifier of a tunnel L4 destination port value. Only applies to tunnel
39600 * types that has l4 destination port parameters.
39602 uint16_t tunnel_dst_port_id;
39603 uint8_t unused_0[5];
39605 * This field is used in Output records to indicate that the output
39606 * is completely written to RAM. This field should be read as '1'
39607 * to indicate that the output has been completely written.
39608 * When writing a command completion or response to an internal processor,
39609 * the order of writes has to be such that this field is written last.
39614 /*****************************
39615 * hwrm_tunnel_dst_port_free *
39616 *****************************/
39619 /* hwrm_tunnel_dst_port_free_input (size:192b/24B) */
39620 struct hwrm_tunnel_dst_port_free_input {
39621 /* The HWRM command request type. */
39624 * The completion ring to send the completion event on. This should
39625 * be the NQ ID returned from the `nq_alloc` HWRM command.
39627 uint16_t cmpl_ring;
39629 * The sequence ID is used by the driver for tracking multiple
39630 * commands. This ID is treated as opaque data by the firmware and
39631 * the value is returned in the `hwrm_resp_hdr` upon completion.
39635 * The target ID of the command:
39636 * * 0x0-0xFFF8 - The function ID
39637 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
39638 * * 0xFFFD - Reserved for user-space HWRM interface
39641 uint16_t target_id;
39643 * A physical address pointer pointing to a host buffer that the
39644 * command's response data will be written. This can be either a host
39645 * physical address (HPA) or a guest physical address (GPA) and must
39646 * point to a physically contiguous block of memory.
39648 uint64_t resp_addr;
39650 uint8_t tunnel_type;
39651 /* Virtual eXtensible Local Area Network (VXLAN) */
39652 #define HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_VXLAN \
39654 /* Generic Network Virtualization Encapsulation (Geneve) */
39655 #define HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_GENEVE \
39657 /* IPV4 over virtual eXtensible Local Area Network (IPV4oVXLAN) */
39658 #define HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_VXLAN_V4 \
39660 /* Enhance Generic Routing Encapsulation (GRE version 1) inside IP datagram payload */
39661 #define HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_IPGRE_V1 \
39663 /* Use fixed layer 2 ether type of 0xFFFF */
39664 #define HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_L2_ETYPE \
39666 /* IPV6 over virtual eXtensible Local Area Network with GPE header (IPV6oVXLANGPE) */
39667 #define HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_VXLAN_GPE_V6 \
39669 #define HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_LAST \
39670 HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_VXLAN_GPE_V6
39673 * Identifier of a tunnel L4 destination port value. Only applies to tunnel
39674 * types that has l4 destination port parameters.
39676 uint16_t tunnel_dst_port_id;
39677 uint8_t unused_1[4];
39680 /* hwrm_tunnel_dst_port_free_output (size:128b/16B) */
39681 struct hwrm_tunnel_dst_port_free_output {
39682 /* The specific error status for the command. */
39683 uint16_t error_code;
39684 /* The HWRM command request type. */
39686 /* The sequence ID from the original command. */
39688 /* The length of the response data in number of bytes. */
39690 uint8_t unused_1[7];
39692 * This field is used in Output records to indicate that the output
39693 * is completely written to RAM. This field should be read as '1'
39694 * to indicate that the output has been completely written.
39695 * When writing a command completion or response to an internal processor,
39696 * the order of writes has to be such that this field is written last.
39701 /* Periodic statistics context DMA to host. */
39702 /* ctx_hw_stats (size:1280b/160B) */
39703 struct ctx_hw_stats {
39704 /* Number of received unicast packets */
39705 uint64_t rx_ucast_pkts;
39706 /* Number of received multicast packets */
39707 uint64_t rx_mcast_pkts;
39708 /* Number of received broadcast packets */
39709 uint64_t rx_bcast_pkts;
39710 /* Number of discarded packets on receive path */
39711 uint64_t rx_discard_pkts;
39712 /* Number of packets on receive path with error */
39713 uint64_t rx_error_pkts;
39714 /* Number of received bytes for unicast traffic */
39715 uint64_t rx_ucast_bytes;
39716 /* Number of received bytes for multicast traffic */
39717 uint64_t rx_mcast_bytes;
39718 /* Number of received bytes for broadcast traffic */
39719 uint64_t rx_bcast_bytes;
39720 /* Number of transmitted unicast packets */
39721 uint64_t tx_ucast_pkts;
39722 /* Number of transmitted multicast packets */
39723 uint64_t tx_mcast_pkts;
39724 /* Number of transmitted broadcast packets */
39725 uint64_t tx_bcast_pkts;
39726 /* Number of packets on transmit path with error */
39727 uint64_t tx_error_pkts;
39728 /* Number of discarded packets on transmit path */
39729 uint64_t tx_discard_pkts;
39730 /* Number of transmitted bytes for unicast traffic */
39731 uint64_t tx_ucast_bytes;
39732 /* Number of transmitted bytes for multicast traffic */
39733 uint64_t tx_mcast_bytes;
39734 /* Number of transmitted bytes for broadcast traffic */
39735 uint64_t tx_bcast_bytes;
39736 /* Number of TPA packets */
39738 /* Number of TPA bytes */
39739 uint64_t tpa_bytes;
39740 /* Number of TPA events */
39741 uint64_t tpa_events;
39742 /* Number of TPA aborts */
39743 uint64_t tpa_aborts;
39747 * Extended periodic statistics context DMA to host. On cards that
39748 * support TPA v2, additional TPA related stats exist and can be retrieved
39749 * by DMA of ctx_hw_stats_ext, rather than legacy ctx_hw_stats structure.
39751 /* ctx_hw_stats_ext (size:1344b/168B) */
39752 struct ctx_hw_stats_ext {
39753 /* Number of received unicast packets */
39754 uint64_t rx_ucast_pkts;
39755 /* Number of received multicast packets */
39756 uint64_t rx_mcast_pkts;
39757 /* Number of received broadcast packets */
39758 uint64_t rx_bcast_pkts;
39759 /* Number of discarded packets on receive path */
39760 uint64_t rx_discard_pkts;
39761 /* Number of packets on receive path with error */
39762 uint64_t rx_error_pkts;
39763 /* Number of received bytes for unicast traffic */
39764 uint64_t rx_ucast_bytes;
39765 /* Number of received bytes for multicast traffic */
39766 uint64_t rx_mcast_bytes;
39767 /* Number of received bytes for broadcast traffic */
39768 uint64_t rx_bcast_bytes;
39769 /* Number of transmitted unicast packets */
39770 uint64_t tx_ucast_pkts;
39771 /* Number of transmitted multicast packets */
39772 uint64_t tx_mcast_pkts;
39773 /* Number of transmitted broadcast packets */
39774 uint64_t tx_bcast_pkts;
39775 /* Number of packets on transmit path with error */
39776 uint64_t tx_error_pkts;
39777 /* Number of discarded packets on transmit path */
39778 uint64_t tx_discard_pkts;
39779 /* Number of transmitted bytes for unicast traffic */
39780 uint64_t tx_ucast_bytes;
39781 /* Number of transmitted bytes for multicast traffic */
39782 uint64_t tx_mcast_bytes;
39783 /* Number of transmitted bytes for broadcast traffic */
39784 uint64_t tx_bcast_bytes;
39785 /* Number of TPA eligible packets */
39786 uint64_t rx_tpa_eligible_pkt;
39787 /* Number of TPA eligible bytes */
39788 uint64_t rx_tpa_eligible_bytes;
39789 /* Number of TPA packets */
39790 uint64_t rx_tpa_pkt;
39791 /* Number of TPA bytes */
39792 uint64_t rx_tpa_bytes;
39793 /* Number of TPA errors */
39794 uint64_t rx_tpa_errors;
39797 /* Periodic Engine statistics context DMA to host. */
39798 /* ctx_eng_stats (size:512b/64B) */
39799 struct ctx_eng_stats {
39801 * Count of data bytes into the Engine.
39802 * This includes any user supplied prefix,
39803 * but does not include any predefined
39806 uint64_t eng_bytes_in;
39807 /* Count of data bytes out of the Engine. */
39808 uint64_t eng_bytes_out;
39810 * Count, in 4-byte (dword) units, of bytes
39811 * that are input as auxiliary data.
39812 * This includes the aux_cmd data.
39814 uint64_t aux_bytes_in;
39816 * Count, in 4-byte (dword) units, of bytes
39817 * that are output as auxiliary data.
39818 * This count is the buffer space for aux_data
39819 * output provided in the RQE, not the actual
39822 uint64_t aux_bytes_out;
39823 /* Count of number of commands executed. */
39826 * Count of number of error commands.
39827 * These are the commands with a
39828 * non-zero status value.
39830 uint64_t error_commands;
39832 * Compression/Encryption Engine usage,
39833 * the unit is count of clock cycles
39835 uint64_t cce_engine_usage;
39837 * De-Compression/De-cryption Engine usage,
39838 * the unit is count of clock cycles
39840 uint64_t cdd_engine_usage;
39843 /***********************
39844 * hwrm_stat_ctx_alloc *
39845 ***********************/
39848 /* hwrm_stat_ctx_alloc_input (size:256b/32B) */
39849 struct hwrm_stat_ctx_alloc_input {
39850 /* The HWRM command request type. */
39853 * The completion ring to send the completion event on. This should
39854 * be the NQ ID returned from the `nq_alloc` HWRM command.
39856 uint16_t cmpl_ring;
39858 * The sequence ID is used by the driver for tracking multiple
39859 * commands. This ID is treated as opaque data by the firmware and
39860 * the value is returned in the `hwrm_resp_hdr` upon completion.
39864 * The target ID of the command:
39865 * * 0x0-0xFFF8 - The function ID
39866 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
39867 * * 0xFFFD - Reserved for user-space HWRM interface
39870 uint16_t target_id;
39872 * A physical address pointer pointing to a host buffer that the
39873 * command's response data will be written. This can be either a host
39874 * physical address (HPA) or a guest physical address (GPA) and must
39875 * point to a physically contiguous block of memory.
39877 uint64_t resp_addr;
39879 * This is the address for statistic block.
39880 * > For new versions of the chip, this address should be 128B
39883 uint64_t stats_dma_addr;
39885 * The statistic block update period in ms.
39886 * e.g. 250ms, 500ms, 750ms, 1000ms.
39887 * If update_period_ms is 0, then the stats update
39888 * shall be never done and the DMA address shall not be used.
39889 * In this case, the stat block can only be read by
39890 * hwrm_stat_ctx_query command.
39891 * On Ethernet/L2 based devices:
39892 * if tpa v2 supported (hwrm_vnic_qcaps[max_aggs_supported]>0),
39893 * ctx_hw_stats_ext is used for DMA,
39895 * ctx_hw_stats is used for DMA.
39897 uint32_t update_period_ms;
39899 * This field is used to specify statistics context specific
39900 * configuration flags.
39902 uint8_t stat_ctx_flags;
39904 * When this bit is set to '1', the statistics context shall be
39905 * allocated for RoCE traffic only. In this case, traffic other
39906 * than offloaded RoCE traffic shall not be included in this
39907 * statistic context.
39908 * When this bit is set to '0', the statistics context shall be
39909 * used for network traffic or engine traffic.
39911 #define HWRM_STAT_CTX_ALLOC_INPUT_STAT_CTX_FLAGS_ROCE UINT32_C(0x1)
39914 * This is the size of the structure (ctx_hw_stats or
39915 * ctx_hw_stats_ext) that the driver has allocated to be used
39916 * for the periodic DMA updates.
39918 uint16_t stats_dma_length;
39921 /* hwrm_stat_ctx_alloc_output (size:128b/16B) */
39922 struct hwrm_stat_ctx_alloc_output {
39923 /* The specific error status for the command. */
39924 uint16_t error_code;
39925 /* The HWRM command request type. */
39927 /* The sequence ID from the original command. */
39929 /* The length of the response data in number of bytes. */
39931 /* This is the statistics context ID value. */
39932 uint32_t stat_ctx_id;
39933 uint8_t unused_0[3];
39935 * This field is used in Output records to indicate that the output
39936 * is completely written to RAM. This field should be read as '1'
39937 * to indicate that the output has been completely written.
39938 * When writing a command completion or response to an internal processor,
39939 * the order of writes has to be such that this field is written last.
39944 /**********************
39945 * hwrm_stat_ctx_free *
39946 **********************/
39949 /* hwrm_stat_ctx_free_input (size:192b/24B) */
39950 struct hwrm_stat_ctx_free_input {
39951 /* The HWRM command request type. */
39954 * The completion ring to send the completion event on. This should
39955 * be the NQ ID returned from the `nq_alloc` HWRM command.
39957 uint16_t cmpl_ring;
39959 * The sequence ID is used by the driver for tracking multiple
39960 * commands. This ID is treated as opaque data by the firmware and
39961 * the value is returned in the `hwrm_resp_hdr` upon completion.
39965 * The target ID of the command:
39966 * * 0x0-0xFFF8 - The function ID
39967 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
39968 * * 0xFFFD - Reserved for user-space HWRM interface
39971 uint16_t target_id;
39973 * A physical address pointer pointing to a host buffer that the
39974 * command's response data will be written. This can be either a host
39975 * physical address (HPA) or a guest physical address (GPA) and must
39976 * point to a physically contiguous block of memory.
39978 uint64_t resp_addr;
39979 /* ID of the statistics context that is being queried. */
39980 uint32_t stat_ctx_id;
39981 uint8_t unused_0[4];
39984 /* hwrm_stat_ctx_free_output (size:128b/16B) */
39985 struct hwrm_stat_ctx_free_output {
39986 /* The specific error status for the command. */
39987 uint16_t error_code;
39988 /* The HWRM command request type. */
39990 /* The sequence ID from the original command. */
39992 /* The length of the response data in number of bytes. */
39994 /* This is the statistics context ID value. */
39995 uint32_t stat_ctx_id;
39996 uint8_t unused_0[3];
39998 * This field is used in Output records to indicate that the output
39999 * is completely written to RAM. This field should be read as '1'
40000 * to indicate that the output has been completely written.
40001 * When writing a command completion or response to an internal processor,
40002 * the order of writes has to be such that this field is written last.
40007 /***********************
40008 * hwrm_stat_ctx_query *
40009 ***********************/
40012 /* hwrm_stat_ctx_query_input (size:192b/24B) */
40013 struct hwrm_stat_ctx_query_input {
40014 /* The HWRM command request type. */
40017 * The completion ring to send the completion event on. This should
40018 * be the NQ ID returned from the `nq_alloc` HWRM command.
40020 uint16_t cmpl_ring;
40022 * The sequence ID is used by the driver for tracking multiple
40023 * commands. This ID is treated as opaque data by the firmware and
40024 * the value is returned in the `hwrm_resp_hdr` upon completion.
40028 * The target ID of the command:
40029 * * 0x0-0xFFF8 - The function ID
40030 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
40031 * * 0xFFFD - Reserved for user-space HWRM interface
40034 uint16_t target_id;
40036 * A physical address pointer pointing to a host buffer that the
40037 * command's response data will be written. This can be either a host
40038 * physical address (HPA) or a guest physical address (GPA) and must
40039 * point to a physically contiguous block of memory.
40041 uint64_t resp_addr;
40042 /* ID of the statistics context that is being queried. */
40043 uint32_t stat_ctx_id;
40046 * This bit is set to 1 when request is for a counter mask,
40047 * representing the width of each of the stats counters, rather
40048 * than counters themselves.
40050 #define HWRM_STAT_CTX_QUERY_INPUT_FLAGS_COUNTER_MASK UINT32_C(0x1)
40051 uint8_t unused_0[3];
40054 /* hwrm_stat_ctx_query_output (size:1408b/176B) */
40055 struct hwrm_stat_ctx_query_output {
40056 /* The specific error status for the command. */
40057 uint16_t error_code;
40058 /* The HWRM command request type. */
40060 /* The sequence ID from the original command. */
40062 /* The length of the response data in number of bytes. */
40064 /* Number of transmitted unicast packets */
40065 uint64_t tx_ucast_pkts;
40066 /* Number of transmitted multicast packets */
40067 uint64_t tx_mcast_pkts;
40068 /* Number of transmitted broadcast packets */
40069 uint64_t tx_bcast_pkts;
40070 /* Number of transmitted packets with error */
40071 uint64_t tx_err_pkts;
40072 /* Number of dropped packets on transmit path */
40073 uint64_t tx_drop_pkts;
40074 /* Number of transmitted bytes for unicast traffic */
40075 uint64_t tx_ucast_bytes;
40076 /* Number of transmitted bytes for multicast traffic */
40077 uint64_t tx_mcast_bytes;
40078 /* Number of transmitted bytes for broadcast traffic */
40079 uint64_t tx_bcast_bytes;
40080 /* Number of received unicast packets */
40081 uint64_t rx_ucast_pkts;
40082 /* Number of received multicast packets */
40083 uint64_t rx_mcast_pkts;
40084 /* Number of received broadcast packets */
40085 uint64_t rx_bcast_pkts;
40086 /* Number of received packets with error */
40087 uint64_t rx_err_pkts;
40088 /* Number of dropped packets on receive path */
40089 uint64_t rx_drop_pkts;
40090 /* Number of received bytes for unicast traffic */
40091 uint64_t rx_ucast_bytes;
40092 /* Number of received bytes for multicast traffic */
40093 uint64_t rx_mcast_bytes;
40094 /* Number of received bytes for broadcast traffic */
40095 uint64_t rx_bcast_bytes;
40096 /* Number of aggregated unicast packets */
40097 uint64_t rx_agg_pkts;
40098 /* Number of aggregated unicast bytes */
40099 uint64_t rx_agg_bytes;
40100 /* Number of aggregation events */
40101 uint64_t rx_agg_events;
40102 /* Number of aborted aggregations */
40103 uint64_t rx_agg_aborts;
40104 uint8_t unused_0[7];
40106 * This field is used in Output records to indicate that the output
40107 * is completely written to RAM. This field should be read as '1'
40108 * to indicate that the output has been completely written.
40109 * When writing a command completion or response to an internal processor,
40110 * the order of writes has to be such that this field is written last.
40115 /***************************
40116 * hwrm_stat_ext_ctx_query *
40117 ***************************/
40120 /* hwrm_stat_ext_ctx_query_input (size:192b/24B) */
40121 struct hwrm_stat_ext_ctx_query_input {
40122 /* The HWRM command request type. */
40125 * The completion ring to send the completion event on. This should
40126 * be the NQ ID returned from the `nq_alloc` HWRM command.
40128 uint16_t cmpl_ring;
40130 * The sequence ID is used by the driver for tracking multiple
40131 * commands. This ID is treated as opaque data by the firmware and
40132 * the value is returned in the `hwrm_resp_hdr` upon completion.
40136 * The target ID of the command:
40137 * * 0x0-0xFFF8 - The function ID
40138 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
40139 * * 0xFFFD - Reserved for user-space HWRM interface
40142 uint16_t target_id;
40144 * A physical address pointer pointing to a host buffer that the
40145 * command's response data will be written. This can be either a host
40146 * physical address (HPA) or a guest physical address (GPA) and must
40147 * point to a physically contiguous block of memory.
40149 uint64_t resp_addr;
40150 /* ID of the extended statistics context that is being queried. */
40151 uint32_t stat_ctx_id;
40154 * This bit is set to 1 when request is for a counter mask,
40155 * representing the width of each of the stats counters, rather
40156 * than counters themselves.
40158 #define HWRM_STAT_EXT_CTX_QUERY_INPUT_FLAGS_COUNTER_MASK \
40160 uint8_t unused_0[3];
40163 /* hwrm_stat_ext_ctx_query_output (size:1472b/184B) */
40164 struct hwrm_stat_ext_ctx_query_output {
40165 /* The specific error status for the command. */
40166 uint16_t error_code;
40167 /* The HWRM command request type. */
40169 /* The sequence ID from the original command. */
40171 /* The length of the response data in number of bytes. */
40173 /* Number of received unicast packets */
40174 uint64_t rx_ucast_pkts;
40175 /* Number of received multicast packets */
40176 uint64_t rx_mcast_pkts;
40177 /* Number of received broadcast packets */
40178 uint64_t rx_bcast_pkts;
40179 /* Number of discarded packets on receive path */
40180 uint64_t rx_discard_pkts;
40181 /* Number of packets on receive path with error */
40182 uint64_t rx_error_pkts;
40183 /* Number of received bytes for unicast traffic */
40184 uint64_t rx_ucast_bytes;
40185 /* Number of received bytes for multicast traffic */
40186 uint64_t rx_mcast_bytes;
40187 /* Number of received bytes for broadcast traffic */
40188 uint64_t rx_bcast_bytes;
40189 /* Number of transmitted unicast packets */
40190 uint64_t tx_ucast_pkts;
40191 /* Number of transmitted multicast packets */
40192 uint64_t tx_mcast_pkts;
40193 /* Number of transmitted broadcast packets */
40194 uint64_t tx_bcast_pkts;
40195 /* Number of packets on transmit path with error */
40196 uint64_t tx_error_pkts;
40197 /* Number of discarded packets on transmit path */
40198 uint64_t tx_discard_pkts;
40199 /* Number of transmitted bytes for unicast traffic */
40200 uint64_t tx_ucast_bytes;
40201 /* Number of transmitted bytes for multicast traffic */
40202 uint64_t tx_mcast_bytes;
40203 /* Number of transmitted bytes for broadcast traffic */
40204 uint64_t tx_bcast_bytes;
40205 /* Number of TPA eligible packets */
40206 uint64_t rx_tpa_eligible_pkt;
40207 /* Number of TPA eligible bytes */
40208 uint64_t rx_tpa_eligible_bytes;
40209 /* Number of TPA packets */
40210 uint64_t rx_tpa_pkt;
40211 /* Number of TPA bytes */
40212 uint64_t rx_tpa_bytes;
40213 /* Number of TPA errors */
40214 uint64_t rx_tpa_errors;
40215 uint8_t unused_0[7];
40217 * This field is used in Output records to indicate that the output
40218 * is completely written to RAM. This field should be read as '1'
40219 * to indicate that the output has been completely written.
40220 * When writing a command completion or response to an internal processor,
40221 * the order of writes has to be such that this field is written last.
40226 /***************************
40227 * hwrm_stat_ctx_eng_query *
40228 ***************************/
40231 /* hwrm_stat_ctx_eng_query_input (size:192b/24B) */
40232 struct hwrm_stat_ctx_eng_query_input {
40233 /* The HWRM command request type. */
40236 * The completion ring to send the completion event on. This should
40237 * be the NQ ID returned from the `nq_alloc` HWRM command.
40239 uint16_t cmpl_ring;
40241 * The sequence ID is used by the driver for tracking multiple
40242 * commands. This ID is treated as opaque data by the firmware and
40243 * the value is returned in the `hwrm_resp_hdr` upon completion.
40247 * The target ID of the command:
40248 * * 0x0-0xFFF8 - The function ID
40249 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
40250 * * 0xFFFD - Reserved for user-space HWRM interface
40253 uint16_t target_id;
40255 * A physical address pointer pointing to a host buffer that the
40256 * command's response data will be written. This can be either a host
40257 * physical address (HPA) or a guest physical address (GPA) and must
40258 * point to a physically contiguous block of memory.
40260 uint64_t resp_addr;
40261 /* ID of the statistics context that is being queried. */
40262 uint32_t stat_ctx_id;
40263 uint8_t unused_0[4];
40266 /* hwrm_stat_ctx_eng_query_output (size:640b/80B) */
40267 struct hwrm_stat_ctx_eng_query_output {
40268 /* The specific error status for the command. */
40269 uint16_t error_code;
40270 /* The HWRM command request type. */
40272 /* The sequence ID from the original command. */
40274 /* The length of the response data in number of bytes. */
40277 * Count of data bytes into the Engine.
40278 * This includes any user supplied prefix,
40279 * but does not include any predefined
40282 uint64_t eng_bytes_in;
40283 /* Count of data bytes out of the Engine. */
40284 uint64_t eng_bytes_out;
40286 * Count, in 4-byte (dword) units, of bytes
40287 * that are input as auxiliary data.
40288 * This includes the aux_cmd data.
40290 uint64_t aux_bytes_in;
40292 * Count, in 4-byte (dword) units, of bytes
40293 * that are output as auxiliary data.
40294 * This count is the buffer space for aux_data
40295 * output provided in the RQE, not the actual
40298 uint64_t aux_bytes_out;
40299 /* Count of number of commands executed. */
40302 * Count of number of error commands.
40303 * These are the commands with a
40304 * non-zero status value.
40306 uint64_t error_commands;
40308 * Compression/Encryption Engine usage,
40309 * the unit is count of clock cycles
40311 uint64_t cce_engine_usage;
40313 * De-Compression/De-cryption Engine usage,
40314 * the unit is count of clock cycles
40316 uint64_t cdd_engine_usage;
40317 uint8_t unused_0[7];
40319 * This field is used in Output records to indicate that the output
40320 * is completely written to RAM. This field should be read as '1'
40321 * to indicate that the output has been completely written.
40322 * When writing a command completion or response to an internal processor,
40323 * the order of writes has to be such that this field is written last.
40328 /***************************
40329 * hwrm_stat_ctx_clr_stats *
40330 ***************************/
40333 /* hwrm_stat_ctx_clr_stats_input (size:192b/24B) */
40334 struct hwrm_stat_ctx_clr_stats_input {
40335 /* The HWRM command request type. */
40338 * The completion ring to send the completion event on. This should
40339 * be the NQ ID returned from the `nq_alloc` HWRM command.
40341 uint16_t cmpl_ring;
40343 * The sequence ID is used by the driver for tracking multiple
40344 * commands. This ID is treated as opaque data by the firmware and
40345 * the value is returned in the `hwrm_resp_hdr` upon completion.
40349 * The target ID of the command:
40350 * * 0x0-0xFFF8 - The function ID
40351 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
40352 * * 0xFFFD - Reserved for user-space HWRM interface
40355 uint16_t target_id;
40357 * A physical address pointer pointing to a host buffer that the
40358 * command's response data will be written. This can be either a host
40359 * physical address (HPA) or a guest physical address (GPA) and must
40360 * point to a physically contiguous block of memory.
40362 uint64_t resp_addr;
40363 /* ID of the statistics context that is being queried. */
40364 uint32_t stat_ctx_id;
40365 uint8_t unused_0[4];
40368 /* hwrm_stat_ctx_clr_stats_output (size:128b/16B) */
40369 struct hwrm_stat_ctx_clr_stats_output {
40370 /* The specific error status for the command. */
40371 uint16_t error_code;
40372 /* The HWRM command request type. */
40374 /* The sequence ID from the original command. */
40376 /* The length of the response data in number of bytes. */
40378 uint8_t unused_0[7];
40380 * This field is used in Output records to indicate that the output
40381 * is completely written to RAM. This field should be read as '1'
40382 * to indicate that the output has been completely written.
40383 * When writing a command completion or response to an internal processor,
40384 * the order of writes has to be such that this field is written last.
40389 /********************
40390 * hwrm_pcie_qstats *
40391 ********************/
40394 /* hwrm_pcie_qstats_input (size:256b/32B) */
40395 struct hwrm_pcie_qstats_input {
40396 /* The HWRM command request type. */
40399 * The completion ring to send the completion event on. This should
40400 * be the NQ ID returned from the `nq_alloc` HWRM command.
40402 uint16_t cmpl_ring;
40404 * The sequence ID is used by the driver for tracking multiple
40405 * commands. This ID is treated as opaque data by the firmware and
40406 * the value is returned in the `hwrm_resp_hdr` upon completion.
40410 * The target ID of the command:
40411 * * 0x0-0xFFF8 - The function ID
40412 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
40413 * * 0xFFFD - Reserved for user-space HWRM interface
40416 uint16_t target_id;
40418 * A physical address pointer pointing to a host buffer that the
40419 * command's response data will be written. This can be either a host
40420 * physical address (HPA) or a guest physical address (GPA) and must
40421 * point to a physically contiguous block of memory.
40423 uint64_t resp_addr;
40425 * The size of PCIe statistics block in bytes.
40426 * Firmware will DMA the PCIe statistics to
40427 * the host with this field size in the response.
40429 uint16_t pcie_stat_size;
40430 uint8_t unused_0[6];
40432 * This is the host address where
40433 * PCIe statistics will be stored
40435 uint64_t pcie_stat_host_addr;
40438 /* hwrm_pcie_qstats_output (size:128b/16B) */
40439 struct hwrm_pcie_qstats_output {
40440 /* The specific error status for the command. */
40441 uint16_t error_code;
40442 /* The HWRM command request type. */
40444 /* The sequence ID from the original command. */
40446 /* The length of the response data in number of bytes. */
40448 /* The size of PCIe statistics block in bytes. */
40449 uint16_t pcie_stat_size;
40450 uint8_t unused_0[5];
40452 * This field is used in Output records to indicate that the output
40453 * is completely written to RAM. This field should be read as '1'
40454 * to indicate that the output has been completely written.
40455 * When writing a command completion or response to an internal processor,
40456 * the order of writes has to be such that this field is written last.
40461 /* PCIe Statistics Formats */
40462 /* pcie_ctx_hw_stats (size:768b/96B) */
40463 struct pcie_ctx_hw_stats {
40464 /* Number of physical layer receiver errors */
40465 uint64_t pcie_pl_signal_integrity;
40466 /* Number of DLLP CRC errors detected by Data Link Layer */
40467 uint64_t pcie_dl_signal_integrity;
40469 * Number of TLP LCRC and sequence number errors detected
40470 * by Data Link Layer
40472 uint64_t pcie_tl_signal_integrity;
40473 /* Number of times LTSSM entered Recovery state */
40474 uint64_t pcie_link_integrity;
40475 /* Report number of TLP bits that have been transmitted in Mbps */
40476 uint64_t pcie_tx_traffic_rate;
40477 /* Report number of TLP bits that have been received in Mbps */
40478 uint64_t pcie_rx_traffic_rate;
40479 /* Number of DLLP bytes that have been transmitted */
40480 uint64_t pcie_tx_dllp_statistics;
40481 /* Number of DLLP bytes that have been received */
40482 uint64_t pcie_rx_dllp_statistics;
40484 * Number of times spent in each phase of gen3
40487 uint64_t pcie_equalization_time;
40488 /* Records the last 16 transitions of the LTSSM */
40489 uint32_t pcie_ltssm_histogram[4];
40491 * Record the last 8 reasons on why LTSSM transitioned
40494 uint64_t pcie_recovery_histogram;
40497 /**********************
40498 * hwrm_exec_fwd_resp *
40499 **********************/
40502 /* hwrm_exec_fwd_resp_input (size:1024b/128B) */
40503 struct hwrm_exec_fwd_resp_input {
40504 /* The HWRM command request type. */
40507 * The completion ring to send the completion event on. This should
40508 * be the NQ ID returned from the `nq_alloc` HWRM command.
40510 uint16_t cmpl_ring;
40512 * The sequence ID is used by the driver for tracking multiple
40513 * commands. This ID is treated as opaque data by the firmware and
40514 * the value is returned in the `hwrm_resp_hdr` upon completion.
40518 * The target ID of the command:
40519 * * 0x0-0xFFF8 - The function ID
40520 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
40521 * * 0xFFFD - Reserved for user-space HWRM interface
40524 uint16_t target_id;
40526 * A physical address pointer pointing to a host buffer that the
40527 * command's response data will be written. This can be either a host
40528 * physical address (HPA) or a guest physical address (GPA) and must
40529 * point to a physically contiguous block of memory.
40531 uint64_t resp_addr;
40533 * This is an encapsulated request. This request should
40534 * be executed by the HWRM and the response should be
40535 * provided in the response buffer inside the encapsulated
40538 uint32_t encap_request[26];
40540 * This value indicates the target id of the response to
40541 * the encapsulated request.
40542 * 0x0 - 0xFFF8 - Used for function ids
40543 * 0xFFF8 - 0xFFFE - Reserved for internal processors
40546 uint16_t encap_resp_target_id;
40547 uint8_t unused_0[6];
40550 /* hwrm_exec_fwd_resp_output (size:128b/16B) */
40551 struct hwrm_exec_fwd_resp_output {
40552 /* The specific error status for the command. */
40553 uint16_t error_code;
40554 /* The HWRM command request type. */
40556 /* The sequence ID from the original command. */
40558 /* The length of the response data in number of bytes. */
40560 uint8_t unused_0[7];
40562 * This field is used in Output records to indicate that the output
40563 * is completely written to RAM. This field should be read as '1'
40564 * to indicate that the output has been completely written.
40565 * When writing a command completion or response to an internal processor,
40566 * the order of writes has to be such that this field is written last.
40571 /************************
40572 * hwrm_reject_fwd_resp *
40573 ************************/
40576 /* hwrm_reject_fwd_resp_input (size:1024b/128B) */
40577 struct hwrm_reject_fwd_resp_input {
40578 /* The HWRM command request type. */
40581 * The completion ring to send the completion event on. This should
40582 * be the NQ ID returned from the `nq_alloc` HWRM command.
40584 uint16_t cmpl_ring;
40586 * The sequence ID is used by the driver for tracking multiple
40587 * commands. This ID is treated as opaque data by the firmware and
40588 * the value is returned in the `hwrm_resp_hdr` upon completion.
40592 * The target ID of the command:
40593 * * 0x0-0xFFF8 - The function ID
40594 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
40595 * * 0xFFFD - Reserved for user-space HWRM interface
40598 uint16_t target_id;
40600 * A physical address pointer pointing to a host buffer that the
40601 * command's response data will be written. This can be either a host
40602 * physical address (HPA) or a guest physical address (GPA) and must
40603 * point to a physically contiguous block of memory.
40605 uint64_t resp_addr;
40607 * This is an encapsulated request. This request should
40608 * be rejected by the HWRM and the error response should be
40609 * provided in the response buffer inside the encapsulated
40612 uint32_t encap_request[26];
40614 * This value indicates the target id of the response to
40615 * the encapsulated request.
40616 * 0x0 - 0xFFF8 - Used for function ids
40617 * 0xFFF8 - 0xFFFE - Reserved for internal processors
40620 uint16_t encap_resp_target_id;
40621 uint8_t unused_0[6];
40624 /* hwrm_reject_fwd_resp_output (size:128b/16B) */
40625 struct hwrm_reject_fwd_resp_output {
40626 /* The specific error status for the command. */
40627 uint16_t error_code;
40628 /* The HWRM command request type. */
40630 /* The sequence ID from the original command. */
40632 /* The length of the response data in number of bytes. */
40634 uint8_t unused_0[7];
40636 * This field is used in Output records to indicate that the output
40637 * is completely written to RAM. This field should be read as '1'
40638 * to indicate that the output has been completely written.
40639 * When writing a command completion or response to an internal processor,
40640 * the order of writes has to be such that this field is written last.
40650 /* hwrm_fwd_resp_input (size:1024b/128B) */
40651 struct hwrm_fwd_resp_input {
40652 /* The HWRM command request type. */
40655 * The completion ring to send the completion event on. This should
40656 * be the NQ ID returned from the `nq_alloc` HWRM command.
40658 uint16_t cmpl_ring;
40660 * The sequence ID is used by the driver for tracking multiple
40661 * commands. This ID is treated as opaque data by the firmware and
40662 * the value is returned in the `hwrm_resp_hdr` upon completion.
40666 * The target ID of the command:
40667 * * 0x0-0xFFF8 - The function ID
40668 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
40669 * * 0xFFFD - Reserved for user-space HWRM interface
40672 uint16_t target_id;
40674 * A physical address pointer pointing to a host buffer that the
40675 * command's response data will be written. This can be either a host
40676 * physical address (HPA) or a guest physical address (GPA) and must
40677 * point to a physically contiguous block of memory.
40679 uint64_t resp_addr;
40681 * This value indicates the target id of the encapsulated
40683 * 0x0 - 0xFFF8 - Used for function ids
40684 * 0xFFF8 - 0xFFFE - Reserved for internal processors
40687 uint16_t encap_resp_target_id;
40689 * This value indicates the completion ring the encapsulated
40690 * response will be optionally completed on. If the value is
40691 * -1, then no CR completion shall be generated for the
40692 * encapsulated response. Any other value must be a
40693 * valid CR ring_id value. If a valid encap_resp_cmpl_ring
40694 * is provided, then a CR completion shall be generated for
40695 * the encapsulated response.
40697 uint16_t encap_resp_cmpl_ring;
40698 /* This field indicates the length of encapsulated response. */
40699 uint16_t encap_resp_len;
40703 * This is the host address where the encapsulated response
40705 * This area must be 16B aligned and must be cleared to zero
40706 * before the original request is made.
40708 uint64_t encap_resp_addr;
40709 /* This is an encapsulated response. */
40710 uint32_t encap_resp[24];
40713 /* hwrm_fwd_resp_output (size:128b/16B) */
40714 struct hwrm_fwd_resp_output {
40715 /* The specific error status for the command. */
40716 uint16_t error_code;
40717 /* The HWRM command request type. */
40719 /* The sequence ID from the original command. */
40721 /* The length of the response data in number of bytes. */
40723 uint8_t unused_0[7];
40725 * This field is used in Output records to indicate that the output
40726 * is completely written to RAM. This field should be read as '1'
40727 * to indicate that the output has been completely written.
40728 * When writing a command completion or response to an internal processor,
40729 * the order of writes has to be such that this field is written last.
40734 /*****************************
40735 * hwrm_fwd_async_event_cmpl *
40736 *****************************/
40739 /* hwrm_fwd_async_event_cmpl_input (size:320b/40B) */
40740 struct hwrm_fwd_async_event_cmpl_input {
40741 /* The HWRM command request type. */
40744 * The completion ring to send the completion event on. This should
40745 * be the NQ ID returned from the `nq_alloc` HWRM command.
40747 uint16_t cmpl_ring;
40749 * The sequence ID is used by the driver for tracking multiple
40750 * commands. This ID is treated as opaque data by the firmware and
40751 * the value is returned in the `hwrm_resp_hdr` upon completion.
40755 * The target ID of the command:
40756 * * 0x0-0xFFF8 - The function ID
40757 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
40758 * * 0xFFFD - Reserved for user-space HWRM interface
40761 uint16_t target_id;
40763 * A physical address pointer pointing to a host buffer that the
40764 * command's response data will be written. This can be either a host
40765 * physical address (HPA) or a guest physical address (GPA) and must
40766 * point to a physically contiguous block of memory.
40768 uint64_t resp_addr;
40770 * This value indicates the target id of the encapsulated
40771 * asynchronous event.
40772 * 0x0 - 0xFFF8 - Used for function ids
40773 * 0xFFF8 - 0xFFFE - Reserved for internal processors
40774 * 0xFFFF - Broadcast to all children VFs (only applicable when
40775 * a PF is the requester)
40777 uint16_t encap_async_event_target_id;
40778 uint8_t unused_0[6];
40779 /* This is an encapsulated asynchronous event completion. */
40780 uint32_t encap_async_event_cmpl[4];
40783 /* hwrm_fwd_async_event_cmpl_output (size:128b/16B) */
40784 struct hwrm_fwd_async_event_cmpl_output {
40785 /* The specific error status for the command. */
40786 uint16_t error_code;
40787 /* The HWRM command request type. */
40789 /* The sequence ID from the original command. */
40791 /* The length of the response data in number of bytes. */
40793 uint8_t unused_0[7];
40795 * This field is used in Output records to indicate that the output
40796 * is completely written to RAM. This field should be read as '1'
40797 * to indicate that the output has been completely written.
40798 * When writing a command completion or response to an internal processor,
40799 * the order of writes has to be such that this field is written last.
40804 /**************************
40805 * hwrm_nvm_raw_write_blk *
40806 **************************/
40809 /* hwrm_nvm_raw_write_blk_input (size:256b/32B) */
40810 struct hwrm_nvm_raw_write_blk_input {
40811 /* The HWRM command request type. */
40814 * The completion ring to send the completion event on. This should
40815 * be the NQ ID returned from the `nq_alloc` HWRM command.
40817 uint16_t cmpl_ring;
40819 * The sequence ID is used by the driver for tracking multiple
40820 * commands. This ID is treated as opaque data by the firmware and
40821 * the value is returned in the `hwrm_resp_hdr` upon completion.
40825 * The target ID of the command:
40826 * * 0x0-0xFFF8 - The function ID
40827 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
40828 * * 0xFFFD - Reserved for user-space HWRM interface
40831 uint16_t target_id;
40833 * A physical address pointer pointing to a host buffer that the
40834 * command's response data will be written. This can be either a host
40835 * physical address (HPA) or a guest physical address (GPA) and must
40836 * point to a physically contiguous block of memory.
40838 uint64_t resp_addr;
40840 * 64-bit Host Source Address.
40841 * This is the location of the source data to be written.
40843 uint64_t host_src_addr;
40845 * 32-bit Destination Address.
40846 * This is the NVRAM byte-offset where the source data will be written to.
40848 uint32_t dest_addr;
40849 /* Length of data to be written, in bytes. */
40853 /* hwrm_nvm_raw_write_blk_output (size:128b/16B) */
40854 struct hwrm_nvm_raw_write_blk_output {
40855 /* The specific error status for the command. */
40856 uint16_t error_code;
40857 /* The HWRM command request type. */
40859 /* The sequence ID from the original command. */
40861 /* The length of the response data in number of bytes. */
40863 uint8_t unused_0[7];
40865 * This field is used in Output records to indicate that the output
40866 * is completely written to RAM. This field should be read as '1'
40867 * to indicate that the output has been completely written.
40868 * When writing a command completion or response to an internal processor,
40869 * the order of writes has to be such that this field is written last.
40879 /* hwrm_nvm_read_input (size:320b/40B) */
40880 struct hwrm_nvm_read_input {
40881 /* The HWRM command request type. */
40884 * The completion ring to send the completion event on. This should
40885 * be the NQ ID returned from the `nq_alloc` HWRM command.
40887 uint16_t cmpl_ring;
40889 * The sequence ID is used by the driver for tracking multiple
40890 * commands. This ID is treated as opaque data by the firmware and
40891 * the value is returned in the `hwrm_resp_hdr` upon completion.
40895 * The target ID of the command:
40896 * * 0x0-0xFFF8 - The function ID
40897 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
40898 * * 0xFFFD - Reserved for user-space HWRM interface
40901 uint16_t target_id;
40903 * A physical address pointer pointing to a host buffer that the
40904 * command's response data will be written. This can be either a host
40905 * physical address (HPA) or a guest physical address (GPA) and must
40906 * point to a physically contiguous block of memory.
40908 uint64_t resp_addr;
40910 * 64-bit Host Destination Address.
40911 * This is the host address where the data will be written to.
40913 uint64_t host_dest_addr;
40914 /* The 0-based index of the directory entry. */
40916 uint8_t unused_0[2];
40917 /* The NVRAM byte-offset to read from. */
40919 /* The length of the data to be read, in bytes. */
40921 uint8_t unused_1[4];
40924 /* hwrm_nvm_read_output (size:128b/16B) */
40925 struct hwrm_nvm_read_output {
40926 /* The specific error status for the command. */
40927 uint16_t error_code;
40928 /* The HWRM command request type. */
40930 /* The sequence ID from the original command. */
40932 /* The length of the response data in number of bytes. */
40934 uint8_t unused_0[7];
40936 * This field is used in Output records to indicate that the output
40937 * is completely written to RAM. This field should be read as '1'
40938 * to indicate that the output has been completely written.
40939 * When writing a command completion or response to an internal processor,
40940 * the order of writes has to be such that this field is written last.
40945 /*********************
40946 * hwrm_nvm_raw_dump *
40947 *********************/
40950 /* hwrm_nvm_raw_dump_input (size:256b/32B) */
40951 struct hwrm_nvm_raw_dump_input {
40952 /* The HWRM command request type. */
40955 * The completion ring to send the completion event on. This should
40956 * be the NQ ID returned from the `nq_alloc` HWRM command.
40958 uint16_t cmpl_ring;
40960 * The sequence ID is used by the driver for tracking multiple
40961 * commands. This ID is treated as opaque data by the firmware and
40962 * the value is returned in the `hwrm_resp_hdr` upon completion.
40966 * The target ID of the command:
40967 * * 0x0-0xFFF8 - The function ID
40968 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
40969 * * 0xFFFD - Reserved for user-space HWRM interface
40972 uint16_t target_id;
40974 * A physical address pointer pointing to a host buffer that the
40975 * command's response data will be written. This can be either a host
40976 * physical address (HPA) or a guest physical address (GPA) and must
40977 * point to a physically contiguous block of memory.
40979 uint64_t resp_addr;
40981 * 64-bit Host Destination Address.
40982 * This is the host address where the data will be written to.
40984 uint64_t host_dest_addr;
40985 /* 32-bit NVRAM byte-offset to read from. */
40987 /* Total length of NVRAM contents to be read, in bytes. */
40991 /* hwrm_nvm_raw_dump_output (size:128b/16B) */
40992 struct hwrm_nvm_raw_dump_output {
40993 /* The specific error status for the command. */
40994 uint16_t error_code;
40995 /* The HWRM command request type. */
40997 /* The sequence ID from the original command. */
40999 /* The length of the response data in number of bytes. */
41001 uint8_t unused_0[7];
41003 * This field is used in Output records to indicate that the output
41004 * is completely written to RAM. This field should be read as '1'
41005 * to indicate that the output has been completely written.
41006 * When writing a command completion or response to an internal processor,
41007 * the order of writes has to be such that this field is written last.
41012 /****************************
41013 * hwrm_nvm_get_dir_entries *
41014 ****************************/
41017 /* hwrm_nvm_get_dir_entries_input (size:192b/24B) */
41018 struct hwrm_nvm_get_dir_entries_input {
41019 /* The HWRM command request type. */
41022 * The completion ring to send the completion event on. This should
41023 * be the NQ ID returned from the `nq_alloc` HWRM command.
41025 uint16_t cmpl_ring;
41027 * The sequence ID is used by the driver for tracking multiple
41028 * commands. This ID is treated as opaque data by the firmware and
41029 * the value is returned in the `hwrm_resp_hdr` upon completion.
41033 * The target ID of the command:
41034 * * 0x0-0xFFF8 - The function ID
41035 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
41036 * * 0xFFFD - Reserved for user-space HWRM interface
41039 uint16_t target_id;
41041 * A physical address pointer pointing to a host buffer that the
41042 * command's response data will be written. This can be either a host
41043 * physical address (HPA) or a guest physical address (GPA) and must
41044 * point to a physically contiguous block of memory.
41046 uint64_t resp_addr;
41048 * 64-bit Host Destination Address.
41049 * This is the host address where the directory will be written.
41051 uint64_t host_dest_addr;
41054 /* hwrm_nvm_get_dir_entries_output (size:128b/16B) */
41055 struct hwrm_nvm_get_dir_entries_output {
41056 /* The specific error status for the command. */
41057 uint16_t error_code;
41058 /* The HWRM command request type. */
41060 /* The sequence ID from the original command. */
41062 /* The length of the response data in number of bytes. */
41064 uint8_t unused_0[7];
41066 * This field is used in Output records to indicate that the output
41067 * is completely written to RAM. This field should be read as '1'
41068 * to indicate that the output has been completely written.
41069 * When writing a command completion or response to an internal processor,
41070 * the order of writes has to be such that this field is written last.
41075 /*************************
41076 * hwrm_nvm_get_dir_info *
41077 *************************/
41080 /* hwrm_nvm_get_dir_info_input (size:128b/16B) */
41081 struct hwrm_nvm_get_dir_info_input {
41082 /* The HWRM command request type. */
41085 * The completion ring to send the completion event on. This should
41086 * be the NQ ID returned from the `nq_alloc` HWRM command.
41088 uint16_t cmpl_ring;
41090 * The sequence ID is used by the driver for tracking multiple
41091 * commands. This ID is treated as opaque data by the firmware and
41092 * the value is returned in the `hwrm_resp_hdr` upon completion.
41096 * The target ID of the command:
41097 * * 0x0-0xFFF8 - The function ID
41098 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
41099 * * 0xFFFD - Reserved for user-space HWRM interface
41102 uint16_t target_id;
41104 * A physical address pointer pointing to a host buffer that the
41105 * command's response data will be written. This can be either a host
41106 * physical address (HPA) or a guest physical address (GPA) and must
41107 * point to a physically contiguous block of memory.
41109 uint64_t resp_addr;
41112 /* hwrm_nvm_get_dir_info_output (size:192b/24B) */
41113 struct hwrm_nvm_get_dir_info_output {
41114 /* The specific error status for the command. */
41115 uint16_t error_code;
41116 /* The HWRM command request type. */
41118 /* The sequence ID from the original command. */
41120 /* The length of the response data in number of bytes. */
41122 /* Number of directory entries in the directory. */
41124 /* Size of each directory entry, in bytes. */
41125 uint32_t entry_length;
41126 uint8_t unused_0[7];
41128 * This field is used in Output records to indicate that the output
41129 * is completely written to RAM. This field should be read as '1'
41130 * to indicate that the output has been completely written.
41131 * When writing a command completion or response to an internal processor,
41132 * the order of writes has to be such that this field is written last.
41137 /******************
41139 ******************/
41142 /* hwrm_nvm_write_input (size:384b/48B) */
41143 struct hwrm_nvm_write_input {
41144 /* The HWRM command request type. */
41147 * The completion ring to send the completion event on. This should
41148 * be the NQ ID returned from the `nq_alloc` HWRM command.
41150 uint16_t cmpl_ring;
41152 * The sequence ID is used by the driver for tracking multiple
41153 * commands. This ID is treated as opaque data by the firmware and
41154 * the value is returned in the `hwrm_resp_hdr` upon completion.
41158 * The target ID of the command:
41159 * * 0x0-0xFFF8 - The function ID
41160 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
41161 * * 0xFFFD - Reserved for user-space HWRM interface
41164 uint16_t target_id;
41166 * A physical address pointer pointing to a host buffer that the
41167 * command's response data will be written. This can be either a host
41168 * physical address (HPA) or a guest physical address (GPA) and must
41169 * point to a physically contiguous block of memory.
41171 uint64_t resp_addr;
41173 * 64-bit Host Source Address.
41174 * This is where the source data is.
41176 uint64_t host_src_addr;
41177 /* The Directory Entry Type (valid values are defined in the bnxnvm_directory_type enum defined in the file bnxnvm_defs.h). */
41180 * Directory ordinal.
41181 * The 0-based instance of the combined Directory Entry Type and Extension.
41183 uint16_t dir_ordinal;
41184 /* The Directory Entry Extension flags (see BNX_DIR_EXT_* in the file bnxnvm_defs.h). */
41186 /* Directory Entry Attribute flags (see BNX_DIR_ATTR_* in the file bnxnvm_defs.h). */
41189 * Length of data to write, in bytes. May be less than or equal to the allocated size for the directory entry.
41190 * The data length stored in the directory entry will be updated to reflect this value once the write is complete.
41192 uint32_t dir_data_length;
41197 * When this bit is '1', the original active image
41198 * will not be removed. TBD: what purpose is this?
41200 #define HWRM_NVM_WRITE_INPUT_FLAGS_KEEP_ORIG_ACTIVE_IMG \
41203 * The requested length of the allocated NVM for the item, in bytes. This value may be greater than or equal to the specified data length (dir_data_length).
41204 * If this value is less than the specified data length, it will be ignored.
41205 * The response will contain the actual allocated item length, which may be greater than the requested item length.
41206 * The purpose for allocating more than the required number of bytes for an item's data is to pre-allocate extra storage (padding) to accommodate
41207 * the potential future growth of an item (e.g. upgraded firmware with a size increase, log growth, expanded configuration data).
41209 uint32_t dir_item_length;
41213 /* hwrm_nvm_write_output (size:128b/16B) */
41214 struct hwrm_nvm_write_output {
41215 /* The specific error status for the command. */
41216 uint16_t error_code;
41217 /* The HWRM command request type. */
41219 /* The sequence ID from the original command. */
41221 /* The length of the response data in number of bytes. */
41224 * Length of the allocated NVM for the item, in bytes. The value may be greater than or equal to the specified data length or the requested item length.
41225 * The actual item length used when creating a new directory entry will be a multiple of an NVM block size.
41227 uint32_t dir_item_length;
41228 /* The directory index of the created or modified item. */
41232 * This field is used in Output records to indicate that the output
41233 * is completely written to RAM. This field should be read as '1'
41234 * to indicate that the output has been completely written.
41235 * When writing a command completion or response to an internal processor,
41236 * the order of writes has to be such that this field is written last.
41241 /* hwrm_nvm_write_cmd_err (size:64b/8B) */
41242 struct hwrm_nvm_write_cmd_err {
41244 * command specific error codes that goes to
41245 * the cmd_err field in Common HWRM Error Response.
41248 /* Unknown error */
41249 #define HWRM_NVM_WRITE_CMD_ERR_CODE_UNKNOWN UINT32_C(0x0)
41250 /* Unable to complete operation due to fragmentation */
41251 #define HWRM_NVM_WRITE_CMD_ERR_CODE_FRAG_ERR UINT32_C(0x1)
41252 /* nvm is completely full. */
41253 #define HWRM_NVM_WRITE_CMD_ERR_CODE_NO_SPACE UINT32_C(0x2)
41254 #define HWRM_NVM_WRITE_CMD_ERR_CODE_LAST \
41255 HWRM_NVM_WRITE_CMD_ERR_CODE_NO_SPACE
41256 uint8_t unused_0[7];
41259 /*******************
41260 * hwrm_nvm_modify *
41261 *******************/
41264 /* hwrm_nvm_modify_input (size:320b/40B) */
41265 struct hwrm_nvm_modify_input {
41266 /* The HWRM command request type. */
41269 * The completion ring to send the completion event on. This should
41270 * be the NQ ID returned from the `nq_alloc` HWRM command.
41272 uint16_t cmpl_ring;
41274 * The sequence ID is used by the driver for tracking multiple
41275 * commands. This ID is treated as opaque data by the firmware and
41276 * the value is returned in the `hwrm_resp_hdr` upon completion.
41280 * The target ID of the command:
41281 * * 0x0-0xFFF8 - The function ID
41282 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
41283 * * 0xFFFD - Reserved for user-space HWRM interface
41286 uint16_t target_id;
41288 * A physical address pointer pointing to a host buffer that the
41289 * command's response data will be written. This can be either a host
41290 * physical address (HPA) or a guest physical address (GPA) and must
41291 * point to a physically contiguous block of memory.
41293 uint64_t resp_addr;
41295 * 64-bit Host Source Address.
41296 * This is where the modified data is.
41298 uint64_t host_src_addr;
41299 /* 16-bit directory entry index. */
41303 * This flag indicates the sender wants to modify a continuous NVRAM
41304 * area using a batch of this HWRM requests. The offset of a request
41305 * must be continuous to the end of previous request's. Firmware does
41306 * not update the directory entry until receiving the last request,
41307 * which is indicated by the batch_last flag.
41308 * This flag is set usually when a sender does not have a block of
41309 * memory that is big enough to hold the entire NVRAM data for send
41312 #define HWRM_NVM_MODIFY_INPUT_FLAGS_BATCH_MODE UINT32_C(0x1)
41314 * This flag can be used only when the batch_mode flag is set.
41315 * It indicates this request is the last of batch requests.
41317 #define HWRM_NVM_MODIFY_INPUT_FLAGS_BATCH_LAST UINT32_C(0x2)
41318 /* 32-bit NVRAM byte-offset to modify content from. */
41321 * Length of data to be modified, in bytes. The length shall
41325 uint8_t unused_1[4];
41328 /* hwrm_nvm_modify_output (size:128b/16B) */
41329 struct hwrm_nvm_modify_output {
41330 /* The specific error status for the command. */
41331 uint16_t error_code;
41332 /* The HWRM command request type. */
41334 /* The sequence ID from the original command. */
41336 /* The length of the response data in number of bytes. */
41338 uint8_t unused_0[7];
41340 * This field is used in Output records to indicate that the output
41341 * is completely written to RAM. This field should be read as '1'
41342 * to indicate that the output has been completely written.
41343 * When writing a command completion or response to an internal processor,
41344 * the order of writes has to be such that this field is written last.
41349 /***************************
41350 * hwrm_nvm_find_dir_entry *
41351 ***************************/
41354 /* hwrm_nvm_find_dir_entry_input (size:256b/32B) */
41355 struct hwrm_nvm_find_dir_entry_input {
41356 /* The HWRM command request type. */
41359 * The completion ring to send the completion event on. This should
41360 * be the NQ ID returned from the `nq_alloc` HWRM command.
41362 uint16_t cmpl_ring;
41364 * The sequence ID is used by the driver for tracking multiple
41365 * commands. This ID is treated as opaque data by the firmware and
41366 * the value is returned in the `hwrm_resp_hdr` upon completion.
41370 * The target ID of the command:
41371 * * 0x0-0xFFF8 - The function ID
41372 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
41373 * * 0xFFFD - Reserved for user-space HWRM interface
41376 uint16_t target_id;
41378 * A physical address pointer pointing to a host buffer that the
41379 * command's response data will be written. This can be either a host
41380 * physical address (HPA) or a guest physical address (GPA) and must
41381 * point to a physically contiguous block of memory.
41383 uint64_t resp_addr;
41386 * This bit must be '1' for the dir_idx_valid field to be
41389 #define HWRM_NVM_FIND_DIR_ENTRY_INPUT_ENABLES_DIR_IDX_VALID \
41391 /* Directory Entry Index */
41393 /* Directory Entry (Image) Type */
41396 * Directory ordinal.
41397 * The instance of this Directory Type
41399 uint16_t dir_ordinal;
41400 /* The Directory Entry Extension flags. */
41402 /* This value indicates the search option using dir_ordinal. */
41403 uint8_t opt_ordinal;
41404 /* This value indicates the search option using dir_ordinal. */
41405 #define HWRM_NVM_FIND_DIR_ENTRY_INPUT_OPT_ORDINAL_MASK UINT32_C(0x3)
41406 #define HWRM_NVM_FIND_DIR_ENTRY_INPUT_OPT_ORDINAL_SFT 0
41407 /* Equal to specified ordinal value. */
41408 #define HWRM_NVM_FIND_DIR_ENTRY_INPUT_OPT_ORDINAL_EQ UINT32_C(0x0)
41409 /* Greater than or equal to specified ordinal value */
41410 #define HWRM_NVM_FIND_DIR_ENTRY_INPUT_OPT_ORDINAL_GE UINT32_C(0x1)
41411 /* Greater than specified ordinal value */
41412 #define HWRM_NVM_FIND_DIR_ENTRY_INPUT_OPT_ORDINAL_GT UINT32_C(0x2)
41413 #define HWRM_NVM_FIND_DIR_ENTRY_INPUT_OPT_ORDINAL_LAST \
41414 HWRM_NVM_FIND_DIR_ENTRY_INPUT_OPT_ORDINAL_GT
41415 uint8_t unused_0[3];
41418 /* hwrm_nvm_find_dir_entry_output (size:256b/32B) */
41419 struct hwrm_nvm_find_dir_entry_output {
41420 /* The specific error status for the command. */
41421 uint16_t error_code;
41422 /* The HWRM command request type. */
41424 /* The sequence ID from the original command. */
41426 /* The length of the response data in number of bytes. */
41428 /* Allocated NVRAM for this directory entry, in bytes. */
41429 uint32_t dir_item_length;
41430 /* Size of the stored data for this directory entry, in bytes. */
41431 uint32_t dir_data_length;
41433 * Firmware version.
41434 * Only valid if the directory entry is for embedded firmware stored in APE_BIN Format.
41437 /* Directory ordinal. */
41438 uint16_t dir_ordinal;
41439 /* Directory Entry Index */
41441 uint8_t unused_0[7];
41443 * This field is used in Output records to indicate that the output
41444 * is completely written to RAM. This field should be read as '1'
41445 * to indicate that the output has been completely written.
41446 * When writing a command completion or response to an internal processor,
41447 * the order of writes has to be such that this field is written last.
41452 /****************************
41453 * hwrm_nvm_erase_dir_entry *
41454 ****************************/
41457 /* hwrm_nvm_erase_dir_entry_input (size:192b/24B) */
41458 struct hwrm_nvm_erase_dir_entry_input {
41459 /* The HWRM command request type. */
41462 * The completion ring to send the completion event on. This should
41463 * be the NQ ID returned from the `nq_alloc` HWRM command.
41465 uint16_t cmpl_ring;
41467 * The sequence ID is used by the driver for tracking multiple
41468 * commands. This ID is treated as opaque data by the firmware and
41469 * the value is returned in the `hwrm_resp_hdr` upon completion.
41473 * The target ID of the command:
41474 * * 0x0-0xFFF8 - The function ID
41475 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
41476 * * 0xFFFD - Reserved for user-space HWRM interface
41479 uint16_t target_id;
41481 * A physical address pointer pointing to a host buffer that the
41482 * command's response data will be written. This can be either a host
41483 * physical address (HPA) or a guest physical address (GPA) and must
41484 * point to a physically contiguous block of memory.
41486 uint64_t resp_addr;
41487 /* Directory Entry Index */
41489 uint8_t unused_0[6];
41492 /* hwrm_nvm_erase_dir_entry_output (size:128b/16B) */
41493 struct hwrm_nvm_erase_dir_entry_output {
41494 /* The specific error status for the command. */
41495 uint16_t error_code;
41496 /* The HWRM command request type. */
41498 /* The sequence ID from the original command. */
41500 /* The length of the response data in number of bytes. */
41502 uint8_t unused_0[7];
41504 * This field is used in Output records to indicate that the output
41505 * is completely written to RAM. This field should be read as '1'
41506 * to indicate that the output has been completely written.
41507 * When writing a command completion or response to an internal processor,
41508 * the order of writes has to be such that this field is written last.
41513 /*************************
41514 * hwrm_nvm_get_dev_info *
41515 *************************/
41518 /* hwrm_nvm_get_dev_info_input (size:128b/16B) */
41519 struct hwrm_nvm_get_dev_info_input {
41520 /* The HWRM command request type. */
41523 * The completion ring to send the completion event on. This should
41524 * be the NQ ID returned from the `nq_alloc` HWRM command.
41526 uint16_t cmpl_ring;
41528 * The sequence ID is used by the driver for tracking multiple
41529 * commands. This ID is treated as opaque data by the firmware and
41530 * the value is returned in the `hwrm_resp_hdr` upon completion.
41534 * The target ID of the command:
41535 * * 0x0-0xFFF8 - The function ID
41536 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
41537 * * 0xFFFD - Reserved for user-space HWRM interface
41540 uint16_t target_id;
41542 * A physical address pointer pointing to a host buffer that the
41543 * command's response data will be written. This can be either a host
41544 * physical address (HPA) or a guest physical address (GPA) and must
41545 * point to a physically contiguous block of memory.
41547 uint64_t resp_addr;
41550 /* hwrm_nvm_get_dev_info_output (size:256b/32B) */
41551 struct hwrm_nvm_get_dev_info_output {
41552 /* The specific error status for the command. */
41553 uint16_t error_code;
41554 /* The HWRM command request type. */
41556 /* The sequence ID from the original command. */
41558 /* The length of the response data in number of bytes. */
41560 /* Manufacturer ID. */
41561 uint16_t manufacturer_id;
41563 uint16_t device_id;
41564 /* Sector size of the NVRAM device. */
41565 uint32_t sector_size;
41566 /* Total size, in bytes of the NVRAM device. */
41567 uint32_t nvram_size;
41568 uint32_t reserved_size;
41569 /* Available size that can be used, in bytes. Available size is the NVRAM size take away the used size and reserved size. */
41570 uint32_t available_size;
41571 /* This field represents the major version of NVM cfg */
41572 uint8_t nvm_cfg_ver_maj;
41573 /* This field represents the minor version of NVM cfg */
41574 uint8_t nvm_cfg_ver_min;
41575 /* This field represents the update version of NVM cfg */
41576 uint8_t nvm_cfg_ver_upd;
41578 * This field is used in Output records to indicate that the output
41579 * is completely written to RAM. This field should be read as '1'
41580 * to indicate that the output has been completely written.
41581 * When writing a command completion or response to an internal processor,
41582 * the order of writes has to be such that this field is written last.
41587 /**************************
41588 * hwrm_nvm_mod_dir_entry *
41589 **************************/
41592 /* hwrm_nvm_mod_dir_entry_input (size:256b/32B) */
41593 struct hwrm_nvm_mod_dir_entry_input {
41594 /* The HWRM command request type. */
41597 * The completion ring to send the completion event on. This should
41598 * be the NQ ID returned from the `nq_alloc` HWRM command.
41600 uint16_t cmpl_ring;
41602 * The sequence ID is used by the driver for tracking multiple
41603 * commands. This ID is treated as opaque data by the firmware and
41604 * the value is returned in the `hwrm_resp_hdr` upon completion.
41608 * The target ID of the command:
41609 * * 0x0-0xFFF8 - The function ID
41610 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
41611 * * 0xFFFD - Reserved for user-space HWRM interface
41614 uint16_t target_id;
41616 * A physical address pointer pointing to a host buffer that the
41617 * command's response data will be written. This can be either a host
41618 * physical address (HPA) or a guest physical address (GPA) and must
41619 * point to a physically contiguous block of memory.
41621 uint64_t resp_addr;
41624 * This bit must be '1' for the checksum field to be
41627 #define HWRM_NVM_MOD_DIR_ENTRY_INPUT_ENABLES_CHECKSUM UINT32_C(0x1)
41628 /* Directory Entry Index */
41631 * Directory ordinal.
41632 * The (0-based) instance of this Directory Type.
41634 uint16_t dir_ordinal;
41635 /* The Directory Entry Extension flags (see BNX_DIR_EXT_* for extension flag definitions). */
41637 /* Directory Entry Attribute flags (see BNX_DIR_ATTR_* for attribute flag definitions). */
41640 * If valid, then this field updates the checksum
41641 * value of the content in the directory entry.
41646 /* hwrm_nvm_mod_dir_entry_output (size:128b/16B) */
41647 struct hwrm_nvm_mod_dir_entry_output {
41648 /* The specific error status for the command. */
41649 uint16_t error_code;
41650 /* The HWRM command request type. */
41652 /* The sequence ID from the original command. */
41654 /* The length of the response data in number of bytes. */
41656 uint8_t unused_0[7];
41658 * This field is used in Output records to indicate that the output
41659 * is completely written to RAM. This field should be read as '1'
41660 * to indicate that the output has been completely written.
41661 * When writing a command completion or response to an internal processor,
41662 * the order of writes has to be such that this field is written last.
41667 /**************************
41668 * hwrm_nvm_verify_update *
41669 **************************/
41672 /* hwrm_nvm_verify_update_input (size:192b/24B) */
41673 struct hwrm_nvm_verify_update_input {
41674 /* The HWRM command request type. */
41677 * The completion ring to send the completion event on. This should
41678 * be the NQ ID returned from the `nq_alloc` HWRM command.
41680 uint16_t cmpl_ring;
41682 * The sequence ID is used by the driver for tracking multiple
41683 * commands. This ID is treated as opaque data by the firmware and
41684 * the value is returned in the `hwrm_resp_hdr` upon completion.
41688 * The target ID of the command:
41689 * * 0x0-0xFFF8 - The function ID
41690 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
41691 * * 0xFFFD - Reserved for user-space HWRM interface
41694 uint16_t target_id;
41696 * A physical address pointer pointing to a host buffer that the
41697 * command's response data will be written. This can be either a host
41698 * physical address (HPA) or a guest physical address (GPA) and must
41699 * point to a physically contiguous block of memory.
41701 uint64_t resp_addr;
41702 /* Directory Entry Type, to be verified. */
41705 * Directory ordinal.
41706 * The instance of the Directory Type to be verified.
41708 uint16_t dir_ordinal;
41710 * The Directory Entry Extension flags.
41711 * The "UPDATE" extension flag must be set in this value.
41712 * A corresponding directory entry with the same type and ordinal values but *without*
41713 * the "UPDATE" extension flag must also exist. The other flags of the extension must
41714 * be identical between the active and update entries.
41717 uint8_t unused_0[2];
41720 /* hwrm_nvm_verify_update_output (size:128b/16B) */
41721 struct hwrm_nvm_verify_update_output {
41722 /* The specific error status for the command. */
41723 uint16_t error_code;
41724 /* The HWRM command request type. */
41726 /* The sequence ID from the original command. */
41728 /* The length of the response data in number of bytes. */
41730 uint8_t unused_0[7];
41732 * This field is used in Output records to indicate that the output
41733 * is completely written to RAM. This field should be read as '1'
41734 * to indicate that the output has been completely written.
41735 * When writing a command completion or response to an internal processor,
41736 * the order of writes has to be such that this field is written last.
41741 /***************************
41742 * hwrm_nvm_install_update *
41743 ***************************/
41746 /* hwrm_nvm_install_update_input (size:192b/24B) */
41747 struct hwrm_nvm_install_update_input {
41748 /* The HWRM command request type. */
41751 * The completion ring to send the completion event on. This should
41752 * be the NQ ID returned from the `nq_alloc` HWRM command.
41754 uint16_t cmpl_ring;
41756 * The sequence ID is used by the driver for tracking multiple
41757 * commands. This ID is treated as opaque data by the firmware and
41758 * the value is returned in the `hwrm_resp_hdr` upon completion.
41762 * The target ID of the command:
41763 * * 0x0-0xFFF8 - The function ID
41764 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
41765 * * 0xFFFD - Reserved for user-space HWRM interface
41768 uint16_t target_id;
41770 * A physical address pointer pointing to a host buffer that the
41771 * command's response data will be written. This can be either a host
41772 * physical address (HPA) or a guest physical address (GPA) and must
41773 * point to a physically contiguous block of memory.
41775 uint64_t resp_addr;
41777 * Installation type. If the value 3 through 0xffff is used,
41778 * only packaged items with that type value will be installed and
41779 * conditional installation directives for those packaged items
41780 * will be over-ridden (i.e. 'create' or 'replace' will be treated
41783 uint32_t install_type;
41785 * Perform a normal package installation. Conditional installation
41786 * directives (e.g. 'create' and 'replace') of packaged items
41787 * will be followed.
41789 #define HWRM_NVM_INSTALL_UPDATE_INPUT_INSTALL_TYPE_NORMAL UINT32_C(0x0)
41791 * Install all packaged items regardless of installation directive
41792 * (i.e. treat all packaged items as though they have an installation
41793 * directive of 'install').
41795 #define HWRM_NVM_INSTALL_UPDATE_INPUT_INSTALL_TYPE_ALL \
41796 UINT32_C(0xffffffff)
41797 #define HWRM_NVM_INSTALL_UPDATE_INPUT_INSTALL_TYPE_LAST \
41798 HWRM_NVM_INSTALL_UPDATE_INPUT_INSTALL_TYPE_ALL
41800 /* If set to 1, then securely erase all unused locations in persistent storage. */
41801 #define HWRM_NVM_INSTALL_UPDATE_INPUT_FLAGS_ERASE_UNUSED_SPACE \
41804 * If set to 1, then unspecified images, images not in the package file, will be safely deleted.
41805 * When combined with erase_unused_space then unspecified images will be securely erased.
41807 #define HWRM_NVM_INSTALL_UPDATE_INPUT_FLAGS_REMOVE_UNUSED_PKG \
41810 * If set to 1, FW will defragment the NVM if defragmentation is required for the update.
41811 * Allow additional time for this command to complete if this bit is set to 1.
41813 #define HWRM_NVM_INSTALL_UPDATE_INPUT_FLAGS_ALLOWED_TO_DEFRAG \
41816 * If set to 1, FW will verify the package in the "UPDATE" NVM item
41817 * without installing it. This flag is for FW internal use only.
41818 * Users should not set this flag. The request will otherwise fail.
41820 #define HWRM_NVM_INSTALL_UPDATE_INPUT_FLAGS_VERIFY_ONLY \
41822 uint8_t unused_0[2];
41825 /* hwrm_nvm_install_update_output (size:192b/24B) */
41826 struct hwrm_nvm_install_update_output {
41827 /* The specific error status for the command. */
41828 uint16_t error_code;
41829 /* The HWRM command request type. */
41831 /* The sequence ID from the original command. */
41833 /* The length of the response data in number of bytes. */
41836 * Bit-mask of successfully installed items.
41837 * Bit-0 corresponding to the first packaged item, Bit-1 for the second item, etc.
41838 * A value of 0 indicates that no items were successfully installed.
41840 uint64_t installed_items;
41841 /* result is 8 b */
41843 /* There was no problem with the package installation. */
41844 #define HWRM_NVM_INSTALL_UPDATE_OUTPUT_RESULT_SUCCESS UINT32_C(0x0)
41845 #define HWRM_NVM_INSTALL_UPDATE_OUTPUT_RESULT_LAST \
41846 HWRM_NVM_INSTALL_UPDATE_OUTPUT_RESULT_SUCCESS
41847 /* problem_item is 8 b */
41848 uint8_t problem_item;
41849 /* There was no problem with any packaged items. */
41850 #define HWRM_NVM_INSTALL_UPDATE_OUTPUT_PROBLEM_ITEM_NONE \
41852 /* There was a problem with the NVM package itself. */
41853 #define HWRM_NVM_INSTALL_UPDATE_OUTPUT_PROBLEM_ITEM_PACKAGE \
41855 #define HWRM_NVM_INSTALL_UPDATE_OUTPUT_PROBLEM_ITEM_LAST \
41856 HWRM_NVM_INSTALL_UPDATE_OUTPUT_PROBLEM_ITEM_PACKAGE
41857 /* reset_required is 8 b */
41858 uint8_t reset_required;
41860 * No reset is required for installed/updated firmware or
41861 * microcode to take effect.
41863 #define HWRM_NVM_INSTALL_UPDATE_OUTPUT_RESET_REQUIRED_NONE \
41866 * A PCIe reset (e.g. system reboot) is
41867 * required for newly installed/updated firmware or
41868 * microcode to take effect.
41870 #define HWRM_NVM_INSTALL_UPDATE_OUTPUT_RESET_REQUIRED_PCI \
41873 * A controller power reset (e.g. system power-cycle) is
41874 * required for newly installed/updated firmware or
41875 * microcode to take effect. Some newly installed/updated
41876 * firmware or microcode may still take effect upon the
41879 #define HWRM_NVM_INSTALL_UPDATE_OUTPUT_RESET_REQUIRED_POWER \
41881 #define HWRM_NVM_INSTALL_UPDATE_OUTPUT_RESET_REQUIRED_LAST \
41882 HWRM_NVM_INSTALL_UPDATE_OUTPUT_RESET_REQUIRED_POWER
41883 uint8_t unused_0[4];
41885 * This field is used in Output records to indicate that the output
41886 * is completely written to RAM. This field should be read as '1'
41887 * to indicate that the output has been completely written.
41888 * When writing a command completion or response to an internal processor,
41889 * the order of writes has to be such that this field is written last.
41894 /* hwrm_nvm_install_update_cmd_err (size:64b/8B) */
41895 struct hwrm_nvm_install_update_cmd_err {
41897 * command specific error codes that goes to
41898 * the cmd_err field in Common HWRM Error Response.
41901 /* Unknown error */
41902 #define HWRM_NVM_INSTALL_UPDATE_CMD_ERR_CODE_UNKNOWN UINT32_C(0x0)
41903 /* Unable to complete operation due to fragmentation */
41904 #define HWRM_NVM_INSTALL_UPDATE_CMD_ERR_CODE_FRAG_ERR UINT32_C(0x1)
41905 /* nvm is completely full. */
41906 #define HWRM_NVM_INSTALL_UPDATE_CMD_ERR_CODE_NO_SPACE UINT32_C(0x2)
41907 #define HWRM_NVM_INSTALL_UPDATE_CMD_ERR_CODE_LAST \
41908 HWRM_NVM_INSTALL_UPDATE_CMD_ERR_CODE_NO_SPACE
41909 uint8_t unused_0[7];
41912 /******************
41914 ******************/
41917 /* hwrm_nvm_flush_input (size:128b/16B) */
41918 struct hwrm_nvm_flush_input {
41919 /* The HWRM command request type. */
41922 * The completion ring to send the completion event on. This should
41923 * be the NQ ID returned from the `nq_alloc` HWRM command.
41925 uint16_t cmpl_ring;
41927 * The sequence ID is used by the driver for tracking multiple
41928 * commands. This ID is treated as opaque data by the firmware and
41929 * the value is returned in the `hwrm_resp_hdr` upon completion.
41933 * The target ID of the command:
41934 * * 0x0-0xFFF8 - The function ID
41935 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
41936 * * 0xFFFD - Reserved for user-space HWRM interface
41939 uint16_t target_id;
41941 * A physical address pointer pointing to a host buffer that the
41942 * command's response data will be written. This can be either a host
41943 * physical address (HPA) or a guest physical address (GPA) and must
41944 * point to a physically contiguous block of memory.
41946 uint64_t resp_addr;
41949 /* hwrm_nvm_flush_output (size:128b/16B) */
41950 struct hwrm_nvm_flush_output {
41951 /* The specific error status for the command. */
41952 uint16_t error_code;
41953 /* The HWRM command request type. */
41955 /* The sequence ID from the original command. */
41957 /* The length of the response data in number of bytes. */
41959 uint8_t unused_0[7];
41961 * This field is used in Output records to indicate that the output
41962 * is completely written to RAM. This field should be read as '1'
41963 * to indicate that the output has been completely written.
41964 * When writing a command completion or response to an internal processor,
41965 * the order of writes has to be such that this field is written last.
41970 /* hwrm_nvm_flush_cmd_err (size:64b/8B) */
41971 struct hwrm_nvm_flush_cmd_err {
41973 * command specific error codes that goes to
41974 * the cmd_err field in Common HWRM Error Response.
41977 /* Unknown error */
41978 #define HWRM_NVM_FLUSH_CMD_ERR_CODE_UNKNOWN UINT32_C(0x0)
41979 /* flush could not be performed */
41980 #define HWRM_NVM_FLUSH_CMD_ERR_CODE_FAIL UINT32_C(0x1)
41981 #define HWRM_NVM_FLUSH_CMD_ERR_CODE_LAST \
41982 HWRM_NVM_FLUSH_CMD_ERR_CODE_FAIL
41983 uint8_t unused_0[7];
41986 /*************************
41987 * hwrm_nvm_get_variable *
41988 *************************/
41991 /* hwrm_nvm_get_variable_input (size:320b/40B) */
41992 struct hwrm_nvm_get_variable_input {
41993 /* The HWRM command request type. */
41996 * The completion ring to send the completion event on. This should
41997 * be the NQ ID returned from the `nq_alloc` HWRM command.
41999 uint16_t cmpl_ring;
42001 * The sequence ID is used by the driver for tracking multiple
42002 * commands. This ID is treated as opaque data by the firmware and
42003 * the value is returned in the `hwrm_resp_hdr` upon completion.
42007 * The target ID of the command:
42008 * * 0x0-0xFFF8 - The function ID
42009 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
42010 * * 0xFFFD - Reserved for user-space HWRM interface
42013 uint16_t target_id;
42015 * A physical address pointer pointing to a host buffer that the
42016 * command's response data will be written. This can be either a host
42017 * physical address (HPA) or a guest physical address (GPA) and must
42018 * point to a physically contiguous block of memory.
42020 uint64_t resp_addr;
42022 * This is the host address where
42023 * nvm variable will be stored
42025 uint64_t dest_data_addr;
42026 /* size of data in bits */
42028 /* nvm cfg option number */
42029 uint16_t option_num;
42031 #define HWRM_NVM_GET_VARIABLE_INPUT_OPTION_NUM_RSVD_0 UINT32_C(0x0)
42033 #define HWRM_NVM_GET_VARIABLE_INPUT_OPTION_NUM_RSVD_FFFF \
42035 #define HWRM_NVM_GET_VARIABLE_INPUT_OPTION_NUM_LAST \
42036 HWRM_NVM_GET_VARIABLE_INPUT_OPTION_NUM_RSVD_FFFF
42038 * Number of dimensions for this nvm configuration variable.
42039 * This value indicates how many of the indexN values to use.
42040 * A value of 0 means that none of the indexN values are valid.
42041 * A value of 1 requires at index0 is valued, a value of 2
42042 * requires that index0 and index1 are valid, and so forth
42044 uint16_t dimensions;
42045 /* index for the 1st dimensions */
42047 /* index for the 2nd dimensions */
42049 /* index for the 3rd dimensions */
42051 /* index for the 4th dimensions */
42055 * When this bit is set to 1, the factory default value will be returned,
42056 * 0 returns the operational value.
42058 #define HWRM_NVM_GET_VARIABLE_INPUT_FLAGS_FACTORY_DFLT \
42063 /* hwrm_nvm_get_variable_output (size:128b/16B) */
42064 struct hwrm_nvm_get_variable_output {
42065 /* The specific error status for the command. */
42066 uint16_t error_code;
42067 /* The HWRM command request type. */
42069 /* The sequence ID from the original command. */
42071 /* The length of the response data in number of bytes. */
42073 /* size of data of the actual variable retrieved in bits */
42076 * option_num is the option number for the data retrieved. It is possible in the
42077 * future that the option number returned would be different than requested. This
42078 * condition could occur if an option is deprecated and a new option id is defined
42079 * with similar characteristics, but has a slightly different definition. This
42080 * also makes it convenient for the caller to identify the variable result with
42081 * the option id from the response.
42083 uint16_t option_num;
42085 #define HWRM_NVM_GET_VARIABLE_OUTPUT_OPTION_NUM_RSVD_0 UINT32_C(0x0)
42087 #define HWRM_NVM_GET_VARIABLE_OUTPUT_OPTION_NUM_RSVD_FFFF \
42089 #define HWRM_NVM_GET_VARIABLE_OUTPUT_OPTION_NUM_LAST \
42090 HWRM_NVM_GET_VARIABLE_OUTPUT_OPTION_NUM_RSVD_FFFF
42091 uint8_t unused_0[3];
42093 * This field is used in Output records to indicate that the output
42094 * is completely written to RAM. This field should be read as '1'
42095 * to indicate that the output has been completely written.
42096 * When writing a command completion or response to an internal processor,
42097 * the order of writes has to be such that this field is written last.
42102 /* hwrm_nvm_get_variable_cmd_err (size:64b/8B) */
42103 struct hwrm_nvm_get_variable_cmd_err {
42105 * command specific error codes that goes to
42106 * the cmd_err field in Common HWRM Error Response.
42109 /* Unknown error */
42110 #define HWRM_NVM_GET_VARIABLE_CMD_ERR_CODE_UNKNOWN UINT32_C(0x0)
42111 /* variable does not exist */
42112 #define HWRM_NVM_GET_VARIABLE_CMD_ERR_CODE_VAR_NOT_EXIST UINT32_C(0x1)
42113 /* configuration is corrupted and the variable cannot be saved */
42114 #define HWRM_NVM_GET_VARIABLE_CMD_ERR_CODE_CORRUPT_VAR UINT32_C(0x2)
42115 /* length specified is too small */
42116 #define HWRM_NVM_GET_VARIABLE_CMD_ERR_CODE_LEN_TOO_SHORT UINT32_C(0x3)
42117 #define HWRM_NVM_GET_VARIABLE_CMD_ERR_CODE_LAST \
42118 HWRM_NVM_GET_VARIABLE_CMD_ERR_CODE_LEN_TOO_SHORT
42119 uint8_t unused_0[7];
42122 /*************************
42123 * hwrm_nvm_set_variable *
42124 *************************/
42127 /* hwrm_nvm_set_variable_input (size:320b/40B) */
42128 struct hwrm_nvm_set_variable_input {
42129 /* The HWRM command request type. */
42132 * The completion ring to send the completion event on. This should
42133 * be the NQ ID returned from the `nq_alloc` HWRM command.
42135 uint16_t cmpl_ring;
42137 * The sequence ID is used by the driver for tracking multiple
42138 * commands. This ID is treated as opaque data by the firmware and
42139 * the value is returned in the `hwrm_resp_hdr` upon completion.
42143 * The target ID of the command:
42144 * * 0x0-0xFFF8 - The function ID
42145 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
42146 * * 0xFFFD - Reserved for user-space HWRM interface
42149 uint16_t target_id;
42151 * A physical address pointer pointing to a host buffer that the
42152 * command's response data will be written. This can be either a host
42153 * physical address (HPA) or a guest physical address (GPA) and must
42154 * point to a physically contiguous block of memory.
42156 uint64_t resp_addr;
42158 * This is the host address where
42159 * nvm variable will be copied from
42161 uint64_t src_data_addr;
42162 /* size of data in bits */
42164 /* nvm cfg option number */
42165 uint16_t option_num;
42167 #define HWRM_NVM_SET_VARIABLE_INPUT_OPTION_NUM_RSVD_0 UINT32_C(0x0)
42169 #define HWRM_NVM_SET_VARIABLE_INPUT_OPTION_NUM_RSVD_FFFF \
42171 #define HWRM_NVM_SET_VARIABLE_INPUT_OPTION_NUM_LAST \
42172 HWRM_NVM_SET_VARIABLE_INPUT_OPTION_NUM_RSVD_FFFF
42174 * Number of dimensions for this nvm configuration variable.
42175 * This value indicates how many of the indexN values to use.
42176 * A value of 0 means that none of the indexN values are valid.
42177 * A value of 1 requires at index0 is valued, a value of 2
42178 * requires that index0 and index1 are valid, and so forth
42180 uint16_t dimensions;
42181 /* index for the 1st dimensions */
42183 /* index for the 2nd dimensions */
42185 /* index for the 3rd dimensions */
42187 /* index for the 4th dimensions */
42190 /* When this bit is 1, flush internal cache after this write operation (see hwrm_nvm_flush command.) */
42191 #define HWRM_NVM_SET_VARIABLE_INPUT_FLAGS_FORCE_FLUSH \
42193 /* encryption method */
42194 #define HWRM_NVM_SET_VARIABLE_INPUT_FLAGS_ENCRYPT_MODE_MASK \
42196 #define HWRM_NVM_SET_VARIABLE_INPUT_FLAGS_ENCRYPT_MODE_SFT 1
42197 /* No encryption. */
42198 #define HWRM_NVM_SET_VARIABLE_INPUT_FLAGS_ENCRYPT_MODE_NONE \
42199 (UINT32_C(0x0) << 1)
42200 /* one-way encryption. */
42201 #define HWRM_NVM_SET_VARIABLE_INPUT_FLAGS_ENCRYPT_MODE_HMAC_SHA1 \
42202 (UINT32_C(0x1) << 1)
42203 /* symmetric AES256 encryption. */
42204 #define HWRM_NVM_SET_VARIABLE_INPUT_FLAGS_ENCRYPT_MODE_AES256 \
42205 (UINT32_C(0x2) << 1)
42206 /* SHA1 digest appended to plaintext contents, for authentication */
42207 #define HWRM_NVM_SET_VARIABLE_INPUT_FLAGS_ENCRYPT_MODE_HMAC_SHA1_AUTH \
42208 (UINT32_C(0x3) << 1)
42209 #define HWRM_NVM_SET_VARIABLE_INPUT_FLAGS_ENCRYPT_MODE_LAST \
42210 HWRM_NVM_SET_VARIABLE_INPUT_FLAGS_ENCRYPT_MODE_HMAC_SHA1_AUTH
42211 #define HWRM_NVM_SET_VARIABLE_INPUT_FLAGS_FLAGS_UNUSED_0_MASK \
42213 #define HWRM_NVM_SET_VARIABLE_INPUT_FLAGS_FLAGS_UNUSED_0_SFT 4
42214 /* When this bit is 1, update the factory default region */
42215 #define HWRM_NVM_SET_VARIABLE_INPUT_FLAGS_FACTORY_DEFAULT \
42220 /* hwrm_nvm_set_variable_output (size:128b/16B) */
42221 struct hwrm_nvm_set_variable_output {
42222 /* The specific error status for the command. */
42223 uint16_t error_code;
42224 /* The HWRM command request type. */
42226 /* The sequence ID from the original command. */
42228 /* The length of the response data in number of bytes. */
42230 uint8_t unused_0[7];
42232 * This field is used in Output records to indicate that the output
42233 * is completely written to RAM. This field should be read as '1'
42234 * to indicate that the output has been completely written.
42235 * When writing a command completion or response to an internal processor,
42236 * the order of writes has to be such that this field is written last.
42241 /* hwrm_nvm_set_variable_cmd_err (size:64b/8B) */
42242 struct hwrm_nvm_set_variable_cmd_err {
42244 * command specific error codes that goes to
42245 * the cmd_err field in Common HWRM Error Response.
42248 /* Unknown error */
42249 #define HWRM_NVM_SET_VARIABLE_CMD_ERR_CODE_UNKNOWN UINT32_C(0x0)
42250 /* variable does not exist */
42251 #define HWRM_NVM_SET_VARIABLE_CMD_ERR_CODE_VAR_NOT_EXIST UINT32_C(0x1)
42252 /* configuration is corrupted and the variable cannot be saved */
42253 #define HWRM_NVM_SET_VARIABLE_CMD_ERR_CODE_CORRUPT_VAR UINT32_C(0x2)
42254 #define HWRM_NVM_SET_VARIABLE_CMD_ERR_CODE_LAST \
42255 HWRM_NVM_SET_VARIABLE_CMD_ERR_CODE_CORRUPT_VAR
42256 uint8_t unused_0[7];
42259 /****************************
42260 * hwrm_nvm_validate_option *
42261 ****************************/
42264 /* hwrm_nvm_validate_option_input (size:320b/40B) */
42265 struct hwrm_nvm_validate_option_input {
42266 /* The HWRM command request type. */
42269 * The completion ring to send the completion event on. This should
42270 * be the NQ ID returned from the `nq_alloc` HWRM command.
42272 uint16_t cmpl_ring;
42274 * The sequence ID is used by the driver for tracking multiple
42275 * commands. This ID is treated as opaque data by the firmware and
42276 * the value is returned in the `hwrm_resp_hdr` upon completion.
42280 * The target ID of the command:
42281 * * 0x0-0xFFF8 - The function ID
42282 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
42283 * * 0xFFFD - Reserved for user-space HWRM interface
42286 uint16_t target_id;
42288 * A physical address pointer pointing to a host buffer that the
42289 * command's response data will be written. This can be either a host
42290 * physical address (HPA) or a guest physical address (GPA) and must
42291 * point to a physically contiguous block of memory.
42293 uint64_t resp_addr;
42295 * This is the host address where
42296 * nvm variable will be copied from
42298 uint64_t src_data_addr;
42299 /* size of data in bits */
42301 /* nvm cfg option number */
42302 uint16_t option_num;
42304 #define HWRM_NVM_VALIDATE_OPTION_INPUT_OPTION_NUM_RSVD_0 \
42307 #define HWRM_NVM_VALIDATE_OPTION_INPUT_OPTION_NUM_RSVD_FFFF \
42309 #define HWRM_NVM_VALIDATE_OPTION_INPUT_OPTION_NUM_LAST \
42310 HWRM_NVM_VALIDATE_OPTION_INPUT_OPTION_NUM_RSVD_FFFF
42312 * Number of dimensions for this nvm configuration variable.
42313 * This value indicates how many of the indexN values to use.
42314 * A value of 0 means that none of the indexN values are valid.
42315 * A value of 1 requires at index0 is valued, a value of 2
42316 * requires that index0 and index1 are valid, and so forth
42318 uint16_t dimensions;
42319 /* index for the 1st dimensions */
42321 /* index for the 2nd dimensions */
42323 /* index for the 3rd dimensions */
42325 /* index for the 4th dimensions */
42327 uint8_t unused_0[2];
42330 /* hwrm_nvm_validate_option_output (size:128b/16B) */
42331 struct hwrm_nvm_validate_option_output {
42332 /* The specific error status for the command. */
42333 uint16_t error_code;
42334 /* The HWRM command request type. */
42336 /* The sequence ID from the original command. */
42338 /* The length of the response data in number of bytes. */
42341 /* indicates that the value provided for the option is not matching with the saved data. */
42342 #define HWRM_NVM_VALIDATE_OPTION_OUTPUT_RESULT_NOT_MATCH UINT32_C(0x0)
42343 /* indicates that the value provided for the option is matching the saved data. */
42344 #define HWRM_NVM_VALIDATE_OPTION_OUTPUT_RESULT_MATCH UINT32_C(0x1)
42345 #define HWRM_NVM_VALIDATE_OPTION_OUTPUT_RESULT_LAST \
42346 HWRM_NVM_VALIDATE_OPTION_OUTPUT_RESULT_MATCH
42347 uint8_t unused_0[6];
42349 * This field is used in Output records to indicate that the output
42350 * is completely written to RAM. This field should be read as '1'
42351 * to indicate that the output has been completely written.
42352 * When writing a command completion or response to an internal processor,
42353 * the order of writes has to be such that this field is written last.
42358 /* hwrm_nvm_validate_option_cmd_err (size:64b/8B) */
42359 struct hwrm_nvm_validate_option_cmd_err {
42361 * command specific error codes that goes to
42362 * the cmd_err field in Common HWRM Error Response.
42365 /* Unknown error */
42366 #define HWRM_NVM_VALIDATE_OPTION_CMD_ERR_CODE_UNKNOWN UINT32_C(0x0)
42367 #define HWRM_NVM_VALIDATE_OPTION_CMD_ERR_CODE_LAST \
42368 HWRM_NVM_VALIDATE_OPTION_CMD_ERR_CODE_UNKNOWN
42369 uint8_t unused_0[7];
42377 /* hwrm_oem_cmd_input (size:1024b/128B) */
42378 struct hwrm_oem_cmd_input {
42379 /* The HWRM command request type. */
42382 * The completion ring to send the completion event on. This should
42383 * be the NQ ID returned from the `nq_alloc` HWRM command.
42385 uint16_t cmpl_ring;
42387 * The sequence ID is used by the driver for tracking multiple
42388 * commands. This ID is treated as opaque data by the firmware and
42389 * the value is returned in the `hwrm_resp_hdr` upon completion.
42393 * The target ID of the command:
42394 * * 0x0-0xFFF8 - The function ID
42395 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
42396 * * 0xFFFD - Reserved for user-space HWRM interface
42399 uint16_t target_id;
42401 * A physical address pointer pointing to a host buffer that the
42402 * command's response data will be written. This can be either a host
42403 * physical address (HPA) or a guest physical address (GPA) and must
42404 * point to a physically contiguous block of memory.
42406 uint64_t resp_addr;
42409 /* This field contains the vendor specific command data. */
42410 uint32_t oem_data[26];
42413 /* hwrm_oem_cmd_output (size:768b/96B) */
42414 struct hwrm_oem_cmd_output {
42415 /* The specific error status for the command. */
42416 uint16_t error_code;
42417 /* The HWRM command request type. */
42419 /* The sequence ID from the original command. */
42421 /* The length of the response data in number of bytes. */
42425 /* This field contains the vendor specific response data. */
42426 uint32_t oem_data[18];
42427 uint8_t unused_1[7];
42429 * This field is used in Output records to indicate that the output
42430 * is completely written to RAM. This field should be read as '1'
42431 * to indicate that the output has been completely written.
42432 * When writing a command completion or response to an internal processor,
42433 * the order of writes has to be such that this field is written last.
42440 ******************/
42443 /* hwrm_fw_reset_input (size:192b/24B) */
42444 struct hwrm_fw_reset_input {
42445 /* The HWRM command request type. */
42448 * The completion ring to send the completion event on. This should
42449 * be the NQ ID returned from the `nq_alloc` HWRM command.
42451 uint16_t cmpl_ring;
42453 * The sequence ID is used by the driver for tracking multiple
42454 * commands. This ID is treated as opaque data by the firmware and
42455 * the value is returned in the `hwrm_resp_hdr` upon completion.
42459 * The target ID of the command:
42460 * * 0x0-0xFFF8 - The function ID
42461 * * 0xFFF8-0xFFFE - Reserved for internal processors
42464 uint16_t target_id;
42466 * A physical address pointer pointing to a host buffer that the
42467 * command's response data will be written. This can be either a host
42468 * physical address (HPA) or a guest physical address (GPA) and must
42469 * point to a physically contiguous block of memory.
42471 uint64_t resp_addr;
42472 /* Type of embedded processor. */
42473 uint8_t embedded_proc_type;
42474 /* Boot Processor */
42475 #define HWRM_FW_RESET_INPUT_EMBEDDED_PROC_TYPE_BOOT \
42477 /* Management Processor */
42478 #define HWRM_FW_RESET_INPUT_EMBEDDED_PROC_TYPE_MGMT \
42480 /* Network control processor */
42481 #define HWRM_FW_RESET_INPUT_EMBEDDED_PROC_TYPE_NETCTRL \
42483 /* RoCE control processor */
42484 #define HWRM_FW_RESET_INPUT_EMBEDDED_PROC_TYPE_ROCE \
42487 * Host (in multi-host environment): This is only valid if requester is IPC.
42488 * Reinit host hardware resources and PCIe.
42490 #define HWRM_FW_RESET_INPUT_EMBEDDED_PROC_TYPE_HOST \
42492 /* AP processor complex (in multi-host environment). Use host_idx to control which core is reset */
42493 #define HWRM_FW_RESET_INPUT_EMBEDDED_PROC_TYPE_AP \
42495 /* Reset all blocks of the chip (including all processors) */
42496 #define HWRM_FW_RESET_INPUT_EMBEDDED_PROC_TYPE_CHIP \
42499 * Host (in multi-host environment): This is only valid if requester is IPC.
42500 * Reinit host hardware resources.
42502 #define HWRM_FW_RESET_INPUT_EMBEDDED_PROC_TYPE_HOST_RESOURCE_REINIT \
42504 #define HWRM_FW_RESET_INPUT_EMBEDDED_PROC_TYPE_LAST \
42505 HWRM_FW_RESET_INPUT_EMBEDDED_PROC_TYPE_HOST_RESOURCE_REINIT
42506 /* Type of self reset. */
42507 uint8_t selfrst_status;
42508 /* No Self Reset */
42509 #define HWRM_FW_RESET_INPUT_SELFRST_STATUS_SELFRSTNONE \
42511 /* Self Reset as soon as possible to do so safely */
42512 #define HWRM_FW_RESET_INPUT_SELFRST_STATUS_SELFRSTASAP \
42514 /* Self Reset on PCIe Reset */
42515 #define HWRM_FW_RESET_INPUT_SELFRST_STATUS_SELFRSTPCIERST \
42517 /* Self Reset immediately after notification to all clients. */
42518 #define HWRM_FW_RESET_INPUT_SELFRST_STATUS_SELFRSTIMMEDIATE \
42520 #define HWRM_FW_RESET_INPUT_SELFRST_STATUS_LAST \
42521 HWRM_FW_RESET_INPUT_SELFRST_STATUS_SELFRSTIMMEDIATE
42523 * Indicate which host is being reset. 0 means first host.
42524 * Only valid when embedded_proc_type is host in multihost
42530 * When this bit is '1', then the core firmware initiates
42531 * the reset only after graceful shut down of all registered instances.
42532 * If not, the device will continue with the existing firmware.
42534 #define HWRM_FW_RESET_INPUT_FLAGS_RESET_GRACEFUL UINT32_C(0x1)
42535 uint8_t unused_0[4];
42538 /* hwrm_fw_reset_output (size:128b/16B) */
42539 struct hwrm_fw_reset_output {
42540 /* The specific error status for the command. */
42541 uint16_t error_code;
42542 /* The HWRM command request type. */
42544 /* The sequence ID from the original command. */
42546 /* The length of the response data in number of bytes. */
42548 /* Type of self reset. */
42549 uint8_t selfrst_status;
42550 /* No Self Reset */
42551 #define HWRM_FW_RESET_OUTPUT_SELFRST_STATUS_SELFRSTNONE \
42553 /* Self Reset as soon as possible to do so safely */
42554 #define HWRM_FW_RESET_OUTPUT_SELFRST_STATUS_SELFRSTASAP \
42556 /* Self Reset on PCIe Reset */
42557 #define HWRM_FW_RESET_OUTPUT_SELFRST_STATUS_SELFRSTPCIERST \
42559 /* Self Reset immediately after notification to all clients. */
42560 #define HWRM_FW_RESET_OUTPUT_SELFRST_STATUS_SELFRSTIMMEDIATE \
42562 #define HWRM_FW_RESET_OUTPUT_SELFRST_STATUS_LAST \
42563 HWRM_FW_RESET_OUTPUT_SELFRST_STATUS_SELFRSTIMMEDIATE
42564 uint8_t unused_0[6];
42566 * This field is used in Output records to indicate that the output
42567 * is completely written to RAM. This field should be read as '1'
42568 * to indicate that the output has been completely written.
42569 * When writing a command completion or response to an internal processor,
42570 * the order of writes has to be such that this field is written last.
42575 /**********************
42576 * hwrm_port_ts_query *
42577 ***********************/
42580 /* hwrm_port_ts_query_input (size:192b/24B) */
42581 struct hwrm_port_ts_query_input {
42582 /* The HWRM command request type. */
42585 * The completion ring to send the completion event on. This should
42586 * be the NQ ID returned from the `nq_alloc` HWRM command.
42588 uint16_t cmpl_ring;
42590 * The sequence ID is used by the driver for tracking multiple
42591 * commands. This ID is treated as opaque data by the firmware and
42592 * the value is returned in the `hwrm_resp_hdr` upon completion.
42596 * The target ID of the command:
42597 * * 0x0-0xFFF8 - The function ID
42598 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
42599 * * 0xFFFD - Reserved for user-space HWRM interface
42602 uint16_t target_id;
42604 * A physical address pointer pointing to a host buffer that the
42605 * command's response data will be written. This can be either a host
42606 * physical address (HPA) or a guest physical address (GPA) and must
42607 * point to a physically contiguous block of memory.
42609 uint64_t resp_addr;
42612 * Enumeration denoting the RX, TX type of the resource.
42613 * This enumeration is used for resources that are similar for both
42614 * TX and RX paths of the chip.
42616 #define HWRM_PORT_TS_QUERY_INPUT_FLAGS_PATH 0x1UL
42618 #define HWRM_PORT_TS_QUERY_INPUT_FLAGS_PATH_TX 0x0UL
42620 #define HWRM_PORT_TS_QUERY_INPUT_FLAGS_PATH_RX 0x1UL
42621 #define HWRM_PORT_TS_QUERY_INPUT_FLAGS_PATH_LAST \
42622 HWRM_PORT_TS_QUERY_INPUT_FLAGS_PATH_RX
42624 * If set, the response includes the current value of the free
42627 #define HWRM_PORT_TS_QUERY_INPUT_FLAGS_CURRENT_TIME 0x2UL
42628 /* Port ID of port that is being queried. */
42630 uint8_t unused_0[2];
42633 /* hwrm_port_ts_query_output (size:192b/24B) */
42634 struct hwrm_port_ts_query_output {
42635 /* The specific error status for the command. */
42636 uint16_t error_code;
42637 /* The HWRM command request type. */
42639 /* The sequence ID from the original command. */
42641 /* The length of the response data in number of bytes. */
42644 * Timestamp value of PTP message captured, or current value of
42645 * free running timer.
42647 uint32_t ptp_msg_ts[2];
42648 /* Sequence ID of the PTP message captured. */
42649 uint16_t ptp_msg_seqid;
42650 uint8_t unused_0[5];
42652 * This field is used in Output records to indicate that the output
42653 * is completely written to RAM. This field should be read as '1'
42654 * to indicate that the output has been completely written.
42655 * When writing a command completion or response to an internal processor,
42656 * the order of writes has to be such that this field is written last.
42662 * This structure is fixed at the beginning of the ChiMP SRAM (GRC
42663 * offset: 0x31001F0). Host software is expected to read from this
42664 * location for a defined signature. If it exists, the software can
42665 * assume the presence of this structure and the validity of the
42666 * FW_STATUS location in the next field.
42668 /* hcomm_status (size:64b/8B) */
42669 struct hcomm_status {
42672 * This field defines the version of the structure. The latest
42673 * version value is 1.
42675 #define HCOMM_STATUS_VER_MASK UINT32_C(0xff)
42676 #define HCOMM_STATUS_VER_SFT 0
42677 #define HCOMM_STATUS_VER_LATEST UINT32_C(0x1)
42678 #define HCOMM_STATUS_VER_LAST HCOMM_STATUS_VER_LATEST
42680 * This field is to store the signature value to indicate the
42681 * presence of the structure.
42683 #define HCOMM_STATUS_SIGNATURE_MASK UINT32_C(0xffffff00)
42684 #define HCOMM_STATUS_SIGNATURE_SFT 8
42685 #define HCOMM_STATUS_SIGNATURE_VAL (UINT32_C(0x484353) << 8)
42686 #define HCOMM_STATUS_SIGNATURE_LAST HCOMM_STATUS_SIGNATURE_VAL
42687 uint32_t fw_status_loc;
42688 #define HCOMM_STATUS_TRUE_ADDR_SPACE_MASK UINT32_C(0x3)
42689 #define HCOMM_STATUS_TRUE_ADDR_SPACE_SFT 0
42690 /* PCIE configuration space */
42691 #define HCOMM_STATUS_FW_STATUS_LOC_ADDR_SPACE_PCIE_CFG UINT32_C(0x0)
42693 #define HCOMM_STATUS_FW_STATUS_LOC_ADDR_SPACE_GRC UINT32_C(0x1)
42695 #define HCOMM_STATUS_FW_STATUS_LOC_ADDR_SPACE_BAR0 UINT32_C(0x2)
42697 #define HCOMM_STATUS_FW_STATUS_LOC_ADDR_SPACE_BAR1 UINT32_C(0x3)
42698 #define HCOMM_STATUS_FW_STATUS_LOC_ADDR_SPACE_LAST \
42699 HCOMM_STATUS_FW_STATUS_LOC_ADDR_SPACE_BAR1
42701 * This offset where the fw_status register is located. The value
42702 * is generally 4-byte aligned.
42704 #define HCOMM_STATUS_TRUE_OFFSET_MASK UINT32_C(0xfffffffc)
42705 #define HCOMM_STATUS_TRUE_OFFSET_SFT 2
42707 /* This is the GRC offset where the hcomm_status struct resides. */
42708 #define HCOMM_STATUS_STRUCT_LOC 0x31001F0UL
42710 /**************************
42711 * hwrm_cfa_counter_qcaps *
42712 **************************/
42715 /* hwrm_cfa_counter_qcaps_input (size:128b/16B) */
42716 struct hwrm_cfa_counter_qcaps_input {
42717 /* The HWRM command request type. */
42720 * The completion ring to send the completion event on. This should
42721 * be the NQ ID returned from the `nq_alloc` HWRM command.
42723 uint16_t cmpl_ring;
42725 * The sequence ID is used by the driver for tracking multiple
42726 * commands. This ID is treated as opaque data by the firmware and
42727 * the value is returned in the `hwrm_resp_hdr` upon completion.
42731 * The target ID of the command:
42732 * * 0x0-0xFFF8 - The function ID
42733 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
42734 * * 0xFFFD - Reserved for user-space HWRM interface
42737 uint16_t target_id;
42739 * A physical address pointer pointing to a host buffer that the
42740 * command's response data will be written. This can be either a host
42741 * physical address (HPA) or a guest physical address (GPA) and must
42742 * point to a physically contiguous block of memory.
42744 uint64_t resp_addr;
42747 /* hwrm_cfa_counter_qcaps_output (size:576b/72B) */
42748 struct hwrm_cfa_counter_qcaps_output {
42749 /* The specific error status for the command. */
42750 uint16_t error_code;
42751 /* The HWRM command request type. */
42753 /* The sequence ID from the original command. */
42755 /* The length of the response data in number of bytes. */
42758 /* Enumeration denoting the supported CFA counter format. */
42759 #define HWRM_CFA_COUNTER_QCAPS_OUTPUT_FLAGS_COUNTER_FORMAT \
42761 /* CFA counter types are not supported. */
42762 #define HWRM_CFA_COUNTER_QCAPS_OUTPUT_FLAGS_COUNTER_FORMAT_NONE \
42764 /* 64-bit packet counters followed by 64-bit byte counters format. */
42765 #define HWRM_CFA_COUNTER_QCAPS_OUTPUT_FLAGS_COUNTER_FORMAT_64_BIT \
42767 #define HWRM_CFA_COUNTER_QCAPS_OUTPUT_FLAGS_COUNTER_FORMAT_LAST \
42768 HWRM_CFA_COUNTER_QCAPS_OUTPUT_FLAGS_COUNTER_FORMAT_64_BIT
42770 /* Minimum guaranteed number of flow counters supported for this function, in RX direction. */
42771 uint32_t min_rx_fc;
42772 /* Maximum non-guaranteed number of flow counters supported for this function, in RX direction. */
42773 uint32_t max_rx_fc;
42774 /* Minimum guaranteed number of flow counters supported for this function, in TX direction. */
42775 uint32_t min_tx_fc;
42776 /* Maximum non-guaranteed number of flow counters supported for this function, in TX direction. */
42777 uint32_t max_tx_fc;
42778 /* Minimum guaranteed number of extension flow counters supported for this function, in RX direction. */
42779 uint32_t min_rx_efc;
42780 /* Maximum non-guaranteed number of extension flow counters supported for this function, in RX direction. */
42781 uint32_t max_rx_efc;
42782 /* Minimum guaranteed number of extension flow counters supported for this function, in TX direction. */
42783 uint32_t min_tx_efc;
42784 /* Maximum non-guaranteed number of extension flow counters supported for this function, in TX direction. */
42785 uint32_t max_tx_efc;
42786 /* Minimum guaranteed number of meter drop counters supported for this function, in RX direction. */
42787 uint32_t min_rx_mdc;
42788 /* Maximum non-guaranteed number of meter drop counters supported for this function, in RX direction. */
42789 uint32_t max_rx_mdc;
42790 /* Minimum guaranteed number of meter drop counters supported for this function, in TX direction. */
42791 uint32_t min_tx_mdc;
42792 /* Maximum non-guaranteed number of meter drop counters supported for this function, in TX direction. */
42793 uint32_t max_tx_mdc;
42794 /* Maximum guaranteed number of flow counters which can be used during flow alloc. */
42795 uint32_t max_flow_alloc_fc;
42796 uint8_t unused_1[3];
42798 * This field is used in Output records to indicate that the output
42799 * is completely written to RAM. This field should be read as '1'
42800 * to indicate that the output has been completely written.
42801 * When writing a command completion or response to an internal processor,
42802 * the order of writes has to be such that this field is written last.
42807 /************************
42808 * hwrm_cfa_counter_cfg *
42809 ************************/
42812 /* hwrm_cfa_counter_cfg_input (size:256b/32B) */
42813 struct hwrm_cfa_counter_cfg_input {
42814 /* The HWRM command request type. */
42817 * The completion ring to send the completion event on. This should
42818 * be the NQ ID returned from the `nq_alloc` HWRM command.
42820 uint16_t cmpl_ring;
42822 * The sequence ID is used by the driver for tracking multiple
42823 * commands. This ID is treated as opaque data by the firmware and
42824 * the value is returned in the `hwrm_resp_hdr` upon completion.
42828 * The target ID of the command:
42829 * * 0x0-0xFFF8 - The function ID
42830 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
42831 * * 0xFFFD - Reserved for user-space HWRM interface
42834 uint16_t target_id;
42836 * A physical address pointer pointing to a host buffer that the
42837 * command's response data will be written. This can be either a host
42838 * physical address (HPA) or a guest physical address (GPA) and must
42839 * point to a physically contiguous block of memory.
42841 uint64_t resp_addr;
42843 /* Enumeration denoting the configuration mode. */
42844 #define HWRM_CFA_COUNTER_CFG_INPUT_FLAGS_CFG_MODE \
42846 /* Disable the configuration mode. */
42847 #define HWRM_CFA_COUNTER_CFG_INPUT_FLAGS_CFG_MODE_DISABLE \
42849 /* Enable the configuration mode. */
42850 #define HWRM_CFA_COUNTER_CFG_INPUT_FLAGS_CFG_MODE_ENABLE \
42852 #define HWRM_CFA_COUNTER_CFG_INPUT_FLAGS_CFG_MODE_LAST \
42853 HWRM_CFA_COUNTER_CFG_INPUT_FLAGS_CFG_MODE_ENABLE
42854 /* Enumeration denoting the RX, TX type of the resource. */
42855 #define HWRM_CFA_COUNTER_CFG_INPUT_FLAGS_PATH \
42858 #define HWRM_CFA_COUNTER_CFG_INPUT_FLAGS_PATH_TX \
42859 (UINT32_C(0x0) << 1)
42861 #define HWRM_CFA_COUNTER_CFG_INPUT_FLAGS_PATH_RX \
42862 (UINT32_C(0x1) << 1)
42863 #define HWRM_CFA_COUNTER_CFG_INPUT_FLAGS_PATH_LAST \
42864 HWRM_CFA_COUNTER_CFG_INPUT_FLAGS_PATH_RX
42865 /* Enumeration denoting the data transfer mode. */
42866 #define HWRM_CFA_COUNTER_CFG_INPUT_FLAGS_DATA_TRANSFER_MODE_MASK \
42868 #define HWRM_CFA_COUNTER_CFG_INPUT_FLAGS_DATA_TRANSFER_MODE_SFT 2
42870 #define HWRM_CFA_COUNTER_CFG_INPUT_FLAGS_DATA_TRANSFER_MODE_PUSH \
42871 (UINT32_C(0x0) << 2)
42873 #define HWRM_CFA_COUNTER_CFG_INPUT_FLAGS_DATA_TRANSFER_MODE_PULL \
42874 (UINT32_C(0x1) << 2)
42875 /* Pull on async update. */
42876 #define HWRM_CFA_COUNTER_CFG_INPUT_FLAGS_DATA_TRANSFER_MODE_PULL_ASYNC \
42877 (UINT32_C(0x2) << 2)
42878 #define HWRM_CFA_COUNTER_CFG_INPUT_FLAGS_DATA_TRANSFER_MODE_LAST \
42879 HWRM_CFA_COUNTER_CFG_INPUT_FLAGS_DATA_TRANSFER_MODE_PULL_ASYNC
42880 uint16_t counter_type;
42881 /* Flow counters. */
42882 #define HWRM_CFA_COUNTER_CFG_INPUT_COUNTER_TYPE_FC UINT32_C(0x0)
42883 /* Extended flow counters. */
42884 #define HWRM_CFA_COUNTER_CFG_INPUT_COUNTER_TYPE_EFC UINT32_C(0x1)
42885 /* Meter drop counters. */
42886 #define HWRM_CFA_COUNTER_CFG_INPUT_COUNTER_TYPE_MDC UINT32_C(0x2)
42887 #define HWRM_CFA_COUNTER_CFG_INPUT_COUNTER_TYPE_LAST \
42888 HWRM_CFA_COUNTER_CFG_INPUT_COUNTER_TYPE_MDC
42889 /* Ctx memory handle to be used for the counter. */
42891 /* Counter update cadence hint (only in Push mode). */
42892 uint16_t update_tmr_ms;
42893 /* Total number of entries. */
42894 uint32_t num_entries;
42898 /* hwrm_cfa_counter_cfg_output (size:128b/16B) */
42899 struct hwrm_cfa_counter_cfg_output {
42900 /* The specific error status for the command. */
42901 uint16_t error_code;
42902 /* The HWRM command request type. */
42904 /* The sequence ID from the original command. */
42906 /* The length of the response data in number of bytes. */
42908 uint8_t unused_0[7];
42910 * This field is used in Output records to indicate that the output
42911 * is completely written to RAM. This field should be read as '1'
42912 * to indicate that the output has been completely written.
42913 * When writing a command completion or response to an internal processor,
42914 * the order of writes has to be such that this field is written last.
42919 /***************************
42920 * hwrm_cfa_counter_qstats *
42921 ***************************/
42924 /* hwrm_cfa_counter_qstats_input (size:320b/40B) */
42925 struct hwrm_cfa_counter_qstats_input {
42926 /* The HWRM command request type. */
42929 * The completion ring to send the completion event on. This should
42930 * be the NQ ID returned from the `nq_alloc` HWRM command.
42932 uint16_t cmpl_ring;
42934 * The sequence ID is used by the driver for tracking multiple
42935 * commands. This ID is treated as opaque data by the firmware and
42936 * the value is returned in the `hwrm_resp_hdr` upon completion.
42940 * The target ID of the command:
42941 * * 0x0-0xFFF8 - The function ID
42942 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
42943 * * 0xFFFD - Reserved for user-space HWRM interface
42946 uint16_t target_id;
42948 * A physical address pointer pointing to a host buffer that the
42949 * command's response data will be written. This can be either a host
42950 * physical address (HPA) or a guest physical address (GPA) and must
42951 * point to a physically contiguous block of memory.
42953 uint64_t resp_addr;
42955 /* Enumeration denoting the RX, TX type of the resource. */
42956 #define HWRM_CFA_COUNTER_QSTATS_INPUT_FLAGS_PATH UINT32_C(0x1)
42958 #define HWRM_CFA_COUNTER_QSTATS_INPUT_FLAGS_PATH_TX UINT32_C(0x0)
42960 #define HWRM_CFA_COUNTER_QSTATS_INPUT_FLAGS_PATH_RX UINT32_C(0x1)
42961 #define HWRM_CFA_COUNTER_QSTATS_INPUT_FLAGS_PATH_LAST \
42962 HWRM_CFA_COUNTER_QSTATS_INPUT_FLAGS_PATH_RX
42963 uint16_t counter_type;
42964 uint16_t input_flow_ctx_id;
42965 uint16_t num_entries;
42966 uint16_t delta_time_ms;
42967 uint16_t meter_instance_id;
42968 uint16_t mdc_ctx_id;
42969 uint8_t unused_0[2];
42970 uint64_t expected_count;
42973 /* hwrm_cfa_counter_qstats_output (size:128b/16B) */
42974 struct hwrm_cfa_counter_qstats_output {
42975 /* The specific error status for the command. */
42976 uint16_t error_code;
42977 /* The HWRM command request type. */
42979 /* The sequence ID from the original command. */
42981 /* The length of the response data in number of bytes. */
42983 uint8_t unused_0[7];
42985 * This field is used in Output records to indicate that the output
42986 * is completely written to RAM. This field should be read as '1'
42987 * to indicate that the output has been completely written.
42988 * When writing a command completion or response to an internal processor,
42989 * the order of writes has to be such that this field is written last.
42994 /***********************
42995 * hwrm_cfa_pair_alloc *
42996 ***********************/
42999 /* hwrm_cfa_pair_alloc_input (size:576b/72B) */
43000 struct hwrm_cfa_pair_alloc_input {
43001 /* The HWRM command request type. */
43004 * The completion ring to send the completion event on. This should
43005 * be the NQ ID returned from the `nq_alloc` HWRM command.
43007 uint16_t cmpl_ring;
43009 * The sequence ID is used by the driver for tracking multiple
43010 * commands. This ID is treated as opaque data by the firmware and
43011 * the value is returned in the `hwrm_resp_hdr` upon completion.
43015 * The target ID of the command:
43016 * * 0x0-0xFFF8 - The function ID
43017 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
43018 * * 0xFFFD - Reserved for user-space HWRM interface
43021 uint16_t target_id;
43023 * A physical address pointer pointing to a host buffer that the
43024 * command's response data will be written. This can be either a host
43025 * physical address (HPA) or a guest physical address (GPA) and must
43026 * point to a physically contiguous block of memory.
43028 uint64_t resp_addr;
43030 * Pair mode (0-vf2fn, 1-rep2fn, 2-rep2rep, 3-proxy, 4-pfpair,
43031 * 5-rep2fn_mod, 6-rep2fn_modall, 7-rep2fn_truflow).
43033 uint16_t pair_mode;
43034 /* Pair between VF on local host with PF or VF on specified host. */
43035 #define HWRM_CFA_PAIR_ALLOC_INPUT_PAIR_MODE_VF2FN \
43037 /* Pair between REP on local host with PF or VF on specified host. */
43038 #define HWRM_CFA_PAIR_ALLOC_INPUT_PAIR_MODE_REP2FN \
43040 /* Pair between REP on local host with REP on specified host. */
43041 #define HWRM_CFA_PAIR_ALLOC_INPUT_PAIR_MODE_REP2REP \
43043 /* Pair for the proxy interface. */
43044 #define HWRM_CFA_PAIR_ALLOC_INPUT_PAIR_MODE_PROXY \
43046 /* Pair for the PF interface. */
43047 #define HWRM_CFA_PAIR_ALLOC_INPUT_PAIR_MODE_PFPAIR \
43049 /* Modify existing rep2fn pair and move pair to new PF. */
43050 #define HWRM_CFA_PAIR_ALLOC_INPUT_PAIR_MODE_REP2FN_MOD \
43052 /* Modify existing rep2fn pairs paired with same PF and move pairs to new PF. */
43053 #define HWRM_CFA_PAIR_ALLOC_INPUT_PAIR_MODE_REP2FN_MODALL \
43055 /* Truflow pair between REP on local host with PF or VF on specified host. */
43056 #define HWRM_CFA_PAIR_ALLOC_INPUT_PAIR_MODE_REP2FN_TRUFLOW \
43058 #define HWRM_CFA_PAIR_ALLOC_INPUT_PAIR_MODE_LAST \
43059 HWRM_CFA_PAIR_ALLOC_INPUT_PAIR_MODE_REP2FN_TRUFLOW
43060 /* Logical VF number (range: 0 -> MAX_VFS -1). */
43062 /* Logical Host (0xff-local host). */
43064 /* Logical PF (0xff-PF for command channel). */
43066 /* Logical VF number (range: 0 -> MAX_VFS -1). */
43068 /* Loopback port (0xff-internal loopback), valid for mode-3. */
43070 /* Priority used for encap of loopback packets valid for mode-3. */
43072 /* New PF for rep2fn modify, valid for mode 5. */
43073 uint16_t new_pf_fid;
43076 * This bit must be '1' for the q_ab field to be
43079 #define HWRM_CFA_PAIR_ALLOC_INPUT_ENABLES_Q_AB_VALID UINT32_C(0x1)
43081 * This bit must be '1' for the q_ba field to be
43084 #define HWRM_CFA_PAIR_ALLOC_INPUT_ENABLES_Q_BA_VALID UINT32_C(0x2)
43086 * This bit must be '1' for the fc_ab field to be
43089 #define HWRM_CFA_PAIR_ALLOC_INPUT_ENABLES_FC_AB_VALID UINT32_C(0x4)
43091 * This bit must be '1' for the fc_ba field to be
43094 #define HWRM_CFA_PAIR_ALLOC_INPUT_ENABLES_FC_BA_VALID UINT32_C(0x8)
43095 /* VF Pair name (32 byte string). */
43096 char pair_name[32];
43098 * The q_ab value specifies the logical index of the TX/RX CoS
43099 * queue to be assigned for traffic in the A to B direction of
43100 * the interface pair. The default value is 0.
43104 * The q_ba value specifies the logical index of the TX/RX CoS
43105 * queue to be assigned for traffic in the B to A direction of
43106 * the interface pair. The default value is 1.
43110 * Specifies whether RX ring flow control is disabled (0) or enabled
43111 * (1) in the A to B direction. The default value is 0, meaning that
43112 * packets will be dropped when the B-side RX rings are full.
43116 * Specifies whether RX ring flow control is disabled (0) or enabled
43117 * (1) in the B to A direction. The default value is 1, meaning that
43118 * the RX CoS queue will be flow controlled when the A-side RX rings
43122 uint8_t unused_1[4];
43125 /* hwrm_cfa_pair_alloc_output (size:192b/24B) */
43126 struct hwrm_cfa_pair_alloc_output {
43127 /* The specific error status for the command. */
43128 uint16_t error_code;
43129 /* The HWRM command request type. */
43131 /* The sequence ID from the original command. */
43133 /* The length of the response data in number of bytes. */
43135 /* Only valid for modes 1 and 2. */
43136 uint16_t rx_cfa_code_a;
43137 /* Only valid for modes 1 and 2. */
43138 uint16_t tx_cfa_action_a;
43139 /* Only valid for mode 2. */
43140 uint16_t rx_cfa_code_b;
43141 /* Only valid for mode 2. */
43142 uint16_t tx_cfa_action_b;
43143 uint8_t unused_0[7];
43145 * This field is used in Output records to indicate that the output
43146 * is completely written to RAM. This field should be read as '1'
43147 * to indicate that the output has been completely written.
43148 * When writing a command completion or response to an internal processor,
43149 * the order of writes has to be such that this field is written last.
43154 /**********************
43155 * hwrm_cfa_pair_free *
43156 **********************/
43159 /* hwrm_cfa_pair_free_input (size:448b/56B) */
43160 struct hwrm_cfa_pair_free_input {
43161 /* The HWRM command request type. */
43164 * The completion ring to send the completion event on. This should
43165 * be the NQ ID returned from the `nq_alloc` HWRM command.
43167 uint16_t cmpl_ring;
43169 * The sequence ID is used by the driver for tracking multiple
43170 * commands. This ID is treated as opaque data by the firmware and
43171 * the value is returned in the `hwrm_resp_hdr` upon completion.
43175 * The target ID of the command:
43176 * * 0x0-0xFFF8 - The function ID
43177 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
43178 * * 0xFFFD - Reserved for user-space HWRM interface
43181 uint16_t target_id;
43183 * A physical address pointer pointing to a host buffer that the
43184 * command's response data will be written. This can be either a host
43185 * physical address (HPA) or a guest physical address (GPA) and must
43186 * point to a physically contiguous block of memory.
43188 uint64_t resp_addr;
43189 /* VF Pair name (32 byte string). */
43190 char pair_name[32];
43191 /* Logical PF (0xff-PF for command channel). */
43193 uint8_t unused_0[3];
43194 /* Logical VF number (range: 0 -> MAX_VFS -1). */
43197 * Pair mode (0-vf2fn, 1-rep2fn, 2-rep2rep, 3-proxy, 4-pfpair,
43198 * 5-rep2fn_mod, 6-rep2fn_modall, 7-rep2fn_truflow).
43200 uint16_t pair_mode;
43201 /* Pair between VF on local host with PF or VF on specified host. */
43202 #define HWRM_CFA_PAIR_FREE_INPUT_PAIR_MODE_VF2FN UINT32_C(0x0)
43203 /* Pair between REP on local host with PF or VF on specified host. */
43204 #define HWRM_CFA_PAIR_FREE_INPUT_PAIR_MODE_REP2FN UINT32_C(0x1)
43205 /* Pair between REP on local host with REP on specified host. */
43206 #define HWRM_CFA_PAIR_FREE_INPUT_PAIR_MODE_REP2REP UINT32_C(0x2)
43207 /* Pair for the proxy interface. */
43208 #define HWRM_CFA_PAIR_FREE_INPUT_PAIR_MODE_PROXY UINT32_C(0x3)
43209 /* Pair for the PF interface. */
43210 #define HWRM_CFA_PAIR_FREE_INPUT_PAIR_MODE_PFPAIR UINT32_C(0x4)
43211 /* Modify existing rep2fn pair and move pair to new PF. */
43212 #define HWRM_CFA_PAIR_FREE_INPUT_PAIR_MODE_REP2FN_MOD UINT32_C(0x5)
43213 /* Modify existing rep2fn pairs paired with same PF and move pairs to new PF. */
43214 #define HWRM_CFA_PAIR_FREE_INPUT_PAIR_MODE_REP2FN_MODALL UINT32_C(0x6)
43215 /* Truflow pair between REP on local host with PF or VF on specified host. */
43216 #define HWRM_CFA_PAIR_FREE_INPUT_PAIR_MODE_REP2FN_TRUFLOW UINT32_C(0x7)
43217 #define HWRM_CFA_PAIR_FREE_INPUT_PAIR_MODE_LAST \
43218 HWRM_CFA_PAIR_FREE_INPUT_PAIR_MODE_REP2FN_TRUFLOW
43221 /* hwrm_cfa_pair_free_output (size:128b/16B) */
43222 struct hwrm_cfa_pair_free_output {
43223 /* The specific error status for the command. */
43224 uint16_t error_code;
43225 /* The HWRM command request type. */
43227 /* The sequence ID from the original command. */
43229 /* The length of the response data in number of bytes. */
43231 uint8_t unused_0[7];
43233 * This field is used in Output records to indicate that the output
43234 * is completely written to RAM. This field should be read as '1'
43235 * to indicate that the output has been completely written.
43236 * When writing a command completion or response to an internal processor,
43237 * the order of writes has to be such that this field is written last.
43242 #endif /* _HSI_STRUCT_DEF_DPDK_H_ */