1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright (c) 2014-2021 Broadcom Inc.
5 * DO NOT MODIFY!!! This file is automatically generated.
8 #ifndef _HSI_STRUCT_DEF_DPDK_H_
9 #define _HSI_STRUCT_DEF_DPDK_H_
11 /* This is the HWRM command header. */
12 /* hwrm_cmd_hdr (size:128b/16B) */
14 /* The HWRM command request type. */
17 * The completion ring to send the completion event on. This should
18 * be the NQ ID returned from the `nq_alloc` HWRM command.
22 * The sequence ID is used by the driver for tracking multiple
23 * commands. This ID is treated as opaque data by the firmware and
24 * the value is returned in the `hwrm_resp_hdr` upon completion.
28 * The target ID of the command:
29 * * 0x0-0xFFF8 - The function ID
30 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
31 * * 0xFFFD - Reserved for user-space HWRM interface
36 * A physical address pointer pointing to a host buffer that the
37 * command's response data will be written. This can be either a host
38 * physical address (HPA) or a guest physical address (GPA) and must
39 * point to a physically contiguous block of memory.
44 /* This is the HWRM response header. */
45 /* hwrm_resp_hdr (size:64b/8B) */
46 struct hwrm_resp_hdr {
47 /* The specific error status for the command. */
49 /* The HWRM command request type. */
51 /* The sequence ID from the original command. */
53 /* The length of the response data in number of bytes. */
58 * TLV encapsulated message. Use the TLV type field of the
59 * TLV to determine the type of message encapsulated.
61 #define CMD_DISCR_TLV_ENCAP UINT32_C(0x8000)
62 #define CMD_DISCR_LAST CMD_DISCR_TLV_ENCAP
65 /* HWRM request message */
66 #define TLV_TYPE_HWRM_REQUEST UINT32_C(0x1)
67 /* HWRM response message */
68 #define TLV_TYPE_HWRM_RESPONSE UINT32_C(0x2)
69 /* RoCE slow path command */
70 #define TLV_TYPE_ROCE_SP_COMMAND UINT32_C(0x3)
71 /* RoCE slow path command to query CC Gen1 support. */
72 #define TLV_TYPE_QUERY_ROCE_CC_GEN1 UINT32_C(0x4)
73 /* RoCE slow path command to modify CC Gen1 support. */
74 #define TLV_TYPE_MODIFY_ROCE_CC_GEN1 UINT32_C(0x5)
75 /* Engine CKV - The Alias key EC curve and ECC public key information. */
76 #define TLV_TYPE_ENGINE_CKV_ALIAS_ECC_PUBLIC_KEY UINT32_C(0x8001)
77 /* Engine CKV - Initialization vector. */
78 #define TLV_TYPE_ENGINE_CKV_IV UINT32_C(0x8003)
79 /* Engine CKV - Authentication tag. */
80 #define TLV_TYPE_ENGINE_CKV_AUTH_TAG UINT32_C(0x8004)
81 /* Engine CKV - The encrypted data. */
82 #define TLV_TYPE_ENGINE_CKV_CIPHERTEXT UINT32_C(0x8005)
83 /* Engine CKV - Supported host_algorithms. */
84 #define TLV_TYPE_ENGINE_CKV_HOST_ALGORITHMS UINT32_C(0x8006)
85 /* Engine CKV - The Host EC curve name and ECC public key information. */
86 #define TLV_TYPE_ENGINE_CKV_HOST_ECC_PUBLIC_KEY UINT32_C(0x8007)
87 /* Engine CKV - The ECDSA signature. */
88 #define TLV_TYPE_ENGINE_CKV_ECDSA_SIGNATURE UINT32_C(0x8008)
89 /* Engine CKV - The firmware EC curve name and ECC public key information. */
90 #define TLV_TYPE_ENGINE_CKV_FW_ECC_PUBLIC_KEY UINT32_C(0x8009)
91 /* Engine CKV - Supported firmware algorithms. */
92 #define TLV_TYPE_ENGINE_CKV_FW_ALGORITHMS UINT32_C(0x800a)
93 #define TLV_TYPE_LAST \
94 TLV_TYPE_ENGINE_CKV_FW_ALGORITHMS
97 /* tlv (size:64b/8B) */
100 * The command discriminator is used to differentiate between various
101 * types of HWRM messages. This includes legacy HWRM and RoCE slowpath
102 * command messages as well as newer TLV encapsulated HWRM commands.
104 * For TLV encapsulated messages this field must be 0x8000.
110 * Indicates the presence of additional TLV encapsulated data
113 #define TLV_FLAGS_MORE UINT32_C(0x1)
114 /* Last TLV in a sequence of TLVs. */
115 #define TLV_FLAGS_MORE_LAST UINT32_C(0x0)
116 /* More TLVs follow this TLV. */
117 #define TLV_FLAGS_MORE_NOT_LAST UINT32_C(0x1)
119 * When an HWRM receiver detects a TLV type that it does not
120 * support with the TLV required flag set, the receiver must
121 * reject the HWRM message with an error code indicating an
122 * unsupported TLV type.
124 #define TLV_FLAGS_REQUIRED UINT32_C(0x2)
126 #define TLV_FLAGS_REQUIRED_NO (UINT32_C(0x0) << 1)
128 #define TLV_FLAGS_REQUIRED_YES (UINT32_C(0x1) << 1)
129 #define TLV_FLAGS_REQUIRED_LAST TLV_FLAGS_REQUIRED_YES
131 * This field defines the TLV type value which is divided into
132 * two ranges to differentiate between global and local TLV types.
133 * Global TLV types must be unique across all defined TLV types.
134 * Local TLV types are valid only for extensions to a given
135 * HWRM message and may be repeated across different HWRM message
136 * types. There is a direct correlation of each HWRM message type
137 * to a single global TLV type value.
139 * Global TLV range: `0 - (63k-1)`
141 * Local TLV range: `63k - (64k-1)`
145 * Length of the message data encapsulated by this TLV in bytes.
146 * This length does not include the size of the TLV header itself
147 * and it must be an integer multiple of 8B.
153 /* input (size:128b/16B) */
156 * This value indicates what type of request this is. The format
157 * for the rest of the command is determined by this field.
161 * This value indicates the what completion ring the request will
162 * be optionally completed on. If the value is -1, then no
163 * CR completion will be generated. Any other value must be a
164 * valid CR ring_id value for this function.
167 /* This value indicates the command sequence number. */
170 * Target ID of this command.
172 * 0x0 - 0xFFF8 - Used for function ids
173 * 0xFFF8 - 0xFFFE - Reserved for internal processors
178 * This is the host address where the response will be written
179 * when the request is complete. This area must be 16B aligned
180 * and must be cleared to zero before the request is made.
186 /* output (size:64b/8B) */
189 * Pass/Fail or error type
191 * Note: receiver to verify the in parameters, and fail the call
192 * with an error when appropriate
195 /* This field returns the type of original request. */
197 /* This field provides original sequence number of the command. */
200 * This field is the length of the response in bytes. The
201 * last byte of the response is a valid flag that will read
202 * as '1' when the command has been completely written to
208 /* Short Command Structure */
209 /* hwrm_short_input (size:128b/16B) */
210 struct hwrm_short_input {
212 * This field indicates the type of request in the request buffer.
213 * The format for the rest of the command (request) is determined
218 * This field indicates a signature that is used to identify short
219 * form of the command listed here. This field shall be set to
223 /* Signature indicating this is a short form of HWRM command */
224 #define HWRM_SHORT_INPUT_SIGNATURE_SHORT_CMD UINT32_C(0x4321)
225 #define HWRM_SHORT_INPUT_SIGNATURE_LAST \
226 HWRM_SHORT_INPUT_SIGNATURE_SHORT_CMD
227 /* The target ID of the command */
229 /* Default target_id (0x0) to maintain compatibility with old driver */
230 #define HWRM_SHORT_INPUT_TARGET_ID_DEFAULT UINT32_C(0x0)
231 /* Reserved for user-space HWRM interface */
232 #define HWRM_SHORT_INPUT_TARGET_ID_TOOLS UINT32_C(0xfffd)
233 #define HWRM_SHORT_INPUT_TARGET_ID_LAST \
234 HWRM_SHORT_INPUT_TARGET_ID_TOOLS
235 /* This value indicates the length of the request. */
238 * This is the host address where the request was written.
239 * This area must be 16B aligned.
246 * # NOTE - definitions already in hwrm_req_type, in hwrm_types.yaml
247 * # So only structure definition is provided here.
249 /* cmd_nums (size:64b/8B) */
252 * This version of the specification defines the commands listed in
253 * the table below. The following are general implementation
254 * requirements for these commands:
256 * # All commands listed below that are marked neither
257 * reserved nor experimental shall be implemented by the HWRM.
258 * # A HWRM client compliant to this specification should not use
259 * commands outside of the list below.
260 * # A HWRM client compliant to this specification should not use
261 * command numbers marked reserved below.
262 * # A command marked experimental below may not be implemented
264 * # A command marked experimental may change in the
265 * future version of the HWRM specification.
266 * # A command not listed below may be implemented by the HWRM.
267 * The behavior of commands that are not listed below is outside
268 * the scope of this specification.
271 #define HWRM_VER_GET UINT32_C(0x0)
272 #define HWRM_FUNC_ECHO_RESPONSE UINT32_C(0xb)
273 #define HWRM_ERROR_RECOVERY_QCFG UINT32_C(0xc)
274 #define HWRM_FUNC_DRV_IF_CHANGE UINT32_C(0xd)
275 #define HWRM_FUNC_BUF_UNRGTR UINT32_C(0xe)
276 #define HWRM_FUNC_VF_CFG UINT32_C(0xf)
277 /* Reserved for future use. */
278 #define HWRM_RESERVED1 UINT32_C(0x10)
279 #define HWRM_FUNC_RESET UINT32_C(0x11)
280 #define HWRM_FUNC_GETFID UINT32_C(0x12)
281 #define HWRM_FUNC_VF_ALLOC UINT32_C(0x13)
282 #define HWRM_FUNC_VF_FREE UINT32_C(0x14)
283 #define HWRM_FUNC_QCAPS UINT32_C(0x15)
284 #define HWRM_FUNC_QCFG UINT32_C(0x16)
285 #define HWRM_FUNC_CFG UINT32_C(0x17)
286 #define HWRM_FUNC_QSTATS UINT32_C(0x18)
287 #define HWRM_FUNC_CLR_STATS UINT32_C(0x19)
288 #define HWRM_FUNC_DRV_UNRGTR UINT32_C(0x1a)
289 #define HWRM_FUNC_VF_RESC_FREE UINT32_C(0x1b)
290 #define HWRM_FUNC_VF_VNIC_IDS_QUERY UINT32_C(0x1c)
291 #define HWRM_FUNC_DRV_RGTR UINT32_C(0x1d)
292 #define HWRM_FUNC_DRV_QVER UINT32_C(0x1e)
293 #define HWRM_FUNC_BUF_RGTR UINT32_C(0x1f)
294 #define HWRM_PORT_PHY_CFG UINT32_C(0x20)
295 #define HWRM_PORT_MAC_CFG UINT32_C(0x21)
297 #define HWRM_PORT_TS_QUERY UINT32_C(0x22)
298 #define HWRM_PORT_QSTATS UINT32_C(0x23)
299 #define HWRM_PORT_LPBK_QSTATS UINT32_C(0x24)
301 #define HWRM_PORT_CLR_STATS UINT32_C(0x25)
303 #define HWRM_PORT_LPBK_CLR_STATS UINT32_C(0x26)
304 #define HWRM_PORT_PHY_QCFG UINT32_C(0x27)
305 #define HWRM_PORT_MAC_QCFG UINT32_C(0x28)
307 #define HWRM_PORT_MAC_PTP_QCFG UINT32_C(0x29)
308 #define HWRM_PORT_PHY_QCAPS UINT32_C(0x2a)
309 #define HWRM_PORT_PHY_I2C_WRITE UINT32_C(0x2b)
310 #define HWRM_PORT_PHY_I2C_READ UINT32_C(0x2c)
311 #define HWRM_PORT_LED_CFG UINT32_C(0x2d)
312 #define HWRM_PORT_LED_QCFG UINT32_C(0x2e)
313 #define HWRM_PORT_LED_QCAPS UINT32_C(0x2f)
314 #define HWRM_QUEUE_QPORTCFG UINT32_C(0x30)
315 #define HWRM_QUEUE_QCFG UINT32_C(0x31)
316 #define HWRM_QUEUE_CFG UINT32_C(0x32)
317 #define HWRM_FUNC_VLAN_CFG UINT32_C(0x33)
318 #define HWRM_FUNC_VLAN_QCFG UINT32_C(0x34)
319 #define HWRM_QUEUE_PFCENABLE_QCFG UINT32_C(0x35)
320 #define HWRM_QUEUE_PFCENABLE_CFG UINT32_C(0x36)
321 #define HWRM_QUEUE_PRI2COS_QCFG UINT32_C(0x37)
322 #define HWRM_QUEUE_PRI2COS_CFG UINT32_C(0x38)
323 #define HWRM_QUEUE_COS2BW_QCFG UINT32_C(0x39)
324 #define HWRM_QUEUE_COS2BW_CFG UINT32_C(0x3a)
325 #define HWRM_QUEUE_DSCP_QCAPS UINT32_C(0x3b)
326 #define HWRM_QUEUE_DSCP2PRI_QCFG UINT32_C(0x3c)
327 #define HWRM_QUEUE_DSCP2PRI_CFG UINT32_C(0x3d)
328 #define HWRM_VNIC_ALLOC UINT32_C(0x40)
329 #define HWRM_VNIC_FREE UINT32_C(0x41)
330 #define HWRM_VNIC_CFG UINT32_C(0x42)
331 #define HWRM_VNIC_QCFG UINT32_C(0x43)
332 #define HWRM_VNIC_TPA_CFG UINT32_C(0x44)
334 #define HWRM_VNIC_TPA_QCFG UINT32_C(0x45)
335 #define HWRM_VNIC_RSS_CFG UINT32_C(0x46)
336 #define HWRM_VNIC_RSS_QCFG UINT32_C(0x47)
337 #define HWRM_VNIC_PLCMODES_CFG UINT32_C(0x48)
338 #define HWRM_VNIC_PLCMODES_QCFG UINT32_C(0x49)
339 #define HWRM_VNIC_QCAPS UINT32_C(0x4a)
340 /* Updates specific fields in RX VNIC structure */
341 #define HWRM_VNIC_UPDATE UINT32_C(0x4b)
342 #define HWRM_RING_ALLOC UINT32_C(0x50)
343 #define HWRM_RING_FREE UINT32_C(0x51)
344 #define HWRM_RING_CMPL_RING_QAGGINT_PARAMS UINT32_C(0x52)
345 #define HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS UINT32_C(0x53)
346 #define HWRM_RING_AGGINT_QCAPS UINT32_C(0x54)
347 #define HWRM_RING_SCHQ_ALLOC UINT32_C(0x55)
348 #define HWRM_RING_SCHQ_CFG UINT32_C(0x56)
349 #define HWRM_RING_SCHQ_FREE UINT32_C(0x57)
350 #define HWRM_RING_RESET UINT32_C(0x5e)
351 #define HWRM_RING_GRP_ALLOC UINT32_C(0x60)
352 #define HWRM_RING_GRP_FREE UINT32_C(0x61)
353 #define HWRM_RING_CFG UINT32_C(0x62)
354 #define HWRM_RING_QCFG UINT32_C(0x63)
355 /* Reserved for future use. */
356 #define HWRM_RESERVED5 UINT32_C(0x64)
357 /* Reserved for future use. */
358 #define HWRM_RESERVED6 UINT32_C(0x65)
359 #define HWRM_VNIC_RSS_COS_LB_CTX_ALLOC UINT32_C(0x70)
360 #define HWRM_VNIC_RSS_COS_LB_CTX_FREE UINT32_C(0x71)
361 #define HWRM_QUEUE_MPLS_QCAPS UINT32_C(0x80)
362 #define HWRM_QUEUE_MPLSTC2PRI_QCFG UINT32_C(0x81)
363 #define HWRM_QUEUE_MPLSTC2PRI_CFG UINT32_C(0x82)
364 #define HWRM_QUEUE_VLANPRI_QCAPS UINT32_C(0x83)
365 #define HWRM_QUEUE_VLANPRI2PRI_QCFG UINT32_C(0x84)
366 #define HWRM_QUEUE_VLANPRI2PRI_CFG UINT32_C(0x85)
367 #define HWRM_CFA_L2_FILTER_ALLOC UINT32_C(0x90)
368 #define HWRM_CFA_L2_FILTER_FREE UINT32_C(0x91)
369 #define HWRM_CFA_L2_FILTER_CFG UINT32_C(0x92)
370 #define HWRM_CFA_L2_SET_RX_MASK UINT32_C(0x93)
371 #define HWRM_CFA_VLAN_ANTISPOOF_CFG UINT32_C(0x94)
372 #define HWRM_CFA_TUNNEL_FILTER_ALLOC UINT32_C(0x95)
373 #define HWRM_CFA_TUNNEL_FILTER_FREE UINT32_C(0x96)
375 #define HWRM_CFA_ENCAP_RECORD_ALLOC UINT32_C(0x97)
377 #define HWRM_CFA_ENCAP_RECORD_FREE UINT32_C(0x98)
378 #define HWRM_CFA_NTUPLE_FILTER_ALLOC UINT32_C(0x99)
379 #define HWRM_CFA_NTUPLE_FILTER_FREE UINT32_C(0x9a)
380 #define HWRM_CFA_NTUPLE_FILTER_CFG UINT32_C(0x9b)
382 #define HWRM_CFA_EM_FLOW_ALLOC UINT32_C(0x9c)
384 #define HWRM_CFA_EM_FLOW_FREE UINT32_C(0x9d)
386 #define HWRM_CFA_EM_FLOW_CFG UINT32_C(0x9e)
387 #define HWRM_TUNNEL_DST_PORT_QUERY UINT32_C(0xa0)
388 #define HWRM_TUNNEL_DST_PORT_ALLOC UINT32_C(0xa1)
389 #define HWRM_TUNNEL_DST_PORT_FREE UINT32_C(0xa2)
390 #define HWRM_STAT_CTX_ENG_QUERY UINT32_C(0xaf)
391 #define HWRM_STAT_CTX_ALLOC UINT32_C(0xb0)
392 #define HWRM_STAT_CTX_FREE UINT32_C(0xb1)
393 #define HWRM_STAT_CTX_QUERY UINT32_C(0xb2)
394 #define HWRM_STAT_CTX_CLR_STATS UINT32_C(0xb3)
395 #define HWRM_PORT_QSTATS_EXT UINT32_C(0xb4)
396 #define HWRM_PORT_PHY_MDIO_WRITE UINT32_C(0xb5)
397 #define HWRM_PORT_PHY_MDIO_READ UINT32_C(0xb6)
398 #define HWRM_PORT_PHY_MDIO_BUS_ACQUIRE UINT32_C(0xb7)
399 #define HWRM_PORT_PHY_MDIO_BUS_RELEASE UINT32_C(0xb8)
400 #define HWRM_PORT_QSTATS_EXT_PFC_WD UINT32_C(0xb9)
402 #define HWRM_RESERVED7 UINT32_C(0xba)
403 #define HWRM_PORT_TX_FIR_CFG UINT32_C(0xbb)
404 #define HWRM_PORT_TX_FIR_QCFG UINT32_C(0xbc)
405 #define HWRM_PORT_ECN_QSTATS UINT32_C(0xbd)
406 #define HWRM_FW_LIVEPATCH_QUERY UINT32_C(0xbe)
407 #define HWRM_FW_LIVEPATCH UINT32_C(0xbf)
408 #define HWRM_FW_RESET UINT32_C(0xc0)
409 #define HWRM_FW_QSTATUS UINT32_C(0xc1)
410 #define HWRM_FW_HEALTH_CHECK UINT32_C(0xc2)
411 #define HWRM_FW_SYNC UINT32_C(0xc3)
412 #define HWRM_FW_STATE_QCAPS UINT32_C(0xc4)
413 #define HWRM_FW_STATE_QUIESCE UINT32_C(0xc5)
414 #define HWRM_FW_STATE_BACKUP UINT32_C(0xc6)
415 #define HWRM_FW_STATE_RESTORE UINT32_C(0xc7)
417 #define HWRM_FW_SET_TIME UINT32_C(0xc8)
419 #define HWRM_FW_GET_TIME UINT32_C(0xc9)
421 #define HWRM_FW_SET_STRUCTURED_DATA UINT32_C(0xca)
423 #define HWRM_FW_GET_STRUCTURED_DATA UINT32_C(0xcb)
425 #define HWRM_FW_IPC_MAILBOX UINT32_C(0xcc)
426 #define HWRM_FW_ECN_CFG UINT32_C(0xcd)
427 #define HWRM_FW_ECN_QCFG UINT32_C(0xce)
428 #define HWRM_FW_SECURE_CFG UINT32_C(0xcf)
429 #define HWRM_EXEC_FWD_RESP UINT32_C(0xd0)
430 #define HWRM_REJECT_FWD_RESP UINT32_C(0xd1)
431 #define HWRM_FWD_RESP UINT32_C(0xd2)
432 #define HWRM_FWD_ASYNC_EVENT_CMPL UINT32_C(0xd3)
433 #define HWRM_OEM_CMD UINT32_C(0xd4)
434 /* Tells the fw to run PRBS test on a given port and lane. */
435 #define HWRM_PORT_PRBS_TEST UINT32_C(0xd5)
436 #define HWRM_PORT_SFP_SIDEBAND_CFG UINT32_C(0xd6)
437 #define HWRM_PORT_SFP_SIDEBAND_QCFG UINT32_C(0xd7)
438 #define HWRM_FW_STATE_UNQUIESCE UINT32_C(0xd8)
439 /* Tells the fw to collect dsc dump on a given port and lane. */
440 #define HWRM_PORT_DSC_DUMP UINT32_C(0xd9)
441 #define HWRM_TEMP_MONITOR_QUERY UINT32_C(0xe0)
442 #define HWRM_REG_POWER_QUERY UINT32_C(0xe1)
443 #define HWRM_CORE_FREQUENCY_QUERY UINT32_C(0xe2)
444 #define HWRM_REG_POWER_HISTOGRAM UINT32_C(0xe3)
445 #define HWRM_WOL_FILTER_ALLOC UINT32_C(0xf0)
446 #define HWRM_WOL_FILTER_FREE UINT32_C(0xf1)
447 #define HWRM_WOL_FILTER_QCFG UINT32_C(0xf2)
448 #define HWRM_WOL_REASON_QCFG UINT32_C(0xf3)
450 #define HWRM_CFA_METER_QCAPS UINT32_C(0xf4)
452 #define HWRM_CFA_METER_PROFILE_ALLOC UINT32_C(0xf5)
454 #define HWRM_CFA_METER_PROFILE_FREE UINT32_C(0xf6)
456 #define HWRM_CFA_METER_PROFILE_CFG UINT32_C(0xf7)
458 #define HWRM_CFA_METER_INSTANCE_ALLOC UINT32_C(0xf8)
460 #define HWRM_CFA_METER_INSTANCE_FREE UINT32_C(0xf9)
462 #define HWRM_CFA_METER_INSTANCE_CFG UINT32_C(0xfa)
464 #define HWRM_CFA_VFR_ALLOC UINT32_C(0xfd)
466 #define HWRM_CFA_VFR_FREE UINT32_C(0xfe)
468 #define HWRM_CFA_VF_PAIR_ALLOC UINT32_C(0x100)
470 #define HWRM_CFA_VF_PAIR_FREE UINT32_C(0x101)
472 #define HWRM_CFA_VF_PAIR_INFO UINT32_C(0x102)
474 #define HWRM_CFA_FLOW_ALLOC UINT32_C(0x103)
476 #define HWRM_CFA_FLOW_FREE UINT32_C(0x104)
478 #define HWRM_CFA_FLOW_FLUSH UINT32_C(0x105)
480 #define HWRM_CFA_FLOW_STATS UINT32_C(0x106)
482 #define HWRM_CFA_FLOW_INFO UINT32_C(0x107)
484 #define HWRM_CFA_DECAP_FILTER_ALLOC UINT32_C(0x108)
486 #define HWRM_CFA_DECAP_FILTER_FREE UINT32_C(0x109)
487 #define HWRM_CFA_VLAN_ANTISPOOF_QCFG UINT32_C(0x10a)
488 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_ALLOC UINT32_C(0x10b)
489 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_FREE UINT32_C(0x10c)
491 #define HWRM_CFA_PAIR_ALLOC UINT32_C(0x10d)
493 #define HWRM_CFA_PAIR_FREE UINT32_C(0x10e)
495 #define HWRM_CFA_PAIR_INFO UINT32_C(0x10f)
497 #define HWRM_FW_IPC_MSG UINT32_C(0x110)
498 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_INFO UINT32_C(0x111)
499 #define HWRM_CFA_REDIRECT_QUERY_TUNNEL_TYPE UINT32_C(0x112)
501 #define HWRM_CFA_FLOW_AGING_TIMER_RESET UINT32_C(0x113)
503 #define HWRM_CFA_FLOW_AGING_CFG UINT32_C(0x114)
505 #define HWRM_CFA_FLOW_AGING_QCFG UINT32_C(0x115)
507 #define HWRM_CFA_FLOW_AGING_QCAPS UINT32_C(0x116)
509 #define HWRM_CFA_CTX_MEM_RGTR UINT32_C(0x117)
511 #define HWRM_CFA_CTX_MEM_UNRGTR UINT32_C(0x118)
513 #define HWRM_CFA_CTX_MEM_QCTX UINT32_C(0x119)
515 #define HWRM_CFA_CTX_MEM_QCAPS UINT32_C(0x11a)
517 #define HWRM_CFA_COUNTER_QCAPS UINT32_C(0x11b)
519 #define HWRM_CFA_COUNTER_CFG UINT32_C(0x11c)
521 #define HWRM_CFA_COUNTER_QCFG UINT32_C(0x11d)
523 #define HWRM_CFA_COUNTER_QSTATS UINT32_C(0x11e)
525 #define HWRM_CFA_TCP_FLAG_PROCESS_QCFG UINT32_C(0x11f)
527 #define HWRM_CFA_EEM_QCAPS UINT32_C(0x120)
529 #define HWRM_CFA_EEM_CFG UINT32_C(0x121)
531 #define HWRM_CFA_EEM_QCFG UINT32_C(0x122)
533 #define HWRM_CFA_EEM_OP UINT32_C(0x123)
535 #define HWRM_CFA_ADV_FLOW_MGNT_QCAPS UINT32_C(0x124)
536 /* Experimental - DEPRECATED */
537 #define HWRM_CFA_TFLIB UINT32_C(0x125)
538 /* Engine CKV - Get the current allocation status of keys provisioned in the key vault. */
539 #define HWRM_ENGINE_CKV_STATUS UINT32_C(0x12e)
540 /* Engine CKV - Add a new CKEK used to encrypt keys. */
541 #define HWRM_ENGINE_CKV_CKEK_ADD UINT32_C(0x12f)
542 /* Engine CKV - Delete a previously added CKEK. */
543 #define HWRM_ENGINE_CKV_CKEK_DELETE UINT32_C(0x130)
544 /* Engine CKV - Add a new key to the key vault. */
545 #define HWRM_ENGINE_CKV_KEY_ADD UINT32_C(0x131)
546 /* Engine CKV - Delete a key from the key vault. */
547 #define HWRM_ENGINE_CKV_KEY_DELETE UINT32_C(0x132)
548 /* Engine CKV - Delete all keys from the key vault. */
549 #define HWRM_ENGINE_CKV_FLUSH UINT32_C(0x133)
550 /* Engine CKV - Get random data. */
551 #define HWRM_ENGINE_CKV_RNG_GET UINT32_C(0x134)
552 /* Engine CKV - Generate and encrypt a new AES key. */
553 #define HWRM_ENGINE_CKV_KEY_GEN UINT32_C(0x135)
554 /* Engine CKV - Configure a label index with a label value. */
555 #define HWRM_ENGINE_CKV_KEY_LABEL_CFG UINT32_C(0x136)
556 /* Engine CKV - Query a label */
557 #define HWRM_ENGINE_CKV_KEY_LABEL_QCFG UINT32_C(0x137)
558 /* Engine - Query the available queue groups configuration. */
559 #define HWRM_ENGINE_QG_CONFIG_QUERY UINT32_C(0x13c)
560 /* Engine - Query the queue groups assigned to a function. */
561 #define HWRM_ENGINE_QG_QUERY UINT32_C(0x13d)
562 /* Engine - Query the available queue group meter profile configuration. */
563 #define HWRM_ENGINE_QG_METER_PROFILE_CONFIG_QUERY UINT32_C(0x13e)
564 /* Engine - Query the configuration of a queue group meter profile. */
565 #define HWRM_ENGINE_QG_METER_PROFILE_QUERY UINT32_C(0x13f)
566 /* Engine - Allocate a queue group meter profile. */
567 #define HWRM_ENGINE_QG_METER_PROFILE_ALLOC UINT32_C(0x140)
568 /* Engine - Free a queue group meter profile. */
569 #define HWRM_ENGINE_QG_METER_PROFILE_FREE UINT32_C(0x141)
570 /* Engine - Query the meters assigned to a queue group. */
571 #define HWRM_ENGINE_QG_METER_QUERY UINT32_C(0x142)
572 /* Engine - Bind a queue group meter profile to a queue group. */
573 #define HWRM_ENGINE_QG_METER_BIND UINT32_C(0x143)
574 /* Engine - Unbind a queue group meter profile from a queue group. */
575 #define HWRM_ENGINE_QG_METER_UNBIND UINT32_C(0x144)
576 /* Engine - Bind a queue group to a function. */
577 #define HWRM_ENGINE_QG_FUNC_BIND UINT32_C(0x145)
578 /* Engine - Query the scheduling group configuration. */
579 #define HWRM_ENGINE_SG_CONFIG_QUERY UINT32_C(0x146)
580 /* Engine - Query the queue groups assigned to a scheduling group. */
581 #define HWRM_ENGINE_SG_QUERY UINT32_C(0x147)
582 /* Engine - Query the configuration of a scheduling group's meter profiles. */
583 #define HWRM_ENGINE_SG_METER_QUERY UINT32_C(0x148)
584 /* Engine - Configure a scheduling group's meter profiles. */
585 #define HWRM_ENGINE_SG_METER_CONFIG UINT32_C(0x149)
586 /* Engine - Bind a queue group to a scheduling group. */
587 #define HWRM_ENGINE_SG_QG_BIND UINT32_C(0x14a)
588 /* Engine - Unbind a queue group from its scheduling group. */
589 #define HWRM_ENGINE_QG_SG_UNBIND UINT32_C(0x14b)
590 /* Engine - Query the Engine configuration. */
591 #define HWRM_ENGINE_CONFIG_QUERY UINT32_C(0x154)
592 /* Engine - Configure the statistics accumulator for an Engine. */
593 #define HWRM_ENGINE_STATS_CONFIG UINT32_C(0x155)
594 /* Engine - Clear the statistics accumulator for an Engine. */
595 #define HWRM_ENGINE_STATS_CLEAR UINT32_C(0x156)
596 /* Engine - Query the statistics accumulator for an Engine. */
597 #define HWRM_ENGINE_STATS_QUERY UINT32_C(0x157)
598 /* Engine - Query statistics counters for continuous errors from all CDDIP Engines. */
599 #define HWRM_ENGINE_STATS_QUERY_CONTINUOUS_ERROR UINT32_C(0x158)
600 /* Engine - Allocate an Engine RQ. */
601 #define HWRM_ENGINE_RQ_ALLOC UINT32_C(0x15e)
602 /* Engine - Free an Engine RQ. */
603 #define HWRM_ENGINE_RQ_FREE UINT32_C(0x15f)
604 /* Engine - Allocate an Engine CQ. */
605 #define HWRM_ENGINE_CQ_ALLOC UINT32_C(0x160)
606 /* Engine - Free an Engine CQ. */
607 #define HWRM_ENGINE_CQ_FREE UINT32_C(0x161)
608 /* Engine - Allocate an NQ. */
609 #define HWRM_ENGINE_NQ_ALLOC UINT32_C(0x162)
610 /* Engine - Free an NQ. */
611 #define HWRM_ENGINE_NQ_FREE UINT32_C(0x163)
612 /* Engine - Set the on-die RQE credit update location. */
613 #define HWRM_ENGINE_ON_DIE_RQE_CREDITS UINT32_C(0x164)
614 /* Engine - Query the engine function configuration. */
615 #define HWRM_ENGINE_FUNC_QCFG UINT32_C(0x165)
617 #define HWRM_FUNC_RESOURCE_QCAPS UINT32_C(0x190)
619 #define HWRM_FUNC_VF_RESOURCE_CFG UINT32_C(0x191)
621 #define HWRM_FUNC_BACKING_STORE_QCAPS UINT32_C(0x192)
623 #define HWRM_FUNC_BACKING_STORE_CFG UINT32_C(0x193)
625 #define HWRM_FUNC_BACKING_STORE_QCFG UINT32_C(0x194)
626 /* Configures the BW of any VF */
627 #define HWRM_FUNC_VF_BW_CFG UINT32_C(0x195)
628 /* Queries the BW of any VF */
629 #define HWRM_FUNC_VF_BW_QCFG UINT32_C(0x196)
630 /* Queries pf ids belong to specified host(s) */
631 #define HWRM_FUNC_HOST_PF_IDS_QUERY UINT32_C(0x197)
632 /* Queries extended stats per function */
633 #define HWRM_FUNC_QSTATS_EXT UINT32_C(0x198)
634 /* Queries extended statistics context */
635 #define HWRM_STAT_EXT_CTX_QUERY UINT32_C(0x199)
636 /* Configure SoC packet DMA settings */
637 #define HWRM_FUNC_SPD_CFG UINT32_C(0x19a)
638 /* Query SoC packet DMA settings */
639 #define HWRM_FUNC_SPD_QCFG UINT32_C(0x19b)
641 #define HWRM_SELFTEST_QLIST UINT32_C(0x200)
643 #define HWRM_SELFTEST_EXEC UINT32_C(0x201)
645 #define HWRM_SELFTEST_IRQ UINT32_C(0x202)
647 #define HWRM_SELFTEST_RETRIEVE_SERDES_DATA UINT32_C(0x203)
649 #define HWRM_PCIE_QSTATS UINT32_C(0x204)
651 #define HWRM_MFG_FRU_WRITE_CONTROL UINT32_C(0x205)
652 /* Returns the current value of a free running counter from the device. */
653 #define HWRM_MFG_TIMERS_QUERY UINT32_C(0x206)
655 #define HWRM_MFG_OTP_CFG UINT32_C(0x207)
657 #define HWRM_MFG_OTP_QCFG UINT32_C(0x208)
659 * Tells the fw to run the DMA read from the host and DMA write
662 #define HWRM_MFG_HDMA_TEST UINT32_C(0x209)
663 /* Tells the fw to program the fru memory */
664 #define HWRM_MFG_FRU_EEPROM_WRITE UINT32_C(0x20a)
665 /* Tells the fw to read the fru memory */
666 #define HWRM_MFG_FRU_EEPROM_READ UINT32_C(0x20b)
667 /* Used to provision SoC software images */
668 #define HWRM_MFG_SOC_IMAGE UINT32_C(0x20c)
669 /* Retrieves the SoC status and image provisioning information */
670 #define HWRM_MFG_SOC_QSTATUS UINT32_C(0x20d)
671 /* Tells the fw to program the seeprom memory */
672 #define HWRM_MFG_PARAM_SEEPROM_SYNC UINT32_C(0x20e)
673 /* Tells the fw to read the seeprom memory */
674 #define HWRM_MFG_PARAM_SEEPROM_READ UINT32_C(0x20f)
675 /* Tells the fw to get the health of seeprom data */
676 #define HWRM_MFG_PARAM_SEEPROM_HEALTH UINT32_C(0x210)
678 #define HWRM_TF UINT32_C(0x2bc)
680 #define HWRM_TF_VERSION_GET UINT32_C(0x2bd)
682 #define HWRM_TF_SESSION_OPEN UINT32_C(0x2c6)
684 #define HWRM_TF_SESSION_ATTACH UINT32_C(0x2c7)
686 #define HWRM_TF_SESSION_REGISTER UINT32_C(0x2c8)
688 #define HWRM_TF_SESSION_UNREGISTER UINT32_C(0x2c9)
690 #define HWRM_TF_SESSION_CLOSE UINT32_C(0x2ca)
692 #define HWRM_TF_SESSION_QCFG UINT32_C(0x2cb)
694 #define HWRM_TF_SESSION_RESC_QCAPS UINT32_C(0x2cc)
696 #define HWRM_TF_SESSION_RESC_ALLOC UINT32_C(0x2cd)
698 #define HWRM_TF_SESSION_RESC_FREE UINT32_C(0x2ce)
700 #define HWRM_TF_SESSION_RESC_FLUSH UINT32_C(0x2cf)
702 #define HWRM_TF_TBL_TYPE_GET UINT32_C(0x2da)
704 #define HWRM_TF_TBL_TYPE_SET UINT32_C(0x2db)
706 #define HWRM_TF_TBL_TYPE_BULK_GET UINT32_C(0x2dc)
708 #define HWRM_TF_CTXT_MEM_ALLOC UINT32_C(0x2e2)
710 #define HWRM_TF_CTXT_MEM_FREE UINT32_C(0x2e3)
712 #define HWRM_TF_CTXT_MEM_RGTR UINT32_C(0x2e4)
714 #define HWRM_TF_CTXT_MEM_UNRGTR UINT32_C(0x2e5)
716 #define HWRM_TF_EXT_EM_QCAPS UINT32_C(0x2e6)
718 #define HWRM_TF_EXT_EM_OP UINT32_C(0x2e7)
720 #define HWRM_TF_EXT_EM_CFG UINT32_C(0x2e8)
722 #define HWRM_TF_EXT_EM_QCFG UINT32_C(0x2e9)
724 #define HWRM_TF_EM_INSERT UINT32_C(0x2ea)
726 #define HWRM_TF_EM_DELETE UINT32_C(0x2eb)
728 #define HWRM_TF_EM_HASH_INSERT UINT32_C(0x2ec)
730 #define HWRM_TF_TCAM_SET UINT32_C(0x2f8)
732 #define HWRM_TF_TCAM_GET UINT32_C(0x2f9)
734 #define HWRM_TF_TCAM_MOVE UINT32_C(0x2fa)
736 #define HWRM_TF_TCAM_FREE UINT32_C(0x2fb)
738 #define HWRM_TF_GLOBAL_CFG_SET UINT32_C(0x2fc)
740 #define HWRM_TF_GLOBAL_CFG_GET UINT32_C(0x2fd)
742 #define HWRM_TF_IF_TBL_SET UINT32_C(0x2fe)
744 #define HWRM_TF_IF_TBL_GET UINT32_C(0x2ff)
746 #define HWRM_SV UINT32_C(0x400)
748 #define HWRM_DBG_READ_DIRECT UINT32_C(0xff10)
750 #define HWRM_DBG_READ_INDIRECT UINT32_C(0xff11)
752 #define HWRM_DBG_WRITE_DIRECT UINT32_C(0xff12)
754 #define HWRM_DBG_WRITE_INDIRECT UINT32_C(0xff13)
755 #define HWRM_DBG_DUMP UINT32_C(0xff14)
757 #define HWRM_DBG_ERASE_NVM UINT32_C(0xff15)
759 #define HWRM_DBG_CFG UINT32_C(0xff16)
761 #define HWRM_DBG_COREDUMP_LIST UINT32_C(0xff17)
763 #define HWRM_DBG_COREDUMP_INITIATE UINT32_C(0xff18)
765 #define HWRM_DBG_COREDUMP_RETRIEVE UINT32_C(0xff19)
767 #define HWRM_DBG_FW_CLI UINT32_C(0xff1a)
769 #define HWRM_DBG_I2C_CMD UINT32_C(0xff1b)
771 #define HWRM_DBG_RING_INFO_GET UINT32_C(0xff1c)
773 #define HWRM_DBG_CRASHDUMP_HEADER UINT32_C(0xff1d)
775 #define HWRM_DBG_CRASHDUMP_ERASE UINT32_C(0xff1e)
776 /* Send driver debug information to firmware */
777 #define HWRM_DBG_DRV_TRACE UINT32_C(0xff1f)
778 /* Query debug capabilities of firmware */
779 #define HWRM_DBG_QCAPS UINT32_C(0xff20)
780 /* Retrieve debug settings of firmware */
781 #define HWRM_DBG_QCFG UINT32_C(0xff21)
782 /* Set destination parameters for crashdump medium */
783 #define HWRM_DBG_CRASHDUMP_MEDIUM_CFG UINT32_C(0xff22)
784 #define HWRM_NVM_REQ_ARBITRATION UINT32_C(0xffed)
786 #define HWRM_NVM_FACTORY_DEFAULTS UINT32_C(0xffee)
787 #define HWRM_NVM_VALIDATE_OPTION UINT32_C(0xffef)
788 #define HWRM_NVM_FLUSH UINT32_C(0xfff0)
789 #define HWRM_NVM_GET_VARIABLE UINT32_C(0xfff1)
790 #define HWRM_NVM_SET_VARIABLE UINT32_C(0xfff2)
791 #define HWRM_NVM_INSTALL_UPDATE UINT32_C(0xfff3)
792 #define HWRM_NVM_MODIFY UINT32_C(0xfff4)
793 #define HWRM_NVM_VERIFY_UPDATE UINT32_C(0xfff5)
794 #define HWRM_NVM_GET_DEV_INFO UINT32_C(0xfff6)
795 #define HWRM_NVM_ERASE_DIR_ENTRY UINT32_C(0xfff7)
796 #define HWRM_NVM_MOD_DIR_ENTRY UINT32_C(0xfff8)
797 #define HWRM_NVM_FIND_DIR_ENTRY UINT32_C(0xfff9)
798 #define HWRM_NVM_GET_DIR_ENTRIES UINT32_C(0xfffa)
799 #define HWRM_NVM_GET_DIR_INFO UINT32_C(0xfffb)
800 #define HWRM_NVM_RAW_DUMP UINT32_C(0xfffc)
801 #define HWRM_NVM_READ UINT32_C(0xfffd)
802 #define HWRM_NVM_WRITE UINT32_C(0xfffe)
803 #define HWRM_NVM_RAW_WRITE_BLK UINT32_C(0xffff)
804 #define HWRM_LAST HWRM_NVM_RAW_WRITE_BLK
805 uint16_t unused_0[3];
809 /* ret_codes (size:64b/8B) */
812 /* Request was successfully executed by the HWRM. */
813 #define HWRM_ERR_CODE_SUCCESS UINT32_C(0x0)
814 /* The HWRM failed to execute the request. */
815 #define HWRM_ERR_CODE_FAIL UINT32_C(0x1)
817 * The request contains invalid argument(s) or input
820 #define HWRM_ERR_CODE_INVALID_PARAMS UINT32_C(0x2)
822 * The requester is not allowed to access the requested
823 * resource. This error code shall be provided in a
824 * response to a request to query or modify an existing
825 * resource that is not accessible by the requester.
827 #define HWRM_ERR_CODE_RESOURCE_ACCESS_DENIED UINT32_C(0x3)
829 * The HWRM is unable to allocate the requested resource.
830 * This code only applies to requests for HWRM resource
833 #define HWRM_ERR_CODE_RESOURCE_ALLOC_ERROR UINT32_C(0x4)
835 * Invalid combination of flags is specified in the
838 #define HWRM_ERR_CODE_INVALID_FLAGS UINT32_C(0x5)
840 * Invalid combination of enables fields is specified in
843 #define HWRM_ERR_CODE_INVALID_ENABLES UINT32_C(0x6)
845 * Request contains a required TLV that is not supported by
846 * the installed version of firmware.
848 #define HWRM_ERR_CODE_UNSUPPORTED_TLV UINT32_C(0x7)
850 * No firmware buffer available to accept the request. Driver
851 * should retry the request.
853 #define HWRM_ERR_CODE_NO_BUFFER UINT32_C(0x8)
855 * This error code is only reported by firmware when some
856 * sub-option of a supported HWRM command is unsupported.
858 #define HWRM_ERR_CODE_UNSUPPORTED_OPTION_ERR UINT32_C(0x9)
860 * This error code is only reported by firmware when the specific
861 * request is not able to process when the HOT reset in progress.
863 #define HWRM_ERR_CODE_HOT_RESET_PROGRESS UINT32_C(0xa)
865 * This error code is only reported by firmware when the registered
866 * driver instances are not capable of hot reset.
868 #define HWRM_ERR_CODE_HOT_RESET_FAIL UINT32_C(0xb)
870 * This error code is only reported by the firmware when during
871 * flow allocation when a request for a flow counter fails because
872 * the number of flow counters are exhausted.
874 #define HWRM_ERR_CODE_NO_FLOW_COUNTER_DURING_ALLOC UINT32_C(0xc)
876 * This error code is only reported by firmware when the registered
877 * driver instances requested to offloaded a flow but was unable to because
878 * the requested key's hash collides with the installed keys.
880 #define HWRM_ERR_CODE_KEY_HASH_COLLISION UINT32_C(0xd)
882 * This error code is only reported by firmware when the registered
883 * driver instances requested to offloaded a flow but was unable to because
884 * the same key has already been installed.
886 #define HWRM_ERR_CODE_KEY_ALREADY_EXISTS UINT32_C(0xe)
888 * Generic HWRM execution error that represents an
891 #define HWRM_ERR_CODE_HWRM_ERROR UINT32_C(0xf)
893 * Firmware is unable to service the request at the present time. Caller
894 * may try again later.
896 #define HWRM_ERR_CODE_BUSY UINT32_C(0x10)
898 * This error code is reported by Firmware when an operation requested
899 * by the host is not allowed due to a secure lock violation.
901 #define HWRM_ERR_CODE_RESOURCE_LOCKED UINT32_C(0x11)
903 * This value indicates that the HWRM response is in TLV format and
904 * should be interpreted as one or more TLVs starting with the
905 * hwrm_resp_hdr TLV. This value is not an indication of any error
906 * by itself, just an indication that the response should be parsed
907 * as TLV and the actual error code will be in the hwrm_resp_hdr TLV.
909 #define HWRM_ERR_CODE_TLV_ENCAPSULATED_RESPONSE UINT32_C(0x8000)
911 #define HWRM_ERR_CODE_UNKNOWN_ERR UINT32_C(0xfffe)
912 /* Unsupported or invalid command */
913 #define HWRM_ERR_CODE_CMD_NOT_SUPPORTED UINT32_C(0xffff)
914 #define HWRM_ERR_CODE_LAST \
915 HWRM_ERR_CODE_CMD_NOT_SUPPORTED
916 uint16_t unused_0[3];
920 /* hwrm_err_output (size:128b/16B) */
921 struct hwrm_err_output {
923 * Pass/Fail or error type
925 * Note: receiver to verify the in parameters, and fail the call
926 * with an error when appropriate
929 /* This field returns the type of original request. */
931 /* This field provides original sequence number of the command. */
934 * This field is the length of the response in bytes. The
935 * last byte of the response is a valid flag that will read
936 * as '1' when the command has been completely written to
940 /* debug info for this error response. */
942 /* debug info for this error response. */
945 * In the case of an error response, command specific error
946 * code is returned in this field.
950 * This field is used in Output records to indicate that the output
951 * is completely written to RAM. This field should be read as '1'
952 * to indicate that the output has been completely written.
953 * When writing a command completion or response to an internal processor,
954 * the order of writes has to be such that this field is written last.
959 * Following is the signature for HWRM message field that indicates not
960 * applicable (All F's). Need to cast it the size of the field if needed.
962 #define HWRM_NA_SIGNATURE ((uint32_t)(-1))
963 /* hwrm_func_buf_rgtr */
964 #define HWRM_MAX_REQ_LEN 128
965 /* hwrm_cfa_flow_info */
966 #define HWRM_MAX_RESP_LEN 704
967 /* 7 bit indirection table index. */
968 #define HW_HASH_INDEX_SIZE 0x80
969 #define HW_HASH_KEY_SIZE 40
970 /* valid key for HWRM response */
971 #define HWRM_RESP_VALID_KEY 1
972 /* Reserved for BONO processor */
973 #define HWRM_TARGET_ID_BONO 0xFFF8
974 /* Reserved for KONG processor */
975 #define HWRM_TARGET_ID_KONG 0xFFF9
976 /* Reserved for APE processor */
977 #define HWRM_TARGET_ID_APE 0xFFFA
979 * This value will be used by tools for User-space HWRM Interface.
980 * When tool execute any HWRM command with this target_id, firmware
981 * will copy the response and/or data payload via register space instead
984 #define HWRM_TARGET_ID_TOOLS 0xFFFD
985 #define HWRM_VERSION_MAJOR 1
986 #define HWRM_VERSION_MINOR 10
987 #define HWRM_VERSION_UPDATE 2
988 /* non-zero means beta version */
989 #define HWRM_VERSION_RSVD 15
990 #define HWRM_VERSION_STR "1.10.2.15"
997 /* hwrm_ver_get_input (size:192b/24B) */
998 struct hwrm_ver_get_input {
999 /* The HWRM command request type. */
1002 * The completion ring to send the completion event on. This should
1003 * be the NQ ID returned from the `nq_alloc` HWRM command.
1007 * The sequence ID is used by the driver for tracking multiple
1008 * commands. This ID is treated as opaque data by the firmware and
1009 * the value is returned in the `hwrm_resp_hdr` upon completion.
1013 * The target ID of the command:
1014 * * 0x0-0xFFF8 - The function ID
1015 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
1016 * * 0xFFFD - Reserved for user-space HWRM interface
1021 * A physical address pointer pointing to a host buffer that the
1022 * command's response data will be written. This can be either a host
1023 * physical address (HPA) or a guest physical address (GPA) and must
1024 * point to a physically contiguous block of memory.
1028 * This field represents the major version of HWRM interface
1029 * specification supported by the driver HWRM implementation.
1030 * The interface major version is intended to change only when
1031 * non backward compatible changes are made to the HWRM
1032 * interface specification.
1034 uint8_t hwrm_intf_maj;
1036 * This field represents the minor version of HWRM interface
1037 * specification supported by the driver HWRM implementation.
1038 * A change in interface minor version is used to reflect
1039 * significant backward compatible modification to HWRM
1040 * interface specification.
1041 * This can be due to addition or removal of functionality.
1042 * HWRM interface specifications with the same major version
1043 * but different minor versions are compatible.
1045 uint8_t hwrm_intf_min;
1047 * This field represents the update version of HWRM interface
1048 * specification supported by the driver HWRM implementation.
1049 * The interface update version is used to reflect minor
1050 * changes or bug fixes to a released HWRM interface
1053 uint8_t hwrm_intf_upd;
1054 uint8_t unused_0[5];
1057 /* hwrm_ver_get_output (size:1408b/176B) */
1058 struct hwrm_ver_get_output {
1059 /* The specific error status for the command. */
1060 uint16_t error_code;
1061 /* The HWRM command request type. */
1063 /* The sequence ID from the original command. */
1065 /* The length of the response data in number of bytes. */
1068 * This field represents the major version of HWRM interface
1069 * specification supported by the HWRM implementation.
1070 * The interface major version is intended to change only when
1071 * non backward compatible changes are made to the HWRM
1072 * interface specification.
1073 * A HWRM implementation that is compliant with this
1074 * specification shall provide value of 1 in this field.
1076 uint8_t hwrm_intf_maj_8b;
1078 * This field represents the minor version of HWRM interface
1079 * specification supported by the HWRM implementation.
1080 * A change in interface minor version is used to reflect
1081 * significant backward compatible modification to HWRM
1082 * interface specification.
1083 * This can be due to addition or removal of functionality.
1084 * HWRM interface specifications with the same major version
1085 * but different minor versions are compatible.
1086 * A HWRM implementation that is compliant with this
1087 * specification shall provide value of 2 in this field.
1089 uint8_t hwrm_intf_min_8b;
1091 * This field represents the update version of HWRM interface
1092 * specification supported by the HWRM implementation.
1093 * The interface update version is used to reflect minor
1094 * changes or bug fixes to a released HWRM interface
1096 * A HWRM implementation that is compliant with this
1097 * specification shall provide value of 2 in this field.
1099 uint8_t hwrm_intf_upd_8b;
1100 uint8_t hwrm_intf_rsvd_8b;
1102 * This field represents the major version of HWRM firmware.
1103 * A change in firmware major version represents a major
1106 uint8_t hwrm_fw_maj_8b;
1108 * This field represents the minor version of HWRM firmware.
1109 * A change in firmware minor version represents significant
1110 * firmware functionality changes.
1112 uint8_t hwrm_fw_min_8b;
1114 * This field represents the build version of HWRM firmware.
1115 * A change in firmware build version represents bug fixes
1116 * to a released firmware.
1118 uint8_t hwrm_fw_bld_8b;
1120 * This field is a reserved field. This field can be used to
1121 * represent firmware branches or customer specific releases
1122 * tied to a specific (major,minor,update) version of the
1125 uint8_t hwrm_fw_rsvd_8b;
1127 * This field represents the major version of mgmt firmware.
1128 * A change in major version represents a major release.
1130 uint8_t mgmt_fw_maj_8b;
1132 * This field represents the minor version of mgmt firmware.
1133 * A change in minor version represents significant
1134 * functionality changes.
1136 uint8_t mgmt_fw_min_8b;
1138 * This field represents the build version of mgmt firmware.
1139 * A change in update version represents bug fixes.
1141 uint8_t mgmt_fw_bld_8b;
1143 * This field is a reserved field. This field can be used to
1144 * represent firmware branches or customer specific releases
1145 * tied to a specific (major,minor,update) version
1147 uint8_t mgmt_fw_rsvd_8b;
1149 * This field represents the major version of network
1151 * A change in major version represents a major release.
1153 uint8_t netctrl_fw_maj_8b;
1155 * This field represents the minor version of network
1157 * A change in minor version represents significant
1158 * functionality changes.
1160 uint8_t netctrl_fw_min_8b;
1162 * This field represents the build version of network
1164 * A change in update version represents bug fixes.
1166 uint8_t netctrl_fw_bld_8b;
1168 * This field is a reserved field. This field can be used to
1169 * represent firmware branches or customer specific releases
1170 * tied to a specific (major,minor,update) version
1172 uint8_t netctrl_fw_rsvd_8b;
1174 * This field is used to indicate device's capabilities and
1177 uint32_t dev_caps_cfg;
1179 * If set to 1, then secure firmware update behavior
1181 * If set to 0, then secure firmware update behavior is
1184 #define HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_SECURE_FW_UPD_SUPPORTED \
1187 * If set to 1, then firmware based DCBX agent is supported.
1188 * If set to 0, then firmware based DCBX agent capability
1189 * is not supported on this device.
1191 #define HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_FW_DCBX_AGENT_SUPPORTED \
1194 * If set to 1, then HWRM short command format is supported.
1195 * If set to 0, then HWRM short command format is not supported.
1197 #define HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_SHORT_CMD_SUPPORTED \
1200 * If set to 1, then HWRM short command format is required.
1201 * If set to 0, then HWRM short command format is not required.
1203 #define HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_SHORT_CMD_REQUIRED \
1206 * If set to 1, then the KONG host mailbox channel is supported.
1207 * If set to 0, then the KONG host mailbox channel is not supported.
1208 * By default, this flag should be 0 for older version of core firmware.
1210 #define HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_KONG_MB_CHNL_SUPPORTED \
1213 * If set to 1, then the 64bit flow handle is supported in addition to the
1214 * legacy 16bit flow handle. If set to 0, then the 64bit flow handle is not
1215 * supported. By default, this flag should be 0 for older version of core firmware.
1217 #define HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_FLOW_HANDLE_64BIT_SUPPORTED \
1220 * If set to 1, then filter type can be provided in filter_alloc or filter_cfg
1221 * filter types like L2 for l2 traffic and ROCE for roce & l2 traffic.
1222 * If set to 0, then filter types not supported.
1223 * By default, this flag should be 0 for older version of core firmware.
1225 #define HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_L2_FILTER_TYPES_ROCE_OR_L2_SUPPORTED \
1228 * If set to 1, firmware is capable to support virtio vSwitch offload model.
1229 * If set to 0, firmware can't supported virtio vSwitch offload model.
1230 * By default, this flag should be 0 for older version of core firmware.
1232 #define HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_VIRTIO_VSWITCH_OFFLOAD_SUPPORTED \
1235 * If set to 1, firmware is capable to support trusted VF.
1236 * If set to 0, firmware is not capable to support trusted VF.
1237 * By default, this flag should be 0 for older version of core firmware.
1239 #define HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_TRUSTED_VF_SUPPORTED \
1242 * If set to 1, firmware is capable to support flow aging.
1243 * If set to 0, firmware is not capable to support flow aging.
1244 * By default, this flag should be 0 for older version of core firmware.
1246 #define HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_FLOW_AGING_SUPPORTED \
1249 * If set to 1, firmware is capable to support advanced flow counters like,
1250 * Meter drop counters and EEM counters.
1251 * If set to 0, firmware is not capable to support advanced flow counters.
1252 * By default, this flag should be 0 for older version of core firmware.
1254 #define HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_ADV_FLOW_COUNTERS_SUPPORTED \
1257 * If set to 1, the firmware is able to support the use of the CFA
1258 * Extended Exact Match(EEM) feature.
1259 * If set to 0, firmware is not capable to support the use of the
1261 * By default, this flag should be 0 for older version of core firmware.
1263 #define HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_CFA_EEM_SUPPORTED \
1266 * If set to 1, the firmware is able to support advance CFA flow management
1267 * features reported in the HWRM_CFA_FLOW_MGNT_QCAPS.
1268 * If set to 0, then the firmware doesn’t support the advance CFA flow management
1270 * By default, this flag should be 0 for older version of core firmware.
1272 #define HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_CFA_ADV_FLOW_MGNT_SUPPORTED \
1275 * Deprecated and replaced with cfa_truflow_supported.
1276 * If set to 1, the firmware is able to support TFLIB features.
1277 * If set to 0, then the firmware doesn’t support TFLIB features.
1278 * By default, this flag should be 0 for older version of core firmware.
1280 #define HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_CFA_TFLIB_SUPPORTED \
1283 * If set to 1, the firmware is able to support TruFlow features.
1284 * If set to 0, then the firmware doesn’t support TruFlow features.
1285 * By default, this flag should be 0 for older version of
1288 #define HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_CFA_TRUFLOW_SUPPORTED \
1291 * This field represents the major version of RoCE firmware.
1292 * A change in major version represents a major release.
1294 uint8_t roce_fw_maj_8b;
1296 * This field represents the minor version of RoCE firmware.
1297 * A change in minor version represents significant
1298 * functionality changes.
1300 uint8_t roce_fw_min_8b;
1302 * This field represents the build version of RoCE firmware.
1303 * A change in update version represents bug fixes.
1305 uint8_t roce_fw_bld_8b;
1307 * This field is a reserved field. This field can be used to
1308 * represent firmware branches or customer specific releases
1309 * tied to a specific (major,minor,update) version
1311 uint8_t roce_fw_rsvd_8b;
1313 * This field represents the name of HWRM FW (ASCII chars
1314 * with NULL at the end).
1316 char hwrm_fw_name[16];
1318 * This field represents the name of mgmt FW (ASCII chars
1319 * with NULL at the end).
1321 char mgmt_fw_name[16];
1323 * This field represents the name of network control
1324 * firmware (ASCII chars with NULL at the end).
1326 char netctrl_fw_name[16];
1327 /* This field represents the active board package name. */
1328 char active_pkg_name[16];
1330 * This field represents the name of RoCE FW (ASCII chars
1331 * with NULL at the end).
1333 char roce_fw_name[16];
1334 /* This field returns the chip number. */
1336 /* This field returns the revision of chip. */
1338 /* This field returns the chip metal number. */
1340 /* This field returns the bond id of the chip. */
1341 uint8_t chip_bond_id;
1342 /* This value indicates the type of platform used for chip implementation. */
1343 uint8_t chip_platform_type;
1345 #define HWRM_VER_GET_OUTPUT_CHIP_PLATFORM_TYPE_ASIC UINT32_C(0x0)
1346 /* FPGA platform of the chip. */
1347 #define HWRM_VER_GET_OUTPUT_CHIP_PLATFORM_TYPE_FPGA UINT32_C(0x1)
1348 /* Palladium platform of the chip. */
1349 #define HWRM_VER_GET_OUTPUT_CHIP_PLATFORM_TYPE_PALLADIUM UINT32_C(0x2)
1350 #define HWRM_VER_GET_OUTPUT_CHIP_PLATFORM_TYPE_LAST \
1351 HWRM_VER_GET_OUTPUT_CHIP_PLATFORM_TYPE_PALLADIUM
1353 * This field returns the maximum value of request window that
1354 * is supported by the HWRM. The request window is mapped
1355 * into device address space using MMIO.
1357 uint16_t max_req_win_len;
1359 * This field returns the maximum value of response buffer in
1362 uint16_t max_resp_len;
1364 * This field returns the default request timeout value in
1367 uint16_t def_req_timeout;
1369 * This field will indicate if any subsystems is not fully
1374 * If set to 1, it will indicate to host drivers that firmware is
1375 * not ready to start full blown HWRM commands. Host drivers should
1376 * re-try HWRM_VER_GET with some timeout period. The timeout period
1377 * can be selected up to 5 seconds. Host drivers should also check
1378 * for dev_not_rdy_backing_store to identify if flag is set due to
1379 * backing store not been available.
1380 * For Example, PCIe hot-plug:
1381 * Hot plug timing is system dependent. It generally takes up to
1382 * 600 miliseconds for firmware to clear DEV_NOT_RDY flag.
1383 * If set to 0, device is ready to accept all HWRM commands.
1385 #define HWRM_VER_GET_OUTPUT_FLAGS_DEV_NOT_RDY \
1388 * If set to 1, external version present.
1389 * If set to 0, external version not present.
1391 #define HWRM_VER_GET_OUTPUT_FLAGS_EXT_VER_AVAIL \
1394 * Firmware sets this flag along with dev_not_rdy flag to indicate
1395 * host drivers that it has not completed resource initialization
1396 * required for data path operations. Host drivers should not send
1397 * any HWRM command that requires data path resources. Firmware will
1398 * fail those commands with HWRM_ERR_CODE_BUSY. Host drivers can retry
1399 * those commands once both the flags are cleared.
1400 * If this flag and dev_not_rdy flag are set to 0, device is ready
1401 * to accept all HWRM commands.
1403 #define HWRM_VER_GET_OUTPUT_FLAGS_DEV_NOT_RDY_BACKING_STORE \
1405 uint8_t unused_0[2];
1407 * For backward compatibility this field must be set to 1.
1408 * Older drivers might look for this field to be 1 before
1409 * processing the message.
1413 * This field represents the major version of HWRM interface
1414 * specification supported by the HWRM implementation.
1415 * The interface major version is intended to change only when
1416 * non backward compatible changes are made to the HWRM
1417 * interface specification. A HWRM implementation that is
1418 * compliant with this specification shall provide value of 1
1421 uint16_t hwrm_intf_major;
1423 * This field represents the minor version of HWRM interface
1424 * specification supported by the HWRM implementation.
1425 * A change in interface minor version is used to reflect
1426 * significant backward compatible modification to HWRM
1427 * interface specification. This can be due to addition or
1428 * removal of functionality. HWRM interface specifications
1429 * with the same major version but different minor versions are
1430 * compatible. A HWRM implementation that is compliant with
1431 * this specification shall provide value of 2 in this field.
1433 uint16_t hwrm_intf_minor;
1435 * This field represents the update version of HWRM interface
1436 * specification supported by the HWRM implementation. The
1437 * interface update version is used to reflect minor changes or
1438 * bug fixes to a released HWRM interface specification.
1439 * A HWRM implementation that is compliant with this
1440 * specification shall provide value of 2 in this field.
1442 uint16_t hwrm_intf_build;
1444 * This field represents the patch version of HWRM interface
1445 * specification supported by the HWRM implementation.
1447 uint16_t hwrm_intf_patch;
1449 * This field represents the major version of HWRM firmware.
1450 * A change in firmware major version represents a major
1453 uint16_t hwrm_fw_major;
1455 * This field represents the minor version of HWRM firmware.
1456 * A change in firmware minor version represents significant
1457 * firmware functionality changes.
1459 uint16_t hwrm_fw_minor;
1461 * This field represents the build version of HWRM firmware.
1462 * A change in firmware build version represents bug fixes to
1463 * a released firmware.
1465 uint16_t hwrm_fw_build;
1467 * This field is a reserved field.
1468 * This field can be used to represent firmware branches or customer
1469 * specific releases tied to a specific (major,minor,update) version
1470 * of the HWRM firmware.
1472 uint16_t hwrm_fw_patch;
1474 * This field represents the major version of mgmt firmware.
1475 * A change in major version represents a major release.
1477 uint16_t mgmt_fw_major;
1479 * This field represents the minor version of HWRM firmware.
1480 * A change in firmware minor version represents significant
1481 * firmware functionality changes.
1483 uint16_t mgmt_fw_minor;
1485 * This field represents the build version of mgmt firmware.
1486 * A change in update version represents bug fixes.
1488 uint16_t mgmt_fw_build;
1490 * This field is a reserved field. This field can be used to
1491 * represent firmware branches or customer specific releases
1492 * tied to a specific (major,minor,update) version.
1494 uint16_t mgmt_fw_patch;
1496 * This field represents the major version of network control
1497 * firmware. A change in major version represents
1500 uint16_t netctrl_fw_major;
1502 * This field represents the minor version of network control
1503 * firmware. A change in minor version represents significant
1504 * functionality changes.
1506 uint16_t netctrl_fw_minor;
1508 * This field represents the build version of network control
1509 * firmware. A change in update version represents bug fixes.
1511 uint16_t netctrl_fw_build;
1513 * This field is a reserved field. This field can be used to
1514 * represent firmware branches or customer specific releases
1515 * tied to a specific (major,minor,update) version
1517 uint16_t netctrl_fw_patch;
1519 * This field represents the major version of RoCE firmware.
1520 * A change in major version represents a major release.
1522 uint16_t roce_fw_major;
1524 * This field represents the minor version of RoCE firmware.
1525 * A change in minor version represents significant
1526 * functionality changes.
1528 uint16_t roce_fw_minor;
1530 * This field represents the build version of RoCE firmware.
1531 * A change in update version represents bug fixes.
1533 uint16_t roce_fw_build;
1535 * This field is a reserved field. This field can be used to
1536 * represent firmware branches or customer specific releases
1537 * tied to a specific (major,minor,update) version
1539 uint16_t roce_fw_patch;
1541 * This field returns the maximum extended request length acceptable
1542 * by the device which allows requests greater than mailbox size when
1543 * used with the short cmd request format.
1545 uint16_t max_ext_req_len;
1546 uint8_t unused_1[5];
1548 * This field is used in Output records to indicate that the output
1549 * is completely written to RAM. This field should be read as '1'
1550 * to indicate that the output has been completely written.
1551 * When writing a command completion or response to an internal processor,
1552 * the order of writes has to be such that this field is written last.
1557 /* cfa_bds_read_cmd_data_msg (size:128b/16B) */
1558 struct cfa_bds_read_cmd_data_msg {
1559 /* This value selects the format for the mid-path command for the CFA. */
1562 * This is read command. From 32 to 128B can be read from a table
1563 * using this command.
1565 #define CFA_BDS_READ_CMD_DATA_MSG_OPCODE_READ UINT32_C(0x0)
1566 #define CFA_BDS_READ_CMD_DATA_MSG_OPCODE_LAST \
1567 CFA_BDS_READ_CMD_DATA_MSG_OPCODE_READ
1568 /* This value selects the table type to be acted upon. */
1570 /* This value selects the table type to be acted upon. */
1571 #define CFA_BDS_READ_CMD_DATA_MSG_TABLE_TYPE_MASK UINT32_C(0xf)
1572 #define CFA_BDS_READ_CMD_DATA_MSG_TABLE_TYPE_SFT 0
1573 /* This command acts on the action table of the specified scope. */
1574 #define CFA_BDS_READ_CMD_DATA_MSG_TABLE_TYPE_ACTION UINT32_C(0x0)
1575 /* This command acts on the exact match table of the specified scope. */
1576 #define CFA_BDS_READ_CMD_DATA_MSG_TABLE_TYPE_EM UINT32_C(0x1)
1577 #define CFA_BDS_READ_CMD_DATA_MSG_TABLE_TYPE_LAST \
1578 CFA_BDS_READ_CMD_DATA_MSG_TABLE_TYPE_EM
1579 /* This value selects which table scope will be accessed. */
1580 uint8_t table_scope;
1581 #define CFA_BDS_READ_CMD_DATA_MSG_TABLE_SCOPE_MASK UINT32_C(0x1f)
1582 #define CFA_BDS_READ_CMD_DATA_MSG_TABLE_SCOPE_SFT 0
1584 * This value identifies the number of 32B units will be accessed. A
1585 * value of zero is invalid. Maximum value is 4.
1588 #define CFA_BDS_READ_CMD_DATA_MSG_DATA_SIZE_MASK UINT32_C(0x7)
1589 #define CFA_BDS_READ_CMD_DATA_MSG_DATA_SIZE_SFT 0
1590 /* This is the 32B index into the selected table to access. */
1591 uint32_t table_index;
1592 #define CFA_BDS_READ_CMD_DATA_MSG_TABLE_INDEX_MASK UINT32_C(0x3ffffff)
1593 #define CFA_BDS_READ_CMD_DATA_MSG_TABLE_INDEX_SFT 0
1595 * This is the 64b host address where you want the data returned to. The
1596 * data will be written to the same function as the one that owns the SQ
1597 * this command is read from. The bottom two bits of this value must be
1598 * zero. The size of the write is controlled by the data_size field.
1600 uint64_t host_address;
1603 /* cfa_bds_write_cmd_data_msg (size:1152b/144B) */
1604 struct cfa_bds_write_cmd_data_msg {
1605 /* This value selects the format for the mid-path command for the CFA. */
1608 * This is write command. From 32 to 128B can be written to a table
1609 * using this command.
1611 #define CFA_BDS_WRITE_CMD_DATA_MSG_OPCODE_WRITE UINT32_C(0x1)
1612 #define CFA_BDS_WRITE_CMD_DATA_MSG_OPCODE_LAST \
1613 CFA_BDS_WRITE_CMD_DATA_MSG_OPCODE_WRITE
1614 /* This value selects the table type to be acted upon. */
1615 uint8_t write_thru_table_type;
1616 /* This value selects the table type to be acted upon. */
1617 #define CFA_BDS_WRITE_CMD_DATA_MSG_TABLE_TYPE_MASK UINT32_C(0xf)
1618 #define CFA_BDS_WRITE_CMD_DATA_MSG_TABLE_TYPE_SFT 0
1619 /* This command acts on the action table of the specified scope. */
1620 #define CFA_BDS_WRITE_CMD_DATA_MSG_TABLE_TYPE_ACTION UINT32_C(0x0)
1621 /* This command acts on the exact match table of the specified scope. */
1622 #define CFA_BDS_WRITE_CMD_DATA_MSG_TABLE_TYPE_EM UINT32_C(0x1)
1623 #define CFA_BDS_WRITE_CMD_DATA_MSG_TABLE_TYPE_LAST \
1624 CFA_BDS_WRITE_CMD_DATA_MSG_TABLE_TYPE_EM
1626 * Indicates write-through control. Indicates write-through when set,
1627 * or write back when cleared.
1629 #define CFA_BDS_WRITE_CMD_DATA_MSG_WRITE_THRU UINT32_C(0x10)
1630 /* This value selects which table scope will be accessed. */
1631 uint8_t table_scope;
1632 #define CFA_BDS_WRITE_CMD_DATA_MSG_TABLE_SCOPE_MASK UINT32_C(0x1f)
1633 #define CFA_BDS_WRITE_CMD_DATA_MSG_TABLE_SCOPE_SFT 0
1635 * This value identifies the number of 32B units will be accessed. A
1636 * value of zero is invalid. Maximum value is 4.
1639 #define CFA_BDS_WRITE_CMD_DATA_MSG_DATA_SIZE_MASK UINT32_C(0x7)
1640 #define CFA_BDS_WRITE_CMD_DATA_MSG_DATA_SIZE_SFT 0
1641 /* This is the 32B index into the selected table to access. */
1642 uint32_t table_index;
1643 #define CFA_BDS_WRITE_CMD_DATA_MSG_TABLE_INDEX_MASK UINT32_C(0x3ffffff)
1644 #define CFA_BDS_WRITE_CMD_DATA_MSG_TABLE_INDEX_SFT 0
1648 * This is the data to be written. Data length is determined by the
1649 * data_size field. The bd_cnt in the encapsulating BD must also be set
1650 * correctly to ensure that the BD is processed correctly and the full
1651 * WRITE_CMD message is extracted from the BD.
1656 /* cfa_bds_read_clr_cmd_data_msg (size:256b/32B) */
1657 struct cfa_bds_read_clr_cmd_data_msg {
1658 /* This value selects the format for the mid-path command for the CFA. */
1661 * This is read-clear command. 32B can be read from a table and
1662 * a 16b mask can be used to clear specific 16b units after the
1663 * read as an atomic operation.
1665 #define CFA_BDS_READ_CLR_CMD_DATA_MSG_OPCODE_READ_CLR UINT32_C(0x2)
1666 #define CFA_BDS_READ_CLR_CMD_DATA_MSG_OPCODE_LAST \
1667 CFA_BDS_READ_CLR_CMD_DATA_MSG_OPCODE_READ_CLR
1668 /* This value selects the table type to be acted upon. */
1670 /* This value selects the table type to be acted upon. */
1671 #define CFA_BDS_READ_CLR_CMD_DATA_MSG_TABLE_TYPE_MASK UINT32_C(0xf)
1672 #define CFA_BDS_READ_CLR_CMD_DATA_MSG_TABLE_TYPE_SFT 0
1673 /* This command acts on the action table of the specified scope. */
1674 #define CFA_BDS_READ_CLR_CMD_DATA_MSG_TABLE_TYPE_ACTION UINT32_C(0x0)
1675 /* This command acts on the exact match table of the specified scope. */
1676 #define CFA_BDS_READ_CLR_CMD_DATA_MSG_TABLE_TYPE_EM UINT32_C(0x1)
1677 #define CFA_BDS_READ_CLR_CMD_DATA_MSG_TABLE_TYPE_LAST \
1678 CFA_BDS_READ_CLR_CMD_DATA_MSG_TABLE_TYPE_EM
1679 /* This value selects which table scope will be accessed. */
1680 uint8_t table_scope;
1681 #define CFA_BDS_READ_CLR_CMD_DATA_MSG_TABLE_SCOPE_MASK UINT32_C(0x1f)
1682 #define CFA_BDS_READ_CLR_CMD_DATA_MSG_TABLE_SCOPE_SFT 0
1684 * This value identifies the number of 32B units will be accessed.
1685 * Always set the value to 1.
1688 #define CFA_BDS_READ_CLR_CMD_DATA_MSG_DATA_SIZE_MASK UINT32_C(0x7)
1689 #define CFA_BDS_READ_CLR_CMD_DATA_MSG_DATA_SIZE_SFT 0
1690 /* This is the 32B index into the selected table to access. */
1691 uint32_t table_index;
1692 #define CFA_BDS_READ_CLR_CMD_DATA_MSG_TABLE_INDEX_MASK \
1694 #define CFA_BDS_READ_CLR_CMD_DATA_MSG_TABLE_INDEX_SFT 0
1696 * This is the 64b host address where you want the data returned to. The
1697 * data will be written to the same function as the one that owns the SQ
1698 * this command is read from. The bottom two bits of this value must be
1699 * zero. The size of the write is controlled by the data_size field.
1701 uint64_t host_address;
1703 * This is active high clear mask for the 32B of data that this command
1704 * can read. Bit 0 of the field will clear bits 15:0 of the first word
1705 * of data read when set to '1'.
1707 uint16_t clear_mask;
1708 uint16_t unused0[3];
1709 uint16_t unused1[4];
1712 /* cfa_bds_em_insert_cmd_data_msg (size:1152b/144B) */
1713 struct cfa_bds_em_insert_cmd_data_msg {
1714 /* This value selects the format for the mid-path command for the CFA. */
1717 * An exact match table insert will be attempted into the table.
1718 * If there is a free location in the bucket, the payload will
1719 * be written to the bucket.
1721 #define CFA_BDS_EM_INSERT_CMD_DATA_MSG_OPCODE_EM_INSERT UINT32_C(0x3)
1722 #define CFA_BDS_EM_INSERT_CMD_DATA_MSG_OPCODE_LAST \
1723 CFA_BDS_EM_INSERT_CMD_DATA_MSG_OPCODE_EM_INSERT
1725 * Indicates write-through control. Indicates write-through when set,
1726 * or write back when cleared.
1729 #define CFA_BDS_EM_INSERT_CMD_DATA_MSG_UNUSED_MASK UINT32_C(0xf)
1730 #define CFA_BDS_EM_INSERT_CMD_DATA_MSG_UNUSED_SFT 0
1732 * Indicates write-through control. Indicates write-through when set,
1733 * or write back when cleared.
1735 #define CFA_BDS_EM_INSERT_CMD_DATA_MSG_WRITE_THRU UINT32_C(0x10)
1736 /* This value selects which table scope will be accessed. */
1737 uint8_t table_scope;
1738 #define CFA_BDS_EM_INSERT_CMD_DATA_MSG_TABLE_SCOPE_MASK UINT32_C(0x1f)
1739 #define CFA_BDS_EM_INSERT_CMD_DATA_MSG_TABLE_SCOPE_SFT 0
1741 * This value identifies the number of 32B units will be accessed. A
1742 * value of zero is invalid. Maximum value is 4.
1745 #define CFA_BDS_EM_INSERT_CMD_DATA_MSG_DATA_SIZE_MASK UINT32_C(0x7)
1746 #define CFA_BDS_EM_INSERT_CMD_DATA_MSG_DATA_SIZE_SFT 0
1747 /* This is the 32B index into the selected table to access. */
1748 uint32_t table_index;
1749 #define CFA_BDS_EM_INSERT_CMD_DATA_MSG_TABLE_INDEX_MASK \
1751 #define CFA_BDS_EM_INSERT_CMD_DATA_MSG_TABLE_INDEX_SFT 0
1753 * This is the 64b host address where you want the data returned to. The
1754 * data will be written to the same function as the one that owns the SQ
1756 uint64_t host_address;
1758 * This is the Exact Match Lookup Record. Data length is determined by
1759 * the data_size field. The bd_cnt in the encapsulating BD must also be
1764 /* cfa_bds_em_delete_cmd_data_msg (size:256b/32B) */
1765 struct cfa_bds_em_delete_cmd_data_msg {
1766 /* This value selects the format for the mid-path command for the CFA. */
1768 /* An exact match table delete will be attempted. */
1769 #define CFA_BDS_EM_DELETE_CMD_DATA_MSG_OPCODE_EM_DELETE UINT32_C(0x4)
1770 #define CFA_BDS_EM_DELETE_CMD_DATA_MSG_OPCODE_LAST \
1771 CFA_BDS_EM_DELETE_CMD_DATA_MSG_OPCODE_EM_DELETE
1773 * Indicates write-through control. Indicates write-through when set,
1774 * or write back when cleared.
1777 #define CFA_BDS_EM_DELETE_CMD_DATA_MSG_UNUSED_MASK UINT32_C(0xf)
1778 #define CFA_BDS_EM_DELETE_CMD_DATA_MSG_UNUSED_SFT 0
1780 * Indicates write-through control. Indicates write-through when set,
1781 * or write back when cleared.
1783 #define CFA_BDS_EM_DELETE_CMD_DATA_MSG_WRITE_THRU UINT32_C(0x10)
1784 /* This value selects which table scope will be accessed. */
1785 uint8_t table_scope;
1786 #define CFA_BDS_EM_DELETE_CMD_DATA_MSG_TABLE_SCOPE_MASK UINT32_C(0x1f)
1787 #define CFA_BDS_EM_DELETE_CMD_DATA_MSG_TABLE_SCOPE_SFT 0
1789 * This value identifies the number of 32B units will be accessed. A
1790 * value of zero is invalid. Maximum value is 4.
1793 #define CFA_BDS_EM_DELETE_CMD_DATA_MSG_DATA_SIZE_MASK UINT32_C(0x7)
1794 #define CFA_BDS_EM_DELETE_CMD_DATA_MSG_DATA_SIZE_SFT 0
1797 * This is the 64b host address where you want the data returned to. The
1798 * data will be written to the same function as the one that owns the SQ
1800 uint64_t host_address;
1802 * This is the Exact Match Lookup Record. Data length is determined by
1803 * the data_size field. The bd_cnt in the encapsulating BD must also be
1806 uint32_t unused1[2];
1809 /* cfa_bds_invalidate_cmd_data_msg (size:128b/16B) */
1810 struct cfa_bds_invalidate_cmd_data_msg {
1811 /* This value selects the format for the mid-path command for the CFA. */
1814 * The specified table area will be invalidated. If it is needed.
1815 * again, it will be read from the backing store.
1817 #define CFA_BDS_INVALIDATE_CMD_DATA_MSG_OPCODE_INVALIDATE UINT32_C(0x5)
1818 #define CFA_BDS_INVALIDATE_CMD_DATA_MSG_OPCODE_LAST \
1819 CFA_BDS_INVALIDATE_CMD_DATA_MSG_OPCODE_INVALIDATE
1820 /* This value selects the table type to be acted upon. */
1822 /* This value selects the table type to be acted upon. */
1823 #define CFA_BDS_INVALIDATE_CMD_DATA_MSG_TABLE_TYPE_MASK UINT32_C(0xf)
1824 #define CFA_BDS_INVALIDATE_CMD_DATA_MSG_TABLE_TYPE_SFT 0
1825 /* This command acts on the action table of the specified scope. */
1826 #define CFA_BDS_INVALIDATE_CMD_DATA_MSG_TABLE_TYPE_ACTION \
1828 /* This command acts on the exact match table of the specified scope. */
1829 #define CFA_BDS_INVALIDATE_CMD_DATA_MSG_TABLE_TYPE_EM \
1831 #define CFA_BDS_INVALIDATE_CMD_DATA_MSG_TABLE_TYPE_LAST \
1832 CFA_BDS_INVALIDATE_CMD_DATA_MSG_TABLE_TYPE_EM
1833 /* This value selects which table scope will be accessed. */
1834 uint8_t table_scope;
1835 #define CFA_BDS_INVALIDATE_CMD_DATA_MSG_TABLE_SCOPE_MASK UINT32_C(0x1f)
1836 #define CFA_BDS_INVALIDATE_CMD_DATA_MSG_TABLE_SCOPE_SFT 0
1837 /* This value specifies the number of cache lines to invalidate. */
1839 #define CFA_BDS_INVALIDATE_CMD_DATA_MSG_DATA_SIZE_MASK UINT32_C(0x7)
1840 #define CFA_BDS_INVALIDATE_CMD_DATA_MSG_DATA_SIZE_SFT 0
1841 /* This is the 32B index into the selected table to access. */
1842 uint32_t table_index;
1843 #define CFA_BDS_INVALIDATE_CMD_DATA_MSG_TABLE_INDEX_MASK \
1845 #define CFA_BDS_INVALIDATE_CMD_DATA_MSG_TABLE_INDEX_SFT 0
1849 /* cfa_bds_event_collect_cmd_data_msg (size:128b/16B) */
1850 struct cfa_bds_event_collect_cmd_data_msg {
1851 /* This value selects the format for the mid-path command for the CFA. */
1853 /* Reads notification messages from the Host Notification Queue. */
1854 #define CFA_BDS_EVENT_COLLECT_CMD_DATA_MSG_OPCODE_EVENT_COLLECT \
1856 #define CFA_BDS_EVENT_COLLECT_CMD_DATA_MSG_OPCODE_LAST \
1857 CFA_BDS_EVENT_COLLECT_CMD_DATA_MSG_OPCODE_EVENT_COLLECT
1859 /* This value selects which table scope will be accessed. */
1860 uint8_t table_scope;
1861 #define CFA_BDS_EVENT_COLLECT_CMD_DATA_MSG_TABLE_SCOPE_MASK \
1863 #define CFA_BDS_EVENT_COLLECT_CMD_DATA_MSG_TABLE_SCOPE_SFT 0
1865 * This value identifies the number of 32B units will be accessed. A
1866 * value of zero is invalid. Maximum value is 4.
1869 #define CFA_BDS_EVENT_COLLECT_CMD_DATA_MSG_DATA_SIZE_MASK UINT32_C(0x7)
1870 #define CFA_BDS_EVENT_COLLECT_CMD_DATA_MSG_DATA_SIZE_SFT 0
1873 * This is the 64b host address where you want the data returned to. The
1874 * data will be written to the same function as the one that owns the SQ
1876 uint64_t host_address;
1879 /* ce_bds_add_data_msg (size:512b/64B) */
1880 struct ce_bds_add_data_msg {
1881 uint32_t version_algorithm_kid_opcode;
1883 * This value selects the operation for the mid-path command for the
1886 #define CE_BDS_ADD_DATA_MSG_OPCODE_MASK UINT32_C(0xf)
1887 #define CE_BDS_ADD_DATA_MSG_OPCODE_SFT 0
1889 * This is the add command. Using this opcode, Host Driver can add
1890 * information required for kTLS processing. The information is
1891 * updated in the CFCK context.
1893 #define CE_BDS_ADD_DATA_MSG_OPCODE_ADD UINT32_C(0x1)
1894 #define CE_BDS_ADD_DATA_MSG_OPCODE_LAST \
1895 CE_BDS_ADD_DATA_MSG_OPCODE_ADD
1897 * This field is the Crypto Context ID. The KID is used to store
1898 * information used by the associated kTLS offloaded connection.
1900 #define CE_BDS_ADD_DATA_MSG_KID_MASK \
1902 #define CE_BDS_ADD_DATA_MSG_KID_SFT 4
1904 * Currently only two algorithms are supported, AES_GCM_128 and
1905 * AES_GCM_256. Additional bits for future growth.
1907 #define CE_BDS_ADD_DATA_MSG_ALGORITHM_MASK \
1909 #define CE_BDS_ADD_DATA_MSG_ALGORITHM_SFT 24
1910 /* AES_GCM_128 Algorithm */
1911 #define CE_BDS_ADD_DATA_MSG_ALGORITHM_AES_GCM_128 \
1913 /* AES_GCM_256 Algorithm */
1914 #define CE_BDS_ADD_DATA_MSG_ALGORITHM_AES_GCM_256 \
1917 * Version number of TLS connection. HW will provide registers that
1918 * converts the 4b encoded version number to 16b of actual version
1919 * number in the TLS Header. * Initialized --> By mid-path command *
1920 * Updated --> Never though another mid-path command will result in an
1923 #define CE_BDS_ADD_DATA_MSG_VERSION_MASK \
1924 UINT32_C(0xf0000000)
1925 #define CE_BDS_ADD_DATA_MSG_VERSION_SFT 28
1926 /* TLS1.2 Version */
1927 #define CE_BDS_ADD_DATA_MSG__TLS1_2 \
1928 (UINT32_C(0x0) << 28)
1929 /* TLS1.3 Version */
1930 #define CE_BDS_ADD_DATA_MSG__TLS1_3 \
1931 (UINT32_C(0x1) << 28)
1932 #define CE_BDS_ADD_DATA_MSG__LAST \
1933 CE_BDS_ADD_DATA_MSG__TLS1_3
1935 * Command Type in the TLS header. HW will provide registers that
1936 * converts the 3b encoded command type to 8b of actual command type in
1937 * the TLS Header. * Initialized --> By mid-path command * Updated -->
1938 * Never though another mid-path command will result in an update
1941 #define CE_BDS_ADD_DATA_MSG_CMD_TYPE_MASK UINT32_C(0x7)
1942 #define CE_BDS_ADD_DATA_MSG_CMD_TYPE_SFT 0
1944 #define CE_BDS_ADD_DATA_MSG_CMD_TYPE_APP UINT32_C(0x0)
1945 #define CE_BDS_ADD_DATA_MSG_CMD_TYPE_LAST \
1946 CE_BDS_ADD_DATA_MSG_CMD_TYPE_APP
1949 * Salt is part of the nonce that is used as the Initial Vector (IV) in
1950 * AES-GCM cipher suites. These are exchanged as part of the handshake
1951 * process and is either the client_write_iv (when the client is
1952 * sending) or server_write_iv (when the server is sending). In
1953 * TLS1.2, 4B of Salt is concatenated with 8B of explicit_nonce to
1954 * generate the 12B of IV. In TLS1.3, 8B of TLS record sequence number
1955 * is zero padded to 12B and then xor'ed with the 4B of salt to generate
1956 * the 12B of IV. This value is initialized by this mid-path command.
1961 * This field keeps track of the TCP sequence number that is expected as
1962 * the first byte in the next TCP packet. This field is calculated by HW
1963 * using the output of the parser. The field is initialized as part of
1964 * the Mid-path BD download/update of a kTLS connection. For every TCP
1965 * packet processed, TCE HW will update the value to Current packet TCP
1966 * sequence number + Current packet TCP Payload Length.
1968 uint32_t pkt_tcp_seq_num;
1970 * This field maintains the TCP sequence number of the first byte in the
1971 * header of the active TLS record. This field is initialized as part of
1972 * the Mid-path BD download/update of a kTLS connection. For every
1973 * record that is processed, TCE HW copies the value from the
1974 * next_tls_header_tcp_seq_num field.
1976 uint32_t tls_header_tcp_seq_num;
1978 * This is sequence number for the TLS record in a particular session.
1979 * In TLS1.2, record sequence number is part of the Associated Data (AD)
1980 * in the AEAD algorithm. In TLS1.3, record sequence number is part of
1981 * the Initial Vector (IV). The field is initialized as part of the
1982 * mid-path BD download/update of a kTLS connection. TCE HW increments
1983 * the field after that for every record processed as it parses the TCP
1986 uint32_t record_seq_num[2];
1988 * Key used for encrypting or decrypting TLS records. The Key is
1989 * exchanged during the hand-shake protocol by the client-server and
1990 * provided to HW through this mid-path BD.
1992 uint32_t session_key[8];
1995 /* ce_bds_delete_data_msg (size:64b/8B) */
1996 struct ce_bds_delete_data_msg {
1997 uint32_t kid_opcode;
1999 * This value selects the operation for the mid-path command for the
2002 #define CE_BDS_DELETE_DATA_MSG_OPCODE_MASK UINT32_C(0xf)
2003 #define CE_BDS_DELETE_DATA_MSG_OPCODE_SFT 0
2005 * This is the delete command. Using this opcode, the host Driver
2006 * can remove a key context from the CFCK. If context is deleted
2007 * and packets with the same KID come through the pipeline, the
2008 * following actions are taken. For transmit packets, no crypto
2009 * operation will be performed, payload will be zero'ed out. For
2010 * receive packets, no crypto operation will be performed,
2011 * payload will be unmodified.
2013 #define CE_BDS_DELETE_DATA_MSG_OPCODE_DELETE UINT32_C(0x2)
2014 #define CE_BDS_DELETE_DATA_MSG_OPCODE_LAST \
2015 CE_BDS_DELETE_DATA_MSG_OPCODE_DELETE
2017 * This field is the Crypto Context ID. The KID is used to store
2018 * information used by the associated kTLS offloaded connection.
2020 #define CE_BDS_DELETE_DATA_MSG_KID_MASK UINT32_C(0xfffff0)
2021 #define CE_BDS_DELETE_DATA_MSG_KID_SFT 4
2025 /* ce_bds_resync_resp_ack_msg (size:128b/16B) */
2026 struct ce_bds_resync_resp_ack_msg {
2027 uint32_t resync_status_kid_opcode;
2029 * This value selects the operation for the mid-path command for the
2032 #define CE_BDS_RESYNC_RESP_ACK_MSG_OPCODE_MASK UINT32_C(0xf)
2033 #define CE_BDS_RESYNC_RESP_ACK_MSG_OPCODE_SFT 0
2035 * This command is used by the driver as a response to the resync
2036 * request sent by the crypto engine.
2038 #define CE_BDS_RESYNC_RESP_ACK_MSG_OPCODE_RESYNC UINT32_C(0x3)
2039 #define CE_BDS_RESYNC_RESP_ACK_MSG_OPCODE_LAST \
2040 CE_BDS_RESYNC_RESP_ACK_MSG_OPCODE_RESYNC
2042 * This field is the Crypto Context ID. The KID is used to store
2043 * information used by the associated kTLS offloaded connection.
2045 #define CE_BDS_RESYNC_RESP_ACK_MSG_KID_MASK UINT32_C(0xfffff0)
2046 #define CE_BDS_RESYNC_RESP_ACK_MSG_KID_SFT 4
2048 * This field indicates if the resync request resulted in a success or
2051 #define CE_BDS_RESYNC_RESP_ACK_MSG_RESYNC_STATUS \
2054 * An ACK indicates that the driver was able to find the TLS record
2055 * associated with TCP sequence number provided by the HW
2057 #define CE_BDS_RESYNC_RESP_ACK_MSG_RESYNC_STATUS_ACK \
2058 (UINT32_C(0x0) << 24)
2059 #define CE_BDS_RESYNC_RESP_ACK_MSG_RESYNC_STATUS_LAST \
2060 CE_BDS_RESYNC_RESP_ACK_MSG_RESYNC_STATUS_ACK
2062 * This field is the echo of the TCP sequence number provided in the
2063 * resync request by the HW. If HW sent multiple resync requests, it
2064 * only tracks the latest TCP sequence number. When the response from
2065 * the Driver doesn't match the latest request, HW will drop the resync
2068 uint32_t resync_record_tcp_seq_num;
2070 * This field indicates the TLS record sequence number associated with
2071 * the resync request. HW will take this number and add the delta records
2072 * it has found since sending the resync request, update the context and
2073 * resume decrypting records.
2075 uint32_t resync_record_seq_num[2];
2078 /* ce_bds_resync_resp_nack_msg (size:64b/8B) */
2079 struct ce_bds_resync_resp_nack_msg {
2080 uint32_t resync_status_kid_opcode;
2082 * This value selects the operation for the mid-path command for the
2085 #define CE_BDS_RESYNC_RESP_NACK_MSG_OPCODE_MASK UINT32_C(0xf)
2086 #define CE_BDS_RESYNC_RESP_NACK_MSG_OPCODE_SFT 0
2088 * This command is used by the driver as a response to the resync
2089 * request sent by the crypto engine.
2091 #define CE_BDS_RESYNC_RESP_NACK_MSG_OPCODE_RESYNC UINT32_C(0x3)
2092 #define CE_BDS_RESYNC_RESP_NACK_MSG_OPCODE_LAST \
2093 CE_BDS_RESYNC_RESP_NACK_MSG_OPCODE_RESYNC
2095 * This field is the Crypto Context ID. The KID is used to store
2096 * information used by the associated kTLS offloaded connection.
2098 #define CE_BDS_RESYNC_RESP_NACK_MSG_KID_MASK \
2100 #define CE_BDS_RESYNC_RESP_NACK_MSG_KID_SFT 4
2102 * This field indicates if the resync request resulted in a success or
2105 #define CE_BDS_RESYNC_RESP_NACK_MSG_RESYNC_STATUS \
2108 * An NAK indicates that the driver wasn't able to find the TLS
2109 * record associated with TCP sequence number provided by the HW
2111 #define CE_BDS_RESYNC_RESP_NACK_MSG_RESYNC_STATUS_NACK \
2112 (UINT32_C(0x1) << 24)
2113 #define CE_BDS_RESYNC_RESP_NACK_MSG_RESYNC_STATUS_LAST \
2114 CE_BDS_RESYNC_RESP_NACK_MSG_RESYNC_STATUS_NACK
2116 * This field is the echo of the TCP sequence number provided in the
2117 * resync request by the HW. If HW sent multiple resync requests, it
2118 * only tracks the latest TCP sequence number. When the response from
2119 * the Driver doesn't match the latest request, HW will drop the resync
2122 uint32_t resync_record_tcp_seq_num;
2125 /* crypto_presync_bd_cmd (size:256b/32B) */
2126 struct crypto_presync_bd_cmd {
2129 * Typically, presync BDs are used for packet retransmissions. Source
2130 * port sends all the packets in order over the network to destination
2131 * port and packets get dropped in the network. The destination port
2132 * will request retranmission of dropped packets and source port driver
2133 * will send presync BD to setup the transmitter appropriately. It will
2134 * provide the start and end TCP sequence number of the data to be
2135 * transmitted. HW keeps two sets of context variable, one for in order
2136 * traffic and one for retransmission traffic. HW is designed to
2137 * transmit everything posted in the presync BD and return to in order
2138 * mode after that. No inorder context variables are updated in the
2139 * process. There is a special case where packets can be dropped
2140 * between the TCP stack and Device Driver (Berkeley Packet Filter for
2141 * ex) and HW still needs to transmit rest of the traffic. In this
2142 * mode, driver will send a presync BD as if it is a retransmission but
2143 * at the end of the transmission, the in order variables need to be
2144 * updated. This flag is used by driver to indicate that in order
2145 * variables needs to be updated at the end of completing the task
2146 * associated with the presync BD.
2148 #define CRYPTO_PRESYNC_BD_CMD_FLAGS_UPDATE_IN_ORDER_VAR \
2153 * This field maintains the TCP sequence number of the first byte in the
2154 * Header of the active TLS record. This field is set to 0 during
2155 * mid-path BD updates, but is set to correct value when a presync BD is
2156 * detected. For every record that is processed, the value from the
2157 * next_tls_header_tcp_seq_num field is copied.
2159 uint32_t header_tcp_seq_num;
2161 * When a retransmitted packet has a TLS authentication TAG present and
2162 * the data spans multiple TCP Packets, HW is required to read the entire
2163 * record to recalculate the TAG but only transmit what is required. This
2164 * field is the start TCP sequence number of the packet(s) that need to
2165 * be re-transmitted. This field is initialized to 0 during Mid-path BD
2166 * add command and initialized to value provided by the driver when
2167 * Pre-sync BD is detected. This field is never updated unless another
2168 * Pre-sync BD signaling a new retransmission is scheduled.
2170 uint32_t start_tcp_seq_num;
2172 * When a retransmitted packet has a TLS authentication TAG present and
2173 * the data spans multiple TCP Packets, HW is required to read the
2174 * entire record to recalculate the TAG but only transmit what is
2175 * required. This field is the end TCP sequence number of the packet(s)
2176 * that need to be re-transmitted. This field is initialized to 0 during
2177 * Mid-path BD add command and initialized to value provided by the
2178 * driver when Pre-sync BD is detected. This field is never updated
2179 * unless another Pre-sync BD signaling a new retransmission is
2182 uint32_t end_tcp_seq_num;
2184 * For TLS1.2, an explicit nonce is used as part of the IV (concatenated
2185 * with the SALT). For retans packets, this field is extracted from the
2186 * TLS record, field right after the TLS Header and stored in the
2187 * context. This field needs to be stored in context as TCP segmentation
2188 * could have split the field into multiple TCP packets. This value is
2189 * initialized to 0 when presync BD is detected by taking the value from
2190 * the first TLS header. When subsequent TLS Headers are detected, the
2191 * value is extracted from packet.
2193 uint32_t explicit_nonce[2];
2195 * This is sequence number for the TLS record in a particular session. In
2196 * TLS1.2, record sequence number is part of the Associated Data (AD) in
2197 * the AEAD algorithm. In TLS1.3, record sequence number is part of the
2198 * Initial Vector (IV). The field is initialized to 0 during Mid-path BD
2199 * download. Is initialized to correct value when a pre-sync BD is
2200 * detected. TCE HW increments the field after that for every record
2201 * processed as it parses the TCP packet. Subsequent pre-sync BDs
2202 * delivering more retransmission instruction will also update this
2205 uint32_t record_seq_num[2];
2208 /* bd_base (size:64b/8B) */
2211 /* This value identifies the type of buffer descriptor. */
2212 #define BD_BASE_TYPE_MASK UINT32_C(0x3f)
2213 #define BD_BASE_TYPE_SFT 0
2215 * Indicates that this BD is 16B long and is used for
2216 * normal L2 packet transmission.
2218 #define BD_BASE_TYPE_TX_BD_SHORT UINT32_C(0x0)
2220 * Indicates that this BD is 1BB long and is an empty
2221 * TX BD. Not valid for use by the driver.
2223 #define BD_BASE_TYPE_TX_BD_EMPTY UINT32_C(0x1)
2225 * Indicates that this BD is 16B long and is an RX Producer
2226 * (i.e. empty) buffer descriptor.
2228 #define BD_BASE_TYPE_RX_PROD_PKT UINT32_C(0x4)
2230 * Indicates that this BD is 16B long and is an RX
2231 * Producer Buffer BD.
2233 #define BD_BASE_TYPE_RX_PROD_BFR UINT32_C(0x5)
2235 * Indicates that this BD is 16B long and is an
2236 * RX Producer Assembly Buffer Descriptor.
2238 #define BD_BASE_TYPE_RX_PROD_AGG UINT32_C(0x6)
2240 * Indicates that this BD is used to issue a command to one of
2241 * the mid-path destinations.
2243 #define BD_BASE_TYPE_TX_BD_MP_CMD UINT32_C(0x8)
2245 * Indicates that this BD is used to issue a cryptographic pre-
2246 * sync command through the fast path and destined for TCE.
2248 #define BD_BASE_TYPE_TX_BD_PRESYNC_CMD UINT32_C(0x9)
2250 * Indicates that this BD is 32B long and is used for
2251 * normal L2 packet transmission.
2253 #define BD_BASE_TYPE_TX_BD_LONG UINT32_C(0x10)
2255 * Indicates that this BD is 32B long and is used for
2256 * L2 packet transmission for small packets that require
2259 #define BD_BASE_TYPE_TX_BD_LONG_INLINE UINT32_C(0x11)
2260 #define BD_BASE_TYPE_LAST BD_BASE_TYPE_TX_BD_LONG_INLINE
2261 uint8_t unused_1[7];
2264 /* tx_bd_short (size:128b/16B) */
2265 struct tx_bd_short {
2267 * All bits in this field must be valid on the first BD of a packet.
2268 * Only the packet_end bit must be valid for the remaining BDs
2271 uint16_t flags_type;
2272 /* This value identifies the type of buffer descriptor. */
2273 #define TX_BD_SHORT_TYPE_MASK UINT32_C(0x3f)
2274 #define TX_BD_SHORT_TYPE_SFT 0
2276 * Indicates that this BD is 16B long and is used for
2277 * normal L2 packet transmission.
2279 #define TX_BD_SHORT_TYPE_TX_BD_SHORT UINT32_C(0x0)
2280 #define TX_BD_SHORT_TYPE_LAST TX_BD_SHORT_TYPE_TX_BD_SHORT
2282 * All bits in this field must be valid on the first BD of a packet.
2283 * Only the packet_end bit must be valid for the remaining BDs
2286 #define TX_BD_SHORT_FLAGS_MASK UINT32_C(0xffc0)
2287 #define TX_BD_SHORT_FLAGS_SFT 6
2289 * If set to 1, the packet ends with the data in the buffer
2290 * pointed to by this descriptor. This flag must be
2291 * valid on every BD.
2293 #define TX_BD_SHORT_FLAGS_PACKET_END UINT32_C(0x40)
2295 * If set to 1, the device will not generate a completion for
2296 * this transmit packet unless there is an error in it's
2299 * is set to 0, then the packet will be completed normally.
2301 * This bit must be valid only on the first BD of a packet.
2303 #define TX_BD_SHORT_FLAGS_NO_CMPL UINT32_C(0x80)
2305 * This value indicates how many 16B BD locations are consumed
2306 * in the ring by this packet.
2307 * A value of 1 indicates that this BD is the only BD (and that
2308 * it is a short BD). A value
2309 * of 3 indicates either 3 short BDs or 1 long BD and one short
2310 * BD in the packet. A value of 0 indicates
2311 * that there are 32 BD locations in the packet (the maximum).
2313 * This field is valid only on the first BD of a packet.
2315 #define TX_BD_SHORT_FLAGS_BD_CNT_MASK UINT32_C(0x1f00)
2316 #define TX_BD_SHORT_FLAGS_BD_CNT_SFT 8
2318 * This value is a hint for the length of the entire packet.
2319 * It is used by the chip to optimize internal processing.
2321 * The packet will be dropped if the hint is too short.
2323 * This field is valid only on the first BD of a packet.
2325 #define TX_BD_SHORT_FLAGS_LHINT_MASK UINT32_C(0x6000)
2326 #define TX_BD_SHORT_FLAGS_LHINT_SFT 13
2327 /* indicates packet length < 512B */
2328 #define TX_BD_SHORT_FLAGS_LHINT_LT512 (UINT32_C(0x0) << 13)
2329 /* indicates 512 <= packet length < 1KB */
2330 #define TX_BD_SHORT_FLAGS_LHINT_LT1K (UINT32_C(0x1) << 13)
2331 /* indicates 1KB <= packet length < 2KB */
2332 #define TX_BD_SHORT_FLAGS_LHINT_LT2K (UINT32_C(0x2) << 13)
2333 /* indicates packet length >= 2KB */
2334 #define TX_BD_SHORT_FLAGS_LHINT_GTE2K (UINT32_C(0x3) << 13)
2335 #define TX_BD_SHORT_FLAGS_LHINT_LAST \
2336 TX_BD_SHORT_FLAGS_LHINT_GTE2K
2338 * If set to 1, the device immediately updates the Send Consumer
2339 * Index after the buffer associated with this descriptor has
2340 * been transferred via DMA to NIC memory from host memory. An
2341 * interrupt may or may not be generated according to the state
2342 * of the interrupt avoidance mechanisms. If this bit
2343 * is set to 0, then the Consumer Index is only updated as soon
2344 * as one of the host interrupt coalescing conditions has been met.
2346 * This bit must be valid on the first BD of a packet.
2348 #define TX_BD_SHORT_FLAGS_COAL_NOW UINT32_C(0x8000)
2350 * This is the length of the host physical buffer this BD describes
2353 * This field must be valid on all BDs of a packet.
2357 * The opaque data field is pass through to the completion and can be
2358 * used for any data that the driver wants to associate with the
2361 * This field must be valid on the first BD of a packet. If completion
2362 * coalescing is enabled on the TX ring, it is suggested that the driver
2363 * populate the opaque field to indicate the specific TX ring with which
2364 * the completion is associated, then utilize the opaque and sq_cons_idx
2365 * fields in the coalesced completion record to determine the specific
2366 * packets that are to be completed on that ring.
2370 * This is the host physical address for the portion of the packet
2371 * described by this TX BD.
2373 * This value must be valid on all BDs of a packet.
2378 /* tx_bd_long (size:128b/16B) */
2380 /* This value identifies the type of buffer descriptor. */
2381 uint16_t flags_type;
2383 * This value indicates the type of buffer descriptor.
2386 #define TX_BD_LONG_TYPE_MASK UINT32_C(0x3f)
2387 #define TX_BD_LONG_TYPE_SFT 0
2389 * Indicates that this BD is 32B long and is used for
2390 * normal L2 packet transmission.
2392 #define TX_BD_LONG_TYPE_TX_BD_LONG UINT32_C(0x10)
2393 #define TX_BD_LONG_TYPE_LAST TX_BD_LONG_TYPE_TX_BD_LONG
2395 * All bits in this field must be valid on the first BD of a packet.
2396 * Only the packet_end bit must be valid for the remaining BDs
2399 #define TX_BD_LONG_FLAGS_MASK UINT32_C(0xffc0)
2400 #define TX_BD_LONG_FLAGS_SFT 6
2402 * If set to 1, the packet ends with the data in the buffer
2403 * pointed to by this descriptor. This flag must be
2404 * valid on every BD.
2406 #define TX_BD_LONG_FLAGS_PACKET_END UINT32_C(0x40)
2408 * If set to 1, the device will not generate a completion for
2409 * this transmit packet unless there is an error in it's
2412 * is set to 0, then the packet will be completed normally.
2414 * This bit must be valid only on the first BD of a packet.
2416 #define TX_BD_LONG_FLAGS_NO_CMPL UINT32_C(0x80)
2418 * This value indicates how many 16B BD locations are consumed
2419 * in the ring by this packet.
2420 * A value of 1 indicates that this BD is the only BD (and that
2421 * it is a short BD). A value
2422 * of 3 indicates either 3 short BDs or 1 long BD and one short
2423 * BD in the packet. A value of 0 indicates
2424 * that there are 32 BD locations in the packet (the maximum).
2426 * This field is valid only on the first BD of a packet.
2428 #define TX_BD_LONG_FLAGS_BD_CNT_MASK UINT32_C(0x1f00)
2429 #define TX_BD_LONG_FLAGS_BD_CNT_SFT 8
2431 * This value is a hint for the length of the entire packet.
2432 * It is used by the chip to optimize internal processing.
2434 * The packet will be dropped if the hint is too short.
2436 * This field is valid only on the first BD of a packet.
2438 #define TX_BD_LONG_FLAGS_LHINT_MASK UINT32_C(0x6000)
2439 #define TX_BD_LONG_FLAGS_LHINT_SFT 13
2440 /* indicates packet length < 512B */
2441 #define TX_BD_LONG_FLAGS_LHINT_LT512 (UINT32_C(0x0) << 13)
2442 /* indicates 512 <= packet length < 1KB */
2443 #define TX_BD_LONG_FLAGS_LHINT_LT1K (UINT32_C(0x1) << 13)
2444 /* indicates 1KB <= packet length < 2KB */
2445 #define TX_BD_LONG_FLAGS_LHINT_LT2K (UINT32_C(0x2) << 13)
2446 /* indicates packet length >= 2KB */
2447 #define TX_BD_LONG_FLAGS_LHINT_GTE2K (UINT32_C(0x3) << 13)
2448 #define TX_BD_LONG_FLAGS_LHINT_LAST TX_BD_LONG_FLAGS_LHINT_GTE2K
2450 * If set to 1, the device immediately updates the Send Consumer
2451 * Index after the buffer associated with this descriptor has
2452 * been transferred via DMA to NIC memory from host memory. An
2453 * interrupt may or may not be generated according to the state
2454 * of the interrupt avoidance mechanisms. If this bit
2455 * is set to 0, then the Consumer Index is only updated as soon
2456 * as one of the host interrupt coalescing conditions has been met.
2458 * This bit must be valid on the first BD of a packet.
2460 #define TX_BD_LONG_FLAGS_COAL_NOW UINT32_C(0x8000)
2462 * This is the length of the host physical buffer this BD describes
2465 * This field must be valid on all BDs of a packet.
2469 * The opaque data field is passed through to the completion and can be
2470 * used for any data that the driver wants to associate with the
2473 * This field must be valid on the first BD of a packet. If completion
2474 * coalescing is enabled on the TX ring, it is suggested that the driver
2475 * populate the opaque field to indicate the specific TX ring with which
2476 * the completion is associated, then utilize the opaque and sq_cons_idx
2477 * fields in the coalesced completion record to determine the specific
2478 * packets that are to be completed on that ring.
2482 * This is the host physical address for the portion of the packet
2483 * described by this TX BD.
2485 * This value must be valid on all BDs of a packet.
2490 /* Last 16 bytes of tx_bd_long. */
2491 /* tx_bd_long_hi (size:128b/16B) */
2492 struct tx_bd_long_hi {
2494 * All bits in this field must be valid on the first BD of a packet.
2495 * Their value on other BDs of the packet will be ignored.
2499 * If set to 1, the controller replaces the TCP/UPD checksum
2500 * fields of normal TCP/UPD checksum, or the inner TCP/UDP
2501 * checksum field of the encapsulated TCP/UDP packets with the
2502 * hardware calculated TCP/UDP checksum for the packet associated
2503 * with this descriptor. The flag is ignored if the LSO flag is set.
2505 * This bit must be valid on the first BD of a packet.
2507 #define TX_BD_LONG_LFLAGS_TCP_UDP_CHKSUM UINT32_C(0x1)
2509 * If set to 1, the controller replaces the IP checksum of the
2510 * normal packets, or the inner IP checksum of the encapsulated
2511 * packets with the hardware calculated IP checksum for the
2512 * packet associated with this descriptor.
2514 * This bit must be valid on the first BD of a packet.
2516 #define TX_BD_LONG_LFLAGS_IP_CHKSUM UINT32_C(0x2)
2518 * If set to 1, the controller will not append an Ethernet CRC
2519 * to the end of the frame.
2521 * This bit must be valid on the first BD of a packet.
2523 * Packet must be 64B or longer when this flag is set. It is not
2524 * useful to use this bit with any form of TX offload such as
2525 * CSO or LSO. The intent is that the packet from the host already
2526 * has a valid Ethernet CRC on the packet.
2528 #define TX_BD_LONG_LFLAGS_NOCRC UINT32_C(0x4)
2530 * If set to 1, the device will record the time at which the packet
2531 * was actually transmitted at the TX MAC for 2-step time sync.
2533 * This bit must be valid on the first BD of a packet.
2535 #define TX_BD_LONG_LFLAGS_STAMP UINT32_C(0x8)
2537 * If set to 1, The controller replaces the tunnel IP checksum
2538 * field with hardware calculated IP checksum for the IP header
2539 * of the packet associated with this descriptor.
2541 * For outer UDP checksum, global outer UDP checksum TE_NIC register
2542 * needs to be enabled. If the global outer UDP checksum TE_NIC register
2543 * bit is set, outer UDP checksum will be calculated for the following
2545 * 1. Packets with tcp_udp_chksum flag set to offload checksum for inner
2546 * packet AND the inner packet is TCP/UDP. If the inner packet is ICMP for
2547 * example (non-TCP/UDP), even if the tcp_udp_chksum is set, the outer UDP
2548 * checksum will not be calculated.
2549 * 2. Packets with lso flag set which implies inner TCP checksum calculation
2550 * as part of LSO operation.
2552 #define TX_BD_LONG_LFLAGS_T_IP_CHKSUM UINT32_C(0x10)
2554 * If set to 1, the device will treat this packet with LSO(Large
2555 * Send Offload) processing for both normal or encapsulated
2556 * packets, which is a form of TCP segmentation. When this bit
2557 * is 1, the hdr_size and mss fields must be valid. The driver
2558 * doesn't need to set ot_ip_chksum, t_ip_chksum, ip_chksum, and
2559 * tcp_udp_chksum flags since the controller will replace the
2560 * appropriate checksum fields for segmented packets.
2562 * When this bit is 1, the hdr_size and mss fields must be valid.
2564 #define TX_BD_LONG_LFLAGS_LSO UINT32_C(0x20)
2566 * If set to zero when LSO is '1', then the IPID will be treated
2567 * as a 16b number and will be wrapped if it exceeds a value of
2570 * If set to one when LSO is '1', then the IPID will be treated
2571 * as a 15b number and will be wrapped if it exceeds a value 0f
2574 #define TX_BD_LONG_LFLAGS_IPID_FMT UINT32_C(0x40)
2576 * If set to zero when LSO is '1', then the IPID of the tunnel
2577 * IP header will not be modified during LSO operations.
2579 * If set to one when LSO is '1', then the IPID of the tunnel
2580 * IP header will be incremented for each subsequent segment of an
2583 * The flag is ignored if the LSO packet is a normal (non-tunneled)
2586 #define TX_BD_LONG_LFLAGS_T_IPID UINT32_C(0x80)
2588 * If set to '1', then the RoCE ICRC will be appended to the
2589 * packet. Packet must be a valid RoCE format packet.
2591 #define TX_BD_LONG_LFLAGS_ROCE_CRC UINT32_C(0x100)
2593 * If set to '1', then the FCoE CRC will be appended to the
2594 * packet. Packet must be a valid FCoE format packet.
2596 #define TX_BD_LONG_LFLAGS_FCOE_CRC UINT32_C(0x200)
2598 * If set to '1', then the timestamp from the BD is used. If cleared
2599 * to 0, then TWE provides the timestamp.
2601 #define TX_BD_LONG_LFLAGS_BD_TS_EN UINT32_C(0x400)
2603 * If set to '1', this operation will cause a trace capture in each
2604 * block it passes through.
2606 #define TX_BD_LONG_LFLAGS_DEBUG_TRACE UINT32_C(0x800)
2608 * If set to '1', the device will record the time at which the packet
2609 * was actually transmitted at the TX MAC for 1-step time sync. This
2610 * bit must be valid on the first BD of a packet.
2612 #define TX_BD_LONG_LFLAGS_STAMP_1STEP UINT32_C(0x1000)
2614 * If set to '1', the controller replaces the Outer-tunnel IP checksum
2615 * field with hardware calculated IP checksum for the IP header of the
2616 * packet associated with this descriptor. For outer UDP checksum, it
2617 * will be the following behavior for all cases independent of settings
2618 * of inner LSO and checksum offload BD flags. If outer UDP checksum
2619 * is 0, then do not update it. If outer UDP checksum is non zero, then
2620 * the hardware should compute and update it.
2622 #define TX_BD_LONG_LFLAGS_OT_IP_CHKSUM UINT32_C(0x2000)
2624 * If set to zero when LSO is '1', then the IPID of the Outer-tunnel IP
2625 * header will not be modified during LSO operations. If set to one
2626 * when LSO is '1', then the IPID of the Outer-tunnel IP header will be
2627 * incremented for each subsequent segment of an LSO operation. The
2628 * flag is ignored if the LSO packet is a normal (non-tunneled) TCP
2631 #define TX_BD_LONG_LFLAGS_OT_IPID UINT32_C(0x4000)
2633 * If set to '1', When set to 1, KTLS encryption will be enabled for
2636 #define TX_BD_LONG_LFLAGS_CRYPTO_EN UINT32_C(0x8000)
2637 uint16_t kid_or_ts_low_hdr_size;
2639 * When LSO is '1', this field must contain the offset of the
2640 * TCP payload from the beginning of the packet in as
2641 * 16b words. In case of encapsulated/tunneling packet, this field
2642 * contains the offset of the inner TCP payload from beginning of the
2643 * packet as 16-bit words.
2645 * This value must be valid on the first BD of a packet.
2647 #define TX_BD_LONG_HDR_SIZE_MASK UINT32_C(0x1ff)
2648 #define TX_BD_LONG_HDR_SIZE_SFT 0
2650 * If lflags.bd_ts_en is 1, this is the lower 7 bits of the 24-bit
2651 * timestamp. If lflags.crypto_en is 1, this is the lower 7 bits of the
2654 #define TX_BD_LONG_KID_OR_TS_LOW_MASK UINT32_C(0xfe00)
2655 #define TX_BD_LONG_KID_OR_TS_LOW_SFT 9
2656 uint32_t kid_or_ts_high_mss;
2658 * This is the MSS value that will be used to do the LSO processing.
2659 * The value is the length in bytes of the TCP payload for each
2660 * segment generated by the LSO operation.
2662 * This value must be valid on the first BD of a packet.
2664 #define TX_BD_LONG_MSS_MASK UINT32_C(0x7fff)
2665 #define TX_BD_LONG_MSS_SFT 0
2667 * If lflags.bd_ts_en is 1, this is the upper 17 bits of the 24-bit
2668 * timestamp. If lflags.crypto_en is 1, the least significant 13 bits
2669 * of this field contain the upper 13 bits of the 20-bit KID.
2671 #define TX_BD_LONG_KID_OR_TS_HIGH_MASK UINT32_C(0xffff8000)
2672 #define TX_BD_LONG_KID_OR_TS_HIGH_SFT 15
2674 * This value selects bits 25:16 of the CFA action to perform on the
2675 * packet. See the cfa_action field for more information.
2677 uint16_t cfa_action_high;
2678 #define TX_BD_LONG_CFA_ACTION_HIGH_MASK UINT32_C(0x3ff)
2679 #define TX_BD_LONG_CFA_ACTION_HIGH_SFT 0
2681 * This value selects a CFA action to perform on the packet.
2682 * Set this value to zero if no CFA action is desired.
2684 * This value must be valid on the first BD of a packet.
2686 uint16_t cfa_action;
2688 * This value is action meta-data that defines CFA edit operations
2689 * that are done in addition to any action editing.
2692 /* When key=1, This is the VLAN tag VID value. */
2693 #define TX_BD_LONG_CFA_META_VLAN_VID_MASK UINT32_C(0xfff)
2694 #define TX_BD_LONG_CFA_META_VLAN_VID_SFT 0
2695 /* When key=1, This is the VLAN tag DE value. */
2696 #define TX_BD_LONG_CFA_META_VLAN_DE UINT32_C(0x1000)
2697 /* When key=1, This is the VLAN tag PRI value. */
2698 #define TX_BD_LONG_CFA_META_VLAN_PRI_MASK UINT32_C(0xe000)
2699 #define TX_BD_LONG_CFA_META_VLAN_PRI_SFT 13
2700 /* When key=1, This is the VLAN tag TPID select value. */
2701 #define TX_BD_LONG_CFA_META_VLAN_TPID_MASK UINT32_C(0x70000)
2702 #define TX_BD_LONG_CFA_META_VLAN_TPID_SFT 16
2704 #define TX_BD_LONG_CFA_META_VLAN_TPID_TPID88A8 \
2705 (UINT32_C(0x0) << 16)
2707 #define TX_BD_LONG_CFA_META_VLAN_TPID_TPID8100 \
2708 (UINT32_C(0x1) << 16)
2710 #define TX_BD_LONG_CFA_META_VLAN_TPID_TPID9100 \
2711 (UINT32_C(0x2) << 16)
2713 #define TX_BD_LONG_CFA_META_VLAN_TPID_TPID9200 \
2714 (UINT32_C(0x3) << 16)
2716 #define TX_BD_LONG_CFA_META_VLAN_TPID_TPID9300 \
2717 (UINT32_C(0x4) << 16)
2718 /* Value programmed in CFA VLANTPID register. */
2719 #define TX_BD_LONG_CFA_META_VLAN_TPID_TPIDCFG \
2720 (UINT32_C(0x5) << 16)
2721 #define TX_BD_LONG_CFA_META_VLAN_TPID_LAST \
2722 TX_BD_LONG_CFA_META_VLAN_TPID_TPIDCFG
2723 /* When key=1, This is the VLAN tag TPID select value. */
2724 #define TX_BD_LONG_CFA_META_VLAN_RESERVED_MASK UINT32_C(0xff80000)
2725 #define TX_BD_LONG_CFA_META_VLAN_RESERVED_SFT 19
2727 * This field identifies the type of edit to be performed
2730 * This value must be valid on the first BD of a packet.
2732 #define TX_BD_LONG_CFA_META_KEY_MASK UINT32_C(0xf0000000)
2733 #define TX_BD_LONG_CFA_META_KEY_SFT 28
2735 #define TX_BD_LONG_CFA_META_KEY_NONE \
2736 (UINT32_C(0x0) << 28)
2738 * - meta[17:16] - TPID select value (0 = 0x8100).
2739 * - meta[15:12] - PRI/DE value.
2740 * - meta[11:0] - VID value.
2742 #define TX_BD_LONG_CFA_META_KEY_VLAN_TAG \
2743 (UINT32_C(0x1) << 28)
2746 * - Wh+/SR - this option is not supported.
2747 * - Thor - cfa_meta[15:0] is used for metadata output if en_bd_meta
2748 * is set in the Lookup Table.
2749 * - SR2 - {4’d0, cfa_meta[27:0]} is used for metadata output if
2750 * en_bd_meta is set in the Lookup Table.
2752 #define TX_BD_LONG_CFA_META_KEY_METADATA_TRANSFER \
2753 (UINT32_C(0x2) << 28)
2754 #define TX_BD_LONG_CFA_META_KEY_LAST \
2755 TX_BD_LONG_CFA_META_KEY_METADATA_TRANSFER
2759 * This structure is used to inform the NIC of packet data that needs to be
2760 * transmitted with additional processing that requires extra data such as
2761 * VLAN insertion plus attached inline data. This BD type may be used to
2762 * improve latency for small packets needing the additional extended features
2763 * supported by long BDs.
2765 /* tx_bd_long_inline (size:256b/32B) */
2766 struct tx_bd_long_inline {
2767 uint16_t flags_type;
2768 /* This value identifies the type of buffer descriptor. */
2769 #define TX_BD_LONG_INLINE_TYPE_MASK UINT32_C(0x3f)
2770 #define TX_BD_LONG_INLINE_TYPE_SFT 0
2772 * This type of BD is 32B long and is used for inline L2 packet
2775 #define TX_BD_LONG_INLINE_TYPE_TX_BD_LONG_INLINE UINT32_C(0x11)
2776 #define TX_BD_LONG_INLINE_TYPE_LAST \
2777 TX_BD_LONG_INLINE_TYPE_TX_BD_LONG_INLINE
2779 * All bits in this field may be set on the first BD of a packet.
2780 * Only the packet_end bit may be set in non-first BDs.
2782 #define TX_BD_LONG_INLINE_FLAGS_MASK UINT32_C(0xffc0)
2783 #define TX_BD_LONG_INLINE_FLAGS_SFT 6
2785 * If set to 1, the packet ends with the data in the buffer
2786 * pointed to by this descriptor. This flag must be
2787 * valid on every BD.
2789 #define TX_BD_LONG_INLINE_FLAGS_PACKET_END UINT32_C(0x40)
2791 * If set to 1, the device will not generate a completion for
2792 * this transmit packet unless there is an error in its processing.
2793 * If this bit is set to 0, then the packet will be completed
2796 * This bit may be set only on the first BD of a packet.
2798 #define TX_BD_LONG_INLINE_FLAGS_NO_CMPL UINT32_C(0x80)
2800 * This value indicates how many 16B BD locations are consumed
2801 * in the ring by this packet, including the BD and inline
2804 #define TX_BD_LONG_INLINE_FLAGS_BD_CNT_MASK UINT32_C(0x1f00)
2805 #define TX_BD_LONG_INLINE_FLAGS_BD_CNT_SFT 8
2806 /* This field is deprecated. */
2807 #define TX_BD_LONG_INLINE_FLAGS_LHINT_MASK UINT32_C(0x6000)
2808 #define TX_BD_LONG_INLINE_FLAGS_LHINT_SFT 13
2810 * If set to 1, the device immediately updates the Send Consumer
2811 * Index after the buffer associated with this descriptor has
2812 * been transferred via DMA to NIC memory from host memory. An
2813 * interrupt may or may not be generated according to the state
2814 * of the interrupt avoidance mechanisms. If this bit
2815 * is set to 0, then the Consumer Index is only updated as soon
2816 * as one of the host interrupt coalescing conditions has been met.
2818 * This bit must be valid on the first BD of a packet.
2820 #define TX_BD_LONG_INLINE_FLAGS_COAL_NOW UINT32_C(0x8000)
2822 * This is the length of the inline data, not including BD length, in
2824 * The maximum value is 480.
2826 * This field must be valid on all BDs of a packet.
2830 * The opaque data field is passed through to the completion and can be
2831 * used for any data that the driver wants to associate with the transmit
2832 * BD. This field must be valid on the first BD of a packet. If
2833 * completion coalescing is enabled on the TX ring, it is suggested that
2834 * the driver populate the opaque field to indicate the specific TX ring
2835 * with which the completion is associated, then utilize the opaque and
2836 * sq_cons_idx fields in the coalesced completion record to determine
2837 * the specific packets that are to be completed on that ring.
2839 * This field must be valid on the first BD of a packet.
2844 * All bits in this field must be valid on the first BD of a packet.
2845 * Their value on other BDs of the packet is ignored.
2849 * If set to 1, the controller replaces the TCP/UPD checksum
2850 * fields of normal TCP/UPD checksum, or the inner TCP/UDP
2851 * checksum field of the encapsulated TCP/UDP packets with the
2852 * hardware calculated TCP/UDP checksum for the packet associated
2853 * with this descriptor. The flag is ignored if the LSO flag is set.
2855 #define TX_BD_LONG_INLINE_LFLAGS_TCP_UDP_CHKSUM UINT32_C(0x1)
2857 * If set to 1, the controller replaces the IP checksum of the
2858 * normal packets, or the inner IP checksum of the encapsulated
2859 * packets with the hardware calculated IP checksum for the
2860 * packet associated with this descriptor.
2862 #define TX_BD_LONG_INLINE_LFLAGS_IP_CHKSUM UINT32_C(0x2)
2864 * If set to 1, the controller will not append an Ethernet CRC
2865 * to the end of the frame.
2867 * Packet must be 64B or longer when this flag is set. It is not
2868 * useful to use this bit with any form of TX offload such as
2869 * CSO or LSO. The intent is that the packet from the host already
2870 * has a valid Ethernet CRC on the packet.
2872 #define TX_BD_LONG_INLINE_LFLAGS_NOCRC UINT32_C(0x4)
2874 * If set to 1, the device will record the time at which the packet
2875 * was actually transmitted at the TX MAC for 2-step time sync. This
2876 * bit must be valid on the first BD of a packet.
2878 #define TX_BD_LONG_INLINE_LFLAGS_STAMP UINT32_C(0x8)
2880 * If set to 1, the controller replaces the tunnel IP checksum
2881 * field with hardware calculated IP checksum for the IP header
2882 * of the packet associated with this descriptor. The hardware
2883 * updates an outer UDP checksum if it is non-zero.
2885 #define TX_BD_LONG_INLINE_LFLAGS_T_IP_CHKSUM UINT32_C(0x10)
2887 * This bit must be 0 for BDs of this type. LSO is not supported with
2890 #define TX_BD_LONG_INLINE_LFLAGS_LSO UINT32_C(0x20)
2891 /* Since LSO is not supported with inline BDs, this bit is not used. */
2892 #define TX_BD_LONG_INLINE_LFLAGS_IPID_FMT UINT32_C(0x40)
2893 /* Since LSO is not supported with inline BDs, this bit is not used. */
2894 #define TX_BD_LONG_INLINE_LFLAGS_T_IPID UINT32_C(0x80)
2896 * If set to '1', then the RoCE ICRC will be appended to the
2897 * packet. Packet must be a valid RoCE format packet.
2899 #define TX_BD_LONG_INLINE_LFLAGS_ROCE_CRC UINT32_C(0x100)
2901 * If set to '1', then the FCoE CRC will be appended to the
2902 * packet. Packet must be a valid FCoE format packet.
2904 #define TX_BD_LONG_INLINE_LFLAGS_FCOE_CRC UINT32_C(0x200)
2906 * If set to '1', then the timestamp from the BD is used. If cleared
2907 * to 0, then TWE provides the timestamp.
2909 #define TX_BD_LONG_INLINE_LFLAGS_BD_TS_EN UINT32_C(0x400)
2911 * If set to '1', this operation will cause a trace capture in each
2912 * block it passes through.
2914 #define TX_BD_LONG_INLINE_LFLAGS_DEBUG_TRACE UINT32_C(0x800)
2916 * If set to '1', the device will record the time at which the packet
2917 * was actually transmitted at the TX MAC for 1-step time sync. This
2918 * bit must be valid on the first BD of a packet.
2920 #define TX_BD_LONG_INLINE_LFLAGS_STAMP_1STEP UINT32_C(0x1000)
2922 * If set to '1', the controller replaces the Outer-tunnel IP checksum
2923 * field with hardware calculated IP checksum for the IP header of the
2924 * packet associated with this descriptor. For outer UDP checksum, it
2925 * will be the following behavior for all cases independent of settings
2926 * of inner LSO and checksum offload BD flags. If outer UDP checksum
2927 * is 0, then do not update it. If outer UDP checksum is non zero, then
2928 * the hardware should compute and update it.
2930 #define TX_BD_LONG_INLINE_LFLAGS_OT_IP_CHKSUM UINT32_C(0x2000)
2932 * If set to zero when LSO is '1', then the IPID of the Outer-tunnel IP
2933 * header will not be modified during LSO operations. If set to one
2934 * when LSO is '1', then the IPID of the Outer-tunnel IP header will be
2935 * incremented for each subsequent segment of an LSO operation. The
2936 * flag is ignored if the LSO packet is a normal (non-tunneled) TCP
2939 #define TX_BD_LONG_INLINE_LFLAGS_OT_IPID UINT32_C(0x4000)
2941 * If set to '1', When set to 1, KTLS encryption will be enabled for
2944 #define TX_BD_LONG_INLINE_LFLAGS_CRYPTO_EN UINT32_C(0x8000)
2946 uint8_t kid_or_ts_low;
2947 #define TX_BD_LONG_INLINE_UNUSED UINT32_C(0x1)
2949 * If lflags.bd_ts_en is 1, this is the lower 7 bits of the 24-bit
2950 * timestamp. If lflags.crypto_en is 1, this is the lower 7 bits of
2953 #define TX_BD_LONG_INLINE_KID_OR_TS_LOW_MASK UINT32_C(0xfe)
2954 #define TX_BD_LONG_INLINE_KID_OR_TS_LOW_SFT 1
2955 uint32_t kid_or_ts_high;
2956 #define TX_BD_LONG_INLINE_UNUSED_MASK UINT32_C(0x7fff)
2957 #define TX_BD_LONG_INLINE_UNUSED_SFT 0
2959 * If lflags.bd_ts_en is 1, this is the upper 17 bits of the 24-bit
2960 * timestamp. If lflags.crypto_en is 1, the least significant 13 bits
2961 * of this field contain the upper 13 bits of the 20-bit KID.
2963 #define TX_BD_LONG_INLINE_KID_OR_TS_HIGH_MASK UINT32_C(0xffff8000)
2964 #define TX_BD_LONG_INLINE_KID_OR_TS_HIGH_SFT 15
2966 * This value selects bits 25:16 of the CFA action to perform on the
2967 * packet. See the cfa_action field for more information.
2969 uint16_t cfa_action_high;
2970 #define TX_BD_LONG_INLINE_CFA_ACTION_HIGH_MASK UINT32_C(0x3ff)
2971 #define TX_BD_LONG_INLINE_CFA_ACTION_HIGH_SFT 0
2973 * This value selects a CFA action to perform on the packet.
2974 * Set this value to zero if no CFA action is desired.
2976 * This value must be valid on the first BD of a packet.
2978 uint16_t cfa_action;
2980 * This value is action meta-data that defines CFA edit operations
2981 * that are done in addition to any action editing.
2984 /* When key = 1, this is the VLAN tag VID value. */
2985 #define TX_BD_LONG_INLINE_CFA_META_VLAN_VID_MASK UINT32_C(0xfff)
2986 #define TX_BD_LONG_INLINE_CFA_META_VLAN_VID_SFT 0
2987 /* When key = 1, this is the VLAN tag DE value. */
2988 #define TX_BD_LONG_INLINE_CFA_META_VLAN_DE \
2990 /* When key = 1, this is the VLAN tag PRI value. */
2991 #define TX_BD_LONG_INLINE_CFA_META_VLAN_PRI_MASK \
2993 #define TX_BD_LONG_INLINE_CFA_META_VLAN_PRI_SFT 13
2994 /* When key = 1, this is the VLAN tag TPID select value. */
2995 #define TX_BD_LONG_INLINE_CFA_META_VLAN_TPID_MASK \
2997 #define TX_BD_LONG_INLINE_CFA_META_VLAN_TPID_SFT 16
2999 #define TX_BD_LONG_INLINE_CFA_META_VLAN_TPID_TPID88A8 \
3000 (UINT32_C(0x0) << 16)
3002 #define TX_BD_LONG_INLINE_CFA_META_VLAN_TPID_TPID8100 \
3003 (UINT32_C(0x1) << 16)
3005 #define TX_BD_LONG_INLINE_CFA_META_VLAN_TPID_TPID9100 \
3006 (UINT32_C(0x2) << 16)
3008 #define TX_BD_LONG_INLINE_CFA_META_VLAN_TPID_TPID9200 \
3009 (UINT32_C(0x3) << 16)
3011 #define TX_BD_LONG_INLINE_CFA_META_VLAN_TPID_TPID9300 \
3012 (UINT32_C(0x4) << 16)
3013 /* Value programmed in CFA VLANTPID register. */
3014 #define TX_BD_LONG_INLINE_CFA_META_VLAN_TPID_TPIDCFG \
3015 (UINT32_C(0x5) << 16)
3016 #define TX_BD_LONG_INLINE_CFA_META_VLAN_TPID_LAST \
3017 TX_BD_LONG_INLINE_CFA_META_VLAN_TPID_TPIDCFG
3018 #define TX_BD_LONG_INLINE_CFA_META_VLAN_RESERVED_MASK \
3020 #define TX_BD_LONG_INLINE_CFA_META_VLAN_RESERVED_SFT 19
3022 * This field identifies the type of edit to be performed
3025 * This value must be valid on the first BD of a packet.
3027 #define TX_BD_LONG_INLINE_CFA_META_KEY_MASK \
3028 UINT32_C(0xf0000000)
3029 #define TX_BD_LONG_INLINE_CFA_META_KEY_SFT 28
3031 #define TX_BD_LONG_INLINE_CFA_META_KEY_NONE \
3032 (UINT32_C(0x0) << 28)
3034 * - meta[17:16] - TPID select value (0 = 0x8100).
3035 * - meta[15:12] - PRI/DE value.
3036 * - meta[11:0] - VID value.
3038 #define TX_BD_LONG_INLINE_CFA_META_KEY_VLAN_TAG \
3039 (UINT32_C(0x1) << 28)
3042 * - Wh+/SR - this option is not supported.
3043 * - Thor - cfa_meta[15:0] is used for metadata output if en_bd_meta
3044 * is set in the Lookup Table.
3045 * - SR2 - {4’d0, cfa_meta[27:0]} is used for metadata output if
3046 * en_bd_meta is set in the Lookup Table.
3048 #define TX_BD_LONG_INLINE_CFA_META_KEY_METADATA_TRANSFER \
3049 (UINT32_C(0x2) << 28)
3050 #define TX_BD_LONG_INLINE_CFA_META_KEY_LAST \
3051 TX_BD_LONG_INLINE_CFA_META_KEY_METADATA_TRANSFER
3054 /* tx_bd_empty (size:128b/16B) */
3055 struct tx_bd_empty {
3056 /* This value identifies the type of buffer descriptor. */
3058 #define TX_BD_EMPTY_TYPE_MASK UINT32_C(0x3f)
3059 #define TX_BD_EMPTY_TYPE_SFT 0
3061 * Indicates that this BD is 1BB long and is an empty
3062 * TX BD. Not valid for use by the driver.
3064 #define TX_BD_EMPTY_TYPE_TX_BD_EMPTY UINT32_C(0x1)
3065 #define TX_BD_EMPTY_TYPE_LAST TX_BD_EMPTY_TYPE_TX_BD_EMPTY
3066 uint8_t unused_1[3];
3068 uint8_t unused_3[3];
3069 uint8_t unused_4[8];
3072 /* tx_bd_mp_cmd (size:128b/16B) */
3073 struct tx_bd_mp_cmd {
3074 /* Unless otherwise stated, sub-fields of this field are always valid. */
3075 uint16_t flags_type;
3076 /* This value identifies the type of buffer descriptor. */
3077 #define TX_BD_MP_CMD_TYPE_MASK UINT32_C(0x3f)
3078 #define TX_BD_MP_CMD_TYPE_SFT 0
3080 * Indicates that this BD is used to issue a command to one of
3081 * the mid-path destinations.
3083 #define TX_BD_MP_CMD_TYPE_TX_BD_MP_CMD UINT32_C(0x8)
3084 #define TX_BD_MP_CMD_TYPE_LAST TX_BD_MP_CMD_TYPE_TX_BD_MP_CMD
3085 #define TX_BD_MP_CMD_FLAGS_MASK UINT32_C(0xffc0)
3086 #define TX_BD_MP_CMD_FLAGS_SFT 6
3088 #define TX_BD_MP_CMD_FLAGS_UNUSED_MASK UINT32_C(0xc0)
3089 #define TX_BD_MP_CMD_FLAGS_UNUSED_SFT 6
3091 * This value indicates the number of 16B BD locations (slots)
3092 * consumed in the ring by this mid-path command BD, including the
3093 * BD header and the command field.
3095 #define TX_BD_MP_CMD_FLAGS_BD_CNT_MASK UINT32_C(0x1f00)
3096 #define TX_BD_MP_CMD_FLAGS_BD_CNT_SFT 8
3098 * This value defines the length of command field in bytes. The maximum
3099 * value shall be 496.
3103 * The opaque data field is pass through to the completion and can be
3104 * used for any data that the driver wants to associate with this
3105 * Tx mid-path command.
3111 /* tx_bd_presync_cmd (size:128b/16B) */
3112 struct tx_bd_presync_cmd {
3113 /* Unless otherwise stated, sub-fields of this field are always valid. */
3114 uint16_t flags_type;
3115 /* This value identifies the type of buffer descriptor. */
3116 #define TX_BD_PRESYNC_CMD_TYPE_MASK UINT32_C(0x3f)
3117 #define TX_BD_PRESYNC_CMD_TYPE_SFT 0
3119 * Indicates that this BD is used to issue a cryptographic pre-
3120 * sync command through the fast path and destined for TCE.
3122 #define TX_BD_PRESYNC_CMD_TYPE_TX_BD_PRESYNC_CMD UINT32_C(0x9)
3123 #define TX_BD_PRESYNC_CMD_TYPE_LAST \
3124 TX_BD_PRESYNC_CMD_TYPE_TX_BD_PRESYNC_CMD
3125 #define TX_BD_PRESYNC_CMD_FLAGS_MASK UINT32_C(0xffc0)
3126 #define TX_BD_PRESYNC_CMD_FLAGS_SFT 6
3128 #define TX_BD_PRESYNC_CMD_FLAGS_UNUSED_MASK UINT32_C(0xc0)
3129 #define TX_BD_PRESYNC_CMD_FLAGS_UNUSED_SFT 6
3131 * This value indicates the number of 16B BD locations (slots)
3132 * consumed in the ring by this pre-sync command BD, including the
3133 * BD header and the command field.
3135 #define TX_BD_PRESYNC_CMD_FLAGS_BD_CNT_MASK UINT32_C(0x1f00)
3136 #define TX_BD_PRESYNC_CMD_FLAGS_BD_CNT_SFT 8
3138 * This value defines the length of command field in bytes. The maximum
3139 * value shall be 496.
3143 * The opaque data field is pass through to TCE and can be used for
3148 * This field is the Crypto Context ID to which the retransmit packet is
3149 * applied. The KID references the context fields used by the
3150 * associated kTLS offloaded connection.
3154 * The KID value of all-ones is reserved for non-KTLS packets, which
3155 * only implies that this value must not be used when filling this
3156 * field for crypto packets.
3158 #define TX_BD_PRESYNC_CMD_KID_VAL_MASK UINT32_C(0xfffff)
3159 #define TX_BD_PRESYNC_CMD_KID_VAL_SFT 0
3163 /* rx_prod_pkt_bd (size:128b/16B) */
3164 struct rx_prod_pkt_bd {
3165 /* This value identifies the type of buffer descriptor. */
3166 uint16_t flags_type;
3167 /* This value identifies the type of buffer descriptor. */
3168 #define RX_PROD_PKT_BD_TYPE_MASK UINT32_C(0x3f)
3169 #define RX_PROD_PKT_BD_TYPE_SFT 0
3171 * Indicates that this BD is 16B long and is an RX Producer
3172 * (i.e. empty) buffer descriptor.
3174 #define RX_PROD_PKT_BD_TYPE_RX_PROD_PKT UINT32_C(0x4)
3175 #define RX_PROD_PKT_BD_TYPE_LAST \
3176 RX_PROD_PKT_BD_TYPE_RX_PROD_PKT
3177 #define RX_PROD_PKT_BD_FLAGS_MASK UINT32_C(0xffc0)
3178 #define RX_PROD_PKT_BD_FLAGS_SFT 6
3180 * If set to 1, the packet will be placed at the address plus
3181 * 2B. The 2 Bytes of padding will be written as zero.
3183 #define RX_PROD_PKT_BD_FLAGS_SOP_PAD UINT32_C(0x40)
3185 * If set to 1, the packet write will be padded out to the
3186 * nearest cache-line with zero value padding.
3188 #define RX_PROD_PKT_BD_FLAGS_EOP_PAD UINT32_C(0x80)
3190 * This field has been deprecated. There can be no additional
3191 * BDs for this packet from this ring.
3194 * This value is the number of additional buffers in the ring that
3195 * describe the buffer space to be consumed for this packet.
3196 * If the value is zero, then the packet must fit within the
3197 * space described by this BD. If this value is 1 or more, it
3198 * indicates how many additional "buffer" BDs are in the ring
3199 * immediately following this BD to be used for the same
3200 * network packet. Even if the packet to be placed does not need
3201 * all the additional buffers, they will be consumed anyway.
3203 #define RX_PROD_PKT_BD_FLAGS_BUFFERS_MASK UINT32_C(0x300)
3204 #define RX_PROD_PKT_BD_FLAGS_BUFFERS_SFT 8
3206 * This is the length in Bytes of the host physical buffer where
3207 * data for the packet may be placed in host memory.
3211 * The opaque data field is pass through to the completion and can be
3212 * used for any data that the driver wants to associate with this
3213 * receive buffer set.
3217 * This is the host physical address where data for the packet may
3218 * be placed in host memory.
3223 /* rx_prod_bfr_bd (size:128b/16B) */
3224 struct rx_prod_bfr_bd {
3225 /* This value identifies the type of buffer descriptor. */
3226 uint16_t flags_type;
3227 /* This value identifies the type of buffer descriptor. */
3228 #define RX_PROD_BFR_BD_TYPE_MASK UINT32_C(0x3f)
3229 #define RX_PROD_BFR_BD_TYPE_SFT 0
3231 * Indicates that this BD is 16B long and is an RX
3232 * Producer Buffer BD.
3234 #define RX_PROD_BFR_BD_TYPE_RX_PROD_BFR UINT32_C(0x5)
3235 #define RX_PROD_BFR_BD_TYPE_LAST RX_PROD_BFR_BD_TYPE_RX_PROD_BFR
3236 #define RX_PROD_BFR_BD_FLAGS_MASK UINT32_C(0xffc0)
3237 #define RX_PROD_BFR_BD_FLAGS_SFT 6
3239 * This is the length in Bytes of the host physical buffer where
3240 * data for the packet may be placed in host memory.
3243 /* This field is not used. */
3246 * This is the host physical address where data for the packet may
3247 * be placed in host memory.
3252 /* rx_prod_agg_bd (size:128b/16B) */
3253 struct rx_prod_agg_bd {
3254 /* This value identifies the type of buffer descriptor. */
3255 uint16_t flags_type;
3256 /* This value identifies the type of buffer descriptor. */
3257 #define RX_PROD_AGG_BD_TYPE_MASK UINT32_C(0x3f)
3258 #define RX_PROD_AGG_BD_TYPE_SFT 0
3260 * Indicates that this BD is 16B long and is an
3261 * RX Producer Assembly Buffer Descriptor.
3263 #define RX_PROD_AGG_BD_TYPE_RX_PROD_AGG UINT32_C(0x6)
3264 #define RX_PROD_AGG_BD_TYPE_LAST \
3265 RX_PROD_AGG_BD_TYPE_RX_PROD_AGG
3266 #define RX_PROD_AGG_BD_FLAGS_MASK UINT32_C(0xffc0)
3267 #define RX_PROD_AGG_BD_FLAGS_SFT 6
3269 * If set to 1, the packet write will be padded out to the
3270 * nearest cache-line with zero value padding.
3272 #define RX_PROD_AGG_BD_FLAGS_EOP_PAD UINT32_C(0x40)
3274 * This is the length in Bytes of the host physical buffer where
3275 * data for the packet may be placed in host memory.
3279 * The opaque data field is pass through to the completion and can be
3280 * used for any data that the driver wants to associate with this
3281 * receive assembly buffer.
3285 * This is the host physical address where data for the packet may
3286 * be placed in host memory.
3291 /* cfa_cmpls_cmp_data_msg (size:128b/16B) */
3292 struct cfa_cmpls_cmp_data_msg {
3293 uint32_t mp_client_dma_length_opcode_status_type;
3295 * This field represents the Mid-Path client that generated the
3298 #define CFA_CMPLS_CMP_DATA_MSG_TYPE_MASK UINT32_C(0x3f)
3299 #define CFA_CMPLS_CMP_DATA_MSG_TYPE_SFT 0
3300 /* Mid Path Short Completion with length = 16B. */
3301 #define CFA_CMPLS_CMP_DATA_MSG_TYPE_MID_PATH_SHORT \
3303 #define CFA_CMPLS_CMP_DATA_MSG_TYPE_LAST \
3304 CFA_CMPLS_CMP_DATA_MSG_TYPE_MID_PATH_SHORT
3305 /* This value indicates the status for the command. */
3306 #define CFA_CMPLS_CMP_DATA_MSG_STATUS_MASK UINT32_C(0x3c0)
3307 #define CFA_CMPLS_CMP_DATA_MSG_STATUS_SFT 6
3308 /* Completed without error. */
3309 #define CFA_CMPLS_CMP_DATA_MSG_STATUS_OK \
3310 (UINT32_C(0x0) << 6)
3311 /* Indicates an unsupported CFA opcode in the command. */
3312 #define CFA_CMPLS_CMP_DATA_MSG_STATUS_UNSPRT_ERR \
3313 (UINT32_C(0x1) << 6)
3315 * Indicates a CFA command formatting error. This error can occur on
3316 * any of the supported CFA commands.
3318 #define CFA_CMPLS_CMP_DATA_MSG_STATUS_FMT_ERR \
3319 (UINT32_C(0x2) << 6)
3321 * Indicates an SVIF-Table scope error. This error can occur on any
3322 * of the supported CFA commands.
3324 #define CFA_CMPLS_CMP_DATA_MSG_STATUS_SCOPE_ERR \
3325 (UINT32_C(0x3) << 6)
3327 * Indicates that the table_index is either outside of the
3328 * table_scope range set by its EM_SIZE or, for EM Insert, it is in
3329 * the static bucket range. This error can occur on EM Insert
3330 * commands. It can also occur on Read, Read Clear, Write, and
3331 * Invalidate commands if the table_type is EM.
3333 #define CFA_CMPLS_CMP_DATA_MSG_STATUS_ADDR_ERR \
3334 (UINT32_C(0x4) << 6)
3336 * Cache operation responded with an error. This error can occur on
3337 * Read, Read Clear, Write, EM Insert, and EM Delete commands.
3339 #define CFA_CMPLS_CMP_DATA_MSG_STATUS_CACHE_ERR \
3340 (UINT32_C(0x5) << 6)
3342 * Indicates failure on EM Insert or EM Delete Command. Hash index
3343 * and hash msb are returned in table_index and hash_msb fields.
3344 * Dma_length is set to 1 if the bucket is also returned (as dma
3347 #define CFA_CMPLS_CMP_DATA_MSG_STATUS_EM_FAIL \
3348 (UINT32_C(0x6) << 6)
3350 * Indicates no notifications were available on an Event Collection
3353 #define CFA_CMPLS_CMP_DATA_MSG_STATUS_EVENT_COLLECT_FAIL \
3354 (UINT32_C(0x7) << 6)
3355 #define CFA_CMPLS_CMP_DATA_MSG_STATUS_LAST \
3356 CFA_CMPLS_CMP_DATA_MSG_STATUS_EVENT_COLLECT_FAIL
3357 #define CFA_CMPLS_CMP_DATA_MSG_UNUSED0_MASK UINT32_C(0xc00)
3358 #define CFA_CMPLS_CMP_DATA_MSG_UNUSED0_SFT 10
3359 /* This is the opcode from the command. */
3360 #define CFA_CMPLS_CMP_DATA_MSG_OPCODE_MASK \
3362 #define CFA_CMPLS_CMP_DATA_MSG_OPCODE_SFT 12
3364 * This is read command. From 32 to 128B can be read from a table
3365 * using this command.
3367 #define CFA_CMPLS_CMP_DATA_MSG_OPCODE_READ \
3368 (UINT32_C(0x0) << 12)
3370 * This is write command. From 32 to 128B can be written to a table
3371 * using this command.
3373 #define CFA_CMPLS_CMP_DATA_MSG_OPCODE_WRITE \
3374 (UINT32_C(0x1) << 12)
3376 * This is read-clear command. 32B can be read from a table and a 16b
3377 * mask can be used to clear specific 16b units after the read as an
3380 #define CFA_CMPLS_CMP_DATA_MSG_OPCODE_READ_CLR \
3381 (UINT32_C(0x2) << 12)
3383 * An exact match table insert will be attempted into the table. If
3384 * there is a free location in the bucket, the payload will be
3385 * written to the bucket.
3387 #define CFA_CMPLS_CMP_DATA_MSG_OPCODE_EM_INSERT \
3388 (UINT32_C(0x3) << 12)
3389 /* An exact match table delete will be attempted. */
3390 #define CFA_CMPLS_CMP_DATA_MSG_OPCODE_EM_DELETE \
3391 (UINT32_C(0x4) << 12)
3393 * The specified table area will be invalidated. If it is needed
3394 * again, it will be read from the backing store.
3396 #define CFA_CMPLS_CMP_DATA_MSG_OPCODE_INVALIDATE \
3397 (UINT32_C(0x5) << 12)
3398 /* Reads notification messages from the Host Notification Queue. */
3399 #define CFA_CMPLS_CMP_DATA_MSG_OPCODE_EVENT_COLLECT \
3400 (UINT32_C(0x6) << 12)
3401 #define CFA_CMPLS_CMP_DATA_MSG_OPCODE_LAST \
3402 CFA_CMPLS_CMP_DATA_MSG_OPCODE_EVENT_COLLECT
3404 * This field indicates the length of the DMA that accompanies the
3405 * completion. Specified in units of DWords (32b). Valid values are
3406 * between 0 and 128. A value of zero indicates that there is no DMA
3407 * that accompanies the completion.
3409 #define CFA_CMPLS_CMP_DATA_MSG_DMA_LENGTH_MASK \
3411 #define CFA_CMPLS_CMP_DATA_MSG_DMA_LENGTH_SFT 20
3413 * This field represents the Mid-Path client that generated the
3416 #define CFA_CMPLS_CMP_DATA_MSG_MP_CLIENT_MASK \
3417 UINT32_C(0xf0000000)
3418 #define CFA_CMPLS_CMP_DATA_MSG_MP_CLIENT_SFT 28
3419 /* TX configrable flow processing block. */
3420 #define CFA_CMPLS_CMP_DATA_MSG_MP_CLIENT_TE_CFA \
3421 (UINT32_C(0x2) << 28)
3422 /* RX configrable flow processing block. */
3423 #define CFA_CMPLS_CMP_DATA_MSG_MP_CLIENT_RE_CFA \
3424 (UINT32_C(0x3) << 28)
3425 #define CFA_CMPLS_CMP_DATA_MSG_MP_CLIENT_LAST \
3426 CFA_CMPLS_CMP_DATA_MSG_MP_CLIENT_RE_CFA
3428 * This is a copy of the opaque field from the mid path BD of this
3432 uint16_t hash_msb_v;
3434 * This value is written by the NIC such that it will be different for
3435 * each pass through the completion queue. The even passes will
3436 * write 1. The odd passes will write 0.
3438 #define CFA_CMPLS_CMP_DATA_MSG_V UINT32_C(0x1)
3439 #define CFA_CMPLS_CMP_DATA_MSG_UNUSED1_MASK UINT32_C(0xe)
3440 #define CFA_CMPLS_CMP_DATA_MSG_UNUSED1_SFT 1
3442 * This is the upper 12b of the hash, returned on Exact Match
3443 * Insertion/Deletion Commands.
3445 #define CFA_CMPLS_CMP_DATA_MSG_HASH_MSB_MASK UINT32_C(0xfff0)
3446 #define CFA_CMPLS_CMP_DATA_MSG_HASH_MSB_SFT 4
3447 /* This is the table type from the command. */
3449 #define CFA_CMPLS_CMP_DATA_MSG_UNUSED2_MASK UINT32_C(0xf)
3450 #define CFA_CMPLS_CMP_DATA_MSG_UNUSED2_SFT 0
3451 #define CFA_CMPLS_CMP_DATA_MSG_TABLE_TYPE_MASK UINT32_C(0xf0)
3452 #define CFA_CMPLS_CMP_DATA_MSG_TABLE_TYPE_SFT 4
3453 /* This command acts on the action table of the specified scope. */
3454 #define CFA_CMPLS_CMP_DATA_MSG_TABLE_TYPE_ACTION (UINT32_C(0x0) << 4)
3455 /* This command acts on the exact match table of the specified scope. */
3456 #define CFA_CMPLS_CMP_DATA_MSG_TABLE_TYPE_EM (UINT32_C(0x1) << 4)
3457 #define CFA_CMPLS_CMP_DATA_MSG_TABLE_TYPE_LAST \
3458 CFA_CMPLS_CMP_DATA_MSG_TABLE_TYPE_EM
3459 uint8_t table_scope;
3460 /* This is the table scope from the command. */
3461 #define CFA_CMPLS_CMP_DATA_MSG_TABLE_SCOPE_MASK UINT32_C(0x1f)
3462 #define CFA_CMPLS_CMP_DATA_MSG_TABLE_SCOPE_SFT 0
3463 uint32_t table_index;
3465 * This is the table index from the command (if it exists). However, if
3466 * an Exact Match Insertion/Deletion command failed, then this is the
3467 * table index of the calculated static hash bucket.
3469 #define CFA_CMPLS_CMP_DATA_MSG_TABLE_INDEX_MASK UINT32_C(0x3ffffff)
3470 #define CFA_CMPLS_CMP_DATA_MSG_TABLE_INDEX_SFT 0
3473 /* CFA Mid-Path 32B DMA Message */
3474 /* cfa_dma32b_data_msg (size:256b/32B) */
3475 struct cfa_dma32b_data_msg {
3476 /* DMA data value. */
3480 /* CFA Mid-Path 64B DMA Message */
3481 /* cfa_dma64b_data_msg (size:512b/64B) */
3482 struct cfa_dma64b_data_msg {
3483 /* DMA data value. */
3487 /* CFA Mid-Path 96B DMA Message */
3488 /* cfa_dma96b_data_msg (size:768b/96B) */
3489 struct cfa_dma96b_data_msg {
3490 /* DMA data value. */
3494 /* CFA Mid-Path 128B DMA Message */
3495 /* cfa_dma128b_data_msg (size:1024b/128B) */
3496 struct cfa_dma128b_data_msg {
3497 /* DMA data value. */
3501 /* ce_cmpls_cmp_data_msg (size:128b/16B) */
3502 struct ce_cmpls_cmp_data_msg {
3503 uint16_t status_subtype_type;
3505 * This field indicates the exact type of the completion. By
3506 * convention, the LSB identifies the length of the record in 16B
3507 * units. Even values indicate 16B records. Odd values indicate 32B
3510 #define CE_CMPLS_CMP_DATA_MSG_TYPE_MASK UINT32_C(0x3f)
3511 #define CE_CMPLS_CMP_DATA_MSG_TYPE_SFT 0
3512 /* Completion of a Mid Path Command. Length = 16B */
3513 #define CE_CMPLS_CMP_DATA_MSG_TYPE_MID_PATH_SHORT UINT32_C(0x1e)
3514 #define CE_CMPLS_CMP_DATA_MSG_TYPE_LAST \
3515 CE_CMPLS_CMP_DATA_MSG_TYPE_MID_PATH_SHORT
3517 * This value indicates the CE sub-type operation that is being
3520 #define CE_CMPLS_CMP_DATA_MSG_SUBTYPE_MASK UINT32_C(0x3c0)
3521 #define CE_CMPLS_CMP_DATA_MSG_SUBTYPE_SFT 6
3522 /* Completion Response for a Solicited Command. */
3523 #define CE_CMPLS_CMP_DATA_MSG_SUBTYPE_SOLICITED (UINT32_C(0x0) << 6)
3524 /* Error Completion (Unsolicited). */
3525 #define CE_CMPLS_CMP_DATA_MSG_SUBTYPE_ERR (UINT32_C(0x1) << 6)
3526 /* Re-Sync Completion (Unsolicited) */
3527 #define CE_CMPLS_CMP_DATA_MSG_SUBTYPE_RESYNC (UINT32_C(0x2) << 6)
3528 #define CE_CMPLS_CMP_DATA_MSG_SUBTYPE_LAST \
3529 CE_CMPLS_CMP_DATA_MSG_SUBTYPE_RESYNC
3530 /* This value indicates the status for the command. */
3531 #define CE_CMPLS_CMP_DATA_MSG_STATUS_MASK UINT32_C(0x3c00)
3532 #define CE_CMPLS_CMP_DATA_MSG_STATUS_SFT 10
3533 /* Completed without error. */
3534 #define CE_CMPLS_CMP_DATA_MSG_STATUS_OK \
3535 (UINT32_C(0x0) << 10)
3536 /* CFCK load error. */
3537 #define CE_CMPLS_CMP_DATA_MSG_STATUS_CTX_LD_ERR \
3538 (UINT32_C(0x1) << 10)
3539 /* FID check error. */
3540 #define CE_CMPLS_CMP_DATA_MSG_STATUS_FID_CHK_ERR \
3541 (UINT32_C(0x2) << 10)
3542 #define CE_CMPLS_CMP_DATA_MSG_STATUS_LAST \
3543 CE_CMPLS_CMP_DATA_MSG_STATUS_FID_CHK_ERR
3546 #define CE_CMPLS_CMP_DATA_MSG_UNUSED1_MASK UINT32_C(0xf)
3547 #define CE_CMPLS_CMP_DATA_MSG_UNUSED1_SFT 0
3549 * This field represents the Mid-Path client that generated the
3552 #define CE_CMPLS_CMP_DATA_MSG_MP_CLIENTS_MASK UINT32_C(0xf0)
3553 #define CE_CMPLS_CMP_DATA_MSG_MP_CLIENTS_SFT 4
3554 /* TX crypto engine block. */
3555 #define CE_CMPLS_CMP_DATA_MSG_MP_CLIENTS_TCE (UINT32_C(0x0) << 4)
3556 /* RX crypto engine block. */
3557 #define CE_CMPLS_CMP_DATA_MSG_MP_CLIENTS_RCE (UINT32_C(0x1) << 4)
3558 #define CE_CMPLS_CMP_DATA_MSG_MP_CLIENTS_LAST \
3559 CE_CMPLS_CMP_DATA_MSG_MP_CLIENTS_RCE
3561 * This is a copy of the opaque field from the mid path BD of this
3568 * This value is written by the NIC such that it will be different
3569 * for each pass through the completion queue. The even passes will
3570 * write 1. The odd passes will write 0.
3572 #define CE_CMPLS_CMP_DATA_MSG_V UINT32_C(0x1)
3574 * This field is the Crypto Context ID. The KID is used to store
3575 * information used by the associated kTLS offloaded connection.
3577 #define CE_CMPLS_CMP_DATA_MSG_KID_MASK UINT32_C(0x1ffffe)
3578 #define CE_CMPLS_CMP_DATA_MSG_KID_SFT 1
3582 /* cmpl_base (size:128b/16B) */
3586 * This field indicates the exact type of the completion.
3587 * By convention, the LSB identifies the length of the
3588 * record in 16B units. Even values indicate 16B
3589 * records. Odd values indicate 32B
3592 #define CMPL_BASE_TYPE_MASK UINT32_C(0x3f)
3593 #define CMPL_BASE_TYPE_SFT 0
3596 * Completion of TX packet. Length = 16B
3598 #define CMPL_BASE_TYPE_TX_L2 UINT32_C(0x0)
3601 * Completion of NO-OP. Length = 16B
3603 #define CMPL_BASE_TYPE_NO_OP UINT32_C(0x1)
3605 * TX L2 coalesced completion:
3606 * Completion of coalesced TX packet. Length = 16B
3608 #define CMPL_BASE_TYPE_TX_L2_COAL UINT32_C(0x2)
3610 * TX L2 PTP completion:
3611 * Completion of PTP TX packet. Length = 32B
3613 #define CMPL_BASE_TYPE_TX_L2_PTP UINT32_C(0x3)
3615 * RX L2 TPA Start V2 Completion:
3616 * Completion of and L2 RX packet. Length = 32B
3617 * This is the new version of the RX_TPA_START completion used
3618 * in SR2 and later chips.
3620 #define CMPL_BASE_TYPE_RX_TPA_START_V2 UINT32_C(0xd)
3622 * RX L2 V2 completion:
3623 * Completion of and L2 RX packet. Length = 32B
3624 * This is the new version of the RX_L2 completion used in SR2
3627 #define CMPL_BASE_TYPE_RX_L2_V2 UINT32_C(0xf)
3630 * Completion of and L2 RX packet. Length = 32B
3632 #define CMPL_BASE_TYPE_RX_L2 UINT32_C(0x11)
3634 * RX Aggregation Buffer completion :
3635 * Completion of an L2 aggregation buffer in support of
3636 * TPA, HDS, or Jumbo packet completion. Length = 16B
3638 #define CMPL_BASE_TYPE_RX_AGG UINT32_C(0x12)
3640 * RX L2 TPA Start Completion:
3641 * Completion at the beginning of a TPA operation.
3644 #define CMPL_BASE_TYPE_RX_TPA_START UINT32_C(0x13)
3646 * RX L2 TPA End Completion:
3647 * Completion at the end of a TPA operation.
3650 #define CMPL_BASE_TYPE_RX_TPA_END UINT32_C(0x15)
3652 * Statistics Ejection Completion:
3653 * Completion of statistics data ejection buffer.
3656 #define CMPL_BASE_TYPE_STAT_EJECT UINT32_C(0x1a)
3658 * VEE Flush Completion:
3659 * This completion is inserted manually by
3660 * the Primate and processed by the VEE hardware to ensure that
3661 * all completions on a VEE function have been processed by the
3662 * VEE hardware before FLR process is completed.
3664 #define CMPL_BASE_TYPE_VEE_FLUSH UINT32_C(0x1c)
3666 * Mid Path Short Completion :
3667 * Completion of a Mid Path Command. Length = 16B
3669 #define CMPL_BASE_TYPE_MID_PATH_SHORT UINT32_C(0x1e)
3671 * Mid Path Long Completion :
3672 * Completion of a Mid Path Command. Length = 32B
3674 #define CMPL_BASE_TYPE_MID_PATH_LONG UINT32_C(0x1f)
3676 * HWRM Command Completion:
3677 * Completion of an HWRM command.
3679 #define CMPL_BASE_TYPE_HWRM_DONE UINT32_C(0x20)
3680 /* Forwarded HWRM Request */
3681 #define CMPL_BASE_TYPE_HWRM_FWD_REQ UINT32_C(0x22)
3682 /* Forwarded HWRM Response */
3683 #define CMPL_BASE_TYPE_HWRM_FWD_RESP UINT32_C(0x24)
3684 /* HWRM Asynchronous Event Information */
3685 #define CMPL_BASE_TYPE_HWRM_ASYNC_EVENT UINT32_C(0x2e)
3686 /* CQ Notification */
3687 #define CMPL_BASE_TYPE_CQ_NOTIFICATION UINT32_C(0x30)
3688 /* SRQ Threshold Event */
3689 #define CMPL_BASE_TYPE_SRQ_EVENT UINT32_C(0x32)
3690 /* DBQ Threshold Event */
3691 #define CMPL_BASE_TYPE_DBQ_EVENT UINT32_C(0x34)
3692 /* QP Async Notification */
3693 #define CMPL_BASE_TYPE_QP_EVENT UINT32_C(0x38)
3694 /* Function Async Notification */
3695 #define CMPL_BASE_TYPE_FUNC_EVENT UINT32_C(0x3a)
3696 #define CMPL_BASE_TYPE_LAST CMPL_BASE_TYPE_FUNC_EVENT
3702 * This value is written by the NIC such that it will be different
3703 * for each pass through the completion queue. The even passes
3704 * will write 1. The odd passes will write 0.
3707 #define CMPL_BASE_V UINT32_C(0x1)
3708 #define CMPL_BASE_INFO3_MASK UINT32_C(0xfffffffe)
3709 #define CMPL_BASE_INFO3_SFT 1
3714 /* tx_cmpl (size:128b/16B) */
3716 uint16_t flags_type;
3718 * This field indicates the exact type of the completion.
3719 * By convention, the LSB identifies the length of the
3720 * record in 16B units. Even values indicate 16B
3721 * records. Odd values indicate 32B
3724 #define TX_CMPL_TYPE_MASK UINT32_C(0x3f)
3725 #define TX_CMPL_TYPE_SFT 0
3728 * Completion of TX packet. Length = 16B
3730 #define TX_CMPL_TYPE_TX_L2 UINT32_C(0x0)
3731 #define TX_CMPL_TYPE_LAST TX_CMPL_TYPE_TX_L2
3732 #define TX_CMPL_FLAGS_MASK UINT32_C(0xffc0)
3733 #define TX_CMPL_FLAGS_SFT 6
3735 * When this bit is '1', it indicates a packet that has an
3736 * error of some type. Type of error is indicated in
3739 #define TX_CMPL_FLAGS_ERROR UINT32_C(0x40)
3741 * When this bit is '1', it indicates that the packet completed
3742 * was transmitted using the push acceleration data provided
3743 * by the driver. When this bit is '0', it indicates that the
3744 * packet had not push acceleration data written or was executed
3745 * as a normal packet even though push data was provided.
3747 #define TX_CMPL_FLAGS_PUSH UINT32_C(0x80)
3748 /* unused1 is 16 b */
3751 * This is a copy of the opaque field from the first TX BD of this
3752 * transmitted packet. Note that, if the packet was described by a short
3753 * CSO or short CSO inline BD, then the 16-bit opaque field from the
3754 * short CSO BD will appear in the bottom 16 bits of this field.
3759 * This value is written by the NIC such that it will be different
3760 * for each pass through the completion queue. The even passes
3761 * will write 1. The odd passes will write 0.
3763 #define TX_CMPL_V UINT32_C(0x1)
3764 #define TX_CMPL_ERRORS_MASK UINT32_C(0xfffe)
3765 #define TX_CMPL_ERRORS_SFT 1
3767 * This error indicates that there was some sort of problem
3768 * with the BDs for the packet.
3770 #define TX_CMPL_ERRORS_BUFFER_ERROR_MASK UINT32_C(0xe)
3771 #define TX_CMPL_ERRORS_BUFFER_ERROR_SFT 1
3773 #define TX_CMPL_ERRORS_BUFFER_ERROR_NO_ERROR \
3774 (UINT32_C(0x0) << 1)
3777 * BDs were not formatted correctly.
3779 #define TX_CMPL_ERRORS_BUFFER_ERROR_BAD_FMT \
3780 (UINT32_C(0x2) << 1)
3781 #define TX_CMPL_ERRORS_BUFFER_ERROR_LAST \
3782 TX_CMPL_ERRORS_BUFFER_ERROR_BAD_FMT
3784 * When this bit is '1', it indicates that the length of
3785 * the packet was zero. No packet was transmitted.
3787 #define TX_CMPL_ERRORS_ZERO_LENGTH_PKT UINT32_C(0x10)
3789 * When this bit is '1', it indicates that the packet
3790 * was longer than the programmed limit in TDI. No
3791 * packet was transmitted.
3793 #define TX_CMPL_ERRORS_EXCESSIVE_BD_LENGTH UINT32_C(0x20)
3795 * When this bit is '1', it indicates that one or more of the
3796 * BDs associated with this packet generated a PCI error.
3797 * This probably means the address was not valid.
3799 #define TX_CMPL_ERRORS_DMA_ERROR UINT32_C(0x40)
3801 * When this bit is '1', it indicates that the packet was longer
3802 * than indicated by the hint. No packet was transmitted.
3804 #define TX_CMPL_ERRORS_HINT_TOO_SHORT UINT32_C(0x80)
3806 * When this bit is '1', it indicates that the packet was
3807 * dropped due to Poison TLP error on one or more of the
3808 * TLPs in the PXP completion.
3810 #define TX_CMPL_ERRORS_POISON_TLP_ERROR UINT32_C(0x100)
3812 * When this bit is '1', it indicates that the packet was dropped
3813 * due to a transient internal error in TDC. The packet or LSO can
3814 * be retried and may transmit successfully on a subsequent attempt.
3816 #define TX_CMPL_ERRORS_INTERNAL_ERROR UINT32_C(0x200)
3818 * When this bit is '1', it was not possible to collect a a timestamp
3819 * for a PTP completion, in which case the timestamp_hi and
3820 * timestamp_lo fields are invalid. When this bit is '0' for a PTP
3821 * completion, the timestamp_hi and timestamp_lo fields are valid.
3822 * RJRN will copy the value of this bit into the field of the same
3823 * name in all TX completions, regardless of whether such completions
3824 * are PTP completions or other TX completions.
3826 #define TX_CMPL_ERRORS_TIMESTAMP_INVALID_ERROR UINT32_C(0x400)
3827 /* unused2 is 16 b */
3829 /* unused3 is 32 b */
3833 /* tx_cmpl_coal (size:128b/16B) */
3834 struct tx_cmpl_coal {
3835 uint16_t flags_type;
3837 * This field indicates the exact type of the completion.
3838 * By convention, the LSB identifies the length of the
3839 * record in 16B units. Even values indicate 16B
3840 * records. Odd values indicate 32B
3843 #define TX_CMPL_COAL_TYPE_MASK UINT32_C(0x3f)
3844 #define TX_CMPL_COAL_TYPE_SFT 0
3846 * TX L2 coalesced completion:
3847 * Completion of TX packet. Length = 16B
3849 #define TX_CMPL_COAL_TYPE_TX_L2_COAL UINT32_C(0x2)
3850 #define TX_CMPL_COAL_TYPE_LAST TX_CMPL_COAL_TYPE_TX_L2_COAL
3851 #define TX_CMPL_COAL_FLAGS_MASK UINT32_C(0xffc0)
3852 #define TX_CMPL_COAL_FLAGS_SFT 6
3854 * When this bit is '1', it indicates a packet that has an
3855 * error of some type. Type of error is indicated in
3858 #define TX_CMPL_COAL_FLAGS_ERROR UINT32_C(0x40)
3860 * When this bit is '1', it indicates that the packet completed
3861 * was transmitted using the push acceleration data provided
3862 * by the driver. When this bit is '0', it indicates that the
3863 * packet had not push acceleration data written or was executed
3864 * as a normal packet even though push data was provided.
3866 #define TX_CMPL_COAL_FLAGS_PUSH UINT32_C(0x80)
3867 /* unused1 is 16 b */
3870 * This is a copy of the opaque field from the first TX BD of the packet
3871 * which corresponds with the reported sq_cons_idx. Note that, with
3872 * coalesced completions, completions are generated for only some of the
3873 * packets. The driver will see the opaque field for only those packets.
3874 * Note that, if the packet was described by a short CSO or short CSO
3875 * inline BD, then the 16-bit opaque field from the short CSO BD will
3876 * appear in the bottom 16 bits of this field. For TX rings with
3877 * completion coalescing enabled (which would use the coalesced
3878 * completion record), it is suggested that the driver populate the
3879 * opaque field to indicate the specific TX ring with which the
3880 * completion is associated, then utilize the opaque and sq_cons_idx
3881 * fields in the coalesced completion record to determine the specific
3882 * packets that are to be completed on that ring.
3887 * This value is written by the NIC such that it will be different
3888 * for each pass through the completion queue. The even passes
3889 * will write 1. The odd passes will write 0.
3891 #define TX_CMPL_COAL_V UINT32_C(0x1)
3892 #define TX_CMPL_COAL_ERRORS_MASK \
3894 #define TX_CMPL_COAL_ERRORS_SFT 1
3896 * This error indicates that there was some sort of problem
3897 * with the BDs for the packet.
3899 #define TX_CMPL_COAL_ERRORS_BUFFER_ERROR_MASK UINT32_C(0xe)
3900 #define TX_CMPL_COAL_ERRORS_BUFFER_ERROR_SFT 1
3902 #define TX_CMPL_COAL_ERRORS_BUFFER_ERROR_NO_ERROR \
3903 (UINT32_C(0x0) << 1)
3906 * BDs were not formatted correctly.
3908 #define TX_CMPL_COAL_ERRORS_BUFFER_ERROR_BAD_FMT \
3909 (UINT32_C(0x2) << 1)
3910 #define TX_CMPL_COAL_ERRORS_BUFFER_ERROR_LAST \
3911 TX_CMPL_COAL_ERRORS_BUFFER_ERROR_BAD_FMT
3913 * When this bit is '1', it indicates that the length of
3914 * the packet was zero. No packet was transmitted.
3916 #define TX_CMPL_COAL_ERRORS_ZERO_LENGTH_PKT UINT32_C(0x10)
3918 * When this bit is '1', it indicates that the packet
3919 * was longer than the programmed limit in TDI. No
3920 * packet was transmitted.
3922 #define TX_CMPL_COAL_ERRORS_EXCESSIVE_BD_LENGTH UINT32_C(0x20)
3924 * When this bit is '1', it indicates that one or more of the
3925 * BDs associated with this packet generated a PCI error.
3926 * This probably means the address was not valid.
3928 #define TX_CMPL_COAL_ERRORS_DMA_ERROR UINT32_C(0x40)
3930 * When this bit is '1', it indicates that the packet was longer
3931 * than indicated by the hint. No packet was transmitted.
3933 #define TX_CMPL_COAL_ERRORS_HINT_TOO_SHORT UINT32_C(0x80)
3935 * When this bit is '1', it indicates that the packet was
3936 * dropped due to Poison TLP error on one or more of the
3937 * TLPs in the PXP completion.
3939 #define TX_CMPL_COAL_ERRORS_POISON_TLP_ERROR \
3942 * When this bit is '1', it indicates that the packet was dropped
3943 * due to a transient internal error in TDC. The packet or LSO can
3944 * be retried and may transmit successfully on a subsequent attempt.
3946 #define TX_CMPL_COAL_ERRORS_INTERNAL_ERROR \
3949 * When this bit is '1', it was not possible to collect a a timestamp
3950 * for a PTP completion, in which case the timestamp_hi and
3951 * timestamp_lo fields are invalid. When this bit is '0' for a PTP
3952 * completion, the timestamp_hi and timestamp_lo fields are valid.
3953 * RJRN will copy the value of this bit into the field of the same
3954 * name in all TX completions, regardless of whether such
3955 * completions are PTP completions or other TX completions.
3957 #define TX_CMPL_COAL_ERRORS_TIMESTAMP_INVALID_ERROR \
3959 /* unused2 is 16 b */
3961 uint32_t sq_cons_idx;
3963 * This value is SQ index for the start of the packet following the
3964 * last completed packet.
3966 #define TX_CMPL_COAL_SQ_CONS_IDX_MASK UINT32_C(0xffffff)
3967 #define TX_CMPL_COAL_SQ_CONS_IDX_SFT 0
3970 /* tx_cmpl_ptp (size:128b/16B) */
3971 struct tx_cmpl_ptp {
3972 uint16_t flags_type;
3974 * This field indicates the exact type of the completion.
3975 * By convention, the LSB identifies the length of the
3976 * record in 16B units. Even values indicate 16B
3977 * records. Odd values indicate 32B
3980 #define TX_CMPL_PTP_TYPE_MASK UINT32_C(0x3f)
3981 #define TX_CMPL_PTP_TYPE_SFT 0
3983 * TX L2 PTP completion:
3984 * Completion of TX packet. Length = 32B
3986 #define TX_CMPL_PTP_TYPE_TX_L2_PTP UINT32_C(0x2)
3987 #define TX_CMPL_PTP_TYPE_LAST TX_CMPL_PTP_TYPE_TX_L2_PTP
3988 #define TX_CMPL_PTP_FLAGS_MASK UINT32_C(0xffc0)
3989 #define TX_CMPL_PTP_FLAGS_SFT 6
3991 * When this bit is '1', it indicates a packet that has an
3992 * error of some type. Type of error is indicated in
3995 #define TX_CMPL_PTP_FLAGS_ERROR UINT32_C(0x40)
3997 * When this bit is '1', it indicates that the packet completed
3998 * was transmitted using the push acceleration data provided
3999 * by the driver. When this bit is '0', it indicates that the
4000 * packet had not push acceleration data written or was executed
4001 * as a normal packet even though push data was provided.
4003 #define TX_CMPL_PTP_FLAGS_PUSH UINT32_C(0x80)
4004 /* unused1 is 16 b */
4007 * This is a copy of the opaque field from the first TX BD of this
4008 * transmitted packet. Note that, if the packet was described by a short
4009 * CSO or short CSO inline BD, then the 16-bit opaque field from the
4010 * short CSO BD will appear in the bottom 16 bits of this field.
4015 * This value is written by the NIC such that it will be different
4016 * for each pass through the completion queue. The even passes
4017 * will write 1. The odd passes will write 0.
4019 #define TX_CMPL_PTP_V UINT32_C(0x1)
4020 #define TX_CMPL_PTP_ERRORS_MASK UINT32_C(0xfffe)
4021 #define TX_CMPL_PTP_ERRORS_SFT 1
4023 * This error indicates that there was some sort of problem
4024 * with the BDs for the packet.
4026 #define TX_CMPL_PTP_ERRORS_BUFFER_ERROR_MASK UINT32_C(0xe)
4027 #define TX_CMPL_PTP_ERRORS_BUFFER_ERROR_SFT 1
4029 #define TX_CMPL_PTP_ERRORS_BUFFER_ERROR_NO_ERROR \
4030 (UINT32_C(0x0) << 1)
4033 * BDs were not formatted correctly.
4035 #define TX_CMPL_PTP_ERRORS_BUFFER_ERROR_BAD_FMT \
4036 (UINT32_C(0x2) << 1)
4037 #define TX_CMPL_PTP_ERRORS_BUFFER_ERROR_LAST \
4038 TX_CMPL_PTP_ERRORS_BUFFER_ERROR_BAD_FMT
4040 * When this bit is '1', it indicates that the length of
4041 * the packet was zero. No packet was transmitted.
4043 #define TX_CMPL_PTP_ERRORS_ZERO_LENGTH_PKT UINT32_C(0x10)
4045 * When this bit is '1', it indicates that the packet
4046 * was longer than the programmed limit in TDI. No
4047 * packet was transmitted.
4049 #define TX_CMPL_PTP_ERRORS_EXCESSIVE_BD_LENGTH UINT32_C(0x20)
4051 * When this bit is '1', it indicates that one or more of the
4052 * BDs associated with this packet generated a PCI error.
4053 * This probably means the address was not valid.
4055 #define TX_CMPL_PTP_ERRORS_DMA_ERROR UINT32_C(0x40)
4057 * When this bit is '1', it indicates that the packet was longer
4058 * than indicated by the hint. No packet was transmitted.
4060 #define TX_CMPL_PTP_ERRORS_HINT_TOO_SHORT UINT32_C(0x80)
4062 * When this bit is '1', it indicates that the packet was
4063 * dropped due to Poison TLP error on one or more of the
4064 * TLPs in the PXP completion.
4066 #define TX_CMPL_PTP_ERRORS_POISON_TLP_ERROR UINT32_C(0x100)
4068 * When this bit is '1', it indicates that the packet was dropped due
4069 * to a transient internal error in TDC. The packet or LSO can be
4070 * retried and may transmit successfully on a subsequent attempt.
4072 #define TX_CMPL_PTP_ERRORS_INTERNAL_ERROR UINT32_C(0x200)
4074 * When this bit is '1', it was not possible to collect a a timestamp
4075 * for a PTP completion, in which case the timestamp_hi and
4076 * timestamp_lo fields are invalid. When this bit is '0' for a PTP
4077 * completion, the timestamp_hi and timestamp_lo fields are valid.
4078 * RJRN will copy the value of this bit into the field of the same
4079 * name in all TX completions, regardless of whether such
4080 * completions are PTP completions or other TX completions.
4082 #define TX_CMPL_PTP_ERRORS_TIMESTAMP_INVALID_ERROR UINT32_C(0x400)
4083 /* unused2 is 16 b */
4086 * This is timestamp value (lower 32bits) read from PM for the PTP
4087 * timestamp enabled packet.
4089 uint32_t timestamp_lo;
4092 /* tx_cmpl_ptp_hi (size:128b/16B) */
4093 struct tx_cmpl_ptp_hi {
4095 * This is timestamp value (lower 32bits) read from PM for the PTP
4096 * timestamp enabled packet.
4098 uint16_t timestamp_hi[3];
4099 uint16_t reserved16;
4102 * This value is written by the NIC such that it will be different for
4103 * each pass through the completion queue.The even passes will write 1.
4104 * The odd passes will write 0
4106 #define TX_CMPL_PTP_HI_V2 UINT32_C(0x1)
4109 /* rx_pkt_cmpl (size:128b/16B) */
4110 struct rx_pkt_cmpl {
4111 uint16_t flags_type;
4113 * This field indicates the exact type of the completion.
4114 * By convention, the LSB identifies the length of the
4115 * record in 16B units. Even values indicate 16B
4116 * records. Odd values indicate 32B
4119 #define RX_PKT_CMPL_TYPE_MASK UINT32_C(0x3f)
4120 #define RX_PKT_CMPL_TYPE_SFT 0
4123 * Completion of and L2 RX packet. Length = 32B
4125 #define RX_PKT_CMPL_TYPE_RX_L2 UINT32_C(0x11)
4126 #define RX_PKT_CMPL_TYPE_LAST RX_PKT_CMPL_TYPE_RX_L2
4127 #define RX_PKT_CMPL_FLAGS_MASK UINT32_C(0xffc0)
4128 #define RX_PKT_CMPL_FLAGS_SFT 6
4130 * When this bit is '1', it indicates a packet that has an
4131 * error of some type. Type of error is indicated in
4134 #define RX_PKT_CMPL_FLAGS_ERROR UINT32_C(0x40)
4135 /* This field indicates how the packet was placed in the buffer. */
4136 #define RX_PKT_CMPL_FLAGS_PLACEMENT_MASK UINT32_C(0x380)
4137 #define RX_PKT_CMPL_FLAGS_PLACEMENT_SFT 7
4140 * Packet was placed using normal algorithm.
4142 #define RX_PKT_CMPL_FLAGS_PLACEMENT_NORMAL (UINT32_C(0x0) << 7)
4145 * Packet was placed using jumbo algorithm.
4147 #define RX_PKT_CMPL_FLAGS_PLACEMENT_JUMBO (UINT32_C(0x1) << 7)
4149 * Header/Data Separation:
4150 * Packet was placed using Header/Data separation algorithm.
4151 * The separation location is indicated by the itype field.
4153 #define RX_PKT_CMPL_FLAGS_PLACEMENT_HDS (UINT32_C(0x2) << 7)
4154 #define RX_PKT_CMPL_FLAGS_PLACEMENT_LAST \
4155 RX_PKT_CMPL_FLAGS_PLACEMENT_HDS
4156 /* This bit is '1' if the RSS field in this completion is valid. */
4157 #define RX_PKT_CMPL_FLAGS_RSS_VALID UINT32_C(0x400)
4159 #define RX_PKT_CMPL_FLAGS_UNUSED UINT32_C(0x800)
4161 * This value indicates what the inner packet determined for the
4164 #define RX_PKT_CMPL_FLAGS_ITYPE_MASK UINT32_C(0xf000)
4165 #define RX_PKT_CMPL_FLAGS_ITYPE_SFT 12
4168 * Indicates that the packet type was not known.
4170 #define RX_PKT_CMPL_FLAGS_ITYPE_NOT_KNOWN \
4171 (UINT32_C(0x0) << 12)
4174 * Indicates that the packet was an IP packet, but further
4175 * classification was not possible.
4177 #define RX_PKT_CMPL_FLAGS_ITYPE_IP \
4178 (UINT32_C(0x1) << 12)
4181 * Indicates that the packet was IP and TCP.
4182 * This indicates that the payload_offset field is valid.
4184 #define RX_PKT_CMPL_FLAGS_ITYPE_TCP \
4185 (UINT32_C(0x2) << 12)
4188 * Indicates that the packet was IP and UDP.
4189 * This indicates that the payload_offset field is valid.
4191 #define RX_PKT_CMPL_FLAGS_ITYPE_UDP \
4192 (UINT32_C(0x3) << 12)
4195 * Indicates that the packet was recognized as a FCoE.
4196 * This also indicates that the payload_offset field is valid.
4198 #define RX_PKT_CMPL_FLAGS_ITYPE_FCOE \
4199 (UINT32_C(0x4) << 12)
4202 * Indicates that the packet was recognized as a RoCE.
4203 * This also indicates that the payload_offset field is valid.
4205 #define RX_PKT_CMPL_FLAGS_ITYPE_ROCE \
4206 (UINT32_C(0x5) << 12)
4209 * Indicates that the packet was recognized as ICMP.
4210 * This indicates that the payload_offset field is valid.
4212 #define RX_PKT_CMPL_FLAGS_ITYPE_ICMP \
4213 (UINT32_C(0x7) << 12)
4215 * PtP packet wo/timestamp:
4216 * Indicates that the packet was recognized as a PtP
4219 #define RX_PKT_CMPL_FLAGS_ITYPE_PTP_WO_TIMESTAMP \
4220 (UINT32_C(0x8) << 12)
4222 * PtP packet w/timestamp:
4223 * Indicates that the packet was recognized as a PtP
4224 * packet and that a timestamp was taken for the packet.
4226 #define RX_PKT_CMPL_FLAGS_ITYPE_PTP_W_TIMESTAMP \
4227 (UINT32_C(0x9) << 12)
4228 #define RX_PKT_CMPL_FLAGS_ITYPE_LAST \
4229 RX_PKT_CMPL_FLAGS_ITYPE_PTP_W_TIMESTAMP
4231 * This is the length of the data for the packet stored in the
4232 * buffer(s) identified by the opaque value. This includes
4233 * the packet BD and any associated buffer BDs. This does not include
4234 * the length of any data places in aggregation BDs.
4238 * This is a copy of the opaque field from the RX BD this completion
4242 uint8_t agg_bufs_v1;
4244 * This value is written by the NIC such that it will be different
4245 * for each pass through the completion queue. The even passes
4246 * will write 1. The odd passes will write 0.
4248 #define RX_PKT_CMPL_V1 UINT32_C(0x1)
4250 * This value is the number of aggregation buffers that follow this
4251 * entry in the completion ring that are a part of this packet.
4252 * If the value is zero, then the packet is completely contained
4253 * in the buffer space provided for the packet in the RX ring.
4255 #define RX_PKT_CMPL_AGG_BUFS_MASK UINT32_C(0x3e)
4256 #define RX_PKT_CMPL_AGG_BUFS_SFT 1
4257 /* unused1 is 2 b */
4258 #define RX_PKT_CMPL_UNUSED1_MASK UINT32_C(0xc0)
4259 #define RX_PKT_CMPL_UNUSED1_SFT 6
4261 * This is the RSS hash type for the packet. The value is packed
4262 * {tuple_extrac_op[1:0],rss_profile_id[4:0],tuple_extrac_op[2]}.
4264 * The value of tuple_extrac_op provides the information about
4265 * what fields the hash was computed on.
4266 * * 0: The RSS hash was computed over source IP address,
4267 * destination IP address, source port, and destination port of inner
4268 * IP and TCP or UDP headers. Note: For non-tunneled packets,
4269 * the packet headers are considered inner packet headers for the RSS
4270 * hash computation purpose.
4271 * * 1: The RSS hash was computed over source IP address and destination
4272 * IP address of inner IP header. Note: For non-tunneled packets,
4273 * the packet headers are considered inner packet headers for the RSS
4274 * hash computation purpose.
4275 * * 2: The RSS hash was computed over source IP address,
4276 * destination IP address, source port, and destination port of
4277 * IP and TCP or UDP headers of outer tunnel headers.
4278 * Note: For non-tunneled packets, this value is not applicable.
4279 * * 3: The RSS hash was computed over source IP address and
4280 * destination IP address of IP header of outer tunnel headers.
4281 * Note: For non-tunneled packets, this value is not applicable.
4283 * Note that 4-tuples values listed above are applicable
4284 * for layer 4 protocols supported and enabled for RSS in the hardware,
4285 * HWRM firmware, and drivers. For example, if RSS hash is supported and
4286 * enabled for TCP traffic only, then the values of tuple_extract_op
4287 * corresponding to 4-tuples are only valid for TCP traffic.
4289 uint8_t rss_hash_type;
4291 * This value indicates the offset in bytes from the beginning of the packet
4292 * where the inner payload starts. This value is valid for TCP, UDP,
4293 * FCoE, and RoCE packets.
4295 * A value of zero indicates that header is 256B into the packet.
4297 uint8_t payload_offset;
4298 /* unused2 is 8 b */
4301 * This value is the RSS hash value calculated for the packet
4302 * based on the mode bits and key value in the VNIC.
4307 /* Last 16 bytes of rx_pkt_cmpl. */
4308 /* rx_pkt_cmpl_hi (size:128b/16B) */
4309 struct rx_pkt_cmpl_hi {
4312 * This indicates that the ip checksum was calculated for the
4313 * inner packet and that the ip_cs_error field indicates if there
4316 #define RX_PKT_CMPL_FLAGS2_IP_CS_CALC UINT32_C(0x1)
4318 * This indicates that the TCP, UDP or ICMP checksum was
4319 * calculated for the inner packet and that the l4_cs_error field
4320 * indicates if there was an error.
4322 #define RX_PKT_CMPL_FLAGS2_L4_CS_CALC UINT32_C(0x2)
4324 * This indicates that the ip checksum was calculated for the
4325 * tunnel header and that the t_ip_cs_error field indicates if there
4328 #define RX_PKT_CMPL_FLAGS2_T_IP_CS_CALC UINT32_C(0x4)
4330 * This indicates that the UDP checksum was
4331 * calculated for the tunnel packet and that the t_l4_cs_error field
4332 * indicates if there was an error.
4334 #define RX_PKT_CMPL_FLAGS2_T_L4_CS_CALC UINT32_C(0x8)
4335 /* This value indicates what format the metadata field is. */
4336 #define RX_PKT_CMPL_FLAGS2_META_FORMAT_MASK UINT32_C(0xf0)
4337 #define RX_PKT_CMPL_FLAGS2_META_FORMAT_SFT 4
4338 /* No metadata information. Value is zero. */
4339 #define RX_PKT_CMPL_FLAGS2_META_FORMAT_NONE \
4340 (UINT32_C(0x0) << 4)
4342 * The metadata field contains the VLAN tag and TPID value.
4343 * - metadata[11:0] contains the vlan VID value.
4344 * - metadata[12] contains the vlan DE value.
4345 * - metadata[15:13] contains the vlan PRI value.
4346 * - metadata[31:16] contains the vlan TPID value.
4348 #define RX_PKT_CMPL_FLAGS2_META_FORMAT_VLAN \
4349 (UINT32_C(0x1) << 4)
4351 * If ext_meta_format is equal to 1, the metadata field
4352 * contains the lower 16b of the tunnel ID value, justified
4354 * - VXLAN = VNI[23:0] -> VXLAN Network ID
4355 * - Geneve (NGE) = VNI[23:0] a-> Virtual Network Identifier.
4356 * - NVGRE = TNI[23:0] -> Tenant Network ID
4357 * - GRE = KEY[31:0] -> key field with bit mask. zero if K = 0
4358 * - IPV4 = 0 (not populated)
4359 * - IPV6 = Flow Label[19:0]
4360 * - PPPoE = sessionID[15:0]
4361 * - MPLs = Outer label[19:0]
4362 * - UPAR = Selected[31:0] with bit mask
4364 #define RX_PKT_CMPL_FLAGS2_META_FORMAT_TUNNEL_ID \
4365 (UINT32_C(0x2) << 4)
4367 * if ext_meta_format is equal to 1, metadata field contains
4368 * 16b metadata from the prepended header (chdr_data).
4370 #define RX_PKT_CMPL_FLAGS2_META_FORMAT_CHDR_DATA \
4371 (UINT32_C(0x3) << 4)
4373 * If ext_meta_format is equal to 1, the metadata field contains
4374 * the outer_l3_offset, inner_l2_offset, inner_l3_offset and
4376 * - metadata[8:0] contains the outer_l3_offset.
4377 * - metadata[17:9] contains the inner_l2_offset.
4378 * - metadata[26:18] contains the inner_l3_offset.
4379 * - metadata[31:27] contains the inner_l4_size.
4381 #define RX_PKT_CMPL_FLAGS2_META_FORMAT_HDR_OFFSET \
4382 (UINT32_C(0x4) << 4)
4383 #define RX_PKT_CMPL_FLAGS2_META_FORMAT_LAST \
4384 RX_PKT_CMPL_FLAGS2_META_FORMAT_HDR_OFFSET
4386 * This field indicates the IP type for the inner-most IP header.
4387 * A value of '0' indicates IPv4. A value of '1' indicates IPv6.
4388 * This value is only valid if itype indicates a packet
4389 * with an IP header.
4391 #define RX_PKT_CMPL_FLAGS2_IP_TYPE UINT32_C(0x100)
4393 * This indicates that the complete 1's complement checksum was
4394 * calculated for the packet.
4396 #define RX_PKT_CMPL_FLAGS2_COMPLETE_CHECKSUM_CALC UINT32_C(0x200)
4398 * The combination of this value and meta_format indicated what
4399 * format the metadata field is.
4401 #define RX_PKT_CMPL_FLAGS2_EXT_META_FORMAT_MASK UINT32_C(0xc00)
4402 #define RX_PKT_CMPL_FLAGS2_EXT_META_FORMAT_SFT 10
4404 * This value is the complete 1's complement checksum calculated from
4405 * the start of the outer L3 header to the end of the packet (not
4406 * including the ethernet crc). It is valid when the
4407 * 'complete_checksum_calc' flag is set.
4409 #define RX_PKT_CMPL_FLAGS2_COMPLETE_CHECKSUM_MASK \
4410 UINT32_C(0xffff0000)
4411 #define RX_PKT_CMPL_FLAGS2_COMPLETE_CHECKSUM_SFT 16
4413 * This is data from the CFA block as indicated by the meta_format
4417 /* When meta_format=1, this value is the VLAN VID. */
4418 #define RX_PKT_CMPL_METADATA_VID_MASK UINT32_C(0xfff)
4419 #define RX_PKT_CMPL_METADATA_VID_SFT 0
4420 /* When meta_format=1, this value is the VLAN DE. */
4421 #define RX_PKT_CMPL_METADATA_DE UINT32_C(0x1000)
4422 /* When meta_format=1, this value is the VLAN PRI. */
4423 #define RX_PKT_CMPL_METADATA_PRI_MASK UINT32_C(0xe000)
4424 #define RX_PKT_CMPL_METADATA_PRI_SFT 13
4425 /* When meta_format=1, this value is the VLAN TPID. */
4426 #define RX_PKT_CMPL_METADATA_TPID_MASK UINT32_C(0xffff0000)
4427 #define RX_PKT_CMPL_METADATA_TPID_SFT 16
4430 * This value is written by the NIC such that it will be different
4431 * for each pass through the completion queue. The even passes
4432 * will write 1. The odd passes will write 0.
4434 #define RX_PKT_CMPL_V2 \
4436 #define RX_PKT_CMPL_ERRORS_MASK \
4438 #define RX_PKT_CMPL_ERRORS_SFT 1
4440 * This error indicates that there was some sort of problem with
4441 * the BDs for the packet that was found after part of the
4442 * packet was already placed. The packet should be treated as
4445 #define RX_PKT_CMPL_ERRORS_BUFFER_ERROR_MASK \
4447 #define RX_PKT_CMPL_ERRORS_BUFFER_ERROR_SFT 1
4448 /* No buffer error */
4449 #define RX_PKT_CMPL_ERRORS_BUFFER_ERROR_NO_BUFFER \
4450 (UINT32_C(0x0) << 1)
4453 * Packet did not fit into packet buffer provided.
4454 * For regular placement, this means the packet did not fit
4455 * in the buffer provided. For HDS and jumbo placement, this
4456 * means that the packet could not be placed into 7 physical
4459 #define RX_PKT_CMPL_ERRORS_BUFFER_ERROR_DID_NOT_FIT \
4460 (UINT32_C(0x1) << 1)
4463 * All BDs needed for the packet were not on-chip when
4464 * the packet arrived.
4466 #define RX_PKT_CMPL_ERRORS_BUFFER_ERROR_NOT_ON_CHIP \
4467 (UINT32_C(0x2) << 1)
4470 * BDs were not formatted correctly.
4472 #define RX_PKT_CMPL_ERRORS_BUFFER_ERROR_BAD_FORMAT \
4473 (UINT32_C(0x3) << 1)
4476 * There was a bad_format error on the previous operation
4478 #define RX_PKT_CMPL_ERRORS_BUFFER_ERROR_FLUSH \
4479 (UINT32_C(0x5) << 1)
4480 #define RX_PKT_CMPL_ERRORS_BUFFER_ERROR_LAST \
4481 RX_PKT_CMPL_ERRORS_BUFFER_ERROR_FLUSH
4483 * This indicates that there was an error in the IP header
4486 #define RX_PKT_CMPL_ERRORS_IP_CS_ERROR \
4489 * This indicates that there was an error in the TCP, UDP
4492 #define RX_PKT_CMPL_ERRORS_L4_CS_ERROR \
4495 * This indicates that there was an error in the tunnel
4496 * IP header checksum.
4498 #define RX_PKT_CMPL_ERRORS_T_IP_CS_ERROR \
4501 * This indicates that there was an error in the tunnel
4504 #define RX_PKT_CMPL_ERRORS_T_L4_CS_ERROR \
4507 * This indicates that there was a CRC error on either an FCoE
4508 * or RoCE packet. The itype indicates the packet type.
4510 #define RX_PKT_CMPL_ERRORS_CRC_ERROR \
4513 * This indicates that there was an error in the tunnel
4514 * portion of the packet when this
4515 * field is non-zero.
4517 #define RX_PKT_CMPL_ERRORS_T_PKT_ERROR_MASK \
4519 #define RX_PKT_CMPL_ERRORS_T_PKT_ERROR_SFT 9
4521 * No additional error occurred on the tunnel portion
4522 * or the packet of the packet does not have a tunnel.
4524 #define RX_PKT_CMPL_ERRORS_T_PKT_ERROR_NO_ERROR \
4525 (UINT32_C(0x0) << 9)
4527 * Indicates that IP header version does not match
4528 * expectation from L2 Ethertype for IPv4 and IPv6
4529 * in the tunnel header.
4531 #define RX_PKT_CMPL_ERRORS_T_PKT_ERROR_T_L3_BAD_VERSION \
4532 (UINT32_C(0x1) << 9)
4534 * Indicates that header length is out of range in the
4535 * tunnel header. Valid for
4538 #define RX_PKT_CMPL_ERRORS_T_PKT_ERROR_T_L3_BAD_HDR_LEN \
4539 (UINT32_C(0x2) << 9)
4541 * Indicates that the physical packet is shorter than that
4542 * claimed by the PPPoE header length for a tunnel PPPoE
4545 #define RX_PKT_CMPL_ERRORS_T_PKT_ERROR_TUNNEL_TOTAL_ERROR \
4546 (UINT32_C(0x3) << 9)
4548 * Indicates that physical packet is shorter than that claimed
4549 * by the tunnel l3 header length. Valid for IPv4, or IPv6
4550 * tunnel packet packets.
4552 #define RX_PKT_CMPL_ERRORS_T_PKT_ERROR_T_IP_TOTAL_ERROR \
4553 (UINT32_C(0x4) << 9)
4555 * Indicates that the physical packet is shorter than that
4556 * claimed by the tunnel UDP header length for a tunnel
4557 * UDP packet that is not fragmented.
4559 #define RX_PKT_CMPL_ERRORS_T_PKT_ERROR_T_UDP_TOTAL_ERROR \
4560 (UINT32_C(0x5) << 9)
4562 * indicates that the IPv4 TTL or IPv6 hop limit check
4563 * have failed (e.g. TTL = 0) in the tunnel header. Valid
4564 * for IPv4, and IPv6.
4566 #define RX_PKT_CMPL_ERRORS_T_PKT_ERROR_T_L3_BAD_TTL \
4567 (UINT32_C(0x6) << 9)
4568 #define RX_PKT_CMPL_ERRORS_T_PKT_ERROR_LAST \
4569 RX_PKT_CMPL_ERRORS_T_PKT_ERROR_T_L3_BAD_TTL
4571 * This indicates that there was an error in the inner
4572 * portion of the packet when this
4573 * field is non-zero.
4575 #define RX_PKT_CMPL_ERRORS_PKT_ERROR_MASK \
4577 #define RX_PKT_CMPL_ERRORS_PKT_ERROR_SFT 12
4579 * No additional error occurred on the tunnel portion
4580 * or the packet of the packet does not have a tunnel.
4582 #define RX_PKT_CMPL_ERRORS_PKT_ERROR_NO_ERROR \
4583 (UINT32_C(0x0) << 12)
4585 * Indicates that IP header version does not match
4586 * expectation from L2 Ethertype for IPv4 and IPv6 or that
4587 * option other than VFT was parsed on
4590 #define RX_PKT_CMPL_ERRORS_PKT_ERROR_L3_BAD_VERSION \
4591 (UINT32_C(0x1) << 12)
4593 * indicates that header length is out of range. Valid for
4596 #define RX_PKT_CMPL_ERRORS_PKT_ERROR_L3_BAD_HDR_LEN \
4597 (UINT32_C(0x2) << 12)
4599 * indicates that the IPv4 TTL or IPv6 hop limit check
4600 * have failed (e.g. TTL = 0). Valid for IPv4, and IPv6
4602 #define RX_PKT_CMPL_ERRORS_PKT_ERROR_L3_BAD_TTL \
4603 (UINT32_C(0x3) << 12)
4605 * Indicates that physical packet is shorter than that
4606 * claimed by the l3 header length. Valid for IPv4,
4607 * IPv6 packet or RoCE packets.
4609 #define RX_PKT_CMPL_ERRORS_PKT_ERROR_IP_TOTAL_ERROR \
4610 (UINT32_C(0x4) << 12)
4612 * Indicates that the physical packet is shorter than that
4613 * claimed by the UDP header length for a UDP packet that is
4616 #define RX_PKT_CMPL_ERRORS_PKT_ERROR_UDP_TOTAL_ERROR \
4617 (UINT32_C(0x5) << 12)
4619 * Indicates that TCP header length > IP payload. Valid for
4622 #define RX_PKT_CMPL_ERRORS_PKT_ERROR_L4_BAD_HDR_LEN \
4623 (UINT32_C(0x6) << 12)
4624 /* Indicates that TCP header length < 5. Valid for TCP. */
4625 #define RX_PKT_CMPL_ERRORS_PKT_ERROR_L4_BAD_HDR_LEN_TOO_SMALL \
4626 (UINT32_C(0x7) << 12)
4628 * Indicates that TCP option headers result in a TCP header
4629 * size that does not match data offset in TCP header. Valid
4632 #define RX_PKT_CMPL_ERRORS_PKT_ERROR_L4_BAD_OPT_LEN \
4633 (UINT32_C(0x8) << 12)
4634 #define RX_PKT_CMPL_ERRORS_PKT_ERROR_LAST \
4635 RX_PKT_CMPL_ERRORS_PKT_ERROR_L4_BAD_OPT_LEN
4637 * This field identifies the CFA action rule that was used for this
4643 * This value holds the reordering sequence number for the packet.
4644 * If the reordering sequence is not valid, then this value is zero.
4645 * The reordering domain for the packet is in the bottom 8 to 10b of
4646 * the rss_hash value. The bottom 20b of this value contain the
4647 * ordering domain value for the packet.
4649 #define RX_PKT_CMPL_REORDER_MASK UINT32_C(0xffffff)
4650 #define RX_PKT_CMPL_REORDER_SFT 0
4653 /* rx_pkt_v2_cmpl (size:128b/16B) */
4654 struct rx_pkt_v2_cmpl {
4655 uint16_t flags_type;
4657 * This field indicates the exact type of the completion.
4658 * By convention, the LSB identifies the length of the
4659 * record in 16B units. Even values indicate 16B
4660 * records. Odd values indicate 32B
4663 #define RX_PKT_V2_CMPL_TYPE_MASK UINT32_C(0x3f)
4664 #define RX_PKT_V2_CMPL_TYPE_SFT 0
4666 * RX L2 V2 completion:
4667 * Completion of and L2 RX packet. Length = 32B
4668 * This is the new version of the RX_L2 completion used in SR2
4671 #define RX_PKT_V2_CMPL_TYPE_RX_L2_V2 UINT32_C(0xf)
4672 #define RX_PKT_V2_CMPL_TYPE_LAST \
4673 RX_PKT_V2_CMPL_TYPE_RX_L2_V2
4674 #define RX_PKT_V2_CMPL_FLAGS_MASK UINT32_C(0xffc0)
4675 #define RX_PKT_V2_CMPL_FLAGS_SFT 6
4677 * When this bit is '1', it indicates a packet that has an
4678 * error of some type. Type of error is indicated in
4681 #define RX_PKT_V2_CMPL_FLAGS_ERROR UINT32_C(0x40)
4682 /* This field indicates how the packet was placed in the buffer. */
4683 #define RX_PKT_V2_CMPL_FLAGS_PLACEMENT_MASK UINT32_C(0x380)
4684 #define RX_PKT_V2_CMPL_FLAGS_PLACEMENT_SFT 7
4687 * Packet was placed using normal algorithm.
4689 #define RX_PKT_V2_CMPL_FLAGS_PLACEMENT_NORMAL \
4690 (UINT32_C(0x0) << 7)
4693 * Packet was placed using jumbo algorithm.
4695 #define RX_PKT_V2_CMPL_FLAGS_PLACEMENT_JUMBO \
4696 (UINT32_C(0x1) << 7)
4698 * Header/Data Separation:
4699 * Packet was placed using Header/Data separation algorithm.
4700 * The separation location is indicated by the itype field.
4702 #define RX_PKT_V2_CMPL_FLAGS_PLACEMENT_HDS \
4703 (UINT32_C(0x2) << 7)
4706 * Packet was placed using truncation algorithm. The
4707 * placed (truncated) length is indicated in the payload_offset
4708 * field. The original length is indicated in the len field.
4710 #define RX_PKT_V2_CMPL_FLAGS_PLACEMENT_TRUNCATION \
4711 (UINT32_C(0x3) << 7)
4712 #define RX_PKT_V2_CMPL_FLAGS_PLACEMENT_LAST \
4713 RX_PKT_V2_CMPL_FLAGS_PLACEMENT_TRUNCATION
4714 /* This bit is '1' if the RSS field in this completion is valid. */
4715 #define RX_PKT_V2_CMPL_FLAGS_RSS_VALID UINT32_C(0x400)
4717 * This bit is '1' if metadata has been added to the end of the
4718 * packet in host memory. Metadata starts at the first 32B boundary
4719 * after the end of the packet for regular and jumbo placement.
4720 * It starts at the first 32B boundary after the end of the header
4721 * for HDS placement. The length of the metadata is indicated in the
4724 #define RX_PKT_V2_CMPL_FLAGS_PKT_METADATA_PRESENT UINT32_C(0x800)
4726 * This value indicates what the inner packet determined for the
4729 #define RX_PKT_V2_CMPL_FLAGS_ITYPE_MASK UINT32_C(0xf000)
4730 #define RX_PKT_V2_CMPL_FLAGS_ITYPE_SFT 12
4733 * Indicates that the packet type was not known.
4735 #define RX_PKT_V2_CMPL_FLAGS_ITYPE_NOT_KNOWN \
4736 (UINT32_C(0x0) << 12)
4739 * Indicates that the packet was an IP packet, but further
4740 * classification was not possible.
4742 #define RX_PKT_V2_CMPL_FLAGS_ITYPE_IP \
4743 (UINT32_C(0x1) << 12)
4746 * Indicates that the packet was IP and TCP.
4747 * This indicates that the payload_offset field is valid.
4749 #define RX_PKT_V2_CMPL_FLAGS_ITYPE_TCP \
4750 (UINT32_C(0x2) << 12)
4753 * Indicates that the packet was IP and UDP.
4754 * This indicates that the payload_offset field is valid.
4756 #define RX_PKT_V2_CMPL_FLAGS_ITYPE_UDP \
4757 (UINT32_C(0x3) << 12)
4760 * Indicates that the packet was recognized as a FCoE.
4761 * This also indicates that the payload_offset field is valid.
4763 #define RX_PKT_V2_CMPL_FLAGS_ITYPE_FCOE \
4764 (UINT32_C(0x4) << 12)
4767 * Indicates that the packet was recognized as a RoCE.
4768 * This also indicates that the payload_offset field is valid.
4770 #define RX_PKT_V2_CMPL_FLAGS_ITYPE_ROCE \
4771 (UINT32_C(0x5) << 12)
4774 * Indicates that the packet was recognized as ICMP.
4775 * This indicates that the payload_offset field is valid.
4777 #define RX_PKT_V2_CMPL_FLAGS_ITYPE_ICMP \
4778 (UINT32_C(0x7) << 12)
4780 * PtP packet wo/timestamp:
4781 * Indicates that the packet was recognized as a PtP
4784 #define RX_PKT_V2_CMPL_FLAGS_ITYPE_PTP_WO_TIMESTAMP \
4785 (UINT32_C(0x8) << 12)
4787 * PtP packet w/timestamp:
4788 * Indicates that the packet was recognized as a PtP
4789 * packet and that a timestamp was taken for the packet.
4791 #define RX_PKT_V2_CMPL_FLAGS_ITYPE_PTP_W_TIMESTAMP \
4792 (UINT32_C(0x9) << 12)
4793 #define RX_PKT_V2_CMPL_FLAGS_ITYPE_LAST \
4794 RX_PKT_V2_CMPL_FLAGS_ITYPE_PTP_W_TIMESTAMP
4796 * This is the length of the data for the packet stored in the
4797 * buffer(s) identified by the opaque value. This includes
4798 * the packet BD and any associated buffer BDs. This does not include
4799 * the length of any data places in aggregation BDs.
4803 * This is a copy of the opaque field from the RX BD this completion
4807 uint8_t agg_bufs_v1;
4809 * This value is written by the NIC such that it will be different
4810 * for each pass through the completion queue. The even passes
4811 * will write 1. The odd passes will write 0.
4813 #define RX_PKT_V2_CMPL_V1 UINT32_C(0x1)
4815 * This value is the number of aggregation buffers that follow this
4816 * entry in the completion ring that are a part of this packet.
4817 * If the value is zero, then the packet is completely contained
4818 * in the buffer space provided for the packet in the RX ring.
4820 #define RX_PKT_V2_CMPL_AGG_BUFS_MASK UINT32_C(0x3e)
4821 #define RX_PKT_V2_CMPL_AGG_BUFS_SFT 1
4822 /* unused1 is 2 b */
4823 #define RX_PKT_V2_CMPL_UNUSED1_MASK UINT32_C(0xc0)
4824 #define RX_PKT_V2_CMPL_UNUSED1_SFT 6
4826 * This is the RSS hash type for the packet. The value is packed
4827 * {tuple_extrac_op[1:0],rss_profile_id[4:0],tuple_extrac_op[2]}.
4829 * The value of tuple_extrac_op provides the information about
4830 * what fields the hash was computed on.
4831 * * 0: The RSS hash was computed over source IP address,
4832 * destination IP address, source port, and destination port of inner
4833 * IP and TCP or UDP headers. Note: For non-tunneled packets,
4834 * the packet headers are considered inner packet headers for the RSS
4835 * hash computation purpose.
4836 * * 1: The RSS hash was computed over source IP address and destination
4837 * IP address of inner IP header. Note: For non-tunneled packets,
4838 * the packet headers are considered inner packet headers for the RSS
4839 * hash computation purpose.
4840 * * 2: The RSS hash was computed over source IP address,
4841 * destination IP address, source port, and destination port of
4842 * IP and TCP or UDP headers of outer tunnel headers.
4843 * Note: For non-tunneled packets, this value is not applicable.
4844 * * 3: The RSS hash was computed over source IP address and
4845 * destination IP address of IP header of outer tunnel headers.
4846 * Note: For non-tunneled packets, this value is not applicable.
4848 * Note that 4-tuples values listed above are applicable
4849 * for layer 4 protocols supported and enabled for RSS in the hardware,
4850 * HWRM firmware, and drivers. For example, if RSS hash is supported and
4851 * enabled for TCP traffic only, then the values of tuple_extract_op
4852 * corresponding to 4-tuples are only valid for TCP traffic.
4854 uint8_t rss_hash_type;
4855 uint16_t metadata1_payload_offset;
4857 * This is data from the CFA as indicated by the meta_format field.
4858 * If truncation placement is not used, this value indicates the offset
4859 * in bytes from the beginning of the packet where the inner payload
4860 * starts. This value is valid for TCP, UDP, FCoE, and RoCE packets. If
4861 * truncation placement is used, this value represents the placed
4862 * (truncated) length of the packet.
4864 #define RX_PKT_V2_CMPL_PAYLOAD_OFFSET_MASK UINT32_C(0x1ff)
4865 #define RX_PKT_V2_CMPL_PAYLOAD_OFFSET_SFT 0
4866 /* This is data from the CFA as indicated by the meta_format field. */
4867 #define RX_PKT_V2_CMPL_METADATA1_MASK UINT32_C(0xf000)
4868 #define RX_PKT_V2_CMPL_METADATA1_SFT 12
4869 /* When meta_format != 0, this value is the VLAN TPID_SEL. */
4870 #define RX_PKT_V2_CMPL_METADATA1_TPID_SEL_MASK UINT32_C(0x7000)
4871 #define RX_PKT_V2_CMPL_METADATA1_TPID_SEL_SFT 12
4873 #define RX_PKT_V2_CMPL_METADATA1_TPID_SEL_TPID88A8 \
4874 (UINT32_C(0x0) << 12)
4876 #define RX_PKT_V2_CMPL_METADATA1_TPID_SEL_TPID8100 \
4877 (UINT32_C(0x1) << 12)
4879 #define RX_PKT_V2_CMPL_METADATA1_TPID_SEL_TPID9100 \
4880 (UINT32_C(0x2) << 12)
4882 #define RX_PKT_V2_CMPL_METADATA1_TPID_SEL_TPID9200 \
4883 (UINT32_C(0x3) << 12)
4885 #define RX_PKT_V2_CMPL_METADATA1_TPID_SEL_TPID9300 \
4886 (UINT32_C(0x4) << 12)
4887 /* Value programmed in CFA VLANTPID register. */
4888 #define RX_PKT_V2_CMPL_METADATA1_TPID_SEL_TPIDCFG \
4889 (UINT32_C(0x5) << 12)
4890 #define RX_PKT_V2_CMPL_METADATA1_TPID_SEL_LAST \
4891 RX_PKT_V2_CMPL_METADATA1_TPID_SEL_TPIDCFG
4892 /* When meta_format != 0, this value is the VLAN valid. */
4893 #define RX_PKT_V2_CMPL_METADATA1_VALID UINT32_C(0x8000)
4895 * This value is the RSS hash value calculated for the packet
4896 * based on the mode bits and key value in the VNIC. When vee_cmpl_mode
4897 * is set in VNIC context, this is the lower 32b of the host address
4898 * from the first BD used to place the packet.
4903 /* Last 16 bytes of RX Packet V2 Completion Record */
4904 /* rx_pkt_v2_cmpl_hi (size:128b/16B) */
4905 struct rx_pkt_v2_cmpl_hi {
4908 * When this bit is '0', the cs_ok field has the following definition:-
4909 * ip_cs_ok[2:0] = The number of header groups with a valid IP checksum
4910 * in the delivered packet, counted from the outer-most header group to
4911 * the inner-most header group, stopping at the first error. -
4912 * l4_cs_ok[5:3] = The number of header groups with a valid L4 checksum
4913 * in the delivered packet, counted from the outer-most header group to
4914 * the inner-most header group, stopping at the first error. When this
4915 * bit is '1', the cs_ok field has the following definition: -
4916 * hdr_cnt[2:0] = The number of header groups that were parsed by the
4917 * chip and passed in the delivered packet. - ip_cs_all_ok[3] =This bit
4918 * will be '1' if all the parsed header groups with an IP checksum are
4919 * valid. - l4_cs_all_ok[4] = This bit will be '1' if all the parsed
4920 * header groups with an L4 checksum are valid.
4922 #define RX_PKT_V2_CMPL_HI_FLAGS2_CS_ALL_OK_MODE \
4924 /* This value indicates what format the metadata field is. */
4925 #define RX_PKT_V2_CMPL_HI_FLAGS2_META_FORMAT_MASK \
4927 #define RX_PKT_V2_CMPL_HI_FLAGS2_META_FORMAT_SFT 4
4928 /* There is no metadata information. Values are zero. */
4929 #define RX_PKT_V2_CMPL_HI_FLAGS2_META_FORMAT_NONE \
4930 (UINT32_C(0x0) << 4)
4932 * The {metadata1, metadata0} fields contain the vtag
4933 * information: - vtag[19:0] = {valid, tpid_sel[2:0], pri[2:0],
4934 * de, vid[11:0]} The metadata2 field contains the table scope
4935 * and action record pointer. - metadata2[25:0] contains the
4936 * action record pointer. - metadata2[31:26] contains the table
4939 #define RX_PKT_V2_CMPL_HI_FLAGS2_META_FORMAT_ACT_REC_PTR \
4940 (UINT32_C(0x1) << 4)
4942 * The {metadata1, metadata0} fields contain the vtag
4944 * - vtag[19:0] = {valid, tpid_sel[2:0], pri[2:0], de, vid[11:0]}
4945 * The metadata2 field contains the Tunnel ID
4946 * value, justified to LSB. i
4947 * - VXLAN = VNI[23:0] -> VXLAN Network ID
4948 * - Geneve (NGE) = VNI[23:0] a-> Virtual Network Identifier
4949 * - NVGRE = TNI[23:0] -> Tenant Network ID
4950 * - GRE = KEY[31:0] -> key field with bit mask. zero if K=0
4951 * - IPv4 = 0 (not populated)
4952 * - IPv6 = Flow Label[19:0]
4953 * - PPPoE = sessionID[15:0]
4954 * - MPLs = Outer label[19:0]
4955 * - UPAR = Selected[31:0] with bit mask
4957 #define RX_PKT_V2_CMPL_HI_FLAGS2_META_FORMAT_TUNNEL_ID \
4958 (UINT32_C(0x2) << 4)
4960 * The {metadata1, metadata0} fields contain the vtag
4962 * - vtag[19:0] = {valid, tpid_sel[2:0], pri[2:0],de, vid[11:0]}
4963 * The metadata2 field contains the 32b metadata from the prepended
4964 * header (chdr_data).
4966 #define RX_PKT_V2_CMPL_HI_FLAGS2_META_FORMAT_CHDR_DATA \
4967 (UINT32_C(0x3) << 4)
4969 * The {metadata1, metadata0} fields contain the vtag
4971 * - vtag[19:0] = {valid, tpid_sel[2:0], pri[2:0], de, vid[11:0]}
4972 * The metadata2 field contains the outer_l3_offset,
4973 * inner_l2_offset, inner_l3_offset, and inner_l4_size.
4974 * - metadata2[8:0] contains the outer_l3_offset.
4975 * - metadata2[17:9] contains the inner_l2_offset.
4976 * - metadata2[26:18] contains the inner_l3_offset.
4977 * - metadata2[31:27] contains the inner_l4_size.
4979 #define RX_PKT_V2_CMPL_HI_FLAGS2_META_FORMAT_HDR_OFFSET \
4980 (UINT32_C(0x4) << 4)
4981 #define RX_PKT_V2_CMPL_HI_FLAGS2_META_FORMAT_LAST \
4982 RX_PKT_V2_CMPL_HI_FLAGS2_META_FORMAT_HDR_OFFSET
4984 * This field indicates the IP type for the inner-most IP header.
4985 * A value of '0' indicates IPv4. A value of '1' indicates IPv6.
4986 * This value is only valid if itype indicates a packet
4987 * with an IP header.
4989 #define RX_PKT_V2_CMPL_HI_FLAGS2_IP_TYPE \
4992 * This indicates that the complete 1's complement checksum was
4993 * calculated for the packet.
4995 #define RX_PKT_V2_CMPL_HI_FLAGS2_COMPLETE_CHECKSUM_CALC \
4998 * This field indicates the status of IP and L4 CS calculations done
4999 * by the chip. The format of this field is indicated by the
5000 * cs_all_ok_mode bit.
5002 #define RX_PKT_V2_CMPL_HI_FLAGS2_CS_OK_MASK \
5004 #define RX_PKT_V2_CMPL_HI_FLAGS2_CS_OK_SFT 10
5006 * This value is the complete 1's complement checksum calculated from
5007 * the start of the outer L3 header to the end of the packet (not
5008 * including the ethernet crc). It is valid when the
5009 * 'complete_checksum_calc' flag is set.
5011 #define RX_PKT_V2_CMPL_HI_FLAGS2_COMPLETE_CHECKSUM_MASK \
5012 UINT32_C(0xffff0000)
5013 #define RX_PKT_V2_CMPL_HI_FLAGS2_COMPLETE_CHECKSUM_SFT 16
5015 * This is data from the CFA block as indicated by the meta_format
5017 * - meta_format 0 - none - metadata2 = 0 - not valid/not stripped
5018 * - meta_format 1 - act_rec_ptr - metadata2 = {table_scope[5:0],
5019 * act_rec_ptr[25:0]}
5020 * - meta_format 2 - tunnel_id - metadata2 = tunnel_id[31:0]
5021 * - meta_format 3 - chdr_data - metadata2 = updated_chdr_data[31:0]
5022 * - meta_format 4 - hdr_offsets - metadata2 = hdr_offsets[31:0]
5023 * When vee_cmpl_mode is set in VNIC context, this is the upper 32b
5024 * of the host address from the first BD used to place the packet.
5029 * This value is written by the NIC such that it will be different
5030 * for each pass through the completion queue. The even passes
5031 * will write 1. The odd passes will write 0.
5033 #define RX_PKT_V2_CMPL_HI_V2 \
5035 #define RX_PKT_V2_CMPL_HI_ERRORS_MASK \
5037 #define RX_PKT_V2_CMPL_HI_ERRORS_SFT 1
5039 * This error indicates that there was some sort of problem with
5040 * the BDs for the packet that was found after part of the
5041 * packet was already placed. The packet should be treated as
5044 #define RX_PKT_V2_CMPL_HI_ERRORS_BUFFER_ERROR_MASK \
5046 #define RX_PKT_V2_CMPL_HI_ERRORS_BUFFER_ERROR_SFT 1
5047 /* No buffer error */
5048 #define RX_PKT_V2_CMPL_HI_ERRORS_BUFFER_ERROR_NO_BUFFER \
5049 (UINT32_C(0x0) << 1)
5051 * Did Not Fit: Packet did not fit into packet buffer provided.
5052 * For regular placement, this means the packet did not fit in
5053 * the buffer provided. For HDS and jumbo placement, this means
5054 * that the packet could not be placed into 8 physical buffers
5055 * (if fixed-size buffers are used), or that the packet could
5056 * not be placed in the number of physical buffers configured
5057 * for the VNIC (if variable-size buffers are used)
5059 #define RX_PKT_V2_CMPL_HI_ERRORS_BUFFER_ERROR_DID_NOT_FIT \
5060 (UINT32_C(0x1) << 1)
5062 * Not On Chip: All BDs needed for the packet were not on-chip
5063 * when the packet arrived. For regular placement, this error is
5064 * not valid. For HDS and jumbo placement, this means that not
5065 * enough agg BDs were posted to place the packet.
5067 #define RX_PKT_V2_CMPL_HI_ERRORS_BUFFER_ERROR_NOT_ON_CHIP \
5068 (UINT32_C(0x2) << 1)
5071 * BDs were not formatted correctly.
5073 #define RX_PKT_V2_CMPL_HI_ERRORS_BUFFER_ERROR_BAD_FORMAT \
5074 (UINT32_C(0x3) << 1)
5077 * There was a bad_format error on the previous operation
5079 #define RX_PKT_V2_CMPL_HI_ERRORS_BUFFER_ERROR_FLUSH \
5080 (UINT32_C(0x5) << 1)
5081 #define RX_PKT_V2_CMPL_HI_ERRORS_BUFFER_ERROR_LAST \
5082 RX_PKT_V2_CMPL_HI_ERRORS_BUFFER_ERROR_FLUSH
5084 * This indicates that there was an error in the outer tunnel
5085 * portion of the packet when this field is non-zero.
5087 #define RX_PKT_V2_CMPL_HI_ERRORS_OT_PKT_ERROR_MASK \
5089 #define RX_PKT_V2_CMPL_HI_ERRORS_OT_PKT_ERROR_SFT 4
5091 * No additional error occurred on the outer tunnel portion
5092 * of the packet or the packet does not have a outer tunnel.
5094 #define RX_PKT_V2_CMPL_HI_ERRORS_OT_PKT_ERROR_NO_ERROR \
5095 (UINT32_C(0x0) << 4)
5097 * Indicates that IP header version does not match expectation
5098 * from L2 Ethertype for IPv4 and IPv6 in the outer tunnel header.
5100 #define RX_PKT_V2_CMPL_HI_ERRORS_OT_PKT_ERROR_OT_L3_BAD_VERSION \
5101 (UINT32_C(0x1) << 4)
5103 * Indicates that header length is out of range in the outer
5104 * tunnel header. Valid for IPv4.
5106 #define RX_PKT_V2_CMPL_HI_ERRORS_OT_PKT_ERROR_OT_L3_BAD_HDR_LEN \
5107 (UINT32_C(0x2) << 4)
5109 * Indicates that physical packet is shorter than that claimed
5110 * by the outer tunnel l3 header length. Valid for IPv4, or
5111 * IPv6 outer tunnel packets.
5113 #define RX_PKT_V2_CMPL_HI_ERRORS_OT_PKT_ERROR_OT_IP_TOTAL_ERROR \
5114 (UINT32_C(0x3) << 4)
5116 * Indicates that the physical packet is shorter than that
5117 * claimed by the outer tunnel UDP header length for a outer
5118 * tunnel UDP packet that is not fragmented.
5120 #define RX_PKT_V2_CMPL_HI_ERRORS_OT_PKT_ERROR_OT_UDP_TOTAL_ERROR \
5121 (UINT32_C(0x4) << 4)
5123 * Indicates that the IPv4 TTL or IPv6 hop limit check have
5124 * failed (e.g. TTL = 0) in the outer tunnel header. Valid for
5127 #define RX_PKT_V2_CMPL_HI_ERRORS_OT_PKT_ERROR_OT_L3_BAD_TTL \
5128 (UINT32_C(0x5) << 4)
5130 * Indicates that the IP checksum failed its check in the outer
5133 #define RX_PKT_V2_CMPL_HI_ERRORS_OT_PKT_ERROR_OT_IP_CS_ERROR \
5134 (UINT32_C(0x6) << 4)
5136 * Indicates that the L4 checksum failed its check in the outer
5139 #define RX_PKT_V2_CMPL_HI_ERRORS_OT_PKT_ERROR_OT_L4_CS_ERROR \
5140 (UINT32_C(0x7) << 4)
5141 #define RX_PKT_V2_CMPL_HI_ERRORS_OT_PKT_ERROR_LAST \
5142 RX_PKT_V2_CMPL_HI_ERRORS_OT_PKT_ERROR_OT_L4_CS_ERROR
5144 * This indicates that there was a CRC error on either an FCoE
5145 * or RoCE packet. The itype indicates the packet type.
5147 #define RX_PKT_V2_CMPL_HI_ERRORS_CRC_ERROR \
5150 * This indicates that there was an error in the tunnel portion
5151 * of the packet when this field is non-zero.
5153 #define RX_PKT_V2_CMPL_HI_ERRORS_T_PKT_ERROR_MASK \
5155 #define RX_PKT_V2_CMPL_HI_ERRORS_T_PKT_ERROR_SFT 9
5157 * No additional error occurred on the tunnel portion
5158 * of the packet or the packet does not have a tunnel.
5160 #define RX_PKT_V2_CMPL_HI_ERRORS_T_PKT_ERROR_NO_ERROR \
5161 (UINT32_C(0x0) << 9)
5163 * Indicates that IP header version does not match expectation
5164 * from L2 Ethertype for IPv4 and IPv6 in the tunnel header.
5166 #define RX_PKT_V2_CMPL_HI_ERRORS_T_PKT_ERROR_T_L3_BAD_VERSION \
5167 (UINT32_C(0x1) << 9)
5169 * Indicates that header length is out of range in the tunnel
5170 * header. Valid for IPv4.
5172 #define RX_PKT_V2_CMPL_HI_ERRORS_T_PKT_ERROR_T_L3_BAD_HDR_LEN \
5173 (UINT32_C(0x2) << 9)
5175 * Indicates that physical packet is shorter than that claimed
5176 * by the tunnel l3 header length. Valid for IPv4, or IPv6 tunnel
5179 #define RX_PKT_V2_CMPL_HI_ERRORS_T_PKT_ERROR_T_IP_TOTAL_ERROR \
5180 (UINT32_C(0x3) << 9)
5182 * Indicates that the physical packet is shorter than that claimed
5183 * by the tunnel UDP header length for a tunnel UDP packet that is
5186 #define RX_PKT_V2_CMPL_HI_ERRORS_T_PKT_ERROR_T_UDP_TOTAL_ERROR \
5187 (UINT32_C(0x4) << 9)
5189 * Indicates that the IPv4 TTL or IPv6 hop limit check have failed
5190 * (e.g. TTL = 0) in the tunnel header. Valid for IPv4, and IPv6.
5192 #define RX_PKT_V2_CMPL_HI_ERRORS_T_PKT_ERROR_T_L3_BAD_TTL \
5193 (UINT32_C(0x5) << 9)
5195 * Indicates that the IP checksum failed its check in the tunnel
5198 #define RX_PKT_V2_CMPL_HI_ERRORS_T_PKT_ERROR_T_IP_CS_ERROR \
5199 (UINT32_C(0x6) << 9)
5201 * Indicates that the L4 checksum failed its check in the tunnel
5204 #define RX_PKT_V2_CMPL_HI_ERRORS_T_PKT_ERROR_T_L4_CS_ERROR \
5205 (UINT32_C(0x7) << 9)
5206 #define RX_PKT_V2_CMPL_HI_ERRORS_T_PKT_ERROR_LAST \
5207 RX_PKT_V2_CMPL_HI_ERRORS_T_PKT_ERROR_T_L4_CS_ERROR
5209 * This indicates that there was an error in the inner
5210 * portion of the packet when this
5211 * field is non-zero.
5213 #define RX_PKT_V2_CMPL_HI_ERRORS_PKT_ERROR_MASK \
5215 #define RX_PKT_V2_CMPL_HI_ERRORS_PKT_ERROR_SFT 12
5217 * No additional error occurred on the tunnel portion
5218 * or the packet of the packet does not have a tunnel.
5220 #define RX_PKT_V2_CMPL_HI_ERRORS_PKT_ERROR_NO_ERROR \
5221 (UINT32_C(0x0) << 12)
5223 * Indicates that IP header version does not match
5224 * expectation from L2 Ethertype for IPv4 and IPv6 or that
5225 * option other than VFT was parsed on
5228 #define RX_PKT_V2_CMPL_HI_ERRORS_PKT_ERROR_L3_BAD_VERSION \
5229 (UINT32_C(0x1) << 12)
5231 * indicates that header length is out of range. Valid for
5234 #define RX_PKT_V2_CMPL_HI_ERRORS_PKT_ERROR_L3_BAD_HDR_LEN \
5235 (UINT32_C(0x2) << 12)
5237 * indicates that the IPv4 TTL or IPv6 hop limit check
5238 * have failed (e.g. TTL = 0). Valid for IPv4, and IPv6
5240 #define RX_PKT_V2_CMPL_HI_ERRORS_PKT_ERROR_L3_BAD_TTL \
5241 (UINT32_C(0x3) << 12)
5243 * Indicates that physical packet is shorter than that
5244 * claimed by the l3 header length. Valid for IPv4,
5245 * IPv6 packet or RoCE packets.
5247 #define RX_PKT_V2_CMPL_HI_ERRORS_PKT_ERROR_IP_TOTAL_ERROR \
5248 (UINT32_C(0x4) << 12)
5250 * Indicates that the physical packet is shorter than that
5251 * claimed by the UDP header length for a UDP packet that is
5254 #define RX_PKT_V2_CMPL_HI_ERRORS_PKT_ERROR_UDP_TOTAL_ERROR \
5255 (UINT32_C(0x5) << 12)
5257 * Indicates that TCP header length > IP payload. Valid for
5260 #define RX_PKT_V2_CMPL_HI_ERRORS_PKT_ERROR_L4_BAD_HDR_LEN \
5261 (UINT32_C(0x6) << 12)
5262 /* Indicates that TCP header length < 5. Valid for TCP. */
5263 #define RX_PKT_V2_CMPL_HI_ERRORS_PKT_ERROR_L4_BAD_HDR_LEN_TOO_SMALL \
5264 (UINT32_C(0x7) << 12)
5266 * Indicates that TCP option headers result in a TCP header
5267 * size that does not match data offset in TCP header. Valid
5270 #define RX_PKT_V2_CMPL_HI_ERRORS_PKT_ERROR_L4_BAD_OPT_LEN \
5271 (UINT32_C(0x8) << 12)
5273 * Indicates that the IP checksum failed its check in the
5276 #define RX_PKT_V2_CMPL_HI_ERRORS_PKT_ERROR_IP_CS_ERROR \
5277 (UINT32_C(0x9) << 12)
5279 * Indicates that the L4 checksum failed its check in the
5282 #define RX_PKT_V2_CMPL_HI_ERRORS_PKT_ERROR_L4_CS_ERROR \
5283 (UINT32_C(0xa) << 12)
5284 #define RX_PKT_V2_CMPL_HI_ERRORS_PKT_ERROR_LAST \
5285 RX_PKT_V2_CMPL_HI_ERRORS_PKT_ERROR_L4_CS_ERROR
5287 * This is data from the CFA block as indicated by the meta_format
5291 /* When meta_format=1, this value is the VLAN VID. */
5292 #define RX_PKT_V2_CMPL_HI_METADATA0_VID_MASK UINT32_C(0xfff)
5293 #define RX_PKT_V2_CMPL_HI_METADATA0_VID_SFT 0
5294 /* When meta_format=1, this value is the VLAN DE. */
5295 #define RX_PKT_V2_CMPL_HI_METADATA0_DE UINT32_C(0x1000)
5296 /* When meta_format=1, this value is the VLAN PRI. */
5297 #define RX_PKT_V2_CMPL_HI_METADATA0_PRI_MASK UINT32_C(0xe000)
5298 #define RX_PKT_V2_CMPL_HI_METADATA0_PRI_SFT 13
5300 * The timestamp field contains the 32b timestamp for the packet from
5307 * This TPA completion structure is used on devices where the
5308 * `hwrm_vnic_qcaps.max_aggs_supported` value is 0.
5310 /* rx_tpa_start_cmpl (size:128b/16B) */
5311 struct rx_tpa_start_cmpl {
5312 uint16_t flags_type;
5314 * This field indicates the exact type of the completion.
5315 * By convention, the LSB identifies the length of the
5316 * record in 16B units. Even values indicate 16B
5317 * records. Odd values indicate 32B
5320 #define RX_TPA_START_CMPL_TYPE_MASK UINT32_C(0x3f)
5321 #define RX_TPA_START_CMPL_TYPE_SFT 0
5323 * RX L2 TPA Start Completion:
5324 * Completion at the beginning of a TPA operation.
5327 #define RX_TPA_START_CMPL_TYPE_RX_TPA_START UINT32_C(0x13)
5328 #define RX_TPA_START_CMPL_TYPE_LAST \
5329 RX_TPA_START_CMPL_TYPE_RX_TPA_START
5330 #define RX_TPA_START_CMPL_FLAGS_MASK UINT32_C(0xffc0)
5331 #define RX_TPA_START_CMPL_FLAGS_SFT 6
5332 /* This bit will always be '0' for TPA start completions. */
5333 #define RX_TPA_START_CMPL_FLAGS_ERROR UINT32_C(0x40)
5334 /* This field indicates how the packet was placed in the buffer. */
5335 #define RX_TPA_START_CMPL_FLAGS_PLACEMENT_MASK UINT32_C(0x380)
5336 #define RX_TPA_START_CMPL_FLAGS_PLACEMENT_SFT 7
5339 * TPA Packet was placed using jumbo algorithm. This means
5340 * that the first buffer will be filled with data before
5341 * moving to aggregation buffers. Each aggregation buffer
5342 * will be filled before moving to the next aggregation
5345 #define RX_TPA_START_CMPL_FLAGS_PLACEMENT_JUMBO \
5346 (UINT32_C(0x1) << 7)
5348 * Header/Data Separation:
5349 * Packet was placed using Header/Data separation algorithm.
5350 * The separation location is indicated by the itype field.
5352 #define RX_TPA_START_CMPL_FLAGS_PLACEMENT_HDS \
5353 (UINT32_C(0x2) << 7)
5356 * Packet will be placed using GRO/Jumbo where the first
5357 * packet is filled with data. Subsequent packets will be
5358 * placed such that any one packet does not span two
5359 * aggregation buffers unless it starts at the beginning of
5360 * an aggregation buffer.
5362 #define RX_TPA_START_CMPL_FLAGS_PLACEMENT_GRO_JUMBO \
5363 (UINT32_C(0x5) << 7)
5365 * GRO/Header-Data Separation:
5366 * Packet will be placed using GRO/HDS where the header
5367 * is in the first packet.
5368 * Payload of each packet will be
5369 * placed such that any one packet does not span two
5370 * aggregation buffers unless it starts at the beginning of
5371 * an aggregation buffer.
5373 #define RX_TPA_START_CMPL_FLAGS_PLACEMENT_GRO_HDS \
5374 (UINT32_C(0x6) << 7)
5375 #define RX_TPA_START_CMPL_FLAGS_PLACEMENT_LAST \
5376 RX_TPA_START_CMPL_FLAGS_PLACEMENT_GRO_HDS
5377 /* This bit is '1' if the RSS field in this completion is valid. */
5378 #define RX_TPA_START_CMPL_FLAGS_RSS_VALID UINT32_C(0x400)
5380 #define RX_TPA_START_CMPL_FLAGS_UNUSED UINT32_C(0x800)
5382 * This value indicates what the inner packet determined for the
5385 #define RX_TPA_START_CMPL_FLAGS_ITYPE_MASK UINT32_C(0xf000)
5386 #define RX_TPA_START_CMPL_FLAGS_ITYPE_SFT 12
5389 * Indicates that the packet was IP and TCP.
5391 #define RX_TPA_START_CMPL_FLAGS_ITYPE_TCP \
5392 (UINT32_C(0x2) << 12)
5393 #define RX_TPA_START_CMPL_FLAGS_ITYPE_LAST \
5394 RX_TPA_START_CMPL_FLAGS_ITYPE_TCP
5396 * This value indicates the amount of packet data written to the
5397 * buffer the opaque field in this completion corresponds to.
5401 * This is a copy of the opaque field from the RX BD this completion
5406 * This value is written by the NIC such that it will be different
5407 * for each pass through the completion queue. The even passes
5408 * will write 1. The odd passes will write 0.
5412 * This value is written by the NIC such that it will be different
5413 * for each pass through the completion queue. The even passes
5414 * will write 1. The odd passes will write 0.
5416 #define RX_TPA_START_CMPL_V1 UINT32_C(0x1)
5417 #define RX_TPA_START_CMPL_LAST RX_TPA_START_CMPL_V1
5419 * This is the RSS hash type for the packet. The value is packed
5420 * {tuple_extrac_op[1:0],rss_profile_id[4:0],tuple_extrac_op[2]}.
5422 * The value of tuple_extrac_op provides the information about
5423 * what fields the hash was computed on.
5424 * * 0: The RSS hash was computed over source IP address,
5425 * destination IP address, source port, and destination port of inner
5426 * IP and TCP or UDP headers. Note: For non-tunneled packets,
5427 * the packet headers are considered inner packet headers for the RSS
5428 * hash computation purpose.
5429 * * 1: The RSS hash was computed over source IP address and destination
5430 * IP address of inner IP header. Note: For non-tunneled packets,
5431 * the packet headers are considered inner packet headers for the RSS
5432 * hash computation purpose.
5433 * * 2: The RSS hash was computed over source IP address,
5434 * destination IP address, source port, and destination port of
5435 * IP and TCP or UDP headers of outer tunnel headers.
5436 * Note: For non-tunneled packets, this value is not applicable.
5437 * * 3: The RSS hash was computed over source IP address and
5438 * destination IP address of IP header of outer tunnel headers.
5439 * Note: For non-tunneled packets, this value is not applicable.
5441 * Note that 4-tuples values listed above are applicable
5442 * for layer 4 protocols supported and enabled for RSS in the hardware,
5443 * HWRM firmware, and drivers. For example, if RSS hash is supported and
5444 * enabled for TCP traffic only, then the values of tuple_extract_op
5445 * corresponding to 4-tuples are only valid for TCP traffic.
5447 uint8_t rss_hash_type;
5449 * This is the aggregation ID that the completion is associated
5450 * with. Use this number to correlate the TPA start completion
5451 * with the TPA end completion.
5454 /* unused2 is 9 b */
5455 #define RX_TPA_START_CMPL_UNUSED2_MASK UINT32_C(0x1ff)
5456 #define RX_TPA_START_CMPL_UNUSED2_SFT 0
5458 * This is the aggregation ID that the completion is associated
5459 * with. Use this number to correlate the TPA start completion
5460 * with the TPA end completion.
5462 #define RX_TPA_START_CMPL_AGG_ID_MASK UINT32_C(0xfe00)
5463 #define RX_TPA_START_CMPL_AGG_ID_SFT 9
5465 * This value is the RSS hash value calculated for the packet
5466 * based on the mode bits and key value in the VNIC.
5472 * Last 16 bytes of rx_tpa_start_cmpl.
5474 * This TPA completion structure is used on devices where the
5475 * `hwrm_vnic_qcaps.max_aggs_supported` value is 0.
5477 /* rx_tpa_start_cmpl_hi (size:128b/16B) */
5478 struct rx_tpa_start_cmpl_hi {
5481 * This indicates that the ip checksum was calculated for the
5482 * inner packet and that the sum passed for all segments
5483 * included in the aggregation.
5485 #define RX_TPA_START_CMPL_FLAGS2_IP_CS_CALC UINT32_C(0x1)
5487 * This indicates that the TCP, UDP or ICMP checksum was
5488 * calculated for the inner packet and that the sum passed
5489 * for all segments included in the aggregation.
5491 #define RX_TPA_START_CMPL_FLAGS2_L4_CS_CALC UINT32_C(0x2)
5493 * This indicates that the ip checksum was calculated for the
5494 * tunnel header and that the sum passed for all segments
5495 * included in the aggregation.
5497 #define RX_TPA_START_CMPL_FLAGS2_T_IP_CS_CALC UINT32_C(0x4)
5499 * This indicates that the UDP checksum was
5500 * calculated for the tunnel packet and that the sum passed for
5501 * all segments included in the aggregation.
5503 #define RX_TPA_START_CMPL_FLAGS2_T_L4_CS_CALC UINT32_C(0x8)
5504 /* This value indicates what format the metadata field is. */
5505 #define RX_TPA_START_CMPL_FLAGS2_META_FORMAT_MASK UINT32_C(0xf0)
5506 #define RX_TPA_START_CMPL_FLAGS2_META_FORMAT_SFT 4
5507 /* No metadata information. Value is zero. */
5508 #define RX_TPA_START_CMPL_FLAGS2_META_FORMAT_NONE \
5509 (UINT32_C(0x0) << 4)
5511 * The metadata field contains the VLAN tag and TPID value.
5512 * - metadata[11:0] contains the vlan VID value.
5513 * - metadata[12] contains the vlan DE value.
5514 * - metadata[15:13] contains the vlan PRI value.
5515 * - metadata[31:16] contains the vlan TPID value.
5517 #define RX_TPA_START_CMPL_FLAGS2_META_FORMAT_VLAN \
5518 (UINT32_C(0x1) << 4)
5519 #define RX_TPA_START_CMPL_FLAGS2_META_FORMAT_LAST \
5520 RX_TPA_START_CMPL_FLAGS2_META_FORMAT_VLAN
5522 * This field indicates the IP type for the inner-most IP header.
5523 * A value of '0' indicates IPv4. A value of '1' indicates IPv6.
5525 #define RX_TPA_START_CMPL_FLAGS2_IP_TYPE UINT32_C(0x100)
5527 * This is data from the CFA block as indicated by the meta_format
5531 /* When meta_format=1, this value is the VLAN VID. */
5532 #define RX_TPA_START_CMPL_METADATA_VID_MASK UINT32_C(0xfff)
5533 #define RX_TPA_START_CMPL_METADATA_VID_SFT 0
5534 /* When meta_format=1, this value is the VLAN DE. */
5535 #define RX_TPA_START_CMPL_METADATA_DE UINT32_C(0x1000)
5536 /* When meta_format=1, this value is the VLAN PRI. */
5537 #define RX_TPA_START_CMPL_METADATA_PRI_MASK UINT32_C(0xe000)
5538 #define RX_TPA_START_CMPL_METADATA_PRI_SFT 13
5539 /* When meta_format=1, this value is the VLAN TPID. */
5540 #define RX_TPA_START_CMPL_METADATA_TPID_MASK UINT32_C(0xffff0000)
5541 #define RX_TPA_START_CMPL_METADATA_TPID_SFT 16
5544 * This value is written by the NIC such that it will be different
5545 * for each pass through the completion queue. The even passes
5546 * will write 1. The odd passes will write 0.
5548 #define RX_TPA_START_CMPL_V2 UINT32_C(0x1)
5550 * This field identifies the CFA action rule that was used for this
5555 * This is the size in bytes of the inner most L4 header.
5556 * This can be subtracted from the payload_offset to determine
5557 * the start of the inner most L4 header.
5559 uint32_t inner_l4_size_inner_l3_offset_inner_l2_offset_outer_l3_offset;
5561 * This is the offset from the beginning of the packet in bytes for
5562 * the outer L3 header. If there is no outer L3 header, then this
5565 #define RX_TPA_START_CMPL_OUTER_L3_OFFSET_MASK UINT32_C(0x1ff)
5566 #define RX_TPA_START_CMPL_OUTER_L3_OFFSET_SFT 0
5568 * This is the offset from the beginning of the packet in bytes for
5569 * the inner most L2 header.
5571 #define RX_TPA_START_CMPL_INNER_L2_OFFSET_MASK UINT32_C(0x3fe00)
5572 #define RX_TPA_START_CMPL_INNER_L2_OFFSET_SFT 9
5574 * This is the offset from the beginning of the packet in bytes for
5575 * the inner most L3 header.
5577 #define RX_TPA_START_CMPL_INNER_L3_OFFSET_MASK UINT32_C(0x7fc0000)
5578 #define RX_TPA_START_CMPL_INNER_L3_OFFSET_SFT 18
5580 * This is the size in bytes of the inner most L4 header.
5581 * This can be subtracted from the payload_offset to determine
5582 * the start of the inner most L4 header.
5584 #define RX_TPA_START_CMPL_INNER_L4_SIZE_MASK UINT32_C(0xf8000000)
5585 #define RX_TPA_START_CMPL_INNER_L4_SIZE_SFT 27
5589 * This TPA completion structure is used on devices where the
5590 * `hwrm_vnic_qcaps.max_aggs_supported` value is 0.
5591 * RX L2 TPA Start V2 Completion Record (32 bytes split to 2 16-byte
5594 /* rx_tpa_start_v2_cmpl (size:128b/16B) */
5595 struct rx_tpa_start_v2_cmpl {
5596 uint16_t flags_type;
5598 * This field indicates the exact type of the completion.
5599 * By convention, the LSB identifies the length of the
5600 * record in 16B units. Even values indicate 16B
5601 * records. Odd values indicate 32B
5604 #define RX_TPA_START_V2_CMPL_TYPE_MASK \
5606 #define RX_TPA_START_V2_CMPL_TYPE_SFT 0
5608 * RX L2 TPA Start V2 Completion:
5609 * Completion at the beginning of a TPA operation.
5611 * This is the new version of the RX_TPA_START completion used
5612 * in SR2 and later chips.
5614 #define RX_TPA_START_V2_CMPL_TYPE_RX_TPA_START_V2 \
5616 #define RX_TPA_START_V2_CMPL_TYPE_LAST \
5617 RX_TPA_START_V2_CMPL_TYPE_RX_TPA_START_V2
5618 #define RX_TPA_START_V2_CMPL_FLAGS_MASK \
5620 #define RX_TPA_START_V2_CMPL_FLAGS_SFT 6
5622 * When this bit is '1', it indicates a packet that has an error
5623 * of some type. Type of error is indicated in error_flags.
5625 #define RX_TPA_START_V2_CMPL_FLAGS_ERROR \
5627 /* This field indicates how the packet was placed in the buffer. */
5628 #define RX_TPA_START_V2_CMPL_FLAGS_PLACEMENT_MASK \
5630 #define RX_TPA_START_V2_CMPL_FLAGS_PLACEMENT_SFT 7
5633 * TPA Packet was placed using jumbo algorithm. This means
5634 * that the first buffer will be filled with data before
5635 * moving to aggregation buffers. Each aggregation buffer
5636 * will be filled before moving to the next aggregation
5639 #define RX_TPA_START_V2_CMPL_FLAGS_PLACEMENT_JUMBO \
5640 (UINT32_C(0x1) << 7)
5642 * Header/Data Separation:
5643 * Packet was placed using Header/Data separation algorithm.
5644 * The separation location is indicated by the itype field.
5646 #define RX_TPA_START_V2_CMPL_FLAGS_PLACEMENT_HDS \
5647 (UINT32_C(0x2) << 7)
5650 * Packet will be placed using In-Order Completion/Jumbo where
5651 * the first packet of the aggregation is placed using Jumbo
5652 * Placement. Subsequent packets will be placed such that each
5653 * packet starts at the beginning of an aggregation buffer.
5655 #define RX_TPA_START_V2_CMPL_FLAGS_PLACEMENT_IOC_JUMBO \
5656 (UINT32_C(0x4) << 7)
5659 * Packet will be placed using GRO/Jumbo where the first
5660 * packet is filled with data. Subsequent packets will be
5661 * placed such that any one packet does not span two
5662 * aggregation buffers unless it starts at the beginning of
5663 * an aggregation buffer.
5665 #define RX_TPA_START_V2_CMPL_FLAGS_PLACEMENT_GRO_JUMBO \
5666 (UINT32_C(0x5) << 7)
5668 * GRO/Header-Data Separation:
5669 * Packet will be placed using GRO/HDS where the header
5670 * is in the first packet.
5671 * Payload of each packet will be
5672 * placed such that any one packet does not span two
5673 * aggregation buffers unless it starts at the beginning of
5674 * an aggregation buffer.
5676 #define RX_TPA_START_V2_CMPL_FLAGS_PLACEMENT_GRO_HDS \
5677 (UINT32_C(0x6) << 7)
5679 * IOC/Header-Data Separation:
5680 * Packet will be placed using In-Order Completion/HDS where
5681 * the header is in the first packet buffer. Payload of each
5682 * packet will be placed such that each packet starts at the
5683 * beginning of an aggregation buffer.
5685 #define RX_TPA_START_V2_CMPL_FLAGS_PLACEMENT_IOC_HDS \
5686 (UINT32_C(0x7) << 7)
5687 #define RX_TPA_START_V2_CMPL_FLAGS_PLACEMENT_LAST \
5688 RX_TPA_START_V2_CMPL_FLAGS_PLACEMENT_IOC_HDS
5689 /* This bit is '1' if the RSS field in this completion is valid. */
5690 #define RX_TPA_START_V2_CMPL_FLAGS_RSS_VALID \
5693 * This bit is '1' if metadata has been added to the end of the
5694 * packet in host memory. Metadata starts at the first 32B boundary
5695 * after the end of the packet for regular and jumbo placement. It
5696 * starts at the first 32B boundary after the end of the header for
5697 * HDS placement. The length of the metadata is indicated in the
5700 #define RX_TPA_START_V2_CMPL_FLAGS_PKT_METADATA_PRESENT \
5703 * This value indicates what the inner packet determined for the
5706 #define RX_TPA_START_V2_CMPL_FLAGS_ITYPE_MASK \
5708 #define RX_TPA_START_V2_CMPL_FLAGS_ITYPE_SFT 12
5711 * Indicates that the packet was IP and TCP.
5713 #define RX_TPA_START_V2_CMPL_FLAGS_ITYPE_TCP \
5714 (UINT32_C(0x2) << 12)
5715 #define RX_TPA_START_V2_CMPL_FLAGS_ITYPE_LAST \
5716 RX_TPA_START_V2_CMPL_FLAGS_ITYPE_TCP
5718 * This value indicates the amount of packet data written to the
5719 * buffer the opaque field in this completion corresponds to.
5723 * This is a copy of the opaque field from the RX BD this completion
5724 * corresponds to. If the VNIC is configured to not use an Rx BD for
5725 * the TPA Start completion, then this is a copy of the opaque field
5726 * from the first BD used to place the TPA Start packet.
5730 * This value is written by the NIC such that it will be different
5731 * for each pass through the completion queue. The even passes
5732 * will write 1. The odd passes will write 0.
5736 * This value is written by the NIC such that it will be different
5737 * for each pass through the completion queue. The even passes
5738 * will write 1. The odd passes will write 0.
5740 #define RX_TPA_START_V2_CMPL_V1 UINT32_C(0x1)
5741 #define RX_TPA_START_V2_CMPL_LAST RX_TPA_START_V2_CMPL_V1
5743 * This is the RSS hash type for the packet. The value is packed
5744 * {tuple_extrac_op[1:0],rss_profile_id[4:0],tuple_extrac_op[2]}.
5746 * The value of tuple_extrac_op provides the information about
5747 * what fields the hash was computed on.
5748 * * 0: The RSS hash was computed over source IP address,
5749 * destination IP address, source port, and destination port of inner
5750 * IP and TCP or UDP headers. Note: For non-tunneled packets,
5751 * the packet headers are considered inner packet headers for the RSS
5752 * hash computation purpose.
5753 * * 1: The RSS hash was computed over source IP address and destination
5754 * IP address of inner IP header. Note: For non-tunneled packets,
5755 * the packet headers are considered inner packet headers for the RSS
5756 * hash computation purpose.
5757 * * 2: The RSS hash was computed over source IP address,
5758 * destination IP address, source port, and destination port of
5759 * IP and TCP or UDP headers of outer tunnel headers.
5760 * Note: For non-tunneled packets, this value is not applicable.
5761 * * 3: The RSS hash was computed over source IP address and
5762 * destination IP address of IP header of outer tunnel headers.
5763 * Note: For non-tunneled packets, this value is not applicable.
5765 * Note that 4-tuples values listed above are applicable
5766 * for layer 4 protocols supported and enabled for RSS in the hardware,
5767 * HWRM firmware, and drivers. For example, if RSS hash is supported and
5768 * enabled for TCP traffic only, then the values of tuple_extract_op
5769 * corresponding to 4-tuples are only valid for TCP traffic.
5771 uint8_t rss_hash_type;
5773 * This is the aggregation ID that the completion is associated
5774 * with. Use this number to correlate the TPA start completion
5775 * with the TPA end completion.
5779 * This is the aggregation ID that the completion is associated
5780 * with. Use this number to correlate the TPA start completion
5781 * with the TPA end completion.
5783 #define RX_TPA_START_V2_CMPL_AGG_ID_MASK UINT32_C(0xfff)
5784 #define RX_TPA_START_V2_CMPL_AGG_ID_SFT 0
5785 #define RX_TPA_START_V2_CMPL_METADATA1_MASK \
5787 #define RX_TPA_START_V2_CMPL_METADATA1_SFT 12
5788 /* When meta_format != 0, this value is the VLAN TPID_SEL. */
5789 #define RX_TPA_START_V2_CMPL_METADATA1_TPID_SEL_MASK \
5791 #define RX_TPA_START_V2_CMPL_METADATA1_TPID_SEL_SFT 12
5793 #define RX_TPA_START_V2_CMPL_METADATA1_TPID_SEL_TPID88A8 \
5794 (UINT32_C(0x0) << 12)
5796 #define RX_TPA_START_V2_CMPL_METADATA1_TPID_SEL_TPID8100 \
5797 (UINT32_C(0x1) << 12)
5799 #define RX_TPA_START_V2_CMPL_METADATA1_TPID_SEL_TPID9100 \
5800 (UINT32_C(0x2) << 12)
5802 #define RX_TPA_START_V2_CMPL_METADATA1_TPID_SEL_TPID9200 \
5803 (UINT32_C(0x3) << 12)
5805 #define RX_TPA_START_V2_CMPL_METADATA1_TPID_SEL_TPID9300 \
5806 (UINT32_C(0x4) << 12)
5807 /* Value programmed in CFA VLANTPID register. */
5808 #define RX_TPA_START_V2_CMPL_METADATA1_TPID_SEL_TPIDCFG \
5809 (UINT32_C(0x5) << 12)
5810 #define RX_TPA_START_V2_CMPL_METADATA1_TPID_SEL_LAST \
5811 RX_TPA_START_V2_CMPL_METADATA1_TPID_SEL_TPIDCFG
5812 /* When meta_format != 0, this value is the VLAN valid. */
5813 #define RX_TPA_START_V2_CMPL_METADATA1_VALID \
5816 * This value is the RSS hash value calculated for the packet
5817 * based on the mode bits and key value in the VNIC.
5818 * When vee_cmpl_mode is set in VNIC context, this is the lower
5819 * 32b of the host address from the first BD used to place the packet.
5825 * Last 16 bytes of RX L2 TPA Start V2 Completion Record
5827 * This TPA completion structure is used on devices where the
5828 * `hwrm_vnic_qcaps.max_aggs_supported` value is 0.
5830 /* rx_tpa_start_v2_cmpl_hi (size:128b/16B) */
5831 struct rx_tpa_start_v2_cmpl_hi {
5833 /* This indicates that the aggregation was done using GRO rules. */
5834 #define RX_TPA_START_V2_CMPL_FLAGS2_AGG_GRO \
5837 * When this bit is '0', the cs_ok field has the following definition:-
5838 * ip_cs_ok[2:0] = The number of header groups with a valid IP checksum
5839 * in the delivered packet, counted from the outer-most header group to
5840 * the inner-most header group, stopping at the first error. -
5841 * l4_cs_ok[5:3] = The number of header groups with a valid L4 checksum
5842 * in the delivered packet, counted from the outer-most header group to
5843 * the inner-most header group, stopping at the first error. When this
5844 * bit is '1', the cs_ok field has the following definition: -
5845 * hdr_cnt[2:0] = The number of header groups that were parsed by the
5846 * chip and passed in the delivered packet. - ip_cs_all_ok[3] =This bit
5847 * will be '1' if all the parsed header groups with an IP checksum are
5848 * valid. - l4_cs_all_ok[4] = This bit will be '1' if all the parsed
5849 * header groups with an L4 checksum are valid.
5851 #define RX_TPA_START_V2_CMPL_FLAGS2_CS_ALL_OK_MODE \
5853 /* This value indicates what format the metadata field is. */
5854 #define RX_TPA_START_V2_CMPL_FLAGS2_META_FORMAT_MASK \
5856 #define RX_TPA_START_V2_CMPL_FLAGS2_META_FORMAT_SFT 4
5857 /* There is no metadata information. Values are zero. */
5858 #define RX_TPA_START_V2_CMPL_FLAGS2_META_FORMAT_NONE \
5859 (UINT32_C(0x0) << 4)
5861 * The {metadata1, metadata0} fields contain the vtag
5862 * information: - vtag[19:0] = {valid, tpid_sel[2:0], pri[2:0],
5863 * de, vid[11:0]} The metadata2 field contains the table scope
5864 * and action record pointer. - metadata2[25:0] contains the
5865 * action record pointer. - metadata2[31:26] contains the table
5868 #define RX_TPA_START_V2_CMPL_FLAGS2_META_FORMAT_ACT_REC_PTR \
5869 (UINT32_C(0x1) << 4)
5871 * The {metadata1, metadata0} fields contain the vtag
5873 * - vtag[19:0] = {valid, tpid_sel[2:0], pri[2:0], de, vid[11:0]}
5874 * The metadata2 field contains the Tunnel ID
5875 * value, justified to LSB. i
5876 * - VXLAN = VNI[23:0] -> VXLAN Network ID
5877 * - Geneve (NGE) = VNI[23:0] a-> Virtual Network Identifier
5878 * - NVGRE = TNI[23:0] -> Tenant Network ID
5879 * - GRE = KEY[31:0] -> key field with bit mask. zero if K=0
5880 * - IPv4 = 0 (not populated)
5881 * - IPv6 = Flow Label[19:0]
5882 * - PPPoE = sessionID[15:0]
5883 * - MPLs = Outer label[19:0]
5884 * - UPAR = Selected[31:0] with bit mask
5886 #define RX_TPA_START_V2_CMPL_FLAGS2_META_FORMAT_TUNNEL_ID \
5887 (UINT32_C(0x2) << 4)
5889 * The {metadata1, metadata0} fields contain the vtag
5891 * - vtag[19:0] = {valid, tpid_sel[2:0], pri[2:0],de, vid[11:0]}
5892 * The metadata2 field contains the 32b metadata from the prepended
5893 * header (chdr_data).
5895 #define RX_TPA_START_V2_CMPL_FLAGS2_META_FORMAT_CHDR_DATA \
5896 (UINT32_C(0x3) << 4)
5898 * The {metadata1, metadata0} fields contain the vtag
5900 * - vtag[19:0] = {valid, tpid_sel[2:0], pri[2:0], de, vid[11:0]}
5901 * The metadata2 field contains the outer_l3_offset,
5902 * inner_l2_offset, inner_l3_offset, and inner_l4_size.
5903 * - metadata2[8:0] contains the outer_l3_offset.
5904 * - metadata2[17:9] contains the inner_l2_offset.
5905 * - metadata2[26:18] contains the inner_l3_offset.
5906 * - metadata2[31:27] contains the inner_l4_size.
5908 #define RX_TPA_START_V2_CMPL_FLAGS2_META_FORMAT_HDR_OFFSET \
5909 (UINT32_C(0x4) << 4)
5910 #define RX_TPA_START_V2_CMPL_FLAGS2_META_FORMAT_LAST \
5911 RX_TPA_START_V2_CMPL_FLAGS2_META_FORMAT_HDR_OFFSET
5913 * This field indicates the IP type for the inner-most IP header.
5914 * A value of '0' indicates IPv4. A value of '1' indicates IPv6.
5915 * This value is only valid if itype indicates a packet
5916 * with an IP header.
5918 #define RX_TPA_START_V2_CMPL_FLAGS2_IP_TYPE \
5921 * This indicates that the complete 1's complement checksum was
5922 * calculated for the packet in the affregation.
5924 #define RX_TPA_START_V2_CMPL_FLAGS2_COMPLETE_CHECKSUM_CALC \
5927 * This field indicates the status of IP and L4 CS calculations done
5928 * by the chip. The format of this field is indicated by the
5929 * cs_all_ok_mode bit.
5930 * CS status for TPA packets is always valid. This means that "all_ok"
5931 * status will always be set. The ok count status will be set
5932 * appropriately for the packet header, such that all existing CS
5935 #define RX_TPA_START_V2_CMPL_FLAGS2_CS_OK_MASK \
5937 #define RX_TPA_START_V2_CMPL_FLAGS2_CS_OK_SFT 10
5939 * This value is the complete 1's complement checksum calculated from
5940 * the start of the outer L3 header to the end of the packet (not
5941 * including the ethernet crc). It is valid when the
5942 * 'complete_checksum_calc' flag is set. For TPA Start completions,
5943 * the complete checksum is calculated for the first packet in the
5946 #define RX_TPA_START_V2_CMPL_FLAGS2_COMPLETE_CHECKSUM_MASK \
5947 UINT32_C(0xffff0000)
5948 #define RX_TPA_START_V2_CMPL_FLAGS2_COMPLETE_CHECKSUM_SFT 16
5950 * This is data from the CFA block as indicated by the meta_format
5952 * - meta_format 0 - none - metadata2 = 0 - not valid/not stripped
5953 * - meta_format 1 - act_rec_ptr - metadata2 = {table_scope[5:0],
5954 * act_rec_ptr[25:0]}
5955 * - meta_format 2 - tunnel_id - metadata2 = tunnel_id[31:0]
5956 * - meta_format 3 - chdr_data - metadata2 = updated_chdr_data[31:0]
5957 * - meta_format 4 - hdr_offsets - metadata2 = hdr_offsets[31:0]
5958 * When vee_cmpl_mode is set in VNIC context, this is the upper 32b
5959 * of the host address from the first BD used to place the packet.
5964 * This value is written by the NIC such that it will be different
5965 * for each pass through the completion queue. The even passes
5966 * will write 1. The odd passes will write 0.
5968 #define RX_TPA_START_V2_CMPL_V2 \
5970 #define RX_TPA_START_V2_CMPL_ERRORS_MASK \
5972 #define RX_TPA_START_V2_CMPL_ERRORS_SFT 1
5974 * This error indicates that there was some sort of problem with
5975 * the BDs for the packetThe packet should be treated as
5978 #define RX_TPA_START_V2_CMPL_ERRORS_BUFFER_ERROR_MASK \
5980 #define RX_TPA_START_V2_CMPL_ERRORS_BUFFER_ERROR_SFT 1
5981 /* No buffer error */
5982 #define RX_TPA_START_V2_CMPL_ERRORS_BUFFER_ERROR_NO_BUFFER \
5983 (UINT32_C(0x0) << 1)
5986 * Packet did not fit into packet buffer provided. This means
5987 * that the TPA Start packet was too big to be placed into the
5988 * per-packet maximum number of physical buffers configured for
5989 * the VNIC, or that it was too big to be placed into the
5990 * per-aggregation maximum number of physical buffers configured
5991 * for the VNIC. This error only occurs when the VNIC is
5992 * configured for variable size receive buffers.
5994 #define RX_TPA_START_V2_CMPL_ERRORS_BUFFER_ERROR_DID_NOT_FIT \
5995 (UINT32_C(0x1) << 1)
5998 * BDs were not formatted correctly.
6000 #define RX_TPA_START_V2_CMPL_ERRORS_BUFFER_ERROR_BAD_FORMAT \
6001 (UINT32_C(0x3) << 1)
6004 * There was a bad_format error on the previous operation
6006 #define RX_TPA_START_V2_CMPL_ERRORS_BUFFER_ERROR_FLUSH \
6007 (UINT32_C(0x5) << 1)
6008 #define RX_TPA_START_V2_CMPL_ERRORS_BUFFER_ERROR_LAST \
6009 RX_TPA_START_V2_CMPL_ERRORS_BUFFER_ERROR_FLUSH
6011 * This is data from the CFA block as indicated by the meta_format
6015 /* When meta_format != 0, this value is the VLAN VID. */
6016 #define RX_TPA_START_V2_CMPL_METADATA0_VID_MASK UINT32_C(0xfff)
6017 #define RX_TPA_START_V2_CMPL_METADATA0_VID_SFT 0
6018 /* When meta_format != 0, this value is the VLAN DE. */
6019 #define RX_TPA_START_V2_CMPL_METADATA0_DE UINT32_C(0x1000)
6020 /* When meta_format != 0, this value is the VLAN PRI. */
6021 #define RX_TPA_START_V2_CMPL_METADATA0_PRI_MASK UINT32_C(0xe000)
6022 #define RX_TPA_START_V2_CMPL_METADATA0_PRI_SFT 13
6024 * This field contains the outer_l3_offset, inner_l2_offset,
6025 * inner_l3_offset, and inner_l4_size.
6027 * hdr_offsets[8:0] contains the outer_l3_offset.
6028 * hdr_offsets[17:9] contains the inner_l2_offset.
6029 * hdr_offsets[26:18] contains the inner_l3_offset.
6030 * hdr_offsets[31:27] contains the inner_l4_size.
6032 uint32_t hdr_offsets;
6036 * This TPA completion structure is used on devices where the
6037 * `hwrm_vnic_qcaps.max_aggs_supported` value is 0.
6039 /* rx_tpa_end_cmpl (size:128b/16B) */
6040 struct rx_tpa_end_cmpl {
6041 uint16_t flags_type;
6043 * This field indicates the exact type of the completion.
6044 * By convention, the LSB identifies the length of the
6045 * record in 16B units. Even values indicate 16B
6046 * records. Odd values indicate 32B
6049 #define RX_TPA_END_CMPL_TYPE_MASK UINT32_C(0x3f)
6050 #define RX_TPA_END_CMPL_TYPE_SFT 0
6052 * RX L2 TPA End Completion:
6053 * Completion at the end of a TPA operation.
6056 #define RX_TPA_END_CMPL_TYPE_RX_TPA_END UINT32_C(0x15)
6057 #define RX_TPA_END_CMPL_TYPE_LAST \
6058 RX_TPA_END_CMPL_TYPE_RX_TPA_END
6059 #define RX_TPA_END_CMPL_FLAGS_MASK UINT32_C(0xffc0)
6060 #define RX_TPA_END_CMPL_FLAGS_SFT 6
6062 * When this bit is '1', it indicates a packet that has an
6063 * error of some type. Type of error is indicated in
6066 #define RX_TPA_END_CMPL_FLAGS_ERROR UINT32_C(0x40)
6067 /* This field indicates how the packet was placed in the buffer. */
6068 #define RX_TPA_END_CMPL_FLAGS_PLACEMENT_MASK UINT32_C(0x380)
6069 #define RX_TPA_END_CMPL_FLAGS_PLACEMENT_SFT 7
6072 * TPA Packet was placed using jumbo algorithm. This means
6073 * that the first buffer will be filled with data before
6074 * moving to aggregation buffers. Each aggregation buffer
6075 * will be filled before moving to the next aggregation
6078 #define RX_TPA_END_CMPL_FLAGS_PLACEMENT_JUMBO \
6079 (UINT32_C(0x1) << 7)
6081 * Header/Data Separation:
6082 * Packet was placed using Header/Data separation algorithm.
6083 * The separation location is indicated by the itype field.
6085 #define RX_TPA_END_CMPL_FLAGS_PLACEMENT_HDS \
6086 (UINT32_C(0x2) << 7)
6089 * Packet will be placed using In-Order Completion/Jumbo where
6090 * the first packet of the aggregation is placed using Jumbo
6091 * Placement. Subsequent packets will be placed such that each
6092 * packet starts at the beginning of an aggregation buffer.
6094 #define RX_TPA_END_CMPL_FLAGS_PLACEMENT_IOC_JUMBO \
6095 (UINT32_C(0x4) << 7)
6098 * Packet will be placed using GRO/Jumbo where the first
6099 * packet is filled with data. Subsequent packets will be
6100 * placed such that any one packet does not span two
6101 * aggregation buffers unless it starts at the beginning of
6102 * an aggregation buffer.
6104 #define RX_TPA_END_CMPL_FLAGS_PLACEMENT_GRO_JUMBO \
6105 (UINT32_C(0x5) << 7)
6107 * GRO/Header-Data Separation:
6108 * Packet will be placed using GRO/HDS where the header
6109 * is in the first packet.
6110 * Payload of each packet will be
6111 * placed such that any one packet does not span two
6112 * aggregation buffers unless it starts at the beginning of
6113 * an aggregation buffer.
6115 #define RX_TPA_END_CMPL_FLAGS_PLACEMENT_GRO_HDS \
6116 (UINT32_C(0x6) << 7)
6118 * IOC/Header-Data Separation:
6119 * Packet will be placed using In-Order Completion/HDS where
6120 * the header is in the first packet buffer. Payload of each
6121 * packet will be placed such that each packet starts at the
6122 * beginning of an aggregation buffer.
6124 #define RX_TPA_END_CMPL_FLAGS_PLACEMENT_IOC_HDS \
6125 (UINT32_C(0x7) << 7)
6126 #define RX_TPA_END_CMPL_FLAGS_PLACEMENT_LAST \
6127 RX_TPA_END_CMPL_FLAGS_PLACEMENT_IOC_HDS
6129 #define RX_TPA_END_CMPL_FLAGS_UNUSED UINT32_C(0x400)
6131 * This bit is '1' if metadata has been added to the end of the
6132 * packet in host memory. Metadata starts at the first 32B boundary
6133 * after the end of the packet for regular and jumbo placement.
6134 * It starts at the first 32B boundary after the end of the header
6135 * for HDS placement. The length of the metadata is indicated in the
6138 #define RX_TPA_END_CMPL_FLAGS_PKT_METADATA_PRESENT UINT32_C(0x800)
6140 * This value indicates what the inner packet determined for the
6143 * Indicates that the packet was IP and TCP. This indicates
6144 * that the ip_cs field is valid and that the tcp_udp_cs
6145 * field is valid and contains the TCP checksum.
6146 * This also indicates that the payload_offset field is valid.
6148 #define RX_TPA_END_CMPL_FLAGS_ITYPE_MASK \
6150 #define RX_TPA_END_CMPL_FLAGS_ITYPE_SFT 12
6152 * This value is zero for TPA End completions.
6153 * There is no data in the buffer that corresponds to the opaque
6154 * value in this completion.
6158 * This is a copy of the opaque field from the RX BD this completion
6163 * This value is written by the NIC such that it will be different
6164 * for each pass through the completion queue. The even passes
6165 * will write 1. The odd passes will write 0.
6167 uint8_t agg_bufs_v1;
6169 * This value is written by the NIC such that it will be different
6170 * for each pass through the completion queue. The even passes
6171 * will write 1. The odd passes will write 0.
6173 #define RX_TPA_END_CMPL_V1 UINT32_C(0x1)
6175 * This value is the number of aggregation buffers that follow this
6176 * entry in the completion ring that are a part of this aggregation
6178 * If the value is zero, then the packet is completely contained
6179 * in the buffer space provided in the aggregation start completion.
6181 #define RX_TPA_END_CMPL_AGG_BUFS_MASK UINT32_C(0x7e)
6182 #define RX_TPA_END_CMPL_AGG_BUFS_SFT 1
6183 /* This value is the number of segments in the TPA operation. */
6186 * This value indicates the offset in bytes from the beginning of the packet
6187 * where the inner payload starts. This value is valid for TCP, UDP,
6188 * FCoE, and RoCE packets.
6190 * A value of zero indicates an offset of 256 bytes.
6192 uint8_t payload_offset;
6194 /* unused2 is 1 b */
6195 #define RX_TPA_END_CMPL_UNUSED2 UINT32_C(0x1)
6197 * This is the aggregation ID that the completion is associated
6198 * with. Use this number to correlate the TPA start completion
6199 * with the TPA end completion.
6201 #define RX_TPA_END_CMPL_AGG_ID_MASK UINT32_C(0xfe)
6202 #define RX_TPA_END_CMPL_AGG_ID_SFT 1
6204 * For non-GRO packets, this value is the
6205 * timestamp delta between earliest and latest timestamp values for
6206 * TPA packet. If packets were not time stamped, then delta will be
6209 * For GRO packets, this field is zero except for the following
6212 * Timestamp present indication. When '0', no Timestamp
6213 * option is in the packet. When '1', then a Timestamp
6214 * option is present in the packet.
6220 * Last 16 bytes of rx_tpa_end_cmpl.
6222 * This TPA completion structure is used on devices where the
6223 * `hwrm_vnic_qcaps.max_aggs_supported` value is 0.
6225 /* rx_tpa_end_cmpl_hi (size:128b/16B) */
6226 struct rx_tpa_end_cmpl_hi {
6227 uint32_t tpa_dup_acks;
6229 * This value is the number of duplicate ACKs that have been
6230 * received as part of the TPA operation.
6232 #define RX_TPA_END_CMPL_TPA_DUP_ACKS_MASK UINT32_C(0xf)
6233 #define RX_TPA_END_CMPL_TPA_DUP_ACKS_SFT 0
6235 * This value is the valid when TPA completion is active. It
6236 * indicates the length of the longest segment of the TPA operation
6237 * for LRO mode and the length of the first segment in GRO mode.
6239 * This value may be used by GRO software to re-construct the original
6240 * packet stream from the TPA packet. This is the length of all
6241 * but the last segment for GRO. In LRO mode this value may be used
6242 * to indicate MSS size to the stack.
6244 uint16_t tpa_seg_len;
6245 /* unused4 is 16 b */
6249 * This value is written by the NIC such that it will be different
6250 * for each pass through the completion queue. The even passes
6251 * will write 1. The odd passes will write 0.
6253 #define RX_TPA_END_CMPL_V2 UINT32_C(0x1)
6254 #define RX_TPA_END_CMPL_ERRORS_MASK UINT32_C(0xfffe)
6255 #define RX_TPA_END_CMPL_ERRORS_SFT 1
6257 * This error indicates that there was some sort of problem with
6258 * the BDs for the packet that was found after part of the
6259 * packet was already placed. The packet should be treated as
6262 #define RX_TPA_END_CMPL_ERRORS_BUFFER_ERROR_MASK UINT32_C(0xe)
6263 #define RX_TPA_END_CMPL_ERRORS_BUFFER_ERROR_SFT 1
6265 * This error occurs when there is a fatal HW problem in
6266 * the chip only. It indicates that there were not
6267 * BDs on chip but that there was adequate reservation.
6268 * provided by the TPA block.
6270 #define RX_TPA_END_CMPL_ERRORS_BUFFER_ERROR_NOT_ON_CHIP \
6271 (UINT32_C(0x2) << 1)
6273 * This error occurs when TPA block was not configured to
6274 * reserve adequate BDs for TPA operations on this RX
6275 * ring. All data for the TPA operation was not placed.
6277 * This error can also be generated when the number of
6278 * segments is not programmed correctly in TPA and the
6279 * 33 total aggregation buffers allowed for the TPA
6280 * operation has been exceeded.
6282 #define RX_TPA_END_CMPL_ERRORS_BUFFER_ERROR_RSV_ERROR \
6283 (UINT32_C(0x4) << 1)
6284 #define RX_TPA_END_CMPL_ERRORS_BUFFER_ERROR_LAST \
6285 RX_TPA_END_CMPL_ERRORS_BUFFER_ERROR_RSV_ERROR
6286 /* unused5 is 16 b */
6289 * This is the opaque value that was completed for the TPA start
6290 * completion that corresponds to this TPA end completion.
6292 uint32_t start_opaque;
6296 * This TPA completion structure is used on devices where the
6297 * `hwrm_vnic_qcaps.max_aggs_supported` value is greater than 0.
6299 /* rx_tpa_v2_start_cmpl (size:128b/16B) */
6300 struct rx_tpa_v2_start_cmpl {
6301 uint16_t flags_type;
6303 * This field indicates the exact type of the completion.
6304 * By convention, the LSB identifies the length of the
6305 * record in 16B units. Even values indicate 16B
6306 * records. Odd values indicate 32B
6309 #define RX_TPA_V2_START_CMPL_TYPE_MASK \
6311 #define RX_TPA_V2_START_CMPL_TYPE_SFT 0
6313 * RX L2 TPA Start Completion:
6314 * Completion at the beginning of a TPA operation.
6317 #define RX_TPA_V2_START_CMPL_TYPE_RX_TPA_START \
6319 #define RX_TPA_V2_START_CMPL_TYPE_LAST \
6320 RX_TPA_V2_START_CMPL_TYPE_RX_TPA_START
6321 #define RX_TPA_V2_START_CMPL_FLAGS_MASK \
6323 #define RX_TPA_V2_START_CMPL_FLAGS_SFT 6
6324 /* This bit will always be '0' for TPA start completions. */
6325 #define RX_TPA_V2_START_CMPL_FLAGS_ERROR \
6327 /* This field indicates how the packet was placed in the buffer. */
6328 #define RX_TPA_V2_START_CMPL_FLAGS_PLACEMENT_MASK \
6330 #define RX_TPA_V2_START_CMPL_FLAGS_PLACEMENT_SFT 7
6333 * TPA Packet was placed using jumbo algorithm. This means
6334 * that the first buffer will be filled with data before
6335 * moving to aggregation buffers. Each aggregation buffer
6336 * will be filled before moving to the next aggregation
6339 #define RX_TPA_V2_START_CMPL_FLAGS_PLACEMENT_JUMBO \
6340 (UINT32_C(0x1) << 7)
6342 * Header/Data Separation:
6343 * Packet was placed using Header/Data separation algorithm.
6344 * The separation location is indicated by the itype field.
6346 #define RX_TPA_V2_START_CMPL_FLAGS_PLACEMENT_HDS \
6347 (UINT32_C(0x2) << 7)
6350 * Packet will be placed using GRO/Jumbo where the first
6351 * packet is filled with data. Subsequent packets will be
6352 * placed such that any one packet does not span two
6353 * aggregation buffers unless it starts at the beginning of
6354 * an aggregation buffer.
6356 #define RX_TPA_V2_START_CMPL_FLAGS_PLACEMENT_GRO_JUMBO \
6357 (UINT32_C(0x5) << 7)
6359 * GRO/Header-Data Separation:
6360 * Packet will be placed using GRO/HDS where the header
6361 * is in the first packet.
6362 * Payload of each packet will be
6363 * placed such that any one packet does not span two
6364 * aggregation buffers unless it starts at the beginning of
6365 * an aggregation buffer.
6367 #define RX_TPA_V2_START_CMPL_FLAGS_PLACEMENT_GRO_HDS \
6368 (UINT32_C(0x6) << 7)
6369 #define RX_TPA_V2_START_CMPL_FLAGS_PLACEMENT_LAST \
6370 RX_TPA_V2_START_CMPL_FLAGS_PLACEMENT_GRO_HDS
6371 /* This bit is '1' if the RSS field in this completion is valid. */
6372 #define RX_TPA_V2_START_CMPL_FLAGS_RSS_VALID \
6375 * For devices that support timestamps, when this bit is cleared the
6376 * `inner_l4_size_inner_l3_offset_inner_l2_offset_outer_l3_offset`
6377 * field contains the 32b timestamp for
6378 * the packet from the MAC. When this bit is set, the
6379 * `inner_l4_size_inner_l3_offset_inner_l2_offset_outer_l3_offset`
6380 * field contains the outer_l3_offset, inner_l2_offset,
6381 * inner_l3_offset, and inner_l4_size.
6383 #define RX_TPA_V2_START_CMPL_FLAGS_TIMESTAMP_FLD_FORMAT \
6386 * This value indicates what the inner packet determined for the
6389 #define RX_TPA_V2_START_CMPL_FLAGS_ITYPE_MASK \
6391 #define RX_TPA_V2_START_CMPL_FLAGS_ITYPE_SFT 12
6394 * Indicates that the packet was IP and TCP.
6396 #define RX_TPA_V2_START_CMPL_FLAGS_ITYPE_TCP \
6397 (UINT32_C(0x2) << 12)
6398 #define RX_TPA_V2_START_CMPL_FLAGS_ITYPE_LAST \
6399 RX_TPA_V2_START_CMPL_FLAGS_ITYPE_TCP
6401 * This value indicates the amount of packet data written to the
6402 * buffer the opaque field in this completion corresponds to.
6406 * This is a copy of the opaque field from the RX BD this completion
6411 * This value is written by the NIC such that it will be different
6412 * for each pass through the completion queue. The even passes
6413 * will write 1. The odd passes will write 0.
6417 * This value is written by the NIC such that it will be different
6418 * for each pass through the completion queue. The even passes
6419 * will write 1. The odd passes will write 0.
6421 #define RX_TPA_V2_START_CMPL_V1 UINT32_C(0x1)
6422 #define RX_TPA_V2_START_CMPL_LAST RX_TPA_V2_START_CMPL_V1
6424 * This is the RSS hash type for the packet. The value is packed
6425 * {tuple_extrac_op[1:0],rss_profile_id[4:0],tuple_extrac_op[2]}.
6427 * The value of tuple_extrac_op provides the information about
6428 * what fields the hash was computed on.
6429 * * 0: The RSS hash was computed over source IP address,
6430 * destination IP address, source port, and destination port of inner
6431 * IP and TCP or UDP headers. Note: For non-tunneled packets,
6432 * the packet headers are considered inner packet headers for the RSS
6433 * hash computation purpose.
6434 * * 1: The RSS hash was computed over source IP address and destination
6435 * IP address of inner IP header. Note: For non-tunneled packets,
6436 * the packet headers are considered inner packet headers for the RSS
6437 * hash computation purpose.
6438 * * 2: The RSS hash was computed over source IP address,
6439 * destination IP address, source port, and destination port of
6440 * IP and TCP or UDP headers of outer tunnel headers.
6441 * Note: For non-tunneled packets, this value is not applicable.
6442 * * 3: The RSS hash was computed over source IP address and
6443 * destination IP address of IP header of outer tunnel headers.
6444 * Note: For non-tunneled packets, this value is not applicable.
6446 * Note that 4-tuples values listed above are applicable
6447 * for layer 4 protocols supported and enabled for RSS in the hardware,
6448 * HWRM firmware, and drivers. For example, if RSS hash is supported and
6449 * enabled for TCP traffic only, then the values of tuple_extract_op
6450 * corresponding to 4-tuples are only valid for TCP traffic.
6452 uint8_t rss_hash_type;
6454 * This is the aggregation ID that the completion is associated
6455 * with. Use this number to correlate the TPA start completion
6456 * with the TPA end completion.
6460 * This value is the RSS hash value calculated for the packet
6461 * based on the mode bits and key value in the VNIC.
6467 * Last 16 bytes of rx_tpa_v2_start_cmpl.
6469 * This TPA completion structure is used on devices where the
6470 * `hwrm_vnic_qcaps.max_aggs_supported` value is greater than 0.
6472 /* rx_tpa_v2_start_cmpl_hi (size:128b/16B) */
6473 struct rx_tpa_v2_start_cmpl_hi {
6476 * This indicates that the ip checksum was calculated for the
6477 * inner packet and that the sum passed for all segments
6478 * included in the aggregation.
6480 #define RX_TPA_V2_START_CMPL_FLAGS2_IP_CS_CALC \
6483 * This indicates that the TCP, UDP or ICMP checksum was
6484 * calculated for the inner packet and that the sum passed
6485 * for all segments included in the aggregation.
6487 #define RX_TPA_V2_START_CMPL_FLAGS2_L4_CS_CALC \
6490 * This indicates that the ip checksum was calculated for the
6491 * tunnel header and that the sum passed for all segments
6492 * included in the aggregation.
6494 #define RX_TPA_V2_START_CMPL_FLAGS2_T_IP_CS_CALC \
6497 * This indicates that the UDP checksum was
6498 * calculated for the tunnel packet and that the sum passed for
6499 * all segments included in the aggregation.
6501 #define RX_TPA_V2_START_CMPL_FLAGS2_T_L4_CS_CALC \
6503 /* This value indicates what format the metadata field is. */
6504 #define RX_TPA_V2_START_CMPL_FLAGS2_META_FORMAT_MASK \
6506 #define RX_TPA_V2_START_CMPL_FLAGS2_META_FORMAT_SFT 4
6507 /* No metadata informtaion. Value is zero. */
6508 #define RX_TPA_V2_START_CMPL_FLAGS2_META_FORMAT_NONE \
6509 (UINT32_C(0x0) << 4)
6511 * The metadata field contains the VLAN tag and TPID value.
6512 * - metadata[11:0] contains the vlan VID value.
6513 * - metadata[12] contains the vlan DE value.
6514 * - metadata[15:13] contains the vlan PRI value.
6515 * - metadata[31:16] contains the vlan TPID value.
6517 #define RX_TPA_V2_START_CMPL_FLAGS2_META_FORMAT_VLAN \
6518 (UINT32_C(0x1) << 4)
6520 * If ext_meta_format is equal to 1, the metadata field
6521 * contains the lower 16b of the tunnel ID value, justified
6523 * - VXLAN = VNI[23:0] -> VXLAN Network ID
6524 * - Geneve (NGE) = VNI[23:0] a-> Virtual Network Identifier.
6525 * - NVGRE = TNI[23:0] -> Tenant Network ID
6526 * - GRE = KEY[31:0 -> key fieled with bit mask. zero if K = 0
6527 * - IPV4 = 0 (not populated)
6528 * - IPV6 = Flow Label[19:0]
6529 * - PPPoE = sessionID[15:0]
6530 * - MPLs = Outer label[19:0]
6531 * - UPAR = Selected[31:0] with bit mask
6533 #define RX_TPA_V2_START_CMPL_FLAGS2_META_FORMAT_TUNNEL_ID \
6534 (UINT32_C(0x2) << 4)
6536 * if ext_meta_format is equal to 1, metadata field contains
6537 * 16b metadata from the prepended header (chdr_data).
6539 #define RX_TPA_V2_START_CMPL_FLAGS2_META_FORMAT_CHDR_DATA \
6540 (UINT32_C(0x3) << 4)
6542 * If ext_meta_format is equal to 1, the metadata field contains
6543 * the outer_l3_offset, inner_l2_offset, inner_l3_offset and
6545 * - metadata[8:0] contains the outer_l3_offset.
6546 * - metadata[17:9] contains the inner_l2_offset.
6547 * - metadata[26:18] contains the inner_l3_offset.
6548 * - metadata[31:27] contains the inner_l4_size.
6550 #define RX_TPA_V2_START_CMPL_FLAGS2_META_FORMAT_HDR_OFFSET \
6551 (UINT32_C(0x4) << 4)
6552 #define RX_TPA_V2_START_CMPL_FLAGS2_META_FORMAT_LAST \
6553 RX_TPA_V2_START_CMPL_FLAGS2_META_FORMAT_HDR_OFFSET
6555 * This field indicates the IP type for the inner-most IP header.
6556 * A value of '0' indicates IPv4. A value of '1' indicates IPv6.
6558 #define RX_TPA_V2_START_CMPL_FLAGS2_IP_TYPE \
6561 * This indicates that the complete 1's complement checksum was
6562 * calculated for the packet.
6564 #define RX_TPA_V2_START_CMPL_FLAGS2_COMPLETE_CHECKSUM_CALC \
6567 * The combination of this value and meta_format indicated what
6568 * format the metadata field is.
6570 #define RX_TPA_V2_START_CMPL_FLAGS2_EXT_META_FORMAT_MASK \
6572 #define RX_TPA_V2_START_CMPL_FLAGS2_EXT_META_FORMAT_SFT 10
6574 * This value is the complete 1's complement checksum calculated from
6575 * the start of the outer L3 header to the end of the packet (not
6576 * including the ethernet crc). It is valid when the
6577 * 'complete_checksum_calc' flag is set. For TPA Start completions,
6578 * the complete checksum is calculated for the first packet in the
6581 #define RX_TPA_V2_START_CMPL_FLAGS2_COMPLETE_CHECKSUM_MASK \
6582 UINT32_C(0xffff0000)
6583 #define RX_TPA_V2_START_CMPL_FLAGS2_COMPLETE_CHECKSUM_SFT 16
6585 * This is data from the CFA block as indicated by the meta_format
6589 /* When {ext_meta_format,meta_format}=1, this value is the VLAN VID. */
6590 #define RX_TPA_V2_START_CMPL_METADATA_VID_MASK UINT32_C(0xfff)
6591 #define RX_TPA_V2_START_CMPL_METADATA_VID_SFT 0
6592 /* When {ext_meta_format,meta_format}=1, this value is the VLAN DE. */
6593 #define RX_TPA_V2_START_CMPL_METADATA_DE UINT32_C(0x1000)
6594 /* When {ext_meta_format,meta_format}=1, this value is the VLAN PRI. */
6595 #define RX_TPA_V2_START_CMPL_METADATA_PRI_MASK UINT32_C(0xe000)
6596 #define RX_TPA_V2_START_CMPL_METADATA_PRI_SFT 13
6597 /* When {ext_meta_format,meta_format}=1, this value is the VLAN TPID. */
6598 #define RX_TPA_V2_START_CMPL_METADATA_TPID_MASK UINT32_C(0xffff0000)
6599 #define RX_TPA_V2_START_CMPL_METADATA_TPID_SFT 16
6602 * This value is written by the NIC such that it will be different
6603 * for each pass through the completion queue. The even passes
6604 * will write 1. The odd passes will write 0.
6606 #define RX_TPA_V2_START_CMPL_V2 \
6608 #define RX_TPA_V2_START_CMPL_ERRORS_MASK \
6610 #define RX_TPA_V2_START_CMPL_ERRORS_SFT 1
6612 * This error indicates that there was some sort of problem with
6613 * the BDs for the packet that was found after part of the
6614 * packet was already placed. The packet should be treated as
6617 #define RX_TPA_V2_START_CMPL_ERRORS_BUFFER_ERROR_MASK \
6619 #define RX_TPA_V2_START_CMPL_ERRORS_BUFFER_ERROR_SFT 1
6620 /* No buffer error */
6621 #define RX_TPA_V2_START_CMPL_ERRORS_BUFFER_ERROR_NO_BUFFER \
6622 (UINT32_C(0x0) << 1)
6625 * BDs were not formatted correctly.
6627 #define RX_TPA_V2_START_CMPL_ERRORS_BUFFER_ERROR_BAD_FORMAT \
6628 (UINT32_C(0x3) << 1)
6631 * There was a bad_format error on the previous operation
6633 #define RX_TPA_V2_START_CMPL_ERRORS_BUFFER_ERROR_FLUSH \
6634 (UINT32_C(0x5) << 1)
6635 #define RX_TPA_V2_START_CMPL_ERRORS_BUFFER_ERROR_LAST \
6636 RX_TPA_V2_START_CMPL_ERRORS_BUFFER_ERROR_FLUSH
6638 * This field identifies the CFA action rule that was used for this
6643 * For devices that support timestamps this field is overridden
6644 * with the timestamp value. When `flags.timestamp_fld_format` is
6645 * cleared, this field contains the 32b timestamp for the packet from the
6648 * When `flags.timestamp_fld_format` is set, this field contains the
6649 * outer_l3_offset, inner_l2_offset, inner_l3_offset, and inner_l4_size
6652 uint32_t inner_l4_size_inner_l3_offset_inner_l2_offset_outer_l3_offset;
6654 * This is the offset from the beginning of the packet in bytes for
6655 * the outer L3 header. If there is no outer L3 header, then this
6658 #define RX_TPA_V2_START_CMPL_OUTER_L3_OFFSET_MASK UINT32_C(0x1ff)
6659 #define RX_TPA_V2_START_CMPL_OUTER_L3_OFFSET_SFT 0
6661 * This is the offset from the beginning of the packet in bytes for
6662 * the inner most L2 header.
6664 #define RX_TPA_V2_START_CMPL_INNER_L2_OFFSET_MASK UINT32_C(0x3fe00)
6665 #define RX_TPA_V2_START_CMPL_INNER_L2_OFFSET_SFT 9
6667 * This is the offset from the beginning of the packet in bytes for
6668 * the inner most L3 header.
6670 #define RX_TPA_V2_START_CMPL_INNER_L3_OFFSET_MASK UINT32_C(0x7fc0000)
6671 #define RX_TPA_V2_START_CMPL_INNER_L3_OFFSET_SFT 18
6673 * This is the size in bytes of the inner most L4 header.
6674 * This can be subtracted from the payload_offset to determine
6675 * the start of the inner most L4 header.
6677 #define RX_TPA_V2_START_CMPL_INNER_L4_SIZE_MASK UINT32_C(0xf8000000)
6678 #define RX_TPA_V2_START_CMPL_INNER_L4_SIZE_SFT 27
6682 * This TPA completion structure is used on devices where the
6683 * `hwrm_vnic_qcaps.max_aggs_supported` value is greater than 0.
6685 /* rx_tpa_v2_end_cmpl (size:128b/16B) */
6686 struct rx_tpa_v2_end_cmpl {
6687 uint16_t flags_type;
6689 * This field indicates the exact type of the completion.
6690 * By convention, the LSB identifies the length of the
6691 * record in 16B units. Even values indicate 16B
6692 * records. Odd values indicate 32B
6695 #define RX_TPA_V2_END_CMPL_TYPE_MASK \
6697 #define RX_TPA_V2_END_CMPL_TYPE_SFT 0
6699 * RX L2 TPA End Completion:
6700 * Completion at the end of a TPA operation.
6703 #define RX_TPA_V2_END_CMPL_TYPE_RX_TPA_END \
6705 #define RX_TPA_V2_END_CMPL_TYPE_LAST \
6706 RX_TPA_V2_END_CMPL_TYPE_RX_TPA_END
6707 #define RX_TPA_V2_END_CMPL_FLAGS_MASK \
6709 #define RX_TPA_V2_END_CMPL_FLAGS_SFT 6
6711 * When this bit is '1', it indicates a packet that has an
6712 * error of some type. Type of error is indicated in
6715 #define RX_TPA_V2_END_CMPL_FLAGS_ERROR \
6717 /* This field indicates how the packet was placed in the buffer. */
6718 #define RX_TPA_V2_END_CMPL_FLAGS_PLACEMENT_MASK \
6720 #define RX_TPA_V2_END_CMPL_FLAGS_PLACEMENT_SFT 7
6723 * TPA Packet was placed using jumbo algorithm. This means
6724 * that the first buffer will be filled with data before
6725 * moving to aggregation buffers. Each aggregation buffer
6726 * will be filled before moving to the next aggregation
6729 #define RX_TPA_V2_END_CMPL_FLAGS_PLACEMENT_JUMBO \
6730 (UINT32_C(0x1) << 7)
6732 * Header/Data Separation:
6733 * Packet was placed using Header/Data separation algorithm.
6734 * The separation location is indicated by the itype field.
6736 #define RX_TPA_V2_END_CMPL_FLAGS_PLACEMENT_HDS \
6737 (UINT32_C(0x2) << 7)
6740 * Packet will be placed using GRO/Jumbo where the first
6741 * packet is filled with data. Subsequent packets will be
6742 * placed such that any one packet does not span two
6743 * aggregation buffers unless it starts at the beginning of
6744 * an aggregation buffer.
6746 #define RX_TPA_V2_END_CMPL_FLAGS_PLACEMENT_GRO_JUMBO \
6747 (UINT32_C(0x5) << 7)
6749 * GRO/Header-Data Separation:
6750 * Packet will be placed using GRO/HDS where the header
6751 * is in the first packet.
6752 * Payload of each packet will be
6753 * placed such that any one packet does not span two
6754 * aggregation buffers unless it starts at the beginning of
6755 * an aggregation buffer.
6757 #define RX_TPA_V2_END_CMPL_FLAGS_PLACEMENT_GRO_HDS \
6758 (UINT32_C(0x6) << 7)
6760 * IOC/Header-Data Separation:
6761 * Packet will be placed using In-Order Completion/HDS where
6762 * the header is in the first packet buffer. Payload of each
6763 * packet will be placed such that each packet starts at the
6764 * beginning of an aggregation buffer.
6766 #define RX_TPA_V2_END_CMPL_FLAGS_PLACEMENT_IOC_HDS \
6767 (UINT32_C(0x7) << 7)
6768 #define RX_TPA_V2_END_CMPL_FLAGS_PLACEMENT_LAST \
6769 RX_TPA_V2_END_CMPL_FLAGS_PLACEMENT_IOC_HDS
6771 #define RX_TPA_V2_END_CMPL_FLAGS_UNUSED \
6774 * This bit is '1' if metadata has been added to the end of the
6775 * packet in host memory. Metadata starts at the first 32B boundary
6776 * after the end of the packet for regular and jumbo placement.
6777 * It starts at the first 32B boundary after the end of the header
6778 * for HDS placement. The length of the metadata is indicated in the
6781 #define RX_TPA_V2_END_CMPL_FLAGS_PKT_METADATA_PRESENT \
6784 * This value indicates what the inner packet determined for the
6787 * Indicates that the packet was IP and TCP. This indicates
6788 * that the ip_cs field is valid and that the tcp_udp_cs
6789 * field is valid and contains the TCP checksum.
6790 * This also indicates that the payload_offset field is valid.
6792 #define RX_TPA_V2_END_CMPL_FLAGS_ITYPE_MASK \
6794 #define RX_TPA_V2_END_CMPL_FLAGS_ITYPE_SFT 12
6796 * This value is zero for TPA End completions.
6797 * There is no data in the buffer that corresponds to the opaque
6798 * value in this completion.
6802 * This is a copy of the opaque field from the RX BD this completion
6808 * This value is written by the NIC such that it will be different
6809 * for each pass through the completion queue. The even passes
6810 * will write 1. The odd passes will write 0.
6812 #define RX_TPA_V2_END_CMPL_V1 UINT32_C(0x1)
6813 /* This value is the number of segments in the TPA operation. */
6816 * This is the aggregation ID that the completion is associated
6817 * with. Use this number to correlate the TPA start completion
6818 * with the TPA end completion.
6822 * For non-GRO packets, this value is the
6823 * timestamp delta between earliest and latest timestamp values for
6824 * TPA packet. If packets were not time stamped, then delta will be
6827 * For GRO packets, this field is zero except for the following
6830 * Timestamp present indication. When '0', no Timestamp
6831 * option is in the packet. When '1', then a Timestamp
6832 * option is present in the packet.
6838 * Last 16 bytes of rx_tpa_v2_end_cmpl.
6840 * This TPA completion structure is used on devices where the
6841 * `hwrm_vnic_qcaps.max_aggs_supported` value is greater than 0.
6843 /* rx_tpa_v2_end_cmpl_hi (size:128b/16B) */
6844 struct rx_tpa_v2_end_cmpl_hi {
6846 * This value is the number of duplicate ACKs that have been
6847 * received as part of the TPA operation.
6849 uint16_t tpa_dup_acks;
6851 * This value is the number of duplicate ACKs that have been
6852 * received as part of the TPA operation.
6854 #define RX_TPA_V2_END_CMPL_TPA_DUP_ACKS_MASK UINT32_C(0xf)
6855 #define RX_TPA_V2_END_CMPL_TPA_DUP_ACKS_SFT 0
6857 * This value indicated the offset in bytes from the beginning of
6858 * the packet where the inner payload starts. This value is valid
6859 * for TCP, UDP, FCoE and RoCE packets
6861 uint8_t payload_offset;
6863 * The value is the total number of aggregation buffers that were
6864 * used in the TPA operation. All TPA aggregation buffer completions
6865 * precede the TPA End completion. If the value is zero, then the
6866 * aggregation is completely contained in the buffer space provided
6867 * in the aggregation start completion.
6868 * Note that the field is simply provided as a cross check.
6870 uint8_t tpa_agg_bufs;
6872 * This value is the valid when TPA completion is active. It
6873 * indicates the length of the longest segment of the TPA operation
6874 * for LRO mode and the length of the first segment in GRO mode.
6876 * This value may be used by GRO software to re-construct the original
6877 * packet stream from the TPA packet. This is the length of all
6878 * but the last segment for GRO. In LRO mode this value may be used
6879 * to indicate MSS size to the stack.
6881 uint16_t tpa_seg_len;
6885 * This value is written by the NIC such that it will be different
6886 * for each pass through the completion queue. The even passes
6887 * will write 1. The odd passes will write 0.
6889 #define RX_TPA_V2_END_CMPL_V2 UINT32_C(0x1)
6890 #define RX_TPA_V2_END_CMPL_ERRORS_MASK \
6892 #define RX_TPA_V2_END_CMPL_ERRORS_SFT 1
6894 * This error indicates that there was some sort of problem with
6895 * the BDs for the packet that was found after part of the
6896 * packet was already placed. The packet should be treated as
6899 #define RX_TPA_V2_END_CMPL_ERRORS_BUFFER_ERROR_MASK \
6901 #define RX_TPA_V2_END_CMPL_ERRORS_BUFFER_ERROR_SFT 1
6902 /* No buffer error */
6903 #define RX_TPA_V2_END_CMPL_ERRORS_BUFFER_ERROR_NO_BUFFER \
6904 (UINT32_C(0x0) << 1)
6906 * This error occurs when there is a fatal HW problem in
6907 * the chip only. It indicates that there were not
6908 * BDs on chip but that there was adequate reservation.
6909 * provided by the TPA block.
6911 #define RX_TPA_V2_END_CMPL_ERRORS_BUFFER_ERROR_NOT_ON_CHIP \
6912 (UINT32_C(0x2) << 1)
6915 * BDs were not formatted correctly.
6917 #define RX_TPA_V2_END_CMPL_ERRORS_BUFFER_ERROR_BAD_FORMAT \
6918 (UINT32_C(0x3) << 1)
6920 * This error occurs when TPA block was not configured to
6921 * reserve adequate BDs for TPA operations on this RX
6922 * ring. All data for the TPA operation was not placed.
6924 * This error can also be generated when the number of
6925 * segments is not programmed correctly in TPA and the
6926 * 33 total aggregation buffers allowed for the TPA
6927 * operation has been exceeded.
6929 #define RX_TPA_V2_END_CMPL_ERRORS_BUFFER_ERROR_RSV_ERROR \
6930 (UINT32_C(0x4) << 1)
6933 * There was a bad_format error on the previous operation
6935 #define RX_TPA_V2_END_CMPL_ERRORS_BUFFER_ERROR_FLUSH \
6936 (UINT32_C(0x5) << 1)
6937 #define RX_TPA_V2_END_CMPL_ERRORS_BUFFER_ERROR_LAST \
6938 RX_TPA_V2_END_CMPL_ERRORS_BUFFER_ERROR_FLUSH
6941 * This is the opaque value that was completed for the TPA start
6942 * completion that corresponds to this TPA end completion.
6944 uint32_t start_opaque;
6948 * This TPA completion structure is used on devices where the
6949 * `hwrm_vnic_qcaps.max_aggs_supported` value is greater than 0.
6951 /* rx_tpa_v2_abuf_cmpl (size:128b/16B) */
6952 struct rx_tpa_v2_abuf_cmpl {
6955 * This field indicates the exact type of the completion.
6956 * By convention, the LSB identifies the length of the
6957 * record in 16B units. Even values indicate 16B
6958 * records. Odd values indicate 32B
6961 #define RX_TPA_V2_ABUF_CMPL_TYPE_MASK UINT32_C(0x3f)
6962 #define RX_TPA_V2_ABUF_CMPL_TYPE_SFT 0
6964 * RX TPA Aggregation Buffer completion :
6965 * Completion of an L2 aggregation buffer in support of
6966 * TPA packet completion. Length = 16B
6968 #define RX_TPA_V2_ABUF_CMPL_TYPE_RX_TPA_AGG UINT32_C(0x16)
6969 #define RX_TPA_V2_ABUF_CMPL_TYPE_LAST \
6970 RX_TPA_V2_ABUF_CMPL_TYPE_RX_TPA_AGG
6972 * This is the length of the data for the packet stored in this
6973 * aggregation buffer identified by the opaque value. This does not
6974 * include the length of any
6975 * data placed in other aggregation BDs or in the packet or buffer
6976 * BDs. This length does not include any space added due to
6977 * hdr_offset register during HDS placement mode.
6981 * This is a copy of the opaque field from the RX BD this aggregation
6982 * buffer corresponds to.
6987 * This value is written by the NIC such that it will be different
6988 * for each pass through the completion queue. The even passes
6989 * will write 1. The odd passes will write 0.
6991 #define RX_TPA_V2_ABUF_CMPL_V UINT32_C(0x1)
6993 * This is the aggregation ID that the completion is associated with. Use
6994 * this number to correlate the TPA agg completion with the TPA start
6995 * completion and the TPA end completion.
7001 /* rx_abuf_cmpl (size:128b/16B) */
7002 struct rx_abuf_cmpl {
7005 * This field indicates the exact type of the completion.
7006 * By convention, the LSB identifies the length of the
7007 * record in 16B units. Even values indicate 16B
7008 * records. Odd values indicate 32B
7011 #define RX_ABUF_CMPL_TYPE_MASK UINT32_C(0x3f)
7012 #define RX_ABUF_CMPL_TYPE_SFT 0
7014 * RX Aggregation Buffer completion :
7015 * Completion of an L2 aggregation buffer in support of
7016 * TPA, HDS, or Jumbo packet completion. Length = 16B
7018 #define RX_ABUF_CMPL_TYPE_RX_AGG UINT32_C(0x12)
7019 #define RX_ABUF_CMPL_TYPE_LAST RX_ABUF_CMPL_TYPE_RX_AGG
7021 * This is the length of the data for the packet stored in this
7022 * aggregation buffer identified by the opaque value. This does not
7023 * include the length of any
7024 * data placed in other aggregation BDs or in the packet or buffer
7025 * BDs. This length does not include any space added due to
7026 * hdr_offset register during HDS placement mode.
7030 * This is a copy of the opaque field from the RX BD this aggregation
7031 * buffer corresponds to.
7036 * This value is written by the NIC such that it will be different
7037 * for each pass through the completion queue. The even passes
7038 * will write 1. The odd passes will write 0.
7040 #define RX_ABUF_CMPL_V UINT32_C(0x1)
7041 /* unused3 is 32 b */
7045 /* VEE FLUSH Completion Record (16 bytes) */
7046 /* vee_flush (size:128b/16B) */
7048 uint32_t downstream_path_type;
7050 * This field indicates the exact type of the completion.
7051 * By convention, the LSB identifies the length of the
7052 * record in 16B units. Even values indicate 16B
7053 * records. Odd values indicate 32B
7056 #define VEE_FLUSH_TYPE_MASK UINT32_C(0x3f)
7057 #define VEE_FLUSH_TYPE_SFT 0
7059 * VEE Flush Completion:
7060 * This completion is inserted manually by the Primate and processed
7061 * by the VEE hardware to ensure that all completions on a VEE
7062 * function have been processed by the VEE hardware before FLR
7063 * process is completed.
7065 #define VEE_FLUSH_TYPE_VEE_FLUSH UINT32_C(0x1c)
7066 #define VEE_FLUSH_TYPE_LAST VEE_FLUSH_TYPE_VEE_FLUSH
7067 /* downstream_path is 1 b */
7068 #define VEE_FLUSH_DOWNSTREAM_PATH UINT32_C(0x40)
7069 /* This completion is associated with VEE Transmit */
7070 #define VEE_FLUSH_DOWNSTREAM_PATH_TX (UINT32_C(0x0) << 6)
7071 /* This completion is associated with VEE Receive */
7072 #define VEE_FLUSH_DOWNSTREAM_PATH_RX (UINT32_C(0x1) << 6)
7073 #define VEE_FLUSH_DOWNSTREAM_PATH_LAST VEE_FLUSH_DOWNSTREAM_PATH_RX
7075 * This is an opaque value that is passed through the completion
7076 * to the VEE handler SW and is used to indicate what VEE VQ or
7077 * function has completed FLR processing.
7082 * This value is written by the NIC such that it will be different
7083 * for each pass through the completion queue. The even passes will
7084 * write 1. The odd passes will write 0.
7086 #define VEE_FLUSH_V UINT32_C(0x1)
7087 /* unused3 is 32 b */
7091 /* eject_cmpl (size:128b/16B) */
7095 * This field indicates the exact type of the completion.
7096 * By convention, the LSB identifies the length of the
7097 * record in 16B units. Even values indicate 16B
7098 * records. Odd values indicate 32B
7101 #define EJECT_CMPL_TYPE_MASK UINT32_C(0x3f)
7102 #define EJECT_CMPL_TYPE_SFT 0
7104 * Statistics Ejection Completion:
7105 * Completion of statistics data ejection buffer.
7108 #define EJECT_CMPL_TYPE_STAT_EJECT UINT32_C(0x1a)
7109 #define EJECT_CMPL_TYPE_LAST EJECT_CMPL_TYPE_STAT_EJECT
7110 #define EJECT_CMPL_FLAGS_MASK UINT32_C(0xffc0)
7111 #define EJECT_CMPL_FLAGS_SFT 6
7113 * When this bit is '1', it indicates a packet that has an
7114 * error of some type. Type of error is indicated in
7117 #define EJECT_CMPL_FLAGS_ERROR UINT32_C(0x40)
7119 * This is the length of the statistics data stored in this
7124 * This is a copy of the opaque field from the RX BD this ejection
7125 * buffer corresponds to.
7130 * This value is written by the NIC such that it will be different
7131 * for each pass through the completion queue. The even passes
7132 * will write 1. The odd passes will write 0.
7134 #define EJECT_CMPL_V UINT32_C(0x1)
7135 #define EJECT_CMPL_ERRORS_MASK UINT32_C(0xfffe)
7136 #define EJECT_CMPL_ERRORS_SFT 1
7138 * This error indicates that there was some sort of problem with
7139 * the BDs for statistics ejection. The statistics ejection should
7140 * be treated as invalid
7142 #define EJECT_CMPL_ERRORS_BUFFER_ERROR_MASK UINT32_C(0xe)
7143 #define EJECT_CMPL_ERRORS_BUFFER_ERROR_SFT 1
7144 /* No buffer error */
7145 #define EJECT_CMPL_ERRORS_BUFFER_ERROR_NO_BUFFER \
7146 (UINT32_C(0x0) << 1)
7149 * Statistics did not fit into aggregation buffer provided.
7151 #define EJECT_CMPL_ERRORS_BUFFER_ERROR_DID_NOT_FIT \
7152 (UINT32_C(0x1) << 1)
7155 * BDs were not formatted correctly.
7157 #define EJECT_CMPL_ERRORS_BUFFER_ERROR_BAD_FORMAT \
7158 (UINT32_C(0x3) << 1)
7161 * There was a bad_format error on the previous operation
7163 #define EJECT_CMPL_ERRORS_BUFFER_ERROR_FLUSH \
7164 (UINT32_C(0x5) << 1)
7165 #define EJECT_CMPL_ERRORS_BUFFER_ERROR_LAST \
7166 EJECT_CMPL_ERRORS_BUFFER_ERROR_FLUSH
7167 /* reserved16 is 16 b */
7168 uint16_t reserved16;
7169 /* unused3 is 32 b */
7173 /* hwrm_cmpl (size:128b/16B) */
7177 * This field indicates the exact type of the completion.
7178 * By convention, the LSB identifies the length of the
7179 * record in 16B units. Even values indicate 16B
7180 * records. Odd values indicate 32B
7183 #define HWRM_CMPL_TYPE_MASK UINT32_C(0x3f)
7184 #define HWRM_CMPL_TYPE_SFT 0
7186 * HWRM Command Completion:
7187 * Completion of an HWRM command.
7189 #define HWRM_CMPL_TYPE_HWRM_DONE UINT32_C(0x20)
7190 #define HWRM_CMPL_TYPE_LAST HWRM_CMPL_TYPE_HWRM_DONE
7191 /* This is the sequence_id of the HWRM command that has completed. */
7192 uint16_t sequence_id;
7193 /* unused2 is 32 b */
7197 * This value is written by the NIC such that it will be different
7198 * for each pass through the completion queue. The even passes
7199 * will write 1. The odd passes will write 0.
7201 #define HWRM_CMPL_V UINT32_C(0x1)
7202 /* unused4 is 32 b */
7206 /* hwrm_fwd_req_cmpl (size:128b/16B) */
7207 struct hwrm_fwd_req_cmpl {
7209 * This field indicates the exact type of the completion.
7210 * By convention, the LSB identifies the length of the
7211 * record in 16B units. Even values indicate 16B
7212 * records. Odd values indicate 32B
7215 uint16_t req_len_type;
7217 * This field indicates the exact type of the completion.
7218 * By convention, the LSB identifies the length of the
7219 * record in 16B units. Even values indicate 16B
7220 * records. Odd values indicate 32B
7223 #define HWRM_FWD_REQ_CMPL_TYPE_MASK UINT32_C(0x3f)
7224 #define HWRM_FWD_REQ_CMPL_TYPE_SFT 0
7225 /* Forwarded HWRM Request */
7226 #define HWRM_FWD_REQ_CMPL_TYPE_HWRM_FWD_REQ UINT32_C(0x22)
7227 #define HWRM_FWD_REQ_CMPL_TYPE_LAST \
7228 HWRM_FWD_REQ_CMPL_TYPE_HWRM_FWD_REQ
7229 /* Length of forwarded request in bytes. */
7230 #define HWRM_FWD_REQ_CMPL_REQ_LEN_MASK UINT32_C(0xffc0)
7231 #define HWRM_FWD_REQ_CMPL_REQ_LEN_SFT 6
7233 * Source ID of this request.
7234 * Typically used in forwarding requests and responses.
7235 * 0x0 - 0xFFF8 - Used for function ids
7236 * 0xFFF8 - 0xFFFE - Reserved for internal processors
7240 /* unused1 is 32 b */
7242 /* Address of forwarded request. */
7243 uint32_t req_buf_addr_v[2];
7245 * This value is written by the NIC such that it will be different
7246 * for each pass through the completion queue. The even passes
7247 * will write 1. The odd passes will write 0.
7249 #define HWRM_FWD_REQ_CMPL_V UINT32_C(0x1)
7250 /* Address of forwarded request. */
7251 #define HWRM_FWD_REQ_CMPL_REQ_BUF_ADDR_MASK UINT32_C(0xfffffffe)
7252 #define HWRM_FWD_REQ_CMPL_REQ_BUF_ADDR_SFT 1
7255 /* hwrm_fwd_resp_cmpl (size:128b/16B) */
7256 struct hwrm_fwd_resp_cmpl {
7259 * This field indicates the exact type of the completion.
7260 * By convention, the LSB identifies the length of the
7261 * record in 16B units. Even values indicate 16B
7262 * records. Odd values indicate 32B
7265 #define HWRM_FWD_RESP_CMPL_TYPE_MASK UINT32_C(0x3f)
7266 #define HWRM_FWD_RESP_CMPL_TYPE_SFT 0
7267 /* Forwarded HWRM Response */
7268 #define HWRM_FWD_RESP_CMPL_TYPE_HWRM_FWD_RESP UINT32_C(0x24)
7269 #define HWRM_FWD_RESP_CMPL_TYPE_LAST \
7270 HWRM_FWD_RESP_CMPL_TYPE_HWRM_FWD_RESP
7272 * Source ID of this response.
7273 * Typically used in forwarding requests and responses.
7274 * 0x0 - 0xFFF8 - Used for function ids
7275 * 0xFFF8 - 0xFFFE - Reserved for internal processors
7279 /* Length of forwarded response in bytes. */
7281 /* unused2 is 16 b */
7283 /* Address of forwarded request. */
7284 uint32_t resp_buf_addr_v[2];
7286 * This value is written by the NIC such that it will be different
7287 * for each pass through the completion queue. The even passes
7288 * will write 1. The odd passes will write 0.
7290 #define HWRM_FWD_RESP_CMPL_V UINT32_C(0x1)
7291 /* Address of forwarded request. */
7292 #define HWRM_FWD_RESP_CMPL_RESP_BUF_ADDR_MASK UINT32_C(0xfffffffe)
7293 #define HWRM_FWD_RESP_CMPL_RESP_BUF_ADDR_SFT 1
7296 /* hwrm_async_event_cmpl (size:128b/16B) */
7297 struct hwrm_async_event_cmpl {
7300 * This field indicates the exact type of the completion.
7301 * By convention, the LSB identifies the length of the
7302 * record in 16B units. Even values indicate 16B
7303 * records. Odd values indicate 32B
7306 #define HWRM_ASYNC_EVENT_CMPL_TYPE_MASK UINT32_C(0x3f)
7307 #define HWRM_ASYNC_EVENT_CMPL_TYPE_SFT 0
7308 /* HWRM Asynchronous Event Information */
7309 #define HWRM_ASYNC_EVENT_CMPL_TYPE_HWRM_ASYNC_EVENT UINT32_C(0x2e)
7310 #define HWRM_ASYNC_EVENT_CMPL_TYPE_LAST \
7311 HWRM_ASYNC_EVENT_CMPL_TYPE_HWRM_ASYNC_EVENT
7312 /* Identifiers of events. */
7314 /* Link status changed */
7315 #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_LINK_STATUS_CHANGE \
7317 /* Link MTU changed */
7318 #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_LINK_MTU_CHANGE \
7320 /* Link speed changed */
7321 #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_LINK_SPEED_CHANGE \
7323 /* DCB Configuration changed */
7324 #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_DCB_CONFIG_CHANGE \
7326 /* Port connection not allowed */
7327 #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_PORT_CONN_NOT_ALLOWED \
7329 /* Link speed configuration was not allowed */
7330 #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_LINK_SPEED_CFG_NOT_ALLOWED \
7332 /* Link speed configuration change */
7333 #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_LINK_SPEED_CFG_CHANGE \
7335 /* Port PHY configuration change */
7336 #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_PORT_PHY_CFG_CHANGE \
7338 /* Reset notification to clients */
7339 #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_RESET_NOTIFY \
7341 /* Master function selection event */
7342 #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_ERROR_RECOVERY \
7345 * An event signifying that a ring has been disabled by
7348 #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_RING_MONITOR_MSG \
7350 /* Function driver unloaded */
7351 #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_FUNC_DRVR_UNLOAD \
7353 /* Function driver loaded */
7354 #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_FUNC_DRVR_LOAD \
7356 /* Function FLR related processing has completed */
7357 #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_FUNC_FLR_PROC_CMPLT \
7359 /* PF driver unloaded */
7360 #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_PF_DRVR_UNLOAD \
7362 /* PF driver loaded */
7363 #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_PF_DRVR_LOAD \
7365 /* VF Function Level Reset (FLR) */
7366 #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_VF_FLR \
7368 /* VF MAC Address Change */
7369 #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_VF_MAC_ADDR_CHANGE \
7371 /* PF-VF communication channel status change. */
7372 #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_PF_VF_COMM_STATUS_CHANGE \
7374 /* VF Configuration Change */
7375 #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_VF_CFG_CHANGE \
7377 /* LLFC/PFC Configuration Change */
7378 #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_LLFC_PFC_CHANGE \
7380 /* Default VNIC Configuration Change */
7381 #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_DEFAULT_VNIC_CHANGE \
7384 #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_HW_FLOW_AGED \
7387 * A debug notification being posted to the driver. These
7388 * notifications are purely for diagnostic purpose and should not be
7389 * used for functional purpose. The driver is not supposed to act
7390 * on these messages except to log/record it.
7392 #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_DEBUG_NOTIFICATION \
7395 * An EEM flow cached memory flush for all flows request event being
7396 * posted to the PF driver.
7398 #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_EEM_CACHE_FLUSH_REQ \
7401 * An EEM flow cache memory flush completion event being posted to the
7402 * firmware by the PF driver. This is indication that host EEM flush
7403 * has completed by the PF.
7405 #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_EEM_CACHE_FLUSH_DONE \
7408 * A tcp flag action change event being posted to the PF or trusted VF
7409 * driver by the firmware. The PF or trusted VF driver should query
7410 * the firmware for the new TCP flag action update after receiving
7413 #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_TCP_FLAG_ACTION_CHANGE \
7416 * An EEM flow active event being posted to the PF or trusted VF driver
7417 * by the firmware. The PF or trusted VF driver should update the
7418 * flow's aging timer after receiving this async event.
7420 #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_EEM_FLOW_ACTIVE \
7423 * A eem cfg change event being posted to the trusted VF driver by the
7424 * firmware if the parent PF EEM configuration changed.
7426 #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_EEM_CFG_CHANGE \
7430 * TFLIB unique default VNIC Configuration Change
7432 #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_TFLIB_DEFAULT_VNIC_CHANGE \
7436 * TFLIB unique link status changed
7438 #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_TFLIB_LINK_STATUS_CHANGE \
7441 * An event signifying completion for HWRM_FW_STATE_QUIESCE
7442 * (completion, timeout, or error)
7444 #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_QUIESCE_DONE \
7447 * An event signifying a HWRM command is in progress and its
7448 * response will be deferred. This event is used on crypto controllers
7451 #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_DEFERRED_RESPONSE \
7454 * An event signifying that a PFC WatchDog configuration
7455 * has changed on any port / cos.
7457 #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_PFC_WATCHDOG_CFG_CHANGE \
7460 * An echo request from the firmware. An echo response is expected by
7463 #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_ECHO_REQUEST \
7465 /* Maximum Registrable event id. */
7466 #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_MAX_RGTR_EVENT_ID \
7469 * A trace log message. This contains firmware trace logs string
7470 * embedded in the asynchronous message. This is an experimental
7471 * event, not meant for production use at this time.
7473 #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_FW_TRACE_MSG \
7476 #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_HWRM_ERROR \
7478 #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_LAST \
7479 HWRM_ASYNC_EVENT_CMPL_EVENT_ID_HWRM_ERROR
7480 /* Event specific data */
7481 uint32_t event_data2;
7484 * This value is written by the NIC such that it will be different
7485 * for each pass through the completion queue. The even passes
7486 * will write 1. The odd passes will write 0.
7488 #define HWRM_ASYNC_EVENT_CMPL_V UINT32_C(0x1)
7490 #define HWRM_ASYNC_EVENT_CMPL_OPAQUE_MASK UINT32_C(0xfe)
7491 #define HWRM_ASYNC_EVENT_CMPL_OPAQUE_SFT 1
7492 /* 8-lsb timestamp from POR (100-msec resolution) */
7493 uint8_t timestamp_lo;
7494 /* 16-lsb timestamp from POR (100-msec resolution) */
7495 uint16_t timestamp_hi;
7496 /* Event specific data */
7497 uint32_t event_data1;
7500 /* hwrm_async_event_cmpl_link_status_change (size:128b/16B) */
7501 struct hwrm_async_event_cmpl_link_status_change {
7504 * This field indicates the exact type of the completion.
7505 * By convention, the LSB identifies the length of the
7506 * record in 16B units. Even values indicate 16B
7507 * records. Odd values indicate 32B
7510 #define HWRM_ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_TYPE_MASK \
7512 #define HWRM_ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_TYPE_SFT 0
7513 /* HWRM Asynchronous Event Information */
7514 #define HWRM_ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_TYPE_HWRM_ASYNC_EVENT \
7516 #define HWRM_ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_TYPE_LAST \
7517 HWRM_ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_TYPE_HWRM_ASYNC_EVENT
7518 /* Identifiers of events. */
7520 /* Link status changed */
7521 #define HWRM_ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_ID_LINK_STATUS_CHANGE \
7523 #define HWRM_ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_ID_LAST \
7524 HWRM_ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_ID_LINK_STATUS_CHANGE
7525 /* Event specific data */
7526 uint32_t event_data2;
7529 * This value is written by the NIC such that it will be different
7530 * for each pass through the completion queue. The even passes
7531 * will write 1. The odd passes will write 0.
7533 #define HWRM_ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_V \
7536 #define HWRM_ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_OPAQUE_MASK \
7538 #define HWRM_ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_OPAQUE_SFT 1
7539 /* 8-lsb timestamp from POR (100-msec resolution) */
7540 uint8_t timestamp_lo;
7541 /* 16-lsb timestamp from POR (100-msec resolution) */
7542 uint16_t timestamp_hi;
7543 /* Event specific data */
7544 uint32_t event_data1;
7545 /* Indicates link status change */
7546 #define HWRM_ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_DATA1_LINK_CHANGE \
7549 * If this bit set to 0, then it indicates that the link
7550 * was up and it went down.
7552 #define HWRM_ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_DATA1_LINK_CHANGE_DOWN \
7555 * If this bit is set to 1, then it indicates that the link
7556 * was down and it went up.
7558 #define HWRM_ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_DATA1_LINK_CHANGE_UP \
7560 #define HWRM_ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_DATA1_LINK_CHANGE_LAST \
7561 HWRM_ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_DATA1_LINK_CHANGE_UP
7562 /* Indicates the physical port this link status change occur */
7563 #define HWRM_ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_DATA1_PORT_MASK \
7565 #define HWRM_ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_DATA1_PORT_SFT \
7568 #define HWRM_ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_DATA1_PORT_ID_MASK \
7570 #define HWRM_ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_DATA1_PORT_ID_SFT \
7572 /* Indicates the physical function this event occurred on. */
7573 #define HWRM_ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_DATA1_PF_ID_MASK \
7575 #define HWRM_ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_DATA1_PF_ID_SFT \
7579 /* hwrm_async_event_cmpl_link_mtu_change (size:128b/16B) */
7580 struct hwrm_async_event_cmpl_link_mtu_change {
7583 * This field indicates the exact type of the completion.
7584 * By convention, the LSB identifies the length of the
7585 * record in 16B units. Even values indicate 16B
7586 * records. Odd values indicate 32B
7589 #define HWRM_ASYNC_EVENT_CMPL_LINK_MTU_CHANGE_TYPE_MASK \
7591 #define HWRM_ASYNC_EVENT_CMPL_LINK_MTU_CHANGE_TYPE_SFT 0
7592 /* HWRM Asynchronous Event Information */
7593 #define HWRM_ASYNC_EVENT_CMPL_LINK_MTU_CHANGE_TYPE_HWRM_ASYNC_EVENT \
7595 #define HWRM_ASYNC_EVENT_CMPL_LINK_MTU_CHANGE_TYPE_LAST \
7596 HWRM_ASYNC_EVENT_CMPL_LINK_MTU_CHANGE_TYPE_HWRM_ASYNC_EVENT
7597 /* Identifiers of events. */
7599 /* Link MTU changed */
7600 #define HWRM_ASYNC_EVENT_CMPL_LINK_MTU_CHANGE_EVENT_ID_LINK_MTU_CHANGE \
7602 #define HWRM_ASYNC_EVENT_CMPL_LINK_MTU_CHANGE_EVENT_ID_LAST \
7603 HWRM_ASYNC_EVENT_CMPL_LINK_MTU_CHANGE_EVENT_ID_LINK_MTU_CHANGE
7604 /* Event specific data */
7605 uint32_t event_data2;
7608 * This value is written by the NIC such that it will be different
7609 * for each pass through the completion queue. The even passes
7610 * will write 1. The odd passes will write 0.
7612 #define HWRM_ASYNC_EVENT_CMPL_LINK_MTU_CHANGE_V UINT32_C(0x1)
7614 #define HWRM_ASYNC_EVENT_CMPL_LINK_MTU_CHANGE_OPAQUE_MASK \
7616 #define HWRM_ASYNC_EVENT_CMPL_LINK_MTU_CHANGE_OPAQUE_SFT 1
7617 /* 8-lsb timestamp from POR (100-msec resolution) */
7618 uint8_t timestamp_lo;
7619 /* 16-lsb timestamp from POR (100-msec resolution) */
7620 uint16_t timestamp_hi;
7621 /* Event specific data */
7622 uint32_t event_data1;
7623 /* The new MTU of the link in bytes. */
7624 #define HWRM_ASYNC_EVENT_CMPL_LINK_MTU_CHANGE_EVENT_DATA1_NEW_MTU_MASK \
7626 #define HWRM_ASYNC_EVENT_CMPL_LINK_MTU_CHANGE_EVENT_DATA1_NEW_MTU_SFT 0
7629 /* hwrm_async_event_cmpl_link_speed_change (size:128b/16B) */
7630 struct hwrm_async_event_cmpl_link_speed_change {
7633 * This field indicates the exact type of the completion.
7634 * By convention, the LSB identifies the length of the
7635 * record in 16B units. Even values indicate 16B
7636 * records. Odd values indicate 32B
7639 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_TYPE_MASK \
7641 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_TYPE_SFT 0
7642 /* HWRM Asynchronous Event Information */
7643 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_TYPE_HWRM_ASYNC_EVENT \
7645 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_TYPE_LAST \
7646 HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_TYPE_HWRM_ASYNC_EVENT
7647 /* Identifiers of events. */
7649 /* Link speed changed */
7650 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_EVENT_ID_LINK_SPEED_CHANGE \
7652 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_EVENT_ID_LAST \
7653 HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_EVENT_ID_LINK_SPEED_CHANGE
7654 /* Event specific data */
7655 uint32_t event_data2;
7658 * This value is written by the NIC such that it will be different
7659 * for each pass through the completion queue. The even passes
7660 * will write 1. The odd passes will write 0.
7662 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_V \
7665 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_OPAQUE_MASK \
7667 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_OPAQUE_SFT 1
7668 /* 8-lsb timestamp from POR (100-msec resolution) */
7669 uint8_t timestamp_lo;
7670 /* 16-lsb timestamp from POR (100-msec resolution) */
7671 uint16_t timestamp_hi;
7672 /* Event specific data */
7673 uint32_t event_data1;
7675 * When this bit is '1', the link was forced to the
7676 * force_link_speed value.
7678 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_EVENT_DATA1_FORCE \
7680 /* The new link speed in 100 Mbps units. */
7681 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_EVENT_DATA1_NEW_LINK_SPEED_100MBPS_MASK \
7683 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_EVENT_DATA1_NEW_LINK_SPEED_100MBPS_SFT \
7685 /* 100Mb link speed */
7686 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_EVENT_DATA1_NEW_LINK_SPEED_100MBPS_100MB \
7687 (UINT32_C(0x1) << 1)
7688 /* 1Gb link speed */
7689 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_EVENT_DATA1_NEW_LINK_SPEED_100MBPS_1GB \
7690 (UINT32_C(0xa) << 1)
7691 /* 2Gb link speed */
7692 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_EVENT_DATA1_NEW_LINK_SPEED_100MBPS_2GB \
7693 (UINT32_C(0x14) << 1)
7694 /* 25Gb link speed */
7695 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_EVENT_DATA1_NEW_LINK_SPEED_100MBPS_2_5GB \
7696 (UINT32_C(0x19) << 1)
7697 /* 10Gb link speed */
7698 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_EVENT_DATA1_NEW_LINK_SPEED_100MBPS_10GB \
7699 (UINT32_C(0x64) << 1)
7700 /* 20Mb link speed */
7701 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_EVENT_DATA1_NEW_LINK_SPEED_100MBPS_20GB \
7702 (UINT32_C(0xc8) << 1)
7703 /* 25Gb link speed */
7704 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_EVENT_DATA1_NEW_LINK_SPEED_100MBPS_25GB \
7705 (UINT32_C(0xfa) << 1)
7706 /* 40Gb link speed */
7707 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_EVENT_DATA1_NEW_LINK_SPEED_100MBPS_40GB \
7708 (UINT32_C(0x190) << 1)
7709 /* 50Gb link speed */
7710 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_EVENT_DATA1_NEW_LINK_SPEED_100MBPS_50GB \
7711 (UINT32_C(0x1f4) << 1)
7712 /* 100Gb link speed */
7713 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_EVENT_DATA1_NEW_LINK_SPEED_100MBPS_100GB \
7714 (UINT32_C(0x3e8) << 1)
7715 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_EVENT_DATA1_NEW_LINK_SPEED_100MBPS_LAST \
7716 HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_EVENT_DATA1_NEW_LINK_SPEED_100MBPS_100GB
7718 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_EVENT_DATA1_PORT_ID_MASK \
7719 UINT32_C(0xffff0000)
7720 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_EVENT_DATA1_PORT_ID_SFT \
7724 /* hwrm_async_event_cmpl_dcb_config_change (size:128b/16B) */
7725 struct hwrm_async_event_cmpl_dcb_config_change {
7728 * This field indicates the exact type of the completion.
7729 * By convention, the LSB identifies the length of the
7730 * record in 16B units. Even values indicate 16B
7731 * records. Odd values indicate 32B
7734 #define HWRM_ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_TYPE_MASK \
7736 #define HWRM_ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_TYPE_SFT 0
7737 /* HWRM Asynchronous Event Information */
7738 #define HWRM_ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_TYPE_HWRM_ASYNC_EVENT \
7740 #define HWRM_ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_TYPE_LAST \
7741 HWRM_ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_TYPE_HWRM_ASYNC_EVENT
7742 /* Identifiers of events. */
7744 /* DCB Configuration changed */
7745 #define HWRM_ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_EVENT_ID_DCB_CONFIG_CHANGE \
7747 #define HWRM_ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_EVENT_ID_LAST \
7748 HWRM_ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_EVENT_ID_DCB_CONFIG_CHANGE
7749 /* Event specific data */
7750 uint32_t event_data2;
7751 /* ETS configuration change */
7752 #define HWRM_ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_EVENT_DATA2_ETS \
7754 /* PFC configuration change */
7755 #define HWRM_ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_EVENT_DATA2_PFC \
7757 /* APP configuration change */
7758 #define HWRM_ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_EVENT_DATA2_APP \
7762 * This value is written by the NIC such that it will be different
7763 * for each pass through the completion queue. The even passes
7764 * will write 1. The odd passes will write 0.
7766 #define HWRM_ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_V \
7769 #define HWRM_ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_OPAQUE_MASK \
7771 #define HWRM_ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_OPAQUE_SFT 1
7772 /* 8-lsb timestamp from POR (100-msec resolution) */
7773 uint8_t timestamp_lo;
7774 /* 16-lsb timestamp from POR (100-msec resolution) */
7775 uint16_t timestamp_hi;
7776 /* Event specific data */
7777 uint32_t event_data1;
7779 #define HWRM_ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_EVENT_DATA1_PORT_ID_MASK \
7781 #define HWRM_ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_EVENT_DATA1_PORT_ID_SFT \
7783 /* Priority recommended for RoCE traffic */
7784 #define HWRM_ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_EVENT_DATA1_RECOMMEND_ROCE_PRIORITY_MASK \
7786 #define HWRM_ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_EVENT_DATA1_RECOMMEND_ROCE_PRIORITY_SFT \
7789 #define HWRM_ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_EVENT_DATA1_RECOMMEND_ROCE_PRIORITY_NONE \
7790 (UINT32_C(0xff) << 16)
7791 #define HWRM_ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_EVENT_DATA1_RECOMMEND_ROCE_PRIORITY_LAST \
7792 HWRM_ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_EVENT_DATA1_RECOMMEND_ROCE_PRIORITY_NONE
7793 /* Priority recommended for L2 traffic */
7794 #define HWRM_ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_EVENT_DATA1_RECOMMEND_L2_PRIORITY_MASK \
7795 UINT32_C(0xff000000)
7796 #define HWRM_ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_EVENT_DATA1_RECOMMEND_L2_PRIORITY_SFT \
7799 #define HWRM_ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_EVENT_DATA1_RECOMMEND_L2_PRIORITY_NONE \
7800 (UINT32_C(0xff) << 24)
7801 #define HWRM_ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_EVENT_DATA1_RECOMMEND_L2_PRIORITY_LAST \
7802 HWRM_ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_EVENT_DATA1_RECOMMEND_L2_PRIORITY_NONE
7805 /* hwrm_async_event_cmpl_port_conn_not_allowed (size:128b/16B) */
7806 struct hwrm_async_event_cmpl_port_conn_not_allowed {
7809 * This field indicates the exact type of the completion.
7810 * By convention, the LSB identifies the length of the
7811 * record in 16B units. Even values indicate 16B
7812 * records. Odd values indicate 32B
7815 #define HWRM_ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_TYPE_MASK \
7817 #define HWRM_ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_TYPE_SFT \
7819 /* HWRM Asynchronous Event Information */
7820 #define HWRM_ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_TYPE_HWRM_ASYNC_EVENT \
7822 #define HWRM_ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_TYPE_LAST \
7823 HWRM_ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_TYPE_HWRM_ASYNC_EVENT
7824 /* Identifiers of events. */
7826 /* Port connection not allowed */
7827 #define HWRM_ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_ID_PORT_CONN_NOT_ALLOWED \
7829 #define HWRM_ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_ID_LAST \
7830 HWRM_ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_ID_PORT_CONN_NOT_ALLOWED
7831 /* Event specific data */
7832 uint32_t event_data2;
7835 * This value is written by the NIC such that it will be different
7836 * for each pass through the completion queue. The even passes
7837 * will write 1. The odd passes will write 0.
7839 #define HWRM_ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_V \
7842 #define HWRM_ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_OPAQUE_MASK \
7844 #define HWRM_ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_OPAQUE_SFT 1
7845 /* 8-lsb timestamp from POR (100-msec resolution) */
7846 uint8_t timestamp_lo;
7847 /* 16-lsb timestamp from POR (100-msec resolution) */
7848 uint16_t timestamp_hi;
7849 /* Event specific data */
7850 uint32_t event_data1;
7852 #define HWRM_ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_PORT_ID_MASK \
7854 #define HWRM_ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_PORT_ID_SFT \
7857 * This value indicates the current port level enforcement policy
7858 * for the optics module when there is an optical module mismatch
7859 * and port is not connected.
7861 #define HWRM_ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_ENFORCEMENT_POLICY_MASK \
7863 #define HWRM_ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_ENFORCEMENT_POLICY_SFT \
7865 /* No enforcement */
7866 #define HWRM_ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_ENFORCEMENT_POLICY_NONE \
7867 (UINT32_C(0x0) << 16)
7868 /* Disable Transmit side Laser. */
7869 #define HWRM_ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_ENFORCEMENT_POLICY_DISABLETX \
7870 (UINT32_C(0x1) << 16)
7871 /* Raise a warning message. */
7872 #define HWRM_ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_ENFORCEMENT_POLICY_WARNINGMSG \
7873 (UINT32_C(0x2) << 16)
7874 /* Power down the module. */
7875 #define HWRM_ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_ENFORCEMENT_POLICY_PWRDOWN \
7876 (UINT32_C(0x3) << 16)
7877 #define HWRM_ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_ENFORCEMENT_POLICY_LAST \
7878 HWRM_ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_ENFORCEMENT_POLICY_PWRDOWN
7881 /* hwrm_async_event_cmpl_link_speed_cfg_not_allowed (size:128b/16B) */
7882 struct hwrm_async_event_cmpl_link_speed_cfg_not_allowed {
7885 * This field indicates the exact type of the completion.
7886 * By convention, the LSB identifies the length of the
7887 * record in 16B units. Even values indicate 16B
7888 * records. Odd values indicate 32B
7891 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_NOT_ALLOWED_TYPE_MASK \
7893 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_NOT_ALLOWED_TYPE_SFT \
7895 /* HWRM Asynchronous Event Information */
7896 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_NOT_ALLOWED_TYPE_HWRM_ASYNC_EVENT \
7898 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_NOT_ALLOWED_TYPE_LAST \
7899 HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_NOT_ALLOWED_TYPE_HWRM_ASYNC_EVENT
7900 /* Identifiers of events. */
7902 /* Link speed configuration was not allowed */
7903 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_NOT_ALLOWED_EVENT_ID_LINK_SPEED_CFG_NOT_ALLOWED \
7905 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_NOT_ALLOWED_EVENT_ID_LAST \
7906 HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_NOT_ALLOWED_EVENT_ID_LINK_SPEED_CFG_NOT_ALLOWED
7907 /* Event specific data */
7908 uint32_t event_data2;
7911 * This value is written by the NIC such that it will be different
7912 * for each pass through the completion queue. The even passes
7913 * will write 1. The odd passes will write 0.
7915 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_NOT_ALLOWED_V \
7918 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_NOT_ALLOWED_OPAQUE_MASK \
7920 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_NOT_ALLOWED_OPAQUE_SFT 1
7921 /* 8-lsb timestamp from POR (100-msec resolution) */
7922 uint8_t timestamp_lo;
7923 /* 16-lsb timestamp from POR (100-msec resolution) */
7924 uint16_t timestamp_hi;
7925 /* Event specific data */
7926 uint32_t event_data1;
7928 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_NOT_ALLOWED_EVENT_DATA1_PORT_ID_MASK \
7930 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_NOT_ALLOWED_EVENT_DATA1_PORT_ID_SFT \
7934 /* hwrm_async_event_cmpl_link_speed_cfg_change (size:128b/16B) */
7935 struct hwrm_async_event_cmpl_link_speed_cfg_change {
7938 * This field indicates the exact type of the completion.
7939 * By convention, the LSB identifies the length of the
7940 * record in 16B units. Even values indicate 16B
7941 * records. Odd values indicate 32B
7944 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_TYPE_MASK \
7946 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_TYPE_SFT \
7948 /* HWRM Asynchronous Event Information */
7949 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_TYPE_HWRM_ASYNC_EVENT \
7951 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_TYPE_LAST \
7952 HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_TYPE_HWRM_ASYNC_EVENT
7953 /* Identifiers of events. */
7955 /* Link speed configuration change */
7956 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_EVENT_ID_LINK_SPEED_CFG_CHANGE \
7958 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_EVENT_ID_LAST \
7959 HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_EVENT_ID_LINK_SPEED_CFG_CHANGE
7960 /* Event specific data */
7961 uint32_t event_data2;
7964 * This value is written by the NIC such that it will be different
7965 * for each pass through the completion queue. The even passes
7966 * will write 1. The odd passes will write 0.
7968 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_V \
7971 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_OPAQUE_MASK \
7973 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_OPAQUE_SFT 1
7974 /* 8-lsb timestamp from POR (100-msec resolution) */
7975 uint8_t timestamp_lo;
7976 /* 16-lsb timestamp from POR (100-msec resolution) */
7977 uint16_t timestamp_hi;
7978 /* Event specific data */
7979 uint32_t event_data1;
7981 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_EVENT_DATA1_PORT_ID_MASK \
7983 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_EVENT_DATA1_PORT_ID_SFT \
7986 * If set to 1, it indicates that the supported link speeds
7987 * configuration on the port has changed.
7988 * If set to 0, then there is no change in supported link speeds
7991 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_EVENT_DATA1_SUPPORTED_LINK_SPEEDS_CHANGE \
7994 * If set to 1, it indicates that the link speed configuration
7995 * on the port has become illegal or invalid.
7996 * If set to 0, then the link speed configuration on the port is
7999 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_EVENT_DATA1_ILLEGAL_LINK_SPEED_CFG \
8003 /* hwrm_async_event_cmpl_port_phy_cfg_change (size:128b/16B) */
8004 struct hwrm_async_event_cmpl_port_phy_cfg_change {
8007 * This field indicates the exact type of the completion.
8008 * By convention, the LSB identifies the length of the
8009 * record in 16B units. Even values indicate 16B
8010 * records. Odd values indicate 32B
8013 #define HWRM_ASYNC_EVENT_CMPL_PORT_PHY_CFG_CHANGE_TYPE_MASK \
8015 #define HWRM_ASYNC_EVENT_CMPL_PORT_PHY_CFG_CHANGE_TYPE_SFT \
8017 /* HWRM Asynchronous Event Information */
8018 #define HWRM_ASYNC_EVENT_CMPL_PORT_PHY_CFG_CHANGE_TYPE_HWRM_ASYNC_EVENT \
8020 #define HWRM_ASYNC_EVENT_CMPL_PORT_PHY_CFG_CHANGE_TYPE_LAST \
8021 HWRM_ASYNC_EVENT_CMPL_PORT_PHY_CFG_CHANGE_TYPE_HWRM_ASYNC_EVENT
8022 /* Identifiers of events. */
8024 /* Port PHY configuration change */
8025 #define HWRM_ASYNC_EVENT_CMPL_PORT_PHY_CFG_CHANGE_EVENT_ID_PORT_PHY_CFG_CHANGE \
8027 #define HWRM_ASYNC_EVENT_CMPL_PORT_PHY_CFG_CHANGE_EVENT_ID_LAST \
8028 HWRM_ASYNC_EVENT_CMPL_PORT_PHY_CFG_CHANGE_EVENT_ID_PORT_PHY_CFG_CHANGE
8029 /* Event specific data */
8030 uint32_t event_data2;
8033 * This value is written by the NIC such that it will be different
8034 * for each pass through the completion queue. The even passes
8035 * will write 1. The odd passes will write 0.
8037 #define HWRM_ASYNC_EVENT_CMPL_PORT_PHY_CFG_CHANGE_V \
8040 #define HWRM_ASYNC_EVENT_CMPL_PORT_PHY_CFG_CHANGE_OPAQUE_MASK \
8042 #define HWRM_ASYNC_EVENT_CMPL_PORT_PHY_CFG_CHANGE_OPAQUE_SFT 1
8043 /* 8-lsb timestamp from POR (100-msec resolution) */
8044 uint8_t timestamp_lo;
8045 /* 16-lsb timestamp from POR (100-msec resolution) */
8046 uint16_t timestamp_hi;
8047 /* Event specific data */
8048 uint32_t event_data1;
8050 #define HWRM_ASYNC_EVENT_CMPL_PORT_PHY_CFG_CHANGE_EVENT_DATA1_PORT_ID_MASK \
8052 #define HWRM_ASYNC_EVENT_CMPL_PORT_PHY_CFG_CHANGE_EVENT_DATA1_PORT_ID_SFT \
8055 * If set to 1, it indicates that the FEC
8056 * configuration on the port has changed.
8057 * If set to 0, then there is no change in FEC configuration.
8059 #define HWRM_ASYNC_EVENT_CMPL_PORT_PHY_CFG_CHANGE_EVENT_DATA1_FEC_CFG_CHANGE \
8062 * If set to 1, it indicates that the EEE configuration
8063 * on the port has changed.
8064 * If set to 0, then there is no change in EEE configuration
8067 #define HWRM_ASYNC_EVENT_CMPL_PORT_PHY_CFG_CHANGE_EVENT_DATA1_EEE_CFG_CHANGE \
8070 * If set to 1, it indicates that the pause configuration
8071 * on the PHY has changed.
8072 * If set to 0, then there is no change in the pause
8073 * configuration on the PHY.
8075 #define HWRM_ASYNC_EVENT_CMPL_PORT_PHY_CFG_CHANGE_EVENT_DATA1_PAUSE_CFG_CHANGE \
8079 /* hwrm_async_event_cmpl_reset_notify (size:128b/16B) */
8080 struct hwrm_async_event_cmpl_reset_notify {
8083 * This field indicates the exact type of the completion.
8084 * By convention, the LSB identifies the length of the
8085 * record in 16B units. Even values indicate 16B
8086 * records. Odd values indicate 32B
8089 #define HWRM_ASYNC_EVENT_CMPL_RESET_NOTIFY_TYPE_MASK \
8091 #define HWRM_ASYNC_EVENT_CMPL_RESET_NOTIFY_TYPE_SFT 0
8092 /* HWRM Asynchronous Event Information */
8093 #define HWRM_ASYNC_EVENT_CMPL_RESET_NOTIFY_TYPE_HWRM_ASYNC_EVENT \
8095 #define HWRM_ASYNC_EVENT_CMPL_RESET_NOTIFY_TYPE_LAST \
8096 HWRM_ASYNC_EVENT_CMPL_RESET_NOTIFY_TYPE_HWRM_ASYNC_EVENT
8097 /* Identifiers of events. */
8099 /* Notify clients of imminent reset. */
8100 #define HWRM_ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_ID_RESET_NOTIFY \
8102 #define HWRM_ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_ID_LAST \
8103 HWRM_ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_ID_RESET_NOTIFY
8104 /* Event specific data. The data is for internal debug use only. */
8105 uint32_t event_data2;
8107 * These bits indicate the status as being reported by the firmware.
8108 * This value is exactly the same as status code in fw_status register.
8109 * If the status code is equal to 0x8000, then the reset is initiated
8110 * by the Host using the FW_RESET command when the FW is in a healthy
8111 * state. If the status code is not equal to 0x8000, then the reset is
8112 * initiated by the FW to recover from the error or FATAL state.
8114 #define HWRM_ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA2_FW_STATUS_CODE_MASK \
8116 #define HWRM_ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA2_FW_STATUS_CODE_SFT \
8120 * This value is written by the NIC such that it will be different
8121 * for each pass through the completion queue. The even passes
8122 * will write 1. The odd passes will write 0.
8124 #define HWRM_ASYNC_EVENT_CMPL_RESET_NOTIFY_V UINT32_C(0x1)
8126 #define HWRM_ASYNC_EVENT_CMPL_RESET_NOTIFY_OPAQUE_MASK UINT32_C(0xfe)
8127 #define HWRM_ASYNC_EVENT_CMPL_RESET_NOTIFY_OPAQUE_SFT 1
8129 * 8-lsb timestamp (100-msec resolution)
8130 * The Minimum time required for the Firmware readiness after sending this
8131 * notification to the driver instances.
8133 uint8_t timestamp_lo;
8135 * 16-lsb timestamp (100-msec resolution)
8136 * The Maximum Firmware Reset bail out value in the order of 100
8137 * milli seconds. The driver instances will use this value to re-initiate the
8138 * registration process again if the core firmware didn’t set the ready
8141 uint16_t timestamp_hi;
8142 /* Event specific data */
8143 uint32_t event_data1;
8144 /* Indicates driver action requested */
8145 #define HWRM_ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_DRIVER_ACTION_MASK \
8147 #define HWRM_ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_DRIVER_ACTION_SFT \
8150 * If set to 1, it indicates that the l2 client should
8151 * stop sending in band traffic to Nitro.
8152 * if set to 0, there is no change in L2 client behavior.
8154 #define HWRM_ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_DRIVER_ACTION_DRIVER_STOP_TX_QUEUE \
8157 * If set to 1, it indicates that the L2 client should
8158 * bring down the interface.
8159 * If set to 0, then there is no change in L2 client behavior.
8161 #define HWRM_ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_DRIVER_ACTION_DRIVER_IFDOWN \
8163 #define HWRM_ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_DRIVER_ACTION_LAST \
8164 HWRM_ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_DRIVER_ACTION_DRIVER_IFDOWN
8165 /* Indicates reason for reset. */
8166 #define HWRM_ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_REASON_CODE_MASK \
8168 #define HWRM_ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_REASON_CODE_SFT \
8170 /* A management client has requested reset. */
8171 #define HWRM_ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_REASON_CODE_MANAGEMENT_RESET_REQUEST \
8172 (UINT32_C(0x1) << 8)
8173 /* A fatal firmware exception has occurred. */
8174 #define HWRM_ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_REASON_CODE_FW_EXCEPTION_FATAL \
8175 (UINT32_C(0x2) << 8)
8176 /* A non-fatal firmware exception has occurred. */
8177 #define HWRM_ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_REASON_CODE_FW_EXCEPTION_NON_FATAL \
8178 (UINT32_C(0x3) << 8)
8180 #define HWRM_ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_REASON_CODE_FAST_RESET \
8181 (UINT32_C(0x4) << 8)
8182 #define HWRM_ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_REASON_CODE_LAST \
8183 HWRM_ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_REASON_CODE_FAST_RESET
8185 * Minimum time before driver should attempt access - units 100ms ticks.
8188 #define HWRM_ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_DELAY_IN_100MS_TICKS_MASK \
8189 UINT32_C(0xffff0000)
8190 #define HWRM_ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_DELAY_IN_100MS_TICKS_SFT \
8194 /* hwrm_async_event_cmpl_error_recovery (size:128b/16B) */
8195 struct hwrm_async_event_cmpl_error_recovery {
8198 * This field indicates the exact type of the completion.
8199 * By convention, the LSB identifies the length of the
8200 * record in 16B units. Even values indicate 16B
8201 * records. Odd values indicate 32B
8204 #define HWRM_ASYNC_EVENT_CMPL_ERROR_RECOVERY_TYPE_MASK \
8206 #define HWRM_ASYNC_EVENT_CMPL_ERROR_RECOVERY_TYPE_SFT 0
8207 /* HWRM Asynchronous Event Information */
8208 #define HWRM_ASYNC_EVENT_CMPL_ERROR_RECOVERY_TYPE_HWRM_ASYNC_EVENT \
8210 #define HWRM_ASYNC_EVENT_CMPL_ERROR_RECOVERY_TYPE_LAST \
8211 HWRM_ASYNC_EVENT_CMPL_ERROR_RECOVERY_TYPE_HWRM_ASYNC_EVENT
8212 /* Identifiers of events. */
8215 * This async notification message can be used for selecting or
8216 * deselecting master function for error recovery,
8217 * and to communicate to all the functions whether error recovery
8218 * was enabled/disabled.
8220 #define HWRM_ASYNC_EVENT_CMPL_ERROR_RECOVERY_EVENT_ID_ERROR_RECOVERY \
8222 #define HWRM_ASYNC_EVENT_CMPL_ERROR_RECOVERY_EVENT_ID_LAST \
8223 HWRM_ASYNC_EVENT_CMPL_ERROR_RECOVERY_EVENT_ID_ERROR_RECOVERY
8224 /* Event specific data */
8225 uint32_t event_data2;
8228 * This value is written by the NIC such that it will be different
8229 * for each pass through the completion queue. The even passes
8230 * will write 1. The odd passes will write 0.
8232 #define HWRM_ASYNC_EVENT_CMPL_ERROR_RECOVERY_V UINT32_C(0x1)
8234 #define HWRM_ASYNC_EVENT_CMPL_ERROR_RECOVERY_OPAQUE_MASK UINT32_C(0xfe)
8235 #define HWRM_ASYNC_EVENT_CMPL_ERROR_RECOVERY_OPAQUE_SFT 1
8236 /* 8-lsb timestamp (100-msec resolution) */
8237 uint8_t timestamp_lo;
8238 /* 16-lsb timestamp (100-msec resolution) */
8239 uint16_t timestamp_hi;
8240 /* Event specific data */
8241 uint32_t event_data1;
8242 /* Indicates driver action requested */
8243 #define HWRM_ASYNC_EVENT_CMPL_ERROR_RECOVERY_EVENT_DATA1_FLAGS_MASK \
8245 #define HWRM_ASYNC_EVENT_CMPL_ERROR_RECOVERY_EVENT_DATA1_FLAGS_SFT \
8248 * If set to 1, this function is selected as Master function.
8249 * This function has responsibility to do 'chip reset' when it
8250 * detects a fatal error. If set to 0, master function functionality
8251 * is disabled on this function.
8253 #define HWRM_ASYNC_EVENT_CMPL_ERROR_RECOVERY_EVENT_DATA1_FLAGS_MASTER_FUNC \
8256 * If set to 1, error recovery is enabled.
8257 * If set to 0, error recovery is disabled.
8259 #define HWRM_ASYNC_EVENT_CMPL_ERROR_RECOVERY_EVENT_DATA1_FLAGS_RECOVERY_ENABLED \
8263 /* hwrm_async_event_cmpl_ring_monitor_msg (size:128b/16B) */
8264 struct hwrm_async_event_cmpl_ring_monitor_msg {
8267 * This field indicates the exact type of the completion.
8268 * By convention, the LSB identifies the length of the
8269 * record in 16B units. Even values indicate 16B
8270 * records. Odd values indicate 32B
8273 #define HWRM_ASYNC_EVENT_CMPL_RING_MONITOR_MSG_TYPE_MASK \
8275 #define HWRM_ASYNC_EVENT_CMPL_RING_MONITOR_MSG_TYPE_SFT 0
8276 /* HWRM Asynchronous Event Information */
8277 #define HWRM_ASYNC_EVENT_CMPL_RING_MONITOR_MSG_TYPE_HWRM_ASYNC_EVENT \
8279 #define HWRM_ASYNC_EVENT_CMPL_RING_MONITOR_MSG_TYPE_LAST \
8280 HWRM_ASYNC_EVENT_CMPL_RING_MONITOR_MSG_TYPE_HWRM_ASYNC_EVENT
8281 /* Identifiers of events. */
8283 /* Ring Monitor Message. */
8284 #define HWRM_ASYNC_EVENT_CMPL_RING_MONITOR_MSG_EVENT_ID_RING_MONITOR_MSG \
8286 #define HWRM_ASYNC_EVENT_CMPL_RING_MONITOR_MSG_EVENT_ID_LAST \
8287 HWRM_ASYNC_EVENT_CMPL_RING_MONITOR_MSG_EVENT_ID_RING_MONITOR_MSG
8288 /* Event specific data */
8289 uint32_t event_data2;
8290 /* Type of Ring disabled. */
8291 #define HWRM_ASYNC_EVENT_CMPL_RING_MONITOR_MSG_EVENT_DATA2_DISABLE_RING_TYPE_MASK \
8293 #define HWRM_ASYNC_EVENT_CMPL_RING_MONITOR_MSG_EVENT_DATA2_DISABLE_RING_TYPE_SFT \
8295 /* tx ring disabled. */
8296 #define HWRM_ASYNC_EVENT_CMPL_RING_MONITOR_MSG_EVENT_DATA2_DISABLE_RING_TYPE_TX \
8298 /* rx ring disabled. */
8299 #define HWRM_ASYNC_EVENT_CMPL_RING_MONITOR_MSG_EVENT_DATA2_DISABLE_RING_TYPE_RX \
8301 /* cmpl ring disabled. */
8302 #define HWRM_ASYNC_EVENT_CMPL_RING_MONITOR_MSG_EVENT_DATA2_DISABLE_RING_TYPE_CMPL \
8304 #define HWRM_ASYNC_EVENT_CMPL_RING_MONITOR_MSG_EVENT_DATA2_DISABLE_RING_TYPE_LAST \
8305 HWRM_ASYNC_EVENT_CMPL_RING_MONITOR_MSG_EVENT_DATA2_DISABLE_RING_TYPE_CMPL
8308 * This value is written by the NIC such that it will be different
8309 * for each pass through the completion queue. The even passes
8310 * will write 1. The odd passes will write 0.
8312 #define HWRM_ASYNC_EVENT_CMPL_RING_MONITOR_MSG_V UINT32_C(0x1)
8314 #define HWRM_ASYNC_EVENT_CMPL_RING_MONITOR_MSG_OPAQUE_MASK \
8316 #define HWRM_ASYNC_EVENT_CMPL_RING_MONITOR_MSG_OPAQUE_SFT 1
8317 /* 8-lsb timestamp from POR (100-msec resolution) */
8318 uint8_t timestamp_lo;
8319 /* 16-lsb timestamp from POR (100-msec resolution) */
8320 uint16_t timestamp_hi;
8322 * Event specific data. If ring_type_disabled indicates a tx,rx or cmpl
8323 * then this field will indicate the ring id.
8325 uint32_t event_data1;
8328 /* hwrm_async_event_cmpl_func_drvr_unload (size:128b/16B) */
8329 struct hwrm_async_event_cmpl_func_drvr_unload {
8332 * This field indicates the exact type of the completion.
8333 * By convention, the LSB identifies the length of the
8334 * record in 16B units. Even values indicate 16B
8335 * records. Odd values indicate 32B
8338 #define HWRM_ASYNC_EVENT_CMPL_FUNC_DRVR_UNLOAD_TYPE_MASK \
8340 #define HWRM_ASYNC_EVENT_CMPL_FUNC_DRVR_UNLOAD_TYPE_SFT 0
8341 /* HWRM Asynchronous Event Information */
8342 #define HWRM_ASYNC_EVENT_CMPL_FUNC_DRVR_UNLOAD_TYPE_HWRM_ASYNC_EVENT \
8344 #define HWRM_ASYNC_EVENT_CMPL_FUNC_DRVR_UNLOAD_TYPE_LAST \
8345 HWRM_ASYNC_EVENT_CMPL_FUNC_DRVR_UNLOAD_TYPE_HWRM_ASYNC_EVENT
8346 /* Identifiers of events. */
8348 /* Function driver unloaded */
8349 #define HWRM_ASYNC_EVENT_CMPL_FUNC_DRVR_UNLOAD_EVENT_ID_FUNC_DRVR_UNLOAD \
8351 #define HWRM_ASYNC_EVENT_CMPL_FUNC_DRVR_UNLOAD_EVENT_ID_LAST \
8352 HWRM_ASYNC_EVENT_CMPL_FUNC_DRVR_UNLOAD_EVENT_ID_FUNC_DRVR_UNLOAD
8353 /* Event specific data */
8354 uint32_t event_data2;
8357 * This value is written by the NIC such that it will be different
8358 * for each pass through the completion queue. The even passes
8359 * will write 1. The odd passes will write 0.
8361 #define HWRM_ASYNC_EVENT_CMPL_FUNC_DRVR_UNLOAD_V UINT32_C(0x1)
8363 #define HWRM_ASYNC_EVENT_CMPL_FUNC_DRVR_UNLOAD_OPAQUE_MASK \
8365 #define HWRM_ASYNC_EVENT_CMPL_FUNC_DRVR_UNLOAD_OPAQUE_SFT 1
8366 /* 8-lsb timestamp from POR (100-msec resolution) */
8367 uint8_t timestamp_lo;
8368 /* 16-lsb timestamp from POR (100-msec resolution) */
8369 uint16_t timestamp_hi;
8370 /* Event specific data */
8371 uint32_t event_data1;
8373 #define HWRM_ASYNC_EVENT_CMPL_FUNC_DRVR_UNLOAD_EVENT_DATA1_FUNC_ID_MASK \
8375 #define HWRM_ASYNC_EVENT_CMPL_FUNC_DRVR_UNLOAD_EVENT_DATA1_FUNC_ID_SFT \
8379 /* hwrm_async_event_cmpl_func_drvr_load (size:128b/16B) */
8380 struct hwrm_async_event_cmpl_func_drvr_load {
8383 * This field indicates the exact type of the completion.
8384 * By convention, the LSB identifies the length of the
8385 * record in 16B units. Even values indicate 16B
8386 * records. Odd values indicate 32B
8389 #define HWRM_ASYNC_EVENT_CMPL_FUNC_DRVR_LOAD_TYPE_MASK \
8391 #define HWRM_ASYNC_EVENT_CMPL_FUNC_DRVR_LOAD_TYPE_SFT 0
8392 /* HWRM Asynchronous Event Information */
8393 #define HWRM_ASYNC_EVENT_CMPL_FUNC_DRVR_LOAD_TYPE_HWRM_ASYNC_EVENT \
8395 #define HWRM_ASYNC_EVENT_CMPL_FUNC_DRVR_LOAD_TYPE_LAST \
8396 HWRM_ASYNC_EVENT_CMPL_FUNC_DRVR_LOAD_TYPE_HWRM_ASYNC_EVENT
8397 /* Identifiers of events. */
8399 /* Function driver loaded */
8400 #define HWRM_ASYNC_EVENT_CMPL_FUNC_DRVR_LOAD_EVENT_ID_FUNC_DRVR_LOAD \
8402 #define HWRM_ASYNC_EVENT_CMPL_FUNC_DRVR_LOAD_EVENT_ID_LAST \
8403 HWRM_ASYNC_EVENT_CMPL_FUNC_DRVR_LOAD_EVENT_ID_FUNC_DRVR_LOAD
8404 /* Event specific data */
8405 uint32_t event_data2;
8408 * This value is written by the NIC such that it will be different
8409 * for each pass through the completion queue. The even passes
8410 * will write 1. The odd passes will write 0.
8412 #define HWRM_ASYNC_EVENT_CMPL_FUNC_DRVR_LOAD_V UINT32_C(0x1)
8414 #define HWRM_ASYNC_EVENT_CMPL_FUNC_DRVR_LOAD_OPAQUE_MASK UINT32_C(0xfe)
8415 #define HWRM_ASYNC_EVENT_CMPL_FUNC_DRVR_LOAD_OPAQUE_SFT 1
8416 /* 8-lsb timestamp from POR (100-msec resolution) */
8417 uint8_t timestamp_lo;
8418 /* 16-lsb timestamp from POR (100-msec resolution) */
8419 uint16_t timestamp_hi;
8420 /* Event specific data */
8421 uint32_t event_data1;
8423 #define HWRM_ASYNC_EVENT_CMPL_FUNC_DRVR_LOAD_EVENT_DATA1_FUNC_ID_MASK \
8425 #define HWRM_ASYNC_EVENT_CMPL_FUNC_DRVR_LOAD_EVENT_DATA1_FUNC_ID_SFT 0
8428 /* hwrm_async_event_cmpl_func_flr_proc_cmplt (size:128b/16B) */
8429 struct hwrm_async_event_cmpl_func_flr_proc_cmplt {
8432 * This field indicates the exact type of the completion.
8433 * By convention, the LSB identifies the length of the
8434 * record in 16B units. Even values indicate 16B
8435 * records. Odd values indicate 32B
8438 #define HWRM_ASYNC_EVENT_CMPL_FUNC_FLR_PROC_CMPLT_TYPE_MASK \
8440 #define HWRM_ASYNC_EVENT_CMPL_FUNC_FLR_PROC_CMPLT_TYPE_SFT \
8442 /* HWRM Asynchronous Event Information */
8443 #define HWRM_ASYNC_EVENT_CMPL_FUNC_FLR_PROC_CMPLT_TYPE_HWRM_ASYNC_EVENT \
8445 #define HWRM_ASYNC_EVENT_CMPL_FUNC_FLR_PROC_CMPLT_TYPE_LAST \
8446 HWRM_ASYNC_EVENT_CMPL_FUNC_FLR_PROC_CMPLT_TYPE_HWRM_ASYNC_EVENT
8447 /* Identifiers of events. */
8449 /* Function FLR related processing has completed */
8450 #define HWRM_ASYNC_EVENT_CMPL_FUNC_FLR_PROC_CMPLT_EVENT_ID_FUNC_FLR_PROC_CMPLT \
8452 #define HWRM_ASYNC_EVENT_CMPL_FUNC_FLR_PROC_CMPLT_EVENT_ID_LAST \
8453 HWRM_ASYNC_EVENT_CMPL_FUNC_FLR_PROC_CMPLT_EVENT_ID_FUNC_FLR_PROC_CMPLT
8454 /* Event specific data */
8455 uint32_t event_data2;
8458 * This value is written by the NIC such that it will be different
8459 * for each pass through the completion queue. The even passes
8460 * will write 1. The odd passes will write 0.
8462 #define HWRM_ASYNC_EVENT_CMPL_FUNC_FLR_PROC_CMPLT_V \
8465 #define HWRM_ASYNC_EVENT_CMPL_FUNC_FLR_PROC_CMPLT_OPAQUE_MASK \
8467 #define HWRM_ASYNC_EVENT_CMPL_FUNC_FLR_PROC_CMPLT_OPAQUE_SFT 1
8468 /* 8-lsb timestamp from POR (100-msec resolution) */
8469 uint8_t timestamp_lo;
8470 /* 16-lsb timestamp from POR (100-msec resolution) */
8471 uint16_t timestamp_hi;
8472 /* Event specific data */
8473 uint32_t event_data1;
8475 #define HWRM_ASYNC_EVENT_CMPL_FUNC_FLR_PROC_CMPLT_EVENT_DATA1_FUNC_ID_MASK \
8477 #define HWRM_ASYNC_EVENT_CMPL_FUNC_FLR_PROC_CMPLT_EVENT_DATA1_FUNC_ID_SFT \
8481 /* hwrm_async_event_cmpl_pf_drvr_unload (size:128b/16B) */
8482 struct hwrm_async_event_cmpl_pf_drvr_unload {
8485 * This field indicates the exact type of the completion.
8486 * By convention, the LSB identifies the length of the
8487 * record in 16B units. Even values indicate 16B
8488 * records. Odd values indicate 32B
8491 #define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_UNLOAD_TYPE_MASK \
8493 #define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_UNLOAD_TYPE_SFT 0
8494 /* HWRM Asynchronous Event Information */
8495 #define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_UNLOAD_TYPE_HWRM_ASYNC_EVENT \
8497 #define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_UNLOAD_TYPE_LAST \
8498 HWRM_ASYNC_EVENT_CMPL_PF_DRVR_UNLOAD_TYPE_HWRM_ASYNC_EVENT
8499 /* Identifiers of events. */
8501 /* PF driver unloaded */
8502 #define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_UNLOAD_EVENT_ID_PF_DRVR_UNLOAD \
8504 #define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_UNLOAD_EVENT_ID_LAST \
8505 HWRM_ASYNC_EVENT_CMPL_PF_DRVR_UNLOAD_EVENT_ID_PF_DRVR_UNLOAD
8506 /* Event specific data */
8507 uint32_t event_data2;
8510 * This value is written by the NIC such that it will be different
8511 * for each pass through the completion queue. The even passes
8512 * will write 1. The odd passes will write 0.
8514 #define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_UNLOAD_V UINT32_C(0x1)
8516 #define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_UNLOAD_OPAQUE_MASK UINT32_C(0xfe)
8517 #define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_UNLOAD_OPAQUE_SFT 1
8518 /* 8-lsb timestamp from POR (100-msec resolution) */
8519 uint8_t timestamp_lo;
8520 /* 16-lsb timestamp from POR (100-msec resolution) */
8521 uint16_t timestamp_hi;
8522 /* Event specific data */
8523 uint32_t event_data1;
8525 #define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_UNLOAD_EVENT_DATA1_FUNC_ID_MASK \
8527 #define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_UNLOAD_EVENT_DATA1_FUNC_ID_SFT 0
8528 /* Indicates the physical port this pf belongs to */
8529 #define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_UNLOAD_EVENT_DATA1_PORT_MASK \
8531 #define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_UNLOAD_EVENT_DATA1_PORT_SFT 16
8534 /* hwrm_async_event_cmpl_pf_drvr_load (size:128b/16B) */
8535 struct hwrm_async_event_cmpl_pf_drvr_load {
8538 * This field indicates the exact type of the completion.
8539 * By convention, the LSB identifies the length of the
8540 * record in 16B units. Even values indicate 16B
8541 * records. Odd values indicate 32B
8544 #define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_LOAD_TYPE_MASK \
8546 #define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_LOAD_TYPE_SFT 0
8547 /* HWRM Asynchronous Event Information */
8548 #define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_LOAD_TYPE_HWRM_ASYNC_EVENT \
8550 #define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_LOAD_TYPE_LAST \
8551 HWRM_ASYNC_EVENT_CMPL_PF_DRVR_LOAD_TYPE_HWRM_ASYNC_EVENT
8552 /* Identifiers of events. */
8554 /* PF driver loaded */
8555 #define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_LOAD_EVENT_ID_PF_DRVR_LOAD \
8557 #define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_LOAD_EVENT_ID_LAST \
8558 HWRM_ASYNC_EVENT_CMPL_PF_DRVR_LOAD_EVENT_ID_PF_DRVR_LOAD
8559 /* Event specific data */
8560 uint32_t event_data2;
8563 * This value is written by the NIC such that it will be different
8564 * for each pass through the completion queue. The even passes
8565 * will write 1. The odd passes will write 0.
8567 #define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_LOAD_V UINT32_C(0x1)
8569 #define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_LOAD_OPAQUE_MASK UINT32_C(0xfe)
8570 #define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_LOAD_OPAQUE_SFT 1
8571 /* 8-lsb timestamp from POR (100-msec resolution) */
8572 uint8_t timestamp_lo;
8573 /* 16-lsb timestamp from POR (100-msec resolution) */
8574 uint16_t timestamp_hi;
8575 /* Event specific data */
8576 uint32_t event_data1;
8578 #define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_LOAD_EVENT_DATA1_FUNC_ID_MASK \
8580 #define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_LOAD_EVENT_DATA1_FUNC_ID_SFT 0
8581 /* Indicates the physical port this pf belongs to */
8582 #define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_LOAD_EVENT_DATA1_PORT_MASK \
8584 #define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_LOAD_EVENT_DATA1_PORT_SFT 16
8587 /* hwrm_async_event_cmpl_vf_flr (size:128b/16B) */
8588 struct hwrm_async_event_cmpl_vf_flr {
8591 * This field indicates the exact type of the completion.
8592 * By convention, the LSB identifies the length of the
8593 * record in 16B units. Even values indicate 16B
8594 * records. Odd values indicate 32B
8597 #define HWRM_ASYNC_EVENT_CMPL_VF_FLR_TYPE_MASK \
8599 #define HWRM_ASYNC_EVENT_CMPL_VF_FLR_TYPE_SFT 0
8600 /* HWRM Asynchronous Event Information */
8601 #define HWRM_ASYNC_EVENT_CMPL_VF_FLR_TYPE_HWRM_ASYNC_EVENT \
8603 #define HWRM_ASYNC_EVENT_CMPL_VF_FLR_TYPE_LAST \
8604 HWRM_ASYNC_EVENT_CMPL_VF_FLR_TYPE_HWRM_ASYNC_EVENT
8605 /* Identifiers of events. */
8607 /* VF Function Level Reset (FLR) */
8608 #define HWRM_ASYNC_EVENT_CMPL_VF_FLR_EVENT_ID_VF_FLR UINT32_C(0x30)
8609 #define HWRM_ASYNC_EVENT_CMPL_VF_FLR_EVENT_ID_LAST \
8610 HWRM_ASYNC_EVENT_CMPL_VF_FLR_EVENT_ID_VF_FLR
8611 /* Event specific data */
8612 uint32_t event_data2;
8615 * This value is written by the NIC such that it will be different
8616 * for each pass through the completion queue. The even passes
8617 * will write 1. The odd passes will write 0.
8619 #define HWRM_ASYNC_EVENT_CMPL_VF_FLR_V UINT32_C(0x1)
8621 #define HWRM_ASYNC_EVENT_CMPL_VF_FLR_OPAQUE_MASK UINT32_C(0xfe)
8622 #define HWRM_ASYNC_EVENT_CMPL_VF_FLR_OPAQUE_SFT 1
8623 /* 8-lsb timestamp from POR (100-msec resolution) */
8624 uint8_t timestamp_lo;
8625 /* 16-lsb timestamp from POR (100-msec resolution) */
8626 uint16_t timestamp_hi;
8627 /* Event specific data */
8628 uint32_t event_data1;
8630 #define HWRM_ASYNC_EVENT_CMPL_VF_FLR_EVENT_DATA1_VF_ID_MASK \
8632 #define HWRM_ASYNC_EVENT_CMPL_VF_FLR_EVENT_DATA1_VF_ID_SFT 0
8633 /* Indicates the physical function this event occurred on. */
8634 #define HWRM_ASYNC_EVENT_CMPL_VF_FLR_EVENT_DATA1_PF_ID_MASK \
8636 #define HWRM_ASYNC_EVENT_CMPL_VF_FLR_EVENT_DATA1_PF_ID_SFT 16
8639 /* hwrm_async_event_cmpl_vf_mac_addr_change (size:128b/16B) */
8640 struct hwrm_async_event_cmpl_vf_mac_addr_change {
8643 * This field indicates the exact type of the completion.
8644 * By convention, the LSB identifies the length of the
8645 * record in 16B units. Even values indicate 16B
8646 * records. Odd values indicate 32B
8649 #define HWRM_ASYNC_EVENT_CMPL_VF_MAC_ADDR_CHANGE_TYPE_MASK \
8651 #define HWRM_ASYNC_EVENT_CMPL_VF_MAC_ADDR_CHANGE_TYPE_SFT 0
8652 /* HWRM Asynchronous Event Information */
8653 #define HWRM_ASYNC_EVENT_CMPL_VF_MAC_ADDR_CHANGE_TYPE_HWRM_ASYNC_EVENT \
8655 #define HWRM_ASYNC_EVENT_CMPL_VF_MAC_ADDR_CHANGE_TYPE_LAST \
8656 HWRM_ASYNC_EVENT_CMPL_VF_MAC_ADDR_CHANGE_TYPE_HWRM_ASYNC_EVENT
8657 /* Identifiers of events. */
8659 /* VF MAC Address Change */
8660 #define HWRM_ASYNC_EVENT_CMPL_VF_MAC_ADDR_CHANGE_EVENT_ID_VF_MAC_ADDR_CHANGE \
8662 #define HWRM_ASYNC_EVENT_CMPL_VF_MAC_ADDR_CHANGE_EVENT_ID_LAST \
8663 HWRM_ASYNC_EVENT_CMPL_VF_MAC_ADDR_CHANGE_EVENT_ID_VF_MAC_ADDR_CHANGE
8664 /* Event specific data */
8665 uint32_t event_data2;
8668 * This value is written by the NIC such that it will be different
8669 * for each pass through the completion queue. The even passes
8670 * will write 1. The odd passes will write 0.
8672 #define HWRM_ASYNC_EVENT_CMPL_VF_MAC_ADDR_CHANGE_V \
8675 #define HWRM_ASYNC_EVENT_CMPL_VF_MAC_ADDR_CHANGE_OPAQUE_MASK \
8677 #define HWRM_ASYNC_EVENT_CMPL_VF_MAC_ADDR_CHANGE_OPAQUE_SFT 1
8678 /* 8-lsb timestamp from POR (100-msec resolution) */
8679 uint8_t timestamp_lo;
8680 /* 16-lsb timestamp from POR (100-msec resolution) */
8681 uint16_t timestamp_hi;
8682 /* Event specific data */
8683 uint32_t event_data1;
8685 #define HWRM_ASYNC_EVENT_CMPL_VF_MAC_ADDR_CHANGE_EVENT_DATA1_VF_ID_MASK \
8687 #define HWRM_ASYNC_EVENT_CMPL_VF_MAC_ADDR_CHANGE_EVENT_DATA1_VF_ID_SFT \
8691 /* hwrm_async_event_cmpl_pf_vf_comm_status_change (size:128b/16B) */
8692 struct hwrm_async_event_cmpl_pf_vf_comm_status_change {
8695 * This field indicates the exact type of the completion.
8696 * By convention, the LSB identifies the length of the
8697 * record in 16B units. Even values indicate 16B
8698 * records. Odd values indicate 32B
8701 #define HWRM_ASYNC_EVENT_CMPL_PF_VF_COMM_STATUS_CHANGE_TYPE_MASK \
8703 #define HWRM_ASYNC_EVENT_CMPL_PF_VF_COMM_STATUS_CHANGE_TYPE_SFT \
8705 /* HWRM Asynchronous Event Information */
8706 #define HWRM_ASYNC_EVENT_CMPL_PF_VF_COMM_STATUS_CHANGE_TYPE_HWRM_ASYNC_EVENT \
8708 #define HWRM_ASYNC_EVENT_CMPL_PF_VF_COMM_STATUS_CHANGE_TYPE_LAST \
8709 HWRM_ASYNC_EVENT_CMPL_PF_VF_COMM_STATUS_CHANGE_TYPE_HWRM_ASYNC_EVENT
8710 /* Identifiers of events. */
8712 /* PF-VF communication channel status change. */
8713 #define HWRM_ASYNC_EVENT_CMPL_PF_VF_COMM_STATUS_CHANGE_EVENT_ID_PF_VF_COMM_STATUS_CHANGE \
8715 #define HWRM_ASYNC_EVENT_CMPL_PF_VF_COMM_STATUS_CHANGE_EVENT_ID_LAST \
8716 HWRM_ASYNC_EVENT_CMPL_PF_VF_COMM_STATUS_CHANGE_EVENT_ID_PF_VF_COMM_STATUS_CHANGE
8717 /* Event specific data */
8718 uint32_t event_data2;
8721 * This value is written by the NIC such that it will be different
8722 * for each pass through the completion queue. The even passes
8723 * will write 1. The odd passes will write 0.
8725 #define HWRM_ASYNC_EVENT_CMPL_PF_VF_COMM_STATUS_CHANGE_V \
8728 #define HWRM_ASYNC_EVENT_CMPL_PF_VF_COMM_STATUS_CHANGE_OPAQUE_MASK \
8730 #define HWRM_ASYNC_EVENT_CMPL_PF_VF_COMM_STATUS_CHANGE_OPAQUE_SFT 1
8731 /* 8-lsb timestamp from POR (100-msec resolution) */
8732 uint8_t timestamp_lo;
8733 /* 16-lsb timestamp from POR (100-msec resolution) */
8734 uint16_t timestamp_hi;
8735 /* Event specific data */
8736 uint32_t event_data1;
8738 * If this bit is set to 1, then it indicates that the PF-VF
8739 * communication was lost and it is established.
8740 * If this bit set to 0, then it indicates that the PF-VF
8741 * communication was established and it is lost.
8743 #define HWRM_ASYNC_EVENT_CMPL_PF_VF_COMM_STATUS_CHANGE_EVENT_DATA1_COMM_ESTABLISHED \
8747 /* hwrm_async_event_cmpl_vf_cfg_change (size:128b/16B) */
8748 struct hwrm_async_event_cmpl_vf_cfg_change {
8751 * This field indicates the exact type of the completion.
8752 * By convention, the LSB identifies the length of the
8753 * record in 16B units. Even values indicate 16B
8754 * records. Odd values indicate 32B
8757 #define HWRM_ASYNC_EVENT_CMPL_VF_CFG_CHANGE_TYPE_MASK \
8759 #define HWRM_ASYNC_EVENT_CMPL_VF_CFG_CHANGE_TYPE_SFT 0
8760 /* HWRM Asynchronous Event Information */
8761 #define HWRM_ASYNC_EVENT_CMPL_VF_CFG_CHANGE_TYPE_HWRM_ASYNC_EVENT \
8763 #define HWRM_ASYNC_EVENT_CMPL_VF_CFG_CHANGE_TYPE_LAST \
8764 HWRM_ASYNC_EVENT_CMPL_VF_CFG_CHANGE_TYPE_HWRM_ASYNC_EVENT
8765 /* Identifiers of events. */
8767 /* VF Configuration Change */
8768 #define HWRM_ASYNC_EVENT_CMPL_VF_CFG_CHANGE_EVENT_ID_VF_CFG_CHANGE \
8770 #define HWRM_ASYNC_EVENT_CMPL_VF_CFG_CHANGE_EVENT_ID_LAST \
8771 HWRM_ASYNC_EVENT_CMPL_VF_CFG_CHANGE_EVENT_ID_VF_CFG_CHANGE
8772 /* Event specific data */
8773 uint32_t event_data2;
8776 * This value is written by the NIC such that it will be different
8777 * for each pass through the completion queue. The even passes
8778 * will write 1. The odd passes will write 0.
8780 #define HWRM_ASYNC_EVENT_CMPL_VF_CFG_CHANGE_V UINT32_C(0x1)
8782 #define HWRM_ASYNC_EVENT_CMPL_VF_CFG_CHANGE_OPAQUE_MASK UINT32_C(0xfe)
8783 #define HWRM_ASYNC_EVENT_CMPL_VF_CFG_CHANGE_OPAQUE_SFT 1
8784 /* 8-lsb timestamp from POR (100-msec resolution) */
8785 uint8_t timestamp_lo;
8786 /* 16-lsb timestamp from POR (100-msec resolution) */
8787 uint16_t timestamp_hi;
8789 * Each flag provided in this field indicates a specific VF
8790 * configuration change. At least one of these flags shall be set to 1
8791 * when an asynchronous event completion of this type is provided
8794 uint32_t event_data1;
8796 * If this bit is set to 1, then the value of MTU
8797 * was changed on this VF.
8798 * If set to 0, then this bit should be ignored.
8800 #define HWRM_ASYNC_EVENT_CMPL_VF_CFG_CHANGE_EVENT_DATA1_MTU_CHANGE \
8803 * If this bit is set to 1, then the value of MRU
8804 * was changed on this VF.
8805 * If set to 0, then this bit should be ignored.
8807 #define HWRM_ASYNC_EVENT_CMPL_VF_CFG_CHANGE_EVENT_DATA1_MRU_CHANGE \
8810 * If this bit is set to 1, then the value of default MAC
8811 * address was changed on this VF.
8812 * If set to 0, then this bit should be ignored.
8814 #define HWRM_ASYNC_EVENT_CMPL_VF_CFG_CHANGE_EVENT_DATA1_DFLT_MAC_ADDR_CHANGE \
8817 * If this bit is set to 1, then the value of default VLAN
8818 * was changed on this VF.
8819 * If set to 0, then this bit should be ignored.
8821 #define HWRM_ASYNC_EVENT_CMPL_VF_CFG_CHANGE_EVENT_DATA1_DFLT_VLAN_CHANGE \
8824 * If this bit is set to 1, then the value of trusted VF enable
8825 * was changed on this VF.
8826 * If set to 0, then this bit should be ignored.
8828 #define HWRM_ASYNC_EVENT_CMPL_VF_CFG_CHANGE_EVENT_DATA1_TRUSTED_VF_CFG_CHANGE \
8832 /* hwrm_async_event_cmpl_llfc_pfc_change (size:128b/16B) */
8833 struct hwrm_async_event_cmpl_llfc_pfc_change {
8836 * This field indicates the exact type of the completion.
8837 * By convention, the LSB identifies the length of the
8838 * record in 16B units. Even values indicate 16B
8839 * records. Odd values indicate 32B
8842 #define HWRM_ASYNC_EVENT_CMPL_LLFC_PFC_CHANGE_TYPE_MASK \
8844 #define HWRM_ASYNC_EVENT_CMPL_LLFC_PFC_CHANGE_TYPE_SFT 0
8845 /* HWRM Asynchronous Event Information */
8846 #define HWRM_ASYNC_EVENT_CMPL_LLFC_PFC_CHANGE_TYPE_HWRM_ASYNC_EVENT \
8848 #define HWRM_ASYNC_EVENT_CMPL_LLFC_PFC_CHANGE_TYPE_LAST \
8849 HWRM_ASYNC_EVENT_CMPL_LLFC_PFC_CHANGE_TYPE_HWRM_ASYNC_EVENT
8850 /* unused1 is 10 b */
8851 #define HWRM_ASYNC_EVENT_CMPL_LLFC_PFC_CHANGE_UNUSED1_MASK \
8853 #define HWRM_ASYNC_EVENT_CMPL_LLFC_PFC_CHANGE_UNUSED1_SFT 6
8854 /* Identifiers of events. */
8856 /* LLFC/PFC Configuration Change */
8857 #define HWRM_ASYNC_EVENT_CMPL_LLFC_PFC_CHANGE_EVENT_ID_LLFC_PFC_CHANGE \
8859 #define HWRM_ASYNC_EVENT_CMPL_LLFC_PFC_CHANGE_EVENT_ID_LAST \
8860 HWRM_ASYNC_EVENT_CMPL_LLFC_PFC_CHANGE_EVENT_ID_LLFC_PFC_CHANGE
8861 /* Event specific data */
8862 uint32_t event_data2;
8865 * This value is written by the NIC such that it will be different
8866 * for each pass through the completion queue. The even passes
8867 * will write 1. The odd passes will write 0.
8869 #define HWRM_ASYNC_EVENT_CMPL_LLFC_PFC_CHANGE_V UINT32_C(0x1)
8871 #define HWRM_ASYNC_EVENT_CMPL_LLFC_PFC_CHANGE_OPAQUE_MASK \
8873 #define HWRM_ASYNC_EVENT_CMPL_LLFC_PFC_CHANGE_OPAQUE_SFT 1
8874 /* 8-lsb timestamp from POR (100-msec resolution) */
8875 uint8_t timestamp_lo;
8876 /* 16-lsb timestamp from POR (100-msec resolution) */
8877 uint16_t timestamp_hi;
8878 /* Event specific data */
8879 uint32_t event_data1;
8880 /* Indicates llfc pfc status change */
8881 #define HWRM_ASYNC_EVENT_CMPL_LLFC_PFC_CHANGE_EVENT_DATA1_LLFC_PFC_MASK \
8883 #define HWRM_ASYNC_EVENT_CMPL_LLFC_PFC_CHANGE_EVENT_DATA1_LLFC_PFC_SFT \
8886 * If this field set to 1, then it indicates that llfc is
8889 #define HWRM_ASYNC_EVENT_CMPL_LLFC_PFC_CHANGE_EVENT_DATA1_LLFC_PFC_LLFC \
8892 * If this field is set to 2, then it indicates that pfc
8895 #define HWRM_ASYNC_EVENT_CMPL_LLFC_PFC_CHANGE_EVENT_DATA1_LLFC_PFC_PFC \
8897 #define HWRM_ASYNC_EVENT_CMPL_LLFC_PFC_CHANGE_EVENT_DATA1_LLFC_PFC_LAST \
8898 HWRM_ASYNC_EVENT_CMPL_LLFC_PFC_CHANGE_EVENT_DATA1_LLFC_PFC_PFC
8899 /* Indicates the physical port this llfc pfc change occur */
8900 #define HWRM_ASYNC_EVENT_CMPL_LLFC_PFC_CHANGE_EVENT_DATA1_PORT_MASK \
8902 #define HWRM_ASYNC_EVENT_CMPL_LLFC_PFC_CHANGE_EVENT_DATA1_PORT_SFT \
8905 #define HWRM_ASYNC_EVENT_CMPL_LLFC_PFC_CHANGE_EVENT_DATA1_PORT_ID_MASK \
8907 #define HWRM_ASYNC_EVENT_CMPL_LLFC_PFC_CHANGE_EVENT_DATA1_PORT_ID_SFT \
8911 /* hwrm_async_event_cmpl_default_vnic_change (size:128b/16B) */
8912 struct hwrm_async_event_cmpl_default_vnic_change {
8915 * This field indicates the exact type of the completion.
8916 * By convention, the LSB identifies the length of the
8917 * record in 16B units. Even values indicate 16B
8918 * records. Odd values indicate 32B
8921 #define HWRM_ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_TYPE_MASK \
8923 #define HWRM_ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_TYPE_SFT \
8925 /* HWRM Asynchronous Event Information */
8926 #define HWRM_ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_TYPE_HWRM_ASYNC_EVENT \
8928 #define HWRM_ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_TYPE_LAST \
8929 HWRM_ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_TYPE_HWRM_ASYNC_EVENT
8930 /* unused1 is 10 b */
8931 #define HWRM_ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_UNUSED1_MASK \
8933 #define HWRM_ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_UNUSED1_SFT \
8935 /* Identifiers of events. */
8937 /* Notification of a default vnic allocation or free */
8938 #define HWRM_ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_EVENT_ID_ALLOC_FREE_NOTIFICATION \
8940 #define HWRM_ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_EVENT_ID_LAST \
8941 HWRM_ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_EVENT_ID_ALLOC_FREE_NOTIFICATION
8942 /* Event specific data */
8943 uint32_t event_data2;
8946 * This value is written by the NIC such that it will be different
8947 * for each pass through the completion queue. The even passes
8948 * will write 1. The odd passes will write 0.
8950 #define HWRM_ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_V \
8953 #define HWRM_ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_OPAQUE_MASK \
8955 #define HWRM_ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_OPAQUE_SFT 1
8956 /* 8-lsb timestamp from POR (100-msec resolution) */
8957 uint8_t timestamp_lo;
8958 /* 16-lsb timestamp from POR (100-msec resolution) */
8959 uint16_t timestamp_hi;
8960 /* Event specific data */
8961 uint32_t event_data1;
8962 /* Indicates default vnic configuration change */
8963 #define HWRM_ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_EVENT_DATA1_DEF_VNIC_STATE_MASK \
8965 #define HWRM_ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_EVENT_DATA1_DEF_VNIC_STATE_SFT \
8968 * If this field is set to 1, then it indicates that
8969 * a default VNIC has been allocate.
8971 #define HWRM_ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_EVENT_DATA1_DEF_VNIC_STATE_DEF_VNIC_ALLOC \
8974 * If this field is set to 2, then it indicates that
8975 * a default VNIC has been freed.
8977 #define HWRM_ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_EVENT_DATA1_DEF_VNIC_STATE_DEF_VNIC_FREE \
8979 #define HWRM_ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_EVENT_DATA1_DEF_VNIC_STATE_LAST \
8980 HWRM_ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_EVENT_DATA1_DEF_VNIC_STATE_DEF_VNIC_FREE
8981 /* Indicates the physical function this event occurred on. */
8982 #define HWRM_ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_EVENT_DATA1_PF_ID_MASK \
8984 #define HWRM_ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_EVENT_DATA1_PF_ID_SFT \
8986 /* Indicates the virtual function this event occurred on */
8987 #define HWRM_ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_EVENT_DATA1_VF_ID_MASK \
8989 #define HWRM_ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_EVENT_DATA1_VF_ID_SFT \
8993 /* hwrm_async_event_cmpl_hw_flow_aged (size:128b/16B) */
8994 struct hwrm_async_event_cmpl_hw_flow_aged {
8997 * This field indicates the exact type of the completion.
8998 * By convention, the LSB identifies the length of the
8999 * record in 16B units. Even values indicate 16B
9000 * records. Odd values indicate 32B
9003 #define HWRM_ASYNC_EVENT_CMPL_HW_FLOW_AGED_TYPE_MASK \
9005 #define HWRM_ASYNC_EVENT_CMPL_HW_FLOW_AGED_TYPE_SFT 0
9006 /* HWRM Asynchronous Event Information */
9007 #define HWRM_ASYNC_EVENT_CMPL_HW_FLOW_AGED_TYPE_HWRM_ASYNC_EVENT \
9009 #define HWRM_ASYNC_EVENT_CMPL_HW_FLOW_AGED_TYPE_LAST \
9010 HWRM_ASYNC_EVENT_CMPL_HW_FLOW_AGED_TYPE_HWRM_ASYNC_EVENT
9011 /* Identifiers of events. */
9013 /* Notification of a hw flow aged */
9014 #define HWRM_ASYNC_EVENT_CMPL_HW_FLOW_AGED_EVENT_ID_HW_FLOW_AGED \
9016 #define HWRM_ASYNC_EVENT_CMPL_HW_FLOW_AGED_EVENT_ID_LAST \
9017 HWRM_ASYNC_EVENT_CMPL_HW_FLOW_AGED_EVENT_ID_HW_FLOW_AGED
9018 /* Event specific data */
9019 uint32_t event_data2;
9022 * This value is written by the NIC such that it will be different
9023 * for each pass through the completion queue. The even passes
9024 * will write 1. The odd passes will write 0.
9026 #define HWRM_ASYNC_EVENT_CMPL_HW_FLOW_AGED_V UINT32_C(0x1)
9028 #define HWRM_ASYNC_EVENT_CMPL_HW_FLOW_AGED_OPAQUE_MASK UINT32_C(0xfe)
9029 #define HWRM_ASYNC_EVENT_CMPL_HW_FLOW_AGED_OPAQUE_SFT 1
9030 /* 8-lsb timestamp from POR (100-msec resolution) */
9031 uint8_t timestamp_lo;
9032 /* 16-lsb timestamp from POR (100-msec resolution) */
9033 uint16_t timestamp_hi;
9034 /* Event specific data */
9035 uint32_t event_data1;
9036 /* Indicates flow ID this event occurred on. */
9037 #define HWRM_ASYNC_EVENT_CMPL_HW_FLOW_AGED_EVENT_DATA1_FLOW_ID_MASK \
9038 UINT32_C(0x7fffffff)
9039 #define HWRM_ASYNC_EVENT_CMPL_HW_FLOW_AGED_EVENT_DATA1_FLOW_ID_SFT \
9041 /* Indicates flow direction this event occurred on. */
9042 #define HWRM_ASYNC_EVENT_CMPL_HW_FLOW_AGED_EVENT_DATA1_FLOW_DIRECTION \
9043 UINT32_C(0x80000000)
9045 * If this bit set to 0, then it indicates that the aged
9046 * event was rx flow.
9048 #define HWRM_ASYNC_EVENT_CMPL_HW_FLOW_AGED_EVENT_DATA1_FLOW_DIRECTION_RX \
9049 (UINT32_C(0x0) << 31)
9051 * If this bit is set to 1, then it indicates that the aged
9052 * event was tx flow.
9054 #define HWRM_ASYNC_EVENT_CMPL_HW_FLOW_AGED_EVENT_DATA1_FLOW_DIRECTION_TX \
9055 (UINT32_C(0x1) << 31)
9056 #define HWRM_ASYNC_EVENT_CMPL_HW_FLOW_AGED_EVENT_DATA1_FLOW_DIRECTION_LAST \
9057 HWRM_ASYNC_EVENT_CMPL_HW_FLOW_AGED_EVENT_DATA1_FLOW_DIRECTION_TX
9060 /* hwrm_async_event_cmpl_eem_cache_flush_req (size:128b/16B) */
9061 struct hwrm_async_event_cmpl_eem_cache_flush_req {
9064 * This field indicates the exact type of the completion.
9065 * By convention, the LSB identifies the length of the
9066 * record in 16B units. Even values indicate 16B
9067 * records. Odd values indicate 32B
9070 #define HWRM_ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_REQ_TYPE_MASK \
9072 #define HWRM_ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_REQ_TYPE_SFT \
9074 /* HWRM Asynchronous Event Information */
9075 #define HWRM_ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_REQ_TYPE_HWRM_ASYNC_EVENT \
9077 #define HWRM_ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_REQ_TYPE_LAST \
9078 HWRM_ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_REQ_TYPE_HWRM_ASYNC_EVENT
9079 /* Identifiers of events. */
9081 /* Notification of a eem_cache_flush request */
9082 #define HWRM_ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_REQ_EVENT_ID_EEM_CACHE_FLUSH_REQ \
9084 #define HWRM_ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_REQ_EVENT_ID_LAST \
9085 HWRM_ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_REQ_EVENT_ID_EEM_CACHE_FLUSH_REQ
9086 /* Event specific data */
9087 uint32_t event_data2;
9090 * This value is written by the NIC such that it will be different
9091 * for each pass through the completion queue. The even passes
9092 * will write 1. The odd passes will write 0.
9094 #define HWRM_ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_REQ_V \
9097 #define HWRM_ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_REQ_OPAQUE_MASK \
9099 #define HWRM_ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_REQ_OPAQUE_SFT 1
9100 /* 8-lsb timestamp from POR (100-msec resolution) */
9101 uint8_t timestamp_lo;
9102 /* 16-lsb timestamp from POR (100-msec resolution) */
9103 uint16_t timestamp_hi;
9104 /* Event specific data */
9105 uint32_t event_data1;
9108 /* hwrm_async_event_cmpl_eem_cache_flush_done (size:128b/16B) */
9109 struct hwrm_async_event_cmpl_eem_cache_flush_done {
9112 * This field indicates the exact type of the completion.
9113 * By convention, the LSB identifies the length of the
9114 * record in 16B units. Even values indicate 16B
9115 * records. Odd values indicate 32B
9118 #define HWRM_ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_DONE_TYPE_MASK \
9120 #define HWRM_ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_DONE_TYPE_SFT \
9122 /* HWRM Asynchronous Event Information */
9123 #define HWRM_ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_DONE_TYPE_HWRM_ASYNC_EVENT \
9125 #define HWRM_ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_DONE_TYPE_LAST \
9126 HWRM_ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_DONE_TYPE_HWRM_ASYNC_EVENT
9127 /* Identifiers of events. */
9130 * Notification of a host eem_cache_flush has completed. This event
9131 * is generated by the host driver.
9133 #define HWRM_ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_DONE_EVENT_ID_EEM_CACHE_FLUSH_DONE \
9135 #define HWRM_ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_DONE_EVENT_ID_LAST \
9136 HWRM_ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_DONE_EVENT_ID_EEM_CACHE_FLUSH_DONE
9137 /* Event specific data */
9138 uint32_t event_data2;
9141 * This value is written by the NIC such that it will be different
9142 * for each pass through the completion queue. The even passes
9143 * will write 1. The odd passes will write 0.
9145 #define HWRM_ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_DONE_V \
9148 #define HWRM_ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_DONE_OPAQUE_MASK \
9150 #define HWRM_ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_DONE_OPAQUE_SFT 1
9151 /* 8-lsb timestamp from POR (100-msec resolution) */
9152 uint8_t timestamp_lo;
9153 /* 16-lsb timestamp from POR (100-msec resolution) */
9154 uint16_t timestamp_hi;
9155 /* Event specific data */
9156 uint32_t event_data1;
9157 /* Indicates function ID that this event occurred on. */
9158 #define HWRM_ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_DONE_EVENT_DATA1_FID_MASK \
9160 #define HWRM_ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_DONE_EVENT_DATA1_FID_SFT \
9164 /* hwrm_async_event_cmpl_tcp_flag_action_change (size:128b/16B) */
9165 struct hwrm_async_event_cmpl_tcp_flag_action_change {
9168 * This field indicates the exact type of the completion.
9169 * By convention, the LSB identifies the length of the
9170 * record in 16B units. Even values indicate 16B
9171 * records. Odd values indicate 32B
9174 #define HWRM_ASYNC_EVENT_CMPL_TCP_FLAG_ACTION_CHANGE_TYPE_MASK \
9176 #define HWRM_ASYNC_EVENT_CMPL_TCP_FLAG_ACTION_CHANGE_TYPE_SFT \
9178 /* HWRM Asynchronous Event Information */
9179 #define HWRM_ASYNC_EVENT_CMPL_TCP_FLAG_ACTION_CHANGE_TYPE_HWRM_ASYNC_EVENT \
9181 #define HWRM_ASYNC_EVENT_CMPL_TCP_FLAG_ACTION_CHANGE_TYPE_LAST \
9182 HWRM_ASYNC_EVENT_CMPL_TCP_FLAG_ACTION_CHANGE_TYPE_HWRM_ASYNC_EVENT
9183 /* Identifiers of events. */
9185 /* Notification of tcp flag action change */
9186 #define HWRM_ASYNC_EVENT_CMPL_TCP_FLAG_ACTION_CHANGE_EVENT_ID_TCP_FLAG_ACTION_CHANGE \
9188 #define HWRM_ASYNC_EVENT_CMPL_TCP_FLAG_ACTION_CHANGE_EVENT_ID_LAST \
9189 HWRM_ASYNC_EVENT_CMPL_TCP_FLAG_ACTION_CHANGE_EVENT_ID_TCP_FLAG_ACTION_CHANGE
9190 /* Event specific data */
9191 uint32_t event_data2;
9194 * This value is written by the NIC such that it will be different
9195 * for each pass through the completion queue. The even passes
9196 * will write 1. The odd passes will write 0.
9198 #define HWRM_ASYNC_EVENT_CMPL_TCP_FLAG_ACTION_CHANGE_V \
9201 #define HWRM_ASYNC_EVENT_CMPL_TCP_FLAG_ACTION_CHANGE_OPAQUE_MASK \
9203 #define HWRM_ASYNC_EVENT_CMPL_TCP_FLAG_ACTION_CHANGE_OPAQUE_SFT 1
9204 /* 8-lsb timestamp from POR (100-msec resolution) */
9205 uint8_t timestamp_lo;
9206 /* 16-lsb timestamp from POR (100-msec resolution) */
9207 uint16_t timestamp_hi;
9208 /* Event specific data */
9209 uint32_t event_data1;
9212 /* hwrm_async_event_cmpl_eem_flow_active (size:128b/16B) */
9213 struct hwrm_async_event_cmpl_eem_flow_active {
9216 * This field indicates the exact type of the completion.
9217 * By convention, the LSB identifies the length of the
9218 * record in 16B units. Even values indicate 16B
9219 * records. Odd values indicate 32B
9222 #define HWRM_ASYNC_EVENT_CMPL_EEM_FLOW_ACTIVE_TYPE_MASK \
9224 #define HWRM_ASYNC_EVENT_CMPL_EEM_FLOW_ACTIVE_TYPE_SFT 0
9225 /* HWRM Asynchronous Event Information */
9226 #define HWRM_ASYNC_EVENT_CMPL_EEM_FLOW_ACTIVE_TYPE_HWRM_ASYNC_EVENT \
9228 #define HWRM_ASYNC_EVENT_CMPL_EEM_FLOW_ACTIVE_TYPE_LAST \
9229 HWRM_ASYNC_EVENT_CMPL_EEM_FLOW_ACTIVE_TYPE_HWRM_ASYNC_EVENT
9230 /* Identifiers of events. */
9232 /* Notification of an active eem flow */
9233 #define HWRM_ASYNC_EVENT_CMPL_EEM_FLOW_ACTIVE_EVENT_ID_EEM_FLOW_ACTIVE \
9235 #define HWRM_ASYNC_EVENT_CMPL_EEM_FLOW_ACTIVE_EVENT_ID_LAST \
9236 HWRM_ASYNC_EVENT_CMPL_EEM_FLOW_ACTIVE_EVENT_ID_EEM_FLOW_ACTIVE
9237 /* Event specific data */
9238 uint32_t event_data2;
9239 /* Indicates the 2nd global id this event occurred on. */
9240 #define HWRM_ASYNC_EVENT_CMPL_EEM_FLOW_ACTIVE_EVENT_DATA2_GLOBAL_ID_2_MASK \
9241 UINT32_C(0x3fffffff)
9242 #define HWRM_ASYNC_EVENT_CMPL_EEM_FLOW_ACTIVE_EVENT_DATA2_GLOBAL_ID_2_SFT \
9245 * Indicates flow direction of the flow identified by
9248 #define HWRM_ASYNC_EVENT_CMPL_EEM_FLOW_ACTIVE_EVENT_DATA2_FLOW_DIRECTION \
9249 UINT32_C(0x40000000)
9250 /* If this bit is set to 0, then it indicates that this rx flow. */
9251 #define HWRM_ASYNC_EVENT_CMPL_EEM_FLOW_ACTIVE_EVENT_DATA2_FLOW_DIRECTION_RX \
9252 (UINT32_C(0x0) << 30)
9253 /* If this bit is set to 1, then it indicates that this tx flow. */
9254 #define HWRM_ASYNC_EVENT_CMPL_EEM_FLOW_ACTIVE_EVENT_DATA2_FLOW_DIRECTION_TX \
9255 (UINT32_C(0x1) << 30)
9256 #define HWRM_ASYNC_EVENT_CMPL_EEM_FLOW_ACTIVE_EVENT_DATA2_FLOW_DIRECTION_LAST \
9257 HWRM_ASYNC_EVENT_CMPL_EEM_FLOW_ACTIVE_EVENT_DATA2_FLOW_DIRECTION_TX
9260 * This value is written by the NIC such that it will be different
9261 * for each pass through the completion queue. The even passes
9262 * will write 1. The odd passes will write 0.
9264 #define HWRM_ASYNC_EVENT_CMPL_EEM_FLOW_ACTIVE_V UINT32_C(0x1)
9266 #define HWRM_ASYNC_EVENT_CMPL_EEM_FLOW_ACTIVE_OPAQUE_MASK \
9268 #define HWRM_ASYNC_EVENT_CMPL_EEM_FLOW_ACTIVE_OPAQUE_SFT 1
9269 /* 8-lsb timestamp from POR (100-msec resolution) */
9270 uint8_t timestamp_lo;
9271 /* 16-lsb timestamp from POR (100-msec resolution) */
9272 uint16_t timestamp_hi;
9273 /* Event specific data */
9274 uint32_t event_data1;
9275 /* Indicates the 1st global id this event occurred on. */
9276 #define HWRM_ASYNC_EVENT_CMPL_EEM_FLOW_ACTIVE_EVENT_DATA1_GLOBAL_ID_1_MASK \
9277 UINT32_C(0x3fffffff)
9278 #define HWRM_ASYNC_EVENT_CMPL_EEM_FLOW_ACTIVE_EVENT_DATA1_GLOBAL_ID_1_SFT \
9281 * Indicates flow direction of the flow identified by the
9284 #define HWRM_ASYNC_EVENT_CMPL_EEM_FLOW_ACTIVE_EVENT_DATA1_FLOW_DIRECTION \
9285 UINT32_C(0x40000000)
9286 /* If this bit is set to 0, then it indicates that this is rx flow. */
9287 #define HWRM_ASYNC_EVENT_CMPL_EEM_FLOW_ACTIVE_EVENT_DATA1_FLOW_DIRECTION_RX \
9288 (UINT32_C(0x0) << 30)
9289 /* If this bit is set to 1, then it indicates that this is tx flow. */
9290 #define HWRM_ASYNC_EVENT_CMPL_EEM_FLOW_ACTIVE_EVENT_DATA1_FLOW_DIRECTION_TX \
9291 (UINT32_C(0x1) << 30)
9292 #define HWRM_ASYNC_EVENT_CMPL_EEM_FLOW_ACTIVE_EVENT_DATA1_FLOW_DIRECTION_LAST \
9293 HWRM_ASYNC_EVENT_CMPL_EEM_FLOW_ACTIVE_EVENT_DATA1_FLOW_DIRECTION_TX
9295 * Indicates EEM flow aging mode this event occurred on. If
9296 * this bit is set to 0, the event_data1 is the EEM global
9297 * ID. If this bit is set to 1, the event_data1 is the number
9298 * of global ID in the context memory.
9300 #define HWRM_ASYNC_EVENT_CMPL_EEM_FLOW_ACTIVE_EVENT_DATA1_MODE \
9301 UINT32_C(0x80000000)
9302 /* EEM flow aging mode 0. */
9303 #define HWRM_ASYNC_EVENT_CMPL_EEM_FLOW_ACTIVE_EVENT_DATA1_MODE_0 \
9304 (UINT32_C(0x0) << 31)
9305 /* EEM flow aging mode 1. */
9306 #define HWRM_ASYNC_EVENT_CMPL_EEM_FLOW_ACTIVE_EVENT_DATA1_MODE_1 \
9307 (UINT32_C(0x1) << 31)
9308 #define HWRM_ASYNC_EVENT_CMPL_EEM_FLOW_ACTIVE_EVENT_DATA1_MODE_LAST \
9309 HWRM_ASYNC_EVENT_CMPL_EEM_FLOW_ACTIVE_EVENT_DATA1_MODE_1
9312 /* hwrm_async_event_cmpl_eem_cfg_change (size:128b/16B) */
9313 struct hwrm_async_event_cmpl_eem_cfg_change {
9316 * This field indicates the exact type of the completion.
9317 * By convention, the LSB identifies the length of the
9318 * record in 16B units. Even values indicate 16B
9319 * records. Odd values indicate 32B
9322 #define HWRM_ASYNC_EVENT_CMPL_EEM_CFG_CHANGE_TYPE_MASK \
9324 #define HWRM_ASYNC_EVENT_CMPL_EEM_CFG_CHANGE_TYPE_SFT 0
9325 /* HWRM Asynchronous Event Information */
9326 #define HWRM_ASYNC_EVENT_CMPL_EEM_CFG_CHANGE_TYPE_HWRM_ASYNC_EVENT \
9328 #define HWRM_ASYNC_EVENT_CMPL_EEM_CFG_CHANGE_TYPE_LAST \
9329 HWRM_ASYNC_EVENT_CMPL_EEM_CFG_CHANGE_TYPE_HWRM_ASYNC_EVENT
9330 /* Identifiers of events. */
9332 /* Notification of EEM configuration change */
9333 #define HWRM_ASYNC_EVENT_CMPL_EEM_CFG_CHANGE_EVENT_ID_EEM_CFG_CHANGE \
9335 #define HWRM_ASYNC_EVENT_CMPL_EEM_CFG_CHANGE_EVENT_ID_LAST \
9336 HWRM_ASYNC_EVENT_CMPL_EEM_CFG_CHANGE_EVENT_ID_EEM_CFG_CHANGE
9337 /* Event specific data */
9338 uint32_t event_data2;
9341 * This value is written by the NIC such that it will be different
9342 * for each pass through the completion queue. The even passes
9343 * will write 1. The odd passes will write 0.
9345 #define HWRM_ASYNC_EVENT_CMPL_EEM_CFG_CHANGE_V UINT32_C(0x1)
9347 #define HWRM_ASYNC_EVENT_CMPL_EEM_CFG_CHANGE_OPAQUE_MASK UINT32_C(0xfe)
9348 #define HWRM_ASYNC_EVENT_CMPL_EEM_CFG_CHANGE_OPAQUE_SFT 1
9349 /* 8-lsb timestamp from POR (100-msec resolution) */
9350 uint8_t timestamp_lo;
9351 /* 16-lsb timestamp from POR (100-msec resolution) */
9352 uint16_t timestamp_hi;
9353 /* Event specific data */
9354 uint32_t event_data1;
9356 * Value of 1 to indicate EEM TX configuration is enabled. Value of
9357 * 0 to indicate the EEM TX configuration is disabled.
9359 #define HWRM_ASYNC_EVENT_CMPL_EEM_CFG_CHANGE_EVENT_DATA1_EEM_TX_ENABLE \
9362 * Value of 1 to indicate EEM RX configuration is enabled. Value of 0
9363 * to indicate the EEM RX configuration is disabled.
9365 #define HWRM_ASYNC_EVENT_CMPL_EEM_CFG_CHANGE_EVENT_DATA1_EEM_RX_ENABLE \
9369 /* hwrm_async_event_cmpl_quiesce_done (size:128b/16B) */
9370 struct hwrm_async_event_cmpl_quiesce_done {
9373 * This field indicates the exact type of the completion.
9374 * By convention, the LSB identifies the length of the
9375 * record in 16B units. Even values indicate 16B
9376 * records. Odd values indicate 32B
9379 #define HWRM_ASYNC_EVENT_CMPL_QUIESCE_DONE_TYPE_MASK \
9381 #define HWRM_ASYNC_EVENT_CMPL_QUIESCE_DONE_TYPE_SFT 0
9382 /* HWRM Asynchronous Event Information */
9383 #define HWRM_ASYNC_EVENT_CMPL_QUIESCE_DONE_TYPE_HWRM_ASYNC_EVENT \
9385 #define HWRM_ASYNC_EVENT_CMPL_QUIESCE_DONE_TYPE_LAST \
9386 HWRM_ASYNC_EVENT_CMPL_QUIESCE_DONE_TYPE_HWRM_ASYNC_EVENT
9387 /* Identifiers of events. */
9389 /* An event signifying completion of HWRM_FW_STATE_QUIESCE */
9390 #define HWRM_ASYNC_EVENT_CMPL_QUIESCE_DONE_EVENT_ID_QUIESCE_DONE \
9392 #define HWRM_ASYNC_EVENT_CMPL_QUIESCE_DONE_EVENT_ID_LAST \
9393 HWRM_ASYNC_EVENT_CMPL_QUIESCE_DONE_EVENT_ID_QUIESCE_DONE
9394 /* Event specific data */
9395 uint32_t event_data2;
9396 /* Status of HWRM_FW_STATE_QUIESCE completion */
9397 #define HWRM_ASYNC_EVENT_CMPL_QUIESCE_DONE_EVENT_DATA2_QUIESCE_STATUS_MASK \
9399 #define HWRM_ASYNC_EVENT_CMPL_QUIESCE_DONE_EVENT_DATA2_QUIESCE_STATUS_SFT \
9402 * The quiesce operation started by HWRM_FW_STATE_QUIESCE
9403 * completed successfully.
9405 #define HWRM_ASYNC_EVENT_CMPL_QUIESCE_DONE_EVENT_DATA2_QUIESCE_STATUS_SUCCESS \
9408 * The quiesce operation started by HWRM_FW_STATE_QUIESCE timed
9411 #define HWRM_ASYNC_EVENT_CMPL_QUIESCE_DONE_EVENT_DATA2_QUIESCE_STATUS_TIMEOUT \
9414 * The quiesce operation started by HWRM_FW_STATE_QUIESCE
9415 * encountered an error.
9417 #define HWRM_ASYNC_EVENT_CMPL_QUIESCE_DONE_EVENT_DATA2_QUIESCE_STATUS_ERROR \
9419 #define HWRM_ASYNC_EVENT_CMPL_QUIESCE_DONE_EVENT_DATA2_QUIESCE_STATUS_LAST \
9420 HWRM_ASYNC_EVENT_CMPL_QUIESCE_DONE_EVENT_DATA2_QUIESCE_STATUS_ERROR
9422 #define HWRM_ASYNC_EVENT_CMPL_QUIESCE_DONE_EVENT_DATA2_OPAQUE_MASK \
9424 #define HWRM_ASYNC_EVENT_CMPL_QUIESCE_DONE_EVENT_DATA2_OPAQUE_SFT \
9427 * Additional information about internal hardware state related to
9428 * idle/quiesce state. QUIESCE may succeed per quiesce_status
9429 * regardless of idle_state_flags. If QUIESCE fails, the host may
9430 * inspect idle_state_flags to determine whether a retry is warranted.
9432 #define HWRM_ASYNC_EVENT_CMPL_QUIESCE_DONE_EVENT_DATA2_IDLE_STATE_FLAGS_MASK \
9434 #define HWRM_ASYNC_EVENT_CMPL_QUIESCE_DONE_EVENT_DATA2_IDLE_STATE_FLAGS_SFT \
9437 * Failure to quiesce is caused by host not updating the NQ consumer
9440 #define HWRM_ASYNC_EVENT_CMPL_QUIESCE_DONE_EVENT_DATA2_IDLE_STATE_FLAGS_INCOMPLETE_NQ \
9442 /* Flag 1 indicating partial non-idle state. */
9443 #define HWRM_ASYNC_EVENT_CMPL_QUIESCE_DONE_EVENT_DATA2_IDLE_STATE_FLAGS_IDLE_STATUS_1 \
9445 /* Flag 2 indicating partial non-idle state. */
9446 #define HWRM_ASYNC_EVENT_CMPL_QUIESCE_DONE_EVENT_DATA2_IDLE_STATE_FLAGS_IDLE_STATUS_2 \
9448 /* Flag 3 indicating partial non-idle state. */
9449 #define HWRM_ASYNC_EVENT_CMPL_QUIESCE_DONE_EVENT_DATA2_IDLE_STATE_FLAGS_IDLE_STATUS_3 \
9453 * This value is written by the NIC such that it will be different
9454 * for each pass through the completion queue. The even passes
9455 * will write 1. The odd passes will write 0.
9457 #define HWRM_ASYNC_EVENT_CMPL_QUIESCE_DONE_V UINT32_C(0x1)
9459 #define HWRM_ASYNC_EVENT_CMPL_QUIESCE_DONE_OPAQUE_MASK UINT32_C(0xfe)
9460 #define HWRM_ASYNC_EVENT_CMPL_QUIESCE_DONE_OPAQUE_SFT 1
9461 /* 8-lsb timestamp from POR (100-msec resolution) */
9462 uint8_t timestamp_lo;
9463 /* 16-lsb timestamp from POR (100-msec resolution) */
9464 uint16_t timestamp_hi;
9465 /* Event specific data */
9466 uint32_t event_data1;
9467 /* Time stamp for error event */
9468 #define HWRM_ASYNC_EVENT_CMPL_QUIESCE_DONE_EVENT_DATA1_TIMESTAMP \
9472 /* hwrm_async_event_cmpl_deferred_response (size:128b/16B) */
9473 struct hwrm_async_event_cmpl_deferred_response {
9476 * This field indicates the exact type of the completion.
9477 * By convention, the LSB identifies the length of the
9478 * record in 16B units. Even values indicate 16B
9479 * records. Odd values indicate 32B
9482 #define HWRM_ASYNC_EVENT_CMPL_DEFERRED_RESPONSE_TYPE_MASK \
9484 #define HWRM_ASYNC_EVENT_CMPL_DEFERRED_RESPONSE_TYPE_SFT 0
9485 /* HWRM Asynchronous Event Information */
9486 #define HWRM_ASYNC_EVENT_CMPL_DEFERRED_RESPONSE_TYPE_HWRM_ASYNC_EVENT \
9488 #define HWRM_ASYNC_EVENT_CMPL_DEFERRED_RESPONSE_TYPE_LAST \
9489 HWRM_ASYNC_EVENT_CMPL_DEFERRED_RESPONSE_TYPE_HWRM_ASYNC_EVENT
9490 /* Identifiers of events. */
9493 * An event signifying a HWRM command is in progress and its
9494 * response will be deferred
9496 #define HWRM_ASYNC_EVENT_CMPL_DEFERRED_RESPONSE_EVENT_ID_DEFERRED_RESPONSE \
9498 #define HWRM_ASYNC_EVENT_CMPL_DEFERRED_RESPONSE_EVENT_ID_LAST \
9499 HWRM_ASYNC_EVENT_CMPL_DEFERRED_RESPONSE_EVENT_ID_DEFERRED_RESPONSE
9500 /* Event specific data */
9501 uint32_t event_data2;
9503 * The PF's mailbox is clear to issue another command.
9504 * A command with this seq_id is still in progress
9505 * and will return a regular HWRM completion when done.
9506 * 'event_data1' field, if non-zero, contains the estimated
9507 * execution time for the command.
9509 #define HWRM_ASYNC_EVENT_CMPL_DEFERRED_RESPONSE_EVENT_DATA2_SEQ_ID_MASK \
9511 #define HWRM_ASYNC_EVENT_CMPL_DEFERRED_RESPONSE_EVENT_DATA2_SEQ_ID_SFT \
9515 * This value is written by the NIC such that it will be different
9516 * for each pass through the completion queue. The even passes
9517 * will write 1. The odd passes will write 0.
9519 #define HWRM_ASYNC_EVENT_CMPL_DEFERRED_RESPONSE_V \
9522 #define HWRM_ASYNC_EVENT_CMPL_DEFERRED_RESPONSE_OPAQUE_MASK \
9524 #define HWRM_ASYNC_EVENT_CMPL_DEFERRED_RESPONSE_OPAQUE_SFT 1
9525 /* 8-lsb timestamp from POR (100-msec resolution) */
9526 uint8_t timestamp_lo;
9527 /* 16-lsb timestamp from POR (100-msec resolution) */
9528 uint16_t timestamp_hi;
9529 /* Estimated remaining time of command execution in ms (if not zero) */
9530 uint32_t event_data1;
9533 /* hwrm_async_event_cmpl_pfc_watchdog_cfg_change (size:128b/16B) */
9534 struct hwrm_async_event_cmpl_pfc_watchdog_cfg_change {
9537 * This field indicates the exact type of the completion.
9538 * By convention, the LSB identifies the length of the
9539 * record in 16B units. Even values indicate 16B
9540 * records. Odd values indicate 32B
9543 #define HWRM_ASYNC_EVENT_CMPL_PFC_WATCHDOG_CFG_CHANGE_TYPE_MASK \
9545 #define HWRM_ASYNC_EVENT_CMPL_PFC_WATCHDOG_CFG_CHANGE_TYPE_SFT \
9547 /* HWRM Asynchronous Event Information */
9548 #define HWRM_ASYNC_EVENT_CMPL_PFC_WATCHDOG_CFG_CHANGE_TYPE_HWRM_ASYNC_EVENT \
9550 #define HWRM_ASYNC_EVENT_CMPL_PFC_WATCHDOG_CFG_CHANGE_TYPE_LAST \
9551 HWRM_ASYNC_EVENT_CMPL_PFC_WATCHDOG_CFG_CHANGE_TYPE_HWRM_ASYNC_EVENT
9552 /* Identifiers of events. */
9554 /* PFC watchdog configuration change for given port/cos */
9555 #define HWRM_ASYNC_EVENT_CMPL_PFC_WATCHDOG_CFG_CHANGE_EVENT_ID_PFC_WATCHDOG_CFG_CHANGE \
9557 #define HWRM_ASYNC_EVENT_CMPL_PFC_WATCHDOG_CFG_CHANGE_EVENT_ID_LAST \
9558 HWRM_ASYNC_EVENT_CMPL_PFC_WATCHDOG_CFG_CHANGE_EVENT_ID_PFC_WATCHDOG_CFG_CHANGE
9559 /* Event specific data */
9560 uint32_t event_data2;
9563 * This value is written by the NIC such that it will be different
9564 * for each pass through the completion queue. The even passes
9565 * will write 1. The odd passes will write 0.
9567 #define HWRM_ASYNC_EVENT_CMPL_PFC_WATCHDOG_CFG_CHANGE_V \
9570 #define HWRM_ASYNC_EVENT_CMPL_PFC_WATCHDOG_CFG_CHANGE_OPAQUE_MASK \
9572 #define HWRM_ASYNC_EVENT_CMPL_PFC_WATCHDOG_CFG_CHANGE_OPAQUE_SFT 1
9573 /* 8-lsb timestamp from POR (100-msec resolution) */
9574 uint8_t timestamp_lo;
9575 /* 16-lsb timestamp from POR (100-msec resolution) */
9576 uint16_t timestamp_hi;
9577 /* Event specific data */
9578 uint32_t event_data1;
9580 * 1 in bit position X indicates PFC watchdog should
9583 #define HWRM_ASYNC_EVENT_CMPL_PFC_WATCHDOG_CFG_CHANGE_EVENT_DATA1_PFC_WD_COS_MASK \
9585 #define HWRM_ASYNC_EVENT_CMPL_PFC_WATCHDOG_CFG_CHANGE_EVENT_DATA1_PFC_WD_COS_SFT \
9587 /* 1 means PFC WD for COS0 is on, 0 - off. */
9588 #define HWRM_ASYNC_EVENT_CMPL_PFC_WATCHDOG_CFG_CHANGE_EVENT_DATA1_PFC_WD_COS_PFC_WD_COS0 \
9590 /* 1 means PFC WD for COS1 is on, 0 - off. */
9591 #define HWRM_ASYNC_EVENT_CMPL_PFC_WATCHDOG_CFG_CHANGE_EVENT_DATA1_PFC_WD_COS_PFC_WD_COS1 \
9593 /* 1 means PFC WD for COS2 is on, 0 - off. */
9594 #define HWRM_ASYNC_EVENT_CMPL_PFC_WATCHDOG_CFG_CHANGE_EVENT_DATA1_PFC_WD_COS_PFC_WD_COS2 \
9596 /* 1 means PFC WD for COS3 is on, 0 - off. */
9597 #define HWRM_ASYNC_EVENT_CMPL_PFC_WATCHDOG_CFG_CHANGE_EVENT_DATA1_PFC_WD_COS_PFC_WD_COS3 \
9599 /* 1 means PFC WD for COS4 is on, 0 - off. */
9600 #define HWRM_ASYNC_EVENT_CMPL_PFC_WATCHDOG_CFG_CHANGE_EVENT_DATA1_PFC_WD_COS_PFC_WD_COS4 \
9602 /* 1 means PFC WD for COS5 is on, 0 - off. */
9603 #define HWRM_ASYNC_EVENT_CMPL_PFC_WATCHDOG_CFG_CHANGE_EVENT_DATA1_PFC_WD_COS_PFC_WD_COS5 \
9605 /* 1 means PFC WD for COS6 is on, 0 - off. */
9606 #define HWRM_ASYNC_EVENT_CMPL_PFC_WATCHDOG_CFG_CHANGE_EVENT_DATA1_PFC_WD_COS_PFC_WD_COS6 \
9608 /* 1 means PFC WD for COS7 is on, 0 - off. */
9609 #define HWRM_ASYNC_EVENT_CMPL_PFC_WATCHDOG_CFG_CHANGE_EVENT_DATA1_PFC_WD_COS_PFC_WD_COS7 \
9612 #define HWRM_ASYNC_EVENT_CMPL_PFC_WATCHDOG_CFG_CHANGE_EVENT_DATA1_PORT_ID_MASK \
9614 #define HWRM_ASYNC_EVENT_CMPL_PFC_WATCHDOG_CFG_CHANGE_EVENT_DATA1_PORT_ID_SFT \
9618 /* hwrm_async_event_cmpl_echo_request (size:128b/16B) */
9619 struct hwrm_async_event_cmpl_echo_request {
9622 * This field indicates the exact type of the completion.
9623 * By convention, the LSB identifies the length of the
9624 * record in 16B units. Even values indicate 16B
9625 * records. Odd values indicate 32B
9628 #define HWRM_ASYNC_EVENT_CMPL_ECHO_REQUEST_TYPE_MASK \
9630 #define HWRM_ASYNC_EVENT_CMPL_ECHO_REQUEST_TYPE_SFT 0
9631 /* HWRM Asynchronous Event Information */
9632 #define HWRM_ASYNC_EVENT_CMPL_ECHO_REQUEST_TYPE_HWRM_ASYNC_EVENT \
9634 #define HWRM_ASYNC_EVENT_CMPL_ECHO_REQUEST_TYPE_LAST \
9635 HWRM_ASYNC_EVENT_CMPL_ECHO_REQUEST_TYPE_HWRM_ASYNC_EVENT
9636 /* Identifiers of events. */
9639 * An echo request from the firmware. An echo response is expected by
9642 #define HWRM_ASYNC_EVENT_CMPL_ECHO_REQUEST_EVENT_ID_ECHO_REQUEST \
9644 #define HWRM_ASYNC_EVENT_CMPL_ECHO_REQUEST_EVENT_ID_LAST \
9645 HWRM_ASYNC_EVENT_CMPL_ECHO_REQUEST_EVENT_ID_ECHO_REQUEST
9646 /* Event specific data that should be provided in the echo response */
9647 uint32_t event_data2;
9650 * This value is written by the NIC such that it will be different
9651 * for each pass through the completion queue. The even passes
9652 * will write 1. The odd passes will write 0.
9654 #define HWRM_ASYNC_EVENT_CMPL_ECHO_REQUEST_V UINT32_C(0x1)
9656 #define HWRM_ASYNC_EVENT_CMPL_ECHO_REQUEST_OPAQUE_MASK UINT32_C(0xfe)
9657 #define HWRM_ASYNC_EVENT_CMPL_ECHO_REQUEST_OPAQUE_SFT 1
9658 /* 8-lsb timestamp from POR (100-msec resolution) */
9659 uint8_t timestamp_lo;
9660 /* 16-lsb timestamp from POR (100-msec resolution) */
9661 uint16_t timestamp_hi;
9662 /* Event specific data that should be provided in the echo response */
9663 uint32_t event_data1;
9666 /* hwrm_async_event_cmpl_fw_trace_msg (size:128b/16B) */
9667 struct hwrm_async_event_cmpl_fw_trace_msg {
9670 * This field indicates the exact type of the completion.
9671 * By convention, the LSB identifies the length of the
9672 * record in 16B units. Even values indicate 16B
9673 * records. Odd values indicate 32B
9676 #define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_TYPE_MASK \
9678 #define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_TYPE_SFT 0
9679 /* HWRM Asynchronous Event Information */
9680 #define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_TYPE_HWRM_ASYNC_EVENT \
9682 #define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_TYPE_LAST \
9683 HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_TYPE_HWRM_ASYNC_EVENT
9684 /* Identifiers of events. */
9686 /* Firmware trace log message */
9687 #define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_EVENT_ID_FW_TRACE_MSG \
9689 #define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_EVENT_ID_LAST \
9690 HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_EVENT_ID_FW_TRACE_MSG
9691 /* Trace byte 0 to 3 */
9692 uint32_t event_data2;
9694 #define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_EVENT_DATA2_BYTE0_MASK \
9696 #define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_EVENT_DATA2_BYTE0_SFT 0
9698 #define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_EVENT_DATA2_BYTE1_MASK \
9700 #define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_EVENT_DATA2_BYTE1_SFT 8
9702 #define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_EVENT_DATA2_BYTE2_MASK \
9704 #define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_EVENT_DATA2_BYTE2_SFT 16
9706 #define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_EVENT_DATA2_BYTE3_MASK \
9707 UINT32_C(0xff000000)
9708 #define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_EVENT_DATA2_BYTE3_SFT 24
9711 * This value is written by the NIC such that it will be different
9712 * for each pass through the completion queue. The even passes
9713 * will write 1. The odd passes will write 0.
9715 #define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_V UINT32_C(0x1)
9717 #define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_OPAQUE_MASK UINT32_C(0xfe)
9718 #define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_OPAQUE_SFT 1
9720 uint8_t timestamp_lo;
9721 /* Indicates if the string is partial or complete. */
9722 #define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_TIMESTAMP_LO_STRING \
9724 /* Complete string */
9725 #define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_TIMESTAMP_LO_STRING_COMPLETE \
9727 /* Partial string */
9728 #define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_TIMESTAMP_LO_STRING_PARTIAL \
9730 #define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_TIMESTAMP_LO_STRING_LAST \
9731 HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_TIMESTAMP_LO_STRING_PARTIAL
9732 /* Indicates the firmware that sent the trace message. */
9733 #define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_TIMESTAMP_LO_FIRMWARE \
9735 /* Primary firmware */
9736 #define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_TIMESTAMP_LO_FIRMWARE_PRIMARY \
9737 (UINT32_C(0x0) << 1)
9738 /* Secondary firmware */
9739 #define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_TIMESTAMP_LO_FIRMWARE_SECONDARY \
9740 (UINT32_C(0x1) << 1)
9741 #define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_TIMESTAMP_LO_FIRMWARE_LAST \
9742 HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_TIMESTAMP_LO_FIRMWARE_SECONDARY
9743 /* Trace byte 4 to 5 */
9744 uint16_t timestamp_hi;
9746 #define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_TIMESTAMP_HI_BYTE4_MASK \
9748 #define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_TIMESTAMP_HI_BYTE4_SFT 0
9750 #define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_TIMESTAMP_HI_BYTE5_MASK \
9752 #define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_TIMESTAMP_HI_BYTE5_SFT 8
9753 /* Trace byte 6 to 9 */
9754 uint32_t event_data1;
9756 #define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_EVENT_DATA1_BYTE6_MASK \
9758 #define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_EVENT_DATA1_BYTE6_SFT 0
9760 #define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_EVENT_DATA1_BYTE7_MASK \
9762 #define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_EVENT_DATA1_BYTE7_SFT 8
9764 #define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_EVENT_DATA1_BYTE8_MASK \
9766 #define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_EVENT_DATA1_BYTE8_SFT 16
9768 #define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_EVENT_DATA1_BYTE9_MASK \
9769 UINT32_C(0xff000000)
9770 #define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_EVENT_DATA1_BYTE9_SFT 24
9773 /* hwrm_async_event_cmpl_hwrm_error (size:128b/16B) */
9774 struct hwrm_async_event_cmpl_hwrm_error {
9777 * This field indicates the exact type of the completion.
9778 * By convention, the LSB identifies the length of the
9779 * record in 16B units. Even values indicate 16B
9780 * records. Odd values indicate 32B
9783 #define HWRM_ASYNC_EVENT_CMPL_HWRM_ERROR_TYPE_MASK \
9785 #define HWRM_ASYNC_EVENT_CMPL_HWRM_ERROR_TYPE_SFT 0
9786 /* HWRM Asynchronous Event Information */
9787 #define HWRM_ASYNC_EVENT_CMPL_HWRM_ERROR_TYPE_HWRM_ASYNC_EVENT \
9789 #define HWRM_ASYNC_EVENT_CMPL_HWRM_ERROR_TYPE_LAST \
9790 HWRM_ASYNC_EVENT_CMPL_HWRM_ERROR_TYPE_HWRM_ASYNC_EVENT
9791 /* Identifiers of events. */
9794 #define HWRM_ASYNC_EVENT_CMPL_HWRM_ERROR_EVENT_ID_HWRM_ERROR \
9796 #define HWRM_ASYNC_EVENT_CMPL_HWRM_ERROR_EVENT_ID_LAST \
9797 HWRM_ASYNC_EVENT_CMPL_HWRM_ERROR_EVENT_ID_HWRM_ERROR
9798 /* Event specific data */
9799 uint32_t event_data2;
9800 /* Severity of HWRM Error */
9801 #define HWRM_ASYNC_EVENT_CMPL_HWRM_ERROR_EVENT_DATA2_SEVERITY_MASK \
9803 #define HWRM_ASYNC_EVENT_CMPL_HWRM_ERROR_EVENT_DATA2_SEVERITY_SFT 0
9805 #define HWRM_ASYNC_EVENT_CMPL_HWRM_ERROR_EVENT_DATA2_SEVERITY_WARNING \
9807 /* Non-fatal Error */
9808 #define HWRM_ASYNC_EVENT_CMPL_HWRM_ERROR_EVENT_DATA2_SEVERITY_NONFATAL \
9811 #define HWRM_ASYNC_EVENT_CMPL_HWRM_ERROR_EVENT_DATA2_SEVERITY_FATAL \
9813 #define HWRM_ASYNC_EVENT_CMPL_HWRM_ERROR_EVENT_DATA2_SEVERITY_LAST \
9814 HWRM_ASYNC_EVENT_CMPL_HWRM_ERROR_EVENT_DATA2_SEVERITY_FATAL
9817 * This value is written by the NIC such that it will be different
9818 * for each pass through the completion queue. The even passes
9819 * will write 1. The odd passes will write 0.
9821 #define HWRM_ASYNC_EVENT_CMPL_HWRM_ERROR_V UINT32_C(0x1)
9823 #define HWRM_ASYNC_EVENT_CMPL_HWRM_ERROR_OPAQUE_MASK UINT32_C(0xfe)
9824 #define HWRM_ASYNC_EVENT_CMPL_HWRM_ERROR_OPAQUE_SFT 1
9825 /* 8-lsb timestamp from POR (100-msec resolution) */
9826 uint8_t timestamp_lo;
9827 /* 16-lsb timestamp from POR (100-msec resolution) */
9828 uint16_t timestamp_hi;
9829 /* Event specific data */
9830 uint32_t event_data1;
9831 /* Time stamp for error event */
9832 #define HWRM_ASYNC_EVENT_CMPL_HWRM_ERROR_EVENT_DATA1_TIMESTAMP \
9836 /* metadata_base_msg (size:64b/8B) */
9837 struct metadata_base_msg {
9838 uint16_t md_type_link;
9839 /* This field classifies the data present in the meta-data. */
9840 #define METADATA_BASE_MSG_MD_TYPE_MASK UINT32_C(0x1f)
9841 #define METADATA_BASE_MSG_MD_TYPE_SFT 0
9842 /* Meta data fields are not valid */
9843 #define METADATA_BASE_MSG_MD_TYPE_NONE UINT32_C(0x0)
9845 * This setting is used when packets are coming in-order. Depending on
9846 * the state of the receive context, the meta-data will carry different
9849 #define METADATA_BASE_MSG_MD_TYPE_TLS_INSYNC UINT32_C(0x1)
9851 * With this setting HW passes the TCP sequence number of the TLS
9852 * record that it is requesting a resync on in the meta data.
9854 #define METADATA_BASE_MSG_MD_TYPE_TLS_RESYNC UINT32_C(0x2)
9855 #define METADATA_BASE_MSG_MD_TYPE_LAST \
9856 METADATA_BASE_MSG_MD_TYPE_TLS_RESYNC
9858 * This field indicates where the next metadata block starts. It is
9859 * counted in 16B units. A value of zero indicates that there is no
9862 #define METADATA_BASE_MSG_LINK_MASK UINT32_C(0x1e0)
9863 #define METADATA_BASE_MSG_LINK_SFT 5
9868 /* tls_metadata_base_msg (size:64b/8B) */
9869 struct tls_metadata_base_msg {
9870 uint32_t md_type_link_flags_kid_lo;
9871 /* This field classifies the data present in the meta-data. */
9872 #define TLS_METADATA_BASE_MSG_MD_TYPE_MASK \
9874 #define TLS_METADATA_BASE_MSG_MD_TYPE_SFT 0
9876 * This setting is used when packets are coming in-order. Depending on
9877 * the state of the receive context, the meta-data will carry different
9880 #define TLS_METADATA_BASE_MSG_MD_TYPE_TLS_INSYNC \
9883 * With this setting HW passes the TCP sequence number of the TLS
9884 * record that it is requesting a resync on in the meta data.
9886 #define TLS_METADATA_BASE_MSG_MD_TYPE_TLS_RESYNC \
9888 #define TLS_METADATA_BASE_MSG_MD_TYPE_LAST \
9889 TLS_METADATA_BASE_MSG_MD_TYPE_TLS_RESYNC
9891 * This field indicates where the next metadata block starts. It is
9892 * counted in 16B units. A value of zero indicates that there is no
9895 #define TLS_METADATA_BASE_MSG_LINK_MASK \
9897 #define TLS_METADATA_BASE_MSG_LINK_SFT 5
9898 /* These are flags present in the metadata. */
9899 #define TLS_METADATA_BASE_MSG_FLAGS_MASK \
9901 #define TLS_METADATA_BASE_MSG_FLAGS_SFT 9
9903 * A value of 1 implies that the packet was decrypted by HW. Otherwise
9904 * the packet is passed on as it came in on the wire.
9906 #define TLS_METADATA_BASE_MSG_FLAGS_DECRYPTED \
9909 * This field indicates the state of the ghash field passed in the
9912 #define TLS_METADATA_BASE_MSG_FLAGS_GHASH_MASK \
9914 #define TLS_METADATA_BASE_MSG_FLAGS_GHASH_SFT 10
9916 * This enumeration states that the ghash is not valid in the
9919 #define TLS_METADATA_BASE_MSG_FLAGS_GHASH_NOT_VALID \
9920 (UINT32_C(0x0) << 10)
9922 * This enumeration indicates that this pkt contains the record's
9923 * tag and this pkt was received ooo, the partial_ghash field
9924 * contains the ghash.
9926 #define TLS_METADATA_BASE_MSG_FLAGS_GHASH_CUR_REC \
9927 (UINT32_C(0x1) << 10)
9929 * This enumeration indicates that the current record's tag wasn't
9930 * seen and the chip is moving on to the next record, the
9931 * partial_ghash field contains the ghash.
9933 #define TLS_METADATA_BASE_MSG_FLAGS_GHASH_PRIOR_REC \
9934 (UINT32_C(0x2) << 10)
9935 #define TLS_METADATA_BASE_MSG_FLAGS_GHASH_LAST \
9936 TLS_METADATA_BASE_MSG_FLAGS_GHASH_PRIOR_REC
9937 /* This field indicates the status of tag authentication. */
9938 #define TLS_METADATA_BASE_MSG_FLAGS_TAG_AUTH_STATUS_MASK \
9940 #define TLS_METADATA_BASE_MSG_FLAGS_TAG_AUTH_STATUS_SFT 12
9942 * This enumeration is set when there is no tags present in the
9945 #define TLS_METADATA_BASE_MSG_FLAGS_TAG_AUTH_STATUS_NONE \
9946 (UINT32_C(0x0) << 12)
9948 * This enumeration states that there is at least one tag in the
9949 * packet and every tag is valid.
9951 #define TLS_METADATA_BASE_MSG_FLAGS_TAG_AUTH_STATUS_SUCCESS \
9952 (UINT32_C(0x1) << 12)
9954 * This enumeration states that there is at least one tag in the
9955 * packet and at least one of the tag is invalid. The entire packet
9956 * is sent decrypted to the host.
9958 #define TLS_METADATA_BASE_MSG_FLAGS_TAG_AUTH_STATUS_FAILURE \
9959 (UINT32_C(0x2) << 12)
9960 #define TLS_METADATA_BASE_MSG_FLAGS_TAG_AUTH_STATUS_LAST \
9961 TLS_METADATA_BASE_MSG_FLAGS_TAG_AUTH_STATUS_FAILURE
9963 * A value of 1 indicates that this packet contains a record that
9964 * starts in the packet and extends beyond the packet.
9966 #define TLS_METADATA_BASE_MSG_FLAGS_HEADER_FLDS_VALID \
9969 * This value indicates the lower 7-bit of the Crypto Key ID
9970 * associated with this operation.
9972 #define TLS_METADATA_BASE_MSG_KID_LO_MASK \
9973 UINT32_C(0xfe000000)
9974 #define TLS_METADATA_BASE_MSG_KID_LO_SFT 25
9977 * This value indicates the upper 13-bit of the Crypto Key ID
9978 * associated with this operation.
9980 #define TLS_METADATA_BASE_MSG_KID_HI_MASK UINT32_C(0x1fff)
9981 #define TLS_METADATA_BASE_MSG_KID_HI_SFT 0
9985 /* tls_metadata_insync_msg (size:192b/24B) */
9986 struct tls_metadata_insync_msg {
9987 uint32_t md_type_link_flags_kid_lo;
9988 /* This field classifies the data present in the meta-data. */
9989 #define TLS_METADATA_INSYNC_MSG_MD_TYPE_MASK \
9991 #define TLS_METADATA_INSYNC_MSG_MD_TYPE_SFT 0
9993 * This setting is used when packets are coming in-order. Depending on
9994 * the state of the receive context, the meta-data will carry different
9997 #define TLS_METADATA_INSYNC_MSG_MD_TYPE_TLS_INSYNC \
9999 #define TLS_METADATA_INSYNC_MSG_MD_TYPE_LAST \
10000 TLS_METADATA_INSYNC_MSG_MD_TYPE_TLS_INSYNC
10002 * This field indicates where the next metadata block starts. It is
10003 * counted in 16B units. A value of zero indicates that there is no
10006 #define TLS_METADATA_INSYNC_MSG_LINK_MASK \
10008 #define TLS_METADATA_INSYNC_MSG_LINK_SFT 5
10009 /* These are flags present in the metadata. */
10010 #define TLS_METADATA_INSYNC_MSG_FLAGS_MASK \
10011 UINT32_C(0x1fffe00)
10012 #define TLS_METADATA_INSYNC_MSG_FLAGS_SFT 9
10014 * A value of 1 implies that the packet was decrypted by HW. Otherwise
10015 * the packet is passed on as it came in on the wire.
10017 #define TLS_METADATA_INSYNC_MSG_FLAGS_DECRYPTED \
10020 * This field indicates the state of the ghash field passed in the
10023 #define TLS_METADATA_INSYNC_MSG_FLAGS_GHASH_MASK \
10025 #define TLS_METADATA_INSYNC_MSG_FLAGS_GHASH_SFT 10
10027 * This enumeration states that the ghash is not valid in the
10030 #define TLS_METADATA_INSYNC_MSG_FLAGS_GHASH_NOT_VALID \
10031 (UINT32_C(0x0) << 10)
10033 * This enumeration indicates that this pkt contains the record's
10034 * tag and this pkt was received ooo, the partial_ghash field
10035 * contains the ghash.
10037 #define TLS_METADATA_INSYNC_MSG_FLAGS_GHASH_CUR_REC \
10038 (UINT32_C(0x1) << 10)
10040 * This enumeration indicates that the current record's tag wasn't
10041 * seen and the chip is moving on to the next record, the
10042 * partial_ghash field contains the ghash.
10044 #define TLS_METADATA_INSYNC_MSG_FLAGS_GHASH_PRIOR_REC \
10045 (UINT32_C(0x2) << 10)
10046 #define TLS_METADATA_INSYNC_MSG_FLAGS_GHASH_LAST \
10047 TLS_METADATA_INSYNC_MSG_FLAGS_GHASH_PRIOR_REC
10048 /* This field indicates the status of tag authentication. */
10049 #define TLS_METADATA_INSYNC_MSG_FLAGS_TAG_AUTH_STATUS_MASK \
10051 #define TLS_METADATA_INSYNC_MSG_FLAGS_TAG_AUTH_STATUS_SFT 12
10053 * This enumeration is set when there is no tags present in the
10056 #define TLS_METADATA_INSYNC_MSG_FLAGS_TAG_AUTH_STATUS_NONE \
10057 (UINT32_C(0x0) << 12)
10059 * This enumeration states that there is at least one tag in the
10060 * packet and every tag is valid.
10062 #define TLS_METADATA_INSYNC_MSG_FLAGS_TAG_AUTH_STATUS_SUCCESS \
10063 (UINT32_C(0x1) << 12)
10065 * This enumeration states that there is at least one tag in the
10066 * packet and at least one of the tag is invalid. The entire packet
10067 * is sent decrypted to the host.
10069 #define TLS_METADATA_INSYNC_MSG_FLAGS_TAG_AUTH_STATUS_FAILURE \
10070 (UINT32_C(0x2) << 12)
10071 #define TLS_METADATA_INSYNC_MSG_FLAGS_TAG_AUTH_STATUS_LAST \
10072 TLS_METADATA_INSYNC_MSG_FLAGS_TAG_AUTH_STATUS_FAILURE
10074 * A value of 1 indicates that this packet contains a record that
10075 * starts in the packet and extends beyond the packet.
10077 #define TLS_METADATA_INSYNC_MSG_FLAGS_HEADER_FLDS_VALID \
10080 * This value indicates the lower 7-bit of the Crypto Key ID
10081 * associated with this operation.
10083 #define TLS_METADATA_INSYNC_MSG_KID_LO_MASK \
10084 UINT32_C(0xfe000000)
10085 #define TLS_METADATA_INSYNC_MSG_KID_LO_SFT 25
10088 * This value indicates the upper 13-bit of the Crypto Key ID
10089 * associated with this operation.
10091 #define TLS_METADATA_INSYNC_MSG_KID_HI_MASK UINT32_C(0x1fff)
10092 #define TLS_METADATA_INSYNC_MSG_KID_HI_SFT 0
10094 * This field is only valid when md_type is set to tls_insync. This field
10095 * indicates the offset within the current TCP packet where the TLS header
10096 * starts. If there are multiple TLS headers in the packet, this provides
10097 * the offset of the last TLS header.
10099 * The field is calculated by subtracting TCP sequence number of the first
10100 * byte of the TCP payload of the packet from the TCP sequence number of
10101 * the last TLS header in the packet.
10103 uint16_t tls_header_offset;
10105 * This is the sequence Number of the record that was processed by the HW.
10106 * If there are multiple records in a packet, this would be the sequence
10107 * number of the last record.
10109 uint64_t record_seq_num;
10111 * This field contains cumulative partial GHASH value of all the packets
10112 * decrypted by the HW associated with a TLS record. This field is valid
10113 * on when packets belonging to have arrived out-of-order and HW could
10114 * not decrypt every packet and authenticate the record. Partial GHASH is
10115 * only sent out with packet having the TAG field.
10117 uint64_t partial_ghash;
10120 /* tls_metadata_resync_msg (size:256b/32B) */
10121 struct tls_metadata_resync_msg {
10122 uint32_t md_type_link_flags_kid_lo;
10123 /* This field classifies the data present in the meta-data. */
10124 #define TLS_METADATA_RESYNC_MSG_MD_TYPE_MASK \
10126 #define TLS_METADATA_RESYNC_MSG_MD_TYPE_SFT 0
10128 * With this setting HW passes the TCP sequence number of the TLS
10129 * record that it is requesting a resync on in the meta data.
10131 #define TLS_METADATA_RESYNC_MSG_MD_TYPE_TLS_RESYNC \
10133 #define TLS_METADATA_RESYNC_MSG_MD_TYPE_LAST \
10134 TLS_METADATA_RESYNC_MSG_MD_TYPE_TLS_RESYNC
10136 * This field indicates where the next metadata block starts. It is
10137 * counted in 16B units. A value of zero indicates that there is no
10140 #define TLS_METADATA_RESYNC_MSG_LINK_MASK \
10142 #define TLS_METADATA_RESYNC_MSG_LINK_SFT 5
10143 /* These are flags present in the metadata. */
10144 #define TLS_METADATA_RESYNC_MSG_FLAGS_MASK \
10145 UINT32_C(0x1fffe00)
10146 #define TLS_METADATA_RESYNC_MSG_FLAGS_SFT 9
10148 * A value of 1 implies that the packet was decrypted by HW. Otherwise
10149 * the packet is passed on as it came in on the wire.
10151 #define TLS_METADATA_RESYNC_MSG_FLAGS_DECRYPTED \
10154 * This field indicates the state of the ghash field passed in the
10157 #define TLS_METADATA_RESYNC_MSG_FLAGS_GHASH_MASK \
10159 #define TLS_METADATA_RESYNC_MSG_FLAGS_GHASH_SFT 10
10161 * This enumeration states that the ghash is not valid in the
10164 #define TLS_METADATA_RESYNC_MSG_FLAGS_GHASH_NOT_VALID \
10165 (UINT32_C(0x0) << 10)
10166 #define TLS_METADATA_RESYNC_MSG_FLAGS_GHASH_LAST \
10167 TLS_METADATA_RESYNC_MSG_FLAGS_GHASH_NOT_VALID
10168 /* This field indicates the status of tag authentication. */
10169 #define TLS_METADATA_RESYNC_MSG_FLAGS_TAG_AUTH_STATUS_MASK \
10171 #define TLS_METADATA_RESYNC_MSG_FLAGS_TAG_AUTH_STATUS_SFT 12
10173 * This enumeration is set when there is no tags present in the
10176 #define TLS_METADATA_RESYNC_MSG_FLAGS_TAG_AUTH_STATUS_NONE \
10177 (UINT32_C(0x0) << 12)
10178 #define TLS_METADATA_RESYNC_MSG_FLAGS_TAG_AUTH_STATUS_LAST \
10179 TLS_METADATA_RESYNC_MSG_FLAGS_TAG_AUTH_STATUS_NONE
10181 * A value of 1 indicates that this packet contains a record that
10182 * starts in the packet and extends beyond the packet.
10184 #define TLS_METADATA_RESYNC_MSG_FLAGS_HEADER_FLDS_VALID \
10187 * This value indicates the lower 7-bit of the Crypto Key ID
10188 * associated with this operation.
10190 #define TLS_METADATA_RESYNC_MSG_KID_LO_MASK \
10191 UINT32_C(0xfe000000)
10192 #define TLS_METADATA_RESYNC_MSG_KID_LO_SFT 25
10195 * This value indicates the upper 13-bit of the Crypto Key ID
10196 * associated with this operation.
10198 #define TLS_METADATA_RESYNC_MSG_KID_HI_MASK UINT32_C(0x1fff)
10199 #define TLS_METADATA_RESYNC_MSG_KID_HI_SFT 0
10200 /* This field is unused in this context. */
10201 uint16_t metadata_0;
10203 * This field indicates the TCP sequence number of the TLS record that HW
10204 * is requesting a resync on from the Driver. HW will keep a count of the
10205 * TLS records it found after this record (delta_records). Driver will
10206 * provide the TLS Record Sequence Number associated with the record. HW
10207 * will add the delta_records to the Record Sequence Number provided by
10208 * the driver and get back on sync.
10210 uint32_t resync_record_tcp_seq_num;
10212 /* This field is unused in this context. */
10213 uint64_t metadata_2;
10214 /* This field is unused in this context. */
10215 uint64_t metadata_3;
10218 /*******************
10219 * hwrm_func_reset *
10220 *******************/
10223 /* hwrm_func_reset_input (size:192b/24B) */
10224 struct hwrm_func_reset_input {
10225 /* The HWRM command request type. */
10228 * The completion ring to send the completion event on. This should
10229 * be the NQ ID returned from the `nq_alloc` HWRM command.
10231 uint16_t cmpl_ring;
10233 * The sequence ID is used by the driver for tracking multiple
10234 * commands. This ID is treated as opaque data by the firmware and
10235 * the value is returned in the `hwrm_resp_hdr` upon completion.
10239 * The target ID of the command:
10240 * * 0x0-0xFFF8 - The function ID
10241 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
10242 * * 0xFFFD - Reserved for user-space HWRM interface
10245 uint16_t target_id;
10247 * A physical address pointer pointing to a host buffer that the
10248 * command's response data will be written. This can be either a host
10249 * physical address (HPA) or a guest physical address (GPA) and must
10250 * point to a physically contiguous block of memory.
10252 uint64_t resp_addr;
10255 * This bit must be '1' for the vf_id_valid field to be
10258 #define HWRM_FUNC_RESET_INPUT_ENABLES_VF_ID_VALID UINT32_C(0x1)
10260 * The ID of the VF that this PF is trying to reset.
10261 * Only the parent PF shall be allowed to reset a child VF.
10263 * A parent PF driver shall use this field only when a specific child VF
10264 * is requested to be reset.
10267 /* This value indicates the level of a function reset. */
10268 uint8_t func_reset_level;
10270 * Reset the caller function and its children VFs (if any). If no
10271 * children functions exist, then reset the caller function only.
10273 #define HWRM_FUNC_RESET_INPUT_FUNC_RESET_LEVEL_RESETALL \
10275 /* Reset the caller function only */
10276 #define HWRM_FUNC_RESET_INPUT_FUNC_RESET_LEVEL_RESETME \
10279 * Reset all children VFs of the caller function driver if the
10280 * caller is a PF driver.
10281 * It is an error to specify this level by a VF driver.
10282 * It is an error to specify this level by a PF driver with
10285 #define HWRM_FUNC_RESET_INPUT_FUNC_RESET_LEVEL_RESETCHILDREN \
10288 * Reset a specific VF of the caller function driver if the caller
10289 * is the parent PF driver.
10290 * It is an error to specify this level by a VF driver.
10291 * It is an error to specify this level by a PF driver that is not
10292 * the parent of the VF that is being requested to reset.
10294 #define HWRM_FUNC_RESET_INPUT_FUNC_RESET_LEVEL_RESETVF \
10296 #define HWRM_FUNC_RESET_INPUT_FUNC_RESET_LEVEL_LAST \
10297 HWRM_FUNC_RESET_INPUT_FUNC_RESET_LEVEL_RESETVF
10301 /* hwrm_func_reset_output (size:128b/16B) */
10302 struct hwrm_func_reset_output {
10303 /* The specific error status for the command. */
10304 uint16_t error_code;
10305 /* The HWRM command request type. */
10307 /* The sequence ID from the original command. */
10309 /* The length of the response data in number of bytes. */
10311 uint8_t unused_0[7];
10313 * This field is used in Output records to indicate that the output
10314 * is completely written to RAM. This field should be read as '1'
10315 * to indicate that the output has been completely written.
10316 * When writing a command completion or response to an internal processor,
10317 * the order of writes has to be such that this field is written last.
10322 /********************
10323 * hwrm_func_getfid *
10324 ********************/
10327 /* hwrm_func_getfid_input (size:192b/24B) */
10328 struct hwrm_func_getfid_input {
10329 /* The HWRM command request type. */
10332 * The completion ring to send the completion event on. This should
10333 * be the NQ ID returned from the `nq_alloc` HWRM command.
10335 uint16_t cmpl_ring;
10337 * The sequence ID is used by the driver for tracking multiple
10338 * commands. This ID is treated as opaque data by the firmware and
10339 * the value is returned in the `hwrm_resp_hdr` upon completion.
10343 * The target ID of the command:
10344 * * 0x0-0xFFF8 - The function ID
10345 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
10346 * * 0xFFFD - Reserved for user-space HWRM interface
10349 uint16_t target_id;
10351 * A physical address pointer pointing to a host buffer that the
10352 * command's response data will be written. This can be either a host
10353 * physical address (HPA) or a guest physical address (GPA) and must
10354 * point to a physically contiguous block of memory.
10356 uint64_t resp_addr;
10359 * This bit must be '1' for the pci_id field to be
10362 #define HWRM_FUNC_GETFID_INPUT_ENABLES_PCI_ID UINT32_C(0x1)
10364 * This value is the PCI ID of the queried function.
10365 * If ARI is enabled, then it is
10366 * Bus Number (8b):Function Number(8b). Otherwise, it is
10367 * Bus Number (8b):Device Number (5b):Function Number(3b).
10370 uint8_t unused_0[2];
10373 /* hwrm_func_getfid_output (size:128b/16B) */
10374 struct hwrm_func_getfid_output {
10375 /* The specific error status for the command. */
10376 uint16_t error_code;
10377 /* The HWRM command request type. */
10379 /* The sequence ID from the original command. */
10381 /* The length of the response data in number of bytes. */
10384 * FID value. This value is used to identify operations on the PCI
10385 * bus as belonging to a particular PCI function.
10388 uint8_t unused_0[5];
10390 * This field is used in Output records to indicate that the output
10391 * is completely written to RAM. This field should be read as '1'
10392 * to indicate that the output has been completely written.
10393 * When writing a command completion or response to an internal processor,
10394 * the order of writes has to be such that this field is written last.
10399 /**********************
10400 * hwrm_func_vf_alloc *
10401 **********************/
10404 /* hwrm_func_vf_alloc_input (size:192b/24B) */
10405 struct hwrm_func_vf_alloc_input {
10406 /* The HWRM command request type. */
10409 * The completion ring to send the completion event on. This should
10410 * be the NQ ID returned from the `nq_alloc` HWRM command.
10412 uint16_t cmpl_ring;
10414 * The sequence ID is used by the driver for tracking multiple
10415 * commands. This ID is treated as opaque data by the firmware and
10416 * the value is returned in the `hwrm_resp_hdr` upon completion.
10420 * The target ID of the command:
10421 * * 0x0-0xFFF8 - The function ID
10422 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
10423 * * 0xFFFD - Reserved for user-space HWRM interface
10426 uint16_t target_id;
10428 * A physical address pointer pointing to a host buffer that the
10429 * command's response data will be written. This can be either a host
10430 * physical address (HPA) or a guest physical address (GPA) and must
10431 * point to a physically contiguous block of memory.
10433 uint64_t resp_addr;
10436 * This bit must be '1' for the first_vf_id field to be
10439 #define HWRM_FUNC_VF_ALLOC_INPUT_ENABLES_FIRST_VF_ID UINT32_C(0x1)
10441 * This value is used to identify a Virtual Function (VF).
10442 * The scope of VF ID is local within a PF.
10444 uint16_t first_vf_id;
10445 /* The number of virtual functions requested. */
10449 /* hwrm_func_vf_alloc_output (size:128b/16B) */
10450 struct hwrm_func_vf_alloc_output {
10451 /* The specific error status for the command. */
10452 uint16_t error_code;
10453 /* The HWRM command request type. */
10455 /* The sequence ID from the original command. */
10457 /* The length of the response data in number of bytes. */
10459 /* The ID of the first VF allocated. */
10460 uint16_t first_vf_id;
10461 uint8_t unused_0[5];
10463 * This field is used in Output records to indicate that the output
10464 * is completely written to RAM. This field should be read as '1'
10465 * to indicate that the output has been completely written.
10466 * When writing a command completion or response to an internal processor,
10467 * the order of writes has to be such that this field is written last.
10472 /*********************
10473 * hwrm_func_vf_free *
10474 *********************/
10477 /* hwrm_func_vf_free_input (size:192b/24B) */
10478 struct hwrm_func_vf_free_input {
10479 /* The HWRM command request type. */
10482 * The completion ring to send the completion event on. This should
10483 * be the NQ ID returned from the `nq_alloc` HWRM command.
10485 uint16_t cmpl_ring;
10487 * The sequence ID is used by the driver for tracking multiple
10488 * commands. This ID is treated as opaque data by the firmware and
10489 * the value is returned in the `hwrm_resp_hdr` upon completion.
10493 * The target ID of the command:
10494 * * 0x0-0xFFF8 - The function ID
10495 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
10496 * * 0xFFFD - Reserved for user-space HWRM interface
10499 uint16_t target_id;
10501 * A physical address pointer pointing to a host buffer that the
10502 * command's response data will be written. This can be either a host
10503 * physical address (HPA) or a guest physical address (GPA) and must
10504 * point to a physically contiguous block of memory.
10506 uint64_t resp_addr;
10509 * This bit must be '1' for the first_vf_id field to be
10512 #define HWRM_FUNC_VF_FREE_INPUT_ENABLES_FIRST_VF_ID UINT32_C(0x1)
10514 * This value is used to identify a Virtual Function (VF).
10515 * The scope of VF ID is local within a PF.
10517 uint16_t first_vf_id;
10519 * The number of virtual functions requested.
10520 * 0xFFFF - Cleanup all children of this PF.
10525 /* hwrm_func_vf_free_output (size:128b/16B) */
10526 struct hwrm_func_vf_free_output {
10527 /* The specific error status for the command. */
10528 uint16_t error_code;
10529 /* The HWRM command request type. */
10531 /* The sequence ID from the original command. */
10533 /* The length of the response data in number of bytes. */
10535 uint8_t unused_0[7];
10537 * This field is used in Output records to indicate that the output
10538 * is completely written to RAM. This field should be read as '1'
10539 * to indicate that the output has been completely written.
10540 * When writing a command completion or response to an internal processor,
10541 * the order of writes has to be such that this field is written last.
10546 /********************
10547 * hwrm_func_vf_cfg *
10548 ********************/
10551 /* hwrm_func_vf_cfg_input (size:448b/56B) */
10552 struct hwrm_func_vf_cfg_input {
10553 /* The HWRM command request type. */
10556 * The completion ring to send the completion event on. This should
10557 * be the NQ ID returned from the `nq_alloc` HWRM command.
10559 uint16_t cmpl_ring;
10561 * The sequence ID is used by the driver for tracking multiple
10562 * commands. This ID is treated as opaque data by the firmware and
10563 * the value is returned in the `hwrm_resp_hdr` upon completion.
10567 * The target ID of the command:
10568 * * 0x0-0xFFF8 - The function ID
10569 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
10570 * * 0xFFFD - Reserved for user-space HWRM interface
10573 uint16_t target_id;
10575 * A physical address pointer pointing to a host buffer that the
10576 * command's response data will be written. This can be either a host
10577 * physical address (HPA) or a guest physical address (GPA) and must
10578 * point to a physically contiguous block of memory.
10580 uint64_t resp_addr;
10583 * This bit must be '1' for the mtu field to be
10586 #define HWRM_FUNC_VF_CFG_INPUT_ENABLES_MTU \
10589 * This bit must be '1' for the guest_vlan field to be
10592 #define HWRM_FUNC_VF_CFG_INPUT_ENABLES_GUEST_VLAN \
10595 * This bit must be '1' for the async_event_cr field to be
10598 #define HWRM_FUNC_VF_CFG_INPUT_ENABLES_ASYNC_EVENT_CR \
10601 * This bit must be '1' for the dflt_mac_addr field to be
10604 #define HWRM_FUNC_VF_CFG_INPUT_ENABLES_DFLT_MAC_ADDR \
10607 * This bit must be '1' for the num_rsscos_ctxs field to be
10610 #define HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_RSSCOS_CTXS \
10613 * This bit must be '1' for the num_cmpl_rings field to be
10616 #define HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_CMPL_RINGS \
10619 * This bit must be '1' for the num_tx_rings field to be
10622 #define HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_TX_RINGS \
10625 * This bit must be '1' for the num_rx_rings field to be
10628 #define HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_RX_RINGS \
10631 * This bit must be '1' for the num_l2_ctxs field to be
10634 #define HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_L2_CTXS \
10637 * This bit must be '1' for the num_vnics field to be
10640 #define HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_VNICS \
10643 * This bit must be '1' for the num_stat_ctxs field to be
10646 #define HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_STAT_CTXS \
10649 * This bit must be '1' for the num_hw_ring_grps field to be
10652 #define HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_HW_RING_GRPS \
10655 * The maximum transmission unit requested on the function.
10656 * The HWRM should make sure that the mtu of
10657 * the function does not exceed the mtu of the physical
10658 * port that this function is associated with.
10660 * In addition to requesting mtu per function, it is
10661 * possible to configure mtu per transmit ring.
10662 * By default, the mtu of each transmit ring associated
10663 * with a function is equal to the mtu of the function.
10664 * The HWRM should make sure that the mtu of each transmit
10665 * ring that is assigned to a function has a valid mtu.
10669 * The guest VLAN for the function being configured.
10670 * This field's format is same as 802.1Q Tag's
10671 * Tag Control Information (TCI) format that includes both
10672 * Priority Code Point (PCP) and VLAN Identifier (VID).
10674 uint16_t guest_vlan;
10676 * ID of the target completion ring for receiving asynchronous
10677 * event completions. If this field is not valid, then the
10678 * HWRM shall use the default completion ring of the function
10679 * that is being configured as the target completion ring for
10680 * providing any asynchronous event completions for that
10682 * If this field is valid, then the HWRM shall use the
10683 * completion ring identified by this ID as the target
10684 * completion ring for providing any asynchronous event
10685 * completions for the function that is being configured.
10687 uint16_t async_event_cr;
10689 * This value is the current MAC address requested by the VF
10690 * driver to be configured on this VF. A value of
10691 * 00-00-00-00-00-00 indicates no MAC address configuration
10692 * is requested by the VF driver.
10693 * The parent PF driver may reject or overwrite this
10696 uint8_t dflt_mac_addr[6];
10699 * This bit requests that the firmware test to see if all the assets
10700 * requested in this command (i.e. number of TX rings) are available.
10701 * The firmware will return an error if the requested assets are
10702 * not available. The firwmare will NOT reserve the assets if they
10705 #define HWRM_FUNC_VF_CFG_INPUT_FLAGS_TX_ASSETS_TEST \
10708 * This bit requests that the firmware test to see if all the assets
10709 * requested in this command (i.e. number of RX rings) are available.
10710 * The firmware will return an error if the requested assets are
10711 * not available. The firwmare will NOT reserve the assets if they
10714 #define HWRM_FUNC_VF_CFG_INPUT_FLAGS_RX_ASSETS_TEST \
10717 * This bit requests that the firmware test to see if all the assets
10718 * requested in this command (i.e. number of CMPL rings) are available.
10719 * The firmware will return an error if the requested assets are
10720 * not available. The firwmare will NOT reserve the assets if they
10723 #define HWRM_FUNC_VF_CFG_INPUT_FLAGS_CMPL_ASSETS_TEST \
10726 * This bit requests that the firmware test to see if all the assets
10727 * requested in this command (i.e. number of RSS ctx) are available.
10728 * The firmware will return an error if the requested assets are
10729 * not available. The firwmare will NOT reserve the assets if they
10732 #define HWRM_FUNC_VF_CFG_INPUT_FLAGS_RSSCOS_CTX_ASSETS_TEST \
10735 * This bit requests that the firmware test to see if all the assets
10736 * requested in this command (i.e. number of ring groups) are available.
10737 * The firmware will return an error if the requested assets are
10738 * not available. The firwmare will NOT reserve the assets if they
10741 #define HWRM_FUNC_VF_CFG_INPUT_FLAGS_RING_GRP_ASSETS_TEST \
10744 * This bit requests that the firmware test to see if all the assets
10745 * requested in this command (i.e. number of stat ctx) are available.
10746 * The firmware will return an error if the requested assets are
10747 * not available. The firwmare will NOT reserve the assets if they
10750 #define HWRM_FUNC_VF_CFG_INPUT_FLAGS_STAT_CTX_ASSETS_TEST \
10753 * This bit requests that the firmware test to see if all the assets
10754 * requested in this command (i.e. number of VNICs) are available.
10755 * The firmware will return an error if the requested assets are
10756 * not available. The firwmare will NOT reserve the assets if they
10759 #define HWRM_FUNC_VF_CFG_INPUT_FLAGS_VNIC_ASSETS_TEST \
10762 * This bit requests that the firmware test to see if all the assets
10763 * requested in this command (i.e. number of L2 ctx) are available.
10764 * The firmware will return an error if the requested assets are
10765 * not available. The firwmare will NOT reserve the assets if they
10768 #define HWRM_FUNC_VF_CFG_INPUT_FLAGS_L2_CTX_ASSETS_TEST \
10771 * If this bit is set to 1, the VF driver is requesting FW to enable
10772 * PPP TX PUSH feature on all the TX rings specified in the
10773 * num_tx_rings field. By default, the PPP TX push feature is
10774 * disabled for all the TX rings of the VF. This flag is ignored if
10775 * the num_tx_rings field is not specified or the VF doesn't support
10776 * PPP tx push feature.
10778 #define HWRM_FUNC_VF_CFG_INPUT_FLAGS_PPP_PUSH_MODE_ENABLE \
10781 * If this bit is set to 1, the VF driver is requesting FW to disable
10782 * PPP TX PUSH feature on all the TX rings of the VF. This flag is
10783 * ignored if the VF doesn't support PPP tx push feature.
10785 #define HWRM_FUNC_VF_CFG_INPUT_FLAGS_PPP_PUSH_MODE_DISABLE \
10787 /* The number of RSS/COS contexts requested for the VF. */
10788 uint16_t num_rsscos_ctxs;
10789 /* The number of completion rings requested for the VF. */
10790 uint16_t num_cmpl_rings;
10791 /* The number of transmit rings requested for the VF. */
10792 uint16_t num_tx_rings;
10793 /* The number of receive rings requested for the VF. */
10794 uint16_t num_rx_rings;
10795 /* The number of L2 contexts requested for the VF. */
10796 uint16_t num_l2_ctxs;
10797 /* The number of vnics requested for the VF. */
10798 uint16_t num_vnics;
10799 /* The number of statistic contexts requested for the VF. */
10800 uint16_t num_stat_ctxs;
10801 /* The number of HW ring groups requested for the VF. */
10802 uint16_t num_hw_ring_grps;
10803 uint8_t unused_0[4];
10806 /* hwrm_func_vf_cfg_output (size:128b/16B) */
10807 struct hwrm_func_vf_cfg_output {
10808 /* The specific error status for the command. */
10809 uint16_t error_code;
10810 /* The HWRM command request type. */
10812 /* The sequence ID from the original command. */
10814 /* The length of the response data in number of bytes. */
10816 uint8_t unused_0[7];
10818 * This field is used in Output records to indicate that the output
10819 * is completely written to RAM. This field should be read as '1'
10820 * to indicate that the output has been completely written.
10821 * When writing a command completion or response to an internal processor,
10822 * the order of writes has to be such that this field is written last.
10827 /*******************
10828 * hwrm_func_qcaps *
10829 *******************/
10832 /* hwrm_func_qcaps_input (size:192b/24B) */
10833 struct hwrm_func_qcaps_input {
10834 /* The HWRM command request type. */
10837 * The completion ring to send the completion event on. This should
10838 * be the NQ ID returned from the `nq_alloc` HWRM command.
10840 uint16_t cmpl_ring;
10842 * The sequence ID is used by the driver for tracking multiple
10843 * commands. This ID is treated as opaque data by the firmware and
10844 * the value is returned in the `hwrm_resp_hdr` upon completion.
10848 * The target ID of the command:
10849 * * 0x0-0xFFF8 - The function ID
10850 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
10851 * * 0xFFFD - Reserved for user-space HWRM interface
10854 uint16_t target_id;
10856 * A physical address pointer pointing to a host buffer that the
10857 * command's response data will be written. This can be either a host
10858 * physical address (HPA) or a guest physical address (GPA) and must
10859 * point to a physically contiguous block of memory.
10861 uint64_t resp_addr;
10863 * Function ID of the function that is being queried.
10864 * 0xFF... (All Fs) if the query is for the requesting
10866 * 0xFFFE (REQUESTING_PARENT_FID) This is a special FID
10867 * to be used by a trusted VF to query its parent PF.
10870 uint8_t unused_0[6];
10873 /* hwrm_func_qcaps_output (size:704b/88B) */
10874 struct hwrm_func_qcaps_output {
10875 /* The specific error status for the command. */
10876 uint16_t error_code;
10877 /* The HWRM command request type. */
10879 /* The sequence ID from the original command. */
10881 /* The length of the response data in number of bytes. */
10884 * FID value. This value is used to identify operations on the PCI
10885 * bus as belonging to a particular PCI function.
10889 * Port ID of port that this function is associated with.
10890 * Valid only for the PF.
10891 * 0xFF... (All Fs) if this function is not associated with
10893 * 0xFF... (All Fs) if this function is called from a VF.
10897 /* If 1, then Push mode is supported on this function. */
10898 #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_PUSH_MODE_SUPPORTED \
10901 * If 1, then the global MSI-X auto-masking is enabled for the
10904 #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_GLOBAL_MSIX_AUTOMASKING \
10907 * If 1, then the Precision Time Protocol (PTP) processing
10908 * is supported on this function.
10909 * The HWRM should enable PTP on only a single Physical
10910 * Function (PF) per port.
10912 #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_PTP_SUPPORTED \
10915 * If 1, then RDMA over Converged Ethernet (RoCE) v1
10916 * is supported on this function.
10918 #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_ROCE_V1_SUPPORTED \
10921 * If 1, then RDMA over Converged Ethernet (RoCE) v2
10922 * is supported on this function.
10924 #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_ROCE_V2_SUPPORTED \
10927 * If 1, then control and configuration of WoL magic packet
10928 * are supported on this function.
10930 #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_WOL_MAGICPKT_SUPPORTED \
10933 * If 1, then control and configuration of bitmap pattern
10934 * packet are supported on this function.
10936 #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_WOL_BMP_SUPPORTED \
10939 * If set to 1, then the control and configuration of rate limit
10940 * of an allocated TX ring on the queried function is supported.
10942 #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_TX_RING_RL_SUPPORTED \
10945 * If 1, then control and configuration of minimum and
10946 * maximum bandwidths are supported on the queried function.
10948 #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_TX_BW_CFG_SUPPORTED \
10951 * If the query is for a VF, then this flag shall be ignored.
10952 * If this query is for a PF and this flag is set to 1,
10953 * then the PF has the capability to set the rate limits
10954 * on the TX rings of its children VFs.
10955 * If this query is for a PF and this flag is set to 0, then
10956 * the PF does not have the capability to set the rate limits
10957 * on the TX rings of its children VFs.
10959 #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_VF_TX_RING_RL_SUPPORTED \
10962 * If the query is for a VF, then this flag shall be ignored.
10963 * If this query is for a PF and this flag is set to 1,
10964 * then the PF has the capability to set the minimum and/or
10965 * maximum bandwidths for its children VFs.
10966 * If this query is for a PF and this flag is set to 0, then
10967 * the PF does not have the capability to set the minimum or
10968 * maximum bandwidths for its children VFs.
10970 #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_VF_BW_CFG_SUPPORTED \
10973 * Standard TX Ring mode is used for the allocation of TX ring
10974 * and underlying scheduling resources that allow bandwidth
10975 * reservation and limit settings on the queried function.
10976 * If set to 1, then standard TX ring mode is supported
10977 * on the queried function.
10978 * If set to 0, then standard TX ring mode is not available
10979 * on the queried function.
10981 #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_STD_TX_RING_MODE_SUPPORTED \
10984 * If the query is for a VF, then this flag shall be ignored,
10985 * If this query is for a PF and this flag is set to 1,
10986 * then the PF has the capability to detect GENEVE tunnel
10989 #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_GENEVE_TUN_FLAGS_SUPPORTED \
10992 * If the query is for a VF, then this flag shall be ignored,
10993 * If this query is for a PF and this flag is set to 1,
10994 * then the PF has the capability to detect NVGRE tunnel
10997 #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_NVGRE_TUN_FLAGS_SUPPORTED \
11000 * If the query is for a VF, then this flag shall be ignored,
11001 * If this query is for a PF and this flag is set to 1,
11002 * then the PF has the capability to detect GRE tunnel
11005 #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_GRE_TUN_FLAGS_SUPPORTED \
11008 * If the query is for a VF, then this flag shall be ignored,
11009 * If this query is for a PF and this flag is set to 1,
11010 * then the PF has the capability to detect MPLS tunnel
11013 #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_MPLS_TUN_FLAGS_SUPPORTED \
11016 * If the query is for a VF, then this flag shall be ignored,
11017 * If this query is for a PF and this flag is set to 1,
11018 * then the PF has the capability to support pcie stats.
11020 #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_PCIE_STATS_SUPPORTED \
11023 * If the query is for a VF, then this flag shall be ignored,
11024 * If this query is for a PF and this flag is set to 1,
11025 * then the PF has the capability to adopt the VF's belonging
11028 #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_ADOPTED_PF_SUPPORTED \
11031 * If the query is for a VF, then this flag shall be ignored,
11032 * If this query is for a PF and this flag is set to 1,
11033 * then the PF has the administrative privilege to configure another PF
11035 #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_ADMIN_PF_SUPPORTED \
11038 * If the query is for a VF, then this flag shall be ignored.
11039 * If this query is for a PF and this flag is set to 1, then
11040 * the PF will know that the firmware has the capability to track
11041 * the virtual link status.
11043 #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_LINK_ADMIN_STATUS_SUPPORTED \
11046 * If 1, then this function supports the push mode that uses
11047 * write combine buffers and the long inline tx buffer descriptor.
11049 #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_WCB_PUSH_MODE \
11052 * If 1, then FW has capability to allocate TX rings dynamically
11053 * in ring alloc even if PF reserved pool is zero.
11054 * This bit will be used only for PFs.
11056 #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_DYNAMIC_TX_RING_ALLOC \
11059 * When this bit is '1', it indicates that core firmware is
11060 * capable of Hot Reset.
11062 #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_HOT_RESET_CAPABLE \
11065 * This flag will be set to 1 by the FW if FW supports adapter error
11068 #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_ERROR_RECOVERY_CAPABLE \
11071 * If the query is for a VF, then this flag shall be ignored.
11072 * If this query is for a PF and this flag is set to 1, then
11073 * the PF has the capability to support extended stats.
11075 #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_EXT_STATS_SUPPORTED \
11076 UINT32_C(0x1000000)
11078 * If the query is for a VF, then this flag shall be ignored.
11079 * If this query is for a PF and this flag is set to 1, then host
11080 * must initiate reset or reload (or fastboot) the firmware image
11081 * upon detection of device shutdown state.
11083 #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_ERR_RECOVER_RELOAD \
11084 UINT32_C(0x2000000)
11086 * If the query is for a VF, then this flag (always set to 0) shall
11087 * be ignored. If this query is for a PF and this flag is set to 1,
11088 * host, when registered for the default vnic change async event,
11089 * receives async notification whenever a default vnic state is
11090 * changed for any of child or adopted VFs.
11092 #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_NOTIFY_VF_DEF_VNIC_CHNG_SUPPORTED \
11093 UINT32_C(0x4000000)
11094 /* If set to 1, then the vlan acceleration for TX is disabled. */
11095 #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_VLAN_ACCELERATION_TX_DISABLED \
11096 UINT32_C(0x8000000)
11098 * When this bit is '1', it indicates that core firmware supports
11099 * DBG_COREDUMP_XXX commands.
11101 #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_COREDUMP_CMD_SUPPORTED \
11102 UINT32_C(0x10000000)
11104 * When this bit is '1', it indicates that core firmware supports
11105 * DBG_CRASHDUMP_XXX commands.
11107 #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_CRASHDUMP_CMD_SUPPORTED \
11108 UINT32_C(0x20000000)
11110 * If the query is for a VF, then this flag should be ignored.
11111 * If the query is for a PF and this flag is set to 1, then
11112 * the PF has the capability to support retrieval of
11113 * rx_port_stats_ext_pfc_wd statistics (supported by the PFC
11114 * WatchDog feature) via the hwrm_port_qstats_ext_pfc_wd command.
11115 * If this flag is set to 1, only that (supported) command should
11116 * be used for retrieval of PFC related statistics (rather than
11117 * hwrm_port_qstats_ext command, which could previously be used).
11119 #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_PFC_WD_STATS_SUPPORTED \
11120 UINT32_C(0x40000000)
11122 * When this bit is '1', it indicates that core firmware supports
11123 * DBG_QCAPS command
11125 #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_DBG_QCAPS_CMD_SUPPORTED \
11126 UINT32_C(0x80000000)
11128 * This value is current MAC address configured for this
11129 * function. A value of 00-00-00-00-00-00 indicates no
11130 * MAC address is currently configured.
11132 uint8_t mac_address[6];
11134 * The maximum number of RSS/COS contexts that can be
11135 * allocated to the function.
11137 uint16_t max_rsscos_ctx;
11139 * The maximum number of completion rings that can be
11140 * allocated to the function.
11142 uint16_t max_cmpl_rings;
11144 * The maximum number of transmit rings that can be
11145 * allocated to the function.
11147 uint16_t max_tx_rings;
11149 * The maximum number of receive rings that can be
11150 * allocated to the function.
11152 uint16_t max_rx_rings;
11154 * The maximum number of L2 contexts that can be
11155 * allocated to the function.
11157 uint16_t max_l2_ctxs;
11159 * The maximum number of VNICs that can be
11160 * allocated to the function.
11162 uint16_t max_vnics;
11164 * The identifier for the first VF enabled on a PF. This
11165 * is valid only on the PF with SR-IOV enabled.
11166 * 0xFF... (All Fs) if this command is called on a PF with
11167 * SR-IOV disabled or on a VF.
11169 uint16_t first_vf_id;
11171 * The maximum number of VFs that can be
11172 * allocated to the function. This is valid only on the
11173 * PF with SR-IOV enabled. 0xFF... (All Fs) if this
11174 * command is called on a PF with SR-IOV disabled or
11179 * The maximum number of statistic contexts that can be
11180 * allocated to the function.
11182 uint16_t max_stat_ctx;
11184 * The maximum number of Encapsulation records that can be
11185 * offloaded by this function.
11187 uint32_t max_encap_records;
11189 * The maximum number of decapsulation records that can
11190 * be offloaded by this function.
11192 uint32_t max_decap_records;
11194 * The maximum number of Exact Match (EM) flows that can be
11195 * offloaded by this function on the TX side.
11197 uint32_t max_tx_em_flows;
11199 * The maximum number of Wildcard Match (WM) flows that can
11200 * be offloaded by this function on the TX side.
11202 uint32_t max_tx_wm_flows;
11204 * The maximum number of Exact Match (EM) flows that can be
11205 * offloaded by this function on the RX side.
11207 uint32_t max_rx_em_flows;
11209 * The maximum number of Wildcard Match (WM) flows that can
11210 * be offloaded by this function on the RX side.
11212 uint32_t max_rx_wm_flows;
11214 * The maximum number of multicast filters that can
11215 * be supported by this function on the RX side.
11217 uint32_t max_mcast_filters;
11219 * The maximum value of flow_id that can be supported
11220 * in completion records.
11222 uint32_t max_flow_id;
11224 * The maximum number of HW ring groups that can be
11225 * supported on this function.
11227 uint32_t max_hw_ring_grps;
11229 * The maximum number of strict priority transmit rings
11230 * that can be allocated to the function.
11231 * This number indicates the maximum number of TX rings
11232 * that can be assigned strict priorities out of the
11233 * maximum number of TX rings that can be allocated
11234 * (max_tx_rings) to the function.
11236 uint16_t max_sp_tx_rings;
11237 uint8_t unused_0[2];
11238 uint32_t flags_ext;
11240 * If 1, the device can be configured to set the ECN bits in the
11241 * IP header of received packets if the receive queue length
11242 * exceeds a given threshold.
11244 #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_EXT_ECN_MARK_SUPPORTED \
11247 * If 1, the device can report the number of received packets
11248 * that it marked as having experienced congestion.
11250 #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_EXT_ECN_STATS_SUPPORTED \
11253 * If 1, the device can report extended hw statistics (including
11254 * additional tpa statistics).
11256 #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_EXT_EXT_HW_STATS_SUPPORTED \
11259 * If set to 1, then the core firmware has support to enable/
11260 * disable hot reset support for interface dynamically through
11263 #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_EXT_HOT_RESET_IF_SUPPORT \
11265 /* If 1, the proxy mode is supported on this function */
11266 #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_EXT_PROXY_MODE_SUPPORT \
11269 * If 1, the tx rings source interface override feature is supported
11270 * on this function.
11272 #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_EXT_TX_PROXY_SRC_INTF_OVERRIDE_SUPPORT \
11275 * If 1, the device supports scheduler queues. SCHQs can be managed
11276 * using RING_SCHQ_ALLOC/CFG/FREE commands.
11278 #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_EXT_SCHQ_SUPPORTED \
11281 * If set to 1, then this function supports the TX push mode that
11282 * uses ping-pong buffers from the push pages.
11284 #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_EXT_PPP_PUSH_MODE_SUPPORTED \
11287 * If set to 1, then this function doesn't have the privilege to
11288 * configure the EVB mode of the port it uses.
11290 #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_EXT_EVB_MODE_CFG_NOT_SUPPORTED \
11293 * If set to 1, then the HW and FW support the SoC packet DMA
11294 * datapath between SoC and NIC. This function can act as the
11295 * HWRM communication transport agent on behalf of the SoC SPD
11296 * software module. This capability is only advertised to the
11299 #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_EXT_SOC_SPD_SUPPORTED \
11302 * If set to 1, then this function supports FW_LIVEPATCH for
11303 * firmware livepatch commands.
11305 #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_EXT_FW_LIVEPATCH_SUPPORTED \
11308 * When this bit is '1', it indicates that core firmware is
11309 * capable of fast Reset.
11311 #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_EXT_FAST_RESET_CAPABLE \
11314 * When this bit is '1', it indicates that firmware and hardware
11315 * are capable of updating tx_metadata via hwrm_ring_cfg command.
11317 #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_EXT_TX_METADATA_CFG_CAPABLE \
11320 * If set to 1, then the device can report the action
11321 * needed to activate set nvm options.
11323 #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_EXT_NVM_OPTION_ACTION_SUPPORTED \
11326 * When this bit is '1', it indicates that the BD metadata feature
11327 * is supported for this function.
11329 #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_EXT_BD_METADATA_SUPPORTED \
11332 * When this bit is '1', it indicates that the echo request feature
11333 * is supported for this function. If the driver registers for the
11334 * echo request asynchronous event, then the firmware can send an
11335 * unsolicited echo request to the driver and expect an echo
11338 #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_EXT_ECHO_REQUEST_SUPPORTED \
11340 /* The maximum number of SCHQs supported by this device. */
11342 uint8_t mpc_chnls_cap;
11344 * When this bit is '1', it indicates that HW and firmware
11345 * supports the use of a MPC channel with destination set
11346 * to the TX crypto engine block.
11348 #define HWRM_FUNC_QCAPS_OUTPUT_MPC_CHNLS_CAP_TCE UINT32_C(0x1)
11350 * When this bit is '1', it indicates that HW and firmware
11351 * supports the use of a MPC channel with destination set
11352 * to the RX crypto engine block.
11354 #define HWRM_FUNC_QCAPS_OUTPUT_MPC_CHNLS_CAP_RCE UINT32_C(0x2)
11356 * When this bit is '1', it indicates that HW and firmware
11357 * supports the use of a MPC channel with destination set
11358 * to the TX configurable flow processing block.
11360 #define HWRM_FUNC_QCAPS_OUTPUT_MPC_CHNLS_CAP_TE_CFA UINT32_C(0x4)
11362 * When this bit is '1', it indicates that HW and firmware
11363 * supports the use of a MPC channel with destination set
11364 * to the RX configurable flow processing block.
11366 #define HWRM_FUNC_QCAPS_OUTPUT_MPC_CHNLS_CAP_RE_CFA UINT32_C(0x8)
11368 * When this bit is '1', it indicates that HW and firmware
11369 * supports the use of a MPC channel with destination set
11370 * to the primate processor block.
11372 #define HWRM_FUNC_QCAPS_OUTPUT_MPC_CHNLS_CAP_PRIMATE UINT32_C(0x10)
11375 * This field is used in Output records to indicate that the output
11376 * is completely written to RAM. This field should be read as '1'
11377 * to indicate that the output has been completely written.
11378 * When writing a command completion or response to an internal processor,
11379 * the order of writes has to be such that this field is written last.
11384 /******************
11386 ******************/
11389 /* hwrm_func_qcfg_input (size:192b/24B) */
11390 struct hwrm_func_qcfg_input {
11391 /* The HWRM command request type. */
11394 * The completion ring to send the completion event on. This should
11395 * be the NQ ID returned from the `nq_alloc` HWRM command.
11397 uint16_t cmpl_ring;
11399 * The sequence ID is used by the driver for tracking multiple
11400 * commands. This ID is treated as opaque data by the firmware and
11401 * the value is returned in the `hwrm_resp_hdr` upon completion.
11405 * The target ID of the command:
11406 * * 0x0-0xFFF8 - The function ID
11407 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
11408 * * 0xFFFD - Reserved for user-space HWRM interface
11411 uint16_t target_id;
11413 * A physical address pointer pointing to a host buffer that the
11414 * command's response data will be written. This can be either a host
11415 * physical address (HPA) or a guest physical address (GPA) and must
11416 * point to a physically contiguous block of memory.
11418 uint64_t resp_addr;
11420 * Function ID of the function that is being queried.
11421 * 0xFF... (All Fs) if the query is for the requesting
11423 * 0xFFFE (REQUESTING_PARENT_FID) This is a special FID
11424 * to be used by a trusted VF to query its parent PF.
11427 uint8_t unused_0[6];
11430 /* hwrm_func_qcfg_output (size:768b/96B) */
11431 struct hwrm_func_qcfg_output {
11432 /* The specific error status for the command. */
11433 uint16_t error_code;
11434 /* The HWRM command request type. */
11436 /* The sequence ID from the original command. */
11438 /* The length of the response data in number of bytes. */
11441 * FID value. This value is used to identify operations on the PCI
11442 * bus as belonging to a particular PCI function.
11446 * Port ID of port that this function is associated with.
11447 * 0xFF... (All Fs) if this function is not associated with
11452 * This value is the current VLAN setting for this
11453 * function. The value of 0 for this field indicates
11454 * no priority tagging or VLAN is used.
11455 * This field's format is same as 802.1Q Tag's
11456 * Tag Control Information (TCI) format that includes both
11457 * Priority Code Point (PCP) and VLAN Identifier (VID).
11462 * If 1, then magic packet based Out-Of-Box WoL is enabled on
11463 * the port associated with this function.
11465 #define HWRM_FUNC_QCFG_OUTPUT_FLAGS_OOB_WOL_MAGICPKT_ENABLED \
11468 * If 1, then bitmap pattern based Out-Of-Box WoL packet is enabled
11469 * on the port associated with this function.
11471 #define HWRM_FUNC_QCFG_OUTPUT_FLAGS_OOB_WOL_BMP_ENABLED \
11474 * If set to 1, then FW based DCBX agent is enabled and running on
11475 * the port associated with this function.
11476 * If set to 0, then DCBX agent is not running in the firmware.
11478 #define HWRM_FUNC_QCFG_OUTPUT_FLAGS_FW_DCBX_AGENT_ENABLED \
11481 * Standard TX Ring mode is used for the allocation of TX ring
11482 * and underlying scheduling resources that allow bandwidth
11483 * reservation and limit settings on the queried function.
11484 * If set to 1, then standard TX ring mode is enabled
11485 * on the queried function.
11486 * If set to 0, then the standard TX ring mode is disabled
11487 * on the queried function. In this extended TX ring resource
11488 * mode, the minimum and maximum bandwidth settings are not
11489 * supported to allow the allocation of TX rings to span multiple
11492 #define HWRM_FUNC_QCFG_OUTPUT_FLAGS_STD_TX_RING_MODE_ENABLED \
11495 * If set to 1 then FW based LLDP agent is enabled and running on
11496 * the port associated with this function.
11497 * If set to 0 then the LLDP agent is not running in the firmware.
11499 #define HWRM_FUNC_QCFG_OUTPUT_FLAGS_FW_LLDP_AGENT_ENABLED \
11502 * If set to 1, then multi-host mode is active for this function.
11503 * The NIC is attached to two or more independent host systems
11504 * through two or more PCIe endpoints.
11505 * If set to 0, then multi-host mode is inactive for this function
11506 * or not applicable for this device.
11508 #define HWRM_FUNC_QCFG_OUTPUT_FLAGS_MULTI_HOST \
11511 * If the function that is being queried is a PF, then the HWRM shall
11512 * set this field to 0 and the HWRM client shall ignore this field.
11513 * If the function that is being queried is a VF, then the HWRM shall
11514 * set this field to 1 if the queried VF is trusted, otherwise the HWRM
11515 * shall set this field to 0.
11517 #define HWRM_FUNC_QCFG_OUTPUT_FLAGS_TRUSTED_VF \
11520 * If set to 1, then secure mode is enabled for this function or device.
11521 * If set to 0, then secure mode is disabled (or normal mode) for this
11522 * function or device.
11524 #define HWRM_FUNC_QCFG_OUTPUT_FLAGS_SECURE_MODE_ENABLED \
11527 * If set to 1, then this PF is enabled with a preboot driver that
11528 * requires access to the legacy L2 ring model and legacy 32b
11529 * doorbells. If set to 0, then this PF is not allowed to use
11530 * the legacy L2 rings. This feature is not allowed on VFs and
11531 * is only relevant for devices that require a context backing
11534 #define HWRM_FUNC_QCFG_OUTPUT_FLAGS_PREBOOT_LEGACY_L2_RINGS \
11537 * If set to 1, then the firmware and all currently registered driver
11538 * instances support hot reset. The hot reset support will be updated
11539 * dynamically based on the driver interface advertisement.
11540 * If set to 0, then the adapter is not currently able to initiate
11543 #define HWRM_FUNC_QCFG_OUTPUT_FLAGS_HOT_RESET_ALLOWED \
11546 * If set to 1, then the PPP tx push mode is enabled for all the
11547 * reserved TX rings of this function. If set to 0, then PPP tx push
11548 * mode is disabled for all the reserved TX rings of this function.
11550 #define HWRM_FUNC_QCFG_OUTPUT_FLAGS_PPP_PUSH_MODE_ENABLED \
11553 * If set to 1, then the firmware will notify driver using async
11554 * event when a ring is disabled due to a Hardware error.
11556 #define HWRM_FUNC_QCFG_OUTPUT_FLAGS_RING_MONITOR_ENABLED \
11559 * If set to 1, then the firmware and all currently registered driver
11560 * instances support fast reset. The fast reset support will be
11561 * updated dynamically based on the driver interface advertisement.
11562 * If set to 0, then the adapter is not currently able to initiate
11565 #define HWRM_FUNC_QCFG_OUTPUT_FLAGS_FAST_RESET_ALLOWED \
11568 * If set to 1, then multi-root mode is active for this function.
11569 * The NIC is attached to a single host with a single operating
11570 * system, but through two or more PCIe endpoints.
11571 * If set to 0, then multi-root mode is inactive for this function
11572 * or not applicable for this device.
11574 #define HWRM_FUNC_QCFG_OUTPUT_FLAGS_MULTI_ROOT \
11577 * This value is current MAC address configured for this
11578 * function. A value of 00-00-00-00-00-00 indicates no
11579 * MAC address is currently configured.
11581 uint8_t mac_address[6];
11583 * This value is current PCI ID of this
11584 * function. If ARI is enabled, then it is
11585 * Bus Number (8b):Function Number(8b). Otherwise, it is
11586 * Bus Number (8b):Device Number (4b):Function Number(4b).
11587 * If multi-host mode is active, the 4 lsb will indicate
11588 * the PF index for this function.
11592 * The number of RSS/COS contexts currently
11593 * allocated to the function.
11595 uint16_t alloc_rsscos_ctx;
11597 * The number of completion rings currently allocated to
11598 * the function. This does not include the rings allocated
11599 * to any children functions if any.
11601 uint16_t alloc_cmpl_rings;
11603 * The number of transmit rings currently allocated to
11604 * the function. This does not include the rings allocated
11605 * to any children functions if any.
11607 uint16_t alloc_tx_rings;
11609 * The number of receive rings currently allocated to
11610 * the function. This does not include the rings allocated
11611 * to any children functions if any.
11613 uint16_t alloc_rx_rings;
11614 /* The allocated number of L2 contexts to the function. */
11615 uint16_t alloc_l2_ctx;
11616 /* The allocated number of vnics to the function. */
11617 uint16_t alloc_vnics;
11619 * The maximum transmission unit of the function.
11620 * If the reported mtu value is non-zero then it will used for the
11621 * rings allocated on this function. otherwise the default
11622 * value is used if ring MTU is not specified.
11626 * The maximum receive unit of the function.
11627 * For vnics allocated on this function, this default
11628 * value is used if vnic MRU is not specified.
11631 /* The statistics context assigned to a function. */
11632 uint16_t stat_ctx_id;
11634 * The HWRM shall return Unknown value for this field
11635 * when this command is used to query VF's configuration.
11637 uint8_t port_partition_type;
11638 /* Single physical function */
11639 #define HWRM_FUNC_QCFG_OUTPUT_PORT_PARTITION_TYPE_SPF UINT32_C(0x0)
11640 /* Multiple physical functions */
11641 #define HWRM_FUNC_QCFG_OUTPUT_PORT_PARTITION_TYPE_MPFS UINT32_C(0x1)
11642 /* Network Partitioning 1.0 */
11643 #define HWRM_FUNC_QCFG_OUTPUT_PORT_PARTITION_TYPE_NPAR1_0 UINT32_C(0x2)
11644 /* Network Partitioning 1.5 */
11645 #define HWRM_FUNC_QCFG_OUTPUT_PORT_PARTITION_TYPE_NPAR1_5 UINT32_C(0x3)
11646 /* Network Partitioning 2.0 */
11647 #define HWRM_FUNC_QCFG_OUTPUT_PORT_PARTITION_TYPE_NPAR2_0 UINT32_C(0x4)
11649 #define HWRM_FUNC_QCFG_OUTPUT_PORT_PARTITION_TYPE_UNKNOWN \
11651 #define HWRM_FUNC_QCFG_OUTPUT_PORT_PARTITION_TYPE_LAST \
11652 HWRM_FUNC_QCFG_OUTPUT_PORT_PARTITION_TYPE_UNKNOWN
11654 * This field will indicate number of physical functions on this port_partition.
11655 * HWRM shall return unavail (i.e. value of 0) for this field
11656 * when this command is used to query VF's configuration or
11657 * from older firmware that doesn't support this field.
11659 uint8_t port_pf_cnt;
11660 /* number of PFs is not available */
11661 #define HWRM_FUNC_QCFG_OUTPUT_PORT_PF_CNT_UNAVAIL UINT32_C(0x0)
11662 #define HWRM_FUNC_QCFG_OUTPUT_PORT_PF_CNT_LAST \
11663 HWRM_FUNC_QCFG_OUTPUT_PORT_PF_CNT_UNAVAIL
11665 * The default VNIC ID assigned to a function that is
11668 uint16_t dflt_vnic_id;
11669 uint16_t max_mtu_configured;
11671 * Minimum BW allocated for this function.
11672 * The HWRM will translate this value into byte counter and
11673 * time interval used for the scheduler inside the device.
11674 * A value of 0 indicates the minimum bandwidth is not
11678 /* The bandwidth value. */
11679 #define HWRM_FUNC_QCFG_OUTPUT_MIN_BW_BW_VALUE_MASK \
11680 UINT32_C(0xfffffff)
11681 #define HWRM_FUNC_QCFG_OUTPUT_MIN_BW_BW_VALUE_SFT 0
11682 /* The granularity of the value (bits or bytes). */
11683 #define HWRM_FUNC_QCFG_OUTPUT_MIN_BW_SCALE \
11684 UINT32_C(0x10000000)
11685 /* Value is in bits. */
11686 #define HWRM_FUNC_QCFG_OUTPUT_MIN_BW_SCALE_BITS \
11687 (UINT32_C(0x0) << 28)
11688 /* Value is in bytes. */
11689 #define HWRM_FUNC_QCFG_OUTPUT_MIN_BW_SCALE_BYTES \
11690 (UINT32_C(0x1) << 28)
11691 #define HWRM_FUNC_QCFG_OUTPUT_MIN_BW_SCALE_LAST \
11692 HWRM_FUNC_QCFG_OUTPUT_MIN_BW_SCALE_BYTES
11693 /* bw_value_unit is 3 b */
11694 #define HWRM_FUNC_QCFG_OUTPUT_MIN_BW_BW_VALUE_UNIT_MASK \
11695 UINT32_C(0xe0000000)
11696 #define HWRM_FUNC_QCFG_OUTPUT_MIN_BW_BW_VALUE_UNIT_SFT 29
11697 /* Value is in Mb or MB (base 10). */
11698 #define HWRM_FUNC_QCFG_OUTPUT_MIN_BW_BW_VALUE_UNIT_MEGA \
11699 (UINT32_C(0x0) << 29)
11700 /* Value is in Kb or KB (base 10). */
11701 #define HWRM_FUNC_QCFG_OUTPUT_MIN_BW_BW_VALUE_UNIT_KILO \
11702 (UINT32_C(0x2) << 29)
11703 /* Value is in bits or bytes. */
11704 #define HWRM_FUNC_QCFG_OUTPUT_MIN_BW_BW_VALUE_UNIT_BASE \
11705 (UINT32_C(0x4) << 29)
11706 /* Value is in Gb or GB (base 10). */
11707 #define HWRM_FUNC_QCFG_OUTPUT_MIN_BW_BW_VALUE_UNIT_GIGA \
11708 (UINT32_C(0x6) << 29)
11709 /* Value is in 1/100th of a percentage of total bandwidth. */
11710 #define HWRM_FUNC_QCFG_OUTPUT_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 \
11711 (UINT32_C(0x1) << 29)
11713 #define HWRM_FUNC_QCFG_OUTPUT_MIN_BW_BW_VALUE_UNIT_INVALID \
11714 (UINT32_C(0x7) << 29)
11715 #define HWRM_FUNC_QCFG_OUTPUT_MIN_BW_BW_VALUE_UNIT_LAST \
11716 HWRM_FUNC_QCFG_OUTPUT_MIN_BW_BW_VALUE_UNIT_INVALID
11718 * Maximum BW allocated for this function.
11719 * The HWRM will translate this value into byte counter and
11720 * time interval used for the scheduler inside the device.
11721 * A value of 0 indicates that the maximum bandwidth is not
11725 /* The bandwidth value. */
11726 #define HWRM_FUNC_QCFG_OUTPUT_MAX_BW_BW_VALUE_MASK \
11727 UINT32_C(0xfffffff)
11728 #define HWRM_FUNC_QCFG_OUTPUT_MAX_BW_BW_VALUE_SFT 0
11729 /* The granularity of the value (bits or bytes). */
11730 #define HWRM_FUNC_QCFG_OUTPUT_MAX_BW_SCALE \
11731 UINT32_C(0x10000000)
11732 /* Value is in bits. */
11733 #define HWRM_FUNC_QCFG_OUTPUT_MAX_BW_SCALE_BITS \
11734 (UINT32_C(0x0) << 28)
11735 /* Value is in bytes. */
11736 #define HWRM_FUNC_QCFG_OUTPUT_MAX_BW_SCALE_BYTES \
11737 (UINT32_C(0x1) << 28)
11738 #define HWRM_FUNC_QCFG_OUTPUT_MAX_BW_SCALE_LAST \
11739 HWRM_FUNC_QCFG_OUTPUT_MAX_BW_SCALE_BYTES
11740 /* bw_value_unit is 3 b */
11741 #define HWRM_FUNC_QCFG_OUTPUT_MAX_BW_BW_VALUE_UNIT_MASK \
11742 UINT32_C(0xe0000000)
11743 #define HWRM_FUNC_QCFG_OUTPUT_MAX_BW_BW_VALUE_UNIT_SFT 29
11744 /* Value is in Mb or MB (base 10). */
11745 #define HWRM_FUNC_QCFG_OUTPUT_MAX_BW_BW_VALUE_UNIT_MEGA \
11746 (UINT32_C(0x0) << 29)
11747 /* Value is in Kb or KB (base 10). */
11748 #define HWRM_FUNC_QCFG_OUTPUT_MAX_BW_BW_VALUE_UNIT_KILO \
11749 (UINT32_C(0x2) << 29)
11750 /* Value is in bits or bytes. */
11751 #define HWRM_FUNC_QCFG_OUTPUT_MAX_BW_BW_VALUE_UNIT_BASE \
11752 (UINT32_C(0x4) << 29)
11753 /* Value is in Gb or GB (base 10). */
11754 #define HWRM_FUNC_QCFG_OUTPUT_MAX_BW_BW_VALUE_UNIT_GIGA \
11755 (UINT32_C(0x6) << 29)
11756 /* Value is in 1/100th of a percentage of total bandwidth. */
11757 #define HWRM_FUNC_QCFG_OUTPUT_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 \
11758 (UINT32_C(0x1) << 29)
11760 #define HWRM_FUNC_QCFG_OUTPUT_MAX_BW_BW_VALUE_UNIT_INVALID \
11761 (UINT32_C(0x7) << 29)
11762 #define HWRM_FUNC_QCFG_OUTPUT_MAX_BW_BW_VALUE_UNIT_LAST \
11763 HWRM_FUNC_QCFG_OUTPUT_MAX_BW_BW_VALUE_UNIT_INVALID
11765 * This value indicates the Edge virtual bridge mode for the
11766 * domain that this function belongs to.
11769 /* No Edge Virtual Bridging (EVB) */
11770 #define HWRM_FUNC_QCFG_OUTPUT_EVB_MODE_NO_EVB UINT32_C(0x0)
11771 /* Virtual Ethernet Bridge (VEB) */
11772 #define HWRM_FUNC_QCFG_OUTPUT_EVB_MODE_VEB UINT32_C(0x1)
11773 /* Virtual Ethernet Port Aggregator (VEPA) */
11774 #define HWRM_FUNC_QCFG_OUTPUT_EVB_MODE_VEPA UINT32_C(0x2)
11775 #define HWRM_FUNC_QCFG_OUTPUT_EVB_MODE_LAST \
11776 HWRM_FUNC_QCFG_OUTPUT_EVB_MODE_VEPA
11779 * This value indicates the PCIE device cache line size.
11780 * The cache line size allows the DMA writes to terminate and
11781 * start at the cache boundary.
11783 #define HWRM_FUNC_QCFG_OUTPUT_OPTIONS_CACHE_LINESIZE_MASK \
11785 #define HWRM_FUNC_QCFG_OUTPUT_OPTIONS_CACHE_LINESIZE_SFT 0
11786 /* Cache Line Size 64 bytes */
11787 #define HWRM_FUNC_QCFG_OUTPUT_OPTIONS_CACHE_LINESIZE_SIZE_64 \
11789 /* Cache Line Size 128 bytes */
11790 #define HWRM_FUNC_QCFG_OUTPUT_OPTIONS_CACHE_LINESIZE_SIZE_128 \
11792 #define HWRM_FUNC_QCFG_OUTPUT_OPTIONS_CACHE_LINESIZE_LAST \
11793 HWRM_FUNC_QCFG_OUTPUT_OPTIONS_CACHE_LINESIZE_SIZE_128
11794 /* This value is the virtual link admin state setting. */
11795 #define HWRM_FUNC_QCFG_OUTPUT_OPTIONS_LINK_ADMIN_STATE_MASK \
11797 #define HWRM_FUNC_QCFG_OUTPUT_OPTIONS_LINK_ADMIN_STATE_SFT 2
11798 /* Admin link state is in forced down mode. */
11799 #define HWRM_FUNC_QCFG_OUTPUT_OPTIONS_LINK_ADMIN_STATE_FORCED_DOWN \
11800 (UINT32_C(0x0) << 2)
11801 /* Admin link state is in forced up mode. */
11802 #define HWRM_FUNC_QCFG_OUTPUT_OPTIONS_LINK_ADMIN_STATE_FORCED_UP \
11803 (UINT32_C(0x1) << 2)
11804 /* Admin link state is in auto mode - follows the physical link state. */
11805 #define HWRM_FUNC_QCFG_OUTPUT_OPTIONS_LINK_ADMIN_STATE_AUTO \
11806 (UINT32_C(0x2) << 2)
11807 #define HWRM_FUNC_QCFG_OUTPUT_OPTIONS_LINK_ADMIN_STATE_LAST \
11808 HWRM_FUNC_QCFG_OUTPUT_OPTIONS_LINK_ADMIN_STATE_AUTO
11809 /* Reserved for future. */
11810 #define HWRM_FUNC_QCFG_OUTPUT_OPTIONS_RSVD_MASK \
11812 #define HWRM_FUNC_QCFG_OUTPUT_OPTIONS_RSVD_SFT 4
11814 * The number of VFs that are allocated to the function.
11815 * This is valid only on the PF with SR-IOV enabled.
11816 * 0xFF... (All Fs) if this command is called on a PF with
11817 * SR-IOV disabled or on a VF.
11819 uint16_t alloc_vfs;
11821 * The number of allocated multicast filters for this
11822 * function on the RX side.
11824 uint32_t alloc_mcast_filters;
11826 * The number of allocated HW ring groups for this
11829 uint32_t alloc_hw_ring_grps;
11831 * The number of strict priority transmit rings out of
11832 * currently allocated TX rings to the function
11833 * (alloc_tx_rings).
11835 uint16_t alloc_sp_tx_rings;
11837 * The number of statistics contexts
11838 * currently reserved for the function.
11840 uint16_t alloc_stat_ctx;
11842 * This field specifies how many NQs are reserved for the PF.
11843 * Remaining NQs that belong to the PF are available for VFs.
11844 * Once a PF has created VFs, it cannot change how many NQs are
11845 * reserved for itself (since the NQs must be contiguous in HW).
11847 uint16_t alloc_msix;
11849 * The number of registered VF’s associated with the PF. This field
11850 * should be ignored when the request received on the VF interface.
11851 * This field will be updated on the PF interface to initiate
11852 * the unregister request on PF in the HOT Reset Process.
11854 uint16_t registered_vfs;
11856 * The size of the doorbell BAR in KBytes reserved for L2 including
11857 * any area that is shared between L2 and RoCE. The L2 driver
11858 * should only map the L2 portion of the doorbell BAR. Any rounding
11859 * of the BAR size to the native CPU page size should be performed
11860 * by the driver. If the value is zero, no special partitioning
11861 * of the doorbell BAR between L2 and RoCE is required.
11863 uint16_t l2_doorbell_bar_size_kb;
11866 * For backward compatibility this field must be set to 1.
11867 * Older drivers might look for this field to be 1 before
11868 * processing the message.
11872 * This GRC address location is used by the Host driver interfaces to poll
11873 * the adapter ready state to re-initiate the registration process again
11874 * after receiving the RESET Notify event.
11876 uint32_t reset_addr_poll;
11878 * This field specifies legacy L2 doorbell size in KBytes. Drivers should use
11879 * this value to find out the doorbell page offset from the BAR.
11881 uint16_t legacy_l2_db_size_kb;
11882 uint16_t svif_info;
11884 * This field specifies the source virtual interface of the function being
11885 * queried. Drivers can use this to program svif field in the L2 context
11888 #define HWRM_FUNC_QCFG_OUTPUT_SVIF_INFO_SVIF_MASK UINT32_C(0x7fff)
11889 #define HWRM_FUNC_QCFG_OUTPUT_SVIF_INFO_SVIF_SFT 0
11890 /* This field specifies whether svif is valid or not */
11891 #define HWRM_FUNC_QCFG_OUTPUT_SVIF_INFO_SVIF_VALID UINT32_C(0x8000)
11894 * When this bit is '1', it indicates that a MPC channel with
11895 * destination set to the TX crypto engine block is enabled.
11897 #define HWRM_FUNC_QCFG_OUTPUT_MPC_CHNLS_TCE_ENABLED \
11900 * When this bit is '1', it indicates that a MPC channel with
11901 * destination set to the RX crypto engine block is enabled.
11903 #define HWRM_FUNC_QCFG_OUTPUT_MPC_CHNLS_RCE_ENABLED \
11906 * When this bit is '1', it indicates that a MPC channel with
11907 * destination set to the TX configurable flow processing block is
11910 #define HWRM_FUNC_QCFG_OUTPUT_MPC_CHNLS_TE_CFA_ENABLED \
11913 * When this bit is '1', it indicates that a MPC channel with
11914 * destination set to the RX configurable flow processing block is
11917 #define HWRM_FUNC_QCFG_OUTPUT_MPC_CHNLS_RE_CFA_ENABLED \
11920 * When this bit is '1', it indicates that a MPC channel with
11921 * destination set to the primate processor block is enabled.
11923 #define HWRM_FUNC_QCFG_OUTPUT_MPC_CHNLS_PRIMATE_ENABLED \
11925 uint8_t unused_2[6];
11927 * This field is used in Output records to indicate that the output
11928 * is completely written to RAM. This field should be read as '1'
11929 * to indicate that the output has been completely written.
11930 * When writing a command completion or response to an internal processor,
11931 * the order of writes has to be such that this field is written last.
11941 /* hwrm_func_cfg_input (size:768b/96B) */
11942 struct hwrm_func_cfg_input {
11943 /* The HWRM command request type. */
11946 * The completion ring to send the completion event on. This should
11947 * be the NQ ID returned from the `nq_alloc` HWRM command.
11949 uint16_t cmpl_ring;
11951 * The sequence ID is used by the driver for tracking multiple
11952 * commands. This ID is treated as opaque data by the firmware and
11953 * the value is returned in the `hwrm_resp_hdr` upon completion.
11957 * The target ID of the command:
11958 * * 0x0-0xFFF8 - The function ID
11959 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
11960 * * 0xFFFD - Reserved for user-space HWRM interface
11963 uint16_t target_id;
11965 * A physical address pointer pointing to a host buffer that the
11966 * command's response data will be written. This can be either a host
11967 * physical address (HPA) or a guest physical address (GPA) and must
11968 * point to a physically contiguous block of memory.
11970 uint64_t resp_addr;
11972 * Function ID of the function that is being
11974 * If set to 0xFF... (All Fs), then the configuration is
11975 * for the requesting function.
11979 * This field specifies how many NQs will be reserved for the PF.
11980 * Remaining NQs that belong to the PF become available for VFs.
11981 * Once a PF has created VFs, it cannot change how many NQs are
11982 * reserved for itself (since the NQs must be contiguous in HW).
11987 * When this bit is '1', the function is disabled with
11988 * source MAC address check.
11989 * This is an anti-spoofing check. If this flag is set,
11990 * then the function shall be configured to disallow
11991 * transmission of frames with the source MAC address that
11992 * is configured for this function.
11994 #define HWRM_FUNC_CFG_INPUT_FLAGS_SRC_MAC_ADDR_CHECK_DISABLE \
11997 * When this bit is '1', the function is enabled with
11998 * source MAC address check.
11999 * This is an anti-spoofing check. If this flag is set,
12000 * then the function shall be configured to allow
12001 * transmission of frames with the source MAC address that
12002 * is configured for this function.
12004 #define HWRM_FUNC_CFG_INPUT_FLAGS_SRC_MAC_ADDR_CHECK_ENABLE \
12007 #define HWRM_FUNC_CFG_INPUT_FLAGS_RSVD_MASK \
12009 #define HWRM_FUNC_CFG_INPUT_FLAGS_RSVD_SFT 2
12011 * Standard TX Ring mode is used for the allocation of TX ring
12012 * and underlying scheduling resources that allow bandwidth
12013 * reservation and limit settings on the queried function.
12014 * If set to 1, then standard TX ring mode is requested to be
12015 * enabled on the function being configured.
12017 #define HWRM_FUNC_CFG_INPUT_FLAGS_STD_TX_RING_MODE_ENABLE \
12020 * Standard TX Ring mode is used for the allocation of TX ring
12021 * and underlying scheduling resources that allow bandwidth
12022 * reservation and limit settings on the queried function.
12023 * If set to 1, then the standard TX ring mode is requested to
12024 * be disabled on the function being configured. In this extended
12025 * TX ring resource mode, the minimum and maximum bandwidth settings
12026 * are not supported to allow the allocation of TX rings to
12027 * span multiple scheduler nodes.
12029 #define HWRM_FUNC_CFG_INPUT_FLAGS_STD_TX_RING_MODE_DISABLE \
12032 * If this bit is set, virtual mac address configured
12033 * in this command will be persistent over warm boot.
12035 #define HWRM_FUNC_CFG_INPUT_FLAGS_VIRT_MAC_PERSIST \
12038 * This bit only applies to the VF. If this bit is set, the statistic
12039 * context counters will not be cleared when the statistic context is freed
12040 * or a function reset is called on VF. This bit will be cleared when the PF
12041 * is unloaded or a function reset is called on the PF.
12043 #define HWRM_FUNC_CFG_INPUT_FLAGS_NO_AUTOCLEAR_STATISTIC \
12046 * This bit requests that the firmware test to see if all the assets
12047 * requested in this command (i.e. number of TX rings) are available.
12048 * The firmware will return an error if the requested assets are
12049 * not available. The firwmare will NOT reserve the assets if they
12052 #define HWRM_FUNC_CFG_INPUT_FLAGS_TX_ASSETS_TEST \
12055 * This bit requests that the firmware test to see if all the assets
12056 * requested in this command (i.e. number of RX rings) are available.
12057 * The firmware will return an error if the requested assets are
12058 * not available. The firwmare will NOT reserve the assets if they
12061 #define HWRM_FUNC_CFG_INPUT_FLAGS_RX_ASSETS_TEST \
12064 * This bit requests that the firmware test to see if all the assets
12065 * requested in this command (i.e. number of CMPL rings) are available.
12066 * The firmware will return an error if the requested assets are
12067 * not available. The firwmare will NOT reserve the assets if they
12070 #define HWRM_FUNC_CFG_INPUT_FLAGS_CMPL_ASSETS_TEST \
12073 * This bit requests that the firmware test to see if all the assets
12074 * requested in this command (i.e. number of RSS ctx) are available.
12075 * The firmware will return an error if the requested assets are
12076 * not available. The firwmare will NOT reserve the assets if they
12079 #define HWRM_FUNC_CFG_INPUT_FLAGS_RSSCOS_CTX_ASSETS_TEST \
12082 * This bit requests that the firmware test to see if all the assets
12083 * requested in this command (i.e. number of ring groups) are available.
12084 * The firmware will return an error if the requested assets are
12085 * not available. The firwmare will NOT reserve the assets if they
12088 #define HWRM_FUNC_CFG_INPUT_FLAGS_RING_GRP_ASSETS_TEST \
12091 * This bit requests that the firmware test to see if all the assets
12092 * requested in this command (i.e. number of stat ctx) are available.
12093 * The firmware will return an error if the requested assets are
12094 * not available. The firwmare will NOT reserve the assets if they
12097 #define HWRM_FUNC_CFG_INPUT_FLAGS_STAT_CTX_ASSETS_TEST \
12100 * This bit requests that the firmware test to see if all the assets
12101 * requested in this command (i.e. number of VNICs) are available.
12102 * The firmware will return an error if the requested assets are
12103 * not available. The firwmare will NOT reserve the assets if they
12106 #define HWRM_FUNC_CFG_INPUT_FLAGS_VNIC_ASSETS_TEST \
12109 * This bit requests that the firmware test to see if all the assets
12110 * requested in this command (i.e. number of L2 ctx) are available.
12111 * The firmware will return an error if the requested assets are
12112 * not available. The firwmare will NOT reserve the assets if they
12115 #define HWRM_FUNC_CFG_INPUT_FLAGS_L2_CTX_ASSETS_TEST \
12118 * This configuration change can be initiated by a PF driver. This
12119 * configuration request shall be targeted to a VF. From local host
12120 * resident HWRM clients, only the parent PF driver shall be allowed
12121 * to initiate this change on one of its children VFs. If this bit is
12122 * set to 1, then the VF that is being configured is requested to be
12125 #define HWRM_FUNC_CFG_INPUT_FLAGS_TRUSTED_VF_ENABLE \
12128 * When this bit it set, even if PF reserved pool size is zero,
12129 * FW will allow driver to create TX rings in ring alloc,
12130 * by reserving TX ring, S3 node dynamically.
12132 #define HWRM_FUNC_CFG_INPUT_FLAGS_DYNAMIC_TX_RING_ALLOC \
12135 * This bit requests that the firmware test to see if all the assets
12136 * requested in this command (i.e. number of NQ rings) are available.
12137 * The firmware will return an error if the requested assets are
12138 * not available. The firwmare will NOT reserve the assets if they
12141 #define HWRM_FUNC_CFG_INPUT_FLAGS_NQ_ASSETS_TEST \
12144 * This configuration change can be initiated by a PF driver. This
12145 * configuration request shall be targeted to a VF. From local host
12146 * resident HWRM clients, only the parent PF driver shall be allowed
12147 * to initiate this change on one of its children VFs. If this bit is
12148 * set to 1, then the VF that is being configured is requested to be
12151 #define HWRM_FUNC_CFG_INPUT_FLAGS_TRUSTED_VF_DISABLE \
12152 UINT32_C(0x1000000)
12154 * This bit is used by preboot drivers on a PF that require access
12155 * to the legacy L2 ring model and legacy 32b doorbells. This
12156 * feature is not allowed on VFs and is only relevant for devices
12157 * that require a context backing store.
12159 #define HWRM_FUNC_CFG_INPUT_FLAGS_PREBOOT_LEGACY_L2_RINGS \
12160 UINT32_C(0x2000000)
12162 * If this bit is set to 0, then the interface does not support hot
12163 * reset capability which it advertised with the hot_reset_support
12164 * flag in HWRM_FUNC_DRV_RGTR. If any of the function has set this
12165 * flag to 0, adapter cannot do the hot reset. In this state, if the
12166 * firmware receives a hot reset request, firmware must fail the
12167 * request. If this bit is set to 1, then interface is renabling the
12168 * hot reset capability.
12170 #define HWRM_FUNC_CFG_INPUT_FLAGS_HOT_RESET_IF_EN_DIS \
12171 UINT32_C(0x4000000)
12173 * If this bit is set to 1, the PF driver is requesting FW
12174 * to enable PPP TX PUSH feature on all the TX rings specified in
12175 * the num_tx_rings field. By default, the PPP TX push feature is
12176 * disabled for all the TX rings of the function. This flag is
12177 * ignored if num_tx_rings field is not specified or the function
12178 * doesn't support PPP tx push feature.
12180 #define HWRM_FUNC_CFG_INPUT_FLAGS_PPP_PUSH_MODE_ENABLE \
12181 UINT32_C(0x8000000)
12183 * If this bit is set to 1, the PF driver is requesting FW
12184 * to disable PPP TX PUSH feature on all the TX rings specified in
12185 * the num_tx_rings field. This flag is ignored if num_tx_rings
12186 * field is not specified or the function doesn't support PPP tx
12189 #define HWRM_FUNC_CFG_INPUT_FLAGS_PPP_PUSH_MODE_DISABLE \
12190 UINT32_C(0x10000000)
12192 * If this bit is set to 1, the driver is requesting FW to enable
12193 * the BD_METADATA feature for this function. The FW returns error
12194 * on this request if the TX_METADATA is enabled for this function.
12196 #define HWRM_FUNC_CFG_INPUT_FLAGS_BD_METADATA_ENABLE \
12197 UINT32_C(0x20000000)
12199 * If this bit is set to 1, the driver is requesting FW to disable
12200 * the BD_METADATA feature for this function. The FW returns error
12201 * on this request if the TX_METADATA is enabled for this function.
12203 #define HWRM_FUNC_CFG_INPUT_FLAGS_BD_METADATA_DISABLE \
12204 UINT32_C(0x40000000)
12207 * This bit must be '1' for the mtu field to be
12210 #define HWRM_FUNC_CFG_INPUT_ENABLES_MTU \
12213 * This bit must be '1' for the mru field to be
12216 #define HWRM_FUNC_CFG_INPUT_ENABLES_MRU \
12219 * This bit must be '1' for the num_rsscos_ctxs field to be
12222 #define HWRM_FUNC_CFG_INPUT_ENABLES_NUM_RSSCOS_CTXS \
12225 * This bit must be '1' for the num_cmpl_rings field to be
12228 #define HWRM_FUNC_CFG_INPUT_ENABLES_NUM_CMPL_RINGS \
12231 * This bit must be '1' for the num_tx_rings field to be
12234 #define HWRM_FUNC_CFG_INPUT_ENABLES_NUM_TX_RINGS \
12237 * This bit must be '1' for the num_rx_rings field to be
12240 #define HWRM_FUNC_CFG_INPUT_ENABLES_NUM_RX_RINGS \
12243 * This bit must be '1' for the num_l2_ctxs field to be
12246 #define HWRM_FUNC_CFG_INPUT_ENABLES_NUM_L2_CTXS \
12249 * This bit must be '1' for the num_vnics field to be
12252 #define HWRM_FUNC_CFG_INPUT_ENABLES_NUM_VNICS \
12255 * This bit must be '1' for the num_stat_ctxs field to be
12258 #define HWRM_FUNC_CFG_INPUT_ENABLES_NUM_STAT_CTXS \
12261 * This bit must be '1' for the dflt_mac_addr field to be
12264 #define HWRM_FUNC_CFG_INPUT_ENABLES_DFLT_MAC_ADDR \
12267 * This bit must be '1' for the dflt_vlan field to be
12270 #define HWRM_FUNC_CFG_INPUT_ENABLES_DFLT_VLAN \
12273 * This bit must be '1' for the dflt_ip_addr field to be
12276 #define HWRM_FUNC_CFG_INPUT_ENABLES_DFLT_IP_ADDR \
12279 * This bit must be '1' for the min_bw field to be
12282 #define HWRM_FUNC_CFG_INPUT_ENABLES_MIN_BW \
12285 * This bit must be '1' for the max_bw field to be
12288 #define HWRM_FUNC_CFG_INPUT_ENABLES_MAX_BW \
12291 * This bit must be '1' for the async_event_cr field to be
12294 #define HWRM_FUNC_CFG_INPUT_ENABLES_ASYNC_EVENT_CR \
12297 * This bit must be '1' for the vlan_antispoof_mode field to be
12300 #define HWRM_FUNC_CFG_INPUT_ENABLES_VLAN_ANTISPOOF_MODE \
12303 * This bit must be '1' for the allowed_vlan_pris field to be
12306 #define HWRM_FUNC_CFG_INPUT_ENABLES_ALLOWED_VLAN_PRIS \
12309 * This bit must be '1' for the evb_mode field to be
12312 #define HWRM_FUNC_CFG_INPUT_ENABLES_EVB_MODE \
12315 * This bit must be '1' for the num_mcast_filters field to be
12318 #define HWRM_FUNC_CFG_INPUT_ENABLES_NUM_MCAST_FILTERS \
12321 * This bit must be '1' for the num_hw_ring_grps field to be
12324 #define HWRM_FUNC_CFG_INPUT_ENABLES_NUM_HW_RING_GRPS \
12327 * This bit must be '1' for the cache_linesize field to be
12330 #define HWRM_FUNC_CFG_INPUT_ENABLES_CACHE_LINESIZE \
12333 * This bit must be '1' for the num_msix field to be
12336 #define HWRM_FUNC_CFG_INPUT_ENABLES_NUM_MSIX \
12339 * This bit must be '1' for the link admin state field to be
12342 #define HWRM_FUNC_CFG_INPUT_ENABLES_ADMIN_LINK_STATE \
12345 * This bit must be '1' for the hot_reset_if_en_dis field to be
12348 #define HWRM_FUNC_CFG_INPUT_ENABLES_HOT_RESET_IF_SUPPORT \
12351 * This bit must be '1' for the schq_id field to be
12354 #define HWRM_FUNC_CFG_INPUT_ENABLES_SCHQ_ID \
12355 UINT32_C(0x1000000)
12357 * This bit must be '1' for the mpc_chnls field to be
12360 #define HWRM_FUNC_CFG_INPUT_ENABLES_MPC_CHNLS \
12361 UINT32_C(0x2000000)
12363 * The maximum transmission unit of the function.
12364 * The HWRM should make sure that the mtu of
12365 * the function does not exceed the mtu of the physical
12366 * port that this function is associated with.
12368 * In addition to configuring mtu per function, it is
12369 * possible to configure mtu per transmit ring.
12370 * By default, the mtu of each transmit ring associated
12371 * with a function is equal to the mtu of the function.
12372 * The HWRM should make sure that the mtu of each transmit
12373 * ring that is assigned to a function has a valid mtu.
12377 * The maximum receive unit of the function.
12378 * The HWRM should make sure that the mru of
12379 * the function does not exceed the mru of the physical
12380 * port that this function is associated with.
12382 * In addition to configuring mru per function, it is
12383 * possible to configure mru per vnic.
12384 * By default, the mru of each vnic associated
12385 * with a function is equal to the mru of the function.
12386 * The HWRM should make sure that the mru of each vnic
12387 * that is assigned to a function has a valid mru.
12391 * The number of RSS/COS contexts requested for the
12394 uint16_t num_rsscos_ctxs;
12396 * The number of completion rings requested for the
12397 * function. This does not include the rings allocated
12398 * to any children functions if any.
12400 uint16_t num_cmpl_rings;
12402 * The number of transmit rings requested for the function.
12403 * This does not include the rings allocated to any
12404 * children functions if any.
12406 uint16_t num_tx_rings;
12408 * The number of receive rings requested for the function.
12409 * This does not include the rings allocated
12410 * to any children functions if any.
12412 uint16_t num_rx_rings;
12413 /* The requested number of L2 contexts for the function. */
12414 uint16_t num_l2_ctxs;
12415 /* The requested number of vnics for the function. */
12416 uint16_t num_vnics;
12417 /* The requested number of statistic contexts for the function. */
12418 uint16_t num_stat_ctxs;
12420 * The number of HW ring groups that should
12421 * be reserved for this function.
12423 uint16_t num_hw_ring_grps;
12424 /* The default MAC address for the function being configured. */
12425 uint8_t dflt_mac_addr[6];
12427 * The default VLAN for the function being configured.
12428 * This field's format is same as 802.1Q Tag's
12429 * Tag Control Information (TCI) format that includes both
12430 * Priority Code Point (PCP) and VLAN Identifier (VID).
12432 uint16_t dflt_vlan;
12434 * The default IP address for the function being configured.
12435 * This address is only used in enabling source property check.
12437 uint32_t dflt_ip_addr[4];
12439 * Minimum BW allocated for this function.
12440 * The HWRM will translate this value into byte counter and
12441 * time interval used for the scheduler inside the device.
12444 /* The bandwidth value. */
12445 #define HWRM_FUNC_CFG_INPUT_MIN_BW_BW_VALUE_MASK \
12446 UINT32_C(0xfffffff)
12447 #define HWRM_FUNC_CFG_INPUT_MIN_BW_BW_VALUE_SFT 0
12448 /* The granularity of the value (bits or bytes). */
12449 #define HWRM_FUNC_CFG_INPUT_MIN_BW_SCALE \
12450 UINT32_C(0x10000000)
12451 /* Value is in bits. */
12452 #define HWRM_FUNC_CFG_INPUT_MIN_BW_SCALE_BITS \
12453 (UINT32_C(0x0) << 28)
12454 /* Value is in bytes. */
12455 #define HWRM_FUNC_CFG_INPUT_MIN_BW_SCALE_BYTES \
12456 (UINT32_C(0x1) << 28)
12457 #define HWRM_FUNC_CFG_INPUT_MIN_BW_SCALE_LAST \
12458 HWRM_FUNC_CFG_INPUT_MIN_BW_SCALE_BYTES
12459 /* bw_value_unit is 3 b */
12460 #define HWRM_FUNC_CFG_INPUT_MIN_BW_BW_VALUE_UNIT_MASK \
12461 UINT32_C(0xe0000000)
12462 #define HWRM_FUNC_CFG_INPUT_MIN_BW_BW_VALUE_UNIT_SFT 29
12463 /* Value is in Mb or MB (base 10). */
12464 #define HWRM_FUNC_CFG_INPUT_MIN_BW_BW_VALUE_UNIT_MEGA \
12465 (UINT32_C(0x0) << 29)
12466 /* Value is in Kb or KB (base 10). */
12467 #define HWRM_FUNC_CFG_INPUT_MIN_BW_BW_VALUE_UNIT_KILO \
12468 (UINT32_C(0x2) << 29)
12469 /* Value is in bits or bytes. */
12470 #define HWRM_FUNC_CFG_INPUT_MIN_BW_BW_VALUE_UNIT_BASE \
12471 (UINT32_C(0x4) << 29)
12472 /* Value is in Gb or GB (base 10). */
12473 #define HWRM_FUNC_CFG_INPUT_MIN_BW_BW_VALUE_UNIT_GIGA \
12474 (UINT32_C(0x6) << 29)
12475 /* Value is in 1/100th of a percentage of total bandwidth. */
12476 #define HWRM_FUNC_CFG_INPUT_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 \
12477 (UINT32_C(0x1) << 29)
12479 #define HWRM_FUNC_CFG_INPUT_MIN_BW_BW_VALUE_UNIT_INVALID \
12480 (UINT32_C(0x7) << 29)
12481 #define HWRM_FUNC_CFG_INPUT_MIN_BW_BW_VALUE_UNIT_LAST \
12482 HWRM_FUNC_CFG_INPUT_MIN_BW_BW_VALUE_UNIT_INVALID
12484 * Maximum BW allocated for this function.
12485 * The HWRM will translate this value into byte counter and
12486 * time interval used for the scheduler inside the device.
12489 /* The bandwidth value. */
12490 #define HWRM_FUNC_CFG_INPUT_MAX_BW_BW_VALUE_MASK \
12491 UINT32_C(0xfffffff)
12492 #define HWRM_FUNC_CFG_INPUT_MAX_BW_BW_VALUE_SFT 0
12493 /* The granularity of the value (bits or bytes). */
12494 #define HWRM_FUNC_CFG_INPUT_MAX_BW_SCALE \
12495 UINT32_C(0x10000000)
12496 /* Value is in bits. */
12497 #define HWRM_FUNC_CFG_INPUT_MAX_BW_SCALE_BITS \
12498 (UINT32_C(0x0) << 28)
12499 /* Value is in bytes. */
12500 #define HWRM_FUNC_CFG_INPUT_MAX_BW_SCALE_BYTES \
12501 (UINT32_C(0x1) << 28)
12502 #define HWRM_FUNC_CFG_INPUT_MAX_BW_SCALE_LAST \
12503 HWRM_FUNC_CFG_INPUT_MAX_BW_SCALE_BYTES
12504 /* bw_value_unit is 3 b */
12505 #define HWRM_FUNC_CFG_INPUT_MAX_BW_BW_VALUE_UNIT_MASK \
12506 UINT32_C(0xe0000000)
12507 #define HWRM_FUNC_CFG_INPUT_MAX_BW_BW_VALUE_UNIT_SFT 29
12508 /* Value is in Mb or MB (base 10). */
12509 #define HWRM_FUNC_CFG_INPUT_MAX_BW_BW_VALUE_UNIT_MEGA \
12510 (UINT32_C(0x0) << 29)
12511 /* Value is in Kb or KB (base 10). */
12512 #define HWRM_FUNC_CFG_INPUT_MAX_BW_BW_VALUE_UNIT_KILO \
12513 (UINT32_C(0x2) << 29)
12514 /* Value is in bits or bytes. */
12515 #define HWRM_FUNC_CFG_INPUT_MAX_BW_BW_VALUE_UNIT_BASE \
12516 (UINT32_C(0x4) << 29)
12517 /* Value is in Gb or GB (base 10). */
12518 #define HWRM_FUNC_CFG_INPUT_MAX_BW_BW_VALUE_UNIT_GIGA \
12519 (UINT32_C(0x6) << 29)
12520 /* Value is in 1/100th of a percentage of total bandwidth. */
12521 #define HWRM_FUNC_CFG_INPUT_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 \
12522 (UINT32_C(0x1) << 29)
12524 #define HWRM_FUNC_CFG_INPUT_MAX_BW_BW_VALUE_UNIT_INVALID \
12525 (UINT32_C(0x7) << 29)
12526 #define HWRM_FUNC_CFG_INPUT_MAX_BW_BW_VALUE_UNIT_LAST \
12527 HWRM_FUNC_CFG_INPUT_MAX_BW_BW_VALUE_UNIT_INVALID
12529 * ID of the target completion ring for receiving asynchronous
12530 * event completions. If this field is not valid, then the
12531 * HWRM shall use the default completion ring of the function
12532 * that is being configured as the target completion ring for
12533 * providing any asynchronous event completions for that
12535 * If this field is valid, then the HWRM shall use the
12536 * completion ring identified by this ID as the target
12537 * completion ring for providing any asynchronous event
12538 * completions for the function that is being configured.
12540 uint16_t async_event_cr;
12541 /* VLAN Anti-spoofing mode. */
12542 uint8_t vlan_antispoof_mode;
12543 /* No VLAN anti-spoofing checks are enabled */
12544 #define HWRM_FUNC_CFG_INPUT_VLAN_ANTISPOOF_MODE_NOCHECK \
12546 /* Validate VLAN against the configured VLAN(s) */
12547 #define HWRM_FUNC_CFG_INPUT_VLAN_ANTISPOOF_MODE_VALIDATE_VLAN \
12549 /* Insert VLAN if it does not exist, otherwise discard */
12550 #define HWRM_FUNC_CFG_INPUT_VLAN_ANTISPOOF_MODE_INSERT_IF_VLANDNE \
12552 /* Insert VLAN if it does not exist, override VLAN if it exists */
12553 #define HWRM_FUNC_CFG_INPUT_VLAN_ANTISPOOF_MODE_INSERT_OR_OVERRIDE_VLAN \
12555 #define HWRM_FUNC_CFG_INPUT_VLAN_ANTISPOOF_MODE_LAST \
12556 HWRM_FUNC_CFG_INPUT_VLAN_ANTISPOOF_MODE_INSERT_OR_OVERRIDE_VLAN
12558 * This bit field defines VLAN PRIs that are allowed on
12560 * If nth bit is set, then VLAN PRI n is allowed on this
12563 uint8_t allowed_vlan_pris;
12565 * The evb_mode is configured on a per port basis. The default evb_mode
12566 * is configured based on the NVM EVB mode setting upon firmware
12567 * initialization. The HWRM allows a PF driver to change EVB mode for a
12568 * port used by the PF only when one of the following conditions is
12570 * 1. The current operating mode is single function mode.
12571 * (ie. one PF per port)
12572 * 2. For SmartNIC, any one of the PAXC PFs is permitted to change the
12573 * EVB mode of the port used by the PAXC PF. None of the X86 PFs
12574 * should have privileges.
12575 * The HWRM doesn't permit any PFs to change the underlying EVB mode
12576 * when running as MHB or NPAR mode in performance NIC configuration.
12577 * The HWRM doesn't permit a VF driver to change the EVB mode.
12578 * Once the HWRM determines a function doesn't meet the conditions
12579 * to configure the EVB mode, it sets the evb_mode_cfg_not_supported
12580 * flag in HWRM_FUNC_QCAPS command response for the function.
12581 * The HWRM takes into account the switching of EVB mode from one to
12582 * another and reconfigure hardware resources as reqiured. The
12583 * switching from VEB to VEPA mode requires the disabling of the
12584 * loopback traffic. Additionally, source knockouts are handled
12585 * differently in VEB and VEPA modes.
12588 /* No Edge Virtual Bridging (EVB) */
12589 #define HWRM_FUNC_CFG_INPUT_EVB_MODE_NO_EVB UINT32_C(0x0)
12590 /* Virtual Ethernet Bridge (VEB) */
12591 #define HWRM_FUNC_CFG_INPUT_EVB_MODE_VEB UINT32_C(0x1)
12592 /* Virtual Ethernet Port Aggregator (VEPA) */
12593 #define HWRM_FUNC_CFG_INPUT_EVB_MODE_VEPA UINT32_C(0x2)
12594 #define HWRM_FUNC_CFG_INPUT_EVB_MODE_LAST \
12595 HWRM_FUNC_CFG_INPUT_EVB_MODE_VEPA
12598 * This value indicates the PCIE device cache line size.
12599 * The cache line size allows the DMA writes to terminate and
12600 * start at the cache boundary.
12602 #define HWRM_FUNC_CFG_INPUT_OPTIONS_CACHE_LINESIZE_MASK \
12604 #define HWRM_FUNC_CFG_INPUT_OPTIONS_CACHE_LINESIZE_SFT 0
12605 /* Cache Line Size 64 bytes */
12606 #define HWRM_FUNC_CFG_INPUT_OPTIONS_CACHE_LINESIZE_SIZE_64 \
12608 /* Cache Line Size 128 bytes */
12609 #define HWRM_FUNC_CFG_INPUT_OPTIONS_CACHE_LINESIZE_SIZE_128 \
12611 #define HWRM_FUNC_CFG_INPUT_OPTIONS_CACHE_LINESIZE_LAST \
12612 HWRM_FUNC_CFG_INPUT_OPTIONS_CACHE_LINESIZE_SIZE_128
12613 /* This value is the virtual link admin state setting. */
12614 #define HWRM_FUNC_CFG_INPUT_OPTIONS_LINK_ADMIN_STATE_MASK \
12616 #define HWRM_FUNC_CFG_INPUT_OPTIONS_LINK_ADMIN_STATE_SFT 2
12617 /* Admin state is forced down. */
12618 #define HWRM_FUNC_CFG_INPUT_OPTIONS_LINK_ADMIN_STATE_FORCED_DOWN \
12619 (UINT32_C(0x0) << 2)
12620 /* Admin state is forced up. */
12621 #define HWRM_FUNC_CFG_INPUT_OPTIONS_LINK_ADMIN_STATE_FORCED_UP \
12622 (UINT32_C(0x1) << 2)
12623 /* Admin state is in auto mode - is to follow the physical link state. */
12624 #define HWRM_FUNC_CFG_INPUT_OPTIONS_LINK_ADMIN_STATE_AUTO \
12625 (UINT32_C(0x2) << 2)
12626 #define HWRM_FUNC_CFG_INPUT_OPTIONS_LINK_ADMIN_STATE_LAST \
12627 HWRM_FUNC_CFG_INPUT_OPTIONS_LINK_ADMIN_STATE_AUTO
12628 /* Reserved for future. */
12629 #define HWRM_FUNC_CFG_INPUT_OPTIONS_RSVD_MASK \
12631 #define HWRM_FUNC_CFG_INPUT_OPTIONS_RSVD_SFT 4
12633 * The number of multicast filters that should
12634 * be reserved for this function on the RX side.
12636 uint16_t num_mcast_filters;
12637 /* Used by a PF driver to associate a SCHQ with a VF. */
12639 uint16_t mpc_chnls;
12641 * When this bit is '1', the caller requests to enable a MPC
12642 * channel with destination to the TX crypto engine block.
12643 * When this bit is ‘0’, this flag has no effect.
12645 #define HWRM_FUNC_CFG_INPUT_MPC_CHNLS_TCE_ENABLE UINT32_C(0x1)
12647 * When this bit is '1', the caller requests to disable a MPC
12648 * channel with destination to the TX crypto engine block.
12649 * When this bit is ‘0’, this flag has no effect.
12651 #define HWRM_FUNC_CFG_INPUT_MPC_CHNLS_TCE_DISABLE UINT32_C(0x2)
12653 * When this bit is '1', the caller requests to enable a MPC
12654 * channel with destination to the RX crypto engine block.
12655 * When this bit is ‘0’, this flag has no effect.
12657 #define HWRM_FUNC_CFG_INPUT_MPC_CHNLS_RCE_ENABLE UINT32_C(0x4)
12659 * When this bit is '1', the caller requests to disable a MPC
12660 * channel with destination to the RX crypto engine block.
12661 * When this bit is ‘0’, this flag has no effect.
12663 #define HWRM_FUNC_CFG_INPUT_MPC_CHNLS_RCE_DISABLE UINT32_C(0x8)
12665 * When this bit is '1', the caller requests to enable a MPC
12666 * channel with destination to the TX configurable flow processing
12667 * block. When this bit is ‘0’, this flag has no effect.
12669 #define HWRM_FUNC_CFG_INPUT_MPC_CHNLS_TE_CFA_ENABLE \
12672 * When this bit is '1', the caller requests to disable a MPC
12673 * channel with destination to the TX configurable flow processing
12674 * block. When this bit is ‘0’, this flag has no effect.
12676 #define HWRM_FUNC_CFG_INPUT_MPC_CHNLS_TE_CFA_DISABLE \
12679 * When this bit is '1', the caller requests to enable a MPC
12680 * channel with destination to the RX configurable flow processing
12681 * block. When this bit is ‘0’, this flag has no effect.
12683 #define HWRM_FUNC_CFG_INPUT_MPC_CHNLS_RE_CFA_ENABLE \
12686 * When this bit is '1', the caller requests to disable a MPC
12687 * channel with destination to the RX configurable flow processing
12688 * block. When this bit is ‘0’, this flag has no effect.
12690 #define HWRM_FUNC_CFG_INPUT_MPC_CHNLS_RE_CFA_DISABLE \
12693 * When this bit is '1', the caller requests to enable a MPC
12694 * channel with destination to the primate processor block.
12695 * When this bit is ‘0’, this flag has no effect.
12697 #define HWRM_FUNC_CFG_INPUT_MPC_CHNLS_PRIMATE_ENABLE \
12700 * When this bit is '1', the caller requests to disable a MPC
12701 * channel with destination to the primate processor block.
12702 * When this bit is ‘0’, this flag has no effect.
12704 #define HWRM_FUNC_CFG_INPUT_MPC_CHNLS_PRIMATE_DISABLE \
12706 uint8_t unused_0[4];
12709 /* hwrm_func_cfg_output (size:128b/16B) */
12710 struct hwrm_func_cfg_output {
12711 /* The specific error status for the command. */
12712 uint16_t error_code;
12713 /* The HWRM command request type. */
12715 /* The sequence ID from the original command. */
12717 /* The length of the response data in number of bytes. */
12719 uint8_t unused_0[7];
12721 * This field is used in Output records to indicate that the output
12722 * is completely written to RAM. This field should be read as '1'
12723 * to indicate that the output has been completely written.
12724 * When writing a command completion or response to an internal processor,
12725 * the order of writes has to be such that this field is written last.
12730 /********************
12731 * hwrm_func_qstats *
12732 ********************/
12735 /* hwrm_func_qstats_input (size:192b/24B) */
12736 struct hwrm_func_qstats_input {
12737 /* The HWRM command request type. */
12740 * The completion ring to send the completion event on. This should
12741 * be the NQ ID returned from the `nq_alloc` HWRM command.
12743 uint16_t cmpl_ring;
12745 * The sequence ID is used by the driver for tracking multiple
12746 * commands. This ID is treated as opaque data by the firmware and
12747 * the value is returned in the `hwrm_resp_hdr` upon completion.
12751 * The target ID of the command:
12752 * * 0x0-0xFFF8 - The function ID
12753 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
12754 * * 0xFFFD - Reserved for user-space HWRM interface
12757 uint16_t target_id;
12759 * A physical address pointer pointing to a host buffer that the
12760 * command's response data will be written. This can be either a host
12761 * physical address (HPA) or a guest physical address (GPA) and must
12762 * point to a physically contiguous block of memory.
12764 uint64_t resp_addr;
12766 * Function ID of the function that is being queried.
12767 * 0xFF... (All Fs) if the query is for the requesting
12769 * A privileged PF can query for other function's statistics.
12772 /* This flags indicates the type of statistics request. */
12774 /* This value is not used to avoid backward compatibility issues. */
12775 #define HWRM_FUNC_QSTATS_INPUT_FLAGS_UNUSED UINT32_C(0x0)
12777 * flags should be set to 1 when request is for only RoCE statistics.
12778 * This will be honored only if the caller_fid is a privileged PF.
12779 * In all other cases FID and caller_fid should be the same.
12781 #define HWRM_FUNC_QSTATS_INPUT_FLAGS_ROCE_ONLY UINT32_C(0x1)
12783 * flags should be set to 2 when request is for the counter mask,
12784 * representing the width of each of the stats counters, rather
12785 * than counters themselves.
12787 #define HWRM_FUNC_QSTATS_INPUT_FLAGS_COUNTER_MASK UINT32_C(0x2)
12788 #define HWRM_FUNC_QSTATS_INPUT_FLAGS_LAST \
12789 HWRM_FUNC_QSTATS_INPUT_FLAGS_COUNTER_MASK
12790 uint8_t unused_0[5];
12793 /* hwrm_func_qstats_output (size:1408b/176B) */
12794 struct hwrm_func_qstats_output {
12795 /* The specific error status for the command. */
12796 uint16_t error_code;
12797 /* The HWRM command request type. */
12799 /* The sequence ID from the original command. */
12801 /* The length of the response data in number of bytes. */
12803 /* Number of transmitted unicast packets on the function. */
12804 uint64_t tx_ucast_pkts;
12805 /* Number of transmitted multicast packets on the function. */
12806 uint64_t tx_mcast_pkts;
12807 /* Number of transmitted broadcast packets on the function. */
12808 uint64_t tx_bcast_pkts;
12810 * Number of transmitted packets that were discarded due to
12811 * internal NIC resource problems. For transmit, this
12812 * can only happen if TMP is configured to allow dropping
12813 * in HOL blocking conditions, which is not a normal
12816 uint64_t tx_discard_pkts;
12818 * Number of dropped packets on transmit path on the function.
12819 * These are packets that have been marked for drop by
12820 * the TE CFA block or are packets that exceeded the
12821 * transmit MTU limit for the function.
12823 uint64_t tx_drop_pkts;
12824 /* Number of transmitted bytes for unicast traffic on the function. */
12825 uint64_t tx_ucast_bytes;
12826 /* Number of transmitted bytes for multicast traffic on the function. */
12827 uint64_t tx_mcast_bytes;
12828 /* Number of transmitted bytes for broadcast traffic on the function. */
12829 uint64_t tx_bcast_bytes;
12830 /* Number of received unicast packets on the function. */
12831 uint64_t rx_ucast_pkts;
12832 /* Number of received multicast packets on the function. */
12833 uint64_t rx_mcast_pkts;
12834 /* Number of received broadcast packets on the function. */
12835 uint64_t rx_bcast_pkts;
12837 * Number of received packets that were discarded on the function
12838 * due to resource limitations. This can happen for 3 reasons.
12839 * # The BD used for the packet has a bad format.
12840 * # There were no BDs available in the ring for the packet.
12841 * # There were no BDs available on-chip for the packet.
12843 uint64_t rx_discard_pkts;
12845 * Number of dropped packets on received path on the function.
12846 * These are packets that have been marked for drop by the
12849 uint64_t rx_drop_pkts;
12850 /* Number of received bytes for unicast traffic on the function. */
12851 uint64_t rx_ucast_bytes;
12852 /* Number of received bytes for multicast traffic on the function. */
12853 uint64_t rx_mcast_bytes;
12854 /* Number of received bytes for broadcast traffic on the function. */
12855 uint64_t rx_bcast_bytes;
12856 /* Number of aggregated unicast packets on the function. */
12857 uint64_t rx_agg_pkts;
12858 /* Number of aggregated unicast bytes on the function. */
12859 uint64_t rx_agg_bytes;
12860 /* Number of aggregation events on the function. */
12861 uint64_t rx_agg_events;
12862 /* Number of aborted aggregations on the function. */
12863 uint64_t rx_agg_aborts;
12864 uint8_t unused_0[7];
12866 * This field is used in Output records to indicate that the output
12867 * is completely written to RAM. This field should be read as '1'
12868 * to indicate that the output has been completely written.
12869 * When writing a command completion or response to an internal processor,
12870 * the order of writes has to be such that this field is written last.
12875 /************************
12876 * hwrm_func_qstats_ext *
12877 ************************/
12880 /* hwrm_func_qstats_ext_input (size:256b/32B) */
12881 struct hwrm_func_qstats_ext_input {
12882 /* The HWRM command request type. */
12885 * The completion ring to send the completion event on. This should
12886 * be the NQ ID returned from the `nq_alloc` HWRM command.
12888 uint16_t cmpl_ring;
12890 * The sequence ID is used by the driver for tracking multiple
12891 * commands. This ID is treated as opaque data by the firmware and
12892 * the value is returned in the `hwrm_resp_hdr` upon completion.
12896 * The target ID of the command:
12897 * * 0x0-0xFFF8 - The function ID
12898 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
12899 * * 0xFFFD - Reserved for user-space HWRM interface
12902 uint16_t target_id;
12904 * A physical address pointer pointing to a host buffer that the
12905 * command's response data will be written. This can be either a host
12906 * physical address (HPA) or a guest physical address (GPA) and must
12907 * point to a physically contiguous block of memory.
12909 uint64_t resp_addr;
12911 * Function ID of the function that is being queried.
12912 * 0xFF... (All Fs) if the query is for the requesting
12914 * A privileged PF can query for other function's statistics.
12917 /* This flags indicates the type of statistics request. */
12919 /* This value is not used to avoid backward compatibility issues. */
12920 #define HWRM_FUNC_QSTATS_EXT_INPUT_FLAGS_UNUSED UINT32_C(0x0)
12922 * flags should be set to 1 when request is for only RoCE statistics.
12923 * This will be honored only if the caller_fid is a privileged PF.
12924 * In all other cases FID and caller_fid should be the same.
12926 #define HWRM_FUNC_QSTATS_EXT_INPUT_FLAGS_ROCE_ONLY UINT32_C(0x1)
12928 * flags should be set to 2 when request is for the counter mask
12929 * representing the width of each of the stats counters, rather
12930 * than counters themselves.
12932 #define HWRM_FUNC_QSTATS_EXT_INPUT_FLAGS_COUNTER_MASK UINT32_C(0x2)
12933 #define HWRM_FUNC_QSTATS_EXT_INPUT_FLAGS_LAST \
12934 HWRM_FUNC_QSTATS_EXT_INPUT_FLAGS_COUNTER_MASK
12935 uint8_t unused_0[1];
12938 * This bit must be '1' for the schq_id and traffic_class fields to
12941 #define HWRM_FUNC_QSTATS_EXT_INPUT_ENABLES_SCHQ_ID UINT32_C(0x1)
12942 /* Specifies the SCHQ for which to gather statistics */
12945 * Specifies the traffic class for which to gather statistics. Valid
12946 * values are 0 through (max_configurable_queues - 1), where
12947 * max_configurable_queues is in the response of HWRM_QUEUE_QPORTCFG
12949 uint16_t traffic_class;
12950 uint8_t unused_1[4];
12953 /* hwrm_func_qstats_ext_output (size:1536b/192B) */
12954 struct hwrm_func_qstats_ext_output {
12955 /* The specific error status for the command. */
12956 uint16_t error_code;
12957 /* The HWRM command request type. */
12959 /* The sequence ID from the original command. */
12961 /* The length of the response data in number of bytes. */
12963 /* Number of received unicast packets */
12964 uint64_t rx_ucast_pkts;
12965 /* Number of received multicast packets */
12966 uint64_t rx_mcast_pkts;
12967 /* Number of received broadcast packets */
12968 uint64_t rx_bcast_pkts;
12969 /* Number of discarded packets on received path */
12970 uint64_t rx_discard_pkts;
12971 /* Number of packets on receive path with error */
12972 uint64_t rx_error_pkts;
12973 /* Number of received bytes for unicast traffic */
12974 uint64_t rx_ucast_bytes;
12975 /* Number of received bytes for multicast traffic */
12976 uint64_t rx_mcast_bytes;
12977 /* Number of received bytes for broadcast traffic */
12978 uint64_t rx_bcast_bytes;
12979 /* Number of transmitted unicast packets */
12980 uint64_t tx_ucast_pkts;
12981 /* Number of transmitted multicast packets */
12982 uint64_t tx_mcast_pkts;
12983 /* Number of transmitted broadcast packets */
12984 uint64_t tx_bcast_pkts;
12985 /* Number of packets on transmit path with error */
12986 uint64_t tx_error_pkts;
12987 /* Number of discarded packets on transmit path */
12988 uint64_t tx_discard_pkts;
12989 /* Number of transmitted bytes for unicast traffic */
12990 uint64_t tx_ucast_bytes;
12991 /* Number of transmitted bytes for multicast traffic */
12992 uint64_t tx_mcast_bytes;
12993 /* Number of transmitted bytes for broadcast traffic */
12994 uint64_t tx_bcast_bytes;
12995 /* Number of TPA eligible packets */
12996 uint64_t rx_tpa_eligible_pkt;
12997 /* Number of TPA eligible bytes */
12998 uint64_t rx_tpa_eligible_bytes;
12999 /* Number of TPA packets */
13000 uint64_t rx_tpa_pkt;
13001 /* Number of TPA bytes */
13002 uint64_t rx_tpa_bytes;
13003 /* Number of TPA errors */
13004 uint64_t rx_tpa_errors;
13005 /* Number of TPA errors */
13006 uint64_t rx_tpa_events;
13007 uint8_t unused_0[7];
13009 * This field is used in Output records to indicate that the output
13010 * is completely written to RAM. This field should be read as '1'
13011 * to indicate that the output has been completely written.
13012 * When writing a command completion or response to an internal processor,
13013 * the order of writes has to be such that this field is written last.
13018 /***********************
13019 * hwrm_func_clr_stats *
13020 ***********************/
13023 /* hwrm_func_clr_stats_input (size:192b/24B) */
13024 struct hwrm_func_clr_stats_input {
13025 /* The HWRM command request type. */
13028 * The completion ring to send the completion event on. This should
13029 * be the NQ ID returned from the `nq_alloc` HWRM command.
13031 uint16_t cmpl_ring;
13033 * The sequence ID is used by the driver for tracking multiple
13034 * commands. This ID is treated as opaque data by the firmware and
13035 * the value is returned in the `hwrm_resp_hdr` upon completion.
13039 * The target ID of the command:
13040 * * 0x0-0xFFF8 - The function ID
13041 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
13042 * * 0xFFFD - Reserved for user-space HWRM interface
13045 uint16_t target_id;
13047 * A physical address pointer pointing to a host buffer that the
13048 * command's response data will be written. This can be either a host
13049 * physical address (HPA) or a guest physical address (GPA) and must
13050 * point to a physically contiguous block of memory.
13052 uint64_t resp_addr;
13054 * Function ID of the function.
13055 * 0xFF... (All Fs) if the query is for the requesting
13059 uint8_t unused_0[6];
13062 /* hwrm_func_clr_stats_output (size:128b/16B) */
13063 struct hwrm_func_clr_stats_output {
13064 /* The specific error status for the command. */
13065 uint16_t error_code;
13066 /* The HWRM command request type. */
13068 /* The sequence ID from the original command. */
13070 /* The length of the response data in number of bytes. */
13072 uint8_t unused_0[7];
13074 * This field is used in Output records to indicate that the output
13075 * is completely written to RAM. This field should be read as '1'
13076 * to indicate that the output has been completely written.
13077 * When writing a command completion or response to an internal processor,
13078 * the order of writes has to be such that this field is written last.
13083 /**************************
13084 * hwrm_func_vf_resc_free *
13085 **************************/
13088 /* hwrm_func_vf_resc_free_input (size:192b/24B) */
13089 struct hwrm_func_vf_resc_free_input {
13090 /* The HWRM command request type. */
13093 * The completion ring to send the completion event on. This should
13094 * be the NQ ID returned from the `nq_alloc` HWRM command.
13096 uint16_t cmpl_ring;
13098 * The sequence ID is used by the driver for tracking multiple
13099 * commands. This ID is treated as opaque data by the firmware and
13100 * the value is returned in the `hwrm_resp_hdr` upon completion.
13104 * The target ID of the command:
13105 * * 0x0-0xFFF8 - The function ID
13106 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
13107 * * 0xFFFD - Reserved for user-space HWRM interface
13110 uint16_t target_id;
13112 * A physical address pointer pointing to a host buffer that the
13113 * command's response data will be written. This can be either a host
13114 * physical address (HPA) or a guest physical address (GPA) and must
13115 * point to a physically contiguous block of memory.
13117 uint64_t resp_addr;
13119 * This value is used to identify a Virtual Function (VF).
13120 * The scope of VF ID is local within a PF.
13123 uint8_t unused_0[6];
13126 /* hwrm_func_vf_resc_free_output (size:128b/16B) */
13127 struct hwrm_func_vf_resc_free_output {
13128 /* The specific error status for the command. */
13129 uint16_t error_code;
13130 /* The HWRM command request type. */
13132 /* The sequence ID from the original command. */
13134 /* The length of the response data in number of bytes. */
13136 uint8_t unused_0[7];
13138 * This field is used in Output records to indicate that the output
13139 * is completely written to RAM. This field should be read as '1'
13140 * to indicate that the output has been completely written.
13141 * When writing a command completion or response to an internal processor,
13142 * the order of writes has to be such that this field is written last.
13147 /**********************
13148 * hwrm_func_drv_rgtr *
13149 **********************/
13152 /* hwrm_func_drv_rgtr_input (size:896b/112B) */
13153 struct hwrm_func_drv_rgtr_input {
13154 /* The HWRM command request type. */
13157 * The completion ring to send the completion event on. This should
13158 * be the NQ ID returned from the `nq_alloc` HWRM command.
13160 uint16_t cmpl_ring;
13162 * The sequence ID is used by the driver for tracking multiple
13163 * commands. This ID is treated as opaque data by the firmware and
13164 * the value is returned in the `hwrm_resp_hdr` upon completion.
13168 * The target ID of the command:
13169 * * 0x0-0xFFF8 - The function ID
13170 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
13171 * * 0xFFFD - Reserved for user-space HWRM interface
13174 uint16_t target_id;
13176 * A physical address pointer pointing to a host buffer that the
13177 * command's response data will be written. This can be either a host
13178 * physical address (HPA) or a guest physical address (GPA) and must
13179 * point to a physically contiguous block of memory.
13181 uint64_t resp_addr;
13184 * When this bit is '1', the function driver is requesting
13185 * all requests from its children VF drivers to be
13186 * forwarded to itself.
13187 * This flag can only be set by the PF driver.
13188 * If a VF driver sets this flag, it should be ignored
13191 #define HWRM_FUNC_DRV_RGTR_INPUT_FLAGS_FWD_ALL_MODE \
13194 * When this bit is '1', the function is requesting none of
13195 * the requests from its children VF drivers to be
13196 * forwarded to itself.
13197 * This flag can only be set by the PF driver.
13198 * If a VF driver sets this flag, it should be ignored
13201 #define HWRM_FUNC_DRV_RGTR_INPUT_FLAGS_FWD_NONE_MODE \
13204 * When this bit is '1', then ver_maj_8b, ver_min_8b, ver_upd_8b
13205 * fields shall be ignored and ver_maj, ver_min, ver_upd
13206 * and ver_patch shall be used for the driver version information.
13207 * When this bit is '0', then ver_maj_8b, ver_min_8b, ver_upd_8b
13208 * fields shall be used for the driver version information and
13209 * ver_maj, ver_min, ver_upd and ver_patch shall be ignored.
13211 #define HWRM_FUNC_DRV_RGTR_INPUT_FLAGS_16BIT_VER_MODE \
13214 * When this bit is '1', the function is indicating support of
13215 * 64bit flow handle. The firmware that only supports 64bit flow
13216 * handle should check this bit before allowing processing of
13217 * HWRM_CFA_FLOW_XXX commands from the requesting function as firmware
13218 * with 64bit flow handle support can only be compatible with drivers
13219 * that support 64bit flow handle. The legacy drivers that don't support
13220 * 64bit flow handle won't be able to use HWRM_CFA_FLOW_XXX commands when
13221 * running with new firmware that only supports 64bit flow handle. The new
13222 * firmware support 64bit flow handle returns HWRM_ERR_CODE_CMD_NOT_SUPPORTED
13223 * status to the legacy driver when encounters these commands.
13225 #define HWRM_FUNC_DRV_RGTR_INPUT_FLAGS_FLOW_HANDLE_64BIT_MODE \
13228 * When this bit is '1', the function is indicating support of
13229 * Hot Reset. The driver interface will destroy the resources,
13230 * unregister the function and register again up on receiving
13231 * the RESET_NOTIFY Async notification from the core firmware.
13232 * The core firmware will this use flag and trigger the Hot Reset
13233 * process only if all the registered driver instances are capable
13236 #define HWRM_FUNC_DRV_RGTR_INPUT_FLAGS_HOT_RESET_SUPPORT \
13239 * When this bit is 1, the function is indicating the support of the
13240 * error recovery capability. Error recovery support will be used by
13241 * firmware only if all the driver instances support error recovery
13242 * process. By setting this bit, driver is indicating support for
13243 * corresponding async event completion message. These will be
13244 * delivered to the driver even if they did not register for it.
13245 * If supported, after receiving reset notify async event with fatal
13246 * flag set in event data1, then all the drivers have to tear down
13247 * their resources without sending any HWRM commands to FW.
13249 #define HWRM_FUNC_DRV_RGTR_INPUT_FLAGS_ERROR_RECOVERY_SUPPORT \
13252 * When this bit is 1, the function is indicating the support of the
13253 * Master capability. The Firmware will use this capability to select the
13254 * Master function. The master function will be used to initiate
13255 * designated functionality like error recovery etc… If none of the
13256 * registered PF’s or trusted VF’s indicate this support, then
13257 * firmware will select the 1st registered PF as Master capable instance.
13259 #define HWRM_FUNC_DRV_RGTR_INPUT_FLAGS_MASTER_SUPPORT \
13262 * When this bit is 1, the function is indicating the support of the
13263 * fast reset capability. Fast reset support will be used by
13264 * firmware only if all the driver instances support fast reset
13265 * process. By setting this bit, driver is indicating support for
13266 * corresponding async event completion message. These will be
13267 * delivered to the driver even if they did not register for it.
13268 * If supported, after receiving reset notify async event with fast
13269 * reset flag set in event data1, then all the drivers have to tear
13270 * down their resources without sending any HWRM commands to FW.
13272 #define HWRM_FUNC_DRV_RGTR_INPUT_FLAGS_FAST_RESET_SUPPORT \
13276 * This bit must be '1' for the os_type field to be
13279 #define HWRM_FUNC_DRV_RGTR_INPUT_ENABLES_OS_TYPE \
13282 * This bit must be '1' for the ver field to be
13285 #define HWRM_FUNC_DRV_RGTR_INPUT_ENABLES_VER \
13288 * This bit must be '1' for the timestamp field to be
13291 #define HWRM_FUNC_DRV_RGTR_INPUT_ENABLES_TIMESTAMP \
13294 * This bit must be '1' for the vf_req_fwd field to be
13297 #define HWRM_FUNC_DRV_RGTR_INPUT_ENABLES_VF_REQ_FWD \
13300 * This bit must be '1' for the async_event_fwd field to be
13303 #define HWRM_FUNC_DRV_RGTR_INPUT_ENABLES_ASYNC_EVENT_FWD \
13305 /* This value indicates the type of OS. The values are based on CIM_OperatingSystem.mof file as published by the DMTF. */
13308 #define HWRM_FUNC_DRV_RGTR_INPUT_OS_TYPE_UNKNOWN UINT32_C(0x0)
13309 /* Other OS not listed below. */
13310 #define HWRM_FUNC_DRV_RGTR_INPUT_OS_TYPE_OTHER UINT32_C(0x1)
13312 #define HWRM_FUNC_DRV_RGTR_INPUT_OS_TYPE_MSDOS UINT32_C(0xe)
13314 #define HWRM_FUNC_DRV_RGTR_INPUT_OS_TYPE_WINDOWS UINT32_C(0x12)
13316 #define HWRM_FUNC_DRV_RGTR_INPUT_OS_TYPE_SOLARIS UINT32_C(0x1d)
13318 #define HWRM_FUNC_DRV_RGTR_INPUT_OS_TYPE_LINUX UINT32_C(0x24)
13320 #define HWRM_FUNC_DRV_RGTR_INPUT_OS_TYPE_FREEBSD UINT32_C(0x2a)
13321 /* VMware ESXi OS. */
13322 #define HWRM_FUNC_DRV_RGTR_INPUT_OS_TYPE_ESXI UINT32_C(0x68)
13323 /* Microsoft Windows 8 64-bit OS. */
13324 #define HWRM_FUNC_DRV_RGTR_INPUT_OS_TYPE_WIN864 UINT32_C(0x73)
13325 /* Microsoft Windows Server 2012 R2 OS. */
13326 #define HWRM_FUNC_DRV_RGTR_INPUT_OS_TYPE_WIN2012R2 UINT32_C(0x74)
13328 #define HWRM_FUNC_DRV_RGTR_INPUT_OS_TYPE_UEFI UINT32_C(0x8000)
13329 #define HWRM_FUNC_DRV_RGTR_INPUT_OS_TYPE_LAST \
13330 HWRM_FUNC_DRV_RGTR_INPUT_OS_TYPE_UEFI
13331 /* This is the 8bit major version of the driver. */
13332 uint8_t ver_maj_8b;
13333 /* This is the 8bit minor version of the driver. */
13334 uint8_t ver_min_8b;
13335 /* This is the 8bit update version of the driver. */
13336 uint8_t ver_upd_8b;
13337 uint8_t unused_0[3];
13339 * This is a 32-bit timestamp provided by the driver for
13341 * The timestamp is in multiples of 1ms.
13343 uint32_t timestamp;
13344 uint8_t unused_1[4];
13346 * This is a 256-bit bit mask provided by the PF driver for
13347 * letting the HWRM know what commands issued by the VF driver
13348 * to the HWRM should be forwarded to the PF driver.
13349 * Nth bit refers to the Nth req_type.
13351 * Setting Nth bit to 1 indicates that requests from the
13352 * VF driver with req_type equal to N shall be forwarded to
13353 * the parent PF driver.
13355 * This field is not valid for the VF driver.
13357 uint32_t vf_req_fwd[8];
13359 * This is a 256-bit bit mask provided by the function driver
13360 * (PF or VF driver) to indicate the list of asynchronous event
13361 * completions to be forwarded.
13363 * Nth bit refers to the Nth event_id.
13365 * Setting Nth bit to 1 by the function driver shall result in
13366 * the HWRM forwarding asynchronous event completion with
13367 * event_id equal to N.
13369 * If all bits are set to 0 (value of 0), then the HWRM shall
13370 * not forward any asynchronous event completion to this
13373 uint32_t async_event_fwd[8];
13374 /* This is the 16bit major version of the driver. */
13376 /* This is the 16bit minor version of the driver. */
13378 /* This is the 16bit update version of the driver. */
13380 /* This is the 16bit patch version of the driver. */
13381 uint16_t ver_patch;
13384 /* hwrm_func_drv_rgtr_output (size:128b/16B) */
13385 struct hwrm_func_drv_rgtr_output {
13386 /* The specific error status for the command. */
13387 uint16_t error_code;
13388 /* The HWRM command request type. */
13390 /* The sequence ID from the original command. */
13392 /* The length of the response data in number of bytes. */
13396 * When this bit is '1', it indicates that the
13397 * HWRM_FUNC_DRV_IF_CHANGE call is supported.
13399 #define HWRM_FUNC_DRV_RGTR_OUTPUT_FLAGS_IF_CHANGE_SUPPORTED \
13401 uint8_t unused_0[3];
13403 * This field is used in Output records to indicate that the output
13404 * is completely written to RAM. This field should be read as '1'
13405 * to indicate that the output has been completely written.
13406 * When writing a command completion or response to an internal processor,
13407 * the order of writes has to be such that this field is written last.
13412 /************************
13413 * hwrm_func_drv_unrgtr *
13414 ************************/
13417 /* hwrm_func_drv_unrgtr_input (size:192b/24B) */
13418 struct hwrm_func_drv_unrgtr_input {
13419 /* The HWRM command request type. */
13422 * The completion ring to send the completion event on. This should
13423 * be the NQ ID returned from the `nq_alloc` HWRM command.
13425 uint16_t cmpl_ring;
13427 * The sequence ID is used by the driver for tracking multiple
13428 * commands. This ID is treated as opaque data by the firmware and
13429 * the value is returned in the `hwrm_resp_hdr` upon completion.
13433 * The target ID of the command:
13434 * * 0x0-0xFFF8 - The function ID
13435 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
13436 * * 0xFFFD - Reserved for user-space HWRM interface
13439 uint16_t target_id;
13441 * A physical address pointer pointing to a host buffer that the
13442 * command's response data will be written. This can be either a host
13443 * physical address (HPA) or a guest physical address (GPA) and must
13444 * point to a physically contiguous block of memory.
13446 uint64_t resp_addr;
13449 * When this bit is '1', the function driver is notifying
13450 * the HWRM to prepare for the shutdown.
13452 #define HWRM_FUNC_DRV_UNRGTR_INPUT_FLAGS_PREPARE_FOR_SHUTDOWN \
13454 uint8_t unused_0[4];
13457 /* hwrm_func_drv_unrgtr_output (size:128b/16B) */
13458 struct hwrm_func_drv_unrgtr_output {
13459 /* The specific error status for the command. */
13460 uint16_t error_code;
13461 /* The HWRM command request type. */
13463 /* The sequence ID from the original command. */
13465 /* The length of the response data in number of bytes. */
13467 uint8_t unused_0[7];
13469 * This field is used in Output records to indicate that the output
13470 * is completely written to RAM. This field should be read as '1'
13471 * to indicate that the output has been completely written.
13472 * When writing a command completion or response to an internal processor,
13473 * the order of writes has to be such that this field is written last.
13478 /**********************
13479 * hwrm_func_buf_rgtr *
13480 **********************/
13483 /* hwrm_func_buf_rgtr_input (size:1024b/128B) */
13484 struct hwrm_func_buf_rgtr_input {
13485 /* The HWRM command request type. */
13488 * The completion ring to send the completion event on. This should
13489 * be the NQ ID returned from the `nq_alloc` HWRM command.
13491 uint16_t cmpl_ring;
13493 * The sequence ID is used by the driver for tracking multiple
13494 * commands. This ID is treated as opaque data by the firmware and
13495 * the value is returned in the `hwrm_resp_hdr` upon completion.
13499 * The target ID of the command:
13500 * * 0x0-0xFFF8 - The function ID
13501 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
13502 * * 0xFFFD - Reserved for user-space HWRM interface
13505 uint16_t target_id;
13507 * A physical address pointer pointing to a host buffer that the
13508 * command's response data will be written. This can be either a host
13509 * physical address (HPA) or a guest physical address (GPA) and must
13510 * point to a physically contiguous block of memory.
13512 uint64_t resp_addr;
13515 * This bit must be '1' for the vf_id field to be
13518 #define HWRM_FUNC_BUF_RGTR_INPUT_ENABLES_VF_ID UINT32_C(0x1)
13520 * This bit must be '1' for the err_buf_addr field to be
13523 #define HWRM_FUNC_BUF_RGTR_INPUT_ENABLES_ERR_BUF_ADDR UINT32_C(0x2)
13525 * This value is used to identify a Virtual Function (VF).
13526 * The scope of VF ID is local within a PF.
13530 * This field represents the number of pages used for request
13533 uint16_t req_buf_num_pages;
13535 * This field represents the page size used for request
13538 uint16_t req_buf_page_size;
13540 #define HWRM_FUNC_BUF_RGTR_INPUT_REQ_BUF_PAGE_SIZE_16B UINT32_C(0x4)
13542 #define HWRM_FUNC_BUF_RGTR_INPUT_REQ_BUF_PAGE_SIZE_4K UINT32_C(0xc)
13544 #define HWRM_FUNC_BUF_RGTR_INPUT_REQ_BUF_PAGE_SIZE_8K UINT32_C(0xd)
13546 #define HWRM_FUNC_BUF_RGTR_INPUT_REQ_BUF_PAGE_SIZE_64K UINT32_C(0x10)
13548 #define HWRM_FUNC_BUF_RGTR_INPUT_REQ_BUF_PAGE_SIZE_2M UINT32_C(0x15)
13550 #define HWRM_FUNC_BUF_RGTR_INPUT_REQ_BUF_PAGE_SIZE_4M UINT32_C(0x16)
13552 #define HWRM_FUNC_BUF_RGTR_INPUT_REQ_BUF_PAGE_SIZE_1G UINT32_C(0x1e)
13553 #define HWRM_FUNC_BUF_RGTR_INPUT_REQ_BUF_PAGE_SIZE_LAST \
13554 HWRM_FUNC_BUF_RGTR_INPUT_REQ_BUF_PAGE_SIZE_1G
13555 /* The length of the request buffer per VF in bytes. */
13556 uint16_t req_buf_len;
13557 /* The length of the response buffer in bytes. */
13558 uint16_t resp_buf_len;
13559 uint8_t unused_0[2];
13560 /* This field represents the page address of page #0. */
13561 uint64_t req_buf_page_addr0;
13562 /* This field represents the page address of page #1. */
13563 uint64_t req_buf_page_addr1;
13564 /* This field represents the page address of page #2. */
13565 uint64_t req_buf_page_addr2;
13566 /* This field represents the page address of page #3. */
13567 uint64_t req_buf_page_addr3;
13568 /* This field represents the page address of page #4. */
13569 uint64_t req_buf_page_addr4;
13570 /* This field represents the page address of page #5. */
13571 uint64_t req_buf_page_addr5;
13572 /* This field represents the page address of page #6. */
13573 uint64_t req_buf_page_addr6;
13574 /* This field represents the page address of page #7. */
13575 uint64_t req_buf_page_addr7;
13576 /* This field represents the page address of page #8. */
13577 uint64_t req_buf_page_addr8;
13578 /* This field represents the page address of page #9. */
13579 uint64_t req_buf_page_addr9;
13581 * This field is used to receive the error reporting from
13582 * the chipset. Only applicable for PFs.
13584 uint64_t error_buf_addr;
13586 * This field is used to receive the response forwarded by the
13589 uint64_t resp_buf_addr;
13592 /* hwrm_func_buf_rgtr_output (size:128b/16B) */
13593 struct hwrm_func_buf_rgtr_output {
13594 /* The specific error status for the command. */
13595 uint16_t error_code;
13596 /* The HWRM command request type. */
13598 /* The sequence ID from the original command. */
13600 /* The length of the response data in number of bytes. */
13602 uint8_t unused_0[7];
13604 * This field is used in Output records to indicate that the output
13605 * is completely written to RAM. This field should be read as '1'
13606 * to indicate that the output has been completely written.
13607 * When writing a command completion or response to an internal processor,
13608 * the order of writes has to be such that this field is written last.
13613 /************************
13614 * hwrm_func_buf_unrgtr *
13615 ************************/
13618 /* hwrm_func_buf_unrgtr_input (size:192b/24B) */
13619 struct hwrm_func_buf_unrgtr_input {
13620 /* The HWRM command request type. */
13623 * The completion ring to send the completion event on. This should
13624 * be the NQ ID returned from the `nq_alloc` HWRM command.
13626 uint16_t cmpl_ring;
13628 * The sequence ID is used by the driver for tracking multiple
13629 * commands. This ID is treated as opaque data by the firmware and
13630 * the value is returned in the `hwrm_resp_hdr` upon completion.
13634 * The target ID of the command:
13635 * * 0x0-0xFFF8 - The function ID
13636 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
13637 * * 0xFFFD - Reserved for user-space HWRM interface
13640 uint16_t target_id;
13642 * A physical address pointer pointing to a host buffer that the
13643 * command's response data will be written. This can be either a host
13644 * physical address (HPA) or a guest physical address (GPA) and must
13645 * point to a physically contiguous block of memory.
13647 uint64_t resp_addr;
13650 * This bit must be '1' for the vf_id field to be
13653 #define HWRM_FUNC_BUF_UNRGTR_INPUT_ENABLES_VF_ID UINT32_C(0x1)
13655 * This value is used to identify a Virtual Function (VF).
13656 * The scope of VF ID is local within a PF.
13659 uint8_t unused_0[2];
13662 /* hwrm_func_buf_unrgtr_output (size:128b/16B) */
13663 struct hwrm_func_buf_unrgtr_output {
13664 /* The specific error status for the command. */
13665 uint16_t error_code;
13666 /* The HWRM command request type. */
13668 /* The sequence ID from the original command. */
13670 /* The length of the response data in number of bytes. */
13672 uint8_t unused_0[7];
13674 * This field is used in Output records to indicate that the output
13675 * is completely written to RAM. This field should be read as '1'
13676 * to indicate that the output has been completely written.
13677 * When writing a command completion or response to an internal processor,
13678 * the order of writes has to be such that this field is written last.
13683 /**********************
13684 * hwrm_func_drv_qver *
13685 **********************/
13688 /* hwrm_func_drv_qver_input (size:192b/24B) */
13689 struct hwrm_func_drv_qver_input {
13690 /* The HWRM command request type. */
13693 * The completion ring to send the completion event on. This should
13694 * be the NQ ID returned from the `nq_alloc` HWRM command.
13696 uint16_t cmpl_ring;
13698 * The sequence ID is used by the driver for tracking multiple
13699 * commands. This ID is treated as opaque data by the firmware and
13700 * the value is returned in the `hwrm_resp_hdr` upon completion.
13704 * The target ID of the command:
13705 * * 0x0-0xFFF8 - The function ID
13706 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
13707 * * 0xFFFD - Reserved for user-space HWRM interface
13710 uint16_t target_id;
13712 * A physical address pointer pointing to a host buffer that the
13713 * command's response data will be written. This can be either a host
13714 * physical address (HPA) or a guest physical address (GPA) and must
13715 * point to a physically contiguous block of memory.
13717 uint64_t resp_addr;
13718 /* Reserved for future use. */
13721 * Function ID of the function that is being queried.
13722 * 0xFF... (All Fs) if the query is for the requesting
13726 uint8_t unused_0[2];
13729 /* hwrm_func_drv_qver_output (size:256b/32B) */
13730 struct hwrm_func_drv_qver_output {
13731 /* The specific error status for the command. */
13732 uint16_t error_code;
13733 /* The HWRM command request type. */
13735 /* The sequence ID from the original command. */
13737 /* The length of the response data in number of bytes. */
13739 /* This value indicates the type of OS. The values are based on CIM_OperatingSystem.mof file as published by the DMTF. */
13742 #define HWRM_FUNC_DRV_QVER_OUTPUT_OS_TYPE_UNKNOWN UINT32_C(0x0)
13743 /* Other OS not listed below. */
13744 #define HWRM_FUNC_DRV_QVER_OUTPUT_OS_TYPE_OTHER UINT32_C(0x1)
13746 #define HWRM_FUNC_DRV_QVER_OUTPUT_OS_TYPE_MSDOS UINT32_C(0xe)
13748 #define HWRM_FUNC_DRV_QVER_OUTPUT_OS_TYPE_WINDOWS UINT32_C(0x12)
13750 #define HWRM_FUNC_DRV_QVER_OUTPUT_OS_TYPE_SOLARIS UINT32_C(0x1d)
13752 #define HWRM_FUNC_DRV_QVER_OUTPUT_OS_TYPE_LINUX UINT32_C(0x24)
13754 #define HWRM_FUNC_DRV_QVER_OUTPUT_OS_TYPE_FREEBSD UINT32_C(0x2a)
13755 /* VMware ESXi OS. */
13756 #define HWRM_FUNC_DRV_QVER_OUTPUT_OS_TYPE_ESXI UINT32_C(0x68)
13757 /* Microsoft Windows 8 64-bit OS. */
13758 #define HWRM_FUNC_DRV_QVER_OUTPUT_OS_TYPE_WIN864 UINT32_C(0x73)
13759 /* Microsoft Windows Server 2012 R2 OS. */
13760 #define HWRM_FUNC_DRV_QVER_OUTPUT_OS_TYPE_WIN2012R2 UINT32_C(0x74)
13762 #define HWRM_FUNC_DRV_QVER_OUTPUT_OS_TYPE_UEFI UINT32_C(0x8000)
13763 #define HWRM_FUNC_DRV_QVER_OUTPUT_OS_TYPE_LAST \
13764 HWRM_FUNC_DRV_QVER_OUTPUT_OS_TYPE_UEFI
13765 /* This is the 8bit major version of the driver. */
13766 uint8_t ver_maj_8b;
13767 /* This is the 8bit minor version of the driver. */
13768 uint8_t ver_min_8b;
13769 /* This is the 8bit update version of the driver. */
13770 uint8_t ver_upd_8b;
13771 uint8_t unused_0[3];
13772 /* This is the 16bit major version of the driver. */
13774 /* This is the 16bit minor version of the driver. */
13776 /* This is the 16bit update version of the driver. */
13778 /* This is the 16bit patch version of the driver. */
13779 uint16_t ver_patch;
13780 uint8_t unused_1[7];
13782 * This field is used in Output records to indicate that the output
13783 * is completely written to RAM. This field should be read as '1'
13784 * to indicate that the output has been completely written.
13785 * When writing a command completion or response to an internal processor,
13786 * the order of writes has to be such that this field is written last.
13791 /****************************
13792 * hwrm_func_resource_qcaps *
13793 ****************************/
13796 /* hwrm_func_resource_qcaps_input (size:192b/24B) */
13797 struct hwrm_func_resource_qcaps_input {
13798 /* The HWRM command request type. */
13801 * The completion ring to send the completion event on. This should
13802 * be the NQ ID returned from the `nq_alloc` HWRM command.
13804 uint16_t cmpl_ring;
13806 * The sequence ID is used by the driver for tracking multiple
13807 * commands. This ID is treated as opaque data by the firmware and
13808 * the value is returned in the `hwrm_resp_hdr` upon completion.
13812 * The target ID of the command:
13813 * * 0x0-0xFFF8 - The function ID
13814 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
13815 * * 0xFFFD - Reserved for user-space HWRM interface
13818 uint16_t target_id;
13820 * A physical address pointer pointing to a host buffer that the
13821 * command's response data will be written. This can be either a host
13822 * physical address (HPA) or a guest physical address (GPA) and must
13823 * point to a physically contiguous block of memory.
13825 uint64_t resp_addr;
13827 * Function ID of the function that is being queried.
13828 * 0xFF... (All Fs) if the query is for the requesting
13832 uint8_t unused_0[6];
13835 /* hwrm_func_resource_qcaps_output (size:448b/56B) */
13836 struct hwrm_func_resource_qcaps_output {
13837 /* The specific error status for the command. */
13838 uint16_t error_code;
13839 /* The HWRM command request type. */
13841 /* The sequence ID from the original command. */
13843 /* The length of the response data in number of bytes. */
13845 /* Maximum guaranteed number of VFs supported by PF. Not applicable for VFs. */
13847 /* Maximum guaranteed number of MSI-X vectors supported by function */
13849 /* Hint of strategy to be used by PF driver to reserve resources for its VF */
13850 uint16_t vf_reservation_strategy;
13851 /* The PF driver should evenly divide its remaining resources among all VFs. */
13852 #define HWRM_FUNC_RESOURCE_QCAPS_OUTPUT_VF_RESERVATION_STRATEGY_MAXIMAL \
13854 /* The PF driver should only reserve minimal resources for each VF. */
13855 #define HWRM_FUNC_RESOURCE_QCAPS_OUTPUT_VF_RESERVATION_STRATEGY_MINIMAL \
13858 * The PF driver should not reserve any resources for each VF until the
13859 * the VF interface is brought up.
13861 #define HWRM_FUNC_RESOURCE_QCAPS_OUTPUT_VF_RESERVATION_STRATEGY_MINIMAL_STATIC \
13863 #define HWRM_FUNC_RESOURCE_QCAPS_OUTPUT_VF_RESERVATION_STRATEGY_LAST \
13864 HWRM_FUNC_RESOURCE_QCAPS_OUTPUT_VF_RESERVATION_STRATEGY_MINIMAL_STATIC
13865 /* Minimum guaranteed number of RSS/COS contexts */
13866 uint16_t min_rsscos_ctx;
13867 /* Maximum non-guaranteed number of RSS/COS contexts */
13868 uint16_t max_rsscos_ctx;
13869 /* Minimum guaranteed number of completion rings */
13870 uint16_t min_cmpl_rings;
13871 /* Maximum non-guaranteed number of completion rings */
13872 uint16_t max_cmpl_rings;
13873 /* Minimum guaranteed number of transmit rings */
13874 uint16_t min_tx_rings;
13875 /* Maximum non-guaranteed number of transmit rings */
13876 uint16_t max_tx_rings;
13877 /* Minimum guaranteed number of receive rings */
13878 uint16_t min_rx_rings;
13879 /* Maximum non-guaranteed number of receive rings */
13880 uint16_t max_rx_rings;
13881 /* Minimum guaranteed number of L2 contexts */
13882 uint16_t min_l2_ctxs;
13883 /* Maximum non-guaranteed number of L2 contexts */
13884 uint16_t max_l2_ctxs;
13885 /* Minimum guaranteed number of VNICs */
13886 uint16_t min_vnics;
13887 /* Maximum non-guaranteed number of VNICs */
13888 uint16_t max_vnics;
13889 /* Minimum guaranteed number of statistic contexts */
13890 uint16_t min_stat_ctx;
13891 /* Maximum non-guaranteed number of statistic contexts */
13892 uint16_t max_stat_ctx;
13893 /* Minimum guaranteed number of ring groups */
13894 uint16_t min_hw_ring_grps;
13895 /* Maximum non-guaranteed number of ring groups */
13896 uint16_t max_hw_ring_grps;
13898 * Maximum number of inputs into the transmit scheduler for this function.
13899 * The number of TX rings assigned to the function cannot exceed this value.
13901 uint16_t max_tx_scheduler_inputs;
13904 * When this bit is '1', it indicates that VF_RESOURCE_CFG supports
13905 * feature to reserve all minimum resources when minimum >= 1, otherwise
13906 * returns an error.
13908 #define HWRM_FUNC_RESOURCE_QCAPS_OUTPUT_FLAGS_MIN_GUARANTEED \
13910 uint8_t unused_0[5];
13912 * This field is used in Output records to indicate that the output
13913 * is completely written to RAM. This field should be read as '1'
13914 * to indicate that the output has been completely written.
13915 * When writing a command completion or response to an internal processor,
13916 * the order of writes has to be such that this field is written last.
13921 /*****************************
13922 * hwrm_func_vf_resource_cfg *
13923 *****************************/
13926 /* hwrm_func_vf_resource_cfg_input (size:448b/56B) */
13927 struct hwrm_func_vf_resource_cfg_input {
13928 /* The HWRM command request type. */
13931 * The completion ring to send the completion event on. This should
13932 * be the NQ ID returned from the `nq_alloc` HWRM command.
13934 uint16_t cmpl_ring;
13936 * The sequence ID is used by the driver for tracking multiple
13937 * commands. This ID is treated as opaque data by the firmware and
13938 * the value is returned in the `hwrm_resp_hdr` upon completion.
13942 * The target ID of the command:
13943 * * 0x0-0xFFF8 - The function ID
13944 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
13945 * * 0xFFFD - Reserved for user-space HWRM interface
13948 uint16_t target_id;
13950 * A physical address pointer pointing to a host buffer that the
13951 * command's response data will be written. This can be either a host
13952 * physical address (HPA) or a guest physical address (GPA) and must
13953 * point to a physically contiguous block of memory.
13955 uint64_t resp_addr;
13956 /* VF ID that is being configured by PF */
13958 /* Maximum guaranteed number of MSI-X vectors for the function */
13960 /* Minimum guaranteed number of RSS/COS contexts */
13961 uint16_t min_rsscos_ctx;
13962 /* Maximum non-guaranteed number of RSS/COS contexts */
13963 uint16_t max_rsscos_ctx;
13964 /* Minimum guaranteed number of completion rings */
13965 uint16_t min_cmpl_rings;
13966 /* Maximum non-guaranteed number of completion rings */
13967 uint16_t max_cmpl_rings;
13968 /* Minimum guaranteed number of transmit rings */
13969 uint16_t min_tx_rings;
13970 /* Maximum non-guaranteed number of transmit rings */
13971 uint16_t max_tx_rings;
13972 /* Minimum guaranteed number of receive rings */
13973 uint16_t min_rx_rings;
13974 /* Maximum non-guaranteed number of receive rings */
13975 uint16_t max_rx_rings;
13976 /* Minimum guaranteed number of L2 contexts */
13977 uint16_t min_l2_ctxs;
13978 /* Maximum non-guaranteed number of L2 contexts */
13979 uint16_t max_l2_ctxs;
13980 /* Minimum guaranteed number of VNICs */
13981 uint16_t min_vnics;
13982 /* Maximum non-guaranteed number of VNICs */
13983 uint16_t max_vnics;
13984 /* Minimum guaranteed number of statistic contexts */
13985 uint16_t min_stat_ctx;
13986 /* Maximum non-guaranteed number of statistic contexts */
13987 uint16_t max_stat_ctx;
13988 /* Minimum guaranteed number of ring groups */
13989 uint16_t min_hw_ring_grps;
13990 /* Maximum non-guaranteed number of ring groups */
13991 uint16_t max_hw_ring_grps;
13994 * If this bit is set, all minimum resources requested should be
13995 * reserved if minimum >= 1, otherwise return error. In case of
13996 * error, keep all existing reservations before the call.
13998 #define HWRM_FUNC_VF_RESOURCE_CFG_INPUT_FLAGS_MIN_GUARANTEED \
14000 uint8_t unused_0[2];
14003 /* hwrm_func_vf_resource_cfg_output (size:256b/32B) */
14004 struct hwrm_func_vf_resource_cfg_output {
14005 /* The specific error status for the command. */
14006 uint16_t error_code;
14007 /* The HWRM command request type. */
14009 /* The sequence ID from the original command. */
14011 /* The length of the response data in number of bytes. */
14013 /* Reserved number of RSS/COS contexts */
14014 uint16_t reserved_rsscos_ctx;
14015 /* Reserved number of completion rings */
14016 uint16_t reserved_cmpl_rings;
14017 /* Reserved number of transmit rings */
14018 uint16_t reserved_tx_rings;
14019 /* Reserved number of receive rings */
14020 uint16_t reserved_rx_rings;
14021 /* Reserved number of L2 contexts */
14022 uint16_t reserved_l2_ctxs;
14023 /* Reserved number of VNICs */
14024 uint16_t reserved_vnics;
14025 /* Reserved number of statistic contexts */
14026 uint16_t reserved_stat_ctx;
14027 /* Reserved number of ring groups */
14028 uint16_t reserved_hw_ring_grps;
14029 uint8_t unused_0[7];
14031 * This field is used in Output records to indicate that the output
14032 * is completely written to RAM. This field should be read as '1'
14033 * to indicate that the output has been completely written.
14034 * When writing a command completion or response to an internal processor,
14035 * the order of writes has to be such that this field is written last.
14040 /*********************************
14041 * hwrm_func_backing_store_qcaps *
14042 *********************************/
14045 /* hwrm_func_backing_store_qcaps_input (size:128b/16B) */
14046 struct hwrm_func_backing_store_qcaps_input {
14047 /* The HWRM command request type. */
14050 * The completion ring to send the completion event on. This should
14051 * be the NQ ID returned from the `nq_alloc` HWRM command.
14053 uint16_t cmpl_ring;
14055 * The sequence ID is used by the driver for tracking multiple
14056 * commands. This ID is treated as opaque data by the firmware and
14057 * the value is returned in the `hwrm_resp_hdr` upon completion.
14061 * The target ID of the command:
14062 * * 0x0-0xFFF8 - The function ID
14063 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
14064 * * 0xFFFD - Reserved for user-space HWRM interface
14067 uint16_t target_id;
14069 * A physical address pointer pointing to a host buffer that the
14070 * command's response data will be written. This can be either a host
14071 * physical address (HPA) or a guest physical address (GPA) and must
14072 * point to a physically contiguous block of memory.
14074 uint64_t resp_addr;
14077 /* hwrm_func_backing_store_qcaps_output (size:704b/88B) */
14078 struct hwrm_func_backing_store_qcaps_output {
14079 /* The specific error status for the command. */
14080 uint16_t error_code;
14081 /* The HWRM command request type. */
14083 /* The sequence ID from the original command. */
14085 /* The length of the response data in number of bytes. */
14087 /* Maximum number of QP context entries supported for this function. */
14088 uint32_t qp_max_entries;
14090 * Minimum number of QP context entries that are needed to be reserved
14091 * for QP1 for the PF and its VFs. PF drivers must allocate at least
14092 * this many QP context entries, even if RoCE will not be used.
14094 uint16_t qp_min_qp1_entries;
14095 /* Maximum number of QP context entries that can be used for L2. */
14096 uint16_t qp_max_l2_entries;
14097 /* Number of bytes that must be allocated for each context entry. */
14098 uint16_t qp_entry_size;
14099 /* Maximum number of SRQ context entries that can be used for L2. */
14100 uint16_t srq_max_l2_entries;
14101 /* Maximum number of SRQ context entries supported for this function. */
14102 uint32_t srq_max_entries;
14103 /* Number of bytes that must be allocated for each context entry. */
14104 uint16_t srq_entry_size;
14105 /* Maximum number of CQ context entries that can be used for L2. */
14106 uint16_t cq_max_l2_entries;
14107 /* Maximum number of CQ context entries supported for this function. */
14108 uint32_t cq_max_entries;
14109 /* Number of bytes that must be allocated for each context entry. */
14110 uint16_t cq_entry_size;
14111 /* Maximum number of VNIC context entries supported for this function. */
14112 uint16_t vnic_max_vnic_entries;
14113 /* Maximum number of Ring table context entries supported for this function. */
14114 uint16_t vnic_max_ring_table_entries;
14115 /* Number of bytes that must be allocated for each context entry. */
14116 uint16_t vnic_entry_size;
14117 /* Maximum number of statistic context entries supported for this function. */
14118 uint32_t stat_max_entries;
14119 /* Number of bytes that must be allocated for each context entry. */
14120 uint16_t stat_entry_size;
14121 /* Number of bytes that must be allocated for each context entry. */
14122 uint16_t tqm_entry_size;
14123 /* Minimum number of TQM context entries required per ring. */
14124 uint32_t tqm_min_entries_per_ring;
14126 * Maximum number of TQM context entries supported per ring. This is
14127 * actually a recommended TQM queue size based on worst case usage of
14130 * TQM fastpath rings should be sized large enough to accommodate the
14131 * maximum number of QPs (either L2 or RoCE, or both if shared)
14132 * that can be enqueued to the TQM ring.
14134 * TQM slowpath rings should be sized as follows:
14136 * num_entries = num_vnics + num_l2_tx_rings + 2 * num_roce_qps + tqm_min_size
14139 * num_vnics is the number of VNICs allocated in the VNIC backing store
14140 * num_l2_tx_rings is the number of L2 rings in the QP backing store
14141 * num_roce_qps is the number of RoCE QPs in the QP backing store
14142 * tqm_min_size is tqm_min_entries_per_ring reported by
14143 * HWRM_FUNC_BACKING_STORE_QCAPS
14145 * Note that TQM ring sizes cannot be extended while the system is
14146 * operational. If a PF driver needs to extend a TQM ring, it needs
14147 * to reset the function (e.g. HWRM_FUNC_RESET) and then reallocate
14148 * the backing store.
14150 uint32_t tqm_max_entries_per_ring;
14152 * Maximum number of MR plus AV context entries supported for this
14155 uint32_t mrav_max_entries;
14156 /* Number of bytes that must be allocated for each context entry. */
14157 uint16_t mrav_entry_size;
14158 /* Number of bytes that must be allocated for each context entry. */
14159 uint16_t tim_entry_size;
14160 /* Maximum number of Timer context entries supported for this function. */
14161 uint32_t tim_max_entries;
14163 * When this field is zero, the 32b `mrav_num_entries` field in the
14164 * `backing_store_cfg` and `backing_store_qcfg` commands represents
14165 * the total number of MR plus AV entries allowed in the MR/AV backing
14168 * When this field is non-zero, the 32b `mrav_num_entries` field in
14169 * the `backing_store_cfg` and `backing_store_qcfg` commands is
14170 * logically divided into two 16b fields. Bits `[31:16]` represents
14171 * the `mr_num_entries` and bits `[15:0]` represents `av_num_entries`.
14172 * Both of these values are represented in a unit granularity
14173 * specified by this field. For example, if this field is 16 and
14174 * `mrav_num_entries` is `0x02000100`, then the number of MR entries
14175 * is 8192 and the number of AV entries is 4096.
14177 uint16_t mrav_num_entries_units;
14179 * The number of entries specified for any TQM ring must be a
14180 * multiple of this value to prevent any resource allocation
14183 uint8_t tqm_entries_multiple;
14185 * Initializer to be used by drivers
14186 * to initialize context memory to ensure
14187 * context subsystem flags an error for an attack
14188 * before the first time context load.
14190 uint8_t ctx_kind_initializer;
14192 * Specifies which context kinds need to be initialized with the
14193 * ctx_kind_initializer.
14195 uint16_t ctx_init_mask;
14197 * If this bit is '1' then this context type should be initialized
14198 * with the ctx_kind_initializer at the specified offset.
14200 #define HWRM_FUNC_BACKING_STORE_QCAPS_OUTPUT_CTX_INIT_MASK_QP \
14203 * If this bit is '1' then this context type should be initialized
14204 * with the ctx_kind_initializer at the specified offset.
14206 #define HWRM_FUNC_BACKING_STORE_QCAPS_OUTPUT_CTX_INIT_MASK_SRQ \
14209 * If this bit is '1' then this context type should be initialized
14210 * with the ctx_kind_initializer at the specified offset.
14212 #define HWRM_FUNC_BACKING_STORE_QCAPS_OUTPUT_CTX_INIT_MASK_CQ \
14215 * If this bit is '1' then this context type should be initialized
14216 * with the ctx_kind_initializer at the specified offset.
14218 #define HWRM_FUNC_BACKING_STORE_QCAPS_OUTPUT_CTX_INIT_MASK_VNIC \
14221 * If this bit is '1' then this context type should be initialized
14222 * with the ctx_kind_initializer at the specified offset.
14224 #define HWRM_FUNC_BACKING_STORE_QCAPS_OUTPUT_CTX_INIT_MASK_STAT \
14227 * If this bit is '1' then this context type should be initialized
14228 * with the ctx_kind_initializer at the specified offset.
14230 #define HWRM_FUNC_BACKING_STORE_QCAPS_OUTPUT_CTX_INIT_MASK_MRAV \
14233 * Specifies the doubleword offset of ctx_kind_initializer for this
14236 uint8_t qp_init_offset;
14238 * Specifies the doubleword offset of ctx_kind_initializer for this
14241 uint8_t srq_init_offset;
14243 * Specifies the doubleword offset of ctx_kind_initializer for this
14246 uint8_t cq_init_offset;
14248 * Specifies the doubleword offset of ctx_kind_initializer for this
14251 uint8_t vnic_init_offset;
14253 * Count of TQM fastpath rings to be used for allocating backing store.
14254 * Backing store configuration must be specified for each TQM ring from
14255 * this count in `backing_store_cfg`.
14256 * Only first 8 TQM FP rings will be advertised with this field.
14258 uint8_t tqm_fp_rings_count;
14260 * Specifies the doubleword offset of ctx_kind_initializer for this
14263 uint8_t stat_init_offset;
14265 * Specifies the doubleword offset of ctx_kind_initializer for this
14268 uint8_t mrav_init_offset;
14270 * Count of TQM extended fastpath rings to be used for allocating
14271 * backing store beyond 8 rings(rings 9,10,11)
14272 * Backing store configuration must be specified for each TQM ring from
14273 * this count in `backing_store_cfg`.
14275 uint8_t tqm_fp_rings_count_ext;
14276 /* Reserved for future. */
14279 * This field is used in Output records to indicate that the output
14280 * is completely written to RAM. This field should be read as '1'
14281 * to indicate that the output has been completely written.
14282 * When writing a command completion or response to an internal processor,
14283 * the order of writes has to be such that this field is written last.
14288 /* tqm_fp_ring_cfg (size:128b/16B) */
14289 struct tqm_fp_ring_cfg {
14290 /* TQM ring page size and level. */
14291 uint8_t tqm_ring_pg_size_tqm_ring_lvl;
14292 /* TQM ring PBL indirect levels. */
14293 #define TQM_FP_RING_CFG_TQM_RING_CFG_TQM_RING_LVL_MASK \
14295 #define TQM_FP_RING_CFG_TQM_RING_CFG_TQM_RING_LVL_SFT 0
14296 /* PBL pointer is physical start address. */
14297 #define TQM_FP_RING_CFG_TQM_RING_CFG_TQM_RING_LVL_LVL_0 \
14299 /* PBL pointer points to PTE table. */
14300 #define TQM_FP_RING_CFG_TQM_RING_CFG_TQM_RING_LVL_LVL_1 \
14303 * PBL pointer points to PDE table with each entry pointing to
14306 #define TQM_FP_RING_CFG_TQM_RING_CFG_TQM_RING_LVL_LVL_2 \
14308 #define TQM_FP_RING_CFG_TQM_RING_CFG_TQM_RING_LVL_LAST \
14309 TQM_FP_RING_CFG_TQM_RING_CFG_TQM_RING_LVL_LVL_2
14310 /* TQM ring page size. */
14311 #define TQM_FP_RING_CFG_TQM_RING_CFG_TQM_RING_PG_SIZE_MASK \
14313 #define TQM_FP_RING_CFG_TQM_RING_CFG_TQM_RING_PG_SIZE_SFT 4
14315 #define TQM_FP_RING_CFG_TQM_RING_CFG_TQM_RING_PG_SIZE_PG_4K \
14316 (UINT32_C(0x0) << 4)
14318 #define TQM_FP_RING_CFG_TQM_RING_CFG_TQM_RING_PG_SIZE_PG_8K \
14319 (UINT32_C(0x1) << 4)
14321 #define TQM_FP_RING_CFG_TQM_RING_CFG_TQM_RING_PG_SIZE_PG_64K \
14322 (UINT32_C(0x2) << 4)
14324 #define TQM_FP_RING_CFG_TQM_RING_CFG_TQM_RING_PG_SIZE_PG_2M \
14325 (UINT32_C(0x3) << 4)
14327 #define TQM_FP_RING_CFG_TQM_RING_CFG_TQM_RING_PG_SIZE_PG_8M \
14328 (UINT32_C(0x4) << 4)
14330 #define TQM_FP_RING_CFG_TQM_RING_CFG_TQM_RING_PG_SIZE_PG_1G \
14331 (UINT32_C(0x5) << 4)
14332 #define TQM_FP_RING_CFG_TQM_RING_CFG_TQM_RING_PG_SIZE_LAST \
14333 TQM_FP_RING_CFG_TQM_RING_CFG_TQM_RING_PG_SIZE_PG_1G
14335 /* Number of TQM ring entries. */
14336 uint32_t tqm_ring_num_entries;
14337 /* TQM ring page directory. */
14338 uint64_t tqm_ring_page_dir;
14341 /*******************************
14342 * hwrm_func_backing_store_cfg *
14343 *******************************/
14346 /* hwrm_func_backing_store_cfg_input (size:2432b/304B) */
14347 struct hwrm_func_backing_store_cfg_input {
14348 /* The HWRM command request type. */
14351 * The completion ring to send the completion event on. This should
14352 * be the NQ ID returned from the `nq_alloc` HWRM command.
14354 uint16_t cmpl_ring;
14356 * The sequence ID is used by the driver for tracking multiple
14357 * commands. This ID is treated as opaque data by the firmware and
14358 * the value is returned in the `hwrm_resp_hdr` upon completion.
14362 * The target ID of the command:
14363 * * 0x0-0xFFF8 - The function ID
14364 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
14365 * * 0xFFFD - Reserved for user-space HWRM interface
14368 uint16_t target_id;
14370 * A physical address pointer pointing to a host buffer that the
14371 * command's response data will be written. This can be either a host
14372 * physical address (HPA) or a guest physical address (GPA) and must
14373 * point to a physically contiguous block of memory.
14375 uint64_t resp_addr;
14378 * When set, the firmware only uses on-chip resources and does not
14379 * expect any backing store to be provided by the host driver. This
14380 * mode provides minimal L2 functionality (e.g. limited L2 resources,
14383 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_FLAGS_PREBOOT_MODE \
14386 * When set, the 32b `mrav_num_entries` field is logically divided
14387 * into two 16b fields, `mr_num_entries` and `av_num_entries`.
14389 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_FLAGS_MRAV_RESERVATION_SPLIT \
14393 * This bit must be '1' for the qp fields to be
14396 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_QP \
14399 * This bit must be '1' for the srq fields to be
14402 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_SRQ \
14405 * This bit must be '1' for the cq fields to be
14408 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_CQ \
14411 * This bit must be '1' for the vnic fields to be
14414 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_VNIC \
14417 * This bit must be '1' for the stat fields to be
14420 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_STAT \
14423 * This bit must be '1' for the tqm_sp fields to be
14426 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_TQM_SP \
14429 * This bit must be '1' for the tqm_ring0 fields to be
14432 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_TQM_RING0 \
14435 * This bit must be '1' for the tqm_ring1 fields to be
14438 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_TQM_RING1 \
14441 * This bit must be '1' for the tqm_ring2 fields to be
14444 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_TQM_RING2 \
14447 * This bit must be '1' for the tqm_ring3 fields to be
14450 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_TQM_RING3 \
14453 * This bit must be '1' for the tqm_ring4 fields to be
14456 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_TQM_RING4 \
14459 * This bit must be '1' for the tqm_ring5 fields to be
14462 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_TQM_RING5 \
14465 * This bit must be '1' for the tqm_ring6 fields to be
14468 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_TQM_RING6 \
14471 * This bit must be '1' for the tqm_ring7 fields to be
14474 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_TQM_RING7 \
14477 * This bit must be '1' for the mrav fields to be
14480 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_MRAV \
14483 * This bit must be '1' for the tim fields to be
14486 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_TIM \
14489 * This bit must be '1' for the tqm_ring8 fields to be
14492 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_TQM_RING8 \
14495 * This bit must be '1' for the tqm_ring9 fields to be
14498 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_TQM_RING9 \
14501 * This bit must be '1' for the tqm_ring10 fields to be
14504 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_TQM_RING10 \
14506 /* QPC page size and level. */
14507 uint8_t qpc_pg_size_qpc_lvl;
14508 /* QPC PBL indirect levels. */
14509 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_QPC_LVL_MASK \
14511 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_QPC_LVL_SFT 0
14512 /* PBL pointer is physical start address. */
14513 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_QPC_LVL_LVL_0 \
14515 /* PBL pointer points to PTE table. */
14516 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_QPC_LVL_LVL_1 \
14518 /* PBL pointer points to PDE table with each entry pointing to PTE tables. */
14519 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_QPC_LVL_LVL_2 \
14521 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_QPC_LVL_LAST \
14522 HWRM_FUNC_BACKING_STORE_CFG_INPUT_QPC_LVL_LVL_2
14523 /* QPC page size. */
14524 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_QPC_PG_SIZE_MASK \
14526 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_QPC_PG_SIZE_SFT 4
14528 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_QPC_PG_SIZE_PG_4K \
14529 (UINT32_C(0x0) << 4)
14531 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_QPC_PG_SIZE_PG_8K \
14532 (UINT32_C(0x1) << 4)
14534 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_QPC_PG_SIZE_PG_64K \
14535 (UINT32_C(0x2) << 4)
14537 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_QPC_PG_SIZE_PG_2M \
14538 (UINT32_C(0x3) << 4)
14540 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_QPC_PG_SIZE_PG_8M \
14541 (UINT32_C(0x4) << 4)
14543 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_QPC_PG_SIZE_PG_1G \
14544 (UINT32_C(0x5) << 4)
14545 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_QPC_PG_SIZE_LAST \
14546 HWRM_FUNC_BACKING_STORE_CFG_INPUT_QPC_PG_SIZE_PG_1G
14547 /* SRQ page size and level. */
14548 uint8_t srq_pg_size_srq_lvl;
14549 /* SRQ PBL indirect levels. */
14550 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_SRQ_LVL_MASK \
14552 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_SRQ_LVL_SFT 0
14553 /* PBL pointer is physical start address. */
14554 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_SRQ_LVL_LVL_0 \
14556 /* PBL pointer points to PTE table. */
14557 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_SRQ_LVL_LVL_1 \
14559 /* PBL pointer points to PDE table with each entry pointing to PTE tables. */
14560 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_SRQ_LVL_LVL_2 \
14562 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_SRQ_LVL_LAST \
14563 HWRM_FUNC_BACKING_STORE_CFG_INPUT_SRQ_LVL_LVL_2
14564 /* SRQ page size. */
14565 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_SRQ_PG_SIZE_MASK \
14567 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_SRQ_PG_SIZE_SFT 4
14569 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_SRQ_PG_SIZE_PG_4K \
14570 (UINT32_C(0x0) << 4)
14572 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_SRQ_PG_SIZE_PG_8K \
14573 (UINT32_C(0x1) << 4)
14575 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_SRQ_PG_SIZE_PG_64K \
14576 (UINT32_C(0x2) << 4)
14578 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_SRQ_PG_SIZE_PG_2M \
14579 (UINT32_C(0x3) << 4)
14581 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_SRQ_PG_SIZE_PG_8M \
14582 (UINT32_C(0x4) << 4)
14584 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_SRQ_PG_SIZE_PG_1G \
14585 (UINT32_C(0x5) << 4)
14586 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_SRQ_PG_SIZE_LAST \
14587 HWRM_FUNC_BACKING_STORE_CFG_INPUT_SRQ_PG_SIZE_PG_1G
14588 /* CQ page size and level. */
14589 uint8_t cq_pg_size_cq_lvl;
14590 /* CQ PBL indirect levels. */
14591 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_CQ_LVL_MASK \
14593 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_CQ_LVL_SFT 0
14594 /* PBL pointer is physical start address. */
14595 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_CQ_LVL_LVL_0 \
14597 /* PBL pointer points to PTE table. */
14598 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_CQ_LVL_LVL_1 \
14600 /* PBL pointer points to PDE table with each entry pointing to PTE tables. */
14601 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_CQ_LVL_LVL_2 \
14603 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_CQ_LVL_LAST \
14604 HWRM_FUNC_BACKING_STORE_CFG_INPUT_CQ_LVL_LVL_2
14605 /* CQ page size. */
14606 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_CQ_PG_SIZE_MASK \
14608 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_CQ_PG_SIZE_SFT 4
14610 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_CQ_PG_SIZE_PG_4K \
14611 (UINT32_C(0x0) << 4)
14613 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_CQ_PG_SIZE_PG_8K \
14614 (UINT32_C(0x1) << 4)
14616 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_CQ_PG_SIZE_PG_64K \
14617 (UINT32_C(0x2) << 4)
14619 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_CQ_PG_SIZE_PG_2M \
14620 (UINT32_C(0x3) << 4)
14622 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_CQ_PG_SIZE_PG_8M \
14623 (UINT32_C(0x4) << 4)
14625 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_CQ_PG_SIZE_PG_1G \
14626 (UINT32_C(0x5) << 4)
14627 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_CQ_PG_SIZE_LAST \
14628 HWRM_FUNC_BACKING_STORE_CFG_INPUT_CQ_PG_SIZE_PG_1G
14629 /* VNIC page size and level. */
14630 uint8_t vnic_pg_size_vnic_lvl;
14631 /* VNIC PBL indirect levels. */
14632 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_VNIC_LVL_MASK \
14634 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_VNIC_LVL_SFT 0
14635 /* PBL pointer is physical start address. */
14636 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_VNIC_LVL_LVL_0 \
14638 /* PBL pointer points to PTE table. */
14639 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_VNIC_LVL_LVL_1 \
14641 /* PBL pointer points to PDE table with each entry pointing to PTE tables. */
14642 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_VNIC_LVL_LVL_2 \
14644 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_VNIC_LVL_LAST \
14645 HWRM_FUNC_BACKING_STORE_CFG_INPUT_VNIC_LVL_LVL_2
14646 /* VNIC page size. */
14647 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_VNIC_PG_SIZE_MASK \
14649 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_VNIC_PG_SIZE_SFT 4
14651 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_VNIC_PG_SIZE_PG_4K \
14652 (UINT32_C(0x0) << 4)
14654 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_VNIC_PG_SIZE_PG_8K \
14655 (UINT32_C(0x1) << 4)
14657 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_VNIC_PG_SIZE_PG_64K \
14658 (UINT32_C(0x2) << 4)
14660 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_VNIC_PG_SIZE_PG_2M \
14661 (UINT32_C(0x3) << 4)
14663 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_VNIC_PG_SIZE_PG_8M \
14664 (UINT32_C(0x4) << 4)
14666 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_VNIC_PG_SIZE_PG_1G \
14667 (UINT32_C(0x5) << 4)
14668 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_VNIC_PG_SIZE_LAST \
14669 HWRM_FUNC_BACKING_STORE_CFG_INPUT_VNIC_PG_SIZE_PG_1G
14670 /* Stat page size and level. */
14671 uint8_t stat_pg_size_stat_lvl;
14672 /* Stat PBL indirect levels. */
14673 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_STAT_LVL_MASK \
14675 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_STAT_LVL_SFT 0
14676 /* PBL pointer is physical start address. */
14677 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_STAT_LVL_LVL_0 \
14679 /* PBL pointer points to PTE table. */
14680 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_STAT_LVL_LVL_1 \
14682 /* PBL pointer points to PDE table with each entry pointing to PTE tables. */
14683 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_STAT_LVL_LVL_2 \
14685 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_STAT_LVL_LAST \
14686 HWRM_FUNC_BACKING_STORE_CFG_INPUT_STAT_LVL_LVL_2
14687 /* Stat page size. */
14688 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_STAT_PG_SIZE_MASK \
14690 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_STAT_PG_SIZE_SFT 4
14692 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_STAT_PG_SIZE_PG_4K \
14693 (UINT32_C(0x0) << 4)
14695 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_STAT_PG_SIZE_PG_8K \
14696 (UINT32_C(0x1) << 4)
14698 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_STAT_PG_SIZE_PG_64K \
14699 (UINT32_C(0x2) << 4)
14701 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_STAT_PG_SIZE_PG_2M \
14702 (UINT32_C(0x3) << 4)
14704 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_STAT_PG_SIZE_PG_8M \
14705 (UINT32_C(0x4) << 4)
14707 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_STAT_PG_SIZE_PG_1G \
14708 (UINT32_C(0x5) << 4)
14709 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_STAT_PG_SIZE_LAST \
14710 HWRM_FUNC_BACKING_STORE_CFG_INPUT_STAT_PG_SIZE_PG_1G
14711 /* TQM slow path page size and level. */
14712 uint8_t tqm_sp_pg_size_tqm_sp_lvl;
14713 /* TQM slow path PBL indirect levels. */
14714 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_SP_LVL_MASK \
14716 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_SP_LVL_SFT 0
14717 /* PBL pointer is physical start address. */
14718 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_SP_LVL_LVL_0 \
14720 /* PBL pointer points to PTE table. */
14721 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_SP_LVL_LVL_1 \
14723 /* PBL pointer points to PDE table with each entry pointing to PTE tables. */
14724 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_SP_LVL_LVL_2 \
14726 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_SP_LVL_LAST \
14727 HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_SP_LVL_LVL_2
14728 /* TQM slow path page size. */
14729 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_SP_PG_SIZE_MASK \
14731 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_SP_PG_SIZE_SFT 4
14733 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_SP_PG_SIZE_PG_4K \
14734 (UINT32_C(0x0) << 4)
14736 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_SP_PG_SIZE_PG_8K \
14737 (UINT32_C(0x1) << 4)
14739 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_SP_PG_SIZE_PG_64K \
14740 (UINT32_C(0x2) << 4)
14742 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_SP_PG_SIZE_PG_2M \
14743 (UINT32_C(0x3) << 4)
14745 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_SP_PG_SIZE_PG_8M \
14746 (UINT32_C(0x4) << 4)
14748 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_SP_PG_SIZE_PG_1G \
14749 (UINT32_C(0x5) << 4)
14750 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_SP_PG_SIZE_LAST \
14751 HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_SP_PG_SIZE_PG_1G
14752 /* TQM ring 0 page size and level. */
14753 uint8_t tqm_ring0_pg_size_tqm_ring0_lvl;
14754 /* TQM ring 0 PBL indirect levels. */
14755 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING0_LVL_MASK \
14757 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING0_LVL_SFT 0
14758 /* PBL pointer is physical start address. */
14759 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING0_LVL_LVL_0 \
14761 /* PBL pointer points to PTE table. */
14762 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING0_LVL_LVL_1 \
14764 /* PBL pointer points to PDE table with each entry pointing to PTE tables. */
14765 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING0_LVL_LVL_2 \
14767 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING0_LVL_LAST \
14768 HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING0_LVL_LVL_2
14769 /* TQM ring 0 page size. */
14770 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING0_PG_SIZE_MASK \
14772 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING0_PG_SIZE_SFT 4
14774 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING0_PG_SIZE_PG_4K \
14775 (UINT32_C(0x0) << 4)
14777 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING0_PG_SIZE_PG_8K \
14778 (UINT32_C(0x1) << 4)
14780 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING0_PG_SIZE_PG_64K \
14781 (UINT32_C(0x2) << 4)
14783 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING0_PG_SIZE_PG_2M \
14784 (UINT32_C(0x3) << 4)
14786 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING0_PG_SIZE_PG_8M \
14787 (UINT32_C(0x4) << 4)
14789 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING0_PG_SIZE_PG_1G \
14790 (UINT32_C(0x5) << 4)
14791 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING0_PG_SIZE_LAST \
14792 HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING0_PG_SIZE_PG_1G
14793 /* TQM ring 1 page size and level. */
14794 uint8_t tqm_ring1_pg_size_tqm_ring1_lvl;
14795 /* TQM ring 1 PBL indirect levels. */
14796 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING1_LVL_MASK \
14798 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING1_LVL_SFT 0
14799 /* PBL pointer is physical start address. */
14800 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING1_LVL_LVL_0 \
14802 /* PBL pointer points to PTE table. */
14803 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING1_LVL_LVL_1 \
14805 /* PBL pointer points to PDE table with each entry pointing to PTE tables. */
14806 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING1_LVL_LVL_2 \
14808 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING1_LVL_LAST \
14809 HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING1_LVL_LVL_2
14810 /* TQM ring 1 page size. */
14811 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING1_PG_SIZE_MASK \
14813 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING1_PG_SIZE_SFT 4
14815 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING1_PG_SIZE_PG_4K \
14816 (UINT32_C(0x0) << 4)
14818 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING1_PG_SIZE_PG_8K \
14819 (UINT32_C(0x1) << 4)
14821 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING1_PG_SIZE_PG_64K \
14822 (UINT32_C(0x2) << 4)
14824 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING1_PG_SIZE_PG_2M \
14825 (UINT32_C(0x3) << 4)
14827 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING1_PG_SIZE_PG_8M \
14828 (UINT32_C(0x4) << 4)
14830 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING1_PG_SIZE_PG_1G \
14831 (UINT32_C(0x5) << 4)
14832 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING1_PG_SIZE_LAST \
14833 HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING1_PG_SIZE_PG_1G
14834 /* TQM ring 2 page size and level. */
14835 uint8_t tqm_ring2_pg_size_tqm_ring2_lvl;
14836 /* TQM ring 2 PBL indirect levels. */
14837 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING2_LVL_MASK \
14839 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING2_LVL_SFT 0
14840 /* PBL pointer is physical start address. */
14841 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING2_LVL_LVL_0 \
14843 /* PBL pointer points to PTE table. */
14844 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING2_LVL_LVL_1 \
14846 /* PBL pointer points to PDE table with each entry pointing to PTE tables. */
14847 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING2_LVL_LVL_2 \
14849 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING2_LVL_LAST \
14850 HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING2_LVL_LVL_2
14851 /* TQM ring 2 page size. */
14852 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING2_PG_SIZE_MASK \
14854 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING2_PG_SIZE_SFT 4
14856 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING2_PG_SIZE_PG_4K \
14857 (UINT32_C(0x0) << 4)
14859 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING2_PG_SIZE_PG_8K \
14860 (UINT32_C(0x1) << 4)
14862 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING2_PG_SIZE_PG_64K \
14863 (UINT32_C(0x2) << 4)
14865 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING2_PG_SIZE_PG_2M \
14866 (UINT32_C(0x3) << 4)
14868 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING2_PG_SIZE_PG_8M \
14869 (UINT32_C(0x4) << 4)
14871 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING2_PG_SIZE_PG_1G \
14872 (UINT32_C(0x5) << 4)
14873 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING2_PG_SIZE_LAST \
14874 HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING2_PG_SIZE_PG_1G
14875 /* TQM ring 3 page size and level. */
14876 uint8_t tqm_ring3_pg_size_tqm_ring3_lvl;
14877 /* TQM ring 3 PBL indirect levels. */
14878 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING3_LVL_MASK \
14880 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING3_LVL_SFT 0
14881 /* PBL pointer is physical start address. */
14882 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING3_LVL_LVL_0 \
14884 /* PBL pointer points to PTE table. */
14885 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING3_LVL_LVL_1 \
14887 /* PBL pointer points to PDE table with each entry pointing to PTE tables. */
14888 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING3_LVL_LVL_2 \
14890 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING3_LVL_LAST \
14891 HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING3_LVL_LVL_2
14892 /* TQM ring 3 page size. */
14893 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING3_PG_SIZE_MASK \
14895 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING3_PG_SIZE_SFT 4
14897 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING3_PG_SIZE_PG_4K \
14898 (UINT32_C(0x0) << 4)
14900 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING3_PG_SIZE_PG_8K \
14901 (UINT32_C(0x1) << 4)
14903 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING3_PG_SIZE_PG_64K \
14904 (UINT32_C(0x2) << 4)
14906 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING3_PG_SIZE_PG_2M \
14907 (UINT32_C(0x3) << 4)
14909 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING3_PG_SIZE_PG_8M \
14910 (UINT32_C(0x4) << 4)
14912 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING3_PG_SIZE_PG_1G \
14913 (UINT32_C(0x5) << 4)
14914 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING3_PG_SIZE_LAST \
14915 HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING3_PG_SIZE_PG_1G
14916 /* TQM ring 4 page size and level. */
14917 uint8_t tqm_ring4_pg_size_tqm_ring4_lvl;
14918 /* TQM ring 4 PBL indirect levels. */
14919 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING4_LVL_MASK \
14921 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING4_LVL_SFT 0
14922 /* PBL pointer is physical start address. */
14923 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING4_LVL_LVL_0 \
14925 /* PBL pointer points to PTE table. */
14926 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING4_LVL_LVL_1 \
14928 /* PBL pointer points to PDE table with each entry pointing to PTE tables. */
14929 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING4_LVL_LVL_2 \
14931 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING4_LVL_LAST \
14932 HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING4_LVL_LVL_2
14933 /* TQM ring 4 page size. */
14934 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING4_PG_SIZE_MASK \
14936 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING4_PG_SIZE_SFT 4
14938 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING4_PG_SIZE_PG_4K \
14939 (UINT32_C(0x0) << 4)
14941 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING4_PG_SIZE_PG_8K \
14942 (UINT32_C(0x1) << 4)
14944 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING4_PG_SIZE_PG_64K \
14945 (UINT32_C(0x2) << 4)
14947 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING4_PG_SIZE_PG_2M \
14948 (UINT32_C(0x3) << 4)
14950 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING4_PG_SIZE_PG_8M \
14951 (UINT32_C(0x4) << 4)
14953 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING4_PG_SIZE_PG_1G \
14954 (UINT32_C(0x5) << 4)
14955 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING4_PG_SIZE_LAST \
14956 HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING4_PG_SIZE_PG_1G
14957 /* TQM ring 5 page size and level. */
14958 uint8_t tqm_ring5_pg_size_tqm_ring5_lvl;
14959 /* TQM ring 5 PBL indirect levels. */
14960 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING5_LVL_MASK \
14962 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING5_LVL_SFT 0
14963 /* PBL pointer is physical start address. */
14964 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING5_LVL_LVL_0 \
14966 /* PBL pointer points to PTE table. */
14967 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING5_LVL_LVL_1 \
14969 /* PBL pointer points to PDE table with each entry pointing to PTE tables. */
14970 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING5_LVL_LVL_2 \
14972 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING5_LVL_LAST \
14973 HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING5_LVL_LVL_2
14974 /* TQM ring 5 page size. */
14975 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING5_PG_SIZE_MASK \
14977 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING5_PG_SIZE_SFT 4
14979 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING5_PG_SIZE_PG_4K \
14980 (UINT32_C(0x0) << 4)
14982 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING5_PG_SIZE_PG_8K \
14983 (UINT32_C(0x1) << 4)
14985 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING5_PG_SIZE_PG_64K \
14986 (UINT32_C(0x2) << 4)
14988 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING5_PG_SIZE_PG_2M \
14989 (UINT32_C(0x3) << 4)
14991 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING5_PG_SIZE_PG_8M \
14992 (UINT32_C(0x4) << 4)
14994 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING5_PG_SIZE_PG_1G \
14995 (UINT32_C(0x5) << 4)
14996 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING5_PG_SIZE_LAST \
14997 HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING5_PG_SIZE_PG_1G
14998 /* TQM ring 6 page size and level. */
14999 uint8_t tqm_ring6_pg_size_tqm_ring6_lvl;
15000 /* TQM ring 6 PBL indirect levels. */
15001 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING6_LVL_MASK \
15003 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING6_LVL_SFT 0
15004 /* PBL pointer is physical start address. */
15005 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING6_LVL_LVL_0 \
15007 /* PBL pointer points to PTE table. */
15008 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING6_LVL_LVL_1 \
15010 /* PBL pointer points to PDE table with each entry pointing to PTE tables. */
15011 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING6_LVL_LVL_2 \
15013 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING6_LVL_LAST \
15014 HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING6_LVL_LVL_2
15015 /* TQM ring 6 page size. */
15016 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING6_PG_SIZE_MASK \
15018 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING6_PG_SIZE_SFT 4
15020 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING6_PG_SIZE_PG_4K \
15021 (UINT32_C(0x0) << 4)
15023 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING6_PG_SIZE_PG_8K \
15024 (UINT32_C(0x1) << 4)
15026 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING6_PG_SIZE_PG_64K \
15027 (UINT32_C(0x2) << 4)
15029 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING6_PG_SIZE_PG_2M \
15030 (UINT32_C(0x3) << 4)
15032 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING6_PG_SIZE_PG_8M \
15033 (UINT32_C(0x4) << 4)
15035 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING6_PG_SIZE_PG_1G \
15036 (UINT32_C(0x5) << 4)
15037 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING6_PG_SIZE_LAST \
15038 HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING6_PG_SIZE_PG_1G
15039 /* TQM ring 7 page size and level. */
15040 uint8_t tqm_ring7_pg_size_tqm_ring7_lvl;
15041 /* TQM ring 7 PBL indirect levels. */
15042 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING7_LVL_MASK \
15044 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING7_LVL_SFT 0
15045 /* PBL pointer is physical start address. */
15046 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING7_LVL_LVL_0 \
15048 /* PBL pointer points to PTE table. */
15049 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING7_LVL_LVL_1 \
15051 /* PBL pointer points to PDE table with each entry pointing to PTE tables. */
15052 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING7_LVL_LVL_2 \
15054 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING7_LVL_LAST \
15055 HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING7_LVL_LVL_2
15056 /* TQM ring 7 page size. */
15057 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING7_PG_SIZE_MASK \
15059 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING7_PG_SIZE_SFT 4
15061 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING7_PG_SIZE_PG_4K \
15062 (UINT32_C(0x0) << 4)
15064 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING7_PG_SIZE_PG_8K \
15065 (UINT32_C(0x1) << 4)
15067 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING7_PG_SIZE_PG_64K \
15068 (UINT32_C(0x2) << 4)
15070 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING7_PG_SIZE_PG_2M \
15071 (UINT32_C(0x3) << 4)
15073 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING7_PG_SIZE_PG_8M \
15074 (UINT32_C(0x4) << 4)
15076 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING7_PG_SIZE_PG_1G \
15077 (UINT32_C(0x5) << 4)
15078 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING7_PG_SIZE_LAST \
15079 HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING7_PG_SIZE_PG_1G
15080 /* MR/AV page size and level. */
15081 uint8_t mrav_pg_size_mrav_lvl;
15082 /* MR/AV PBL indirect levels. */
15083 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_MRAV_LVL_MASK \
15085 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_MRAV_LVL_SFT 0
15086 /* PBL pointer is physical start address. */
15087 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_MRAV_LVL_LVL_0 \
15089 /* PBL pointer points to PTE table. */
15090 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_MRAV_LVL_LVL_1 \
15092 /* PBL pointer points to PDE table with each entry pointing to PTE tables. */
15093 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_MRAV_LVL_LVL_2 \
15095 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_MRAV_LVL_LAST \
15096 HWRM_FUNC_BACKING_STORE_CFG_INPUT_MRAV_LVL_LVL_2
15097 /* MR/AV page size. */
15098 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_MRAV_PG_SIZE_MASK \
15100 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_MRAV_PG_SIZE_SFT 4
15102 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_MRAV_PG_SIZE_PG_4K \
15103 (UINT32_C(0x0) << 4)
15105 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_MRAV_PG_SIZE_PG_8K \
15106 (UINT32_C(0x1) << 4)
15108 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_MRAV_PG_SIZE_PG_64K \
15109 (UINT32_C(0x2) << 4)
15111 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_MRAV_PG_SIZE_PG_2M \
15112 (UINT32_C(0x3) << 4)
15114 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_MRAV_PG_SIZE_PG_8M \
15115 (UINT32_C(0x4) << 4)
15117 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_MRAV_PG_SIZE_PG_1G \
15118 (UINT32_C(0x5) << 4)
15119 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_MRAV_PG_SIZE_LAST \
15120 HWRM_FUNC_BACKING_STORE_CFG_INPUT_MRAV_PG_SIZE_PG_1G
15121 /* Timer page size and level. */
15122 uint8_t tim_pg_size_tim_lvl;
15123 /* Timer PBL indirect levels. */
15124 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TIM_LVL_MASK \
15126 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TIM_LVL_SFT 0
15127 /* PBL pointer is physical start address. */
15128 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TIM_LVL_LVL_0 \
15130 /* PBL pointer points to PTE table. */
15131 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TIM_LVL_LVL_1 \
15133 /* PBL pointer points to PDE table with each entry pointing to PTE tables. */
15134 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TIM_LVL_LVL_2 \
15136 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TIM_LVL_LAST \
15137 HWRM_FUNC_BACKING_STORE_CFG_INPUT_TIM_LVL_LVL_2
15138 /* Timer page size. */
15139 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TIM_PG_SIZE_MASK \
15141 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TIM_PG_SIZE_SFT 4
15143 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TIM_PG_SIZE_PG_4K \
15144 (UINT32_C(0x0) << 4)
15146 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TIM_PG_SIZE_PG_8K \
15147 (UINT32_C(0x1) << 4)
15149 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TIM_PG_SIZE_PG_64K \
15150 (UINT32_C(0x2) << 4)
15152 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TIM_PG_SIZE_PG_2M \
15153 (UINT32_C(0x3) << 4)
15155 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TIM_PG_SIZE_PG_8M \
15156 (UINT32_C(0x4) << 4)
15158 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TIM_PG_SIZE_PG_1G \
15159 (UINT32_C(0x5) << 4)
15160 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TIM_PG_SIZE_LAST \
15161 HWRM_FUNC_BACKING_STORE_CFG_INPUT_TIM_PG_SIZE_PG_1G
15162 /* QP page directory. */
15163 uint64_t qpc_page_dir;
15164 /* SRQ page directory. */
15165 uint64_t srq_page_dir;
15166 /* CQ page directory. */
15167 uint64_t cq_page_dir;
15168 /* VNIC page directory. */
15169 uint64_t vnic_page_dir;
15170 /* Stat page directory. */
15171 uint64_t stat_page_dir;
15172 /* TQM slowpath page directory. */
15173 uint64_t tqm_sp_page_dir;
15174 /* TQM ring 0 page directory. */
15175 uint64_t tqm_ring0_page_dir;
15176 /* TQM ring 1 page directory. */
15177 uint64_t tqm_ring1_page_dir;
15178 /* TQM ring 2 page directory. */
15179 uint64_t tqm_ring2_page_dir;
15180 /* TQM ring 3 page directory. */
15181 uint64_t tqm_ring3_page_dir;
15182 /* TQM ring 4 page directory. */
15183 uint64_t tqm_ring4_page_dir;
15184 /* TQM ring 5 page directory. */
15185 uint64_t tqm_ring5_page_dir;
15186 /* TQM ring 6 page directory. */
15187 uint64_t tqm_ring6_page_dir;
15188 /* TQM ring 7 page directory. */
15189 uint64_t tqm_ring7_page_dir;
15190 /* MR/AV page directory. */
15191 uint64_t mrav_page_dir;
15192 /* Timer page directory. */
15193 uint64_t tim_page_dir;
15194 /* Number of QPs. */
15195 uint32_t qp_num_entries;
15196 /* Number of SRQs. */
15197 uint32_t srq_num_entries;
15198 /* Number of CQs. */
15199 uint32_t cq_num_entries;
15200 /* Number of Stats. */
15201 uint32_t stat_num_entries;
15203 * Number of TQM slowpath entries.
15205 * TQM slowpath rings should be sized as follows:
15207 * num_entries = num_vnics + num_l2_tx_rings + 2 * num_roce_qps + tqm_min_size
15210 * num_vnics is the number of VNICs allocated in the VNIC backing store
15211 * num_l2_tx_rings is the number of L2 rings in the QP backing store
15212 * num_roce_qps is the number of RoCE QPs in the QP backing store
15213 * tqm_min_size is tqm_min_entries_per_ring reported by
15214 * HWRM_FUNC_BACKING_STORE_QCAPS
15216 * Note that TQM ring sizes cannot be extended while the system is
15217 * operational. If a PF driver needs to extend a TQM ring, it needs
15218 * to reset the function (e.g. HWRM_FUNC_RESET) and then reallocate
15219 * the backing store.
15221 uint32_t tqm_sp_num_entries;
15223 * Number of TQM ring 0 entries.
15225 * TQM fastpath rings should be sized large enough to accommodate the
15226 * maximum number of QPs (either L2 or RoCE, or both if shared)
15227 * that can be enqueued to the TQM ring.
15229 * Note that TQM ring sizes cannot be extended while the system is
15230 * operational. If a PF driver needs to extend a TQM ring, it needs
15231 * to reset the function (e.g. HWRM_FUNC_RESET) and then reallocate
15232 * the backing store.
15234 uint32_t tqm_ring0_num_entries;
15236 * Number of TQM ring 1 entries.
15238 * TQM fastpath rings should be sized large enough to accommodate the
15239 * maximum number of QPs (either L2 or RoCE, or both if shared)
15240 * that can be enqueued to the TQM ring.
15242 * Note that TQM ring sizes cannot be extended while the system is
15243 * operational. If a PF driver needs to extend a TQM ring, it needs
15244 * to reset the function (e.g. HWRM_FUNC_RESET) and then reallocate
15245 * the backing store.
15247 uint32_t tqm_ring1_num_entries;
15249 * Number of TQM ring 2 entries.
15251 * TQM fastpath rings should be sized large enough to accommodate the
15252 * maximum number of QPs (either L2 or RoCE, or both if shared)
15253 * that can be enqueued to the TQM ring.
15255 * Note that TQM ring sizes cannot be extended while the system is
15256 * operational. If a PF driver needs to extend a TQM ring, it needs
15257 * to reset the function (e.g. HWRM_FUNC_RESET) and then reallocate
15258 * the backing store.
15260 uint32_t tqm_ring2_num_entries;
15262 * Number of TQM ring 3 entries.
15264 * TQM fastpath rings should be sized large enough to accommodate the
15265 * maximum number of QPs (either L2 or RoCE, or both if shared)
15266 * that can be enqueued to the TQM ring.
15268 * Note that TQM ring sizes cannot be extended while the system is
15269 * operational. If a PF driver needs to extend a TQM ring, it needs
15270 * to reset the function (e.g. HWRM_FUNC_RESET) and then reallocate
15271 * the backing store.
15273 uint32_t tqm_ring3_num_entries;
15275 * Number of TQM ring 4 entries.
15277 * TQM fastpath rings should be sized large enough to accommodate the
15278 * maximum number of QPs (either L2 or RoCE, or both if shared)
15279 * that can be enqueued to the TQM ring.
15281 * Note that TQM ring sizes cannot be extended while the system is
15282 * operational. If a PF driver needs to extend a TQM ring, it needs
15283 * to reset the function (e.g. HWRM_FUNC_RESET) and then reallocate
15284 * the backing store.
15286 uint32_t tqm_ring4_num_entries;
15288 * Number of TQM ring 5 entries.
15290 * TQM fastpath rings should be sized large enough to accommodate the
15291 * maximum number of QPs (either L2 or RoCE, or both if shared)
15292 * that can be enqueued to the TQM ring.
15294 * Note that TQM ring sizes cannot be extended while the system is
15295 * operational. If a PF driver needs to extend a TQM ring, it needs
15296 * to reset the function (e.g. HWRM_FUNC_RESET) and then reallocate
15297 * the backing store.
15299 uint32_t tqm_ring5_num_entries;
15301 * Number of TQM ring 6 entries.
15303 * TQM fastpath rings should be sized large enough to accommodate the
15304 * maximum number of QPs (either L2 or RoCE, or both if shared)
15305 * that can be enqueued to the TQM ring.
15307 * Note that TQM ring sizes cannot be extended while the system is
15308 * operational. If a PF driver needs to extend a TQM ring, it needs
15309 * to reset the function (e.g. HWRM_FUNC_RESET) and then reallocate
15310 * the backing store.
15312 uint32_t tqm_ring6_num_entries;
15314 * Number of TQM ring 7 entries.
15316 * TQM fastpath rings should be sized large enough to accommodate the
15317 * maximum number of QPs (either L2 or RoCE, or both if shared)
15318 * that can be enqueued to the TQM ring.
15320 * Note that TQM ring sizes cannot be extended while the system is
15321 * operational. If a PF driver needs to extend a TQM ring, it needs
15322 * to reset the function (e.g. HWRM_FUNC_RESET) and then reallocate
15323 * the backing store.
15325 uint32_t tqm_ring7_num_entries;
15327 * If the MR/AV split reservation flag is not set, then this field
15328 * represents the total number of MR plus AV entries. For versions
15329 * of firmware that support the split reservation, when it is not
15330 * specified half of the entries will be reserved for MRs and the
15331 * other half for AVs.
15333 * If the MR/AV split reservation flag is set, then this
15334 * field is logically divided into two 16b fields. Bits `[31:16]`
15335 * represents the `mr_num_entries` and bits `[15:0]` represents
15336 * `av_num_entries`. The granularity of these values is defined by
15337 * the `mrav_num_entries_unit` field returned by the
15338 * `backing_store_qcaps` command.
15340 uint32_t mrav_num_entries;
15341 /* Number of Timer entries. */
15342 uint32_t tim_num_entries;
15343 /* Number of entries to reserve for QP1 */
15344 uint16_t qp_num_qp1_entries;
15345 /* Number of entries to reserve for L2 */
15346 uint16_t qp_num_l2_entries;
15347 /* Number of bytes that have been allocated for each context entry. */
15348 uint16_t qp_entry_size;
15349 /* Number of entries to reserve for L2 */
15350 uint16_t srq_num_l2_entries;
15351 /* Number of bytes that have been allocated for each context entry. */
15352 uint16_t srq_entry_size;
15353 /* Number of entries to reserve for L2 */
15354 uint16_t cq_num_l2_entries;
15355 /* Number of bytes that have been allocated for each context entry. */
15356 uint16_t cq_entry_size;
15357 /* Number of entries to reserve for VNIC entries */
15358 uint16_t vnic_num_vnic_entries;
15359 /* Number of entries to reserve for Ring table entries */
15360 uint16_t vnic_num_ring_table_entries;
15361 /* Number of bytes that have been allocated for each context entry. */
15362 uint16_t vnic_entry_size;
15363 /* Number of bytes that have been allocated for each context entry. */
15364 uint16_t stat_entry_size;
15365 /* Number of bytes that have been allocated for each context entry. */
15366 uint16_t tqm_entry_size;
15367 /* Number of bytes that have been allocated for each context entry. */
15368 uint16_t mrav_entry_size;
15369 /* Number of bytes that have been allocated for each context entry. */
15370 uint16_t tim_entry_size;
15371 /* TQM ring page size and level. */
15372 uint8_t tqm_ring8_pg_size_tqm_ring_lvl;
15373 /* TQM ring PBL indirect levels. */
15374 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_RING8_TQM_RING_LVL_MASK \
15376 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_RING8_TQM_RING_LVL_SFT \
15378 /* PBL pointer is physical start address. */
15379 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_RING8_TQM_RING_LVL_LVL_0 \
15381 /* PBL pointer points to PTE table. */
15382 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_RING8_TQM_RING_LVL_LVL_1 \
15385 * PBL pointer points to PDE table with each entry pointing to
15388 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_RING8_TQM_RING_LVL_LVL_2 \
15390 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_RING8_TQM_RING_LVL_LAST \
15391 HWRM_FUNC_BACKING_STORE_CFG_INPUT_RING8_TQM_RING_LVL_LVL_2
15392 /* TQM ring page size. */
15393 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_RING8_TQM_RING_PG_SIZE_MASK \
15395 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_RING8_TQM_RING_PG_SIZE_SFT \
15398 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_RING8_TQM_RING_PG_SIZE_PG_4K \
15399 (UINT32_C(0x0) << 4)
15401 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_RING8_TQM_RING_PG_SIZE_PG_8K \
15402 (UINT32_C(0x1) << 4)
15404 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_RING8_TQM_RING_PG_SIZE_PG_64K \
15405 (UINT32_C(0x2) << 4)
15407 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_RING8_TQM_RING_PG_SIZE_PG_2M \
15408 (UINT32_C(0x3) << 4)
15410 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_RING8_TQM_RING_PG_SIZE_PG_8M \
15411 (UINT32_C(0x4) << 4)
15413 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_RING8_TQM_RING_PG_SIZE_PG_1G \
15414 (UINT32_C(0x5) << 4)
15415 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_RING8_TQM_RING_PG_SIZE_LAST \
15416 HWRM_FUNC_BACKING_STORE_CFG_INPUT_RING8_TQM_RING_PG_SIZE_PG_1G
15417 uint8_t ring8_unused[3];
15418 /* Number of TQM ring entries. */
15419 uint32_t tqm_ring8_num_entries;
15420 /* TQM ring page directory. */
15421 uint64_t tqm_ring8_page_dir;
15422 /* TQM ring page size and level. */
15423 uint8_t tqm_ring9_pg_size_tqm_ring_lvl;
15424 /* TQM ring PBL indirect levels. */
15425 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_RING9_TQM_RING_LVL_MASK \
15427 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_RING9_TQM_RING_LVL_SFT \
15429 /* PBL pointer is physical start address. */
15430 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_RING9_TQM_RING_LVL_LVL_0 \
15432 /* PBL pointer points to PTE table. */
15433 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_RING9_TQM_RING_LVL_LVL_1 \
15436 * PBL pointer points to PDE table with each entry pointing to
15439 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_RING9_TQM_RING_LVL_LVL_2 \
15441 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_RING9_TQM_RING_LVL_LAST \
15442 HWRM_FUNC_BACKING_STORE_CFG_INPUT_RING9_TQM_RING_LVL_LVL_2
15443 /* TQM ring page size. */
15444 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_RING9_TQM_RING_PG_SIZE_MASK \
15446 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_RING9_TQM_RING_PG_SIZE_SFT \
15449 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_RING9_TQM_RING_PG_SIZE_PG_4K \
15450 (UINT32_C(0x0) << 4)
15452 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_RING9_TQM_RING_PG_SIZE_PG_8K \
15453 (UINT32_C(0x1) << 4)
15455 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_RING9_TQM_RING_PG_SIZE_PG_64K \
15456 (UINT32_C(0x2) << 4)
15458 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_RING9_TQM_RING_PG_SIZE_PG_2M \
15459 (UINT32_C(0x3) << 4)
15461 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_RING9_TQM_RING_PG_SIZE_PG_8M \
15462 (UINT32_C(0x4) << 4)
15464 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_RING9_TQM_RING_PG_SIZE_PG_1G \
15465 (UINT32_C(0x5) << 4)
15466 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_RING9_TQM_RING_PG_SIZE_LAST \
15467 HWRM_FUNC_BACKING_STORE_CFG_INPUT_RING9_TQM_RING_PG_SIZE_PG_1G
15468 uint8_t ring9_unused[3];
15469 /* Number of TQM ring entries. */
15470 uint32_t tqm_ring9_num_entries;
15471 /* TQM ring page directory. */
15472 uint64_t tqm_ring9_page_dir;
15473 /* TQM ring page size and level. */
15474 uint8_t tqm_ring10_pg_size_tqm_ring_lvl;
15475 /* TQM ring PBL indirect levels. */
15476 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_RING10_TQM_RING_LVL_MASK \
15478 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_RING10_TQM_RING_LVL_SFT \
15480 /* PBL pointer is physical start address. */
15481 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_RING10_TQM_RING_LVL_LVL_0 \
15483 /* PBL pointer points to PTE table. */
15484 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_RING10_TQM_RING_LVL_LVL_1 \
15487 * PBL pointer points to PDE table with each entry pointing to
15490 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_RING10_TQM_RING_LVL_LVL_2 \
15492 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_RING10_TQM_RING_LVL_LAST \
15493 HWRM_FUNC_BACKING_STORE_CFG_INPUT_RING10_TQM_RING_LVL_LVL_2
15494 /* TQM ring page size. */
15495 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_RING10_TQM_RING_PG_SIZE_MASK \
15497 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_RING10_TQM_RING_PG_SIZE_SFT \
15500 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_RING10_TQM_RING_PG_SIZE_PG_4K \
15501 (UINT32_C(0x0) << 4)
15503 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_RING10_TQM_RING_PG_SIZE_PG_8K \
15504 (UINT32_C(0x1) << 4)
15506 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_RING10_TQM_RING_PG_SIZE_PG_64K \
15507 (UINT32_C(0x2) << 4)
15509 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_RING10_TQM_RING_PG_SIZE_PG_2M \
15510 (UINT32_C(0x3) << 4)
15512 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_RING10_TQM_RING_PG_SIZE_PG_8M \
15513 (UINT32_C(0x4) << 4)
15515 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_RING10_TQM_RING_PG_SIZE_PG_1G \
15516 (UINT32_C(0x5) << 4)
15517 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_RING10_TQM_RING_PG_SIZE_LAST \
15518 HWRM_FUNC_BACKING_STORE_CFG_INPUT_RING10_TQM_RING_PG_SIZE_PG_1G
15519 uint8_t ring10_unused[3];
15520 /* Number of TQM ring entries. */
15521 uint32_t tqm_ring10_num_entries;
15522 /* TQM ring page directory. */
15523 uint64_t tqm_ring10_page_dir;
15526 /* hwrm_func_backing_store_cfg_output (size:128b/16B) */
15527 struct hwrm_func_backing_store_cfg_output {
15528 /* The specific error status for the command. */
15529 uint16_t error_code;
15530 /* The HWRM command request type. */
15532 /* The sequence ID from the original command. */
15534 /* The length of the response data in number of bytes. */
15536 uint8_t unused_0[7];
15538 * This field is used in Output records to indicate that the output
15539 * is completely written to RAM. This field should be read as '1'
15540 * to indicate that the output has been completely written.
15541 * When writing a command completion or response to an internal processor,
15542 * the order of writes has to be such that this field is written last.
15547 /********************************
15548 * hwrm_func_backing_store_qcfg *
15549 ********************************/
15552 /* hwrm_func_backing_store_qcfg_input (size:128b/16B) */
15553 struct hwrm_func_backing_store_qcfg_input {
15554 /* The HWRM command request type. */
15557 * The completion ring to send the completion event on. This should
15558 * be the NQ ID returned from the `nq_alloc` HWRM command.
15560 uint16_t cmpl_ring;
15562 * The sequence ID is used by the driver for tracking multiple
15563 * commands. This ID is treated as opaque data by the firmware and
15564 * the value is returned in the `hwrm_resp_hdr` upon completion.
15568 * The target ID of the command:
15569 * * 0x0-0xFFF8 - The function ID
15570 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
15571 * * 0xFFFD - Reserved for user-space HWRM interface
15574 uint16_t target_id;
15576 * A physical address pointer pointing to a host buffer that the
15577 * command's response data will be written. This can be either a host
15578 * physical address (HPA) or a guest physical address (GPA) and must
15579 * point to a physically contiguous block of memory.
15581 uint64_t resp_addr;
15584 /* hwrm_func_backing_store_qcfg_output (size:2304b/288B) */
15585 struct hwrm_func_backing_store_qcfg_output {
15586 /* The specific error status for the command. */
15587 uint16_t error_code;
15588 /* The HWRM command request type. */
15590 /* The sequence ID from the original command. */
15592 /* The length of the response data in number of bytes. */
15596 * When set, the firmware only uses on-chip resources and does not
15597 * expect any backing store to be provided by the host driver. This
15598 * mode provides minimal L2 functionality (e.g. limited L2 resources,
15601 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_FLAGS_PREBOOT_MODE \
15604 * When set, the 32b `mrav_num_entries` field is logically divided
15605 * into two 16b fields, `mr_num_entries` and `av_num_entries`.
15607 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_FLAGS_MRAV_RESERVATION_SPLIT \
15611 * This bit must be '1' for the qp fields to be
15614 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_ENABLES_QP \
15617 * This bit must be '1' for the srq fields to be
15620 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_ENABLES_SRQ \
15623 * This bit must be '1' for the cq fields to be
15626 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_ENABLES_CQ \
15629 * This bit must be '1' for the vnic fields to be
15632 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_ENABLES_VNIC \
15635 * This bit must be '1' for the stat fields to be
15638 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_ENABLES_STAT \
15641 * This bit must be '1' for the tqm_sp fields to be
15644 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_ENABLES_TQM_SP \
15647 * This bit must be '1' for the tqm_ring0 fields to be
15650 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_ENABLES_TQM_RING0 \
15653 * This bit must be '1' for the tqm_ring1 fields to be
15656 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_ENABLES_TQM_RING1 \
15659 * This bit must be '1' for the tqm_ring2 fields to be
15662 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_ENABLES_TQM_RING2 \
15665 * This bit must be '1' for the tqm_ring3 fields to be
15668 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_ENABLES_TQM_RING3 \
15671 * This bit must be '1' for the tqm_ring4 fields to be
15674 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_ENABLES_TQM_RING4 \
15677 * This bit must be '1' for the tqm_ring5 fields to be
15680 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_ENABLES_TQM_RING5 \
15683 * This bit must be '1' for the tqm_ring6 fields to be
15686 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_ENABLES_TQM_RING6 \
15689 * This bit must be '1' for the tqm_ring7 fields to be
15692 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_ENABLES_TQM_RING7 \
15695 * This bit must be '1' for the mrav fields to be
15698 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_ENABLES_MRAV \
15701 * This bit must be '1' for the tim fields to be
15704 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_ENABLES_TIM \
15707 * This bit must be '1' for the tqm_ring8 fields to be
15710 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_ENABLES_TQM_RING8 \
15713 * This bit must be '1' for the tqm_ring9 fields to be
15716 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_ENABLES_TQM_RING9 \
15719 * This bit must be '1' for the tqm_ring10 fields to be
15722 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_ENABLES_TQM_RING10 \
15724 /* QPC page size and level. */
15725 uint8_t qpc_pg_size_qpc_lvl;
15726 /* QPC PBL indirect levels. */
15727 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_QPC_LVL_MASK \
15729 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_QPC_LVL_SFT 0
15730 /* PBL pointer is physical start address. */
15731 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_QPC_LVL_LVL_0 \
15733 /* PBL pointer points to PTE table. */
15734 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_QPC_LVL_LVL_1 \
15736 /* PBL pointer points to PDE table with each entry pointing to PTE tables. */
15737 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_QPC_LVL_LVL_2 \
15739 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_QPC_LVL_LAST \
15740 HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_QPC_LVL_LVL_2
15741 /* QPC page size. */
15742 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_QPC_PG_SIZE_MASK \
15744 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_QPC_PG_SIZE_SFT 4
15746 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_QPC_PG_SIZE_PG_4K \
15747 (UINT32_C(0x0) << 4)
15749 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_QPC_PG_SIZE_PG_8K \
15750 (UINT32_C(0x1) << 4)
15752 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_QPC_PG_SIZE_PG_64K \
15753 (UINT32_C(0x2) << 4)
15755 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_QPC_PG_SIZE_PG_2M \
15756 (UINT32_C(0x3) << 4)
15758 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_QPC_PG_SIZE_PG_8M \
15759 (UINT32_C(0x4) << 4)
15761 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_QPC_PG_SIZE_PG_1G \
15762 (UINT32_C(0x5) << 4)
15763 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_QPC_PG_SIZE_LAST \
15764 HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_QPC_PG_SIZE_PG_1G
15765 /* SRQ page size and level. */
15766 uint8_t srq_pg_size_srq_lvl;
15767 /* SRQ PBL indirect levels. */
15768 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_SRQ_LVL_MASK \
15770 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_SRQ_LVL_SFT 0
15771 /* PBL pointer is physical start address. */
15772 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_SRQ_LVL_LVL_0 \
15774 /* PBL pointer points to PTE table. */
15775 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_SRQ_LVL_LVL_1 \
15777 /* PBL pointer points to PDE table with each entry pointing to PTE tables. */
15778 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_SRQ_LVL_LVL_2 \
15780 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_SRQ_LVL_LAST \
15781 HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_SRQ_LVL_LVL_2
15782 /* SRQ page size. */
15783 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_SRQ_PG_SIZE_MASK \
15785 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_SRQ_PG_SIZE_SFT 4
15787 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_SRQ_PG_SIZE_PG_4K \
15788 (UINT32_C(0x0) << 4)
15790 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_SRQ_PG_SIZE_PG_8K \
15791 (UINT32_C(0x1) << 4)
15793 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_SRQ_PG_SIZE_PG_64K \
15794 (UINT32_C(0x2) << 4)
15796 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_SRQ_PG_SIZE_PG_2M \
15797 (UINT32_C(0x3) << 4)
15799 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_SRQ_PG_SIZE_PG_8M \
15800 (UINT32_C(0x4) << 4)
15802 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_SRQ_PG_SIZE_PG_1G \
15803 (UINT32_C(0x5) << 4)
15804 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_SRQ_PG_SIZE_LAST \
15805 HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_SRQ_PG_SIZE_PG_1G
15806 /* CQ page size and level. */
15807 uint8_t cq_pg_size_cq_lvl;
15808 /* CQ PBL indirect levels. */
15809 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_CQ_LVL_MASK \
15811 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_CQ_LVL_SFT 0
15812 /* PBL pointer is physical start address. */
15813 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_CQ_LVL_LVL_0 \
15815 /* PBL pointer points to PTE table. */
15816 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_CQ_LVL_LVL_1 \
15818 /* PBL pointer points to PDE table with each entry pointing to PTE tables. */
15819 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_CQ_LVL_LVL_2 \
15821 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_CQ_LVL_LAST \
15822 HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_CQ_LVL_LVL_2
15823 /* CQ page size. */
15824 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_CQ_PG_SIZE_MASK \
15826 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_CQ_PG_SIZE_SFT 4
15828 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_CQ_PG_SIZE_PG_4K \
15829 (UINT32_C(0x0) << 4)
15831 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_CQ_PG_SIZE_PG_8K \
15832 (UINT32_C(0x1) << 4)
15834 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_CQ_PG_SIZE_PG_64K \
15835 (UINT32_C(0x2) << 4)
15837 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_CQ_PG_SIZE_PG_2M \
15838 (UINT32_C(0x3) << 4)
15840 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_CQ_PG_SIZE_PG_8M \
15841 (UINT32_C(0x4) << 4)
15843 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_CQ_PG_SIZE_PG_1G \
15844 (UINT32_C(0x5) << 4)
15845 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_CQ_PG_SIZE_LAST \
15846 HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_CQ_PG_SIZE_PG_1G
15847 /* VNIC page size and level. */
15848 uint8_t vnic_pg_size_vnic_lvl;
15849 /* VNIC PBL indirect levels. */
15850 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_VNIC_LVL_MASK \
15852 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_VNIC_LVL_SFT 0
15853 /* PBL pointer is physical start address. */
15854 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_VNIC_LVL_LVL_0 \
15856 /* PBL pointer points to PTE table. */
15857 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_VNIC_LVL_LVL_1 \
15859 /* PBL pointer points to PDE table with each entry pointing to PTE tables. */
15860 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_VNIC_LVL_LVL_2 \
15862 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_VNIC_LVL_LAST \
15863 HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_VNIC_LVL_LVL_2
15864 /* VNIC page size. */
15865 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_VNIC_PG_SIZE_MASK \
15867 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_VNIC_PG_SIZE_SFT 4
15869 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_VNIC_PG_SIZE_PG_4K \
15870 (UINT32_C(0x0) << 4)
15872 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_VNIC_PG_SIZE_PG_8K \
15873 (UINT32_C(0x1) << 4)
15875 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_VNIC_PG_SIZE_PG_64K \
15876 (UINT32_C(0x2) << 4)
15878 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_VNIC_PG_SIZE_PG_2M \
15879 (UINT32_C(0x3) << 4)
15881 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_VNIC_PG_SIZE_PG_8M \
15882 (UINT32_C(0x4) << 4)
15884 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_VNIC_PG_SIZE_PG_1G \
15885 (UINT32_C(0x5) << 4)
15886 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_VNIC_PG_SIZE_LAST \
15887 HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_VNIC_PG_SIZE_PG_1G
15888 /* Stat page size and level. */
15889 uint8_t stat_pg_size_stat_lvl;
15890 /* Stat PBL indirect levels. */
15891 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_STAT_LVL_MASK \
15893 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_STAT_LVL_SFT 0
15894 /* PBL pointer is physical start address. */
15895 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_STAT_LVL_LVL_0 \
15897 /* PBL pointer points to PTE table. */
15898 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_STAT_LVL_LVL_1 \
15900 /* PBL pointer points to PDE table with each entry pointing to PTE tables. */
15901 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_STAT_LVL_LVL_2 \
15903 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_STAT_LVL_LAST \
15904 HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_STAT_LVL_LVL_2
15905 /* Stat page size. */
15906 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_STAT_PG_SIZE_MASK \
15908 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_STAT_PG_SIZE_SFT 4
15910 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_STAT_PG_SIZE_PG_4K \
15911 (UINT32_C(0x0) << 4)
15913 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_STAT_PG_SIZE_PG_8K \
15914 (UINT32_C(0x1) << 4)
15916 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_STAT_PG_SIZE_PG_64K \
15917 (UINT32_C(0x2) << 4)
15919 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_STAT_PG_SIZE_PG_2M \
15920 (UINT32_C(0x3) << 4)
15922 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_STAT_PG_SIZE_PG_8M \
15923 (UINT32_C(0x4) << 4)
15925 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_STAT_PG_SIZE_PG_1G \
15926 (UINT32_C(0x5) << 4)
15927 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_STAT_PG_SIZE_LAST \
15928 HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_STAT_PG_SIZE_PG_1G
15929 /* TQM slow path page size and level. */
15930 uint8_t tqm_sp_pg_size_tqm_sp_lvl;
15931 /* TQM slow path PBL indirect levels. */
15932 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_SP_LVL_MASK \
15934 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_SP_LVL_SFT 0
15935 /* PBL pointer is physical start address. */
15936 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_SP_LVL_LVL_0 \
15938 /* PBL pointer points to PTE table. */
15939 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_SP_LVL_LVL_1 \
15941 /* PBL pointer points to PDE table with each entry pointing to PTE tables. */
15942 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_SP_LVL_LVL_2 \
15944 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_SP_LVL_LAST \
15945 HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_SP_LVL_LVL_2
15946 /* TQM slow path page size. */
15947 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_SP_PG_SIZE_MASK \
15949 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_SP_PG_SIZE_SFT 4
15951 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_SP_PG_SIZE_PG_4K \
15952 (UINT32_C(0x0) << 4)
15954 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_SP_PG_SIZE_PG_8K \
15955 (UINT32_C(0x1) << 4)
15957 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_SP_PG_SIZE_PG_64K \
15958 (UINT32_C(0x2) << 4)
15960 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_SP_PG_SIZE_PG_2M \
15961 (UINT32_C(0x3) << 4)
15963 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_SP_PG_SIZE_PG_8M \
15964 (UINT32_C(0x4) << 4)
15966 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_SP_PG_SIZE_PG_1G \
15967 (UINT32_C(0x5) << 4)
15968 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_SP_PG_SIZE_LAST \
15969 HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_SP_PG_SIZE_PG_1G
15970 /* TQM ring 0 page size and level. */
15971 uint8_t tqm_ring0_pg_size_tqm_ring0_lvl;
15972 /* TQM ring 0 PBL indirect levels. */
15973 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING0_LVL_MASK \
15975 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING0_LVL_SFT 0
15976 /* PBL pointer is physical start address. */
15977 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING0_LVL_LVL_0 \
15979 /* PBL pointer points to PTE table. */
15980 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING0_LVL_LVL_1 \
15982 /* PBL pointer points to PDE table with each entry pointing to PTE tables. */
15983 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING0_LVL_LVL_2 \
15985 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING0_LVL_LAST \
15986 HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING0_LVL_LVL_2
15987 /* TQM ring 0 page size. */
15988 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING0_PG_SIZE_MASK \
15990 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING0_PG_SIZE_SFT 4
15992 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING0_PG_SIZE_PG_4K \
15993 (UINT32_C(0x0) << 4)
15995 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING0_PG_SIZE_PG_8K \
15996 (UINT32_C(0x1) << 4)
15998 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING0_PG_SIZE_PG_64K \
15999 (UINT32_C(0x2) << 4)
16001 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING0_PG_SIZE_PG_2M \
16002 (UINT32_C(0x3) << 4)
16004 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING0_PG_SIZE_PG_8M \
16005 (UINT32_C(0x4) << 4)
16007 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING0_PG_SIZE_PG_1G \
16008 (UINT32_C(0x5) << 4)
16009 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING0_PG_SIZE_LAST \
16010 HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING0_PG_SIZE_PG_1G
16011 /* TQM ring 1 page size and level. */
16012 uint8_t tqm_ring1_pg_size_tqm_ring1_lvl;
16013 /* TQM ring 1 PBL indirect levels. */
16014 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING1_LVL_MASK \
16016 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING1_LVL_SFT 0
16017 /* PBL pointer is physical start address. */
16018 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING1_LVL_LVL_0 \
16020 /* PBL pointer points to PTE table. */
16021 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING1_LVL_LVL_1 \
16023 /* PBL pointer points to PDE table with each entry pointing to PTE tables. */
16024 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING1_LVL_LVL_2 \
16026 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING1_LVL_LAST \
16027 HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING1_LVL_LVL_2
16028 /* TQM ring 1 page size. */
16029 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING1_PG_SIZE_MASK \
16031 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING1_PG_SIZE_SFT 4
16033 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING1_PG_SIZE_PG_4K \
16034 (UINT32_C(0x0) << 4)
16036 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING1_PG_SIZE_PG_8K \
16037 (UINT32_C(0x1) << 4)
16039 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING1_PG_SIZE_PG_64K \
16040 (UINT32_C(0x2) << 4)
16042 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING1_PG_SIZE_PG_2M \
16043 (UINT32_C(0x3) << 4)
16045 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING1_PG_SIZE_PG_8M \
16046 (UINT32_C(0x4) << 4)
16048 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING1_PG_SIZE_PG_1G \
16049 (UINT32_C(0x5) << 4)
16050 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING1_PG_SIZE_LAST \
16051 HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING1_PG_SIZE_PG_1G
16052 /* TQM ring 2 page size and level. */
16053 uint8_t tqm_ring2_pg_size_tqm_ring2_lvl;
16054 /* TQM ring 2 PBL indirect levels. */
16055 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING2_LVL_MASK \
16057 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING2_LVL_SFT 0
16058 /* PBL pointer is physical start address. */
16059 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING2_LVL_LVL_0 \
16061 /* PBL pointer points to PTE table. */
16062 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING2_LVL_LVL_1 \
16064 /* PBL pointer points to PDE table with each entry pointing to PTE tables. */
16065 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING2_LVL_LVL_2 \
16067 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING2_LVL_LAST \
16068 HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING2_LVL_LVL_2
16069 /* TQM ring 2 page size. */
16070 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING2_PG_SIZE_MASK \
16072 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING2_PG_SIZE_SFT 4
16074 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING2_PG_SIZE_PG_4K \
16075 (UINT32_C(0x0) << 4)
16077 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING2_PG_SIZE_PG_8K \
16078 (UINT32_C(0x1) << 4)
16080 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING2_PG_SIZE_PG_64K \
16081 (UINT32_C(0x2) << 4)
16083 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING2_PG_SIZE_PG_2M \
16084 (UINT32_C(0x3) << 4)
16086 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING2_PG_SIZE_PG_8M \
16087 (UINT32_C(0x4) << 4)
16089 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING2_PG_SIZE_PG_1G \
16090 (UINT32_C(0x5) << 4)
16091 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING2_PG_SIZE_LAST \
16092 HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING2_PG_SIZE_PG_1G
16093 /* TQM ring 3 page size and level. */
16094 uint8_t tqm_ring3_pg_size_tqm_ring3_lvl;
16095 /* TQM ring 3 PBL indirect levels. */
16096 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING3_LVL_MASK \
16098 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING3_LVL_SFT 0
16099 /* PBL pointer is physical start address. */
16100 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING3_LVL_LVL_0 \
16102 /* PBL pointer points to PTE table. */
16103 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING3_LVL_LVL_1 \
16105 /* PBL pointer points to PDE table with each entry pointing to PTE tables. */
16106 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING3_LVL_LVL_2 \
16108 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING3_LVL_LAST \
16109 HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING3_LVL_LVL_2
16110 /* TQM ring 3 page size. */
16111 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING3_PG_SIZE_MASK \
16113 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING3_PG_SIZE_SFT 4
16115 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING3_PG_SIZE_PG_4K \
16116 (UINT32_C(0x0) << 4)
16118 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING3_PG_SIZE_PG_8K \
16119 (UINT32_C(0x1) << 4)
16121 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING3_PG_SIZE_PG_64K \
16122 (UINT32_C(0x2) << 4)
16124 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING3_PG_SIZE_PG_2M \
16125 (UINT32_C(0x3) << 4)
16127 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING3_PG_SIZE_PG_8M \
16128 (UINT32_C(0x4) << 4)
16130 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING3_PG_SIZE_PG_1G \
16131 (UINT32_C(0x5) << 4)
16132 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING3_PG_SIZE_LAST \
16133 HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING3_PG_SIZE_PG_1G
16134 /* TQM ring 4 page size and level. */
16135 uint8_t tqm_ring4_pg_size_tqm_ring4_lvl;
16136 /* TQM ring 4 PBL indirect levels. */
16137 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING4_LVL_MASK \
16139 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING4_LVL_SFT 0
16140 /* PBL pointer is physical start address. */
16141 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING4_LVL_LVL_0 \
16143 /* PBL pointer points to PTE table. */
16144 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING4_LVL_LVL_1 \
16146 /* PBL pointer points to PDE table with each entry pointing to PTE tables. */
16147 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING4_LVL_LVL_2 \
16149 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING4_LVL_LAST \
16150 HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING4_LVL_LVL_2
16151 /* TQM ring 4 page size. */
16152 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING4_PG_SIZE_MASK \
16154 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING4_PG_SIZE_SFT 4
16156 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING4_PG_SIZE_PG_4K \
16157 (UINT32_C(0x0) << 4)
16159 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING4_PG_SIZE_PG_8K \
16160 (UINT32_C(0x1) << 4)
16162 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING4_PG_SIZE_PG_64K \
16163 (UINT32_C(0x2) << 4)
16165 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING4_PG_SIZE_PG_2M \
16166 (UINT32_C(0x3) << 4)
16168 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING4_PG_SIZE_PG_8M \
16169 (UINT32_C(0x4) << 4)
16171 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING4_PG_SIZE_PG_1G \
16172 (UINT32_C(0x5) << 4)
16173 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING4_PG_SIZE_LAST \
16174 HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING4_PG_SIZE_PG_1G
16175 /* TQM ring 5 page size and level. */
16176 uint8_t tqm_ring5_pg_size_tqm_ring5_lvl;
16177 /* TQM ring 5 PBL indirect levels. */
16178 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING5_LVL_MASK \
16180 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING5_LVL_SFT 0
16181 /* PBL pointer is physical start address. */
16182 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING5_LVL_LVL_0 \
16184 /* PBL pointer points to PTE table. */
16185 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING5_LVL_LVL_1 \
16187 /* PBL pointer points to PDE table with each entry pointing to PTE tables. */
16188 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING5_LVL_LVL_2 \
16190 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING5_LVL_LAST \
16191 HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING5_LVL_LVL_2
16192 /* TQM ring 5 page size. */
16193 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING5_PG_SIZE_MASK \
16195 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING5_PG_SIZE_SFT 4
16197 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING5_PG_SIZE_PG_4K \
16198 (UINT32_C(0x0) << 4)
16200 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING5_PG_SIZE_PG_8K \
16201 (UINT32_C(0x1) << 4)
16203 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING5_PG_SIZE_PG_64K \
16204 (UINT32_C(0x2) << 4)
16206 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING5_PG_SIZE_PG_2M \
16207 (UINT32_C(0x3) << 4)
16209 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING5_PG_SIZE_PG_8M \
16210 (UINT32_C(0x4) << 4)
16212 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING5_PG_SIZE_PG_1G \
16213 (UINT32_C(0x5) << 4)
16214 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING5_PG_SIZE_LAST \
16215 HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING5_PG_SIZE_PG_1G
16216 /* TQM ring 6 page size and level. */
16217 uint8_t tqm_ring6_pg_size_tqm_ring6_lvl;
16218 /* TQM ring 6 PBL indirect levels. */
16219 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING6_LVL_MASK \
16221 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING6_LVL_SFT 0
16222 /* PBL pointer is physical start address. */
16223 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING6_LVL_LVL_0 \
16225 /* PBL pointer points to PTE table. */
16226 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING6_LVL_LVL_1 \
16228 /* PBL pointer points to PDE table with each entry pointing to PTE tables. */
16229 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING6_LVL_LVL_2 \
16231 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING6_LVL_LAST \
16232 HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING6_LVL_LVL_2
16233 /* TQM ring 6 page size. */
16234 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING6_PG_SIZE_MASK \
16236 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING6_PG_SIZE_SFT 4
16238 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING6_PG_SIZE_PG_4K \
16239 (UINT32_C(0x0) << 4)
16241 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING6_PG_SIZE_PG_8K \
16242 (UINT32_C(0x1) << 4)
16244 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING6_PG_SIZE_PG_64K \
16245 (UINT32_C(0x2) << 4)
16247 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING6_PG_SIZE_PG_2M \
16248 (UINT32_C(0x3) << 4)
16250 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING6_PG_SIZE_PG_8M \
16251 (UINT32_C(0x4) << 4)
16253 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING6_PG_SIZE_PG_1G \
16254 (UINT32_C(0x5) << 4)
16255 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING6_PG_SIZE_LAST \
16256 HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING6_PG_SIZE_PG_1G
16257 /* TQM ring 7 page size and level. */
16258 uint8_t tqm_ring7_pg_size_tqm_ring7_lvl;
16259 /* TQM ring 7 PBL indirect levels. */
16260 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING7_LVL_MASK \
16262 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING7_LVL_SFT 0
16263 /* PBL pointer is physical start address. */
16264 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING7_LVL_LVL_0 \
16266 /* PBL pointer points to PTE table. */
16267 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING7_LVL_LVL_1 \
16269 /* PBL pointer points to PDE table with each entry pointing to PTE tables. */
16270 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING7_LVL_LVL_2 \
16272 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING7_LVL_LAST \
16273 HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING7_LVL_LVL_2
16274 /* TQM ring 7 page size. */
16275 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING7_PG_SIZE_MASK \
16277 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING7_PG_SIZE_SFT 4
16279 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING7_PG_SIZE_PG_4K \
16280 (UINT32_C(0x0) << 4)
16282 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING7_PG_SIZE_PG_8K \
16283 (UINT32_C(0x1) << 4)
16285 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING7_PG_SIZE_PG_64K \
16286 (UINT32_C(0x2) << 4)
16288 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING7_PG_SIZE_PG_2M \
16289 (UINT32_C(0x3) << 4)
16291 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING7_PG_SIZE_PG_8M \
16292 (UINT32_C(0x4) << 4)
16294 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING7_PG_SIZE_PG_1G \
16295 (UINT32_C(0x5) << 4)
16296 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING7_PG_SIZE_LAST \
16297 HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING7_PG_SIZE_PG_1G
16298 /* MR/AV page size and level. */
16299 uint8_t mrav_pg_size_mrav_lvl;
16300 /* MR/AV PBL indirect levels. */
16301 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_MRAV_LVL_MASK \
16303 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_MRAV_LVL_SFT 0
16304 /* PBL pointer is physical start address. */
16305 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_MRAV_LVL_LVL_0 \
16307 /* PBL pointer points to PTE table. */
16308 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_MRAV_LVL_LVL_1 \
16310 /* PBL pointer points to PDE table with each entry pointing to PTE tables. */
16311 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_MRAV_LVL_LVL_2 \
16313 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_MRAV_LVL_LAST \
16314 HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_MRAV_LVL_LVL_2
16315 /* MR/AV page size. */
16316 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_MRAV_PG_SIZE_MASK \
16318 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_MRAV_PG_SIZE_SFT 4
16320 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_MRAV_PG_SIZE_PG_4K \
16321 (UINT32_C(0x0) << 4)
16323 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_MRAV_PG_SIZE_PG_8K \
16324 (UINT32_C(0x1) << 4)
16326 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_MRAV_PG_SIZE_PG_64K \
16327 (UINT32_C(0x2) << 4)
16329 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_MRAV_PG_SIZE_PG_2M \
16330 (UINT32_C(0x3) << 4)
16332 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_MRAV_PG_SIZE_PG_8M \
16333 (UINT32_C(0x4) << 4)
16335 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_MRAV_PG_SIZE_PG_1G \
16336 (UINT32_C(0x5) << 4)
16337 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_MRAV_PG_SIZE_LAST \
16338 HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_MRAV_PG_SIZE_PG_1G
16339 /* Timer page size and level. */
16340 uint8_t tim_pg_size_tim_lvl;
16341 /* Timer PBL indirect levels. */
16342 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TIM_LVL_MASK \
16344 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TIM_LVL_SFT 0
16345 /* PBL pointer is physical start address. */
16346 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TIM_LVL_LVL_0 \
16348 /* PBL pointer points to PTE table. */
16349 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TIM_LVL_LVL_1 \
16351 /* PBL pointer points to PDE table with each entry pointing to PTE tables. */
16352 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TIM_LVL_LVL_2 \
16354 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TIM_LVL_LAST \
16355 HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TIM_LVL_LVL_2
16356 /* Timer page size. */
16357 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TIM_PG_SIZE_MASK \
16359 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TIM_PG_SIZE_SFT 4
16361 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TIM_PG_SIZE_PG_4K \
16362 (UINT32_C(0x0) << 4)
16364 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TIM_PG_SIZE_PG_8K \
16365 (UINT32_C(0x1) << 4)
16367 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TIM_PG_SIZE_PG_64K \
16368 (UINT32_C(0x2) << 4)
16370 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TIM_PG_SIZE_PG_2M \
16371 (UINT32_C(0x3) << 4)
16373 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TIM_PG_SIZE_PG_8M \
16374 (UINT32_C(0x4) << 4)
16376 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TIM_PG_SIZE_PG_1G \
16377 (UINT32_C(0x5) << 4)
16378 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TIM_PG_SIZE_LAST \
16379 HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TIM_PG_SIZE_PG_1G
16380 /* QP page directory. */
16381 uint64_t qpc_page_dir;
16382 /* SRQ page directory. */
16383 uint64_t srq_page_dir;
16384 /* CQ page directory. */
16385 uint64_t cq_page_dir;
16386 /* VNIC page directory. */
16387 uint64_t vnic_page_dir;
16388 /* Stat page directory. */
16389 uint64_t stat_page_dir;
16390 /* TQM slowpath page directory. */
16391 uint64_t tqm_sp_page_dir;
16392 /* TQM ring 0 page directory. */
16393 uint64_t tqm_ring0_page_dir;
16394 /* TQM ring 1 page directory. */
16395 uint64_t tqm_ring1_page_dir;
16396 /* TQM ring 2 page directory. */
16397 uint64_t tqm_ring2_page_dir;
16398 /* TQM ring 3 page directory. */
16399 uint64_t tqm_ring3_page_dir;
16400 /* TQM ring 4 page directory. */
16401 uint64_t tqm_ring4_page_dir;
16402 /* TQM ring 5 page directory. */
16403 uint64_t tqm_ring5_page_dir;
16404 /* TQM ring 6 page directory. */
16405 uint64_t tqm_ring6_page_dir;
16406 /* TQM ring 7 page directory. */
16407 uint64_t tqm_ring7_page_dir;
16408 /* MR/AV page directory. */
16409 uint64_t mrav_page_dir;
16410 /* Timer page directory. */
16411 uint64_t tim_page_dir;
16412 /* Number of entries to reserve for QP1 */
16413 uint16_t qp_num_qp1_entries;
16414 /* Number of entries to reserve for L2 */
16415 uint16_t qp_num_l2_entries;
16416 /* Number of QPs. */
16417 uint32_t qp_num_entries;
16418 /* Number of SRQs. */
16419 uint32_t srq_num_entries;
16420 /* Number of entries to reserve for L2 */
16421 uint16_t srq_num_l2_entries;
16422 /* Number of entries to reserve for L2 */
16423 uint16_t cq_num_l2_entries;
16424 /* Number of CQs. */
16425 uint32_t cq_num_entries;
16426 /* Number of entries to reserve for VNIC entries */
16427 uint16_t vnic_num_vnic_entries;
16428 /* Number of entries to reserve for Ring table entries */
16429 uint16_t vnic_num_ring_table_entries;
16430 /* Number of Stats. */
16431 uint32_t stat_num_entries;
16432 /* Number of TQM slowpath entries. */
16433 uint32_t tqm_sp_num_entries;
16434 /* Number of TQM ring 0 entries. */
16435 uint32_t tqm_ring0_num_entries;
16436 /* Number of TQM ring 1 entries. */
16437 uint32_t tqm_ring1_num_entries;
16438 /* Number of TQM ring 2 entries. */
16439 uint32_t tqm_ring2_num_entries;
16440 /* Number of TQM ring 3 entries. */
16441 uint32_t tqm_ring3_num_entries;
16442 /* Number of TQM ring 4 entries. */
16443 uint32_t tqm_ring4_num_entries;
16444 /* Number of TQM ring 5 entries. */
16445 uint32_t tqm_ring5_num_entries;
16446 /* Number of TQM ring 6 entries. */
16447 uint32_t tqm_ring6_num_entries;
16448 /* Number of TQM ring 7 entries. */
16449 uint32_t tqm_ring7_num_entries;
16451 * If the MR/AV split reservation flag is not set, then this field
16452 * represents the total number of MR plus AV entries. For versions
16453 * of firmware that support the split reservation, when it is not
16454 * specified half of the entries will be reserved for MRs and the
16455 * other half for AVs.
16457 * If the MR/AV split reservation flag is set, then this
16458 * field is logically divided into two 16b fields. Bits `[31:16]`
16459 * represents the `mr_num_entries` and bits `[15:0]` represents
16460 * `av_num_entries`. The granularity of these values is defined by
16461 * the `mrav_num_entries_unit` field returned by the
16462 * `backing_store_qcaps` command.
16464 uint32_t mrav_num_entries;
16465 /* Number of Timer entries. */
16466 uint32_t tim_num_entries;
16467 /* TQM ring page size and level. */
16468 uint8_t tqm_ring8_pg_size_tqm_ring_lvl;
16469 /* TQM ring PBL indirect levels. */
16470 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_RING8_TQM_RING_LVL_MASK \
16472 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_RING8_TQM_RING_LVL_SFT \
16474 /* PBL pointer is physical start address. */
16475 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_RING8_TQM_RING_LVL_LVL_0 \
16477 /* PBL pointer points to PTE table. */
16478 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_RING8_TQM_RING_LVL_LVL_1 \
16481 * PBL pointer points to PDE table with each entry pointing to
16484 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_RING8_TQM_RING_LVL_LVL_2 \
16486 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_RING8_TQM_RING_LVL_LAST \
16487 HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_RING8_TQM_RING_LVL_LVL_2
16488 /* TQM ring page size. */
16489 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_RING8_TQM_RING_PG_SIZE_MASK \
16491 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_RING8_TQM_RING_PG_SIZE_SFT \
16494 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_RING8_TQM_RING_PG_SIZE_PG_4K \
16495 (UINT32_C(0x0) << 4)
16497 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_RING8_TQM_RING_PG_SIZE_PG_8K \
16498 (UINT32_C(0x1) << 4)
16500 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_RING8_TQM_RING_PG_SIZE_PG_64K \
16501 (UINT32_C(0x2) << 4)
16503 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_RING8_TQM_RING_PG_SIZE_PG_2M \
16504 (UINT32_C(0x3) << 4)
16506 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_RING8_TQM_RING_PG_SIZE_PG_8M \
16507 (UINT32_C(0x4) << 4)
16509 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_RING8_TQM_RING_PG_SIZE_PG_1G \
16510 (UINT32_C(0x5) << 4)
16511 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_RING8_TQM_RING_PG_SIZE_LAST \
16512 HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_RING8_TQM_RING_PG_SIZE_PG_1G
16513 uint8_t ring8_unused[3];
16514 /* Number of TQM ring entries. */
16515 uint32_t tqm_ring8_num_entries;
16516 /* TQM ring page directory. */
16517 uint64_t tqm_ring8_page_dir;
16518 /* TQM ring page size and level. */
16519 uint8_t tqm_ring9_pg_size_tqm_ring_lvl;
16520 /* TQM ring PBL indirect levels. */
16521 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_RING9_TQM_RING_LVL_MASK \
16523 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_RING9_TQM_RING_LVL_SFT \
16525 /* PBL pointer is physical start address. */
16526 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_RING9_TQM_RING_LVL_LVL_0 \
16528 /* PBL pointer points to PTE table. */
16529 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_RING9_TQM_RING_LVL_LVL_1 \
16532 * PBL pointer points to PDE table with each entry pointing to
16535 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_RING9_TQM_RING_LVL_LVL_2 \
16537 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_RING9_TQM_RING_LVL_LAST \
16538 HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_RING9_TQM_RING_LVL_LVL_2
16539 /* TQM ring page size. */
16540 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_RING9_TQM_RING_PG_SIZE_MASK \
16542 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_RING9_TQM_RING_PG_SIZE_SFT \
16545 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_RING9_TQM_RING_PG_SIZE_PG_4K \
16546 (UINT32_C(0x0) << 4)
16548 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_RING9_TQM_RING_PG_SIZE_PG_8K \
16549 (UINT32_C(0x1) << 4)
16551 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_RING9_TQM_RING_PG_SIZE_PG_64K \
16552 (UINT32_C(0x2) << 4)
16554 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_RING9_TQM_RING_PG_SIZE_PG_2M \
16555 (UINT32_C(0x3) << 4)
16557 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_RING9_TQM_RING_PG_SIZE_PG_8M \
16558 (UINT32_C(0x4) << 4)
16560 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_RING9_TQM_RING_PG_SIZE_PG_1G \
16561 (UINT32_C(0x5) << 4)
16562 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_RING9_TQM_RING_PG_SIZE_LAST \
16563 HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_RING9_TQM_RING_PG_SIZE_PG_1G
16564 uint8_t ring9_unused[3];
16565 /* Number of TQM ring entries. */
16566 uint32_t tqm_ring9_num_entries;
16567 /* TQM ring page directory. */
16568 uint64_t tqm_ring9_page_dir;
16569 /* TQM ring page size and level. */
16570 uint8_t tqm_ring10_pg_size_tqm_ring_lvl;
16571 /* TQM ring PBL indirect levels. */
16572 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_RING10_TQM_RING_LVL_MASK \
16574 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_RING10_TQM_RING_LVL_SFT \
16576 /* PBL pointer is physical start address. */
16577 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_RING10_TQM_RING_LVL_LVL_0 \
16579 /* PBL pointer points to PTE table. */
16580 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_RING10_TQM_RING_LVL_LVL_1 \
16583 * PBL pointer points to PDE table with each entry pointing to
16586 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_RING10_TQM_RING_LVL_LVL_2 \
16588 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_RING10_TQM_RING_LVL_LAST \
16589 HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_RING10_TQM_RING_LVL_LVL_2
16590 /* TQM ring page size. */
16591 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_RING10_TQM_RING_PG_SIZE_MASK \
16593 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_RING10_TQM_RING_PG_SIZE_SFT \
16596 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_RING10_TQM_RING_PG_SIZE_PG_4K \
16597 (UINT32_C(0x0) << 4)
16599 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_RING10_TQM_RING_PG_SIZE_PG_8K \
16600 (UINT32_C(0x1) << 4)
16602 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_RING10_TQM_RING_PG_SIZE_PG_64K \
16603 (UINT32_C(0x2) << 4)
16605 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_RING10_TQM_RING_PG_SIZE_PG_2M \
16606 (UINT32_C(0x3) << 4)
16608 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_RING10_TQM_RING_PG_SIZE_PG_8M \
16609 (UINT32_C(0x4) << 4)
16611 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_RING10_TQM_RING_PG_SIZE_PG_1G \
16612 (UINT32_C(0x5) << 4)
16613 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_RING10_TQM_RING_PG_SIZE_LAST \
16614 HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_RING10_TQM_RING_PG_SIZE_PG_1G
16615 uint8_t ring10_unused[3];
16616 /* Number of TQM ring entries. */
16617 uint32_t tqm_ring10_num_entries;
16618 /* TQM ring page directory. */
16619 uint64_t tqm_ring10_page_dir;
16620 uint8_t unused_1[7];
16622 * This field is used in Output records to indicate that the output
16623 * is completely written to RAM. This field should be read as 1
16624 * to indicate that the output has been completely written.
16625 * When writing a command completion or response to an internal
16626 * processor, the order of writes has to be such that this field
16632 /****************************
16633 * hwrm_error_recovery_qcfg *
16634 ****************************/
16637 /* hwrm_error_recovery_qcfg_input (size:192b/24B) */
16638 struct hwrm_error_recovery_qcfg_input {
16639 /* The HWRM command request type. */
16642 * The completion ring to send the completion event on. This should
16643 * be the NQ ID returned from the `nq_alloc` HWRM command.
16645 uint16_t cmpl_ring;
16647 * The sequence ID is used by the driver for tracking multiple
16648 * commands. This ID is treated as opaque data by the firmware and
16649 * the value is returned in the `hwrm_resp_hdr` upon completion.
16653 * The target ID of the command:
16654 * * 0x0-0xFFF8 - The function ID
16655 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
16656 * * 0xFFFD - Reserved for user-space HWRM interface
16659 uint16_t target_id;
16661 * A physical address pointer pointing to a host buffer that the
16662 * command's response data will be written. This can be either a host
16663 * physical address (HPA) or a guest physical address (GPA) and must
16664 * point to a physically contiguous block of memory.
16666 uint64_t resp_addr;
16667 uint8_t unused_0[8];
16670 /* hwrm_error_recovery_qcfg_output (size:1664b/208B) */
16671 struct hwrm_error_recovery_qcfg_output {
16672 /* The specific error status for the command. */
16673 uint16_t error_code;
16674 /* The HWRM command request type. */
16676 /* The sequence ID from the original command. */
16678 /* The length of the response data in number of bytes. */
16682 * When this flag is set to 1, error recovery will be initiated
16683 * through master function driver.
16685 #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FLAGS_HOST UINT32_C(0x1)
16687 * When this flag is set to 1, error recovery will be performed
16688 * through Co processor.
16690 #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FLAGS_CO_CPU UINT32_C(0x2)
16692 * Driver Polling frequency. This value is in units of 100msec.
16693 * Typical value would be 10 to indicate 1sec.
16694 * Drivers can poll FW health status, Heartbeat, reset_counter with
16697 uint32_t driver_polling_freq;
16699 * This value is in units of 100msec.
16700 * Typical value would be 30 to indicate 3sec.
16701 * Master function wait period from detecting a fatal error to
16702 * initiating reset. In this time period Master PF expects every
16703 * active driver will detect fatal error.
16705 uint32_t master_func_wait_period;
16707 * This value is in units of 100msec.
16708 * Typical value would be 50 to indicate 5sec.
16709 * Normal function wait period from fatal error detection to
16710 * polling FW health status. In this time period, drivers should not
16711 * do any PCIe MMIO transaction and should not send any HWRM commands.
16713 uint32_t normal_func_wait_period;
16715 * This value is in units of 100msec.
16716 * Typical value would be 20 to indicate 2sec.
16717 * This field indicates that, master function wait period after chip
16718 * reset. After this time, master function should reinitialize with
16721 uint32_t master_func_wait_period_after_reset;
16723 * This value is in units of 100msec.
16724 * Typical value would be 60 to indicate 6sec.
16725 * This field is applicable to both master and normal functions.
16726 * Even after chip reset, if FW status not changed to ready,
16727 * then all the functions can poll for this much time and bailout.
16729 uint32_t max_bailout_time_after_reset;
16731 * FW health status register.
16732 * Lower 2 bits indicates address space location and upper 30 bits
16733 * indicates upper 30bits of the register address.
16734 * A value of 0xFFFF-FFFF indicates this register does not exist.
16736 uint32_t fw_health_status_reg;
16737 /* Lower 2 bits indicates address space location. */
16738 #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FW_HEALTH_STATUS_REG_ADDR_SPACE_MASK \
16740 #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FW_HEALTH_STATUS_REG_ADDR_SPACE_SFT \
16743 * If value is 0, this register is located in PCIe config space.
16744 * Drivers have to map appropriate window to access this
16747 #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FW_HEALTH_STATUS_REG_ADDR_SPACE_PCIE_CFG \
16750 * If value is 1, this register is located in GRC address space.
16751 * Drivers have to map appropriate window to access this
16754 #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FW_HEALTH_STATUS_REG_ADDR_SPACE_GRC \
16757 * If value is 2, this register is located in first BAR address
16758 * space. Drivers have to map appropriate window to access this
16761 #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FW_HEALTH_STATUS_REG_ADDR_SPACE_BAR0 \
16764 * If value is 3, this register is located in second BAR address
16765 * space. Drivers have to map appropriate window to access this
16766 * Drivers have to map appropriate window to access this
16769 #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FW_HEALTH_STATUS_REG_ADDR_SPACE_BAR1 \
16771 #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FW_HEALTH_STATUS_REG_ADDR_SPACE_LAST \
16772 HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FW_HEALTH_STATUS_REG_ADDR_SPACE_BAR1
16773 /* Upper 30bits of the register address. */
16774 #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FW_HEALTH_STATUS_REG_ADDR_MASK \
16775 UINT32_C(0xfffffffc)
16776 #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FW_HEALTH_STATUS_REG_ADDR_SFT \
16779 * FW HeartBeat register.
16780 * Lower 2 bits indicates address space location and upper 30 bits
16781 * indicates actual address.
16782 * A value of 0xFFFF-FFFF indicates this register does not exist.
16784 uint32_t fw_heartbeat_reg;
16785 /* Lower 2 bits indicates address space location. */
16786 #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FW_HEARTBEAT_REG_ADDR_SPACE_MASK \
16788 #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FW_HEARTBEAT_REG_ADDR_SPACE_SFT \
16791 * If value is 0, this register is located in PCIe config space.
16792 * Drivers have to map appropriate window to access this
16795 #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FW_HEARTBEAT_REG_ADDR_SPACE_PCIE_CFG \
16798 * If value is 1, this register is located in GRC address space.
16799 * Drivers have to map appropriate window to access this
16802 #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FW_HEARTBEAT_REG_ADDR_SPACE_GRC \
16805 * If value is 2, this register is located in first BAR address
16806 * space. Drivers have to map appropriate window to access this
16809 #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FW_HEARTBEAT_REG_ADDR_SPACE_BAR0 \
16812 * If value is 3, this register is located in second BAR address
16813 * space. Drivers have to map appropriate window to access this
16816 #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FW_HEARTBEAT_REG_ADDR_SPACE_BAR1 \
16818 #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FW_HEARTBEAT_REG_ADDR_SPACE_LAST \
16819 HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FW_HEARTBEAT_REG_ADDR_SPACE_BAR1
16820 /* Upper 30bits of the register address. */
16821 #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FW_HEARTBEAT_REG_ADDR_MASK \
16822 UINT32_C(0xfffffffc)
16823 #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FW_HEARTBEAT_REG_ADDR_SFT \
16826 * FW reset counter.
16827 * Lower 2 bits indicates address space location and upper 30 bits
16828 * indicates actual address.
16829 * A value of 0xFFFF-FFFF indicates this register does not exist.
16831 uint32_t fw_reset_cnt_reg;
16832 /* Lower 2 bits indicates address space location. */
16833 #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FW_RESET_CNT_REG_ADDR_SPACE_MASK \
16835 #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FW_RESET_CNT_REG_ADDR_SPACE_SFT \
16838 * If value is 0, this register is located in PCIe config space.
16839 * Drivers have to map appropriate window to access this
16842 #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FW_RESET_CNT_REG_ADDR_SPACE_PCIE_CFG \
16845 * If value is 1, this register is located in GRC address space.
16846 * Drivers have to map appropriate window to access this
16849 #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FW_RESET_CNT_REG_ADDR_SPACE_GRC \
16852 * If value is 2, this register is located in first BAR address
16853 * space. Drivers have to map appropriate window to access this
16856 #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FW_RESET_CNT_REG_ADDR_SPACE_BAR0 \
16859 * If value is 3, this register is located in second BAR address
16860 * space. Drivers have to map appropriate window to access this
16863 #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FW_RESET_CNT_REG_ADDR_SPACE_BAR1 \
16865 #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FW_RESET_CNT_REG_ADDR_SPACE_LAST \
16866 HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FW_RESET_CNT_REG_ADDR_SPACE_BAR1
16867 /* Upper 30bits of the register address. */
16868 #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FW_RESET_CNT_REG_ADDR_MASK \
16869 UINT32_C(0xfffffffc)
16870 #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FW_RESET_CNT_REG_ADDR_SFT \
16873 * Reset Inprogress Register address for PFs.
16874 * Lower 2 bits indicates address space location and upper 30 bits
16875 * indicates actual address.
16876 * A value of 0xFFFF-FFFF indicates this register does not exist.
16878 uint32_t reset_inprogress_reg;
16879 /* Lower 2 bits indicates address space location. */
16880 #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_RESET_INPROGRESS_REG_ADDR_SPACE_MASK \
16882 #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_RESET_INPROGRESS_REG_ADDR_SPACE_SFT \
16885 * If value is 0, this register is located in PCIe config space.
16886 * Drivers have to map appropriate window to access this
16889 #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_RESET_INPROGRESS_REG_ADDR_SPACE_PCIE_CFG \
16892 * If value is 1, this register is located in GRC address space.
16893 * Drivers have to map appropriate window to access this
16896 #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_RESET_INPROGRESS_REG_ADDR_SPACE_GRC \
16899 * If value is 2, this register is located in first BAR address
16900 * space. Drivers have to map appropriate window to access this
16903 #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_RESET_INPROGRESS_REG_ADDR_SPACE_BAR0 \
16906 * If value is 3, this register is located in second BAR address
16907 * space. Drivers have to map appropriate window to access this
16910 #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_RESET_INPROGRESS_REG_ADDR_SPACE_BAR1 \
16912 #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_RESET_INPROGRESS_REG_ADDR_SPACE_LAST \
16913 HWRM_ERROR_RECOVERY_QCFG_OUTPUT_RESET_INPROGRESS_REG_ADDR_SPACE_BAR1
16914 /* Upper 30bits of the register address. */
16915 #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_RESET_INPROGRESS_REG_ADDR_MASK \
16916 UINT32_C(0xfffffffc)
16917 #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_RESET_INPROGRESS_REG_ADDR_SFT \
16919 /* This field indicates the mask value for reset_inprogress_reg. */
16920 uint32_t reset_inprogress_reg_mask;
16921 uint8_t unused_0[3];
16923 * Array of registers and value count to reset the Chip
16924 * Each array count has reset_reg, reset_reg_val, delay_after_reset
16925 * in TLV format. Depending upon Chip type, number of reset registers
16926 * will vary. Drivers have to write reset_reg_val in the reset_reg
16927 * location in the same sequence in order to recover from a fatal
16930 uint8_t reg_array_cnt;
16933 * Lower 2 bits indicates address space location and upper 30 bits
16934 * indicates actual address.
16935 * A value of 0xFFFF-FFFF indicates this register does not exist.
16937 uint32_t reset_reg[16];
16938 /* Lower 2 bits indicates address space location. */
16939 #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_RESET_REG_ADDR_SPACE_MASK \
16941 #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_RESET_REG_ADDR_SPACE_SFT 0
16943 * If value is 0, this register is located in PCIe config space.
16944 * Drivers have to map appropriate window to access this
16947 #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_RESET_REG_ADDR_SPACE_PCIE_CFG \
16950 * If value is 1, this register is located in GRC address space.
16951 * Drivers have to map appropriate window to access this
16954 #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_RESET_REG_ADDR_SPACE_GRC \
16957 * If value is 2, this register is located in first BAR address
16958 * space. Drivers have to map appropriate window to access this
16961 #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_RESET_REG_ADDR_SPACE_BAR0 \
16964 * If value is 3, this register is located in second BAR address
16965 * space. Drivers have to map appropriate window to access this
16968 #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_RESET_REG_ADDR_SPACE_BAR1 \
16970 #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_RESET_REG_ADDR_SPACE_LAST \
16971 HWRM_ERROR_RECOVERY_QCFG_OUTPUT_RESET_REG_ADDR_SPACE_BAR1
16972 /* Upper 30bits of the register address. */
16973 #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_RESET_REG_ADDR_MASK \
16974 UINT32_C(0xfffffffc)
16975 #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_RESET_REG_ADDR_SFT 2
16976 /* Value to be written in reset_reg to reset the controller. */
16977 uint32_t reset_reg_val[16];
16979 * This value is in units of 1msec.
16980 * Typical value would be 10 to indicate 10msec.
16981 * Some of the operations like Core reset require delay before
16982 * accessing PCIE MMIO register space.
16983 * If this value is non-zero, drivers have to wait for
16984 * this much time after writing reset_reg_val in reset_reg.
16986 uint8_t delay_after_reset[16];
16988 * Error recovery counter.
16989 * Lower 2 bits indicates address space location and upper 30 bits
16990 * indicates actual address.
16991 * A value of 0xFFFF-FFFF indicates this register does not exist.
16993 uint32_t err_recovery_cnt_reg;
16994 /* Lower 2 bits indicates address space location. */
16995 #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_ERR_RECOVERY_CNT_REG_ADDR_SPACE_MASK \
16997 #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_ERR_RECOVERY_CNT_REG_ADDR_SPACE_SFT \
17000 * If value is 0, this register is located in PCIe config space.
17001 * Drivers have to map appropriate window to access this
17004 #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_ERR_RECOVERY_CNT_REG_ADDR_SPACE_PCIE_CFG \
17007 * If value is 1, this register is located in GRC address space.
17008 * Drivers have to map appropriate window to access this
17011 #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_ERR_RECOVERY_CNT_REG_ADDR_SPACE_GRC \
17014 * If value is 2, this register is located in first BAR address
17015 * space. Drivers have to map appropriate window to access this
17018 #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_ERR_RECOVERY_CNT_REG_ADDR_SPACE_BAR0 \
17021 * If value is 3, this register is located in second BAR address
17022 * space. Drivers have to map appropriate window to access this
17025 #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_ERR_RECOVERY_CNT_REG_ADDR_SPACE_BAR1 \
17027 #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_ERR_RECOVERY_CNT_REG_ADDR_SPACE_LAST \
17028 HWRM_ERROR_RECOVERY_QCFG_OUTPUT_ERR_RECOVERY_CNT_REG_ADDR_SPACE_BAR1
17029 /* Upper 30bits of the register address. */
17030 #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_ERR_RECOVERY_CNT_REG_ADDR_MASK \
17031 UINT32_C(0xfffffffc)
17032 #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_ERR_RECOVERY_CNT_REG_ADDR_SFT \
17034 uint8_t unused_1[3];
17036 * This field is used in Output records to indicate that the output
17037 * is completely written to RAM. This field should be read as '1'
17038 * to indicate that the output has been completely written.
17039 * When writing a command completion or response to an internal
17040 * processor, the order of writes has to be such that this field
17046 /***************************
17047 * hwrm_func_echo_response *
17048 ****************************/
17051 /* hwrm_func_echo_response_input (size:192b/24B) */
17052 struct hwrm_func_echo_response_input {
17053 /* The HWRM command request type. */
17056 * The completion ring to send the completion event on. This should
17057 * be the NQ ID returned from the `nq_alloc` HWRM command.
17059 uint16_t cmpl_ring;
17061 * The sequence ID is used by the driver for tracking multiple
17062 * commands. This ID is treated as opaque data by the firmware and
17063 * the value is returned in the `hwrm_resp_hdr` upon completion.
17067 * The target ID of the command:
17068 * 0x0-0xFFF8 - The function ID
17069 * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
17070 * 0xFFFD - Reserved for user-space HWRM interface
17073 uint16_t target_id;
17075 * A physical address pointer pointing to a host buffer that the
17076 * command's response data will be written. This can be either a host
17077 * physical address (HPA) or a guest physical address (GPA) and must
17078 * point to a physically contiguous block of memory.
17080 uint64_t resp_addr;
17081 uint32_t event_data1;
17082 uint32_t event_data2;
17085 /* hwrm_func_echo_response_output (size:128b/16B) */
17086 struct hwrm_func_echo_response_output {
17087 /* The specific error status for the command. */
17088 uint16_t error_code;
17089 /* The HWRM command request type. */
17091 /* The sequence ID from the original command. */
17093 /* The length of the response data in number of bytes. */
17095 uint8_t unused_0[7];
17097 * This field is used in Output records to indicate that the output
17098 * is completely written to RAM. This field should be read as '1'
17099 * to indicate that the output has been completely written.
17100 * When writing a command completion or response to an internal processor,
17101 * the order of writes has to be such that this field is written last.
17106 /***********************
17107 * hwrm_func_vlan_qcfg *
17108 ***********************/
17111 /* hwrm_func_vlan_qcfg_input (size:192b/24B) */
17112 struct hwrm_func_vlan_qcfg_input {
17113 /* The HWRM command request type. */
17116 * The completion ring to send the completion event on. This should
17117 * be the NQ ID returned from the `nq_alloc` HWRM command.
17119 uint16_t cmpl_ring;
17121 * The sequence ID is used by the driver for tracking multiple
17122 * commands. This ID is treated as opaque data by the firmware and
17123 * the value is returned in the `hwrm_resp_hdr` upon completion.
17127 * The target ID of the command:
17128 * * 0x0-0xFFF8 - The function ID
17129 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
17130 * * 0xFFFD - Reserved for user-space HWRM interface
17133 uint16_t target_id;
17135 * A physical address pointer pointing to a host buffer that the
17136 * command's response data will be written. This can be either a host
17137 * physical address (HPA) or a guest physical address (GPA) and must
17138 * point to a physically contiguous block of memory.
17140 uint64_t resp_addr;
17142 * Function ID of the function that is being
17144 * If set to 0xFF... (All Fs), then the configuration is
17145 * for the requesting function.
17148 uint8_t unused_0[6];
17151 /* hwrm_func_vlan_qcfg_output (size:320b/40B) */
17152 struct hwrm_func_vlan_qcfg_output {
17153 /* The specific error status for the command. */
17154 uint16_t error_code;
17155 /* The HWRM command request type. */
17157 /* The sequence ID from the original command. */
17159 /* The length of the response data in number of bytes. */
17162 /* S-TAG VLAN identifier configured for the function. */
17164 /* S-TAG PCP value configured for the function. */
17168 * S-TAG TPID value configured for the function. This field is specified in
17169 * network byte order.
17171 uint16_t stag_tpid;
17172 /* C-TAG VLAN identifier configured for the function. */
17174 /* C-TAG PCP value configured for the function. */
17178 * C-TAG TPID value configured for the function. This field is specified in
17179 * network byte order.
17181 uint16_t ctag_tpid;
17186 uint8_t unused_3[3];
17188 * This field is used in Output records to indicate that the output
17189 * is completely written to RAM. This field should be read as '1'
17190 * to indicate that the output has been completely written.
17191 * When writing a command completion or response to an internal processor,
17192 * the order of writes has to be such that this field is written last.
17197 /**********************
17198 * hwrm_func_vlan_cfg *
17199 **********************/
17202 /* hwrm_func_vlan_cfg_input (size:384b/48B) */
17203 struct hwrm_func_vlan_cfg_input {
17204 /* The HWRM command request type. */
17207 * The completion ring to send the completion event on. This should
17208 * be the NQ ID returned from the `nq_alloc` HWRM command.
17210 uint16_t cmpl_ring;
17212 * The sequence ID is used by the driver for tracking multiple
17213 * commands. This ID is treated as opaque data by the firmware and
17214 * the value is returned in the `hwrm_resp_hdr` upon completion.
17218 * The target ID of the command:
17219 * * 0x0-0xFFF8 - The function ID
17220 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
17221 * * 0xFFFD - Reserved for user-space HWRM interface
17224 uint16_t target_id;
17226 * A physical address pointer pointing to a host buffer that the
17227 * command's response data will be written. This can be either a host
17228 * physical address (HPA) or a guest physical address (GPA) and must
17229 * point to a physically contiguous block of memory.
17231 uint64_t resp_addr;
17233 * Function ID of the function that is being
17235 * If set to 0xFF... (All Fs), then the configuration is
17236 * for the requesting function.
17239 uint8_t unused_0[2];
17242 * This bit must be '1' for the stag_vid field to be
17245 #define HWRM_FUNC_VLAN_CFG_INPUT_ENABLES_STAG_VID UINT32_C(0x1)
17247 * This bit must be '1' for the ctag_vid field to be
17250 #define HWRM_FUNC_VLAN_CFG_INPUT_ENABLES_CTAG_VID UINT32_C(0x2)
17252 * This bit must be '1' for the stag_pcp field to be
17255 #define HWRM_FUNC_VLAN_CFG_INPUT_ENABLES_STAG_PCP UINT32_C(0x4)
17257 * This bit must be '1' for the ctag_pcp field to be
17260 #define HWRM_FUNC_VLAN_CFG_INPUT_ENABLES_CTAG_PCP UINT32_C(0x8)
17262 * This bit must be '1' for the stag_tpid field to be
17265 #define HWRM_FUNC_VLAN_CFG_INPUT_ENABLES_STAG_TPID UINT32_C(0x10)
17267 * This bit must be '1' for the ctag_tpid field to be
17270 #define HWRM_FUNC_VLAN_CFG_INPUT_ENABLES_CTAG_TPID UINT32_C(0x20)
17271 /* S-TAG VLAN identifier configured for the function. */
17273 /* S-TAG PCP value configured for the function. */
17277 * S-TAG TPID value configured for the function. This field is specified in
17278 * network byte order.
17280 uint16_t stag_tpid;
17281 /* C-TAG VLAN identifier configured for the function. */
17283 /* C-TAG PCP value configured for the function. */
17287 * C-TAG TPID value configured for the function. This field is specified in
17288 * network byte order.
17290 uint16_t ctag_tpid;
17295 uint8_t unused_3[4];
17298 /* hwrm_func_vlan_cfg_output (size:128b/16B) */
17299 struct hwrm_func_vlan_cfg_output {
17300 /* The specific error status for the command. */
17301 uint16_t error_code;
17302 /* The HWRM command request type. */
17304 /* The sequence ID from the original command. */
17306 /* The length of the response data in number of bytes. */
17308 uint8_t unused_0[7];
17310 * This field is used in Output records to indicate that the output
17311 * is completely written to RAM. This field should be read as '1'
17312 * to indicate that the output has been completely written.
17313 * When writing a command completion or response to an internal processor,
17314 * the order of writes has to be such that this field is written last.
17319 /*******************************
17320 * hwrm_func_vf_vnic_ids_query *
17321 *******************************/
17324 /* hwrm_func_vf_vnic_ids_query_input (size:256b/32B) */
17325 struct hwrm_func_vf_vnic_ids_query_input {
17326 /* The HWRM command request type. */
17329 * The completion ring to send the completion event on. This should
17330 * be the NQ ID returned from the `nq_alloc` HWRM command.
17332 uint16_t cmpl_ring;
17334 * The sequence ID is used by the driver for tracking multiple
17335 * commands. This ID is treated as opaque data by the firmware and
17336 * the value is returned in the `hwrm_resp_hdr` upon completion.
17340 * The target ID of the command:
17341 * * 0x0-0xFFF8 - The function ID
17342 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
17343 * * 0xFFFD - Reserved for user-space HWRM interface
17346 uint16_t target_id;
17348 * A physical address pointer pointing to a host buffer that the
17349 * command's response data will be written. This can be either a host
17350 * physical address (HPA) or a guest physical address (GPA) and must
17351 * point to a physically contiguous block of memory.
17353 uint64_t resp_addr;
17355 * This value is used to identify a Virtual Function (VF).
17356 * The scope of VF ID is local within a PF.
17359 uint8_t unused_0[2];
17360 /* Max number of vnic ids in vnic id table */
17361 uint32_t max_vnic_id_cnt;
17362 /* This is the address for VF VNIC ID table */
17363 uint64_t vnic_id_tbl_addr;
17366 /* hwrm_func_vf_vnic_ids_query_output (size:128b/16B) */
17367 struct hwrm_func_vf_vnic_ids_query_output {
17368 /* The specific error status for the command. */
17369 uint16_t error_code;
17370 /* The HWRM command request type. */
17372 /* The sequence ID from the original command. */
17374 /* The length of the response data in number of bytes. */
17377 * Actual number of vnic ids
17379 * Each VNIC ID is written as a 32-bit number.
17381 uint32_t vnic_id_cnt;
17382 uint8_t unused_0[3];
17384 * This field is used in Output records to indicate that the output
17385 * is completely written to RAM. This field should be read as '1'
17386 * to indicate that the output has been completely written.
17387 * When writing a command completion or response to an internal processor,
17388 * the order of writes has to be such that this field is written last.
17393 /***********************
17394 * hwrm_func_vf_bw_cfg *
17395 ***********************/
17398 /* hwrm_func_vf_bw_cfg_input (size:960b/120B) */
17399 struct hwrm_func_vf_bw_cfg_input {
17400 /* The HWRM command request type. */
17403 * The completion ring to send the completion event on. This should
17404 * be the NQ ID returned from the `nq_alloc` HWRM command.
17406 uint16_t cmpl_ring;
17408 * The sequence ID is used by the driver for tracking multiple
17409 * commands. This ID is treated as opaque data by the firmware and
17410 * the value is returned in the `hwrm_resp_hdr` upon completion.
17414 * The target ID of the command:
17415 * * 0x0-0xFFF8 - The function ID
17416 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
17417 * * 0xFFFD - Reserved for user-space HWRM interface
17420 uint16_t target_id;
17422 * A physical address pointer pointing to a host buffer that the
17423 * command's response data will be written. This can be either a host
17424 * physical address (HPA) or a guest physical address (GPA) and must
17425 * point to a physically contiguous block of memory.
17427 uint64_t resp_addr;
17429 * The number of VF functions that are being configured.
17430 * The cmd space allows up to 50 VFs' BW to be configured with one cmd.
17433 uint16_t unused[3];
17434 /* These 16-bit fields contain the VF fid and the rate scale percentage. */
17436 /* The physical VF id the adjustment will be made to. */
17437 #define HWRM_FUNC_VF_BW_CFG_INPUT_VFN_VFID_MASK UINT32_C(0xfff)
17438 #define HWRM_FUNC_VF_BW_CFG_INPUT_VFN_VFID_SFT 0
17440 * This field configures the rate scale percentage of the VF as specified
17441 * by the physical VF id.
17443 #define HWRM_FUNC_VF_BW_CFG_INPUT_VFN_RATE_MASK UINT32_C(0xf000)
17444 #define HWRM_FUNC_VF_BW_CFG_INPUT_VFN_RATE_SFT 12
17445 /* 0% of the max tx rate */
17446 #define HWRM_FUNC_VF_BW_CFG_INPUT_VFN_RATE_PCT_0 \
17447 (UINT32_C(0x0) << 12)
17448 /* 6.66% of the max tx rate */
17449 #define HWRM_FUNC_VF_BW_CFG_INPUT_VFN_RATE_PCT_6_66 \
17450 (UINT32_C(0x1) << 12)
17451 /* 13.33% of the max tx rate */
17452 #define HWRM_FUNC_VF_BW_CFG_INPUT_VFN_RATE_PCT_13_33 \
17453 (UINT32_C(0x2) << 12)
17454 /* 20% of the max tx rate */
17455 #define HWRM_FUNC_VF_BW_CFG_INPUT_VFN_RATE_PCT_20 \
17456 (UINT32_C(0x3) << 12)
17457 /* 26.66% of the max tx rate */
17458 #define HWRM_FUNC_VF_BW_CFG_INPUT_VFN_RATE_PCT_26_66 \
17459 (UINT32_C(0x4) << 12)
17460 /* 33% of the max tx rate */
17461 #define HWRM_FUNC_VF_BW_CFG_INPUT_VFN_RATE_PCT_33_33 \
17462 (UINT32_C(0x5) << 12)
17463 /* 40% of the max tx rate */
17464 #define HWRM_FUNC_VF_BW_CFG_INPUT_VFN_RATE_PCT_40 \
17465 (UINT32_C(0x6) << 12)
17466 /* 46.66% of the max tx rate */
17467 #define HWRM_FUNC_VF_BW_CFG_INPUT_VFN_RATE_PCT_46_66 \
17468 (UINT32_C(0x7) << 12)
17469 /* 53.33% of the max tx rate */
17470 #define HWRM_FUNC_VF_BW_CFG_INPUT_VFN_RATE_PCT_53_33 \
17471 (UINT32_C(0x8) << 12)
17472 /* 60% of the max tx rate */
17473 #define HWRM_FUNC_VF_BW_CFG_INPUT_VFN_RATE_PCT_60 \
17474 (UINT32_C(0x9) << 12)
17475 /* 66.66% of the max tx rate */
17476 #define HWRM_FUNC_VF_BW_CFG_INPUT_VFN_RATE_PCT_66_66 \
17477 (UINT32_C(0xa) << 12)
17478 /* 53.33% of the max tx rate */
17479 #define HWRM_FUNC_VF_BW_CFG_INPUT_VFN_RATE_PCT_73_33 \
17480 (UINT32_C(0xb) << 12)
17481 /* 80% of the max tx rate */
17482 #define HWRM_FUNC_VF_BW_CFG_INPUT_VFN_RATE_PCT_80 \
17483 (UINT32_C(0xc) << 12)
17484 /* 86.66% of the max tx rate */
17485 #define HWRM_FUNC_VF_BW_CFG_INPUT_VFN_RATE_PCT_86_66 \
17486 (UINT32_C(0xd) << 12)
17487 /* 93.33% of the max tx rate */
17488 #define HWRM_FUNC_VF_BW_CFG_INPUT_VFN_RATE_PCT_93_33 \
17489 (UINT32_C(0xe) << 12)
17490 /* 100% of the max tx rate */
17491 #define HWRM_FUNC_VF_BW_CFG_INPUT_VFN_RATE_PCT_100 \
17492 (UINT32_C(0xf) << 12)
17493 #define HWRM_FUNC_VF_BW_CFG_INPUT_VFN_RATE_LAST \
17494 HWRM_FUNC_VF_BW_CFG_INPUT_VFN_RATE_PCT_100
17497 /* hwrm_func_vf_bw_cfg_output (size:128b/16B) */
17498 struct hwrm_func_vf_bw_cfg_output {
17499 /* The specific error status for the command. */
17500 uint16_t error_code;
17501 /* The HWRM command request type. */
17503 /* The sequence ID from the original command. */
17505 /* The length of the response data in number of bytes. */
17507 uint8_t unused_0[7];
17509 * This field is used in Output records to indicate that the output
17510 * is completely written to RAM. This field should be read as '1'
17511 * to indicate that the output has been completely written.
17512 * When writing a command completion or response to an internal processor,
17513 * the order of writes has to be such that this field is written last.
17518 /************************
17519 * hwrm_func_vf_bw_qcfg *
17520 ************************/
17523 /* hwrm_func_vf_bw_qcfg_input (size:960b/120B) */
17524 struct hwrm_func_vf_bw_qcfg_input {
17525 /* The HWRM command request type. */
17528 * The completion ring to send the completion event on. This should
17529 * be the NQ ID returned from the `nq_alloc` HWRM command.
17531 uint16_t cmpl_ring;
17533 * The sequence ID is used by the driver for tracking multiple
17534 * commands. This ID is treated as opaque data by the firmware and
17535 * the value is returned in the `hwrm_resp_hdr` upon completion.
17539 * The target ID of the command:
17540 * * 0x0-0xFFF8 - The function ID
17541 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
17542 * * 0xFFFD - Reserved for user-space HWRM interface
17545 uint16_t target_id;
17547 * A physical address pointer pointing to a host buffer that the
17548 * command's response data will be written. This can be either a host
17549 * physical address (HPA) or a guest physical address (GPA) and must
17550 * point to a physically contiguous block of memory.
17552 uint64_t resp_addr;
17554 * The number of VF functions that are being queried.
17555 * The inline response space allows the host to query up to 50 VFs'
17556 * rate scale percentage
17559 uint16_t unused[3];
17560 /* These 16-bit fields contain the VF fid */
17562 /* The physical VF id of interest */
17563 #define HWRM_FUNC_VF_BW_QCFG_INPUT_VFN_VFID_MASK UINT32_C(0xfff)
17564 #define HWRM_FUNC_VF_BW_QCFG_INPUT_VFN_VFID_SFT 0
17567 /* hwrm_func_vf_bw_qcfg_output (size:960b/120B) */
17568 struct hwrm_func_vf_bw_qcfg_output {
17569 /* The specific error status for the command. */
17570 uint16_t error_code;
17571 /* The HWRM command request type. */
17573 /* The sequence ID from the original command. */
17575 /* The length of the response data in number of bytes. */
17578 * The number of VF functions that are being queried.
17579 * The inline response space allows the host to query up to 50 VFs' rate
17583 uint16_t unused[3];
17584 /* These 16-bit fields contain the VF fid and the rate scale percentage. */
17586 /* The physical VF id the adjustment will be made to. */
17587 #define HWRM_FUNC_VF_BW_QCFG_OUTPUT_VFN_VFID_MASK UINT32_C(0xfff)
17588 #define HWRM_FUNC_VF_BW_QCFG_OUTPUT_VFN_VFID_SFT 0
17590 * This field configures the rate scale percentage of the VF as specified
17591 * by the physical VF id.
17593 #define HWRM_FUNC_VF_BW_QCFG_OUTPUT_VFN_RATE_MASK UINT32_C(0xf000)
17594 #define HWRM_FUNC_VF_BW_QCFG_OUTPUT_VFN_RATE_SFT 12
17595 /* 0% of the max tx rate */
17596 #define HWRM_FUNC_VF_BW_QCFG_OUTPUT_VFN_RATE_PCT_0 \
17597 (UINT32_C(0x0) << 12)
17598 /* 6.66% of the max tx rate */
17599 #define HWRM_FUNC_VF_BW_QCFG_OUTPUT_VFN_RATE_PCT_6_66 \
17600 (UINT32_C(0x1) << 12)
17601 /* 13.33% of the max tx rate */
17602 #define HWRM_FUNC_VF_BW_QCFG_OUTPUT_VFN_RATE_PCT_13_33 \
17603 (UINT32_C(0x2) << 12)
17604 /* 20% of the max tx rate */
17605 #define HWRM_FUNC_VF_BW_QCFG_OUTPUT_VFN_RATE_PCT_20 \
17606 (UINT32_C(0x3) << 12)
17607 /* 26.66% of the max tx rate */
17608 #define HWRM_FUNC_VF_BW_QCFG_OUTPUT_VFN_RATE_PCT_26_66 \
17609 (UINT32_C(0x4) << 12)
17610 /* 33% of the max tx rate */
17611 #define HWRM_FUNC_VF_BW_QCFG_OUTPUT_VFN_RATE_PCT_33_33 \
17612 (UINT32_C(0x5) << 12)
17613 /* 40% of the max tx rate */
17614 #define HWRM_FUNC_VF_BW_QCFG_OUTPUT_VFN_RATE_PCT_40 \
17615 (UINT32_C(0x6) << 12)
17616 /* 46.66% of the max tx rate */
17617 #define HWRM_FUNC_VF_BW_QCFG_OUTPUT_VFN_RATE_PCT_46_66 \
17618 (UINT32_C(0x7) << 12)
17619 /* 53.33% of the max tx rate */
17620 #define HWRM_FUNC_VF_BW_QCFG_OUTPUT_VFN_RATE_PCT_53_33 \
17621 (UINT32_C(0x8) << 12)
17622 /* 60% of the max tx rate */
17623 #define HWRM_FUNC_VF_BW_QCFG_OUTPUT_VFN_RATE_PCT_60 \
17624 (UINT32_C(0x9) << 12)
17625 /* 66.66% of the max tx rate */
17626 #define HWRM_FUNC_VF_BW_QCFG_OUTPUT_VFN_RATE_PCT_66_66 \
17627 (UINT32_C(0xa) << 12)
17628 /* 53.33% of the max tx rate */
17629 #define HWRM_FUNC_VF_BW_QCFG_OUTPUT_VFN_RATE_PCT_73_33 \
17630 (UINT32_C(0xb) << 12)
17631 /* 80% of the max tx rate */
17632 #define HWRM_FUNC_VF_BW_QCFG_OUTPUT_VFN_RATE_PCT_80 \
17633 (UINT32_C(0xc) << 12)
17634 /* 86.66% of the max tx rate */
17635 #define HWRM_FUNC_VF_BW_QCFG_OUTPUT_VFN_RATE_PCT_86_66 \
17636 (UINT32_C(0xd) << 12)
17637 /* 93.33% of the max tx rate */
17638 #define HWRM_FUNC_VF_BW_QCFG_OUTPUT_VFN_RATE_PCT_93_33 \
17639 (UINT32_C(0xe) << 12)
17640 /* 100% of the max tx rate */
17641 #define HWRM_FUNC_VF_BW_QCFG_OUTPUT_VFN_RATE_PCT_100 \
17642 (UINT32_C(0xf) << 12)
17643 #define HWRM_FUNC_VF_BW_QCFG_OUTPUT_VFN_RATE_LAST \
17644 HWRM_FUNC_VF_BW_QCFG_OUTPUT_VFN_RATE_PCT_100
17645 uint8_t unused_0[7];
17647 * This field is used in Output records to indicate that the output
17648 * is completely written to RAM. This field should be read as '1'
17649 * to indicate that the output has been completely written.
17650 * When writing a command completion or response to an internal processor,
17651 * the order of writes has to be such that this field is written last.
17656 /***************************
17657 * hwrm_func_drv_if_change *
17658 ***************************/
17661 /* hwrm_func_drv_if_change_input (size:192b/24B) */
17662 struct hwrm_func_drv_if_change_input {
17663 /* The HWRM command request type. */
17666 * The completion ring to send the completion event on. This should
17667 * be the NQ ID returned from the `nq_alloc` HWRM command.
17669 uint16_t cmpl_ring;
17671 * The sequence ID is used by the driver for tracking multiple
17672 * commands. This ID is treated as opaque data by the firmware and
17673 * the value is returned in the `hwrm_resp_hdr` upon completion.
17677 * The target ID of the command:
17678 * * 0x0-0xFFF8 - The function ID
17679 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
17680 * * 0xFFFD - Reserved for user-space HWRM interface
17683 uint16_t target_id;
17685 * A physical address pointer pointing to a host buffer that the
17686 * command's response data will be written. This can be either a host
17687 * physical address (HPA) or a guest physical address (GPA) and must
17688 * point to a physically contiguous block of memory.
17690 uint64_t resp_addr;
17693 * When this bit is '1', the function driver is indicating
17694 * that the IF state is changing to UP state. The call should
17695 * be made at the beginning of the driver's open call before
17696 * resources are allocated. After making the call, the driver
17697 * should check the response to see if any resources may have
17698 * changed (see the response below). If the driver fails
17699 * the open call, the driver should make this call again with
17700 * this bit cleared to indicate that the IF state is not UP.
17701 * During the driver's close call when the IF state is changing
17702 * to DOWN, the driver should make this call with the bit cleared
17703 * after all resources have been freed.
17705 #define HWRM_FUNC_DRV_IF_CHANGE_INPUT_FLAGS_UP UINT32_C(0x1)
17709 /* hwrm_func_drv_if_change_output (size:128b/16B) */
17710 struct hwrm_func_drv_if_change_output {
17711 /* The specific error status for the command. */
17712 uint16_t error_code;
17713 /* The HWRM command request type. */
17715 /* The sequence ID from the original command. */
17717 /* The length of the response data in number of bytes. */
17721 * When this bit is '1', it indicates that the resources reserved
17722 * for this function may have changed. The driver should check
17723 * resource capabilities and reserve resources again before
17724 * allocating resources.
17726 #define HWRM_FUNC_DRV_IF_CHANGE_OUTPUT_FLAGS_RESC_CHANGE \
17729 * When this bit is '1', it indicates that the firmware got changed / reset.
17730 * The driver should do complete re-initialization when that bit is set.
17732 #define HWRM_FUNC_DRV_IF_CHANGE_OUTPUT_FLAGS_HOT_FW_RESET_DONE \
17734 uint8_t unused_0[3];
17736 * This field is used in Output records to indicate that the output
17737 * is completely written to RAM. This field should be read as '1'
17738 * to indicate that the output has been completely written.
17739 * When writing a command completion or response to an internal processor,
17740 * the order of writes has to be such that this field is written last.
17745 /*******************************
17746 * hwrm_func_host_pf_ids_query *
17747 *******************************/
17750 /* hwrm_func_host_pf_ids_query_input (size:192b/24B) */
17751 struct hwrm_func_host_pf_ids_query_input {
17752 /* The HWRM command request type. */
17755 * The completion ring to send the completion event on. This should
17756 * be the NQ ID returned from the `nq_alloc` HWRM command.
17758 uint16_t cmpl_ring;
17760 * The sequence ID is used by the driver for tracking multiple
17761 * commands. This ID is treated as opaque data by the firmware and
17762 * the value is returned in the `hwrm_resp_hdr` upon completion.
17766 * The target ID of the command:
17767 * * 0x0-0xFFF8 - The function ID
17768 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
17769 * * 0xFFFD - Reserved for user-space HWRM interface
17772 uint16_t target_id;
17774 * A physical address pointer pointing to a host buffer that the
17775 * command's response data will be written. This can be either a host
17776 * physical address (HPA) or a guest physical address (GPA) and must
17777 * point to a physically contiguous block of memory.
17779 uint64_t resp_addr;
17782 * # If this bit is set to '1', the query will contain PF(s)
17783 * belongs to SOC host.
17785 #define HWRM_FUNC_HOST_PF_IDS_QUERY_INPUT_HOST_SOC UINT32_C(0x1)
17787 * # If this bit is set to '1', the query will contain PF(s)
17788 * belongs to EP0 host.
17790 #define HWRM_FUNC_HOST_PF_IDS_QUERY_INPUT_HOST_EP_0 UINT32_C(0x2)
17792 * # If this bit is set to '1', the query will contain PF(s)
17793 * belongs to EP1 host.
17795 #define HWRM_FUNC_HOST_PF_IDS_QUERY_INPUT_HOST_EP_1 UINT32_C(0x4)
17797 * # If this bit is set to '1', the query will contain PF(s)
17798 * belongs to EP2 host.
17800 #define HWRM_FUNC_HOST_PF_IDS_QUERY_INPUT_HOST_EP_2 UINT32_C(0x8)
17802 * # If this bit is set to '1', the query will contain PF(s)
17803 * belongs to EP3 host.
17805 #define HWRM_FUNC_HOST_PF_IDS_QUERY_INPUT_HOST_EP_3 UINT32_C(0x10)
17807 * This provides a filter of what PF(s) will be returned in the
17812 * all available PF(s) belong to the host(s) (defined in the
17813 * host field). This includes the hidden PFs.
17815 #define HWRM_FUNC_HOST_PF_IDS_QUERY_INPUT_FILTER_ALL UINT32_C(0x0)
17817 * all available PF(s) belong to the host(s) (defined in the
17818 * host field) that is available for L2 traffic.
17820 #define HWRM_FUNC_HOST_PF_IDS_QUERY_INPUT_FILTER_L2 UINT32_C(0x1)
17822 * all available PF(s) belong to the host(s) (defined in the
17823 * host field) that is available for ROCE traffic.
17825 #define HWRM_FUNC_HOST_PF_IDS_QUERY_INPUT_FILTER_ROCE UINT32_C(0x2)
17826 #define HWRM_FUNC_HOST_PF_IDS_QUERY_INPUT_FILTER_LAST \
17827 HWRM_FUNC_HOST_PF_IDS_QUERY_INPUT_FILTER_ROCE
17828 uint8_t unused_1[6];
17831 /* hwrm_func_host_pf_ids_query_output (size:128b/16B) */
17832 struct hwrm_func_host_pf_ids_query_output {
17833 /* The specific error status for the command. */
17834 uint16_t error_code;
17835 /* The HWRM command request type. */
17837 /* The sequence ID from the original command. */
17839 /* The length of the response data in number of bytes. */
17841 /* This provides the first PF ID of the device. */
17842 uint16_t first_pf_id;
17843 uint16_t pf_ordinal_mask;
17845 * When this bit is '1', it indicates first PF belongs to one of
17846 * the hosts defined in the input request.
17848 #define HWRM_FUNC_HOST_PF_IDS_QUERY_OUTPUT_PF_ORDINAL_MASK_FUNC_0 \
17851 * When this bit is '1', it indicates 2nd PF belongs to one of the
17852 * hosts defined in the input request.
17854 #define HWRM_FUNC_HOST_PF_IDS_QUERY_OUTPUT_PF_ORDINAL_MASK_FUNC_1 \
17857 * When this bit is '1', it indicates 3rd PF belongs to one of the
17858 * hosts defined in the input request.
17860 #define HWRM_FUNC_HOST_PF_IDS_QUERY_OUTPUT_PF_ORDINAL_MASK_FUNC_2 \
17863 * When this bit is '1', it indicates 4th PF belongs to one of the
17864 * hosts defined in the input request.
17866 #define HWRM_FUNC_HOST_PF_IDS_QUERY_OUTPUT_PF_ORDINAL_MASK_FUNC_3 \
17869 * When this bit is '1', it indicates 5th PF belongs to one of the
17870 * hosts defined in the input request.
17872 #define HWRM_FUNC_HOST_PF_IDS_QUERY_OUTPUT_PF_ORDINAL_MASK_FUNC_4 \
17875 * When this bit is '1', it indicates 6th PF belongs to one of the
17876 * hosts defined in the input request.
17878 #define HWRM_FUNC_HOST_PF_IDS_QUERY_OUTPUT_PF_ORDINAL_MASK_FUNC_5 \
17881 * When this bit is '1', it indicates 7th PF belongs to one of the
17882 * hosts defined in the input request.
17884 #define HWRM_FUNC_HOST_PF_IDS_QUERY_OUTPUT_PF_ORDINAL_MASK_FUNC_6 \
17887 * When this bit is '1', it indicates 8th PF belongs to one of the
17888 * hosts defined in the input request.
17890 #define HWRM_FUNC_HOST_PF_IDS_QUERY_OUTPUT_PF_ORDINAL_MASK_FUNC_7 \
17893 * When this bit is '1', it indicates 9th PF belongs to one of the
17894 * hosts defined in the input request.
17896 #define HWRM_FUNC_HOST_PF_IDS_QUERY_OUTPUT_PF_ORDINAL_MASK_FUNC_8 \
17899 * When this bit is '1', it indicates 10th PF belongs to one of the
17900 * hosts defined in the input request.
17902 #define HWRM_FUNC_HOST_PF_IDS_QUERY_OUTPUT_PF_ORDINAL_MASK_FUNC_9 \
17905 * When this bit is '1', it indicates 11th PF belongs to one of the
17906 * hosts defined in the input request.
17908 #define HWRM_FUNC_HOST_PF_IDS_QUERY_OUTPUT_PF_ORDINAL_MASK_FUNC_10 \
17911 * When this bit is '1', it indicates 12th PF belongs to one of the
17912 * hosts defined in the input request.
17914 #define HWRM_FUNC_HOST_PF_IDS_QUERY_OUTPUT_PF_ORDINAL_MASK_FUNC_11 \
17917 * When this bit is '1', it indicates 13th PF belongs to one of the
17918 * hosts defined in the input request.
17920 #define HWRM_FUNC_HOST_PF_IDS_QUERY_OUTPUT_PF_ORDINAL_MASK_FUNC_12 \
17923 * When this bit is '1', it indicates 14th PF belongs to one of the
17924 * hosts defined in the input request.
17926 #define HWRM_FUNC_HOST_PF_IDS_QUERY_OUTPUT_PF_ORDINAL_MASK_FUNC_13 \
17929 * When this bit is '1', it indicates 15th PF belongs to one of the
17930 * hosts defined in the input request.
17932 #define HWRM_FUNC_HOST_PF_IDS_QUERY_OUTPUT_PF_ORDINAL_MASK_FUNC_14 \
17935 * When this bit is '1', it indicates 16th PF belongs to one of the
17936 * hosts defined in the input request.
17938 #define HWRM_FUNC_HOST_PF_IDS_QUERY_OUTPUT_PF_ORDINAL_MASK_FUNC_15 \
17940 uint8_t unused_1[3];
17942 * This field is used in Output records to indicate that the output
17943 * is completely written to RAM. This field should be read as '1'
17944 * to indicate that the output has been completely written.
17945 * When writing a command completion or response to an internal processor,
17946 * the order of writes has to be such that this field is written last.
17951 /*********************
17952 * hwrm_func_spd_cfg *
17953 *********************/
17956 /* hwrm_func_spd_cfg_input (size:384b/48B) */
17957 struct hwrm_func_spd_cfg_input {
17958 /* The HWRM command request type. */
17961 * The completion ring to send the completion event on. This should
17962 * be the NQ ID returned from the `nq_alloc` HWRM command.
17964 uint16_t cmpl_ring;
17966 * The sequence ID is used by the driver for tracking multiple
17967 * commands. This ID is treated as opaque data by the firmware and
17968 * the value is returned in the `hwrm_resp_hdr` upon completion.
17972 * The target ID of the command:
17973 * * 0x0-0xFFF8 - The function ID
17974 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
17975 * * 0xFFFD - Reserved for user-space HWRM interface
17978 uint16_t target_id;
17980 * A physical address pointer pointing to a host buffer that the
17981 * command's response data will be written. This can be either a host
17982 * physical address (HPA) or a guest physical address (GPA) and must
17983 * point to a physically contiguous block of memory.
17985 uint64_t resp_addr;
17987 /* Set this bit is '1' to enable the SPD datapath forwarding. */
17988 #define HWRM_FUNC_SPD_CFG_INPUT_FLAGS_FWD_ENABLE UINT32_C(0x1)
17989 /* Set this bit is '1' to disable the SPD datapath forwarding. */
17990 #define HWRM_FUNC_SPD_CFG_INPUT_FLAGS_FWD_DISABLE UINT32_C(0x2)
17992 * Set this bit is '1' to enable the SPD datapath checksum
17995 #define HWRM_FUNC_SPD_CFG_INPUT_FLAGS_CSUM_ENABLE UINT32_C(0x4)
17997 * Set this bit is '1' to disable the SPD datapath checksum
18000 #define HWRM_FUNC_SPD_CFG_INPUT_FLAGS_CSUM_DISABLE UINT32_C(0x8)
18002 * Set this bit is '1' to enable the SPD datapath debug
18005 #define HWRM_FUNC_SPD_CFG_INPUT_FLAGS_DBG_ENABLE UINT32_C(0x10)
18007 * Set this bit is '1' to disable the SPD datapath debug
18010 #define HWRM_FUNC_SPD_CFG_INPUT_FLAGS_DBG_DISABLE UINT32_C(0x20)
18013 * This bit must be '1' for the ethertype field to be
18016 #define HWRM_FUNC_SPD_CFG_INPUT_ENABLES_ETHERTYPE \
18019 * This bit must be '1' for the hash_mode_flags field to be
18022 #define HWRM_FUNC_SPD_CFG_INPUT_ENABLES_HASH_MODE_FLAGS \
18025 * This bit must be '1' for the hash_type field to be
18028 #define HWRM_FUNC_SPD_CFG_INPUT_ENABLES_HASH_TYPE \
18031 * This bit must be '1' for the ring_tbl_addr field to be
18034 #define HWRM_FUNC_SPD_CFG_INPUT_ENABLES_RING_TBL_ADDR \
18037 * This bit must be '1' for the hash_key_tbl_addr field to be
18040 #define HWRM_FUNC_SPD_CFG_INPUT_ENABLES_HASH_KEY_TBL_ADDR \
18043 * Ethertype value used in the encapsulated SPD packet header.
18044 * The user must choose a value that is not conflicting with
18045 * publicly defined ethertype values. By default, the ethertype
18046 * value of 0xffff is used if there is no user specified value.
18048 uint16_t ethertype;
18049 /* Flags to specify different RSS hash modes. */
18050 uint8_t hash_mode_flags;
18052 * When this bit is '1', it indicates using current RSS
18053 * hash mode setting configured in the device.
18055 #define HWRM_FUNC_SPD_CFG_INPUT_HASH_MODE_FLAGS_DEFAULT \
18058 * When this bit is '1', it indicates requesting support of
18059 * RSS hashing over innermost 4 tuples {l3.src, l3.dest,
18060 * l4.src, l4.dest} for tunnel packets. For none-tunnel
18061 * packets, the RSS hash is computed over the normal
18062 * src/dest l3 and src/dest l4 headers.
18064 #define HWRM_FUNC_SPD_CFG_INPUT_HASH_MODE_FLAGS_INNERMOST_4 \
18067 * When this bit is '1', it indicates requesting support of
18068 * RSS hashing over innermost 2 tuples {l3.src, l3.dest} for
18069 * tunnel packets. For none-tunnel packets, the RSS hash is
18070 * computed over the normal src/dest l3 headers.
18072 #define HWRM_FUNC_SPD_CFG_INPUT_HASH_MODE_FLAGS_INNERMOST_2 \
18075 * When this bit is '1', it indicates requesting support of
18076 * RSS hashing over outermost 4 tuples {t_l3.src, t_l3.dest,
18077 * t_l4.src, t_l4.dest} for tunnel packets. For none-tunnel
18078 * packets, the RSS hash is computed over the normal
18079 * src/dest l3 and src/dest l4 headers.
18081 #define HWRM_FUNC_SPD_CFG_INPUT_HASH_MODE_FLAGS_OUTERMOST_4 \
18084 * When this bit is '1', it indicates requesting support of
18085 * RSS hashing over outermost 2 tuples {t_l3.src, t_l3.dest} for
18086 * tunnel packets. For none-tunnel packets, the RSS hash is
18087 * computed over the normal src/dest l3 headers.
18089 #define HWRM_FUNC_SPD_CFG_INPUT_HASH_MODE_FLAGS_OUTERMOST_2 \
18092 uint32_t hash_type;
18094 * When this bit is '1', the RSS hash shall be computed
18095 * over source and destination IPv4 addresses of IPv4
18098 #define HWRM_FUNC_SPD_CFG_INPUT_HASH_TYPE_IPV4 UINT32_C(0x1)
18100 * When this bit is '1', the RSS hash shall be computed
18101 * over source/destination IPv4 addresses and
18102 * source/destination ports of TCP/IPv4 packets.
18104 #define HWRM_FUNC_SPD_CFG_INPUT_HASH_TYPE_TCP_IPV4 UINT32_C(0x2)
18106 * When this bit is '1', the RSS hash shall be computed
18107 * over source/destination IPv4 addresses and
18108 * source/destination ports of UDP/IPv4 packets.
18110 #define HWRM_FUNC_SPD_CFG_INPUT_HASH_TYPE_UDP_IPV4 UINT32_C(0x4)
18112 * When this bit is '1', the RSS hash shall be computed
18113 * over source and destination IPv4 addresses of IPv6
18116 #define HWRM_FUNC_SPD_CFG_INPUT_HASH_TYPE_IPV6 UINT32_C(0x8)
18118 * When this bit is '1', the RSS hash shall be computed
18119 * over source/destination IPv6 addresses and
18120 * source/destination ports of TCP/IPv6 packets.
18122 #define HWRM_FUNC_SPD_CFG_INPUT_HASH_TYPE_TCP_IPV6 UINT32_C(0x10)
18124 * When this bit is '1', the RSS hash shall be computed
18125 * over source/destination IPv6 addresses and
18126 * source/destination ports of UDP/IPv6 packets.
18128 #define HWRM_FUNC_SPD_CFG_INPUT_HASH_TYPE_UDP_IPV6 UINT32_C(0x20)
18129 /* This is the address for rss ring group table */
18130 uint64_t ring_grp_tbl_addr;
18131 /* This is the address for rss hash key table */
18132 uint64_t hash_key_tbl_addr;
18135 /* hwrm_func_spd_cfg_output (size:128b/16B) */
18136 struct hwrm_func_spd_cfg_output {
18137 /* The specific error status for the command. */
18138 uint16_t error_code;
18139 /* The HWRM command request type. */
18141 /* The sequence ID from the original command. */
18143 /* The length of the response data in number of bytes. */
18145 uint8_t unused_0[7];
18147 * This field is used in Output records to indicate that the output
18148 * is completely written to RAM. This field should be read as '1'
18149 * to indicate that the output has been completely written.
18150 * When writing a command completion or response to an internal processor,
18151 * the order of writes has to be such that this field is written last.
18156 /**********************
18157 * hwrm_func_spd_qcfg *
18158 **********************/
18161 /* hwrm_func_spd_qcfg_input (size:128b/16B) */
18162 struct hwrm_func_spd_qcfg_input {
18163 /* The HWRM command request type. */
18166 * The completion ring to send the completion event on. This should
18167 * be the NQ ID returned from the `nq_alloc` HWRM command.
18169 uint16_t cmpl_ring;
18171 * The sequence ID is used by the driver for tracking multiple
18172 * commands. This ID is treated as opaque data by the firmware and
18173 * the value is returned in the `hwrm_resp_hdr` upon completion.
18177 * The target ID of the command:
18178 * * 0x0-0xFFF8 - The function ID
18179 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
18180 * * 0xFFFD - Reserved for user-space HWRM interface
18183 uint16_t target_id;
18185 * A physical address pointer pointing to a host buffer that the
18186 * command's response data will be written. This can be either a host
18187 * physical address (HPA) or a guest physical address (GPA) and must
18188 * point to a physically contiguous block of memory.
18190 uint64_t resp_addr;
18193 /* hwrm_func_spd_qcfg_output (size:512b/64B) */
18194 struct hwrm_func_spd_qcfg_output {
18195 /* The specific error status for the command. */
18196 uint16_t error_code;
18197 /* The HWRM command request type. */
18199 /* The sequence ID from the original command. */
18201 /* The length of the response data in number of bytes. */
18205 * The SPD datapath forwarding is currently enabled when this
18206 * flag is set to '1'.
18208 #define HWRM_FUNC_SPD_QCFG_OUTPUT_FLAGS_FWD_ENABLED UINT32_C(0x1)
18210 * The SPD datapath checksum feature is currently enabled when
18211 * this flag is set to '1'.
18213 #define HWRM_FUNC_SPD_QCFG_OUTPUT_FLAGS_CSUM_ENABLED UINT32_C(0x2)
18215 * The SPD datapath debug feature is currently enabled when
18216 * this flag is set to '1'.
18218 #define HWRM_FUNC_SPD_QCFG_OUTPUT_FLAGS_DBG_ENABLED UINT32_C(0x4)
18219 uint32_t hash_type;
18221 * When this bit is '1', the RSS hash shall be computed
18222 * over source and destination IPv4 addresses of IPv4
18225 #define HWRM_FUNC_SPD_QCFG_OUTPUT_HASH_TYPE_IPV4 UINT32_C(0x1)
18227 * When this bit is '1', the RSS hash shall be computed
18228 * over source/destination IPv4 addresses and
18229 * source/destination ports of TCP/IPv4 packets.
18231 #define HWRM_FUNC_SPD_QCFG_OUTPUT_HASH_TYPE_TCP_IPV4 UINT32_C(0x2)
18233 * When this bit is '1', the RSS hash shall be computed
18234 * over source/destination IPv4 addresses and
18235 * source/destination ports of UDP/IPv4 packets.
18237 #define HWRM_FUNC_SPD_QCFG_OUTPUT_HASH_TYPE_UDP_IPV4 UINT32_C(0x4)
18239 * When this bit is '1', the RSS hash shall be computed
18240 * over source and destination IPv4 addresses of IPv6
18243 #define HWRM_FUNC_SPD_QCFG_OUTPUT_HASH_TYPE_IPV6 UINT32_C(0x8)
18245 * When this bit is '1', the RSS hash shall be computed
18246 * over source/destination IPv6 addresses and
18247 * source/destination ports of TCP/IPv6 packets.
18249 #define HWRM_FUNC_SPD_QCFG_OUTPUT_HASH_TYPE_TCP_IPV6 UINT32_C(0x10)
18251 * When this bit is '1', the RSS hash shall be computed
18252 * over source/destination IPv6 addresses and
18253 * source/destination ports of UDP/IPv6 packets.
18255 #define HWRM_FUNC_SPD_QCFG_OUTPUT_HASH_TYPE_UDP_IPV6 UINT32_C(0x20)
18256 /* This is the value of rss hash key */
18257 uint32_t hash_key[10];
18258 /* Flags to specify different RSS hash modes. */
18259 uint8_t hash_mode_flags;
18261 * When this bit is '1', it indicates using current RSS
18262 * hash mode setting configured in the device.
18264 #define HWRM_FUNC_SPD_QCFG_OUTPUT_HASH_MODE_FLAGS_DEFAULT \
18267 * When this bit is '1', it indicates requesting support of
18268 * RSS hashing over innermost 4 tuples {l3.src, l3.dest,
18269 * l4.src, l4.dest} for tunnel packets. For none-tunnel
18270 * packets, the RSS hash is computed over the normal
18271 * src/dest l3 and src/dest l4 headers.
18273 #define HWRM_FUNC_SPD_QCFG_OUTPUT_HASH_MODE_FLAGS_INNERMOST_4 \
18276 * When this bit is '1', it indicates requesting support of
18277 * RSS hashing over innermost 2 tuples {l3.src, l3.dest} for
18278 * tunnel packets. For none-tunnel packets, the RSS hash is
18279 * computed over the normal src/dest l3 headers.
18281 #define HWRM_FUNC_SPD_QCFG_OUTPUT_HASH_MODE_FLAGS_INNERMOST_2 \
18284 * When this bit is '1', it indicates requesting support of
18285 * RSS hashing over outermost 4 tuples {t_l3.src, t_l3.dest,
18286 * t_l4.src, t_l4.dest} for tunnel packets. For none-tunnel
18287 * packets, the RSS hash is computed over the normal
18288 * src/dest l3 and src/dest l4 headers.
18290 #define HWRM_FUNC_SPD_QCFG_OUTPUT_HASH_MODE_FLAGS_OUTERMOST_4 \
18293 * When this bit is '1', it indicates requesting support of
18294 * RSS hashing over outermost 2 tuples {t_l3.src, t_l3.dest} for
18295 * tunnel packets. For none-tunnel packets, the RSS hash is
18296 * computed over the normal src/dest l3 headers.
18298 #define HWRM_FUNC_SPD_QCFG_OUTPUT_HASH_MODE_FLAGS_OUTERMOST_2 \
18302 * Ethertype value used in the encapsulated SPD packet header.
18303 * The user must choose a value that is not conflicting with
18304 * publicly defined ethertype values. By default, the ethertype
18305 * value of 0xffff is used if there is no user specified value.
18307 uint16_t ethertype;
18308 uint8_t unused_2[3];
18310 * This field is used in Output records to indicate that the output
18311 * is completely written to RAM. This field should be read as '1'
18312 * to indicate that the output has been completely written.
18313 * When writing a command completion or response to an internal processor,
18314 * the order of writes has to be such that this field is written last.
18319 /*********************
18320 * hwrm_port_phy_cfg *
18321 *********************/
18324 /* hwrm_port_phy_cfg_input (size:448b/56B) */
18325 struct hwrm_port_phy_cfg_input {
18326 /* The HWRM command request type. */
18329 * The completion ring to send the completion event on. This should
18330 * be the NQ ID returned from the `nq_alloc` HWRM command.
18332 uint16_t cmpl_ring;
18334 * The sequence ID is used by the driver for tracking multiple
18335 * commands. This ID is treated as opaque data by the firmware and
18336 * the value is returned in the `hwrm_resp_hdr` upon completion.
18340 * The target ID of the command:
18341 * * 0x0-0xFFF8 - The function ID
18342 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
18343 * * 0xFFFD - Reserved for user-space HWRM interface
18346 uint16_t target_id;
18348 * A physical address pointer pointing to a host buffer that the
18349 * command's response data will be written. This can be either a host
18350 * physical address (HPA) or a guest physical address (GPA) and must
18351 * point to a physically contiguous block of memory.
18353 uint64_t resp_addr;
18356 * When this bit is set to '1', the PHY for the port shall
18359 * # If this bit is set to 1, then the HWRM shall reset the
18360 * PHY after applying PHY configuration changes specified
18362 * # In order to guarantee that PHY configuration changes
18363 * specified in this command take effect, the HWRM
18364 * client should set this flag to 1.
18365 * # If this bit is not set to 1, then the HWRM may reset
18366 * the PHY depending on the current PHY configuration and
18367 * settings specified in this command.
18369 #define HWRM_PORT_PHY_CFG_INPUT_FLAGS_RESET_PHY \
18371 /* deprecated bit. Do not use!!! */
18372 #define HWRM_PORT_PHY_CFG_INPUT_FLAGS_DEPRECATED \
18375 * When this bit is set to '1', and the force_pam4_link_speed
18376 * bit in the 'enables' field is '0', the link shall be forced
18377 * to the force_link_speed value.
18379 * When this bit is set to '1', and the force_pam4_link_speed
18380 * bit in the 'enables' field is '1', the link shall be forced
18381 * to the force_pam4_link_speed value.
18383 * When this bit is set to '1', the HWRM client should
18384 * not enable any of the auto negotiation related
18385 * fields represented by auto_XXX fields in this command.
18386 * When this bit is set to '1' and the HWRM client has
18387 * enabled a auto_XXX field in this command, then the
18388 * HWRM shall ignore the enabled auto_XXX field.
18390 * When this bit is set to zero, the link
18391 * shall be allowed to autoneg.
18393 #define HWRM_PORT_PHY_CFG_INPUT_FLAGS_FORCE \
18396 * When this bit is set to '1', the auto-negotiation process
18397 * shall be restarted on the link.
18399 #define HWRM_PORT_PHY_CFG_INPUT_FLAGS_RESTART_AUTONEG \
18402 * When this bit is set to '1', Energy Efficient Ethernet
18403 * (EEE) is requested to be enabled on this link.
18404 * If EEE is not supported on this port, then this flag
18405 * shall be ignored by the HWRM.
18407 #define HWRM_PORT_PHY_CFG_INPUT_FLAGS_EEE_ENABLE \
18410 * When this bit is set to '1', Energy Efficient Ethernet
18411 * (EEE) is requested to be disabled on this link.
18412 * If EEE is not supported on this port, then this flag
18413 * shall be ignored by the HWRM.
18415 #define HWRM_PORT_PHY_CFG_INPUT_FLAGS_EEE_DISABLE \
18418 * When this bit is set to '1' and EEE is enabled on this
18419 * link, then TX LPI is requested to be enabled on the link.
18420 * If EEE is not supported on this port, then this flag
18421 * shall be ignored by the HWRM.
18422 * If EEE is disabled on this port, then this flag shall be
18423 * ignored by the HWRM.
18425 #define HWRM_PORT_PHY_CFG_INPUT_FLAGS_EEE_TX_LPI_ENABLE \
18428 * When this bit is set to '1' and EEE is enabled on this
18429 * link, then TX LPI is requested to be disabled on the link.
18430 * If EEE is not supported on this port, then this flag
18431 * shall be ignored by the HWRM.
18432 * If EEE is disabled on this port, then this flag shall be
18433 * ignored by the HWRM.
18435 #define HWRM_PORT_PHY_CFG_INPUT_FLAGS_EEE_TX_LPI_DISABLE \
18438 * When set to 1, then the HWRM shall enable FEC autonegotitation
18439 * on this port if supported. When enabled, at least one of the
18440 * FEC modes must be advertised by enabling the fec_clause_74_enable,
18441 * fec_clause_91_enable, fec_rs544_1xn_enable, fec_rs544_ieee_enable,
18442 * fec_rs272_1xn_enable, or fec_rs272_ieee_enable flag. If none
18443 * of the FEC mode is currently enabled, the HWRM shall choose
18444 * a default advertisement setting.
18445 * The default advertisement setting can be queried by calling
18446 * hwrm_port_phy_qcfg. Note that the link speed must be
18447 * in autonegotiation mode for FEC autonegotiation to take effect.
18448 * When set to 0, then this flag shall be ignored.
18449 * If FEC autonegotiation is not supported, then the HWRM shall ignore this
18452 #define HWRM_PORT_PHY_CFG_INPUT_FLAGS_FEC_AUTONEG_ENABLE \
18455 * When set to 1, then the HWRM shall disable FEC autonegotiation
18456 * on this port and use forced FEC mode. In forced FEC mode, one
18457 * or more FEC forced settings under the same clause can be set.
18458 * When set to 0, then this flag shall be ignored.
18459 * If FEC autonegotiation is not supported, then the HWRM shall ignore this
18462 #define HWRM_PORT_PHY_CFG_INPUT_FLAGS_FEC_AUTONEG_DISABLE \
18465 * When set to 1, then the HWRM shall enable FEC CLAUSE 74 (Fire Code)
18466 * on this port if supported, by advertising FEC CLAUSE 74 if
18467 * FEC autonegotiation is enabled or force enabled otherwise.
18468 * When set to 0, then this flag shall be ignored.
18469 * If FEC CLAUSE 74 is not supported, then the HWRM shall ignore this
18472 #define HWRM_PORT_PHY_CFG_INPUT_FLAGS_FEC_CLAUSE74_ENABLE \
18475 * When set to 1, then the HWRM shall disable FEC CLAUSE 74 (Fire Code)
18476 * on this port if supported, by not advertising FEC CLAUSE 74 if
18477 * FEC autonegotiation is enabled or force disabled otherwise.
18478 * When set to 0, then this flag shall be ignored.
18479 * If FEC CLAUSE 74 is not supported, then the HWRM shall ignore this
18482 #define HWRM_PORT_PHY_CFG_INPUT_FLAGS_FEC_CLAUSE74_DISABLE \
18485 * When set to 1, then the HWRM shall enable FEC CLAUSE 91
18486 * (Reed Solomon RS(528,514) for NRZ) on this port if supported,
18487 * by advertising FEC RS(528,514) if FEC autonegotiation is enabled
18488 * or force enabled otherwise. In forced FEC mode, this flag
18489 * will only take effect if the speed is NRZ. Additional
18490 * RS544 or RS272 flags (also under clause 91) may be set for PAM4
18491 * in forced FEC mode.
18492 * When set to 0, then this flag shall be ignored.
18493 * If FEC RS(528,514) is not supported, then the HWRM shall ignore
18496 #define HWRM_PORT_PHY_CFG_INPUT_FLAGS_FEC_CLAUSE91_ENABLE \
18499 * When set to 1, then the HWRM shall disable FEC CLAUSE 91
18500 * (Reed Solomon RS(528,514) for NRZ) on this port if supported, by
18501 * not advertising RS(528,514) if FEC autonegotiation is enabled or
18502 * force disabled otherwise. When set to 0, then this flag shall be
18503 * ignored. If FEC RS(528,514) is not supported, then the HWRM
18504 * shall ignore this flag.
18506 #define HWRM_PORT_PHY_CFG_INPUT_FLAGS_FEC_CLAUSE91_DISABLE \
18509 * When this bit is set to '1', the link shall be forced to
18512 * # When this bit is set to '1", all other
18513 * command input settings related to the link speed shall
18515 * Once the link state is forced down, it can be
18516 * explicitly cleared from that state by setting this flag
18518 * # If this flag is set to '0', then the link shall be
18519 * cleared from forced down state if the link is in forced
18521 * There may be conditions (e.g. out-of-band or sideband
18522 * configuration changes for the link) outside the scope
18523 * of the HWRM implementation that may clear forced down
18526 #define HWRM_PORT_PHY_CFG_INPUT_FLAGS_FORCE_LINK_DWN \
18529 * When set to 1, then the HWRM shall enable FEC RS544_1XN
18530 * on this port if supported, by advertising FEC RS544_1XN if
18531 * FEC autonegotiation is enabled or force enabled otherwise.
18532 * In forced mode, this flag will only take effect if the speed is
18533 * PAM4. If this flag and fec_rs544_ieee_enable are set, the
18534 * HWRM shall choose one of the RS544 modes.
18535 * When set to 0, then this flag shall be ignored.
18536 * If FEC RS544_1XN is not supported, then the HWRM shall ignore this
18539 #define HWRM_PORT_PHY_CFG_INPUT_FLAGS_FEC_RS544_1XN_ENABLE \
18542 * When set to 1, then the HWRM shall disable FEC RS544_1XN
18543 * on this port if supported, by not advertising FEC RS544_1XN if
18544 * FEC autonegotiation is enabled or force disabled otherwise.
18545 * When set to 0, then this flag shall be ignored.
18546 * If FEC RS544_1XN is not supported, then the HWRM shall ignore this
18549 #define HWRM_PORT_PHY_CFG_INPUT_FLAGS_FEC_RS544_1XN_DISABLE \
18552 * When set to 1, then the HWRM shall enable FEC RS(544,514)
18553 * on this port if supported, by advertising FEC RS(544,514) if
18554 * FEC autonegotiation is enabled or force enabled otherwise.
18555 * In forced mode, this flag will only take effect if the speed is
18556 * PAM4. If this flag and fec_rs544_1xn_enable are set, the
18557 * HWRM shall choose one of the RS544 modes.
18558 * When set to 0, then this flag shall be ignored.
18559 * If FEC RS(544,514) is not supported, then the HWRM shall ignore
18562 #define HWRM_PORT_PHY_CFG_INPUT_FLAGS_FEC_RS544_IEEE_ENABLE \
18565 * When set to 1, then the HWRM shall disable FEC RS(544,514)
18566 * on this port if supported, by not advertising FEC RS(544,514) if
18567 * FEC autonegotiation is enabled or force disabled otherwise.
18568 * When set to 0, then this flag shall be ignored.
18569 * If FEC RS(544,514) is not supported, then the HWRM shall ignore
18572 #define HWRM_PORT_PHY_CFG_INPUT_FLAGS_FEC_RS544_IEEE_DISABLE \
18575 * When set to 1, then the HWRM shall enable FEC RS272_1XN
18576 * on this port if supported, by advertising FEC RS272_1XN if
18577 * FEC autonegotiation is enabled or force enabled otherwise.
18578 * In forced mode, this flag will only take effect if the speed is
18579 * PAM4. If this flag and fec_rs272_ieee_enable are set, the
18580 * HWRM shall choose one of the RS272 modes. Note that RS272
18581 * and RS544 modes cannot be set at the same time in forced FEC mode.
18582 * When set to 0, then this flag shall be ignored.
18583 * If FEC RS272_1XN is not supported, then the HWRM shall ignore this
18586 #define HWRM_PORT_PHY_CFG_INPUT_FLAGS_FEC_RS272_1XN_ENABLE \
18589 * When set to 1, then the HWRM shall disable FEC RS272_1XN
18590 * on this port if supported, by not advertising FEC RS272_1XN if
18591 * FEC autonegotiation is enabled or force disabled otherwise.
18592 * When set to 0, then this flag shall be ignored.
18593 * If FEC RS272_1XN is not supported, then the HWRM shall ignore
18596 #define HWRM_PORT_PHY_CFG_INPUT_FLAGS_FEC_RS272_1XN_DISABLE \
18599 * When set to 1, then the HWRM shall enable FEC RS(272,257)
18600 * on this port if supported, by advertising FEC RS(272,257) if
18601 * FEC autonegotiation is enabled or force enabled otherwise.
18602 * In forced mode, this flag will only take effect if the speed is
18603 * PAM4. If this flag and fec_rs272_1xn_enable are set, the
18604 * HWRM shall choose one of the RS272 modes. Note that RS272
18605 * and RS544 modes cannot be set at the same time in forced FEC mode.
18606 * When set to 0, then this flag shall be ignored.
18607 * If FEC RS(272,257) is not supported, then the HWRM shall ignore
18610 #define HWRM_PORT_PHY_CFG_INPUT_FLAGS_FEC_RS272_IEEE_ENABLE \
18613 * When set to 1, then the HWRM shall disable FEC RS(272,257)
18614 * on this port if supported, by not advertising FEC RS(272,257) if
18615 * FEC autonegotiation is enabled or force disabled otherwise.
18616 * When set to 0, then this flag shall be ignored.
18617 * If FEC RS(272,257) is not supported, then the HWRM shall ignore
18620 #define HWRM_PORT_PHY_CFG_INPUT_FLAGS_FEC_RS272_IEEE_DISABLE \
18624 * This bit must be '1' for the auto_mode field to be
18627 #define HWRM_PORT_PHY_CFG_INPUT_ENABLES_AUTO_MODE \
18630 * This bit must be '1' for the auto_duplex field to be
18633 #define HWRM_PORT_PHY_CFG_INPUT_ENABLES_AUTO_DUPLEX \
18636 * This bit must be '1' for the auto_pause field to be
18639 #define HWRM_PORT_PHY_CFG_INPUT_ENABLES_AUTO_PAUSE \
18642 * This bit must be '1' for the auto_link_speed field to be
18645 #define HWRM_PORT_PHY_CFG_INPUT_ENABLES_AUTO_LINK_SPEED \
18648 * This bit must be '1' for the auto_link_speed_mask field to be
18651 #define HWRM_PORT_PHY_CFG_INPUT_ENABLES_AUTO_LINK_SPEED_MASK \
18654 * This bit must be '1' for the wirespeed field to be
18657 #define HWRM_PORT_PHY_CFG_INPUT_ENABLES_WIRESPEED \
18660 * This bit must be '1' for the lpbk field to be
18663 #define HWRM_PORT_PHY_CFG_INPUT_ENABLES_LPBK \
18666 * This bit must be '1' for the preemphasis field to be
18669 #define HWRM_PORT_PHY_CFG_INPUT_ENABLES_PREEMPHASIS \
18672 * This bit must be '1' for the force_pause field to be
18675 #define HWRM_PORT_PHY_CFG_INPUT_ENABLES_FORCE_PAUSE \
18678 * This bit must be '1' for the eee_link_speed_mask field to be
18681 #define HWRM_PORT_PHY_CFG_INPUT_ENABLES_EEE_LINK_SPEED_MASK \
18684 * This bit must be '1' for the tx_lpi_timer field to be
18687 #define HWRM_PORT_PHY_CFG_INPUT_ENABLES_TX_LPI_TIMER \
18690 * This bit must be '1' for the force_pam4_link_speed field to be
18693 #define HWRM_PORT_PHY_CFG_INPUT_ENABLES_FORCE_PAM4_LINK_SPEED \
18696 * This bit must be '1' for the auto_pam4_link_speed_mask field to
18699 #define HWRM_PORT_PHY_CFG_INPUT_ENABLES_AUTO_PAM4_LINK_SPEED_MASK \
18701 /* Port ID of port that is to be configured. */
18704 * This is the speed that will be used if the force
18705 * bit is '1'. If unsupported speed is selected, an error
18706 * will be generated.
18708 uint16_t force_link_speed;
18709 /* 100Mb link speed */
18710 #define HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_100MB UINT32_C(0x1)
18711 /* 1Gb link speed */
18712 #define HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_1GB UINT32_C(0xa)
18713 /* 2Gb link speed */
18714 #define HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_2GB UINT32_C(0x14)
18715 /* 25Gb link speed */
18716 #define HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_2_5GB UINT32_C(0x19)
18717 /* 10Gb link speed */
18718 #define HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_10GB UINT32_C(0x64)
18719 /* 20Mb link speed */
18720 #define HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_20GB UINT32_C(0xc8)
18721 /* 25Gb link speed */
18722 #define HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_25GB UINT32_C(0xfa)
18723 /* 40Gb link speed */
18724 #define HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_40GB UINT32_C(0x190)
18725 /* 50Gb link speed */
18726 #define HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_50GB UINT32_C(0x1f4)
18727 /* 100Gb link speed */
18728 #define HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_100GB UINT32_C(0x3e8)
18729 /* 10Mb link speed */
18730 #define HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_10MB UINT32_C(0xffff)
18731 #define HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_LAST \
18732 HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_10MB
18734 * This value is used to identify what autoneg mode is
18735 * used when the link speed is not being forced.
18738 /* Disable autoneg or autoneg disabled. No speeds are selected. */
18739 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_MODE_NONE UINT32_C(0x0)
18740 /* Select all possible speeds for autoneg mode. */
18741 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_MODE_ALL_SPEEDS UINT32_C(0x1)
18743 * Select only the auto_link_speed speed for autoneg mode. This mode has
18744 * been DEPRECATED. An HWRM client should not use this mode.
18746 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_MODE_ONE_SPEED UINT32_C(0x2)
18748 * Select the auto_link_speed or any speed below that speed for autoneg.
18749 * This mode has been DEPRECATED. An HWRM client should not use this mode.
18751 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_MODE_ONE_OR_BELOW UINT32_C(0x3)
18753 * Select the speeds based on the corresponding link speed mask values
18754 * that are provided. The included speeds are specified in the
18755 * auto_link_speed and auto_pam4_link_speed fields.
18757 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_MODE_SPEED_MASK UINT32_C(0x4)
18758 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_MODE_LAST \
18759 HWRM_PORT_PHY_CFG_INPUT_AUTO_MODE_SPEED_MASK
18761 * This is the duplex setting that will be used if the autoneg_mode
18762 * is "one_speed" or "one_or_below".
18764 uint8_t auto_duplex;
18765 /* Half Duplex will be requested. */
18766 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_HALF UINT32_C(0x0)
18767 /* Full duplex will be requested. */
18768 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_FULL UINT32_C(0x1)
18769 /* Both Half and Full dupex will be requested. */
18770 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_BOTH UINT32_C(0x2)
18771 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_LAST \
18772 HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_BOTH
18774 * This value is used to configure the pause that will be
18775 * used for autonegotiation.
18776 * Add text on the usage of auto_pause and force_pause.
18778 uint8_t auto_pause;
18780 * When this bit is '1', Generation of tx pause messages
18781 * has been requested. Disabled otherwise.
18783 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_TX \
18786 * When this bit is '1', Reception of rx pause messages
18787 * has been requested. Disabled otherwise.
18789 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_RX \
18792 * When set to 1, the advertisement of pause is enabled.
18794 * # When the auto_mode is not set to none and this flag is
18795 * set to 1, then the auto_pause bits on this port are being
18796 * advertised and autoneg pause results are being interpreted.
18797 * # When the auto_mode is not set to none and this
18798 * flag is set to 0, the pause is forced as indicated in
18799 * force_pause, and also advertised as auto_pause bits, but
18800 * the autoneg results are not interpreted since the pause
18801 * configuration is being forced.
18802 * # When the auto_mode is set to none and this flag is set to
18803 * 1, auto_pause bits should be ignored and should be set to 0.
18805 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_AUTONEG_PAUSE \
18809 * This is the speed that will be used if the autoneg_mode
18810 * is "one_speed" or "one_or_below". If an unsupported speed
18811 * is selected, an error will be generated.
18813 uint16_t auto_link_speed;
18814 /* 100Mb link speed */
18815 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_100MB UINT32_C(0x1)
18816 /* 1Gb link speed */
18817 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_1GB UINT32_C(0xa)
18818 /* 2Gb link speed */
18819 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_2GB UINT32_C(0x14)
18820 /* 25Gb link speed */
18821 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_2_5GB UINT32_C(0x19)
18822 /* 10Gb link speed */
18823 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_10GB UINT32_C(0x64)
18824 /* 20Mb link speed */
18825 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_20GB UINT32_C(0xc8)
18826 /* 25Gb link speed */
18827 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_25GB UINT32_C(0xfa)
18828 /* 40Gb link speed */
18829 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_40GB UINT32_C(0x190)
18830 /* 50Gb link speed */
18831 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_50GB UINT32_C(0x1f4)
18832 /* 100Gb link speed */
18833 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_100GB UINT32_C(0x3e8)
18834 /* 10Mb link speed */
18835 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_10MB UINT32_C(0xffff)
18836 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_LAST \
18837 HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_10MB
18839 * This is a mask of link speeds that will be used if
18840 * autoneg_mode is "mask". If unsupported speed is enabled
18841 * an error will be generated.
18843 uint16_t auto_link_speed_mask;
18844 /* 100Mb link speed (Half-duplex) */
18845 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_100MBHD \
18847 /* 100Mb link speed (Full-duplex) */
18848 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_100MB \
18850 /* 1Gb link speed (Half-duplex) */
18851 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_1GBHD \
18853 /* 1Gb link speed (Full-duplex) */
18854 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_1GB \
18856 /* 2Gb link speed */
18857 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_2GB \
18859 /* 25Gb link speed */
18860 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_2_5GB \
18862 /* 10Gb link speed */
18863 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_10GB \
18865 /* 20Gb link speed */
18866 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_20GB \
18868 /* 25Gb link speed */
18869 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_25GB \
18871 /* 40Gb link speed */
18872 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_40GB \
18874 /* 50Gb link speed */
18875 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_50GB \
18877 /* 100Gb link speed */
18878 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_100GB \
18880 /* 10Mb link speed (Half-duplex) */
18881 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_10MBHD \
18883 /* 10Mb link speed (Full-duplex) */
18884 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_10MB \
18886 /* This value controls the wirespeed feature. */
18888 /* Wirespeed feature is disabled. */
18889 #define HWRM_PORT_PHY_CFG_INPUT_WIRESPEED_OFF UINT32_C(0x0)
18890 /* Wirespeed feature is enabled. */
18891 #define HWRM_PORT_PHY_CFG_INPUT_WIRESPEED_ON UINT32_C(0x1)
18892 #define HWRM_PORT_PHY_CFG_INPUT_WIRESPEED_LAST \
18893 HWRM_PORT_PHY_CFG_INPUT_WIRESPEED_ON
18894 /* This value controls the loopback setting for the PHY. */
18896 /* No loopback is selected. Normal operation. */
18897 #define HWRM_PORT_PHY_CFG_INPUT_LPBK_NONE UINT32_C(0x0)
18899 * The HW will be configured with local loopback such that
18900 * host data is sent back to the host without modification.
18902 #define HWRM_PORT_PHY_CFG_INPUT_LPBK_LOCAL UINT32_C(0x1)
18904 * The HW will be configured with remote loopback such that
18905 * port logic will send packets back out the transmitter that
18908 #define HWRM_PORT_PHY_CFG_INPUT_LPBK_REMOTE UINT32_C(0x2)
18910 * The HW will be configured with external loopback such that
18911 * host data is sent on the transmitter and based on the external
18912 * loopback connection the data will be received without modification.
18914 #define HWRM_PORT_PHY_CFG_INPUT_LPBK_EXTERNAL UINT32_C(0x3)
18915 #define HWRM_PORT_PHY_CFG_INPUT_LPBK_LAST \
18916 HWRM_PORT_PHY_CFG_INPUT_LPBK_EXTERNAL
18918 * This value is used to configure the pause that will be
18919 * used for force mode.
18921 uint8_t force_pause;
18923 * When this bit is '1', Generation of tx pause messages
18924 * is supported. Disabled otherwise.
18926 #define HWRM_PORT_PHY_CFG_INPUT_FORCE_PAUSE_TX UINT32_C(0x1)
18928 * When this bit is '1', Reception of rx pause messages
18929 * is supported. Disabled otherwise.
18931 #define HWRM_PORT_PHY_CFG_INPUT_FORCE_PAUSE_RX UINT32_C(0x2)
18934 * This value controls the pre-emphasis to be used for the
18935 * link. Driver should not set this value (use
18936 * enable.preemphasis = 0) unless driver is sure of setting.
18937 * Normally HWRM FW will determine proper pre-emphasis.
18939 uint32_t preemphasis;
18941 * Setting for link speed mask that is used to
18942 * advertise speeds during autonegotiation when EEE is enabled.
18943 * This field is valid only when EEE is enabled.
18944 * The speeds specified in this field shall be a subset of
18945 * speeds specified in auto_link_speed_mask.
18946 * If EEE is enabled,then at least one speed shall be provided
18949 uint16_t eee_link_speed_mask;
18951 #define HWRM_PORT_PHY_CFG_INPUT_EEE_LINK_SPEED_MASK_RSVD1 \
18953 /* 100Mb link speed (Full-duplex) */
18954 #define HWRM_PORT_PHY_CFG_INPUT_EEE_LINK_SPEED_MASK_100MB \
18957 #define HWRM_PORT_PHY_CFG_INPUT_EEE_LINK_SPEED_MASK_RSVD2 \
18959 /* 1Gb link speed (Full-duplex) */
18960 #define HWRM_PORT_PHY_CFG_INPUT_EEE_LINK_SPEED_MASK_1GB \
18963 #define HWRM_PORT_PHY_CFG_INPUT_EEE_LINK_SPEED_MASK_RSVD3 \
18966 #define HWRM_PORT_PHY_CFG_INPUT_EEE_LINK_SPEED_MASK_RSVD4 \
18968 /* 10Gb link speed */
18969 #define HWRM_PORT_PHY_CFG_INPUT_EEE_LINK_SPEED_MASK_10GB \
18972 * This is the speed that will be used if the force and force_pam4
18973 * bits are '1'. If unsupported speed is selected, an error
18974 * will be generated.
18976 uint16_t force_pam4_link_speed;
18977 /* 50Gb link speed */
18978 #define HWRM_PORT_PHY_CFG_INPUT_FORCE_PAM4_LINK_SPEED_50GB \
18980 /* 100Gb link speed */
18981 #define HWRM_PORT_PHY_CFG_INPUT_FORCE_PAM4_LINK_SPEED_100GB \
18983 /* 200Gb link speed */
18984 #define HWRM_PORT_PHY_CFG_INPUT_FORCE_PAM4_LINK_SPEED_200GB \
18986 #define HWRM_PORT_PHY_CFG_INPUT_FORCE_PAM4_LINK_SPEED_LAST \
18987 HWRM_PORT_PHY_CFG_INPUT_FORCE_PAM4_LINK_SPEED_200GB
18989 * Requested setting of TX LPI timer in microseconds.
18990 * This field is valid only when EEE is enabled and TX LPI is
18993 uint32_t tx_lpi_timer;
18994 #define HWRM_PORT_PHY_CFG_INPUT_TX_LPI_TIMER_MASK UINT32_C(0xffffff)
18995 #define HWRM_PORT_PHY_CFG_INPUT_TX_LPI_TIMER_SFT 0
18996 /* This field specifies which PAM4 speeds are enabled for auto mode. */
18997 uint16_t auto_link_pam4_speed_mask;
18998 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_PAM4_SPEED_MASK_50G \
19000 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_PAM4_SPEED_MASK_100G \
19002 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_PAM4_SPEED_MASK_200G \
19004 uint8_t unused_2[2];
19007 /* hwrm_port_phy_cfg_output (size:128b/16B) */
19008 struct hwrm_port_phy_cfg_output {
19009 /* The specific error status for the command. */
19010 uint16_t error_code;
19011 /* The HWRM command request type. */
19013 /* The sequence ID from the original command. */
19015 /* The length of the response data in number of bytes. */
19017 uint8_t unused_0[7];
19019 * This field is used in Output records to indicate that the output
19020 * is completely written to RAM. This field should be read as '1'
19021 * to indicate that the output has been completely written.
19022 * When writing a command completion or response to an internal processor,
19023 * the order of writes has to be such that this field is written last.
19028 /* hwrm_port_phy_cfg_cmd_err (size:64b/8B) */
19029 struct hwrm_port_phy_cfg_cmd_err {
19031 * command specific error codes that goes to
19032 * the cmd_err field in Common HWRM Error Response.
19035 /* Unknown error */
19036 #define HWRM_PORT_PHY_CFG_CMD_ERR_CODE_UNKNOWN UINT32_C(0x0)
19037 /* Unable to complete operation due to invalid speed */
19038 #define HWRM_PORT_PHY_CFG_CMD_ERR_CODE_ILLEGAL_SPEED UINT32_C(0x1)
19040 * retry the command since the phy is not ready.
19041 * retry count is returned in opaque_0.
19042 * This is only valid for the first command and
19043 * this value will not change for successive calls.
19044 * but if a 0 is returned at any time then this should
19045 * be treated as an un recoverable failure,
19047 * retry interval in milli seconds is returned in opaque_1.
19048 * This specifies the time that user should wait before
19049 * issuing the next port_phy_cfg command.
19051 #define HWRM_PORT_PHY_CFG_CMD_ERR_CODE_RETRY UINT32_C(0x2)
19052 #define HWRM_PORT_PHY_CFG_CMD_ERR_CODE_LAST \
19053 HWRM_PORT_PHY_CFG_CMD_ERR_CODE_RETRY
19054 uint8_t unused_0[7];
19057 /**********************
19058 * hwrm_port_phy_qcfg *
19059 **********************/
19062 /* hwrm_port_phy_qcfg_input (size:192b/24B) */
19063 struct hwrm_port_phy_qcfg_input {
19064 /* The HWRM command request type. */
19067 * The completion ring to send the completion event on. This should
19068 * be the NQ ID returned from the `nq_alloc` HWRM command.
19070 uint16_t cmpl_ring;
19072 * The sequence ID is used by the driver for tracking multiple
19073 * commands. This ID is treated as opaque data by the firmware and
19074 * the value is returned in the `hwrm_resp_hdr` upon completion.
19078 * The target ID of the command:
19079 * * 0x0-0xFFF8 - The function ID
19080 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
19081 * * 0xFFFD - Reserved for user-space HWRM interface
19084 uint16_t target_id;
19086 * A physical address pointer pointing to a host buffer that the
19087 * command's response data will be written. This can be either a host
19088 * physical address (HPA) or a guest physical address (GPA) and must
19089 * point to a physically contiguous block of memory.
19091 uint64_t resp_addr;
19092 /* Port ID of port that is to be queried. */
19094 uint8_t unused_0[6];
19097 /* hwrm_port_phy_qcfg_output (size:768b/96B) */
19098 struct hwrm_port_phy_qcfg_output {
19099 /* The specific error status for the command. */
19100 uint16_t error_code;
19101 /* The HWRM command request type. */
19103 /* The sequence ID from the original command. */
19105 /* The length of the response data in number of bytes. */
19107 /* This value indicates the current link status. */
19109 /* There is no link or cable detected. */
19110 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_NO_LINK UINT32_C(0x0)
19111 /* There is no link, but a cable has been detected. */
19112 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SIGNAL UINT32_C(0x1)
19113 /* There is a link. */
19114 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_LINK UINT32_C(0x2)
19115 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_LAST \
19116 HWRM_PORT_PHY_QCFG_OUTPUT_LINK_LINK
19117 uint8_t active_fec_signal_mode;
19119 * This value indicates the current link signaling mode of the
19122 #define HWRM_PORT_PHY_QCFG_OUTPUT_SIGNAL_MODE_MASK \
19124 #define HWRM_PORT_PHY_QCFG_OUTPUT_SIGNAL_MODE_SFT 0
19125 /* NRZ signaling */
19126 #define HWRM_PORT_PHY_QCFG_OUTPUT_SIGNAL_MODE_NRZ \
19128 /* PAM4 signaling */
19129 #define HWRM_PORT_PHY_QCFG_OUTPUT_SIGNAL_MODE_PAM4 \
19131 #define HWRM_PORT_PHY_QCFG_OUTPUT_SIGNAL_MODE_LAST \
19132 HWRM_PORT_PHY_QCFG_OUTPUT_SIGNAL_MODE_PAM4
19133 /* This value indicates the current active FEC mode. */
19134 #define HWRM_PORT_PHY_QCFG_OUTPUT_ACTIVE_FEC_MASK \
19136 #define HWRM_PORT_PHY_QCFG_OUTPUT_ACTIVE_FEC_SFT 4
19137 /* No active FEC */
19138 #define HWRM_PORT_PHY_QCFG_OUTPUT_ACTIVE_FEC_FEC_NONE_ACTIVE \
19139 (UINT32_C(0x0) << 4)
19140 /* FEC CLAUSE 74 (Fire Code) active, autonegotiated or forced. */
19141 #define HWRM_PORT_PHY_QCFG_OUTPUT_ACTIVE_FEC_FEC_CLAUSE74_ACTIVE \
19142 (UINT32_C(0x1) << 4)
19143 /* FEC CLAUSE 91 RS(528,514) active, autonegoatiated or forced. */
19144 #define HWRM_PORT_PHY_QCFG_OUTPUT_ACTIVE_FEC_FEC_CLAUSE91_ACTIVE \
19145 (UINT32_C(0x2) << 4)
19146 /* FEC RS544_1XN active, autonegoatiated or forced. */
19147 #define HWRM_PORT_PHY_QCFG_OUTPUT_ACTIVE_FEC_FEC_RS544_1XN_ACTIVE \
19148 (UINT32_C(0x3) << 4)
19149 /* FEC RS(544,528) active, autonegoatiated or forced. */
19150 #define HWRM_PORT_PHY_QCFG_OUTPUT_ACTIVE_FEC_FEC_RS544_IEEE_ACTIVE \
19151 (UINT32_C(0x4) << 4)
19152 /* FEC RS272_1XN active, autonegotiated or forced. */
19153 #define HWRM_PORT_PHY_QCFG_OUTPUT_ACTIVE_FEC_FEC_RS272_1XN_ACTIVE \
19154 (UINT32_C(0x5) << 4)
19155 /* FEC RS(272,257) active, autonegoatiated or forced. */
19156 #define HWRM_PORT_PHY_QCFG_OUTPUT_ACTIVE_FEC_FEC_RS272_IEEE_ACTIVE \
19157 (UINT32_C(0x6) << 4)
19158 #define HWRM_PORT_PHY_QCFG_OUTPUT_ACTIVE_FEC_LAST \
19159 HWRM_PORT_PHY_QCFG_OUTPUT_ACTIVE_FEC_FEC_RS272_IEEE_ACTIVE
19161 * This value indicates the current link speed of the connection.
19162 * The signal_mode field indicates if the link is using
19163 * NRZ or PAM4 signaling.
19165 uint16_t link_speed;
19166 /* 100Mb link speed */
19167 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_100MB UINT32_C(0x1)
19168 /* 1Gb link speed */
19169 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_1GB UINT32_C(0xa)
19170 /* 2Gb link speed */
19171 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_2GB UINT32_C(0x14)
19172 /* 25Gb link speed */
19173 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_2_5GB UINT32_C(0x19)
19174 /* 10Gb link speed */
19175 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_10GB UINT32_C(0x64)
19176 /* 20Mb link speed */
19177 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_20GB UINT32_C(0xc8)
19178 /* 25Gb link speed */
19179 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_25GB UINT32_C(0xfa)
19180 /* 40Gb link speed */
19181 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_40GB UINT32_C(0x190)
19182 /* 50Gb link speed */
19183 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_50GB UINT32_C(0x1f4)
19184 /* 100Gb link speed */
19185 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_100GB UINT32_C(0x3e8)
19186 /* 200Gb link speed */
19187 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_200GB UINT32_C(0x7d0)
19188 /* 10Mb link speed */
19189 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_10MB UINT32_C(0xffff)
19190 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_LAST \
19191 HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_10MB
19193 * This value is indicates the duplex of the current
19196 uint8_t duplex_cfg;
19197 /* Half Duplex connection. */
19198 #define HWRM_PORT_PHY_QCFG_OUTPUT_DUPLEX_CFG_HALF UINT32_C(0x0)
19199 /* Full duplex connection. */
19200 #define HWRM_PORT_PHY_QCFG_OUTPUT_DUPLEX_CFG_FULL UINT32_C(0x1)
19201 #define HWRM_PORT_PHY_QCFG_OUTPUT_DUPLEX_CFG_LAST \
19202 HWRM_PORT_PHY_QCFG_OUTPUT_DUPLEX_CFG_FULL
19204 * This value is used to indicate the current
19205 * pause configuration. When autoneg is enabled, this value
19206 * represents the autoneg results of pause configuration.
19210 * When this bit is '1', Generation of tx pause messages
19211 * is supported. Disabled otherwise.
19213 #define HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_TX UINT32_C(0x1)
19215 * When this bit is '1', Reception of rx pause messages
19216 * is supported. Disabled otherwise.
19218 #define HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_RX UINT32_C(0x2)
19220 * The supported speeds for the port. This is a bit mask.
19221 * For each speed that is supported, the corresponding
19222 * bit will be set to '1'.
19224 uint16_t support_speeds;
19225 /* 100Mb link speed (Half-duplex) */
19226 #define HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_100MBHD \
19228 /* 100Mb link speed (Full-duplex) */
19229 #define HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_100MB \
19231 /* 1Gb link speed (Half-duplex) */
19232 #define HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_1GBHD \
19234 /* 1Gb link speed (Full-duplex) */
19235 #define HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_1GB \
19237 /* 2Gb link speed */
19238 #define HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_2GB \
19240 /* 25Gb link speed */
19241 #define HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_2_5GB \
19243 /* 10Gb link speed */
19244 #define HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_10GB \
19246 /* 20Gb link speed */
19247 #define HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_20GB \
19249 /* 25Gb link speed */
19250 #define HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_25GB \
19252 /* 40Gb link speed */
19253 #define HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_40GB \
19255 /* 50Gb link speed */
19256 #define HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_50GB \
19258 /* 100Gb link speed */
19259 #define HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_100GB \
19261 /* 10Mb link speed (Half-duplex) */
19262 #define HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_10MBHD \
19264 /* 10Mb link speed (Full-duplex) */
19265 #define HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_10MB \
19268 * Current setting of forced link speed.
19269 * When the link speed is not being forced, this
19270 * value shall be set to 0.
19272 uint16_t force_link_speed;
19273 /* 100Mb link speed */
19274 #define HWRM_PORT_PHY_QCFG_OUTPUT_FORCE_LINK_SPEED_100MB UINT32_C(0x1)
19275 /* 1Gb link speed */
19276 #define HWRM_PORT_PHY_QCFG_OUTPUT_FORCE_LINK_SPEED_1GB UINT32_C(0xa)
19277 /* 2Gb link speed */
19278 #define HWRM_PORT_PHY_QCFG_OUTPUT_FORCE_LINK_SPEED_2GB UINT32_C(0x14)
19279 /* 25Gb link speed */
19280 #define HWRM_PORT_PHY_QCFG_OUTPUT_FORCE_LINK_SPEED_2_5GB UINT32_C(0x19)
19281 /* 10Gb link speed */
19282 #define HWRM_PORT_PHY_QCFG_OUTPUT_FORCE_LINK_SPEED_10GB UINT32_C(0x64)
19283 /* 20Mb link speed */
19284 #define HWRM_PORT_PHY_QCFG_OUTPUT_FORCE_LINK_SPEED_20GB UINT32_C(0xc8)
19285 /* 25Gb link speed */
19286 #define HWRM_PORT_PHY_QCFG_OUTPUT_FORCE_LINK_SPEED_25GB UINT32_C(0xfa)
19287 /* 40Gb link speed */
19288 #define HWRM_PORT_PHY_QCFG_OUTPUT_FORCE_LINK_SPEED_40GB \
19290 /* 50Gb link speed */
19291 #define HWRM_PORT_PHY_QCFG_OUTPUT_FORCE_LINK_SPEED_50GB \
19293 /* 100Gb link speed */
19294 #define HWRM_PORT_PHY_QCFG_OUTPUT_FORCE_LINK_SPEED_100GB \
19296 /* 10Mb link speed */
19297 #define HWRM_PORT_PHY_QCFG_OUTPUT_FORCE_LINK_SPEED_10MB \
19299 #define HWRM_PORT_PHY_QCFG_OUTPUT_FORCE_LINK_SPEED_LAST \
19300 HWRM_PORT_PHY_QCFG_OUTPUT_FORCE_LINK_SPEED_10MB
19301 /* Current setting of auto negotiation mode. */
19303 /* Disable autoneg or autoneg disabled. No speeds are selected. */
19304 #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_MODE_NONE UINT32_C(0x0)
19305 /* Select all possible speeds for autoneg mode. */
19306 #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_MODE_ALL_SPEEDS UINT32_C(0x1)
19308 * Select only the auto_link_speed speed for autoneg mode. This mode has
19309 * been DEPRECATED. An HWRM client should not use this mode.
19311 #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_MODE_ONE_SPEED UINT32_C(0x2)
19313 * Select the auto_link_speed or any speed below that speed for autoneg.
19314 * This mode has been DEPRECATED. An HWRM client should not use this mode.
19316 #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_MODE_ONE_OR_BELOW UINT32_C(0x3)
19318 * Select the speeds based on the corresponding link speed mask value
19319 * that is provided.
19321 #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_MODE_SPEED_MASK UINT32_C(0x4)
19322 #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_MODE_LAST \
19323 HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_MODE_SPEED_MASK
19325 * Current setting of pause autonegotiation.
19326 * Move autoneg_pause flag here.
19328 uint8_t auto_pause;
19330 * When this bit is '1', Generation of tx pause messages
19331 * has been requested. Disabled otherwise.
19333 #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_PAUSE_TX \
19336 * When this bit is '1', Reception of rx pause messages
19337 * has been requested. Disabled otherwise.
19339 #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_PAUSE_RX \
19342 * When set to 1, the advertisement of pause is enabled.
19344 * # When the auto_mode is not set to none and this flag is
19345 * set to 1, then the auto_pause bits on this port are being
19346 * advertised and autoneg pause results are being interpreted.
19347 * # When the auto_mode is not set to none and this
19348 * flag is set to 0, the pause is forced as indicated in
19349 * force_pause, and also advertised as auto_pause bits, but
19350 * the autoneg results are not interpreted since the pause
19351 * configuration is being forced.
19352 * # When the auto_mode is set to none and this flag is set to
19353 * 1, auto_pause bits should be ignored and should be set to 0.
19355 #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_PAUSE_AUTONEG_PAUSE \
19358 * Current setting for auto_link_speed. This field is only
19359 * valid when auto_mode is set to "one_speed" or "one_or_below".
19361 uint16_t auto_link_speed;
19362 /* 100Mb link speed */
19363 #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_100MB UINT32_C(0x1)
19364 /* 1Gb link speed */
19365 #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_1GB UINT32_C(0xa)
19366 /* 2Gb link speed */
19367 #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_2GB UINT32_C(0x14)
19368 /* 25Gb link speed */
19369 #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_2_5GB UINT32_C(0x19)
19370 /* 10Gb link speed */
19371 #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_10GB UINT32_C(0x64)
19372 /* 20Mb link speed */
19373 #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_20GB UINT32_C(0xc8)
19374 /* 25Gb link speed */
19375 #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_25GB UINT32_C(0xfa)
19376 /* 40Gb link speed */
19377 #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_40GB UINT32_C(0x190)
19378 /* 50Gb link speed */
19379 #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_50GB UINT32_C(0x1f4)
19380 /* 100Gb link speed */
19381 #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_100GB UINT32_C(0x3e8)
19382 /* 10Mb link speed */
19383 #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_10MB \
19385 #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_LAST \
19386 HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_10MB
19388 * Current setting for auto_link_speed_mask that is used to
19389 * advertise speeds during autonegotiation.
19390 * This field is only valid when auto_mode is set to "mask".
19391 * The speeds specified in this field shall be a subset of
19392 * supported speeds on this port.
19394 uint16_t auto_link_speed_mask;
19395 /* 100Mb link speed (Half-duplex) */
19396 #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_MASK_100MBHD \
19398 /* 100Mb link speed (Full-duplex) */
19399 #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_MASK_100MB \
19401 /* 1Gb link speed (Half-duplex) */
19402 #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_MASK_1GBHD \
19404 /* 1Gb link speed (Full-duplex) */
19405 #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_MASK_1GB \
19407 /* 2Gb link speed */
19408 #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_MASK_2GB \
19410 /* 25Gb link speed */
19411 #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_MASK_2_5GB \
19413 /* 10Gb link speed */
19414 #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_MASK_10GB \
19416 /* 20Gb link speed */
19417 #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_MASK_20GB \
19419 /* 25Gb link speed */
19420 #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_MASK_25GB \
19422 /* 40Gb link speed */
19423 #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_MASK_40GB \
19425 /* 50Gb link speed */
19426 #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_MASK_50GB \
19428 /* 100Gb link speed */
19429 #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_MASK_100GB \
19431 /* 10Mb link speed (Half-duplex) */
19432 #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_MASK_10MBHD \
19434 /* 10Mb link speed (Full-duplex) */
19435 #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_MASK_10MB \
19437 /* Current setting for wirespeed. */
19439 /* Wirespeed feature is disabled. */
19440 #define HWRM_PORT_PHY_QCFG_OUTPUT_WIRESPEED_OFF UINT32_C(0x0)
19441 /* Wirespeed feature is enabled. */
19442 #define HWRM_PORT_PHY_QCFG_OUTPUT_WIRESPEED_ON UINT32_C(0x1)
19443 #define HWRM_PORT_PHY_QCFG_OUTPUT_WIRESPEED_LAST \
19444 HWRM_PORT_PHY_QCFG_OUTPUT_WIRESPEED_ON
19445 /* Current setting for loopback. */
19447 /* No loopback is selected. Normal operation. */
19448 #define HWRM_PORT_PHY_QCFG_OUTPUT_LPBK_NONE UINT32_C(0x0)
19450 * The HW will be configured with local loopback such that
19451 * host data is sent back to the host without modification.
19453 #define HWRM_PORT_PHY_QCFG_OUTPUT_LPBK_LOCAL UINT32_C(0x1)
19455 * The HW will be configured with remote loopback such that
19456 * port logic will send packets back out the transmitter that
19459 #define HWRM_PORT_PHY_QCFG_OUTPUT_LPBK_REMOTE UINT32_C(0x2)
19461 * The HW will be configured with external loopback such that
19462 * host data is sent on the transmitter and based on the external
19463 * loopback connection the data will be received without modification.
19465 #define HWRM_PORT_PHY_QCFG_OUTPUT_LPBK_EXTERNAL UINT32_C(0x3)
19466 #define HWRM_PORT_PHY_QCFG_OUTPUT_LPBK_LAST \
19467 HWRM_PORT_PHY_QCFG_OUTPUT_LPBK_EXTERNAL
19469 * Current setting of forced pause.
19470 * When the pause configuration is not being forced, then
19471 * this value shall be set to 0.
19473 uint8_t force_pause;
19475 * When this bit is '1', Generation of tx pause messages
19476 * is supported. Disabled otherwise.
19478 #define HWRM_PORT_PHY_QCFG_OUTPUT_FORCE_PAUSE_TX UINT32_C(0x1)
19480 * When this bit is '1', Reception of rx pause messages
19481 * is supported. Disabled otherwise.
19483 #define HWRM_PORT_PHY_QCFG_OUTPUT_FORCE_PAUSE_RX UINT32_C(0x2)
19485 * This value indicates the current status of the optics module on
19488 uint8_t module_status;
19489 /* Module is inserted and accepted */
19490 #define HWRM_PORT_PHY_QCFG_OUTPUT_MODULE_STATUS_NONE \
19492 /* Module is rejected and transmit side Laser is disabled. */
19493 #define HWRM_PORT_PHY_QCFG_OUTPUT_MODULE_STATUS_DISABLETX \
19495 /* Module mismatch warning. */
19496 #define HWRM_PORT_PHY_QCFG_OUTPUT_MODULE_STATUS_WARNINGMSG \
19498 /* Module is rejected and powered down. */
19499 #define HWRM_PORT_PHY_QCFG_OUTPUT_MODULE_STATUS_PWRDOWN \
19501 /* Module is not inserted. */
19502 #define HWRM_PORT_PHY_QCFG_OUTPUT_MODULE_STATUS_NOTINSERTED \
19504 /* Module is powered down because of over current fault. */
19505 #define HWRM_PORT_PHY_QCFG_OUTPUT_MODULE_STATUS_CURRENTFAULT \
19507 /* Module status is not applicable. */
19508 #define HWRM_PORT_PHY_QCFG_OUTPUT_MODULE_STATUS_NOTAPPLICABLE \
19510 #define HWRM_PORT_PHY_QCFG_OUTPUT_MODULE_STATUS_LAST \
19511 HWRM_PORT_PHY_QCFG_OUTPUT_MODULE_STATUS_NOTAPPLICABLE
19512 /* Current setting for preemphasis. */
19513 uint32_t preemphasis;
19514 /* This field represents the major version of the PHY. */
19516 /* This field represents the minor version of the PHY. */
19518 /* This field represents the build version of the PHY. */
19520 /* This value represents a PHY type. */
19523 #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_UNKNOWN \
19526 #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_BASECR \
19528 /* BASE-KR4 (Deprecated) */
19529 #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_BASEKR4 \
19532 #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_BASELR \
19535 #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_BASESR \
19537 /* BASE-KR2 (Deprecated) */
19538 #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_BASEKR2 \
19541 #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_BASEKX \
19544 #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_BASEKR \
19547 #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_BASET \
19549 /* EEE capable BASE-T */
19550 #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_BASETE \
19552 /* SGMII connected external PHY */
19553 #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_SGMIIEXTPHY \
19555 /* 25G_BASECR_CA_L */
19556 #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_25G_BASECR_CA_L \
19558 /* 25G_BASECR_CA_S */
19559 #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_25G_BASECR_CA_S \
19561 /* 25G_BASECR_CA_N */
19562 #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_25G_BASECR_CA_N \
19565 #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_25G_BASESR \
19568 #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_100G_BASECR4 \
19571 #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_100G_BASESR4 \
19574 #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_100G_BASELR4 \
19577 #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_100G_BASEER4 \
19579 /* 100G_BASESR10 */
19580 #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_100G_BASESR10 \
19583 #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_40G_BASECR4 \
19586 #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_40G_BASESR4 \
19589 #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_40G_BASELR4 \
19592 #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_40G_BASEER4 \
19594 /* 40G_ACTIVE_CABLE */
19595 #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_40G_ACTIVE_CABLE \
19598 #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_1G_BASET \
19601 #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_1G_BASESX \
19604 #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_1G_BASECX \
19607 #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_200G_BASECR4 \
19610 #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_200G_BASESR4 \
19613 #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_200G_BASELR4 \
19616 #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_200G_BASEER4 \
19618 #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_LAST \
19619 HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_200G_BASEER4
19620 /* This value represents a media type. */
19621 uint8_t media_type;
19623 #define HWRM_PORT_PHY_QCFG_OUTPUT_MEDIA_TYPE_UNKNOWN UINT32_C(0x0)
19625 #define HWRM_PORT_PHY_QCFG_OUTPUT_MEDIA_TYPE_TP UINT32_C(0x1)
19626 /* Direct Attached Copper */
19627 #define HWRM_PORT_PHY_QCFG_OUTPUT_MEDIA_TYPE_DAC UINT32_C(0x2)
19629 #define HWRM_PORT_PHY_QCFG_OUTPUT_MEDIA_TYPE_FIBRE UINT32_C(0x3)
19630 #define HWRM_PORT_PHY_QCFG_OUTPUT_MEDIA_TYPE_LAST \
19631 HWRM_PORT_PHY_QCFG_OUTPUT_MEDIA_TYPE_FIBRE
19632 /* This value represents a transceiver type. */
19633 uint8_t xcvr_pkg_type;
19634 /* PHY and MAC are in the same package */
19635 #define HWRM_PORT_PHY_QCFG_OUTPUT_XCVR_PKG_TYPE_XCVR_INTERNAL \
19637 /* PHY and MAC are in different packages */
19638 #define HWRM_PORT_PHY_QCFG_OUTPUT_XCVR_PKG_TYPE_XCVR_EXTERNAL \
19640 #define HWRM_PORT_PHY_QCFG_OUTPUT_XCVR_PKG_TYPE_LAST \
19641 HWRM_PORT_PHY_QCFG_OUTPUT_XCVR_PKG_TYPE_XCVR_EXTERNAL
19642 uint8_t eee_config_phy_addr;
19643 /* This field represents PHY address. */
19644 #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_ADDR_MASK \
19646 #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_ADDR_SFT 0
19648 * This field represents flags related to EEE configuration.
19649 * These EEE configuration flags are valid only when the
19650 * auto_mode is not set to none (in other words autonegotiation
19653 #define HWRM_PORT_PHY_QCFG_OUTPUT_EEE_CONFIG_MASK \
19655 #define HWRM_PORT_PHY_QCFG_OUTPUT_EEE_CONFIG_SFT 5
19657 * When set to 1, Energy Efficient Ethernet (EEE) mode is enabled.
19658 * Speeds for autoneg with EEE mode enabled
19659 * are based on eee_link_speed_mask.
19661 #define HWRM_PORT_PHY_QCFG_OUTPUT_EEE_CONFIG_EEE_ENABLED \
19664 * This flag is valid only when eee_enabled is set to 1.
19666 * # If eee_enabled is set to 0, then EEE mode is disabled
19667 * and this flag shall be ignored.
19668 * # If eee_enabled is set to 1 and this flag is set to 1,
19669 * then Energy Efficient Ethernet (EEE) mode is enabled
19671 * # If eee_enabled is set to 1 and this flag is set to 0,
19672 * then Energy Efficient Ethernet (EEE) mode is enabled
19673 * but is currently not in use.
19675 #define HWRM_PORT_PHY_QCFG_OUTPUT_EEE_CONFIG_EEE_ACTIVE \
19678 * This flag is valid only when eee_enabled is set to 1.
19680 * # If eee_enabled is set to 0, then EEE mode is disabled
19681 * and this flag shall be ignored.
19682 * # If eee_enabled is set to 1 and this flag is set to 1,
19683 * then Energy Efficient Ethernet (EEE) mode is enabled
19684 * and TX LPI is enabled.
19685 * # If eee_enabled is set to 1 and this flag is set to 0,
19686 * then Energy Efficient Ethernet (EEE) mode is enabled
19687 * but TX LPI is disabled.
19689 #define HWRM_PORT_PHY_QCFG_OUTPUT_EEE_CONFIG_EEE_TX_LPI \
19692 * When set to 1, the parallel detection is used to determine
19693 * the speed of the link partner.
19695 * Parallel detection is used when a autonegotiation capable
19696 * device is connected to a link parter that is not capable
19697 * of autonegotiation.
19699 uint8_t parallel_detect;
19701 * When set to 1, the parallel detection is used to determine
19702 * the speed of the link partner.
19704 * Parallel detection is used when a autonegotiation capable
19705 * device is connected to a link parter that is not capable
19706 * of autonegotiation.
19708 #define HWRM_PORT_PHY_QCFG_OUTPUT_PARALLEL_DETECT UINT32_C(0x1)
19710 * The advertised speeds for the port by the link partner.
19711 * Each advertised speed will be set to '1'.
19713 uint16_t link_partner_adv_speeds;
19714 /* 100Mb link speed (Half-duplex) */
19715 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_SPEEDS_100MBHD \
19717 /* 100Mb link speed (Full-duplex) */
19718 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_SPEEDS_100MB \
19720 /* 1Gb link speed (Half-duplex) */
19721 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_SPEEDS_1GBHD \
19723 /* 1Gb link speed (Full-duplex) */
19724 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_SPEEDS_1GB \
19726 /* 2Gb link speed */
19727 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_SPEEDS_2GB \
19729 /* 25Gb link speed */
19730 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_SPEEDS_2_5GB \
19732 /* 10Gb link speed */
19733 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_SPEEDS_10GB \
19735 /* 20Gb link speed */
19736 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_SPEEDS_20GB \
19738 /* 25Gb link speed */
19739 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_SPEEDS_25GB \
19741 /* 40Gb link speed */
19742 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_SPEEDS_40GB \
19744 /* 50Gb link speed */
19745 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_SPEEDS_50GB \
19747 /* 100Gb link speed */
19748 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_SPEEDS_100GB \
19750 /* 10Mb link speed (Half-duplex) */
19751 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_SPEEDS_10MBHD \
19753 /* 10Mb link speed (Full-duplex) */
19754 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_SPEEDS_10MB \
19757 * The advertised autoneg for the port by the link partner.
19758 * This field is deprecated and should be set to 0.
19760 uint8_t link_partner_adv_auto_mode;
19761 /* Disable autoneg or autoneg disabled. No speeds are selected. */
19762 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_AUTO_MODE_NONE \
19764 /* Select all possible speeds for autoneg mode. */
19765 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_AUTO_MODE_ALL_SPEEDS \
19768 * Select only the auto_link_speed speed for autoneg mode. This mode has
19769 * been DEPRECATED. An HWRM client should not use this mode.
19771 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_AUTO_MODE_ONE_SPEED \
19774 * Select the auto_link_speed or any speed below that speed for autoneg.
19775 * This mode has been DEPRECATED. An HWRM client should not use this mode.
19777 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_AUTO_MODE_ONE_OR_BELOW \
19780 * Select the speeds based on the corresponding link speed mask value
19781 * that is provided.
19783 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_AUTO_MODE_SPEED_MASK \
19785 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_AUTO_MODE_LAST \
19786 HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_AUTO_MODE_SPEED_MASK
19787 /* The advertised pause settings on the port by the link partner. */
19788 uint8_t link_partner_adv_pause;
19790 * When this bit is '1', Generation of tx pause messages
19791 * is supported. Disabled otherwise.
19793 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_PAUSE_TX \
19796 * When this bit is '1', Reception of rx pause messages
19797 * is supported. Disabled otherwise.
19799 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_PAUSE_RX \
19802 * Current setting for link speed mask that is used to
19803 * advertise speeds during autonegotiation when EEE is enabled.
19804 * This field is valid only when eee_enabled flags is set to 1.
19805 * The speeds specified in this field shall be a subset of
19806 * speeds specified in auto_link_speed_mask.
19808 uint16_t adv_eee_link_speed_mask;
19810 #define HWRM_PORT_PHY_QCFG_OUTPUT_ADV_EEE_LINK_SPEED_MASK_RSVD1 \
19812 /* 100Mb link speed (Full-duplex) */
19813 #define HWRM_PORT_PHY_QCFG_OUTPUT_ADV_EEE_LINK_SPEED_MASK_100MB \
19816 #define HWRM_PORT_PHY_QCFG_OUTPUT_ADV_EEE_LINK_SPEED_MASK_RSVD2 \
19818 /* 1Gb link speed (Full-duplex) */
19819 #define HWRM_PORT_PHY_QCFG_OUTPUT_ADV_EEE_LINK_SPEED_MASK_1GB \
19822 #define HWRM_PORT_PHY_QCFG_OUTPUT_ADV_EEE_LINK_SPEED_MASK_RSVD3 \
19825 #define HWRM_PORT_PHY_QCFG_OUTPUT_ADV_EEE_LINK_SPEED_MASK_RSVD4 \
19827 /* 10Gb link speed */
19828 #define HWRM_PORT_PHY_QCFG_OUTPUT_ADV_EEE_LINK_SPEED_MASK_10GB \
19831 * Current setting for link speed mask that is advertised by
19832 * the link partner when EEE is enabled.
19833 * This field is valid only when eee_enabled flags is set to 1.
19835 uint16_t link_partner_adv_eee_link_speed_mask;
19837 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_EEE_LINK_SPEED_MASK_RSVD1 \
19839 /* 100Mb link speed (Full-duplex) */
19840 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_EEE_LINK_SPEED_MASK_100MB \
19843 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_EEE_LINK_SPEED_MASK_RSVD2 \
19845 /* 1Gb link speed (Full-duplex) */
19846 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_EEE_LINK_SPEED_MASK_1GB \
19849 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_EEE_LINK_SPEED_MASK_RSVD3 \
19852 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_EEE_LINK_SPEED_MASK_RSVD4 \
19854 /* 10Gb link speed */
19855 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_EEE_LINK_SPEED_MASK_10GB \
19857 uint32_t xcvr_identifier_type_tx_lpi_timer;
19859 * Current setting of TX LPI timer in microseconds.
19860 * This field is valid only when_eee_enabled flag is set to 1
19861 * and tx_lpi_enabled is set to 1.
19863 #define HWRM_PORT_PHY_QCFG_OUTPUT_TX_LPI_TIMER_MASK \
19865 #define HWRM_PORT_PHY_QCFG_OUTPUT_TX_LPI_TIMER_SFT 0
19866 /* This value represents transceiver identifier type. */
19867 #define HWRM_PORT_PHY_QCFG_OUTPUT_XCVR_IDENTIFIER_TYPE_MASK \
19868 UINT32_C(0xff000000)
19869 #define HWRM_PORT_PHY_QCFG_OUTPUT_XCVR_IDENTIFIER_TYPE_SFT 24
19871 #define HWRM_PORT_PHY_QCFG_OUTPUT_XCVR_IDENTIFIER_TYPE_UNKNOWN \
19872 (UINT32_C(0x0) << 24)
19873 /* SFP/SFP+/SFP28 */
19874 #define HWRM_PORT_PHY_QCFG_OUTPUT_XCVR_IDENTIFIER_TYPE_SFP \
19875 (UINT32_C(0x3) << 24)
19877 #define HWRM_PORT_PHY_QCFG_OUTPUT_XCVR_IDENTIFIER_TYPE_QSFP \
19878 (UINT32_C(0xc) << 24)
19880 #define HWRM_PORT_PHY_QCFG_OUTPUT_XCVR_IDENTIFIER_TYPE_QSFPPLUS \
19881 (UINT32_C(0xd) << 24)
19883 #define HWRM_PORT_PHY_QCFG_OUTPUT_XCVR_IDENTIFIER_TYPE_QSFP28 \
19884 (UINT32_C(0x11) << 24)
19885 #define HWRM_PORT_PHY_QCFG_OUTPUT_XCVR_IDENTIFIER_TYPE_LAST \
19886 HWRM_PORT_PHY_QCFG_OUTPUT_XCVR_IDENTIFIER_TYPE_QSFP28
19888 * This value represents the current configuration of
19889 * Forward Error Correction (FEC) on the port.
19893 * When set to 1, then FEC is not supported on this port. If this flag
19894 * is set to 1, then all other FEC configuration flags shall be ignored.
19895 * When set to 0, then FEC is supported as indicated by other
19896 * configuration flags.
19898 #define HWRM_PORT_PHY_QCFG_OUTPUT_FEC_CFG_FEC_NONE_SUPPORTED \
19901 * When set to 1, then FEC autonegotiation is supported on this port.
19902 * When set to 0, then FEC autonegotiation is not supported on this port.
19904 #define HWRM_PORT_PHY_QCFG_OUTPUT_FEC_CFG_FEC_AUTONEG_SUPPORTED \
19907 * When set to 1, then FEC autonegotiation is enabled on this port.
19908 * When set to 0, then FEC autonegotiation is disabled if supported.
19909 * This flag should be ignored if FEC autonegotiation is not supported on this port.
19911 #define HWRM_PORT_PHY_QCFG_OUTPUT_FEC_CFG_FEC_AUTONEG_ENABLED \
19914 * When set to 1, then FEC CLAUSE 74 (Fire Code) is supported on this port.
19915 * When set to 0, then FEC CLAUSE 74 (Fire Code) is not supported on this port.
19917 #define HWRM_PORT_PHY_QCFG_OUTPUT_FEC_CFG_FEC_CLAUSE74_SUPPORTED \
19920 * When set to 1, then FEC CLAUSE 74 (Fire Code) is enabled on this
19921 * port. This means that FEC CLAUSE 74 is either advertised if
19922 * FEC autonegotiation is enabled or FEC CLAUSE 74 is force enabled.
19923 * When set to 0, then FEC CLAUSE 74 (Fire Code) is disabled if supported.
19924 * This flag should be ignored if FEC CLAUSE 74 is not supported on this port.
19926 #define HWRM_PORT_PHY_QCFG_OUTPUT_FEC_CFG_FEC_CLAUSE74_ENABLED \
19929 * When set to 1, then FEC CLAUSE 91 (Reed Solomon RS(528,514) for
19930 * NRZ) is supported on this port.
19931 * When set to 0, then FEC RS(528,418) is not supported on this port.
19933 #define HWRM_PORT_PHY_QCFG_OUTPUT_FEC_CFG_FEC_CLAUSE91_SUPPORTED \
19936 * When set to 1, then FEC CLAUSE 91 (Reed Solomon RS(528,514) for
19937 * NRZ) is enabled on this port. This means that FEC RS(528,514) is
19938 * either advertised if FEC autonegotiation is enabled or FEC
19939 * RS(528,514) is force enabled. When set to 0, then FEC RS(528,514)
19940 * is disabled if supported.
19941 * This flag should be ignored if FEC CLAUSE 91 is not supported on this port.
19943 #define HWRM_PORT_PHY_QCFG_OUTPUT_FEC_CFG_FEC_CLAUSE91_ENABLED \
19946 * When set to 1, then FEC RS544_1XN is supported on this port.
19947 * When set to 0, then FEC RS544_1XN is not supported on this port.
19949 #define HWRM_PORT_PHY_QCFG_OUTPUT_FEC_CFG_FEC_RS544_1XN_SUPPORTED \
19952 * When set to 1, then RS544_1XN is enabled on this
19953 * port. This means that FEC RS544_1XN is either advertised if
19954 * FEC autonegotiation is enabled or FEC RS544_1XN is force enabled.
19955 * When set to 0, then FEC RS544_1XN is disabled if supported.
19956 * This flag should be ignored if FEC RS544_1XN is not supported on this port.
19958 #define HWRM_PORT_PHY_QCFG_OUTPUT_FEC_CFG_FEC_RS544_1XN_ENABLED \
19961 * When set to 1, then FEC RS(544,514) is supported on this port.
19962 * When set to 0, then FEC RS(544,514) is not supported on this port.
19964 #define HWRM_PORT_PHY_QCFG_OUTPUT_FEC_CFG_FEC_RS544_IEEE_SUPPORTED \
19967 * When set to 1, then RS(544,514) is enabled on this
19968 * port. This means that FEC RS(544,514) is either advertised if
19969 * FEC autonegotiation is enabled or FEC RS(544,514) is force
19970 * enabled. When set to 0, then FEC RS(544,514) is disabled if supported.
19971 * This flag should be ignored if FEC RS(544,514) is not supported on this port.
19973 #define HWRM_PORT_PHY_QCFG_OUTPUT_FEC_CFG_FEC_RS544_IEEE_ENABLED \
19976 * When set to 1, then FEC RS272_1XN is supported on this port.
19977 * When set to 0, then FEC RS272_1XN is not supported on this port.
19979 #define HWRM_PORT_PHY_QCFG_OUTPUT_FEC_CFG_FEC_RS272_1XN_SUPPORTED \
19982 * When set to 1, then RS272_1XN is enabled on this
19983 * port. This means that FEC RS272_1XN is either advertised if
19984 * FEC autonegotiation is enabled or FEC RS272_1XN is force
19985 * enabled. When set to 0, then FEC RS272_1XN is disabled if supported.
19986 * This flag should be ignored if FEC RS272_1XN is not supported on this port.
19988 #define HWRM_PORT_PHY_QCFG_OUTPUT_FEC_CFG_FEC_RS272_1XN_ENABLED \
19991 * When set to 1, then FEC RS(272,514) is supported on this port.
19992 * When set to 0, then FEC RS(272,514) is not supported on this port.
19994 #define HWRM_PORT_PHY_QCFG_OUTPUT_FEC_CFG_FEC_RS272_IEEE_SUPPORTED \
19997 * When set to 1, then RS(272,257) is enabled on this
19998 * port. This means that FEC RS(272,257) is either advertised if
19999 * FEC autonegotiation is enabled or FEC RS(272,257) is force
20000 * enabled. When set to 0, then FEC RS(272,257) is disabled if supported.
20001 * This flag should be ignored if FEC RS(272,257) is not supported on this port.
20003 #define HWRM_PORT_PHY_QCFG_OUTPUT_FEC_CFG_FEC_RS272_IEEE_ENABLED \
20006 * This value is indicates the duplex of the current
20007 * connection state.
20009 uint8_t duplex_state;
20010 /* Half Duplex connection. */
20011 #define HWRM_PORT_PHY_QCFG_OUTPUT_DUPLEX_STATE_HALF UINT32_C(0x0)
20012 /* Full duplex connection. */
20013 #define HWRM_PORT_PHY_QCFG_OUTPUT_DUPLEX_STATE_FULL UINT32_C(0x1)
20014 #define HWRM_PORT_PHY_QCFG_OUTPUT_DUPLEX_STATE_LAST \
20015 HWRM_PORT_PHY_QCFG_OUTPUT_DUPLEX_STATE_FULL
20016 /* Option flags fields. */
20017 uint8_t option_flags;
20018 /* When this bit is '1', Media auto detect is enabled. */
20019 #define HWRM_PORT_PHY_QCFG_OUTPUT_OPTION_FLAGS_MEDIA_AUTO_DETECT \
20022 * When this bit is '1', active_fec_signal_mode can be
20025 #define HWRM_PORT_PHY_QCFG_OUTPUT_OPTION_FLAGS_SIGNAL_MODE_KNOWN \
20028 * Up to 16 bytes of null padded ASCII string representing
20030 * If the string is set to null, then the vendor name is not
20033 char phy_vendor_name[16];
20035 * Up to 16 bytes of null padded ASCII string that
20036 * identifies vendor specific part number of the PHY.
20037 * If the string is set to null, then the vendor specific
20038 * part number is not available.
20040 char phy_vendor_partnumber[16];
20042 * The supported PAM4 speeds for the port. This is a bit mask.
20043 * For each speed that is supported, the corresponding
20044 * bit will be set to '1'.
20046 uint16_t support_pam4_speeds;
20047 #define HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_PAM4_SPEEDS_50G \
20049 #define HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_PAM4_SPEEDS_100G \
20051 #define HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_PAM4_SPEEDS_200G \
20054 * Current setting of forced PAM4 link speed.
20055 * When the link speed is not being forced, this
20056 * value shall be set to 0.
20058 uint16_t force_pam4_link_speed;
20059 /* 50Gb link speed */
20060 #define HWRM_PORT_PHY_QCFG_OUTPUT_FORCE_PAM4_LINK_SPEED_50GB \
20062 /* 100Gb link speed */
20063 #define HWRM_PORT_PHY_QCFG_OUTPUT_FORCE_PAM4_LINK_SPEED_100GB \
20065 /* 200Gb link speed */
20066 #define HWRM_PORT_PHY_QCFG_OUTPUT_FORCE_PAM4_LINK_SPEED_200GB \
20068 #define HWRM_PORT_PHY_QCFG_OUTPUT_FORCE_PAM4_LINK_SPEED_LAST \
20069 HWRM_PORT_PHY_QCFG_OUTPUT_FORCE_PAM4_LINK_SPEED_200GB
20071 * Current setting for auto_pam4_link_speed_mask that is used to
20072 * advertise speeds during autonegotiation.
20073 * This field is only valid when auto_mode is set to "mask".
20074 * The speeds specified in this field shall be a subset of
20075 * supported speeds on this port.
20077 uint16_t auto_pam4_link_speed_mask;
20078 #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_PAM4_LINK_SPEED_MASK_50G \
20080 #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_PAM4_LINK_SPEED_MASK_100G \
20082 #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_PAM4_LINK_SPEED_MASK_200G \
20085 * The advertised PAM4 speeds for the port by the link partner.
20086 * Each advertised speed will be set to '1'.
20088 uint8_t link_partner_pam4_adv_speeds;
20089 /* 50Gb link speed */
20090 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_PAM4_ADV_SPEEDS_50GB \
20092 /* 100Gb link speed */
20093 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_PAM4_ADV_SPEEDS_100GB \
20095 /* 200Gb link speed */
20096 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_PAM4_ADV_SPEEDS_200GB \
20099 * This field is used in Output records to indicate that the output
20100 * is completely written to RAM. This field should be read as '1'
20101 * to indicate that the output has been completely written.
20102 * When writing a command completion or response to an internal processor,
20103 * the order of writes has to be such that this field is written last.
20108 /*********************
20109 * hwrm_port_mac_cfg *
20110 *********************/
20113 /* hwrm_port_mac_cfg_input (size:384b/48B) */
20114 struct hwrm_port_mac_cfg_input {
20115 /* The HWRM command request type. */
20118 * The completion ring to send the completion event on. This should
20119 * be the NQ ID returned from the `nq_alloc` HWRM command.
20121 uint16_t cmpl_ring;
20123 * The sequence ID is used by the driver for tracking multiple
20124 * commands. This ID is treated as opaque data by the firmware and
20125 * the value is returned in the `hwrm_resp_hdr` upon completion.
20129 * The target ID of the command:
20130 * * 0x0-0xFFF8 - The function ID
20131 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
20132 * * 0xFFFD - Reserved for user-space HWRM interface
20135 uint16_t target_id;
20137 * A physical address pointer pointing to a host buffer that the
20138 * command's response data will be written. This can be either a host
20139 * physical address (HPA) or a guest physical address (GPA) and must
20140 * point to a physically contiguous block of memory.
20142 uint64_t resp_addr;
20144 * In this field, there are a number of CoS mappings related flags
20145 * that are used to configure CoS mappings and their corresponding
20146 * priorities in the hardware.
20147 * For the priorities of CoS mappings, the HWRM uses the following
20148 * priority order (high to low) by default:
20151 * # tunnel_vlan_pri
20154 * A subset of CoS mappings can be enabled.
20155 * If a priority is not specified for an enabled CoS mapping, the
20156 * priority will be assigned in the above order for the enabled CoS
20157 * mappings. For example, if vlan_pri and ip_dscp CoS mappings are
20158 * enabled and their priorities are not specified, the following
20159 * priority order (high to low) will be used by the HWRM:
20164 * vlan_pri CoS mapping together with default CoS with lower priority
20165 * are enabled by default by the HWRM.
20169 * When this bit is '1', this command will configure
20170 * the MAC to match the current link state of the PHY.
20171 * If the link is not established on the PHY, then this
20172 * bit has no effect.
20174 #define HWRM_PORT_MAC_CFG_INPUT_FLAGS_MATCH_LINK \
20177 * When this bit is set to '1', the inner VLAN PRI to CoS mapping
20178 * is requested to be enabled.
20180 #define HWRM_PORT_MAC_CFG_INPUT_FLAGS_VLAN_PRI2COS_ENABLE \
20183 * When this bit is set to '1', tunnel VLAN PRI field to
20184 * CoS mapping is requested to be enabled.
20186 #define HWRM_PORT_MAC_CFG_INPUT_FLAGS_TUNNEL_PRI2COS_ENABLE \
20189 * When this bit is set to '1', the IP DSCP to CoS mapping is
20190 * requested to be enabled.
20192 #define HWRM_PORT_MAC_CFG_INPUT_FLAGS_IP_DSCP2COS_ENABLE \
20195 * When this bit is '1', the HWRM is requested to
20196 * enable timestamp capture capability on the receive side
20199 #define HWRM_PORT_MAC_CFG_INPUT_FLAGS_PTP_RX_TS_CAPTURE_ENABLE \
20202 * When this bit is '1', the HWRM is requested to
20203 * disable timestamp capture capability on the receive side
20206 #define HWRM_PORT_MAC_CFG_INPUT_FLAGS_PTP_RX_TS_CAPTURE_DISABLE \
20209 * When this bit is '1', the HWRM is requested to
20210 * enable timestamp capture capability on the transmit side
20213 #define HWRM_PORT_MAC_CFG_INPUT_FLAGS_PTP_TX_TS_CAPTURE_ENABLE \
20216 * When this bit is '1', the HWRM is requested to
20217 * disable timestamp capture capability on the transmit side
20220 #define HWRM_PORT_MAC_CFG_INPUT_FLAGS_PTP_TX_TS_CAPTURE_DISABLE \
20223 * When this bit is '1', the Out-Of-Box WoL is requested to
20224 * be enabled on this port.
20226 #define HWRM_PORT_MAC_CFG_INPUT_FLAGS_OOB_WOL_ENABLE \
20229 * When this bit is '1', the Out-Of-Box WoL is requested to
20230 * be disabled on this port.
20232 #define HWRM_PORT_MAC_CFG_INPUT_FLAGS_OOB_WOL_DISABLE \
20235 * When this bit is set to '1', the inner VLAN PRI to CoS mapping
20236 * is requested to be disabled.
20238 #define HWRM_PORT_MAC_CFG_INPUT_FLAGS_VLAN_PRI2COS_DISABLE \
20241 * When this bit is set to '1', tunnel VLAN PRI field to
20242 * CoS mapping is requested to be disabled.
20244 #define HWRM_PORT_MAC_CFG_INPUT_FLAGS_TUNNEL_PRI2COS_DISABLE \
20247 * When this bit is set to '1', the IP DSCP to CoS mapping is
20248 * requested to be disabled.
20250 #define HWRM_PORT_MAC_CFG_INPUT_FLAGS_IP_DSCP2COS_DISABLE \
20253 * When this bit is set to '1', and the ptp_tx_ts_capture_enable
20254 * bit is set, then the device uses one step Tx timestamping.
20255 * This bit is temporary and used for experimental purposes.
20257 #define HWRM_PORT_MAC_CFG_INPUT_FLAGS_PTP_ONE_STEP_TX_TS \
20261 * This bit must be '1' for the ipg field to be
20264 #define HWRM_PORT_MAC_CFG_INPUT_ENABLES_IPG \
20267 * This bit must be '1' for the lpbk field to be
20270 #define HWRM_PORT_MAC_CFG_INPUT_ENABLES_LPBK \
20273 * This bit must be '1' for the vlan_pri2cos_map_pri field to be
20276 #define HWRM_PORT_MAC_CFG_INPUT_ENABLES_VLAN_PRI2COS_MAP_PRI \
20279 * This bit must be '1' for the tunnel_pri2cos_map_pri field to be
20282 #define HWRM_PORT_MAC_CFG_INPUT_ENABLES_TUNNEL_PRI2COS_MAP_PRI \
20285 * This bit must be '1' for the dscp2cos_map_pri field to be
20288 #define HWRM_PORT_MAC_CFG_INPUT_ENABLES_DSCP2COS_MAP_PRI \
20291 * This bit must be '1' for the rx_ts_capture_ptp_msg_type field to be
20294 #define HWRM_PORT_MAC_CFG_INPUT_ENABLES_RX_TS_CAPTURE_PTP_MSG_TYPE \
20297 * This bit must be '1' for the tx_ts_capture_ptp_msg_type field to be
20300 #define HWRM_PORT_MAC_CFG_INPUT_ENABLES_TX_TS_CAPTURE_PTP_MSG_TYPE \
20303 * This bit must be '1' for the cos_field_cfg field to be
20306 #define HWRM_PORT_MAC_CFG_INPUT_ENABLES_COS_FIELD_CFG \
20309 * This bit must be '1' for the ptp_freq_adj_ppb field to be
20312 #define HWRM_PORT_MAC_CFG_INPUT_ENABLES_PTP_FREQ_ADJ_PPB \
20314 /* Port ID of port that is to be configured. */
20317 * This value is used to configure the minimum IPG that will
20318 * be sent between packets by this port.
20321 /* This value controls the loopback setting for the MAC. */
20323 /* No loopback is selected. Normal operation. */
20324 #define HWRM_PORT_MAC_CFG_INPUT_LPBK_NONE UINT32_C(0x0)
20326 * The HW will be configured with local loopback such that
20327 * host data is sent back to the host without modification.
20329 #define HWRM_PORT_MAC_CFG_INPUT_LPBK_LOCAL UINT32_C(0x1)
20331 * The HW will be configured with remote loopback such that
20332 * port logic will send packets back out the transmitter that
20335 #define HWRM_PORT_MAC_CFG_INPUT_LPBK_REMOTE UINT32_C(0x2)
20336 #define HWRM_PORT_MAC_CFG_INPUT_LPBK_LAST \
20337 HWRM_PORT_MAC_CFG_INPUT_LPBK_REMOTE
20339 * This value controls the priority setting of VLAN PRI to CoS
20340 * mapping based on VLAN Tags of inner packet headers of
20341 * tunneled packets or packet headers of non-tunneled packets.
20343 * # Each XXX_pri variable shall have a unique priority value
20344 * when it is being specified.
20345 * # When comparing priorities of mappings, higher value
20346 * indicates higher priority.
20347 * For example, a value of 0-3 is returned where 0 is being
20348 * the lowest priority and 3 is being the highest priority.
20350 uint8_t vlan_pri2cos_map_pri;
20351 /* Reserved field. */
20354 * This value controls the priority setting of VLAN PRI to CoS
20355 * mapping based on VLAN Tags of tunneled header.
20356 * This mapping only applies when tunneled headers
20359 * # Each XXX_pri variable shall have a unique priority value
20360 * when it is being specified.
20361 * # When comparing priorities of mappings, higher value
20362 * indicates higher priority.
20363 * For example, a value of 0-3 is returned where 0 is being
20364 * the lowest priority and 3 is being the highest priority.
20366 uint8_t tunnel_pri2cos_map_pri;
20368 * This value controls the priority setting of IP DSCP to CoS
20369 * mapping based on inner IP header of tunneled packets or
20370 * IP header of non-tunneled packets.
20372 * # Each XXX_pri variable shall have a unique priority value
20373 * when it is being specified.
20374 * # When comparing priorities of mappings, higher value
20375 * indicates higher priority.
20376 * For example, a value of 0-3 is returned where 0 is being
20377 * the lowest priority and 3 is being the highest priority.
20379 uint8_t dscp2pri_map_pri;
20381 * This is a 16-bit bit mask that is used to request a
20382 * specific configuration of time stamp capture of PTP messages
20383 * on the receive side of this port.
20384 * This field shall be ignored if the ptp_rx_ts_capture_enable
20385 * flag is not set in this command.
20386 * Otherwise, if bit 'i' is set, then the HWRM is being
20387 * requested to configure the receive side of the port to
20388 * capture the time stamp of every received PTP message
20389 * with messageType field value set to i.
20391 uint16_t rx_ts_capture_ptp_msg_type;
20393 * This is a 16-bit bit mask that is used to request a
20394 * specific configuration of time stamp capture of PTP messages
20395 * on the transmit side of this port.
20396 * This field shall be ignored if the ptp_tx_ts_capture_enable
20397 * flag is not set in this command.
20398 * Otherwise, if bit 'i' is set, then the HWRM is being
20399 * requested to configure the transmit side of the port to
20400 * capture the time stamp of every transmitted PTP message
20401 * with messageType field value set to i.
20403 uint16_t tx_ts_capture_ptp_msg_type;
20404 /* Configuration of CoS fields. */
20405 uint8_t cos_field_cfg;
20407 #define HWRM_PORT_MAC_CFG_INPUT_COS_FIELD_CFG_RSVD1 \
20410 * This field is used to specify selection of VLAN PRI value
20411 * based on whether one or two VLAN Tags are present in
20412 * the inner packet headers of tunneled packets or
20413 * non-tunneled packets.
20414 * This field is valid only if inner VLAN PRI to CoS mapping
20416 * If VLAN PRI to CoS mapping is not enabled, then this
20417 * field shall be ignored.
20419 #define HWRM_PORT_MAC_CFG_INPUT_COS_FIELD_CFG_VLAN_PRI_SEL_MASK \
20421 #define HWRM_PORT_MAC_CFG_INPUT_COS_FIELD_CFG_VLAN_PRI_SEL_SFT \
20424 * Select inner VLAN PRI when 1 or 2 VLAN Tags are
20425 * present in the inner packet headers
20427 #define HWRM_PORT_MAC_CFG_INPUT_COS_FIELD_CFG_VLAN_PRI_SEL_INNERMOST \
20428 (UINT32_C(0x0) << 1)
20430 * Select outer VLAN Tag PRI when 2 VLAN Tags are
20431 * present in the inner packet headers.
20432 * No VLAN PRI shall be selected for this configuration
20433 * if only one VLAN Tag is present in the inner
20436 #define HWRM_PORT_MAC_CFG_INPUT_COS_FIELD_CFG_VLAN_PRI_SEL_OUTER \
20437 (UINT32_C(0x1) << 1)
20439 * Select outermost VLAN PRI when 1 or 2 VLAN Tags
20440 * are present in the inner packet headers
20442 #define HWRM_PORT_MAC_CFG_INPUT_COS_FIELD_CFG_VLAN_PRI_SEL_OUTERMOST \
20443 (UINT32_C(0x2) << 1)
20445 #define HWRM_PORT_MAC_CFG_INPUT_COS_FIELD_CFG_VLAN_PRI_SEL_UNSPECIFIED \
20446 (UINT32_C(0x3) << 1)
20447 #define HWRM_PORT_MAC_CFG_INPUT_COS_FIELD_CFG_VLAN_PRI_SEL_LAST \
20448 HWRM_PORT_MAC_CFG_INPUT_COS_FIELD_CFG_VLAN_PRI_SEL_UNSPECIFIED
20450 * This field is used to specify selection of tunnel VLAN
20451 * PRI value based on whether one or two VLAN Tags are
20452 * present in tunnel headers.
20453 * This field is valid only if tunnel VLAN PRI to CoS mapping
20455 * If tunnel VLAN PRI to CoS mapping is not enabled, then this
20456 * field shall be ignored.
20458 #define HWRM_PORT_MAC_CFG_INPUT_COS_FIELD_CFG_T_VLAN_PRI_SEL_MASK \
20460 #define HWRM_PORT_MAC_CFG_INPUT_COS_FIELD_CFG_T_VLAN_PRI_SEL_SFT \
20463 * Select inner VLAN PRI when 1 or 2 VLAN Tags are
20464 * present in the tunnel packet headers
20466 #define HWRM_PORT_MAC_CFG_INPUT_COS_FIELD_CFG_T_VLAN_PRI_SEL_INNERMOST \
20467 (UINT32_C(0x0) << 3)
20469 * Select outer VLAN Tag PRI when 2 VLAN Tags are
20470 * present in the tunnel packet headers.
20471 * No tunnel VLAN PRI shall be selected for this
20472 * configuration if only one VLAN Tag is present in
20473 * the tunnel packet headers.
20475 #define HWRM_PORT_MAC_CFG_INPUT_COS_FIELD_CFG_T_VLAN_PRI_SEL_OUTER \
20476 (UINT32_C(0x1) << 3)
20478 * Select outermost VLAN PRI when 1 or 2 VLAN Tags
20479 * are present in the tunnel packet headers
20481 #define HWRM_PORT_MAC_CFG_INPUT_COS_FIELD_CFG_T_VLAN_PRI_SEL_OUTERMOST \
20482 (UINT32_C(0x2) << 3)
20484 #define HWRM_PORT_MAC_CFG_INPUT_COS_FIELD_CFG_T_VLAN_PRI_SEL_UNSPECIFIED \
20485 (UINT32_C(0x3) << 3)
20486 #define HWRM_PORT_MAC_CFG_INPUT_COS_FIELD_CFG_T_VLAN_PRI_SEL_LAST \
20487 HWRM_PORT_MAC_CFG_INPUT_COS_FIELD_CFG_T_VLAN_PRI_SEL_UNSPECIFIED
20489 * This field shall be used to provide default CoS value
20490 * that has been configured on this port.
20491 * This field is valid only if default CoS mapping
20493 * If default CoS mapping is not enabled, then this
20494 * field shall be ignored.
20496 #define HWRM_PORT_MAC_CFG_INPUT_COS_FIELD_CFG_DEFAULT_COS_MASK \
20498 #define HWRM_PORT_MAC_CFG_INPUT_COS_FIELD_CFG_DEFAULT_COS_SFT \
20500 uint8_t unused_0[3];
20502 * This signed field specifies by how much to adjust the frequency
20503 * of sync timer updates (measured in parts per billion).
20505 int32_t ptp_freq_adj_ppb;
20506 uint8_t unused_1[4];
20509 /* hwrm_port_mac_cfg_output (size:128b/16B) */
20510 struct hwrm_port_mac_cfg_output {
20511 /* The specific error status for the command. */
20512 uint16_t error_code;
20513 /* The HWRM command request type. */
20515 /* The sequence ID from the original command. */
20517 /* The length of the response data in number of bytes. */
20520 * This is the configured maximum length of Ethernet packet
20521 * payload that is allowed to be received on the port.
20522 * This value does not include the number of bytes used by
20523 * Ethernet header and trailer (CRC).
20527 * This is the configured maximum length of Ethernet packet
20528 * payload that is allowed to be transmitted on the port.
20529 * This value does not include the number of bytes used by
20530 * Ethernet header and trailer (CRC).
20533 /* Current configuration of the IPG value. */
20535 /* Current value of the loopback value. */
20537 /* No loopback is selected. Normal operation. */
20538 #define HWRM_PORT_MAC_CFG_OUTPUT_LPBK_NONE UINT32_C(0x0)
20540 * The HW will be configured with local loopback such that
20541 * host data is sent back to the host without modification.
20543 #define HWRM_PORT_MAC_CFG_OUTPUT_LPBK_LOCAL UINT32_C(0x1)
20545 * The HW will be configured with remote loopback such that
20546 * port logic will send packets back out the transmitter that
20549 #define HWRM_PORT_MAC_CFG_OUTPUT_LPBK_REMOTE UINT32_C(0x2)
20550 #define HWRM_PORT_MAC_CFG_OUTPUT_LPBK_LAST \
20551 HWRM_PORT_MAC_CFG_OUTPUT_LPBK_REMOTE
20554 * This field is used in Output records to indicate that the output
20555 * is completely written to RAM. This field should be read as '1'
20556 * to indicate that the output has been completely written.
20557 * When writing a command completion or response to an internal processor,
20558 * the order of writes has to be such that this field is written last.
20563 /**********************
20564 * hwrm_port_mac_qcfg *
20565 **********************/
20568 /* hwrm_port_mac_qcfg_input (size:192b/24B) */
20569 struct hwrm_port_mac_qcfg_input {
20570 /* The HWRM command request type. */
20573 * The completion ring to send the completion event on. This should
20574 * be the NQ ID returned from the `nq_alloc` HWRM command.
20576 uint16_t cmpl_ring;
20578 * The sequence ID is used by the driver for tracking multiple
20579 * commands. This ID is treated as opaque data by the firmware and
20580 * the value is returned in the `hwrm_resp_hdr` upon completion.
20584 * The target ID of the command:
20585 * * 0x0-0xFFF8 - The function ID
20586 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
20587 * * 0xFFFD - Reserved for user-space HWRM interface
20590 uint16_t target_id;
20592 * A physical address pointer pointing to a host buffer that the
20593 * command's response data will be written. This can be either a host
20594 * physical address (HPA) or a guest physical address (GPA) and must
20595 * point to a physically contiguous block of memory.
20597 uint64_t resp_addr;
20598 /* Port ID of port that is to be configured. */
20600 uint8_t unused_0[6];
20603 /* hwrm_port_mac_qcfg_output (size:256b/32B) */
20604 struct hwrm_port_mac_qcfg_output {
20605 /* The specific error status for the command. */
20606 uint16_t error_code;
20607 /* The HWRM command request type. */
20609 /* The sequence ID from the original command. */
20611 /* The length of the response data in number of bytes. */
20614 * This is the configured maximum length of Ethernet packet
20615 * payload that is allowed to be received on the port.
20616 * This value does not include the number of bytes used by the
20617 * Ethernet header and trailer (CRC).
20621 * This is the configured maximum length of Ethernet packet
20622 * payload that is allowed to be transmitted on the port.
20623 * This value does not include the number of bytes used by the
20624 * Ethernet header and trailer (CRC).
20628 * The minimum IPG that will
20629 * be sent between packets by this port.
20632 /* The loopback setting for the MAC. */
20634 /* No loopback is selected. Normal operation. */
20635 #define HWRM_PORT_MAC_QCFG_OUTPUT_LPBK_NONE UINT32_C(0x0)
20637 * The HW will be configured with local loopback such that
20638 * host data is sent back to the host without modification.
20640 #define HWRM_PORT_MAC_QCFG_OUTPUT_LPBK_LOCAL UINT32_C(0x1)
20642 * The HW will be configured with remote loopback such that
20643 * port logic will send packets back out the transmitter that
20646 #define HWRM_PORT_MAC_QCFG_OUTPUT_LPBK_REMOTE UINT32_C(0x2)
20647 #define HWRM_PORT_MAC_QCFG_OUTPUT_LPBK_LAST \
20648 HWRM_PORT_MAC_QCFG_OUTPUT_LPBK_REMOTE
20650 * Priority setting for VLAN PRI to CoS mapping.
20651 * # Each XXX_pri variable shall have a unique priority value
20652 * when it is being used.
20653 * # When comparing priorities of mappings, higher value
20654 * indicates higher priority.
20655 * For example, a value of 0-3 is returned where 0 is being
20656 * the lowest priority and 3 is being the highest priority.
20657 * # If the correspoding CoS mapping is not enabled, then this
20658 * field should be ignored.
20659 * # This value indicates the normalized priority value retained
20662 uint8_t vlan_pri2cos_map_pri;
20664 * In this field, a number of CoS mappings related flags
20665 * are used to indicate configured CoS mappings.
20669 * When this bit is set to '1', the inner VLAN PRI to CoS mapping
20672 #define HWRM_PORT_MAC_QCFG_OUTPUT_FLAGS_VLAN_PRI2COS_ENABLE \
20675 * When this bit is set to '1', tunnel VLAN PRI field to
20676 * CoS mapping is enabled.
20678 #define HWRM_PORT_MAC_QCFG_OUTPUT_FLAGS_TUNNEL_PRI2COS_ENABLE \
20681 * When this bit is set to '1', the IP DSCP to CoS mapping is
20684 #define HWRM_PORT_MAC_QCFG_OUTPUT_FLAGS_IP_DSCP2COS_ENABLE \
20687 * When this bit is '1', the Out-Of-Box WoL is enabled on this
20690 #define HWRM_PORT_MAC_QCFG_OUTPUT_FLAGS_OOB_WOL_ENABLE \
20692 /* When this bit is '1', PTP is enabled for RX on this port. */
20693 #define HWRM_PORT_MAC_QCFG_OUTPUT_FLAGS_PTP_RX_TS_CAPTURE_ENABLE \
20695 /* When this bit is '1', PTP is enabled for TX on this port. */
20696 #define HWRM_PORT_MAC_QCFG_OUTPUT_FLAGS_PTP_TX_TS_CAPTURE_ENABLE \
20699 * Priority setting for tunnel VLAN PRI to CoS mapping.
20700 * # Each XXX_pri variable shall have a unique priority value
20701 * when it is being used.
20702 * # When comparing priorities of mappings, higher value
20703 * indicates higher priority.
20704 * For example, a value of 0-3 is returned where 0 is being
20705 * the lowest priority and 3 is being the highest priority.
20706 * # If the correspoding CoS mapping is not enabled, then this
20707 * field should be ignored.
20708 * # This value indicates the normalized priority value retained
20711 uint8_t tunnel_pri2cos_map_pri;
20713 * Priority setting for DSCP to PRI mapping.
20714 * # Each XXX_pri variable shall have a unique priority value
20715 * when it is being used.
20716 * # When comparing priorities of mappings, higher value
20717 * indicates higher priority.
20718 * For example, a value of 0-3 is returned where 0 is being
20719 * the lowest priority and 3 is being the highest priority.
20720 * # If the correspoding CoS mapping is not enabled, then this
20721 * field should be ignored.
20722 * # This value indicates the normalized priority value retained
20725 uint8_t dscp2pri_map_pri;
20727 * This is a 16-bit bit mask that represents the
20728 * current configuration of time stamp capture of PTP messages
20729 * on the receive side of this port.
20730 * If bit 'i' is set, then the receive side of the port
20731 * is configured to capture the time stamp of every
20732 * received PTP message with messageType field value set
20734 * If all bits are set to 0 (i.e. field value set 0),
20735 * then the receive side of the port is not configured
20736 * to capture timestamp for PTP messages.
20737 * If all bits are set to 1, then the receive side of the
20738 * port is configured to capture timestamp for all PTP
20741 uint16_t rx_ts_capture_ptp_msg_type;
20743 * This is a 16-bit bit mask that represents the
20744 * current configuration of time stamp capture of PTP messages
20745 * on the transmit side of this port.
20746 * If bit 'i' is set, then the transmit side of the port
20747 * is configured to capture the time stamp of every
20748 * received PTP message with messageType field value set
20750 * If all bits are set to 0 (i.e. field value set 0),
20751 * then the transmit side of the port is not configured
20752 * to capture timestamp for PTP messages.
20753 * If all bits are set to 1, then the transmit side of the
20754 * port is configured to capture timestamp for all PTP
20757 uint16_t tx_ts_capture_ptp_msg_type;
20758 /* Configuration of CoS fields. */
20759 uint8_t cos_field_cfg;
20761 #define HWRM_PORT_MAC_QCFG_OUTPUT_COS_FIELD_CFG_RSVD \
20764 * This field is used for selecting VLAN PRI value
20765 * based on whether one or two VLAN Tags are present in
20766 * the inner packet headers of tunneled packets or
20767 * non-tunneled packets.
20769 #define HWRM_PORT_MAC_QCFG_OUTPUT_COS_FIELD_CFG_VLAN_PRI_SEL_MASK \
20771 #define HWRM_PORT_MAC_QCFG_OUTPUT_COS_FIELD_CFG_VLAN_PRI_SEL_SFT \
20774 * Select inner VLAN PRI when 1 or 2 VLAN Tags are
20775 * present in the inner packet headers
20777 #define HWRM_PORT_MAC_QCFG_OUTPUT_COS_FIELD_CFG_VLAN_PRI_SEL_INNERMOST \
20778 (UINT32_C(0x0) << 1)
20780 * Select outer VLAN Tag PRI when 2 VLAN Tags are
20781 * present in the inner packet headers.
20782 * No VLAN PRI is selected for this configuration
20783 * if only one VLAN Tag is present in the inner
20786 #define HWRM_PORT_MAC_QCFG_OUTPUT_COS_FIELD_CFG_VLAN_PRI_SEL_OUTER \
20787 (UINT32_C(0x1) << 1)
20789 * Select outermost VLAN PRI when 1 or 2 VLAN Tags
20790 * are present in the inner packet headers
20792 #define HWRM_PORT_MAC_QCFG_OUTPUT_COS_FIELD_CFG_VLAN_PRI_SEL_OUTERMOST \
20793 (UINT32_C(0x2) << 1)
20795 #define HWRM_PORT_MAC_QCFG_OUTPUT_COS_FIELD_CFG_VLAN_PRI_SEL_UNSPECIFIED \
20796 (UINT32_C(0x3) << 1)
20797 #define HWRM_PORT_MAC_QCFG_OUTPUT_COS_FIELD_CFG_VLAN_PRI_SEL_LAST \
20798 HWRM_PORT_MAC_QCFG_OUTPUT_COS_FIELD_CFG_VLAN_PRI_SEL_UNSPECIFIED
20800 * This field is used for selecting tunnel VLAN PRI value
20801 * based on whether one or two VLAN Tags are present in
20802 * the tunnel headers of tunneled packets. This selection
20803 * does not apply to non-tunneled packets.
20805 #define HWRM_PORT_MAC_QCFG_OUTPUT_COS_FIELD_CFG_T_VLAN_PRI_SEL_MASK \
20807 #define HWRM_PORT_MAC_QCFG_OUTPUT_COS_FIELD_CFG_T_VLAN_PRI_SEL_SFT \
20810 * Select inner VLAN PRI when 1 or 2 VLAN Tags are
20811 * present in the tunnel packet headers
20813 #define HWRM_PORT_MAC_QCFG_OUTPUT_COS_FIELD_CFG_T_VLAN_PRI_SEL_INNERMOST \
20814 (UINT32_C(0x0) << 3)
20816 * Select outer VLAN Tag PRI when 2 VLAN Tags are
20817 * present in the tunnel packet headers.
20818 * No VLAN PRI is selected for this configuration
20819 * if only one VLAN Tag is present in the tunnel
20822 #define HWRM_PORT_MAC_QCFG_OUTPUT_COS_FIELD_CFG_T_VLAN_PRI_SEL_OUTER \
20823 (UINT32_C(0x1) << 3)
20825 * Select outermost VLAN PRI when 1 or 2 VLAN Tags
20826 * are present in the tunnel packet headers
20828 #define HWRM_PORT_MAC_QCFG_OUTPUT_COS_FIELD_CFG_T_VLAN_PRI_SEL_OUTERMOST \
20829 (UINT32_C(0x2) << 3)
20831 #define HWRM_PORT_MAC_QCFG_OUTPUT_COS_FIELD_CFG_T_VLAN_PRI_SEL_UNSPECIFIED \
20832 (UINT32_C(0x3) << 3)
20833 #define HWRM_PORT_MAC_QCFG_OUTPUT_COS_FIELD_CFG_T_VLAN_PRI_SEL_LAST \
20834 HWRM_PORT_MAC_QCFG_OUTPUT_COS_FIELD_CFG_T_VLAN_PRI_SEL_UNSPECIFIED
20836 * This field is used to provide default CoS value that
20837 * has been configured on this port.
20839 #define HWRM_PORT_MAC_QCFG_OUTPUT_COS_FIELD_CFG_DEFAULT_COS_MASK \
20841 #define HWRM_PORT_MAC_QCFG_OUTPUT_COS_FIELD_CFG_DEFAULT_COS_SFT \
20844 uint16_t port_svif_info;
20846 * This field specifies the source virtual interface of the port being
20847 * queried. Drivers can use this to program port svif field in the
20850 #define HWRM_PORT_MAC_QCFG_OUTPUT_PORT_SVIF_INFO_PORT_SVIF_MASK \
20852 #define HWRM_PORT_MAC_QCFG_OUTPUT_PORT_SVIF_INFO_PORT_SVIF_SFT 0
20853 /* This field specifies whether port_svif is valid or not */
20854 #define HWRM_PORT_MAC_QCFG_OUTPUT_PORT_SVIF_INFO_PORT_SVIF_VALID \
20856 uint8_t unused_2[5];
20858 * This field is used in Output records to indicate that the output
20859 * is completely written to RAM. This field should be read as '1'
20860 * to indicate that the output has been completely written.
20861 * When writing a command completion or response to an internal processor,
20862 * the order of writes has to be such that this field is written last.
20867 /**************************
20868 * hwrm_port_mac_ptp_qcfg *
20869 **************************/
20872 /* hwrm_port_mac_ptp_qcfg_input (size:192b/24B) */
20873 struct hwrm_port_mac_ptp_qcfg_input {
20874 /* The HWRM command request type. */
20877 * The completion ring to send the completion event on. This should
20878 * be the NQ ID returned from the `nq_alloc` HWRM command.
20880 uint16_t cmpl_ring;
20882 * The sequence ID is used by the driver for tracking multiple
20883 * commands. This ID is treated as opaque data by the firmware and
20884 * the value is returned in the `hwrm_resp_hdr` upon completion.
20888 * The target ID of the command:
20889 * * 0x0-0xFFF8 - The function ID
20890 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
20891 * * 0xFFFD - Reserved for user-space HWRM interface
20894 uint16_t target_id;
20896 * A physical address pointer pointing to a host buffer that the
20897 * command's response data will be written. This can be either a host
20898 * physical address (HPA) or a guest physical address (GPA) and must
20899 * point to a physically contiguous block of memory.
20901 uint64_t resp_addr;
20902 /* Port ID of port that is being queried. */
20904 uint8_t unused_0[6];
20907 /* hwrm_port_mac_ptp_qcfg_output (size:640b/80B) */
20908 struct hwrm_port_mac_ptp_qcfg_output {
20909 /* The specific error status for the command. */
20910 uint16_t error_code;
20911 /* The HWRM command request type. */
20913 /* The sequence ID from the original command. */
20915 /* The length of the response data in number of bytes. */
20918 * In this field, a number of PTP related flags
20919 * are used to indicate configured PTP capabilities.
20923 * When this bit is set to '1', the PTP related registers are
20924 * directly accessible by the host.
20926 #define HWRM_PORT_MAC_PTP_QCFG_OUTPUT_FLAGS_DIRECT_ACCESS \
20929 * When this bit is set to '1', the device supports one-step
20932 #define HWRM_PORT_MAC_PTP_QCFG_OUTPUT_FLAGS_ONE_STEP_TX_TS \
20935 * When this bit is set to '1', the PTP information is accessible
20936 * via HWRM commands.
20938 #define HWRM_PORT_MAC_PTP_QCFG_OUTPUT_FLAGS_HWRM_ACCESS \
20940 uint8_t unused_0[3];
20941 /* Offset of the PTP register for the lower 32 bits of timestamp for RX. */
20942 uint32_t rx_ts_reg_off_lower;
20943 /* Offset of the PTP register for the upper 32 bits of timestamp for RX. */
20944 uint32_t rx_ts_reg_off_upper;
20945 /* Offset of the PTP register for the sequence ID for RX. */
20946 uint32_t rx_ts_reg_off_seq_id;
20947 /* Offset of the first PTP source ID for RX. */
20948 uint32_t rx_ts_reg_off_src_id_0;
20949 /* Offset of the second PTP source ID for RX. */
20950 uint32_t rx_ts_reg_off_src_id_1;
20951 /* Offset of the third PTP source ID for RX. */
20952 uint32_t rx_ts_reg_off_src_id_2;
20953 /* Offset of the domain ID for RX. */
20954 uint32_t rx_ts_reg_off_domain_id;
20955 /* Offset of the PTP FIFO register for RX. */
20956 uint32_t rx_ts_reg_off_fifo;
20957 /* Offset of the PTP advance FIFO register for RX. */
20958 uint32_t rx_ts_reg_off_fifo_adv;
20959 /* PTP timestamp granularity for RX. */
20960 uint32_t rx_ts_reg_off_granularity;
20961 /* Offset of the PTP register for the lower 32 bits of timestamp for TX. */
20962 uint32_t tx_ts_reg_off_lower;
20963 /* Offset of the PTP register for the upper 32 bits of timestamp for TX. */
20964 uint32_t tx_ts_reg_off_upper;
20965 /* Offset of the PTP register for the sequence ID for TX. */
20966 uint32_t tx_ts_reg_off_seq_id;
20967 /* Offset of the PTP FIFO register for TX. */
20968 uint32_t tx_ts_reg_off_fifo;
20969 /* PTP timestamp granularity for TX. */
20970 uint32_t tx_ts_reg_off_granularity;
20971 uint8_t unused_1[7];
20973 * This field is used in Output records to indicate that the output
20974 * is completely written to RAM. This field should be read as '1'
20975 * to indicate that the output has been completely written.
20976 * When writing a command completion or response to an internal processor,
20977 * the order of writes has to be such that this field is written last.
20982 /* Port Tx Statistics Format */
20983 /* tx_port_stats (size:3264b/408B) */
20984 struct tx_port_stats {
20985 /* Total Number of 64 Bytes frames transmitted */
20986 uint64_t tx_64b_frames;
20987 /* Total Number of 65-127 Bytes frames transmitted */
20988 uint64_t tx_65b_127b_frames;
20989 /* Total Number of 128-255 Bytes frames transmitted */
20990 uint64_t tx_128b_255b_frames;
20991 /* Total Number of 256-511 Bytes frames transmitted */
20992 uint64_t tx_256b_511b_frames;
20993 /* Total Number of 512-1023 Bytes frames transmitted */
20994 uint64_t tx_512b_1023b_frames;
20995 /* Total Number of 1024-1518 Bytes frames transmitted */
20996 uint64_t tx_1024b_1518b_frames;
20998 * Total Number of each good VLAN (exludes FCS errors)
20999 * frame transmitted which is 1519 to 1522 bytes in length
21000 * inclusive (excluding framing bits but including FCS bytes).
21002 uint64_t tx_good_vlan_frames;
21003 /* Total Number of 1519-2047 Bytes frames transmitted */
21004 uint64_t tx_1519b_2047b_frames;
21005 /* Total Number of 2048-4095 Bytes frames transmitted */
21006 uint64_t tx_2048b_4095b_frames;
21007 /* Total Number of 4096-9216 Bytes frames transmitted */
21008 uint64_t tx_4096b_9216b_frames;
21009 /* Total Number of 9217-16383 Bytes frames transmitted */
21010 uint64_t tx_9217b_16383b_frames;
21011 /* Total Number of good frames transmitted */
21012 uint64_t tx_good_frames;
21013 /* Total Number of frames transmitted */
21014 uint64_t tx_total_frames;
21015 /* Total number of unicast frames transmitted */
21016 uint64_t tx_ucast_frames;
21017 /* Total number of multicast frames transmitted */
21018 uint64_t tx_mcast_frames;
21019 /* Total number of broadcast frames transmitted */
21020 uint64_t tx_bcast_frames;
21021 /* Total number of PAUSE control frames transmitted */
21022 uint64_t tx_pause_frames;
21024 * Total number of PFC/per-priority PAUSE
21025 * control frames transmitted
21027 uint64_t tx_pfc_frames;
21028 /* Total number of jabber frames transmitted */
21029 uint64_t tx_jabber_frames;
21030 /* Total number of frames transmitted with FCS error */
21031 uint64_t tx_fcs_err_frames;
21032 /* Total number of control frames transmitted */
21033 uint64_t tx_control_frames;
21034 /* Total number of over-sized frames transmitted */
21035 uint64_t tx_oversz_frames;
21036 /* Total number of frames with single deferral */
21037 uint64_t tx_single_dfrl_frames;
21038 /* Total number of frames with multiple deferrals */
21039 uint64_t tx_multi_dfrl_frames;
21040 /* Total number of frames with single collision */
21041 uint64_t tx_single_coll_frames;
21042 /* Total number of frames with multiple collisions */
21043 uint64_t tx_multi_coll_frames;
21044 /* Total number of frames with late collisions */
21045 uint64_t tx_late_coll_frames;
21046 /* Total number of frames with excessive collisions */
21047 uint64_t tx_excessive_coll_frames;
21048 /* Total number of fragmented frames transmitted */
21049 uint64_t tx_frag_frames;
21050 /* Total number of transmit errors */
21052 /* Total number of single VLAN tagged frames transmitted */
21053 uint64_t tx_tagged_frames;
21054 /* Total number of double VLAN tagged frames transmitted */
21055 uint64_t tx_dbl_tagged_frames;
21056 /* Total number of runt frames transmitted */
21057 uint64_t tx_runt_frames;
21058 /* Total number of TX FIFO under runs */
21059 uint64_t tx_fifo_underruns;
21061 * Total number of PFC frames with PFC enabled bit for
21062 * Pri 0 transmitted
21064 uint64_t tx_pfc_ena_frames_pri0;
21066 * Total number of PFC frames with PFC enabled bit for
21067 * Pri 1 transmitted
21069 uint64_t tx_pfc_ena_frames_pri1;
21071 * Total number of PFC frames with PFC enabled bit for
21072 * Pri 2 transmitted
21074 uint64_t tx_pfc_ena_frames_pri2;
21076 * Total number of PFC frames with PFC enabled bit for
21077 * Pri 3 transmitted
21079 uint64_t tx_pfc_ena_frames_pri3;
21081 * Total number of PFC frames with PFC enabled bit for
21082 * Pri 4 transmitted
21084 uint64_t tx_pfc_ena_frames_pri4;
21086 * Total number of PFC frames with PFC enabled bit for
21087 * Pri 5 transmitted
21089 uint64_t tx_pfc_ena_frames_pri5;
21091 * Total number of PFC frames with PFC enabled bit for
21092 * Pri 6 transmitted
21094 uint64_t tx_pfc_ena_frames_pri6;
21096 * Total number of PFC frames with PFC enabled bit for
21097 * Pri 7 transmitted
21099 uint64_t tx_pfc_ena_frames_pri7;
21100 /* Total number of EEE LPI Events on TX */
21101 uint64_t tx_eee_lpi_events;
21102 /* EEE LPI Duration Counter on TX */
21103 uint64_t tx_eee_lpi_duration;
21105 * Total number of Link Level Flow Control (LLFC) messages
21108 uint64_t tx_llfc_logical_msgs;
21109 /* Total number of HCFC messages transmitted */
21110 uint64_t tx_hcfc_msgs;
21111 /* Total number of TX collisions */
21112 uint64_t tx_total_collisions;
21113 /* Total number of transmitted bytes */
21115 /* Total number of end-to-end HOL frames */
21116 uint64_t tx_xthol_frames;
21117 /* Total Tx Drops per Port reported by STATS block */
21118 uint64_t tx_stat_discard;
21119 /* Total Tx Error Drops per Port reported by STATS block */
21120 uint64_t tx_stat_error;
21123 /* Port Rx Statistics Format */
21124 /* rx_port_stats (size:4224b/528B) */
21125 struct rx_port_stats {
21126 /* Total Number of 64 Bytes frames received */
21127 uint64_t rx_64b_frames;
21128 /* Total Number of 65-127 Bytes frames received */
21129 uint64_t rx_65b_127b_frames;
21130 /* Total Number of 128-255 Bytes frames received */
21131 uint64_t rx_128b_255b_frames;
21132 /* Total Number of 256-511 Bytes frames received */
21133 uint64_t rx_256b_511b_frames;
21134 /* Total Number of 512-1023 Bytes frames received */
21135 uint64_t rx_512b_1023b_frames;
21136 /* Total Number of 1024-1518 Bytes frames received */
21137 uint64_t rx_1024b_1518b_frames;
21139 * Total Number of each good VLAN (exludes FCS errors)
21140 * frame received which is 1519 to 1522 bytes in length
21141 * inclusive (excluding framing bits but including FCS bytes).
21143 uint64_t rx_good_vlan_frames;
21144 /* Total Number of 1519-2047 Bytes frames received */
21145 uint64_t rx_1519b_2047b_frames;
21146 /* Total Number of 2048-4095 Bytes frames received */
21147 uint64_t rx_2048b_4095b_frames;
21148 /* Total Number of 4096-9216 Bytes frames received */
21149 uint64_t rx_4096b_9216b_frames;
21150 /* Total Number of 9217-16383 Bytes frames received */
21151 uint64_t rx_9217b_16383b_frames;
21152 /* Total number of frames received */
21153 uint64_t rx_total_frames;
21154 /* Total number of unicast frames received */
21155 uint64_t rx_ucast_frames;
21156 /* Total number of multicast frames received */
21157 uint64_t rx_mcast_frames;
21158 /* Total number of broadcast frames received */
21159 uint64_t rx_bcast_frames;
21160 /* Total number of received frames with FCS error */
21161 uint64_t rx_fcs_err_frames;
21162 /* Total number of control frames received */
21163 uint64_t rx_ctrl_frames;
21164 /* Total number of PAUSE frames received */
21165 uint64_t rx_pause_frames;
21166 /* Total number of PFC frames received */
21167 uint64_t rx_pfc_frames;
21169 * Total number of frames received with an unsupported
21172 uint64_t rx_unsupported_opcode_frames;
21174 * Total number of frames received with an unsupported
21175 * DA for pause and PFC
21177 uint64_t rx_unsupported_da_pausepfc_frames;
21178 /* Total number of frames received with an unsupported SA */
21179 uint64_t rx_wrong_sa_frames;
21180 /* Total number of received packets with alignment error */
21181 uint64_t rx_align_err_frames;
21182 /* Total number of received frames with out-of-range length */
21183 uint64_t rx_oor_len_frames;
21184 /* Total number of received frames with error termination */
21185 uint64_t rx_code_err_frames;
21187 * Total number of received frames with a false carrier is
21188 * detected during idle, as defined by RX_ER samples active
21189 * and RXD is 0xE. The event is reported along with the
21190 * statistics generated on the next received frame. Only
21191 * one false carrier condition can be detected and logged
21194 * Carrier event, valid for 10M/100M speed modes only.
21196 uint64_t rx_false_carrier_frames;
21197 /* Total number of over-sized frames received */
21198 uint64_t rx_ovrsz_frames;
21199 /* Total number of jabber packets received */
21200 uint64_t rx_jbr_frames;
21201 /* Total number of received frames with MTU error */
21202 uint64_t rx_mtu_err_frames;
21203 /* Total number of received frames with CRC match */
21204 uint64_t rx_match_crc_frames;
21205 /* Total number of frames received promiscuously */
21206 uint64_t rx_promiscuous_frames;
21208 * Total number of received frames with one or two VLAN
21211 uint64_t rx_tagged_frames;
21212 /* Total number of received frames with two VLAN tags */
21213 uint64_t rx_double_tagged_frames;
21214 /* Total number of truncated frames received */
21215 uint64_t rx_trunc_frames;
21216 /* Total number of good frames (without errors) received */
21217 uint64_t rx_good_frames;
21219 * Total number of received PFC frames with transition from
21220 * XON to XOFF on Pri 0
21222 uint64_t rx_pfc_xon2xoff_frames_pri0;
21224 * Total number of received PFC frames with transition from
21225 * XON to XOFF on Pri 1
21227 uint64_t rx_pfc_xon2xoff_frames_pri1;
21229 * Total number of received PFC frames with transition from
21230 * XON to XOFF on Pri 2
21232 uint64_t rx_pfc_xon2xoff_frames_pri2;
21234 * Total number of received PFC frames with transition from
21235 * XON to XOFF on Pri 3
21237 uint64_t rx_pfc_xon2xoff_frames_pri3;
21239 * Total number of received PFC frames with transition from
21240 * XON to XOFF on Pri 4
21242 uint64_t rx_pfc_xon2xoff_frames_pri4;
21244 * Total number of received PFC frames with transition from
21245 * XON to XOFF on Pri 5
21247 uint64_t rx_pfc_xon2xoff_frames_pri5;
21249 * Total number of received PFC frames with transition from
21250 * XON to XOFF on Pri 6
21252 uint64_t rx_pfc_xon2xoff_frames_pri6;
21254 * Total number of received PFC frames with transition from
21255 * XON to XOFF on Pri 7
21257 uint64_t rx_pfc_xon2xoff_frames_pri7;
21259 * Total number of received PFC frames with PFC enabled
21262 uint64_t rx_pfc_ena_frames_pri0;
21264 * Total number of received PFC frames with PFC enabled
21267 uint64_t rx_pfc_ena_frames_pri1;
21269 * Total number of received PFC frames with PFC enabled
21272 uint64_t rx_pfc_ena_frames_pri2;
21274 * Total number of received PFC frames with PFC enabled
21277 uint64_t rx_pfc_ena_frames_pri3;
21279 * Total number of received PFC frames with PFC enabled
21282 uint64_t rx_pfc_ena_frames_pri4;
21284 * Total number of received PFC frames with PFC enabled
21287 uint64_t rx_pfc_ena_frames_pri5;
21289 * Total number of received PFC frames with PFC enabled
21292 uint64_t rx_pfc_ena_frames_pri6;
21294 * Total number of received PFC frames with PFC enabled
21297 uint64_t rx_pfc_ena_frames_pri7;
21298 /* Total Number of frames received with SCH CRC error */
21299 uint64_t rx_sch_crc_err_frames;
21300 /* Total Number of under-sized frames received */
21301 uint64_t rx_undrsz_frames;
21302 /* Total Number of fragmented frames received */
21303 uint64_t rx_frag_frames;
21304 /* Total number of RX EEE LPI Events */
21305 uint64_t rx_eee_lpi_events;
21306 /* EEE LPI Duration Counter on RX */
21307 uint64_t rx_eee_lpi_duration;
21309 * Total number of physical type Link Level Flow Control
21310 * (LLFC) messages received
21312 uint64_t rx_llfc_physical_msgs;
21314 * Total number of logical type Link Level Flow Control
21315 * (LLFC) messages received
21317 uint64_t rx_llfc_logical_msgs;
21319 * Total number of logical type Link Level Flow Control
21320 * (LLFC) messages received with CRC error
21322 uint64_t rx_llfc_msgs_with_crc_err;
21323 /* Total number of HCFC messages received */
21324 uint64_t rx_hcfc_msgs;
21325 /* Total number of HCFC messages received with CRC error */
21326 uint64_t rx_hcfc_msgs_with_crc_err;
21327 /* Total number of received bytes */
21329 /* Total number of bytes received in runt frames */
21330 uint64_t rx_runt_bytes;
21331 /* Total number of runt frames received */
21332 uint64_t rx_runt_frames;
21333 /* Total Rx Discards per Port reported by STATS block */
21334 uint64_t rx_stat_discard;
21335 uint64_t rx_stat_err;
21338 /********************
21339 * hwrm_port_qstats *
21340 ********************/
21343 /* hwrm_port_qstats_input (size:320b/40B) */
21344 struct hwrm_port_qstats_input {
21345 /* The HWRM command request type. */
21348 * The completion ring to send the completion event on. This should
21349 * be the NQ ID returned from the `nq_alloc` HWRM command.
21351 uint16_t cmpl_ring;
21353 * The sequence ID is used by the driver for tracking multiple
21354 * commands. This ID is treated as opaque data by the firmware and
21355 * the value is returned in the `hwrm_resp_hdr` upon completion.
21359 * The target ID of the command:
21360 * * 0x0-0xFFF8 - The function ID
21361 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
21362 * * 0xFFFD - Reserved for user-space HWRM interface
21365 uint16_t target_id;
21367 * A physical address pointer pointing to a host buffer that the
21368 * command's response data will be written. This can be either a host
21369 * physical address (HPA) or a guest physical address (GPA) and must
21370 * point to a physically contiguous block of memory.
21372 uint64_t resp_addr;
21373 /* Port ID of port that is being queried. */
21376 /* This value is not used to avoid backward compatibility issues. */
21377 #define HWRM_PORT_QSTATS_INPUT_FLAGS_UNUSED UINT32_C(0x0)
21379 * This bit is set to 1 when request is for a counter mask,
21380 * representing the width of each of the stats counters, rather
21381 * than counters themselves.
21383 #define HWRM_PORT_QSTATS_INPUT_FLAGS_COUNTER_MASK UINT32_C(0x1)
21384 #define HWRM_PORT_QSTATS_INPUT_FLAGS_LAST \
21385 HWRM_PORT_QSTATS_INPUT_FLAGS_COUNTER_MASK
21386 uint8_t unused_0[5];
21388 * This is the host address where
21389 * Tx port statistics will be stored
21391 uint64_t tx_stat_host_addr;
21393 * This is the host address where
21394 * Rx port statistics will be stored
21396 uint64_t rx_stat_host_addr;
21399 /* hwrm_port_qstats_output (size:128b/16B) */
21400 struct hwrm_port_qstats_output {
21401 /* The specific error status for the command. */
21402 uint16_t error_code;
21403 /* The HWRM command request type. */
21405 /* The sequence ID from the original command. */
21407 /* The length of the response data in number of bytes. */
21409 /* The size of TX port statistics block in bytes. */
21410 uint16_t tx_stat_size;
21411 /* The size of RX port statistics block in bytes. */
21412 uint16_t rx_stat_size;
21413 uint8_t unused_0[3];
21415 * This field is used in Output records to indicate that the output
21416 * is completely written to RAM. This field should be read as '1'
21417 * to indicate that the output has been completely written.
21418 * When writing a command completion or response to an internal processor,
21419 * the order of writes has to be such that this field is written last.
21424 /* Port Tx Statistics extended Format */
21425 /* tx_port_stats_ext (size:2048b/256B) */
21426 struct tx_port_stats_ext {
21427 /* Total number of tx bytes count on cos queue 0 */
21428 uint64_t tx_bytes_cos0;
21429 /* Total number of tx bytes count on cos queue 1 */
21430 uint64_t tx_bytes_cos1;
21431 /* Total number of tx bytes count on cos queue 2 */
21432 uint64_t tx_bytes_cos2;
21433 /* Total number of tx bytes count on cos queue 3 */
21434 uint64_t tx_bytes_cos3;
21435 /* Total number of tx bytes count on cos queue 4 */
21436 uint64_t tx_bytes_cos4;
21437 /* Total number of tx bytes count on cos queue 5 */
21438 uint64_t tx_bytes_cos5;
21439 /* Total number of tx bytes count on cos queue 6 */
21440 uint64_t tx_bytes_cos6;
21441 /* Total number of tx bytes count on cos queue 7 */
21442 uint64_t tx_bytes_cos7;
21443 /* Total number of tx packets count on cos queue 0 */
21444 uint64_t tx_packets_cos0;
21445 /* Total number of tx packets count on cos queue 1 */
21446 uint64_t tx_packets_cos1;
21447 /* Total number of tx packets count on cos queue 2 */
21448 uint64_t tx_packets_cos2;
21449 /* Total number of tx packets count on cos queue 3 */
21450 uint64_t tx_packets_cos3;
21451 /* Total number of tx packets count on cos queue 4 */
21452 uint64_t tx_packets_cos4;
21453 /* Total number of tx packets count on cos queue 5 */
21454 uint64_t tx_packets_cos5;
21455 /* Total number of tx packets count on cos queue 6 */
21456 uint64_t tx_packets_cos6;
21457 /* Total number of tx packets count on cos queue 7 */
21458 uint64_t tx_packets_cos7;
21459 /* time duration between transmitting a XON -> XOFF and a subsequent XOFF -> XON for priority 0 */
21460 uint64_t pfc_pri0_tx_duration_us;
21461 /* Number of times, a XON -> XOFF and XOFF -> XON transitions occur for priority 0 */
21462 uint64_t pfc_pri0_tx_transitions;
21463 /* time duration between transmitting a XON -> XOFF and a subsequent XOFF -> XON for priority 1 */
21464 uint64_t pfc_pri1_tx_duration_us;
21465 /* Number of times, a XON -> XOFF and XOFF -> XON transitions occur for priority 1 */
21466 uint64_t pfc_pri1_tx_transitions;
21467 /* time duration between transmitting a XON -> XOFF and a subsequent XOFF -> XON for priority 2 */
21468 uint64_t pfc_pri2_tx_duration_us;
21469 /* Number of times, a XON -> XOFF and XOFF -> XON transitions occur for priority 2 */
21470 uint64_t pfc_pri2_tx_transitions;
21471 /* time duration between transmitting a XON -> XOFF and a subsequent XOFF -> XON for priority 3 */
21472 uint64_t pfc_pri3_tx_duration_us;
21473 /* Number of times, a XON -> XOFF and XOFF -> XON transitions occur for priority 3 */
21474 uint64_t pfc_pri3_tx_transitions;
21475 /* time duration between transmitting a XON -> XOFF and a subsequent XOFF -> XON for priority 4 */
21476 uint64_t pfc_pri4_tx_duration_us;
21477 /* Number of times, a XON -> XOFF and XOFF -> XON transitions occur for priority 4 */
21478 uint64_t pfc_pri4_tx_transitions;
21479 /* time duration between transmitting a XON -> XOFF and a subsequent XOFF -> XON for priority 5 */
21480 uint64_t pfc_pri5_tx_duration_us;
21481 /* Number of times, a XON -> XOFF and XOFF -> XON transitions occur for priority 5 */
21482 uint64_t pfc_pri5_tx_transitions;
21483 /* time duration between transmitting a XON -> XOFF and a subsequent XOFF -> XON for priority 6 */
21484 uint64_t pfc_pri6_tx_duration_us;
21485 /* Number of times, a XON -> XOFF and XOFF -> XON transitions occur for priority 6 */
21486 uint64_t pfc_pri6_tx_transitions;
21487 /* time duration between transmitting a XON -> XOFF and a subsequent XOFF -> XON for priority 7 */
21488 uint64_t pfc_pri7_tx_duration_us;
21489 /* Number of times, a XON -> XOFF and XOFF -> XON transitions occur for priority 7 */
21490 uint64_t pfc_pri7_tx_transitions;
21493 /* Port Rx Statistics extended Format */
21494 /* rx_port_stats_ext (size:3648b/456B) */
21495 struct rx_port_stats_ext {
21496 /* Number of times link state changed to down */
21497 uint64_t link_down_events;
21498 /* Number of times the idle rings with pause bit are found */
21499 uint64_t continuous_pause_events;
21500 /* Number of times the active rings pause bit resumed back */
21501 uint64_t resume_pause_events;
21502 /* Number of times, the ROCE cos queue PFC is disabled to avoid pause flood/burst */
21503 uint64_t continuous_roce_pause_events;
21504 /* Number of times, the ROCE cos queue PFC is enabled back */
21505 uint64_t resume_roce_pause_events;
21506 /* Total number of rx bytes count on cos queue 0 */
21507 uint64_t rx_bytes_cos0;
21508 /* Total number of rx bytes count on cos queue 1 */
21509 uint64_t rx_bytes_cos1;
21510 /* Total number of rx bytes count on cos queue 2 */
21511 uint64_t rx_bytes_cos2;
21512 /* Total number of rx bytes count on cos queue 3 */
21513 uint64_t rx_bytes_cos3;
21514 /* Total number of rx bytes count on cos queue 4 */
21515 uint64_t rx_bytes_cos4;
21516 /* Total number of rx bytes count on cos queue 5 */
21517 uint64_t rx_bytes_cos5;
21518 /* Total number of rx bytes count on cos queue 6 */
21519 uint64_t rx_bytes_cos6;
21520 /* Total number of rx bytes count on cos queue 7 */
21521 uint64_t rx_bytes_cos7;
21522 /* Total number of rx packets count on cos queue 0 */
21523 uint64_t rx_packets_cos0;
21524 /* Total number of rx packets count on cos queue 1 */
21525 uint64_t rx_packets_cos1;
21526 /* Total number of rx packets count on cos queue 2 */
21527 uint64_t rx_packets_cos2;
21528 /* Total number of rx packets count on cos queue 3 */
21529 uint64_t rx_packets_cos3;
21530 /* Total number of rx packets count on cos queue 4 */
21531 uint64_t rx_packets_cos4;
21532 /* Total number of rx packets count on cos queue 5 */
21533 uint64_t rx_packets_cos5;
21534 /* Total number of rx packets count on cos queue 6 */
21535 uint64_t rx_packets_cos6;
21536 /* Total number of rx packets count on cos queue 7 */
21537 uint64_t rx_packets_cos7;
21538 /* time duration receiving a XON -> XOFF and a subsequent XOFF -> XON for priority 0 */
21539 uint64_t pfc_pri0_rx_duration_us;
21540 /* Number of times, a XON -> XOFF and XOFF -> XON transitions occur for priority 0 */
21541 uint64_t pfc_pri0_rx_transitions;
21542 /* time duration receiving a XON -> XOFF and a subsequent XOFF -> XON for priority 1 */
21543 uint64_t pfc_pri1_rx_duration_us;
21544 /* Number of times, a XON -> XOFF and XOFF -> XON transitions occur for priority 1 */
21545 uint64_t pfc_pri1_rx_transitions;
21546 /* time duration receiving a XON -> XOFF and a subsequent XOFF -> XON for priority 2 */
21547 uint64_t pfc_pri2_rx_duration_us;
21548 /* Number of times, a XON -> XOFF and XOFF -> XON transitions occur for priority 2 */
21549 uint64_t pfc_pri2_rx_transitions;
21550 /* time duration receiving a XON -> XOFF and a subsequent XOFF -> XON for priority 3 */
21551 uint64_t pfc_pri3_rx_duration_us;
21552 /* Number of times, a XON -> XOFF and XOFF -> XON transitions occur for priority 3 */
21553 uint64_t pfc_pri3_rx_transitions;
21554 /* time duration receiving a XON -> XOFF and a subsequent XOFF -> XON for priority 4 */
21555 uint64_t pfc_pri4_rx_duration_us;
21556 /* Number of times, a XON -> XOFF and XOFF -> XON transitions occur for priority 4 */
21557 uint64_t pfc_pri4_rx_transitions;
21558 /* time duration receiving a XON -> XOFF and a subsequent XOFF -> XON for priority 5 */
21559 uint64_t pfc_pri5_rx_duration_us;
21560 /* Number of times, a XON -> XOFF and XOFF -> XON transitions occur for priority 5 */
21561 uint64_t pfc_pri5_rx_transitions;
21562 /* time duration receiving a XON -> XOFF and a subsequent XOFF -> XON for priority 6 */
21563 uint64_t pfc_pri6_rx_duration_us;
21564 /* Number of times, a XON -> XOFF and XOFF -> XON transitions occur for priority 6 */
21565 uint64_t pfc_pri6_rx_transitions;
21566 /* time duration receiving a XON -> XOFF and a subsequent XOFF -> XON for priority 7 */
21567 uint64_t pfc_pri7_rx_duration_us;
21568 /* Number of times, a XON -> XOFF and XOFF -> XON transitions occur for priority 7 */
21569 uint64_t pfc_pri7_rx_transitions;
21570 /* Total number of received bits */
21572 /* The number of events where the port receive buffer was over 85% full */
21573 uint64_t rx_buffer_passed_threshold;
21575 * The number of symbol errors that wasn't corrected by FEC correction
21578 uint64_t rx_pcs_symbol_err;
21579 /* The number of corrected bits on the port according to active FEC */
21580 uint64_t rx_corrected_bits;
21581 /* Total number of rx discard bytes count on cos queue 0 */
21582 uint64_t rx_discard_bytes_cos0;
21583 /* Total number of rx discard bytes count on cos queue 1 */
21584 uint64_t rx_discard_bytes_cos1;
21585 /* Total number of rx discard bytes count on cos queue 2 */
21586 uint64_t rx_discard_bytes_cos2;
21587 /* Total number of rx discard bytes count on cos queue 3 */
21588 uint64_t rx_discard_bytes_cos3;
21589 /* Total number of rx discard bytes count on cos queue 4 */
21590 uint64_t rx_discard_bytes_cos4;
21591 /* Total number of rx discard bytes count on cos queue 5 */
21592 uint64_t rx_discard_bytes_cos5;
21593 /* Total number of rx discard bytes count on cos queue 6 */
21594 uint64_t rx_discard_bytes_cos6;
21595 /* Total number of rx discard bytes count on cos queue 7 */
21596 uint64_t rx_discard_bytes_cos7;
21597 /* Total number of rx discard packets count on cos queue 0 */
21598 uint64_t rx_discard_packets_cos0;
21599 /* Total number of rx discard packets count on cos queue 1 */
21600 uint64_t rx_discard_packets_cos1;
21601 /* Total number of rx discard packets count on cos queue 2 */
21602 uint64_t rx_discard_packets_cos2;
21603 /* Total number of rx discard packets count on cos queue 3 */
21604 uint64_t rx_discard_packets_cos3;
21605 /* Total number of rx discard packets count on cos queue 4 */
21606 uint64_t rx_discard_packets_cos4;
21607 /* Total number of rx discard packets count on cos queue 5 */
21608 uint64_t rx_discard_packets_cos5;
21609 /* Total number of rx discard packets count on cos queue 6 */
21610 uint64_t rx_discard_packets_cos6;
21611 /* Total number of rx discard packets count on cos queue 7 */
21612 uint64_t rx_discard_packets_cos7;
21616 * Port Rx Statistics extended PFC WatchDog Format.
21617 * StormDetect and StormRevert event determination is based
21618 * on an integration period and a percentage threshold.
21619 * StormDetect event - when percentage of XOFF frames received
21620 * within an integration period exceeds the configured threshold.
21621 * StormRevert event - when percentage of XON frames received
21622 * within an integration period exceeds the configured threshold.
21623 * Actual number of XOFF/XON frames for the events to be triggered
21624 * depends on both configured integration period and sampling rate.
21625 * The statistics in this structure represent counts of specified
21626 * events from the moment the feature (PFC WatchDog) is enabled via
21627 * hwrm_queue_pfc_enable_cfg call.
21629 /* rx_port_stats_ext_pfc_wd (size:5120b/640B) */
21630 struct rx_port_stats_ext_pfc_wd {
21632 * Total number of PFC WatchDog StormDetect events detected
21635 uint64_t rx_pfc_watchdog_storms_detected_pri0;
21637 * Total number of PFC WatchDog StormDetect events detected
21640 uint64_t rx_pfc_watchdog_storms_detected_pri1;
21642 * Total number of PFC WatchDog StormDetect events detected
21645 uint64_t rx_pfc_watchdog_storms_detected_pri2;
21647 * Total number of PFC WatchDog StormDetect events detected
21650 uint64_t rx_pfc_watchdog_storms_detected_pri3;
21652 * Total number of PFC WatchDog StormDetect events detected
21655 uint64_t rx_pfc_watchdog_storms_detected_pri4;
21657 * Total number of PFC WatchDog StormDetect events detected
21660 uint64_t rx_pfc_watchdog_storms_detected_pri5;
21662 * Total number of PFC WatchDog StormDetect events detected
21665 uint64_t rx_pfc_watchdog_storms_detected_pri6;
21667 * Total number of PFC WatchDog StormDetect events detected
21670 uint64_t rx_pfc_watchdog_storms_detected_pri7;
21672 * Total number of PFC WatchDog StormRevert events detected
21675 uint64_t rx_pfc_watchdog_storms_reverted_pri0;
21677 * Total number of PFC WatchDog StormRevert events detected
21680 uint64_t rx_pfc_watchdog_storms_reverted_pri1;
21682 * Total number of PFC WatchDog StormRevert events detected
21685 uint64_t rx_pfc_watchdog_storms_reverted_pri2;
21687 * Total number of PFC WatchDog StormRevert events detected
21690 uint64_t rx_pfc_watchdog_storms_reverted_pri3;
21692 * Total number of PFC WatchDog StormRevert events detected
21695 uint64_t rx_pfc_watchdog_storms_reverted_pri4;
21697 * Total number of PFC WatchDog StormRevert events detected
21700 uint64_t rx_pfc_watchdog_storms_reverted_pri5;
21702 * Total number of PFC WatchDog StormRevert events detected
21705 uint64_t rx_pfc_watchdog_storms_reverted_pri6;
21707 * Total number of PFC WatchDog StormRevert events detected
21710 uint64_t rx_pfc_watchdog_storms_reverted_pri7;
21712 * Total number of packets received during PFC watchdog storm
21715 uint64_t rx_pfc_watchdog_storms_rx_packets_pri0;
21717 * Total number of packets received during PFC watchdog storm
21720 uint64_t rx_pfc_watchdog_storms_rx_packets_pri1;
21722 * Total number of packets received during PFC watchdog storm
21725 uint64_t rx_pfc_watchdog_storms_rx_packets_pri2;
21727 * Total number of packets received during PFC watchdog storm
21730 uint64_t rx_pfc_watchdog_storms_rx_packets_pri3;
21732 * Total number of packets received during PFC watchdog storm
21735 uint64_t rx_pfc_watchdog_storms_rx_packets_pri4;
21737 * Total number of packets received during PFC watchdog storm
21740 uint64_t rx_pfc_watchdog_storms_rx_packets_pri5;
21742 * Total number of packets received during PFC watchdog storm
21745 uint64_t rx_pfc_watchdog_storms_rx_packets_pri6;
21747 * Total number of packets received during PFC watchdog storm
21750 uint64_t rx_pfc_watchdog_storms_rx_packets_pri7;
21752 * Total number of bytes received during PFC watchdog storm
21755 uint64_t rx_pfc_watchdog_storms_rx_bytes_pri0;
21757 * Total number of bytes received during PFC watchdog storm
21760 uint64_t rx_pfc_watchdog_storms_rx_bytes_pri1;
21762 * Total number of bytes received during PFC watchdog storm
21765 uint64_t rx_pfc_watchdog_storms_rx_bytes_pri2;
21767 * Total number of bytes received during PFC watchdog storm
21770 uint64_t rx_pfc_watchdog_storms_rx_bytes_pri3;
21772 * Total number of bytes received during PFC watchdog storm
21775 uint64_t rx_pfc_watchdog_storms_rx_bytes_pri4;
21777 * Total number of bytes received during PFC watchdog storm
21780 uint64_t rx_pfc_watchdog_storms_rx_bytes_pri5;
21782 * Total number of bytes received during PFC watchdog storm
21785 uint64_t rx_pfc_watchdog_storms_rx_bytes_pri6;
21787 * Total number of bytes received during PFC watchdog storm
21790 uint64_t rx_pfc_watchdog_storms_rx_bytes_pri7;
21792 * Total number of packets dropped on rx during PFC watchdog storm
21795 uint64_t rx_pfc_watchdog_storms_rx_packets_dropped_pri0;
21797 * Total number of packets dropped on rx during PFC watchdog storm
21800 uint64_t rx_pfc_watchdog_storms_rx_packets_dropped_pri1;
21802 * Total number of packets dropped on rx during PFC watchdog storm
21805 uint64_t rx_pfc_watchdog_storms_rx_packets_dropped_pri2;
21807 * Total number of packets dropped on rx during PFC watchdog storm
21810 uint64_t rx_pfc_watchdog_storms_rx_packets_dropped_pri3;
21812 * Total number of packets dropped on rx during PFC watchdog storm
21815 uint64_t rx_pfc_watchdog_storms_rx_packets_dropped_pri4;
21817 * Total number of packets dropped on rx during PFC watchdog storm
21820 uint64_t rx_pfc_watchdog_storms_rx_packets_dropped_pri5;
21822 * Total number of packets dropped on rx during PFC watchdog storm
21825 uint64_t rx_pfc_watchdog_storms_rx_packets_dropped_pri6;
21827 * Total number of packets dropped on rx during PFC watchdog storm
21830 uint64_t rx_pfc_watchdog_storms_rx_packets_dropped_pri7;
21832 * Total number of bytes dropped on rx during PFC watchdog storm
21835 uint64_t rx_pfc_watchdog_storms_rx_bytes_dropped_pri0;
21837 * Total number of bytes dropped on rx during PFC watchdog storm
21840 uint64_t rx_pfc_watchdog_storms_rx_bytes_dropped_pri1;
21842 * Total number of bytes dropped on rx during PFC watchdog storm
21845 uint64_t rx_pfc_watchdog_storms_rx_bytes_dropped_pri2;
21847 * Total number of bytes dropped on rx during PFC watchdog storm
21850 uint64_t rx_pfc_watchdog_storms_rx_bytes_dropped_pri3;
21852 * Total number of bytes dropped on rx during PFC watchdog storm
21855 uint64_t rx_pfc_watchdog_storms_rx_bytes_dropped_pri4;
21857 * Total number of bytes dropped on rx during PFC watchdog storm
21860 uint64_t rx_pfc_watchdog_storms_rx_bytes_dropped_pri5;
21862 * Total number of bytes dropped on rx during PFC watchdog storm
21865 uint64_t rx_pfc_watchdog_storms_rx_bytes_dropped_pri6;
21867 * Total number of bytes dropped on rx during PFC watchdog storm
21870 uint64_t rx_pfc_watchdog_storms_rx_bytes_dropped_pri7;
21872 * Number of packets received during last PFC watchdog storm
21875 uint64_t rx_pfc_watchdog_last_storm_rx_packets_pri0;
21877 * Number of packets received during last PFC watchdog storm
21880 uint64_t rx_pfc_watchdog_last_storm_rx_packets_pri1;
21882 * Number of packets received during last PFC watchdog storm
21885 uint64_t rx_pfc_watchdog_last_storm_rx_packets_pri2;
21887 * Number of packets received during last PFC watchdog storm
21890 uint64_t rx_pfc_watchdog_last_storm_rx_packets_pri3;
21892 * Number of packets received during last PFC watchdog storm
21895 uint64_t rx_pfc_watchdog_last_storm_rx_packets_pri4;
21897 * Number of packets received during last PFC watchdog storm
21900 uint64_t rx_pfc_watchdog_last_storm_rx_packets_pri5;
21902 * Number of packets received during last PFC watchdog storm
21905 uint64_t rx_pfc_watchdog_last_storm_rx_packets_pri6;
21907 * Number of packets received during last PFC watchdog storm
21910 uint64_t rx_pfc_watchdog_last_storm_rx_packets_pri7;
21912 * Number of bytes received during last PFC watchdog storm
21915 uint64_t rx_pfc_watchdog_last_storm_rx_bytes_pri0;
21917 * Number of bytes received during last PFC watchdog storm
21920 uint64_t rx_pfc_watchdog_last_storm_rx_bytes_pri1;
21922 * Number of bytes received during last PFC watchdog storm
21925 uint64_t rx_pfc_watchdog_last_storm_rx_bytes_pri2;
21927 * Number of bytes received during last PFC watchdog storm
21930 uint64_t rx_pfc_watchdog_last_storm_rx_bytes_pri3;
21932 * Number of bytes received during last PFC watchdog storm
21935 uint64_t rx_pfc_watchdog_last_storm_rx_bytes_pri4;
21937 * Number of bytes received during last PFC watchdog storm
21940 uint64_t rx_pfc_watchdog_last_storm_rx_bytes_pri5;
21942 * Number of bytes received during last PFC watchdog storm
21945 uint64_t rx_pfc_watchdog_last_storm_rx_bytes_pri6;
21947 * Number of bytes received during last PFC watchdog storm
21950 uint64_t rx_pfc_watchdog_last_storm_rx_bytes_pri7;
21952 * Number of packets dropped on rx during last PFC watchdog storm
21955 uint64_t rx_pfc_watchdog_last_storm_rx_packets_dropped_pri0;
21957 * Number of packets dropped on rx during last PFC watchdog storm
21960 uint64_t rx_pfc_watchdog_last_storm_rx_packets_dropped_pri1;
21962 * Number of packets dropped on rx during last PFC watchdog storm
21965 uint64_t rx_pfc_watchdog_last_storm_rx_packets_dropped_pri2;
21967 * Number of packets dropped on rx during last PFC watchdog storm
21970 uint64_t rx_pfc_watchdog_last_storm_rx_packets_dropped_pri3;
21972 * Number of packets dropped on rx during last PFC watchdog storm
21975 uint64_t rx_pfc_watchdog_last_storm_rx_packets_dropped_pri4;
21977 * Number of packets dropped on rx during last PFC watchdog storm
21980 uint64_t rx_pfc_watchdog_last_storm_rx_packets_dropped_pri5;
21982 * Number of packets dropped on rx during last PFC watchdog storm
21985 uint64_t rx_pfc_watchdog_last_storm_rx_packets_dropped_pri6;
21987 * Number of packets dropped on rx during last PFC watchdog storm
21990 uint64_t rx_pfc_watchdog_last_storm_rx_packets_dropped_pri7;
21992 * Total number of bytes dropped on rx during PFC watchdog storm
21995 uint64_t rx_pfc_watchdog_last_storm_rx_bytes_dropped_pri0;
21997 * Number of bytes dropped on rx during last PFC watchdog storm
22000 uint64_t rx_pfc_watchdog_last_storm_rx_bytes_dropped_pri1;
22002 * Number of bytes dropped on rx during last PFC watchdog storm
22005 uint64_t rx_pfc_watchdog_last_storm_rx_bytes_dropped_pri2;
22007 * Number of bytes dropped on rx during last PFC watchdog storm
22010 uint64_t rx_pfc_watchdog_last_storm_rx_bytes_dropped_pri3;
22012 * Number of bytes dropped on rx during last PFC watchdog storm
22015 uint64_t rx_pfc_watchdog_last_storm_rx_bytes_dropped_pri4;
22017 * Number of bytes dropped on rx during last PFC watchdog storm
22020 uint64_t rx_pfc_watchdog_last_storm_rx_bytes_dropped_pri5;
22022 * Number of bytes dropped on rx during last PFC watchdog storm
22025 uint64_t rx_pfc_watchdog_last_storm_rx_bytes_dropped_pri6;
22027 * Number of bytes dropped on rx during last PFC watchdog storm
22030 uint64_t rx_pfc_watchdog_last_storm_rx_bytes_dropped_pri7;
22033 /************************
22034 * hwrm_port_qstats_ext *
22035 ************************/
22038 /* hwrm_port_qstats_ext_input (size:320b/40B) */
22039 struct hwrm_port_qstats_ext_input {
22040 /* The HWRM command request type. */
22043 * The completion ring to send the completion event on. This should
22044 * be the NQ ID returned from the `nq_alloc` HWRM command.
22046 uint16_t cmpl_ring;
22048 * The sequence ID is used by the driver for tracking multiple
22049 * commands. This ID is treated as opaque data by the firmware and
22050 * the value is returned in the `hwrm_resp_hdr` upon completion.
22054 * The target ID of the command:
22055 * * 0x0-0xFFF8 - The function ID
22056 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
22057 * * 0xFFFD - Reserved for user-space HWRM interface
22060 uint16_t target_id;
22062 * A physical address pointer pointing to a host buffer that the
22063 * command's response data will be written. This can be either a host
22064 * physical address (HPA) or a guest physical address (GPA) and must
22065 * point to a physically contiguous block of memory.
22067 uint64_t resp_addr;
22068 /* Port ID of port that is being queried. */
22071 * The size of TX port extended
22072 * statistics block in bytes.
22074 uint16_t tx_stat_size;
22076 * The size of RX port extended
22077 * statistics block in bytes
22079 uint16_t rx_stat_size;
22081 /* This value is not used to avoid backward compatibility issues. */
22082 #define HWRM_PORT_QSTATS_EXT_INPUT_FLAGS_UNUSED UINT32_C(0x0)
22084 * This bit is set to 1 when request is for the counter mask,
22085 * representing width of each of the stats counters, rather than
22086 * counters themselves.
22088 #define HWRM_PORT_QSTATS_EXT_INPUT_FLAGS_COUNTER_MASK UINT32_C(0x1)
22089 #define HWRM_PORT_QSTATS_EXT_INPUT_FLAGS_LAST \
22090 HWRM_PORT_QSTATS_EXT_INPUT_FLAGS_COUNTER_MASK
22093 * This is the host address where
22094 * Tx port statistics will be stored
22096 uint64_t tx_stat_host_addr;
22098 * This is the host address where
22099 * Rx port statistics will be stored
22101 uint64_t rx_stat_host_addr;
22104 /* hwrm_port_qstats_ext_output (size:128b/16B) */
22105 struct hwrm_port_qstats_ext_output {
22106 /* The specific error status for the command. */
22107 uint16_t error_code;
22108 /* The HWRM command request type. */
22110 /* The sequence ID from the original command. */
22112 /* The length of the response data in number of bytes. */
22114 /* The size of TX port statistics block in bytes. */
22115 uint16_t tx_stat_size;
22116 /* The size of RX port statistics block in bytes. */
22117 uint16_t rx_stat_size;
22118 /* Total number of active cos queues available. */
22119 uint16_t total_active_cos_queues;
22122 * If set to 1, then this field indicates that clear
22123 * roce specific counters is supported.
22125 #define HWRM_PORT_QSTATS_EXT_OUTPUT_FLAGS_CLEAR_ROCE_COUNTERS_SUPPORTED \
22128 * This field is used in Output records to indicate that the output
22129 * is completely written to RAM. This field should be read as '1'
22130 * to indicate that the output has been completely written.
22131 * When writing a command completion or response to an internal processor,
22132 * the order of writes has to be such that this field is written last.
22137 /*******************************
22138 * hwrm_port_qstats_ext_pfc_wd *
22139 *******************************/
22142 /* hwrm_port_qstats_ext_pfc_wd_input (size:256b/32B) */
22143 struct hwrm_port_qstats_ext_pfc_wd_input {
22144 /* The HWRM command request type. */
22147 * The completion ring to send the completion event on. This should
22148 * be the NQ ID returned from the `nq_alloc` HWRM command.
22150 uint16_t cmpl_ring;
22152 * The sequence ID is used by the driver for tracking multiple
22153 * commands. This ID is treated as opaque data by the firmware and
22154 * the value is returned in the `hwrm_resp_hdr` upon completion.
22158 * The target ID of the command:
22159 * * 0x0-0xFFF8 - The function ID
22160 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
22161 * * 0xFFFD - Reserved for user-space HWRM interface
22164 uint16_t target_id;
22166 * A physical address pointer pointing to a host buffer that the
22167 * command's response data will be written. This can be either a host
22168 * physical address (HPA) or a guest physical address (GPA) and must
22169 * point to a physically contiguous block of memory.
22171 uint64_t resp_addr;
22172 /* Port ID of port that is being queried. */
22175 * The size of rx_port_stats_ext_pfc_wd
22178 uint16_t pfc_wd_stat_size;
22179 uint8_t unused_0[4];
22181 * This is the host address where
22182 * rx_port_stats_ext_pfc_wd will be stored
22184 uint64_t pfc_wd_stat_host_addr;
22187 /* hwrm_port_qstats_ext_pfc_wd_output (size:128b/16B) */
22188 struct hwrm_port_qstats_ext_pfc_wd_output {
22189 /* The specific error status for the command. */
22190 uint16_t error_code;
22191 /* The HWRM command request type. */
22193 /* The sequence ID from the original command. */
22195 /* The length of the response data in number of bytes. */
22198 * The size of rx_port_stats_ext_pfc_wd
22199 * statistics block in bytes.
22201 uint16_t pfc_wd_stat_size;
22204 * This field is used in Output records to indicate that the output
22205 * is completely written to RAM. This field should be read as '1'
22206 * to indicate that the output has been completely written.
22207 * When writing a command completion or response to an internal processor,
22208 * the order of writes has to be such that this field is written last.
22211 uint8_t unused_0[4];
22214 /*************************
22215 * hwrm_port_lpbk_qstats *
22216 *************************/
22219 /* hwrm_port_lpbk_qstats_input (size:128b/16B) */
22220 struct hwrm_port_lpbk_qstats_input {
22221 /* The HWRM command request type. */
22224 * The completion ring to send the completion event on. This should
22225 * be the NQ ID returned from the `nq_alloc` HWRM command.
22227 uint16_t cmpl_ring;
22229 * The sequence ID is used by the driver for tracking multiple
22230 * commands. This ID is treated as opaque data by the firmware and
22231 * the value is returned in the `hwrm_resp_hdr` upon completion.
22235 * The target ID of the command:
22236 * * 0x0-0xFFF8 - The function ID
22237 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
22238 * * 0xFFFD - Reserved for user-space HWRM interface
22241 uint16_t target_id;
22243 * A physical address pointer pointing to a host buffer that the
22244 * command's response data will be written. This can be either a host
22245 * physical address (HPA) or a guest physical address (GPA) and must
22246 * point to a physically contiguous block of memory.
22248 uint64_t resp_addr;
22251 /* hwrm_port_lpbk_qstats_output (size:768b/96B) */
22252 struct hwrm_port_lpbk_qstats_output {
22253 /* The specific error status for the command. */
22254 uint16_t error_code;
22255 /* The HWRM command request type. */
22257 /* The sequence ID from the original command. */
22259 /* The length of the response data in number of bytes. */
22261 /* Number of transmitted unicast frames */
22262 uint64_t lpbk_ucast_frames;
22263 /* Number of transmitted multicast frames */
22264 uint64_t lpbk_mcast_frames;
22265 /* Number of transmitted broadcast frames */
22266 uint64_t lpbk_bcast_frames;
22267 /* Number of transmitted bytes for unicast traffic */
22268 uint64_t lpbk_ucast_bytes;
22269 /* Number of transmitted bytes for multicast traffic */
22270 uint64_t lpbk_mcast_bytes;
22271 /* Number of transmitted bytes for broadcast traffic */
22272 uint64_t lpbk_bcast_bytes;
22273 /* Total Tx Drops for loopback traffic reported by STATS block */
22274 uint64_t tx_stat_discard;
22275 /* Total Tx Error Drops for loopback traffic reported by STATS block */
22276 uint64_t tx_stat_error;
22277 /* Total Rx Drops for loopback traffic reported by STATS block */
22278 uint64_t rx_stat_discard;
22279 /* Total Rx Error Drops for loopback traffic reported by STATS block */
22280 uint64_t rx_stat_error;
22281 uint8_t unused_0[7];
22283 * This field is used in Output records to indicate that the output
22284 * is completely written to RAM. This field should be read as '1'
22285 * to indicate that the output has been completely written.
22286 * When writing a command completion or response to an internal processor,
22287 * the order of writes has to be such that this field is written last.
22292 /************************
22293 * hwrm_port_ecn_qstats *
22294 ************************/
22297 /* hwrm_port_ecn_qstats_input (size:256b/32B) */
22298 struct hwrm_port_ecn_qstats_input {
22299 /* The HWRM command request type. */
22302 * The completion ring to send the completion event on. This should
22303 * be the NQ ID returned from the `nq_alloc` HWRM command.
22305 uint16_t cmpl_ring;
22307 * The sequence ID is used by the driver for tracking multiple
22308 * commands. This ID is treated as opaque data by the firmware and
22309 * the value is returned in the `hwrm_resp_hdr` upon completion.
22313 * The target ID of the command:
22314 * * 0x0-0xFFF8 - The function ID
22315 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
22316 * * 0xFFFD - Reserved for user-space HWRM interface
22319 uint16_t target_id;
22321 * A physical address pointer pointing to a host buffer that the
22322 * command's response data will be written. This can be either a host
22323 * physical address (HPA) or a guest physical address (GPA) and must
22324 * point to a physically contiguous block of memory.
22326 uint64_t resp_addr;
22328 * Port ID of port that is being queried. Unused if NIC is in
22333 * Size of the DMA buffer the caller has allocated for the firmware to
22336 uint16_t ecn_stat_buf_size;
22338 /* This value is not used to avoid backward compatibility issues. */
22339 #define HWRM_PORT_ECN_QSTATS_INPUT_FLAGS_UNUSED UINT32_C(0x0)
22341 * This bit is set to 1 when request is for a counter mask,
22342 * representing the width of each of the stats counters, rather
22343 * than counters themselves.
22345 #define HWRM_PORT_ECN_QSTATS_INPUT_FLAGS_COUNTER_MASK UINT32_C(0x1)
22346 #define HWRM_PORT_ECN_QSTATS_INPUT_FLAGS_LAST \
22347 HWRM_PORT_ECN_QSTATS_INPUT_FLAGS_COUNTER_MASK
22348 uint8_t unused_0[3];
22350 * This is the host address where
22351 * ECN port statistics will be stored
22353 uint64_t ecn_stat_host_addr;
22356 /* hwrm_port_ecn_qstats_output (size:128b/16B) */
22357 struct hwrm_port_ecn_qstats_output {
22358 /* The specific error status for the command. */
22359 uint16_t error_code;
22360 /* The HWRM command request type. */
22362 /* The sequence ID from the original command. */
22364 /* The length of the response data in number of bytes. */
22366 /* Number of bytes of stats the firmware wrote to the DMA buffer. */
22367 uint16_t ecn_stat_buf_size;
22369 * Bitmask that indicates which CoS queues have ECN marking enabled.
22370 * Bit i corresponds to CoS queue i.
22373 uint8_t unused_0[4];
22375 * This field is used in Output records to indicate that the output
22376 * is completely written to RAM. This field should be read as '1'
22377 * to indicate that the output has been completely written.
22378 * When writing a command completion or response to an internal processor,
22379 * the order of writes has to be such that this field is written last.
22384 /* ECN mark statistics format */
22385 /* port_stats_ecn (size:512b/64B) */
22386 struct port_stats_ecn {
22388 * Number of packets marked in CoS queue 0.
22389 * Or, if the driver requested counter masks, a mask to indicate the size
22392 uint64_t mark_cnt_cos0;
22394 * Number of packets marked in CoS queue 1.
22395 * Or, if the driver requested counter masks, a mask to indicate the size
22398 uint64_t mark_cnt_cos1;
22400 * Number of packets marked in CoS queue 2.
22401 * Or, if the driver requested counter masks, a mask to indicate the size
22404 uint64_t mark_cnt_cos2;
22406 * Number of packets marked in CoS queue 3.
22407 * Or, if the driver requested counter masks, a mask to indicate the size
22410 uint64_t mark_cnt_cos3;
22412 * Number of packets marked in CoS queue 4.
22413 * Or, if the driver requested counter masks, a mask to indicate the size
22416 uint64_t mark_cnt_cos4;
22418 * Number of packets marked in CoS queue 5.
22419 * Or, if the driver requested counter masks, a mask to indicate the size
22422 uint64_t mark_cnt_cos5;
22424 * Number of packets marked in CoS queue 6.
22425 * Or, if the driver requested counter masks, a mask to indicate the size
22428 uint64_t mark_cnt_cos6;
22430 * Number of packets marked in CoS queue 7.
22431 * Or, if the driver requested counter masks, a mask to indicate the size
22434 uint64_t mark_cnt_cos7;
22437 /***********************
22438 * hwrm_port_clr_stats *
22439 ***********************/
22442 /* hwrm_port_clr_stats_input (size:192b/24B) */
22443 struct hwrm_port_clr_stats_input {
22444 /* The HWRM command request type. */
22447 * The completion ring to send the completion event on. This should
22448 * be the NQ ID returned from the `nq_alloc` HWRM command.
22450 uint16_t cmpl_ring;
22452 * The sequence ID is used by the driver for tracking multiple
22453 * commands. This ID is treated as opaque data by the firmware and
22454 * the value is returned in the `hwrm_resp_hdr` upon completion.
22458 * The target ID of the command:
22459 * * 0x0-0xFFF8 - The function ID
22460 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
22461 * * 0xFFFD - Reserved for user-space HWRM interface
22464 uint16_t target_id;
22466 * A physical address pointer pointing to a host buffer that the
22467 * command's response data will be written. This can be either a host
22468 * physical address (HPA) or a guest physical address (GPA) and must
22469 * point to a physically contiguous block of memory.
22471 uint64_t resp_addr;
22472 /* Port ID of port that is being queried. */
22476 * If set to 1, then this field indicates clear the following RoCE
22477 * specific counters.
22478 * RoCE associated TX/RX cos counters
22479 * CNP associated TX/RX cos counters
22480 * RoCE/CNP specific TX/RX flow counters
22481 * Firmware will determine the RoCE/CNP cos queue based on qos profile.
22482 * This flag is honored only when RoCE is enabled on that port.
22484 #define HWRM_PORT_CLR_STATS_INPUT_FLAGS_ROCE_COUNTERS UINT32_C(0x1)
22485 uint8_t unused_0[5];
22488 /* hwrm_port_clr_stats_output (size:128b/16B) */
22489 struct hwrm_port_clr_stats_output {
22490 /* The specific error status for the command. */
22491 uint16_t error_code;
22492 /* The HWRM command request type. */
22494 /* The sequence ID from the original command. */
22496 /* The length of the response data in number of bytes. */
22498 uint8_t unused_0[7];
22500 * This field is used in Output records to indicate that the output
22501 * is completely written to RAM. This field should be read as '1'
22502 * to indicate that the output has been completely written.
22503 * When writing a command completion or response to an internal processor,
22504 * the order of writes has to be such that this field is written last.
22509 /***********************
22510 * hwrm_port_phy_qcaps *
22511 ***********************/
22514 /* hwrm_port_phy_qcaps_input (size:192b/24B) */
22515 struct hwrm_port_phy_qcaps_input {
22516 /* The HWRM command request type. */
22519 * The completion ring to send the completion event on. This should
22520 * be the NQ ID returned from the `nq_alloc` HWRM command.
22522 uint16_t cmpl_ring;
22524 * The sequence ID is used by the driver for tracking multiple
22525 * commands. This ID is treated as opaque data by the firmware and
22526 * the value is returned in the `hwrm_resp_hdr` upon completion.
22530 * The target ID of the command:
22531 * * 0x0-0xFFF8 - The function ID
22532 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
22533 * * 0xFFFD - Reserved for user-space HWRM interface
22536 uint16_t target_id;
22538 * A physical address pointer pointing to a host buffer that the
22539 * command's response data will be written. This can be either a host
22540 * physical address (HPA) or a guest physical address (GPA) and must
22541 * point to a physically contiguous block of memory.
22543 uint64_t resp_addr;
22544 /* Port ID of port that is being queried. */
22546 uint8_t unused_0[6];
22549 /* hwrm_port_phy_qcaps_output (size:256b/32B) */
22550 struct hwrm_port_phy_qcaps_output {
22551 /* The specific error status for the command. */
22552 uint16_t error_code;
22553 /* The HWRM command request type. */
22555 /* The sequence ID from the original command. */
22557 /* The length of the response data in number of bytes. */
22559 /* PHY capability flags */
22562 * If set to 1, then this field indicates that the
22563 * link is capable of supporting EEE.
22565 #define HWRM_PORT_PHY_QCAPS_OUTPUT_FLAGS_EEE_SUPPORTED \
22568 * If set to 1, then this field indicates that the
22569 * PHY is capable of supporting external loopback.
22571 #define HWRM_PORT_PHY_QCAPS_OUTPUT_FLAGS_EXTERNAL_LPBK_SUPPORTED \
22574 * If set to 1, then this field indicates that the
22575 * PHY is capable of supporting loopback in autoneg mode.
22577 #define HWRM_PORT_PHY_QCAPS_OUTPUT_FLAGS_AUTONEG_LPBK_SUPPORTED \
22580 * Indicates if the configuration of shared PHY settings is supported.
22581 * In cases where a physical port is shared by multiple functions
22582 * (e.g. NPAR, multihost, etc), the configuration of PHY
22583 * settings may not be allowed. Callers to HWRM_PORT_PHY_CFG will
22584 * get an HWRM_ERR_CODE_RESOURCE_ACCESS_DENIED error in this case.
22586 #define HWRM_PORT_PHY_QCAPS_OUTPUT_FLAGS_SHARED_PHY_CFG_SUPPORTED \
22589 * If set to 1, it indicates that the port counters and extended
22590 * port counters will not reset when the firmware shuts down or
22591 * resets the PHY. These counters will only be reset during power
22592 * cycle or by calling HWRM_PORT_CLR_STATS.
22593 * If set to 0, the state of the counters is unspecified when
22594 * firmware shuts down or resets the PHY.
22596 #define HWRM_PORT_PHY_QCAPS_OUTPUT_FLAGS_CUMULATIVE_COUNTERS_ON_RESET \
22599 * If set to 1, then this field indicates that the
22600 * local loopback is not supported on this controller.
22602 #define HWRM_PORT_PHY_QCAPS_OUTPUT_FLAGS_LOCAL_LPBK_NOT_SUPPORTED \
22605 * If set to 1, then this field indicates that the
22606 * PHY/Link down policy during PF shutdown is totally
22607 * controlled by the firmware. It can shutdown the link
22608 * even when there are active VFs associated with the PF.
22609 * Host PF driver can send HWRM_PHY_CFG command to bring
22610 * down the PHY even when the port is shared between VFs
22613 #define HWRM_PORT_PHY_QCAPS_OUTPUT_FLAGS_FW_MANAGED_LINK_DOWN \
22616 * If set to 1, this field indicates that the FCS may
22617 * be disabled for a given packet via the transmit
22618 * buffer descriptor.
22620 #define HWRM_PORT_PHY_QCAPS_OUTPUT_FLAGS_NO_FCS \
22622 /* Number of front panel ports for this device. */
22624 /* Not supported or unknown */
22625 #define HWRM_PORT_PHY_QCAPS_OUTPUT_PORT_CNT_UNKNOWN UINT32_C(0x0)
22626 /* single port device */
22627 #define HWRM_PORT_PHY_QCAPS_OUTPUT_PORT_CNT_1 UINT32_C(0x1)
22628 /* 2-port device */
22629 #define HWRM_PORT_PHY_QCAPS_OUTPUT_PORT_CNT_2 UINT32_C(0x2)
22630 /* 3-port device */
22631 #define HWRM_PORT_PHY_QCAPS_OUTPUT_PORT_CNT_3 UINT32_C(0x3)
22632 /* 4-port device */
22633 #define HWRM_PORT_PHY_QCAPS_OUTPUT_PORT_CNT_4 UINT32_C(0x4)
22634 #define HWRM_PORT_PHY_QCAPS_OUTPUT_PORT_CNT_LAST \
22635 HWRM_PORT_PHY_QCAPS_OUTPUT_PORT_CNT_4
22637 * This is a bit mask to indicate what speeds are supported
22638 * as forced speeds on this link.
22639 * For each speed that can be forced on this link, the
22640 * corresponding mask bit shall be set to '1'.
22642 uint16_t supported_speeds_force_mode;
22643 /* 100Mb link speed (Half-duplex) */
22644 #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_FORCE_MODE_100MBHD \
22646 /* 100Mb link speed (Full-duplex) */
22647 #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_FORCE_MODE_100MB \
22649 /* 1Gb link speed (Half-duplex) */
22650 #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_FORCE_MODE_1GBHD \
22652 /* 1Gb link speed (Full-duplex) */
22653 #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_FORCE_MODE_1GB \
22655 /* 2Gb link speed */
22656 #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_FORCE_MODE_2GB \
22658 /* 25Gb link speed */
22659 #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_FORCE_MODE_2_5GB \
22661 /* 10Gb link speed */
22662 #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_FORCE_MODE_10GB \
22664 /* 20Gb link speed */
22665 #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_FORCE_MODE_20GB \
22667 /* 25Gb link speed */
22668 #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_FORCE_MODE_25GB \
22670 /* 40Gb link speed */
22671 #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_FORCE_MODE_40GB \
22673 /* 50Gb link speed */
22674 #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_FORCE_MODE_50GB \
22676 /* 100Gb link speed */
22677 #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_FORCE_MODE_100GB \
22679 /* 10Mb link speed (Half-duplex) */
22680 #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_FORCE_MODE_10MBHD \
22682 /* 10Mb link speed (Full-duplex) */
22683 #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_FORCE_MODE_10MB \
22686 * This is a bit mask to indicate what speeds are supported
22687 * for autonegotiation on this link.
22688 * For each speed that can be autonegotiated on this link, the
22689 * corresponding mask bit shall be set to '1'.
22691 uint16_t supported_speeds_auto_mode;
22692 /* 100Mb link speed (Half-duplex) */
22693 #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_AUTO_MODE_100MBHD \
22695 /* 100Mb link speed (Full-duplex) */
22696 #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_AUTO_MODE_100MB \
22698 /* 1Gb link speed (Half-duplex) */
22699 #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_AUTO_MODE_1GBHD \
22701 /* 1Gb link speed (Full-duplex) */
22702 #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_AUTO_MODE_1GB \
22704 /* 2Gb link speed */
22705 #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_AUTO_MODE_2GB \
22707 /* 25Gb link speed */
22708 #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_AUTO_MODE_2_5GB \
22710 /* 10Gb link speed */
22711 #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_AUTO_MODE_10GB \
22713 /* 20Gb link speed */
22714 #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_AUTO_MODE_20GB \
22716 /* 25Gb link speed */
22717 #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_AUTO_MODE_25GB \
22719 /* 40Gb link speed */
22720 #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_AUTO_MODE_40GB \
22722 /* 50Gb link speed */
22723 #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_AUTO_MODE_50GB \
22725 /* 100Gb link speed */
22726 #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_AUTO_MODE_100GB \
22728 /* 10Mb link speed (Half-duplex) */
22729 #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_AUTO_MODE_10MBHD \
22731 /* 10Mb link speed (Full-duplex) */
22732 #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_AUTO_MODE_10MB \
22735 * This is a bit mask to indicate what speeds are supported
22736 * for EEE on this link.
22737 * For each speed that can be autonegotiated when EEE is enabled
22738 * on this link, the corresponding mask bit shall be set to '1'.
22739 * This field is only valid when the eee_suppotred is set to '1'.
22741 uint16_t supported_speeds_eee_mode;
22743 #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_EEE_MODE_RSVD1 \
22745 /* 100Mb link speed (Full-duplex) */
22746 #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_EEE_MODE_100MB \
22749 #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_EEE_MODE_RSVD2 \
22751 /* 1Gb link speed (Full-duplex) */
22752 #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_EEE_MODE_1GB \
22755 #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_EEE_MODE_RSVD3 \
22758 #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_EEE_MODE_RSVD4 \
22760 /* 10Gb link speed */
22761 #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_EEE_MODE_10GB \
22763 uint32_t tx_lpi_timer_low;
22765 * The lowest value of TX LPI timer that can be set on this link
22766 * when EEE is enabled. This value is in microseconds.
22767 * This field is valid only when_eee_supported is set to '1'.
22769 #define HWRM_PORT_PHY_QCAPS_OUTPUT_TX_LPI_TIMER_LOW_MASK \
22771 #define HWRM_PORT_PHY_QCAPS_OUTPUT_TX_LPI_TIMER_LOW_SFT 0
22773 * Reserved field. The HWRM shall set this field to 0.
22774 * An HWRM client shall ignore this field.
22776 #define HWRM_PORT_PHY_QCAPS_OUTPUT_RSVD2_MASK \
22777 UINT32_C(0xff000000)
22778 #define HWRM_PORT_PHY_QCAPS_OUTPUT_RSVD2_SFT 24
22779 uint32_t valid_tx_lpi_timer_high;
22781 * The highest value of TX LPI timer that can be set on this link
22782 * when EEE is enabled. This value is in microseconds.
22783 * This field is valid only when_eee_supported is set to '1'.
22785 #define HWRM_PORT_PHY_QCAPS_OUTPUT_TX_LPI_TIMER_HIGH_MASK \
22787 #define HWRM_PORT_PHY_QCAPS_OUTPUT_TX_LPI_TIMER_HIGH_SFT 0
22789 * Reserved field. The HWRM shall set this field to 0.
22790 * An HWRM client shall ignore this field.
22792 #define HWRM_PORT_PHY_QCAPS_OUTPUT_RSVD_MASK \
22793 UINT32_C(0xff000000)
22794 #define HWRM_PORT_PHY_QCAPS_OUTPUT_RSVD_SFT 24
22796 * This field is used to advertise which PAM4 speeds are supported
22799 uint16_t supported_pam4_speeds_auto_mode;
22800 #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_PAM4_SPEEDS_AUTO_MODE_50G \
22802 #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_PAM4_SPEEDS_AUTO_MODE_100G \
22804 #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_PAM4_SPEEDS_AUTO_MODE_200G \
22807 * This field is used to advertise which PAM4 speeds are supported
22810 uint16_t supported_pam4_speeds_force_mode;
22811 #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_PAM4_SPEEDS_FORCE_MODE_50G \
22813 #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_PAM4_SPEEDS_FORCE_MODE_100G \
22815 #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_PAM4_SPEEDS_FORCE_MODE_200G \
22817 uint8_t unused_0[3];
22819 * This field is used in Output records to indicate that the output
22820 * is completely written to RAM. This field should be read as '1'
22821 * to indicate that the output has been completely written.
22822 * When writing a command completion or response to an internal processor,
22823 * the order of writes has to be such that this field is written last.
22828 /****************************
22829 * hwrm_port_phy_mdio_write *
22830 ****************************/
22833 /* hwrm_port_phy_mdio_write_input (size:320b/40B) */
22834 struct hwrm_port_phy_mdio_write_input {
22835 /* The HWRM command request type. */
22838 * The completion ring to send the completion event on. This should
22839 * be the NQ ID returned from the `nq_alloc` HWRM command.
22841 uint16_t cmpl_ring;
22843 * The sequence ID is used by the driver for tracking multiple
22844 * commands. This ID is treated as opaque data by the firmware and
22845 * the value is returned in the `hwrm_resp_hdr` upon completion.
22849 * The target ID of the command:
22850 * * 0x0-0xFFF8 - The function ID
22851 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
22852 * * 0xFFFD - Reserved for user-space HWRM interface
22855 uint16_t target_id;
22857 * A physical address pointer pointing to a host buffer that the
22858 * command's response data will be written. This can be either a host
22859 * physical address (HPA) or a guest physical address (GPA) and must
22860 * point to a physically contiguous block of memory.
22862 uint64_t resp_addr;
22863 /* Reserved for future use. */
22864 uint32_t unused_0[2];
22865 /* Port ID of port. */
22867 /* If phy_address is 0xFF, port_id will be used to derive phy_addr. */
22869 /* 8-bit device address. */
22871 /* 16-bit register address. */
22873 /* 16-bit register data. */
22876 * When this bit is set to 1 a Clause 45 mdio access is done.
22877 * when this bit is set to 0 a Clause 22 mdio access is done.
22881 uint8_t unused_1[7];
22884 /* hwrm_port_phy_mdio_write_output (size:128b/16B) */
22885 struct hwrm_port_phy_mdio_write_output {
22886 /* The specific error status for the command. */
22887 uint16_t error_code;
22888 /* The HWRM command request type. */
22890 /* The sequence ID from the original command. */
22892 /* The length of the response data in number of bytes. */
22894 uint8_t unused_0[7];
22896 * This field is used in Output records to indicate that the output
22897 * is completely written to RAM. This field should be read as '1'
22898 * to indicate that the output has been completely written.
22899 * When writing a command completion or response to an internal processor,
22900 * the order of writes has to be such that this field is written last.
22905 /***************************
22906 * hwrm_port_phy_mdio_read *
22907 ***************************/
22910 /* hwrm_port_phy_mdio_read_input (size:256b/32B) */
22911 struct hwrm_port_phy_mdio_read_input {
22912 /* The HWRM command request type. */
22915 * The completion ring to send the completion event on. This should
22916 * be the NQ ID returned from the `nq_alloc` HWRM command.
22918 uint16_t cmpl_ring;
22920 * The sequence ID is used by the driver for tracking multiple
22921 * commands. This ID is treated as opaque data by the firmware and
22922 * the value is returned in the `hwrm_resp_hdr` upon completion.
22926 * The target ID of the command:
22927 * * 0x0-0xFFF8 - The function ID
22928 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
22929 * * 0xFFFD - Reserved for user-space HWRM interface
22932 uint16_t target_id;
22934 * A physical address pointer pointing to a host buffer that the
22935 * command's response data will be written. This can be either a host
22936 * physical address (HPA) or a guest physical address (GPA) and must
22937 * point to a physically contiguous block of memory.
22939 uint64_t resp_addr;
22940 /* Reserved for future use. */
22941 uint32_t unused_0[2];
22942 /* Port ID of port. */
22944 /* If phy_address is 0xFF, port_id will be used to derive phy_addr. */
22946 /* 8-bit device address. */
22948 /* 16-bit register address. */
22951 * When this bit is set to 1 a Clause 45 mdio access is done.
22952 * when this bit is set to 0 a Clause 22 mdio access is done.
22959 /* hwrm_port_phy_mdio_read_output (size:128b/16B) */
22960 struct hwrm_port_phy_mdio_read_output {
22961 /* The specific error status for the command. */
22962 uint16_t error_code;
22963 /* The HWRM command request type. */
22965 /* The sequence ID from the original command. */
22967 /* The length of the response data in number of bytes. */
22969 /* 16-bit register data. */
22971 uint8_t unused_0[5];
22973 * This field is used in Output records to indicate that the output
22974 * is completely written to RAM. This field should be read as '1'
22975 * to indicate that the output has been completely written.
22976 * When writing a command completion or response to an internal processor,
22977 * the order of writes has to be such that this field is written last.
22982 /*********************
22983 * hwrm_port_led_cfg *
22984 *********************/
22987 /* hwrm_port_led_cfg_input (size:512b/64B) */
22988 struct hwrm_port_led_cfg_input {
22989 /* The HWRM command request type. */
22992 * The completion ring to send the completion event on. This should
22993 * be the NQ ID returned from the `nq_alloc` HWRM command.
22995 uint16_t cmpl_ring;
22997 * The sequence ID is used by the driver for tracking multiple
22998 * commands. This ID is treated as opaque data by the firmware and
22999 * the value is returned in the `hwrm_resp_hdr` upon completion.
23003 * The target ID of the command:
23004 * * 0x0-0xFFF8 - The function ID
23005 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
23006 * * 0xFFFD - Reserved for user-space HWRM interface
23009 uint16_t target_id;
23011 * A physical address pointer pointing to a host buffer that the
23012 * command's response data will be written. This can be either a host
23013 * physical address (HPA) or a guest physical address (GPA) and must
23014 * point to a physically contiguous block of memory.
23016 uint64_t resp_addr;
23019 * This bit must be '1' for the led0_id field to be
23022 #define HWRM_PORT_LED_CFG_INPUT_ENABLES_LED0_ID \
23025 * This bit must be '1' for the led0_state field to be
23028 #define HWRM_PORT_LED_CFG_INPUT_ENABLES_LED0_STATE \
23031 * This bit must be '1' for the led0_color field to be
23034 #define HWRM_PORT_LED_CFG_INPUT_ENABLES_LED0_COLOR \
23037 * This bit must be '1' for the led0_blink_on field to be
23040 #define HWRM_PORT_LED_CFG_INPUT_ENABLES_LED0_BLINK_ON \
23043 * This bit must be '1' for the led0_blink_off field to be
23046 #define HWRM_PORT_LED_CFG_INPUT_ENABLES_LED0_BLINK_OFF \
23049 * This bit must be '1' for the led0_group_id field to be
23052 #define HWRM_PORT_LED_CFG_INPUT_ENABLES_LED0_GROUP_ID \
23055 * This bit must be '1' for the led1_id field to be
23058 #define HWRM_PORT_LED_CFG_INPUT_ENABLES_LED1_ID \
23061 * This bit must be '1' for the led1_state field to be
23064 #define HWRM_PORT_LED_CFG_INPUT_ENABLES_LED1_STATE \
23067 * This bit must be '1' for the led1_color field to be
23070 #define HWRM_PORT_LED_CFG_INPUT_ENABLES_LED1_COLOR \
23073 * This bit must be '1' for the led1_blink_on field to be
23076 #define HWRM_PORT_LED_CFG_INPUT_ENABLES_LED1_BLINK_ON \
23079 * This bit must be '1' for the led1_blink_off field to be
23082 #define HWRM_PORT_LED_CFG_INPUT_ENABLES_LED1_BLINK_OFF \
23085 * This bit must be '1' for the led1_group_id field to be
23088 #define HWRM_PORT_LED_CFG_INPUT_ENABLES_LED1_GROUP_ID \
23091 * This bit must be '1' for the led2_id field to be
23094 #define HWRM_PORT_LED_CFG_INPUT_ENABLES_LED2_ID \
23097 * This bit must be '1' for the led2_state field to be
23100 #define HWRM_PORT_LED_CFG_INPUT_ENABLES_LED2_STATE \
23103 * This bit must be '1' for the led2_color field to be
23106 #define HWRM_PORT_LED_CFG_INPUT_ENABLES_LED2_COLOR \
23109 * This bit must be '1' for the led2_blink_on field to be
23112 #define HWRM_PORT_LED_CFG_INPUT_ENABLES_LED2_BLINK_ON \
23115 * This bit must be '1' for the led2_blink_off field to be
23118 #define HWRM_PORT_LED_CFG_INPUT_ENABLES_LED2_BLINK_OFF \
23121 * This bit must be '1' for the led2_group_id field to be
23124 #define HWRM_PORT_LED_CFG_INPUT_ENABLES_LED2_GROUP_ID \
23127 * This bit must be '1' for the led3_id field to be
23130 #define HWRM_PORT_LED_CFG_INPUT_ENABLES_LED3_ID \
23133 * This bit must be '1' for the led3_state field to be
23136 #define HWRM_PORT_LED_CFG_INPUT_ENABLES_LED3_STATE \
23139 * This bit must be '1' for the led3_color field to be
23142 #define HWRM_PORT_LED_CFG_INPUT_ENABLES_LED3_COLOR \
23145 * This bit must be '1' for the led3_blink_on field to be
23148 #define HWRM_PORT_LED_CFG_INPUT_ENABLES_LED3_BLINK_ON \
23151 * This bit must be '1' for the led3_blink_off field to be
23154 #define HWRM_PORT_LED_CFG_INPUT_ENABLES_LED3_BLINK_OFF \
23157 * This bit must be '1' for the led3_group_id field to be
23160 #define HWRM_PORT_LED_CFG_INPUT_ENABLES_LED3_GROUP_ID \
23162 /* Port ID of port whose LEDs are configured. */
23165 * The number of LEDs that are being configured.
23166 * Up to 4 LEDs can be configured with this command.
23169 /* Reserved field. */
23171 /* An identifier for the LED #0. */
23173 /* The requested state of the LED #0. */
23174 uint8_t led0_state;
23175 /* Default state of the LED */
23176 #define HWRM_PORT_LED_CFG_INPUT_LED0_STATE_DEFAULT UINT32_C(0x0)
23178 #define HWRM_PORT_LED_CFG_INPUT_LED0_STATE_OFF UINT32_C(0x1)
23180 #define HWRM_PORT_LED_CFG_INPUT_LED0_STATE_ON UINT32_C(0x2)
23182 #define HWRM_PORT_LED_CFG_INPUT_LED0_STATE_BLINK UINT32_C(0x3)
23183 /* Blink Alternately */
23184 #define HWRM_PORT_LED_CFG_INPUT_LED0_STATE_BLINKALT UINT32_C(0x4)
23185 #define HWRM_PORT_LED_CFG_INPUT_LED0_STATE_LAST \
23186 HWRM_PORT_LED_CFG_INPUT_LED0_STATE_BLINKALT
23187 /* The requested color of LED #0. */
23188 uint8_t led0_color;
23190 #define HWRM_PORT_LED_CFG_INPUT_LED0_COLOR_DEFAULT UINT32_C(0x0)
23192 #define HWRM_PORT_LED_CFG_INPUT_LED0_COLOR_AMBER UINT32_C(0x1)
23194 #define HWRM_PORT_LED_CFG_INPUT_LED0_COLOR_GREEN UINT32_C(0x2)
23195 /* Green or Amber */
23196 #define HWRM_PORT_LED_CFG_INPUT_LED0_COLOR_GREENAMBER UINT32_C(0x3)
23197 #define HWRM_PORT_LED_CFG_INPUT_LED0_COLOR_LAST \
23198 HWRM_PORT_LED_CFG_INPUT_LED0_COLOR_GREENAMBER
23201 * If the LED #0 state is "blink" or "blinkalt", then
23202 * this field represents the requested time in milliseconds
23203 * to keep LED on between cycles.
23205 uint16_t led0_blink_on;
23207 * If the LED #0 state is "blink" or "blinkalt", then
23208 * this field represents the requested time in milliseconds
23209 * to keep LED off between cycles.
23211 uint16_t led0_blink_off;
23213 * An identifier for the group of LEDs that LED #0 belongs
23215 * If set to 0, then the LED #0 shall not be grouped and
23216 * shall be treated as an individual resource.
23217 * For all other non-zero values of this field, LED #0 shall
23218 * be grouped together with the LEDs with the same group ID
23221 uint8_t led0_group_id;
23222 /* Reserved field. */
23224 /* An identifier for the LED #1. */
23226 /* The requested state of the LED #1. */
23227 uint8_t led1_state;
23228 /* Default state of the LED */
23229 #define HWRM_PORT_LED_CFG_INPUT_LED1_STATE_DEFAULT UINT32_C(0x0)
23231 #define HWRM_PORT_LED_CFG_INPUT_LED1_STATE_OFF UINT32_C(0x1)
23233 #define HWRM_PORT_LED_CFG_INPUT_LED1_STATE_ON UINT32_C(0x2)
23235 #define HWRM_PORT_LED_CFG_INPUT_LED1_STATE_BLINK UINT32_C(0x3)
23236 /* Blink Alternately */
23237 #define HWRM_PORT_LED_CFG_INPUT_LED1_STATE_BLINKALT UINT32_C(0x4)
23238 #define HWRM_PORT_LED_CFG_INPUT_LED1_STATE_LAST \
23239 HWRM_PORT_LED_CFG_INPUT_LED1_STATE_BLINKALT
23240 /* The requested color of LED #1. */
23241 uint8_t led1_color;
23243 #define HWRM_PORT_LED_CFG_INPUT_LED1_COLOR_DEFAULT UINT32_C(0x0)
23245 #define HWRM_PORT_LED_CFG_INPUT_LED1_COLOR_AMBER UINT32_C(0x1)
23247 #define HWRM_PORT_LED_CFG_INPUT_LED1_COLOR_GREEN UINT32_C(0x2)
23248 /* Green or Amber */
23249 #define HWRM_PORT_LED_CFG_INPUT_LED1_COLOR_GREENAMBER UINT32_C(0x3)
23250 #define HWRM_PORT_LED_CFG_INPUT_LED1_COLOR_LAST \
23251 HWRM_PORT_LED_CFG_INPUT_LED1_COLOR_GREENAMBER
23254 * If the LED #1 state is "blink" or "blinkalt", then
23255 * this field represents the requested time in milliseconds
23256 * to keep LED on between cycles.
23258 uint16_t led1_blink_on;
23260 * If the LED #1 state is "blink" or "blinkalt", then
23261 * this field represents the requested time in milliseconds
23262 * to keep LED off between cycles.
23264 uint16_t led1_blink_off;
23266 * An identifier for the group of LEDs that LED #1 belongs
23268 * If set to 0, then the LED #1 shall not be grouped and
23269 * shall be treated as an individual resource.
23270 * For all other non-zero values of this field, LED #1 shall
23271 * be grouped together with the LEDs with the same group ID
23274 uint8_t led1_group_id;
23275 /* Reserved field. */
23277 /* An identifier for the LED #2. */
23279 /* The requested state of the LED #2. */
23280 uint8_t led2_state;
23281 /* Default state of the LED */
23282 #define HWRM_PORT_LED_CFG_INPUT_LED2_STATE_DEFAULT UINT32_C(0x0)
23284 #define HWRM_PORT_LED_CFG_INPUT_LED2_STATE_OFF UINT32_C(0x1)
23286 #define HWRM_PORT_LED_CFG_INPUT_LED2_STATE_ON UINT32_C(0x2)
23288 #define HWRM_PORT_LED_CFG_INPUT_LED2_STATE_BLINK UINT32_C(0x3)
23289 /* Blink Alternately */
23290 #define HWRM_PORT_LED_CFG_INPUT_LED2_STATE_BLINKALT UINT32_C(0x4)
23291 #define HWRM_PORT_LED_CFG_INPUT_LED2_STATE_LAST \
23292 HWRM_PORT_LED_CFG_INPUT_LED2_STATE_BLINKALT
23293 /* The requested color of LED #2. */
23294 uint8_t led2_color;
23296 #define HWRM_PORT_LED_CFG_INPUT_LED2_COLOR_DEFAULT UINT32_C(0x0)
23298 #define HWRM_PORT_LED_CFG_INPUT_LED2_COLOR_AMBER UINT32_C(0x1)
23300 #define HWRM_PORT_LED_CFG_INPUT_LED2_COLOR_GREEN UINT32_C(0x2)
23301 /* Green or Amber */
23302 #define HWRM_PORT_LED_CFG_INPUT_LED2_COLOR_GREENAMBER UINT32_C(0x3)
23303 #define HWRM_PORT_LED_CFG_INPUT_LED2_COLOR_LAST \
23304 HWRM_PORT_LED_CFG_INPUT_LED2_COLOR_GREENAMBER
23307 * If the LED #2 state is "blink" or "blinkalt", then
23308 * this field represents the requested time in milliseconds
23309 * to keep LED on between cycles.
23311 uint16_t led2_blink_on;
23313 * If the LED #2 state is "blink" or "blinkalt", then
23314 * this field represents the requested time in milliseconds
23315 * to keep LED off between cycles.
23317 uint16_t led2_blink_off;
23319 * An identifier for the group of LEDs that LED #2 belongs
23321 * If set to 0, then the LED #2 shall not be grouped and
23322 * shall be treated as an individual resource.
23323 * For all other non-zero values of this field, LED #2 shall
23324 * be grouped together with the LEDs with the same group ID
23327 uint8_t led2_group_id;
23328 /* Reserved field. */
23330 /* An identifier for the LED #3. */
23332 /* The requested state of the LED #3. */
23333 uint8_t led3_state;
23334 /* Default state of the LED */
23335 #define HWRM_PORT_LED_CFG_INPUT_LED3_STATE_DEFAULT UINT32_C(0x0)
23337 #define HWRM_PORT_LED_CFG_INPUT_LED3_STATE_OFF UINT32_C(0x1)
23339 #define HWRM_PORT_LED_CFG_INPUT_LED3_STATE_ON UINT32_C(0x2)
23341 #define HWRM_PORT_LED_CFG_INPUT_LED3_STATE_BLINK UINT32_C(0x3)
23342 /* Blink Alternately */
23343 #define HWRM_PORT_LED_CFG_INPUT_LED3_STATE_BLINKALT UINT32_C(0x4)
23344 #define HWRM_PORT_LED_CFG_INPUT_LED3_STATE_LAST \
23345 HWRM_PORT_LED_CFG_INPUT_LED3_STATE_BLINKALT
23346 /* The requested color of LED #3. */
23347 uint8_t led3_color;
23349 #define HWRM_PORT_LED_CFG_INPUT_LED3_COLOR_DEFAULT UINT32_C(0x0)
23351 #define HWRM_PORT_LED_CFG_INPUT_LED3_COLOR_AMBER UINT32_C(0x1)
23353 #define HWRM_PORT_LED_CFG_INPUT_LED3_COLOR_GREEN UINT32_C(0x2)
23354 /* Green or Amber */
23355 #define HWRM_PORT_LED_CFG_INPUT_LED3_COLOR_GREENAMBER UINT32_C(0x3)
23356 #define HWRM_PORT_LED_CFG_INPUT_LED3_COLOR_LAST \
23357 HWRM_PORT_LED_CFG_INPUT_LED3_COLOR_GREENAMBER
23360 * If the LED #3 state is "blink" or "blinkalt", then
23361 * this field represents the requested time in milliseconds
23362 * to keep LED on between cycles.
23364 uint16_t led3_blink_on;
23366 * If the LED #3 state is "blink" or "blinkalt", then
23367 * this field represents the requested time in milliseconds
23368 * to keep LED off between cycles.
23370 uint16_t led3_blink_off;
23372 * An identifier for the group of LEDs that LED #3 belongs
23374 * If set to 0, then the LED #3 shall not be grouped and
23375 * shall be treated as an individual resource.
23376 * For all other non-zero values of this field, LED #3 shall
23377 * be grouped together with the LEDs with the same group ID
23380 uint8_t led3_group_id;
23381 /* Reserved field. */
23385 /* hwrm_port_led_cfg_output (size:128b/16B) */
23386 struct hwrm_port_led_cfg_output {
23387 /* The specific error status for the command. */
23388 uint16_t error_code;
23389 /* The HWRM command request type. */
23391 /* The sequence ID from the original command. */
23393 /* The length of the response data in number of bytes. */
23395 uint8_t unused_0[7];
23397 * This field is used in Output records to indicate that the output
23398 * is completely written to RAM. This field should be read as '1'
23399 * to indicate that the output has been completely written.
23400 * When writing a command completion or response to an internal processor,
23401 * the order of writes has to be such that this field is written last.
23406 /**********************
23407 * hwrm_port_led_qcfg *
23408 **********************/
23411 /* hwrm_port_led_qcfg_input (size:192b/24B) */
23412 struct hwrm_port_led_qcfg_input {
23413 /* The HWRM command request type. */
23416 * The completion ring to send the completion event on. This should
23417 * be the NQ ID returned from the `nq_alloc` HWRM command.
23419 uint16_t cmpl_ring;
23421 * The sequence ID is used by the driver for tracking multiple
23422 * commands. This ID is treated as opaque data by the firmware and
23423 * the value is returned in the `hwrm_resp_hdr` upon completion.
23427 * The target ID of the command:
23428 * * 0x0-0xFFF8 - The function ID
23429 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
23430 * * 0xFFFD - Reserved for user-space HWRM interface
23433 uint16_t target_id;
23435 * A physical address pointer pointing to a host buffer that the
23436 * command's response data will be written. This can be either a host
23437 * physical address (HPA) or a guest physical address (GPA) and must
23438 * point to a physically contiguous block of memory.
23440 uint64_t resp_addr;
23441 /* Port ID of port whose LED configuration is being queried. */
23443 uint8_t unused_0[6];
23446 /* hwrm_port_led_qcfg_output (size:448b/56B) */
23447 struct hwrm_port_led_qcfg_output {
23448 /* The specific error status for the command. */
23449 uint16_t error_code;
23450 /* The HWRM command request type. */
23452 /* The sequence ID from the original command. */
23454 /* The length of the response data in number of bytes. */
23457 * The number of LEDs that are configured on this port.
23458 * Up to 4 LEDs can be returned in the response.
23461 /* An identifier for the LED #0. */
23463 /* The type of LED #0. */
23466 #define HWRM_PORT_LED_QCFG_OUTPUT_LED0_TYPE_SPEED UINT32_C(0x0)
23468 #define HWRM_PORT_LED_QCFG_OUTPUT_LED0_TYPE_ACTIVITY UINT32_C(0x1)
23470 #define HWRM_PORT_LED_QCFG_OUTPUT_LED0_TYPE_INVALID UINT32_C(0xff)
23471 #define HWRM_PORT_LED_QCFG_OUTPUT_LED0_TYPE_LAST \
23472 HWRM_PORT_LED_QCFG_OUTPUT_LED0_TYPE_INVALID
23473 /* The current state of the LED #0. */
23474 uint8_t led0_state;
23475 /* Default state of the LED */
23476 #define HWRM_PORT_LED_QCFG_OUTPUT_LED0_STATE_DEFAULT UINT32_C(0x0)
23478 #define HWRM_PORT_LED_QCFG_OUTPUT_LED0_STATE_OFF UINT32_C(0x1)
23480 #define HWRM_PORT_LED_QCFG_OUTPUT_LED0_STATE_ON UINT32_C(0x2)
23482 #define HWRM_PORT_LED_QCFG_OUTPUT_LED0_STATE_BLINK UINT32_C(0x3)
23483 /* Blink Alternately */
23484 #define HWRM_PORT_LED_QCFG_OUTPUT_LED0_STATE_BLINKALT UINT32_C(0x4)
23485 #define HWRM_PORT_LED_QCFG_OUTPUT_LED0_STATE_LAST \
23486 HWRM_PORT_LED_QCFG_OUTPUT_LED0_STATE_BLINKALT
23487 /* The color of LED #0. */
23488 uint8_t led0_color;
23490 #define HWRM_PORT_LED_QCFG_OUTPUT_LED0_COLOR_DEFAULT UINT32_C(0x0)
23492 #define HWRM_PORT_LED_QCFG_OUTPUT_LED0_COLOR_AMBER UINT32_C(0x1)
23494 #define HWRM_PORT_LED_QCFG_OUTPUT_LED0_COLOR_GREEN UINT32_C(0x2)
23495 /* Green or Amber */
23496 #define HWRM_PORT_LED_QCFG_OUTPUT_LED0_COLOR_GREENAMBER UINT32_C(0x3)
23497 #define HWRM_PORT_LED_QCFG_OUTPUT_LED0_COLOR_LAST \
23498 HWRM_PORT_LED_QCFG_OUTPUT_LED0_COLOR_GREENAMBER
23501 * If the LED #0 state is "blink" or "blinkalt", then
23502 * this field represents the requested time in milliseconds
23503 * to keep LED on between cycles.
23505 uint16_t led0_blink_on;
23507 * If the LED #0 state is "blink" or "blinkalt", then
23508 * this field represents the requested time in milliseconds
23509 * to keep LED off between cycles.
23511 uint16_t led0_blink_off;
23513 * An identifier for the group of LEDs that LED #0 belongs
23515 * If set to 0, then the LED #0 is not grouped.
23516 * For all other non-zero values of this field, LED #0 is
23517 * grouped together with the LEDs with the same group ID
23520 uint8_t led0_group_id;
23521 /* An identifier for the LED #1. */
23523 /* The type of LED #1. */
23526 #define HWRM_PORT_LED_QCFG_OUTPUT_LED1_TYPE_SPEED UINT32_C(0x0)
23528 #define HWRM_PORT_LED_QCFG_OUTPUT_LED1_TYPE_ACTIVITY UINT32_C(0x1)
23530 #define HWRM_PORT_LED_QCFG_OUTPUT_LED1_TYPE_INVALID UINT32_C(0xff)
23531 #define HWRM_PORT_LED_QCFG_OUTPUT_LED1_TYPE_LAST \
23532 HWRM_PORT_LED_QCFG_OUTPUT_LED1_TYPE_INVALID
23533 /* The current state of the LED #1. */
23534 uint8_t led1_state;
23535 /* Default state of the LED */
23536 #define HWRM_PORT_LED_QCFG_OUTPUT_LED1_STATE_DEFAULT UINT32_C(0x0)
23538 #define HWRM_PORT_LED_QCFG_OUTPUT_LED1_STATE_OFF UINT32_C(0x1)
23540 #define HWRM_PORT_LED_QCFG_OUTPUT_LED1_STATE_ON UINT32_C(0x2)
23542 #define HWRM_PORT_LED_QCFG_OUTPUT_LED1_STATE_BLINK UINT32_C(0x3)
23543 /* Blink Alternately */
23544 #define HWRM_PORT_LED_QCFG_OUTPUT_LED1_STATE_BLINKALT UINT32_C(0x4)
23545 #define HWRM_PORT_LED_QCFG_OUTPUT_LED1_STATE_LAST \
23546 HWRM_PORT_LED_QCFG_OUTPUT_LED1_STATE_BLINKALT
23547 /* The color of LED #1. */
23548 uint8_t led1_color;
23550 #define HWRM_PORT_LED_QCFG_OUTPUT_LED1_COLOR_DEFAULT UINT32_C(0x0)
23552 #define HWRM_PORT_LED_QCFG_OUTPUT_LED1_COLOR_AMBER UINT32_C(0x1)
23554 #define HWRM_PORT_LED_QCFG_OUTPUT_LED1_COLOR_GREEN UINT32_C(0x2)
23555 /* Green or Amber */
23556 #define HWRM_PORT_LED_QCFG_OUTPUT_LED1_COLOR_GREENAMBER UINT32_C(0x3)
23557 #define HWRM_PORT_LED_QCFG_OUTPUT_LED1_COLOR_LAST \
23558 HWRM_PORT_LED_QCFG_OUTPUT_LED1_COLOR_GREENAMBER
23561 * If the LED #1 state is "blink" or "blinkalt", then
23562 * this field represents the requested time in milliseconds
23563 * to keep LED on between cycles.
23565 uint16_t led1_blink_on;
23567 * If the LED #1 state is "blink" or "blinkalt", then
23568 * this field represents the requested time in milliseconds
23569 * to keep LED off between cycles.
23571 uint16_t led1_blink_off;
23573 * An identifier for the group of LEDs that LED #1 belongs
23575 * If set to 0, then the LED #1 is not grouped.
23576 * For all other non-zero values of this field, LED #1 is
23577 * grouped together with the LEDs with the same group ID
23580 uint8_t led1_group_id;
23581 /* An identifier for the LED #2. */
23583 /* The type of LED #2. */
23586 #define HWRM_PORT_LED_QCFG_OUTPUT_LED2_TYPE_SPEED UINT32_C(0x0)
23588 #define HWRM_PORT_LED_QCFG_OUTPUT_LED2_TYPE_ACTIVITY UINT32_C(0x1)
23590 #define HWRM_PORT_LED_QCFG_OUTPUT_LED2_TYPE_INVALID UINT32_C(0xff)
23591 #define HWRM_PORT_LED_QCFG_OUTPUT_LED2_TYPE_LAST \
23592 HWRM_PORT_LED_QCFG_OUTPUT_LED2_TYPE_INVALID
23593 /* The current state of the LED #2. */
23594 uint8_t led2_state;
23595 /* Default state of the LED */
23596 #define HWRM_PORT_LED_QCFG_OUTPUT_LED2_STATE_DEFAULT UINT32_C(0x0)
23598 #define HWRM_PORT_LED_QCFG_OUTPUT_LED2_STATE_OFF UINT32_C(0x1)
23600 #define HWRM_PORT_LED_QCFG_OUTPUT_LED2_STATE_ON UINT32_C(0x2)
23602 #define HWRM_PORT_LED_QCFG_OUTPUT_LED2_STATE_BLINK UINT32_C(0x3)
23603 /* Blink Alternately */
23604 #define HWRM_PORT_LED_QCFG_OUTPUT_LED2_STATE_BLINKALT UINT32_C(0x4)
23605 #define HWRM_PORT_LED_QCFG_OUTPUT_LED2_STATE_LAST \
23606 HWRM_PORT_LED_QCFG_OUTPUT_LED2_STATE_BLINKALT
23607 /* The color of LED #2. */
23608 uint8_t led2_color;
23610 #define HWRM_PORT_LED_QCFG_OUTPUT_LED2_COLOR_DEFAULT UINT32_C(0x0)
23612 #define HWRM_PORT_LED_QCFG_OUTPUT_LED2_COLOR_AMBER UINT32_C(0x1)
23614 #define HWRM_PORT_LED_QCFG_OUTPUT_LED2_COLOR_GREEN UINT32_C(0x2)
23615 /* Green or Amber */
23616 #define HWRM_PORT_LED_QCFG_OUTPUT_LED2_COLOR_GREENAMBER UINT32_C(0x3)
23617 #define HWRM_PORT_LED_QCFG_OUTPUT_LED2_COLOR_LAST \
23618 HWRM_PORT_LED_QCFG_OUTPUT_LED2_COLOR_GREENAMBER
23621 * If the LED #2 state is "blink" or "blinkalt", then
23622 * this field represents the requested time in milliseconds
23623 * to keep LED on between cycles.
23625 uint16_t led2_blink_on;
23627 * If the LED #2 state is "blink" or "blinkalt", then
23628 * this field represents the requested time in milliseconds
23629 * to keep LED off between cycles.
23631 uint16_t led2_blink_off;
23633 * An identifier for the group of LEDs that LED #2 belongs
23635 * If set to 0, then the LED #2 is not grouped.
23636 * For all other non-zero values of this field, LED #2 is
23637 * grouped together with the LEDs with the same group ID
23640 uint8_t led2_group_id;
23641 /* An identifier for the LED #3. */
23643 /* The type of LED #3. */
23646 #define HWRM_PORT_LED_QCFG_OUTPUT_LED3_TYPE_SPEED UINT32_C(0x0)
23648 #define HWRM_PORT_LED_QCFG_OUTPUT_LED3_TYPE_ACTIVITY UINT32_C(0x1)
23650 #define HWRM_PORT_LED_QCFG_OUTPUT_LED3_TYPE_INVALID UINT32_C(0xff)
23651 #define HWRM_PORT_LED_QCFG_OUTPUT_LED3_TYPE_LAST \
23652 HWRM_PORT_LED_QCFG_OUTPUT_LED3_TYPE_INVALID
23653 /* The current state of the LED #3. */
23654 uint8_t led3_state;
23655 /* Default state of the LED */
23656 #define HWRM_PORT_LED_QCFG_OUTPUT_LED3_STATE_DEFAULT UINT32_C(0x0)
23658 #define HWRM_PORT_LED_QCFG_OUTPUT_LED3_STATE_OFF UINT32_C(0x1)
23660 #define HWRM_PORT_LED_QCFG_OUTPUT_LED3_STATE_ON UINT32_C(0x2)
23662 #define HWRM_PORT_LED_QCFG_OUTPUT_LED3_STATE_BLINK UINT32_C(0x3)
23663 /* Blink Alternately */
23664 #define HWRM_PORT_LED_QCFG_OUTPUT_LED3_STATE_BLINKALT UINT32_C(0x4)
23665 #define HWRM_PORT_LED_QCFG_OUTPUT_LED3_STATE_LAST \
23666 HWRM_PORT_LED_QCFG_OUTPUT_LED3_STATE_BLINKALT
23667 /* The color of LED #3. */
23668 uint8_t led3_color;
23670 #define HWRM_PORT_LED_QCFG_OUTPUT_LED3_COLOR_DEFAULT UINT32_C(0x0)
23672 #define HWRM_PORT_LED_QCFG_OUTPUT_LED3_COLOR_AMBER UINT32_C(0x1)
23674 #define HWRM_PORT_LED_QCFG_OUTPUT_LED3_COLOR_GREEN UINT32_C(0x2)
23675 /* Green or Amber */
23676 #define HWRM_PORT_LED_QCFG_OUTPUT_LED3_COLOR_GREENAMBER UINT32_C(0x3)
23677 #define HWRM_PORT_LED_QCFG_OUTPUT_LED3_COLOR_LAST \
23678 HWRM_PORT_LED_QCFG_OUTPUT_LED3_COLOR_GREENAMBER
23681 * If the LED #3 state is "blink" or "blinkalt", then
23682 * this field represents the requested time in milliseconds
23683 * to keep LED on between cycles.
23685 uint16_t led3_blink_on;
23687 * If the LED #3 state is "blink" or "blinkalt", then
23688 * this field represents the requested time in milliseconds
23689 * to keep LED off between cycles.
23691 uint16_t led3_blink_off;
23693 * An identifier for the group of LEDs that LED #3 belongs
23695 * If set to 0, then the LED #3 is not grouped.
23696 * For all other non-zero values of this field, LED #3 is
23697 * grouped together with the LEDs with the same group ID
23700 uint8_t led3_group_id;
23701 uint8_t unused_4[6];
23703 * This field is used in Output records to indicate that the output
23704 * is completely written to RAM. This field should be read as '1'
23705 * to indicate that the output has been completely written.
23706 * When writing a command completion or response to an internal processor,
23707 * the order of writes has to be such that this field is written last.
23712 /***********************
23713 * hwrm_port_led_qcaps *
23714 ***********************/
23717 /* hwrm_port_led_qcaps_input (size:192b/24B) */
23718 struct hwrm_port_led_qcaps_input {
23719 /* The HWRM command request type. */
23722 * The completion ring to send the completion event on. This should
23723 * be the NQ ID returned from the `nq_alloc` HWRM command.
23725 uint16_t cmpl_ring;
23727 * The sequence ID is used by the driver for tracking multiple
23728 * commands. This ID is treated as opaque data by the firmware and
23729 * the value is returned in the `hwrm_resp_hdr` upon completion.
23733 * The target ID of the command:
23734 * * 0x0-0xFFF8 - The function ID
23735 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
23736 * * 0xFFFD - Reserved for user-space HWRM interface
23739 uint16_t target_id;
23741 * A physical address pointer pointing to a host buffer that the
23742 * command's response data will be written. This can be either a host
23743 * physical address (HPA) or a guest physical address (GPA) and must
23744 * point to a physically contiguous block of memory.
23746 uint64_t resp_addr;
23747 /* Port ID of port whose LED configuration is being queried. */
23749 uint8_t unused_0[6];
23752 /* hwrm_port_led_qcaps_output (size:384b/48B) */
23753 struct hwrm_port_led_qcaps_output {
23754 /* The specific error status for the command. */
23755 uint16_t error_code;
23756 /* The HWRM command request type. */
23758 /* The sequence ID from the original command. */
23760 /* The length of the response data in number of bytes. */
23763 * The number of LEDs that are configured on this port.
23764 * Up to 4 LEDs can be returned in the response.
23767 /* Reserved for future use. */
23769 /* An identifier for the LED #0. */
23771 /* The type of LED #0. */
23774 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED0_TYPE_SPEED UINT32_C(0x0)
23776 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED0_TYPE_ACTIVITY UINT32_C(0x1)
23778 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED0_TYPE_INVALID UINT32_C(0xff)
23779 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED0_TYPE_LAST \
23780 HWRM_PORT_LED_QCAPS_OUTPUT_LED0_TYPE_INVALID
23782 * An identifier for the group of LEDs that LED #0 belongs
23784 * If set to 0, then the LED #0 cannot be grouped.
23785 * For all other non-zero values of this field, LED #0 is
23786 * grouped together with the LEDs with the same group ID
23789 uint8_t led0_group_id;
23791 /* The states supported by LED #0. */
23792 uint16_t led0_state_caps;
23794 * If set to 1, this LED is enabled.
23795 * If set to 0, this LED is disabled.
23797 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED0_STATE_CAPS_ENABLED \
23800 * If set to 1, off state is supported on this LED.
23801 * If set to 0, off state is not supported on this LED.
23803 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED0_STATE_CAPS_OFF_SUPPORTED \
23806 * If set to 1, on state is supported on this LED.
23807 * If set to 0, on state is not supported on this LED.
23809 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED0_STATE_CAPS_ON_SUPPORTED \
23812 * If set to 1, blink state is supported on this LED.
23813 * If set to 0, blink state is not supported on this LED.
23815 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED0_STATE_CAPS_BLINK_SUPPORTED \
23818 * If set to 1, blink_alt state is supported on this LED.
23819 * If set to 0, blink_alt state is not supported on this LED.
23821 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED0_STATE_CAPS_BLINK_ALT_SUPPORTED \
23823 /* The colors supported by LED #0. */
23824 uint16_t led0_color_caps;
23826 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED0_COLOR_CAPS_RSVD \
23829 * If set to 1, Amber color is supported on this LED.
23830 * If set to 0, Amber color is not supported on this LED.
23832 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED0_COLOR_CAPS_AMBER_SUPPORTED \
23835 * If set to 1, Green color is supported on this LED.
23836 * If set to 0, Green color is not supported on this LED.
23838 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED0_COLOR_CAPS_GREEN_SUPPORTED \
23840 /* An identifier for the LED #1. */
23842 /* The type of LED #1. */
23845 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED1_TYPE_SPEED UINT32_C(0x0)
23847 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED1_TYPE_ACTIVITY UINT32_C(0x1)
23849 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED1_TYPE_INVALID UINT32_C(0xff)
23850 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED1_TYPE_LAST \
23851 HWRM_PORT_LED_QCAPS_OUTPUT_LED1_TYPE_INVALID
23853 * An identifier for the group of LEDs that LED #1 belongs
23855 * If set to 0, then the LED #0 cannot be grouped.
23856 * For all other non-zero values of this field, LED #0 is
23857 * grouped together with the LEDs with the same group ID
23860 uint8_t led1_group_id;
23862 /* The states supported by LED #1. */
23863 uint16_t led1_state_caps;
23865 * If set to 1, this LED is enabled.
23866 * If set to 0, this LED is disabled.
23868 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED1_STATE_CAPS_ENABLED \
23871 * If set to 1, off state is supported on this LED.
23872 * If set to 0, off state is not supported on this LED.
23874 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED1_STATE_CAPS_OFF_SUPPORTED \
23877 * If set to 1, on state is supported on this LED.
23878 * If set to 0, on state is not supported on this LED.
23880 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED1_STATE_CAPS_ON_SUPPORTED \
23883 * If set to 1, blink state is supported on this LED.
23884 * If set to 0, blink state is not supported on this LED.
23886 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED1_STATE_CAPS_BLINK_SUPPORTED \
23889 * If set to 1, blink_alt state is supported on this LED.
23890 * If set to 0, blink_alt state is not supported on this LED.
23892 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED1_STATE_CAPS_BLINK_ALT_SUPPORTED \
23894 /* The colors supported by LED #1. */
23895 uint16_t led1_color_caps;
23897 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED1_COLOR_CAPS_RSVD \
23900 * If set to 1, Amber color is supported on this LED.
23901 * If set to 0, Amber color is not supported on this LED.
23903 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED1_COLOR_CAPS_AMBER_SUPPORTED \
23906 * If set to 1, Green color is supported on this LED.
23907 * If set to 0, Green color is not supported on this LED.
23909 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED1_COLOR_CAPS_GREEN_SUPPORTED \
23911 /* An identifier for the LED #2. */
23913 /* The type of LED #2. */
23916 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED2_TYPE_SPEED UINT32_C(0x0)
23918 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED2_TYPE_ACTIVITY UINT32_C(0x1)
23920 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED2_TYPE_INVALID UINT32_C(0xff)
23921 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED2_TYPE_LAST \
23922 HWRM_PORT_LED_QCAPS_OUTPUT_LED2_TYPE_INVALID
23924 * An identifier for the group of LEDs that LED #0 belongs
23926 * If set to 0, then the LED #0 cannot be grouped.
23927 * For all other non-zero values of this field, LED #0 is
23928 * grouped together with the LEDs with the same group ID
23931 uint8_t led2_group_id;
23933 /* The states supported by LED #2. */
23934 uint16_t led2_state_caps;
23936 * If set to 1, this LED is enabled.
23937 * If set to 0, this LED is disabled.
23939 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED2_STATE_CAPS_ENABLED \
23942 * If set to 1, off state is supported on this LED.
23943 * If set to 0, off state is not supported on this LED.
23945 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED2_STATE_CAPS_OFF_SUPPORTED \
23948 * If set to 1, on state is supported on this LED.
23949 * If set to 0, on state is not supported on this LED.
23951 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED2_STATE_CAPS_ON_SUPPORTED \
23954 * If set to 1, blink state is supported on this LED.
23955 * If set to 0, blink state is not supported on this LED.
23957 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED2_STATE_CAPS_BLINK_SUPPORTED \
23960 * If set to 1, blink_alt state is supported on this LED.
23961 * If set to 0, blink_alt state is not supported on this LED.
23963 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED2_STATE_CAPS_BLINK_ALT_SUPPORTED \
23965 /* The colors supported by LED #2. */
23966 uint16_t led2_color_caps;
23968 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED2_COLOR_CAPS_RSVD \
23971 * If set to 1, Amber color is supported on this LED.
23972 * If set to 0, Amber color is not supported on this LED.
23974 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED2_COLOR_CAPS_AMBER_SUPPORTED \
23977 * If set to 1, Green color is supported on this LED.
23978 * If set to 0, Green color is not supported on this LED.
23980 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED2_COLOR_CAPS_GREEN_SUPPORTED \
23982 /* An identifier for the LED #3. */
23984 /* The type of LED #3. */
23987 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED3_TYPE_SPEED UINT32_C(0x0)
23989 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED3_TYPE_ACTIVITY UINT32_C(0x1)
23991 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED3_TYPE_INVALID UINT32_C(0xff)
23992 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED3_TYPE_LAST \
23993 HWRM_PORT_LED_QCAPS_OUTPUT_LED3_TYPE_INVALID
23995 * An identifier for the group of LEDs that LED #3 belongs
23997 * If set to 0, then the LED #0 cannot be grouped.
23998 * For all other non-zero values of this field, LED #0 is
23999 * grouped together with the LEDs with the same group ID
24002 uint8_t led3_group_id;
24004 /* The states supported by LED #3. */
24005 uint16_t led3_state_caps;
24007 * If set to 1, this LED is enabled.
24008 * If set to 0, this LED is disabled.
24010 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED3_STATE_CAPS_ENABLED \
24013 * If set to 1, off state is supported on this LED.
24014 * If set to 0, off state is not supported on this LED.
24016 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED3_STATE_CAPS_OFF_SUPPORTED \
24019 * If set to 1, on state is supported on this LED.
24020 * If set to 0, on state is not supported on this LED.
24022 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED3_STATE_CAPS_ON_SUPPORTED \
24025 * If set to 1, blink state is supported on this LED.
24026 * If set to 0, blink state is not supported on this LED.
24028 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED3_STATE_CAPS_BLINK_SUPPORTED \
24031 * If set to 1, blink_alt state is supported on this LED.
24032 * If set to 0, blink_alt state is not supported on this LED.
24034 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED3_STATE_CAPS_BLINK_ALT_SUPPORTED \
24036 /* The colors supported by LED #3. */
24037 uint16_t led3_color_caps;
24039 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED3_COLOR_CAPS_RSVD \
24042 * If set to 1, Amber color is supported on this LED.
24043 * If set to 0, Amber color is not supported on this LED.
24045 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED3_COLOR_CAPS_AMBER_SUPPORTED \
24048 * If set to 1, Green color is supported on this LED.
24049 * If set to 0, Green color is not supported on this LED.
24051 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED3_COLOR_CAPS_GREEN_SUPPORTED \
24053 uint8_t unused_4[3];
24055 * This field is used in Output records to indicate that the output
24056 * is completely written to RAM. This field should be read as '1'
24057 * to indicate that the output has been completely written.
24058 * When writing a command completion or response to an internal processor,
24059 * the order of writes has to be such that this field is written last.
24064 /***********************
24065 * hwrm_port_prbs_test *
24066 ***********************/
24069 /* hwrm_port_prbs_test_input (size:384b/48B) */
24070 struct hwrm_port_prbs_test_input {
24071 /* The HWRM command request type. */
24074 * The completion ring to send the completion event on. This should
24075 * be the NQ ID returned from the `nq_alloc` HWRM command.
24077 uint16_t cmpl_ring;
24079 * The sequence ID is used by the driver for tracking multiple
24080 * commands. This ID is treated as opaque data by the firmware and
24081 * the value is returned in the `hwrm_resp_hdr` upon completion.
24085 * The target ID of the command:
24086 * * 0x0-0xFFF8 - The function ID
24087 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
24088 * * 0xFFFD - Reserved for user-space HWRM interface
24091 uint16_t target_id;
24093 * A physical address pointer pointing to a host buffer that the
24094 * command's response data will be written. This can be either a host
24095 * physical address (HPA) or a guest physical address (GPA) and must
24096 * point to a physically contiguous block of memory.
24098 uint64_t resp_addr;
24099 /* Host address data is to DMA'd to. */
24100 uint64_t resp_data_addr;
24102 * Size of the buffer pointed to by resp_data_addr. The firmware may
24103 * use this entire buffer or less than the entire buffer, but never more.
24108 /* Port ID of port where PRBS test to be run. */
24110 /* Polynomial selection for PRBS test. */
24113 #define HWRM_PORT_PRBS_TEST_INPUT_POLY_PRBS7 UINT32_C(0x0)
24115 #define HWRM_PORT_PRBS_TEST_INPUT_POLY_PRBS9 UINT32_C(0x1)
24117 #define HWRM_PORT_PRBS_TEST_INPUT_POLY_PRBS11 UINT32_C(0x2)
24119 #define HWRM_PORT_PRBS_TEST_INPUT_POLY_PRBS15 UINT32_C(0x3)
24121 #define HWRM_PORT_PRBS_TEST_INPUT_POLY_PRBS23 UINT32_C(0x4)
24123 #define HWRM_PORT_PRBS_TEST_INPUT_POLY_PRBS31 UINT32_C(0x5)
24125 #define HWRM_PORT_PRBS_TEST_INPUT_POLY_PRBS58 UINT32_C(0x6)
24127 #define HWRM_PORT_PRBS_TEST_INPUT_POLY_INVALID UINT32_C(0xff)
24128 #define HWRM_PORT_PRBS_TEST_INPUT_POLY_LAST \
24129 HWRM_PORT_PRBS_TEST_INPUT_POLY_INVALID
24131 * Configuration bits for PRBS test.
24132 * Use enable bit to start/stop test.
24133 * Use tx/rx lane map bits to run test on specific lanes,
24134 * if set to 0 test will be run on all lanes.
24136 uint16_t prbs_config;
24138 * Set 0 to stop test currently in progress
24139 * Set 1 to start test with configuration provided.
24141 #define HWRM_PORT_PRBS_TEST_INPUT_PRBS_CONFIG_START_STOP \
24144 * If set to 1, tx_lane_map bitmap should have lane bits set.
24145 * If set to 0, test will be run on all lanes for this port.
24147 #define HWRM_PORT_PRBS_TEST_INPUT_PRBS_CONFIG_TX_LANE_MAP_VALID \
24150 * If set to 1, rx_lane_map bitmap should have lane bits set.
24151 * If set to 0, test will be run on all lanes for this port.
24153 #define HWRM_PORT_PRBS_TEST_INPUT_PRBS_CONFIG_RX_LANE_MAP_VALID \
24155 /* Duration in seconds to run the PRBS test. */
24158 * If tx_lane_map_valid is set to 1, this field is a bitmap
24159 * of tx lanes to run PRBS test. bit0 = lane0,
24160 * bit1 = lane1 ..bit31 = lane31
24162 uint32_t tx_lane_map;
24164 * If rx_lane_map_valid is set to 1, this field is a bitmap
24165 * of rx lanes to run PRBS test. bit0 = lane0,
24166 * bit1 = lane1 ..bit31 = lane31
24168 uint32_t rx_lane_map;
24171 /* hwrm_port_prbs_test_output (size:128b/16B) */
24172 struct hwrm_port_prbs_test_output {
24173 /* The specific error status for the command. */
24174 uint16_t error_code;
24175 /* The HWRM command request type. */
24177 /* The sequence ID from the original command. */
24179 /* The length of the response data in number of bytes. */
24181 /* Total length of stored data. */
24182 uint16_t total_data_len;
24184 uint8_t unused_1[3];
24186 * This field is used in Output records to indicate that the output
24187 * is completely written to RAM. This field should be read as '1'
24188 * to indicate that the output has been completely written.
24189 * When writing a command completion or response to an internal processor,
24190 * the order of writes has to be such that this field is written last.
24195 /**********************
24196 * hwrm_port_dsc_dump *
24197 **********************/
24200 /* hwrm_port_dsc_dump_input (size:320b/40B) */
24201 struct hwrm_port_dsc_dump_input {
24202 /* The HWRM command request type. */
24205 * The completion ring to send the completion event on. This should
24206 * be the NQ ID returned from the `nq_alloc` HWRM command.
24208 uint16_t cmpl_ring;
24210 * The sequence ID is used by the driver for tracking multiple
24211 * commands. This ID is treated as opaque data by the firmware and
24212 * the value is returned in the `hwrm_resp_hdr` upon completion.
24216 * The target ID of the command:
24217 * * 0x0-0xFFF8 - The function ID
24218 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
24219 * * 0xFFFD - Reserved for user-space HWRM interface
24222 uint16_t target_id;
24224 * A physical address pointer pointing to a host buffer that the
24225 * command's response data will be written. This can be either a host
24226 * physical address (HPA) or a guest physical address (GPA) and must
24227 * point to a physically contiguous block of memory.
24229 uint64_t resp_addr;
24230 /* Host address where response diagnostic data is returned. */
24231 uint64_t resp_data_addr;
24233 * Size of the buffer pointed to by resp_data_addr. The firmware
24234 * may use this entire buffer or less than the entire buffer, but
24240 /* Port ID of port where dsc dump to be collected. */
24242 /* Diag level specified by the user */
24243 uint16_t diag_level;
24244 /* SRDS_DIAG_LANE */
24245 #define HWRM_PORT_DSC_DUMP_INPUT_DIAG_LEVEL_SRDS_DIAG_LANE \
24247 /* SRDS_DIAG_CORE */
24248 #define HWRM_PORT_DSC_DUMP_INPUT_DIAG_LEVEL_SRDS_DIAG_CORE \
24250 /* SRDS_DIAG_EVENT */
24251 #define HWRM_PORT_DSC_DUMP_INPUT_DIAG_LEVEL_SRDS_DIAG_EVENT \
24253 /* SRDS_DIAG_EYE */
24254 #define HWRM_PORT_DSC_DUMP_INPUT_DIAG_LEVEL_SRDS_DIAG_EYE \
24256 /* SRDS_DIAG_REG_CORE */
24257 #define HWRM_PORT_DSC_DUMP_INPUT_DIAG_LEVEL_SRDS_DIAG_REG_CORE \
24259 /* SRDS_DIAG_REG_LANE */
24260 #define HWRM_PORT_DSC_DUMP_INPUT_DIAG_LEVEL_SRDS_DIAG_REG_LANE \
24262 /* SRDS_DIAG_UC_CORE */
24263 #define HWRM_PORT_DSC_DUMP_INPUT_DIAG_LEVEL_SRDS_DIAG_UC_CORE \
24265 /* SRDS_DIAG_UC_LANE */
24266 #define HWRM_PORT_DSC_DUMP_INPUT_DIAG_LEVEL_SRDS_DIAG_UC_LANE \
24268 /* SRDS_DIAG_LANE_DEBUG */
24269 #define HWRM_PORT_DSC_DUMP_INPUT_DIAG_LEVEL_SRDS_DIAG_LANE_DEBUG \
24271 /* SRDS_DIAG_BER_VERT */
24272 #define HWRM_PORT_DSC_DUMP_INPUT_DIAG_LEVEL_SRDS_DIAG_BER_VERT \
24274 /* SRDS_DIAG_BER_HORZ */
24275 #define HWRM_PORT_DSC_DUMP_INPUT_DIAG_LEVEL_SRDS_DIAG_BER_HORZ \
24277 /* SRDS_DIAG_EVENT_SAFE */
24278 #define HWRM_PORT_DSC_DUMP_INPUT_DIAG_LEVEL_SRDS_DIAG_EVENT_SAFE \
24280 /* SRDS_DIAG_TIMESTAMP */
24281 #define HWRM_PORT_DSC_DUMP_INPUT_DIAG_LEVEL_SRDS_DIAG_TIMESTAMP \
24283 #define HWRM_PORT_DSC_DUMP_INPUT_DIAG_LEVEL_LAST \
24284 HWRM_PORT_DSC_DUMP_INPUT_DIAG_LEVEL_SRDS_DIAG_TIMESTAMP
24286 * This field is a lane number
24287 * on which to collect the dsc dump
24289 uint16_t lane_number;
24291 * Configuration bits.
24292 * Use enable bit to start dsc dump or retrieve dump
24294 uint16_t dsc_dump_config;
24296 * Set 0 to retrieve the dsc dump
24297 * Set 1 to start the dsc dump
24299 #define HWRM_PORT_DSC_DUMP_INPUT_DSC_DUMP_CONFIG_START_RETRIEVE \
24303 /* hwrm_port_dsc_dump_output (size:128b/16B) */
24304 struct hwrm_port_dsc_dump_output {
24305 /* The specific error status for the command. */
24306 uint16_t error_code;
24307 /* The HWRM command request type. */
24309 /* The sequence ID from the original command. */
24311 /* The length of the response data in number of bytes. */
24313 /* Total length of stored data. */
24314 uint16_t total_data_len;
24316 uint8_t unused_1[3];
24318 * This field is used in Output records to indicate that the output
24319 * is completely written to RAM. This field should be read as '1'
24320 * to indicate that the output has been completely written.
24321 * When writing a command completion or response to an internal processor,
24322 * the order of writes has to be such that this field is written last.
24327 /******************************
24328 * hwrm_port_sfp_sideband_cfg *
24329 ******************************/
24332 /* hwrm_port_sfp_sideband_cfg_input (size:256b/32B) */
24333 struct hwrm_port_sfp_sideband_cfg_input {
24334 /* The HWRM command request type. */
24337 * The completion ring to send the completion event on. This should
24338 * be the NQ ID returned from the `nq_alloc` HWRM command.
24340 uint16_t cmpl_ring;
24342 * The sequence ID is used by the driver for tracking multiple
24343 * commands. This ID is treated as opaque data by the firmware and
24344 * the value is returned in the `hwrm_resp_hdr` upon completion.
24348 * The target ID of the command:
24349 * * 0x0-0xFFF8 - The function ID
24350 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
24351 * * 0xFFFD - Reserved for user-space HWRM interface
24354 uint16_t target_id;
24356 * A physical address pointer pointing to a host buffer that the
24357 * command's response data will be written. This can be either a host
24358 * physical address (HPA) or a guest physical address (GPA) and must
24359 * point to a physically contiguous block of memory.
24361 uint64_t resp_addr;
24362 /* Port ID of port that is to be queried. */
24364 uint8_t unused_0[6];
24366 * This bitfield is used to specify which bits from the 'flags'
24367 * fields are being configured by the caller.
24370 /* This bit must be '1' for rs0 to be configured. */
24371 #define HWRM_PORT_SFP_SIDEBAND_CFG_INPUT_ENABLES_RS0 \
24373 /* This bit must be '1' for rs1 to be configured. */
24374 #define HWRM_PORT_SFP_SIDEBAND_CFG_INPUT_ENABLES_RS1 \
24376 /* This bit must be '1' for tx_disable to be configured. */
24377 #define HWRM_PORT_SFP_SIDEBAND_CFG_INPUT_ENABLES_TX_DIS \
24380 * This bit must be '1' for mod_sel to be configured.
24381 * Valid only on QSFP modules
24383 #define HWRM_PORT_SFP_SIDEBAND_CFG_INPUT_ENABLES_MOD_SEL \
24385 /* This bit must be '1' for reset_l to be configured. */
24386 #define HWRM_PORT_SFP_SIDEBAND_CFG_INPUT_ENABLES_RESET_L \
24388 /* This bit must be '1' for lp_mode to be configured. */
24389 #define HWRM_PORT_SFP_SIDEBAND_CFG_INPUT_ENABLES_LP_MODE \
24391 /* This bit must be '1' for pwr_disable to be configured. */
24392 #define HWRM_PORT_SFP_SIDEBAND_CFG_INPUT_ENABLES_PWR_DIS \
24395 * Only bits that have corresponding bits in the 'enables'
24396 * bitfield are processed by the firmware, all other bits
24397 * of 'flags' are ignored.
24401 * This bit along with rs1 configures the current speed of the dual
24402 * rate module. If these pins are GNDed then the speed can be changed
24403 * by driectly writing to EEPROM.
24405 #define HWRM_PORT_SFP_SIDEBAND_CFG_INPUT_FLAGS_RS0 \
24408 * This bit along with rs0 configures the current speed of the dual
24409 * rate module. If these pins are GNDed then the speed can be changed
24410 * by driectly writing to EEPROM.
24412 #define HWRM_PORT_SFP_SIDEBAND_CFG_INPUT_FLAGS_RS1 \
24415 * When this bit is set to '1', tx_disable is set.
24416 * On a 1G BASE-T module, if this bit is set,
24417 * module PHY registers will not be accessible.
24419 #define HWRM_PORT_SFP_SIDEBAND_CFG_INPUT_FLAGS_TX_DIS \
24422 * When this bit is set to '1', this module is selected.
24423 * Valid only on QSFP modules
24425 #define HWRM_PORT_SFP_SIDEBAND_CFG_INPUT_FLAGS_MOD_SEL \
24428 * If reset_l is set to 0, Module will be taken out of reset
24429 * and other signals will be set to their requested state once
24430 * the module is out of reset.
24431 * Valid only on QSFP modules
24433 #define HWRM_PORT_SFP_SIDEBAND_CFG_INPUT_FLAGS_RESET_L \
24436 * When this bit is set to '1', the module will be configured
24437 * in low power mode.
24438 * Valid only on QSFP modules
24440 #define HWRM_PORT_SFP_SIDEBAND_CFG_INPUT_FLAGS_LP_MODE \
24442 /* When this bit is set to '1', the module will be powered down. */
24443 #define HWRM_PORT_SFP_SIDEBAND_CFG_INPUT_FLAGS_PWR_DIS \
24447 /* hwrm_port_sfp_sideband_cfg_output (size:128b/16B) */
24448 struct hwrm_port_sfp_sideband_cfg_output {
24449 /* The specific error status for the command. */
24450 uint16_t error_code;
24451 /* The HWRM command request type. */
24453 /* The sequence ID from the original command. */
24455 /* The length of the response data in number of bytes. */
24459 * This field is used in Output records to indicate that the output
24460 * is completely written to RAM. This field should be read as '1'
24461 * to indicate that the output has been completely written. When
24462 * writing a command completion or response to an internal processor,
24463 * the order of writes has to be such that this field is written last.
24468 /*******************************
24469 * hwrm_port_sfp_sideband_qcfg *
24470 *******************************/
24473 /* hwrm_port_sfp_sideband_qcfg_input (size:192b/24B) */
24474 struct hwrm_port_sfp_sideband_qcfg_input {
24475 /* The HWRM command request type. */
24478 * The completion ring to send the completion event on. This should
24479 * be the NQ ID returned from the `nq_alloc` HWRM command.
24481 uint16_t cmpl_ring;
24483 * The sequence ID is used by the driver for tracking multiple
24484 * commands. This ID is treated as opaque data by the firmware and
24485 * the value is returned in the `hwrm_resp_hdr` upon completion.
24489 * The target ID of the command:
24490 * * 0x0-0xFFF8 - The function ID
24491 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
24492 * * 0xFFFD - Reserved for user-space HWRM interface
24495 uint16_t target_id;
24497 * A physical address pointer pointing to a host buffer that the
24498 * command's response data will be written. This can be either a host
24499 * physical address (HPA) or a guest physical address (GPA) and must
24500 * point to a physically contiguous block of memory.
24502 uint64_t resp_addr;
24503 /* Port ID of port that is to be queried. */
24505 uint8_t unused_0[6];
24508 /* hwrm_port_sfp_sideband_qcfg_output (size:192b/24B) */
24509 struct hwrm_port_sfp_sideband_qcfg_output {
24510 /* The specific error status for the command. */
24511 uint16_t error_code;
24512 /* The HWRM command request type. */
24514 /* The sequence ID from the original command. */
24516 /* The length of the response data in number of bytes. */
24519 * Bitmask indicating which sideband signals are valid.
24520 * This is based on the board and nvm cfg that is present on the board.
24522 uint32_t supported_mask;
24523 uint32_t sideband_signals;
24524 /* When this bit is set to '1', the Module is absent. */
24525 #define HWRM_PORT_SFP_SIDEBAND_QCFG_OUTPUT_SIDEBAND_SIGNALS_MOD_ABS \
24528 * When this bit is set to '1', there is no valid signal on RX.
24529 * This signal is a filtered version of Signal Detect.
24531 #define HWRM_PORT_SFP_SIDEBAND_QCFG_OUTPUT_SIDEBAND_SIGNALS_RX_LOS \
24534 * This bit along with rs1 indiactes the current speed of the dual
24535 * rate module.If these pins are grounded then the speed can be
24536 * changed by driectky writing to EEPROM.
24538 #define HWRM_PORT_SFP_SIDEBAND_QCFG_OUTPUT_SIDEBAND_SIGNALS_RS0 \
24541 * This bit along with rs0 indiactes the current speed of the dual
24542 * rate module.If these pins are grounded then the speed can be
24543 * changed by driectky writing to EEPROM.
24545 #define HWRM_PORT_SFP_SIDEBAND_QCFG_OUTPUT_SIDEBAND_SIGNALS_RS1 \
24548 * When this bit is set to '1', tx_disable is set.
24549 * On a 1G BASE-T module, if this bit is set, module PHY
24550 * registers will not be accessible.
24552 #define HWRM_PORT_SFP_SIDEBAND_QCFG_OUTPUT_SIDEBAND_SIGNALS_TX_DIS \
24554 /* When this bit is set to '1', tx_fault is set. */
24555 #define HWRM_PORT_SFP_SIDEBAND_QCFG_OUTPUT_SIDEBAND_SIGNALS_TX_FAULT \
24558 * When this bit is set to '1', module is selected.
24559 * Valid only on QSFP modules
24561 #define HWRM_PORT_SFP_SIDEBAND_QCFG_OUTPUT_SIDEBAND_SIGNALS_MOD_SEL \
24564 * When this bit is set to '0', the module is held in reset.
24565 * if reset_l is set to 1,first module is taken out of reset
24566 * and other signals will be set to their requested state.
24567 * Valid only on QSFP modules.
24569 #define HWRM_PORT_SFP_SIDEBAND_QCFG_OUTPUT_SIDEBAND_SIGNALS_RESET_L \
24572 * When this bit is set to '1', the module is in low power mode.
24573 * Valid only on QSFP modules
24575 #define HWRM_PORT_SFP_SIDEBAND_QCFG_OUTPUT_SIDEBAND_SIGNALS_LP_MODE \
24577 /* When this bit is set to '1', module is in power down state. */
24578 #define HWRM_PORT_SFP_SIDEBAND_QCFG_OUTPUT_SIDEBAND_SIGNALS_PWR_DIS \
24582 * This field is used in Output records to indicate that the output
24583 * is completely written to RAM. This field should be read as '1'
24584 * to indicate that the output has been completely written. When
24585 * writing a command completion or response to an internal processor,
24586 * the order of writes has to be such that this field is written last.
24591 /**********************************
24592 * hwrm_port_phy_mdio_bus_acquire *
24593 **********************************/
24596 /* hwrm_port_phy_mdio_bus_acquire_input (size:192b/24B) */
24597 struct hwrm_port_phy_mdio_bus_acquire_input {
24598 /* The HWRM command request type. */
24601 * The completion ring to send the completion event on. This should
24602 * be the NQ ID returned from the `nq_alloc` HWRM command.
24604 uint16_t cmpl_ring;
24606 * The sequence ID is used by the driver for tracking multiple
24607 * commands. This ID is treated as opaque data by the firmware and
24608 * the value is returned in the `hwrm_resp_hdr` upon completion.
24612 * The target ID of the command:
24613 * * 0x0-0xFFF8 - The function ID
24614 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
24615 * * 0xFFFD - Reserved for user-space HWRM interface
24618 uint16_t target_id;
24620 * A physical address pointer pointing to a host buffer that the
24621 * command's response data will be written. This can be either a host
24622 * physical address (HPA) or a guest physical address (GPA) and must
24623 * point to a physically contiguous block of memory.
24625 uint64_t resp_addr;
24626 /* Port ID of the port. */
24629 * client_id of the client requesting BUS access.
24630 * Any value from 0x10 to 0xFFFF can be used.
24631 * Client should make sure that the returned client_id
24632 * in response matches the client_id in request.
24633 * 0-0xF are reserved for internal use.
24635 uint16_t client_id;
24637 * Timeout in milli seconds, MDIO BUS will be released automatically
24638 * after this time, if another mdio acquire command is not received
24639 * within the timeout window from the same client.
24640 * A 0xFFFF will hold the bus until this bus is released.
24642 uint16_t mdio_bus_timeout;
24643 uint8_t unused_0[2];
24646 /* hwrm_port_phy_mdio_bus_acquire_output (size:128b/16B) */
24647 struct hwrm_port_phy_mdio_bus_acquire_output {
24648 /* The specific error status for the command. */
24649 uint16_t error_code;
24650 /* The HWRM command request type. */
24652 /* The sequence ID from the original command. */
24654 /* The length of the response data in number of bytes. */
24658 * client_id of the module holding the BUS.
24659 * 0-0xF are reserved for internal use.
24661 uint16_t client_id;
24662 uint8_t unused_1[3];
24664 * This field is used in Output records to indicate that the output
24665 * is completely written to RAM. This field should be read as '1'
24666 * to indicate that the output has been completely written.
24667 * When writing a command completion or response to an internal processor,
24668 * the order of writes has to be such that this field is written last.
24673 /**********************************
24674 * hwrm_port_phy_mdio_bus_release *
24675 **********************************/
24678 /* hwrm_port_phy_mdio_bus_release_input (size:192b/24B) */
24679 struct hwrm_port_phy_mdio_bus_release_input {
24680 /* The HWRM command request type. */
24683 * The completion ring to send the completion event on. This should
24684 * be the NQ ID returned from the `nq_alloc` HWRM command.
24686 uint16_t cmpl_ring;
24688 * The sequence ID is used by the driver for tracking multiple
24689 * commands. This ID is treated as opaque data by the firmware and
24690 * the value is returned in the `hwrm_resp_hdr` upon completion.
24694 * The target ID of the command:
24695 * * 0x0-0xFFF8 - The function ID
24696 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
24697 * * 0xFFFD - Reserved for user-space HWRM interface
24700 uint16_t target_id;
24702 * A physical address pointer pointing to a host buffer that the
24703 * command's response data will be written. This can be either a host
24704 * physical address (HPA) or a guest physical address (GPA) and must
24705 * point to a physically contiguous block of memory.
24707 uint64_t resp_addr;
24708 /* Port ID of the port. */
24711 * client_id of the client requesting BUS release.
24712 * A client should not release any other clients BUS.
24714 uint16_t client_id;
24715 uint8_t unused_0[4];
24718 /* hwrm_port_phy_mdio_bus_release_output (size:128b/16B) */
24719 struct hwrm_port_phy_mdio_bus_release_output {
24720 /* The specific error status for the command. */
24721 uint16_t error_code;
24722 /* The HWRM command request type. */
24724 /* The sequence ID from the original command. */
24726 /* The length of the response data in number of bytes. */
24729 /* The BUS is released if client_id matches the client_id in request. */
24730 uint16_t clients_id;
24731 uint8_t unused_1[3];
24733 * This field is used in Output records to indicate that the output
24734 * is completely written to RAM. This field should be read as '1'
24735 * to indicate that the output has been completely written.
24736 * When writing a command completion or response to an internal processor,
24737 * the order of writes has to be such that this field is written last.
24742 /************************
24743 * hwrm_port_tx_fir_cfg *
24744 ************************/
24747 /* hwrm_port_tx_fir_cfg_input (size:320b/40B) */
24748 struct hwrm_port_tx_fir_cfg_input {
24749 /* The HWRM command request type. */
24752 * The completion ring to send the completion event on. This should
24753 * be the NQ ID returned from the `nq_alloc` HWRM command.
24755 uint16_t cmpl_ring;
24757 * The sequence ID is used by the driver for tracking multiple
24758 * commands. This ID is treated as opaque data by the firmware and
24759 * the value is returned in the `hwrm_resp_hdr` upon completion.
24763 * The target ID of the command:
24764 * * 0x0-0xFFF8 - The function ID
24765 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
24766 * * 0xFFFD - Reserved for user-space HWRM interface
24769 uint16_t target_id;
24771 * A physical address pointer pointing to a host buffer that the
24772 * command's response data will be written. This can be either a host
24773 * physical address (HPA) or a guest physical address (GPA) and must
24774 * point to a physically contiguous block of memory.
24776 uint64_t resp_addr;
24777 /* Modulation types of TX FIR: NRZ, PAM4. */
24780 #define HWRM_PORT_TX_FIR_CFG_INPUT_MOD_TYPE_NRZ UINT32_C(0x0)
24782 #define HWRM_PORT_TX_FIR_CFG_INPUT_MOD_TYPE_PAM4 UINT32_C(0x1)
24783 #define HWRM_PORT_TX_FIR_CFG_INPUT_MOD_TYPE_LAST \
24784 HWRM_PORT_TX_FIR_CFG_INPUT_MOD_TYPE_PAM4
24785 /* The lane mask of the lane TX FIR will be configured. */
24787 uint8_t unused_0[2];
24788 /* Value1 of TX FIR, required for NRZ or PAM4. */
24789 uint32_t txfir_val_1;
24790 /* Value2 of TX FIR, required for NRZ or PAM4. */
24791 uint32_t txfir_val_2;
24792 /* Value3 of TX FIR, required for PAM4. */
24793 uint32_t txfir_val_3;
24794 /* Value4 of TX FIR, required for PAM4. */
24795 uint32_t txfir_val_4;
24796 uint8_t unused_1[4];
24799 /* hwrm_port_tx_fir_cfg_output (size:128b/16B) */
24800 struct hwrm_port_tx_fir_cfg_output {
24801 /* The specific error status for the command. */
24802 uint16_t error_code;
24803 /* The HWRM command request type. */
24805 /* The sequence ID from the original command. */
24807 /* The length of the response data in number of bytes. */
24811 * This field is used in Output records to indicate that the output
24812 * is completely written to RAM. This field should be read as '1'
24813 * to indicate that the output has been completely written.
24814 * When writing a command completion or response to an internal processor,
24815 * the order of writes has to be such that this field is written last.
24820 /*************************
24821 * hwrm_port_tx_fir_qcfg *
24822 *************************/
24825 /* hwrm_port_tx_fir_qcfg_input (size:192b/24B) */
24826 struct hwrm_port_tx_fir_qcfg_input {
24827 /* The HWRM command request type. */
24830 * The completion ring to send the completion event on. This should
24831 * be the NQ ID returned from the `nq_alloc` HWRM command.
24833 uint16_t cmpl_ring;
24835 * The sequence ID is used by the driver for tracking multiple
24836 * commands. This ID is treated as opaque data by the firmware and
24837 * the value is returned in the `hwrm_resp_hdr` upon completion.
24841 * The target ID of the command:
24842 * * 0x0-0xFFF8 - The function ID
24843 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
24844 * * 0xFFFD - Reserved for user-space HWRM interface
24847 uint16_t target_id;
24849 * A physical address pointer pointing to a host buffer that the
24850 * command's response data will be written. This can be either a host
24851 * physical address (HPA) or a guest physical address (GPA) and must
24852 * point to a physically contiguous block of memory.
24854 uint64_t resp_addr;
24855 /* Modulation types of TX FIR: NRZ, PAM4. */
24858 #define HWRM_PORT_TX_FIR_QCFG_INPUT_MOD_TYPE_NRZ UINT32_C(0x0)
24860 #define HWRM_PORT_TX_FIR_QCFG_INPUT_MOD_TYPE_PAM4 UINT32_C(0x1)
24861 #define HWRM_PORT_TX_FIR_QCFG_INPUT_MOD_TYPE_LAST \
24862 HWRM_PORT_TX_FIR_QCFG_INPUT_MOD_TYPE_PAM4
24863 /* The ID of the lane TX FIR will be queried. */
24868 /* hwrm_port_tx_fir_qcfg_output (size:256b/32B) */
24869 struct hwrm_port_tx_fir_qcfg_output {
24870 /* The specific error status for the command. */
24871 uint16_t error_code;
24872 /* The HWRM command request type. */
24874 /* The sequence ID from the original command. */
24876 /* The length of the response data in number of bytes. */
24878 /* Value1 of TX FIR, required for NRZ or PAM4. */
24879 uint32_t txfir_val_1;
24880 /* Value2 of TX FIR, required for NRZ or PAM4. */
24881 uint32_t txfir_val_2;
24882 /* Value3 of TX FIR, required for PAM4. */
24883 uint32_t txfir_val_3;
24884 /* Value4 of TX FIR, required for PAM4. */
24885 uint32_t txfir_val_4;
24888 * This field is used in Output records to indicate that the output
24889 * is completely written to RAM. This field should be read as '1'
24890 * to indicate that the output has been completely written.
24891 * When writing a command completion or response to an internal processor,
24892 * the order of writes has to be such that this field is written last.
24897 /***********************
24898 * hwrm_queue_qportcfg *
24899 ***********************/
24902 /* hwrm_queue_qportcfg_input (size:192b/24B) */
24903 struct hwrm_queue_qportcfg_input {
24904 /* The HWRM command request type. */
24907 * The completion ring to send the completion event on. This should
24908 * be the NQ ID returned from the `nq_alloc` HWRM command.
24910 uint16_t cmpl_ring;
24912 * The sequence ID is used by the driver for tracking multiple
24913 * commands. This ID is treated as opaque data by the firmware and
24914 * the value is returned in the `hwrm_resp_hdr` upon completion.
24918 * The target ID of the command:
24919 * * 0x0-0xFFF8 - The function ID
24920 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
24921 * * 0xFFFD - Reserved for user-space HWRM interface
24924 uint16_t target_id;
24926 * A physical address pointer pointing to a host buffer that the
24927 * command's response data will be written. This can be either a host
24928 * physical address (HPA) or a guest physical address (GPA) and must
24929 * point to a physically contiguous block of memory.
24931 uint64_t resp_addr;
24934 * Enumeration denoting the RX, TX type of the resource.
24935 * This enumeration is used for resources that are similar for both
24936 * TX and RX paths of the chip.
24938 #define HWRM_QUEUE_QPORTCFG_INPUT_FLAGS_PATH UINT32_C(0x1)
24940 #define HWRM_QUEUE_QPORTCFG_INPUT_FLAGS_PATH_TX UINT32_C(0x0)
24942 #define HWRM_QUEUE_QPORTCFG_INPUT_FLAGS_PATH_RX UINT32_C(0x1)
24943 #define HWRM_QUEUE_QPORTCFG_INPUT_FLAGS_PATH_LAST \
24944 HWRM_QUEUE_QPORTCFG_INPUT_FLAGS_PATH_RX
24946 * Port ID of port for which the queue configuration is being
24947 * queried. This field is only required when sent by IPC.
24951 * Drivers will set this capability when it can use
24952 * queue_idx_service_profile to map the queues to application.
24954 uint8_t drv_qmap_cap;
24956 #define HWRM_QUEUE_QPORTCFG_INPUT_DRV_QMAP_CAP_DISABLED UINT32_C(0x0)
24958 #define HWRM_QUEUE_QPORTCFG_INPUT_DRV_QMAP_CAP_ENABLED UINT32_C(0x1)
24959 #define HWRM_QUEUE_QPORTCFG_INPUT_DRV_QMAP_CAP_LAST \
24960 HWRM_QUEUE_QPORTCFG_INPUT_DRV_QMAP_CAP_ENABLED
24964 /* hwrm_queue_qportcfg_output (size:1344b/168B) */
24965 struct hwrm_queue_qportcfg_output {
24966 /* The specific error status for the command. */
24967 uint16_t error_code;
24968 /* The HWRM command request type. */
24970 /* The sequence ID from the original command. */
24972 /* The length of the response data in number of bytes. */
24975 * The maximum number of queues that can be configured on this
24977 * Valid values range from 1 through 8.
24979 uint8_t max_configurable_queues;
24981 * The maximum number of lossless queues that can be configured
24983 * Valid values range from 0 through 8.
24985 uint8_t max_configurable_lossless_queues;
24987 * Bitmask indicating which queues can be configured by the
24988 * hwrm_queue_cfg command.
24990 * Each bit represents a specific queue where bit 0 represents
24991 * queue 0 and bit 7 represents queue 7.
24992 * # A value of 0 indicates that the queue is not configurable
24993 * by the hwrm_queue_cfg command.
24994 * # A value of 1 indicates that the queue is configurable.
24995 * # A hwrm_queue_cfg command shall return error when trying to
24996 * configure a queue not configurable.
24998 uint8_t queue_cfg_allowed;
24999 /* Information about queue configuration. */
25000 uint8_t queue_cfg_info;
25002 * If this flag is set to '1', then the queues are
25003 * configured asymmetrically on TX and RX sides.
25004 * If this flag is set to '0', then the queues are
25005 * configured symmetrically on TX and RX sides. For
25006 * symmetric configuration, the queue configuration
25007 * including queue ids and service profiles on the
25008 * TX side is the same as the corresponding queue
25009 * configuration on the RX side.
25011 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_CFG_INFO_ASYM_CFG \
25014 * Bitmask indicating which queues can be configured by the
25015 * hwrm_queue_pfcenable_cfg command.
25017 * Each bit represents a specific priority where bit 0 represents
25018 * priority 0 and bit 7 represents priority 7.
25019 * # A value of 0 indicates that the priority is not configurable by
25020 * the hwrm_queue_pfcenable_cfg command.
25021 * # A value of 1 indicates that the priority is configurable.
25022 * # A hwrm_queue_pfcenable_cfg command shall return error when
25023 * trying to configure a priority that is not configurable.
25025 uint8_t queue_pfcenable_cfg_allowed;
25027 * Bitmask indicating which queues can be configured by the
25028 * hwrm_queue_pri2cos_cfg command.
25030 * Each bit represents a specific queue where bit 0 represents
25031 * queue 0 and bit 7 represents queue 7.
25032 * # A value of 0 indicates that the queue is not configurable
25033 * by the hwrm_queue_pri2cos_cfg command.
25034 * # A value of 1 indicates that the queue is configurable.
25035 * # A hwrm_queue_pri2cos_cfg command shall return error when
25036 * trying to configure a queue that is not configurable.
25038 uint8_t queue_pri2cos_cfg_allowed;
25040 * Bitmask indicating which queues can be configured by the
25041 * hwrm_queue_pri2cos_cfg command.
25043 * Each bit represents a specific queue where bit 0 represents
25044 * queue 0 and bit 7 represents queue 7.
25045 * # A value of 0 indicates that the queue is not configurable
25046 * by the hwrm_queue_pri2cos_cfg command.
25047 * # A value of 1 indicates that the queue is configurable.
25048 * # A hwrm_queue_pri2cos_cfg command shall return error when
25049 * trying to configure a queue not configurable.
25051 uint8_t queue_cos2bw_cfg_allowed;
25053 * ID of CoS Queue 0.
25056 * # This ID can be used on any subsequent call to an hwrm command
25057 * that takes a queue id.
25058 * # IDs must always be queried by this command before any use
25059 * by the driver or software.
25060 * # The CoS queue index is obtained by applying modulo 10 to the
25061 * CoS queue ID. Valid CoS queue indexes are in the range of 0 to 7.
25062 * The CoS queue index is used to reference port statistics for the
25064 * # A value of 0xff indicates that the queue is not available.
25065 * # Available queues may not be in sequential order.
25068 /* This value specifies service profile kind for CoS queue */
25069 uint8_t queue_id0_service_profile;
25070 /* Lossy (best-effort) */
25071 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID0_SERVICE_PROFILE_LOSSY \
25074 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID0_SERVICE_PROFILE_LOSSLESS \
25076 /* Lossless RoCE (deprecated) */
25077 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID0_SERVICE_PROFILE_LOSSLESS_ROCE \
25079 /* Lossy RoCE CNP (deprecated) */
25080 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID0_SERVICE_PROFILE_LOSSY_ROCE_CNP \
25082 /* Lossless NIC (deprecated) */
25083 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID0_SERVICE_PROFILE_LOSSLESS_NIC \
25085 /* Set to 0xFF... (All Fs) if there is no service profile specified */
25086 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID0_SERVICE_PROFILE_UNKNOWN \
25088 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID0_SERVICE_PROFILE_LAST \
25089 HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID0_SERVICE_PROFILE_UNKNOWN
25091 * ID of CoS Queue 1.
25094 * # This ID can be used on any subsequent call to an hwrm command
25095 * that takes a queue id.
25096 * # IDs must always be queried by this command before any use
25097 * by the driver or software.
25098 * # The CoS queue index is obtained by applying modulo 10 to the
25099 * CoS queue ID. Valid CoS queue indexes are in the range of 0 to 7.
25100 * The CoS queue index is used to reference port statistics for the
25102 * # A value of 0xff indicates that the queue is not available.
25103 * # Available queues may not be in sequential order.
25106 /* This value specifies service profile kind for CoS queue */
25107 uint8_t queue_id1_service_profile;
25108 /* Lossy (best-effort) */
25109 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID1_SERVICE_PROFILE_LOSSY \
25112 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID1_SERVICE_PROFILE_LOSSLESS \
25114 /* Lossless RoCE (deprecated) */
25115 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID1_SERVICE_PROFILE_LOSSLESS_ROCE \
25117 /* Lossy RoCE CNP (deprecated) */
25118 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID1_SERVICE_PROFILE_LOSSY_ROCE_CNP \
25120 /* Lossless NIC (deprecated) */
25121 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID1_SERVICE_PROFILE_LOSSLESS_NIC \
25123 /* Set to 0xFF... (All Fs) if there is no service profile specified */
25124 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID1_SERVICE_PROFILE_UNKNOWN \
25126 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID1_SERVICE_PROFILE_LAST \
25127 HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID1_SERVICE_PROFILE_UNKNOWN
25129 * ID of CoS Queue 2.
25132 * # This ID can be used on any subsequent call to an hwrm command
25133 * that takes a queue id.
25134 * # IDs must always be queried by this command before any use
25135 * by the driver or software.
25136 * # The CoS queue index is obtained by applying modulo 10 to the
25137 * CoS queue ID. Valid CoS queue indexes are in the range of 0 to 7.
25138 * The CoS queue index is used to reference port statistics for the
25140 * # A value of 0xff indicates that the queue is not available.
25141 * # Available queues may not be in sequential order.
25144 /* This value specifies service profile kind for CoS queue */
25145 uint8_t queue_id2_service_profile;
25146 /* Lossy (best-effort) */
25147 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID2_SERVICE_PROFILE_LOSSY \
25150 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID2_SERVICE_PROFILE_LOSSLESS \
25152 /* Lossless RoCE (deprecated) */
25153 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID2_SERVICE_PROFILE_LOSSLESS_ROCE \
25155 /* Lossy RoCE CNP (deprecated) */
25156 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID2_SERVICE_PROFILE_LOSSY_ROCE_CNP \
25158 /* Lossless NIC (deprecated) */
25159 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID2_SERVICE_PROFILE_LOSSLESS_NIC \
25161 /* Set to 0xFF... (All Fs) if there is no service profile specified */
25162 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID2_SERVICE_PROFILE_UNKNOWN \
25164 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID2_SERVICE_PROFILE_LAST \
25165 HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID2_SERVICE_PROFILE_UNKNOWN
25167 * ID of CoS Queue 3.
25170 * # This ID can be used on any subsequent call to an hwrm command
25171 * that takes a queue id.
25172 * # IDs must always be queried by this command before any use
25173 * by the driver or software.
25174 * # The CoS queue index is obtained by applying modulo 10 to the
25175 * CoS queue ID. Valid CoS queue indexes are in the range of 0 to 7.
25176 * The CoS queue index is used to reference port statistics for the
25178 * # A value of 0xff indicates that the queue is not available.
25179 * # Available queues may not be in sequential order.
25182 /* This value specifies service profile kind for CoS queue */
25183 uint8_t queue_id3_service_profile;
25184 /* Lossy (best-effort) */
25185 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID3_SERVICE_PROFILE_LOSSY \
25188 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID3_SERVICE_PROFILE_LOSSLESS \
25190 /* Lossless RoCE (deprecated) */
25191 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID3_SERVICE_PROFILE_LOSSLESS_ROCE \
25193 /* Lossy RoCE CNP (deprecated) */
25194 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID3_SERVICE_PROFILE_LOSSY_ROCE_CNP \
25196 /* Lossless NIC (deprecated) */
25197 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID3_SERVICE_PROFILE_LOSSLESS_NIC \
25199 /* Set to 0xFF... (All Fs) if there is no service profile specified */
25200 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID3_SERVICE_PROFILE_UNKNOWN \
25202 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID3_SERVICE_PROFILE_LAST \
25203 HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID3_SERVICE_PROFILE_UNKNOWN
25205 * ID of CoS Queue 4.
25208 * # This ID can be used on any subsequent call to an hwrm command
25209 * that takes a queue id.
25210 * # IDs must always be queried by this command before any use
25211 * by the driver or software.
25212 * # The CoS queue index is obtained by applying modulo 10 to the
25213 * CoS queue ID. Valid CoS queue indexes are in the range of 0 to 7.
25214 * The CoS queue index is used to reference port statistics for the
25216 * # A value of 0xff indicates that the queue is not available.
25217 * # Available queues may not be in sequential order.
25220 /* This value specifies service profile kind for CoS queue */
25221 uint8_t queue_id4_service_profile;
25222 /* Lossy (best-effort) */
25223 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID4_SERVICE_PROFILE_LOSSY \
25226 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID4_SERVICE_PROFILE_LOSSLESS \
25228 /* Lossless RoCE (deprecated) */
25229 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID4_SERVICE_PROFILE_LOSSLESS_ROCE \
25231 /* Lossy RoCE CNP (deprecated) */
25232 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID4_SERVICE_PROFILE_LOSSY_ROCE_CNP \
25234 /* Lossless NIC (deprecated) */
25235 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID4_SERVICE_PROFILE_LOSSLESS_NIC \
25237 /* Set to 0xFF... (All Fs) if there is no service profile specified */
25238 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID4_SERVICE_PROFILE_UNKNOWN \
25240 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID4_SERVICE_PROFILE_LAST \
25241 HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID4_SERVICE_PROFILE_UNKNOWN
25243 * ID of CoS Queue 5.
25246 * # This ID can be used on any subsequent call to an hwrm command
25247 * that takes a queue id.
25248 * # IDs must always be queried by this command before any use
25249 * by the driver or software.
25250 * # The CoS queue index is obtained by applying modulo 10 to the
25251 * CoS queue ID. Valid CoS queue indexes are in the range of 0 to 7.
25252 * The CoS queue index is used to reference port statistics for the
25254 * # A value of 0xff indicates that the queue is not available.
25255 * # Available queues may not be in sequential order.
25258 /* This value specifies service profile kind for CoS queue */
25259 uint8_t queue_id5_service_profile;
25260 /* Lossy (best-effort) */
25261 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID5_SERVICE_PROFILE_LOSSY \
25264 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID5_SERVICE_PROFILE_LOSSLESS \
25266 /* Lossless RoCE (deprecated) */
25267 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID5_SERVICE_PROFILE_LOSSLESS_ROCE \
25269 /* Lossy RoCE CNP (deprecated) */
25270 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID5_SERVICE_PROFILE_LOSSY_ROCE_CNP \
25272 /* Lossless NIC (deprecated) */
25273 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID5_SERVICE_PROFILE_LOSSLESS_NIC \
25275 /* Set to 0xFF... (All Fs) if there is no service profile specified */
25276 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID5_SERVICE_PROFILE_UNKNOWN \
25278 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID5_SERVICE_PROFILE_LAST \
25279 HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID5_SERVICE_PROFILE_UNKNOWN
25281 * ID of CoS Queue 6.
25284 * # This ID can be used on any subsequent call to an hwrm command
25285 * that takes a queue id.
25286 * # IDs must always be queried by this command before any use
25287 * by the driver or software.
25288 * # The CoS queue index is obtained by applying modulo 10 to the
25289 * CoS queue ID. Valid CoS queue indexes are in the range of 0 to 7.
25290 * The CoS queue index is used to reference port statistics for the
25292 * # A value of 0xff indicates that the queue is not available.
25293 * # Available queues may not be in sequential order.
25296 /* This value specifies service profile kind for CoS queue */
25297 uint8_t queue_id6_service_profile;
25298 /* Lossy (best-effort) */
25299 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID6_SERVICE_PROFILE_LOSSY \
25302 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID6_SERVICE_PROFILE_LOSSLESS \
25304 /* Lossless RoCE (deprecated) */
25305 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID6_SERVICE_PROFILE_LOSSLESS_ROCE \
25307 /* Lossy RoCE CNP (deprecated) */
25308 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID6_SERVICE_PROFILE_LOSSY_ROCE_CNP \
25310 /* Lossless NIC (deprecated) */
25311 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID6_SERVICE_PROFILE_LOSSLESS_NIC \
25313 /* Set to 0xFF... (All Fs) if there is no service profile specified */
25314 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID6_SERVICE_PROFILE_UNKNOWN \
25316 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID6_SERVICE_PROFILE_LAST \
25317 HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID6_SERVICE_PROFILE_UNKNOWN
25319 * ID of CoS Queue 7.
25322 * # This ID can be used on any subsequent call to an hwrm command
25323 * that takes a queue id.
25324 * # IDs must always be queried by this command before any use
25325 * by the driver or software.
25326 * # The CoS queue index is obtained by applying modulo 10 to the
25327 * CoS queue ID. Valid CoS queue indexes are in the range of 0 to 7.
25328 * The CoS queue index is used to reference port statistics for the
25330 * # A value of 0xff indicates that the queue is not available.
25331 * # Available queues may not be in sequential order.
25334 /* This value specifies service profile kind for CoS queue */
25335 uint8_t queue_id7_service_profile;
25336 /* Lossy (best-effort) */
25337 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID7_SERVICE_PROFILE_LOSSY \
25340 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID7_SERVICE_PROFILE_LOSSLESS \
25342 /* Lossless RoCE (deprecated) */
25343 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID7_SERVICE_PROFILE_LOSSLESS_ROCE \
25345 /* Lossy RoCE CNP (deprecated) */
25346 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID7_SERVICE_PROFILE_LOSSY_ROCE_CNP \
25348 /* Lossless NIC (deprecated) */
25349 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID7_SERVICE_PROFILE_LOSSLESS_NIC \
25351 /* Set to 0xFF... (All Fs) if there is no service profile specified */
25352 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID7_SERVICE_PROFILE_UNKNOWN \
25354 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID7_SERVICE_PROFILE_LAST \
25355 HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID7_SERVICE_PROFILE_UNKNOWN
25357 * This value specifies traffic type for the service profile. We can
25358 * have a TC mapped to multiple traffic types. For example shared
25359 * CoS Q for CNP and NIC will have both cnp and nic bits set (0x6).
25360 * A value of zero is considered as invalid.
25362 uint8_t queue_id0_service_profile_type;
25363 /* Recommended to be used for RoCE traffic only. */
25364 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID0_SERVICE_PROFILE_TYPE_ROCE \
25366 /* Recommended to be used for NIC/L2 traffic only. */
25367 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID0_SERVICE_PROFILE_TYPE_NIC \
25369 /* Recommended to be used for CNP traffic only. */
25370 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID0_SERVICE_PROFILE_TYPE_CNP \
25373 * Up to 16 bytes of null padded ASCII string describing this queue.
25374 * The queue name includes a CoS queue index and, in some cases, text
25375 * that distinguishes the queue from other queues in the group.
25377 char qid0_name[16];
25378 /* Up to 16 bytes of null padded ASCII string describing this queue. */
25379 char qid1_name[16];
25380 /* Up to 16 bytes of null padded ASCII string describing this queue. */
25381 char qid2_name[16];
25382 /* Up to 16 bytes of null padded ASCII string describing this queue. */
25383 char qid3_name[16];
25384 /* Up to 16 bytes of null padded ASCII string describing this queue. */
25385 char qid4_name[16];
25386 /* Up to 16 bytes of null padded ASCII string describing this queue. */
25387 char qid5_name[16];
25388 /* Up to 16 bytes of null padded ASCII string describing this queue. */
25389 char qid6_name[16];
25390 /* Up to 16 bytes of null padded ASCII string describing this queue. */
25391 char qid7_name[16];
25393 * This value specifies traffic type for the service profile. We can
25394 * have a TC mapped to multiple traffic types. For example shared
25395 * CoS Q for CNP and NIC will have both cnp and nic bits set (0x6).
25396 * A value of zero is considered as invalid.
25398 uint8_t queue_id1_service_profile_type;
25399 /* Recommended to be used for RoCE traffic only. */
25400 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID1_SERVICE_PROFILE_TYPE_ROCE \
25402 /* Recommended to be used for NIC/L2 traffic only. */
25403 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID1_SERVICE_PROFILE_TYPE_NIC \
25405 /* Recommended to be used for CNP traffic only. */
25406 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID1_SERVICE_PROFILE_TYPE_CNP \
25409 * This value specifies traffic type for the service profile. We can
25410 * have a TC mapped to multiple traffic types. For example shared
25411 * CoS Q for CNP and NIC will have both cnp and nic bits set (0x6).
25412 * A value of zero is considered as invalid.
25414 uint8_t queue_id2_service_profile_type;
25415 /* Recommended to be used for RoCE traffic only. */
25416 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID2_SERVICE_PROFILE_TYPE_ROCE \
25418 /* Recommended to be used for NIC/L2 traffic only. */
25419 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID2_SERVICE_PROFILE_TYPE_NIC \
25421 /* Recommended to be used for CNP traffic only. */
25422 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID2_SERVICE_PROFILE_TYPE_CNP \
25425 * This value specifies traffic type for the service profile. We can
25426 * have a TC mapped to multiple traffic types. For example shared
25427 * CoS Q for CNP and NIC will have both cnp and nic bits set (0x6).
25428 * A value of zero is considered as invalid.
25430 uint8_t queue_id3_service_profile_type;
25431 /* Recommended to be used for RoCE traffic only. */
25432 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID3_SERVICE_PROFILE_TYPE_ROCE \
25434 /* Recommended to be used for NIC/L2 traffic only. */
25435 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID3_SERVICE_PROFILE_TYPE_NIC \
25437 /* Recommended to be used for CNP traffic only. */
25438 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID3_SERVICE_PROFILE_TYPE_CNP \
25441 * This value specifies traffic type for the service profile. We can
25442 * have a TC mapped to multiple traffic types. For example shared
25443 * CoS Q for CNP and NIC will have both cnp and nic bits set (0x6).
25444 * A value of zero is considered as invalid.
25446 uint8_t queue_id4_service_profile_type;
25447 /* Recommended to be used for RoCE traffic only. */
25448 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID4_SERVICE_PROFILE_TYPE_ROCE \
25450 /* Recommended to be used for NIC/L2 traffic only. */
25451 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID4_SERVICE_PROFILE_TYPE_NIC \
25453 /* Recommended to be used for CNP traffic only. */
25454 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID4_SERVICE_PROFILE_TYPE_CNP \
25457 * This value specifies traffic type for the service profile. We can
25458 * have a TC mapped to multiple traffic types. For example shared
25459 * CoS Q for CNP and NIC will have both cnp and nic bits set (0x6).
25460 * A value of zero is considered as invalid.
25462 uint8_t queue_id5_service_profile_type;
25463 /* Recommended to be used for RoCE traffic only. */
25464 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID5_SERVICE_PROFILE_TYPE_ROCE \
25466 /* Recommended to be used for NIC/L2 traffic only. */
25467 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID5_SERVICE_PROFILE_TYPE_NIC \
25469 /* Recommended to be used for CNP traffic only. */
25470 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID5_SERVICE_PROFILE_TYPE_CNP \
25473 * This value specifies traffic type for the service profile. We can
25474 * have a TC mapped to multiple traffic types. For example shared
25475 * CoS Q for CNP and NIC will have both cnp and nic bits set (0x6).
25476 * A value of zero is considered as invalid.
25478 uint8_t queue_id6_service_profile_type;
25479 /* Recommended to be used for RoCE traffic only. */
25480 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID6_SERVICE_PROFILE_TYPE_ROCE \
25482 /* Recommended to be used for NIC/L2 traffic only. */
25483 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID6_SERVICE_PROFILE_TYPE_NIC \
25485 /* Recommended to be used for CNP traffic only. */
25486 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID6_SERVICE_PROFILE_TYPE_CNP \
25489 * This value specifies traffic type for the service profile. We can
25490 * have a TC mapped to multiple traffic types. For example shared
25491 * CoS Q for CNP and NIC will have both cnp and nic bits set (0x6).
25492 * A value of zero is considered as invalid.
25494 uint8_t queue_id7_service_profile_type;
25495 /* Recommended to be used for RoCE traffic only. */
25496 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID7_SERVICE_PROFILE_TYPE_ROCE \
25498 /* Recommended to be used for NIC/L2 traffic only. */
25499 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID7_SERVICE_PROFILE_TYPE_NIC \
25501 /* Recommended to be used for CNP traffic only. */
25502 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID7_SERVICE_PROFILE_TYPE_CNP \
25505 * This field is used in Output records to indicate that the output
25506 * is completely written to RAM. This field should be read as '1'
25507 * to indicate that the output has been completely written.
25508 * When writing a command completion or response to an internal processor,
25509 * the order of writes has to be such that this field is written last.
25514 /*******************
25515 * hwrm_queue_qcfg *
25516 *******************/
25519 /* hwrm_queue_qcfg_input (size:192b/24B) */
25520 struct hwrm_queue_qcfg_input {
25521 /* The HWRM command request type. */
25524 * The completion ring to send the completion event on. This should
25525 * be the NQ ID returned from the `nq_alloc` HWRM command.
25527 uint16_t cmpl_ring;
25529 * The sequence ID is used by the driver for tracking multiple
25530 * commands. This ID is treated as opaque data by the firmware and
25531 * the value is returned in the `hwrm_resp_hdr` upon completion.
25535 * The target ID of the command:
25536 * * 0x0-0xFFF8 - The function ID
25537 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
25538 * * 0xFFFD - Reserved for user-space HWRM interface
25541 uint16_t target_id;
25543 * A physical address pointer pointing to a host buffer that the
25544 * command's response data will be written. This can be either a host
25545 * physical address (HPA) or a guest physical address (GPA) and must
25546 * point to a physically contiguous block of memory.
25548 uint64_t resp_addr;
25551 * Enumeration denoting the RX, TX type of the resource.
25552 * This enumeration is used for resources that are similar for both
25553 * TX and RX paths of the chip.
25555 #define HWRM_QUEUE_QCFG_INPUT_FLAGS_PATH UINT32_C(0x1)
25557 #define HWRM_QUEUE_QCFG_INPUT_FLAGS_PATH_TX UINT32_C(0x0)
25559 #define HWRM_QUEUE_QCFG_INPUT_FLAGS_PATH_RX UINT32_C(0x1)
25560 #define HWRM_QUEUE_QCFG_INPUT_FLAGS_PATH_LAST \
25561 HWRM_QUEUE_QCFG_INPUT_FLAGS_PATH_RX
25562 /* Queue ID of the queue. */
25566 /* hwrm_queue_qcfg_output (size:128b/16B) */
25567 struct hwrm_queue_qcfg_output {
25568 /* The specific error status for the command. */
25569 uint16_t error_code;
25570 /* The HWRM command request type. */
25572 /* The sequence ID from the original command. */
25574 /* The length of the response data in number of bytes. */
25577 * This value is the estimate packet length used in the
25580 uint32_t queue_len;
25581 /* This value is applicable to CoS queues only. */
25582 uint8_t service_profile;
25583 /* Lossy (best-effort) */
25584 #define HWRM_QUEUE_QCFG_OUTPUT_SERVICE_PROFILE_LOSSY UINT32_C(0x0)
25586 #define HWRM_QUEUE_QCFG_OUTPUT_SERVICE_PROFILE_LOSSLESS UINT32_C(0x1)
25587 /* Set to 0xFF... (All Fs) if there is no service profile specified */
25588 #define HWRM_QUEUE_QCFG_OUTPUT_SERVICE_PROFILE_UNKNOWN UINT32_C(0xff)
25589 #define HWRM_QUEUE_QCFG_OUTPUT_SERVICE_PROFILE_LAST \
25590 HWRM_QUEUE_QCFG_OUTPUT_SERVICE_PROFILE_UNKNOWN
25591 /* Information about queue configuration. */
25592 uint8_t queue_cfg_info;
25594 * If this flag is set to '1', then the queue is
25595 * configured asymmetrically on TX and RX sides.
25596 * If this flag is set to '0', then this queue is
25597 * configured symmetrically on TX and RX sides.
25599 #define HWRM_QUEUE_QCFG_OUTPUT_QUEUE_CFG_INFO_ASYM_CFG \
25603 * This field is used in Output records to indicate that the output
25604 * is completely written to RAM. This field should be read as '1'
25605 * to indicate that the output has been completely written.
25606 * When writing a command completion or response to an internal processor,
25607 * the order of writes has to be such that this field is written last.
25612 /******************
25614 ******************/
25617 /* hwrm_queue_cfg_input (size:320b/40B) */
25618 struct hwrm_queue_cfg_input {
25619 /* The HWRM command request type. */
25622 * The completion ring to send the completion event on. This should
25623 * be the NQ ID returned from the `nq_alloc` HWRM command.
25625 uint16_t cmpl_ring;
25627 * The sequence ID is used by the driver for tracking multiple
25628 * commands. This ID is treated as opaque data by the firmware and
25629 * the value is returned in the `hwrm_resp_hdr` upon completion.
25633 * The target ID of the command:
25634 * * 0x0-0xFFF8 - The function ID
25635 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
25636 * * 0xFFFD - Reserved for user-space HWRM interface
25639 uint16_t target_id;
25641 * A physical address pointer pointing to a host buffer that the
25642 * command's response data will be written. This can be either a host
25643 * physical address (HPA) or a guest physical address (GPA) and must
25644 * point to a physically contiguous block of memory.
25646 uint64_t resp_addr;
25649 * Enumeration denoting the RX, TX, or both directions applicable to the resource.
25650 * This enumeration is used for resources that are similar for both
25651 * TX and RX paths of the chip.
25653 #define HWRM_QUEUE_CFG_INPUT_FLAGS_PATH_MASK UINT32_C(0x3)
25654 #define HWRM_QUEUE_CFG_INPUT_FLAGS_PATH_SFT 0
25656 #define HWRM_QUEUE_CFG_INPUT_FLAGS_PATH_TX UINT32_C(0x0)
25658 #define HWRM_QUEUE_CFG_INPUT_FLAGS_PATH_RX UINT32_C(0x1)
25659 /* Bi-directional (Symmetrically applicable to TX and RX paths) */
25660 #define HWRM_QUEUE_CFG_INPUT_FLAGS_PATH_BIDIR UINT32_C(0x2)
25661 #define HWRM_QUEUE_CFG_INPUT_FLAGS_PATH_LAST \
25662 HWRM_QUEUE_CFG_INPUT_FLAGS_PATH_BIDIR
25665 * This bit must be '1' for the dflt_len field to be
25668 #define HWRM_QUEUE_CFG_INPUT_ENABLES_DFLT_LEN UINT32_C(0x1)
25670 * This bit must be '1' for the service_profile field to be
25673 #define HWRM_QUEUE_CFG_INPUT_ENABLES_SERVICE_PROFILE UINT32_C(0x2)
25674 /* Queue ID of queue that is to be configured by this function. */
25677 * This value is a the estimate packet length used in the
25679 * Set to 0xFF... (All Fs) to not adjust this value.
25682 /* This value is applicable to CoS queues only. */
25683 uint8_t service_profile;
25684 /* Lossy (best-effort) */
25685 #define HWRM_QUEUE_CFG_INPUT_SERVICE_PROFILE_LOSSY UINT32_C(0x0)
25687 #define HWRM_QUEUE_CFG_INPUT_SERVICE_PROFILE_LOSSLESS UINT32_C(0x1)
25688 /* Set to 0xFF... (All Fs) if there is no service profile specified */
25689 #define HWRM_QUEUE_CFG_INPUT_SERVICE_PROFILE_UNKNOWN UINT32_C(0xff)
25690 #define HWRM_QUEUE_CFG_INPUT_SERVICE_PROFILE_LAST \
25691 HWRM_QUEUE_CFG_INPUT_SERVICE_PROFILE_UNKNOWN
25692 uint8_t unused_0[7];
25695 /* hwrm_queue_cfg_output (size:128b/16B) */
25696 struct hwrm_queue_cfg_output {
25697 /* The specific error status for the command. */
25698 uint16_t error_code;
25699 /* The HWRM command request type. */
25701 /* The sequence ID from the original command. */
25703 /* The length of the response data in number of bytes. */
25705 uint8_t unused_0[7];
25707 * This field is used in Output records to indicate that the output
25708 * is completely written to RAM. This field should be read as '1'
25709 * to indicate that the output has been completely written.
25710 * When writing a command completion or response to an internal processor,
25711 * the order of writes has to be such that this field is written last.
25716 /*****************************
25717 * hwrm_queue_pfcenable_qcfg *
25718 *****************************/
25721 /* hwrm_queue_pfcenable_qcfg_input (size:192b/24B) */
25722 struct hwrm_queue_pfcenable_qcfg_input {
25723 /* The HWRM command request type. */
25726 * The completion ring to send the completion event on. This should
25727 * be the NQ ID returned from the `nq_alloc` HWRM command.
25729 uint16_t cmpl_ring;
25731 * The sequence ID is used by the driver for tracking multiple
25732 * commands. This ID is treated as opaque data by the firmware and
25733 * the value is returned in the `hwrm_resp_hdr` upon completion.
25737 * The target ID of the command:
25738 * * 0x0-0xFFF8 - The function ID
25739 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
25740 * * 0xFFFD - Reserved for user-space HWRM interface
25743 uint16_t target_id;
25745 * A physical address pointer pointing to a host buffer that the
25746 * command's response data will be written. This can be either a host
25747 * physical address (HPA) or a guest physical address (GPA) and must
25748 * point to a physically contiguous block of memory.
25750 uint64_t resp_addr;
25752 * Port ID of port for which the table is being configured.
25753 * The HWRM needs to check whether this function is allowed
25754 * to configure pri2cos mapping on this port.
25757 uint8_t unused_0[6];
25760 /* hwrm_queue_pfcenable_qcfg_output (size:128b/16B) */
25761 struct hwrm_queue_pfcenable_qcfg_output {
25762 /* The specific error status for the command. */
25763 uint16_t error_code;
25764 /* The HWRM command request type. */
25766 /* The sequence ID from the original command. */
25768 /* The length of the response data in number of bytes. */
25771 /* If set to 1, then PFC is enabled on PRI 0. */
25772 #define HWRM_QUEUE_PFCENABLE_QCFG_OUTPUT_FLAGS_PRI0_PFC_ENABLED \
25774 /* If set to 1, then PFC is enabled on PRI 1. */
25775 #define HWRM_QUEUE_PFCENABLE_QCFG_OUTPUT_FLAGS_PRI1_PFC_ENABLED \
25777 /* If set to 1, then PFC is enabled on PRI 2. */
25778 #define HWRM_QUEUE_PFCENABLE_QCFG_OUTPUT_FLAGS_PRI2_PFC_ENABLED \
25780 /* If set to 1, then PFC is enabled on PRI 3. */
25781 #define HWRM_QUEUE_PFCENABLE_QCFG_OUTPUT_FLAGS_PRI3_PFC_ENABLED \
25783 /* If set to 1, then PFC is enabled on PRI 4. */
25784 #define HWRM_QUEUE_PFCENABLE_QCFG_OUTPUT_FLAGS_PRI4_PFC_ENABLED \
25786 /* If set to 1, then PFC is enabled on PRI 5. */
25787 #define HWRM_QUEUE_PFCENABLE_QCFG_OUTPUT_FLAGS_PRI5_PFC_ENABLED \
25789 /* If set to 1, then PFC is enabled on PRI 6. */
25790 #define HWRM_QUEUE_PFCENABLE_QCFG_OUTPUT_FLAGS_PRI6_PFC_ENABLED \
25792 /* If set to 1, then PFC is enabled on PRI 7. */
25793 #define HWRM_QUEUE_PFCENABLE_QCFG_OUTPUT_FLAGS_PRI7_PFC_ENABLED \
25795 /* If set to 1, then PFC WatchDog is requested to be enabled on PRI0. */
25796 #define HWRM_QUEUE_PFCENABLE_QCFG_OUTPUT_FLAGS_PRI0_PFC_WATCHDOG_ENABLED \
25798 /* If set to 1, then PFC WatchDog is requested to be enabled on PRI1. */
25799 #define HWRM_QUEUE_PFCENABLE_QCFG_OUTPUT_FLAGS_PRI1_PFC_WATCHDOG_ENABLED \
25801 /* If set to 1, then PFC WatchDog is requested to be enabled on PRI2. */
25802 #define HWRM_QUEUE_PFCENABLE_QCFG_OUTPUT_FLAGS_PRI2_PFC_WATCHDOG_ENABLED \
25804 /* If set to 1, then PFC WatchDog is requested to be enabled on PRI3. */
25805 #define HWRM_QUEUE_PFCENABLE_QCFG_OUTPUT_FLAGS_PRI3_PFC_WATCHDOG_ENABLED \
25807 /* If set to 1, then PFC WatchDog is requested to be enabled on PRI4. */
25808 #define HWRM_QUEUE_PFCENABLE_QCFG_OUTPUT_FLAGS_PRI4_PFC_WATCHDOG_ENABLED \
25810 /* If set to 1, then PFC WatchDog is requested to be enabled on PRI5. */
25811 #define HWRM_QUEUE_PFCENABLE_QCFG_OUTPUT_FLAGS_PRI5_PFC_WATCHDOG_ENABLED \
25813 /* If set to 1, then PFC WatchDog is requested to be enabled on PRI6. */
25814 #define HWRM_QUEUE_PFCENABLE_QCFG_OUTPUT_FLAGS_PRI6_PFC_WATCHDOG_ENABLED \
25816 /* If set to 1, then PFC WatchDog is requested to be enabled on PRI7. */
25817 #define HWRM_QUEUE_PFCENABLE_QCFG_OUTPUT_FLAGS_PRI7_PFC_WATCHDOG_ENABLED \
25819 uint8_t unused_0[3];
25821 * This field is used in Output records to indicate that the output
25822 * is completely written to RAM. This field should be read as '1'
25823 * to indicate that the output has been completely written.
25824 * When writing a command completion or response to an internal processor,
25825 * the order of writes has to be such that this field is written last.
25830 /****************************
25831 * hwrm_queue_pfcenable_cfg *
25832 ****************************/
25835 /* hwrm_queue_pfcenable_cfg_input (size:192b/24B) */
25836 struct hwrm_queue_pfcenable_cfg_input {
25837 /* The HWRM command request type. */
25840 * The completion ring to send the completion event on. This should
25841 * be the NQ ID returned from the `nq_alloc` HWRM command.
25843 uint16_t cmpl_ring;
25845 * The sequence ID is used by the driver for tracking multiple
25846 * commands. This ID is treated as opaque data by the firmware and
25847 * the value is returned in the `hwrm_resp_hdr` upon completion.
25851 * The target ID of the command:
25852 * * 0x0-0xFFF8 - The function ID
25853 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
25854 * * 0xFFFD - Reserved for user-space HWRM interface
25857 uint16_t target_id;
25859 * A physical address pointer pointing to a host buffer that the
25860 * command's response data will be written. This can be either a host
25861 * physical address (HPA) or a guest physical address (GPA) and must
25862 * point to a physically contiguous block of memory.
25864 uint64_t resp_addr;
25866 /* If set to 1, then PFC is requested to be enabled on PRI 0. */
25867 #define HWRM_QUEUE_PFCENABLE_CFG_INPUT_FLAGS_PRI0_PFC_ENABLED \
25869 /* If set to 1, then PFC is requested to be enabled on PRI 1. */
25870 #define HWRM_QUEUE_PFCENABLE_CFG_INPUT_FLAGS_PRI1_PFC_ENABLED \
25872 /* If set to 1, then PFC is requested to be enabled on PRI 2. */
25873 #define HWRM_QUEUE_PFCENABLE_CFG_INPUT_FLAGS_PRI2_PFC_ENABLED \
25875 /* If set to 1, then PFC is requested to be enabled on PRI 3. */
25876 #define HWRM_QUEUE_PFCENABLE_CFG_INPUT_FLAGS_PRI3_PFC_ENABLED \
25878 /* If set to 1, then PFC is requested to be enabled on PRI 4. */
25879 #define HWRM_QUEUE_PFCENABLE_CFG_INPUT_FLAGS_PRI4_PFC_ENABLED \
25881 /* If set to 1, then PFC is requested to be enabled on PRI 5. */
25882 #define HWRM_QUEUE_PFCENABLE_CFG_INPUT_FLAGS_PRI5_PFC_ENABLED \
25884 /* If set to 1, then PFC is requested to be enabled on PRI 6. */
25885 #define HWRM_QUEUE_PFCENABLE_CFG_INPUT_FLAGS_PRI6_PFC_ENABLED \
25887 /* If set to 1, then PFC is requested to be enabled on PRI 7. */
25888 #define HWRM_QUEUE_PFCENABLE_CFG_INPUT_FLAGS_PRI7_PFC_ENABLED \
25890 /* If set to 1, then PFC WatchDog is requested to be enabled on PRI0. */
25891 #define HWRM_QUEUE_PFCENABLE_CFG_INPUT_FLAGS_PRI0_PFC_WATCHDOG_ENABLED \
25893 /* If set to 1, then PFC WatchDog is requested to be enabled on PRI1. */
25894 #define HWRM_QUEUE_PFCENABLE_CFG_INPUT_FLAGS_PRI1_PFC_WATCHDOG_ENABLED \
25896 /* If set to 1, then PFC WatchDog is requested to be enabled on PRI2. */
25897 #define HWRM_QUEUE_PFCENABLE_CFG_INPUT_FLAGS_PRI2_PFC_WATCHDOG_ENABLED \
25899 /* If set to 1, then PFC WatchDog is requested to be enabled on PRI3. */
25900 #define HWRM_QUEUE_PFCENABLE_CFG_INPUT_FLAGS_PRI3_PFC_WATCHDOG_ENABLED \
25902 /* If set to 1, then PFC WatchDog is requested to be enabled on PRI4. */
25903 #define HWRM_QUEUE_PFCENABLE_CFG_INPUT_FLAGS_PRI4_PFC_WATCHDOG_ENABLED \
25905 /* If set to 1, then PFC WatchDog is requested to be enabled on PRI5. */
25906 #define HWRM_QUEUE_PFCENABLE_CFG_INPUT_FLAGS_PRI5_PFC_WATCHDOG_ENABLED \
25908 /* If set to 1, then PFC WatchDog is requested to be enabled on PRI6. */
25909 #define HWRM_QUEUE_PFCENABLE_CFG_INPUT_FLAGS_PRI6_PFC_WATCHDOG_ENABLED \
25911 /* If set to 1, then PFC WatchDog is requested to be enabled on PRI7. */
25912 #define HWRM_QUEUE_PFCENABLE_CFG_INPUT_FLAGS_PRI7_PFC_WATCHDOG_ENABLED \
25915 * Port ID of port for which the table is being configured.
25916 * The HWRM needs to check whether this function is allowed
25917 * to configure pri2cos mapping on this port.
25920 uint8_t unused_0[2];
25923 /* hwrm_queue_pfcenable_cfg_output (size:128b/16B) */
25924 struct hwrm_queue_pfcenable_cfg_output {
25925 /* The specific error status for the command. */
25926 uint16_t error_code;
25927 /* The HWRM command request type. */
25929 /* The sequence ID from the original command. */
25931 /* The length of the response data in number of bytes. */
25933 uint8_t unused_0[7];
25935 * This field is used in Output records to indicate that the output
25936 * is completely written to RAM. This field should be read as '1'
25937 * to indicate that the output has been completely written.
25938 * When writing a command completion or response to an internal processor,
25939 * the order of writes has to be such that this field is written last.
25944 /***************************
25945 * hwrm_queue_pri2cos_qcfg *
25946 ***************************/
25949 /* hwrm_queue_pri2cos_qcfg_input (size:192b/24B) */
25950 struct hwrm_queue_pri2cos_qcfg_input {
25951 /* The HWRM command request type. */
25954 * The completion ring to send the completion event on. This should
25955 * be the NQ ID returned from the `nq_alloc` HWRM command.
25957 uint16_t cmpl_ring;
25959 * The sequence ID is used by the driver for tracking multiple
25960 * commands. This ID is treated as opaque data by the firmware and
25961 * the value is returned in the `hwrm_resp_hdr` upon completion.
25965 * The target ID of the command:
25966 * * 0x0-0xFFF8 - The function ID
25967 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
25968 * * 0xFFFD - Reserved for user-space HWRM interface
25971 uint16_t target_id;
25973 * A physical address pointer pointing to a host buffer that the
25974 * command's response data will be written. This can be either a host
25975 * physical address (HPA) or a guest physical address (GPA) and must
25976 * point to a physically contiguous block of memory.
25978 uint64_t resp_addr;
25981 * Enumeration denoting the RX, TX type of the resource.
25982 * This enumeration is used for resources that are similar for both
25983 * TX and RX paths of the chip.
25985 #define HWRM_QUEUE_PRI2COS_QCFG_INPUT_FLAGS_PATH UINT32_C(0x1)
25987 #define HWRM_QUEUE_PRI2COS_QCFG_INPUT_FLAGS_PATH_TX UINT32_C(0x0)
25989 #define HWRM_QUEUE_PRI2COS_QCFG_INPUT_FLAGS_PATH_RX UINT32_C(0x1)
25990 #define HWRM_QUEUE_PRI2COS_QCFG_INPUT_FLAGS_PATH_LAST \
25991 HWRM_QUEUE_PRI2COS_QCFG_INPUT_FLAGS_PATH_RX
25993 * When this bit is set to '0', the query is
25994 * for PRI from tunnel headers.
25995 * When this bit is set to '1', the query is
25996 * for PRI from inner packet headers.
25998 #define HWRM_QUEUE_PRI2COS_QCFG_INPUT_FLAGS_IVLAN UINT32_C(0x2)
26000 * Port ID of port for which the table is being configured.
26001 * The HWRM needs to check whether this function is allowed
26002 * to configure pri2cos mapping on this port.
26005 uint8_t unused_0[3];
26008 /* hwrm_queue_pri2cos_qcfg_output (size:192b/24B) */
26009 struct hwrm_queue_pri2cos_qcfg_output {
26010 /* The specific error status for the command. */
26011 uint16_t error_code;
26012 /* The HWRM command request type. */
26014 /* The sequence ID from the original command. */
26016 /* The length of the response data in number of bytes. */
26019 * CoS Queue assigned to priority 0. This value can only
26020 * be changed before traffic has started.
26021 * A value of 0xff indicates that no CoS queue is assigned to the
26022 * specified priority.
26024 uint8_t pri0_cos_queue_id;
26026 * CoS Queue assigned to priority 1. This value can only
26027 * be changed before traffic has started.
26028 * A value of 0xff indicates that no CoS queue is assigned to the
26029 * specified priority.
26031 uint8_t pri1_cos_queue_id;
26033 * CoS Queue assigned to priority 2. This value can only
26034 * be changed before traffic has started.
26035 * A value of 0xff indicates that no CoS queue is assigned to the
26036 * specified priority.
26038 uint8_t pri2_cos_queue_id;
26040 * CoS Queue assigned to priority 3. This value can only
26041 * be changed before traffic has started.
26042 * A value of 0xff indicates that no CoS queue is assigned to the
26043 * specified priority.
26045 uint8_t pri3_cos_queue_id;
26047 * CoS Queue assigned to priority 4. This value can only
26048 * be changed before traffic has started.
26049 * A value of 0xff indicates that no CoS queue is assigned to the
26050 * specified priority.
26052 uint8_t pri4_cos_queue_id;
26054 * CoS Queue assigned to priority 5. This value can only
26055 * be changed before traffic has started.
26056 * A value of 0xff indicates that no CoS queue is assigned to the
26057 * specified priority.
26059 uint8_t pri5_cos_queue_id;
26061 * CoS Queue assigned to priority 6. This value can only
26062 * be changed before traffic has started.
26063 * A value of 0xff indicates that no CoS queue is assigned to the
26064 * specified priority.
26066 uint8_t pri6_cos_queue_id;
26068 * CoS Queue assigned to priority 7. This value can only
26069 * be changed before traffic has started.
26070 * A value of 0xff indicates that no CoS queue is assigned to the
26071 * specified priority.
26073 uint8_t pri7_cos_queue_id;
26074 /* Information about queue configuration. */
26075 uint8_t queue_cfg_info;
26077 * If this flag is set to '1', then the PRI to CoS
26078 * configuration is asymmetric on TX and RX sides.
26079 * If this flag is set to '0', then PRI to CoS configuration
26080 * is symmetric on TX and RX sides.
26082 #define HWRM_QUEUE_PRI2COS_QCFG_OUTPUT_QUEUE_CFG_INFO_ASYM_CFG \
26084 uint8_t unused_0[6];
26086 * This field is used in Output records to indicate that the output
26087 * is completely written to RAM. This field should be read as '1'
26088 * to indicate that the output has been completely written.
26089 * When writing a command completion or response to an internal processor,
26090 * the order of writes has to be such that this field is written last.
26095 /**************************
26096 * hwrm_queue_pri2cos_cfg *
26097 **************************/
26100 /* hwrm_queue_pri2cos_cfg_input (size:320b/40B) */
26101 struct hwrm_queue_pri2cos_cfg_input {
26102 /* The HWRM command request type. */
26105 * The completion ring to send the completion event on. This should
26106 * be the NQ ID returned from the `nq_alloc` HWRM command.
26108 uint16_t cmpl_ring;
26110 * The sequence ID is used by the driver for tracking multiple
26111 * commands. This ID is treated as opaque data by the firmware and
26112 * the value is returned in the `hwrm_resp_hdr` upon completion.
26116 * The target ID of the command:
26117 * * 0x0-0xFFF8 - The function ID
26118 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
26119 * * 0xFFFD - Reserved for user-space HWRM interface
26122 uint16_t target_id;
26124 * A physical address pointer pointing to a host buffer that the
26125 * command's response data will be written. This can be either a host
26126 * physical address (HPA) or a guest physical address (GPA) and must
26127 * point to a physically contiguous block of memory.
26129 uint64_t resp_addr;
26132 * Enumeration denoting the RX, TX, or both directions applicable to the resource.
26133 * This enumeration is used for resources that are similar for both
26134 * TX and RX paths of the chip.
26136 #define HWRM_QUEUE_PRI2COS_CFG_INPUT_FLAGS_PATH_MASK UINT32_C(0x3)
26137 #define HWRM_QUEUE_PRI2COS_CFG_INPUT_FLAGS_PATH_SFT 0
26139 #define HWRM_QUEUE_PRI2COS_CFG_INPUT_FLAGS_PATH_TX UINT32_C(0x0)
26141 #define HWRM_QUEUE_PRI2COS_CFG_INPUT_FLAGS_PATH_RX UINT32_C(0x1)
26142 /* Bi-directional (Symmetrically applicable to TX and RX paths) */
26143 #define HWRM_QUEUE_PRI2COS_CFG_INPUT_FLAGS_PATH_BIDIR UINT32_C(0x2)
26144 #define HWRM_QUEUE_PRI2COS_CFG_INPUT_FLAGS_PATH_LAST \
26145 HWRM_QUEUE_PRI2COS_CFG_INPUT_FLAGS_PATH_BIDIR
26147 * When this bit is set to '0', the mapping is requested
26148 * for PRI from tunnel headers.
26149 * When this bit is set to '1', the mapping is requested
26150 * for PRI from inner packet headers.
26152 #define HWRM_QUEUE_PRI2COS_CFG_INPUT_FLAGS_IVLAN UINT32_C(0x4)
26155 * This bit must be '1' for the pri0_cos_queue_id field to be
26158 #define HWRM_QUEUE_PRI2COS_CFG_INPUT_ENABLES_PRI0_COS_QUEUE_ID \
26161 * This bit must be '1' for the pri1_cos_queue_id field to be
26164 #define HWRM_QUEUE_PRI2COS_CFG_INPUT_ENABLES_PRI1_COS_QUEUE_ID \
26167 * This bit must be '1' for the pri2_cos_queue_id field to be
26170 #define HWRM_QUEUE_PRI2COS_CFG_INPUT_ENABLES_PRI2_COS_QUEUE_ID \
26173 * This bit must be '1' for the pri3_cos_queue_id field to be
26176 #define HWRM_QUEUE_PRI2COS_CFG_INPUT_ENABLES_PRI3_COS_QUEUE_ID \
26179 * This bit must be '1' for the pri4_cos_queue_id field to be
26182 #define HWRM_QUEUE_PRI2COS_CFG_INPUT_ENABLES_PRI4_COS_QUEUE_ID \
26185 * This bit must be '1' for the pri5_cos_queue_id field to be
26188 #define HWRM_QUEUE_PRI2COS_CFG_INPUT_ENABLES_PRI5_COS_QUEUE_ID \
26191 * This bit must be '1' for the pri6_cos_queue_id field to be
26194 #define HWRM_QUEUE_PRI2COS_CFG_INPUT_ENABLES_PRI6_COS_QUEUE_ID \
26197 * This bit must be '1' for the pri7_cos_queue_id field to be
26200 #define HWRM_QUEUE_PRI2COS_CFG_INPUT_ENABLES_PRI7_COS_QUEUE_ID \
26203 * Port ID of port for which the table is being configured.
26204 * The HWRM needs to check whether this function is allowed
26205 * to configure pri2cos mapping on this port.
26209 * CoS Queue assigned to priority 0. This value can only
26210 * be changed before traffic has started.
26212 uint8_t pri0_cos_queue_id;
26214 * CoS Queue assigned to priority 1. This value can only
26215 * be changed before traffic has started.
26217 uint8_t pri1_cos_queue_id;
26219 * CoS Queue assigned to priority 2 This value can only
26220 * be changed before traffic has started.
26222 uint8_t pri2_cos_queue_id;
26224 * CoS Queue assigned to priority 3. This value can only
26225 * be changed before traffic has started.
26227 uint8_t pri3_cos_queue_id;
26229 * CoS Queue assigned to priority 4. This value can only
26230 * be changed before traffic has started.
26232 uint8_t pri4_cos_queue_id;
26234 * CoS Queue assigned to priority 5. This value can only
26235 * be changed before traffic has started.
26237 uint8_t pri5_cos_queue_id;
26239 * CoS Queue assigned to priority 6. This value can only
26240 * be changed before traffic has started.
26242 uint8_t pri6_cos_queue_id;
26244 * CoS Queue assigned to priority 7. This value can only
26245 * be changed before traffic has started.
26247 uint8_t pri7_cos_queue_id;
26248 uint8_t unused_0[7];
26251 /* hwrm_queue_pri2cos_cfg_output (size:128b/16B) */
26252 struct hwrm_queue_pri2cos_cfg_output {
26253 /* The specific error status for the command. */
26254 uint16_t error_code;
26255 /* The HWRM command request type. */
26257 /* The sequence ID from the original command. */
26259 /* The length of the response data in number of bytes. */
26261 uint8_t unused_0[7];
26263 * This field is used in Output records to indicate that the output
26264 * is completely written to RAM. This field should be read as '1'
26265 * to indicate that the output has been completely written.
26266 * When writing a command completion or response to an internal processor,
26267 * the order of writes has to be such that this field is written last.
26272 /**************************
26273 * hwrm_queue_cos2bw_qcfg *
26274 **************************/
26277 /* hwrm_queue_cos2bw_qcfg_input (size:192b/24B) */
26278 struct hwrm_queue_cos2bw_qcfg_input {
26279 /* The HWRM command request type. */
26282 * The completion ring to send the completion event on. This should
26283 * be the NQ ID returned from the `nq_alloc` HWRM command.
26285 uint16_t cmpl_ring;
26287 * The sequence ID is used by the driver for tracking multiple
26288 * commands. This ID is treated as opaque data by the firmware and
26289 * the value is returned in the `hwrm_resp_hdr` upon completion.
26293 * The target ID of the command:
26294 * * 0x0-0xFFF8 - The function ID
26295 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
26296 * * 0xFFFD - Reserved for user-space HWRM interface
26299 uint16_t target_id;
26301 * A physical address pointer pointing to a host buffer that the
26302 * command's response data will be written. This can be either a host
26303 * physical address (HPA) or a guest physical address (GPA) and must
26304 * point to a physically contiguous block of memory.
26306 uint64_t resp_addr;
26308 * Port ID of port for which the table is being configured.
26309 * The HWRM needs to check whether this function is allowed
26310 * to configure TC BW assignment on this port.
26313 uint8_t unused_0[6];
26316 /* hwrm_queue_cos2bw_qcfg_output (size:896b/112B) */
26317 struct hwrm_queue_cos2bw_qcfg_output {
26318 /* The specific error status for the command. */
26319 uint16_t error_code;
26320 /* The HWRM command request type. */
26322 /* The sequence ID from the original command. */
26324 /* The length of the response data in number of bytes. */
26326 /* ID of CoS Queue 0. */
26331 * Minimum BW allocated to CoS Queue.
26332 * The HWRM will translate this value into byte counter and
26333 * time interval used for this COS inside the device.
26335 uint32_t queue_id0_min_bw;
26336 /* The bandwidth value. */
26337 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MIN_BW_BW_VALUE_MASK \
26338 UINT32_C(0xfffffff)
26339 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MIN_BW_BW_VALUE_SFT \
26341 /* The granularity of the value (bits or bytes). */
26342 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MIN_BW_SCALE \
26343 UINT32_C(0x10000000)
26344 /* Value is in bits. */
26345 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MIN_BW_SCALE_BITS \
26346 (UINT32_C(0x0) << 28)
26347 /* Value is in bytes. */
26348 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MIN_BW_SCALE_BYTES \
26349 (UINT32_C(0x1) << 28)
26350 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MIN_BW_SCALE_LAST \
26351 HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MIN_BW_SCALE_BYTES
26352 /* bw_value_unit is 3 b */
26353 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_MASK \
26354 UINT32_C(0xe0000000)
26355 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_SFT \
26357 /* Value is in Mb or MB (base 10). */
26358 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_MEGA \
26359 (UINT32_C(0x0) << 29)
26360 /* Value is in Kb or KB (base 10). */
26361 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_KILO \
26362 (UINT32_C(0x2) << 29)
26363 /* Value is in bits or bytes. */
26364 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_BASE \
26365 (UINT32_C(0x4) << 29)
26366 /* Value is in Gb or GB (base 10). */
26367 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_GIGA \
26368 (UINT32_C(0x6) << 29)
26369 /* Value is in 1/100th of a percentage of total bandwidth. */
26370 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 \
26371 (UINT32_C(0x1) << 29)
26373 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_INVALID \
26374 (UINT32_C(0x7) << 29)
26375 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_LAST \
26376 HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_INVALID
26378 * Maximum BW allocated to CoS Queue.
26379 * The HWRM will translate this value into byte counter and
26380 * time interval used for this COS inside the device.
26382 uint32_t queue_id0_max_bw;
26383 /* The bandwidth value. */
26384 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MAX_BW_BW_VALUE_MASK \
26385 UINT32_C(0xfffffff)
26386 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MAX_BW_BW_VALUE_SFT \
26388 /* The granularity of the value (bits or bytes). */
26389 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MAX_BW_SCALE \
26390 UINT32_C(0x10000000)
26391 /* Value is in bits. */
26392 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MAX_BW_SCALE_BITS \
26393 (UINT32_C(0x0) << 28)
26394 /* Value is in bytes. */
26395 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MAX_BW_SCALE_BYTES \
26396 (UINT32_C(0x1) << 28)
26397 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MAX_BW_SCALE_LAST \
26398 HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MAX_BW_SCALE_BYTES
26399 /* bw_value_unit is 3 b */
26400 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_MASK \
26401 UINT32_C(0xe0000000)
26402 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_SFT \
26404 /* Value is in Mb or MB (base 10). */
26405 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_MEGA \
26406 (UINT32_C(0x0) << 29)
26407 /* Value is in Kb or KB (base 10). */
26408 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_KILO \
26409 (UINT32_C(0x2) << 29)
26410 /* Value is in bits or bytes. */
26411 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_BASE \
26412 (UINT32_C(0x4) << 29)
26413 /* Value is in Gb or GB (base 10). */
26414 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_GIGA \
26415 (UINT32_C(0x6) << 29)
26416 /* Value is in 1/100th of a percentage of total bandwidth. */
26417 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 \
26418 (UINT32_C(0x1) << 29)
26420 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_INVALID \
26421 (UINT32_C(0x7) << 29)
26422 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_LAST \
26423 HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_INVALID
26424 /* Transmission Selection Algorithm (TSA) for CoS Queue. */
26425 uint8_t queue_id0_tsa_assign;
26426 /* Strict Priority */
26427 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_TSA_ASSIGN_SP \
26429 /* Enhanced Transmission Selection */
26430 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_TSA_ASSIGN_ETS \
26433 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_TSA_ASSIGN_RESERVED_FIRST \
26436 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_TSA_ASSIGN_RESERVED_LAST \
26439 * Priority level for strict priority. Valid only when the
26440 * tsa_assign is 0 - Strict Priority (SP)
26441 * 0..7 - Valid values.
26442 * 8..255 - Reserved.
26444 uint8_t queue_id0_pri_lvl;
26446 * Weight used to allocate remaining BW for this COS after
26447 * servicing guaranteed bandwidths for all COS.
26449 uint8_t queue_id0_bw_weight;
26450 /* ID of CoS Queue 1. */
26453 * Minimum BW allocated to CoS Queue.
26454 * The HWRM will translate this value into byte counter and
26455 * time interval used for this COS inside the device.
26457 uint32_t queue_id1_min_bw;
26458 /* The bandwidth value. */
26459 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MIN_BW_BW_VALUE_MASK \
26460 UINT32_C(0xfffffff)
26461 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MIN_BW_BW_VALUE_SFT \
26463 /* The granularity of the value (bits or bytes). */
26464 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MIN_BW_SCALE \
26465 UINT32_C(0x10000000)
26466 /* Value is in bits. */
26467 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MIN_BW_SCALE_BITS \
26468 (UINT32_C(0x0) << 28)
26469 /* Value is in bytes. */
26470 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MIN_BW_SCALE_BYTES \
26471 (UINT32_C(0x1) << 28)
26472 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MIN_BW_SCALE_LAST \
26473 HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MIN_BW_SCALE_BYTES
26474 /* bw_value_unit is 3 b */
26475 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_MASK \
26476 UINT32_C(0xe0000000)
26477 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_SFT \
26479 /* Value is in Mb or MB (base 10). */
26480 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_MEGA \
26481 (UINT32_C(0x0) << 29)
26482 /* Value is in Kb or KB (base 10). */
26483 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_KILO \
26484 (UINT32_C(0x2) << 29)
26485 /* Value is in bits or bytes. */
26486 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_BASE \
26487 (UINT32_C(0x4) << 29)
26488 /* Value is in Gb or GB (base 10). */
26489 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_GIGA \
26490 (UINT32_C(0x6) << 29)
26491 /* Value is in 1/100th of a percentage of total bandwidth. */
26492 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 \
26493 (UINT32_C(0x1) << 29)
26495 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_INVALID \
26496 (UINT32_C(0x7) << 29)
26497 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_LAST \
26498 HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_INVALID
26500 * Maximum BW allocated to CoS queue.
26501 * The HWRM will translate this value into byte counter and
26502 * time interval used for this COS inside the device.
26504 uint32_t queue_id1_max_bw;
26505 /* The bandwidth value. */
26506 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MAX_BW_BW_VALUE_MASK \
26507 UINT32_C(0xfffffff)
26508 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MAX_BW_BW_VALUE_SFT \
26510 /* The granularity of the value (bits or bytes). */
26511 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MAX_BW_SCALE \
26512 UINT32_C(0x10000000)
26513 /* Value is in bits. */
26514 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MAX_BW_SCALE_BITS \
26515 (UINT32_C(0x0) << 28)
26516 /* Value is in bytes. */
26517 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MAX_BW_SCALE_BYTES \
26518 (UINT32_C(0x1) << 28)
26519 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MAX_BW_SCALE_LAST \
26520 HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MAX_BW_SCALE_BYTES
26521 /* bw_value_unit is 3 b */
26522 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_MASK \
26523 UINT32_C(0xe0000000)
26524 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_SFT \
26526 /* Value is in Mb or MB (base 10). */
26527 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_MEGA \
26528 (UINT32_C(0x0) << 29)
26529 /* Value is in Kb or KB (base 10). */
26530 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_KILO \
26531 (UINT32_C(0x2) << 29)
26532 /* Value is in bits or bytes. */
26533 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_BASE \
26534 (UINT32_C(0x4) << 29)
26535 /* Value is in Gb or GB (base 10). */
26536 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_GIGA \
26537 (UINT32_C(0x6) << 29)
26538 /* Value is in 1/100th of a percentage of total bandwidth. */
26539 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 \
26540 (UINT32_C(0x1) << 29)
26542 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_INVALID \
26543 (UINT32_C(0x7) << 29)
26544 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_LAST \
26545 HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_INVALID
26546 /* Transmission Selection Algorithm (TSA) for CoS Queue. */
26547 uint8_t queue_id1_tsa_assign;
26548 /* Strict Priority */
26549 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_TSA_ASSIGN_SP \
26551 /* Enhanced Transmission Selection */
26552 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_TSA_ASSIGN_ETS \
26555 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_TSA_ASSIGN_RESERVED_FIRST \
26558 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_TSA_ASSIGN_RESERVED_LAST \
26561 * Priority level for strict priority. Valid only when the
26562 * tsa_assign is 0 - Strict Priority (SP)
26563 * 0..7 - Valid values.
26564 * 8..255 - Reserved.
26566 uint8_t queue_id1_pri_lvl;
26568 * Weight used to allocate remaining BW for this COS after
26569 * servicing guaranteed bandwidths for all COS.
26571 uint8_t queue_id1_bw_weight;
26572 /* ID of CoS Queue 2. */
26575 * Minimum BW allocated to CoS Queue.
26576 * The HWRM will translate this value into byte counter and
26577 * time interval used for this COS inside the device.
26579 uint32_t queue_id2_min_bw;
26580 /* The bandwidth value. */
26581 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MIN_BW_BW_VALUE_MASK \
26582 UINT32_C(0xfffffff)
26583 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MIN_BW_BW_VALUE_SFT \
26585 /* The granularity of the value (bits or bytes). */
26586 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MIN_BW_SCALE \
26587 UINT32_C(0x10000000)
26588 /* Value is in bits. */
26589 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MIN_BW_SCALE_BITS \
26590 (UINT32_C(0x0) << 28)
26591 /* Value is in bytes. */
26592 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MIN_BW_SCALE_BYTES \
26593 (UINT32_C(0x1) << 28)
26594 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MIN_BW_SCALE_LAST \
26595 HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MIN_BW_SCALE_BYTES
26596 /* bw_value_unit is 3 b */
26597 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_MASK \
26598 UINT32_C(0xe0000000)
26599 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_SFT \
26601 /* Value is in Mb or MB (base 10). */
26602 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_MEGA \
26603 (UINT32_C(0x0) << 29)
26604 /* Value is in Kb or KB (base 10). */
26605 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_KILO \
26606 (UINT32_C(0x2) << 29)
26607 /* Value is in bits or bytes. */
26608 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_BASE \
26609 (UINT32_C(0x4) << 29)
26610 /* Value is in Gb or GB (base 10). */
26611 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_GIGA \
26612 (UINT32_C(0x6) << 29)
26613 /* Value is in 1/100th of a percentage of total bandwidth. */
26614 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 \
26615 (UINT32_C(0x1) << 29)
26617 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_INVALID \
26618 (UINT32_C(0x7) << 29)
26619 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_LAST \
26620 HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_INVALID
26622 * Maximum BW allocated to CoS queue.
26623 * The HWRM will translate this value into byte counter and
26624 * time interval used for this COS inside the device.
26626 uint32_t queue_id2_max_bw;
26627 /* The bandwidth value. */
26628 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MAX_BW_BW_VALUE_MASK \
26629 UINT32_C(0xfffffff)
26630 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MAX_BW_BW_VALUE_SFT \
26632 /* The granularity of the value (bits or bytes). */
26633 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MAX_BW_SCALE \
26634 UINT32_C(0x10000000)
26635 /* Value is in bits. */
26636 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MAX_BW_SCALE_BITS \
26637 (UINT32_C(0x0) << 28)
26638 /* Value is in bytes. */
26639 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MAX_BW_SCALE_BYTES \
26640 (UINT32_C(0x1) << 28)
26641 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MAX_BW_SCALE_LAST \
26642 HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MAX_BW_SCALE_BYTES
26643 /* bw_value_unit is 3 b */
26644 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_MASK \
26645 UINT32_C(0xe0000000)
26646 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_SFT \
26648 /* Value is in Mb or MB (base 10). */
26649 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_MEGA \
26650 (UINT32_C(0x0) << 29)
26651 /* Value is in Kb or KB (base 10). */
26652 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_KILO \
26653 (UINT32_C(0x2) << 29)
26654 /* Value is in bits or bytes. */
26655 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_BASE \
26656 (UINT32_C(0x4) << 29)
26657 /* Value is in Gb or GB (base 10). */
26658 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_GIGA \
26659 (UINT32_C(0x6) << 29)
26660 /* Value is in 1/100th of a percentage of total bandwidth. */
26661 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 \
26662 (UINT32_C(0x1) << 29)
26664 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_INVALID \
26665 (UINT32_C(0x7) << 29)
26666 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_LAST \
26667 HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_INVALID
26668 /* Transmission Selection Algorithm (TSA) for CoS Queue. */
26669 uint8_t queue_id2_tsa_assign;
26670 /* Strict Priority */
26671 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_TSA_ASSIGN_SP \
26673 /* Enhanced Transmission Selection */
26674 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_TSA_ASSIGN_ETS \
26677 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_TSA_ASSIGN_RESERVED_FIRST \
26680 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_TSA_ASSIGN_RESERVED_LAST \
26683 * Priority level for strict priority. Valid only when the
26684 * tsa_assign is 0 - Strict Priority (SP)
26685 * 0..7 - Valid values.
26686 * 8..255 - Reserved.
26688 uint8_t queue_id2_pri_lvl;
26690 * Weight used to allocate remaining BW for this COS after
26691 * servicing guaranteed bandwidths for all COS.
26693 uint8_t queue_id2_bw_weight;
26694 /* ID of CoS Queue 3. */
26697 * Minimum BW allocated to CoS Queue.
26698 * The HWRM will translate this value into byte counter and
26699 * time interval used for this COS inside the device.
26701 uint32_t queue_id3_min_bw;
26702 /* The bandwidth value. */
26703 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MIN_BW_BW_VALUE_MASK \
26704 UINT32_C(0xfffffff)
26705 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MIN_BW_BW_VALUE_SFT \
26707 /* The granularity of the value (bits or bytes). */
26708 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MIN_BW_SCALE \
26709 UINT32_C(0x10000000)
26710 /* Value is in bits. */
26711 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MIN_BW_SCALE_BITS \
26712 (UINT32_C(0x0) << 28)
26713 /* Value is in bytes. */
26714 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MIN_BW_SCALE_BYTES \
26715 (UINT32_C(0x1) << 28)
26716 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MIN_BW_SCALE_LAST \
26717 HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MIN_BW_SCALE_BYTES
26718 /* bw_value_unit is 3 b */
26719 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_MASK \
26720 UINT32_C(0xe0000000)
26721 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_SFT \
26723 /* Value is in Mb or MB (base 10). */
26724 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_MEGA \
26725 (UINT32_C(0x0) << 29)
26726 /* Value is in Kb or KB (base 10). */
26727 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_KILO \
26728 (UINT32_C(0x2) << 29)
26729 /* Value is in bits or bytes. */
26730 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_BASE \
26731 (UINT32_C(0x4) << 29)
26732 /* Value is in Gb or GB (base 10). */
26733 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_GIGA \
26734 (UINT32_C(0x6) << 29)
26735 /* Value is in 1/100th of a percentage of total bandwidth. */
26736 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 \
26737 (UINT32_C(0x1) << 29)
26739 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_INVALID \
26740 (UINT32_C(0x7) << 29)
26741 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_LAST \
26742 HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_INVALID
26744 * Maximum BW allocated to CoS queue.
26745 * The HWRM will translate this value into byte counter and
26746 * time interval used for this COS inside the device.
26748 uint32_t queue_id3_max_bw;
26749 /* The bandwidth value. */
26750 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MAX_BW_BW_VALUE_MASK \
26751 UINT32_C(0xfffffff)
26752 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MAX_BW_BW_VALUE_SFT \
26754 /* The granularity of the value (bits or bytes). */
26755 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MAX_BW_SCALE \
26756 UINT32_C(0x10000000)
26757 /* Value is in bits. */
26758 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MAX_BW_SCALE_BITS \
26759 (UINT32_C(0x0) << 28)
26760 /* Value is in bytes. */
26761 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MAX_BW_SCALE_BYTES \
26762 (UINT32_C(0x1) << 28)
26763 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MAX_BW_SCALE_LAST \
26764 HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MAX_BW_SCALE_BYTES
26765 /* bw_value_unit is 3 b */
26766 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_MASK \
26767 UINT32_C(0xe0000000)
26768 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_SFT \
26770 /* Value is in Mb or MB (base 10). */
26771 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_MEGA \
26772 (UINT32_C(0x0) << 29)
26773 /* Value is in Kb or KB (base 10). */
26774 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_KILO \
26775 (UINT32_C(0x2) << 29)
26776 /* Value is in bits or bytes. */
26777 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_BASE \
26778 (UINT32_C(0x4) << 29)
26779 /* Value is in Gb or GB (base 10). */
26780 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_GIGA \
26781 (UINT32_C(0x6) << 29)
26782 /* Value is in 1/100th of a percentage of total bandwidth. */
26783 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 \
26784 (UINT32_C(0x1) << 29)
26786 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_INVALID \
26787 (UINT32_C(0x7) << 29)
26788 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_LAST \
26789 HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_INVALID
26790 /* Transmission Selection Algorithm (TSA) for CoS Queue. */
26791 uint8_t queue_id3_tsa_assign;
26792 /* Strict Priority */
26793 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_TSA_ASSIGN_SP \
26795 /* Enhanced Transmission Selection */
26796 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_TSA_ASSIGN_ETS \
26799 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_TSA_ASSIGN_RESERVED_FIRST \
26802 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_TSA_ASSIGN_RESERVED_LAST \
26805 * Priority level for strict priority. Valid only when the
26806 * tsa_assign is 0 - Strict Priority (SP)
26807 * 0..7 - Valid values.
26808 * 8..255 - Reserved.
26810 uint8_t queue_id3_pri_lvl;
26812 * Weight used to allocate remaining BW for this COS after
26813 * servicing guaranteed bandwidths for all COS.
26815 uint8_t queue_id3_bw_weight;
26816 /* ID of CoS Queue 4. */
26819 * Minimum BW allocated to CoS Queue.
26820 * The HWRM will translate this value into byte counter and
26821 * time interval used for this COS inside the device.
26823 uint32_t queue_id4_min_bw;
26824 /* The bandwidth value. */
26825 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MIN_BW_BW_VALUE_MASK \
26826 UINT32_C(0xfffffff)
26827 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MIN_BW_BW_VALUE_SFT \
26829 /* The granularity of the value (bits or bytes). */
26830 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MIN_BW_SCALE \
26831 UINT32_C(0x10000000)
26832 /* Value is in bits. */
26833 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MIN_BW_SCALE_BITS \
26834 (UINT32_C(0x0) << 28)
26835 /* Value is in bytes. */
26836 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MIN_BW_SCALE_BYTES \
26837 (UINT32_C(0x1) << 28)
26838 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MIN_BW_SCALE_LAST \
26839 HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MIN_BW_SCALE_BYTES
26840 /* bw_value_unit is 3 b */
26841 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_MASK \
26842 UINT32_C(0xe0000000)
26843 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_SFT \
26845 /* Value is in Mb or MB (base 10). */
26846 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_MEGA \
26847 (UINT32_C(0x0) << 29)
26848 /* Value is in Kb or KB (base 10). */
26849 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_KILO \
26850 (UINT32_C(0x2) << 29)
26851 /* Value is in bits or bytes. */
26852 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_BASE \
26853 (UINT32_C(0x4) << 29)
26854 /* Value is in Gb or GB (base 10). */
26855 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_GIGA \
26856 (UINT32_C(0x6) << 29)
26857 /* Value is in 1/100th of a percentage of total bandwidth. */
26858 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 \
26859 (UINT32_C(0x1) << 29)
26861 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_INVALID \
26862 (UINT32_C(0x7) << 29)
26863 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_LAST \
26864 HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_INVALID
26866 * Maximum BW allocated to CoS queue.
26867 * The HWRM will translate this value into byte counter and
26868 * time interval used for this COS inside the device.
26870 uint32_t queue_id4_max_bw;
26871 /* The bandwidth value. */
26872 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MAX_BW_BW_VALUE_MASK \
26873 UINT32_C(0xfffffff)
26874 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MAX_BW_BW_VALUE_SFT \
26876 /* The granularity of the value (bits or bytes). */
26877 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MAX_BW_SCALE \
26878 UINT32_C(0x10000000)
26879 /* Value is in bits. */
26880 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MAX_BW_SCALE_BITS \
26881 (UINT32_C(0x0) << 28)
26882 /* Value is in bytes. */
26883 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MAX_BW_SCALE_BYTES \
26884 (UINT32_C(0x1) << 28)
26885 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MAX_BW_SCALE_LAST \
26886 HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MAX_BW_SCALE_BYTES
26887 /* bw_value_unit is 3 b */
26888 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_MASK \
26889 UINT32_C(0xe0000000)
26890 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_SFT \
26892 /* Value is in Mb or MB (base 10). */
26893 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_MEGA \
26894 (UINT32_C(0x0) << 29)
26895 /* Value is in Kb or KB (base 10). */
26896 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_KILO \
26897 (UINT32_C(0x2) << 29)
26898 /* Value is in bits or bytes. */
26899 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_BASE \
26900 (UINT32_C(0x4) << 29)
26901 /* Value is in Gb or GB (base 10). */
26902 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_GIGA \
26903 (UINT32_C(0x6) << 29)
26904 /* Value is in 1/100th of a percentage of total bandwidth. */
26905 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 \
26906 (UINT32_C(0x1) << 29)
26908 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_INVALID \
26909 (UINT32_C(0x7) << 29)
26910 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_LAST \
26911 HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_INVALID
26912 /* Transmission Selection Algorithm (TSA) for CoS Queue. */
26913 uint8_t queue_id4_tsa_assign;
26914 /* Strict Priority */
26915 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_TSA_ASSIGN_SP \
26917 /* Enhanced Transmission Selection */
26918 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_TSA_ASSIGN_ETS \
26921 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_TSA_ASSIGN_RESERVED_FIRST \
26924 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_TSA_ASSIGN_RESERVED_LAST \
26927 * Priority level for strict priority. Valid only when the
26928 * tsa_assign is 0 - Strict Priority (SP)
26929 * 0..7 - Valid values.
26930 * 8..255 - Reserved.
26932 uint8_t queue_id4_pri_lvl;
26934 * Weight used to allocate remaining BW for this COS after
26935 * servicing guaranteed bandwidths for all COS.
26937 uint8_t queue_id4_bw_weight;
26938 /* ID of CoS Queue 5. */
26941 * Minimum BW allocated to CoS Queue.
26942 * The HWRM will translate this value into byte counter and
26943 * time interval used for this COS inside the device.
26945 uint32_t queue_id5_min_bw;
26946 /* The bandwidth value. */
26947 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MIN_BW_BW_VALUE_MASK \
26948 UINT32_C(0xfffffff)
26949 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MIN_BW_BW_VALUE_SFT \
26951 /* The granularity of the value (bits or bytes). */
26952 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MIN_BW_SCALE \
26953 UINT32_C(0x10000000)
26954 /* Value is in bits. */
26955 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MIN_BW_SCALE_BITS \
26956 (UINT32_C(0x0) << 28)
26957 /* Value is in bytes. */
26958 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MIN_BW_SCALE_BYTES \
26959 (UINT32_C(0x1) << 28)
26960 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MIN_BW_SCALE_LAST \
26961 HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MIN_BW_SCALE_BYTES
26962 /* bw_value_unit is 3 b */
26963 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_MASK \
26964 UINT32_C(0xe0000000)
26965 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_SFT \
26967 /* Value is in Mb or MB (base 10). */
26968 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_MEGA \
26969 (UINT32_C(0x0) << 29)
26970 /* Value is in Kb or KB (base 10). */
26971 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_KILO \
26972 (UINT32_C(0x2) << 29)
26973 /* Value is in bits or bytes. */
26974 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_BASE \
26975 (UINT32_C(0x4) << 29)
26976 /* Value is in Gb or GB (base 10). */
26977 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_GIGA \
26978 (UINT32_C(0x6) << 29)
26979 /* Value is in 1/100th of a percentage of total bandwidth. */
26980 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 \
26981 (UINT32_C(0x1) << 29)
26983 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_INVALID \
26984 (UINT32_C(0x7) << 29)
26985 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_LAST \
26986 HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_INVALID
26988 * Maximum BW allocated to CoS queue.
26989 * The HWRM will translate this value into byte counter and
26990 * time interval used for this COS inside the device.
26992 uint32_t queue_id5_max_bw;
26993 /* The bandwidth value. */
26994 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MAX_BW_BW_VALUE_MASK \
26995 UINT32_C(0xfffffff)
26996 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MAX_BW_BW_VALUE_SFT \
26998 /* The granularity of the value (bits or bytes). */
26999 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MAX_BW_SCALE \
27000 UINT32_C(0x10000000)
27001 /* Value is in bits. */
27002 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MAX_BW_SCALE_BITS \
27003 (UINT32_C(0x0) << 28)
27004 /* Value is in bytes. */
27005 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MAX_BW_SCALE_BYTES \
27006 (UINT32_C(0x1) << 28)
27007 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MAX_BW_SCALE_LAST \
27008 HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MAX_BW_SCALE_BYTES
27009 /* bw_value_unit is 3 b */
27010 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_MASK \
27011 UINT32_C(0xe0000000)
27012 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_SFT \
27014 /* Value is in Mb or MB (base 10). */
27015 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_MEGA \
27016 (UINT32_C(0x0) << 29)
27017 /* Value is in Kb or KB (base 10). */
27018 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_KILO \
27019 (UINT32_C(0x2) << 29)
27020 /* Value is in bits or bytes. */
27021 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_BASE \
27022 (UINT32_C(0x4) << 29)
27023 /* Value is in Gb or GB (base 10). */
27024 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_GIGA \
27025 (UINT32_C(0x6) << 29)
27026 /* Value is in 1/100th of a percentage of total bandwidth. */
27027 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 \
27028 (UINT32_C(0x1) << 29)
27030 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_INVALID \
27031 (UINT32_C(0x7) << 29)
27032 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_LAST \
27033 HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_INVALID
27034 /* Transmission Selection Algorithm (TSA) for CoS Queue. */
27035 uint8_t queue_id5_tsa_assign;
27036 /* Strict Priority */
27037 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_TSA_ASSIGN_SP \
27039 /* Enhanced Transmission Selection */
27040 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_TSA_ASSIGN_ETS \
27043 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_TSA_ASSIGN_RESERVED_FIRST \
27046 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_TSA_ASSIGN_RESERVED_LAST \
27049 * Priority level for strict priority. Valid only when the
27050 * tsa_assign is 0 - Strict Priority (SP)
27051 * 0..7 - Valid values.
27052 * 8..255 - Reserved.
27054 uint8_t queue_id5_pri_lvl;
27056 * Weight used to allocate remaining BW for this COS after
27057 * servicing guaranteed bandwidths for all COS.
27059 uint8_t queue_id5_bw_weight;
27060 /* ID of CoS Queue 6. */
27063 * Minimum BW allocated to CoS Queue.
27064 * The HWRM will translate this value into byte counter and
27065 * time interval used for this COS inside the device.
27067 uint32_t queue_id6_min_bw;
27068 /* The bandwidth value. */
27069 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MIN_BW_BW_VALUE_MASK \
27070 UINT32_C(0xfffffff)
27071 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MIN_BW_BW_VALUE_SFT \
27073 /* The granularity of the value (bits or bytes). */
27074 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MIN_BW_SCALE \
27075 UINT32_C(0x10000000)
27076 /* Value is in bits. */
27077 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MIN_BW_SCALE_BITS \
27078 (UINT32_C(0x0) << 28)
27079 /* Value is in bytes. */
27080 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MIN_BW_SCALE_BYTES \
27081 (UINT32_C(0x1) << 28)
27082 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MIN_BW_SCALE_LAST \
27083 HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MIN_BW_SCALE_BYTES
27084 /* bw_value_unit is 3 b */
27085 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_MASK \
27086 UINT32_C(0xe0000000)
27087 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_SFT \
27089 /* Value is in Mb or MB (base 10). */
27090 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_MEGA \
27091 (UINT32_C(0x0) << 29)
27092 /* Value is in Kb or KB (base 10). */
27093 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_KILO \
27094 (UINT32_C(0x2) << 29)
27095 /* Value is in bits or bytes. */
27096 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_BASE \
27097 (UINT32_C(0x4) << 29)
27098 /* Value is in Gb or GB (base 10). */
27099 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_GIGA \
27100 (UINT32_C(0x6) << 29)
27101 /* Value is in 1/100th of a percentage of total bandwidth. */
27102 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 \
27103 (UINT32_C(0x1) << 29)
27105 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_INVALID \
27106 (UINT32_C(0x7) << 29)
27107 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_LAST \
27108 HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_INVALID
27110 * Maximum BW allocated to CoS queue.
27111 * The HWRM will translate this value into byte counter and
27112 * time interval used for this COS inside the device.
27114 uint32_t queue_id6_max_bw;
27115 /* The bandwidth value. */
27116 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MAX_BW_BW_VALUE_MASK \
27117 UINT32_C(0xfffffff)
27118 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MAX_BW_BW_VALUE_SFT \
27120 /* The granularity of the value (bits or bytes). */
27121 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MAX_BW_SCALE \
27122 UINT32_C(0x10000000)
27123 /* Value is in bits. */
27124 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MAX_BW_SCALE_BITS \
27125 (UINT32_C(0x0) << 28)
27126 /* Value is in bytes. */
27127 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MAX_BW_SCALE_BYTES \
27128 (UINT32_C(0x1) << 28)
27129 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MAX_BW_SCALE_LAST \
27130 HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MAX_BW_SCALE_BYTES
27131 /* bw_value_unit is 3 b */
27132 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_MASK \
27133 UINT32_C(0xe0000000)
27134 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_SFT \
27136 /* Value is in Mb or MB (base 10). */
27137 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_MEGA \
27138 (UINT32_C(0x0) << 29)
27139 /* Value is in Kb or KB (base 10). */
27140 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_KILO \
27141 (UINT32_C(0x2) << 29)
27142 /* Value is in bits or bytes. */
27143 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_BASE \
27144 (UINT32_C(0x4) << 29)
27145 /* Value is in Gb or GB (base 10). */
27146 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_GIGA \
27147 (UINT32_C(0x6) << 29)
27148 /* Value is in 1/100th of a percentage of total bandwidth. */
27149 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 \
27150 (UINT32_C(0x1) << 29)
27152 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_INVALID \
27153 (UINT32_C(0x7) << 29)
27154 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_LAST \
27155 HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_INVALID
27156 /* Transmission Selection Algorithm (TSA) for CoS Queue. */
27157 uint8_t queue_id6_tsa_assign;
27158 /* Strict Priority */
27159 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_TSA_ASSIGN_SP \
27161 /* Enhanced Transmission Selection */
27162 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_TSA_ASSIGN_ETS \
27165 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_TSA_ASSIGN_RESERVED_FIRST \
27168 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_TSA_ASSIGN_RESERVED_LAST \
27171 * Priority level for strict priority. Valid only when the
27172 * tsa_assign is 0 - Strict Priority (SP)
27173 * 0..7 - Valid values.
27174 * 8..255 - Reserved.
27176 uint8_t queue_id6_pri_lvl;
27178 * Weight used to allocate remaining BW for this COS after
27179 * servicing guaranteed bandwidths for all COS.
27181 uint8_t queue_id6_bw_weight;
27182 /* ID of CoS Queue 7. */
27185 * Minimum BW allocated to CoS Queue.
27186 * The HWRM will translate this value into byte counter and
27187 * time interval used for this COS inside the device.
27189 uint32_t queue_id7_min_bw;
27190 /* The bandwidth value. */
27191 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MIN_BW_BW_VALUE_MASK \
27192 UINT32_C(0xfffffff)
27193 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MIN_BW_BW_VALUE_SFT \
27195 /* The granularity of the value (bits or bytes). */
27196 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MIN_BW_SCALE \
27197 UINT32_C(0x10000000)
27198 /* Value is in bits. */
27199 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MIN_BW_SCALE_BITS \
27200 (UINT32_C(0x0) << 28)
27201 /* Value is in bytes. */
27202 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MIN_BW_SCALE_BYTES \
27203 (UINT32_C(0x1) << 28)
27204 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MIN_BW_SCALE_LAST \
27205 HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MIN_BW_SCALE_BYTES
27206 /* bw_value_unit is 3 b */
27207 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_MASK \
27208 UINT32_C(0xe0000000)
27209 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_SFT \
27211 /* Value is in Mb or MB (base 10). */
27212 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_MEGA \
27213 (UINT32_C(0x0) << 29)
27214 /* Value is in Kb or KB (base 10). */
27215 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_KILO \
27216 (UINT32_C(0x2) << 29)
27217 /* Value is in bits or bytes. */
27218 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_BASE \
27219 (UINT32_C(0x4) << 29)
27220 /* Value is in Gb or GB (base 10). */
27221 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_GIGA \
27222 (UINT32_C(0x6) << 29)
27223 /* Value is in 1/100th of a percentage of total bandwidth. */
27224 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 \
27225 (UINT32_C(0x1) << 29)
27227 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_INVALID \
27228 (UINT32_C(0x7) << 29)
27229 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_LAST \
27230 HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_INVALID
27232 * Maximum BW allocated to CoS queue.
27233 * The HWRM will translate this value into byte counter and
27234 * time interval used for this COS inside the device.
27236 uint32_t queue_id7_max_bw;
27237 /* The bandwidth value. */
27238 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MAX_BW_BW_VALUE_MASK \
27239 UINT32_C(0xfffffff)
27240 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MAX_BW_BW_VALUE_SFT \
27242 /* The granularity of the value (bits or bytes). */
27243 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MAX_BW_SCALE \
27244 UINT32_C(0x10000000)
27245 /* Value is in bits. */
27246 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MAX_BW_SCALE_BITS \
27247 (UINT32_C(0x0) << 28)
27248 /* Value is in bytes. */
27249 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MAX_BW_SCALE_BYTES \
27250 (UINT32_C(0x1) << 28)
27251 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MAX_BW_SCALE_LAST \
27252 HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MAX_BW_SCALE_BYTES
27253 /* bw_value_unit is 3 b */
27254 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_MASK \
27255 UINT32_C(0xe0000000)
27256 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_SFT \
27258 /* Value is in Mb or MB (base 10). */
27259 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_MEGA \
27260 (UINT32_C(0x0) << 29)
27261 /* Value is in Kb or KB (base 10). */
27262 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_KILO \
27263 (UINT32_C(0x2) << 29)
27264 /* Value is in bits or bytes. */
27265 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_BASE \
27266 (UINT32_C(0x4) << 29)
27267 /* Value is in Gb or GB (base 10). */
27268 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_GIGA \
27269 (UINT32_C(0x6) << 29)
27270 /* Value is in 1/100th of a percentage of total bandwidth. */
27271 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 \
27272 (UINT32_C(0x1) << 29)
27274 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_INVALID \
27275 (UINT32_C(0x7) << 29)
27276 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_LAST \
27277 HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_INVALID
27278 /* Transmission Selection Algorithm (TSA) for CoS Queue. */
27279 uint8_t queue_id7_tsa_assign;
27280 /* Strict Priority */
27281 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_TSA_ASSIGN_SP \
27283 /* Enhanced Transmission Selection */
27284 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_TSA_ASSIGN_ETS \
27287 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_TSA_ASSIGN_RESERVED_FIRST \
27290 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_TSA_ASSIGN_RESERVED_LAST \
27293 * Priority level for strict priority. Valid only when the
27294 * tsa_assign is 0 - Strict Priority (SP)
27295 * 0..7 - Valid values.
27296 * 8..255 - Reserved.
27298 uint8_t queue_id7_pri_lvl;
27300 * Weight used to allocate remaining BW for this COS after
27301 * servicing guaranteed bandwidths for all COS.
27303 uint8_t queue_id7_bw_weight;
27304 uint8_t unused_2[4];
27306 * This field is used in Output records to indicate that the output
27307 * is completely written to RAM. This field should be read as '1'
27308 * to indicate that the output has been completely written.
27309 * When writing a command completion or response to an internal processor,
27310 * the order of writes has to be such that this field is written last.
27315 /*************************
27316 * hwrm_queue_cos2bw_cfg *
27317 *************************/
27320 /* hwrm_queue_cos2bw_cfg_input (size:1024b/128B) */
27321 struct hwrm_queue_cos2bw_cfg_input {
27322 /* The HWRM command request type. */
27325 * The completion ring to send the completion event on. This should
27326 * be the NQ ID returned from the `nq_alloc` HWRM command.
27328 uint16_t cmpl_ring;
27330 * The sequence ID is used by the driver for tracking multiple
27331 * commands. This ID is treated as opaque data by the firmware and
27332 * the value is returned in the `hwrm_resp_hdr` upon completion.
27336 * The target ID of the command:
27337 * * 0x0-0xFFF8 - The function ID
27338 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
27339 * * 0xFFFD - Reserved for user-space HWRM interface
27342 uint16_t target_id;
27344 * A physical address pointer pointing to a host buffer that the
27345 * command's response data will be written. This can be either a host
27346 * physical address (HPA) or a guest physical address (GPA) and must
27347 * point to a physically contiguous block of memory.
27349 uint64_t resp_addr;
27353 * If this bit is set to 1, then all queue_id0 related
27354 * parameters in this command are valid.
27356 #define HWRM_QUEUE_COS2BW_CFG_INPUT_ENABLES_COS_QUEUE_ID0_VALID \
27359 * If this bit is set to 1, then all queue_id1 related
27360 * parameters in this command are valid.
27362 #define HWRM_QUEUE_COS2BW_CFG_INPUT_ENABLES_COS_QUEUE_ID1_VALID \
27365 * If this bit is set to 1, then all queue_id2 related
27366 * parameters in this command are valid.
27368 #define HWRM_QUEUE_COS2BW_CFG_INPUT_ENABLES_COS_QUEUE_ID2_VALID \
27371 * If this bit is set to 1, then all queue_id3 related
27372 * parameters in this command are valid.
27374 #define HWRM_QUEUE_COS2BW_CFG_INPUT_ENABLES_COS_QUEUE_ID3_VALID \
27377 * If this bit is set to 1, then all queue_id4 related
27378 * parameters in this command are valid.
27380 #define HWRM_QUEUE_COS2BW_CFG_INPUT_ENABLES_COS_QUEUE_ID4_VALID \
27383 * If this bit is set to 1, then all queue_id5 related
27384 * parameters in this command are valid.
27386 #define HWRM_QUEUE_COS2BW_CFG_INPUT_ENABLES_COS_QUEUE_ID5_VALID \
27389 * If this bit is set to 1, then all queue_id6 related
27390 * parameters in this command are valid.
27392 #define HWRM_QUEUE_COS2BW_CFG_INPUT_ENABLES_COS_QUEUE_ID6_VALID \
27395 * If this bit is set to 1, then all queue_id7 related
27396 * parameters in this command are valid.
27398 #define HWRM_QUEUE_COS2BW_CFG_INPUT_ENABLES_COS_QUEUE_ID7_VALID \
27401 * Port ID of port for which the table is being configured.
27402 * The HWRM needs to check whether this function is allowed
27403 * to configure TC BW assignment on this port.
27406 /* ID of CoS Queue 0. */
27410 * Minimum BW allocated to CoS Queue.
27411 * The HWRM will translate this value into byte counter and
27412 * time interval used for this COS inside the device.
27414 uint32_t queue_id0_min_bw;
27415 /* The bandwidth value. */
27416 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MIN_BW_BW_VALUE_MASK \
27417 UINT32_C(0xfffffff)
27418 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MIN_BW_BW_VALUE_SFT \
27420 /* The granularity of the value (bits or bytes). */
27421 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MIN_BW_SCALE \
27422 UINT32_C(0x10000000)
27423 /* Value is in bits. */
27424 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MIN_BW_SCALE_BITS \
27425 (UINT32_C(0x0) << 28)
27426 /* Value is in bytes. */
27427 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MIN_BW_SCALE_BYTES \
27428 (UINT32_C(0x1) << 28)
27429 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MIN_BW_SCALE_LAST \
27430 HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MIN_BW_SCALE_BYTES
27431 /* bw_value_unit is 3 b */
27432 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_MASK \
27433 UINT32_C(0xe0000000)
27434 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_SFT \
27436 /* Value is in Mb or MB (base 10). */
27437 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_MEGA \
27438 (UINT32_C(0x0) << 29)
27439 /* Value is in Kb or KB (base 10). */
27440 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_KILO \
27441 (UINT32_C(0x2) << 29)
27442 /* Value is in bits or bytes. */
27443 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_BASE \
27444 (UINT32_C(0x4) << 29)
27445 /* Value is in Gb or GB (base 10). */
27446 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_GIGA \
27447 (UINT32_C(0x6) << 29)
27448 /* Value is in 1/100th of a percentage of total bandwidth. */
27449 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 \
27450 (UINT32_C(0x1) << 29)
27452 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_INVALID \
27453 (UINT32_C(0x7) << 29)
27454 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_LAST \
27455 HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_INVALID
27457 * Maximum BW allocated to CoS Queue.
27458 * The HWRM will translate this value into byte counter and
27459 * time interval used for this COS inside the device.
27461 uint32_t queue_id0_max_bw;
27462 /* The bandwidth value. */
27463 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MAX_BW_BW_VALUE_MASK \
27464 UINT32_C(0xfffffff)
27465 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MAX_BW_BW_VALUE_SFT \
27467 /* The granularity of the value (bits or bytes). */
27468 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MAX_BW_SCALE \
27469 UINT32_C(0x10000000)
27470 /* Value is in bits. */
27471 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MAX_BW_SCALE_BITS \
27472 (UINT32_C(0x0) << 28)
27473 /* Value is in bytes. */
27474 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MAX_BW_SCALE_BYTES \
27475 (UINT32_C(0x1) << 28)
27476 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MAX_BW_SCALE_LAST \
27477 HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MAX_BW_SCALE_BYTES
27478 /* bw_value_unit is 3 b */
27479 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_MASK \
27480 UINT32_C(0xe0000000)
27481 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_SFT \
27483 /* Value is in Mb or MB (base 10). */
27484 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_MEGA \
27485 (UINT32_C(0x0) << 29)
27486 /* Value is in Kb or KB (base 10). */
27487 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_KILO \
27488 (UINT32_C(0x2) << 29)
27489 /* Value is in bits or bytes. */
27490 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_BASE \
27491 (UINT32_C(0x4) << 29)
27492 /* Value is in Gb or GB (base 10). */
27493 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_GIGA \
27494 (UINT32_C(0x6) << 29)
27495 /* Value is in 1/100th of a percentage of total bandwidth. */
27496 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 \
27497 (UINT32_C(0x1) << 29)
27499 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_INVALID \
27500 (UINT32_C(0x7) << 29)
27501 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_LAST \
27502 HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_INVALID
27503 /* Transmission Selection Algorithm (TSA) for CoS Queue. */
27504 uint8_t queue_id0_tsa_assign;
27505 /* Strict Priority */
27506 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_TSA_ASSIGN_SP \
27508 /* Enhanced Transmission Selection */
27509 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_TSA_ASSIGN_ETS \
27512 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_TSA_ASSIGN_RESERVED_FIRST \
27515 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_TSA_ASSIGN_RESERVED_LAST \
27518 * Priority level for strict priority. Valid only when the
27519 * tsa_assign is 0 - Strict Priority (SP)
27520 * 0..7 - Valid values.
27521 * 8..255 - Reserved.
27523 uint8_t queue_id0_pri_lvl;
27525 * Weight used to allocate remaining BW for this COS after
27526 * servicing guaranteed bandwidths for all COS.
27528 uint8_t queue_id0_bw_weight;
27529 /* ID of CoS Queue 1. */
27532 * Minimum BW allocated to CoS Queue.
27533 * The HWRM will translate this value into byte counter and
27534 * time interval used for this COS inside the device.
27536 uint32_t queue_id1_min_bw;
27537 /* The bandwidth value. */
27538 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MIN_BW_BW_VALUE_MASK \
27539 UINT32_C(0xfffffff)
27540 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MIN_BW_BW_VALUE_SFT \
27542 /* The granularity of the value (bits or bytes). */
27543 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MIN_BW_SCALE \
27544 UINT32_C(0x10000000)
27545 /* Value is in bits. */
27546 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MIN_BW_SCALE_BITS \
27547 (UINT32_C(0x0) << 28)
27548 /* Value is in bytes. */
27549 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MIN_BW_SCALE_BYTES \
27550 (UINT32_C(0x1) << 28)
27551 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MIN_BW_SCALE_LAST \
27552 HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MIN_BW_SCALE_BYTES
27553 /* bw_value_unit is 3 b */
27554 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_MASK \
27555 UINT32_C(0xe0000000)
27556 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_SFT \
27558 /* Value is in Mb or MB (base 10). */
27559 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_MEGA \
27560 (UINT32_C(0x0) << 29)
27561 /* Value is in Kb or KB (base 10). */
27562 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_KILO \
27563 (UINT32_C(0x2) << 29)
27564 /* Value is in bits or bytes. */
27565 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_BASE \
27566 (UINT32_C(0x4) << 29)
27567 /* Value is in Gb or GB (base 10). */
27568 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_GIGA \
27569 (UINT32_C(0x6) << 29)
27570 /* Value is in 1/100th of a percentage of total bandwidth. */
27571 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 \
27572 (UINT32_C(0x1) << 29)
27574 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_INVALID \
27575 (UINT32_C(0x7) << 29)
27576 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_LAST \
27577 HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_INVALID
27579 * Maximum BW allocated to CoS queue.
27580 * The HWRM will translate this value into byte counter and
27581 * time interval used for this COS inside the device.
27583 uint32_t queue_id1_max_bw;
27584 /* The bandwidth value. */
27585 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MAX_BW_BW_VALUE_MASK \
27586 UINT32_C(0xfffffff)
27587 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MAX_BW_BW_VALUE_SFT \
27589 /* The granularity of the value (bits or bytes). */
27590 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MAX_BW_SCALE \
27591 UINT32_C(0x10000000)
27592 /* Value is in bits. */
27593 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MAX_BW_SCALE_BITS \
27594 (UINT32_C(0x0) << 28)
27595 /* Value is in bytes. */
27596 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MAX_BW_SCALE_BYTES \
27597 (UINT32_C(0x1) << 28)
27598 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MAX_BW_SCALE_LAST \
27599 HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MAX_BW_SCALE_BYTES
27600 /* bw_value_unit is 3 b */
27601 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_MASK \
27602 UINT32_C(0xe0000000)
27603 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_SFT \
27605 /* Value is in Mb or MB (base 10). */
27606 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_MEGA \
27607 (UINT32_C(0x0) << 29)
27608 /* Value is in Kb or KB (base 10). */
27609 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_KILO \
27610 (UINT32_C(0x2) << 29)
27611 /* Value is in bits or bytes. */
27612 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_BASE \
27613 (UINT32_C(0x4) << 29)
27614 /* Value is in Gb or GB (base 10). */
27615 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_GIGA \
27616 (UINT32_C(0x6) << 29)
27617 /* Value is in 1/100th of a percentage of total bandwidth. */
27618 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 \
27619 (UINT32_C(0x1) << 29)
27621 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_INVALID \
27622 (UINT32_C(0x7) << 29)
27623 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_LAST \
27624 HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_INVALID
27625 /* Transmission Selection Algorithm (TSA) for CoS Queue. */
27626 uint8_t queue_id1_tsa_assign;
27627 /* Strict Priority */
27628 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_TSA_ASSIGN_SP \
27630 /* Enhanced Transmission Selection */
27631 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_TSA_ASSIGN_ETS \
27634 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_TSA_ASSIGN_RESERVED_FIRST \
27637 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_TSA_ASSIGN_RESERVED_LAST \
27640 * Priority level for strict priority. Valid only when the
27641 * tsa_assign is 0 - Strict Priority (SP)
27642 * 0..7 - Valid values.
27643 * 8..255 - Reserved.
27645 uint8_t queue_id1_pri_lvl;
27647 * Weight used to allocate remaining BW for this COS after
27648 * servicing guaranteed bandwidths for all COS.
27650 uint8_t queue_id1_bw_weight;
27651 /* ID of CoS Queue 2. */
27654 * Minimum BW allocated to CoS Queue.
27655 * The HWRM will translate this value into byte counter and
27656 * time interval used for this COS inside the device.
27658 uint32_t queue_id2_min_bw;
27659 /* The bandwidth value. */
27660 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MIN_BW_BW_VALUE_MASK \
27661 UINT32_C(0xfffffff)
27662 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MIN_BW_BW_VALUE_SFT \
27664 /* The granularity of the value (bits or bytes). */
27665 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MIN_BW_SCALE \
27666 UINT32_C(0x10000000)
27667 /* Value is in bits. */
27668 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MIN_BW_SCALE_BITS \
27669 (UINT32_C(0x0) << 28)
27670 /* Value is in bytes. */
27671 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MIN_BW_SCALE_BYTES \
27672 (UINT32_C(0x1) << 28)
27673 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MIN_BW_SCALE_LAST \
27674 HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MIN_BW_SCALE_BYTES
27675 /* bw_value_unit is 3 b */
27676 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_MASK \
27677 UINT32_C(0xe0000000)
27678 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_SFT \
27680 /* Value is in Mb or MB (base 10). */
27681 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_MEGA \
27682 (UINT32_C(0x0) << 29)
27683 /* Value is in Kb or KB (base 10). */
27684 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_KILO \
27685 (UINT32_C(0x2) << 29)
27686 /* Value is in bits or bytes. */
27687 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_BASE \
27688 (UINT32_C(0x4) << 29)
27689 /* Value is in Gb or GB (base 10). */
27690 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_GIGA \
27691 (UINT32_C(0x6) << 29)
27692 /* Value is in 1/100th of a percentage of total bandwidth. */
27693 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 \
27694 (UINT32_C(0x1) << 29)
27696 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_INVALID \
27697 (UINT32_C(0x7) << 29)
27698 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_LAST \
27699 HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_INVALID
27701 * Maximum BW allocated to CoS queue.
27702 * The HWRM will translate this value into byte counter and
27703 * time interval used for this COS inside the device.
27705 uint32_t queue_id2_max_bw;
27706 /* The bandwidth value. */
27707 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MAX_BW_BW_VALUE_MASK \
27708 UINT32_C(0xfffffff)
27709 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MAX_BW_BW_VALUE_SFT \
27711 /* The granularity of the value (bits or bytes). */
27712 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MAX_BW_SCALE \
27713 UINT32_C(0x10000000)
27714 /* Value is in bits. */
27715 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MAX_BW_SCALE_BITS \
27716 (UINT32_C(0x0) << 28)
27717 /* Value is in bytes. */
27718 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MAX_BW_SCALE_BYTES \
27719 (UINT32_C(0x1) << 28)
27720 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MAX_BW_SCALE_LAST \
27721 HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MAX_BW_SCALE_BYTES
27722 /* bw_value_unit is 3 b */
27723 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_MASK \
27724 UINT32_C(0xe0000000)
27725 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_SFT \
27727 /* Value is in Mb or MB (base 10). */
27728 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_MEGA \
27729 (UINT32_C(0x0) << 29)
27730 /* Value is in Kb or KB (base 10). */
27731 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_KILO \
27732 (UINT32_C(0x2) << 29)
27733 /* Value is in bits or bytes. */
27734 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_BASE \
27735 (UINT32_C(0x4) << 29)
27736 /* Value is in Gb or GB (base 10). */
27737 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_GIGA \
27738 (UINT32_C(0x6) << 29)
27739 /* Value is in 1/100th of a percentage of total bandwidth. */
27740 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 \
27741 (UINT32_C(0x1) << 29)
27743 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_INVALID \
27744 (UINT32_C(0x7) << 29)
27745 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_LAST \
27746 HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_INVALID
27747 /* Transmission Selection Algorithm (TSA) for CoS Queue. */
27748 uint8_t queue_id2_tsa_assign;
27749 /* Strict Priority */
27750 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_TSA_ASSIGN_SP \
27752 /* Enhanced Transmission Selection */
27753 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_TSA_ASSIGN_ETS \
27756 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_TSA_ASSIGN_RESERVED_FIRST \
27759 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_TSA_ASSIGN_RESERVED_LAST \
27762 * Priority level for strict priority. Valid only when the
27763 * tsa_assign is 0 - Strict Priority (SP)
27764 * 0..7 - Valid values.
27765 * 8..255 - Reserved.
27767 uint8_t queue_id2_pri_lvl;
27769 * Weight used to allocate remaining BW for this COS after
27770 * servicing guaranteed bandwidths for all COS.
27772 uint8_t queue_id2_bw_weight;
27773 /* ID of CoS Queue 3. */
27776 * Minimum BW allocated to CoS Queue.
27777 * The HWRM will translate this value into byte counter and
27778 * time interval used for this COS inside the device.
27780 uint32_t queue_id3_min_bw;
27781 /* The bandwidth value. */
27782 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MIN_BW_BW_VALUE_MASK \
27783 UINT32_C(0xfffffff)
27784 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MIN_BW_BW_VALUE_SFT \
27786 /* The granularity of the value (bits or bytes). */
27787 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MIN_BW_SCALE \
27788 UINT32_C(0x10000000)
27789 /* Value is in bits. */
27790 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MIN_BW_SCALE_BITS \
27791 (UINT32_C(0x0) << 28)
27792 /* Value is in bytes. */
27793 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MIN_BW_SCALE_BYTES \
27794 (UINT32_C(0x1) << 28)
27795 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MIN_BW_SCALE_LAST \
27796 HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MIN_BW_SCALE_BYTES
27797 /* bw_value_unit is 3 b */
27798 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_MASK \
27799 UINT32_C(0xe0000000)
27800 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_SFT \
27802 /* Value is in Mb or MB (base 10). */
27803 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_MEGA \
27804 (UINT32_C(0x0) << 29)
27805 /* Value is in Kb or KB (base 10). */
27806 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_KILO \
27807 (UINT32_C(0x2) << 29)
27808 /* Value is in bits or bytes. */
27809 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_BASE \
27810 (UINT32_C(0x4) << 29)
27811 /* Value is in Gb or GB (base 10). */
27812 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_GIGA \
27813 (UINT32_C(0x6) << 29)
27814 /* Value is in 1/100th of a percentage of total bandwidth. */
27815 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 \
27816 (UINT32_C(0x1) << 29)
27818 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_INVALID \
27819 (UINT32_C(0x7) << 29)
27820 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_LAST \
27821 HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_INVALID
27823 * Maximum BW allocated to CoS queue.
27824 * The HWRM will translate this value into byte counter and
27825 * time interval used for this COS inside the device.
27827 uint32_t queue_id3_max_bw;
27828 /* The bandwidth value. */
27829 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MAX_BW_BW_VALUE_MASK \
27830 UINT32_C(0xfffffff)
27831 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MAX_BW_BW_VALUE_SFT \
27833 /* The granularity of the value (bits or bytes). */
27834 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MAX_BW_SCALE \
27835 UINT32_C(0x10000000)
27836 /* Value is in bits. */
27837 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MAX_BW_SCALE_BITS \
27838 (UINT32_C(0x0) << 28)
27839 /* Value is in bytes. */
27840 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MAX_BW_SCALE_BYTES \
27841 (UINT32_C(0x1) << 28)
27842 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MAX_BW_SCALE_LAST \
27843 HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MAX_BW_SCALE_BYTES
27844 /* bw_value_unit is 3 b */
27845 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_MASK \
27846 UINT32_C(0xe0000000)
27847 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_SFT \
27849 /* Value is in Mb or MB (base 10). */
27850 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_MEGA \
27851 (UINT32_C(0x0) << 29)
27852 /* Value is in Kb or KB (base 10). */
27853 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_KILO \
27854 (UINT32_C(0x2) << 29)
27855 /* Value is in bits or bytes. */
27856 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_BASE \
27857 (UINT32_C(0x4) << 29)
27858 /* Value is in Gb or GB (base 10). */
27859 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_GIGA \
27860 (UINT32_C(0x6) << 29)
27861 /* Value is in 1/100th of a percentage of total bandwidth. */
27862 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 \
27863 (UINT32_C(0x1) << 29)
27865 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_INVALID \
27866 (UINT32_C(0x7) << 29)
27867 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_LAST \
27868 HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_INVALID
27869 /* Transmission Selection Algorithm (TSA) for CoS Queue. */
27870 uint8_t queue_id3_tsa_assign;
27871 /* Strict Priority */
27872 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_TSA_ASSIGN_SP \
27874 /* Enhanced Transmission Selection */
27875 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_TSA_ASSIGN_ETS \
27878 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_TSA_ASSIGN_RESERVED_FIRST \
27881 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_TSA_ASSIGN_RESERVED_LAST \
27884 * Priority level for strict priority. Valid only when the
27885 * tsa_assign is 0 - Strict Priority (SP)
27886 * 0..7 - Valid values.
27887 * 8..255 - Reserved.
27889 uint8_t queue_id3_pri_lvl;
27891 * Weight used to allocate remaining BW for this COS after
27892 * servicing guaranteed bandwidths for all COS.
27894 uint8_t queue_id3_bw_weight;
27895 /* ID of CoS Queue 4. */
27898 * Minimum BW allocated to CoS Queue.
27899 * The HWRM will translate this value into byte counter and
27900 * time interval used for this COS inside the device.
27902 uint32_t queue_id4_min_bw;
27903 /* The bandwidth value. */
27904 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MIN_BW_BW_VALUE_MASK \
27905 UINT32_C(0xfffffff)
27906 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MIN_BW_BW_VALUE_SFT \
27908 /* The granularity of the value (bits or bytes). */
27909 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MIN_BW_SCALE \
27910 UINT32_C(0x10000000)
27911 /* Value is in bits. */
27912 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MIN_BW_SCALE_BITS \
27913 (UINT32_C(0x0) << 28)
27914 /* Value is in bytes. */
27915 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MIN_BW_SCALE_BYTES \
27916 (UINT32_C(0x1) << 28)
27917 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MIN_BW_SCALE_LAST \
27918 HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MIN_BW_SCALE_BYTES
27919 /* bw_value_unit is 3 b */
27920 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_MASK \
27921 UINT32_C(0xe0000000)
27922 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_SFT \
27924 /* Value is in Mb or MB (base 10). */
27925 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_MEGA \
27926 (UINT32_C(0x0) << 29)
27927 /* Value is in Kb or KB (base 10). */
27928 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_KILO \
27929 (UINT32_C(0x2) << 29)
27930 /* Value is in bits or bytes. */
27931 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_BASE \
27932 (UINT32_C(0x4) << 29)
27933 /* Value is in Gb or GB (base 10). */
27934 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_GIGA \
27935 (UINT32_C(0x6) << 29)
27936 /* Value is in 1/100th of a percentage of total bandwidth. */
27937 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 \
27938 (UINT32_C(0x1) << 29)
27940 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_INVALID \
27941 (UINT32_C(0x7) << 29)
27942 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_LAST \
27943 HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_INVALID
27945 * Maximum BW allocated to CoS queue.
27946 * The HWRM will translate this value into byte counter and
27947 * time interval used for this COS inside the device.
27949 uint32_t queue_id4_max_bw;
27950 /* The bandwidth value. */
27951 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MAX_BW_BW_VALUE_MASK \
27952 UINT32_C(0xfffffff)
27953 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MAX_BW_BW_VALUE_SFT \
27955 /* The granularity of the value (bits or bytes). */
27956 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MAX_BW_SCALE \
27957 UINT32_C(0x10000000)
27958 /* Value is in bits. */
27959 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MAX_BW_SCALE_BITS \
27960 (UINT32_C(0x0) << 28)
27961 /* Value is in bytes. */
27962 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MAX_BW_SCALE_BYTES \
27963 (UINT32_C(0x1) << 28)
27964 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MAX_BW_SCALE_LAST \
27965 HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MAX_BW_SCALE_BYTES
27966 /* bw_value_unit is 3 b */
27967 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_MASK \
27968 UINT32_C(0xe0000000)
27969 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_SFT \
27971 /* Value is in Mb or MB (base 10). */
27972 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_MEGA \
27973 (UINT32_C(0x0) << 29)
27974 /* Value is in Kb or KB (base 10). */
27975 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_KILO \
27976 (UINT32_C(0x2) << 29)
27977 /* Value is in bits or bytes. */
27978 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_BASE \
27979 (UINT32_C(0x4) << 29)
27980 /* Value is in Gb or GB (base 10). */
27981 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_GIGA \
27982 (UINT32_C(0x6) << 29)
27983 /* Value is in 1/100th of a percentage of total bandwidth. */
27984 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 \
27985 (UINT32_C(0x1) << 29)
27987 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_INVALID \
27988 (UINT32_C(0x7) << 29)
27989 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_LAST \
27990 HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_INVALID
27991 /* Transmission Selection Algorithm (TSA) for CoS Queue. */
27992 uint8_t queue_id4_tsa_assign;
27993 /* Strict Priority */
27994 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_TSA_ASSIGN_SP \
27996 /* Enhanced Transmission Selection */
27997 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_TSA_ASSIGN_ETS \
28000 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_TSA_ASSIGN_RESERVED_FIRST \
28003 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_TSA_ASSIGN_RESERVED_LAST \
28006 * Priority level for strict priority. Valid only when the
28007 * tsa_assign is 0 - Strict Priority (SP)
28008 * 0..7 - Valid values.
28009 * 8..255 - Reserved.
28011 uint8_t queue_id4_pri_lvl;
28013 * Weight used to allocate remaining BW for this COS after
28014 * servicing guaranteed bandwidths for all COS.
28016 uint8_t queue_id4_bw_weight;
28017 /* ID of CoS Queue 5. */
28020 * Minimum BW allocated to CoS Queue.
28021 * The HWRM will translate this value into byte counter and
28022 * time interval used for this COS inside the device.
28024 uint32_t queue_id5_min_bw;
28025 /* The bandwidth value. */
28026 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MIN_BW_BW_VALUE_MASK \
28027 UINT32_C(0xfffffff)
28028 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MIN_BW_BW_VALUE_SFT \
28030 /* The granularity of the value (bits or bytes). */
28031 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MIN_BW_SCALE \
28032 UINT32_C(0x10000000)
28033 /* Value is in bits. */
28034 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MIN_BW_SCALE_BITS \
28035 (UINT32_C(0x0) << 28)
28036 /* Value is in bytes. */
28037 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MIN_BW_SCALE_BYTES \
28038 (UINT32_C(0x1) << 28)
28039 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MIN_BW_SCALE_LAST \
28040 HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MIN_BW_SCALE_BYTES
28041 /* bw_value_unit is 3 b */
28042 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_MASK \
28043 UINT32_C(0xe0000000)
28044 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_SFT \
28046 /* Value is in Mb or MB (base 10). */
28047 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_MEGA \
28048 (UINT32_C(0x0) << 29)
28049 /* Value is in Kb or KB (base 10). */
28050 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_KILO \
28051 (UINT32_C(0x2) << 29)
28052 /* Value is in bits or bytes. */
28053 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_BASE \
28054 (UINT32_C(0x4) << 29)
28055 /* Value is in Gb or GB (base 10). */
28056 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_GIGA \
28057 (UINT32_C(0x6) << 29)
28058 /* Value is in 1/100th of a percentage of total bandwidth. */
28059 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 \
28060 (UINT32_C(0x1) << 29)
28062 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_INVALID \
28063 (UINT32_C(0x7) << 29)
28064 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_LAST \
28065 HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_INVALID
28067 * Maximum BW allocated to CoS queue.
28068 * The HWRM will translate this value into byte counter and
28069 * time interval used for this COS inside the device.
28071 uint32_t queue_id5_max_bw;
28072 /* The bandwidth value. */
28073 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MAX_BW_BW_VALUE_MASK \
28074 UINT32_C(0xfffffff)
28075 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MAX_BW_BW_VALUE_SFT \
28077 /* The granularity of the value (bits or bytes). */
28078 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MAX_BW_SCALE \
28079 UINT32_C(0x10000000)
28080 /* Value is in bits. */
28081 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MAX_BW_SCALE_BITS \
28082 (UINT32_C(0x0) << 28)
28083 /* Value is in bytes. */
28084 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MAX_BW_SCALE_BYTES \
28085 (UINT32_C(0x1) << 28)
28086 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MAX_BW_SCALE_LAST \
28087 HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MAX_BW_SCALE_BYTES
28088 /* bw_value_unit is 3 b */
28089 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_MASK \
28090 UINT32_C(0xe0000000)
28091 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_SFT \
28093 /* Value is in Mb or MB (base 10). */
28094 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_MEGA \
28095 (UINT32_C(0x0) << 29)
28096 /* Value is in Kb or KB (base 10). */
28097 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_KILO \
28098 (UINT32_C(0x2) << 29)
28099 /* Value is in bits or bytes. */
28100 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_BASE \
28101 (UINT32_C(0x4) << 29)
28102 /* Value is in Gb or GB (base 10). */
28103 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_GIGA \
28104 (UINT32_C(0x6) << 29)
28105 /* Value is in 1/100th of a percentage of total bandwidth. */
28106 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 \
28107 (UINT32_C(0x1) << 29)
28109 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_INVALID \
28110 (UINT32_C(0x7) << 29)
28111 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_LAST \
28112 HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_INVALID
28113 /* Transmission Selection Algorithm (TSA) for CoS Queue. */
28114 uint8_t queue_id5_tsa_assign;
28115 /* Strict Priority */
28116 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_TSA_ASSIGN_SP \
28118 /* Enhanced Transmission Selection */
28119 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_TSA_ASSIGN_ETS \
28122 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_TSA_ASSIGN_RESERVED_FIRST \
28125 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_TSA_ASSIGN_RESERVED_LAST \
28128 * Priority level for strict priority. Valid only when the
28129 * tsa_assign is 0 - Strict Priority (SP)
28130 * 0..7 - Valid values.
28131 * 8..255 - Reserved.
28133 uint8_t queue_id5_pri_lvl;
28135 * Weight used to allocate remaining BW for this COS after
28136 * servicing guaranteed bandwidths for all COS.
28138 uint8_t queue_id5_bw_weight;
28139 /* ID of CoS Queue 6. */
28142 * Minimum BW allocated to CoS Queue.
28143 * The HWRM will translate this value into byte counter and
28144 * time interval used for this COS inside the device.
28146 uint32_t queue_id6_min_bw;
28147 /* The bandwidth value. */
28148 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MIN_BW_BW_VALUE_MASK \
28149 UINT32_C(0xfffffff)
28150 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MIN_BW_BW_VALUE_SFT \
28152 /* The granularity of the value (bits or bytes). */
28153 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MIN_BW_SCALE \
28154 UINT32_C(0x10000000)
28155 /* Value is in bits. */
28156 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MIN_BW_SCALE_BITS \
28157 (UINT32_C(0x0) << 28)
28158 /* Value is in bytes. */
28159 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MIN_BW_SCALE_BYTES \
28160 (UINT32_C(0x1) << 28)
28161 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MIN_BW_SCALE_LAST \
28162 HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MIN_BW_SCALE_BYTES
28163 /* bw_value_unit is 3 b */
28164 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_MASK \
28165 UINT32_C(0xe0000000)
28166 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_SFT \
28168 /* Value is in Mb or MB (base 10). */
28169 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_MEGA \
28170 (UINT32_C(0x0) << 29)
28171 /* Value is in Kb or KB (base 10). */
28172 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_KILO \
28173 (UINT32_C(0x2) << 29)
28174 /* Value is in bits or bytes. */
28175 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_BASE \
28176 (UINT32_C(0x4) << 29)
28177 /* Value is in Gb or GB (base 10). */
28178 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_GIGA \
28179 (UINT32_C(0x6) << 29)
28180 /* Value is in 1/100th of a percentage of total bandwidth. */
28181 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 \
28182 (UINT32_C(0x1) << 29)
28184 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_INVALID \
28185 (UINT32_C(0x7) << 29)
28186 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_LAST \
28187 HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_INVALID
28189 * Maximum BW allocated to CoS queue.
28190 * The HWRM will translate this value into byte counter and
28191 * time interval used for this COS inside the device.
28193 uint32_t queue_id6_max_bw;
28194 /* The bandwidth value. */
28195 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MAX_BW_BW_VALUE_MASK \
28196 UINT32_C(0xfffffff)
28197 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MAX_BW_BW_VALUE_SFT \
28199 /* The granularity of the value (bits or bytes). */
28200 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MAX_BW_SCALE \
28201 UINT32_C(0x10000000)
28202 /* Value is in bits. */
28203 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MAX_BW_SCALE_BITS \
28204 (UINT32_C(0x0) << 28)
28205 /* Value is in bytes. */
28206 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MAX_BW_SCALE_BYTES \
28207 (UINT32_C(0x1) << 28)
28208 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MAX_BW_SCALE_LAST \
28209 HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MAX_BW_SCALE_BYTES
28210 /* bw_value_unit is 3 b */
28211 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_MASK \
28212 UINT32_C(0xe0000000)
28213 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_SFT \
28215 /* Value is in Mb or MB (base 10). */
28216 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_MEGA \
28217 (UINT32_C(0x0) << 29)
28218 /* Value is in Kb or KB (base 10). */
28219 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_KILO \
28220 (UINT32_C(0x2) << 29)
28221 /* Value is in bits or bytes. */
28222 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_BASE \
28223 (UINT32_C(0x4) << 29)
28224 /* Value is in Gb or GB (base 10). */
28225 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_GIGA \
28226 (UINT32_C(0x6) << 29)
28227 /* Value is in 1/100th of a percentage of total bandwidth. */
28228 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 \
28229 (UINT32_C(0x1) << 29)
28231 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_INVALID \
28232 (UINT32_C(0x7) << 29)
28233 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_LAST \
28234 HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_INVALID
28235 /* Transmission Selection Algorithm (TSA) for CoS Queue. */
28236 uint8_t queue_id6_tsa_assign;
28237 /* Strict Priority */
28238 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_TSA_ASSIGN_SP \
28240 /* Enhanced Transmission Selection */
28241 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_TSA_ASSIGN_ETS \
28244 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_TSA_ASSIGN_RESERVED_FIRST \
28247 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_TSA_ASSIGN_RESERVED_LAST \
28250 * Priority level for strict priority. Valid only when the
28251 * tsa_assign is 0 - Strict Priority (SP)
28252 * 0..7 - Valid values.
28253 * 8..255 - Reserved.
28255 uint8_t queue_id6_pri_lvl;
28257 * Weight used to allocate remaining BW for this COS after
28258 * servicing guaranteed bandwidths for all COS.
28260 uint8_t queue_id6_bw_weight;
28261 /* ID of CoS Queue 7. */
28264 * Minimum BW allocated to CoS Queue.
28265 * The HWRM will translate this value into byte counter and
28266 * time interval used for this COS inside the device.
28268 uint32_t queue_id7_min_bw;
28269 /* The bandwidth value. */
28270 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MIN_BW_BW_VALUE_MASK \
28271 UINT32_C(0xfffffff)
28272 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MIN_BW_BW_VALUE_SFT \
28274 /* The granularity of the value (bits or bytes). */
28275 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MIN_BW_SCALE \
28276 UINT32_C(0x10000000)
28277 /* Value is in bits. */
28278 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MIN_BW_SCALE_BITS \
28279 (UINT32_C(0x0) << 28)
28280 /* Value is in bytes. */
28281 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MIN_BW_SCALE_BYTES \
28282 (UINT32_C(0x1) << 28)
28283 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MIN_BW_SCALE_LAST \
28284 HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MIN_BW_SCALE_BYTES
28285 /* bw_value_unit is 3 b */
28286 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_MASK \
28287 UINT32_C(0xe0000000)
28288 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_SFT \
28290 /* Value is in Mb or MB (base 10). */
28291 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_MEGA \
28292 (UINT32_C(0x0) << 29)
28293 /* Value is in Kb or KB (base 10). */
28294 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_KILO \
28295 (UINT32_C(0x2) << 29)
28296 /* Value is in bits or bytes. */
28297 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_BASE \
28298 (UINT32_C(0x4) << 29)
28299 /* Value is in Gb or GB (base 10). */
28300 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_GIGA \
28301 (UINT32_C(0x6) << 29)
28302 /* Value is in 1/100th of a percentage of total bandwidth. */
28303 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 \
28304 (UINT32_C(0x1) << 29)
28306 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_INVALID \
28307 (UINT32_C(0x7) << 29)
28308 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_LAST \
28309 HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_INVALID
28311 * Maximum BW allocated to CoS queue.
28312 * The HWRM will translate this value into byte counter and
28313 * time interval used for this COS inside the device.
28315 uint32_t queue_id7_max_bw;
28316 /* The bandwidth value. */
28317 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MAX_BW_BW_VALUE_MASK \
28318 UINT32_C(0xfffffff)
28319 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MAX_BW_BW_VALUE_SFT \
28321 /* The granularity of the value (bits or bytes). */
28322 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MAX_BW_SCALE \
28323 UINT32_C(0x10000000)
28324 /* Value is in bits. */
28325 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MAX_BW_SCALE_BITS \
28326 (UINT32_C(0x0) << 28)
28327 /* Value is in bytes. */
28328 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MAX_BW_SCALE_BYTES \
28329 (UINT32_C(0x1) << 28)
28330 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MAX_BW_SCALE_LAST \
28331 HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MAX_BW_SCALE_BYTES
28332 /* bw_value_unit is 3 b */
28333 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_MASK \
28334 UINT32_C(0xe0000000)
28335 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_SFT \
28337 /* Value is in Mb or MB (base 10). */
28338 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_MEGA \
28339 (UINT32_C(0x0) << 29)
28340 /* Value is in Kb or KB (base 10). */
28341 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_KILO \
28342 (UINT32_C(0x2) << 29)
28343 /* Value is in bits or bytes. */
28344 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_BASE \
28345 (UINT32_C(0x4) << 29)
28346 /* Value is in Gb or GB (base 10). */
28347 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_GIGA \
28348 (UINT32_C(0x6) << 29)
28349 /* Value is in 1/100th of a percentage of total bandwidth. */
28350 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 \
28351 (UINT32_C(0x1) << 29)
28353 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_INVALID \
28354 (UINT32_C(0x7) << 29)
28355 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_LAST \
28356 HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_INVALID
28357 /* Transmission Selection Algorithm (TSA) for CoS Queue. */
28358 uint8_t queue_id7_tsa_assign;
28359 /* Strict Priority */
28360 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_TSA_ASSIGN_SP \
28362 /* Enhanced Transmission Selection */
28363 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_TSA_ASSIGN_ETS \
28366 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_TSA_ASSIGN_RESERVED_FIRST \
28369 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_TSA_ASSIGN_RESERVED_LAST \
28372 * Priority level for strict priority. Valid only when the
28373 * tsa_assign is 0 - Strict Priority (SP)
28374 * 0..7 - Valid values.
28375 * 8..255 - Reserved.
28377 uint8_t queue_id7_pri_lvl;
28379 * Weight used to allocate remaining BW for this COS after
28380 * servicing guaranteed bandwidths for all COS.
28382 uint8_t queue_id7_bw_weight;
28383 uint8_t unused_1[5];
28386 /* hwrm_queue_cos2bw_cfg_output (size:128b/16B) */
28387 struct hwrm_queue_cos2bw_cfg_output {
28388 /* The specific error status for the command. */
28389 uint16_t error_code;
28390 /* The HWRM command request type. */
28392 /* The sequence ID from the original command. */
28394 /* The length of the response data in number of bytes. */
28396 uint8_t unused_0[7];
28398 * This field is used in Output records to indicate that the output
28399 * is completely written to RAM. This field should be read as '1'
28400 * to indicate that the output has been completely written.
28401 * When writing a command completion or response to an internal processor,
28402 * the order of writes has to be such that this field is written last.
28407 /*************************
28408 * hwrm_queue_dscp_qcaps *
28409 *************************/
28412 /* hwrm_queue_dscp_qcaps_input (size:192b/24B) */
28413 struct hwrm_queue_dscp_qcaps_input {
28414 /* The HWRM command request type. */
28417 * The completion ring to send the completion event on. This should
28418 * be the NQ ID returned from the `nq_alloc` HWRM command.
28420 uint16_t cmpl_ring;
28422 * The sequence ID is used by the driver for tracking multiple
28423 * commands. This ID is treated as opaque data by the firmware and
28424 * the value is returned in the `hwrm_resp_hdr` upon completion.
28428 * The target ID of the command:
28429 * * 0x0-0xFFF8 - The function ID
28430 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
28431 * * 0xFFFD - Reserved for user-space HWRM interface
28434 uint16_t target_id;
28436 * A physical address pointer pointing to a host buffer that the
28437 * command's response data will be written. This can be either a host
28438 * physical address (HPA) or a guest physical address (GPA) and must
28439 * point to a physically contiguous block of memory.
28441 uint64_t resp_addr;
28443 * Port ID of port for which the table is being configured.
28444 * The HWRM needs to check whether this function is allowed
28445 * to configure pri2cos mapping on this port.
28448 uint8_t unused_0[7];
28451 /* hwrm_queue_dscp_qcaps_output (size:128b/16B) */
28452 struct hwrm_queue_dscp_qcaps_output {
28453 /* The specific error status for the command. */
28454 uint16_t error_code;
28455 /* The HWRM command request type. */
28457 /* The sequence ID from the original command. */
28459 /* The length of the response data in number of bytes. */
28461 /* The number of bits provided by the hardware for the DSCP value. */
28462 uint8_t num_dscp_bits;
28464 /* Max number of DSCP-MASK-PRI entries supported. */
28465 uint16_t max_entries;
28466 uint8_t unused_1[3];
28468 * This field is used in Output records to indicate that the output
28469 * is completely written to RAM. This field should be read as '1'
28470 * to indicate that the output has been completely written.
28471 * When writing a command completion or response to an internal processor,
28472 * the order of writes has to be such that this field is written last.
28477 /****************************
28478 * hwrm_queue_dscp2pri_qcfg *
28479 ****************************/
28482 /* hwrm_queue_dscp2pri_qcfg_input (size:256b/32B) */
28483 struct hwrm_queue_dscp2pri_qcfg_input {
28484 /* The HWRM command request type. */
28487 * The completion ring to send the completion event on. This should
28488 * be the NQ ID returned from the `nq_alloc` HWRM command.
28490 uint16_t cmpl_ring;
28492 * The sequence ID is used by the driver for tracking multiple
28493 * commands. This ID is treated as opaque data by the firmware and
28494 * the value is returned in the `hwrm_resp_hdr` upon completion.
28498 * The target ID of the command:
28499 * * 0x0-0xFFF8 - The function ID
28500 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
28501 * * 0xFFFD - Reserved for user-space HWRM interface
28504 uint16_t target_id;
28506 * A physical address pointer pointing to a host buffer that the
28507 * command's response data will be written. This can be either a host
28508 * physical address (HPA) or a guest physical address (GPA) and must
28509 * point to a physically contiguous block of memory.
28511 uint64_t resp_addr;
28513 * This is the host address where the 24-bits DSCP-MASK-PRI
28514 * tuple(s) will be copied to.
28516 uint64_t dest_data_addr;
28518 * Port ID of port for which the table is being configured.
28519 * The HWRM needs to check whether this function is allowed
28520 * to configure pri2cos mapping on this port.
28524 /* Size of the buffer pointed to by dest_data_addr. */
28525 uint16_t dest_data_buffer_size;
28526 uint8_t unused_1[4];
28529 /* hwrm_queue_dscp2pri_qcfg_output (size:128b/16B) */
28530 struct hwrm_queue_dscp2pri_qcfg_output {
28531 /* The specific error status for the command. */
28532 uint16_t error_code;
28533 /* The HWRM command request type. */
28535 /* The sequence ID from the original command. */
28537 /* The length of the response data in number of bytes. */
28540 * A count of the number of DSCP-MASK-PRI tuple(s) pointed to
28541 * by the dest_data_addr.
28543 uint16_t entry_cnt;
28545 * This is the default PRI which un-initialized DSCP values are
28548 uint8_t default_pri;
28549 uint8_t unused_0[4];
28551 * This field is used in Output records to indicate that the output
28552 * is completely written to RAM. This field should be read as '1'
28553 * to indicate that the output has been completely written.
28554 * When writing a command completion or response to an internal processor,
28555 * the order of writes has to be such that this field is written last.
28560 /***************************
28561 * hwrm_queue_dscp2pri_cfg *
28562 ***************************/
28565 /* hwrm_queue_dscp2pri_cfg_input (size:320b/40B) */
28566 struct hwrm_queue_dscp2pri_cfg_input {
28567 /* The HWRM command request type. */
28570 * The completion ring to send the completion event on. This should
28571 * be the NQ ID returned from the `nq_alloc` HWRM command.
28573 uint16_t cmpl_ring;
28575 * The sequence ID is used by the driver for tracking multiple
28576 * commands. This ID is treated as opaque data by the firmware and
28577 * the value is returned in the `hwrm_resp_hdr` upon completion.
28581 * The target ID of the command:
28582 * * 0x0-0xFFF8 - The function ID
28583 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
28584 * * 0xFFFD - Reserved for user-space HWRM interface
28587 uint16_t target_id;
28589 * A physical address pointer pointing to a host buffer that the
28590 * command's response data will be written. This can be either a host
28591 * physical address (HPA) or a guest physical address (GPA) and must
28592 * point to a physically contiguous block of memory.
28594 uint64_t resp_addr;
28596 * This is the host address where the 24-bits DSCP-MASK-PRI tuple
28597 * will be copied from.
28599 uint64_t src_data_addr;
28601 /* use_hw_default_pri is 1 b */
28602 #define HWRM_QUEUE_DSCP2PRI_CFG_INPUT_FLAGS_USE_HW_DEFAULT_PRI \
28606 * This bit must be '1' for the default_pri field to be
28609 #define HWRM_QUEUE_DSCP2PRI_CFG_INPUT_ENABLES_DEFAULT_PRI \
28612 * Port ID of port for which the table is being configured.
28613 * The HWRM needs to check whether this function is allowed
28614 * to configure pri2cos mapping on this port.
28618 * This is the default PRI which un-initialized DSCP values will be
28621 uint8_t default_pri;
28623 * A count of the number of DSCP-MASK-PRI tuple(s) in the data pointed
28624 * to by src_data_addr.
28626 uint16_t entry_cnt;
28627 uint8_t unused_0[4];
28630 /* hwrm_queue_dscp2pri_cfg_output (size:128b/16B) */
28631 struct hwrm_queue_dscp2pri_cfg_output {
28632 /* The specific error status for the command. */
28633 uint16_t error_code;
28634 /* The HWRM command request type. */
28636 /* The sequence ID from the original command. */
28638 /* The length of the response data in number of bytes. */
28640 uint8_t unused_0[7];
28642 * This field is used in Output records to indicate that the output
28643 * is completely written to RAM. This field should be read as '1'
28644 * to indicate that the output has been completely written.
28645 * When writing a command completion or response to an internal processor,
28646 * the order of writes has to be such that this field is written last.
28651 /*************************
28652 * hwrm_queue_mpls_qcaps *
28653 *************************/
28656 /* hwrm_queue_mpls_qcaps_input (size:192b/24B) */
28657 struct hwrm_queue_mpls_qcaps_input {
28658 /* The HWRM command request type. */
28661 * The completion ring to send the completion event on. This should
28662 * be the NQ ID returned from the `nq_alloc` HWRM command.
28664 uint16_t cmpl_ring;
28666 * The sequence ID is used by the driver for tracking multiple
28667 * commands. This ID is treated as opaque data by the firmware and
28668 * the value is returned in the `hwrm_resp_hdr` upon completion.
28672 * The target ID of the command:
28673 * * 0x0-0xFFF8 - The function ID
28674 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
28675 * * 0xFFFD - Reserved for user-space HWRM interface
28678 uint16_t target_id;
28680 * A physical address pointer pointing to a host buffer that the
28681 * command's response data will be written. This can be either a host
28682 * physical address (HPA) or a guest physical address (GPA) and must
28683 * point to a physically contiguous block of memory.
28685 uint64_t resp_addr;
28687 * Port ID of port for which the table is being configured.
28688 * The HWRM needs to check whether this function is allowed
28689 * to configure MPLS TC(EXP) to pri mapping on this port.
28692 uint8_t unused_0[7];
28695 /* hwrm_queue_mpls_qcaps_output (size:128b/16B) */
28696 struct hwrm_queue_mpls_qcaps_output {
28697 /* The specific error status for the command. */
28698 uint16_t error_code;
28699 /* The HWRM command request type. */
28701 /* The sequence ID from the original command. */
28703 /* The length of the response data in number of bytes. */
28706 * Bitmask indicating which queues can be configured by the
28707 * hwrm_queue_mplstc2pri_cfg command.
28709 * Each bit represents a specific pri where bit 0 represents
28710 * pri 0 and bit 7 represents pri 7.
28711 * # A value of 0 indicates that the pri is not configurable
28712 * by the hwrm_queue_mplstc2pri_cfg command.
28713 * # A value of 1 indicates that the pri is configurable.
28714 * # A hwrm_queue_mplstc2pri_cfg command shall return error when
28715 * trying to configure a pri that is not configurable.
28717 uint8_t queue_mplstc2pri_cfg_allowed;
28719 * This is the default PRI which un-initialized MPLS values will be
28722 uint8_t hw_default_pri;
28723 uint8_t unused_0[5];
28725 * This field is used in Output records to indicate that the output
28726 * is completely written to RAM. This field should be read as '1'
28727 * to indicate that the output has been completely written.
28728 * When writing a command completion or response to an internal processor,
28729 * the order of writes has to be such that this field is written last.
28734 /******************************
28735 * hwrm_queue_mplstc2pri_qcfg *
28736 ******************************/
28739 /* hwrm_queue_mplstc2pri_qcfg_input (size:192b/24B) */
28740 struct hwrm_queue_mplstc2pri_qcfg_input {
28741 /* The HWRM command request type. */
28744 * The completion ring to send the completion event on. This should
28745 * be the NQ ID returned from the `nq_alloc` HWRM command.
28747 uint16_t cmpl_ring;
28749 * The sequence ID is used by the driver for tracking multiple
28750 * commands. This ID is treated as opaque data by the firmware and
28751 * the value is returned in the `hwrm_resp_hdr` upon completion.
28755 * The target ID of the command:
28756 * * 0x0-0xFFF8 - The function ID
28757 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
28758 * * 0xFFFD - Reserved for user-space HWRM interface
28761 uint16_t target_id;
28763 * A physical address pointer pointing to a host buffer that the
28764 * command's response data will be written. This can be either a host
28765 * physical address (HPA) or a guest physical address (GPA) and must
28766 * point to a physically contiguous block of memory.
28768 uint64_t resp_addr;
28770 * Port ID of port for which the table is being configured.
28771 * The HWRM needs to check whether this function is allowed
28772 * to configure MPLS TC(EXP) to pri mapping on this port.
28775 uint8_t unused_0[7];
28778 /* hwrm_queue_mplstc2pri_qcfg_output (size:192b/24B) */
28779 struct hwrm_queue_mplstc2pri_qcfg_output {
28780 /* The specific error status for the command. */
28781 uint16_t error_code;
28782 /* The HWRM command request type. */
28784 /* The sequence ID from the original command. */
28786 /* The length of the response data in number of bytes. */
28789 * pri assigned to MPLS TC(EXP) 0. This value can only be changed
28790 * before traffic has started.
28791 * A value of 0xff indicates that no pri is assigned to the
28794 uint8_t tc0_pri_queue_id;
28796 * pri assigned to MPLS TC(EXP) 1. This value can only be changed
28797 * before traffic has started.
28798 * A value of 0xff indicates that no pri is assigned to the
28801 uint8_t tc1_pri_queue_id;
28803 * pri assigned to MPLS TC(EXP) 2. This value can only be changed
28804 * before traffic has started.
28805 * A value of 0xff indicates that no pri is assigned to the
28808 uint8_t tc2_pri_queue_id;
28810 * pri assigned to MPLS TC(EXP) 3. This value can only be changed
28811 * before traffic has started.
28812 * A value of 0xff indicates that no pri is assigned to the
28815 uint8_t tc3_pri_queue_id;
28817 * pri assigned to MPLS TC(EXP) 4. This value can only be changed
28818 * before traffic has started.
28819 * A value of 0xff indicates that no pri is assigned to the
28822 uint8_t tc4_pri_queue_id;
28824 * pri assigned to MPLS TC(EXP) 5. This value can only be changed
28825 * before traffic has started.
28826 * A value of 0xff indicates that no pri is assigned to the
28829 uint8_t tc5_pri_queue_id;
28831 * pri assigned to MPLS TC(EXP) 6. This value can only
28832 * be changed before traffic has started.
28833 * A value of 0xff indicates that no pri is assigned to the
28836 uint8_t tc6_pri_queue_id;
28838 * pri assigned to MPLS TC(EXP) 7. This value can only
28839 * be changed before traffic has started.
28840 * A value of 0xff indicates that no pri is assigned to the
28843 uint8_t tc7_pri_queue_id;
28844 uint8_t unused_0[7];
28846 * This field is used in Output records to indicate that the output
28847 * is completely written to RAM. This field should be read as '1'
28848 * to indicate that the output has been completely written.
28849 * When writing a command completion or response to an internal processor,
28850 * the order of writes has to be such that this field is written last.
28855 /*****************************
28856 * hwrm_queue_mplstc2pri_cfg *
28857 *****************************/
28860 /* hwrm_queue_mplstc2pri_cfg_input (size:256b/32B) */
28861 struct hwrm_queue_mplstc2pri_cfg_input {
28862 /* The HWRM command request type. */
28865 * The completion ring to send the completion event on. This should
28866 * be the NQ ID returned from the `nq_alloc` HWRM command.
28868 uint16_t cmpl_ring;
28870 * The sequence ID is used by the driver for tracking multiple
28871 * commands. This ID is treated as opaque data by the firmware and
28872 * the value is returned in the `hwrm_resp_hdr` upon completion.
28876 * The target ID of the command:
28877 * * 0x0-0xFFF8 - The function ID
28878 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
28879 * * 0xFFFD - Reserved for user-space HWRM interface
28882 uint16_t target_id;
28884 * A physical address pointer pointing to a host buffer that the
28885 * command's response data will be written. This can be either a host
28886 * physical address (HPA) or a guest physical address (GPA) and must
28887 * point to a physically contiguous block of memory.
28889 uint64_t resp_addr;
28892 * This bit must be '1' for the mplstc0_pri_queue_id field to be
28895 #define HWRM_QUEUE_MPLSTC2PRI_CFG_INPUT_ENABLES_TC0_PRI_QUEUE_ID \
28898 * This bit must be '1' for the mplstc1_pri_queue_id field to be
28901 #define HWRM_QUEUE_MPLSTC2PRI_CFG_INPUT_ENABLES_TC1_PRI_QUEUE_ID \
28904 * This bit must be '1' for the mplstc2_pri_queue_id field to be
28907 #define HWRM_QUEUE_MPLSTC2PRI_CFG_INPUT_ENABLES_TC2_PRI_QUEUE_ID \
28910 * This bit must be '1' for the mplstc3_pri_queue_id field to be
28913 #define HWRM_QUEUE_MPLSTC2PRI_CFG_INPUT_ENABLES_TC3_PRI_QUEUE_ID \
28916 * This bit must be '1' for the mplstc4_pri_queue_id field to be
28919 #define HWRM_QUEUE_MPLSTC2PRI_CFG_INPUT_ENABLES_TC4_PRI_QUEUE_ID \
28922 * This bit must be '1' for the mplstc5_pri_queue_id field to be
28925 #define HWRM_QUEUE_MPLSTC2PRI_CFG_INPUT_ENABLES_TC5_PRI_QUEUE_ID \
28928 * This bit must be '1' for the mplstc6_pri_queue_id field to be
28931 #define HWRM_QUEUE_MPLSTC2PRI_CFG_INPUT_ENABLES_TC6_PRI_QUEUE_ID \
28934 * This bit must be '1' for the mplstc7_pri_queue_id field to be
28937 #define HWRM_QUEUE_MPLSTC2PRI_CFG_INPUT_ENABLES_TC7_PRI_QUEUE_ID \
28940 * Port ID of port for which the table is being configured.
28941 * The HWRM needs to check whether this function is allowed
28942 * to configure MPLS TC(EXP)to pri mapping on this port.
28945 uint8_t unused_0[3];
28947 * pri assigned to MPLS TC(EXP) 0. This value can only
28948 * be changed before traffic has started.
28950 uint8_t tc0_pri_queue_id;
28952 * pri assigned to MPLS TC(EXP) 1. This value can only
28953 * be changed before traffic has started.
28955 uint8_t tc1_pri_queue_id;
28957 * pri assigned to MPLS TC(EXP) 2 This value can only
28958 * be changed before traffic has started.
28960 uint8_t tc2_pri_queue_id;
28962 * pri assigned to MPLS TC(EXP) 3. This value can only
28963 * be changed before traffic has started.
28965 uint8_t tc3_pri_queue_id;
28967 * pri assigned to MPLS TC(EXP) 4. This value can only
28968 * be changed before traffic has started.
28970 uint8_t tc4_pri_queue_id;
28972 * pri assigned to MPLS TC(EXP) 5. This value can only
28973 * be changed before traffic has started.
28975 uint8_t tc5_pri_queue_id;
28977 * pri assigned to MPLS TC(EXP) 6. This value can only
28978 * be changed before traffic has started.
28980 uint8_t tc6_pri_queue_id;
28982 * pri assigned to MPLS TC(EXP) 7. This value can only
28983 * be changed before traffic has started.
28985 uint8_t tc7_pri_queue_id;
28988 /* hwrm_queue_mplstc2pri_cfg_output (size:128b/16B) */
28989 struct hwrm_queue_mplstc2pri_cfg_output {
28990 /* The specific error status for the command. */
28991 uint16_t error_code;
28992 /* The HWRM command request type. */
28994 /* The sequence ID from the original command. */
28996 /* The length of the response data in number of bytes. */
28998 uint8_t unused_0[7];
29000 * This field is used in Output records to indicate that the output
29001 * is completely written to RAM. This field should be read as '1'
29002 * to indicate that the output has been completely written.
29003 * When writing a command completion or response to an internal processor,
29004 * the order of writes has to be such that this field is written last.
29009 /****************************
29010 * hwrm_queue_vlanpri_qcaps *
29011 ****************************/
29014 /* hwrm_queue_vlanpri_qcaps_input (size:192b/24B) */
29015 struct hwrm_queue_vlanpri_qcaps_input {
29016 /* The HWRM command request type. */
29019 * The completion ring to send the completion event on. This should
29020 * be the NQ ID returned from the `nq_alloc` HWRM command.
29022 uint16_t cmpl_ring;
29024 * The sequence ID is used by the driver for tracking multiple
29025 * commands. This ID is treated as opaque data by the firmware and
29026 * the value is returned in the `hwrm_resp_hdr` upon completion.
29030 * The target ID of the command:
29031 * * 0x0-0xFFF8 - The function ID
29032 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
29033 * * 0xFFFD - Reserved for user-space HWRM interface
29036 uint16_t target_id;
29038 * A physical address pointer pointing to a host buffer that the
29039 * command's response data will be written. This can be either a host
29040 * physical address (HPA) or a guest physical address (GPA) and must
29041 * point to a physically contiguous block of memory.
29043 uint64_t resp_addr;
29045 * Port ID of port for which the table is being configured.
29046 * The HWRM needs to check whether this function is allowed
29047 * to configure VLAN priority to user priority mapping on this port.
29050 uint8_t unused_0[7];
29053 /* hwrm_queue_vlanpri_qcaps_output (size:128b/16B) */
29054 struct hwrm_queue_vlanpri_qcaps_output {
29055 /* The specific error status for the command. */
29056 uint16_t error_code;
29057 /* The HWRM command request type. */
29059 /* The sequence ID from the original command. */
29061 /* The length of the response data in number of bytes. */
29064 * This is the default user priority which all VLAN priority values
29065 * are mapped to if there is no VLAN priority to user priority mapping.
29067 uint8_t hw_default_pri;
29068 uint8_t unused_0[6];
29070 * This field is used in Output records to indicate that the output
29071 * is completely written to RAM. This field should be read as '1'
29072 * to indicate that the output has been completely written.
29073 * When writing a command completion or response to an internal processor,
29074 * the order of writes has to be such that this field is written last.
29079 /*******************************
29080 * hwrm_queue_vlanpri2pri_qcfg *
29081 *******************************/
29084 /* hwrm_queue_vlanpri2pri_qcfg_input (size:192b/24B) */
29085 struct hwrm_queue_vlanpri2pri_qcfg_input {
29086 /* The HWRM command request type. */
29089 * The completion ring to send the completion event on. This should
29090 * be the NQ ID returned from the `nq_alloc` HWRM command.
29092 uint16_t cmpl_ring;
29094 * The sequence ID is used by the driver for tracking multiple
29095 * commands. This ID is treated as opaque data by the firmware and
29096 * the value is returned in the `hwrm_resp_hdr` upon completion.
29100 * The target ID of the command:
29101 * * 0x0-0xFFF8 - The function ID
29102 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
29103 * * 0xFFFD - Reserved for user-space HWRM interface
29106 uint16_t target_id;
29108 * A physical address pointer pointing to a host buffer that the
29109 * command's response data will be written. This can be either a host
29110 * physical address (HPA) or a guest physical address (GPA) and must
29111 * point to a physically contiguous block of memory.
29113 uint64_t resp_addr;
29115 * Port ID of port for which the table is being configured.
29116 * The HWRM needs to check whether this function is allowed
29117 * to configure VLAN priority to user priority mapping on this port.
29120 uint8_t unused_0[7];
29123 /* hwrm_queue_vlanpri2pri_qcfg_output (size:192b/24B) */
29124 struct hwrm_queue_vlanpri2pri_qcfg_output {
29125 /* The specific error status for the command. */
29126 uint16_t error_code;
29127 /* The HWRM command request type. */
29129 /* The sequence ID from the original command. */
29131 /* The length of the response data in number of bytes. */
29134 * User priority assigned to VLAN priority 0. A value of 0xff
29135 * indicates that no user priority is assigned. The default user
29136 * priority will be used.
29138 uint8_t vlanpri0_user_pri_id;
29140 * User priority assigned to VLAN priority 1. A value of 0xff
29141 * indicates that no user priority is assigned. The default user
29142 * priority will be used.
29144 uint8_t vlanpri1_user_pri_id;
29146 * User priority assigned to VLAN priority 2. A value of 0xff
29147 * indicates that no user priority is assigned. The default user
29148 * priority will be used.
29150 uint8_t vlanpri2_user_pri_id;
29152 * User priority assigned to VLAN priority 3. A value of 0xff
29153 * indicates that no user priority is assigned. The default user
29154 * priority will be used.
29156 uint8_t vlanpri3_user_pri_id;
29158 * User priority assigned to VLAN priority 4. A value of 0xff
29159 * indicates that no user priority is assigned. The default user
29160 * priority will be used.
29162 uint8_t vlanpri4_user_pri_id;
29164 * User priority assigned to VLAN priority 5. A value of 0xff
29165 * indicates that no user priority is assigned. The default user
29166 * priority will be used.
29168 uint8_t vlanpri5_user_pri_id;
29170 * User priority assigned to VLAN priority 6. A value of 0xff
29171 * indicates that no user priority is assigned. The default user
29172 * priority will be used.
29174 uint8_t vlanpri6_user_pri_id;
29176 * User priority assigned to VLAN priority 7. A value of 0xff
29177 * indicates that no user priority is assigned. The default user
29178 * priority will be used.
29180 uint8_t vlanpri7_user_pri_id;
29181 uint8_t unused_0[7];
29183 * This field is used in Output records to indicate that the output
29184 * is completely written to RAM. This field should be read as '1'
29185 * to indicate that the output has been completely written.
29186 * When writing a command completion or response to an internal processor,
29187 * the order of writes has to be such that this field is written last.
29192 /******************************
29193 * hwrm_queue_vlanpri2pri_cfg *
29194 ******************************/
29197 /* hwrm_queue_vlanpri2pri_cfg_input (size:256b/32B) */
29198 struct hwrm_queue_vlanpri2pri_cfg_input {
29199 /* The HWRM command request type. */
29202 * The completion ring to send the completion event on. This should
29203 * be the NQ ID returned from the `nq_alloc` HWRM command.
29205 uint16_t cmpl_ring;
29207 * The sequence ID is used by the driver for tracking multiple
29208 * commands. This ID is treated as opaque data by the firmware and
29209 * the value is returned in the `hwrm_resp_hdr` upon completion.
29213 * The target ID of the command:
29214 * * 0x0-0xFFF8 - The function ID
29215 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
29216 * * 0xFFFD - Reserved for user-space HWRM interface
29219 uint16_t target_id;
29221 * A physical address pointer pointing to a host buffer that the
29222 * command's response data will be written. This can be either a host
29223 * physical address (HPA) or a guest physical address (GPA) and must
29224 * point to a physically contiguous block of memory.
29226 uint64_t resp_addr;
29229 * This bit must be '1' for the vlanpri0_user_pri_id field to be
29232 #define HWRM_QUEUE_VLANPRI2PRI_CFG_INPUT_ENABLES_VLANPRI0_USER_PRI_ID \
29235 * This bit must be '1' for the vlanpri1_user_pri_id field to be
29238 #define HWRM_QUEUE_VLANPRI2PRI_CFG_INPUT_ENABLES_VLANPRI1_USER_PRI_ID \
29241 * This bit must be '1' for the vlanpri2_user_pri_id field to be
29244 #define HWRM_QUEUE_VLANPRI2PRI_CFG_INPUT_ENABLES_VLANPRI2_USER_PRI_ID \
29247 * This bit must be '1' for the vlanpri3_user_pri_id field to be
29250 #define HWRM_QUEUE_VLANPRI2PRI_CFG_INPUT_ENABLES_VLANPRI3_USER_PRI_ID \
29253 * This bit must be '1' for the vlanpri4_user_pri_id field to be
29256 #define HWRM_QUEUE_VLANPRI2PRI_CFG_INPUT_ENABLES_VLANPRI4_USER_PRI_ID \
29259 * This bit must be '1' for the vlanpri5_user_pri_id field to be
29262 #define HWRM_QUEUE_VLANPRI2PRI_CFG_INPUT_ENABLES_VLANPRI5_USER_PRI_ID \
29265 * This bit must be '1' for the vlanpri6_user_pri_id field to be
29268 #define HWRM_QUEUE_VLANPRI2PRI_CFG_INPUT_ENABLES_VLANPRI6_USER_PRI_ID \
29271 * This bit must be '1' for the vlanpri7_user_pri_id field to be
29274 #define HWRM_QUEUE_VLANPRI2PRI_CFG_INPUT_ENABLES_VLANPRI7_USER_PRI_ID \
29277 * Port ID of port for which the table is being configured.
29278 * The HWRM needs to check whether this function is allowed
29279 * to configure VLAN priority to user priority mapping on this port.
29282 uint8_t unused_0[3];
29284 * User priority assigned to VLAN priority 0. This value can only
29285 * be changed before traffic has started.
29287 uint8_t vlanpri0_user_pri_id;
29289 * User priority assigned to VLAN priority 1. This value can only
29290 * be changed before traffic has started.
29292 uint8_t vlanpri1_user_pri_id;
29294 * User priority assigned to VLAN priority 2. This value can only
29295 * be changed before traffic has started.
29297 uint8_t vlanpri2_user_pri_id;
29299 * User priority assigned to VLAN priority 3. This value can only
29300 * be changed before traffic has started.
29302 uint8_t vlanpri3_user_pri_id;
29304 * User priority assigned to VLAN priority 4. This value can only
29305 * be changed before traffic has started.
29307 uint8_t vlanpri4_user_pri_id;
29309 * User priority assigned to VLAN priority 5. This value can only
29310 * be changed before traffic has started.
29312 uint8_t vlanpri5_user_pri_id;
29314 * User priority assigned to VLAN priority 6. This value can only
29315 * be changed before traffic has started.
29317 uint8_t vlanpri6_user_pri_id;
29319 * User priority assigned to VLAN priority 7. This value can only
29320 * be changed before traffic has started.
29322 uint8_t vlanpri7_user_pri_id;
29325 /* hwrm_queue_vlanpri2pri_cfg_output (size:128b/16B) */
29326 struct hwrm_queue_vlanpri2pri_cfg_output {
29327 /* The specific error status for the command. */
29328 uint16_t error_code;
29329 /* The HWRM command request type. */
29331 /* The sequence ID from the original command. */
29333 /* The length of the response data in number of bytes. */
29335 uint8_t unused_0[7];
29337 * This field is used in Output records to indicate that the output
29338 * is completely written to RAM. This field should be read as '1'
29339 * to indicate that the output has been completely written.
29340 * When writing a command completion or response to an internal processor,
29341 * the order of writes has to be such that this field is written last.
29346 /*******************
29347 * hwrm_vnic_alloc *
29348 *******************/
29351 /* hwrm_vnic_alloc_input (size:192b/24B) */
29352 struct hwrm_vnic_alloc_input {
29353 /* The HWRM command request type. */
29356 * The completion ring to send the completion event on. This should
29357 * be the NQ ID returned from the `nq_alloc` HWRM command.
29359 uint16_t cmpl_ring;
29361 * The sequence ID is used by the driver for tracking multiple
29362 * commands. This ID is treated as opaque data by the firmware and
29363 * the value is returned in the `hwrm_resp_hdr` upon completion.
29367 * The target ID of the command:
29368 * * 0x0-0xFFF8 - The function ID
29369 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
29370 * * 0xFFFD - Reserved for user-space HWRM interface
29373 uint16_t target_id;
29375 * A physical address pointer pointing to a host buffer that the
29376 * command's response data will be written. This can be either a host
29377 * physical address (HPA) or a guest physical address (GPA) and must
29378 * point to a physically contiguous block of memory.
29380 uint64_t resp_addr;
29383 * When this bit is '1', this VNIC is requested to
29384 * be the default VNIC for this function.
29386 #define HWRM_VNIC_ALLOC_INPUT_FLAGS_DEFAULT \
29389 * When this bit is '1', proxy VEE PF is requesting
29390 * allocation of a default VNIC on behalf of virtio-net
29391 * function given in virtio_net_fid field.
29393 #define HWRM_VNIC_ALLOC_INPUT_FLAGS_VIRTIO_NET_FID_VALID \
29396 * Virtio-net function's FID.
29397 * This virtio-net function is requesting allocation of default
29398 * VNIC through proxy VEE PF.
29400 uint16_t virtio_net_fid;
29401 uint8_t unused_0[2];
29404 /* hwrm_vnic_alloc_output (size:128b/16B) */
29405 struct hwrm_vnic_alloc_output {
29406 /* The specific error status for the command. */
29407 uint16_t error_code;
29408 /* The HWRM command request type. */
29410 /* The sequence ID from the original command. */
29412 /* The length of the response data in number of bytes. */
29414 /* Logical vnic ID */
29416 uint8_t unused_0[3];
29418 * This field is used in Output records to indicate that the output
29419 * is completely written to RAM. This field should be read as '1'
29420 * to indicate that the output has been completely written.
29421 * When writing a command completion or response to an internal processor,
29422 * the order of writes has to be such that this field is written last.
29427 /********************
29428 * hwrm_vnic_update *
29429 ********************/
29432 /* hwrm_vnic_update_input (size:256b/32B) */
29433 struct hwrm_vnic_update_input {
29434 /* The HWRM command request type. */
29437 * The completion ring to send the completion event on. This should
29438 * be the NQ ID returned from the `nq_alloc` HWRM command.
29440 uint16_t cmpl_ring;
29442 * The sequence ID is used by the driver for tracking multiple
29443 * commands. This ID is treated as opaque data by the firmware and
29444 * the value is returned in the `hwrm_resp_hdr` upon completion.
29448 * The target ID of the command:
29449 * * 0x0-0xFFF8 - The function ID
29450 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
29451 * * 0xFFFD - Reserved for user-space HWRM interface
29454 uint16_t target_id;
29456 * A physical address pointer pointing to a host buffer that the
29457 * command's response data will be written. This can be either a host
29458 * physical address (HPA) or a guest physical address (GPA) and must
29459 * point to a physically contiguous block of memory.
29461 uint64_t resp_addr;
29462 /* Logical vnic ID */
29466 * This bit must be '1' for the vnic_state field to be
29469 #define HWRM_VNIC_UPDATE_INPUT_ENABLES_VNIC_STATE_VALID \
29472 * This bit must be '1' for the mru field to be
29475 #define HWRM_VNIC_UPDATE_INPUT_ENABLES_MRU_VALID \
29478 * This bit must be '1' for the metadata_format_type field to be
29481 #define HWRM_VNIC_UPDATE_INPUT_ENABLES_METADATA_FORMAT_TYPE_VALID \
29484 * This will update the context variable with the same name if
29485 * the corresponding enable is set.
29487 uint8_t vnic_state;
29488 /* Normal operation state for the VNIC. */
29489 #define HWRM_VNIC_UPDATE_INPUT_VNIC_STATE_NORMAL UINT32_C(0x0)
29490 /* All packets are dropped in this state. */
29491 #define HWRM_VNIC_UPDATE_INPUT_VNIC_STATE_DROP UINT32_C(0x1)
29492 #define HWRM_VNIC_UPDATE_INPUT_VNIC_STATE_LAST \
29493 HWRM_VNIC_UPDATE_INPUT_VNIC_STATE_DROP
29495 * The metadata format type used in all the RX packet completions
29496 * going through this VNIC.
29498 uint8_t metadata_format_type;
29499 /* No metadata information. */
29500 #define HWRM_VNIC_UPDATE_INPUT_METADATA_FORMAT_TYPE_NONE \
29503 * Action record pointer (table_scope[4:0], act_rec_ptr[25:0],
29506 #define HWRM_VNIC_UPDATE_INPUT_METADATA_FORMAT_TYPE_ACT_RECORD_PTR \
29508 /* Tunnel ID (tunnel_id[31:0], vtag[19:0]) */
29509 #define HWRM_VNIC_UPDATE_INPUT_METADATA_FORMAT_TYPE_TUNNEL_ID \
29511 /* Custom header data (updated_chdr_data[31:0], vtag[19:0]) */
29512 #define HWRM_VNIC_UPDATE_INPUT_METADATA_FORMAT_TYPE_CUSTOM_HDR_DATA \
29514 /* Header offsets (hdr_offsets[31:0], vtag[19:0]) */
29515 #define HWRM_VNIC_UPDATE_INPUT_METADATA_FORMAT_TYPE_HDR_OFFSETS \
29517 #define HWRM_VNIC_UPDATE_INPUT_METADATA_FORMAT_TYPE_LAST \
29518 HWRM_VNIC_UPDATE_INPUT_METADATA_FORMAT_TYPE_HDR_OFFSETS
29520 * The maximum receive unit of the vnic.
29521 * Each vnic is associated with a function.
29522 * The vnic mru value overwrites the mru setting of the
29523 * associated function.
29524 * The HWRM shall make sure that vnic mru does not exceed
29525 * the mru of the port the function is associated with.
29528 uint8_t unused_1[4];
29531 /* hwrm_vnic_update_output (size:128b/16B) */
29532 struct hwrm_vnic_update_output {
29533 /* The specific error status for the command. */
29534 uint16_t error_code;
29535 /* The HWRM command request type. */
29537 /* The sequence ID from the original command. */
29539 /* The length of the response data in number of bytes. */
29541 uint8_t unused_0[7];
29543 * This field is used in Output records to indicate that the output
29544 * is completely written to RAM. This field should be read as '1'
29545 * to indicate that the output has been completely written.
29546 * When writing a command completion or response to an internal
29547 * processor, the order of writes has to be such that this field is
29553 /******************
29555 ******************/
29558 /* hwrm_vnic_free_input (size:192b/24B) */
29559 struct hwrm_vnic_free_input {
29560 /* The HWRM command request type. */
29563 * The completion ring to send the completion event on. This should
29564 * be the NQ ID returned from the `nq_alloc` HWRM command.
29566 uint16_t cmpl_ring;
29568 * The sequence ID is used by the driver for tracking multiple
29569 * commands. This ID is treated as opaque data by the firmware and
29570 * the value is returned in the `hwrm_resp_hdr` upon completion.
29574 * The target ID of the command:
29575 * * 0x0-0xFFF8 - The function ID
29576 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
29577 * * 0xFFFD - Reserved for user-space HWRM interface
29580 uint16_t target_id;
29582 * A physical address pointer pointing to a host buffer that the
29583 * command's response data will be written. This can be either a host
29584 * physical address (HPA) or a guest physical address (GPA) and must
29585 * point to a physically contiguous block of memory.
29587 uint64_t resp_addr;
29588 /* Logical vnic ID */
29590 uint8_t unused_0[4];
29593 /* hwrm_vnic_free_output (size:128b/16B) */
29594 struct hwrm_vnic_free_output {
29595 /* The specific error status for the command. */
29596 uint16_t error_code;
29597 /* The HWRM command request type. */
29599 /* The sequence ID from the original command. */
29601 /* The length of the response data in number of bytes. */
29603 uint8_t unused_0[7];
29605 * This field is used in Output records to indicate that the output
29606 * is completely written to RAM. This field should be read as '1'
29607 * to indicate that the output has been completely written.
29608 * When writing a command completion or response to an internal processor,
29609 * the order of writes has to be such that this field is written last.
29619 /* hwrm_vnic_cfg_input (size:384b/48B) */
29620 struct hwrm_vnic_cfg_input {
29621 /* The HWRM command request type. */
29624 * The completion ring to send the completion event on. This should
29625 * be the NQ ID returned from the `nq_alloc` HWRM command.
29627 uint16_t cmpl_ring;
29629 * The sequence ID is used by the driver for tracking multiple
29630 * commands. This ID is treated as opaque data by the firmware and
29631 * the value is returned in the `hwrm_resp_hdr` upon completion.
29635 * The target ID of the command:
29636 * * 0x0-0xFFF8 - The function ID
29637 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
29638 * * 0xFFFD - Reserved for user-space HWRM interface
29641 uint16_t target_id;
29643 * A physical address pointer pointing to a host buffer that the
29644 * command's response data will be written. This can be either a host
29645 * physical address (HPA) or a guest physical address (GPA) and must
29646 * point to a physically contiguous block of memory.
29648 uint64_t resp_addr;
29651 * When this bit is '1', the VNIC is requested to
29652 * be the default VNIC for the function.
29654 #define HWRM_VNIC_CFG_INPUT_FLAGS_DEFAULT \
29657 * When this bit is '1', the VNIC is being configured to
29658 * strip VLAN in the RX path.
29659 * If set to '0', then VLAN stripping is disabled on
29662 #define HWRM_VNIC_CFG_INPUT_FLAGS_VLAN_STRIP_MODE \
29665 * When this bit is '1', the VNIC is being configured to
29666 * buffer receive packets in the hardware until the host
29667 * posts new receive buffers.
29668 * If set to '0', then bd_stall is being configured to be
29669 * disabled on this VNIC.
29671 #define HWRM_VNIC_CFG_INPUT_FLAGS_BD_STALL_MODE \
29674 * When this bit is '1', the VNIC is being configured to
29675 * receive both RoCE and non-RoCE traffic.
29676 * If set to '0', then this VNIC is not configured to be
29677 * operating in dual VNIC mode.
29679 #define HWRM_VNIC_CFG_INPUT_FLAGS_ROCE_DUAL_VNIC_MODE \
29682 * When this flag is set to '1', the VNIC is requested to
29683 * be configured to receive only RoCE traffic.
29684 * If this flag is set to '0', then this flag shall be
29685 * ignored by the HWRM.
29686 * If roce_dual_vnic_mode flag is set to '1'
29687 * or roce_mirroring_capable_vnic_mode flag to 1,
29688 * then the HWRM client shall not set this flag to '1'.
29690 #define HWRM_VNIC_CFG_INPUT_FLAGS_ROCE_ONLY_VNIC_MODE \
29693 * When a VNIC uses one destination ring group for certain
29694 * application (e.g. Receive Flow Steering) where
29695 * exact match is used to direct packets to a VNIC with one
29696 * destination ring group only, there is no need to configure
29697 * RSS indirection table for that VNIC as only one destination
29698 * ring group is used.
29700 * This flag is used to enable a mode where
29701 * RSS is enabled in the VNIC using a RSS context
29702 * for computing RSS hash but the RSS indirection table is
29703 * not configured using hwrm_vnic_rss_cfg.
29705 * If this mode is enabled, then the driver should not program
29706 * RSS indirection table for the RSS context that is used for
29707 * computing RSS hash only.
29709 #define HWRM_VNIC_CFG_INPUT_FLAGS_RSS_DFLT_CR_MODE \
29712 * When this bit is '1', the VNIC is being configured to
29713 * receive both RoCE and non-RoCE traffic, but forward only the
29714 * RoCE traffic further. Also, RoCE traffic can be mirrored to
29717 #define HWRM_VNIC_CFG_INPUT_FLAGS_ROCE_MIRRORING_CAPABLE_VNIC_MODE \
29721 * This bit must be '1' for the dflt_ring_grp field to be
29724 #define HWRM_VNIC_CFG_INPUT_ENABLES_DFLT_RING_GRP \
29727 * This bit must be '1' for the rss_rule field to be
29730 #define HWRM_VNIC_CFG_INPUT_ENABLES_RSS_RULE \
29733 * This bit must be '1' for the cos_rule field to be
29736 #define HWRM_VNIC_CFG_INPUT_ENABLES_COS_RULE \
29739 * This bit must be '1' for the lb_rule field to be
29742 #define HWRM_VNIC_CFG_INPUT_ENABLES_LB_RULE \
29745 * This bit must be '1' for the mru field to be
29748 #define HWRM_VNIC_CFG_INPUT_ENABLES_MRU \
29751 * This bit must be '1' for the default_rx_ring_id field to be
29754 #define HWRM_VNIC_CFG_INPUT_ENABLES_DEFAULT_RX_RING_ID \
29757 * This bit must be '1' for the default_cmpl_ring_id field to be
29760 #define HWRM_VNIC_CFG_INPUT_ENABLES_DEFAULT_CMPL_RING_ID \
29762 /* This bit must be '1' for the queue_id field to be configured. */
29763 #define HWRM_VNIC_CFG_INPUT_ENABLES_QUEUE_ID \
29765 /* This bit must be '1' for the rx_csum_v2_mode field to be configured. */
29766 #define HWRM_VNIC_CFG_INPUT_ENABLES_RX_CSUM_V2_MODE \
29768 /* Logical vnic ID */
29771 * Default Completion ring for the VNIC. This ring will
29772 * be chosen if packet does not match any RSS rules and if
29773 * there is no COS rule.
29775 uint16_t dflt_ring_grp;
29777 * RSS ID for RSS rule/table structure. 0xFF... (All Fs) if
29778 * there is no RSS rule.
29782 * RSS ID for COS rule/table structure. 0xFF... (All Fs) if
29783 * there is no COS rule.
29787 * RSS ID for load balancing rule/table structure.
29788 * 0xFF... (All Fs) if there is no LB rule.
29792 * The maximum receive unit of the vnic.
29793 * Each vnic is associated with a function.
29794 * The vnic mru value overwrites the mru setting of the
29795 * associated function.
29796 * The HWRM shall make sure that vnic mru does not exceed
29797 * the mru of the port the function is associated with.
29801 * Default Rx ring for the VNIC. This ring will
29802 * be chosen if packet does not match any RSS rules.
29803 * The aggregation ring associated with the Rx ring is
29804 * implied based on the Rx ring specified when the
29805 * aggregation ring was allocated.
29807 uint16_t default_rx_ring_id;
29809 * Default completion ring for the VNIC. This ring will
29810 * be chosen if packet does not match any RSS rules.
29812 uint16_t default_cmpl_ring_id;
29814 * When specified, only incoming packets classified to the specified CoS
29815 * queue ID will be arriving on this VNIC. Packet priority to CoS mapping
29816 * rules can be specified using HWRM_QUEUE_PRI2COS_CFG. In this mode,
29817 * ntuple filters with VNIC destination specified are invalid since they
29818 * conflict with the CoS to VNIC steering rules in this mode.
29820 * If this field is not specified, packet to VNIC steering will be
29821 * subject to the standard L2 filter rules and any additional ntuple
29822 * filter rules with destination VNIC specified.
29826 * If the device supports the RX V2 and RX TPA start V2 completion
29827 * records as indicated by the HWRM_VNIC_QCAPS command, this field is
29828 * used to specify the two RX checksum modes supported by these
29829 * completion records.
29831 uint8_t rx_csum_v2_mode;
29833 * When configured with this checksum mode, the number of header
29834 * groups in the delivered packet with a valid IP checksum and
29835 * the number of header groups in the delivered packet with a valid
29836 * L4 checksum are reported. Valid checksums are counted from the
29837 * outermost header group to the innermost header group, stopping at
29838 * the first error. This is the default checksum mode supported if
29839 * the driver doesn't explicitly configure the RX checksum mode.
29841 #define HWRM_VNIC_CFG_INPUT_RX_CSUM_V2_MODE_DEFAULT UINT32_C(0x0)
29843 * When configured with this checksum mode, the checksum status is
29844 * reported using 'all ok' mode. In the RX completion record, one
29845 * bit indicates if the IP checksum is valid for all the parsed
29846 * header groups with an IP checksum. Another bit indicates if the
29847 * L4 checksum is valid for all the parsed header groups with an L4
29848 * checksum. The number of header groups that were parsed by the
29849 * chip and passed in the delivered packet is also reported.
29851 #define HWRM_VNIC_CFG_INPUT_RX_CSUM_V2_MODE_ALL_OK UINT32_C(0x1)
29853 * Any rx_csum_v2_mode value larger than or equal to this is not
29856 #define HWRM_VNIC_CFG_INPUT_RX_CSUM_V2_MODE_MAX UINT32_C(0x2)
29857 #define HWRM_VNIC_CFG_INPUT_RX_CSUM_V2_MODE_LAST \
29858 HWRM_VNIC_CFG_INPUT_RX_CSUM_V2_MODE_MAX
29859 uint8_t unused0[5];
29862 /* hwrm_vnic_cfg_output (size:128b/16B) */
29863 struct hwrm_vnic_cfg_output {
29864 /* The specific error status for the command. */
29865 uint16_t error_code;
29866 /* The HWRM command request type. */
29868 /* The sequence ID from the original command. */
29870 /* The length of the response data in number of bytes. */
29872 uint8_t unused_0[7];
29874 * This field is used in Output records to indicate that the output
29875 * is completely written to RAM. This field should be read as '1'
29876 * to indicate that the output has been completely written.
29877 * When writing a command completion or response to an internal processor,
29878 * the order of writes has to be such that this field is written last.
29883 /******************
29885 ******************/
29888 /* hwrm_vnic_qcfg_input (size:256b/32B) */
29889 struct hwrm_vnic_qcfg_input {
29890 /* The HWRM command request type. */
29893 * The completion ring to send the completion event on. This should
29894 * be the NQ ID returned from the `nq_alloc` HWRM command.
29896 uint16_t cmpl_ring;
29898 * The sequence ID is used by the driver for tracking multiple
29899 * commands. This ID is treated as opaque data by the firmware and
29900 * the value is returned in the `hwrm_resp_hdr` upon completion.
29904 * The target ID of the command:
29905 * * 0x0-0xFFF8 - The function ID
29906 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
29907 * * 0xFFFD - Reserved for user-space HWRM interface
29910 uint16_t target_id;
29912 * A physical address pointer pointing to a host buffer that the
29913 * command's response data will be written. This can be either a host
29914 * physical address (HPA) or a guest physical address (GPA) and must
29915 * point to a physically contiguous block of memory.
29917 uint64_t resp_addr;
29920 * This bit must be '1' for the vf_id_valid field to be
29923 #define HWRM_VNIC_QCFG_INPUT_ENABLES_VF_ID_VALID UINT32_C(0x1)
29924 /* Logical vnic ID */
29926 /* ID of Virtual Function whose VNIC resource is being queried. */
29928 uint8_t unused_0[6];
29931 /* hwrm_vnic_qcfg_output (size:256b/32B) */
29932 struct hwrm_vnic_qcfg_output {
29933 /* The specific error status for the command. */
29934 uint16_t error_code;
29935 /* The HWRM command request type. */
29937 /* The sequence ID from the original command. */
29939 /* The length of the response data in number of bytes. */
29941 /* Default Completion ring for the VNIC. */
29942 uint16_t dflt_ring_grp;
29944 * RSS ID for RSS rule/table structure. 0xFF... (All Fs) if
29945 * there is no RSS rule.
29949 * RSS ID for COS rule/table structure. 0xFF... (All Fs) if
29950 * there is no COS rule.
29954 * RSS ID for load balancing rule/table structure.
29955 * 0xFF... (All Fs) if there is no LB rule.
29958 /* The maximum receive unit of the vnic. */
29960 uint8_t unused_0[2];
29963 * When this bit is '1', the VNIC is the default VNIC for
29966 #define HWRM_VNIC_QCFG_OUTPUT_FLAGS_DEFAULT \
29969 * When this bit is '1', the VNIC is configured to
29970 * strip VLAN in the RX path.
29971 * If set to '0', then VLAN stripping is disabled on
29974 #define HWRM_VNIC_QCFG_OUTPUT_FLAGS_VLAN_STRIP_MODE \
29977 * When this bit is '1', the VNIC is configured to
29978 * buffer receive packets in the hardware until the host
29979 * posts new receive buffers.
29980 * If set to '0', then bd_stall is disabled on
29983 #define HWRM_VNIC_QCFG_OUTPUT_FLAGS_BD_STALL_MODE \
29986 * When this bit is '1', the VNIC is configured to
29987 * receive both RoCE and non-RoCE traffic.
29988 * If set to '0', then this VNIC is not configured to
29989 * operate in dual VNIC mode.
29991 #define HWRM_VNIC_QCFG_OUTPUT_FLAGS_ROCE_DUAL_VNIC_MODE \
29994 * When this flag is set to '1', the VNIC is configured to
29995 * receive only RoCE traffic.
29996 * When this flag is set to '0', the VNIC is not configured
29997 * to receive only RoCE traffic.
29998 * If roce_dual_vnic_mode flag and this flag both are set
29999 * to '1', then it is an invalid configuration of the
30000 * VNIC. The HWRM should not allow that type of
30001 * mis-configuration by HWRM clients.
30003 #define HWRM_VNIC_QCFG_OUTPUT_FLAGS_ROCE_ONLY_VNIC_MODE \
30006 * When a VNIC uses one destination ring group for certain
30007 * application (e.g. Receive Flow Steering) where
30008 * exact match is used to direct packets to a VNIC with one
30009 * destination ring group only, there is no need to configure
30010 * RSS indirection table for that VNIC as only one destination
30011 * ring group is used.
30013 * When this bit is set to '1', then the VNIC is enabled in a
30014 * mode where RSS is enabled in the VNIC using a RSS context
30015 * for computing RSS hash but the RSS indirection table is
30018 #define HWRM_VNIC_QCFG_OUTPUT_FLAGS_RSS_DFLT_CR_MODE \
30021 * When this bit is '1', the VNIC is configured to
30022 * receive both RoCE and non-RoCE traffic, but forward only
30023 * RoCE traffic further. Also RoCE traffic can be mirrored to
30026 #define HWRM_VNIC_QCFG_OUTPUT_FLAGS_ROCE_MIRRORING_CAPABLE_VNIC_MODE \
30029 * When this bit is '0', VNIC is in normal operation state.
30030 * When this bit is '1', VNIC drops all the received packets.
30032 #define HWRM_VNIC_QCFG_OUTPUT_FLAGS_OPERATION_STATE \
30035 * When returned with a valid CoS Queue id, the CoS Queue/VNIC association
30036 * is valid. Otherwise it will return 0xFFFF to indicate no VNIC/CoS
30037 * queue association.
30041 * If the device supports the RX V2 and RX TPA start V2 completion
30042 * records as indicated by the HWRM_VNIC_QCAPS command, this field is
30043 * used to specify the current RX checksum mode configured for all the
30044 * RX rings of a VNIC.
30046 uint8_t rx_csum_v2_mode;
30048 * This value indicates that the VNIC is configured to use the
30049 * default RX checksum mode for all the rings associated with this
30052 #define HWRM_VNIC_QCFG_OUTPUT_RX_CSUM_V2_MODE_DEFAULT UINT32_C(0x0)
30054 * This value indicates that the VNIC is configured to use the RX
30055 * checksum ‘all_ok’ mode for all the rings associated with this
30058 #define HWRM_VNIC_QCFG_OUTPUT_RX_CSUM_V2_MODE_ALL_OK UINT32_C(0x1)
30060 * Any rx_csum_v2_mode value larger than or equal to this is not
30063 #define HWRM_VNIC_QCFG_OUTPUT_RX_CSUM_V2_MODE_MAX UINT32_C(0x2)
30064 #define HWRM_VNIC_QCFG_OUTPUT_RX_CSUM_V2_MODE_LAST \
30065 HWRM_VNIC_QCFG_OUTPUT_RX_CSUM_V2_MODE_MAX
30066 uint8_t unused_1[4];
30068 * This field is used in Output records to indicate that the output
30069 * is completely written to RAM. This field should be read as '1'
30070 * to indicate that the output has been completely written.
30071 * When writing a command completion or response to an internal processor,
30072 * the order of writes has to be such that this field is written last.
30077 /*******************
30078 * hwrm_vnic_qcaps *
30079 *******************/
30082 /* hwrm_vnic_qcaps_input (size:192b/24B) */
30083 struct hwrm_vnic_qcaps_input {
30084 /* The HWRM command request type. */
30087 * The completion ring to send the completion event on. This should
30088 * be the NQ ID returned from the `nq_alloc` HWRM command.
30090 uint16_t cmpl_ring;
30092 * The sequence ID is used by the driver for tracking multiple
30093 * commands. This ID is treated as opaque data by the firmware and
30094 * the value is returned in the `hwrm_resp_hdr` upon completion.
30098 * The target ID of the command:
30099 * * 0x0-0xFFF8 - The function ID
30100 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
30101 * * 0xFFFD - Reserved for user-space HWRM interface
30104 uint16_t target_id;
30106 * A physical address pointer pointing to a host buffer that the
30107 * command's response data will be written. This can be either a host
30108 * physical address (HPA) or a guest physical address (GPA) and must
30109 * point to a physically contiguous block of memory.
30111 uint64_t resp_addr;
30113 uint8_t unused_0[4];
30116 /* hwrm_vnic_qcaps_output (size:192b/24B) */
30117 struct hwrm_vnic_qcaps_output {
30118 /* The specific error status for the command. */
30119 uint16_t error_code;
30120 /* The HWRM command request type. */
30122 /* The sequence ID from the original command. */
30124 /* The length of the response data in number of bytes. */
30126 /* The maximum receive unit that is settable on a vnic. */
30128 uint8_t unused_0[2];
30131 #define HWRM_VNIC_QCAPS_OUTPUT_FLAGS_UNUSED \
30134 * When this bit is '1', the capability of stripping VLAN in
30135 * the RX path is supported on VNIC(s).
30136 * If set to '0', then VLAN stripping capability is
30137 * not supported on VNIC(s).
30139 #define HWRM_VNIC_QCAPS_OUTPUT_FLAGS_VLAN_STRIP_CAP \
30142 * When this bit is '1', the capability to buffer receive
30143 * packets in the hardware until the host posts new receive buffers
30144 * is supported on VNIC(s).
30145 * If set to '0', then bd_stall capability is not supported
30148 #define HWRM_VNIC_QCAPS_OUTPUT_FLAGS_BD_STALL_CAP \
30151 * When this bit is '1', the capability to
30152 * receive both RoCE and non-RoCE traffic on VNIC(s) is
30154 * If set to '0', then the capability to receive
30155 * both RoCE and non-RoCE traffic on VNIC(s) is
30158 #define HWRM_VNIC_QCAPS_OUTPUT_FLAGS_ROCE_DUAL_VNIC_CAP \
30161 * When this bit is set to '1', the capability to configure
30162 * a VNIC to receive only RoCE traffic is supported.
30163 * When this flag is set to '0', the VNIC capability to
30164 * configure to receive only RoCE traffic is not supported.
30166 #define HWRM_VNIC_QCAPS_OUTPUT_FLAGS_ROCE_ONLY_VNIC_CAP \
30169 * When this bit is set to '1', then the capability to enable
30170 * a VNIC in a mode where RSS context without configuring
30171 * RSS indirection table is supported (for RSS hash computation).
30172 * When this bit is set to '0', then a VNIC can not be configured
30173 * with a mode to enable RSS context without configuring RSS
30174 * indirection table.
30176 #define HWRM_VNIC_QCAPS_OUTPUT_FLAGS_RSS_DFLT_CR_CAP \
30179 * When this bit is '1', the capability to
30180 * mirror the the RoCE traffic is supported.
30181 * If set to '0', then the capability to mirror the
30182 * RoCE traffic is not supported.
30184 #define HWRM_VNIC_QCAPS_OUTPUT_FLAGS_ROCE_MIRRORING_CAPABLE_VNIC_CAP \
30187 * When this bit is '1', the outermost RSS hashing capability
30188 * is supported. If set to '0', then the outermost RSS hashing
30189 * capability is not supported.
30191 #define HWRM_VNIC_QCAPS_OUTPUT_FLAGS_OUTERMOST_RSS_CAP \
30194 * When this bit is '1', it indicates that firmware supports the
30195 * ability to steer incoming packets from one CoS queue to one
30196 * VNIC. This optional feature can then be enabled
30197 * using HWRM_VNIC_CFG on any VNIC. This feature is only
30198 * available when NVM option “enable_cos_classfication” is set
30199 * to 1. If set to '0', firmware does not support this feature.
30201 #define HWRM_VNIC_QCAPS_OUTPUT_FLAGS_COS_ASSIGNMENT_CAP \
30204 * When this bit is '1', it indicates that HW and firmware supports
30205 * the use of RX V2 and RX TPA start V2 completion records for all
30206 * the RX rings of a VNIC. Once set, this feature is mandatory to
30207 * be used for the RX rings of the VNIC. Additionally, two new RX
30208 * checksum features supported by these ompletion records can be
30209 * configured using the HWRM_VNIC_CFG on a VNIC. If set to '0', the
30210 * HW and the firmware does not support this feature.
30212 #define HWRM_VNIC_QCAPS_OUTPUT_FLAGS_RX_CMPL_V2_CAP \
30215 * When this bit is '1', it indicates that HW and firmware support
30216 * vnic state change. Host drivers can change the vnic state using
30217 * HWRM_VNIC_UPDATE. If set to '0', the HW and firmware do not
30218 * support this feature.
30220 #define HWRM_VNIC_QCAPS_OUTPUT_FLAGS_VNIC_STATE_CAP \
30223 * When this bit is '1', it indicates that firmware supports
30224 * virtio-net functions default VNIC allocation using
30226 * This capability is available only on Proxy VEE PF. If set to '0',
30227 * firmware does not support this feature.
30229 #define HWRM_VNIC_QCAPS_OUTPUT_FLAGS_VIRTIO_NET_VNIC_ALLOC_CAP \
30232 * When this bit is set '1', then the capability to configure the
30233 * metadata format in the RX completion is supported for the VNIC.
30234 * When this bit is set to '0', then the capability to configure
30235 * the metadata format in the RX completion is not supported for
30238 #define HWRM_VNIC_QCAPS_OUTPUT_FLAGS_METADATA_FORMAT_CAP \
30241 * This field advertises the maximum concurrent TPA aggregations
30242 * supported by the VNIC on new devices that support TPA v2.
30243 * '0' means that TPA v2 is not supported.
30245 uint16_t max_aggs_supported;
30246 uint8_t unused_1[5];
30248 * This field is used in Output records to indicate that the output
30249 * is completely written to RAM. This field should be read as '1'
30250 * to indicate that the output has been completely written.
30251 * When writing a command completion or response to an internal processor,
30252 * the order of writes has to be such that this field is written last.
30257 /*********************
30258 * hwrm_vnic_tpa_cfg *
30259 *********************/
30262 /* hwrm_vnic_tpa_cfg_input (size:320b/40B) */
30263 struct hwrm_vnic_tpa_cfg_input {
30264 /* The HWRM command request type. */
30267 * The completion ring to send the completion event on. This should
30268 * be the NQ ID returned from the `nq_alloc` HWRM command.
30270 uint16_t cmpl_ring;
30272 * The sequence ID is used by the driver for tracking multiple
30273 * commands. This ID is treated as opaque data by the firmware and
30274 * the value is returned in the `hwrm_resp_hdr` upon completion.
30278 * The target ID of the command:
30279 * * 0x0-0xFFF8 - The function ID
30280 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
30281 * * 0xFFFD - Reserved for user-space HWRM interface
30284 uint16_t target_id;
30286 * A physical address pointer pointing to a host buffer that the
30287 * command's response data will be written. This can be either a host
30288 * physical address (HPA) or a guest physical address (GPA) and must
30289 * point to a physically contiguous block of memory.
30291 uint64_t resp_addr;
30294 * When this bit is '1', the VNIC shall be configured to
30295 * perform transparent packet aggregation (TPA) of
30296 * non-tunneled TCP packets.
30298 #define HWRM_VNIC_TPA_CFG_INPUT_FLAGS_TPA \
30301 * When this bit is '1', the VNIC shall be configured to
30302 * perform transparent packet aggregation (TPA) of
30303 * tunneled TCP packets.
30305 #define HWRM_VNIC_TPA_CFG_INPUT_FLAGS_ENCAP_TPA \
30308 * When this bit is '1', the VNIC shall be configured to
30309 * perform transparent packet aggregation (TPA) according
30310 * to Windows Receive Segment Coalescing (RSC) rules.
30312 #define HWRM_VNIC_TPA_CFG_INPUT_FLAGS_RSC_WND_UPDATE \
30315 * When this bit is '1', the VNIC shall be configured to
30316 * perform transparent packet aggregation (TPA) according
30317 * to Linux Generic Receive Offload (GRO) rules.
30319 #define HWRM_VNIC_TPA_CFG_INPUT_FLAGS_GRO \
30322 * When this bit is '1', the VNIC shall be configured to
30323 * perform transparent packet aggregation (TPA) for TCP
30324 * packets with IP ECN set to non-zero.
30326 #define HWRM_VNIC_TPA_CFG_INPUT_FLAGS_AGG_WITH_ECN \
30329 * When this bit is '1', the VNIC shall be configured to
30330 * perform transparent packet aggregation (TPA) for
30331 * GRE tunneled TCP packets only if all packets have the
30332 * same GRE sequence.
30334 #define HWRM_VNIC_TPA_CFG_INPUT_FLAGS_AGG_WITH_SAME_GRE_SEQ \
30337 * When this bit is '1' and the GRO mode is enabled,
30338 * the VNIC shall be configured to
30339 * perform transparent packet aggregation (TPA) for
30340 * TCP/IPv4 packets with consecutively increasing IPIDs.
30341 * In other words, the last packet that is being
30342 * aggregated to an already existing aggregation context
30343 * shall have IPID 1 more than the IPID of the last packet
30344 * that was aggregated in that aggregation context.
30346 #define HWRM_VNIC_TPA_CFG_INPUT_FLAGS_GRO_IPID_CHECK \
30349 * When this bit is '1' and the GRO mode is enabled,
30350 * the VNIC shall be configured to
30351 * perform transparent packet aggregation (TPA) for
30352 * TCP packets with the same TTL (IPv4) or Hop limit (IPv6)
30355 #define HWRM_VNIC_TPA_CFG_INPUT_FLAGS_GRO_TTL_CHECK \
30358 * When this bit is '1' and the GRO mode is enabled,
30359 * the VNIC shall DMA payload data using GRO rules.
30360 * When this bit is '0', the VNIC shall DMA payload data
30361 * using the more efficient LRO rules of filling all
30362 * aggregation buffers.
30364 #define HWRM_VNIC_TPA_CFG_INPUT_FLAGS_AGG_PACK_AS_GRO \
30368 * This bit must be '1' for the max_agg_segs field to be
30371 #define HWRM_VNIC_TPA_CFG_INPUT_ENABLES_MAX_AGG_SEGS UINT32_C(0x1)
30373 * This bit must be '1' for the max_aggs field to be
30376 #define HWRM_VNIC_TPA_CFG_INPUT_ENABLES_MAX_AGGS UINT32_C(0x2)
30378 * This bit must be '1' for the max_agg_timer field to be
30381 #define HWRM_VNIC_TPA_CFG_INPUT_ENABLES_MAX_AGG_TIMER UINT32_C(0x4)
30382 /* deprecated bit. Do not use!!! */
30383 #define HWRM_VNIC_TPA_CFG_INPUT_ENABLES_MIN_AGG_LEN UINT32_C(0x8)
30384 /* Logical vnic ID */
30387 * This is the maximum number of TCP segments that can
30388 * be aggregated (unit is Log2). Max value is 31. On new
30389 * devices supporting TPA v2, the unit is multiples of 4 and
30390 * valid values are > 0 and <= 63.
30392 uint16_t max_agg_segs;
30394 #define HWRM_VNIC_TPA_CFG_INPUT_MAX_AGG_SEGS_1 UINT32_C(0x0)
30396 #define HWRM_VNIC_TPA_CFG_INPUT_MAX_AGG_SEGS_2 UINT32_C(0x1)
30398 #define HWRM_VNIC_TPA_CFG_INPUT_MAX_AGG_SEGS_4 UINT32_C(0x2)
30400 #define HWRM_VNIC_TPA_CFG_INPUT_MAX_AGG_SEGS_8 UINT32_C(0x3)
30401 /* Any segment size larger than this is not valid */
30402 #define HWRM_VNIC_TPA_CFG_INPUT_MAX_AGG_SEGS_MAX UINT32_C(0x1f)
30403 #define HWRM_VNIC_TPA_CFG_INPUT_MAX_AGG_SEGS_LAST \
30404 HWRM_VNIC_TPA_CFG_INPUT_MAX_AGG_SEGS_MAX
30406 * This is the maximum number of aggregations this VNIC is
30407 * allowed (unit is Log2). Max value is 7. On new devices
30408 * supporting TPA v2, this is in unit of 1 and must be > 0
30409 * and <= max_aggs_supported in the hwrm_vnic_qcaps response
30410 * to enable TPA v2.
30413 /* 1 aggregation */
30414 #define HWRM_VNIC_TPA_CFG_INPUT_MAX_AGGS_1 UINT32_C(0x0)
30415 /* 2 aggregations */
30416 #define HWRM_VNIC_TPA_CFG_INPUT_MAX_AGGS_2 UINT32_C(0x1)
30417 /* 4 aggregations */
30418 #define HWRM_VNIC_TPA_CFG_INPUT_MAX_AGGS_4 UINT32_C(0x2)
30419 /* 8 aggregations */
30420 #define HWRM_VNIC_TPA_CFG_INPUT_MAX_AGGS_8 UINT32_C(0x3)
30421 /* 16 aggregations */
30422 #define HWRM_VNIC_TPA_CFG_INPUT_MAX_AGGS_16 UINT32_C(0x4)
30423 /* Any aggregation size larger than this is not valid */
30424 #define HWRM_VNIC_TPA_CFG_INPUT_MAX_AGGS_MAX UINT32_C(0x7)
30425 #define HWRM_VNIC_TPA_CFG_INPUT_MAX_AGGS_LAST \
30426 HWRM_VNIC_TPA_CFG_INPUT_MAX_AGGS_MAX
30427 uint8_t unused_0[2];
30429 * This is the maximum amount of time allowed for
30430 * an aggregation context to complete after it was initiated.
30432 uint32_t max_agg_timer;
30434 * This is the minimum amount of payload length required to
30435 * start an aggregation context. This field is deprecated and
30436 * should be set to 0. The minimum length is set by firmware
30437 * and can be queried using hwrm_vnic_tpa_qcfg.
30439 uint32_t min_agg_len;
30442 /* hwrm_vnic_tpa_cfg_output (size:128b/16B) */
30443 struct hwrm_vnic_tpa_cfg_output {
30444 /* The specific error status for the command. */
30445 uint16_t error_code;
30446 /* The HWRM command request type. */
30448 /* The sequence ID from the original command. */
30450 /* The length of the response data in number of bytes. */
30452 uint8_t unused_0[7];
30454 * This field is used in Output records to indicate that the output
30455 * is completely written to RAM. This field should be read as '1'
30456 * to indicate that the output has been completely written.
30457 * When writing a command completion or response to an internal processor,
30458 * the order of writes has to be such that this field is written last.
30463 /*********************
30464 * hwrm_vnic_rss_cfg *
30465 *********************/
30468 /* hwrm_vnic_rss_cfg_input (size:384b/48B) */
30469 struct hwrm_vnic_rss_cfg_input {
30470 /* The HWRM command request type. */
30473 * The completion ring to send the completion event on. This should
30474 * be the NQ ID returned from the `nq_alloc` HWRM command.
30476 uint16_t cmpl_ring;
30478 * The sequence ID is used by the driver for tracking multiple
30479 * commands. This ID is treated as opaque data by the firmware and
30480 * the value is returned in the `hwrm_resp_hdr` upon completion.
30484 * The target ID of the command:
30485 * * 0x0-0xFFF8 - The function ID
30486 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
30487 * * 0xFFFD - Reserved for user-space HWRM interface
30490 uint16_t target_id;
30492 * A physical address pointer pointing to a host buffer that the
30493 * command's response data will be written. This can be either a host
30494 * physical address (HPA) or a guest physical address (GPA) and must
30495 * point to a physically contiguous block of memory.
30497 uint64_t resp_addr;
30498 uint32_t hash_type;
30500 * When this bit is '1', the RSS hash shall be computed
30501 * over source and destination IPv4 addresses of IPv4
30504 #define HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV4 UINT32_C(0x1)
30506 * When this bit is '1', the RSS hash shall be computed
30507 * over source/destination IPv4 addresses and
30508 * source/destination ports of TCP/IPv4 packets.
30510 #define HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV4 UINT32_C(0x2)
30512 * When this bit is '1', the RSS hash shall be computed
30513 * over source/destination IPv4 addresses and
30514 * source/destination ports of UDP/IPv4 packets.
30516 #define HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV4 UINT32_C(0x4)
30518 * When this bit is '1', the RSS hash shall be computed
30519 * over source and destination IPv4 addresses of IPv6
30522 #define HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV6 UINT32_C(0x8)
30524 * When this bit is '1', the RSS hash shall be computed
30525 * over source/destination IPv6 addresses and
30526 * source/destination ports of TCP/IPv6 packets.
30528 #define HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV6 UINT32_C(0x10)
30530 * When this bit is '1', the RSS hash shall be computed
30531 * over source/destination IPv6 addresses and
30532 * source/destination ports of UDP/IPv6 packets.
30534 #define HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV6 UINT32_C(0x20)
30535 /* VNIC ID of VNIC associated with RSS table being configured. */
30538 * Specifies which VNIC ring table pair to configure.
30539 * Valid values range from 0 to 7.
30541 uint8_t ring_table_pair_index;
30542 /* Flags to specify different RSS hash modes. */
30543 uint8_t hash_mode_flags;
30545 * When this bit is '1', it indicates using current RSS
30546 * hash mode setting configured in the device.
30548 #define HWRM_VNIC_RSS_CFG_INPUT_HASH_MODE_FLAGS_DEFAULT \
30551 * When this bit is '1', it indicates requesting support of
30552 * RSS hashing over innermost 4 tuples {l3.src, l3.dest,
30553 * l4.src, l4.dest} for tunnel packets. For none-tunnel
30554 * packets, the RSS hash is computed over the normal
30555 * src/dest l3 and src/dest l4 headers.
30557 #define HWRM_VNIC_RSS_CFG_INPUT_HASH_MODE_FLAGS_INNERMOST_4 \
30560 * When this bit is '1', it indicates requesting support of
30561 * RSS hashing over innermost 2 tuples {l3.src, l3.dest} for
30562 * tunnel packets. For none-tunnel packets, the RSS hash is
30563 * computed over the normal src/dest l3 headers.
30565 #define HWRM_VNIC_RSS_CFG_INPUT_HASH_MODE_FLAGS_INNERMOST_2 \
30568 * When this bit is '1', it indicates requesting support of
30569 * RSS hashing over outermost 4 tuples {t_l3.src, t_l3.dest,
30570 * t_l4.src, t_l4.dest} for tunnel packets. For none-tunnel
30571 * packets, the RSS hash is computed over the normal
30572 * src/dest l3 and src/dest l4 headers.
30574 #define HWRM_VNIC_RSS_CFG_INPUT_HASH_MODE_FLAGS_OUTERMOST_4 \
30577 * When this bit is '1', it indicates requesting support of
30578 * RSS hashing over outermost 2 tuples {t_l3.src, t_l3.dest} for
30579 * tunnel packets. For none-tunnel packets, the RSS hash is
30580 * computed over the normal src/dest l3 headers.
30582 #define HWRM_VNIC_RSS_CFG_INPUT_HASH_MODE_FLAGS_OUTERMOST_2 \
30584 /* This is the address for rss ring group table */
30585 uint64_t ring_grp_tbl_addr;
30586 /* This is the address for rss hash key table */
30587 uint64_t hash_key_tbl_addr;
30588 /* Index to the rss indirection table. */
30589 uint16_t rss_ctx_idx;
30590 uint8_t unused_1[6];
30593 /* hwrm_vnic_rss_cfg_output (size:128b/16B) */
30594 struct hwrm_vnic_rss_cfg_output {
30595 /* The specific error status for the command. */
30596 uint16_t error_code;
30597 /* The HWRM command request type. */
30599 /* The sequence ID from the original command. */
30601 /* The length of the response data in number of bytes. */
30603 uint8_t unused_0[7];
30605 * This field is used in Output records to indicate that the output
30606 * is completely written to RAM. This field should be read as '1'
30607 * to indicate that the output has been completely written.
30608 * When writing a command completion or response to an internal processor,
30609 * the order of writes has to be such that this field is written last.
30614 /* hwrm_vnic_rss_cfg_cmd_err (size:64b/8B) */
30615 struct hwrm_vnic_rss_cfg_cmd_err {
30617 * command specific error codes that goes to
30618 * the cmd_err field in Common HWRM Error Response.
30621 /* Unknown error */
30622 #define HWRM_VNIC_RSS_CFG_CMD_ERR_CODE_UNKNOWN \
30625 * Unable to change global RSS mode to outer due to all active
30626 * interfaces are not ready to support outer RSS hashing.
30628 #define HWRM_VNIC_RSS_CFG_CMD_ERR_CODE_INTERFACE_NOT_READY \
30630 #define HWRM_VNIC_RSS_CFG_CMD_ERR_CODE_LAST \
30631 HWRM_VNIC_RSS_CFG_CMD_ERR_CODE_INTERFACE_NOT_READY
30632 uint8_t unused_0[7];
30635 /**********************
30636 * hwrm_vnic_rss_qcfg *
30637 **********************/
30640 /* hwrm_vnic_rss_qcfg_input (size:192b/24B) */
30641 struct hwrm_vnic_rss_qcfg_input {
30642 /* The HWRM command request type. */
30645 * The completion ring to send the completion event on. This should
30646 * be the NQ ID returned from the `nq_alloc` HWRM command.
30648 uint16_t cmpl_ring;
30650 * The sequence ID is used by the driver for tracking multiple
30651 * commands. This ID is treated as opaque data by the firmware and
30652 * the value is returned in the `hwrm_resp_hdr` upon completion.
30656 * The target ID of the command:
30657 * * 0x0-0xFFF8 - The function ID
30658 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
30659 * * 0xFFFD - Reserved for user-space HWRM interface
30662 uint16_t target_id;
30664 * A physical address pointer pointing to a host buffer that the
30665 * command's response data will be written. This can be either a host
30666 * physical address (HPA) or a guest physical address (GPA) and must
30667 * point to a physically contiguous block of memory.
30669 uint64_t resp_addr;
30670 /* Index to the rss indirection table. */
30671 uint16_t rss_ctx_idx;
30672 uint8_t unused_0[6];
30675 /* hwrm_vnic_rss_qcfg_output (size:512b/64B) */
30676 struct hwrm_vnic_rss_qcfg_output {
30677 /* The specific error status for the command. */
30678 uint16_t error_code;
30679 /* The HWRM command request type. */
30681 /* The sequence ID from the original command. */
30683 /* The length of the response data in number of bytes. */
30685 uint32_t hash_type;
30687 * When this bit is '1', the RSS hash shall be computed
30688 * over source and destination IPv4 addresses of IPv4
30691 #define HWRM_VNIC_RSS_QCFG_OUTPUT_HASH_TYPE_IPV4 UINT32_C(0x1)
30693 * When this bit is '1', the RSS hash shall be computed
30694 * over source/destination IPv4 addresses and
30695 * source/destination ports of TCP/IPv4 packets.
30697 #define HWRM_VNIC_RSS_QCFG_OUTPUT_HASH_TYPE_TCP_IPV4 UINT32_C(0x2)
30699 * When this bit is '1', the RSS hash shall be computed
30700 * over source/destination IPv4 addresses and
30701 * source/destination ports of UDP/IPv4 packets.
30703 #define HWRM_VNIC_RSS_QCFG_OUTPUT_HASH_TYPE_UDP_IPV4 UINT32_C(0x4)
30705 * When this bit is '1', the RSS hash shall be computed
30706 * over source and destination IPv4 addresses of IPv6
30709 #define HWRM_VNIC_RSS_QCFG_OUTPUT_HASH_TYPE_IPV6 UINT32_C(0x8)
30711 * When this bit is '1', the RSS hash shall be computed
30712 * over source/destination IPv6 addresses and
30713 * source/destination ports of TCP/IPv6 packets.
30715 #define HWRM_VNIC_RSS_QCFG_OUTPUT_HASH_TYPE_TCP_IPV6 UINT32_C(0x10)
30717 * When this bit is '1', the RSS hash shall be computed
30718 * over source/destination IPv6 addresses and
30719 * source/destination ports of UDP/IPv6 packets.
30721 #define HWRM_VNIC_RSS_QCFG_OUTPUT_HASH_TYPE_UDP_IPV6 UINT32_C(0x20)
30722 uint8_t unused_0[4];
30723 /* This is the value of rss hash key */
30724 uint32_t hash_key[10];
30725 /* Flags to specify different RSS hash modes. */
30726 uint8_t hash_mode_flags;
30728 * When this bit is '1', it indicates using current RSS
30729 * hash mode setting configured in the device.
30731 #define HWRM_VNIC_RSS_QCFG_OUTPUT_HASH_MODE_FLAGS_DEFAULT \
30734 * When this bit is '1', it indicates requesting support of
30735 * RSS hashing over innermost 4 tuples {l3.src, l3.dest,
30736 * l4.src, l4.dest} for tunnel packets. For none-tunnel
30737 * packets, the RSS hash is computed over the normal
30738 * src/dest l3 and src/dest l4 headers.
30740 #define HWRM_VNIC_RSS_QCFG_OUTPUT_HASH_MODE_FLAGS_INNERMOST_4 \
30743 * When this bit is '1', it indicates requesting support of
30744 * RSS hashing over innermost 2 tuples {l3.src, l3.dest} for
30745 * tunnel packets. For none-tunnel packets, the RSS hash is
30746 * computed over the normal src/dest l3 headers.
30748 #define HWRM_VNIC_RSS_QCFG_OUTPUT_HASH_MODE_FLAGS_INNERMOST_2 \
30751 * When this bit is '1', it indicates requesting support of
30752 * RSS hashing over outermost 4 tuples {t_l3.src, t_l3.dest,
30753 * t_l4.src, t_l4.dest} for tunnel packets. For none-tunnel
30754 * packets, the RSS hash is computed over the normal
30755 * src/dest l3 and src/dest l4 headers.
30757 #define HWRM_VNIC_RSS_QCFG_OUTPUT_HASH_MODE_FLAGS_OUTERMOST_4 \
30760 * When this bit is '1', it indicates requesting support of
30761 * RSS hashing over outermost 2 tuples {t_l3.src, t_l3.dest} for
30762 * tunnel packets. For none-tunnel packets, the RSS hash is
30763 * computed over the normal src/dest l3 headers.
30765 #define HWRM_VNIC_RSS_QCFG_OUTPUT_HASH_MODE_FLAGS_OUTERMOST_2 \
30767 uint8_t unused_1[6];
30769 * This field is used in Output records to indicate that the output
30770 * is completely written to RAM. This field should be read as '1'
30771 * to indicate that the output has been completely written.
30772 * When writing a command completion or response to an internal processor,
30773 * the order of writes has to be such that this field is written last.
30778 /**************************
30779 * hwrm_vnic_plcmodes_cfg *
30780 **************************/
30783 /* hwrm_vnic_plcmodes_cfg_input (size:320b/40B) */
30784 struct hwrm_vnic_plcmodes_cfg_input {
30785 /* The HWRM command request type. */
30788 * The completion ring to send the completion event on. This should
30789 * be the NQ ID returned from the `nq_alloc` HWRM command.
30791 uint16_t cmpl_ring;
30793 * The sequence ID is used by the driver for tracking multiple
30794 * commands. This ID is treated as opaque data by the firmware and
30795 * the value is returned in the `hwrm_resp_hdr` upon completion.
30799 * The target ID of the command:
30800 * * 0x0-0xFFF8 - The function ID
30801 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
30802 * * 0xFFFD - Reserved for user-space HWRM interface
30805 uint16_t target_id;
30807 * A physical address pointer pointing to a host buffer that the
30808 * command's response data will be written. This can be either a host
30809 * physical address (HPA) or a guest physical address (GPA) and must
30810 * point to a physically contiguous block of memory.
30812 uint64_t resp_addr;
30815 * When this bit is '1', the VNIC shall be configured to
30816 * use regular placement algorithm.
30817 * By default, the regular placement algorithm shall be
30818 * enabled on the VNIC.
30820 #define HWRM_VNIC_PLCMODES_CFG_INPUT_FLAGS_REGULAR_PLACEMENT \
30823 * When this bit is '1', the VNIC shall be configured
30824 * use the jumbo placement algorithm.
30826 #define HWRM_VNIC_PLCMODES_CFG_INPUT_FLAGS_JUMBO_PLACEMENT \
30829 * When this bit is '1', the VNIC shall be configured
30830 * to enable Header-Data split for IPv4 packets according
30831 * to the following rules:
30832 * # If the packet is identified as TCP/IPv4, then the
30833 * packet is split at the beginning of the TCP payload.
30834 * # If the packet is identified as UDP/IPv4, then the
30835 * packet is split at the beginning of UDP payload.
30836 * # If the packet is identified as non-TCP and non-UDP
30837 * IPv4 packet, then the packet is split at the beginning
30838 * of the upper layer protocol header carried in the IPv4
30841 #define HWRM_VNIC_PLCMODES_CFG_INPUT_FLAGS_HDS_IPV4 \
30844 * When this bit is '1', the VNIC shall be configured
30845 * to enable Header-Data split for IPv6 packets according
30846 * to the following rules:
30847 * # If the packet is identified as TCP/IPv6, then the
30848 * packet is split at the beginning of the TCP payload.
30849 * # If the packet is identified as UDP/IPv6, then the
30850 * packet is split at the beginning of UDP payload.
30851 * # If the packet is identified as non-TCP and non-UDP
30852 * IPv6 packet, then the packet is split at the beginning
30853 * of the upper layer protocol header carried in the IPv6
30856 #define HWRM_VNIC_PLCMODES_CFG_INPUT_FLAGS_HDS_IPV6 \
30859 * When this bit is '1', the VNIC shall be configured
30860 * to enable Header-Data split for FCoE packets at the
30861 * beginning of FC payload.
30863 #define HWRM_VNIC_PLCMODES_CFG_INPUT_FLAGS_HDS_FCOE \
30866 * When this bit is '1', the VNIC shall be configured
30867 * to enable Header-Data split for RoCE packets at the
30868 * beginning of RoCE payload (after BTH/GRH headers).
30870 #define HWRM_VNIC_PLCMODES_CFG_INPUT_FLAGS_HDS_ROCE \
30873 * When this bit is '1', the VNIC shall be configured use the virtio
30874 * placement algorithm. This feature can only be configured when
30875 * proxy mode is supported on the function.
30877 #define HWRM_VNIC_PLCMODES_CFG_INPUT_FLAGS_VIRTIO_PLACEMENT \
30881 * This bit must be '1' for the jumbo_thresh_valid field to be
30884 #define HWRM_VNIC_PLCMODES_CFG_INPUT_ENABLES_JUMBO_THRESH_VALID \
30887 * This bit must be '1' for the hds_offset_valid field to be
30890 #define HWRM_VNIC_PLCMODES_CFG_INPUT_ENABLES_HDS_OFFSET_VALID \
30893 * This bit must be '1' for the hds_threshold_valid field to be
30896 #define HWRM_VNIC_PLCMODES_CFG_INPUT_ENABLES_HDS_THRESHOLD_VALID \
30899 * This bit must be '1' for the max_bds_valid field to be
30902 #define HWRM_VNIC_PLCMODES_CFG_INPUT_ENABLES_MAX_BDS_VALID \
30904 /* Logical vnic ID */
30907 * When jumbo placement algorithm is enabled, this value
30908 * is used to determine the threshold for jumbo placement.
30909 * Packets with length larger than this value will be
30910 * placed according to the jumbo placement algorithm.
30912 uint16_t jumbo_thresh;
30914 * This value is used to determine the offset into
30915 * packet buffer where the split data (payload) will be
30916 * placed according to one of HDS placement algorithm.
30918 * The lengths of packet buffers provided for split data
30919 * shall be larger than this value.
30921 uint16_t hds_offset;
30923 * When one of the HDS placement algorithm is enabled, this
30924 * value is used to determine the threshold for HDS
30926 * Packets with length larger than this value will be
30927 * placed according to the HDS placement algorithm.
30928 * This value shall be in multiple of 4 bytes.
30930 uint16_t hds_threshold;
30932 * When virtio placement algorithm is enabled, this
30933 * value is used to determine the the maximum number of BDs
30934 * that can be used to place an Rx Packet.
30935 * If an incoming packet does not fit in the buffers described
30936 * by the max BDs, the packet will be dropped and an error
30937 * will be reported in the completion. Valid values for this
30938 * field are between 1 and 8. If the VNIC uses header-data-
30939 * separation and/or TPA with buffer spanning enabled, valid
30940 * values for this field are between 2 and 8.
30941 * This feature can only be configured when proxy mode is
30942 * supported on the function.
30945 uint8_t unused_0[4];
30948 /* hwrm_vnic_plcmodes_cfg_output (size:128b/16B) */
30949 struct hwrm_vnic_plcmodes_cfg_output {
30950 /* The specific error status for the command. */
30951 uint16_t error_code;
30952 /* The HWRM command request type. */
30954 /* The sequence ID from the original command. */
30956 /* The length of the response data in number of bytes. */
30958 uint8_t unused_0[7];
30960 * This field is used in Output records to indicate that the output
30961 * is completely written to RAM. This field should be read as '1'
30962 * to indicate that the output has been completely written.
30963 * When writing a command completion or response to an internal
30964 * processor, the order of writes has to be such that this field is
30970 /***************************
30971 * hwrm_vnic_plcmodes_qcfg *
30972 ***************************/
30975 /* hwrm_vnic_plcmodes_qcfg_input (size:192b/24B) */
30976 struct hwrm_vnic_plcmodes_qcfg_input {
30977 /* The HWRM command request type. */
30980 * The completion ring to send the completion event on. This should
30981 * be the NQ ID returned from the `nq_alloc` HWRM command.
30983 uint16_t cmpl_ring;
30985 * The sequence ID is used by the driver for tracking multiple
30986 * commands. This ID is treated as opaque data by the firmware and
30987 * the value is returned in the `hwrm_resp_hdr` upon completion.
30991 * The target ID of the command:
30992 * * 0x0-0xFFF8 - The function ID
30993 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
30994 * * 0xFFFD - Reserved for user-space HWRM interface
30997 uint16_t target_id;
30999 * A physical address pointer pointing to a host buffer that the
31000 * command's response data will be written. This can be either a host
31001 * physical address (HPA) or a guest physical address (GPA) and must
31002 * point to a physically contiguous block of memory.
31004 uint64_t resp_addr;
31005 /* Logical vnic ID */
31007 uint8_t unused_0[4];
31010 /* hwrm_vnic_plcmodes_qcfg_output (size:192b/24B) */
31011 struct hwrm_vnic_plcmodes_qcfg_output {
31012 /* The specific error status for the command. */
31013 uint16_t error_code;
31014 /* The HWRM command request type. */
31016 /* The sequence ID from the original command. */
31018 /* The length of the response data in number of bytes. */
31022 * When this bit is '1', the VNIC is configured to
31023 * use regular placement algorithm.
31025 #define HWRM_VNIC_PLCMODES_QCFG_OUTPUT_FLAGS_REGULAR_PLACEMENT \
31028 * When this bit is '1', the VNIC is configured to
31029 * use the jumbo placement algorithm.
31031 #define HWRM_VNIC_PLCMODES_QCFG_OUTPUT_FLAGS_JUMBO_PLACEMENT \
31034 * When this bit is '1', the VNIC is configured
31035 * to enable Header-Data split for IPv4 packets.
31037 #define HWRM_VNIC_PLCMODES_QCFG_OUTPUT_FLAGS_HDS_IPV4 \
31040 * When this bit is '1', the VNIC is configured
31041 * to enable Header-Data split for IPv6 packets.
31043 #define HWRM_VNIC_PLCMODES_QCFG_OUTPUT_FLAGS_HDS_IPV6 \
31046 * When this bit is '1', the VNIC is configured
31047 * to enable Header-Data split for FCoE packets.
31049 #define HWRM_VNIC_PLCMODES_QCFG_OUTPUT_FLAGS_HDS_FCOE \
31052 * When this bit is '1', the VNIC is configured
31053 * to enable Header-Data split for RoCE packets.
31055 #define HWRM_VNIC_PLCMODES_QCFG_OUTPUT_FLAGS_HDS_ROCE \
31058 * When this bit is '1', the VNIC is configured
31059 * to be the default VNIC of the requesting function.
31061 #define HWRM_VNIC_PLCMODES_QCFG_OUTPUT_FLAGS_DFLT_VNIC \
31064 * When this bit is '1', the VNIC is configured to use the virtio
31065 * placement algorithm. This feature can only be configured when
31066 * proxy mode is supported on the function.
31068 #define HWRM_VNIC_PLCMODES_QCFG_OUTPUT_FLAGS_VIRTIO_PLACEMENT \
31071 * When jumbo placement algorithm is enabled, this value
31072 * is used to determine the threshold for jumbo placement.
31073 * Packets with length larger than this value will be
31074 * placed according to the jumbo placement algorithm.
31076 uint16_t jumbo_thresh;
31078 * This value is used to determine the offset into
31079 * packet buffer where the split data (payload) will be
31080 * placed according to one of HDS placement algorithm.
31082 * The lengths of packet buffers provided for split data
31083 * shall be larger than this value.
31085 uint16_t hds_offset;
31087 * When one of the HDS placement algorithm is enabled, this
31088 * value is used to determine the threshold for HDS
31090 * Packets with length larger than this value will be
31091 * placed according to the HDS placement algorithm.
31092 * This value shall be in multiple of 4 bytes.
31094 uint16_t hds_threshold;
31096 * When virtio placement algorithm is enabled, this
31097 * value is used to determine the the maximum number of BDs
31098 * that can be used to place an Rx Packet.
31099 * If an incoming packet does not fit in the buffers described
31100 * by the max BDs, the packet will be dropped and an error
31101 * will be reported in the completion. Valid values for this
31102 * field are between 1 and 8. If the VNIC uses header-data-
31103 * separation and/or TPA with buffer spanning enabled, valid
31104 * values for this field are between 2 and 8.
31105 * This feature can only be configured when proxy mode is supported
31109 uint8_t unused_0[3];
31111 * This field is used in Output records to indicate that the output
31112 * is completely written to RAM. This field should be read as '1'
31113 * to indicate that the output has been completely written.
31114 * When writing a command completion or response to an internal
31115 * processor, the order of writes has to be such that this field is
31121 /**********************************
31122 * hwrm_vnic_rss_cos_lb_ctx_alloc *
31123 **********************************/
31126 /* hwrm_vnic_rss_cos_lb_ctx_alloc_input (size:128b/16B) */
31127 struct hwrm_vnic_rss_cos_lb_ctx_alloc_input {
31128 /* The HWRM command request type. */
31131 * The completion ring to send the completion event on. This should
31132 * be the NQ ID returned from the `nq_alloc` HWRM command.
31134 uint16_t cmpl_ring;
31136 * The sequence ID is used by the driver for tracking multiple
31137 * commands. This ID is treated as opaque data by the firmware and
31138 * the value is returned in the `hwrm_resp_hdr` upon completion.
31142 * The target ID of the command:
31143 * * 0x0-0xFFF8 - The function ID
31144 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
31145 * * 0xFFFD - Reserved for user-space HWRM interface
31148 uint16_t target_id;
31150 * A physical address pointer pointing to a host buffer that the
31151 * command's response data will be written. This can be either a host
31152 * physical address (HPA) or a guest physical address (GPA) and must
31153 * point to a physically contiguous block of memory.
31155 uint64_t resp_addr;
31158 /* hwrm_vnic_rss_cos_lb_ctx_alloc_output (size:128b/16B) */
31159 struct hwrm_vnic_rss_cos_lb_ctx_alloc_output {
31160 /* The specific error status for the command. */
31161 uint16_t error_code;
31162 /* The HWRM command request type. */
31164 /* The sequence ID from the original command. */
31166 /* The length of the response data in number of bytes. */
31168 /* rss_cos_lb_ctx_id is 16 b */
31169 uint16_t rss_cos_lb_ctx_id;
31170 uint8_t unused_0[5];
31172 * This field is used in Output records to indicate that the output
31173 * is completely written to RAM. This field should be read as '1'
31174 * to indicate that the output has been completely written.
31175 * When writing a command completion or response to an internal processor,
31176 * the order of writes has to be such that this field is written last.
31181 /*********************************
31182 * hwrm_vnic_rss_cos_lb_ctx_free *
31183 *********************************/
31186 /* hwrm_vnic_rss_cos_lb_ctx_free_input (size:192b/24B) */
31187 struct hwrm_vnic_rss_cos_lb_ctx_free_input {
31188 /* The HWRM command request type. */
31191 * The completion ring to send the completion event on. This should
31192 * be the NQ ID returned from the `nq_alloc` HWRM command.
31194 uint16_t cmpl_ring;
31196 * The sequence ID is used by the driver for tracking multiple
31197 * commands. This ID is treated as opaque data by the firmware and
31198 * the value is returned in the `hwrm_resp_hdr` upon completion.
31202 * The target ID of the command:
31203 * * 0x0-0xFFF8 - The function ID
31204 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
31205 * * 0xFFFD - Reserved for user-space HWRM interface
31208 uint16_t target_id;
31210 * A physical address pointer pointing to a host buffer that the
31211 * command's response data will be written. This can be either a host
31212 * physical address (HPA) or a guest physical address (GPA) and must
31213 * point to a physically contiguous block of memory.
31215 uint64_t resp_addr;
31216 /* rss_cos_lb_ctx_id is 16 b */
31217 uint16_t rss_cos_lb_ctx_id;
31218 uint8_t unused_0[6];
31221 /* hwrm_vnic_rss_cos_lb_ctx_free_output (size:128b/16B) */
31222 struct hwrm_vnic_rss_cos_lb_ctx_free_output {
31223 /* The specific error status for the command. */
31224 uint16_t error_code;
31225 /* The HWRM command request type. */
31227 /* The sequence ID from the original command. */
31229 /* The length of the response data in number of bytes. */
31231 uint8_t unused_0[7];
31233 * This field is used in Output records to indicate that the output
31234 * is completely written to RAM. This field should be read as '1'
31235 * to indicate that the output has been completely written.
31236 * When writing a command completion or response to an internal processor,
31237 * the order of writes has to be such that this field is written last.
31242 /*******************
31243 * hwrm_ring_alloc *
31244 *******************/
31247 /* hwrm_ring_alloc_input (size:704b/88B) */
31248 struct hwrm_ring_alloc_input {
31249 /* The HWRM command request type. */
31252 * The completion ring to send the completion event on. This should
31253 * be the NQ ID returned from the `nq_alloc` HWRM command.
31255 uint16_t cmpl_ring;
31257 * The sequence ID is used by the driver for tracking multiple
31258 * commands. This ID is treated as opaque data by the firmware and
31259 * the value is returned in the `hwrm_resp_hdr` upon completion.
31263 * The target ID of the command:
31264 * * 0x0-0xFFF8 - The function ID
31265 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
31266 * * 0xFFFD - Reserved for user-space HWRM interface
31269 uint16_t target_id;
31271 * A physical address pointer pointing to a host buffer that the
31272 * command's response data will be written. This can be either a host
31273 * physical address (HPA) or a guest physical address (GPA) and must
31274 * point to a physically contiguous block of memory.
31276 uint64_t resp_addr;
31279 * This bit must be '1' for the ring_arb_cfg field to be
31282 #define HWRM_RING_ALLOC_INPUT_ENABLES_RING_ARB_CFG \
31285 * This bit must be '1' for the stat_ctx_id_valid field to be
31288 #define HWRM_RING_ALLOC_INPUT_ENABLES_STAT_CTX_ID_VALID \
31291 * This bit must be '1' for the max_bw_valid field to be
31294 #define HWRM_RING_ALLOC_INPUT_ENABLES_MAX_BW_VALID \
31297 * This bit must be '1' for the rx_ring_id field to be
31300 #define HWRM_RING_ALLOC_INPUT_ENABLES_RX_RING_ID_VALID \
31303 * This bit must be '1' for the nq_ring_id field to be
31306 #define HWRM_RING_ALLOC_INPUT_ENABLES_NQ_RING_ID_VALID \
31309 * This bit must be '1' for the rx_buf_size field to be
31312 #define HWRM_RING_ALLOC_INPUT_ENABLES_RX_BUF_SIZE_VALID \
31315 * This bit must be '1' for the schq_id field to be
31318 #define HWRM_RING_ALLOC_INPUT_ENABLES_SCHQ_ID \
31321 * This bit must be '1' for the mpc_chnls_type field to be
31324 #define HWRM_RING_ALLOC_INPUT_ENABLES_MPC_CHNLS_TYPE \
31328 /* L2 Completion Ring (CR) */
31329 #define HWRM_RING_ALLOC_INPUT_RING_TYPE_L2_CMPL UINT32_C(0x0)
31331 #define HWRM_RING_ALLOC_INPUT_RING_TYPE_TX UINT32_C(0x1)
31333 #define HWRM_RING_ALLOC_INPUT_RING_TYPE_RX UINT32_C(0x2)
31334 /* RoCE Notification Completion Ring (ROCE_CR) */
31335 #define HWRM_RING_ALLOC_INPUT_RING_TYPE_ROCE_CMPL UINT32_C(0x3)
31336 /* RX Aggregation Ring */
31337 #define HWRM_RING_ALLOC_INPUT_RING_TYPE_RX_AGG UINT32_C(0x4)
31338 /* Notification Queue */
31339 #define HWRM_RING_ALLOC_INPUT_RING_TYPE_NQ UINT32_C(0x5)
31340 #define HWRM_RING_ALLOC_INPUT_RING_TYPE_LAST \
31341 HWRM_RING_ALLOC_INPUT_RING_TYPE_NQ
31343 /* Ring allocation flags. */
31346 * For Rx rings, the incoming packet data can be placed at either
31347 * a 0B or 2B offset from the start of the Rx packet buffer. When
31348 * '1', the received packet will be padded with 2B of zeros at the
31349 * front of the packet. Note that this flag is only used for
31350 * Rx rings and is ignored for all other rings included Rx
31351 * Aggregation rings.
31353 #define HWRM_RING_ALLOC_INPUT_FLAGS_RX_SOP_PAD UINT32_C(0x1)
31355 * This value is a pointer to the page table for the
31358 uint64_t page_tbl_addr;
31359 /* First Byte Offset of the first entry in the first page. */
31362 * Actual page size in 2^page_size. The supported range is increments
31363 * in powers of 2 from 16 bytes to 1GB.
31365 * Page size is 16 B.
31367 * Page size is 4 KB.
31369 * Page size is 8 KB.
31371 * Page size is 64 KB.
31373 * Page size is 2 MB.
31375 * Page size is 4 MB.
31377 * Page size is 1 GB.
31381 * This value indicates the depth of page table.
31382 * For this version of the specification, value other than 0 or
31383 * 1 shall be considered as an invalid value.
31384 * When the page_tbl_depth = 0, then it is treated as a
31385 * special case with the following.
31386 * 1. FBO and page size fields are not valid.
31387 * 2. page_tbl_addr is the physical address of the first
31388 * element of the ring.
31390 uint8_t page_tbl_depth;
31391 /* Used by a PF driver to associate a SCHQ with one of its TX rings. */
31394 * Number of 16B units in the ring. Minimum size for
31395 * a ring is 16 16B entries.
31399 * Logical ring number for the ring to be allocated.
31400 * This value determines the position in the doorbell
31401 * area where the update to the ring will be made.
31403 * For completion rings, this value is also the MSI-X
31404 * vector number for the function the completion ring is
31407 uint16_t logical_id;
31409 * This field is used only when ring_type is a TX ring.
31410 * This value indicates what completion ring the TX ring
31411 * is associated with.
31413 uint16_t cmpl_ring_id;
31415 * This field is used only when ring_type is a TX ring.
31416 * This value indicates what CoS queue the TX ring
31417 * is associated with.
31421 * When allocating a Rx ring or Rx aggregation ring, this field
31422 * specifies the size of the buffer descriptors posted to the ring.
31424 uint16_t rx_buf_size;
31426 * When allocating an Rx aggregation ring, this field
31427 * specifies the associated Rx ring ID.
31429 uint16_t rx_ring_id;
31431 * When allocating a completion ring, this field
31432 * specifies the associated NQ ring ID.
31434 uint16_t nq_ring_id;
31436 * This field is used only when ring_type is a TX ring.
31437 * This field is used to configure arbitration related
31438 * parameters for a TX ring.
31440 uint16_t ring_arb_cfg;
31441 /* Arbitration policy used for the ring. */
31442 #define HWRM_RING_ALLOC_INPUT_RING_ARB_CFG_ARB_POLICY_MASK \
31444 #define HWRM_RING_ALLOC_INPUT_RING_ARB_CFG_ARB_POLICY_SFT 0
31446 * Use strict priority for the TX ring.
31447 * Priority value is specified in arb_policy_param
31449 #define HWRM_RING_ALLOC_INPUT_RING_ARB_CFG_ARB_POLICY_SP \
31452 * Use weighted fair queue arbitration for the TX ring.
31453 * Weight is specified in arb_policy_param
31455 #define HWRM_RING_ALLOC_INPUT_RING_ARB_CFG_ARB_POLICY_WFQ \
31457 #define HWRM_RING_ALLOC_INPUT_RING_ARB_CFG_ARB_POLICY_LAST \
31458 HWRM_RING_ALLOC_INPUT_RING_ARB_CFG_ARB_POLICY_WFQ
31459 /* Reserved field. */
31460 #define HWRM_RING_ALLOC_INPUT_RING_ARB_CFG_RSVD_MASK \
31462 #define HWRM_RING_ALLOC_INPUT_RING_ARB_CFG_RSVD_SFT 4
31464 * Arbitration policy specific parameter.
31465 * # For strict priority arbitration policy, this field
31466 * represents a priority value. If set to 0, then the priority
31467 * is not specified and the HWRM is allowed to select
31468 * any priority for this TX ring.
31469 * # For weighted fair queue arbitration policy, this field
31470 * represents a weight value. If set to 0, then the weight
31471 * is not specified and the HWRM is allowed to select
31472 * any weight for this TX ring.
31474 #define HWRM_RING_ALLOC_INPUT_RING_ARB_CFG_ARB_POLICY_PARAM_MASK \
31476 #define HWRM_RING_ALLOC_INPUT_RING_ARB_CFG_ARB_POLICY_PARAM_SFT 8
31479 * This field is reserved for the future use.
31480 * It shall be set to 0.
31482 uint32_t reserved3;
31484 * This field is used only when ring_type is a TX ring.
31485 * This input indicates what statistics context this ring
31486 * should be associated with.
31488 uint32_t stat_ctx_id;
31490 * This field is reserved for the future use.
31491 * It shall be set to 0.
31493 uint32_t reserved4;
31495 * This field is used only when ring_type is a TX ring
31496 * to specify maximum BW allocated to the TX ring.
31497 * The HWRM will translate this value into byte counter and
31498 * time interval used for this ring inside the device.
31501 /* The bandwidth value. */
31502 #define HWRM_RING_ALLOC_INPUT_MAX_BW_BW_VALUE_MASK \
31503 UINT32_C(0xfffffff)
31504 #define HWRM_RING_ALLOC_INPUT_MAX_BW_BW_VALUE_SFT 0
31505 /* The granularity of the value (bits or bytes). */
31506 #define HWRM_RING_ALLOC_INPUT_MAX_BW_SCALE \
31507 UINT32_C(0x10000000)
31508 /* Value is in bits. */
31509 #define HWRM_RING_ALLOC_INPUT_MAX_BW_SCALE_BITS \
31510 (UINT32_C(0x0) << 28)
31511 /* Value is in bytes. */
31512 #define HWRM_RING_ALLOC_INPUT_MAX_BW_SCALE_BYTES \
31513 (UINT32_C(0x1) << 28)
31514 #define HWRM_RING_ALLOC_INPUT_MAX_BW_SCALE_LAST \
31515 HWRM_RING_ALLOC_INPUT_MAX_BW_SCALE_BYTES
31516 /* bw_value_unit is 3 b */
31517 #define HWRM_RING_ALLOC_INPUT_MAX_BW_BW_VALUE_UNIT_MASK \
31518 UINT32_C(0xe0000000)
31519 #define HWRM_RING_ALLOC_INPUT_MAX_BW_BW_VALUE_UNIT_SFT 29
31520 /* Value is in Mb or MB (base 10). */
31521 #define HWRM_RING_ALLOC_INPUT_MAX_BW_BW_VALUE_UNIT_MEGA \
31522 (UINT32_C(0x0) << 29)
31523 /* Value is in Kb or KB (base 10). */
31524 #define HWRM_RING_ALLOC_INPUT_MAX_BW_BW_VALUE_UNIT_KILO \
31525 (UINT32_C(0x2) << 29)
31526 /* Value is in bits or bytes. */
31527 #define HWRM_RING_ALLOC_INPUT_MAX_BW_BW_VALUE_UNIT_BASE \
31528 (UINT32_C(0x4) << 29)
31529 /* Value is in Gb or GB (base 10). */
31530 #define HWRM_RING_ALLOC_INPUT_MAX_BW_BW_VALUE_UNIT_GIGA \
31531 (UINT32_C(0x6) << 29)
31532 /* Value is in 1/100th of a percentage of total bandwidth. */
31533 #define HWRM_RING_ALLOC_INPUT_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 \
31534 (UINT32_C(0x1) << 29)
31536 #define HWRM_RING_ALLOC_INPUT_MAX_BW_BW_VALUE_UNIT_INVALID \
31537 (UINT32_C(0x7) << 29)
31538 #define HWRM_RING_ALLOC_INPUT_MAX_BW_BW_VALUE_UNIT_LAST \
31539 HWRM_RING_ALLOC_INPUT_MAX_BW_BW_VALUE_UNIT_INVALID
31541 * This field is used only when ring_type is a Completion ring.
31542 * This value indicates what interrupt mode should be used
31543 * on this completion ring.
31544 * Note: In the legacy interrupt mode, no more than 16
31545 * completion rings are allowed.
31549 #define HWRM_RING_ALLOC_INPUT_INT_MODE_LEGACY UINT32_C(0x0)
31551 #define HWRM_RING_ALLOC_INPUT_INT_MODE_RSVD UINT32_C(0x1)
31553 #define HWRM_RING_ALLOC_INPUT_INT_MODE_MSIX UINT32_C(0x2)
31554 /* No Interrupt - Polled mode */
31555 #define HWRM_RING_ALLOC_INPUT_INT_MODE_POLL UINT32_C(0x3)
31556 #define HWRM_RING_ALLOC_INPUT_INT_MODE_LAST \
31557 HWRM_RING_ALLOC_INPUT_INT_MODE_POLL
31558 /* Midpath channel type */
31559 uint8_t mpc_chnls_type;
31561 * Indicate the TX ring alloc MPC channel type is a MPC channel
31562 * with destination to the TX crypto engine block.
31564 #define HWRM_RING_ALLOC_INPUT_MPC_CHNLS_TYPE_TCE UINT32_C(0x0)
31566 * Indicate the RX ring alloc MPC channel type is a MPC channel
31567 * with destination to the RX crypto engine block.
31569 #define HWRM_RING_ALLOC_INPUT_MPC_CHNLS_TYPE_RCE UINT32_C(0x1)
31571 * Indicate the RX ring alloc MPC channel type is a MPC channel
31572 * with destination to the TX configurable flow processing block.
31574 #define HWRM_RING_ALLOC_INPUT_MPC_CHNLS_TYPE_TE_CFA UINT32_C(0x2)
31576 * Indicate the RX ring alloc MPC channel type is a MPC channel
31577 * with destination to the RX configurable flow processing block.
31579 #define HWRM_RING_ALLOC_INPUT_MPC_CHNLS_TYPE_RE_CFA UINT32_C(0x3)
31581 * Indicate the RX ring alloc MPC channel type is a MPC channel
31582 * with destination to the primate processor block.
31584 #define HWRM_RING_ALLOC_INPUT_MPC_CHNLS_TYPE_PRIMATE UINT32_C(0x4)
31585 #define HWRM_RING_ALLOC_INPUT_MPC_CHNLS_TYPE_LAST \
31586 HWRM_RING_ALLOC_INPUT_MPC_CHNLS_TYPE_PRIMATE
31587 uint8_t unused_4[2];
31589 * The cq_handle is specified when allocating a completion ring. For
31590 * devices that support NQs, this cq_handle will be included in the
31591 * NQE to specify which CQ should be read to retrieve the completion
31594 uint64_t cq_handle;
31597 /* hwrm_ring_alloc_output (size:128b/16B) */
31598 struct hwrm_ring_alloc_output {
31599 /* The specific error status for the command. */
31600 uint16_t error_code;
31601 /* The HWRM command request type. */
31603 /* The sequence ID from the original command. */
31605 /* The length of the response data in number of bytes. */
31608 * Physical number of ring allocated.
31609 * This value shall be unique for a ring type.
31612 /* Logical number of ring allocated. */
31613 uint16_t logical_ring_id;
31615 * This field will tell whether to use ping or pong buffer
31616 * for first push operation.
31618 uint8_t push_buffer_index;
31619 /* Start push from ping buffer index */
31620 #define HWRM_RING_ALLOC_OUTPUT_PUSH_BUFFER_INDEX_PING_BUFFER \
31622 /* Start push from pong buffer index */
31623 #define HWRM_RING_ALLOC_OUTPUT_PUSH_BUFFER_INDEX_PONG_BUFFER \
31625 #define HWRM_RING_ALLOC_OUTPUT_PUSH_BUFFER_INDEX_LAST \
31626 HWRM_RING_ALLOC_OUTPUT_PUSH_BUFFER_INDEX_PONG_BUFFER
31627 uint8_t unused_0[2];
31629 * This field is used in Output records to indicate that the output
31630 * is completely written to RAM. This field should be read as '1'
31631 * to indicate that the output has been completely written.
31632 * When writing a command completion or response to an internal processor,
31633 * the order of writes has to be such that this field is written last.
31638 /******************
31640 ******************/
31643 /* hwrm_ring_free_input (size:192b/24B) */
31644 struct hwrm_ring_free_input {
31645 /* The HWRM command request type. */
31648 * The completion ring to send the completion event on. This should
31649 * be the NQ ID returned from the `nq_alloc` HWRM command.
31651 uint16_t cmpl_ring;
31653 * The sequence ID is used by the driver for tracking multiple
31654 * commands. This ID is treated as opaque data by the firmware and
31655 * the value is returned in the `hwrm_resp_hdr` upon completion.
31659 * The target ID of the command:
31660 * * 0x0-0xFFF8 - The function ID
31661 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
31662 * * 0xFFFD - Reserved for user-space HWRM interface
31665 uint16_t target_id;
31667 * A physical address pointer pointing to a host buffer that the
31668 * command's response data will be written. This can be either a host
31669 * physical address (HPA) or a guest physical address (GPA) and must
31670 * point to a physically contiguous block of memory.
31672 uint64_t resp_addr;
31675 /* L2 Completion Ring (CR) */
31676 #define HWRM_RING_FREE_INPUT_RING_TYPE_L2_CMPL UINT32_C(0x0)
31678 #define HWRM_RING_FREE_INPUT_RING_TYPE_TX UINT32_C(0x1)
31680 #define HWRM_RING_FREE_INPUT_RING_TYPE_RX UINT32_C(0x2)
31681 /* RoCE Notification Completion Ring (ROCE_CR) */
31682 #define HWRM_RING_FREE_INPUT_RING_TYPE_ROCE_CMPL UINT32_C(0x3)
31683 /* RX Aggregation Ring */
31684 #define HWRM_RING_FREE_INPUT_RING_TYPE_RX_AGG UINT32_C(0x4)
31685 /* Notification Queue */
31686 #define HWRM_RING_FREE_INPUT_RING_TYPE_NQ UINT32_C(0x5)
31687 #define HWRM_RING_FREE_INPUT_RING_TYPE_LAST \
31688 HWRM_RING_FREE_INPUT_RING_TYPE_NQ
31690 /* Physical number of ring allocated. */
31692 uint8_t unused_1[4];
31695 /* hwrm_ring_free_output (size:128b/16B) */
31696 struct hwrm_ring_free_output {
31697 /* The specific error status for the command. */
31698 uint16_t error_code;
31699 /* The HWRM command request type. */
31701 /* The sequence ID from the original command. */
31703 /* The length of the response data in number of bytes. */
31705 uint8_t unused_0[7];
31707 * This field is used in Output records to indicate that the output
31708 * is completely written to RAM. This field should be read as '1'
31709 * to indicate that the output has been completely written.
31710 * When writing a command completion or response to an internal processor,
31711 * the order of writes has to be such that this field is written last.
31716 /*******************
31717 * hwrm_ring_reset *
31718 *******************/
31721 /* hwrm_ring_reset_input (size:192b/24B) */
31722 struct hwrm_ring_reset_input {
31723 /* The HWRM command request type. */
31726 * The completion ring to send the completion event on. This should
31727 * be the NQ ID returned from the `nq_alloc` HWRM command.
31729 uint16_t cmpl_ring;
31731 * The sequence ID is used by the driver for tracking multiple
31732 * commands. This ID is treated as opaque data by the firmware and
31733 * the value is returned in the `hwrm_resp_hdr` upon completion.
31737 * The target ID of the command:
31738 * * 0x0-0xFFF8 - The function ID
31739 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
31740 * * 0xFFFD - Reserved for user-space HWRM interface
31743 uint16_t target_id;
31745 * A physical address pointer pointing to a host buffer that the
31746 * command's response data will be written. This can be either a host
31747 * physical address (HPA) or a guest physical address (GPA) and must
31748 * point to a physically contiguous block of memory.
31750 uint64_t resp_addr;
31753 /* L2 Completion Ring (CR) */
31754 #define HWRM_RING_RESET_INPUT_RING_TYPE_L2_CMPL UINT32_C(0x0)
31756 #define HWRM_RING_RESET_INPUT_RING_TYPE_TX UINT32_C(0x1)
31758 #define HWRM_RING_RESET_INPUT_RING_TYPE_RX UINT32_C(0x2)
31759 /* RoCE Notification Completion Ring (ROCE_CR) */
31760 #define HWRM_RING_RESET_INPUT_RING_TYPE_ROCE_CMPL UINT32_C(0x3)
31762 * Rx Ring Group. This is to reset rx and aggregation in an atomic
31763 * operation. Completion ring associated with this ring group is
31766 #define HWRM_RING_RESET_INPUT_RING_TYPE_RX_RING_GRP UINT32_C(0x6)
31767 #define HWRM_RING_RESET_INPUT_RING_TYPE_LAST \
31768 HWRM_RING_RESET_INPUT_RING_TYPE_RX_RING_GRP
31771 * Physical number of the ring. When ring type is rx_ring_grp, ring id
31772 * actually refers to ring group id.
31775 uint8_t unused_1[4];
31778 /* hwrm_ring_reset_output (size:128b/16B) */
31779 struct hwrm_ring_reset_output {
31780 /* The specific error status for the command. */
31781 uint16_t error_code;
31782 /* The HWRM command request type. */
31784 /* The sequence ID from the original command. */
31786 /* The length of the response data in number of bytes. */
31789 * This field will tell whether to use ping or pong buffer
31790 * for first push operation.
31792 uint8_t push_buffer_index;
31793 /* Start push from ping buffer index */
31794 #define HWRM_RING_RESET_OUTPUT_PUSH_BUFFER_INDEX_PING_BUFFER \
31796 /* Start push from pong buffer index */
31797 #define HWRM_RING_RESET_OUTPUT_PUSH_BUFFER_INDEX_PONG_BUFFER \
31799 #define HWRM_RING_RESET_OUTPUT_PUSH_BUFFER_INDEX_LAST \
31800 HWRM_RING_RESET_OUTPUT_PUSH_BUFFER_INDEX_PONG_BUFFER
31801 uint8_t unused_0[3];
31802 /* Position of consumer index after ring reset completes. */
31803 uint8_t consumer_idx[3];
31805 * This field is used in Output records to indicate that the output
31806 * is completely written to RAM. This field should be read as '1'
31807 * to indicate that the output has been completely written.
31808 * When writing a command completion or response to an internal processor,
31809 * the order of writes has to be such that this field is written last.
31819 /* hwrm_ring_cfg_input (size:320b/40B) */
31820 struct hwrm_ring_cfg_input {
31821 /* The HWRM command request type. */
31824 * The completion ring to send the completion event on. This should
31825 * be the NQ ID returned from the `nq_alloc` HWRM command.
31827 uint16_t cmpl_ring;
31829 * The sequence ID is used by the driver for tracking multiple
31830 * commands. This ID is treated as opaque data by the firmware and
31831 * the value is returned in the `hwrm_resp_hdr` upon completion.
31835 * The target ID of the command:
31836 * * 0x0-0xFFF8 - The function ID
31837 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
31838 * * 0xFFFD - Reserved for user-space HWRM interface
31841 uint16_t target_id;
31843 * A physical address pointer pointing to a host buffer that the
31844 * command's response data will be written. This can be either a host
31845 * physical address (HPA) or a guest physical address (GPA) and must
31846 * point to a physically contiguous block of memory.
31848 uint64_t resp_addr;
31852 #define HWRM_RING_CFG_INPUT_RING_TYPE_TX UINT32_C(0x1)
31854 #define HWRM_RING_CFG_INPUT_RING_TYPE_RX UINT32_C(0x2)
31855 #define HWRM_RING_CFG_INPUT_RING_TYPE_LAST \
31856 HWRM_RING_CFG_INPUT_RING_TYPE_RX
31858 /* Physical number of the ring. */
31860 /* Ring config enable bits. */
31863 * For Rx rings, the incoming packet data can be placed at either
31864 * a 0B, 2B, 10B or 12B offset from the start of the Rx packet
31866 * When '1', the received packet will be padded with 2B, 10B or 12B
31867 * of zeros at the front of the packet. The exact offset is specified
31868 * by rx_sop_pad_bytes parameter.
31869 * When '0', the received packet will not be padded.
31870 * Note that this flag is only used for Rx rings and is ignored
31871 * for all other rings included Rx Aggregation rings.
31873 #define HWRM_RING_CFG_INPUT_ENABLES_RX_SOP_PAD_ENABLE \
31876 * Proxy mode enable, for Tx, Rx and Rx aggregation rings only.
31877 * When rings are allocated, the PCI function on which driver issues
31878 * HWRM_RING_CFG command is assumed to own the rings. Hardware takes
31879 * the buffer descriptors (BDs) from those rings is assumed to issue
31880 * packet payload DMA using same PCI function. When proxy mode is
31881 * enabled, hardware can perform payload DMA using another PCI
31882 * function on same or different host.
31883 * When set to '0', the PCI function on which driver issues
31884 * HWRM_RING_CFG command is used for host payload DMA operation.
31885 * When set to '1', the host PCI function specified by proxy_fid is
31886 * used for host payload DMA operation.
31888 #define HWRM_RING_CFG_INPUT_ENABLES_PROXY_MODE_ENABLE \
31891 * Tx ring packet source interface override, for Tx rings only.
31892 * When TX rings are allocated, the PCI function on which driver
31893 * issues HWRM_RING_CFG is assumed to be source interface of
31894 * packets sent from TX ring.
31895 * When set to '1', the host PCI function specified by proxy_fid
31896 * is used as source interface of the transmitted packets.
31898 #define HWRM_RING_CFG_INPUT_ENABLES_TX_PROXY_SRC_INTF_OVERRIDE \
31900 /* The schq_id field is valid */
31901 #define HWRM_RING_CFG_INPUT_ENABLES_SCHQ_ID \
31903 /* Update completion ring ID associated with Tx or Rx ring. */
31904 #define HWRM_RING_CFG_INPUT_ENABLES_CMPL_RING_ID_UPDATE \
31907 * When set to '1', metadata value provided by tx_metadata
31908 * field in this command is inserted in the lb_header_metadata
31909 * QP context field. When set to '0', no change done to metadata.
31910 * Firmware rejects the tx ring metadata programming with
31911 * HWRM_ERR_CODE_UNSUPPORTED error if the per function CFA BD
31912 * metadata feature is not disabled.
31914 #define HWRM_RING_CFG_INPUT_ENABLES_TX_METADATA \
31917 * Proxy function FID value.
31918 * This value is only used when either proxy_mode_enable flag or
31919 * tx_proxy_svif_override is set to '1'.
31920 * When proxy_mode_enable is set to '1', it identifies a host PCI
31921 * function used for host payload DMA operations.
31922 * When tx_proxy_src_intf is set to '1', it identifies a host PCI
31923 * function as source interface for all transmitted packets from
31926 uint16_t proxy_fid;
31928 * Identifies the new scheduler queue (SCHQ) to associate with the
31929 * ring. Only valid for Tx rings.
31930 * A value of zero indicates that the Tx ring should be associated
31931 * with the default scheduler queue (SCHQ).
31935 * This field is valid for TX or Rx rings. This value identifies the
31936 * new completion ring ID to associate with the TX or Rx ring.
31938 uint16_t cmpl_ring_id;
31940 * Rx SOP padding amount in bytes.
31941 * This value is only used when rx_sop_pad_enable flag is set to '1'.
31943 uint8_t rx_sop_pad_bytes;
31944 uint8_t unused_1[3];
31946 * When tx_metadata enable bit is set, value specified in this field
31947 * is copied to lb_header_metadata in the QP context.
31949 uint32_t tx_metadata;
31950 uint8_t unused_2[4];
31953 /* hwrm_ring_cfg_output (size:128b/16B) */
31954 struct hwrm_ring_cfg_output {
31955 /* The specific error status for the command. */
31956 uint16_t error_code;
31957 /* The HWRM command request type. */
31959 /* The sequence ID from the original command. */
31961 /* The length of the response data in number of bytes. */
31963 uint8_t unused_0[7];
31965 * This field is used in Output records to indicate that the output
31966 * is completely written to RAM. This field should be read as '1'
31967 * to indicate that the output has been completely written.
31968 * When writing a command completion or response to an internal
31969 * processor, the order of writes has to be such that this field is
31975 /******************
31977 ******************/
31980 /* hwrm_ring_qcfg_input (size:192b/24B) */
31981 struct hwrm_ring_qcfg_input {
31982 /* The HWRM command request type. */
31985 * The completion ring to send the completion event on. This should
31986 * be the NQ ID returned from the `nq_alloc` HWRM command.
31988 uint16_t cmpl_ring;
31990 * The sequence ID is used by the driver for tracking multiple
31991 * commands. This ID is treated as opaque data by the firmware and
31992 * the value is returned in the `hwrm_resp_hdr` upon completion.
31996 * The target ID of the command:
31997 * * 0x0-0xFFF8 - The function ID
31998 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
31999 * * 0xFFFD - Reserved for user-space HWRM interface
32002 uint16_t target_id;
32004 * A physical address pointer pointing to a host buffer that the
32005 * command's response data will be written. This can be either a host
32006 * physical address (HPA) or a guest physical address (GPA) and must
32007 * point to a physically contiguous block of memory.
32009 uint64_t resp_addr;
32013 #define HWRM_RING_QCFG_INPUT_RING_TYPE_TX UINT32_C(0x1)
32015 #define HWRM_RING_QCFG_INPUT_RING_TYPE_RX UINT32_C(0x2)
32016 #define HWRM_RING_QCFG_INPUT_RING_TYPE_LAST \
32017 HWRM_RING_QCFG_INPUT_RING_TYPE_RX
32018 uint8_t unused_0[5];
32019 /* Physical number of the ring. */
32023 /* hwrm_ring_qcfg_output (size:256b/32B) */
32024 struct hwrm_ring_qcfg_output {
32025 /* The specific error status for the command. */
32026 uint16_t error_code;
32027 /* The HWRM command request type. */
32029 /* The sequence ID from the original command. */
32031 /* The length of the response data in number of bytes. */
32033 /* Ring config enable bits. */
32036 * For Rx rings, the incoming packet data can be placed at either
32037 * a 0B, 2B, 10B or 12B offset from the start of the Rx packet
32039 * When '1', the received packet will be padded with 2B, 10B or 12B
32040 * of zeros at the front of the packet. The exact offset is specified
32041 * by rx_sop_pad_bytes parameter.
32042 * When '0', the received packet will not be padded.
32043 * Note that this flag is only used for Rx rings and is ignored
32044 * for all other rings included Rx Aggregation rings.
32046 #define HWRM_RING_QCFG_OUTPUT_ENABLES_RX_SOP_PAD_ENABLE \
32049 * Proxy mode enable, for Tx, Rx and Rx aggregation rings only.
32050 * When rings are allocated, the PCI function on which driver issues
32051 * HWRM_RING_CFG command is assumed to own the rings. Hardware takes
32052 * the buffer descriptors (BDs) from those rings is assumed to issue
32053 * packet payload DMA using same PCI function. When proxy mode is
32054 * enabled, hardware can perform payload DMA using another PCI
32055 * function on same or different host.
32056 * When set to '0', the PCI function on which driver issues
32057 * HWRM_RING_CFG command is used for host payload DMA operation.
32058 * When set to '1', the host PCI function specified by proxy_fid is
32059 * used for host payload DMA operation.
32061 #define HWRM_RING_QCFG_OUTPUT_ENABLES_PROXY_MODE_ENABLE \
32064 * Tx ring packet source interface override, for Tx rings only.
32065 * When TX rings are allocated, the PCI function on which driver
32066 * issues HWRM_RING_CFG is assumed to be source interface of
32067 * packets sent from TX ring.
32068 * When set to '1', the host PCI function specified by proxy_fid is
32069 * used as source interface of the transmitted packets.
32071 #define HWRM_RING_QCFG_OUTPUT_ENABLES_TX_PROXY_SRC_INTF_OVERRIDE \
32074 * Proxy function FID value.
32075 * This value is only used when either proxy_mode_enable flag or
32076 * tx_proxy_svif_override is set to '1'.
32077 * When proxy_mode_enable is set to '1', it identifies a host PCI
32078 * function used for host payload DMA operations.
32079 * When tx_proxy_src_intf is set to '1', it identifies a host PCI
32080 * function as source interface for all transmitted packets from the TX
32083 uint16_t proxy_fid;
32085 * Identifies the new scheduler queue (SCHQ) to associate with the
32086 * ring. Only valid for Tx rings.
32087 * A value of zero indicates that the Tx ring should be associated with
32088 * the default scheduler queue (SCHQ).
32092 * This field is used when ring_type is a TX or Rx ring.
32093 * This value indicates what completion ring the TX or Rx ring
32094 * is associated with.
32096 uint16_t cmpl_ring_id;
32098 * Rx SOP padding amount in bytes.
32099 * This value is only used when rx_sop_pad_enable flag is set to '1'.
32101 uint8_t rx_sop_pad_bytes;
32102 uint8_t unused_0[3];
32103 /* lb_header_metadata in the QP context is copied to this field. */
32104 uint32_t tx_metadata;
32105 uint8_t unused_1[7];
32107 * This field is used in Output records to indicate that the output
32108 * is completely written to RAM. This field should be read as '1'
32109 * to indicate that the output has been completely written.
32110 * When writing a command completion or response to an internal
32111 * processor, the order of writes has to be such that this field is
32117 /**************************
32118 * hwrm_ring_aggint_qcaps *
32119 **************************/
32122 /* hwrm_ring_aggint_qcaps_input (size:128b/16B) */
32123 struct hwrm_ring_aggint_qcaps_input {
32124 /* The HWRM command request type. */
32127 * The completion ring to send the completion event on. This should
32128 * be the NQ ID returned from the `nq_alloc` HWRM command.
32130 uint16_t cmpl_ring;
32132 * The sequence ID is used by the driver for tracking multiple
32133 * commands. This ID is treated as opaque data by the firmware and
32134 * the value is returned in the `hwrm_resp_hdr` upon completion.
32138 * The target ID of the command:
32139 * * 0x0-0xFFF8 - The function ID
32140 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
32141 * * 0xFFFD - Reserved for user-space HWRM interface
32144 uint16_t target_id;
32146 * A physical address pointer pointing to a host buffer that the
32147 * command's response data will be written. This can be either a host
32148 * physical address (HPA) or a guest physical address (GPA) and must
32149 * point to a physically contiguous block of memory.
32151 uint64_t resp_addr;
32154 /* hwrm_ring_aggint_qcaps_output (size:384b/48B) */
32155 struct hwrm_ring_aggint_qcaps_output {
32156 /* The specific error status for the command. */
32157 uint16_t error_code;
32158 /* The HWRM command request type. */
32160 /* The sequence ID from the original command. */
32162 /* The length of the response data in number of bytes. */
32164 uint32_t cmpl_params;
32166 * When this bit is set to '1', int_lat_tmr_min can be configured
32167 * on completion rings.
32169 #define HWRM_RING_AGGINT_QCAPS_OUTPUT_CMPL_PARAMS_INT_LAT_TMR_MIN \
32172 * When this bit is set to '1', int_lat_tmr_max can be configured
32173 * on completion rings.
32175 #define HWRM_RING_AGGINT_QCAPS_OUTPUT_CMPL_PARAMS_INT_LAT_TMR_MAX \
32178 * When this bit is set to '1', timer_reset can be enabled
32179 * on completion rings.
32181 #define HWRM_RING_AGGINT_QCAPS_OUTPUT_CMPL_PARAMS_TIMER_RESET \
32184 * When this bit is set to '1', ring_idle can be enabled
32185 * on completion rings.
32187 #define HWRM_RING_AGGINT_QCAPS_OUTPUT_CMPL_PARAMS_RING_IDLE \
32190 * When this bit is set to '1', num_cmpl_dma_aggr can be configured
32191 * on completion rings.
32193 #define HWRM_RING_AGGINT_QCAPS_OUTPUT_CMPL_PARAMS_NUM_CMPL_DMA_AGGR \
32196 * When this bit is set to '1', num_cmpl_dma_aggr_during_int can be configured
32197 * on completion rings.
32199 #define HWRM_RING_AGGINT_QCAPS_OUTPUT_CMPL_PARAMS_NUM_CMPL_DMA_AGGR_DURING_INT \
32202 * When this bit is set to '1', cmpl_aggr_dma_tmr can be configured
32203 * on completion rings.
32205 #define HWRM_RING_AGGINT_QCAPS_OUTPUT_CMPL_PARAMS_CMPL_AGGR_DMA_TMR \
32208 * When this bit is set to '1', cmpl_aggr_dma_tmr_during_int can be configured
32209 * on completion rings.
32211 #define HWRM_RING_AGGINT_QCAPS_OUTPUT_CMPL_PARAMS_CMPL_AGGR_DMA_TMR_DURING_INT \
32214 * When this bit is set to '1', num_cmpl_aggr_int can be configured
32215 * on completion rings.
32217 #define HWRM_RING_AGGINT_QCAPS_OUTPUT_CMPL_PARAMS_NUM_CMPL_AGGR_INT \
32219 uint32_t nq_params;
32221 * When this bit is set to '1', int_lat_tmr_min can be configured
32222 * on notification queues.
32224 #define HWRM_RING_AGGINT_QCAPS_OUTPUT_NQ_PARAMS_INT_LAT_TMR_MIN \
32226 /* Minimum value for num_cmpl_dma_aggr */
32227 uint16_t num_cmpl_dma_aggr_min;
32228 /* Maximum value for num_cmpl_dma_aggr */
32229 uint16_t num_cmpl_dma_aggr_max;
32230 /* Minimum value for num_cmpl_dma_aggr_during_int */
32231 uint16_t num_cmpl_dma_aggr_during_int_min;
32232 /* Maximum value for num_cmpl_dma_aggr_during_int */
32233 uint16_t num_cmpl_dma_aggr_during_int_max;
32234 /* Minimum value for cmpl_aggr_dma_tmr */
32235 uint16_t cmpl_aggr_dma_tmr_min;
32236 /* Maximum value for cmpl_aggr_dma_tmr */
32237 uint16_t cmpl_aggr_dma_tmr_max;
32238 /* Minimum value for cmpl_aggr_dma_tmr_during_int */
32239 uint16_t cmpl_aggr_dma_tmr_during_int_min;
32240 /* Maximum value for cmpl_aggr_dma_tmr_during_int */
32241 uint16_t cmpl_aggr_dma_tmr_during_int_max;
32242 /* Minimum value for int_lat_tmr_min */
32243 uint16_t int_lat_tmr_min_min;
32244 /* Maximum value for int_lat_tmr_min */
32245 uint16_t int_lat_tmr_min_max;
32246 /* Minimum value for int_lat_tmr_max */
32247 uint16_t int_lat_tmr_max_min;
32248 /* Maximum value for int_lat_tmr_max */
32249 uint16_t int_lat_tmr_max_max;
32250 /* Minimum value for num_cmpl_aggr_int */
32251 uint16_t num_cmpl_aggr_int_min;
32252 /* Maximum value for num_cmpl_aggr_int */
32253 uint16_t num_cmpl_aggr_int_max;
32254 /* The units for timer parameters, in nanoseconds. */
32255 uint16_t timer_units;
32256 uint8_t unused_0[1];
32258 * This field is used in Output records to indicate that the output
32259 * is completely written to RAM. This field should be read as '1'
32260 * to indicate that the output has been completely written.
32261 * When writing a command completion or response to an internal processor,
32262 * the order of writes has to be such that this field is written last.
32267 /**************************************
32268 * hwrm_ring_cmpl_ring_qaggint_params *
32269 **************************************/
32272 /* hwrm_ring_cmpl_ring_qaggint_params_input (size:192b/24B) */
32273 struct hwrm_ring_cmpl_ring_qaggint_params_input {
32274 /* The HWRM command request type. */
32277 * The completion ring to send the completion event on. This should
32278 * be the NQ ID returned from the `nq_alloc` HWRM command.
32280 uint16_t cmpl_ring;
32282 * The sequence ID is used by the driver for tracking multiple
32283 * commands. This ID is treated as opaque data by the firmware and
32284 * the value is returned in the `hwrm_resp_hdr` upon completion.
32288 * The target ID of the command:
32289 * * 0x0-0xFFF8 - The function ID
32290 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
32291 * * 0xFFFD - Reserved for user-space HWRM interface
32294 uint16_t target_id;
32296 * A physical address pointer pointing to a host buffer that the
32297 * command's response data will be written. This can be either a host
32298 * physical address (HPA) or a guest physical address (GPA) and must
32299 * point to a physically contiguous block of memory.
32301 uint64_t resp_addr;
32302 /* Physical number of completion ring. */
32305 #define HWRM_RING_CMPL_RING_QAGGINT_PARAMS_INPUT_FLAGS_UNUSED_0_MASK \
32307 #define HWRM_RING_CMPL_RING_QAGGINT_PARAMS_INPUT_FLAGS_UNUSED_0_SFT 0
32309 * Set this flag to 1 when querying parameters on a notification
32310 * queue. Set this flag to 0 when querying parameters on a
32311 * completion queue or completion ring.
32313 #define HWRM_RING_CMPL_RING_QAGGINT_PARAMS_INPUT_FLAGS_IS_NQ \
32315 uint8_t unused_0[4];
32318 /* hwrm_ring_cmpl_ring_qaggint_params_output (size:256b/32B) */
32319 struct hwrm_ring_cmpl_ring_qaggint_params_output {
32320 /* The specific error status for the command. */
32321 uint16_t error_code;
32322 /* The HWRM command request type. */
32324 /* The sequence ID from the original command. */
32326 /* The length of the response data in number of bytes. */
32330 * When this bit is set to '1', interrupt max
32331 * timer is reset whenever a completion is received.
32333 #define HWRM_RING_CMPL_RING_QAGGINT_PARAMS_OUTPUT_FLAGS_TIMER_RESET \
32336 * When this bit is set to '1', ring idle mode
32337 * aggregation will be enabled.
32339 #define HWRM_RING_CMPL_RING_QAGGINT_PARAMS_OUTPUT_FLAGS_RING_IDLE \
32342 * Number of completions to aggregate before DMA
32343 * during the normal mode.
32345 uint16_t num_cmpl_dma_aggr;
32347 * Number of completions to aggregate before DMA
32348 * during the interrupt mode.
32350 uint16_t num_cmpl_dma_aggr_during_int;
32352 * Timer used to aggregate completions before
32353 * DMA during the normal mode (not in interrupt mode).
32355 uint16_t cmpl_aggr_dma_tmr;
32357 * Timer used to aggregate completions before
32358 * DMA when in interrupt mode.
32360 uint16_t cmpl_aggr_dma_tmr_during_int;
32361 /* Minimum time between two interrupts. */
32362 uint16_t int_lat_tmr_min;
32364 * Maximum wait time spent aggregating
32365 * completions before signaling the interrupt after the
32366 * interrupt is enabled.
32368 uint16_t int_lat_tmr_max;
32370 * Minimum number of completions aggregated before signaling
32373 uint16_t num_cmpl_aggr_int;
32374 uint8_t unused_0[7];
32376 * This field is used in Output records to indicate that the output
32377 * is completely written to RAM. This field should be read as '1'
32378 * to indicate that the output has been completely written.
32379 * When writing a command completion or response to an internal processor,
32380 * the order of writes has to be such that this field is written last.
32385 /*****************************************
32386 * hwrm_ring_cmpl_ring_cfg_aggint_params *
32387 *****************************************/
32390 /* hwrm_ring_cmpl_ring_cfg_aggint_params_input (size:320b/40B) */
32391 struct hwrm_ring_cmpl_ring_cfg_aggint_params_input {
32392 /* The HWRM command request type. */
32395 * The completion ring to send the completion event on. This should
32396 * be the NQ ID returned from the `nq_alloc` HWRM command.
32398 uint16_t cmpl_ring;
32400 * The sequence ID is used by the driver for tracking multiple
32401 * commands. This ID is treated as opaque data by the firmware and
32402 * the value is returned in the `hwrm_resp_hdr` upon completion.
32406 * The target ID of the command:
32407 * * 0x0-0xFFF8 - The function ID
32408 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
32409 * * 0xFFFD - Reserved for user-space HWRM interface
32412 uint16_t target_id;
32414 * A physical address pointer pointing to a host buffer that the
32415 * command's response data will be written. This can be either a host
32416 * physical address (HPA) or a guest physical address (GPA) and must
32417 * point to a physically contiguous block of memory.
32419 uint64_t resp_addr;
32420 /* Physical number of completion ring. */
32424 * When this bit is set to '1', interrupt latency max
32425 * timer is reset whenever a completion is received.
32427 #define HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_FLAGS_TIMER_RESET \
32430 * When this bit is set to '1', ring idle mode
32431 * aggregation will be enabled.
32433 #define HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_FLAGS_RING_IDLE \
32436 * Set this flag to 1 when configuring parameters on a
32437 * notification queue. Set this flag to 0 when configuring
32438 * parameters on a completion queue or completion ring.
32440 #define HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_FLAGS_IS_NQ \
32443 * Number of completions to aggregate before DMA
32444 * during the normal mode.
32446 uint16_t num_cmpl_dma_aggr;
32448 * Number of completions to aggregate before DMA
32449 * during the interrupt mode.
32451 uint16_t num_cmpl_dma_aggr_during_int;
32453 * Timer used to aggregate completions before
32454 * DMA during the normal mode (not in interrupt mode).
32456 uint16_t cmpl_aggr_dma_tmr;
32458 * Timer used to aggregate completions before
32459 * DMA while in interrupt mode.
32461 uint16_t cmpl_aggr_dma_tmr_during_int;
32462 /* Minimum time between two interrupts. */
32463 uint16_t int_lat_tmr_min;
32465 * Maximum wait time spent aggregating
32466 * completions before signaling the interrupt after the
32467 * interrupt is enabled.
32469 uint16_t int_lat_tmr_max;
32471 * Minimum number of completions aggregated before signaling
32474 uint16_t num_cmpl_aggr_int;
32476 * Bitfield that indicates which parameters are to be applied. Only
32477 * required when configuring devices with notification queues, and
32478 * used in that case to set certain parameters on completion queues
32479 * and others on notification queues.
32483 * This bit must be '1' for the num_cmpl_dma_aggr field to be
32486 #define HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_ENABLES_NUM_CMPL_DMA_AGGR \
32489 * This bit must be '1' for the num_cmpl_dma_aggr_during_int field to be
32492 #define HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_ENABLES_NUM_CMPL_DMA_AGGR_DURING_INT \
32495 * This bit must be '1' for the cmpl_aggr_dma_tmr field to be
32498 #define HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_ENABLES_CMPL_AGGR_DMA_TMR \
32501 * This bit must be '1' for the int_lat_tmr_min field to be
32504 #define HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_ENABLES_INT_LAT_TMR_MIN \
32507 * This bit must be '1' for the int_lat_tmr_max field to be
32510 #define HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_ENABLES_INT_LAT_TMR_MAX \
32513 * This bit must be '1' for the num_cmpl_aggr_int field to be
32516 #define HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_ENABLES_NUM_CMPL_AGGR_INT \
32518 uint8_t unused_0[4];
32521 /* hwrm_ring_cmpl_ring_cfg_aggint_params_output (size:128b/16B) */
32522 struct hwrm_ring_cmpl_ring_cfg_aggint_params_output {
32523 /* The specific error status for the command. */
32524 uint16_t error_code;
32525 /* The HWRM command request type. */
32527 /* The sequence ID from the original command. */
32529 /* The length of the response data in number of bytes. */
32531 uint8_t unused_0[7];
32533 * This field is used in Output records to indicate that the output
32534 * is completely written to RAM. This field should be read as '1'
32535 * to indicate that the output has been completely written.
32536 * When writing a command completion or response to an internal processor,
32537 * the order of writes has to be such that this field is written last.
32542 /***********************
32543 * hwrm_ring_grp_alloc *
32544 ***********************/
32547 /* hwrm_ring_grp_alloc_input (size:192b/24B) */
32548 struct hwrm_ring_grp_alloc_input {
32549 /* The HWRM command request type. */
32552 * The completion ring to send the completion event on. This should
32553 * be the NQ ID returned from the `nq_alloc` HWRM command.
32555 uint16_t cmpl_ring;
32557 * The sequence ID is used by the driver for tracking multiple
32558 * commands. This ID is treated as opaque data by the firmware and
32559 * the value is returned in the `hwrm_resp_hdr` upon completion.
32563 * The target ID of the command:
32564 * * 0x0-0xFFF8 - The function ID
32565 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
32566 * * 0xFFFD - Reserved for user-space HWRM interface
32569 uint16_t target_id;
32571 * A physical address pointer pointing to a host buffer that the
32572 * command's response data will be written. This can be either a host
32573 * physical address (HPA) or a guest physical address (GPA) and must
32574 * point to a physically contiguous block of memory.
32576 uint64_t resp_addr;
32578 * This value identifies the CR associated with the ring
32583 * This value identifies the main RR associated with the ring
32588 * This value identifies the aggregation RR associated with
32589 * the ring group. If this value is 0xFF... (All Fs), then no
32590 * Aggregation ring will be set.
32594 * This value identifies the statistics context associated
32595 * with the ring group.
32600 /* hwrm_ring_grp_alloc_output (size:128b/16B) */
32601 struct hwrm_ring_grp_alloc_output {
32602 /* The specific error status for the command. */
32603 uint16_t error_code;
32604 /* The HWRM command request type. */
32606 /* The sequence ID from the original command. */
32608 /* The length of the response data in number of bytes. */
32611 * This is the ring group ID value. Use this value to program
32612 * the default ring group for the VNIC or as table entries
32613 * in an RSS/COS context.
32615 uint32_t ring_group_id;
32616 uint8_t unused_0[3];
32618 * This field is used in Output records to indicate that the output
32619 * is completely written to RAM. This field should be read as '1'
32620 * to indicate that the output has been completely written.
32621 * When writing a command completion or response to an internal processor,
32622 * the order of writes has to be such that this field is written last.
32627 /**********************
32628 * hwrm_ring_grp_free *
32629 **********************/
32632 /* hwrm_ring_grp_free_input (size:192b/24B) */
32633 struct hwrm_ring_grp_free_input {
32634 /* The HWRM command request type. */
32637 * The completion ring to send the completion event on. This should
32638 * be the NQ ID returned from the `nq_alloc` HWRM command.
32640 uint16_t cmpl_ring;
32642 * The sequence ID is used by the driver for tracking multiple
32643 * commands. This ID is treated as opaque data by the firmware and
32644 * the value is returned in the `hwrm_resp_hdr` upon completion.
32648 * The target ID of the command:
32649 * * 0x0-0xFFF8 - The function ID
32650 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
32651 * * 0xFFFD - Reserved for user-space HWRM interface
32654 uint16_t target_id;
32656 * A physical address pointer pointing to a host buffer that the
32657 * command's response data will be written. This can be either a host
32658 * physical address (HPA) or a guest physical address (GPA) and must
32659 * point to a physically contiguous block of memory.
32661 uint64_t resp_addr;
32662 /* This is the ring group ID value. */
32663 uint32_t ring_group_id;
32664 uint8_t unused_0[4];
32667 /* hwrm_ring_grp_free_output (size:128b/16B) */
32668 struct hwrm_ring_grp_free_output {
32669 /* The specific error status for the command. */
32670 uint16_t error_code;
32671 /* The HWRM command request type. */
32673 /* The sequence ID from the original command. */
32675 /* The length of the response data in number of bytes. */
32677 uint8_t unused_0[7];
32679 * This field is used in Output records to indicate that the output
32680 * is completely written to RAM. This field should be read as '1'
32681 * to indicate that the output has been completely written.
32682 * When writing a command completion or response to an internal processor,
32683 * the order of writes has to be such that this field is written last.
32688 /************************
32689 * hwrm_ring_schq_alloc *
32690 ************************/
32693 /* hwrm_ring_schq_alloc_input (size:1088b/136B) */
32694 struct hwrm_ring_schq_alloc_input {
32695 /* The HWRM command request type. */
32698 * The completion ring to send the completion event on. This should
32699 * be the NQ ID returned from the `nq_alloc` HWRM command.
32701 uint16_t cmpl_ring;
32703 * The sequence ID is used by the driver for tracking multiple
32704 * commands. This ID is treated as opaque data by the firmware and
32705 * the value is returned in the `hwrm_resp_hdr` upon completion.
32709 * The target ID of the command:
32710 * * 0x0-0xFFF8 - The function ID
32711 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
32712 * * 0xFFFD - Reserved for user-space HWRM interface
32715 uint16_t target_id;
32717 * A physical address pointer pointing to a host buffer that the
32718 * command's response data will be written. This can be either a host
32719 * physical address (HPA) or a guest physical address (GPA) and must
32720 * point to a physically contiguous block of memory.
32722 uint64_t resp_addr;
32725 * This bit must be '1' for the tqm_ring0 fields to be
32728 #define HWRM_RING_SCHQ_ALLOC_INPUT_ENABLES_TQM_RING0 UINT32_C(0x1)
32730 * This bit must be '1' for the tqm_ring1 fields to be
32733 #define HWRM_RING_SCHQ_ALLOC_INPUT_ENABLES_TQM_RING1 UINT32_C(0x2)
32735 * This bit must be '1' for the tqm_ring2 fields to be
32738 #define HWRM_RING_SCHQ_ALLOC_INPUT_ENABLES_TQM_RING2 UINT32_C(0x4)
32740 * This bit must be '1' for the tqm_ring3 fields to be
32743 #define HWRM_RING_SCHQ_ALLOC_INPUT_ENABLES_TQM_RING3 UINT32_C(0x8)
32745 * This bit must be '1' for the tqm_ring4 fields to be
32748 #define HWRM_RING_SCHQ_ALLOC_INPUT_ENABLES_TQM_RING4 UINT32_C(0x10)
32750 * This bit must be '1' for the tqm_ring5 fields to be
32753 #define HWRM_RING_SCHQ_ALLOC_INPUT_ENABLES_TQM_RING5 UINT32_C(0x20)
32755 * This bit must be '1' for the tqm_ring6 fields to be
32758 #define HWRM_RING_SCHQ_ALLOC_INPUT_ENABLES_TQM_RING6 UINT32_C(0x40)
32760 * This bit must be '1' for the tqm_ring7 fields to be
32763 #define HWRM_RING_SCHQ_ALLOC_INPUT_ENABLES_TQM_RING7 UINT32_C(0x80)
32764 /* Reserved for future use. */
32766 /* TQM ring 0 page size and level. */
32767 uint8_t tqm_ring0_pg_size_tqm_ring0_lvl;
32768 /* TQM ring 0 PBL indirect levels. */
32769 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING0_LVL_MASK \
32771 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING0_LVL_SFT 0
32772 /* PBL pointer is physical start address. */
32773 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING0_LVL_LVL_0 \
32775 /* PBL pointer points to PTE table. */
32776 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING0_LVL_LVL_1 \
32779 * PBL pointer points to PDE table with each entry pointing to PTE
32782 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING0_LVL_LVL_2 \
32784 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING0_LVL_LAST \
32785 HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING0_LVL_LVL_2
32786 /* TQM ring 0 page size. */
32787 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING0_PG_SIZE_MASK \
32789 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING0_PG_SIZE_SFT 4
32791 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING0_PG_SIZE_PG_4K \
32792 (UINT32_C(0x0) << 4)
32794 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING0_PG_SIZE_PG_8K \
32795 (UINT32_C(0x1) << 4)
32797 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING0_PG_SIZE_PG_64K \
32798 (UINT32_C(0x2) << 4)
32800 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING0_PG_SIZE_PG_2M \
32801 (UINT32_C(0x3) << 4)
32803 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING0_PG_SIZE_PG_8M \
32804 (UINT32_C(0x4) << 4)
32806 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING0_PG_SIZE_PG_1G \
32807 (UINT32_C(0x5) << 4)
32808 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING0_PG_SIZE_LAST \
32809 HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING0_PG_SIZE_PG_1G
32810 /* TQM ring 1 page size and level. */
32811 uint8_t tqm_ring1_pg_size_tqm_ring1_lvl;
32812 /* TQM ring 1 PBL indirect levels. */
32813 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING1_LVL_MASK \
32815 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING1_LVL_SFT 0
32816 /* PBL pointer is physical start address. */
32817 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING1_LVL_LVL_0 \
32819 /* PBL pointer points to PTE table. */
32820 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING1_LVL_LVL_1 \
32823 * PBL pointer points to PDE table with each entry pointing to PTE
32826 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING1_LVL_LVL_2 \
32828 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING1_LVL_LAST \
32829 HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING1_LVL_LVL_2
32830 /* TQM ring 1 page size. */
32831 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING1_PG_SIZE_MASK \
32833 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING1_PG_SIZE_SFT 4
32835 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING1_PG_SIZE_PG_4K \
32836 (UINT32_C(0x0) << 4)
32838 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING1_PG_SIZE_PG_8K \
32839 (UINT32_C(0x1) << 4)
32841 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING1_PG_SIZE_PG_64K \
32842 (UINT32_C(0x2) << 4)
32844 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING1_PG_SIZE_PG_2M \
32845 (UINT32_C(0x3) << 4)
32847 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING1_PG_SIZE_PG_8M \
32848 (UINT32_C(0x4) << 4)
32850 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING1_PG_SIZE_PG_1G \
32851 (UINT32_C(0x5) << 4)
32852 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING1_PG_SIZE_LAST \
32853 HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING1_PG_SIZE_PG_1G
32854 /* TQM ring 2 page size and level. */
32855 uint8_t tqm_ring2_pg_size_tqm_ring2_lvl;
32856 /* TQM ring 2 PBL indirect levels. */
32857 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING2_LVL_MASK \
32859 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING2_LVL_SFT 0
32860 /* PBL pointer is physical start address. */
32861 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING2_LVL_LVL_0 \
32863 /* PBL pointer points to PTE table. */
32864 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING2_LVL_LVL_1 \
32867 * PBL pointer points to PDE table with each entry pointing to PTE
32870 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING2_LVL_LVL_2 \
32872 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING2_LVL_LAST \
32873 HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING2_LVL_LVL_2
32874 /* TQM ring 2 page size. */
32875 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING2_PG_SIZE_MASK \
32877 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING2_PG_SIZE_SFT 4
32879 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING2_PG_SIZE_PG_4K \
32880 (UINT32_C(0x0) << 4)
32882 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING2_PG_SIZE_PG_8K \
32883 (UINT32_C(0x1) << 4)
32885 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING2_PG_SIZE_PG_64K \
32886 (UINT32_C(0x2) << 4)
32888 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING2_PG_SIZE_PG_2M \
32889 (UINT32_C(0x3) << 4)
32891 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING2_PG_SIZE_PG_8M \
32892 (UINT32_C(0x4) << 4)
32894 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING2_PG_SIZE_PG_1G \
32895 (UINT32_C(0x5) << 4)
32896 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING2_PG_SIZE_LAST \
32897 HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING2_PG_SIZE_PG_1G
32898 /* TQM ring 3 page size and level. */
32899 uint8_t tqm_ring3_pg_size_tqm_ring3_lvl;
32900 /* TQM ring 3 PBL indirect levels. */
32901 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING3_LVL_MASK \
32903 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING3_LVL_SFT 0
32904 /* PBL pointer is physical start address. */
32905 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING3_LVL_LVL_0 \
32907 /* PBL pointer points to PTE table. */
32908 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING3_LVL_LVL_1 \
32911 * PBL pointer points to PDE table with each entry pointing to PTE
32914 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING3_LVL_LVL_2 \
32916 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING3_LVL_LAST \
32917 HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING3_LVL_LVL_2
32918 /* TQM ring 3 page size. */
32919 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING3_PG_SIZE_MASK \
32921 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING3_PG_SIZE_SFT 4
32923 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING3_PG_SIZE_PG_4K \
32924 (UINT32_C(0x0) << 4)
32926 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING3_PG_SIZE_PG_8K \
32927 (UINT32_C(0x1) << 4)
32929 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING3_PG_SIZE_PG_64K \
32930 (UINT32_C(0x2) << 4)
32932 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING3_PG_SIZE_PG_2M \
32933 (UINT32_C(0x3) << 4)
32935 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING3_PG_SIZE_PG_8M \
32936 (UINT32_C(0x4) << 4)
32938 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING3_PG_SIZE_PG_1G \
32939 (UINT32_C(0x5) << 4)
32940 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING3_PG_SIZE_LAST \
32941 HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING3_PG_SIZE_PG_1G
32942 /* TQM ring 4 page size and level. */
32943 uint8_t tqm_ring4_pg_size_tqm_ring4_lvl;
32944 /* TQM ring 4 PBL indirect levels. */
32945 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING4_LVL_MASK \
32947 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING4_LVL_SFT 0
32948 /* PBL pointer is physical start address. */
32949 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING4_LVL_LVL_0 \
32951 /* PBL pointer points to PTE table. */
32952 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING4_LVL_LVL_1 \
32955 * PBL pointer points to PDE table with each entry pointing to PTE
32958 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING4_LVL_LVL_2 \
32960 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING4_LVL_LAST \
32961 HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING4_LVL_LVL_2
32962 /* TQM ring 4 page size. */
32963 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING4_PG_SIZE_MASK \
32965 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING4_PG_SIZE_SFT 4
32967 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING4_PG_SIZE_PG_4K \
32968 (UINT32_C(0x0) << 4)
32970 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING4_PG_SIZE_PG_8K \
32971 (UINT32_C(0x1) << 4)
32973 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING4_PG_SIZE_PG_64K \
32974 (UINT32_C(0x2) << 4)
32976 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING4_PG_SIZE_PG_2M \
32977 (UINT32_C(0x3) << 4)
32979 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING4_PG_SIZE_PG_8M \
32980 (UINT32_C(0x4) << 4)
32982 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING4_PG_SIZE_PG_1G \
32983 (UINT32_C(0x5) << 4)
32984 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING4_PG_SIZE_LAST \
32985 HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING4_PG_SIZE_PG_1G
32986 /* TQM ring 5 page size and level. */
32987 uint8_t tqm_ring5_pg_size_tqm_ring5_lvl;
32988 /* TQM ring 5 PBL indirect levels. */
32989 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING5_LVL_MASK \
32991 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING5_LVL_SFT 0
32992 /* PBL pointer is physical start address. */
32993 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING5_LVL_LVL_0 \
32995 /* PBL pointer points to PTE table. */
32996 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING5_LVL_LVL_1 \
32999 * PBL pointer points to PDE table with each entry pointing to PTE
33002 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING5_LVL_LVL_2 \
33004 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING5_LVL_LAST \
33005 HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING5_LVL_LVL_2
33006 /* TQM ring 5 page size. */
33007 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING5_PG_SIZE_MASK \
33009 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING5_PG_SIZE_SFT 4
33011 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING5_PG_SIZE_PG_4K \
33012 (UINT32_C(0x0) << 4)
33014 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING5_PG_SIZE_PG_8K \
33015 (UINT32_C(0x1) << 4)
33017 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING5_PG_SIZE_PG_64K \
33018 (UINT32_C(0x2) << 4)
33020 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING5_PG_SIZE_PG_2M \
33021 (UINT32_C(0x3) << 4)
33023 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING5_PG_SIZE_PG_8M \
33024 (UINT32_C(0x4) << 4)
33026 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING5_PG_SIZE_PG_1G \
33027 (UINT32_C(0x5) << 4)
33028 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING5_PG_SIZE_LAST \
33029 HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING5_PG_SIZE_PG_1G
33030 /* TQM ring 6 page size and level. */
33031 uint8_t tqm_ring6_pg_size_tqm_ring6_lvl;
33032 /* TQM ring 6 PBL indirect levels. */
33033 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING6_LVL_MASK \
33035 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING6_LVL_SFT 0
33036 /* PBL pointer is physical start address. */
33037 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING6_LVL_LVL_0 \
33039 /* PBL pointer points to PTE table. */
33040 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING6_LVL_LVL_1 \
33043 * PBL pointer points to PDE table with each entry pointing to PTE
33046 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING6_LVL_LVL_2 \
33048 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING6_LVL_LAST \
33049 HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING6_LVL_LVL_2
33050 /* TQM ring 6 page size. */
33051 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING6_PG_SIZE_MASK \
33053 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING6_PG_SIZE_SFT 4
33055 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING6_PG_SIZE_PG_4K \
33056 (UINT32_C(0x0) << 4)
33058 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING6_PG_SIZE_PG_8K \
33059 (UINT32_C(0x1) << 4)
33061 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING6_PG_SIZE_PG_64K \
33062 (UINT32_C(0x2) << 4)
33064 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING6_PG_SIZE_PG_2M \
33065 (UINT32_C(0x3) << 4)
33067 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING6_PG_SIZE_PG_8M \
33068 (UINT32_C(0x4) << 4)
33070 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING6_PG_SIZE_PG_1G \
33071 (UINT32_C(0x5) << 4)
33072 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING6_PG_SIZE_LAST \
33073 HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING6_PG_SIZE_PG_1G
33074 /* TQM ring 7 page size and level. */
33075 uint8_t tqm_ring7_pg_size_tqm_ring7_lvl;
33076 /* TQM ring 7 PBL indirect levels. */
33077 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING7_LVL_MASK \
33079 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING7_LVL_SFT 0
33080 /* PBL pointer is physical start address. */
33081 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING7_LVL_LVL_0 \
33083 /* PBL pointer points to PTE table. */
33084 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING7_LVL_LVL_1 \
33087 * PBL pointer points to PDE table with each entry pointing to PTE
33090 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING7_LVL_LVL_2 \
33092 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING7_LVL_LAST \
33093 HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING7_LVL_LVL_2
33094 /* TQM ring 7 page size. */
33095 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING7_PG_SIZE_MASK \
33097 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING7_PG_SIZE_SFT 4
33099 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING7_PG_SIZE_PG_4K \
33100 (UINT32_C(0x0) << 4)
33102 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING7_PG_SIZE_PG_8K \
33103 (UINT32_C(0x1) << 4)
33105 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING7_PG_SIZE_PG_64K \
33106 (UINT32_C(0x2) << 4)
33108 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING7_PG_SIZE_PG_2M \
33109 (UINT32_C(0x3) << 4)
33111 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING7_PG_SIZE_PG_8M \
33112 (UINT32_C(0x4) << 4)
33114 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING7_PG_SIZE_PG_1G \
33115 (UINT32_C(0x5) << 4)
33116 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING7_PG_SIZE_LAST \
33117 HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING7_PG_SIZE_PG_1G
33118 /* TQM ring 0 page directory. */
33119 uint64_t tqm_ring0_page_dir;
33120 /* TQM ring 1 page directory. */
33121 uint64_t tqm_ring1_page_dir;
33122 /* TQM ring 2 page directory. */
33123 uint64_t tqm_ring2_page_dir;
33124 /* TQM ring 3 page directory. */
33125 uint64_t tqm_ring3_page_dir;
33126 /* TQM ring 4 page directory. */
33127 uint64_t tqm_ring4_page_dir;
33128 /* TQM ring 5 page directory. */
33129 uint64_t tqm_ring5_page_dir;
33130 /* TQM ring 6 page directory. */
33131 uint64_t tqm_ring6_page_dir;
33132 /* TQM ring 7 page directory. */
33133 uint64_t tqm_ring7_page_dir;
33135 * Number of TQM ring 0 entries.
33137 * TQM fastpath rings should be sized large enough to accommodate the
33138 * maximum number of QPs (either L2 or RoCE, or both if shared)
33139 * that can be enqueued to the TQM ring.
33141 * Note that TQM ring sizes cannot be extended while the system is
33142 * operational. If a PF driver needs to extend a TQM ring, it needs
33143 * to delete the SCHQ and then reallocate it.
33145 uint32_t tqm_ring0_num_entries;
33147 * Number of TQM ring 1 entries.
33149 * TQM fastpath rings should be sized large enough to accommodate the
33150 * maximum number of QPs (either L2 or RoCE, or both if shared)
33151 * that can be enqueued to the TQM ring.
33153 * Note that TQM ring sizes cannot be extended while the system is
33154 * operational. If a PF driver needs to extend a TQM ring, it needs
33155 * to delete the SCHQ and then reallocate it.
33157 uint32_t tqm_ring1_num_entries;
33159 * Number of TQM ring 2 entries.
33161 * TQM fastpath rings should be sized large enough to accommodate the
33162 * maximum number of QPs (either L2 or RoCE, or both if shared)
33163 * that can be enqueued to the TQM ring.
33165 * Note that TQM ring sizes cannot be extended while the system is
33166 * operational. If a PF driver needs to extend a TQM ring, it needs
33167 * to delete the SCHQ and then reallocate it.
33169 uint32_t tqm_ring2_num_entries;
33171 * Number of TQM ring 3 entries.
33173 * TQM fastpath rings should be sized large enough to accommodate the
33174 * maximum number of QPs (either L2 or RoCE, or both if shared)
33175 * that can be enqueued to the TQM ring.
33177 * Note that TQM ring sizes cannot be extended while the system is
33178 * operational. If a PF driver needs to extend a TQM ring, it needs
33179 * to delete the SCHQ and then reallocate it.
33181 uint32_t tqm_ring3_num_entries;
33183 * Number of TQM ring 4 entries.
33185 * TQM fastpath rings should be sized large enough to accommodate the
33186 * maximum number of QPs (either L2 or RoCE, or both if shared)
33187 * that can be enqueued to the TQM ring.
33189 * Note that TQM ring sizes cannot be extended while the system is
33190 * operational. If a PF driver needs to extend a TQM ring, it needs
33191 * to delete the SCHQ and then reallocate it.
33193 uint32_t tqm_ring4_num_entries;
33195 * Number of TQM ring 5 entries.
33197 * TQM fastpath rings should be sized large enough to accommodate the
33198 * maximum number of QPs (either L2 or RoCE, or both if shared)
33199 * that can be enqueued to the TQM ring.
33201 * Note that TQM ring sizes cannot be extended while the system is
33202 * operational. If a PF driver needs to extend a TQM ring, it needs
33203 * to delete the SCHQ and then reallocate it.
33205 uint32_t tqm_ring5_num_entries;
33207 * Number of TQM ring 6 entries.
33209 * TQM fastpath rings should be sized large enough to accommodate the
33210 * maximum number of QPs (either L2 or RoCE, or both if shared)
33211 * that can be enqueued to the TQM ring.
33213 * Note that TQM ring sizes cannot be extended while the system is
33214 * operational. If a PF driver needs to extend a TQM ring, it needs
33215 * to delete the SCHQ and then reallocate it.
33217 uint32_t tqm_ring6_num_entries;
33219 * Number of TQM ring 7 entries.
33221 * TQM fastpath rings should be sized large enough to accommodate the
33222 * maximum number of QPs (either L2 or RoCE, or both if shared)
33223 * that can be enqueued to the TQM ring.
33225 * Note that TQM ring sizes cannot be extended while the system is
33226 * operational. If a PF driver needs to extend a TQM ring, it needs
33227 * to delete the SCHQ and then reallocate it.
33229 uint32_t tqm_ring7_num_entries;
33230 /* Number of bytes that have been allocated for each context entry. */
33231 uint16_t tqm_entry_size;
33232 uint8_t unused_0[6];
33235 /* hwrm_ring_schq_alloc_output (size:128b/16B) */
33236 struct hwrm_ring_schq_alloc_output {
33237 /* The specific error status for the command. */
33238 uint16_t error_code;
33239 /* The HWRM command request type. */
33241 /* The sequence ID from the original command. */
33243 /* The length of the response data in number of bytes. */
33246 * This is an identifier for the SCHQ to be used in other HWRM commands
33247 * that need to reference this SCHQ. This value is greater than zero
33248 * (i.e. a schq_id of zero references the default SCHQ).
33251 uint8_t unused_0[5];
33253 * This field is used in Output records to indicate that the output
33254 * is completely written to RAM. This field should be read as '1'
33255 * to indicate that the output has been completely written.
33256 * When writing a command completion or response to an internal processor,
33257 * the order of writes has to be such that this field is written last.
33262 /**********************
33263 * hwrm_ring_schq_cfg *
33264 **********************/
33267 /* hwrm_ring_schq_cfg_input (size:768b/96B) */
33268 struct hwrm_ring_schq_cfg_input {
33269 /* The HWRM command request type. */
33272 * The completion ring to send the completion event on. This should
33273 * be the NQ ID returned from the `nq_alloc` HWRM command.
33275 uint16_t cmpl_ring;
33277 * The sequence ID is used by the driver for tracking multiple
33278 * commands. This ID is treated as opaque data by the firmware and
33279 * the value is returned in the `hwrm_resp_hdr` upon completion.
33283 * The target ID of the command:
33284 * * 0x0-0xFFF8 - The function ID
33285 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
33286 * * 0xFFFD - Reserved for user-space HWRM interface
33289 uint16_t target_id;
33291 * A physical address pointer pointing to a host buffer that the
33292 * command's response data will be written. This can be either a host
33293 * physical address (HPA) or a guest physical address (GPA) and must
33294 * point to a physically contiguous block of memory.
33296 uint64_t resp_addr;
33298 * Identifies the SCHQ being configured. A schq_id of zero refers to
33299 * the default SCHQ.
33303 * This field is an 8 bit bitmap that indicates which TCs are enabled
33304 * in this SCHQ. Bit 0 represents traffic class 0 and bit 7 represents
33307 uint8_t tc_enabled;
33310 /* The tc_max_bw array and the max_bw parameters are valid */
33311 #define HWRM_RING_SCHQ_CFG_INPUT_FLAGS_TC_MAX_BW_ENABLED \
33313 /* The tc_min_bw array is valid */
33314 #define HWRM_RING_SCHQ_CFG_INPUT_FLAGS_TC_MIN_BW_ENABLED \
33316 /* Maximum bandwidth of the traffic class, specified in Mbps. */
33317 uint32_t max_bw_tc0;
33318 /* Maximum bandwidth of the traffic class, specified in Mbps. */
33319 uint32_t max_bw_tc1;
33320 /* Maximum bandwidth of the traffic class, specified in Mbps. */
33321 uint32_t max_bw_tc2;
33322 /* Maximum bandwidth of the traffic class, specified in Mbps. */
33323 uint32_t max_bw_tc3;
33324 /* Maximum bandwidth of the traffic class, specified in Mbps. */
33325 uint32_t max_bw_tc4;
33326 /* Maximum bandwidth of the traffic class, specified in Mbps. */
33327 uint32_t max_bw_tc5;
33328 /* Maximum bandwidth of the traffic class, specified in Mbps. */
33329 uint32_t max_bw_tc6;
33330 /* Maximum bandwidth of the traffic class, specified in Mbps. */
33331 uint32_t max_bw_tc7;
33333 * Bandwidth reservation for the traffic class, specified in Mbps.
33334 * A value of zero signifies that traffic belonging to this class
33335 * shares the bandwidth reservation for the same traffic class of
33336 * the default SCHQ.
33338 uint32_t min_bw_tc0;
33340 * Bandwidth reservation for the traffic class, specified in Mbps.
33341 * A value of zero signifies that traffic belonging to this class
33342 * shares the bandwidth reservation for the same traffic class of
33343 * the default SCHQ.
33345 uint32_t min_bw_tc1;
33347 * Bandwidth reservation for the traffic class, specified in Mbps.
33348 * A value of zero signifies that traffic belonging to this class
33349 * shares the bandwidth reservation for the same traffic class of
33350 * the default SCHQ.
33352 uint32_t min_bw_tc2;
33354 * Bandwidth reservation for the traffic class, specified in Mbps.
33355 * A value of zero signifies that traffic belonging to this class
33356 * shares the bandwidth reservation for the same traffic class of
33357 * the default SCHQ.
33359 uint32_t min_bw_tc3;
33361 * Bandwidth reservation for the traffic class, specified in Mbps.
33362 * A value of zero signifies that traffic belonging to this class
33363 * shares the bandwidth reservation for the same traffic class of
33364 * the default SCHQ.
33366 uint32_t min_bw_tc4;
33368 * Bandwidth reservation for the traffic class, specified in Mbps.
33369 * A value of zero signifies that traffic belonging to this class
33370 * shares the bandwidth reservation for the same traffic class of
33371 * the default SCHQ.
33373 uint32_t min_bw_tc5;
33375 * Bandwidth reservation for the traffic class, specified in Mbps.
33376 * A value of zero signifies that traffic belonging to this class
33377 * shares the bandwidth reservation for the same traffic class of
33378 * the default SCHQ.
33380 uint32_t min_bw_tc6;
33382 * Bandwidth reservation for the traffic class, specified in Mbps.
33383 * A value of zero signifies that traffic belonging to this class
33384 * shares the bandwidth reservation for the same traffic class of
33385 * the default SCHQ.
33387 uint32_t min_bw_tc7;
33389 * Indicates the max bandwidth for all enabled traffic classes in
33390 * this SCHQ, specified in Mbps.
33393 uint8_t unused_1[4];
33396 /* hwrm_ring_schq_cfg_output (size:128b/16B) */
33397 struct hwrm_ring_schq_cfg_output {
33398 /* The specific error status for the command. */
33399 uint16_t error_code;
33400 /* The HWRM command request type. */
33402 /* The sequence ID from the original command. */
33404 /* The length of the response data in number of bytes. */
33406 uint8_t unused_0[7];
33408 * This field is used in Output records to indicate that the output
33409 * is completely written to RAM. This field should be read as '1'
33410 * to indicate that the output has been completely written.
33411 * When writing a command completion or response to an internal processor,
33412 * the order of writes has to be such that this field is written last.
33417 /***********************
33418 * hwrm_ring_schq_free *
33419 ***********************/
33422 /* hwrm_ring_schq_free_input (size:192b/24B) */
33423 struct hwrm_ring_schq_free_input {
33424 /* The HWRM command request type. */
33427 * The completion ring to send the completion event on. This should
33428 * be the NQ ID returned from the `nq_alloc` HWRM command.
33430 uint16_t cmpl_ring;
33432 * The sequence ID is used by the driver for tracking multiple
33433 * commands. This ID is treated as opaque data by the firmware and
33434 * the value is returned in the `hwrm_resp_hdr` upon completion.
33438 * The target ID of the command:
33439 * * 0x0-0xFFF8 - The function ID
33440 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
33441 * * 0xFFFD - Reserved for user-space HWRM interface
33444 uint16_t target_id;
33446 * A physical address pointer pointing to a host buffer that the
33447 * command's response data will be written. This can be either a host
33448 * physical address (HPA) or a guest physical address (GPA) and must
33449 * point to a physically contiguous block of memory.
33451 uint64_t resp_addr;
33452 /* Identifies the SCHQ being freed. */
33454 uint8_t unused_0[6];
33457 /* hwrm_ring_schq_free_output (size:128b/16B) */
33458 struct hwrm_ring_schq_free_output {
33459 /* The specific error status for the command. */
33460 uint16_t error_code;
33461 /* The HWRM command request type. */
33463 /* The sequence ID from the original command. */
33465 /* The length of the response data in number of bytes. */
33467 uint8_t unused_0[7];
33469 * This field is used in Output records to indicate that the output
33470 * is completely written to RAM. This field should be read as '1'
33471 * to indicate that the output has been completely written.
33472 * When writing a command completion or response to an internal processor,
33473 * the order of writes has to be such that this field is written last.
33478 * special reserved flow ID to identify per function default
33479 * flows for vSwitch offload
33481 #define DEFAULT_FLOW_ID 0xFFFFFFFFUL
33483 * special reserved flow ID to identify per function RoCEv1
33486 #define ROCEV1_FLOW_ID 0xFFFFFFFEUL
33488 * special reserved flow ID to identify per function RoCEv2
33491 #define ROCEV2_FLOW_ID 0xFFFFFFFDUL
33493 * special reserved flow ID to identify per function RoCEv2
33496 #define ROCEV2_CNP_FLOW_ID 0xFFFFFFFCUL
33498 /****************************
33499 * hwrm_cfa_l2_filter_alloc *
33500 ****************************/
33503 /* hwrm_cfa_l2_filter_alloc_input (size:768b/96B) */
33504 struct hwrm_cfa_l2_filter_alloc_input {
33505 /* The HWRM command request type. */
33508 * The completion ring to send the completion event on. This should
33509 * be the NQ ID returned from the `nq_alloc` HWRM command.
33511 uint16_t cmpl_ring;
33513 * The sequence ID is used by the driver for tracking multiple
33514 * commands. This ID is treated as opaque data by the firmware and
33515 * the value is returned in the `hwrm_resp_hdr` upon completion.
33519 * The target ID of the command:
33520 * * 0x0-0xFFF8 - The function ID
33521 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
33522 * * 0xFFFD - Reserved for user-space HWRM interface
33525 uint16_t target_id;
33527 * A physical address pointer pointing to a host buffer that the
33528 * command's response data will be written. This can be either a host
33529 * physical address (HPA) or a guest physical address (GPA) and must
33530 * point to a physically contiguous block of memory.
33532 uint64_t resp_addr;
33535 * Enumeration denoting the RX, TX type of the resource.
33536 * This enumeration is used for resources that are similar for both
33537 * TX and RX paths of the chip.
33539 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_PATH \
33542 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_PATH_TX \
33545 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_PATH_RX \
33547 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_PATH_LAST \
33548 HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_PATH_RX
33550 * Setting of this flag indicates the applicability to the loopback
33553 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_LOOPBACK \
33556 * Setting of this flag indicates drop action. If this flag is not
33557 * set, then it should be considered accept action.
33559 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_DROP \
33562 * If this flag is set, all t_l2_* fields are invalid
33563 * and they should not be specified.
33564 * If this flag is set, then l2_* fields refer to
33565 * fields of outermost L2 header.
33567 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_OUTERMOST \
33570 * Enumeration denoting NO_ROCE_L2 to support old drivers.
33571 * New driver L2 for only L2 traffic, ROCE for roce and l2 traffic
33573 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_TRAFFIC_MASK \
33575 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_TRAFFIC_SFT 4
33576 /* To support old drivers */
33577 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_TRAFFIC_NO_ROCE_L2 \
33578 (UINT32_C(0x0) << 4)
33579 /* Only L2 traffic */
33580 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_TRAFFIC_L2 \
33581 (UINT32_C(0x1) << 4)
33582 /* Roce & L2 traffic */
33583 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_TRAFFIC_ROCE \
33584 (UINT32_C(0x2) << 4)
33585 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_TRAFFIC_LAST \
33586 HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_TRAFFIC_ROCE
33588 * Setting of this flag indicates that no XDP filter is created with
33590 * 0 - legacy behavior, XDP filter is created with L2 filter
33591 * 1 - XDP filter won't be created with L2 filter
33593 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_XDP_DISABLE \
33596 * Setting this flag to 1 indicate the L2 fields in this command
33597 * pertain to source fields. Setting this flag to 0 indicate the
33598 * L2 fields in this command pertain to the destination fields
33599 * and this is the default/legacy behavior.
33601 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_SOURCE_VALID \
33605 * This bit must be '1' for the l2_addr field to be
33608 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_ADDR \
33611 * This bit must be '1' for the l2_addr_mask field to be
33614 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_ADDR_MASK \
33617 * This bit must be '1' for the l2_ovlan field to be
33620 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_OVLAN \
33623 * This bit must be '1' for the l2_ovlan_mask field to be
33626 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_OVLAN_MASK \
33629 * This bit must be '1' for the l2_ivlan field to be
33632 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN \
33635 * This bit must be '1' for the l2_ivlan_mask field to be
33638 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN_MASK \
33641 * This bit must be '1' for the t_l2_addr field to be
33644 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_T_L2_ADDR \
33647 * This bit must be '1' for the t_l2_addr_mask field to be
33650 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_T_L2_ADDR_MASK \
33653 * This bit must be '1' for the t_l2_ovlan field to be
33656 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_T_L2_OVLAN \
33659 * This bit must be '1' for the t_l2_ovlan_mask field to be
33662 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_T_L2_OVLAN_MASK \
33665 * This bit must be '1' for the t_l2_ivlan field to be
33668 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_T_L2_IVLAN \
33671 * This bit must be '1' for the t_l2_ivlan_mask field to be
33674 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_T_L2_IVLAN_MASK \
33677 * This bit must be '1' for the src_type field to be
33680 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_SRC_TYPE \
33683 * This bit must be '1' for the src_id field to be
33686 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_SRC_ID \
33689 * This bit must be '1' for the tunnel_type field to be
33692 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_TUNNEL_TYPE \
33695 * This bit must be '1' for the dst_id field to be
33698 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_DST_ID \
33701 * This bit must be '1' for the mirror_vnic_id field to be
33704 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_MIRROR_VNIC_ID \
33707 * This bit must be '1' for the num_vlans field to be
33710 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_NUM_VLANS \
33713 * This bit must be '1' for the t_num_vlans field to be
33716 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_T_NUM_VLANS \
33719 * This value sets the match value for the L2 MAC address.
33720 * Destination MAC address for RX path.
33721 * Source MAC address for TX path.
33723 uint8_t l2_addr[6];
33724 /* This value sets the match value for the number of VLANs. */
33727 * This value sets the match value for the number of VLANs
33728 * in the tunnel headers.
33730 uint8_t t_num_vlans;
33732 * This value sets the mask value for the L2 address.
33733 * A value of 0 will mask the corresponding bit from
33736 uint8_t l2_addr_mask[6];
33737 /* This value sets VLAN ID value for outer VLAN. */
33740 * This value sets the mask value for the ovlan id.
33741 * A value of 0 will mask the corresponding bit from
33744 uint16_t l2_ovlan_mask;
33745 /* This value sets VLAN ID value for inner VLAN. */
33748 * This value sets the mask value for the ivlan id.
33749 * A value of 0 will mask the corresponding bit from
33752 uint16_t l2_ivlan_mask;
33753 uint8_t unused_1[2];
33755 * This value sets the match value for the tunnel
33757 * Destination MAC address for RX path.
33758 * Source MAC address for TX path.
33760 uint8_t t_l2_addr[6];
33761 uint8_t unused_2[2];
33763 * This value sets the mask value for the tunnel L2
33765 * A value of 0 will mask the corresponding bit from
33768 uint8_t t_l2_addr_mask[6];
33769 /* This value sets VLAN ID value for tunnel outer VLAN. */
33770 uint16_t t_l2_ovlan;
33772 * This value sets the mask value for the tunnel ovlan id.
33773 * A value of 0 will mask the corresponding bit from
33776 uint16_t t_l2_ovlan_mask;
33777 /* This value sets VLAN ID value for tunnel inner VLAN. */
33778 uint16_t t_l2_ivlan;
33780 * This value sets the mask value for the tunnel ivlan id.
33781 * A value of 0 will mask the corresponding bit from
33784 uint16_t t_l2_ivlan_mask;
33785 /* This value identifies the type of source of the packet. */
33788 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_SRC_TYPE_NPORT UINT32_C(0x0)
33789 /* Physical function */
33790 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_SRC_TYPE_PF UINT32_C(0x1)
33791 /* Virtual function */
33792 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_SRC_TYPE_VF UINT32_C(0x2)
33793 /* Virtual NIC of a function */
33794 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_SRC_TYPE_VNIC UINT32_C(0x3)
33795 /* Embedded processor for CFA management */
33796 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_SRC_TYPE_KONG UINT32_C(0x4)
33797 /* Embedded processor for OOB management */
33798 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_SRC_TYPE_APE UINT32_C(0x5)
33799 /* Embedded processor for RoCE */
33800 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_SRC_TYPE_BONO UINT32_C(0x6)
33801 /* Embedded processor for network proxy functions */
33802 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_SRC_TYPE_TANG UINT32_C(0x7)
33803 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_SRC_TYPE_LAST \
33804 HWRM_CFA_L2_FILTER_ALLOC_INPUT_SRC_TYPE_TANG
33807 * This value is the id of the source.
33808 * For a network port, it represents port_id.
33809 * For a physical function, it represents fid.
33810 * For a virtual function, it represents vf_id.
33811 * For a vnic, it represents vnic_id.
33812 * For embedded processors, this id is not valid.
33815 * 1. The function ID is implied if it src_id is
33816 * not provided for a src_type that is either
33820 uint8_t tunnel_type;
33822 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_TUNNEL_TYPE_NONTUNNEL \
33824 /* Virtual eXtensible Local Area Network (VXLAN) */
33825 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_TUNNEL_TYPE_VXLAN \
33827 /* Network Virtualization Generic Routing Encapsulation (NVGRE) */
33828 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_TUNNEL_TYPE_NVGRE \
33830 /* Generic Routing Encapsulation (GRE) inside Ethernet payload */
33831 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_TUNNEL_TYPE_L2GRE \
33834 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_TUNNEL_TYPE_IPIP \
33836 /* Generic Network Virtualization Encapsulation (Geneve) */
33837 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_TUNNEL_TYPE_GENEVE \
33839 /* Multi-Protocol Label Switching (MPLS) */
33840 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_TUNNEL_TYPE_MPLS \
33842 /* Stateless Transport Tunnel (STT) */
33843 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_TUNNEL_TYPE_STT \
33845 /* Generic Routing Encapsulation (GRE) inside IP datagram payload */
33846 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_TUNNEL_TYPE_IPGRE \
33848 /* IPV4 over virtual eXtensible Local Area Network (IPV4oVXLAN) */
33849 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_TUNNEL_TYPE_VXLAN_V4 \
33852 * Enhance Generic Routing Encapsulation (GRE version 1) inside IP
33855 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_TUNNEL_TYPE_IPGRE_V1 \
33857 /* Use fixed layer 2 ether type of 0xFFFF */
33858 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_TUNNEL_TYPE_L2_ETYPE \
33861 * IPV6 over virtual eXtensible Local Area Network with GPE header
33864 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_TUNNEL_TYPE_VXLAN_GPE_V6 \
33866 /* Any tunneled traffic */
33867 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_TUNNEL_TYPE_ANYTUNNEL \
33869 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_TUNNEL_TYPE_LAST \
33870 HWRM_CFA_L2_FILTER_ALLOC_INPUT_TUNNEL_TYPE_ANYTUNNEL
33873 * If set, this value shall represent the
33874 * Logical VNIC ID of the destination VNIC for the RX
33875 * path and network port id of the destination port for
33880 * Logical VNIC ID of the VNIC where traffic is
33883 uint16_t mirror_vnic_id;
33885 * This hint is provided to help in placing
33886 * the filter in the filter table.
33889 /* No preference */
33890 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_PRI_HINT_NO_PREFER \
33892 /* Above the given filter */
33893 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_PRI_HINT_ABOVE_FILTER \
33895 /* Below the given filter */
33896 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_PRI_HINT_BELOW_FILTER \
33898 /* As high as possible */
33899 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_PRI_HINT_MAX \
33901 /* As low as possible */
33902 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_PRI_HINT_MIN \
33904 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_PRI_HINT_LAST \
33905 HWRM_CFA_L2_FILTER_ALLOC_INPUT_PRI_HINT_MIN
33909 * This is the ID of the filter that goes along with
33912 * This field is valid only for the following values.
33913 * 1 - Above the given filter
33914 * 2 - Below the given filter
33916 uint64_t l2_filter_id_hint;
33919 /* hwrm_cfa_l2_filter_alloc_output (size:192b/24B) */
33920 struct hwrm_cfa_l2_filter_alloc_output {
33921 /* The specific error status for the command. */
33922 uint16_t error_code;
33923 /* The HWRM command request type. */
33925 /* The sequence ID from the original command. */
33927 /* The length of the response data in number of bytes. */
33930 * This value identifies a set of CFA data structures used for an L2
33933 uint64_t l2_filter_id;
33935 * The flow id value in bit 0-29 is the actual ID of the flow
33936 * associated with this filter and it shall be used to match
33937 * and associate the flow identifier returned in completion
33938 * records. A value of 0xFFFFFFFF in the 32-bit flow_id field
33939 * shall indicate no valid flow id.
33942 /* Indicate the flow id value. */
33943 #define HWRM_CFA_L2_FILTER_ALLOC_OUTPUT_FLOW_ID_VALUE_MASK \
33944 UINT32_C(0x3fffffff)
33945 #define HWRM_CFA_L2_FILTER_ALLOC_OUTPUT_FLOW_ID_VALUE_SFT 0
33946 /* Indicate type of the flow. */
33947 #define HWRM_CFA_L2_FILTER_ALLOC_OUTPUT_FLOW_ID_TYPE \
33948 UINT32_C(0x40000000)
33950 * If this bit set to 0, then it indicates that the flow is
33953 #define HWRM_CFA_L2_FILTER_ALLOC_OUTPUT_FLOW_ID_TYPE_INT \
33954 (UINT32_C(0x0) << 30)
33956 * If this bit is set to 1, then it indicates that the flow is
33959 #define HWRM_CFA_L2_FILTER_ALLOC_OUTPUT_FLOW_ID_TYPE_EXT \
33960 (UINT32_C(0x1) << 30)
33961 #define HWRM_CFA_L2_FILTER_ALLOC_OUTPUT_FLOW_ID_TYPE_LAST \
33962 HWRM_CFA_L2_FILTER_ALLOC_OUTPUT_FLOW_ID_TYPE_EXT
33963 /* Indicate the flow direction. */
33964 #define HWRM_CFA_L2_FILTER_ALLOC_OUTPUT_FLOW_ID_DIR \
33965 UINT32_C(0x80000000)
33966 /* If this bit set to 0, then it indicates rx flow. */
33967 #define HWRM_CFA_L2_FILTER_ALLOC_OUTPUT_FLOW_ID_DIR_RX \
33968 (UINT32_C(0x0) << 31)
33969 /* If this bit is set to 1, then it indicates that tx flow. */
33970 #define HWRM_CFA_L2_FILTER_ALLOC_OUTPUT_FLOW_ID_DIR_TX \
33971 (UINT32_C(0x1) << 31)
33972 #define HWRM_CFA_L2_FILTER_ALLOC_OUTPUT_FLOW_ID_DIR_LAST \
33973 HWRM_CFA_L2_FILTER_ALLOC_OUTPUT_FLOW_ID_DIR_TX
33974 uint8_t unused_0[3];
33976 * This field is used in Output records to indicate that the output
33977 * is completely written to RAM. This field should be read as '1'
33978 * to indicate that the output has been completely written.
33979 * When writing a command completion or response to an internal
33980 * processor, the order of writes has to be such that this field is
33986 /***************************
33987 * hwrm_cfa_l2_filter_free *
33988 ***************************/
33991 /* hwrm_cfa_l2_filter_free_input (size:192b/24B) */
33992 struct hwrm_cfa_l2_filter_free_input {
33993 /* The HWRM command request type. */
33996 * The completion ring to send the completion event on. This should
33997 * be the NQ ID returned from the `nq_alloc` HWRM command.
33999 uint16_t cmpl_ring;
34001 * The sequence ID is used by the driver for tracking multiple
34002 * commands. This ID is treated as opaque data by the firmware and
34003 * the value is returned in the `hwrm_resp_hdr` upon completion.
34007 * The target ID of the command:
34008 * * 0x0-0xFFF8 - The function ID
34009 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
34010 * * 0xFFFD - Reserved for user-space HWRM interface
34013 uint16_t target_id;
34015 * A physical address pointer pointing to a host buffer that the
34016 * command's response data will be written. This can be either a host
34017 * physical address (HPA) or a guest physical address (GPA) and must
34018 * point to a physically contiguous block of memory.
34020 uint64_t resp_addr;
34022 * This value identifies a set of CFA data structures used for an L2
34025 uint64_t l2_filter_id;
34028 /* hwrm_cfa_l2_filter_free_output (size:128b/16B) */
34029 struct hwrm_cfa_l2_filter_free_output {
34030 /* The specific error status for the command. */
34031 uint16_t error_code;
34032 /* The HWRM command request type. */
34034 /* The sequence ID from the original command. */
34036 /* The length of the response data in number of bytes. */
34038 uint8_t unused_0[7];
34040 * This field is used in Output records to indicate that the output
34041 * is completely written to RAM. This field should be read as '1'
34042 * to indicate that the output has been completely written.
34043 * When writing a command completion or response to an internal
34044 * processor, the order of writes has to be such that this field is
34050 /**************************
34051 * hwrm_cfa_l2_filter_cfg *
34052 **************************/
34055 /* hwrm_cfa_l2_filter_cfg_input (size:320b/40B) */
34056 struct hwrm_cfa_l2_filter_cfg_input {
34057 /* The HWRM command request type. */
34060 * The completion ring to send the completion event on. This should
34061 * be the NQ ID returned from the `nq_alloc` HWRM command.
34063 uint16_t cmpl_ring;
34065 * The sequence ID is used by the driver for tracking multiple
34066 * commands. This ID is treated as opaque data by the firmware and
34067 * the value is returned in the `hwrm_resp_hdr` upon completion.
34071 * The target ID of the command:
34072 * * 0x0-0xFFF8 - The function ID
34073 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
34074 * * 0xFFFD - Reserved for user-space HWRM interface
34077 uint16_t target_id;
34079 * A physical address pointer pointing to a host buffer that the
34080 * command's response data will be written. This can be either a host
34081 * physical address (HPA) or a guest physical address (GPA) and must
34082 * point to a physically contiguous block of memory.
34084 uint64_t resp_addr;
34087 * Enumeration denoting the RX, TX type of the resource.
34088 * This enumeration is used for resources that are similar for both
34089 * TX and RX paths of the chip.
34091 #define HWRM_CFA_L2_FILTER_CFG_INPUT_FLAGS_PATH \
34094 #define HWRM_CFA_L2_FILTER_CFG_INPUT_FLAGS_PATH_TX \
34097 #define HWRM_CFA_L2_FILTER_CFG_INPUT_FLAGS_PATH_RX \
34099 #define HWRM_CFA_L2_FILTER_CFG_INPUT_FLAGS_PATH_LAST \
34100 HWRM_CFA_L2_FILTER_CFG_INPUT_FLAGS_PATH_RX
34102 * Setting of this flag indicates drop action. If this flag is not
34103 * set, then it should be considered accept action.
34105 #define HWRM_CFA_L2_FILTER_CFG_INPUT_FLAGS_DROP \
34108 * Enumeration denoting NO_ROCE_L2 to support old drivers.
34109 * New driver L2 for only L2 traffic, ROCE for roce and l2 traffic
34111 #define HWRM_CFA_L2_FILTER_CFG_INPUT_FLAGS_TRAFFIC_MASK \
34113 #define HWRM_CFA_L2_FILTER_CFG_INPUT_FLAGS_TRAFFIC_SFT 2
34114 /* To support old drivers */
34115 #define HWRM_CFA_L2_FILTER_CFG_INPUT_FLAGS_TRAFFIC_NO_ROCE_L2 \
34116 (UINT32_C(0x0) << 2)
34117 /* Only L2 traffic */
34118 #define HWRM_CFA_L2_FILTER_CFG_INPUT_FLAGS_TRAFFIC_L2 \
34119 (UINT32_C(0x1) << 2)
34120 /* Roce & L2 traffic */
34121 #define HWRM_CFA_L2_FILTER_CFG_INPUT_FLAGS_TRAFFIC_ROCE \
34122 (UINT32_C(0x2) << 2)
34123 #define HWRM_CFA_L2_FILTER_CFG_INPUT_FLAGS_TRAFFIC_LAST \
34124 HWRM_CFA_L2_FILTER_CFG_INPUT_FLAGS_TRAFFIC_ROCE
34127 * This bit must be '1' for the dst_id field to be
34130 #define HWRM_CFA_L2_FILTER_CFG_INPUT_ENABLES_DST_ID \
34133 * This bit must be '1' for the new_mirror_vnic_id field to be
34136 #define HWRM_CFA_L2_FILTER_CFG_INPUT_ENABLES_NEW_MIRROR_VNIC_ID \
34139 * This value identifies a set of CFA data structures used for an L2
34142 uint64_t l2_filter_id;
34144 * If set, this value shall represent the
34145 * Logical VNIC ID of the destination VNIC for the RX
34146 * path and network port id of the destination port for
34151 * New Logical VNIC ID of the VNIC where traffic is
34154 uint32_t new_mirror_vnic_id;
34157 /* hwrm_cfa_l2_filter_cfg_output (size:128b/16B) */
34158 struct hwrm_cfa_l2_filter_cfg_output {
34159 /* The specific error status for the command. */
34160 uint16_t error_code;
34161 /* The HWRM command request type. */
34163 /* The sequence ID from the original command. */
34165 /* The length of the response data in number of bytes. */
34167 uint8_t unused_0[7];
34169 * This field is used in Output records to indicate that the output
34170 * is completely written to RAM. This field should be read as '1'
34171 * to indicate that the output has been completely written.
34172 * When writing a command completion or response to an internal
34173 * processor, the order of writes has to be such that this field is
34179 /***************************
34180 * hwrm_cfa_l2_set_rx_mask *
34181 ***************************/
34184 /* hwrm_cfa_l2_set_rx_mask_input (size:448b/56B) */
34185 struct hwrm_cfa_l2_set_rx_mask_input {
34186 /* The HWRM command request type. */
34189 * The completion ring to send the completion event on. This should
34190 * be the NQ ID returned from the `nq_alloc` HWRM command.
34192 uint16_t cmpl_ring;
34194 * The sequence ID is used by the driver for tracking multiple
34195 * commands. This ID is treated as opaque data by the firmware and
34196 * the value is returned in the `hwrm_resp_hdr` upon completion.
34200 * The target ID of the command:
34201 * * 0x0-0xFFF8 - The function ID
34202 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
34203 * * 0xFFFD - Reserved for user-space HWRM interface
34206 uint16_t target_id;
34208 * A physical address pointer pointing to a host buffer that the
34209 * command's response data will be written. This can be either a host
34210 * physical address (HPA) or a guest physical address (GPA) and must
34211 * point to a physically contiguous block of memory.
34213 uint64_t resp_addr;
34218 * When this bit is '1', the function is requested to accept
34219 * multi-cast packets specified by the multicast addr table.
34221 #define HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_MCAST \
34224 * When this bit is '1', the function is requested to accept
34225 * all multi-cast packets.
34227 #define HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_ALL_MCAST \
34230 * When this bit is '1', the function is requested to accept
34231 * broadcast packets.
34233 #define HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_BCAST \
34236 * When this bit is '1', the function is requested to be
34237 * put in the promiscuous mode.
34239 * The HWRM should accept any function to set up
34240 * promiscuous mode.
34242 * The HWRM shall follow the semantics below for the
34243 * promiscuous mode support.
34244 * # When partitioning is not enabled on a port
34245 * (i.e. single PF on the port), then the PF shall
34246 * be allowed to be in the promiscuous mode. When the
34247 * PF is in the promiscuous mode, then it shall
34248 * receive all host bound traffic on that port.
34249 * # When partitioning is enabled on a port
34250 * (i.e. multiple PFs per port) and a PF on that
34251 * port is in the promiscuous mode, then the PF
34252 * receives all traffic within that partition as
34253 * identified by a unique identifier for the
34254 * PF (e.g. S-Tag). If a unique outer VLAN
34255 * for the PF is specified, then the setting of
34256 * promiscuous mode on that PF shall result in the
34257 * PF receiving all host bound traffic with matching
34259 * # A VF shall can be set in the promiscuous mode.
34260 * In the promiscuous mode, the VF does not receive any
34261 * traffic unless a unique outer VLAN for the
34262 * VF is specified. If a unique outer VLAN
34263 * for the VF is specified, then the setting of
34264 * promiscuous mode on that VF shall result in the
34265 * VF receiving all host bound traffic with the
34266 * matching outer VLAN.
34267 * # The HWRM shall allow the setting of promiscuous
34268 * mode on a function independently from the
34269 * promiscuous mode settings on other functions.
34271 #define HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_PROMISCUOUS \
34274 * If this flag is set, the corresponding RX
34275 * filters shall be set up to cover multicast/broadcast
34276 * filters for the outermost Layer 2 destination MAC
34279 #define HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_OUTERMOST \
34282 * If this flag is set, the corresponding RX
34283 * filters shall be set up to cover multicast/broadcast
34284 * filters for the VLAN-tagged packets that match the
34285 * TPID and VID fields of VLAN tags in the VLAN tag
34286 * table specified in this command.
34288 #define HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_VLANONLY \
34291 * If this flag is set, the corresponding RX
34292 * filters shall be set up to cover multicast/broadcast
34293 * filters for non-VLAN tagged packets and VLAN-tagged
34294 * packets that match the TPID and VID fields of VLAN
34295 * tags in the VLAN tag table specified in this command.
34297 #define HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_VLAN_NONVLAN \
34300 * If this flag is set, the corresponding RX
34301 * filters shall be set up to cover multicast/broadcast
34302 * filters for non-VLAN tagged packets and VLAN-tagged
34303 * packets matching any VLAN tag.
34305 * If this flag is set, then the HWRM shall ignore
34306 * VLAN tags specified in vlan_tag_tbl.
34308 * If none of vlanonly, vlan_nonvlan, and anyvlan_nonvlan
34309 * flags is set, then the HWRM shall ignore
34310 * VLAN tags specified in vlan_tag_tbl.
34312 * The HWRM client shall set at most one flag out of
34313 * vlanonly, vlan_nonvlan, and anyvlan_nonvlan.
34315 #define HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_ANYVLAN_NONVLAN \
34317 /* This is the address for mcast address tbl. */
34318 uint64_t mc_tbl_addr;
34320 * This value indicates how many entries in mc_tbl are valid.
34321 * Each entry is 6 bytes.
34323 uint32_t num_mc_entries;
34324 uint8_t unused_0[4];
34326 * This is the address for VLAN tag table.
34327 * Each VLAN entry in the table is 4 bytes of a VLAN tag
34328 * including TPID, PCP, DEI, and VID fields in network byte
34331 uint64_t vlan_tag_tbl_addr;
34333 * This value indicates how many entries in vlan_tag_tbl are
34334 * valid. Each entry is 4 bytes.
34336 uint32_t num_vlan_tags;
34337 uint8_t unused_1[4];
34340 /* hwrm_cfa_l2_set_rx_mask_output (size:128b/16B) */
34341 struct hwrm_cfa_l2_set_rx_mask_output {
34342 /* The specific error status for the command. */
34343 uint16_t error_code;
34344 /* The HWRM command request type. */
34346 /* The sequence ID from the original command. */
34348 /* The length of the response data in number of bytes. */
34350 uint8_t unused_0[7];
34352 * This field is used in Output records to indicate that the output
34353 * is completely written to RAM. This field should be read as '1'
34354 * to indicate that the output has been completely written.
34355 * When writing a command completion or response to an internal
34356 * processor, the order of writes has to be such that this field is
34362 /* hwrm_cfa_l2_set_rx_mask_cmd_err (size:64b/8B) */
34363 struct hwrm_cfa_l2_set_rx_mask_cmd_err {
34365 * command specific error codes that goes to
34366 * the cmd_err field in Common HWRM Error Response.
34369 /* Unknown error */
34370 #define HWRM_CFA_L2_SET_RX_MASK_CMD_ERR_CODE_UNKNOWN \
34372 /* Unable to complete operation due to conflict with Ntuple Filter */
34373 #define HWRM_CFA_L2_SET_RX_MASK_CMD_ERR_CODE_NTUPLE_FILTER_CONFLICT_ERR \
34375 #define HWRM_CFA_L2_SET_RX_MASK_CMD_ERR_CODE_LAST \
34376 HWRM_CFA_L2_SET_RX_MASK_CMD_ERR_CODE_NTUPLE_FILTER_CONFLICT_ERR
34377 uint8_t unused_0[7];
34380 /*******************************
34381 * hwrm_cfa_vlan_antispoof_cfg *
34382 *******************************/
34385 /* hwrm_cfa_vlan_antispoof_cfg_input (size:256b/32B) */
34386 struct hwrm_cfa_vlan_antispoof_cfg_input {
34387 /* The HWRM command request type. */
34390 * The completion ring to send the completion event on. This should
34391 * be the NQ ID returned from the `nq_alloc` HWRM command.
34393 uint16_t cmpl_ring;
34395 * The sequence ID is used by the driver for tracking multiple
34396 * commands. This ID is treated as opaque data by the firmware and
34397 * the value is returned in the `hwrm_resp_hdr` upon completion.
34401 * The target ID of the command:
34402 * * 0x0-0xFFF8 - The function ID
34403 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
34404 * * 0xFFFD - Reserved for user-space HWRM interface
34407 uint16_t target_id;
34409 * A physical address pointer pointing to a host buffer that the
34410 * command's response data will be written. This can be either a host
34411 * physical address (HPA) or a guest physical address (GPA) and must
34412 * point to a physically contiguous block of memory.
34414 uint64_t resp_addr;
34416 * Function ID of the function that is being configured.
34417 * Only valid for a VF FID configured by the PF.
34420 uint8_t unused_0[2];
34421 /* Number of VLAN entries in the vlan_tag_mask_tbl. */
34422 uint32_t num_vlan_entries;
34424 * The vlan_tag_mask_tbl_addr is the DMA address of the VLAN
34425 * antispoof table. Each table entry contains the 16-bit TPID
34426 * (0x8100 or 0x88a8 only), 16-bit VLAN ID, and a 16-bit mask,
34427 * all in network order to match hwrm_cfa_l2_set_rx_mask.
34428 * For an individual VLAN entry, the mask value should be 0xfff
34429 * for the 12-bit VLAN ID.
34431 uint64_t vlan_tag_mask_tbl_addr;
34434 /* hwrm_cfa_vlan_antispoof_cfg_output (size:128b/16B) */
34435 struct hwrm_cfa_vlan_antispoof_cfg_output {
34436 /* The specific error status for the command. */
34437 uint16_t error_code;
34438 /* The HWRM command request type. */
34440 /* The sequence ID from the original command. */
34442 /* The length of the response data in number of bytes. */
34444 uint8_t unused_0[7];
34446 * This field is used in Output records to indicate that the output
34447 * is completely written to RAM. This field should be read as '1'
34448 * to indicate that the output has been completely written.
34449 * When writing a command completion or response to an internal
34450 * processor, the order of writes has to be such that this field is
34456 /********************************
34457 * hwrm_cfa_vlan_antispoof_qcfg *
34458 ********************************/
34461 /* hwrm_cfa_vlan_antispoof_qcfg_input (size:256b/32B) */
34462 struct hwrm_cfa_vlan_antispoof_qcfg_input {
34463 /* The HWRM command request type. */
34466 * The completion ring to send the completion event on. This should
34467 * be the NQ ID returned from the `nq_alloc` HWRM command.
34469 uint16_t cmpl_ring;
34471 * The sequence ID is used by the driver for tracking multiple
34472 * commands. This ID is treated as opaque data by the firmware and
34473 * the value is returned in the `hwrm_resp_hdr` upon completion.
34477 * The target ID of the command:
34478 * * 0x0-0xFFF8 - The function ID
34479 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
34480 * * 0xFFFD - Reserved for user-space HWRM interface
34483 uint16_t target_id;
34485 * A physical address pointer pointing to a host buffer that the
34486 * command's response data will be written. This can be either a host
34487 * physical address (HPA) or a guest physical address (GPA) and must
34488 * point to a physically contiguous block of memory.
34490 uint64_t resp_addr;
34492 * Function ID of the function that is being queried.
34493 * Only valid for a VF FID queried by the PF.
34496 uint8_t unused_0[2];
34498 * Maximum number of VLAN entries the firmware is allowed to DMA
34499 * to vlan_tag_mask_tbl.
34501 uint32_t max_vlan_entries;
34503 * The vlan_tag_mask_tbl_addr is the DMA address of the VLAN
34504 * antispoof table to which firmware will DMA to. Each table
34505 * entry will contain the 16-bit TPID (0x8100 or 0x88a8 only),
34506 * 16-bit VLAN ID, and a 16-bit mask, all in network order to
34507 * match hwrm_cfa_l2_set_rx_mask. For an individual VLAN entry,
34508 * the mask value should be 0xfff for the 12-bit VLAN ID.
34510 uint64_t vlan_tag_mask_tbl_addr;
34513 /* hwrm_cfa_vlan_antispoof_qcfg_output (size:128b/16B) */
34514 struct hwrm_cfa_vlan_antispoof_qcfg_output {
34515 /* The specific error status for the command. */
34516 uint16_t error_code;
34517 /* The HWRM command request type. */
34519 /* The sequence ID from the original command. */
34521 /* The length of the response data in number of bytes. */
34523 /* Number of valid entries DMAd by firmware to vlan_tag_mask_tbl. */
34524 uint32_t num_vlan_entries;
34525 uint8_t unused_0[3];
34527 * This field is used in Output records to indicate that the output
34528 * is completely written to RAM. This field should be read as '1'
34529 * to indicate that the output has been completely written.
34530 * When writing a command completion or response to an internal
34531 * processor, the order of writes has to be such that this field is
34537 /********************************
34538 * hwrm_cfa_tunnel_filter_alloc *
34539 ********************************/
34542 /* hwrm_cfa_tunnel_filter_alloc_input (size:704b/88B) */
34543 struct hwrm_cfa_tunnel_filter_alloc_input {
34544 /* The HWRM command request type. */
34547 * The completion ring to send the completion event on. This should
34548 * be the NQ ID returned from the `nq_alloc` HWRM command.
34550 uint16_t cmpl_ring;
34552 * The sequence ID is used by the driver for tracking multiple
34553 * commands. This ID is treated as opaque data by the firmware and
34554 * the value is returned in the `hwrm_resp_hdr` upon completion.
34558 * The target ID of the command:
34559 * * 0x0-0xFFF8 - The function ID
34560 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
34561 * * 0xFFFD - Reserved for user-space HWRM interface
34564 uint16_t target_id;
34566 * A physical address pointer pointing to a host buffer that the
34567 * command's response data will be written. This can be either a host
34568 * physical address (HPA) or a guest physical address (GPA) and must
34569 * point to a physically contiguous block of memory.
34571 uint64_t resp_addr;
34574 * Setting of this flag indicates the applicability to the loopback
34577 #define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_FLAGS_LOOPBACK \
34581 * This bit must be '1' for the l2_filter_id field to be
34584 #define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_ENABLES_L2_FILTER_ID \
34587 * This bit must be '1' for the l2_addr field to be
34590 #define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_ENABLES_L2_ADDR \
34593 * This bit must be '1' for the l2_ivlan field to be
34596 #define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN \
34599 * This bit must be '1' for the l3_addr field to be
34602 #define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_ENABLES_L3_ADDR \
34605 * This bit must be '1' for the l3_addr_type field to be
34608 #define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_ENABLES_L3_ADDR_TYPE \
34611 * This bit must be '1' for the t_l3_addr_type field to be
34614 #define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_ENABLES_T_L3_ADDR_TYPE \
34617 * This bit must be '1' for the t_l3_addr field to be
34620 #define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_ENABLES_T_L3_ADDR \
34623 * This bit must be '1' for the tunnel_type field to be
34626 #define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_ENABLES_TUNNEL_TYPE \
34629 * This bit must be '1' for the vni field to be
34632 #define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_ENABLES_VNI \
34635 * This bit must be '1' for the dst_vnic_id field to be
34638 #define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_ENABLES_DST_VNIC_ID \
34641 * This bit must be '1' for the mirror_vnic_id field to be
34644 #define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_ENABLES_MIRROR_VNIC_ID \
34647 * This value identifies a set of CFA data structures used for an L2
34650 uint64_t l2_filter_id;
34652 * This value sets the match value for the inner L2
34654 * Destination MAC address for RX path.
34655 * Source MAC address for TX path.
34657 uint8_t l2_addr[6];
34659 * This value sets VLAN ID value for inner VLAN.
34660 * Only 12-bits of VLAN ID are used in setting the filter.
34664 * The value of inner destination IP address to be used in filtering.
34665 * For IPv4, first four bytes represent the IP address.
34667 uint32_t l3_addr[4];
34669 * The value of tunnel destination IP address to be used in filtering.
34670 * For IPv4, first four bytes represent the IP address.
34672 uint32_t t_l3_addr[4];
34674 * This value indicates the type of inner IP address.
34677 * All others are invalid.
34679 uint8_t l3_addr_type;
34681 * This value indicates the type of tunnel IP address.
34684 * All others are invalid.
34686 uint8_t t_l3_addr_type;
34688 uint8_t tunnel_type;
34690 #define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_TUNNEL_TYPE_NONTUNNEL \
34692 /* Virtual eXtensible Local Area Network (VXLAN) */
34693 #define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_TUNNEL_TYPE_VXLAN \
34695 /* Network Virtualization Generic Routing Encapsulation (NVGRE) */
34696 #define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_TUNNEL_TYPE_NVGRE \
34698 /* Generic Routing Encapsulation (GRE) inside Ethernet payload */
34699 #define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_TUNNEL_TYPE_L2GRE \
34702 #define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_TUNNEL_TYPE_IPIP \
34704 /* Generic Network Virtualization Encapsulation (Geneve) */
34705 #define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_TUNNEL_TYPE_GENEVE \
34707 /* Multi-Protocol Label Switching (MPLS) */
34708 #define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_TUNNEL_TYPE_MPLS \
34710 /* Stateless Transport Tunnel (STT) */
34711 #define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_TUNNEL_TYPE_STT \
34713 /* Generic Routing Encapsulation (GRE) inside IP datagram payload */
34714 #define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_TUNNEL_TYPE_IPGRE \
34716 /* IPV4 over virtual eXtensible Local Area Network (IPV4oVXLAN) */
34717 #define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_TUNNEL_TYPE_VXLAN_V4 \
34720 * Enhance Generic Routing Encapsulation (GRE version 1) inside IP
34723 #define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_TUNNEL_TYPE_IPGRE_V1 \
34725 /* Use fixed layer 2 ether type of 0xFFFF */
34726 #define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_TUNNEL_TYPE_L2_ETYPE \
34729 * IPV6 over virtual eXtensible Local Area Network with GPE header
34732 #define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_TUNNEL_TYPE_VXLAN_GPE_V6 \
34734 /* Any tunneled traffic */
34735 #define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_TUNNEL_TYPE_ANYTUNNEL \
34737 #define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_TUNNEL_TYPE_LAST \
34738 HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_TUNNEL_TYPE_ANYTUNNEL
34740 * tunnel_flags allows the user to indicate the tunnel tag detection
34741 * for the tunnel type specified in tunnel_type.
34743 uint8_t tunnel_flags;
34745 * If the tunnel_type is geneve, then this bit indicates if we
34746 * need to match the geneve OAM packet.
34747 * If the tunnel_type is nvgre or gre, then this bit indicates if
34748 * we need to detect checksum present bit in geneve header.
34749 * If the tunnel_type is mpls, then this bit indicates if we need
34750 * to match mpls packet with explicit IPV4/IPV6 null header.
34752 #define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_TUNNEL_FLAGS_TUN_FLAGS_OAM_CHECKSUM_EXPLHDR \
34755 * If the tunnel_type is geneve, then this bit indicates if we
34756 * need to detect the critical option bit set in the oam packet.
34757 * If the tunnel_type is nvgre or gre, then this bit indicates
34758 * if we need to match nvgre packets with key present bit set in
34760 * If the tunnel_type is mpls, then this bit indicates if we
34761 * need to match mpls packet with S bit from inner/second label.
34763 #define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_TUNNEL_FLAGS_TUN_FLAGS_CRITICAL_OPT_S1 \
34766 * If the tunnel_type is geneve, then this bit indicates if we
34767 * need to match geneve packet with extended header bit set in
34769 * If the tunnel_type is nvgre or gre, then this bit indicates
34770 * if we need to match nvgre packets with sequence number
34771 * present bit set in gre header.
34772 * If the tunnel_type is mpls, then this bit indicates if we
34773 * need to match mpls packet with S bit from out/first label.
34775 #define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_TUNNEL_FLAGS_TUN_FLAGS_EXTHDR_SEQNUM_S0 \
34778 * Virtual Network Identifier (VNI). Only valid with
34779 * tunnel_types VXLAN, NVGRE, and Geneve.
34780 * Only lower 24-bits of VNI field are used
34781 * in setting up the filter.
34784 /* Logical VNIC ID of the destination VNIC. */
34785 uint32_t dst_vnic_id;
34787 * Logical VNIC ID of the VNIC where traffic is
34790 uint32_t mirror_vnic_id;
34793 /* hwrm_cfa_tunnel_filter_alloc_output (size:192b/24B) */
34794 struct hwrm_cfa_tunnel_filter_alloc_output {
34795 /* The specific error status for the command. */
34796 uint16_t error_code;
34797 /* The HWRM command request type. */
34799 /* The sequence ID from the original command. */
34801 /* The length of the response data in number of bytes. */
34803 /* This value is an opaque id into CFA data structures. */
34804 uint64_t tunnel_filter_id;
34806 * The flow id value in bit 0-29 is the actual ID of the flow
34807 * associated with this filter and it shall be used to match
34808 * and associate the flow identifier returned in completion
34809 * records. A value of 0xFFFFFFFF in the 32-bit flow_id field
34810 * shall indicate no valid flow id.
34813 /* Indicate the flow id value. */
34814 #define HWRM_CFA_TUNNEL_FILTER_ALLOC_OUTPUT_FLOW_ID_VALUE_MASK \
34815 UINT32_C(0x3fffffff)
34816 #define HWRM_CFA_TUNNEL_FILTER_ALLOC_OUTPUT_FLOW_ID_VALUE_SFT 0
34817 /* Indicate type of the flow. */
34818 #define HWRM_CFA_TUNNEL_FILTER_ALLOC_OUTPUT_FLOW_ID_TYPE \
34819 UINT32_C(0x40000000)
34821 * If this bit set to 0, then it indicates that the flow is
34824 #define HWRM_CFA_TUNNEL_FILTER_ALLOC_OUTPUT_FLOW_ID_TYPE_INT \
34825 (UINT32_C(0x0) << 30)
34827 * If this bit is set to 1, then it indicates that the flow is
34830 #define HWRM_CFA_TUNNEL_FILTER_ALLOC_OUTPUT_FLOW_ID_TYPE_EXT \
34831 (UINT32_C(0x1) << 30)
34832 #define HWRM_CFA_TUNNEL_FILTER_ALLOC_OUTPUT_FLOW_ID_TYPE_LAST \
34833 HWRM_CFA_TUNNEL_FILTER_ALLOC_OUTPUT_FLOW_ID_TYPE_EXT
34834 /* Indicate the flow direction. */
34835 #define HWRM_CFA_TUNNEL_FILTER_ALLOC_OUTPUT_FLOW_ID_DIR \
34836 UINT32_C(0x80000000)
34837 /* If this bit set to 0, then it indicates rx flow. */
34838 #define HWRM_CFA_TUNNEL_FILTER_ALLOC_OUTPUT_FLOW_ID_DIR_RX \
34839 (UINT32_C(0x0) << 31)
34840 /* If this bit is set to 1, then it indicates that tx flow. */
34841 #define HWRM_CFA_TUNNEL_FILTER_ALLOC_OUTPUT_FLOW_ID_DIR_TX \
34842 (UINT32_C(0x1) << 31)
34843 #define HWRM_CFA_TUNNEL_FILTER_ALLOC_OUTPUT_FLOW_ID_DIR_LAST \
34844 HWRM_CFA_TUNNEL_FILTER_ALLOC_OUTPUT_FLOW_ID_DIR_TX
34845 uint8_t unused_0[3];
34847 * This field is used in Output records to indicate that the output
34848 * is completely written to RAM. This field should be read as '1'
34849 * to indicate that the output has been completely written.
34850 * When writing a command completion or response to an internal
34851 * processor, the order of writes has to be such that this field is
34857 /*******************************
34858 * hwrm_cfa_tunnel_filter_free *
34859 *******************************/
34862 /* hwrm_cfa_tunnel_filter_free_input (size:192b/24B) */
34863 struct hwrm_cfa_tunnel_filter_free_input {
34864 /* The HWRM command request type. */
34867 * The completion ring to send the completion event on. This should
34868 * be the NQ ID returned from the `nq_alloc` HWRM command.
34870 uint16_t cmpl_ring;
34872 * The sequence ID is used by the driver for tracking multiple
34873 * commands. This ID is treated as opaque data by the firmware and
34874 * the value is returned in the `hwrm_resp_hdr` upon completion.
34878 * The target ID of the command:
34879 * * 0x0-0xFFF8 - The function ID
34880 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
34881 * * 0xFFFD - Reserved for user-space HWRM interface
34884 uint16_t target_id;
34886 * A physical address pointer pointing to a host buffer that the
34887 * command's response data will be written. This can be either a host
34888 * physical address (HPA) or a guest physical address (GPA) and must
34889 * point to a physically contiguous block of memory.
34891 uint64_t resp_addr;
34892 /* This value is an opaque id into CFA data structures. */
34893 uint64_t tunnel_filter_id;
34896 /* hwrm_cfa_tunnel_filter_free_output (size:128b/16B) */
34897 struct hwrm_cfa_tunnel_filter_free_output {
34898 /* The specific error status for the command. */
34899 uint16_t error_code;
34900 /* The HWRM command request type. */
34902 /* The sequence ID from the original command. */
34904 /* The length of the response data in number of bytes. */
34906 uint8_t unused_0[7];
34908 * This field is used in Output records to indicate that the output
34909 * is completely written to RAM. This field should be read as '1'
34910 * to indicate that the output has been completely written.
34911 * When writing a command completion or response to an internal
34912 * processor, the order of writes has to be such that this field is
34918 /***************************************
34919 * hwrm_cfa_redirect_tunnel_type_alloc *
34920 ***************************************/
34923 /* hwrm_cfa_redirect_tunnel_type_alloc_input (size:192b/24B) */
34924 struct hwrm_cfa_redirect_tunnel_type_alloc_input {
34925 /* The HWRM command request type. */
34928 * The completion ring to send the completion event on. This should
34929 * be the NQ ID returned from the `nq_alloc` HWRM command.
34931 uint16_t cmpl_ring;
34933 * The sequence ID is used by the driver for tracking multiple
34934 * commands. This ID is treated as opaque data by the firmware and
34935 * the value is returned in the `hwrm_resp_hdr` upon completion.
34939 * The target ID of the command:
34940 * * 0x0-0xFFF8 - The function ID
34941 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
34942 * * 0xFFFD - Reserved for user-space HWRM interface
34945 uint16_t target_id;
34947 * A physical address pointer pointing to a host buffer that the
34948 * command's response data will be written. This can be either a host
34949 * physical address (HPA) or a guest physical address (GPA) and must
34950 * point to a physically contiguous block of memory.
34952 uint64_t resp_addr;
34953 /* The destination function id, to whom the traffic is redirected. */
34956 uint8_t tunnel_type;
34958 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_ALLOC_INPUT_TUNNEL_TYPE_NONTUNNEL \
34960 /* Virtual eXtensible Local Area Network (VXLAN) */
34961 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_ALLOC_INPUT_TUNNEL_TYPE_VXLAN \
34963 /* Network Virtualization Generic Routing Encapsulation (NVGRE) */
34964 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_ALLOC_INPUT_TUNNEL_TYPE_NVGRE \
34966 /* Generic Routing Encapsulation (GRE) inside Ethernet payload */
34967 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_ALLOC_INPUT_TUNNEL_TYPE_L2GRE \
34970 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_ALLOC_INPUT_TUNNEL_TYPE_IPIP \
34972 /* Generic Network Virtualization Encapsulation (Geneve) */
34973 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_ALLOC_INPUT_TUNNEL_TYPE_GENEVE \
34975 /* Multi-Protocol Label Switching (MPLS) */
34976 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_ALLOC_INPUT_TUNNEL_TYPE_MPLS \
34978 /* Stateless Transport Tunnel (STT) */
34979 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_ALLOC_INPUT_TUNNEL_TYPE_STT \
34981 /* Generic Routing Encapsulation (GRE) inside IP datagram payload */
34982 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_ALLOC_INPUT_TUNNEL_TYPE_IPGRE \
34984 /* IPV4 over virtual eXtensible Local Area Network (IPV4oVXLAN) */
34985 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_ALLOC_INPUT_TUNNEL_TYPE_VXLAN_V4 \
34988 * Enhance Generic Routing Encapsulation (GRE version 1) inside IP
34991 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_ALLOC_INPUT_TUNNEL_TYPE_IPGRE_V1 \
34993 /* Use fixed layer 2 ether type of 0xFFFF */
34994 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_ALLOC_INPUT_TUNNEL_TYPE_L2_ETYPE \
34997 * IPV6 over virtual eXtensible Local Area Network with GPE header
35000 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_ALLOC_INPUT_TUNNEL_TYPE_VXLAN_GPE_V6 \
35002 /* Any tunneled traffic */
35003 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_ALLOC_INPUT_TUNNEL_TYPE_ANYTUNNEL \
35005 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_ALLOC_INPUT_TUNNEL_TYPE_LAST \
35006 HWRM_CFA_REDIRECT_TUNNEL_TYPE_ALLOC_INPUT_TUNNEL_TYPE_ANYTUNNEL
35007 /* Tunnel alloc flags. */
35010 * Setting of this flag indicates modify existing redirect tunnel
35011 * to new destination function ID.
35013 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_ALLOC_INPUT_FLAGS_MODIFY_DST \
35015 uint8_t unused_0[4];
35018 /* hwrm_cfa_redirect_tunnel_type_alloc_output (size:128b/16B) */
35019 struct hwrm_cfa_redirect_tunnel_type_alloc_output {
35020 /* The specific error status for the command. */
35021 uint16_t error_code;
35022 /* The HWRM command request type. */
35024 /* The sequence ID from the original command. */
35026 /* The length of the response data in number of bytes. */
35028 uint8_t unused_0[7];
35030 * This field is used in Output records to indicate that the output
35031 * is completely written to RAM. This field should be read as '1'
35032 * to indicate that the output has been completely written.
35033 * When writing a command completion or response to an internal
35034 * processor, the order of writes has to be such that this field is
35040 /**************************************
35041 * hwrm_cfa_redirect_tunnel_type_free *
35042 **************************************/
35045 /* hwrm_cfa_redirect_tunnel_type_free_input (size:192b/24B) */
35046 struct hwrm_cfa_redirect_tunnel_type_free_input {
35047 /* The HWRM command request type. */
35050 * The completion ring to send the completion event on. This should
35051 * be the NQ ID returned from the `nq_alloc` HWRM command.
35053 uint16_t cmpl_ring;
35055 * The sequence ID is used by the driver for tracking multiple
35056 * commands. This ID is treated as opaque data by the firmware and
35057 * the value is returned in the `hwrm_resp_hdr` upon completion.
35061 * The target ID of the command:
35062 * * 0x0-0xFFF8 - The function ID
35063 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
35064 * * 0xFFFD - Reserved for user-space HWRM interface
35067 uint16_t target_id;
35069 * A physical address pointer pointing to a host buffer that the
35070 * command's response data will be written. This can be either a host
35071 * physical address (HPA) or a guest physical address (GPA) and must
35072 * point to a physically contiguous block of memory.
35074 uint64_t resp_addr;
35075 /* The destination function id, to whom the traffic is redirected. */
35078 uint8_t tunnel_type;
35080 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_FREE_INPUT_TUNNEL_TYPE_NONTUNNEL \
35082 /* Virtual eXtensible Local Area Network (VXLAN) */
35083 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_FREE_INPUT_TUNNEL_TYPE_VXLAN \
35085 /* Network Virtualization Generic Routing Encapsulation (NVGRE) */
35086 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_FREE_INPUT_TUNNEL_TYPE_NVGRE \
35088 /* Generic Routing Encapsulation (GRE) inside Ethernet payload */
35089 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_FREE_INPUT_TUNNEL_TYPE_L2GRE \
35092 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_FREE_INPUT_TUNNEL_TYPE_IPIP \
35094 /* Generic Network Virtualization Encapsulation (Geneve) */
35095 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_FREE_INPUT_TUNNEL_TYPE_GENEVE \
35097 /* Multi-Protocol Label Switching (MPLS) */
35098 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_FREE_INPUT_TUNNEL_TYPE_MPLS \
35100 /* Stateless Transport Tunnel (STT) */
35101 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_FREE_INPUT_TUNNEL_TYPE_STT \
35103 /* Generic Routing Encapsulation (GRE) inside IP datagram payload */
35104 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_FREE_INPUT_TUNNEL_TYPE_IPGRE \
35106 /* IPV4 over virtual eXtensible Local Area Network (IPV4oVXLAN) */
35107 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_FREE_INPUT_TUNNEL_TYPE_VXLAN_V4 \
35110 * Enhance Generic Routing Encapsulation (GRE version 1) inside IP
35113 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_FREE_INPUT_TUNNEL_TYPE_IPGRE_V1 \
35115 /* Use fixed layer 2 ether type of 0xFFFF */
35116 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_FREE_INPUT_TUNNEL_TYPE_L2_ETYPE \
35119 * IPV6 over virtual eXtensible Local Area Network with GPE header
35122 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_FREE_INPUT_TUNNEL_TYPE_VXLAN_GPE_V6 \
35124 /* Any tunneled traffic */
35125 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_FREE_INPUT_TUNNEL_TYPE_ANYTUNNEL \
35127 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_FREE_INPUT_TUNNEL_TYPE_LAST \
35128 HWRM_CFA_REDIRECT_TUNNEL_TYPE_FREE_INPUT_TUNNEL_TYPE_ANYTUNNEL
35129 uint8_t unused_0[5];
35132 /* hwrm_cfa_redirect_tunnel_type_free_output (size:128b/16B) */
35133 struct hwrm_cfa_redirect_tunnel_type_free_output {
35134 /* The specific error status for the command. */
35135 uint16_t error_code;
35136 /* The HWRM command request type. */
35138 /* The sequence ID from the original command. */
35140 /* The length of the response data in number of bytes. */
35142 uint8_t unused_0[7];
35144 * This field is used in Output records to indicate that the output
35145 * is completely written to RAM. This field should be read as '1'
35146 * to indicate that the output has been completely written.
35147 * When writing a command completion or response to an internal
35148 * processor, the order of writes has to be such that this field is
35154 /**************************************
35155 * hwrm_cfa_redirect_tunnel_type_info *
35156 **************************************/
35159 /* hwrm_cfa_redirect_tunnel_type_info_input (size:192b/24B) */
35160 struct hwrm_cfa_redirect_tunnel_type_info_input {
35161 /* The HWRM command request type. */
35164 * The completion ring to send the completion event on. This should
35165 * be the NQ ID returned from the `nq_alloc` HWRM command.
35167 uint16_t cmpl_ring;
35169 * The sequence ID is used by the driver for tracking multiple
35170 * commands. This ID is treated as opaque data by the firmware and
35171 * the value is returned in the `hwrm_resp_hdr` upon completion.
35175 * The target ID of the command:
35176 * * 0x0-0xFFF8 - The function ID
35177 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
35178 * * 0xFFFD - Reserved for user-space HWRM interface
35181 uint16_t target_id;
35183 * A physical address pointer pointing to a host buffer that the
35184 * command's response data will be written. This can be either a host
35185 * physical address (HPA) or a guest physical address (GPA) and must
35186 * point to a physically contiguous block of memory.
35188 uint64_t resp_addr;
35189 /* The source function id. */
35192 uint8_t tunnel_type;
35194 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_INFO_INPUT_TUNNEL_TYPE_NONTUNNEL \
35196 /* Virtual eXtensible Local Area Network (VXLAN) */
35197 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_INFO_INPUT_TUNNEL_TYPE_VXLAN \
35199 /* Network Virtualization Generic Routing Encapsulation (NVGRE) */
35200 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_INFO_INPUT_TUNNEL_TYPE_NVGRE \
35202 /* Generic Routing Encapsulation (GRE) inside Ethernet payload */
35203 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_INFO_INPUT_TUNNEL_TYPE_L2GRE \
35206 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_INFO_INPUT_TUNNEL_TYPE_IPIP \
35208 /* Generic Network Virtualization Encapsulation (Geneve) */
35209 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_INFO_INPUT_TUNNEL_TYPE_GENEVE \
35211 /* Multi-Protocol Label Switching (MPLS) */
35212 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_INFO_INPUT_TUNNEL_TYPE_MPLS \
35214 /* Stateless Transport Tunnel (STT) */
35215 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_INFO_INPUT_TUNNEL_TYPE_STT \
35217 /* Generic Routing Encapsulation (GRE) inside IP datagram payload */
35218 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_INFO_INPUT_TUNNEL_TYPE_IPGRE \
35220 /* IPV4 over virtual eXtensible Local Area Network (IPV4oVXLAN) */
35221 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_INFO_INPUT_TUNNEL_TYPE_VXLAN_V4 \
35224 * Enhance Generic Routing Encapsulation (GRE version 1) inside IP
35227 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_INFO_INPUT_TUNNEL_TYPE_IPGRE_V1 \
35229 /* Use fixed layer 2 ether type of 0xFFFF */
35230 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_INFO_INPUT_TUNNEL_TYPE_L2_ETYPE \
35233 * IPV6 over virtual eXtensible Local Area Network with GPE header
35236 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_INFO_INPUT_TUNNEL_TYPE_VXLAN_GPE_V6 \
35238 /* Any tunneled traffic */
35239 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_INFO_INPUT_TUNNEL_TYPE_ANYTUNNEL \
35241 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_INFO_INPUT_TUNNEL_TYPE_LAST \
35242 HWRM_CFA_REDIRECT_TUNNEL_TYPE_INFO_INPUT_TUNNEL_TYPE_ANYTUNNEL
35243 uint8_t unused_0[5];
35246 /* hwrm_cfa_redirect_tunnel_type_info_output (size:128b/16B) */
35247 struct hwrm_cfa_redirect_tunnel_type_info_output {
35248 /* The specific error status for the command. */
35249 uint16_t error_code;
35250 /* The HWRM command request type. */
35252 /* The sequence ID from the original command. */
35254 /* The length of the response data in number of bytes. */
35256 /* The destination function id, to whom the traffic is redirected. */
35258 uint8_t unused_0[5];
35260 * This field is used in Output records to indicate that the output
35261 * is completely written to RAM. This field should be read as '1'
35262 * to indicate that the output has been completely written.
35263 * When writing a command completion or response to an internal
35264 * processor, the order of writes has to be such that this field is
35270 /* hwrm_vxlan_ipv4_hdr (size:128b/16B) */
35271 struct hwrm_vxlan_ipv4_hdr {
35272 /* IPv4 version and header length. */
35274 /* IPv4 header length */
35275 #define HWRM_VXLAN_IPV4_HDR_VER_HLEN_HEADER_LENGTH_MASK UINT32_C(0xf)
35276 #define HWRM_VXLAN_IPV4_HDR_VER_HLEN_HEADER_LENGTH_SFT 0
35278 #define HWRM_VXLAN_IPV4_HDR_VER_HLEN_VERSION_MASK UINT32_C(0xf0)
35279 #define HWRM_VXLAN_IPV4_HDR_VER_HLEN_VERSION_SFT 4
35280 /* IPv4 type of service. */
35282 /* IPv4 identification. */
35284 /* IPv4 flags and offset. */
35285 uint16_t flags_frag_offset;
35288 /* IPv4 protocol. */
35290 /* IPv4 source address. */
35291 uint32_t src_ip_addr;
35292 /* IPv4 destination address. */
35293 uint32_t dest_ip_addr;
35296 /* hwrm_vxlan_ipv6_hdr (size:320b/40B) */
35297 struct hwrm_vxlan_ipv6_hdr {
35298 /* IPv6 version, traffic class and flow label. */
35299 uint32_t ver_tc_flow_label;
35300 /* IPv6 version shift */
35301 #define HWRM_VXLAN_IPV6_HDR_VER_TC_FLOW_LABEL_VER_SFT \
35303 /* IPv6 version mask */
35304 #define HWRM_VXLAN_IPV6_HDR_VER_TC_FLOW_LABEL_VER_MASK \
35305 UINT32_C(0xf0000000)
35306 /* IPv6 TC shift */
35307 #define HWRM_VXLAN_IPV6_HDR_VER_TC_FLOW_LABEL_TC_SFT \
35310 #define HWRM_VXLAN_IPV6_HDR_VER_TC_FLOW_LABEL_TC_MASK \
35311 UINT32_C(0xff00000)
35312 /* IPv6 flow label shift */
35313 #define HWRM_VXLAN_IPV6_HDR_VER_TC_FLOW_LABEL_FLOW_LABEL_SFT \
35315 /* IPv6 flow label mask */
35316 #define HWRM_VXLAN_IPV6_HDR_VER_TC_FLOW_LABEL_FLOW_LABEL_MASK \
35318 #define HWRM_VXLAN_IPV6_HDR_VER_TC_FLOW_LABEL_LAST \
35319 HWRM_VXLAN_IPV6_HDR_VER_TC_FLOW_LABEL_FLOW_LABEL_MASK
35320 /* IPv6 payload length. */
35321 uint16_t payload_len;
35322 /* IPv6 next header. */
35326 /* IPv6 source address. */
35327 uint32_t src_ip_addr[4];
35328 /* IPv6 destination address. */
35329 uint32_t dest_ip_addr[4];
35332 /* hwrm_cfa_encap_data_vxlan (size:640b/80B) */
35333 struct hwrm_cfa_encap_data_vxlan {
35334 /* Source MAC address. */
35335 uint8_t src_mac_addr[6];
35338 /* Destination MAC address. */
35339 uint8_t dst_mac_addr[6];
35340 /* Number of VLAN tags. */
35341 uint8_t num_vlan_tags;
35344 /* Outer VLAN TPID. */
35345 uint16_t ovlan_tpid;
35346 /* Outer VLAN TCI. */
35347 uint16_t ovlan_tci;
35348 /* Inner VLAN TPID. */
35349 uint16_t ivlan_tpid;
35350 /* Inner VLAN TCI. */
35351 uint16_t ivlan_tci;
35352 /* L3 header fields. */
35354 /* IP version mask. */
35355 #define HWRM_CFA_ENCAP_DATA_VXLAN_L3_VER_MASK UINT32_C(0xf)
35356 /* IP version 4. */
35357 #define HWRM_CFA_ENCAP_DATA_VXLAN_L3_VER_IPV4 UINT32_C(0x4)
35358 /* IP version 6. */
35359 #define HWRM_CFA_ENCAP_DATA_VXLAN_L3_VER_IPV6 UINT32_C(0x6)
35360 #define HWRM_CFA_ENCAP_DATA_VXLAN_L3_LAST \
35361 HWRM_CFA_ENCAP_DATA_VXLAN_L3_VER_IPV6
35362 /* UDP source port. */
35364 /* UDP destination port. */
35366 /* VXLAN Network Identifier. */
35369 * 3 bytes VXLAN header reserve fields from 1st dword of the VXLAN
35372 uint8_t hdr_rsvd0[3];
35373 /* 1 byte VXLAN header reserve field from 2nd dword of the VXLAN header. */
35375 /* VXLAN header flags field. */
35380 /*******************************
35381 * hwrm_cfa_encap_record_alloc *
35382 *******************************/
35385 /* hwrm_cfa_encap_record_alloc_input (size:832b/104B) */
35386 struct hwrm_cfa_encap_record_alloc_input {
35387 /* The HWRM command request type. */
35390 * The completion ring to send the completion event on. This should
35391 * be the NQ ID returned from the `nq_alloc` HWRM command.
35393 uint16_t cmpl_ring;
35395 * The sequence ID is used by the driver for tracking multiple
35396 * commands. This ID is treated as opaque data by the firmware and
35397 * the value is returned in the `hwrm_resp_hdr` upon completion.
35401 * The target ID of the command:
35402 * * 0x0-0xFFF8 - The function ID
35403 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
35404 * * 0xFFFD - Reserved for user-space HWRM interface
35407 uint16_t target_id;
35409 * A physical address pointer pointing to a host buffer that the
35410 * command's response data will be written. This can be either a host
35411 * physical address (HPA) or a guest physical address (GPA) and must
35412 * point to a physically contiguous block of memory.
35414 uint64_t resp_addr;
35417 * Setting of this flag indicates the applicability to the loopback
35420 #define HWRM_CFA_ENCAP_RECORD_ALLOC_INPUT_FLAGS_LOOPBACK \
35423 * Setting of this flag indicates this encap record is external
35424 * encap record. Resetting of this flag indicates this flag is
35425 * internal encap record and this is the default setting.
35427 #define HWRM_CFA_ENCAP_RECORD_ALLOC_INPUT_FLAGS_EXTERNAL \
35429 /* Encapsulation Type. */
35430 uint8_t encap_type;
35431 /* Virtual eXtensible Local Area Network (VXLAN) */
35432 #define HWRM_CFA_ENCAP_RECORD_ALLOC_INPUT_ENCAP_TYPE_VXLAN \
35434 /* Network Virtualization Generic Routing Encapsulation (NVGRE) */
35435 #define HWRM_CFA_ENCAP_RECORD_ALLOC_INPUT_ENCAP_TYPE_NVGRE \
35437 /* Generic Routing Encapsulation (GRE) after inside Ethernet payload */
35438 #define HWRM_CFA_ENCAP_RECORD_ALLOC_INPUT_ENCAP_TYPE_L2GRE \
35441 #define HWRM_CFA_ENCAP_RECORD_ALLOC_INPUT_ENCAP_TYPE_IPIP \
35443 /* Generic Network Virtualization Encapsulation (Geneve) */
35444 #define HWRM_CFA_ENCAP_RECORD_ALLOC_INPUT_ENCAP_TYPE_GENEVE \
35446 /* Multi-Protocol Label Switching (MPLS) */
35447 #define HWRM_CFA_ENCAP_RECORD_ALLOC_INPUT_ENCAP_TYPE_MPLS \
35450 #define HWRM_CFA_ENCAP_RECORD_ALLOC_INPUT_ENCAP_TYPE_VLAN \
35452 /* Generic Routing Encapsulation (GRE) inside IP datagram payload */
35453 #define HWRM_CFA_ENCAP_RECORD_ALLOC_INPUT_ENCAP_TYPE_IPGRE \
35455 /* IPV4 over virtual eXtensible Local Area Network (IPV4oVXLAN) */
35456 #define HWRM_CFA_ENCAP_RECORD_ALLOC_INPUT_ENCAP_TYPE_VXLAN_V4 \
35459 * Enhance Generic Routing Encapsulation (GRE version 1) inside IP
35462 #define HWRM_CFA_ENCAP_RECORD_ALLOC_INPUT_ENCAP_TYPE_IPGRE_V1 \
35464 /* Use fixed layer 2 ether type of 0xFFFF */
35465 #define HWRM_CFA_ENCAP_RECORD_ALLOC_INPUT_ENCAP_TYPE_L2_ETYPE \
35468 * IPV6 over virtual eXtensible Local Area Network with GPE header
35471 #define HWRM_CFA_ENCAP_RECORD_ALLOC_INPUT_ENCAP_TYPE_VXLAN_GPE_V6 \
35473 #define HWRM_CFA_ENCAP_RECORD_ALLOC_INPUT_ENCAP_TYPE_LAST \
35474 HWRM_CFA_ENCAP_RECORD_ALLOC_INPUT_ENCAP_TYPE_VXLAN_GPE_V6
35475 uint8_t unused_0[3];
35476 /* This value is encap data used for the given encap type. */
35477 uint32_t encap_data[20];
35480 /* hwrm_cfa_encap_record_alloc_output (size:128b/16B) */
35481 struct hwrm_cfa_encap_record_alloc_output {
35482 /* The specific error status for the command. */
35483 uint16_t error_code;
35484 /* The HWRM command request type. */
35486 /* The sequence ID from the original command. */
35488 /* The length of the response data in number of bytes. */
35490 /* This value is an opaque id into CFA data structures. */
35491 uint32_t encap_record_id;
35492 uint8_t unused_0[3];
35494 * This field is used in Output records to indicate that the output
35495 * is completely written to RAM. This field should be read as '1'
35496 * to indicate that the output has been completely written.
35497 * When writing a command completion or response to an internal
35498 * processor, the order of writes has to be such that this field is
35504 /******************************
35505 * hwrm_cfa_encap_record_free *
35506 ******************************/
35509 /* hwrm_cfa_encap_record_free_input (size:192b/24B) */
35510 struct hwrm_cfa_encap_record_free_input {
35511 /* The HWRM command request type. */
35514 * The completion ring to send the completion event on. This should
35515 * be the NQ ID returned from the `nq_alloc` HWRM command.
35517 uint16_t cmpl_ring;
35519 * The sequence ID is used by the driver for tracking multiple
35520 * commands. This ID is treated as opaque data by the firmware and
35521 * the value is returned in the `hwrm_resp_hdr` upon completion.
35525 * The target ID of the command:
35526 * * 0x0-0xFFF8 - The function ID
35527 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
35528 * * 0xFFFD - Reserved for user-space HWRM interface
35531 uint16_t target_id;
35533 * A physical address pointer pointing to a host buffer that the
35534 * command's response data will be written. This can be either a host
35535 * physical address (HPA) or a guest physical address (GPA) and must
35536 * point to a physically contiguous block of memory.
35538 uint64_t resp_addr;
35539 /* This value is an opaque id into CFA data structures. */
35540 uint32_t encap_record_id;
35541 uint8_t unused_0[4];
35544 /* hwrm_cfa_encap_record_free_output (size:128b/16B) */
35545 struct hwrm_cfa_encap_record_free_output {
35546 /* The specific error status for the command. */
35547 uint16_t error_code;
35548 /* The HWRM command request type. */
35550 /* The sequence ID from the original command. */
35552 /* The length of the response data in number of bytes. */
35554 uint8_t unused_0[7];
35556 * This field is used in Output records to indicate that the output
35557 * is completely written to RAM. This field should be read as '1'
35558 * to indicate that the output has been completely written.
35559 * When writing a command completion or response to an internal
35560 * processor, the order of writes has to be such that this field is
35566 /********************************
35567 * hwrm_cfa_ntuple_filter_alloc *
35568 ********************************/
35571 /* hwrm_cfa_ntuple_filter_alloc_input (size:1024b/128B) */
35572 struct hwrm_cfa_ntuple_filter_alloc_input {
35573 /* The HWRM command request type. */
35576 * The completion ring to send the completion event on. This should
35577 * be the NQ ID returned from the `nq_alloc` HWRM command.
35579 uint16_t cmpl_ring;
35581 * The sequence ID is used by the driver for tracking multiple
35582 * commands. This ID is treated as opaque data by the firmware and
35583 * the value is returned in the `hwrm_resp_hdr` upon completion.
35587 * The target ID of the command:
35588 * * 0x0-0xFFF8 - The function ID
35589 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
35590 * * 0xFFFD - Reserved for user-space HWRM interface
35593 uint16_t target_id;
35595 * A physical address pointer pointing to a host buffer that the
35596 * command's response data will be written. This can be either a host
35597 * physical address (HPA) or a guest physical address (GPA) and must
35598 * point to a physically contiguous block of memory.
35600 uint64_t resp_addr;
35603 * Setting of this flag indicates the applicability to the loopback
35606 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_FLAGS_LOOPBACK \
35609 * Setting of this flag indicates drop action. If this flag is not
35610 * set, then it should be considered accept action.
35612 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_FLAGS_DROP \
35615 * Setting of this flag indicates that a meter is expected to be
35616 * attached to this flow. This hint can be used when choosing the
35617 * action record format required for the flow.
35619 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_FLAGS_METER \
35622 * Setting of this flag indicates that the dst_id field contains
35623 * function ID. If this is not set it indicates dest_id is VNIC
35626 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_FLAGS_DEST_FID \
35629 * Setting of this flag indicates match on arp reply when ethertype
35630 * is 0x0806. If this is not set it indicates no specific arp opcode
35633 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_FLAGS_ARP_REPLY \
35636 * Setting of this flag indicates that the dst_id field contains RFS
35637 * ring table index. If this is not set it indicates dst_id is VNIC
35638 * or VPORT or function ID. Note dest_fid and dest_rfs_ring_idx
35639 * can’t be set at the same time.
35641 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_FLAGS_DEST_RFS_RING_IDX \
35645 * This bit must be '1' for the l2_filter_id field to be
35648 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_L2_FILTER_ID \
35651 * This bit must be '1' for the ethertype field to be
35654 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_ETHERTYPE \
35657 * This bit must be '1' for the tunnel_type field to be
35660 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_TUNNEL_TYPE \
35663 * This bit must be '1' for the src_macaddr field to be
35666 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_SRC_MACADDR \
35669 * This bit must be '1' for the ipaddr_type field to be
35672 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_IPADDR_TYPE \
35675 * This bit must be '1' for the src_ipaddr field to be
35678 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_SRC_IPADDR \
35681 * This bit must be '1' for the src_ipaddr_mask field to be
35684 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_SRC_IPADDR_MASK \
35687 * This bit must be '1' for the dst_ipaddr field to be
35690 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_IPADDR \
35693 * This bit must be '1' for the dst_ipaddr_mask field to be
35696 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_IPADDR_MASK \
35699 * This bit must be '1' for the ip_protocol field to be
35702 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_IP_PROTOCOL \
35705 * This bit must be '1' for the src_port field to be
35708 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_SRC_PORT \
35711 * This bit must be '1' for the src_port_mask field to be
35714 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_SRC_PORT_MASK \
35717 * This bit must be '1' for the dst_port field to be
35720 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_PORT \
35723 * This bit must be '1' for the dst_port_mask field to be
35726 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_PORT_MASK \
35729 * This bit must be '1' for the pri_hint field to be
35732 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_PRI_HINT \
35735 * This bit must be '1' for the ntuple_filter_id field to be
35738 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_NTUPLE_FILTER_ID \
35741 * This bit must be '1' for the dst_id field to be
35744 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_ID \
35747 * This bit must be '1' for the mirror_vnic_id field to be
35750 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_MIRROR_VNIC_ID \
35753 * This bit must be '1' for the dst_macaddr field to be
35756 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_MACADDR \
35758 /* This flag is deprecated. */
35759 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_RFS_RING_TBL_IDX \
35762 * This value identifies a set of CFA data structures used for an L2
35765 uint64_t l2_filter_id;
35767 * This value indicates the source MAC address in
35768 * the Ethernet header.
35770 uint8_t src_macaddr[6];
35771 /* This value indicates the ethertype in the Ethernet header. */
35772 uint16_t ethertype;
35774 * This value indicates the type of IP address.
35777 * All others are invalid.
35779 uint8_t ip_addr_type;
35781 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_IP_ADDR_TYPE_UNKNOWN \
35784 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_IP_ADDR_TYPE_IPV4 \
35787 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_IP_ADDR_TYPE_IPV6 \
35789 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_IP_ADDR_TYPE_LAST \
35790 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_IP_ADDR_TYPE_IPV6
35792 * The value of protocol filed in IP header.
35793 * Applies to UDP and TCP traffic.
35797 uint8_t ip_protocol;
35799 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_IP_PROTOCOL_UNKNOWN \
35802 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_IP_PROTOCOL_TCP \
35805 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_IP_PROTOCOL_UDP \
35807 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_IP_PROTOCOL_LAST \
35808 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_IP_PROTOCOL_UDP
35810 * If set, this value shall represent the
35811 * Logical VNIC ID of the destination VNIC for the RX
35812 * path and network port id of the destination port for
35817 * Logical VNIC ID of the VNIC where traffic is
35820 uint16_t mirror_vnic_id;
35822 * This value indicates the tunnel type for this filter.
35823 * If this field is not specified, then the filter shall
35824 * apply to both non-tunneled and tunneled packets.
35825 * If this field conflicts with the tunnel_type specified
35826 * in the l2_filter_id, then the HWRM shall return an
35827 * error for this command.
35829 uint8_t tunnel_type;
35831 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_TUNNEL_TYPE_NONTUNNEL \
35833 /* Virtual eXtensible Local Area Network (VXLAN) */
35834 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_TUNNEL_TYPE_VXLAN \
35836 /* Network Virtualization Generic Routing Encapsulation (NVGRE) */
35837 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_TUNNEL_TYPE_NVGRE \
35839 /* Generic Routing Encapsulation (GRE) inside Ethernet payload */
35840 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_TUNNEL_TYPE_L2GRE \
35843 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_TUNNEL_TYPE_IPIP \
35845 /* Generic Network Virtualization Encapsulation (Geneve) */
35846 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_TUNNEL_TYPE_GENEVE \
35848 /* Multi-Protocol Label Switching (MPLS) */
35849 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_TUNNEL_TYPE_MPLS \
35851 /* Stateless Transport Tunnel (STT) */
35852 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_TUNNEL_TYPE_STT \
35854 /* Generic Routing Encapsulation (GRE) inside IP datagram payload */
35855 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_TUNNEL_TYPE_IPGRE \
35857 /* IPV4 over virtual eXtensible Local Area Network (IPV4oVXLAN) */
35858 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_TUNNEL_TYPE_VXLAN_V4 \
35861 * Enhance Generic Routing Encapsulation (GRE version 1) inside IP
35864 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_TUNNEL_TYPE_IPGRE_V1 \
35866 /* Use fixed layer 2 ether type of 0xFFFF */
35867 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_TUNNEL_TYPE_L2_ETYPE \
35870 * IPV6 over virtual eXtensible Local Area Network with GPE header
35873 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_TUNNEL_TYPE_VXLAN_GPE_V6 \
35875 /* Any tunneled traffic */
35876 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_TUNNEL_TYPE_ANYTUNNEL \
35878 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_TUNNEL_TYPE_LAST \
35879 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_TUNNEL_TYPE_ANYTUNNEL
35881 * This hint is provided to help in placing
35882 * the filter in the filter table.
35885 /* No preference */
35886 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_PRI_HINT_NO_PREFER \
35888 /* Above the given filter */
35889 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_PRI_HINT_ABOVE \
35891 /* Below the given filter */
35892 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_PRI_HINT_BELOW \
35894 /* As high as possible */
35895 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_PRI_HINT_HIGHEST \
35897 /* As low as possible */
35898 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_PRI_HINT_LOWEST \
35900 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_PRI_HINT_LAST \
35901 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_PRI_HINT_LOWEST
35903 * The value of source IP address to be used in filtering.
35904 * For IPv4, first four bytes represent the IP address.
35906 uint32_t src_ipaddr[4];
35908 * The value of source IP address mask to be used in
35910 * For IPv4, first four bytes represent the IP address mask.
35912 uint32_t src_ipaddr_mask[4];
35914 * The value of destination IP address to be used in filtering.
35915 * For IPv4, first four bytes represent the IP address.
35917 uint32_t dst_ipaddr[4];
35919 * The value of destination IP address mask to be used in
35921 * For IPv4, first four bytes represent the IP address mask.
35923 uint32_t dst_ipaddr_mask[4];
35925 * The value of source port to be used in filtering.
35926 * Applies to UDP and TCP traffic.
35930 * The value of source port mask to be used in filtering.
35931 * Applies to UDP and TCP traffic.
35933 uint16_t src_port_mask;
35935 * The value of destination port to be used in filtering.
35936 * Applies to UDP and TCP traffic.
35940 * The value of destination port mask to be used in
35942 * Applies to UDP and TCP traffic.
35944 uint16_t dst_port_mask;
35946 * This is the ID of the filter that goes along with
35949 uint64_t ntuple_filter_id_hint;
35952 /* hwrm_cfa_ntuple_filter_alloc_output (size:192b/24B) */
35953 struct hwrm_cfa_ntuple_filter_alloc_output {
35954 /* The specific error status for the command. */
35955 uint16_t error_code;
35956 /* The HWRM command request type. */
35958 /* The sequence ID from the original command. */
35960 /* The length of the response data in number of bytes. */
35962 /* This value is an opaque id into CFA data structures. */
35963 uint64_t ntuple_filter_id;
35965 * The flow id value in bit 0-29 is the actual ID of the flow
35966 * associated with this filter and it shall be used to match
35967 * and associate the flow identifier returned in completion
35968 * records. A value of 0xFFFFFFFF in the 32-bit flow_id field
35969 * shall indicate no valid flow id.
35972 /* Indicate the flow id value. */
35973 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_OUTPUT_FLOW_ID_VALUE_MASK \
35974 UINT32_C(0x3fffffff)
35975 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_OUTPUT_FLOW_ID_VALUE_SFT 0
35976 /* Indicate type of the flow. */
35977 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_OUTPUT_FLOW_ID_TYPE \
35978 UINT32_C(0x40000000)
35980 * If this bit set to 0, then it indicates that the flow is
35983 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_OUTPUT_FLOW_ID_TYPE_INT \
35984 (UINT32_C(0x0) << 30)
35986 * If this bit is set to 1, then it indicates that the flow is
35989 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_OUTPUT_FLOW_ID_TYPE_EXT \
35990 (UINT32_C(0x1) << 30)
35991 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_OUTPUT_FLOW_ID_TYPE_LAST \
35992 HWRM_CFA_NTUPLE_FILTER_ALLOC_OUTPUT_FLOW_ID_TYPE_EXT
35993 /* Indicate the flow direction. */
35994 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_OUTPUT_FLOW_ID_DIR \
35995 UINT32_C(0x80000000)
35996 /* If this bit set to 0, then it indicates rx flow. */
35997 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_OUTPUT_FLOW_ID_DIR_RX \
35998 (UINT32_C(0x0) << 31)
35999 /* If this bit is set to 1, then it indicates that tx flow. */
36000 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_OUTPUT_FLOW_ID_DIR_TX \
36001 (UINT32_C(0x1) << 31)
36002 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_OUTPUT_FLOW_ID_DIR_LAST \
36003 HWRM_CFA_NTUPLE_FILTER_ALLOC_OUTPUT_FLOW_ID_DIR_TX
36004 uint8_t unused_0[3];
36006 * This field is used in Output records to indicate that the output
36007 * is completely written to RAM. This field should be read as '1'
36008 * to indicate that the output has been completely written.
36009 * When writing a command completion or response to an internal
36010 * processor, the order of writes has to be such that this field is
36016 /* hwrm_cfa_ntuple_filter_alloc_cmd_err (size:64b/8B) */
36017 struct hwrm_cfa_ntuple_filter_alloc_cmd_err {
36019 * command specific error codes that goes to
36020 * the cmd_err field in Common HWRM Error Response.
36023 /* Unknown error */
36024 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_CMD_ERR_CODE_UNKNOWN \
36026 /* Unable to complete operation due to conflict with Rx Mask VLAN */
36027 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_CMD_ERR_CODE_RX_MASK_VLAN_CONFLICT_ERR \
36029 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_CMD_ERR_CODE_LAST \
36030 HWRM_CFA_NTUPLE_FILTER_ALLOC_CMD_ERR_CODE_RX_MASK_VLAN_CONFLICT_ERR
36031 uint8_t unused_0[7];
36034 /*******************************
36035 * hwrm_cfa_ntuple_filter_free *
36036 *******************************/
36039 /* hwrm_cfa_ntuple_filter_free_input (size:192b/24B) */
36040 struct hwrm_cfa_ntuple_filter_free_input {
36041 /* The HWRM command request type. */
36044 * The completion ring to send the completion event on. This should
36045 * be the NQ ID returned from the `nq_alloc` HWRM command.
36047 uint16_t cmpl_ring;
36049 * The sequence ID is used by the driver for tracking multiple
36050 * commands. This ID is treated as opaque data by the firmware and
36051 * the value is returned in the `hwrm_resp_hdr` upon completion.
36055 * The target ID of the command:
36056 * * 0x0-0xFFF8 - The function ID
36057 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
36058 * * 0xFFFD - Reserved for user-space HWRM interface
36061 uint16_t target_id;
36063 * A physical address pointer pointing to a host buffer that the
36064 * command's response data will be written. This can be either a host
36065 * physical address (HPA) or a guest physical address (GPA) and must
36066 * point to a physically contiguous block of memory.
36068 uint64_t resp_addr;
36069 /* This value is an opaque id into CFA data structures. */
36070 uint64_t ntuple_filter_id;
36073 /* hwrm_cfa_ntuple_filter_free_output (size:128b/16B) */
36074 struct hwrm_cfa_ntuple_filter_free_output {
36075 /* The specific error status for the command. */
36076 uint16_t error_code;
36077 /* The HWRM command request type. */
36079 /* The sequence ID from the original command. */
36081 /* The length of the response data in number of bytes. */
36083 uint8_t unused_0[7];
36085 * This field is used in Output records to indicate that the output
36086 * is completely written to RAM. This field should be read as '1'
36087 * to indicate that the output has been completely written.
36088 * When writing a command completion or response to an internal
36089 * processor, the order of writes has to be such that this field is
36095 /******************************
36096 * hwrm_cfa_ntuple_filter_cfg *
36097 ******************************/
36100 /* hwrm_cfa_ntuple_filter_cfg_input (size:384b/48B) */
36101 struct hwrm_cfa_ntuple_filter_cfg_input {
36102 /* The HWRM command request type. */
36105 * The completion ring to send the completion event on. This should
36106 * be the NQ ID returned from the `nq_alloc` HWRM command.
36108 uint16_t cmpl_ring;
36110 * The sequence ID is used by the driver for tracking multiple
36111 * commands. This ID is treated as opaque data by the firmware and
36112 * the value is returned in the `hwrm_resp_hdr` upon completion.
36116 * The target ID of the command:
36117 * * 0x0-0xFFF8 - The function ID
36118 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
36119 * * 0xFFFD - Reserved for user-space HWRM interface
36122 uint16_t target_id;
36124 * A physical address pointer pointing to a host buffer that the
36125 * command's response data will be written. This can be either a host
36126 * physical address (HPA) or a guest physical address (GPA) and must
36127 * point to a physically contiguous block of memory.
36129 uint64_t resp_addr;
36132 * This bit must be '1' for the new_dst_id field to be
36135 #define HWRM_CFA_NTUPLE_FILTER_CFG_INPUT_ENABLES_NEW_DST_ID \
36138 * This bit must be '1' for the new_mirror_vnic_id field to be
36141 #define HWRM_CFA_NTUPLE_FILTER_CFG_INPUT_ENABLES_NEW_MIRROR_VNIC_ID \
36144 * This bit must be '1' for the new_meter_instance_id field to be
36147 #define HWRM_CFA_NTUPLE_FILTER_CFG_INPUT_ENABLES_NEW_METER_INSTANCE_ID \
36151 * Setting this bit to 1 indicates that dest_id field contains FID.
36152 * Setting this to 0 indicates that dest_id field contains VNIC or
36155 #define HWRM_CFA_NTUPLE_FILTER_CFG_INPUT_FLAGS_DEST_FID \
36158 * Setting of this flag indicates that the new_dst_id field contains
36159 * RFS ring table index. If this is not set it indicates new_dst_id
36160 * is VNIC or VPORT or function ID. Note dest_fid and
36161 * dest_rfs_ring_idx can’t be set at the same time.
36163 #define HWRM_CFA_NTUPLE_FILTER_CFG_INPUT_FLAGS_DEST_RFS_RING_IDX \
36165 /* This value is an opaque id into CFA data structures. */
36166 uint64_t ntuple_filter_id;
36168 * If set, this value shall represent the new
36169 * Logical VNIC ID of the destination VNIC for the RX
36170 * path and new network port id of the destination port for
36173 uint32_t new_dst_id;
36175 * New Logical VNIC ID of the VNIC where traffic is
36178 uint32_t new_mirror_vnic_id;
36180 * New meter to attach to the flow. Specifying the
36181 * invalid instance ID is used to remove any existing
36182 * meter from the flow.
36184 uint16_t new_meter_instance_id;
36186 * A value of 0xfff is considered invalid and implies the
36187 * instance is not configured.
36189 #define HWRM_CFA_NTUPLE_FILTER_CFG_INPUT_NEW_METER_INSTANCE_ID_INVALID \
36191 #define HWRM_CFA_NTUPLE_FILTER_CFG_INPUT_NEW_METER_INSTANCE_ID_LAST \
36192 HWRM_CFA_NTUPLE_FILTER_CFG_INPUT_NEW_METER_INSTANCE_ID_INVALID
36193 uint8_t unused_1[6];
36196 /* hwrm_cfa_ntuple_filter_cfg_output (size:128b/16B) */
36197 struct hwrm_cfa_ntuple_filter_cfg_output {
36198 /* The specific error status for the command. */
36199 uint16_t error_code;
36200 /* The HWRM command request type. */
36202 /* The sequence ID from the original command. */
36204 /* The length of the response data in number of bytes. */
36206 uint8_t unused_0[7];
36208 * This field is used in Output records to indicate that the output
36209 * is completely written to RAM. This field should be read as '1'
36210 * to indicate that the output has been completely written.
36211 * When writing a command completion or response to an internal
36212 * processor, the order of writes has to be such that this field is
36218 /**************************
36219 * hwrm_cfa_em_flow_alloc *
36220 **************************/
36223 /* hwrm_cfa_em_flow_alloc_input (size:896b/112B) */
36224 struct hwrm_cfa_em_flow_alloc_input {
36225 /* The HWRM command request type. */
36228 * The completion ring to send the completion event on. This should
36229 * be the NQ ID returned from the `nq_alloc` HWRM command.
36231 uint16_t cmpl_ring;
36233 * The sequence ID is used by the driver for tracking multiple
36234 * commands. This ID is treated as opaque data by the firmware and
36235 * the value is returned in the `hwrm_resp_hdr` upon completion.
36239 * The target ID of the command:
36240 * * 0x0-0xFFF8 - The function ID
36241 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
36242 * * 0xFFFD - Reserved for user-space HWRM interface
36245 uint16_t target_id;
36247 * A physical address pointer pointing to a host buffer that the
36248 * command's response data will be written. This can be either a host
36249 * physical address (HPA) or a guest physical address (GPA) and must
36250 * point to a physically contiguous block of memory.
36252 uint64_t resp_addr;
36255 * Enumeration denoting the RX, TX type of the resource.
36256 * This enumeration is used for resources that are similar for both
36257 * TX and RX paths of the chip.
36259 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_FLAGS_PATH UINT32_C(0x1)
36261 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_FLAGS_PATH_TX UINT32_C(0x0)
36263 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_FLAGS_PATH_RX UINT32_C(0x1)
36264 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_FLAGS_PATH_LAST \
36265 HWRM_CFA_EM_FLOW_ALLOC_INPUT_FLAGS_PATH_RX
36267 * Setting of this flag indicates enabling of a byte counter for a
36270 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_FLAGS_BYTE_CTR UINT32_C(0x2)
36272 * Setting of this flag indicates enabling of a packet counter for a
36275 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_FLAGS_PKT_CTR UINT32_C(0x4)
36277 * Setting of this flag indicates de-capsulation action for the
36280 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_FLAGS_DECAP UINT32_C(0x8)
36282 * Setting of this flag indicates encapsulation action for the
36285 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_FLAGS_ENCAP UINT32_C(0x10)
36287 * Setting of this flag indicates drop action. If this flag is not
36288 * set, then it should be considered accept action.
36290 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_FLAGS_DROP UINT32_C(0x20)
36292 * Setting of this flag indicates that a meter is expected to be
36293 * attached to this flow. This hint can be used when choosing the
36294 * action record format required for the flow.
36296 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_FLAGS_METER UINT32_C(0x40)
36299 * This bit must be '1' for the l2_filter_id field to be
36302 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_L2_FILTER_ID \
36305 * This bit must be '1' for the tunnel_type field to be
36308 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_TUNNEL_TYPE \
36311 * This bit must be '1' for the tunnel_id field to be
36314 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_TUNNEL_ID \
36317 * This bit must be '1' for the src_macaddr field to be
36320 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_SRC_MACADDR \
36323 * This bit must be '1' for the dst_macaddr field to be
36326 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_DST_MACADDR \
36329 * This bit must be '1' for the ovlan_vid field to be
36332 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_OVLAN_VID \
36335 * This bit must be '1' for the ivlan_vid field to be
36338 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_IVLAN_VID \
36341 * This bit must be '1' for the ethertype field to be
36344 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_ETHERTYPE \
36347 * This bit must be '1' for the src_ipaddr field to be
36350 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_SRC_IPADDR \
36353 * This bit must be '1' for the dst_ipaddr field to be
36356 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_DST_IPADDR \
36359 * This bit must be '1' for the ipaddr_type field to be
36362 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_IPADDR_TYPE \
36365 * This bit must be '1' for the ip_protocol field to be
36368 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_IP_PROTOCOL \
36371 * This bit must be '1' for the src_port field to be
36374 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_SRC_PORT \
36377 * This bit must be '1' for the dst_port field to be
36380 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_DST_PORT \
36383 * This bit must be '1' for the dst_id field to be
36386 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_DST_ID \
36389 * This bit must be '1' for the mirror_vnic_id field to be
36392 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_MIRROR_VNIC_ID \
36395 * This bit must be '1' for the encap_record_id field to be
36398 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_ENCAP_RECORD_ID \
36401 * This bit must be '1' for the meter_instance_id field to be
36404 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_METER_INSTANCE_ID \
36407 * This value identifies a set of CFA data structures used for an L2
36410 uint64_t l2_filter_id;
36412 uint8_t tunnel_type;
36414 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_TUNNEL_TYPE_NONTUNNEL \
36416 /* Virtual eXtensible Local Area Network (VXLAN) */
36417 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_TUNNEL_TYPE_VXLAN \
36419 /* Network Virtualization Generic Routing Encapsulation (NVGRE) */
36420 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_TUNNEL_TYPE_NVGRE \
36422 /* Generic Routing Encapsulation (GRE) inside Ethernet payload */
36423 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_TUNNEL_TYPE_L2GRE \
36426 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_TUNNEL_TYPE_IPIP \
36428 /* Generic Network Virtualization Encapsulation (Geneve) */
36429 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_TUNNEL_TYPE_GENEVE \
36431 /* Multi-Protocol Label Switching (MPLS) */
36432 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_TUNNEL_TYPE_MPLS \
36434 /* Stateless Transport Tunnel (STT) */
36435 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_TUNNEL_TYPE_STT \
36437 /* Generic Routing Encapsulation (GRE) inside IP datagram payload */
36438 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_TUNNEL_TYPE_IPGRE \
36440 /* IPV4 over virtual eXtensible Local Area Network (IPV4oVXLAN) */
36441 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_TUNNEL_TYPE_VXLAN_V4 \
36444 * Enhance Generic Routing Encapsulation (GRE version 1) inside IP
36447 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_TUNNEL_TYPE_IPGRE_V1 \
36449 /* Use fixed layer 2 ether type of 0xFFFF */
36450 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_TUNNEL_TYPE_L2_ETYPE \
36453 * IPV6 over virtual eXtensible Local Area Network with GPE header
36456 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_TUNNEL_TYPE_VXLAN_GPE_V6 \
36458 /* Any tunneled traffic */
36459 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_TUNNEL_TYPE_ANYTUNNEL \
36461 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_TUNNEL_TYPE_LAST \
36462 HWRM_CFA_EM_FLOW_ALLOC_INPUT_TUNNEL_TYPE_ANYTUNNEL
36463 uint8_t unused_0[3];
36465 * Tunnel identifier.
36466 * Virtual Network Identifier (VNI). Only valid with
36467 * tunnel_types VXLAN, NVGRE, and Geneve.
36468 * Only lower 24-bits of VNI field are used
36469 * in setting up the filter.
36471 uint32_t tunnel_id;
36473 * This value indicates the source MAC address in
36474 * the Ethernet header.
36476 uint8_t src_macaddr[6];
36477 /* The meter instance to attach to the flow. */
36478 uint16_t meter_instance_id;
36480 * A value of 0xfff is considered invalid and implies the
36481 * instance is not configured.
36483 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_METER_INSTANCE_ID_INVALID \
36485 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_METER_INSTANCE_ID_LAST \
36486 HWRM_CFA_EM_FLOW_ALLOC_INPUT_METER_INSTANCE_ID_INVALID
36488 * This value indicates the destination MAC address in
36489 * the Ethernet header.
36491 uint8_t dst_macaddr[6];
36493 * This value indicates the VLAN ID of the outer VLAN tag
36494 * in the Ethernet header.
36496 uint16_t ovlan_vid;
36498 * This value indicates the VLAN ID of the inner VLAN tag
36499 * in the Ethernet header.
36501 uint16_t ivlan_vid;
36502 /* This value indicates the ethertype in the Ethernet header. */
36503 uint16_t ethertype;
36505 * This value indicates the type of IP address.
36508 * All others are invalid.
36510 uint8_t ip_addr_type;
36512 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_IP_ADDR_TYPE_UNKNOWN UINT32_C(0x0)
36514 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_IP_ADDR_TYPE_IPV4 UINT32_C(0x4)
36516 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_IP_ADDR_TYPE_IPV6 UINT32_C(0x6)
36517 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_IP_ADDR_TYPE_LAST \
36518 HWRM_CFA_EM_FLOW_ALLOC_INPUT_IP_ADDR_TYPE_IPV6
36520 * The value of protocol filed in IP header.
36521 * Applies to UDP and TCP traffic.
36525 uint8_t ip_protocol;
36527 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_IP_PROTOCOL_UNKNOWN UINT32_C(0x0)
36529 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_IP_PROTOCOL_TCP UINT32_C(0x6)
36531 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_IP_PROTOCOL_UDP UINT32_C(0x11)
36532 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_IP_PROTOCOL_LAST \
36533 HWRM_CFA_EM_FLOW_ALLOC_INPUT_IP_PROTOCOL_UDP
36534 uint8_t unused_1[2];
36536 * The value of source IP address to be used in filtering.
36537 * For IPv4, first four bytes represent the IP address.
36539 uint32_t src_ipaddr[4];
36541 * big_endian = True
36542 * The value of destination IP address to be used in filtering.
36543 * For IPv4, first four bytes represent the IP address.
36545 uint32_t dst_ipaddr[4];
36547 * The value of source port to be used in filtering.
36548 * Applies to UDP and TCP traffic.
36552 * The value of destination port to be used in filtering.
36553 * Applies to UDP and TCP traffic.
36557 * If set, this value shall represent the
36558 * Logical VNIC ID of the destination VNIC for the RX
36559 * path and network port id of the destination port for
36564 * Logical VNIC ID of the VNIC where traffic is
36567 uint16_t mirror_vnic_id;
36568 /* Logical ID of the encapsulation record. */
36569 uint32_t encap_record_id;
36570 uint8_t unused_2[4];
36573 /* hwrm_cfa_em_flow_alloc_output (size:192b/24B) */
36574 struct hwrm_cfa_em_flow_alloc_output {
36575 /* The specific error status for the command. */
36576 uint16_t error_code;
36577 /* The HWRM command request type. */
36579 /* The sequence ID from the original command. */
36581 /* The length of the response data in number of bytes. */
36583 /* This value is an opaque id into CFA data structures. */
36584 uint64_t em_filter_id;
36586 * The flow id value in bit 0-29 is the actual ID of the flow
36587 * associated with this filter and it shall be used to match
36588 * and associate the flow identifier returned in completion
36589 * records. A value of 0xFFFFFFFF in the 32-bit flow_id field
36590 * shall indicate no valid flow id.
36593 /* Indicate the flow id value. */
36594 #define HWRM_CFA_EM_FLOW_ALLOC_OUTPUT_FLOW_ID_VALUE_MASK \
36595 UINT32_C(0x3fffffff)
36596 #define HWRM_CFA_EM_FLOW_ALLOC_OUTPUT_FLOW_ID_VALUE_SFT 0
36597 /* Indicate type of the flow. */
36598 #define HWRM_CFA_EM_FLOW_ALLOC_OUTPUT_FLOW_ID_TYPE \
36599 UINT32_C(0x40000000)
36601 * If this bit set to 0, then it indicates that the flow is
36604 #define HWRM_CFA_EM_FLOW_ALLOC_OUTPUT_FLOW_ID_TYPE_INT \
36605 (UINT32_C(0x0) << 30)
36607 * If this bit is set to 1, then it indicates that the flow is
36610 #define HWRM_CFA_EM_FLOW_ALLOC_OUTPUT_FLOW_ID_TYPE_EXT \
36611 (UINT32_C(0x1) << 30)
36612 #define HWRM_CFA_EM_FLOW_ALLOC_OUTPUT_FLOW_ID_TYPE_LAST \
36613 HWRM_CFA_EM_FLOW_ALLOC_OUTPUT_FLOW_ID_TYPE_EXT
36614 /* Indicate the flow direction. */
36615 #define HWRM_CFA_EM_FLOW_ALLOC_OUTPUT_FLOW_ID_DIR \
36616 UINT32_C(0x80000000)
36617 /* If this bit set to 0, then it indicates rx flow. */
36618 #define HWRM_CFA_EM_FLOW_ALLOC_OUTPUT_FLOW_ID_DIR_RX \
36619 (UINT32_C(0x0) << 31)
36620 /* If this bit is set to 1, then it indicates that tx flow. */
36621 #define HWRM_CFA_EM_FLOW_ALLOC_OUTPUT_FLOW_ID_DIR_TX \
36622 (UINT32_C(0x1) << 31)
36623 #define HWRM_CFA_EM_FLOW_ALLOC_OUTPUT_FLOW_ID_DIR_LAST \
36624 HWRM_CFA_EM_FLOW_ALLOC_OUTPUT_FLOW_ID_DIR_TX
36625 uint8_t unused_0[3];
36627 * This field is used in Output records to indicate that the output
36628 * is completely written to RAM. This field should be read as '1'
36629 * to indicate that the output has been completely written.
36630 * When writing a command completion or response to an internal
36631 * processor, the order of writes has to be such that this field is
36637 /*************************
36638 * hwrm_cfa_em_flow_free *
36639 *************************/
36642 /* hwrm_cfa_em_flow_free_input (size:192b/24B) */
36643 struct hwrm_cfa_em_flow_free_input {
36644 /* The HWRM command request type. */
36647 * The completion ring to send the completion event on. This should
36648 * be the NQ ID returned from the `nq_alloc` HWRM command.
36650 uint16_t cmpl_ring;
36652 * The sequence ID is used by the driver for tracking multiple
36653 * commands. This ID is treated as opaque data by the firmware and
36654 * the value is returned in the `hwrm_resp_hdr` upon completion.
36658 * The target ID of the command:
36659 * * 0x0-0xFFF8 - The function ID
36660 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
36661 * * 0xFFFD - Reserved for user-space HWRM interface
36664 uint16_t target_id;
36666 * A physical address pointer pointing to a host buffer that the
36667 * command's response data will be written. This can be either a host
36668 * physical address (HPA) or a guest physical address (GPA) and must
36669 * point to a physically contiguous block of memory.
36671 uint64_t resp_addr;
36672 /* This value is an opaque id into CFA data structures. */
36673 uint64_t em_filter_id;
36676 /* hwrm_cfa_em_flow_free_output (size:128b/16B) */
36677 struct hwrm_cfa_em_flow_free_output {
36678 /* The specific error status for the command. */
36679 uint16_t error_code;
36680 /* The HWRM command request type. */
36682 /* The sequence ID from the original command. */
36684 /* The length of the response data in number of bytes. */
36686 uint8_t unused_0[7];
36688 * This field is used in Output records to indicate that the output
36689 * is completely written to RAM. This field should be read as '1'
36690 * to indicate that the output has been completely written.
36691 * When writing a command completion or response to an internal
36692 * processor, the order of writes has to be such that this field is
36698 /************************
36699 * hwrm_cfa_meter_qcaps *
36700 ************************/
36703 /* hwrm_cfa_meter_qcaps_input (size:128b/16B) */
36704 struct hwrm_cfa_meter_qcaps_input {
36705 /* The HWRM command request type. */
36708 * The completion ring to send the completion event on. This should
36709 * be the NQ ID returned from the `nq_alloc` HWRM command.
36711 uint16_t cmpl_ring;
36713 * The sequence ID is used by the driver for tracking multiple
36714 * commands. This ID is treated as opaque data by the firmware and
36715 * the value is returned in the `hwrm_resp_hdr` upon completion.
36719 * The target ID of the command:
36720 * * 0x0-0xFFF8 - The function ID
36721 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
36722 * * 0xFFFD - Reserved for user-space HWRM interface
36725 uint16_t target_id;
36727 * A physical address pointer pointing to a host buffer that the
36728 * command's response data will be written. This can be either a host
36729 * physical address (HPA) or a guest physical address (GPA) and must
36730 * point to a physically contiguous block of memory.
36732 uint64_t resp_addr;
36735 /* hwrm_cfa_meter_qcaps_output (size:320b/40B) */
36736 struct hwrm_cfa_meter_qcaps_output {
36737 /* The specific error status for the command. */
36738 uint16_t error_code;
36739 /* The HWRM command request type. */
36741 /* The sequence ID from the original command. */
36743 /* The length of the response data in number of bytes. */
36747 * Enumeration denoting the clock at which the Meter is running
36748 * with. This enumeration is used for resources that are similar
36749 * for both TX and RX paths of the chip.
36751 #define HWRM_CFA_METER_QCAPS_OUTPUT_FLAGS_CLOCK_MASK UINT32_C(0xf)
36752 #define HWRM_CFA_METER_QCAPS_OUTPUT_FLAGS_CLOCK_SFT 0
36754 #define HWRM_CFA_METER_QCAPS_OUTPUT_FLAGS_CLOCK_375MHZ UINT32_C(0x0)
36756 #define HWRM_CFA_METER_QCAPS_OUTPUT_FLAGS_CLOCK_625MHZ UINT32_C(0x1)
36757 #define HWRM_CFA_METER_QCAPS_OUTPUT_FLAGS_CLOCK_LAST \
36758 HWRM_CFA_METER_QCAPS_OUTPUT_FLAGS_CLOCK_625MHZ
36759 uint8_t unused_0[4];
36761 * The minimum guaranteed number of tx meter profiles supported
36762 * for this function.
36764 uint16_t min_tx_profile;
36766 * The maximum non-guaranteed number of tx meter profiles supported
36767 * for this function.
36769 uint16_t max_tx_profile;
36771 * The minimum guaranteed number of rx meter profiles supported
36772 * for this function.
36774 uint16_t min_rx_profile;
36776 * The maximum non-guaranteed number of rx meter profiles supported
36777 * for this function.
36779 uint16_t max_rx_profile;
36781 * The minimum guaranteed number of tx meter instances supported
36782 * for this function.
36784 uint16_t min_tx_instance;
36786 * The maximum non-guaranteed number of tx meter instances supported
36787 * for this function.
36789 uint16_t max_tx_instance;
36791 * The minimum guaranteed number of rx meter instances supported
36792 * for this function.
36794 uint16_t min_rx_instance;
36796 * The maximum non-guaranteed number of rx meter instances supported
36797 * for this function.
36799 uint16_t max_rx_instance;
36800 uint8_t unused_1[7];
36802 * This field is used in Output records to indicate that the output
36803 * is completely written to RAM. This field should be read as '1'
36804 * to indicate that the output has been completely written.
36805 * When writing a command completion or response to an internal
36806 * processor, the order of writes has to be such that this field is
36812 /********************************
36813 * hwrm_cfa_meter_profile_alloc *
36814 ********************************/
36817 /* hwrm_cfa_meter_profile_alloc_input (size:320b/40B) */
36818 struct hwrm_cfa_meter_profile_alloc_input {
36819 /* The HWRM command request type. */
36822 * The completion ring to send the completion event on. This should
36823 * be the NQ ID returned from the `nq_alloc` HWRM command.
36825 uint16_t cmpl_ring;
36827 * The sequence ID is used by the driver for tracking multiple
36828 * commands. This ID is treated as opaque data by the firmware and
36829 * the value is returned in the `hwrm_resp_hdr` upon completion.
36833 * The target ID of the command:
36834 * * 0x0-0xFFF8 - The function ID
36835 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
36836 * * 0xFFFD - Reserved for user-space HWRM interface
36839 uint16_t target_id;
36841 * A physical address pointer pointing to a host buffer that the
36842 * command's response data will be written. This can be either a host
36843 * physical address (HPA) or a guest physical address (GPA) and must
36844 * point to a physically contiguous block of memory.
36846 uint64_t resp_addr;
36849 * Enumeration denoting the RX, TX type of the resource.
36850 * This enumeration is used for resources that are similar for both
36851 * TX and RX paths of the chip.
36853 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_FLAGS_PATH UINT32_C(0x1)
36855 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_FLAGS_PATH_TX \
36858 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_FLAGS_PATH_RX \
36860 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_FLAGS_PATH_LAST \
36861 HWRM_CFA_METER_PROFILE_ALLOC_INPUT_FLAGS_PATH_RX
36862 /* The meter algorithm type. */
36863 uint8_t meter_type;
36864 /* RFC 2697 (srTCM) */
36865 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_METER_TYPE_RFC2697 \
36867 /* RFC 2698 (trTCM) */
36868 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_METER_TYPE_RFC2698 \
36870 /* RFC 4115 (trTCM) */
36871 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_METER_TYPE_RFC4115 \
36873 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_METER_TYPE_LAST \
36874 HWRM_CFA_METER_PROFILE_ALLOC_INPUT_METER_TYPE_RFC4115
36876 * This field is reserved for the future use.
36877 * It shall be set to 0.
36879 uint16_t reserved1;
36881 * This field is reserved for the future use.
36882 * It shall be set to 0.
36884 uint32_t reserved2;
36885 /* A meter rate specified in bytes-per-second. */
36886 uint32_t commit_rate;
36887 /* The bandwidth value. */
36888 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_RATE_BW_VALUE_MASK \
36889 UINT32_C(0xfffffff)
36890 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_RATE_BW_VALUE_SFT \
36892 /* The granularity of the value (bits or bytes). */
36893 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_RATE_SCALE \
36894 UINT32_C(0x10000000)
36895 /* Value is in bits. */
36896 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_RATE_SCALE_BITS \
36897 (UINT32_C(0x0) << 28)
36898 /* Value is in bytes. */
36899 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_RATE_SCALE_BYTES \
36900 (UINT32_C(0x1) << 28)
36901 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_RATE_SCALE_LAST \
36902 HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_RATE_SCALE_BYTES
36903 /* bw_value_unit is 3 b */
36904 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_RATE_BW_VALUE_UNIT_MASK \
36905 UINT32_C(0xe0000000)
36906 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_RATE_BW_VALUE_UNIT_SFT \
36908 /* Value is in Mb or MB (base 10). */
36909 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_RATE_BW_VALUE_UNIT_MEGA \
36910 (UINT32_C(0x0) << 29)
36911 /* Value is in Kb or KB (base 10). */
36912 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_RATE_BW_VALUE_UNIT_KILO \
36913 (UINT32_C(0x2) << 29)
36914 /* Value is in bits or bytes. */
36915 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_RATE_BW_VALUE_UNIT_BASE \
36916 (UINT32_C(0x4) << 29)
36917 /* Value is in Gb or GB (base 10). */
36918 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_RATE_BW_VALUE_UNIT_GIGA \
36919 (UINT32_C(0x6) << 29)
36920 /* Value is in 1/100th of a percentage of total bandwidth. */
36921 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_RATE_BW_VALUE_UNIT_PERCENT1_100 \
36922 (UINT32_C(0x1) << 29)
36924 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_RATE_BW_VALUE_UNIT_RAW \
36925 (UINT32_C(0x7) << 29)
36926 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_RATE_BW_VALUE_UNIT_LAST \
36927 HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_RATE_BW_VALUE_UNIT_RAW
36928 /* A meter burst size specified in bytes. */
36929 uint32_t commit_burst;
36930 /* The bandwidth value. */
36931 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_BURST_BW_VALUE_MASK \
36932 UINT32_C(0xfffffff)
36933 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_BURST_BW_VALUE_SFT \
36935 /* The granularity of the value (bits or bytes). */
36936 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_BURST_SCALE \
36937 UINT32_C(0x10000000)
36938 /* Value is in bits. */
36939 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_BURST_SCALE_BITS \
36940 (UINT32_C(0x0) << 28)
36941 /* Value is in bytes. */
36942 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_BURST_SCALE_BYTES \
36943 (UINT32_C(0x1) << 28)
36944 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_BURST_SCALE_LAST \
36945 HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_BURST_SCALE_BYTES
36946 /* bw_value_unit is 3 b */
36947 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_BURST_BW_VALUE_UNIT_MASK \
36948 UINT32_C(0xe0000000)
36949 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_BURST_BW_VALUE_UNIT_SFT \
36951 /* Value is in Mb or MB (base 10). */
36952 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_BURST_BW_VALUE_UNIT_MEGA \
36953 (UINT32_C(0x0) << 29)
36954 /* Value is in Kb or KB (base 10). */
36955 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_BURST_BW_VALUE_UNIT_KILO \
36956 (UINT32_C(0x2) << 29)
36957 /* Value is in bits or bytes. */
36958 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_BURST_BW_VALUE_UNIT_BASE \
36959 (UINT32_C(0x4) << 29)
36960 /* Value is in Gb or GB (base 10). */
36961 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_BURST_BW_VALUE_UNIT_GIGA \
36962 (UINT32_C(0x6) << 29)
36963 /* Value is in 1/100th of a percentage of total bandwidth. */
36964 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_BURST_BW_VALUE_UNIT_PERCENT1_100 \
36965 (UINT32_C(0x1) << 29)
36966 /* Invalid value */
36967 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_BURST_BW_VALUE_UNIT_INVALID \
36968 (UINT32_C(0x7) << 29)
36969 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_BURST_BW_VALUE_UNIT_LAST \
36970 HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_BURST_BW_VALUE_UNIT_INVALID
36971 /* A meter rate specified in bytes-per-second. */
36972 uint32_t excess_peak_rate;
36973 /* The bandwidth value. */
36974 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_RATE_BW_VALUE_MASK \
36975 UINT32_C(0xfffffff)
36976 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_RATE_BW_VALUE_SFT \
36978 /* The granularity of the value (bits or bytes). */
36979 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_RATE_SCALE \
36980 UINT32_C(0x10000000)
36981 /* Value is in bits. */
36982 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_RATE_SCALE_BITS \
36983 (UINT32_C(0x0) << 28)
36984 /* Value is in bytes. */
36985 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_RATE_SCALE_BYTES \
36986 (UINT32_C(0x1) << 28)
36987 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_RATE_SCALE_LAST \
36988 HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_RATE_SCALE_BYTES
36989 /* bw_value_unit is 3 b */
36990 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_RATE_BW_VALUE_UNIT_MASK \
36991 UINT32_C(0xe0000000)
36992 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_RATE_BW_VALUE_UNIT_SFT \
36994 /* Value is in Mb or MB (base 10). */
36995 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_RATE_BW_VALUE_UNIT_MEGA \
36996 (UINT32_C(0x0) << 29)
36997 /* Value is in Kb or KB (base 10). */
36998 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_RATE_BW_VALUE_UNIT_KILO \
36999 (UINT32_C(0x2) << 29)
37000 /* Value is in bits or bytes. */
37001 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_RATE_BW_VALUE_UNIT_BASE \
37002 (UINT32_C(0x4) << 29)
37003 /* Value is in Gb or GB (base 10). */
37004 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_RATE_BW_VALUE_UNIT_GIGA \
37005 (UINT32_C(0x6) << 29)
37006 /* Value is in 1/100th of a percentage of total bandwidth. */
37007 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_RATE_BW_VALUE_UNIT_PERCENT1_100 \
37008 (UINT32_C(0x1) << 29)
37010 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_RATE_BW_VALUE_UNIT_RAW \
37011 (UINT32_C(0x7) << 29)
37012 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_RATE_BW_VALUE_UNIT_LAST \
37013 HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_RATE_BW_VALUE_UNIT_RAW
37014 /* A meter burst size specified in bytes. */
37015 uint32_t excess_peak_burst;
37016 /* The bandwidth value. */
37017 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_BURST_BW_VALUE_MASK \
37018 UINT32_C(0xfffffff)
37019 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_BURST_BW_VALUE_SFT \
37021 /* The granularity of the value (bits or bytes). */
37022 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_BURST_SCALE \
37023 UINT32_C(0x10000000)
37024 /* Value is in bits. */
37025 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_BURST_SCALE_BITS \
37026 (UINT32_C(0x0) << 28)
37027 /* Value is in bytes. */
37028 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_BURST_SCALE_BYTES \
37029 (UINT32_C(0x1) << 28)
37030 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_BURST_SCALE_LAST \
37031 HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_BURST_SCALE_BYTES
37032 /* bw_value_unit is 3 b */
37033 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_BURST_BW_VALUE_UNIT_MASK \
37034 UINT32_C(0xe0000000)
37035 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_BURST_BW_VALUE_UNIT_SFT \
37037 /* Value is in Mb or MB (base 10). */
37038 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_BURST_BW_VALUE_UNIT_MEGA \
37039 (UINT32_C(0x0) << 29)
37040 /* Value is in Kb or KB (base 10). */
37041 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_BURST_BW_VALUE_UNIT_KILO \
37042 (UINT32_C(0x2) << 29)
37043 /* Value is in bits or bytes. */
37044 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_BURST_BW_VALUE_UNIT_BASE \
37045 (UINT32_C(0x4) << 29)
37046 /* Value is in Gb or GB (base 10). */
37047 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_BURST_BW_VALUE_UNIT_GIGA \
37048 (UINT32_C(0x6) << 29)
37049 /* Value is in 1/100th of a percentage of total bandwidth. */
37050 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_BURST_BW_VALUE_UNIT_PERCENT1_100 \
37051 (UINT32_C(0x1) << 29)
37053 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_BURST_BW_VALUE_UNIT_INVALID \
37054 (UINT32_C(0x7) << 29)
37055 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_BURST_BW_VALUE_UNIT_LAST \
37056 HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_BURST_BW_VALUE_UNIT_INVALID
37059 /* hwrm_cfa_meter_profile_alloc_output (size:128b/16B) */
37060 struct hwrm_cfa_meter_profile_alloc_output {
37061 /* The specific error status for the command. */
37062 uint16_t error_code;
37063 /* The HWRM command request type. */
37065 /* The sequence ID from the original command. */
37067 /* The length of the response data in number of bytes. */
37069 /* This value identifies a meter profile in CFA. */
37070 uint16_t meter_profile_id;
37072 * A value of 0xfff is considered invalid and implies the
37073 * profile is not configured.
37075 #define HWRM_CFA_METER_PROFILE_ALLOC_OUTPUT_METER_PROFILE_ID_INVALID \
37077 #define HWRM_CFA_METER_PROFILE_ALLOC_OUTPUT_METER_PROFILE_ID_LAST \
37078 HWRM_CFA_METER_PROFILE_ALLOC_OUTPUT_METER_PROFILE_ID_INVALID
37079 uint8_t unused_0[5];
37081 * This field is used in Output records to indicate that the output
37082 * is completely written to RAM. This field should be read as '1'
37083 * to indicate that the output has been completely written.
37084 * When writing a command completion or response to an internal
37085 * processor, the order of writes has to be such that this field is
37091 /*******************************
37092 * hwrm_cfa_meter_profile_free *
37093 *******************************/
37096 /* hwrm_cfa_meter_profile_free_input (size:192b/24B) */
37097 struct hwrm_cfa_meter_profile_free_input {
37098 /* The HWRM command request type. */
37101 * The completion ring to send the completion event on. This should
37102 * be the NQ ID returned from the `nq_alloc` HWRM command.
37104 uint16_t cmpl_ring;
37106 * The sequence ID is used by the driver for tracking multiple
37107 * commands. This ID is treated as opaque data by the firmware and
37108 * the value is returned in the `hwrm_resp_hdr` upon completion.
37112 * The target ID of the command:
37113 * * 0x0-0xFFF8 - The function ID
37114 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
37115 * * 0xFFFD - Reserved for user-space HWRM interface
37118 uint16_t target_id;
37120 * A physical address pointer pointing to a host buffer that the
37121 * command's response data will be written. This can be either a host
37122 * physical address (HPA) or a guest physical address (GPA) and must
37123 * point to a physically contiguous block of memory.
37125 uint64_t resp_addr;
37128 * Enumeration denoting the RX, TX type of the resource.
37129 * This enumeration is used for resources that are similar for both
37130 * TX and RX paths of the chip.
37132 #define HWRM_CFA_METER_PROFILE_FREE_INPUT_FLAGS_PATH UINT32_C(0x1)
37134 #define HWRM_CFA_METER_PROFILE_FREE_INPUT_FLAGS_PATH_TX \
37137 #define HWRM_CFA_METER_PROFILE_FREE_INPUT_FLAGS_PATH_RX \
37139 #define HWRM_CFA_METER_PROFILE_FREE_INPUT_FLAGS_PATH_LAST \
37140 HWRM_CFA_METER_PROFILE_FREE_INPUT_FLAGS_PATH_RX
37142 /* This value identifies a meter profile in CFA. */
37143 uint16_t meter_profile_id;
37145 * A value of 0xfff is considered invalid and implies the
37146 * profile is not configured.
37148 #define HWRM_CFA_METER_PROFILE_FREE_INPUT_METER_PROFILE_ID_INVALID \
37150 #define HWRM_CFA_METER_PROFILE_FREE_INPUT_METER_PROFILE_ID_LAST \
37151 HWRM_CFA_METER_PROFILE_FREE_INPUT_METER_PROFILE_ID_INVALID
37152 uint8_t unused_1[4];
37155 /* hwrm_cfa_meter_profile_free_output (size:128b/16B) */
37156 struct hwrm_cfa_meter_profile_free_output {
37157 /* The specific error status for the command. */
37158 uint16_t error_code;
37159 /* The HWRM command request type. */
37161 /* The sequence ID from the original command. */
37163 /* The length of the response data in number of bytes. */
37165 uint8_t unused_0[7];
37167 * This field is used in Output records to indicate that the output
37168 * is completely written to RAM. This field should be read as '1'
37169 * to indicate that the output has been completely written.
37170 * When writing a command completion or response to an internal
37171 * processor, the order of writes has to be such that this field is
37177 /******************************
37178 * hwrm_cfa_meter_profile_cfg *
37179 ******************************/
37182 /* hwrm_cfa_meter_profile_cfg_input (size:320b/40B) */
37183 struct hwrm_cfa_meter_profile_cfg_input {
37184 /* The HWRM command request type. */
37187 * The completion ring to send the completion event on. This should
37188 * be the NQ ID returned from the `nq_alloc` HWRM command.
37190 uint16_t cmpl_ring;
37192 * The sequence ID is used by the driver for tracking multiple
37193 * commands. This ID is treated as opaque data by the firmware and
37194 * the value is returned in the `hwrm_resp_hdr` upon completion.
37198 * The target ID of the command:
37199 * * 0x0-0xFFF8 - The function ID
37200 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
37201 * * 0xFFFD - Reserved for user-space HWRM interface
37204 uint16_t target_id;
37206 * A physical address pointer pointing to a host buffer that the
37207 * command's response data will be written. This can be either a host
37208 * physical address (HPA) or a guest physical address (GPA) and must
37209 * point to a physically contiguous block of memory.
37211 uint64_t resp_addr;
37214 * Enumeration denoting the RX, TX type of the resource.
37215 * This enumeration is used for resources that are similar for both
37216 * TX and RX paths of the chip.
37218 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_FLAGS_PATH UINT32_C(0x1)
37220 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_FLAGS_PATH_TX UINT32_C(0x0)
37222 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_FLAGS_PATH_RX UINT32_C(0x1)
37223 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_FLAGS_PATH_LAST \
37224 HWRM_CFA_METER_PROFILE_CFG_INPUT_FLAGS_PATH_RX
37225 /* The meter algorithm type. */
37226 uint8_t meter_type;
37227 /* RFC 2697 (srTCM) */
37228 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_METER_TYPE_RFC2697 \
37230 /* RFC 2698 (trTCM) */
37231 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_METER_TYPE_RFC2698 \
37233 /* RFC 4115 (trTCM) */
37234 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_METER_TYPE_RFC4115 \
37236 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_METER_TYPE_LAST \
37237 HWRM_CFA_METER_PROFILE_CFG_INPUT_METER_TYPE_RFC4115
37238 /* This value identifies a meter profile in CFA. */
37239 uint16_t meter_profile_id;
37241 * A value of 0xfff is considered invalid and implies the
37242 * profile is not configured.
37244 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_METER_PROFILE_ID_INVALID \
37246 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_METER_PROFILE_ID_LAST \
37247 HWRM_CFA_METER_PROFILE_CFG_INPUT_METER_PROFILE_ID_INVALID
37249 * This field is reserved for the future use.
37250 * It shall be set to 0.
37253 /* A meter rate specified in bytes-per-second. */
37254 uint32_t commit_rate;
37255 /* The bandwidth value. */
37256 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_RATE_BW_VALUE_MASK \
37257 UINT32_C(0xfffffff)
37258 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_RATE_BW_VALUE_SFT \
37260 /* The granularity of the value (bits or bytes). */
37261 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_RATE_SCALE \
37262 UINT32_C(0x10000000)
37263 /* Value is in bits. */
37264 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_RATE_SCALE_BITS \
37265 (UINT32_C(0x0) << 28)
37266 /* Value is in bytes. */
37267 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_RATE_SCALE_BYTES \
37268 (UINT32_C(0x1) << 28)
37269 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_RATE_SCALE_LAST \
37270 HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_RATE_SCALE_BYTES
37271 /* bw_value_unit is 3 b */
37272 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_RATE_BW_VALUE_UNIT_MASK \
37273 UINT32_C(0xe0000000)
37274 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_RATE_BW_VALUE_UNIT_SFT \
37276 /* Value is in Mb or MB (base 10). */
37277 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_RATE_BW_VALUE_UNIT_MEGA \
37278 (UINT32_C(0x0) << 29)
37279 /* Value is in Kb or KB (base 10). */
37280 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_RATE_BW_VALUE_UNIT_KILO \
37281 (UINT32_C(0x2) << 29)
37282 /* Value is in bits or bytes. */
37283 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_RATE_BW_VALUE_UNIT_BASE \
37284 (UINT32_C(0x4) << 29)
37285 /* Value is in Gb or GB (base 10). */
37286 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_RATE_BW_VALUE_UNIT_GIGA \
37287 (UINT32_C(0x6) << 29)
37288 /* Value is in 1/100th of a percentage of total bandwidth. */
37289 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_RATE_BW_VALUE_UNIT_PERCENT1_100 \
37290 (UINT32_C(0x1) << 29)
37292 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_RATE_BW_VALUE_UNIT_RAW \
37293 (UINT32_C(0x7) << 29)
37294 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_RATE_BW_VALUE_UNIT_LAST \
37295 HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_RATE_BW_VALUE_UNIT_RAW
37296 /* A meter burst size specified in bytes. */
37297 uint32_t commit_burst;
37298 /* The bandwidth value. */
37299 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_BURST_BW_VALUE_MASK \
37300 UINT32_C(0xfffffff)
37301 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_BURST_BW_VALUE_SFT \
37303 /* The granularity of the value (bits or bytes). */
37304 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_BURST_SCALE \
37305 UINT32_C(0x10000000)
37306 /* Value is in bits. */
37307 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_BURST_SCALE_BITS \
37308 (UINT32_C(0x0) << 28)
37309 /* Value is in bytes. */
37310 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_BURST_SCALE_BYTES \
37311 (UINT32_C(0x1) << 28)
37312 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_BURST_SCALE_LAST \
37313 HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_BURST_SCALE_BYTES
37314 /* bw_value_unit is 3 b */
37315 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_BURST_BW_VALUE_UNIT_MASK \
37316 UINT32_C(0xe0000000)
37317 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_BURST_BW_VALUE_UNIT_SFT \
37319 /* Value is in Mb or MB (base 10). */
37320 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_BURST_BW_VALUE_UNIT_MEGA \
37321 (UINT32_C(0x0) << 29)
37322 /* Value is in Kb or KB (base 10). */
37323 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_BURST_BW_VALUE_UNIT_KILO \
37324 (UINT32_C(0x2) << 29)
37325 /* Value is in bits or bytes. */
37326 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_BURST_BW_VALUE_UNIT_BASE \
37327 (UINT32_C(0x4) << 29)
37328 /* Value is in Gb or GB (base 10). */
37329 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_BURST_BW_VALUE_UNIT_GIGA \
37330 (UINT32_C(0x6) << 29)
37331 /* Value is in 1/100th of a percentage of total bandwidth. */
37332 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_BURST_BW_VALUE_UNIT_PERCENT1_100 \
37333 (UINT32_C(0x1) << 29)
37334 /* Invalid value */
37335 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_BURST_BW_VALUE_UNIT_INVALID \
37336 (UINT32_C(0x7) << 29)
37337 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_BURST_BW_VALUE_UNIT_LAST \
37338 HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_BURST_BW_VALUE_UNIT_INVALID
37339 /* A meter rate specified in bytes-per-second. */
37340 uint32_t excess_peak_rate;
37341 /* The bandwidth value. */
37342 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_RATE_BW_VALUE_MASK \
37343 UINT32_C(0xfffffff)
37344 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_RATE_BW_VALUE_SFT \
37346 /* The granularity of the value (bits or bytes). */
37347 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_RATE_SCALE \
37348 UINT32_C(0x10000000)
37349 /* Value is in bits. */
37350 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_RATE_SCALE_BITS \
37351 (UINT32_C(0x0) << 28)
37352 /* Value is in bytes. */
37353 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_RATE_SCALE_BYTES \
37354 (UINT32_C(0x1) << 28)
37355 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_RATE_SCALE_LAST \
37356 HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_RATE_SCALE_BYTES
37357 /* bw_value_unit is 3 b */
37358 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_RATE_BW_VALUE_UNIT_MASK \
37359 UINT32_C(0xe0000000)
37360 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_RATE_BW_VALUE_UNIT_SFT \
37362 /* Value is in Mb or MB (base 10). */
37363 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_RATE_BW_VALUE_UNIT_MEGA \
37364 (UINT32_C(0x0) << 29)
37365 /* Value is in Kb or KB (base 10). */
37366 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_RATE_BW_VALUE_UNIT_KILO \
37367 (UINT32_C(0x2) << 29)
37368 /* Value is in bits or bytes. */
37369 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_RATE_BW_VALUE_UNIT_BASE \
37370 (UINT32_C(0x4) << 29)
37371 /* Value is in Gb or GB (base 10). */
37372 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_RATE_BW_VALUE_UNIT_GIGA \
37373 (UINT32_C(0x6) << 29)
37374 /* Value is in 1/100th of a percentage of total bandwidth. */
37375 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_RATE_BW_VALUE_UNIT_PERCENT1_100 \
37376 (UINT32_C(0x1) << 29)
37378 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_RATE_BW_VALUE_UNIT_RAW \
37379 (UINT32_C(0x7) << 29)
37380 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_RATE_BW_VALUE_UNIT_LAST \
37381 HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_RATE_BW_VALUE_UNIT_RAW
37382 /* A meter burst size specified in bytes. */
37383 uint32_t excess_peak_burst;
37384 /* The bandwidth value. */
37385 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_BURST_BW_VALUE_MASK \
37386 UINT32_C(0xfffffff)
37387 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_BURST_BW_VALUE_SFT \
37389 /* The granularity of the value (bits or bytes). */
37390 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_BURST_SCALE \
37391 UINT32_C(0x10000000)
37392 /* Value is in bits. */
37393 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_BURST_SCALE_BITS \
37394 (UINT32_C(0x0) << 28)
37395 /* Value is in bytes. */
37396 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_BURST_SCALE_BYTES \
37397 (UINT32_C(0x1) << 28)
37398 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_BURST_SCALE_LAST \
37399 HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_BURST_SCALE_BYTES
37400 /* bw_value_unit is 3 b */
37401 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_BURST_BW_VALUE_UNIT_MASK \
37402 UINT32_C(0xe0000000)
37403 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_BURST_BW_VALUE_UNIT_SFT \
37405 /* Value is in Mb or MB (base 10). */
37406 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_BURST_BW_VALUE_UNIT_MEGA \
37407 (UINT32_C(0x0) << 29)
37408 /* Value is in Kb or KB (base 10). */
37409 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_BURST_BW_VALUE_UNIT_KILO \
37410 (UINT32_C(0x2) << 29)
37411 /* Value is in bits or bytes. */
37412 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_BURST_BW_VALUE_UNIT_BASE \
37413 (UINT32_C(0x4) << 29)
37414 /* Value is in Gb or GB (base 10). */
37415 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_BURST_BW_VALUE_UNIT_GIGA \
37416 (UINT32_C(0x6) << 29)
37417 /* Value is in 1/100th of a percentage of total bandwidth. */
37418 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_BURST_BW_VALUE_UNIT_PERCENT1_100 \
37419 (UINT32_C(0x1) << 29)
37421 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_BURST_BW_VALUE_UNIT_INVALID \
37422 (UINT32_C(0x7) << 29)
37423 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_BURST_BW_VALUE_UNIT_LAST \
37424 HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_BURST_BW_VALUE_UNIT_INVALID
37427 /* hwrm_cfa_meter_profile_cfg_output (size:128b/16B) */
37428 struct hwrm_cfa_meter_profile_cfg_output {
37429 /* The specific error status for the command. */
37430 uint16_t error_code;
37431 /* The HWRM command request type. */
37433 /* The sequence ID from the original command. */
37435 /* The length of the response data in number of bytes. */
37437 uint8_t unused_0[7];
37439 * This field is used in Output records to indicate that the output
37440 * is completely written to RAM. This field should be read as '1'
37441 * to indicate that the output has been completely written.
37442 * When writing a command completion or response to an internal
37443 * processor, the order of writes has to be such that this field is
37449 /*********************************
37450 * hwrm_cfa_meter_instance_alloc *
37451 *********************************/
37454 /* hwrm_cfa_meter_instance_alloc_input (size:192b/24B) */
37455 struct hwrm_cfa_meter_instance_alloc_input {
37456 /* The HWRM command request type. */
37459 * The completion ring to send the completion event on. This should
37460 * be the NQ ID returned from the `nq_alloc` HWRM command.
37462 uint16_t cmpl_ring;
37464 * The sequence ID is used by the driver for tracking multiple
37465 * commands. This ID is treated as opaque data by the firmware and
37466 * the value is returned in the `hwrm_resp_hdr` upon completion.
37470 * The target ID of the command:
37471 * * 0x0-0xFFF8 - The function ID
37472 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
37473 * * 0xFFFD - Reserved for user-space HWRM interface
37476 uint16_t target_id;
37478 * A physical address pointer pointing to a host buffer that the
37479 * command's response data will be written. This can be either a host
37480 * physical address (HPA) or a guest physical address (GPA) and must
37481 * point to a physically contiguous block of memory.
37483 uint64_t resp_addr;
37486 * Enumeration denoting the RX, TX type of the resource.
37487 * This enumeration is used for resources that are similar for both
37488 * TX and RX paths of the chip.
37490 #define HWRM_CFA_METER_INSTANCE_ALLOC_INPUT_FLAGS_PATH \
37493 #define HWRM_CFA_METER_INSTANCE_ALLOC_INPUT_FLAGS_PATH_TX \
37496 #define HWRM_CFA_METER_INSTANCE_ALLOC_INPUT_FLAGS_PATH_RX \
37498 #define HWRM_CFA_METER_INSTANCE_ALLOC_INPUT_FLAGS_PATH_LAST \
37499 HWRM_CFA_METER_INSTANCE_ALLOC_INPUT_FLAGS_PATH_RX
37501 /* This value identifies a meter profile in CFA. */
37502 uint16_t meter_profile_id;
37504 * A value of 0xffff is considered invalid and implies the
37505 * profile is not configured.
37507 #define HWRM_CFA_METER_INSTANCE_ALLOC_INPUT_METER_PROFILE_ID_INVALID \
37509 #define HWRM_CFA_METER_INSTANCE_ALLOC_INPUT_METER_PROFILE_ID_LAST \
37510 HWRM_CFA_METER_INSTANCE_ALLOC_INPUT_METER_PROFILE_ID_INVALID
37511 uint8_t unused_1[4];
37514 /* hwrm_cfa_meter_instance_alloc_output (size:128b/16B) */
37515 struct hwrm_cfa_meter_instance_alloc_output {
37516 /* The specific error status for the command. */
37517 uint16_t error_code;
37518 /* The HWRM command request type. */
37520 /* The sequence ID from the original command. */
37522 /* The length of the response data in number of bytes. */
37524 /* This value identifies a meter instance in CFA. */
37525 uint16_t meter_instance_id;
37527 * A value of 0xffff is considered invalid and implies the
37528 * instance is not configured.
37530 #define HWRM_CFA_METER_INSTANCE_ALLOC_OUTPUT_METER_INSTANCE_ID_INVALID \
37532 #define HWRM_CFA_METER_INSTANCE_ALLOC_OUTPUT_METER_INSTANCE_ID_LAST \
37533 HWRM_CFA_METER_INSTANCE_ALLOC_OUTPUT_METER_INSTANCE_ID_INVALID
37534 uint8_t unused_0[5];
37536 * This field is used in Output records to indicate that the output
37537 * is completely written to RAM. This field should be read as '1'
37538 * to indicate that the output has been completely written.
37539 * When writing a command completion or response to an internal
37540 * processor, the order of writes has to be such that this field is
37546 /*******************************
37547 * hwrm_cfa_meter_instance_cfg *
37548 *******************************/
37551 /* hwrm_cfa_meter_instance_cfg_input (size:192b/24B) */
37552 struct hwrm_cfa_meter_instance_cfg_input {
37553 /* The HWRM command request type. */
37556 * The completion ring to send the completion event on. This should
37557 * be the NQ ID returned from the `nq_alloc` HWRM command.
37559 uint16_t cmpl_ring;
37561 * The sequence ID is used by the driver for tracking multiple
37562 * commands. This ID is treated as opaque data by the firmware and
37563 * the value is returned in the `hwrm_resp_hdr` upon completion.
37567 * The target ID of the command:
37568 * * 0x0-0xFFF8 - The function ID
37569 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
37570 * * 0xFFFD - Reserved for user-space HWRM interface
37573 uint16_t target_id;
37575 * A physical address pointer pointing to a host buffer that the
37576 * command's response data will be written. This can be either a host
37577 * physical address (HPA) or a guest physical address (GPA) and must
37578 * point to a physically contiguous block of memory.
37580 uint64_t resp_addr;
37583 * Enumeration denoting the RX, TX type of the resource.
37584 * This enumeration is used for resources that are similar for both
37585 * TX and RX paths of the chip.
37587 #define HWRM_CFA_METER_INSTANCE_CFG_INPUT_FLAGS_PATH UINT32_C(0x1)
37589 #define HWRM_CFA_METER_INSTANCE_CFG_INPUT_FLAGS_PATH_TX \
37592 #define HWRM_CFA_METER_INSTANCE_CFG_INPUT_FLAGS_PATH_RX \
37594 #define HWRM_CFA_METER_INSTANCE_CFG_INPUT_FLAGS_PATH_LAST \
37595 HWRM_CFA_METER_INSTANCE_CFG_INPUT_FLAGS_PATH_RX
37598 * This value identifies a new meter profile to be associated with
37599 * the meter instance specified in this command.
37601 uint16_t meter_profile_id;
37603 * A value of 0xffff is considered invalid and implies the
37604 * profile is not configured.
37606 #define HWRM_CFA_METER_INSTANCE_CFG_INPUT_METER_PROFILE_ID_INVALID \
37608 #define HWRM_CFA_METER_INSTANCE_CFG_INPUT_METER_PROFILE_ID_LAST \
37609 HWRM_CFA_METER_INSTANCE_CFG_INPUT_METER_PROFILE_ID_INVALID
37611 * This value identifies the ID of a meter instance that needs to be
37612 * updated with a new meter profile specified in this command.
37614 uint16_t meter_instance_id;
37615 uint8_t unused_1[2];
37618 /* hwrm_cfa_meter_instance_cfg_output (size:128b/16B) */
37619 struct hwrm_cfa_meter_instance_cfg_output {
37620 /* The specific error status for the command. */
37621 uint16_t error_code;
37622 /* The HWRM command request type. */
37624 /* The sequence ID from the original command. */
37626 /* The length of the response data in number of bytes. */
37628 uint8_t unused_0[7];
37630 * This field is used in Output records to indicate that the output
37631 * is completely written to RAM. This field should be read as '1'
37632 * to indicate that the output has been completely written.
37633 * When writing a command completion or response to an internal
37634 * processor, the order of writes has to be such that this field is
37640 /********************************
37641 * hwrm_cfa_meter_instance_free *
37642 ********************************/
37645 /* hwrm_cfa_meter_instance_free_input (size:192b/24B) */
37646 struct hwrm_cfa_meter_instance_free_input {
37647 /* The HWRM command request type. */
37650 * The completion ring to send the completion event on. This should
37651 * be the NQ ID returned from the `nq_alloc` HWRM command.
37653 uint16_t cmpl_ring;
37655 * The sequence ID is used by the driver for tracking multiple
37656 * commands. This ID is treated as opaque data by the firmware and
37657 * the value is returned in the `hwrm_resp_hdr` upon completion.
37661 * The target ID of the command:
37662 * * 0x0-0xFFF8 - The function ID
37663 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
37664 * * 0xFFFD - Reserved for user-space HWRM interface
37667 uint16_t target_id;
37669 * A physical address pointer pointing to a host buffer that the
37670 * command's response data will be written. This can be either a host
37671 * physical address (HPA) or a guest physical address (GPA) and must
37672 * point to a physically contiguous block of memory.
37674 uint64_t resp_addr;
37677 * Enumeration denoting the RX, TX type of the resource.
37678 * This enumeration is used for resources that are similar for both
37679 * TX and RX paths of the chip.
37681 #define HWRM_CFA_METER_INSTANCE_FREE_INPUT_FLAGS_PATH UINT32_C(0x1)
37683 #define HWRM_CFA_METER_INSTANCE_FREE_INPUT_FLAGS_PATH_TX \
37686 #define HWRM_CFA_METER_INSTANCE_FREE_INPUT_FLAGS_PATH_RX \
37688 #define HWRM_CFA_METER_INSTANCE_FREE_INPUT_FLAGS_PATH_LAST \
37689 HWRM_CFA_METER_INSTANCE_FREE_INPUT_FLAGS_PATH_RX
37691 /* This value identifies a meter instance in CFA. */
37692 uint16_t meter_instance_id;
37694 * A value of 0xfff is considered invalid and implies the
37695 * instance is not configured.
37697 #define HWRM_CFA_METER_INSTANCE_FREE_INPUT_METER_INSTANCE_ID_INVALID \
37699 #define HWRM_CFA_METER_INSTANCE_FREE_INPUT_METER_INSTANCE_ID_LAST \
37700 HWRM_CFA_METER_INSTANCE_FREE_INPUT_METER_INSTANCE_ID_INVALID
37701 uint8_t unused_1[4];
37704 /* hwrm_cfa_meter_instance_free_output (size:128b/16B) */
37705 struct hwrm_cfa_meter_instance_free_output {
37706 /* The specific error status for the command. */
37707 uint16_t error_code;
37708 /* The HWRM command request type. */
37710 /* The sequence ID from the original command. */
37712 /* The length of the response data in number of bytes. */
37714 uint8_t unused_0[7];
37716 * This field is used in Output records to indicate that the output
37717 * is completely written to RAM. This field should be read as '1'
37718 * to indicate that the output has been completely written.
37719 * When writing a command completion or response to an internal
37720 * processor, the order of writes has to be such that this field is
37726 /*******************************
37727 * hwrm_cfa_decap_filter_alloc *
37728 *******************************/
37731 /* hwrm_cfa_decap_filter_alloc_input (size:832b/104B) */
37732 struct hwrm_cfa_decap_filter_alloc_input {
37733 /* The HWRM command request type. */
37736 * The completion ring to send the completion event on. This should
37737 * be the NQ ID returned from the `nq_alloc` HWRM command.
37739 uint16_t cmpl_ring;
37741 * The sequence ID is used by the driver for tracking multiple
37742 * commands. This ID is treated as opaque data by the firmware and
37743 * the value is returned in the `hwrm_resp_hdr` upon completion.
37747 * The target ID of the command:
37748 * * 0x0-0xFFF8 - The function ID
37749 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
37750 * * 0xFFFD - Reserved for user-space HWRM interface
37753 uint16_t target_id;
37755 * A physical address pointer pointing to a host buffer that the
37756 * command's response data will be written. This can be either a host
37757 * physical address (HPA) or a guest physical address (GPA) and must
37758 * point to a physically contiguous block of memory.
37760 uint64_t resp_addr;
37762 /* ovs_tunnel is 1 b */
37763 #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_FLAGS_OVS_TUNNEL \
37767 * This bit must be '1' for the tunnel_type field to be
37770 #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_ENABLES_TUNNEL_TYPE \
37773 * This bit must be '1' for the tunnel_id field to be
37776 #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_ENABLES_TUNNEL_ID \
37779 * This bit must be '1' for the src_macaddr field to be
37782 #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_ENABLES_SRC_MACADDR \
37785 * This bit must be '1' for the dst_macaddr field to be
37788 #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_ENABLES_DST_MACADDR \
37791 * This bit must be '1' for the ovlan_vid field to be
37794 #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_ENABLES_OVLAN_VID \
37797 * This bit must be '1' for the ivlan_vid field to be
37800 #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_ENABLES_IVLAN_VID \
37803 * This bit must be '1' for the t_ovlan_vid field to be
37806 #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_ENABLES_T_OVLAN_VID \
37809 * This bit must be '1' for the t_ivlan_vid field to be
37812 #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_ENABLES_T_IVLAN_VID \
37815 * This bit must be '1' for the ethertype field to be
37818 #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_ENABLES_ETHERTYPE \
37821 * This bit must be '1' for the src_ipaddr field to be
37824 #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_ENABLES_SRC_IPADDR \
37827 * This bit must be '1' for the dst_ipaddr field to be
37830 #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_ENABLES_DST_IPADDR \
37833 * This bit must be '1' for the ipaddr_type field to be
37836 #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_ENABLES_IPADDR_TYPE \
37839 * This bit must be '1' for the ip_protocol field to be
37842 #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_ENABLES_IP_PROTOCOL \
37845 * This bit must be '1' for the src_port field to be
37848 #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_ENABLES_SRC_PORT \
37851 * This bit must be '1' for the dst_port field to be
37854 #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_ENABLES_DST_PORT \
37857 * This bit must be '1' for the dst_id field to be
37860 #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_ENABLES_DST_ID \
37863 * This bit must be '1' for the mirror_vnic_id field to be
37866 #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_ENABLES_MIRROR_VNIC_ID \
37869 * Tunnel identifier.
37870 * Virtual Network Identifier (VNI). Only valid with
37871 * tunnel_types VXLAN, NVGRE, and Geneve.
37872 * Only lower 24-bits of VNI field are used
37873 * in setting up the filter.
37875 uint32_t tunnel_id;
37877 uint8_t tunnel_type;
37879 #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_TUNNEL_TYPE_NONTUNNEL \
37881 /* Virtual eXtensible Local Area Network (VXLAN) */
37882 #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_TUNNEL_TYPE_VXLAN \
37884 /* Network Virtualization Generic Routing Encapsulation (NVGRE) */
37885 #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_TUNNEL_TYPE_NVGRE \
37887 /* Generic Routing Encapsulation (GRE) inside Ethernet payload */
37888 #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_TUNNEL_TYPE_L2GRE \
37891 #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_TUNNEL_TYPE_IPIP \
37893 /* Generic Network Virtualization Encapsulation (Geneve) */
37894 #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_TUNNEL_TYPE_GENEVE \
37896 /* Multi-Protocol Label Switching (MPLS) */
37897 #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_TUNNEL_TYPE_MPLS \
37899 /* Stateless Transport Tunnel (STT) */
37900 #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_TUNNEL_TYPE_STT \
37902 /* Generic Routing Encapsulation (GRE) inside IP datagram payload */
37903 #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_TUNNEL_TYPE_IPGRE \
37905 /* IPV4 over virtual eXtensible Local Area Network (IPV4oVXLAN) */
37906 #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_TUNNEL_TYPE_VXLAN_V4 \
37909 * Enhance Generic Routing Encapsulation (GRE version 1) inside IP
37912 #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_TUNNEL_TYPE_IPGRE_V1 \
37914 /* Use fixed layer 2 ether type of 0xFFFF */
37915 #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_TUNNEL_TYPE_L2_ETYPE \
37918 * IPV6 over virtual eXtensible Local Area Network with GPE header
37921 #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_TUNNEL_TYPE_VXLAN_GPE_V6 \
37923 /* Any tunneled traffic */
37924 #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_TUNNEL_TYPE_ANYTUNNEL \
37926 #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_TUNNEL_TYPE_LAST \
37927 HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_TUNNEL_TYPE_ANYTUNNEL
37931 * This value indicates the source MAC address in
37932 * the Ethernet header.
37934 uint8_t src_macaddr[6];
37935 uint8_t unused_2[2];
37937 * This value indicates the destination MAC address in
37938 * the Ethernet header.
37940 uint8_t dst_macaddr[6];
37942 * This value indicates the VLAN ID of the outer VLAN tag
37943 * in the Ethernet header.
37945 uint16_t ovlan_vid;
37947 * This value indicates the VLAN ID of the inner VLAN tag
37948 * in the Ethernet header.
37950 uint16_t ivlan_vid;
37952 * This value indicates the VLAN ID of the outer VLAN tag
37953 * in the tunnel Ethernet header.
37955 uint16_t t_ovlan_vid;
37957 * This value indicates the VLAN ID of the inner VLAN tag
37958 * in the tunnel Ethernet header.
37960 uint16_t t_ivlan_vid;
37961 /* This value indicates the ethertype in the Ethernet header. */
37962 uint16_t ethertype;
37964 * This value indicates the type of IP address.
37967 * All others are invalid.
37969 uint8_t ip_addr_type;
37971 #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_IP_ADDR_TYPE_UNKNOWN \
37974 #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_IP_ADDR_TYPE_IPV4 \
37977 #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_IP_ADDR_TYPE_IPV6 \
37979 #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_IP_ADDR_TYPE_LAST \
37980 HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_IP_ADDR_TYPE_IPV6
37982 * The value of protocol filed in IP header.
37983 * Applies to UDP and TCP traffic.
37987 uint8_t ip_protocol;
37989 #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_IP_PROTOCOL_UNKNOWN \
37992 #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_IP_PROTOCOL_TCP \
37995 #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_IP_PROTOCOL_UDP \
37997 #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_IP_PROTOCOL_LAST \
37998 HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_IP_PROTOCOL_UDP
38002 * The value of source IP address to be used in filtering.
38003 * For IPv4, first four bytes represent the IP address.
38005 uint32_t src_ipaddr[4];
38007 * The value of destination IP address to be used in filtering.
38008 * For IPv4, first four bytes represent the IP address.
38010 uint32_t dst_ipaddr[4];
38012 * The value of source port to be used in filtering.
38013 * Applies to UDP and TCP traffic.
38017 * The value of destination port to be used in filtering.
38018 * Applies to UDP and TCP traffic.
38022 * If set, this value shall represent the
38023 * Logical VNIC ID of the destination VNIC for the RX
38028 * If set, this value shall represent the L2 context that matches the
38029 * L2 information of the decap filter.
38031 uint16_t l2_ctxt_ref_id;
38034 /* hwrm_cfa_decap_filter_alloc_output (size:128b/16B) */
38035 struct hwrm_cfa_decap_filter_alloc_output {
38036 /* The specific error status for the command. */
38037 uint16_t error_code;
38038 /* The HWRM command request type. */
38040 /* The sequence ID from the original command. */
38042 /* The length of the response data in number of bytes. */
38044 /* This value is an opaque id into CFA data structures. */
38045 uint32_t decap_filter_id;
38046 uint8_t unused_0[3];
38048 * This field is used in Output records to indicate that the output
38049 * is completely written to RAM. This field should be read as '1'
38050 * to indicate that the output has been completely written.
38051 * When writing a command completion or response to an internal
38052 * processor, the order of writes has to be such that this field is
38058 /******************************
38059 * hwrm_cfa_decap_filter_free *
38060 ******************************/
38063 /* hwrm_cfa_decap_filter_free_input (size:192b/24B) */
38064 struct hwrm_cfa_decap_filter_free_input {
38065 /* The HWRM command request type. */
38068 * The completion ring to send the completion event on. This should
38069 * be the NQ ID returned from the `nq_alloc` HWRM command.
38071 uint16_t cmpl_ring;
38073 * The sequence ID is used by the driver for tracking multiple
38074 * commands. This ID is treated as opaque data by the firmware and
38075 * the value is returned in the `hwrm_resp_hdr` upon completion.
38079 * The target ID of the command:
38080 * * 0x0-0xFFF8 - The function ID
38081 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
38082 * * 0xFFFD - Reserved for user-space HWRM interface
38085 uint16_t target_id;
38087 * A physical address pointer pointing to a host buffer that the
38088 * command's response data will be written. This can be either a host
38089 * physical address (HPA) or a guest physical address (GPA) and must
38090 * point to a physically contiguous block of memory.
38092 uint64_t resp_addr;
38093 /* This value is an opaque id into CFA data structures. */
38094 uint32_t decap_filter_id;
38095 uint8_t unused_0[4];
38098 /* hwrm_cfa_decap_filter_free_output (size:128b/16B) */
38099 struct hwrm_cfa_decap_filter_free_output {
38100 /* The specific error status for the command. */
38101 uint16_t error_code;
38102 /* The HWRM command request type. */
38104 /* The sequence ID from the original command. */
38106 /* The length of the response data in number of bytes. */
38108 uint8_t unused_0[7];
38110 * This field is used in Output records to indicate that the output
38111 * is completely written to RAM. This field should be read as '1'
38112 * to indicate that the output has been completely written.
38113 * When writing a command completion or response to an internal
38114 * processor, the order of writes has to be such that this field is
38120 /***********************
38121 * hwrm_cfa_flow_alloc *
38122 ***********************/
38125 /* hwrm_cfa_flow_alloc_input (size:1024b/128B) */
38126 struct hwrm_cfa_flow_alloc_input {
38127 /* The HWRM command request type. */
38130 * The completion ring to send the completion event on. This should
38131 * be the NQ ID returned from the `nq_alloc` HWRM command.
38133 uint16_t cmpl_ring;
38135 * The sequence ID is used by the driver for tracking multiple
38136 * commands. This ID is treated as opaque data by the firmware and
38137 * the value is returned in the `hwrm_resp_hdr` upon completion.
38141 * The target ID of the command:
38142 * * 0x0-0xFFF8 - The function ID
38143 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
38144 * * 0xFFFD - Reserved for user-space HWRM interface
38147 uint16_t target_id;
38149 * A physical address pointer pointing to a host buffer that the
38150 * command's response data will be written. This can be either a host
38151 * physical address (HPA) or a guest physical address (GPA) and must
38152 * point to a physically contiguous block of memory.
38154 uint64_t resp_addr;
38156 /* tunnel is 1 b */
38157 #define HWRM_CFA_FLOW_ALLOC_INPUT_FLAGS_TUNNEL \
38159 /* num_vlan is 2 b */
38160 #define HWRM_CFA_FLOW_ALLOC_INPUT_FLAGS_NUM_VLAN_MASK \
38162 #define HWRM_CFA_FLOW_ALLOC_INPUT_FLAGS_NUM_VLAN_SFT 1
38164 #define HWRM_CFA_FLOW_ALLOC_INPUT_FLAGS_NUM_VLAN_NONE \
38165 (UINT32_C(0x0) << 1)
38167 #define HWRM_CFA_FLOW_ALLOC_INPUT_FLAGS_NUM_VLAN_ONE \
38168 (UINT32_C(0x1) << 1)
38170 #define HWRM_CFA_FLOW_ALLOC_INPUT_FLAGS_NUM_VLAN_TWO \
38171 (UINT32_C(0x2) << 1)
38172 #define HWRM_CFA_FLOW_ALLOC_INPUT_FLAGS_NUM_VLAN_LAST \
38173 HWRM_CFA_FLOW_ALLOC_INPUT_FLAGS_NUM_VLAN_TWO
38174 /* Enumeration denoting the Flow Type. */
38175 #define HWRM_CFA_FLOW_ALLOC_INPUT_FLAGS_FLOWTYPE_MASK \
38177 #define HWRM_CFA_FLOW_ALLOC_INPUT_FLAGS_FLOWTYPE_SFT 3
38179 #define HWRM_CFA_FLOW_ALLOC_INPUT_FLAGS_FLOWTYPE_L2 \
38180 (UINT32_C(0x0) << 3)
38182 #define HWRM_CFA_FLOW_ALLOC_INPUT_FLAGS_FLOWTYPE_IPV4 \
38183 (UINT32_C(0x1) << 3)
38185 #define HWRM_CFA_FLOW_ALLOC_INPUT_FLAGS_FLOWTYPE_IPV6 \
38186 (UINT32_C(0x2) << 3)
38187 #define HWRM_CFA_FLOW_ALLOC_INPUT_FLAGS_FLOWTYPE_LAST \
38188 HWRM_CFA_FLOW_ALLOC_INPUT_FLAGS_FLOWTYPE_IPV6
38190 * when set to 1, indicates TX flow offload for function specified
38191 * in src_fid and the dst_fid should be set to invalid value. To
38192 * indicate a VM to VM flow, both of the path_tx and path_rx flags
38193 * need to be set. For virtio vSwitch offload case, the src_fid and
38194 * dst_fid is set to the same fid value. For the SRIOV vSwitch
38195 * offload case, the src_fid and dst_fid must be set to the same VF
38196 * FID belong to the children VFs of the same PF to indicate VM to
38199 #define HWRM_CFA_FLOW_ALLOC_INPUT_FLAGS_PATH_TX \
38202 * when set to 1, indicates RX flow offload for function specified
38203 * in dst_fid and the src_fid should be set to invalid value.
38205 #define HWRM_CFA_FLOW_ALLOC_INPUT_FLAGS_PATH_RX \
38208 * Set to 1 to indicate matching of VXLAN VNI from the custom vxlan
38209 * header is required and the VXLAN VNI value is stored in the first
38210 * 24 bits of the dmac field. This flag is only valid when the flow
38213 #define HWRM_CFA_FLOW_ALLOC_INPUT_FLAGS_MATCH_VXLAN_IP_VNI \
38216 * Set to 1 to indicate vhost_id is specified in the outer_vlan_tci
38219 #define HWRM_CFA_FLOW_ALLOC_INPUT_FLAGS_VHOST_ID_USE_VLAN \
38226 /* Tunnel handle valid when tunnel flag is set. */
38227 uint32_t tunnel_handle;
38228 uint16_t action_flags;
38230 * Setting of this flag indicates drop action. If this flag is not
38231 * set, then it should be considered accept action.
38233 #define HWRM_CFA_FLOW_ALLOC_INPUT_ACTION_FLAGS_FWD \
38235 /* recycle is 1 b */
38236 #define HWRM_CFA_FLOW_ALLOC_INPUT_ACTION_FLAGS_RECYCLE \
38239 * Setting of this flag indicates drop action. If this flag is not
38240 * set, then it should be considered accept action.
38242 #define HWRM_CFA_FLOW_ALLOC_INPUT_ACTION_FLAGS_DROP \
38245 #define HWRM_CFA_FLOW_ALLOC_INPUT_ACTION_FLAGS_METER \
38247 /* tunnel is 1 b */
38248 #define HWRM_CFA_FLOW_ALLOC_INPUT_ACTION_FLAGS_TUNNEL \
38250 /* nat_src is 1 b */
38251 #define HWRM_CFA_FLOW_ALLOC_INPUT_ACTION_FLAGS_NAT_SRC \
38253 /* nat_dest is 1 b */
38254 #define HWRM_CFA_FLOW_ALLOC_INPUT_ACTION_FLAGS_NAT_DEST \
38256 /* nat_ipv4_address is 1 b */
38257 #define HWRM_CFA_FLOW_ALLOC_INPUT_ACTION_FLAGS_NAT_IPV4_ADDRESS \
38259 /* l2_header_rewrite is 1 b */
38260 #define HWRM_CFA_FLOW_ALLOC_INPUT_ACTION_FLAGS_L2_HEADER_REWRITE \
38262 /* ttl_decrement is 1 b */
38263 #define HWRM_CFA_FLOW_ALLOC_INPUT_ACTION_FLAGS_TTL_DECREMENT \
38266 * If set to 1 and flow direction is TX, it indicates decap of L2
38267 * header and encap of tunnel header. If set to 1 and flow direction
38268 * is RX, it indicates decap of tunnel header and encap L2 header.
38269 * The type of tunnel is specified in the tunnel_type field.
38271 #define HWRM_CFA_FLOW_ALLOC_INPUT_ACTION_FLAGS_TUNNEL_IP \
38273 /* If set to 1, flow aging is enabled for this flow. */
38274 #define HWRM_CFA_FLOW_ALLOC_INPUT_ACTION_FLAGS_FLOW_AGING_ENABLED \
38277 * If set to 1 an attempt will be made to try to offload this flow
38278 * to the most optimal flow table resource. If set to 0, the flow
38279 * will be placed to the default flow table resource.
38281 #define HWRM_CFA_FLOW_ALLOC_INPUT_ACTION_FLAGS_PRI_HINT \
38284 * If set to 1 there will be no attempt to allocate an on-chip try
38285 * to offload this flow. If set to 0, which will keep compatibility
38286 * with the older drivers, will cause the FW to attempt to allocate
38287 * an on-chip flow counter for the newly created flow. This will
38288 * keep the existing behavior with EM flows which always had an
38289 * associated flow counter.
38291 #define HWRM_CFA_FLOW_ALLOC_INPUT_ACTION_FLAGS_NO_FLOW_COUNTER_ALLOC \
38294 * Tx Flow: pf or vf fid.
38298 /* VLAN tpid, valid when push_vlan flag is set. */
38299 uint16_t l2_rewrite_vlan_tpid;
38300 /* VLAN tci, valid when push_vlan flag is set. */
38301 uint16_t l2_rewrite_vlan_tci;
38302 /* Meter id, valid when meter flag is set. */
38303 uint16_t act_meter_id;
38304 /* Flow with the same l2 context tcam key. */
38305 uint16_t ref_flow_handle;
38306 /* This value sets the match value for the ethertype. */
38307 uint16_t ethertype;
38308 /* valid when num tags is 1 or 2. */
38309 uint16_t outer_vlan_tci;
38310 /* This value sets the match value for the Destination MAC address. */
38312 /* valid when num tags is 2. */
38313 uint16_t inner_vlan_tci;
38314 /* This value sets the match value for the Source MAC address. */
38316 /* The bit length of destination IP address mask. */
38317 uint8_t ip_dst_mask_len;
38318 /* The bit length of source IP address mask. */
38319 uint8_t ip_src_mask_len;
38320 /* The value of destination IPv4/IPv6 address. */
38321 uint32_t ip_dst[4];
38322 /* The source IPv4/IPv6 address. */
38323 uint32_t ip_src[4];
38325 * The value of source port.
38326 * Applies to UDP and TCP traffic.
38328 uint16_t l4_src_port;
38330 * The value of source port mask.
38331 * Applies to UDP and TCP traffic.
38333 uint16_t l4_src_port_mask;
38335 * The value of destination port.
38336 * Applies to UDP and TCP traffic.
38338 uint16_t l4_dst_port;
38340 * The value of destination port mask.
38341 * Applies to UDP and TCP traffic.
38343 uint16_t l4_dst_port_mask;
38345 * NAT IPv4/6 address based on address type flag.
38346 * 0 values are ignored.
38348 uint32_t nat_ip_address[4];
38349 /* L2 header re-write Destination MAC address. */
38350 uint16_t l2_rewrite_dmac[3];
38352 * The NAT source/destination port based on direction flag.
38353 * Applies to UDP and TCP traffic.
38354 * 0 values are ignored.
38357 /* L2 header re-write Source MAC address. */
38358 uint16_t l2_rewrite_smac[3];
38359 /* The value of ip protocol. */
38362 uint8_t tunnel_type;
38364 #define HWRM_CFA_FLOW_ALLOC_INPUT_TUNNEL_TYPE_NONTUNNEL \
38366 /* Virtual eXtensible Local Area Network (VXLAN) */
38367 #define HWRM_CFA_FLOW_ALLOC_INPUT_TUNNEL_TYPE_VXLAN \
38369 /* Network Virtualization Generic Routing Encapsulation (NVGRE) */
38370 #define HWRM_CFA_FLOW_ALLOC_INPUT_TUNNEL_TYPE_NVGRE \
38372 /* Generic Routing Encapsulation (GRE) inside Ethernet payload */
38373 #define HWRM_CFA_FLOW_ALLOC_INPUT_TUNNEL_TYPE_L2GRE \
38376 #define HWRM_CFA_FLOW_ALLOC_INPUT_TUNNEL_TYPE_IPIP \
38378 /* Generic Network Virtualization Encapsulation (Geneve) */
38379 #define HWRM_CFA_FLOW_ALLOC_INPUT_TUNNEL_TYPE_GENEVE \
38381 /* Multi-Protocol Label Switching (MPLS) */
38382 #define HWRM_CFA_FLOW_ALLOC_INPUT_TUNNEL_TYPE_MPLS \
38384 /* Stateless Transport Tunnel (STT) */
38385 #define HWRM_CFA_FLOW_ALLOC_INPUT_TUNNEL_TYPE_STT \
38387 /* Generic Routing Encapsulation (GRE) inside IP datagram payload */
38388 #define HWRM_CFA_FLOW_ALLOC_INPUT_TUNNEL_TYPE_IPGRE \
38390 /* IPV4 over virtual eXtensible Local Area Network (IPV4oVXLAN) */
38391 #define HWRM_CFA_FLOW_ALLOC_INPUT_TUNNEL_TYPE_VXLAN_V4 \
38394 * Enhance Generic Routing Encapsulation (GRE version 1) inside IP
38397 #define HWRM_CFA_FLOW_ALLOC_INPUT_TUNNEL_TYPE_IPGRE_V1 \
38399 /* Use fixed layer 2 ether type of 0xFFFF */
38400 #define HWRM_CFA_FLOW_ALLOC_INPUT_TUNNEL_TYPE_L2_ETYPE \
38403 * IPV6 over virtual eXtensible Local Area Network with GPE header
38406 #define HWRM_CFA_FLOW_ALLOC_INPUT_TUNNEL_TYPE_VXLAN_GPE_V6 \
38408 /* Any tunneled traffic */
38409 #define HWRM_CFA_FLOW_ALLOC_INPUT_TUNNEL_TYPE_ANYTUNNEL \
38411 #define HWRM_CFA_FLOW_ALLOC_INPUT_TUNNEL_TYPE_LAST \
38412 HWRM_CFA_FLOW_ALLOC_INPUT_TUNNEL_TYPE_ANYTUNNEL
38415 /* hwrm_cfa_flow_alloc_output (size:256b/32B) */
38416 struct hwrm_cfa_flow_alloc_output {
38417 /* The specific error status for the command. */
38418 uint16_t error_code;
38419 /* The HWRM command request type. */
38421 /* The sequence ID from the original command. */
38423 /* The length of the response data in number of bytes. */
38425 /* Flow record index. */
38426 uint16_t flow_handle;
38427 uint8_t unused_0[2];
38429 * The flow id value in bit 0-29 is the actual ID of the flow
38430 * associated with this filter and it shall be used to match
38431 * and associate the flow identifier returned in completion
38432 * records. A value of 0xFFFFFFFF in the 32-bit flow_id field
38433 * shall indicate no valid flow id.
38436 /* Indicate the flow id value. */
38437 #define HWRM_CFA_FLOW_ALLOC_OUTPUT_FLOW_ID_VALUE_MASK \
38438 UINT32_C(0x3fffffff)
38439 #define HWRM_CFA_FLOW_ALLOC_OUTPUT_FLOW_ID_VALUE_SFT 0
38440 /* Indicate type of the flow. */
38441 #define HWRM_CFA_FLOW_ALLOC_OUTPUT_FLOW_ID_TYPE \
38442 UINT32_C(0x40000000)
38444 * If this bit set to 0, then it indicates that the flow is
38447 #define HWRM_CFA_FLOW_ALLOC_OUTPUT_FLOW_ID_TYPE_INT \
38448 (UINT32_C(0x0) << 30)
38450 * If this bit is set to 1, then it indicates that the flow is
38453 #define HWRM_CFA_FLOW_ALLOC_OUTPUT_FLOW_ID_TYPE_EXT \
38454 (UINT32_C(0x1) << 30)
38455 #define HWRM_CFA_FLOW_ALLOC_OUTPUT_FLOW_ID_TYPE_LAST \
38456 HWRM_CFA_FLOW_ALLOC_OUTPUT_FLOW_ID_TYPE_EXT
38457 /* Indicate the flow direction. */
38458 #define HWRM_CFA_FLOW_ALLOC_OUTPUT_FLOW_ID_DIR \
38459 UINT32_C(0x80000000)
38460 /* If this bit set to 0, then it indicates rx flow. */
38461 #define HWRM_CFA_FLOW_ALLOC_OUTPUT_FLOW_ID_DIR_RX \
38462 (UINT32_C(0x0) << 31)
38463 /* If this bit is set to 1, then it indicates that tx flow. */
38464 #define HWRM_CFA_FLOW_ALLOC_OUTPUT_FLOW_ID_DIR_TX \
38465 (UINT32_C(0x1) << 31)
38466 #define HWRM_CFA_FLOW_ALLOC_OUTPUT_FLOW_ID_DIR_LAST \
38467 HWRM_CFA_FLOW_ALLOC_OUTPUT_FLOW_ID_DIR_TX
38468 /* This value identifies a set of CFA data structures used for a flow. */
38469 uint64_t ext_flow_handle;
38470 uint32_t flow_counter_id;
38471 uint8_t unused_1[3];
38473 * This field is used in Output records to indicate that the output
38474 * is completely written to RAM. This field should be read as '1'
38475 * to indicate that the output has been completely written.
38476 * When writing a command completion or response to an internal
38477 * processor, the order of writes has to be such that this field is
38483 /* hwrm_cfa_flow_alloc_cmd_err (size:64b/8B) */
38484 struct hwrm_cfa_flow_alloc_cmd_err {
38486 * command specific error codes that goes to
38487 * the cmd_err field in Common HWRM Error Response.
38490 /* Unknown error */
38491 #define HWRM_CFA_FLOW_ALLOC_CMD_ERR_CODE_UNKNOWN UINT32_C(0x0)
38492 /* No more L2 Context TCAM */
38493 #define HWRM_CFA_FLOW_ALLOC_CMD_ERR_CODE_L2_CONTEXT_TCAM UINT32_C(0x1)
38494 /* No more action records */
38495 #define HWRM_CFA_FLOW_ALLOC_CMD_ERR_CODE_ACTION_RECORD UINT32_C(0x2)
38496 /* No more flow counters */
38497 #define HWRM_CFA_FLOW_ALLOC_CMD_ERR_CODE_FLOW_COUNTER UINT32_C(0x3)
38498 /* No more wild-card TCAM */
38499 #define HWRM_CFA_FLOW_ALLOC_CMD_ERR_CODE_WILD_CARD_TCAM UINT32_C(0x4)
38500 /* Hash collsion in exact match tables */
38501 #define HWRM_CFA_FLOW_ALLOC_CMD_ERR_CODE_HASH_COLLISION UINT32_C(0x5)
38502 /* Key is already installed */
38503 #define HWRM_CFA_FLOW_ALLOC_CMD_ERR_CODE_KEY_EXISTS UINT32_C(0x6)
38504 /* Flow Context DB is out of resource */
38505 #define HWRM_CFA_FLOW_ALLOC_CMD_ERR_CODE_FLOW_CTXT_DB UINT32_C(0x7)
38506 #define HWRM_CFA_FLOW_ALLOC_CMD_ERR_CODE_LAST \
38507 HWRM_CFA_FLOW_ALLOC_CMD_ERR_CODE_FLOW_CTXT_DB
38508 uint8_t unused_0[7];
38511 /**********************
38512 * hwrm_cfa_flow_free *
38513 **********************/
38516 /* hwrm_cfa_flow_free_input (size:256b/32B) */
38517 struct hwrm_cfa_flow_free_input {
38518 /* The HWRM command request type. */
38521 * The completion ring to send the completion event on. This should
38522 * be the NQ ID returned from the `nq_alloc` HWRM command.
38524 uint16_t cmpl_ring;
38526 * The sequence ID is used by the driver for tracking multiple
38527 * commands. This ID is treated as opaque data by the firmware and
38528 * the value is returned in the `hwrm_resp_hdr` upon completion.
38532 * The target ID of the command:
38533 * * 0x0-0xFFF8 - The function ID
38534 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
38535 * * 0xFFFD - Reserved for user-space HWRM interface
38538 uint16_t target_id;
38540 * A physical address pointer pointing to a host buffer that the
38541 * command's response data will be written. This can be either a host
38542 * physical address (HPA) or a guest physical address (GPA) and must
38543 * point to a physically contiguous block of memory.
38545 uint64_t resp_addr;
38546 /* Flow record index. */
38547 uint16_t flow_handle;
38549 /* Flow counter id to be freed. */
38550 uint32_t flow_counter_id;
38551 /* This value identifies a set of CFA data structures used for a flow. */
38552 uint64_t ext_flow_handle;
38555 /* hwrm_cfa_flow_free_output (size:256b/32B) */
38556 struct hwrm_cfa_flow_free_output {
38557 /* The specific error status for the command. */
38558 uint16_t error_code;
38559 /* The HWRM command request type. */
38561 /* The sequence ID from the original command. */
38563 /* The length of the response data in number of bytes. */
38565 /* packet is 64 b */
38569 uint8_t unused_0[7];
38571 * This field is used in Output records to indicate that the output
38572 * is completely written to RAM. This field should be read as '1'
38573 * to indicate that the output has been completely written.
38574 * When writing a command completion or response to an internal
38575 * processor, the order of writes has to be such that this field is
38581 /* hwrm_cfa_flow_action_data (size:960b/120B) */
38582 struct hwrm_cfa_flow_action_data {
38583 uint16_t action_flags;
38584 /* Setting of this flag indicates accept action. */
38585 #define HWRM_CFA_FLOW_ACTION_DATA_ACTION_FLAGS_FWD \
38587 /* Setting of this flag indicates recycle action. */
38588 #define HWRM_CFA_FLOW_ACTION_DATA_ACTION_FLAGS_RECYCLE \
38590 /* Setting of this flag indicates drop action. */
38591 #define HWRM_CFA_FLOW_ACTION_DATA_ACTION_FLAGS_DROP \
38593 /* Setting of this flag indicates meter action. */
38594 #define HWRM_CFA_FLOW_ACTION_DATA_ACTION_FLAGS_METER \
38596 /* Setting of this flag indicates tunnel action. */
38597 #define HWRM_CFA_FLOW_ACTION_DATA_ACTION_FLAGS_TUNNEL \
38600 * If set to 1 and flow direction is TX, it indicates decap of L2
38601 * header and encap of tunnel header. If set to 1 and flow direction
38602 * is RX, it indicates decap of tunnel header and encap L2 header.
38604 #define HWRM_CFA_FLOW_ACTION_DATA_ACTION_FLAGS_TUNNEL_IP \
38606 /* Setting of this flag indicates ttl decrement action. */
38607 #define HWRM_CFA_FLOW_ACTION_DATA_ACTION_FLAGS_TTL_DECREMENT \
38609 /* If set to 1, flow aging is enabled for this flow. */
38610 #define HWRM_CFA_FLOW_ACTION_DATA_ACTION_FLAGS_FLOW_AGING_ENABLED \
38612 /* Setting of this flag indicates encap action. */
38613 #define HWRM_CFA_FLOW_ACTION_DATA_ACTION_FLAGS_ENCAP \
38615 /* Setting of this flag indicates decap action. */
38616 #define HWRM_CFA_FLOW_ACTION_DATA_ACTION_FLAGS_DECAP \
38619 uint16_t act_meter_id;
38622 /* vport number. */
38624 /* The NAT source/destination. */
38626 uint16_t unused_0[3];
38627 /* NAT IPv4/IPv6 address. */
38628 uint32_t nat_ip_address[4];
38629 /* Encapsulation Type. */
38630 uint8_t encap_type;
38631 /* Virtual eXtensible Local Area Network (VXLAN) */
38632 #define HWRM_CFA_FLOW_ACTION_DATA_ENCAP_TYPE_VXLAN UINT32_C(0x1)
38633 /* Network Virtualization Generic Routing Encapsulation (NVGRE) */
38634 #define HWRM_CFA_FLOW_ACTION_DATA_ENCAP_TYPE_NVGRE UINT32_C(0x2)
38635 /* Generic Routing Encapsulation (GRE) after inside Ethernet payload */
38636 #define HWRM_CFA_FLOW_ACTION_DATA_ENCAP_TYPE_L2GRE UINT32_C(0x3)
38638 #define HWRM_CFA_FLOW_ACTION_DATA_ENCAP_TYPE_IPIP UINT32_C(0x4)
38639 /* Generic Network Virtualization Encapsulation (Geneve) */
38640 #define HWRM_CFA_FLOW_ACTION_DATA_ENCAP_TYPE_GENEVE UINT32_C(0x5)
38641 /* Multi-Protocol Label Switching (MPLS) */
38642 #define HWRM_CFA_FLOW_ACTION_DATA_ENCAP_TYPE_MPLS UINT32_C(0x6)
38644 #define HWRM_CFA_FLOW_ACTION_DATA_ENCAP_TYPE_VLAN UINT32_C(0x7)
38645 /* Generic Routing Encapsulation (GRE) inside IP datagram payload */
38646 #define HWRM_CFA_FLOW_ACTION_DATA_ENCAP_TYPE_IPGRE UINT32_C(0x8)
38647 /* IPV4 over virtual eXtensible Local Area Network (IPV4oVXLAN) */
38648 #define HWRM_CFA_FLOW_ACTION_DATA_ENCAP_TYPE_VXLAN_V4 UINT32_C(0x9)
38650 * Enhance Generic Routing Encapsulation (GRE version 1) inside IP
38653 #define HWRM_CFA_FLOW_ACTION_DATA_ENCAP_TYPE_IPGRE_V1 UINT32_C(0xa)
38654 /* Use fixed layer 2 ether type of 0xFFFF */
38655 #define HWRM_CFA_FLOW_ACTION_DATA_ENCAP_TYPE_L2_ETYPE UINT32_C(0xb)
38657 * IPV6 over virtual eXtensible Local Area Network with GPE header
38660 #define HWRM_CFA_FLOW_ACTION_DATA_ENCAP_TYPE_VXLAN_GPE_V6 UINT32_C(0xc)
38661 #define HWRM_CFA_FLOW_ACTION_DATA_ENCAP_TYPE_LAST \
38662 HWRM_CFA_FLOW_ACTION_DATA_ENCAP_TYPE_VXLAN_GPE_V6
38664 /* This value is encap data for the associated encap type. */
38665 uint32_t encap_data[20];
38668 /* hwrm_cfa_flow_tunnel_hdr_data (size:64b/8B) */
38669 struct hwrm_cfa_flow_tunnel_hdr_data {
38671 uint8_t tunnel_type;
38673 #define HWRM_CFA_FLOW_TUNNEL_HDR_DATA_TUNNEL_TYPE_NONTUNNEL \
38675 /* Virtual eXtensible Local Area Network (VXLAN) */
38676 #define HWRM_CFA_FLOW_TUNNEL_HDR_DATA_TUNNEL_TYPE_VXLAN \
38678 /* Network Virtualization Generic Routing Encapsulation (NVGRE) */
38679 #define HWRM_CFA_FLOW_TUNNEL_HDR_DATA_TUNNEL_TYPE_NVGRE \
38681 /* Generic Routing Encapsulation (GRE) inside Ethernet payload */
38682 #define HWRM_CFA_FLOW_TUNNEL_HDR_DATA_TUNNEL_TYPE_L2GRE \
38685 #define HWRM_CFA_FLOW_TUNNEL_HDR_DATA_TUNNEL_TYPE_IPIP \
38687 /* Generic Network Virtualization Encapsulation (Geneve) */
38688 #define HWRM_CFA_FLOW_TUNNEL_HDR_DATA_TUNNEL_TYPE_GENEVE \
38690 /* Multi-Protocol Label Switching (MPLS) */
38691 #define HWRM_CFA_FLOW_TUNNEL_HDR_DATA_TUNNEL_TYPE_MPLS \
38693 /* Stateless Transport Tunnel (STT) */
38694 #define HWRM_CFA_FLOW_TUNNEL_HDR_DATA_TUNNEL_TYPE_STT \
38696 /* Generic Routing Encapsulation (GRE) inside IP datagram payload */
38697 #define HWRM_CFA_FLOW_TUNNEL_HDR_DATA_TUNNEL_TYPE_IPGRE \
38699 /* IPV4 over virtual eXtensible Local Area Network (IPV4oVXLAN) */
38700 #define HWRM_CFA_FLOW_TUNNEL_HDR_DATA_TUNNEL_TYPE_VXLAN_V4 \
38703 * Enhance Generic Routing Encapsulation (GRE version 1) inside IP
38706 #define HWRM_CFA_FLOW_TUNNEL_HDR_DATA_TUNNEL_TYPE_IPGRE_V1 \
38708 /* Use fixed layer 2 ether type of 0xFFFF */
38709 #define HWRM_CFA_FLOW_TUNNEL_HDR_DATA_TUNNEL_TYPE_L2_ETYPE \
38712 * IPV6 over virtual eXtensible Local Area Network with GPE header
38715 #define HWRM_CFA_FLOW_TUNNEL_HDR_DATA_TUNNEL_TYPE_VXLAN_GPE_V6 \
38717 /* Any tunneled traffic */
38718 #define HWRM_CFA_FLOW_TUNNEL_HDR_DATA_TUNNEL_TYPE_ANYTUNNEL \
38720 #define HWRM_CFA_FLOW_TUNNEL_HDR_DATA_TUNNEL_TYPE_LAST \
38721 HWRM_CFA_FLOW_TUNNEL_HDR_DATA_TUNNEL_TYPE_ANYTUNNEL
38724 * Tunnel identifier.
38725 * Virtual Network Identifier (VNI).
38727 uint32_t tunnel_id;
38730 /* hwrm_cfa_flow_l4_key_data (size:64b/8B) */
38731 struct hwrm_cfa_flow_l4_key_data {
38732 /* The value of source port. */
38733 uint16_t l4_src_port;
38734 /* The value of destination port. */
38735 uint16_t l4_dst_port;
38739 /* hwrm_cfa_flow_l3_key_data (size:512b/64B) */
38740 struct hwrm_cfa_flow_l3_key_data {
38741 /* The value of ip protocol. */
38742 uint8_t ip_protocol;
38743 uint8_t unused_0[7];
38744 /* The value of destination IPv4/IPv6 address. */
38745 uint32_t ip_dst[4];
38746 /* The source IPv4/IPv6 address. */
38747 uint32_t ip_src[4];
38748 /* NAT IPv4/IPv6 address. */
38749 uint32_t nat_ip_address[4];
38750 uint32_t unused[2];
38753 /* hwrm_cfa_flow_l2_key_data (size:448b/56B) */
38754 struct hwrm_cfa_flow_l2_key_data {
38755 /* Destination MAC address. */
38758 /* Source MAC address. */
38761 /* L2 header re-write Destination MAC address. */
38762 uint16_t l2_rewrite_dmac[3];
38764 /* L2 header re-write Source MAC address. */
38765 uint16_t l2_rewrite_smac[3];
38767 uint16_t ethertype;
38768 /* Number of VLAN tags. */
38769 uint16_t num_vlan_tags;
38771 uint16_t l2_rewrite_vlan_tpid;
38773 uint16_t l2_rewrite_vlan_tci;
38774 uint8_t unused_3[2];
38775 /* Outer VLAN TPID. */
38776 uint16_t ovlan_tpid;
38777 /* Outer VLAN TCI. */
38778 uint16_t ovlan_tci;
38779 /* Inner VLAN TPID. */
38780 uint16_t ivlan_tpid;
38781 /* Inner VLAN TCI. */
38782 uint16_t ivlan_tci;
38786 /* hwrm_cfa_flow_key_data (size:4160b/520B) */
38787 struct hwrm_cfa_flow_key_data {
38788 /* Flow associated tunnel L2 header key info. */
38789 uint32_t t_l2_key_data[14];
38790 /* Flow associated tunnel L2 header mask info. */
38791 uint32_t t_l2_key_mask[14];
38792 /* Flow associated tunnel L3 header key info. */
38793 uint32_t t_l3_key_data[16];
38794 /* Flow associated tunnel L3 header mask info. */
38795 uint32_t t_l3_key_mask[16];
38796 /* Flow associated tunnel L4 header key info. */
38797 uint32_t t_l4_key_data[2];
38798 /* Flow associated tunnel L4 header mask info. */
38799 uint32_t t_l4_key_mask[2];
38800 /* Flow associated tunnel header info. */
38801 uint32_t tunnel_hdr[2];
38802 /* Flow associated L2 header key info. */
38803 uint32_t l2_key_data[14];
38804 /* Flow associated L2 header mask info. */
38805 uint32_t l2_key_mask[14];
38806 /* Flow associated L3 header key info. */
38807 uint32_t l3_key_data[16];
38808 /* Flow associated L3 header mask info. */
38809 uint32_t l3_key_mask[16];
38810 /* Flow associated L4 header key info. */
38811 uint32_t l4_key_data[2];
38812 /* Flow associated L4 header mask info. */
38813 uint32_t l4_key_mask[2];
38816 /**********************
38817 * hwrm_cfa_flow_info *
38818 **********************/
38821 /* hwrm_cfa_flow_info_input (size:256b/32B) */
38822 struct hwrm_cfa_flow_info_input {
38823 /* The HWRM command request type. */
38826 * The completion ring to send the completion event on. This should
38827 * be the NQ ID returned from the `nq_alloc` HWRM command.
38829 uint16_t cmpl_ring;
38831 * The sequence ID is used by the driver for tracking multiple
38832 * commands. This ID is treated as opaque data by the firmware and
38833 * the value is returned in the `hwrm_resp_hdr` upon completion.
38837 * The target ID of the command:
38838 * * 0x0-0xFFF8 - The function ID
38839 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
38840 * * 0xFFFD - Reserved for user-space HWRM interface
38843 uint16_t target_id;
38845 * A physical address pointer pointing to a host buffer that the
38846 * command's response data will be written. This can be either a host
38847 * physical address (HPA) or a guest physical address (GPA) and must
38848 * point to a physically contiguous block of memory.
38850 uint64_t resp_addr;
38851 /* Flow record index. */
38852 uint16_t flow_handle;
38853 /* Max flow handle */
38854 #define HWRM_CFA_FLOW_INFO_INPUT_FLOW_HANDLE_MAX_MASK \
38856 #define HWRM_CFA_FLOW_INFO_INPUT_FLOW_HANDLE_MAX_SFT 0
38857 /* CNP flow handle */
38858 #define HWRM_CFA_FLOW_INFO_INPUT_FLOW_HANDLE_CNP_CNT \
38860 /* RoCEv1 flow handle */
38861 #define HWRM_CFA_FLOW_INFO_INPUT_FLOW_HANDLE_ROCEV1_CNT \
38863 /* RoCEv2 flow handle */
38864 #define HWRM_CFA_FLOW_INFO_INPUT_FLOW_HANDLE_ROCEV2_CNT \
38866 /* Direction rx = 1 */
38867 #define HWRM_CFA_FLOW_INFO_INPUT_FLOW_HANDLE_DIR_RX \
38869 uint8_t unused_0[6];
38870 /* This value identifies a set of CFA data structures used for a flow. */
38871 uint64_t ext_flow_handle;
38874 /* hwrm_cfa_flow_info_output (size:5632b/704B) */
38875 struct hwrm_cfa_flow_info_output {
38876 /* The specific error status for the command. */
38877 uint16_t error_code;
38878 /* The HWRM command request type. */
38880 /* The sequence ID from the original command. */
38882 /* The length of the response data in number of bytes. */
38885 /* When set to 1, indicates the configuration is the TX flow. */
38886 #define HWRM_CFA_FLOW_INFO_OUTPUT_FLAGS_PATH_TX UINT32_C(0x1)
38887 /* When set to 1, indicates the configuration is the RX flow. */
38888 #define HWRM_CFA_FLOW_INFO_OUTPUT_FLAGS_PATH_RX UINT32_C(0x2)
38889 /* profile is 8 b */
38891 /* src_fid is 16 b */
38893 /* dst_fid is 16 b */
38895 /* l2_ctxt_id is 16 b */
38896 uint16_t l2_ctxt_id;
38897 /* em_info is 64 b */
38899 /* tcam_info is 64 b */
38900 uint64_t tcam_info;
38901 /* vfp_tcam_info is 64 b */
38902 uint64_t vfp_tcam_info;
38903 /* ar_id is 16 b */
38905 /* flow_handle is 16 b */
38906 uint16_t flow_handle;
38907 /* tunnel_handle is 32 b */
38908 uint32_t tunnel_handle;
38909 /* The flow aging timer for the flow, the unit is 100 milliseconds */
38910 uint16_t flow_timer;
38911 uint8_t unused_0[6];
38912 /* Flow associated L2, L3 and L4 headers info. */
38913 uint32_t flow_key_data[130];
38914 /* Flow associated action record info. */
38915 uint32_t flow_action_info[30];
38916 uint8_t unused_1[7];
38918 * This field is used in Output records to indicate that the output
38919 * is completely written to RAM. This field should be read as '1'
38920 * to indicate that the output has been completely written.
38921 * When writing a command completion or response to an internal
38922 * processor, the order of writes has to be such that this field is
38928 /***********************
38929 * hwrm_cfa_flow_flush *
38930 ***********************/
38933 /* hwrm_cfa_flow_flush_input (size:256b/32B) */
38934 struct hwrm_cfa_flow_flush_input {
38935 /* The HWRM command request type. */
38938 * The completion ring to send the completion event on. This should
38939 * be the NQ ID returned from the `nq_alloc` HWRM command.
38941 uint16_t cmpl_ring;
38943 * The sequence ID is used by the driver for tracking multiple
38944 * commands. This ID is treated as opaque data by the firmware and
38945 * the value is returned in the `hwrm_resp_hdr` upon completion.
38949 * The target ID of the command:
38950 * * 0x0-0xFFF8 - The function ID
38951 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
38952 * * 0xFFFD - Reserved for user-space HWRM interface
38955 uint16_t target_id;
38957 * A physical address pointer pointing to a host buffer that the
38958 * command's response data will be written. This can be either a host
38959 * physical address (HPA) or a guest physical address (GPA) and must
38960 * point to a physically contiguous block of memory.
38962 uint64_t resp_addr;
38963 /* flags is 32 b */
38966 * Set to 1 to indicate the page size, page layers, and
38967 * flow_handle_table_dma_addr fields are valid. The flow flush
38968 * operation should only flush the flows from the flow table
38969 * specified. This flag is set to 0 by older driver. For older
38970 * firmware, setting this flag has no effect.
38972 #define HWRM_CFA_FLOW_FLUSH_INPUT_FLAGS_FLOW_TABLE_VALID \
38975 * Set to 1 to indicate flow flush operation to cleanup all the
38976 * flows, meters, CFA context memory tables etc. This flag is set to
38977 * 0 by older driver. For older firmware, setting this flag has no
38980 #define HWRM_CFA_FLOW_FLUSH_INPUT_FLAGS_FLOW_RESET_ALL \
38983 * Set to 1 to indicate flow flush operation to cleanup all the
38984 * flows by the caller. This flag is set to 0 by older driver. For
38985 * older firmware, setting this flag has no effect.
38987 #define HWRM_CFA_FLOW_FLUSH_INPUT_FLAGS_FLOW_RESET_PORT \
38990 * Set to 1 to indicate the flow counter IDs are included in the
38993 #define HWRM_CFA_FLOW_FLUSH_INPUT_FLAGS_FLOW_HANDLE_INCL_FC \
38994 UINT32_C(0x8000000)
38996 * This specifies the size of flow handle entries provided by the
38997 * driver in the flow table specified below. Only two flow handle
38998 * size enums are defined.
39000 #define HWRM_CFA_FLOW_FLUSH_INPUT_FLAGS_FLOW_HANDLE_ENTRY_SIZE_MASK \
39001 UINT32_C(0xc0000000)
39002 #define HWRM_CFA_FLOW_FLUSH_INPUT_FLAGS_FLOW_HANDLE_ENTRY_SIZE_SFT \
39004 /* The flow handle is 16bit */
39005 #define HWRM_CFA_FLOW_FLUSH_INPUT_FLAGS_FLOW_HANDLE_ENTRY_SIZE_FLOW_HND_16BIT \
39006 (UINT32_C(0x0) << 30)
39007 /* The flow handle is 64bit */
39008 #define HWRM_CFA_FLOW_FLUSH_INPUT_FLAGS_FLOW_HANDLE_ENTRY_SIZE_FLOW_HND_64BIT \
39009 (UINT32_C(0x1) << 30)
39010 #define HWRM_CFA_FLOW_FLUSH_INPUT_FLAGS_FLOW_HANDLE_ENTRY_SIZE_LAST \
39011 HWRM_CFA_FLOW_FLUSH_INPUT_FLAGS_FLOW_HANDLE_ENTRY_SIZE_FLOW_HND_64BIT
39012 /* Specify page size of the flow table memory. */
39014 /* The page size is 4K */
39015 #define HWRM_CFA_FLOW_FLUSH_INPUT_PAGE_SIZE_4K UINT32_C(0x0)
39016 /* The page size is 8K */
39017 #define HWRM_CFA_FLOW_FLUSH_INPUT_PAGE_SIZE_8K UINT32_C(0x1)
39018 /* The page size is 64K */
39019 #define HWRM_CFA_FLOW_FLUSH_INPUT_PAGE_SIZE_64K UINT32_C(0x4)
39020 /* The page size is 256K */
39021 #define HWRM_CFA_FLOW_FLUSH_INPUT_PAGE_SIZE_256K UINT32_C(0x6)
39022 /* The page size is 1M */
39023 #define HWRM_CFA_FLOW_FLUSH_INPUT_PAGE_SIZE_1M UINT32_C(0x8)
39024 /* The page size is 2M */
39025 #define HWRM_CFA_FLOW_FLUSH_INPUT_PAGE_SIZE_2M UINT32_C(0x9)
39026 /* The page size is 4M */
39027 #define HWRM_CFA_FLOW_FLUSH_INPUT_PAGE_SIZE_4M UINT32_C(0xa)
39028 /* The page size is 1G */
39029 #define HWRM_CFA_FLOW_FLUSH_INPUT_PAGE_SIZE_1G UINT32_C(0x12)
39030 #define HWRM_CFA_FLOW_FLUSH_INPUT_PAGE_SIZE_LAST \
39031 HWRM_CFA_FLOW_FLUSH_INPUT_PAGE_SIZE_1G
39032 /* FLow table memory indirect levels. */
39033 uint8_t page_level;
39034 /* PBL pointer is physical start address. */
39035 #define HWRM_CFA_FLOW_FLUSH_INPUT_PAGE_LEVEL_LVL_0 UINT32_C(0x0)
39036 /* PBL pointer points to PTE table. */
39037 #define HWRM_CFA_FLOW_FLUSH_INPUT_PAGE_LEVEL_LVL_1 UINT32_C(0x1)
39039 * PBL pointer points to PDE table with each entry pointing to PTE
39042 #define HWRM_CFA_FLOW_FLUSH_INPUT_PAGE_LEVEL_LVL_2 UINT32_C(0x2)
39043 #define HWRM_CFA_FLOW_FLUSH_INPUT_PAGE_LEVEL_LAST \
39044 HWRM_CFA_FLOW_FLUSH_INPUT_PAGE_LEVEL_LVL_2
39045 /* number of flows in the flow table */
39046 uint16_t num_flows;
39047 /* Pointer to the PBL, or PDL depending on number of levels */
39051 /* hwrm_cfa_flow_flush_output (size:128b/16B) */
39052 struct hwrm_cfa_flow_flush_output {
39053 /* The specific error status for the command. */
39054 uint16_t error_code;
39055 /* The HWRM command request type. */
39057 /* The sequence ID from the original command. */
39059 /* The length of the response data in number of bytes. */
39061 uint8_t unused_0[7];
39063 * This field is used in Output records to indicate that the output
39064 * is completely written to RAM. This field should be read as '1'
39065 * to indicate that the output has been completely written.
39066 * When writing a command completion or response to an internal
39067 * processor, the order of writes has to be such that this field is
39073 /***********************
39074 * hwrm_cfa_flow_stats *
39075 ***********************/
39078 /* hwrm_cfa_flow_stats_input (size:640b/80B) */
39079 struct hwrm_cfa_flow_stats_input {
39080 /* The HWRM command request type. */
39083 * The completion ring to send the completion event on. This should
39084 * be the NQ ID returned from the `nq_alloc` HWRM command.
39086 uint16_t cmpl_ring;
39088 * The sequence ID is used by the driver for tracking multiple
39089 * commands. This ID is treated as opaque data by the firmware and
39090 * the value is returned in the `hwrm_resp_hdr` upon completion.
39094 * The target ID of the command:
39095 * * 0x0-0xFFF8 - The function ID
39096 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
39097 * * 0xFFFD - Reserved for user-space HWRM interface
39100 uint16_t target_id;
39102 * A physical address pointer pointing to a host buffer that the
39103 * command's response data will be written. This can be either a host
39104 * physical address (HPA) or a guest physical address (GPA) and must
39105 * point to a physically contiguous block of memory.
39107 uint64_t resp_addr;
39109 uint16_t num_flows;
39111 uint16_t flow_handle_0;
39113 uint16_t flow_handle_1;
39115 uint16_t flow_handle_2;
39117 uint16_t flow_handle_3;
39119 uint16_t flow_handle_4;
39121 uint16_t flow_handle_5;
39123 uint16_t flow_handle_6;
39125 uint16_t flow_handle_7;
39127 uint16_t flow_handle_8;
39129 uint16_t flow_handle_9;
39130 uint8_t unused_0[2];
39131 /* Flow ID of a flow. */
39132 uint32_t flow_id_0;
39133 /* Flow ID of a flow. */
39134 uint32_t flow_id_1;
39135 /* Flow ID of a flow. */
39136 uint32_t flow_id_2;
39137 /* Flow ID of a flow. */
39138 uint32_t flow_id_3;
39139 /* Flow ID of a flow. */
39140 uint32_t flow_id_4;
39141 /* Flow ID of a flow. */
39142 uint32_t flow_id_5;
39143 /* Flow ID of a flow. */
39144 uint32_t flow_id_6;
39145 /* Flow ID of a flow. */
39146 uint32_t flow_id_7;
39147 /* Flow ID of a flow. */
39148 uint32_t flow_id_8;
39149 /* Flow ID of a flow. */
39150 uint32_t flow_id_9;
39153 /* hwrm_cfa_flow_stats_output (size:1408b/176B) */
39154 struct hwrm_cfa_flow_stats_output {
39155 /* The specific error status for the command. */
39156 uint16_t error_code;
39157 /* The HWRM command request type. */
39159 /* The sequence ID from the original command. */
39161 /* The length of the response data in number of bytes. */
39163 /* packet_0 is 64 b */
39165 /* packet_1 is 64 b */
39167 /* packet_2 is 64 b */
39169 /* packet_3 is 64 b */
39171 /* packet_4 is 64 b */
39173 /* packet_5 is 64 b */
39175 /* packet_6 is 64 b */
39177 /* packet_7 is 64 b */
39179 /* packet_8 is 64 b */
39181 /* packet_9 is 64 b */
39183 /* byte_0 is 64 b */
39185 /* byte_1 is 64 b */
39187 /* byte_2 is 64 b */
39189 /* byte_3 is 64 b */
39191 /* byte_4 is 64 b */
39193 /* byte_5 is 64 b */
39195 /* byte_6 is 64 b */
39197 /* byte_7 is 64 b */
39199 /* byte_8 is 64 b */
39201 /* byte_9 is 64 b */
39203 uint8_t unused_0[7];
39205 * This field is used in Output records to indicate that the output
39206 * is completely written to RAM. This field should be read as '1'
39207 * to indicate that the output has been completely written.
39208 * When writing a command completion or response to an internal
39209 * processor, the order of writes has to be such that this field is
39215 /***********************************
39216 * hwrm_cfa_flow_aging_timer_reset *
39217 ***********************************/
39220 /* hwrm_cfa_flow_aging_timer_reset_input (size:256b/32B) */
39221 struct hwrm_cfa_flow_aging_timer_reset_input {
39222 /* The HWRM command request type. */
39225 * The completion ring to send the completion event on. This should
39226 * be the NQ ID returned from the `nq_alloc` HWRM command.
39228 uint16_t cmpl_ring;
39230 * The sequence ID is used by the driver for tracking multiple
39231 * commands. This ID is treated as opaque data by the firmware and
39232 * the value is returned in the `hwrm_resp_hdr` upon completion.
39236 * The target ID of the command:
39237 * * 0x0-0xFFF8 - The function ID
39238 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
39239 * * 0xFFFD - Reserved for user-space HWRM interface
39242 uint16_t target_id;
39244 * A physical address pointer pointing to a host buffer that the
39245 * command's response data will be written. This can be either a host
39246 * physical address (HPA) or a guest physical address (GPA) and must
39247 * point to a physically contiguous block of memory.
39249 uint64_t resp_addr;
39250 /* Flow record index. */
39251 uint16_t flow_handle;
39252 uint8_t unused_0[2];
39254 * New flow timer value for the flow specified in the ext_flow_handle.
39255 * The flow timer unit is 100ms.
39257 uint32_t flow_timer;
39258 /* This value identifies a set of CFA data structures used for a flow. */
39259 uint64_t ext_flow_handle;
39262 /* hwrm_cfa_flow_aging_timer_reset_output (size:128b/16B) */
39263 struct hwrm_cfa_flow_aging_timer_reset_output {
39264 /* The specific error status for the command. */
39265 uint16_t error_code;
39266 /* The HWRM command request type. */
39268 /* The sequence ID from the original command. */
39270 /* The length of the response data in number of bytes. */
39272 uint8_t unused_0[7];
39274 * This field is used in Output records to indicate that the output
39275 * is completely written to RAM. This field should be read as '1'
39276 * to indicate that the output has been completely written.
39277 * When writing a command completion or response to an internal
39278 * processor, the order of writes has to be such that this field is
39284 /***************************
39285 * hwrm_cfa_flow_aging_cfg *
39286 ***************************/
39289 /* hwrm_cfa_flow_aging_cfg_input (size:384b/48B) */
39290 struct hwrm_cfa_flow_aging_cfg_input {
39291 /* The HWRM command request type. */
39294 * The completion ring to send the completion event on. This should
39295 * be the NQ ID returned from the `nq_alloc` HWRM command.
39297 uint16_t cmpl_ring;
39299 * The sequence ID is used by the driver for tracking multiple
39300 * commands. This ID is treated as opaque data by the firmware and
39301 * the value is returned in the `hwrm_resp_hdr` upon completion.
39305 * The target ID of the command:
39306 * * 0x0-0xFFF8 - The function ID
39307 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
39308 * * 0xFFFD - Reserved for user-space HWRM interface
39311 uint16_t target_id;
39313 * A physical address pointer pointing to a host buffer that the
39314 * command's response data will be written. This can be either a host
39315 * physical address (HPA) or a guest physical address (GPA) and must
39316 * point to a physically contiguous block of memory.
39318 uint64_t resp_addr;
39319 /* The bit field to enable per flow aging configuration. */
39322 * This bit must be '1' for the tcp flow timer field to be
39325 #define HWRM_CFA_FLOW_AGING_CFG_INPUT_ENABLES_TCP_FLOW_TIMER \
39328 * This bit must be '1' for the tcp finish timer field to be
39331 #define HWRM_CFA_FLOW_AGING_CFG_INPUT_ENABLES_TCP_FIN_TIMER \
39334 * This bit must be '1' for the udp flow timer field to be
39337 #define HWRM_CFA_FLOW_AGING_CFG_INPUT_ENABLES_UDP_FLOW_TIMER \
39340 * This bit must be '1' for the eem dma interval field to be
39343 #define HWRM_CFA_FLOW_AGING_CFG_INPUT_ENABLES_EEM_DMA_INTERVAL \
39346 * This bit must be '1' for the eem notice interval field to be
39349 #define HWRM_CFA_FLOW_AGING_CFG_INPUT_ENABLES_EEM_NOTICE_INTERVAL \
39352 * This bit must be '1' for the eem context memory maximum entries
39353 * field to be configured
39355 #define HWRM_CFA_FLOW_AGING_CFG_INPUT_ENABLES_EEM_CTX_MAX_ENTRIES \
39358 * This bit must be '1' for the eem context memory ID field to be
39361 #define HWRM_CFA_FLOW_AGING_CFG_INPUT_ENABLES_EEM_CTX_ID \
39364 * This bit must be '1' for the eem context memory type field to be
39367 #define HWRM_CFA_FLOW_AGING_CFG_INPUT_ENABLES_EEM_CTX_MEM_TYPE \
39370 /* Enumeration denoting the RX, TX type of the resource. */
39371 #define HWRM_CFA_FLOW_AGING_CFG_INPUT_FLAGS_PATH UINT32_C(0x1)
39373 #define HWRM_CFA_FLOW_AGING_CFG_INPUT_FLAGS_PATH_TX UINT32_C(0x0)
39375 #define HWRM_CFA_FLOW_AGING_CFG_INPUT_FLAGS_PATH_RX UINT32_C(0x1)
39376 #define HWRM_CFA_FLOW_AGING_CFG_INPUT_FLAGS_PATH_LAST \
39377 HWRM_CFA_FLOW_AGING_CFG_INPUT_FLAGS_PATH_RX
39379 * Enumeration denoting the enable, disable eem flow aging
39382 #define HWRM_CFA_FLOW_AGING_CFG_INPUT_FLAGS_EEM UINT32_C(0x2)
39384 #define HWRM_CFA_FLOW_AGING_CFG_INPUT_FLAGS_EEM_DISABLE \
39385 (UINT32_C(0x0) << 1)
39387 #define HWRM_CFA_FLOW_AGING_CFG_INPUT_FLAGS_EEM_ENABLE \
39388 (UINT32_C(0x1) << 1)
39389 #define HWRM_CFA_FLOW_AGING_CFG_INPUT_FLAGS_EEM_LAST \
39390 HWRM_CFA_FLOW_AGING_CFG_INPUT_FLAGS_EEM_ENABLE
39393 * The flow aging timer for all TCP flows, the unit is 100
39396 uint32_t tcp_flow_timer;
39398 * The TCP finished timer for all TCP flows, the unit is 100
39401 uint32_t tcp_fin_timer;
39403 * The flow aging timer for all UDP flows, the unit is 100
39406 uint32_t udp_flow_timer;
39408 * The interval to dma eem ejection data to host memory, the unit is
39411 uint16_t eem_dma_interval;
39413 * The interval to notify driver to read the eem ejection data, the
39414 * unit is milliseconds.
39416 uint16_t eem_notice_interval;
39417 /* The maximum entries number in the eem context memory. */
39418 uint32_t eem_ctx_max_entries;
39419 /* The context memory ID for eem flow aging. */
39420 uint16_t eem_ctx_id;
39421 uint16_t eem_ctx_mem_type;
39423 * The content of context memory is eem ejection data, the size of
39424 * each entry is 4 bytes.
39426 #define HWRM_CFA_FLOW_AGING_CFG_INPUT_EEM_CTX_MEM_TYPE_EJECTION_DATA \
39428 #define HWRM_CFA_FLOW_AGING_CFG_INPUT_EEM_CTX_MEM_TYPE_LAST \
39429 HWRM_CFA_FLOW_AGING_CFG_INPUT_EEM_CTX_MEM_TYPE_EJECTION_DATA
39430 uint8_t unused_1[4];
39433 /* hwrm_cfa_flow_aging_cfg_output (size:128b/16B) */
39434 struct hwrm_cfa_flow_aging_cfg_output {
39435 /* The specific error status for the command. */
39436 uint16_t error_code;
39437 /* The HWRM command request type. */
39439 /* The sequence ID from the original command. */
39441 /* The length of the response data in number of bytes. */
39443 uint8_t unused_0[7];
39445 * This field is used in Output records to indicate that the output
39446 * is completely written to RAM. This field should be read as '1'
39447 * to indicate that the output has been completely written.
39448 * When writing a command completion or response to an internal
39449 * processor, the order of writes has to be such that this field is
39455 /****************************
39456 * hwrm_cfa_flow_aging_qcfg *
39457 ****************************/
39460 /* hwrm_cfa_flow_aging_qcfg_input (size:192b/24B) */
39461 struct hwrm_cfa_flow_aging_qcfg_input {
39462 /* The HWRM command request type. */
39465 * The completion ring to send the completion event on. This should
39466 * be the NQ ID returned from the `nq_alloc` HWRM command.
39468 uint16_t cmpl_ring;
39470 * The sequence ID is used by the driver for tracking multiple
39471 * commands. This ID is treated as opaque data by the firmware and
39472 * the value is returned in the `hwrm_resp_hdr` upon completion.
39476 * The target ID of the command:
39477 * * 0x0-0xFFF8 - The function ID
39478 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
39479 * * 0xFFFD - Reserved for user-space HWRM interface
39482 uint16_t target_id;
39484 * A physical address pointer pointing to a host buffer that the
39485 * command's response data will be written. This can be either a host
39486 * physical address (HPA) or a guest physical address (GPA) and must
39487 * point to a physically contiguous block of memory.
39489 uint64_t resp_addr;
39491 * The direction for the flow aging configuration, 1 is rx path, 2 is
39495 /* Enumeration denoting the RX, TX type of the resource. */
39496 #define HWRM_CFA_FLOW_AGING_QCFG_INPUT_FLAGS_PATH UINT32_C(0x1)
39498 #define HWRM_CFA_FLOW_AGING_QCFG_INPUT_FLAGS_PATH_TX UINT32_C(0x0)
39500 #define HWRM_CFA_FLOW_AGING_QCFG_INPUT_FLAGS_PATH_RX UINT32_C(0x1)
39501 #define HWRM_CFA_FLOW_AGING_QCFG_INPUT_FLAGS_PATH_LAST \
39502 HWRM_CFA_FLOW_AGING_QCFG_INPUT_FLAGS_PATH_RX
39503 uint8_t unused_0[7];
39506 /* hwrm_cfa_flow_aging_qcfg_output (size:320b/40B) */
39507 struct hwrm_cfa_flow_aging_qcfg_output {
39508 /* The specific error status for the command. */
39509 uint16_t error_code;
39510 /* The HWRM command request type. */
39512 /* The sequence ID from the original command. */
39514 /* The length of the response data in number of bytes. */
39517 * The current flow aging timer for all TCP flows, the unit is 100
39520 uint32_t tcp_flow_timer;
39522 * The current TCP finished timer for all TCP flows, the unit is 100
39525 uint32_t tcp_fin_timer;
39527 * The current flow aging timer for all UDP flows, the unit is 100
39530 uint32_t udp_flow_timer;
39532 * The interval to dma eem ejection data to host memory, the unit is
39535 uint16_t eem_dma_interval;
39537 * The interval to notify driver to read the eem ejection data, the
39538 * unit is milliseconds.
39540 uint16_t eem_notice_interval;
39541 /* The maximum entries number in the eem context memory. */
39542 uint32_t eem_ctx_max_entries;
39543 /* The context memory ID for eem flow aging. */
39544 uint16_t eem_ctx_id;
39545 /* The context memory type for eem flow aging. */
39546 uint16_t eem_ctx_mem_type;
39547 uint8_t unused_0[7];
39549 * This field is used in Output records to indicate that the output
39550 * is completely written to RAM. This field should be read as '1'
39551 * to indicate that the output has been completely written.
39552 * When writing a command completion or response to an internal
39553 * processor, the order of writes has to be such that this field is
39559 /*****************************
39560 * hwrm_cfa_flow_aging_qcaps *
39561 *****************************/
39564 /* hwrm_cfa_flow_aging_qcaps_input (size:192b/24B) */
39565 struct hwrm_cfa_flow_aging_qcaps_input {
39566 /* The HWRM command request type. */
39569 * The completion ring to send the completion event on. This should
39570 * be the NQ ID returned from the `nq_alloc` HWRM command.
39572 uint16_t cmpl_ring;
39574 * The sequence ID is used by the driver for tracking multiple
39575 * commands. This ID is treated as opaque data by the firmware and
39576 * the value is returned in the `hwrm_resp_hdr` upon completion.
39580 * The target ID of the command:
39581 * * 0x0-0xFFF8 - The function ID
39582 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
39583 * * 0xFFFD - Reserved for user-space HWRM interface
39586 uint16_t target_id;
39588 * A physical address pointer pointing to a host buffer that the
39589 * command's response data will be written. This can be either a host
39590 * physical address (HPA) or a guest physical address (GPA) and must
39591 * point to a physically contiguous block of memory.
39593 uint64_t resp_addr;
39595 * The direction for the flow aging configuration, 1 is rx path, 2 is
39599 /* Enumeration denoting the RX, TX type of the resource. */
39600 #define HWRM_CFA_FLOW_AGING_QCAPS_INPUT_FLAGS_PATH UINT32_C(0x1)
39602 #define HWRM_CFA_FLOW_AGING_QCAPS_INPUT_FLAGS_PATH_TX UINT32_C(0x0)
39604 #define HWRM_CFA_FLOW_AGING_QCAPS_INPUT_FLAGS_PATH_RX UINT32_C(0x1)
39605 #define HWRM_CFA_FLOW_AGING_QCAPS_INPUT_FLAGS_PATH_LAST \
39606 HWRM_CFA_FLOW_AGING_QCAPS_INPUT_FLAGS_PATH_RX
39607 uint8_t unused_0[7];
39610 /* hwrm_cfa_flow_aging_qcaps_output (size:256b/32B) */
39611 struct hwrm_cfa_flow_aging_qcaps_output {
39612 /* The specific error status for the command. */
39613 uint16_t error_code;
39614 /* The HWRM command request type. */
39616 /* The sequence ID from the original command. */
39618 /* The length of the response data in number of bytes. */
39621 * The maximum flow aging timer for all TCP flows, the unit is 100
39624 uint32_t max_tcp_flow_timer;
39626 * The maximum TCP finished timer for all TCP flows, the unit is 100
39629 uint32_t max_tcp_fin_timer;
39631 * The maximum flow aging timer for all UDP flows, the unit is 100
39634 uint32_t max_udp_flow_timer;
39635 /* The maximum aging flows that HW can support. */
39636 uint32_t max_aging_flows;
39637 uint8_t unused_0[7];
39639 * This field is used in Output records to indicate that the output
39640 * is completely written to RAM. This field should be read as '1'
39641 * to indicate that the output has been completely written.
39642 * When writing a command completion or response to an internal
39643 * processor, the order of writes has to be such that this field is
39649 /**********************************
39650 * hwrm_cfa_tcp_flag_process_qcfg *
39651 **********************************/
39654 /* hwrm_cfa_tcp_flag_process_qcfg_input (size:128b/16B) */
39655 struct hwrm_cfa_tcp_flag_process_qcfg_input {
39656 /* The HWRM command request type. */
39659 * The completion ring to send the completion event on. This should
39660 * be the NQ ID returned from the `nq_alloc` HWRM command.
39662 uint16_t cmpl_ring;
39664 * The sequence ID is used by the driver for tracking multiple
39665 * commands. This ID is treated as opaque data by the firmware and
39666 * the value is returned in the `hwrm_resp_hdr` upon completion.
39670 * The target ID of the command:
39671 * * 0x0-0xFFF8 - The function ID
39672 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
39673 * * 0xFFFD - Reserved for user-space HWRM interface
39676 uint16_t target_id;
39678 * A physical address pointer pointing to a host buffer that the
39679 * command's response data will be written. This can be either a host
39680 * physical address (HPA) or a guest physical address (GPA) and must
39681 * point to a physically contiguous block of memory.
39683 uint64_t resp_addr;
39686 /* hwrm_cfa_tcp_flag_process_qcfg_output (size:192b/24B) */
39687 struct hwrm_cfa_tcp_flag_process_qcfg_output {
39688 /* The specific error status for the command. */
39689 uint16_t error_code;
39690 /* The HWRM command request type. */
39692 /* The sequence ID from the original command. */
39694 /* The length of the response data in number of bytes. */
39696 /* The port 0 RX mirror action record ID. */
39697 uint16_t rx_ar_id_port0;
39698 /* The port 1 RX mirror action record ID. */
39699 uint16_t rx_ar_id_port1;
39701 * The port 0 RX action record ID for TX TCP flag packets from
39704 uint16_t tx_ar_id_port0;
39706 * The port 1 RX action record ID for TX TCP flag packets from
39709 uint16_t tx_ar_id_port1;
39710 uint8_t unused_0[7];
39712 * This field is used in Output records to indicate that the output
39713 * is completely written to RAM. This field should be read as '1'
39714 * to indicate that the output has been completely written.
39715 * When writing a command completion or response to an internal
39716 * processor, the order of writes has to be such that this field is
39722 /**************************
39723 * hwrm_cfa_vf_pair_alloc *
39724 **************************/
39727 /* hwrm_cfa_vf_pair_alloc_input (size:448b/56B) */
39728 struct hwrm_cfa_vf_pair_alloc_input {
39729 /* The HWRM command request type. */
39732 * The completion ring to send the completion event on. This should
39733 * be the NQ ID returned from the `nq_alloc` HWRM command.
39735 uint16_t cmpl_ring;
39737 * The sequence ID is used by the driver for tracking multiple
39738 * commands. This ID is treated as opaque data by the firmware and
39739 * the value is returned in the `hwrm_resp_hdr` upon completion.
39743 * The target ID of the command:
39744 * * 0x0-0xFFF8 - The function ID
39745 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
39746 * * 0xFFFD - Reserved for user-space HWRM interface
39749 uint16_t target_id;
39751 * A physical address pointer pointing to a host buffer that the
39752 * command's response data will be written. This can be either a host
39753 * physical address (HPA) or a guest physical address (GPA) and must
39754 * point to a physically contiguous block of memory.
39756 uint64_t resp_addr;
39757 /* Logical VF number (range: 0 -> MAX_VFS -1). */
39759 /* Logical VF number (range: 0 -> MAX_VFS -1). */
39761 uint8_t unused_0[4];
39762 /* VF Pair name (32 byte string). */
39763 char pair_name[32];
39766 /* hwrm_cfa_vf_pair_alloc_output (size:128b/16B) */
39767 struct hwrm_cfa_vf_pair_alloc_output {
39768 /* The specific error status for the command. */
39769 uint16_t error_code;
39770 /* The HWRM command request type. */
39772 /* The sequence ID from the original command. */
39774 /* The length of the response data in number of bytes. */
39776 uint8_t unused_0[7];
39778 * This field is used in Output records to indicate that the output
39779 * is completely written to RAM. This field should be read as '1'
39780 * to indicate that the output has been completely written.
39781 * When writing a command completion or response to an internal
39782 * processor, the order of writes has to be such that this field is
39788 /*************************
39789 * hwrm_cfa_vf_pair_free *
39790 *************************/
39793 /* hwrm_cfa_vf_pair_free_input (size:384b/48B) */
39794 struct hwrm_cfa_vf_pair_free_input {
39795 /* The HWRM command request type. */
39798 * The completion ring to send the completion event on. This should
39799 * be the NQ ID returned from the `nq_alloc` HWRM command.
39801 uint16_t cmpl_ring;
39803 * The sequence ID is used by the driver for tracking multiple
39804 * commands. This ID is treated as opaque data by the firmware and
39805 * the value is returned in the `hwrm_resp_hdr` upon completion.
39809 * The target ID of the command:
39810 * * 0x0-0xFFF8 - The function ID
39811 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
39812 * * 0xFFFD - Reserved for user-space HWRM interface
39815 uint16_t target_id;
39817 * A physical address pointer pointing to a host buffer that the
39818 * command's response data will be written. This can be either a host
39819 * physical address (HPA) or a guest physical address (GPA) and must
39820 * point to a physically contiguous block of memory.
39822 uint64_t resp_addr;
39823 /* VF Pair name (32 byte string). */
39824 char pair_name[32];
39827 /* hwrm_cfa_vf_pair_free_output (size:128b/16B) */
39828 struct hwrm_cfa_vf_pair_free_output {
39829 /* The specific error status for the command. */
39830 uint16_t error_code;
39831 /* The HWRM command request type. */
39833 /* The sequence ID from the original command. */
39835 /* The length of the response data in number of bytes. */
39837 uint8_t unused_0[7];
39839 * This field is used in Output records to indicate that the output
39840 * is completely written to RAM. This field should be read as '1'
39841 * to indicate that the output has been completely written.
39842 * When writing a command completion or response to an internal
39843 * processor, the order of writes has to be such that this field is
39849 /*************************
39850 * hwrm_cfa_vf_pair_info *
39851 *************************/
39854 /* hwrm_cfa_vf_pair_info_input (size:448b/56B) */
39855 struct hwrm_cfa_vf_pair_info_input {
39856 /* The HWRM command request type. */
39859 * The completion ring to send the completion event on. This should
39860 * be the NQ ID returned from the `nq_alloc` HWRM command.
39862 uint16_t cmpl_ring;
39864 * The sequence ID is used by the driver for tracking multiple
39865 * commands. This ID is treated as opaque data by the firmware and
39866 * the value is returned in the `hwrm_resp_hdr` upon completion.
39870 * The target ID of the command:
39871 * * 0x0-0xFFF8 - The function ID
39872 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
39873 * * 0xFFFD - Reserved for user-space HWRM interface
39876 uint16_t target_id;
39878 * A physical address pointer pointing to a host buffer that the
39879 * command's response data will be written. This can be either a host
39880 * physical address (HPA) or a guest physical address (GPA) and must
39881 * point to a physically contiguous block of memory.
39883 uint64_t resp_addr;
39885 /* If this flag is set, lookup by name else lookup by index. */
39886 #define HWRM_CFA_VF_PAIR_INFO_INPUT_FLAGS_LOOKUP_TYPE UINT32_C(0x1)
39887 /* vf pair table index. */
39888 uint16_t vf_pair_index;
39889 uint8_t unused_0[2];
39890 /* VF Pair name (32 byte string). */
39891 char vf_pair_name[32];
39894 /* hwrm_cfa_vf_pair_info_output (size:512b/64B) */
39895 struct hwrm_cfa_vf_pair_info_output {
39896 /* The specific error status for the command. */
39897 uint16_t error_code;
39898 /* The HWRM command request type. */
39900 /* The sequence ID from the original command. */
39902 /* The length of the response data in number of bytes. */
39904 /* vf pair table index. */
39905 uint16_t next_vf_pair_index;
39906 /* vf pair member a's vf_fid. */
39908 /* vf pair member a's Linux logical VF number. */
39909 uint16_t vf_a_index;
39910 /* vf pair member b's vf_fid. */
39912 /* vf pair member a's Linux logical VF number. */
39913 uint16_t vf_b_index;
39914 /* vf pair state. */
39915 uint8_t pair_state;
39916 /* Pair has been allocated */
39917 #define HWRM_CFA_VF_PAIR_INFO_OUTPUT_PAIR_STATE_ALLOCATED UINT32_C(0x1)
39918 /* Both pair members are active */
39919 #define HWRM_CFA_VF_PAIR_INFO_OUTPUT_PAIR_STATE_ACTIVE UINT32_C(0x2)
39920 #define HWRM_CFA_VF_PAIR_INFO_OUTPUT_PAIR_STATE_LAST \
39921 HWRM_CFA_VF_PAIR_INFO_OUTPUT_PAIR_STATE_ACTIVE
39922 uint8_t unused_0[5];
39923 /* VF Pair name (32 byte string). */
39924 char pair_name[32];
39925 uint8_t unused_1[7];
39927 * This field is used in Output records to indicate that the output
39928 * is completely written to RAM. This field should be read as '1'
39929 * to indicate that the output has been completely written.
39930 * When writing a command completion or response to an internal
39931 * processor, the order of writes has to be such that this field is
39937 /***********************
39938 * hwrm_cfa_pair_alloc *
39939 ***********************/
39942 /* hwrm_cfa_pair_alloc_input (size:576b/72B) */
39943 struct hwrm_cfa_pair_alloc_input {
39944 /* The HWRM command request type. */
39947 * The completion ring to send the completion event on. This should
39948 * be the NQ ID returned from the `nq_alloc` HWRM command.
39950 uint16_t cmpl_ring;
39952 * The sequence ID is used by the driver for tracking multiple
39953 * commands. This ID is treated as opaque data by the firmware and
39954 * the value is returned in the `hwrm_resp_hdr` upon completion.
39958 * The target ID of the command:
39959 * * 0x0-0xFFF8 - The function ID
39960 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
39961 * * 0xFFFD - Reserved for user-space HWRM interface
39964 uint16_t target_id;
39966 * A physical address pointer pointing to a host buffer that the
39967 * command's response data will be written. This can be either a host
39968 * physical address (HPA) or a guest physical address (GPA) and must
39969 * point to a physically contiguous block of memory.
39971 uint64_t resp_addr;
39973 * Pair mode (0-vf2fn, 1-rep2fn, 2-rep2rep, 3-proxy, 4-pfpair,
39974 * 5-rep2fn_mod, 6-rep2fn_modall, 7-rep2fn_truflow).
39976 uint16_t pair_mode;
39977 /* Pair between VF on local host with PF or VF on specified host. */
39978 #define HWRM_CFA_PAIR_ALLOC_INPUT_PAIR_MODE_VF2FN \
39980 /* Pair between REP on local host with PF or VF on specified host. */
39981 #define HWRM_CFA_PAIR_ALLOC_INPUT_PAIR_MODE_REP2FN \
39983 /* Pair between REP on local host with REP on specified host. */
39984 #define HWRM_CFA_PAIR_ALLOC_INPUT_PAIR_MODE_REP2REP \
39986 /* Pair for the proxy interface. */
39987 #define HWRM_CFA_PAIR_ALLOC_INPUT_PAIR_MODE_PROXY \
39989 /* Pair for the PF interface. */
39990 #define HWRM_CFA_PAIR_ALLOC_INPUT_PAIR_MODE_PFPAIR \
39992 /* Modify existing rep2fn pair and move pair to new PF. */
39993 #define HWRM_CFA_PAIR_ALLOC_INPUT_PAIR_MODE_REP2FN_MOD \
39996 * Modify existing rep2fn pairs paired with same PF and move pairs
39999 #define HWRM_CFA_PAIR_ALLOC_INPUT_PAIR_MODE_REP2FN_MODALL \
40002 * Truflow pair between REP on local host with PF or VF on specified
40005 #define HWRM_CFA_PAIR_ALLOC_INPUT_PAIR_MODE_REP2FN_TRUFLOW \
40007 #define HWRM_CFA_PAIR_ALLOC_INPUT_PAIR_MODE_LAST \
40008 HWRM_CFA_PAIR_ALLOC_INPUT_PAIR_MODE_REP2FN_TRUFLOW
40009 /* Logical VF number (range: 0 -> MAX_VFS -1). */
40011 /* Logical Host (0xff-local host). */
40013 /* Logical PF (0xff-PF for command channel). */
40015 /* Logical VF number (range: 0 -> MAX_VFS -1). */
40017 /* Loopback port (0xff-internal loopback), valid for mode-3. */
40019 /* Priority used for encap of loopback packets valid for mode-3. */
40021 /* New PF for rep2fn modify, valid for mode 5. */
40022 uint16_t new_pf_fid;
40025 * This bit must be '1' for the q_ab field to be
40028 #define HWRM_CFA_PAIR_ALLOC_INPUT_ENABLES_Q_AB_VALID UINT32_C(0x1)
40030 * This bit must be '1' for the q_ba field to be
40033 #define HWRM_CFA_PAIR_ALLOC_INPUT_ENABLES_Q_BA_VALID UINT32_C(0x2)
40035 * This bit must be '1' for the fc_ab field to be
40038 #define HWRM_CFA_PAIR_ALLOC_INPUT_ENABLES_FC_AB_VALID UINT32_C(0x4)
40040 * This bit must be '1' for the fc_ba field to be
40043 #define HWRM_CFA_PAIR_ALLOC_INPUT_ENABLES_FC_BA_VALID UINT32_C(0x8)
40044 /* VF Pair name (32 byte string). */
40045 char pair_name[32];
40047 * The q_ab value specifies the logical index of the TX/RX CoS
40048 * queue to be assigned for traffic in the A to B direction of
40049 * the interface pair. The default value is 0.
40053 * The q_ba value specifies the logical index of the TX/RX CoS
40054 * queue to be assigned for traffic in the B to A direction of
40055 * the interface pair. The default value is 1.
40059 * Specifies whether RX ring flow control is disabled (0) or enabled
40060 * (1) in the A to B direction. The default value is 0, meaning that
40061 * packets will be dropped when the B-side RX rings are full.
40065 * Specifies whether RX ring flow control is disabled (0) or enabled
40066 * (1) in the B to A direction. The default value is 1, meaning that
40067 * the RX CoS queue will be flow controlled when the A-side RX rings
40071 uint8_t unused_1[4];
40074 /* hwrm_cfa_pair_alloc_output (size:192b/24B) */
40075 struct hwrm_cfa_pair_alloc_output {
40076 /* The specific error status for the command. */
40077 uint16_t error_code;
40078 /* The HWRM command request type. */
40080 /* The sequence ID from the original command. */
40082 /* The length of the response data in number of bytes. */
40084 /* Only valid for modes 1 and 2. */
40085 uint16_t rx_cfa_code_a;
40086 /* Only valid for modes 1 and 2. */
40087 uint16_t tx_cfa_action_a;
40088 /* Only valid for mode 2. */
40089 uint16_t rx_cfa_code_b;
40090 /* Only valid for mode 2. */
40091 uint16_t tx_cfa_action_b;
40092 uint8_t unused_0[7];
40094 * This field is used in Output records to indicate that the output
40095 * is completely written to RAM. This field should be read as '1'
40096 * to indicate that the output has been completely written.
40097 * When writing a command completion or response to an internal
40098 * processor, the order of writes has to be such that this field is
40104 /**********************
40105 * hwrm_cfa_pair_free *
40106 **********************/
40109 /* hwrm_cfa_pair_free_input (size:448b/56B) */
40110 struct hwrm_cfa_pair_free_input {
40111 /* The HWRM command request type. */
40114 * The completion ring to send the completion event on. This should
40115 * be the NQ ID returned from the `nq_alloc` HWRM command.
40117 uint16_t cmpl_ring;
40119 * The sequence ID is used by the driver for tracking multiple
40120 * commands. This ID is treated as opaque data by the firmware and
40121 * the value is returned in the `hwrm_resp_hdr` upon completion.
40125 * The target ID of the command:
40126 * * 0x0-0xFFF8 - The function ID
40127 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
40128 * * 0xFFFD - Reserved for user-space HWRM interface
40131 uint16_t target_id;
40133 * A physical address pointer pointing to a host buffer that the
40134 * command's response data will be written. This can be either a host
40135 * physical address (HPA) or a guest physical address (GPA) and must
40136 * point to a physically contiguous block of memory.
40138 uint64_t resp_addr;
40139 /* VF Pair name (32 byte string). */
40140 char pair_name[32];
40141 /* Logical PF (0xff-PF for command channel). */
40143 uint8_t unused_0[3];
40144 /* Logical VF number (range: 0 -> MAX_VFS -1). */
40147 * Pair mode (0-vf2fn, 1-rep2fn, 2-rep2rep, 3-proxy, 4-pfpair,
40148 * 5-rep2fn_mod, 6-rep2fn_modall, 7-rep2fn_truflow).
40150 uint16_t pair_mode;
40151 /* Pair between VF on local host with PF or VF on specified host. */
40152 #define HWRM_CFA_PAIR_FREE_INPUT_PAIR_MODE_VF2FN UINT32_C(0x0)
40153 /* Pair between REP on local host with PF or VF on specified host. */
40154 #define HWRM_CFA_PAIR_FREE_INPUT_PAIR_MODE_REP2FN UINT32_C(0x1)
40155 /* Pair between REP on local host with REP on specified host. */
40156 #define HWRM_CFA_PAIR_FREE_INPUT_PAIR_MODE_REP2REP UINT32_C(0x2)
40157 /* Pair for the proxy interface. */
40158 #define HWRM_CFA_PAIR_FREE_INPUT_PAIR_MODE_PROXY UINT32_C(0x3)
40159 /* Pair for the PF interface. */
40160 #define HWRM_CFA_PAIR_FREE_INPUT_PAIR_MODE_PFPAIR UINT32_C(0x4)
40161 /* Modify existing rep2fn pair and move pair to new PF. */
40162 #define HWRM_CFA_PAIR_FREE_INPUT_PAIR_MODE_REP2FN_MOD UINT32_C(0x5)
40164 * Modify existing rep2fn pairs paired with same PF and move pairs
40167 #define HWRM_CFA_PAIR_FREE_INPUT_PAIR_MODE_REP2FN_MODALL UINT32_C(0x6)
40169 * Truflow pair between REP on local host with PF or VF on
40172 #define HWRM_CFA_PAIR_FREE_INPUT_PAIR_MODE_REP2FN_TRUFLOW UINT32_C(0x7)
40173 #define HWRM_CFA_PAIR_FREE_INPUT_PAIR_MODE_LAST \
40174 HWRM_CFA_PAIR_FREE_INPUT_PAIR_MODE_REP2FN_TRUFLOW
40177 /* hwrm_cfa_pair_free_output (size:128b/16B) */
40178 struct hwrm_cfa_pair_free_output {
40179 /* The specific error status for the command. */
40180 uint16_t error_code;
40181 /* The HWRM command request type. */
40183 /* The sequence ID from the original command. */
40185 /* The length of the response data in number of bytes. */
40187 uint8_t unused_0[7];
40189 * This field is used in Output records to indicate that the output
40190 * is completely written to RAM. This field should be read as '1'
40191 * to indicate that the output has been completely written.
40192 * When writing a command completion or response to an internal
40193 * processor, the order of writes has to be such that this field is
40199 /**********************
40200 * hwrm_cfa_pair_info *
40201 **********************/
40204 /* hwrm_cfa_pair_info_input (size:448b/56B) */
40205 struct hwrm_cfa_pair_info_input {
40206 /* The HWRM command request type. */
40209 * The completion ring to send the completion event on. This should
40210 * be the NQ ID returned from the `nq_alloc` HWRM command.
40212 uint16_t cmpl_ring;
40214 * The sequence ID is used by the driver for tracking multiple
40215 * commands. This ID is treated as opaque data by the firmware and
40216 * the value is returned in the `hwrm_resp_hdr` upon completion.
40220 * The target ID of the command:
40221 * * 0x0-0xFFF8 - The function ID
40222 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
40223 * * 0xFFFD - Reserved for user-space HWRM interface
40226 uint16_t target_id;
40228 * A physical address pointer pointing to a host buffer that the
40229 * command's response data will be written. This can be either a host
40230 * physical address (HPA) or a guest physical address (GPA) and must
40231 * point to a physically contiguous block of memory.
40233 uint64_t resp_addr;
40235 /* If this flag is set, lookup by name else lookup by index. */
40236 #define HWRM_CFA_PAIR_INFO_INPUT_FLAGS_LOOKUP_TYPE UINT32_C(0x1)
40237 /* If this flag is set, lookup by PF id and VF id. */
40238 #define HWRM_CFA_PAIR_INFO_INPUT_FLAGS_LOOKUP_REPRE UINT32_C(0x2)
40239 /* Pair table index. */
40240 uint16_t pair_index;
40241 /* Pair pf index. */
40243 /* Pair vf index. */
40245 /* Pair name (32 byte string). */
40246 char pair_name[32];
40249 /* hwrm_cfa_pair_info_output (size:576b/72B) */
40250 struct hwrm_cfa_pair_info_output {
40251 /* The specific error status for the command. */
40252 uint16_t error_code;
40253 /* The HWRM command request type. */
40255 /* The sequence ID from the original command. */
40257 /* The length of the response data in number of bytes. */
40259 /* Pair table index. */
40260 uint16_t next_pair_index;
40261 /* Pair member a's fid. */
40263 /* Logical host number. */
40264 uint8_t host_a_index;
40265 /* Logical PF number. */
40266 uint8_t pf_a_index;
40267 /* Pair member a's Linux logical VF number. */
40268 uint16_t vf_a_index;
40270 uint16_t rx_cfa_code_a;
40271 /* Tx CFA action. */
40272 uint16_t tx_cfa_action_a;
40273 /* Pair member b's fid. */
40275 /* Logical host number. */
40276 uint8_t host_b_index;
40277 /* Logical PF number. */
40278 uint8_t pf_b_index;
40279 /* Pair member a's Linux logical VF number. */
40280 uint16_t vf_b_index;
40282 uint16_t rx_cfa_code_b;
40283 /* Tx CFA action. */
40284 uint16_t tx_cfa_action_b;
40285 /* Pair mode (0-vf2fn, 1-rep2fn, 2-rep2rep, 3-proxy, 4-pfpair). */
40287 /* Pair between VF on local host with PF or VF on specified host. */
40288 #define HWRM_CFA_PAIR_INFO_OUTPUT_PAIR_MODE_VF2FN UINT32_C(0x0)
40289 /* Pair between REP on local host with PF or VF on specified host. */
40290 #define HWRM_CFA_PAIR_INFO_OUTPUT_PAIR_MODE_REP2FN UINT32_C(0x1)
40291 /* Pair between REP on local host with REP on specified host. */
40292 #define HWRM_CFA_PAIR_INFO_OUTPUT_PAIR_MODE_REP2REP UINT32_C(0x2)
40293 /* Pair for the proxy interface. */
40294 #define HWRM_CFA_PAIR_INFO_OUTPUT_PAIR_MODE_PROXY UINT32_C(0x3)
40295 /* Pair for the PF interface. */
40296 #define HWRM_CFA_PAIR_INFO_OUTPUT_PAIR_MODE_PFPAIR UINT32_C(0x4)
40297 #define HWRM_CFA_PAIR_INFO_OUTPUT_PAIR_MODE_LAST \
40298 HWRM_CFA_PAIR_INFO_OUTPUT_PAIR_MODE_PFPAIR
40300 uint8_t pair_state;
40301 /* Pair has been allocated */
40302 #define HWRM_CFA_PAIR_INFO_OUTPUT_PAIR_STATE_ALLOCATED UINT32_C(0x1)
40303 /* Both pair members are active */
40304 #define HWRM_CFA_PAIR_INFO_OUTPUT_PAIR_STATE_ACTIVE UINT32_C(0x2)
40305 #define HWRM_CFA_PAIR_INFO_OUTPUT_PAIR_STATE_LAST \
40306 HWRM_CFA_PAIR_INFO_OUTPUT_PAIR_STATE_ACTIVE
40307 /* Pair name (32 byte string). */
40308 char pair_name[32];
40309 uint8_t unused_0[7];
40311 * This field is used in Output records to indicate that the output
40312 * is completely written to RAM. This field should be read as '1'
40313 * to indicate that the output has been completely written.
40314 * When writing a command completion or response to an internal
40315 * processor, the order of writes has to be such that this field is
40321 /**********************
40322 * hwrm_cfa_vfr_alloc *
40323 **********************/
40326 /* hwrm_cfa_vfr_alloc_input (size:448b/56B) */
40327 struct hwrm_cfa_vfr_alloc_input {
40328 /* The HWRM command request type. */
40331 * The completion ring to send the completion event on. This should
40332 * be the NQ ID returned from the `nq_alloc` HWRM command.
40334 uint16_t cmpl_ring;
40336 * The sequence ID is used by the driver for tracking multiple
40337 * commands. This ID is treated as opaque data by the firmware and
40338 * the value is returned in the `hwrm_resp_hdr` upon completion.
40342 * The target ID of the command:
40343 * * 0x0-0xFFF8 - The function ID
40344 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
40345 * * 0xFFFD - Reserved for user-space HWRM interface
40348 uint16_t target_id;
40350 * A physical address pointer pointing to a host buffer that the
40351 * command's response data will be written. This can be either a host
40352 * physical address (HPA) or a guest physical address (GPA) and must
40353 * point to a physically contiguous block of memory.
40355 uint64_t resp_addr;
40356 /* Logical VF number (range: 0 -> MAX_VFS -1). */
40359 * This field is reserved for the future use.
40360 * It shall be set to 0.
40363 uint8_t unused_0[4];
40364 /* VF Representor name (32 byte string). */
40368 /* hwrm_cfa_vfr_alloc_output (size:128b/16B) */
40369 struct hwrm_cfa_vfr_alloc_output {
40370 /* The specific error status for the command. */
40371 uint16_t error_code;
40372 /* The HWRM command request type. */
40374 /* The sequence ID from the original command. */
40376 /* The length of the response data in number of bytes. */
40379 uint16_t rx_cfa_code;
40380 /* Tx CFA action. */
40381 uint16_t tx_cfa_action;
40382 uint8_t unused_0[3];
40384 * This field is used in Output records to indicate that the output
40385 * is completely written to RAM. This field should be read as '1'
40386 * to indicate that the output has been completely written.
40387 * When writing a command completion or response to an internal
40388 * processor, the order of writes has to be such that this field is
40394 /*********************
40395 * hwrm_cfa_vfr_free *
40396 *********************/
40399 /* hwrm_cfa_vfr_free_input (size:448b/56B) */
40400 struct hwrm_cfa_vfr_free_input {
40401 /* The HWRM command request type. */
40404 * The completion ring to send the completion event on. This should
40405 * be the NQ ID returned from the `nq_alloc` HWRM command.
40407 uint16_t cmpl_ring;
40409 * The sequence ID is used by the driver for tracking multiple
40410 * commands. This ID is treated as opaque data by the firmware and
40411 * the value is returned in the `hwrm_resp_hdr` upon completion.
40415 * The target ID of the command:
40416 * * 0x0-0xFFF8 - The function ID
40417 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
40418 * * 0xFFFD - Reserved for user-space HWRM interface
40421 uint16_t target_id;
40423 * A physical address pointer pointing to a host buffer that the
40424 * command's response data will be written. This can be either a host
40425 * physical address (HPA) or a guest physical address (GPA) and must
40426 * point to a physically contiguous block of memory.
40428 uint64_t resp_addr;
40429 /* VF Representor name (32 byte string). */
40431 /* Logical VF number (range: 0 -> MAX_VFS -1). */
40434 * This field is reserved for the future use.
40435 * It shall be set to 0.
40438 uint8_t unused_0[4];
40441 /* hwrm_cfa_vfr_free_output (size:128b/16B) */
40442 struct hwrm_cfa_vfr_free_output {
40443 /* The specific error status for the command. */
40444 uint16_t error_code;
40445 /* The HWRM command request type. */
40447 /* The sequence ID from the original command. */
40449 /* The length of the response data in number of bytes. */
40451 uint8_t unused_0[7];
40453 * This field is used in Output records to indicate that the output
40454 * is completely written to RAM. This field should be read as '1'
40455 * to indicate that the output has been completely written.
40456 * When writing a command completion or response to an internal
40457 * processor, the order of writes has to be such that this field is
40463 /***************************************
40464 * hwrm_cfa_redirect_query_tunnel_type *
40465 ***************************************/
40468 /* hwrm_cfa_redirect_query_tunnel_type_input (size:192b/24B) */
40469 struct hwrm_cfa_redirect_query_tunnel_type_input {
40470 /* The HWRM command request type. */
40473 * The completion ring to send the completion event on. This should
40474 * be the NQ ID returned from the `nq_alloc` HWRM command.
40476 uint16_t cmpl_ring;
40478 * The sequence ID is used by the driver for tracking multiple
40479 * commands. This ID is treated as opaque data by the firmware and
40480 * the value is returned in the `hwrm_resp_hdr` upon completion.
40484 * The target ID of the command:
40485 * * 0x0-0xFFF8 - The function ID
40486 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
40487 * * 0xFFFD - Reserved for user-space HWRM interface
40490 uint16_t target_id;
40492 * A physical address pointer pointing to a host buffer that the
40493 * command's response data will be written. This can be either a host
40494 * physical address (HPA) or a guest physical address (GPA) and must
40495 * point to a physically contiguous block of memory.
40497 uint64_t resp_addr;
40498 /* The source function id. */
40500 uint8_t unused_0[6];
40503 /* hwrm_cfa_redirect_query_tunnel_type_output (size:128b/16B) */
40504 struct hwrm_cfa_redirect_query_tunnel_type_output {
40505 /* The specific error status for the command. */
40506 uint16_t error_code;
40507 /* The HWRM command request type. */
40509 /* The sequence ID from the original command. */
40511 /* The length of the response data in number of bytes. */
40514 uint32_t tunnel_mask;
40516 #define HWRM_CFA_REDIRECT_QUERY_TUNNEL_TYPE_OUTPUT_TUNNEL_MASK_NONTUNNEL \
40518 /* Virtual eXtensible Local Area Network (VXLAN) */
40519 #define HWRM_CFA_REDIRECT_QUERY_TUNNEL_TYPE_OUTPUT_TUNNEL_MASK_VXLAN \
40521 /* Network Virtualization Generic Routing Encapsulation (NVGRE) */
40522 #define HWRM_CFA_REDIRECT_QUERY_TUNNEL_TYPE_OUTPUT_TUNNEL_MASK_NVGRE \
40524 /* Generic Routing Encapsulation (GRE) inside Ethernet payload */
40525 #define HWRM_CFA_REDIRECT_QUERY_TUNNEL_TYPE_OUTPUT_TUNNEL_MASK_L2GRE \
40528 #define HWRM_CFA_REDIRECT_QUERY_TUNNEL_TYPE_OUTPUT_TUNNEL_MASK_IPIP \
40530 /* Generic Network Virtualization Encapsulation (Geneve) */
40531 #define HWRM_CFA_REDIRECT_QUERY_TUNNEL_TYPE_OUTPUT_TUNNEL_MASK_GENEVE \
40533 /* Multi-Protocol Label Switching (MPLS) */
40534 #define HWRM_CFA_REDIRECT_QUERY_TUNNEL_TYPE_OUTPUT_TUNNEL_MASK_MPLS \
40536 /* Stateless Transport Tunnel (STT) */
40537 #define HWRM_CFA_REDIRECT_QUERY_TUNNEL_TYPE_OUTPUT_TUNNEL_MASK_STT \
40539 /* Generic Routing Encapsulation (GRE) inside IP datagram payload */
40540 #define HWRM_CFA_REDIRECT_QUERY_TUNNEL_TYPE_OUTPUT_TUNNEL_MASK_IPGRE \
40542 /* IPV4 over virtual eXtensible Local Area Network (IPV4oVXLAN) */
40543 #define HWRM_CFA_REDIRECT_QUERY_TUNNEL_TYPE_OUTPUT_TUNNEL_MASK_VXLAN_V4 \
40546 * Enhance Generic Routing Encapsulation (GRE version 1) inside IP
40549 #define HWRM_CFA_REDIRECT_QUERY_TUNNEL_TYPE_OUTPUT_TUNNEL_MASK_IPGRE_V1 \
40551 /* Any tunneled traffic */
40552 #define HWRM_CFA_REDIRECT_QUERY_TUNNEL_TYPE_OUTPUT_TUNNEL_MASK_ANYTUNNEL \
40554 /* Use fixed layer 2 ether type of 0xFFFF */
40555 #define HWRM_CFA_REDIRECT_QUERY_TUNNEL_TYPE_OUTPUT_TUNNEL_MASK_L2_ETYPE \
40558 * IPV6 over virtual eXtensible Local Area Network with GPE header
40561 #define HWRM_CFA_REDIRECT_QUERY_TUNNEL_TYPE_OUTPUT_TUNNEL_MASK_VXLAN_GPE_V6 \
40563 uint8_t unused_0[3];
40565 * This field is used in Output records to indicate that the output
40566 * is completely written to RAM. This field should be read as '1'
40567 * to indicate that the output has been completely written.
40568 * When writing a command completion or response to an internal
40569 * processor, the order of writes has to be such that this field is
40575 /*************************
40576 * hwrm_cfa_ctx_mem_rgtr *
40577 *************************/
40580 /* hwrm_cfa_ctx_mem_rgtr_input (size:256b/32B) */
40581 struct hwrm_cfa_ctx_mem_rgtr_input {
40582 /* The HWRM command request type. */
40585 * The completion ring to send the completion event on. This should
40586 * be the NQ ID returned from the `nq_alloc` HWRM command.
40588 uint16_t cmpl_ring;
40590 * The sequence ID is used by the driver for tracking multiple
40591 * commands. This ID is treated as opaque data by the firmware and
40592 * the value is returned in the `hwrm_resp_hdr` upon completion.
40596 * The target ID of the command:
40597 * * 0x0-0xFFF8 - The function ID
40598 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
40599 * * 0xFFFD - Reserved for user-space HWRM interface
40602 uint16_t target_id;
40604 * A physical address pointer pointing to a host buffer that the
40605 * command's response data will be written. This can be either a host
40606 * physical address (HPA) or a guest physical address (GPA) and must
40607 * point to a physically contiguous block of memory.
40609 uint64_t resp_addr;
40611 /* Counter PBL indirect levels. */
40612 uint8_t page_level;
40613 /* PBL pointer is physical start address. */
40614 #define HWRM_CFA_CTX_MEM_RGTR_INPUT_PAGE_LEVEL_LVL_0 UINT32_C(0x0)
40615 /* PBL pointer points to PTE table. */
40616 #define HWRM_CFA_CTX_MEM_RGTR_INPUT_PAGE_LEVEL_LVL_1 UINT32_C(0x1)
40618 * PBL pointer points to PDE table with each entry pointing to PTE
40621 #define HWRM_CFA_CTX_MEM_RGTR_INPUT_PAGE_LEVEL_LVL_2 UINT32_C(0x2)
40622 #define HWRM_CFA_CTX_MEM_RGTR_INPUT_PAGE_LEVEL_LAST \
40623 HWRM_CFA_CTX_MEM_RGTR_INPUT_PAGE_LEVEL_LVL_2
40626 /* 4KB page size. */
40627 #define HWRM_CFA_CTX_MEM_RGTR_INPUT_PAGE_SIZE_4K UINT32_C(0x0)
40628 /* 8KB page size. */
40629 #define HWRM_CFA_CTX_MEM_RGTR_INPUT_PAGE_SIZE_8K UINT32_C(0x1)
40630 /* 64KB page size. */
40631 #define HWRM_CFA_CTX_MEM_RGTR_INPUT_PAGE_SIZE_64K UINT32_C(0x4)
40632 /* 256KB page size. */
40633 #define HWRM_CFA_CTX_MEM_RGTR_INPUT_PAGE_SIZE_256K UINT32_C(0x6)
40634 /* 1MB page size. */
40635 #define HWRM_CFA_CTX_MEM_RGTR_INPUT_PAGE_SIZE_1M UINT32_C(0x8)
40636 /* 2MB page size. */
40637 #define HWRM_CFA_CTX_MEM_RGTR_INPUT_PAGE_SIZE_2M UINT32_C(0x9)
40638 /* 4MB page size. */
40639 #define HWRM_CFA_CTX_MEM_RGTR_INPUT_PAGE_SIZE_4M UINT32_C(0xa)
40640 /* 1GB page size. */
40641 #define HWRM_CFA_CTX_MEM_RGTR_INPUT_PAGE_SIZE_1G UINT32_C(0x12)
40642 #define HWRM_CFA_CTX_MEM_RGTR_INPUT_PAGE_SIZE_LAST \
40643 HWRM_CFA_CTX_MEM_RGTR_INPUT_PAGE_SIZE_1G
40645 /* Pointer to the PBL, or PDL depending on number of levels */
40649 /* hwrm_cfa_ctx_mem_rgtr_output (size:128b/16B) */
40650 struct hwrm_cfa_ctx_mem_rgtr_output {
40651 /* The specific error status for the command. */
40652 uint16_t error_code;
40653 /* The HWRM command request type. */
40655 /* The sequence ID from the original command. */
40657 /* The length of the response data in number of bytes. */
40660 * Id/Handle to the recently register context memory. This handle is
40661 * passed to the CFA feature.
40664 uint8_t unused_0[5];
40666 * This field is used in Output records to indicate that the output
40667 * is completely written to RAM. This field should be read as '1'
40668 * to indicate that the output has been completely written.
40669 * When writing a command completion or response to an internal
40670 * processor, the order of writes has to be such that this field is
40676 /***************************
40677 * hwrm_cfa_ctx_mem_unrgtr *
40678 ***************************/
40681 /* hwrm_cfa_ctx_mem_unrgtr_input (size:192b/24B) */
40682 struct hwrm_cfa_ctx_mem_unrgtr_input {
40683 /* The HWRM command request type. */
40686 * The completion ring to send the completion event on. This should
40687 * be the NQ ID returned from the `nq_alloc` HWRM command.
40689 uint16_t cmpl_ring;
40691 * The sequence ID is used by the driver for tracking multiple
40692 * commands. This ID is treated as opaque data by the firmware and
40693 * the value is returned in the `hwrm_resp_hdr` upon completion.
40697 * The target ID of the command:
40698 * * 0x0-0xFFF8 - The function ID
40699 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
40700 * * 0xFFFD - Reserved for user-space HWRM interface
40703 uint16_t target_id;
40705 * A physical address pointer pointing to a host buffer that the
40706 * command's response data will be written. This can be either a host
40707 * physical address (HPA) or a guest physical address (GPA) and must
40708 * point to a physically contiguous block of memory.
40710 uint64_t resp_addr;
40712 * Id/Handle to the recently register context memory. This handle is
40713 * passed to the CFA feature.
40716 uint8_t unused_0[6];
40719 /* hwrm_cfa_ctx_mem_unrgtr_output (size:128b/16B) */
40720 struct hwrm_cfa_ctx_mem_unrgtr_output {
40721 /* The specific error status for the command. */
40722 uint16_t error_code;
40723 /* The HWRM command request type. */
40725 /* The sequence ID from the original command. */
40727 /* The length of the response data in number of bytes. */
40729 uint8_t unused_0[7];
40731 * This field is used in Output records to indicate that the output
40732 * is completely written to RAM. This field should be read as '1'
40733 * to indicate that the output has been completely written.
40734 * When writing a command completion or response to an internal
40735 * processor, the order of writes has to be such that this field is
40741 /*************************
40742 * hwrm_cfa_ctx_mem_qctx *
40743 *************************/
40746 /* hwrm_cfa_ctx_mem_qctx_input (size:192b/24B) */
40747 struct hwrm_cfa_ctx_mem_qctx_input {
40748 /* The HWRM command request type. */
40751 * The completion ring to send the completion event on. This should
40752 * be the NQ ID returned from the `nq_alloc` HWRM command.
40754 uint16_t cmpl_ring;
40756 * The sequence ID is used by the driver for tracking multiple
40757 * commands. This ID is treated as opaque data by the firmware and
40758 * the value is returned in the `hwrm_resp_hdr` upon completion.
40762 * The target ID of the command:
40763 * * 0x0-0xFFF8 - The function ID
40764 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
40765 * * 0xFFFD - Reserved for user-space HWRM interface
40768 uint16_t target_id;
40770 * A physical address pointer pointing to a host buffer that the
40771 * command's response data will be written. This can be either a host
40772 * physical address (HPA) or a guest physical address (GPA) and must
40773 * point to a physically contiguous block of memory.
40775 uint64_t resp_addr;
40777 * Id/Handle to the recently register context memory. This handle is
40778 * passed to the CFA feature.
40781 uint8_t unused_0[6];
40784 /* hwrm_cfa_ctx_mem_qctx_output (size:256b/32B) */
40785 struct hwrm_cfa_ctx_mem_qctx_output {
40786 /* The specific error status for the command. */
40787 uint16_t error_code;
40788 /* The HWRM command request type. */
40790 /* The sequence ID from the original command. */
40792 /* The length of the response data in number of bytes. */
40795 /* Counter PBL indirect levels. */
40796 uint8_t page_level;
40797 /* PBL pointer is physical start address. */
40798 #define HWRM_CFA_CTX_MEM_QCTX_OUTPUT_PAGE_LEVEL_LVL_0 UINT32_C(0x0)
40799 /* PBL pointer points to PTE table. */
40800 #define HWRM_CFA_CTX_MEM_QCTX_OUTPUT_PAGE_LEVEL_LVL_1 UINT32_C(0x1)
40802 * PBL pointer points to PDE table with each entry pointing to PTE
40805 #define HWRM_CFA_CTX_MEM_QCTX_OUTPUT_PAGE_LEVEL_LVL_2 UINT32_C(0x2)
40806 #define HWRM_CFA_CTX_MEM_QCTX_OUTPUT_PAGE_LEVEL_LAST \
40807 HWRM_CFA_CTX_MEM_QCTX_OUTPUT_PAGE_LEVEL_LVL_2
40810 /* 4KB page size. */
40811 #define HWRM_CFA_CTX_MEM_QCTX_OUTPUT_PAGE_SIZE_4K UINT32_C(0x0)
40812 /* 8KB page size. */
40813 #define HWRM_CFA_CTX_MEM_QCTX_OUTPUT_PAGE_SIZE_8K UINT32_C(0x1)
40814 /* 64KB page size. */
40815 #define HWRM_CFA_CTX_MEM_QCTX_OUTPUT_PAGE_SIZE_64K UINT32_C(0x4)
40816 /* 256KB page size. */
40817 #define HWRM_CFA_CTX_MEM_QCTX_OUTPUT_PAGE_SIZE_256K UINT32_C(0x6)
40818 /* 1MB page size. */
40819 #define HWRM_CFA_CTX_MEM_QCTX_OUTPUT_PAGE_SIZE_1M UINT32_C(0x8)
40820 /* 2MB page size. */
40821 #define HWRM_CFA_CTX_MEM_QCTX_OUTPUT_PAGE_SIZE_2M UINT32_C(0x9)
40822 /* 4MB page size. */
40823 #define HWRM_CFA_CTX_MEM_QCTX_OUTPUT_PAGE_SIZE_4M UINT32_C(0xa)
40824 /* 1GB page size. */
40825 #define HWRM_CFA_CTX_MEM_QCTX_OUTPUT_PAGE_SIZE_1G UINT32_C(0x12)
40826 #define HWRM_CFA_CTX_MEM_QCTX_OUTPUT_PAGE_SIZE_LAST \
40827 HWRM_CFA_CTX_MEM_QCTX_OUTPUT_PAGE_SIZE_1G
40828 uint8_t unused_0[4];
40829 /* Pointer to the PBL, or PDL depending on number of levels */
40831 uint8_t unused_1[7];
40833 * This field is used in Output records to indicate that the output
40834 * is completely written to RAM. This field should be read as '1'
40835 * to indicate that the output has been completely written.
40836 * When writing a command completion or response to an internal
40837 * processor, the order of writes has to be such that this field is
40843 /**************************
40844 * hwrm_cfa_ctx_mem_qcaps *
40845 **************************/
40848 /* hwrm_cfa_ctx_mem_qcaps_input (size:128b/16B) */
40849 struct hwrm_cfa_ctx_mem_qcaps_input {
40850 /* The HWRM command request type. */
40853 * The completion ring to send the completion event on. This should
40854 * be the NQ ID returned from the `nq_alloc` HWRM command.
40856 uint16_t cmpl_ring;
40858 * The sequence ID is used by the driver for tracking multiple
40859 * commands. This ID is treated as opaque data by the firmware and
40860 * the value is returned in the `hwrm_resp_hdr` upon completion.
40864 * The target ID of the command:
40865 * * 0x0-0xFFF8 - The function ID
40866 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
40867 * * 0xFFFD - Reserved for user-space HWRM interface
40870 uint16_t target_id;
40872 * A physical address pointer pointing to a host buffer that the
40873 * command's response data will be written. This can be either a host
40874 * physical address (HPA) or a guest physical address (GPA) and must
40875 * point to a physically contiguous block of memory.
40877 uint64_t resp_addr;
40880 /* hwrm_cfa_ctx_mem_qcaps_output (size:128b/16B) */
40881 struct hwrm_cfa_ctx_mem_qcaps_output {
40882 /* The specific error status for the command. */
40883 uint16_t error_code;
40884 /* The HWRM command request type. */
40886 /* The sequence ID from the original command. */
40888 /* The length of the response data in number of bytes. */
40891 * Indicates the maximum number of context memory which can be
40894 uint16_t max_entries;
40895 uint8_t unused_0[5];
40897 * This field is used in Output records to indicate that the output
40898 * is completely written to RAM. This field should be read as '1'
40899 * to indicate that the output has been completely written.
40900 * When writing a command completion or response to an internal
40901 * processor, the order of writes has to be such that this field is
40907 /**************************
40908 * hwrm_cfa_counter_qcaps *
40909 **************************/
40912 /* hwrm_cfa_counter_qcaps_input (size:128b/16B) */
40913 struct hwrm_cfa_counter_qcaps_input {
40914 /* The HWRM command request type. */
40917 * The completion ring to send the completion event on. This should
40918 * be the NQ ID returned from the `nq_alloc` HWRM command.
40920 uint16_t cmpl_ring;
40922 * The sequence ID is used by the driver for tracking multiple
40923 * commands. This ID is treated as opaque data by the firmware and
40924 * the value is returned in the `hwrm_resp_hdr` upon completion.
40928 * The target ID of the command:
40929 * * 0x0-0xFFF8 - The function ID
40930 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
40931 * * 0xFFFD - Reserved for user-space HWRM interface
40934 uint16_t target_id;
40936 * A physical address pointer pointing to a host buffer that the
40937 * command's response data will be written. This can be either a host
40938 * physical address (HPA) or a guest physical address (GPA) and must
40939 * point to a physically contiguous block of memory.
40941 uint64_t resp_addr;
40944 /* hwrm_cfa_counter_qcaps_output (size:576b/72B) */
40945 struct hwrm_cfa_counter_qcaps_output {
40946 /* The specific error status for the command. */
40947 uint16_t error_code;
40948 /* The HWRM command request type. */
40950 /* The sequence ID from the original command. */
40952 /* The length of the response data in number of bytes. */
40955 /* Enumeration denoting the supported CFA counter format. */
40956 #define HWRM_CFA_COUNTER_QCAPS_OUTPUT_FLAGS_COUNTER_FORMAT \
40958 /* CFA counter types are not supported. */
40959 #define HWRM_CFA_COUNTER_QCAPS_OUTPUT_FLAGS_COUNTER_FORMAT_NONE \
40961 /* 64-bit packet counters followed by 64-bit byte counters format. */
40962 #define HWRM_CFA_COUNTER_QCAPS_OUTPUT_FLAGS_COUNTER_FORMAT_64_BIT \
40964 #define HWRM_CFA_COUNTER_QCAPS_OUTPUT_FLAGS_COUNTER_FORMAT_LAST \
40965 HWRM_CFA_COUNTER_QCAPS_OUTPUT_FLAGS_COUNTER_FORMAT_64_BIT
40968 * Minimum guaranteed number of flow counters supported for this
40969 * function, in RX direction.
40971 uint32_t min_rx_fc;
40973 * Maximum non-guaranteed number of flow counters supported for this
40974 * function, in RX direction.
40976 uint32_t max_rx_fc;
40978 * Minimum guaranteed number of flow counters supported for this
40979 * function, in TX direction.
40981 uint32_t min_tx_fc;
40983 * Maximum non-guaranteed number of flow counters supported for this
40984 * function, in TX direction.
40986 uint32_t max_tx_fc;
40988 * Minimum guaranteed number of extension flow counters supported for
40989 * this function, in RX direction.
40991 uint32_t min_rx_efc;
40993 * Maximum non-guaranteed number of extension flow counters supported
40994 * for this function, in RX direction.
40996 uint32_t max_rx_efc;
40998 * Minimum guaranteed number of extension flow counters supported for
40999 * this function, in TX direction.
41001 uint32_t min_tx_efc;
41003 * Maximum non-guaranteed number of extension flow counters supported
41004 * for this function, in TX direction.
41006 uint32_t max_tx_efc;
41008 * Minimum guaranteed number of meter drop counters supported for
41009 * this function, in RX direction.
41011 uint32_t min_rx_mdc;
41013 * Maximum non-guaranteed number of meter drop counters supported for
41014 * this function, in RX direction.
41016 uint32_t max_rx_mdc;
41018 * Minimum guaranteed number of meter drop counters supported for this
41019 * function, in TX direction.
41021 uint32_t min_tx_mdc;
41023 * Maximum non-guaranteed number of meter drop counters supported for
41024 * this function, in TX direction.
41026 uint32_t max_tx_mdc;
41028 * Maximum guaranteed number of flow counters which can be used during
41031 uint32_t max_flow_alloc_fc;
41032 uint8_t unused_1[3];
41034 * This field is used in Output records to indicate that the output
41035 * is completely written to RAM. This field should be read as '1'
41036 * to indicate that the output has been completely written.
41037 * When writing a command completion or response to an internal
41038 * processor, the order of writes has to be such that this field is
41044 /************************
41045 * hwrm_cfa_counter_cfg *
41046 ************************/
41049 /* hwrm_cfa_counter_cfg_input (size:256b/32B) */
41050 struct hwrm_cfa_counter_cfg_input {
41051 /* The HWRM command request type. */
41054 * The completion ring to send the completion event on. This should
41055 * be the NQ ID returned from the `nq_alloc` HWRM command.
41057 uint16_t cmpl_ring;
41059 * The sequence ID is used by the driver for tracking multiple
41060 * commands. This ID is treated as opaque data by the firmware and
41061 * the value is returned in the `hwrm_resp_hdr` upon completion.
41065 * The target ID of the command:
41066 * * 0x0-0xFFF8 - The function ID
41067 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
41068 * * 0xFFFD - Reserved for user-space HWRM interface
41071 uint16_t target_id;
41073 * A physical address pointer pointing to a host buffer that the
41074 * command's response data will be written. This can be either a host
41075 * physical address (HPA) or a guest physical address (GPA) and must
41076 * point to a physically contiguous block of memory.
41078 uint64_t resp_addr;
41080 /* Enumeration denoting the configuration mode. */
41081 #define HWRM_CFA_COUNTER_CFG_INPUT_FLAGS_CFG_MODE \
41083 /* Disable the configuration mode. */
41084 #define HWRM_CFA_COUNTER_CFG_INPUT_FLAGS_CFG_MODE_DISABLE \
41086 /* Enable the configuration mode. */
41087 #define HWRM_CFA_COUNTER_CFG_INPUT_FLAGS_CFG_MODE_ENABLE \
41089 #define HWRM_CFA_COUNTER_CFG_INPUT_FLAGS_CFG_MODE_LAST \
41090 HWRM_CFA_COUNTER_CFG_INPUT_FLAGS_CFG_MODE_ENABLE
41091 /* Enumeration denoting the RX, TX type of the resource. */
41092 #define HWRM_CFA_COUNTER_CFG_INPUT_FLAGS_PATH \
41095 #define HWRM_CFA_COUNTER_CFG_INPUT_FLAGS_PATH_TX \
41096 (UINT32_C(0x0) << 1)
41098 #define HWRM_CFA_COUNTER_CFG_INPUT_FLAGS_PATH_RX \
41099 (UINT32_C(0x1) << 1)
41100 #define HWRM_CFA_COUNTER_CFG_INPUT_FLAGS_PATH_LAST \
41101 HWRM_CFA_COUNTER_CFG_INPUT_FLAGS_PATH_RX
41102 /* Enumeration denoting the data transfer mode. */
41103 #define HWRM_CFA_COUNTER_CFG_INPUT_FLAGS_DATA_TRANSFER_MODE_MASK \
41105 #define HWRM_CFA_COUNTER_CFG_INPUT_FLAGS_DATA_TRANSFER_MODE_SFT 2
41107 #define HWRM_CFA_COUNTER_CFG_INPUT_FLAGS_DATA_TRANSFER_MODE_PUSH \
41108 (UINT32_C(0x0) << 2)
41110 #define HWRM_CFA_COUNTER_CFG_INPUT_FLAGS_DATA_TRANSFER_MODE_PULL \
41111 (UINT32_C(0x1) << 2)
41112 /* Pull on async update. */
41113 #define HWRM_CFA_COUNTER_CFG_INPUT_FLAGS_DATA_TRANSFER_MODE_PULL_ASYNC \
41114 (UINT32_C(0x2) << 2)
41115 #define HWRM_CFA_COUNTER_CFG_INPUT_FLAGS_DATA_TRANSFER_MODE_LAST \
41116 HWRM_CFA_COUNTER_CFG_INPUT_FLAGS_DATA_TRANSFER_MODE_PULL_ASYNC
41117 uint16_t counter_type;
41118 /* Flow counters. */
41119 #define HWRM_CFA_COUNTER_CFG_INPUT_COUNTER_TYPE_FC UINT32_C(0x0)
41120 /* Extended flow counters. */
41121 #define HWRM_CFA_COUNTER_CFG_INPUT_COUNTER_TYPE_EFC UINT32_C(0x1)
41122 /* Meter drop counters. */
41123 #define HWRM_CFA_COUNTER_CFG_INPUT_COUNTER_TYPE_MDC UINT32_C(0x2)
41124 #define HWRM_CFA_COUNTER_CFG_INPUT_COUNTER_TYPE_LAST \
41125 HWRM_CFA_COUNTER_CFG_INPUT_COUNTER_TYPE_MDC
41126 /* Ctx memory handle to be used for the counter. */
41128 /* Counter update cadence hint (only in Push mode). */
41129 uint16_t update_tmr_ms;
41130 /* Total number of entries. */
41131 uint32_t num_entries;
41135 /* hwrm_cfa_counter_cfg_output (size:128b/16B) */
41136 struct hwrm_cfa_counter_cfg_output {
41137 /* The specific error status for the command. */
41138 uint16_t error_code;
41139 /* The HWRM command request type. */
41141 /* The sequence ID from the original command. */
41143 /* The length of the response data in number of bytes. */
41145 uint8_t unused_0[7];
41147 * This field is used in Output records to indicate that the output
41148 * is completely written to RAM. This field should be read as '1'
41149 * to indicate that the output has been completely written.
41150 * When writing a command completion or response to an internal
41151 * processor, the order of writes has to be such that this field is
41157 /***************************
41158 * hwrm_cfa_counter_qstats *
41159 ***************************/
41162 /* hwrm_cfa_counter_qstats_input (size:320b/40B) */
41163 struct hwrm_cfa_counter_qstats_input {
41164 /* The HWRM command request type. */
41167 * The completion ring to send the completion event on. This should
41168 * be the NQ ID returned from the `nq_alloc` HWRM command.
41170 uint16_t cmpl_ring;
41172 * The sequence ID is used by the driver for tracking multiple
41173 * commands. This ID is treated as opaque data by the firmware and
41174 * the value is returned in the `hwrm_resp_hdr` upon completion.
41178 * The target ID of the command:
41179 * * 0x0-0xFFF8 - The function ID
41180 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
41181 * * 0xFFFD - Reserved for user-space HWRM interface
41184 uint16_t target_id;
41186 * A physical address pointer pointing to a host buffer that the
41187 * command's response data will be written. This can be either a host
41188 * physical address (HPA) or a guest physical address (GPA) and must
41189 * point to a physically contiguous block of memory.
41191 uint64_t resp_addr;
41193 /* Enumeration denoting the RX, TX type of the resource. */
41194 #define HWRM_CFA_COUNTER_QSTATS_INPUT_FLAGS_PATH UINT32_C(0x1)
41196 #define HWRM_CFA_COUNTER_QSTATS_INPUT_FLAGS_PATH_TX UINT32_C(0x0)
41198 #define HWRM_CFA_COUNTER_QSTATS_INPUT_FLAGS_PATH_RX UINT32_C(0x1)
41199 #define HWRM_CFA_COUNTER_QSTATS_INPUT_FLAGS_PATH_LAST \
41200 HWRM_CFA_COUNTER_QSTATS_INPUT_FLAGS_PATH_RX
41201 uint16_t counter_type;
41202 uint16_t input_flow_ctx_id;
41203 uint16_t num_entries;
41204 uint16_t delta_time_ms;
41205 uint16_t meter_instance_id;
41206 uint16_t mdc_ctx_id;
41207 uint8_t unused_0[2];
41208 uint64_t expected_count;
41211 /* hwrm_cfa_counter_qstats_output (size:128b/16B) */
41212 struct hwrm_cfa_counter_qstats_output {
41213 /* The specific error status for the command. */
41214 uint16_t error_code;
41215 /* The HWRM command request type. */
41217 /* The sequence ID from the original command. */
41219 /* The length of the response data in number of bytes. */
41221 uint8_t unused_0[7];
41223 * This field is used in Output records to indicate that the output
41224 * is completely written to RAM. This field should be read as '1'
41225 * to indicate that the output has been completely written.
41226 * When writing a command completion or response to an internal
41227 * processor, the order of writes has to be such that this field is
41233 /**********************
41234 * hwrm_cfa_eem_qcaps *
41235 **********************/
41238 /* hwrm_cfa_eem_qcaps_input (size:192b/24B) */
41239 struct hwrm_cfa_eem_qcaps_input {
41240 /* The HWRM command request type. */
41243 * The completion ring to send the completion event on. This should
41244 * be the NQ ID returned from the `nq_alloc` HWRM command.
41246 uint16_t cmpl_ring;
41248 * The sequence ID is used by the driver for tracking multiple
41249 * commands. This ID is treated as opaque data by the firmware and
41250 * the value is returned in the `hwrm_resp_hdr` upon completion.
41254 * The target ID of the command:
41255 * * 0x0-0xFFF8 - The function ID
41256 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
41257 * * 0xFFFD - Reserved for user-space HWRM interface
41260 uint16_t target_id;
41262 * A physical address pointer pointing to a host buffer that the
41263 * command's response data will be written. This can be either a host
41264 * physical address (HPA) or a guest physical address (GPA) and must
41265 * point to a physically contiguous block of memory.
41267 uint64_t resp_addr;
41270 * When set to 1, indicates the configuration will apply to TX flows
41271 * which are to be offloaded.
41272 * Note if this bit is set then the path_rx bit can't be set.
41274 #define HWRM_CFA_EEM_QCAPS_INPUT_FLAGS_PATH_TX \
41277 * When set to 1, indicates the configuration will apply to RX flows
41278 * which are to be offloaded.
41279 * Note if this bit is set then the path_tx bit can't be set.
41281 #define HWRM_CFA_EEM_QCAPS_INPUT_FLAGS_PATH_RX \
41283 /* When set to 1, all offloaded flows will be sent to EEM. */
41284 #define HWRM_CFA_EEM_QCAPS_INPUT_FLAGS_PREFERRED_OFFLOAD \
41289 /* hwrm_cfa_eem_qcaps_output (size:320b/40B) */
41290 struct hwrm_cfa_eem_qcaps_output {
41291 /* The specific error status for the command. */
41292 uint16_t error_code;
41293 /* The HWRM command request type. */
41295 /* The sequence ID from the original command. */
41297 /* The length of the response data in number of bytes. */
41301 * When set to 1, indicates the configuration will apply to TX flows
41302 * which are to be offloaded.
41303 * Note if this bit is set then the path_rx bit can't be set.
41305 #define HWRM_CFA_EEM_QCAPS_OUTPUT_FLAGS_PATH_TX \
41308 * When set to 1, indicates the configuration will apply to RX flows
41309 * which are to be offloaded.
41310 * Note if this bit is set then the path_tx bit can't be set.
41312 #define HWRM_CFA_EEM_QCAPS_OUTPUT_FLAGS_PATH_RX \
41315 * When set to 1, indicates the FW supports the Centralized
41316 * Memory Model. The concept designates one entity for the
41317 * memory allocation while all others ‘subscribe’ to it.
41319 #define HWRM_CFA_EEM_QCAPS_OUTPUT_FLAGS_CENTRALIZED_MEMORY_MODEL_SUPPORTED \
41322 * When set to 1, indicates the FW supports the Detached
41323 * Centralized Memory Model. The memory is allocated and managed
41324 * as a separate entity. All PFs and VFs will be granted direct
41325 * or semi-direct access to the allocated memory while none of
41326 * which can interfere with the management of the memory.
41328 #define HWRM_CFA_EEM_QCAPS_OUTPUT_FLAGS_DETACHED_CENTRALIZED_MEMORY_MODEL_SUPPORTED \
41331 uint32_t supported;
41333 * If set to 1, then EEM KEY0 table is supported using crc32 hash.
41334 * If set to 0, EEM KEY0 table is not supported.
41336 #define HWRM_CFA_EEM_QCAPS_OUTPUT_SUPPORTED_KEY0_TABLE \
41339 * If set to 1, then EEM KEY1 table is supported using lookup3 hash.
41340 * If set to 0, EEM KEY1 table is not supported.
41342 #define HWRM_CFA_EEM_QCAPS_OUTPUT_SUPPORTED_KEY1_TABLE \
41345 * If set to 1, then EEM External Record table is supported.
41346 * If set to 0, EEM External Record table is not supported.
41347 * (This table includes action record, EFC pointers, encap pointers)
41349 #define HWRM_CFA_EEM_QCAPS_OUTPUT_SUPPORTED_EXTERNAL_RECORD_TABLE \
41352 * If set to 1, then EEM External Flow Counters table is supported.
41353 * If set to 0, EEM External Flow Counters table is not supported.
41355 #define HWRM_CFA_EEM_QCAPS_OUTPUT_SUPPORTED_EXTERNAL_FLOW_COUNTERS_TABLE \
41358 * If set to 1, then FID table used for implicit flow flush is
41360 * If set to 0, then FID table used for implicit flow flush is
41363 #define HWRM_CFA_EEM_QCAPS_OUTPUT_SUPPORTED_FID_TABLE \
41366 * The maximum number of entries supported by EEM. When configuring
41367 * the host memory, the number of numbers of entries that can
41369 * 32k, 64k 128k, 256k, 512k, 1M, 2M, 4M, 8M, 32M, 64M, 128M
41371 * Any value that are not these values, the FW will round down to the
41372 * closest support number of entries.
41374 uint32_t max_entries_supported;
41375 /* The entry size in bytes of each entry in the EEM KEY0/KEY1 tables. */
41376 uint16_t key_entry_size;
41377 /* The entry size in bytes of each entry in the EEM RECORD tables. */
41378 uint16_t record_entry_size;
41379 /* The entry size in bytes of each entry in the EEM EFC tables. */
41380 uint16_t efc_entry_size;
41381 /* The FID size in bytes of each entry in the EEM FID tables. */
41382 uint16_t fid_entry_size;
41383 uint8_t unused_1[7];
41385 * This field is used in Output records to indicate that the output
41386 * is completely written to RAM. This field should be read as '1'
41387 * to indicate that the output has been completely written.
41388 * When writing a command completion or response to an internal
41389 * processor, the order of writes has to be such that this field is
41395 /********************
41396 * hwrm_cfa_eem_cfg *
41397 ********************/
41400 /* hwrm_cfa_eem_cfg_input (size:384b/48B) */
41401 struct hwrm_cfa_eem_cfg_input {
41402 /* The HWRM command request type. */
41405 * The completion ring to send the completion event on. This should
41406 * be the NQ ID returned from the `nq_alloc` HWRM command.
41408 uint16_t cmpl_ring;
41410 * The sequence ID is used by the driver for tracking multiple
41411 * commands. This ID is treated as opaque data by the firmware and
41412 * the value is returned in the `hwrm_resp_hdr` upon completion.
41416 * The target ID of the command:
41417 * * 0x0-0xFFF8 - The function ID
41418 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
41419 * * 0xFFFD - Reserved for user-space HWRM interface
41422 uint16_t target_id;
41424 * A physical address pointer pointing to a host buffer that the
41425 * command's response data will be written. This can be either a host
41426 * physical address (HPA) or a guest physical address (GPA) and must
41427 * point to a physically contiguous block of memory.
41429 uint64_t resp_addr;
41432 * When set to 1, indicates the configuration will apply to TX flows
41433 * which are to be offloaded.
41434 * Note if this bit is set then the path_rx bit can't be set.
41436 #define HWRM_CFA_EEM_CFG_INPUT_FLAGS_PATH_TX \
41439 * When set to 1, indicates the configuration will apply to RX flows
41440 * which are to be offloaded.
41441 * Note if this bit is set then the path_tx bit can't be set.
41443 #define HWRM_CFA_EEM_CFG_INPUT_FLAGS_PATH_RX \
41445 /* When set to 1, all offloaded flows will be sent to EEM. */
41446 #define HWRM_CFA_EEM_CFG_INPUT_FLAGS_PREFERRED_OFFLOAD \
41448 /* When set to 1, secondary, 0 means primary. */
41449 #define HWRM_CFA_EEM_CFG_INPUT_FLAGS_SECONDARY_PF \
41452 * Group_id which used by Firmware to identify memory pools belonging
41453 * to certain group.
41458 * Configured EEM with the given number of entries. All the EEM tables
41459 * KEY0, KEY1, RECORD, EFC all have the same number of entries and all
41460 * tables will be configured using this value. Current minimum value
41461 * is 32k. Current maximum value is 128M.
41463 uint32_t num_entries;
41465 /* Configured EEM with the given context if for KEY0 table. */
41466 uint16_t key0_ctx_id;
41467 /* Configured EEM with the given context if for KEY1 table. */
41468 uint16_t key1_ctx_id;
41469 /* Configured EEM with the given context if for RECORD table. */
41470 uint16_t record_ctx_id;
41471 /* Configured EEM with the given context if for EFC table. */
41472 uint16_t efc_ctx_id;
41473 /* Configured EEM with the given context if for EFC table. */
41474 uint16_t fid_ctx_id;
41479 /* hwrm_cfa_eem_cfg_output (size:128b/16B) */
41480 struct hwrm_cfa_eem_cfg_output {
41481 /* The specific error status for the command. */
41482 uint16_t error_code;
41483 /* The HWRM command request type. */
41485 /* The sequence ID from the original command. */
41487 /* The length of the response data in number of bytes. */
41489 uint8_t unused_0[7];
41491 * This field is used in Output records to indicate that the output
41492 * is completely written to RAM. This field should be read as '1'
41493 * to indicate that the output has been completely written.
41494 * When writing a command completion or response to an internal
41495 * processor, the order of writes has to be such that this field is
41501 /*********************
41502 * hwrm_cfa_eem_qcfg *
41503 *********************/
41506 /* hwrm_cfa_eem_qcfg_input (size:192b/24B) */
41507 struct hwrm_cfa_eem_qcfg_input {
41508 /* The HWRM command request type. */
41511 * The completion ring to send the completion event on. This should
41512 * be the NQ ID returned from the `nq_alloc` HWRM command.
41514 uint16_t cmpl_ring;
41516 * The sequence ID is used by the driver for tracking multiple
41517 * commands. This ID is treated as opaque data by the firmware and
41518 * the value is returned in the `hwrm_resp_hdr` upon completion.
41522 * The target ID of the command:
41523 * * 0x0-0xFFF8 - The function ID
41524 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
41525 * * 0xFFFD - Reserved for user-space HWRM interface
41528 uint16_t target_id;
41530 * A physical address pointer pointing to a host buffer that the
41531 * command's response data will be written. This can be either a host
41532 * physical address (HPA) or a guest physical address (GPA) and must
41533 * point to a physically contiguous block of memory.
41535 uint64_t resp_addr;
41537 /* When set to 1, indicates the configuration is the TX flow. */
41538 #define HWRM_CFA_EEM_QCFG_INPUT_FLAGS_PATH_TX UINT32_C(0x1)
41539 /* When set to 1, indicates the configuration is the RX flow. */
41540 #define HWRM_CFA_EEM_QCFG_INPUT_FLAGS_PATH_RX UINT32_C(0x2)
41544 /* hwrm_cfa_eem_qcfg_output (size:256b/32B) */
41545 struct hwrm_cfa_eem_qcfg_output {
41546 /* The specific error status for the command. */
41547 uint16_t error_code;
41548 /* The HWRM command request type. */
41550 /* The sequence ID from the original command. */
41552 /* The length of the response data in number of bytes. */
41555 /* When set to 1, indicates the configuration is the TX flow. */
41556 #define HWRM_CFA_EEM_QCFG_OUTPUT_FLAGS_PATH_TX \
41558 /* When set to 1, indicates the configuration is the RX flow. */
41559 #define HWRM_CFA_EEM_QCFG_OUTPUT_FLAGS_PATH_RX \
41561 /* When set to 1, all offloaded flows will be sent to EEM. */
41562 #define HWRM_CFA_EEM_QCFG_OUTPUT_FLAGS_PREFERRED_OFFLOAD \
41564 /* The number of entries the FW has configured for EEM. */
41565 uint32_t num_entries;
41566 /* Configured EEM with the given context if for KEY0 table. */
41567 uint16_t key0_ctx_id;
41568 /* Configured EEM with the given context if for KEY1 table. */
41569 uint16_t key1_ctx_id;
41570 /* Configured EEM with the given context if for RECORD table. */
41571 uint16_t record_ctx_id;
41572 /* Configured EEM with the given context if for EFC table. */
41573 uint16_t efc_ctx_id;
41574 /* Configured EEM with the given context if for EFC table. */
41575 uint16_t fid_ctx_id;
41576 uint8_t unused_2[5];
41578 * This field is used in Output records to indicate that the output
41579 * is completely written to RAM. This field should be read as '1'
41580 * to indicate that the output has been completely written.
41581 * When writing a command completion or response to an internal
41582 * processor, the order of writes has to be such that this field is
41588 /*******************
41589 * hwrm_cfa_eem_op *
41590 *******************/
41593 /* hwrm_cfa_eem_op_input (size:192b/24B) */
41594 struct hwrm_cfa_eem_op_input {
41595 /* The HWRM command request type. */
41598 * The completion ring to send the completion event on. This should
41599 * be the NQ ID returned from the `nq_alloc` HWRM command.
41601 uint16_t cmpl_ring;
41603 * The sequence ID is used by the driver for tracking multiple
41604 * commands. This ID is treated as opaque data by the firmware and
41605 * the value is returned in the `hwrm_resp_hdr` upon completion.
41609 * The target ID of the command:
41610 * * 0x0-0xFFF8 - The function ID
41611 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
41612 * * 0xFFFD - Reserved for user-space HWRM interface
41615 uint16_t target_id;
41617 * A physical address pointer pointing to a host buffer that the
41618 * command's response data will be written. This can be either a host
41619 * physical address (HPA) or a guest physical address (GPA) and must
41620 * point to a physically contiguous block of memory.
41622 uint64_t resp_addr;
41625 * When set to 1, indicates the host memory which is passed will be
41626 * used for the TX flow offload function specified in fid.
41627 * Note if this bit is set then the path_rx bit can't be set.
41629 #define HWRM_CFA_EEM_OP_INPUT_FLAGS_PATH_TX UINT32_C(0x1)
41631 * When set to 1, indicates the host memory which is passed will be
41632 * used for the RX flow offload function specified in fid.
41633 * Note if this bit is set then the path_tx bit can't be set.
41635 #define HWRM_CFA_EEM_OP_INPUT_FLAGS_PATH_RX UINT32_C(0x2)
41637 /* The number of EEM key table entries to be configured. */
41639 /* This value is reserved and should not be used. */
41640 #define HWRM_CFA_EEM_OP_INPUT_OP_RESERVED UINT32_C(0x0)
41642 * To properly stop EEM and ensure there are no DMA's, the caller
41643 * must disable EEM for the given PF, using this call. This will
41644 * safely disable EEM and ensure that all DMA'ed to the
41645 * keys/records/efc have been completed.
41647 #define HWRM_CFA_EEM_OP_INPUT_OP_EEM_DISABLE UINT32_C(0x1)
41649 * Once the EEM host memory has been configured, EEM options have
41650 * been configured. Then the caller should enable EEM for the given
41651 * PF. Note once this call has been made, then the EEM mechanism
41652 * will be active and DMA's will occur as packets are processed.
41654 #define HWRM_CFA_EEM_OP_INPUT_OP_EEM_ENABLE UINT32_C(0x2)
41656 * Clear EEM settings for the given PF so that the register values
41657 * are reset back to there initial state.
41659 #define HWRM_CFA_EEM_OP_INPUT_OP_EEM_CLEANUP UINT32_C(0x3)
41660 #define HWRM_CFA_EEM_OP_INPUT_OP_LAST \
41661 HWRM_CFA_EEM_OP_INPUT_OP_EEM_CLEANUP
41664 /* hwrm_cfa_eem_op_output (size:128b/16B) */
41665 struct hwrm_cfa_eem_op_output {
41666 /* The specific error status for the command. */
41667 uint16_t error_code;
41668 /* The HWRM command request type. */
41670 /* The sequence ID from the original command. */
41672 /* The length of the response data in number of bytes. */
41674 uint8_t unused_0[7];
41676 * This field is used in Output records to indicate that the output
41677 * is completely written to RAM. This field should be read as '1'
41678 * to indicate that the output has been completely written.
41679 * When writing a command completion or response to an internal
41680 * processor, the order of writes has to be such that this field is
41686 /********************************
41687 * hwrm_cfa_adv_flow_mgnt_qcaps *
41688 ********************************/
41691 /* hwrm_cfa_adv_flow_mgnt_qcaps_input (size:256b/32B) */
41692 struct hwrm_cfa_adv_flow_mgnt_qcaps_input {
41693 /* The HWRM command request type. */
41696 * The completion ring to send the completion event on. This should
41697 * be the NQ ID returned from the `nq_alloc` HWRM command.
41699 uint16_t cmpl_ring;
41701 * The sequence ID is used by the driver for tracking multiple
41702 * commands. This ID is treated as opaque data by the firmware and
41703 * the value is returned in the `hwrm_resp_hdr` upon completion.
41707 * The target ID of the command:
41708 * * 0x0-0xFFF8 - The function ID
41709 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
41710 * * 0xFFFD - Reserved for user-space HWRM interface
41713 uint16_t target_id;
41715 * A physical address pointer pointing to a host buffer that the
41716 * command's response data will be written. This can be either a host
41717 * physical address (HPA) or a guest physical address (GPA) and must
41718 * point to a physically contiguous block of memory.
41720 uint64_t resp_addr;
41721 uint32_t unused_0[4];
41724 /* hwrm_cfa_adv_flow_mgnt_qcaps_output (size:128b/16B) */
41725 struct hwrm_cfa_adv_flow_mgnt_qcaps_output {
41726 /* The specific error status for the command. */
41727 uint16_t error_code;
41728 /* The HWRM command request type. */
41730 /* The sequence ID from the original command. */
41732 /* The length of the response data in number of bytes. */
41736 * Value of 1 to indicate firmware support 16-bit flow handle.
41737 * Value of 0 to indicate firmware not support 16-bit flow handle.
41739 #define HWRM_CFA_ADV_FLOW_MGNT_QCAPS_OUTPUT_FLAGS_FLOW_HND_16BIT_SUPPORTED \
41742 * Value of 1 to indicate firmware support 64-bit flow handle.
41743 * Value of 0 to indicate firmware not support 64-bit flow handle.
41745 #define HWRM_CFA_ADV_FLOW_MGNT_QCAPS_OUTPUT_FLAGS_FLOW_HND_64BIT_SUPPORTED \
41748 * Value of 1 to indicate firmware support flow batch delete
41749 * operation through HWRM_CFA_FLOW_FLUSH command.
41750 * Value of 0 to indicate that the firmware does not support flow
41751 * batch delete operation.
41753 #define HWRM_CFA_ADV_FLOW_MGNT_QCAPS_OUTPUT_FLAGS_FLOW_BATCH_DELETE_SUPPORTED \
41756 * Value of 1 to indicate that the firmware support flow reset all
41757 * operation through HWRM_CFA_FLOW_FLUSH command.
41758 * Value of 0 indicates firmware does not support flow reset all
41761 #define HWRM_CFA_ADV_FLOW_MGNT_QCAPS_OUTPUT_FLAGS_FLOW_RESET_ALL_SUPPORTED \
41764 * Value of 1 to indicate that firmware supports use of FID as
41765 * dest_id in HWRM_CFA_NTUPLE_ALLOC/CFG commands.
41766 * Value of 0 indicates firmware does not support use of FID as
41769 #define HWRM_CFA_ADV_FLOW_MGNT_QCAPS_OUTPUT_FLAGS_NTUPLE_FLOW_DEST_FUNC_SUPPORTED \
41772 * Value of 1 to indicate that firmware supports TX EEM flows.
41773 * Value of 0 indicates firmware does not support TX EEM flows.
41775 #define HWRM_CFA_ADV_FLOW_MGNT_QCAPS_OUTPUT_FLAGS_TX_EEM_FLOW_SUPPORTED \
41778 * Value of 1 to indicate that firmware supports RX EEM flows.
41779 * Value of 0 indicates firmware does not support RX EEM flows.
41781 #define HWRM_CFA_ADV_FLOW_MGNT_QCAPS_OUTPUT_FLAGS_RX_EEM_FLOW_SUPPORTED \
41784 * Value of 1 to indicate that firmware supports the dynamic
41785 * allocation of an on-chip flow counter which can be used for EEM
41786 * flows. Value of 0 indicates firmware does not support the dynamic
41787 * allocation of an on-chip flow counter.
41789 #define HWRM_CFA_ADV_FLOW_MGNT_QCAPS_OUTPUT_FLAGS_FLOW_COUNTER_ALLOC_SUPPORTED \
41792 * Value of 1 to indicate that firmware supports setting of
41793 * rfs_ring_tbl_idx in HWRM_CFA_NTUPLE_ALLOC command.
41794 * Value of 0 indicates firmware does not support rfs_ring_tbl_idx.
41796 #define HWRM_CFA_ADV_FLOW_MGNT_QCAPS_OUTPUT_FLAGS_RFS_RING_TBL_IDX_SUPPORTED \
41799 * Value of 1 to indicate that firmware supports untagged matching
41800 * criteria on HWRM_CFA_L2_FILTER_ALLOC command. Value of 0
41801 * indicates firmware does not support untagged matching.
41803 #define HWRM_CFA_ADV_FLOW_MGNT_QCAPS_OUTPUT_FLAGS_UNTAGGED_VLAN_SUPPORTED \
41806 * Value of 1 to indicate that firmware supports XDP filter. Value
41807 * of 0 indicates firmware does not support XDP filter.
41809 #define HWRM_CFA_ADV_FLOW_MGNT_QCAPS_OUTPUT_FLAGS_XDP_SUPPORTED \
41812 * Value of 1 to indicate that the firmware support L2 header source
41813 * fields matching criteria on HWRM_CFA_L2_FILTER_ALLOC command.
41814 * Value of 0 indicates firmware does not support L2 header source
41817 #define HWRM_CFA_ADV_FLOW_MGNT_QCAPS_OUTPUT_FLAGS_L2_HEADER_SOURCE_FIELDS_SUPPORTED \
41820 * If set to 1, firmware is capable of supporting ARP ethertype as
41821 * matching criteria for HWRM_CFA_NTUPLE_FILTER_ALLOC command on the
41822 * RX direction. By default, this flag should be 0 for older version
41825 #define HWRM_CFA_ADV_FLOW_MGNT_QCAPS_OUTPUT_FLAGS_NTUPLE_FLOW_RX_ARP_SUPPORTED \
41828 * Value of 1 to indicate that firmware supports setting of
41829 * rfs_ring_tbl_idx in dst_id field of the HWRM_CFA_NTUPLE_ALLOC
41830 * command. Value of 0 indicates firmware does not support
41831 * rfs_ring_tbl_idx in dst_id field.
41833 #define HWRM_CFA_ADV_FLOW_MGNT_QCAPS_OUTPUT_FLAGS_RFS_RING_TBL_IDX_V2_SUPPORTED \
41836 * If set to 1, firmware is capable of supporting IPv4/IPv6 as
41837 * ethertype in HWRM_CFA_NTUPLE_FILTER_ALLOC command on the RX
41838 * direction. By default, this flag should be 0 for older version
41841 #define HWRM_CFA_ADV_FLOW_MGNT_QCAPS_OUTPUT_FLAGS_NTUPLE_FLOW_RX_ETHERTYPE_IP_SUPPORTED \
41844 * When this bit is '1', it indicates that core firmware is
41845 * capable of TruFlow. Driver can restrict sending HWRM CFA_FLOW_XXX
41846 * and CFA_ENCAP_XXX, CFA_DECAP_XXX commands.
41848 #define HWRM_CFA_ADV_FLOW_MGNT_QCAPS_OUTPUT_FLAGS_TRUFLOW_CAPABLE \
41851 * If set to 1, firmware is capable of supporting L2/ROCE as
41852 * traffic type in flags field of HWRM_CFA_L2_FILTER_ALLOC command.
41853 * By default, this flag should be 0 for older version of firmware.
41855 #define HWRM_CFA_ADV_FLOW_MGNT_QCAPS_OUTPUT_FLAGS_L2_FILTER_TRAFFIC_TYPE_L2_ROCE_SUPPORTED \
41857 uint8_t unused_0[3];
41859 * This field is used in Output records to indicate that the output
41860 * is completely written to RAM. This field should be read as '1'
41861 * to indicate that the output has been completely written.
41862 * When writing a command completion or response to an internal
41863 * processor, the order of writes has to be such that this field is
41869 /******************
41871 ******************/
41874 /* hwrm_cfa_tflib_input (size:1024b/128B) */
41875 struct hwrm_cfa_tflib_input {
41876 /* The HWRM command request type. */
41879 * The completion ring to send the completion event on. This should
41880 * be the NQ ID returned from the `nq_alloc` HWRM command.
41882 uint16_t cmpl_ring;
41884 * The sequence ID is used by the driver for tracking multiple
41885 * commands. This ID is treated as opaque data by the firmware and
41886 * the value is returned in the `hwrm_resp_hdr` upon completion.
41890 * The target ID of the command:
41891 * * 0x0-0xFFF8 - The function ID
41892 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
41893 * * 0xFFFD - Reserved for user-space HWRM interface
41896 uint16_t target_id;
41898 * A physical address pointer pointing to a host buffer that the
41899 * command's response data will be written. This can be either a host
41900 * physical address (HPA) or a guest physical address (GPA) and must
41901 * point to a physically contiguous block of memory.
41903 uint64_t resp_addr;
41904 /* TFLIB message type. */
41906 /* TFLIB message subtype. */
41907 uint16_t tf_subtype;
41909 uint8_t unused0[4];
41910 /* TFLIB request data. */
41911 uint32_t tf_req[26];
41914 /* hwrm_cfa_tflib_output (size:5632b/704B) */
41915 struct hwrm_cfa_tflib_output {
41916 /* The specific error status for the command. */
41917 uint16_t error_code;
41918 /* The HWRM command request type. */
41920 /* The sequence ID from the original command. */
41922 /* The length of the response data in number of bytes. */
41924 /* TFLIB message type. */
41926 /* TFLIB message subtype. */
41927 uint16_t tf_subtype;
41928 /* TFLIB response code */
41929 uint32_t tf_resp_code;
41930 /* TFLIB response data. */
41931 uint32_t tf_resp[170];
41933 uint8_t unused1[7];
41935 * This field is used in Output records to indicate that the output
41936 * is completely written to RAM. This field should be read as '1'
41937 * to indicate that the output has been completely written.
41938 * When writing a command completion or response to an internal
41939 * processor, the order of writes has to be such that this field is
41950 /* hwrm_tf_input (size:1024b/128B) */
41951 struct hwrm_tf_input {
41952 /* The HWRM command request type. */
41955 * The completion ring to send the completion event on. This should
41956 * be the NQ ID returned from the `nq_alloc` HWRM command.
41958 uint16_t cmpl_ring;
41960 * The sequence ID is used by the driver for tracking multiple
41961 * commands. This ID is treated as opaque data by the firmware and
41962 * the value is returned in the `hwrm_resp_hdr` upon completion.
41966 * The target ID of the command:
41967 * * 0x0-0xFFF8 - The function ID
41968 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
41969 * * 0xFFFD - Reserved for user-space HWRM interface
41972 uint16_t target_id;
41974 * A physical address pointer pointing to a host buffer that the
41975 * command's response data will be written. This can be either a host
41976 * physical address (HPA) or a guest physical address (GPA) and must
41977 * point to a physically contiguous block of memory.
41979 uint64_t resp_addr;
41980 /* TF message type. */
41982 /* TF message subtype. */
41985 uint8_t unused0[4];
41986 /* TF request data. */
41990 /* hwrm_tf_output (size:5632b/704B) */
41991 struct hwrm_tf_output {
41992 /* The specific error status for the command. */
41993 uint16_t error_code;
41994 /* The HWRM command request type. */
41996 /* The sequence ID from the original command. */
41998 /* The length of the response data in number of bytes. */
42000 /* TF message type. */
42002 /* TF message subtype. */
42004 /* TF response code */
42005 uint32_t resp_code;
42006 /* TF response data. */
42007 uint32_t resp[170];
42009 uint8_t unused1[7];
42011 * This field is used in Output records to indicate that the
42012 * output is completely written to RAM. This field should be
42013 * read as '1' to indicate that the output has been
42014 * completely written. When writing a command completion or
42015 * response to an internal processor, the order of writes has
42016 * to be such that this field is written last.
42021 /***********************
42022 * hwrm_tf_version_get *
42023 ***********************/
42026 /* hwrm_tf_version_get_input (size:128b/16B) */
42027 struct hwrm_tf_version_get_input {
42028 /* The HWRM command request type. */
42031 * The completion ring to send the completion event on. This should
42032 * be the NQ ID returned from the `nq_alloc` HWRM command.
42034 uint16_t cmpl_ring;
42036 * The sequence ID is used by the driver for tracking multiple
42037 * commands. This ID is treated as opaque data by the firmware and
42038 * the value is returned in the `hwrm_resp_hdr` upon completion.
42042 * The target ID of the command:
42043 * * 0x0-0xFFF8 - The function ID
42044 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
42045 * * 0xFFFD - Reserved for user-space HWRM interface
42048 uint16_t target_id;
42050 * A physical address pointer pointing to a host buffer that the
42051 * command's response data will be written. This can be either a host
42052 * physical address (HPA) or a guest physical address (GPA) and must
42053 * point to a physically contiguous block of memory.
42055 uint64_t resp_addr;
42058 /* hwrm_tf_version_get_output (size:128b/16B) */
42059 struct hwrm_tf_version_get_output {
42060 /* The specific error status for the command. */
42061 uint16_t error_code;
42062 /* The HWRM command request type. */
42064 /* The sequence ID from the original command. */
42066 /* The length of the response data in number of bytes. */
42068 /* Version Major number. */
42070 /* Version Minor number. */
42072 /* Version Update number. */
42075 uint8_t unused0[4];
42077 * This field is used in Output records to indicate that the output
42078 * is completely written to RAM. This field should be read as '1'
42079 * to indicate that the output has been completely written.
42080 * When writing a command completion or response to an internal
42081 * processor, the order of writes has to be such that this field is
42087 /************************
42088 * hwrm_tf_session_open *
42089 ************************/
42092 /* hwrm_tf_session_open_input (size:640b/80B) */
42093 struct hwrm_tf_session_open_input {
42094 /* The HWRM command request type. */
42097 * The completion ring to send the completion event on. This should
42098 * be the NQ ID returned from the `nq_alloc` HWRM command.
42100 uint16_t cmpl_ring;
42102 * The sequence ID is used by the driver for tracking multiple
42103 * commands. This ID is treated as opaque data by the firmware and
42104 * the value is returned in the `hwrm_resp_hdr` upon completion.
42108 * The target ID of the command:
42109 * * 0x0-0xFFF8 - The function ID
42110 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
42111 * * 0xFFFD - Reserved for user-space HWRM interface
42114 uint16_t target_id;
42116 * A physical address pointer pointing to a host buffer that the
42117 * command's response data will be written. This can be either a host
42118 * physical address (HPA) or a guest physical address (GPA) and must
42119 * point to a physically contiguous block of memory.
42121 uint64_t resp_addr;
42122 /* Name of the session. */
42123 uint8_t session_name[64];
42126 /* hwrm_tf_session_open_output (size:192b/24B) */
42127 struct hwrm_tf_session_open_output {
42128 /* The specific error status for the command. */
42129 uint16_t error_code;
42130 /* The HWRM command request type. */
42132 /* The sequence ID from the original command. */
42134 /* The length of the response data in number of bytes. */
42137 * Unique session identifier for the session created by the
42140 uint32_t fw_session_id;
42142 * Unique session client identifier for the first client on
42143 * the newly created session.
42145 uint32_t fw_session_client_id;
42149 uint8_t unused1[3];
42151 * This field is used in Output records to indicate that the output
42152 * is completely written to RAM. This field should be read as '1'
42153 * to indicate that the output has been completely written.
42154 * When writing a command completion or response to an internal
42155 * processor, the order of writes has to be such that this field is
42161 /**************************
42162 * hwrm_tf_session_attach *
42163 **************************/
42166 /* hwrm_tf_session_attach_input (size:704b/88B) */
42167 struct hwrm_tf_session_attach_input {
42168 /* The HWRM command request type. */
42171 * The completion ring to send the completion event on. This should
42172 * be the NQ ID returned from the `nq_alloc` HWRM command.
42174 uint16_t cmpl_ring;
42176 * The sequence ID is used by the driver for tracking multiple
42177 * commands. This ID is treated as opaque data by the firmware and
42178 * the value is returned in the `hwrm_resp_hdr` upon completion.
42182 * The target ID of the command:
42183 * * 0x0-0xFFF8 - The function ID
42184 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
42185 * * 0xFFFD - Reserved for user-space HWRM interface
42188 uint16_t target_id;
42190 * A physical address pointer pointing to a host buffer that the
42191 * command's response data will be written. This can be either a host
42192 * physical address (HPA) or a guest physical address (GPA) and must
42193 * point to a physically contiguous block of memory.
42195 uint64_t resp_addr;
42197 * Unique session identifier for the session that the attach
42198 * request want to attach to. This value originates from the
42199 * shared session memory that the attach request opened by
42200 * way of the 'attach name' that was passed in to the core
42202 * The fw_session_id of the attach session includes PCIe bus
42203 * info to distinguish the PF and session info to identify
42204 * the associated TruFlow session.
42206 uint32_t attach_fw_session_id;
42209 /* Name of the session it self. */
42210 uint8_t session_name[64];
42213 /* hwrm_tf_session_attach_output (size:128b/16B) */
42214 struct hwrm_tf_session_attach_output {
42215 /* The specific error status for the command. */
42216 uint16_t error_code;
42217 /* The HWRM command request type. */
42219 /* The sequence ID from the original command. */
42221 /* The length of the response data in number of bytes. */
42224 * Unique session identifier for the session created by the
42225 * firmware. It includes PCIe bus info to distinguish the PF
42226 * and session info to identify the associated TruFlow
42227 * session. This fw_session_id is unique to the attach
42230 uint32_t fw_session_id;
42232 uint8_t unused0[3];
42234 * This field is used in Output records to indicate that the output
42235 * is completely written to RAM. This field should be read as '1'
42236 * to indicate that the output has been completely written.
42237 * When writing a command completion or response to an internal
42238 * processor, the order of writes has to be such that this field is
42244 /****************************
42245 * hwrm_tf_session_register *
42246 ****************************/
42249 /* hwrm_tf_session_register_input (size:704b/88B) */
42250 struct hwrm_tf_session_register_input {
42251 /* The HWRM command request type. */
42254 * The completion ring to send the completion event on. This should
42255 * be the NQ ID returned from the `nq_alloc` HWRM command.
42257 uint16_t cmpl_ring;
42259 * The sequence ID is used by the driver for tracking multiple
42260 * commands. This ID is treated as opaque data by the firmware and
42261 * the value is returned in the `hwrm_resp_hdr` upon completion.
42265 * The target ID of the command:
42266 * * 0x0-0xFFF8 - The function ID
42267 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
42268 * * 0xFFFD - Reserved for user-space HWRM interface
42271 uint16_t target_id;
42273 * A physical address pointer pointing to a host buffer that the
42274 * command's response data will be written. This can be either a host
42275 * physical address (HPA) or a guest physical address (GPA) and must
42276 * point to a physically contiguous block of memory.
42278 uint64_t resp_addr;
42280 * Unique session identifier for the session that the
42281 * register request want to create a new client on. This
42282 * value originates from the first open request.
42283 * The fw_session_id of the attach session includes PCIe bus
42284 * info to distinguish the PF and session info to identify
42285 * the associated TruFlow session.
42287 uint32_t fw_session_id;
42290 /* Name of the session client. */
42291 uint8_t session_client_name[64];
42294 /* hwrm_tf_session_register_output (size:128b/16B) */
42295 struct hwrm_tf_session_register_output {
42296 /* The specific error status for the command. */
42297 uint16_t error_code;
42298 /* The HWRM command request type. */
42300 /* The sequence ID from the original command. */
42302 /* The length of the response data in number of bytes. */
42305 * Unique session client identifier for the session created
42306 * by the firmware. It includes the session the client it
42307 * attached to and session client info.
42309 uint32_t fw_session_client_id;
42311 uint8_t unused0[3];
42313 * This field is used in Output records to indicate that the output
42314 * is completely written to RAM. This field should be read as '1'
42315 * to indicate that the output has been completely written.
42316 * When writing a command completion or response to an internal
42317 * processor, the order of writes has to be such that this field is
42323 /******************************
42324 * hwrm_tf_session_unregister *
42325 ******************************/
42328 /* hwrm_tf_session_unregister_input (size:192b/24B) */
42329 struct hwrm_tf_session_unregister_input {
42330 /* The HWRM command request type. */
42333 * The completion ring to send the completion event on. This should
42334 * be the NQ ID returned from the `nq_alloc` HWRM command.
42336 uint16_t cmpl_ring;
42338 * The sequence ID is used by the driver for tracking multiple
42339 * commands. This ID is treated as opaque data by the firmware and
42340 * the value is returned in the `hwrm_resp_hdr` upon completion.
42344 * The target ID of the command:
42345 * * 0x0-0xFFF8 - The function ID
42346 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
42347 * * 0xFFFD - Reserved for user-space HWRM interface
42350 uint16_t target_id;
42352 * A physical address pointer pointing to a host buffer that the
42353 * command's response data will be written. This can be either a host
42354 * physical address (HPA) or a guest physical address (GPA) and must
42355 * point to a physically contiguous block of memory.
42357 uint64_t resp_addr;
42359 * Unique session identifier for the session that the
42360 * unregister request want to close a session client on.
42362 uint32_t fw_session_id;
42364 * Unique session client identifier for the session that the
42365 * unregister request want to close.
42367 uint32_t fw_session_client_id;
42370 /* hwrm_tf_session_unregister_output (size:128b/16B) */
42371 struct hwrm_tf_session_unregister_output {
42372 /* The specific error status for the command. */
42373 uint16_t error_code;
42374 /* The HWRM command request type. */
42376 /* The sequence ID from the original command. */
42378 /* The length of the response data in number of bytes. */
42381 uint8_t unused0[7];
42383 * This field is used in Output records to indicate that the output
42384 * is completely written to RAM. This field should be read as '1'
42385 * to indicate that the output has been completely written.
42386 * When writing a command completion or response to an internal
42387 * processor, the order of writes has to be such that this field is
42393 /*************************
42394 * hwrm_tf_session_close *
42395 *************************/
42398 /* hwrm_tf_session_close_input (size:192b/24B) */
42399 struct hwrm_tf_session_close_input {
42400 /* The HWRM command request type. */
42403 * The completion ring to send the completion event on. This should
42404 * be the NQ ID returned from the `nq_alloc` HWRM command.
42406 uint16_t cmpl_ring;
42408 * The sequence ID is used by the driver for tracking multiple
42409 * commands. This ID is treated as opaque data by the firmware and
42410 * the value is returned in the `hwrm_resp_hdr` upon completion.
42414 * The target ID of the command:
42415 * * 0x0-0xFFF8 - The function ID
42416 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
42417 * * 0xFFFD - Reserved for user-space HWRM interface
42420 uint16_t target_id;
42422 * A physical address pointer pointing to a host buffer that the
42423 * command's response data will be written. This can be either a host
42424 * physical address (HPA) or a guest physical address (GPA) and must
42425 * point to a physically contiguous block of memory.
42427 uint64_t resp_addr;
42428 /* Firmware session id returned when HWRM_TF_SESSION_OPEN is sent. */
42429 uint32_t fw_session_id;
42431 uint8_t unused0[4];
42434 /* hwrm_tf_session_close_output (size:128b/16B) */
42435 struct hwrm_tf_session_close_output {
42436 /* The specific error status for the command. */
42437 uint16_t error_code;
42438 /* The HWRM command request type. */
42440 /* The sequence ID from the original command. */
42442 /* The length of the response data in number of bytes. */
42445 uint8_t unused0[7];
42447 * This field is used in Output records to indicate that the output
42448 * is completely written to RAM. This field should be read as '1'
42449 * to indicate that the output has been completely written.
42450 * When writing a command completion or response to an internal
42451 * processor, the order of writes has to be such that this field
42457 /************************
42458 * hwrm_tf_session_qcfg *
42459 ************************/
42462 /* hwrm_tf_session_qcfg_input (size:192b/24B) */
42463 struct hwrm_tf_session_qcfg_input {
42464 /* The HWRM command request type. */
42467 * The completion ring to send the completion event on. This should
42468 * be the NQ ID returned from the `nq_alloc` HWRM command.
42470 uint16_t cmpl_ring;
42472 * The sequence ID is used by the driver for tracking multiple
42473 * commands. This ID is treated as opaque data by the firmware and
42474 * the value is returned in the `hwrm_resp_hdr` upon completion.
42478 * The target ID of the command:
42479 * * 0x0-0xFFF8 - The function ID
42480 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
42481 * * 0xFFFD - Reserved for user-space HWRM interface
42484 uint16_t target_id;
42486 * A physical address pointer pointing to a host buffer that the
42487 * command's response data will be written. This can be either a host
42488 * physical address (HPA) or a guest physical address (GPA) and must
42489 * point to a physically contiguous block of memory.
42491 uint64_t resp_addr;
42492 /* Firmware session id returned when HWRM_TF_SESSION_OPEN is sent. */
42493 uint32_t fw_session_id;
42495 uint8_t unused0[4];
42498 /* hwrm_tf_session_qcfg_output (size:128b/16B) */
42499 struct hwrm_tf_session_qcfg_output {
42500 /* The specific error status for the command. */
42501 uint16_t error_code;
42502 /* The HWRM command request type. */
42504 /* The sequence ID from the original command. */
42506 /* The length of the response data in number of bytes. */
42508 /* RX action control settings flags. */
42509 uint8_t rx_act_flags;
42511 * A value of 1 in this field indicates that Global Flow ID
42512 * reporting into cfa_code and cfa_metadata is enabled.
42514 #define HWRM_TF_SESSION_QCFG_OUTPUT_RX_ACT_FLAGS_ABCR_GFID_EN \
42517 * A value of 1 in this field indicates that both inner and outer
42518 * are stripped and inner tag is passed.
42521 #define HWRM_TF_SESSION_QCFG_OUTPUT_RX_ACT_FLAGS_ABCR_VTAG_DLT_BOTH \
42524 * A value of 1 in this field indicates that the re-use of
42525 * existing tunnel L2 header SMAC is enabled for
42526 * Non-tunnel L2, L2-L3 and IP-IP tunnel.
42528 #define HWRM_TF_SESSION_QCFG_OUTPUT_RX_ACT_FLAGS_TECT_SMAC_OVR_RUTNSL2 \
42530 /* TX Action control settings flags. */
42531 uint8_t tx_act_flags;
42533 #define HWRM_TF_SESSION_QCFG_OUTPUT_TX_ACT_FLAGS_ABCR_VEB_EN \
42536 * When set to 1 any GRE tunnels will include the
42537 * optional Key field.
42539 #define HWRM_TF_SESSION_QCFG_OUTPUT_TX_ACT_FLAGS_TECT_GRE_SET_K \
42542 * When set to 1, for GRE tunnels, the IPV6 Traffic Class (TC)
42543 * field of the outer header is inherited from the inner header
42544 * (if present) or the fixed value as taken from the encap
42547 #define HWRM_TF_SESSION_QCFG_OUTPUT_TX_ACT_FLAGS_TECT_IPV6_TC_IH \
42550 * When set to 1, for GRE tunnels, the IPV4 Type Of Service (TOS)
42551 * field of the outer header is inherited from the inner header
42552 * (if present) or the fixed value as taken from the encap record.
42554 #define HWRM_TF_SESSION_QCFG_OUTPUT_TX_ACT_FLAGS_TECT_IPV4_TOS_IH \
42557 uint8_t unused0[5];
42559 * This field is used in Output records to indicate that the output
42560 * is completely written to RAM. This field should be read as '1'
42561 * to indicate that the output has been completely written.
42562 * When writing a command completion or response to an internal
42563 * processor, the order of writes has to be such that this field
42569 /******************************
42570 * hwrm_tf_session_resc_qcaps *
42571 ******************************/
42574 /* hwrm_tf_session_resc_qcaps_input (size:256b/32B) */
42575 struct hwrm_tf_session_resc_qcaps_input {
42576 /* The HWRM command request type. */
42579 * The completion ring to send the completion event on. This should
42580 * be the NQ ID returned from the `nq_alloc` HWRM command.
42582 uint16_t cmpl_ring;
42584 * The sequence ID is used by the driver for tracking multiple
42585 * commands. This ID is treated as opaque data by the firmware and
42586 * the value is returned in the `hwrm_resp_hdr` upon completion.
42590 * The target ID of the command:
42591 * * 0x0-0xFFF8 - The function ID
42592 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
42593 * * 0xFFFD - Reserved for user-space HWRM interface
42596 uint16_t target_id;
42598 * A physical address pointer pointing to a host buffer that the
42599 * command's response data will be written. This can be either a host
42600 * physical address (HPA) or a guest physical address (GPA) and must
42601 * point to a physically contiguous block of memory.
42603 uint64_t resp_addr;
42604 /* Firmware session id returned when HWRM_TF_SESSION_OPEN is sent. */
42605 uint32_t fw_session_id;
42606 /* Control flags. */
42608 /* Indicates the flow direction. */
42609 #define HWRM_TF_SESSION_RESC_QCAPS_INPUT_FLAGS_DIR UINT32_C(0x1)
42610 /* If this bit set to 0, then it indicates rx flow. */
42611 #define HWRM_TF_SESSION_RESC_QCAPS_INPUT_FLAGS_DIR_RX UINT32_C(0x0)
42612 /* If this bit is set to 1, then it indicates that tx flow. */
42613 #define HWRM_TF_SESSION_RESC_QCAPS_INPUT_FLAGS_DIR_TX UINT32_C(0x1)
42614 #define HWRM_TF_SESSION_RESC_QCAPS_INPUT_FLAGS_DIR_LAST \
42615 HWRM_TF_SESSION_RESC_QCAPS_INPUT_FLAGS_DIR_TX
42617 * Defines the size of the provided qcaps_addr array
42618 * buffer. The size should be set to the Resource Manager
42619 * provided max number of qcaps entries which is device
42620 * specific. Resource Manager gets the max size from HCAPI
42623 uint16_t qcaps_size;
42625 * This is the DMA address for the qcaps output data array
42626 * buffer. Array is of tf_rm_resc_req_entry type and is
42629 uint64_t qcaps_addr;
42632 /* hwrm_tf_session_resc_qcaps_output (size:192b/24B) */
42633 struct hwrm_tf_session_resc_qcaps_output {
42634 /* The specific error status for the command. */
42635 uint16_t error_code;
42636 /* The HWRM command request type. */
42638 /* The sequence ID from the original command. */
42640 /* The length of the response data in number of bytes. */
42642 /* Control flags. */
42644 /* Session reservation strategy. */
42645 #define HWRM_TF_SESSION_RESC_QCAPS_OUTPUT_FLAGS_SESS_RESV_STRATEGY_MASK \
42647 #define HWRM_TF_SESSION_RESC_QCAPS_OUTPUT_FLAGS_SESS_RESV_STRATEGY_SFT \
42649 /* Static partitioning. */
42650 #define HWRM_TF_SESSION_RESC_QCAPS_OUTPUT_FLAGS_SESS_RESV_STRATEGY_STATIC \
42653 #define HWRM_TF_SESSION_RESC_QCAPS_OUTPUT_FLAGS_SESS_RESV_STRATEGY_1 \
42656 #define HWRM_TF_SESSION_RESC_QCAPS_OUTPUT_FLAGS_SESS_RESV_STRATEGY_2 \
42659 #define HWRM_TF_SESSION_RESC_QCAPS_OUTPUT_FLAGS_SESS_RESV_STRATEGY_3 \
42661 #define HWRM_TF_SESSION_RESC_QCAPS_OUTPUT_FLAGS_SESS_RESV_STRATEGY_LAST \
42662 HWRM_TF_SESSION_RESC_QCAPS_OUTPUT_FLAGS_SESS_RESV_STRATEGY_3
42664 * Size of the returned qcaps_addr data array buffer. The
42665 * value cannot exceed the size defined by the input msg,
42672 uint8_t unused1[7];
42674 * This field is used in Output records to indicate that the output
42675 * is completely written to RAM. This field should be read as '1'
42676 * to indicate that the output has been completely written.
42677 * When writing a command completion or response to an internal
42678 * processor, the order of writes has to be such that this field is
42684 /******************************
42685 * hwrm_tf_session_resc_alloc *
42686 ******************************/
42689 /* hwrm_tf_session_resc_alloc_input (size:320b/40B) */
42690 struct hwrm_tf_session_resc_alloc_input {
42691 /* The HWRM command request type. */
42694 * The completion ring to send the completion event on. This should
42695 * be the NQ ID returned from the `nq_alloc` HWRM command.
42697 uint16_t cmpl_ring;
42699 * The sequence ID is used by the driver for tracking multiple
42700 * commands. This ID is treated as opaque data by the firmware and
42701 * the value is returned in the `hwrm_resp_hdr` upon completion.
42705 * The target ID of the command:
42706 * * 0x0-0xFFF8 - The function ID
42707 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
42708 * * 0xFFFD - Reserved for user-space HWRM interface
42711 uint16_t target_id;
42713 * A physical address pointer pointing to a host buffer that the
42714 * command's response data will be written. This can be either a host
42715 * physical address (HPA) or a guest physical address (GPA) and must
42716 * point to a physically contiguous block of memory.
42718 uint64_t resp_addr;
42719 /* Firmware session id returned when HWRM_TF_SESSION_OPEN is sent. */
42720 uint32_t fw_session_id;
42721 /* Control flags. */
42723 /* Indicates the flow direction. */
42724 #define HWRM_TF_SESSION_RESC_ALLOC_INPUT_FLAGS_DIR UINT32_C(0x1)
42725 /* If this bit set to 0, then it indicates rx flow. */
42726 #define HWRM_TF_SESSION_RESC_ALLOC_INPUT_FLAGS_DIR_RX UINT32_C(0x0)
42727 /* If this bit is set to 1, then it indicates that tx flow. */
42728 #define HWRM_TF_SESSION_RESC_ALLOC_INPUT_FLAGS_DIR_TX UINT32_C(0x1)
42729 #define HWRM_TF_SESSION_RESC_ALLOC_INPUT_FLAGS_DIR_LAST \
42730 HWRM_TF_SESSION_RESC_ALLOC_INPUT_FLAGS_DIR_TX
42732 * Defines the array size of the provided req_addr and
42733 * resv_addr array buffers. Should be set to the number of
42738 * This is the DMA address for the request input data array
42739 * buffer. Array is of tf_rm_resc_req_entry type. Size of the
42740 * array buffer is provided by the 'req_size' field in this
42745 * This is the DMA address for the resc output data array
42746 * buffer. Array is of tf_rm_resc_entry type. Size of the array
42747 * buffer is provided by the 'req_size' field in this
42750 uint64_t resc_addr;
42753 /* hwrm_tf_session_resc_alloc_output (size:128b/16B) */
42754 struct hwrm_tf_session_resc_alloc_output {
42755 /* The specific error status for the command. */
42756 uint16_t error_code;
42757 /* The HWRM command request type. */
42759 /* The sequence ID from the original command. */
42761 /* The length of the response data in number of bytes. */
42764 * Size of the returned tf_rm_resc_entry data array. The value
42765 * cannot exceed the req_size defined by the input msg. The data
42766 * array is returned using the resv_addr specified DMA
42767 * address also provided by the input msg.
42771 uint8_t unused0[5];
42773 * This field is used in Output records to indicate that the output
42774 * is completely written to RAM. This field should be read as '1'
42775 * to indicate that the output has been completely written.
42776 * When writing a command completion or response to an internal
42777 * processor, the order of writes has to be such that this field is
42783 /*****************************
42784 * hwrm_tf_session_resc_free *
42785 *****************************/
42788 /* hwrm_tf_session_resc_free_input (size:256b/32B) */
42789 struct hwrm_tf_session_resc_free_input {
42790 /* The HWRM command request type. */
42793 * The completion ring to send the completion event on. This should
42794 * be the NQ ID returned from the `nq_alloc` HWRM command.
42796 uint16_t cmpl_ring;
42798 * The sequence ID is used by the driver for tracking multiple
42799 * commands. This ID is treated as opaque data by the firmware and
42800 * the value is returned in the `hwrm_resp_hdr` upon completion.
42804 * The target ID of the command:
42805 * * 0x0-0xFFF8 - The function ID
42806 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
42807 * * 0xFFFD - Reserved for user-space HWRM interface
42810 uint16_t target_id;
42812 * A physical address pointer pointing to a host buffer that the
42813 * command's response data will be written. This can be either a host
42814 * physical address (HPA) or a guest physical address (GPA) and must
42815 * point to a physically contiguous block of memory.
42817 uint64_t resp_addr;
42818 /* Firmware session id returned when HWRM_TF_SESSION_OPEN is sent. */
42819 uint32_t fw_session_id;
42820 /* Control flags. */
42822 /* Indicates the flow direction. */
42823 #define HWRM_TF_SESSION_RESC_FREE_INPUT_FLAGS_DIR UINT32_C(0x1)
42824 /* If this bit set to 0, then it indicates rx flow. */
42825 #define HWRM_TF_SESSION_RESC_FREE_INPUT_FLAGS_DIR_RX UINT32_C(0x0)
42826 /* If this bit is set to 1, then it indicates that tx flow. */
42827 #define HWRM_TF_SESSION_RESC_FREE_INPUT_FLAGS_DIR_TX UINT32_C(0x1)
42828 #define HWRM_TF_SESSION_RESC_FREE_INPUT_FLAGS_DIR_LAST \
42829 HWRM_TF_SESSION_RESC_FREE_INPUT_FLAGS_DIR_TX
42831 * Defines the size, in bytes, of the provided free_addr
42834 uint16_t free_size;
42836 * This is the DMA address for the free input data array
42837 * buffer. Array is of tf_rm_resc_entry type. Size of the
42838 * buffer is provided by the 'free_size' field of this
42841 uint64_t free_addr;
42844 /* hwrm_tf_session_resc_free_output (size:128b/16B) */
42845 struct hwrm_tf_session_resc_free_output {
42846 /* The specific error status for the command. */
42847 uint16_t error_code;
42848 /* The HWRM command request type. */
42850 /* The sequence ID from the original command. */
42852 /* The length of the response data in number of bytes. */
42855 uint8_t unused0[7];
42857 * This field is used in Output records to indicate that the output
42858 * is completely written to RAM. This field should be read as '1'
42859 * to indicate that the output has been completely written.
42860 * When writing a command completion or response to an internal
42861 * processor, the order of writes has to be such that this field is
42867 /******************************
42868 * hwrm_tf_session_resc_flush *
42869 ******************************/
42872 /* hwrm_tf_session_resc_flush_input (size:256b/32B) */
42873 struct hwrm_tf_session_resc_flush_input {
42874 /* The HWRM command request type. */
42877 * The completion ring to send the completion event on. This should
42878 * be the NQ ID returned from the `nq_alloc` HWRM command.
42880 uint16_t cmpl_ring;
42882 * The sequence ID is used by the driver for tracking multiple
42883 * commands. This ID is treated as opaque data by the firmware and
42884 * the value is returned in the `hwrm_resp_hdr` upon completion.
42888 * The target ID of the command:
42889 * * 0x0-0xFFF8 - The function ID
42890 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
42891 * * 0xFFFD - Reserved for user-space HWRM interface
42894 uint16_t target_id;
42896 * A physical address pointer pointing to a host buffer that the
42897 * command's response data will be written. This can be either a host
42898 * physical address (HPA) or a guest physical address (GPA) and must
42899 * point to a physically contiguous block of memory.
42901 uint64_t resp_addr;
42902 /* Firmware session id returned when HWRM_TF_SESSION_OPEN is sent. */
42903 uint32_t fw_session_id;
42904 /* Control flags. */
42906 /* Indicates the flow direction. */
42907 #define HWRM_TF_SESSION_RESC_FLUSH_INPUT_FLAGS_DIR UINT32_C(0x1)
42908 /* If this bit set to 0, then it indicates rx flow. */
42909 #define HWRM_TF_SESSION_RESC_FLUSH_INPUT_FLAGS_DIR_RX UINT32_C(0x0)
42910 /* If this bit is set to 1, then it indicates that tx flow. */
42911 #define HWRM_TF_SESSION_RESC_FLUSH_INPUT_FLAGS_DIR_TX UINT32_C(0x1)
42912 #define HWRM_TF_SESSION_RESC_FLUSH_INPUT_FLAGS_DIR_LAST \
42913 HWRM_TF_SESSION_RESC_FLUSH_INPUT_FLAGS_DIR_TX
42915 * Defines the size, in bytes, of the provided flush_addr
42918 uint16_t flush_size;
42920 * This is the DMA address for the flush input data array
42921 * buffer. Array of tf_rm_resc_entry type. Size of the
42922 * buffer is provided by the 'flush_size' field in this
42925 uint64_t flush_addr;
42928 /* hwrm_tf_session_resc_flush_output (size:128b/16B) */
42929 struct hwrm_tf_session_resc_flush_output {
42930 /* The specific error status for the command. */
42931 uint16_t error_code;
42932 /* The HWRM command request type. */
42934 /* The sequence ID from the original command. */
42936 /* The length of the response data in number of bytes. */
42939 uint8_t unused0[7];
42941 * This field is used in Output records to indicate that the output
42942 * is completely written to RAM. This field should be read as '1'
42943 * to indicate that the output has been completely written.
42944 * When writing a command completion or response to an internal
42945 * processor, the order of writes has to be such that this field is
42951 /* TruFlow RM capability of a resource. */
42952 /* tf_rm_resc_req_entry (size:64b/8B) */
42953 struct tf_rm_resc_req_entry {
42954 /* Type of the resource, defined globally in HCAPI RM. */
42956 /* Minimum value. */
42958 /* Maximum value. */
42962 /* TruFlow RM reservation information. */
42963 /* tf_rm_resc_entry (size:64b/8B) */
42964 struct tf_rm_resc_entry {
42965 /* Type of the resource, defined globally in HCAPI RM. */
42967 /* Start offset. */
42969 /* Number of resources. */
42973 /************************
42974 * hwrm_tf_tbl_type_get *
42975 ************************/
42978 /* hwrm_tf_tbl_type_get_input (size:256b/32B) */
42979 struct hwrm_tf_tbl_type_get_input {
42980 /* The HWRM command request type. */
42983 * The completion ring to send the completion event on. This should
42984 * be the NQ ID returned from the `nq_alloc` HWRM command.
42986 uint16_t cmpl_ring;
42988 * The sequence ID is used by the driver for tracking multiple
42989 * commands. This ID is treated as opaque data by the firmware and
42990 * the value is returned in the `hwrm_resp_hdr` upon completion.
42994 * The target ID of the command:
42995 * * 0x0-0xFFF8 - The function ID
42996 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
42997 * * 0xFFFD - Reserved for user-space HWRM interface
43000 uint16_t target_id;
43002 * A physical address pointer pointing to a host buffer that the
43003 * command's response data will be written. This can be either a host
43004 * physical address (HPA) or a guest physical address (GPA) and must
43005 * point to a physically contiguous block of memory.
43007 uint64_t resp_addr;
43008 /* Firmware session id returned when HWRM_TF_SESSION_OPEN is sent. */
43009 uint32_t fw_session_id;
43010 /* Control flags. */
43012 /* Indicates the flow direction. */
43013 #define HWRM_TF_TBL_TYPE_GET_INPUT_FLAGS_DIR UINT32_C(0x1)
43014 /* If this bit set to 0, then it indicates rx flow. */
43015 #define HWRM_TF_TBL_TYPE_GET_INPUT_FLAGS_DIR_RX UINT32_C(0x0)
43016 /* If this bit is set to 1, then it indicates that tx flow. */
43017 #define HWRM_TF_TBL_TYPE_GET_INPUT_FLAGS_DIR_TX UINT32_C(0x1)
43018 #define HWRM_TF_TBL_TYPE_GET_INPUT_FLAGS_DIR_LAST \
43019 HWRM_TF_TBL_TYPE_GET_INPUT_FLAGS_DIR_TX
43021 uint8_t unused0[2];
43023 * Type of the resource, defined globally in the
43024 * hwrm_tf_resc_type enum.
43027 /* Index of the type to retrieve. */
43031 /* hwrm_tf_tbl_type_get_output (size:1216b/152B) */
43032 struct hwrm_tf_tbl_type_get_output {
43033 /* The specific error status for the command. */
43034 uint16_t error_code;
43035 /* The HWRM command request type. */
43037 /* The sequence ID from the original command. */
43039 /* The length of the response data in number of bytes. */
43041 /* Response code. */
43042 uint32_t resp_code;
43043 /* Response size. */
43047 /* Response data. */
43050 uint8_t unused1[7];
43052 * This field is used in Output records to indicate that the output
43053 * is completely written to RAM. This field should be read as '1'
43054 * to indicate that the output has been completely written.
43055 * When writing a command completion or response to an internal
43056 * processor, the order of writes has to be such that this field
43062 /************************
43063 * hwrm_tf_tbl_type_set *
43064 ************************/
43067 /* hwrm_tf_tbl_type_set_input (size:1024b/128B) */
43068 struct hwrm_tf_tbl_type_set_input {
43069 /* The HWRM command request type. */
43072 * The completion ring to send the completion event on. This should
43073 * be the NQ ID returned from the `nq_alloc` HWRM command.
43075 uint16_t cmpl_ring;
43077 * The sequence ID is used by the driver for tracking multiple
43078 * commands. This ID is treated as opaque data by the firmware and
43079 * the value is returned in the `hwrm_resp_hdr` upon completion.
43083 * The target ID of the command:
43084 * * 0x0-0xFFF8 - The function ID
43085 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
43086 * * 0xFFFD - Reserved for user-space HWRM interface
43089 uint16_t target_id;
43091 * A physical address pointer pointing to a host buffer that the
43092 * command's response data will be written. This can be either a host
43093 * physical address (HPA) or a guest physical address (GPA) and must
43094 * point to a physically contiguous block of memory.
43096 uint64_t resp_addr;
43097 /* Firmware session id returned when HWRM_TF_SESSION_OPEN is sent. */
43098 uint32_t fw_session_id;
43099 /* Control flags. */
43101 /* Indicates the flow direction. */
43102 #define HWRM_TF_TBL_TYPE_SET_INPUT_FLAGS_DIR UINT32_C(0x1)
43103 /* If this bit set to 0, then it indicates rx flow. */
43104 #define HWRM_TF_TBL_TYPE_SET_INPUT_FLAGS_DIR_RX UINT32_C(0x0)
43105 /* If this bit is set to 1, then it indicates that tx flow. */
43106 #define HWRM_TF_TBL_TYPE_SET_INPUT_FLAGS_DIR_TX UINT32_C(0x1)
43107 #define HWRM_TF_TBL_TYPE_SET_INPUT_FLAGS_DIR_LAST \
43108 HWRM_TF_TBL_TYPE_SET_INPUT_FLAGS_DIR_TX
43110 uint8_t unused0[2];
43112 * Type of the resource, defined globally in the
43113 * hwrm_tf_resc_type enum.
43116 /* Index of the type to retrieve. */
43118 /* Size of the data to set. */
43121 uint8_t unused1[6];
43122 /* Data to be set. */
43126 /* hwrm_tf_tbl_type_set_output (size:128b/16B) */
43127 struct hwrm_tf_tbl_type_set_output {
43128 /* The specific error status for the command. */
43129 uint16_t error_code;
43130 /* The HWRM command request type. */
43132 /* The sequence ID from the original command. */
43134 /* The length of the response data in number of bytes. */
43137 uint8_t unused0[7];
43139 * This field is used in Output records to indicate that the output
43140 * is completely written to RAM. This field should be read as '1'
43141 * to indicate that the output has been completely written.
43142 * When writing a command completion or response to an internal
43143 * processor, the order of writes has to be such that this field
43149 /**************************
43150 * hwrm_tf_ctxt_mem_alloc *
43151 **************************/
43154 /* hwrm_tf_ctxt_mem_alloc_input (size:192b/24B) */
43155 struct hwrm_tf_ctxt_mem_alloc_input {
43156 /* The HWRM command request type. */
43159 * The completion ring to send the completion event on. This should
43160 * be the NQ ID returned from the `nq_alloc` HWRM command.
43162 uint16_t cmpl_ring;
43164 * The sequence ID is used by the driver for tracking multiple
43165 * commands. This ID is treated as opaque data by the firmware and
43166 * the value is returned in the `hwrm_resp_hdr` upon completion.
43170 * The target ID of the command:
43171 * * 0x0-0xFFF8 - The function ID
43172 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
43173 * * 0xFFFD - Reserved for user-space HWRM interface
43176 uint16_t target_id;
43178 * A physical address pointer pointing to a host buffer that the
43179 * command's response data will be written. This can be either a host
43180 * physical address (HPA) or a guest physical address (GPA) and must
43181 * point to a physically contiguous block of memory.
43183 uint64_t resp_addr;
43184 /* Size in KB of memory to be allocated. */
43186 /* Firmware session id returned when HWRM_TF_SESSION_OPEN is sent. */
43187 uint32_t fw_session_id;
43190 /* hwrm_tf_ctxt_mem_alloc_output (size:192b/24B) */
43191 struct hwrm_tf_ctxt_mem_alloc_output {
43192 /* The specific error status for the command. */
43193 uint16_t error_code;
43194 /* The HWRM command request type. */
43196 /* The sequence ID from the original command. */
43198 /* The length of the response data in number of bytes. */
43200 /* Pointer to the PBL, or PDL depending on number of levels */
43202 /* Size of memory allocated. */
43204 /* Counter PBL indirect levels. */
43205 uint8_t page_level;
43206 /* PBL pointer is physical start address. */
43207 #define HWRM_TF_CTXT_MEM_ALLOC_OUTPUT_PAGE_LEVEL_LVL_0 UINT32_C(0x0)
43208 /* PBL pointer points to PTE table. */
43209 #define HWRM_TF_CTXT_MEM_ALLOC_OUTPUT_PAGE_LEVEL_LVL_1 UINT32_C(0x1)
43211 * PBL pointer points to PDE table with each entry pointing
43214 #define HWRM_TF_CTXT_MEM_ALLOC_OUTPUT_PAGE_LEVEL_LVL_2 UINT32_C(0x2)
43215 #define HWRM_TF_CTXT_MEM_ALLOC_OUTPUT_PAGE_LEVEL_LAST \
43216 HWRM_TF_CTXT_MEM_ALLOC_OUTPUT_PAGE_LEVEL_LVL_2
43219 /* 4KB page size. */
43220 #define HWRM_TF_CTXT_MEM_ALLOC_OUTPUT_PAGE_SIZE_4K UINT32_C(0x0)
43221 /* 8KB page size. */
43222 #define HWRM_TF_CTXT_MEM_ALLOC_OUTPUT_PAGE_SIZE_8K UINT32_C(0x1)
43223 /* 64KB page size. */
43224 #define HWRM_TF_CTXT_MEM_ALLOC_OUTPUT_PAGE_SIZE_64K UINT32_C(0x4)
43225 /* 128KB page size. */
43226 #define HWRM_TF_CTXT_MEM_ALLOC_OUTPUT_PAGE_SIZE_128K UINT32_C(0x5)
43227 /* 256KB page size. */
43228 #define HWRM_TF_CTXT_MEM_ALLOC_OUTPUT_PAGE_SIZE_256K UINT32_C(0x6)
43229 /* 512KB page size. */
43230 #define HWRM_TF_CTXT_MEM_ALLOC_OUTPUT_PAGE_SIZE_512K UINT32_C(0x7)
43231 /* 1MB page size. */
43232 #define HWRM_TF_CTXT_MEM_ALLOC_OUTPUT_PAGE_SIZE_1M UINT32_C(0x8)
43233 /* 2MB page size. */
43234 #define HWRM_TF_CTXT_MEM_ALLOC_OUTPUT_PAGE_SIZE_2M UINT32_C(0x9)
43235 /* 4MB page size. */
43236 #define HWRM_TF_CTXT_MEM_ALLOC_OUTPUT_PAGE_SIZE_4M UINT32_C(0xa)
43237 /* 8MB page size. */
43238 #define HWRM_TF_CTXT_MEM_ALLOC_OUTPUT_PAGE_SIZE_8M UINT32_C(0xb)
43239 /* 1GB page size. */
43240 #define HWRM_TF_CTXT_MEM_ALLOC_OUTPUT_PAGE_SIZE_1G UINT32_C(0x12)
43241 #define HWRM_TF_CTXT_MEM_ALLOC_OUTPUT_PAGE_SIZE_LAST \
43242 HWRM_TF_CTXT_MEM_ALLOC_OUTPUT_PAGE_SIZE_1G
43246 * This field is used in Output records to indicate that the
43247 * output is completely written to RAM. This field should be
43248 * read as '1' to indicate that the output has been
43249 * completely written. When writing a command completion or
43250 * response to an internal processor, the order of writes has
43251 * to be such that this field is written last.
43256 /*************************
43257 * hwrm_tf_ctxt_mem_free *
43258 *************************/
43261 /* hwrm_tf_ctxt_mem_free_input (size:320b/40B) */
43262 struct hwrm_tf_ctxt_mem_free_input {
43263 /* The HWRM command request type. */
43266 * The completion ring to send the completion event on. This should
43267 * be the NQ ID returned from the `nq_alloc` HWRM command.
43269 uint16_t cmpl_ring;
43271 * The sequence ID is used by the driver for tracking multiple
43272 * commands. This ID is treated as opaque data by the firmware and
43273 * the value is returned in the `hwrm_resp_hdr` upon completion.
43277 * The target ID of the command:
43278 * * 0x0-0xFFF8 - The function ID
43279 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
43280 * * 0xFFFD - Reserved for user-space HWRM interface
43283 uint16_t target_id;
43285 * A physical address pointer pointing to a host buffer that the
43286 * command's response data will be written. This can be either a host
43287 * physical address (HPA) or a guest physical address (GPA) and must
43288 * point to a physically contiguous block of memory.
43290 uint64_t resp_addr;
43291 /* Firmware session id returned when HWRM_TF_SESSION_OPEN is sent. */
43292 uint32_t fw_session_id;
43293 /* Counter PBL indirect levels. */
43294 uint8_t page_level;
43295 /* PBL pointer is physical start address. */
43296 #define HWRM_TF_CTXT_MEM_FREE_INPUT_PAGE_LEVEL_LVL_0 UINT32_C(0x0)
43297 /* PBL pointer points to PTE table. */
43298 #define HWRM_TF_CTXT_MEM_FREE_INPUT_PAGE_LEVEL_LVL_1 UINT32_C(0x1)
43300 * PBL pointer points to PDE table with each entry pointing
43303 #define HWRM_TF_CTXT_MEM_FREE_INPUT_PAGE_LEVEL_LVL_2 UINT32_C(0x2)
43304 #define HWRM_TF_CTXT_MEM_FREE_INPUT_PAGE_LEVEL_LAST \
43305 HWRM_TF_CTXT_MEM_FREE_INPUT_PAGE_LEVEL_LVL_2
43308 /* 4KB page size. */
43309 #define HWRM_TF_CTXT_MEM_FREE_INPUT_PAGE_SIZE_4K UINT32_C(0x0)
43310 /* 8KB page size. */
43311 #define HWRM_TF_CTXT_MEM_FREE_INPUT_PAGE_SIZE_8K UINT32_C(0x1)
43312 /* 64KB page size. */
43313 #define HWRM_TF_CTXT_MEM_FREE_INPUT_PAGE_SIZE_64K UINT32_C(0x4)
43314 /* 128KB page size. */
43315 #define HWRM_TF_CTXT_MEM_FREE_INPUT_PAGE_SIZE_128K UINT32_C(0x5)
43316 /* 256KB page size. */
43317 #define HWRM_TF_CTXT_MEM_FREE_INPUT_PAGE_SIZE_256K UINT32_C(0x6)
43318 /* 512KB page size. */
43319 #define HWRM_TF_CTXT_MEM_FREE_INPUT_PAGE_SIZE_512K UINT32_C(0x7)
43320 /* 1MB page size. */
43321 #define HWRM_TF_CTXT_MEM_FREE_INPUT_PAGE_SIZE_1M UINT32_C(0x8)
43322 /* 2MB page size. */
43323 #define HWRM_TF_CTXT_MEM_FREE_INPUT_PAGE_SIZE_2M UINT32_C(0x9)
43324 /* 4MB page size. */
43325 #define HWRM_TF_CTXT_MEM_FREE_INPUT_PAGE_SIZE_4M UINT32_C(0xa)
43326 /* 8MB page size. */
43327 #define HWRM_TF_CTXT_MEM_FREE_INPUT_PAGE_SIZE_8M UINT32_C(0xb)
43328 /* 1GB page size. */
43329 #define HWRM_TF_CTXT_MEM_FREE_INPUT_PAGE_SIZE_1G UINT32_C(0x12)
43330 #define HWRM_TF_CTXT_MEM_FREE_INPUT_PAGE_SIZE_LAST \
43331 HWRM_TF_CTXT_MEM_FREE_INPUT_PAGE_SIZE_1G
43333 uint8_t unused0[2];
43334 /* Pointer to the PBL, or PDL depending on number of levels */
43336 /* Size of memory allocated. */
43339 uint8_t unused1[4];
43342 /* hwrm_tf_ctxt_mem_free_output (size:128b/16B) */
43343 struct hwrm_tf_ctxt_mem_free_output {
43344 /* The specific error status for the command. */
43345 uint16_t error_code;
43346 /* The HWRM command request type. */
43348 /* The sequence ID from the original command. */
43350 /* The length of the response data in number of bytes. */
43353 uint8_t unused0[7];
43355 * This field is used in Output records to indicate that the
43356 * output is completely written to RAM. This field should be
43357 * read as '1' to indicate that the output has been
43358 * completely written. When writing a command completion or
43359 * response to an internal processor, the order of writes has
43360 * to be such that this field is written last.
43365 /*************************
43366 * hwrm_tf_ctxt_mem_rgtr *
43367 *************************/
43370 /* hwrm_tf_ctxt_mem_rgtr_input (size:256b/32B) */
43371 struct hwrm_tf_ctxt_mem_rgtr_input {
43372 /* The HWRM command request type. */
43375 * The completion ring to send the completion event on. This should
43376 * be the NQ ID returned from the `nq_alloc` HWRM command.
43378 uint16_t cmpl_ring;
43380 * The sequence ID is used by the driver for tracking multiple
43381 * commands. This ID is treated as opaque data by the firmware and
43382 * the value is returned in the `hwrm_resp_hdr` upon completion.
43386 * The target ID of the command:
43387 * * 0x0-0xFFF8 - The function ID
43388 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
43389 * * 0xFFFD - Reserved for user-space HWRM interface
43392 uint16_t target_id;
43394 * A physical address pointer pointing to a host buffer that the
43395 * command's response data will be written. This can be either a host
43396 * physical address (HPA) or a guest physical address (GPA) and must
43397 * point to a physically contiguous block of memory.
43399 uint64_t resp_addr;
43400 /* Control flags. */
43402 /* Counter PBL indirect levels. */
43403 uint8_t page_level;
43404 /* PBL pointer is physical start address. */
43405 #define HWRM_TF_CTXT_MEM_RGTR_INPUT_PAGE_LEVEL_LVL_0 UINT32_C(0x0)
43406 /* PBL pointer points to PTE table. */
43407 #define HWRM_TF_CTXT_MEM_RGTR_INPUT_PAGE_LEVEL_LVL_1 UINT32_C(0x1)
43409 * PBL pointer points to PDE table with each entry pointing
43412 #define HWRM_TF_CTXT_MEM_RGTR_INPUT_PAGE_LEVEL_LVL_2 UINT32_C(0x2)
43413 #define HWRM_TF_CTXT_MEM_RGTR_INPUT_PAGE_LEVEL_LAST \
43414 HWRM_TF_CTXT_MEM_RGTR_INPUT_PAGE_LEVEL_LVL_2
43417 /* 4KB page size. */
43418 #define HWRM_TF_CTXT_MEM_RGTR_INPUT_PAGE_SIZE_4K UINT32_C(0x0)
43419 /* 8KB page size. */
43420 #define HWRM_TF_CTXT_MEM_RGTR_INPUT_PAGE_SIZE_8K UINT32_C(0x1)
43421 /* 64KB page size. */
43422 #define HWRM_TF_CTXT_MEM_RGTR_INPUT_PAGE_SIZE_64K UINT32_C(0x4)
43423 /* 128KB page size. */
43424 #define HWRM_TF_CTXT_MEM_RGTR_INPUT_PAGE_SIZE_128K UINT32_C(0x5)
43425 /* 256KB page size. */
43426 #define HWRM_TF_CTXT_MEM_RGTR_INPUT_PAGE_SIZE_256K UINT32_C(0x6)
43427 /* 512KB page size. */
43428 #define HWRM_TF_CTXT_MEM_RGTR_INPUT_PAGE_SIZE_512K UINT32_C(0x7)
43429 /* 1MB page size. */
43430 #define HWRM_TF_CTXT_MEM_RGTR_INPUT_PAGE_SIZE_1M UINT32_C(0x8)
43431 /* 2MB page size. */
43432 #define HWRM_TF_CTXT_MEM_RGTR_INPUT_PAGE_SIZE_2M UINT32_C(0x9)
43433 /* 4MB page size. */
43434 #define HWRM_TF_CTXT_MEM_RGTR_INPUT_PAGE_SIZE_4M UINT32_C(0xa)
43435 /* 8MB page size. */
43436 #define HWRM_TF_CTXT_MEM_RGTR_INPUT_PAGE_SIZE_8M UINT32_C(0xb)
43437 /* 1GB page size. */
43438 #define HWRM_TF_CTXT_MEM_RGTR_INPUT_PAGE_SIZE_1G UINT32_C(0x12)
43439 #define HWRM_TF_CTXT_MEM_RGTR_INPUT_PAGE_SIZE_LAST \
43440 HWRM_TF_CTXT_MEM_RGTR_INPUT_PAGE_SIZE_1G
43441 /* Firmware session id returned when HWRM_TF_SESSION_OPEN is sent. */
43442 uint32_t fw_session_id;
43443 /* Pointer to the PBL, or PDL depending on number of levels */
43447 /* hwrm_tf_ctxt_mem_rgtr_output (size:128b/16B) */
43448 struct hwrm_tf_ctxt_mem_rgtr_output {
43449 /* The specific error status for the command. */
43450 uint16_t error_code;
43451 /* The HWRM command request type. */
43453 /* The sequence ID from the original command. */
43455 /* The length of the response data in number of bytes. */
43458 * Id/Handle to the recently register context memory. This
43459 * handle is passed to the TF session.
43463 uint8_t unused0[5];
43465 * This field is used in Output records to indicate that the
43466 * output is completely written to RAM. This field should be
43467 * read as '1' to indicate that the output has been
43468 * completely written. When writing a command completion or
43469 * response to an internal processor, the order of writes has
43470 * to be such that this field is written last.
43475 /***************************
43476 * hwrm_tf_ctxt_mem_unrgtr *
43477 ***************************/
43480 /* hwrm_tf_ctxt_mem_unrgtr_input (size:192b/24B) */
43481 struct hwrm_tf_ctxt_mem_unrgtr_input {
43482 /* The HWRM command request type. */
43485 * The completion ring to send the completion event on. This should
43486 * be the NQ ID returned from the `nq_alloc` HWRM command.
43488 uint16_t cmpl_ring;
43490 * The sequence ID is used by the driver for tracking multiple
43491 * commands. This ID is treated as opaque data by the firmware and
43492 * the value is returned in the `hwrm_resp_hdr` upon completion.
43496 * The target ID of the command:
43497 * * 0x0-0xFFF8 - The function ID
43498 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
43499 * * 0xFFFD - Reserved for user-space HWRM interface
43502 uint16_t target_id;
43504 * A physical address pointer pointing to a host buffer that the
43505 * command's response data will be written. This can be either a host
43506 * physical address (HPA) or a guest physical address (GPA) and must
43507 * point to a physically contiguous block of memory.
43509 uint64_t resp_addr;
43511 * Id/Handle to the recently register context memory. This
43512 * handle is passed to the TF session.
43516 uint8_t unused0[2];
43517 /* Firmware session id returned when HWRM_TF_SESSION_OPEN is sent. */
43518 uint32_t fw_session_id;
43521 /* hwrm_tf_ctxt_mem_unrgtr_output (size:128b/16B) */
43522 struct hwrm_tf_ctxt_mem_unrgtr_output {
43523 /* The specific error status for the command. */
43524 uint16_t error_code;
43525 /* The HWRM command request type. */
43527 /* The sequence ID from the original command. */
43529 /* The length of the response data in number of bytes. */
43532 uint8_t unused0[7];
43534 * This field is used in Output records to indicate that the
43535 * output is completely written to RAM. This field should be
43536 * read as '1' to indicate that the output has been
43537 * completely written. When writing a command completion or
43538 * response to an internal processor, the order of writes has
43539 * to be such that this field is written last.
43544 /************************
43545 * hwrm_tf_ext_em_qcaps *
43546 ************************/
43549 /* hwrm_tf_ext_em_qcaps_input (size:192b/24B) */
43550 struct hwrm_tf_ext_em_qcaps_input {
43551 /* The HWRM command request type. */
43554 * The completion ring to send the completion event on. This should
43555 * be the NQ ID returned from the `nq_alloc` HWRM command.
43557 uint16_t cmpl_ring;
43559 * The sequence ID is used by the driver for tracking multiple
43560 * commands. This ID is treated as opaque data by the firmware and
43561 * the value is returned in the `hwrm_resp_hdr` upon completion.
43565 * The target ID of the command:
43566 * * 0x0-0xFFF8 - The function ID
43567 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
43568 * * 0xFFFD - Reserved for user-space HWRM interface
43571 uint16_t target_id;
43573 * A physical address pointer pointing to a host buffer that the
43574 * command's response data will be written. This can be either a host
43575 * physical address (HPA) or a guest physical address (GPA) and must
43576 * point to a physically contiguous block of memory.
43578 uint64_t resp_addr;
43579 /* Control flags. */
43581 /* Indicates the flow direction. */
43582 #define HWRM_TF_EXT_EM_QCAPS_INPUT_FLAGS_DIR \
43584 /* If this bit set to 0, then it indicates rx flow. */
43585 #define HWRM_TF_EXT_EM_QCAPS_INPUT_FLAGS_DIR_RX \
43587 /* If this bit is set to 1, then it indicates that tx flow. */
43588 #define HWRM_TF_EXT_EM_QCAPS_INPUT_FLAGS_DIR_TX \
43590 #define HWRM_TF_EXT_EM_QCAPS_INPUT_FLAGS_DIR_LAST \
43591 HWRM_TF_EXT_EM_QCAPS_INPUT_FLAGS_DIR_TX
43592 /* When set to 1, all offloaded flows will be sent to EXT EM. */
43593 #define HWRM_TF_EXT_EM_QCAPS_INPUT_FLAGS_PREFERRED_OFFLOAD \
43595 /* Firmware session id returned when HWRM_TF_SESSION_OPEN is sent. */
43596 uint32_t fw_session_id;
43599 /* hwrm_tf_ext_em_qcaps_output (size:384b/48B) */
43600 struct hwrm_tf_ext_em_qcaps_output {
43601 /* The specific error status for the command. */
43602 uint16_t error_code;
43603 /* The HWRM command request type. */
43605 /* The sequence ID from the original command. */
43607 /* The length of the response data in number of bytes. */
43611 * When set to 1, indicates the FW supports the Centralized
43612 * Memory Model. The concept designates one entity for the
43613 * memory allocation while all others ‘subscribe’ to it.
43615 #define HWRM_TF_EXT_EM_QCAPS_OUTPUT_FLAGS_CENTRALIZED_MEMORY_MODEL_SUPPORTED \
43618 * When set to 1, indicates the FW supports the Detached
43619 * Centralized Memory Model. The memory is allocated and managed
43620 * as a separate entity. All PFs and VFs will be granted direct
43621 * or semi-direct access to the allocated memory while none of
43622 * which can interfere with the management of the memory.
43624 #define HWRM_TF_EXT_EM_QCAPS_OUTPUT_FLAGS_DETACHED_CENTRALIZED_MEMORY_MODEL_SUPPORTED \
43626 /* When set to 1, indicates FW support for host based EEM memory. */
43627 #define HWRM_TF_EXT_EM_QCAPS_OUTPUT_FLAGS_HOST_MEMORY_SUPPORTED \
43629 /* When set to 1, indicates FW support for on-chip based EEM memory. */
43630 #define HWRM_TF_EXT_EM_QCAPS_OUTPUT_FLAGS_FW_MEMORY_SUPPORTED \
43634 /* Support flags. */
43635 uint32_t supported;
43637 * If set to 1, then EXT EM KEY0 table is supported using
43639 * If set to 0, EXT EM KEY0 table is not supported.
43641 #define HWRM_TF_EXT_EM_QCAPS_OUTPUT_SUPPORTED_KEY0_TABLE \
43644 * If set to 1, then EXT EM KEY1 table is supported using
43646 * If set to 0, EXT EM KEY1 table is not supported.
43648 #define HWRM_TF_EXT_EM_QCAPS_OUTPUT_SUPPORTED_KEY1_TABLE \
43651 * If set to 1, then EXT EM External Record table is supported.
43652 * If set to 0, EXT EM External Record table is not
43653 * supported. (This table includes action record, EFC
43654 * pointers, encap pointers)
43656 #define HWRM_TF_EXT_EM_QCAPS_OUTPUT_SUPPORTED_EXTERNAL_RECORD_TABLE \
43659 * If set to 1, then EXT EM External Flow Counters table is
43661 * If set to 0, EXT EM External Flow Counters table is not
43664 #define HWRM_TF_EXT_EM_QCAPS_OUTPUT_SUPPORTED_EXTERNAL_FLOW_COUNTERS_TABLE \
43667 * If set to 1, then FID table used for implicit flow flush
43669 * If set to 0, then FID table used for implicit flow flush
43670 * is not supported.
43672 #define HWRM_TF_EXT_EM_QCAPS_OUTPUT_SUPPORTED_FID_TABLE \
43675 * If set to 1, then table scopes are supported.
43676 * If set to 0, then table scopes are not supported.
43678 #define HWRM_TF_EXT_EM_QCAPS_OUTPUT_SUPPORTED_TBL_SCOPES \
43681 * The maximum number of entries supported by EXT EM. When
43682 * configuring the host memory the number of numbers of
43683 * entries that can supported are -
43684 * 32k, 64k 128k, 256k, 512k, 1M, 2M, 4M, 8M, 32M, 64M,
43686 * Any value that are not these values, the FW will round
43687 * down to the closest support number of entries.
43689 uint32_t max_entries_supported;
43691 * The entry size in bytes of each entry in the EXT EM
43692 * KEY0/KEY1 tables.
43694 uint16_t key_entry_size;
43696 * The entry size in bytes of each entry in the EXT EM RECORD
43699 uint16_t record_entry_size;
43700 /* The entry size in bytes of each entry in the EXT EM EFC tables. */
43701 uint16_t efc_entry_size;
43702 /* The FID size in bytes of each entry in the EXT EM FID tables. */
43703 uint16_t fid_entry_size;
43704 /* Maximum number of ctxt mem allocations allowed. */
43705 uint32_t max_ctxt_mem_allocs;
43707 * Maximum number of static buckets that can be assigned to lookup
43710 uint32_t max_static_buckets;
43712 uint8_t unused1[7];
43714 * This field is used in Output records to indicate that the
43715 * output is completely written to RAM. This field should be
43716 * read as '1' to indicate that the output has been
43717 * completely written. When writing a command completion or
43718 * response to an internal processor, the order of writes has
43719 * to be such that this field is written last.
43724 /*********************
43725 * hwrm_tf_ext_em_op *
43726 *********************/
43729 /* hwrm_tf_ext_em_op_input (size:256b/32B) */
43730 struct hwrm_tf_ext_em_op_input {
43731 /* The HWRM command request type. */
43734 * The completion ring to send the completion event on. This should
43735 * be the NQ ID returned from the `nq_alloc` HWRM command.
43737 uint16_t cmpl_ring;
43739 * The sequence ID is used by the driver for tracking multiple
43740 * commands. This ID is treated as opaque data by the firmware and
43741 * the value is returned in the `hwrm_resp_hdr` upon completion.
43745 * The target ID of the command:
43746 * * 0x0-0xFFF8 - The function ID
43747 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
43748 * * 0xFFFD - Reserved for user-space HWRM interface
43751 uint16_t target_id;
43753 * A physical address pointer pointing to a host buffer that the
43754 * command's response data will be written. This can be either a host
43755 * physical address (HPA) or a guest physical address (GPA) and must
43756 * point to a physically contiguous block of memory.
43758 uint64_t resp_addr;
43759 /* Control flags. */
43761 /* Indicates the flow direction. */
43762 #define HWRM_TF_EXT_EM_OP_INPUT_FLAGS_DIR UINT32_C(0x1)
43763 /* If this bit set to 0, then it indicates rx flow. */
43764 #define HWRM_TF_EXT_EM_OP_INPUT_FLAGS_DIR_RX UINT32_C(0x0)
43765 /* If this bit is set to 1, then it indicates that tx flow. */
43766 #define HWRM_TF_EXT_EM_OP_INPUT_FLAGS_DIR_TX UINT32_C(0x1)
43767 #define HWRM_TF_EXT_EM_OP_INPUT_FLAGS_DIR_LAST \
43768 HWRM_TF_EXT_EM_OP_INPUT_FLAGS_DIR_TX
43771 /* The number of EXT EM key table entries to be configured. */
43773 /* This value is reserved and should not be used. */
43774 #define HWRM_TF_EXT_EM_OP_INPUT_OP_RESERVED UINT32_C(0x0)
43776 * To properly stop EXT EM and ensure there are no DMA's,
43777 * the caller must disable EXT EM for the given PF, using
43778 * this call. This will safely disable EXT EM and ensure
43779 * that all DMA'ed to the keys/records/efc have been
43782 #define HWRM_TF_EXT_EM_OP_INPUT_OP_EXT_EM_DISABLE UINT32_C(0x1)
43784 * Once the EXT EM host memory has been configured, EXT EM
43785 * options have been configured. Then the caller should
43786 * enable EXT EM for the given PF. Note once this call has
43787 * been made, then the EXT EM mechanism will be active and
43788 * DMA's will occur as packets are processed.
43790 #define HWRM_TF_EXT_EM_OP_INPUT_OP_EXT_EM_ENABLE UINT32_C(0x2)
43792 * Clear EXT EM settings for the given PF so that the
43793 * register values are reset back to their initial state.
43795 #define HWRM_TF_EXT_EM_OP_INPUT_OP_EXT_EM_CLEANUP UINT32_C(0x3)
43796 #define HWRM_TF_EXT_EM_OP_INPUT_OP_LAST \
43797 HWRM_TF_EXT_EM_OP_INPUT_OP_EXT_EM_CLEANUP
43800 /* Firmware session id returned when HWRM_TF_SESSION_OPEN is sent. */
43801 uint32_t fw_session_id;
43806 /* hwrm_tf_ext_em_op_output (size:128b/16B) */
43807 struct hwrm_tf_ext_em_op_output {
43808 /* The specific error status for the command. */
43809 uint16_t error_code;
43810 /* The HWRM command request type. */
43812 /* The sequence ID from the original command. */
43814 /* The length of the response data in number of bytes. */
43817 uint8_t unused0[7];
43819 * This field is used in Output records to indicate that the
43820 * output is completely written to RAM. This field should be
43821 * read as '1' to indicate that the output has been
43822 * completely written. When writing a command completion or
43823 * response to an internal processor, the order of writes has
43824 * to be such that this field is written last.
43829 /**********************
43830 * hwrm_tf_ext_em_cfg *
43831 **********************/
43834 /* hwrm_tf_ext_em_cfg_input (size:512b/64B) */
43835 struct hwrm_tf_ext_em_cfg_input {
43836 /* The HWRM command request type. */
43839 * The completion ring to send the completion event on. This should
43840 * be the NQ ID returned from the `nq_alloc` HWRM command.
43842 uint16_t cmpl_ring;
43844 * The sequence ID is used by the driver for tracking multiple
43845 * commands. This ID is treated as opaque data by the firmware and
43846 * the value is returned in the `hwrm_resp_hdr` upon completion.
43850 * The target ID of the command:
43851 * * 0x0-0xFFF8 - The function ID
43852 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
43853 * * 0xFFFD - Reserved for user-space HWRM interface
43856 uint16_t target_id;
43858 * A physical address pointer pointing to a host buffer that the
43859 * command's response data will be written. This can be either a host
43860 * physical address (HPA) or a guest physical address (GPA) and must
43861 * point to a physically contiguous block of memory.
43863 uint64_t resp_addr;
43864 /* Control flags. */
43866 /* Indicates the flow direction. */
43867 #define HWRM_TF_EXT_EM_CFG_INPUT_FLAGS_DIR \
43869 /* If this bit set to 0, then it indicates rx flow. */
43870 #define HWRM_TF_EXT_EM_CFG_INPUT_FLAGS_DIR_RX \
43872 /* If this bit is set to 1, then it indicates that tx flow. */
43873 #define HWRM_TF_EXT_EM_CFG_INPUT_FLAGS_DIR_TX \
43875 #define HWRM_TF_EXT_EM_CFG_INPUT_FLAGS_DIR_LAST \
43876 HWRM_TF_EXT_EM_CFG_INPUT_FLAGS_DIR_TX
43877 /* When set to 1, all offloaded flows will be sent to EXT EM. */
43878 #define HWRM_TF_EXT_EM_CFG_INPUT_FLAGS_PREFERRED_OFFLOAD \
43880 /* When set to 1, secondary, 0 means primary. */
43881 #define HWRM_TF_EXT_EM_CFG_INPUT_FLAGS_SECONDARY_PF \
43884 * Group_id which used by Firmware to identify memory pools belonging
43885 * to certain group.
43889 * Dynamically reconfigure EEM pending cache every 1/10th of second.
43890 * If set to 0 it will disable the EEM HW flush of the pending cache.
43892 uint8_t flush_interval;
43896 * Configured EXT EM with the given number of entries. All
43897 * the EXT EM tables KEY0, KEY1, RECORD, EFC all have the
43898 * same number of entries and all tables will be configured
43899 * using this value. Current minimum value is 32k. Current
43900 * maximum value is 128M.
43902 uint32_t num_entries;
43905 * This bit must be '1' for the group_id field to be
43908 #define HWRM_TF_EXT_EM_CFG_INPUT_ENABLES_GROUP_ID \
43911 * This bit must be '1' for the flush_interval field to be
43914 #define HWRM_TF_EXT_EM_CFG_INPUT_ENABLES_FLUSH_INTERVAL \
43917 * This bit must be '1' for the num_entries field to be
43920 #define HWRM_TF_EXT_EM_CFG_INPUT_ENABLES_NUM_ENTRIES \
43923 * This bit must be '1' for the key0_ctx_id field to be
43926 #define HWRM_TF_EXT_EM_CFG_INPUT_ENABLES_KEY0_CTX_ID \
43929 * This bit must be '1' for the key1_ctx_id field to be
43932 #define HWRM_TF_EXT_EM_CFG_INPUT_ENABLES_KEY1_CTX_ID \
43935 * This bit must be '1' for the record_ctx_id field to be
43938 #define HWRM_TF_EXT_EM_CFG_INPUT_ENABLES_RECORD_CTX_ID \
43941 * This bit must be '1' for the efc_ctx_id field to be
43944 #define HWRM_TF_EXT_EM_CFG_INPUT_ENABLES_EFC_CTX_ID \
43947 * This bit must be '1' for the fid_ctx_id field to be
43950 #define HWRM_TF_EXT_EM_CFG_INPUT_ENABLES_FID_CTX_ID \
43953 * This bit must be '1' for the action_ctx_id field to be
43956 #define HWRM_TF_EXT_EM_CFG_INPUT_ENABLES_ACTION_CTX_ID \
43959 * This bit must be '1' for the action_tbl_scope field to be
43962 #define HWRM_TF_EXT_EM_CFG_INPUT_ENABLES_ACTION_TBL_SCOPE \
43965 * This bit must be '1' for the lkup_ctx_id field to be
43968 #define HWRM_TF_EXT_EM_CFG_INPUT_ENABLES_LKUP_CTX_ID \
43971 * This bit must be '1' for the lkup_tbl_scope field to be
43974 #define HWRM_TF_EXT_EM_CFG_INPUT_ENABLES_LKUP_TBL_SCOPE \
43977 * This bit must be '1' for the lkup_static_buckets field to be
43980 #define HWRM_TF_EXT_EM_CFG_INPUT_ENABLES_LKUP_STATIC_BUCKETS \
43982 /* Configured EXT EM with the given context if for KEY0 table. */
43983 uint16_t key0_ctx_id;
43984 /* Configured EXT EM with the given context if for KEY1 table. */
43985 uint16_t key1_ctx_id;
43986 /* Configured EXT EM with the given context if for RECORD table. */
43987 uint16_t record_ctx_id;
43988 /* Configured EXT EM with the given context if for EFC table. */
43989 uint16_t efc_ctx_id;
43990 /* Configured EXT EM with the given context if for EFC table. */
43991 uint16_t fid_ctx_id;
43992 /* Context id of action table scope. */
43993 uint16_t action_ctx_id;
43994 /* Table scope id used for action record entries. */
43995 uint16_t action_tbl_scope;
43996 /* Context id of lookup table scope. */
43997 uint16_t lkup_ctx_id;
43998 /* Table scope id used for EM lookup entries. */
43999 uint16_t lkup_tbl_scope;
44003 * Number of 32B static buckets to be allocated at the beginning
44006 uint32_t lkup_static_buckets;
44007 /* Firmware session id returned when HWRM_TF_SESSION_OPEN is sent. */
44008 uint32_t fw_session_id;
44013 /* hwrm_tf_ext_em_cfg_output (size:128b/16B) */
44014 struct hwrm_tf_ext_em_cfg_output {
44015 /* The specific error status for the command. */
44016 uint16_t error_code;
44017 /* The HWRM command request type. */
44019 /* The sequence ID from the original command. */
44021 /* The length of the response data in number of bytes. */
44024 uint8_t unused0[7];
44026 * This field is used in Output records to indicate that the
44027 * output is completely written to RAM. This field should be
44028 * read as '1' to indicate that the output has been
44029 * completely written. When writing a command completion or
44030 * response to an internal processor, the order of writes has
44031 * to be such that this field is written last.
44036 /***********************
44037 * hwrm_tf_ext_em_qcfg *
44038 ***********************/
44041 /* hwrm_tf_ext_em_qcfg_input (size:192b/24B) */
44042 struct hwrm_tf_ext_em_qcfg_input {
44043 /* The HWRM command request type. */
44046 * The completion ring to send the completion event on. This should
44047 * be the NQ ID returned from the `nq_alloc` HWRM command.
44049 uint16_t cmpl_ring;
44051 * The sequence ID is used by the driver for tracking multiple
44052 * commands. This ID is treated as opaque data by the firmware and
44053 * the value is returned in the `hwrm_resp_hdr` upon completion.
44057 * The target ID of the command:
44058 * * 0x0-0xFFF8 - The function ID
44059 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
44060 * * 0xFFFD - Reserved for user-space HWRM interface
44063 uint16_t target_id;
44065 * A physical address pointer pointing to a host buffer that the
44066 * command's response data will be written. This can be either a host
44067 * physical address (HPA) or a guest physical address (GPA) and must
44068 * point to a physically contiguous block of memory.
44070 uint64_t resp_addr;
44071 /* Control flags. */
44073 /* Indicates the flow direction. */
44074 #define HWRM_TF_EXT_EM_QCFG_INPUT_FLAGS_DIR UINT32_C(0x1)
44075 /* If this bit set to 0, then it indicates rx flow. */
44076 #define HWRM_TF_EXT_EM_QCFG_INPUT_FLAGS_DIR_RX UINT32_C(0x0)
44077 /* If this bit is set to 1, then it indicates that tx flow. */
44078 #define HWRM_TF_EXT_EM_QCFG_INPUT_FLAGS_DIR_TX UINT32_C(0x1)
44079 #define HWRM_TF_EXT_EM_QCFG_INPUT_FLAGS_DIR_LAST \
44080 HWRM_TF_EXT_EM_QCFG_INPUT_FLAGS_DIR_TX
44081 /* Firmware session id returned when HWRM_TF_SESSION_OPEN is sent. */
44082 uint32_t fw_session_id;
44085 /* hwrm_tf_ext_em_qcfg_output (size:448b/56B) */
44086 struct hwrm_tf_ext_em_qcfg_output {
44087 /* The specific error status for the command. */
44088 uint16_t error_code;
44089 /* The HWRM command request type. */
44091 /* The sequence ID from the original command. */
44093 /* The length of the response data in number of bytes. */
44095 /* Control flags. */
44097 /* Indicates the flow direction. */
44098 #define HWRM_TF_EXT_EM_QCFG_OUTPUT_FLAGS_DIR \
44100 /* If this bit set to 0, then it indicates rx flow. */
44101 #define HWRM_TF_EXT_EM_QCFG_OUTPUT_FLAGS_DIR_RX \
44103 /* If this bit is set to 1, then it indicates that tx flow. */
44104 #define HWRM_TF_EXT_EM_QCFG_OUTPUT_FLAGS_DIR_TX \
44106 #define HWRM_TF_EXT_EM_QCFG_OUTPUT_FLAGS_DIR_LAST \
44107 HWRM_TF_EXT_EM_QCFG_OUTPUT_FLAGS_DIR_TX
44108 /* When set to 1, all offloaded flows will be sent to EXT EM. */
44109 #define HWRM_TF_EXT_EM_QCFG_OUTPUT_FLAGS_PREFERRED_OFFLOAD \
44111 /* The number of entries the FW has configured for EXT EM. */
44112 uint32_t num_entries;
44113 /* Configured EXT EM with the given context if for KEY0 table. */
44114 uint16_t key0_ctx_id;
44115 /* Configured EXT EM with the given context if for KEY1 table. */
44116 uint16_t key1_ctx_id;
44117 /* Configured EXT EM with the given context if for RECORD table. */
44118 uint16_t record_ctx_id;
44119 /* Configured EXT EM with the given context if for EFC table. */
44120 uint16_t efc_ctx_id;
44121 /* Configured EXT EM with the given context if for EFC table. */
44122 uint16_t fid_ctx_id;
44125 uint32_t supported;
44126 /* This bit must be '1' for the group_id field is set. */
44127 #define HWRM_TF_EXT_EM_QCFG_OUTPUT_SUPPORTED_GROUP_ID \
44129 /* This bit must be '1' for the flush_interval field is set. */
44130 #define HWRM_TF_EXT_EM_QCFG_OUTPUT_SUPPORTED_FLUSH_INTERVAL \
44132 /* This bit must be '1' for the num_entries field is set. */
44133 #define HWRM_TF_EXT_EM_QCFG_OUTPUT_SUPPORTED_NUM_ENTRIES \
44135 /* This bit must be '1' for the key0_ctx_id field is set. */
44136 #define HWRM_TF_EXT_EM_QCFG_OUTPUT_SUPPORTED_KEY0_CTX_ID \
44138 /* This bit must be '1' for the key1_ctx_id field is set. */
44139 #define HWRM_TF_EXT_EM_QCFG_OUTPUT_SUPPORTED_KEY1_CTX_ID \
44141 /* This bit must be '1' for the record_ctx_id field is set. */
44142 #define HWRM_TF_EXT_EM_QCFG_OUTPUT_SUPPORTED_RECORD_CTX_ID \
44144 /* This bit must be '1' for the efc_ctx_id field is set. */
44145 #define HWRM_TF_EXT_EM_QCFG_OUTPUT_SUPPORTED_EFC_CTX_ID \
44147 /* This bit must be '1' for the fid_ctx_id field is set. */
44148 #define HWRM_TF_EXT_EM_QCFG_OUTPUT_SUPPORTED_FID_CTX_ID \
44150 /* This bit must be '1' for the action_ctx_id field is set. */
44151 #define HWRM_TF_EXT_EM_QCFG_OUTPUT_SUPPORTED_ACTION_CTX_ID \
44153 /* This bit must be '1' for the action_tbl_scope field is set. */
44154 #define HWRM_TF_EXT_EM_QCFG_OUTPUT_SUPPORTED_ACTION_TBL_SCOPE \
44156 /* This bit must be '1' for the lkup_ctx_id field is set. */
44157 #define HWRM_TF_EXT_EM_QCFG_OUTPUT_SUPPORTED_LKUP_CTX_ID \
44159 /* This bit must be '1' for the lkup_tbl_scope field is set. */
44160 #define HWRM_TF_EXT_EM_QCFG_OUTPUT_SUPPORTED_LKUP_TBL_SCOPE \
44162 /* This bit must be '1' for the lkup_static_buckets field is set. */
44163 #define HWRM_TF_EXT_EM_QCFG_OUTPUT_SUPPORTED_LKUP_STATIC_BUCKETS \
44166 * Group id is used by firmware to identify memory pools belonging
44167 * to certain group.
44170 /* EEM pending cache flush interval in 1/10th of second. */
44171 uint8_t flush_interval;
44174 /* Context id of action table scope. */
44175 uint16_t action_ctx_id;
44176 /* Table scope id used for action record entries. */
44177 uint16_t action_tbl_scope;
44178 /* Context id of lookup table scope. */
44179 uint16_t lkup_ctx_id;
44180 /* Table scope id used for EM lookup entries. */
44181 uint16_t lkup_tbl_scope;
44183 * Number of 32B static buckets to be allocated at the beginning
44186 uint32_t lkup_static_buckets;
44188 uint8_t unused2[7];
44190 * This field is used in Output records to indicate that the
44191 * output is completely written to RAM. This field should be
44192 * read as '1' to indicate that the output has been
44193 * completely written. When writing a command completion or
44194 * response to an internal processor, the order of writes has
44195 * to be such that this field is written last.
44200 /*********************
44201 * hwrm_tf_em_insert *
44202 *********************/
44205 /* hwrm_tf_em_insert_input (size:832b/104B) */
44206 struct hwrm_tf_em_insert_input {
44207 /* The HWRM command request type. */
44210 * The completion ring to send the completion event on. This should
44211 * be the NQ ID returned from the `nq_alloc` HWRM command.
44213 uint16_t cmpl_ring;
44215 * The sequence ID is used by the driver for tracking multiple
44216 * commands. This ID is treated as opaque data by the firmware and
44217 * the value is returned in the `hwrm_resp_hdr` upon completion.
44221 * The target ID of the command:
44222 * * 0x0-0xFFF8 - The function ID
44223 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
44224 * * 0xFFFD - Reserved for user-space HWRM interface
44227 uint16_t target_id;
44229 * A physical address pointer pointing to a host buffer that the
44230 * command's response data will be written. This can be either a host
44231 * physical address (HPA) or a guest physical address (GPA) and must
44232 * point to a physically contiguous block of memory.
44234 uint64_t resp_addr;
44235 /* Firmware Session Id. */
44236 uint32_t fw_session_id;
44237 /* Control Flags. */
44239 /* Indicates the flow direction. */
44240 #define HWRM_TF_EM_INSERT_INPUT_FLAGS_DIR UINT32_C(0x1)
44241 /* If this bit set to 0, then it indicates rx flow. */
44242 #define HWRM_TF_EM_INSERT_INPUT_FLAGS_DIR_RX UINT32_C(0x0)
44243 /* If this bit is set to 1, then it indicates that tx flow. */
44244 #define HWRM_TF_EM_INSERT_INPUT_FLAGS_DIR_TX UINT32_C(0x1)
44245 #define HWRM_TF_EM_INSERT_INPUT_FLAGS_DIR_LAST \
44246 HWRM_TF_EM_INSERT_INPUT_FLAGS_DIR_TX
44247 /* Reported match strength. */
44249 /* Index to action. */
44250 uint32_t action_ptr;
44251 /* Index of EM record. */
44252 uint32_t em_record_idx;
44253 /* EM Key value. */
44254 uint64_t em_key[8];
44255 /* Number of bits in em_key. */
44256 uint16_t em_key_bitlen;
44258 uint16_t unused0[3];
44261 /* hwrm_tf_em_insert_output (size:128b/16B) */
44262 struct hwrm_tf_em_insert_output {
44263 /* The specific error status for the command. */
44264 uint16_t error_code;
44265 /* The HWRM command request type. */
44267 /* The sequence ID from the original command. */
44269 /* The length of the response data in number of bytes. */
44271 /* EM record pointer index. */
44272 uint16_t rptr_index;
44273 /* EM record offset 0~3. */
44274 uint8_t rptr_entry;
44275 /* Number of word entries consumed by the key. */
44276 uint8_t num_of_entries;
44281 /**************************
44282 * hwrm_tf_em_hash_insert *
44283 **************************/
44286 /* hwrm_tf_em_hash_insert_input (size:1024b/128B) */
44287 struct hwrm_tf_em_hash_insert_input {
44288 /* The HWRM command request type. */
44291 * The completion ring to send the completion event on. This should
44292 * be the NQ ID returned from the `nq_alloc` HWRM command.
44294 uint16_t cmpl_ring;
44296 * The sequence ID is used by the driver for tracking multiple
44297 * commands. This ID is treated as opaque data by the firmware and
44298 * the value is returned in the `hwrm_resp_hdr` upon completion.
44302 * The target ID of the command:
44303 * * 0x0-0xFFF8 - The function ID
44304 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
44305 * * 0xFFFD - Reserved for user-space HWRM interface
44308 uint16_t target_id;
44310 * A physical address pointer pointing to a host buffer that the
44311 * command's response data will be written. This can be either a host
44312 * physical address (HPA) or a guest physical address (GPA) and must
44313 * point to a physically contiguous block of memory.
44315 uint64_t resp_addr;
44316 /* Firmware Session Id. */
44317 uint32_t fw_session_id;
44318 /* Control Flags. */
44320 /* Indicates the flow direction. */
44321 #define HWRM_TF_EM_HASH_INSERT_INPUT_FLAGS_DIR UINT32_C(0x1)
44322 /* If this bit set to 0, then it indicates rx flow. */
44323 #define HWRM_TF_EM_HASH_INSERT_INPUT_FLAGS_DIR_RX UINT32_C(0x0)
44324 /* If this bit is set to 1, then it indicates that tx flow. */
44325 #define HWRM_TF_EM_HASH_INSERT_INPUT_FLAGS_DIR_TX UINT32_C(0x1)
44326 #define HWRM_TF_EM_HASH_INSERT_INPUT_FLAGS_DIR_LAST \
44327 HWRM_TF_EM_HASH_INSERT_INPUT_FLAGS_DIR_TX
44328 /* Number of bits in the EM record. */
44329 uint16_t em_record_size_bits;
44330 /* CRC32 hash of key. */
44331 uint32_t key0_hash;
44332 /* Lookup3 hash of key. */
44333 uint32_t key1_hash;
44334 /* Index of EM record. */
44335 uint32_t em_record_idx;
44339 uint64_t em_record[11];
44342 /* hwrm_tf_em_hash_insert_output (size:128b/16B) */
44343 struct hwrm_tf_em_hash_insert_output {
44344 /* The specific error status for the command. */
44345 uint16_t error_code;
44346 /* The HWRM command request type. */
44348 /* The sequence ID from the original command. */
44350 /* The length of the response data in number of bytes. */
44352 /* EM record pointer index. */
44353 uint16_t rptr_index;
44354 /* EM record offset 0~3. */
44355 uint8_t rptr_entry;
44356 /* Number of word entries consumed by the key. */
44357 uint8_t num_of_entries;
44362 /*********************
44363 * hwrm_tf_em_delete *
44364 *********************/
44367 /* hwrm_tf_em_delete_input (size:832b/104B) */
44368 struct hwrm_tf_em_delete_input {
44369 /* The HWRM command request type. */
44372 * The completion ring to send the completion event on. This should
44373 * be the NQ ID returned from the `nq_alloc` HWRM command.
44375 uint16_t cmpl_ring;
44377 * The sequence ID is used by the driver for tracking multiple
44378 * commands. This ID is treated as opaque data by the firmware and
44379 * the value is returned in the `hwrm_resp_hdr` upon completion.
44383 * The target ID of the command:
44384 * * 0x0-0xFFF8 - The function ID
44385 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
44386 * * 0xFFFD - Reserved for user-space HWRM interface
44389 uint16_t target_id;
44391 * A physical address pointer pointing to a host buffer that the
44392 * command's response data will be written. This can be either a host
44393 * physical address (HPA) or a guest physical address (GPA) and must
44394 * point to a physically contiguous block of memory.
44396 uint64_t resp_addr;
44398 uint32_t fw_session_id;
44399 /* Control flags. */
44401 /* Indicates the flow direction. */
44402 #define HWRM_TF_EM_DELETE_INPUT_FLAGS_DIR UINT32_C(0x1)
44403 /* If this bit set to 0, then it indicates rx flow. */
44404 #define HWRM_TF_EM_DELETE_INPUT_FLAGS_DIR_RX UINT32_C(0x0)
44405 /* If this bit is set to 1, then it indicates that tx flow. */
44406 #define HWRM_TF_EM_DELETE_INPUT_FLAGS_DIR_TX UINT32_C(0x1)
44407 #define HWRM_TF_EM_DELETE_INPUT_FLAGS_DIR_LAST \
44408 HWRM_TF_EM_DELETE_INPUT_FLAGS_DIR_TX
44411 /* EM internal flow hanndle. */
44412 uint64_t flow_handle;
44414 uint64_t em_key[8];
44415 /* Number of bits in em_key. */
44416 uint16_t em_key_bitlen;
44418 uint16_t unused1[3];
44421 /* hwrm_tf_em_delete_output (size:128b/16B) */
44422 struct hwrm_tf_em_delete_output {
44423 /* The specific error status for the command. */
44424 uint16_t error_code;
44425 /* The HWRM command request type. */
44427 /* The sequence ID from the original command. */
44429 /* The length of the response data in number of bytes. */
44431 /* Original stack allocation index. */
44434 uint16_t unused0[3];
44437 /********************
44438 * hwrm_tf_tcam_set *
44439 ********************/
44442 /* hwrm_tf_tcam_set_input (size:1024b/128B) */
44443 struct hwrm_tf_tcam_set_input {
44444 /* The HWRM command request type. */
44447 * The completion ring to send the completion event on. This should
44448 * be the NQ ID returned from the `nq_alloc` HWRM command.
44450 uint16_t cmpl_ring;
44452 * The sequence ID is used by the driver for tracking multiple
44453 * commands. This ID is treated as opaque data by the firmware and
44454 * the value is returned in the `hwrm_resp_hdr` upon completion.
44458 * The target ID of the command:
44459 * * 0x0-0xFFF8 - The function ID
44460 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
44461 * * 0xFFFD - Reserved for user-space HWRM interface
44464 uint16_t target_id;
44466 * A physical address pointer pointing to a host buffer that the
44467 * command's response data will be written. This can be either a host
44468 * physical address (HPA) or a guest physical address (GPA) and must
44469 * point to a physically contiguous block of memory.
44471 uint64_t resp_addr;
44472 /* Firmware session id returned when HWRM_TF_SESSION_OPEN is sent. */
44473 uint32_t fw_session_id;
44474 /* Control flags. */
44476 /* Indicates the flow direction. */
44477 #define HWRM_TF_TCAM_SET_INPUT_FLAGS_DIR UINT32_C(0x1)
44478 /* If this bit set to 0, then it indicates rx flow. */
44479 #define HWRM_TF_TCAM_SET_INPUT_FLAGS_DIR_RX UINT32_C(0x0)
44480 /* If this bit is set to 1, then it indicates that tx flow. */
44481 #define HWRM_TF_TCAM_SET_INPUT_FLAGS_DIR_TX UINT32_C(0x1)
44482 #define HWRM_TF_TCAM_SET_INPUT_FLAGS_DIR_LAST \
44483 HWRM_TF_TCAM_SET_INPUT_FLAGS_DIR_TX
44485 * Indicate device data is being sent via DMA, the device
44486 * data is packing does not change.
44488 #define HWRM_TF_TCAM_SET_INPUT_FLAGS_DMA UINT32_C(0x2)
44490 * TCAM type of the resource, defined globally in the
44491 * hwrm_tf_resc_type enum.
44494 /* Index of TCAM entry. */
44496 /* Number of bytes in the TCAM key. */
44498 /* Number of bytes in the TCAM result. */
44499 uint8_t result_size;
44501 * Offset from which the mask bytes start in the device data
44502 * array, key offset is always 0.
44504 uint8_t mask_offset;
44505 /* Offset from which the result bytes start in the device data array. */
44506 uint8_t result_offset;
44508 uint8_t unused0[6];
44510 * TCAM key located at offset 0, mask located at mask_offsec
44511 * and result at result_offsec for the device.
44513 uint8_t dev_data[88];
44516 /* hwrm_tf_tcam_set_output (size:128b/16B) */
44517 struct hwrm_tf_tcam_set_output {
44518 /* The specific error status for the command. */
44519 uint16_t error_code;
44520 /* The HWRM command request type. */
44522 /* The sequence ID from the original command. */
44524 /* The length of the response data in number of bytes. */
44527 uint8_t unused0[7];
44529 * This field is used in Output records to indicate that the
44530 * output is completely written to RAM. This field should be
44531 * read as '1' to indicate that the output has been
44532 * completely written. When writing a command completion or
44533 * response to an internal processor, the order of writes has
44534 * to be such that this field is written last.
44539 /********************
44540 * hwrm_tf_tcam_get *
44541 ********************/
44544 /* hwrm_tf_tcam_get_input (size:256b/32B) */
44545 struct hwrm_tf_tcam_get_input {
44546 /* The HWRM command request type. */
44549 * The completion ring to send the completion event on. This should
44550 * be the NQ ID returned from the `nq_alloc` HWRM command.
44552 uint16_t cmpl_ring;
44554 * The sequence ID is used by the driver for tracking multiple
44555 * commands. This ID is treated as opaque data by the firmware and
44556 * the value is returned in the `hwrm_resp_hdr` upon completion.
44560 * The target ID of the command:
44561 * * 0x0-0xFFF8 - The function ID
44562 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
44563 * * 0xFFFD - Reserved for user-space HWRM interface
44566 uint16_t target_id;
44568 * A physical address pointer pointing to a host buffer that the
44569 * command's response data will be written. This can be either a host
44570 * physical address (HPA) or a guest physical address (GPA) and must
44571 * point to a physically contiguous block of memory.
44573 uint64_t resp_addr;
44574 /* Firmware session id returned when HWRM_TF_SESSION_OPEN is sent. */
44575 uint32_t fw_session_id;
44576 /* Control flags. */
44578 /* Indicates the flow direction. */
44579 #define HWRM_TF_TCAM_GET_INPUT_FLAGS_DIR UINT32_C(0x1)
44580 /* If this bit set to 0, then it indicates rx flow. */
44581 #define HWRM_TF_TCAM_GET_INPUT_FLAGS_DIR_RX UINT32_C(0x0)
44582 /* If this bit is set to 1, then it indicates that tx flow. */
44583 #define HWRM_TF_TCAM_GET_INPUT_FLAGS_DIR_TX UINT32_C(0x1)
44584 #define HWRM_TF_TCAM_GET_INPUT_FLAGS_DIR_LAST \
44585 HWRM_TF_TCAM_GET_INPUT_FLAGS_DIR_TX
44587 * TCAM type of the resource, defined globally in the
44588 * hwrm_tf_resc_type enum.
44591 /* Index of a TCAM entry. */
44597 /* hwrm_tf_tcam_get_output (size:2368b/296B) */
44598 struct hwrm_tf_tcam_get_output {
44599 /* The specific error status for the command. */
44600 uint16_t error_code;
44601 /* The HWRM command request type. */
44603 /* The sequence ID from the original command. */
44605 /* The length of the response data in number of bytes. */
44607 /* Number of bytes in the TCAM key. */
44609 /* Number of bytes in the TCAM entry. */
44610 uint8_t result_size;
44611 /* Offset from which the mask bytes start in the device data array. */
44612 uint8_t mask_offset;
44613 /* Offset from which the result bytes start in the device data array. */
44614 uint8_t result_offset;
44616 uint8_t unused0[4];
44618 * TCAM key located at offset 0, mask located at mask_offsec
44619 * and result at result_offsec for the device.
44621 uint8_t dev_data[272];
44623 uint8_t unused1[7];
44625 * This field is used in Output records to indicate that the
44626 * output is completely written to RAM. This field should be
44627 * read as '1' to indicate that the output has been
44628 * completely written. When writing a command completion or
44629 * response to an internal processor, the order of writes has
44630 * to be such that this field is written last.
44635 /*********************
44636 * hwrm_tf_tcam_move *
44637 *********************/
44640 /* hwrm_tf_tcam_move_input (size:1024b/128B) */
44641 struct hwrm_tf_tcam_move_input {
44642 /* The HWRM command request type. */
44645 * The completion ring to send the completion event on. This should
44646 * be the NQ ID returned from the `nq_alloc` HWRM command.
44648 uint16_t cmpl_ring;
44650 * The sequence ID is used by the driver for tracking multiple
44651 * commands. This ID is treated as opaque data by the firmware and
44652 * the value is returned in the `hwrm_resp_hdr` upon completion.
44656 * The target ID of the command:
44657 * * 0x0-0xFFF8 - The function ID
44658 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
44659 * * 0xFFFD - Reserved for user-space HWRM interface
44662 uint16_t target_id;
44664 * A physical address pointer pointing to a host buffer that the
44665 * command's response data will be written. This can be either a host
44666 * physical address (HPA) or a guest physical address (GPA) and must
44667 * point to a physically contiguous block of memory.
44669 uint64_t resp_addr;
44670 /* Firmware session id returned when HWRM_TF_SESSION_OPEN is sent. */
44671 uint32_t fw_session_id;
44672 /* Control flags. */
44674 /* Indicates the flow direction. */
44675 #define HWRM_TF_TCAM_MOVE_INPUT_FLAGS_DIR UINT32_C(0x1)
44676 /* If this bit set to 0, then it indicates rx flow. */
44677 #define HWRM_TF_TCAM_MOVE_INPUT_FLAGS_DIR_RX UINT32_C(0x0)
44678 /* If this bit is set to 1, then it indicates that tx flow. */
44679 #define HWRM_TF_TCAM_MOVE_INPUT_FLAGS_DIR_TX UINT32_C(0x1)
44680 #define HWRM_TF_TCAM_MOVE_INPUT_FLAGS_DIR_LAST \
44681 HWRM_TF_TCAM_MOVE_INPUT_FLAGS_DIR_TX
44683 * TCAM type of the resource, defined globally in the
44684 * hwrm_tf_resc_type enum.
44687 /* Number of TCAM index pairs to be swapped for the device. */
44691 /* TCAM index pairs to be swapped for the device. */
44692 uint16_t idx_pairs[48];
44695 /* hwrm_tf_tcam_move_output (size:128b/16B) */
44696 struct hwrm_tf_tcam_move_output {
44697 /* The specific error status for the command. */
44698 uint16_t error_code;
44699 /* The HWRM command request type. */
44701 /* The sequence ID from the original command. */
44703 /* The length of the response data in number of bytes. */
44706 uint8_t unused0[7];
44708 * This field is used in Output records to indicate that the
44709 * output is completely written to RAM. This field should be
44710 * read as '1' to indicate that the output has been
44711 * completely written. When writing a command completion or
44712 * response to an internal processor, the order of writes has
44713 * to be such that this field is written last.
44718 /*********************
44719 * hwrm_tf_tcam_free *
44720 *********************/
44723 /* hwrm_tf_tcam_free_input (size:1024b/128B) */
44724 struct hwrm_tf_tcam_free_input {
44725 /* The HWRM command request type. */
44728 * The completion ring to send the completion event on. This should
44729 * be the NQ ID returned from the `nq_alloc` HWRM command.
44731 uint16_t cmpl_ring;
44733 * The sequence ID is used by the driver for tracking multiple
44734 * commands. This ID is treated as opaque data by the firmware and
44735 * the value is returned in the `hwrm_resp_hdr` upon completion.
44739 * The target ID of the command:
44740 * * 0x0-0xFFF8 - The function ID
44741 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
44742 * * 0xFFFD - Reserved for user-space HWRM interface
44745 uint16_t target_id;
44747 * A physical address pointer pointing to a host buffer that the
44748 * command's response data will be written. This can be either a host
44749 * physical address (HPA) or a guest physical address (GPA) and must
44750 * point to a physically contiguous block of memory.
44752 uint64_t resp_addr;
44753 /* Firmware session id returned when HWRM_TF_SESSION_OPEN is sent. */
44754 uint32_t fw_session_id;
44755 /* Control flags. */
44757 /* Indicates the flow direction. */
44758 #define HWRM_TF_TCAM_FREE_INPUT_FLAGS_DIR UINT32_C(0x1)
44759 /* If this bit set to 0, then it indicates rx flow. */
44760 #define HWRM_TF_TCAM_FREE_INPUT_FLAGS_DIR_RX UINT32_C(0x0)
44761 /* If this bit is set to 1, then it indicates that tx flow. */
44762 #define HWRM_TF_TCAM_FREE_INPUT_FLAGS_DIR_TX UINT32_C(0x1)
44763 #define HWRM_TF_TCAM_FREE_INPUT_FLAGS_DIR_LAST \
44764 HWRM_TF_TCAM_FREE_INPUT_FLAGS_DIR_TX
44766 * TCAM type of the resource, defined globally in the
44767 * hwrm_tf_resc_type enum.
44770 /* Number of TCAM index to be deleted for the device. */
44774 /* TCAM index list to be deleted for the device. */
44775 uint16_t idx_list[48];
44778 /* hwrm_tf_tcam_free_output (size:128b/16B) */
44779 struct hwrm_tf_tcam_free_output {
44780 /* The specific error status for the command. */
44781 uint16_t error_code;
44782 /* The HWRM command request type. */
44784 /* The sequence ID from the original command. */
44786 /* The length of the response data in number of bytes. */
44789 uint8_t unused0[7];
44791 * This field is used in Output records to indicate that the
44792 * output is completely written to RAM. This field should be
44793 * read as '1' to indicate that the output has been
44794 * completely written. When writing a command completion or
44795 * response to an internal processor, the order of writes has
44796 * to be such that this field is written last.
44801 /**************************
44802 * hwrm_tf_global_cfg_set *
44803 **************************/
44806 /* hwrm_tf_global_cfg_set_input (size:448b/56B) */
44807 struct hwrm_tf_global_cfg_set_input {
44808 /* The HWRM command request type. */
44811 * The completion ring to send the completion event on. This should
44812 * be the NQ ID returned from the `nq_alloc` HWRM command.
44814 uint16_t cmpl_ring;
44816 * The sequence ID is used by the driver for tracking multiple
44817 * commands. This ID is treated as opaque data by the firmware and
44818 * the value is returned in the `hwrm_resp_hdr` upon completion.
44822 * The target ID of the command:
44823 * * 0x0-0xFFF8 - The function ID
44824 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
44825 * * 0xFFFD - Reserved for user-space HWRM interface
44828 uint16_t target_id;
44830 * A physical address pointer pointing to a host buffer that the
44831 * command's response data will be written. This can be either a host
44832 * physical address (HPA) or a guest physical address (GPA) and must
44833 * point to a physically contiguous block of memory.
44835 uint64_t resp_addr;
44836 /* Firmware session id returned when HWRM_TF_SESSION_OPEN is sent. */
44837 uint32_t fw_session_id;
44838 /* Control flags. */
44840 /* Indicates the flow direction. */
44841 #define HWRM_TF_GLOBAL_CFG_SET_INPUT_FLAGS_DIR UINT32_C(0x1)
44842 /* If this bit set to 0, then it indicates rx flow. */
44843 #define HWRM_TF_GLOBAL_CFG_SET_INPUT_FLAGS_DIR_RX UINT32_C(0x0)
44844 /* If this bit is set to 1, then it indicates that tx flow. */
44845 #define HWRM_TF_GLOBAL_CFG_SET_INPUT_FLAGS_DIR_TX UINT32_C(0x1)
44846 #define HWRM_TF_GLOBAL_CFG_SET_INPUT_FLAGS_DIR_LAST \
44847 HWRM_TF_GLOBAL_CFG_SET_INPUT_FLAGS_DIR_TX
44848 /* Global Cfg type */
44850 /* Offset of the type */
44852 /* Size of the data to set in bytes */
44855 uint8_t unused0[6];
44858 /* Mask of data to set, 0 indicates no mask */
44862 /* hwrm_tf_global_cfg_set_output (size:128b/16B) */
44863 struct hwrm_tf_global_cfg_set_output {
44864 /* The specific error status for the command. */
44865 uint16_t error_code;
44866 /* The HWRM command request type. */
44868 /* The sequence ID from the original command. */
44870 /* The length of the response data in number of bytes. */
44873 uint8_t unused0[7];
44875 * This field is used in Output records to indicate that the
44876 * output is completely written to RAM. This field should be
44877 * read as '1' to indicate that the output has been
44878 * completely written. When writing a command completion or
44879 * response to an internal processor, the order of writes has
44880 * to be such that this field is written last.
44885 /**************************
44886 * hwrm_tf_global_cfg_get *
44887 **************************/
44890 /* hwrm_tf_global_cfg_get_input (size:320b/40B) */
44891 struct hwrm_tf_global_cfg_get_input {
44892 /* The HWRM command request type. */
44895 * The completion ring to send the completion event on. This should
44896 * be the NQ ID returned from the `nq_alloc` HWRM command.
44898 uint16_t cmpl_ring;
44900 * The sequence ID is used by the driver for tracking multiple
44901 * commands. This ID is treated as opaque data by the firmware and
44902 * the value is returned in the `hwrm_resp_hdr` upon completion.
44906 * The target ID of the command:
44907 * * 0x0-0xFFF8 - The function ID
44908 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
44909 * * 0xFFFD - Reserved for user-space HWRM interface
44912 uint16_t target_id;
44914 * A physical address pointer pointing to a host buffer that the
44915 * command's response data will be written. This can be either a host
44916 * physical address (HPA) or a guest physical address (GPA) and must
44917 * point to a physically contiguous block of memory.
44919 uint64_t resp_addr;
44920 /* Firmware session id returned when HWRM_TF_SESSION_OPEN is sent. */
44921 uint32_t fw_session_id;
44922 /* Control flags. */
44924 /* Indicates the flow direction. */
44925 #define HWRM_TF_GLOBAL_CFG_GET_INPUT_FLAGS_DIR UINT32_C(0x1)
44926 /* If this bit set to 0, then it indicates rx flow. */
44927 #define HWRM_TF_GLOBAL_CFG_GET_INPUT_FLAGS_DIR_RX UINT32_C(0x0)
44928 /* If this bit is set to 1, then it indicates that tx flow. */
44929 #define HWRM_TF_GLOBAL_CFG_GET_INPUT_FLAGS_DIR_TX UINT32_C(0x1)
44930 #define HWRM_TF_GLOBAL_CFG_GET_INPUT_FLAGS_DIR_LAST \
44931 HWRM_TF_GLOBAL_CFG_GET_INPUT_FLAGS_DIR_TX
44932 /* Global Cfg type */
44934 /* Offset of the type */
44936 /* Size of the data to set in bytes */
44939 uint8_t unused0[6];
44942 /* hwrm_tf_global_cfg_get_output (size:256b/32B) */
44943 struct hwrm_tf_global_cfg_get_output {
44944 /* The specific error status for the command. */
44945 uint16_t error_code;
44946 /* The HWRM command request type. */
44948 /* The sequence ID from the original command. */
44950 /* The length of the response data in number of bytes. */
44952 /* Size of the data read in bytes */
44955 uint8_t unused0[6];
44960 /**********************
44961 * hwrm_tf_if_tbl_get *
44962 **********************/
44965 /* hwrm_tf_if_tbl_get_input (size:256b/32B) */
44966 struct hwrm_tf_if_tbl_get_input {
44967 /* The HWRM command request type. */
44970 * The completion ring to send the completion event on. This should
44971 * be the NQ ID returned from the `nq_alloc` HWRM command.
44973 uint16_t cmpl_ring;
44975 * The sequence ID is used by the driver for tracking multiple
44976 * commands. This ID is treated as opaque data by the firmware and
44977 * the value is returned in the `hwrm_resp_hdr` upon completion.
44981 * The target ID of the command:
44982 * * 0x0-0xFFF8 - The function ID
44983 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
44984 * * 0xFFFD - Reserved for user-space HWRM interface
44987 uint16_t target_id;
44989 * A physical address pointer pointing to a host buffer that the
44990 * command's response data will be written. This can be either a host
44991 * physical address (HPA) or a guest physical address (GPA) and must
44992 * point to a physically contiguous block of memory.
44994 uint64_t resp_addr;
44995 /* Firmware session id returned when HWRM_TF_SESSION_OPEN is sent. */
44996 uint32_t fw_session_id;
44997 /* Control flags. */
44999 /* Indicates the flow direction. */
45000 #define HWRM_TF_IF_TBL_GET_INPUT_FLAGS_DIR UINT32_C(0x1)
45001 /* If this bit set to 0, then it indicates rx flow. */
45002 #define HWRM_TF_IF_TBL_GET_INPUT_FLAGS_DIR_RX UINT32_C(0x0)
45003 /* If this bit is set to 1, then it indicates that tx flow. */
45004 #define HWRM_TF_IF_TBL_GET_INPUT_FLAGS_DIR_TX UINT32_C(0x1)
45005 #define HWRM_TF_IF_TBL_GET_INPUT_FLAGS_DIR_LAST \
45006 HWRM_TF_IF_TBL_GET_INPUT_FLAGS_DIR_TX
45007 /* Size of the data to set. */
45010 * Type of the resource, defined globally in the
45011 * hwrm_tf_resc_type enum.
45014 /* Index of the type to retrieve. */
45018 /* hwrm_tf_if_tbl_get_output (size:256b/32B) */
45019 struct hwrm_tf_if_tbl_get_output {
45020 /* The specific error status for the command. */
45021 uint16_t error_code;
45022 /* The HWRM command request type. */
45024 /* The sequence ID from the original command. */
45026 /* The length of the response data in number of bytes. */
45028 /* Response code. */
45029 uint32_t resp_code;
45030 /* Response size. */
45034 /* Response data. */
45037 uint8_t unused1[7];
45039 * This field is used in Output records to indicate that the output
45040 * is completely written to RAM. This field should be read as '1'
45041 * to indicate that the output has been completely written.
45042 * When writing a command completion or response to an internal
45043 * processor, the order of writes has to be such that this field
45049 /***************************
45050 * hwrm_tf_if_tbl_type_set *
45051 ***************************/
45054 /* hwrm_tf_if_tbl_set_input (size:384b/48B) */
45055 struct hwrm_tf_if_tbl_set_input {
45056 /* The HWRM command request type. */
45059 * The completion ring to send the completion event on. This should
45060 * be the NQ ID returned from the `nq_alloc` HWRM command.
45062 uint16_t cmpl_ring;
45064 * The sequence ID is used by the driver for tracking multiple
45065 * commands. This ID is treated as opaque data by the firmware and
45066 * the value is returned in the `hwrm_resp_hdr` upon completion.
45070 * The target ID of the command:
45071 * * 0x0-0xFFF8 - The function ID
45072 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
45073 * * 0xFFFD - Reserved for user-space HWRM interface
45076 uint16_t target_id;
45078 * A physical address pointer pointing to a host buffer that the
45079 * command's response data will be written. This can be either a host
45080 * physical address (HPA) or a guest physical address (GPA) and must
45081 * point to a physically contiguous block of memory.
45083 uint64_t resp_addr;
45084 /* Firmware session id returned when HWRM_TF_SESSION_OPEN is sent. */
45085 uint32_t fw_session_id;
45086 /* Control flags. */
45088 /* Indicates the flow direction. */
45089 #define HWRM_TF_IF_TBL_SET_INPUT_FLAGS_DIR UINT32_C(0x1)
45090 /* If this bit set to 0, then it indicates rx flow. */
45091 #define HWRM_TF_IF_TBL_SET_INPUT_FLAGS_DIR_RX UINT32_C(0x0)
45092 /* If this bit is set to 1, then it indicates that tx flow. */
45093 #define HWRM_TF_IF_TBL_SET_INPUT_FLAGS_DIR_TX UINT32_C(0x1)
45094 #define HWRM_TF_IF_TBL_SET_INPUT_FLAGS_DIR_LAST \
45095 HWRM_TF_IF_TBL_SET_INPUT_FLAGS_DIR_TX
45097 uint8_t unused0[2];
45099 * Type of the resource, defined globally in the
45100 * hwrm_tf_resc_type enum.
45103 /* Index of the type to set. */
45105 /* Size of the data to set. */
45108 uint8_t unused1[6];
45109 /* Data to be set. */
45113 /* hwrm_tf_if_tbl_set_output (size:128b/16B) */
45114 struct hwrm_tf_if_tbl_set_output {
45115 /* The specific error status for the command. */
45116 uint16_t error_code;
45117 /* The HWRM command request type. */
45119 /* The sequence ID from the original command. */
45121 /* The length of the response data in number of bytes. */
45124 uint8_t unused0[7];
45126 * This field is used in Output records to indicate that the output
45127 * is completely written to RAM. This field should be read as '1'
45128 * to indicate that the output has been completely written.
45129 * When writing a command completion or response to an internal
45130 * processor, the order of writes has to be such that this field
45136 /*****************************
45137 * hwrm_tf_tbl_type_bulk_get *
45138 *****************************/
45141 /* hwrm_tf_tbl_type_bulk_get_input (size:384b/48B) */
45142 struct hwrm_tf_tbl_type_bulk_get_input {
45143 /* The HWRM command request type. */
45146 * The completion ring to send the completion event on. This should
45147 * be the NQ ID returned from the `nq_alloc` HWRM command.
45149 uint16_t cmpl_ring;
45151 * The sequence ID is used by the driver for tracking multiple
45152 * commands. This ID is treated as opaque data by the firmware and
45153 * the value is returned in the `hwrm_resp_hdr` upon completion.
45157 * The target ID of the command:
45158 * * 0x0-0xFFF8 - The function ID
45159 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
45160 * * 0xFFFD - Reserved for user-space HWRM interface
45163 uint16_t target_id;
45165 * A physical address pointer pointing to a host buffer that the
45166 * command's response data will be written. This can be either a host
45167 * physical address (HPA) or a guest physical address (GPA) and must
45168 * point to a physically contiguous block of memory.
45170 uint64_t resp_addr;
45171 /* Firmware session id returned when HWRM_TF_SESSION_OPEN is sent. */
45172 uint32_t fw_session_id;
45173 /* Control flags. */
45175 /* Indicates the flow direction. */
45176 #define HWRM_TF_TBL_TYPE_BULK_GET_INPUT_FLAGS_DIR UINT32_C(0x1)
45177 /* If this bit set to 0, then it indicates rx flow. */
45178 #define HWRM_TF_TBL_TYPE_BULK_GET_INPUT_FLAGS_DIR_RX UINT32_C(0x0)
45179 /* If this bit is set to 1, then it indicates that tx flow. */
45180 #define HWRM_TF_TBL_TYPE_BULK_GET_INPUT_FLAGS_DIR_TX UINT32_C(0x1)
45181 #define HWRM_TF_TBL_TYPE_BULK_GET_INPUT_FLAGS_DIR_LAST \
45182 HWRM_TF_TBL_TYPE_BULK_GET_INPUT_FLAGS_DIR_TX
45184 uint8_t unused0[2];
45186 * Type of the resource, defined globally in the
45187 * hwrm_tf_resc_type enum.
45190 /* Starting index of the type to retrieve. */
45191 uint32_t start_index;
45192 /* Number of entries to retrieve. */
45193 uint32_t num_entries;
45194 /* Number of entries to retrieve. */
45196 /* Host memory where data will be stored. */
45197 uint64_t host_addr;
45200 /* hwrm_tf_tbl_type_bulk_get_output (size:128b/16B) */
45201 struct hwrm_tf_tbl_type_bulk_get_output {
45202 /* The specific error status for the command. */
45203 uint16_t error_code;
45204 /* The HWRM command request type. */
45206 /* The sequence ID from the original command. */
45208 /* The length of the response data in number of bytes. */
45210 /* Response code. */
45211 uint32_t resp_code;
45212 /* Response size. */
45217 * This field is used in Output records to indicate that the output
45218 * is completely written to RAM. This field should be read as '1'
45219 * to indicate that the output has been completely written.
45220 * When writing a command completion or response to an internal
45221 * processor, the order of writes has to be such that this field
45227 /******************************
45228 * hwrm_tunnel_dst_port_query *
45229 ******************************/
45232 /* hwrm_tunnel_dst_port_query_input (size:192b/24B) */
45233 struct hwrm_tunnel_dst_port_query_input {
45234 /* The HWRM command request type. */
45237 * The completion ring to send the completion event on. This should
45238 * be the NQ ID returned from the `nq_alloc` HWRM command.
45240 uint16_t cmpl_ring;
45242 * The sequence ID is used by the driver for tracking multiple
45243 * commands. This ID is treated as opaque data by the firmware and
45244 * the value is returned in the `hwrm_resp_hdr` upon completion.
45248 * The target ID of the command:
45249 * * 0x0-0xFFF8 - The function ID
45250 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
45251 * * 0xFFFD - Reserved for user-space HWRM interface
45254 uint16_t target_id;
45256 * A physical address pointer pointing to a host buffer that the
45257 * command's response data will be written. This can be either a host
45258 * physical address (HPA) or a guest physical address (GPA) and must
45259 * point to a physically contiguous block of memory.
45261 uint64_t resp_addr;
45263 uint8_t tunnel_type;
45264 /* Virtual eXtensible Local Area Network (VXLAN) */
45265 #define HWRM_TUNNEL_DST_PORT_QUERY_INPUT_TUNNEL_TYPE_VXLAN \
45267 /* Generic Network Virtualization Encapsulation (Geneve) */
45268 #define HWRM_TUNNEL_DST_PORT_QUERY_INPUT_TUNNEL_TYPE_GENEVE \
45270 /* IPV4 over virtual eXtensible Local Area Network (IPV4oVXLAN) */
45271 #define HWRM_TUNNEL_DST_PORT_QUERY_INPUT_TUNNEL_TYPE_VXLAN_V4 \
45273 /* Enhance Generic Routing Encapsulation (GRE version 1) inside IP datagram payload */
45274 #define HWRM_TUNNEL_DST_PORT_QUERY_INPUT_TUNNEL_TYPE_IPGRE_V1 \
45276 /* Use fixed layer 2 ether type of 0xFFFF */
45277 #define HWRM_TUNNEL_DST_PORT_QUERY_INPUT_TUNNEL_TYPE_L2_ETYPE \
45279 /* IPV6 over virtual eXtensible Local Area Network with GPE header (IPV6oVXLANGPE) */
45280 #define HWRM_TUNNEL_DST_PORT_QUERY_INPUT_TUNNEL_TYPE_VXLAN_GPE_V6 \
45282 #define HWRM_TUNNEL_DST_PORT_QUERY_INPUT_TUNNEL_TYPE_LAST \
45283 HWRM_TUNNEL_DST_PORT_QUERY_INPUT_TUNNEL_TYPE_VXLAN_GPE_V6
45284 uint8_t unused_0[7];
45287 /* hwrm_tunnel_dst_port_query_output (size:128b/16B) */
45288 struct hwrm_tunnel_dst_port_query_output {
45289 /* The specific error status for the command. */
45290 uint16_t error_code;
45291 /* The HWRM command request type. */
45293 /* The sequence ID from the original command. */
45295 /* The length of the response data in number of bytes. */
45298 * This field represents the identifier of L4 destination port
45299 * used for the given tunnel type. This field is valid for
45300 * specific tunnel types that use layer 4 (e.g. UDP)
45301 * transports for tunneling.
45303 uint16_t tunnel_dst_port_id;
45305 * This field represents the value of L4 destination port
45306 * identified by tunnel_dst_port_id. This field is valid for
45307 * specific tunnel types that use layer 4 (e.g. UDP)
45308 * transports for tunneling.
45309 * This field is in network byte order.
45311 * A value of 0 means that the destination port is not
45314 uint16_t tunnel_dst_port_val;
45315 uint8_t unused_0[3];
45317 * This field is used in Output records to indicate that the output
45318 * is completely written to RAM. This field should be read as '1'
45319 * to indicate that the output has been completely written.
45320 * When writing a command completion or response to an internal processor,
45321 * the order of writes has to be such that this field is written last.
45326 /******************************
45327 * hwrm_tunnel_dst_port_alloc *
45328 ******************************/
45331 /* hwrm_tunnel_dst_port_alloc_input (size:192b/24B) */
45332 struct hwrm_tunnel_dst_port_alloc_input {
45333 /* The HWRM command request type. */
45336 * The completion ring to send the completion event on. This should
45337 * be the NQ ID returned from the `nq_alloc` HWRM command.
45339 uint16_t cmpl_ring;
45341 * The sequence ID is used by the driver for tracking multiple
45342 * commands. This ID is treated as opaque data by the firmware and
45343 * the value is returned in the `hwrm_resp_hdr` upon completion.
45347 * The target ID of the command:
45348 * * 0x0-0xFFF8 - The function ID
45349 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
45350 * * 0xFFFD - Reserved for user-space HWRM interface
45353 uint16_t target_id;
45355 * A physical address pointer pointing to a host buffer that the
45356 * command's response data will be written. This can be either a host
45357 * physical address (HPA) or a guest physical address (GPA) and must
45358 * point to a physically contiguous block of memory.
45360 uint64_t resp_addr;
45362 uint8_t tunnel_type;
45363 /* Virtual eXtensible Local Area Network (VXLAN) */
45364 #define HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_VXLAN \
45366 /* Generic Network Virtualization Encapsulation (Geneve) */
45367 #define HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_GENEVE \
45369 /* IPV4 over virtual eXtensible Local Area Network (IPV4oVXLAN) */
45370 #define HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_VXLAN_V4 \
45372 /* Enhance Generic Routing Encapsulation (GRE version 1) inside IP datagram payload */
45373 #define HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_IPGRE_V1 \
45375 /* Use fixed layer 2 ether type of 0xFFFF */
45376 #define HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_L2_ETYPE \
45378 /* IPV6 over virtual eXtensible Local Area Network with GPE header (IPV6oVXLANGPE) */
45379 #define HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_VXLAN_GPE_V6 \
45381 #define HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_LAST \
45382 HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_VXLAN_GPE_V6
45385 * This field represents the value of L4 destination port used
45386 * for the given tunnel type. This field is valid for
45387 * specific tunnel types that use layer 4 (e.g. UDP)
45388 * transports for tunneling.
45390 * This field is in network byte order.
45392 * A value of 0 shall fail the command.
45394 uint16_t tunnel_dst_port_val;
45395 uint8_t unused_1[4];
45398 /* hwrm_tunnel_dst_port_alloc_output (size:128b/16B) */
45399 struct hwrm_tunnel_dst_port_alloc_output {
45400 /* The specific error status for the command. */
45401 uint16_t error_code;
45402 /* The HWRM command request type. */
45404 /* The sequence ID from the original command. */
45406 /* The length of the response data in number of bytes. */
45409 * Identifier of a tunnel L4 destination port value. Only applies to tunnel
45410 * types that has l4 destination port parameters.
45412 uint16_t tunnel_dst_port_id;
45413 uint8_t unused_0[5];
45415 * This field is used in Output records to indicate that the output
45416 * is completely written to RAM. This field should be read as '1'
45417 * to indicate that the output has been completely written.
45418 * When writing a command completion or response to an internal processor,
45419 * the order of writes has to be such that this field is written last.
45424 /*****************************
45425 * hwrm_tunnel_dst_port_free *
45426 *****************************/
45429 /* hwrm_tunnel_dst_port_free_input (size:192b/24B) */
45430 struct hwrm_tunnel_dst_port_free_input {
45431 /* The HWRM command request type. */
45434 * The completion ring to send the completion event on. This should
45435 * be the NQ ID returned from the `nq_alloc` HWRM command.
45437 uint16_t cmpl_ring;
45439 * The sequence ID is used by the driver for tracking multiple
45440 * commands. This ID is treated as opaque data by the firmware and
45441 * the value is returned in the `hwrm_resp_hdr` upon completion.
45445 * The target ID of the command:
45446 * * 0x0-0xFFF8 - The function ID
45447 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
45448 * * 0xFFFD - Reserved for user-space HWRM interface
45451 uint16_t target_id;
45453 * A physical address pointer pointing to a host buffer that the
45454 * command's response data will be written. This can be either a host
45455 * physical address (HPA) or a guest physical address (GPA) and must
45456 * point to a physically contiguous block of memory.
45458 uint64_t resp_addr;
45460 uint8_t tunnel_type;
45461 /* Virtual eXtensible Local Area Network (VXLAN) */
45462 #define HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_VXLAN \
45464 /* Generic Network Virtualization Encapsulation (Geneve) */
45465 #define HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_GENEVE \
45467 /* IPV4 over virtual eXtensible Local Area Network (IPV4oVXLAN) */
45468 #define HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_VXLAN_V4 \
45470 /* Enhance Generic Routing Encapsulation (GRE version 1) inside IP datagram payload */
45471 #define HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_IPGRE_V1 \
45473 /* Use fixed layer 2 ether type of 0xFFFF */
45474 #define HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_L2_ETYPE \
45476 /* IPV6 over virtual eXtensible Local Area Network with GPE header (IPV6oVXLANGPE) */
45477 #define HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_VXLAN_GPE_V6 \
45479 #define HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_LAST \
45480 HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_VXLAN_GPE_V6
45483 * Identifier of a tunnel L4 destination port value. Only applies to tunnel
45484 * types that has l4 destination port parameters.
45486 uint16_t tunnel_dst_port_id;
45487 uint8_t unused_1[4];
45490 /* hwrm_tunnel_dst_port_free_output (size:128b/16B) */
45491 struct hwrm_tunnel_dst_port_free_output {
45492 /* The specific error status for the command. */
45493 uint16_t error_code;
45494 /* The HWRM command request type. */
45496 /* The sequence ID from the original command. */
45498 /* The length of the response data in number of bytes. */
45500 uint8_t unused_1[7];
45502 * This field is used in Output records to indicate that the output
45503 * is completely written to RAM. This field should be read as '1'
45504 * to indicate that the output has been completely written.
45505 * When writing a command completion or response to an internal processor,
45506 * the order of writes has to be such that this field is written last.
45511 /* Periodic statistics context DMA to host. */
45512 /* ctx_hw_stats (size:1280b/160B) */
45513 struct ctx_hw_stats {
45514 /* Number of received unicast packets */
45515 uint64_t rx_ucast_pkts;
45516 /* Number of received multicast packets */
45517 uint64_t rx_mcast_pkts;
45518 /* Number of received broadcast packets */
45519 uint64_t rx_bcast_pkts;
45520 /* Number of discarded packets on receive path */
45521 uint64_t rx_discard_pkts;
45522 /* Number of packets on receive path with error */
45523 uint64_t rx_error_pkts;
45524 /* Number of received bytes for unicast traffic */
45525 uint64_t rx_ucast_bytes;
45526 /* Number of received bytes for multicast traffic */
45527 uint64_t rx_mcast_bytes;
45528 /* Number of received bytes for broadcast traffic */
45529 uint64_t rx_bcast_bytes;
45530 /* Number of transmitted unicast packets */
45531 uint64_t tx_ucast_pkts;
45532 /* Number of transmitted multicast packets */
45533 uint64_t tx_mcast_pkts;
45534 /* Number of transmitted broadcast packets */
45535 uint64_t tx_bcast_pkts;
45536 /* Number of packets on transmit path with error */
45537 uint64_t tx_error_pkts;
45538 /* Number of discarded packets on transmit path */
45539 uint64_t tx_discard_pkts;
45540 /* Number of transmitted bytes for unicast traffic */
45541 uint64_t tx_ucast_bytes;
45542 /* Number of transmitted bytes for multicast traffic */
45543 uint64_t tx_mcast_bytes;
45544 /* Number of transmitted bytes for broadcast traffic */
45545 uint64_t tx_bcast_bytes;
45546 /* Number of TPA packets */
45548 /* Number of TPA bytes */
45549 uint64_t tpa_bytes;
45550 /* Number of TPA events */
45551 uint64_t tpa_events;
45552 /* Number of TPA aborts */
45553 uint64_t tpa_aborts;
45557 * Extended periodic statistics context DMA to host. On cards that
45558 * support TPA v2, additional TPA related stats exist and can be retrieved
45559 * by DMA of ctx_hw_stats_ext, rather than legacy ctx_hw_stats structure.
45561 /* ctx_hw_stats_ext (size:1408b/176B) */
45562 struct ctx_hw_stats_ext {
45563 /* Number of received unicast packets */
45564 uint64_t rx_ucast_pkts;
45565 /* Number of received multicast packets */
45566 uint64_t rx_mcast_pkts;
45567 /* Number of received broadcast packets */
45568 uint64_t rx_bcast_pkts;
45569 /* Number of discarded packets on receive path */
45570 uint64_t rx_discard_pkts;
45571 /* Number of packets on receive path with error */
45572 uint64_t rx_error_pkts;
45573 /* Number of received bytes for unicast traffic */
45574 uint64_t rx_ucast_bytes;
45575 /* Number of received bytes for multicast traffic */
45576 uint64_t rx_mcast_bytes;
45577 /* Number of received bytes for broadcast traffic */
45578 uint64_t rx_bcast_bytes;
45579 /* Number of transmitted unicast packets */
45580 uint64_t tx_ucast_pkts;
45581 /* Number of transmitted multicast packets */
45582 uint64_t tx_mcast_pkts;
45583 /* Number of transmitted broadcast packets */
45584 uint64_t tx_bcast_pkts;
45585 /* Number of packets on transmit path with error */
45586 uint64_t tx_error_pkts;
45587 /* Number of discarded packets on transmit path */
45588 uint64_t tx_discard_pkts;
45589 /* Number of transmitted bytes for unicast traffic */
45590 uint64_t tx_ucast_bytes;
45591 /* Number of transmitted bytes for multicast traffic */
45592 uint64_t tx_mcast_bytes;
45593 /* Number of transmitted bytes for broadcast traffic */
45594 uint64_t tx_bcast_bytes;
45595 /* Number of TPA eligible packets */
45596 uint64_t rx_tpa_eligible_pkt;
45597 /* Number of TPA eligible bytes */
45598 uint64_t rx_tpa_eligible_bytes;
45599 /* Number of TPA packets */
45600 uint64_t rx_tpa_pkt;
45601 /* Number of TPA bytes */
45602 uint64_t rx_tpa_bytes;
45603 /* Number of TPA errors */
45604 uint64_t rx_tpa_errors;
45605 /* Number of TPA events */
45606 uint64_t rx_tpa_events;
45609 /* Periodic Engine statistics context DMA to host. */
45610 /* ctx_eng_stats (size:512b/64B) */
45611 struct ctx_eng_stats {
45613 * Count of data bytes into the Engine.
45614 * This includes any user supplied prefix,
45615 * but does not include any predefined
45618 uint64_t eng_bytes_in;
45619 /* Count of data bytes out of the Engine. */
45620 uint64_t eng_bytes_out;
45622 * Count, in 4-byte (dword) units, of bytes
45623 * that are input as auxiliary data.
45624 * This includes the aux_cmd data.
45626 uint64_t aux_bytes_in;
45628 * Count, in 4-byte (dword) units, of bytes
45629 * that are output as auxiliary data.
45630 * This count is the buffer space for aux_data
45631 * output provided in the RQE, not the actual
45634 uint64_t aux_bytes_out;
45635 /* Count of number of commands executed. */
45638 * Count of number of error commands.
45639 * These are the commands with a
45640 * non-zero status value.
45642 uint64_t error_commands;
45644 * Compression/Encryption Engine usage,
45645 * the unit is count of clock cycles
45647 uint64_t cce_engine_usage;
45649 * De-Compression/De-cryption Engine usage,
45650 * the unit is count of clock cycles
45652 uint64_t cdd_engine_usage;
45655 /***********************
45656 * hwrm_stat_ctx_alloc *
45657 ***********************/
45660 /* hwrm_stat_ctx_alloc_input (size:256b/32B) */
45661 struct hwrm_stat_ctx_alloc_input {
45662 /* The HWRM command request type. */
45665 * The completion ring to send the completion event on. This should
45666 * be the NQ ID returned from the `nq_alloc` HWRM command.
45668 uint16_t cmpl_ring;
45670 * The sequence ID is used by the driver for tracking multiple
45671 * commands. This ID is treated as opaque data by the firmware and
45672 * the value is returned in the `hwrm_resp_hdr` upon completion.
45676 * The target ID of the command:
45677 * * 0x0-0xFFF8 - The function ID
45678 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
45679 * * 0xFFFD - Reserved for user-space HWRM interface
45682 uint16_t target_id;
45684 * A physical address pointer pointing to a host buffer that the
45685 * command's response data will be written. This can be either a host
45686 * physical address (HPA) or a guest physical address (GPA) and must
45687 * point to a physically contiguous block of memory.
45689 uint64_t resp_addr;
45691 * This is the address for statistic block.
45692 * > For new versions of the chip, this address should be 128B
45695 uint64_t stats_dma_addr;
45697 * The statistic block update period in ms.
45698 * e.g. 250ms, 500ms, 750ms, 1000ms.
45699 * If update_period_ms is 0, then the stats update
45700 * shall be never done and the DMA address shall not be used.
45701 * In this case, the stat block can only be read by
45702 * hwrm_stat_ctx_query command.
45703 * On Ethernet/L2 based devices:
45704 * if tpa v2 supported (hwrm_vnic_qcaps[max_aggs_supported]>0),
45705 * ctx_hw_stats_ext is used for DMA,
45707 * ctx_hw_stats is used for DMA.
45709 uint32_t update_period_ms;
45711 * This field is used to specify statistics context specific
45712 * configuration flags.
45714 uint8_t stat_ctx_flags;
45716 * When this bit is set to '1', the statistics context shall be
45717 * allocated for RoCE traffic only. In this case, traffic other
45718 * than offloaded RoCE traffic shall not be included in this
45719 * statistic context.
45720 * When this bit is set to '0', the statistics context shall be
45721 * used for network traffic or engine traffic.
45723 #define HWRM_STAT_CTX_ALLOC_INPUT_STAT_CTX_FLAGS_ROCE UINT32_C(0x1)
45726 * This is the size of the structure (ctx_hw_stats or
45727 * ctx_hw_stats_ext) that the driver has allocated to be used
45728 * for the periodic DMA updates.
45730 uint16_t stats_dma_length;
45733 /* hwrm_stat_ctx_alloc_output (size:128b/16B) */
45734 struct hwrm_stat_ctx_alloc_output {
45735 /* The specific error status for the command. */
45736 uint16_t error_code;
45737 /* The HWRM command request type. */
45739 /* The sequence ID from the original command. */
45741 /* The length of the response data in number of bytes. */
45743 /* This is the statistics context ID value. */
45744 uint32_t stat_ctx_id;
45745 uint8_t unused_0[3];
45747 * This field is used in Output records to indicate that the output
45748 * is completely written to RAM. This field should be read as '1'
45749 * to indicate that the output has been completely written.
45750 * When writing a command completion or response to an internal processor,
45751 * the order of writes has to be such that this field is written last.
45756 /**********************
45757 * hwrm_stat_ctx_free *
45758 **********************/
45761 /* hwrm_stat_ctx_free_input (size:192b/24B) */
45762 struct hwrm_stat_ctx_free_input {
45763 /* The HWRM command request type. */
45766 * The completion ring to send the completion event on. This should
45767 * be the NQ ID returned from the `nq_alloc` HWRM command.
45769 uint16_t cmpl_ring;
45771 * The sequence ID is used by the driver for tracking multiple
45772 * commands. This ID is treated as opaque data by the firmware and
45773 * the value is returned in the `hwrm_resp_hdr` upon completion.
45777 * The target ID of the command:
45778 * * 0x0-0xFFF8 - The function ID
45779 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
45780 * * 0xFFFD - Reserved for user-space HWRM interface
45783 uint16_t target_id;
45785 * A physical address pointer pointing to a host buffer that the
45786 * command's response data will be written. This can be either a host
45787 * physical address (HPA) or a guest physical address (GPA) and must
45788 * point to a physically contiguous block of memory.
45790 uint64_t resp_addr;
45791 /* ID of the statistics context that is being queried. */
45792 uint32_t stat_ctx_id;
45793 uint8_t unused_0[4];
45796 /* hwrm_stat_ctx_free_output (size:128b/16B) */
45797 struct hwrm_stat_ctx_free_output {
45798 /* The specific error status for the command. */
45799 uint16_t error_code;
45800 /* The HWRM command request type. */
45802 /* The sequence ID from the original command. */
45804 /* The length of the response data in number of bytes. */
45806 /* This is the statistics context ID value. */
45807 uint32_t stat_ctx_id;
45808 uint8_t unused_0[3];
45810 * This field is used in Output records to indicate that the output
45811 * is completely written to RAM. This field should be read as '1'
45812 * to indicate that the output has been completely written.
45813 * When writing a command completion or response to an internal processor,
45814 * the order of writes has to be such that this field is written last.
45819 /***********************
45820 * hwrm_stat_ctx_query *
45821 ***********************/
45824 /* hwrm_stat_ctx_query_input (size:192b/24B) */
45825 struct hwrm_stat_ctx_query_input {
45826 /* The HWRM command request type. */
45829 * The completion ring to send the completion event on. This should
45830 * be the NQ ID returned from the `nq_alloc` HWRM command.
45832 uint16_t cmpl_ring;
45834 * The sequence ID is used by the driver for tracking multiple
45835 * commands. This ID is treated as opaque data by the firmware and
45836 * the value is returned in the `hwrm_resp_hdr` upon completion.
45840 * The target ID of the command:
45841 * * 0x0-0xFFF8 - The function ID
45842 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
45843 * * 0xFFFD - Reserved for user-space HWRM interface
45846 uint16_t target_id;
45848 * A physical address pointer pointing to a host buffer that the
45849 * command's response data will be written. This can be either a host
45850 * physical address (HPA) or a guest physical address (GPA) and must
45851 * point to a physically contiguous block of memory.
45853 uint64_t resp_addr;
45854 /* ID of the statistics context that is being queried. */
45855 uint32_t stat_ctx_id;
45858 * This bit is set to 1 when request is for a counter mask,
45859 * representing the width of each of the stats counters, rather
45860 * than counters themselves.
45862 #define HWRM_STAT_CTX_QUERY_INPUT_FLAGS_COUNTER_MASK UINT32_C(0x1)
45863 uint8_t unused_0[3];
45866 /* hwrm_stat_ctx_query_output (size:1408b/176B) */
45867 struct hwrm_stat_ctx_query_output {
45868 /* The specific error status for the command. */
45869 uint16_t error_code;
45870 /* The HWRM command request type. */
45872 /* The sequence ID from the original command. */
45874 /* The length of the response data in number of bytes. */
45876 /* Number of transmitted unicast packets */
45877 uint64_t tx_ucast_pkts;
45878 /* Number of transmitted multicast packets */
45879 uint64_t tx_mcast_pkts;
45880 /* Number of transmitted broadcast packets */
45881 uint64_t tx_bcast_pkts;
45882 /* Number of packets discarded in transmit path */
45883 uint64_t tx_discard_pkts;
45884 /* Number of packets in transmit path with error */
45885 uint64_t tx_error_pkts;
45886 /* Number of transmitted bytes for unicast traffic */
45887 uint64_t tx_ucast_bytes;
45888 /* Number of transmitted bytes for multicast traffic */
45889 uint64_t tx_mcast_bytes;
45890 /* Number of transmitted bytes for broadcast traffic */
45891 uint64_t tx_bcast_bytes;
45892 /* Number of received unicast packets */
45893 uint64_t rx_ucast_pkts;
45894 /* Number of received multicast packets */
45895 uint64_t rx_mcast_pkts;
45896 /* Number of received broadcast packets */
45897 uint64_t rx_bcast_pkts;
45898 /* Number of packets discarded in receive path */
45899 uint64_t rx_discard_pkts;
45900 /* Number of packets in receive path with errors */
45901 uint64_t rx_error_pkts;
45902 /* Number of received bytes for unicast traffic */
45903 uint64_t rx_ucast_bytes;
45904 /* Number of received bytes for multicast traffic */
45905 uint64_t rx_mcast_bytes;
45906 /* Number of received bytes for broadcast traffic */
45907 uint64_t rx_bcast_bytes;
45908 /* Number of aggregated unicast packets */
45909 uint64_t rx_agg_pkts;
45910 /* Number of aggregated unicast bytes */
45911 uint64_t rx_agg_bytes;
45912 /* Number of aggregation events */
45913 uint64_t rx_agg_events;
45914 /* Number of aborted aggregations */
45915 uint64_t rx_agg_aborts;
45916 uint8_t unused_0[7];
45918 * This field is used in Output records to indicate that the output
45919 * is completely written to RAM. This field should be read as '1'
45920 * to indicate that the output has been completely written.
45921 * When writing a command completion or response to an internal processor,
45922 * the order of writes has to be such that this field is written last.
45927 /***************************
45928 * hwrm_stat_ext_ctx_query *
45929 ***************************/
45932 /* hwrm_stat_ext_ctx_query_input (size:192b/24B) */
45933 struct hwrm_stat_ext_ctx_query_input {
45934 /* The HWRM command request type. */
45937 * The completion ring to send the completion event on. This should
45938 * be the NQ ID returned from the `nq_alloc` HWRM command.
45940 uint16_t cmpl_ring;
45942 * The sequence ID is used by the driver for tracking multiple
45943 * commands. This ID is treated as opaque data by the firmware and
45944 * the value is returned in the `hwrm_resp_hdr` upon completion.
45948 * The target ID of the command:
45949 * * 0x0-0xFFF8 - The function ID
45950 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
45951 * * 0xFFFD - Reserved for user-space HWRM interface
45954 uint16_t target_id;
45956 * A physical address pointer pointing to a host buffer that the
45957 * command's response data will be written. This can be either a host
45958 * physical address (HPA) or a guest physical address (GPA) and must
45959 * point to a physically contiguous block of memory.
45961 uint64_t resp_addr;
45962 /* ID of the extended statistics context that is being queried. */
45963 uint32_t stat_ctx_id;
45966 * This bit is set to 1 when request is for a counter mask,
45967 * representing the width of each of the stats counters, rather
45968 * than counters themselves.
45970 #define HWRM_STAT_EXT_CTX_QUERY_INPUT_FLAGS_COUNTER_MASK \
45972 uint8_t unused_0[3];
45975 /* hwrm_stat_ext_ctx_query_output (size:1536b/192B) */
45976 struct hwrm_stat_ext_ctx_query_output {
45977 /* The specific error status for the command. */
45978 uint16_t error_code;
45979 /* The HWRM command request type. */
45981 /* The sequence ID from the original command. */
45983 /* The length of the response data in number of bytes. */
45985 /* Number of received unicast packets */
45986 uint64_t rx_ucast_pkts;
45987 /* Number of received multicast packets */
45988 uint64_t rx_mcast_pkts;
45989 /* Number of received broadcast packets */
45990 uint64_t rx_bcast_pkts;
45991 /* Number of discarded packets on receive path */
45992 uint64_t rx_discard_pkts;
45993 /* Number of packets on receive path with error */
45994 uint64_t rx_error_pkts;
45995 /* Number of received bytes for unicast traffic */
45996 uint64_t rx_ucast_bytes;
45997 /* Number of received bytes for multicast traffic */
45998 uint64_t rx_mcast_bytes;
45999 /* Number of received bytes for broadcast traffic */
46000 uint64_t rx_bcast_bytes;
46001 /* Number of transmitted unicast packets */
46002 uint64_t tx_ucast_pkts;
46003 /* Number of transmitted multicast packets */
46004 uint64_t tx_mcast_pkts;
46005 /* Number of transmitted broadcast packets */
46006 uint64_t tx_bcast_pkts;
46007 /* Number of packets on transmit path with error */
46008 uint64_t tx_error_pkts;
46009 /* Number of discarded packets on transmit path */
46010 uint64_t tx_discard_pkts;
46011 /* Number of transmitted bytes for unicast traffic */
46012 uint64_t tx_ucast_bytes;
46013 /* Number of transmitted bytes for multicast traffic */
46014 uint64_t tx_mcast_bytes;
46015 /* Number of transmitted bytes for broadcast traffic */
46016 uint64_t tx_bcast_bytes;
46017 /* Number of TPA eligible packets */
46018 uint64_t rx_tpa_eligible_pkt;
46019 /* Number of TPA eligible bytes */
46020 uint64_t rx_tpa_eligible_bytes;
46021 /* Number of TPA packets */
46022 uint64_t rx_tpa_pkt;
46023 /* Number of TPA bytes */
46024 uint64_t rx_tpa_bytes;
46025 /* Number of TPA errors */
46026 uint64_t rx_tpa_errors;
46027 /* Number of TPA events */
46028 uint64_t rx_tpa_events;
46029 uint8_t unused_0[7];
46031 * This field is used in Output records to indicate that the output
46032 * is completely written to RAM. This field should be read as '1'
46033 * to indicate that the output has been completely written.
46034 * When writing a command completion or response to an internal processor,
46035 * the order of writes has to be such that this field is written last.
46040 /***************************
46041 * hwrm_stat_ctx_eng_query *
46042 ***************************/
46045 /* hwrm_stat_ctx_eng_query_input (size:192b/24B) */
46046 struct hwrm_stat_ctx_eng_query_input {
46047 /* The HWRM command request type. */
46050 * The completion ring to send the completion event on. This should
46051 * be the NQ ID returned from the `nq_alloc` HWRM command.
46053 uint16_t cmpl_ring;
46055 * The sequence ID is used by the driver for tracking multiple
46056 * commands. This ID is treated as opaque data by the firmware and
46057 * the value is returned in the `hwrm_resp_hdr` upon completion.
46061 * The target ID of the command:
46062 * * 0x0-0xFFF8 - The function ID
46063 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
46064 * * 0xFFFD - Reserved for user-space HWRM interface
46067 uint16_t target_id;
46069 * A physical address pointer pointing to a host buffer that the
46070 * command's response data will be written. This can be either a host
46071 * physical address (HPA) or a guest physical address (GPA) and must
46072 * point to a physically contiguous block of memory.
46074 uint64_t resp_addr;
46075 /* ID of the statistics context that is being queried. */
46076 uint32_t stat_ctx_id;
46077 uint8_t unused_0[4];
46080 /* hwrm_stat_ctx_eng_query_output (size:640b/80B) */
46081 struct hwrm_stat_ctx_eng_query_output {
46082 /* The specific error status for the command. */
46083 uint16_t error_code;
46084 /* The HWRM command request type. */
46086 /* The sequence ID from the original command. */
46088 /* The length of the response data in number of bytes. */
46091 * Count of data bytes into the Engine.
46092 * This includes any user supplied prefix,
46093 * but does not include any predefined
46096 uint64_t eng_bytes_in;
46097 /* Count of data bytes out of the Engine. */
46098 uint64_t eng_bytes_out;
46100 * Count, in 4-byte (dword) units, of bytes
46101 * that are input as auxiliary data.
46102 * This includes the aux_cmd data.
46104 uint64_t aux_bytes_in;
46106 * Count, in 4-byte (dword) units, of bytes
46107 * that are output as auxiliary data.
46108 * This count is the buffer space for aux_data
46109 * output provided in the RQE, not the actual
46112 uint64_t aux_bytes_out;
46113 /* Count of number of commands executed. */
46116 * Count of number of error commands.
46117 * These are the commands with a
46118 * non-zero status value.
46120 uint64_t error_commands;
46122 * Compression/Encryption Engine usage,
46123 * the unit is count of clock cycles
46125 uint64_t cce_engine_usage;
46127 * De-Compression/De-cryption Engine usage,
46128 * the unit is count of clock cycles
46130 uint64_t cdd_engine_usage;
46131 uint8_t unused_0[7];
46133 * This field is used in Output records to indicate that the output
46134 * is completely written to RAM. This field should be read as '1'
46135 * to indicate that the output has been completely written.
46136 * When writing a command completion or response to an internal processor,
46137 * the order of writes has to be such that this field is written last.
46142 /***************************
46143 * hwrm_stat_ctx_clr_stats *
46144 ***************************/
46147 /* hwrm_stat_ctx_clr_stats_input (size:192b/24B) */
46148 struct hwrm_stat_ctx_clr_stats_input {
46149 /* The HWRM command request type. */
46152 * The completion ring to send the completion event on. This should
46153 * be the NQ ID returned from the `nq_alloc` HWRM command.
46155 uint16_t cmpl_ring;
46157 * The sequence ID is used by the driver for tracking multiple
46158 * commands. This ID is treated as opaque data by the firmware and
46159 * the value is returned in the `hwrm_resp_hdr` upon completion.
46163 * The target ID of the command:
46164 * * 0x0-0xFFF8 - The function ID
46165 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
46166 * * 0xFFFD - Reserved for user-space HWRM interface
46169 uint16_t target_id;
46171 * A physical address pointer pointing to a host buffer that the
46172 * command's response data will be written. This can be either a host
46173 * physical address (HPA) or a guest physical address (GPA) and must
46174 * point to a physically contiguous block of memory.
46176 uint64_t resp_addr;
46177 /* ID of the statistics context that is being queried. */
46178 uint32_t stat_ctx_id;
46179 uint8_t unused_0[4];
46182 /* hwrm_stat_ctx_clr_stats_output (size:128b/16B) */
46183 struct hwrm_stat_ctx_clr_stats_output {
46184 /* The specific error status for the command. */
46185 uint16_t error_code;
46186 /* The HWRM command request type. */
46188 /* The sequence ID from the original command. */
46190 /* The length of the response data in number of bytes. */
46192 uint8_t unused_0[7];
46194 * This field is used in Output records to indicate that the output
46195 * is completely written to RAM. This field should be read as '1'
46196 * to indicate that the output has been completely written.
46197 * When writing a command completion or response to an internal processor,
46198 * the order of writes has to be such that this field is written last.
46203 /********************
46204 * hwrm_pcie_qstats *
46205 ********************/
46208 /* hwrm_pcie_qstats_input (size:256b/32B) */
46209 struct hwrm_pcie_qstats_input {
46210 /* The HWRM command request type. */
46213 * The completion ring to send the completion event on. This should
46214 * be the NQ ID returned from the `nq_alloc` HWRM command.
46216 uint16_t cmpl_ring;
46218 * The sequence ID is used by the driver for tracking multiple
46219 * commands. This ID is treated as opaque data by the firmware and
46220 * the value is returned in the `hwrm_resp_hdr` upon completion.
46224 * The target ID of the command:
46225 * * 0x0-0xFFF8 - The function ID
46226 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
46227 * * 0xFFFD - Reserved for user-space HWRM interface
46230 uint16_t target_id;
46232 * A physical address pointer pointing to a host buffer that the
46233 * command's response data will be written. This can be either a host
46234 * physical address (HPA) or a guest physical address (GPA) and must
46235 * point to a physically contiguous block of memory.
46237 uint64_t resp_addr;
46239 * The size of PCIe statistics block in bytes.
46240 * Firmware will DMA the PCIe statistics to
46241 * the host with this field size in the response.
46243 uint16_t pcie_stat_size;
46244 uint8_t unused_0[6];
46246 * This is the host address where
46247 * PCIe statistics will be stored
46249 uint64_t pcie_stat_host_addr;
46252 /* hwrm_pcie_qstats_output (size:128b/16B) */
46253 struct hwrm_pcie_qstats_output {
46254 /* The specific error status for the command. */
46255 uint16_t error_code;
46256 /* The HWRM command request type. */
46258 /* The sequence ID from the original command. */
46260 /* The length of the response data in number of bytes. */
46262 /* The size of PCIe statistics block in bytes. */
46263 uint16_t pcie_stat_size;
46264 uint8_t unused_0[5];
46266 * This field is used in Output records to indicate that the output
46267 * is completely written to RAM. This field should be read as '1'
46268 * to indicate that the output has been completely written.
46269 * When writing a command completion or response to an internal processor,
46270 * the order of writes has to be such that this field is written last.
46275 /* PCIe Statistics Formats */
46276 /* pcie_ctx_hw_stats (size:768b/96B) */
46277 struct pcie_ctx_hw_stats {
46278 /* Number of physical layer receiver errors */
46279 uint64_t pcie_pl_signal_integrity;
46280 /* Number of DLLP CRC errors detected by Data Link Layer */
46281 uint64_t pcie_dl_signal_integrity;
46283 * Number of TLP LCRC and sequence number errors detected
46284 * by Data Link Layer
46286 uint64_t pcie_tl_signal_integrity;
46287 /* Number of times LTSSM entered Recovery state */
46288 uint64_t pcie_link_integrity;
46289 /* Report number of TLP bits that have been transmitted in Mbps */
46290 uint64_t pcie_tx_traffic_rate;
46291 /* Report number of TLP bits that have been received in Mbps */
46292 uint64_t pcie_rx_traffic_rate;
46293 /* Number of DLLP bytes that have been transmitted */
46294 uint64_t pcie_tx_dllp_statistics;
46295 /* Number of DLLP bytes that have been received */
46296 uint64_t pcie_rx_dllp_statistics;
46298 * Number of times spent in each phase of gen3
46301 uint64_t pcie_equalization_time;
46302 /* Records the last 16 transitions of the LTSSM */
46303 uint32_t pcie_ltssm_histogram[4];
46305 * Record the last 8 reasons on why LTSSM transitioned
46308 uint64_t pcie_recovery_histogram;
46311 /**********************
46312 * hwrm_exec_fwd_resp *
46313 **********************/
46316 /* hwrm_exec_fwd_resp_input (size:1024b/128B) */
46317 struct hwrm_exec_fwd_resp_input {
46318 /* The HWRM command request type. */
46321 * The completion ring to send the completion event on. This should
46322 * be the NQ ID returned from the `nq_alloc` HWRM command.
46324 uint16_t cmpl_ring;
46326 * The sequence ID is used by the driver for tracking multiple
46327 * commands. This ID is treated as opaque data by the firmware and
46328 * the value is returned in the `hwrm_resp_hdr` upon completion.
46332 * The target ID of the command:
46333 * * 0x0-0xFFF8 - The function ID
46334 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
46335 * * 0xFFFD - Reserved for user-space HWRM interface
46338 uint16_t target_id;
46340 * A physical address pointer pointing to a host buffer that the
46341 * command's response data will be written. This can be either a host
46342 * physical address (HPA) or a guest physical address (GPA) and must
46343 * point to a physically contiguous block of memory.
46345 uint64_t resp_addr;
46347 * This is an encapsulated request. This request should
46348 * be executed by the HWRM and the response should be
46349 * provided in the response buffer inside the encapsulated
46352 uint32_t encap_request[26];
46354 * This value indicates the target id of the response to
46355 * the encapsulated request.
46356 * 0x0 - 0xFFF8 - Used for function ids
46357 * 0xFFF8 - 0xFFFE - Reserved for internal processors
46360 uint16_t encap_resp_target_id;
46361 uint8_t unused_0[6];
46364 /* hwrm_exec_fwd_resp_output (size:128b/16B) */
46365 struct hwrm_exec_fwd_resp_output {
46366 /* The specific error status for the command. */
46367 uint16_t error_code;
46368 /* The HWRM command request type. */
46370 /* The sequence ID from the original command. */
46372 /* The length of the response data in number of bytes. */
46374 uint8_t unused_0[7];
46376 * This field is used in Output records to indicate that the output
46377 * is completely written to RAM. This field should be read as '1'
46378 * to indicate that the output has been completely written.
46379 * When writing a command completion or response to an internal processor,
46380 * the order of writes has to be such that this field is written last.
46385 /************************
46386 * hwrm_reject_fwd_resp *
46387 ************************/
46390 /* hwrm_reject_fwd_resp_input (size:1024b/128B) */
46391 struct hwrm_reject_fwd_resp_input {
46392 /* The HWRM command request type. */
46395 * The completion ring to send the completion event on. This should
46396 * be the NQ ID returned from the `nq_alloc` HWRM command.
46398 uint16_t cmpl_ring;
46400 * The sequence ID is used by the driver for tracking multiple
46401 * commands. This ID is treated as opaque data by the firmware and
46402 * the value is returned in the `hwrm_resp_hdr` upon completion.
46406 * The target ID of the command:
46407 * * 0x0-0xFFF8 - The function ID
46408 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
46409 * * 0xFFFD - Reserved for user-space HWRM interface
46412 uint16_t target_id;
46414 * A physical address pointer pointing to a host buffer that the
46415 * command's response data will be written. This can be either a host
46416 * physical address (HPA) or a guest physical address (GPA) and must
46417 * point to a physically contiguous block of memory.
46419 uint64_t resp_addr;
46421 * This is an encapsulated request. This request should
46422 * be rejected by the HWRM and the error response should be
46423 * provided in the response buffer inside the encapsulated
46426 uint32_t encap_request[26];
46428 * This value indicates the target id of the response to
46429 * the encapsulated request.
46430 * 0x0 - 0xFFF8 - Used for function ids
46431 * 0xFFF8 - 0xFFFE - Reserved for internal processors
46434 uint16_t encap_resp_target_id;
46435 uint8_t unused_0[6];
46438 /* hwrm_reject_fwd_resp_output (size:128b/16B) */
46439 struct hwrm_reject_fwd_resp_output {
46440 /* The specific error status for the command. */
46441 uint16_t error_code;
46442 /* The HWRM command request type. */
46444 /* The sequence ID from the original command. */
46446 /* The length of the response data in number of bytes. */
46448 uint8_t unused_0[7];
46450 * This field is used in Output records to indicate that the output
46451 * is completely written to RAM. This field should be read as '1'
46452 * to indicate that the output has been completely written.
46453 * When writing a command completion or response to an internal processor,
46454 * the order of writes has to be such that this field is written last.
46464 /* hwrm_fwd_resp_input (size:1024b/128B) */
46465 struct hwrm_fwd_resp_input {
46466 /* The HWRM command request type. */
46469 * The completion ring to send the completion event on. This should
46470 * be the NQ ID returned from the `nq_alloc` HWRM command.
46472 uint16_t cmpl_ring;
46474 * The sequence ID is used by the driver for tracking multiple
46475 * commands. This ID is treated as opaque data by the firmware and
46476 * the value is returned in the `hwrm_resp_hdr` upon completion.
46480 * The target ID of the command:
46481 * * 0x0-0xFFF8 - The function ID
46482 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
46483 * * 0xFFFD - Reserved for user-space HWRM interface
46486 uint16_t target_id;
46488 * A physical address pointer pointing to a host buffer that the
46489 * command's response data will be written. This can be either a host
46490 * physical address (HPA) or a guest physical address (GPA) and must
46491 * point to a physically contiguous block of memory.
46493 uint64_t resp_addr;
46495 * This value indicates the target id of the encapsulated
46497 * 0x0 - 0xFFF8 - Used for function ids
46498 * 0xFFF8 - 0xFFFE - Reserved for internal processors
46501 uint16_t encap_resp_target_id;
46503 * This value indicates the completion ring the encapsulated
46504 * response will be optionally completed on. If the value is
46505 * -1, then no CR completion shall be generated for the
46506 * encapsulated response. Any other value must be a
46507 * valid CR ring_id value. If a valid encap_resp_cmpl_ring
46508 * is provided, then a CR completion shall be generated for
46509 * the encapsulated response.
46511 uint16_t encap_resp_cmpl_ring;
46512 /* This field indicates the length of encapsulated response. */
46513 uint16_t encap_resp_len;
46517 * This is the host address where the encapsulated response
46519 * This area must be 16B aligned and must be cleared to zero
46520 * before the original request is made.
46522 uint64_t encap_resp_addr;
46523 /* This is an encapsulated response. */
46524 uint32_t encap_resp[24];
46527 /* hwrm_fwd_resp_output (size:128b/16B) */
46528 struct hwrm_fwd_resp_output {
46529 /* The specific error status for the command. */
46530 uint16_t error_code;
46531 /* The HWRM command request type. */
46533 /* The sequence ID from the original command. */
46535 /* The length of the response data in number of bytes. */
46537 uint8_t unused_0[7];
46539 * This field is used in Output records to indicate that the output
46540 * is completely written to RAM. This field should be read as '1'
46541 * to indicate that the output has been completely written.
46542 * When writing a command completion or response to an internal processor,
46543 * the order of writes has to be such that this field is written last.
46548 /*****************************
46549 * hwrm_fwd_async_event_cmpl *
46550 *****************************/
46553 /* hwrm_fwd_async_event_cmpl_input (size:320b/40B) */
46554 struct hwrm_fwd_async_event_cmpl_input {
46555 /* The HWRM command request type. */
46558 * The completion ring to send the completion event on. This should
46559 * be the NQ ID returned from the `nq_alloc` HWRM command.
46561 uint16_t cmpl_ring;
46563 * The sequence ID is used by the driver for tracking multiple
46564 * commands. This ID is treated as opaque data by the firmware and
46565 * the value is returned in the `hwrm_resp_hdr` upon completion.
46569 * The target ID of the command:
46570 * * 0x0-0xFFF8 - The function ID
46571 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
46572 * * 0xFFFD - Reserved for user-space HWRM interface
46575 uint16_t target_id;
46577 * A physical address pointer pointing to a host buffer that the
46578 * command's response data will be written. This can be either a host
46579 * physical address (HPA) or a guest physical address (GPA) and must
46580 * point to a physically contiguous block of memory.
46582 uint64_t resp_addr;
46584 * This value indicates the target id of the encapsulated
46585 * asynchronous event.
46586 * 0x0 - 0xFFF8 - Used for function ids
46587 * 0xFFF8 - 0xFFFE - Reserved for internal processors
46588 * 0xFFFF - Broadcast to all children VFs (only applicable when
46589 * a PF is the requester)
46591 uint16_t encap_async_event_target_id;
46592 uint8_t unused_0[6];
46593 /* This is an encapsulated asynchronous event completion. */
46594 uint32_t encap_async_event_cmpl[4];
46597 /* hwrm_fwd_async_event_cmpl_output (size:128b/16B) */
46598 struct hwrm_fwd_async_event_cmpl_output {
46599 /* The specific error status for the command. */
46600 uint16_t error_code;
46601 /* The HWRM command request type. */
46603 /* The sequence ID from the original command. */
46605 /* The length of the response data in number of bytes. */
46607 uint8_t unused_0[7];
46609 * This field is used in Output records to indicate that the output
46610 * is completely written to RAM. This field should be read as '1'
46611 * to indicate that the output has been completely written.
46612 * When writing a command completion or response to an internal processor,
46613 * the order of writes has to be such that this field is written last.
46618 /**************************
46619 * hwrm_nvm_raw_write_blk *
46620 **************************/
46623 /* hwrm_nvm_raw_write_blk_input (size:256b/32B) */
46624 struct hwrm_nvm_raw_write_blk_input {
46625 /* The HWRM command request type. */
46628 * The completion ring to send the completion event on. This should
46629 * be the NQ ID returned from the `nq_alloc` HWRM command.
46631 uint16_t cmpl_ring;
46633 * The sequence ID is used by the driver for tracking multiple
46634 * commands. This ID is treated as opaque data by the firmware and
46635 * the value is returned in the `hwrm_resp_hdr` upon completion.
46639 * The target ID of the command:
46640 * * 0x0-0xFFF8 - The function ID
46641 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
46642 * * 0xFFFD - Reserved for user-space HWRM interface
46645 uint16_t target_id;
46647 * A physical address pointer pointing to a host buffer that the
46648 * command's response data will be written. This can be either a host
46649 * physical address (HPA) or a guest physical address (GPA) and must
46650 * point to a physically contiguous block of memory.
46652 uint64_t resp_addr;
46654 * 64-bit Host Source Address.
46655 * This is the location of the source data to be written.
46657 uint64_t host_src_addr;
46659 * 32-bit Destination Address.
46660 * This is the NVRAM byte-offset where the source data will be written to.
46662 uint32_t dest_addr;
46663 /* Length of data to be written, in bytes. */
46667 /* hwrm_nvm_raw_write_blk_output (size:128b/16B) */
46668 struct hwrm_nvm_raw_write_blk_output {
46669 /* The specific error status for the command. */
46670 uint16_t error_code;
46671 /* The HWRM command request type. */
46673 /* The sequence ID from the original command. */
46675 /* The length of the response data in number of bytes. */
46677 uint8_t unused_0[7];
46679 * This field is used in Output records to indicate that the output
46680 * is completely written to RAM. This field should be read as '1'
46681 * to indicate that the output has been completely written.
46682 * When writing a command completion or response to an internal processor,
46683 * the order of writes has to be such that this field is written last.
46693 /* hwrm_nvm_read_input (size:320b/40B) */
46694 struct hwrm_nvm_read_input {
46695 /* The HWRM command request type. */
46698 * The completion ring to send the completion event on. This should
46699 * be the NQ ID returned from the `nq_alloc` HWRM command.
46701 uint16_t cmpl_ring;
46703 * The sequence ID is used by the driver for tracking multiple
46704 * commands. This ID is treated as opaque data by the firmware and
46705 * the value is returned in the `hwrm_resp_hdr` upon completion.
46709 * The target ID of the command:
46710 * * 0x0-0xFFF8 - The function ID
46711 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
46712 * * 0xFFFD - Reserved for user-space HWRM interface
46715 uint16_t target_id;
46717 * A physical address pointer pointing to a host buffer that the
46718 * command's response data will be written. This can be either a host
46719 * physical address (HPA) or a guest physical address (GPA) and must
46720 * point to a physically contiguous block of memory.
46722 uint64_t resp_addr;
46724 * 64-bit Host Destination Address.
46725 * This is the host address where the data will be written to.
46727 uint64_t host_dest_addr;
46728 /* The 0-based index of the directory entry. */
46730 uint8_t unused_0[2];
46731 /* The NVRAM byte-offset to read from. */
46733 /* The length of the data to be read, in bytes. */
46735 uint8_t unused_1[4];
46738 /* hwrm_nvm_read_output (size:128b/16B) */
46739 struct hwrm_nvm_read_output {
46740 /* The specific error status for the command. */
46741 uint16_t error_code;
46742 /* The HWRM command request type. */
46744 /* The sequence ID from the original command. */
46746 /* The length of the response data in number of bytes. */
46748 uint8_t unused_0[7];
46750 * This field is used in Output records to indicate that the output
46751 * is completely written to RAM. This field should be read as '1'
46752 * to indicate that the output has been completely written.
46753 * When writing a command completion or response to an internal processor,
46754 * the order of writes has to be such that this field is written last.
46759 /*********************
46760 * hwrm_nvm_raw_dump *
46761 *********************/
46764 /* hwrm_nvm_raw_dump_input (size:256b/32B) */
46765 struct hwrm_nvm_raw_dump_input {
46766 /* The HWRM command request type. */
46769 * The completion ring to send the completion event on. This should
46770 * be the NQ ID returned from the `nq_alloc` HWRM command.
46772 uint16_t cmpl_ring;
46774 * The sequence ID is used by the driver for tracking multiple
46775 * commands. This ID is treated as opaque data by the firmware and
46776 * the value is returned in the `hwrm_resp_hdr` upon completion.
46780 * The target ID of the command:
46781 * * 0x0-0xFFF8 - The function ID
46782 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
46783 * * 0xFFFD - Reserved for user-space HWRM interface
46786 uint16_t target_id;
46788 * A physical address pointer pointing to a host buffer that the
46789 * command's response data will be written. This can be either a host
46790 * physical address (HPA) or a guest physical address (GPA) and must
46791 * point to a physically contiguous block of memory.
46793 uint64_t resp_addr;
46795 * 64-bit Host Destination Address.
46796 * This is the host address where the data will be written to.
46798 uint64_t host_dest_addr;
46799 /* 32-bit NVRAM byte-offset to read from. */
46801 /* Total length of NVRAM contents to be read, in bytes. */
46805 /* hwrm_nvm_raw_dump_output (size:128b/16B) */
46806 struct hwrm_nvm_raw_dump_output {
46807 /* The specific error status for the command. */
46808 uint16_t error_code;
46809 /* The HWRM command request type. */
46811 /* The sequence ID from the original command. */
46813 /* The length of the response data in number of bytes. */
46815 uint8_t unused_0[7];
46817 * This field is used in Output records to indicate that the output
46818 * is completely written to RAM. This field should be read as '1'
46819 * to indicate that the output has been completely written.
46820 * When writing a command completion or response to an internal processor,
46821 * the order of writes has to be such that this field is written last.
46826 /****************************
46827 * hwrm_nvm_get_dir_entries *
46828 ****************************/
46831 /* hwrm_nvm_get_dir_entries_input (size:192b/24B) */
46832 struct hwrm_nvm_get_dir_entries_input {
46833 /* The HWRM command request type. */
46836 * The completion ring to send the completion event on. This should
46837 * be the NQ ID returned from the `nq_alloc` HWRM command.
46839 uint16_t cmpl_ring;
46841 * The sequence ID is used by the driver for tracking multiple
46842 * commands. This ID is treated as opaque data by the firmware and
46843 * the value is returned in the `hwrm_resp_hdr` upon completion.
46847 * The target ID of the command:
46848 * * 0x0-0xFFF8 - The function ID
46849 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
46850 * * 0xFFFD - Reserved for user-space HWRM interface
46853 uint16_t target_id;
46855 * A physical address pointer pointing to a host buffer that the
46856 * command's response data will be written. This can be either a host
46857 * physical address (HPA) or a guest physical address (GPA) and must
46858 * point to a physically contiguous block of memory.
46860 uint64_t resp_addr;
46862 * 64-bit Host Destination Address.
46863 * This is the host address where the directory will be written.
46865 uint64_t host_dest_addr;
46868 /* hwrm_nvm_get_dir_entries_output (size:128b/16B) */
46869 struct hwrm_nvm_get_dir_entries_output {
46870 /* The specific error status for the command. */
46871 uint16_t error_code;
46872 /* The HWRM command request type. */
46874 /* The sequence ID from the original command. */
46876 /* The length of the response data in number of bytes. */
46878 uint8_t unused_0[7];
46880 * This field is used in Output records to indicate that the output
46881 * is completely written to RAM. This field should be read as '1'
46882 * to indicate that the output has been completely written.
46883 * When writing a command completion or response to an internal processor,
46884 * the order of writes has to be such that this field is written last.
46889 /*************************
46890 * hwrm_nvm_get_dir_info *
46891 *************************/
46894 /* hwrm_nvm_get_dir_info_input (size:128b/16B) */
46895 struct hwrm_nvm_get_dir_info_input {
46896 /* The HWRM command request type. */
46899 * The completion ring to send the completion event on. This should
46900 * be the NQ ID returned from the `nq_alloc` HWRM command.
46902 uint16_t cmpl_ring;
46904 * The sequence ID is used by the driver for tracking multiple
46905 * commands. This ID is treated as opaque data by the firmware and
46906 * the value is returned in the `hwrm_resp_hdr` upon completion.
46910 * The target ID of the command:
46911 * * 0x0-0xFFF8 - The function ID
46912 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
46913 * * 0xFFFD - Reserved for user-space HWRM interface
46916 uint16_t target_id;
46918 * A physical address pointer pointing to a host buffer that the
46919 * command's response data will be written. This can be either a host
46920 * physical address (HPA) or a guest physical address (GPA) and must
46921 * point to a physically contiguous block of memory.
46923 uint64_t resp_addr;
46926 /* hwrm_nvm_get_dir_info_output (size:192b/24B) */
46927 struct hwrm_nvm_get_dir_info_output {
46928 /* The specific error status for the command. */
46929 uint16_t error_code;
46930 /* The HWRM command request type. */
46932 /* The sequence ID from the original command. */
46934 /* The length of the response data in number of bytes. */
46936 /* Number of directory entries in the directory. */
46938 /* Size of each directory entry, in bytes. */
46939 uint32_t entry_length;
46940 uint8_t unused_0[7];
46942 * This field is used in Output records to indicate that the output
46943 * is completely written to RAM. This field should be read as '1'
46944 * to indicate that the output has been completely written.
46945 * When writing a command completion or response to an internal processor,
46946 * the order of writes has to be such that this field is written last.
46951 /******************
46953 ******************/
46956 /* hwrm_nvm_write_input (size:384b/48B) */
46957 struct hwrm_nvm_write_input {
46958 /* The HWRM command request type. */
46961 * The completion ring to send the completion event on. This should
46962 * be the NQ ID returned from the `nq_alloc` HWRM command.
46964 uint16_t cmpl_ring;
46966 * The sequence ID is used by the driver for tracking multiple
46967 * commands. This ID is treated as opaque data by the firmware and
46968 * the value is returned in the `hwrm_resp_hdr` upon completion.
46972 * The target ID of the command:
46973 * * 0x0-0xFFF8 - The function ID
46974 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
46975 * * 0xFFFD - Reserved for user-space HWRM interface
46978 uint16_t target_id;
46980 * A physical address pointer pointing to a host buffer that the
46981 * command's response data will be written. This can be either a host
46982 * physical address (HPA) or a guest physical address (GPA) and must
46983 * point to a physically contiguous block of memory.
46985 uint64_t resp_addr;
46987 * 64-bit Host Source Address.
46988 * This is where the source data is.
46990 uint64_t host_src_addr;
46992 * The Directory Entry Type (valid values are defined in the bnxnvm
46993 * directory_type enum defined in the file bnxnvm_defs.h).
46997 * Directory ordinal.
46998 * The 0-based instance of the combined Directory Entry Type and Extension.
47000 uint16_t dir_ordinal;
47001 /* The Directory Entry Extension flags (see BNX_DIR_EXT_* in the file bnxnvm_defs.h). */
47003 /* Directory Entry Attribute flags (see BNX_DIR_ATTR_* in the file bnxnvm_defs.h). */
47006 * Length of data to write, in bytes. May be less than or equal to the allocated
47007 * size for the directory entry.
47008 * The data length stored in the directory entry will be updated to reflect
47009 * this value once the write is complete.
47011 uint32_t dir_data_length;
47016 * When this bit is '1', the original active image
47017 * will not be removed. TBD: what purpose is this?
47019 #define HWRM_NVM_WRITE_INPUT_FLAGS_KEEP_ORIG_ACTIVE_IMG \
47022 * The requested length of the allocated NVM for the item, in bytes. This
47023 * value may be greater than or equal to the specified data length (dir_data_length).
47024 * If this value is less than the specified data length, it will be ignored.
47025 * The response will contain the actual allocated item length, which may be
47026 * greater than the requested item length.
47027 * The purpose for allocating more than the required number of bytes for
47028 * an item's data is to pre-allocate extra storage (padding) to accommodate
47029 * the potential future growth of an item (e.g. upgraded firmware with a
47030 * size increase, log growth, expanded configuration data).
47032 uint32_t dir_item_length;
47036 /* hwrm_nvm_write_output (size:128b/16B) */
47037 struct hwrm_nvm_write_output {
47038 /* The specific error status for the command. */
47039 uint16_t error_code;
47040 /* The HWRM command request type. */
47042 /* The sequence ID from the original command. */
47044 /* The length of the response data in number of bytes. */
47047 * Length of the allocated NVM for the item, in bytes. The value may be
47048 * greater than or equal to the specified data length or the requested
47050 * The actual item length used when creating a new directory entry will be
47051 * a multiple of an NVM block size.
47053 uint32_t dir_item_length;
47054 /* The directory index of the created or modified item. */
47058 * This field is used in Output records to indicate that the output
47059 * is completely written to RAM. This field should be read as '1'
47060 * to indicate that the output has been completely written.
47061 * When writing a command completion or response to an internal processor,
47062 * the order of writes has to be such that this field is written last.
47067 /* hwrm_nvm_write_cmd_err (size:64b/8B) */
47068 struct hwrm_nvm_write_cmd_err {
47070 * command specific error codes that goes to
47071 * the cmd_err field in Common HWRM Error Response.
47074 /* Unknown error */
47075 #define HWRM_NVM_WRITE_CMD_ERR_CODE_UNKNOWN UINT32_C(0x0)
47076 /* Unable to complete operation due to fragmentation */
47077 #define HWRM_NVM_WRITE_CMD_ERR_CODE_FRAG_ERR UINT32_C(0x1)
47078 /* nvm is completely full. */
47079 #define HWRM_NVM_WRITE_CMD_ERR_CODE_NO_SPACE UINT32_C(0x2)
47080 #define HWRM_NVM_WRITE_CMD_ERR_CODE_LAST \
47081 HWRM_NVM_WRITE_CMD_ERR_CODE_NO_SPACE
47082 uint8_t unused_0[7];
47085 /*******************
47086 * hwrm_nvm_modify *
47087 *******************/
47090 /* hwrm_nvm_modify_input (size:320b/40B) */
47091 struct hwrm_nvm_modify_input {
47092 /* The HWRM command request type. */
47095 * The completion ring to send the completion event on. This should
47096 * be the NQ ID returned from the `nq_alloc` HWRM command.
47098 uint16_t cmpl_ring;
47100 * The sequence ID is used by the driver for tracking multiple
47101 * commands. This ID is treated as opaque data by the firmware and
47102 * the value is returned in the `hwrm_resp_hdr` upon completion.
47106 * The target ID of the command:
47107 * * 0x0-0xFFF8 - The function ID
47108 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
47109 * * 0xFFFD - Reserved for user-space HWRM interface
47112 uint16_t target_id;
47114 * A physical address pointer pointing to a host buffer that the
47115 * command's response data will be written. This can be either a host
47116 * physical address (HPA) or a guest physical address (GPA) and must
47117 * point to a physically contiguous block of memory.
47119 uint64_t resp_addr;
47121 * 64-bit Host Source Address.
47122 * This is where the modified data is.
47124 uint64_t host_src_addr;
47125 /* 16-bit directory entry index. */
47129 * This flag indicates the sender wants to modify a continuous NVRAM
47130 * area using a batch of this HWRM requests. The offset of a request
47131 * must be continuous to the end of previous request's. Firmware does
47132 * not update the directory entry until receiving the last request,
47133 * which is indicated by the batch_last flag.
47134 * This flag is set usually when a sender does not have a block of
47135 * memory that is big enough to hold the entire NVRAM data for send
47138 #define HWRM_NVM_MODIFY_INPUT_FLAGS_BATCH_MODE UINT32_C(0x1)
47140 * This flag can be used only when the batch_mode flag is set.
47141 * It indicates this request is the last of batch requests.
47143 #define HWRM_NVM_MODIFY_INPUT_FLAGS_BATCH_LAST UINT32_C(0x2)
47144 /* 32-bit NVRAM byte-offset to modify content from. */
47147 * Length of data to be modified, in bytes. The length shall
47151 uint8_t unused_1[4];
47154 /* hwrm_nvm_modify_output (size:128b/16B) */
47155 struct hwrm_nvm_modify_output {
47156 /* The specific error status for the command. */
47157 uint16_t error_code;
47158 /* The HWRM command request type. */
47160 /* The sequence ID from the original command. */
47162 /* The length of the response data in number of bytes. */
47164 uint8_t unused_0[7];
47166 * This field is used in Output records to indicate that the output
47167 * is completely written to RAM. This field should be read as '1'
47168 * to indicate that the output has been completely written.
47169 * When writing a command completion or response to an internal processor,
47170 * the order of writes has to be such that this field is written last.
47175 /***************************
47176 * hwrm_nvm_find_dir_entry *
47177 ***************************/
47180 /* hwrm_nvm_find_dir_entry_input (size:256b/32B) */
47181 struct hwrm_nvm_find_dir_entry_input {
47182 /* The HWRM command request type. */
47185 * The completion ring to send the completion event on. This should
47186 * be the NQ ID returned from the `nq_alloc` HWRM command.
47188 uint16_t cmpl_ring;
47190 * The sequence ID is used by the driver for tracking multiple
47191 * commands. This ID is treated as opaque data by the firmware and
47192 * the value is returned in the `hwrm_resp_hdr` upon completion.
47196 * The target ID of the command:
47197 * * 0x0-0xFFF8 - The function ID
47198 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
47199 * * 0xFFFD - Reserved for user-space HWRM interface
47202 uint16_t target_id;
47204 * A physical address pointer pointing to a host buffer that the
47205 * command's response data will be written. This can be either a host
47206 * physical address (HPA) or a guest physical address (GPA) and must
47207 * point to a physically contiguous block of memory.
47209 uint64_t resp_addr;
47212 * This bit must be '1' for the dir_idx_valid field to be
47215 #define HWRM_NVM_FIND_DIR_ENTRY_INPUT_ENABLES_DIR_IDX_VALID \
47217 /* Directory Entry Index */
47219 /* Directory Entry (Image) Type */
47222 * Directory ordinal.
47223 * The instance of this Directory Type
47225 uint16_t dir_ordinal;
47226 /* The Directory Entry Extension flags. */
47228 /* This value indicates the search option using dir_ordinal. */
47229 uint8_t opt_ordinal;
47230 /* This value indicates the search option using dir_ordinal. */
47231 #define HWRM_NVM_FIND_DIR_ENTRY_INPUT_OPT_ORDINAL_MASK UINT32_C(0x3)
47232 #define HWRM_NVM_FIND_DIR_ENTRY_INPUT_OPT_ORDINAL_SFT 0
47233 /* Equal to specified ordinal value. */
47234 #define HWRM_NVM_FIND_DIR_ENTRY_INPUT_OPT_ORDINAL_EQ UINT32_C(0x0)
47235 /* Greater than or equal to specified ordinal value */
47236 #define HWRM_NVM_FIND_DIR_ENTRY_INPUT_OPT_ORDINAL_GE UINT32_C(0x1)
47237 /* Greater than specified ordinal value */
47238 #define HWRM_NVM_FIND_DIR_ENTRY_INPUT_OPT_ORDINAL_GT UINT32_C(0x2)
47239 #define HWRM_NVM_FIND_DIR_ENTRY_INPUT_OPT_ORDINAL_LAST \
47240 HWRM_NVM_FIND_DIR_ENTRY_INPUT_OPT_ORDINAL_GT
47241 uint8_t unused_0[3];
47244 /* hwrm_nvm_find_dir_entry_output (size:256b/32B) */
47245 struct hwrm_nvm_find_dir_entry_output {
47246 /* The specific error status for the command. */
47247 uint16_t error_code;
47248 /* The HWRM command request type. */
47250 /* The sequence ID from the original command. */
47252 /* The length of the response data in number of bytes. */
47254 /* Allocated NVRAM for this directory entry, in bytes. */
47255 uint32_t dir_item_length;
47256 /* Size of the stored data for this directory entry, in bytes. */
47257 uint32_t dir_data_length;
47259 * Firmware version.
47260 * Only valid if the directory entry is for embedded firmware stored in APE_BIN Format.
47263 /* Directory ordinal. */
47264 uint16_t dir_ordinal;
47265 /* Directory Entry Index */
47267 uint8_t unused_0[7];
47269 * This field is used in Output records to indicate that the output
47270 * is completely written to RAM. This field should be read as '1'
47271 * to indicate that the output has been completely written.
47272 * When writing a command completion or response to an internal processor,
47273 * the order of writes has to be such that this field is written last.
47278 /****************************
47279 * hwrm_nvm_erase_dir_entry *
47280 ****************************/
47283 /* hwrm_nvm_erase_dir_entry_input (size:192b/24B) */
47284 struct hwrm_nvm_erase_dir_entry_input {
47285 /* The HWRM command request type. */
47288 * The completion ring to send the completion event on. This should
47289 * be the NQ ID returned from the `nq_alloc` HWRM command.
47291 uint16_t cmpl_ring;
47293 * The sequence ID is used by the driver for tracking multiple
47294 * commands. This ID is treated as opaque data by the firmware and
47295 * the value is returned in the `hwrm_resp_hdr` upon completion.
47299 * The target ID of the command:
47300 * * 0x0-0xFFF8 - The function ID
47301 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
47302 * * 0xFFFD - Reserved for user-space HWRM interface
47305 uint16_t target_id;
47307 * A physical address pointer pointing to a host buffer that the
47308 * command's response data will be written. This can be either a host
47309 * physical address (HPA) or a guest physical address (GPA) and must
47310 * point to a physically contiguous block of memory.
47312 uint64_t resp_addr;
47313 /* Directory Entry Index */
47315 uint8_t unused_0[6];
47318 /* hwrm_nvm_erase_dir_entry_output (size:128b/16B) */
47319 struct hwrm_nvm_erase_dir_entry_output {
47320 /* The specific error status for the command. */
47321 uint16_t error_code;
47322 /* The HWRM command request type. */
47324 /* The sequence ID from the original command. */
47326 /* The length of the response data in number of bytes. */
47328 uint8_t unused_0[7];
47330 * This field is used in Output records to indicate that the output
47331 * is completely written to RAM. This field should be read as '1'
47332 * to indicate that the output has been completely written.
47333 * When writing a command completion or response to an internal processor,
47334 * the order of writes has to be such that this field is written last.
47339 /*************************
47340 * hwrm_nvm_get_dev_info *
47341 *************************/
47344 /* hwrm_nvm_get_dev_info_input (size:128b/16B) */
47345 struct hwrm_nvm_get_dev_info_input {
47346 /* The HWRM command request type. */
47349 * The completion ring to send the completion event on. This should
47350 * be the NQ ID returned from the `nq_alloc` HWRM command.
47352 uint16_t cmpl_ring;
47354 * The sequence ID is used by the driver for tracking multiple
47355 * commands. This ID is treated as opaque data by the firmware and
47356 * the value is returned in the `hwrm_resp_hdr` upon completion.
47360 * The target ID of the command:
47361 * * 0x0-0xFFF8 - The function ID
47362 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
47363 * * 0xFFFD - Reserved for user-space HWRM interface
47366 uint16_t target_id;
47368 * A physical address pointer pointing to a host buffer that the
47369 * command's response data will be written. This can be either a host
47370 * physical address (HPA) or a guest physical address (GPA) and must
47371 * point to a physically contiguous block of memory.
47373 uint64_t resp_addr;
47376 /* hwrm_nvm_get_dev_info_output (size:640b/80B) */
47377 struct hwrm_nvm_get_dev_info_output {
47378 /* The specific error status for the command. */
47379 uint16_t error_code;
47380 /* The HWRM command request type. */
47382 /* The sequence ID from the original command. */
47384 /* The length of the response data in number of bytes. */
47386 /* Manufacturer ID. */
47387 uint16_t manufacturer_id;
47389 uint16_t device_id;
47390 /* Sector size of the NVRAM device. */
47391 uint32_t sector_size;
47392 /* Total size, in bytes of the NVRAM device. */
47393 uint32_t nvram_size;
47394 uint32_t reserved_size;
47396 * Available size that can be used, in bytes. Available size is the
47397 * NVRAM size take away the used size and reserved size.
47399 uint32_t available_size;
47400 /* This field represents the major version of NVM cfg */
47401 uint8_t nvm_cfg_ver_maj;
47402 /* This field represents the minor version of NVM cfg */
47403 uint8_t nvm_cfg_ver_min;
47404 /* This field represents the update version of NVM cfg */
47405 uint8_t nvm_cfg_ver_upd;
47408 * If set to 1, firmware will provide various firmware version
47409 * information stored in the flash.
47411 #define HWRM_NVM_GET_DEV_INFO_OUTPUT_FLAGS_FW_VER_VALID \
47414 * This field represents the board package name stored in the flash.
47415 * (ASCII chars with NULL at the end).
47419 * This field represents the major version of HWRM firmware, stored in
47422 uint16_t hwrm_fw_major;
47424 * This field represents the minor version of HWRM firmware, stored in
47427 uint16_t hwrm_fw_minor;
47429 * This field represents the build version of HWRM firmware, stored in
47432 uint16_t hwrm_fw_build;
47434 * This field can be used to represent firmware branches or customer
47435 * specific releases tied to a specific (major, minor, build) version
47436 * of the HWRM firmware.
47438 uint16_t hwrm_fw_patch;
47440 * This field represents the major version of mgmt firmware, stored in
47443 uint16_t mgmt_fw_major;
47445 * This field represents the minor version of mgmt firmware, stored in
47448 uint16_t mgmt_fw_minor;
47450 * This field represents the build version of mgmt firmware, stored in
47453 uint16_t mgmt_fw_build;
47455 * This field can be used to represent firmware branches or customer
47456 * specific releases tied to a specific (major, minor, build) version
47457 * of the mgmt firmware.
47459 uint16_t mgmt_fw_patch;
47461 * This field represents the major version of roce firmware, stored in
47464 uint16_t roce_fw_major;
47466 * This field represents the minor version of roce firmware, stored in
47469 uint16_t roce_fw_minor;
47471 * This field represents the build version of roce firmware, stored in
47474 uint16_t roce_fw_build;
47476 * This field can be used to represent firmware branches or customer
47477 * specific releases tied to a specific (major, minor, build) version
47478 * of the roce firmware.
47480 uint16_t roce_fw_patch;
47481 uint8_t unused_0[7];
47483 * This field is used in Output records to indicate that the output
47484 * is completely written to RAM. This field should be read as '1'
47485 * to indicate that the output has been completely written.
47486 * When writing a command completion or response to an internal processor,
47487 * the order of writes has to be such that this field is written last.
47492 /**************************
47493 * hwrm_nvm_mod_dir_entry *
47494 **************************/
47497 /* hwrm_nvm_mod_dir_entry_input (size:256b/32B) */
47498 struct hwrm_nvm_mod_dir_entry_input {
47499 /* The HWRM command request type. */
47502 * The completion ring to send the completion event on. This should
47503 * be the NQ ID returned from the `nq_alloc` HWRM command.
47505 uint16_t cmpl_ring;
47507 * The sequence ID is used by the driver for tracking multiple
47508 * commands. This ID is treated as opaque data by the firmware and
47509 * the value is returned in the `hwrm_resp_hdr` upon completion.
47513 * The target ID of the command:
47514 * * 0x0-0xFFF8 - The function ID
47515 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
47516 * * 0xFFFD - Reserved for user-space HWRM interface
47519 uint16_t target_id;
47521 * A physical address pointer pointing to a host buffer that the
47522 * command's response data will be written. This can be either a host
47523 * physical address (HPA) or a guest physical address (GPA) and must
47524 * point to a physically contiguous block of memory.
47526 uint64_t resp_addr;
47529 * This bit must be '1' for the checksum field to be
47532 #define HWRM_NVM_MOD_DIR_ENTRY_INPUT_ENABLES_CHECKSUM UINT32_C(0x1)
47533 /* Directory Entry Index */
47536 * Directory ordinal.
47537 * The (0-based) instance of this Directory Type.
47539 uint16_t dir_ordinal;
47541 * The Directory Entry Extension flags (see BNX_DIR_EXT_* for extension
47542 * flag definitions).
47546 * Directory Entry Attribute flags (see BNX_DIR_ATTR_* for attribute flag
47551 * If valid, then this field updates the checksum
47552 * value of the content in the directory entry.
47557 /* hwrm_nvm_mod_dir_entry_output (size:128b/16B) */
47558 struct hwrm_nvm_mod_dir_entry_output {
47559 /* The specific error status for the command. */
47560 uint16_t error_code;
47561 /* The HWRM command request type. */
47563 /* The sequence ID from the original command. */
47565 /* The length of the response data in number of bytes. */
47567 uint8_t unused_0[7];
47569 * This field is used in Output records to indicate that the output
47570 * is completely written to RAM. This field should be read as '1'
47571 * to indicate that the output has been completely written.
47572 * When writing a command completion or response to an internal processor,
47573 * the order of writes has to be such that this field is written last.
47578 /**************************
47579 * hwrm_nvm_verify_update *
47580 **************************/
47583 /* hwrm_nvm_verify_update_input (size:192b/24B) */
47584 struct hwrm_nvm_verify_update_input {
47585 /* The HWRM command request type. */
47588 * The completion ring to send the completion event on. This should
47589 * be the NQ ID returned from the `nq_alloc` HWRM command.
47591 uint16_t cmpl_ring;
47593 * The sequence ID is used by the driver for tracking multiple
47594 * commands. This ID is treated as opaque data by the firmware and
47595 * the value is returned in the `hwrm_resp_hdr` upon completion.
47599 * The target ID of the command:
47600 * * 0x0-0xFFF8 - The function ID
47601 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
47602 * * 0xFFFD - Reserved for user-space HWRM interface
47605 uint16_t target_id;
47607 * A physical address pointer pointing to a host buffer that the
47608 * command's response data will be written. This can be either a host
47609 * physical address (HPA) or a guest physical address (GPA) and must
47610 * point to a physically contiguous block of memory.
47612 uint64_t resp_addr;
47613 /* Directory Entry Type, to be verified. */
47616 * Directory ordinal.
47617 * The instance of the Directory Type to be verified.
47619 uint16_t dir_ordinal;
47621 * The Directory Entry Extension flags.
47622 * The "UPDATE" extension flag must be set in this value.
47623 * A corresponding directory entry with the same type and ordinal values but *without*
47624 * the "UPDATE" extension flag must also exist. The other flags of the extension must
47625 * be identical between the active and update entries.
47628 uint8_t unused_0[2];
47631 /* hwrm_nvm_verify_update_output (size:128b/16B) */
47632 struct hwrm_nvm_verify_update_output {
47633 /* The specific error status for the command. */
47634 uint16_t error_code;
47635 /* The HWRM command request type. */
47637 /* The sequence ID from the original command. */
47639 /* The length of the response data in number of bytes. */
47641 uint8_t unused_0[7];
47643 * This field is used in Output records to indicate that the output
47644 * is completely written to RAM. This field should be read as '1'
47645 * to indicate that the output has been completely written.
47646 * When writing a command completion or response to an internal processor,
47647 * the order of writes has to be such that this field is written last.
47652 /***************************
47653 * hwrm_nvm_install_update *
47654 ***************************/
47657 /* hwrm_nvm_install_update_input (size:192b/24B) */
47658 struct hwrm_nvm_install_update_input {
47659 /* The HWRM command request type. */
47662 * The completion ring to send the completion event on. This should
47663 * be the NQ ID returned from the `nq_alloc` HWRM command.
47665 uint16_t cmpl_ring;
47667 * The sequence ID is used by the driver for tracking multiple
47668 * commands. This ID is treated as opaque data by the firmware and
47669 * the value is returned in the `hwrm_resp_hdr` upon completion.
47673 * The target ID of the command:
47674 * * 0x0-0xFFF8 - The function ID
47675 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
47676 * * 0xFFFD - Reserved for user-space HWRM interface
47679 uint16_t target_id;
47681 * A physical address pointer pointing to a host buffer that the
47682 * command's response data will be written. This can be either a host
47683 * physical address (HPA) or a guest physical address (GPA) and must
47684 * point to a physically contiguous block of memory.
47686 uint64_t resp_addr;
47688 * Installation type. If the value 3 through 0xffff is used,
47689 * only packaged items with that type value will be installed and
47690 * conditional installation directives for those packaged items
47691 * will be over-ridden (i.e. 'create' or 'replace' will be treated
47694 uint32_t install_type;
47696 * Perform a normal package installation. Conditional installation
47697 * directives (e.g. 'create' and 'replace') of packaged items
47698 * will be followed.
47700 #define HWRM_NVM_INSTALL_UPDATE_INPUT_INSTALL_TYPE_NORMAL UINT32_C(0x0)
47702 * Install all packaged items regardless of installation directive
47703 * (i.e. treat all packaged items as though they have an installation
47704 * directive of 'install').
47706 #define HWRM_NVM_INSTALL_UPDATE_INPUT_INSTALL_TYPE_ALL \
47707 UINT32_C(0xffffffff)
47708 #define HWRM_NVM_INSTALL_UPDATE_INPUT_INSTALL_TYPE_LAST \
47709 HWRM_NVM_INSTALL_UPDATE_INPUT_INSTALL_TYPE_ALL
47711 /* If set to 1, then securely erase all unused locations in persistent storage. */
47712 #define HWRM_NVM_INSTALL_UPDATE_INPUT_FLAGS_ERASE_UNUSED_SPACE \
47715 * If set to 1, then unspecified images, images not in the package file,
47716 * will be safely deleted.
47717 * When combined with erase_unused_space then unspecified images will be
47720 #define HWRM_NVM_INSTALL_UPDATE_INPUT_FLAGS_REMOVE_UNUSED_PKG \
47723 * If set to 1, FW will defragment the NVM if defragmentation is required for the update.
47724 * Allow additional time for this command to complete if this bit is set to 1.
47726 #define HWRM_NVM_INSTALL_UPDATE_INPUT_FLAGS_ALLOWED_TO_DEFRAG \
47729 * If set to 1, FW will verify the package in the "UPDATE" NVM item
47730 * without installing it. This flag is for FW internal use only.
47731 * Users should not set this flag. The request will otherwise fail.
47733 #define HWRM_NVM_INSTALL_UPDATE_INPUT_FLAGS_VERIFY_ONLY \
47735 uint8_t unused_0[2];
47738 /* hwrm_nvm_install_update_output (size:192b/24B) */
47739 struct hwrm_nvm_install_update_output {
47740 /* The specific error status for the command. */
47741 uint16_t error_code;
47742 /* The HWRM command request type. */
47744 /* The sequence ID from the original command. */
47746 /* The length of the response data in number of bytes. */
47749 * Bit-mask of successfully installed items.
47750 * Bit-0 corresponding to the first packaged item, Bit-1 for the second item, etc.
47751 * A value of 0 indicates that no items were successfully installed.
47753 uint64_t installed_items;
47754 /* result is 8 b */
47756 /* There was no problem with the package installation. */
47757 #define HWRM_NVM_INSTALL_UPDATE_OUTPUT_RESULT_SUCCESS UINT32_C(0x0)
47758 #define HWRM_NVM_INSTALL_UPDATE_OUTPUT_RESULT_LAST \
47759 HWRM_NVM_INSTALL_UPDATE_OUTPUT_RESULT_SUCCESS
47760 /* problem_item is 8 b */
47761 uint8_t problem_item;
47762 /* There was no problem with any packaged items. */
47763 #define HWRM_NVM_INSTALL_UPDATE_OUTPUT_PROBLEM_ITEM_NONE \
47765 /* There was a problem with the NVM package itself. */
47766 #define HWRM_NVM_INSTALL_UPDATE_OUTPUT_PROBLEM_ITEM_PACKAGE \
47768 #define HWRM_NVM_INSTALL_UPDATE_OUTPUT_PROBLEM_ITEM_LAST \
47769 HWRM_NVM_INSTALL_UPDATE_OUTPUT_PROBLEM_ITEM_PACKAGE
47770 /* reset_required is 8 b */
47771 uint8_t reset_required;
47773 * No reset is required for installed/updated firmware or
47774 * microcode to take effect.
47776 #define HWRM_NVM_INSTALL_UPDATE_OUTPUT_RESET_REQUIRED_NONE \
47779 * A PCIe reset (e.g. system reboot) is
47780 * required for newly installed/updated firmware or
47781 * microcode to take effect.
47783 #define HWRM_NVM_INSTALL_UPDATE_OUTPUT_RESET_REQUIRED_PCI \
47786 * A controller power reset (e.g. system power-cycle) is
47787 * required for newly installed/updated firmware or
47788 * microcode to take effect. Some newly installed/updated
47789 * firmware or microcode may still take effect upon the
47792 #define HWRM_NVM_INSTALL_UPDATE_OUTPUT_RESET_REQUIRED_POWER \
47794 #define HWRM_NVM_INSTALL_UPDATE_OUTPUT_RESET_REQUIRED_LAST \
47795 HWRM_NVM_INSTALL_UPDATE_OUTPUT_RESET_REQUIRED_POWER
47796 uint8_t unused_0[4];
47798 * This field is used in Output records to indicate that the output
47799 * is completely written to RAM. This field should be read as '1'
47800 * to indicate that the output has been completely written.
47801 * When writing a command completion or response to an internal processor,
47802 * the order of writes has to be such that this field is written last.
47807 /* hwrm_nvm_install_update_cmd_err (size:64b/8B) */
47808 struct hwrm_nvm_install_update_cmd_err {
47810 * command specific error codes that goes to
47811 * the cmd_err field in Common HWRM Error Response.
47814 /* Unknown error */
47815 #define HWRM_NVM_INSTALL_UPDATE_CMD_ERR_CODE_UNKNOWN UINT32_C(0x0)
47816 /* Unable to complete operation due to fragmentation */
47817 #define HWRM_NVM_INSTALL_UPDATE_CMD_ERR_CODE_FRAG_ERR UINT32_C(0x1)
47818 /* nvm is completely full. */
47819 #define HWRM_NVM_INSTALL_UPDATE_CMD_ERR_CODE_NO_SPACE UINT32_C(0x2)
47820 #define HWRM_NVM_INSTALL_UPDATE_CMD_ERR_CODE_LAST \
47821 HWRM_NVM_INSTALL_UPDATE_CMD_ERR_CODE_NO_SPACE
47822 uint8_t unused_0[7];
47825 /******************
47827 ******************/
47830 /* hwrm_nvm_flush_input (size:128b/16B) */
47831 struct hwrm_nvm_flush_input {
47832 /* The HWRM command request type. */
47835 * The completion ring to send the completion event on. This should
47836 * be the NQ ID returned from the `nq_alloc` HWRM command.
47838 uint16_t cmpl_ring;
47840 * The sequence ID is used by the driver for tracking multiple
47841 * commands. This ID is treated as opaque data by the firmware and
47842 * the value is returned in the `hwrm_resp_hdr` upon completion.
47846 * The target ID of the command:
47847 * * 0x0-0xFFF8 - The function ID
47848 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
47849 * * 0xFFFD - Reserved for user-space HWRM interface
47852 uint16_t target_id;
47854 * A physical address pointer pointing to a host buffer that the
47855 * command's response data will be written. This can be either a host
47856 * physical address (HPA) or a guest physical address (GPA) and must
47857 * point to a physically contiguous block of memory.
47859 uint64_t resp_addr;
47862 /* hwrm_nvm_flush_output (size:128b/16B) */
47863 struct hwrm_nvm_flush_output {
47864 /* The specific error status for the command. */
47865 uint16_t error_code;
47866 /* The HWRM command request type. */
47868 /* The sequence ID from the original command. */
47870 /* The length of the response data in number of bytes. */
47872 uint8_t unused_0[7];
47874 * This field is used in Output records to indicate that the output
47875 * is completely written to RAM. This field should be read as '1'
47876 * to indicate that the output has been completely written.
47877 * When writing a command completion or response to an internal processor,
47878 * the order of writes has to be such that this field is written last.
47883 /* hwrm_nvm_flush_cmd_err (size:64b/8B) */
47884 struct hwrm_nvm_flush_cmd_err {
47886 * command specific error codes that goes to
47887 * the cmd_err field in Common HWRM Error Response.
47890 /* Unknown error */
47891 #define HWRM_NVM_FLUSH_CMD_ERR_CODE_UNKNOWN UINT32_C(0x0)
47892 /* flush could not be performed */
47893 #define HWRM_NVM_FLUSH_CMD_ERR_CODE_FAIL UINT32_C(0x1)
47894 #define HWRM_NVM_FLUSH_CMD_ERR_CODE_LAST \
47895 HWRM_NVM_FLUSH_CMD_ERR_CODE_FAIL
47896 uint8_t unused_0[7];
47899 /*************************
47900 * hwrm_nvm_get_variable *
47901 *************************/
47904 /* hwrm_nvm_get_variable_input (size:320b/40B) */
47905 struct hwrm_nvm_get_variable_input {
47906 /* The HWRM command request type. */
47909 * The completion ring to send the completion event on. This should
47910 * be the NQ ID returned from the `nq_alloc` HWRM command.
47912 uint16_t cmpl_ring;
47914 * The sequence ID is used by the driver for tracking multiple
47915 * commands. This ID is treated as opaque data by the firmware and
47916 * the value is returned in the `hwrm_resp_hdr` upon completion.
47920 * The target ID of the command:
47921 * * 0x0-0xFFF8 - The function ID
47922 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
47923 * * 0xFFFD - Reserved for user-space HWRM interface
47926 uint16_t target_id;
47928 * A physical address pointer pointing to a host buffer that the
47929 * command's response data will be written. This can be either a host
47930 * physical address (HPA) or a guest physical address (GPA) and must
47931 * point to a physically contiguous block of memory.
47933 uint64_t resp_addr;
47935 * This is the host address where
47936 * nvm variable will be stored
47938 uint64_t dest_data_addr;
47939 /* size of data in bits */
47941 /* nvm cfg option number */
47942 uint16_t option_num;
47944 #define HWRM_NVM_GET_VARIABLE_INPUT_OPTION_NUM_RSVD_0 UINT32_C(0x0)
47946 #define HWRM_NVM_GET_VARIABLE_INPUT_OPTION_NUM_RSVD_FFFF \
47948 #define HWRM_NVM_GET_VARIABLE_INPUT_OPTION_NUM_LAST \
47949 HWRM_NVM_GET_VARIABLE_INPUT_OPTION_NUM_RSVD_FFFF
47951 * Number of dimensions for this nvm configuration variable.
47952 * This value indicates how many of the indexN values to use.
47953 * A value of 0 means that none of the indexN values are valid.
47954 * A value of 1 requires at index0 is valued, a value of 2
47955 * requires that index0 and index1 are valid, and so forth
47957 uint16_t dimensions;
47958 /* index for the 1st dimensions */
47960 /* index for the 2nd dimensions */
47962 /* index for the 3rd dimensions */
47964 /* index for the 4th dimensions */
47968 * When this bit is set to 1, the factory default value will be returned,
47969 * 0 returns the operational value.
47971 #define HWRM_NVM_GET_VARIABLE_INPUT_FLAGS_FACTORY_DFLT \
47976 /* hwrm_nvm_get_variable_output (size:128b/16B) */
47977 struct hwrm_nvm_get_variable_output {
47978 /* The specific error status for the command. */
47979 uint16_t error_code;
47980 /* The HWRM command request type. */
47982 /* The sequence ID from the original command. */
47984 /* The length of the response data in number of bytes. */
47986 /* size of data of the actual variable retrieved in bits */
47989 * option_num is the option number for the data retrieved. It is possible in the
47990 * future that the option number returned would be different than requested. This
47991 * condition could occur if an option is deprecated and a new option id is defined
47992 * with similar characteristics, but has a slightly different definition. This
47993 * also makes it convenient for the caller to identify the variable result with
47994 * the option id from the response.
47996 uint16_t option_num;
47998 #define HWRM_NVM_GET_VARIABLE_OUTPUT_OPTION_NUM_RSVD_0 UINT32_C(0x0)
48000 #define HWRM_NVM_GET_VARIABLE_OUTPUT_OPTION_NUM_RSVD_FFFF \
48002 #define HWRM_NVM_GET_VARIABLE_OUTPUT_OPTION_NUM_LAST \
48003 HWRM_NVM_GET_VARIABLE_OUTPUT_OPTION_NUM_RSVD_FFFF
48004 uint8_t unused_0[3];
48006 * This field is used in Output records to indicate that the output
48007 * is completely written to RAM. This field should be read as '1'
48008 * to indicate that the output has been completely written.
48009 * When writing a command completion or response to an internal processor,
48010 * the order of writes has to be such that this field is written last.
48015 /* hwrm_nvm_get_variable_cmd_err (size:64b/8B) */
48016 struct hwrm_nvm_get_variable_cmd_err {
48018 * command specific error codes that goes to
48019 * the cmd_err field in Common HWRM Error Response.
48022 /* Unknown error */
48023 #define HWRM_NVM_GET_VARIABLE_CMD_ERR_CODE_UNKNOWN UINT32_C(0x0)
48024 /* variable does not exist */
48025 #define HWRM_NVM_GET_VARIABLE_CMD_ERR_CODE_VAR_NOT_EXIST UINT32_C(0x1)
48026 /* configuration is corrupted and the variable cannot be saved */
48027 #define HWRM_NVM_GET_VARIABLE_CMD_ERR_CODE_CORRUPT_VAR UINT32_C(0x2)
48028 /* length specified is too small */
48029 #define HWRM_NVM_GET_VARIABLE_CMD_ERR_CODE_LEN_TOO_SHORT UINT32_C(0x3)
48030 #define HWRM_NVM_GET_VARIABLE_CMD_ERR_CODE_LAST \
48031 HWRM_NVM_GET_VARIABLE_CMD_ERR_CODE_LEN_TOO_SHORT
48032 uint8_t unused_0[7];
48035 /*************************
48036 * hwrm_nvm_set_variable *
48037 *************************/
48040 /* hwrm_nvm_set_variable_input (size:320b/40B) */
48041 struct hwrm_nvm_set_variable_input {
48042 /* The HWRM command request type. */
48045 * The completion ring to send the completion event on. This should
48046 * be the NQ ID returned from the `nq_alloc` HWRM command.
48048 uint16_t cmpl_ring;
48050 * The sequence ID is used by the driver for tracking multiple
48051 * commands. This ID is treated as opaque data by the firmware and
48052 * the value is returned in the `hwrm_resp_hdr` upon completion.
48056 * The target ID of the command:
48057 * * 0x0-0xFFF8 - The function ID
48058 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
48059 * * 0xFFFD - Reserved for user-space HWRM interface
48062 uint16_t target_id;
48064 * A physical address pointer pointing to a host buffer that the
48065 * command's response data will be written. This can be either a host
48066 * physical address (HPA) or a guest physical address (GPA) and must
48067 * point to a physically contiguous block of memory.
48069 uint64_t resp_addr;
48071 * This is the host address where
48072 * nvm variable will be copied from
48074 uint64_t src_data_addr;
48075 /* size of data in bits */
48077 /* nvm cfg option number */
48078 uint16_t option_num;
48080 #define HWRM_NVM_SET_VARIABLE_INPUT_OPTION_NUM_RSVD_0 UINT32_C(0x0)
48082 #define HWRM_NVM_SET_VARIABLE_INPUT_OPTION_NUM_RSVD_FFFF \
48084 #define HWRM_NVM_SET_VARIABLE_INPUT_OPTION_NUM_LAST \
48085 HWRM_NVM_SET_VARIABLE_INPUT_OPTION_NUM_RSVD_FFFF
48087 * Number of dimensions for this nvm configuration variable.
48088 * This value indicates how many of the indexN values to use.
48089 * A value of 0 means that none of the indexN values are valid.
48090 * A value of 1 requires at index0 is valued, a value of 2
48091 * requires that index0 and index1 are valid, and so forth
48093 uint16_t dimensions;
48094 /* index for the 1st dimensions */
48096 /* index for the 2nd dimensions */
48098 /* index for the 3rd dimensions */
48100 /* index for the 4th dimensions */
48104 * When this bit is 1, flush internal cache after this write operation
48105 * (see hwrm_nvm_flush command.)
48107 #define HWRM_NVM_SET_VARIABLE_INPUT_FLAGS_FORCE_FLUSH \
48109 /* encryption method */
48110 #define HWRM_NVM_SET_VARIABLE_INPUT_FLAGS_ENCRYPT_MODE_MASK \
48112 #define HWRM_NVM_SET_VARIABLE_INPUT_FLAGS_ENCRYPT_MODE_SFT 1
48113 /* No encryption. */
48114 #define HWRM_NVM_SET_VARIABLE_INPUT_FLAGS_ENCRYPT_MODE_NONE \
48115 (UINT32_C(0x0) << 1)
48116 /* one-way encryption. */
48117 #define HWRM_NVM_SET_VARIABLE_INPUT_FLAGS_ENCRYPT_MODE_HMAC_SHA1 \
48118 (UINT32_C(0x1) << 1)
48119 /* symmetric AES256 encryption. */
48120 #define HWRM_NVM_SET_VARIABLE_INPUT_FLAGS_ENCRYPT_MODE_AES256 \
48121 (UINT32_C(0x2) << 1)
48122 /* SHA1 digest appended to plaintext contents, for authentication */
48123 #define HWRM_NVM_SET_VARIABLE_INPUT_FLAGS_ENCRYPT_MODE_HMAC_SHA1_AUTH \
48124 (UINT32_C(0x3) << 1)
48125 #define HWRM_NVM_SET_VARIABLE_INPUT_FLAGS_ENCRYPT_MODE_LAST \
48126 HWRM_NVM_SET_VARIABLE_INPUT_FLAGS_ENCRYPT_MODE_HMAC_SHA1_AUTH
48127 #define HWRM_NVM_SET_VARIABLE_INPUT_FLAGS_FLAGS_UNUSED_0_MASK \
48129 #define HWRM_NVM_SET_VARIABLE_INPUT_FLAGS_FLAGS_UNUSED_0_SFT 4
48130 /* When this bit is 1, update the factory default region */
48131 #define HWRM_NVM_SET_VARIABLE_INPUT_FLAGS_FACTORY_DEFAULT \
48136 /* hwrm_nvm_set_variable_output (size:128b/16B) */
48137 struct hwrm_nvm_set_variable_output {
48138 /* The specific error status for the command. */
48139 uint16_t error_code;
48140 /* The HWRM command request type. */
48142 /* The sequence ID from the original command. */
48144 /* The length of the response data in number of bytes. */
48146 uint8_t unused_0[7];
48148 * This field is used in Output records to indicate that the output
48149 * is completely written to RAM. This field should be read as '1'
48150 * to indicate that the output has been completely written.
48151 * When writing a command completion or response to an internal processor,
48152 * the order of writes has to be such that this field is written last.
48157 /* hwrm_nvm_set_variable_cmd_err (size:64b/8B) */
48158 struct hwrm_nvm_set_variable_cmd_err {
48160 * command specific error codes that goes to
48161 * the cmd_err field in Common HWRM Error Response.
48164 /* Unknown error */
48165 #define HWRM_NVM_SET_VARIABLE_CMD_ERR_CODE_UNKNOWN UINT32_C(0x0)
48166 /* variable does not exist */
48167 #define HWRM_NVM_SET_VARIABLE_CMD_ERR_CODE_VAR_NOT_EXIST UINT32_C(0x1)
48168 /* configuration is corrupted and the variable cannot be saved */
48169 #define HWRM_NVM_SET_VARIABLE_CMD_ERR_CODE_CORRUPT_VAR UINT32_C(0x2)
48170 #define HWRM_NVM_SET_VARIABLE_CMD_ERR_CODE_LAST \
48171 HWRM_NVM_SET_VARIABLE_CMD_ERR_CODE_CORRUPT_VAR
48172 uint8_t unused_0[7];
48175 /****************************
48176 * hwrm_nvm_validate_option *
48177 ****************************/
48180 /* hwrm_nvm_validate_option_input (size:320b/40B) */
48181 struct hwrm_nvm_validate_option_input {
48182 /* The HWRM command request type. */
48185 * The completion ring to send the completion event on. This should
48186 * be the NQ ID returned from the `nq_alloc` HWRM command.
48188 uint16_t cmpl_ring;
48190 * The sequence ID is used by the driver for tracking multiple
48191 * commands. This ID is treated as opaque data by the firmware and
48192 * the value is returned in the `hwrm_resp_hdr` upon completion.
48196 * The target ID of the command:
48197 * * 0x0-0xFFF8 - The function ID
48198 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
48199 * * 0xFFFD - Reserved for user-space HWRM interface
48202 uint16_t target_id;
48204 * A physical address pointer pointing to a host buffer that the
48205 * command's response data will be written. This can be either a host
48206 * physical address (HPA) or a guest physical address (GPA) and must
48207 * point to a physically contiguous block of memory.
48209 uint64_t resp_addr;
48211 * This is the host address where
48212 * nvm variable will be copied from
48214 uint64_t src_data_addr;
48215 /* size of data in bits */
48217 /* nvm cfg option number */
48218 uint16_t option_num;
48220 #define HWRM_NVM_VALIDATE_OPTION_INPUT_OPTION_NUM_RSVD_0 \
48223 #define HWRM_NVM_VALIDATE_OPTION_INPUT_OPTION_NUM_RSVD_FFFF \
48225 #define HWRM_NVM_VALIDATE_OPTION_INPUT_OPTION_NUM_LAST \
48226 HWRM_NVM_VALIDATE_OPTION_INPUT_OPTION_NUM_RSVD_FFFF
48228 * Number of dimensions for this nvm configuration variable.
48229 * This value indicates how many of the indexN values to use.
48230 * A value of 0 means that none of the indexN values are valid.
48231 * A value of 1 requires at index0 is valued, a value of 2
48232 * requires that index0 and index1 are valid, and so forth
48234 uint16_t dimensions;
48235 /* index for the 1st dimensions */
48237 /* index for the 2nd dimensions */
48239 /* index for the 3rd dimensions */
48241 /* index for the 4th dimensions */
48243 uint8_t unused_0[2];
48246 /* hwrm_nvm_validate_option_output (size:128b/16B) */
48247 struct hwrm_nvm_validate_option_output {
48248 /* The specific error status for the command. */
48249 uint16_t error_code;
48250 /* The HWRM command request type. */
48252 /* The sequence ID from the original command. */
48254 /* The length of the response data in number of bytes. */
48257 /* indicates that the value provided for the option is not matching with the saved data. */
48258 #define HWRM_NVM_VALIDATE_OPTION_OUTPUT_RESULT_NOT_MATCH UINT32_C(0x0)
48259 /* indicates that the value provided for the option is matching the saved data. */
48260 #define HWRM_NVM_VALIDATE_OPTION_OUTPUT_RESULT_MATCH UINT32_C(0x1)
48261 #define HWRM_NVM_VALIDATE_OPTION_OUTPUT_RESULT_LAST \
48262 HWRM_NVM_VALIDATE_OPTION_OUTPUT_RESULT_MATCH
48263 uint8_t unused_0[6];
48265 * This field is used in Output records to indicate that the output
48266 * is completely written to RAM. This field should be read as '1'
48267 * to indicate that the output has been completely written.
48268 * When writing a command completion or response to an internal processor,
48269 * the order of writes has to be such that this field is written last.
48274 /* hwrm_nvm_validate_option_cmd_err (size:64b/8B) */
48275 struct hwrm_nvm_validate_option_cmd_err {
48277 * command specific error codes that goes to
48278 * the cmd_err field in Common HWRM Error Response.
48281 /* Unknown error */
48282 #define HWRM_NVM_VALIDATE_OPTION_CMD_ERR_CODE_UNKNOWN UINT32_C(0x0)
48283 #define HWRM_NVM_VALIDATE_OPTION_CMD_ERR_CODE_LAST \
48284 HWRM_NVM_VALIDATE_OPTION_CMD_ERR_CODE_UNKNOWN
48285 uint8_t unused_0[7];
48293 /* hwrm_oem_cmd_input (size:1024b/128B) */
48294 struct hwrm_oem_cmd_input {
48295 /* The HWRM command request type. */
48298 * The completion ring to send the completion event on. This should
48299 * be the NQ ID returned from the `nq_alloc` HWRM command.
48301 uint16_t cmpl_ring;
48303 * The sequence ID is used by the driver for tracking multiple
48304 * commands. This ID is treated as opaque data by the firmware and
48305 * the value is returned in the `hwrm_resp_hdr` upon completion.
48309 * The target ID of the command:
48310 * * 0x0-0xFFF8 - The function ID
48311 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
48312 * * 0xFFFD - Reserved for user-space HWRM interface
48315 uint16_t target_id;
48317 * A physical address pointer pointing to a host buffer that the
48318 * command's response data will be written. This can be either a host
48319 * physical address (HPA) or a guest physical address (GPA) and must
48320 * point to a physically contiguous block of memory.
48322 uint64_t resp_addr;
48325 /* This field contains the vendor specific command data. */
48326 uint32_t oem_data[26];
48329 /* hwrm_oem_cmd_output (size:768b/96B) */
48330 struct hwrm_oem_cmd_output {
48331 /* The specific error status for the command. */
48332 uint16_t error_code;
48333 /* The HWRM command request type. */
48335 /* The sequence ID from the original command. */
48337 /* The length of the response data in number of bytes. */
48341 /* This field contains the vendor specific response data. */
48342 uint32_t oem_data[18];
48343 uint8_t unused_1[7];
48345 * This field is used in Output records to indicate that the output
48346 * is completely written to RAM. This field should be read as '1'
48347 * to indicate that the output has been completely written.
48348 * When writing a command completion or response to an internal processor,
48349 * the order of writes has to be such that this field is written last.
48356 ******************/
48359 /* hwrm_fw_reset_input (size:192b/24B) */
48360 struct hwrm_fw_reset_input {
48361 /* The HWRM command request type. */
48364 * The completion ring to send the completion event on. This should
48365 * be the NQ ID returned from the `nq_alloc` HWRM command.
48367 uint16_t cmpl_ring;
48369 * The sequence ID is used by the driver for tracking multiple
48370 * commands. This ID is treated as opaque data by the firmware and
48371 * the value is returned in the `hwrm_resp_hdr` upon completion.
48375 * The target ID of the command:
48376 * * 0x0-0xFFF8 - The function ID
48377 * * 0xFFF8-0xFFFE - Reserved for internal processors
48380 uint16_t target_id;
48382 * A physical address pointer pointing to a host buffer that the
48383 * command's response data will be written. This can be either a host
48384 * physical address (HPA) or a guest physical address (GPA) and must
48385 * point to a physically contiguous block of memory.
48387 uint64_t resp_addr;
48388 /* Type of embedded processor. */
48389 uint8_t embedded_proc_type;
48390 /* Boot Processor */
48391 #define HWRM_FW_RESET_INPUT_EMBEDDED_PROC_TYPE_BOOT \
48393 /* Management Processor */
48394 #define HWRM_FW_RESET_INPUT_EMBEDDED_PROC_TYPE_MGMT \
48396 /* Network control processor */
48397 #define HWRM_FW_RESET_INPUT_EMBEDDED_PROC_TYPE_NETCTRL \
48399 /* RoCE control processor */
48400 #define HWRM_FW_RESET_INPUT_EMBEDDED_PROC_TYPE_ROCE \
48403 * Host (in multi-host environment): This is only valid if requester is IPC.
48404 * Reinit host hardware resources and PCIe.
48406 #define HWRM_FW_RESET_INPUT_EMBEDDED_PROC_TYPE_HOST \
48409 * AP processor complex (in multi-host environment). Use host_idx to
48410 * control which core is reset
48412 #define HWRM_FW_RESET_INPUT_EMBEDDED_PROC_TYPE_AP \
48414 /* Reset all blocks of the chip (including all processors) */
48415 #define HWRM_FW_RESET_INPUT_EMBEDDED_PROC_TYPE_CHIP \
48418 * Host (in multi-host environment): This is only valid if requester is IPC.
48419 * Reinit host hardware resources.
48421 #define HWRM_FW_RESET_INPUT_EMBEDDED_PROC_TYPE_HOST_RESOURCE_REINIT \
48423 #define HWRM_FW_RESET_INPUT_EMBEDDED_PROC_TYPE_LAST \
48424 HWRM_FW_RESET_INPUT_EMBEDDED_PROC_TYPE_HOST_RESOURCE_REINIT
48425 /* Type of self reset. */
48426 uint8_t selfrst_status;
48427 /* No Self Reset */
48428 #define HWRM_FW_RESET_INPUT_SELFRST_STATUS_SELFRSTNONE \
48430 /* Self Reset as soon as possible to do so safely */
48431 #define HWRM_FW_RESET_INPUT_SELFRST_STATUS_SELFRSTASAP \
48433 /* Self Reset on PCIe Reset */
48434 #define HWRM_FW_RESET_INPUT_SELFRST_STATUS_SELFRSTPCIERST \
48436 /* Self Reset immediately after notification to all clients. */
48437 #define HWRM_FW_RESET_INPUT_SELFRST_STATUS_SELFRSTIMMEDIATE \
48439 #define HWRM_FW_RESET_INPUT_SELFRST_STATUS_LAST \
48440 HWRM_FW_RESET_INPUT_SELFRST_STATUS_SELFRSTIMMEDIATE
48442 * Indicate which host is being reset. 0 means first host.
48443 * Only valid when embedded_proc_type is host in multihost
48449 * When this bit is '1', then the core firmware initiates
48450 * the reset only after graceful shut down of all registered instances.
48451 * If not, the device will continue with the existing firmware.
48453 #define HWRM_FW_RESET_INPUT_FLAGS_RESET_GRACEFUL UINT32_C(0x1)
48454 uint8_t unused_0[4];
48457 /* hwrm_fw_reset_output (size:128b/16B) */
48458 struct hwrm_fw_reset_output {
48459 /* The specific error status for the command. */
48460 uint16_t error_code;
48461 /* The HWRM command request type. */
48463 /* The sequence ID from the original command. */
48465 /* The length of the response data in number of bytes. */
48467 /* Type of self reset. */
48468 uint8_t selfrst_status;
48469 /* No Self Reset */
48470 #define HWRM_FW_RESET_OUTPUT_SELFRST_STATUS_SELFRSTNONE \
48472 /* Self Reset as soon as possible to do so safely */
48473 #define HWRM_FW_RESET_OUTPUT_SELFRST_STATUS_SELFRSTASAP \
48475 /* Self Reset on PCIe Reset */
48476 #define HWRM_FW_RESET_OUTPUT_SELFRST_STATUS_SELFRSTPCIERST \
48478 /* Self Reset immediately after notification to all clients. */
48479 #define HWRM_FW_RESET_OUTPUT_SELFRST_STATUS_SELFRSTIMMEDIATE \
48481 #define HWRM_FW_RESET_OUTPUT_SELFRST_STATUS_LAST \
48482 HWRM_FW_RESET_OUTPUT_SELFRST_STATUS_SELFRSTIMMEDIATE
48483 uint8_t unused_0[6];
48485 * This field is used in Output records to indicate that the output
48486 * is completely written to RAM. This field should be read as '1'
48487 * to indicate that the output has been completely written.
48488 * When writing a command completion or response to an internal processor,
48489 * the order of writes has to be such that this field is written last.
48494 /**********************
48495 * hwrm_port_ts_query *
48496 ***********************/
48499 /* hwrm_port_ts_query_input (size:192b/24B) */
48500 struct hwrm_port_ts_query_input {
48501 /* The HWRM command request type. */
48504 * The completion ring to send the completion event on. This should
48505 * be the NQ ID returned from the `nq_alloc` HWRM command.
48507 uint16_t cmpl_ring;
48509 * The sequence ID is used by the driver for tracking multiple
48510 * commands. This ID is treated as opaque data by the firmware and
48511 * the value is returned in the `hwrm_resp_hdr` upon completion.
48515 * The target ID of the command:
48516 * * 0x0-0xFFF8 - The function ID
48517 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
48518 * * 0xFFFD - Reserved for user-space HWRM interface
48521 uint16_t target_id;
48523 * A physical address pointer pointing to a host buffer that the
48524 * command's response data will be written. This can be either a host
48525 * physical address (HPA) or a guest physical address (GPA) and must
48526 * point to a physically contiguous block of memory.
48528 uint64_t resp_addr;
48531 * Enumeration denoting the RX, TX type of the resource.
48532 * This enumeration is used for resources that are similar for both
48533 * TX and RX paths of the chip.
48535 #define HWRM_PORT_TS_QUERY_INPUT_FLAGS_PATH 0x1UL
48537 #define HWRM_PORT_TS_QUERY_INPUT_FLAGS_PATH_TX 0x0UL
48539 #define HWRM_PORT_TS_QUERY_INPUT_FLAGS_PATH_RX 0x1UL
48540 #define HWRM_PORT_TS_QUERY_INPUT_FLAGS_PATH_LAST \
48541 HWRM_PORT_TS_QUERY_INPUT_FLAGS_PATH_RX
48543 * If set, the response includes the current value of the free
48546 #define HWRM_PORT_TS_QUERY_INPUT_FLAGS_CURRENT_TIME 0x2UL
48547 /* Port ID of port that is being queried. */
48549 uint8_t unused_0[2];
48552 /* hwrm_port_ts_query_output (size:192b/24B) */
48553 struct hwrm_port_ts_query_output {
48554 /* The specific error status for the command. */
48555 uint16_t error_code;
48556 /* The HWRM command request type. */
48558 /* The sequence ID from the original command. */
48560 /* The length of the response data in number of bytes. */
48563 * Timestamp value of PTP message captured, or current value of
48564 * free running timer.
48566 uint32_t ptp_msg_ts[2];
48567 /* Sequence ID of the PTP message captured. */
48568 uint16_t ptp_msg_seqid;
48569 uint8_t unused_0[5];
48571 * This field is used in Output records to indicate that the output
48572 * is completely written to RAM. This field should be read as '1'
48573 * to indicate that the output has been completely written.
48574 * When writing a command completion or response to an internal processor,
48575 * the order of writes has to be such that this field is written last.
48581 * This structure is fixed at the beginning of the ChiMP SRAM (GRC
48582 * offset: 0x31001F0). Host software is expected to read from this
48583 * location for a defined signature. If it exists, the software can
48584 * assume the presence of this structure and the validity of the
48585 * FW_STATUS location in the next field.
48587 /* hcomm_status (size:64b/8B) */
48588 struct hcomm_status {
48591 * This field defines the version of the structure. The latest
48592 * version value is 1.
48594 #define HCOMM_STATUS_VER_MASK UINT32_C(0xff)
48595 #define HCOMM_STATUS_VER_SFT 0
48596 #define HCOMM_STATUS_VER_LATEST UINT32_C(0x1)
48597 #define HCOMM_STATUS_VER_LAST HCOMM_STATUS_VER_LATEST
48599 * This field is to store the signature value to indicate the
48600 * presence of the structure.
48602 #define HCOMM_STATUS_SIGNATURE_MASK UINT32_C(0xffffff00)
48603 #define HCOMM_STATUS_SIGNATURE_SFT 8
48604 #define HCOMM_STATUS_SIGNATURE_VAL (UINT32_C(0x484353) << 8)
48605 #define HCOMM_STATUS_SIGNATURE_LAST HCOMM_STATUS_SIGNATURE_VAL
48606 uint32_t fw_status_loc;
48607 #define HCOMM_STATUS_TRUE_ADDR_SPACE_MASK UINT32_C(0x3)
48608 #define HCOMM_STATUS_TRUE_ADDR_SPACE_SFT 0
48609 /* PCIE configuration space */
48610 #define HCOMM_STATUS_FW_STATUS_LOC_ADDR_SPACE_PCIE_CFG UINT32_C(0x0)
48612 #define HCOMM_STATUS_FW_STATUS_LOC_ADDR_SPACE_GRC UINT32_C(0x1)
48614 #define HCOMM_STATUS_FW_STATUS_LOC_ADDR_SPACE_BAR0 UINT32_C(0x2)
48616 #define HCOMM_STATUS_FW_STATUS_LOC_ADDR_SPACE_BAR1 UINT32_C(0x3)
48617 #define HCOMM_STATUS_FW_STATUS_LOC_ADDR_SPACE_LAST \
48618 HCOMM_STATUS_FW_STATUS_LOC_ADDR_SPACE_BAR1
48620 * This offset where the fw_status register is located. The value
48621 * is generally 4-byte aligned.
48623 #define HCOMM_STATUS_TRUE_OFFSET_MASK UINT32_C(0xfffffffc)
48624 #define HCOMM_STATUS_TRUE_OFFSET_SFT 2
48626 /* This is the GRC offset where the hcomm_status struct resides. */
48627 #define HCOMM_STATUS_STRUCT_LOC 0x31001F0UL
48628 #endif /* _HSI_STRUCT_DEF_DPDK_H_ */